24973 lines
906 KiB
Plaintext
24973 lines
906 KiB
Plaintext
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modularkbd.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000001c4 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00009440 080001c4 080001c4 000011c4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000054 08009604 08009604 0000a604 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08009658 08009658 0000b138 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 08009658 08009658 0000a658 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 08009660 08009660 0000b138 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08009660 08009660 0000a660 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 08009664 08009664 0000a664 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 00000138 20000000 08009668 0000b000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000d54 20000138 080097a0 0000b138 2**2
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ALLOC
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10 ._user_heap_stack 00000604 20000e8c 080097a0 0000be8c 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0000b138 2**0
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CONTENTS, READONLY
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12 .debug_info 00019733 00000000 00000000 0000b168 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00003874 00000000 00000000 0002489b 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 000016a8 00000000 00000000 00028110 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 000011b4 00000000 00000000 000297b8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00025576 00000000 00000000 0002a96c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 0001c096 00000000 00000000 0004fee2 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000d7cec 00000000 00000000 0006bf78 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 00143c64 2**0
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CONTENTS, READONLY
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20 .debug_frame 000060f0 00000000 00000000 00143ca8 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000062 00000000 00000000 00149d98 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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080001c4 <__do_global_dtors_aux>:
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80001c4: b510 push {r4, lr}
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80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>)
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80001c8: 7823 ldrb r3, [r4, #0]
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80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16>
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80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>)
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80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12>
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80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>)
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80001d2: f3af 8000 nop.w
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80001d6: 2301 movs r3, #1
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80001d8: 7023 strb r3, [r4, #0]
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80001da: bd10 pop {r4, pc}
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80001dc: 20000138 .word 0x20000138
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80001e0: 00000000 .word 0x00000000
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80001e4: 080095ec .word 0x080095ec
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080001e8 <frame_dummy>:
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80001e8: b508 push {r3, lr}
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80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 <frame_dummy+0x10>)
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80001ec: b11b cbz r3, 80001f6 <frame_dummy+0xe>
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80001ee: 4903 ldr r1, [pc, #12] @ (80001fc <frame_dummy+0x14>)
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80001f0: 4803 ldr r0, [pc, #12] @ (8000200 <frame_dummy+0x18>)
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80001f2: f3af 8000 nop.w
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80001f6: bd08 pop {r3, pc}
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80001f8: 00000000 .word 0x00000000
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80001fc: 2000013c .word 0x2000013c
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8000200: 080095ec .word 0x080095ec
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08000204 <__aeabi_uldivmod>:
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8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18>
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8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18>
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8000208: 2900 cmp r1, #0
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800020a: bf08 it eq
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800020c: 2800 cmpeq r0, #0
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800020e: bf1c itt ne
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8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
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8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
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8000218: f000 b988 b.w 800052c <__aeabi_idiv0>
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800021c: f1ad 0c08 sub.w ip, sp, #8
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8000220: e96d ce04 strd ip, lr, [sp, #-16]!
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8000224: f000 f806 bl 8000234 <__udivmoddi4>
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8000228: f8dd e004 ldr.w lr, [sp, #4]
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800022c: e9dd 2302 ldrd r2, r3, [sp, #8]
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8000230: b004 add sp, #16
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8000232: 4770 bx lr
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08000234 <__udivmoddi4>:
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8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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8000238: 9d08 ldr r5, [sp, #32]
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800023a: 468e mov lr, r1
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800023c: 4604 mov r4, r0
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800023e: 4688 mov r8, r1
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8000240: 2b00 cmp r3, #0
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8000242: d14a bne.n 80002da <__udivmoddi4+0xa6>
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8000244: 428a cmp r2, r1
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8000246: 4617 mov r7, r2
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8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc>
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800024a: fab2 f682 clz r6, r2
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800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30>
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8000250: f1c6 0320 rsb r3, r6, #32
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8000254: fa01 f806 lsl.w r8, r1, r6
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8000258: fa20 f303 lsr.w r3, r0, r3
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800025c: 40b7 lsls r7, r6
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800025e: ea43 0808 orr.w r8, r3, r8
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8000262: 40b4 lsls r4, r6
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8000264: ea4f 4e17 mov.w lr, r7, lsr #16
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8000268: fa1f fc87 uxth.w ip, r7
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800026c: fbb8 f1fe udiv r1, r8, lr
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8000270: 0c23 lsrs r3, r4, #16
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8000272: fb0e 8811 mls r8, lr, r1, r8
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8000276: ea43 4308 orr.w r3, r3, r8, lsl #16
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800027a: fb01 f20c mul.w r2, r1, ip
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800027e: 429a cmp r2, r3
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8000280: d909 bls.n 8000296 <__udivmoddi4+0x62>
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8000282: 18fb adds r3, r7, r3
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8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
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8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c>
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800028c: 429a cmp r2, r3
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800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c>
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8000292: 3902 subs r1, #2
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8000294: 443b add r3, r7
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8000296: 1a9a subs r2, r3, r2
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8000298: b2a3 uxth r3, r4
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800029a: fbb2 f0fe udiv r0, r2, lr
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800029e: fb0e 2210 mls r2, lr, r0, r2
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80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16
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80002a6: fb00 fc0c mul.w ip, r0, ip
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80002aa: 459c cmp ip, r3
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80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e>
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80002ae: 18fb adds r3, r7, r3
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80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
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80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230>
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80002b8: 459c cmp ip, r3
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80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230>
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80002be: 443b add r3, r7
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80002c0: 3802 subs r0, #2
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80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16
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80002c6: eba3 030c sub.w r3, r3, ip
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80002ca: 2100 movs r1, #0
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80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2>
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80002ce: 40f3 lsrs r3, r6
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80002d0: 2200 movs r2, #0
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80002d2: e9c5 3200 strd r3, r2, [r5]
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80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002da: 428b cmp r3, r1
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80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6>
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80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0>
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80002e0: e9c5 0100 strd r0, r1, [r5]
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80002e4: 2100 movs r1, #0
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80002e6: 4608 mov r0, r1
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80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2>
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80002ea: fab3 f183 clz r1, r3
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80002ee: 2900 cmp r1, #0
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80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c>
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80002f2: 4573 cmp r3, lr
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80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8>
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80002f6: 4282 cmp r2, r0
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80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2>
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80002fc: 1a84 subs r4, r0, r2
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80002fe: eb6e 0203 sbc.w r2, lr, r3
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8000302: 2001 movs r0, #1
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8000304: 4690 mov r8, r2
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8000306: 2d00 cmp r5, #0
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8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2>
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800030a: e9c5 4800 strd r4, r8, [r5]
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800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2>
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8000310: 2a00 cmp r2, #0
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8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202>
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8000316: fab2 f682 clz r6, r2
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800031a: 2e00 cmp r6, #0
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800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234>
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8000320: 1a8a subs r2, r1, r2
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8000322: 0c03 lsrs r3, r0, #16
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8000324: ea4f 4e17 mov.w lr, r7, lsr #16
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8000328: b280 uxth r0, r0
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800032a: b2bc uxth r4, r7
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800032c: 2101 movs r1, #1
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800032e: fbb2 fcfe udiv ip, r2, lr
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8000332: fb0e 221c mls r2, lr, ip, r2
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8000336: ea43 4302 orr.w r3, r3, r2, lsl #16
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800033a: fb04 f20c mul.w r2, r4, ip
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800033e: 429a cmp r2, r3
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8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e>
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8000342: 18fb adds r3, r7, r3
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8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
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8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c>
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800034a: 429a cmp r2, r3
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800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc>
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8000350: 46c4 mov ip, r8
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8000352: 1a9b subs r3, r3, r2
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8000354: fbb3 f2fe udiv r2, r3, lr
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8000358: fb0e 3312 mls r3, lr, r2, r3
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800035c: ea40 4303 orr.w r3, r0, r3, lsl #16
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8000360: fb02 f404 mul.w r4, r2, r4
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8000364: 429c cmp r4, r3
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8000366: d907 bls.n 8000378 <__udivmoddi4+0x144>
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8000368: 18fb adds r3, r7, r3
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800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
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800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142>
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8000370: 429c cmp r4, r3
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8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6>
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8000376: 4602 mov r2, r0
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8000378: 1b1b subs r3, r3, r4
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800037a: ea42 400c orr.w r0, r2, ip, lsl #16
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800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98>
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8000380: f1c1 0620 rsb r6, r1, #32
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8000384: 408b lsls r3, r1
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8000386: fa22 f706 lsr.w r7, r2, r6
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800038a: 431f orrs r7, r3
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800038c: fa0e f401 lsl.w r4, lr, r1
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8000390: fa20 f306 lsr.w r3, r0, r6
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8000394: fa2e fe06 lsr.w lr, lr, r6
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8000398: ea4f 4917 mov.w r9, r7, lsr #16
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800039c: 4323 orrs r3, r4
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800039e: fa00 f801 lsl.w r8, r0, r1
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80003a2: fa1f fc87 uxth.w ip, r7
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80003a6: fbbe f0f9 udiv r0, lr, r9
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80003aa: 0c1c lsrs r4, r3, #16
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80003ac: fb09 ee10 mls lr, r9, r0, lr
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80003b0: ea44 440e orr.w r4, r4, lr, lsl #16
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80003b4: fb00 fe0c mul.w lr, r0, ip
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80003b8: 45a6 cmp lr, r4
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80003ba: fa02 f201 lsl.w r2, r2, r1
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80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0>
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80003c0: 193c adds r4, r7, r4
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80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
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80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce>
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80003ca: 45a6 cmp lr, r4
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80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce>
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80003d0: 3802 subs r0, #2
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80003d2: 443c add r4, r7
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80003d4: eba4 040e sub.w r4, r4, lr
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80003d8: fa1f fe83 uxth.w lr, r3
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80003dc: fbb4 f3f9 udiv r3, r4, r9
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80003e0: fb09 4413 mls r4, r9, r3, r4
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80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16
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80003e8: fb03 fc0c mul.w ip, r3, ip
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80003ec: 45a4 cmp ip, r4
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80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce>
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80003f0: 193c adds r4, r7, r4
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80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
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80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca>
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80003fa: 45a4 cmp ip, r4
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80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca>
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80003fe: 3b02 subs r3, #2
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8000400: 443c add r4, r7
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8000402: ea43 4000 orr.w r0, r3, r0, lsl #16
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8000406: eba4 040c sub.w r4, r4, ip
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800040a: fba0 ec02 umull lr, ip, r0, r2
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800040e: 4564 cmp r4, ip
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8000410: 4673 mov r3, lr
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8000412: 46e1 mov r9, ip
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8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8>
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8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4>
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8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe>
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800041a: ebb8 0203 subs.w r2, r8, r3
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800041e: eb64 0409 sbc.w r4, r4, r9
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8000422: fa04 f606 lsl.w r6, r4, r6
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8000426: fa22 f301 lsr.w r3, r2, r1
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800042a: 431e orrs r6, r3
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800042c: 40cc lsrs r4, r1
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800042e: e9c5 6400 strd r6, r4, [r5]
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8000432: 2100 movs r1, #0
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8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2>
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8000436: fbb1 fcf2 udiv ip, r1, r2
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800043a: 0c01 lsrs r1, r0, #16
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800043c: ea41 410e orr.w r1, r1, lr, lsl #16
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8000440: b280 uxth r0, r0
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8000442: ea40 4201 orr.w r2, r0, r1, lsl #16
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8000446: 463b mov r3, r7
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8000448: 4638 mov r0, r7
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800044a: 463c mov r4, r7
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800044c: 46b8 mov r8, r7
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800044e: 46be mov lr, r7
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8000450: 2620 movs r6, #32
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8000452: fbb1 f1f7 udiv r1, r1, r7
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8000456: eba2 0208 sub.w r2, r2, r8
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800045a: ea41 410c orr.w r1, r1, ip, lsl #16
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800045e: e766 b.n 800032e <__udivmoddi4+0xfa>
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8000460: 4601 mov r1, r0
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8000462: e718 b.n 8000296 <__udivmoddi4+0x62>
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8000464: 4610 mov r0, r2
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8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e>
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8000468: f1c6 0220 rsb r2, r6, #32
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800046c: fa2e f302 lsr.w r3, lr, r2
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8000470: 40b7 lsls r7, r6
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8000472: 40b1 lsls r1, r6
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8000474: fa20 f202 lsr.w r2, r0, r2
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8000478: ea4f 4e17 mov.w lr, r7, lsr #16
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800047c: 430a orrs r2, r1
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800047e: fbb3 f8fe udiv r8, r3, lr
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8000482: b2bc uxth r4, r7
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8000484: fb0e 3318 mls r3, lr, r8, r3
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8000488: 0c11 lsrs r1, r2, #16
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800048a: ea41 4103 orr.w r1, r1, r3, lsl #16
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800048e: fb08 f904 mul.w r9, r8, r4
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8000492: 40b0 lsls r0, r6
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8000494: 4589 cmp r9, r1
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8000496: ea4f 4310 mov.w r3, r0, lsr #16
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800049a: b280 uxth r0, r0
|
|
800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8>
|
|
800049e: 1879 adds r1, r7, r1
|
|
80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276>
|
|
80004a6: 4589 cmp r9, r1
|
|
80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6>
|
|
80004aa: eba1 0109 sub.w r1, r1, r9
|
|
80004ae: fbb1 f9fe udiv r9, r1, lr
|
|
80004b2: fb09 f804 mul.w r8, r9, r4
|
|
80004b6: fb0e 1119 mls r1, lr, r9, r1
|
|
80004ba: b292 uxth r2, r2
|
|
80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
80004c0: 4542 cmp r2, r8
|
|
80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4>
|
|
80004c4: 18ba adds r2, r7, r2
|
|
80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222>
|
|
80004cc: 4542 cmp r2, r8
|
|
80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222>
|
|
80004d0: f1a9 0102 sub.w r1, r9, #2
|
|
80004d4: 443a add r2, r7
|
|
80004d6: e7be b.n 8000456 <__udivmoddi4+0x222>
|
|
80004d8: 45f0 cmp r8, lr
|
|
80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4>
|
|
80004dc: ebbe 0302 subs.w r3, lr, r2
|
|
80004e0: eb6c 0c07 sbc.w ip, ip, r7
|
|
80004e4: 3801 subs r0, #1
|
|
80004e6: 46e1 mov r9, ip
|
|
80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4>
|
|
80004ea: eba7 0909 sub.w r9, r7, r9
|
|
80004ee: 4449 add r1, r9
|
|
80004f0: f1a8 0c02 sub.w ip, r8, #2
|
|
80004f4: fbb1 f9fe udiv r9, r1, lr
|
|
80004f8: fb09 f804 mul.w r8, r9, r4
|
|
80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282>
|
|
80004fe: 4673 mov r3, lr
|
|
8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce>
|
|
8000502: 4650 mov r0, sl
|
|
8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0>
|
|
8000506: 4608 mov r0, r1
|
|
8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2>
|
|
800050a: 443b add r3, r7
|
|
800050c: 3a02 subs r2, #2
|
|
800050e: e733 b.n 8000378 <__udivmoddi4+0x144>
|
|
8000510: f1ac 0c02 sub.w ip, ip, #2
|
|
8000514: 443b add r3, r7
|
|
8000516: e71c b.n 8000352 <__udivmoddi4+0x11e>
|
|
8000518: 4649 mov r1, r9
|
|
800051a: e79c b.n 8000456 <__udivmoddi4+0x222>
|
|
800051c: eba1 0109 sub.w r1, r1, r9
|
|
8000520: 46c4 mov ip, r8
|
|
8000522: fbb1 f9fe udiv r9, r1, lr
|
|
8000526: fb09 f804 mul.w r8, r9, r4
|
|
800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282>
|
|
|
|
0800052c <__aeabi_idiv0>:
|
|
800052c: 4770 bx lr
|
|
800052e: bf00 nop
|
|
|
|
08000530 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8000530: b580 push {r7, lr}
|
|
8000532: b084 sub sp, #16
|
|
8000534: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8000536: f000 ff89 bl 800144c <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
800053a: f000 f87d bl 8000638 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
800053e: f000 faf9 bl 8000b34 <MX_GPIO_Init>
|
|
MX_TIM2_Init();
|
|
8000542: f000 f913 bl 800076c <MX_TIM2_Init>
|
|
MX_TIM3_Init();
|
|
8000546: f000 f969 bl 800081c <MX_TIM3_Init>
|
|
MX_DMA_Init();
|
|
800054a: f000 fa8d bl 8000a68 <MX_DMA_Init>
|
|
MX_UART4_Init();
|
|
800054e: f000 f9b9 bl 80008c4 <MX_UART4_Init>
|
|
MX_UART5_Init();
|
|
8000552: f000 f9e1 bl 8000918 <MX_UART5_Init>
|
|
MX_USART1_UART_Init();
|
|
8000556: f000 fa09 bl 800096c <MX_USART1_UART_Init>
|
|
MX_USART2_UART_Init();
|
|
800055a: f000 fa31 bl 80009c0 <MX_USART2_UART_Init>
|
|
MX_I2C1_Init();
|
|
800055e: f000 f8d7 bl 8000710 <MX_I2C1_Init>
|
|
MX_USART3_UART_Init();
|
|
8000562: f000 fa57 bl 8000a14 <MX_USART3_UART_Init>
|
|
MX_USB_DEVICE_Init();
|
|
8000566: f008 fb67 bl 8008c38 <MX_USB_DEVICE_Init>
|
|
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
if (MODE != MODE_INACTIVE){
|
|
800056a: 4b27 ldr r3, [pc, #156] @ (8000608 <main+0xd8>)
|
|
800056c: 781b ldrb r3, [r3, #0]
|
|
800056e: b2db uxtb r3, r3
|
|
8000570: 2b00 cmp r3, #0
|
|
8000572: d023 beq.n 80005bc <main+0x8c>
|
|
//Reset Report
|
|
resetReport();
|
|
8000574: f000 fc92 bl 8000e9c <resetReport>
|
|
|
|
//Query Neighbors
|
|
UARTMessage query;
|
|
query.depth = DEPTH;
|
|
8000578: 4b24 ldr r3, [pc, #144] @ (800060c <main+0xdc>)
|
|
800057a: 881b ldrh r3, [r3, #0]
|
|
800057c: 803b strh r3, [r7, #0]
|
|
query.msgType = 0x01;
|
|
800057e: 2301 movs r3, #1
|
|
8000580: 807b strh r3, [r7, #2]
|
|
memset(query.keypress, 1,sizeof(query.keypress));
|
|
8000582: 463b mov r3, r7
|
|
8000584: 3304 adds r3, #4
|
|
8000586: 220c movs r2, #12
|
|
8000588: 2101 movs r1, #1
|
|
800058a: 4618 mov r0, r3
|
|
800058c: f009 f802 bl 8009594 <memset>
|
|
|
|
matrixScan();
|
|
8000590: f000 fc2c bl 8000dec <matrixScan>
|
|
|
|
switch (MODE){
|
|
8000594: 4b1c ldr r3, [pc, #112] @ (8000608 <main+0xd8>)
|
|
8000596: 781b ldrb r3, [r3, #0]
|
|
8000598: b2db uxtb r3, r3
|
|
800059a: 2b01 cmp r3, #1
|
|
800059c: d008 beq.n 80005b0 <main+0x80>
|
|
800059e: 2b02 cmp r3, #2
|
|
80005a0: d129 bne.n 80005f6 <main+0xc6>
|
|
|
|
case MODE_ACTIVE:
|
|
HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&query, sizeof(query));
|
|
80005a2: 463b mov r3, r7
|
|
80005a4: 2210 movs r2, #16
|
|
80005a6: 4619 mov r1, r3
|
|
80005a8: 4819 ldr r0, [pc, #100] @ (8000610 <main+0xe0>)
|
|
80005aa: f004 fc93 bl 8004ed4 <HAL_UART_Transmit_DMA>
|
|
break;
|
|
80005ae: e022 b.n 80005f6 <main+0xc6>
|
|
|
|
case MODE_MAINBOARD:
|
|
//Send to USB
|
|
USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT));
|
|
80005b0: 220e movs r2, #14
|
|
80005b2: 4918 ldr r1, [pc, #96] @ (8000614 <main+0xe4>)
|
|
80005b4: 4818 ldr r0, [pc, #96] @ (8000618 <main+0xe8>)
|
|
80005b6: f006 ff5f bl 8007478 <USBD_HID_SendReport>
|
|
break;
|
|
80005ba: e01c b.n 80005f6 <main+0xc6>
|
|
//TODO: Send heartbeat signal to child nodes
|
|
|
|
|
|
}else{ //INACTIVE Mode
|
|
//Check if the USB is enumerated/connected.
|
|
if (hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED) {
|
|
80005bc: 4b16 ldr r3, [pc, #88] @ (8000618 <main+0xe8>)
|
|
80005be: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80005c2: b2db uxtb r3, r3
|
|
80005c4: 2b03 cmp r3, #3
|
|
80005c6: d116 bne.n 80005f6 <main+0xc6>
|
|
MODE = MODE_MAINBOARD;
|
|
80005c8: 4b0f ldr r3, [pc, #60] @ (8000608 <main+0xd8>)
|
|
80005ca: 2201 movs r2, #1
|
|
80005cc: 701a strb r2, [r3, #0]
|
|
//Enable DMA RX
|
|
HAL_UART_Receive_DMA(&huart1, UART1_RX_BUFF, UART_RX_BUFF_SIZE);
|
|
80005ce: 2240 movs r2, #64 @ 0x40
|
|
80005d0: 4912 ldr r1, [pc, #72] @ (800061c <main+0xec>)
|
|
80005d2: 4813 ldr r0, [pc, #76] @ (8000620 <main+0xf0>)
|
|
80005d4: f004 fcfa bl 8004fcc <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart2, UART2_RX_BUFF, UART_RX_BUFF_SIZE);
|
|
80005d8: 2240 movs r2, #64 @ 0x40
|
|
80005da: 4912 ldr r1, [pc, #72] @ (8000624 <main+0xf4>)
|
|
80005dc: 4812 ldr r0, [pc, #72] @ (8000628 <main+0xf8>)
|
|
80005de: f004 fcf5 bl 8004fcc <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart4, UART4_RX_BUFF, UART_RX_BUFF_SIZE);
|
|
80005e2: 2240 movs r2, #64 @ 0x40
|
|
80005e4: 4911 ldr r1, [pc, #68] @ (800062c <main+0xfc>)
|
|
80005e6: 480a ldr r0, [pc, #40] @ (8000610 <main+0xe0>)
|
|
80005e8: f004 fcf0 bl 8004fcc <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart5, UART5_RX_BUFF, UART_RX_BUFF_SIZE);
|
|
80005ec: 2240 movs r2, #64 @ 0x40
|
|
80005ee: 4910 ldr r1, [pc, #64] @ (8000630 <main+0x100>)
|
|
80005f0: 4810 ldr r0, [pc, #64] @ (8000634 <main+0x104>)
|
|
80005f2: f004 fceb bl 8004fcc <HAL_UART_Receive_DMA>
|
|
}else{
|
|
|
|
}
|
|
}
|
|
HAL_Delay(USBD_HID_GetPollingInterval(&hUsbDeviceFS));
|
|
80005f6: 4808 ldr r0, [pc, #32] @ (8000618 <main+0xe8>)
|
|
80005f8: f006 ff6e bl 80074d8 <USBD_HID_GetPollingInterval>
|
|
80005fc: 4603 mov r3, r0
|
|
80005fe: 4618 mov r0, r3
|
|
8000600: f000 ff96 bl 8001530 <HAL_Delay>
|
|
if (MODE != MODE_INACTIVE){
|
|
8000604: e7b1 b.n 800056a <main+0x3a>
|
|
8000606: bf00 nop
|
|
8000608: 20000024 .word 0x20000024
|
|
800060c: 200004ae .word 0x200004ae
|
|
8000610: 20000238 .word 0x20000238
|
|
8000614: 200004a0 .word 0x200004a0
|
|
8000618: 200004b8 .word 0x200004b8
|
|
800061c: 200003a0 .word 0x200003a0
|
|
8000620: 200002c8 .word 0x200002c8
|
|
8000624: 200003e0 .word 0x200003e0
|
|
8000628: 20000310 .word 0x20000310
|
|
800062c: 20000420 .word 0x20000420
|
|
8000630: 20000460 .word 0x20000460
|
|
8000634: 20000280 .word 0x20000280
|
|
|
|
08000638 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8000638: b580 push {r7, lr}
|
|
800063a: b094 sub sp, #80 @ 0x50
|
|
800063c: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
800063e: f107 031c add.w r3, r7, #28
|
|
8000642: 2234 movs r2, #52 @ 0x34
|
|
8000644: 2100 movs r1, #0
|
|
8000646: 4618 mov r0, r3
|
|
8000648: f008 ffa4 bl 8009594 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
800064c: f107 0308 add.w r3, r7, #8
|
|
8000650: 2200 movs r2, #0
|
|
8000652: 601a str r2, [r3, #0]
|
|
8000654: 605a str r2, [r3, #4]
|
|
8000656: 609a str r2, [r3, #8]
|
|
8000658: 60da str r2, [r3, #12]
|
|
800065a: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800065c: 2300 movs r3, #0
|
|
800065e: 607b str r3, [r7, #4]
|
|
8000660: 4b29 ldr r3, [pc, #164] @ (8000708 <SystemClock_Config+0xd0>)
|
|
8000662: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000664: 4a28 ldr r2, [pc, #160] @ (8000708 <SystemClock_Config+0xd0>)
|
|
8000666: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800066a: 6413 str r3, [r2, #64] @ 0x40
|
|
800066c: 4b26 ldr r3, [pc, #152] @ (8000708 <SystemClock_Config+0xd0>)
|
|
800066e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000670: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8000674: 607b str r3, [r7, #4]
|
|
8000676: 687b ldr r3, [r7, #4]
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
|
|
8000678: 2300 movs r3, #0
|
|
800067a: 603b str r3, [r7, #0]
|
|
800067c: 4b23 ldr r3, [pc, #140] @ (800070c <SystemClock_Config+0xd4>)
|
|
800067e: 681b ldr r3, [r3, #0]
|
|
8000680: f423 4340 bic.w r3, r3, #49152 @ 0xc000
|
|
8000684: 4a21 ldr r2, [pc, #132] @ (800070c <SystemClock_Config+0xd4>)
|
|
8000686: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
800068a: 6013 str r3, [r2, #0]
|
|
800068c: 4b1f ldr r3, [pc, #124] @ (800070c <SystemClock_Config+0xd4>)
|
|
800068e: 681b ldr r3, [r3, #0]
|
|
8000690: f403 4340 and.w r3, r3, #49152 @ 0xc000
|
|
8000694: 603b str r3, [r7, #0]
|
|
8000696: 683b ldr r3, [r7, #0]
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
8000698: 2301 movs r3, #1
|
|
800069a: 61fb str r3, [r7, #28]
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
800069c: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
80006a0: 623b str r3, [r7, #32]
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
80006a2: 2302 movs r3, #2
|
|
80006a4: 637b str r3, [r7, #52] @ 0x34
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
80006a6: f44f 0380 mov.w r3, #4194304 @ 0x400000
|
|
80006aa: 63bb str r3, [r7, #56] @ 0x38
|
|
RCC_OscInitStruct.PLL.PLLM = 4;
|
|
80006ac: 2304 movs r3, #4
|
|
80006ae: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.PLL.PLLN = 96;
|
|
80006b0: 2360 movs r3, #96 @ 0x60
|
|
80006b2: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
80006b4: 2302 movs r3, #2
|
|
80006b6: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLQ = 4;
|
|
80006b8: 2304 movs r3, #4
|
|
80006ba: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLR = 2;
|
|
80006bc: 2302 movs r3, #2
|
|
80006be: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
80006c0: f107 031c add.w r3, r7, #28
|
|
80006c4: 4618 mov r0, r3
|
|
80006c6: f003 fcf3 bl 80040b0 <HAL_RCC_OscConfig>
|
|
80006ca: 4603 mov r3, r0
|
|
80006cc: 2b00 cmp r3, #0
|
|
80006ce: d001 beq.n 80006d4 <SystemClock_Config+0x9c>
|
|
{
|
|
Error_Handler();
|
|
80006d0: f000 fbf4 bl 8000ebc <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
80006d4: 230f movs r3, #15
|
|
80006d6: 60bb str r3, [r7, #8]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
80006d8: 2302 movs r3, #2
|
|
80006da: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
|
|
80006dc: 2380 movs r3, #128 @ 0x80
|
|
80006de: 613b str r3, [r7, #16]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
|
|
80006e0: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
80006e4: 617b str r3, [r7, #20]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
80006e6: 2300 movs r3, #0
|
|
80006e8: 61bb str r3, [r7, #24]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
|
|
80006ea: f107 0308 add.w r3, r7, #8
|
|
80006ee: 2101 movs r1, #1
|
|
80006f0: 4618 mov r0, r3
|
|
80006f2: f002 fe69 bl 80033c8 <HAL_RCC_ClockConfig>
|
|
80006f6: 4603 mov r3, r0
|
|
80006f8: 2b00 cmp r3, #0
|
|
80006fa: d001 beq.n 8000700 <SystemClock_Config+0xc8>
|
|
{
|
|
Error_Handler();
|
|
80006fc: f000 fbde bl 8000ebc <Error_Handler>
|
|
}
|
|
}
|
|
8000700: bf00 nop
|
|
8000702: 3750 adds r7, #80 @ 0x50
|
|
8000704: 46bd mov sp, r7
|
|
8000706: bd80 pop {r7, pc}
|
|
8000708: 40023800 .word 0x40023800
|
|
800070c: 40007000 .word 0x40007000
|
|
|
|
08000710 <MX_I2C1_Init>:
|
|
* @brief I2C1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C1_Init(void)
|
|
{
|
|
8000710: b580 push {r7, lr}
|
|
8000712: af00 add r7, sp, #0
|
|
/* USER CODE END I2C1_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C1_Init 1 */
|
|
|
|
/* USER CODE END I2C1_Init 1 */
|
|
hi2c1.Instance = I2C1;
|
|
8000714: 4b12 ldr r3, [pc, #72] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
8000716: 4a13 ldr r2, [pc, #76] @ (8000764 <MX_I2C1_Init+0x54>)
|
|
8000718: 601a str r2, [r3, #0]
|
|
hi2c1.Init.ClockSpeed = 100000;
|
|
800071a: 4b11 ldr r3, [pc, #68] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
800071c: 4a12 ldr r2, [pc, #72] @ (8000768 <MX_I2C1_Init+0x58>)
|
|
800071e: 605a str r2, [r3, #4]
|
|
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
|
|
8000720: 4b0f ldr r3, [pc, #60] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
8000722: 2200 movs r2, #0
|
|
8000724: 609a str r2, [r3, #8]
|
|
hi2c1.Init.OwnAddress1 = 0;
|
|
8000726: 4b0e ldr r3, [pc, #56] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
8000728: 2200 movs r2, #0
|
|
800072a: 60da str r2, [r3, #12]
|
|
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
800072c: 4b0c ldr r3, [pc, #48] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
800072e: f44f 4280 mov.w r2, #16384 @ 0x4000
|
|
8000732: 611a str r2, [r3, #16]
|
|
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8000734: 4b0a ldr r3, [pc, #40] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
8000736: 2200 movs r2, #0
|
|
8000738: 615a str r2, [r3, #20]
|
|
hi2c1.Init.OwnAddress2 = 0;
|
|
800073a: 4b09 ldr r3, [pc, #36] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
800073c: 2200 movs r2, #0
|
|
800073e: 619a str r2, [r3, #24]
|
|
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8000740: 4b07 ldr r3, [pc, #28] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
8000742: 2200 movs r2, #0
|
|
8000744: 61da str r2, [r3, #28]
|
|
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8000746: 4b06 ldr r3, [pc, #24] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
8000748: 2200 movs r2, #0
|
|
800074a: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
|
|
800074c: 4804 ldr r0, [pc, #16] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
800074e: f001 fa71 bl 8001c34 <HAL_I2C_Init>
|
|
8000752: 4603 mov r3, r0
|
|
8000754: 2b00 cmp r3, #0
|
|
8000756: d001 beq.n 800075c <MX_I2C1_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8000758: f000 fbb0 bl 8000ebc <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C1_Init 2 */
|
|
|
|
/* USER CODE END I2C1_Init 2 */
|
|
|
|
}
|
|
800075c: bf00 nop
|
|
800075e: bd80 pop {r7, pc}
|
|
8000760: 20000154 .word 0x20000154
|
|
8000764: 40005400 .word 0x40005400
|
|
8000768: 000186a0 .word 0x000186a0
|
|
|
|
0800076c <MX_TIM2_Init>:
|
|
* @brief TIM2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM2_Init(void)
|
|
{
|
|
800076c: b580 push {r7, lr}
|
|
800076e: b08a sub sp, #40 @ 0x28
|
|
8000770: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM2_Init 0 */
|
|
|
|
/* USER CODE END TIM2_Init 0 */
|
|
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8000772: f107 0320 add.w r3, r7, #32
|
|
8000776: 2200 movs r2, #0
|
|
8000778: 601a str r2, [r3, #0]
|
|
800077a: 605a str r2, [r3, #4]
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
800077c: 1d3b adds r3, r7, #4
|
|
800077e: 2200 movs r2, #0
|
|
8000780: 601a str r2, [r3, #0]
|
|
8000782: 605a str r2, [r3, #4]
|
|
8000784: 609a str r2, [r3, #8]
|
|
8000786: 60da str r2, [r3, #12]
|
|
8000788: 611a str r2, [r3, #16]
|
|
800078a: 615a str r2, [r3, #20]
|
|
800078c: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE BEGIN TIM2_Init 1 */
|
|
|
|
/* USER CODE END TIM2_Init 1 */
|
|
htim2.Instance = TIM2;
|
|
800078e: 4b22 ldr r3, [pc, #136] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
8000790: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
|
|
8000794: 601a str r2, [r3, #0]
|
|
htim2.Init.Prescaler = 0;
|
|
8000796: 4b20 ldr r3, [pc, #128] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
8000798: 2200 movs r2, #0
|
|
800079a: 605a str r2, [r3, #4]
|
|
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
800079c: 4b1e ldr r3, [pc, #120] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
800079e: 2200 movs r2, #0
|
|
80007a0: 609a str r2, [r3, #8]
|
|
htim2.Init.Period = 4294967295;
|
|
80007a2: 4b1d ldr r3, [pc, #116] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
80007a4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80007a8: 60da str r2, [r3, #12]
|
|
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
80007aa: 4b1b ldr r3, [pc, #108] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
80007ac: 2200 movs r2, #0
|
|
80007ae: 611a str r2, [r3, #16]
|
|
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
80007b0: 4b19 ldr r3, [pc, #100] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
80007b2: 2200 movs r2, #0
|
|
80007b4: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_OC_Init(&htim2) != HAL_OK)
|
|
80007b6: 4818 ldr r0, [pc, #96] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
80007b8: f003 ff18 bl 80045ec <HAL_TIM_OC_Init>
|
|
80007bc: 4603 mov r3, r0
|
|
80007be: 2b00 cmp r3, #0
|
|
80007c0: d001 beq.n 80007c6 <MX_TIM2_Init+0x5a>
|
|
{
|
|
Error_Handler();
|
|
80007c2: f000 fb7b bl 8000ebc <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
80007c6: 2300 movs r3, #0
|
|
80007c8: 623b str r3, [r7, #32]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
80007ca: 2300 movs r3, #0
|
|
80007cc: 627b str r3, [r7, #36] @ 0x24
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
|
|
80007ce: f107 0320 add.w r3, r7, #32
|
|
80007d2: 4619 mov r1, r3
|
|
80007d4: 4810 ldr r0, [pc, #64] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
80007d6: f004 fab1 bl 8004d3c <HAL_TIMEx_MasterConfigSynchronization>
|
|
80007da: 4603 mov r3, r0
|
|
80007dc: 2b00 cmp r3, #0
|
|
80007de: d001 beq.n 80007e4 <MX_TIM2_Init+0x78>
|
|
{
|
|
Error_Handler();
|
|
80007e0: f000 fb6c bl 8000ebc <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE;
|
|
80007e4: 2350 movs r3, #80 @ 0x50
|
|
80007e6: 607b str r3, [r7, #4]
|
|
sConfigOC.Pulse = 0;
|
|
80007e8: 2300 movs r3, #0
|
|
80007ea: 60bb str r3, [r7, #8]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
80007ec: 2300 movs r3, #0
|
|
80007ee: 60fb str r3, [r7, #12]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
80007f0: 2300 movs r3, #0
|
|
80007f2: 617b str r3, [r7, #20]
|
|
if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
80007f4: 1d3b adds r3, r7, #4
|
|
80007f6: 2200 movs r2, #0
|
|
80007f8: 4619 mov r1, r3
|
|
80007fa: 4807 ldr r0, [pc, #28] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
80007fc: f003 ffec bl 80047d8 <HAL_TIM_OC_ConfigChannel>
|
|
8000800: 4603 mov r3, r0
|
|
8000802: 2b00 cmp r3, #0
|
|
8000804: d001 beq.n 800080a <MX_TIM2_Init+0x9e>
|
|
{
|
|
Error_Handler();
|
|
8000806: f000 fb59 bl 8000ebc <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM2_Init 2 */
|
|
|
|
/* USER CODE END TIM2_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim2);
|
|
800080a: 4803 ldr r0, [pc, #12] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
800080c: f000 fc34 bl 8001078 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
8000810: bf00 nop
|
|
8000812: 3728 adds r7, #40 @ 0x28
|
|
8000814: 46bd mov sp, r7
|
|
8000816: bd80 pop {r7, pc}
|
|
8000818: 200001a8 .word 0x200001a8
|
|
|
|
0800081c <MX_TIM3_Init>:
|
|
* @brief TIM3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM3_Init(void)
|
|
{
|
|
800081c: b580 push {r7, lr}
|
|
800081e: b08c sub sp, #48 @ 0x30
|
|
8000820: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM3_Init 0 */
|
|
|
|
/* USER CODE END TIM3_Init 0 */
|
|
|
|
TIM_Encoder_InitTypeDef sConfig = {0};
|
|
8000822: f107 030c add.w r3, r7, #12
|
|
8000826: 2224 movs r2, #36 @ 0x24
|
|
8000828: 2100 movs r1, #0
|
|
800082a: 4618 mov r0, r3
|
|
800082c: f008 feb2 bl 8009594 <memset>
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8000830: 1d3b adds r3, r7, #4
|
|
8000832: 2200 movs r2, #0
|
|
8000834: 601a str r2, [r3, #0]
|
|
8000836: 605a str r2, [r3, #4]
|
|
|
|
/* USER CODE BEGIN TIM3_Init 1 */
|
|
|
|
/* USER CODE END TIM3_Init 1 */
|
|
htim3.Instance = TIM3;
|
|
8000838: 4b20 ldr r3, [pc, #128] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
800083a: 4a21 ldr r2, [pc, #132] @ (80008c0 <MX_TIM3_Init+0xa4>)
|
|
800083c: 601a str r2, [r3, #0]
|
|
htim3.Init.Prescaler = 0;
|
|
800083e: 4b1f ldr r3, [pc, #124] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
8000840: 2200 movs r2, #0
|
|
8000842: 605a str r2, [r3, #4]
|
|
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8000844: 4b1d ldr r3, [pc, #116] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
8000846: 2200 movs r2, #0
|
|
8000848: 609a str r2, [r3, #8]
|
|
htim3.Init.Period = 65535;
|
|
800084a: 4b1c ldr r3, [pc, #112] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
800084c: f64f 72ff movw r2, #65535 @ 0xffff
|
|
8000850: 60da str r2, [r3, #12]
|
|
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8000852: 4b1a ldr r3, [pc, #104] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
8000854: 2200 movs r2, #0
|
|
8000856: 611a str r2, [r3, #16]
|
|
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8000858: 4b18 ldr r3, [pc, #96] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
800085a: 2200 movs r2, #0
|
|
800085c: 619a str r2, [r3, #24]
|
|
sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
|
|
800085e: 2301 movs r3, #1
|
|
8000860: 60fb str r3, [r7, #12]
|
|
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
|
|
8000862: 2300 movs r3, #0
|
|
8000864: 613b str r3, [r7, #16]
|
|
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
|
|
8000866: 2301 movs r3, #1
|
|
8000868: 617b str r3, [r7, #20]
|
|
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
|
|
800086a: 2300 movs r3, #0
|
|
800086c: 61bb str r3, [r7, #24]
|
|
sConfig.IC1Filter = 0;
|
|
800086e: 2300 movs r3, #0
|
|
8000870: 61fb str r3, [r7, #28]
|
|
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
|
|
8000872: 2300 movs r3, #0
|
|
8000874: 623b str r3, [r7, #32]
|
|
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
|
|
8000876: 2301 movs r3, #1
|
|
8000878: 627b str r3, [r7, #36] @ 0x24
|
|
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
|
|
800087a: 2300 movs r3, #0
|
|
800087c: 62bb str r3, [r7, #40] @ 0x28
|
|
sConfig.IC2Filter = 0;
|
|
800087e: 2300 movs r3, #0
|
|
8000880: 62fb str r3, [r7, #44] @ 0x2c
|
|
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
|
|
8000882: f107 030c add.w r3, r7, #12
|
|
8000886: 4619 mov r1, r3
|
|
8000888: 480c ldr r0, [pc, #48] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
800088a: f003 fefe bl 800468a <HAL_TIM_Encoder_Init>
|
|
800088e: 4603 mov r3, r0
|
|
8000890: 2b00 cmp r3, #0
|
|
8000892: d001 beq.n 8000898 <MX_TIM3_Init+0x7c>
|
|
{
|
|
Error_Handler();
|
|
8000894: f000 fb12 bl 8000ebc <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8000898: 2300 movs r3, #0
|
|
800089a: 607b str r3, [r7, #4]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
800089c: 2300 movs r3, #0
|
|
800089e: 60bb str r3, [r7, #8]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
|
80008a0: 1d3b adds r3, r7, #4
|
|
80008a2: 4619 mov r1, r3
|
|
80008a4: 4805 ldr r0, [pc, #20] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
80008a6: f004 fa49 bl 8004d3c <HAL_TIMEx_MasterConfigSynchronization>
|
|
80008aa: 4603 mov r3, r0
|
|
80008ac: 2b00 cmp r3, #0
|
|
80008ae: d001 beq.n 80008b4 <MX_TIM3_Init+0x98>
|
|
{
|
|
Error_Handler();
|
|
80008b0: f000 fb04 bl 8000ebc <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM3_Init 2 */
|
|
|
|
/* USER CODE END TIM3_Init 2 */
|
|
|
|
}
|
|
80008b4: bf00 nop
|
|
80008b6: 3730 adds r7, #48 @ 0x30
|
|
80008b8: 46bd mov sp, r7
|
|
80008ba: bd80 pop {r7, pc}
|
|
80008bc: 200001f0 .word 0x200001f0
|
|
80008c0: 40000400 .word 0x40000400
|
|
|
|
080008c4 <MX_UART4_Init>:
|
|
* @brief UART4 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_UART4_Init(void)
|
|
{
|
|
80008c4: b580 push {r7, lr}
|
|
80008c6: af00 add r7, sp, #0
|
|
/* USER CODE END UART4_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART4_Init 1 */
|
|
|
|
/* USER CODE END UART4_Init 1 */
|
|
huart4.Instance = UART4;
|
|
80008c8: 4b11 ldr r3, [pc, #68] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008ca: 4a12 ldr r2, [pc, #72] @ (8000914 <MX_UART4_Init+0x50>)
|
|
80008cc: 601a str r2, [r3, #0]
|
|
huart4.Init.BaudRate = 115200;
|
|
80008ce: 4b10 ldr r3, [pc, #64] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008d0: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
80008d4: 605a str r2, [r3, #4]
|
|
huart4.Init.WordLength = UART_WORDLENGTH_8B;
|
|
80008d6: 4b0e ldr r3, [pc, #56] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008d8: 2200 movs r2, #0
|
|
80008da: 609a str r2, [r3, #8]
|
|
huart4.Init.StopBits = UART_STOPBITS_1;
|
|
80008dc: 4b0c ldr r3, [pc, #48] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008de: 2200 movs r2, #0
|
|
80008e0: 60da str r2, [r3, #12]
|
|
huart4.Init.Parity = UART_PARITY_NONE;
|
|
80008e2: 4b0b ldr r3, [pc, #44] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008e4: 2200 movs r2, #0
|
|
80008e6: 611a str r2, [r3, #16]
|
|
huart4.Init.Mode = UART_MODE_TX_RX;
|
|
80008e8: 4b09 ldr r3, [pc, #36] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008ea: 220c movs r2, #12
|
|
80008ec: 615a str r2, [r3, #20]
|
|
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80008ee: 4b08 ldr r3, [pc, #32] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008f0: 2200 movs r2, #0
|
|
80008f2: 619a str r2, [r3, #24]
|
|
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80008f4: 4b06 ldr r3, [pc, #24] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008f6: 2200 movs r2, #0
|
|
80008f8: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart4) != HAL_OK)
|
|
80008fa: 4805 ldr r0, [pc, #20] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008fc: f004 fa9a bl 8004e34 <HAL_UART_Init>
|
|
8000900: 4603 mov r3, r0
|
|
8000902: 2b00 cmp r3, #0
|
|
8000904: d001 beq.n 800090a <MX_UART4_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8000906: f000 fad9 bl 8000ebc <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART4_Init 2 */
|
|
|
|
/* USER CODE END UART4_Init 2 */
|
|
|
|
}
|
|
800090a: bf00 nop
|
|
800090c: bd80 pop {r7, pc}
|
|
800090e: bf00 nop
|
|
8000910: 20000238 .word 0x20000238
|
|
8000914: 40004c00 .word 0x40004c00
|
|
|
|
08000918 <MX_UART5_Init>:
|
|
* @brief UART5 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_UART5_Init(void)
|
|
{
|
|
8000918: b580 push {r7, lr}
|
|
800091a: af00 add r7, sp, #0
|
|
/* USER CODE END UART5_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART5_Init 1 */
|
|
|
|
/* USER CODE END UART5_Init 1 */
|
|
huart5.Instance = UART5;
|
|
800091c: 4b11 ldr r3, [pc, #68] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
800091e: 4a12 ldr r2, [pc, #72] @ (8000968 <MX_UART5_Init+0x50>)
|
|
8000920: 601a str r2, [r3, #0]
|
|
huart5.Init.BaudRate = 115200;
|
|
8000922: 4b10 ldr r3, [pc, #64] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
8000924: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8000928: 605a str r2, [r3, #4]
|
|
huart5.Init.WordLength = UART_WORDLENGTH_8B;
|
|
800092a: 4b0e ldr r3, [pc, #56] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
800092c: 2200 movs r2, #0
|
|
800092e: 609a str r2, [r3, #8]
|
|
huart5.Init.StopBits = UART_STOPBITS_1;
|
|
8000930: 4b0c ldr r3, [pc, #48] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
8000932: 2200 movs r2, #0
|
|
8000934: 60da str r2, [r3, #12]
|
|
huart5.Init.Parity = UART_PARITY_NONE;
|
|
8000936: 4b0b ldr r3, [pc, #44] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
8000938: 2200 movs r2, #0
|
|
800093a: 611a str r2, [r3, #16]
|
|
huart5.Init.Mode = UART_MODE_TX_RX;
|
|
800093c: 4b09 ldr r3, [pc, #36] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
800093e: 220c movs r2, #12
|
|
8000940: 615a str r2, [r3, #20]
|
|
huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8000942: 4b08 ldr r3, [pc, #32] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
8000944: 2200 movs r2, #0
|
|
8000946: 619a str r2, [r3, #24]
|
|
huart5.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8000948: 4b06 ldr r3, [pc, #24] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
800094a: 2200 movs r2, #0
|
|
800094c: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart5) != HAL_OK)
|
|
800094e: 4805 ldr r0, [pc, #20] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
8000950: f004 fa70 bl 8004e34 <HAL_UART_Init>
|
|
8000954: 4603 mov r3, r0
|
|
8000956: 2b00 cmp r3, #0
|
|
8000958: d001 beq.n 800095e <MX_UART5_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
800095a: f000 faaf bl 8000ebc <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART5_Init 2 */
|
|
|
|
/* USER CODE END UART5_Init 2 */
|
|
|
|
}
|
|
800095e: bf00 nop
|
|
8000960: bd80 pop {r7, pc}
|
|
8000962: bf00 nop
|
|
8000964: 20000280 .word 0x20000280
|
|
8000968: 40005000 .word 0x40005000
|
|
|
|
0800096c <MX_USART1_UART_Init>:
|
|
* @brief USART1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART1_UART_Init(void)
|
|
{
|
|
800096c: b580 push {r7, lr}
|
|
800096e: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
8000970: 4b11 ldr r3, [pc, #68] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
8000972: 4a12 ldr r2, [pc, #72] @ (80009bc <MX_USART1_UART_Init+0x50>)
|
|
8000974: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8000976: 4b10 ldr r3, [pc, #64] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
8000978: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
800097c: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
800097e: 4b0e ldr r3, [pc, #56] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
8000980: 2200 movs r2, #0
|
|
8000982: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8000984: 4b0c ldr r3, [pc, #48] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
8000986: 2200 movs r2, #0
|
|
8000988: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
800098a: 4b0b ldr r3, [pc, #44] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
800098c: 2200 movs r2, #0
|
|
800098e: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8000990: 4b09 ldr r3, [pc, #36] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
8000992: 220c movs r2, #12
|
|
8000994: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8000996: 4b08 ldr r3, [pc, #32] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
8000998: 2200 movs r2, #0
|
|
800099a: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
800099c: 4b06 ldr r3, [pc, #24] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
800099e: 2200 movs r2, #0
|
|
80009a0: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
80009a2: 4805 ldr r0, [pc, #20] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
80009a4: f004 fa46 bl 8004e34 <HAL_UART_Init>
|
|
80009a8: 4603 mov r3, r0
|
|
80009aa: 2b00 cmp r3, #0
|
|
80009ac: d001 beq.n 80009b2 <MX_USART1_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
80009ae: f000 fa85 bl 8000ebc <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
80009b2: bf00 nop
|
|
80009b4: bd80 pop {r7, pc}
|
|
80009b6: bf00 nop
|
|
80009b8: 200002c8 .word 0x200002c8
|
|
80009bc: 40011000 .word 0x40011000
|
|
|
|
080009c0 <MX_USART2_UART_Init>:
|
|
* @brief USART2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART2_UART_Init(void)
|
|
{
|
|
80009c0: b580 push {r7, lr}
|
|
80009c2: af00 add r7, sp, #0
|
|
/* USER CODE END USART2_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
|
|
|
/* USER CODE END USART2_Init 1 */
|
|
huart2.Instance = USART2;
|
|
80009c4: 4b11 ldr r3, [pc, #68] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009c6: 4a12 ldr r2, [pc, #72] @ (8000a10 <MX_USART2_UART_Init+0x50>)
|
|
80009c8: 601a str r2, [r3, #0]
|
|
huart2.Init.BaudRate = 115200;
|
|
80009ca: 4b10 ldr r3, [pc, #64] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009cc: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
80009d0: 605a str r2, [r3, #4]
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
80009d2: 4b0e ldr r3, [pc, #56] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009d4: 2200 movs r2, #0
|
|
80009d6: 609a str r2, [r3, #8]
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
80009d8: 4b0c ldr r3, [pc, #48] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009da: 2200 movs r2, #0
|
|
80009dc: 60da str r2, [r3, #12]
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
80009de: 4b0b ldr r3, [pc, #44] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009e0: 2200 movs r2, #0
|
|
80009e2: 611a str r2, [r3, #16]
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
80009e4: 4b09 ldr r3, [pc, #36] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009e6: 220c movs r2, #12
|
|
80009e8: 615a str r2, [r3, #20]
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80009ea: 4b08 ldr r3, [pc, #32] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009ec: 2200 movs r2, #0
|
|
80009ee: 619a str r2, [r3, #24]
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80009f0: 4b06 ldr r3, [pc, #24] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009f2: 2200 movs r2, #0
|
|
80009f4: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
|
80009f6: 4805 ldr r0, [pc, #20] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009f8: f004 fa1c bl 8004e34 <HAL_UART_Init>
|
|
80009fc: 4603 mov r3, r0
|
|
80009fe: 2b00 cmp r3, #0
|
|
8000a00: d001 beq.n 8000a06 <MX_USART2_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8000a02: f000 fa5b bl 8000ebc <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
|
|
|
/* USER CODE END USART2_Init 2 */
|
|
|
|
}
|
|
8000a06: bf00 nop
|
|
8000a08: bd80 pop {r7, pc}
|
|
8000a0a: bf00 nop
|
|
8000a0c: 20000310 .word 0x20000310
|
|
8000a10: 40004400 .word 0x40004400
|
|
|
|
08000a14 <MX_USART3_UART_Init>:
|
|
* @brief USART3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART3_UART_Init(void)
|
|
{
|
|
8000a14: b580 push {r7, lr}
|
|
8000a16: af00 add r7, sp, #0
|
|
/* USER CODE END USART3_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART3_Init 1 */
|
|
|
|
/* USER CODE END USART3_Init 1 */
|
|
huart3.Instance = USART3;
|
|
8000a18: 4b11 ldr r3, [pc, #68] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a1a: 4a12 ldr r2, [pc, #72] @ (8000a64 <MX_USART3_UART_Init+0x50>)
|
|
8000a1c: 601a str r2, [r3, #0]
|
|
huart3.Init.BaudRate = 115200;
|
|
8000a1e: 4b10 ldr r3, [pc, #64] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a20: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8000a24: 605a str r2, [r3, #4]
|
|
huart3.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8000a26: 4b0e ldr r3, [pc, #56] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a28: 2200 movs r2, #0
|
|
8000a2a: 609a str r2, [r3, #8]
|
|
huart3.Init.StopBits = UART_STOPBITS_1;
|
|
8000a2c: 4b0c ldr r3, [pc, #48] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a2e: 2200 movs r2, #0
|
|
8000a30: 60da str r2, [r3, #12]
|
|
huart3.Init.Parity = UART_PARITY_NONE;
|
|
8000a32: 4b0b ldr r3, [pc, #44] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a34: 2200 movs r2, #0
|
|
8000a36: 611a str r2, [r3, #16]
|
|
huart3.Init.Mode = UART_MODE_TX_RX;
|
|
8000a38: 4b09 ldr r3, [pc, #36] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a3a: 220c movs r2, #12
|
|
8000a3c: 615a str r2, [r3, #20]
|
|
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8000a3e: 4b08 ldr r3, [pc, #32] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a40: 2200 movs r2, #0
|
|
8000a42: 619a str r2, [r3, #24]
|
|
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8000a44: 4b06 ldr r3, [pc, #24] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a46: 2200 movs r2, #0
|
|
8000a48: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart3) != HAL_OK)
|
|
8000a4a: 4805 ldr r0, [pc, #20] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a4c: f004 f9f2 bl 8004e34 <HAL_UART_Init>
|
|
8000a50: 4603 mov r3, r0
|
|
8000a52: 2b00 cmp r3, #0
|
|
8000a54: d001 beq.n 8000a5a <MX_USART3_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8000a56: f000 fa31 bl 8000ebc <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART3_Init 2 */
|
|
|
|
/* USER CODE END USART3_Init 2 */
|
|
}
|
|
8000a5a: bf00 nop
|
|
8000a5c: bd80 pop {r7, pc}
|
|
8000a5e: bf00 nop
|
|
8000a60: 20000358 .word 0x20000358
|
|
8000a64: 40004800 .word 0x40004800
|
|
|
|
08000a68 <MX_DMA_Init>:
|
|
|
|
static void MX_DMA_Init(void)
|
|
{
|
|
8000a68: b580 push {r7, lr}
|
|
8000a6a: b082 sub sp, #8
|
|
8000a6c: af00 add r7, sp, #0
|
|
|
|
/* DMA controller clock enable */
|
|
__HAL_RCC_DMA2_CLK_ENABLE();
|
|
8000a6e: 2300 movs r3, #0
|
|
8000a70: 607b str r3, [r7, #4]
|
|
8000a72: 4b2f ldr r3, [pc, #188] @ (8000b30 <MX_DMA_Init+0xc8>)
|
|
8000a74: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a76: 4a2e ldr r2, [pc, #184] @ (8000b30 <MX_DMA_Init+0xc8>)
|
|
8000a78: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8000a7c: 6313 str r3, [r2, #48] @ 0x30
|
|
8000a7e: 4b2c ldr r3, [pc, #176] @ (8000b30 <MX_DMA_Init+0xc8>)
|
|
8000a80: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a82: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8000a86: 607b str r3, [r7, #4]
|
|
8000a88: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_DMA1_CLK_ENABLE();
|
|
8000a8a: 2300 movs r3, #0
|
|
8000a8c: 603b str r3, [r7, #0]
|
|
8000a8e: 4b28 ldr r3, [pc, #160] @ (8000b30 <MX_DMA_Init+0xc8>)
|
|
8000a90: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a92: 4a27 ldr r2, [pc, #156] @ (8000b30 <MX_DMA_Init+0xc8>)
|
|
8000a94: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8000a98: 6313 str r3, [r2, #48] @ 0x30
|
|
8000a9a: 4b25 ldr r3, [pc, #148] @ (8000b30 <MX_DMA_Init+0xc8>)
|
|
8000a9c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a9e: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8000aa2: 603b str r3, [r7, #0]
|
|
8000aa4: 683b ldr r3, [r7, #0]
|
|
|
|
/* DMA interrupt init */
|
|
/* DMA1_Stream0_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);
|
|
8000aa6: 2200 movs r2, #0
|
|
8000aa8: 2100 movs r1, #0
|
|
8000aaa: 200b movs r0, #11
|
|
8000aac: f000 fe3f bl 800172e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
|
|
8000ab0: 200b movs r0, #11
|
|
8000ab2: f000 fe58 bl 8001766 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream2_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0);
|
|
8000ab6: 2200 movs r2, #0
|
|
8000ab8: 2100 movs r1, #0
|
|
8000aba: 200d movs r0, #13
|
|
8000abc: f000 fe37 bl 800172e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
|
|
8000ac0: 200d movs r0, #13
|
|
8000ac2: f000 fe50 bl 8001766 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream4_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0);
|
|
8000ac6: 2200 movs r2, #0
|
|
8000ac8: 2100 movs r1, #0
|
|
8000aca: 200f movs r0, #15
|
|
8000acc: f000 fe2f bl 800172e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);
|
|
8000ad0: 200f movs r0, #15
|
|
8000ad2: f000 fe48 bl 8001766 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream5_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0);
|
|
8000ad6: 2200 movs r2, #0
|
|
8000ad8: 2100 movs r1, #0
|
|
8000ada: 2010 movs r0, #16
|
|
8000adc: f000 fe27 bl 800172e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
|
|
8000ae0: 2010 movs r0, #16
|
|
8000ae2: f000 fe40 bl 8001766 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream6_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0);
|
|
8000ae6: 2200 movs r2, #0
|
|
8000ae8: 2100 movs r1, #0
|
|
8000aea: 2011 movs r0, #17
|
|
8000aec: f000 fe1f bl 800172e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn);
|
|
8000af0: 2011 movs r0, #17
|
|
8000af2: f000 fe38 bl 8001766 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream7_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0);
|
|
8000af6: 2200 movs r2, #0
|
|
8000af8: 2100 movs r1, #0
|
|
8000afa: 202f movs r0, #47 @ 0x2f
|
|
8000afc: f000 fe17 bl 800172e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);
|
|
8000b00: 202f movs r0, #47 @ 0x2f
|
|
8000b02: f000 fe30 bl 8001766 <HAL_NVIC_EnableIRQ>
|
|
/* DMA2_Stream2_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0);
|
|
8000b06: 2200 movs r2, #0
|
|
8000b08: 2100 movs r1, #0
|
|
8000b0a: 203a movs r0, #58 @ 0x3a
|
|
8000b0c: f000 fe0f bl 800172e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
|
|
8000b10: 203a movs r0, #58 @ 0x3a
|
|
8000b12: f000 fe28 bl 8001766 <HAL_NVIC_EnableIRQ>
|
|
/* DMA2_Stream7_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0);
|
|
8000b16: 2200 movs r2, #0
|
|
8000b18: 2100 movs r1, #0
|
|
8000b1a: 2046 movs r0, #70 @ 0x46
|
|
8000b1c: f000 fe07 bl 800172e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
|
|
8000b20: 2046 movs r0, #70 @ 0x46
|
|
8000b22: f000 fe20 bl 8001766 <HAL_NVIC_EnableIRQ>
|
|
|
|
}
|
|
8000b26: bf00 nop
|
|
8000b28: 3708 adds r7, #8
|
|
8000b2a: 46bd mov sp, r7
|
|
8000b2c: bd80 pop {r7, pc}
|
|
8000b2e: bf00 nop
|
|
8000b30: 40023800 .word 0x40023800
|
|
|
|
08000b34 <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8000b34: b580 push {r7, lr}
|
|
8000b36: b08a sub sp, #40 @ 0x28
|
|
8000b38: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000b3a: f107 0314 add.w r3, r7, #20
|
|
8000b3e: 2200 movs r2, #0
|
|
8000b40: 601a str r2, [r3, #0]
|
|
8000b42: 605a str r2, [r3, #4]
|
|
8000b44: 609a str r2, [r3, #8]
|
|
8000b46: 60da str r2, [r3, #12]
|
|
8000b48: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
8000b4a: 2300 movs r3, #0
|
|
8000b4c: 613b str r3, [r7, #16]
|
|
8000b4e: 4b45 ldr r3, [pc, #276] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b50: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b52: 4a44 ldr r2, [pc, #272] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b54: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8000b58: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b5a: 4b42 ldr r3, [pc, #264] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b5c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b5e: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8000b62: 613b str r3, [r7, #16]
|
|
8000b64: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000b66: 2300 movs r3, #0
|
|
8000b68: 60fb str r3, [r7, #12]
|
|
8000b6a: 4b3e ldr r3, [pc, #248] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b6c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b6e: 4a3d ldr r2, [pc, #244] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b70: f043 0301 orr.w r3, r3, #1
|
|
8000b74: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b76: 4b3b ldr r3, [pc, #236] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b78: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b7a: f003 0301 and.w r3, r3, #1
|
|
8000b7e: 60fb str r3, [r7, #12]
|
|
8000b80: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8000b82: 2300 movs r3, #0
|
|
8000b84: 60bb str r3, [r7, #8]
|
|
8000b86: 4b37 ldr r3, [pc, #220] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b88: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b8a: 4a36 ldr r2, [pc, #216] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b8c: f043 0304 orr.w r3, r3, #4
|
|
8000b90: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b92: 4b34 ldr r3, [pc, #208] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b94: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b96: f003 0304 and.w r3, r3, #4
|
|
8000b9a: 60bb str r3, [r7, #8]
|
|
8000b9c: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000b9e: 2300 movs r3, #0
|
|
8000ba0: 607b str r3, [r7, #4]
|
|
8000ba2: 4b30 ldr r3, [pc, #192] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000ba4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000ba6: 4a2f ldr r2, [pc, #188] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000ba8: f043 0302 orr.w r3, r3, #2
|
|
8000bac: 6313 str r3, [r2, #48] @ 0x30
|
|
8000bae: 4b2d ldr r3, [pc, #180] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000bb0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000bb2: f003 0302 and.w r3, r3, #2
|
|
8000bb6: 607b str r3, [r7, #4]
|
|
8000bb8: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8000bba: 2300 movs r3, #0
|
|
8000bbc: 603b str r3, [r7, #0]
|
|
8000bbe: 4b29 ldr r3, [pc, #164] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000bc0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000bc2: 4a28 ldr r2, [pc, #160] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000bc4: f043 0308 orr.w r3, r3, #8
|
|
8000bc8: 6313 str r3, [r2, #48] @ 0x30
|
|
8000bca: 4b26 ldr r3, [pc, #152] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000bcc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000bce: f003 0308 and.w r3, r3, #8
|
|
8000bd2: 603b str r3, [r7, #0]
|
|
8000bd4: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET);
|
|
8000bd6: 2200 movs r2, #0
|
|
8000bd8: f44f 7170 mov.w r1, #960 @ 0x3c0
|
|
8000bdc: 4822 ldr r0, [pc, #136] @ (8000c68 <MX_GPIO_Init+0x134>)
|
|
8000bde: f001 f80f bl 8001c00 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET);
|
|
8000be2: 2200 movs r2, #0
|
|
8000be4: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8000be8: 4820 ldr r0, [pc, #128] @ (8000c6c <MX_GPIO_Init+0x138>)
|
|
8000bea: f001 f809 bl 8001c00 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : PC4 PC5 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
|
|
8000bee: 2330 movs r3, #48 @ 0x30
|
|
8000bf0: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8000bf2: 2300 movs r3, #0
|
|
8000bf4: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
8000bf6: 2302 movs r3, #2
|
|
8000bf8: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8000bfa: f107 0314 add.w r3, r7, #20
|
|
8000bfe: 4619 mov r1, r3
|
|
8000c00: 4819 ldr r0, [pc, #100] @ (8000c68 <MX_GPIO_Init+0x134>)
|
|
8000c02: f000 fe51 bl 80018a8 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PB0 PB1 PB2 PB10 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10;
|
|
8000c06: f240 4307 movw r3, #1031 @ 0x407
|
|
8000c0a: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8000c0c: 2300 movs r3, #0
|
|
8000c0e: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
8000c10: 2302 movs r3, #2
|
|
8000c12: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8000c14: f107 0314 add.w r3, r7, #20
|
|
8000c18: 4619 mov r1, r3
|
|
8000c1a: 4815 ldr r0, [pc, #84] @ (8000c70 <MX_GPIO_Init+0x13c>)
|
|
8000c1c: f000 fe44 bl 80018a8 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PC6 PC7 PC8 PC9 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9;
|
|
8000c20: f44f 7370 mov.w r3, #960 @ 0x3c0
|
|
8000c24: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000c26: 2301 movs r3, #1
|
|
8000c28: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
8000c2a: 2302 movs r3, #2
|
|
8000c2c: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000c2e: 2300 movs r3, #0
|
|
8000c30: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8000c32: f107 0314 add.w r3, r7, #20
|
|
8000c36: 4619 mov r1, r3
|
|
8000c38: 480b ldr r0, [pc, #44] @ (8000c68 <MX_GPIO_Init+0x134>)
|
|
8000c3a: f000 fe35 bl 80018a8 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : PA8 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_8;
|
|
8000c3e: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8000c42: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000c44: 2301 movs r3, #1
|
|
8000c46: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
8000c48: 2302 movs r3, #2
|
|
8000c4a: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000c4c: 2300 movs r3, #0
|
|
8000c4e: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000c50: f107 0314 add.w r3, r7, #20
|
|
8000c54: 4619 mov r1, r3
|
|
8000c56: 4805 ldr r0, [pc, #20] @ (8000c6c <MX_GPIO_Init+0x138>)
|
|
8000c58: f000 fe26 bl 80018a8 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
8000c5c: bf00 nop
|
|
8000c5e: 3728 adds r7, #40 @ 0x28
|
|
8000c60: 46bd mov sp, r7
|
|
8000c62: bd80 pop {r7, pc}
|
|
8000c64: 40023800 .word 0x40023800
|
|
8000c68: 40020800 .word 0x40020800
|
|
8000c6c: 40020000 .word 0x40020000
|
|
8000c70: 40020400 .word 0x40020400
|
|
|
|
08000c74 <HAL_UART_RxCpltCallback>:
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
//UART Message Requests Goes Here
|
|
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart){
|
|
8000c74: b580 push {r7, lr}
|
|
8000c76: b082 sub sp, #8
|
|
8000c78: af00 add r7, sp, #0
|
|
8000c7a: 6078 str r0, [r7, #4]
|
|
if(huart->Instance == USART1){
|
|
8000c7c: 687b ldr r3, [r7, #4]
|
|
8000c7e: 681b ldr r3, [r3, #0]
|
|
8000c80: 4a07 ldr r2, [pc, #28] @ (8000ca0 <HAL_UART_RxCpltCallback+0x2c>)
|
|
8000c82: 4293 cmp r3, r2
|
|
8000c84: d108 bne.n 8000c98 <HAL_UART_RxCpltCallback+0x24>
|
|
handleUARTMessages(UART1_RX_BUFF, huart);
|
|
8000c86: 6879 ldr r1, [r7, #4]
|
|
8000c88: 4806 ldr r0, [pc, #24] @ (8000ca4 <HAL_UART_RxCpltCallback+0x30>)
|
|
8000c8a: f000 f80d bl 8000ca8 <handleUARTMessages>
|
|
HAL_UART_Receive_DMA(huart, UART1_RX_BUFF, UART_RX_BUFF_SIZE);
|
|
8000c8e: 2240 movs r2, #64 @ 0x40
|
|
8000c90: 4904 ldr r1, [pc, #16] @ (8000ca4 <HAL_UART_RxCpltCallback+0x30>)
|
|
8000c92: 6878 ldr r0, [r7, #4]
|
|
8000c94: f004 f99a bl 8004fcc <HAL_UART_Receive_DMA>
|
|
}
|
|
}
|
|
8000c98: bf00 nop
|
|
8000c9a: 3708 adds r7, #8
|
|
8000c9c: 46bd mov sp, r7
|
|
8000c9e: bd80 pop {r7, pc}
|
|
8000ca0: 40011000 .word 0x40011000
|
|
8000ca4: 200003a0 .word 0x200003a0
|
|
|
|
08000ca8 <handleUARTMessages>:
|
|
|
|
void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender){
|
|
8000ca8: b580 push {r7, lr}
|
|
8000caa: b08c sub sp, #48 @ 0x30
|
|
8000cac: af00 add r7, sp, #0
|
|
8000cae: 6078 str r0, [r7, #4]
|
|
8000cb0: 6039 str r1, [r7, #0]
|
|
UARTMessage msg;
|
|
UARTMessage res;
|
|
|
|
// Parse incoming message
|
|
msg.depth = (data[0]<<8) | data[1];
|
|
8000cb2: 687b ldr r3, [r7, #4]
|
|
8000cb4: 781b ldrb r3, [r3, #0]
|
|
8000cb6: b21b sxth r3, r3
|
|
8000cb8: 021b lsls r3, r3, #8
|
|
8000cba: b21a sxth r2, r3
|
|
8000cbc: 687b ldr r3, [r7, #4]
|
|
8000cbe: 3301 adds r3, #1
|
|
8000cc0: 781b ldrb r3, [r3, #0]
|
|
8000cc2: b21b sxth r3, r3
|
|
8000cc4: 4313 orrs r3, r2
|
|
8000cc6: b21b sxth r3, r3
|
|
8000cc8: b29b uxth r3, r3
|
|
8000cca: 83bb strh r3, [r7, #28]
|
|
msg.msgType = (data[2]<<8) | data[3];
|
|
8000ccc: 687b ldr r3, [r7, #4]
|
|
8000cce: 3302 adds r3, #2
|
|
8000cd0: 781b ldrb r3, [r3, #0]
|
|
8000cd2: b21b sxth r3, r3
|
|
8000cd4: 021b lsls r3, r3, #8
|
|
8000cd6: b21a sxth r2, r3
|
|
8000cd8: 687b ldr r3, [r7, #4]
|
|
8000cda: 3303 adds r3, #3
|
|
8000cdc: 781b ldrb r3, [r3, #0]
|
|
8000cde: b21b sxth r3, r3
|
|
8000ce0: 4313 orrs r3, r2
|
|
8000ce2: b21b sxth r3, r3
|
|
8000ce4: b29b uxth r3, r3
|
|
8000ce6: 83fb strh r3, [r7, #30]
|
|
memcpy(msg.keypress, &data[4], 12);
|
|
8000ce8: 687b ldr r3, [r7, #4]
|
|
8000cea: 1d1a adds r2, r3, #4
|
|
8000cec: f107 0320 add.w r3, r7, #32
|
|
8000cf0: 6810 ldr r0, [r2, #0]
|
|
8000cf2: 6851 ldr r1, [r2, #4]
|
|
8000cf4: 6892 ldr r2, [r2, #8]
|
|
8000cf6: c307 stmia r3!, {r0, r1, r2}
|
|
|
|
switch(msg.msgType){
|
|
8000cf8: 8bfb ldrh r3, [r7, #30]
|
|
8000cfa: 2b01 cmp r3, #1
|
|
8000cfc: d002 beq.n 8000d04 <handleUARTMessages+0x5c>
|
|
8000cfe: 2b10 cmp r3, #16
|
|
8000d00: d01b beq.n 8000d3a <handleUARTMessages+0x92>
|
|
for (int i = 0; i < 12; i++) {
|
|
REPORT.KEYPRESS[i] |= msg.keypress[i];
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
8000d02: e037 b.n 8000d74 <handleUARTMessages+0xcc>
|
|
if (sender->gState == HAL_UART_STATE_READY) {
|
|
8000d04: 683b ldr r3, [r7, #0]
|
|
8000d06: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8000d0a: b2db uxtb r3, r3
|
|
8000d0c: 2b20 cmp r3, #32
|
|
8000d0e: d130 bne.n 8000d72 <handleUARTMessages+0xca>
|
|
res.depth = DEPTH;
|
|
8000d10: 4b1a ldr r3, [pc, #104] @ (8000d7c <handleUARTMessages+0xd4>)
|
|
8000d12: 881b ldrh r3, [r3, #0]
|
|
8000d14: 81bb strh r3, [r7, #12]
|
|
res.msgType = 0x10;
|
|
8000d16: 2310 movs r3, #16
|
|
8000d18: 81fb strh r3, [r7, #14]
|
|
memcpy(res.keypress, &REPORT.KEYPRESS, sizeof(REPORT.KEYPRESS));
|
|
8000d1a: 4a19 ldr r2, [pc, #100] @ (8000d80 <handleUARTMessages+0xd8>)
|
|
8000d1c: f107 0310 add.w r3, r7, #16
|
|
8000d20: 3202 adds r2, #2
|
|
8000d22: 6810 ldr r0, [r2, #0]
|
|
8000d24: 6851 ldr r1, [r2, #4]
|
|
8000d26: 6892 ldr r2, [r2, #8]
|
|
8000d28: c307 stmia r3!, {r0, r1, r2}
|
|
HAL_UART_Transmit_DMA(sender, (uint8_t *)&res, sizeof(res));
|
|
8000d2a: f107 030c add.w r3, r7, #12
|
|
8000d2e: 2210 movs r2, #16
|
|
8000d30: 4619 mov r1, r3
|
|
8000d32: 6838 ldr r0, [r7, #0]
|
|
8000d34: f004 f8ce bl 8004ed4 <HAL_UART_Transmit_DMA>
|
|
break;
|
|
8000d38: e01b b.n 8000d72 <handleUARTMessages+0xca>
|
|
for (int i = 0; i < 12; i++) {
|
|
8000d3a: 2300 movs r3, #0
|
|
8000d3c: 62fb str r3, [r7, #44] @ 0x2c
|
|
8000d3e: e014 b.n 8000d6a <handleUARTMessages+0xc2>
|
|
REPORT.KEYPRESS[i] |= msg.keypress[i];
|
|
8000d40: 4a0f ldr r2, [pc, #60] @ (8000d80 <handleUARTMessages+0xd8>)
|
|
8000d42: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8000d44: 4413 add r3, r2
|
|
8000d46: 3302 adds r3, #2
|
|
8000d48: 781a ldrb r2, [r3, #0]
|
|
8000d4a: f107 0120 add.w r1, r7, #32
|
|
8000d4e: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8000d50: 440b add r3, r1
|
|
8000d52: 781b ldrb r3, [r3, #0]
|
|
8000d54: 4313 orrs r3, r2
|
|
8000d56: b2d9 uxtb r1, r3
|
|
8000d58: 4a09 ldr r2, [pc, #36] @ (8000d80 <handleUARTMessages+0xd8>)
|
|
8000d5a: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8000d5c: 4413 add r3, r2
|
|
8000d5e: 3302 adds r3, #2
|
|
8000d60: 460a mov r2, r1
|
|
8000d62: 701a strb r2, [r3, #0]
|
|
for (int i = 0; i < 12; i++) {
|
|
8000d64: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8000d66: 3301 adds r3, #1
|
|
8000d68: 62fb str r3, [r7, #44] @ 0x2c
|
|
8000d6a: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8000d6c: 2b0b cmp r3, #11
|
|
8000d6e: dde7 ble.n 8000d40 <handleUARTMessages+0x98>
|
|
break;
|
|
8000d70: e000 b.n 8000d74 <handleUARTMessages+0xcc>
|
|
break;
|
|
8000d72: bf00 nop
|
|
}
|
|
8000d74: bf00 nop
|
|
8000d76: 3730 adds r7, #48 @ 0x30
|
|
8000d78: 46bd mov sp, r7
|
|
8000d7a: bd80 pop {r7, pc}
|
|
8000d7c: 200004ae .word 0x200004ae
|
|
8000d80: 200004a0 .word 0x200004a0
|
|
|
|
08000d84 <addUSBReport>:
|
|
void addUSBReport(uint8_t usageID){
|
|
8000d84: b480 push {r7}
|
|
8000d86: b085 sub sp, #20
|
|
8000d88: af00 add r7, sp, #0
|
|
8000d8a: 4603 mov r3, r0
|
|
8000d8c: 71fb strb r3, [r7, #7]
|
|
if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds
|
|
8000d8e: 79fb ldrb r3, [r7, #7]
|
|
8000d90: 2b03 cmp r3, #3
|
|
8000d92: d922 bls.n 8000dda <addUSBReport+0x56>
|
|
8000d94: 79fb ldrb r3, [r7, #7]
|
|
8000d96: 2b73 cmp r3, #115 @ 0x73
|
|
8000d98: d81f bhi.n 8000dda <addUSBReport+0x56>
|
|
uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit
|
|
8000d9a: 79fb ldrb r3, [r7, #7]
|
|
8000d9c: b29b uxth r3, r3
|
|
8000d9e: 3b04 subs r3, #4
|
|
8000da0: 81fb strh r3, [r7, #14]
|
|
uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array
|
|
8000da2: 89fb ldrh r3, [r7, #14]
|
|
8000da4: 08db lsrs r3, r3, #3
|
|
8000da6: b29b uxth r3, r3
|
|
8000da8: 737b strb r3, [r7, #13]
|
|
uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset
|
|
8000daa: 89fb ldrh r3, [r7, #14]
|
|
8000dac: b2db uxtb r3, r3
|
|
8000dae: f003 0307 and.w r3, r3, #7
|
|
8000db2: 733b strb r3, [r7, #12]
|
|
REPORT.KEYPRESS[byte_index] |= (1 << bit_offset);
|
|
8000db4: 7b7b ldrb r3, [r7, #13]
|
|
8000db6: 4a0c ldr r2, [pc, #48] @ (8000de8 <addUSBReport+0x64>)
|
|
8000db8: 4413 add r3, r2
|
|
8000dba: 789b ldrb r3, [r3, #2]
|
|
8000dbc: b25a sxtb r2, r3
|
|
8000dbe: 7b3b ldrb r3, [r7, #12]
|
|
8000dc0: 2101 movs r1, #1
|
|
8000dc2: fa01 f303 lsl.w r3, r1, r3
|
|
8000dc6: b25b sxtb r3, r3
|
|
8000dc8: 4313 orrs r3, r2
|
|
8000dca: b25a sxtb r2, r3
|
|
8000dcc: 7b7b ldrb r3, [r7, #13]
|
|
8000dce: b2d1 uxtb r1, r2
|
|
8000dd0: 4a05 ldr r2, [pc, #20] @ (8000de8 <addUSBReport+0x64>)
|
|
8000dd2: 4413 add r3, r2
|
|
8000dd4: 460a mov r2, r1
|
|
8000dd6: 709a strb r2, [r3, #2]
|
|
8000dd8: e000 b.n 8000ddc <addUSBReport+0x58>
|
|
if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds
|
|
8000dda: bf00 nop
|
|
}
|
|
8000ddc: 3714 adds r7, #20
|
|
8000dde: 46bd mov sp, r7
|
|
8000de0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000de4: 4770 bx lr
|
|
8000de6: bf00 nop
|
|
8000de8: 200004a0 .word 0x200004a0
|
|
|
|
08000dec <matrixScan>:
|
|
|
|
void matrixScan(void){
|
|
8000dec: b580 push {r7, lr}
|
|
8000dee: b082 sub sp, #8
|
|
8000df0: af00 add r7, sp, #0
|
|
for (uint8_t col = 0; col < COL; col++){
|
|
8000df2: 2300 movs r3, #0
|
|
8000df4: 71fb strb r3, [r7, #7]
|
|
8000df6: e042 b.n 8000e7e <matrixScan+0x92>
|
|
HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET);
|
|
8000df8: 79fb ldrb r3, [r7, #7]
|
|
8000dfa: 4a25 ldr r2, [pc, #148] @ (8000e90 <matrixScan+0xa4>)
|
|
8000dfc: f852 0033 ldr.w r0, [r2, r3, lsl #3]
|
|
8000e00: 79fb ldrb r3, [r7, #7]
|
|
8000e02: 4a23 ldr r2, [pc, #140] @ (8000e90 <matrixScan+0xa4>)
|
|
8000e04: 00db lsls r3, r3, #3
|
|
8000e06: 4413 add r3, r2
|
|
8000e08: 889b ldrh r3, [r3, #4]
|
|
8000e0a: 2201 movs r2, #1
|
|
8000e0c: 4619 mov r1, r3
|
|
8000e0e: f000 fef7 bl 8001c00 <HAL_GPIO_WritePin>
|
|
HAL_Delay(1);
|
|
8000e12: 2001 movs r0, #1
|
|
8000e14: f000 fb8c bl 8001530 <HAL_Delay>
|
|
for(uint8_t row = 0; row < ROW; row++){
|
|
8000e18: 2300 movs r3, #0
|
|
8000e1a: 71bb strb r3, [r7, #6]
|
|
8000e1c: e01c b.n 8000e58 <matrixScan+0x6c>
|
|
if(HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN)){
|
|
8000e1e: 79bb ldrb r3, [r7, #6]
|
|
8000e20: 4a1c ldr r2, [pc, #112] @ (8000e94 <matrixScan+0xa8>)
|
|
8000e22: f852 2033 ldr.w r2, [r2, r3, lsl #3]
|
|
8000e26: 79bb ldrb r3, [r7, #6]
|
|
8000e28: 491a ldr r1, [pc, #104] @ (8000e94 <matrixScan+0xa8>)
|
|
8000e2a: 00db lsls r3, r3, #3
|
|
8000e2c: 440b add r3, r1
|
|
8000e2e: 889b ldrh r3, [r3, #4]
|
|
8000e30: 4619 mov r1, r3
|
|
8000e32: 4610 mov r0, r2
|
|
8000e34: f000 fecc bl 8001bd0 <HAL_GPIO_ReadPin>
|
|
8000e38: 4603 mov r3, r0
|
|
8000e3a: 2b00 cmp r3, #0
|
|
8000e3c: d009 beq.n 8000e52 <matrixScan+0x66>
|
|
addUSBReport(KEYCODES[row][col]);
|
|
8000e3e: 79ba ldrb r2, [r7, #6]
|
|
8000e40: 79fb ldrb r3, [r7, #7]
|
|
8000e42: 4915 ldr r1, [pc, #84] @ (8000e98 <matrixScan+0xac>)
|
|
8000e44: 0052 lsls r2, r2, #1
|
|
8000e46: 440a add r2, r1
|
|
8000e48: 4413 add r3, r2
|
|
8000e4a: 781b ldrb r3, [r3, #0]
|
|
8000e4c: 4618 mov r0, r3
|
|
8000e4e: f7ff ff99 bl 8000d84 <addUSBReport>
|
|
for(uint8_t row = 0; row < ROW; row++){
|
|
8000e52: 79bb ldrb r3, [r7, #6]
|
|
8000e54: 3301 adds r3, #1
|
|
8000e56: 71bb strb r3, [r7, #6]
|
|
8000e58: 79bb ldrb r3, [r7, #6]
|
|
8000e5a: 2b01 cmp r3, #1
|
|
8000e5c: d9df bls.n 8000e1e <matrixScan+0x32>
|
|
}
|
|
}
|
|
HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET);
|
|
8000e5e: 79fb ldrb r3, [r7, #7]
|
|
8000e60: 4a0b ldr r2, [pc, #44] @ (8000e90 <matrixScan+0xa4>)
|
|
8000e62: f852 0033 ldr.w r0, [r2, r3, lsl #3]
|
|
8000e66: 79fb ldrb r3, [r7, #7]
|
|
8000e68: 4a09 ldr r2, [pc, #36] @ (8000e90 <matrixScan+0xa4>)
|
|
8000e6a: 00db lsls r3, r3, #3
|
|
8000e6c: 4413 add r3, r2
|
|
8000e6e: 889b ldrh r3, [r3, #4]
|
|
8000e70: 2200 movs r2, #0
|
|
8000e72: 4619 mov r1, r3
|
|
8000e74: f000 fec4 bl 8001c00 <HAL_GPIO_WritePin>
|
|
for (uint8_t col = 0; col < COL; col++){
|
|
8000e78: 79fb ldrb r3, [r7, #7]
|
|
8000e7a: 3301 adds r3, #1
|
|
8000e7c: 71fb strb r3, [r7, #7]
|
|
8000e7e: 79fb ldrb r3, [r7, #7]
|
|
8000e80: 2b01 cmp r3, #1
|
|
8000e82: d9b9 bls.n 8000df8 <matrixScan+0xc>
|
|
}
|
|
}
|
|
8000e84: bf00 nop
|
|
8000e86: bf00 nop
|
|
8000e88: 3708 adds r7, #8
|
|
8000e8a: 46bd mov sp, r7
|
|
8000e8c: bd80 pop {r7, pc}
|
|
8000e8e: bf00 nop
|
|
8000e90: 20000010 .word 0x20000010
|
|
8000e94: 20000000 .word 0x20000000
|
|
8000e98: 20000020 .word 0x20000020
|
|
|
|
08000e9c <resetReport>:
|
|
|
|
void resetReport(void){
|
|
8000e9c: b580 push {r7, lr}
|
|
8000e9e: af00 add r7, sp, #0
|
|
REPORT.MODIFIER = 0;
|
|
8000ea0: 4b04 ldr r3, [pc, #16] @ (8000eb4 <resetReport+0x18>)
|
|
8000ea2: 2200 movs r2, #0
|
|
8000ea4: 701a strb r2, [r3, #0]
|
|
memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS));
|
|
8000ea6: 220c movs r2, #12
|
|
8000ea8: 2100 movs r1, #0
|
|
8000eaa: 4803 ldr r0, [pc, #12] @ (8000eb8 <resetReport+0x1c>)
|
|
8000eac: f008 fb72 bl 8009594 <memset>
|
|
}
|
|
8000eb0: bf00 nop
|
|
8000eb2: bd80 pop {r7, pc}
|
|
8000eb4: 200004a0 .word 0x200004a0
|
|
8000eb8: 200004a2 .word 0x200004a2
|
|
|
|
08000ebc <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8000ebc: b480 push {r7}
|
|
8000ebe: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8000ec0: b672 cpsid i
|
|
}
|
|
8000ec2: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8000ec4: bf00 nop
|
|
8000ec6: e7fd b.n 8000ec4 <Error_Handler+0x8>
|
|
|
|
08000ec8 <HAL_MspInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8000ec8: b480 push {r7}
|
|
8000eca: b083 sub sp, #12
|
|
8000ecc: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8000ece: 2300 movs r3, #0
|
|
8000ed0: 607b str r3, [r7, #4]
|
|
8000ed2: 4b10 ldr r3, [pc, #64] @ (8000f14 <HAL_MspInit+0x4c>)
|
|
8000ed4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000ed6: 4a0f ldr r2, [pc, #60] @ (8000f14 <HAL_MspInit+0x4c>)
|
|
8000ed8: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8000edc: 6453 str r3, [r2, #68] @ 0x44
|
|
8000ede: 4b0d ldr r3, [pc, #52] @ (8000f14 <HAL_MspInit+0x4c>)
|
|
8000ee0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000ee2: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8000ee6: 607b str r3, [r7, #4]
|
|
8000ee8: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000eea: 2300 movs r3, #0
|
|
8000eec: 603b str r3, [r7, #0]
|
|
8000eee: 4b09 ldr r3, [pc, #36] @ (8000f14 <HAL_MspInit+0x4c>)
|
|
8000ef0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000ef2: 4a08 ldr r2, [pc, #32] @ (8000f14 <HAL_MspInit+0x4c>)
|
|
8000ef4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8000ef8: 6413 str r3, [r2, #64] @ 0x40
|
|
8000efa: 4b06 ldr r3, [pc, #24] @ (8000f14 <HAL_MspInit+0x4c>)
|
|
8000efc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000efe: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8000f02: 603b str r3, [r7, #0]
|
|
8000f04: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8000f06: bf00 nop
|
|
8000f08: 370c adds r7, #12
|
|
8000f0a: 46bd mov sp, r7
|
|
8000f0c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000f10: 4770 bx lr
|
|
8000f12: bf00 nop
|
|
8000f14: 40023800 .word 0x40023800
|
|
|
|
08000f18 <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
8000f18: b580 push {r7, lr}
|
|
8000f1a: b08a sub sp, #40 @ 0x28
|
|
8000f1c: af00 add r7, sp, #0
|
|
8000f1e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000f20: f107 0314 add.w r3, r7, #20
|
|
8000f24: 2200 movs r2, #0
|
|
8000f26: 601a str r2, [r3, #0]
|
|
8000f28: 605a str r2, [r3, #4]
|
|
8000f2a: 609a str r2, [r3, #8]
|
|
8000f2c: 60da str r2, [r3, #12]
|
|
8000f2e: 611a str r2, [r3, #16]
|
|
if(hi2c->Instance==I2C1)
|
|
8000f30: 687b ldr r3, [r7, #4]
|
|
8000f32: 681b ldr r3, [r3, #0]
|
|
8000f34: 4a19 ldr r2, [pc, #100] @ (8000f9c <HAL_I2C_MspInit+0x84>)
|
|
8000f36: 4293 cmp r3, r2
|
|
8000f38: d12b bne.n 8000f92 <HAL_I2C_MspInit+0x7a>
|
|
{
|
|
/* USER CODE BEGIN I2C1_MspInit 0 */
|
|
|
|
/* USER CODE END I2C1_MspInit 0 */
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000f3a: 2300 movs r3, #0
|
|
8000f3c: 613b str r3, [r7, #16]
|
|
8000f3e: 4b18 ldr r3, [pc, #96] @ (8000fa0 <HAL_I2C_MspInit+0x88>)
|
|
8000f40: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f42: 4a17 ldr r2, [pc, #92] @ (8000fa0 <HAL_I2C_MspInit+0x88>)
|
|
8000f44: f043 0302 orr.w r3, r3, #2
|
|
8000f48: 6313 str r3, [r2, #48] @ 0x30
|
|
8000f4a: 4b15 ldr r3, [pc, #84] @ (8000fa0 <HAL_I2C_MspInit+0x88>)
|
|
8000f4c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f4e: f003 0302 and.w r3, r3, #2
|
|
8000f52: 613b str r3, [r7, #16]
|
|
8000f54: 693b ldr r3, [r7, #16]
|
|
/**I2C1 GPIO Configuration
|
|
PB6 ------> I2C1_SCL
|
|
PB7 ------> I2C1_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
8000f56: 23c0 movs r3, #192 @ 0xc0
|
|
8000f58: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
8000f5a: 2312 movs r3, #18
|
|
8000f5c: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000f5e: 2300 movs r3, #0
|
|
8000f60: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8000f62: 2303 movs r3, #3
|
|
8000f64: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
|
|
8000f66: 2304 movs r3, #4
|
|
8000f68: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8000f6a: f107 0314 add.w r3, r7, #20
|
|
8000f6e: 4619 mov r1, r3
|
|
8000f70: 480c ldr r0, [pc, #48] @ (8000fa4 <HAL_I2C_MspInit+0x8c>)
|
|
8000f72: f000 fc99 bl 80018a8 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C1_CLK_ENABLE();
|
|
8000f76: 2300 movs r3, #0
|
|
8000f78: 60fb str r3, [r7, #12]
|
|
8000f7a: 4b09 ldr r3, [pc, #36] @ (8000fa0 <HAL_I2C_MspInit+0x88>)
|
|
8000f7c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000f7e: 4a08 ldr r2, [pc, #32] @ (8000fa0 <HAL_I2C_MspInit+0x88>)
|
|
8000f80: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8000f84: 6413 str r3, [r2, #64] @ 0x40
|
|
8000f86: 4b06 ldr r3, [pc, #24] @ (8000fa0 <HAL_I2C_MspInit+0x88>)
|
|
8000f88: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000f8a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8000f8e: 60fb str r3, [r7, #12]
|
|
8000f90: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END I2C1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000f92: bf00 nop
|
|
8000f94: 3728 adds r7, #40 @ 0x28
|
|
8000f96: 46bd mov sp, r7
|
|
8000f98: bd80 pop {r7, pc}
|
|
8000f9a: bf00 nop
|
|
8000f9c: 40005400 .word 0x40005400
|
|
8000fa0: 40023800 .word 0x40023800
|
|
8000fa4: 40020400 .word 0x40020400
|
|
|
|
08000fa8 <HAL_TIM_OC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_oc: TIM_OC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* htim_oc)
|
|
{
|
|
8000fa8: b480 push {r7}
|
|
8000faa: b085 sub sp, #20
|
|
8000fac: af00 add r7, sp, #0
|
|
8000fae: 6078 str r0, [r7, #4]
|
|
if(htim_oc->Instance==TIM2)
|
|
8000fb0: 687b ldr r3, [r7, #4]
|
|
8000fb2: 681b ldr r3, [r3, #0]
|
|
8000fb4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8000fb8: d10d bne.n 8000fd6 <HAL_TIM_OC_MspInit+0x2e>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
|
8000fba: 2300 movs r3, #0
|
|
8000fbc: 60fb str r3, [r7, #12]
|
|
8000fbe: 4b09 ldr r3, [pc, #36] @ (8000fe4 <HAL_TIM_OC_MspInit+0x3c>)
|
|
8000fc0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000fc2: 4a08 ldr r2, [pc, #32] @ (8000fe4 <HAL_TIM_OC_MspInit+0x3c>)
|
|
8000fc4: f043 0301 orr.w r3, r3, #1
|
|
8000fc8: 6413 str r3, [r2, #64] @ 0x40
|
|
8000fca: 4b06 ldr r3, [pc, #24] @ (8000fe4 <HAL_TIM_OC_MspInit+0x3c>)
|
|
8000fcc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000fce: f003 0301 and.w r3, r3, #1
|
|
8000fd2: 60fb str r3, [r7, #12]
|
|
8000fd4: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END TIM2_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000fd6: bf00 nop
|
|
8000fd8: 3714 adds r7, #20
|
|
8000fda: 46bd mov sp, r7
|
|
8000fdc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000fe0: 4770 bx lr
|
|
8000fe2: bf00 nop
|
|
8000fe4: 40023800 .word 0x40023800
|
|
|
|
08000fe8 <HAL_TIM_Encoder_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_encoder: TIM_Encoder handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
|
|
{
|
|
8000fe8: b580 push {r7, lr}
|
|
8000fea: b08a sub sp, #40 @ 0x28
|
|
8000fec: af00 add r7, sp, #0
|
|
8000fee: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000ff0: f107 0314 add.w r3, r7, #20
|
|
8000ff4: 2200 movs r2, #0
|
|
8000ff6: 601a str r2, [r3, #0]
|
|
8000ff8: 605a str r2, [r3, #4]
|
|
8000ffa: 609a str r2, [r3, #8]
|
|
8000ffc: 60da str r2, [r3, #12]
|
|
8000ffe: 611a str r2, [r3, #16]
|
|
if(htim_encoder->Instance==TIM3)
|
|
8001000: 687b ldr r3, [r7, #4]
|
|
8001002: 681b ldr r3, [r3, #0]
|
|
8001004: 4a19 ldr r2, [pc, #100] @ (800106c <HAL_TIM_Encoder_MspInit+0x84>)
|
|
8001006: 4293 cmp r3, r2
|
|
8001008: d12b bne.n 8001062 <HAL_TIM_Encoder_MspInit+0x7a>
|
|
{
|
|
/* USER CODE BEGIN TIM3_MspInit 0 */
|
|
|
|
/* USER CODE END TIM3_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
800100a: 2300 movs r3, #0
|
|
800100c: 613b str r3, [r7, #16]
|
|
800100e: 4b18 ldr r3, [pc, #96] @ (8001070 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001010: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001012: 4a17 ldr r2, [pc, #92] @ (8001070 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001014: f043 0302 orr.w r3, r3, #2
|
|
8001018: 6413 str r3, [r2, #64] @ 0x40
|
|
800101a: 4b15 ldr r3, [pc, #84] @ (8001070 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
800101c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800101e: f003 0302 and.w r3, r3, #2
|
|
8001022: 613b str r3, [r7, #16]
|
|
8001024: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001026: 2300 movs r3, #0
|
|
8001028: 60fb str r3, [r7, #12]
|
|
800102a: 4b11 ldr r3, [pc, #68] @ (8001070 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
800102c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800102e: 4a10 ldr r2, [pc, #64] @ (8001070 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001030: f043 0301 orr.w r3, r3, #1
|
|
8001034: 6313 str r3, [r2, #48] @ 0x30
|
|
8001036: 4b0e ldr r3, [pc, #56] @ (8001070 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001038: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800103a: f003 0301 and.w r3, r3, #1
|
|
800103e: 60fb str r3, [r7, #12]
|
|
8001040: 68fb ldr r3, [r7, #12]
|
|
/**TIM3 GPIO Configuration
|
|
PA6 ------> TIM3_CH1
|
|
PA7 ------> TIM3_CH2
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
8001042: 23c0 movs r3, #192 @ 0xc0
|
|
8001044: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001046: 2302 movs r3, #2
|
|
8001048: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800104a: 2300 movs r3, #0
|
|
800104c: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800104e: 2300 movs r3, #0
|
|
8001050: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
|
|
8001052: 2302 movs r3, #2
|
|
8001054: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001056: f107 0314 add.w r3, r7, #20
|
|
800105a: 4619 mov r1, r3
|
|
800105c: 4805 ldr r0, [pc, #20] @ (8001074 <HAL_TIM_Encoder_MspInit+0x8c>)
|
|
800105e: f000 fc23 bl 80018a8 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END TIM3_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8001062: bf00 nop
|
|
8001064: 3728 adds r7, #40 @ 0x28
|
|
8001066: 46bd mov sp, r7
|
|
8001068: bd80 pop {r7, pc}
|
|
800106a: bf00 nop
|
|
800106c: 40000400 .word 0x40000400
|
|
8001070: 40023800 .word 0x40023800
|
|
8001074: 40020000 .word 0x40020000
|
|
|
|
08001078 <HAL_TIM_MspPostInit>:
|
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
|
{
|
|
8001078: b580 push {r7, lr}
|
|
800107a: b088 sub sp, #32
|
|
800107c: af00 add r7, sp, #0
|
|
800107e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001080: f107 030c add.w r3, r7, #12
|
|
8001084: 2200 movs r2, #0
|
|
8001086: 601a str r2, [r3, #0]
|
|
8001088: 605a str r2, [r3, #4]
|
|
800108a: 609a str r2, [r3, #8]
|
|
800108c: 60da str r2, [r3, #12]
|
|
800108e: 611a str r2, [r3, #16]
|
|
if(htim->Instance==TIM2)
|
|
8001090: 687b ldr r3, [r7, #4]
|
|
8001092: 681b ldr r3, [r3, #0]
|
|
8001094: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8001098: d11d bne.n 80010d6 <HAL_TIM_MspPostInit+0x5e>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 0 */
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800109a: 2300 movs r3, #0
|
|
800109c: 60bb str r3, [r7, #8]
|
|
800109e: 4b10 ldr r3, [pc, #64] @ (80010e0 <HAL_TIM_MspPostInit+0x68>)
|
|
80010a0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80010a2: 4a0f ldr r2, [pc, #60] @ (80010e0 <HAL_TIM_MspPostInit+0x68>)
|
|
80010a4: f043 0301 orr.w r3, r3, #1
|
|
80010a8: 6313 str r3, [r2, #48] @ 0x30
|
|
80010aa: 4b0d ldr r3, [pc, #52] @ (80010e0 <HAL_TIM_MspPostInit+0x68>)
|
|
80010ac: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80010ae: f003 0301 and.w r3, r3, #1
|
|
80010b2: 60bb str r3, [r7, #8]
|
|
80010b4: 68bb ldr r3, [r7, #8]
|
|
/**TIM2 GPIO Configuration
|
|
PA5 ------> TIM2_CH1
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_5;
|
|
80010b6: 2320 movs r3, #32
|
|
80010b8: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80010ba: 2302 movs r3, #2
|
|
80010bc: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80010be: 2300 movs r3, #0
|
|
80010c0: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80010c2: 2300 movs r3, #0
|
|
80010c4: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
|
|
80010c6: 2301 movs r3, #1
|
|
80010c8: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80010ca: f107 030c add.w r3, r7, #12
|
|
80010ce: 4619 mov r1, r3
|
|
80010d0: 4804 ldr r0, [pc, #16] @ (80010e4 <HAL_TIM_MspPostInit+0x6c>)
|
|
80010d2: f000 fbe9 bl 80018a8 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM2_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
80010d6: bf00 nop
|
|
80010d8: 3720 adds r7, #32
|
|
80010da: 46bd mov sp, r7
|
|
80010dc: bd80 pop {r7, pc}
|
|
80010de: bf00 nop
|
|
80010e0: 40023800 .word 0x40023800
|
|
80010e4: 40020000 .word 0x40020000
|
|
|
|
080010e8 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
80010e8: b580 push {r7, lr}
|
|
80010ea: b092 sub sp, #72 @ 0x48
|
|
80010ec: af00 add r7, sp, #0
|
|
80010ee: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80010f0: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
80010f4: 2200 movs r2, #0
|
|
80010f6: 601a str r2, [r3, #0]
|
|
80010f8: 605a str r2, [r3, #4]
|
|
80010fa: 609a str r2, [r3, #8]
|
|
80010fc: 60da str r2, [r3, #12]
|
|
80010fe: 611a str r2, [r3, #16]
|
|
if(huart->Instance==UART4)
|
|
8001100: 687b ldr r3, [r7, #4]
|
|
8001102: 681b ldr r3, [r3, #0]
|
|
8001104: 4a8d ldr r2, [pc, #564] @ (800133c <HAL_UART_MspInit+0x254>)
|
|
8001106: 4293 cmp r3, r2
|
|
8001108: d12c bne.n 8001164 <HAL_UART_MspInit+0x7c>
|
|
{
|
|
/* USER CODE BEGIN UART4_MspInit 0 */
|
|
|
|
/* USER CODE END UART4_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_UART4_CLK_ENABLE();
|
|
800110a: 2300 movs r3, #0
|
|
800110c: 633b str r3, [r7, #48] @ 0x30
|
|
800110e: 4b8c ldr r3, [pc, #560] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001110: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001112: 4a8b ldr r2, [pc, #556] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001114: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8001118: 6413 str r3, [r2, #64] @ 0x40
|
|
800111a: 4b89 ldr r3, [pc, #548] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
800111c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800111e: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8001122: 633b str r3, [r7, #48] @ 0x30
|
|
8001124: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001126: 2300 movs r3, #0
|
|
8001128: 62fb str r3, [r7, #44] @ 0x2c
|
|
800112a: 4b85 ldr r3, [pc, #532] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
800112c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800112e: 4a84 ldr r2, [pc, #528] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001130: f043 0301 orr.w r3, r3, #1
|
|
8001134: 6313 str r3, [r2, #48] @ 0x30
|
|
8001136: 4b82 ldr r3, [pc, #520] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001138: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800113a: f003 0301 and.w r3, r3, #1
|
|
800113e: 62fb str r3, [r7, #44] @ 0x2c
|
|
8001140: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
/**UART4 GPIO Configuration
|
|
PA0-WKUP ------> UART4_TX
|
|
PA1 ------> UART4_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
|
|
8001142: 2303 movs r3, #3
|
|
8001144: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001146: 2302 movs r3, #2
|
|
8001148: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800114a: 2300 movs r3, #0
|
|
800114c: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800114e: 2303 movs r3, #3
|
|
8001150: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
|
|
8001152: 2308 movs r3, #8
|
|
8001154: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001156: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
800115a: 4619 mov r1, r3
|
|
800115c: 4879 ldr r0, [pc, #484] @ (8001344 <HAL_UART_MspInit+0x25c>)
|
|
800115e: f000 fba3 bl 80018a8 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN USART3_MspInit 1 */
|
|
|
|
/* USER CODE END USART3_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8001162: e0e7 b.n 8001334 <HAL_UART_MspInit+0x24c>
|
|
else if(huart->Instance==UART5)
|
|
8001164: 687b ldr r3, [r7, #4]
|
|
8001166: 681b ldr r3, [r3, #0]
|
|
8001168: 4a77 ldr r2, [pc, #476] @ (8001348 <HAL_UART_MspInit+0x260>)
|
|
800116a: 4293 cmp r3, r2
|
|
800116c: d14b bne.n 8001206 <HAL_UART_MspInit+0x11e>
|
|
__HAL_RCC_UART5_CLK_ENABLE();
|
|
800116e: 2300 movs r3, #0
|
|
8001170: 62bb str r3, [r7, #40] @ 0x28
|
|
8001172: 4b73 ldr r3, [pc, #460] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001174: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001176: 4a72 ldr r2, [pc, #456] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001178: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
800117c: 6413 str r3, [r2, #64] @ 0x40
|
|
800117e: 4b70 ldr r3, [pc, #448] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001180: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001182: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8001186: 62bb str r3, [r7, #40] @ 0x28
|
|
8001188: 6abb ldr r3, [r7, #40] @ 0x28
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
800118a: 2300 movs r3, #0
|
|
800118c: 627b str r3, [r7, #36] @ 0x24
|
|
800118e: 4b6c ldr r3, [pc, #432] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001190: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001192: 4a6b ldr r2, [pc, #428] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001194: f043 0304 orr.w r3, r3, #4
|
|
8001198: 6313 str r3, [r2, #48] @ 0x30
|
|
800119a: 4b69 ldr r3, [pc, #420] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
800119c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800119e: f003 0304 and.w r3, r3, #4
|
|
80011a2: 627b str r3, [r7, #36] @ 0x24
|
|
80011a4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
80011a6: 2300 movs r3, #0
|
|
80011a8: 623b str r3, [r7, #32]
|
|
80011aa: 4b65 ldr r3, [pc, #404] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
80011ac: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80011ae: 4a64 ldr r2, [pc, #400] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
80011b0: f043 0308 orr.w r3, r3, #8
|
|
80011b4: 6313 str r3, [r2, #48] @ 0x30
|
|
80011b6: 4b62 ldr r3, [pc, #392] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
80011b8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80011ba: f003 0308 and.w r3, r3, #8
|
|
80011be: 623b str r3, [r7, #32]
|
|
80011c0: 6a3b ldr r3, [r7, #32]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_12;
|
|
80011c2: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
80011c6: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80011c8: 2302 movs r3, #2
|
|
80011ca: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80011cc: 2300 movs r3, #0
|
|
80011ce: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80011d0: 2303 movs r3, #3
|
|
80011d2: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
|
|
80011d4: 2308 movs r3, #8
|
|
80011d6: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80011d8: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
80011dc: 4619 mov r1, r3
|
|
80011de: 485b ldr r0, [pc, #364] @ (800134c <HAL_UART_MspInit+0x264>)
|
|
80011e0: f000 fb62 bl 80018a8 <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
80011e4: 2304 movs r3, #4
|
|
80011e6: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80011e8: 2302 movs r3, #2
|
|
80011ea: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80011ec: 2300 movs r3, #0
|
|
80011ee: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80011f0: 2303 movs r3, #3
|
|
80011f2: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
|
|
80011f4: 2308 movs r3, #8
|
|
80011f6: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
80011f8: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
80011fc: 4619 mov r1, r3
|
|
80011fe: 4854 ldr r0, [pc, #336] @ (8001350 <HAL_UART_MspInit+0x268>)
|
|
8001200: f000 fb52 bl 80018a8 <HAL_GPIO_Init>
|
|
}
|
|
8001204: e096 b.n 8001334 <HAL_UART_MspInit+0x24c>
|
|
else if(huart->Instance==USART1)
|
|
8001206: 687b ldr r3, [r7, #4]
|
|
8001208: 681b ldr r3, [r3, #0]
|
|
800120a: 4a52 ldr r2, [pc, #328] @ (8001354 <HAL_UART_MspInit+0x26c>)
|
|
800120c: 4293 cmp r3, r2
|
|
800120e: d12d bne.n 800126c <HAL_UART_MspInit+0x184>
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8001210: 2300 movs r3, #0
|
|
8001212: 61fb str r3, [r7, #28]
|
|
8001214: 4b4a ldr r3, [pc, #296] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001216: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001218: 4a49 ldr r2, [pc, #292] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
800121a: f043 0310 orr.w r3, r3, #16
|
|
800121e: 6453 str r3, [r2, #68] @ 0x44
|
|
8001220: 4b47 ldr r3, [pc, #284] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001222: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001224: f003 0310 and.w r3, r3, #16
|
|
8001228: 61fb str r3, [r7, #28]
|
|
800122a: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800122c: 2300 movs r3, #0
|
|
800122e: 61bb str r3, [r7, #24]
|
|
8001230: 4b43 ldr r3, [pc, #268] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001232: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001234: 4a42 ldr r2, [pc, #264] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001236: f043 0301 orr.w r3, r3, #1
|
|
800123a: 6313 str r3, [r2, #48] @ 0x30
|
|
800123c: 4b40 ldr r3, [pc, #256] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
800123e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001240: f003 0301 and.w r3, r3, #1
|
|
8001244: 61bb str r3, [r7, #24]
|
|
8001246: 69bb ldr r3, [r7, #24]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
|
|
8001248: f44f 63c0 mov.w r3, #1536 @ 0x600
|
|
800124c: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800124e: 2302 movs r3, #2
|
|
8001250: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001252: 2300 movs r3, #0
|
|
8001254: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001256: 2303 movs r3, #3
|
|
8001258: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
800125a: 2307 movs r3, #7
|
|
800125c: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800125e: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8001262: 4619 mov r1, r3
|
|
8001264: 4837 ldr r0, [pc, #220] @ (8001344 <HAL_UART_MspInit+0x25c>)
|
|
8001266: f000 fb1f bl 80018a8 <HAL_GPIO_Init>
|
|
}
|
|
800126a: e063 b.n 8001334 <HAL_UART_MspInit+0x24c>
|
|
else if(huart->Instance==USART2)
|
|
800126c: 687b ldr r3, [r7, #4]
|
|
800126e: 681b ldr r3, [r3, #0]
|
|
8001270: 4a39 ldr r2, [pc, #228] @ (8001358 <HAL_UART_MspInit+0x270>)
|
|
8001272: 4293 cmp r3, r2
|
|
8001274: d12c bne.n 80012d0 <HAL_UART_MspInit+0x1e8>
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
8001276: 2300 movs r3, #0
|
|
8001278: 617b str r3, [r7, #20]
|
|
800127a: 4b31 ldr r3, [pc, #196] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
800127c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800127e: 4a30 ldr r2, [pc, #192] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001280: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8001284: 6413 str r3, [r2, #64] @ 0x40
|
|
8001286: 4b2e ldr r3, [pc, #184] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001288: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800128a: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800128e: 617b str r3, [r7, #20]
|
|
8001290: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001292: 2300 movs r3, #0
|
|
8001294: 613b str r3, [r7, #16]
|
|
8001296: 4b2a ldr r3, [pc, #168] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001298: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800129a: 4a29 ldr r2, [pc, #164] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
800129c: f043 0301 orr.w r3, r3, #1
|
|
80012a0: 6313 str r3, [r2, #48] @ 0x30
|
|
80012a2: 4b27 ldr r3, [pc, #156] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
80012a4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80012a6: f003 0301 and.w r3, r3, #1
|
|
80012aa: 613b str r3, [r7, #16]
|
|
80012ac: 693b ldr r3, [r7, #16]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
|
|
80012ae: 230c movs r3, #12
|
|
80012b0: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80012b2: 2302 movs r3, #2
|
|
80012b4: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80012b6: 2300 movs r3, #0
|
|
80012b8: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80012ba: 2303 movs r3, #3
|
|
80012bc: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
|
80012be: 2307 movs r3, #7
|
|
80012c0: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80012c2: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
80012c6: 4619 mov r1, r3
|
|
80012c8: 481e ldr r0, [pc, #120] @ (8001344 <HAL_UART_MspInit+0x25c>)
|
|
80012ca: f000 faed bl 80018a8 <HAL_GPIO_Init>
|
|
}
|
|
80012ce: e031 b.n 8001334 <HAL_UART_MspInit+0x24c>
|
|
else if(huart->Instance==USART3)
|
|
80012d0: 687b ldr r3, [r7, #4]
|
|
80012d2: 681b ldr r3, [r3, #0]
|
|
80012d4: 4a21 ldr r2, [pc, #132] @ (800135c <HAL_UART_MspInit+0x274>)
|
|
80012d6: 4293 cmp r3, r2
|
|
80012d8: d12c bne.n 8001334 <HAL_UART_MspInit+0x24c>
|
|
__HAL_RCC_USART3_CLK_ENABLE();
|
|
80012da: 2300 movs r3, #0
|
|
80012dc: 60fb str r3, [r7, #12]
|
|
80012de: 4b18 ldr r3, [pc, #96] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
80012e0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80012e2: 4a17 ldr r2, [pc, #92] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
80012e4: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
80012e8: 6413 str r3, [r2, #64] @ 0x40
|
|
80012ea: 4b15 ldr r3, [pc, #84] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
80012ec: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80012ee: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
80012f2: 60fb str r3, [r7, #12]
|
|
80012f4: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
80012f6: 2300 movs r3, #0
|
|
80012f8: 60bb str r3, [r7, #8]
|
|
80012fa: 4b11 ldr r3, [pc, #68] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
80012fc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80012fe: 4a10 ldr r2, [pc, #64] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001300: f043 0304 orr.w r3, r3, #4
|
|
8001304: 6313 str r3, [r2, #48] @ 0x30
|
|
8001306: 4b0e ldr r3, [pc, #56] @ (8001340 <HAL_UART_MspInit+0x258>)
|
|
8001308: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800130a: f003 0304 and.w r3, r3, #4
|
|
800130e: 60bb str r3, [r7, #8]
|
|
8001310: 68bb ldr r3, [r7, #8]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
|
|
8001312: f44f 6340 mov.w r3, #3072 @ 0xc00
|
|
8001316: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001318: 2302 movs r3, #2
|
|
800131a: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800131c: 2300 movs r3, #0
|
|
800131e: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001320: 2303 movs r3, #3
|
|
8001322: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
|
|
8001324: 2307 movs r3, #7
|
|
8001326: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8001328: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
800132c: 4619 mov r1, r3
|
|
800132e: 4807 ldr r0, [pc, #28] @ (800134c <HAL_UART_MspInit+0x264>)
|
|
8001330: f000 faba bl 80018a8 <HAL_GPIO_Init>
|
|
}
|
|
8001334: bf00 nop
|
|
8001336: 3748 adds r7, #72 @ 0x48
|
|
8001338: 46bd mov sp, r7
|
|
800133a: bd80 pop {r7, pc}
|
|
800133c: 40004c00 .word 0x40004c00
|
|
8001340: 40023800 .word 0x40023800
|
|
8001344: 40020000 .word 0x40020000
|
|
8001348: 40005000 .word 0x40005000
|
|
800134c: 40020800 .word 0x40020800
|
|
8001350: 40020c00 .word 0x40020c00
|
|
8001354: 40011000 .word 0x40011000
|
|
8001358: 40004400 .word 0x40004400
|
|
800135c: 40004800 .word 0x40004800
|
|
|
|
08001360 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8001360: b480 push {r7}
|
|
8001362: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8001364: bf00 nop
|
|
8001366: e7fd b.n 8001364 <NMI_Handler+0x4>
|
|
|
|
08001368 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8001368: b480 push {r7}
|
|
800136a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
800136c: bf00 nop
|
|
800136e: e7fd b.n 800136c <HardFault_Handler+0x4>
|
|
|
|
08001370 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8001370: b480 push {r7}
|
|
8001372: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8001374: bf00 nop
|
|
8001376: e7fd b.n 8001374 <MemManage_Handler+0x4>
|
|
|
|
08001378 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pre-fetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8001378: b480 push {r7}
|
|
800137a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
800137c: bf00 nop
|
|
800137e: e7fd b.n 800137c <BusFault_Handler+0x4>
|
|
|
|
08001380 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8001380: b480 push {r7}
|
|
8001382: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8001384: bf00 nop
|
|
8001386: e7fd b.n 8001384 <UsageFault_Handler+0x4>
|
|
|
|
08001388 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8001388: b480 push {r7}
|
|
800138a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
800138c: bf00 nop
|
|
800138e: 46bd mov sp, r7
|
|
8001390: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001394: 4770 bx lr
|
|
|
|
08001396 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8001396: b480 push {r7}
|
|
8001398: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
800139a: bf00 nop
|
|
800139c: 46bd mov sp, r7
|
|
800139e: f85d 7b04 ldr.w r7, [sp], #4
|
|
80013a2: 4770 bx lr
|
|
|
|
080013a4 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
80013a4: b480 push {r7}
|
|
80013a6: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
80013a8: bf00 nop
|
|
80013aa: 46bd mov sp, r7
|
|
80013ac: f85d 7b04 ldr.w r7, [sp], #4
|
|
80013b0: 4770 bx lr
|
|
|
|
080013b2 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
80013b2: b580 push {r7, lr}
|
|
80013b4: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
80013b6: f000 f89b bl 80014f0 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
80013ba: bf00 nop
|
|
80013bc: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080013c0 <OTG_FS_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USB On The Go FS global interrupt.
|
|
*/
|
|
void OTG_FS_IRQHandler(void)
|
|
{
|
|
80013c0: b580 push {r7, lr}
|
|
80013c2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN OTG_FS_IRQn 0 */
|
|
|
|
/* USER CODE END OTG_FS_IRQn 0 */
|
|
HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
|
|
80013c4: 4802 ldr r0, [pc, #8] @ (80013d0 <OTG_FS_IRQHandler+0x10>)
|
|
80013c6: f000 fec4 bl 8002152 <HAL_PCD_IRQHandler>
|
|
/* USER CODE BEGIN OTG_FS_IRQn 1 */
|
|
|
|
/* USER CODE END OTG_FS_IRQn 1 */
|
|
}
|
|
80013ca: bf00 nop
|
|
80013cc: bd80 pop {r7, pc}
|
|
80013ce: bf00 nop
|
|
80013d0: 20000994 .word 0x20000994
|
|
|
|
080013d4 <SystemInit>:
|
|
* configuration.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
80013d4: b480 push {r7}
|
|
80013d6: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
80013d8: 4b06 ldr r3, [pc, #24] @ (80013f4 <SystemInit+0x20>)
|
|
80013da: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80013de: 4a05 ldr r2, [pc, #20] @ (80013f4 <SystemInit+0x20>)
|
|
80013e0: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
80013e4: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
80013e8: bf00 nop
|
|
80013ea: 46bd mov sp, r7
|
|
80013ec: f85d 7b04 ldr.w r7, [sp], #4
|
|
80013f0: 4770 bx lr
|
|
80013f2: bf00 nop
|
|
80013f4: e000ed00 .word 0xe000ed00
|
|
|
|
080013f8 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* set stack pointer */
|
|
80013f8: f8df d034 ldr.w sp, [pc, #52] @ 8001430 <LoopFillZerobss+0xe>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
80013fc: f7ff ffea bl 80013d4 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8001400: 480c ldr r0, [pc, #48] @ (8001434 <LoopFillZerobss+0x12>)
|
|
ldr r1, =_edata
|
|
8001402: 490d ldr r1, [pc, #52] @ (8001438 <LoopFillZerobss+0x16>)
|
|
ldr r2, =_sidata
|
|
8001404: 4a0d ldr r2, [pc, #52] @ (800143c <LoopFillZerobss+0x1a>)
|
|
movs r3, #0
|
|
8001406: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
8001408: e002 b.n 8001410 <LoopCopyDataInit>
|
|
|
|
0800140a <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
800140a: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
800140c: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
800140e: 3304 adds r3, #4
|
|
|
|
08001410 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8001410: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8001412: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8001414: d3f9 bcc.n 800140a <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
8001416: 4a0a ldr r2, [pc, #40] @ (8001440 <LoopFillZerobss+0x1e>)
|
|
ldr r4, =_ebss
|
|
8001418: 4c0a ldr r4, [pc, #40] @ (8001444 <LoopFillZerobss+0x22>)
|
|
movs r3, #0
|
|
800141a: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
800141c: e001 b.n 8001422 <LoopFillZerobss>
|
|
|
|
0800141e <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
800141e: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8001420: 3204 adds r2, #4
|
|
|
|
08001422 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8001422: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8001424: d3fb bcc.n 800141e <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8001426: f008 f8bd bl 80095a4 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
800142a: f7ff f881 bl 8000530 <main>
|
|
bx lr
|
|
800142e: 4770 bx lr
|
|
ldr sp, =_estack /* set stack pointer */
|
|
8001430: 20020000 .word 0x20020000
|
|
ldr r0, =_sdata
|
|
8001434: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
8001438: 20000138 .word 0x20000138
|
|
ldr r2, =_sidata
|
|
800143c: 08009668 .word 0x08009668
|
|
ldr r2, =_sbss
|
|
8001440: 20000138 .word 0x20000138
|
|
ldr r4, =_ebss
|
|
8001444: 20000e8c .word 0x20000e8c
|
|
|
|
08001448 <ADC_IRQHandler>:
|
|
* @retval None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8001448: e7fe b.n 8001448 <ADC_IRQHandler>
|
|
...
|
|
|
|
0800144c <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
800144c: b580 push {r7, lr}
|
|
800144e: af00 add r7, sp, #0
|
|
/* Configure Flash prefetch, Instruction cache, Data cache */
|
|
#if (INSTRUCTION_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
|
|
8001450: 4b0e ldr r3, [pc, #56] @ (800148c <HAL_Init+0x40>)
|
|
8001452: 681b ldr r3, [r3, #0]
|
|
8001454: 4a0d ldr r2, [pc, #52] @ (800148c <HAL_Init+0x40>)
|
|
8001456: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
800145a: 6013 str r3, [r2, #0]
|
|
#endif /* INSTRUCTION_CACHE_ENABLE */
|
|
|
|
#if (DATA_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_DATA_CACHE_ENABLE();
|
|
800145c: 4b0b ldr r3, [pc, #44] @ (800148c <HAL_Init+0x40>)
|
|
800145e: 681b ldr r3, [r3, #0]
|
|
8001460: 4a0a ldr r2, [pc, #40] @ (800148c <HAL_Init+0x40>)
|
|
8001462: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8001466: 6013 str r3, [r2, #0]
|
|
#endif /* DATA_CACHE_ENABLE */
|
|
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
8001468: 4b08 ldr r3, [pc, #32] @ (800148c <HAL_Init+0x40>)
|
|
800146a: 681b ldr r3, [r3, #0]
|
|
800146c: 4a07 ldr r2, [pc, #28] @ (800148c <HAL_Init+0x40>)
|
|
800146e: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8001472: 6013 str r3, [r2, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8001474: 2003 movs r0, #3
|
|
8001476: f000 f94f bl 8001718 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
800147a: 200f movs r0, #15
|
|
800147c: f000 f808 bl 8001490 <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8001480: f7ff fd22 bl 8000ec8 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8001484: 2300 movs r3, #0
|
|
}
|
|
8001486: 4618 mov r0, r3
|
|
8001488: bd80 pop {r7, pc}
|
|
800148a: bf00 nop
|
|
800148c: 40023c00 .word 0x40023c00
|
|
|
|
08001490 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8001490: b580 push {r7, lr}
|
|
8001492: b082 sub sp, #8
|
|
8001494: af00 add r7, sp, #0
|
|
8001496: 6078 str r0, [r7, #4]
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
8001498: 4b12 ldr r3, [pc, #72] @ (80014e4 <HAL_InitTick+0x54>)
|
|
800149a: 681a ldr r2, [r3, #0]
|
|
800149c: 4b12 ldr r3, [pc, #72] @ (80014e8 <HAL_InitTick+0x58>)
|
|
800149e: 781b ldrb r3, [r3, #0]
|
|
80014a0: 4619 mov r1, r3
|
|
80014a2: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
80014a6: fbb3 f3f1 udiv r3, r3, r1
|
|
80014aa: fbb2 f3f3 udiv r3, r2, r3
|
|
80014ae: 4618 mov r0, r3
|
|
80014b0: f000 f967 bl 8001782 <HAL_SYSTICK_Config>
|
|
80014b4: 4603 mov r3, r0
|
|
80014b6: 2b00 cmp r3, #0
|
|
80014b8: d001 beq.n 80014be <HAL_InitTick+0x2e>
|
|
{
|
|
return HAL_ERROR;
|
|
80014ba: 2301 movs r3, #1
|
|
80014bc: e00e b.n 80014dc <HAL_InitTick+0x4c>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
80014be: 687b ldr r3, [r7, #4]
|
|
80014c0: 2b0f cmp r3, #15
|
|
80014c2: d80a bhi.n 80014da <HAL_InitTick+0x4a>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
80014c4: 2200 movs r2, #0
|
|
80014c6: 6879 ldr r1, [r7, #4]
|
|
80014c8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80014cc: f000 f92f bl 800172e <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
80014d0: 4a06 ldr r2, [pc, #24] @ (80014ec <HAL_InitTick+0x5c>)
|
|
80014d2: 687b ldr r3, [r7, #4]
|
|
80014d4: 6013 str r3, [r2, #0]
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80014d6: 2300 movs r3, #0
|
|
80014d8: e000 b.n 80014dc <HAL_InitTick+0x4c>
|
|
return HAL_ERROR;
|
|
80014da: 2301 movs r3, #1
|
|
}
|
|
80014dc: 4618 mov r0, r3
|
|
80014de: 3708 adds r7, #8
|
|
80014e0: 46bd mov sp, r7
|
|
80014e2: bd80 pop {r7, pc}
|
|
80014e4: 20000028 .word 0x20000028
|
|
80014e8: 20000030 .word 0x20000030
|
|
80014ec: 2000002c .word 0x2000002c
|
|
|
|
080014f0 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
80014f0: b480 push {r7}
|
|
80014f2: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
80014f4: 4b06 ldr r3, [pc, #24] @ (8001510 <HAL_IncTick+0x20>)
|
|
80014f6: 781b ldrb r3, [r3, #0]
|
|
80014f8: 461a mov r2, r3
|
|
80014fa: 4b06 ldr r3, [pc, #24] @ (8001514 <HAL_IncTick+0x24>)
|
|
80014fc: 681b ldr r3, [r3, #0]
|
|
80014fe: 4413 add r3, r2
|
|
8001500: 4a04 ldr r2, [pc, #16] @ (8001514 <HAL_IncTick+0x24>)
|
|
8001502: 6013 str r3, [r2, #0]
|
|
}
|
|
8001504: bf00 nop
|
|
8001506: 46bd mov sp, r7
|
|
8001508: f85d 7b04 ldr.w r7, [sp], #4
|
|
800150c: 4770 bx lr
|
|
800150e: bf00 nop
|
|
8001510: 20000030 .word 0x20000030
|
|
8001514: 200004b0 .word 0x200004b0
|
|
|
|
08001518 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8001518: b480 push {r7}
|
|
800151a: af00 add r7, sp, #0
|
|
return uwTick;
|
|
800151c: 4b03 ldr r3, [pc, #12] @ (800152c <HAL_GetTick+0x14>)
|
|
800151e: 681b ldr r3, [r3, #0]
|
|
}
|
|
8001520: 4618 mov r0, r3
|
|
8001522: 46bd mov sp, r7
|
|
8001524: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001528: 4770 bx lr
|
|
800152a: bf00 nop
|
|
800152c: 200004b0 .word 0x200004b0
|
|
|
|
08001530 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8001530: b580 push {r7, lr}
|
|
8001532: b084 sub sp, #16
|
|
8001534: af00 add r7, sp, #0
|
|
8001536: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8001538: f7ff ffee bl 8001518 <HAL_GetTick>
|
|
800153c: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
800153e: 687b ldr r3, [r7, #4]
|
|
8001540: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8001542: 68fb ldr r3, [r7, #12]
|
|
8001544: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8001548: d005 beq.n 8001556 <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
800154a: 4b0a ldr r3, [pc, #40] @ (8001574 <HAL_Delay+0x44>)
|
|
800154c: 781b ldrb r3, [r3, #0]
|
|
800154e: 461a mov r2, r3
|
|
8001550: 68fb ldr r3, [r7, #12]
|
|
8001552: 4413 add r3, r2
|
|
8001554: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while((HAL_GetTick() - tickstart) < wait)
|
|
8001556: bf00 nop
|
|
8001558: f7ff ffde bl 8001518 <HAL_GetTick>
|
|
800155c: 4602 mov r2, r0
|
|
800155e: 68bb ldr r3, [r7, #8]
|
|
8001560: 1ad3 subs r3, r2, r3
|
|
8001562: 68fa ldr r2, [r7, #12]
|
|
8001564: 429a cmp r2, r3
|
|
8001566: d8f7 bhi.n 8001558 <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
8001568: bf00 nop
|
|
800156a: bf00 nop
|
|
800156c: 3710 adds r7, #16
|
|
800156e: 46bd mov sp, r7
|
|
8001570: bd80 pop {r7, pc}
|
|
8001572: bf00 nop
|
|
8001574: 20000030 .word 0x20000030
|
|
|
|
08001578 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001578: b480 push {r7}
|
|
800157a: b085 sub sp, #20
|
|
800157c: af00 add r7, sp, #0
|
|
800157e: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8001580: 687b ldr r3, [r7, #4]
|
|
8001582: f003 0307 and.w r3, r3, #7
|
|
8001586: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
8001588: 4b0c ldr r3, [pc, #48] @ (80015bc <__NVIC_SetPriorityGrouping+0x44>)
|
|
800158a: 68db ldr r3, [r3, #12]
|
|
800158c: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
800158e: 68ba ldr r2, [r7, #8]
|
|
8001590: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
8001594: 4013 ands r3, r2
|
|
8001596: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
8001598: 68fb ldr r3, [r7, #12]
|
|
800159a: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
800159c: 68bb ldr r3, [r7, #8]
|
|
800159e: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80015a0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80015a4: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80015a8: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80015aa: 4a04 ldr r2, [pc, #16] @ (80015bc <__NVIC_SetPriorityGrouping+0x44>)
|
|
80015ac: 68bb ldr r3, [r7, #8]
|
|
80015ae: 60d3 str r3, [r2, #12]
|
|
}
|
|
80015b0: bf00 nop
|
|
80015b2: 3714 adds r7, #20
|
|
80015b4: 46bd mov sp, r7
|
|
80015b6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80015ba: 4770 bx lr
|
|
80015bc: e000ed00 .word 0xe000ed00
|
|
|
|
080015c0 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
80015c0: b480 push {r7}
|
|
80015c2: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
80015c4: 4b04 ldr r3, [pc, #16] @ (80015d8 <__NVIC_GetPriorityGrouping+0x18>)
|
|
80015c6: 68db ldr r3, [r3, #12]
|
|
80015c8: 0a1b lsrs r3, r3, #8
|
|
80015ca: f003 0307 and.w r3, r3, #7
|
|
}
|
|
80015ce: 4618 mov r0, r3
|
|
80015d0: 46bd mov sp, r7
|
|
80015d2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80015d6: 4770 bx lr
|
|
80015d8: e000ed00 .word 0xe000ed00
|
|
|
|
080015dc <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
80015dc: b480 push {r7}
|
|
80015de: b083 sub sp, #12
|
|
80015e0: af00 add r7, sp, #0
|
|
80015e2: 4603 mov r3, r0
|
|
80015e4: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
80015e6: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80015ea: 2b00 cmp r3, #0
|
|
80015ec: db0b blt.n 8001606 <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
80015ee: 79fb ldrb r3, [r7, #7]
|
|
80015f0: f003 021f and.w r2, r3, #31
|
|
80015f4: 4907 ldr r1, [pc, #28] @ (8001614 <__NVIC_EnableIRQ+0x38>)
|
|
80015f6: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80015fa: 095b lsrs r3, r3, #5
|
|
80015fc: 2001 movs r0, #1
|
|
80015fe: fa00 f202 lsl.w r2, r0, r2
|
|
8001602: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
8001606: bf00 nop
|
|
8001608: 370c adds r7, #12
|
|
800160a: 46bd mov sp, r7
|
|
800160c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001610: 4770 bx lr
|
|
8001612: bf00 nop
|
|
8001614: e000e100 .word 0xe000e100
|
|
|
|
08001618 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8001618: b480 push {r7}
|
|
800161a: b083 sub sp, #12
|
|
800161c: af00 add r7, sp, #0
|
|
800161e: 4603 mov r3, r0
|
|
8001620: 6039 str r1, [r7, #0]
|
|
8001622: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001624: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001628: 2b00 cmp r3, #0
|
|
800162a: db0a blt.n 8001642 <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
800162c: 683b ldr r3, [r7, #0]
|
|
800162e: b2da uxtb r2, r3
|
|
8001630: 490c ldr r1, [pc, #48] @ (8001664 <__NVIC_SetPriority+0x4c>)
|
|
8001632: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001636: 0112 lsls r2, r2, #4
|
|
8001638: b2d2 uxtb r2, r2
|
|
800163a: 440b add r3, r1
|
|
800163c: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8001640: e00a b.n 8001658 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001642: 683b ldr r3, [r7, #0]
|
|
8001644: b2da uxtb r2, r3
|
|
8001646: 4908 ldr r1, [pc, #32] @ (8001668 <__NVIC_SetPriority+0x50>)
|
|
8001648: 79fb ldrb r3, [r7, #7]
|
|
800164a: f003 030f and.w r3, r3, #15
|
|
800164e: 3b04 subs r3, #4
|
|
8001650: 0112 lsls r2, r2, #4
|
|
8001652: b2d2 uxtb r2, r2
|
|
8001654: 440b add r3, r1
|
|
8001656: 761a strb r2, [r3, #24]
|
|
}
|
|
8001658: bf00 nop
|
|
800165a: 370c adds r7, #12
|
|
800165c: 46bd mov sp, r7
|
|
800165e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001662: 4770 bx lr
|
|
8001664: e000e100 .word 0xe000e100
|
|
8001668: e000ed00 .word 0xe000ed00
|
|
|
|
0800166c <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
800166c: b480 push {r7}
|
|
800166e: b089 sub sp, #36 @ 0x24
|
|
8001670: af00 add r7, sp, #0
|
|
8001672: 60f8 str r0, [r7, #12]
|
|
8001674: 60b9 str r1, [r7, #8]
|
|
8001676: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8001678: 68fb ldr r3, [r7, #12]
|
|
800167a: f003 0307 and.w r3, r3, #7
|
|
800167e: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8001680: 69fb ldr r3, [r7, #28]
|
|
8001682: f1c3 0307 rsb r3, r3, #7
|
|
8001686: 2b04 cmp r3, #4
|
|
8001688: bf28 it cs
|
|
800168a: 2304 movcs r3, #4
|
|
800168c: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
800168e: 69fb ldr r3, [r7, #28]
|
|
8001690: 3304 adds r3, #4
|
|
8001692: 2b06 cmp r3, #6
|
|
8001694: d902 bls.n 800169c <NVIC_EncodePriority+0x30>
|
|
8001696: 69fb ldr r3, [r7, #28]
|
|
8001698: 3b03 subs r3, #3
|
|
800169a: e000 b.n 800169e <NVIC_EncodePriority+0x32>
|
|
800169c: 2300 movs r3, #0
|
|
800169e: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80016a0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80016a4: 69bb ldr r3, [r7, #24]
|
|
80016a6: fa02 f303 lsl.w r3, r2, r3
|
|
80016aa: 43da mvns r2, r3
|
|
80016ac: 68bb ldr r3, [r7, #8]
|
|
80016ae: 401a ands r2, r3
|
|
80016b0: 697b ldr r3, [r7, #20]
|
|
80016b2: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80016b4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
80016b8: 697b ldr r3, [r7, #20]
|
|
80016ba: fa01 f303 lsl.w r3, r1, r3
|
|
80016be: 43d9 mvns r1, r3
|
|
80016c0: 687b ldr r3, [r7, #4]
|
|
80016c2: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80016c4: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
80016c6: 4618 mov r0, r3
|
|
80016c8: 3724 adds r7, #36 @ 0x24
|
|
80016ca: 46bd mov sp, r7
|
|
80016cc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80016d0: 4770 bx lr
|
|
...
|
|
|
|
080016d4 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
80016d4: b580 push {r7, lr}
|
|
80016d6: b082 sub sp, #8
|
|
80016d8: af00 add r7, sp, #0
|
|
80016da: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
80016dc: 687b ldr r3, [r7, #4]
|
|
80016de: 3b01 subs r3, #1
|
|
80016e0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
80016e4: d301 bcc.n 80016ea <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
80016e6: 2301 movs r3, #1
|
|
80016e8: e00f b.n 800170a <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
80016ea: 4a0a ldr r2, [pc, #40] @ (8001714 <SysTick_Config+0x40>)
|
|
80016ec: 687b ldr r3, [r7, #4]
|
|
80016ee: 3b01 subs r3, #1
|
|
80016f0: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
80016f2: 210f movs r1, #15
|
|
80016f4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80016f8: f7ff ff8e bl 8001618 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
80016fc: 4b05 ldr r3, [pc, #20] @ (8001714 <SysTick_Config+0x40>)
|
|
80016fe: 2200 movs r2, #0
|
|
8001700: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8001702: 4b04 ldr r3, [pc, #16] @ (8001714 <SysTick_Config+0x40>)
|
|
8001704: 2207 movs r2, #7
|
|
8001706: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8001708: 2300 movs r3, #0
|
|
}
|
|
800170a: 4618 mov r0, r3
|
|
800170c: 3708 adds r7, #8
|
|
800170e: 46bd mov sp, r7
|
|
8001710: bd80 pop {r7, pc}
|
|
8001712: bf00 nop
|
|
8001714: e000e010 .word 0xe000e010
|
|
|
|
08001718 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001718: b580 push {r7, lr}
|
|
800171a: b082 sub sp, #8
|
|
800171c: af00 add r7, sp, #0
|
|
800171e: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8001720: 6878 ldr r0, [r7, #4]
|
|
8001722: f7ff ff29 bl 8001578 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8001726: bf00 nop
|
|
8001728: 3708 adds r7, #8
|
|
800172a: 46bd mov sp, r7
|
|
800172c: bd80 pop {r7, pc}
|
|
|
|
0800172e <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
800172e: b580 push {r7, lr}
|
|
8001730: b086 sub sp, #24
|
|
8001732: af00 add r7, sp, #0
|
|
8001734: 4603 mov r3, r0
|
|
8001736: 60b9 str r1, [r7, #8]
|
|
8001738: 607a str r2, [r7, #4]
|
|
800173a: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
800173c: 2300 movs r3, #0
|
|
800173e: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8001740: f7ff ff3e bl 80015c0 <__NVIC_GetPriorityGrouping>
|
|
8001744: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8001746: 687a ldr r2, [r7, #4]
|
|
8001748: 68b9 ldr r1, [r7, #8]
|
|
800174a: 6978 ldr r0, [r7, #20]
|
|
800174c: f7ff ff8e bl 800166c <NVIC_EncodePriority>
|
|
8001750: 4602 mov r2, r0
|
|
8001752: f997 300f ldrsb.w r3, [r7, #15]
|
|
8001756: 4611 mov r1, r2
|
|
8001758: 4618 mov r0, r3
|
|
800175a: f7ff ff5d bl 8001618 <__NVIC_SetPriority>
|
|
}
|
|
800175e: bf00 nop
|
|
8001760: 3718 adds r7, #24
|
|
8001762: 46bd mov sp, r7
|
|
8001764: bd80 pop {r7, pc}
|
|
|
|
08001766 <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001766: b580 push {r7, lr}
|
|
8001768: b082 sub sp, #8
|
|
800176a: af00 add r7, sp, #0
|
|
800176c: 4603 mov r3, r0
|
|
800176e: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8001770: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001774: 4618 mov r0, r3
|
|
8001776: f7ff ff31 bl 80015dc <__NVIC_EnableIRQ>
|
|
}
|
|
800177a: bf00 nop
|
|
800177c: 3708 adds r7, #8
|
|
800177e: 46bd mov sp, r7
|
|
8001780: bd80 pop {r7, pc}
|
|
|
|
08001782 <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
8001782: b580 push {r7, lr}
|
|
8001784: b082 sub sp, #8
|
|
8001786: af00 add r7, sp, #0
|
|
8001788: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
800178a: 6878 ldr r0, [r7, #4]
|
|
800178c: f7ff ffa2 bl 80016d4 <SysTick_Config>
|
|
8001790: 4603 mov r3, r0
|
|
}
|
|
8001792: 4618 mov r0, r3
|
|
8001794: 3708 adds r7, #8
|
|
8001796: 46bd mov sp, r7
|
|
8001798: bd80 pop {r7, pc}
|
|
|
|
0800179a <HAL_DMA_Start_IT>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
800179a: b580 push {r7, lr}
|
|
800179c: b086 sub sp, #24
|
|
800179e: af00 add r7, sp, #0
|
|
80017a0: 60f8 str r0, [r7, #12]
|
|
80017a2: 60b9 str r1, [r7, #8]
|
|
80017a4: 607a str r2, [r7, #4]
|
|
80017a6: 603b str r3, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80017a8: 2300 movs r3, #0
|
|
80017aa: 75fb strb r3, [r7, #23]
|
|
|
|
/* calculate DMA base and stream number */
|
|
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
|
|
80017ac: 68fb ldr r3, [r7, #12]
|
|
80017ae: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80017b0: 613b str r3, [r7, #16]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma);
|
|
80017b2: 68fb ldr r3, [r7, #12]
|
|
80017b4: f893 3034 ldrb.w r3, [r3, #52] @ 0x34
|
|
80017b8: 2b01 cmp r3, #1
|
|
80017ba: d101 bne.n 80017c0 <HAL_DMA_Start_IT+0x26>
|
|
80017bc: 2302 movs r3, #2
|
|
80017be: e040 b.n 8001842 <HAL_DMA_Start_IT+0xa8>
|
|
80017c0: 68fb ldr r3, [r7, #12]
|
|
80017c2: 2201 movs r2, #1
|
|
80017c4: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
if(HAL_DMA_STATE_READY == hdma->State)
|
|
80017c8: 68fb ldr r3, [r7, #12]
|
|
80017ca: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
|
|
80017ce: b2db uxtb r3, r3
|
|
80017d0: 2b01 cmp r3, #1
|
|
80017d2: d12f bne.n 8001834 <HAL_DMA_Start_IT+0x9a>
|
|
{
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
80017d4: 68fb ldr r3, [r7, #12]
|
|
80017d6: 2202 movs r2, #2
|
|
80017d8: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Initialize the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
80017dc: 68fb ldr r3, [r7, #12]
|
|
80017de: 2200 movs r2, #0
|
|
80017e0: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Configure the source, destination address and the data length */
|
|
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
|
80017e2: 683b ldr r3, [r7, #0]
|
|
80017e4: 687a ldr r2, [r7, #4]
|
|
80017e6: 68b9 ldr r1, [r7, #8]
|
|
80017e8: 68f8 ldr r0, [r7, #12]
|
|
80017ea: f000 f82e bl 800184a <DMA_SetConfig>
|
|
|
|
/* Clear all interrupt flags at correct offset within the register */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
80017ee: 68fb ldr r3, [r7, #12]
|
|
80017f0: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80017f2: 223f movs r2, #63 @ 0x3f
|
|
80017f4: 409a lsls r2, r3
|
|
80017f6: 693b ldr r3, [r7, #16]
|
|
80017f8: 609a str r2, [r3, #8]
|
|
|
|
/* Enable Common interrupts*/
|
|
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
|
|
80017fa: 68fb ldr r3, [r7, #12]
|
|
80017fc: 681b ldr r3, [r3, #0]
|
|
80017fe: 681a ldr r2, [r3, #0]
|
|
8001800: 68fb ldr r3, [r7, #12]
|
|
8001802: 681b ldr r3, [r3, #0]
|
|
8001804: f042 0216 orr.w r2, r2, #22
|
|
8001808: 601a str r2, [r3, #0]
|
|
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
800180a: 68fb ldr r3, [r7, #12]
|
|
800180c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800180e: 2b00 cmp r3, #0
|
|
8001810: d007 beq.n 8001822 <HAL_DMA_Start_IT+0x88>
|
|
{
|
|
hdma->Instance->CR |= DMA_IT_HT;
|
|
8001812: 68fb ldr r3, [r7, #12]
|
|
8001814: 681b ldr r3, [r3, #0]
|
|
8001816: 681a ldr r2, [r3, #0]
|
|
8001818: 68fb ldr r3, [r7, #12]
|
|
800181a: 681b ldr r3, [r3, #0]
|
|
800181c: f042 0208 orr.w r2, r2, #8
|
|
8001820: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_DMA_ENABLE(hdma);
|
|
8001822: 68fb ldr r3, [r7, #12]
|
|
8001824: 681b ldr r3, [r3, #0]
|
|
8001826: 681a ldr r2, [r3, #0]
|
|
8001828: 68fb ldr r3, [r7, #12]
|
|
800182a: 681b ldr r3, [r3, #0]
|
|
800182c: f042 0201 orr.w r2, r2, #1
|
|
8001830: 601a str r2, [r3, #0]
|
|
8001832: e005 b.n 8001840 <HAL_DMA_Start_IT+0xa6>
|
|
}
|
|
else
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001834: 68fb ldr r3, [r7, #12]
|
|
8001836: 2200 movs r2, #0
|
|
8001838: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
/* Return error status */
|
|
status = HAL_BUSY;
|
|
800183c: 2302 movs r3, #2
|
|
800183e: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return status;
|
|
8001840: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8001842: 4618 mov r0, r3
|
|
8001844: 3718 adds r7, #24
|
|
8001846: 46bd mov sp, r7
|
|
8001848: bd80 pop {r7, pc}
|
|
|
|
0800184a <DMA_SetConfig>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
800184a: b480 push {r7}
|
|
800184c: b085 sub sp, #20
|
|
800184e: af00 add r7, sp, #0
|
|
8001850: 60f8 str r0, [r7, #12]
|
|
8001852: 60b9 str r1, [r7, #8]
|
|
8001854: 607a str r2, [r7, #4]
|
|
8001856: 603b str r3, [r7, #0]
|
|
/* Clear DBM bit */
|
|
hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
|
|
8001858: 68fb ldr r3, [r7, #12]
|
|
800185a: 681b ldr r3, [r3, #0]
|
|
800185c: 681a ldr r2, [r3, #0]
|
|
800185e: 68fb ldr r3, [r7, #12]
|
|
8001860: 681b ldr r3, [r3, #0]
|
|
8001862: f422 2280 bic.w r2, r2, #262144 @ 0x40000
|
|
8001866: 601a str r2, [r3, #0]
|
|
|
|
/* Configure DMA Stream data length */
|
|
hdma->Instance->NDTR = DataLength;
|
|
8001868: 68fb ldr r3, [r7, #12]
|
|
800186a: 681b ldr r3, [r3, #0]
|
|
800186c: 683a ldr r2, [r7, #0]
|
|
800186e: 605a str r2, [r3, #4]
|
|
|
|
/* Memory to Peripheral */
|
|
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
|
8001870: 68fb ldr r3, [r7, #12]
|
|
8001872: 689b ldr r3, [r3, #8]
|
|
8001874: 2b40 cmp r3, #64 @ 0x40
|
|
8001876: d108 bne.n 800188a <DMA_SetConfig+0x40>
|
|
{
|
|
/* Configure DMA Stream destination address */
|
|
hdma->Instance->PAR = DstAddress;
|
|
8001878: 68fb ldr r3, [r7, #12]
|
|
800187a: 681b ldr r3, [r3, #0]
|
|
800187c: 687a ldr r2, [r7, #4]
|
|
800187e: 609a str r2, [r3, #8]
|
|
|
|
/* Configure DMA Stream source address */
|
|
hdma->Instance->M0AR = SrcAddress;
|
|
8001880: 68fb ldr r3, [r7, #12]
|
|
8001882: 681b ldr r3, [r3, #0]
|
|
8001884: 68ba ldr r2, [r7, #8]
|
|
8001886: 60da str r2, [r3, #12]
|
|
hdma->Instance->PAR = SrcAddress;
|
|
|
|
/* Configure DMA Stream destination address */
|
|
hdma->Instance->M0AR = DstAddress;
|
|
}
|
|
}
|
|
8001888: e007 b.n 800189a <DMA_SetConfig+0x50>
|
|
hdma->Instance->PAR = SrcAddress;
|
|
800188a: 68fb ldr r3, [r7, #12]
|
|
800188c: 681b ldr r3, [r3, #0]
|
|
800188e: 68ba ldr r2, [r7, #8]
|
|
8001890: 609a str r2, [r3, #8]
|
|
hdma->Instance->M0AR = DstAddress;
|
|
8001892: 68fb ldr r3, [r7, #12]
|
|
8001894: 681b ldr r3, [r3, #0]
|
|
8001896: 687a ldr r2, [r7, #4]
|
|
8001898: 60da str r2, [r3, #12]
|
|
}
|
|
800189a: bf00 nop
|
|
800189c: 3714 adds r7, #20
|
|
800189e: 46bd mov sp, r7
|
|
80018a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80018a4: 4770 bx lr
|
|
...
|
|
|
|
080018a8 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
80018a8: b480 push {r7}
|
|
80018aa: b089 sub sp, #36 @ 0x24
|
|
80018ac: af00 add r7, sp, #0
|
|
80018ae: 6078 str r0, [r7, #4]
|
|
80018b0: 6039 str r1, [r7, #0]
|
|
uint32_t position;
|
|
uint32_t ioposition = 0x00U;
|
|
80018b2: 2300 movs r3, #0
|
|
80018b4: 617b str r3, [r7, #20]
|
|
uint32_t iocurrent = 0x00U;
|
|
80018b6: 2300 movs r3, #0
|
|
80018b8: 613b str r3, [r7, #16]
|
|
uint32_t temp = 0x00U;
|
|
80018ba: 2300 movs r3, #0
|
|
80018bc: 61bb str r3, [r7, #24]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
80018be: 2300 movs r3, #0
|
|
80018c0: 61fb str r3, [r7, #28]
|
|
80018c2: e165 b.n 8001b90 <HAL_GPIO_Init+0x2e8>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = 0x01U << position;
|
|
80018c4: 2201 movs r2, #1
|
|
80018c6: 69fb ldr r3, [r7, #28]
|
|
80018c8: fa02 f303 lsl.w r3, r2, r3
|
|
80018cc: 617b str r3, [r7, #20]
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
80018ce: 683b ldr r3, [r7, #0]
|
|
80018d0: 681b ldr r3, [r3, #0]
|
|
80018d2: 697a ldr r2, [r7, #20]
|
|
80018d4: 4013 ands r3, r2
|
|
80018d6: 613b str r3, [r7, #16]
|
|
|
|
if(iocurrent == ioposition)
|
|
80018d8: 693a ldr r2, [r7, #16]
|
|
80018da: 697b ldr r3, [r7, #20]
|
|
80018dc: 429a cmp r2, r3
|
|
80018de: f040 8154 bne.w 8001b8a <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
80018e2: 683b ldr r3, [r7, #0]
|
|
80018e4: 685b ldr r3, [r3, #4]
|
|
80018e6: f003 0303 and.w r3, r3, #3
|
|
80018ea: 2b01 cmp r3, #1
|
|
80018ec: d005 beq.n 80018fa <HAL_GPIO_Init+0x52>
|
|
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
80018ee: 683b ldr r3, [r7, #0]
|
|
80018f0: 685b ldr r3, [r3, #4]
|
|
80018f2: f003 0303 and.w r3, r3, #3
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
80018f6: 2b02 cmp r3, #2
|
|
80018f8: d130 bne.n 800195c <HAL_GPIO_Init+0xb4>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
80018fa: 687b ldr r3, [r7, #4]
|
|
80018fc: 689b ldr r3, [r3, #8]
|
|
80018fe: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
|
8001900: 69fb ldr r3, [r7, #28]
|
|
8001902: 005b lsls r3, r3, #1
|
|
8001904: 2203 movs r2, #3
|
|
8001906: fa02 f303 lsl.w r3, r2, r3
|
|
800190a: 43db mvns r3, r3
|
|
800190c: 69ba ldr r2, [r7, #24]
|
|
800190e: 4013 ands r3, r2
|
|
8001910: 61bb str r3, [r7, #24]
|
|
temp |= (GPIO_Init->Speed << (position * 2U));
|
|
8001912: 683b ldr r3, [r7, #0]
|
|
8001914: 68da ldr r2, [r3, #12]
|
|
8001916: 69fb ldr r3, [r7, #28]
|
|
8001918: 005b lsls r3, r3, #1
|
|
800191a: fa02 f303 lsl.w r3, r2, r3
|
|
800191e: 69ba ldr r2, [r7, #24]
|
|
8001920: 4313 orrs r3, r2
|
|
8001922: 61bb str r3, [r7, #24]
|
|
GPIOx->OSPEEDR = temp;
|
|
8001924: 687b ldr r3, [r7, #4]
|
|
8001926: 69ba ldr r2, [r7, #24]
|
|
8001928: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
800192a: 687b ldr r3, [r7, #4]
|
|
800192c: 685b ldr r3, [r3, #4]
|
|
800192e: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
8001930: 2201 movs r2, #1
|
|
8001932: 69fb ldr r3, [r7, #28]
|
|
8001934: fa02 f303 lsl.w r3, r2, r3
|
|
8001938: 43db mvns r3, r3
|
|
800193a: 69ba ldr r2, [r7, #24]
|
|
800193c: 4013 ands r3, r2
|
|
800193e: 61bb str r3, [r7, #24]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8001940: 683b ldr r3, [r7, #0]
|
|
8001942: 685b ldr r3, [r3, #4]
|
|
8001944: 091b lsrs r3, r3, #4
|
|
8001946: f003 0201 and.w r2, r3, #1
|
|
800194a: 69fb ldr r3, [r7, #28]
|
|
800194c: fa02 f303 lsl.w r3, r2, r3
|
|
8001950: 69ba ldr r2, [r7, #24]
|
|
8001952: 4313 orrs r3, r2
|
|
8001954: 61bb str r3, [r7, #24]
|
|
GPIOx->OTYPER = temp;
|
|
8001956: 687b ldr r3, [r7, #4]
|
|
8001958: 69ba ldr r2, [r7, #24]
|
|
800195a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
800195c: 683b ldr r3, [r7, #0]
|
|
800195e: 685b ldr r3, [r3, #4]
|
|
8001960: f003 0303 and.w r3, r3, #3
|
|
8001964: 2b03 cmp r3, #3
|
|
8001966: d017 beq.n 8001998 <HAL_GPIO_Init+0xf0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
8001968: 687b ldr r3, [r7, #4]
|
|
800196a: 68db ldr r3, [r3, #12]
|
|
800196c: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
|
800196e: 69fb ldr r3, [r7, #28]
|
|
8001970: 005b lsls r3, r3, #1
|
|
8001972: 2203 movs r2, #3
|
|
8001974: fa02 f303 lsl.w r3, r2, r3
|
|
8001978: 43db mvns r3, r3
|
|
800197a: 69ba ldr r2, [r7, #24]
|
|
800197c: 4013 ands r3, r2
|
|
800197e: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
8001980: 683b ldr r3, [r7, #0]
|
|
8001982: 689a ldr r2, [r3, #8]
|
|
8001984: 69fb ldr r3, [r7, #28]
|
|
8001986: 005b lsls r3, r3, #1
|
|
8001988: fa02 f303 lsl.w r3, r2, r3
|
|
800198c: 69ba ldr r2, [r7, #24]
|
|
800198e: 4313 orrs r3, r2
|
|
8001990: 61bb str r3, [r7, #24]
|
|
GPIOx->PUPDR = temp;
|
|
8001992: 687b ldr r3, [r7, #4]
|
|
8001994: 69ba ldr r2, [r7, #24]
|
|
8001996: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8001998: 683b ldr r3, [r7, #0]
|
|
800199a: 685b ldr r3, [r3, #4]
|
|
800199c: f003 0303 and.w r3, r3, #3
|
|
80019a0: 2b02 cmp r3, #2
|
|
80019a2: d123 bne.n 80019ec <HAL_GPIO_Init+0x144>
|
|
{
|
|
/* Check the Alternate function parameter */
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3U];
|
|
80019a4: 69fb ldr r3, [r7, #28]
|
|
80019a6: 08da lsrs r2, r3, #3
|
|
80019a8: 687b ldr r3, [r7, #4]
|
|
80019aa: 3208 adds r2, #8
|
|
80019ac: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80019b0: 61bb str r3, [r7, #24]
|
|
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
|
|
80019b2: 69fb ldr r3, [r7, #28]
|
|
80019b4: f003 0307 and.w r3, r3, #7
|
|
80019b8: 009b lsls r3, r3, #2
|
|
80019ba: 220f movs r2, #15
|
|
80019bc: fa02 f303 lsl.w r3, r2, r3
|
|
80019c0: 43db mvns r3, r3
|
|
80019c2: 69ba ldr r2, [r7, #24]
|
|
80019c4: 4013 ands r3, r2
|
|
80019c6: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
|
|
80019c8: 683b ldr r3, [r7, #0]
|
|
80019ca: 691a ldr r2, [r3, #16]
|
|
80019cc: 69fb ldr r3, [r7, #28]
|
|
80019ce: f003 0307 and.w r3, r3, #7
|
|
80019d2: 009b lsls r3, r3, #2
|
|
80019d4: fa02 f303 lsl.w r3, r2, r3
|
|
80019d8: 69ba ldr r2, [r7, #24]
|
|
80019da: 4313 orrs r3, r2
|
|
80019dc: 61bb str r3, [r7, #24]
|
|
GPIOx->AFR[position >> 3U] = temp;
|
|
80019de: 69fb ldr r3, [r7, #28]
|
|
80019e0: 08da lsrs r2, r3, #3
|
|
80019e2: 687b ldr r3, [r7, #4]
|
|
80019e4: 3208 adds r2, #8
|
|
80019e6: 69b9 ldr r1, [r7, #24]
|
|
80019e8: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
80019ec: 687b ldr r3, [r7, #4]
|
|
80019ee: 681b ldr r3, [r3, #0]
|
|
80019f0: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
|
80019f2: 69fb ldr r3, [r7, #28]
|
|
80019f4: 005b lsls r3, r3, #1
|
|
80019f6: 2203 movs r2, #3
|
|
80019f8: fa02 f303 lsl.w r3, r2, r3
|
|
80019fc: 43db mvns r3, r3
|
|
80019fe: 69ba ldr r2, [r7, #24]
|
|
8001a00: 4013 ands r3, r2
|
|
8001a02: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
|
8001a04: 683b ldr r3, [r7, #0]
|
|
8001a06: 685b ldr r3, [r3, #4]
|
|
8001a08: f003 0203 and.w r2, r3, #3
|
|
8001a0c: 69fb ldr r3, [r7, #28]
|
|
8001a0e: 005b lsls r3, r3, #1
|
|
8001a10: fa02 f303 lsl.w r3, r2, r3
|
|
8001a14: 69ba ldr r2, [r7, #24]
|
|
8001a16: 4313 orrs r3, r2
|
|
8001a18: 61bb str r3, [r7, #24]
|
|
GPIOx->MODER = temp;
|
|
8001a1a: 687b ldr r3, [r7, #4]
|
|
8001a1c: 69ba ldr r2, [r7, #24]
|
|
8001a1e: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
|
|
8001a20: 683b ldr r3, [r7, #0]
|
|
8001a22: 685b ldr r3, [r3, #4]
|
|
8001a24: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8001a28: 2b00 cmp r3, #0
|
|
8001a2a: f000 80ae beq.w 8001b8a <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8001a2e: 2300 movs r3, #0
|
|
8001a30: 60fb str r3, [r7, #12]
|
|
8001a32: 4b5d ldr r3, [pc, #372] @ (8001ba8 <HAL_GPIO_Init+0x300>)
|
|
8001a34: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001a36: 4a5c ldr r2, [pc, #368] @ (8001ba8 <HAL_GPIO_Init+0x300>)
|
|
8001a38: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8001a3c: 6453 str r3, [r2, #68] @ 0x44
|
|
8001a3e: 4b5a ldr r3, [pc, #360] @ (8001ba8 <HAL_GPIO_Init+0x300>)
|
|
8001a40: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001a42: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8001a46: 60fb str r3, [r7, #12]
|
|
8001a48: 68fb ldr r3, [r7, #12]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2U];
|
|
8001a4a: 4a58 ldr r2, [pc, #352] @ (8001bac <HAL_GPIO_Init+0x304>)
|
|
8001a4c: 69fb ldr r3, [r7, #28]
|
|
8001a4e: 089b lsrs r3, r3, #2
|
|
8001a50: 3302 adds r3, #2
|
|
8001a52: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8001a56: 61bb str r3, [r7, #24]
|
|
temp &= ~(0x0FU << (4U * (position & 0x03U)));
|
|
8001a58: 69fb ldr r3, [r7, #28]
|
|
8001a5a: f003 0303 and.w r3, r3, #3
|
|
8001a5e: 009b lsls r3, r3, #2
|
|
8001a60: 220f movs r2, #15
|
|
8001a62: fa02 f303 lsl.w r3, r2, r3
|
|
8001a66: 43db mvns r3, r3
|
|
8001a68: 69ba ldr r2, [r7, #24]
|
|
8001a6a: 4013 ands r3, r2
|
|
8001a6c: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
|
|
8001a6e: 687b ldr r3, [r7, #4]
|
|
8001a70: 4a4f ldr r2, [pc, #316] @ (8001bb0 <HAL_GPIO_Init+0x308>)
|
|
8001a72: 4293 cmp r3, r2
|
|
8001a74: d025 beq.n 8001ac2 <HAL_GPIO_Init+0x21a>
|
|
8001a76: 687b ldr r3, [r7, #4]
|
|
8001a78: 4a4e ldr r2, [pc, #312] @ (8001bb4 <HAL_GPIO_Init+0x30c>)
|
|
8001a7a: 4293 cmp r3, r2
|
|
8001a7c: d01f beq.n 8001abe <HAL_GPIO_Init+0x216>
|
|
8001a7e: 687b ldr r3, [r7, #4]
|
|
8001a80: 4a4d ldr r2, [pc, #308] @ (8001bb8 <HAL_GPIO_Init+0x310>)
|
|
8001a82: 4293 cmp r3, r2
|
|
8001a84: d019 beq.n 8001aba <HAL_GPIO_Init+0x212>
|
|
8001a86: 687b ldr r3, [r7, #4]
|
|
8001a88: 4a4c ldr r2, [pc, #304] @ (8001bbc <HAL_GPIO_Init+0x314>)
|
|
8001a8a: 4293 cmp r3, r2
|
|
8001a8c: d013 beq.n 8001ab6 <HAL_GPIO_Init+0x20e>
|
|
8001a8e: 687b ldr r3, [r7, #4]
|
|
8001a90: 4a4b ldr r2, [pc, #300] @ (8001bc0 <HAL_GPIO_Init+0x318>)
|
|
8001a92: 4293 cmp r3, r2
|
|
8001a94: d00d beq.n 8001ab2 <HAL_GPIO_Init+0x20a>
|
|
8001a96: 687b ldr r3, [r7, #4]
|
|
8001a98: 4a4a ldr r2, [pc, #296] @ (8001bc4 <HAL_GPIO_Init+0x31c>)
|
|
8001a9a: 4293 cmp r3, r2
|
|
8001a9c: d007 beq.n 8001aae <HAL_GPIO_Init+0x206>
|
|
8001a9e: 687b ldr r3, [r7, #4]
|
|
8001aa0: 4a49 ldr r2, [pc, #292] @ (8001bc8 <HAL_GPIO_Init+0x320>)
|
|
8001aa2: 4293 cmp r3, r2
|
|
8001aa4: d101 bne.n 8001aaa <HAL_GPIO_Init+0x202>
|
|
8001aa6: 2306 movs r3, #6
|
|
8001aa8: e00c b.n 8001ac4 <HAL_GPIO_Init+0x21c>
|
|
8001aaa: 2307 movs r3, #7
|
|
8001aac: e00a b.n 8001ac4 <HAL_GPIO_Init+0x21c>
|
|
8001aae: 2305 movs r3, #5
|
|
8001ab0: e008 b.n 8001ac4 <HAL_GPIO_Init+0x21c>
|
|
8001ab2: 2304 movs r3, #4
|
|
8001ab4: e006 b.n 8001ac4 <HAL_GPIO_Init+0x21c>
|
|
8001ab6: 2303 movs r3, #3
|
|
8001ab8: e004 b.n 8001ac4 <HAL_GPIO_Init+0x21c>
|
|
8001aba: 2302 movs r3, #2
|
|
8001abc: e002 b.n 8001ac4 <HAL_GPIO_Init+0x21c>
|
|
8001abe: 2301 movs r3, #1
|
|
8001ac0: e000 b.n 8001ac4 <HAL_GPIO_Init+0x21c>
|
|
8001ac2: 2300 movs r3, #0
|
|
8001ac4: 69fa ldr r2, [r7, #28]
|
|
8001ac6: f002 0203 and.w r2, r2, #3
|
|
8001aca: 0092 lsls r2, r2, #2
|
|
8001acc: 4093 lsls r3, r2
|
|
8001ace: 69ba ldr r2, [r7, #24]
|
|
8001ad0: 4313 orrs r3, r2
|
|
8001ad2: 61bb str r3, [r7, #24]
|
|
SYSCFG->EXTICR[position >> 2U] = temp;
|
|
8001ad4: 4935 ldr r1, [pc, #212] @ (8001bac <HAL_GPIO_Init+0x304>)
|
|
8001ad6: 69fb ldr r3, [r7, #28]
|
|
8001ad8: 089b lsrs r3, r3, #2
|
|
8001ada: 3302 adds r3, #2
|
|
8001adc: 69ba ldr r2, [r7, #24]
|
|
8001ade: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR;
|
|
8001ae2: 4b3a ldr r3, [pc, #232] @ (8001bcc <HAL_GPIO_Init+0x324>)
|
|
8001ae4: 689b ldr r3, [r3, #8]
|
|
8001ae6: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001ae8: 693b ldr r3, [r7, #16]
|
|
8001aea: 43db mvns r3, r3
|
|
8001aec: 69ba ldr r2, [r7, #24]
|
|
8001aee: 4013 ands r3, r2
|
|
8001af0: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
|
|
8001af2: 683b ldr r3, [r7, #0]
|
|
8001af4: 685b ldr r3, [r3, #4]
|
|
8001af6: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8001afa: 2b00 cmp r3, #0
|
|
8001afc: d003 beq.n 8001b06 <HAL_GPIO_Init+0x25e>
|
|
{
|
|
temp |= iocurrent;
|
|
8001afe: 69ba ldr r2, [r7, #24]
|
|
8001b00: 693b ldr r3, [r7, #16]
|
|
8001b02: 4313 orrs r3, r2
|
|
8001b04: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->RTSR = temp;
|
|
8001b06: 4a31 ldr r2, [pc, #196] @ (8001bcc <HAL_GPIO_Init+0x324>)
|
|
8001b08: 69bb ldr r3, [r7, #24]
|
|
8001b0a: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR;
|
|
8001b0c: 4b2f ldr r3, [pc, #188] @ (8001bcc <HAL_GPIO_Init+0x324>)
|
|
8001b0e: 68db ldr r3, [r3, #12]
|
|
8001b10: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001b12: 693b ldr r3, [r7, #16]
|
|
8001b14: 43db mvns r3, r3
|
|
8001b16: 69ba ldr r2, [r7, #24]
|
|
8001b18: 4013 ands r3, r2
|
|
8001b1a: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
|
|
8001b1c: 683b ldr r3, [r7, #0]
|
|
8001b1e: 685b ldr r3, [r3, #4]
|
|
8001b20: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8001b24: 2b00 cmp r3, #0
|
|
8001b26: d003 beq.n 8001b30 <HAL_GPIO_Init+0x288>
|
|
{
|
|
temp |= iocurrent;
|
|
8001b28: 69ba ldr r2, [r7, #24]
|
|
8001b2a: 693b ldr r3, [r7, #16]
|
|
8001b2c: 4313 orrs r3, r2
|
|
8001b2e: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->FTSR = temp;
|
|
8001b30: 4a26 ldr r2, [pc, #152] @ (8001bcc <HAL_GPIO_Init+0x324>)
|
|
8001b32: 69bb ldr r3, [r7, #24]
|
|
8001b34: 60d3 str r3, [r2, #12]
|
|
|
|
temp = EXTI->EMR;
|
|
8001b36: 4b25 ldr r3, [pc, #148] @ (8001bcc <HAL_GPIO_Init+0x324>)
|
|
8001b38: 685b ldr r3, [r3, #4]
|
|
8001b3a: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001b3c: 693b ldr r3, [r7, #16]
|
|
8001b3e: 43db mvns r3, r3
|
|
8001b40: 69ba ldr r2, [r7, #24]
|
|
8001b42: 4013 ands r3, r2
|
|
8001b44: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
|
|
8001b46: 683b ldr r3, [r7, #0]
|
|
8001b48: 685b ldr r3, [r3, #4]
|
|
8001b4a: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001b4e: 2b00 cmp r3, #0
|
|
8001b50: d003 beq.n 8001b5a <HAL_GPIO_Init+0x2b2>
|
|
{
|
|
temp |= iocurrent;
|
|
8001b52: 69ba ldr r2, [r7, #24]
|
|
8001b54: 693b ldr r3, [r7, #16]
|
|
8001b56: 4313 orrs r3, r2
|
|
8001b58: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->EMR = temp;
|
|
8001b5a: 4a1c ldr r2, [pc, #112] @ (8001bcc <HAL_GPIO_Init+0x324>)
|
|
8001b5c: 69bb ldr r3, [r7, #24]
|
|
8001b5e: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR;
|
|
8001b60: 4b1a ldr r3, [pc, #104] @ (8001bcc <HAL_GPIO_Init+0x324>)
|
|
8001b62: 681b ldr r3, [r3, #0]
|
|
8001b64: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001b66: 693b ldr r3, [r7, #16]
|
|
8001b68: 43db mvns r3, r3
|
|
8001b6a: 69ba ldr r2, [r7, #24]
|
|
8001b6c: 4013 ands r3, r2
|
|
8001b6e: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
|
|
8001b70: 683b ldr r3, [r7, #0]
|
|
8001b72: 685b ldr r3, [r3, #4]
|
|
8001b74: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8001b78: 2b00 cmp r3, #0
|
|
8001b7a: d003 beq.n 8001b84 <HAL_GPIO_Init+0x2dc>
|
|
{
|
|
temp |= iocurrent;
|
|
8001b7c: 69ba ldr r2, [r7, #24]
|
|
8001b7e: 693b ldr r3, [r7, #16]
|
|
8001b80: 4313 orrs r3, r2
|
|
8001b82: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->IMR = temp;
|
|
8001b84: 4a11 ldr r2, [pc, #68] @ (8001bcc <HAL_GPIO_Init+0x324>)
|
|
8001b86: 69bb ldr r3, [r7, #24]
|
|
8001b88: 6013 str r3, [r2, #0]
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
8001b8a: 69fb ldr r3, [r7, #28]
|
|
8001b8c: 3301 adds r3, #1
|
|
8001b8e: 61fb str r3, [r7, #28]
|
|
8001b90: 69fb ldr r3, [r7, #28]
|
|
8001b92: 2b0f cmp r3, #15
|
|
8001b94: f67f ae96 bls.w 80018c4 <HAL_GPIO_Init+0x1c>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8001b98: bf00 nop
|
|
8001b9a: bf00 nop
|
|
8001b9c: 3724 adds r7, #36 @ 0x24
|
|
8001b9e: 46bd mov sp, r7
|
|
8001ba0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001ba4: 4770 bx lr
|
|
8001ba6: bf00 nop
|
|
8001ba8: 40023800 .word 0x40023800
|
|
8001bac: 40013800 .word 0x40013800
|
|
8001bb0: 40020000 .word 0x40020000
|
|
8001bb4: 40020400 .word 0x40020400
|
|
8001bb8: 40020800 .word 0x40020800
|
|
8001bbc: 40020c00 .word 0x40020c00
|
|
8001bc0: 40021000 .word 0x40021000
|
|
8001bc4: 40021400 .word 0x40021400
|
|
8001bc8: 40021800 .word 0x40021800
|
|
8001bcc: 40013c00 .word 0x40013c00
|
|
|
|
08001bd0 <HAL_GPIO_ReadPin>:
|
|
* @param GPIO_Pin specifies the port bit to read.
|
|
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
|
* @retval The input port pin value.
|
|
*/
|
|
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
8001bd0: b480 push {r7}
|
|
8001bd2: b085 sub sp, #20
|
|
8001bd4: af00 add r7, sp, #0
|
|
8001bd6: 6078 str r0, [r7, #4]
|
|
8001bd8: 460b mov r3, r1
|
|
8001bda: 807b strh r3, [r7, #2]
|
|
GPIO_PinState bitstatus;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
|
8001bdc: 687b ldr r3, [r7, #4]
|
|
8001bde: 691a ldr r2, [r3, #16]
|
|
8001be0: 887b ldrh r3, [r7, #2]
|
|
8001be2: 4013 ands r3, r2
|
|
8001be4: 2b00 cmp r3, #0
|
|
8001be6: d002 beq.n 8001bee <HAL_GPIO_ReadPin+0x1e>
|
|
{
|
|
bitstatus = GPIO_PIN_SET;
|
|
8001be8: 2301 movs r3, #1
|
|
8001bea: 73fb strb r3, [r7, #15]
|
|
8001bec: e001 b.n 8001bf2 <HAL_GPIO_ReadPin+0x22>
|
|
}
|
|
else
|
|
{
|
|
bitstatus = GPIO_PIN_RESET;
|
|
8001bee: 2300 movs r3, #0
|
|
8001bf0: 73fb strb r3, [r7, #15]
|
|
}
|
|
return bitstatus;
|
|
8001bf2: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001bf4: 4618 mov r0, r3
|
|
8001bf6: 3714 adds r7, #20
|
|
8001bf8: 46bd mov sp, r7
|
|
8001bfa: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001bfe: 4770 bx lr
|
|
|
|
08001c00 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8001c00: b480 push {r7}
|
|
8001c02: b083 sub sp, #12
|
|
8001c04: af00 add r7, sp, #0
|
|
8001c06: 6078 str r0, [r7, #4]
|
|
8001c08: 460b mov r3, r1
|
|
8001c0a: 807b strh r3, [r7, #2]
|
|
8001c0c: 4613 mov r3, r2
|
|
8001c0e: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8001c10: 787b ldrb r3, [r7, #1]
|
|
8001c12: 2b00 cmp r3, #0
|
|
8001c14: d003 beq.n 8001c1e <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = GPIO_Pin;
|
|
8001c16: 887a ldrh r2, [r7, #2]
|
|
8001c18: 687b ldr r3, [r7, #4]
|
|
8001c1a: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
}
|
|
}
|
|
8001c1c: e003 b.n 8001c26 <HAL_GPIO_WritePin+0x26>
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
8001c1e: 887b ldrh r3, [r7, #2]
|
|
8001c20: 041a lsls r2, r3, #16
|
|
8001c22: 687b ldr r3, [r7, #4]
|
|
8001c24: 619a str r2, [r3, #24]
|
|
}
|
|
8001c26: bf00 nop
|
|
8001c28: 370c adds r7, #12
|
|
8001c2a: 46bd mov sp, r7
|
|
8001c2c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001c30: 4770 bx lr
|
|
...
|
|
|
|
08001c34 <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8001c34: b580 push {r7, lr}
|
|
8001c36: b084 sub sp, #16
|
|
8001c38: af00 add r7, sp, #0
|
|
8001c3a: 6078 str r0, [r7, #4]
|
|
uint32_t freqrange;
|
|
uint32_t pclk1;
|
|
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8001c3c: 687b ldr r3, [r7, #4]
|
|
8001c3e: 2b00 cmp r3, #0
|
|
8001c40: d101 bne.n 8001c46 <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001c42: 2301 movs r3, #1
|
|
8001c44: e12b b.n 8001e9e <HAL_I2C_Init+0x26a>
|
|
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
8001c46: 687b ldr r3, [r7, #4]
|
|
8001c48: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8001c4c: b2db uxtb r3, r3
|
|
8001c4e: 2b00 cmp r3, #0
|
|
8001c50: d106 bne.n 8001c60 <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
8001c52: 687b ldr r3, [r7, #4]
|
|
8001c54: 2200 movs r2, #0
|
|
8001c56: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_I2C_MspInit(hi2c);
|
|
8001c5a: 6878 ldr r0, [r7, #4]
|
|
8001c5c: f7ff f95c bl 8000f18 <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8001c60: 687b ldr r3, [r7, #4]
|
|
8001c62: 2224 movs r2, #36 @ 0x24
|
|
8001c64: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8001c68: 687b ldr r3, [r7, #4]
|
|
8001c6a: 681b ldr r3, [r3, #0]
|
|
8001c6c: 681a ldr r2, [r3, #0]
|
|
8001c6e: 687b ldr r3, [r7, #4]
|
|
8001c70: 681b ldr r3, [r3, #0]
|
|
8001c72: f022 0201 bic.w r2, r2, #1
|
|
8001c76: 601a str r2, [r3, #0]
|
|
|
|
/*Reset I2C*/
|
|
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
|
|
8001c78: 687b ldr r3, [r7, #4]
|
|
8001c7a: 681b ldr r3, [r3, #0]
|
|
8001c7c: 681a ldr r2, [r3, #0]
|
|
8001c7e: 687b ldr r3, [r7, #4]
|
|
8001c80: 681b ldr r3, [r3, #0]
|
|
8001c82: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
8001c86: 601a str r2, [r3, #0]
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
|
|
8001c88: 687b ldr r3, [r7, #4]
|
|
8001c8a: 681b ldr r3, [r3, #0]
|
|
8001c8c: 681a ldr r2, [r3, #0]
|
|
8001c8e: 687b ldr r3, [r7, #4]
|
|
8001c90: 681b ldr r3, [r3, #0]
|
|
8001c92: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8001c96: 601a str r2, [r3, #0]
|
|
|
|
/* Get PCLK1 frequency */
|
|
pclk1 = HAL_RCC_GetPCLK1Freq();
|
|
8001c98: f001 fc88 bl 80035ac <HAL_RCC_GetPCLK1Freq>
|
|
8001c9c: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check the minimum allowed PCLK1 frequency */
|
|
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
|
|
8001c9e: 687b ldr r3, [r7, #4]
|
|
8001ca0: 685b ldr r3, [r3, #4]
|
|
8001ca2: 4a81 ldr r2, [pc, #516] @ (8001ea8 <HAL_I2C_Init+0x274>)
|
|
8001ca4: 4293 cmp r3, r2
|
|
8001ca6: d807 bhi.n 8001cb8 <HAL_I2C_Init+0x84>
|
|
8001ca8: 68fb ldr r3, [r7, #12]
|
|
8001caa: 4a80 ldr r2, [pc, #512] @ (8001eac <HAL_I2C_Init+0x278>)
|
|
8001cac: 4293 cmp r3, r2
|
|
8001cae: bf94 ite ls
|
|
8001cb0: 2301 movls r3, #1
|
|
8001cb2: 2300 movhi r3, #0
|
|
8001cb4: b2db uxtb r3, r3
|
|
8001cb6: e006 b.n 8001cc6 <HAL_I2C_Init+0x92>
|
|
8001cb8: 68fb ldr r3, [r7, #12]
|
|
8001cba: 4a7d ldr r2, [pc, #500] @ (8001eb0 <HAL_I2C_Init+0x27c>)
|
|
8001cbc: 4293 cmp r3, r2
|
|
8001cbe: bf94 ite ls
|
|
8001cc0: 2301 movls r3, #1
|
|
8001cc2: 2300 movhi r3, #0
|
|
8001cc4: b2db uxtb r3, r3
|
|
8001cc6: 2b00 cmp r3, #0
|
|
8001cc8: d001 beq.n 8001cce <HAL_I2C_Init+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
8001cca: 2301 movs r3, #1
|
|
8001ccc: e0e7 b.n 8001e9e <HAL_I2C_Init+0x26a>
|
|
}
|
|
|
|
/* Calculate frequency range */
|
|
freqrange = I2C_FREQRANGE(pclk1);
|
|
8001cce: 68fb ldr r3, [r7, #12]
|
|
8001cd0: 4a78 ldr r2, [pc, #480] @ (8001eb4 <HAL_I2C_Init+0x280>)
|
|
8001cd2: fba2 2303 umull r2, r3, r2, r3
|
|
8001cd6: 0c9b lsrs r3, r3, #18
|
|
8001cd8: 60bb str r3, [r7, #8]
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
|
|
8001cda: 687b ldr r3, [r7, #4]
|
|
8001cdc: 681b ldr r3, [r3, #0]
|
|
8001cde: 685b ldr r3, [r3, #4]
|
|
8001ce0: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
8001ce4: 687b ldr r3, [r7, #4]
|
|
8001ce6: 681b ldr r3, [r3, #0]
|
|
8001ce8: 68ba ldr r2, [r7, #8]
|
|
8001cea: 430a orrs r2, r1
|
|
8001cec: 605a str r2, [r3, #4]
|
|
|
|
/*---------------------------- I2Cx TRISE Configuration --------------------*/
|
|
/* Configure I2Cx: Rise Time */
|
|
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
|
|
8001cee: 687b ldr r3, [r7, #4]
|
|
8001cf0: 681b ldr r3, [r3, #0]
|
|
8001cf2: 6a1b ldr r3, [r3, #32]
|
|
8001cf4: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
8001cf8: 687b ldr r3, [r7, #4]
|
|
8001cfa: 685b ldr r3, [r3, #4]
|
|
8001cfc: 4a6a ldr r2, [pc, #424] @ (8001ea8 <HAL_I2C_Init+0x274>)
|
|
8001cfe: 4293 cmp r3, r2
|
|
8001d00: d802 bhi.n 8001d08 <HAL_I2C_Init+0xd4>
|
|
8001d02: 68bb ldr r3, [r7, #8]
|
|
8001d04: 3301 adds r3, #1
|
|
8001d06: e009 b.n 8001d1c <HAL_I2C_Init+0xe8>
|
|
8001d08: 68bb ldr r3, [r7, #8]
|
|
8001d0a: f44f 7296 mov.w r2, #300 @ 0x12c
|
|
8001d0e: fb02 f303 mul.w r3, r2, r3
|
|
8001d12: 4a69 ldr r2, [pc, #420] @ (8001eb8 <HAL_I2C_Init+0x284>)
|
|
8001d14: fba2 2303 umull r2, r3, r2, r3
|
|
8001d18: 099b lsrs r3, r3, #6
|
|
8001d1a: 3301 adds r3, #1
|
|
8001d1c: 687a ldr r2, [r7, #4]
|
|
8001d1e: 6812 ldr r2, [r2, #0]
|
|
8001d20: 430b orrs r3, r1
|
|
8001d22: 6213 str r3, [r2, #32]
|
|
|
|
/*---------------------------- I2Cx CCR Configuration ----------------------*/
|
|
/* Configure I2Cx: Speed */
|
|
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
|
|
8001d24: 687b ldr r3, [r7, #4]
|
|
8001d26: 681b ldr r3, [r3, #0]
|
|
8001d28: 69db ldr r3, [r3, #28]
|
|
8001d2a: f423 424f bic.w r2, r3, #52992 @ 0xcf00
|
|
8001d2e: f022 02ff bic.w r2, r2, #255 @ 0xff
|
|
8001d32: 687b ldr r3, [r7, #4]
|
|
8001d34: 685b ldr r3, [r3, #4]
|
|
8001d36: 495c ldr r1, [pc, #368] @ (8001ea8 <HAL_I2C_Init+0x274>)
|
|
8001d38: 428b cmp r3, r1
|
|
8001d3a: d819 bhi.n 8001d70 <HAL_I2C_Init+0x13c>
|
|
8001d3c: 68fb ldr r3, [r7, #12]
|
|
8001d3e: 1e59 subs r1, r3, #1
|
|
8001d40: 687b ldr r3, [r7, #4]
|
|
8001d42: 685b ldr r3, [r3, #4]
|
|
8001d44: 005b lsls r3, r3, #1
|
|
8001d46: fbb1 f3f3 udiv r3, r1, r3
|
|
8001d4a: 1c59 adds r1, r3, #1
|
|
8001d4c: f640 73fc movw r3, #4092 @ 0xffc
|
|
8001d50: 400b ands r3, r1
|
|
8001d52: 2b00 cmp r3, #0
|
|
8001d54: d00a beq.n 8001d6c <HAL_I2C_Init+0x138>
|
|
8001d56: 68fb ldr r3, [r7, #12]
|
|
8001d58: 1e59 subs r1, r3, #1
|
|
8001d5a: 687b ldr r3, [r7, #4]
|
|
8001d5c: 685b ldr r3, [r3, #4]
|
|
8001d5e: 005b lsls r3, r3, #1
|
|
8001d60: fbb1 f3f3 udiv r3, r1, r3
|
|
8001d64: 3301 adds r3, #1
|
|
8001d66: f3c3 030b ubfx r3, r3, #0, #12
|
|
8001d6a: e051 b.n 8001e10 <HAL_I2C_Init+0x1dc>
|
|
8001d6c: 2304 movs r3, #4
|
|
8001d6e: e04f b.n 8001e10 <HAL_I2C_Init+0x1dc>
|
|
8001d70: 687b ldr r3, [r7, #4]
|
|
8001d72: 689b ldr r3, [r3, #8]
|
|
8001d74: 2b00 cmp r3, #0
|
|
8001d76: d111 bne.n 8001d9c <HAL_I2C_Init+0x168>
|
|
8001d78: 68fb ldr r3, [r7, #12]
|
|
8001d7a: 1e58 subs r0, r3, #1
|
|
8001d7c: 687b ldr r3, [r7, #4]
|
|
8001d7e: 6859 ldr r1, [r3, #4]
|
|
8001d80: 460b mov r3, r1
|
|
8001d82: 005b lsls r3, r3, #1
|
|
8001d84: 440b add r3, r1
|
|
8001d86: fbb0 f3f3 udiv r3, r0, r3
|
|
8001d8a: 3301 adds r3, #1
|
|
8001d8c: f3c3 030b ubfx r3, r3, #0, #12
|
|
8001d90: 2b00 cmp r3, #0
|
|
8001d92: bf0c ite eq
|
|
8001d94: 2301 moveq r3, #1
|
|
8001d96: 2300 movne r3, #0
|
|
8001d98: b2db uxtb r3, r3
|
|
8001d9a: e012 b.n 8001dc2 <HAL_I2C_Init+0x18e>
|
|
8001d9c: 68fb ldr r3, [r7, #12]
|
|
8001d9e: 1e58 subs r0, r3, #1
|
|
8001da0: 687b ldr r3, [r7, #4]
|
|
8001da2: 6859 ldr r1, [r3, #4]
|
|
8001da4: 460b mov r3, r1
|
|
8001da6: 009b lsls r3, r3, #2
|
|
8001da8: 440b add r3, r1
|
|
8001daa: 0099 lsls r1, r3, #2
|
|
8001dac: 440b add r3, r1
|
|
8001dae: fbb0 f3f3 udiv r3, r0, r3
|
|
8001db2: 3301 adds r3, #1
|
|
8001db4: f3c3 030b ubfx r3, r3, #0, #12
|
|
8001db8: 2b00 cmp r3, #0
|
|
8001dba: bf0c ite eq
|
|
8001dbc: 2301 moveq r3, #1
|
|
8001dbe: 2300 movne r3, #0
|
|
8001dc0: b2db uxtb r3, r3
|
|
8001dc2: 2b00 cmp r3, #0
|
|
8001dc4: d001 beq.n 8001dca <HAL_I2C_Init+0x196>
|
|
8001dc6: 2301 movs r3, #1
|
|
8001dc8: e022 b.n 8001e10 <HAL_I2C_Init+0x1dc>
|
|
8001dca: 687b ldr r3, [r7, #4]
|
|
8001dcc: 689b ldr r3, [r3, #8]
|
|
8001dce: 2b00 cmp r3, #0
|
|
8001dd0: d10e bne.n 8001df0 <HAL_I2C_Init+0x1bc>
|
|
8001dd2: 68fb ldr r3, [r7, #12]
|
|
8001dd4: 1e58 subs r0, r3, #1
|
|
8001dd6: 687b ldr r3, [r7, #4]
|
|
8001dd8: 6859 ldr r1, [r3, #4]
|
|
8001dda: 460b mov r3, r1
|
|
8001ddc: 005b lsls r3, r3, #1
|
|
8001dde: 440b add r3, r1
|
|
8001de0: fbb0 f3f3 udiv r3, r0, r3
|
|
8001de4: 3301 adds r3, #1
|
|
8001de6: f3c3 030b ubfx r3, r3, #0, #12
|
|
8001dea: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8001dee: e00f b.n 8001e10 <HAL_I2C_Init+0x1dc>
|
|
8001df0: 68fb ldr r3, [r7, #12]
|
|
8001df2: 1e58 subs r0, r3, #1
|
|
8001df4: 687b ldr r3, [r7, #4]
|
|
8001df6: 6859 ldr r1, [r3, #4]
|
|
8001df8: 460b mov r3, r1
|
|
8001dfa: 009b lsls r3, r3, #2
|
|
8001dfc: 440b add r3, r1
|
|
8001dfe: 0099 lsls r1, r3, #2
|
|
8001e00: 440b add r3, r1
|
|
8001e02: fbb0 f3f3 udiv r3, r0, r3
|
|
8001e06: 3301 adds r3, #1
|
|
8001e08: f3c3 030b ubfx r3, r3, #0, #12
|
|
8001e0c: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8001e10: 6879 ldr r1, [r7, #4]
|
|
8001e12: 6809 ldr r1, [r1, #0]
|
|
8001e14: 4313 orrs r3, r2
|
|
8001e16: 61cb str r3, [r1, #28]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
|
|
8001e18: 687b ldr r3, [r7, #4]
|
|
8001e1a: 681b ldr r3, [r3, #0]
|
|
8001e1c: 681b ldr r3, [r3, #0]
|
|
8001e1e: f023 01c0 bic.w r1, r3, #192 @ 0xc0
|
|
8001e22: 687b ldr r3, [r7, #4]
|
|
8001e24: 69da ldr r2, [r3, #28]
|
|
8001e26: 687b ldr r3, [r7, #4]
|
|
8001e28: 6a1b ldr r3, [r3, #32]
|
|
8001e2a: 431a orrs r2, r3
|
|
8001e2c: 687b ldr r3, [r7, #4]
|
|
8001e2e: 681b ldr r3, [r3, #0]
|
|
8001e30: 430a orrs r2, r1
|
|
8001e32: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Configure I2Cx: Own Address1 and addressing mode */
|
|
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
|
|
8001e34: 687b ldr r3, [r7, #4]
|
|
8001e36: 681b ldr r3, [r3, #0]
|
|
8001e38: 689b ldr r3, [r3, #8]
|
|
8001e3a: f423 4303 bic.w r3, r3, #33536 @ 0x8300
|
|
8001e3e: f023 03ff bic.w r3, r3, #255 @ 0xff
|
|
8001e42: 687a ldr r2, [r7, #4]
|
|
8001e44: 6911 ldr r1, [r2, #16]
|
|
8001e46: 687a ldr r2, [r7, #4]
|
|
8001e48: 68d2 ldr r2, [r2, #12]
|
|
8001e4a: 4311 orrs r1, r2
|
|
8001e4c: 687a ldr r2, [r7, #4]
|
|
8001e4e: 6812 ldr r2, [r2, #0]
|
|
8001e50: 430b orrs r3, r1
|
|
8001e52: 6093 str r3, [r2, #8]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
|
|
8001e54: 687b ldr r3, [r7, #4]
|
|
8001e56: 681b ldr r3, [r3, #0]
|
|
8001e58: 68db ldr r3, [r3, #12]
|
|
8001e5a: f023 01ff bic.w r1, r3, #255 @ 0xff
|
|
8001e5e: 687b ldr r3, [r7, #4]
|
|
8001e60: 695a ldr r2, [r3, #20]
|
|
8001e62: 687b ldr r3, [r7, #4]
|
|
8001e64: 699b ldr r3, [r3, #24]
|
|
8001e66: 431a orrs r2, r3
|
|
8001e68: 687b ldr r3, [r7, #4]
|
|
8001e6a: 681b ldr r3, [r3, #0]
|
|
8001e6c: 430a orrs r2, r1
|
|
8001e6e: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8001e70: 687b ldr r3, [r7, #4]
|
|
8001e72: 681b ldr r3, [r3, #0]
|
|
8001e74: 681a ldr r2, [r3, #0]
|
|
8001e76: 687b ldr r3, [r7, #4]
|
|
8001e78: 681b ldr r3, [r3, #0]
|
|
8001e7a: f042 0201 orr.w r2, r2, #1
|
|
8001e7e: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8001e80: 687b ldr r3, [r7, #4]
|
|
8001e82: 2200 movs r2, #0
|
|
8001e84: 641a str r2, [r3, #64] @ 0x40
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8001e86: 687b ldr r3, [r7, #4]
|
|
8001e88: 2220 movs r2, #32
|
|
8001e8a: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8001e8e: 687b ldr r3, [r7, #4]
|
|
8001e90: 2200 movs r2, #0
|
|
8001e92: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8001e94: 687b ldr r3, [r7, #4]
|
|
8001e96: 2200 movs r2, #0
|
|
8001e98: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
|
|
return HAL_OK;
|
|
8001e9c: 2300 movs r3, #0
|
|
}
|
|
8001e9e: 4618 mov r0, r3
|
|
8001ea0: 3710 adds r7, #16
|
|
8001ea2: 46bd mov sp, r7
|
|
8001ea4: bd80 pop {r7, pc}
|
|
8001ea6: bf00 nop
|
|
8001ea8: 000186a0 .word 0x000186a0
|
|
8001eac: 001e847f .word 0x001e847f
|
|
8001eb0: 003d08ff .word 0x003d08ff
|
|
8001eb4: 431bde83 .word 0x431bde83
|
|
8001eb8: 10624dd3 .word 0x10624dd3
|
|
|
|
08001ebc <HAL_PCD_Init>:
|
|
* parameters in the PCD_InitTypeDef and initialize the associated handle.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8001ebc: b580 push {r7, lr}
|
|
8001ebe: b086 sub sp, #24
|
|
8001ec0: af02 add r7, sp, #8
|
|
8001ec2: 6078 str r0, [r7, #4]
|
|
const USB_OTG_GlobalTypeDef *USBx;
|
|
#endif /* defined (USB_OTG_FS) */
|
|
uint8_t i;
|
|
|
|
/* Check the PCD handle allocation */
|
|
if (hpcd == NULL)
|
|
8001ec4: 687b ldr r3, [r7, #4]
|
|
8001ec6: 2b00 cmp r3, #0
|
|
8001ec8: d101 bne.n 8001ece <HAL_PCD_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001eca: 2301 movs r3, #1
|
|
8001ecc: e108 b.n 80020e0 <HAL_PCD_Init+0x224>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
|
|
|
|
#if defined (USB_OTG_FS)
|
|
USBx = hpcd->Instance;
|
|
8001ece: 687b ldr r3, [r7, #4]
|
|
8001ed0: 681b ldr r3, [r3, #0]
|
|
8001ed2: 60bb str r3, [r7, #8]
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
if (hpcd->State == HAL_PCD_STATE_RESET)
|
|
8001ed4: 687b ldr r3, [r7, #4]
|
|
8001ed6: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495
|
|
8001eda: b2db uxtb r3, r3
|
|
8001edc: 2b00 cmp r3, #0
|
|
8001ede: d106 bne.n 8001eee <HAL_PCD_Init+0x32>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hpcd->Lock = HAL_UNLOCKED;
|
|
8001ee0: 687b ldr r3, [r7, #4]
|
|
8001ee2: 2200 movs r2, #0
|
|
8001ee4: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
/* Init the low level hardware */
|
|
hpcd->MspInitCallback(hpcd);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_PCD_MspInit(hpcd);
|
|
8001ee8: 6878 ldr r0, [r7, #4]
|
|
8001eea: f006 ffed bl 8008ec8 <HAL_PCD_MspInit>
|
|
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
hpcd->State = HAL_PCD_STATE_BUSY;
|
|
8001eee: 687b ldr r3, [r7, #4]
|
|
8001ef0: 2203 movs r2, #3
|
|
8001ef2: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
|
|
#if defined (USB_OTG_FS)
|
|
/* Disable DMA mode for FS instance */
|
|
if (USBx == USB_OTG_FS)
|
|
8001ef6: 68bb ldr r3, [r7, #8]
|
|
8001ef8: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8001efc: d102 bne.n 8001f04 <HAL_PCD_Init+0x48>
|
|
{
|
|
hpcd->Init.dma_enable = 0U;
|
|
8001efe: 687b ldr r3, [r7, #4]
|
|
8001f00: 2200 movs r2, #0
|
|
8001f02: 719a strb r2, [r3, #6]
|
|
}
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
/* Disable the Interrupts */
|
|
__HAL_PCD_DISABLE(hpcd);
|
|
8001f04: 687b ldr r3, [r7, #4]
|
|
8001f06: 681b ldr r3, [r3, #0]
|
|
8001f08: 4618 mov r0, r3
|
|
8001f0a: f003 fece bl 8005caa <USB_DisableGlobalInt>
|
|
|
|
/*Init the Core (common init.) */
|
|
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8001f0e: 687b ldr r3, [r7, #4]
|
|
8001f10: 6818 ldr r0, [r3, #0]
|
|
8001f12: 687b ldr r3, [r7, #4]
|
|
8001f14: 7c1a ldrb r2, [r3, #16]
|
|
8001f16: f88d 2000 strb.w r2, [sp]
|
|
8001f1a: 3304 adds r3, #4
|
|
8001f1c: cb0e ldmia r3, {r1, r2, r3}
|
|
8001f1e: f003 fdad bl 8005a7c <USB_CoreInit>
|
|
8001f22: 4603 mov r3, r0
|
|
8001f24: 2b00 cmp r3, #0
|
|
8001f26: d005 beq.n 8001f34 <HAL_PCD_Init+0x78>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8001f28: 687b ldr r3, [r7, #4]
|
|
8001f2a: 2202 movs r2, #2
|
|
8001f2c: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8001f30: 2301 movs r3, #1
|
|
8001f32: e0d5 b.n 80020e0 <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
/* Force Device Mode */
|
|
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
|
|
8001f34: 687b ldr r3, [r7, #4]
|
|
8001f36: 681b ldr r3, [r3, #0]
|
|
8001f38: 2100 movs r1, #0
|
|
8001f3a: 4618 mov r0, r3
|
|
8001f3c: f003 fec6 bl 8005ccc <USB_SetCurrentMode>
|
|
8001f40: 4603 mov r3, r0
|
|
8001f42: 2b00 cmp r3, #0
|
|
8001f44: d005 beq.n 8001f52 <HAL_PCD_Init+0x96>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8001f46: 687b ldr r3, [r7, #4]
|
|
8001f48: 2202 movs r2, #2
|
|
8001f4a: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8001f4e: 2301 movs r3, #1
|
|
8001f50: e0c6 b.n 80020e0 <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
/* Init endpoints structures */
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001f52: 2300 movs r3, #0
|
|
8001f54: 73fb strb r3, [r7, #15]
|
|
8001f56: e04a b.n 8001fee <HAL_PCD_Init+0x132>
|
|
{
|
|
/* Init ep structure */
|
|
hpcd->IN_ep[i].is_in = 1U;
|
|
8001f58: 7bfa ldrb r2, [r7, #15]
|
|
8001f5a: 6879 ldr r1, [r7, #4]
|
|
8001f5c: 4613 mov r3, r2
|
|
8001f5e: 00db lsls r3, r3, #3
|
|
8001f60: 4413 add r3, r2
|
|
8001f62: 009b lsls r3, r3, #2
|
|
8001f64: 440b add r3, r1
|
|
8001f66: 3315 adds r3, #21
|
|
8001f68: 2201 movs r2, #1
|
|
8001f6a: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].num = i;
|
|
8001f6c: 7bfa ldrb r2, [r7, #15]
|
|
8001f6e: 6879 ldr r1, [r7, #4]
|
|
8001f70: 4613 mov r3, r2
|
|
8001f72: 00db lsls r3, r3, #3
|
|
8001f74: 4413 add r3, r2
|
|
8001f76: 009b lsls r3, r3, #2
|
|
8001f78: 440b add r3, r1
|
|
8001f7a: 3314 adds r3, #20
|
|
8001f7c: 7bfa ldrb r2, [r7, #15]
|
|
8001f7e: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].tx_fifo_num = i;
|
|
8001f80: 7bfa ldrb r2, [r7, #15]
|
|
8001f82: 7bfb ldrb r3, [r7, #15]
|
|
8001f84: b298 uxth r0, r3
|
|
8001f86: 6879 ldr r1, [r7, #4]
|
|
8001f88: 4613 mov r3, r2
|
|
8001f8a: 00db lsls r3, r3, #3
|
|
8001f8c: 4413 add r3, r2
|
|
8001f8e: 009b lsls r3, r3, #2
|
|
8001f90: 440b add r3, r1
|
|
8001f92: 332e adds r3, #46 @ 0x2e
|
|
8001f94: 4602 mov r2, r0
|
|
8001f96: 801a strh r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
|
|
8001f98: 7bfa ldrb r2, [r7, #15]
|
|
8001f9a: 6879 ldr r1, [r7, #4]
|
|
8001f9c: 4613 mov r3, r2
|
|
8001f9e: 00db lsls r3, r3, #3
|
|
8001fa0: 4413 add r3, r2
|
|
8001fa2: 009b lsls r3, r3, #2
|
|
8001fa4: 440b add r3, r1
|
|
8001fa6: 3318 adds r3, #24
|
|
8001fa8: 2200 movs r2, #0
|
|
8001faa: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].maxpacket = 0U;
|
|
8001fac: 7bfa ldrb r2, [r7, #15]
|
|
8001fae: 6879 ldr r1, [r7, #4]
|
|
8001fb0: 4613 mov r3, r2
|
|
8001fb2: 00db lsls r3, r3, #3
|
|
8001fb4: 4413 add r3, r2
|
|
8001fb6: 009b lsls r3, r3, #2
|
|
8001fb8: 440b add r3, r1
|
|
8001fba: 331c adds r3, #28
|
|
8001fbc: 2200 movs r2, #0
|
|
8001fbe: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_buff = 0U;
|
|
8001fc0: 7bfa ldrb r2, [r7, #15]
|
|
8001fc2: 6879 ldr r1, [r7, #4]
|
|
8001fc4: 4613 mov r3, r2
|
|
8001fc6: 00db lsls r3, r3, #3
|
|
8001fc8: 4413 add r3, r2
|
|
8001fca: 009b lsls r3, r3, #2
|
|
8001fcc: 440b add r3, r1
|
|
8001fce: 3320 adds r3, #32
|
|
8001fd0: 2200 movs r2, #0
|
|
8001fd2: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_len = 0U;
|
|
8001fd4: 7bfa ldrb r2, [r7, #15]
|
|
8001fd6: 6879 ldr r1, [r7, #4]
|
|
8001fd8: 4613 mov r3, r2
|
|
8001fda: 00db lsls r3, r3, #3
|
|
8001fdc: 4413 add r3, r2
|
|
8001fde: 009b lsls r3, r3, #2
|
|
8001fe0: 440b add r3, r1
|
|
8001fe2: 3324 adds r3, #36 @ 0x24
|
|
8001fe4: 2200 movs r2, #0
|
|
8001fe6: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001fe8: 7bfb ldrb r3, [r7, #15]
|
|
8001fea: 3301 adds r3, #1
|
|
8001fec: 73fb strb r3, [r7, #15]
|
|
8001fee: 687b ldr r3, [r7, #4]
|
|
8001ff0: 791b ldrb r3, [r3, #4]
|
|
8001ff2: 7bfa ldrb r2, [r7, #15]
|
|
8001ff4: 429a cmp r2, r3
|
|
8001ff6: d3af bcc.n 8001f58 <HAL_PCD_Init+0x9c>
|
|
}
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001ff8: 2300 movs r3, #0
|
|
8001ffa: 73fb strb r3, [r7, #15]
|
|
8001ffc: e044 b.n 8002088 <HAL_PCD_Init+0x1cc>
|
|
{
|
|
hpcd->OUT_ep[i].is_in = 0U;
|
|
8001ffe: 7bfa ldrb r2, [r7, #15]
|
|
8002000: 6879 ldr r1, [r7, #4]
|
|
8002002: 4613 mov r3, r2
|
|
8002004: 00db lsls r3, r3, #3
|
|
8002006: 4413 add r3, r2
|
|
8002008: 009b lsls r3, r3, #2
|
|
800200a: 440b add r3, r1
|
|
800200c: f203 2355 addw r3, r3, #597 @ 0x255
|
|
8002010: 2200 movs r2, #0
|
|
8002012: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].num = i;
|
|
8002014: 7bfa ldrb r2, [r7, #15]
|
|
8002016: 6879 ldr r1, [r7, #4]
|
|
8002018: 4613 mov r3, r2
|
|
800201a: 00db lsls r3, r3, #3
|
|
800201c: 4413 add r3, r2
|
|
800201e: 009b lsls r3, r3, #2
|
|
8002020: 440b add r3, r1
|
|
8002022: f503 7315 add.w r3, r3, #596 @ 0x254
|
|
8002026: 7bfa ldrb r2, [r7, #15]
|
|
8002028: 701a strb r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
|
|
800202a: 7bfa ldrb r2, [r7, #15]
|
|
800202c: 6879 ldr r1, [r7, #4]
|
|
800202e: 4613 mov r3, r2
|
|
8002030: 00db lsls r3, r3, #3
|
|
8002032: 4413 add r3, r2
|
|
8002034: 009b lsls r3, r3, #2
|
|
8002036: 440b add r3, r1
|
|
8002038: f503 7316 add.w r3, r3, #600 @ 0x258
|
|
800203c: 2200 movs r2, #0
|
|
800203e: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].maxpacket = 0U;
|
|
8002040: 7bfa ldrb r2, [r7, #15]
|
|
8002042: 6879 ldr r1, [r7, #4]
|
|
8002044: 4613 mov r3, r2
|
|
8002046: 00db lsls r3, r3, #3
|
|
8002048: 4413 add r3, r2
|
|
800204a: 009b lsls r3, r3, #2
|
|
800204c: 440b add r3, r1
|
|
800204e: f503 7317 add.w r3, r3, #604 @ 0x25c
|
|
8002052: 2200 movs r2, #0
|
|
8002054: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_buff = 0U;
|
|
8002056: 7bfa ldrb r2, [r7, #15]
|
|
8002058: 6879 ldr r1, [r7, #4]
|
|
800205a: 4613 mov r3, r2
|
|
800205c: 00db lsls r3, r3, #3
|
|
800205e: 4413 add r3, r2
|
|
8002060: 009b lsls r3, r3, #2
|
|
8002062: 440b add r3, r1
|
|
8002064: f503 7318 add.w r3, r3, #608 @ 0x260
|
|
8002068: 2200 movs r2, #0
|
|
800206a: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_len = 0U;
|
|
800206c: 7bfa ldrb r2, [r7, #15]
|
|
800206e: 6879 ldr r1, [r7, #4]
|
|
8002070: 4613 mov r3, r2
|
|
8002072: 00db lsls r3, r3, #3
|
|
8002074: 4413 add r3, r2
|
|
8002076: 009b lsls r3, r3, #2
|
|
8002078: 440b add r3, r1
|
|
800207a: f503 7319 add.w r3, r3, #612 @ 0x264
|
|
800207e: 2200 movs r2, #0
|
|
8002080: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8002082: 7bfb ldrb r3, [r7, #15]
|
|
8002084: 3301 adds r3, #1
|
|
8002086: 73fb strb r3, [r7, #15]
|
|
8002088: 687b ldr r3, [r7, #4]
|
|
800208a: 791b ldrb r3, [r3, #4]
|
|
800208c: 7bfa ldrb r2, [r7, #15]
|
|
800208e: 429a cmp r2, r3
|
|
8002090: d3b5 bcc.n 8001ffe <HAL_PCD_Init+0x142>
|
|
}
|
|
|
|
/* Init Device */
|
|
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8002092: 687b ldr r3, [r7, #4]
|
|
8002094: 6818 ldr r0, [r3, #0]
|
|
8002096: 687b ldr r3, [r7, #4]
|
|
8002098: 7c1a ldrb r2, [r3, #16]
|
|
800209a: f88d 2000 strb.w r2, [sp]
|
|
800209e: 3304 adds r3, #4
|
|
80020a0: cb0e ldmia r3, {r1, r2, r3}
|
|
80020a2: f003 fe5f bl 8005d64 <USB_DevInit>
|
|
80020a6: 4603 mov r3, r0
|
|
80020a8: 2b00 cmp r3, #0
|
|
80020aa: d005 beq.n 80020b8 <HAL_PCD_Init+0x1fc>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
80020ac: 687b ldr r3, [r7, #4]
|
|
80020ae: 2202 movs r2, #2
|
|
80020b0: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
80020b4: 2301 movs r3, #1
|
|
80020b6: e013 b.n 80020e0 <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
hpcd->USB_Address = 0U;
|
|
80020b8: 687b ldr r3, [r7, #4]
|
|
80020ba: 2200 movs r2, #0
|
|
80020bc: 745a strb r2, [r3, #17]
|
|
hpcd->State = HAL_PCD_STATE_READY;
|
|
80020be: 687b ldr r3, [r7, #4]
|
|
80020c0: 2201 movs r2, #1
|
|
80020c2: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* Activate LPM */
|
|
if (hpcd->Init.lpm_enable == 1U)
|
|
80020c6: 687b ldr r3, [r7, #4]
|
|
80020c8: 7b1b ldrb r3, [r3, #12]
|
|
80020ca: 2b01 cmp r3, #1
|
|
80020cc: d102 bne.n 80020d4 <HAL_PCD_Init+0x218>
|
|
{
|
|
(void)HAL_PCDEx_ActivateLPM(hpcd);
|
|
80020ce: 6878 ldr r0, [r7, #4]
|
|
80020d0: f001 f956 bl 8003380 <HAL_PCDEx_ActivateLPM>
|
|
}
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
(void)USB_DevDisconnect(hpcd->Instance);
|
|
80020d4: 687b ldr r3, [r7, #4]
|
|
80020d6: 681b ldr r3, [r3, #0]
|
|
80020d8: 4618 mov r0, r3
|
|
80020da: f004 fe9c bl 8006e16 <USB_DevDisconnect>
|
|
|
|
return HAL_OK;
|
|
80020de: 2300 movs r3, #0
|
|
}
|
|
80020e0: 4618 mov r0, r3
|
|
80020e2: 3710 adds r7, #16
|
|
80020e4: 46bd mov sp, r7
|
|
80020e6: bd80 pop {r7, pc}
|
|
|
|
080020e8 <HAL_PCD_Start>:
|
|
* @brief Start the USB device
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
80020e8: b580 push {r7, lr}
|
|
80020ea: b084 sub sp, #16
|
|
80020ec: af00 add r7, sp, #0
|
|
80020ee: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
80020f0: 687b ldr r3, [r7, #4]
|
|
80020f2: 681b ldr r3, [r3, #0]
|
|
80020f4: 60fb str r3, [r7, #12]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
80020f6: 687b ldr r3, [r7, #4]
|
|
80020f8: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
80020fc: 2b01 cmp r3, #1
|
|
80020fe: d101 bne.n 8002104 <HAL_PCD_Start+0x1c>
|
|
8002100: 2302 movs r3, #2
|
|
8002102: e022 b.n 800214a <HAL_PCD_Start+0x62>
|
|
8002104: 687b ldr r3, [r7, #4]
|
|
8002106: 2201 movs r2, #1
|
|
8002108: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
|
|
800210c: 68fb ldr r3, [r7, #12]
|
|
800210e: 68db ldr r3, [r3, #12]
|
|
8002110: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8002114: 2b00 cmp r3, #0
|
|
8002116: d009 beq.n 800212c <HAL_PCD_Start+0x44>
|
|
(hpcd->Init.battery_charging_enable == 1U))
|
|
8002118: 687b ldr r3, [r7, #4]
|
|
800211a: 7b5b ldrb r3, [r3, #13]
|
|
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
|
|
800211c: 2b01 cmp r3, #1
|
|
800211e: d105 bne.n 800212c <HAL_PCD_Start+0x44>
|
|
{
|
|
/* Enable USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
8002120: 68fb ldr r3, [r7, #12]
|
|
8002122: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8002124: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
8002128: 68fb ldr r3, [r7, #12]
|
|
800212a: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
|
|
__HAL_PCD_ENABLE(hpcd);
|
|
800212c: 687b ldr r3, [r7, #4]
|
|
800212e: 681b ldr r3, [r3, #0]
|
|
8002130: 4618 mov r0, r3
|
|
8002132: f003 fda9 bl 8005c88 <USB_EnableGlobalInt>
|
|
(void)USB_DevConnect(hpcd->Instance);
|
|
8002136: 687b ldr r3, [r7, #4]
|
|
8002138: 681b ldr r3, [r3, #0]
|
|
800213a: 4618 mov r0, r3
|
|
800213c: f004 fe4a bl 8006dd4 <USB_DevConnect>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002140: 687b ldr r3, [r7, #4]
|
|
8002142: 2200 movs r2, #0
|
|
8002144: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8002148: 2300 movs r3, #0
|
|
}
|
|
800214a: 4618 mov r0, r3
|
|
800214c: 3710 adds r7, #16
|
|
800214e: 46bd mov sp, r7
|
|
8002150: bd80 pop {r7, pc}
|
|
|
|
08002152 <HAL_PCD_IRQHandler>:
|
|
* @brief Handles PCD interrupt request.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8002152: b590 push {r4, r7, lr}
|
|
8002154: b08d sub sp, #52 @ 0x34
|
|
8002156: af00 add r7, sp, #0
|
|
8002158: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
800215a: 687b ldr r3, [r7, #4]
|
|
800215c: 681b ldr r3, [r3, #0]
|
|
800215e: 623b str r3, [r7, #32]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8002160: 6a3b ldr r3, [r7, #32]
|
|
8002162: 61fb str r3, [r7, #28]
|
|
uint32_t epnum;
|
|
uint32_t fifoemptymsk;
|
|
uint32_t RegVal;
|
|
|
|
/* ensure that we are in device mode */
|
|
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
|
|
8002164: 687b ldr r3, [r7, #4]
|
|
8002166: 681b ldr r3, [r3, #0]
|
|
8002168: 4618 mov r0, r3
|
|
800216a: f004 ff08 bl 8006f7e <USB_GetMode>
|
|
800216e: 4603 mov r3, r0
|
|
8002170: 2b00 cmp r3, #0
|
|
8002172: f040 84b9 bne.w 8002ae8 <HAL_PCD_IRQHandler+0x996>
|
|
{
|
|
/* avoid spurious interrupt */
|
|
if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
|
|
8002176: 687b ldr r3, [r7, #4]
|
|
8002178: 681b ldr r3, [r3, #0]
|
|
800217a: 4618 mov r0, r3
|
|
800217c: f004 fe6c bl 8006e58 <USB_ReadInterrupts>
|
|
8002180: 4603 mov r3, r0
|
|
8002182: 2b00 cmp r3, #0
|
|
8002184: f000 84af beq.w 8002ae6 <HAL_PCD_IRQHandler+0x994>
|
|
{
|
|
return;
|
|
}
|
|
|
|
/* store current frame number */
|
|
hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos;
|
|
8002188: 69fb ldr r3, [r7, #28]
|
|
800218a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800218e: 689b ldr r3, [r3, #8]
|
|
8002190: 0a1b lsrs r3, r3, #8
|
|
8002192: f3c3 020d ubfx r2, r3, #0, #14
|
|
8002196: 687b ldr r3, [r7, #4]
|
|
8002198: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
|
|
800219c: 687b ldr r3, [r7, #4]
|
|
800219e: 681b ldr r3, [r3, #0]
|
|
80021a0: 4618 mov r0, r3
|
|
80021a2: f004 fe59 bl 8006e58 <USB_ReadInterrupts>
|
|
80021a6: 4603 mov r3, r0
|
|
80021a8: f003 0302 and.w r3, r3, #2
|
|
80021ac: 2b02 cmp r3, #2
|
|
80021ae: d107 bne.n 80021c0 <HAL_PCD_IRQHandler+0x6e>
|
|
{
|
|
/* incorrect mode, acknowledge the interrupt */
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
|
|
80021b0: 687b ldr r3, [r7, #4]
|
|
80021b2: 681b ldr r3, [r3, #0]
|
|
80021b4: 695a ldr r2, [r3, #20]
|
|
80021b6: 687b ldr r3, [r7, #4]
|
|
80021b8: 681b ldr r3, [r3, #0]
|
|
80021ba: f002 0202 and.w r2, r2, #2
|
|
80021be: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle RxQLevel Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
|
|
80021c0: 687b ldr r3, [r7, #4]
|
|
80021c2: 681b ldr r3, [r3, #0]
|
|
80021c4: 4618 mov r0, r3
|
|
80021c6: f004 fe47 bl 8006e58 <USB_ReadInterrupts>
|
|
80021ca: 4603 mov r3, r0
|
|
80021cc: f003 0310 and.w r3, r3, #16
|
|
80021d0: 2b10 cmp r3, #16
|
|
80021d2: d161 bne.n 8002298 <HAL_PCD_IRQHandler+0x146>
|
|
{
|
|
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
80021d4: 687b ldr r3, [r7, #4]
|
|
80021d6: 681b ldr r3, [r3, #0]
|
|
80021d8: 699a ldr r2, [r3, #24]
|
|
80021da: 687b ldr r3, [r7, #4]
|
|
80021dc: 681b ldr r3, [r3, #0]
|
|
80021de: f022 0210 bic.w r2, r2, #16
|
|
80021e2: 619a str r2, [r3, #24]
|
|
|
|
RegVal = USBx->GRXSTSP;
|
|
80021e4: 6a3b ldr r3, [r7, #32]
|
|
80021e6: 6a1b ldr r3, [r3, #32]
|
|
80021e8: 61bb str r3, [r7, #24]
|
|
|
|
ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM];
|
|
80021ea: 69bb ldr r3, [r7, #24]
|
|
80021ec: f003 020f and.w r2, r3, #15
|
|
80021f0: 4613 mov r3, r2
|
|
80021f2: 00db lsls r3, r3, #3
|
|
80021f4: 4413 add r3, r2
|
|
80021f6: 009b lsls r3, r3, #2
|
|
80021f8: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
80021fc: 687a ldr r2, [r7, #4]
|
|
80021fe: 4413 add r3, r2
|
|
8002200: 3304 adds r3, #4
|
|
8002202: 617b str r3, [r7, #20]
|
|
|
|
if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
|
|
8002204: 69bb ldr r3, [r7, #24]
|
|
8002206: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
|
|
800220a: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
800220e: d124 bne.n 800225a <HAL_PCD_IRQHandler+0x108>
|
|
{
|
|
if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U)
|
|
8002210: 69ba ldr r2, [r7, #24]
|
|
8002212: f647 73f0 movw r3, #32752 @ 0x7ff0
|
|
8002216: 4013 ands r3, r2
|
|
8002218: 2b00 cmp r3, #0
|
|
800221a: d035 beq.n 8002288 <HAL_PCD_IRQHandler+0x136>
|
|
{
|
|
(void)USB_ReadPacket(USBx, ep->xfer_buff,
|
|
800221c: 697b ldr r3, [r7, #20]
|
|
800221e: 68d9 ldr r1, [r3, #12]
|
|
(uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4));
|
|
8002220: 69bb ldr r3, [r7, #24]
|
|
8002222: 091b lsrs r3, r3, #4
|
|
8002224: b29b uxth r3, r3
|
|
(void)USB_ReadPacket(USBx, ep->xfer_buff,
|
|
8002226: f3c3 030a ubfx r3, r3, #0, #11
|
|
800222a: b29b uxth r3, r3
|
|
800222c: 461a mov r2, r3
|
|
800222e: 6a38 ldr r0, [r7, #32]
|
|
8002230: f004 fc7e bl 8006b30 <USB_ReadPacket>
|
|
|
|
ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8002234: 697b ldr r3, [r7, #20]
|
|
8002236: 68da ldr r2, [r3, #12]
|
|
8002238: 69bb ldr r3, [r7, #24]
|
|
800223a: 091b lsrs r3, r3, #4
|
|
800223c: f3c3 030a ubfx r3, r3, #0, #11
|
|
8002240: 441a add r2, r3
|
|
8002242: 697b ldr r3, [r7, #20]
|
|
8002244: 60da str r2, [r3, #12]
|
|
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8002246: 697b ldr r3, [r7, #20]
|
|
8002248: 695a ldr r2, [r3, #20]
|
|
800224a: 69bb ldr r3, [r7, #24]
|
|
800224c: 091b lsrs r3, r3, #4
|
|
800224e: f3c3 030a ubfx r3, r3, #0, #11
|
|
8002252: 441a add r2, r3
|
|
8002254: 697b ldr r3, [r7, #20]
|
|
8002256: 615a str r2, [r3, #20]
|
|
8002258: e016 b.n 8002288 <HAL_PCD_IRQHandler+0x136>
|
|
}
|
|
}
|
|
else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
|
|
800225a: 69bb ldr r3, [r7, #24]
|
|
800225c: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
|
|
8002260: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000
|
|
8002264: d110 bne.n 8002288 <HAL_PCD_IRQHandler+0x136>
|
|
{
|
|
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
|
|
8002266: 687b ldr r3, [r7, #4]
|
|
8002268: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
800226c: 2208 movs r2, #8
|
|
800226e: 4619 mov r1, r3
|
|
8002270: 6a38 ldr r0, [r7, #32]
|
|
8002272: f004 fc5d bl 8006b30 <USB_ReadPacket>
|
|
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8002276: 697b ldr r3, [r7, #20]
|
|
8002278: 695a ldr r2, [r3, #20]
|
|
800227a: 69bb ldr r3, [r7, #24]
|
|
800227c: 091b lsrs r3, r3, #4
|
|
800227e: f3c3 030a ubfx r3, r3, #0, #11
|
|
8002282: 441a add r2, r3
|
|
8002284: 697b ldr r3, [r7, #20]
|
|
8002286: 615a str r2, [r3, #20]
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
|
|
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
8002288: 687b ldr r3, [r7, #4]
|
|
800228a: 681b ldr r3, [r3, #0]
|
|
800228c: 699a ldr r2, [r3, #24]
|
|
800228e: 687b ldr r3, [r7, #4]
|
|
8002290: 681b ldr r3, [r3, #0]
|
|
8002292: f042 0210 orr.w r2, r2, #16
|
|
8002296: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
|
|
8002298: 687b ldr r3, [r7, #4]
|
|
800229a: 681b ldr r3, [r3, #0]
|
|
800229c: 4618 mov r0, r3
|
|
800229e: f004 fddb bl 8006e58 <USB_ReadInterrupts>
|
|
80022a2: 4603 mov r3, r0
|
|
80022a4: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
80022a8: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
|
|
80022ac: f040 80a7 bne.w 80023fe <HAL_PCD_IRQHandler+0x2ac>
|
|
{
|
|
epnum = 0U;
|
|
80022b0: 2300 movs r3, #0
|
|
80022b2: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Read in the device interrupt bits */
|
|
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
|
|
80022b4: 687b ldr r3, [r7, #4]
|
|
80022b6: 681b ldr r3, [r3, #0]
|
|
80022b8: 4618 mov r0, r3
|
|
80022ba: f004 fde0 bl 8006e7e <USB_ReadDevAllOutEpInterrupt>
|
|
80022be: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
while (ep_intr != 0U)
|
|
80022c0: e099 b.n 80023f6 <HAL_PCD_IRQHandler+0x2a4>
|
|
{
|
|
if ((ep_intr & 0x1U) != 0U)
|
|
80022c2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80022c4: f003 0301 and.w r3, r3, #1
|
|
80022c8: 2b00 cmp r3, #0
|
|
80022ca: f000 808e beq.w 80023ea <HAL_PCD_IRQHandler+0x298>
|
|
{
|
|
epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
|
|
80022ce: 687b ldr r3, [r7, #4]
|
|
80022d0: 681b ldr r3, [r3, #0]
|
|
80022d2: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80022d4: b2d2 uxtb r2, r2
|
|
80022d6: 4611 mov r1, r2
|
|
80022d8: 4618 mov r0, r3
|
|
80022da: f004 fe04 bl 8006ee6 <USB_ReadDevOutEPInterrupt>
|
|
80022de: 6138 str r0, [r7, #16]
|
|
|
|
if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
|
|
80022e0: 693b ldr r3, [r7, #16]
|
|
80022e2: f003 0301 and.w r3, r3, #1
|
|
80022e6: 2b00 cmp r3, #0
|
|
80022e8: d00c beq.n 8002304 <HAL_PCD_IRQHandler+0x1b2>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
|
|
80022ea: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80022ec: 015a lsls r2, r3, #5
|
|
80022ee: 69fb ldr r3, [r7, #28]
|
|
80022f0: 4413 add r3, r2
|
|
80022f2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80022f6: 461a mov r2, r3
|
|
80022f8: 2301 movs r3, #1
|
|
80022fa: 6093 str r3, [r2, #8]
|
|
(void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
|
|
80022fc: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
80022fe: 6878 ldr r0, [r7, #4]
|
|
8002300: f000 feb8 bl 8003074 <PCD_EP_OutXfrComplete_int>
|
|
}
|
|
|
|
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
|
|
8002304: 693b ldr r3, [r7, #16]
|
|
8002306: f003 0308 and.w r3, r3, #8
|
|
800230a: 2b00 cmp r3, #0
|
|
800230c: d00c beq.n 8002328 <HAL_PCD_IRQHandler+0x1d6>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
|
|
800230e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002310: 015a lsls r2, r3, #5
|
|
8002312: 69fb ldr r3, [r7, #28]
|
|
8002314: 4413 add r3, r2
|
|
8002316: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800231a: 461a mov r2, r3
|
|
800231c: 2308 movs r3, #8
|
|
800231e: 6093 str r3, [r2, #8]
|
|
/* Class B setup phase done for previous decoded setup */
|
|
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
|
|
8002320: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8002322: 6878 ldr r0, [r7, #4]
|
|
8002324: f000 ff8e bl 8003244 <PCD_EP_OutSetupPacket_int>
|
|
}
|
|
|
|
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
|
|
8002328: 693b ldr r3, [r7, #16]
|
|
800232a: f003 0310 and.w r3, r3, #16
|
|
800232e: 2b00 cmp r3, #0
|
|
8002330: d008 beq.n 8002344 <HAL_PCD_IRQHandler+0x1f2>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
|
|
8002332: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002334: 015a lsls r2, r3, #5
|
|
8002336: 69fb ldr r3, [r7, #28]
|
|
8002338: 4413 add r3, r2
|
|
800233a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800233e: 461a mov r2, r3
|
|
8002340: 2310 movs r3, #16
|
|
8002342: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear OUT Endpoint disable interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
|
|
8002344: 693b ldr r3, [r7, #16]
|
|
8002346: f003 0302 and.w r3, r3, #2
|
|
800234a: 2b00 cmp r3, #0
|
|
800234c: d030 beq.n 80023b0 <HAL_PCD_IRQHandler+0x25e>
|
|
{
|
|
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF)
|
|
800234e: 6a3b ldr r3, [r7, #32]
|
|
8002350: 695b ldr r3, [r3, #20]
|
|
8002352: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002356: 2b80 cmp r3, #128 @ 0x80
|
|
8002358: d109 bne.n 800236e <HAL_PCD_IRQHandler+0x21c>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
|
|
800235a: 69fb ldr r3, [r7, #28]
|
|
800235c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002360: 685b ldr r3, [r3, #4]
|
|
8002362: 69fa ldr r2, [r7, #28]
|
|
8002364: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8002368: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
800236c: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
ep = &hpcd->OUT_ep[epnum];
|
|
800236e: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002370: 4613 mov r3, r2
|
|
8002372: 00db lsls r3, r3, #3
|
|
8002374: 4413 add r3, r2
|
|
8002376: 009b lsls r3, r3, #2
|
|
8002378: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
800237c: 687a ldr r2, [r7, #4]
|
|
800237e: 4413 add r3, r2
|
|
8002380: 3304 adds r3, #4
|
|
8002382: 617b str r3, [r7, #20]
|
|
|
|
if (ep->is_iso_incomplete == 1U)
|
|
8002384: 697b ldr r3, [r7, #20]
|
|
8002386: 78db ldrb r3, [r3, #3]
|
|
8002388: 2b01 cmp r3, #1
|
|
800238a: d108 bne.n 800239e <HAL_PCD_IRQHandler+0x24c>
|
|
{
|
|
ep->is_iso_incomplete = 0U;
|
|
800238c: 697b ldr r3, [r7, #20]
|
|
800238e: 2200 movs r2, #0
|
|
8002390: 70da strb r2, [r3, #3]
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
8002392: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002394: b2db uxtb r3, r3
|
|
8002396: 4619 mov r1, r3
|
|
8002398: 6878 ldr r0, [r7, #4]
|
|
800239a: f006 feb1 bl 8009100 <HAL_PCD_ISOOUTIncompleteCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
|
|
800239e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80023a0: 015a lsls r2, r3, #5
|
|
80023a2: 69fb ldr r3, [r7, #28]
|
|
80023a4: 4413 add r3, r2
|
|
80023a6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80023aa: 461a mov r2, r3
|
|
80023ac: 2302 movs r3, #2
|
|
80023ae: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear Status Phase Received interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
|
|
80023b0: 693b ldr r3, [r7, #16]
|
|
80023b2: f003 0320 and.w r3, r3, #32
|
|
80023b6: 2b00 cmp r3, #0
|
|
80023b8: d008 beq.n 80023cc <HAL_PCD_IRQHandler+0x27a>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
80023ba: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80023bc: 015a lsls r2, r3, #5
|
|
80023be: 69fb ldr r3, [r7, #28]
|
|
80023c0: 4413 add r3, r2
|
|
80023c2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80023c6: 461a mov r2, r3
|
|
80023c8: 2320 movs r3, #32
|
|
80023ca: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear OUT NAK interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
|
|
80023cc: 693b ldr r3, [r7, #16]
|
|
80023ce: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
80023d2: 2b00 cmp r3, #0
|
|
80023d4: d009 beq.n 80023ea <HAL_PCD_IRQHandler+0x298>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
|
|
80023d6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80023d8: 015a lsls r2, r3, #5
|
|
80023da: 69fb ldr r3, [r7, #28]
|
|
80023dc: 4413 add r3, r2
|
|
80023de: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80023e2: 461a mov r2, r3
|
|
80023e4: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
80023e8: 6093 str r3, [r2, #8]
|
|
}
|
|
}
|
|
epnum++;
|
|
80023ea: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80023ec: 3301 adds r3, #1
|
|
80023ee: 627b str r3, [r7, #36] @ 0x24
|
|
ep_intr >>= 1U;
|
|
80023f0: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80023f2: 085b lsrs r3, r3, #1
|
|
80023f4: 62bb str r3, [r7, #40] @ 0x28
|
|
while (ep_intr != 0U)
|
|
80023f6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80023f8: 2b00 cmp r3, #0
|
|
80023fa: f47f af62 bne.w 80022c2 <HAL_PCD_IRQHandler+0x170>
|
|
}
|
|
}
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
|
|
80023fe: 687b ldr r3, [r7, #4]
|
|
8002400: 681b ldr r3, [r3, #0]
|
|
8002402: 4618 mov r0, r3
|
|
8002404: f004 fd28 bl 8006e58 <USB_ReadInterrupts>
|
|
8002408: 4603 mov r3, r0
|
|
800240a: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
800240e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
8002412: f040 80db bne.w 80025cc <HAL_PCD_IRQHandler+0x47a>
|
|
{
|
|
/* Read in the device interrupt bits */
|
|
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
|
|
8002416: 687b ldr r3, [r7, #4]
|
|
8002418: 681b ldr r3, [r3, #0]
|
|
800241a: 4618 mov r0, r3
|
|
800241c: f004 fd49 bl 8006eb2 <USB_ReadDevAllInEpInterrupt>
|
|
8002420: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
epnum = 0U;
|
|
8002422: 2300 movs r3, #0
|
|
8002424: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
while (ep_intr != 0U)
|
|
8002426: e0cd b.n 80025c4 <HAL_PCD_IRQHandler+0x472>
|
|
{
|
|
if ((ep_intr & 0x1U) != 0U) /* In ITR */
|
|
8002428: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800242a: f003 0301 and.w r3, r3, #1
|
|
800242e: 2b00 cmp r3, #0
|
|
8002430: f000 80c2 beq.w 80025b8 <HAL_PCD_IRQHandler+0x466>
|
|
{
|
|
epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
|
|
8002434: 687b ldr r3, [r7, #4]
|
|
8002436: 681b ldr r3, [r3, #0]
|
|
8002438: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800243a: b2d2 uxtb r2, r2
|
|
800243c: 4611 mov r1, r2
|
|
800243e: 4618 mov r0, r3
|
|
8002440: f004 fd6f bl 8006f22 <USB_ReadDevInEPInterrupt>
|
|
8002444: 6138 str r0, [r7, #16]
|
|
|
|
if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
|
|
8002446: 693b ldr r3, [r7, #16]
|
|
8002448: f003 0301 and.w r3, r3, #1
|
|
800244c: 2b00 cmp r3, #0
|
|
800244e: d057 beq.n 8002500 <HAL_PCD_IRQHandler+0x3ae>
|
|
{
|
|
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
|
|
8002450: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002452: f003 030f and.w r3, r3, #15
|
|
8002456: 2201 movs r2, #1
|
|
8002458: fa02 f303 lsl.w r3, r2, r3
|
|
800245c: 60fb str r3, [r7, #12]
|
|
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
|
|
800245e: 69fb ldr r3, [r7, #28]
|
|
8002460: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002464: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8002466: 68fb ldr r3, [r7, #12]
|
|
8002468: 43db mvns r3, r3
|
|
800246a: 69f9 ldr r1, [r7, #28]
|
|
800246c: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8002470: 4013 ands r3, r2
|
|
8002472: 634b str r3, [r1, #52] @ 0x34
|
|
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
|
|
8002474: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002476: 015a lsls r2, r3, #5
|
|
8002478: 69fb ldr r3, [r7, #28]
|
|
800247a: 4413 add r3, r2
|
|
800247c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002480: 461a mov r2, r3
|
|
8002482: 2301 movs r3, #1
|
|
8002484: 6093 str r3, [r2, #8]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8002486: 687b ldr r3, [r7, #4]
|
|
8002488: 799b ldrb r3, [r3, #6]
|
|
800248a: 2b01 cmp r3, #1
|
|
800248c: d132 bne.n 80024f4 <HAL_PCD_IRQHandler+0x3a2>
|
|
{
|
|
hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
|
|
800248e: 6879 ldr r1, [r7, #4]
|
|
8002490: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002492: 4613 mov r3, r2
|
|
8002494: 00db lsls r3, r3, #3
|
|
8002496: 4413 add r3, r2
|
|
8002498: 009b lsls r3, r3, #2
|
|
800249a: 440b add r3, r1
|
|
800249c: 3320 adds r3, #32
|
|
800249e: 6819 ldr r1, [r3, #0]
|
|
80024a0: 6878 ldr r0, [r7, #4]
|
|
80024a2: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80024a4: 4613 mov r3, r2
|
|
80024a6: 00db lsls r3, r3, #3
|
|
80024a8: 4413 add r3, r2
|
|
80024aa: 009b lsls r3, r3, #2
|
|
80024ac: 4403 add r3, r0
|
|
80024ae: 331c adds r3, #28
|
|
80024b0: 681b ldr r3, [r3, #0]
|
|
80024b2: 4419 add r1, r3
|
|
80024b4: 6878 ldr r0, [r7, #4]
|
|
80024b6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80024b8: 4613 mov r3, r2
|
|
80024ba: 00db lsls r3, r3, #3
|
|
80024bc: 4413 add r3, r2
|
|
80024be: 009b lsls r3, r3, #2
|
|
80024c0: 4403 add r3, r0
|
|
80024c2: 3320 adds r3, #32
|
|
80024c4: 6019 str r1, [r3, #0]
|
|
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
|
|
80024c6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80024c8: 2b00 cmp r3, #0
|
|
80024ca: d113 bne.n 80024f4 <HAL_PCD_IRQHandler+0x3a2>
|
|
80024cc: 6879 ldr r1, [r7, #4]
|
|
80024ce: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80024d0: 4613 mov r3, r2
|
|
80024d2: 00db lsls r3, r3, #3
|
|
80024d4: 4413 add r3, r2
|
|
80024d6: 009b lsls r3, r3, #2
|
|
80024d8: 440b add r3, r1
|
|
80024da: 3324 adds r3, #36 @ 0x24
|
|
80024dc: 681b ldr r3, [r3, #0]
|
|
80024de: 2b00 cmp r3, #0
|
|
80024e0: d108 bne.n 80024f4 <HAL_PCD_IRQHandler+0x3a2>
|
|
{
|
|
/* prepare to rx more setup packets */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
80024e2: 687b ldr r3, [r7, #4]
|
|
80024e4: 6818 ldr r0, [r3, #0]
|
|
80024e6: 687b ldr r3, [r7, #4]
|
|
80024e8: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
80024ec: 461a mov r2, r3
|
|
80024ee: 2101 movs r1, #1
|
|
80024f0: f004 fd76 bl 8006fe0 <USB_EP0_OutStart>
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
|
|
80024f4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80024f6: b2db uxtb r3, r3
|
|
80024f8: 4619 mov r1, r3
|
|
80024fa: 6878 ldr r0, [r7, #4]
|
|
80024fc: f006 fd7b bl 8008ff6 <HAL_PCD_DataInStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
|
|
8002500: 693b ldr r3, [r7, #16]
|
|
8002502: f003 0308 and.w r3, r3, #8
|
|
8002506: 2b00 cmp r3, #0
|
|
8002508: d008 beq.n 800251c <HAL_PCD_IRQHandler+0x3ca>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
|
|
800250a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800250c: 015a lsls r2, r3, #5
|
|
800250e: 69fb ldr r3, [r7, #28]
|
|
8002510: 4413 add r3, r2
|
|
8002512: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002516: 461a mov r2, r3
|
|
8002518: 2308 movs r3, #8
|
|
800251a: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
|
|
800251c: 693b ldr r3, [r7, #16]
|
|
800251e: f003 0310 and.w r3, r3, #16
|
|
8002522: 2b00 cmp r3, #0
|
|
8002524: d008 beq.n 8002538 <HAL_PCD_IRQHandler+0x3e6>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
|
|
8002526: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002528: 015a lsls r2, r3, #5
|
|
800252a: 69fb ldr r3, [r7, #28]
|
|
800252c: 4413 add r3, r2
|
|
800252e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002532: 461a mov r2, r3
|
|
8002534: 2310 movs r3, #16
|
|
8002536: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
|
|
8002538: 693b ldr r3, [r7, #16]
|
|
800253a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800253e: 2b00 cmp r3, #0
|
|
8002540: d008 beq.n 8002554 <HAL_PCD_IRQHandler+0x402>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
|
|
8002542: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002544: 015a lsls r2, r3, #5
|
|
8002546: 69fb ldr r3, [r7, #28]
|
|
8002548: 4413 add r3, r2
|
|
800254a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800254e: 461a mov r2, r3
|
|
8002550: 2340 movs r3, #64 @ 0x40
|
|
8002552: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
|
|
8002554: 693b ldr r3, [r7, #16]
|
|
8002556: f003 0302 and.w r3, r3, #2
|
|
800255a: 2b00 cmp r3, #0
|
|
800255c: d023 beq.n 80025a6 <HAL_PCD_IRQHandler+0x454>
|
|
{
|
|
(void)USB_FlushTxFifo(USBx, epnum);
|
|
800255e: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8002560: 6a38 ldr r0, [r7, #32]
|
|
8002562: f003 fd5d bl 8006020 <USB_FlushTxFifo>
|
|
|
|
ep = &hpcd->IN_ep[epnum];
|
|
8002566: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002568: 4613 mov r3, r2
|
|
800256a: 00db lsls r3, r3, #3
|
|
800256c: 4413 add r3, r2
|
|
800256e: 009b lsls r3, r3, #2
|
|
8002570: 3310 adds r3, #16
|
|
8002572: 687a ldr r2, [r7, #4]
|
|
8002574: 4413 add r3, r2
|
|
8002576: 3304 adds r3, #4
|
|
8002578: 617b str r3, [r7, #20]
|
|
|
|
if (ep->is_iso_incomplete == 1U)
|
|
800257a: 697b ldr r3, [r7, #20]
|
|
800257c: 78db ldrb r3, [r3, #3]
|
|
800257e: 2b01 cmp r3, #1
|
|
8002580: d108 bne.n 8002594 <HAL_PCD_IRQHandler+0x442>
|
|
{
|
|
ep->is_iso_incomplete = 0U;
|
|
8002582: 697b ldr r3, [r7, #20]
|
|
8002584: 2200 movs r2, #0
|
|
8002586: 70da strb r2, [r3, #3]
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
8002588: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800258a: b2db uxtb r3, r3
|
|
800258c: 4619 mov r1, r3
|
|
800258e: 6878 ldr r0, [r7, #4]
|
|
8002590: f006 fdc8 bl 8009124 <HAL_PCD_ISOINIncompleteCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
|
|
8002594: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002596: 015a lsls r2, r3, #5
|
|
8002598: 69fb ldr r3, [r7, #28]
|
|
800259a: 4413 add r3, r2
|
|
800259c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80025a0: 461a mov r2, r3
|
|
80025a2: 2302 movs r3, #2
|
|
80025a4: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
|
|
80025a6: 693b ldr r3, [r7, #16]
|
|
80025a8: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80025ac: 2b00 cmp r3, #0
|
|
80025ae: d003 beq.n 80025b8 <HAL_PCD_IRQHandler+0x466>
|
|
{
|
|
(void)PCD_WriteEmptyTxFifo(hpcd, epnum);
|
|
80025b0: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
80025b2: 6878 ldr r0, [r7, #4]
|
|
80025b4: f000 fcd2 bl 8002f5c <PCD_WriteEmptyTxFifo>
|
|
}
|
|
}
|
|
epnum++;
|
|
80025b8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80025ba: 3301 adds r3, #1
|
|
80025bc: 627b str r3, [r7, #36] @ 0x24
|
|
ep_intr >>= 1U;
|
|
80025be: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80025c0: 085b lsrs r3, r3, #1
|
|
80025c2: 62bb str r3, [r7, #40] @ 0x28
|
|
while (ep_intr != 0U)
|
|
80025c4: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80025c6: 2b00 cmp r3, #0
|
|
80025c8: f47f af2e bne.w 8002428 <HAL_PCD_IRQHandler+0x2d6>
|
|
}
|
|
}
|
|
|
|
/* Handle Resume Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
|
|
80025cc: 687b ldr r3, [r7, #4]
|
|
80025ce: 681b ldr r3, [r3, #0]
|
|
80025d0: 4618 mov r0, r3
|
|
80025d2: f004 fc41 bl 8006e58 <USB_ReadInterrupts>
|
|
80025d6: 4603 mov r3, r0
|
|
80025d8: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80025dc: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80025e0: d122 bne.n 8002628 <HAL_PCD_IRQHandler+0x4d6>
|
|
{
|
|
/* Clear the Remote Wake-up Signaling */
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
|
|
80025e2: 69fb ldr r3, [r7, #28]
|
|
80025e4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80025e8: 685b ldr r3, [r3, #4]
|
|
80025ea: 69fa ldr r2, [r7, #28]
|
|
80025ec: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80025f0: f023 0301 bic.w r3, r3, #1
|
|
80025f4: 6053 str r3, [r2, #4]
|
|
|
|
if (hpcd->LPM_State == LPM_L1)
|
|
80025f6: 687b ldr r3, [r7, #4]
|
|
80025f8: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
|
|
80025fc: 2b01 cmp r3, #1
|
|
80025fe: d108 bne.n 8002612 <HAL_PCD_IRQHandler+0x4c0>
|
|
{
|
|
hpcd->LPM_State = LPM_L0;
|
|
8002600: 687b ldr r3, [r7, #4]
|
|
8002602: 2200 movs r2, #0
|
|
8002604: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
|
|
#else
|
|
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
|
|
8002608: 2100 movs r1, #0
|
|
800260a: 6878 ldr r0, [r7, #4]
|
|
800260c: f006 ff30 bl 8009470 <HAL_PCDEx_LPM_Callback>
|
|
8002610: e002 b.n 8002618 <HAL_PCD_IRQHandler+0x4c6>
|
|
else
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResumeCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResumeCallback(hpcd);
|
|
8002612: 6878 ldr r0, [r7, #4]
|
|
8002614: f006 fd66 bl 80090e4 <HAL_PCD_ResumeCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
|
|
8002618: 687b ldr r3, [r7, #4]
|
|
800261a: 681b ldr r3, [r3, #0]
|
|
800261c: 695a ldr r2, [r3, #20]
|
|
800261e: 687b ldr r3, [r7, #4]
|
|
8002620: 681b ldr r3, [r3, #0]
|
|
8002622: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000
|
|
8002626: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Suspend Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
|
|
8002628: 687b ldr r3, [r7, #4]
|
|
800262a: 681b ldr r3, [r3, #0]
|
|
800262c: 4618 mov r0, r3
|
|
800262e: f004 fc13 bl 8006e58 <USB_ReadInterrupts>
|
|
8002632: 4603 mov r3, r0
|
|
8002634: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8002638: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
800263c: d112 bne.n 8002664 <HAL_PCD_IRQHandler+0x512>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
|
|
800263e: 69fb ldr r3, [r7, #28]
|
|
8002640: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002644: 689b ldr r3, [r3, #8]
|
|
8002646: f003 0301 and.w r3, r3, #1
|
|
800264a: 2b01 cmp r3, #1
|
|
800264c: d102 bne.n 8002654 <HAL_PCD_IRQHandler+0x502>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SuspendCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
800264e: 6878 ldr r0, [r7, #4]
|
|
8002650: f006 fd22 bl 8009098 <HAL_PCD_SuspendCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
|
|
8002654: 687b ldr r3, [r7, #4]
|
|
8002656: 681b ldr r3, [r3, #0]
|
|
8002658: 695a ldr r2, [r3, #20]
|
|
800265a: 687b ldr r3, [r7, #4]
|
|
800265c: 681b ldr r3, [r3, #0]
|
|
800265e: f402 6200 and.w r2, r2, #2048 @ 0x800
|
|
8002662: 615a str r2, [r3, #20]
|
|
}
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* Handle LPM Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
|
|
8002664: 687b ldr r3, [r7, #4]
|
|
8002666: 681b ldr r3, [r3, #0]
|
|
8002668: 4618 mov r0, r3
|
|
800266a: f004 fbf5 bl 8006e58 <USB_ReadInterrupts>
|
|
800266e: 4603 mov r3, r0
|
|
8002670: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8002674: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8002678: d121 bne.n 80026be <HAL_PCD_IRQHandler+0x56c>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
|
|
800267a: 687b ldr r3, [r7, #4]
|
|
800267c: 681b ldr r3, [r3, #0]
|
|
800267e: 695a ldr r2, [r3, #20]
|
|
8002680: 687b ldr r3, [r7, #4]
|
|
8002682: 681b ldr r3, [r3, #0]
|
|
8002684: f002 6200 and.w r2, r2, #134217728 @ 0x8000000
|
|
8002688: 615a str r2, [r3, #20]
|
|
|
|
if (hpcd->LPM_State == LPM_L0)
|
|
800268a: 687b ldr r3, [r7, #4]
|
|
800268c: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
|
|
8002690: 2b00 cmp r3, #0
|
|
8002692: d111 bne.n 80026b8 <HAL_PCD_IRQHandler+0x566>
|
|
{
|
|
hpcd->LPM_State = LPM_L1;
|
|
8002694: 687b ldr r3, [r7, #4]
|
|
8002696: 2201 movs r2, #1
|
|
8002698: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
|
|
800269c: 687b ldr r3, [r7, #4]
|
|
800269e: 681b ldr r3, [r3, #0]
|
|
80026a0: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80026a2: 089b lsrs r3, r3, #2
|
|
80026a4: f003 020f and.w r2, r3, #15
|
|
80026a8: 687b ldr r3, [r7, #4]
|
|
80026aa: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
|
|
#else
|
|
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
|
|
80026ae: 2101 movs r1, #1
|
|
80026b0: 6878 ldr r0, [r7, #4]
|
|
80026b2: f006 fedd bl 8009470 <HAL_PCDEx_LPM_Callback>
|
|
80026b6: e002 b.n 80026be <HAL_PCD_IRQHandler+0x56c>
|
|
else
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SuspendCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
80026b8: 6878 ldr r0, [r7, #4]
|
|
80026ba: f006 fced bl 8009098 <HAL_PCD_SuspendCallback>
|
|
}
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
/* Handle Reset Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
|
|
80026be: 687b ldr r3, [r7, #4]
|
|
80026c0: 681b ldr r3, [r3, #0]
|
|
80026c2: 4618 mov r0, r3
|
|
80026c4: f004 fbc8 bl 8006e58 <USB_ReadInterrupts>
|
|
80026c8: 4603 mov r3, r0
|
|
80026ca: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
80026ce: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
80026d2: f040 80b7 bne.w 8002844 <HAL_PCD_IRQHandler+0x6f2>
|
|
{
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
|
|
80026d6: 69fb ldr r3, [r7, #28]
|
|
80026d8: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80026dc: 685b ldr r3, [r3, #4]
|
|
80026de: 69fa ldr r2, [r7, #28]
|
|
80026e0: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80026e4: f023 0301 bic.w r3, r3, #1
|
|
80026e8: 6053 str r3, [r2, #4]
|
|
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
|
|
80026ea: 687b ldr r3, [r7, #4]
|
|
80026ec: 681b ldr r3, [r3, #0]
|
|
80026ee: 2110 movs r1, #16
|
|
80026f0: 4618 mov r0, r3
|
|
80026f2: f003 fc95 bl 8006020 <USB_FlushTxFifo>
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
80026f6: 2300 movs r3, #0
|
|
80026f8: 62fb str r3, [r7, #44] @ 0x2c
|
|
80026fa: e046 b.n 800278a <HAL_PCD_IRQHandler+0x638>
|
|
{
|
|
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
|
80026fc: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80026fe: 015a lsls r2, r3, #5
|
|
8002700: 69fb ldr r3, [r7, #28]
|
|
8002702: 4413 add r3, r2
|
|
8002704: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002708: 461a mov r2, r3
|
|
800270a: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
800270e: 6093 str r3, [r2, #8]
|
|
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
|
8002710: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002712: 015a lsls r2, r3, #5
|
|
8002714: 69fb ldr r3, [r7, #28]
|
|
8002716: 4413 add r3, r2
|
|
8002718: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800271c: 681b ldr r3, [r3, #0]
|
|
800271e: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8002720: 0151 lsls r1, r2, #5
|
|
8002722: 69fa ldr r2, [r7, #28]
|
|
8002724: 440a add r2, r1
|
|
8002726: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800272a: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
800272e: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
|
8002730: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002732: 015a lsls r2, r3, #5
|
|
8002734: 69fb ldr r3, [r7, #28]
|
|
8002736: 4413 add r3, r2
|
|
8002738: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800273c: 461a mov r2, r3
|
|
800273e: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
8002742: 6093 str r3, [r2, #8]
|
|
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
|
8002744: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002746: 015a lsls r2, r3, #5
|
|
8002748: 69fb ldr r3, [r7, #28]
|
|
800274a: 4413 add r3, r2
|
|
800274c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002750: 681b ldr r3, [r3, #0]
|
|
8002752: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8002754: 0151 lsls r1, r2, #5
|
|
8002756: 69fa ldr r2, [r7, #28]
|
|
8002758: 440a add r2, r1
|
|
800275a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800275e: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
8002762: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
|
8002764: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002766: 015a lsls r2, r3, #5
|
|
8002768: 69fb ldr r3, [r7, #28]
|
|
800276a: 4413 add r3, r2
|
|
800276c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002770: 681b ldr r3, [r3, #0]
|
|
8002772: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8002774: 0151 lsls r1, r2, #5
|
|
8002776: 69fa ldr r2, [r7, #28]
|
|
8002778: 440a add r2, r1
|
|
800277a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800277e: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8002782: 6013 str r3, [r2, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8002784: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002786: 3301 adds r3, #1
|
|
8002788: 62fb str r3, [r7, #44] @ 0x2c
|
|
800278a: 687b ldr r3, [r7, #4]
|
|
800278c: 791b ldrb r3, [r3, #4]
|
|
800278e: 461a mov r2, r3
|
|
8002790: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002792: 4293 cmp r3, r2
|
|
8002794: d3b2 bcc.n 80026fc <HAL_PCD_IRQHandler+0x5aa>
|
|
}
|
|
USBx_DEVICE->DAINTMSK |= 0x10001U;
|
|
8002796: 69fb ldr r3, [r7, #28]
|
|
8002798: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800279c: 69db ldr r3, [r3, #28]
|
|
800279e: 69fa ldr r2, [r7, #28]
|
|
80027a0: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80027a4: f043 1301 orr.w r3, r3, #65537 @ 0x10001
|
|
80027a8: 61d3 str r3, [r2, #28]
|
|
|
|
if (hpcd->Init.use_dedicated_ep1 != 0U)
|
|
80027aa: 687b ldr r3, [r7, #4]
|
|
80027ac: 7bdb ldrb r3, [r3, #15]
|
|
80027ae: 2b00 cmp r3, #0
|
|
80027b0: d016 beq.n 80027e0 <HAL_PCD_IRQHandler+0x68e>
|
|
{
|
|
USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
|
|
80027b2: 69fb ldr r3, [r7, #28]
|
|
80027b4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80027b8: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80027bc: 69fa ldr r2, [r7, #28]
|
|
80027be: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80027c2: f043 030b orr.w r3, r3, #11
|
|
80027c6: f8c2 3084 str.w r3, [r2, #132] @ 0x84
|
|
USB_OTG_DOEPMSK_XFRCM |
|
|
USB_OTG_DOEPMSK_EPDM;
|
|
|
|
USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
|
|
80027ca: 69fb ldr r3, [r7, #28]
|
|
80027cc: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80027d0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80027d2: 69fa ldr r2, [r7, #28]
|
|
80027d4: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80027d8: f043 030b orr.w r3, r3, #11
|
|
80027dc: 6453 str r3, [r2, #68] @ 0x44
|
|
80027de: e015 b.n 800280c <HAL_PCD_IRQHandler+0x6ba>
|
|
USB_OTG_DIEPMSK_XFRCM |
|
|
USB_OTG_DIEPMSK_EPDM;
|
|
}
|
|
else
|
|
{
|
|
USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
|
|
80027e0: 69fb ldr r3, [r7, #28]
|
|
80027e2: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80027e6: 695b ldr r3, [r3, #20]
|
|
80027e8: 69fa ldr r2, [r7, #28]
|
|
80027ea: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80027ee: f443 5300 orr.w r3, r3, #8192 @ 0x2000
|
|
80027f2: f043 032b orr.w r3, r3, #43 @ 0x2b
|
|
80027f6: 6153 str r3, [r2, #20]
|
|
USB_OTG_DOEPMSK_XFRCM |
|
|
USB_OTG_DOEPMSK_EPDM |
|
|
USB_OTG_DOEPMSK_OTEPSPRM |
|
|
USB_OTG_DOEPMSK_NAKM;
|
|
|
|
USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
|
|
80027f8: 69fb ldr r3, [r7, #28]
|
|
80027fa: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80027fe: 691b ldr r3, [r3, #16]
|
|
8002800: 69fa ldr r2, [r7, #28]
|
|
8002802: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8002806: f043 030b orr.w r3, r3, #11
|
|
800280a: 6113 str r3, [r2, #16]
|
|
USB_OTG_DIEPMSK_XFRCM |
|
|
USB_OTG_DIEPMSK_EPDM;
|
|
}
|
|
|
|
/* Set Default Address to 0 */
|
|
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
|
|
800280c: 69fb ldr r3, [r7, #28]
|
|
800280e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002812: 681b ldr r3, [r3, #0]
|
|
8002814: 69fa ldr r2, [r7, #28]
|
|
8002816: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
800281a: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
|
|
800281e: 6013 str r3, [r2, #0]
|
|
|
|
/* setup EP0 to receive SETUP packets */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
|
|
8002820: 687b ldr r3, [r7, #4]
|
|
8002822: 6818 ldr r0, [r3, #0]
|
|
8002824: 687b ldr r3, [r7, #4]
|
|
8002826: 7999 ldrb r1, [r3, #6]
|
|
(uint8_t *)hpcd->Setup);
|
|
8002828: 687b ldr r3, [r7, #4]
|
|
800282a: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
|
|
800282e: 461a mov r2, r3
|
|
8002830: f004 fbd6 bl 8006fe0 <USB_EP0_OutStart>
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
|
|
8002834: 687b ldr r3, [r7, #4]
|
|
8002836: 681b ldr r3, [r3, #0]
|
|
8002838: 695a ldr r2, [r3, #20]
|
|
800283a: 687b ldr r3, [r7, #4]
|
|
800283c: 681b ldr r3, [r3, #0]
|
|
800283e: f402 5280 and.w r2, r2, #4096 @ 0x1000
|
|
8002842: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Enumeration done Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
|
|
8002844: 687b ldr r3, [r7, #4]
|
|
8002846: 681b ldr r3, [r3, #0]
|
|
8002848: 4618 mov r0, r3
|
|
800284a: f004 fb05 bl 8006e58 <USB_ReadInterrupts>
|
|
800284e: 4603 mov r3, r0
|
|
8002850: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
8002854: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
8002858: d123 bne.n 80028a2 <HAL_PCD_IRQHandler+0x750>
|
|
{
|
|
(void)USB_ActivateSetup(hpcd->Instance);
|
|
800285a: 687b ldr r3, [r7, #4]
|
|
800285c: 681b ldr r3, [r3, #0]
|
|
800285e: 4618 mov r0, r3
|
|
8002860: f004 fb9b bl 8006f9a <USB_ActivateSetup>
|
|
hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
|
|
8002864: 687b ldr r3, [r7, #4]
|
|
8002866: 681b ldr r3, [r3, #0]
|
|
8002868: 4618 mov r0, r3
|
|
800286a: f003 fc52 bl 8006112 <USB_GetDevSpeed>
|
|
800286e: 4603 mov r3, r0
|
|
8002870: 461a mov r2, r3
|
|
8002872: 687b ldr r3, [r7, #4]
|
|
8002874: 71da strb r2, [r3, #7]
|
|
|
|
/* Set USB Turnaround time */
|
|
(void)USB_SetTurnaroundTime(hpcd->Instance,
|
|
8002876: 687b ldr r3, [r7, #4]
|
|
8002878: 681c ldr r4, [r3, #0]
|
|
800287a: f000 fe8b bl 8003594 <HAL_RCC_GetHCLKFreq>
|
|
800287e: 4601 mov r1, r0
|
|
HAL_RCC_GetHCLKFreq(),
|
|
(uint8_t)hpcd->Init.speed);
|
|
8002880: 687b ldr r3, [r7, #4]
|
|
8002882: 79db ldrb r3, [r3, #7]
|
|
(void)USB_SetTurnaroundTime(hpcd->Instance,
|
|
8002884: 461a mov r2, r3
|
|
8002886: 4620 mov r0, r4
|
|
8002888: f003 f95c bl 8005b44 <USB_SetTurnaroundTime>
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResetCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResetCallback(hpcd);
|
|
800288c: 6878 ldr r0, [r7, #4]
|
|
800288e: f006 fbda bl 8009046 <HAL_PCD_ResetCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
|
|
8002892: 687b ldr r3, [r7, #4]
|
|
8002894: 681b ldr r3, [r3, #0]
|
|
8002896: 695a ldr r2, [r3, #20]
|
|
8002898: 687b ldr r3, [r7, #4]
|
|
800289a: 681b ldr r3, [r3, #0]
|
|
800289c: f402 5200 and.w r2, r2, #8192 @ 0x2000
|
|
80028a0: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle SOF Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
|
|
80028a2: 687b ldr r3, [r7, #4]
|
|
80028a4: 681b ldr r3, [r3, #0]
|
|
80028a6: 4618 mov r0, r3
|
|
80028a8: f004 fad6 bl 8006e58 <USB_ReadInterrupts>
|
|
80028ac: 4603 mov r3, r0
|
|
80028ae: f003 0308 and.w r3, r3, #8
|
|
80028b2: 2b08 cmp r3, #8
|
|
80028b4: d10a bne.n 80028cc <HAL_PCD_IRQHandler+0x77a>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SOFCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SOFCallback(hpcd);
|
|
80028b6: 6878 ldr r0, [r7, #4]
|
|
80028b8: f006 fbb7 bl 800902a <HAL_PCD_SOFCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
|
|
80028bc: 687b ldr r3, [r7, #4]
|
|
80028be: 681b ldr r3, [r3, #0]
|
|
80028c0: 695a ldr r2, [r3, #20]
|
|
80028c2: 687b ldr r3, [r7, #4]
|
|
80028c4: 681b ldr r3, [r3, #0]
|
|
80028c6: f002 0208 and.w r2, r2, #8
|
|
80028ca: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Global OUT NAK effective Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF))
|
|
80028cc: 687b ldr r3, [r7, #4]
|
|
80028ce: 681b ldr r3, [r3, #0]
|
|
80028d0: 4618 mov r0, r3
|
|
80028d2: f004 fac1 bl 8006e58 <USB_ReadInterrupts>
|
|
80028d6: 4603 mov r3, r0
|
|
80028d8: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80028dc: 2b80 cmp r3, #128 @ 0x80
|
|
80028de: d123 bne.n 8002928 <HAL_PCD_IRQHandler+0x7d6>
|
|
{
|
|
USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM;
|
|
80028e0: 6a3b ldr r3, [r7, #32]
|
|
80028e2: 699b ldr r3, [r3, #24]
|
|
80028e4: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
80028e8: 6a3b ldr r3, [r7, #32]
|
|
80028ea: 619a str r2, [r3, #24]
|
|
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
80028ec: 2301 movs r3, #1
|
|
80028ee: 627b str r3, [r7, #36] @ 0x24
|
|
80028f0: e014 b.n 800291c <HAL_PCD_IRQHandler+0x7ca>
|
|
{
|
|
if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U)
|
|
80028f2: 6879 ldr r1, [r7, #4]
|
|
80028f4: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80028f6: 4613 mov r3, r2
|
|
80028f8: 00db lsls r3, r3, #3
|
|
80028fa: 4413 add r3, r2
|
|
80028fc: 009b lsls r3, r3, #2
|
|
80028fe: 440b add r3, r1
|
|
8002900: f203 2357 addw r3, r3, #599 @ 0x257
|
|
8002904: 781b ldrb r3, [r3, #0]
|
|
8002906: 2b01 cmp r3, #1
|
|
8002908: d105 bne.n 8002916 <HAL_PCD_IRQHandler+0x7c4>
|
|
{
|
|
/* Abort current transaction and disable the EP */
|
|
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum);
|
|
800290a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800290c: b2db uxtb r3, r3
|
|
800290e: 4619 mov r1, r3
|
|
8002910: 6878 ldr r0, [r7, #4]
|
|
8002912: f000 faf2 bl 8002efa <HAL_PCD_EP_Abort>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
8002916: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002918: 3301 adds r3, #1
|
|
800291a: 627b str r3, [r7, #36] @ 0x24
|
|
800291c: 687b ldr r3, [r7, #4]
|
|
800291e: 791b ldrb r3, [r3, #4]
|
|
8002920: 461a mov r2, r3
|
|
8002922: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002924: 4293 cmp r3, r2
|
|
8002926: d3e4 bcc.n 80028f2 <HAL_PCD_IRQHandler+0x7a0>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Handle Incomplete ISO IN Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
|
|
8002928: 687b ldr r3, [r7, #4]
|
|
800292a: 681b ldr r3, [r3, #0]
|
|
800292c: 4618 mov r0, r3
|
|
800292e: f004 fa93 bl 8006e58 <USB_ReadInterrupts>
|
|
8002932: 4603 mov r3, r0
|
|
8002934: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8002938: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
800293c: d13c bne.n 80029b8 <HAL_PCD_IRQHandler+0x866>
|
|
{
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
800293e: 2301 movs r3, #1
|
|
8002940: 627b str r3, [r7, #36] @ 0x24
|
|
8002942: e02b b.n 800299c <HAL_PCD_IRQHandler+0x84a>
|
|
{
|
|
RegVal = USBx_INEP(epnum)->DIEPCTL;
|
|
8002944: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002946: 015a lsls r2, r3, #5
|
|
8002948: 69fb ldr r3, [r7, #28]
|
|
800294a: 4413 add r3, r2
|
|
800294c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002950: 681b ldr r3, [r3, #0]
|
|
8002952: 61bb str r3, [r7, #24]
|
|
|
|
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
8002954: 6879 ldr r1, [r7, #4]
|
|
8002956: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002958: 4613 mov r3, r2
|
|
800295a: 00db lsls r3, r3, #3
|
|
800295c: 4413 add r3, r2
|
|
800295e: 009b lsls r3, r3, #2
|
|
8002960: 440b add r3, r1
|
|
8002962: 3318 adds r3, #24
|
|
8002964: 781b ldrb r3, [r3, #0]
|
|
8002966: 2b01 cmp r3, #1
|
|
8002968: d115 bne.n 8002996 <HAL_PCD_IRQHandler+0x844>
|
|
((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA))
|
|
800296a: 69bb ldr r3, [r7, #24]
|
|
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
800296c: 2b00 cmp r3, #0
|
|
800296e: da12 bge.n 8002996 <HAL_PCD_IRQHandler+0x844>
|
|
{
|
|
hpcd->IN_ep[epnum].is_iso_incomplete = 1U;
|
|
8002970: 6879 ldr r1, [r7, #4]
|
|
8002972: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002974: 4613 mov r3, r2
|
|
8002976: 00db lsls r3, r3, #3
|
|
8002978: 4413 add r3, r2
|
|
800297a: 009b lsls r3, r3, #2
|
|
800297c: 440b add r3, r1
|
|
800297e: 3317 adds r3, #23
|
|
8002980: 2201 movs r2, #1
|
|
8002982: 701a strb r2, [r3, #0]
|
|
|
|
/* Abort current transaction and disable the EP */
|
|
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U));
|
|
8002984: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002986: b2db uxtb r3, r3
|
|
8002988: f063 037f orn r3, r3, #127 @ 0x7f
|
|
800298c: b2db uxtb r3, r3
|
|
800298e: 4619 mov r1, r3
|
|
8002990: 6878 ldr r0, [r7, #4]
|
|
8002992: f000 fab2 bl 8002efa <HAL_PCD_EP_Abort>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
8002996: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002998: 3301 adds r3, #1
|
|
800299a: 627b str r3, [r7, #36] @ 0x24
|
|
800299c: 687b ldr r3, [r7, #4]
|
|
800299e: 791b ldrb r3, [r3, #4]
|
|
80029a0: 461a mov r2, r3
|
|
80029a2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80029a4: 4293 cmp r3, r2
|
|
80029a6: d3cd bcc.n 8002944 <HAL_PCD_IRQHandler+0x7f2>
|
|
}
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
|
|
80029a8: 687b ldr r3, [r7, #4]
|
|
80029aa: 681b ldr r3, [r3, #0]
|
|
80029ac: 695a ldr r2, [r3, #20]
|
|
80029ae: 687b ldr r3, [r7, #4]
|
|
80029b0: 681b ldr r3, [r3, #0]
|
|
80029b2: f402 1280 and.w r2, r2, #1048576 @ 0x100000
|
|
80029b6: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Incomplete ISO OUT Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
|
|
80029b8: 687b ldr r3, [r7, #4]
|
|
80029ba: 681b ldr r3, [r3, #0]
|
|
80029bc: 4618 mov r0, r3
|
|
80029be: f004 fa4b bl 8006e58 <USB_ReadInterrupts>
|
|
80029c2: 4603 mov r3, r0
|
|
80029c4: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
80029c8: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
|
|
80029cc: d156 bne.n 8002a7c <HAL_PCD_IRQHandler+0x92a>
|
|
{
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
80029ce: 2301 movs r3, #1
|
|
80029d0: 627b str r3, [r7, #36] @ 0x24
|
|
80029d2: e045 b.n 8002a60 <HAL_PCD_IRQHandler+0x90e>
|
|
{
|
|
RegVal = USBx_OUTEP(epnum)->DOEPCTL;
|
|
80029d4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80029d6: 015a lsls r2, r3, #5
|
|
80029d8: 69fb ldr r3, [r7, #28]
|
|
80029da: 4413 add r3, r2
|
|
80029dc: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80029e0: 681b ldr r3, [r3, #0]
|
|
80029e2: 61bb str r3, [r7, #24]
|
|
|
|
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
80029e4: 6879 ldr r1, [r7, #4]
|
|
80029e6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80029e8: 4613 mov r3, r2
|
|
80029ea: 00db lsls r3, r3, #3
|
|
80029ec: 4413 add r3, r2
|
|
80029ee: 009b lsls r3, r3, #2
|
|
80029f0: 440b add r3, r1
|
|
80029f2: f503 7316 add.w r3, r3, #600 @ 0x258
|
|
80029f6: 781b ldrb r3, [r3, #0]
|
|
80029f8: 2b01 cmp r3, #1
|
|
80029fa: d12e bne.n 8002a5a <HAL_PCD_IRQHandler+0x908>
|
|
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
|
|
80029fc: 69bb ldr r3, [r7, #24]
|
|
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
80029fe: 2b00 cmp r3, #0
|
|
8002a00: da2b bge.n 8002a5a <HAL_PCD_IRQHandler+0x908>
|
|
(((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U)))
|
|
8002a02: 69bb ldr r3, [r7, #24]
|
|
8002a04: 0c1a lsrs r2, r3, #16
|
|
8002a06: 687b ldr r3, [r7, #4]
|
|
8002a08: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4
|
|
8002a0c: 4053 eors r3, r2
|
|
8002a0e: f003 0301 and.w r3, r3, #1
|
|
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
|
|
8002a12: 2b00 cmp r3, #0
|
|
8002a14: d121 bne.n 8002a5a <HAL_PCD_IRQHandler+0x908>
|
|
{
|
|
hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
|
|
8002a16: 6879 ldr r1, [r7, #4]
|
|
8002a18: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002a1a: 4613 mov r3, r2
|
|
8002a1c: 00db lsls r3, r3, #3
|
|
8002a1e: 4413 add r3, r2
|
|
8002a20: 009b lsls r3, r3, #2
|
|
8002a22: 440b add r3, r1
|
|
8002a24: f203 2357 addw r3, r3, #599 @ 0x257
|
|
8002a28: 2201 movs r2, #1
|
|
8002a2a: 701a strb r2, [r3, #0]
|
|
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM;
|
|
8002a2c: 6a3b ldr r3, [r7, #32]
|
|
8002a2e: 699b ldr r3, [r3, #24]
|
|
8002a30: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
8002a34: 6a3b ldr r3, [r7, #32]
|
|
8002a36: 619a str r2, [r3, #24]
|
|
|
|
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U)
|
|
8002a38: 6a3b ldr r3, [r7, #32]
|
|
8002a3a: 695b ldr r3, [r3, #20]
|
|
8002a3c: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002a40: 2b00 cmp r3, #0
|
|
8002a42: d10a bne.n 8002a5a <HAL_PCD_IRQHandler+0x908>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
|
|
8002a44: 69fb ldr r3, [r7, #28]
|
|
8002a46: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002a4a: 685b ldr r3, [r3, #4]
|
|
8002a4c: 69fa ldr r2, [r7, #28]
|
|
8002a4e: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8002a52: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8002a56: 6053 str r3, [r2, #4]
|
|
break;
|
|
8002a58: e008 b.n 8002a6c <HAL_PCD_IRQHandler+0x91a>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
8002a5a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002a5c: 3301 adds r3, #1
|
|
8002a5e: 627b str r3, [r7, #36] @ 0x24
|
|
8002a60: 687b ldr r3, [r7, #4]
|
|
8002a62: 791b ldrb r3, [r3, #4]
|
|
8002a64: 461a mov r2, r3
|
|
8002a66: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002a68: 4293 cmp r3, r2
|
|
8002a6a: d3b3 bcc.n 80029d4 <HAL_PCD_IRQHandler+0x882>
|
|
}
|
|
}
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
|
|
8002a6c: 687b ldr r3, [r7, #4]
|
|
8002a6e: 681b ldr r3, [r3, #0]
|
|
8002a70: 695a ldr r2, [r3, #20]
|
|
8002a72: 687b ldr r3, [r7, #4]
|
|
8002a74: 681b ldr r3, [r3, #0]
|
|
8002a76: f402 1200 and.w r2, r2, #2097152 @ 0x200000
|
|
8002a7a: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Connection event Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
|
|
8002a7c: 687b ldr r3, [r7, #4]
|
|
8002a7e: 681b ldr r3, [r3, #0]
|
|
8002a80: 4618 mov r0, r3
|
|
8002a82: f004 f9e9 bl 8006e58 <USB_ReadInterrupts>
|
|
8002a86: 4603 mov r3, r0
|
|
8002a88: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
|
|
8002a8c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8002a90: d10a bne.n 8002aa8 <HAL_PCD_IRQHandler+0x956>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ConnectCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ConnectCallback(hpcd);
|
|
8002a92: 6878 ldr r0, [r7, #4]
|
|
8002a94: f006 fb58 bl 8009148 <HAL_PCD_ConnectCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
|
|
8002a98: 687b ldr r3, [r7, #4]
|
|
8002a9a: 681b ldr r3, [r3, #0]
|
|
8002a9c: 695a ldr r2, [r3, #20]
|
|
8002a9e: 687b ldr r3, [r7, #4]
|
|
8002aa0: 681b ldr r3, [r3, #0]
|
|
8002aa2: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000
|
|
8002aa6: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Disconnection event Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
|
|
8002aa8: 687b ldr r3, [r7, #4]
|
|
8002aaa: 681b ldr r3, [r3, #0]
|
|
8002aac: 4618 mov r0, r3
|
|
8002aae: f004 f9d3 bl 8006e58 <USB_ReadInterrupts>
|
|
8002ab2: 4603 mov r3, r0
|
|
8002ab4: f003 0304 and.w r3, r3, #4
|
|
8002ab8: 2b04 cmp r3, #4
|
|
8002aba: d115 bne.n 8002ae8 <HAL_PCD_IRQHandler+0x996>
|
|
{
|
|
RegVal = hpcd->Instance->GOTGINT;
|
|
8002abc: 687b ldr r3, [r7, #4]
|
|
8002abe: 681b ldr r3, [r3, #0]
|
|
8002ac0: 685b ldr r3, [r3, #4]
|
|
8002ac2: 61bb str r3, [r7, #24]
|
|
|
|
if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
|
|
8002ac4: 69bb ldr r3, [r7, #24]
|
|
8002ac6: f003 0304 and.w r3, r3, #4
|
|
8002aca: 2b00 cmp r3, #0
|
|
8002acc: d002 beq.n 8002ad4 <HAL_PCD_IRQHandler+0x982>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DisconnectCallback(hpcd);
|
|
#else
|
|
HAL_PCD_DisconnectCallback(hpcd);
|
|
8002ace: 6878 ldr r0, [r7, #4]
|
|
8002ad0: f006 fb48 bl 8009164 <HAL_PCD_DisconnectCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
hpcd->Instance->GOTGINT |= RegVal;
|
|
8002ad4: 687b ldr r3, [r7, #4]
|
|
8002ad6: 681b ldr r3, [r3, #0]
|
|
8002ad8: 6859 ldr r1, [r3, #4]
|
|
8002ada: 687b ldr r3, [r7, #4]
|
|
8002adc: 681b ldr r3, [r3, #0]
|
|
8002ade: 69ba ldr r2, [r7, #24]
|
|
8002ae0: 430a orrs r2, r1
|
|
8002ae2: 605a str r2, [r3, #4]
|
|
8002ae4: e000 b.n 8002ae8 <HAL_PCD_IRQHandler+0x996>
|
|
return;
|
|
8002ae6: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
8002ae8: 3734 adds r7, #52 @ 0x34
|
|
8002aea: 46bd mov sp, r7
|
|
8002aec: bd90 pop {r4, r7, pc}
|
|
|
|
08002aee <HAL_PCD_SetAddress>:
|
|
* @param hpcd PCD handle
|
|
* @param address new device address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
|
|
{
|
|
8002aee: b580 push {r7, lr}
|
|
8002af0: b082 sub sp, #8
|
|
8002af2: af00 add r7, sp, #0
|
|
8002af4: 6078 str r0, [r7, #4]
|
|
8002af6: 460b mov r3, r1
|
|
8002af8: 70fb strb r3, [r7, #3]
|
|
__HAL_LOCK(hpcd);
|
|
8002afa: 687b ldr r3, [r7, #4]
|
|
8002afc: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002b00: 2b01 cmp r3, #1
|
|
8002b02: d101 bne.n 8002b08 <HAL_PCD_SetAddress+0x1a>
|
|
8002b04: 2302 movs r3, #2
|
|
8002b06: e012 b.n 8002b2e <HAL_PCD_SetAddress+0x40>
|
|
8002b08: 687b ldr r3, [r7, #4]
|
|
8002b0a: 2201 movs r2, #1
|
|
8002b0c: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
hpcd->USB_Address = address;
|
|
8002b10: 687b ldr r3, [r7, #4]
|
|
8002b12: 78fa ldrb r2, [r7, #3]
|
|
8002b14: 745a strb r2, [r3, #17]
|
|
(void)USB_SetDevAddress(hpcd->Instance, address);
|
|
8002b16: 687b ldr r3, [r7, #4]
|
|
8002b18: 681b ldr r3, [r3, #0]
|
|
8002b1a: 78fa ldrb r2, [r7, #3]
|
|
8002b1c: 4611 mov r1, r2
|
|
8002b1e: 4618 mov r0, r3
|
|
8002b20: f004 f932 bl 8006d88 <USB_SetDevAddress>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002b24: 687b ldr r3, [r7, #4]
|
|
8002b26: 2200 movs r2, #0
|
|
8002b28: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8002b2c: 2300 movs r3, #0
|
|
}
|
|
8002b2e: 4618 mov r0, r3
|
|
8002b30: 3708 adds r7, #8
|
|
8002b32: 46bd mov sp, r7
|
|
8002b34: bd80 pop {r7, pc}
|
|
|
|
08002b36 <HAL_PCD_EP_Open>:
|
|
* @param ep_type endpoint type
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
|
uint16_t ep_mps, uint8_t ep_type)
|
|
{
|
|
8002b36: b580 push {r7, lr}
|
|
8002b38: b084 sub sp, #16
|
|
8002b3a: af00 add r7, sp, #0
|
|
8002b3c: 6078 str r0, [r7, #4]
|
|
8002b3e: 4608 mov r0, r1
|
|
8002b40: 4611 mov r1, r2
|
|
8002b42: 461a mov r2, r3
|
|
8002b44: 4603 mov r3, r0
|
|
8002b46: 70fb strb r3, [r7, #3]
|
|
8002b48: 460b mov r3, r1
|
|
8002b4a: 803b strh r3, [r7, #0]
|
|
8002b4c: 4613 mov r3, r2
|
|
8002b4e: 70bb strb r3, [r7, #2]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8002b50: 2300 movs r3, #0
|
|
8002b52: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8002b54: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002b58: 2b00 cmp r3, #0
|
|
8002b5a: da0f bge.n 8002b7c <HAL_PCD_EP_Open+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002b5c: 78fb ldrb r3, [r7, #3]
|
|
8002b5e: f003 020f and.w r2, r3, #15
|
|
8002b62: 4613 mov r3, r2
|
|
8002b64: 00db lsls r3, r3, #3
|
|
8002b66: 4413 add r3, r2
|
|
8002b68: 009b lsls r3, r3, #2
|
|
8002b6a: 3310 adds r3, #16
|
|
8002b6c: 687a ldr r2, [r7, #4]
|
|
8002b6e: 4413 add r3, r2
|
|
8002b70: 3304 adds r3, #4
|
|
8002b72: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8002b74: 68fb ldr r3, [r7, #12]
|
|
8002b76: 2201 movs r2, #1
|
|
8002b78: 705a strb r2, [r3, #1]
|
|
8002b7a: e00f b.n 8002b9c <HAL_PCD_EP_Open+0x66>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002b7c: 78fb ldrb r3, [r7, #3]
|
|
8002b7e: f003 020f and.w r2, r3, #15
|
|
8002b82: 4613 mov r3, r2
|
|
8002b84: 00db lsls r3, r3, #3
|
|
8002b86: 4413 add r3, r2
|
|
8002b88: 009b lsls r3, r3, #2
|
|
8002b8a: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002b8e: 687a ldr r2, [r7, #4]
|
|
8002b90: 4413 add r3, r2
|
|
8002b92: 3304 adds r3, #4
|
|
8002b94: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8002b96: 68fb ldr r3, [r7, #12]
|
|
8002b98: 2200 movs r2, #0
|
|
8002b9a: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002b9c: 78fb ldrb r3, [r7, #3]
|
|
8002b9e: f003 030f and.w r3, r3, #15
|
|
8002ba2: b2da uxtb r2, r3
|
|
8002ba4: 68fb ldr r3, [r7, #12]
|
|
8002ba6: 701a strb r2, [r3, #0]
|
|
ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
|
|
8002ba8: 883b ldrh r3, [r7, #0]
|
|
8002baa: f3c3 020a ubfx r2, r3, #0, #11
|
|
8002bae: 68fb ldr r3, [r7, #12]
|
|
8002bb0: 609a str r2, [r3, #8]
|
|
ep->type = ep_type;
|
|
8002bb2: 68fb ldr r3, [r7, #12]
|
|
8002bb4: 78ba ldrb r2, [r7, #2]
|
|
8002bb6: 711a strb r2, [r3, #4]
|
|
|
|
if (ep->is_in != 0U)
|
|
8002bb8: 68fb ldr r3, [r7, #12]
|
|
8002bba: 785b ldrb r3, [r3, #1]
|
|
8002bbc: 2b00 cmp r3, #0
|
|
8002bbe: d004 beq.n 8002bca <HAL_PCD_EP_Open+0x94>
|
|
{
|
|
/* Assign a Tx FIFO */
|
|
ep->tx_fifo_num = ep->num;
|
|
8002bc0: 68fb ldr r3, [r7, #12]
|
|
8002bc2: 781b ldrb r3, [r3, #0]
|
|
8002bc4: 461a mov r2, r3
|
|
8002bc6: 68fb ldr r3, [r7, #12]
|
|
8002bc8: 835a strh r2, [r3, #26]
|
|
}
|
|
|
|
/* Set initial data PID. */
|
|
if (ep_type == EP_TYPE_BULK)
|
|
8002bca: 78bb ldrb r3, [r7, #2]
|
|
8002bcc: 2b02 cmp r3, #2
|
|
8002bce: d102 bne.n 8002bd6 <HAL_PCD_EP_Open+0xa0>
|
|
{
|
|
ep->data_pid_start = 0U;
|
|
8002bd0: 68fb ldr r3, [r7, #12]
|
|
8002bd2: 2200 movs r2, #0
|
|
8002bd4: 715a strb r2, [r3, #5]
|
|
}
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8002bd6: 687b ldr r3, [r7, #4]
|
|
8002bd8: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002bdc: 2b01 cmp r3, #1
|
|
8002bde: d101 bne.n 8002be4 <HAL_PCD_EP_Open+0xae>
|
|
8002be0: 2302 movs r3, #2
|
|
8002be2: e00e b.n 8002c02 <HAL_PCD_EP_Open+0xcc>
|
|
8002be4: 687b ldr r3, [r7, #4]
|
|
8002be6: 2201 movs r2, #1
|
|
8002be8: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
|
|
8002bec: 687b ldr r3, [r7, #4]
|
|
8002bee: 681b ldr r3, [r3, #0]
|
|
8002bf0: 68f9 ldr r1, [r7, #12]
|
|
8002bf2: 4618 mov r0, r3
|
|
8002bf4: f003 fab2 bl 800615c <USB_ActivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002bf8: 687b ldr r3, [r7, #4]
|
|
8002bfa: 2200 movs r2, #0
|
|
8002bfc: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return ret;
|
|
8002c00: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
8002c02: 4618 mov r0, r3
|
|
8002c04: 3710 adds r7, #16
|
|
8002c06: 46bd mov sp, r7
|
|
8002c08: bd80 pop {r7, pc}
|
|
|
|
08002c0a <HAL_PCD_EP_Close>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8002c0a: b580 push {r7, lr}
|
|
8002c0c: b084 sub sp, #16
|
|
8002c0e: af00 add r7, sp, #0
|
|
8002c10: 6078 str r0, [r7, #4]
|
|
8002c12: 460b mov r3, r1
|
|
8002c14: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8002c16: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002c1a: 2b00 cmp r3, #0
|
|
8002c1c: da0f bge.n 8002c3e <HAL_PCD_EP_Close+0x34>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002c1e: 78fb ldrb r3, [r7, #3]
|
|
8002c20: f003 020f and.w r2, r3, #15
|
|
8002c24: 4613 mov r3, r2
|
|
8002c26: 00db lsls r3, r3, #3
|
|
8002c28: 4413 add r3, r2
|
|
8002c2a: 009b lsls r3, r3, #2
|
|
8002c2c: 3310 adds r3, #16
|
|
8002c2e: 687a ldr r2, [r7, #4]
|
|
8002c30: 4413 add r3, r2
|
|
8002c32: 3304 adds r3, #4
|
|
8002c34: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8002c36: 68fb ldr r3, [r7, #12]
|
|
8002c38: 2201 movs r2, #1
|
|
8002c3a: 705a strb r2, [r3, #1]
|
|
8002c3c: e00f b.n 8002c5e <HAL_PCD_EP_Close+0x54>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002c3e: 78fb ldrb r3, [r7, #3]
|
|
8002c40: f003 020f and.w r2, r3, #15
|
|
8002c44: 4613 mov r3, r2
|
|
8002c46: 00db lsls r3, r3, #3
|
|
8002c48: 4413 add r3, r2
|
|
8002c4a: 009b lsls r3, r3, #2
|
|
8002c4c: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002c50: 687a ldr r2, [r7, #4]
|
|
8002c52: 4413 add r3, r2
|
|
8002c54: 3304 adds r3, #4
|
|
8002c56: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8002c58: 68fb ldr r3, [r7, #12]
|
|
8002c5a: 2200 movs r2, #0
|
|
8002c5c: 705a strb r2, [r3, #1]
|
|
}
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002c5e: 78fb ldrb r3, [r7, #3]
|
|
8002c60: f003 030f and.w r3, r3, #15
|
|
8002c64: b2da uxtb r2, r3
|
|
8002c66: 68fb ldr r3, [r7, #12]
|
|
8002c68: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8002c6a: 687b ldr r3, [r7, #4]
|
|
8002c6c: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002c70: 2b01 cmp r3, #1
|
|
8002c72: d101 bne.n 8002c78 <HAL_PCD_EP_Close+0x6e>
|
|
8002c74: 2302 movs r3, #2
|
|
8002c76: e00e b.n 8002c96 <HAL_PCD_EP_Close+0x8c>
|
|
8002c78: 687b ldr r3, [r7, #4]
|
|
8002c7a: 2201 movs r2, #1
|
|
8002c7c: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
|
|
8002c80: 687b ldr r3, [r7, #4]
|
|
8002c82: 681b ldr r3, [r3, #0]
|
|
8002c84: 68f9 ldr r1, [r7, #12]
|
|
8002c86: 4618 mov r0, r3
|
|
8002c88: f003 faf0 bl 800626c <USB_DeactivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002c8c: 687b ldr r3, [r7, #4]
|
|
8002c8e: 2200 movs r2, #0
|
|
8002c90: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
return HAL_OK;
|
|
8002c94: 2300 movs r3, #0
|
|
}
|
|
8002c96: 4618 mov r0, r3
|
|
8002c98: 3710 adds r7, #16
|
|
8002c9a: 46bd mov sp, r7
|
|
8002c9c: bd80 pop {r7, pc}
|
|
|
|
08002c9e <HAL_PCD_EP_Receive>:
|
|
* @param pBuf pointer to the reception buffer
|
|
* @param len amount of data to be received
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
8002c9e: b580 push {r7, lr}
|
|
8002ca0: b086 sub sp, #24
|
|
8002ca2: af00 add r7, sp, #0
|
|
8002ca4: 60f8 str r0, [r7, #12]
|
|
8002ca6: 607a str r2, [r7, #4]
|
|
8002ca8: 603b str r3, [r7, #0]
|
|
8002caa: 460b mov r3, r1
|
|
8002cac: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002cae: 7afb ldrb r3, [r7, #11]
|
|
8002cb0: f003 020f and.w r2, r3, #15
|
|
8002cb4: 4613 mov r3, r2
|
|
8002cb6: 00db lsls r3, r3, #3
|
|
8002cb8: 4413 add r3, r2
|
|
8002cba: 009b lsls r3, r3, #2
|
|
8002cbc: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002cc0: 68fa ldr r2, [r7, #12]
|
|
8002cc2: 4413 add r3, r2
|
|
8002cc4: 3304 adds r3, #4
|
|
8002cc6: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
8002cc8: 697b ldr r3, [r7, #20]
|
|
8002cca: 687a ldr r2, [r7, #4]
|
|
8002ccc: 60da str r2, [r3, #12]
|
|
ep->xfer_len = len;
|
|
8002cce: 697b ldr r3, [r7, #20]
|
|
8002cd0: 683a ldr r2, [r7, #0]
|
|
8002cd2: 611a str r2, [r3, #16]
|
|
ep->xfer_count = 0U;
|
|
8002cd4: 697b ldr r3, [r7, #20]
|
|
8002cd6: 2200 movs r2, #0
|
|
8002cd8: 615a str r2, [r3, #20]
|
|
ep->is_in = 0U;
|
|
8002cda: 697b ldr r3, [r7, #20]
|
|
8002cdc: 2200 movs r2, #0
|
|
8002cde: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002ce0: 7afb ldrb r3, [r7, #11]
|
|
8002ce2: f003 030f and.w r3, r3, #15
|
|
8002ce6: b2da uxtb r2, r3
|
|
8002ce8: 697b ldr r3, [r7, #20]
|
|
8002cea: 701a strb r2, [r3, #0]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8002cec: 68fb ldr r3, [r7, #12]
|
|
8002cee: 799b ldrb r3, [r3, #6]
|
|
8002cf0: 2b01 cmp r3, #1
|
|
8002cf2: d102 bne.n 8002cfa <HAL_PCD_EP_Receive+0x5c>
|
|
{
|
|
ep->dma_addr = (uint32_t)pBuf;
|
|
8002cf4: 687a ldr r2, [r7, #4]
|
|
8002cf6: 697b ldr r3, [r7, #20]
|
|
8002cf8: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
|
|
8002cfa: 68fb ldr r3, [r7, #12]
|
|
8002cfc: 6818 ldr r0, [r3, #0]
|
|
8002cfe: 68fb ldr r3, [r7, #12]
|
|
8002d00: 799b ldrb r3, [r3, #6]
|
|
8002d02: 461a mov r2, r3
|
|
8002d04: 6979 ldr r1, [r7, #20]
|
|
8002d06: f003 fb8d bl 8006424 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
8002d0a: 2300 movs r3, #0
|
|
}
|
|
8002d0c: 4618 mov r0, r3
|
|
8002d0e: 3718 adds r7, #24
|
|
8002d10: 46bd mov sp, r7
|
|
8002d12: bd80 pop {r7, pc}
|
|
|
|
08002d14 <HAL_PCD_EP_Transmit>:
|
|
* @param pBuf pointer to the transmission buffer
|
|
* @param len amount of data to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
8002d14: b580 push {r7, lr}
|
|
8002d16: b086 sub sp, #24
|
|
8002d18: af00 add r7, sp, #0
|
|
8002d1a: 60f8 str r0, [r7, #12]
|
|
8002d1c: 607a str r2, [r7, #4]
|
|
8002d1e: 603b str r3, [r7, #0]
|
|
8002d20: 460b mov r3, r1
|
|
8002d22: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002d24: 7afb ldrb r3, [r7, #11]
|
|
8002d26: f003 020f and.w r2, r3, #15
|
|
8002d2a: 4613 mov r3, r2
|
|
8002d2c: 00db lsls r3, r3, #3
|
|
8002d2e: 4413 add r3, r2
|
|
8002d30: 009b lsls r3, r3, #2
|
|
8002d32: 3310 adds r3, #16
|
|
8002d34: 68fa ldr r2, [r7, #12]
|
|
8002d36: 4413 add r3, r2
|
|
8002d38: 3304 adds r3, #4
|
|
8002d3a: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
8002d3c: 697b ldr r3, [r7, #20]
|
|
8002d3e: 687a ldr r2, [r7, #4]
|
|
8002d40: 60da str r2, [r3, #12]
|
|
ep->xfer_len = len;
|
|
8002d42: 697b ldr r3, [r7, #20]
|
|
8002d44: 683a ldr r2, [r7, #0]
|
|
8002d46: 611a str r2, [r3, #16]
|
|
ep->xfer_count = 0U;
|
|
8002d48: 697b ldr r3, [r7, #20]
|
|
8002d4a: 2200 movs r2, #0
|
|
8002d4c: 615a str r2, [r3, #20]
|
|
ep->is_in = 1U;
|
|
8002d4e: 697b ldr r3, [r7, #20]
|
|
8002d50: 2201 movs r2, #1
|
|
8002d52: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002d54: 7afb ldrb r3, [r7, #11]
|
|
8002d56: f003 030f and.w r3, r3, #15
|
|
8002d5a: b2da uxtb r2, r3
|
|
8002d5c: 697b ldr r3, [r7, #20]
|
|
8002d5e: 701a strb r2, [r3, #0]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8002d60: 68fb ldr r3, [r7, #12]
|
|
8002d62: 799b ldrb r3, [r3, #6]
|
|
8002d64: 2b01 cmp r3, #1
|
|
8002d66: d102 bne.n 8002d6e <HAL_PCD_EP_Transmit+0x5a>
|
|
{
|
|
ep->dma_addr = (uint32_t)pBuf;
|
|
8002d68: 687a ldr r2, [r7, #4]
|
|
8002d6a: 697b ldr r3, [r7, #20]
|
|
8002d6c: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
|
|
8002d6e: 68fb ldr r3, [r7, #12]
|
|
8002d70: 6818 ldr r0, [r3, #0]
|
|
8002d72: 68fb ldr r3, [r7, #12]
|
|
8002d74: 799b ldrb r3, [r3, #6]
|
|
8002d76: 461a mov r2, r3
|
|
8002d78: 6979 ldr r1, [r7, #20]
|
|
8002d7a: f003 fb53 bl 8006424 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
8002d7e: 2300 movs r3, #0
|
|
}
|
|
8002d80: 4618 mov r0, r3
|
|
8002d82: 3718 adds r7, #24
|
|
8002d84: 46bd mov sp, r7
|
|
8002d86: bd80 pop {r7, pc}
|
|
|
|
08002d88 <HAL_PCD_EP_SetStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8002d88: b580 push {r7, lr}
|
|
8002d8a: b084 sub sp, #16
|
|
8002d8c: af00 add r7, sp, #0
|
|
8002d8e: 6078 str r0, [r7, #4]
|
|
8002d90: 460b mov r3, r1
|
|
8002d92: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
|
|
8002d94: 78fb ldrb r3, [r7, #3]
|
|
8002d96: f003 030f and.w r3, r3, #15
|
|
8002d9a: 687a ldr r2, [r7, #4]
|
|
8002d9c: 7912 ldrb r2, [r2, #4]
|
|
8002d9e: 4293 cmp r3, r2
|
|
8002da0: d901 bls.n 8002da6 <HAL_PCD_EP_SetStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8002da2: 2301 movs r3, #1
|
|
8002da4: e04f b.n 8002e46 <HAL_PCD_EP_SetStall+0xbe>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8002da6: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002daa: 2b00 cmp r3, #0
|
|
8002dac: da0f bge.n 8002dce <HAL_PCD_EP_SetStall+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002dae: 78fb ldrb r3, [r7, #3]
|
|
8002db0: f003 020f and.w r2, r3, #15
|
|
8002db4: 4613 mov r3, r2
|
|
8002db6: 00db lsls r3, r3, #3
|
|
8002db8: 4413 add r3, r2
|
|
8002dba: 009b lsls r3, r3, #2
|
|
8002dbc: 3310 adds r3, #16
|
|
8002dbe: 687a ldr r2, [r7, #4]
|
|
8002dc0: 4413 add r3, r2
|
|
8002dc2: 3304 adds r3, #4
|
|
8002dc4: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8002dc6: 68fb ldr r3, [r7, #12]
|
|
8002dc8: 2201 movs r2, #1
|
|
8002dca: 705a strb r2, [r3, #1]
|
|
8002dcc: e00d b.n 8002dea <HAL_PCD_EP_SetStall+0x62>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr];
|
|
8002dce: 78fa ldrb r2, [r7, #3]
|
|
8002dd0: 4613 mov r3, r2
|
|
8002dd2: 00db lsls r3, r3, #3
|
|
8002dd4: 4413 add r3, r2
|
|
8002dd6: 009b lsls r3, r3, #2
|
|
8002dd8: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002ddc: 687a ldr r2, [r7, #4]
|
|
8002dde: 4413 add r3, r2
|
|
8002de0: 3304 adds r3, #4
|
|
8002de2: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8002de4: 68fb ldr r3, [r7, #12]
|
|
8002de6: 2200 movs r2, #0
|
|
8002de8: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 1U;
|
|
8002dea: 68fb ldr r3, [r7, #12]
|
|
8002dec: 2201 movs r2, #1
|
|
8002dee: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002df0: 78fb ldrb r3, [r7, #3]
|
|
8002df2: f003 030f and.w r3, r3, #15
|
|
8002df6: b2da uxtb r2, r3
|
|
8002df8: 68fb ldr r3, [r7, #12]
|
|
8002dfa: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8002dfc: 687b ldr r3, [r7, #4]
|
|
8002dfe: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002e02: 2b01 cmp r3, #1
|
|
8002e04: d101 bne.n 8002e0a <HAL_PCD_EP_SetStall+0x82>
|
|
8002e06: 2302 movs r3, #2
|
|
8002e08: e01d b.n 8002e46 <HAL_PCD_EP_SetStall+0xbe>
|
|
8002e0a: 687b ldr r3, [r7, #4]
|
|
8002e0c: 2201 movs r2, #1
|
|
8002e0e: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
(void)USB_EPSetStall(hpcd->Instance, ep);
|
|
8002e12: 687b ldr r3, [r7, #4]
|
|
8002e14: 681b ldr r3, [r3, #0]
|
|
8002e16: 68f9 ldr r1, [r7, #12]
|
|
8002e18: 4618 mov r0, r3
|
|
8002e1a: f003 fee1 bl 8006be0 <USB_EPSetStall>
|
|
|
|
if ((ep_addr & EP_ADDR_MSK) == 0U)
|
|
8002e1e: 78fb ldrb r3, [r7, #3]
|
|
8002e20: f003 030f and.w r3, r3, #15
|
|
8002e24: 2b00 cmp r3, #0
|
|
8002e26: d109 bne.n 8002e3c <HAL_PCD_EP_SetStall+0xb4>
|
|
{
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
|
|
8002e28: 687b ldr r3, [r7, #4]
|
|
8002e2a: 6818 ldr r0, [r3, #0]
|
|
8002e2c: 687b ldr r3, [r7, #4]
|
|
8002e2e: 7999 ldrb r1, [r3, #6]
|
|
8002e30: 687b ldr r3, [r7, #4]
|
|
8002e32: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8002e36: 461a mov r2, r3
|
|
8002e38: f004 f8d2 bl 8006fe0 <USB_EP0_OutStart>
|
|
}
|
|
|
|
__HAL_UNLOCK(hpcd);
|
|
8002e3c: 687b ldr r3, [r7, #4]
|
|
8002e3e: 2200 movs r2, #0
|
|
8002e40: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8002e44: 2300 movs r3, #0
|
|
}
|
|
8002e46: 4618 mov r0, r3
|
|
8002e48: 3710 adds r7, #16
|
|
8002e4a: 46bd mov sp, r7
|
|
8002e4c: bd80 pop {r7, pc}
|
|
|
|
08002e4e <HAL_PCD_EP_ClrStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8002e4e: b580 push {r7, lr}
|
|
8002e50: b084 sub sp, #16
|
|
8002e52: af00 add r7, sp, #0
|
|
8002e54: 6078 str r0, [r7, #4]
|
|
8002e56: 460b mov r3, r1
|
|
8002e58: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
|
|
8002e5a: 78fb ldrb r3, [r7, #3]
|
|
8002e5c: f003 030f and.w r3, r3, #15
|
|
8002e60: 687a ldr r2, [r7, #4]
|
|
8002e62: 7912 ldrb r2, [r2, #4]
|
|
8002e64: 4293 cmp r3, r2
|
|
8002e66: d901 bls.n 8002e6c <HAL_PCD_EP_ClrStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8002e68: 2301 movs r3, #1
|
|
8002e6a: e042 b.n 8002ef2 <HAL_PCD_EP_ClrStall+0xa4>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8002e6c: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002e70: 2b00 cmp r3, #0
|
|
8002e72: da0f bge.n 8002e94 <HAL_PCD_EP_ClrStall+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002e74: 78fb ldrb r3, [r7, #3]
|
|
8002e76: f003 020f and.w r2, r3, #15
|
|
8002e7a: 4613 mov r3, r2
|
|
8002e7c: 00db lsls r3, r3, #3
|
|
8002e7e: 4413 add r3, r2
|
|
8002e80: 009b lsls r3, r3, #2
|
|
8002e82: 3310 adds r3, #16
|
|
8002e84: 687a ldr r2, [r7, #4]
|
|
8002e86: 4413 add r3, r2
|
|
8002e88: 3304 adds r3, #4
|
|
8002e8a: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8002e8c: 68fb ldr r3, [r7, #12]
|
|
8002e8e: 2201 movs r2, #1
|
|
8002e90: 705a strb r2, [r3, #1]
|
|
8002e92: e00f b.n 8002eb4 <HAL_PCD_EP_ClrStall+0x66>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002e94: 78fb ldrb r3, [r7, #3]
|
|
8002e96: f003 020f and.w r2, r3, #15
|
|
8002e9a: 4613 mov r3, r2
|
|
8002e9c: 00db lsls r3, r3, #3
|
|
8002e9e: 4413 add r3, r2
|
|
8002ea0: 009b lsls r3, r3, #2
|
|
8002ea2: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002ea6: 687a ldr r2, [r7, #4]
|
|
8002ea8: 4413 add r3, r2
|
|
8002eaa: 3304 adds r3, #4
|
|
8002eac: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8002eae: 68fb ldr r3, [r7, #12]
|
|
8002eb0: 2200 movs r2, #0
|
|
8002eb2: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 0U;
|
|
8002eb4: 68fb ldr r3, [r7, #12]
|
|
8002eb6: 2200 movs r2, #0
|
|
8002eb8: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002eba: 78fb ldrb r3, [r7, #3]
|
|
8002ebc: f003 030f and.w r3, r3, #15
|
|
8002ec0: b2da uxtb r2, r3
|
|
8002ec2: 68fb ldr r3, [r7, #12]
|
|
8002ec4: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8002ec6: 687b ldr r3, [r7, #4]
|
|
8002ec8: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002ecc: 2b01 cmp r3, #1
|
|
8002ece: d101 bne.n 8002ed4 <HAL_PCD_EP_ClrStall+0x86>
|
|
8002ed0: 2302 movs r3, #2
|
|
8002ed2: e00e b.n 8002ef2 <HAL_PCD_EP_ClrStall+0xa4>
|
|
8002ed4: 687b ldr r3, [r7, #4]
|
|
8002ed6: 2201 movs r2, #1
|
|
8002ed8: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_EPClearStall(hpcd->Instance, ep);
|
|
8002edc: 687b ldr r3, [r7, #4]
|
|
8002ede: 681b ldr r3, [r3, #0]
|
|
8002ee0: 68f9 ldr r1, [r7, #12]
|
|
8002ee2: 4618 mov r0, r3
|
|
8002ee4: f003 feea bl 8006cbc <USB_EPClearStall>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002ee8: 687b ldr r3, [r7, #4]
|
|
8002eea: 2200 movs r2, #0
|
|
8002eec: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8002ef0: 2300 movs r3, #0
|
|
}
|
|
8002ef2: 4618 mov r0, r3
|
|
8002ef4: 3710 adds r7, #16
|
|
8002ef6: 46bd mov sp, r7
|
|
8002ef8: bd80 pop {r7, pc}
|
|
|
|
08002efa <HAL_PCD_EP_Abort>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8002efa: b580 push {r7, lr}
|
|
8002efc: b084 sub sp, #16
|
|
8002efe: af00 add r7, sp, #0
|
|
8002f00: 6078 str r0, [r7, #4]
|
|
8002f02: 460b mov r3, r1
|
|
8002f04: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef ret;
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8002f06: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002f0a: 2b00 cmp r3, #0
|
|
8002f0c: da0c bge.n 8002f28 <HAL_PCD_EP_Abort+0x2e>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002f0e: 78fb ldrb r3, [r7, #3]
|
|
8002f10: f003 020f and.w r2, r3, #15
|
|
8002f14: 4613 mov r3, r2
|
|
8002f16: 00db lsls r3, r3, #3
|
|
8002f18: 4413 add r3, r2
|
|
8002f1a: 009b lsls r3, r3, #2
|
|
8002f1c: 3310 adds r3, #16
|
|
8002f1e: 687a ldr r2, [r7, #4]
|
|
8002f20: 4413 add r3, r2
|
|
8002f22: 3304 adds r3, #4
|
|
8002f24: 60fb str r3, [r7, #12]
|
|
8002f26: e00c b.n 8002f42 <HAL_PCD_EP_Abort+0x48>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002f28: 78fb ldrb r3, [r7, #3]
|
|
8002f2a: f003 020f and.w r2, r3, #15
|
|
8002f2e: 4613 mov r3, r2
|
|
8002f30: 00db lsls r3, r3, #3
|
|
8002f32: 4413 add r3, r2
|
|
8002f34: 009b lsls r3, r3, #2
|
|
8002f36: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002f3a: 687a ldr r2, [r7, #4]
|
|
8002f3c: 4413 add r3, r2
|
|
8002f3e: 3304 adds r3, #4
|
|
8002f40: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Stop Xfer */
|
|
ret = USB_EPStopXfer(hpcd->Instance, ep);
|
|
8002f42: 687b ldr r3, [r7, #4]
|
|
8002f44: 681b ldr r3, [r3, #0]
|
|
8002f46: 68f9 ldr r1, [r7, #12]
|
|
8002f48: 4618 mov r0, r3
|
|
8002f4a: f003 fd09 bl 8006960 <USB_EPStopXfer>
|
|
8002f4e: 4603 mov r3, r0
|
|
8002f50: 72fb strb r3, [r7, #11]
|
|
|
|
return ret;
|
|
8002f52: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
8002f54: 4618 mov r0, r3
|
|
8002f56: 3710 adds r7, #16
|
|
8002f58: 46bd mov sp, r7
|
|
8002f5a: bd80 pop {r7, pc}
|
|
|
|
08002f5c <PCD_WriteEmptyTxFifo>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8002f5c: b580 push {r7, lr}
|
|
8002f5e: b08a sub sp, #40 @ 0x28
|
|
8002f60: af02 add r7, sp, #8
|
|
8002f62: 6078 str r0, [r7, #4]
|
|
8002f64: 6039 str r1, [r7, #0]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8002f66: 687b ldr r3, [r7, #4]
|
|
8002f68: 681b ldr r3, [r3, #0]
|
|
8002f6a: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8002f6c: 697b ldr r3, [r7, #20]
|
|
8002f6e: 613b str r3, [r7, #16]
|
|
USB_OTG_EPTypeDef *ep;
|
|
uint32_t len;
|
|
uint32_t len32b;
|
|
uint32_t fifoemptymsk;
|
|
|
|
ep = &hpcd->IN_ep[epnum];
|
|
8002f70: 683a ldr r2, [r7, #0]
|
|
8002f72: 4613 mov r3, r2
|
|
8002f74: 00db lsls r3, r3, #3
|
|
8002f76: 4413 add r3, r2
|
|
8002f78: 009b lsls r3, r3, #2
|
|
8002f7a: 3310 adds r3, #16
|
|
8002f7c: 687a ldr r2, [r7, #4]
|
|
8002f7e: 4413 add r3, r2
|
|
8002f80: 3304 adds r3, #4
|
|
8002f82: 60fb str r3, [r7, #12]
|
|
|
|
if (ep->xfer_count > ep->xfer_len)
|
|
8002f84: 68fb ldr r3, [r7, #12]
|
|
8002f86: 695a ldr r2, [r3, #20]
|
|
8002f88: 68fb ldr r3, [r7, #12]
|
|
8002f8a: 691b ldr r3, [r3, #16]
|
|
8002f8c: 429a cmp r2, r3
|
|
8002f8e: d901 bls.n 8002f94 <PCD_WriteEmptyTxFifo+0x38>
|
|
{
|
|
return HAL_ERROR;
|
|
8002f90: 2301 movs r3, #1
|
|
8002f92: e06b b.n 800306c <PCD_WriteEmptyTxFifo+0x110>
|
|
}
|
|
|
|
len = ep->xfer_len - ep->xfer_count;
|
|
8002f94: 68fb ldr r3, [r7, #12]
|
|
8002f96: 691a ldr r2, [r3, #16]
|
|
8002f98: 68fb ldr r3, [r7, #12]
|
|
8002f9a: 695b ldr r3, [r3, #20]
|
|
8002f9c: 1ad3 subs r3, r2, r3
|
|
8002f9e: 61fb str r3, [r7, #28]
|
|
|
|
if (len > ep->maxpacket)
|
|
8002fa0: 68fb ldr r3, [r7, #12]
|
|
8002fa2: 689b ldr r3, [r3, #8]
|
|
8002fa4: 69fa ldr r2, [r7, #28]
|
|
8002fa6: 429a cmp r2, r3
|
|
8002fa8: d902 bls.n 8002fb0 <PCD_WriteEmptyTxFifo+0x54>
|
|
{
|
|
len = ep->maxpacket;
|
|
8002faa: 68fb ldr r3, [r7, #12]
|
|
8002fac: 689b ldr r3, [r3, #8]
|
|
8002fae: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
len32b = (len + 3U) / 4U;
|
|
8002fb0: 69fb ldr r3, [r7, #28]
|
|
8002fb2: 3303 adds r3, #3
|
|
8002fb4: 089b lsrs r3, r3, #2
|
|
8002fb6: 61bb str r3, [r7, #24]
|
|
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8002fb8: e02a b.n 8003010 <PCD_WriteEmptyTxFifo+0xb4>
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
{
|
|
/* Write the FIFO */
|
|
len = ep->xfer_len - ep->xfer_count;
|
|
8002fba: 68fb ldr r3, [r7, #12]
|
|
8002fbc: 691a ldr r2, [r3, #16]
|
|
8002fbe: 68fb ldr r3, [r7, #12]
|
|
8002fc0: 695b ldr r3, [r3, #20]
|
|
8002fc2: 1ad3 subs r3, r2, r3
|
|
8002fc4: 61fb str r3, [r7, #28]
|
|
|
|
if (len > ep->maxpacket)
|
|
8002fc6: 68fb ldr r3, [r7, #12]
|
|
8002fc8: 689b ldr r3, [r3, #8]
|
|
8002fca: 69fa ldr r2, [r7, #28]
|
|
8002fcc: 429a cmp r2, r3
|
|
8002fce: d902 bls.n 8002fd6 <PCD_WriteEmptyTxFifo+0x7a>
|
|
{
|
|
len = ep->maxpacket;
|
|
8002fd0: 68fb ldr r3, [r7, #12]
|
|
8002fd2: 689b ldr r3, [r3, #8]
|
|
8002fd4: 61fb str r3, [r7, #28]
|
|
}
|
|
len32b = (len + 3U) / 4U;
|
|
8002fd6: 69fb ldr r3, [r7, #28]
|
|
8002fd8: 3303 adds r3, #3
|
|
8002fda: 089b lsrs r3, r3, #2
|
|
8002fdc: 61bb str r3, [r7, #24]
|
|
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
|
|
8002fde: 68fb ldr r3, [r7, #12]
|
|
8002fe0: 68d9 ldr r1, [r3, #12]
|
|
8002fe2: 683b ldr r3, [r7, #0]
|
|
8002fe4: b2da uxtb r2, r3
|
|
8002fe6: 69fb ldr r3, [r7, #28]
|
|
8002fe8: b298 uxth r0, r3
|
|
(uint8_t)hpcd->Init.dma_enable);
|
|
8002fea: 687b ldr r3, [r7, #4]
|
|
8002fec: 799b ldrb r3, [r3, #6]
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
|
|
8002fee: 9300 str r3, [sp, #0]
|
|
8002ff0: 4603 mov r3, r0
|
|
8002ff2: 6978 ldr r0, [r7, #20]
|
|
8002ff4: f003 fd5e bl 8006ab4 <USB_WritePacket>
|
|
|
|
ep->xfer_buff += len;
|
|
8002ff8: 68fb ldr r3, [r7, #12]
|
|
8002ffa: 68da ldr r2, [r3, #12]
|
|
8002ffc: 69fb ldr r3, [r7, #28]
|
|
8002ffe: 441a add r2, r3
|
|
8003000: 68fb ldr r3, [r7, #12]
|
|
8003002: 60da str r2, [r3, #12]
|
|
ep->xfer_count += len;
|
|
8003004: 68fb ldr r3, [r7, #12]
|
|
8003006: 695a ldr r2, [r3, #20]
|
|
8003008: 69fb ldr r3, [r7, #28]
|
|
800300a: 441a add r2, r3
|
|
800300c: 68fb ldr r3, [r7, #12]
|
|
800300e: 615a str r2, [r3, #20]
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8003010: 683b ldr r3, [r7, #0]
|
|
8003012: 015a lsls r2, r3, #5
|
|
8003014: 693b ldr r3, [r7, #16]
|
|
8003016: 4413 add r3, r2
|
|
8003018: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800301c: 699b ldr r3, [r3, #24]
|
|
800301e: b29b uxth r3, r3
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
8003020: 69ba ldr r2, [r7, #24]
|
|
8003022: 429a cmp r2, r3
|
|
8003024: d809 bhi.n 800303a <PCD_WriteEmptyTxFifo+0xde>
|
|
8003026: 68fb ldr r3, [r7, #12]
|
|
8003028: 695a ldr r2, [r3, #20]
|
|
800302a: 68fb ldr r3, [r7, #12]
|
|
800302c: 691b ldr r3, [r3, #16]
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
800302e: 429a cmp r2, r3
|
|
8003030: d203 bcs.n 800303a <PCD_WriteEmptyTxFifo+0xde>
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
8003032: 68fb ldr r3, [r7, #12]
|
|
8003034: 691b ldr r3, [r3, #16]
|
|
8003036: 2b00 cmp r3, #0
|
|
8003038: d1bf bne.n 8002fba <PCD_WriteEmptyTxFifo+0x5e>
|
|
}
|
|
|
|
if (ep->xfer_len <= ep->xfer_count)
|
|
800303a: 68fb ldr r3, [r7, #12]
|
|
800303c: 691a ldr r2, [r3, #16]
|
|
800303e: 68fb ldr r3, [r7, #12]
|
|
8003040: 695b ldr r3, [r3, #20]
|
|
8003042: 429a cmp r2, r3
|
|
8003044: d811 bhi.n 800306a <PCD_WriteEmptyTxFifo+0x10e>
|
|
{
|
|
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
|
|
8003046: 683b ldr r3, [r7, #0]
|
|
8003048: f003 030f and.w r3, r3, #15
|
|
800304c: 2201 movs r2, #1
|
|
800304e: fa02 f303 lsl.w r3, r2, r3
|
|
8003052: 60bb str r3, [r7, #8]
|
|
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
|
|
8003054: 693b ldr r3, [r7, #16]
|
|
8003056: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800305a: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
800305c: 68bb ldr r3, [r7, #8]
|
|
800305e: 43db mvns r3, r3
|
|
8003060: 6939 ldr r1, [r7, #16]
|
|
8003062: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8003066: 4013 ands r3, r2
|
|
8003068: 634b str r3, [r1, #52] @ 0x34
|
|
}
|
|
|
|
return HAL_OK;
|
|
800306a: 2300 movs r3, #0
|
|
}
|
|
800306c: 4618 mov r0, r3
|
|
800306e: 3720 adds r7, #32
|
|
8003070: 46bd mov sp, r7
|
|
8003072: bd80 pop {r7, pc}
|
|
|
|
08003074 <PCD_EP_OutXfrComplete_int>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8003074: b580 push {r7, lr}
|
|
8003076: b088 sub sp, #32
|
|
8003078: af00 add r7, sp, #0
|
|
800307a: 6078 str r0, [r7, #4]
|
|
800307c: 6039 str r1, [r7, #0]
|
|
USB_OTG_EPTypeDef *ep;
|
|
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
800307e: 687b ldr r3, [r7, #4]
|
|
8003080: 681b ldr r3, [r3, #0]
|
|
8003082: 61fb str r3, [r7, #28]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8003084: 69fb ldr r3, [r7, #28]
|
|
8003086: 61bb str r3, [r7, #24]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
8003088: 69fb ldr r3, [r7, #28]
|
|
800308a: 333c adds r3, #60 @ 0x3c
|
|
800308c: 3304 adds r3, #4
|
|
800308e: 681b ldr r3, [r3, #0]
|
|
8003090: 617b str r3, [r7, #20]
|
|
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
|
|
8003092: 683b ldr r3, [r7, #0]
|
|
8003094: 015a lsls r2, r3, #5
|
|
8003096: 69bb ldr r3, [r7, #24]
|
|
8003098: 4413 add r3, r2
|
|
800309a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800309e: 689b ldr r3, [r3, #8]
|
|
80030a0: 613b str r3, [r7, #16]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
80030a2: 687b ldr r3, [r7, #4]
|
|
80030a4: 799b ldrb r3, [r3, #6]
|
|
80030a6: 2b01 cmp r3, #1
|
|
80030a8: d17b bne.n 80031a2 <PCD_EP_OutXfrComplete_int+0x12e>
|
|
{
|
|
if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
|
|
80030aa: 693b ldr r3, [r7, #16]
|
|
80030ac: f003 0308 and.w r3, r3, #8
|
|
80030b0: 2b00 cmp r3, #0
|
|
80030b2: d015 beq.n 80030e0 <PCD_EP_OutXfrComplete_int+0x6c>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
80030b4: 697b ldr r3, [r7, #20]
|
|
80030b6: 4a61 ldr r2, [pc, #388] @ (800323c <PCD_EP_OutXfrComplete_int+0x1c8>)
|
|
80030b8: 4293 cmp r3, r2
|
|
80030ba: f240 80b9 bls.w 8003230 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
80030be: 693b ldr r3, [r7, #16]
|
|
80030c0: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
80030c4: 2b00 cmp r3, #0
|
|
80030c6: f000 80b3 beq.w 8003230 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
80030ca: 683b ldr r3, [r7, #0]
|
|
80030cc: 015a lsls r2, r3, #5
|
|
80030ce: 69bb ldr r3, [r7, #24]
|
|
80030d0: 4413 add r3, r2
|
|
80030d2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80030d6: 461a mov r2, r3
|
|
80030d8: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
80030dc: 6093 str r3, [r2, #8]
|
|
80030de: e0a7 b.n 8003230 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
}
|
|
else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
|
|
80030e0: 693b ldr r3, [r7, #16]
|
|
80030e2: f003 0320 and.w r3, r3, #32
|
|
80030e6: 2b00 cmp r3, #0
|
|
80030e8: d009 beq.n 80030fe <PCD_EP_OutXfrComplete_int+0x8a>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
80030ea: 683b ldr r3, [r7, #0]
|
|
80030ec: 015a lsls r2, r3, #5
|
|
80030ee: 69bb ldr r3, [r7, #24]
|
|
80030f0: 4413 add r3, r2
|
|
80030f2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80030f6: 461a mov r2, r3
|
|
80030f8: 2320 movs r3, #32
|
|
80030fa: 6093 str r3, [r2, #8]
|
|
80030fc: e098 b.n 8003230 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
|
|
80030fe: 693b ldr r3, [r7, #16]
|
|
8003100: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
8003104: 2b00 cmp r3, #0
|
|
8003106: f040 8093 bne.w 8003230 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
800310a: 697b ldr r3, [r7, #20]
|
|
800310c: 4a4b ldr r2, [pc, #300] @ (800323c <PCD_EP_OutXfrComplete_int+0x1c8>)
|
|
800310e: 4293 cmp r3, r2
|
|
8003110: d90f bls.n 8003132 <PCD_EP_OutXfrComplete_int+0xbe>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
8003112: 693b ldr r3, [r7, #16]
|
|
8003114: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8003118: 2b00 cmp r3, #0
|
|
800311a: d00a beq.n 8003132 <PCD_EP_OutXfrComplete_int+0xbe>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
800311c: 683b ldr r3, [r7, #0]
|
|
800311e: 015a lsls r2, r3, #5
|
|
8003120: 69bb ldr r3, [r7, #24]
|
|
8003122: 4413 add r3, r2
|
|
8003124: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003128: 461a mov r2, r3
|
|
800312a: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
800312e: 6093 str r3, [r2, #8]
|
|
8003130: e07e b.n 8003230 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[epnum];
|
|
8003132: 683a ldr r2, [r7, #0]
|
|
8003134: 4613 mov r3, r2
|
|
8003136: 00db lsls r3, r3, #3
|
|
8003138: 4413 add r3, r2
|
|
800313a: 009b lsls r3, r3, #2
|
|
800313c: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003140: 687a ldr r2, [r7, #4]
|
|
8003142: 4413 add r3, r2
|
|
8003144: 3304 adds r3, #4
|
|
8003146: 60fb str r3, [r7, #12]
|
|
|
|
/* out data packet received over EP */
|
|
ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
|
|
8003148: 68fb ldr r3, [r7, #12]
|
|
800314a: 6a1a ldr r2, [r3, #32]
|
|
800314c: 683b ldr r3, [r7, #0]
|
|
800314e: 0159 lsls r1, r3, #5
|
|
8003150: 69bb ldr r3, [r7, #24]
|
|
8003152: 440b add r3, r1
|
|
8003154: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003158: 691b ldr r3, [r3, #16]
|
|
800315a: f3c3 0312 ubfx r3, r3, #0, #19
|
|
800315e: 1ad2 subs r2, r2, r3
|
|
8003160: 68fb ldr r3, [r7, #12]
|
|
8003162: 615a str r2, [r3, #20]
|
|
|
|
if (epnum == 0U)
|
|
8003164: 683b ldr r3, [r7, #0]
|
|
8003166: 2b00 cmp r3, #0
|
|
8003168: d114 bne.n 8003194 <PCD_EP_OutXfrComplete_int+0x120>
|
|
{
|
|
if (ep->xfer_len == 0U)
|
|
800316a: 68fb ldr r3, [r7, #12]
|
|
800316c: 691b ldr r3, [r3, #16]
|
|
800316e: 2b00 cmp r3, #0
|
|
8003170: d109 bne.n 8003186 <PCD_EP_OutXfrComplete_int+0x112>
|
|
{
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
8003172: 687b ldr r3, [r7, #4]
|
|
8003174: 6818 ldr r0, [r3, #0]
|
|
8003176: 687b ldr r3, [r7, #4]
|
|
8003178: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
800317c: 461a mov r2, r3
|
|
800317e: 2101 movs r1, #1
|
|
8003180: f003 ff2e bl 8006fe0 <USB_EP0_OutStart>
|
|
8003184: e006 b.n 8003194 <PCD_EP_OutXfrComplete_int+0x120>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_buff += ep->xfer_count;
|
|
8003186: 68fb ldr r3, [r7, #12]
|
|
8003188: 68da ldr r2, [r3, #12]
|
|
800318a: 68fb ldr r3, [r7, #12]
|
|
800318c: 695b ldr r3, [r3, #20]
|
|
800318e: 441a add r2, r3
|
|
8003190: 68fb ldr r3, [r7, #12]
|
|
8003192: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
8003194: 683b ldr r3, [r7, #0]
|
|
8003196: b2db uxtb r3, r3
|
|
8003198: 4619 mov r1, r3
|
|
800319a: 6878 ldr r0, [r7, #4]
|
|
800319c: f005 ff10 bl 8008fc0 <HAL_PCD_DataOutStageCallback>
|
|
80031a0: e046 b.n 8003230 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
/* ... */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (gSNPSiD == USB_OTG_CORE_ID_310A)
|
|
80031a2: 697b ldr r3, [r7, #20]
|
|
80031a4: 4a26 ldr r2, [pc, #152] @ (8003240 <PCD_EP_OutXfrComplete_int+0x1cc>)
|
|
80031a6: 4293 cmp r3, r2
|
|
80031a8: d124 bne.n 80031f4 <PCD_EP_OutXfrComplete_int+0x180>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
|
|
80031aa: 693b ldr r3, [r7, #16]
|
|
80031ac: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80031b0: 2b00 cmp r3, #0
|
|
80031b2: d00a beq.n 80031ca <PCD_EP_OutXfrComplete_int+0x156>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
80031b4: 683b ldr r3, [r7, #0]
|
|
80031b6: 015a lsls r2, r3, #5
|
|
80031b8: 69bb ldr r3, [r7, #24]
|
|
80031ba: 4413 add r3, r2
|
|
80031bc: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80031c0: 461a mov r2, r3
|
|
80031c2: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
80031c6: 6093 str r3, [r2, #8]
|
|
80031c8: e032 b.n 8003230 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else
|
|
{
|
|
if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
|
|
80031ca: 693b ldr r3, [r7, #16]
|
|
80031cc: f003 0320 and.w r3, r3, #32
|
|
80031d0: 2b00 cmp r3, #0
|
|
80031d2: d008 beq.n 80031e6 <PCD_EP_OutXfrComplete_int+0x172>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
80031d4: 683b ldr r3, [r7, #0]
|
|
80031d6: 015a lsls r2, r3, #5
|
|
80031d8: 69bb ldr r3, [r7, #24]
|
|
80031da: 4413 add r3, r2
|
|
80031dc: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80031e0: 461a mov r2, r3
|
|
80031e2: 2320 movs r3, #32
|
|
80031e4: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
80031e6: 683b ldr r3, [r7, #0]
|
|
80031e8: b2db uxtb r3, r3
|
|
80031ea: 4619 mov r1, r3
|
|
80031ec: 6878 ldr r0, [r7, #4]
|
|
80031ee: f005 fee7 bl 8008fc0 <HAL_PCD_DataOutStageCallback>
|
|
80031f2: e01d b.n 8003230 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
|
|
80031f4: 683b ldr r3, [r7, #0]
|
|
80031f6: 2b00 cmp r3, #0
|
|
80031f8: d114 bne.n 8003224 <PCD_EP_OutXfrComplete_int+0x1b0>
|
|
80031fa: 6879 ldr r1, [r7, #4]
|
|
80031fc: 683a ldr r2, [r7, #0]
|
|
80031fe: 4613 mov r3, r2
|
|
8003200: 00db lsls r3, r3, #3
|
|
8003202: 4413 add r3, r2
|
|
8003204: 009b lsls r3, r3, #2
|
|
8003206: 440b add r3, r1
|
|
8003208: f503 7319 add.w r3, r3, #612 @ 0x264
|
|
800320c: 681b ldr r3, [r3, #0]
|
|
800320e: 2b00 cmp r3, #0
|
|
8003210: d108 bne.n 8003224 <PCD_EP_OutXfrComplete_int+0x1b0>
|
|
{
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
|
|
8003212: 687b ldr r3, [r7, #4]
|
|
8003214: 6818 ldr r0, [r3, #0]
|
|
8003216: 687b ldr r3, [r7, #4]
|
|
8003218: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
800321c: 461a mov r2, r3
|
|
800321e: 2100 movs r1, #0
|
|
8003220: f003 fede bl 8006fe0 <USB_EP0_OutStart>
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
8003224: 683b ldr r3, [r7, #0]
|
|
8003226: b2db uxtb r3, r3
|
|
8003228: 4619 mov r1, r3
|
|
800322a: 6878 ldr r0, [r7, #4]
|
|
800322c: f005 fec8 bl 8008fc0 <HAL_PCD_DataOutStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003230: 2300 movs r3, #0
|
|
}
|
|
8003232: 4618 mov r0, r3
|
|
8003234: 3720 adds r7, #32
|
|
8003236: 46bd mov sp, r7
|
|
8003238: bd80 pop {r7, pc}
|
|
800323a: bf00 nop
|
|
800323c: 4f54300a .word 0x4f54300a
|
|
8003240: 4f54310a .word 0x4f54310a
|
|
|
|
08003244 <PCD_EP_OutSetupPacket_int>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8003244: b580 push {r7, lr}
|
|
8003246: b086 sub sp, #24
|
|
8003248: af00 add r7, sp, #0
|
|
800324a: 6078 str r0, [r7, #4]
|
|
800324c: 6039 str r1, [r7, #0]
|
|
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
800324e: 687b ldr r3, [r7, #4]
|
|
8003250: 681b ldr r3, [r3, #0]
|
|
8003252: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8003254: 697b ldr r3, [r7, #20]
|
|
8003256: 613b str r3, [r7, #16]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
8003258: 697b ldr r3, [r7, #20]
|
|
800325a: 333c adds r3, #60 @ 0x3c
|
|
800325c: 3304 adds r3, #4
|
|
800325e: 681b ldr r3, [r3, #0]
|
|
8003260: 60fb str r3, [r7, #12]
|
|
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
|
|
8003262: 683b ldr r3, [r7, #0]
|
|
8003264: 015a lsls r2, r3, #5
|
|
8003266: 693b ldr r3, [r7, #16]
|
|
8003268: 4413 add r3, r2
|
|
800326a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800326e: 689b ldr r3, [r3, #8]
|
|
8003270: 60bb str r3, [r7, #8]
|
|
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8003272: 68fb ldr r3, [r7, #12]
|
|
8003274: 4a15 ldr r2, [pc, #84] @ (80032cc <PCD_EP_OutSetupPacket_int+0x88>)
|
|
8003276: 4293 cmp r3, r2
|
|
8003278: d90e bls.n 8003298 <PCD_EP_OutSetupPacket_int+0x54>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
800327a: 68bb ldr r3, [r7, #8]
|
|
800327c: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8003280: 2b00 cmp r3, #0
|
|
8003282: d009 beq.n 8003298 <PCD_EP_OutSetupPacket_int+0x54>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8003284: 683b ldr r3, [r7, #0]
|
|
8003286: 015a lsls r2, r3, #5
|
|
8003288: 693b ldr r3, [r7, #16]
|
|
800328a: 4413 add r3, r2
|
|
800328c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003290: 461a mov r2, r3
|
|
8003292: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8003296: 6093 str r3, [r2, #8]
|
|
|
|
/* Inform the upper layer that a setup packet is available */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SetupStageCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SetupStageCallback(hpcd);
|
|
8003298: 6878 ldr r0, [r7, #4]
|
|
800329a: f005 fe7f bl 8008f9c <HAL_PCD_SetupStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
|
|
800329e: 68fb ldr r3, [r7, #12]
|
|
80032a0: 4a0a ldr r2, [pc, #40] @ (80032cc <PCD_EP_OutSetupPacket_int+0x88>)
|
|
80032a2: 4293 cmp r3, r2
|
|
80032a4: d90c bls.n 80032c0 <PCD_EP_OutSetupPacket_int+0x7c>
|
|
80032a6: 687b ldr r3, [r7, #4]
|
|
80032a8: 799b ldrb r3, [r3, #6]
|
|
80032aa: 2b01 cmp r3, #1
|
|
80032ac: d108 bne.n 80032c0 <PCD_EP_OutSetupPacket_int+0x7c>
|
|
{
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
80032ae: 687b ldr r3, [r7, #4]
|
|
80032b0: 6818 ldr r0, [r3, #0]
|
|
80032b2: 687b ldr r3, [r7, #4]
|
|
80032b4: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
80032b8: 461a mov r2, r3
|
|
80032ba: 2101 movs r1, #1
|
|
80032bc: f003 fe90 bl 8006fe0 <USB_EP0_OutStart>
|
|
}
|
|
|
|
return HAL_OK;
|
|
80032c0: 2300 movs r3, #0
|
|
}
|
|
80032c2: 4618 mov r0, r3
|
|
80032c4: 3718 adds r7, #24
|
|
80032c6: 46bd mov sp, r7
|
|
80032c8: bd80 pop {r7, pc}
|
|
80032ca: bf00 nop
|
|
80032cc: 4f54300a .word 0x4f54300a
|
|
|
|
080032d0 <HAL_PCDEx_SetTxFiFo>:
|
|
* @param fifo The number of Tx fifo
|
|
* @param size Fifo size
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
|
|
{
|
|
80032d0: b480 push {r7}
|
|
80032d2: b085 sub sp, #20
|
|
80032d4: af00 add r7, sp, #0
|
|
80032d6: 6078 str r0, [r7, #4]
|
|
80032d8: 460b mov r3, r1
|
|
80032da: 70fb strb r3, [r7, #3]
|
|
80032dc: 4613 mov r3, r2
|
|
80032de: 803b strh r3, [r7, #0]
|
|
--> Txn should be configured with the minimum space of 16 words
|
|
The FIFO is used optimally when used TxFIFOs are allocated in the top
|
|
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
|
|
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
|
|
|
|
Tx_Offset = hpcd->Instance->GRXFSIZ;
|
|
80032e0: 687b ldr r3, [r7, #4]
|
|
80032e2: 681b ldr r3, [r3, #0]
|
|
80032e4: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80032e6: 60bb str r3, [r7, #8]
|
|
|
|
if (fifo == 0U)
|
|
80032e8: 78fb ldrb r3, [r7, #3]
|
|
80032ea: 2b00 cmp r3, #0
|
|
80032ec: d107 bne.n 80032fe <HAL_PCDEx_SetTxFiFo+0x2e>
|
|
{
|
|
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
|
|
80032ee: 883b ldrh r3, [r7, #0]
|
|
80032f0: 0419 lsls r1, r3, #16
|
|
80032f2: 687b ldr r3, [r7, #4]
|
|
80032f4: 681b ldr r3, [r3, #0]
|
|
80032f6: 68ba ldr r2, [r7, #8]
|
|
80032f8: 430a orrs r2, r1
|
|
80032fa: 629a str r2, [r3, #40] @ 0x28
|
|
80032fc: e028 b.n 8003350 <HAL_PCDEx_SetTxFiFo+0x80>
|
|
}
|
|
else
|
|
{
|
|
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
|
|
80032fe: 687b ldr r3, [r7, #4]
|
|
8003300: 681b ldr r3, [r3, #0]
|
|
8003302: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003304: 0c1b lsrs r3, r3, #16
|
|
8003306: 68ba ldr r2, [r7, #8]
|
|
8003308: 4413 add r3, r2
|
|
800330a: 60bb str r3, [r7, #8]
|
|
for (i = 0U; i < (fifo - 1U); i++)
|
|
800330c: 2300 movs r3, #0
|
|
800330e: 73fb strb r3, [r7, #15]
|
|
8003310: e00d b.n 800332e <HAL_PCDEx_SetTxFiFo+0x5e>
|
|
{
|
|
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
|
|
8003312: 687b ldr r3, [r7, #4]
|
|
8003314: 681a ldr r2, [r3, #0]
|
|
8003316: 7bfb ldrb r3, [r7, #15]
|
|
8003318: 3340 adds r3, #64 @ 0x40
|
|
800331a: 009b lsls r3, r3, #2
|
|
800331c: 4413 add r3, r2
|
|
800331e: 685b ldr r3, [r3, #4]
|
|
8003320: 0c1b lsrs r3, r3, #16
|
|
8003322: 68ba ldr r2, [r7, #8]
|
|
8003324: 4413 add r3, r2
|
|
8003326: 60bb str r3, [r7, #8]
|
|
for (i = 0U; i < (fifo - 1U); i++)
|
|
8003328: 7bfb ldrb r3, [r7, #15]
|
|
800332a: 3301 adds r3, #1
|
|
800332c: 73fb strb r3, [r7, #15]
|
|
800332e: 7bfa ldrb r2, [r7, #15]
|
|
8003330: 78fb ldrb r3, [r7, #3]
|
|
8003332: 3b01 subs r3, #1
|
|
8003334: 429a cmp r2, r3
|
|
8003336: d3ec bcc.n 8003312 <HAL_PCDEx_SetTxFiFo+0x42>
|
|
}
|
|
|
|
/* Multiply Tx_Size by 2 to get higher performance */
|
|
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
|
|
8003338: 883b ldrh r3, [r7, #0]
|
|
800333a: 0418 lsls r0, r3, #16
|
|
800333c: 687b ldr r3, [r7, #4]
|
|
800333e: 6819 ldr r1, [r3, #0]
|
|
8003340: 78fb ldrb r3, [r7, #3]
|
|
8003342: 3b01 subs r3, #1
|
|
8003344: 68ba ldr r2, [r7, #8]
|
|
8003346: 4302 orrs r2, r0
|
|
8003348: 3340 adds r3, #64 @ 0x40
|
|
800334a: 009b lsls r3, r3, #2
|
|
800334c: 440b add r3, r1
|
|
800334e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003350: 2300 movs r3, #0
|
|
}
|
|
8003352: 4618 mov r0, r3
|
|
8003354: 3714 adds r7, #20
|
|
8003356: 46bd mov sp, r7
|
|
8003358: f85d 7b04 ldr.w r7, [sp], #4
|
|
800335c: 4770 bx lr
|
|
|
|
0800335e <HAL_PCDEx_SetRxFiFo>:
|
|
* @param hpcd PCD handle
|
|
* @param size Size of Rx fifo
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
|
|
{
|
|
800335e: b480 push {r7}
|
|
8003360: b083 sub sp, #12
|
|
8003362: af00 add r7, sp, #0
|
|
8003364: 6078 str r0, [r7, #4]
|
|
8003366: 460b mov r3, r1
|
|
8003368: 807b strh r3, [r7, #2]
|
|
hpcd->Instance->GRXFSIZ = size;
|
|
800336a: 687b ldr r3, [r7, #4]
|
|
800336c: 681b ldr r3, [r3, #0]
|
|
800336e: 887a ldrh r2, [r7, #2]
|
|
8003370: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_OK;
|
|
8003372: 2300 movs r3, #0
|
|
}
|
|
8003374: 4618 mov r0, r3
|
|
8003376: 370c adds r7, #12
|
|
8003378: 46bd mov sp, r7
|
|
800337a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800337e: 4770 bx lr
|
|
|
|
08003380 <HAL_PCDEx_ActivateLPM>:
|
|
* @brief Activate LPM feature.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8003380: b480 push {r7}
|
|
8003382: b085 sub sp, #20
|
|
8003384: af00 add r7, sp, #0
|
|
8003386: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8003388: 687b ldr r3, [r7, #4]
|
|
800338a: 681b ldr r3, [r3, #0]
|
|
800338c: 60fb str r3, [r7, #12]
|
|
|
|
hpcd->lpm_active = 1U;
|
|
800338e: 687b ldr r3, [r7, #4]
|
|
8003390: 2201 movs r2, #1
|
|
8003392: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8
|
|
hpcd->LPM_State = LPM_L0;
|
|
8003396: 687b ldr r3, [r7, #4]
|
|
8003398: 2200 movs r2, #0
|
|
800339a: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
|
|
800339e: 68fb ldr r3, [r7, #12]
|
|
80033a0: 699b ldr r3, [r3, #24]
|
|
80033a2: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000
|
|
80033a6: 68fb ldr r3, [r7, #12]
|
|
80033a8: 619a str r2, [r3, #24]
|
|
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
|
|
80033aa: 68fb ldr r3, [r7, #12]
|
|
80033ac: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80033ae: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80033b2: f043 0303 orr.w r3, r3, #3
|
|
80033b6: 68fa ldr r2, [r7, #12]
|
|
80033b8: 6553 str r3, [r2, #84] @ 0x54
|
|
|
|
return HAL_OK;
|
|
80033ba: 2300 movs r3, #0
|
|
}
|
|
80033bc: 4618 mov r0, r3
|
|
80033be: 3714 adds r7, #20
|
|
80033c0: 46bd mov sp, r7
|
|
80033c2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80033c6: 4770 bx lr
|
|
|
|
080033c8 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
80033c8: b580 push {r7, lr}
|
|
80033ca: b084 sub sp, #16
|
|
80033cc: af00 add r7, sp, #0
|
|
80033ce: 6078 str r0, [r7, #4]
|
|
80033d0: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
80033d2: 687b ldr r3, [r7, #4]
|
|
80033d4: 2b00 cmp r3, #0
|
|
80033d6: d101 bne.n 80033dc <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
80033d8: 2301 movs r3, #1
|
|
80033da: e0cc b.n 8003576 <HAL_RCC_ClockConfig+0x1ae>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
80033dc: 4b68 ldr r3, [pc, #416] @ (8003580 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80033de: 681b ldr r3, [r3, #0]
|
|
80033e0: f003 030f and.w r3, r3, #15
|
|
80033e4: 683a ldr r2, [r7, #0]
|
|
80033e6: 429a cmp r2, r3
|
|
80033e8: d90c bls.n 8003404 <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80033ea: 4b65 ldr r3, [pc, #404] @ (8003580 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80033ec: 683a ldr r2, [r7, #0]
|
|
80033ee: b2d2 uxtb r2, r2
|
|
80033f0: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80033f2: 4b63 ldr r3, [pc, #396] @ (8003580 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80033f4: 681b ldr r3, [r3, #0]
|
|
80033f6: f003 030f and.w r3, r3, #15
|
|
80033fa: 683a ldr r2, [r7, #0]
|
|
80033fc: 429a cmp r2, r3
|
|
80033fe: d001 beq.n 8003404 <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003400: 2301 movs r3, #1
|
|
8003402: e0b8 b.n 8003576 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8003404: 687b ldr r3, [r7, #4]
|
|
8003406: 681b ldr r3, [r3, #0]
|
|
8003408: f003 0302 and.w r3, r3, #2
|
|
800340c: 2b00 cmp r3, #0
|
|
800340e: d020 beq.n 8003452 <HAL_RCC_ClockConfig+0x8a>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8003410: 687b ldr r3, [r7, #4]
|
|
8003412: 681b ldr r3, [r3, #0]
|
|
8003414: f003 0304 and.w r3, r3, #4
|
|
8003418: 2b00 cmp r3, #0
|
|
800341a: d005 beq.n 8003428 <HAL_RCC_ClockConfig+0x60>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
800341c: 4b59 ldr r3, [pc, #356] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800341e: 689b ldr r3, [r3, #8]
|
|
8003420: 4a58 ldr r2, [pc, #352] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003422: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
|
|
8003426: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8003428: 687b ldr r3, [r7, #4]
|
|
800342a: 681b ldr r3, [r3, #0]
|
|
800342c: f003 0308 and.w r3, r3, #8
|
|
8003430: 2b00 cmp r3, #0
|
|
8003432: d005 beq.n 8003440 <HAL_RCC_ClockConfig+0x78>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
8003434: 4b53 ldr r3, [pc, #332] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003436: 689b ldr r3, [r3, #8]
|
|
8003438: 4a52 ldr r2, [pc, #328] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800343a: f443 4360 orr.w r3, r3, #57344 @ 0xe000
|
|
800343e: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8003440: 4b50 ldr r3, [pc, #320] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003442: 689b ldr r3, [r3, #8]
|
|
8003444: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8003448: 687b ldr r3, [r7, #4]
|
|
800344a: 689b ldr r3, [r3, #8]
|
|
800344c: 494d ldr r1, [pc, #308] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800344e: 4313 orrs r3, r2
|
|
8003450: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8003452: 687b ldr r3, [r7, #4]
|
|
8003454: 681b ldr r3, [r3, #0]
|
|
8003456: f003 0301 and.w r3, r3, #1
|
|
800345a: 2b00 cmp r3, #0
|
|
800345c: d044 beq.n 80034e8 <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
800345e: 687b ldr r3, [r7, #4]
|
|
8003460: 685b ldr r3, [r3, #4]
|
|
8003462: 2b01 cmp r3, #1
|
|
8003464: d107 bne.n 8003476 <HAL_RCC_ClockConfig+0xae>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8003466: 4b47 ldr r3, [pc, #284] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003468: 681b ldr r3, [r3, #0]
|
|
800346a: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800346e: 2b00 cmp r3, #0
|
|
8003470: d119 bne.n 80034a6 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8003472: 2301 movs r3, #1
|
|
8003474: e07f b.n 8003576 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
8003476: 687b ldr r3, [r7, #4]
|
|
8003478: 685b ldr r3, [r3, #4]
|
|
800347a: 2b02 cmp r3, #2
|
|
800347c: d003 beq.n 8003486 <HAL_RCC_ClockConfig+0xbe>
|
|
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
|
|
800347e: 687b ldr r3, [r7, #4]
|
|
8003480: 685b ldr r3, [r3, #4]
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
8003482: 2b03 cmp r3, #3
|
|
8003484: d107 bne.n 8003496 <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8003486: 4b3f ldr r3, [pc, #252] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003488: 681b ldr r3, [r3, #0]
|
|
800348a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800348e: 2b00 cmp r3, #0
|
|
8003490: d109 bne.n 80034a6 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8003492: 2301 movs r3, #1
|
|
8003494: e06f b.n 8003576 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8003496: 4b3b ldr r3, [pc, #236] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003498: 681b ldr r3, [r3, #0]
|
|
800349a: f003 0302 and.w r3, r3, #2
|
|
800349e: 2b00 cmp r3, #0
|
|
80034a0: d101 bne.n 80034a6 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
80034a2: 2301 movs r3, #1
|
|
80034a4: e067 b.n 8003576 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
80034a6: 4b37 ldr r3, [pc, #220] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80034a8: 689b ldr r3, [r3, #8]
|
|
80034aa: f023 0203 bic.w r2, r3, #3
|
|
80034ae: 687b ldr r3, [r7, #4]
|
|
80034b0: 685b ldr r3, [r3, #4]
|
|
80034b2: 4934 ldr r1, [pc, #208] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80034b4: 4313 orrs r3, r2
|
|
80034b6: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80034b8: f7fe f82e bl 8001518 <HAL_GetTick>
|
|
80034bc: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80034be: e00a b.n 80034d6 <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80034c0: f7fe f82a bl 8001518 <HAL_GetTick>
|
|
80034c4: 4602 mov r2, r0
|
|
80034c6: 68fb ldr r3, [r7, #12]
|
|
80034c8: 1ad3 subs r3, r2, r3
|
|
80034ca: f241 3288 movw r2, #5000 @ 0x1388
|
|
80034ce: 4293 cmp r3, r2
|
|
80034d0: d901 bls.n 80034d6 <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80034d2: 2303 movs r3, #3
|
|
80034d4: e04f b.n 8003576 <HAL_RCC_ClockConfig+0x1ae>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80034d6: 4b2b ldr r3, [pc, #172] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80034d8: 689b ldr r3, [r3, #8]
|
|
80034da: f003 020c and.w r2, r3, #12
|
|
80034de: 687b ldr r3, [r7, #4]
|
|
80034e0: 685b ldr r3, [r3, #4]
|
|
80034e2: 009b lsls r3, r3, #2
|
|
80034e4: 429a cmp r2, r3
|
|
80034e6: d1eb bne.n 80034c0 <HAL_RCC_ClockConfig+0xf8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
80034e8: 4b25 ldr r3, [pc, #148] @ (8003580 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80034ea: 681b ldr r3, [r3, #0]
|
|
80034ec: f003 030f and.w r3, r3, #15
|
|
80034f0: 683a ldr r2, [r7, #0]
|
|
80034f2: 429a cmp r2, r3
|
|
80034f4: d20c bcs.n 8003510 <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80034f6: 4b22 ldr r3, [pc, #136] @ (8003580 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80034f8: 683a ldr r2, [r7, #0]
|
|
80034fa: b2d2 uxtb r2, r2
|
|
80034fc: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80034fe: 4b20 ldr r3, [pc, #128] @ (8003580 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8003500: 681b ldr r3, [r3, #0]
|
|
8003502: f003 030f and.w r3, r3, #15
|
|
8003506: 683a ldr r2, [r7, #0]
|
|
8003508: 429a cmp r2, r3
|
|
800350a: d001 beq.n 8003510 <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
return HAL_ERROR;
|
|
800350c: 2301 movs r3, #1
|
|
800350e: e032 b.n 8003576 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8003510: 687b ldr r3, [r7, #4]
|
|
8003512: 681b ldr r3, [r3, #0]
|
|
8003514: f003 0304 and.w r3, r3, #4
|
|
8003518: 2b00 cmp r3, #0
|
|
800351a: d008 beq.n 800352e <HAL_RCC_ClockConfig+0x166>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
800351c: 4b19 ldr r3, [pc, #100] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800351e: 689b ldr r3, [r3, #8]
|
|
8003520: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
|
|
8003524: 687b ldr r3, [r7, #4]
|
|
8003526: 68db ldr r3, [r3, #12]
|
|
8003528: 4916 ldr r1, [pc, #88] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800352a: 4313 orrs r3, r2
|
|
800352c: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
800352e: 687b ldr r3, [r7, #4]
|
|
8003530: 681b ldr r3, [r3, #0]
|
|
8003532: f003 0308 and.w r3, r3, #8
|
|
8003536: 2b00 cmp r3, #0
|
|
8003538: d009 beq.n 800354e <HAL_RCC_ClockConfig+0x186>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
800353a: 4b12 ldr r3, [pc, #72] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800353c: 689b ldr r3, [r3, #8]
|
|
800353e: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
8003542: 687b ldr r3, [r7, #4]
|
|
8003544: 691b ldr r3, [r3, #16]
|
|
8003546: 00db lsls r3, r3, #3
|
|
8003548: 490e ldr r1, [pc, #56] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800354a: 4313 orrs r3, r2
|
|
800354c: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
800354e: f000 fb7f bl 8003c50 <HAL_RCC_GetSysClockFreq>
|
|
8003552: 4602 mov r2, r0
|
|
8003554: 4b0b ldr r3, [pc, #44] @ (8003584 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003556: 689b ldr r3, [r3, #8]
|
|
8003558: 091b lsrs r3, r3, #4
|
|
800355a: f003 030f and.w r3, r3, #15
|
|
800355e: 490a ldr r1, [pc, #40] @ (8003588 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8003560: 5ccb ldrb r3, [r1, r3]
|
|
8003562: fa22 f303 lsr.w r3, r2, r3
|
|
8003566: 4a09 ldr r2, [pc, #36] @ (800358c <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003568: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings */
|
|
HAL_InitTick(uwTickPrio);
|
|
800356a: 4b09 ldr r3, [pc, #36] @ (8003590 <HAL_RCC_ClockConfig+0x1c8>)
|
|
800356c: 681b ldr r3, [r3, #0]
|
|
800356e: 4618 mov r0, r3
|
|
8003570: f7fd ff8e bl 8001490 <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
8003574: 2300 movs r3, #0
|
|
}
|
|
8003576: 4618 mov r0, r3
|
|
8003578: 3710 adds r7, #16
|
|
800357a: 46bd mov sp, r7
|
|
800357c: bd80 pop {r7, pc}
|
|
800357e: bf00 nop
|
|
8003580: 40023c00 .word 0x40023c00
|
|
8003584: 40023800 .word 0x40023800
|
|
8003588: 08009640 .word 0x08009640
|
|
800358c: 20000028 .word 0x20000028
|
|
8003590: 2000002c .word 0x2000002c
|
|
|
|
08003594 <HAL_RCC_GetHCLKFreq>:
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8003594: b480 push {r7}
|
|
8003596: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
8003598: 4b03 ldr r3, [pc, #12] @ (80035a8 <HAL_RCC_GetHCLKFreq+0x14>)
|
|
800359a: 681b ldr r3, [r3, #0]
|
|
}
|
|
800359c: 4618 mov r0, r3
|
|
800359e: 46bd mov sp, r7
|
|
80035a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80035a4: 4770 bx lr
|
|
80035a6: bf00 nop
|
|
80035a8: 20000028 .word 0x20000028
|
|
|
|
080035ac <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
80035ac: b580 push {r7, lr}
|
|
80035ae: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
80035b0: f7ff fff0 bl 8003594 <HAL_RCC_GetHCLKFreq>
|
|
80035b4: 4602 mov r2, r0
|
|
80035b6: 4b05 ldr r3, [pc, #20] @ (80035cc <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
80035b8: 689b ldr r3, [r3, #8]
|
|
80035ba: 0a9b lsrs r3, r3, #10
|
|
80035bc: f003 0307 and.w r3, r3, #7
|
|
80035c0: 4903 ldr r1, [pc, #12] @ (80035d0 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
80035c2: 5ccb ldrb r3, [r1, r3]
|
|
80035c4: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80035c8: 4618 mov r0, r3
|
|
80035ca: bd80 pop {r7, pc}
|
|
80035cc: 40023800 .word 0x40023800
|
|
80035d0: 08009650 .word 0x08009650
|
|
|
|
080035d4 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
80035d4: b580 push {r7, lr}
|
|
80035d6: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
80035d8: f7ff ffdc bl 8003594 <HAL_RCC_GetHCLKFreq>
|
|
80035dc: 4602 mov r2, r0
|
|
80035de: 4b05 ldr r3, [pc, #20] @ (80035f4 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
80035e0: 689b ldr r3, [r3, #8]
|
|
80035e2: 0b5b lsrs r3, r3, #13
|
|
80035e4: f003 0307 and.w r3, r3, #7
|
|
80035e8: 4903 ldr r1, [pc, #12] @ (80035f8 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
80035ea: 5ccb ldrb r3, [r1, r3]
|
|
80035ec: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80035f0: 4618 mov r0, r3
|
|
80035f2: bd80 pop {r7, pc}
|
|
80035f4: 40023800 .word 0x40023800
|
|
80035f8: 08009650 .word 0x08009650
|
|
|
|
080035fc <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the backup registers) and RCC_BDCR register are set to their reset values.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
80035fc: b580 push {r7, lr}
|
|
80035fe: b08c sub sp, #48 @ 0x30
|
|
8003600: af00 add r7, sp, #0
|
|
8003602: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
8003604: 2300 movs r3, #0
|
|
8003606: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t tmpreg1 = 0U;
|
|
8003608: 2300 movs r3, #0
|
|
800360a: 623b str r3, [r7, #32]
|
|
uint32_t plli2sp = 0U;
|
|
800360c: 2300 movs r3, #0
|
|
800360e: 61fb str r3, [r7, #28]
|
|
uint32_t plli2sq = 0U;
|
|
8003610: 2300 movs r3, #0
|
|
8003612: 61bb str r3, [r7, #24]
|
|
uint32_t plli2sr = 0U;
|
|
8003614: 2300 movs r3, #0
|
|
8003616: 617b str r3, [r7, #20]
|
|
uint32_t pllsaip = 0U;
|
|
8003618: 2300 movs r3, #0
|
|
800361a: 613b str r3, [r7, #16]
|
|
uint32_t pllsaiq = 0U;
|
|
800361c: 2300 movs r3, #0
|
|
800361e: 60fb str r3, [r7, #12]
|
|
uint32_t plli2sused = 0U;
|
|
8003620: 2300 movs r3, #0
|
|
8003622: 62fb str r3, [r7, #44] @ 0x2c
|
|
uint32_t pllsaiused = 0U;
|
|
8003624: 2300 movs r3, #0
|
|
8003626: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Check the peripheral clock selection parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*------------------------ I2S APB1 configuration --------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
|
|
8003628: 687b ldr r3, [r7, #4]
|
|
800362a: 681b ldr r3, [r3, #0]
|
|
800362c: f003 0301 and.w r3, r3, #1
|
|
8003630: 2b00 cmp r3, #0
|
|
8003632: d010 beq.n 8003656 <HAL_RCCEx_PeriphCLKConfig+0x5a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
|
|
|
|
/* Configure I2S Clock source */
|
|
__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
|
|
8003634: 4b6f ldr r3, [pc, #444] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003636: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
800363a: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000
|
|
800363e: 687b ldr r3, [r7, #4]
|
|
8003640: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003642: 496c ldr r1, [pc, #432] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003644: 4313 orrs r3, r2
|
|
8003646: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for I2S */
|
|
if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
|
|
800364a: 687b ldr r3, [r7, #4]
|
|
800364c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800364e: 2b00 cmp r3, #0
|
|
8003650: d101 bne.n 8003656 <HAL_RCCEx_PeriphCLKConfig+0x5a>
|
|
{
|
|
plli2sused = 1U;
|
|
8003652: 2301 movs r3, #1
|
|
8003654: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- I2S APB2 configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
|
|
8003656: 687b ldr r3, [r7, #4]
|
|
8003658: 681b ldr r3, [r3, #0]
|
|
800365a: f003 0302 and.w r3, r3, #2
|
|
800365e: 2b00 cmp r3, #0
|
|
8003660: d010 beq.n 8003684 <HAL_RCCEx_PeriphCLKConfig+0x88>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
|
|
|
|
/* Configure I2S Clock source */
|
|
__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
|
|
8003662: 4b64 ldr r3, [pc, #400] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003664: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8003668: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000
|
|
800366c: 687b ldr r3, [r7, #4]
|
|
800366e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8003670: 4960 ldr r1, [pc, #384] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003672: 4313 orrs r3, r2
|
|
8003674: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for I2S */
|
|
if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
|
|
8003678: 687b ldr r3, [r7, #4]
|
|
800367a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800367c: 2b00 cmp r3, #0
|
|
800367e: d101 bne.n 8003684 <HAL_RCCEx_PeriphCLKConfig+0x88>
|
|
{
|
|
plli2sused = 1U;
|
|
8003680: 2301 movs r3, #1
|
|
8003682: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*--------------------------- SAI1 configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
|
|
8003684: 687b ldr r3, [r7, #4]
|
|
8003686: 681b ldr r3, [r3, #0]
|
|
8003688: f003 0304 and.w r3, r3, #4
|
|
800368c: 2b00 cmp r3, #0
|
|
800368e: d017 beq.n 80036c0 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
/* Configure SAI1 Clock source */
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
8003690: 4b58 ldr r3, [pc, #352] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003692: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8003696: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
800369a: 687b ldr r3, [r7, #4]
|
|
800369c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800369e: 4955 ldr r1, [pc, #340] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80036a0: 4313 orrs r3, r2
|
|
80036a2: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
|
|
80036a6: 687b ldr r3, [r7, #4]
|
|
80036a8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80036aa: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
80036ae: d101 bne.n 80036b4 <HAL_RCCEx_PeriphCLKConfig+0xb8>
|
|
{
|
|
plli2sused = 1U;
|
|
80036b0: 2301 movs r3, #1
|
|
80036b2: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
/* Enable the PLLSAI when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
|
|
80036b4: 687b ldr r3, [r7, #4]
|
|
80036b6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80036b8: 2b00 cmp r3, #0
|
|
80036ba: d101 bne.n 80036c0 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|
{
|
|
pllsaiused = 1U;
|
|
80036bc: 2301 movs r3, #1
|
|
80036be: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*-------------------------- SAI2 configuration ----------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
|
|
80036c0: 687b ldr r3, [r7, #4]
|
|
80036c2: 681b ldr r3, [r3, #0]
|
|
80036c4: f003 0308 and.w r3, r3, #8
|
|
80036c8: 2b00 cmp r3, #0
|
|
80036ca: d017 beq.n 80036fc <HAL_RCCEx_PeriphCLKConfig+0x100>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
|
|
|
|
/* Configure SAI2 Clock source */
|
|
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
|
|
80036cc: 4b49 ldr r3, [pc, #292] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80036ce: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80036d2: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
80036d6: 687b ldr r3, [r7, #4]
|
|
80036d8: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80036da: 4946 ldr r1, [pc, #280] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80036dc: 4313 orrs r3, r2
|
|
80036de: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
|
|
/* Enable the PLLI2S when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
|
|
80036e2: 687b ldr r3, [r7, #4]
|
|
80036e4: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80036e6: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80036ea: d101 bne.n 80036f0 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
{
|
|
plli2sused = 1U;
|
|
80036ec: 2301 movs r3, #1
|
|
80036ee: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
/* Enable the PLLSAI when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
|
|
80036f0: 687b ldr r3, [r7, #4]
|
|
80036f2: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80036f4: 2b00 cmp r3, #0
|
|
80036f6: d101 bne.n 80036fc <HAL_RCCEx_PeriphCLKConfig+0x100>
|
|
{
|
|
pllsaiused = 1U;
|
|
80036f8: 2301 movs r3, #1
|
|
80036fa: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- RTC configuration --------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
|
80036fc: 687b ldr r3, [r7, #4]
|
|
80036fe: 681b ldr r3, [r3, #0]
|
|
8003700: f003 0320 and.w r3, r3, #32
|
|
8003704: 2b00 cmp r3, #0
|
|
8003706: f000 808a beq.w 800381e <HAL_RCCEx_PeriphCLKConfig+0x222>
|
|
{
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800370a: 2300 movs r3, #0
|
|
800370c: 60bb str r3, [r7, #8]
|
|
800370e: 4b39 ldr r3, [pc, #228] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003710: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003712: 4a38 ldr r2, [pc, #224] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003714: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8003718: 6413 str r3, [r2, #64] @ 0x40
|
|
800371a: 4b36 ldr r3, [pc, #216] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800371c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800371e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003722: 60bb str r3, [r7, #8]
|
|
8003724: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Enable write access to Backup domain */
|
|
PWR->CR |= PWR_CR_DBP;
|
|
8003726: 4b34 ldr r3, [pc, #208] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
8003728: 681b ldr r3, [r3, #0]
|
|
800372a: 4a33 ldr r2, [pc, #204] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
800372c: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8003730: 6013 str r3, [r2, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003732: f7fd fef1 bl 8001518 <HAL_GetTick>
|
|
8003736: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
8003738: e008 b.n 800374c <HAL_RCCEx_PeriphCLKConfig+0x150>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
800373a: f7fd feed bl 8001518 <HAL_GetTick>
|
|
800373e: 4602 mov r2, r0
|
|
8003740: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003742: 1ad3 subs r3, r2, r3
|
|
8003744: 2b02 cmp r3, #2
|
|
8003746: d901 bls.n 800374c <HAL_RCCEx_PeriphCLKConfig+0x150>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003748: 2303 movs r3, #3
|
|
800374a: e278 b.n 8003c3e <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
800374c: 4b2a ldr r3, [pc, #168] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
800374e: 681b ldr r3, [r3, #0]
|
|
8003750: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003754: 2b00 cmp r3, #0
|
|
8003756: d0f0 beq.n 800373a <HAL_RCCEx_PeriphCLKConfig+0x13e>
|
|
}
|
|
}
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
8003758: 4b26 ldr r3, [pc, #152] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800375a: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800375c: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8003760: 623b str r3, [r7, #32]
|
|
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
8003762: 6a3b ldr r3, [r7, #32]
|
|
8003764: 2b00 cmp r3, #0
|
|
8003766: d02f beq.n 80037c8 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
8003768: 687b ldr r3, [r7, #4]
|
|
800376a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800376c: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8003770: 6a3a ldr r2, [r7, #32]
|
|
8003772: 429a cmp r2, r3
|
|
8003774: d028 beq.n 80037c8 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
8003776: 4b1f ldr r3, [pc, #124] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003778: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800377a: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800377e: 623b str r3, [r7, #32]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8003780: 4b1e ldr r3, [pc, #120] @ (80037fc <HAL_RCCEx_PeriphCLKConfig+0x200>)
|
|
8003782: 2201 movs r2, #1
|
|
8003784: 601a str r2, [r3, #0]
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8003786: 4b1d ldr r3, [pc, #116] @ (80037fc <HAL_RCCEx_PeriphCLKConfig+0x200>)
|
|
8003788: 2200 movs r2, #0
|
|
800378a: 601a str r2, [r3, #0]
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpreg1;
|
|
800378c: 4a19 ldr r2, [pc, #100] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800378e: 6a3b ldr r3, [r7, #32]
|
|
8003790: 6713 str r3, [r2, #112] @ 0x70
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
|
|
8003792: 4b18 ldr r3, [pc, #96] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003794: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003796: f003 0301 and.w r3, r3, #1
|
|
800379a: 2b01 cmp r3, #1
|
|
800379c: d114 bne.n 80037c8 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800379e: f7fd febb bl 8001518 <HAL_GetTick>
|
|
80037a2: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
80037a4: e00a b.n 80037bc <HAL_RCCEx_PeriphCLKConfig+0x1c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
80037a6: f7fd feb7 bl 8001518 <HAL_GetTick>
|
|
80037aa: 4602 mov r2, r0
|
|
80037ac: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80037ae: 1ad3 subs r3, r2, r3
|
|
80037b0: f241 3288 movw r2, #5000 @ 0x1388
|
|
80037b4: 4293 cmp r3, r2
|
|
80037b6: d901 bls.n 80037bc <HAL_RCCEx_PeriphCLKConfig+0x1c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80037b8: 2303 movs r3, #3
|
|
80037ba: e240 b.n 8003c3e <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
80037bc: 4b0d ldr r3, [pc, #52] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80037be: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80037c0: f003 0302 and.w r3, r3, #2
|
|
80037c4: 2b00 cmp r3, #0
|
|
80037c6: d0ee beq.n 80037a6 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
80037c8: 687b ldr r3, [r7, #4]
|
|
80037ca: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80037cc: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80037d0: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
80037d4: d114 bne.n 8003800 <HAL_RCCEx_PeriphCLKConfig+0x204>
|
|
80037d6: 4b07 ldr r3, [pc, #28] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80037d8: 689b ldr r3, [r3, #8]
|
|
80037da: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
|
|
80037de: 687b ldr r3, [r7, #4]
|
|
80037e0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80037e2: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000
|
|
80037e6: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80037ea: 4902 ldr r1, [pc, #8] @ (80037f4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80037ec: 4313 orrs r3, r2
|
|
80037ee: 608b str r3, [r1, #8]
|
|
80037f0: e00c b.n 800380c <HAL_RCCEx_PeriphCLKConfig+0x210>
|
|
80037f2: bf00 nop
|
|
80037f4: 40023800 .word 0x40023800
|
|
80037f8: 40007000 .word 0x40007000
|
|
80037fc: 42470e40 .word 0x42470e40
|
|
8003800: 4b4a ldr r3, [pc, #296] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003802: 689b ldr r3, [r3, #8]
|
|
8003804: 4a49 ldr r2, [pc, #292] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003806: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
|
|
800380a: 6093 str r3, [r2, #8]
|
|
800380c: 4b47 ldr r3, [pc, #284] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
800380e: 6f1a ldr r2, [r3, #112] @ 0x70
|
|
8003810: 687b ldr r3, [r7, #4]
|
|
8003812: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003814: f3c3 030b ubfx r3, r3, #0, #12
|
|
8003818: 4944 ldr r1, [pc, #272] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
800381a: 4313 orrs r3, r2
|
|
800381c: 670b str r3, [r1, #112] @ 0x70
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- TIM configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
|
|
800381e: 687b ldr r3, [r7, #4]
|
|
8003820: 681b ldr r3, [r3, #0]
|
|
8003822: f003 0310 and.w r3, r3, #16
|
|
8003826: 2b00 cmp r3, #0
|
|
8003828: d004 beq.n 8003834 <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
{
|
|
/* Configure Timer Prescaler */
|
|
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
|
|
800382a: 687b ldr r3, [r7, #4]
|
|
800382c: f893 2058 ldrb.w r2, [r3, #88] @ 0x58
|
|
8003830: 4b3f ldr r3, [pc, #252] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x334>)
|
|
8003832: 601a str r2, [r3, #0]
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- FMPI2C1 Configuration -----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
|
|
8003834: 687b ldr r3, [r7, #4]
|
|
8003836: 681b ldr r3, [r3, #0]
|
|
8003838: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800383c: 2b00 cmp r3, #0
|
|
800383e: d00a beq.n 8003856 <HAL_RCCEx_PeriphCLKConfig+0x25a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
|
|
|
|
/* Configure the FMPI2C1 clock source */
|
|
__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
|
|
8003840: 4b3a ldr r3, [pc, #232] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003842: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003846: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
800384a: 687b ldr r3, [r7, #4]
|
|
800384c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800384e: 4937 ldr r1, [pc, #220] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003850: 4313 orrs r3, r2
|
|
8003852: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*------------------------------ CEC Configuration -------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
|
|
8003856: 687b ldr r3, [r7, #4]
|
|
8003858: 681b ldr r3, [r3, #0]
|
|
800385a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800385e: 2b00 cmp r3, #0
|
|
8003860: d00a beq.n 8003878 <HAL_RCCEx_PeriphCLKConfig+0x27c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
|
|
|
|
/* Configure the CEC clock source */
|
|
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
|
|
8003862: 4b32 ldr r3, [pc, #200] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003864: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003868: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000
|
|
800386c: 687b ldr r3, [r7, #4]
|
|
800386e: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8003870: 492e ldr r1, [pc, #184] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003872: 4313 orrs r3, r2
|
|
8003874: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- CLK48 Configuration ------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
|
|
8003878: 687b ldr r3, [r7, #4]
|
|
800387a: 681b ldr r3, [r3, #0]
|
|
800387c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003880: 2b00 cmp r3, #0
|
|
8003882: d011 beq.n 80038a8 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
|
|
|
|
/* Configure the CLK48 clock source */
|
|
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
|
|
8003884: 4b29 ldr r3, [pc, #164] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003886: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800388a: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000
|
|
800388e: 687b ldr r3, [r7, #4]
|
|
8003890: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8003892: 4926 ldr r1, [pc, #152] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003894: 4313 orrs r3, r2
|
|
8003896: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
|
|
/* Enable the PLLSAI when it's used as clock source for CLK48 */
|
|
if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
|
|
800389a: 687b ldr r3, [r7, #4]
|
|
800389c: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800389e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
80038a2: d101 bne.n 80038a8 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
pllsaiused = 1U;
|
|
80038a4: 2301 movs r3, #1
|
|
80038a6: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- SDIO Configuration -------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
|
|
80038a8: 687b ldr r3, [r7, #4]
|
|
80038aa: 681b ldr r3, [r3, #0]
|
|
80038ac: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80038b0: 2b00 cmp r3, #0
|
|
80038b2: d00a beq.n 80038ca <HAL_RCCEx_PeriphCLKConfig+0x2ce>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
|
|
|
|
/* Configure the SDIO clock source */
|
|
__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
|
|
80038b4: 4b1d ldr r3, [pc, #116] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80038b6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
80038ba: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
|
|
80038be: 687b ldr r3, [r7, #4]
|
|
80038c0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80038c2: 491a ldr r1, [pc, #104] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80038c4: 4313 orrs r3, r2
|
|
80038c6: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*------------------------------ SPDIFRX Configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
|
80038ca: 687b ldr r3, [r7, #4]
|
|
80038cc: 681b ldr r3, [r3, #0]
|
|
80038ce: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80038d2: 2b00 cmp r3, #0
|
|
80038d4: d011 beq.n 80038fa <HAL_RCCEx_PeriphCLKConfig+0x2fe>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
|
|
|
|
/* Configure the SPDIFRX clock source */
|
|
__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
|
|
80038d6: 4b15 ldr r3, [pc, #84] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80038d8: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
80038dc: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
|
|
80038e0: 687b ldr r3, [r7, #4]
|
|
80038e2: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80038e4: 4911 ldr r1, [pc, #68] @ (800392c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80038e6: 4313 orrs r3, r2
|
|
80038e8: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
|
|
if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
|
|
80038ec: 687b ldr r3, [r7, #4]
|
|
80038ee: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80038f0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
80038f4: d101 bne.n 80038fa <HAL_RCCEx_PeriphCLKConfig+0x2fe>
|
|
{
|
|
plli2sused = 1U;
|
|
80038f6: 2301 movs r3, #1
|
|
80038f8: 62fb str r3, [r7, #44] @ 0x2c
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- PLLI2S Configuration ------------------------*/
|
|
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
|
|
I2S on APB2 or SPDIFRX */
|
|
if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
|
|
80038fa: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80038fc: 2b01 cmp r3, #1
|
|
80038fe: d005 beq.n 800390c <HAL_RCCEx_PeriphCLKConfig+0x310>
|
|
8003900: 687b ldr r3, [r7, #4]
|
|
8003902: 681b ldr r3, [r3, #0]
|
|
8003904: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8003908: f040 80ff bne.w 8003b0a <HAL_RCCEx_PeriphCLKConfig+0x50e>
|
|
{
|
|
/* Disable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_DISABLE();
|
|
800390c: 4b09 ldr r3, [pc, #36] @ (8003934 <HAL_RCCEx_PeriphCLKConfig+0x338>)
|
|
800390e: 2200 movs r2, #0
|
|
8003910: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003912: f7fd fe01 bl 8001518 <HAL_GetTick>
|
|
8003916: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLI2S is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
8003918: e00e b.n 8003938 <HAL_RCCEx_PeriphCLKConfig+0x33c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
800391a: f7fd fdfd bl 8001518 <HAL_GetTick>
|
|
800391e: 4602 mov r2, r0
|
|
8003920: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003922: 1ad3 subs r3, r2, r3
|
|
8003924: 2b02 cmp r3, #2
|
|
8003926: d907 bls.n 8003938 <HAL_RCCEx_PeriphCLKConfig+0x33c>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8003928: 2303 movs r3, #3
|
|
800392a: e188 b.n 8003c3e <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
800392c: 40023800 .word 0x40023800
|
|
8003930: 424711e0 .word 0x424711e0
|
|
8003934: 42470068 .word 0x42470068
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
8003938: 4b7e ldr r3, [pc, #504] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800393a: 681b ldr r3, [r3, #0]
|
|
800393c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8003940: 2b00 cmp r3, #0
|
|
8003942: d1ea bne.n 800391a <HAL_RCCEx_PeriphCLKConfig+0x31e>
|
|
/* check for common PLLI2S Parameters */
|
|
assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
|
|
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
|
|
|
/*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1)
|
|
8003944: 687b ldr r3, [r7, #4]
|
|
8003946: 681b ldr r3, [r3, #0]
|
|
8003948: f003 0301 and.w r3, r3, #1
|
|
800394c: 2b00 cmp r3, #0
|
|
800394e: d003 beq.n 8003958 <HAL_RCCEx_PeriphCLKConfig+0x35c>
|
|
&& (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
|
|
8003950: 687b ldr r3, [r7, #4]
|
|
8003952: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003954: 2b00 cmp r3, #0
|
|
8003956: d009 beq.n 800396c <HAL_RCCEx_PeriphCLKConfig+0x370>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
|
|
8003958: 687b ldr r3, [r7, #4]
|
|
800395a: 681b ldr r3, [r3, #0]
|
|
800395c: f003 0302 and.w r3, r3, #2
|
|
&& (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
|
|
8003960: 2b00 cmp r3, #0
|
|
8003962: d028 beq.n 80039b6 <HAL_RCCEx_PeriphCLKConfig+0x3ba>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
|
|
8003964: 687b ldr r3, [r7, #4]
|
|
8003966: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8003968: 2b00 cmp r3, #0
|
|
800396a: d124 bne.n 80039b6 <HAL_RCCEx_PeriphCLKConfig+0x3ba>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
|
|
/* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
|
|
plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
800396c: 4b71 ldr r3, [pc, #452] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800396e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003972: 0c1b lsrs r3, r3, #16
|
|
8003974: f003 0303 and.w r3, r3, #3
|
|
8003978: 3301 adds r3, #1
|
|
800397a: 005b lsls r3, r3, #1
|
|
800397c: 61fb str r3, [r7, #28]
|
|
plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
|
|
800397e: 4b6d ldr r3, [pc, #436] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003980: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003984: 0e1b lsrs r3, r3, #24
|
|
8003986: f003 030f and.w r3, r3, #15
|
|
800398a: 61bb str r3, [r7, #24]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq,
|
|
800398c: 687b ldr r3, [r7, #4]
|
|
800398e: 685a ldr r2, [r3, #4]
|
|
8003990: 687b ldr r3, [r7, #4]
|
|
8003992: 689b ldr r3, [r3, #8]
|
|
8003994: 019b lsls r3, r3, #6
|
|
8003996: 431a orrs r2, r3
|
|
8003998: 69fb ldr r3, [r7, #28]
|
|
800399a: 085b lsrs r3, r3, #1
|
|
800399c: 3b01 subs r3, #1
|
|
800399e: 041b lsls r3, r3, #16
|
|
80039a0: 431a orrs r2, r3
|
|
80039a2: 69bb ldr r3, [r7, #24]
|
|
80039a4: 061b lsls r3, r3, #24
|
|
80039a6: 431a orrs r2, r3
|
|
80039a8: 687b ldr r3, [r7, #4]
|
|
80039aa: 695b ldr r3, [r3, #20]
|
|
80039ac: 071b lsls r3, r3, #28
|
|
80039ae: 4961 ldr r1, [pc, #388] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80039b0: 4313 orrs r3, r2
|
|
80039b2: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SR);
|
|
}
|
|
|
|
/*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
|
|
80039b6: 687b ldr r3, [r7, #4]
|
|
80039b8: 681b ldr r3, [r3, #0]
|
|
80039ba: f003 0304 and.w r3, r3, #4
|
|
80039be: 2b00 cmp r3, #0
|
|
80039c0: d004 beq.n 80039cc <HAL_RCCEx_PeriphCLKConfig+0x3d0>
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
|
80039c2: 687b ldr r3, [r7, #4]
|
|
80039c4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80039c6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
80039ca: d00a beq.n 80039e2 <HAL_RCCEx_PeriphCLKConfig+0x3e6>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
|
80039cc: 687b ldr r3, [r7, #4]
|
|
80039ce: 681b ldr r3, [r3, #0]
|
|
80039d0: f003 0308 and.w r3, r3, #8
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
|
80039d4: 2b00 cmp r3, #0
|
|
80039d6: d035 beq.n 8003a44 <HAL_RCCEx_PeriphCLKConfig+0x448>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
|
80039d8: 687b ldr r3, [r7, #4]
|
|
80039da: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80039dc: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80039e0: d130 bne.n 8003a44 <HAL_RCCEx_PeriphCLKConfig+0x448>
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
/* Check for PLLI2S/DIVQ parameters */
|
|
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
|
|
|
|
/* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
|
|
plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
80039e2: 4b54 ldr r3, [pc, #336] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80039e4: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80039e8: 0c1b lsrs r3, r3, #16
|
|
80039ea: f003 0303 and.w r3, r3, #3
|
|
80039ee: 3301 adds r3, #1
|
|
80039f0: 005b lsls r3, r3, #1
|
|
80039f2: 61fb str r3, [r7, #28]
|
|
plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
80039f4: 4b4f ldr r3, [pc, #316] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80039f6: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80039fa: 0f1b lsrs r3, r3, #28
|
|
80039fc: f003 0307 and.w r3, r3, #7
|
|
8003a00: 617b str r3, [r7, #20]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
|
|
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
|
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp,
|
|
8003a02: 687b ldr r3, [r7, #4]
|
|
8003a04: 685a ldr r2, [r3, #4]
|
|
8003a06: 687b ldr r3, [r7, #4]
|
|
8003a08: 689b ldr r3, [r3, #8]
|
|
8003a0a: 019b lsls r3, r3, #6
|
|
8003a0c: 431a orrs r2, r3
|
|
8003a0e: 69fb ldr r3, [r7, #28]
|
|
8003a10: 085b lsrs r3, r3, #1
|
|
8003a12: 3b01 subs r3, #1
|
|
8003a14: 041b lsls r3, r3, #16
|
|
8003a16: 431a orrs r2, r3
|
|
8003a18: 687b ldr r3, [r7, #4]
|
|
8003a1a: 691b ldr r3, [r3, #16]
|
|
8003a1c: 061b lsls r3, r3, #24
|
|
8003a1e: 431a orrs r2, r3
|
|
8003a20: 697b ldr r3, [r7, #20]
|
|
8003a22: 071b lsls r3, r3, #28
|
|
8003a24: 4943 ldr r1, [pc, #268] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003a26: 4313 orrs r3, r2
|
|
8003a28: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
|
|
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
|
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
|
|
8003a2c: 4b41 ldr r3, [pc, #260] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003a2e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8003a32: f023 021f bic.w r2, r3, #31
|
|
8003a36: 687b ldr r3, [r7, #4]
|
|
8003a38: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003a3a: 3b01 subs r3, #1
|
|
8003a3c: 493d ldr r1, [pc, #244] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003a3e: 4313 orrs r3, r2
|
|
8003a40: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
|
8003a44: 687b ldr r3, [r7, #4]
|
|
8003a46: 681b ldr r3, [r3, #0]
|
|
8003a48: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003a4c: 2b00 cmp r3, #0
|
|
8003a4e: d029 beq.n 8003aa4 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
|
|
&& (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
|
|
8003a50: 687b ldr r3, [r7, #4]
|
|
8003a52: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8003a54: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8003a58: d124 bne.n 8003aa4 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
|
|
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
|
plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
8003a5a: 4b36 ldr r3, [pc, #216] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003a5c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003a60: 0c1b lsrs r3, r3, #16
|
|
8003a62: f003 0303 and.w r3, r3, #3
|
|
8003a66: 3301 adds r3, #1
|
|
8003a68: 005b lsls r3, r3, #1
|
|
8003a6a: 61bb str r3, [r7, #24]
|
|
plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
8003a6c: 4b31 ldr r3, [pc, #196] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003a6e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003a72: 0f1b lsrs r3, r3, #28
|
|
8003a74: f003 0307 and.w r3, r3, #7
|
|
8003a78: 617b str r3, [r7, #20]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP,
|
|
8003a7a: 687b ldr r3, [r7, #4]
|
|
8003a7c: 685a ldr r2, [r3, #4]
|
|
8003a7e: 687b ldr r3, [r7, #4]
|
|
8003a80: 689b ldr r3, [r3, #8]
|
|
8003a82: 019b lsls r3, r3, #6
|
|
8003a84: 431a orrs r2, r3
|
|
8003a86: 687b ldr r3, [r7, #4]
|
|
8003a88: 68db ldr r3, [r3, #12]
|
|
8003a8a: 085b lsrs r3, r3, #1
|
|
8003a8c: 3b01 subs r3, #1
|
|
8003a8e: 041b lsls r3, r3, #16
|
|
8003a90: 431a orrs r2, r3
|
|
8003a92: 69bb ldr r3, [r7, #24]
|
|
8003a94: 061b lsls r3, r3, #24
|
|
8003a96: 431a orrs r2, r3
|
|
8003a98: 697b ldr r3, [r7, #20]
|
|
8003a9a: 071b lsls r3, r3, #28
|
|
8003a9c: 4925 ldr r1, [pc, #148] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003a9e: 4313 orrs r3, r2
|
|
8003aa0: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
plli2sq, plli2sr);
|
|
}
|
|
|
|
/*----------------- In Case of PLLI2S is just selected -----------------*/
|
|
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
|
|
8003aa4: 687b ldr r3, [r7, #4]
|
|
8003aa6: 681b ldr r3, [r3, #0]
|
|
8003aa8: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8003aac: 2b00 cmp r3, #0
|
|
8003aae: d016 beq.n 8003ade <HAL_RCCEx_PeriphCLKConfig+0x4e2>
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP,
|
|
8003ab0: 687b ldr r3, [r7, #4]
|
|
8003ab2: 685a ldr r2, [r3, #4]
|
|
8003ab4: 687b ldr r3, [r7, #4]
|
|
8003ab6: 689b ldr r3, [r3, #8]
|
|
8003ab8: 019b lsls r3, r3, #6
|
|
8003aba: 431a orrs r2, r3
|
|
8003abc: 687b ldr r3, [r7, #4]
|
|
8003abe: 68db ldr r3, [r3, #12]
|
|
8003ac0: 085b lsrs r3, r3, #1
|
|
8003ac2: 3b01 subs r3, #1
|
|
8003ac4: 041b lsls r3, r3, #16
|
|
8003ac6: 431a orrs r2, r3
|
|
8003ac8: 687b ldr r3, [r7, #4]
|
|
8003aca: 691b ldr r3, [r3, #16]
|
|
8003acc: 061b lsls r3, r3, #24
|
|
8003ace: 431a orrs r2, r3
|
|
8003ad0: 687b ldr r3, [r7, #4]
|
|
8003ad2: 695b ldr r3, [r3, #20]
|
|
8003ad4: 071b lsls r3, r3, #28
|
|
8003ad6: 4917 ldr r1, [pc, #92] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003ad8: 4313 orrs r3, r2
|
|
8003ada: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
|
|
}
|
|
|
|
/* Enable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_ENABLE();
|
|
8003ade: 4b16 ldr r3, [pc, #88] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x53c>)
|
|
8003ae0: 2201 movs r2, #1
|
|
8003ae2: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003ae4: f7fd fd18 bl 8001518 <HAL_GetTick>
|
|
8003ae8: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLI2S is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
8003aea: e008 b.n 8003afe <HAL_RCCEx_PeriphCLKConfig+0x502>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
8003aec: f7fd fd14 bl 8001518 <HAL_GetTick>
|
|
8003af0: 4602 mov r2, r0
|
|
8003af2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003af4: 1ad3 subs r3, r2, r3
|
|
8003af6: 2b02 cmp r3, #2
|
|
8003af8: d901 bls.n 8003afe <HAL_RCCEx_PeriphCLKConfig+0x502>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8003afa: 2303 movs r3, #3
|
|
8003afc: e09f b.n 8003c3e <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
8003afe: 4b0d ldr r3, [pc, #52] @ (8003b34 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003b00: 681b ldr r3, [r3, #0]
|
|
8003b02: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8003b06: 2b00 cmp r3, #0
|
|
8003b08: d0f0 beq.n 8003aec <HAL_RCCEx_PeriphCLKConfig+0x4f0>
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- PLLSAI Configuration -----------------------*/
|
|
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
|
|
if (pllsaiused == 1U)
|
|
8003b0a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003b0c: 2b01 cmp r3, #1
|
|
8003b0e: f040 8095 bne.w 8003c3c <HAL_RCCEx_PeriphCLKConfig+0x640>
|
|
{
|
|
/* Disable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_DISABLE();
|
|
8003b12: 4b0a ldr r3, [pc, #40] @ (8003b3c <HAL_RCCEx_PeriphCLKConfig+0x540>)
|
|
8003b14: 2200 movs r2, #0
|
|
8003b16: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003b18: f7fd fcfe bl 8001518 <HAL_GetTick>
|
|
8003b1c: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLSAI is disabled */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
8003b1e: e00f b.n 8003b40 <HAL_RCCEx_PeriphCLKConfig+0x544>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
8003b20: f7fd fcfa bl 8001518 <HAL_GetTick>
|
|
8003b24: 4602 mov r2, r0
|
|
8003b26: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003b28: 1ad3 subs r3, r2, r3
|
|
8003b2a: 2b02 cmp r3, #2
|
|
8003b2c: d908 bls.n 8003b40 <HAL_RCCEx_PeriphCLKConfig+0x544>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8003b2e: 2303 movs r3, #3
|
|
8003b30: e085 b.n 8003c3e <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
8003b32: bf00 nop
|
|
8003b34: 40023800 .word 0x40023800
|
|
8003b38: 42470068 .word 0x42470068
|
|
8003b3c: 42470070 .word 0x42470070
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
8003b40: 4b41 ldr r3, [pc, #260] @ (8003c48 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003b42: 681b ldr r3, [r3, #0]
|
|
8003b44: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8003b48: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8003b4c: d0e8 beq.n 8003b20 <HAL_RCCEx_PeriphCLKConfig+0x524>
|
|
/* Check the PLLSAI division factors */
|
|
assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
|
|
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
|
|
|
|
/*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
|
|
8003b4e: 687b ldr r3, [r7, #4]
|
|
8003b50: 681b ldr r3, [r3, #0]
|
|
8003b52: f003 0304 and.w r3, r3, #4
|
|
8003b56: 2b00 cmp r3, #0
|
|
8003b58: d003 beq.n 8003b62 <HAL_RCCEx_PeriphCLKConfig+0x566>
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
|
|
8003b5a: 687b ldr r3, [r7, #4]
|
|
8003b5c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8003b5e: 2b00 cmp r3, #0
|
|
8003b60: d009 beq.n 8003b76 <HAL_RCCEx_PeriphCLKConfig+0x57a>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
|
8003b62: 687b ldr r3, [r7, #4]
|
|
8003b64: 681b ldr r3, [r3, #0]
|
|
8003b66: f003 0308 and.w r3, r3, #8
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
|
|
8003b6a: 2b00 cmp r3, #0
|
|
8003b6c: d02b beq.n 8003bc6 <HAL_RCCEx_PeriphCLKConfig+0x5ca>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
|
8003b6e: 687b ldr r3, [r7, #4]
|
|
8003b70: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8003b72: 2b00 cmp r3, #0
|
|
8003b74: d127 bne.n 8003bc6 <HAL_RCCEx_PeriphCLKConfig+0x5ca>
|
|
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
|
|
/* check for PLLSAI/DIVQ Parameter */
|
|
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
|
|
|
|
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
|
|
pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
|
|
8003b76: 4b34 ldr r3, [pc, #208] @ (8003c48 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003b78: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003b7c: 0c1b lsrs r3, r3, #16
|
|
8003b7e: f003 0303 and.w r3, r3, #3
|
|
8003b82: 3301 adds r3, #1
|
|
8003b84: 005b lsls r3, r3, #1
|
|
8003b86: 613b str r3, [r7, #16]
|
|
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
|
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip,
|
|
8003b88: 687b ldr r3, [r7, #4]
|
|
8003b8a: 699a ldr r2, [r3, #24]
|
|
8003b8c: 687b ldr r3, [r7, #4]
|
|
8003b8e: 69db ldr r3, [r3, #28]
|
|
8003b90: 019b lsls r3, r3, #6
|
|
8003b92: 431a orrs r2, r3
|
|
8003b94: 693b ldr r3, [r7, #16]
|
|
8003b96: 085b lsrs r3, r3, #1
|
|
8003b98: 3b01 subs r3, #1
|
|
8003b9a: 041b lsls r3, r3, #16
|
|
8003b9c: 431a orrs r2, r3
|
|
8003b9e: 687b ldr r3, [r7, #4]
|
|
8003ba0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003ba2: 061b lsls r3, r3, #24
|
|
8003ba4: 4928 ldr r1, [pc, #160] @ (8003c48 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003ba6: 4313 orrs r3, r2
|
|
8003ba8: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
|
|
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
|
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
|
|
8003bac: 4b26 ldr r3, [pc, #152] @ (8003c48 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003bae: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8003bb2: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
|
|
8003bb6: 687b ldr r3, [r7, #4]
|
|
8003bb8: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8003bba: 3b01 subs r3, #1
|
|
8003bbc: 021b lsls r3, r3, #8
|
|
8003bbe: 4922 ldr r1, [pc, #136] @ (8003c48 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003bc0: 4313 orrs r3, r2
|
|
8003bc2: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/
|
|
/* In Case of PLLI2S is selected as source clock for CLK48 */
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
|
|
8003bc6: 687b ldr r3, [r7, #4]
|
|
8003bc8: 681b ldr r3, [r3, #0]
|
|
8003bca: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003bce: 2b00 cmp r3, #0
|
|
8003bd0: d01d beq.n 8003c0e <HAL_RCCEx_PeriphCLKConfig+0x612>
|
|
&& (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
|
|
8003bd2: 687b ldr r3, [r7, #4]
|
|
8003bd4: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8003bd6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8003bda: d118 bne.n 8003c0e <HAL_RCCEx_PeriphCLKConfig+0x612>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
|
|
/* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
|
pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
|
|
8003bdc: 4b1a ldr r3, [pc, #104] @ (8003c48 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003bde: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003be2: 0e1b lsrs r3, r3, #24
|
|
8003be4: f003 030f and.w r3, r3, #15
|
|
8003be8: 60fb str r3, [r7, #12]
|
|
/* Configure the PLLSAI division factors */
|
|
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
|
|
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP,
|
|
8003bea: 687b ldr r3, [r7, #4]
|
|
8003bec: 699a ldr r2, [r3, #24]
|
|
8003bee: 687b ldr r3, [r7, #4]
|
|
8003bf0: 69db ldr r3, [r3, #28]
|
|
8003bf2: 019b lsls r3, r3, #6
|
|
8003bf4: 431a orrs r2, r3
|
|
8003bf6: 687b ldr r3, [r7, #4]
|
|
8003bf8: 6a1b ldr r3, [r3, #32]
|
|
8003bfa: 085b lsrs r3, r3, #1
|
|
8003bfc: 3b01 subs r3, #1
|
|
8003bfe: 041b lsls r3, r3, #16
|
|
8003c00: 431a orrs r2, r3
|
|
8003c02: 68fb ldr r3, [r7, #12]
|
|
8003c04: 061b lsls r3, r3, #24
|
|
8003c06: 4910 ldr r1, [pc, #64] @ (8003c48 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003c08: 4313 orrs r3, r2
|
|
8003c0a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
pllsaiq, 0U);
|
|
}
|
|
|
|
/* Enable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_ENABLE();
|
|
8003c0e: 4b0f ldr r3, [pc, #60] @ (8003c4c <HAL_RCCEx_PeriphCLKConfig+0x650>)
|
|
8003c10: 2201 movs r2, #1
|
|
8003c12: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003c14: f7fd fc80 bl 8001518 <HAL_GetTick>
|
|
8003c18: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLSAI is ready */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
8003c1a: e008 b.n 8003c2e <HAL_RCCEx_PeriphCLKConfig+0x632>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
8003c1c: f7fd fc7c bl 8001518 <HAL_GetTick>
|
|
8003c20: 4602 mov r2, r0
|
|
8003c22: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003c24: 1ad3 subs r3, r2, r3
|
|
8003c26: 2b02 cmp r3, #2
|
|
8003c28: d901 bls.n 8003c2e <HAL_RCCEx_PeriphCLKConfig+0x632>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8003c2a: 2303 movs r3, #3
|
|
8003c2c: e007 b.n 8003c3e <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
8003c2e: 4b06 ldr r3, [pc, #24] @ (8003c48 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003c30: 681b ldr r3, [r3, #0]
|
|
8003c32: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8003c36: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8003c3a: d1ef bne.n 8003c1c <HAL_RCCEx_PeriphCLKConfig+0x620>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8003c3c: 2300 movs r3, #0
|
|
}
|
|
8003c3e: 4618 mov r0, r3
|
|
8003c40: 3730 adds r7, #48 @ 0x30
|
|
8003c42: 46bd mov sp, r7
|
|
8003c44: bd80 pop {r7, pc}
|
|
8003c46: bf00 nop
|
|
8003c48: 40023800 .word 0x40023800
|
|
8003c4c: 42470070 .word 0x42470070
|
|
|
|
08003c50 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8003c50: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8003c54: b0ae sub sp, #184 @ 0xb8
|
|
8003c56: af00 add r7, sp, #0
|
|
uint32_t pllm = 0U;
|
|
8003c58: 2300 movs r3, #0
|
|
8003c5a: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
uint32_t pllvco = 0U;
|
|
8003c5e: 2300 movs r3, #0
|
|
8003c60: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
uint32_t pllp = 0U;
|
|
8003c64: 2300 movs r3, #0
|
|
8003c66: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
uint32_t pllr = 0U;
|
|
8003c6a: 2300 movs r3, #0
|
|
8003c6c: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
uint32_t sysclockfreq = 0U;
|
|
8003c70: 2300 movs r3, #0
|
|
8003c72: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
8003c76: 4bcb ldr r3, [pc, #812] @ (8003fa4 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003c78: 689b ldr r3, [r3, #8]
|
|
8003c7a: f003 030c and.w r3, r3, #12
|
|
8003c7e: 2b0c cmp r3, #12
|
|
8003c80: f200 8206 bhi.w 8004090 <HAL_RCC_GetSysClockFreq+0x440>
|
|
8003c84: a201 add r2, pc, #4 @ (adr r2, 8003c8c <HAL_RCC_GetSysClockFreq+0x3c>)
|
|
8003c86: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8003c8a: bf00 nop
|
|
8003c8c: 08003cc1 .word 0x08003cc1
|
|
8003c90: 08004091 .word 0x08004091
|
|
8003c94: 08004091 .word 0x08004091
|
|
8003c98: 08004091 .word 0x08004091
|
|
8003c9c: 08003cc9 .word 0x08003cc9
|
|
8003ca0: 08004091 .word 0x08004091
|
|
8003ca4: 08004091 .word 0x08004091
|
|
8003ca8: 08004091 .word 0x08004091
|
|
8003cac: 08003cd1 .word 0x08003cd1
|
|
8003cb0: 08004091 .word 0x08004091
|
|
8003cb4: 08004091 .word 0x08004091
|
|
8003cb8: 08004091 .word 0x08004091
|
|
8003cbc: 08003ec1 .word 0x08003ec1
|
|
{
|
|
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8003cc0: 4bb9 ldr r3, [pc, #740] @ (8003fa8 <HAL_RCC_GetSysClockFreq+0x358>)
|
|
8003cc2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8003cc6: e1e7 b.n 8004098 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8003cc8: 4bb8 ldr r3, [pc, #736] @ (8003fac <HAL_RCC_GetSysClockFreq+0x35c>)
|
|
8003cca: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8003cce: e1e3 b.n 8004098 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLP */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
8003cd0: 4bb4 ldr r3, [pc, #720] @ (8003fa4 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003cd2: 685b ldr r3, [r3, #4]
|
|
8003cd4: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
8003cd8: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
8003cdc: 4bb1 ldr r3, [pc, #708] @ (8003fa4 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003cde: 685b ldr r3, [r3, #4]
|
|
8003ce0: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8003ce4: 2b00 cmp r3, #0
|
|
8003ce6: d071 beq.n 8003dcc <HAL_RCC_GetSysClockFreq+0x17c>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8003ce8: 4bae ldr r3, [pc, #696] @ (8003fa4 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003cea: 685b ldr r3, [r3, #4]
|
|
8003cec: 099b lsrs r3, r3, #6
|
|
8003cee: 2200 movs r2, #0
|
|
8003cf0: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8003cf4: f8c7 209c str.w r2, [r7, #156] @ 0x9c
|
|
8003cf8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8003cfc: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8003d00: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8003d04: 2300 movs r3, #0
|
|
8003d06: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
8003d0a: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
|
|
8003d0e: 4622 mov r2, r4
|
|
8003d10: 462b mov r3, r5
|
|
8003d12: f04f 0000 mov.w r0, #0
|
|
8003d16: f04f 0100 mov.w r1, #0
|
|
8003d1a: 0159 lsls r1, r3, #5
|
|
8003d1c: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8003d20: 0150 lsls r0, r2, #5
|
|
8003d22: 4602 mov r2, r0
|
|
8003d24: 460b mov r3, r1
|
|
8003d26: 4621 mov r1, r4
|
|
8003d28: 1a51 subs r1, r2, r1
|
|
8003d2a: 6439 str r1, [r7, #64] @ 0x40
|
|
8003d2c: 4629 mov r1, r5
|
|
8003d2e: eb63 0301 sbc.w r3, r3, r1
|
|
8003d32: 647b str r3, [r7, #68] @ 0x44
|
|
8003d34: f04f 0200 mov.w r2, #0
|
|
8003d38: f04f 0300 mov.w r3, #0
|
|
8003d3c: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40
|
|
8003d40: 4649 mov r1, r9
|
|
8003d42: 018b lsls r3, r1, #6
|
|
8003d44: 4641 mov r1, r8
|
|
8003d46: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8003d4a: 4641 mov r1, r8
|
|
8003d4c: 018a lsls r2, r1, #6
|
|
8003d4e: 4641 mov r1, r8
|
|
8003d50: 1a51 subs r1, r2, r1
|
|
8003d52: 63b9 str r1, [r7, #56] @ 0x38
|
|
8003d54: 4649 mov r1, r9
|
|
8003d56: eb63 0301 sbc.w r3, r3, r1
|
|
8003d5a: 63fb str r3, [r7, #60] @ 0x3c
|
|
8003d5c: f04f 0200 mov.w r2, #0
|
|
8003d60: f04f 0300 mov.w r3, #0
|
|
8003d64: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38
|
|
8003d68: 4649 mov r1, r9
|
|
8003d6a: 00cb lsls r3, r1, #3
|
|
8003d6c: 4641 mov r1, r8
|
|
8003d6e: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8003d72: 4641 mov r1, r8
|
|
8003d74: 00ca lsls r2, r1, #3
|
|
8003d76: 4610 mov r0, r2
|
|
8003d78: 4619 mov r1, r3
|
|
8003d7a: 4603 mov r3, r0
|
|
8003d7c: 4622 mov r2, r4
|
|
8003d7e: 189b adds r3, r3, r2
|
|
8003d80: 633b str r3, [r7, #48] @ 0x30
|
|
8003d82: 462b mov r3, r5
|
|
8003d84: 460a mov r2, r1
|
|
8003d86: eb42 0303 adc.w r3, r2, r3
|
|
8003d8a: 637b str r3, [r7, #52] @ 0x34
|
|
8003d8c: f04f 0200 mov.w r2, #0
|
|
8003d90: f04f 0300 mov.w r3, #0
|
|
8003d94: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30
|
|
8003d98: 4629 mov r1, r5
|
|
8003d9a: 024b lsls r3, r1, #9
|
|
8003d9c: 4621 mov r1, r4
|
|
8003d9e: ea43 53d1 orr.w r3, r3, r1, lsr #23
|
|
8003da2: 4621 mov r1, r4
|
|
8003da4: 024a lsls r2, r1, #9
|
|
8003da6: 4610 mov r0, r2
|
|
8003da8: 4619 mov r1, r3
|
|
8003daa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8003dae: 2200 movs r2, #0
|
|
8003db0: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
8003db4: f8c7 208c str.w r2, [r7, #140] @ 0x8c
|
|
8003db8: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88
|
|
8003dbc: f7fc fa22 bl 8000204 <__aeabi_uldivmod>
|
|
8003dc0: 4602 mov r2, r0
|
|
8003dc2: 460b mov r3, r1
|
|
8003dc4: 4613 mov r3, r2
|
|
8003dc6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8003dca: e067 b.n 8003e9c <HAL_RCC_GetSysClockFreq+0x24c>
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8003dcc: 4b75 ldr r3, [pc, #468] @ (8003fa4 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003dce: 685b ldr r3, [r3, #4]
|
|
8003dd0: 099b lsrs r3, r3, #6
|
|
8003dd2: 2200 movs r2, #0
|
|
8003dd4: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8003dd8: f8c7 2084 str.w r2, [r7, #132] @ 0x84
|
|
8003ddc: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
8003de0: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8003de4: 67bb str r3, [r7, #120] @ 0x78
|
|
8003de6: 2300 movs r3, #0
|
|
8003de8: 67fb str r3, [r7, #124] @ 0x7c
|
|
8003dea: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78
|
|
8003dee: 4622 mov r2, r4
|
|
8003df0: 462b mov r3, r5
|
|
8003df2: f04f 0000 mov.w r0, #0
|
|
8003df6: f04f 0100 mov.w r1, #0
|
|
8003dfa: 0159 lsls r1, r3, #5
|
|
8003dfc: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8003e00: 0150 lsls r0, r2, #5
|
|
8003e02: 4602 mov r2, r0
|
|
8003e04: 460b mov r3, r1
|
|
8003e06: 4621 mov r1, r4
|
|
8003e08: 1a51 subs r1, r2, r1
|
|
8003e0a: 62b9 str r1, [r7, #40] @ 0x28
|
|
8003e0c: 4629 mov r1, r5
|
|
8003e0e: eb63 0301 sbc.w r3, r3, r1
|
|
8003e12: 62fb str r3, [r7, #44] @ 0x2c
|
|
8003e14: f04f 0200 mov.w r2, #0
|
|
8003e18: f04f 0300 mov.w r3, #0
|
|
8003e1c: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28
|
|
8003e20: 4649 mov r1, r9
|
|
8003e22: 018b lsls r3, r1, #6
|
|
8003e24: 4641 mov r1, r8
|
|
8003e26: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8003e2a: 4641 mov r1, r8
|
|
8003e2c: 018a lsls r2, r1, #6
|
|
8003e2e: 4641 mov r1, r8
|
|
8003e30: ebb2 0a01 subs.w sl, r2, r1
|
|
8003e34: 4649 mov r1, r9
|
|
8003e36: eb63 0b01 sbc.w fp, r3, r1
|
|
8003e3a: f04f 0200 mov.w r2, #0
|
|
8003e3e: f04f 0300 mov.w r3, #0
|
|
8003e42: ea4f 03cb mov.w r3, fp, lsl #3
|
|
8003e46: ea43 735a orr.w r3, r3, sl, lsr #29
|
|
8003e4a: ea4f 02ca mov.w r2, sl, lsl #3
|
|
8003e4e: 4692 mov sl, r2
|
|
8003e50: 469b mov fp, r3
|
|
8003e52: 4623 mov r3, r4
|
|
8003e54: eb1a 0303 adds.w r3, sl, r3
|
|
8003e58: 623b str r3, [r7, #32]
|
|
8003e5a: 462b mov r3, r5
|
|
8003e5c: eb4b 0303 adc.w r3, fp, r3
|
|
8003e60: 627b str r3, [r7, #36] @ 0x24
|
|
8003e62: f04f 0200 mov.w r2, #0
|
|
8003e66: f04f 0300 mov.w r3, #0
|
|
8003e6a: e9d7 4508 ldrd r4, r5, [r7, #32]
|
|
8003e6e: 4629 mov r1, r5
|
|
8003e70: 028b lsls r3, r1, #10
|
|
8003e72: 4621 mov r1, r4
|
|
8003e74: ea43 5391 orr.w r3, r3, r1, lsr #22
|
|
8003e78: 4621 mov r1, r4
|
|
8003e7a: 028a lsls r2, r1, #10
|
|
8003e7c: 4610 mov r0, r2
|
|
8003e7e: 4619 mov r1, r3
|
|
8003e80: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8003e84: 2200 movs r2, #0
|
|
8003e86: 673b str r3, [r7, #112] @ 0x70
|
|
8003e88: 677a str r2, [r7, #116] @ 0x74
|
|
8003e8a: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70
|
|
8003e8e: f7fc f9b9 bl 8000204 <__aeabi_uldivmod>
|
|
8003e92: 4602 mov r2, r0
|
|
8003e94: 460b mov r3, r1
|
|
8003e96: 4613 mov r3, r2
|
|
8003e98: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
}
|
|
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
|
|
8003e9c: 4b41 ldr r3, [pc, #260] @ (8003fa4 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003e9e: 685b ldr r3, [r3, #4]
|
|
8003ea0: 0c1b lsrs r3, r3, #16
|
|
8003ea2: f003 0303 and.w r3, r3, #3
|
|
8003ea6: 3301 adds r3, #1
|
|
8003ea8: 005b lsls r3, r3, #1
|
|
8003eaa: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
|
|
sysclockfreq = pllvco / pllp;
|
|
8003eae: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
8003eb2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8003eb6: fbb2 f3f3 udiv r3, r2, r3
|
|
8003eba: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8003ebe: e0eb b.n 8004098 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLR */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
8003ec0: 4b38 ldr r3, [pc, #224] @ (8003fa4 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003ec2: 685b ldr r3, [r3, #4]
|
|
8003ec4: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
8003ec8: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
8003ecc: 4b35 ldr r3, [pc, #212] @ (8003fa4 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003ece: 685b ldr r3, [r3, #4]
|
|
8003ed0: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8003ed4: 2b00 cmp r3, #0
|
|
8003ed6: d06b beq.n 8003fb0 <HAL_RCC_GetSysClockFreq+0x360>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8003ed8: 4b32 ldr r3, [pc, #200] @ (8003fa4 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003eda: 685b ldr r3, [r3, #4]
|
|
8003edc: 099b lsrs r3, r3, #6
|
|
8003ede: 2200 movs r2, #0
|
|
8003ee0: 66bb str r3, [r7, #104] @ 0x68
|
|
8003ee2: 66fa str r2, [r7, #108] @ 0x6c
|
|
8003ee4: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8003ee6: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8003eea: 663b str r3, [r7, #96] @ 0x60
|
|
8003eec: 2300 movs r3, #0
|
|
8003eee: 667b str r3, [r7, #100] @ 0x64
|
|
8003ef0: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60
|
|
8003ef4: 4622 mov r2, r4
|
|
8003ef6: 462b mov r3, r5
|
|
8003ef8: f04f 0000 mov.w r0, #0
|
|
8003efc: f04f 0100 mov.w r1, #0
|
|
8003f00: 0159 lsls r1, r3, #5
|
|
8003f02: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8003f06: 0150 lsls r0, r2, #5
|
|
8003f08: 4602 mov r2, r0
|
|
8003f0a: 460b mov r3, r1
|
|
8003f0c: 4621 mov r1, r4
|
|
8003f0e: 1a51 subs r1, r2, r1
|
|
8003f10: 61b9 str r1, [r7, #24]
|
|
8003f12: 4629 mov r1, r5
|
|
8003f14: eb63 0301 sbc.w r3, r3, r1
|
|
8003f18: 61fb str r3, [r7, #28]
|
|
8003f1a: f04f 0200 mov.w r2, #0
|
|
8003f1e: f04f 0300 mov.w r3, #0
|
|
8003f22: e9d7 ab06 ldrd sl, fp, [r7, #24]
|
|
8003f26: 4659 mov r1, fp
|
|
8003f28: 018b lsls r3, r1, #6
|
|
8003f2a: 4651 mov r1, sl
|
|
8003f2c: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8003f30: 4651 mov r1, sl
|
|
8003f32: 018a lsls r2, r1, #6
|
|
8003f34: 4651 mov r1, sl
|
|
8003f36: ebb2 0801 subs.w r8, r2, r1
|
|
8003f3a: 4659 mov r1, fp
|
|
8003f3c: eb63 0901 sbc.w r9, r3, r1
|
|
8003f40: f04f 0200 mov.w r2, #0
|
|
8003f44: f04f 0300 mov.w r3, #0
|
|
8003f48: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8003f4c: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8003f50: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
8003f54: 4690 mov r8, r2
|
|
8003f56: 4699 mov r9, r3
|
|
8003f58: 4623 mov r3, r4
|
|
8003f5a: eb18 0303 adds.w r3, r8, r3
|
|
8003f5e: 613b str r3, [r7, #16]
|
|
8003f60: 462b mov r3, r5
|
|
8003f62: eb49 0303 adc.w r3, r9, r3
|
|
8003f66: 617b str r3, [r7, #20]
|
|
8003f68: f04f 0200 mov.w r2, #0
|
|
8003f6c: f04f 0300 mov.w r3, #0
|
|
8003f70: e9d7 4504 ldrd r4, r5, [r7, #16]
|
|
8003f74: 4629 mov r1, r5
|
|
8003f76: 024b lsls r3, r1, #9
|
|
8003f78: 4621 mov r1, r4
|
|
8003f7a: ea43 53d1 orr.w r3, r3, r1, lsr #23
|
|
8003f7e: 4621 mov r1, r4
|
|
8003f80: 024a lsls r2, r1, #9
|
|
8003f82: 4610 mov r0, r2
|
|
8003f84: 4619 mov r1, r3
|
|
8003f86: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8003f8a: 2200 movs r2, #0
|
|
8003f8c: 65bb str r3, [r7, #88] @ 0x58
|
|
8003f8e: 65fa str r2, [r7, #92] @ 0x5c
|
|
8003f90: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
|
|
8003f94: f7fc f936 bl 8000204 <__aeabi_uldivmod>
|
|
8003f98: 4602 mov r2, r0
|
|
8003f9a: 460b mov r3, r1
|
|
8003f9c: 4613 mov r3, r2
|
|
8003f9e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8003fa2: e065 b.n 8004070 <HAL_RCC_GetSysClockFreq+0x420>
|
|
8003fa4: 40023800 .word 0x40023800
|
|
8003fa8: 00f42400 .word 0x00f42400
|
|
8003fac: 007a1200 .word 0x007a1200
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8003fb0: 4b3d ldr r3, [pc, #244] @ (80040a8 <HAL_RCC_GetSysClockFreq+0x458>)
|
|
8003fb2: 685b ldr r3, [r3, #4]
|
|
8003fb4: 099b lsrs r3, r3, #6
|
|
8003fb6: 2200 movs r2, #0
|
|
8003fb8: 4618 mov r0, r3
|
|
8003fba: 4611 mov r1, r2
|
|
8003fbc: f3c0 0308 ubfx r3, r0, #0, #9
|
|
8003fc0: 653b str r3, [r7, #80] @ 0x50
|
|
8003fc2: 2300 movs r3, #0
|
|
8003fc4: 657b str r3, [r7, #84] @ 0x54
|
|
8003fc6: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50
|
|
8003fca: 4642 mov r2, r8
|
|
8003fcc: 464b mov r3, r9
|
|
8003fce: f04f 0000 mov.w r0, #0
|
|
8003fd2: f04f 0100 mov.w r1, #0
|
|
8003fd6: 0159 lsls r1, r3, #5
|
|
8003fd8: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8003fdc: 0150 lsls r0, r2, #5
|
|
8003fde: 4602 mov r2, r0
|
|
8003fe0: 460b mov r3, r1
|
|
8003fe2: 4641 mov r1, r8
|
|
8003fe4: 1a51 subs r1, r2, r1
|
|
8003fe6: 60b9 str r1, [r7, #8]
|
|
8003fe8: 4649 mov r1, r9
|
|
8003fea: eb63 0301 sbc.w r3, r3, r1
|
|
8003fee: 60fb str r3, [r7, #12]
|
|
8003ff0: f04f 0200 mov.w r2, #0
|
|
8003ff4: f04f 0300 mov.w r3, #0
|
|
8003ff8: e9d7 ab02 ldrd sl, fp, [r7, #8]
|
|
8003ffc: 4659 mov r1, fp
|
|
8003ffe: 018b lsls r3, r1, #6
|
|
8004000: 4651 mov r1, sl
|
|
8004002: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8004006: 4651 mov r1, sl
|
|
8004008: 018a lsls r2, r1, #6
|
|
800400a: 4651 mov r1, sl
|
|
800400c: 1a54 subs r4, r2, r1
|
|
800400e: 4659 mov r1, fp
|
|
8004010: eb63 0501 sbc.w r5, r3, r1
|
|
8004014: f04f 0200 mov.w r2, #0
|
|
8004018: f04f 0300 mov.w r3, #0
|
|
800401c: 00eb lsls r3, r5, #3
|
|
800401e: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
8004022: 00e2 lsls r2, r4, #3
|
|
8004024: 4614 mov r4, r2
|
|
8004026: 461d mov r5, r3
|
|
8004028: 4643 mov r3, r8
|
|
800402a: 18e3 adds r3, r4, r3
|
|
800402c: 603b str r3, [r7, #0]
|
|
800402e: 464b mov r3, r9
|
|
8004030: eb45 0303 adc.w r3, r5, r3
|
|
8004034: 607b str r3, [r7, #4]
|
|
8004036: f04f 0200 mov.w r2, #0
|
|
800403a: f04f 0300 mov.w r3, #0
|
|
800403e: e9d7 4500 ldrd r4, r5, [r7]
|
|
8004042: 4629 mov r1, r5
|
|
8004044: 028b lsls r3, r1, #10
|
|
8004046: 4621 mov r1, r4
|
|
8004048: ea43 5391 orr.w r3, r3, r1, lsr #22
|
|
800404c: 4621 mov r1, r4
|
|
800404e: 028a lsls r2, r1, #10
|
|
8004050: 4610 mov r0, r2
|
|
8004052: 4619 mov r1, r3
|
|
8004054: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8004058: 2200 movs r2, #0
|
|
800405a: 64bb str r3, [r7, #72] @ 0x48
|
|
800405c: 64fa str r2, [r7, #76] @ 0x4c
|
|
800405e: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
|
|
8004062: f7fc f8cf bl 8000204 <__aeabi_uldivmod>
|
|
8004066: 4602 mov r2, r0
|
|
8004068: 460b mov r3, r1
|
|
800406a: 4613 mov r3, r2
|
|
800406c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
}
|
|
pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
|
|
8004070: 4b0d ldr r3, [pc, #52] @ (80040a8 <HAL_RCC_GetSysClockFreq+0x458>)
|
|
8004072: 685b ldr r3, [r3, #4]
|
|
8004074: 0f1b lsrs r3, r3, #28
|
|
8004076: f003 0307 and.w r3, r3, #7
|
|
800407a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
|
|
sysclockfreq = pllvco / pllr;
|
|
800407e: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
8004082: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
8004086: fbb2 f3f3 udiv r3, r2, r3
|
|
800408a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
800408e: e003 b.n 8004098 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
default:
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8004090: 4b06 ldr r3, [pc, #24] @ (80040ac <HAL_RCC_GetSysClockFreq+0x45c>)
|
|
8004092: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8004096: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8004098: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
|
|
}
|
|
800409c: 4618 mov r0, r3
|
|
800409e: 37b8 adds r7, #184 @ 0xb8
|
|
80040a0: 46bd mov sp, r7
|
|
80040a2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
80040a6: bf00 nop
|
|
80040a8: 40023800 .word 0x40023800
|
|
80040ac: 00f42400 .word 0x00f42400
|
|
|
|
080040b0 <HAL_RCC_OscConfig>:
|
|
* @note This function add the PLL/PLLR factor management during PLL configuration this feature
|
|
* is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
80040b0: b580 push {r7, lr}
|
|
80040b2: b086 sub sp, #24
|
|
80040b4: af00 add r7, sp, #0
|
|
80040b6: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
80040b8: 687b ldr r3, [r7, #4]
|
|
80040ba: 2b00 cmp r3, #0
|
|
80040bc: d101 bne.n 80040c2 <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80040be: 2301 movs r3, #1
|
|
80040c0: e28d b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
80040c2: 687b ldr r3, [r7, #4]
|
|
80040c4: 681b ldr r3, [r3, #0]
|
|
80040c6: f003 0301 and.w r3, r3, #1
|
|
80040ca: 2b00 cmp r3, #0
|
|
80040cc: f000 8083 beq.w 80041d6 <HAL_RCC_OscConfig+0x126>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
|
|
#if defined(STM32F446xx)
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
80040d0: 4b94 ldr r3, [pc, #592] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
80040d2: 689b ldr r3, [r3, #8]
|
|
80040d4: f003 030c and.w r3, r3, #12
|
|
80040d8: 2b04 cmp r3, #4
|
|
80040da: d019 beq.n 8004110 <HAL_RCC_OscConfig+0x60>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
80040dc: 4b91 ldr r3, [pc, #580] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
80040de: 689b ldr r3, [r3, #8]
|
|
80040e0: f003 030c and.w r3, r3, #12
|
|
|| \
|
|
80040e4: 2b08 cmp r3, #8
|
|
80040e6: d106 bne.n 80040f6 <HAL_RCC_OscConfig+0x46>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
80040e8: 4b8e ldr r3, [pc, #568] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
80040ea: 685b ldr r3, [r3, #4]
|
|
80040ec: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80040f0: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80040f4: d00c beq.n 8004110 <HAL_RCC_OscConfig+0x60>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
80040f6: 4b8b ldr r3, [pc, #556] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
80040f8: 689b ldr r3, [r3, #8]
|
|
80040fa: f003 030c and.w r3, r3, #12
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
80040fe: 2b0c cmp r3, #12
|
|
8004100: d112 bne.n 8004128 <HAL_RCC_OscConfig+0x78>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
8004102: 4b88 ldr r3, [pc, #544] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004104: 685b ldr r3, [r3, #4]
|
|
8004106: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
800410a: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
800410e: d10b bne.n 8004128 <HAL_RCC_OscConfig+0x78>
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
#endif /* STM32F446xx */
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8004110: 4b84 ldr r3, [pc, #528] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004112: 681b ldr r3, [r3, #0]
|
|
8004114: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004118: 2b00 cmp r3, #0
|
|
800411a: d05b beq.n 80041d4 <HAL_RCC_OscConfig+0x124>
|
|
800411c: 687b ldr r3, [r7, #4]
|
|
800411e: 685b ldr r3, [r3, #4]
|
|
8004120: 2b00 cmp r3, #0
|
|
8004122: d157 bne.n 80041d4 <HAL_RCC_OscConfig+0x124>
|
|
{
|
|
return HAL_ERROR;
|
|
8004124: 2301 movs r3, #1
|
|
8004126: e25a b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8004128: 687b ldr r3, [r7, #4]
|
|
800412a: 685b ldr r3, [r3, #4]
|
|
800412c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8004130: d106 bne.n 8004140 <HAL_RCC_OscConfig+0x90>
|
|
8004132: 4b7c ldr r3, [pc, #496] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004134: 681b ldr r3, [r3, #0]
|
|
8004136: 4a7b ldr r2, [pc, #492] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004138: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800413c: 6013 str r3, [r2, #0]
|
|
800413e: e01d b.n 800417c <HAL_RCC_OscConfig+0xcc>
|
|
8004140: 687b ldr r3, [r7, #4]
|
|
8004142: 685b ldr r3, [r3, #4]
|
|
8004144: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8004148: d10c bne.n 8004164 <HAL_RCC_OscConfig+0xb4>
|
|
800414a: 4b76 ldr r3, [pc, #472] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
800414c: 681b ldr r3, [r3, #0]
|
|
800414e: 4a75 ldr r2, [pc, #468] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004150: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8004154: 6013 str r3, [r2, #0]
|
|
8004156: 4b73 ldr r3, [pc, #460] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004158: 681b ldr r3, [r3, #0]
|
|
800415a: 4a72 ldr r2, [pc, #456] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
800415c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004160: 6013 str r3, [r2, #0]
|
|
8004162: e00b b.n 800417c <HAL_RCC_OscConfig+0xcc>
|
|
8004164: 4b6f ldr r3, [pc, #444] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004166: 681b ldr r3, [r3, #0]
|
|
8004168: 4a6e ldr r2, [pc, #440] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
800416a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800416e: 6013 str r3, [r2, #0]
|
|
8004170: 4b6c ldr r3, [pc, #432] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004172: 681b ldr r3, [r3, #0]
|
|
8004174: 4a6b ldr r2, [pc, #428] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004176: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
800417a: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
|
|
800417c: 687b ldr r3, [r7, #4]
|
|
800417e: 685b ldr r3, [r3, #4]
|
|
8004180: 2b00 cmp r3, #0
|
|
8004182: d013 beq.n 80041ac <HAL_RCC_OscConfig+0xfc>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004184: f7fd f9c8 bl 8001518 <HAL_GetTick>
|
|
8004188: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
800418a: e008 b.n 800419e <HAL_RCC_OscConfig+0xee>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
800418c: f7fd f9c4 bl 8001518 <HAL_GetTick>
|
|
8004190: 4602 mov r2, r0
|
|
8004192: 693b ldr r3, [r7, #16]
|
|
8004194: 1ad3 subs r3, r2, r3
|
|
8004196: 2b64 cmp r3, #100 @ 0x64
|
|
8004198: d901 bls.n 800419e <HAL_RCC_OscConfig+0xee>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800419a: 2303 movs r3, #3
|
|
800419c: e21f b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
800419e: 4b61 ldr r3, [pc, #388] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
80041a0: 681b ldr r3, [r3, #0]
|
|
80041a2: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80041a6: 2b00 cmp r3, #0
|
|
80041a8: d0f0 beq.n 800418c <HAL_RCC_OscConfig+0xdc>
|
|
80041aa: e014 b.n 80041d6 <HAL_RCC_OscConfig+0x126>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80041ac: f7fd f9b4 bl 8001518 <HAL_GetTick>
|
|
80041b0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is bypassed or disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
80041b2: e008 b.n 80041c6 <HAL_RCC_OscConfig+0x116>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
80041b4: f7fd f9b0 bl 8001518 <HAL_GetTick>
|
|
80041b8: 4602 mov r2, r0
|
|
80041ba: 693b ldr r3, [r7, #16]
|
|
80041bc: 1ad3 subs r3, r2, r3
|
|
80041be: 2b64 cmp r3, #100 @ 0x64
|
|
80041c0: d901 bls.n 80041c6 <HAL_RCC_OscConfig+0x116>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80041c2: 2303 movs r3, #3
|
|
80041c4: e20b b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
80041c6: 4b57 ldr r3, [pc, #348] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
80041c8: 681b ldr r3, [r3, #0]
|
|
80041ca: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80041ce: 2b00 cmp r3, #0
|
|
80041d0: d1f0 bne.n 80041b4 <HAL_RCC_OscConfig+0x104>
|
|
80041d2: e000 b.n 80041d6 <HAL_RCC_OscConfig+0x126>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
80041d4: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
80041d6: 687b ldr r3, [r7, #4]
|
|
80041d8: 681b ldr r3, [r3, #0]
|
|
80041da: f003 0302 and.w r3, r3, #2
|
|
80041de: 2b00 cmp r3, #0
|
|
80041e0: d06f beq.n 80042c2 <HAL_RCC_OscConfig+0x212>
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
#if defined(STM32F446xx)
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
|
|
80041e2: 4b50 ldr r3, [pc, #320] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
80041e4: 689b ldr r3, [r3, #8]
|
|
80041e6: f003 030c and.w r3, r3, #12
|
|
80041ea: 2b00 cmp r3, #0
|
|
80041ec: d017 beq.n 800421e <HAL_RCC_OscConfig+0x16e>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
80041ee: 4b4d ldr r3, [pc, #308] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
80041f0: 689b ldr r3, [r3, #8]
|
|
80041f2: f003 030c and.w r3, r3, #12
|
|
|| \
|
|
80041f6: 2b08 cmp r3, #8
|
|
80041f8: d105 bne.n 8004206 <HAL_RCC_OscConfig+0x156>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
80041fa: 4b4a ldr r3, [pc, #296] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
80041fc: 685b ldr r3, [r3, #4]
|
|
80041fe: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004202: 2b00 cmp r3, #0
|
|
8004204: d00b beq.n 800421e <HAL_RCC_OscConfig+0x16e>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
8004206: 4b47 ldr r3, [pc, #284] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004208: 689b ldr r3, [r3, #8]
|
|
800420a: f003 030c and.w r3, r3, #12
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
800420e: 2b0c cmp r3, #12
|
|
8004210: d11c bne.n 800424c <HAL_RCC_OscConfig+0x19c>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
8004212: 4b44 ldr r3, [pc, #272] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004214: 685b ldr r3, [r3, #4]
|
|
8004216: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
800421a: 2b00 cmp r3, #0
|
|
800421c: d116 bne.n 800424c <HAL_RCC_OscConfig+0x19c>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
#endif /* STM32F446xx */
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
800421e: 4b41 ldr r3, [pc, #260] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004220: 681b ldr r3, [r3, #0]
|
|
8004222: f003 0302 and.w r3, r3, #2
|
|
8004226: 2b00 cmp r3, #0
|
|
8004228: d005 beq.n 8004236 <HAL_RCC_OscConfig+0x186>
|
|
800422a: 687b ldr r3, [r7, #4]
|
|
800422c: 68db ldr r3, [r3, #12]
|
|
800422e: 2b01 cmp r3, #1
|
|
8004230: d001 beq.n 8004236 <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
return HAL_ERROR;
|
|
8004232: 2301 movs r3, #1
|
|
8004234: e1d3 b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8004236: 4b3b ldr r3, [pc, #236] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004238: 681b ldr r3, [r3, #0]
|
|
800423a: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
800423e: 687b ldr r3, [r7, #4]
|
|
8004240: 691b ldr r3, [r3, #16]
|
|
8004242: 00db lsls r3, r3, #3
|
|
8004244: 4937 ldr r1, [pc, #220] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004246: 4313 orrs r3, r2
|
|
8004248: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
800424a: e03a b.n 80042c2 <HAL_RCC_OscConfig+0x212>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
|
|
800424c: 687b ldr r3, [r7, #4]
|
|
800424e: 68db ldr r3, [r3, #12]
|
|
8004250: 2b00 cmp r3, #0
|
|
8004252: d020 beq.n 8004296 <HAL_RCC_OscConfig+0x1e6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8004254: 4b34 ldr r3, [pc, #208] @ (8004328 <HAL_RCC_OscConfig+0x278>)
|
|
8004256: 2201 movs r2, #1
|
|
8004258: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800425a: f7fd f95d bl 8001518 <HAL_GetTick>
|
|
800425e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004260: e008 b.n 8004274 <HAL_RCC_OscConfig+0x1c4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8004262: f7fd f959 bl 8001518 <HAL_GetTick>
|
|
8004266: 4602 mov r2, r0
|
|
8004268: 693b ldr r3, [r7, #16]
|
|
800426a: 1ad3 subs r3, r2, r3
|
|
800426c: 2b02 cmp r3, #2
|
|
800426e: d901 bls.n 8004274 <HAL_RCC_OscConfig+0x1c4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004270: 2303 movs r3, #3
|
|
8004272: e1b4 b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004274: 4b2b ldr r3, [pc, #172] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004276: 681b ldr r3, [r3, #0]
|
|
8004278: f003 0302 and.w r3, r3, #2
|
|
800427c: 2b00 cmp r3, #0
|
|
800427e: d0f0 beq.n 8004262 <HAL_RCC_OscConfig+0x1b2>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8004280: 4b28 ldr r3, [pc, #160] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004282: 681b ldr r3, [r3, #0]
|
|
8004284: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8004288: 687b ldr r3, [r7, #4]
|
|
800428a: 691b ldr r3, [r3, #16]
|
|
800428c: 00db lsls r3, r3, #3
|
|
800428e: 4925 ldr r1, [pc, #148] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
8004290: 4313 orrs r3, r2
|
|
8004292: 600b str r3, [r1, #0]
|
|
8004294: e015 b.n 80042c2 <HAL_RCC_OscConfig+0x212>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8004296: 4b24 ldr r3, [pc, #144] @ (8004328 <HAL_RCC_OscConfig+0x278>)
|
|
8004298: 2200 movs r2, #0
|
|
800429a: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800429c: f7fd f93c bl 8001518 <HAL_GetTick>
|
|
80042a0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
80042a2: e008 b.n 80042b6 <HAL_RCC_OscConfig+0x206>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
80042a4: f7fd f938 bl 8001518 <HAL_GetTick>
|
|
80042a8: 4602 mov r2, r0
|
|
80042aa: 693b ldr r3, [r7, #16]
|
|
80042ac: 1ad3 subs r3, r2, r3
|
|
80042ae: 2b02 cmp r3, #2
|
|
80042b0: d901 bls.n 80042b6 <HAL_RCC_OscConfig+0x206>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80042b2: 2303 movs r3, #3
|
|
80042b4: e193 b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
80042b6: 4b1b ldr r3, [pc, #108] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
80042b8: 681b ldr r3, [r3, #0]
|
|
80042ba: f003 0302 and.w r3, r3, #2
|
|
80042be: 2b00 cmp r3, #0
|
|
80042c0: d1f0 bne.n 80042a4 <HAL_RCC_OscConfig+0x1f4>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
80042c2: 687b ldr r3, [r7, #4]
|
|
80042c4: 681b ldr r3, [r3, #0]
|
|
80042c6: f003 0308 and.w r3, r3, #8
|
|
80042ca: 2b00 cmp r3, #0
|
|
80042cc: d036 beq.n 800433c <HAL_RCC_OscConfig+0x28c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
|
|
80042ce: 687b ldr r3, [r7, #4]
|
|
80042d0: 695b ldr r3, [r3, #20]
|
|
80042d2: 2b00 cmp r3, #0
|
|
80042d4: d016 beq.n 8004304 <HAL_RCC_OscConfig+0x254>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
80042d6: 4b15 ldr r3, [pc, #84] @ (800432c <HAL_RCC_OscConfig+0x27c>)
|
|
80042d8: 2201 movs r2, #1
|
|
80042da: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80042dc: f7fd f91c bl 8001518 <HAL_GetTick>
|
|
80042e0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80042e2: e008 b.n 80042f6 <HAL_RCC_OscConfig+0x246>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
80042e4: f7fd f918 bl 8001518 <HAL_GetTick>
|
|
80042e8: 4602 mov r2, r0
|
|
80042ea: 693b ldr r3, [r7, #16]
|
|
80042ec: 1ad3 subs r3, r2, r3
|
|
80042ee: 2b02 cmp r3, #2
|
|
80042f0: d901 bls.n 80042f6 <HAL_RCC_OscConfig+0x246>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80042f2: 2303 movs r3, #3
|
|
80042f4: e173 b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80042f6: 4b0b ldr r3, [pc, #44] @ (8004324 <HAL_RCC_OscConfig+0x274>)
|
|
80042f8: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80042fa: f003 0302 and.w r3, r3, #2
|
|
80042fe: 2b00 cmp r3, #0
|
|
8004300: d0f0 beq.n 80042e4 <HAL_RCC_OscConfig+0x234>
|
|
8004302: e01b b.n 800433c <HAL_RCC_OscConfig+0x28c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8004304: 4b09 ldr r3, [pc, #36] @ (800432c <HAL_RCC_OscConfig+0x27c>)
|
|
8004306: 2200 movs r2, #0
|
|
8004308: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800430a: f7fd f905 bl 8001518 <HAL_GetTick>
|
|
800430e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8004310: e00e b.n 8004330 <HAL_RCC_OscConfig+0x280>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8004312: f7fd f901 bl 8001518 <HAL_GetTick>
|
|
8004316: 4602 mov r2, r0
|
|
8004318: 693b ldr r3, [r7, #16]
|
|
800431a: 1ad3 subs r3, r2, r3
|
|
800431c: 2b02 cmp r3, #2
|
|
800431e: d907 bls.n 8004330 <HAL_RCC_OscConfig+0x280>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004320: 2303 movs r3, #3
|
|
8004322: e15c b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
8004324: 40023800 .word 0x40023800
|
|
8004328: 42470000 .word 0x42470000
|
|
800432c: 42470e80 .word 0x42470e80
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8004330: 4b8a ldr r3, [pc, #552] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
8004332: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8004334: f003 0302 and.w r3, r3, #2
|
|
8004338: 2b00 cmp r3, #0
|
|
800433a: d1ea bne.n 8004312 <HAL_RCC_OscConfig+0x262>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
800433c: 687b ldr r3, [r7, #4]
|
|
800433e: 681b ldr r3, [r3, #0]
|
|
8004340: f003 0304 and.w r3, r3, #4
|
|
8004344: 2b00 cmp r3, #0
|
|
8004346: f000 8097 beq.w 8004478 <HAL_RCC_OscConfig+0x3c8>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
800434a: 2300 movs r3, #0
|
|
800434c: 75fb strb r3, [r7, #23]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
800434e: 4b83 ldr r3, [pc, #524] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
8004350: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004352: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8004356: 2b00 cmp r3, #0
|
|
8004358: d10f bne.n 800437a <HAL_RCC_OscConfig+0x2ca>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800435a: 2300 movs r3, #0
|
|
800435c: 60bb str r3, [r7, #8]
|
|
800435e: 4b7f ldr r3, [pc, #508] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
8004360: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004362: 4a7e ldr r2, [pc, #504] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
8004364: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8004368: 6413 str r3, [r2, #64] @ 0x40
|
|
800436a: 4b7c ldr r3, [pc, #496] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
800436c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800436e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8004372: 60bb str r3, [r7, #8]
|
|
8004374: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8004376: 2301 movs r3, #1
|
|
8004378: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
800437a: 4b79 ldr r3, [pc, #484] @ (8004560 <HAL_RCC_OscConfig+0x4b0>)
|
|
800437c: 681b ldr r3, [r3, #0]
|
|
800437e: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004382: 2b00 cmp r3, #0
|
|
8004384: d118 bne.n 80043b8 <HAL_RCC_OscConfig+0x308>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
8004386: 4b76 ldr r3, [pc, #472] @ (8004560 <HAL_RCC_OscConfig+0x4b0>)
|
|
8004388: 681b ldr r3, [r3, #0]
|
|
800438a: 4a75 ldr r2, [pc, #468] @ (8004560 <HAL_RCC_OscConfig+0x4b0>)
|
|
800438c: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8004390: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8004392: f7fd f8c1 bl 8001518 <HAL_GetTick>
|
|
8004396: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004398: e008 b.n 80043ac <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
800439a: f7fd f8bd bl 8001518 <HAL_GetTick>
|
|
800439e: 4602 mov r2, r0
|
|
80043a0: 693b ldr r3, [r7, #16]
|
|
80043a2: 1ad3 subs r3, r2, r3
|
|
80043a4: 2b02 cmp r3, #2
|
|
80043a6: d901 bls.n 80043ac <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80043a8: 2303 movs r3, #3
|
|
80043aa: e118 b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
80043ac: 4b6c ldr r3, [pc, #432] @ (8004560 <HAL_RCC_OscConfig+0x4b0>)
|
|
80043ae: 681b ldr r3, [r3, #0]
|
|
80043b0: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80043b4: 2b00 cmp r3, #0
|
|
80043b6: d0f0 beq.n 800439a <HAL_RCC_OscConfig+0x2ea>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
80043b8: 687b ldr r3, [r7, #4]
|
|
80043ba: 689b ldr r3, [r3, #8]
|
|
80043bc: 2b01 cmp r3, #1
|
|
80043be: d106 bne.n 80043ce <HAL_RCC_OscConfig+0x31e>
|
|
80043c0: 4b66 ldr r3, [pc, #408] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
80043c2: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80043c4: 4a65 ldr r2, [pc, #404] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
80043c6: f043 0301 orr.w r3, r3, #1
|
|
80043ca: 6713 str r3, [r2, #112] @ 0x70
|
|
80043cc: e01c b.n 8004408 <HAL_RCC_OscConfig+0x358>
|
|
80043ce: 687b ldr r3, [r7, #4]
|
|
80043d0: 689b ldr r3, [r3, #8]
|
|
80043d2: 2b05 cmp r3, #5
|
|
80043d4: d10c bne.n 80043f0 <HAL_RCC_OscConfig+0x340>
|
|
80043d6: 4b61 ldr r3, [pc, #388] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
80043d8: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80043da: 4a60 ldr r2, [pc, #384] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
80043dc: f043 0304 orr.w r3, r3, #4
|
|
80043e0: 6713 str r3, [r2, #112] @ 0x70
|
|
80043e2: 4b5e ldr r3, [pc, #376] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
80043e4: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80043e6: 4a5d ldr r2, [pc, #372] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
80043e8: f043 0301 orr.w r3, r3, #1
|
|
80043ec: 6713 str r3, [r2, #112] @ 0x70
|
|
80043ee: e00b b.n 8004408 <HAL_RCC_OscConfig+0x358>
|
|
80043f0: 4b5a ldr r3, [pc, #360] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
80043f2: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80043f4: 4a59 ldr r2, [pc, #356] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
80043f6: f023 0301 bic.w r3, r3, #1
|
|
80043fa: 6713 str r3, [r2, #112] @ 0x70
|
|
80043fc: 4b57 ldr r3, [pc, #348] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
80043fe: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004400: 4a56 ldr r2, [pc, #344] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
8004402: f023 0304 bic.w r3, r3, #4
|
|
8004406: 6713 str r3, [r2, #112] @ 0x70
|
|
/* Check the LSE State */
|
|
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
|
|
8004408: 687b ldr r3, [r7, #4]
|
|
800440a: 689b ldr r3, [r3, #8]
|
|
800440c: 2b00 cmp r3, #0
|
|
800440e: d015 beq.n 800443c <HAL_RCC_OscConfig+0x38c>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004410: f7fd f882 bl 8001518 <HAL_GetTick>
|
|
8004414: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8004416: e00a b.n 800442e <HAL_RCC_OscConfig+0x37e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8004418: f7fd f87e bl 8001518 <HAL_GetTick>
|
|
800441c: 4602 mov r2, r0
|
|
800441e: 693b ldr r3, [r7, #16]
|
|
8004420: 1ad3 subs r3, r2, r3
|
|
8004422: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004426: 4293 cmp r3, r2
|
|
8004428: d901 bls.n 800442e <HAL_RCC_OscConfig+0x37e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800442a: 2303 movs r3, #3
|
|
800442c: e0d7 b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
800442e: 4b4b ldr r3, [pc, #300] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
8004430: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004432: f003 0302 and.w r3, r3, #2
|
|
8004436: 2b00 cmp r3, #0
|
|
8004438: d0ee beq.n 8004418 <HAL_RCC_OscConfig+0x368>
|
|
800443a: e014 b.n 8004466 <HAL_RCC_OscConfig+0x3b6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800443c: f7fd f86c bl 8001518 <HAL_GetTick>
|
|
8004440: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8004442: e00a b.n 800445a <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8004444: f7fd f868 bl 8001518 <HAL_GetTick>
|
|
8004448: 4602 mov r2, r0
|
|
800444a: 693b ldr r3, [r7, #16]
|
|
800444c: 1ad3 subs r3, r2, r3
|
|
800444e: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004452: 4293 cmp r3, r2
|
|
8004454: d901 bls.n 800445a <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004456: 2303 movs r3, #3
|
|
8004458: e0c1 b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
800445a: 4b40 ldr r3, [pc, #256] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
800445c: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800445e: f003 0302 and.w r3, r3, #2
|
|
8004462: 2b00 cmp r3, #0
|
|
8004464: d1ee bne.n 8004444 <HAL_RCC_OscConfig+0x394>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
8004466: 7dfb ldrb r3, [r7, #23]
|
|
8004468: 2b01 cmp r3, #1
|
|
800446a: d105 bne.n 8004478 <HAL_RCC_OscConfig+0x3c8>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
800446c: 4b3b ldr r3, [pc, #236] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
800446e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004470: 4a3a ldr r2, [pc, #232] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
8004472: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8004476: 6413 str r3, [r2, #64] @ 0x40
|
|
}
|
|
}
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8004478: 687b ldr r3, [r7, #4]
|
|
800447a: 699b ldr r3, [r3, #24]
|
|
800447c: 2b00 cmp r3, #0
|
|
800447e: f000 80ad beq.w 80045dc <HAL_RCC_OscConfig+0x52c>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
|
8004482: 4b36 ldr r3, [pc, #216] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
8004484: 689b ldr r3, [r3, #8]
|
|
8004486: f003 030c and.w r3, r3, #12
|
|
800448a: 2b08 cmp r3, #8
|
|
800448c: d060 beq.n 8004550 <HAL_RCC_OscConfig+0x4a0>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
800448e: 687b ldr r3, [r7, #4]
|
|
8004490: 699b ldr r3, [r3, #24]
|
|
8004492: 2b02 cmp r3, #2
|
|
8004494: d145 bne.n 8004522 <HAL_RCC_OscConfig+0x472>
|
|
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8004496: 4b33 ldr r3, [pc, #204] @ (8004564 <HAL_RCC_OscConfig+0x4b4>)
|
|
8004498: 2200 movs r2, #0
|
|
800449a: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800449c: f7fd f83c bl 8001518 <HAL_GetTick>
|
|
80044a0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80044a2: e008 b.n 80044b6 <HAL_RCC_OscConfig+0x406>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80044a4: f7fd f838 bl 8001518 <HAL_GetTick>
|
|
80044a8: 4602 mov r2, r0
|
|
80044aa: 693b ldr r3, [r7, #16]
|
|
80044ac: 1ad3 subs r3, r2, r3
|
|
80044ae: 2b02 cmp r3, #2
|
|
80044b0: d901 bls.n 80044b6 <HAL_RCC_OscConfig+0x406>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80044b2: 2303 movs r3, #3
|
|
80044b4: e093 b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80044b6: 4b29 ldr r3, [pc, #164] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
80044b8: 681b ldr r3, [r3, #0]
|
|
80044ba: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80044be: 2b00 cmp r3, #0
|
|
80044c0: d1f0 bne.n 80044a4 <HAL_RCC_OscConfig+0x3f4>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
|
|
80044c2: 687b ldr r3, [r7, #4]
|
|
80044c4: 69da ldr r2, [r3, #28]
|
|
80044c6: 687b ldr r3, [r7, #4]
|
|
80044c8: 6a1b ldr r3, [r3, #32]
|
|
80044ca: 431a orrs r2, r3
|
|
80044cc: 687b ldr r3, [r7, #4]
|
|
80044ce: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80044d0: 019b lsls r3, r3, #6
|
|
80044d2: 431a orrs r2, r3
|
|
80044d4: 687b ldr r3, [r7, #4]
|
|
80044d6: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80044d8: 085b lsrs r3, r3, #1
|
|
80044da: 3b01 subs r3, #1
|
|
80044dc: 041b lsls r3, r3, #16
|
|
80044de: 431a orrs r2, r3
|
|
80044e0: 687b ldr r3, [r7, #4]
|
|
80044e2: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80044e4: 061b lsls r3, r3, #24
|
|
80044e6: 431a orrs r2, r3
|
|
80044e8: 687b ldr r3, [r7, #4]
|
|
80044ea: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80044ec: 071b lsls r3, r3, #28
|
|
80044ee: 491b ldr r1, [pc, #108] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
80044f0: 4313 orrs r3, r2
|
|
80044f2: 604b str r3, [r1, #4]
|
|
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
|
|
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
80044f4: 4b1b ldr r3, [pc, #108] @ (8004564 <HAL_RCC_OscConfig+0x4b4>)
|
|
80044f6: 2201 movs r2, #1
|
|
80044f8: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80044fa: f7fd f80d bl 8001518 <HAL_GetTick>
|
|
80044fe: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8004500: e008 b.n 8004514 <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8004502: f7fd f809 bl 8001518 <HAL_GetTick>
|
|
8004506: 4602 mov r2, r0
|
|
8004508: 693b ldr r3, [r7, #16]
|
|
800450a: 1ad3 subs r3, r2, r3
|
|
800450c: 2b02 cmp r3, #2
|
|
800450e: d901 bls.n 8004514 <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004510: 2303 movs r3, #3
|
|
8004512: e064 b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8004514: 4b11 ldr r3, [pc, #68] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
8004516: 681b ldr r3, [r3, #0]
|
|
8004518: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800451c: 2b00 cmp r3, #0
|
|
800451e: d0f0 beq.n 8004502 <HAL_RCC_OscConfig+0x452>
|
|
8004520: e05c b.n 80045dc <HAL_RCC_OscConfig+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8004522: 4b10 ldr r3, [pc, #64] @ (8004564 <HAL_RCC_OscConfig+0x4b4>)
|
|
8004524: 2200 movs r2, #0
|
|
8004526: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004528: f7fc fff6 bl 8001518 <HAL_GetTick>
|
|
800452c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
800452e: e008 b.n 8004542 <HAL_RCC_OscConfig+0x492>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8004530: f7fc fff2 bl 8001518 <HAL_GetTick>
|
|
8004534: 4602 mov r2, r0
|
|
8004536: 693b ldr r3, [r7, #16]
|
|
8004538: 1ad3 subs r3, r2, r3
|
|
800453a: 2b02 cmp r3, #2
|
|
800453c: d901 bls.n 8004542 <HAL_RCC_OscConfig+0x492>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800453e: 2303 movs r3, #3
|
|
8004540: e04d b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8004542: 4b06 ldr r3, [pc, #24] @ (800455c <HAL_RCC_OscConfig+0x4ac>)
|
|
8004544: 681b ldr r3, [r3, #0]
|
|
8004546: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800454a: 2b00 cmp r3, #0
|
|
800454c: d1f0 bne.n 8004530 <HAL_RCC_OscConfig+0x480>
|
|
800454e: e045 b.n 80045dc <HAL_RCC_OscConfig+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8004550: 687b ldr r3, [r7, #4]
|
|
8004552: 699b ldr r3, [r3, #24]
|
|
8004554: 2b01 cmp r3, #1
|
|
8004556: d107 bne.n 8004568 <HAL_RCC_OscConfig+0x4b8>
|
|
{
|
|
return HAL_ERROR;
|
|
8004558: 2301 movs r3, #1
|
|
800455a: e040 b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
800455c: 40023800 .word 0x40023800
|
|
8004560: 40007000 .word 0x40007000
|
|
8004564: 42470060 .word 0x42470060
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->PLLCFGR;
|
|
8004568: 4b1f ldr r3, [pc, #124] @ (80045e8 <HAL_RCC_OscConfig+0x538>)
|
|
800456a: 685b ldr r3, [r3, #4]
|
|
800456c: 60fb str r3, [r7, #12]
|
|
#if defined (RCC_PLLCFGR_PLLR)
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
800456e: 687b ldr r3, [r7, #4]
|
|
8004570: 699b ldr r3, [r3, #24]
|
|
8004572: 2b01 cmp r3, #1
|
|
8004574: d030 beq.n 80045d8 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8004576: 68fb ldr r3, [r7, #12]
|
|
8004578: f403 0280 and.w r2, r3, #4194304 @ 0x400000
|
|
800457c: 687b ldr r3, [r7, #4]
|
|
800457e: 69db ldr r3, [r3, #28]
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
8004580: 429a cmp r2, r3
|
|
8004582: d129 bne.n 80045d8 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
8004584: 68fb ldr r3, [r7, #12]
|
|
8004586: f003 023f and.w r2, r3, #63 @ 0x3f
|
|
800458a: 687b ldr r3, [r7, #4]
|
|
800458c: 6a1b ldr r3, [r3, #32]
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800458e: 429a cmp r2, r3
|
|
8004590: d122 bne.n 80045d8 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
8004592: 68fa ldr r2, [r7, #12]
|
|
8004594: f647 73c0 movw r3, #32704 @ 0x7fc0
|
|
8004598: 4013 ands r3, r2
|
|
800459a: 687a ldr r2, [r7, #4]
|
|
800459c: 6a52 ldr r2, [r2, #36] @ 0x24
|
|
800459e: 0192 lsls r2, r2, #6
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
80045a0: 4293 cmp r3, r2
|
|
80045a2: d119 bne.n 80045d8 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
80045a4: 68fb ldr r3, [r7, #12]
|
|
80045a6: f403 3240 and.w r2, r3, #196608 @ 0x30000
|
|
80045aa: 687b ldr r3, [r7, #4]
|
|
80045ac: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80045ae: 085b lsrs r3, r3, #1
|
|
80045b0: 3b01 subs r3, #1
|
|
80045b2: 041b lsls r3, r3, #16
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
80045b4: 429a cmp r2, r3
|
|
80045b6: d10f bne.n 80045d8 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
80045b8: 68fb ldr r3, [r7, #12]
|
|
80045ba: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
|
|
80045be: 687b ldr r3, [r7, #4]
|
|
80045c0: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80045c2: 061b lsls r3, r3, #24
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
80045c4: 429a cmp r2, r3
|
|
80045c6: d107 bne.n 80045d8 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
|
|
80045c8: 68fb ldr r3, [r7, #12]
|
|
80045ca: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000
|
|
80045ce: 687b ldr r3, [r7, #4]
|
|
80045d0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80045d2: 071b lsls r3, r3, #28
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
80045d4: 429a cmp r2, r3
|
|
80045d6: d001 beq.n 80045dc <HAL_RCC_OscConfig+0x52c>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
|
|
#endif /* RCC_PLLCFGR_PLLR */
|
|
{
|
|
return HAL_ERROR;
|
|
80045d8: 2301 movs r3, #1
|
|
80045da: e000 b.n 80045de <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80045dc: 2300 movs r3, #0
|
|
}
|
|
80045de: 4618 mov r0, r3
|
|
80045e0: 3718 adds r7, #24
|
|
80045e2: 46bd mov sp, r7
|
|
80045e4: bd80 pop {r7, pc}
|
|
80045e6: bf00 nop
|
|
80045e8: 40023800 .word 0x40023800
|
|
|
|
080045ec <HAL_TIM_OC_Init>:
|
|
* Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
|
|
* @param htim TIM Output Compare handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
80045ec: b580 push {r7, lr}
|
|
80045ee: b082 sub sp, #8
|
|
80045f0: af00 add r7, sp, #0
|
|
80045f2: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
80045f4: 687b ldr r3, [r7, #4]
|
|
80045f6: 2b00 cmp r3, #0
|
|
80045f8: d101 bne.n 80045fe <HAL_TIM_OC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80045fa: 2301 movs r3, #1
|
|
80045fc: e041 b.n 8004682 <HAL_TIM_OC_Init+0x96>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
80045fe: 687b ldr r3, [r7, #4]
|
|
8004600: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8004604: b2db uxtb r3, r3
|
|
8004606: 2b00 cmp r3, #0
|
|
8004608: d106 bne.n 8004618 <HAL_TIM_OC_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
800460a: 687b ldr r3, [r7, #4]
|
|
800460c: 2200 movs r2, #0
|
|
800460e: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->OC_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_OC_MspInit(htim);
|
|
8004612: 6878 ldr r0, [r7, #4]
|
|
8004614: f7fc fcc8 bl 8000fa8 <HAL_TIM_OC_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8004618: 687b ldr r3, [r7, #4]
|
|
800461a: 2202 movs r2, #2
|
|
800461c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Init the base time for the Output Compare */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8004620: 687b ldr r3, [r7, #4]
|
|
8004622: 681a ldr r2, [r3, #0]
|
|
8004624: 687b ldr r3, [r7, #4]
|
|
8004626: 3304 adds r3, #4
|
|
8004628: 4619 mov r1, r3
|
|
800462a: 4610 mov r0, r2
|
|
800462c: f000 f930 bl 8004890 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8004630: 687b ldr r3, [r7, #4]
|
|
8004632: 2201 movs r2, #1
|
|
8004634: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8004638: 687b ldr r3, [r7, #4]
|
|
800463a: 2201 movs r2, #1
|
|
800463c: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
8004640: 687b ldr r3, [r7, #4]
|
|
8004642: 2201 movs r2, #1
|
|
8004644: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
8004648: 687b ldr r3, [r7, #4]
|
|
800464a: 2201 movs r2, #1
|
|
800464c: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
8004650: 687b ldr r3, [r7, #4]
|
|
8004652: 2201 movs r2, #1
|
|
8004654: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8004658: 687b ldr r3, [r7, #4]
|
|
800465a: 2201 movs r2, #1
|
|
800465c: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
8004660: 687b ldr r3, [r7, #4]
|
|
8004662: 2201 movs r2, #1
|
|
8004664: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
8004668: 687b ldr r3, [r7, #4]
|
|
800466a: 2201 movs r2, #1
|
|
800466c: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
8004670: 687b ldr r3, [r7, #4]
|
|
8004672: 2201 movs r2, #1
|
|
8004674: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8004678: 687b ldr r3, [r7, #4]
|
|
800467a: 2201 movs r2, #1
|
|
800467c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
8004680: 2300 movs r3, #0
|
|
}
|
|
8004682: 4618 mov r0, r3
|
|
8004684: 3708 adds r7, #8
|
|
8004686: 46bd mov sp, r7
|
|
8004688: bd80 pop {r7, pc}
|
|
|
|
0800468a <HAL_TIM_Encoder_Init>:
|
|
* @param htim TIM Encoder Interface handle
|
|
* @param sConfig TIM Encoder Interface configuration structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
|
|
{
|
|
800468a: b580 push {r7, lr}
|
|
800468c: b086 sub sp, #24
|
|
800468e: af00 add r7, sp, #0
|
|
8004690: 6078 str r0, [r7, #4]
|
|
8004692: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
8004694: 687b ldr r3, [r7, #4]
|
|
8004696: 2b00 cmp r3, #0
|
|
8004698: d101 bne.n 800469e <HAL_TIM_Encoder_Init+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
800469a: 2301 movs r3, #1
|
|
800469c: e097 b.n 80047ce <HAL_TIM_Encoder_Init+0x144>
|
|
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
|
|
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
|
|
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
800469e: 687b ldr r3, [r7, #4]
|
|
80046a0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
80046a4: b2db uxtb r3, r3
|
|
80046a6: 2b00 cmp r3, #0
|
|
80046a8: d106 bne.n 80046b8 <HAL_TIM_Encoder_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
80046aa: 687b ldr r3, [r7, #4]
|
|
80046ac: 2200 movs r2, #0
|
|
80046ae: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Encoder_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_Encoder_MspInit(htim);
|
|
80046b2: 6878 ldr r0, [r7, #4]
|
|
80046b4: f7fc fc98 bl 8000fe8 <HAL_TIM_Encoder_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80046b8: 687b ldr r3, [r7, #4]
|
|
80046ba: 2202 movs r2, #2
|
|
80046bc: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Reset the SMS and ECE bits */
|
|
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
|
|
80046c0: 687b ldr r3, [r7, #4]
|
|
80046c2: 681b ldr r3, [r3, #0]
|
|
80046c4: 689b ldr r3, [r3, #8]
|
|
80046c6: 687a ldr r2, [r7, #4]
|
|
80046c8: 6812 ldr r2, [r2, #0]
|
|
80046ca: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
80046ce: f023 0307 bic.w r3, r3, #7
|
|
80046d2: 6093 str r3, [r2, #8]
|
|
|
|
/* Configure the Time base in the Encoder Mode */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
80046d4: 687b ldr r3, [r7, #4]
|
|
80046d6: 681a ldr r2, [r3, #0]
|
|
80046d8: 687b ldr r3, [r7, #4]
|
|
80046da: 3304 adds r3, #4
|
|
80046dc: 4619 mov r1, r3
|
|
80046de: 4610 mov r0, r2
|
|
80046e0: f000 f8d6 bl 8004890 <TIM_Base_SetConfig>
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80046e4: 687b ldr r3, [r7, #4]
|
|
80046e6: 681b ldr r3, [r3, #0]
|
|
80046e8: 689b ldr r3, [r3, #8]
|
|
80046ea: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmr1 = htim->Instance->CCMR1;
|
|
80046ec: 687b ldr r3, [r7, #4]
|
|
80046ee: 681b ldr r3, [r3, #0]
|
|
80046f0: 699b ldr r3, [r3, #24]
|
|
80046f2: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = htim->Instance->CCER;
|
|
80046f4: 687b ldr r3, [r7, #4]
|
|
80046f6: 681b ldr r3, [r3, #0]
|
|
80046f8: 6a1b ldr r3, [r3, #32]
|
|
80046fa: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the encoder Mode */
|
|
tmpsmcr |= sConfig->EncoderMode;
|
|
80046fc: 683b ldr r3, [r7, #0]
|
|
80046fe: 681b ldr r3, [r3, #0]
|
|
8004700: 697a ldr r2, [r7, #20]
|
|
8004702: 4313 orrs r3, r2
|
|
8004704: 617b str r3, [r7, #20]
|
|
|
|
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
|
|
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
|
|
8004706: 693b ldr r3, [r7, #16]
|
|
8004708: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800470c: f023 0303 bic.w r3, r3, #3
|
|
8004710: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
|
|
8004712: 683b ldr r3, [r7, #0]
|
|
8004714: 689a ldr r2, [r3, #8]
|
|
8004716: 683b ldr r3, [r7, #0]
|
|
8004718: 699b ldr r3, [r3, #24]
|
|
800471a: 021b lsls r3, r3, #8
|
|
800471c: 4313 orrs r3, r2
|
|
800471e: 693a ldr r2, [r7, #16]
|
|
8004720: 4313 orrs r3, r2
|
|
8004722: 613b str r3, [r7, #16]
|
|
|
|
/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
|
|
8004724: 693b ldr r3, [r7, #16]
|
|
8004726: f423 6340 bic.w r3, r3, #3072 @ 0xc00
|
|
800472a: f023 030c bic.w r3, r3, #12
|
|
800472e: 613b str r3, [r7, #16]
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
|
|
8004730: 693b ldr r3, [r7, #16]
|
|
8004732: f423 4370 bic.w r3, r3, #61440 @ 0xf000
|
|
8004736: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
800473a: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
|
|
800473c: 683b ldr r3, [r7, #0]
|
|
800473e: 68da ldr r2, [r3, #12]
|
|
8004740: 683b ldr r3, [r7, #0]
|
|
8004742: 69db ldr r3, [r3, #28]
|
|
8004744: 021b lsls r3, r3, #8
|
|
8004746: 4313 orrs r3, r2
|
|
8004748: 693a ldr r2, [r7, #16]
|
|
800474a: 4313 orrs r3, r2
|
|
800474c: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
|
|
800474e: 683b ldr r3, [r7, #0]
|
|
8004750: 691b ldr r3, [r3, #16]
|
|
8004752: 011a lsls r2, r3, #4
|
|
8004754: 683b ldr r3, [r7, #0]
|
|
8004756: 6a1b ldr r3, [r3, #32]
|
|
8004758: 031b lsls r3, r3, #12
|
|
800475a: 4313 orrs r3, r2
|
|
800475c: 693a ldr r2, [r7, #16]
|
|
800475e: 4313 orrs r3, r2
|
|
8004760: 613b str r3, [r7, #16]
|
|
|
|
/* Set the TI1 and the TI2 Polarities */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
|
|
8004762: 68fb ldr r3, [r7, #12]
|
|
8004764: f023 0322 bic.w r3, r3, #34 @ 0x22
|
|
8004768: 60fb str r3, [r7, #12]
|
|
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
|
|
800476a: 68fb ldr r3, [r7, #12]
|
|
800476c: f023 0388 bic.w r3, r3, #136 @ 0x88
|
|
8004770: 60fb str r3, [r7, #12]
|
|
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
|
|
8004772: 683b ldr r3, [r7, #0]
|
|
8004774: 685a ldr r2, [r3, #4]
|
|
8004776: 683b ldr r3, [r7, #0]
|
|
8004778: 695b ldr r3, [r3, #20]
|
|
800477a: 011b lsls r3, r3, #4
|
|
800477c: 4313 orrs r3, r2
|
|
800477e: 68fa ldr r2, [r7, #12]
|
|
8004780: 4313 orrs r3, r2
|
|
8004782: 60fb str r3, [r7, #12]
|
|
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8004784: 687b ldr r3, [r7, #4]
|
|
8004786: 681b ldr r3, [r3, #0]
|
|
8004788: 697a ldr r2, [r7, #20]
|
|
800478a: 609a str r2, [r3, #8]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
htim->Instance->CCMR1 = tmpccmr1;
|
|
800478c: 687b ldr r3, [r7, #4]
|
|
800478e: 681b ldr r3, [r3, #0]
|
|
8004790: 693a ldr r2, [r7, #16]
|
|
8004792: 619a str r2, [r3, #24]
|
|
|
|
/* Write to TIMx CCER */
|
|
htim->Instance->CCER = tmpccer;
|
|
8004794: 687b ldr r3, [r7, #4]
|
|
8004796: 681b ldr r3, [r3, #0]
|
|
8004798: 68fa ldr r2, [r7, #12]
|
|
800479a: 621a str r2, [r3, #32]
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
800479c: 687b ldr r3, [r7, #4]
|
|
800479e: 2201 movs r2, #1
|
|
80047a0: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Set the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
80047a4: 687b ldr r3, [r7, #4]
|
|
80047a6: 2201 movs r2, #1
|
|
80047a8: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
80047ac: 687b ldr r3, [r7, #4]
|
|
80047ae: 2201 movs r2, #1
|
|
80047b0: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
80047b4: 687b ldr r3, [r7, #4]
|
|
80047b6: 2201 movs r2, #1
|
|
80047b8: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
80047bc: 687b ldr r3, [r7, #4]
|
|
80047be: 2201 movs r2, #1
|
|
80047c0: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80047c4: 687b ldr r3, [r7, #4]
|
|
80047c6: 2201 movs r2, #1
|
|
80047c8: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
80047cc: 2300 movs r3, #0
|
|
}
|
|
80047ce: 4618 mov r0, r3
|
|
80047d0: 3718 adds r7, #24
|
|
80047d2: 46bd mov sp, r7
|
|
80047d4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080047d8 <HAL_TIM_OC_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
const TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
80047d8: b580 push {r7, lr}
|
|
80047da: b086 sub sp, #24
|
|
80047dc: af00 add r7, sp, #0
|
|
80047de: 60f8 str r0, [r7, #12]
|
|
80047e0: 60b9 str r1, [r7, #8]
|
|
80047e2: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80047e4: 2300 movs r3, #0
|
|
80047e6: 75fb strb r3, [r7, #23]
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
80047e8: 68fb ldr r3, [r7, #12]
|
|
80047ea: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
80047ee: 2b01 cmp r3, #1
|
|
80047f0: d101 bne.n 80047f6 <HAL_TIM_OC_ConfigChannel+0x1e>
|
|
80047f2: 2302 movs r3, #2
|
|
80047f4: e048 b.n 8004888 <HAL_TIM_OC_ConfigChannel+0xb0>
|
|
80047f6: 68fb ldr r3, [r7, #12]
|
|
80047f8: 2201 movs r2, #1
|
|
80047fa: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
switch (Channel)
|
|
80047fe: 687b ldr r3, [r7, #4]
|
|
8004800: 2b0c cmp r3, #12
|
|
8004802: d839 bhi.n 8004878 <HAL_TIM_OC_ConfigChannel+0xa0>
|
|
8004804: a201 add r2, pc, #4 @ (adr r2, 800480c <HAL_TIM_OC_ConfigChannel+0x34>)
|
|
8004806: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800480a: bf00 nop
|
|
800480c: 08004841 .word 0x08004841
|
|
8004810: 08004879 .word 0x08004879
|
|
8004814: 08004879 .word 0x08004879
|
|
8004818: 08004879 .word 0x08004879
|
|
800481c: 0800484f .word 0x0800484f
|
|
8004820: 08004879 .word 0x08004879
|
|
8004824: 08004879 .word 0x08004879
|
|
8004828: 08004879 .word 0x08004879
|
|
800482c: 0800485d .word 0x0800485d
|
|
8004830: 08004879 .word 0x08004879
|
|
8004834: 08004879 .word 0x08004879
|
|
8004838: 08004879 .word 0x08004879
|
|
800483c: 0800486b .word 0x0800486b
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 1 in Output Compare */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
8004840: 68fb ldr r3, [r7, #12]
|
|
8004842: 681b ldr r3, [r3, #0]
|
|
8004844: 68b9 ldr r1, [r7, #8]
|
|
8004846: 4618 mov r0, r3
|
|
8004848: f000 f8c8 bl 80049dc <TIM_OC1_SetConfig>
|
|
break;
|
|
800484c: e017 b.n 800487e <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 2 in Output Compare */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
800484e: 68fb ldr r3, [r7, #12]
|
|
8004850: 681b ldr r3, [r3, #0]
|
|
8004852: 68b9 ldr r1, [r7, #8]
|
|
8004854: 4618 mov r0, r3
|
|
8004856: f000 f931 bl 8004abc <TIM_OC2_SetConfig>
|
|
break;
|
|
800485a: e010 b.n 800487e <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 3 in Output Compare */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
800485c: 68fb ldr r3, [r7, #12]
|
|
800485e: 681b ldr r3, [r3, #0]
|
|
8004860: 68b9 ldr r1, [r7, #8]
|
|
8004862: 4618 mov r0, r3
|
|
8004864: f000 f9a0 bl 8004ba8 <TIM_OC3_SetConfig>
|
|
break;
|
|
8004868: e009 b.n 800487e <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 4 in Output Compare */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
800486a: 68fb ldr r3, [r7, #12]
|
|
800486c: 681b ldr r3, [r3, #0]
|
|
800486e: 68b9 ldr r1, [r7, #8]
|
|
8004870: 4618 mov r0, r3
|
|
8004872: f000 fa0d bl 8004c90 <TIM_OC4_SetConfig>
|
|
break;
|
|
8004876: e002 b.n 800487e <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
8004878: 2301 movs r3, #1
|
|
800487a: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800487c: bf00 nop
|
|
}
|
|
|
|
__HAL_UNLOCK(htim);
|
|
800487e: 68fb ldr r3, [r7, #12]
|
|
8004880: 2200 movs r2, #0
|
|
8004882: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
8004886: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8004888: 4618 mov r0, r3
|
|
800488a: 3718 adds r7, #24
|
|
800488c: 46bd mov sp, r7
|
|
800488e: bd80 pop {r7, pc}
|
|
|
|
08004890 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8004890: b480 push {r7}
|
|
8004892: b085 sub sp, #20
|
|
8004894: af00 add r7, sp, #0
|
|
8004896: 6078 str r0, [r7, #4]
|
|
8004898: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
800489a: 687b ldr r3, [r7, #4]
|
|
800489c: 681b ldr r3, [r3, #0]
|
|
800489e: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
80048a0: 687b ldr r3, [r7, #4]
|
|
80048a2: 4a43 ldr r2, [pc, #268] @ (80049b0 <TIM_Base_SetConfig+0x120>)
|
|
80048a4: 4293 cmp r3, r2
|
|
80048a6: d013 beq.n 80048d0 <TIM_Base_SetConfig+0x40>
|
|
80048a8: 687b ldr r3, [r7, #4]
|
|
80048aa: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80048ae: d00f beq.n 80048d0 <TIM_Base_SetConfig+0x40>
|
|
80048b0: 687b ldr r3, [r7, #4]
|
|
80048b2: 4a40 ldr r2, [pc, #256] @ (80049b4 <TIM_Base_SetConfig+0x124>)
|
|
80048b4: 4293 cmp r3, r2
|
|
80048b6: d00b beq.n 80048d0 <TIM_Base_SetConfig+0x40>
|
|
80048b8: 687b ldr r3, [r7, #4]
|
|
80048ba: 4a3f ldr r2, [pc, #252] @ (80049b8 <TIM_Base_SetConfig+0x128>)
|
|
80048bc: 4293 cmp r3, r2
|
|
80048be: d007 beq.n 80048d0 <TIM_Base_SetConfig+0x40>
|
|
80048c0: 687b ldr r3, [r7, #4]
|
|
80048c2: 4a3e ldr r2, [pc, #248] @ (80049bc <TIM_Base_SetConfig+0x12c>)
|
|
80048c4: 4293 cmp r3, r2
|
|
80048c6: d003 beq.n 80048d0 <TIM_Base_SetConfig+0x40>
|
|
80048c8: 687b ldr r3, [r7, #4]
|
|
80048ca: 4a3d ldr r2, [pc, #244] @ (80049c0 <TIM_Base_SetConfig+0x130>)
|
|
80048cc: 4293 cmp r3, r2
|
|
80048ce: d108 bne.n 80048e2 <TIM_Base_SetConfig+0x52>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
80048d0: 68fb ldr r3, [r7, #12]
|
|
80048d2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80048d6: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
80048d8: 683b ldr r3, [r7, #0]
|
|
80048da: 685b ldr r3, [r3, #4]
|
|
80048dc: 68fa ldr r2, [r7, #12]
|
|
80048de: 4313 orrs r3, r2
|
|
80048e0: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80048e2: 687b ldr r3, [r7, #4]
|
|
80048e4: 4a32 ldr r2, [pc, #200] @ (80049b0 <TIM_Base_SetConfig+0x120>)
|
|
80048e6: 4293 cmp r3, r2
|
|
80048e8: d02b beq.n 8004942 <TIM_Base_SetConfig+0xb2>
|
|
80048ea: 687b ldr r3, [r7, #4]
|
|
80048ec: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80048f0: d027 beq.n 8004942 <TIM_Base_SetConfig+0xb2>
|
|
80048f2: 687b ldr r3, [r7, #4]
|
|
80048f4: 4a2f ldr r2, [pc, #188] @ (80049b4 <TIM_Base_SetConfig+0x124>)
|
|
80048f6: 4293 cmp r3, r2
|
|
80048f8: d023 beq.n 8004942 <TIM_Base_SetConfig+0xb2>
|
|
80048fa: 687b ldr r3, [r7, #4]
|
|
80048fc: 4a2e ldr r2, [pc, #184] @ (80049b8 <TIM_Base_SetConfig+0x128>)
|
|
80048fe: 4293 cmp r3, r2
|
|
8004900: d01f beq.n 8004942 <TIM_Base_SetConfig+0xb2>
|
|
8004902: 687b ldr r3, [r7, #4]
|
|
8004904: 4a2d ldr r2, [pc, #180] @ (80049bc <TIM_Base_SetConfig+0x12c>)
|
|
8004906: 4293 cmp r3, r2
|
|
8004908: d01b beq.n 8004942 <TIM_Base_SetConfig+0xb2>
|
|
800490a: 687b ldr r3, [r7, #4]
|
|
800490c: 4a2c ldr r2, [pc, #176] @ (80049c0 <TIM_Base_SetConfig+0x130>)
|
|
800490e: 4293 cmp r3, r2
|
|
8004910: d017 beq.n 8004942 <TIM_Base_SetConfig+0xb2>
|
|
8004912: 687b ldr r3, [r7, #4]
|
|
8004914: 4a2b ldr r2, [pc, #172] @ (80049c4 <TIM_Base_SetConfig+0x134>)
|
|
8004916: 4293 cmp r3, r2
|
|
8004918: d013 beq.n 8004942 <TIM_Base_SetConfig+0xb2>
|
|
800491a: 687b ldr r3, [r7, #4]
|
|
800491c: 4a2a ldr r2, [pc, #168] @ (80049c8 <TIM_Base_SetConfig+0x138>)
|
|
800491e: 4293 cmp r3, r2
|
|
8004920: d00f beq.n 8004942 <TIM_Base_SetConfig+0xb2>
|
|
8004922: 687b ldr r3, [r7, #4]
|
|
8004924: 4a29 ldr r2, [pc, #164] @ (80049cc <TIM_Base_SetConfig+0x13c>)
|
|
8004926: 4293 cmp r3, r2
|
|
8004928: d00b beq.n 8004942 <TIM_Base_SetConfig+0xb2>
|
|
800492a: 687b ldr r3, [r7, #4]
|
|
800492c: 4a28 ldr r2, [pc, #160] @ (80049d0 <TIM_Base_SetConfig+0x140>)
|
|
800492e: 4293 cmp r3, r2
|
|
8004930: d007 beq.n 8004942 <TIM_Base_SetConfig+0xb2>
|
|
8004932: 687b ldr r3, [r7, #4]
|
|
8004934: 4a27 ldr r2, [pc, #156] @ (80049d4 <TIM_Base_SetConfig+0x144>)
|
|
8004936: 4293 cmp r3, r2
|
|
8004938: d003 beq.n 8004942 <TIM_Base_SetConfig+0xb2>
|
|
800493a: 687b ldr r3, [r7, #4]
|
|
800493c: 4a26 ldr r2, [pc, #152] @ (80049d8 <TIM_Base_SetConfig+0x148>)
|
|
800493e: 4293 cmp r3, r2
|
|
8004940: d108 bne.n 8004954 <TIM_Base_SetConfig+0xc4>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
8004942: 68fb ldr r3, [r7, #12]
|
|
8004944: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004948: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
800494a: 683b ldr r3, [r7, #0]
|
|
800494c: 68db ldr r3, [r3, #12]
|
|
800494e: 68fa ldr r2, [r7, #12]
|
|
8004950: 4313 orrs r3, r2
|
|
8004952: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
8004954: 68fb ldr r3, [r7, #12]
|
|
8004956: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
800495a: 683b ldr r3, [r7, #0]
|
|
800495c: 695b ldr r3, [r3, #20]
|
|
800495e: 4313 orrs r3, r2
|
|
8004960: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
8004962: 683b ldr r3, [r7, #0]
|
|
8004964: 689a ldr r2, [r3, #8]
|
|
8004966: 687b ldr r3, [r7, #4]
|
|
8004968: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
800496a: 683b ldr r3, [r7, #0]
|
|
800496c: 681a ldr r2, [r3, #0]
|
|
800496e: 687b ldr r3, [r7, #4]
|
|
8004970: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
8004972: 687b ldr r3, [r7, #4]
|
|
8004974: 4a0e ldr r2, [pc, #56] @ (80049b0 <TIM_Base_SetConfig+0x120>)
|
|
8004976: 4293 cmp r3, r2
|
|
8004978: d003 beq.n 8004982 <TIM_Base_SetConfig+0xf2>
|
|
800497a: 687b ldr r3, [r7, #4]
|
|
800497c: 4a10 ldr r2, [pc, #64] @ (80049c0 <TIM_Base_SetConfig+0x130>)
|
|
800497e: 4293 cmp r3, r2
|
|
8004980: d103 bne.n 800498a <TIM_Base_SetConfig+0xfa>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
8004982: 683b ldr r3, [r7, #0]
|
|
8004984: 691a ldr r2, [r3, #16]
|
|
8004986: 687b ldr r3, [r7, #4]
|
|
8004988: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Disable Update Event (UEV) with Update Generation (UG)
|
|
by changing Update Request Source (URS) to avoid Update flag (UIF) */
|
|
SET_BIT(TIMx->CR1, TIM_CR1_URS);
|
|
800498a: 687b ldr r3, [r7, #4]
|
|
800498c: 681b ldr r3, [r3, #0]
|
|
800498e: f043 0204 orr.w r2, r3, #4
|
|
8004992: 687b ldr r3, [r7, #4]
|
|
8004994: 601a str r2, [r3, #0]
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
8004996: 687b ldr r3, [r7, #4]
|
|
8004998: 2201 movs r2, #1
|
|
800499a: 615a str r2, [r3, #20]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
800499c: 687b ldr r3, [r7, #4]
|
|
800499e: 68fa ldr r2, [r7, #12]
|
|
80049a0: 601a str r2, [r3, #0]
|
|
}
|
|
80049a2: bf00 nop
|
|
80049a4: 3714 adds r7, #20
|
|
80049a6: 46bd mov sp, r7
|
|
80049a8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80049ac: 4770 bx lr
|
|
80049ae: bf00 nop
|
|
80049b0: 40010000 .word 0x40010000
|
|
80049b4: 40000400 .word 0x40000400
|
|
80049b8: 40000800 .word 0x40000800
|
|
80049bc: 40000c00 .word 0x40000c00
|
|
80049c0: 40010400 .word 0x40010400
|
|
80049c4: 40014000 .word 0x40014000
|
|
80049c8: 40014400 .word 0x40014400
|
|
80049cc: 40014800 .word 0x40014800
|
|
80049d0: 40001800 .word 0x40001800
|
|
80049d4: 40001c00 .word 0x40001c00
|
|
80049d8: 40002000 .word 0x40002000
|
|
|
|
080049dc <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
80049dc: b480 push {r7}
|
|
80049de: b087 sub sp, #28
|
|
80049e0: af00 add r7, sp, #0
|
|
80049e2: 6078 str r0, [r7, #4]
|
|
80049e4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
80049e6: 687b ldr r3, [r7, #4]
|
|
80049e8: 6a1b ldr r3, [r3, #32]
|
|
80049ea: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
80049ec: 687b ldr r3, [r7, #4]
|
|
80049ee: 6a1b ldr r3, [r3, #32]
|
|
80049f0: f023 0201 bic.w r2, r3, #1
|
|
80049f4: 687b ldr r3, [r7, #4]
|
|
80049f6: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80049f8: 687b ldr r3, [r7, #4]
|
|
80049fa: 685b ldr r3, [r3, #4]
|
|
80049fc: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
80049fe: 687b ldr r3, [r7, #4]
|
|
8004a00: 699b ldr r3, [r3, #24]
|
|
8004a02: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
8004a04: 68fb ldr r3, [r7, #12]
|
|
8004a06: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8004a0a: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
8004a0c: 68fb ldr r3, [r7, #12]
|
|
8004a0e: f023 0303 bic.w r3, r3, #3
|
|
8004a12: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8004a14: 683b ldr r3, [r7, #0]
|
|
8004a16: 681b ldr r3, [r3, #0]
|
|
8004a18: 68fa ldr r2, [r7, #12]
|
|
8004a1a: 4313 orrs r3, r2
|
|
8004a1c: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
8004a1e: 697b ldr r3, [r7, #20]
|
|
8004a20: f023 0302 bic.w r3, r3, #2
|
|
8004a24: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
8004a26: 683b ldr r3, [r7, #0]
|
|
8004a28: 689b ldr r3, [r3, #8]
|
|
8004a2a: 697a ldr r2, [r7, #20]
|
|
8004a2c: 4313 orrs r3, r2
|
|
8004a2e: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
8004a30: 687b ldr r3, [r7, #4]
|
|
8004a32: 4a20 ldr r2, [pc, #128] @ (8004ab4 <TIM_OC1_SetConfig+0xd8>)
|
|
8004a34: 4293 cmp r3, r2
|
|
8004a36: d003 beq.n 8004a40 <TIM_OC1_SetConfig+0x64>
|
|
8004a38: 687b ldr r3, [r7, #4]
|
|
8004a3a: 4a1f ldr r2, [pc, #124] @ (8004ab8 <TIM_OC1_SetConfig+0xdc>)
|
|
8004a3c: 4293 cmp r3, r2
|
|
8004a3e: d10c bne.n 8004a5a <TIM_OC1_SetConfig+0x7e>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
8004a40: 697b ldr r3, [r7, #20]
|
|
8004a42: f023 0308 bic.w r3, r3, #8
|
|
8004a46: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
8004a48: 683b ldr r3, [r7, #0]
|
|
8004a4a: 68db ldr r3, [r3, #12]
|
|
8004a4c: 697a ldr r2, [r7, #20]
|
|
8004a4e: 4313 orrs r3, r2
|
|
8004a50: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
8004a52: 697b ldr r3, [r7, #20]
|
|
8004a54: f023 0304 bic.w r3, r3, #4
|
|
8004a58: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004a5a: 687b ldr r3, [r7, #4]
|
|
8004a5c: 4a15 ldr r2, [pc, #84] @ (8004ab4 <TIM_OC1_SetConfig+0xd8>)
|
|
8004a5e: 4293 cmp r3, r2
|
|
8004a60: d003 beq.n 8004a6a <TIM_OC1_SetConfig+0x8e>
|
|
8004a62: 687b ldr r3, [r7, #4]
|
|
8004a64: 4a14 ldr r2, [pc, #80] @ (8004ab8 <TIM_OC1_SetConfig+0xdc>)
|
|
8004a66: 4293 cmp r3, r2
|
|
8004a68: d111 bne.n 8004a8e <TIM_OC1_SetConfig+0xb2>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
8004a6a: 693b ldr r3, [r7, #16]
|
|
8004a6c: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8004a70: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
8004a72: 693b ldr r3, [r7, #16]
|
|
8004a74: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
8004a78: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
8004a7a: 683b ldr r3, [r7, #0]
|
|
8004a7c: 695b ldr r3, [r3, #20]
|
|
8004a7e: 693a ldr r2, [r7, #16]
|
|
8004a80: 4313 orrs r3, r2
|
|
8004a82: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
8004a84: 683b ldr r3, [r7, #0]
|
|
8004a86: 699b ldr r3, [r3, #24]
|
|
8004a88: 693a ldr r2, [r7, #16]
|
|
8004a8a: 4313 orrs r3, r2
|
|
8004a8c: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004a8e: 687b ldr r3, [r7, #4]
|
|
8004a90: 693a ldr r2, [r7, #16]
|
|
8004a92: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8004a94: 687b ldr r3, [r7, #4]
|
|
8004a96: 68fa ldr r2, [r7, #12]
|
|
8004a98: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
8004a9a: 683b ldr r3, [r7, #0]
|
|
8004a9c: 685a ldr r2, [r3, #4]
|
|
8004a9e: 687b ldr r3, [r7, #4]
|
|
8004aa0: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004aa2: 687b ldr r3, [r7, #4]
|
|
8004aa4: 697a ldr r2, [r7, #20]
|
|
8004aa6: 621a str r2, [r3, #32]
|
|
}
|
|
8004aa8: bf00 nop
|
|
8004aaa: 371c adds r7, #28
|
|
8004aac: 46bd mov sp, r7
|
|
8004aae: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004ab2: 4770 bx lr
|
|
8004ab4: 40010000 .word 0x40010000
|
|
8004ab8: 40010400 .word 0x40010400
|
|
|
|
08004abc <TIM_OC2_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004abc: b480 push {r7}
|
|
8004abe: b087 sub sp, #28
|
|
8004ac0: af00 add r7, sp, #0
|
|
8004ac2: 6078 str r0, [r7, #4]
|
|
8004ac4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8004ac6: 687b ldr r3, [r7, #4]
|
|
8004ac8: 6a1b ldr r3, [r3, #32]
|
|
8004aca: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8004acc: 687b ldr r3, [r7, #4]
|
|
8004ace: 6a1b ldr r3, [r3, #32]
|
|
8004ad0: f023 0210 bic.w r2, r3, #16
|
|
8004ad4: 687b ldr r3, [r7, #4]
|
|
8004ad6: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8004ad8: 687b ldr r3, [r7, #4]
|
|
8004ada: 685b ldr r3, [r3, #4]
|
|
8004adc: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8004ade: 687b ldr r3, [r7, #4]
|
|
8004ae0: 699b ldr r3, [r3, #24]
|
|
8004ae2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
8004ae4: 68fb ldr r3, [r7, #12]
|
|
8004ae6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8004aea: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
8004aec: 68fb ldr r3, [r7, #12]
|
|
8004aee: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004af2: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8004af4: 683b ldr r3, [r7, #0]
|
|
8004af6: 681b ldr r3, [r3, #0]
|
|
8004af8: 021b lsls r3, r3, #8
|
|
8004afa: 68fa ldr r2, [r7, #12]
|
|
8004afc: 4313 orrs r3, r2
|
|
8004afe: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
8004b00: 697b ldr r3, [r7, #20]
|
|
8004b02: f023 0320 bic.w r3, r3, #32
|
|
8004b06: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
8004b08: 683b ldr r3, [r7, #0]
|
|
8004b0a: 689b ldr r3, [r3, #8]
|
|
8004b0c: 011b lsls r3, r3, #4
|
|
8004b0e: 697a ldr r2, [r7, #20]
|
|
8004b10: 4313 orrs r3, r2
|
|
8004b12: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
8004b14: 687b ldr r3, [r7, #4]
|
|
8004b16: 4a22 ldr r2, [pc, #136] @ (8004ba0 <TIM_OC2_SetConfig+0xe4>)
|
|
8004b18: 4293 cmp r3, r2
|
|
8004b1a: d003 beq.n 8004b24 <TIM_OC2_SetConfig+0x68>
|
|
8004b1c: 687b ldr r3, [r7, #4]
|
|
8004b1e: 4a21 ldr r2, [pc, #132] @ (8004ba4 <TIM_OC2_SetConfig+0xe8>)
|
|
8004b20: 4293 cmp r3, r2
|
|
8004b22: d10d bne.n 8004b40 <TIM_OC2_SetConfig+0x84>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
8004b24: 697b ldr r3, [r7, #20]
|
|
8004b26: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8004b2a: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
8004b2c: 683b ldr r3, [r7, #0]
|
|
8004b2e: 68db ldr r3, [r3, #12]
|
|
8004b30: 011b lsls r3, r3, #4
|
|
8004b32: 697a ldr r2, [r7, #20]
|
|
8004b34: 4313 orrs r3, r2
|
|
8004b36: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
8004b38: 697b ldr r3, [r7, #20]
|
|
8004b3a: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8004b3e: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004b40: 687b ldr r3, [r7, #4]
|
|
8004b42: 4a17 ldr r2, [pc, #92] @ (8004ba0 <TIM_OC2_SetConfig+0xe4>)
|
|
8004b44: 4293 cmp r3, r2
|
|
8004b46: d003 beq.n 8004b50 <TIM_OC2_SetConfig+0x94>
|
|
8004b48: 687b ldr r3, [r7, #4]
|
|
8004b4a: 4a16 ldr r2, [pc, #88] @ (8004ba4 <TIM_OC2_SetConfig+0xe8>)
|
|
8004b4c: 4293 cmp r3, r2
|
|
8004b4e: d113 bne.n 8004b78 <TIM_OC2_SetConfig+0xbc>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
8004b50: 693b ldr r3, [r7, #16]
|
|
8004b52: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8004b56: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
8004b58: 693b ldr r3, [r7, #16]
|
|
8004b5a: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
8004b5e: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
8004b60: 683b ldr r3, [r7, #0]
|
|
8004b62: 695b ldr r3, [r3, #20]
|
|
8004b64: 009b lsls r3, r3, #2
|
|
8004b66: 693a ldr r2, [r7, #16]
|
|
8004b68: 4313 orrs r3, r2
|
|
8004b6a: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
8004b6c: 683b ldr r3, [r7, #0]
|
|
8004b6e: 699b ldr r3, [r3, #24]
|
|
8004b70: 009b lsls r3, r3, #2
|
|
8004b72: 693a ldr r2, [r7, #16]
|
|
8004b74: 4313 orrs r3, r2
|
|
8004b76: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004b78: 687b ldr r3, [r7, #4]
|
|
8004b7a: 693a ldr r2, [r7, #16]
|
|
8004b7c: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8004b7e: 687b ldr r3, [r7, #4]
|
|
8004b80: 68fa ldr r2, [r7, #12]
|
|
8004b82: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
8004b84: 683b ldr r3, [r7, #0]
|
|
8004b86: 685a ldr r2, [r3, #4]
|
|
8004b88: 687b ldr r3, [r7, #4]
|
|
8004b8a: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004b8c: 687b ldr r3, [r7, #4]
|
|
8004b8e: 697a ldr r2, [r7, #20]
|
|
8004b90: 621a str r2, [r3, #32]
|
|
}
|
|
8004b92: bf00 nop
|
|
8004b94: 371c adds r7, #28
|
|
8004b96: 46bd mov sp, r7
|
|
8004b98: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004b9c: 4770 bx lr
|
|
8004b9e: bf00 nop
|
|
8004ba0: 40010000 .word 0x40010000
|
|
8004ba4: 40010400 .word 0x40010400
|
|
|
|
08004ba8 <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004ba8: b480 push {r7}
|
|
8004baa: b087 sub sp, #28
|
|
8004bac: af00 add r7, sp, #0
|
|
8004bae: 6078 str r0, [r7, #4]
|
|
8004bb0: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8004bb2: 687b ldr r3, [r7, #4]
|
|
8004bb4: 6a1b ldr r3, [r3, #32]
|
|
8004bb6: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
8004bb8: 687b ldr r3, [r7, #4]
|
|
8004bba: 6a1b ldr r3, [r3, #32]
|
|
8004bbc: f423 7280 bic.w r2, r3, #256 @ 0x100
|
|
8004bc0: 687b ldr r3, [r7, #4]
|
|
8004bc2: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8004bc4: 687b ldr r3, [r7, #4]
|
|
8004bc6: 685b ldr r3, [r3, #4]
|
|
8004bc8: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8004bca: 687b ldr r3, [r7, #4]
|
|
8004bcc: 69db ldr r3, [r3, #28]
|
|
8004bce: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
8004bd0: 68fb ldr r3, [r7, #12]
|
|
8004bd2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8004bd6: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
8004bd8: 68fb ldr r3, [r7, #12]
|
|
8004bda: f023 0303 bic.w r3, r3, #3
|
|
8004bde: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8004be0: 683b ldr r3, [r7, #0]
|
|
8004be2: 681b ldr r3, [r3, #0]
|
|
8004be4: 68fa ldr r2, [r7, #12]
|
|
8004be6: 4313 orrs r3, r2
|
|
8004be8: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
8004bea: 697b ldr r3, [r7, #20]
|
|
8004bec: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
8004bf0: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
8004bf2: 683b ldr r3, [r7, #0]
|
|
8004bf4: 689b ldr r3, [r3, #8]
|
|
8004bf6: 021b lsls r3, r3, #8
|
|
8004bf8: 697a ldr r2, [r7, #20]
|
|
8004bfa: 4313 orrs r3, r2
|
|
8004bfc: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
8004bfe: 687b ldr r3, [r7, #4]
|
|
8004c00: 4a21 ldr r2, [pc, #132] @ (8004c88 <TIM_OC3_SetConfig+0xe0>)
|
|
8004c02: 4293 cmp r3, r2
|
|
8004c04: d003 beq.n 8004c0e <TIM_OC3_SetConfig+0x66>
|
|
8004c06: 687b ldr r3, [r7, #4]
|
|
8004c08: 4a20 ldr r2, [pc, #128] @ (8004c8c <TIM_OC3_SetConfig+0xe4>)
|
|
8004c0a: 4293 cmp r3, r2
|
|
8004c0c: d10d bne.n 8004c2a <TIM_OC3_SetConfig+0x82>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
8004c0e: 697b ldr r3, [r7, #20]
|
|
8004c10: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
8004c14: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
8004c16: 683b ldr r3, [r7, #0]
|
|
8004c18: 68db ldr r3, [r3, #12]
|
|
8004c1a: 021b lsls r3, r3, #8
|
|
8004c1c: 697a ldr r2, [r7, #20]
|
|
8004c1e: 4313 orrs r3, r2
|
|
8004c20: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
8004c22: 697b ldr r3, [r7, #20]
|
|
8004c24: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8004c28: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004c2a: 687b ldr r3, [r7, #4]
|
|
8004c2c: 4a16 ldr r2, [pc, #88] @ (8004c88 <TIM_OC3_SetConfig+0xe0>)
|
|
8004c2e: 4293 cmp r3, r2
|
|
8004c30: d003 beq.n 8004c3a <TIM_OC3_SetConfig+0x92>
|
|
8004c32: 687b ldr r3, [r7, #4]
|
|
8004c34: 4a15 ldr r2, [pc, #84] @ (8004c8c <TIM_OC3_SetConfig+0xe4>)
|
|
8004c36: 4293 cmp r3, r2
|
|
8004c38: d113 bne.n 8004c62 <TIM_OC3_SetConfig+0xba>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
8004c3a: 693b ldr r3, [r7, #16]
|
|
8004c3c: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
8004c40: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
8004c42: 693b ldr r3, [r7, #16]
|
|
8004c44: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
8004c48: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
8004c4a: 683b ldr r3, [r7, #0]
|
|
8004c4c: 695b ldr r3, [r3, #20]
|
|
8004c4e: 011b lsls r3, r3, #4
|
|
8004c50: 693a ldr r2, [r7, #16]
|
|
8004c52: 4313 orrs r3, r2
|
|
8004c54: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
8004c56: 683b ldr r3, [r7, #0]
|
|
8004c58: 699b ldr r3, [r3, #24]
|
|
8004c5a: 011b lsls r3, r3, #4
|
|
8004c5c: 693a ldr r2, [r7, #16]
|
|
8004c5e: 4313 orrs r3, r2
|
|
8004c60: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004c62: 687b ldr r3, [r7, #4]
|
|
8004c64: 693a ldr r2, [r7, #16]
|
|
8004c66: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8004c68: 687b ldr r3, [r7, #4]
|
|
8004c6a: 68fa ldr r2, [r7, #12]
|
|
8004c6c: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
8004c6e: 683b ldr r3, [r7, #0]
|
|
8004c70: 685a ldr r2, [r3, #4]
|
|
8004c72: 687b ldr r3, [r7, #4]
|
|
8004c74: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004c76: 687b ldr r3, [r7, #4]
|
|
8004c78: 697a ldr r2, [r7, #20]
|
|
8004c7a: 621a str r2, [r3, #32]
|
|
}
|
|
8004c7c: bf00 nop
|
|
8004c7e: 371c adds r7, #28
|
|
8004c80: 46bd mov sp, r7
|
|
8004c82: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004c86: 4770 bx lr
|
|
8004c88: 40010000 .word 0x40010000
|
|
8004c8c: 40010400 .word 0x40010400
|
|
|
|
08004c90 <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004c90: b480 push {r7}
|
|
8004c92: b087 sub sp, #28
|
|
8004c94: af00 add r7, sp, #0
|
|
8004c96: 6078 str r0, [r7, #4]
|
|
8004c98: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8004c9a: 687b ldr r3, [r7, #4]
|
|
8004c9c: 6a1b ldr r3, [r3, #32]
|
|
8004c9e: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
8004ca0: 687b ldr r3, [r7, #4]
|
|
8004ca2: 6a1b ldr r3, [r3, #32]
|
|
8004ca4: f423 5280 bic.w r2, r3, #4096 @ 0x1000
|
|
8004ca8: 687b ldr r3, [r7, #4]
|
|
8004caa: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8004cac: 687b ldr r3, [r7, #4]
|
|
8004cae: 685b ldr r3, [r3, #4]
|
|
8004cb0: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8004cb2: 687b ldr r3, [r7, #4]
|
|
8004cb4: 69db ldr r3, [r3, #28]
|
|
8004cb6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
8004cb8: 68fb ldr r3, [r7, #12]
|
|
8004cba: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8004cbe: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
8004cc0: 68fb ldr r3, [r7, #12]
|
|
8004cc2: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004cc6: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8004cc8: 683b ldr r3, [r7, #0]
|
|
8004cca: 681b ldr r3, [r3, #0]
|
|
8004ccc: 021b lsls r3, r3, #8
|
|
8004cce: 68fa ldr r2, [r7, #12]
|
|
8004cd0: 4313 orrs r3, r2
|
|
8004cd2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
8004cd4: 693b ldr r3, [r7, #16]
|
|
8004cd6: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
8004cda: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
8004cdc: 683b ldr r3, [r7, #0]
|
|
8004cde: 689b ldr r3, [r3, #8]
|
|
8004ce0: 031b lsls r3, r3, #12
|
|
8004ce2: 693a ldr r2, [r7, #16]
|
|
8004ce4: 4313 orrs r3, r2
|
|
8004ce6: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004ce8: 687b ldr r3, [r7, #4]
|
|
8004cea: 4a12 ldr r2, [pc, #72] @ (8004d34 <TIM_OC4_SetConfig+0xa4>)
|
|
8004cec: 4293 cmp r3, r2
|
|
8004cee: d003 beq.n 8004cf8 <TIM_OC4_SetConfig+0x68>
|
|
8004cf0: 687b ldr r3, [r7, #4]
|
|
8004cf2: 4a11 ldr r2, [pc, #68] @ (8004d38 <TIM_OC4_SetConfig+0xa8>)
|
|
8004cf4: 4293 cmp r3, r2
|
|
8004cf6: d109 bne.n 8004d0c <TIM_OC4_SetConfig+0x7c>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
8004cf8: 697b ldr r3, [r7, #20]
|
|
8004cfa: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8004cfe: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
8004d00: 683b ldr r3, [r7, #0]
|
|
8004d02: 695b ldr r3, [r3, #20]
|
|
8004d04: 019b lsls r3, r3, #6
|
|
8004d06: 697a ldr r2, [r7, #20]
|
|
8004d08: 4313 orrs r3, r2
|
|
8004d0a: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004d0c: 687b ldr r3, [r7, #4]
|
|
8004d0e: 697a ldr r2, [r7, #20]
|
|
8004d10: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8004d12: 687b ldr r3, [r7, #4]
|
|
8004d14: 68fa ldr r2, [r7, #12]
|
|
8004d16: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
8004d18: 683b ldr r3, [r7, #0]
|
|
8004d1a: 685a ldr r2, [r3, #4]
|
|
8004d1c: 687b ldr r3, [r7, #4]
|
|
8004d1e: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004d20: 687b ldr r3, [r7, #4]
|
|
8004d22: 693a ldr r2, [r7, #16]
|
|
8004d24: 621a str r2, [r3, #32]
|
|
}
|
|
8004d26: bf00 nop
|
|
8004d28: 371c adds r7, #28
|
|
8004d2a: 46bd mov sp, r7
|
|
8004d2c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004d30: 4770 bx lr
|
|
8004d32: bf00 nop
|
|
8004d34: 40010000 .word 0x40010000
|
|
8004d38: 40010400 .word 0x40010400
|
|
|
|
08004d3c <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
8004d3c: b480 push {r7}
|
|
8004d3e: b085 sub sp, #20
|
|
8004d40: af00 add r7, sp, #0
|
|
8004d42: 6078 str r0, [r7, #4]
|
|
8004d44: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8004d46: 687b ldr r3, [r7, #4]
|
|
8004d48: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8004d4c: 2b01 cmp r3, #1
|
|
8004d4e: d101 bne.n 8004d54 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8004d50: 2302 movs r3, #2
|
|
8004d52: e05a b.n 8004e0a <HAL_TIMEx_MasterConfigSynchronization+0xce>
|
|
8004d54: 687b ldr r3, [r7, #4]
|
|
8004d56: 2201 movs r2, #1
|
|
8004d58: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8004d5c: 687b ldr r3, [r7, #4]
|
|
8004d5e: 2202 movs r2, #2
|
|
8004d60: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8004d64: 687b ldr r3, [r7, #4]
|
|
8004d66: 681b ldr r3, [r3, #0]
|
|
8004d68: 685b ldr r3, [r3, #4]
|
|
8004d6a: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8004d6c: 687b ldr r3, [r7, #4]
|
|
8004d6e: 681b ldr r3, [r3, #0]
|
|
8004d70: 689b ldr r3, [r3, #8]
|
|
8004d72: 60bb str r3, [r7, #8]
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8004d74: 68fb ldr r3, [r7, #12]
|
|
8004d76: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8004d7a: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8004d7c: 683b ldr r3, [r7, #0]
|
|
8004d7e: 681b ldr r3, [r3, #0]
|
|
8004d80: 68fa ldr r2, [r7, #12]
|
|
8004d82: 4313 orrs r3, r2
|
|
8004d84: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8004d86: 687b ldr r3, [r7, #4]
|
|
8004d88: 681b ldr r3, [r3, #0]
|
|
8004d8a: 68fa ldr r2, [r7, #12]
|
|
8004d8c: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8004d8e: 687b ldr r3, [r7, #4]
|
|
8004d90: 681b ldr r3, [r3, #0]
|
|
8004d92: 4a21 ldr r2, [pc, #132] @ (8004e18 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
|
|
8004d94: 4293 cmp r3, r2
|
|
8004d96: d022 beq.n 8004dde <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004d98: 687b ldr r3, [r7, #4]
|
|
8004d9a: 681b ldr r3, [r3, #0]
|
|
8004d9c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8004da0: d01d beq.n 8004dde <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004da2: 687b ldr r3, [r7, #4]
|
|
8004da4: 681b ldr r3, [r3, #0]
|
|
8004da6: 4a1d ldr r2, [pc, #116] @ (8004e1c <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
|
|
8004da8: 4293 cmp r3, r2
|
|
8004daa: d018 beq.n 8004dde <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004dac: 687b ldr r3, [r7, #4]
|
|
8004dae: 681b ldr r3, [r3, #0]
|
|
8004db0: 4a1b ldr r2, [pc, #108] @ (8004e20 <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
|
|
8004db2: 4293 cmp r3, r2
|
|
8004db4: d013 beq.n 8004dde <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004db6: 687b ldr r3, [r7, #4]
|
|
8004db8: 681b ldr r3, [r3, #0]
|
|
8004dba: 4a1a ldr r2, [pc, #104] @ (8004e24 <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
|
|
8004dbc: 4293 cmp r3, r2
|
|
8004dbe: d00e beq.n 8004dde <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004dc0: 687b ldr r3, [r7, #4]
|
|
8004dc2: 681b ldr r3, [r3, #0]
|
|
8004dc4: 4a18 ldr r2, [pc, #96] @ (8004e28 <HAL_TIMEx_MasterConfigSynchronization+0xec>)
|
|
8004dc6: 4293 cmp r3, r2
|
|
8004dc8: d009 beq.n 8004dde <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004dca: 687b ldr r3, [r7, #4]
|
|
8004dcc: 681b ldr r3, [r3, #0]
|
|
8004dce: 4a17 ldr r2, [pc, #92] @ (8004e2c <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
|
|
8004dd0: 4293 cmp r3, r2
|
|
8004dd2: d004 beq.n 8004dde <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004dd4: 687b ldr r3, [r7, #4]
|
|
8004dd6: 681b ldr r3, [r3, #0]
|
|
8004dd8: 4a15 ldr r2, [pc, #84] @ (8004e30 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
|
|
8004dda: 4293 cmp r3, r2
|
|
8004ddc: d10c bne.n 8004df8 <HAL_TIMEx_MasterConfigSynchronization+0xbc>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
8004dde: 68bb ldr r3, [r7, #8]
|
|
8004de0: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8004de4: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
8004de6: 683b ldr r3, [r7, #0]
|
|
8004de8: 685b ldr r3, [r3, #4]
|
|
8004dea: 68ba ldr r2, [r7, #8]
|
|
8004dec: 4313 orrs r3, r2
|
|
8004dee: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8004df0: 687b ldr r3, [r7, #4]
|
|
8004df2: 681b ldr r3, [r3, #0]
|
|
8004df4: 68ba ldr r2, [r7, #8]
|
|
8004df6: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8004df8: 687b ldr r3, [r7, #4]
|
|
8004dfa: 2201 movs r2, #1
|
|
8004dfc: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8004e00: 687b ldr r3, [r7, #4]
|
|
8004e02: 2200 movs r2, #0
|
|
8004e04: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
8004e08: 2300 movs r3, #0
|
|
}
|
|
8004e0a: 4618 mov r0, r3
|
|
8004e0c: 3714 adds r7, #20
|
|
8004e0e: 46bd mov sp, r7
|
|
8004e10: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004e14: 4770 bx lr
|
|
8004e16: bf00 nop
|
|
8004e18: 40010000 .word 0x40010000
|
|
8004e1c: 40000400 .word 0x40000400
|
|
8004e20: 40000800 .word 0x40000800
|
|
8004e24: 40000c00 .word 0x40000c00
|
|
8004e28: 40010400 .word 0x40010400
|
|
8004e2c: 40014000 .word 0x40014000
|
|
8004e30: 40001800 .word 0x40001800
|
|
|
|
08004e34 <HAL_UART_Init>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8004e34: b580 push {r7, lr}
|
|
8004e36: b082 sub sp, #8
|
|
8004e38: af00 add r7, sp, #0
|
|
8004e3a: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8004e3c: 687b ldr r3, [r7, #4]
|
|
8004e3e: 2b00 cmp r3, #0
|
|
8004e40: d101 bne.n 8004e46 <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004e42: 2301 movs r3, #1
|
|
8004e44: e042 b.n 8004ecc <HAL_UART_Init+0x98>
|
|
assert_param(IS_UART_INSTANCE(huart->Instance));
|
|
}
|
|
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
|
|
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8004e46: 687b ldr r3, [r7, #4]
|
|
8004e48: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8004e4c: b2db uxtb r3, r3
|
|
8004e4e: 2b00 cmp r3, #0
|
|
8004e50: d106 bne.n 8004e60 <HAL_UART_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8004e52: 687b ldr r3, [r7, #4]
|
|
8004e54: 2200 movs r2, #0
|
|
8004e56: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8004e5a: 6878 ldr r0, [r7, #4]
|
|
8004e5c: f7fc f944 bl 80010e8 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8004e60: 687b ldr r3, [r7, #4]
|
|
8004e62: 2224 movs r2, #36 @ 0x24
|
|
8004e64: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_UART_DISABLE(huart);
|
|
8004e68: 687b ldr r3, [r7, #4]
|
|
8004e6a: 681b ldr r3, [r3, #0]
|
|
8004e6c: 68da ldr r2, [r3, #12]
|
|
8004e6e: 687b ldr r3, [r7, #4]
|
|
8004e70: 681b ldr r3, [r3, #0]
|
|
8004e72: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
8004e76: 60da str r2, [r3, #12]
|
|
|
|
/* Set the UART Communication parameters */
|
|
UART_SetConfig(huart);
|
|
8004e78: 6878 ldr r0, [r7, #4]
|
|
8004e7a: f000 fb8b bl 8005594 <UART_SetConfig>
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8004e7e: 687b ldr r3, [r7, #4]
|
|
8004e80: 681b ldr r3, [r3, #0]
|
|
8004e82: 691a ldr r2, [r3, #16]
|
|
8004e84: 687b ldr r3, [r7, #4]
|
|
8004e86: 681b ldr r3, [r3, #0]
|
|
8004e88: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
8004e8c: 611a str r2, [r3, #16]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8004e8e: 687b ldr r3, [r7, #4]
|
|
8004e90: 681b ldr r3, [r3, #0]
|
|
8004e92: 695a ldr r2, [r3, #20]
|
|
8004e94: 687b ldr r3, [r7, #4]
|
|
8004e96: 681b ldr r3, [r3, #0]
|
|
8004e98: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
8004e9c: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the peripheral */
|
|
__HAL_UART_ENABLE(huart);
|
|
8004e9e: 687b ldr r3, [r7, #4]
|
|
8004ea0: 681b ldr r3, [r3, #0]
|
|
8004ea2: 68da ldr r2, [r3, #12]
|
|
8004ea4: 687b ldr r3, [r7, #4]
|
|
8004ea6: 681b ldr r3, [r3, #0]
|
|
8004ea8: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
8004eac: 60da str r2, [r3, #12]
|
|
|
|
/* Initialize the UART state */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004eae: 687b ldr r3, [r7, #4]
|
|
8004eb0: 2200 movs r2, #0
|
|
8004eb2: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004eb4: 687b ldr r3, [r7, #4]
|
|
8004eb6: 2220 movs r2, #32
|
|
8004eb8: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004ebc: 687b ldr r3, [r7, #4]
|
|
8004ebe: 2220 movs r2, #32
|
|
8004ec0: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8004ec4: 687b ldr r3, [r7, #4]
|
|
8004ec6: 2200 movs r2, #0
|
|
8004ec8: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_OK;
|
|
8004eca: 2300 movs r3, #0
|
|
}
|
|
8004ecc: 4618 mov r0, r3
|
|
8004ece: 3708 adds r7, #8
|
|
8004ed0: 46bd mov sp, r7
|
|
8004ed2: bd80 pop {r7, pc}
|
|
|
|
08004ed4 <HAL_UART_Transmit_DMA>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
|
|
{
|
|
8004ed4: b580 push {r7, lr}
|
|
8004ed6: b08c sub sp, #48 @ 0x30
|
|
8004ed8: af00 add r7, sp, #0
|
|
8004eda: 60f8 str r0, [r7, #12]
|
|
8004edc: 60b9 str r1, [r7, #8]
|
|
8004ede: 4613 mov r3, r2
|
|
8004ee0: 80fb strh r3, [r7, #6]
|
|
const uint32_t *tmp;
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8004ee2: 68fb ldr r3, [r7, #12]
|
|
8004ee4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8004ee8: b2db uxtb r3, r3
|
|
8004eea: 2b20 cmp r3, #32
|
|
8004eec: d162 bne.n 8004fb4 <HAL_UART_Transmit_DMA+0xe0>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8004eee: 68bb ldr r3, [r7, #8]
|
|
8004ef0: 2b00 cmp r3, #0
|
|
8004ef2: d002 beq.n 8004efa <HAL_UART_Transmit_DMA+0x26>
|
|
8004ef4: 88fb ldrh r3, [r7, #6]
|
|
8004ef6: 2b00 cmp r3, #0
|
|
8004ef8: d101 bne.n 8004efe <HAL_UART_Transmit_DMA+0x2a>
|
|
{
|
|
return HAL_ERROR;
|
|
8004efa: 2301 movs r3, #1
|
|
8004efc: e05b b.n 8004fb6 <HAL_UART_Transmit_DMA+0xe2>
|
|
}
|
|
|
|
huart->pTxBuffPtr = pData;
|
|
8004efe: 68ba ldr r2, [r7, #8]
|
|
8004f00: 68fb ldr r3, [r7, #12]
|
|
8004f02: 621a str r2, [r3, #32]
|
|
huart->TxXferSize = Size;
|
|
8004f04: 68fb ldr r3, [r7, #12]
|
|
8004f06: 88fa ldrh r2, [r7, #6]
|
|
8004f08: 849a strh r2, [r3, #36] @ 0x24
|
|
huart->TxXferCount = Size;
|
|
8004f0a: 68fb ldr r3, [r7, #12]
|
|
8004f0c: 88fa ldrh r2, [r7, #6]
|
|
8004f0e: 84da strh r2, [r3, #38] @ 0x26
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004f10: 68fb ldr r3, [r7, #12]
|
|
8004f12: 2200 movs r2, #0
|
|
8004f14: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
8004f16: 68fb ldr r3, [r7, #12]
|
|
8004f18: 2221 movs r2, #33 @ 0x21
|
|
8004f1a: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Set the UART DMA transfer complete callback */
|
|
huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
|
|
8004f1e: 68fb ldr r3, [r7, #12]
|
|
8004f20: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004f22: 4a27 ldr r2, [pc, #156] @ (8004fc0 <HAL_UART_Transmit_DMA+0xec>)
|
|
8004f24: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Set the UART DMA Half transfer complete callback */
|
|
huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
|
|
8004f26: 68fb ldr r3, [r7, #12]
|
|
8004f28: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004f2a: 4a26 ldr r2, [pc, #152] @ (8004fc4 <HAL_UART_Transmit_DMA+0xf0>)
|
|
8004f2c: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set the DMA error callback */
|
|
huart->hdmatx->XferErrorCallback = UART_DMAError;
|
|
8004f2e: 68fb ldr r3, [r7, #12]
|
|
8004f30: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004f32: 4a25 ldr r2, [pc, #148] @ (8004fc8 <HAL_UART_Transmit_DMA+0xf4>)
|
|
8004f34: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Set the DMA abort callback */
|
|
huart->hdmatx->XferAbortCallback = NULL;
|
|
8004f36: 68fb ldr r3, [r7, #12]
|
|
8004f38: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004f3a: 2200 movs r2, #0
|
|
8004f3c: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Enable the UART transmit DMA stream */
|
|
tmp = (const uint32_t *)&pData;
|
|
8004f3e: f107 0308 add.w r3, r7, #8
|
|
8004f42: 62fb str r3, [r7, #44] @ 0x2c
|
|
if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK)
|
|
8004f44: 68fb ldr r3, [r7, #12]
|
|
8004f46: 6b98 ldr r0, [r3, #56] @ 0x38
|
|
8004f48: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8004f4a: 6819 ldr r1, [r3, #0]
|
|
8004f4c: 68fb ldr r3, [r7, #12]
|
|
8004f4e: 681b ldr r3, [r3, #0]
|
|
8004f50: 3304 adds r3, #4
|
|
8004f52: 461a mov r2, r3
|
|
8004f54: 88fb ldrh r3, [r7, #6]
|
|
8004f56: f7fc fc20 bl 800179a <HAL_DMA_Start_IT>
|
|
8004f5a: 4603 mov r3, r0
|
|
8004f5c: 2b00 cmp r3, #0
|
|
8004f5e: d008 beq.n 8004f72 <HAL_UART_Transmit_DMA+0x9e>
|
|
{
|
|
/* Set error code to DMA */
|
|
huart->ErrorCode = HAL_UART_ERROR_DMA;
|
|
8004f60: 68fb ldr r3, [r7, #12]
|
|
8004f62: 2210 movs r2, #16
|
|
8004f64: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Restore huart->gState to ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004f66: 68fb ldr r3, [r7, #12]
|
|
8004f68: 2220 movs r2, #32
|
|
8004f6a: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
return HAL_ERROR;
|
|
8004f6e: 2301 movs r3, #1
|
|
8004f70: e021 b.n 8004fb6 <HAL_UART_Transmit_DMA+0xe2>
|
|
}
|
|
/* Clear the TC flag in the SR register by writing 0 to it */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
|
|
8004f72: 68fb ldr r3, [r7, #12]
|
|
8004f74: 681b ldr r3, [r3, #0]
|
|
8004f76: f06f 0240 mvn.w r2, #64 @ 0x40
|
|
8004f7a: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the DMA transfer for transmit request by setting the DMAT bit
|
|
in the UART CR3 register */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
|
8004f7c: 68fb ldr r3, [r7, #12]
|
|
8004f7e: 681b ldr r3, [r3, #0]
|
|
8004f80: 3314 adds r3, #20
|
|
8004f82: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004f84: 69bb ldr r3, [r7, #24]
|
|
8004f86: e853 3f00 ldrex r3, [r3]
|
|
8004f8a: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8004f8c: 697b ldr r3, [r7, #20]
|
|
8004f8e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8004f92: 62bb str r3, [r7, #40] @ 0x28
|
|
8004f94: 68fb ldr r3, [r7, #12]
|
|
8004f96: 681b ldr r3, [r3, #0]
|
|
8004f98: 3314 adds r3, #20
|
|
8004f9a: 6aba ldr r2, [r7, #40] @ 0x28
|
|
8004f9c: 627a str r2, [r7, #36] @ 0x24
|
|
8004f9e: 623b str r3, [r7, #32]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004fa0: 6a39 ldr r1, [r7, #32]
|
|
8004fa2: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8004fa4: e841 2300 strex r3, r2, [r1]
|
|
8004fa8: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8004faa: 69fb ldr r3, [r7, #28]
|
|
8004fac: 2b00 cmp r3, #0
|
|
8004fae: d1e5 bne.n 8004f7c <HAL_UART_Transmit_DMA+0xa8>
|
|
|
|
return HAL_OK;
|
|
8004fb0: 2300 movs r3, #0
|
|
8004fb2: e000 b.n 8004fb6 <HAL_UART_Transmit_DMA+0xe2>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004fb4: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004fb6: 4618 mov r0, r3
|
|
8004fb8: 3730 adds r7, #48 @ 0x30
|
|
8004fba: 46bd mov sp, r7
|
|
8004fbc: bd80 pop {r7, pc}
|
|
8004fbe: bf00 nop
|
|
8004fc0: 0800507f .word 0x0800507f
|
|
8004fc4: 08005119 .word 0x08005119
|
|
8004fc8: 0800529d .word 0x0800529d
|
|
|
|
08004fcc <HAL_UART_Receive_DMA>:
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
8004fcc: b580 push {r7, lr}
|
|
8004fce: b084 sub sp, #16
|
|
8004fd0: af00 add r7, sp, #0
|
|
8004fd2: 60f8 str r0, [r7, #12]
|
|
8004fd4: 60b9 str r1, [r7, #8]
|
|
8004fd6: 4613 mov r3, r2
|
|
8004fd8: 80fb strh r3, [r7, #6]
|
|
/* Check that a Rx process is not already ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
8004fda: 68fb ldr r3, [r7, #12]
|
|
8004fdc: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
8004fe0: b2db uxtb r3, r3
|
|
8004fe2: 2b20 cmp r3, #32
|
|
8004fe4: d112 bne.n 800500c <HAL_UART_Receive_DMA+0x40>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8004fe6: 68bb ldr r3, [r7, #8]
|
|
8004fe8: 2b00 cmp r3, #0
|
|
8004fea: d002 beq.n 8004ff2 <HAL_UART_Receive_DMA+0x26>
|
|
8004fec: 88fb ldrh r3, [r7, #6]
|
|
8004fee: 2b00 cmp r3, #0
|
|
8004ff0: d101 bne.n 8004ff6 <HAL_UART_Receive_DMA+0x2a>
|
|
{
|
|
return HAL_ERROR;
|
|
8004ff2: 2301 movs r3, #1
|
|
8004ff4: e00b b.n 800500e <HAL_UART_Receive_DMA+0x42>
|
|
}
|
|
|
|
/* Set Reception type to Standard reception */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004ff6: 68fb ldr r3, [r7, #12]
|
|
8004ff8: 2200 movs r2, #0
|
|
8004ffa: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
return (UART_Start_Receive_DMA(huart, pData, Size));
|
|
8004ffc: 88fb ldrh r3, [r7, #6]
|
|
8004ffe: 461a mov r2, r3
|
|
8005000: 68b9 ldr r1, [r7, #8]
|
|
8005002: 68f8 ldr r0, [r7, #12]
|
|
8005004: f000 f994 bl 8005330 <UART_Start_Receive_DMA>
|
|
8005008: 4603 mov r3, r0
|
|
800500a: e000 b.n 800500e <HAL_UART_Receive_DMA+0x42>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
800500c: 2302 movs r3, #2
|
|
}
|
|
}
|
|
800500e: 4618 mov r0, r3
|
|
8005010: 3710 adds r7, #16
|
|
8005012: 46bd mov sp, r7
|
|
8005014: bd80 pop {r7, pc}
|
|
|
|
08005016 <HAL_UART_TxCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8005016: b480 push {r7}
|
|
8005018: b083 sub sp, #12
|
|
800501a: af00 add r7, sp, #0
|
|
800501c: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800501e: bf00 nop
|
|
8005020: 370c adds r7, #12
|
|
8005022: 46bd mov sp, r7
|
|
8005024: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005028: 4770 bx lr
|
|
|
|
0800502a <HAL_UART_TxHalfCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800502a: b480 push {r7}
|
|
800502c: b083 sub sp, #12
|
|
800502e: af00 add r7, sp, #0
|
|
8005030: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxHalfCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005032: bf00 nop
|
|
8005034: 370c adds r7, #12
|
|
8005036: 46bd mov sp, r7
|
|
8005038: f85d 7b04 ldr.w r7, [sp], #4
|
|
800503c: 4770 bx lr
|
|
|
|
0800503e <HAL_UART_RxHalfCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800503e: b480 push {r7}
|
|
8005040: b083 sub sp, #12
|
|
8005042: af00 add r7, sp, #0
|
|
8005044: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_RxHalfCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005046: bf00 nop
|
|
8005048: 370c adds r7, #12
|
|
800504a: 46bd mov sp, r7
|
|
800504c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005050: 4770 bx lr
|
|
|
|
08005052 <HAL_UART_ErrorCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8005052: b480 push {r7}
|
|
8005054: b083 sub sp, #12
|
|
8005056: af00 add r7, sp, #0
|
|
8005058: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_ErrorCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800505a: bf00 nop
|
|
800505c: 370c adds r7, #12
|
|
800505e: 46bd mov sp, r7
|
|
8005060: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005064: 4770 bx lr
|
|
|
|
08005066 <HAL_UARTEx_RxEventCallback>:
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
|
* reception buffer until which, data are available)
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|
{
|
|
8005066: b480 push {r7}
|
|
8005068: b083 sub sp, #12
|
|
800506a: af00 add r7, sp, #0
|
|
800506c: 6078 str r0, [r7, #4]
|
|
800506e: 460b mov r3, r1
|
|
8005070: 807b strh r3, [r7, #2]
|
|
UNUSED(Size);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8005072: bf00 nop
|
|
8005074: 370c adds r7, #12
|
|
8005076: 46bd mov sp, r7
|
|
8005078: f85d 7b04 ldr.w r7, [sp], #4
|
|
800507c: 4770 bx lr
|
|
|
|
0800507e <UART_DMATransmitCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800507e: b580 push {r7, lr}
|
|
8005080: b090 sub sp, #64 @ 0x40
|
|
8005082: af00 add r7, sp, #0
|
|
8005084: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
8005086: 687b ldr r3, [r7, #4]
|
|
8005088: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800508a: 63fb str r3, [r7, #60] @ 0x3c
|
|
/* DMA Normal mode*/
|
|
if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
|
|
800508c: 687b ldr r3, [r7, #4]
|
|
800508e: 681b ldr r3, [r3, #0]
|
|
8005090: 681b ldr r3, [r3, #0]
|
|
8005092: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005096: 2b00 cmp r3, #0
|
|
8005098: d137 bne.n 800510a <UART_DMATransmitCplt+0x8c>
|
|
{
|
|
huart->TxXferCount = 0x00U;
|
|
800509a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800509c: 2200 movs r2, #0
|
|
800509e: 84da strh r2, [r3, #38] @ 0x26
|
|
|
|
/* Disable the DMA transfer for transmit request by setting the DMAT bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
|
80050a0: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80050a2: 681b ldr r3, [r3, #0]
|
|
80050a4: 3314 adds r3, #20
|
|
80050a6: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80050a8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80050aa: e853 3f00 ldrex r3, [r3]
|
|
80050ae: 623b str r3, [r7, #32]
|
|
return(result);
|
|
80050b0: 6a3b ldr r3, [r7, #32]
|
|
80050b2: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
80050b6: 63bb str r3, [r7, #56] @ 0x38
|
|
80050b8: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80050ba: 681b ldr r3, [r3, #0]
|
|
80050bc: 3314 adds r3, #20
|
|
80050be: 6bba ldr r2, [r7, #56] @ 0x38
|
|
80050c0: 633a str r2, [r7, #48] @ 0x30
|
|
80050c2: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80050c4: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80050c6: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80050c8: e841 2300 strex r3, r2, [r1]
|
|
80050cc: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
80050ce: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80050d0: 2b00 cmp r3, #0
|
|
80050d2: d1e5 bne.n 80050a0 <UART_DMATransmitCplt+0x22>
|
|
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
80050d4: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80050d6: 681b ldr r3, [r3, #0]
|
|
80050d8: 330c adds r3, #12
|
|
80050da: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80050dc: 693b ldr r3, [r7, #16]
|
|
80050de: e853 3f00 ldrex r3, [r3]
|
|
80050e2: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80050e4: 68fb ldr r3, [r7, #12]
|
|
80050e6: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
80050ea: 637b str r3, [r7, #52] @ 0x34
|
|
80050ec: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80050ee: 681b ldr r3, [r3, #0]
|
|
80050f0: 330c adds r3, #12
|
|
80050f2: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
80050f4: 61fa str r2, [r7, #28]
|
|
80050f6: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80050f8: 69b9 ldr r1, [r7, #24]
|
|
80050fa: 69fa ldr r2, [r7, #28]
|
|
80050fc: e841 2300 strex r3, r2, [r1]
|
|
8005100: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8005102: 697b ldr r3, [r7, #20]
|
|
8005104: 2b00 cmp r3, #0
|
|
8005106: d1e5 bne.n 80050d4 <UART_DMATransmitCplt+0x56>
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
8005108: e002 b.n 8005110 <UART_DMATransmitCplt+0x92>
|
|
HAL_UART_TxCpltCallback(huart);
|
|
800510a: 6bf8 ldr r0, [r7, #60] @ 0x3c
|
|
800510c: f7ff ff83 bl 8005016 <HAL_UART_TxCpltCallback>
|
|
}
|
|
8005110: bf00 nop
|
|
8005112: 3740 adds r7, #64 @ 0x40
|
|
8005114: 46bd mov sp, r7
|
|
8005116: bd80 pop {r7, pc}
|
|
|
|
08005118 <UART_DMATxHalfCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8005118: b580 push {r7, lr}
|
|
800511a: b084 sub sp, #16
|
|
800511c: af00 add r7, sp, #0
|
|
800511e: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
8005120: 687b ldr r3, [r7, #4]
|
|
8005122: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005124: 60fb str r3, [r7, #12]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxHalfCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxHalfCpltCallback(huart);
|
|
8005126: 68f8 ldr r0, [r7, #12]
|
|
8005128: f7ff ff7f bl 800502a <HAL_UART_TxHalfCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
800512c: bf00 nop
|
|
800512e: 3710 adds r7, #16
|
|
8005130: 46bd mov sp, r7
|
|
8005132: bd80 pop {r7, pc}
|
|
|
|
08005134 <UART_DMAReceiveCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8005134: b580 push {r7, lr}
|
|
8005136: b09c sub sp, #112 @ 0x70
|
|
8005138: af00 add r7, sp, #0
|
|
800513a: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
800513c: 687b ldr r3, [r7, #4]
|
|
800513e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005140: 66fb str r3, [r7, #108] @ 0x6c
|
|
|
|
/* DMA Normal mode*/
|
|
if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
|
|
8005142: 687b ldr r3, [r7, #4]
|
|
8005144: 681b ldr r3, [r3, #0]
|
|
8005146: 681b ldr r3, [r3, #0]
|
|
8005148: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800514c: 2b00 cmp r3, #0
|
|
800514e: d172 bne.n 8005236 <UART_DMAReceiveCplt+0x102>
|
|
{
|
|
huart->RxXferCount = 0U;
|
|
8005150: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005152: 2200 movs r2, #0
|
|
8005154: 85da strh r2, [r3, #46] @ 0x2e
|
|
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8005156: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005158: 681b ldr r3, [r3, #0]
|
|
800515a: 330c adds r3, #12
|
|
800515c: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800515e: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8005160: e853 3f00 ldrex r3, [r3]
|
|
8005164: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
8005166: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8005168: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
800516c: 66bb str r3, [r7, #104] @ 0x68
|
|
800516e: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005170: 681b ldr r3, [r3, #0]
|
|
8005172: 330c adds r3, #12
|
|
8005174: 6eba ldr r2, [r7, #104] @ 0x68
|
|
8005176: 65ba str r2, [r7, #88] @ 0x58
|
|
8005178: 657b str r3, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800517a: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
800517c: 6dba ldr r2, [r7, #88] @ 0x58
|
|
800517e: e841 2300 strex r3, r2, [r1]
|
|
8005182: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
8005184: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8005186: 2b00 cmp r3, #0
|
|
8005188: d1e5 bne.n 8005156 <UART_DMAReceiveCplt+0x22>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800518a: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800518c: 681b ldr r3, [r3, #0]
|
|
800518e: 3314 adds r3, #20
|
|
8005190: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005192: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8005194: e853 3f00 ldrex r3, [r3]
|
|
8005198: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
800519a: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800519c: f023 0301 bic.w r3, r3, #1
|
|
80051a0: 667b str r3, [r7, #100] @ 0x64
|
|
80051a2: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80051a4: 681b ldr r3, [r3, #0]
|
|
80051a6: 3314 adds r3, #20
|
|
80051a8: 6e7a ldr r2, [r7, #100] @ 0x64
|
|
80051aa: 647a str r2, [r7, #68] @ 0x44
|
|
80051ac: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80051ae: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
80051b0: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
80051b2: e841 2300 strex r3, r2, [r1]
|
|
80051b6: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
80051b8: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80051ba: 2b00 cmp r3, #0
|
|
80051bc: d1e5 bne.n 800518a <UART_DMAReceiveCplt+0x56>
|
|
|
|
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
80051be: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80051c0: 681b ldr r3, [r3, #0]
|
|
80051c2: 3314 adds r3, #20
|
|
80051c4: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80051c6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80051c8: e853 3f00 ldrex r3, [r3]
|
|
80051cc: 623b str r3, [r7, #32]
|
|
return(result);
|
|
80051ce: 6a3b ldr r3, [r7, #32]
|
|
80051d0: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80051d4: 663b str r3, [r7, #96] @ 0x60
|
|
80051d6: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80051d8: 681b ldr r3, [r3, #0]
|
|
80051da: 3314 adds r3, #20
|
|
80051dc: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
80051de: 633a str r2, [r7, #48] @ 0x30
|
|
80051e0: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80051e2: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80051e4: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80051e6: e841 2300 strex r3, r2, [r1]
|
|
80051ea: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
80051ec: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80051ee: 2b00 cmp r3, #0
|
|
80051f0: d1e5 bne.n 80051be <UART_DMAReceiveCplt+0x8a>
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80051f2: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80051f4: 2220 movs r2, #32
|
|
80051f6: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80051fa: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80051fc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80051fe: 2b01 cmp r3, #1
|
|
8005200: d119 bne.n 8005236 <UART_DMAReceiveCplt+0x102>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8005202: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005204: 681b ldr r3, [r3, #0]
|
|
8005206: 330c adds r3, #12
|
|
8005208: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800520a: 693b ldr r3, [r7, #16]
|
|
800520c: e853 3f00 ldrex r3, [r3]
|
|
8005210: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8005212: 68fb ldr r3, [r7, #12]
|
|
8005214: f023 0310 bic.w r3, r3, #16
|
|
8005218: 65fb str r3, [r7, #92] @ 0x5c
|
|
800521a: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800521c: 681b ldr r3, [r3, #0]
|
|
800521e: 330c adds r3, #12
|
|
8005220: 6dfa ldr r2, [r7, #92] @ 0x5c
|
|
8005222: 61fa str r2, [r7, #28]
|
|
8005224: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005226: 69b9 ldr r1, [r7, #24]
|
|
8005228: 69fa ldr r2, [r7, #28]
|
|
800522a: e841 2300 strex r3, r2, [r1]
|
|
800522e: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8005230: 697b ldr r3, [r7, #20]
|
|
8005232: 2b00 cmp r3, #0
|
|
8005234: d1e5 bne.n 8005202 <UART_DMAReceiveCplt+0xce>
|
|
}
|
|
}
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8005236: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005238: 2200 movs r2, #0
|
|
800523a: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : use Rx Event callback */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
800523c: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800523e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8005240: 2b01 cmp r3, #1
|
|
8005242: d106 bne.n 8005252 <UART_DMAReceiveCplt+0x11e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8005244: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005246: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8005248: 4619 mov r1, r3
|
|
800524a: 6ef8 ldr r0, [r7, #108] @ 0x6c
|
|
800524c: f7ff ff0b bl 8005066 <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
8005250: e002 b.n 8005258 <UART_DMAReceiveCplt+0x124>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8005252: 6ef8 ldr r0, [r7, #108] @ 0x6c
|
|
8005254: f7fb fd0e bl 8000c74 <HAL_UART_RxCpltCallback>
|
|
}
|
|
8005258: bf00 nop
|
|
800525a: 3770 adds r7, #112 @ 0x70
|
|
800525c: 46bd mov sp, r7
|
|
800525e: bd80 pop {r7, pc}
|
|
|
|
08005260 <UART_DMARxHalfCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8005260: b580 push {r7, lr}
|
|
8005262: b084 sub sp, #16
|
|
8005264: af00 add r7, sp, #0
|
|
8005266: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
8005268: 687b ldr r3, [r7, #4]
|
|
800526a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800526c: 60fb str r3, [r7, #12]
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Half Transfer */
|
|
huart->RxEventType = HAL_UART_RXEVENT_HT;
|
|
800526e: 68fb ldr r3, [r7, #12]
|
|
8005270: 2201 movs r2, #1
|
|
8005272: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : use Rx Event callback */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8005274: 68fb ldr r3, [r7, #12]
|
|
8005276: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8005278: 2b01 cmp r3, #1
|
|
800527a: d108 bne.n 800528e <UART_DMARxHalfCplt+0x2e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize / 2U);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
|
|
800527c: 68fb ldr r3, [r7, #12]
|
|
800527e: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8005280: 085b lsrs r3, r3, #1
|
|
8005282: b29b uxth r3, r3
|
|
8005284: 4619 mov r1, r3
|
|
8005286: 68f8 ldr r0, [r7, #12]
|
|
8005288: f7ff feed bl 8005066 <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx Half complete callback*/
|
|
HAL_UART_RxHalfCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
800528c: e002 b.n 8005294 <UART_DMARxHalfCplt+0x34>
|
|
HAL_UART_RxHalfCpltCallback(huart);
|
|
800528e: 68f8 ldr r0, [r7, #12]
|
|
8005290: f7ff fed5 bl 800503e <HAL_UART_RxHalfCpltCallback>
|
|
}
|
|
8005294: bf00 nop
|
|
8005296: 3710 adds r7, #16
|
|
8005298: 46bd mov sp, r7
|
|
800529a: bd80 pop {r7, pc}
|
|
|
|
0800529c <UART_DMAError>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800529c: b580 push {r7, lr}
|
|
800529e: b084 sub sp, #16
|
|
80052a0: af00 add r7, sp, #0
|
|
80052a2: 6078 str r0, [r7, #4]
|
|
uint32_t dmarequest = 0x00U;
|
|
80052a4: 2300 movs r3, #0
|
|
80052a6: 60fb str r3, [r7, #12]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
80052a8: 687b ldr r3, [r7, #4]
|
|
80052aa: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80052ac: 60bb str r3, [r7, #8]
|
|
|
|
/* Stop UART DMA Tx request if ongoing */
|
|
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
|
|
80052ae: 68bb ldr r3, [r7, #8]
|
|
80052b0: 681b ldr r3, [r3, #0]
|
|
80052b2: 695b ldr r3, [r3, #20]
|
|
80052b4: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80052b8: 2b80 cmp r3, #128 @ 0x80
|
|
80052ba: bf0c ite eq
|
|
80052bc: 2301 moveq r3, #1
|
|
80052be: 2300 movne r3, #0
|
|
80052c0: b2db uxtb r3, r3
|
|
80052c2: 60fb str r3, [r7, #12]
|
|
if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
|
|
80052c4: 68bb ldr r3, [r7, #8]
|
|
80052c6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
80052ca: b2db uxtb r3, r3
|
|
80052cc: 2b21 cmp r3, #33 @ 0x21
|
|
80052ce: d108 bne.n 80052e2 <UART_DMAError+0x46>
|
|
80052d0: 68fb ldr r3, [r7, #12]
|
|
80052d2: 2b00 cmp r3, #0
|
|
80052d4: d005 beq.n 80052e2 <UART_DMAError+0x46>
|
|
{
|
|
huart->TxXferCount = 0x00U;
|
|
80052d6: 68bb ldr r3, [r7, #8]
|
|
80052d8: 2200 movs r2, #0
|
|
80052da: 84da strh r2, [r3, #38] @ 0x26
|
|
UART_EndTxTransfer(huart);
|
|
80052dc: 68b8 ldr r0, [r7, #8]
|
|
80052de: f000 f8cd bl 800547c <UART_EndTxTransfer>
|
|
}
|
|
|
|
/* Stop UART DMA Rx request if ongoing */
|
|
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
|
|
80052e2: 68bb ldr r3, [r7, #8]
|
|
80052e4: 681b ldr r3, [r3, #0]
|
|
80052e6: 695b ldr r3, [r3, #20]
|
|
80052e8: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80052ec: 2b40 cmp r3, #64 @ 0x40
|
|
80052ee: bf0c ite eq
|
|
80052f0: 2301 moveq r3, #1
|
|
80052f2: 2300 movne r3, #0
|
|
80052f4: b2db uxtb r3, r3
|
|
80052f6: 60fb str r3, [r7, #12]
|
|
if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
|
|
80052f8: 68bb ldr r3, [r7, #8]
|
|
80052fa: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
80052fe: b2db uxtb r3, r3
|
|
8005300: 2b22 cmp r3, #34 @ 0x22
|
|
8005302: d108 bne.n 8005316 <UART_DMAError+0x7a>
|
|
8005304: 68fb ldr r3, [r7, #12]
|
|
8005306: 2b00 cmp r3, #0
|
|
8005308: d005 beq.n 8005316 <UART_DMAError+0x7a>
|
|
{
|
|
huart->RxXferCount = 0x00U;
|
|
800530a: 68bb ldr r3, [r7, #8]
|
|
800530c: 2200 movs r2, #0
|
|
800530e: 85da strh r2, [r3, #46] @ 0x2e
|
|
UART_EndRxTransfer(huart);
|
|
8005310: 68b8 ldr r0, [r7, #8]
|
|
8005312: f000 f8db bl 80054cc <UART_EndRxTransfer>
|
|
}
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_DMA;
|
|
8005316: 68bb ldr r3, [r7, #8]
|
|
8005318: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800531a: f043 0210 orr.w r2, r3, #16
|
|
800531e: 68bb ldr r3, [r7, #8]
|
|
8005320: 645a str r2, [r3, #68] @ 0x44
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8005322: 68b8 ldr r0, [r7, #8]
|
|
8005324: f7ff fe95 bl 8005052 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
8005328: bf00 nop
|
|
800532a: 3710 adds r7, #16
|
|
800532c: 46bd mov sp, r7
|
|
800532e: bd80 pop {r7, pc}
|
|
|
|
08005330 <UART_Start_Receive_DMA>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
8005330: b580 push {r7, lr}
|
|
8005332: b098 sub sp, #96 @ 0x60
|
|
8005334: af00 add r7, sp, #0
|
|
8005336: 60f8 str r0, [r7, #12]
|
|
8005338: 60b9 str r1, [r7, #8]
|
|
800533a: 4613 mov r3, r2
|
|
800533c: 80fb strh r3, [r7, #6]
|
|
uint32_t *tmp;
|
|
|
|
huart->pRxBuffPtr = pData;
|
|
800533e: 68ba ldr r2, [r7, #8]
|
|
8005340: 68fb ldr r3, [r7, #12]
|
|
8005342: 629a str r2, [r3, #40] @ 0x28
|
|
huart->RxXferSize = Size;
|
|
8005344: 68fb ldr r3, [r7, #12]
|
|
8005346: 88fa ldrh r2, [r7, #6]
|
|
8005348: 859a strh r2, [r3, #44] @ 0x2c
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800534a: 68fb ldr r3, [r7, #12]
|
|
800534c: 2200 movs r2, #0
|
|
800534e: 645a str r2, [r3, #68] @ 0x44
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
8005350: 68fb ldr r3, [r7, #12]
|
|
8005352: 2222 movs r2, #34 @ 0x22
|
|
8005354: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Set the UART DMA transfer complete callback */
|
|
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
|
|
8005358: 68fb ldr r3, [r7, #12]
|
|
800535a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800535c: 4a44 ldr r2, [pc, #272] @ (8005470 <UART_Start_Receive_DMA+0x140>)
|
|
800535e: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Set the UART DMA Half transfer complete callback */
|
|
huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
|
|
8005360: 68fb ldr r3, [r7, #12]
|
|
8005362: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005364: 4a43 ldr r2, [pc, #268] @ (8005474 <UART_Start_Receive_DMA+0x144>)
|
|
8005366: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set the DMA error callback */
|
|
huart->hdmarx->XferErrorCallback = UART_DMAError;
|
|
8005368: 68fb ldr r3, [r7, #12]
|
|
800536a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800536c: 4a42 ldr r2, [pc, #264] @ (8005478 <UART_Start_Receive_DMA+0x148>)
|
|
800536e: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Set the DMA abort callback */
|
|
huart->hdmarx->XferAbortCallback = NULL;
|
|
8005370: 68fb ldr r3, [r7, #12]
|
|
8005372: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005374: 2200 movs r2, #0
|
|
8005376: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Enable the DMA stream */
|
|
tmp = (uint32_t *)&pData;
|
|
8005378: f107 0308 add.w r3, r7, #8
|
|
800537c: 65fb str r3, [r7, #92] @ 0x5c
|
|
if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK)
|
|
800537e: 68fb ldr r3, [r7, #12]
|
|
8005380: 6bd8 ldr r0, [r3, #60] @ 0x3c
|
|
8005382: 68fb ldr r3, [r7, #12]
|
|
8005384: 681b ldr r3, [r3, #0]
|
|
8005386: 3304 adds r3, #4
|
|
8005388: 4619 mov r1, r3
|
|
800538a: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
800538c: 681a ldr r2, [r3, #0]
|
|
800538e: 88fb ldrh r3, [r7, #6]
|
|
8005390: f7fc fa03 bl 800179a <HAL_DMA_Start_IT>
|
|
8005394: 4603 mov r3, r0
|
|
8005396: 2b00 cmp r3, #0
|
|
8005398: d008 beq.n 80053ac <UART_Start_Receive_DMA+0x7c>
|
|
{
|
|
/* Set error code to DMA */
|
|
huart->ErrorCode = HAL_UART_ERROR_DMA;
|
|
800539a: 68fb ldr r3, [r7, #12]
|
|
800539c: 2210 movs r2, #16
|
|
800539e: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Restore huart->RxState to ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80053a0: 68fb ldr r3, [r7, #12]
|
|
80053a2: 2220 movs r2, #32
|
|
80053a4: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
return HAL_ERROR;
|
|
80053a8: 2301 movs r3, #1
|
|
80053aa: e05d b.n 8005468 <UART_Start_Receive_DMA+0x138>
|
|
}
|
|
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
|
|
__HAL_UART_CLEAR_OREFLAG(huart);
|
|
80053ac: 2300 movs r3, #0
|
|
80053ae: 613b str r3, [r7, #16]
|
|
80053b0: 68fb ldr r3, [r7, #12]
|
|
80053b2: 681b ldr r3, [r3, #0]
|
|
80053b4: 681b ldr r3, [r3, #0]
|
|
80053b6: 613b str r3, [r7, #16]
|
|
80053b8: 68fb ldr r3, [r7, #12]
|
|
80053ba: 681b ldr r3, [r3, #0]
|
|
80053bc: 685b ldr r3, [r3, #4]
|
|
80053be: 613b str r3, [r7, #16]
|
|
80053c0: 693b ldr r3, [r7, #16]
|
|
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
80053c2: 68fb ldr r3, [r7, #12]
|
|
80053c4: 691b ldr r3, [r3, #16]
|
|
80053c6: 2b00 cmp r3, #0
|
|
80053c8: d019 beq.n 80053fe <UART_Start_Receive_DMA+0xce>
|
|
{
|
|
/* Enable the UART Parity Error Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
80053ca: 68fb ldr r3, [r7, #12]
|
|
80053cc: 681b ldr r3, [r3, #0]
|
|
80053ce: 330c adds r3, #12
|
|
80053d0: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80053d2: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80053d4: e853 3f00 ldrex r3, [r3]
|
|
80053d8: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
80053da: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80053dc: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80053e0: 65bb str r3, [r7, #88] @ 0x58
|
|
80053e2: 68fb ldr r3, [r7, #12]
|
|
80053e4: 681b ldr r3, [r3, #0]
|
|
80053e6: 330c adds r3, #12
|
|
80053e8: 6dba ldr r2, [r7, #88] @ 0x58
|
|
80053ea: 64fa str r2, [r7, #76] @ 0x4c
|
|
80053ec: 64bb str r3, [r7, #72] @ 0x48
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80053ee: 6cb9 ldr r1, [r7, #72] @ 0x48
|
|
80053f0: 6cfa ldr r2, [r7, #76] @ 0x4c
|
|
80053f2: e841 2300 strex r3, r2, [r1]
|
|
80053f6: 647b str r3, [r7, #68] @ 0x44
|
|
return(result);
|
|
80053f8: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
80053fa: 2b00 cmp r3, #0
|
|
80053fc: d1e5 bne.n 80053ca <UART_Start_Receive_DMA+0x9a>
|
|
}
|
|
|
|
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
80053fe: 68fb ldr r3, [r7, #12]
|
|
8005400: 681b ldr r3, [r3, #0]
|
|
8005402: 3314 adds r3, #20
|
|
8005404: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005406: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8005408: e853 3f00 ldrex r3, [r3]
|
|
800540c: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
800540e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8005410: f043 0301 orr.w r3, r3, #1
|
|
8005414: 657b str r3, [r7, #84] @ 0x54
|
|
8005416: 68fb ldr r3, [r7, #12]
|
|
8005418: 681b ldr r3, [r3, #0]
|
|
800541a: 3314 adds r3, #20
|
|
800541c: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
800541e: 63ba str r2, [r7, #56] @ 0x38
|
|
8005420: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005422: 6b79 ldr r1, [r7, #52] @ 0x34
|
|
8005424: 6bba ldr r2, [r7, #56] @ 0x38
|
|
8005426: e841 2300 strex r3, r2, [r1]
|
|
800542a: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
800542c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800542e: 2b00 cmp r3, #0
|
|
8005430: d1e5 bne.n 80053fe <UART_Start_Receive_DMA+0xce>
|
|
|
|
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8005432: 68fb ldr r3, [r7, #12]
|
|
8005434: 681b ldr r3, [r3, #0]
|
|
8005436: 3314 adds r3, #20
|
|
8005438: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800543a: 69bb ldr r3, [r7, #24]
|
|
800543c: e853 3f00 ldrex r3, [r3]
|
|
8005440: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8005442: 697b ldr r3, [r7, #20]
|
|
8005444: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8005448: 653b str r3, [r7, #80] @ 0x50
|
|
800544a: 68fb ldr r3, [r7, #12]
|
|
800544c: 681b ldr r3, [r3, #0]
|
|
800544e: 3314 adds r3, #20
|
|
8005450: 6d3a ldr r2, [r7, #80] @ 0x50
|
|
8005452: 627a str r2, [r7, #36] @ 0x24
|
|
8005454: 623b str r3, [r7, #32]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005456: 6a39 ldr r1, [r7, #32]
|
|
8005458: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800545a: e841 2300 strex r3, r2, [r1]
|
|
800545e: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8005460: 69fb ldr r3, [r7, #28]
|
|
8005462: 2b00 cmp r3, #0
|
|
8005464: d1e5 bne.n 8005432 <UART_Start_Receive_DMA+0x102>
|
|
|
|
return HAL_OK;
|
|
8005466: 2300 movs r3, #0
|
|
}
|
|
8005468: 4618 mov r0, r3
|
|
800546a: 3760 adds r7, #96 @ 0x60
|
|
800546c: 46bd mov sp, r7
|
|
800546e: bd80 pop {r7, pc}
|
|
8005470: 08005135 .word 0x08005135
|
|
8005474: 08005261 .word 0x08005261
|
|
8005478: 0800529d .word 0x0800529d
|
|
|
|
0800547c <UART_EndTxTransfer>:
|
|
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
800547c: b480 push {r7}
|
|
800547e: b089 sub sp, #36 @ 0x24
|
|
8005480: af00 add r7, sp, #0
|
|
8005482: 6078 str r0, [r7, #4]
|
|
/* Disable TXEIE and TCIE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
|
|
8005484: 687b ldr r3, [r7, #4]
|
|
8005486: 681b ldr r3, [r3, #0]
|
|
8005488: 330c adds r3, #12
|
|
800548a: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800548c: 68fb ldr r3, [r7, #12]
|
|
800548e: e853 3f00 ldrex r3, [r3]
|
|
8005492: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8005494: 68bb ldr r3, [r7, #8]
|
|
8005496: f023 03c0 bic.w r3, r3, #192 @ 0xc0
|
|
800549a: 61fb str r3, [r7, #28]
|
|
800549c: 687b ldr r3, [r7, #4]
|
|
800549e: 681b ldr r3, [r3, #0]
|
|
80054a0: 330c adds r3, #12
|
|
80054a2: 69fa ldr r2, [r7, #28]
|
|
80054a4: 61ba str r2, [r7, #24]
|
|
80054a6: 617b str r3, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80054a8: 6979 ldr r1, [r7, #20]
|
|
80054aa: 69ba ldr r2, [r7, #24]
|
|
80054ac: e841 2300 strex r3, r2, [r1]
|
|
80054b0: 613b str r3, [r7, #16]
|
|
return(result);
|
|
80054b2: 693b ldr r3, [r7, #16]
|
|
80054b4: 2b00 cmp r3, #0
|
|
80054b6: d1e5 bne.n 8005484 <UART_EndTxTransfer+0x8>
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80054b8: 687b ldr r3, [r7, #4]
|
|
80054ba: 2220 movs r2, #32
|
|
80054bc: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
}
|
|
80054c0: bf00 nop
|
|
80054c2: 3724 adds r7, #36 @ 0x24
|
|
80054c4: 46bd mov sp, r7
|
|
80054c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80054ca: 4770 bx lr
|
|
|
|
080054cc <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
80054cc: b480 push {r7}
|
|
80054ce: b095 sub sp, #84 @ 0x54
|
|
80054d0: af00 add r7, sp, #0
|
|
80054d2: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
80054d4: 687b ldr r3, [r7, #4]
|
|
80054d6: 681b ldr r3, [r3, #0]
|
|
80054d8: 330c adds r3, #12
|
|
80054da: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80054dc: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80054de: e853 3f00 ldrex r3, [r3]
|
|
80054e2: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
80054e4: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80054e6: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
80054ea: 64fb str r3, [r7, #76] @ 0x4c
|
|
80054ec: 687b ldr r3, [r7, #4]
|
|
80054ee: 681b ldr r3, [r3, #0]
|
|
80054f0: 330c adds r3, #12
|
|
80054f2: 6cfa ldr r2, [r7, #76] @ 0x4c
|
|
80054f4: 643a str r2, [r7, #64] @ 0x40
|
|
80054f6: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80054f8: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
80054fa: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
80054fc: e841 2300 strex r3, r2, [r1]
|
|
8005500: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8005502: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8005504: 2b00 cmp r3, #0
|
|
8005506: d1e5 bne.n 80054d4 <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8005508: 687b ldr r3, [r7, #4]
|
|
800550a: 681b ldr r3, [r3, #0]
|
|
800550c: 3314 adds r3, #20
|
|
800550e: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005510: 6a3b ldr r3, [r7, #32]
|
|
8005512: e853 3f00 ldrex r3, [r3]
|
|
8005516: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8005518: 69fb ldr r3, [r7, #28]
|
|
800551a: f023 0301 bic.w r3, r3, #1
|
|
800551e: 64bb str r3, [r7, #72] @ 0x48
|
|
8005520: 687b ldr r3, [r7, #4]
|
|
8005522: 681b ldr r3, [r3, #0]
|
|
8005524: 3314 adds r3, #20
|
|
8005526: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8005528: 62fa str r2, [r7, #44] @ 0x2c
|
|
800552a: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800552c: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
800552e: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8005530: e841 2300 strex r3, r2, [r1]
|
|
8005534: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8005536: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005538: 2b00 cmp r3, #0
|
|
800553a: d1e5 bne.n 8005508 <UART_EndRxTransfer+0x3c>
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
800553c: 687b ldr r3, [r7, #4]
|
|
800553e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8005540: 2b01 cmp r3, #1
|
|
8005542: d119 bne.n 8005578 <UART_EndRxTransfer+0xac>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8005544: 687b ldr r3, [r7, #4]
|
|
8005546: 681b ldr r3, [r3, #0]
|
|
8005548: 330c adds r3, #12
|
|
800554a: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800554c: 68fb ldr r3, [r7, #12]
|
|
800554e: e853 3f00 ldrex r3, [r3]
|
|
8005552: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8005554: 68bb ldr r3, [r7, #8]
|
|
8005556: f023 0310 bic.w r3, r3, #16
|
|
800555a: 647b str r3, [r7, #68] @ 0x44
|
|
800555c: 687b ldr r3, [r7, #4]
|
|
800555e: 681b ldr r3, [r3, #0]
|
|
8005560: 330c adds r3, #12
|
|
8005562: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8005564: 61ba str r2, [r7, #24]
|
|
8005566: 617b str r3, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005568: 6979 ldr r1, [r7, #20]
|
|
800556a: 69ba ldr r2, [r7, #24]
|
|
800556c: e841 2300 strex r3, r2, [r1]
|
|
8005570: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8005572: 693b ldr r3, [r7, #16]
|
|
8005574: 2b00 cmp r3, #0
|
|
8005576: d1e5 bne.n 8005544 <UART_EndRxTransfer+0x78>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8005578: 687b ldr r3, [r7, #4]
|
|
800557a: 2220 movs r2, #32
|
|
800557c: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8005580: 687b ldr r3, [r7, #4]
|
|
8005582: 2200 movs r2, #0
|
|
8005584: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
8005586: bf00 nop
|
|
8005588: 3754 adds r7, #84 @ 0x54
|
|
800558a: 46bd mov sp, r7
|
|
800558c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005590: 4770 bx lr
|
|
...
|
|
|
|
08005594 <UART_SetConfig>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8005594: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8005598: b0c0 sub sp, #256 @ 0x100
|
|
800559a: af00 add r7, sp, #0
|
|
800559c: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4
|
|
assert_param(IS_UART_MODE(huart->Init.Mode));
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits
|
|
according to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
80055a0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055a4: 681b ldr r3, [r3, #0]
|
|
80055a6: 691b ldr r3, [r3, #16]
|
|
80055a8: f423 5040 bic.w r0, r3, #12288 @ 0x3000
|
|
80055ac: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055b0: 68d9 ldr r1, [r3, #12]
|
|
80055b2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055b6: 681a ldr r2, [r3, #0]
|
|
80055b8: ea40 0301 orr.w r3, r0, r1
|
|
80055bc: 6113 str r3, [r2, #16]
|
|
Set the M bits according to huart->Init.WordLength value
|
|
Set PCE and PS bits according to huart->Init.Parity value
|
|
Set TE and RE bits according to huart->Init.Mode value
|
|
Set OVER8 bit according to huart->Init.OverSampling value */
|
|
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
|
|
80055be: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055c2: 689a ldr r2, [r3, #8]
|
|
80055c4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055c8: 691b ldr r3, [r3, #16]
|
|
80055ca: 431a orrs r2, r3
|
|
80055cc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055d0: 695b ldr r3, [r3, #20]
|
|
80055d2: 431a orrs r2, r3
|
|
80055d4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055d8: 69db ldr r3, [r3, #28]
|
|
80055da: 4313 orrs r3, r2
|
|
80055dc: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
80055e0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055e4: 681b ldr r3, [r3, #0]
|
|
80055e6: 68db ldr r3, [r3, #12]
|
|
80055e8: f423 4116 bic.w r1, r3, #38400 @ 0x9600
|
|
80055ec: f021 010c bic.w r1, r1, #12
|
|
80055f0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055f4: 681a ldr r2, [r3, #0]
|
|
80055f6: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
|
|
80055fa: 430b orrs r3, r1
|
|
80055fc: 60d3 str r3, [r2, #12]
|
|
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
|
tmpreg);
|
|
|
|
/*-------------------------- USART CR3 Configuration -----------------------*/
|
|
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
|
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
|
80055fe: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005602: 681b ldr r3, [r3, #0]
|
|
8005604: 695b ldr r3, [r3, #20]
|
|
8005606: f423 7040 bic.w r0, r3, #768 @ 0x300
|
|
800560a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800560e: 6999 ldr r1, [r3, #24]
|
|
8005610: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005614: 681a ldr r2, [r3, #0]
|
|
8005616: ea40 0301 orr.w r3, r0, r1
|
|
800561a: 6153 str r3, [r2, #20]
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#elif defined(USART6)
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6))
|
|
800561c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005620: 681a ldr r2, [r3, #0]
|
|
8005622: 4b8f ldr r3, [pc, #572] @ (8005860 <UART_SetConfig+0x2cc>)
|
|
8005624: 429a cmp r2, r3
|
|
8005626: d005 beq.n 8005634 <UART_SetConfig+0xa0>
|
|
8005628: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800562c: 681a ldr r2, [r3, #0]
|
|
800562e: 4b8d ldr r3, [pc, #564] @ (8005864 <UART_SetConfig+0x2d0>)
|
|
8005630: 429a cmp r2, r3
|
|
8005632: d104 bne.n 800563e <UART_SetConfig+0xaa>
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8005634: f7fd ffce bl 80035d4 <HAL_RCC_GetPCLK2Freq>
|
|
8005638: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
800563c: e003 b.n 8005646 <UART_SetConfig+0xb2>
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#endif /* USART6 */
|
|
else
|
|
{
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
800563e: f7fd ffb5 bl 80035ac <HAL_RCC_GetPCLK1Freq>
|
|
8005642: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
}
|
|
/*-------------------------- USART BRR Configuration ---------------------*/
|
|
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8005646: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800564a: 69db ldr r3, [r3, #28]
|
|
800564c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8005650: f040 810c bne.w 800586c <UART_SetConfig+0x2d8>
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
|
|
8005654: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8005658: 2200 movs r2, #0
|
|
800565a: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
|
|
800565e: f8c7 20ec str.w r2, [r7, #236] @ 0xec
|
|
8005662: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8
|
|
8005666: 4622 mov r2, r4
|
|
8005668: 462b mov r3, r5
|
|
800566a: 1891 adds r1, r2, r2
|
|
800566c: 65b9 str r1, [r7, #88] @ 0x58
|
|
800566e: 415b adcs r3, r3
|
|
8005670: 65fb str r3, [r7, #92] @ 0x5c
|
|
8005672: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
|
|
8005676: 4621 mov r1, r4
|
|
8005678: eb12 0801 adds.w r8, r2, r1
|
|
800567c: 4629 mov r1, r5
|
|
800567e: eb43 0901 adc.w r9, r3, r1
|
|
8005682: f04f 0200 mov.w r2, #0
|
|
8005686: f04f 0300 mov.w r3, #0
|
|
800568a: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
800568e: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8005692: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
8005696: 4690 mov r8, r2
|
|
8005698: 4699 mov r9, r3
|
|
800569a: 4623 mov r3, r4
|
|
800569c: eb18 0303 adds.w r3, r8, r3
|
|
80056a0: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
80056a4: 462b mov r3, r5
|
|
80056a6: eb49 0303 adc.w r3, r9, r3
|
|
80056aa: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
80056ae: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80056b2: 685b ldr r3, [r3, #4]
|
|
80056b4: 2200 movs r2, #0
|
|
80056b6: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
80056ba: f8c7 20dc str.w r2, [r7, #220] @ 0xdc
|
|
80056be: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8
|
|
80056c2: 460b mov r3, r1
|
|
80056c4: 18db adds r3, r3, r3
|
|
80056c6: 653b str r3, [r7, #80] @ 0x50
|
|
80056c8: 4613 mov r3, r2
|
|
80056ca: eb42 0303 adc.w r3, r2, r3
|
|
80056ce: 657b str r3, [r7, #84] @ 0x54
|
|
80056d0: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50
|
|
80056d4: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0
|
|
80056d8: f7fa fd94 bl 8000204 <__aeabi_uldivmod>
|
|
80056dc: 4602 mov r2, r0
|
|
80056de: 460b mov r3, r1
|
|
80056e0: 4b61 ldr r3, [pc, #388] @ (8005868 <UART_SetConfig+0x2d4>)
|
|
80056e2: fba3 2302 umull r2, r3, r3, r2
|
|
80056e6: 095b lsrs r3, r3, #5
|
|
80056e8: 011c lsls r4, r3, #4
|
|
80056ea: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80056ee: 2200 movs r2, #0
|
|
80056f0: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
80056f4: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4
|
|
80056f8: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0
|
|
80056fc: 4642 mov r2, r8
|
|
80056fe: 464b mov r3, r9
|
|
8005700: 1891 adds r1, r2, r2
|
|
8005702: 64b9 str r1, [r7, #72] @ 0x48
|
|
8005704: 415b adcs r3, r3
|
|
8005706: 64fb str r3, [r7, #76] @ 0x4c
|
|
8005708: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
|
|
800570c: 4641 mov r1, r8
|
|
800570e: eb12 0a01 adds.w sl, r2, r1
|
|
8005712: 4649 mov r1, r9
|
|
8005714: eb43 0b01 adc.w fp, r3, r1
|
|
8005718: f04f 0200 mov.w r2, #0
|
|
800571c: f04f 0300 mov.w r3, #0
|
|
8005720: ea4f 03cb mov.w r3, fp, lsl #3
|
|
8005724: ea43 735a orr.w r3, r3, sl, lsr #29
|
|
8005728: ea4f 02ca mov.w r2, sl, lsl #3
|
|
800572c: 4692 mov sl, r2
|
|
800572e: 469b mov fp, r3
|
|
8005730: 4643 mov r3, r8
|
|
8005732: eb1a 0303 adds.w r3, sl, r3
|
|
8005736: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
800573a: 464b mov r3, r9
|
|
800573c: eb4b 0303 adc.w r3, fp, r3
|
|
8005740: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
|
|
8005744: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005748: 685b ldr r3, [r3, #4]
|
|
800574a: 2200 movs r2, #0
|
|
800574c: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
8005750: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4
|
|
8005754: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0
|
|
8005758: 460b mov r3, r1
|
|
800575a: 18db adds r3, r3, r3
|
|
800575c: 643b str r3, [r7, #64] @ 0x40
|
|
800575e: 4613 mov r3, r2
|
|
8005760: eb42 0303 adc.w r3, r2, r3
|
|
8005764: 647b str r3, [r7, #68] @ 0x44
|
|
8005766: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40
|
|
800576a: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8
|
|
800576e: f7fa fd49 bl 8000204 <__aeabi_uldivmod>
|
|
8005772: 4602 mov r2, r0
|
|
8005774: 460b mov r3, r1
|
|
8005776: 4611 mov r1, r2
|
|
8005778: 4b3b ldr r3, [pc, #236] @ (8005868 <UART_SetConfig+0x2d4>)
|
|
800577a: fba3 2301 umull r2, r3, r3, r1
|
|
800577e: 095b lsrs r3, r3, #5
|
|
8005780: 2264 movs r2, #100 @ 0x64
|
|
8005782: fb02 f303 mul.w r3, r2, r3
|
|
8005786: 1acb subs r3, r1, r3
|
|
8005788: 00db lsls r3, r3, #3
|
|
800578a: f103 0232 add.w r2, r3, #50 @ 0x32
|
|
800578e: 4b36 ldr r3, [pc, #216] @ (8005868 <UART_SetConfig+0x2d4>)
|
|
8005790: fba3 2302 umull r2, r3, r3, r2
|
|
8005794: 095b lsrs r3, r3, #5
|
|
8005796: 005b lsls r3, r3, #1
|
|
8005798: f403 73f8 and.w r3, r3, #496 @ 0x1f0
|
|
800579c: 441c add r4, r3
|
|
800579e: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80057a2: 2200 movs r2, #0
|
|
80057a4: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
80057a8: f8c7 20bc str.w r2, [r7, #188] @ 0xbc
|
|
80057ac: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8
|
|
80057b0: 4642 mov r2, r8
|
|
80057b2: 464b mov r3, r9
|
|
80057b4: 1891 adds r1, r2, r2
|
|
80057b6: 63b9 str r1, [r7, #56] @ 0x38
|
|
80057b8: 415b adcs r3, r3
|
|
80057ba: 63fb str r3, [r7, #60] @ 0x3c
|
|
80057bc: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38
|
|
80057c0: 4641 mov r1, r8
|
|
80057c2: 1851 adds r1, r2, r1
|
|
80057c4: 6339 str r1, [r7, #48] @ 0x30
|
|
80057c6: 4649 mov r1, r9
|
|
80057c8: 414b adcs r3, r1
|
|
80057ca: 637b str r3, [r7, #52] @ 0x34
|
|
80057cc: f04f 0200 mov.w r2, #0
|
|
80057d0: f04f 0300 mov.w r3, #0
|
|
80057d4: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30
|
|
80057d8: 4659 mov r1, fp
|
|
80057da: 00cb lsls r3, r1, #3
|
|
80057dc: 4651 mov r1, sl
|
|
80057de: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
80057e2: 4651 mov r1, sl
|
|
80057e4: 00ca lsls r2, r1, #3
|
|
80057e6: 4610 mov r0, r2
|
|
80057e8: 4619 mov r1, r3
|
|
80057ea: 4603 mov r3, r0
|
|
80057ec: 4642 mov r2, r8
|
|
80057ee: 189b adds r3, r3, r2
|
|
80057f0: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
80057f4: 464b mov r3, r9
|
|
80057f6: 460a mov r2, r1
|
|
80057f8: eb42 0303 adc.w r3, r2, r3
|
|
80057fc: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8005800: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005804: 685b ldr r3, [r3, #4]
|
|
8005806: 2200 movs r2, #0
|
|
8005808: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
800580c: f8c7 20ac str.w r2, [r7, #172] @ 0xac
|
|
8005810: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8
|
|
8005814: 460b mov r3, r1
|
|
8005816: 18db adds r3, r3, r3
|
|
8005818: 62bb str r3, [r7, #40] @ 0x28
|
|
800581a: 4613 mov r3, r2
|
|
800581c: eb42 0303 adc.w r3, r2, r3
|
|
8005820: 62fb str r3, [r7, #44] @ 0x2c
|
|
8005822: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
|
|
8005826: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0
|
|
800582a: f7fa fceb bl 8000204 <__aeabi_uldivmod>
|
|
800582e: 4602 mov r2, r0
|
|
8005830: 460b mov r3, r1
|
|
8005832: 4b0d ldr r3, [pc, #52] @ (8005868 <UART_SetConfig+0x2d4>)
|
|
8005834: fba3 1302 umull r1, r3, r3, r2
|
|
8005838: 095b lsrs r3, r3, #5
|
|
800583a: 2164 movs r1, #100 @ 0x64
|
|
800583c: fb01 f303 mul.w r3, r1, r3
|
|
8005840: 1ad3 subs r3, r2, r3
|
|
8005842: 00db lsls r3, r3, #3
|
|
8005844: 3332 adds r3, #50 @ 0x32
|
|
8005846: 4a08 ldr r2, [pc, #32] @ (8005868 <UART_SetConfig+0x2d4>)
|
|
8005848: fba2 2303 umull r2, r3, r2, r3
|
|
800584c: 095b lsrs r3, r3, #5
|
|
800584e: f003 0207 and.w r2, r3, #7
|
|
8005852: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005856: 681b ldr r3, [r3, #0]
|
|
8005858: 4422 add r2, r4
|
|
800585a: 609a str r2, [r3, #8]
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
}
|
|
}
|
|
800585c: e106 b.n 8005a6c <UART_SetConfig+0x4d8>
|
|
800585e: bf00 nop
|
|
8005860: 40011000 .word 0x40011000
|
|
8005864: 40011400 .word 0x40011400
|
|
8005868: 51eb851f .word 0x51eb851f
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
800586c: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8005870: 2200 movs r2, #0
|
|
8005872: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
8005876: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4
|
|
800587a: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0
|
|
800587e: 4642 mov r2, r8
|
|
8005880: 464b mov r3, r9
|
|
8005882: 1891 adds r1, r2, r2
|
|
8005884: 6239 str r1, [r7, #32]
|
|
8005886: 415b adcs r3, r3
|
|
8005888: 627b str r3, [r7, #36] @ 0x24
|
|
800588a: e9d7 2308 ldrd r2, r3, [r7, #32]
|
|
800588e: 4641 mov r1, r8
|
|
8005890: 1854 adds r4, r2, r1
|
|
8005892: 4649 mov r1, r9
|
|
8005894: eb43 0501 adc.w r5, r3, r1
|
|
8005898: f04f 0200 mov.w r2, #0
|
|
800589c: f04f 0300 mov.w r3, #0
|
|
80058a0: 00eb lsls r3, r5, #3
|
|
80058a2: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
80058a6: 00e2 lsls r2, r4, #3
|
|
80058a8: 4614 mov r4, r2
|
|
80058aa: 461d mov r5, r3
|
|
80058ac: 4643 mov r3, r8
|
|
80058ae: 18e3 adds r3, r4, r3
|
|
80058b0: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
80058b4: 464b mov r3, r9
|
|
80058b6: eb45 0303 adc.w r3, r5, r3
|
|
80058ba: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
80058be: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80058c2: 685b ldr r3, [r3, #4]
|
|
80058c4: 2200 movs r2, #0
|
|
80058c6: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
80058ca: f8c7 2094 str.w r2, [r7, #148] @ 0x94
|
|
80058ce: f04f 0200 mov.w r2, #0
|
|
80058d2: f04f 0300 mov.w r3, #0
|
|
80058d6: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
|
|
80058da: 4629 mov r1, r5
|
|
80058dc: 008b lsls r3, r1, #2
|
|
80058de: 4621 mov r1, r4
|
|
80058e0: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
80058e4: 4621 mov r1, r4
|
|
80058e6: 008a lsls r2, r1, #2
|
|
80058e8: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98
|
|
80058ec: f7fa fc8a bl 8000204 <__aeabi_uldivmod>
|
|
80058f0: 4602 mov r2, r0
|
|
80058f2: 460b mov r3, r1
|
|
80058f4: 4b60 ldr r3, [pc, #384] @ (8005a78 <UART_SetConfig+0x4e4>)
|
|
80058f6: fba3 2302 umull r2, r3, r3, r2
|
|
80058fa: 095b lsrs r3, r3, #5
|
|
80058fc: 011c lsls r4, r3, #4
|
|
80058fe: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8005902: 2200 movs r2, #0
|
|
8005904: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
8005908: f8c7 208c str.w r2, [r7, #140] @ 0x8c
|
|
800590c: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88
|
|
8005910: 4642 mov r2, r8
|
|
8005912: 464b mov r3, r9
|
|
8005914: 1891 adds r1, r2, r2
|
|
8005916: 61b9 str r1, [r7, #24]
|
|
8005918: 415b adcs r3, r3
|
|
800591a: 61fb str r3, [r7, #28]
|
|
800591c: e9d7 2306 ldrd r2, r3, [r7, #24]
|
|
8005920: 4641 mov r1, r8
|
|
8005922: 1851 adds r1, r2, r1
|
|
8005924: 6139 str r1, [r7, #16]
|
|
8005926: 4649 mov r1, r9
|
|
8005928: 414b adcs r3, r1
|
|
800592a: 617b str r3, [r7, #20]
|
|
800592c: f04f 0200 mov.w r2, #0
|
|
8005930: f04f 0300 mov.w r3, #0
|
|
8005934: e9d7 ab04 ldrd sl, fp, [r7, #16]
|
|
8005938: 4659 mov r1, fp
|
|
800593a: 00cb lsls r3, r1, #3
|
|
800593c: 4651 mov r1, sl
|
|
800593e: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8005942: 4651 mov r1, sl
|
|
8005944: 00ca lsls r2, r1, #3
|
|
8005946: 4610 mov r0, r2
|
|
8005948: 4619 mov r1, r3
|
|
800594a: 4603 mov r3, r0
|
|
800594c: 4642 mov r2, r8
|
|
800594e: 189b adds r3, r3, r2
|
|
8005950: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8005954: 464b mov r3, r9
|
|
8005956: 460a mov r2, r1
|
|
8005958: eb42 0303 adc.w r3, r2, r3
|
|
800595c: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8005960: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005964: 685b ldr r3, [r3, #4]
|
|
8005966: 2200 movs r2, #0
|
|
8005968: 67bb str r3, [r7, #120] @ 0x78
|
|
800596a: 67fa str r2, [r7, #124] @ 0x7c
|
|
800596c: f04f 0200 mov.w r2, #0
|
|
8005970: f04f 0300 mov.w r3, #0
|
|
8005974: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78
|
|
8005978: 4649 mov r1, r9
|
|
800597a: 008b lsls r3, r1, #2
|
|
800597c: 4641 mov r1, r8
|
|
800597e: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8005982: 4641 mov r1, r8
|
|
8005984: 008a lsls r2, r1, #2
|
|
8005986: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80
|
|
800598a: f7fa fc3b bl 8000204 <__aeabi_uldivmod>
|
|
800598e: 4602 mov r2, r0
|
|
8005990: 460b mov r3, r1
|
|
8005992: 4611 mov r1, r2
|
|
8005994: 4b38 ldr r3, [pc, #224] @ (8005a78 <UART_SetConfig+0x4e4>)
|
|
8005996: fba3 2301 umull r2, r3, r3, r1
|
|
800599a: 095b lsrs r3, r3, #5
|
|
800599c: 2264 movs r2, #100 @ 0x64
|
|
800599e: fb02 f303 mul.w r3, r2, r3
|
|
80059a2: 1acb subs r3, r1, r3
|
|
80059a4: 011b lsls r3, r3, #4
|
|
80059a6: 3332 adds r3, #50 @ 0x32
|
|
80059a8: 4a33 ldr r2, [pc, #204] @ (8005a78 <UART_SetConfig+0x4e4>)
|
|
80059aa: fba2 2303 umull r2, r3, r2, r3
|
|
80059ae: 095b lsrs r3, r3, #5
|
|
80059b0: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
80059b4: 441c add r4, r3
|
|
80059b6: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80059ba: 2200 movs r2, #0
|
|
80059bc: 673b str r3, [r7, #112] @ 0x70
|
|
80059be: 677a str r2, [r7, #116] @ 0x74
|
|
80059c0: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70
|
|
80059c4: 4642 mov r2, r8
|
|
80059c6: 464b mov r3, r9
|
|
80059c8: 1891 adds r1, r2, r2
|
|
80059ca: 60b9 str r1, [r7, #8]
|
|
80059cc: 415b adcs r3, r3
|
|
80059ce: 60fb str r3, [r7, #12]
|
|
80059d0: e9d7 2302 ldrd r2, r3, [r7, #8]
|
|
80059d4: 4641 mov r1, r8
|
|
80059d6: 1851 adds r1, r2, r1
|
|
80059d8: 6039 str r1, [r7, #0]
|
|
80059da: 4649 mov r1, r9
|
|
80059dc: 414b adcs r3, r1
|
|
80059de: 607b str r3, [r7, #4]
|
|
80059e0: f04f 0200 mov.w r2, #0
|
|
80059e4: f04f 0300 mov.w r3, #0
|
|
80059e8: e9d7 ab00 ldrd sl, fp, [r7]
|
|
80059ec: 4659 mov r1, fp
|
|
80059ee: 00cb lsls r3, r1, #3
|
|
80059f0: 4651 mov r1, sl
|
|
80059f2: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
80059f6: 4651 mov r1, sl
|
|
80059f8: 00ca lsls r2, r1, #3
|
|
80059fa: 4610 mov r0, r2
|
|
80059fc: 4619 mov r1, r3
|
|
80059fe: 4603 mov r3, r0
|
|
8005a00: 4642 mov r2, r8
|
|
8005a02: 189b adds r3, r3, r2
|
|
8005a04: 66bb str r3, [r7, #104] @ 0x68
|
|
8005a06: 464b mov r3, r9
|
|
8005a08: 460a mov r2, r1
|
|
8005a0a: eb42 0303 adc.w r3, r2, r3
|
|
8005a0e: 66fb str r3, [r7, #108] @ 0x6c
|
|
8005a10: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005a14: 685b ldr r3, [r3, #4]
|
|
8005a16: 2200 movs r2, #0
|
|
8005a18: 663b str r3, [r7, #96] @ 0x60
|
|
8005a1a: 667a str r2, [r7, #100] @ 0x64
|
|
8005a1c: f04f 0200 mov.w r2, #0
|
|
8005a20: f04f 0300 mov.w r3, #0
|
|
8005a24: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60
|
|
8005a28: 4649 mov r1, r9
|
|
8005a2a: 008b lsls r3, r1, #2
|
|
8005a2c: 4641 mov r1, r8
|
|
8005a2e: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8005a32: 4641 mov r1, r8
|
|
8005a34: 008a lsls r2, r1, #2
|
|
8005a36: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68
|
|
8005a3a: f7fa fbe3 bl 8000204 <__aeabi_uldivmod>
|
|
8005a3e: 4602 mov r2, r0
|
|
8005a40: 460b mov r3, r1
|
|
8005a42: 4b0d ldr r3, [pc, #52] @ (8005a78 <UART_SetConfig+0x4e4>)
|
|
8005a44: fba3 1302 umull r1, r3, r3, r2
|
|
8005a48: 095b lsrs r3, r3, #5
|
|
8005a4a: 2164 movs r1, #100 @ 0x64
|
|
8005a4c: fb01 f303 mul.w r3, r1, r3
|
|
8005a50: 1ad3 subs r3, r2, r3
|
|
8005a52: 011b lsls r3, r3, #4
|
|
8005a54: 3332 adds r3, #50 @ 0x32
|
|
8005a56: 4a08 ldr r2, [pc, #32] @ (8005a78 <UART_SetConfig+0x4e4>)
|
|
8005a58: fba2 2303 umull r2, r3, r2, r3
|
|
8005a5c: 095b lsrs r3, r3, #5
|
|
8005a5e: f003 020f and.w r2, r3, #15
|
|
8005a62: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005a66: 681b ldr r3, [r3, #0]
|
|
8005a68: 4422 add r2, r4
|
|
8005a6a: 609a str r2, [r3, #8]
|
|
}
|
|
8005a6c: bf00 nop
|
|
8005a6e: f507 7780 add.w r7, r7, #256 @ 0x100
|
|
8005a72: 46bd mov sp, r7
|
|
8005a74: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8005a78: 51eb851f .word 0x51eb851f
|
|
|
|
08005a7c <USB_CoreInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8005a7c: b084 sub sp, #16
|
|
8005a7e: b580 push {r7, lr}
|
|
8005a80: b084 sub sp, #16
|
|
8005a82: af00 add r7, sp, #0
|
|
8005a84: 6078 str r0, [r7, #4]
|
|
8005a86: f107 001c add.w r0, r7, #28
|
|
8005a8a: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret;
|
|
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
|
|
8005a8e: f897 3021 ldrb.w r3, [r7, #33] @ 0x21
|
|
8005a92: 2b01 cmp r3, #1
|
|
8005a94: d123 bne.n 8005ade <USB_CoreInit+0x62>
|
|
{
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
8005a96: 687b ldr r3, [r7, #4]
|
|
8005a98: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005a9a: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
8005a9e: 687b ldr r3, [r7, #4]
|
|
8005aa0: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Init The ULPI Interface */
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
|
|
8005aa2: 687b ldr r3, [r7, #4]
|
|
8005aa4: 68db ldr r3, [r3, #12]
|
|
8005aa6: f423 0384 bic.w r3, r3, #4325376 @ 0x420000
|
|
8005aaa: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005aae: 687a ldr r2, [r7, #4]
|
|
8005ab0: 60d3 str r3, [r2, #12]
|
|
|
|
/* Select vbus source */
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
|
|
8005ab2: 687b ldr r3, [r7, #4]
|
|
8005ab4: 68db ldr r3, [r3, #12]
|
|
8005ab6: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
8005aba: 687b ldr r3, [r7, #4]
|
|
8005abc: 60da str r2, [r3, #12]
|
|
if (cfg.use_external_vbus == 1U)
|
|
8005abe: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8005ac2: 2b01 cmp r3, #1
|
|
8005ac4: d105 bne.n 8005ad2 <USB_CoreInit+0x56>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
|
|
8005ac6: 687b ldr r3, [r7, #4]
|
|
8005ac8: 68db ldr r3, [r3, #12]
|
|
8005aca: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
|
|
8005ace: 687b ldr r3, [r7, #4]
|
|
8005ad0: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
8005ad2: 6878 ldr r0, [r7, #4]
|
|
8005ad4: f001 fae2 bl 800709c <USB_CoreReset>
|
|
8005ad8: 4603 mov r3, r0
|
|
8005ada: 73fb strb r3, [r7, #15]
|
|
8005adc: e01b b.n 8005b16 <USB_CoreInit+0x9a>
|
|
}
|
|
else /* FS interface (embedded Phy) */
|
|
{
|
|
/* Select FS Embedded PHY */
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
|
|
8005ade: 687b ldr r3, [r7, #4]
|
|
8005ae0: 68db ldr r3, [r3, #12]
|
|
8005ae2: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
8005ae6: 687b ldr r3, [r7, #4]
|
|
8005ae8: 60da str r2, [r3, #12]
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
8005aea: 6878 ldr r0, [r7, #4]
|
|
8005aec: f001 fad6 bl 800709c <USB_CoreReset>
|
|
8005af0: 4603 mov r3, r0
|
|
8005af2: 73fb strb r3, [r7, #15]
|
|
|
|
if (cfg.battery_charging_enable == 0U)
|
|
8005af4: f897 3025 ldrb.w r3, [r7, #37] @ 0x25
|
|
8005af8: 2b00 cmp r3, #0
|
|
8005afa: d106 bne.n 8005b0a <USB_CoreInit+0x8e>
|
|
{
|
|
/* Activate the USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
8005afc: 687b ldr r3, [r7, #4]
|
|
8005afe: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005b00: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
8005b04: 687b ldr r3, [r7, #4]
|
|
8005b06: 639a str r2, [r3, #56] @ 0x38
|
|
8005b08: e005 b.n 8005b16 <USB_CoreInit+0x9a>
|
|
}
|
|
else
|
|
{
|
|
/* Deactivate the USB Transceiver */
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
8005b0a: 687b ldr r3, [r7, #4]
|
|
8005b0c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005b0e: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
8005b12: 687b ldr r3, [r7, #4]
|
|
8005b14: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
}
|
|
|
|
if (cfg.dma_enable == 1U)
|
|
8005b16: 7fbb ldrb r3, [r7, #30]
|
|
8005b18: 2b01 cmp r3, #1
|
|
8005b1a: d10b bne.n 8005b34 <USB_CoreInit+0xb8>
|
|
{
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
|
|
8005b1c: 687b ldr r3, [r7, #4]
|
|
8005b1e: 689b ldr r3, [r3, #8]
|
|
8005b20: f043 0206 orr.w r2, r3, #6
|
|
8005b24: 687b ldr r3, [r7, #4]
|
|
8005b26: 609a str r2, [r3, #8]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
|
|
8005b28: 687b ldr r3, [r7, #4]
|
|
8005b2a: 689b ldr r3, [r3, #8]
|
|
8005b2c: f043 0220 orr.w r2, r3, #32
|
|
8005b30: 687b ldr r3, [r7, #4]
|
|
8005b32: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
return ret;
|
|
8005b34: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8005b36: 4618 mov r0, r3
|
|
8005b38: 3710 adds r7, #16
|
|
8005b3a: 46bd mov sp, r7
|
|
8005b3c: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
8005b40: b004 add sp, #16
|
|
8005b42: 4770 bx lr
|
|
|
|
08005b44 <USB_SetTurnaroundTime>:
|
|
* @param hclk: AHB clock frequency
|
|
* @retval USB turnaround time In PHY Clocks number
|
|
*/
|
|
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
|
|
uint32_t hclk, uint8_t speed)
|
|
{
|
|
8005b44: b480 push {r7}
|
|
8005b46: b087 sub sp, #28
|
|
8005b48: af00 add r7, sp, #0
|
|
8005b4a: 60f8 str r0, [r7, #12]
|
|
8005b4c: 60b9 str r1, [r7, #8]
|
|
8005b4e: 4613 mov r3, r2
|
|
8005b50: 71fb strb r3, [r7, #7]
|
|
|
|
/* The USBTRD is configured according to the tables below, depending on AHB frequency
|
|
used by application. In the low AHB frequency range it is used to stretch enough the USB response
|
|
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
|
|
latency to the Data FIFO */
|
|
if (speed == USBD_FS_SPEED)
|
|
8005b52: 79fb ldrb r3, [r7, #7]
|
|
8005b54: 2b02 cmp r3, #2
|
|
8005b56: d165 bne.n 8005c24 <USB_SetTurnaroundTime+0xe0>
|
|
{
|
|
if ((hclk >= 14200000U) && (hclk < 15000000U))
|
|
8005b58: 68bb ldr r3, [r7, #8]
|
|
8005b5a: 4a41 ldr r2, [pc, #260] @ (8005c60 <USB_SetTurnaroundTime+0x11c>)
|
|
8005b5c: 4293 cmp r3, r2
|
|
8005b5e: d906 bls.n 8005b6e <USB_SetTurnaroundTime+0x2a>
|
|
8005b60: 68bb ldr r3, [r7, #8]
|
|
8005b62: 4a40 ldr r2, [pc, #256] @ (8005c64 <USB_SetTurnaroundTime+0x120>)
|
|
8005b64: 4293 cmp r3, r2
|
|
8005b66: d202 bcs.n 8005b6e <USB_SetTurnaroundTime+0x2a>
|
|
{
|
|
/* hclk Clock Range between 14.2-15 MHz */
|
|
UsbTrd = 0xFU;
|
|
8005b68: 230f movs r3, #15
|
|
8005b6a: 617b str r3, [r7, #20]
|
|
8005b6c: e062 b.n 8005c34 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 15000000U) && (hclk < 16000000U))
|
|
8005b6e: 68bb ldr r3, [r7, #8]
|
|
8005b70: 4a3c ldr r2, [pc, #240] @ (8005c64 <USB_SetTurnaroundTime+0x120>)
|
|
8005b72: 4293 cmp r3, r2
|
|
8005b74: d306 bcc.n 8005b84 <USB_SetTurnaroundTime+0x40>
|
|
8005b76: 68bb ldr r3, [r7, #8]
|
|
8005b78: 4a3b ldr r2, [pc, #236] @ (8005c68 <USB_SetTurnaroundTime+0x124>)
|
|
8005b7a: 4293 cmp r3, r2
|
|
8005b7c: d202 bcs.n 8005b84 <USB_SetTurnaroundTime+0x40>
|
|
{
|
|
/* hclk Clock Range between 15-16 MHz */
|
|
UsbTrd = 0xEU;
|
|
8005b7e: 230e movs r3, #14
|
|
8005b80: 617b str r3, [r7, #20]
|
|
8005b82: e057 b.n 8005c34 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 16000000U) && (hclk < 17200000U))
|
|
8005b84: 68bb ldr r3, [r7, #8]
|
|
8005b86: 4a38 ldr r2, [pc, #224] @ (8005c68 <USB_SetTurnaroundTime+0x124>)
|
|
8005b88: 4293 cmp r3, r2
|
|
8005b8a: d306 bcc.n 8005b9a <USB_SetTurnaroundTime+0x56>
|
|
8005b8c: 68bb ldr r3, [r7, #8]
|
|
8005b8e: 4a37 ldr r2, [pc, #220] @ (8005c6c <USB_SetTurnaroundTime+0x128>)
|
|
8005b90: 4293 cmp r3, r2
|
|
8005b92: d202 bcs.n 8005b9a <USB_SetTurnaroundTime+0x56>
|
|
{
|
|
/* hclk Clock Range between 16-17.2 MHz */
|
|
UsbTrd = 0xDU;
|
|
8005b94: 230d movs r3, #13
|
|
8005b96: 617b str r3, [r7, #20]
|
|
8005b98: e04c b.n 8005c34 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 17200000U) && (hclk < 18500000U))
|
|
8005b9a: 68bb ldr r3, [r7, #8]
|
|
8005b9c: 4a33 ldr r2, [pc, #204] @ (8005c6c <USB_SetTurnaroundTime+0x128>)
|
|
8005b9e: 4293 cmp r3, r2
|
|
8005ba0: d306 bcc.n 8005bb0 <USB_SetTurnaroundTime+0x6c>
|
|
8005ba2: 68bb ldr r3, [r7, #8]
|
|
8005ba4: 4a32 ldr r2, [pc, #200] @ (8005c70 <USB_SetTurnaroundTime+0x12c>)
|
|
8005ba6: 4293 cmp r3, r2
|
|
8005ba8: d802 bhi.n 8005bb0 <USB_SetTurnaroundTime+0x6c>
|
|
{
|
|
/* hclk Clock Range between 17.2-18.5 MHz */
|
|
UsbTrd = 0xCU;
|
|
8005baa: 230c movs r3, #12
|
|
8005bac: 617b str r3, [r7, #20]
|
|
8005bae: e041 b.n 8005c34 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 18500000U) && (hclk < 20000000U))
|
|
8005bb0: 68bb ldr r3, [r7, #8]
|
|
8005bb2: 4a2f ldr r2, [pc, #188] @ (8005c70 <USB_SetTurnaroundTime+0x12c>)
|
|
8005bb4: 4293 cmp r3, r2
|
|
8005bb6: d906 bls.n 8005bc6 <USB_SetTurnaroundTime+0x82>
|
|
8005bb8: 68bb ldr r3, [r7, #8]
|
|
8005bba: 4a2e ldr r2, [pc, #184] @ (8005c74 <USB_SetTurnaroundTime+0x130>)
|
|
8005bbc: 4293 cmp r3, r2
|
|
8005bbe: d802 bhi.n 8005bc6 <USB_SetTurnaroundTime+0x82>
|
|
{
|
|
/* hclk Clock Range between 18.5-20 MHz */
|
|
UsbTrd = 0xBU;
|
|
8005bc0: 230b movs r3, #11
|
|
8005bc2: 617b str r3, [r7, #20]
|
|
8005bc4: e036 b.n 8005c34 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 20000000U) && (hclk < 21800000U))
|
|
8005bc6: 68bb ldr r3, [r7, #8]
|
|
8005bc8: 4a2a ldr r2, [pc, #168] @ (8005c74 <USB_SetTurnaroundTime+0x130>)
|
|
8005bca: 4293 cmp r3, r2
|
|
8005bcc: d906 bls.n 8005bdc <USB_SetTurnaroundTime+0x98>
|
|
8005bce: 68bb ldr r3, [r7, #8]
|
|
8005bd0: 4a29 ldr r2, [pc, #164] @ (8005c78 <USB_SetTurnaroundTime+0x134>)
|
|
8005bd2: 4293 cmp r3, r2
|
|
8005bd4: d802 bhi.n 8005bdc <USB_SetTurnaroundTime+0x98>
|
|
{
|
|
/* hclk Clock Range between 20-21.8 MHz */
|
|
UsbTrd = 0xAU;
|
|
8005bd6: 230a movs r3, #10
|
|
8005bd8: 617b str r3, [r7, #20]
|
|
8005bda: e02b b.n 8005c34 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 21800000U) && (hclk < 24000000U))
|
|
8005bdc: 68bb ldr r3, [r7, #8]
|
|
8005bde: 4a26 ldr r2, [pc, #152] @ (8005c78 <USB_SetTurnaroundTime+0x134>)
|
|
8005be0: 4293 cmp r3, r2
|
|
8005be2: d906 bls.n 8005bf2 <USB_SetTurnaroundTime+0xae>
|
|
8005be4: 68bb ldr r3, [r7, #8]
|
|
8005be6: 4a25 ldr r2, [pc, #148] @ (8005c7c <USB_SetTurnaroundTime+0x138>)
|
|
8005be8: 4293 cmp r3, r2
|
|
8005bea: d202 bcs.n 8005bf2 <USB_SetTurnaroundTime+0xae>
|
|
{
|
|
/* hclk Clock Range between 21.8-24 MHz */
|
|
UsbTrd = 0x9U;
|
|
8005bec: 2309 movs r3, #9
|
|
8005bee: 617b str r3, [r7, #20]
|
|
8005bf0: e020 b.n 8005c34 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 24000000U) && (hclk < 27700000U))
|
|
8005bf2: 68bb ldr r3, [r7, #8]
|
|
8005bf4: 4a21 ldr r2, [pc, #132] @ (8005c7c <USB_SetTurnaroundTime+0x138>)
|
|
8005bf6: 4293 cmp r3, r2
|
|
8005bf8: d306 bcc.n 8005c08 <USB_SetTurnaroundTime+0xc4>
|
|
8005bfa: 68bb ldr r3, [r7, #8]
|
|
8005bfc: 4a20 ldr r2, [pc, #128] @ (8005c80 <USB_SetTurnaroundTime+0x13c>)
|
|
8005bfe: 4293 cmp r3, r2
|
|
8005c00: d802 bhi.n 8005c08 <USB_SetTurnaroundTime+0xc4>
|
|
{
|
|
/* hclk Clock Range between 24-27.7 MHz */
|
|
UsbTrd = 0x8U;
|
|
8005c02: 2308 movs r3, #8
|
|
8005c04: 617b str r3, [r7, #20]
|
|
8005c06: e015 b.n 8005c34 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 27700000U) && (hclk < 32000000U))
|
|
8005c08: 68bb ldr r3, [r7, #8]
|
|
8005c0a: 4a1d ldr r2, [pc, #116] @ (8005c80 <USB_SetTurnaroundTime+0x13c>)
|
|
8005c0c: 4293 cmp r3, r2
|
|
8005c0e: d906 bls.n 8005c1e <USB_SetTurnaroundTime+0xda>
|
|
8005c10: 68bb ldr r3, [r7, #8]
|
|
8005c12: 4a1c ldr r2, [pc, #112] @ (8005c84 <USB_SetTurnaroundTime+0x140>)
|
|
8005c14: 4293 cmp r3, r2
|
|
8005c16: d202 bcs.n 8005c1e <USB_SetTurnaroundTime+0xda>
|
|
{
|
|
/* hclk Clock Range between 27.7-32 MHz */
|
|
UsbTrd = 0x7U;
|
|
8005c18: 2307 movs r3, #7
|
|
8005c1a: 617b str r3, [r7, #20]
|
|
8005c1c: e00a b.n 8005c34 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else /* if(hclk >= 32000000) */
|
|
{
|
|
/* hclk Clock Range between 32-200 MHz */
|
|
UsbTrd = 0x6U;
|
|
8005c1e: 2306 movs r3, #6
|
|
8005c20: 617b str r3, [r7, #20]
|
|
8005c22: e007 b.n 8005c34 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
}
|
|
else if (speed == USBD_HS_SPEED)
|
|
8005c24: 79fb ldrb r3, [r7, #7]
|
|
8005c26: 2b00 cmp r3, #0
|
|
8005c28: d102 bne.n 8005c30 <USB_SetTurnaroundTime+0xec>
|
|
{
|
|
UsbTrd = USBD_HS_TRDT_VALUE;
|
|
8005c2a: 2309 movs r3, #9
|
|
8005c2c: 617b str r3, [r7, #20]
|
|
8005c2e: e001 b.n 8005c34 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else
|
|
{
|
|
UsbTrd = USBD_DEFAULT_TRDT_VALUE;
|
|
8005c30: 2309 movs r3, #9
|
|
8005c32: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
|
|
8005c34: 68fb ldr r3, [r7, #12]
|
|
8005c36: 68db ldr r3, [r3, #12]
|
|
8005c38: f423 5270 bic.w r2, r3, #15360 @ 0x3c00
|
|
8005c3c: 68fb ldr r3, [r7, #12]
|
|
8005c3e: 60da str r2, [r3, #12]
|
|
USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
|
|
8005c40: 68fb ldr r3, [r7, #12]
|
|
8005c42: 68da ldr r2, [r3, #12]
|
|
8005c44: 697b ldr r3, [r7, #20]
|
|
8005c46: 029b lsls r3, r3, #10
|
|
8005c48: f403 5370 and.w r3, r3, #15360 @ 0x3c00
|
|
8005c4c: 431a orrs r2, r3
|
|
8005c4e: 68fb ldr r3, [r7, #12]
|
|
8005c50: 60da str r2, [r3, #12]
|
|
|
|
return HAL_OK;
|
|
8005c52: 2300 movs r3, #0
|
|
}
|
|
8005c54: 4618 mov r0, r3
|
|
8005c56: 371c adds r7, #28
|
|
8005c58: 46bd mov sp, r7
|
|
8005c5a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005c5e: 4770 bx lr
|
|
8005c60: 00d8acbf .word 0x00d8acbf
|
|
8005c64: 00e4e1c0 .word 0x00e4e1c0
|
|
8005c68: 00f42400 .word 0x00f42400
|
|
8005c6c: 01067380 .word 0x01067380
|
|
8005c70: 011a499f .word 0x011a499f
|
|
8005c74: 01312cff .word 0x01312cff
|
|
8005c78: 014ca43f .word 0x014ca43f
|
|
8005c7c: 016e3600 .word 0x016e3600
|
|
8005c80: 01a6ab1f .word 0x01a6ab1f
|
|
8005c84: 01e84800 .word 0x01e84800
|
|
|
|
08005c88 <USB_EnableGlobalInt>:
|
|
* Enables the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8005c88: b480 push {r7}
|
|
8005c8a: b083 sub sp, #12
|
|
8005c8c: af00 add r7, sp, #0
|
|
8005c8e: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
|
|
8005c90: 687b ldr r3, [r7, #4]
|
|
8005c92: 689b ldr r3, [r3, #8]
|
|
8005c94: f043 0201 orr.w r2, r3, #1
|
|
8005c98: 687b ldr r3, [r7, #4]
|
|
8005c9a: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
8005c9c: 2300 movs r3, #0
|
|
}
|
|
8005c9e: 4618 mov r0, r3
|
|
8005ca0: 370c adds r7, #12
|
|
8005ca2: 46bd mov sp, r7
|
|
8005ca4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005ca8: 4770 bx lr
|
|
|
|
08005caa <USB_DisableGlobalInt>:
|
|
* Disable the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8005caa: b480 push {r7}
|
|
8005cac: b083 sub sp, #12
|
|
8005cae: af00 add r7, sp, #0
|
|
8005cb0: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
|
|
8005cb2: 687b ldr r3, [r7, #4]
|
|
8005cb4: 689b ldr r3, [r3, #8]
|
|
8005cb6: f023 0201 bic.w r2, r3, #1
|
|
8005cba: 687b ldr r3, [r7, #4]
|
|
8005cbc: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
8005cbe: 2300 movs r3, #0
|
|
}
|
|
8005cc0: 4618 mov r0, r3
|
|
8005cc2: 370c adds r7, #12
|
|
8005cc4: 46bd mov sp, r7
|
|
8005cc6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005cca: 4770 bx lr
|
|
|
|
08005ccc <USB_SetCurrentMode>:
|
|
* @arg USB_DEVICE_MODE Peripheral mode
|
|
* @arg USB_HOST_MODE Host mode
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
|
|
{
|
|
8005ccc: b580 push {r7, lr}
|
|
8005cce: b084 sub sp, #16
|
|
8005cd0: af00 add r7, sp, #0
|
|
8005cd2: 6078 str r0, [r7, #4]
|
|
8005cd4: 460b mov r3, r1
|
|
8005cd6: 70fb strb r3, [r7, #3]
|
|
uint32_t ms = 0U;
|
|
8005cd8: 2300 movs r3, #0
|
|
8005cda: 60fb str r3, [r7, #12]
|
|
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
|
|
8005cdc: 687b ldr r3, [r7, #4]
|
|
8005cde: 68db ldr r3, [r3, #12]
|
|
8005ce0: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000
|
|
8005ce4: 687b ldr r3, [r7, #4]
|
|
8005ce6: 60da str r2, [r3, #12]
|
|
|
|
if (mode == USB_HOST_MODE)
|
|
8005ce8: 78fb ldrb r3, [r7, #3]
|
|
8005cea: 2b01 cmp r3, #1
|
|
8005cec: d115 bne.n 8005d1a <USB_SetCurrentMode+0x4e>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
|
|
8005cee: 687b ldr r3, [r7, #4]
|
|
8005cf0: 68db ldr r3, [r3, #12]
|
|
8005cf2: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000
|
|
8005cf6: 687b ldr r3, [r7, #4]
|
|
8005cf8: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
8005cfa: 200a movs r0, #10
|
|
8005cfc: f7fb fc18 bl 8001530 <HAL_Delay>
|
|
ms += 10U;
|
|
8005d00: 68fb ldr r3, [r7, #12]
|
|
8005d02: 330a adds r3, #10
|
|
8005d04: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
8005d06: 6878 ldr r0, [r7, #4]
|
|
8005d08: f001 f939 bl 8006f7e <USB_GetMode>
|
|
8005d0c: 4603 mov r3, r0
|
|
8005d0e: 2b01 cmp r3, #1
|
|
8005d10: d01e beq.n 8005d50 <USB_SetCurrentMode+0x84>
|
|
8005d12: 68fb ldr r3, [r7, #12]
|
|
8005d14: 2bc7 cmp r3, #199 @ 0xc7
|
|
8005d16: d9f0 bls.n 8005cfa <USB_SetCurrentMode+0x2e>
|
|
8005d18: e01a b.n 8005d50 <USB_SetCurrentMode+0x84>
|
|
}
|
|
else if (mode == USB_DEVICE_MODE)
|
|
8005d1a: 78fb ldrb r3, [r7, #3]
|
|
8005d1c: 2b00 cmp r3, #0
|
|
8005d1e: d115 bne.n 8005d4c <USB_SetCurrentMode+0x80>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
|
|
8005d20: 687b ldr r3, [r7, #4]
|
|
8005d22: 68db ldr r3, [r3, #12]
|
|
8005d24: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000
|
|
8005d28: 687b ldr r3, [r7, #4]
|
|
8005d2a: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
8005d2c: 200a movs r0, #10
|
|
8005d2e: f7fb fbff bl 8001530 <HAL_Delay>
|
|
ms += 10U;
|
|
8005d32: 68fb ldr r3, [r7, #12]
|
|
8005d34: 330a adds r3, #10
|
|
8005d36: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
8005d38: 6878 ldr r0, [r7, #4]
|
|
8005d3a: f001 f920 bl 8006f7e <USB_GetMode>
|
|
8005d3e: 4603 mov r3, r0
|
|
8005d40: 2b00 cmp r3, #0
|
|
8005d42: d005 beq.n 8005d50 <USB_SetCurrentMode+0x84>
|
|
8005d44: 68fb ldr r3, [r7, #12]
|
|
8005d46: 2bc7 cmp r3, #199 @ 0xc7
|
|
8005d48: d9f0 bls.n 8005d2c <USB_SetCurrentMode+0x60>
|
|
8005d4a: e001 b.n 8005d50 <USB_SetCurrentMode+0x84>
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
8005d4c: 2301 movs r3, #1
|
|
8005d4e: e005 b.n 8005d5c <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
|
|
8005d50: 68fb ldr r3, [r7, #12]
|
|
8005d52: 2bc8 cmp r3, #200 @ 0xc8
|
|
8005d54: d101 bne.n 8005d5a <USB_SetCurrentMode+0x8e>
|
|
{
|
|
return HAL_ERROR;
|
|
8005d56: 2301 movs r3, #1
|
|
8005d58: e000 b.n 8005d5c <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8005d5a: 2300 movs r3, #0
|
|
}
|
|
8005d5c: 4618 mov r0, r3
|
|
8005d5e: 3710 adds r7, #16
|
|
8005d60: 46bd mov sp, r7
|
|
8005d62: bd80 pop {r7, pc}
|
|
|
|
08005d64 <USB_DevInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8005d64: b084 sub sp, #16
|
|
8005d66: b580 push {r7, lr}
|
|
8005d68: b086 sub sp, #24
|
|
8005d6a: af00 add r7, sp, #0
|
|
8005d6c: 6078 str r0, [r7, #4]
|
|
8005d6e: f107 0024 add.w r0, r7, #36 @ 0x24
|
|
8005d72: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8005d76: 2300 movs r3, #0
|
|
8005d78: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8005d7a: 687b ldr r3, [r7, #4]
|
|
8005d7c: 60fb str r3, [r7, #12]
|
|
uint32_t i;
|
|
|
|
for (i = 0U; i < 15U; i++)
|
|
8005d7e: 2300 movs r3, #0
|
|
8005d80: 613b str r3, [r7, #16]
|
|
8005d82: e009 b.n 8005d98 <USB_DevInit+0x34>
|
|
{
|
|
USBx->DIEPTXF[i] = 0U;
|
|
8005d84: 687a ldr r2, [r7, #4]
|
|
8005d86: 693b ldr r3, [r7, #16]
|
|
8005d88: 3340 adds r3, #64 @ 0x40
|
|
8005d8a: 009b lsls r3, r3, #2
|
|
8005d8c: 4413 add r3, r2
|
|
8005d8e: 2200 movs r2, #0
|
|
8005d90: 605a str r2, [r3, #4]
|
|
for (i = 0U; i < 15U; i++)
|
|
8005d92: 693b ldr r3, [r7, #16]
|
|
8005d94: 3301 adds r3, #1
|
|
8005d96: 613b str r3, [r7, #16]
|
|
8005d98: 693b ldr r3, [r7, #16]
|
|
8005d9a: 2b0e cmp r3, #14
|
|
8005d9c: d9f2 bls.n 8005d84 <USB_DevInit+0x20>
|
|
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* VBUS Sensing setup */
|
|
if (cfg.vbus_sensing_enable == 0U)
|
|
8005d9e: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
8005da2: 2b00 cmp r3, #0
|
|
8005da4: d11c bne.n 8005de0 <USB_DevInit+0x7c>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
8005da6: 68fb ldr r3, [r7, #12]
|
|
8005da8: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005dac: 685b ldr r3, [r3, #4]
|
|
8005dae: 68fa ldr r2, [r7, #12]
|
|
8005db0: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8005db4: f043 0302 orr.w r3, r3, #2
|
|
8005db8: 6053 str r3, [r2, #4]
|
|
|
|
/* Deactivate VBUS Sensing B */
|
|
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
|
|
8005dba: 687b ldr r3, [r7, #4]
|
|
8005dbc: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005dbe: f423 1200 bic.w r2, r3, #2097152 @ 0x200000
|
|
8005dc2: 687b ldr r3, [r7, #4]
|
|
8005dc4: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* B-peripheral session valid override enable */
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
|
|
8005dc6: 687b ldr r3, [r7, #4]
|
|
8005dc8: 681b ldr r3, [r3, #0]
|
|
8005dca: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
8005dce: 687b ldr r3, [r7, #4]
|
|
8005dd0: 601a str r2, [r3, #0]
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
|
|
8005dd2: 687b ldr r3, [r7, #4]
|
|
8005dd4: 681b ldr r3, [r3, #0]
|
|
8005dd6: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
8005dda: 687b ldr r3, [r7, #4]
|
|
8005ddc: 601a str r2, [r3, #0]
|
|
8005dde: e005 b.n 8005dec <USB_DevInit+0x88>
|
|
}
|
|
else
|
|
{
|
|
/* Enable HW VBUS sensing */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
|
|
8005de0: 687b ldr r3, [r7, #4]
|
|
8005de2: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005de4: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
|
|
8005de8: 687b ldr r3, [r7, #4]
|
|
8005dea: 639a str r2, [r3, #56] @ 0x38
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
|
|
/* Restart the Phy Clock */
|
|
USBx_PCGCCTL = 0U;
|
|
8005dec: 68fb ldr r3, [r7, #12]
|
|
8005dee: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
8005df2: 461a mov r2, r3
|
|
8005df4: 2300 movs r3, #0
|
|
8005df6: 6013 str r3, [r2, #0]
|
|
|
|
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
|
|
8005df8: f897 3029 ldrb.w r3, [r7, #41] @ 0x29
|
|
8005dfc: 2b01 cmp r3, #1
|
|
8005dfe: d10d bne.n 8005e1c <USB_DevInit+0xb8>
|
|
{
|
|
if (cfg.speed == USBD_HS_SPEED)
|
|
8005e00: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8005e04: 2b00 cmp r3, #0
|
|
8005e06: d104 bne.n 8005e12 <USB_DevInit+0xae>
|
|
{
|
|
/* Set Core speed to High speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
|
|
8005e08: 2100 movs r1, #0
|
|
8005e0a: 6878 ldr r0, [r7, #4]
|
|
8005e0c: f000 f968 bl 80060e0 <USB_SetDevSpeed>
|
|
8005e10: e008 b.n 8005e24 <USB_DevInit+0xc0>
|
|
}
|
|
else
|
|
{
|
|
/* Set Core speed to Full speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
|
|
8005e12: 2101 movs r1, #1
|
|
8005e14: 6878 ldr r0, [r7, #4]
|
|
8005e16: f000 f963 bl 80060e0 <USB_SetDevSpeed>
|
|
8005e1a: e003 b.n 8005e24 <USB_DevInit+0xc0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set Core speed to Full speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
|
|
8005e1c: 2103 movs r1, #3
|
|
8005e1e: 6878 ldr r0, [r7, #4]
|
|
8005e20: f000 f95e bl 80060e0 <USB_SetDevSpeed>
|
|
}
|
|
|
|
/* Flush the FIFOs */
|
|
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
|
|
8005e24: 2110 movs r1, #16
|
|
8005e26: 6878 ldr r0, [r7, #4]
|
|
8005e28: f000 f8fa bl 8006020 <USB_FlushTxFifo>
|
|
8005e2c: 4603 mov r3, r0
|
|
8005e2e: 2b00 cmp r3, #0
|
|
8005e30: d001 beq.n 8005e36 <USB_DevInit+0xd2>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005e32: 2301 movs r3, #1
|
|
8005e34: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (USB_FlushRxFifo(USBx) != HAL_OK)
|
|
8005e36: 6878 ldr r0, [r7, #4]
|
|
8005e38: f000 f924 bl 8006084 <USB_FlushRxFifo>
|
|
8005e3c: 4603 mov r3, r0
|
|
8005e3e: 2b00 cmp r3, #0
|
|
8005e40: d001 beq.n 8005e46 <USB_DevInit+0xe2>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005e42: 2301 movs r3, #1
|
|
8005e44: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Clear all pending Device Interrupts */
|
|
USBx_DEVICE->DIEPMSK = 0U;
|
|
8005e46: 68fb ldr r3, [r7, #12]
|
|
8005e48: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005e4c: 461a mov r2, r3
|
|
8005e4e: 2300 movs r3, #0
|
|
8005e50: 6113 str r3, [r2, #16]
|
|
USBx_DEVICE->DOEPMSK = 0U;
|
|
8005e52: 68fb ldr r3, [r7, #12]
|
|
8005e54: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005e58: 461a mov r2, r3
|
|
8005e5a: 2300 movs r3, #0
|
|
8005e5c: 6153 str r3, [r2, #20]
|
|
USBx_DEVICE->DAINTMSK = 0U;
|
|
8005e5e: 68fb ldr r3, [r7, #12]
|
|
8005e60: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005e64: 461a mov r2, r3
|
|
8005e66: 2300 movs r3, #0
|
|
8005e68: 61d3 str r3, [r2, #28]
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8005e6a: 2300 movs r3, #0
|
|
8005e6c: 613b str r3, [r7, #16]
|
|
8005e6e: e043 b.n 8005ef8 <USB_DevInit+0x194>
|
|
{
|
|
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
8005e70: 693b ldr r3, [r7, #16]
|
|
8005e72: 015a lsls r2, r3, #5
|
|
8005e74: 68fb ldr r3, [r7, #12]
|
|
8005e76: 4413 add r3, r2
|
|
8005e78: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005e7c: 681b ldr r3, [r3, #0]
|
|
8005e7e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8005e82: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8005e86: d118 bne.n 8005eba <USB_DevInit+0x156>
|
|
{
|
|
if (i == 0U)
|
|
8005e88: 693b ldr r3, [r7, #16]
|
|
8005e8a: 2b00 cmp r3, #0
|
|
8005e8c: d10a bne.n 8005ea4 <USB_DevInit+0x140>
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
|
|
8005e8e: 693b ldr r3, [r7, #16]
|
|
8005e90: 015a lsls r2, r3, #5
|
|
8005e92: 68fb ldr r3, [r7, #12]
|
|
8005e94: 4413 add r3, r2
|
|
8005e96: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005e9a: 461a mov r2, r3
|
|
8005e9c: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
8005ea0: 6013 str r3, [r2, #0]
|
|
8005ea2: e013 b.n 8005ecc <USB_DevInit+0x168>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
|
|
8005ea4: 693b ldr r3, [r7, #16]
|
|
8005ea6: 015a lsls r2, r3, #5
|
|
8005ea8: 68fb ldr r3, [r7, #12]
|
|
8005eaa: 4413 add r3, r2
|
|
8005eac: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005eb0: 461a mov r2, r3
|
|
8005eb2: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
8005eb6: 6013 str r3, [r2, #0]
|
|
8005eb8: e008 b.n 8005ecc <USB_DevInit+0x168>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = 0U;
|
|
8005eba: 693b ldr r3, [r7, #16]
|
|
8005ebc: 015a lsls r2, r3, #5
|
|
8005ebe: 68fb ldr r3, [r7, #12]
|
|
8005ec0: 4413 add r3, r2
|
|
8005ec2: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005ec6: 461a mov r2, r3
|
|
8005ec8: 2300 movs r3, #0
|
|
8005eca: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_INEP(i)->DIEPTSIZ = 0U;
|
|
8005ecc: 693b ldr r3, [r7, #16]
|
|
8005ece: 015a lsls r2, r3, #5
|
|
8005ed0: 68fb ldr r3, [r7, #12]
|
|
8005ed2: 4413 add r3, r2
|
|
8005ed4: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005ed8: 461a mov r2, r3
|
|
8005eda: 2300 movs r3, #0
|
|
8005edc: 6113 str r3, [r2, #16]
|
|
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
|
8005ede: 693b ldr r3, [r7, #16]
|
|
8005ee0: 015a lsls r2, r3, #5
|
|
8005ee2: 68fb ldr r3, [r7, #12]
|
|
8005ee4: 4413 add r3, r2
|
|
8005ee6: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005eea: 461a mov r2, r3
|
|
8005eec: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
8005ef0: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8005ef2: 693b ldr r3, [r7, #16]
|
|
8005ef4: 3301 adds r3, #1
|
|
8005ef6: 613b str r3, [r7, #16]
|
|
8005ef8: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
8005efc: 461a mov r2, r3
|
|
8005efe: 693b ldr r3, [r7, #16]
|
|
8005f00: 4293 cmp r3, r2
|
|
8005f02: d3b5 bcc.n 8005e70 <USB_DevInit+0x10c>
|
|
}
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8005f04: 2300 movs r3, #0
|
|
8005f06: 613b str r3, [r7, #16]
|
|
8005f08: e043 b.n 8005f92 <USB_DevInit+0x22e>
|
|
{
|
|
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
8005f0a: 693b ldr r3, [r7, #16]
|
|
8005f0c: 015a lsls r2, r3, #5
|
|
8005f0e: 68fb ldr r3, [r7, #12]
|
|
8005f10: 4413 add r3, r2
|
|
8005f12: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005f16: 681b ldr r3, [r3, #0]
|
|
8005f18: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8005f1c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8005f20: d118 bne.n 8005f54 <USB_DevInit+0x1f0>
|
|
{
|
|
if (i == 0U)
|
|
8005f22: 693b ldr r3, [r7, #16]
|
|
8005f24: 2b00 cmp r3, #0
|
|
8005f26: d10a bne.n 8005f3e <USB_DevInit+0x1da>
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
|
|
8005f28: 693b ldr r3, [r7, #16]
|
|
8005f2a: 015a lsls r2, r3, #5
|
|
8005f2c: 68fb ldr r3, [r7, #12]
|
|
8005f2e: 4413 add r3, r2
|
|
8005f30: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005f34: 461a mov r2, r3
|
|
8005f36: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
8005f3a: 6013 str r3, [r2, #0]
|
|
8005f3c: e013 b.n 8005f66 <USB_DevInit+0x202>
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
|
|
8005f3e: 693b ldr r3, [r7, #16]
|
|
8005f40: 015a lsls r2, r3, #5
|
|
8005f42: 68fb ldr r3, [r7, #12]
|
|
8005f44: 4413 add r3, r2
|
|
8005f46: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005f4a: 461a mov r2, r3
|
|
8005f4c: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
8005f50: 6013 str r3, [r2, #0]
|
|
8005f52: e008 b.n 8005f66 <USB_DevInit+0x202>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = 0U;
|
|
8005f54: 693b ldr r3, [r7, #16]
|
|
8005f56: 015a lsls r2, r3, #5
|
|
8005f58: 68fb ldr r3, [r7, #12]
|
|
8005f5a: 4413 add r3, r2
|
|
8005f5c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005f60: 461a mov r2, r3
|
|
8005f62: 2300 movs r3, #0
|
|
8005f64: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_OUTEP(i)->DOEPTSIZ = 0U;
|
|
8005f66: 693b ldr r3, [r7, #16]
|
|
8005f68: 015a lsls r2, r3, #5
|
|
8005f6a: 68fb ldr r3, [r7, #12]
|
|
8005f6c: 4413 add r3, r2
|
|
8005f6e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005f72: 461a mov r2, r3
|
|
8005f74: 2300 movs r3, #0
|
|
8005f76: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
|
8005f78: 693b ldr r3, [r7, #16]
|
|
8005f7a: 015a lsls r2, r3, #5
|
|
8005f7c: 68fb ldr r3, [r7, #12]
|
|
8005f7e: 4413 add r3, r2
|
|
8005f80: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005f84: 461a mov r2, r3
|
|
8005f86: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
8005f8a: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8005f8c: 693b ldr r3, [r7, #16]
|
|
8005f8e: 3301 adds r3, #1
|
|
8005f90: 613b str r3, [r7, #16]
|
|
8005f92: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
8005f96: 461a mov r2, r3
|
|
8005f98: 693b ldr r3, [r7, #16]
|
|
8005f9a: 4293 cmp r3, r2
|
|
8005f9c: d3b5 bcc.n 8005f0a <USB_DevInit+0x1a6>
|
|
}
|
|
|
|
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
|
|
8005f9e: 68fb ldr r3, [r7, #12]
|
|
8005fa0: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005fa4: 691b ldr r3, [r3, #16]
|
|
8005fa6: 68fa ldr r2, [r7, #12]
|
|
8005fa8: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8005fac: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8005fb0: 6113 str r3, [r2, #16]
|
|
|
|
/* Disable all interrupts. */
|
|
USBx->GINTMSK = 0U;
|
|
8005fb2: 687b ldr r3, [r7, #4]
|
|
8005fb4: 2200 movs r2, #0
|
|
8005fb6: 619a str r2, [r3, #24]
|
|
|
|
/* Clear any pending interrupts */
|
|
USBx->GINTSTS = 0xBFFFFFFFU;
|
|
8005fb8: 687b ldr r3, [r7, #4]
|
|
8005fba: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000
|
|
8005fbe: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the common interrupts */
|
|
if (cfg.dma_enable == 0U)
|
|
8005fc0: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
|
|
8005fc4: 2b00 cmp r3, #0
|
|
8005fc6: d105 bne.n 8005fd4 <USB_DevInit+0x270>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
|
|
8005fc8: 687b ldr r3, [r7, #4]
|
|
8005fca: 699b ldr r3, [r3, #24]
|
|
8005fcc: f043 0210 orr.w r2, r3, #16
|
|
8005fd0: 687b ldr r3, [r7, #4]
|
|
8005fd2: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
/* Enable interrupts matching to the Device mode ONLY */
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
|
|
8005fd4: 687b ldr r3, [r7, #4]
|
|
8005fd6: 699a ldr r2, [r3, #24]
|
|
8005fd8: 4b10 ldr r3, [pc, #64] @ (800601c <USB_DevInit+0x2b8>)
|
|
8005fda: 4313 orrs r3, r2
|
|
8005fdc: 687a ldr r2, [r7, #4]
|
|
8005fde: 6193 str r3, [r2, #24]
|
|
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
|
|
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
|
|
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
|
|
|
|
if (cfg.Sof_enable != 0U)
|
|
8005fe0: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
8005fe4: 2b00 cmp r3, #0
|
|
8005fe6: d005 beq.n 8005ff4 <USB_DevInit+0x290>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
|
|
8005fe8: 687b ldr r3, [r7, #4]
|
|
8005fea: 699b ldr r3, [r3, #24]
|
|
8005fec: f043 0208 orr.w r2, r3, #8
|
|
8005ff0: 687b ldr r3, [r7, #4]
|
|
8005ff2: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (cfg.vbus_sensing_enable == 1U)
|
|
8005ff4: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
8005ff8: 2b01 cmp r3, #1
|
|
8005ffa: d107 bne.n 800600c <USB_DevInit+0x2a8>
|
|
{
|
|
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
|
|
8005ffc: 687b ldr r3, [r7, #4]
|
|
8005ffe: 699b ldr r3, [r3, #24]
|
|
8006000: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8006004: f043 0304 orr.w r3, r3, #4
|
|
8006008: 687a ldr r2, [r7, #4]
|
|
800600a: 6193 str r3, [r2, #24]
|
|
}
|
|
|
|
return ret;
|
|
800600c: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800600e: 4618 mov r0, r3
|
|
8006010: 3718 adds r7, #24
|
|
8006012: 46bd mov sp, r7
|
|
8006014: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
8006018: b004 add sp, #16
|
|
800601a: 4770 bx lr
|
|
800601c: 803c3800 .word 0x803c3800
|
|
|
|
08006020 <USB_FlushTxFifo>:
|
|
* This parameter can be a value from 1 to 15
|
|
15 means Flush all Tx FIFOs
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
|
|
{
|
|
8006020: b480 push {r7}
|
|
8006022: b085 sub sp, #20
|
|
8006024: af00 add r7, sp, #0
|
|
8006026: 6078 str r0, [r7, #4]
|
|
8006028: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
800602a: 2300 movs r3, #0
|
|
800602c: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
800602e: 68fb ldr r3, [r7, #12]
|
|
8006030: 3301 adds r3, #1
|
|
8006032: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8006034: 68fb ldr r3, [r7, #12]
|
|
8006036: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800603a: d901 bls.n 8006040 <USB_FlushTxFifo+0x20>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800603c: 2303 movs r3, #3
|
|
800603e: e01b b.n 8006078 <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
8006040: 687b ldr r3, [r7, #4]
|
|
8006042: 691b ldr r3, [r3, #16]
|
|
8006044: 2b00 cmp r3, #0
|
|
8006046: daf2 bge.n 800602e <USB_FlushTxFifo+0xe>
|
|
|
|
/* Flush TX Fifo */
|
|
count = 0U;
|
|
8006048: 2300 movs r3, #0
|
|
800604a: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
|
|
800604c: 683b ldr r3, [r7, #0]
|
|
800604e: 019b lsls r3, r3, #6
|
|
8006050: f043 0220 orr.w r2, r3, #32
|
|
8006054: 687b ldr r3, [r7, #4]
|
|
8006056: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8006058: 68fb ldr r3, [r7, #12]
|
|
800605a: 3301 adds r3, #1
|
|
800605c: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800605e: 68fb ldr r3, [r7, #12]
|
|
8006060: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8006064: d901 bls.n 800606a <USB_FlushTxFifo+0x4a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8006066: 2303 movs r3, #3
|
|
8006068: e006 b.n 8006078 <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
|
|
800606a: 687b ldr r3, [r7, #4]
|
|
800606c: 691b ldr r3, [r3, #16]
|
|
800606e: f003 0320 and.w r3, r3, #32
|
|
8006072: 2b20 cmp r3, #32
|
|
8006074: d0f0 beq.n 8006058 <USB_FlushTxFifo+0x38>
|
|
|
|
return HAL_OK;
|
|
8006076: 2300 movs r3, #0
|
|
}
|
|
8006078: 4618 mov r0, r3
|
|
800607a: 3714 adds r7, #20
|
|
800607c: 46bd mov sp, r7
|
|
800607e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006082: 4770 bx lr
|
|
|
|
08006084 <USB_FlushRxFifo>:
|
|
* @brief USB_FlushRxFifo Flush Rx FIFO
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006084: b480 push {r7}
|
|
8006086: b085 sub sp, #20
|
|
8006088: af00 add r7, sp, #0
|
|
800608a: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
800608c: 2300 movs r3, #0
|
|
800608e: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
8006090: 68fb ldr r3, [r7, #12]
|
|
8006092: 3301 adds r3, #1
|
|
8006094: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8006096: 68fb ldr r3, [r7, #12]
|
|
8006098: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800609c: d901 bls.n 80060a2 <USB_FlushRxFifo+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800609e: 2303 movs r3, #3
|
|
80060a0: e018 b.n 80060d4 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
80060a2: 687b ldr r3, [r7, #4]
|
|
80060a4: 691b ldr r3, [r3, #16]
|
|
80060a6: 2b00 cmp r3, #0
|
|
80060a8: daf2 bge.n 8006090 <USB_FlushRxFifo+0xc>
|
|
|
|
/* Flush RX Fifo */
|
|
count = 0U;
|
|
80060aa: 2300 movs r3, #0
|
|
80060ac: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
|
|
80060ae: 687b ldr r3, [r7, #4]
|
|
80060b0: 2210 movs r2, #16
|
|
80060b2: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
80060b4: 68fb ldr r3, [r7, #12]
|
|
80060b6: 3301 adds r3, #1
|
|
80060b8: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80060ba: 68fb ldr r3, [r7, #12]
|
|
80060bc: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80060c0: d901 bls.n 80060c6 <USB_FlushRxFifo+0x42>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80060c2: 2303 movs r3, #3
|
|
80060c4: e006 b.n 80060d4 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
|
|
80060c6: 687b ldr r3, [r7, #4]
|
|
80060c8: 691b ldr r3, [r3, #16]
|
|
80060ca: f003 0310 and.w r3, r3, #16
|
|
80060ce: 2b10 cmp r3, #16
|
|
80060d0: d0f0 beq.n 80060b4 <USB_FlushRxFifo+0x30>
|
|
|
|
return HAL_OK;
|
|
80060d2: 2300 movs r3, #0
|
|
}
|
|
80060d4: 4618 mov r0, r3
|
|
80060d6: 3714 adds r7, #20
|
|
80060d8: 46bd mov sp, r7
|
|
80060da: f85d 7b04 ldr.w r7, [sp], #4
|
|
80060de: 4770 bx lr
|
|
|
|
080060e0 <USB_SetDevSpeed>:
|
|
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
|
|
* @arg USB_OTG_SPEED_FULL: Full speed mode
|
|
* @retval Hal status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
|
|
{
|
|
80060e0: b480 push {r7}
|
|
80060e2: b085 sub sp, #20
|
|
80060e4: af00 add r7, sp, #0
|
|
80060e6: 6078 str r0, [r7, #4]
|
|
80060e8: 460b mov r3, r1
|
|
80060ea: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80060ec: 687b ldr r3, [r7, #4]
|
|
80060ee: 60fb str r3, [r7, #12]
|
|
|
|
USBx_DEVICE->DCFG |= speed;
|
|
80060f0: 68fb ldr r3, [r7, #12]
|
|
80060f2: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80060f6: 681a ldr r2, [r3, #0]
|
|
80060f8: 78fb ldrb r3, [r7, #3]
|
|
80060fa: 68f9 ldr r1, [r7, #12]
|
|
80060fc: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8006100: 4313 orrs r3, r2
|
|
8006102: 600b str r3, [r1, #0]
|
|
return HAL_OK;
|
|
8006104: 2300 movs r3, #0
|
|
}
|
|
8006106: 4618 mov r0, r3
|
|
8006108: 3714 adds r7, #20
|
|
800610a: 46bd mov sp, r7
|
|
800610c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006110: 4770 bx lr
|
|
|
|
08006112 <USB_GetDevSpeed>:
|
|
* This parameter can be one of these values:
|
|
* @arg USBD_HS_SPEED: High speed mode
|
|
* @arg USBD_FS_SPEED: Full speed mode
|
|
*/
|
|
uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006112: b480 push {r7}
|
|
8006114: b087 sub sp, #28
|
|
8006116: af00 add r7, sp, #0
|
|
8006118: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800611a: 687b ldr r3, [r7, #4]
|
|
800611c: 613b str r3, [r7, #16]
|
|
uint8_t speed;
|
|
uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
|
|
800611e: 693b ldr r3, [r7, #16]
|
|
8006120: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006124: 689b ldr r3, [r3, #8]
|
|
8006126: f003 0306 and.w r3, r3, #6
|
|
800612a: 60fb str r3, [r7, #12]
|
|
|
|
if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
|
|
800612c: 68fb ldr r3, [r7, #12]
|
|
800612e: 2b00 cmp r3, #0
|
|
8006130: d102 bne.n 8006138 <USB_GetDevSpeed+0x26>
|
|
{
|
|
speed = USBD_HS_SPEED;
|
|
8006132: 2300 movs r3, #0
|
|
8006134: 75fb strb r3, [r7, #23]
|
|
8006136: e00a b.n 800614e <USB_GetDevSpeed+0x3c>
|
|
}
|
|
else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
|
|
8006138: 68fb ldr r3, [r7, #12]
|
|
800613a: 2b02 cmp r3, #2
|
|
800613c: d002 beq.n 8006144 <USB_GetDevSpeed+0x32>
|
|
800613e: 68fb ldr r3, [r7, #12]
|
|
8006140: 2b06 cmp r3, #6
|
|
8006142: d102 bne.n 800614a <USB_GetDevSpeed+0x38>
|
|
(DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
|
|
{
|
|
speed = USBD_FS_SPEED;
|
|
8006144: 2302 movs r3, #2
|
|
8006146: 75fb strb r3, [r7, #23]
|
|
8006148: e001 b.n 800614e <USB_GetDevSpeed+0x3c>
|
|
}
|
|
else
|
|
{
|
|
speed = 0xFU;
|
|
800614a: 230f movs r3, #15
|
|
800614c: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return speed;
|
|
800614e: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8006150: 4618 mov r0, r3
|
|
8006152: 371c adds r7, #28
|
|
8006154: 46bd mov sp, r7
|
|
8006156: f85d 7b04 ldr.w r7, [sp], #4
|
|
800615a: 4770 bx lr
|
|
|
|
0800615c <USB_ActivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
800615c: b480 push {r7}
|
|
800615e: b085 sub sp, #20
|
|
8006160: af00 add r7, sp, #0
|
|
8006162: 6078 str r0, [r7, #4]
|
|
8006164: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006166: 687b ldr r3, [r7, #4]
|
|
8006168: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
800616a: 683b ldr r3, [r7, #0]
|
|
800616c: 781b ldrb r3, [r3, #0]
|
|
800616e: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
8006170: 683b ldr r3, [r7, #0]
|
|
8006172: 785b ldrb r3, [r3, #1]
|
|
8006174: 2b01 cmp r3, #1
|
|
8006176: d13a bne.n 80061ee <USB_ActivateEndpoint+0x92>
|
|
{
|
|
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
|
|
8006178: 68fb ldr r3, [r7, #12]
|
|
800617a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800617e: 69da ldr r2, [r3, #28]
|
|
8006180: 683b ldr r3, [r7, #0]
|
|
8006182: 781b ldrb r3, [r3, #0]
|
|
8006184: f003 030f and.w r3, r3, #15
|
|
8006188: 2101 movs r1, #1
|
|
800618a: fa01 f303 lsl.w r3, r1, r3
|
|
800618e: b29b uxth r3, r3
|
|
8006190: 68f9 ldr r1, [r7, #12]
|
|
8006192: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8006196: 4313 orrs r3, r2
|
|
8006198: 61cb str r3, [r1, #28]
|
|
|
|
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
|
|
800619a: 68bb ldr r3, [r7, #8]
|
|
800619c: 015a lsls r2, r3, #5
|
|
800619e: 68fb ldr r3, [r7, #12]
|
|
80061a0: 4413 add r3, r2
|
|
80061a2: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80061a6: 681b ldr r3, [r3, #0]
|
|
80061a8: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80061ac: 2b00 cmp r3, #0
|
|
80061ae: d155 bne.n 800625c <USB_ActivateEndpoint+0x100>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
80061b0: 68bb ldr r3, [r7, #8]
|
|
80061b2: 015a lsls r2, r3, #5
|
|
80061b4: 68fb ldr r3, [r7, #12]
|
|
80061b6: 4413 add r3, r2
|
|
80061b8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80061bc: 681a ldr r2, [r3, #0]
|
|
80061be: 683b ldr r3, [r7, #0]
|
|
80061c0: 689b ldr r3, [r3, #8]
|
|
80061c2: f3c3 010a ubfx r1, r3, #0, #11
|
|
((uint32_t)ep->type << 18) | (epnum << 22) |
|
|
80061c6: 683b ldr r3, [r7, #0]
|
|
80061c8: 791b ldrb r3, [r3, #4]
|
|
80061ca: 049b lsls r3, r3, #18
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
80061cc: 4319 orrs r1, r3
|
|
((uint32_t)ep->type << 18) | (epnum << 22) |
|
|
80061ce: 68bb ldr r3, [r7, #8]
|
|
80061d0: 059b lsls r3, r3, #22
|
|
80061d2: 430b orrs r3, r1
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
80061d4: 4313 orrs r3, r2
|
|
80061d6: 68ba ldr r2, [r7, #8]
|
|
80061d8: 0151 lsls r1, r2, #5
|
|
80061da: 68fa ldr r2, [r7, #12]
|
|
80061dc: 440a add r2, r1
|
|
80061de: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80061e2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80061e6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80061ea: 6013 str r3, [r2, #0]
|
|
80061ec: e036 b.n 800625c <USB_ActivateEndpoint+0x100>
|
|
USB_OTG_DIEPCTL_USBAEP;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
|
|
80061ee: 68fb ldr r3, [r7, #12]
|
|
80061f0: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80061f4: 69da ldr r2, [r3, #28]
|
|
80061f6: 683b ldr r3, [r7, #0]
|
|
80061f8: 781b ldrb r3, [r3, #0]
|
|
80061fa: f003 030f and.w r3, r3, #15
|
|
80061fe: 2101 movs r1, #1
|
|
8006200: fa01 f303 lsl.w r3, r1, r3
|
|
8006204: 041b lsls r3, r3, #16
|
|
8006206: 68f9 ldr r1, [r7, #12]
|
|
8006208: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
800620c: 4313 orrs r3, r2
|
|
800620e: 61cb str r3, [r1, #28]
|
|
|
|
if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
|
|
8006210: 68bb ldr r3, [r7, #8]
|
|
8006212: 015a lsls r2, r3, #5
|
|
8006214: 68fb ldr r3, [r7, #12]
|
|
8006216: 4413 add r3, r2
|
|
8006218: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800621c: 681b ldr r3, [r3, #0]
|
|
800621e: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8006222: 2b00 cmp r3, #0
|
|
8006224: d11a bne.n 800625c <USB_ActivateEndpoint+0x100>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
|
|
8006226: 68bb ldr r3, [r7, #8]
|
|
8006228: 015a lsls r2, r3, #5
|
|
800622a: 68fb ldr r3, [r7, #12]
|
|
800622c: 4413 add r3, r2
|
|
800622e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006232: 681a ldr r2, [r3, #0]
|
|
8006234: 683b ldr r3, [r7, #0]
|
|
8006236: 689b ldr r3, [r3, #8]
|
|
8006238: f3c3 010a ubfx r1, r3, #0, #11
|
|
((uint32_t)ep->type << 18) |
|
|
800623c: 683b ldr r3, [r7, #0]
|
|
800623e: 791b ldrb r3, [r3, #4]
|
|
8006240: 049b lsls r3, r3, #18
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
|
|
8006242: 430b orrs r3, r1
|
|
8006244: 4313 orrs r3, r2
|
|
8006246: 68ba ldr r2, [r7, #8]
|
|
8006248: 0151 lsls r1, r2, #5
|
|
800624a: 68fa ldr r2, [r7, #12]
|
|
800624c: 440a add r2, r1
|
|
800624e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006252: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006256: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800625a: 6013 str r3, [r2, #0]
|
|
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DOEPCTL_USBAEP;
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800625c: 2300 movs r3, #0
|
|
}
|
|
800625e: 4618 mov r0, r3
|
|
8006260: 3714 adds r7, #20
|
|
8006262: 46bd mov sp, r7
|
|
8006264: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006268: 4770 bx lr
|
|
...
|
|
|
|
0800626c <USB_DeactivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
800626c: b480 push {r7}
|
|
800626e: b085 sub sp, #20
|
|
8006270: af00 add r7, sp, #0
|
|
8006272: 6078 str r0, [r7, #4]
|
|
8006274: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006276: 687b ldr r3, [r7, #4]
|
|
8006278: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
800627a: 683b ldr r3, [r7, #0]
|
|
800627c: 781b ldrb r3, [r3, #0]
|
|
800627e: 60bb str r3, [r7, #8]
|
|
|
|
/* Read DEPCTLn register */
|
|
if (ep->is_in == 1U)
|
|
8006280: 683b ldr r3, [r7, #0]
|
|
8006282: 785b ldrb r3, [r3, #1]
|
|
8006284: 2b01 cmp r3, #1
|
|
8006286: d161 bne.n 800634c <USB_DeactivateEndpoint+0xe0>
|
|
{
|
|
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
8006288: 68bb ldr r3, [r7, #8]
|
|
800628a: 015a lsls r2, r3, #5
|
|
800628c: 68fb ldr r3, [r7, #12]
|
|
800628e: 4413 add r3, r2
|
|
8006290: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006294: 681b ldr r3, [r3, #0]
|
|
8006296: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
800629a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800629e: d11f bne.n 80062e0 <USB_DeactivateEndpoint+0x74>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
|
|
80062a0: 68bb ldr r3, [r7, #8]
|
|
80062a2: 015a lsls r2, r3, #5
|
|
80062a4: 68fb ldr r3, [r7, #12]
|
|
80062a6: 4413 add r3, r2
|
|
80062a8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80062ac: 681b ldr r3, [r3, #0]
|
|
80062ae: 68ba ldr r2, [r7, #8]
|
|
80062b0: 0151 lsls r1, r2, #5
|
|
80062b2: 68fa ldr r2, [r7, #12]
|
|
80062b4: 440a add r2, r1
|
|
80062b6: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80062ba: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
80062be: 6013 str r3, [r2, #0]
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
|
|
80062c0: 68bb ldr r3, [r7, #8]
|
|
80062c2: 015a lsls r2, r3, #5
|
|
80062c4: 68fb ldr r3, [r7, #12]
|
|
80062c6: 4413 add r3, r2
|
|
80062c8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80062cc: 681b ldr r3, [r3, #0]
|
|
80062ce: 68ba ldr r2, [r7, #8]
|
|
80062d0: 0151 lsls r1, r2, #5
|
|
80062d2: 68fa ldr r2, [r7, #12]
|
|
80062d4: 440a add r2, r1
|
|
80062d6: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80062da: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80062de: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
|
|
80062e0: 68fb ldr r3, [r7, #12]
|
|
80062e2: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80062e6: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
80062e8: 683b ldr r3, [r7, #0]
|
|
80062ea: 781b ldrb r3, [r3, #0]
|
|
80062ec: f003 030f and.w r3, r3, #15
|
|
80062f0: 2101 movs r1, #1
|
|
80062f2: fa01 f303 lsl.w r3, r1, r3
|
|
80062f6: b29b uxth r3, r3
|
|
80062f8: 43db mvns r3, r3
|
|
80062fa: 68f9 ldr r1, [r7, #12]
|
|
80062fc: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8006300: 4013 ands r3, r2
|
|
8006302: 63cb str r3, [r1, #60] @ 0x3c
|
|
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
|
|
8006304: 68fb ldr r3, [r7, #12]
|
|
8006306: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800630a: 69da ldr r2, [r3, #28]
|
|
800630c: 683b ldr r3, [r7, #0]
|
|
800630e: 781b ldrb r3, [r3, #0]
|
|
8006310: f003 030f and.w r3, r3, #15
|
|
8006314: 2101 movs r1, #1
|
|
8006316: fa01 f303 lsl.w r3, r1, r3
|
|
800631a: b29b uxth r3, r3
|
|
800631c: 43db mvns r3, r3
|
|
800631e: 68f9 ldr r1, [r7, #12]
|
|
8006320: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8006324: 4013 ands r3, r2
|
|
8006326: 61cb str r3, [r1, #28]
|
|
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
|
|
8006328: 68bb ldr r3, [r7, #8]
|
|
800632a: 015a lsls r2, r3, #5
|
|
800632c: 68fb ldr r3, [r7, #12]
|
|
800632e: 4413 add r3, r2
|
|
8006330: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006334: 681a ldr r2, [r3, #0]
|
|
8006336: 68bb ldr r3, [r7, #8]
|
|
8006338: 0159 lsls r1, r3, #5
|
|
800633a: 68fb ldr r3, [r7, #12]
|
|
800633c: 440b add r3, r1
|
|
800633e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006342: 4619 mov r1, r3
|
|
8006344: 4b35 ldr r3, [pc, #212] @ (800641c <USB_DeactivateEndpoint+0x1b0>)
|
|
8006346: 4013 ands r3, r2
|
|
8006348: 600b str r3, [r1, #0]
|
|
800634a: e060 b.n 800640e <USB_DeactivateEndpoint+0x1a2>
|
|
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DIEPCTL_EPTYP);
|
|
}
|
|
else
|
|
{
|
|
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
800634c: 68bb ldr r3, [r7, #8]
|
|
800634e: 015a lsls r2, r3, #5
|
|
8006350: 68fb ldr r3, [r7, #12]
|
|
8006352: 4413 add r3, r2
|
|
8006354: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006358: 681b ldr r3, [r3, #0]
|
|
800635a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
800635e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8006362: d11f bne.n 80063a4 <USB_DeactivateEndpoint+0x138>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
|
8006364: 68bb ldr r3, [r7, #8]
|
|
8006366: 015a lsls r2, r3, #5
|
|
8006368: 68fb ldr r3, [r7, #12]
|
|
800636a: 4413 add r3, r2
|
|
800636c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006370: 681b ldr r3, [r3, #0]
|
|
8006372: 68ba ldr r2, [r7, #8]
|
|
8006374: 0151 lsls r1, r2, #5
|
|
8006376: 68fa ldr r2, [r7, #12]
|
|
8006378: 440a add r2, r1
|
|
800637a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800637e: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8006382: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
|
|
8006384: 68bb ldr r3, [r7, #8]
|
|
8006386: 015a lsls r2, r3, #5
|
|
8006388: 68fb ldr r3, [r7, #12]
|
|
800638a: 4413 add r3, r2
|
|
800638c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006390: 681b ldr r3, [r3, #0]
|
|
8006392: 68ba ldr r2, [r7, #8]
|
|
8006394: 0151 lsls r1, r2, #5
|
|
8006396: 68fa ldr r2, [r7, #12]
|
|
8006398: 440a add r2, r1
|
|
800639a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800639e: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80063a2: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
|
|
80063a4: 68fb ldr r3, [r7, #12]
|
|
80063a6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80063aa: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
80063ac: 683b ldr r3, [r7, #0]
|
|
80063ae: 781b ldrb r3, [r3, #0]
|
|
80063b0: f003 030f and.w r3, r3, #15
|
|
80063b4: 2101 movs r1, #1
|
|
80063b6: fa01 f303 lsl.w r3, r1, r3
|
|
80063ba: 041b lsls r3, r3, #16
|
|
80063bc: 43db mvns r3, r3
|
|
80063be: 68f9 ldr r1, [r7, #12]
|
|
80063c0: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80063c4: 4013 ands r3, r2
|
|
80063c6: 63cb str r3, [r1, #60] @ 0x3c
|
|
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
|
|
80063c8: 68fb ldr r3, [r7, #12]
|
|
80063ca: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80063ce: 69da ldr r2, [r3, #28]
|
|
80063d0: 683b ldr r3, [r7, #0]
|
|
80063d2: 781b ldrb r3, [r3, #0]
|
|
80063d4: f003 030f and.w r3, r3, #15
|
|
80063d8: 2101 movs r1, #1
|
|
80063da: fa01 f303 lsl.w r3, r1, r3
|
|
80063de: 041b lsls r3, r3, #16
|
|
80063e0: 43db mvns r3, r3
|
|
80063e2: 68f9 ldr r1, [r7, #12]
|
|
80063e4: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80063e8: 4013 ands r3, r2
|
|
80063ea: 61cb str r3, [r1, #28]
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
|
|
80063ec: 68bb ldr r3, [r7, #8]
|
|
80063ee: 015a lsls r2, r3, #5
|
|
80063f0: 68fb ldr r3, [r7, #12]
|
|
80063f2: 4413 add r3, r2
|
|
80063f4: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80063f8: 681a ldr r2, [r3, #0]
|
|
80063fa: 68bb ldr r3, [r7, #8]
|
|
80063fc: 0159 lsls r1, r3, #5
|
|
80063fe: 68fb ldr r3, [r7, #12]
|
|
8006400: 440b add r3, r1
|
|
8006402: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006406: 4619 mov r1, r3
|
|
8006408: 4b05 ldr r3, [pc, #20] @ (8006420 <USB_DeactivateEndpoint+0x1b4>)
|
|
800640a: 4013 ands r3, r2
|
|
800640c: 600b str r3, [r1, #0]
|
|
USB_OTG_DOEPCTL_MPSIZ |
|
|
USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DOEPCTL_EPTYP);
|
|
}
|
|
|
|
return HAL_OK;
|
|
800640e: 2300 movs r3, #0
|
|
}
|
|
8006410: 4618 mov r0, r3
|
|
8006412: 3714 adds r7, #20
|
|
8006414: 46bd mov sp, r7
|
|
8006416: f85d 7b04 ldr.w r7, [sp], #4
|
|
800641a: 4770 bx lr
|
|
800641c: ec337800 .word 0xec337800
|
|
8006420: eff37800 .word 0xeff37800
|
|
|
|
08006424 <USB_EPStartXfer>:
|
|
* 0 : DMA feature not used
|
|
* 1 : DMA feature used
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
|
|
{
|
|
8006424: b580 push {r7, lr}
|
|
8006426: b08a sub sp, #40 @ 0x28
|
|
8006428: af02 add r7, sp, #8
|
|
800642a: 60f8 str r0, [r7, #12]
|
|
800642c: 60b9 str r1, [r7, #8]
|
|
800642e: 4613 mov r3, r2
|
|
8006430: 71fb strb r3, [r7, #7]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006432: 68fb ldr r3, [r7, #12]
|
|
8006434: 61fb str r3, [r7, #28]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8006436: 68bb ldr r3, [r7, #8]
|
|
8006438: 781b ldrb r3, [r3, #0]
|
|
800643a: 61bb str r3, [r7, #24]
|
|
uint16_t pktcnt;
|
|
|
|
/* IN endpoint */
|
|
if (ep->is_in == 1U)
|
|
800643c: 68bb ldr r3, [r7, #8]
|
|
800643e: 785b ldrb r3, [r3, #1]
|
|
8006440: 2b01 cmp r3, #1
|
|
8006442: f040 817f bne.w 8006744 <USB_EPStartXfer+0x320>
|
|
{
|
|
/* Zero Length Packet? */
|
|
if (ep->xfer_len == 0U)
|
|
8006446: 68bb ldr r3, [r7, #8]
|
|
8006448: 691b ldr r3, [r3, #16]
|
|
800644a: 2b00 cmp r3, #0
|
|
800644c: d132 bne.n 80064b4 <USB_EPStartXfer+0x90>
|
|
{
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
|
800644e: 69bb ldr r3, [r7, #24]
|
|
8006450: 015a lsls r2, r3, #5
|
|
8006452: 69fb ldr r3, [r7, #28]
|
|
8006454: 4413 add r3, r2
|
|
8006456: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800645a: 691b ldr r3, [r3, #16]
|
|
800645c: 69ba ldr r2, [r7, #24]
|
|
800645e: 0151 lsls r1, r2, #5
|
|
8006460: 69fa ldr r2, [r7, #28]
|
|
8006462: 440a add r2, r1
|
|
8006464: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006468: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
800646c: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
8006470: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
|
|
8006472: 69bb ldr r3, [r7, #24]
|
|
8006474: 015a lsls r2, r3, #5
|
|
8006476: 69fb ldr r3, [r7, #28]
|
|
8006478: 4413 add r3, r2
|
|
800647a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800647e: 691b ldr r3, [r3, #16]
|
|
8006480: 69ba ldr r2, [r7, #24]
|
|
8006482: 0151 lsls r1, r2, #5
|
|
8006484: 69fa ldr r2, [r7, #28]
|
|
8006486: 440a add r2, r1
|
|
8006488: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800648c: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8006490: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
|
8006492: 69bb ldr r3, [r7, #24]
|
|
8006494: 015a lsls r2, r3, #5
|
|
8006496: 69fb ldr r3, [r7, #28]
|
|
8006498: 4413 add r3, r2
|
|
800649a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800649e: 691b ldr r3, [r3, #16]
|
|
80064a0: 69ba ldr r2, [r7, #24]
|
|
80064a2: 0151 lsls r1, r2, #5
|
|
80064a4: 69fa ldr r2, [r7, #28]
|
|
80064a6: 440a add r2, r1
|
|
80064a8: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80064ac: 0cdb lsrs r3, r3, #19
|
|
80064ae: 04db lsls r3, r3, #19
|
|
80064b0: 6113 str r3, [r2, #16]
|
|
80064b2: e097 b.n 80065e4 <USB_EPStartXfer+0x1c0>
|
|
/* Program the transfer size and packet count
|
|
* as follows: xfersize = N * maxpacket +
|
|
* short_packet pktcnt = N + (short_packet
|
|
* exist ? 1 : 0)
|
|
*/
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
|
80064b4: 69bb ldr r3, [r7, #24]
|
|
80064b6: 015a lsls r2, r3, #5
|
|
80064b8: 69fb ldr r3, [r7, #28]
|
|
80064ba: 4413 add r3, r2
|
|
80064bc: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80064c0: 691b ldr r3, [r3, #16]
|
|
80064c2: 69ba ldr r2, [r7, #24]
|
|
80064c4: 0151 lsls r1, r2, #5
|
|
80064c6: 69fa ldr r2, [r7, #28]
|
|
80064c8: 440a add r2, r1
|
|
80064ca: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80064ce: 0cdb lsrs r3, r3, #19
|
|
80064d0: 04db lsls r3, r3, #19
|
|
80064d2: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
|
80064d4: 69bb ldr r3, [r7, #24]
|
|
80064d6: 015a lsls r2, r3, #5
|
|
80064d8: 69fb ldr r3, [r7, #28]
|
|
80064da: 4413 add r3, r2
|
|
80064dc: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80064e0: 691b ldr r3, [r3, #16]
|
|
80064e2: 69ba ldr r2, [r7, #24]
|
|
80064e4: 0151 lsls r1, r2, #5
|
|
80064e6: 69fa ldr r2, [r7, #28]
|
|
80064e8: 440a add r2, r1
|
|
80064ea: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80064ee: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
80064f2: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
80064f6: 6113 str r3, [r2, #16]
|
|
|
|
if (epnum == 0U)
|
|
80064f8: 69bb ldr r3, [r7, #24]
|
|
80064fa: 2b00 cmp r3, #0
|
|
80064fc: d11a bne.n 8006534 <USB_EPStartXfer+0x110>
|
|
{
|
|
if (ep->xfer_len > ep->maxpacket)
|
|
80064fe: 68bb ldr r3, [r7, #8]
|
|
8006500: 691a ldr r2, [r3, #16]
|
|
8006502: 68bb ldr r3, [r7, #8]
|
|
8006504: 689b ldr r3, [r3, #8]
|
|
8006506: 429a cmp r2, r3
|
|
8006508: d903 bls.n 8006512 <USB_EPStartXfer+0xee>
|
|
{
|
|
ep->xfer_len = ep->maxpacket;
|
|
800650a: 68bb ldr r3, [r7, #8]
|
|
800650c: 689a ldr r2, [r3, #8]
|
|
800650e: 68bb ldr r3, [r7, #8]
|
|
8006510: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
|
|
8006512: 69bb ldr r3, [r7, #24]
|
|
8006514: 015a lsls r2, r3, #5
|
|
8006516: 69fb ldr r3, [r7, #28]
|
|
8006518: 4413 add r3, r2
|
|
800651a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800651e: 691b ldr r3, [r3, #16]
|
|
8006520: 69ba ldr r2, [r7, #24]
|
|
8006522: 0151 lsls r1, r2, #5
|
|
8006524: 69fa ldr r2, [r7, #28]
|
|
8006526: 440a add r2, r1
|
|
8006528: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800652c: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8006530: 6113 str r3, [r2, #16]
|
|
8006532: e044 b.n 80065be <USB_EPStartXfer+0x19a>
|
|
}
|
|
else
|
|
{
|
|
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
|
|
8006534: 68bb ldr r3, [r7, #8]
|
|
8006536: 691a ldr r2, [r3, #16]
|
|
8006538: 68bb ldr r3, [r7, #8]
|
|
800653a: 689b ldr r3, [r3, #8]
|
|
800653c: 4413 add r3, r2
|
|
800653e: 1e5a subs r2, r3, #1
|
|
8006540: 68bb ldr r3, [r7, #8]
|
|
8006542: 689b ldr r3, [r3, #8]
|
|
8006544: fbb2 f3f3 udiv r3, r2, r3
|
|
8006548: 82fb strh r3, [r7, #22]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19));
|
|
800654a: 69bb ldr r3, [r7, #24]
|
|
800654c: 015a lsls r2, r3, #5
|
|
800654e: 69fb ldr r3, [r7, #28]
|
|
8006550: 4413 add r3, r2
|
|
8006552: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006556: 691a ldr r2, [r3, #16]
|
|
8006558: 8afb ldrh r3, [r7, #22]
|
|
800655a: 04d9 lsls r1, r3, #19
|
|
800655c: 4ba4 ldr r3, [pc, #656] @ (80067f0 <USB_EPStartXfer+0x3cc>)
|
|
800655e: 400b ands r3, r1
|
|
8006560: 69b9 ldr r1, [r7, #24]
|
|
8006562: 0148 lsls r0, r1, #5
|
|
8006564: 69f9 ldr r1, [r7, #28]
|
|
8006566: 4401 add r1, r0
|
|
8006568: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
800656c: 4313 orrs r3, r2
|
|
800656e: 610b str r3, [r1, #16]
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
8006570: 68bb ldr r3, [r7, #8]
|
|
8006572: 791b ldrb r3, [r3, #4]
|
|
8006574: 2b01 cmp r3, #1
|
|
8006576: d122 bne.n 80065be <USB_EPStartXfer+0x19a>
|
|
{
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
|
|
8006578: 69bb ldr r3, [r7, #24]
|
|
800657a: 015a lsls r2, r3, #5
|
|
800657c: 69fb ldr r3, [r7, #28]
|
|
800657e: 4413 add r3, r2
|
|
8006580: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006584: 691b ldr r3, [r3, #16]
|
|
8006586: 69ba ldr r2, [r7, #24]
|
|
8006588: 0151 lsls r1, r2, #5
|
|
800658a: 69fa ldr r2, [r7, #28]
|
|
800658c: 440a add r2, r1
|
|
800658e: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006592: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000
|
|
8006596: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29));
|
|
8006598: 69bb ldr r3, [r7, #24]
|
|
800659a: 015a lsls r2, r3, #5
|
|
800659c: 69fb ldr r3, [r7, #28]
|
|
800659e: 4413 add r3, r2
|
|
80065a0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80065a4: 691a ldr r2, [r3, #16]
|
|
80065a6: 8afb ldrh r3, [r7, #22]
|
|
80065a8: 075b lsls r3, r3, #29
|
|
80065aa: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000
|
|
80065ae: 69b9 ldr r1, [r7, #24]
|
|
80065b0: 0148 lsls r0, r1, #5
|
|
80065b2: 69f9 ldr r1, [r7, #28]
|
|
80065b4: 4401 add r1, r0
|
|
80065b6: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
80065ba: 4313 orrs r3, r2
|
|
80065bc: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
|
|
80065be: 69bb ldr r3, [r7, #24]
|
|
80065c0: 015a lsls r2, r3, #5
|
|
80065c2: 69fb ldr r3, [r7, #28]
|
|
80065c4: 4413 add r3, r2
|
|
80065c6: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80065ca: 691a ldr r2, [r3, #16]
|
|
80065cc: 68bb ldr r3, [r7, #8]
|
|
80065ce: 691b ldr r3, [r3, #16]
|
|
80065d0: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80065d4: 69b9 ldr r1, [r7, #24]
|
|
80065d6: 0148 lsls r0, r1, #5
|
|
80065d8: 69f9 ldr r1, [r7, #28]
|
|
80065da: 4401 add r1, r0
|
|
80065dc: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
80065e0: 4313 orrs r3, r2
|
|
80065e2: 610b str r3, [r1, #16]
|
|
}
|
|
|
|
if (dma == 1U)
|
|
80065e4: 79fb ldrb r3, [r7, #7]
|
|
80065e6: 2b01 cmp r3, #1
|
|
80065e8: d14b bne.n 8006682 <USB_EPStartXfer+0x25e>
|
|
{
|
|
if ((uint32_t)ep->dma_addr != 0U)
|
|
80065ea: 68bb ldr r3, [r7, #8]
|
|
80065ec: 69db ldr r3, [r3, #28]
|
|
80065ee: 2b00 cmp r3, #0
|
|
80065f0: d009 beq.n 8006606 <USB_EPStartXfer+0x1e2>
|
|
{
|
|
USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
|
|
80065f2: 69bb ldr r3, [r7, #24]
|
|
80065f4: 015a lsls r2, r3, #5
|
|
80065f6: 69fb ldr r3, [r7, #28]
|
|
80065f8: 4413 add r3, r2
|
|
80065fa: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80065fe: 461a mov r2, r3
|
|
8006600: 68bb ldr r3, [r7, #8]
|
|
8006602: 69db ldr r3, [r3, #28]
|
|
8006604: 6153 str r3, [r2, #20]
|
|
}
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
8006606: 68bb ldr r3, [r7, #8]
|
|
8006608: 791b ldrb r3, [r3, #4]
|
|
800660a: 2b01 cmp r3, #1
|
|
800660c: d128 bne.n 8006660 <USB_EPStartXfer+0x23c>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
800660e: 69fb ldr r3, [r7, #28]
|
|
8006610: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006614: 689b ldr r3, [r3, #8]
|
|
8006616: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800661a: 2b00 cmp r3, #0
|
|
800661c: d110 bne.n 8006640 <USB_EPStartXfer+0x21c>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
|
|
800661e: 69bb ldr r3, [r7, #24]
|
|
8006620: 015a lsls r2, r3, #5
|
|
8006622: 69fb ldr r3, [r7, #28]
|
|
8006624: 4413 add r3, r2
|
|
8006626: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800662a: 681b ldr r3, [r3, #0]
|
|
800662c: 69ba ldr r2, [r7, #24]
|
|
800662e: 0151 lsls r1, r2, #5
|
|
8006630: 69fa ldr r2, [r7, #28]
|
|
8006632: 440a add r2, r1
|
|
8006634: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006638: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
800663c: 6013 str r3, [r2, #0]
|
|
800663e: e00f b.n 8006660 <USB_EPStartXfer+0x23c>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
|
8006640: 69bb ldr r3, [r7, #24]
|
|
8006642: 015a lsls r2, r3, #5
|
|
8006644: 69fb ldr r3, [r7, #28]
|
|
8006646: 4413 add r3, r2
|
|
8006648: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800664c: 681b ldr r3, [r3, #0]
|
|
800664e: 69ba ldr r2, [r7, #24]
|
|
8006650: 0151 lsls r1, r2, #5
|
|
8006652: 69fa ldr r2, [r7, #28]
|
|
8006654: 440a add r2, r1
|
|
8006656: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800665a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800665e: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
/* EP enable, IN data in FIFO */
|
|
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
|
8006660: 69bb ldr r3, [r7, #24]
|
|
8006662: 015a lsls r2, r3, #5
|
|
8006664: 69fb ldr r3, [r7, #28]
|
|
8006666: 4413 add r3, r2
|
|
8006668: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800666c: 681b ldr r3, [r3, #0]
|
|
800666e: 69ba ldr r2, [r7, #24]
|
|
8006670: 0151 lsls r1, r2, #5
|
|
8006672: 69fa ldr r2, [r7, #28]
|
|
8006674: 440a add r2, r1
|
|
8006676: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800667a: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
800667e: 6013 str r3, [r2, #0]
|
|
8006680: e166 b.n 8006950 <USB_EPStartXfer+0x52c>
|
|
}
|
|
else
|
|
{
|
|
/* EP enable, IN data in FIFO */
|
|
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
|
8006682: 69bb ldr r3, [r7, #24]
|
|
8006684: 015a lsls r2, r3, #5
|
|
8006686: 69fb ldr r3, [r7, #28]
|
|
8006688: 4413 add r3, r2
|
|
800668a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800668e: 681b ldr r3, [r3, #0]
|
|
8006690: 69ba ldr r2, [r7, #24]
|
|
8006692: 0151 lsls r1, r2, #5
|
|
8006694: 69fa ldr r2, [r7, #28]
|
|
8006696: 440a add r2, r1
|
|
8006698: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800669c: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
80066a0: 6013 str r3, [r2, #0]
|
|
|
|
if (ep->type != EP_TYPE_ISOC)
|
|
80066a2: 68bb ldr r3, [r7, #8]
|
|
80066a4: 791b ldrb r3, [r3, #4]
|
|
80066a6: 2b01 cmp r3, #1
|
|
80066a8: d015 beq.n 80066d6 <USB_EPStartXfer+0x2b2>
|
|
{
|
|
/* Enable the Tx FIFO Empty Interrupt for this EP */
|
|
if (ep->xfer_len > 0U)
|
|
80066aa: 68bb ldr r3, [r7, #8]
|
|
80066ac: 691b ldr r3, [r3, #16]
|
|
80066ae: 2b00 cmp r3, #0
|
|
80066b0: f000 814e beq.w 8006950 <USB_EPStartXfer+0x52c>
|
|
{
|
|
USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
|
|
80066b4: 69fb ldr r3, [r7, #28]
|
|
80066b6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80066ba: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80066bc: 68bb ldr r3, [r7, #8]
|
|
80066be: 781b ldrb r3, [r3, #0]
|
|
80066c0: f003 030f and.w r3, r3, #15
|
|
80066c4: 2101 movs r1, #1
|
|
80066c6: fa01 f303 lsl.w r3, r1, r3
|
|
80066ca: 69f9 ldr r1, [r7, #28]
|
|
80066cc: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80066d0: 4313 orrs r3, r2
|
|
80066d2: 634b str r3, [r1, #52] @ 0x34
|
|
80066d4: e13c b.n 8006950 <USB_EPStartXfer+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
80066d6: 69fb ldr r3, [r7, #28]
|
|
80066d8: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80066dc: 689b ldr r3, [r3, #8]
|
|
80066de: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80066e2: 2b00 cmp r3, #0
|
|
80066e4: d110 bne.n 8006708 <USB_EPStartXfer+0x2e4>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
|
|
80066e6: 69bb ldr r3, [r7, #24]
|
|
80066e8: 015a lsls r2, r3, #5
|
|
80066ea: 69fb ldr r3, [r7, #28]
|
|
80066ec: 4413 add r3, r2
|
|
80066ee: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80066f2: 681b ldr r3, [r3, #0]
|
|
80066f4: 69ba ldr r2, [r7, #24]
|
|
80066f6: 0151 lsls r1, r2, #5
|
|
80066f8: 69fa ldr r2, [r7, #28]
|
|
80066fa: 440a add r2, r1
|
|
80066fc: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006700: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8006704: 6013 str r3, [r2, #0]
|
|
8006706: e00f b.n 8006728 <USB_EPStartXfer+0x304>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
|
8006708: 69bb ldr r3, [r7, #24]
|
|
800670a: 015a lsls r2, r3, #5
|
|
800670c: 69fb ldr r3, [r7, #28]
|
|
800670e: 4413 add r3, r2
|
|
8006710: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006714: 681b ldr r3, [r3, #0]
|
|
8006716: 69ba ldr r2, [r7, #24]
|
|
8006718: 0151 lsls r1, r2, #5
|
|
800671a: 69fa ldr r2, [r7, #28]
|
|
800671c: 440a add r2, r1
|
|
800671e: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006722: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006726: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
|
|
8006728: 68bb ldr r3, [r7, #8]
|
|
800672a: 68d9 ldr r1, [r3, #12]
|
|
800672c: 68bb ldr r3, [r7, #8]
|
|
800672e: 781a ldrb r2, [r3, #0]
|
|
8006730: 68bb ldr r3, [r7, #8]
|
|
8006732: 691b ldr r3, [r3, #16]
|
|
8006734: b298 uxth r0, r3
|
|
8006736: 79fb ldrb r3, [r7, #7]
|
|
8006738: 9300 str r3, [sp, #0]
|
|
800673a: 4603 mov r3, r0
|
|
800673c: 68f8 ldr r0, [r7, #12]
|
|
800673e: f000 f9b9 bl 8006ab4 <USB_WritePacket>
|
|
8006742: e105 b.n 8006950 <USB_EPStartXfer+0x52c>
|
|
{
|
|
/* Program the transfer size and packet count as follows:
|
|
* pktcnt = N
|
|
* xfersize = N * maxpacket
|
|
*/
|
|
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
|
|
8006744: 69bb ldr r3, [r7, #24]
|
|
8006746: 015a lsls r2, r3, #5
|
|
8006748: 69fb ldr r3, [r7, #28]
|
|
800674a: 4413 add r3, r2
|
|
800674c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006750: 691b ldr r3, [r3, #16]
|
|
8006752: 69ba ldr r2, [r7, #24]
|
|
8006754: 0151 lsls r1, r2, #5
|
|
8006756: 69fa ldr r2, [r7, #28]
|
|
8006758: 440a add r2, r1
|
|
800675a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800675e: 0cdb lsrs r3, r3, #19
|
|
8006760: 04db lsls r3, r3, #19
|
|
8006762: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
|
|
8006764: 69bb ldr r3, [r7, #24]
|
|
8006766: 015a lsls r2, r3, #5
|
|
8006768: 69fb ldr r3, [r7, #28]
|
|
800676a: 4413 add r3, r2
|
|
800676c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006770: 691b ldr r3, [r3, #16]
|
|
8006772: 69ba ldr r2, [r7, #24]
|
|
8006774: 0151 lsls r1, r2, #5
|
|
8006776: 69fa ldr r2, [r7, #28]
|
|
8006778: 440a add r2, r1
|
|
800677a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800677e: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
8006782: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
8006786: 6113 str r3, [r2, #16]
|
|
|
|
if (epnum == 0U)
|
|
8006788: 69bb ldr r3, [r7, #24]
|
|
800678a: 2b00 cmp r3, #0
|
|
800678c: d132 bne.n 80067f4 <USB_EPStartXfer+0x3d0>
|
|
{
|
|
if (ep->xfer_len > 0U)
|
|
800678e: 68bb ldr r3, [r7, #8]
|
|
8006790: 691b ldr r3, [r3, #16]
|
|
8006792: 2b00 cmp r3, #0
|
|
8006794: d003 beq.n 800679e <USB_EPStartXfer+0x37a>
|
|
{
|
|
ep->xfer_len = ep->maxpacket;
|
|
8006796: 68bb ldr r3, [r7, #8]
|
|
8006798: 689a ldr r2, [r3, #8]
|
|
800679a: 68bb ldr r3, [r7, #8]
|
|
800679c: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
/* Store transfer size, for EP0 this is equal to endpoint max packet size */
|
|
ep->xfer_size = ep->maxpacket;
|
|
800679e: 68bb ldr r3, [r7, #8]
|
|
80067a0: 689a ldr r2, [r3, #8]
|
|
80067a2: 68bb ldr r3, [r7, #8]
|
|
80067a4: 621a str r2, [r3, #32]
|
|
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
|
|
80067a6: 69bb ldr r3, [r7, #24]
|
|
80067a8: 015a lsls r2, r3, #5
|
|
80067aa: 69fb ldr r3, [r7, #28]
|
|
80067ac: 4413 add r3, r2
|
|
80067ae: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80067b2: 691a ldr r2, [r3, #16]
|
|
80067b4: 68bb ldr r3, [r7, #8]
|
|
80067b6: 6a1b ldr r3, [r3, #32]
|
|
80067b8: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80067bc: 69b9 ldr r1, [r7, #24]
|
|
80067be: 0148 lsls r0, r1, #5
|
|
80067c0: 69f9 ldr r1, [r7, #28]
|
|
80067c2: 4401 add r1, r0
|
|
80067c4: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
80067c8: 4313 orrs r3, r2
|
|
80067ca: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
80067cc: 69bb ldr r3, [r7, #24]
|
|
80067ce: 015a lsls r2, r3, #5
|
|
80067d0: 69fb ldr r3, [r7, #28]
|
|
80067d2: 4413 add r3, r2
|
|
80067d4: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80067d8: 691b ldr r3, [r3, #16]
|
|
80067da: 69ba ldr r2, [r7, #24]
|
|
80067dc: 0151 lsls r1, r2, #5
|
|
80067de: 69fa ldr r2, [r7, #28]
|
|
80067e0: 440a add r2, r1
|
|
80067e2: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
80067e6: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
80067ea: 6113 str r3, [r2, #16]
|
|
80067ec: e062 b.n 80068b4 <USB_EPStartXfer+0x490>
|
|
80067ee: bf00 nop
|
|
80067f0: 1ff80000 .word 0x1ff80000
|
|
}
|
|
else
|
|
{
|
|
if (ep->xfer_len == 0U)
|
|
80067f4: 68bb ldr r3, [r7, #8]
|
|
80067f6: 691b ldr r3, [r3, #16]
|
|
80067f8: 2b00 cmp r3, #0
|
|
80067fa: d123 bne.n 8006844 <USB_EPStartXfer+0x420>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
|
|
80067fc: 69bb ldr r3, [r7, #24]
|
|
80067fe: 015a lsls r2, r3, #5
|
|
8006800: 69fb ldr r3, [r7, #28]
|
|
8006802: 4413 add r3, r2
|
|
8006804: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006808: 691a ldr r2, [r3, #16]
|
|
800680a: 68bb ldr r3, [r7, #8]
|
|
800680c: 689b ldr r3, [r3, #8]
|
|
800680e: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8006812: 69b9 ldr r1, [r7, #24]
|
|
8006814: 0148 lsls r0, r1, #5
|
|
8006816: 69f9 ldr r1, [r7, #28]
|
|
8006818: 4401 add r1, r0
|
|
800681a: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
800681e: 4313 orrs r3, r2
|
|
8006820: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
8006822: 69bb ldr r3, [r7, #24]
|
|
8006824: 015a lsls r2, r3, #5
|
|
8006826: 69fb ldr r3, [r7, #28]
|
|
8006828: 4413 add r3, r2
|
|
800682a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800682e: 691b ldr r3, [r3, #16]
|
|
8006830: 69ba ldr r2, [r7, #24]
|
|
8006832: 0151 lsls r1, r2, #5
|
|
8006834: 69fa ldr r2, [r7, #28]
|
|
8006836: 440a add r2, r1
|
|
8006838: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800683c: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8006840: 6113 str r3, [r2, #16]
|
|
8006842: e037 b.n 80068b4 <USB_EPStartXfer+0x490>
|
|
}
|
|
else
|
|
{
|
|
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
|
|
8006844: 68bb ldr r3, [r7, #8]
|
|
8006846: 691a ldr r2, [r3, #16]
|
|
8006848: 68bb ldr r3, [r7, #8]
|
|
800684a: 689b ldr r3, [r3, #8]
|
|
800684c: 4413 add r3, r2
|
|
800684e: 1e5a subs r2, r3, #1
|
|
8006850: 68bb ldr r3, [r7, #8]
|
|
8006852: 689b ldr r3, [r3, #8]
|
|
8006854: fbb2 f3f3 udiv r3, r2, r3
|
|
8006858: 82fb strh r3, [r7, #22]
|
|
ep->xfer_size = ep->maxpacket * pktcnt;
|
|
800685a: 68bb ldr r3, [r7, #8]
|
|
800685c: 689b ldr r3, [r3, #8]
|
|
800685e: 8afa ldrh r2, [r7, #22]
|
|
8006860: fb03 f202 mul.w r2, r3, r2
|
|
8006864: 68bb ldr r3, [r7, #8]
|
|
8006866: 621a str r2, [r3, #32]
|
|
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
|
|
8006868: 69bb ldr r3, [r7, #24]
|
|
800686a: 015a lsls r2, r3, #5
|
|
800686c: 69fb ldr r3, [r7, #28]
|
|
800686e: 4413 add r3, r2
|
|
8006870: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006874: 691a ldr r2, [r3, #16]
|
|
8006876: 8afb ldrh r3, [r7, #22]
|
|
8006878: 04d9 lsls r1, r3, #19
|
|
800687a: 4b38 ldr r3, [pc, #224] @ (800695c <USB_EPStartXfer+0x538>)
|
|
800687c: 400b ands r3, r1
|
|
800687e: 69b9 ldr r1, [r7, #24]
|
|
8006880: 0148 lsls r0, r1, #5
|
|
8006882: 69f9 ldr r1, [r7, #28]
|
|
8006884: 4401 add r1, r0
|
|
8006886: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
800688a: 4313 orrs r3, r2
|
|
800688c: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size;
|
|
800688e: 69bb ldr r3, [r7, #24]
|
|
8006890: 015a lsls r2, r3, #5
|
|
8006892: 69fb ldr r3, [r7, #28]
|
|
8006894: 4413 add r3, r2
|
|
8006896: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800689a: 691a ldr r2, [r3, #16]
|
|
800689c: 68bb ldr r3, [r7, #8]
|
|
800689e: 6a1b ldr r3, [r3, #32]
|
|
80068a0: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80068a4: 69b9 ldr r1, [r7, #24]
|
|
80068a6: 0148 lsls r0, r1, #5
|
|
80068a8: 69f9 ldr r1, [r7, #28]
|
|
80068aa: 4401 add r1, r0
|
|
80068ac: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
80068b0: 4313 orrs r3, r2
|
|
80068b2: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
if (dma == 1U)
|
|
80068b4: 79fb ldrb r3, [r7, #7]
|
|
80068b6: 2b01 cmp r3, #1
|
|
80068b8: d10d bne.n 80068d6 <USB_EPStartXfer+0x4b2>
|
|
{
|
|
if ((uint32_t)ep->xfer_buff != 0U)
|
|
80068ba: 68bb ldr r3, [r7, #8]
|
|
80068bc: 68db ldr r3, [r3, #12]
|
|
80068be: 2b00 cmp r3, #0
|
|
80068c0: d009 beq.n 80068d6 <USB_EPStartXfer+0x4b2>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
|
|
80068c2: 68bb ldr r3, [r7, #8]
|
|
80068c4: 68d9 ldr r1, [r3, #12]
|
|
80068c6: 69bb ldr r3, [r7, #24]
|
|
80068c8: 015a lsls r2, r3, #5
|
|
80068ca: 69fb ldr r3, [r7, #28]
|
|
80068cc: 4413 add r3, r2
|
|
80068ce: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80068d2: 460a mov r2, r1
|
|
80068d4: 615a str r2, [r3, #20]
|
|
}
|
|
}
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
80068d6: 68bb ldr r3, [r7, #8]
|
|
80068d8: 791b ldrb r3, [r3, #4]
|
|
80068da: 2b01 cmp r3, #1
|
|
80068dc: d128 bne.n 8006930 <USB_EPStartXfer+0x50c>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
80068de: 69fb ldr r3, [r7, #28]
|
|
80068e0: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80068e4: 689b ldr r3, [r3, #8]
|
|
80068e6: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80068ea: 2b00 cmp r3, #0
|
|
80068ec: d110 bne.n 8006910 <USB_EPStartXfer+0x4ec>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
|
|
80068ee: 69bb ldr r3, [r7, #24]
|
|
80068f0: 015a lsls r2, r3, #5
|
|
80068f2: 69fb ldr r3, [r7, #28]
|
|
80068f4: 4413 add r3, r2
|
|
80068f6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80068fa: 681b ldr r3, [r3, #0]
|
|
80068fc: 69ba ldr r2, [r7, #24]
|
|
80068fe: 0151 lsls r1, r2, #5
|
|
8006900: 69fa ldr r2, [r7, #28]
|
|
8006902: 440a add r2, r1
|
|
8006904: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006908: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
800690c: 6013 str r3, [r2, #0]
|
|
800690e: e00f b.n 8006930 <USB_EPStartXfer+0x50c>
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
|
|
8006910: 69bb ldr r3, [r7, #24]
|
|
8006912: 015a lsls r2, r3, #5
|
|
8006914: 69fb ldr r3, [r7, #28]
|
|
8006916: 4413 add r3, r2
|
|
8006918: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800691c: 681b ldr r3, [r3, #0]
|
|
800691e: 69ba ldr r2, [r7, #24]
|
|
8006920: 0151 lsls r1, r2, #5
|
|
8006922: 69fa ldr r2, [r7, #28]
|
|
8006924: 440a add r2, r1
|
|
8006926: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800692a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800692e: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
/* EP enable */
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
|
|
8006930: 69bb ldr r3, [r7, #24]
|
|
8006932: 015a lsls r2, r3, #5
|
|
8006934: 69fb ldr r3, [r7, #28]
|
|
8006936: 4413 add r3, r2
|
|
8006938: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800693c: 681b ldr r3, [r3, #0]
|
|
800693e: 69ba ldr r2, [r7, #24]
|
|
8006940: 0151 lsls r1, r2, #5
|
|
8006942: 69fa ldr r2, [r7, #28]
|
|
8006944: 440a add r2, r1
|
|
8006946: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800694a: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
800694e: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006950: 2300 movs r3, #0
|
|
}
|
|
8006952: 4618 mov r0, r3
|
|
8006954: 3720 adds r7, #32
|
|
8006956: 46bd mov sp, r7
|
|
8006958: bd80 pop {r7, pc}
|
|
800695a: bf00 nop
|
|
800695c: 1ff80000 .word 0x1ff80000
|
|
|
|
08006960 <USB_EPStopXfer>:
|
|
* @param USBx usb device instance
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8006960: b480 push {r7}
|
|
8006962: b087 sub sp, #28
|
|
8006964: af00 add r7, sp, #0
|
|
8006966: 6078 str r0, [r7, #4]
|
|
8006968: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
800696a: 2300 movs r3, #0
|
|
800696c: 60fb str r3, [r7, #12]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
800696e: 2300 movs r3, #0
|
|
8006970: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006972: 687b ldr r3, [r7, #4]
|
|
8006974: 613b str r3, [r7, #16]
|
|
|
|
/* IN endpoint */
|
|
if (ep->is_in == 1U)
|
|
8006976: 683b ldr r3, [r7, #0]
|
|
8006978: 785b ldrb r3, [r3, #1]
|
|
800697a: 2b01 cmp r3, #1
|
|
800697c: d14a bne.n 8006a14 <USB_EPStopXfer+0xb4>
|
|
{
|
|
/* EP enable, IN data in FIFO */
|
|
if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
800697e: 683b ldr r3, [r7, #0]
|
|
8006980: 781b ldrb r3, [r3, #0]
|
|
8006982: 015a lsls r2, r3, #5
|
|
8006984: 693b ldr r3, [r7, #16]
|
|
8006986: 4413 add r3, r2
|
|
8006988: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800698c: 681b ldr r3, [r3, #0]
|
|
800698e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006992: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8006996: f040 8086 bne.w 8006aa6 <USB_EPStopXfer+0x146>
|
|
{
|
|
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
|
|
800699a: 683b ldr r3, [r7, #0]
|
|
800699c: 781b ldrb r3, [r3, #0]
|
|
800699e: 015a lsls r2, r3, #5
|
|
80069a0: 693b ldr r3, [r7, #16]
|
|
80069a2: 4413 add r3, r2
|
|
80069a4: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80069a8: 681b ldr r3, [r3, #0]
|
|
80069aa: 683a ldr r2, [r7, #0]
|
|
80069ac: 7812 ldrb r2, [r2, #0]
|
|
80069ae: 0151 lsls r1, r2, #5
|
|
80069b0: 693a ldr r2, [r7, #16]
|
|
80069b2: 440a add r2, r1
|
|
80069b4: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80069b8: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
80069bc: 6013 str r3, [r2, #0]
|
|
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
|
|
80069be: 683b ldr r3, [r7, #0]
|
|
80069c0: 781b ldrb r3, [r3, #0]
|
|
80069c2: 015a lsls r2, r3, #5
|
|
80069c4: 693b ldr r3, [r7, #16]
|
|
80069c6: 4413 add r3, r2
|
|
80069c8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80069cc: 681b ldr r3, [r3, #0]
|
|
80069ce: 683a ldr r2, [r7, #0]
|
|
80069d0: 7812 ldrb r2, [r2, #0]
|
|
80069d2: 0151 lsls r1, r2, #5
|
|
80069d4: 693a ldr r2, [r7, #16]
|
|
80069d6: 440a add r2, r1
|
|
80069d8: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80069dc: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80069e0: 6013 str r3, [r2, #0]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
80069e2: 68fb ldr r3, [r7, #12]
|
|
80069e4: 3301 adds r3, #1
|
|
80069e6: 60fb str r3, [r7, #12]
|
|
|
|
if (count > 10000U)
|
|
80069e8: 68fb ldr r3, [r7, #12]
|
|
80069ea: f242 7210 movw r2, #10000 @ 0x2710
|
|
80069ee: 4293 cmp r3, r2
|
|
80069f0: d902 bls.n 80069f8 <USB_EPStopXfer+0x98>
|
|
{
|
|
ret = HAL_ERROR;
|
|
80069f2: 2301 movs r3, #1
|
|
80069f4: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80069f6: e056 b.n 8006aa6 <USB_EPStopXfer+0x146>
|
|
}
|
|
} while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA);
|
|
80069f8: 683b ldr r3, [r7, #0]
|
|
80069fa: 781b ldrb r3, [r3, #0]
|
|
80069fc: 015a lsls r2, r3, #5
|
|
80069fe: 693b ldr r3, [r7, #16]
|
|
8006a00: 4413 add r3, r2
|
|
8006a02: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006a06: 681b ldr r3, [r3, #0]
|
|
8006a08: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006a0c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8006a10: d0e7 beq.n 80069e2 <USB_EPStopXfer+0x82>
|
|
8006a12: e048 b.n 8006aa6 <USB_EPStopXfer+0x146>
|
|
}
|
|
}
|
|
else /* OUT endpoint */
|
|
{
|
|
if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
8006a14: 683b ldr r3, [r7, #0]
|
|
8006a16: 781b ldrb r3, [r3, #0]
|
|
8006a18: 015a lsls r2, r3, #5
|
|
8006a1a: 693b ldr r3, [r7, #16]
|
|
8006a1c: 4413 add r3, r2
|
|
8006a1e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006a22: 681b ldr r3, [r3, #0]
|
|
8006a24: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006a28: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8006a2c: d13b bne.n 8006aa6 <USB_EPStopXfer+0x146>
|
|
{
|
|
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
|
|
8006a2e: 683b ldr r3, [r7, #0]
|
|
8006a30: 781b ldrb r3, [r3, #0]
|
|
8006a32: 015a lsls r2, r3, #5
|
|
8006a34: 693b ldr r3, [r7, #16]
|
|
8006a36: 4413 add r3, r2
|
|
8006a38: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006a3c: 681b ldr r3, [r3, #0]
|
|
8006a3e: 683a ldr r2, [r7, #0]
|
|
8006a40: 7812 ldrb r2, [r2, #0]
|
|
8006a42: 0151 lsls r1, r2, #5
|
|
8006a44: 693a ldr r2, [r7, #16]
|
|
8006a46: 440a add r2, r1
|
|
8006a48: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006a4c: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8006a50: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
|
|
8006a52: 683b ldr r3, [r7, #0]
|
|
8006a54: 781b ldrb r3, [r3, #0]
|
|
8006a56: 015a lsls r2, r3, #5
|
|
8006a58: 693b ldr r3, [r7, #16]
|
|
8006a5a: 4413 add r3, r2
|
|
8006a5c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006a60: 681b ldr r3, [r3, #0]
|
|
8006a62: 683a ldr r2, [r7, #0]
|
|
8006a64: 7812 ldrb r2, [r2, #0]
|
|
8006a66: 0151 lsls r1, r2, #5
|
|
8006a68: 693a ldr r2, [r7, #16]
|
|
8006a6a: 440a add r2, r1
|
|
8006a6c: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006a70: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8006a74: 6013 str r3, [r2, #0]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8006a76: 68fb ldr r3, [r7, #12]
|
|
8006a78: 3301 adds r3, #1
|
|
8006a7a: 60fb str r3, [r7, #12]
|
|
|
|
if (count > 10000U)
|
|
8006a7c: 68fb ldr r3, [r7, #12]
|
|
8006a7e: f242 7210 movw r2, #10000 @ 0x2710
|
|
8006a82: 4293 cmp r3, r2
|
|
8006a84: d902 bls.n 8006a8c <USB_EPStopXfer+0x12c>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006a86: 2301 movs r3, #1
|
|
8006a88: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8006a8a: e00c b.n 8006aa6 <USB_EPStopXfer+0x146>
|
|
}
|
|
} while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA);
|
|
8006a8c: 683b ldr r3, [r7, #0]
|
|
8006a8e: 781b ldrb r3, [r3, #0]
|
|
8006a90: 015a lsls r2, r3, #5
|
|
8006a92: 693b ldr r3, [r7, #16]
|
|
8006a94: 4413 add r3, r2
|
|
8006a96: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006a9a: 681b ldr r3, [r3, #0]
|
|
8006a9c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006aa0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8006aa4: d0e7 beq.n 8006a76 <USB_EPStopXfer+0x116>
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
8006aa6: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8006aa8: 4618 mov r0, r3
|
|
8006aaa: 371c adds r7, #28
|
|
8006aac: 46bd mov sp, r7
|
|
8006aae: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006ab2: 4770 bx lr
|
|
|
|
08006ab4 <USB_WritePacket>:
|
|
* 1 : DMA feature used
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
|
|
uint8_t ch_ep_num, uint16_t len, uint8_t dma)
|
|
{
|
|
8006ab4: b480 push {r7}
|
|
8006ab6: b089 sub sp, #36 @ 0x24
|
|
8006ab8: af00 add r7, sp, #0
|
|
8006aba: 60f8 str r0, [r7, #12]
|
|
8006abc: 60b9 str r1, [r7, #8]
|
|
8006abe: 4611 mov r1, r2
|
|
8006ac0: 461a mov r2, r3
|
|
8006ac2: 460b mov r3, r1
|
|
8006ac4: 71fb strb r3, [r7, #7]
|
|
8006ac6: 4613 mov r3, r2
|
|
8006ac8: 80bb strh r3, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006aca: 68fb ldr r3, [r7, #12]
|
|
8006acc: 617b str r3, [r7, #20]
|
|
uint8_t *pSrc = src;
|
|
8006ace: 68bb ldr r3, [r7, #8]
|
|
8006ad0: 61fb str r3, [r7, #28]
|
|
uint32_t count32b;
|
|
uint32_t i;
|
|
|
|
if (dma == 0U)
|
|
8006ad2: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8006ad6: 2b00 cmp r3, #0
|
|
8006ad8: d123 bne.n 8006b22 <USB_WritePacket+0x6e>
|
|
{
|
|
count32b = ((uint32_t)len + 3U) / 4U;
|
|
8006ada: 88bb ldrh r3, [r7, #4]
|
|
8006adc: 3303 adds r3, #3
|
|
8006ade: 089b lsrs r3, r3, #2
|
|
8006ae0: 613b str r3, [r7, #16]
|
|
for (i = 0U; i < count32b; i++)
|
|
8006ae2: 2300 movs r3, #0
|
|
8006ae4: 61bb str r3, [r7, #24]
|
|
8006ae6: e018 b.n 8006b1a <USB_WritePacket+0x66>
|
|
{
|
|
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
|
|
8006ae8: 79fb ldrb r3, [r7, #7]
|
|
8006aea: 031a lsls r2, r3, #12
|
|
8006aec: 697b ldr r3, [r7, #20]
|
|
8006aee: 4413 add r3, r2
|
|
8006af0: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8006af4: 461a mov r2, r3
|
|
8006af6: 69fb ldr r3, [r7, #28]
|
|
8006af8: 681b ldr r3, [r3, #0]
|
|
8006afa: 6013 str r3, [r2, #0]
|
|
pSrc++;
|
|
8006afc: 69fb ldr r3, [r7, #28]
|
|
8006afe: 3301 adds r3, #1
|
|
8006b00: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8006b02: 69fb ldr r3, [r7, #28]
|
|
8006b04: 3301 adds r3, #1
|
|
8006b06: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8006b08: 69fb ldr r3, [r7, #28]
|
|
8006b0a: 3301 adds r3, #1
|
|
8006b0c: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8006b0e: 69fb ldr r3, [r7, #28]
|
|
8006b10: 3301 adds r3, #1
|
|
8006b12: 61fb str r3, [r7, #28]
|
|
for (i = 0U; i < count32b; i++)
|
|
8006b14: 69bb ldr r3, [r7, #24]
|
|
8006b16: 3301 adds r3, #1
|
|
8006b18: 61bb str r3, [r7, #24]
|
|
8006b1a: 69ba ldr r2, [r7, #24]
|
|
8006b1c: 693b ldr r3, [r7, #16]
|
|
8006b1e: 429a cmp r2, r3
|
|
8006b20: d3e2 bcc.n 8006ae8 <USB_WritePacket+0x34>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006b22: 2300 movs r3, #0
|
|
}
|
|
8006b24: 4618 mov r0, r3
|
|
8006b26: 3724 adds r7, #36 @ 0x24
|
|
8006b28: 46bd mov sp, r7
|
|
8006b2a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006b2e: 4770 bx lr
|
|
|
|
08006b30 <USB_ReadPacket>:
|
|
* @param dest source pointer
|
|
* @param len Number of bytes to read
|
|
* @retval pointer to destination buffer
|
|
*/
|
|
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
|
|
{
|
|
8006b30: b480 push {r7}
|
|
8006b32: b08b sub sp, #44 @ 0x2c
|
|
8006b34: af00 add r7, sp, #0
|
|
8006b36: 60f8 str r0, [r7, #12]
|
|
8006b38: 60b9 str r1, [r7, #8]
|
|
8006b3a: 4613 mov r3, r2
|
|
8006b3c: 80fb strh r3, [r7, #6]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006b3e: 68fb ldr r3, [r7, #12]
|
|
8006b40: 61bb str r3, [r7, #24]
|
|
uint8_t *pDest = dest;
|
|
8006b42: 68bb ldr r3, [r7, #8]
|
|
8006b44: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t pData;
|
|
uint32_t i;
|
|
uint32_t count32b = (uint32_t)len >> 2U;
|
|
8006b46: 88fb ldrh r3, [r7, #6]
|
|
8006b48: 089b lsrs r3, r3, #2
|
|
8006b4a: b29b uxth r3, r3
|
|
8006b4c: 617b str r3, [r7, #20]
|
|
uint16_t remaining_bytes = len % 4U;
|
|
8006b4e: 88fb ldrh r3, [r7, #6]
|
|
8006b50: f003 0303 and.w r3, r3, #3
|
|
8006b54: 83fb strh r3, [r7, #30]
|
|
|
|
for (i = 0U; i < count32b; i++)
|
|
8006b56: 2300 movs r3, #0
|
|
8006b58: 623b str r3, [r7, #32]
|
|
8006b5a: e014 b.n 8006b86 <USB_ReadPacket+0x56>
|
|
{
|
|
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
|
|
8006b5c: 69bb ldr r3, [r7, #24]
|
|
8006b5e: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8006b62: 681a ldr r2, [r3, #0]
|
|
8006b64: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006b66: 601a str r2, [r3, #0]
|
|
pDest++;
|
|
8006b68: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006b6a: 3301 adds r3, #1
|
|
8006b6c: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8006b6e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006b70: 3301 adds r3, #1
|
|
8006b72: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8006b74: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006b76: 3301 adds r3, #1
|
|
8006b78: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8006b7a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006b7c: 3301 adds r3, #1
|
|
8006b7e: 627b str r3, [r7, #36] @ 0x24
|
|
for (i = 0U; i < count32b; i++)
|
|
8006b80: 6a3b ldr r3, [r7, #32]
|
|
8006b82: 3301 adds r3, #1
|
|
8006b84: 623b str r3, [r7, #32]
|
|
8006b86: 6a3a ldr r2, [r7, #32]
|
|
8006b88: 697b ldr r3, [r7, #20]
|
|
8006b8a: 429a cmp r2, r3
|
|
8006b8c: d3e6 bcc.n 8006b5c <USB_ReadPacket+0x2c>
|
|
}
|
|
|
|
/* When Number of data is not word aligned, read the remaining byte */
|
|
if (remaining_bytes != 0U)
|
|
8006b8e: 8bfb ldrh r3, [r7, #30]
|
|
8006b90: 2b00 cmp r3, #0
|
|
8006b92: d01e beq.n 8006bd2 <USB_ReadPacket+0xa2>
|
|
{
|
|
i = 0U;
|
|
8006b94: 2300 movs r3, #0
|
|
8006b96: 623b str r3, [r7, #32]
|
|
__UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
|
|
8006b98: 69bb ldr r3, [r7, #24]
|
|
8006b9a: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8006b9e: 461a mov r2, r3
|
|
8006ba0: f107 0310 add.w r3, r7, #16
|
|
8006ba4: 6812 ldr r2, [r2, #0]
|
|
8006ba6: 601a str r2, [r3, #0]
|
|
|
|
do
|
|
{
|
|
*(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
|
|
8006ba8: 693a ldr r2, [r7, #16]
|
|
8006baa: 6a3b ldr r3, [r7, #32]
|
|
8006bac: b2db uxtb r3, r3
|
|
8006bae: 00db lsls r3, r3, #3
|
|
8006bb0: fa22 f303 lsr.w r3, r2, r3
|
|
8006bb4: b2da uxtb r2, r3
|
|
8006bb6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006bb8: 701a strb r2, [r3, #0]
|
|
i++;
|
|
8006bba: 6a3b ldr r3, [r7, #32]
|
|
8006bbc: 3301 adds r3, #1
|
|
8006bbe: 623b str r3, [r7, #32]
|
|
pDest++;
|
|
8006bc0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006bc2: 3301 adds r3, #1
|
|
8006bc4: 627b str r3, [r7, #36] @ 0x24
|
|
remaining_bytes--;
|
|
8006bc6: 8bfb ldrh r3, [r7, #30]
|
|
8006bc8: 3b01 subs r3, #1
|
|
8006bca: 83fb strh r3, [r7, #30]
|
|
} while (remaining_bytes != 0U);
|
|
8006bcc: 8bfb ldrh r3, [r7, #30]
|
|
8006bce: 2b00 cmp r3, #0
|
|
8006bd0: d1ea bne.n 8006ba8 <USB_ReadPacket+0x78>
|
|
}
|
|
|
|
return ((void *)pDest);
|
|
8006bd2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
}
|
|
8006bd4: 4618 mov r0, r3
|
|
8006bd6: 372c adds r7, #44 @ 0x2c
|
|
8006bd8: 46bd mov sp, r7
|
|
8006bda: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006bde: 4770 bx lr
|
|
|
|
08006be0 <USB_EPSetStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8006be0: b480 push {r7}
|
|
8006be2: b085 sub sp, #20
|
|
8006be4: af00 add r7, sp, #0
|
|
8006be6: 6078 str r0, [r7, #4]
|
|
8006be8: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006bea: 687b ldr r3, [r7, #4]
|
|
8006bec: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8006bee: 683b ldr r3, [r7, #0]
|
|
8006bf0: 781b ldrb r3, [r3, #0]
|
|
8006bf2: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
8006bf4: 683b ldr r3, [r7, #0]
|
|
8006bf6: 785b ldrb r3, [r3, #1]
|
|
8006bf8: 2b01 cmp r3, #1
|
|
8006bfa: d12c bne.n 8006c56 <USB_EPSetStall+0x76>
|
|
{
|
|
if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
|
|
8006bfc: 68bb ldr r3, [r7, #8]
|
|
8006bfe: 015a lsls r2, r3, #5
|
|
8006c00: 68fb ldr r3, [r7, #12]
|
|
8006c02: 4413 add r3, r2
|
|
8006c04: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006c08: 681b ldr r3, [r3, #0]
|
|
8006c0a: 2b00 cmp r3, #0
|
|
8006c0c: db12 blt.n 8006c34 <USB_EPSetStall+0x54>
|
|
8006c0e: 68bb ldr r3, [r7, #8]
|
|
8006c10: 2b00 cmp r3, #0
|
|
8006c12: d00f beq.n 8006c34 <USB_EPSetStall+0x54>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
|
|
8006c14: 68bb ldr r3, [r7, #8]
|
|
8006c16: 015a lsls r2, r3, #5
|
|
8006c18: 68fb ldr r3, [r7, #12]
|
|
8006c1a: 4413 add r3, r2
|
|
8006c1c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006c20: 681b ldr r3, [r3, #0]
|
|
8006c22: 68ba ldr r2, [r7, #8]
|
|
8006c24: 0151 lsls r1, r2, #5
|
|
8006c26: 68fa ldr r2, [r7, #12]
|
|
8006c28: 440a add r2, r1
|
|
8006c2a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006c2e: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8006c32: 6013 str r3, [r2, #0]
|
|
}
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
|
|
8006c34: 68bb ldr r3, [r7, #8]
|
|
8006c36: 015a lsls r2, r3, #5
|
|
8006c38: 68fb ldr r3, [r7, #12]
|
|
8006c3a: 4413 add r3, r2
|
|
8006c3c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006c40: 681b ldr r3, [r3, #0]
|
|
8006c42: 68ba ldr r2, [r7, #8]
|
|
8006c44: 0151 lsls r1, r2, #5
|
|
8006c46: 68fa ldr r2, [r7, #12]
|
|
8006c48: 440a add r2, r1
|
|
8006c4a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006c4e: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8006c52: 6013 str r3, [r2, #0]
|
|
8006c54: e02b b.n 8006cae <USB_EPSetStall+0xce>
|
|
}
|
|
else
|
|
{
|
|
if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
|
|
8006c56: 68bb ldr r3, [r7, #8]
|
|
8006c58: 015a lsls r2, r3, #5
|
|
8006c5a: 68fb ldr r3, [r7, #12]
|
|
8006c5c: 4413 add r3, r2
|
|
8006c5e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006c62: 681b ldr r3, [r3, #0]
|
|
8006c64: 2b00 cmp r3, #0
|
|
8006c66: db12 blt.n 8006c8e <USB_EPSetStall+0xae>
|
|
8006c68: 68bb ldr r3, [r7, #8]
|
|
8006c6a: 2b00 cmp r3, #0
|
|
8006c6c: d00f beq.n 8006c8e <USB_EPSetStall+0xae>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
|
|
8006c6e: 68bb ldr r3, [r7, #8]
|
|
8006c70: 015a lsls r2, r3, #5
|
|
8006c72: 68fb ldr r3, [r7, #12]
|
|
8006c74: 4413 add r3, r2
|
|
8006c76: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006c7a: 681b ldr r3, [r3, #0]
|
|
8006c7c: 68ba ldr r2, [r7, #8]
|
|
8006c7e: 0151 lsls r1, r2, #5
|
|
8006c80: 68fa ldr r2, [r7, #12]
|
|
8006c82: 440a add r2, r1
|
|
8006c84: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006c88: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8006c8c: 6013 str r3, [r2, #0]
|
|
}
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
|
|
8006c8e: 68bb ldr r3, [r7, #8]
|
|
8006c90: 015a lsls r2, r3, #5
|
|
8006c92: 68fb ldr r3, [r7, #12]
|
|
8006c94: 4413 add r3, r2
|
|
8006c96: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006c9a: 681b ldr r3, [r3, #0]
|
|
8006c9c: 68ba ldr r2, [r7, #8]
|
|
8006c9e: 0151 lsls r1, r2, #5
|
|
8006ca0: 68fa ldr r2, [r7, #12]
|
|
8006ca2: 440a add r2, r1
|
|
8006ca4: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006ca8: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8006cac: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006cae: 2300 movs r3, #0
|
|
}
|
|
8006cb0: 4618 mov r0, r3
|
|
8006cb2: 3714 adds r7, #20
|
|
8006cb4: 46bd mov sp, r7
|
|
8006cb6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006cba: 4770 bx lr
|
|
|
|
08006cbc <USB_EPClearStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8006cbc: b480 push {r7}
|
|
8006cbe: b085 sub sp, #20
|
|
8006cc0: af00 add r7, sp, #0
|
|
8006cc2: 6078 str r0, [r7, #4]
|
|
8006cc4: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006cc6: 687b ldr r3, [r7, #4]
|
|
8006cc8: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8006cca: 683b ldr r3, [r7, #0]
|
|
8006ccc: 781b ldrb r3, [r3, #0]
|
|
8006cce: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
8006cd0: 683b ldr r3, [r7, #0]
|
|
8006cd2: 785b ldrb r3, [r3, #1]
|
|
8006cd4: 2b01 cmp r3, #1
|
|
8006cd6: d128 bne.n 8006d2a <USB_EPClearStall+0x6e>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
|
8006cd8: 68bb ldr r3, [r7, #8]
|
|
8006cda: 015a lsls r2, r3, #5
|
|
8006cdc: 68fb ldr r3, [r7, #12]
|
|
8006cde: 4413 add r3, r2
|
|
8006ce0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006ce4: 681b ldr r3, [r3, #0]
|
|
8006ce6: 68ba ldr r2, [r7, #8]
|
|
8006ce8: 0151 lsls r1, r2, #5
|
|
8006cea: 68fa ldr r2, [r7, #12]
|
|
8006cec: 440a add r2, r1
|
|
8006cee: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006cf2: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
8006cf6: 6013 str r3, [r2, #0]
|
|
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
|
|
8006cf8: 683b ldr r3, [r7, #0]
|
|
8006cfa: 791b ldrb r3, [r3, #4]
|
|
8006cfc: 2b03 cmp r3, #3
|
|
8006cfe: d003 beq.n 8006d08 <USB_EPClearStall+0x4c>
|
|
8006d00: 683b ldr r3, [r7, #0]
|
|
8006d02: 791b ldrb r3, [r3, #4]
|
|
8006d04: 2b02 cmp r3, #2
|
|
8006d06: d138 bne.n 8006d7a <USB_EPClearStall+0xbe>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
|
|
8006d08: 68bb ldr r3, [r7, #8]
|
|
8006d0a: 015a lsls r2, r3, #5
|
|
8006d0c: 68fb ldr r3, [r7, #12]
|
|
8006d0e: 4413 add r3, r2
|
|
8006d10: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006d14: 681b ldr r3, [r3, #0]
|
|
8006d16: 68ba ldr r2, [r7, #8]
|
|
8006d18: 0151 lsls r1, r2, #5
|
|
8006d1a: 68fa ldr r2, [r7, #12]
|
|
8006d1c: 440a add r2, r1
|
|
8006d1e: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006d22: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006d26: 6013 str r3, [r2, #0]
|
|
8006d28: e027 b.n 8006d7a <USB_EPClearStall+0xbe>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
|
8006d2a: 68bb ldr r3, [r7, #8]
|
|
8006d2c: 015a lsls r2, r3, #5
|
|
8006d2e: 68fb ldr r3, [r7, #12]
|
|
8006d30: 4413 add r3, r2
|
|
8006d32: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006d36: 681b ldr r3, [r3, #0]
|
|
8006d38: 68ba ldr r2, [r7, #8]
|
|
8006d3a: 0151 lsls r1, r2, #5
|
|
8006d3c: 68fa ldr r2, [r7, #12]
|
|
8006d3e: 440a add r2, r1
|
|
8006d40: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006d44: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
8006d48: 6013 str r3, [r2, #0]
|
|
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
|
|
8006d4a: 683b ldr r3, [r7, #0]
|
|
8006d4c: 791b ldrb r3, [r3, #4]
|
|
8006d4e: 2b03 cmp r3, #3
|
|
8006d50: d003 beq.n 8006d5a <USB_EPClearStall+0x9e>
|
|
8006d52: 683b ldr r3, [r7, #0]
|
|
8006d54: 791b ldrb r3, [r3, #4]
|
|
8006d56: 2b02 cmp r3, #2
|
|
8006d58: d10f bne.n 8006d7a <USB_EPClearStall+0xbe>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
|
|
8006d5a: 68bb ldr r3, [r7, #8]
|
|
8006d5c: 015a lsls r2, r3, #5
|
|
8006d5e: 68fb ldr r3, [r7, #12]
|
|
8006d60: 4413 add r3, r2
|
|
8006d62: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006d66: 681b ldr r3, [r3, #0]
|
|
8006d68: 68ba ldr r2, [r7, #8]
|
|
8006d6a: 0151 lsls r1, r2, #5
|
|
8006d6c: 68fa ldr r2, [r7, #12]
|
|
8006d6e: 440a add r2, r1
|
|
8006d70: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006d74: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006d78: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8006d7a: 2300 movs r3, #0
|
|
}
|
|
8006d7c: 4618 mov r0, r3
|
|
8006d7e: 3714 adds r7, #20
|
|
8006d80: 46bd mov sp, r7
|
|
8006d82: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006d86: 4770 bx lr
|
|
|
|
08006d88 <USB_SetDevAddress>:
|
|
* @param address new device address to be assigned
|
|
* This parameter can be a value from 0 to 255
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
|
|
{
|
|
8006d88: b480 push {r7}
|
|
8006d8a: b085 sub sp, #20
|
|
8006d8c: af00 add r7, sp, #0
|
|
8006d8e: 6078 str r0, [r7, #4]
|
|
8006d90: 460b mov r3, r1
|
|
8006d92: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006d94: 687b ldr r3, [r7, #4]
|
|
8006d96: 60fb str r3, [r7, #12]
|
|
|
|
USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
|
|
8006d98: 68fb ldr r3, [r7, #12]
|
|
8006d9a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006d9e: 681b ldr r3, [r3, #0]
|
|
8006da0: 68fa ldr r2, [r7, #12]
|
|
8006da2: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8006da6: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
|
|
8006daa: 6013 str r3, [r2, #0]
|
|
USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
|
|
8006dac: 68fb ldr r3, [r7, #12]
|
|
8006dae: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006db2: 681a ldr r2, [r3, #0]
|
|
8006db4: 78fb ldrb r3, [r7, #3]
|
|
8006db6: 011b lsls r3, r3, #4
|
|
8006db8: f403 63fe and.w r3, r3, #2032 @ 0x7f0
|
|
8006dbc: 68f9 ldr r1, [r7, #12]
|
|
8006dbe: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8006dc2: 4313 orrs r3, r2
|
|
8006dc4: 600b str r3, [r1, #0]
|
|
|
|
return HAL_OK;
|
|
8006dc6: 2300 movs r3, #0
|
|
}
|
|
8006dc8: 4618 mov r0, r3
|
|
8006dca: 3714 adds r7, #20
|
|
8006dcc: 46bd mov sp, r7
|
|
8006dce: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006dd2: 4770 bx lr
|
|
|
|
08006dd4 <USB_DevConnect>:
|
|
* @brief USB_DevConnect : Connect the USB device by enabling Rpu
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006dd4: b480 push {r7}
|
|
8006dd6: b085 sub sp, #20
|
|
8006dd8: af00 add r7, sp, #0
|
|
8006dda: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006ddc: 687b ldr r3, [r7, #4]
|
|
8006dde: 60fb str r3, [r7, #12]
|
|
|
|
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
|
|
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
|
|
8006de0: 68fb ldr r3, [r7, #12]
|
|
8006de2: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
8006de6: 681b ldr r3, [r3, #0]
|
|
8006de8: 68fa ldr r2, [r7, #12]
|
|
8006dea: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
8006dee: f023 0303 bic.w r3, r3, #3
|
|
8006df2: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
|
|
8006df4: 68fb ldr r3, [r7, #12]
|
|
8006df6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006dfa: 685b ldr r3, [r3, #4]
|
|
8006dfc: 68fa ldr r2, [r7, #12]
|
|
8006dfe: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8006e02: f023 0302 bic.w r3, r3, #2
|
|
8006e06: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
8006e08: 2300 movs r3, #0
|
|
}
|
|
8006e0a: 4618 mov r0, r3
|
|
8006e0c: 3714 adds r7, #20
|
|
8006e0e: 46bd mov sp, r7
|
|
8006e10: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006e14: 4770 bx lr
|
|
|
|
08006e16 <USB_DevDisconnect>:
|
|
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006e16: b480 push {r7}
|
|
8006e18: b085 sub sp, #20
|
|
8006e1a: af00 add r7, sp, #0
|
|
8006e1c: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006e1e: 687b ldr r3, [r7, #4]
|
|
8006e20: 60fb str r3, [r7, #12]
|
|
|
|
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
|
|
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
|
|
8006e22: 68fb ldr r3, [r7, #12]
|
|
8006e24: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
8006e28: 681b ldr r3, [r3, #0]
|
|
8006e2a: 68fa ldr r2, [r7, #12]
|
|
8006e2c: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
8006e30: f023 0303 bic.w r3, r3, #3
|
|
8006e34: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
8006e36: 68fb ldr r3, [r7, #12]
|
|
8006e38: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006e3c: 685b ldr r3, [r3, #4]
|
|
8006e3e: 68fa ldr r2, [r7, #12]
|
|
8006e40: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8006e44: f043 0302 orr.w r3, r3, #2
|
|
8006e48: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
8006e4a: 2300 movs r3, #0
|
|
}
|
|
8006e4c: 4618 mov r0, r3
|
|
8006e4e: 3714 adds r7, #20
|
|
8006e50: 46bd mov sp, r7
|
|
8006e52: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006e56: 4770 bx lr
|
|
|
|
08006e58 <USB_ReadInterrupts>:
|
|
* @brief USB_ReadInterrupts: return the global USB interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Global Interrupt status
|
|
*/
|
|
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
|
|
{
|
|
8006e58: b480 push {r7}
|
|
8006e5a: b085 sub sp, #20
|
|
8006e5c: af00 add r7, sp, #0
|
|
8006e5e: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx->GINTSTS;
|
|
8006e60: 687b ldr r3, [r7, #4]
|
|
8006e62: 695b ldr r3, [r3, #20]
|
|
8006e64: 60fb str r3, [r7, #12]
|
|
tmpreg &= USBx->GINTMSK;
|
|
8006e66: 687b ldr r3, [r7, #4]
|
|
8006e68: 699b ldr r3, [r3, #24]
|
|
8006e6a: 68fa ldr r2, [r7, #12]
|
|
8006e6c: 4013 ands r3, r2
|
|
8006e6e: 60fb str r3, [r7, #12]
|
|
|
|
return tmpreg;
|
|
8006e70: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8006e72: 4618 mov r0, r3
|
|
8006e74: 3714 adds r7, #20
|
|
8006e76: 46bd mov sp, r7
|
|
8006e78: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006e7c: 4770 bx lr
|
|
|
|
08006e7e <USB_ReadDevAllOutEpInterrupt>:
|
|
* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Device OUT EP interrupt status
|
|
*/
|
|
uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006e7e: b480 push {r7}
|
|
8006e80: b085 sub sp, #20
|
|
8006e82: af00 add r7, sp, #0
|
|
8006e84: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006e86: 687b ldr r3, [r7, #4]
|
|
8006e88: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_DEVICE->DAINT;
|
|
8006e8a: 68fb ldr r3, [r7, #12]
|
|
8006e8c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006e90: 699b ldr r3, [r3, #24]
|
|
8006e92: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DAINTMSK;
|
|
8006e94: 68fb ldr r3, [r7, #12]
|
|
8006e96: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006e9a: 69db ldr r3, [r3, #28]
|
|
8006e9c: 68ba ldr r2, [r7, #8]
|
|
8006e9e: 4013 ands r3, r2
|
|
8006ea0: 60bb str r3, [r7, #8]
|
|
|
|
return ((tmpreg & 0xffff0000U) >> 16);
|
|
8006ea2: 68bb ldr r3, [r7, #8]
|
|
8006ea4: 0c1b lsrs r3, r3, #16
|
|
}
|
|
8006ea6: 4618 mov r0, r3
|
|
8006ea8: 3714 adds r7, #20
|
|
8006eaa: 46bd mov sp, r7
|
|
8006eac: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006eb0: 4770 bx lr
|
|
|
|
08006eb2 <USB_ReadDevAllInEpInterrupt>:
|
|
* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Device IN EP interrupt status
|
|
*/
|
|
uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006eb2: b480 push {r7}
|
|
8006eb4: b085 sub sp, #20
|
|
8006eb6: af00 add r7, sp, #0
|
|
8006eb8: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006eba: 687b ldr r3, [r7, #4]
|
|
8006ebc: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_DEVICE->DAINT;
|
|
8006ebe: 68fb ldr r3, [r7, #12]
|
|
8006ec0: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006ec4: 699b ldr r3, [r3, #24]
|
|
8006ec6: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DAINTMSK;
|
|
8006ec8: 68fb ldr r3, [r7, #12]
|
|
8006eca: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006ece: 69db ldr r3, [r3, #28]
|
|
8006ed0: 68ba ldr r2, [r7, #8]
|
|
8006ed2: 4013 ands r3, r2
|
|
8006ed4: 60bb str r3, [r7, #8]
|
|
|
|
return ((tmpreg & 0xFFFFU));
|
|
8006ed6: 68bb ldr r3, [r7, #8]
|
|
8006ed8: b29b uxth r3, r3
|
|
}
|
|
8006eda: 4618 mov r0, r3
|
|
8006edc: 3714 adds r7, #20
|
|
8006ede: 46bd mov sp, r7
|
|
8006ee0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006ee4: 4770 bx lr
|
|
|
|
08006ee6 <USB_ReadDevOutEPInterrupt>:
|
|
* @param epnum endpoint number
|
|
* This parameter can be a value from 0 to 15
|
|
* @retval Device OUT EP Interrupt register
|
|
*/
|
|
uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
|
|
{
|
|
8006ee6: b480 push {r7}
|
|
8006ee8: b085 sub sp, #20
|
|
8006eea: af00 add r7, sp, #0
|
|
8006eec: 6078 str r0, [r7, #4]
|
|
8006eee: 460b mov r3, r1
|
|
8006ef0: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006ef2: 687b ldr r3, [r7, #4]
|
|
8006ef4: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
|
|
8006ef6: 78fb ldrb r3, [r7, #3]
|
|
8006ef8: 015a lsls r2, r3, #5
|
|
8006efa: 68fb ldr r3, [r7, #12]
|
|
8006efc: 4413 add r3, r2
|
|
8006efe: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006f02: 689b ldr r3, [r3, #8]
|
|
8006f04: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DOEPMSK;
|
|
8006f06: 68fb ldr r3, [r7, #12]
|
|
8006f08: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006f0c: 695b ldr r3, [r3, #20]
|
|
8006f0e: 68ba ldr r2, [r7, #8]
|
|
8006f10: 4013 ands r3, r2
|
|
8006f12: 60bb str r3, [r7, #8]
|
|
|
|
return tmpreg;
|
|
8006f14: 68bb ldr r3, [r7, #8]
|
|
}
|
|
8006f16: 4618 mov r0, r3
|
|
8006f18: 3714 adds r7, #20
|
|
8006f1a: 46bd mov sp, r7
|
|
8006f1c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f20: 4770 bx lr
|
|
|
|
08006f22 <USB_ReadDevInEPInterrupt>:
|
|
* @param epnum endpoint number
|
|
* This parameter can be a value from 0 to 15
|
|
* @retval Device IN EP Interrupt register
|
|
*/
|
|
uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
|
|
{
|
|
8006f22: b480 push {r7}
|
|
8006f24: b087 sub sp, #28
|
|
8006f26: af00 add r7, sp, #0
|
|
8006f28: 6078 str r0, [r7, #4]
|
|
8006f2a: 460b mov r3, r1
|
|
8006f2c: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006f2e: 687b ldr r3, [r7, #4]
|
|
8006f30: 617b str r3, [r7, #20]
|
|
uint32_t tmpreg;
|
|
uint32_t msk;
|
|
uint32_t emp;
|
|
|
|
msk = USBx_DEVICE->DIEPMSK;
|
|
8006f32: 697b ldr r3, [r7, #20]
|
|
8006f34: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006f38: 691b ldr r3, [r3, #16]
|
|
8006f3a: 613b str r3, [r7, #16]
|
|
emp = USBx_DEVICE->DIEPEMPMSK;
|
|
8006f3c: 697b ldr r3, [r7, #20]
|
|
8006f3e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006f42: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8006f44: 60fb str r3, [r7, #12]
|
|
msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
|
|
8006f46: 78fb ldrb r3, [r7, #3]
|
|
8006f48: f003 030f and.w r3, r3, #15
|
|
8006f4c: 68fa ldr r2, [r7, #12]
|
|
8006f4e: fa22 f303 lsr.w r3, r2, r3
|
|
8006f52: 01db lsls r3, r3, #7
|
|
8006f54: b2db uxtb r3, r3
|
|
8006f56: 693a ldr r2, [r7, #16]
|
|
8006f58: 4313 orrs r3, r2
|
|
8006f5a: 613b str r3, [r7, #16]
|
|
tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
|
|
8006f5c: 78fb ldrb r3, [r7, #3]
|
|
8006f5e: 015a lsls r2, r3, #5
|
|
8006f60: 697b ldr r3, [r7, #20]
|
|
8006f62: 4413 add r3, r2
|
|
8006f64: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006f68: 689b ldr r3, [r3, #8]
|
|
8006f6a: 693a ldr r2, [r7, #16]
|
|
8006f6c: 4013 ands r3, r2
|
|
8006f6e: 60bb str r3, [r7, #8]
|
|
|
|
return tmpreg;
|
|
8006f70: 68bb ldr r3, [r7, #8]
|
|
}
|
|
8006f72: 4618 mov r0, r3
|
|
8006f74: 371c adds r7, #28
|
|
8006f76: 46bd mov sp, r7
|
|
8006f78: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f7c: 4770 bx lr
|
|
|
|
08006f7e <USB_GetMode>:
|
|
* This parameter can be one of these values:
|
|
* 1 : Host
|
|
* 0 : Device
|
|
*/
|
|
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006f7e: b480 push {r7}
|
|
8006f80: b083 sub sp, #12
|
|
8006f82: af00 add r7, sp, #0
|
|
8006f84: 6078 str r0, [r7, #4]
|
|
return ((USBx->GINTSTS) & 0x1U);
|
|
8006f86: 687b ldr r3, [r7, #4]
|
|
8006f88: 695b ldr r3, [r3, #20]
|
|
8006f8a: f003 0301 and.w r3, r3, #1
|
|
}
|
|
8006f8e: 4618 mov r0, r3
|
|
8006f90: 370c adds r7, #12
|
|
8006f92: 46bd mov sp, r7
|
|
8006f94: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f98: 4770 bx lr
|
|
|
|
08006f9a <USB_ActivateSetup>:
|
|
* @brief Activate EP0 for Setup transactions
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006f9a: b480 push {r7}
|
|
8006f9c: b085 sub sp, #20
|
|
8006f9e: af00 add r7, sp, #0
|
|
8006fa0: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006fa2: 687b ldr r3, [r7, #4]
|
|
8006fa4: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the MPS of the IN EP0 to 64 bytes */
|
|
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
|
|
8006fa6: 68fb ldr r3, [r7, #12]
|
|
8006fa8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006fac: 681b ldr r3, [r3, #0]
|
|
8006fae: 68fa ldr r2, [r7, #12]
|
|
8006fb0: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006fb4: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
|
|
8006fb8: f023 0307 bic.w r3, r3, #7
|
|
8006fbc: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
|
|
8006fbe: 68fb ldr r3, [r7, #12]
|
|
8006fc0: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006fc4: 685b ldr r3, [r3, #4]
|
|
8006fc6: 68fa ldr r2, [r7, #12]
|
|
8006fc8: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8006fcc: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8006fd0: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
8006fd2: 2300 movs r3, #0
|
|
}
|
|
8006fd4: 4618 mov r0, r3
|
|
8006fd6: 3714 adds r7, #20
|
|
8006fd8: 46bd mov sp, r7
|
|
8006fda: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006fde: 4770 bx lr
|
|
|
|
08006fe0 <USB_EP0_OutStart>:
|
|
* 1 : DMA feature used
|
|
* @param psetup pointer to setup packet
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup)
|
|
{
|
|
8006fe0: b480 push {r7}
|
|
8006fe2: b087 sub sp, #28
|
|
8006fe4: af00 add r7, sp, #0
|
|
8006fe6: 60f8 str r0, [r7, #12]
|
|
8006fe8: 460b mov r3, r1
|
|
8006fea: 607a str r2, [r7, #4]
|
|
8006fec: 72fb strb r3, [r7, #11]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006fee: 68fb ldr r3, [r7, #12]
|
|
8006ff0: 617b str r3, [r7, #20]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
8006ff2: 68fb ldr r3, [r7, #12]
|
|
8006ff4: 333c adds r3, #60 @ 0x3c
|
|
8006ff6: 3304 adds r3, #4
|
|
8006ff8: 681b ldr r3, [r3, #0]
|
|
8006ffa: 613b str r3, [r7, #16]
|
|
|
|
if (gSNPSiD > USB_OTG_CORE_ID_300A)
|
|
8006ffc: 693b ldr r3, [r7, #16]
|
|
8006ffe: 4a26 ldr r2, [pc, #152] @ (8007098 <USB_EP0_OutStart+0xb8>)
|
|
8007000: 4293 cmp r3, r2
|
|
8007002: d90a bls.n 800701a <USB_EP0_OutStart+0x3a>
|
|
{
|
|
if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
8007004: 697b ldr r3, [r7, #20]
|
|
8007006: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800700a: 681b ldr r3, [r3, #0]
|
|
800700c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007010: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8007014: d101 bne.n 800701a <USB_EP0_OutStart+0x3a>
|
|
{
|
|
return HAL_OK;
|
|
8007016: 2300 movs r3, #0
|
|
8007018: e037 b.n 800708a <USB_EP0_OutStart+0xaa>
|
|
}
|
|
}
|
|
|
|
USBx_OUTEP(0U)->DOEPTSIZ = 0U;
|
|
800701a: 697b ldr r3, [r7, #20]
|
|
800701c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007020: 461a mov r2, r3
|
|
8007022: 2300 movs r3, #0
|
|
8007024: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
8007026: 697b ldr r3, [r7, #20]
|
|
8007028: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800702c: 691b ldr r3, [r3, #16]
|
|
800702e: 697a ldr r2, [r7, #20]
|
|
8007030: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007034: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8007038: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
|
|
800703a: 697b ldr r3, [r7, #20]
|
|
800703c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007040: 691b ldr r3, [r3, #16]
|
|
8007042: 697a ldr r2, [r7, #20]
|
|
8007044: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007048: f043 0318 orr.w r3, r3, #24
|
|
800704c: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
|
|
800704e: 697b ldr r3, [r7, #20]
|
|
8007050: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007054: 691b ldr r3, [r3, #16]
|
|
8007056: 697a ldr r2, [r7, #20]
|
|
8007058: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800705c: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000
|
|
8007060: 6113 str r3, [r2, #16]
|
|
|
|
if (dma == 1U)
|
|
8007062: 7afb ldrb r3, [r7, #11]
|
|
8007064: 2b01 cmp r3, #1
|
|
8007066: d10f bne.n 8007088 <USB_EP0_OutStart+0xa8>
|
|
{
|
|
USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
|
|
8007068: 697b ldr r3, [r7, #20]
|
|
800706a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800706e: 461a mov r2, r3
|
|
8007070: 687b ldr r3, [r7, #4]
|
|
8007072: 6153 str r3, [r2, #20]
|
|
/* EP enable */
|
|
USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
|
|
8007074: 697b ldr r3, [r7, #20]
|
|
8007076: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800707a: 681b ldr r3, [r3, #0]
|
|
800707c: 697a ldr r2, [r7, #20]
|
|
800707e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007082: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000
|
|
8007086: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007088: 2300 movs r3, #0
|
|
}
|
|
800708a: 4618 mov r0, r3
|
|
800708c: 371c adds r7, #28
|
|
800708e: 46bd mov sp, r7
|
|
8007090: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007094: 4770 bx lr
|
|
8007096: bf00 nop
|
|
8007098: 4f54300a .word 0x4f54300a
|
|
|
|
0800709c <USB_CoreReset>:
|
|
* @brief Reset the USB Core (needed after USB clock settings change)
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800709c: b480 push {r7}
|
|
800709e: b085 sub sp, #20
|
|
80070a0: af00 add r7, sp, #0
|
|
80070a2: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
80070a4: 2300 movs r3, #0
|
|
80070a6: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
80070a8: 68fb ldr r3, [r7, #12]
|
|
80070aa: 3301 adds r3, #1
|
|
80070ac: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80070ae: 68fb ldr r3, [r7, #12]
|
|
80070b0: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80070b4: d901 bls.n 80070ba <USB_CoreReset+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80070b6: 2303 movs r3, #3
|
|
80070b8: e022 b.n 8007100 <USB_CoreReset+0x64>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
80070ba: 687b ldr r3, [r7, #4]
|
|
80070bc: 691b ldr r3, [r3, #16]
|
|
80070be: 2b00 cmp r3, #0
|
|
80070c0: daf2 bge.n 80070a8 <USB_CoreReset+0xc>
|
|
|
|
count = 10U;
|
|
80070c2: 230a movs r3, #10
|
|
80070c4: 60fb str r3, [r7, #12]
|
|
|
|
/* few cycles before setting core reset */
|
|
while (count > 0U)
|
|
80070c6: e002 b.n 80070ce <USB_CoreReset+0x32>
|
|
{
|
|
count--;
|
|
80070c8: 68fb ldr r3, [r7, #12]
|
|
80070ca: 3b01 subs r3, #1
|
|
80070cc: 60fb str r3, [r7, #12]
|
|
while (count > 0U)
|
|
80070ce: 68fb ldr r3, [r7, #12]
|
|
80070d0: 2b00 cmp r3, #0
|
|
80070d2: d1f9 bne.n 80070c8 <USB_CoreReset+0x2c>
|
|
}
|
|
|
|
/* Core Soft Reset */
|
|
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
|
|
80070d4: 687b ldr r3, [r7, #4]
|
|
80070d6: 691b ldr r3, [r3, #16]
|
|
80070d8: f043 0201 orr.w r2, r3, #1
|
|
80070dc: 687b ldr r3, [r7, #4]
|
|
80070de: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
80070e0: 68fb ldr r3, [r7, #12]
|
|
80070e2: 3301 adds r3, #1
|
|
80070e4: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80070e6: 68fb ldr r3, [r7, #12]
|
|
80070e8: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80070ec: d901 bls.n 80070f2 <USB_CoreReset+0x56>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80070ee: 2303 movs r3, #3
|
|
80070f0: e006 b.n 8007100 <USB_CoreReset+0x64>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
|
|
80070f2: 687b ldr r3, [r7, #4]
|
|
80070f4: 691b ldr r3, [r3, #16]
|
|
80070f6: f003 0301 and.w r3, r3, #1
|
|
80070fa: 2b01 cmp r3, #1
|
|
80070fc: d0f0 beq.n 80070e0 <USB_CoreReset+0x44>
|
|
|
|
return HAL_OK;
|
|
80070fe: 2300 movs r3, #0
|
|
}
|
|
8007100: 4618 mov r0, r3
|
|
8007102: 3714 adds r7, #20
|
|
8007104: 46bd mov sp, r7
|
|
8007106: f85d 7b04 ldr.w r7, [sp], #4
|
|
800710a: 4770 bx lr
|
|
|
|
0800710c <USBD_HID_Init>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
800710c: b580 push {r7, lr}
|
|
800710e: b084 sub sp, #16
|
|
8007110: af00 add r7, sp, #0
|
|
8007112: 6078 str r0, [r7, #4]
|
|
8007114: 460b mov r3, r1
|
|
8007116: 70fb strb r3, [r7, #3]
|
|
UNUSED(cfgidx);
|
|
|
|
USBD_HID_HandleTypeDef *hhid;
|
|
|
|
hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef));
|
|
8007118: 2010 movs r0, #16
|
|
800711a: f002 f9f7 bl 800950c <USBD_static_malloc>
|
|
800711e: 60f8 str r0, [r7, #12]
|
|
|
|
if (hhid == NULL)
|
|
8007120: 68fb ldr r3, [r7, #12]
|
|
8007122: 2b00 cmp r3, #0
|
|
8007124: d109 bne.n 800713a <USBD_HID_Init+0x2e>
|
|
{
|
|
pdev->pClassDataCmsit[pdev->classId] = NULL;
|
|
8007126: 687b ldr r3, [r7, #4]
|
|
8007128: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800712c: 687b ldr r3, [r7, #4]
|
|
800712e: 32b0 adds r2, #176 @ 0xb0
|
|
8007130: 2100 movs r1, #0
|
|
8007132: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
return (uint8_t)USBD_EMEM;
|
|
8007136: 2302 movs r3, #2
|
|
8007138: e048 b.n 80071cc <USBD_HID_Init+0xc0>
|
|
}
|
|
|
|
pdev->pClassDataCmsit[pdev->classId] = (void *)hhid;
|
|
800713a: 687b ldr r3, [r7, #4]
|
|
800713c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007140: 687b ldr r3, [r7, #4]
|
|
8007142: 32b0 adds r2, #176 @ 0xb0
|
|
8007144: 68f9 ldr r1, [r7, #12]
|
|
8007146: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
|
|
800714a: 687b ldr r3, [r7, #4]
|
|
800714c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007150: 687b ldr r3, [r7, #4]
|
|
8007152: 32b0 adds r2, #176 @ 0xb0
|
|
8007154: f853 2022 ldr.w r2, [r3, r2, lsl #2]
|
|
8007158: 687b ldr r3, [r7, #4]
|
|
800715a: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
|
|
#ifdef USE_USBD_COMPOSITE
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
800715e: 687b ldr r3, [r7, #4]
|
|
8007160: 7c1b ldrb r3, [r3, #16]
|
|
8007162: 2b00 cmp r3, #0
|
|
8007164: d10d bne.n 8007182 <USBD_HID_Init+0x76>
|
|
{
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL;
|
|
8007166: 4b1b ldr r3, [pc, #108] @ (80071d4 <USBD_HID_Init+0xc8>)
|
|
8007168: 781b ldrb r3, [r3, #0]
|
|
800716a: f003 020f and.w r2, r3, #15
|
|
800716e: 6879 ldr r1, [r7, #4]
|
|
8007170: 4613 mov r3, r2
|
|
8007172: 009b lsls r3, r3, #2
|
|
8007174: 4413 add r3, r2
|
|
8007176: 009b lsls r3, r3, #2
|
|
8007178: 440b add r3, r1
|
|
800717a: 331c adds r3, #28
|
|
800717c: 2207 movs r2, #7
|
|
800717e: 601a str r2, [r3, #0]
|
|
8007180: e00c b.n 800719c <USBD_HID_Init+0x90>
|
|
}
|
|
else /* LOW and FULL-speed endpoints */
|
|
{
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL;
|
|
8007182: 4b14 ldr r3, [pc, #80] @ (80071d4 <USBD_HID_Init+0xc8>)
|
|
8007184: 781b ldrb r3, [r3, #0]
|
|
8007186: f003 020f and.w r2, r3, #15
|
|
800718a: 6879 ldr r1, [r7, #4]
|
|
800718c: 4613 mov r3, r2
|
|
800718e: 009b lsls r3, r3, #2
|
|
8007190: 4413 add r3, r2
|
|
8007192: 009b lsls r3, r3, #2
|
|
8007194: 440b add r3, r1
|
|
8007196: 331c adds r3, #28
|
|
8007198: 220a movs r2, #10
|
|
800719a: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Open EP IN */
|
|
(void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE);
|
|
800719c: 4b0d ldr r3, [pc, #52] @ (80071d4 <USBD_HID_Init+0xc8>)
|
|
800719e: 7819 ldrb r1, [r3, #0]
|
|
80071a0: 230e movs r3, #14
|
|
80071a2: 2203 movs r2, #3
|
|
80071a4: 6878 ldr r0, [r7, #4]
|
|
80071a6: f002 f852 bl 800924e <USBD_LL_OpenEP>
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U;
|
|
80071aa: 4b0a ldr r3, [pc, #40] @ (80071d4 <USBD_HID_Init+0xc8>)
|
|
80071ac: 781b ldrb r3, [r3, #0]
|
|
80071ae: f003 020f and.w r2, r3, #15
|
|
80071b2: 6879 ldr r1, [r7, #4]
|
|
80071b4: 4613 mov r3, r2
|
|
80071b6: 009b lsls r3, r3, #2
|
|
80071b8: 4413 add r3, r2
|
|
80071ba: 009b lsls r3, r3, #2
|
|
80071bc: 440b add r3, r1
|
|
80071be: 3323 adds r3, #35 @ 0x23
|
|
80071c0: 2201 movs r2, #1
|
|
80071c2: 701a strb r2, [r3, #0]
|
|
|
|
hhid->state = USBD_HID_IDLE;
|
|
80071c4: 68fb ldr r3, [r7, #12]
|
|
80071c6: 2200 movs r2, #0
|
|
80071c8: 731a strb r2, [r3, #12]
|
|
|
|
return (uint8_t)USBD_OK;
|
|
80071ca: 2300 movs r3, #0
|
|
}
|
|
80071cc: 4618 mov r0, r3
|
|
80071ce: 3710 adds r7, #16
|
|
80071d0: 46bd mov sp, r7
|
|
80071d2: bd80 pop {r7, pc}
|
|
80071d4: 200000d5 .word 0x200000d5
|
|
|
|
080071d8 <USBD_HID_DeInit>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
80071d8: b580 push {r7, lr}
|
|
80071da: b082 sub sp, #8
|
|
80071dc: af00 add r7, sp, #0
|
|
80071de: 6078 str r0, [r7, #4]
|
|
80071e0: 460b mov r3, r1
|
|
80071e2: 70fb strb r3, [r7, #3]
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Close HID EPs */
|
|
(void)USBD_LL_CloseEP(pdev, HIDInEpAdd);
|
|
80071e4: 4b1f ldr r3, [pc, #124] @ (8007264 <USBD_HID_DeInit+0x8c>)
|
|
80071e6: 781b ldrb r3, [r3, #0]
|
|
80071e8: 4619 mov r1, r3
|
|
80071ea: 6878 ldr r0, [r7, #4]
|
|
80071ec: f002 f855 bl 800929a <USBD_LL_CloseEP>
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U;
|
|
80071f0: 4b1c ldr r3, [pc, #112] @ (8007264 <USBD_HID_DeInit+0x8c>)
|
|
80071f2: 781b ldrb r3, [r3, #0]
|
|
80071f4: f003 020f and.w r2, r3, #15
|
|
80071f8: 6879 ldr r1, [r7, #4]
|
|
80071fa: 4613 mov r3, r2
|
|
80071fc: 009b lsls r3, r3, #2
|
|
80071fe: 4413 add r3, r2
|
|
8007200: 009b lsls r3, r3, #2
|
|
8007202: 440b add r3, r1
|
|
8007204: 3323 adds r3, #35 @ 0x23
|
|
8007206: 2200 movs r2, #0
|
|
8007208: 701a strb r2, [r3, #0]
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U;
|
|
800720a: 4b16 ldr r3, [pc, #88] @ (8007264 <USBD_HID_DeInit+0x8c>)
|
|
800720c: 781b ldrb r3, [r3, #0]
|
|
800720e: f003 020f and.w r2, r3, #15
|
|
8007212: 6879 ldr r1, [r7, #4]
|
|
8007214: 4613 mov r3, r2
|
|
8007216: 009b lsls r3, r3, #2
|
|
8007218: 4413 add r3, r2
|
|
800721a: 009b lsls r3, r3, #2
|
|
800721c: 440b add r3, r1
|
|
800721e: 331c adds r3, #28
|
|
8007220: 2200 movs r2, #0
|
|
8007222: 601a str r2, [r3, #0]
|
|
|
|
/* Free allocated memory */
|
|
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
|
|
8007224: 687b ldr r3, [r7, #4]
|
|
8007226: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800722a: 687b ldr r3, [r7, #4]
|
|
800722c: 32b0 adds r2, #176 @ 0xb0
|
|
800722e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007232: 2b00 cmp r3, #0
|
|
8007234: d011 beq.n 800725a <USBD_HID_DeInit+0x82>
|
|
{
|
|
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
|
|
8007236: 687b ldr r3, [r7, #4]
|
|
8007238: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800723c: 687b ldr r3, [r7, #4]
|
|
800723e: 32b0 adds r2, #176 @ 0xb0
|
|
8007240: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007244: 4618 mov r0, r3
|
|
8007246: f002 f96f bl 8009528 <USBD_static_free>
|
|
pdev->pClassDataCmsit[pdev->classId] = NULL;
|
|
800724a: 687b ldr r3, [r7, #4]
|
|
800724c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007250: 687b ldr r3, [r7, #4]
|
|
8007252: 32b0 adds r2, #176 @ 0xb0
|
|
8007254: 2100 movs r1, #0
|
|
8007256: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
800725a: 2300 movs r3, #0
|
|
}
|
|
800725c: 4618 mov r0, r3
|
|
800725e: 3708 adds r7, #8
|
|
8007260: 46bd mov sp, r7
|
|
8007262: bd80 pop {r7, pc}
|
|
8007264: 200000d5 .word 0x200000d5
|
|
|
|
08007268 <USBD_HID_Setup>:
|
|
* @param pdev: instance
|
|
* @param req: usb requests
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007268: b580 push {r7, lr}
|
|
800726a: b086 sub sp, #24
|
|
800726c: af00 add r7, sp, #0
|
|
800726e: 6078 str r0, [r7, #4]
|
|
8007270: 6039 str r1, [r7, #0]
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
8007272: 687b ldr r3, [r7, #4]
|
|
8007274: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007278: 687b ldr r3, [r7, #4]
|
|
800727a: 32b0 adds r2, #176 @ 0xb0
|
|
800727c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007280: 60fb str r3, [r7, #12]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007282: 2300 movs r3, #0
|
|
8007284: 75fb strb r3, [r7, #23]
|
|
uint16_t len;
|
|
uint8_t *pbuf;
|
|
uint16_t status_info = 0U;
|
|
8007286: 2300 movs r3, #0
|
|
8007288: 817b strh r3, [r7, #10]
|
|
|
|
if (hhid == NULL)
|
|
800728a: 68fb ldr r3, [r7, #12]
|
|
800728c: 2b00 cmp r3, #0
|
|
800728e: d101 bne.n 8007294 <USBD_HID_Setup+0x2c>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
8007290: 2303 movs r3, #3
|
|
8007292: e0e8 b.n 8007466 <USBD_HID_Setup+0x1fe>
|
|
}
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8007294: 683b ldr r3, [r7, #0]
|
|
8007296: 781b ldrb r3, [r3, #0]
|
|
8007298: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
800729c: 2b00 cmp r3, #0
|
|
800729e: d046 beq.n 800732e <USBD_HID_Setup+0xc6>
|
|
80072a0: 2b20 cmp r3, #32
|
|
80072a2: f040 80d8 bne.w 8007456 <USBD_HID_Setup+0x1ee>
|
|
{
|
|
case USB_REQ_TYPE_CLASS :
|
|
switch (req->bRequest)
|
|
80072a6: 683b ldr r3, [r7, #0]
|
|
80072a8: 785b ldrb r3, [r3, #1]
|
|
80072aa: 3b02 subs r3, #2
|
|
80072ac: 2b09 cmp r3, #9
|
|
80072ae: d836 bhi.n 800731e <USBD_HID_Setup+0xb6>
|
|
80072b0: a201 add r2, pc, #4 @ (adr r2, 80072b8 <USBD_HID_Setup+0x50>)
|
|
80072b2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80072b6: bf00 nop
|
|
80072b8: 0800730f .word 0x0800730f
|
|
80072bc: 080072ef .word 0x080072ef
|
|
80072c0: 0800731f .word 0x0800731f
|
|
80072c4: 0800731f .word 0x0800731f
|
|
80072c8: 0800731f .word 0x0800731f
|
|
80072cc: 0800731f .word 0x0800731f
|
|
80072d0: 0800731f .word 0x0800731f
|
|
80072d4: 0800731f .word 0x0800731f
|
|
80072d8: 080072fd .word 0x080072fd
|
|
80072dc: 080072e1 .word 0x080072e1
|
|
{
|
|
case USBD_HID_REQ_SET_PROTOCOL:
|
|
hhid->Protocol = (uint8_t)(req->wValue);
|
|
80072e0: 683b ldr r3, [r7, #0]
|
|
80072e2: 885b ldrh r3, [r3, #2]
|
|
80072e4: b2db uxtb r3, r3
|
|
80072e6: 461a mov r2, r3
|
|
80072e8: 68fb ldr r3, [r7, #12]
|
|
80072ea: 601a str r2, [r3, #0]
|
|
break;
|
|
80072ec: e01e b.n 800732c <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_GET_PROTOCOL:
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U);
|
|
80072ee: 68fb ldr r3, [r7, #12]
|
|
80072f0: 2201 movs r2, #1
|
|
80072f2: 4619 mov r1, r3
|
|
80072f4: 6878 ldr r0, [r7, #4]
|
|
80072f6: f001 fc39 bl 8008b6c <USBD_CtlSendData>
|
|
break;
|
|
80072fa: e017 b.n 800732c <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_SET_IDLE:
|
|
hhid->IdleState = (uint8_t)(req->wValue >> 8);
|
|
80072fc: 683b ldr r3, [r7, #0]
|
|
80072fe: 885b ldrh r3, [r3, #2]
|
|
8007300: 0a1b lsrs r3, r3, #8
|
|
8007302: b29b uxth r3, r3
|
|
8007304: b2db uxtb r3, r3
|
|
8007306: 461a mov r2, r3
|
|
8007308: 68fb ldr r3, [r7, #12]
|
|
800730a: 605a str r2, [r3, #4]
|
|
break;
|
|
800730c: e00e b.n 800732c <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_GET_IDLE:
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U);
|
|
800730e: 68fb ldr r3, [r7, #12]
|
|
8007310: 3304 adds r3, #4
|
|
8007312: 2201 movs r2, #1
|
|
8007314: 4619 mov r1, r3
|
|
8007316: 6878 ldr r0, [r7, #4]
|
|
8007318: f001 fc28 bl 8008b6c <USBD_CtlSendData>
|
|
break;
|
|
800731c: e006 b.n 800732c <USBD_HID_Setup+0xc4>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800731e: 6839 ldr r1, [r7, #0]
|
|
8007320: 6878 ldr r0, [r7, #4]
|
|
8007322: f001 fba6 bl 8008a72 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8007326: 2303 movs r3, #3
|
|
8007328: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800732a: bf00 nop
|
|
}
|
|
break;
|
|
800732c: e09a b.n 8007464 <USBD_HID_Setup+0x1fc>
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
800732e: 683b ldr r3, [r7, #0]
|
|
8007330: 785b ldrb r3, [r3, #1]
|
|
8007332: 2b0b cmp r3, #11
|
|
8007334: f200 8086 bhi.w 8007444 <USBD_HID_Setup+0x1dc>
|
|
8007338: a201 add r2, pc, #4 @ (adr r2, 8007340 <USBD_HID_Setup+0xd8>)
|
|
800733a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800733e: bf00 nop
|
|
8007340: 08007371 .word 0x08007371
|
|
8007344: 08007453 .word 0x08007453
|
|
8007348: 08007445 .word 0x08007445
|
|
800734c: 08007445 .word 0x08007445
|
|
8007350: 08007445 .word 0x08007445
|
|
8007354: 08007445 .word 0x08007445
|
|
8007358: 0800739b .word 0x0800739b
|
|
800735c: 08007445 .word 0x08007445
|
|
8007360: 08007445 .word 0x08007445
|
|
8007364: 08007445 .word 0x08007445
|
|
8007368: 080073f3 .word 0x080073f3
|
|
800736c: 0800741d .word 0x0800741d
|
|
{
|
|
case USB_REQ_GET_STATUS:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007370: 687b ldr r3, [r7, #4]
|
|
8007372: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007376: b2db uxtb r3, r3
|
|
8007378: 2b03 cmp r3, #3
|
|
800737a: d107 bne.n 800738c <USBD_HID_Setup+0x124>
|
|
{
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
|
|
800737c: f107 030a add.w r3, r7, #10
|
|
8007380: 2202 movs r2, #2
|
|
8007382: 4619 mov r1, r3
|
|
8007384: 6878 ldr r0, [r7, #4]
|
|
8007386: f001 fbf1 bl 8008b6c <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
800738a: e063 b.n 8007454 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
800738c: 6839 ldr r1, [r7, #0]
|
|
800738e: 6878 ldr r0, [r7, #4]
|
|
8007390: f001 fb6f bl 8008a72 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8007394: 2303 movs r3, #3
|
|
8007396: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007398: e05c b.n 8007454 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
if ((req->wValue >> 8) == HID_REPORT_DESC)
|
|
800739a: 683b ldr r3, [r7, #0]
|
|
800739c: 885b ldrh r3, [r3, #2]
|
|
800739e: 0a1b lsrs r3, r3, #8
|
|
80073a0: b29b uxth r3, r3
|
|
80073a2: 2b22 cmp r3, #34 @ 0x22
|
|
80073a4: d108 bne.n 80073b8 <USBD_HID_Setup+0x150>
|
|
{
|
|
len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength);
|
|
80073a6: 683b ldr r3, [r7, #0]
|
|
80073a8: 88db ldrh r3, [r3, #6]
|
|
80073aa: 2b2d cmp r3, #45 @ 0x2d
|
|
80073ac: bf28 it cs
|
|
80073ae: 232d movcs r3, #45 @ 0x2d
|
|
80073b0: 82bb strh r3, [r7, #20]
|
|
pbuf = HID_MOUSE_ReportDesc;
|
|
80073b2: 4b2f ldr r3, [pc, #188] @ (8007470 <USBD_HID_Setup+0x208>)
|
|
80073b4: 613b str r3, [r7, #16]
|
|
80073b6: e015 b.n 80073e4 <USBD_HID_Setup+0x17c>
|
|
}
|
|
else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE)
|
|
80073b8: 683b ldr r3, [r7, #0]
|
|
80073ba: 885b ldrh r3, [r3, #2]
|
|
80073bc: 0a1b lsrs r3, r3, #8
|
|
80073be: b29b uxth r3, r3
|
|
80073c0: 2b21 cmp r3, #33 @ 0x21
|
|
80073c2: d108 bne.n 80073d6 <USBD_HID_Setup+0x16e>
|
|
{
|
|
pbuf = USBD_HID_Desc;
|
|
80073c4: 4b2b ldr r3, [pc, #172] @ (8007474 <USBD_HID_Setup+0x20c>)
|
|
80073c6: 613b str r3, [r7, #16]
|
|
len = MIN(USB_HID_DESC_SIZ, req->wLength);
|
|
80073c8: 683b ldr r3, [r7, #0]
|
|
80073ca: 88db ldrh r3, [r3, #6]
|
|
80073cc: 2b09 cmp r3, #9
|
|
80073ce: bf28 it cs
|
|
80073d0: 2309 movcs r3, #9
|
|
80073d2: 82bb strh r3, [r7, #20]
|
|
80073d4: e006 b.n 80073e4 <USBD_HID_Setup+0x17c>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80073d6: 6839 ldr r1, [r7, #0]
|
|
80073d8: 6878 ldr r0, [r7, #4]
|
|
80073da: f001 fb4a bl 8008a72 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
80073de: 2303 movs r3, #3
|
|
80073e0: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80073e2: e037 b.n 8007454 <USBD_HID_Setup+0x1ec>
|
|
}
|
|
(void)USBD_CtlSendData(pdev, pbuf, len);
|
|
80073e4: 8abb ldrh r3, [r7, #20]
|
|
80073e6: 461a mov r2, r3
|
|
80073e8: 6939 ldr r1, [r7, #16]
|
|
80073ea: 6878 ldr r0, [r7, #4]
|
|
80073ec: f001 fbbe bl 8008b6c <USBD_CtlSendData>
|
|
break;
|
|
80073f0: e030 b.n 8007454 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_GET_INTERFACE :
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80073f2: 687b ldr r3, [r7, #4]
|
|
80073f4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80073f8: b2db uxtb r3, r3
|
|
80073fa: 2b03 cmp r3, #3
|
|
80073fc: d107 bne.n 800740e <USBD_HID_Setup+0x1a6>
|
|
{
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U);
|
|
80073fe: 68fb ldr r3, [r7, #12]
|
|
8007400: 3308 adds r3, #8
|
|
8007402: 2201 movs r2, #1
|
|
8007404: 4619 mov r1, r3
|
|
8007406: 6878 ldr r0, [r7, #4]
|
|
8007408: f001 fbb0 bl 8008b6c <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
800740c: e022 b.n 8007454 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
800740e: 6839 ldr r1, [r7, #0]
|
|
8007410: 6878 ldr r0, [r7, #4]
|
|
8007412: f001 fb2e bl 8008a72 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8007416: 2303 movs r3, #3
|
|
8007418: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800741a: e01b b.n 8007454 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_SET_INTERFACE:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
800741c: 687b ldr r3, [r7, #4]
|
|
800741e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007422: b2db uxtb r3, r3
|
|
8007424: 2b03 cmp r3, #3
|
|
8007426: d106 bne.n 8007436 <USBD_HID_Setup+0x1ce>
|
|
{
|
|
hhid->AltSetting = (uint8_t)(req->wValue);
|
|
8007428: 683b ldr r3, [r7, #0]
|
|
800742a: 885b ldrh r3, [r3, #2]
|
|
800742c: b2db uxtb r3, r3
|
|
800742e: 461a mov r2, r3
|
|
8007430: 68fb ldr r3, [r7, #12]
|
|
8007432: 609a str r2, [r3, #8]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
8007434: e00e b.n 8007454 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
8007436: 6839 ldr r1, [r7, #0]
|
|
8007438: 6878 ldr r0, [r7, #4]
|
|
800743a: f001 fb1a bl 8008a72 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
800743e: 2303 movs r3, #3
|
|
8007440: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007442: e007 b.n 8007454 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
break;
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007444: 6839 ldr r1, [r7, #0]
|
|
8007446: 6878 ldr r0, [r7, #4]
|
|
8007448: f001 fb13 bl 8008a72 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
800744c: 2303 movs r3, #3
|
|
800744e: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007450: e000 b.n 8007454 <USBD_HID_Setup+0x1ec>
|
|
break;
|
|
8007452: bf00 nop
|
|
}
|
|
break;
|
|
8007454: e006 b.n 8007464 <USBD_HID_Setup+0x1fc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007456: 6839 ldr r1, [r7, #0]
|
|
8007458: 6878 ldr r0, [r7, #4]
|
|
800745a: f001 fb0a bl 8008a72 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
800745e: 2303 movs r3, #3
|
|
8007460: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007462: bf00 nop
|
|
}
|
|
|
|
return (uint8_t)ret;
|
|
8007464: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8007466: 4618 mov r0, r3
|
|
8007468: 3718 adds r7, #24
|
|
800746a: 46bd mov sp, r7
|
|
800746c: bd80 pop {r7, pc}
|
|
800746e: bf00 nop
|
|
8007470: 200000a8 .word 0x200000a8
|
|
8007474: 20000090 .word 0x20000090
|
|
|
|
08007478 <USBD_HID_SendReport>:
|
|
uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId)
|
|
{
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId];
|
|
#else
|
|
uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
|
|
{
|
|
8007478: b580 push {r7, lr}
|
|
800747a: b086 sub sp, #24
|
|
800747c: af00 add r7, sp, #0
|
|
800747e: 60f8 str r0, [r7, #12]
|
|
8007480: 60b9 str r1, [r7, #8]
|
|
8007482: 4613 mov r3, r2
|
|
8007484: 80fb strh r3, [r7, #6]
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
8007486: 68fb ldr r3, [r7, #12]
|
|
8007488: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800748c: 68fb ldr r3, [r7, #12]
|
|
800748e: 32b0 adds r2, #176 @ 0xb0
|
|
8007490: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007494: 617b str r3, [r7, #20]
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (hhid == NULL)
|
|
8007496: 697b ldr r3, [r7, #20]
|
|
8007498: 2b00 cmp r3, #0
|
|
800749a: d101 bne.n 80074a0 <USBD_HID_SendReport+0x28>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
800749c: 2303 movs r3, #3
|
|
800749e: e014 b.n 80074ca <USBD_HID_SendReport+0x52>
|
|
#ifdef USE_USBD_COMPOSITE
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80074a0: 68fb ldr r3, [r7, #12]
|
|
80074a2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80074a6: b2db uxtb r3, r3
|
|
80074a8: 2b03 cmp r3, #3
|
|
80074aa: d10d bne.n 80074c8 <USBD_HID_SendReport+0x50>
|
|
{
|
|
if (hhid->state == USBD_HID_IDLE)
|
|
80074ac: 697b ldr r3, [r7, #20]
|
|
80074ae: 7b1b ldrb r3, [r3, #12]
|
|
80074b0: 2b00 cmp r3, #0
|
|
80074b2: d109 bne.n 80074c8 <USBD_HID_SendReport+0x50>
|
|
{
|
|
hhid->state = USBD_HID_BUSY;
|
|
80074b4: 697b ldr r3, [r7, #20]
|
|
80074b6: 2201 movs r2, #1
|
|
80074b8: 731a strb r2, [r3, #12]
|
|
(void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len);
|
|
80074ba: 4b06 ldr r3, [pc, #24] @ (80074d4 <USBD_HID_SendReport+0x5c>)
|
|
80074bc: 7819 ldrb r1, [r3, #0]
|
|
80074be: 88fb ldrh r3, [r7, #6]
|
|
80074c0: 68ba ldr r2, [r7, #8]
|
|
80074c2: 68f8 ldr r0, [r7, #12]
|
|
80074c4: f001 ff91 bl 80093ea <USBD_LL_Transmit>
|
|
}
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
80074c8: 2300 movs r3, #0
|
|
}
|
|
80074ca: 4618 mov r0, r3
|
|
80074cc: 3718 adds r7, #24
|
|
80074ce: 46bd mov sp, r7
|
|
80074d0: bd80 pop {r7, pc}
|
|
80074d2: bf00 nop
|
|
80074d4: 200000d5 .word 0x200000d5
|
|
|
|
080074d8 <USBD_HID_GetPollingInterval>:
|
|
* return polling interval from endpoint descriptor
|
|
* @param pdev: device instance
|
|
* @retval polling interval
|
|
*/
|
|
uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80074d8: b480 push {r7}
|
|
80074da: b085 sub sp, #20
|
|
80074dc: af00 add r7, sp, #0
|
|
80074de: 6078 str r0, [r7, #4]
|
|
uint32_t polling_interval;
|
|
|
|
/* HIGH-speed endpoints */
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
80074e0: 687b ldr r3, [r7, #4]
|
|
80074e2: 7c1b ldrb r3, [r3, #16]
|
|
80074e4: 2b00 cmp r3, #0
|
|
80074e6: d102 bne.n 80074ee <USBD_HID_GetPollingInterval+0x16>
|
|
{
|
|
/* Sets the data transfer polling interval for high speed transfers.
|
|
Values between 1..16 are allowed. Values correspond to interval
|
|
of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */
|
|
polling_interval = (((1U << (HID_HS_BINTERVAL - 1U))) / 8U);
|
|
80074e8: 2308 movs r3, #8
|
|
80074ea: 60fb str r3, [r7, #12]
|
|
80074ec: e001 b.n 80074f2 <USBD_HID_GetPollingInterval+0x1a>
|
|
}
|
|
else /* LOW and FULL-speed endpoints */
|
|
{
|
|
/* Sets the data transfer polling interval for low and full
|
|
speed transfers */
|
|
polling_interval = HID_FS_BINTERVAL;
|
|
80074ee: 230a movs r3, #10
|
|
80074f0: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return ((uint32_t)(polling_interval));
|
|
80074f2: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80074f4: 4618 mov r0, r3
|
|
80074f6: 3714 adds r7, #20
|
|
80074f8: 46bd mov sp, r7
|
|
80074fa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80074fe: 4770 bx lr
|
|
|
|
08007500 <USBD_HID_GetFSCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length)
|
|
{
|
|
8007500: b580 push {r7, lr}
|
|
8007502: b084 sub sp, #16
|
|
8007504: af00 add r7, sp, #0
|
|
8007506: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
8007508: 2181 movs r1, #129 @ 0x81
|
|
800750a: 4809 ldr r0, [pc, #36] @ (8007530 <USBD_HID_GetFSCfgDesc+0x30>)
|
|
800750c: f000 fc4e bl 8007dac <USBD_GetEpDesc>
|
|
8007510: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
8007512: 68fb ldr r3, [r7, #12]
|
|
8007514: 2b00 cmp r3, #0
|
|
8007516: d002 beq.n 800751e <USBD_HID_GetFSCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_FS_BINTERVAL;
|
|
8007518: 68fb ldr r3, [r7, #12]
|
|
800751a: 220a movs r2, #10
|
|
800751c: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
800751e: 687b ldr r3, [r7, #4]
|
|
8007520: 2222 movs r2, #34 @ 0x22
|
|
8007522: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
8007524: 4b02 ldr r3, [pc, #8] @ (8007530 <USBD_HID_GetFSCfgDesc+0x30>)
|
|
}
|
|
8007526: 4618 mov r0, r3
|
|
8007528: 3710 adds r7, #16
|
|
800752a: 46bd mov sp, r7
|
|
800752c: bd80 pop {r7, pc}
|
|
800752e: bf00 nop
|
|
8007530: 2000006c .word 0x2000006c
|
|
|
|
08007534 <USBD_HID_GetHSCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length)
|
|
{
|
|
8007534: b580 push {r7, lr}
|
|
8007536: b084 sub sp, #16
|
|
8007538: af00 add r7, sp, #0
|
|
800753a: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
800753c: 2181 movs r1, #129 @ 0x81
|
|
800753e: 4809 ldr r0, [pc, #36] @ (8007564 <USBD_HID_GetHSCfgDesc+0x30>)
|
|
8007540: f000 fc34 bl 8007dac <USBD_GetEpDesc>
|
|
8007544: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
8007546: 68fb ldr r3, [r7, #12]
|
|
8007548: 2b00 cmp r3, #0
|
|
800754a: d002 beq.n 8007552 <USBD_HID_GetHSCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_HS_BINTERVAL;
|
|
800754c: 68fb ldr r3, [r7, #12]
|
|
800754e: 2207 movs r2, #7
|
|
8007550: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
8007552: 687b ldr r3, [r7, #4]
|
|
8007554: 2222 movs r2, #34 @ 0x22
|
|
8007556: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
8007558: 4b02 ldr r3, [pc, #8] @ (8007564 <USBD_HID_GetHSCfgDesc+0x30>)
|
|
}
|
|
800755a: 4618 mov r0, r3
|
|
800755c: 3710 adds r7, #16
|
|
800755e: 46bd mov sp, r7
|
|
8007560: bd80 pop {r7, pc}
|
|
8007562: bf00 nop
|
|
8007564: 2000006c .word 0x2000006c
|
|
|
|
08007568 <USBD_HID_GetOtherSpeedCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length)
|
|
{
|
|
8007568: b580 push {r7, lr}
|
|
800756a: b084 sub sp, #16
|
|
800756c: af00 add r7, sp, #0
|
|
800756e: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
8007570: 2181 movs r1, #129 @ 0x81
|
|
8007572: 4809 ldr r0, [pc, #36] @ (8007598 <USBD_HID_GetOtherSpeedCfgDesc+0x30>)
|
|
8007574: f000 fc1a bl 8007dac <USBD_GetEpDesc>
|
|
8007578: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
800757a: 68fb ldr r3, [r7, #12]
|
|
800757c: 2b00 cmp r3, #0
|
|
800757e: d002 beq.n 8007586 <USBD_HID_GetOtherSpeedCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_FS_BINTERVAL;
|
|
8007580: 68fb ldr r3, [r7, #12]
|
|
8007582: 220a movs r2, #10
|
|
8007584: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
8007586: 687b ldr r3, [r7, #4]
|
|
8007588: 2222 movs r2, #34 @ 0x22
|
|
800758a: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
800758c: 4b02 ldr r3, [pc, #8] @ (8007598 <USBD_HID_GetOtherSpeedCfgDesc+0x30>)
|
|
}
|
|
800758e: 4618 mov r0, r3
|
|
8007590: 3710 adds r7, #16
|
|
8007592: 46bd mov sp, r7
|
|
8007594: bd80 pop {r7, pc}
|
|
8007596: bf00 nop
|
|
8007598: 2000006c .word 0x2000006c
|
|
|
|
0800759c <USBD_HID_DataIn>:
|
|
* @param pdev: device instance
|
|
* @param epnum: endpoint index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
|
|
{
|
|
800759c: b480 push {r7}
|
|
800759e: b083 sub sp, #12
|
|
80075a0: af00 add r7, sp, #0
|
|
80075a2: 6078 str r0, [r7, #4]
|
|
80075a4: 460b mov r3, r1
|
|
80075a6: 70fb strb r3, [r7, #3]
|
|
UNUSED(epnum);
|
|
/* Ensure that the FIFO is empty before a new transfer, this condition could
|
|
be caused by a new transfer before the end of the previous transfer */
|
|
((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE;
|
|
80075a8: 687b ldr r3, [r7, #4]
|
|
80075aa: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80075ae: 687b ldr r3, [r7, #4]
|
|
80075b0: 32b0 adds r2, #176 @ 0xb0
|
|
80075b2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80075b6: 2200 movs r2, #0
|
|
80075b8: 731a strb r2, [r3, #12]
|
|
|
|
return (uint8_t)USBD_OK;
|
|
80075ba: 2300 movs r3, #0
|
|
}
|
|
80075bc: 4618 mov r0, r3
|
|
80075be: 370c adds r7, #12
|
|
80075c0: 46bd mov sp, r7
|
|
80075c2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80075c6: 4770 bx lr
|
|
|
|
080075c8 <USBD_HID_GetDeviceQualifierDesc>:
|
|
* return Device Qualifier descriptor
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length)
|
|
{
|
|
80075c8: b480 push {r7}
|
|
80075ca: b083 sub sp, #12
|
|
80075cc: af00 add r7, sp, #0
|
|
80075ce: 6078 str r0, [r7, #4]
|
|
*length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc);
|
|
80075d0: 687b ldr r3, [r7, #4]
|
|
80075d2: 220a movs r2, #10
|
|
80075d4: 801a strh r2, [r3, #0]
|
|
|
|
return USBD_HID_DeviceQualifierDesc;
|
|
80075d6: 4b03 ldr r3, [pc, #12] @ (80075e4 <USBD_HID_GetDeviceQualifierDesc+0x1c>)
|
|
}
|
|
80075d8: 4618 mov r0, r3
|
|
80075da: 370c adds r7, #12
|
|
80075dc: 46bd mov sp, r7
|
|
80075de: f85d 7b04 ldr.w r7, [sp], #4
|
|
80075e2: 4770 bx lr
|
|
80075e4: 2000009c .word 0x2000009c
|
|
|
|
080075e8 <USBD_Init>:
|
|
* @param id: Low level core index
|
|
* @retval status: USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
|
|
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
|
|
{
|
|
80075e8: b580 push {r7, lr}
|
|
80075ea: b086 sub sp, #24
|
|
80075ec: af00 add r7, sp, #0
|
|
80075ee: 60f8 str r0, [r7, #12]
|
|
80075f0: 60b9 str r1, [r7, #8]
|
|
80075f2: 4613 mov r3, r2
|
|
80075f4: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef ret;
|
|
|
|
/* Check whether the USB Host handle is valid */
|
|
if (pdev == NULL)
|
|
80075f6: 68fb ldr r3, [r7, #12]
|
|
80075f8: 2b00 cmp r3, #0
|
|
80075fa: d101 bne.n 8007600 <USBD_Init+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Device handle");
|
|
#endif /* (USBD_DEBUG_LEVEL > 1U) */
|
|
return USBD_FAIL;
|
|
80075fc: 2303 movs r3, #3
|
|
80075fe: e01f b.n 8007640 <USBD_Init+0x58>
|
|
pdev->NumClasses = 0;
|
|
pdev->classId = 0;
|
|
}
|
|
#else
|
|
/* Unlink previous class*/
|
|
pdev->pClass[0] = NULL;
|
|
8007600: 68fb ldr r3, [r7, #12]
|
|
8007602: 2200 movs r2, #0
|
|
8007604: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
pdev->pUserData[0] = NULL;
|
|
8007608: 68fb ldr r3, [r7, #12]
|
|
800760a: 2200 movs r2, #0
|
|
800760c: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
pdev->pConfDesc = NULL;
|
|
8007610: 68fb ldr r3, [r7, #12]
|
|
8007612: 2200 movs r2, #0
|
|
8007614: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
|
|
/* Assign USBD Descriptors */
|
|
if (pdesc != NULL)
|
|
8007618: 68bb ldr r3, [r7, #8]
|
|
800761a: 2b00 cmp r3, #0
|
|
800761c: d003 beq.n 8007626 <USBD_Init+0x3e>
|
|
{
|
|
pdev->pDesc = pdesc;
|
|
800761e: 68fb ldr r3, [r7, #12]
|
|
8007620: 68ba ldr r2, [r7, #8]
|
|
8007622: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
|
|
}
|
|
|
|
/* Set Device initial State */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8007626: 68fb ldr r3, [r7, #12]
|
|
8007628: 2201 movs r2, #1
|
|
800762a: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->id = id;
|
|
800762e: 68fb ldr r3, [r7, #12]
|
|
8007630: 79fa ldrb r2, [r7, #7]
|
|
8007632: 701a strb r2, [r3, #0]
|
|
|
|
/* Initialize low level driver */
|
|
ret = USBD_LL_Init(pdev);
|
|
8007634: 68f8 ldr r0, [r7, #12]
|
|
8007636: f001 fda3 bl 8009180 <USBD_LL_Init>
|
|
800763a: 4603 mov r3, r0
|
|
800763c: 75fb strb r3, [r7, #23]
|
|
|
|
return ret;
|
|
800763e: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8007640: 4618 mov r0, r3
|
|
8007642: 3718 adds r7, #24
|
|
8007644: 46bd mov sp, r7
|
|
8007646: bd80 pop {r7, pc}
|
|
|
|
08007648 <USBD_RegisterClass>:
|
|
* @param pdev: Device Handle
|
|
* @param pclass: Class handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
|
|
{
|
|
8007648: b580 push {r7, lr}
|
|
800764a: b084 sub sp, #16
|
|
800764c: af00 add r7, sp, #0
|
|
800764e: 6078 str r0, [r7, #4]
|
|
8007650: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
8007652: 2300 movs r3, #0
|
|
8007654: 81fb strh r3, [r7, #14]
|
|
|
|
if (pclass == NULL)
|
|
8007656: 683b ldr r3, [r7, #0]
|
|
8007658: 2b00 cmp r3, #0
|
|
800765a: d101 bne.n 8007660 <USBD_RegisterClass+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Class handle");
|
|
#endif /* (USBD_DEBUG_LEVEL > 1U) */
|
|
return USBD_FAIL;
|
|
800765c: 2303 movs r3, #3
|
|
800765e: e025 b.n 80076ac <USBD_RegisterClass+0x64>
|
|
}
|
|
|
|
/* link the class to the USB Device handle */
|
|
pdev->pClass[0] = pclass;
|
|
8007660: 687b ldr r3, [r7, #4]
|
|
8007662: 683a ldr r2, [r7, #0]
|
|
8007664: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL)
|
|
{
|
|
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len);
|
|
}
|
|
#else /* Default USE_USB_FS */
|
|
if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL)
|
|
8007668: 687b ldr r3, [r7, #4]
|
|
800766a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800766e: 687b ldr r3, [r7, #4]
|
|
8007670: 32ae adds r2, #174 @ 0xae
|
|
8007672: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007676: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007678: 2b00 cmp r3, #0
|
|
800767a: d00f beq.n 800769c <USBD_RegisterClass+0x54>
|
|
{
|
|
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len);
|
|
800767c: 687b ldr r3, [r7, #4]
|
|
800767e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007682: 687b ldr r3, [r7, #4]
|
|
8007684: 32ae adds r2, #174 @ 0xae
|
|
8007686: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800768a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800768c: f107 020e add.w r2, r7, #14
|
|
8007690: 4610 mov r0, r2
|
|
8007692: 4798 blx r3
|
|
8007694: 4602 mov r2, r0
|
|
8007696: 687b ldr r3, [r7, #4]
|
|
8007698: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
}
|
|
#endif /* USE_USB_FS */
|
|
|
|
/* Increment the NumClasses */
|
|
pdev->NumClasses++;
|
|
800769c: 687b ldr r3, [r7, #4]
|
|
800769e: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
80076a2: 1c5a adds r2, r3, #1
|
|
80076a4: 687b ldr r3, [r7, #4]
|
|
80076a6: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8
|
|
|
|
return USBD_OK;
|
|
80076aa: 2300 movs r3, #0
|
|
}
|
|
80076ac: 4618 mov r0, r3
|
|
80076ae: 3710 adds r7, #16
|
|
80076b0: 46bd mov sp, r7
|
|
80076b2: bd80 pop {r7, pc}
|
|
|
|
080076b4 <USBD_Start>:
|
|
* Start the USB Device Core.
|
|
* @param pdev: Device Handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80076b4: b580 push {r7, lr}
|
|
80076b6: b082 sub sp, #8
|
|
80076b8: af00 add r7, sp, #0
|
|
80076ba: 6078 str r0, [r7, #4]
|
|
#ifdef USE_USBD_COMPOSITE
|
|
pdev->classId = 0U;
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Start the low level driver */
|
|
return USBD_LL_Start(pdev);
|
|
80076bc: 6878 ldr r0, [r7, #4]
|
|
80076be: f001 fdab bl 8009218 <USBD_LL_Start>
|
|
80076c2: 4603 mov r3, r0
|
|
}
|
|
80076c4: 4618 mov r0, r3
|
|
80076c6: 3708 adds r7, #8
|
|
80076c8: 46bd mov sp, r7
|
|
80076ca: bd80 pop {r7, pc}
|
|
|
|
080076cc <USBD_RunTestMode>:
|
|
* Launch test mode process
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80076cc: b480 push {r7}
|
|
80076ce: b083 sub sp, #12
|
|
80076d0: af00 add r7, sp, #0
|
|
80076d2: 6078 str r0, [r7, #4]
|
|
return ret;
|
|
#else
|
|
/* Prevent unused argument compilation warning */
|
|
UNUSED(pdev);
|
|
|
|
return USBD_OK;
|
|
80076d4: 2300 movs r3, #0
|
|
#endif /* USBD_HS_TESTMODE_ENABLE */
|
|
}
|
|
80076d6: 4618 mov r0, r3
|
|
80076d8: 370c adds r7, #12
|
|
80076da: 46bd mov sp, r7
|
|
80076dc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80076e0: 4770 bx lr
|
|
|
|
080076e2 <USBD_SetClassConfig>:
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
|
|
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
80076e2: b580 push {r7, lr}
|
|
80076e4: b084 sub sp, #16
|
|
80076e6: af00 add r7, sp, #0
|
|
80076e8: 6078 str r0, [r7, #4]
|
|
80076ea: 460b mov r3, r1
|
|
80076ec: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80076ee: 2300 movs r3, #0
|
|
80076f0: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
80076f2: 687b ldr r3, [r7, #4]
|
|
80076f4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80076f8: 2b00 cmp r3, #0
|
|
80076fa: d009 beq.n 8007710 <USBD_SetClassConfig+0x2e>
|
|
{
|
|
/* Set configuration and Start the Class */
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx);
|
|
80076fc: 687b ldr r3, [r7, #4]
|
|
80076fe: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007702: 681b ldr r3, [r3, #0]
|
|
8007704: 78fa ldrb r2, [r7, #3]
|
|
8007706: 4611 mov r1, r2
|
|
8007708: 6878 ldr r0, [r7, #4]
|
|
800770a: 4798 blx r3
|
|
800770c: 4603 mov r3, r0
|
|
800770e: 73fb strb r3, [r7, #15]
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8007710: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007712: 4618 mov r0, r3
|
|
8007714: 3710 adds r7, #16
|
|
8007716: 46bd mov sp, r7
|
|
8007718: bd80 pop {r7, pc}
|
|
|
|
0800771a <USBD_ClrClassConfig>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
800771a: b580 push {r7, lr}
|
|
800771c: b084 sub sp, #16
|
|
800771e: af00 add r7, sp, #0
|
|
8007720: 6078 str r0, [r7, #4]
|
|
8007722: 460b mov r3, r1
|
|
8007724: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007726: 2300 movs r3, #0
|
|
8007728: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
/* Clear configuration and De-initialize the Class process */
|
|
if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U)
|
|
800772a: 687b ldr r3, [r7, #4]
|
|
800772c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007730: 685b ldr r3, [r3, #4]
|
|
8007732: 78fa ldrb r2, [r7, #3]
|
|
8007734: 4611 mov r1, r2
|
|
8007736: 6878 ldr r0, [r7, #4]
|
|
8007738: 4798 blx r3
|
|
800773a: 4603 mov r3, r0
|
|
800773c: 2b00 cmp r3, #0
|
|
800773e: d001 beq.n 8007744 <USBD_ClrClassConfig+0x2a>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8007740: 2303 movs r3, #3
|
|
8007742: 73fb strb r3, [r7, #15]
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8007744: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007746: 4618 mov r0, r3
|
|
8007748: 3710 adds r7, #16
|
|
800774a: 46bd mov sp, r7
|
|
800774c: bd80 pop {r7, pc}
|
|
|
|
0800774e <USBD_LL_SetupStage>:
|
|
* @param pdev: device instance
|
|
* @param psetup: setup packet buffer pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
|
|
{
|
|
800774e: b580 push {r7, lr}
|
|
8007750: b084 sub sp, #16
|
|
8007752: af00 add r7, sp, #0
|
|
8007754: 6078 str r0, [r7, #4]
|
|
8007756: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret;
|
|
|
|
USBD_ParseSetupRequest(&pdev->request, psetup);
|
|
8007758: 687b ldr r3, [r7, #4]
|
|
800775a: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
800775e: 6839 ldr r1, [r7, #0]
|
|
8007760: 4618 mov r0, r3
|
|
8007762: f001 f94c bl 80089fe <USBD_ParseSetupRequest>
|
|
|
|
pdev->ep0_state = USBD_EP0_SETUP;
|
|
8007766: 687b ldr r3, [r7, #4]
|
|
8007768: 2201 movs r2, #1
|
|
800776a: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
pdev->ep0_data_len = pdev->request.wLength;
|
|
800776e: 687b ldr r3, [r7, #4]
|
|
8007770: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0
|
|
8007774: 461a mov r2, r3
|
|
8007776: 687b ldr r3, [r7, #4]
|
|
8007778: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
800777c: 687b ldr r3, [r7, #4]
|
|
800777e: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8007782: f003 031f and.w r3, r3, #31
|
|
8007786: 2b02 cmp r3, #2
|
|
8007788: d01a beq.n 80077c0 <USBD_LL_SetupStage+0x72>
|
|
800778a: 2b02 cmp r3, #2
|
|
800778c: d822 bhi.n 80077d4 <USBD_LL_SetupStage+0x86>
|
|
800778e: 2b00 cmp r3, #0
|
|
8007790: d002 beq.n 8007798 <USBD_LL_SetupStage+0x4a>
|
|
8007792: 2b01 cmp r3, #1
|
|
8007794: d00a beq.n 80077ac <USBD_LL_SetupStage+0x5e>
|
|
8007796: e01d b.n 80077d4 <USBD_LL_SetupStage+0x86>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
ret = USBD_StdDevReq(pdev, &pdev->request);
|
|
8007798: 687b ldr r3, [r7, #4]
|
|
800779a: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
800779e: 4619 mov r1, r3
|
|
80077a0: 6878 ldr r0, [r7, #4]
|
|
80077a2: f000 fb77 bl 8007e94 <USBD_StdDevReq>
|
|
80077a6: 4603 mov r3, r0
|
|
80077a8: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80077aa: e020 b.n 80077ee <USBD_LL_SetupStage+0xa0>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
ret = USBD_StdItfReq(pdev, &pdev->request);
|
|
80077ac: 687b ldr r3, [r7, #4]
|
|
80077ae: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
80077b2: 4619 mov r1, r3
|
|
80077b4: 6878 ldr r0, [r7, #4]
|
|
80077b6: f000 fbdf bl 8007f78 <USBD_StdItfReq>
|
|
80077ba: 4603 mov r3, r0
|
|
80077bc: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80077be: e016 b.n 80077ee <USBD_LL_SetupStage+0xa0>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
ret = USBD_StdEPReq(pdev, &pdev->request);
|
|
80077c0: 687b ldr r3, [r7, #4]
|
|
80077c2: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
80077c6: 4619 mov r1, r3
|
|
80077c8: 6878 ldr r0, [r7, #4]
|
|
80077ca: f000 fc41 bl 8008050 <USBD_StdEPReq>
|
|
80077ce: 4603 mov r3, r0
|
|
80077d0: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80077d2: e00c b.n 80077ee <USBD_LL_SetupStage+0xa0>
|
|
|
|
default:
|
|
ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
|
|
80077d4: 687b ldr r3, [r7, #4]
|
|
80077d6: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
80077da: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
80077de: b2db uxtb r3, r3
|
|
80077e0: 4619 mov r1, r3
|
|
80077e2: 6878 ldr r0, [r7, #4]
|
|
80077e4: f001 fd78 bl 80092d8 <USBD_LL_StallEP>
|
|
80077e8: 4603 mov r3, r0
|
|
80077ea: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80077ec: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
80077ee: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80077f0: 4618 mov r0, r3
|
|
80077f2: 3710 adds r7, #16
|
|
80077f4: 46bd mov sp, r7
|
|
80077f6: bd80 pop {r7, pc}
|
|
|
|
080077f8 <USBD_LL_DataOutStage>:
|
|
* @param pdata: data pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
80077f8: b580 push {r7, lr}
|
|
80077fa: b086 sub sp, #24
|
|
80077fc: af00 add r7, sp, #0
|
|
80077fe: 60f8 str r0, [r7, #12]
|
|
8007800: 460b mov r3, r1
|
|
8007802: 607a str r2, [r7, #4]
|
|
8007804: 72fb strb r3, [r7, #11]
|
|
USBD_EndpointTypeDef *pep;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007806: 2300 movs r3, #0
|
|
8007808: 75fb strb r3, [r7, #23]
|
|
uint8_t idx;
|
|
|
|
UNUSED(pdata);
|
|
|
|
if (epnum == 0U)
|
|
800780a: 7afb ldrb r3, [r7, #11]
|
|
800780c: 2b00 cmp r3, #0
|
|
800780e: d177 bne.n 8007900 <USBD_LL_DataOutStage+0x108>
|
|
{
|
|
pep = &pdev->ep_out[0];
|
|
8007810: 68fb ldr r3, [r7, #12]
|
|
8007812: f503 73aa add.w r3, r3, #340 @ 0x154
|
|
8007816: 613b str r3, [r7, #16]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
|
|
8007818: 68fb ldr r3, [r7, #12]
|
|
800781a: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
800781e: 2b03 cmp r3, #3
|
|
8007820: f040 80a1 bne.w 8007966 <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
8007824: 693b ldr r3, [r7, #16]
|
|
8007826: 685b ldr r3, [r3, #4]
|
|
8007828: 693a ldr r2, [r7, #16]
|
|
800782a: 8992 ldrh r2, [r2, #12]
|
|
800782c: 4293 cmp r3, r2
|
|
800782e: d91c bls.n 800786a <USBD_LL_DataOutStage+0x72>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
8007830: 693b ldr r3, [r7, #16]
|
|
8007832: 685b ldr r3, [r3, #4]
|
|
8007834: 693a ldr r2, [r7, #16]
|
|
8007836: 8992 ldrh r2, [r2, #12]
|
|
8007838: 1a9a subs r2, r3, r2
|
|
800783a: 693b ldr r3, [r7, #16]
|
|
800783c: 605a str r2, [r3, #4]
|
|
pep->pbuffer += pep->maxpacket;
|
|
800783e: 693b ldr r3, [r7, #16]
|
|
8007840: 691b ldr r3, [r3, #16]
|
|
8007842: 693a ldr r2, [r7, #16]
|
|
8007844: 8992 ldrh r2, [r2, #12]
|
|
8007846: 441a add r2, r3
|
|
8007848: 693b ldr r3, [r7, #16]
|
|
800784a: 611a str r2, [r3, #16]
|
|
|
|
(void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket));
|
|
800784c: 693b ldr r3, [r7, #16]
|
|
800784e: 6919 ldr r1, [r3, #16]
|
|
8007850: 693b ldr r3, [r7, #16]
|
|
8007852: 899b ldrh r3, [r3, #12]
|
|
8007854: 461a mov r2, r3
|
|
8007856: 693b ldr r3, [r7, #16]
|
|
8007858: 685b ldr r3, [r3, #4]
|
|
800785a: 4293 cmp r3, r2
|
|
800785c: bf38 it cc
|
|
800785e: 4613 movcc r3, r2
|
|
8007860: 461a mov r2, r3
|
|
8007862: 68f8 ldr r0, [r7, #12]
|
|
8007864: f001 f9b1 bl 8008bca <USBD_CtlContinueRx>
|
|
8007868: e07d b.n 8007966 <USBD_LL_DataOutStage+0x16e>
|
|
}
|
|
else
|
|
{
|
|
/* Find the class ID relative to the current request */
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
800786a: 68fb ldr r3, [r7, #12]
|
|
800786c: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8007870: f003 031f and.w r3, r3, #31
|
|
8007874: 2b02 cmp r3, #2
|
|
8007876: d014 beq.n 80078a2 <USBD_LL_DataOutStage+0xaa>
|
|
8007878: 2b02 cmp r3, #2
|
|
800787a: d81d bhi.n 80078b8 <USBD_LL_DataOutStage+0xc0>
|
|
800787c: 2b00 cmp r3, #0
|
|
800787e: d002 beq.n 8007886 <USBD_LL_DataOutStage+0x8e>
|
|
8007880: 2b01 cmp r3, #1
|
|
8007882: d003 beq.n 800788c <USBD_LL_DataOutStage+0x94>
|
|
8007884: e018 b.n 80078b8 <USBD_LL_DataOutStage+0xc0>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
/* Device requests must be managed by the first instantiated class
|
|
(or duplicated by all classes for simplicity) */
|
|
idx = 0U;
|
|
8007886: 2300 movs r3, #0
|
|
8007888: 75bb strb r3, [r7, #22]
|
|
break;
|
|
800788a: e018 b.n 80078be <USBD_LL_DataOutStage+0xc6>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex));
|
|
800788c: 68fb ldr r3, [r7, #12]
|
|
800788e: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
8007892: b2db uxtb r3, r3
|
|
8007894: 4619 mov r1, r3
|
|
8007896: 68f8 ldr r0, [r7, #12]
|
|
8007898: f000 fa6e bl 8007d78 <USBD_CoreFindIF>
|
|
800789c: 4603 mov r3, r0
|
|
800789e: 75bb strb r3, [r7, #22]
|
|
break;
|
|
80078a0: e00d b.n 80078be <USBD_LL_DataOutStage+0xc6>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex));
|
|
80078a2: 68fb ldr r3, [r7, #12]
|
|
80078a4: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
80078a8: b2db uxtb r3, r3
|
|
80078aa: 4619 mov r1, r3
|
|
80078ac: 68f8 ldr r0, [r7, #12]
|
|
80078ae: f000 fa70 bl 8007d92 <USBD_CoreFindEP>
|
|
80078b2: 4603 mov r3, r0
|
|
80078b4: 75bb strb r3, [r7, #22]
|
|
break;
|
|
80078b6: e002 b.n 80078be <USBD_LL_DataOutStage+0xc6>
|
|
|
|
default:
|
|
/* Back to the first class in case of doubt */
|
|
idx = 0U;
|
|
80078b8: 2300 movs r3, #0
|
|
80078ba: 75bb strb r3, [r7, #22]
|
|
break;
|
|
80078bc: bf00 nop
|
|
}
|
|
|
|
if (idx < USBD_MAX_SUPPORTED_CLASS)
|
|
80078be: 7dbb ldrb r3, [r7, #22]
|
|
80078c0: 2b00 cmp r3, #0
|
|
80078c2: d119 bne.n 80078f8 <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
/* Setup the class ID and route the request to the relative class function */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80078c4: 68fb ldr r3, [r7, #12]
|
|
80078c6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80078ca: b2db uxtb r3, r3
|
|
80078cc: 2b03 cmp r3, #3
|
|
80078ce: d113 bne.n 80078f8 <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
if (pdev->pClass[idx]->EP0_RxReady != NULL)
|
|
80078d0: 7dba ldrb r2, [r7, #22]
|
|
80078d2: 68fb ldr r3, [r7, #12]
|
|
80078d4: 32ae adds r2, #174 @ 0xae
|
|
80078d6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80078da: 691b ldr r3, [r3, #16]
|
|
80078dc: 2b00 cmp r3, #0
|
|
80078de: d00b beq.n 80078f8 <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
pdev->classId = idx;
|
|
80078e0: 7dba ldrb r2, [r7, #22]
|
|
80078e2: 68fb ldr r3, [r7, #12]
|
|
80078e4: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
pdev->pClass[idx]->EP0_RxReady(pdev);
|
|
80078e8: 7dba ldrb r2, [r7, #22]
|
|
80078ea: 68fb ldr r3, [r7, #12]
|
|
80078ec: 32ae adds r2, #174 @ 0xae
|
|
80078ee: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80078f2: 691b ldr r3, [r3, #16]
|
|
80078f4: 68f8 ldr r0, [r7, #12]
|
|
80078f6: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80078f8: 68f8 ldr r0, [r7, #12]
|
|
80078fa: f001 f977 bl 8008bec <USBD_CtlSendStatus>
|
|
80078fe: e032 b.n 8007966 <USBD_LL_DataOutStage+0x16e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU));
|
|
8007900: 7afb ldrb r3, [r7, #11]
|
|
8007902: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8007906: b2db uxtb r3, r3
|
|
8007908: 4619 mov r1, r3
|
|
800790a: 68f8 ldr r0, [r7, #12]
|
|
800790c: f000 fa41 bl 8007d92 <USBD_CoreFindEP>
|
|
8007910: 4603 mov r3, r0
|
|
8007912: 75bb strb r3, [r7, #22]
|
|
|
|
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8007914: 7dbb ldrb r3, [r7, #22]
|
|
8007916: 2bff cmp r3, #255 @ 0xff
|
|
8007918: d025 beq.n 8007966 <USBD_LL_DataOutStage+0x16e>
|
|
800791a: 7dbb ldrb r3, [r7, #22]
|
|
800791c: 2b00 cmp r3, #0
|
|
800791e: d122 bne.n 8007966 <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007920: 68fb ldr r3, [r7, #12]
|
|
8007922: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007926: b2db uxtb r3, r3
|
|
8007928: 2b03 cmp r3, #3
|
|
800792a: d117 bne.n 800795c <USBD_LL_DataOutStage+0x164>
|
|
{
|
|
if (pdev->pClass[idx]->DataOut != NULL)
|
|
800792c: 7dba ldrb r2, [r7, #22]
|
|
800792e: 68fb ldr r3, [r7, #12]
|
|
8007930: 32ae adds r2, #174 @ 0xae
|
|
8007932: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007936: 699b ldr r3, [r3, #24]
|
|
8007938: 2b00 cmp r3, #0
|
|
800793a: d00f beq.n 800795c <USBD_LL_DataOutStage+0x164>
|
|
{
|
|
pdev->classId = idx;
|
|
800793c: 7dba ldrb r2, [r7, #22]
|
|
800793e: 68fb ldr r3, [r7, #12]
|
|
8007940: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum);
|
|
8007944: 7dba ldrb r2, [r7, #22]
|
|
8007946: 68fb ldr r3, [r7, #12]
|
|
8007948: 32ae adds r2, #174 @ 0xae
|
|
800794a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800794e: 699b ldr r3, [r3, #24]
|
|
8007950: 7afa ldrb r2, [r7, #11]
|
|
8007952: 4611 mov r1, r2
|
|
8007954: 68f8 ldr r0, [r7, #12]
|
|
8007956: 4798 blx r3
|
|
8007958: 4603 mov r3, r0
|
|
800795a: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
if (ret != USBD_OK)
|
|
800795c: 7dfb ldrb r3, [r7, #23]
|
|
800795e: 2b00 cmp r3, #0
|
|
8007960: d001 beq.n 8007966 <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
return ret;
|
|
8007962: 7dfb ldrb r3, [r7, #23]
|
|
8007964: e000 b.n 8007968 <USBD_LL_DataOutStage+0x170>
|
|
}
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007966: 2300 movs r3, #0
|
|
}
|
|
8007968: 4618 mov r0, r3
|
|
800796a: 3718 adds r7, #24
|
|
800796c: 46bd mov sp, r7
|
|
800796e: bd80 pop {r7, pc}
|
|
|
|
08007970 <USBD_LL_DataInStage>:
|
|
* @param pdata: data pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
8007970: b580 push {r7, lr}
|
|
8007972: b086 sub sp, #24
|
|
8007974: af00 add r7, sp, #0
|
|
8007976: 60f8 str r0, [r7, #12]
|
|
8007978: 460b mov r3, r1
|
|
800797a: 607a str r2, [r7, #4]
|
|
800797c: 72fb strb r3, [r7, #11]
|
|
USBD_StatusTypeDef ret;
|
|
uint8_t idx;
|
|
|
|
UNUSED(pdata);
|
|
|
|
if (epnum == 0U)
|
|
800797e: 7afb ldrb r3, [r7, #11]
|
|
8007980: 2b00 cmp r3, #0
|
|
8007982: d178 bne.n 8007a76 <USBD_LL_DataInStage+0x106>
|
|
{
|
|
pep = &pdev->ep_in[0];
|
|
8007984: 68fb ldr r3, [r7, #12]
|
|
8007986: 3314 adds r3, #20
|
|
8007988: 613b str r3, [r7, #16]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_IN)
|
|
800798a: 68fb ldr r3, [r7, #12]
|
|
800798c: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
8007990: 2b02 cmp r3, #2
|
|
8007992: d163 bne.n 8007a5c <USBD_LL_DataInStage+0xec>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
8007994: 693b ldr r3, [r7, #16]
|
|
8007996: 685b ldr r3, [r3, #4]
|
|
8007998: 693a ldr r2, [r7, #16]
|
|
800799a: 8992 ldrh r2, [r2, #12]
|
|
800799c: 4293 cmp r3, r2
|
|
800799e: d91c bls.n 80079da <USBD_LL_DataInStage+0x6a>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
80079a0: 693b ldr r3, [r7, #16]
|
|
80079a2: 685b ldr r3, [r3, #4]
|
|
80079a4: 693a ldr r2, [r7, #16]
|
|
80079a6: 8992 ldrh r2, [r2, #12]
|
|
80079a8: 1a9a subs r2, r3, r2
|
|
80079aa: 693b ldr r3, [r7, #16]
|
|
80079ac: 605a str r2, [r3, #4]
|
|
pep->pbuffer += pep->maxpacket;
|
|
80079ae: 693b ldr r3, [r7, #16]
|
|
80079b0: 691b ldr r3, [r3, #16]
|
|
80079b2: 693a ldr r2, [r7, #16]
|
|
80079b4: 8992 ldrh r2, [r2, #12]
|
|
80079b6: 441a add r2, r3
|
|
80079b8: 693b ldr r3, [r7, #16]
|
|
80079ba: 611a str r2, [r3, #16]
|
|
|
|
(void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length);
|
|
80079bc: 693b ldr r3, [r7, #16]
|
|
80079be: 6919 ldr r1, [r3, #16]
|
|
80079c0: 693b ldr r3, [r7, #16]
|
|
80079c2: 685b ldr r3, [r3, #4]
|
|
80079c4: 461a mov r2, r3
|
|
80079c6: 68f8 ldr r0, [r7, #12]
|
|
80079c8: f001 f8ee bl 8008ba8 <USBD_CtlContinueSendData>
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
80079cc: 2300 movs r3, #0
|
|
80079ce: 2200 movs r2, #0
|
|
80079d0: 2100 movs r1, #0
|
|
80079d2: 68f8 ldr r0, [r7, #12]
|
|
80079d4: f001 fd2a bl 800942c <USBD_LL_PrepareReceive>
|
|
80079d8: e040 b.n 8007a5c <USBD_LL_DataInStage+0xec>
|
|
}
|
|
else
|
|
{
|
|
/* last packet is MPS multiple, so send ZLP packet */
|
|
if ((pep->maxpacket == pep->rem_length) &&
|
|
80079da: 693b ldr r3, [r7, #16]
|
|
80079dc: 899b ldrh r3, [r3, #12]
|
|
80079de: 461a mov r2, r3
|
|
80079e0: 693b ldr r3, [r7, #16]
|
|
80079e2: 685b ldr r3, [r3, #4]
|
|
80079e4: 429a cmp r2, r3
|
|
80079e6: d11c bne.n 8007a22 <USBD_LL_DataInStage+0xb2>
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
80079e8: 693b ldr r3, [r7, #16]
|
|
80079ea: 681b ldr r3, [r3, #0]
|
|
80079ec: 693a ldr r2, [r7, #16]
|
|
80079ee: 8992 ldrh r2, [r2, #12]
|
|
if ((pep->maxpacket == pep->rem_length) &&
|
|
80079f0: 4293 cmp r3, r2
|
|
80079f2: d316 bcc.n 8007a22 <USBD_LL_DataInStage+0xb2>
|
|
(pep->total_length < pdev->ep0_data_len))
|
|
80079f4: 693b ldr r3, [r7, #16]
|
|
80079f6: 681a ldr r2, [r3, #0]
|
|
80079f8: 68fb ldr r3, [r7, #12]
|
|
80079fa: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
80079fe: 429a cmp r2, r3
|
|
8007a00: d20f bcs.n 8007a22 <USBD_LL_DataInStage+0xb2>
|
|
{
|
|
(void)USBD_CtlContinueSendData(pdev, NULL, 0U);
|
|
8007a02: 2200 movs r2, #0
|
|
8007a04: 2100 movs r1, #0
|
|
8007a06: 68f8 ldr r0, [r7, #12]
|
|
8007a08: f001 f8ce bl 8008ba8 <USBD_CtlContinueSendData>
|
|
pdev->ep0_data_len = 0U;
|
|
8007a0c: 68fb ldr r3, [r7, #12]
|
|
8007a0e: 2200 movs r2, #0
|
|
8007a10: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8007a14: 2300 movs r3, #0
|
|
8007a16: 2200 movs r2, #0
|
|
8007a18: 2100 movs r1, #0
|
|
8007a1a: 68f8 ldr r0, [r7, #12]
|
|
8007a1c: f001 fd06 bl 800942c <USBD_LL_PrepareReceive>
|
|
8007a20: e01c b.n 8007a5c <USBD_LL_DataInStage+0xec>
|
|
}
|
|
else
|
|
{
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007a22: 68fb ldr r3, [r7, #12]
|
|
8007a24: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007a28: b2db uxtb r3, r3
|
|
8007a2a: 2b03 cmp r3, #3
|
|
8007a2c: d10f bne.n 8007a4e <USBD_LL_DataInStage+0xde>
|
|
{
|
|
if (pdev->pClass[0]->EP0_TxSent != NULL)
|
|
8007a2e: 68fb ldr r3, [r7, #12]
|
|
8007a30: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007a34: 68db ldr r3, [r3, #12]
|
|
8007a36: 2b00 cmp r3, #0
|
|
8007a38: d009 beq.n 8007a4e <USBD_LL_DataInStage+0xde>
|
|
{
|
|
pdev->classId = 0U;
|
|
8007a3a: 68fb ldr r3, [r7, #12]
|
|
8007a3c: 2200 movs r2, #0
|
|
8007a3e: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
pdev->pClass[0]->EP0_TxSent(pdev);
|
|
8007a42: 68fb ldr r3, [r7, #12]
|
|
8007a44: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007a48: 68db ldr r3, [r3, #12]
|
|
8007a4a: 68f8 ldr r0, [r7, #12]
|
|
8007a4c: 4798 blx r3
|
|
}
|
|
}
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8007a4e: 2180 movs r1, #128 @ 0x80
|
|
8007a50: 68f8 ldr r0, [r7, #12]
|
|
8007a52: f001 fc41 bl 80092d8 <USBD_LL_StallEP>
|
|
(void)USBD_CtlReceiveStatus(pdev);
|
|
8007a56: 68f8 ldr r0, [r7, #12]
|
|
8007a58: f001 f8db bl 8008c12 <USBD_CtlReceiveStatus>
|
|
}
|
|
}
|
|
}
|
|
|
|
if (pdev->dev_test_mode != 0U)
|
|
8007a5c: 68fb ldr r3, [r7, #12]
|
|
8007a5e: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
|
|
8007a62: 2b00 cmp r3, #0
|
|
8007a64: d03a beq.n 8007adc <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
(void)USBD_RunTestMode(pdev);
|
|
8007a66: 68f8 ldr r0, [r7, #12]
|
|
8007a68: f7ff fe30 bl 80076cc <USBD_RunTestMode>
|
|
pdev->dev_test_mode = 0U;
|
|
8007a6c: 68fb ldr r3, [r7, #12]
|
|
8007a6e: 2200 movs r2, #0
|
|
8007a70: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
8007a74: e032 b.n 8007adc <USBD_LL_DataInStage+0x16c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U));
|
|
8007a76: 7afb ldrb r3, [r7, #11]
|
|
8007a78: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8007a7c: b2db uxtb r3, r3
|
|
8007a7e: 4619 mov r1, r3
|
|
8007a80: 68f8 ldr r0, [r7, #12]
|
|
8007a82: f000 f986 bl 8007d92 <USBD_CoreFindEP>
|
|
8007a86: 4603 mov r3, r0
|
|
8007a88: 75fb strb r3, [r7, #23]
|
|
|
|
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8007a8a: 7dfb ldrb r3, [r7, #23]
|
|
8007a8c: 2bff cmp r3, #255 @ 0xff
|
|
8007a8e: d025 beq.n 8007adc <USBD_LL_DataInStage+0x16c>
|
|
8007a90: 7dfb ldrb r3, [r7, #23]
|
|
8007a92: 2b00 cmp r3, #0
|
|
8007a94: d122 bne.n 8007adc <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007a96: 68fb ldr r3, [r7, #12]
|
|
8007a98: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007a9c: b2db uxtb r3, r3
|
|
8007a9e: 2b03 cmp r3, #3
|
|
8007aa0: d11c bne.n 8007adc <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
if (pdev->pClass[idx]->DataIn != NULL)
|
|
8007aa2: 7dfa ldrb r2, [r7, #23]
|
|
8007aa4: 68fb ldr r3, [r7, #12]
|
|
8007aa6: 32ae adds r2, #174 @ 0xae
|
|
8007aa8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007aac: 695b ldr r3, [r3, #20]
|
|
8007aae: 2b00 cmp r3, #0
|
|
8007ab0: d014 beq.n 8007adc <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
pdev->classId = idx;
|
|
8007ab2: 7dfa ldrb r2, [r7, #23]
|
|
8007ab4: 68fb ldr r3, [r7, #12]
|
|
8007ab6: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum);
|
|
8007aba: 7dfa ldrb r2, [r7, #23]
|
|
8007abc: 68fb ldr r3, [r7, #12]
|
|
8007abe: 32ae adds r2, #174 @ 0xae
|
|
8007ac0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007ac4: 695b ldr r3, [r3, #20]
|
|
8007ac6: 7afa ldrb r2, [r7, #11]
|
|
8007ac8: 4611 mov r1, r2
|
|
8007aca: 68f8 ldr r0, [r7, #12]
|
|
8007acc: 4798 blx r3
|
|
8007ace: 4603 mov r3, r0
|
|
8007ad0: 75bb strb r3, [r7, #22]
|
|
|
|
if (ret != USBD_OK)
|
|
8007ad2: 7dbb ldrb r3, [r7, #22]
|
|
8007ad4: 2b00 cmp r3, #0
|
|
8007ad6: d001 beq.n 8007adc <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
return ret;
|
|
8007ad8: 7dbb ldrb r3, [r7, #22]
|
|
8007ada: e000 b.n 8007ade <USBD_LL_DataInStage+0x16e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007adc: 2300 movs r3, #0
|
|
}
|
|
8007ade: 4618 mov r0, r3
|
|
8007ae0: 3718 adds r7, #24
|
|
8007ae2: 46bd mov sp, r7
|
|
8007ae4: bd80 pop {r7, pc}
|
|
|
|
08007ae6 <USBD_LL_Reset>:
|
|
* Handle Reset event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007ae6: b580 push {r7, lr}
|
|
8007ae8: b084 sub sp, #16
|
|
8007aea: af00 add r7, sp, #0
|
|
8007aec: 6078 str r0, [r7, #4]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007aee: 2300 movs r3, #0
|
|
8007af0: 73fb strb r3, [r7, #15]
|
|
|
|
/* Upon Reset call user call back */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8007af2: 687b ldr r3, [r7, #4]
|
|
8007af4: 2201 movs r2, #1
|
|
8007af6: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->ep0_state = USBD_EP0_IDLE;
|
|
8007afa: 687b ldr r3, [r7, #4]
|
|
8007afc: 2200 movs r2, #0
|
|
8007afe: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->dev_config = 0U;
|
|
8007b02: 687b ldr r3, [r7, #4]
|
|
8007b04: 2200 movs r2, #0
|
|
8007b06: 605a str r2, [r3, #4]
|
|
pdev->dev_remote_wakeup = 0U;
|
|
8007b08: 687b ldr r3, [r7, #4]
|
|
8007b0a: 2200 movs r2, #0
|
|
8007b0c: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
pdev->dev_test_mode = 0U;
|
|
8007b10: 687b ldr r3, [r7, #4]
|
|
8007b12: 2200 movs r2, #0
|
|
8007b14: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
|
|
if (pdev->pClass[0] != NULL)
|
|
8007b18: 687b ldr r3, [r7, #4]
|
|
8007b1a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007b1e: 2b00 cmp r3, #0
|
|
8007b20: d014 beq.n 8007b4c <USBD_LL_Reset+0x66>
|
|
{
|
|
if (pdev->pClass[0]->DeInit != NULL)
|
|
8007b22: 687b ldr r3, [r7, #4]
|
|
8007b24: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007b28: 685b ldr r3, [r3, #4]
|
|
8007b2a: 2b00 cmp r3, #0
|
|
8007b2c: d00e beq.n 8007b4c <USBD_LL_Reset+0x66>
|
|
{
|
|
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK)
|
|
8007b2e: 687b ldr r3, [r7, #4]
|
|
8007b30: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007b34: 685b ldr r3, [r3, #4]
|
|
8007b36: 687a ldr r2, [r7, #4]
|
|
8007b38: 6852 ldr r2, [r2, #4]
|
|
8007b3a: b2d2 uxtb r2, r2
|
|
8007b3c: 4611 mov r1, r2
|
|
8007b3e: 6878 ldr r0, [r7, #4]
|
|
8007b40: 4798 blx r3
|
|
8007b42: 4603 mov r3, r0
|
|
8007b44: 2b00 cmp r3, #0
|
|
8007b46: d001 beq.n 8007b4c <USBD_LL_Reset+0x66>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8007b48: 2303 movs r3, #3
|
|
8007b4a: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Open EP0 OUT */
|
|
(void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
8007b4c: 2340 movs r3, #64 @ 0x40
|
|
8007b4e: 2200 movs r2, #0
|
|
8007b50: 2100 movs r1, #0
|
|
8007b52: 6878 ldr r0, [r7, #4]
|
|
8007b54: f001 fb7b bl 800924e <USBD_LL_OpenEP>
|
|
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
|
|
8007b58: 687b ldr r3, [r7, #4]
|
|
8007b5a: 2201 movs r2, #1
|
|
8007b5c: f883 2163 strb.w r2, [r3, #355] @ 0x163
|
|
|
|
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
8007b60: 687b ldr r3, [r7, #4]
|
|
8007b62: 2240 movs r2, #64 @ 0x40
|
|
8007b64: f8a3 2160 strh.w r2, [r3, #352] @ 0x160
|
|
|
|
/* Open EP0 IN */
|
|
(void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
8007b68: 2340 movs r3, #64 @ 0x40
|
|
8007b6a: 2200 movs r2, #0
|
|
8007b6c: 2180 movs r1, #128 @ 0x80
|
|
8007b6e: 6878 ldr r0, [r7, #4]
|
|
8007b70: f001 fb6d bl 800924e <USBD_LL_OpenEP>
|
|
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
|
|
8007b74: 687b ldr r3, [r7, #4]
|
|
8007b76: 2201 movs r2, #1
|
|
8007b78: f883 2023 strb.w r2, [r3, #35] @ 0x23
|
|
|
|
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
8007b7c: 687b ldr r3, [r7, #4]
|
|
8007b7e: 2240 movs r2, #64 @ 0x40
|
|
8007b80: 841a strh r2, [r3, #32]
|
|
|
|
return ret;
|
|
8007b82: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007b84: 4618 mov r0, r3
|
|
8007b86: 3710 adds r7, #16
|
|
8007b88: 46bd mov sp, r7
|
|
8007b8a: bd80 pop {r7, pc}
|
|
|
|
08007b8c <USBD_LL_SetSpeed>:
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
|
|
USBD_SpeedTypeDef speed)
|
|
{
|
|
8007b8c: b480 push {r7}
|
|
8007b8e: b083 sub sp, #12
|
|
8007b90: af00 add r7, sp, #0
|
|
8007b92: 6078 str r0, [r7, #4]
|
|
8007b94: 460b mov r3, r1
|
|
8007b96: 70fb strb r3, [r7, #3]
|
|
pdev->dev_speed = speed;
|
|
8007b98: 687b ldr r3, [r7, #4]
|
|
8007b9a: 78fa ldrb r2, [r7, #3]
|
|
8007b9c: 741a strb r2, [r3, #16]
|
|
|
|
return USBD_OK;
|
|
8007b9e: 2300 movs r3, #0
|
|
}
|
|
8007ba0: 4618 mov r0, r3
|
|
8007ba2: 370c adds r7, #12
|
|
8007ba4: 46bd mov sp, r7
|
|
8007ba6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007baa: 4770 bx lr
|
|
|
|
08007bac <USBD_LL_Suspend>:
|
|
* Handle Suspend event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007bac: b480 push {r7}
|
|
8007bae: b083 sub sp, #12
|
|
8007bb0: af00 add r7, sp, #0
|
|
8007bb2: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state != USBD_STATE_SUSPENDED)
|
|
8007bb4: 687b ldr r3, [r7, #4]
|
|
8007bb6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007bba: b2db uxtb r3, r3
|
|
8007bbc: 2b04 cmp r3, #4
|
|
8007bbe: d006 beq.n 8007bce <USBD_LL_Suspend+0x22>
|
|
{
|
|
pdev->dev_old_state = pdev->dev_state;
|
|
8007bc0: 687b ldr r3, [r7, #4]
|
|
8007bc2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007bc6: b2da uxtb r2, r3
|
|
8007bc8: 687b ldr r3, [r7, #4]
|
|
8007bca: f883 229d strb.w r2, [r3, #669] @ 0x29d
|
|
}
|
|
|
|
pdev->dev_state = USBD_STATE_SUSPENDED;
|
|
8007bce: 687b ldr r3, [r7, #4]
|
|
8007bd0: 2204 movs r2, #4
|
|
8007bd2: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
|
|
return USBD_OK;
|
|
8007bd6: 2300 movs r3, #0
|
|
}
|
|
8007bd8: 4618 mov r0, r3
|
|
8007bda: 370c adds r7, #12
|
|
8007bdc: 46bd mov sp, r7
|
|
8007bde: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007be2: 4770 bx lr
|
|
|
|
08007be4 <USBD_LL_Resume>:
|
|
* Handle Resume event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007be4: b480 push {r7}
|
|
8007be6: b083 sub sp, #12
|
|
8007be8: af00 add r7, sp, #0
|
|
8007bea: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state == USBD_STATE_SUSPENDED)
|
|
8007bec: 687b ldr r3, [r7, #4]
|
|
8007bee: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007bf2: b2db uxtb r3, r3
|
|
8007bf4: 2b04 cmp r3, #4
|
|
8007bf6: d106 bne.n 8007c06 <USBD_LL_Resume+0x22>
|
|
{
|
|
pdev->dev_state = pdev->dev_old_state;
|
|
8007bf8: 687b ldr r3, [r7, #4]
|
|
8007bfa: f893 329d ldrb.w r3, [r3, #669] @ 0x29d
|
|
8007bfe: b2da uxtb r2, r3
|
|
8007c00: 687b ldr r3, [r7, #4]
|
|
8007c02: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007c06: 2300 movs r3, #0
|
|
}
|
|
8007c08: 4618 mov r0, r3
|
|
8007c0a: 370c adds r7, #12
|
|
8007c0c: 46bd mov sp, r7
|
|
8007c0e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007c12: 4770 bx lr
|
|
|
|
08007c14 <USBD_LL_SOF>:
|
|
* Handle SOF event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007c14: b580 push {r7, lr}
|
|
8007c16: b082 sub sp, #8
|
|
8007c18: af00 add r7, sp, #0
|
|
8007c1a: 6078 str r0, [r7, #4]
|
|
/* The SOF event can be distributed for all classes that support it */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007c1c: 687b ldr r3, [r7, #4]
|
|
8007c1e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007c22: b2db uxtb r3, r3
|
|
8007c24: 2b03 cmp r3, #3
|
|
8007c26: d110 bne.n 8007c4a <USBD_LL_SOF+0x36>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
8007c28: 687b ldr r3, [r7, #4]
|
|
8007c2a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007c2e: 2b00 cmp r3, #0
|
|
8007c30: d00b beq.n 8007c4a <USBD_LL_SOF+0x36>
|
|
{
|
|
if (pdev->pClass[0]->SOF != NULL)
|
|
8007c32: 687b ldr r3, [r7, #4]
|
|
8007c34: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007c38: 69db ldr r3, [r3, #28]
|
|
8007c3a: 2b00 cmp r3, #0
|
|
8007c3c: d005 beq.n 8007c4a <USBD_LL_SOF+0x36>
|
|
{
|
|
(void)pdev->pClass[0]->SOF(pdev);
|
|
8007c3e: 687b ldr r3, [r7, #4]
|
|
8007c40: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007c44: 69db ldr r3, [r3, #28]
|
|
8007c46: 6878 ldr r0, [r7, #4]
|
|
8007c48: 4798 blx r3
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007c4a: 2300 movs r3, #0
|
|
}
|
|
8007c4c: 4618 mov r0, r3
|
|
8007c4e: 3708 adds r7, #8
|
|
8007c50: 46bd mov sp, r7
|
|
8007c52: bd80 pop {r7, pc}
|
|
|
|
08007c54 <USBD_LL_IsoINIncomplete>:
|
|
* @param epnum: Endpoint number
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum)
|
|
{
|
|
8007c54: b580 push {r7, lr}
|
|
8007c56: b082 sub sp, #8
|
|
8007c58: af00 add r7, sp, #0
|
|
8007c5a: 6078 str r0, [r7, #4]
|
|
8007c5c: 460b mov r3, r1
|
|
8007c5e: 70fb strb r3, [r7, #3]
|
|
if (pdev->pClass[pdev->classId] == NULL)
|
|
8007c60: 687b ldr r3, [r7, #4]
|
|
8007c62: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007c66: 687b ldr r3, [r7, #4]
|
|
8007c68: 32ae adds r2, #174 @ 0xae
|
|
8007c6a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007c6e: 2b00 cmp r3, #0
|
|
8007c70: d101 bne.n 8007c76 <USBD_LL_IsoINIncomplete+0x22>
|
|
{
|
|
return USBD_FAIL;
|
|
8007c72: 2303 movs r3, #3
|
|
8007c74: e01c b.n 8007cb0 <USBD_LL_IsoINIncomplete+0x5c>
|
|
}
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007c76: 687b ldr r3, [r7, #4]
|
|
8007c78: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007c7c: b2db uxtb r3, r3
|
|
8007c7e: 2b03 cmp r3, #3
|
|
8007c80: d115 bne.n 8007cae <USBD_LL_IsoINIncomplete+0x5a>
|
|
{
|
|
if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL)
|
|
8007c82: 687b ldr r3, [r7, #4]
|
|
8007c84: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007c88: 687b ldr r3, [r7, #4]
|
|
8007c8a: 32ae adds r2, #174 @ 0xae
|
|
8007c8c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007c90: 6a1b ldr r3, [r3, #32]
|
|
8007c92: 2b00 cmp r3, #0
|
|
8007c94: d00b beq.n 8007cae <USBD_LL_IsoINIncomplete+0x5a>
|
|
{
|
|
(void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum);
|
|
8007c96: 687b ldr r3, [r7, #4]
|
|
8007c98: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007c9c: 687b ldr r3, [r7, #4]
|
|
8007c9e: 32ae adds r2, #174 @ 0xae
|
|
8007ca0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007ca4: 6a1b ldr r3, [r3, #32]
|
|
8007ca6: 78fa ldrb r2, [r7, #3]
|
|
8007ca8: 4611 mov r1, r2
|
|
8007caa: 6878 ldr r0, [r7, #4]
|
|
8007cac: 4798 blx r3
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007cae: 2300 movs r3, #0
|
|
}
|
|
8007cb0: 4618 mov r0, r3
|
|
8007cb2: 3708 adds r7, #8
|
|
8007cb4: 46bd mov sp, r7
|
|
8007cb6: bd80 pop {r7, pc}
|
|
|
|
08007cb8 <USBD_LL_IsoOUTIncomplete>:
|
|
* @param epnum: Endpoint number
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum)
|
|
{
|
|
8007cb8: b580 push {r7, lr}
|
|
8007cba: b082 sub sp, #8
|
|
8007cbc: af00 add r7, sp, #0
|
|
8007cbe: 6078 str r0, [r7, #4]
|
|
8007cc0: 460b mov r3, r1
|
|
8007cc2: 70fb strb r3, [r7, #3]
|
|
if (pdev->pClass[pdev->classId] == NULL)
|
|
8007cc4: 687b ldr r3, [r7, #4]
|
|
8007cc6: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007cca: 687b ldr r3, [r7, #4]
|
|
8007ccc: 32ae adds r2, #174 @ 0xae
|
|
8007cce: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007cd2: 2b00 cmp r3, #0
|
|
8007cd4: d101 bne.n 8007cda <USBD_LL_IsoOUTIncomplete+0x22>
|
|
{
|
|
return USBD_FAIL;
|
|
8007cd6: 2303 movs r3, #3
|
|
8007cd8: e01c b.n 8007d14 <USBD_LL_IsoOUTIncomplete+0x5c>
|
|
}
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007cda: 687b ldr r3, [r7, #4]
|
|
8007cdc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007ce0: b2db uxtb r3, r3
|
|
8007ce2: 2b03 cmp r3, #3
|
|
8007ce4: d115 bne.n 8007d12 <USBD_LL_IsoOUTIncomplete+0x5a>
|
|
{
|
|
if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL)
|
|
8007ce6: 687b ldr r3, [r7, #4]
|
|
8007ce8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007cec: 687b ldr r3, [r7, #4]
|
|
8007cee: 32ae adds r2, #174 @ 0xae
|
|
8007cf0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007cf4: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007cf6: 2b00 cmp r3, #0
|
|
8007cf8: d00b beq.n 8007d12 <USBD_LL_IsoOUTIncomplete+0x5a>
|
|
{
|
|
(void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum);
|
|
8007cfa: 687b ldr r3, [r7, #4]
|
|
8007cfc: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007d00: 687b ldr r3, [r7, #4]
|
|
8007d02: 32ae adds r2, #174 @ 0xae
|
|
8007d04: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007d08: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007d0a: 78fa ldrb r2, [r7, #3]
|
|
8007d0c: 4611 mov r1, r2
|
|
8007d0e: 6878 ldr r0, [r7, #4]
|
|
8007d10: 4798 blx r3
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007d12: 2300 movs r3, #0
|
|
}
|
|
8007d14: 4618 mov r0, r3
|
|
8007d16: 3708 adds r7, #8
|
|
8007d18: 46bd mov sp, r7
|
|
8007d1a: bd80 pop {r7, pc}
|
|
|
|
08007d1c <USBD_LL_DevConnected>:
|
|
* Handle device connection event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007d1c: b480 push {r7}
|
|
8007d1e: b083 sub sp, #12
|
|
8007d20: af00 add r7, sp, #0
|
|
8007d22: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument compilation warning */
|
|
UNUSED(pdev);
|
|
|
|
return USBD_OK;
|
|
8007d24: 2300 movs r3, #0
|
|
}
|
|
8007d26: 4618 mov r0, r3
|
|
8007d28: 370c adds r7, #12
|
|
8007d2a: 46bd mov sp, r7
|
|
8007d2c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007d30: 4770 bx lr
|
|
|
|
08007d32 <USBD_LL_DevDisconnected>:
|
|
* Handle device disconnection event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007d32: b580 push {r7, lr}
|
|
8007d34: b084 sub sp, #16
|
|
8007d36: af00 add r7, sp, #0
|
|
8007d38: 6078 str r0, [r7, #4]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007d3a: 2300 movs r3, #0
|
|
8007d3c: 73fb strb r3, [r7, #15]
|
|
|
|
/* Free Class Resources */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8007d3e: 687b ldr r3, [r7, #4]
|
|
8007d40: 2201 movs r2, #1
|
|
8007d42: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
8007d46: 687b ldr r3, [r7, #4]
|
|
8007d48: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007d4c: 2b00 cmp r3, #0
|
|
8007d4e: d00e beq.n 8007d6e <USBD_LL_DevDisconnected+0x3c>
|
|
{
|
|
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U)
|
|
8007d50: 687b ldr r3, [r7, #4]
|
|
8007d52: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007d56: 685b ldr r3, [r3, #4]
|
|
8007d58: 687a ldr r2, [r7, #4]
|
|
8007d5a: 6852 ldr r2, [r2, #4]
|
|
8007d5c: b2d2 uxtb r2, r2
|
|
8007d5e: 4611 mov r1, r2
|
|
8007d60: 6878 ldr r0, [r7, #4]
|
|
8007d62: 4798 blx r3
|
|
8007d64: 4603 mov r3, r0
|
|
8007d66: 2b00 cmp r3, #0
|
|
8007d68: d001 beq.n 8007d6e <USBD_LL_DevDisconnected+0x3c>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8007d6a: 2303 movs r3, #3
|
|
8007d6c: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8007d6e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007d70: 4618 mov r0, r3
|
|
8007d72: 3710 adds r7, #16
|
|
8007d74: 46bd mov sp, r7
|
|
8007d76: bd80 pop {r7, pc}
|
|
|
|
08007d78 <USBD_CoreFindIF>:
|
|
* @param pdev: device instance
|
|
* @param index : selected interface number
|
|
* @retval index of the class using the selected interface number. OxFF if no class found.
|
|
*/
|
|
uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index)
|
|
{
|
|
8007d78: b480 push {r7}
|
|
8007d7a: b083 sub sp, #12
|
|
8007d7c: af00 add r7, sp, #0
|
|
8007d7e: 6078 str r0, [r7, #4]
|
|
8007d80: 460b mov r3, r1
|
|
8007d82: 70fb strb r3, [r7, #3]
|
|
return 0xFFU;
|
|
#else
|
|
UNUSED(pdev);
|
|
UNUSED(index);
|
|
|
|
return 0x00U;
|
|
8007d84: 2300 movs r3, #0
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
8007d86: 4618 mov r0, r3
|
|
8007d88: 370c adds r7, #12
|
|
8007d8a: 46bd mov sp, r7
|
|
8007d8c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007d90: 4770 bx lr
|
|
|
|
08007d92 <USBD_CoreFindEP>:
|
|
* @param pdev: device instance
|
|
* @param index : selected endpoint number
|
|
* @retval index of the class using the selected endpoint number. 0xFF if no class found.
|
|
*/
|
|
uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index)
|
|
{
|
|
8007d92: b480 push {r7}
|
|
8007d94: b083 sub sp, #12
|
|
8007d96: af00 add r7, sp, #0
|
|
8007d98: 6078 str r0, [r7, #4]
|
|
8007d9a: 460b mov r3, r1
|
|
8007d9c: 70fb strb r3, [r7, #3]
|
|
return 0xFFU;
|
|
#else
|
|
UNUSED(pdev);
|
|
UNUSED(index);
|
|
|
|
return 0x00U;
|
|
8007d9e: 2300 movs r3, #0
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
8007da0: 4618 mov r0, r3
|
|
8007da2: 370c adds r7, #12
|
|
8007da4: 46bd mov sp, r7
|
|
8007da6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007daa: 4770 bx lr
|
|
|
|
08007dac <USBD_GetEpDesc>:
|
|
* @param pConfDesc: pointer to Bos descriptor
|
|
* @param EpAddr: endpoint address
|
|
* @retval pointer to video endpoint descriptor
|
|
*/
|
|
void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr)
|
|
{
|
|
8007dac: b580 push {r7, lr}
|
|
8007dae: b086 sub sp, #24
|
|
8007db0: af00 add r7, sp, #0
|
|
8007db2: 6078 str r0, [r7, #4]
|
|
8007db4: 460b mov r3, r1
|
|
8007db6: 70fb strb r3, [r7, #3]
|
|
USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc;
|
|
8007db8: 687b ldr r3, [r7, #4]
|
|
8007dba: 617b str r3, [r7, #20]
|
|
USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc;
|
|
8007dbc: 687b ldr r3, [r7, #4]
|
|
8007dbe: 60fb str r3, [r7, #12]
|
|
USBD_EpDescTypeDef *pEpDesc = NULL;
|
|
8007dc0: 2300 movs r3, #0
|
|
8007dc2: 613b str r3, [r7, #16]
|
|
uint16_t ptr;
|
|
|
|
if (desc->wTotalLength > desc->bLength)
|
|
8007dc4: 68fb ldr r3, [r7, #12]
|
|
8007dc6: 885b ldrh r3, [r3, #2]
|
|
8007dc8: b29b uxth r3, r3
|
|
8007dca: 68fa ldr r2, [r7, #12]
|
|
8007dcc: 7812 ldrb r2, [r2, #0]
|
|
8007dce: 4293 cmp r3, r2
|
|
8007dd0: d91f bls.n 8007e12 <USBD_GetEpDesc+0x66>
|
|
{
|
|
ptr = desc->bLength;
|
|
8007dd2: 68fb ldr r3, [r7, #12]
|
|
8007dd4: 781b ldrb r3, [r3, #0]
|
|
8007dd6: 817b strh r3, [r7, #10]
|
|
|
|
while (ptr < desc->wTotalLength)
|
|
8007dd8: e013 b.n 8007e02 <USBD_GetEpDesc+0x56>
|
|
{
|
|
pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr);
|
|
8007dda: f107 030a add.w r3, r7, #10
|
|
8007dde: 4619 mov r1, r3
|
|
8007de0: 6978 ldr r0, [r7, #20]
|
|
8007de2: f000 f81b bl 8007e1c <USBD_GetNextDesc>
|
|
8007de6: 6178 str r0, [r7, #20]
|
|
|
|
if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT)
|
|
8007de8: 697b ldr r3, [r7, #20]
|
|
8007dea: 785b ldrb r3, [r3, #1]
|
|
8007dec: 2b05 cmp r3, #5
|
|
8007dee: d108 bne.n 8007e02 <USBD_GetEpDesc+0x56>
|
|
{
|
|
pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc;
|
|
8007df0: 697b ldr r3, [r7, #20]
|
|
8007df2: 613b str r3, [r7, #16]
|
|
|
|
if (pEpDesc->bEndpointAddress == EpAddr)
|
|
8007df4: 693b ldr r3, [r7, #16]
|
|
8007df6: 789b ldrb r3, [r3, #2]
|
|
8007df8: 78fa ldrb r2, [r7, #3]
|
|
8007dfa: 429a cmp r2, r3
|
|
8007dfc: d008 beq.n 8007e10 <USBD_GetEpDesc+0x64>
|
|
{
|
|
break;
|
|
}
|
|
else
|
|
{
|
|
pEpDesc = NULL;
|
|
8007dfe: 2300 movs r3, #0
|
|
8007e00: 613b str r3, [r7, #16]
|
|
while (ptr < desc->wTotalLength)
|
|
8007e02: 68fb ldr r3, [r7, #12]
|
|
8007e04: 885b ldrh r3, [r3, #2]
|
|
8007e06: b29a uxth r2, r3
|
|
8007e08: 897b ldrh r3, [r7, #10]
|
|
8007e0a: 429a cmp r2, r3
|
|
8007e0c: d8e5 bhi.n 8007dda <USBD_GetEpDesc+0x2e>
|
|
8007e0e: e000 b.n 8007e12 <USBD_GetEpDesc+0x66>
|
|
break;
|
|
8007e10: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return (void *)pEpDesc;
|
|
8007e12: 693b ldr r3, [r7, #16]
|
|
}
|
|
8007e14: 4618 mov r0, r3
|
|
8007e16: 3718 adds r7, #24
|
|
8007e18: 46bd mov sp, r7
|
|
8007e1a: bd80 pop {r7, pc}
|
|
|
|
08007e1c <USBD_GetNextDesc>:
|
|
* @param buf: Buffer where the descriptor is available
|
|
* @param ptr: data pointer inside the descriptor
|
|
* @retval next header
|
|
*/
|
|
USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr)
|
|
{
|
|
8007e1c: b480 push {r7}
|
|
8007e1e: b085 sub sp, #20
|
|
8007e20: af00 add r7, sp, #0
|
|
8007e22: 6078 str r0, [r7, #4]
|
|
8007e24: 6039 str r1, [r7, #0]
|
|
USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf;
|
|
8007e26: 687b ldr r3, [r7, #4]
|
|
8007e28: 60fb str r3, [r7, #12]
|
|
|
|
*ptr += pnext->bLength;
|
|
8007e2a: 683b ldr r3, [r7, #0]
|
|
8007e2c: 881b ldrh r3, [r3, #0]
|
|
8007e2e: 68fa ldr r2, [r7, #12]
|
|
8007e30: 7812 ldrb r2, [r2, #0]
|
|
8007e32: 4413 add r3, r2
|
|
8007e34: b29a uxth r2, r3
|
|
8007e36: 683b ldr r3, [r7, #0]
|
|
8007e38: 801a strh r2, [r3, #0]
|
|
pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength);
|
|
8007e3a: 68fb ldr r3, [r7, #12]
|
|
8007e3c: 781b ldrb r3, [r3, #0]
|
|
8007e3e: 461a mov r2, r3
|
|
8007e40: 687b ldr r3, [r7, #4]
|
|
8007e42: 4413 add r3, r2
|
|
8007e44: 60fb str r3, [r7, #12]
|
|
|
|
return (pnext);
|
|
8007e46: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8007e48: 4618 mov r0, r3
|
|
8007e4a: 3714 adds r7, #20
|
|
8007e4c: 46bd mov sp, r7
|
|
8007e4e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007e52: 4770 bx lr
|
|
|
|
08007e54 <SWAPBYTE>:
|
|
|
|
/** @defgroup USBD_DEF_Exported_Macros
|
|
* @{
|
|
*/
|
|
__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
|
|
{
|
|
8007e54: b480 push {r7}
|
|
8007e56: b087 sub sp, #28
|
|
8007e58: af00 add r7, sp, #0
|
|
8007e5a: 6078 str r0, [r7, #4]
|
|
uint16_t _SwapVal;
|
|
uint16_t _Byte1;
|
|
uint16_t _Byte2;
|
|
uint8_t *_pbuff = addr;
|
|
8007e5c: 687b ldr r3, [r7, #4]
|
|
8007e5e: 617b str r3, [r7, #20]
|
|
|
|
_Byte1 = *(uint8_t *)_pbuff;
|
|
8007e60: 697b ldr r3, [r7, #20]
|
|
8007e62: 781b ldrb r3, [r3, #0]
|
|
8007e64: 827b strh r3, [r7, #18]
|
|
_pbuff++;
|
|
8007e66: 697b ldr r3, [r7, #20]
|
|
8007e68: 3301 adds r3, #1
|
|
8007e6a: 617b str r3, [r7, #20]
|
|
_Byte2 = *(uint8_t *)_pbuff;
|
|
8007e6c: 697b ldr r3, [r7, #20]
|
|
8007e6e: 781b ldrb r3, [r3, #0]
|
|
8007e70: 823b strh r3, [r7, #16]
|
|
|
|
_SwapVal = (_Byte2 << 8) | _Byte1;
|
|
8007e72: f9b7 3010 ldrsh.w r3, [r7, #16]
|
|
8007e76: 021b lsls r3, r3, #8
|
|
8007e78: b21a sxth r2, r3
|
|
8007e7a: f9b7 3012 ldrsh.w r3, [r7, #18]
|
|
8007e7e: 4313 orrs r3, r2
|
|
8007e80: b21b sxth r3, r3
|
|
8007e82: 81fb strh r3, [r7, #14]
|
|
|
|
return _SwapVal;
|
|
8007e84: 89fb ldrh r3, [r7, #14]
|
|
}
|
|
8007e86: 4618 mov r0, r3
|
|
8007e88: 371c adds r7, #28
|
|
8007e8a: 46bd mov sp, r7
|
|
8007e8c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007e90: 4770 bx lr
|
|
...
|
|
|
|
08007e94 <USBD_StdDevReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007e94: b580 push {r7, lr}
|
|
8007e96: b084 sub sp, #16
|
|
8007e98: af00 add r7, sp, #0
|
|
8007e9a: 6078 str r0, [r7, #4]
|
|
8007e9c: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007e9e: 2300 movs r3, #0
|
|
8007ea0: 73fb strb r3, [r7, #15]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8007ea2: 683b ldr r3, [r7, #0]
|
|
8007ea4: 781b ldrb r3, [r3, #0]
|
|
8007ea6: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8007eaa: 2b40 cmp r3, #64 @ 0x40
|
|
8007eac: d005 beq.n 8007eba <USBD_StdDevReq+0x26>
|
|
8007eae: 2b40 cmp r3, #64 @ 0x40
|
|
8007eb0: d857 bhi.n 8007f62 <USBD_StdDevReq+0xce>
|
|
8007eb2: 2b00 cmp r3, #0
|
|
8007eb4: d00f beq.n 8007ed6 <USBD_StdDevReq+0x42>
|
|
8007eb6: 2b20 cmp r3, #32
|
|
8007eb8: d153 bne.n 8007f62 <USBD_StdDevReq+0xce>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req);
|
|
8007eba: 687b ldr r3, [r7, #4]
|
|
8007ebc: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007ec0: 687b ldr r3, [r7, #4]
|
|
8007ec2: 32ae adds r2, #174 @ 0xae
|
|
8007ec4: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007ec8: 689b ldr r3, [r3, #8]
|
|
8007eca: 6839 ldr r1, [r7, #0]
|
|
8007ecc: 6878 ldr r0, [r7, #4]
|
|
8007ece: 4798 blx r3
|
|
8007ed0: 4603 mov r3, r0
|
|
8007ed2: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8007ed4: e04a b.n 8007f6c <USBD_StdDevReq+0xd8>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
8007ed6: 683b ldr r3, [r7, #0]
|
|
8007ed8: 785b ldrb r3, [r3, #1]
|
|
8007eda: 2b09 cmp r3, #9
|
|
8007edc: d83b bhi.n 8007f56 <USBD_StdDevReq+0xc2>
|
|
8007ede: a201 add r2, pc, #4 @ (adr r2, 8007ee4 <USBD_StdDevReq+0x50>)
|
|
8007ee0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8007ee4: 08007f39 .word 0x08007f39
|
|
8007ee8: 08007f4d .word 0x08007f4d
|
|
8007eec: 08007f57 .word 0x08007f57
|
|
8007ef0: 08007f43 .word 0x08007f43
|
|
8007ef4: 08007f57 .word 0x08007f57
|
|
8007ef8: 08007f17 .word 0x08007f17
|
|
8007efc: 08007f0d .word 0x08007f0d
|
|
8007f00: 08007f57 .word 0x08007f57
|
|
8007f04: 08007f2f .word 0x08007f2f
|
|
8007f08: 08007f21 .word 0x08007f21
|
|
{
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
USBD_GetDescriptor(pdev, req);
|
|
8007f0c: 6839 ldr r1, [r7, #0]
|
|
8007f0e: 6878 ldr r0, [r7, #4]
|
|
8007f10: f000 fa3e bl 8008390 <USBD_GetDescriptor>
|
|
break;
|
|
8007f14: e024 b.n 8007f60 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_ADDRESS:
|
|
USBD_SetAddress(pdev, req);
|
|
8007f16: 6839 ldr r1, [r7, #0]
|
|
8007f18: 6878 ldr r0, [r7, #4]
|
|
8007f1a: f000 fbcd bl 80086b8 <USBD_SetAddress>
|
|
break;
|
|
8007f1e: e01f b.n 8007f60 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_CONFIGURATION:
|
|
ret = USBD_SetConfig(pdev, req);
|
|
8007f20: 6839 ldr r1, [r7, #0]
|
|
8007f22: 6878 ldr r0, [r7, #4]
|
|
8007f24: f000 fc0c bl 8008740 <USBD_SetConfig>
|
|
8007f28: 4603 mov r3, r0
|
|
8007f2a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8007f2c: e018 b.n 8007f60 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_GET_CONFIGURATION:
|
|
USBD_GetConfig(pdev, req);
|
|
8007f2e: 6839 ldr r1, [r7, #0]
|
|
8007f30: 6878 ldr r0, [r7, #4]
|
|
8007f32: f000 fcaf bl 8008894 <USBD_GetConfig>
|
|
break;
|
|
8007f36: e013 b.n 8007f60 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
USBD_GetStatus(pdev, req);
|
|
8007f38: 6839 ldr r1, [r7, #0]
|
|
8007f3a: 6878 ldr r0, [r7, #4]
|
|
8007f3c: f000 fce0 bl 8008900 <USBD_GetStatus>
|
|
break;
|
|
8007f40: e00e b.n 8007f60 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_FEATURE:
|
|
USBD_SetFeature(pdev, req);
|
|
8007f42: 6839 ldr r1, [r7, #0]
|
|
8007f44: 6878 ldr r0, [r7, #4]
|
|
8007f46: f000 fd0f bl 8008968 <USBD_SetFeature>
|
|
break;
|
|
8007f4a: e009 b.n 8007f60 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
USBD_ClrFeature(pdev, req);
|
|
8007f4c: 6839 ldr r1, [r7, #0]
|
|
8007f4e: 6878 ldr r0, [r7, #4]
|
|
8007f50: f000 fd33 bl 80089ba <USBD_ClrFeature>
|
|
break;
|
|
8007f54: e004 b.n 8007f60 <USBD_StdDevReq+0xcc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007f56: 6839 ldr r1, [r7, #0]
|
|
8007f58: 6878 ldr r0, [r7, #4]
|
|
8007f5a: f000 fd8a bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
8007f5e: bf00 nop
|
|
}
|
|
break;
|
|
8007f60: e004 b.n 8007f6c <USBD_StdDevReq+0xd8>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007f62: 6839 ldr r1, [r7, #0]
|
|
8007f64: 6878 ldr r0, [r7, #4]
|
|
8007f66: f000 fd84 bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
8007f6a: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8007f6c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007f6e: 4618 mov r0, r3
|
|
8007f70: 3710 adds r7, #16
|
|
8007f72: 46bd mov sp, r7
|
|
8007f74: bd80 pop {r7, pc}
|
|
8007f76: bf00 nop
|
|
|
|
08007f78 <USBD_StdItfReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007f78: b580 push {r7, lr}
|
|
8007f7a: b084 sub sp, #16
|
|
8007f7c: af00 add r7, sp, #0
|
|
8007f7e: 6078 str r0, [r7, #4]
|
|
8007f80: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007f82: 2300 movs r3, #0
|
|
8007f84: 73fb strb r3, [r7, #15]
|
|
uint8_t idx;
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8007f86: 683b ldr r3, [r7, #0]
|
|
8007f88: 781b ldrb r3, [r3, #0]
|
|
8007f8a: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8007f8e: 2b40 cmp r3, #64 @ 0x40
|
|
8007f90: d005 beq.n 8007f9e <USBD_StdItfReq+0x26>
|
|
8007f92: 2b40 cmp r3, #64 @ 0x40
|
|
8007f94: d852 bhi.n 800803c <USBD_StdItfReq+0xc4>
|
|
8007f96: 2b00 cmp r3, #0
|
|
8007f98: d001 beq.n 8007f9e <USBD_StdItfReq+0x26>
|
|
8007f9a: 2b20 cmp r3, #32
|
|
8007f9c: d14e bne.n 800803c <USBD_StdItfReq+0xc4>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (pdev->dev_state)
|
|
8007f9e: 687b ldr r3, [r7, #4]
|
|
8007fa0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007fa4: b2db uxtb r3, r3
|
|
8007fa6: 3b01 subs r3, #1
|
|
8007fa8: 2b02 cmp r3, #2
|
|
8007faa: d840 bhi.n 800802e <USBD_StdItfReq+0xb6>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
|
|
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
|
|
8007fac: 683b ldr r3, [r7, #0]
|
|
8007fae: 889b ldrh r3, [r3, #4]
|
|
8007fb0: b2db uxtb r3, r3
|
|
8007fb2: 2b01 cmp r3, #1
|
|
8007fb4: d836 bhi.n 8008024 <USBD_StdItfReq+0xac>
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex));
|
|
8007fb6: 683b ldr r3, [r7, #0]
|
|
8007fb8: 889b ldrh r3, [r3, #4]
|
|
8007fba: b2db uxtb r3, r3
|
|
8007fbc: 4619 mov r1, r3
|
|
8007fbe: 6878 ldr r0, [r7, #4]
|
|
8007fc0: f7ff feda bl 8007d78 <USBD_CoreFindIF>
|
|
8007fc4: 4603 mov r3, r0
|
|
8007fc6: 73bb strb r3, [r7, #14]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8007fc8: 7bbb ldrb r3, [r7, #14]
|
|
8007fca: 2bff cmp r3, #255 @ 0xff
|
|
8007fcc: d01d beq.n 800800a <USBD_StdItfReq+0x92>
|
|
8007fce: 7bbb ldrb r3, [r7, #14]
|
|
8007fd0: 2b00 cmp r3, #0
|
|
8007fd2: d11a bne.n 800800a <USBD_StdItfReq+0x92>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8007fd4: 7bba ldrb r2, [r7, #14]
|
|
8007fd6: 687b ldr r3, [r7, #4]
|
|
8007fd8: 32ae adds r2, #174 @ 0xae
|
|
8007fda: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007fde: 689b ldr r3, [r3, #8]
|
|
8007fe0: 2b00 cmp r3, #0
|
|
8007fe2: d00f beq.n 8008004 <USBD_StdItfReq+0x8c>
|
|
{
|
|
pdev->classId = idx;
|
|
8007fe4: 7bba ldrb r2, [r7, #14]
|
|
8007fe6: 687b ldr r3, [r7, #4]
|
|
8007fe8: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
|
|
8007fec: 7bba ldrb r2, [r7, #14]
|
|
8007fee: 687b ldr r3, [r7, #4]
|
|
8007ff0: 32ae adds r2, #174 @ 0xae
|
|
8007ff2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007ff6: 689b ldr r3, [r3, #8]
|
|
8007ff8: 6839 ldr r1, [r7, #0]
|
|
8007ffa: 6878 ldr r0, [r7, #4]
|
|
8007ffc: 4798 blx r3
|
|
8007ffe: 4603 mov r3, r0
|
|
8008000: 73fb strb r3, [r7, #15]
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8008002: e004 b.n 800800e <USBD_StdItfReq+0x96>
|
|
}
|
|
else
|
|
{
|
|
/* should never reach this condition */
|
|
ret = USBD_FAIL;
|
|
8008004: 2303 movs r3, #3
|
|
8008006: 73fb strb r3, [r7, #15]
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8008008: e001 b.n 800800e <USBD_StdItfReq+0x96>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* No relative interface found */
|
|
ret = USBD_FAIL;
|
|
800800a: 2303 movs r3, #3
|
|
800800c: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
if ((req->wLength == 0U) && (ret == USBD_OK))
|
|
800800e: 683b ldr r3, [r7, #0]
|
|
8008010: 88db ldrh r3, [r3, #6]
|
|
8008012: 2b00 cmp r3, #0
|
|
8008014: d110 bne.n 8008038 <USBD_StdItfReq+0xc0>
|
|
8008016: 7bfb ldrb r3, [r7, #15]
|
|
8008018: 2b00 cmp r3, #0
|
|
800801a: d10d bne.n 8008038 <USBD_StdItfReq+0xc0>
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800801c: 6878 ldr r0, [r7, #4]
|
|
800801e: f000 fde5 bl 8008bec <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
8008022: e009 b.n 8008038 <USBD_StdItfReq+0xc0>
|
|
USBD_CtlError(pdev, req);
|
|
8008024: 6839 ldr r1, [r7, #0]
|
|
8008026: 6878 ldr r0, [r7, #4]
|
|
8008028: f000 fd23 bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
800802c: e004 b.n 8008038 <USBD_StdItfReq+0xc0>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800802e: 6839 ldr r1, [r7, #0]
|
|
8008030: 6878 ldr r0, [r7, #4]
|
|
8008032: f000 fd1e bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
8008036: e000 b.n 800803a <USBD_StdItfReq+0xc2>
|
|
break;
|
|
8008038: bf00 nop
|
|
}
|
|
break;
|
|
800803a: e004 b.n 8008046 <USBD_StdItfReq+0xce>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800803c: 6839 ldr r1, [r7, #0]
|
|
800803e: 6878 ldr r0, [r7, #4]
|
|
8008040: f000 fd17 bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
8008044: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8008046: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008048: 4618 mov r0, r3
|
|
800804a: 3710 adds r7, #16
|
|
800804c: 46bd mov sp, r7
|
|
800804e: bd80 pop {r7, pc}
|
|
|
|
08008050 <USBD_StdEPReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008050: b580 push {r7, lr}
|
|
8008052: b084 sub sp, #16
|
|
8008054: af00 add r7, sp, #0
|
|
8008056: 6078 str r0, [r7, #4]
|
|
8008058: 6039 str r1, [r7, #0]
|
|
USBD_EndpointTypeDef *pep;
|
|
uint8_t ep_addr;
|
|
uint8_t idx;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
800805a: 2300 movs r3, #0
|
|
800805c: 73fb strb r3, [r7, #15]
|
|
|
|
ep_addr = LOBYTE(req->wIndex);
|
|
800805e: 683b ldr r3, [r7, #0]
|
|
8008060: 889b ldrh r3, [r3, #4]
|
|
8008062: 73bb strb r3, [r7, #14]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8008064: 683b ldr r3, [r7, #0]
|
|
8008066: 781b ldrb r3, [r3, #0]
|
|
8008068: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
800806c: 2b40 cmp r3, #64 @ 0x40
|
|
800806e: d007 beq.n 8008080 <USBD_StdEPReq+0x30>
|
|
8008070: 2b40 cmp r3, #64 @ 0x40
|
|
8008072: f200 8181 bhi.w 8008378 <USBD_StdEPReq+0x328>
|
|
8008076: 2b00 cmp r3, #0
|
|
8008078: d02a beq.n 80080d0 <USBD_StdEPReq+0x80>
|
|
800807a: 2b20 cmp r3, #32
|
|
800807c: f040 817c bne.w 8008378 <USBD_StdEPReq+0x328>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
/* Get the class index relative to this endpoint */
|
|
idx = USBD_CoreFindEP(pdev, ep_addr);
|
|
8008080: 7bbb ldrb r3, [r7, #14]
|
|
8008082: 4619 mov r1, r3
|
|
8008084: 6878 ldr r0, [r7, #4]
|
|
8008086: f7ff fe84 bl 8007d92 <USBD_CoreFindEP>
|
|
800808a: 4603 mov r3, r0
|
|
800808c: 737b strb r3, [r7, #13]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
800808e: 7b7b ldrb r3, [r7, #13]
|
|
8008090: 2bff cmp r3, #255 @ 0xff
|
|
8008092: f000 8176 beq.w 8008382 <USBD_StdEPReq+0x332>
|
|
8008096: 7b7b ldrb r3, [r7, #13]
|
|
8008098: 2b00 cmp r3, #0
|
|
800809a: f040 8172 bne.w 8008382 <USBD_StdEPReq+0x332>
|
|
{
|
|
pdev->classId = idx;
|
|
800809e: 7b7a ldrb r2, [r7, #13]
|
|
80080a0: 687b ldr r3, [r7, #4]
|
|
80080a2: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
80080a6: 7b7a ldrb r2, [r7, #13]
|
|
80080a8: 687b ldr r3, [r7, #4]
|
|
80080aa: 32ae adds r2, #174 @ 0xae
|
|
80080ac: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80080b0: 689b ldr r3, [r3, #8]
|
|
80080b2: 2b00 cmp r3, #0
|
|
80080b4: f000 8165 beq.w 8008382 <USBD_StdEPReq+0x332>
|
|
{
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req);
|
|
80080b8: 7b7a ldrb r2, [r7, #13]
|
|
80080ba: 687b ldr r3, [r7, #4]
|
|
80080bc: 32ae adds r2, #174 @ 0xae
|
|
80080be: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80080c2: 689b ldr r3, [r3, #8]
|
|
80080c4: 6839 ldr r1, [r7, #0]
|
|
80080c6: 6878 ldr r0, [r7, #4]
|
|
80080c8: 4798 blx r3
|
|
80080ca: 4603 mov r3, r0
|
|
80080cc: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
80080ce: e158 b.n 8008382 <USBD_StdEPReq+0x332>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
80080d0: 683b ldr r3, [r7, #0]
|
|
80080d2: 785b ldrb r3, [r3, #1]
|
|
80080d4: 2b03 cmp r3, #3
|
|
80080d6: d008 beq.n 80080ea <USBD_StdEPReq+0x9a>
|
|
80080d8: 2b03 cmp r3, #3
|
|
80080da: f300 8147 bgt.w 800836c <USBD_StdEPReq+0x31c>
|
|
80080de: 2b00 cmp r3, #0
|
|
80080e0: f000 809b beq.w 800821a <USBD_StdEPReq+0x1ca>
|
|
80080e4: 2b01 cmp r3, #1
|
|
80080e6: d03c beq.n 8008162 <USBD_StdEPReq+0x112>
|
|
80080e8: e140 b.n 800836c <USBD_StdEPReq+0x31c>
|
|
{
|
|
case USB_REQ_SET_FEATURE:
|
|
switch (pdev->dev_state)
|
|
80080ea: 687b ldr r3, [r7, #4]
|
|
80080ec: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80080f0: b2db uxtb r3, r3
|
|
80080f2: 2b02 cmp r3, #2
|
|
80080f4: d002 beq.n 80080fc <USBD_StdEPReq+0xac>
|
|
80080f6: 2b03 cmp r3, #3
|
|
80080f8: d016 beq.n 8008128 <USBD_StdEPReq+0xd8>
|
|
80080fa: e02c b.n 8008156 <USBD_StdEPReq+0x106>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
80080fc: 7bbb ldrb r3, [r7, #14]
|
|
80080fe: 2b00 cmp r3, #0
|
|
8008100: d00d beq.n 800811e <USBD_StdEPReq+0xce>
|
|
8008102: 7bbb ldrb r3, [r7, #14]
|
|
8008104: 2b80 cmp r3, #128 @ 0x80
|
|
8008106: d00a beq.n 800811e <USBD_StdEPReq+0xce>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
8008108: 7bbb ldrb r3, [r7, #14]
|
|
800810a: 4619 mov r1, r3
|
|
800810c: 6878 ldr r0, [r7, #4]
|
|
800810e: f001 f8e3 bl 80092d8 <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8008112: 2180 movs r1, #128 @ 0x80
|
|
8008114: 6878 ldr r0, [r7, #4]
|
|
8008116: f001 f8df bl 80092d8 <USBD_LL_StallEP>
|
|
800811a: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
800811c: e020 b.n 8008160 <USBD_StdEPReq+0x110>
|
|
USBD_CtlError(pdev, req);
|
|
800811e: 6839 ldr r1, [r7, #0]
|
|
8008120: 6878 ldr r0, [r7, #4]
|
|
8008122: f000 fca6 bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
8008126: e01b b.n 8008160 <USBD_StdEPReq+0x110>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
8008128: 683b ldr r3, [r7, #0]
|
|
800812a: 885b ldrh r3, [r3, #2]
|
|
800812c: 2b00 cmp r3, #0
|
|
800812e: d10e bne.n 800814e <USBD_StdEPReq+0xfe>
|
|
{
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U))
|
|
8008130: 7bbb ldrb r3, [r7, #14]
|
|
8008132: 2b00 cmp r3, #0
|
|
8008134: d00b beq.n 800814e <USBD_StdEPReq+0xfe>
|
|
8008136: 7bbb ldrb r3, [r7, #14]
|
|
8008138: 2b80 cmp r3, #128 @ 0x80
|
|
800813a: d008 beq.n 800814e <USBD_StdEPReq+0xfe>
|
|
800813c: 683b ldr r3, [r7, #0]
|
|
800813e: 88db ldrh r3, [r3, #6]
|
|
8008140: 2b00 cmp r3, #0
|
|
8008142: d104 bne.n 800814e <USBD_StdEPReq+0xfe>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
8008144: 7bbb ldrb r3, [r7, #14]
|
|
8008146: 4619 mov r1, r3
|
|
8008148: 6878 ldr r0, [r7, #4]
|
|
800814a: f001 f8c5 bl 80092d8 <USBD_LL_StallEP>
|
|
}
|
|
}
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800814e: 6878 ldr r0, [r7, #4]
|
|
8008150: f000 fd4c bl 8008bec <USBD_CtlSendStatus>
|
|
|
|
break;
|
|
8008154: e004 b.n 8008160 <USBD_StdEPReq+0x110>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008156: 6839 ldr r1, [r7, #0]
|
|
8008158: 6878 ldr r0, [r7, #4]
|
|
800815a: f000 fc8a bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
800815e: bf00 nop
|
|
}
|
|
break;
|
|
8008160: e109 b.n 8008376 <USBD_StdEPReq+0x326>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
|
|
switch (pdev->dev_state)
|
|
8008162: 687b ldr r3, [r7, #4]
|
|
8008164: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008168: b2db uxtb r3, r3
|
|
800816a: 2b02 cmp r3, #2
|
|
800816c: d002 beq.n 8008174 <USBD_StdEPReq+0x124>
|
|
800816e: 2b03 cmp r3, #3
|
|
8008170: d016 beq.n 80081a0 <USBD_StdEPReq+0x150>
|
|
8008172: e04b b.n 800820c <USBD_StdEPReq+0x1bc>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
8008174: 7bbb ldrb r3, [r7, #14]
|
|
8008176: 2b00 cmp r3, #0
|
|
8008178: d00d beq.n 8008196 <USBD_StdEPReq+0x146>
|
|
800817a: 7bbb ldrb r3, [r7, #14]
|
|
800817c: 2b80 cmp r3, #128 @ 0x80
|
|
800817e: d00a beq.n 8008196 <USBD_StdEPReq+0x146>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
8008180: 7bbb ldrb r3, [r7, #14]
|
|
8008182: 4619 mov r1, r3
|
|
8008184: 6878 ldr r0, [r7, #4]
|
|
8008186: f001 f8a7 bl 80092d8 <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
800818a: 2180 movs r1, #128 @ 0x80
|
|
800818c: 6878 ldr r0, [r7, #4]
|
|
800818e: f001 f8a3 bl 80092d8 <USBD_LL_StallEP>
|
|
8008192: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
8008194: e040 b.n 8008218 <USBD_StdEPReq+0x1c8>
|
|
USBD_CtlError(pdev, req);
|
|
8008196: 6839 ldr r1, [r7, #0]
|
|
8008198: 6878 ldr r0, [r7, #4]
|
|
800819a: f000 fc6a bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
800819e: e03b b.n 8008218 <USBD_StdEPReq+0x1c8>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
80081a0: 683b ldr r3, [r7, #0]
|
|
80081a2: 885b ldrh r3, [r3, #2]
|
|
80081a4: 2b00 cmp r3, #0
|
|
80081a6: d136 bne.n 8008216 <USBD_StdEPReq+0x1c6>
|
|
{
|
|
if ((ep_addr & 0x7FU) != 0x00U)
|
|
80081a8: 7bbb ldrb r3, [r7, #14]
|
|
80081aa: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
80081ae: 2b00 cmp r3, #0
|
|
80081b0: d004 beq.n 80081bc <USBD_StdEPReq+0x16c>
|
|
{
|
|
(void)USBD_LL_ClearStallEP(pdev, ep_addr);
|
|
80081b2: 7bbb ldrb r3, [r7, #14]
|
|
80081b4: 4619 mov r1, r3
|
|
80081b6: 6878 ldr r0, [r7, #4]
|
|
80081b8: f001 f8ad bl 8009316 <USBD_LL_ClearStallEP>
|
|
}
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80081bc: 6878 ldr r0, [r7, #4]
|
|
80081be: f000 fd15 bl 8008bec <USBD_CtlSendStatus>
|
|
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, ep_addr);
|
|
80081c2: 7bbb ldrb r3, [r7, #14]
|
|
80081c4: 4619 mov r1, r3
|
|
80081c6: 6878 ldr r0, [r7, #4]
|
|
80081c8: f7ff fde3 bl 8007d92 <USBD_CoreFindEP>
|
|
80081cc: 4603 mov r3, r0
|
|
80081ce: 737b strb r3, [r7, #13]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
80081d0: 7b7b ldrb r3, [r7, #13]
|
|
80081d2: 2bff cmp r3, #255 @ 0xff
|
|
80081d4: d01f beq.n 8008216 <USBD_StdEPReq+0x1c6>
|
|
80081d6: 7b7b ldrb r3, [r7, #13]
|
|
80081d8: 2b00 cmp r3, #0
|
|
80081da: d11c bne.n 8008216 <USBD_StdEPReq+0x1c6>
|
|
{
|
|
pdev->classId = idx;
|
|
80081dc: 7b7a ldrb r2, [r7, #13]
|
|
80081de: 687b ldr r3, [r7, #4]
|
|
80081e0: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
80081e4: 7b7a ldrb r2, [r7, #13]
|
|
80081e6: 687b ldr r3, [r7, #4]
|
|
80081e8: 32ae adds r2, #174 @ 0xae
|
|
80081ea: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80081ee: 689b ldr r3, [r3, #8]
|
|
80081f0: 2b00 cmp r3, #0
|
|
80081f2: d010 beq.n 8008216 <USBD_StdEPReq+0x1c6>
|
|
{
|
|
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
|
|
80081f4: 7b7a ldrb r2, [r7, #13]
|
|
80081f6: 687b ldr r3, [r7, #4]
|
|
80081f8: 32ae adds r2, #174 @ 0xae
|
|
80081fa: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80081fe: 689b ldr r3, [r3, #8]
|
|
8008200: 6839 ldr r1, [r7, #0]
|
|
8008202: 6878 ldr r0, [r7, #4]
|
|
8008204: 4798 blx r3
|
|
8008206: 4603 mov r3, r0
|
|
8008208: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
800820a: e004 b.n 8008216 <USBD_StdEPReq+0x1c6>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800820c: 6839 ldr r1, [r7, #0]
|
|
800820e: 6878 ldr r0, [r7, #4]
|
|
8008210: f000 fc2f bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
8008214: e000 b.n 8008218 <USBD_StdEPReq+0x1c8>
|
|
break;
|
|
8008216: bf00 nop
|
|
}
|
|
break;
|
|
8008218: e0ad b.n 8008376 <USBD_StdEPReq+0x326>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
switch (pdev->dev_state)
|
|
800821a: 687b ldr r3, [r7, #4]
|
|
800821c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008220: b2db uxtb r3, r3
|
|
8008222: 2b02 cmp r3, #2
|
|
8008224: d002 beq.n 800822c <USBD_StdEPReq+0x1dc>
|
|
8008226: 2b03 cmp r3, #3
|
|
8008228: d033 beq.n 8008292 <USBD_StdEPReq+0x242>
|
|
800822a: e099 b.n 8008360 <USBD_StdEPReq+0x310>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
800822c: 7bbb ldrb r3, [r7, #14]
|
|
800822e: 2b00 cmp r3, #0
|
|
8008230: d007 beq.n 8008242 <USBD_StdEPReq+0x1f2>
|
|
8008232: 7bbb ldrb r3, [r7, #14]
|
|
8008234: 2b80 cmp r3, #128 @ 0x80
|
|
8008236: d004 beq.n 8008242 <USBD_StdEPReq+0x1f2>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008238: 6839 ldr r1, [r7, #0]
|
|
800823a: 6878 ldr r0, [r7, #4]
|
|
800823c: f000 fc19 bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
8008240: e093 b.n 800836a <USBD_StdEPReq+0x31a>
|
|
}
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
8008242: f997 300e ldrsb.w r3, [r7, #14]
|
|
8008246: 2b00 cmp r3, #0
|
|
8008248: da0b bge.n 8008262 <USBD_StdEPReq+0x212>
|
|
800824a: 7bbb ldrb r3, [r7, #14]
|
|
800824c: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
8008250: 4613 mov r3, r2
|
|
8008252: 009b lsls r3, r3, #2
|
|
8008254: 4413 add r3, r2
|
|
8008256: 009b lsls r3, r3, #2
|
|
8008258: 3310 adds r3, #16
|
|
800825a: 687a ldr r2, [r7, #4]
|
|
800825c: 4413 add r3, r2
|
|
800825e: 3304 adds r3, #4
|
|
8008260: e00b b.n 800827a <USBD_StdEPReq+0x22a>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
8008262: 7bbb ldrb r3, [r7, #14]
|
|
8008264: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
8008268: 4613 mov r3, r2
|
|
800826a: 009b lsls r3, r3, #2
|
|
800826c: 4413 add r3, r2
|
|
800826e: 009b lsls r3, r3, #2
|
|
8008270: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8008274: 687a ldr r2, [r7, #4]
|
|
8008276: 4413 add r3, r2
|
|
8008278: 3304 adds r3, #4
|
|
800827a: 60bb str r3, [r7, #8]
|
|
|
|
pep->status = 0x0000U;
|
|
800827c: 68bb ldr r3, [r7, #8]
|
|
800827e: 2200 movs r2, #0
|
|
8008280: 739a strb r2, [r3, #14]
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
|
|
8008282: 68bb ldr r3, [r7, #8]
|
|
8008284: 330e adds r3, #14
|
|
8008286: 2202 movs r2, #2
|
|
8008288: 4619 mov r1, r3
|
|
800828a: 6878 ldr r0, [r7, #4]
|
|
800828c: f000 fc6e bl 8008b6c <USBD_CtlSendData>
|
|
break;
|
|
8008290: e06b b.n 800836a <USBD_StdEPReq+0x31a>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8008292: f997 300e ldrsb.w r3, [r7, #14]
|
|
8008296: 2b00 cmp r3, #0
|
|
8008298: da11 bge.n 80082be <USBD_StdEPReq+0x26e>
|
|
{
|
|
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
|
|
800829a: 7bbb ldrb r3, [r7, #14]
|
|
800829c: f003 020f and.w r2, r3, #15
|
|
80082a0: 6879 ldr r1, [r7, #4]
|
|
80082a2: 4613 mov r3, r2
|
|
80082a4: 009b lsls r3, r3, #2
|
|
80082a6: 4413 add r3, r2
|
|
80082a8: 009b lsls r3, r3, #2
|
|
80082aa: 440b add r3, r1
|
|
80082ac: 3323 adds r3, #35 @ 0x23
|
|
80082ae: 781b ldrb r3, [r3, #0]
|
|
80082b0: 2b00 cmp r3, #0
|
|
80082b2: d117 bne.n 80082e4 <USBD_StdEPReq+0x294>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80082b4: 6839 ldr r1, [r7, #0]
|
|
80082b6: 6878 ldr r0, [r7, #4]
|
|
80082b8: f000 fbdb bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
80082bc: e055 b.n 800836a <USBD_StdEPReq+0x31a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
|
|
80082be: 7bbb ldrb r3, [r7, #14]
|
|
80082c0: f003 020f and.w r2, r3, #15
|
|
80082c4: 6879 ldr r1, [r7, #4]
|
|
80082c6: 4613 mov r3, r2
|
|
80082c8: 009b lsls r3, r3, #2
|
|
80082ca: 4413 add r3, r2
|
|
80082cc: 009b lsls r3, r3, #2
|
|
80082ce: 440b add r3, r1
|
|
80082d0: f203 1363 addw r3, r3, #355 @ 0x163
|
|
80082d4: 781b ldrb r3, [r3, #0]
|
|
80082d6: 2b00 cmp r3, #0
|
|
80082d8: d104 bne.n 80082e4 <USBD_StdEPReq+0x294>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80082da: 6839 ldr r1, [r7, #0]
|
|
80082dc: 6878 ldr r0, [r7, #4]
|
|
80082de: f000 fbc8 bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
80082e2: e042 b.n 800836a <USBD_StdEPReq+0x31a>
|
|
}
|
|
}
|
|
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
80082e4: f997 300e ldrsb.w r3, [r7, #14]
|
|
80082e8: 2b00 cmp r3, #0
|
|
80082ea: da0b bge.n 8008304 <USBD_StdEPReq+0x2b4>
|
|
80082ec: 7bbb ldrb r3, [r7, #14]
|
|
80082ee: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
80082f2: 4613 mov r3, r2
|
|
80082f4: 009b lsls r3, r3, #2
|
|
80082f6: 4413 add r3, r2
|
|
80082f8: 009b lsls r3, r3, #2
|
|
80082fa: 3310 adds r3, #16
|
|
80082fc: 687a ldr r2, [r7, #4]
|
|
80082fe: 4413 add r3, r2
|
|
8008300: 3304 adds r3, #4
|
|
8008302: e00b b.n 800831c <USBD_StdEPReq+0x2cc>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
8008304: 7bbb ldrb r3, [r7, #14]
|
|
8008306: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
800830a: 4613 mov r3, r2
|
|
800830c: 009b lsls r3, r3, #2
|
|
800830e: 4413 add r3, r2
|
|
8008310: 009b lsls r3, r3, #2
|
|
8008312: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8008316: 687a ldr r2, [r7, #4]
|
|
8008318: 4413 add r3, r2
|
|
800831a: 3304 adds r3, #4
|
|
800831c: 60bb str r3, [r7, #8]
|
|
|
|
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
|
|
800831e: 7bbb ldrb r3, [r7, #14]
|
|
8008320: 2b00 cmp r3, #0
|
|
8008322: d002 beq.n 800832a <USBD_StdEPReq+0x2da>
|
|
8008324: 7bbb ldrb r3, [r7, #14]
|
|
8008326: 2b80 cmp r3, #128 @ 0x80
|
|
8008328: d103 bne.n 8008332 <USBD_StdEPReq+0x2e2>
|
|
{
|
|
pep->status = 0x0000U;
|
|
800832a: 68bb ldr r3, [r7, #8]
|
|
800832c: 2200 movs r2, #0
|
|
800832e: 739a strb r2, [r3, #14]
|
|
8008330: e00e b.n 8008350 <USBD_StdEPReq+0x300>
|
|
}
|
|
else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U)
|
|
8008332: 7bbb ldrb r3, [r7, #14]
|
|
8008334: 4619 mov r1, r3
|
|
8008336: 6878 ldr r0, [r7, #4]
|
|
8008338: f001 f80c bl 8009354 <USBD_LL_IsStallEP>
|
|
800833c: 4603 mov r3, r0
|
|
800833e: 2b00 cmp r3, #0
|
|
8008340: d003 beq.n 800834a <USBD_StdEPReq+0x2fa>
|
|
{
|
|
pep->status = 0x0001U;
|
|
8008342: 68bb ldr r3, [r7, #8]
|
|
8008344: 2201 movs r2, #1
|
|
8008346: 739a strb r2, [r3, #14]
|
|
8008348: e002 b.n 8008350 <USBD_StdEPReq+0x300>
|
|
}
|
|
else
|
|
{
|
|
pep->status = 0x0000U;
|
|
800834a: 68bb ldr r3, [r7, #8]
|
|
800834c: 2200 movs r2, #0
|
|
800834e: 739a strb r2, [r3, #14]
|
|
}
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
|
|
8008350: 68bb ldr r3, [r7, #8]
|
|
8008352: 330e adds r3, #14
|
|
8008354: 2202 movs r2, #2
|
|
8008356: 4619 mov r1, r3
|
|
8008358: 6878 ldr r0, [r7, #4]
|
|
800835a: f000 fc07 bl 8008b6c <USBD_CtlSendData>
|
|
break;
|
|
800835e: e004 b.n 800836a <USBD_StdEPReq+0x31a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008360: 6839 ldr r1, [r7, #0]
|
|
8008362: 6878 ldr r0, [r7, #4]
|
|
8008364: f000 fb85 bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
8008368: bf00 nop
|
|
}
|
|
break;
|
|
800836a: e004 b.n 8008376 <USBD_StdEPReq+0x326>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800836c: 6839 ldr r1, [r7, #0]
|
|
800836e: 6878 ldr r0, [r7, #4]
|
|
8008370: f000 fb7f bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
8008374: bf00 nop
|
|
}
|
|
break;
|
|
8008376: e005 b.n 8008384 <USBD_StdEPReq+0x334>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008378: 6839 ldr r1, [r7, #0]
|
|
800837a: 6878 ldr r0, [r7, #4]
|
|
800837c: f000 fb79 bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
8008380: e000 b.n 8008384 <USBD_StdEPReq+0x334>
|
|
break;
|
|
8008382: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8008384: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008386: 4618 mov r0, r3
|
|
8008388: 3710 adds r7, #16
|
|
800838a: 46bd mov sp, r7
|
|
800838c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08008390 <USBD_GetDescriptor>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008390: b580 push {r7, lr}
|
|
8008392: b084 sub sp, #16
|
|
8008394: af00 add r7, sp, #0
|
|
8008396: 6078 str r0, [r7, #4]
|
|
8008398: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
800839a: 2300 movs r3, #0
|
|
800839c: 813b strh r3, [r7, #8]
|
|
uint8_t *pbuf = NULL;
|
|
800839e: 2300 movs r3, #0
|
|
80083a0: 60fb str r3, [r7, #12]
|
|
uint8_t err = 0U;
|
|
80083a2: 2300 movs r3, #0
|
|
80083a4: 72fb strb r3, [r7, #11]
|
|
|
|
switch (req->wValue >> 8)
|
|
80083a6: 683b ldr r3, [r7, #0]
|
|
80083a8: 885b ldrh r3, [r3, #2]
|
|
80083aa: 0a1b lsrs r3, r3, #8
|
|
80083ac: b29b uxth r3, r3
|
|
80083ae: 3b01 subs r3, #1
|
|
80083b0: 2b0e cmp r3, #14
|
|
80083b2: f200 8152 bhi.w 800865a <USBD_GetDescriptor+0x2ca>
|
|
80083b6: a201 add r2, pc, #4 @ (adr r2, 80083bc <USBD_GetDescriptor+0x2c>)
|
|
80083b8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80083bc: 0800842d .word 0x0800842d
|
|
80083c0: 08008445 .word 0x08008445
|
|
80083c4: 08008485 .word 0x08008485
|
|
80083c8: 0800865b .word 0x0800865b
|
|
80083cc: 0800865b .word 0x0800865b
|
|
80083d0: 080085fb .word 0x080085fb
|
|
80083d4: 08008627 .word 0x08008627
|
|
80083d8: 0800865b .word 0x0800865b
|
|
80083dc: 0800865b .word 0x0800865b
|
|
80083e0: 0800865b .word 0x0800865b
|
|
80083e4: 0800865b .word 0x0800865b
|
|
80083e8: 0800865b .word 0x0800865b
|
|
80083ec: 0800865b .word 0x0800865b
|
|
80083f0: 0800865b .word 0x0800865b
|
|
80083f4: 080083f9 .word 0x080083f9
|
|
{
|
|
#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U))
|
|
case USB_DESC_TYPE_BOS:
|
|
if (pdev->pDesc->GetBOSDescriptor != NULL)
|
|
80083f8: 687b ldr r3, [r7, #4]
|
|
80083fa: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80083fe: 69db ldr r3, [r3, #28]
|
|
8008400: 2b00 cmp r3, #0
|
|
8008402: d00b beq.n 800841c <USBD_GetDescriptor+0x8c>
|
|
{
|
|
pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
|
|
8008404: 687b ldr r3, [r7, #4]
|
|
8008406: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800840a: 69db ldr r3, [r3, #28]
|
|
800840c: 687a ldr r2, [r7, #4]
|
|
800840e: 7c12 ldrb r2, [r2, #16]
|
|
8008410: f107 0108 add.w r1, r7, #8
|
|
8008414: 4610 mov r0, r2
|
|
8008416: 4798 blx r3
|
|
8008418: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800841a: e126 b.n 800866a <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
800841c: 6839 ldr r1, [r7, #0]
|
|
800841e: 6878 ldr r0, [r7, #4]
|
|
8008420: f000 fb27 bl 8008a72 <USBD_CtlError>
|
|
err++;
|
|
8008424: 7afb ldrb r3, [r7, #11]
|
|
8008426: 3301 adds r3, #1
|
|
8008428: 72fb strb r3, [r7, #11]
|
|
break;
|
|
800842a: e11e b.n 800866a <USBD_GetDescriptor+0x2da>
|
|
#endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */
|
|
case USB_DESC_TYPE_DEVICE:
|
|
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
|
|
800842c: 687b ldr r3, [r7, #4]
|
|
800842e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008432: 681b ldr r3, [r3, #0]
|
|
8008434: 687a ldr r2, [r7, #4]
|
|
8008436: 7c12 ldrb r2, [r2, #16]
|
|
8008438: f107 0108 add.w r1, r7, #8
|
|
800843c: 4610 mov r0, r2
|
|
800843e: 4798 blx r3
|
|
8008440: 60f8 str r0, [r7, #12]
|
|
break;
|
|
8008442: e112 b.n 800866a <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8008444: 687b ldr r3, [r7, #4]
|
|
8008446: 7c1b ldrb r3, [r3, #16]
|
|
8008448: 2b00 cmp r3, #0
|
|
800844a: d10d bne.n 8008468 <USBD_GetDescriptor+0xd8>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len);
|
|
800844c: 687b ldr r3, [r7, #4]
|
|
800844e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008452: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8008454: f107 0208 add.w r2, r7, #8
|
|
8008458: 4610 mov r0, r2
|
|
800845a: 4798 blx r3
|
|
800845c: 60f8 str r0, [r7, #12]
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
800845e: 68fb ldr r3, [r7, #12]
|
|
8008460: 3301 adds r3, #1
|
|
8008462: 2202 movs r2, #2
|
|
8008464: 701a strb r2, [r3, #0]
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
}
|
|
break;
|
|
8008466: e100 b.n 800866a <USBD_GetDescriptor+0x2da>
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
|
|
8008468: 687b ldr r3, [r7, #4]
|
|
800846a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
800846e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8008470: f107 0208 add.w r2, r7, #8
|
|
8008474: 4610 mov r0, r2
|
|
8008476: 4798 blx r3
|
|
8008478: 60f8 str r0, [r7, #12]
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
800847a: 68fb ldr r3, [r7, #12]
|
|
800847c: 3301 adds r3, #1
|
|
800847e: 2202 movs r2, #2
|
|
8008480: 701a strb r2, [r3, #0]
|
|
break;
|
|
8008482: e0f2 b.n 800866a <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_STRING:
|
|
switch ((uint8_t)(req->wValue))
|
|
8008484: 683b ldr r3, [r7, #0]
|
|
8008486: 885b ldrh r3, [r3, #2]
|
|
8008488: b2db uxtb r3, r3
|
|
800848a: 2b05 cmp r3, #5
|
|
800848c: f200 80ac bhi.w 80085e8 <USBD_GetDescriptor+0x258>
|
|
8008490: a201 add r2, pc, #4 @ (adr r2, 8008498 <USBD_GetDescriptor+0x108>)
|
|
8008492: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8008496: bf00 nop
|
|
8008498: 080084b1 .word 0x080084b1
|
|
800849c: 080084e5 .word 0x080084e5
|
|
80084a0: 08008519 .word 0x08008519
|
|
80084a4: 0800854d .word 0x0800854d
|
|
80084a8: 08008581 .word 0x08008581
|
|
80084ac: 080085b5 .word 0x080085b5
|
|
{
|
|
case USBD_IDX_LANGID_STR:
|
|
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
|
|
80084b0: 687b ldr r3, [r7, #4]
|
|
80084b2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80084b6: 685b ldr r3, [r3, #4]
|
|
80084b8: 2b00 cmp r3, #0
|
|
80084ba: d00b beq.n 80084d4 <USBD_GetDescriptor+0x144>
|
|
{
|
|
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
|
|
80084bc: 687b ldr r3, [r7, #4]
|
|
80084be: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80084c2: 685b ldr r3, [r3, #4]
|
|
80084c4: 687a ldr r2, [r7, #4]
|
|
80084c6: 7c12 ldrb r2, [r2, #16]
|
|
80084c8: f107 0108 add.w r1, r7, #8
|
|
80084cc: 4610 mov r0, r2
|
|
80084ce: 4798 blx r3
|
|
80084d0: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80084d2: e091 b.n 80085f8 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
80084d4: 6839 ldr r1, [r7, #0]
|
|
80084d6: 6878 ldr r0, [r7, #4]
|
|
80084d8: f000 facb bl 8008a72 <USBD_CtlError>
|
|
err++;
|
|
80084dc: 7afb ldrb r3, [r7, #11]
|
|
80084de: 3301 adds r3, #1
|
|
80084e0: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80084e2: e089 b.n 80085f8 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_MFC_STR:
|
|
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
|
|
80084e4: 687b ldr r3, [r7, #4]
|
|
80084e6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80084ea: 689b ldr r3, [r3, #8]
|
|
80084ec: 2b00 cmp r3, #0
|
|
80084ee: d00b beq.n 8008508 <USBD_GetDescriptor+0x178>
|
|
{
|
|
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
|
|
80084f0: 687b ldr r3, [r7, #4]
|
|
80084f2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80084f6: 689b ldr r3, [r3, #8]
|
|
80084f8: 687a ldr r2, [r7, #4]
|
|
80084fa: 7c12 ldrb r2, [r2, #16]
|
|
80084fc: f107 0108 add.w r1, r7, #8
|
|
8008500: 4610 mov r0, r2
|
|
8008502: 4798 blx r3
|
|
8008504: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8008506: e077 b.n 80085f8 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8008508: 6839 ldr r1, [r7, #0]
|
|
800850a: 6878 ldr r0, [r7, #4]
|
|
800850c: f000 fab1 bl 8008a72 <USBD_CtlError>
|
|
err++;
|
|
8008510: 7afb ldrb r3, [r7, #11]
|
|
8008512: 3301 adds r3, #1
|
|
8008514: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8008516: e06f b.n 80085f8 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_PRODUCT_STR:
|
|
if (pdev->pDesc->GetProductStrDescriptor != NULL)
|
|
8008518: 687b ldr r3, [r7, #4]
|
|
800851a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800851e: 68db ldr r3, [r3, #12]
|
|
8008520: 2b00 cmp r3, #0
|
|
8008522: d00b beq.n 800853c <USBD_GetDescriptor+0x1ac>
|
|
{
|
|
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
|
|
8008524: 687b ldr r3, [r7, #4]
|
|
8008526: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800852a: 68db ldr r3, [r3, #12]
|
|
800852c: 687a ldr r2, [r7, #4]
|
|
800852e: 7c12 ldrb r2, [r2, #16]
|
|
8008530: f107 0108 add.w r1, r7, #8
|
|
8008534: 4610 mov r0, r2
|
|
8008536: 4798 blx r3
|
|
8008538: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800853a: e05d b.n 80085f8 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
800853c: 6839 ldr r1, [r7, #0]
|
|
800853e: 6878 ldr r0, [r7, #4]
|
|
8008540: f000 fa97 bl 8008a72 <USBD_CtlError>
|
|
err++;
|
|
8008544: 7afb ldrb r3, [r7, #11]
|
|
8008546: 3301 adds r3, #1
|
|
8008548: 72fb strb r3, [r7, #11]
|
|
break;
|
|
800854a: e055 b.n 80085f8 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_SERIAL_STR:
|
|
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
|
|
800854c: 687b ldr r3, [r7, #4]
|
|
800854e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008552: 691b ldr r3, [r3, #16]
|
|
8008554: 2b00 cmp r3, #0
|
|
8008556: d00b beq.n 8008570 <USBD_GetDescriptor+0x1e0>
|
|
{
|
|
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
|
|
8008558: 687b ldr r3, [r7, #4]
|
|
800855a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800855e: 691b ldr r3, [r3, #16]
|
|
8008560: 687a ldr r2, [r7, #4]
|
|
8008562: 7c12 ldrb r2, [r2, #16]
|
|
8008564: f107 0108 add.w r1, r7, #8
|
|
8008568: 4610 mov r0, r2
|
|
800856a: 4798 blx r3
|
|
800856c: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800856e: e043 b.n 80085f8 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8008570: 6839 ldr r1, [r7, #0]
|
|
8008572: 6878 ldr r0, [r7, #4]
|
|
8008574: f000 fa7d bl 8008a72 <USBD_CtlError>
|
|
err++;
|
|
8008578: 7afb ldrb r3, [r7, #11]
|
|
800857a: 3301 adds r3, #1
|
|
800857c: 72fb strb r3, [r7, #11]
|
|
break;
|
|
800857e: e03b b.n 80085f8 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_CONFIG_STR:
|
|
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
|
|
8008580: 687b ldr r3, [r7, #4]
|
|
8008582: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008586: 695b ldr r3, [r3, #20]
|
|
8008588: 2b00 cmp r3, #0
|
|
800858a: d00b beq.n 80085a4 <USBD_GetDescriptor+0x214>
|
|
{
|
|
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
|
|
800858c: 687b ldr r3, [r7, #4]
|
|
800858e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008592: 695b ldr r3, [r3, #20]
|
|
8008594: 687a ldr r2, [r7, #4]
|
|
8008596: 7c12 ldrb r2, [r2, #16]
|
|
8008598: f107 0108 add.w r1, r7, #8
|
|
800859c: 4610 mov r0, r2
|
|
800859e: 4798 blx r3
|
|
80085a0: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80085a2: e029 b.n 80085f8 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
80085a4: 6839 ldr r1, [r7, #0]
|
|
80085a6: 6878 ldr r0, [r7, #4]
|
|
80085a8: f000 fa63 bl 8008a72 <USBD_CtlError>
|
|
err++;
|
|
80085ac: 7afb ldrb r3, [r7, #11]
|
|
80085ae: 3301 adds r3, #1
|
|
80085b0: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80085b2: e021 b.n 80085f8 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_INTERFACE_STR:
|
|
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
|
|
80085b4: 687b ldr r3, [r7, #4]
|
|
80085b6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80085ba: 699b ldr r3, [r3, #24]
|
|
80085bc: 2b00 cmp r3, #0
|
|
80085be: d00b beq.n 80085d8 <USBD_GetDescriptor+0x248>
|
|
{
|
|
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
|
|
80085c0: 687b ldr r3, [r7, #4]
|
|
80085c2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80085c6: 699b ldr r3, [r3, #24]
|
|
80085c8: 687a ldr r2, [r7, #4]
|
|
80085ca: 7c12 ldrb r2, [r2, #16]
|
|
80085cc: f107 0108 add.w r1, r7, #8
|
|
80085d0: 4610 mov r0, r2
|
|
80085d2: 4798 blx r3
|
|
80085d4: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80085d6: e00f b.n 80085f8 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
80085d8: 6839 ldr r1, [r7, #0]
|
|
80085da: 6878 ldr r0, [r7, #4]
|
|
80085dc: f000 fa49 bl 8008a72 <USBD_CtlError>
|
|
err++;
|
|
80085e0: 7afb ldrb r3, [r7, #11]
|
|
80085e2: 3301 adds r3, #1
|
|
80085e4: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80085e6: e007 b.n 80085f8 <USBD_GetDescriptor+0x268>
|
|
err++;
|
|
}
|
|
#endif /* USBD_SUPPORT_USER_STRING_DESC */
|
|
|
|
#if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U))
|
|
USBD_CtlError(pdev, req);
|
|
80085e8: 6839 ldr r1, [r7, #0]
|
|
80085ea: 6878 ldr r0, [r7, #4]
|
|
80085ec: f000 fa41 bl 8008a72 <USBD_CtlError>
|
|
err++;
|
|
80085f0: 7afb ldrb r3, [r7, #11]
|
|
80085f2: 3301 adds r3, #1
|
|
80085f4: 72fb strb r3, [r7, #11]
|
|
#endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */
|
|
break;
|
|
80085f6: bf00 nop
|
|
}
|
|
break;
|
|
80085f8: e037 b.n 800866a <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_DEVICE_QUALIFIER:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
80085fa: 687b ldr r3, [r7, #4]
|
|
80085fc: 7c1b ldrb r3, [r3, #16]
|
|
80085fe: 2b00 cmp r3, #0
|
|
8008600: d109 bne.n 8008616 <USBD_GetDescriptor+0x286>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len);
|
|
8008602: 687b ldr r3, [r7, #4]
|
|
8008604: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008608: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800860a: f107 0208 add.w r2, r7, #8
|
|
800860e: 4610 mov r0, r2
|
|
8008610: 4798 blx r3
|
|
8008612: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8008614: e029 b.n 800866a <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
8008616: 6839 ldr r1, [r7, #0]
|
|
8008618: 6878 ldr r0, [r7, #4]
|
|
800861a: f000 fa2a bl 8008a72 <USBD_CtlError>
|
|
err++;
|
|
800861e: 7afb ldrb r3, [r7, #11]
|
|
8008620: 3301 adds r3, #1
|
|
8008622: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8008624: e021 b.n 800866a <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8008626: 687b ldr r3, [r7, #4]
|
|
8008628: 7c1b ldrb r3, [r3, #16]
|
|
800862a: 2b00 cmp r3, #0
|
|
800862c: d10d bne.n 800864a <USBD_GetDescriptor+0x2ba>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len);
|
|
800862e: 687b ldr r3, [r7, #4]
|
|
8008630: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008634: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8008636: f107 0208 add.w r2, r7, #8
|
|
800863a: 4610 mov r0, r2
|
|
800863c: 4798 blx r3
|
|
800863e: 60f8 str r0, [r7, #12]
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
|
|
8008640: 68fb ldr r3, [r7, #12]
|
|
8008642: 3301 adds r3, #1
|
|
8008644: 2207 movs r2, #7
|
|
8008646: 701a strb r2, [r3, #0]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8008648: e00f b.n 800866a <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
800864a: 6839 ldr r1, [r7, #0]
|
|
800864c: 6878 ldr r0, [r7, #4]
|
|
800864e: f000 fa10 bl 8008a72 <USBD_CtlError>
|
|
err++;
|
|
8008652: 7afb ldrb r3, [r7, #11]
|
|
8008654: 3301 adds r3, #1
|
|
8008656: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8008658: e007 b.n 800866a <USBD_GetDescriptor+0x2da>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800865a: 6839 ldr r1, [r7, #0]
|
|
800865c: 6878 ldr r0, [r7, #4]
|
|
800865e: f000 fa08 bl 8008a72 <USBD_CtlError>
|
|
err++;
|
|
8008662: 7afb ldrb r3, [r7, #11]
|
|
8008664: 3301 adds r3, #1
|
|
8008666: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8008668: bf00 nop
|
|
}
|
|
|
|
if (err != 0U)
|
|
800866a: 7afb ldrb r3, [r7, #11]
|
|
800866c: 2b00 cmp r3, #0
|
|
800866e: d11e bne.n 80086ae <USBD_GetDescriptor+0x31e>
|
|
{
|
|
return;
|
|
}
|
|
|
|
if (req->wLength != 0U)
|
|
8008670: 683b ldr r3, [r7, #0]
|
|
8008672: 88db ldrh r3, [r3, #6]
|
|
8008674: 2b00 cmp r3, #0
|
|
8008676: d016 beq.n 80086a6 <USBD_GetDescriptor+0x316>
|
|
{
|
|
if (len != 0U)
|
|
8008678: 893b ldrh r3, [r7, #8]
|
|
800867a: 2b00 cmp r3, #0
|
|
800867c: d00e beq.n 800869c <USBD_GetDescriptor+0x30c>
|
|
{
|
|
len = MIN(len, req->wLength);
|
|
800867e: 683b ldr r3, [r7, #0]
|
|
8008680: 88da ldrh r2, [r3, #6]
|
|
8008682: 893b ldrh r3, [r7, #8]
|
|
8008684: 4293 cmp r3, r2
|
|
8008686: bf28 it cs
|
|
8008688: 4613 movcs r3, r2
|
|
800868a: b29b uxth r3, r3
|
|
800868c: 813b strh r3, [r7, #8]
|
|
(void)USBD_CtlSendData(pdev, pbuf, len);
|
|
800868e: 893b ldrh r3, [r7, #8]
|
|
8008690: 461a mov r2, r3
|
|
8008692: 68f9 ldr r1, [r7, #12]
|
|
8008694: 6878 ldr r0, [r7, #4]
|
|
8008696: f000 fa69 bl 8008b6c <USBD_CtlSendData>
|
|
800869a: e009 b.n 80086b0 <USBD_GetDescriptor+0x320>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
800869c: 6839 ldr r1, [r7, #0]
|
|
800869e: 6878 ldr r0, [r7, #4]
|
|
80086a0: f000 f9e7 bl 8008a72 <USBD_CtlError>
|
|
80086a4: e004 b.n 80086b0 <USBD_GetDescriptor+0x320>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80086a6: 6878 ldr r0, [r7, #4]
|
|
80086a8: f000 faa0 bl 8008bec <USBD_CtlSendStatus>
|
|
80086ac: e000 b.n 80086b0 <USBD_GetDescriptor+0x320>
|
|
return;
|
|
80086ae: bf00 nop
|
|
}
|
|
}
|
|
80086b0: 3710 adds r7, #16
|
|
80086b2: 46bd mov sp, r7
|
|
80086b4: bd80 pop {r7, pc}
|
|
80086b6: bf00 nop
|
|
|
|
080086b8 <USBD_SetAddress>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
80086b8: b580 push {r7, lr}
|
|
80086ba: b084 sub sp, #16
|
|
80086bc: af00 add r7, sp, #0
|
|
80086be: 6078 str r0, [r7, #4]
|
|
80086c0: 6039 str r1, [r7, #0]
|
|
uint8_t dev_addr;
|
|
|
|
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
|
|
80086c2: 683b ldr r3, [r7, #0]
|
|
80086c4: 889b ldrh r3, [r3, #4]
|
|
80086c6: 2b00 cmp r3, #0
|
|
80086c8: d131 bne.n 800872e <USBD_SetAddress+0x76>
|
|
80086ca: 683b ldr r3, [r7, #0]
|
|
80086cc: 88db ldrh r3, [r3, #6]
|
|
80086ce: 2b00 cmp r3, #0
|
|
80086d0: d12d bne.n 800872e <USBD_SetAddress+0x76>
|
|
80086d2: 683b ldr r3, [r7, #0]
|
|
80086d4: 885b ldrh r3, [r3, #2]
|
|
80086d6: 2b7f cmp r3, #127 @ 0x7f
|
|
80086d8: d829 bhi.n 800872e <USBD_SetAddress+0x76>
|
|
{
|
|
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
|
|
80086da: 683b ldr r3, [r7, #0]
|
|
80086dc: 885b ldrh r3, [r3, #2]
|
|
80086de: b2db uxtb r3, r3
|
|
80086e0: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
80086e4: 73fb strb r3, [r7, #15]
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80086e6: 687b ldr r3, [r7, #4]
|
|
80086e8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80086ec: b2db uxtb r3, r3
|
|
80086ee: 2b03 cmp r3, #3
|
|
80086f0: d104 bne.n 80086fc <USBD_SetAddress+0x44>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80086f2: 6839 ldr r1, [r7, #0]
|
|
80086f4: 6878 ldr r0, [r7, #4]
|
|
80086f6: f000 f9bc bl 8008a72 <USBD_CtlError>
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80086fa: e01d b.n 8008738 <USBD_SetAddress+0x80>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_address = dev_addr;
|
|
80086fc: 687b ldr r3, [r7, #4]
|
|
80086fe: 7bfa ldrb r2, [r7, #15]
|
|
8008700: f883 229e strb.w r2, [r3, #670] @ 0x29e
|
|
(void)USBD_LL_SetUSBAddress(pdev, dev_addr);
|
|
8008704: 7bfb ldrb r3, [r7, #15]
|
|
8008706: 4619 mov r1, r3
|
|
8008708: 6878 ldr r0, [r7, #4]
|
|
800870a: f000 fe4f bl 80093ac <USBD_LL_SetUSBAddress>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800870e: 6878 ldr r0, [r7, #4]
|
|
8008710: f000 fa6c bl 8008bec <USBD_CtlSendStatus>
|
|
|
|
if (dev_addr != 0U)
|
|
8008714: 7bfb ldrb r3, [r7, #15]
|
|
8008716: 2b00 cmp r3, #0
|
|
8008718: d004 beq.n 8008724 <USBD_SetAddress+0x6c>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
800871a: 687b ldr r3, [r7, #4]
|
|
800871c: 2202 movs r2, #2
|
|
800871e: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008722: e009 b.n 8008738 <USBD_SetAddress+0x80>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8008724: 687b ldr r3, [r7, #4]
|
|
8008726: 2201 movs r2, #1
|
|
8008728: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
800872c: e004 b.n 8008738 <USBD_SetAddress+0x80>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
800872e: 6839 ldr r1, [r7, #0]
|
|
8008730: 6878 ldr r0, [r7, #4]
|
|
8008732: f000 f99e bl 8008a72 <USBD_CtlError>
|
|
}
|
|
}
|
|
8008736: bf00 nop
|
|
8008738: bf00 nop
|
|
800873a: 3710 adds r7, #16
|
|
800873c: 46bd mov sp, r7
|
|
800873e: bd80 pop {r7, pc}
|
|
|
|
08008740 <USBD_SetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008740: b580 push {r7, lr}
|
|
8008742: b084 sub sp, #16
|
|
8008744: af00 add r7, sp, #0
|
|
8008746: 6078 str r0, [r7, #4]
|
|
8008748: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
800874a: 2300 movs r3, #0
|
|
800874c: 73fb strb r3, [r7, #15]
|
|
static uint8_t cfgidx;
|
|
|
|
cfgidx = (uint8_t)(req->wValue);
|
|
800874e: 683b ldr r3, [r7, #0]
|
|
8008750: 885b ldrh r3, [r3, #2]
|
|
8008752: b2da uxtb r2, r3
|
|
8008754: 4b4e ldr r3, [pc, #312] @ (8008890 <USBD_SetConfig+0x150>)
|
|
8008756: 701a strb r2, [r3, #0]
|
|
|
|
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
|
|
8008758: 4b4d ldr r3, [pc, #308] @ (8008890 <USBD_SetConfig+0x150>)
|
|
800875a: 781b ldrb r3, [r3, #0]
|
|
800875c: 2b01 cmp r3, #1
|
|
800875e: d905 bls.n 800876c <USBD_SetConfig+0x2c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008760: 6839 ldr r1, [r7, #0]
|
|
8008762: 6878 ldr r0, [r7, #4]
|
|
8008764: f000 f985 bl 8008a72 <USBD_CtlError>
|
|
return USBD_FAIL;
|
|
8008768: 2303 movs r3, #3
|
|
800876a: e08c b.n 8008886 <USBD_SetConfig+0x146>
|
|
}
|
|
|
|
switch (pdev->dev_state)
|
|
800876c: 687b ldr r3, [r7, #4]
|
|
800876e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008772: b2db uxtb r3, r3
|
|
8008774: 2b02 cmp r3, #2
|
|
8008776: d002 beq.n 800877e <USBD_SetConfig+0x3e>
|
|
8008778: 2b03 cmp r3, #3
|
|
800877a: d029 beq.n 80087d0 <USBD_SetConfig+0x90>
|
|
800877c: e075 b.n 800886a <USBD_SetConfig+0x12a>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if (cfgidx != 0U)
|
|
800877e: 4b44 ldr r3, [pc, #272] @ (8008890 <USBD_SetConfig+0x150>)
|
|
8008780: 781b ldrb r3, [r3, #0]
|
|
8008782: 2b00 cmp r3, #0
|
|
8008784: d020 beq.n 80087c8 <USBD_SetConfig+0x88>
|
|
{
|
|
pdev->dev_config = cfgidx;
|
|
8008786: 4b42 ldr r3, [pc, #264] @ (8008890 <USBD_SetConfig+0x150>)
|
|
8008788: 781b ldrb r3, [r3, #0]
|
|
800878a: 461a mov r2, r3
|
|
800878c: 687b ldr r3, [r7, #4]
|
|
800878e: 605a str r2, [r3, #4]
|
|
|
|
ret = USBD_SetClassConfig(pdev, cfgidx);
|
|
8008790: 4b3f ldr r3, [pc, #252] @ (8008890 <USBD_SetConfig+0x150>)
|
|
8008792: 781b ldrb r3, [r3, #0]
|
|
8008794: 4619 mov r1, r3
|
|
8008796: 6878 ldr r0, [r7, #4]
|
|
8008798: f7fe ffa3 bl 80076e2 <USBD_SetClassConfig>
|
|
800879c: 4603 mov r3, r0
|
|
800879e: 73fb strb r3, [r7, #15]
|
|
|
|
if (ret != USBD_OK)
|
|
80087a0: 7bfb ldrb r3, [r7, #15]
|
|
80087a2: 2b00 cmp r3, #0
|
|
80087a4: d008 beq.n 80087b8 <USBD_SetConfig+0x78>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80087a6: 6839 ldr r1, [r7, #0]
|
|
80087a8: 6878 ldr r0, [r7, #4]
|
|
80087aa: f000 f962 bl 8008a72 <USBD_CtlError>
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
80087ae: 687b ldr r3, [r7, #4]
|
|
80087b0: 2202 movs r2, #2
|
|
80087b2: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
80087b6: e065 b.n 8008884 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80087b8: 6878 ldr r0, [r7, #4]
|
|
80087ba: f000 fa17 bl 8008bec <USBD_CtlSendStatus>
|
|
pdev->dev_state = USBD_STATE_CONFIGURED;
|
|
80087be: 687b ldr r3, [r7, #4]
|
|
80087c0: 2203 movs r2, #3
|
|
80087c2: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
break;
|
|
80087c6: e05d b.n 8008884 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80087c8: 6878 ldr r0, [r7, #4]
|
|
80087ca: f000 fa0f bl 8008bec <USBD_CtlSendStatus>
|
|
break;
|
|
80087ce: e059 b.n 8008884 <USBD_SetConfig+0x144>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (cfgidx == 0U)
|
|
80087d0: 4b2f ldr r3, [pc, #188] @ (8008890 <USBD_SetConfig+0x150>)
|
|
80087d2: 781b ldrb r3, [r3, #0]
|
|
80087d4: 2b00 cmp r3, #0
|
|
80087d6: d112 bne.n 80087fe <USBD_SetConfig+0xbe>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
80087d8: 687b ldr r3, [r7, #4]
|
|
80087da: 2202 movs r2, #2
|
|
80087dc: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->dev_config = cfgidx;
|
|
80087e0: 4b2b ldr r3, [pc, #172] @ (8008890 <USBD_SetConfig+0x150>)
|
|
80087e2: 781b ldrb r3, [r3, #0]
|
|
80087e4: 461a mov r2, r3
|
|
80087e6: 687b ldr r3, [r7, #4]
|
|
80087e8: 605a str r2, [r3, #4]
|
|
(void)USBD_ClrClassConfig(pdev, cfgidx);
|
|
80087ea: 4b29 ldr r3, [pc, #164] @ (8008890 <USBD_SetConfig+0x150>)
|
|
80087ec: 781b ldrb r3, [r3, #0]
|
|
80087ee: 4619 mov r1, r3
|
|
80087f0: 6878 ldr r0, [r7, #4]
|
|
80087f2: f7fe ff92 bl 800771a <USBD_ClrClassConfig>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80087f6: 6878 ldr r0, [r7, #4]
|
|
80087f8: f000 f9f8 bl 8008bec <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
80087fc: e042 b.n 8008884 <USBD_SetConfig+0x144>
|
|
else if (cfgidx != pdev->dev_config)
|
|
80087fe: 4b24 ldr r3, [pc, #144] @ (8008890 <USBD_SetConfig+0x150>)
|
|
8008800: 781b ldrb r3, [r3, #0]
|
|
8008802: 461a mov r2, r3
|
|
8008804: 687b ldr r3, [r7, #4]
|
|
8008806: 685b ldr r3, [r3, #4]
|
|
8008808: 429a cmp r2, r3
|
|
800880a: d02a beq.n 8008862 <USBD_SetConfig+0x122>
|
|
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
800880c: 687b ldr r3, [r7, #4]
|
|
800880e: 685b ldr r3, [r3, #4]
|
|
8008810: b2db uxtb r3, r3
|
|
8008812: 4619 mov r1, r3
|
|
8008814: 6878 ldr r0, [r7, #4]
|
|
8008816: f7fe ff80 bl 800771a <USBD_ClrClassConfig>
|
|
pdev->dev_config = cfgidx;
|
|
800881a: 4b1d ldr r3, [pc, #116] @ (8008890 <USBD_SetConfig+0x150>)
|
|
800881c: 781b ldrb r3, [r3, #0]
|
|
800881e: 461a mov r2, r3
|
|
8008820: 687b ldr r3, [r7, #4]
|
|
8008822: 605a str r2, [r3, #4]
|
|
ret = USBD_SetClassConfig(pdev, cfgidx);
|
|
8008824: 4b1a ldr r3, [pc, #104] @ (8008890 <USBD_SetConfig+0x150>)
|
|
8008826: 781b ldrb r3, [r3, #0]
|
|
8008828: 4619 mov r1, r3
|
|
800882a: 6878 ldr r0, [r7, #4]
|
|
800882c: f7fe ff59 bl 80076e2 <USBD_SetClassConfig>
|
|
8008830: 4603 mov r3, r0
|
|
8008832: 73fb strb r3, [r7, #15]
|
|
if (ret != USBD_OK)
|
|
8008834: 7bfb ldrb r3, [r7, #15]
|
|
8008836: 2b00 cmp r3, #0
|
|
8008838: d00f beq.n 800885a <USBD_SetConfig+0x11a>
|
|
USBD_CtlError(pdev, req);
|
|
800883a: 6839 ldr r1, [r7, #0]
|
|
800883c: 6878 ldr r0, [r7, #4]
|
|
800883e: f000 f918 bl 8008a72 <USBD_CtlError>
|
|
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
8008842: 687b ldr r3, [r7, #4]
|
|
8008844: 685b ldr r3, [r3, #4]
|
|
8008846: b2db uxtb r3, r3
|
|
8008848: 4619 mov r1, r3
|
|
800884a: 6878 ldr r0, [r7, #4]
|
|
800884c: f7fe ff65 bl 800771a <USBD_ClrClassConfig>
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8008850: 687b ldr r3, [r7, #4]
|
|
8008852: 2202 movs r2, #2
|
|
8008854: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
break;
|
|
8008858: e014 b.n 8008884 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800885a: 6878 ldr r0, [r7, #4]
|
|
800885c: f000 f9c6 bl 8008bec <USBD_CtlSendStatus>
|
|
break;
|
|
8008860: e010 b.n 8008884 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8008862: 6878 ldr r0, [r7, #4]
|
|
8008864: f000 f9c2 bl 8008bec <USBD_CtlSendStatus>
|
|
break;
|
|
8008868: e00c b.n 8008884 <USBD_SetConfig+0x144>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800886a: 6839 ldr r1, [r7, #0]
|
|
800886c: 6878 ldr r0, [r7, #4]
|
|
800886e: f000 f900 bl 8008a72 <USBD_CtlError>
|
|
(void)USBD_ClrClassConfig(pdev, cfgidx);
|
|
8008872: 4b07 ldr r3, [pc, #28] @ (8008890 <USBD_SetConfig+0x150>)
|
|
8008874: 781b ldrb r3, [r3, #0]
|
|
8008876: 4619 mov r1, r3
|
|
8008878: 6878 ldr r0, [r7, #4]
|
|
800887a: f7fe ff4e bl 800771a <USBD_ClrClassConfig>
|
|
ret = USBD_FAIL;
|
|
800887e: 2303 movs r3, #3
|
|
8008880: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8008882: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8008884: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008886: 4618 mov r0, r3
|
|
8008888: 3710 adds r7, #16
|
|
800888a: 46bd mov sp, r7
|
|
800888c: bd80 pop {r7, pc}
|
|
800888e: bf00 nop
|
|
8008890: 200004b4 .word 0x200004b4
|
|
|
|
08008894 <USBD_GetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008894: b580 push {r7, lr}
|
|
8008896: b082 sub sp, #8
|
|
8008898: af00 add r7, sp, #0
|
|
800889a: 6078 str r0, [r7, #4]
|
|
800889c: 6039 str r1, [r7, #0]
|
|
if (req->wLength != 1U)
|
|
800889e: 683b ldr r3, [r7, #0]
|
|
80088a0: 88db ldrh r3, [r3, #6]
|
|
80088a2: 2b01 cmp r3, #1
|
|
80088a4: d004 beq.n 80088b0 <USBD_GetConfig+0x1c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80088a6: 6839 ldr r1, [r7, #0]
|
|
80088a8: 6878 ldr r0, [r7, #4]
|
|
80088aa: f000 f8e2 bl 8008a72 <USBD_CtlError>
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
80088ae: e023 b.n 80088f8 <USBD_GetConfig+0x64>
|
|
switch (pdev->dev_state)
|
|
80088b0: 687b ldr r3, [r7, #4]
|
|
80088b2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80088b6: b2db uxtb r3, r3
|
|
80088b8: 2b02 cmp r3, #2
|
|
80088ba: dc02 bgt.n 80088c2 <USBD_GetConfig+0x2e>
|
|
80088bc: 2b00 cmp r3, #0
|
|
80088be: dc03 bgt.n 80088c8 <USBD_GetConfig+0x34>
|
|
80088c0: e015 b.n 80088ee <USBD_GetConfig+0x5a>
|
|
80088c2: 2b03 cmp r3, #3
|
|
80088c4: d00b beq.n 80088de <USBD_GetConfig+0x4a>
|
|
80088c6: e012 b.n 80088ee <USBD_GetConfig+0x5a>
|
|
pdev->dev_default_config = 0U;
|
|
80088c8: 687b ldr r3, [r7, #4]
|
|
80088ca: 2200 movs r2, #0
|
|
80088cc: 609a str r2, [r3, #8]
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
|
|
80088ce: 687b ldr r3, [r7, #4]
|
|
80088d0: 3308 adds r3, #8
|
|
80088d2: 2201 movs r2, #1
|
|
80088d4: 4619 mov r1, r3
|
|
80088d6: 6878 ldr r0, [r7, #4]
|
|
80088d8: f000 f948 bl 8008b6c <USBD_CtlSendData>
|
|
break;
|
|
80088dc: e00c b.n 80088f8 <USBD_GetConfig+0x64>
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U);
|
|
80088de: 687b ldr r3, [r7, #4]
|
|
80088e0: 3304 adds r3, #4
|
|
80088e2: 2201 movs r2, #1
|
|
80088e4: 4619 mov r1, r3
|
|
80088e6: 6878 ldr r0, [r7, #4]
|
|
80088e8: f000 f940 bl 8008b6c <USBD_CtlSendData>
|
|
break;
|
|
80088ec: e004 b.n 80088f8 <USBD_GetConfig+0x64>
|
|
USBD_CtlError(pdev, req);
|
|
80088ee: 6839 ldr r1, [r7, #0]
|
|
80088f0: 6878 ldr r0, [r7, #4]
|
|
80088f2: f000 f8be bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
80088f6: bf00 nop
|
|
}
|
|
80088f8: bf00 nop
|
|
80088fa: 3708 adds r7, #8
|
|
80088fc: 46bd mov sp, r7
|
|
80088fe: bd80 pop {r7, pc}
|
|
|
|
08008900 <USBD_GetStatus>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008900: b580 push {r7, lr}
|
|
8008902: b082 sub sp, #8
|
|
8008904: af00 add r7, sp, #0
|
|
8008906: 6078 str r0, [r7, #4]
|
|
8008908: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
800890a: 687b ldr r3, [r7, #4]
|
|
800890c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008910: b2db uxtb r3, r3
|
|
8008912: 3b01 subs r3, #1
|
|
8008914: 2b02 cmp r3, #2
|
|
8008916: d81e bhi.n 8008956 <USBD_GetStatus+0x56>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wLength != 0x2U)
|
|
8008918: 683b ldr r3, [r7, #0]
|
|
800891a: 88db ldrh r3, [r3, #6]
|
|
800891c: 2b02 cmp r3, #2
|
|
800891e: d004 beq.n 800892a <USBD_GetStatus+0x2a>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008920: 6839 ldr r1, [r7, #0]
|
|
8008922: 6878 ldr r0, [r7, #4]
|
|
8008924: f000 f8a5 bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
8008928: e01a b.n 8008960 <USBD_GetStatus+0x60>
|
|
}
|
|
|
|
#if (USBD_SELF_POWERED == 1U)
|
|
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
|
|
800892a: 687b ldr r3, [r7, #4]
|
|
800892c: 2201 movs r2, #1
|
|
800892e: 60da str r2, [r3, #12]
|
|
#else
|
|
pdev->dev_config_status = 0U;
|
|
#endif /* USBD_SELF_POWERED */
|
|
|
|
if (pdev->dev_remote_wakeup != 0U)
|
|
8008930: 687b ldr r3, [r7, #4]
|
|
8008932: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
|
|
8008936: 2b00 cmp r3, #0
|
|
8008938: d005 beq.n 8008946 <USBD_GetStatus+0x46>
|
|
{
|
|
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
|
|
800893a: 687b ldr r3, [r7, #4]
|
|
800893c: 68db ldr r3, [r3, #12]
|
|
800893e: f043 0202 orr.w r2, r3, #2
|
|
8008942: 687b ldr r3, [r7, #4]
|
|
8008944: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U);
|
|
8008946: 687b ldr r3, [r7, #4]
|
|
8008948: 330c adds r3, #12
|
|
800894a: 2202 movs r2, #2
|
|
800894c: 4619 mov r1, r3
|
|
800894e: 6878 ldr r0, [r7, #4]
|
|
8008950: f000 f90c bl 8008b6c <USBD_CtlSendData>
|
|
break;
|
|
8008954: e004 b.n 8008960 <USBD_GetStatus+0x60>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008956: 6839 ldr r1, [r7, #0]
|
|
8008958: 6878 ldr r0, [r7, #4]
|
|
800895a: f000 f88a bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
800895e: bf00 nop
|
|
}
|
|
}
|
|
8008960: bf00 nop
|
|
8008962: 3708 adds r7, #8
|
|
8008964: 46bd mov sp, r7
|
|
8008966: bd80 pop {r7, pc}
|
|
|
|
08008968 <USBD_SetFeature>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008968: b580 push {r7, lr}
|
|
800896a: b082 sub sp, #8
|
|
800896c: af00 add r7, sp, #0
|
|
800896e: 6078 str r0, [r7, #4]
|
|
8008970: 6039 str r1, [r7, #0]
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
8008972: 683b ldr r3, [r7, #0]
|
|
8008974: 885b ldrh r3, [r3, #2]
|
|
8008976: 2b01 cmp r3, #1
|
|
8008978: d107 bne.n 800898a <USBD_SetFeature+0x22>
|
|
{
|
|
pdev->dev_remote_wakeup = 1U;
|
|
800897a: 687b ldr r3, [r7, #4]
|
|
800897c: 2201 movs r2, #1
|
|
800897e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8008982: 6878 ldr r0, [r7, #4]
|
|
8008984: f000 f932 bl 8008bec <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
}
|
|
8008988: e013 b.n 80089b2 <USBD_SetFeature+0x4a>
|
|
else if (req->wValue == USB_FEATURE_TEST_MODE)
|
|
800898a: 683b ldr r3, [r7, #0]
|
|
800898c: 885b ldrh r3, [r3, #2]
|
|
800898e: 2b02 cmp r3, #2
|
|
8008990: d10b bne.n 80089aa <USBD_SetFeature+0x42>
|
|
pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8);
|
|
8008992: 683b ldr r3, [r7, #0]
|
|
8008994: 889b ldrh r3, [r3, #4]
|
|
8008996: 0a1b lsrs r3, r3, #8
|
|
8008998: b29b uxth r3, r3
|
|
800899a: b2da uxtb r2, r3
|
|
800899c: 687b ldr r3, [r7, #4]
|
|
800899e: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80089a2: 6878 ldr r0, [r7, #4]
|
|
80089a4: f000 f922 bl 8008bec <USBD_CtlSendStatus>
|
|
}
|
|
80089a8: e003 b.n 80089b2 <USBD_SetFeature+0x4a>
|
|
USBD_CtlError(pdev, req);
|
|
80089aa: 6839 ldr r1, [r7, #0]
|
|
80089ac: 6878 ldr r0, [r7, #4]
|
|
80089ae: f000 f860 bl 8008a72 <USBD_CtlError>
|
|
}
|
|
80089b2: bf00 nop
|
|
80089b4: 3708 adds r7, #8
|
|
80089b6: 46bd mov sp, r7
|
|
80089b8: bd80 pop {r7, pc}
|
|
|
|
080089ba <USBD_ClrFeature>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
80089ba: b580 push {r7, lr}
|
|
80089bc: b082 sub sp, #8
|
|
80089be: af00 add r7, sp, #0
|
|
80089c0: 6078 str r0, [r7, #4]
|
|
80089c2: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
80089c4: 687b ldr r3, [r7, #4]
|
|
80089c6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80089ca: b2db uxtb r3, r3
|
|
80089cc: 3b01 subs r3, #1
|
|
80089ce: 2b02 cmp r3, #2
|
|
80089d0: d80b bhi.n 80089ea <USBD_ClrFeature+0x30>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
80089d2: 683b ldr r3, [r7, #0]
|
|
80089d4: 885b ldrh r3, [r3, #2]
|
|
80089d6: 2b01 cmp r3, #1
|
|
80089d8: d10c bne.n 80089f4 <USBD_ClrFeature+0x3a>
|
|
{
|
|
pdev->dev_remote_wakeup = 0U;
|
|
80089da: 687b ldr r3, [r7, #4]
|
|
80089dc: 2200 movs r2, #0
|
|
80089de: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80089e2: 6878 ldr r0, [r7, #4]
|
|
80089e4: f000 f902 bl 8008bec <USBD_CtlSendStatus>
|
|
}
|
|
break;
|
|
80089e8: e004 b.n 80089f4 <USBD_ClrFeature+0x3a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80089ea: 6839 ldr r1, [r7, #0]
|
|
80089ec: 6878 ldr r0, [r7, #4]
|
|
80089ee: f000 f840 bl 8008a72 <USBD_CtlError>
|
|
break;
|
|
80089f2: e000 b.n 80089f6 <USBD_ClrFeature+0x3c>
|
|
break;
|
|
80089f4: bf00 nop
|
|
}
|
|
}
|
|
80089f6: bf00 nop
|
|
80089f8: 3708 adds r7, #8
|
|
80089fa: 46bd mov sp, r7
|
|
80089fc: bd80 pop {r7, pc}
|
|
|
|
080089fe <USBD_ParseSetupRequest>:
|
|
* @param req: usb request
|
|
* @param pdata: setup data pointer
|
|
* @retval None
|
|
*/
|
|
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
|
|
{
|
|
80089fe: b580 push {r7, lr}
|
|
8008a00: b084 sub sp, #16
|
|
8008a02: af00 add r7, sp, #0
|
|
8008a04: 6078 str r0, [r7, #4]
|
|
8008a06: 6039 str r1, [r7, #0]
|
|
uint8_t *pbuff = pdata;
|
|
8008a08: 683b ldr r3, [r7, #0]
|
|
8008a0a: 60fb str r3, [r7, #12]
|
|
|
|
req->bmRequest = *(uint8_t *)(pbuff);
|
|
8008a0c: 68fb ldr r3, [r7, #12]
|
|
8008a0e: 781a ldrb r2, [r3, #0]
|
|
8008a10: 687b ldr r3, [r7, #4]
|
|
8008a12: 701a strb r2, [r3, #0]
|
|
|
|
pbuff++;
|
|
8008a14: 68fb ldr r3, [r7, #12]
|
|
8008a16: 3301 adds r3, #1
|
|
8008a18: 60fb str r3, [r7, #12]
|
|
req->bRequest = *(uint8_t *)(pbuff);
|
|
8008a1a: 68fb ldr r3, [r7, #12]
|
|
8008a1c: 781a ldrb r2, [r3, #0]
|
|
8008a1e: 687b ldr r3, [r7, #4]
|
|
8008a20: 705a strb r2, [r3, #1]
|
|
|
|
pbuff++;
|
|
8008a22: 68fb ldr r3, [r7, #12]
|
|
8008a24: 3301 adds r3, #1
|
|
8008a26: 60fb str r3, [r7, #12]
|
|
req->wValue = SWAPBYTE(pbuff);
|
|
8008a28: 68f8 ldr r0, [r7, #12]
|
|
8008a2a: f7ff fa13 bl 8007e54 <SWAPBYTE>
|
|
8008a2e: 4603 mov r3, r0
|
|
8008a30: 461a mov r2, r3
|
|
8008a32: 687b ldr r3, [r7, #4]
|
|
8008a34: 805a strh r2, [r3, #2]
|
|
|
|
pbuff++;
|
|
8008a36: 68fb ldr r3, [r7, #12]
|
|
8008a38: 3301 adds r3, #1
|
|
8008a3a: 60fb str r3, [r7, #12]
|
|
pbuff++;
|
|
8008a3c: 68fb ldr r3, [r7, #12]
|
|
8008a3e: 3301 adds r3, #1
|
|
8008a40: 60fb str r3, [r7, #12]
|
|
req->wIndex = SWAPBYTE(pbuff);
|
|
8008a42: 68f8 ldr r0, [r7, #12]
|
|
8008a44: f7ff fa06 bl 8007e54 <SWAPBYTE>
|
|
8008a48: 4603 mov r3, r0
|
|
8008a4a: 461a mov r2, r3
|
|
8008a4c: 687b ldr r3, [r7, #4]
|
|
8008a4e: 809a strh r2, [r3, #4]
|
|
|
|
pbuff++;
|
|
8008a50: 68fb ldr r3, [r7, #12]
|
|
8008a52: 3301 adds r3, #1
|
|
8008a54: 60fb str r3, [r7, #12]
|
|
pbuff++;
|
|
8008a56: 68fb ldr r3, [r7, #12]
|
|
8008a58: 3301 adds r3, #1
|
|
8008a5a: 60fb str r3, [r7, #12]
|
|
req->wLength = SWAPBYTE(pbuff);
|
|
8008a5c: 68f8 ldr r0, [r7, #12]
|
|
8008a5e: f7ff f9f9 bl 8007e54 <SWAPBYTE>
|
|
8008a62: 4603 mov r3, r0
|
|
8008a64: 461a mov r2, r3
|
|
8008a66: 687b ldr r3, [r7, #4]
|
|
8008a68: 80da strh r2, [r3, #6]
|
|
}
|
|
8008a6a: bf00 nop
|
|
8008a6c: 3710 adds r7, #16
|
|
8008a6e: 46bd mov sp, r7
|
|
8008a70: bd80 pop {r7, pc}
|
|
|
|
08008a72 <USBD_CtlError>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008a72: b580 push {r7, lr}
|
|
8008a74: b082 sub sp, #8
|
|
8008a76: af00 add r7, sp, #0
|
|
8008a78: 6078 str r0, [r7, #4]
|
|
8008a7a: 6039 str r1, [r7, #0]
|
|
UNUSED(req);
|
|
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8008a7c: 2180 movs r1, #128 @ 0x80
|
|
8008a7e: 6878 ldr r0, [r7, #4]
|
|
8008a80: f000 fc2a bl 80092d8 <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0U);
|
|
8008a84: 2100 movs r1, #0
|
|
8008a86: 6878 ldr r0, [r7, #4]
|
|
8008a88: f000 fc26 bl 80092d8 <USBD_LL_StallEP>
|
|
}
|
|
8008a8c: bf00 nop
|
|
8008a8e: 3708 adds r7, #8
|
|
8008a90: 46bd mov sp, r7
|
|
8008a92: bd80 pop {r7, pc}
|
|
|
|
08008a94 <USBD_GetString>:
|
|
* @param unicode : Formatted string buffer (unicode)
|
|
* @param len : descriptor length
|
|
* @retval None
|
|
*/
|
|
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
|
|
{
|
|
8008a94: b580 push {r7, lr}
|
|
8008a96: b086 sub sp, #24
|
|
8008a98: af00 add r7, sp, #0
|
|
8008a9a: 60f8 str r0, [r7, #12]
|
|
8008a9c: 60b9 str r1, [r7, #8]
|
|
8008a9e: 607a str r2, [r7, #4]
|
|
uint8_t idx = 0U;
|
|
8008aa0: 2300 movs r3, #0
|
|
8008aa2: 75fb strb r3, [r7, #23]
|
|
uint8_t *pdesc;
|
|
|
|
if (desc == NULL)
|
|
8008aa4: 68fb ldr r3, [r7, #12]
|
|
8008aa6: 2b00 cmp r3, #0
|
|
8008aa8: d042 beq.n 8008b30 <USBD_GetString+0x9c>
|
|
{
|
|
return;
|
|
}
|
|
|
|
pdesc = desc;
|
|
8008aaa: 68fb ldr r3, [r7, #12]
|
|
8008aac: 613b str r3, [r7, #16]
|
|
*len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U);
|
|
8008aae: 6938 ldr r0, [r7, #16]
|
|
8008ab0: f000 f842 bl 8008b38 <USBD_GetLen>
|
|
8008ab4: 4603 mov r3, r0
|
|
8008ab6: 3301 adds r3, #1
|
|
8008ab8: 005b lsls r3, r3, #1
|
|
8008aba: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8008abe: d808 bhi.n 8008ad2 <USBD_GetString+0x3e>
|
|
8008ac0: 6938 ldr r0, [r7, #16]
|
|
8008ac2: f000 f839 bl 8008b38 <USBD_GetLen>
|
|
8008ac6: 4603 mov r3, r0
|
|
8008ac8: 3301 adds r3, #1
|
|
8008aca: b29b uxth r3, r3
|
|
8008acc: 005b lsls r3, r3, #1
|
|
8008ace: b29a uxth r2, r3
|
|
8008ad0: e001 b.n 8008ad6 <USBD_GetString+0x42>
|
|
8008ad2: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8008ad6: 687b ldr r3, [r7, #4]
|
|
8008ad8: 801a strh r2, [r3, #0]
|
|
|
|
unicode[idx] = *(uint8_t *)len;
|
|
8008ada: 7dfb ldrb r3, [r7, #23]
|
|
8008adc: 68ba ldr r2, [r7, #8]
|
|
8008ade: 4413 add r3, r2
|
|
8008ae0: 687a ldr r2, [r7, #4]
|
|
8008ae2: 7812 ldrb r2, [r2, #0]
|
|
8008ae4: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8008ae6: 7dfb ldrb r3, [r7, #23]
|
|
8008ae8: 3301 adds r3, #1
|
|
8008aea: 75fb strb r3, [r7, #23]
|
|
unicode[idx] = USB_DESC_TYPE_STRING;
|
|
8008aec: 7dfb ldrb r3, [r7, #23]
|
|
8008aee: 68ba ldr r2, [r7, #8]
|
|
8008af0: 4413 add r3, r2
|
|
8008af2: 2203 movs r2, #3
|
|
8008af4: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8008af6: 7dfb ldrb r3, [r7, #23]
|
|
8008af8: 3301 adds r3, #1
|
|
8008afa: 75fb strb r3, [r7, #23]
|
|
|
|
while (*pdesc != (uint8_t)'\0')
|
|
8008afc: e013 b.n 8008b26 <USBD_GetString+0x92>
|
|
{
|
|
unicode[idx] = *pdesc;
|
|
8008afe: 7dfb ldrb r3, [r7, #23]
|
|
8008b00: 68ba ldr r2, [r7, #8]
|
|
8008b02: 4413 add r3, r2
|
|
8008b04: 693a ldr r2, [r7, #16]
|
|
8008b06: 7812 ldrb r2, [r2, #0]
|
|
8008b08: 701a strb r2, [r3, #0]
|
|
pdesc++;
|
|
8008b0a: 693b ldr r3, [r7, #16]
|
|
8008b0c: 3301 adds r3, #1
|
|
8008b0e: 613b str r3, [r7, #16]
|
|
idx++;
|
|
8008b10: 7dfb ldrb r3, [r7, #23]
|
|
8008b12: 3301 adds r3, #1
|
|
8008b14: 75fb strb r3, [r7, #23]
|
|
|
|
unicode[idx] = 0U;
|
|
8008b16: 7dfb ldrb r3, [r7, #23]
|
|
8008b18: 68ba ldr r2, [r7, #8]
|
|
8008b1a: 4413 add r3, r2
|
|
8008b1c: 2200 movs r2, #0
|
|
8008b1e: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8008b20: 7dfb ldrb r3, [r7, #23]
|
|
8008b22: 3301 adds r3, #1
|
|
8008b24: 75fb strb r3, [r7, #23]
|
|
while (*pdesc != (uint8_t)'\0')
|
|
8008b26: 693b ldr r3, [r7, #16]
|
|
8008b28: 781b ldrb r3, [r3, #0]
|
|
8008b2a: 2b00 cmp r3, #0
|
|
8008b2c: d1e7 bne.n 8008afe <USBD_GetString+0x6a>
|
|
8008b2e: e000 b.n 8008b32 <USBD_GetString+0x9e>
|
|
return;
|
|
8008b30: bf00 nop
|
|
}
|
|
}
|
|
8008b32: 3718 adds r7, #24
|
|
8008b34: 46bd mov sp, r7
|
|
8008b36: bd80 pop {r7, pc}
|
|
|
|
08008b38 <USBD_GetLen>:
|
|
* return the string length
|
|
* @param buf : pointer to the ascii string buffer
|
|
* @retval string length
|
|
*/
|
|
static uint8_t USBD_GetLen(uint8_t *buf)
|
|
{
|
|
8008b38: b480 push {r7}
|
|
8008b3a: b085 sub sp, #20
|
|
8008b3c: af00 add r7, sp, #0
|
|
8008b3e: 6078 str r0, [r7, #4]
|
|
uint8_t len = 0U;
|
|
8008b40: 2300 movs r3, #0
|
|
8008b42: 73fb strb r3, [r7, #15]
|
|
uint8_t *pbuff = buf;
|
|
8008b44: 687b ldr r3, [r7, #4]
|
|
8008b46: 60bb str r3, [r7, #8]
|
|
|
|
while (*pbuff != (uint8_t)'\0')
|
|
8008b48: e005 b.n 8008b56 <USBD_GetLen+0x1e>
|
|
{
|
|
len++;
|
|
8008b4a: 7bfb ldrb r3, [r7, #15]
|
|
8008b4c: 3301 adds r3, #1
|
|
8008b4e: 73fb strb r3, [r7, #15]
|
|
pbuff++;
|
|
8008b50: 68bb ldr r3, [r7, #8]
|
|
8008b52: 3301 adds r3, #1
|
|
8008b54: 60bb str r3, [r7, #8]
|
|
while (*pbuff != (uint8_t)'\0')
|
|
8008b56: 68bb ldr r3, [r7, #8]
|
|
8008b58: 781b ldrb r3, [r3, #0]
|
|
8008b5a: 2b00 cmp r3, #0
|
|
8008b5c: d1f5 bne.n 8008b4a <USBD_GetLen+0x12>
|
|
}
|
|
|
|
return len;
|
|
8008b5e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008b60: 4618 mov r0, r3
|
|
8008b62: 3714 adds r7, #20
|
|
8008b64: 46bd mov sp, r7
|
|
8008b66: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008b6a: 4770 bx lr
|
|
|
|
08008b6c <USBD_CtlSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8008b6c: b580 push {r7, lr}
|
|
8008b6e: b084 sub sp, #16
|
|
8008b70: af00 add r7, sp, #0
|
|
8008b72: 60f8 str r0, [r7, #12]
|
|
8008b74: 60b9 str r1, [r7, #8]
|
|
8008b76: 607a str r2, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_DATA_IN;
|
|
8008b78: 68fb ldr r3, [r7, #12]
|
|
8008b7a: 2202 movs r2, #2
|
|
8008b7c: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->ep_in[0].total_length = len;
|
|
8008b80: 68fb ldr r3, [r7, #12]
|
|
8008b82: 687a ldr r2, [r7, #4]
|
|
8008b84: 615a str r2, [r3, #20]
|
|
pdev->ep_in[0].pbuffer = pbuf;
|
|
8008b86: 68fb ldr r3, [r7, #12]
|
|
8008b88: 68ba ldr r2, [r7, #8]
|
|
8008b8a: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
|
|
pdev->ep_in[0].rem_length = 0U;
|
|
#else
|
|
pdev->ep_in[0].rem_length = len;
|
|
8008b8c: 68fb ldr r3, [r7, #12]
|
|
8008b8e: 687a ldr r2, [r7, #4]
|
|
8008b90: 619a str r2, [r3, #24]
|
|
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
8008b92: 687b ldr r3, [r7, #4]
|
|
8008b94: 68ba ldr r2, [r7, #8]
|
|
8008b96: 2100 movs r1, #0
|
|
8008b98: 68f8 ldr r0, [r7, #12]
|
|
8008b9a: f000 fc26 bl 80093ea <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8008b9e: 2300 movs r3, #0
|
|
}
|
|
8008ba0: 4618 mov r0, r3
|
|
8008ba2: 3710 adds r7, #16
|
|
8008ba4: 46bd mov sp, r7
|
|
8008ba6: bd80 pop {r7, pc}
|
|
|
|
08008ba8 <USBD_CtlContinueSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8008ba8: b580 push {r7, lr}
|
|
8008baa: b084 sub sp, #16
|
|
8008bac: af00 add r7, sp, #0
|
|
8008bae: 60f8 str r0, [r7, #12]
|
|
8008bb0: 60b9 str r1, [r7, #8]
|
|
8008bb2: 607a str r2, [r7, #4]
|
|
/* Start the next transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
8008bb4: 687b ldr r3, [r7, #4]
|
|
8008bb6: 68ba ldr r2, [r7, #8]
|
|
8008bb8: 2100 movs r1, #0
|
|
8008bba: 68f8 ldr r0, [r7, #12]
|
|
8008bbc: f000 fc15 bl 80093ea <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8008bc0: 2300 movs r3, #0
|
|
}
|
|
8008bc2: 4618 mov r0, r3
|
|
8008bc4: 3710 adds r7, #16
|
|
8008bc6: 46bd mov sp, r7
|
|
8008bc8: bd80 pop {r7, pc}
|
|
|
|
08008bca <USBD_CtlContinueRx>:
|
|
* @param len: length of data to be received
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8008bca: b580 push {r7, lr}
|
|
8008bcc: b084 sub sp, #16
|
|
8008bce: af00 add r7, sp, #0
|
|
8008bd0: 60f8 str r0, [r7, #12]
|
|
8008bd2: 60b9 str r1, [r7, #8]
|
|
8008bd4: 607a str r2, [r7, #4]
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
|
|
8008bd6: 687b ldr r3, [r7, #4]
|
|
8008bd8: 68ba ldr r2, [r7, #8]
|
|
8008bda: 2100 movs r1, #0
|
|
8008bdc: 68f8 ldr r0, [r7, #12]
|
|
8008bde: f000 fc25 bl 800942c <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8008be2: 2300 movs r3, #0
|
|
}
|
|
8008be4: 4618 mov r0, r3
|
|
8008be6: 3710 adds r7, #16
|
|
8008be8: 46bd mov sp, r7
|
|
8008bea: bd80 pop {r7, pc}
|
|
|
|
08008bec <USBD_CtlSendStatus>:
|
|
* send zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008bec: b580 push {r7, lr}
|
|
8008bee: b082 sub sp, #8
|
|
8008bf0: af00 add r7, sp, #0
|
|
8008bf2: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_IN;
|
|
8008bf4: 687b ldr r3, [r7, #4]
|
|
8008bf6: 2204 movs r2, #4
|
|
8008bf8: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
|
|
8008bfc: 2300 movs r3, #0
|
|
8008bfe: 2200 movs r2, #0
|
|
8008c00: 2100 movs r1, #0
|
|
8008c02: 6878 ldr r0, [r7, #4]
|
|
8008c04: f000 fbf1 bl 80093ea <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8008c08: 2300 movs r3, #0
|
|
}
|
|
8008c0a: 4618 mov r0, r3
|
|
8008c0c: 3708 adds r7, #8
|
|
8008c0e: 46bd mov sp, r7
|
|
8008c10: bd80 pop {r7, pc}
|
|
|
|
08008c12 <USBD_CtlReceiveStatus>:
|
|
* receive zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008c12: b580 push {r7, lr}
|
|
8008c14: b082 sub sp, #8
|
|
8008c16: af00 add r7, sp, #0
|
|
8008c18: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_OUT;
|
|
8008c1a: 687b ldr r3, [r7, #4]
|
|
8008c1c: 2205 movs r2, #5
|
|
8008c1e: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8008c22: 2300 movs r3, #0
|
|
8008c24: 2200 movs r2, #0
|
|
8008c26: 2100 movs r1, #0
|
|
8008c28: 6878 ldr r0, [r7, #4]
|
|
8008c2a: f000 fbff bl 800942c <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8008c2e: 2300 movs r3, #0
|
|
}
|
|
8008c30: 4618 mov r0, r3
|
|
8008c32: 3708 adds r7, #8
|
|
8008c34: 46bd mov sp, r7
|
|
8008c36: bd80 pop {r7, pc}
|
|
|
|
08008c38 <MX_USB_DEVICE_Init>:
|
|
/**
|
|
* Init USB device Library, add supported class and start the library
|
|
* @retval None
|
|
*/
|
|
void MX_USB_DEVICE_Init(void)
|
|
{
|
|
8008c38: b580 push {r7, lr}
|
|
8008c3a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
|
|
|
|
/* USER CODE END USB_DEVICE_Init_PreTreatment */
|
|
|
|
/* Init Device Library, add supported class and start the library. */
|
|
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
|
|
8008c3c: 2200 movs r2, #0
|
|
8008c3e: 490e ldr r1, [pc, #56] @ (8008c78 <MX_USB_DEVICE_Init+0x40>)
|
|
8008c40: 480e ldr r0, [pc, #56] @ (8008c7c <MX_USB_DEVICE_Init+0x44>)
|
|
8008c42: f7fe fcd1 bl 80075e8 <USBD_Init>
|
|
8008c46: 4603 mov r3, r0
|
|
8008c48: 2b00 cmp r3, #0
|
|
8008c4a: d001 beq.n 8008c50 <MX_USB_DEVICE_Init+0x18>
|
|
{
|
|
Error_Handler();
|
|
8008c4c: f7f8 f936 bl 8000ebc <Error_Handler>
|
|
}
|
|
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK)
|
|
8008c50: 490b ldr r1, [pc, #44] @ (8008c80 <MX_USB_DEVICE_Init+0x48>)
|
|
8008c52: 480a ldr r0, [pc, #40] @ (8008c7c <MX_USB_DEVICE_Init+0x44>)
|
|
8008c54: f7fe fcf8 bl 8007648 <USBD_RegisterClass>
|
|
8008c58: 4603 mov r3, r0
|
|
8008c5a: 2b00 cmp r3, #0
|
|
8008c5c: d001 beq.n 8008c62 <MX_USB_DEVICE_Init+0x2a>
|
|
{
|
|
Error_Handler();
|
|
8008c5e: f7f8 f92d bl 8000ebc <Error_Handler>
|
|
}
|
|
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
|
|
8008c62: 4806 ldr r0, [pc, #24] @ (8008c7c <MX_USB_DEVICE_Init+0x44>)
|
|
8008c64: f7fe fd26 bl 80076b4 <USBD_Start>
|
|
8008c68: 4603 mov r3, r0
|
|
8008c6a: 2b00 cmp r3, #0
|
|
8008c6c: d001 beq.n 8008c72 <MX_USB_DEVICE_Init+0x3a>
|
|
{
|
|
Error_Handler();
|
|
8008c6e: f7f8 f925 bl 8000ebc <Error_Handler>
|
|
}
|
|
|
|
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
|
|
|
|
/* USER CODE END USB_DEVICE_Init_PostTreatment */
|
|
}
|
|
8008c72: bf00 nop
|
|
8008c74: bd80 pop {r7, pc}
|
|
8008c76: bf00 nop
|
|
8008c78: 200000d8 .word 0x200000d8
|
|
8008c7c: 200004b8 .word 0x200004b8
|
|
8008c80: 20000034 .word 0x20000034
|
|
|
|
08008c84 <USBD_FS_DeviceDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008c84: b480 push {r7}
|
|
8008c86: b083 sub sp, #12
|
|
8008c88: af00 add r7, sp, #0
|
|
8008c8a: 4603 mov r3, r0
|
|
8008c8c: 6039 str r1, [r7, #0]
|
|
8008c8e: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_FS_DeviceDesc);
|
|
8008c90: 683b ldr r3, [r7, #0]
|
|
8008c92: 2212 movs r2, #18
|
|
8008c94: 801a strh r2, [r3, #0]
|
|
return USBD_FS_DeviceDesc;
|
|
8008c96: 4b03 ldr r3, [pc, #12] @ (8008ca4 <USBD_FS_DeviceDescriptor+0x20>)
|
|
}
|
|
8008c98: 4618 mov r0, r3
|
|
8008c9a: 370c adds r7, #12
|
|
8008c9c: 46bd mov sp, r7
|
|
8008c9e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008ca2: 4770 bx lr
|
|
8008ca4: 200000f8 .word 0x200000f8
|
|
|
|
08008ca8 <USBD_FS_LangIDStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008ca8: b480 push {r7}
|
|
8008caa: b083 sub sp, #12
|
|
8008cac: af00 add r7, sp, #0
|
|
8008cae: 4603 mov r3, r0
|
|
8008cb0: 6039 str r1, [r7, #0]
|
|
8008cb2: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_LangIDDesc);
|
|
8008cb4: 683b ldr r3, [r7, #0]
|
|
8008cb6: 2204 movs r2, #4
|
|
8008cb8: 801a strh r2, [r3, #0]
|
|
return USBD_LangIDDesc;
|
|
8008cba: 4b03 ldr r3, [pc, #12] @ (8008cc8 <USBD_FS_LangIDStrDescriptor+0x20>)
|
|
}
|
|
8008cbc: 4618 mov r0, r3
|
|
8008cbe: 370c adds r7, #12
|
|
8008cc0: 46bd mov sp, r7
|
|
8008cc2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008cc6: 4770 bx lr
|
|
8008cc8: 20000118 .word 0x20000118
|
|
|
|
08008ccc <USBD_FS_ProductStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008ccc: b580 push {r7, lr}
|
|
8008cce: b082 sub sp, #8
|
|
8008cd0: af00 add r7, sp, #0
|
|
8008cd2: 4603 mov r3, r0
|
|
8008cd4: 6039 str r1, [r7, #0]
|
|
8008cd6: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
8008cd8: 79fb ldrb r3, [r7, #7]
|
|
8008cda: 2b00 cmp r3, #0
|
|
8008cdc: d105 bne.n 8008cea <USBD_FS_ProductStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
|
|
8008cde: 683a ldr r2, [r7, #0]
|
|
8008ce0: 4907 ldr r1, [pc, #28] @ (8008d00 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
8008ce2: 4808 ldr r0, [pc, #32] @ (8008d04 <USBD_FS_ProductStrDescriptor+0x38>)
|
|
8008ce4: f7ff fed6 bl 8008a94 <USBD_GetString>
|
|
8008ce8: e004 b.n 8008cf4 <USBD_FS_ProductStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
|
|
8008cea: 683a ldr r2, [r7, #0]
|
|
8008cec: 4904 ldr r1, [pc, #16] @ (8008d00 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
8008cee: 4805 ldr r0, [pc, #20] @ (8008d04 <USBD_FS_ProductStrDescriptor+0x38>)
|
|
8008cf0: f7ff fed0 bl 8008a94 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8008cf4: 4b02 ldr r3, [pc, #8] @ (8008d00 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
}
|
|
8008cf6: 4618 mov r0, r3
|
|
8008cf8: 3708 adds r7, #8
|
|
8008cfa: 46bd mov sp, r7
|
|
8008cfc: bd80 pop {r7, pc}
|
|
8008cfe: bf00 nop
|
|
8008d00: 20000794 .word 0x20000794
|
|
8008d04: 08009604 .word 0x08009604
|
|
|
|
08008d08 <USBD_FS_ManufacturerStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008d08: b580 push {r7, lr}
|
|
8008d0a: b082 sub sp, #8
|
|
8008d0c: af00 add r7, sp, #0
|
|
8008d0e: 4603 mov r3, r0
|
|
8008d10: 6039 str r1, [r7, #0]
|
|
8008d12: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
|
|
8008d14: 683a ldr r2, [r7, #0]
|
|
8008d16: 4904 ldr r1, [pc, #16] @ (8008d28 <USBD_FS_ManufacturerStrDescriptor+0x20>)
|
|
8008d18: 4804 ldr r0, [pc, #16] @ (8008d2c <USBD_FS_ManufacturerStrDescriptor+0x24>)
|
|
8008d1a: f7ff febb bl 8008a94 <USBD_GetString>
|
|
return USBD_StrDesc;
|
|
8008d1e: 4b02 ldr r3, [pc, #8] @ (8008d28 <USBD_FS_ManufacturerStrDescriptor+0x20>)
|
|
}
|
|
8008d20: 4618 mov r0, r3
|
|
8008d22: 3708 adds r7, #8
|
|
8008d24: 46bd mov sp, r7
|
|
8008d26: bd80 pop {r7, pc}
|
|
8008d28: 20000794 .word 0x20000794
|
|
8008d2c: 08009618 .word 0x08009618
|
|
|
|
08008d30 <USBD_FS_SerialStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008d30: b580 push {r7, lr}
|
|
8008d32: b082 sub sp, #8
|
|
8008d34: af00 add r7, sp, #0
|
|
8008d36: 4603 mov r3, r0
|
|
8008d38: 6039 str r1, [r7, #0]
|
|
8008d3a: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = USB_SIZ_STRING_SERIAL;
|
|
8008d3c: 683b ldr r3, [r7, #0]
|
|
8008d3e: 221a movs r2, #26
|
|
8008d40: 801a strh r2, [r3, #0]
|
|
|
|
/* Update the serial number string descriptor with the data from the unique
|
|
* ID */
|
|
Get_SerialNum();
|
|
8008d42: f000 f855 bl 8008df0 <Get_SerialNum>
|
|
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
|
|
|
|
/* USER CODE END USBD_FS_SerialStrDescriptor */
|
|
return (uint8_t *) USBD_StringSerial;
|
|
8008d46: 4b02 ldr r3, [pc, #8] @ (8008d50 <USBD_FS_SerialStrDescriptor+0x20>)
|
|
}
|
|
8008d48: 4618 mov r0, r3
|
|
8008d4a: 3708 adds r7, #8
|
|
8008d4c: 46bd mov sp, r7
|
|
8008d4e: bd80 pop {r7, pc}
|
|
8008d50: 2000011c .word 0x2000011c
|
|
|
|
08008d54 <USBD_FS_ConfigStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008d54: b580 push {r7, lr}
|
|
8008d56: b082 sub sp, #8
|
|
8008d58: af00 add r7, sp, #0
|
|
8008d5a: 4603 mov r3, r0
|
|
8008d5c: 6039 str r1, [r7, #0]
|
|
8008d5e: 71fb strb r3, [r7, #7]
|
|
if(speed == USBD_SPEED_HIGH)
|
|
8008d60: 79fb ldrb r3, [r7, #7]
|
|
8008d62: 2b00 cmp r3, #0
|
|
8008d64: d105 bne.n 8008d72 <USBD_FS_ConfigStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
|
|
8008d66: 683a ldr r2, [r7, #0]
|
|
8008d68: 4907 ldr r1, [pc, #28] @ (8008d88 <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
8008d6a: 4808 ldr r0, [pc, #32] @ (8008d8c <USBD_FS_ConfigStrDescriptor+0x38>)
|
|
8008d6c: f7ff fe92 bl 8008a94 <USBD_GetString>
|
|
8008d70: e004 b.n 8008d7c <USBD_FS_ConfigStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
|
|
8008d72: 683a ldr r2, [r7, #0]
|
|
8008d74: 4904 ldr r1, [pc, #16] @ (8008d88 <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
8008d76: 4805 ldr r0, [pc, #20] @ (8008d8c <USBD_FS_ConfigStrDescriptor+0x38>)
|
|
8008d78: f7ff fe8c bl 8008a94 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8008d7c: 4b02 ldr r3, [pc, #8] @ (8008d88 <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
}
|
|
8008d7e: 4618 mov r0, r3
|
|
8008d80: 3708 adds r7, #8
|
|
8008d82: 46bd mov sp, r7
|
|
8008d84: bd80 pop {r7, pc}
|
|
8008d86: bf00 nop
|
|
8008d88: 20000794 .word 0x20000794
|
|
8008d8c: 08009624 .word 0x08009624
|
|
|
|
08008d90 <USBD_FS_InterfaceStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008d90: b580 push {r7, lr}
|
|
8008d92: b082 sub sp, #8
|
|
8008d94: af00 add r7, sp, #0
|
|
8008d96: 4603 mov r3, r0
|
|
8008d98: 6039 str r1, [r7, #0]
|
|
8008d9a: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
8008d9c: 79fb ldrb r3, [r7, #7]
|
|
8008d9e: 2b00 cmp r3, #0
|
|
8008da0: d105 bne.n 8008dae <USBD_FS_InterfaceStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
|
|
8008da2: 683a ldr r2, [r7, #0]
|
|
8008da4: 4907 ldr r1, [pc, #28] @ (8008dc4 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
8008da6: 4808 ldr r0, [pc, #32] @ (8008dc8 <USBD_FS_InterfaceStrDescriptor+0x38>)
|
|
8008da8: f7ff fe74 bl 8008a94 <USBD_GetString>
|
|
8008dac: e004 b.n 8008db8 <USBD_FS_InterfaceStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
|
|
8008dae: 683a ldr r2, [r7, #0]
|
|
8008db0: 4904 ldr r1, [pc, #16] @ (8008dc4 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
8008db2: 4805 ldr r0, [pc, #20] @ (8008dc8 <USBD_FS_InterfaceStrDescriptor+0x38>)
|
|
8008db4: f7ff fe6e bl 8008a94 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8008db8: 4b02 ldr r3, [pc, #8] @ (8008dc4 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
}
|
|
8008dba: 4618 mov r0, r3
|
|
8008dbc: 3708 adds r7, #8
|
|
8008dbe: 46bd mov sp, r7
|
|
8008dc0: bd80 pop {r7, pc}
|
|
8008dc2: bf00 nop
|
|
8008dc4: 20000794 .word 0x20000794
|
|
8008dc8: 08009630 .word 0x08009630
|
|
|
|
08008dcc <USBD_FS_USR_BOSDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008dcc: b480 push {r7}
|
|
8008dce: b083 sub sp, #12
|
|
8008dd0: af00 add r7, sp, #0
|
|
8008dd2: 4603 mov r3, r0
|
|
8008dd4: 6039 str r1, [r7, #0]
|
|
8008dd6: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_FS_BOSDesc);
|
|
8008dd8: 683b ldr r3, [r7, #0]
|
|
8008dda: 220c movs r2, #12
|
|
8008ddc: 801a strh r2, [r3, #0]
|
|
return (uint8_t*)USBD_FS_BOSDesc;
|
|
8008dde: 4b03 ldr r3, [pc, #12] @ (8008dec <USBD_FS_USR_BOSDescriptor+0x20>)
|
|
}
|
|
8008de0: 4618 mov r0, r3
|
|
8008de2: 370c adds r7, #12
|
|
8008de4: 46bd mov sp, r7
|
|
8008de6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008dea: 4770 bx lr
|
|
8008dec: 2000010c .word 0x2000010c
|
|
|
|
08008df0 <Get_SerialNum>:
|
|
* @brief Create the serial number string descriptor
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void Get_SerialNum(void)
|
|
{
|
|
8008df0: b580 push {r7, lr}
|
|
8008df2: b084 sub sp, #16
|
|
8008df4: af00 add r7, sp, #0
|
|
uint32_t deviceserial0;
|
|
uint32_t deviceserial1;
|
|
uint32_t deviceserial2;
|
|
|
|
deviceserial0 = *(uint32_t *) DEVICE_ID1;
|
|
8008df6: 4b0f ldr r3, [pc, #60] @ (8008e34 <Get_SerialNum+0x44>)
|
|
8008df8: 681b ldr r3, [r3, #0]
|
|
8008dfa: 60fb str r3, [r7, #12]
|
|
deviceserial1 = *(uint32_t *) DEVICE_ID2;
|
|
8008dfc: 4b0e ldr r3, [pc, #56] @ (8008e38 <Get_SerialNum+0x48>)
|
|
8008dfe: 681b ldr r3, [r3, #0]
|
|
8008e00: 60bb str r3, [r7, #8]
|
|
deviceserial2 = *(uint32_t *) DEVICE_ID3;
|
|
8008e02: 4b0e ldr r3, [pc, #56] @ (8008e3c <Get_SerialNum+0x4c>)
|
|
8008e04: 681b ldr r3, [r3, #0]
|
|
8008e06: 607b str r3, [r7, #4]
|
|
|
|
deviceserial0 += deviceserial2;
|
|
8008e08: 68fa ldr r2, [r7, #12]
|
|
8008e0a: 687b ldr r3, [r7, #4]
|
|
8008e0c: 4413 add r3, r2
|
|
8008e0e: 60fb str r3, [r7, #12]
|
|
|
|
if (deviceserial0 != 0)
|
|
8008e10: 68fb ldr r3, [r7, #12]
|
|
8008e12: 2b00 cmp r3, #0
|
|
8008e14: d009 beq.n 8008e2a <Get_SerialNum+0x3a>
|
|
{
|
|
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
|
|
8008e16: 2208 movs r2, #8
|
|
8008e18: 4909 ldr r1, [pc, #36] @ (8008e40 <Get_SerialNum+0x50>)
|
|
8008e1a: 68f8 ldr r0, [r7, #12]
|
|
8008e1c: f000 f814 bl 8008e48 <IntToUnicode>
|
|
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
|
|
8008e20: 2204 movs r2, #4
|
|
8008e22: 4908 ldr r1, [pc, #32] @ (8008e44 <Get_SerialNum+0x54>)
|
|
8008e24: 68b8 ldr r0, [r7, #8]
|
|
8008e26: f000 f80f bl 8008e48 <IntToUnicode>
|
|
}
|
|
}
|
|
8008e2a: bf00 nop
|
|
8008e2c: 3710 adds r7, #16
|
|
8008e2e: 46bd mov sp, r7
|
|
8008e30: bd80 pop {r7, pc}
|
|
8008e32: bf00 nop
|
|
8008e34: 1fff7a10 .word 0x1fff7a10
|
|
8008e38: 1fff7a14 .word 0x1fff7a14
|
|
8008e3c: 1fff7a18 .word 0x1fff7a18
|
|
8008e40: 2000011e .word 0x2000011e
|
|
8008e44: 2000012e .word 0x2000012e
|
|
|
|
08008e48 <IntToUnicode>:
|
|
* @param pbuf: pointer to the buffer
|
|
* @param len: buffer length
|
|
* @retval None
|
|
*/
|
|
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
|
|
{
|
|
8008e48: b480 push {r7}
|
|
8008e4a: b087 sub sp, #28
|
|
8008e4c: af00 add r7, sp, #0
|
|
8008e4e: 60f8 str r0, [r7, #12]
|
|
8008e50: 60b9 str r1, [r7, #8]
|
|
8008e52: 4613 mov r3, r2
|
|
8008e54: 71fb strb r3, [r7, #7]
|
|
uint8_t idx = 0;
|
|
8008e56: 2300 movs r3, #0
|
|
8008e58: 75fb strb r3, [r7, #23]
|
|
|
|
for (idx = 0; idx < len; idx++)
|
|
8008e5a: 2300 movs r3, #0
|
|
8008e5c: 75fb strb r3, [r7, #23]
|
|
8008e5e: e027 b.n 8008eb0 <IntToUnicode+0x68>
|
|
{
|
|
if (((value >> 28)) < 0xA)
|
|
8008e60: 68fb ldr r3, [r7, #12]
|
|
8008e62: 0f1b lsrs r3, r3, #28
|
|
8008e64: 2b09 cmp r3, #9
|
|
8008e66: d80b bhi.n 8008e80 <IntToUnicode+0x38>
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + '0';
|
|
8008e68: 68fb ldr r3, [r7, #12]
|
|
8008e6a: 0f1b lsrs r3, r3, #28
|
|
8008e6c: b2da uxtb r2, r3
|
|
8008e6e: 7dfb ldrb r3, [r7, #23]
|
|
8008e70: 005b lsls r3, r3, #1
|
|
8008e72: 4619 mov r1, r3
|
|
8008e74: 68bb ldr r3, [r7, #8]
|
|
8008e76: 440b add r3, r1
|
|
8008e78: 3230 adds r2, #48 @ 0x30
|
|
8008e7a: b2d2 uxtb r2, r2
|
|
8008e7c: 701a strb r2, [r3, #0]
|
|
8008e7e: e00a b.n 8008e96 <IntToUnicode+0x4e>
|
|
}
|
|
else
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
|
|
8008e80: 68fb ldr r3, [r7, #12]
|
|
8008e82: 0f1b lsrs r3, r3, #28
|
|
8008e84: b2da uxtb r2, r3
|
|
8008e86: 7dfb ldrb r3, [r7, #23]
|
|
8008e88: 005b lsls r3, r3, #1
|
|
8008e8a: 4619 mov r1, r3
|
|
8008e8c: 68bb ldr r3, [r7, #8]
|
|
8008e8e: 440b add r3, r1
|
|
8008e90: 3237 adds r2, #55 @ 0x37
|
|
8008e92: b2d2 uxtb r2, r2
|
|
8008e94: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
value = value << 4;
|
|
8008e96: 68fb ldr r3, [r7, #12]
|
|
8008e98: 011b lsls r3, r3, #4
|
|
8008e9a: 60fb str r3, [r7, #12]
|
|
|
|
pbuf[2 * idx + 1] = 0;
|
|
8008e9c: 7dfb ldrb r3, [r7, #23]
|
|
8008e9e: 005b lsls r3, r3, #1
|
|
8008ea0: 3301 adds r3, #1
|
|
8008ea2: 68ba ldr r2, [r7, #8]
|
|
8008ea4: 4413 add r3, r2
|
|
8008ea6: 2200 movs r2, #0
|
|
8008ea8: 701a strb r2, [r3, #0]
|
|
for (idx = 0; idx < len; idx++)
|
|
8008eaa: 7dfb ldrb r3, [r7, #23]
|
|
8008eac: 3301 adds r3, #1
|
|
8008eae: 75fb strb r3, [r7, #23]
|
|
8008eb0: 7dfa ldrb r2, [r7, #23]
|
|
8008eb2: 79fb ldrb r3, [r7, #7]
|
|
8008eb4: 429a cmp r2, r3
|
|
8008eb6: d3d3 bcc.n 8008e60 <IntToUnicode+0x18>
|
|
}
|
|
}
|
|
8008eb8: bf00 nop
|
|
8008eba: bf00 nop
|
|
8008ebc: 371c adds r7, #28
|
|
8008ebe: 46bd mov sp, r7
|
|
8008ec0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008ec4: 4770 bx lr
|
|
...
|
|
|
|
08008ec8 <HAL_PCD_MspInit>:
|
|
LL Driver Callbacks (PCD -> USB Device Library)
|
|
*******************************************************************************/
|
|
/* MSP Init */
|
|
|
|
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
|
|
{
|
|
8008ec8: b580 push {r7, lr}
|
|
8008eca: b0a0 sub sp, #128 @ 0x80
|
|
8008ecc: af00 add r7, sp, #0
|
|
8008ece: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8008ed0: f107 036c add.w r3, r7, #108 @ 0x6c
|
|
8008ed4: 2200 movs r2, #0
|
|
8008ed6: 601a str r2, [r3, #0]
|
|
8008ed8: 605a str r2, [r3, #4]
|
|
8008eda: 609a str r2, [r3, #8]
|
|
8008edc: 60da str r2, [r3, #12]
|
|
8008ede: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
8008ee0: f107 0310 add.w r3, r7, #16
|
|
8008ee4: 225c movs r2, #92 @ 0x5c
|
|
8008ee6: 2100 movs r1, #0
|
|
8008ee8: 4618 mov r0, r3
|
|
8008eea: f000 fb53 bl 8009594 <memset>
|
|
if(pcdHandle->Instance==USB_OTG_FS)
|
|
8008eee: 687b ldr r3, [r7, #4]
|
|
8008ef0: 681b ldr r3, [r3, #0]
|
|
8008ef2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8008ef6: d149 bne.n 8008f8c <HAL_PCD_MspInit+0xc4>
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
|
|
8008ef8: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8008efc: 613b str r3, [r7, #16]
|
|
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ;
|
|
8008efe: 2300 movs r3, #0
|
|
8008f00: 667b str r3, [r7, #100] @ 0x64
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
8008f02: f107 0310 add.w r3, r7, #16
|
|
8008f06: 4618 mov r0, r3
|
|
8008f08: f7fa fb78 bl 80035fc <HAL_RCCEx_PeriphCLKConfig>
|
|
8008f0c: 4603 mov r3, r0
|
|
8008f0e: 2b00 cmp r3, #0
|
|
8008f10: d001 beq.n 8008f16 <HAL_PCD_MspInit+0x4e>
|
|
{
|
|
Error_Handler();
|
|
8008f12: f7f7 ffd3 bl 8000ebc <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8008f16: 2300 movs r3, #0
|
|
8008f18: 60fb str r3, [r7, #12]
|
|
8008f1a: 4b1e ldr r3, [pc, #120] @ (8008f94 <HAL_PCD_MspInit+0xcc>)
|
|
8008f1c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8008f1e: 4a1d ldr r2, [pc, #116] @ (8008f94 <HAL_PCD_MspInit+0xcc>)
|
|
8008f20: f043 0301 orr.w r3, r3, #1
|
|
8008f24: 6313 str r3, [r2, #48] @ 0x30
|
|
8008f26: 4b1b ldr r3, [pc, #108] @ (8008f94 <HAL_PCD_MspInit+0xcc>)
|
|
8008f28: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8008f2a: f003 0301 and.w r3, r3, #1
|
|
8008f2e: 60fb str r3, [r7, #12]
|
|
8008f30: 68fb ldr r3, [r7, #12]
|
|
/**USB_OTG_FS GPIO Configuration
|
|
PA11 ------> USB_OTG_FS_DM
|
|
PA12 ------> USB_OTG_FS_DP
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
|
|
8008f32: f44f 53c0 mov.w r3, #6144 @ 0x1800
|
|
8008f36: 66fb str r3, [r7, #108] @ 0x6c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8008f38: 2302 movs r3, #2
|
|
8008f3a: 673b str r3, [r7, #112] @ 0x70
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8008f3c: 2300 movs r3, #0
|
|
8008f3e: 677b str r3, [r7, #116] @ 0x74
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8008f40: 2303 movs r3, #3
|
|
8008f42: 67bb str r3, [r7, #120] @ 0x78
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
|
|
8008f44: 230a movs r3, #10
|
|
8008f46: 67fb str r3, [r7, #124] @ 0x7c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8008f48: f107 036c add.w r3, r7, #108 @ 0x6c
|
|
8008f4c: 4619 mov r1, r3
|
|
8008f4e: 4812 ldr r0, [pc, #72] @ (8008f98 <HAL_PCD_MspInit+0xd0>)
|
|
8008f50: f7f8 fcaa bl 80018a8 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
|
|
8008f54: 4b0f ldr r3, [pc, #60] @ (8008f94 <HAL_PCD_MspInit+0xcc>)
|
|
8008f56: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8008f58: 4a0e ldr r2, [pc, #56] @ (8008f94 <HAL_PCD_MspInit+0xcc>)
|
|
8008f5a: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8008f5e: 6353 str r3, [r2, #52] @ 0x34
|
|
8008f60: 2300 movs r3, #0
|
|
8008f62: 60bb str r3, [r7, #8]
|
|
8008f64: 4b0b ldr r3, [pc, #44] @ (8008f94 <HAL_PCD_MspInit+0xcc>)
|
|
8008f66: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008f68: 4a0a ldr r2, [pc, #40] @ (8008f94 <HAL_PCD_MspInit+0xcc>)
|
|
8008f6a: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8008f6e: 6453 str r3, [r2, #68] @ 0x44
|
|
8008f70: 4b08 ldr r3, [pc, #32] @ (8008f94 <HAL_PCD_MspInit+0xcc>)
|
|
8008f72: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008f74: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8008f78: 60bb str r3, [r7, #8]
|
|
8008f7a: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Peripheral interrupt init */
|
|
HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
|
|
8008f7c: 2200 movs r2, #0
|
|
8008f7e: 2100 movs r1, #0
|
|
8008f80: 2043 movs r0, #67 @ 0x43
|
|
8008f82: f7f8 fbd4 bl 800172e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
|
|
8008f86: 2043 movs r0, #67 @ 0x43
|
|
8008f88: f7f8 fbed bl 8001766 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 1 */
|
|
}
|
|
}
|
|
8008f8c: bf00 nop
|
|
8008f8e: 3780 adds r7, #128 @ 0x80
|
|
8008f90: 46bd mov sp, r7
|
|
8008f92: bd80 pop {r7, pc}
|
|
8008f94: 40023800 .word 0x40023800
|
|
8008f98: 40020000 .word 0x40020000
|
|
|
|
08008f9c <HAL_PCD_SetupStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8008f9c: b580 push {r7, lr}
|
|
8008f9e: b082 sub sp, #8
|
|
8008fa0: af00 add r7, sp, #0
|
|
8008fa2: 6078 str r0, [r7, #4]
|
|
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
|
|
8008fa4: 687b ldr r3, [r7, #4]
|
|
8008fa6: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0
|
|
8008faa: 687b ldr r3, [r7, #4]
|
|
8008fac: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8008fb0: 4619 mov r1, r3
|
|
8008fb2: 4610 mov r0, r2
|
|
8008fb4: f7fe fbcb bl 800774e <USBD_LL_SetupStage>
|
|
}
|
|
8008fb8: bf00 nop
|
|
8008fba: 3708 adds r7, #8
|
|
8008fbc: 46bd mov sp, r7
|
|
8008fbe: bd80 pop {r7, pc}
|
|
|
|
08008fc0 <HAL_PCD_DataOutStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8008fc0: b580 push {r7, lr}
|
|
8008fc2: b082 sub sp, #8
|
|
8008fc4: af00 add r7, sp, #0
|
|
8008fc6: 6078 str r0, [r7, #4]
|
|
8008fc8: 460b mov r3, r1
|
|
8008fca: 70fb strb r3, [r7, #3]
|
|
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
|
|
8008fcc: 687b ldr r3, [r7, #4]
|
|
8008fce: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
|
|
8008fd2: 78fa ldrb r2, [r7, #3]
|
|
8008fd4: 6879 ldr r1, [r7, #4]
|
|
8008fd6: 4613 mov r3, r2
|
|
8008fd8: 00db lsls r3, r3, #3
|
|
8008fda: 4413 add r3, r2
|
|
8008fdc: 009b lsls r3, r3, #2
|
|
8008fde: 440b add r3, r1
|
|
8008fe0: f503 7318 add.w r3, r3, #608 @ 0x260
|
|
8008fe4: 681a ldr r2, [r3, #0]
|
|
8008fe6: 78fb ldrb r3, [r7, #3]
|
|
8008fe8: 4619 mov r1, r3
|
|
8008fea: f7fe fc05 bl 80077f8 <USBD_LL_DataOutStage>
|
|
}
|
|
8008fee: bf00 nop
|
|
8008ff0: 3708 adds r7, #8
|
|
8008ff2: 46bd mov sp, r7
|
|
8008ff4: bd80 pop {r7, pc}
|
|
|
|
08008ff6 <HAL_PCD_DataInStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8008ff6: b580 push {r7, lr}
|
|
8008ff8: b082 sub sp, #8
|
|
8008ffa: af00 add r7, sp, #0
|
|
8008ffc: 6078 str r0, [r7, #4]
|
|
8008ffe: 460b mov r3, r1
|
|
8009000: 70fb strb r3, [r7, #3]
|
|
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
|
|
8009002: 687b ldr r3, [r7, #4]
|
|
8009004: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
|
|
8009008: 78fa ldrb r2, [r7, #3]
|
|
800900a: 6879 ldr r1, [r7, #4]
|
|
800900c: 4613 mov r3, r2
|
|
800900e: 00db lsls r3, r3, #3
|
|
8009010: 4413 add r3, r2
|
|
8009012: 009b lsls r3, r3, #2
|
|
8009014: 440b add r3, r1
|
|
8009016: 3320 adds r3, #32
|
|
8009018: 681a ldr r2, [r3, #0]
|
|
800901a: 78fb ldrb r3, [r7, #3]
|
|
800901c: 4619 mov r1, r3
|
|
800901e: f7fe fca7 bl 8007970 <USBD_LL_DataInStage>
|
|
}
|
|
8009022: bf00 nop
|
|
8009024: 3708 adds r7, #8
|
|
8009026: 46bd mov sp, r7
|
|
8009028: bd80 pop {r7, pc}
|
|
|
|
0800902a <HAL_PCD_SOFCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800902a: b580 push {r7, lr}
|
|
800902c: b082 sub sp, #8
|
|
800902e: af00 add r7, sp, #0
|
|
8009030: 6078 str r0, [r7, #4]
|
|
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
|
|
8009032: 687b ldr r3, [r7, #4]
|
|
8009034: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
8009038: 4618 mov r0, r3
|
|
800903a: f7fe fdeb bl 8007c14 <USBD_LL_SOF>
|
|
}
|
|
800903e: bf00 nop
|
|
8009040: 3708 adds r7, #8
|
|
8009042: 46bd mov sp, r7
|
|
8009044: bd80 pop {r7, pc}
|
|
|
|
08009046 <HAL_PCD_ResetCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009046: b580 push {r7, lr}
|
|
8009048: b084 sub sp, #16
|
|
800904a: af00 add r7, sp, #0
|
|
800904c: 6078 str r0, [r7, #4]
|
|
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
|
|
800904e: 2301 movs r3, #1
|
|
8009050: 73fb strb r3, [r7, #15]
|
|
|
|
if ( hpcd->Init.speed == PCD_SPEED_HIGH)
|
|
8009052: 687b ldr r3, [r7, #4]
|
|
8009054: 79db ldrb r3, [r3, #7]
|
|
8009056: 2b00 cmp r3, #0
|
|
8009058: d102 bne.n 8009060 <HAL_PCD_ResetCallback+0x1a>
|
|
{
|
|
speed = USBD_SPEED_HIGH;
|
|
800905a: 2300 movs r3, #0
|
|
800905c: 73fb strb r3, [r7, #15]
|
|
800905e: e008 b.n 8009072 <HAL_PCD_ResetCallback+0x2c>
|
|
}
|
|
else if ( hpcd->Init.speed == PCD_SPEED_FULL)
|
|
8009060: 687b ldr r3, [r7, #4]
|
|
8009062: 79db ldrb r3, [r3, #7]
|
|
8009064: 2b02 cmp r3, #2
|
|
8009066: d102 bne.n 800906e <HAL_PCD_ResetCallback+0x28>
|
|
{
|
|
speed = USBD_SPEED_FULL;
|
|
8009068: 2301 movs r3, #1
|
|
800906a: 73fb strb r3, [r7, #15]
|
|
800906c: e001 b.n 8009072 <HAL_PCD_ResetCallback+0x2c>
|
|
}
|
|
else
|
|
{
|
|
Error_Handler();
|
|
800906e: f7f7 ff25 bl 8000ebc <Error_Handler>
|
|
}
|
|
/* Set Speed. */
|
|
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
|
|
8009072: 687b ldr r3, [r7, #4]
|
|
8009074: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
8009078: 7bfa ldrb r2, [r7, #15]
|
|
800907a: 4611 mov r1, r2
|
|
800907c: 4618 mov r0, r3
|
|
800907e: f7fe fd85 bl 8007b8c <USBD_LL_SetSpeed>
|
|
|
|
/* Reset Device. */
|
|
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
|
|
8009082: 687b ldr r3, [r7, #4]
|
|
8009084: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
8009088: 4618 mov r0, r3
|
|
800908a: f7fe fd2c bl 8007ae6 <USBD_LL_Reset>
|
|
}
|
|
800908e: bf00 nop
|
|
8009090: 3710 adds r7, #16
|
|
8009092: 46bd mov sp, r7
|
|
8009094: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08009098 <HAL_PCD_SuspendCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009098: b580 push {r7, lr}
|
|
800909a: b082 sub sp, #8
|
|
800909c: af00 add r7, sp, #0
|
|
800909e: 6078 str r0, [r7, #4]
|
|
/* Inform USB library that core enters in suspend Mode. */
|
|
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
|
|
80090a0: 687b ldr r3, [r7, #4]
|
|
80090a2: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
80090a6: 4618 mov r0, r3
|
|
80090a8: f7fe fd80 bl 8007bac <USBD_LL_Suspend>
|
|
__HAL_PCD_GATE_PHYCLOCK(hpcd);
|
|
80090ac: 687b ldr r3, [r7, #4]
|
|
80090ae: 681b ldr r3, [r3, #0]
|
|
80090b0: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80090b4: 681b ldr r3, [r3, #0]
|
|
80090b6: 687a ldr r2, [r7, #4]
|
|
80090b8: 6812 ldr r2, [r2, #0]
|
|
80090ba: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
80090be: f043 0301 orr.w r3, r3, #1
|
|
80090c2: 6013 str r3, [r2, #0]
|
|
/* Enter in STOP mode. */
|
|
/* USER CODE BEGIN 2 */
|
|
if (hpcd->Init.low_power_enable)
|
|
80090c4: 687b ldr r3, [r7, #4]
|
|
80090c6: 7adb ldrb r3, [r3, #11]
|
|
80090c8: 2b00 cmp r3, #0
|
|
80090ca: d005 beq.n 80090d8 <HAL_PCD_SuspendCallback+0x40>
|
|
{
|
|
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
80090cc: 4b04 ldr r3, [pc, #16] @ (80090e0 <HAL_PCD_SuspendCallback+0x48>)
|
|
80090ce: 691b ldr r3, [r3, #16]
|
|
80090d0: 4a03 ldr r2, [pc, #12] @ (80090e0 <HAL_PCD_SuspendCallback+0x48>)
|
|
80090d2: f043 0306 orr.w r3, r3, #6
|
|
80090d6: 6113 str r3, [r2, #16]
|
|
}
|
|
/* USER CODE END 2 */
|
|
}
|
|
80090d8: bf00 nop
|
|
80090da: 3708 adds r7, #8
|
|
80090dc: 46bd mov sp, r7
|
|
80090de: bd80 pop {r7, pc}
|
|
80090e0: e000ed00 .word 0xe000ed00
|
|
|
|
080090e4 <HAL_PCD_ResumeCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
80090e4: b580 push {r7, lr}
|
|
80090e6: b082 sub sp, #8
|
|
80090e8: af00 add r7, sp, #0
|
|
80090ea: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN 3 */
|
|
|
|
/* USER CODE END 3 */
|
|
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
|
|
80090ec: 687b ldr r3, [r7, #4]
|
|
80090ee: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
80090f2: 4618 mov r0, r3
|
|
80090f4: f7fe fd76 bl 8007be4 <USBD_LL_Resume>
|
|
}
|
|
80090f8: bf00 nop
|
|
80090fa: 3708 adds r7, #8
|
|
80090fc: 46bd mov sp, r7
|
|
80090fe: bd80 pop {r7, pc}
|
|
|
|
08009100 <HAL_PCD_ISOOUTIncompleteCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009100: b580 push {r7, lr}
|
|
8009102: b082 sub sp, #8
|
|
8009104: af00 add r7, sp, #0
|
|
8009106: 6078 str r0, [r7, #4]
|
|
8009108: 460b mov r3, r1
|
|
800910a: 70fb strb r3, [r7, #3]
|
|
USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
|
|
800910c: 687b ldr r3, [r7, #4]
|
|
800910e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
8009112: 78fa ldrb r2, [r7, #3]
|
|
8009114: 4611 mov r1, r2
|
|
8009116: 4618 mov r0, r3
|
|
8009118: f7fe fdce bl 8007cb8 <USBD_LL_IsoOUTIncomplete>
|
|
}
|
|
800911c: bf00 nop
|
|
800911e: 3708 adds r7, #8
|
|
8009120: 46bd mov sp, r7
|
|
8009122: bd80 pop {r7, pc}
|
|
|
|
08009124 <HAL_PCD_ISOINIncompleteCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009124: b580 push {r7, lr}
|
|
8009126: b082 sub sp, #8
|
|
8009128: af00 add r7, sp, #0
|
|
800912a: 6078 str r0, [r7, #4]
|
|
800912c: 460b mov r3, r1
|
|
800912e: 70fb strb r3, [r7, #3]
|
|
USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
|
|
8009130: 687b ldr r3, [r7, #4]
|
|
8009132: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
8009136: 78fa ldrb r2, [r7, #3]
|
|
8009138: 4611 mov r1, r2
|
|
800913a: 4618 mov r0, r3
|
|
800913c: f7fe fd8a bl 8007c54 <USBD_LL_IsoINIncomplete>
|
|
}
|
|
8009140: bf00 nop
|
|
8009142: 3708 adds r7, #8
|
|
8009144: 46bd mov sp, r7
|
|
8009146: bd80 pop {r7, pc}
|
|
|
|
08009148 <HAL_PCD_ConnectCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009148: b580 push {r7, lr}
|
|
800914a: b082 sub sp, #8
|
|
800914c: af00 add r7, sp, #0
|
|
800914e: 6078 str r0, [r7, #4]
|
|
USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
|
|
8009150: 687b ldr r3, [r7, #4]
|
|
8009152: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
8009156: 4618 mov r0, r3
|
|
8009158: f7fe fde0 bl 8007d1c <USBD_LL_DevConnected>
|
|
}
|
|
800915c: bf00 nop
|
|
800915e: 3708 adds r7, #8
|
|
8009160: 46bd mov sp, r7
|
|
8009162: bd80 pop {r7, pc}
|
|
|
|
08009164 <HAL_PCD_DisconnectCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009164: b580 push {r7, lr}
|
|
8009166: b082 sub sp, #8
|
|
8009168: af00 add r7, sp, #0
|
|
800916a: 6078 str r0, [r7, #4]
|
|
USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
|
|
800916c: 687b ldr r3, [r7, #4]
|
|
800916e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
8009172: 4618 mov r0, r3
|
|
8009174: f7fe fddd bl 8007d32 <USBD_LL_DevDisconnected>
|
|
}
|
|
8009178: bf00 nop
|
|
800917a: 3708 adds r7, #8
|
|
800917c: 46bd mov sp, r7
|
|
800917e: bd80 pop {r7, pc}
|
|
|
|
08009180 <USBD_LL_Init>:
|
|
* @brief Initializes the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8009180: b580 push {r7, lr}
|
|
8009182: b082 sub sp, #8
|
|
8009184: af00 add r7, sp, #0
|
|
8009186: 6078 str r0, [r7, #4]
|
|
/* Init USB Ip. */
|
|
if (pdev->id == DEVICE_FS) {
|
|
8009188: 687b ldr r3, [r7, #4]
|
|
800918a: 781b ldrb r3, [r3, #0]
|
|
800918c: 2b00 cmp r3, #0
|
|
800918e: d13c bne.n 800920a <USBD_LL_Init+0x8a>
|
|
/* Link the driver to the stack. */
|
|
hpcd_USB_OTG_FS.pData = pdev;
|
|
8009190: 4a20 ldr r2, [pc, #128] @ (8009214 <USBD_LL_Init+0x94>)
|
|
8009192: 687b ldr r3, [r7, #4]
|
|
8009194: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0
|
|
pdev->pData = &hpcd_USB_OTG_FS;
|
|
8009198: 687b ldr r3, [r7, #4]
|
|
800919a: 4a1e ldr r2, [pc, #120] @ (8009214 <USBD_LL_Init+0x94>)
|
|
800919c: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8
|
|
|
|
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
|
|
80091a0: 4b1c ldr r3, [pc, #112] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091a2: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
|
|
80091a6: 601a str r2, [r3, #0]
|
|
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
|
|
80091a8: 4b1a ldr r3, [pc, #104] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091aa: 2206 movs r2, #6
|
|
80091ac: 711a strb r2, [r3, #4]
|
|
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
|
|
80091ae: 4b19 ldr r3, [pc, #100] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091b0: 2202 movs r2, #2
|
|
80091b2: 71da strb r2, [r3, #7]
|
|
hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
|
|
80091b4: 4b17 ldr r3, [pc, #92] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091b6: 2200 movs r2, #0
|
|
80091b8: 719a strb r2, [r3, #6]
|
|
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
|
|
80091ba: 4b16 ldr r3, [pc, #88] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091bc: 2202 movs r2, #2
|
|
80091be: 725a strb r2, [r3, #9]
|
|
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
|
|
80091c0: 4b14 ldr r3, [pc, #80] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091c2: 2200 movs r2, #0
|
|
80091c4: 729a strb r2, [r3, #10]
|
|
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
|
|
80091c6: 4b13 ldr r3, [pc, #76] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091c8: 2200 movs r2, #0
|
|
80091ca: 72da strb r2, [r3, #11]
|
|
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
|
|
80091cc: 4b11 ldr r3, [pc, #68] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091ce: 2200 movs r2, #0
|
|
80091d0: 731a strb r2, [r3, #12]
|
|
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
|
|
80091d2: 4b10 ldr r3, [pc, #64] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091d4: 2200 movs r2, #0
|
|
80091d6: 739a strb r2, [r3, #14]
|
|
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
|
|
80091d8: 4b0e ldr r3, [pc, #56] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091da: 2200 movs r2, #0
|
|
80091dc: 73da strb r2, [r3, #15]
|
|
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
|
|
80091de: 480d ldr r0, [pc, #52] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091e0: f7f8 fe6c bl 8001ebc <HAL_PCD_Init>
|
|
80091e4: 4603 mov r3, r0
|
|
80091e6: 2b00 cmp r3, #0
|
|
80091e8: d001 beq.n 80091ee <USBD_LL_Init+0x6e>
|
|
{
|
|
Error_Handler( );
|
|
80091ea: f7f7 fe67 bl 8000ebc <Error_Handler>
|
|
HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback);
|
|
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback);
|
|
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
|
|
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
|
|
80091ee: 2180 movs r1, #128 @ 0x80
|
|
80091f0: 4808 ldr r0, [pc, #32] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091f2: f7fa f8b4 bl 800335e <HAL_PCDEx_SetRxFiFo>
|
|
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
|
|
80091f6: 2240 movs r2, #64 @ 0x40
|
|
80091f8: 2100 movs r1, #0
|
|
80091fa: 4806 ldr r0, [pc, #24] @ (8009214 <USBD_LL_Init+0x94>)
|
|
80091fc: f7fa f868 bl 80032d0 <HAL_PCDEx_SetTxFiFo>
|
|
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
|
|
8009200: 2280 movs r2, #128 @ 0x80
|
|
8009202: 2101 movs r1, #1
|
|
8009204: 4803 ldr r0, [pc, #12] @ (8009214 <USBD_LL_Init+0x94>)
|
|
8009206: f7fa f863 bl 80032d0 <HAL_PCDEx_SetTxFiFo>
|
|
}
|
|
return USBD_OK;
|
|
800920a: 2300 movs r3, #0
|
|
}
|
|
800920c: 4618 mov r0, r3
|
|
800920e: 3708 adds r7, #8
|
|
8009210: 46bd mov sp, r7
|
|
8009212: bd80 pop {r7, pc}
|
|
8009214: 20000994 .word 0x20000994
|
|
|
|
08009218 <USBD_LL_Start>:
|
|
* @brief Starts the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8009218: b580 push {r7, lr}
|
|
800921a: b084 sub sp, #16
|
|
800921c: af00 add r7, sp, #0
|
|
800921e: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8009220: 2300 movs r3, #0
|
|
8009222: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009224: 2300 movs r3, #0
|
|
8009226: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_Start(pdev->pData);
|
|
8009228: 687b ldr r3, [r7, #4]
|
|
800922a: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800922e: 4618 mov r0, r3
|
|
8009230: f7f8 ff5a bl 80020e8 <HAL_PCD_Start>
|
|
8009234: 4603 mov r3, r0
|
|
8009236: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009238: 7bfb ldrb r3, [r7, #15]
|
|
800923a: 4618 mov r0, r3
|
|
800923c: f000 f97e bl 800953c <USBD_Get_USB_Status>
|
|
8009240: 4603 mov r3, r0
|
|
8009242: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8009244: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8009246: 4618 mov r0, r3
|
|
8009248: 3710 adds r7, #16
|
|
800924a: 46bd mov sp, r7
|
|
800924c: bd80 pop {r7, pc}
|
|
|
|
0800924e <USBD_LL_OpenEP>:
|
|
* @param ep_type: Endpoint type
|
|
* @param ep_mps: Endpoint max packet size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
|
|
{
|
|
800924e: b580 push {r7, lr}
|
|
8009250: b084 sub sp, #16
|
|
8009252: af00 add r7, sp, #0
|
|
8009254: 6078 str r0, [r7, #4]
|
|
8009256: 4608 mov r0, r1
|
|
8009258: 4611 mov r1, r2
|
|
800925a: 461a mov r2, r3
|
|
800925c: 4603 mov r3, r0
|
|
800925e: 70fb strb r3, [r7, #3]
|
|
8009260: 460b mov r3, r1
|
|
8009262: 70bb strb r3, [r7, #2]
|
|
8009264: 4613 mov r3, r2
|
|
8009266: 803b strh r3, [r7, #0]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8009268: 2300 movs r3, #0
|
|
800926a: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800926c: 2300 movs r3, #0
|
|
800926e: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
|
|
8009270: 687b ldr r3, [r7, #4]
|
|
8009272: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
8009276: 78bb ldrb r3, [r7, #2]
|
|
8009278: 883a ldrh r2, [r7, #0]
|
|
800927a: 78f9 ldrb r1, [r7, #3]
|
|
800927c: f7f9 fc5b bl 8002b36 <HAL_PCD_EP_Open>
|
|
8009280: 4603 mov r3, r0
|
|
8009282: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009284: 7bfb ldrb r3, [r7, #15]
|
|
8009286: 4618 mov r0, r3
|
|
8009288: f000 f958 bl 800953c <USBD_Get_USB_Status>
|
|
800928c: 4603 mov r3, r0
|
|
800928e: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8009290: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8009292: 4618 mov r0, r3
|
|
8009294: 3710 adds r7, #16
|
|
8009296: 46bd mov sp, r7
|
|
8009298: bd80 pop {r7, pc}
|
|
|
|
0800929a <USBD_LL_CloseEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
800929a: b580 push {r7, lr}
|
|
800929c: b084 sub sp, #16
|
|
800929e: af00 add r7, sp, #0
|
|
80092a0: 6078 str r0, [r7, #4]
|
|
80092a2: 460b mov r3, r1
|
|
80092a4: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80092a6: 2300 movs r3, #0
|
|
80092a8: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80092aa: 2300 movs r3, #0
|
|
80092ac: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
|
|
80092ae: 687b ldr r3, [r7, #4]
|
|
80092b0: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
80092b4: 78fa ldrb r2, [r7, #3]
|
|
80092b6: 4611 mov r1, r2
|
|
80092b8: 4618 mov r0, r3
|
|
80092ba: f7f9 fca6 bl 8002c0a <HAL_PCD_EP_Close>
|
|
80092be: 4603 mov r3, r0
|
|
80092c0: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80092c2: 7bfb ldrb r3, [r7, #15]
|
|
80092c4: 4618 mov r0, r3
|
|
80092c6: f000 f939 bl 800953c <USBD_Get_USB_Status>
|
|
80092ca: 4603 mov r3, r0
|
|
80092cc: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
80092ce: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
80092d0: 4618 mov r0, r3
|
|
80092d2: 3710 adds r7, #16
|
|
80092d4: 46bd mov sp, r7
|
|
80092d6: bd80 pop {r7, pc}
|
|
|
|
080092d8 <USBD_LL_StallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
80092d8: b580 push {r7, lr}
|
|
80092da: b084 sub sp, #16
|
|
80092dc: af00 add r7, sp, #0
|
|
80092de: 6078 str r0, [r7, #4]
|
|
80092e0: 460b mov r3, r1
|
|
80092e2: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80092e4: 2300 movs r3, #0
|
|
80092e6: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80092e8: 2300 movs r3, #0
|
|
80092ea: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
|
|
80092ec: 687b ldr r3, [r7, #4]
|
|
80092ee: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
80092f2: 78fa ldrb r2, [r7, #3]
|
|
80092f4: 4611 mov r1, r2
|
|
80092f6: 4618 mov r0, r3
|
|
80092f8: f7f9 fd46 bl 8002d88 <HAL_PCD_EP_SetStall>
|
|
80092fc: 4603 mov r3, r0
|
|
80092fe: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009300: 7bfb ldrb r3, [r7, #15]
|
|
8009302: 4618 mov r0, r3
|
|
8009304: f000 f91a bl 800953c <USBD_Get_USB_Status>
|
|
8009308: 4603 mov r3, r0
|
|
800930a: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800930c: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800930e: 4618 mov r0, r3
|
|
8009310: 3710 adds r7, #16
|
|
8009312: 46bd mov sp, r7
|
|
8009314: bd80 pop {r7, pc}
|
|
|
|
08009316 <USBD_LL_ClearStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
8009316: b580 push {r7, lr}
|
|
8009318: b084 sub sp, #16
|
|
800931a: af00 add r7, sp, #0
|
|
800931c: 6078 str r0, [r7, #4]
|
|
800931e: 460b mov r3, r1
|
|
8009320: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8009322: 2300 movs r3, #0
|
|
8009324: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009326: 2300 movs r3, #0
|
|
8009328: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
|
|
800932a: 687b ldr r3, [r7, #4]
|
|
800932c: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
8009330: 78fa ldrb r2, [r7, #3]
|
|
8009332: 4611 mov r1, r2
|
|
8009334: 4618 mov r0, r3
|
|
8009336: f7f9 fd8a bl 8002e4e <HAL_PCD_EP_ClrStall>
|
|
800933a: 4603 mov r3, r0
|
|
800933c: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800933e: 7bfb ldrb r3, [r7, #15]
|
|
8009340: 4618 mov r0, r3
|
|
8009342: f000 f8fb bl 800953c <USBD_Get_USB_Status>
|
|
8009346: 4603 mov r3, r0
|
|
8009348: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800934a: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800934c: 4618 mov r0, r3
|
|
800934e: 3710 adds r7, #16
|
|
8009350: 46bd mov sp, r7
|
|
8009352: bd80 pop {r7, pc}
|
|
|
|
08009354 <USBD_LL_IsStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval Stall (1: Yes, 0: No)
|
|
*/
|
|
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
8009354: b480 push {r7}
|
|
8009356: b085 sub sp, #20
|
|
8009358: af00 add r7, sp, #0
|
|
800935a: 6078 str r0, [r7, #4]
|
|
800935c: 460b mov r3, r1
|
|
800935e: 70fb strb r3, [r7, #3]
|
|
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
|
|
8009360: 687b ldr r3, [r7, #4]
|
|
8009362: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
8009366: 60fb str r3, [r7, #12]
|
|
|
|
if((ep_addr & 0x80) == 0x80)
|
|
8009368: f997 3003 ldrsb.w r3, [r7, #3]
|
|
800936c: 2b00 cmp r3, #0
|
|
800936e: da0b bge.n 8009388 <USBD_LL_IsStallEP+0x34>
|
|
{
|
|
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
|
|
8009370: 78fb ldrb r3, [r7, #3]
|
|
8009372: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
8009376: 68f9 ldr r1, [r7, #12]
|
|
8009378: 4613 mov r3, r2
|
|
800937a: 00db lsls r3, r3, #3
|
|
800937c: 4413 add r3, r2
|
|
800937e: 009b lsls r3, r3, #2
|
|
8009380: 440b add r3, r1
|
|
8009382: 3316 adds r3, #22
|
|
8009384: 781b ldrb r3, [r3, #0]
|
|
8009386: e00b b.n 80093a0 <USBD_LL_IsStallEP+0x4c>
|
|
}
|
|
else
|
|
{
|
|
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
|
|
8009388: 78fb ldrb r3, [r7, #3]
|
|
800938a: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
800938e: 68f9 ldr r1, [r7, #12]
|
|
8009390: 4613 mov r3, r2
|
|
8009392: 00db lsls r3, r3, #3
|
|
8009394: 4413 add r3, r2
|
|
8009396: 009b lsls r3, r3, #2
|
|
8009398: 440b add r3, r1
|
|
800939a: f203 2356 addw r3, r3, #598 @ 0x256
|
|
800939e: 781b ldrb r3, [r3, #0]
|
|
}
|
|
}
|
|
80093a0: 4618 mov r0, r3
|
|
80093a2: 3714 adds r7, #20
|
|
80093a4: 46bd mov sp, r7
|
|
80093a6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80093aa: 4770 bx lr
|
|
|
|
080093ac <USBD_LL_SetUSBAddress>:
|
|
* @param pdev: Device handle
|
|
* @param dev_addr: Device address
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
|
|
{
|
|
80093ac: b580 push {r7, lr}
|
|
80093ae: b084 sub sp, #16
|
|
80093b0: af00 add r7, sp, #0
|
|
80093b2: 6078 str r0, [r7, #4]
|
|
80093b4: 460b mov r3, r1
|
|
80093b6: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80093b8: 2300 movs r3, #0
|
|
80093ba: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80093bc: 2300 movs r3, #0
|
|
80093be: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
|
|
80093c0: 687b ldr r3, [r7, #4]
|
|
80093c2: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
80093c6: 78fa ldrb r2, [r7, #3]
|
|
80093c8: 4611 mov r1, r2
|
|
80093ca: 4618 mov r0, r3
|
|
80093cc: f7f9 fb8f bl 8002aee <HAL_PCD_SetAddress>
|
|
80093d0: 4603 mov r3, r0
|
|
80093d2: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80093d4: 7bfb ldrb r3, [r7, #15]
|
|
80093d6: 4618 mov r0, r3
|
|
80093d8: f000 f8b0 bl 800953c <USBD_Get_USB_Status>
|
|
80093dc: 4603 mov r3, r0
|
|
80093de: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
80093e0: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
80093e2: 4618 mov r0, r3
|
|
80093e4: 3710 adds r7, #16
|
|
80093e6: 46bd mov sp, r7
|
|
80093e8: bd80 pop {r7, pc}
|
|
|
|
080093ea <USBD_LL_Transmit>:
|
|
* @param pbuf: Pointer to data to be sent
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
|
|
{
|
|
80093ea: b580 push {r7, lr}
|
|
80093ec: b086 sub sp, #24
|
|
80093ee: af00 add r7, sp, #0
|
|
80093f0: 60f8 str r0, [r7, #12]
|
|
80093f2: 607a str r2, [r7, #4]
|
|
80093f4: 603b str r3, [r7, #0]
|
|
80093f6: 460b mov r3, r1
|
|
80093f8: 72fb strb r3, [r7, #11]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80093fa: 2300 movs r3, #0
|
|
80093fc: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80093fe: 2300 movs r3, #0
|
|
8009400: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
|
|
8009402: 68fb ldr r3, [r7, #12]
|
|
8009404: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
8009408: 7af9 ldrb r1, [r7, #11]
|
|
800940a: 683b ldr r3, [r7, #0]
|
|
800940c: 687a ldr r2, [r7, #4]
|
|
800940e: f7f9 fc81 bl 8002d14 <HAL_PCD_EP_Transmit>
|
|
8009412: 4603 mov r3, r0
|
|
8009414: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009416: 7dfb ldrb r3, [r7, #23]
|
|
8009418: 4618 mov r0, r3
|
|
800941a: f000 f88f bl 800953c <USBD_Get_USB_Status>
|
|
800941e: 4603 mov r3, r0
|
|
8009420: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
8009422: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
8009424: 4618 mov r0, r3
|
|
8009426: 3718 adds r7, #24
|
|
8009428: 46bd mov sp, r7
|
|
800942a: bd80 pop {r7, pc}
|
|
|
|
0800942c <USBD_LL_PrepareReceive>:
|
|
* @param pbuf: Pointer to data to be received
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
|
|
{
|
|
800942c: b580 push {r7, lr}
|
|
800942e: b086 sub sp, #24
|
|
8009430: af00 add r7, sp, #0
|
|
8009432: 60f8 str r0, [r7, #12]
|
|
8009434: 607a str r2, [r7, #4]
|
|
8009436: 603b str r3, [r7, #0]
|
|
8009438: 460b mov r3, r1
|
|
800943a: 72fb strb r3, [r7, #11]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800943c: 2300 movs r3, #0
|
|
800943e: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009440: 2300 movs r3, #0
|
|
8009442: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
|
|
8009444: 68fb ldr r3, [r7, #12]
|
|
8009446: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
800944a: 7af9 ldrb r1, [r7, #11]
|
|
800944c: 683b ldr r3, [r7, #0]
|
|
800944e: 687a ldr r2, [r7, #4]
|
|
8009450: f7f9 fc25 bl 8002c9e <HAL_PCD_EP_Receive>
|
|
8009454: 4603 mov r3, r0
|
|
8009456: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009458: 7dfb ldrb r3, [r7, #23]
|
|
800945a: 4618 mov r0, r3
|
|
800945c: f000 f86e bl 800953c <USBD_Get_USB_Status>
|
|
8009460: 4603 mov r3, r0
|
|
8009462: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
8009464: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
8009466: 4618 mov r0, r3
|
|
8009468: 3718 adds r7, #24
|
|
800946a: 46bd mov sp, r7
|
|
800946c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08009470 <HAL_PCDEx_LPM_Callback>:
|
|
* @param hpcd: PCD handle
|
|
* @param msg: LPM message
|
|
* @retval None
|
|
*/
|
|
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
|
|
{
|
|
8009470: b580 push {r7, lr}
|
|
8009472: b082 sub sp, #8
|
|
8009474: af00 add r7, sp, #0
|
|
8009476: 6078 str r0, [r7, #4]
|
|
8009478: 460b mov r3, r1
|
|
800947a: 70fb strb r3, [r7, #3]
|
|
switch (msg)
|
|
800947c: 78fb ldrb r3, [r7, #3]
|
|
800947e: 2b00 cmp r3, #0
|
|
8009480: d002 beq.n 8009488 <HAL_PCDEx_LPM_Callback+0x18>
|
|
8009482: 2b01 cmp r3, #1
|
|
8009484: d01f beq.n 80094c6 <HAL_PCDEx_LPM_Callback+0x56>
|
|
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
8009486: e03b b.n 8009500 <HAL_PCDEx_LPM_Callback+0x90>
|
|
if (hpcd->Init.low_power_enable)
|
|
8009488: 687b ldr r3, [r7, #4]
|
|
800948a: 7adb ldrb r3, [r3, #11]
|
|
800948c: 2b00 cmp r3, #0
|
|
800948e: d007 beq.n 80094a0 <HAL_PCDEx_LPM_Callback+0x30>
|
|
SystemClock_Config();
|
|
8009490: f7f7 f8d2 bl 8000638 <SystemClock_Config>
|
|
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
8009494: 4b1c ldr r3, [pc, #112] @ (8009508 <HAL_PCDEx_LPM_Callback+0x98>)
|
|
8009496: 691b ldr r3, [r3, #16]
|
|
8009498: 4a1b ldr r2, [pc, #108] @ (8009508 <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800949a: f023 0306 bic.w r3, r3, #6
|
|
800949e: 6113 str r3, [r2, #16]
|
|
__HAL_PCD_UNGATE_PHYCLOCK(hpcd);
|
|
80094a0: 687b ldr r3, [r7, #4]
|
|
80094a2: 681b ldr r3, [r3, #0]
|
|
80094a4: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80094a8: 681b ldr r3, [r3, #0]
|
|
80094aa: 687a ldr r2, [r7, #4]
|
|
80094ac: 6812 ldr r2, [r2, #0]
|
|
80094ae: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
80094b2: f023 0301 bic.w r3, r3, #1
|
|
80094b6: 6013 str r3, [r2, #0]
|
|
USBD_LL_Resume(hpcd->pData);
|
|
80094b8: 687b ldr r3, [r7, #4]
|
|
80094ba: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
80094be: 4618 mov r0, r3
|
|
80094c0: f7fe fb90 bl 8007be4 <USBD_LL_Resume>
|
|
break;
|
|
80094c4: e01c b.n 8009500 <HAL_PCDEx_LPM_Callback+0x90>
|
|
__HAL_PCD_GATE_PHYCLOCK(hpcd);
|
|
80094c6: 687b ldr r3, [r7, #4]
|
|
80094c8: 681b ldr r3, [r3, #0]
|
|
80094ca: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80094ce: 681b ldr r3, [r3, #0]
|
|
80094d0: 687a ldr r2, [r7, #4]
|
|
80094d2: 6812 ldr r2, [r2, #0]
|
|
80094d4: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
80094d8: f043 0301 orr.w r3, r3, #1
|
|
80094dc: 6013 str r3, [r2, #0]
|
|
USBD_LL_Suspend(hpcd->pData);
|
|
80094de: 687b ldr r3, [r7, #4]
|
|
80094e0: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
80094e4: 4618 mov r0, r3
|
|
80094e6: f7fe fb61 bl 8007bac <USBD_LL_Suspend>
|
|
if (hpcd->Init.low_power_enable)
|
|
80094ea: 687b ldr r3, [r7, #4]
|
|
80094ec: 7adb ldrb r3, [r3, #11]
|
|
80094ee: 2b00 cmp r3, #0
|
|
80094f0: d005 beq.n 80094fe <HAL_PCDEx_LPM_Callback+0x8e>
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
80094f2: 4b05 ldr r3, [pc, #20] @ (8009508 <HAL_PCDEx_LPM_Callback+0x98>)
|
|
80094f4: 691b ldr r3, [r3, #16]
|
|
80094f6: 4a04 ldr r2, [pc, #16] @ (8009508 <HAL_PCDEx_LPM_Callback+0x98>)
|
|
80094f8: f043 0306 orr.w r3, r3, #6
|
|
80094fc: 6113 str r3, [r2, #16]
|
|
break;
|
|
80094fe: bf00 nop
|
|
}
|
|
8009500: bf00 nop
|
|
8009502: 3708 adds r7, #8
|
|
8009504: 46bd mov sp, r7
|
|
8009506: bd80 pop {r7, pc}
|
|
8009508: e000ed00 .word 0xe000ed00
|
|
|
|
0800950c <USBD_static_malloc>:
|
|
* @brief Static single allocation.
|
|
* @param size: Size of allocated memory
|
|
* @retval None
|
|
*/
|
|
void *USBD_static_malloc(uint32_t size)
|
|
{
|
|
800950c: b480 push {r7}
|
|
800950e: b083 sub sp, #12
|
|
8009510: af00 add r7, sp, #0
|
|
8009512: 6078 str r0, [r7, #4]
|
|
static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */
|
|
return mem;
|
|
8009514: 4b03 ldr r3, [pc, #12] @ (8009524 <USBD_static_malloc+0x18>)
|
|
}
|
|
8009516: 4618 mov r0, r3
|
|
8009518: 370c adds r7, #12
|
|
800951a: 46bd mov sp, r7
|
|
800951c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009520: 4770 bx lr
|
|
8009522: bf00 nop
|
|
8009524: 20000e78 .word 0x20000e78
|
|
|
|
08009528 <USBD_static_free>:
|
|
* @brief Dummy memory free
|
|
* @param p: Pointer to allocated memory address
|
|
* @retval None
|
|
*/
|
|
void USBD_static_free(void *p)
|
|
{
|
|
8009528: b480 push {r7}
|
|
800952a: b083 sub sp, #12
|
|
800952c: af00 add r7, sp, #0
|
|
800952e: 6078 str r0, [r7, #4]
|
|
|
|
}
|
|
8009530: bf00 nop
|
|
8009532: 370c adds r7, #12
|
|
8009534: 46bd mov sp, r7
|
|
8009536: f85d 7b04 ldr.w r7, [sp], #4
|
|
800953a: 4770 bx lr
|
|
|
|
0800953c <USBD_Get_USB_Status>:
|
|
* @brief Returns the USB status depending on the HAL status:
|
|
* @param hal_status: HAL status
|
|
* @retval USB status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
|
|
{
|
|
800953c: b480 push {r7}
|
|
800953e: b085 sub sp, #20
|
|
8009540: af00 add r7, sp, #0
|
|
8009542: 4603 mov r3, r0
|
|
8009544: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009546: 2300 movs r3, #0
|
|
8009548: 73fb strb r3, [r7, #15]
|
|
|
|
switch (hal_status)
|
|
800954a: 79fb ldrb r3, [r7, #7]
|
|
800954c: 2b03 cmp r3, #3
|
|
800954e: d817 bhi.n 8009580 <USBD_Get_USB_Status+0x44>
|
|
8009550: a201 add r2, pc, #4 @ (adr r2, 8009558 <USBD_Get_USB_Status+0x1c>)
|
|
8009552: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8009556: bf00 nop
|
|
8009558: 08009569 .word 0x08009569
|
|
800955c: 0800956f .word 0x0800956f
|
|
8009560: 08009575 .word 0x08009575
|
|
8009564: 0800957b .word 0x0800957b
|
|
{
|
|
case HAL_OK :
|
|
usb_status = USBD_OK;
|
|
8009568: 2300 movs r3, #0
|
|
800956a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800956c: e00b b.n 8009586 <USBD_Get_USB_Status+0x4a>
|
|
case HAL_ERROR :
|
|
usb_status = USBD_FAIL;
|
|
800956e: 2303 movs r3, #3
|
|
8009570: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009572: e008 b.n 8009586 <USBD_Get_USB_Status+0x4a>
|
|
case HAL_BUSY :
|
|
usb_status = USBD_BUSY;
|
|
8009574: 2301 movs r3, #1
|
|
8009576: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009578: e005 b.n 8009586 <USBD_Get_USB_Status+0x4a>
|
|
case HAL_TIMEOUT :
|
|
usb_status = USBD_FAIL;
|
|
800957a: 2303 movs r3, #3
|
|
800957c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800957e: e002 b.n 8009586 <USBD_Get_USB_Status+0x4a>
|
|
default :
|
|
usb_status = USBD_FAIL;
|
|
8009580: 2303 movs r3, #3
|
|
8009582: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009584: bf00 nop
|
|
}
|
|
return usb_status;
|
|
8009586: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009588: 4618 mov r0, r3
|
|
800958a: 3714 adds r7, #20
|
|
800958c: 46bd mov sp, r7
|
|
800958e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009592: 4770 bx lr
|
|
|
|
08009594 <memset>:
|
|
8009594: 4402 add r2, r0
|
|
8009596: 4603 mov r3, r0
|
|
8009598: 4293 cmp r3, r2
|
|
800959a: d100 bne.n 800959e <memset+0xa>
|
|
800959c: 4770 bx lr
|
|
800959e: f803 1b01 strb.w r1, [r3], #1
|
|
80095a2: e7f9 b.n 8009598 <memset+0x4>
|
|
|
|
080095a4 <__libc_init_array>:
|
|
80095a4: b570 push {r4, r5, r6, lr}
|
|
80095a6: 4d0d ldr r5, [pc, #52] @ (80095dc <__libc_init_array+0x38>)
|
|
80095a8: 4c0d ldr r4, [pc, #52] @ (80095e0 <__libc_init_array+0x3c>)
|
|
80095aa: 1b64 subs r4, r4, r5
|
|
80095ac: 10a4 asrs r4, r4, #2
|
|
80095ae: 2600 movs r6, #0
|
|
80095b0: 42a6 cmp r6, r4
|
|
80095b2: d109 bne.n 80095c8 <__libc_init_array+0x24>
|
|
80095b4: 4d0b ldr r5, [pc, #44] @ (80095e4 <__libc_init_array+0x40>)
|
|
80095b6: 4c0c ldr r4, [pc, #48] @ (80095e8 <__libc_init_array+0x44>)
|
|
80095b8: f000 f818 bl 80095ec <_init>
|
|
80095bc: 1b64 subs r4, r4, r5
|
|
80095be: 10a4 asrs r4, r4, #2
|
|
80095c0: 2600 movs r6, #0
|
|
80095c2: 42a6 cmp r6, r4
|
|
80095c4: d105 bne.n 80095d2 <__libc_init_array+0x2e>
|
|
80095c6: bd70 pop {r4, r5, r6, pc}
|
|
80095c8: f855 3b04 ldr.w r3, [r5], #4
|
|
80095cc: 4798 blx r3
|
|
80095ce: 3601 adds r6, #1
|
|
80095d0: e7ee b.n 80095b0 <__libc_init_array+0xc>
|
|
80095d2: f855 3b04 ldr.w r3, [r5], #4
|
|
80095d6: 4798 blx r3
|
|
80095d8: 3601 adds r6, #1
|
|
80095da: e7f2 b.n 80095c2 <__libc_init_array+0x1e>
|
|
80095dc: 08009660 .word 0x08009660
|
|
80095e0: 08009660 .word 0x08009660
|
|
80095e4: 08009660 .word 0x08009660
|
|
80095e8: 08009664 .word 0x08009664
|
|
|
|
080095ec <_init>:
|
|
80095ec: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80095ee: bf00 nop
|
|
80095f0: bcf8 pop {r3, r4, r5, r6, r7}
|
|
80095f2: bc08 pop {r3}
|
|
80095f4: 469e mov lr, r3
|
|
80095f6: 4770 bx lr
|
|
|
|
080095f8 <_fini>:
|
|
80095f8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80095fa: bf00 nop
|
|
80095fc: bcf8 pop {r3, r4, r5, r6, r7}
|
|
80095fe: bc08 pop {r3}
|
|
8009600: 469e mov lr, r3
|
|
8009602: 4770 bx lr
|