numpad configuration

This commit is contained in:
2025-09-23 14:46:22 -07:00
parent c97a0956e2
commit 59729453a5
18 changed files with 16612 additions and 15901 deletions

View File

@@ -146,7 +146,7 @@ extern "C" {
#define KEY_UP_ARROW 0x52
// Keypad
#define KEY_NUM_LOCK 0x53
#define NUM_LOCK 0x53
#define KEYPAD_SLASH 0x54
#define KEYPAD_ASTERISK 0x55
#define KEYPAD_MINUS 0x56

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@@ -53,8 +53,8 @@ typedef struct {
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
#define ROW 2
#define COL 2
#define ROW 6
#define COL 5
#define MAXQUEUE 256
#define MODE_INACTIVE 0
@@ -78,6 +78,15 @@ UART_HandleTypeDef huart1;
UART_HandleTypeDef huart2;
UART_HandleTypeDef huart3;
DMA_HandleTypeDef hdma_uart4_tx;
DMA_HandleTypeDef hdma_uart4_rx;
DMA_HandleTypeDef hdma_uart5_rx;
DMA_HandleTypeDef hdma_uart5_tx;
DMA_HandleTypeDef hdma_usart1_rx;
DMA_HandleTypeDef hdma_usart1_tx;
DMA_HandleTypeDef hdma_usart2_rx;
DMA_HandleTypeDef hdma_usart2_tx;
uint8_t UART1_RX_BUFF[UART_RX_BUFF_SIZE];
uint8_t UART2_RX_BUFF[UART_RX_BUFF_SIZE];
@@ -93,27 +102,38 @@ uint16_t UART5_BUFF_LASTPOS = 0;
HIDReport REPORT = {0, 0, {0}};
// Initialize column pins array (no pointer needed)
SwitchPins ROW_PINS[] = {
SwitchPins ROW_PINS[ROW] = {
{GPIOB, GPIO_PIN_10},
{GPIOB, GPIO_PIN_2},
{GPIOB, GPIO_PIN_1},
{GPIOB, GPIO_PIN_0},
{GPIOC, GPIO_PIN_5},
{GPIOC, GPIO_PIN_4},
{GPIOC, GPIO_PIN_5}
};
// Initialize row pins array
SwitchPins COLUMN_PINS[] = {
{GPIOC, GPIO_PIN_6},
{GPIOC, GPIO_PIN_7}
SwitchPins COLUMN_PINS[COL] = {
{GPIOA, GPIO_PIN_8},
{GPIOC, GPIO_PIN_9},
{GPIOC, GPIO_PIN_8},
{GPIOC, GPIO_PIN_7},
{GPIOC, GPIO_PIN_5}
};
// Initialize keycodes array
uint8_t KEYCODES[2][2] = {
{KEY_M, KEY_I}, // 'M', 'I'
{KEY_K, KEY_U} // 'K', 'U'
uint8_t KEYCODES[ROW][COL] = {
{0x00, KEY_F13, KEY_F14, KEY_F15, KEY_F16},
{KEY_F17, NUM_LOCK, KEYPAD_SLASH, KEYPAD_ASTERISK, KEYPAD_MINUS},
{KEY_F18, KEYPAD_7, KEYPAD_8, KEYPAD_9, KEYPAD_PLUS},
{KEY_F19, KEYPAD_4, KEYPAD_5, KEYPAD_6, 0x00},
{KEY_F20, KEYPAD_1, KEYPAD_2, KEYPAD_3, KEYPAD_ENTER},
{KEY_F21, KEYPAD_0, 0x00, KEYPAD_DOT, 0x00}
};
uint16_t DEPTH = 0;
extern USBD_HandleTypeDef hUsbDeviceFS;
volatile uint8_t MODE = MODE_MAINBOARD;
volatile uint8_t MODE = MODE_ACTIVE;
/* USER CODE END PV */

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@@ -1,18 +1,18 @@
../Core/Src/main.c:150:5:main 5
../Core/Src/main.c:245:6:SystemClock_Config 3
../Core/Src/main.c:292:13:MX_I2C1_Init 2
../Core/Src/main.c:326:13:MX_TIM2_Init 4
../Core/Src/main.c:375:13:MX_TIM3_Init 3
../Core/Src/main.c:424:13:MX_UART4_Init 2
../Core/Src/main.c:457:13:MX_UART5_Init 2
../Core/Src/main.c:490:13:MX_USART1_UART_Init 2
../Core/Src/main.c:523:13:MX_USART2_UART_Init 2
../Core/Src/main.c:556:13:MX_USART3_UART_Init 2
../Core/Src/main.c:583:13:MX_DMA_Init 1
../Core/Src/main.c:623:13:MX_GPIO_Init 1
../Core/Src/main.c:676:6:HAL_UART_RxCpltCallback 2
../Core/Src/main.c:683:6:handleUARTMessages 5
../Core/Src/main.c:710:6:addUSBReport 3
../Core/Src/main.c:718:6:matrixScan 4
../Core/Src/main.c:731:6:resetReport 1
../Core/Src/main.c:742:6:Error_Handler 1
../Core/Src/main.c:170:5:main 5
../Core/Src/main.c:265:6:SystemClock_Config 3
../Core/Src/main.c:312:13:MX_I2C1_Init 2
../Core/Src/main.c:346:13:MX_TIM2_Init 4
../Core/Src/main.c:395:13:MX_TIM3_Init 3
../Core/Src/main.c:444:13:MX_UART4_Init 2
../Core/Src/main.c:477:13:MX_UART5_Init 2
../Core/Src/main.c:510:13:MX_USART1_UART_Init 2
../Core/Src/main.c:543:13:MX_USART2_UART_Init 2
../Core/Src/main.c:576:13:MX_USART3_UART_Init 2
../Core/Src/main.c:603:13:MX_DMA_Init 1
../Core/Src/main.c:643:13:MX_GPIO_Init 1
../Core/Src/main.c:696:6:HAL_UART_RxCpltCallback 2
../Core/Src/main.c:703:6:handleUARTMessages 5
../Core/Src/main.c:730:6:addUSBReport 3
../Core/Src/main.c:738:6:matrixScan 4
../Core/Src/main.c:751:6:resetReport 1
../Core/Src/main.c:762:6:Error_Handler 1

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@@ -1,18 +1,18 @@
../Core/Src/main.c:150:5:main 24 static
../Core/Src/main.c:245:6:SystemClock_Config 88 static
../Core/Src/main.c:292:13:MX_I2C1_Init 8 static
../Core/Src/main.c:326:13:MX_TIM2_Init 48 static
../Core/Src/main.c:375:13:MX_TIM3_Init 56 static
../Core/Src/main.c:424:13:MX_UART4_Init 8 static
../Core/Src/main.c:457:13:MX_UART5_Init 8 static
../Core/Src/main.c:490:13:MX_USART1_UART_Init 8 static
../Core/Src/main.c:523:13:MX_USART2_UART_Init 8 static
../Core/Src/main.c:556:13:MX_USART3_UART_Init 8 static
../Core/Src/main.c:583:13:MX_DMA_Init 16 static
../Core/Src/main.c:623:13:MX_GPIO_Init 48 static
../Core/Src/main.c:676:6:HAL_UART_RxCpltCallback 16 static
../Core/Src/main.c:683:6:handleUARTMessages 56 static
../Core/Src/main.c:710:6:addUSBReport 24 static
../Core/Src/main.c:718:6:matrixScan 16 static
../Core/Src/main.c:731:6:resetReport 8 static
../Core/Src/main.c:742:6:Error_Handler 4 static,ignoring_inline_asm
../Core/Src/main.c:170:5:main 24 static
../Core/Src/main.c:265:6:SystemClock_Config 88 static
../Core/Src/main.c:312:13:MX_I2C1_Init 8 static
../Core/Src/main.c:346:13:MX_TIM2_Init 48 static
../Core/Src/main.c:395:13:MX_TIM3_Init 56 static
../Core/Src/main.c:444:13:MX_UART4_Init 8 static
../Core/Src/main.c:477:13:MX_UART5_Init 8 static
../Core/Src/main.c:510:13:MX_USART1_UART_Init 8 static
../Core/Src/main.c:543:13:MX_USART2_UART_Init 8 static
../Core/Src/main.c:576:13:MX_USART3_UART_Init 8 static
../Core/Src/main.c:603:13:MX_DMA_Init 16 static
../Core/Src/main.c:643:13:MX_GPIO_Init 48 static
../Core/Src/main.c:696:6:HAL_UART_RxCpltCallback 16 static
../Core/Src/main.c:703:6:handleUARTMessages 56 static
../Core/Src/main.c:730:6:addUSBReport 24 static
../Core/Src/main.c:738:6:matrixScan 16 static
../Core/Src/main.c:751:6:resetReport 8 static
../Core/Src/main.c:762:6:Error_Handler 4 static,ignoring_inline_asm

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