24975 lines
906 KiB
Plaintext
24975 lines
906 KiB
Plaintext
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modularkbd.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000001c4 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00009444 080001c4 080001c4 000011c4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000054 08009608 08009608 0000a608 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 0800965c 0800965c 0000b188 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 0800965c 0800965c 0000a65c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 08009664 08009664 0000b188 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08009664 08009664 0000a664 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 08009668 08009668 0000a668 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 00000188 20000000 0800966c 0000b000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000d54 20000188 080097f4 0000b188 2**2
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ALLOC
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10 ._user_heap_stack 00000604 20000edc 080097f4 0000bedc 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0000b188 2**0
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CONTENTS, READONLY
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12 .debug_info 000197cf 00000000 00000000 0000b1b8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00003858 00000000 00000000 00024987 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 000016a8 00000000 00000000 000281e0 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 000011b4 00000000 00000000 00029888 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00025576 00000000 00000000 0002aa3c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 0001c096 00000000 00000000 0004ffb2 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000d7d5c 00000000 00000000 0006c048 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 00143da4 2**0
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CONTENTS, READONLY
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20 .debug_frame 000060f0 00000000 00000000 00143de8 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000062 00000000 00000000 00149ed8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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080001c4 <__do_global_dtors_aux>:
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80001c4: b510 push {r4, lr}
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80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>)
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80001c8: 7823 ldrb r3, [r4, #0]
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80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16>
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80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>)
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80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12>
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80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>)
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80001d2: f3af 8000 nop.w
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80001d6: 2301 movs r3, #1
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80001d8: 7023 strb r3, [r4, #0]
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80001da: bd10 pop {r4, pc}
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80001dc: 20000188 .word 0x20000188
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80001e0: 00000000 .word 0x00000000
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80001e4: 080095f0 .word 0x080095f0
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080001e8 <frame_dummy>:
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80001e8: b508 push {r3, lr}
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80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 <frame_dummy+0x10>)
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80001ec: b11b cbz r3, 80001f6 <frame_dummy+0xe>
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80001ee: 4903 ldr r1, [pc, #12] @ (80001fc <frame_dummy+0x14>)
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80001f0: 4803 ldr r0, [pc, #12] @ (8000200 <frame_dummy+0x18>)
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80001f2: f3af 8000 nop.w
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80001f6: bd08 pop {r3, pc}
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80001f8: 00000000 .word 0x00000000
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80001fc: 2000018c .word 0x2000018c
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8000200: 080095f0 .word 0x080095f0
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08000204 <__aeabi_uldivmod>:
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8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18>
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8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18>
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8000208: 2900 cmp r1, #0
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800020a: bf08 it eq
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800020c: 2800 cmpeq r0, #0
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800020e: bf1c itt ne
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8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
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8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
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8000218: f000 b988 b.w 800052c <__aeabi_idiv0>
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800021c: f1ad 0c08 sub.w ip, sp, #8
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8000220: e96d ce04 strd ip, lr, [sp, #-16]!
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8000224: f000 f806 bl 8000234 <__udivmoddi4>
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8000228: f8dd e004 ldr.w lr, [sp, #4]
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800022c: e9dd 2302 ldrd r2, r3, [sp, #8]
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8000230: b004 add sp, #16
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8000232: 4770 bx lr
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08000234 <__udivmoddi4>:
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8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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8000238: 9d08 ldr r5, [sp, #32]
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800023a: 468e mov lr, r1
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800023c: 4604 mov r4, r0
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800023e: 4688 mov r8, r1
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8000240: 2b00 cmp r3, #0
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8000242: d14a bne.n 80002da <__udivmoddi4+0xa6>
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8000244: 428a cmp r2, r1
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8000246: 4617 mov r7, r2
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8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc>
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800024a: fab2 f682 clz r6, r2
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800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30>
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8000250: f1c6 0320 rsb r3, r6, #32
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8000254: fa01 f806 lsl.w r8, r1, r6
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8000258: fa20 f303 lsr.w r3, r0, r3
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800025c: 40b7 lsls r7, r6
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800025e: ea43 0808 orr.w r8, r3, r8
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8000262: 40b4 lsls r4, r6
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8000264: ea4f 4e17 mov.w lr, r7, lsr #16
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8000268: fa1f fc87 uxth.w ip, r7
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800026c: fbb8 f1fe udiv r1, r8, lr
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8000270: 0c23 lsrs r3, r4, #16
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8000272: fb0e 8811 mls r8, lr, r1, r8
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8000276: ea43 4308 orr.w r3, r3, r8, lsl #16
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800027a: fb01 f20c mul.w r2, r1, ip
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800027e: 429a cmp r2, r3
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8000280: d909 bls.n 8000296 <__udivmoddi4+0x62>
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8000282: 18fb adds r3, r7, r3
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8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
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8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c>
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800028c: 429a cmp r2, r3
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800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c>
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8000292: 3902 subs r1, #2
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8000294: 443b add r3, r7
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8000296: 1a9a subs r2, r3, r2
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8000298: b2a3 uxth r3, r4
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800029a: fbb2 f0fe udiv r0, r2, lr
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800029e: fb0e 2210 mls r2, lr, r0, r2
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80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16
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80002a6: fb00 fc0c mul.w ip, r0, ip
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80002aa: 459c cmp ip, r3
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80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e>
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80002ae: 18fb adds r3, r7, r3
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80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
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80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230>
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80002b8: 459c cmp ip, r3
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80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230>
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80002be: 443b add r3, r7
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80002c0: 3802 subs r0, #2
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80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16
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80002c6: eba3 030c sub.w r3, r3, ip
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80002ca: 2100 movs r1, #0
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80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2>
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80002ce: 40f3 lsrs r3, r6
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80002d0: 2200 movs r2, #0
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80002d2: e9c5 3200 strd r3, r2, [r5]
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80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002da: 428b cmp r3, r1
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80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6>
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80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0>
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80002e0: e9c5 0100 strd r0, r1, [r5]
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80002e4: 2100 movs r1, #0
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80002e6: 4608 mov r0, r1
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80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2>
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80002ea: fab3 f183 clz r1, r3
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80002ee: 2900 cmp r1, #0
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80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c>
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80002f2: 4573 cmp r3, lr
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80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8>
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80002f6: 4282 cmp r2, r0
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80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2>
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80002fc: 1a84 subs r4, r0, r2
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80002fe: eb6e 0203 sbc.w r2, lr, r3
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8000302: 2001 movs r0, #1
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8000304: 4690 mov r8, r2
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8000306: 2d00 cmp r5, #0
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8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2>
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800030a: e9c5 4800 strd r4, r8, [r5]
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800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2>
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8000310: 2a00 cmp r2, #0
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8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202>
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8000316: fab2 f682 clz r6, r2
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800031a: 2e00 cmp r6, #0
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800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234>
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8000320: 1a8a subs r2, r1, r2
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8000322: 0c03 lsrs r3, r0, #16
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8000324: ea4f 4e17 mov.w lr, r7, lsr #16
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8000328: b280 uxth r0, r0
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800032a: b2bc uxth r4, r7
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800032c: 2101 movs r1, #1
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800032e: fbb2 fcfe udiv ip, r2, lr
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8000332: fb0e 221c mls r2, lr, ip, r2
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8000336: ea43 4302 orr.w r3, r3, r2, lsl #16
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800033a: fb04 f20c mul.w r2, r4, ip
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800033e: 429a cmp r2, r3
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8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e>
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8000342: 18fb adds r3, r7, r3
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8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
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8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c>
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800034a: 429a cmp r2, r3
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800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc>
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8000350: 46c4 mov ip, r8
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8000352: 1a9b subs r3, r3, r2
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8000354: fbb3 f2fe udiv r2, r3, lr
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8000358: fb0e 3312 mls r3, lr, r2, r3
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800035c: ea40 4303 orr.w r3, r0, r3, lsl #16
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8000360: fb02 f404 mul.w r4, r2, r4
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8000364: 429c cmp r4, r3
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8000366: d907 bls.n 8000378 <__udivmoddi4+0x144>
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8000368: 18fb adds r3, r7, r3
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800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
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800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142>
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8000370: 429c cmp r4, r3
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8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6>
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8000376: 4602 mov r2, r0
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8000378: 1b1b subs r3, r3, r4
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800037a: ea42 400c orr.w r0, r2, ip, lsl #16
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800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98>
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8000380: f1c1 0620 rsb r6, r1, #32
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8000384: 408b lsls r3, r1
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8000386: fa22 f706 lsr.w r7, r2, r6
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800038a: 431f orrs r7, r3
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800038c: fa0e f401 lsl.w r4, lr, r1
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8000390: fa20 f306 lsr.w r3, r0, r6
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8000394: fa2e fe06 lsr.w lr, lr, r6
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8000398: ea4f 4917 mov.w r9, r7, lsr #16
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800039c: 4323 orrs r3, r4
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800039e: fa00 f801 lsl.w r8, r0, r1
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80003a2: fa1f fc87 uxth.w ip, r7
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80003a6: fbbe f0f9 udiv r0, lr, r9
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80003aa: 0c1c lsrs r4, r3, #16
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80003ac: fb09 ee10 mls lr, r9, r0, lr
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80003b0: ea44 440e orr.w r4, r4, lr, lsl #16
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80003b4: fb00 fe0c mul.w lr, r0, ip
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80003b8: 45a6 cmp lr, r4
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80003ba: fa02 f201 lsl.w r2, r2, r1
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80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0>
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80003c0: 193c adds r4, r7, r4
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80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
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80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce>
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80003ca: 45a6 cmp lr, r4
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80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce>
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80003d0: 3802 subs r0, #2
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80003d2: 443c add r4, r7
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80003d4: eba4 040e sub.w r4, r4, lr
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80003d8: fa1f fe83 uxth.w lr, r3
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80003dc: fbb4 f3f9 udiv r3, r4, r9
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80003e0: fb09 4413 mls r4, r9, r3, r4
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80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16
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80003e8: fb03 fc0c mul.w ip, r3, ip
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80003ec: 45a4 cmp ip, r4
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80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce>
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80003f0: 193c adds r4, r7, r4
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80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
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80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca>
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80003fa: 45a4 cmp ip, r4
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80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca>
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80003fe: 3b02 subs r3, #2
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8000400: 443c add r4, r7
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8000402: ea43 4000 orr.w r0, r3, r0, lsl #16
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8000406: eba4 040c sub.w r4, r4, ip
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800040a: fba0 ec02 umull lr, ip, r0, r2
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800040e: 4564 cmp r4, ip
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8000410: 4673 mov r3, lr
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8000412: 46e1 mov r9, ip
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8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8>
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8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4>
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8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe>
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800041a: ebb8 0203 subs.w r2, r8, r3
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800041e: eb64 0409 sbc.w r4, r4, r9
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8000422: fa04 f606 lsl.w r6, r4, r6
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8000426: fa22 f301 lsr.w r3, r2, r1
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800042a: 431e orrs r6, r3
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800042c: 40cc lsrs r4, r1
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800042e: e9c5 6400 strd r6, r4, [r5]
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8000432: 2100 movs r1, #0
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8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2>
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8000436: fbb1 fcf2 udiv ip, r1, r2
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800043a: 0c01 lsrs r1, r0, #16
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800043c: ea41 410e orr.w r1, r1, lr, lsl #16
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8000440: b280 uxth r0, r0
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8000442: ea40 4201 orr.w r2, r0, r1, lsl #16
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8000446: 463b mov r3, r7
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8000448: 4638 mov r0, r7
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800044a: 463c mov r4, r7
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800044c: 46b8 mov r8, r7
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800044e: 46be mov lr, r7
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8000450: 2620 movs r6, #32
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8000452: fbb1 f1f7 udiv r1, r1, r7
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8000456: eba2 0208 sub.w r2, r2, r8
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800045a: ea41 410c orr.w r1, r1, ip, lsl #16
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800045e: e766 b.n 800032e <__udivmoddi4+0xfa>
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8000460: 4601 mov r1, r0
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8000462: e718 b.n 8000296 <__udivmoddi4+0x62>
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8000464: 4610 mov r0, r2
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8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e>
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8000468: f1c6 0220 rsb r2, r6, #32
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800046c: fa2e f302 lsr.w r3, lr, r2
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8000470: 40b7 lsls r7, r6
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8000472: 40b1 lsls r1, r6
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8000474: fa20 f202 lsr.w r2, r0, r2
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8000478: ea4f 4e17 mov.w lr, r7, lsr #16
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800047c: 430a orrs r2, r1
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800047e: fbb3 f8fe udiv r8, r3, lr
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8000482: b2bc uxth r4, r7
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8000484: fb0e 3318 mls r3, lr, r8, r3
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8000488: 0c11 lsrs r1, r2, #16
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800048a: ea41 4103 orr.w r1, r1, r3, lsl #16
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800048e: fb08 f904 mul.w r9, r8, r4
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8000492: 40b0 lsls r0, r6
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8000494: 4589 cmp r9, r1
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8000496: ea4f 4310 mov.w r3, r0, lsr #16
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800049a: b280 uxth r0, r0
|
|
800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8>
|
|
800049e: 1879 adds r1, r7, r1
|
|
80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276>
|
|
80004a6: 4589 cmp r9, r1
|
|
80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6>
|
|
80004aa: eba1 0109 sub.w r1, r1, r9
|
|
80004ae: fbb1 f9fe udiv r9, r1, lr
|
|
80004b2: fb09 f804 mul.w r8, r9, r4
|
|
80004b6: fb0e 1119 mls r1, lr, r9, r1
|
|
80004ba: b292 uxth r2, r2
|
|
80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
80004c0: 4542 cmp r2, r8
|
|
80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4>
|
|
80004c4: 18ba adds r2, r7, r2
|
|
80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222>
|
|
80004cc: 4542 cmp r2, r8
|
|
80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222>
|
|
80004d0: f1a9 0102 sub.w r1, r9, #2
|
|
80004d4: 443a add r2, r7
|
|
80004d6: e7be b.n 8000456 <__udivmoddi4+0x222>
|
|
80004d8: 45f0 cmp r8, lr
|
|
80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4>
|
|
80004dc: ebbe 0302 subs.w r3, lr, r2
|
|
80004e0: eb6c 0c07 sbc.w ip, ip, r7
|
|
80004e4: 3801 subs r0, #1
|
|
80004e6: 46e1 mov r9, ip
|
|
80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4>
|
|
80004ea: eba7 0909 sub.w r9, r7, r9
|
|
80004ee: 4449 add r1, r9
|
|
80004f0: f1a8 0c02 sub.w ip, r8, #2
|
|
80004f4: fbb1 f9fe udiv r9, r1, lr
|
|
80004f8: fb09 f804 mul.w r8, r9, r4
|
|
80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282>
|
|
80004fe: 4673 mov r3, lr
|
|
8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce>
|
|
8000502: 4650 mov r0, sl
|
|
8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0>
|
|
8000506: 4608 mov r0, r1
|
|
8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2>
|
|
800050a: 443b add r3, r7
|
|
800050c: 3a02 subs r2, #2
|
|
800050e: e733 b.n 8000378 <__udivmoddi4+0x144>
|
|
8000510: f1ac 0c02 sub.w ip, ip, #2
|
|
8000514: 443b add r3, r7
|
|
8000516: e71c b.n 8000352 <__udivmoddi4+0x11e>
|
|
8000518: 4649 mov r1, r9
|
|
800051a: e79c b.n 8000456 <__udivmoddi4+0x222>
|
|
800051c: eba1 0109 sub.w r1, r1, r9
|
|
8000520: 46c4 mov ip, r8
|
|
8000522: fbb1 f9fe udiv r9, r1, lr
|
|
8000526: fb09 f804 mul.w r8, r9, r4
|
|
800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282>
|
|
|
|
0800052c <__aeabi_idiv0>:
|
|
800052c: 4770 bx lr
|
|
800052e: bf00 nop
|
|
|
|
08000530 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8000530: b580 push {r7, lr}
|
|
8000532: b084 sub sp, #16
|
|
8000534: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8000536: f000 ff8b bl 8001450 <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
800053a: f000 f87d bl 8000638 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
800053e: f000 faf9 bl 8000b34 <MX_GPIO_Init>
|
|
MX_TIM2_Init();
|
|
8000542: f000 f913 bl 800076c <MX_TIM2_Init>
|
|
MX_TIM3_Init();
|
|
8000546: f000 f969 bl 800081c <MX_TIM3_Init>
|
|
MX_DMA_Init();
|
|
800054a: f000 fa8d bl 8000a68 <MX_DMA_Init>
|
|
MX_UART4_Init();
|
|
800054e: f000 f9b9 bl 80008c4 <MX_UART4_Init>
|
|
MX_UART5_Init();
|
|
8000552: f000 f9e1 bl 8000918 <MX_UART5_Init>
|
|
MX_USART1_UART_Init();
|
|
8000556: f000 fa09 bl 800096c <MX_USART1_UART_Init>
|
|
MX_USART2_UART_Init();
|
|
800055a: f000 fa31 bl 80009c0 <MX_USART2_UART_Init>
|
|
MX_I2C1_Init();
|
|
800055e: f000 f8d7 bl 8000710 <MX_I2C1_Init>
|
|
MX_USART3_UART_Init();
|
|
8000562: f000 fa57 bl 8000a14 <MX_USART3_UART_Init>
|
|
MX_USB_DEVICE_Init();
|
|
8000566: f008 fb69 bl 8008c3c <MX_USB_DEVICE_Init>
|
|
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
if (MODE != MODE_INACTIVE){
|
|
800056a: 4b27 ldr r3, [pc, #156] @ (8000608 <main+0xd8>)
|
|
800056c: 781b ldrb r3, [r3, #0]
|
|
800056e: b2db uxtb r3, r3
|
|
8000570: 2b00 cmp r3, #0
|
|
8000572: d023 beq.n 80005bc <main+0x8c>
|
|
//Reset Report
|
|
resetReport();
|
|
8000574: f000 fc94 bl 8000ea0 <resetReport>
|
|
|
|
//Query Neighbors
|
|
UARTMessage query;
|
|
query.depth = DEPTH;
|
|
8000578: 4b24 ldr r3, [pc, #144] @ (800060c <main+0xdc>)
|
|
800057a: 881b ldrh r3, [r3, #0]
|
|
800057c: 803b strh r3, [r7, #0]
|
|
query.msgType = 0x01;
|
|
800057e: 2301 movs r3, #1
|
|
8000580: 807b strh r3, [r7, #2]
|
|
memset(query.keypress, 1,sizeof(query.keypress));
|
|
8000582: 463b mov r3, r7
|
|
8000584: 3304 adds r3, #4
|
|
8000586: 220c movs r2, #12
|
|
8000588: 2101 movs r1, #1
|
|
800058a: 4618 mov r0, r3
|
|
800058c: f009 f804 bl 8009598 <memset>
|
|
|
|
matrixScan();
|
|
8000590: f000 fc2c bl 8000dec <matrixScan>
|
|
|
|
switch (MODE){
|
|
8000594: 4b1c ldr r3, [pc, #112] @ (8000608 <main+0xd8>)
|
|
8000596: 781b ldrb r3, [r3, #0]
|
|
8000598: b2db uxtb r3, r3
|
|
800059a: 2b01 cmp r3, #1
|
|
800059c: d008 beq.n 80005b0 <main+0x80>
|
|
800059e: 2b02 cmp r3, #2
|
|
80005a0: d129 bne.n 80005f6 <main+0xc6>
|
|
|
|
case MODE_ACTIVE:
|
|
HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&query, sizeof(query));
|
|
80005a2: 463b mov r3, r7
|
|
80005a4: 2210 movs r2, #16
|
|
80005a6: 4619 mov r1, r3
|
|
80005a8: 4819 ldr r0, [pc, #100] @ (8000610 <main+0xe0>)
|
|
80005aa: f004 fc95 bl 8004ed8 <HAL_UART_Transmit_DMA>
|
|
break;
|
|
80005ae: e022 b.n 80005f6 <main+0xc6>
|
|
|
|
case MODE_MAINBOARD:
|
|
//Send to USB
|
|
USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT));
|
|
80005b0: 220e movs r2, #14
|
|
80005b2: 4918 ldr r1, [pc, #96] @ (8000614 <main+0xe4>)
|
|
80005b4: 4818 ldr r0, [pc, #96] @ (8000618 <main+0xe8>)
|
|
80005b6: f006 ff61 bl 800747c <USBD_HID_SendReport>
|
|
break;
|
|
80005ba: e01c b.n 80005f6 <main+0xc6>
|
|
//TODO: Send heartbeat signal to child nodes
|
|
|
|
|
|
}else{ //INACTIVE Mode
|
|
//Check if the USB is enumerated/connected.
|
|
if (hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED) {
|
|
80005bc: 4b16 ldr r3, [pc, #88] @ (8000618 <main+0xe8>)
|
|
80005be: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80005c2: b2db uxtb r3, r3
|
|
80005c4: 2b03 cmp r3, #3
|
|
80005c6: d116 bne.n 80005f6 <main+0xc6>
|
|
MODE = MODE_MAINBOARD;
|
|
80005c8: 4b0f ldr r3, [pc, #60] @ (8000608 <main+0xd8>)
|
|
80005ca: 2201 movs r2, #1
|
|
80005cc: 701a strb r2, [r3, #0]
|
|
//Enable DMA RX
|
|
HAL_UART_Receive_DMA(&huart1, UART1_RX_BUFF, UART_RX_BUFF_SIZE);
|
|
80005ce: 2240 movs r2, #64 @ 0x40
|
|
80005d0: 4912 ldr r1, [pc, #72] @ (800061c <main+0xec>)
|
|
80005d2: 4813 ldr r0, [pc, #76] @ (8000620 <main+0xf0>)
|
|
80005d4: f004 fcfc bl 8004fd0 <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart2, UART2_RX_BUFF, UART_RX_BUFF_SIZE);
|
|
80005d8: 2240 movs r2, #64 @ 0x40
|
|
80005da: 4912 ldr r1, [pc, #72] @ (8000624 <main+0xf4>)
|
|
80005dc: 4812 ldr r0, [pc, #72] @ (8000628 <main+0xf8>)
|
|
80005de: f004 fcf7 bl 8004fd0 <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart4, UART4_RX_BUFF, UART_RX_BUFF_SIZE);
|
|
80005e2: 2240 movs r2, #64 @ 0x40
|
|
80005e4: 4911 ldr r1, [pc, #68] @ (800062c <main+0xfc>)
|
|
80005e6: 480a ldr r0, [pc, #40] @ (8000610 <main+0xe0>)
|
|
80005e8: f004 fcf2 bl 8004fd0 <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart5, UART5_RX_BUFF, UART_RX_BUFF_SIZE);
|
|
80005ec: 2240 movs r2, #64 @ 0x40
|
|
80005ee: 4910 ldr r1, [pc, #64] @ (8000630 <main+0x100>)
|
|
80005f0: 4810 ldr r0, [pc, #64] @ (8000634 <main+0x104>)
|
|
80005f2: f004 fced bl 8004fd0 <HAL_UART_Receive_DMA>
|
|
}else{
|
|
|
|
}
|
|
}
|
|
HAL_Delay(USBD_HID_GetPollingInterval(&hUsbDeviceFS));
|
|
80005f6: 4808 ldr r0, [pc, #32] @ (8000618 <main+0xe8>)
|
|
80005f8: f006 ff70 bl 80074dc <USBD_HID_GetPollingInterval>
|
|
80005fc: 4603 mov r3, r0
|
|
80005fe: 4618 mov r0, r3
|
|
8000600: f000 ff98 bl 8001534 <HAL_Delay>
|
|
if (MODE != MODE_INACTIVE){
|
|
8000604: e7b1 b.n 800056a <main+0x3a>
|
|
8000606: bf00 nop
|
|
8000608: 20000076 .word 0x20000076
|
|
800060c: 200004fe .word 0x200004fe
|
|
8000610: 20000288 .word 0x20000288
|
|
8000614: 200004f0 .word 0x200004f0
|
|
8000618: 20000508 .word 0x20000508
|
|
800061c: 200003f0 .word 0x200003f0
|
|
8000620: 20000318 .word 0x20000318
|
|
8000624: 20000430 .word 0x20000430
|
|
8000628: 20000360 .word 0x20000360
|
|
800062c: 20000470 .word 0x20000470
|
|
8000630: 200004b0 .word 0x200004b0
|
|
8000634: 200002d0 .word 0x200002d0
|
|
|
|
08000638 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8000638: b580 push {r7, lr}
|
|
800063a: b094 sub sp, #80 @ 0x50
|
|
800063c: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
800063e: f107 031c add.w r3, r7, #28
|
|
8000642: 2234 movs r2, #52 @ 0x34
|
|
8000644: 2100 movs r1, #0
|
|
8000646: 4618 mov r0, r3
|
|
8000648: f008 ffa6 bl 8009598 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
800064c: f107 0308 add.w r3, r7, #8
|
|
8000650: 2200 movs r2, #0
|
|
8000652: 601a str r2, [r3, #0]
|
|
8000654: 605a str r2, [r3, #4]
|
|
8000656: 609a str r2, [r3, #8]
|
|
8000658: 60da str r2, [r3, #12]
|
|
800065a: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800065c: 2300 movs r3, #0
|
|
800065e: 607b str r3, [r7, #4]
|
|
8000660: 4b29 ldr r3, [pc, #164] @ (8000708 <SystemClock_Config+0xd0>)
|
|
8000662: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000664: 4a28 ldr r2, [pc, #160] @ (8000708 <SystemClock_Config+0xd0>)
|
|
8000666: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800066a: 6413 str r3, [r2, #64] @ 0x40
|
|
800066c: 4b26 ldr r3, [pc, #152] @ (8000708 <SystemClock_Config+0xd0>)
|
|
800066e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000670: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8000674: 607b str r3, [r7, #4]
|
|
8000676: 687b ldr r3, [r7, #4]
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
|
|
8000678: 2300 movs r3, #0
|
|
800067a: 603b str r3, [r7, #0]
|
|
800067c: 4b23 ldr r3, [pc, #140] @ (800070c <SystemClock_Config+0xd4>)
|
|
800067e: 681b ldr r3, [r3, #0]
|
|
8000680: f423 4340 bic.w r3, r3, #49152 @ 0xc000
|
|
8000684: 4a21 ldr r2, [pc, #132] @ (800070c <SystemClock_Config+0xd4>)
|
|
8000686: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
800068a: 6013 str r3, [r2, #0]
|
|
800068c: 4b1f ldr r3, [pc, #124] @ (800070c <SystemClock_Config+0xd4>)
|
|
800068e: 681b ldr r3, [r3, #0]
|
|
8000690: f403 4340 and.w r3, r3, #49152 @ 0xc000
|
|
8000694: 603b str r3, [r7, #0]
|
|
8000696: 683b ldr r3, [r7, #0]
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
8000698: 2301 movs r3, #1
|
|
800069a: 61fb str r3, [r7, #28]
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
800069c: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
80006a0: 623b str r3, [r7, #32]
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
80006a2: 2302 movs r3, #2
|
|
80006a4: 637b str r3, [r7, #52] @ 0x34
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
80006a6: f44f 0380 mov.w r3, #4194304 @ 0x400000
|
|
80006aa: 63bb str r3, [r7, #56] @ 0x38
|
|
RCC_OscInitStruct.PLL.PLLM = 4;
|
|
80006ac: 2304 movs r3, #4
|
|
80006ae: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.PLL.PLLN = 96;
|
|
80006b0: 2360 movs r3, #96 @ 0x60
|
|
80006b2: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
80006b4: 2302 movs r3, #2
|
|
80006b6: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLQ = 4;
|
|
80006b8: 2304 movs r3, #4
|
|
80006ba: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLR = 2;
|
|
80006bc: 2302 movs r3, #2
|
|
80006be: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
80006c0: f107 031c add.w r3, r7, #28
|
|
80006c4: 4618 mov r0, r3
|
|
80006c6: f003 fcf5 bl 80040b4 <HAL_RCC_OscConfig>
|
|
80006ca: 4603 mov r3, r0
|
|
80006cc: 2b00 cmp r3, #0
|
|
80006ce: d001 beq.n 80006d4 <SystemClock_Config+0x9c>
|
|
{
|
|
Error_Handler();
|
|
80006d0: f000 fbf6 bl 8000ec0 <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
80006d4: 230f movs r3, #15
|
|
80006d6: 60bb str r3, [r7, #8]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
80006d8: 2302 movs r3, #2
|
|
80006da: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
|
|
80006dc: 2380 movs r3, #128 @ 0x80
|
|
80006de: 613b str r3, [r7, #16]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
|
|
80006e0: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
80006e4: 617b str r3, [r7, #20]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
80006e6: 2300 movs r3, #0
|
|
80006e8: 61bb str r3, [r7, #24]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
|
|
80006ea: f107 0308 add.w r3, r7, #8
|
|
80006ee: 2101 movs r1, #1
|
|
80006f0: 4618 mov r0, r3
|
|
80006f2: f002 fe6b bl 80033cc <HAL_RCC_ClockConfig>
|
|
80006f6: 4603 mov r3, r0
|
|
80006f8: 2b00 cmp r3, #0
|
|
80006fa: d001 beq.n 8000700 <SystemClock_Config+0xc8>
|
|
{
|
|
Error_Handler();
|
|
80006fc: f000 fbe0 bl 8000ec0 <Error_Handler>
|
|
}
|
|
}
|
|
8000700: bf00 nop
|
|
8000702: 3750 adds r7, #80 @ 0x50
|
|
8000704: 46bd mov sp, r7
|
|
8000706: bd80 pop {r7, pc}
|
|
8000708: 40023800 .word 0x40023800
|
|
800070c: 40007000 .word 0x40007000
|
|
|
|
08000710 <MX_I2C1_Init>:
|
|
* @brief I2C1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C1_Init(void)
|
|
{
|
|
8000710: b580 push {r7, lr}
|
|
8000712: af00 add r7, sp, #0
|
|
/* USER CODE END I2C1_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C1_Init 1 */
|
|
|
|
/* USER CODE END I2C1_Init 1 */
|
|
hi2c1.Instance = I2C1;
|
|
8000714: 4b12 ldr r3, [pc, #72] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
8000716: 4a13 ldr r2, [pc, #76] @ (8000764 <MX_I2C1_Init+0x54>)
|
|
8000718: 601a str r2, [r3, #0]
|
|
hi2c1.Init.ClockSpeed = 100000;
|
|
800071a: 4b11 ldr r3, [pc, #68] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
800071c: 4a12 ldr r2, [pc, #72] @ (8000768 <MX_I2C1_Init+0x58>)
|
|
800071e: 605a str r2, [r3, #4]
|
|
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
|
|
8000720: 4b0f ldr r3, [pc, #60] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
8000722: 2200 movs r2, #0
|
|
8000724: 609a str r2, [r3, #8]
|
|
hi2c1.Init.OwnAddress1 = 0;
|
|
8000726: 4b0e ldr r3, [pc, #56] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
8000728: 2200 movs r2, #0
|
|
800072a: 60da str r2, [r3, #12]
|
|
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
800072c: 4b0c ldr r3, [pc, #48] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
800072e: f44f 4280 mov.w r2, #16384 @ 0x4000
|
|
8000732: 611a str r2, [r3, #16]
|
|
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8000734: 4b0a ldr r3, [pc, #40] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
8000736: 2200 movs r2, #0
|
|
8000738: 615a str r2, [r3, #20]
|
|
hi2c1.Init.OwnAddress2 = 0;
|
|
800073a: 4b09 ldr r3, [pc, #36] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
800073c: 2200 movs r2, #0
|
|
800073e: 619a str r2, [r3, #24]
|
|
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8000740: 4b07 ldr r3, [pc, #28] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
8000742: 2200 movs r2, #0
|
|
8000744: 61da str r2, [r3, #28]
|
|
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8000746: 4b06 ldr r3, [pc, #24] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
8000748: 2200 movs r2, #0
|
|
800074a: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
|
|
800074c: 4804 ldr r0, [pc, #16] @ (8000760 <MX_I2C1_Init+0x50>)
|
|
800074e: f001 fa73 bl 8001c38 <HAL_I2C_Init>
|
|
8000752: 4603 mov r3, r0
|
|
8000754: 2b00 cmp r3, #0
|
|
8000756: d001 beq.n 800075c <MX_I2C1_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8000758: f000 fbb2 bl 8000ec0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C1_Init 2 */
|
|
|
|
/* USER CODE END I2C1_Init 2 */
|
|
|
|
}
|
|
800075c: bf00 nop
|
|
800075e: bd80 pop {r7, pc}
|
|
8000760: 200001a4 .word 0x200001a4
|
|
8000764: 40005400 .word 0x40005400
|
|
8000768: 000186a0 .word 0x000186a0
|
|
|
|
0800076c <MX_TIM2_Init>:
|
|
* @brief TIM2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM2_Init(void)
|
|
{
|
|
800076c: b580 push {r7, lr}
|
|
800076e: b08a sub sp, #40 @ 0x28
|
|
8000770: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM2_Init 0 */
|
|
|
|
/* USER CODE END TIM2_Init 0 */
|
|
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8000772: f107 0320 add.w r3, r7, #32
|
|
8000776: 2200 movs r2, #0
|
|
8000778: 601a str r2, [r3, #0]
|
|
800077a: 605a str r2, [r3, #4]
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
800077c: 1d3b adds r3, r7, #4
|
|
800077e: 2200 movs r2, #0
|
|
8000780: 601a str r2, [r3, #0]
|
|
8000782: 605a str r2, [r3, #4]
|
|
8000784: 609a str r2, [r3, #8]
|
|
8000786: 60da str r2, [r3, #12]
|
|
8000788: 611a str r2, [r3, #16]
|
|
800078a: 615a str r2, [r3, #20]
|
|
800078c: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE BEGIN TIM2_Init 1 */
|
|
|
|
/* USER CODE END TIM2_Init 1 */
|
|
htim2.Instance = TIM2;
|
|
800078e: 4b22 ldr r3, [pc, #136] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
8000790: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
|
|
8000794: 601a str r2, [r3, #0]
|
|
htim2.Init.Prescaler = 0;
|
|
8000796: 4b20 ldr r3, [pc, #128] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
8000798: 2200 movs r2, #0
|
|
800079a: 605a str r2, [r3, #4]
|
|
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
800079c: 4b1e ldr r3, [pc, #120] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
800079e: 2200 movs r2, #0
|
|
80007a0: 609a str r2, [r3, #8]
|
|
htim2.Init.Period = 4294967295;
|
|
80007a2: 4b1d ldr r3, [pc, #116] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
80007a4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80007a8: 60da str r2, [r3, #12]
|
|
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
80007aa: 4b1b ldr r3, [pc, #108] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
80007ac: 2200 movs r2, #0
|
|
80007ae: 611a str r2, [r3, #16]
|
|
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
80007b0: 4b19 ldr r3, [pc, #100] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
80007b2: 2200 movs r2, #0
|
|
80007b4: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_OC_Init(&htim2) != HAL_OK)
|
|
80007b6: 4818 ldr r0, [pc, #96] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
80007b8: f003 ff1a bl 80045f0 <HAL_TIM_OC_Init>
|
|
80007bc: 4603 mov r3, r0
|
|
80007be: 2b00 cmp r3, #0
|
|
80007c0: d001 beq.n 80007c6 <MX_TIM2_Init+0x5a>
|
|
{
|
|
Error_Handler();
|
|
80007c2: f000 fb7d bl 8000ec0 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
80007c6: 2300 movs r3, #0
|
|
80007c8: 623b str r3, [r7, #32]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
80007ca: 2300 movs r3, #0
|
|
80007cc: 627b str r3, [r7, #36] @ 0x24
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
|
|
80007ce: f107 0320 add.w r3, r7, #32
|
|
80007d2: 4619 mov r1, r3
|
|
80007d4: 4810 ldr r0, [pc, #64] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
80007d6: f004 fab3 bl 8004d40 <HAL_TIMEx_MasterConfigSynchronization>
|
|
80007da: 4603 mov r3, r0
|
|
80007dc: 2b00 cmp r3, #0
|
|
80007de: d001 beq.n 80007e4 <MX_TIM2_Init+0x78>
|
|
{
|
|
Error_Handler();
|
|
80007e0: f000 fb6e bl 8000ec0 <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE;
|
|
80007e4: 2350 movs r3, #80 @ 0x50
|
|
80007e6: 607b str r3, [r7, #4]
|
|
sConfigOC.Pulse = 0;
|
|
80007e8: 2300 movs r3, #0
|
|
80007ea: 60bb str r3, [r7, #8]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
80007ec: 2300 movs r3, #0
|
|
80007ee: 60fb str r3, [r7, #12]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
80007f0: 2300 movs r3, #0
|
|
80007f2: 617b str r3, [r7, #20]
|
|
if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
80007f4: 1d3b adds r3, r7, #4
|
|
80007f6: 2200 movs r2, #0
|
|
80007f8: 4619 mov r1, r3
|
|
80007fa: 4807 ldr r0, [pc, #28] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
80007fc: f003 ffee bl 80047dc <HAL_TIM_OC_ConfigChannel>
|
|
8000800: 4603 mov r3, r0
|
|
8000802: 2b00 cmp r3, #0
|
|
8000804: d001 beq.n 800080a <MX_TIM2_Init+0x9e>
|
|
{
|
|
Error_Handler();
|
|
8000806: f000 fb5b bl 8000ec0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM2_Init 2 */
|
|
|
|
/* USER CODE END TIM2_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim2);
|
|
800080a: 4803 ldr r0, [pc, #12] @ (8000818 <MX_TIM2_Init+0xac>)
|
|
800080c: f000 fc36 bl 800107c <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
8000810: bf00 nop
|
|
8000812: 3728 adds r7, #40 @ 0x28
|
|
8000814: 46bd mov sp, r7
|
|
8000816: bd80 pop {r7, pc}
|
|
8000818: 200001f8 .word 0x200001f8
|
|
|
|
0800081c <MX_TIM3_Init>:
|
|
* @brief TIM3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM3_Init(void)
|
|
{
|
|
800081c: b580 push {r7, lr}
|
|
800081e: b08c sub sp, #48 @ 0x30
|
|
8000820: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM3_Init 0 */
|
|
|
|
/* USER CODE END TIM3_Init 0 */
|
|
|
|
TIM_Encoder_InitTypeDef sConfig = {0};
|
|
8000822: f107 030c add.w r3, r7, #12
|
|
8000826: 2224 movs r2, #36 @ 0x24
|
|
8000828: 2100 movs r1, #0
|
|
800082a: 4618 mov r0, r3
|
|
800082c: f008 feb4 bl 8009598 <memset>
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8000830: 1d3b adds r3, r7, #4
|
|
8000832: 2200 movs r2, #0
|
|
8000834: 601a str r2, [r3, #0]
|
|
8000836: 605a str r2, [r3, #4]
|
|
|
|
/* USER CODE BEGIN TIM3_Init 1 */
|
|
|
|
/* USER CODE END TIM3_Init 1 */
|
|
htim3.Instance = TIM3;
|
|
8000838: 4b20 ldr r3, [pc, #128] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
800083a: 4a21 ldr r2, [pc, #132] @ (80008c0 <MX_TIM3_Init+0xa4>)
|
|
800083c: 601a str r2, [r3, #0]
|
|
htim3.Init.Prescaler = 0;
|
|
800083e: 4b1f ldr r3, [pc, #124] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
8000840: 2200 movs r2, #0
|
|
8000842: 605a str r2, [r3, #4]
|
|
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8000844: 4b1d ldr r3, [pc, #116] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
8000846: 2200 movs r2, #0
|
|
8000848: 609a str r2, [r3, #8]
|
|
htim3.Init.Period = 65535;
|
|
800084a: 4b1c ldr r3, [pc, #112] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
800084c: f64f 72ff movw r2, #65535 @ 0xffff
|
|
8000850: 60da str r2, [r3, #12]
|
|
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8000852: 4b1a ldr r3, [pc, #104] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
8000854: 2200 movs r2, #0
|
|
8000856: 611a str r2, [r3, #16]
|
|
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8000858: 4b18 ldr r3, [pc, #96] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
800085a: 2200 movs r2, #0
|
|
800085c: 619a str r2, [r3, #24]
|
|
sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
|
|
800085e: 2301 movs r3, #1
|
|
8000860: 60fb str r3, [r7, #12]
|
|
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
|
|
8000862: 2300 movs r3, #0
|
|
8000864: 613b str r3, [r7, #16]
|
|
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
|
|
8000866: 2301 movs r3, #1
|
|
8000868: 617b str r3, [r7, #20]
|
|
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
|
|
800086a: 2300 movs r3, #0
|
|
800086c: 61bb str r3, [r7, #24]
|
|
sConfig.IC1Filter = 0;
|
|
800086e: 2300 movs r3, #0
|
|
8000870: 61fb str r3, [r7, #28]
|
|
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
|
|
8000872: 2300 movs r3, #0
|
|
8000874: 623b str r3, [r7, #32]
|
|
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
|
|
8000876: 2301 movs r3, #1
|
|
8000878: 627b str r3, [r7, #36] @ 0x24
|
|
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
|
|
800087a: 2300 movs r3, #0
|
|
800087c: 62bb str r3, [r7, #40] @ 0x28
|
|
sConfig.IC2Filter = 0;
|
|
800087e: 2300 movs r3, #0
|
|
8000880: 62fb str r3, [r7, #44] @ 0x2c
|
|
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
|
|
8000882: f107 030c add.w r3, r7, #12
|
|
8000886: 4619 mov r1, r3
|
|
8000888: 480c ldr r0, [pc, #48] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
800088a: f003 ff00 bl 800468e <HAL_TIM_Encoder_Init>
|
|
800088e: 4603 mov r3, r0
|
|
8000890: 2b00 cmp r3, #0
|
|
8000892: d001 beq.n 8000898 <MX_TIM3_Init+0x7c>
|
|
{
|
|
Error_Handler();
|
|
8000894: f000 fb14 bl 8000ec0 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8000898: 2300 movs r3, #0
|
|
800089a: 607b str r3, [r7, #4]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
800089c: 2300 movs r3, #0
|
|
800089e: 60bb str r3, [r7, #8]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
|
80008a0: 1d3b adds r3, r7, #4
|
|
80008a2: 4619 mov r1, r3
|
|
80008a4: 4805 ldr r0, [pc, #20] @ (80008bc <MX_TIM3_Init+0xa0>)
|
|
80008a6: f004 fa4b bl 8004d40 <HAL_TIMEx_MasterConfigSynchronization>
|
|
80008aa: 4603 mov r3, r0
|
|
80008ac: 2b00 cmp r3, #0
|
|
80008ae: d001 beq.n 80008b4 <MX_TIM3_Init+0x98>
|
|
{
|
|
Error_Handler();
|
|
80008b0: f000 fb06 bl 8000ec0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM3_Init 2 */
|
|
|
|
/* USER CODE END TIM3_Init 2 */
|
|
|
|
}
|
|
80008b4: bf00 nop
|
|
80008b6: 3730 adds r7, #48 @ 0x30
|
|
80008b8: 46bd mov sp, r7
|
|
80008ba: bd80 pop {r7, pc}
|
|
80008bc: 20000240 .word 0x20000240
|
|
80008c0: 40000400 .word 0x40000400
|
|
|
|
080008c4 <MX_UART4_Init>:
|
|
* @brief UART4 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_UART4_Init(void)
|
|
{
|
|
80008c4: b580 push {r7, lr}
|
|
80008c6: af00 add r7, sp, #0
|
|
/* USER CODE END UART4_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART4_Init 1 */
|
|
|
|
/* USER CODE END UART4_Init 1 */
|
|
huart4.Instance = UART4;
|
|
80008c8: 4b11 ldr r3, [pc, #68] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008ca: 4a12 ldr r2, [pc, #72] @ (8000914 <MX_UART4_Init+0x50>)
|
|
80008cc: 601a str r2, [r3, #0]
|
|
huart4.Init.BaudRate = 115200;
|
|
80008ce: 4b10 ldr r3, [pc, #64] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008d0: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
80008d4: 605a str r2, [r3, #4]
|
|
huart4.Init.WordLength = UART_WORDLENGTH_8B;
|
|
80008d6: 4b0e ldr r3, [pc, #56] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008d8: 2200 movs r2, #0
|
|
80008da: 609a str r2, [r3, #8]
|
|
huart4.Init.StopBits = UART_STOPBITS_1;
|
|
80008dc: 4b0c ldr r3, [pc, #48] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008de: 2200 movs r2, #0
|
|
80008e0: 60da str r2, [r3, #12]
|
|
huart4.Init.Parity = UART_PARITY_NONE;
|
|
80008e2: 4b0b ldr r3, [pc, #44] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008e4: 2200 movs r2, #0
|
|
80008e6: 611a str r2, [r3, #16]
|
|
huart4.Init.Mode = UART_MODE_TX_RX;
|
|
80008e8: 4b09 ldr r3, [pc, #36] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008ea: 220c movs r2, #12
|
|
80008ec: 615a str r2, [r3, #20]
|
|
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80008ee: 4b08 ldr r3, [pc, #32] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008f0: 2200 movs r2, #0
|
|
80008f2: 619a str r2, [r3, #24]
|
|
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80008f4: 4b06 ldr r3, [pc, #24] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008f6: 2200 movs r2, #0
|
|
80008f8: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart4) != HAL_OK)
|
|
80008fa: 4805 ldr r0, [pc, #20] @ (8000910 <MX_UART4_Init+0x4c>)
|
|
80008fc: f004 fa9c bl 8004e38 <HAL_UART_Init>
|
|
8000900: 4603 mov r3, r0
|
|
8000902: 2b00 cmp r3, #0
|
|
8000904: d001 beq.n 800090a <MX_UART4_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8000906: f000 fadb bl 8000ec0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART4_Init 2 */
|
|
|
|
/* USER CODE END UART4_Init 2 */
|
|
|
|
}
|
|
800090a: bf00 nop
|
|
800090c: bd80 pop {r7, pc}
|
|
800090e: bf00 nop
|
|
8000910: 20000288 .word 0x20000288
|
|
8000914: 40004c00 .word 0x40004c00
|
|
|
|
08000918 <MX_UART5_Init>:
|
|
* @brief UART5 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_UART5_Init(void)
|
|
{
|
|
8000918: b580 push {r7, lr}
|
|
800091a: af00 add r7, sp, #0
|
|
/* USER CODE END UART5_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART5_Init 1 */
|
|
|
|
/* USER CODE END UART5_Init 1 */
|
|
huart5.Instance = UART5;
|
|
800091c: 4b11 ldr r3, [pc, #68] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
800091e: 4a12 ldr r2, [pc, #72] @ (8000968 <MX_UART5_Init+0x50>)
|
|
8000920: 601a str r2, [r3, #0]
|
|
huart5.Init.BaudRate = 115200;
|
|
8000922: 4b10 ldr r3, [pc, #64] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
8000924: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8000928: 605a str r2, [r3, #4]
|
|
huart5.Init.WordLength = UART_WORDLENGTH_8B;
|
|
800092a: 4b0e ldr r3, [pc, #56] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
800092c: 2200 movs r2, #0
|
|
800092e: 609a str r2, [r3, #8]
|
|
huart5.Init.StopBits = UART_STOPBITS_1;
|
|
8000930: 4b0c ldr r3, [pc, #48] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
8000932: 2200 movs r2, #0
|
|
8000934: 60da str r2, [r3, #12]
|
|
huart5.Init.Parity = UART_PARITY_NONE;
|
|
8000936: 4b0b ldr r3, [pc, #44] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
8000938: 2200 movs r2, #0
|
|
800093a: 611a str r2, [r3, #16]
|
|
huart5.Init.Mode = UART_MODE_TX_RX;
|
|
800093c: 4b09 ldr r3, [pc, #36] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
800093e: 220c movs r2, #12
|
|
8000940: 615a str r2, [r3, #20]
|
|
huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8000942: 4b08 ldr r3, [pc, #32] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
8000944: 2200 movs r2, #0
|
|
8000946: 619a str r2, [r3, #24]
|
|
huart5.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8000948: 4b06 ldr r3, [pc, #24] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
800094a: 2200 movs r2, #0
|
|
800094c: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart5) != HAL_OK)
|
|
800094e: 4805 ldr r0, [pc, #20] @ (8000964 <MX_UART5_Init+0x4c>)
|
|
8000950: f004 fa72 bl 8004e38 <HAL_UART_Init>
|
|
8000954: 4603 mov r3, r0
|
|
8000956: 2b00 cmp r3, #0
|
|
8000958: d001 beq.n 800095e <MX_UART5_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
800095a: f000 fab1 bl 8000ec0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART5_Init 2 */
|
|
|
|
/* USER CODE END UART5_Init 2 */
|
|
|
|
}
|
|
800095e: bf00 nop
|
|
8000960: bd80 pop {r7, pc}
|
|
8000962: bf00 nop
|
|
8000964: 200002d0 .word 0x200002d0
|
|
8000968: 40005000 .word 0x40005000
|
|
|
|
0800096c <MX_USART1_UART_Init>:
|
|
* @brief USART1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART1_UART_Init(void)
|
|
{
|
|
800096c: b580 push {r7, lr}
|
|
800096e: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
8000970: 4b11 ldr r3, [pc, #68] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
8000972: 4a12 ldr r2, [pc, #72] @ (80009bc <MX_USART1_UART_Init+0x50>)
|
|
8000974: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8000976: 4b10 ldr r3, [pc, #64] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
8000978: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
800097c: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
800097e: 4b0e ldr r3, [pc, #56] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
8000980: 2200 movs r2, #0
|
|
8000982: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8000984: 4b0c ldr r3, [pc, #48] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
8000986: 2200 movs r2, #0
|
|
8000988: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
800098a: 4b0b ldr r3, [pc, #44] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
800098c: 2200 movs r2, #0
|
|
800098e: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8000990: 4b09 ldr r3, [pc, #36] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
8000992: 220c movs r2, #12
|
|
8000994: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8000996: 4b08 ldr r3, [pc, #32] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
8000998: 2200 movs r2, #0
|
|
800099a: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
800099c: 4b06 ldr r3, [pc, #24] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
800099e: 2200 movs r2, #0
|
|
80009a0: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
80009a2: 4805 ldr r0, [pc, #20] @ (80009b8 <MX_USART1_UART_Init+0x4c>)
|
|
80009a4: f004 fa48 bl 8004e38 <HAL_UART_Init>
|
|
80009a8: 4603 mov r3, r0
|
|
80009aa: 2b00 cmp r3, #0
|
|
80009ac: d001 beq.n 80009b2 <MX_USART1_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
80009ae: f000 fa87 bl 8000ec0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
80009b2: bf00 nop
|
|
80009b4: bd80 pop {r7, pc}
|
|
80009b6: bf00 nop
|
|
80009b8: 20000318 .word 0x20000318
|
|
80009bc: 40011000 .word 0x40011000
|
|
|
|
080009c0 <MX_USART2_UART_Init>:
|
|
* @brief USART2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART2_UART_Init(void)
|
|
{
|
|
80009c0: b580 push {r7, lr}
|
|
80009c2: af00 add r7, sp, #0
|
|
/* USER CODE END USART2_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
|
|
|
/* USER CODE END USART2_Init 1 */
|
|
huart2.Instance = USART2;
|
|
80009c4: 4b11 ldr r3, [pc, #68] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009c6: 4a12 ldr r2, [pc, #72] @ (8000a10 <MX_USART2_UART_Init+0x50>)
|
|
80009c8: 601a str r2, [r3, #0]
|
|
huart2.Init.BaudRate = 115200;
|
|
80009ca: 4b10 ldr r3, [pc, #64] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009cc: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
80009d0: 605a str r2, [r3, #4]
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
80009d2: 4b0e ldr r3, [pc, #56] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009d4: 2200 movs r2, #0
|
|
80009d6: 609a str r2, [r3, #8]
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
80009d8: 4b0c ldr r3, [pc, #48] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009da: 2200 movs r2, #0
|
|
80009dc: 60da str r2, [r3, #12]
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
80009de: 4b0b ldr r3, [pc, #44] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009e0: 2200 movs r2, #0
|
|
80009e2: 611a str r2, [r3, #16]
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
80009e4: 4b09 ldr r3, [pc, #36] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009e6: 220c movs r2, #12
|
|
80009e8: 615a str r2, [r3, #20]
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80009ea: 4b08 ldr r3, [pc, #32] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009ec: 2200 movs r2, #0
|
|
80009ee: 619a str r2, [r3, #24]
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80009f0: 4b06 ldr r3, [pc, #24] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009f2: 2200 movs r2, #0
|
|
80009f4: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
|
80009f6: 4805 ldr r0, [pc, #20] @ (8000a0c <MX_USART2_UART_Init+0x4c>)
|
|
80009f8: f004 fa1e bl 8004e38 <HAL_UART_Init>
|
|
80009fc: 4603 mov r3, r0
|
|
80009fe: 2b00 cmp r3, #0
|
|
8000a00: d001 beq.n 8000a06 <MX_USART2_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8000a02: f000 fa5d bl 8000ec0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
|
|
|
/* USER CODE END USART2_Init 2 */
|
|
|
|
}
|
|
8000a06: bf00 nop
|
|
8000a08: bd80 pop {r7, pc}
|
|
8000a0a: bf00 nop
|
|
8000a0c: 20000360 .word 0x20000360
|
|
8000a10: 40004400 .word 0x40004400
|
|
|
|
08000a14 <MX_USART3_UART_Init>:
|
|
* @brief USART3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART3_UART_Init(void)
|
|
{
|
|
8000a14: b580 push {r7, lr}
|
|
8000a16: af00 add r7, sp, #0
|
|
/* USER CODE END USART3_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART3_Init 1 */
|
|
|
|
/* USER CODE END USART3_Init 1 */
|
|
huart3.Instance = USART3;
|
|
8000a18: 4b11 ldr r3, [pc, #68] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a1a: 4a12 ldr r2, [pc, #72] @ (8000a64 <MX_USART3_UART_Init+0x50>)
|
|
8000a1c: 601a str r2, [r3, #0]
|
|
huart3.Init.BaudRate = 115200;
|
|
8000a1e: 4b10 ldr r3, [pc, #64] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a20: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8000a24: 605a str r2, [r3, #4]
|
|
huart3.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8000a26: 4b0e ldr r3, [pc, #56] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a28: 2200 movs r2, #0
|
|
8000a2a: 609a str r2, [r3, #8]
|
|
huart3.Init.StopBits = UART_STOPBITS_1;
|
|
8000a2c: 4b0c ldr r3, [pc, #48] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a2e: 2200 movs r2, #0
|
|
8000a30: 60da str r2, [r3, #12]
|
|
huart3.Init.Parity = UART_PARITY_NONE;
|
|
8000a32: 4b0b ldr r3, [pc, #44] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a34: 2200 movs r2, #0
|
|
8000a36: 611a str r2, [r3, #16]
|
|
huart3.Init.Mode = UART_MODE_TX_RX;
|
|
8000a38: 4b09 ldr r3, [pc, #36] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a3a: 220c movs r2, #12
|
|
8000a3c: 615a str r2, [r3, #20]
|
|
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8000a3e: 4b08 ldr r3, [pc, #32] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a40: 2200 movs r2, #0
|
|
8000a42: 619a str r2, [r3, #24]
|
|
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8000a44: 4b06 ldr r3, [pc, #24] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a46: 2200 movs r2, #0
|
|
8000a48: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart3) != HAL_OK)
|
|
8000a4a: 4805 ldr r0, [pc, #20] @ (8000a60 <MX_USART3_UART_Init+0x4c>)
|
|
8000a4c: f004 f9f4 bl 8004e38 <HAL_UART_Init>
|
|
8000a50: 4603 mov r3, r0
|
|
8000a52: 2b00 cmp r3, #0
|
|
8000a54: d001 beq.n 8000a5a <MX_USART3_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8000a56: f000 fa33 bl 8000ec0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART3_Init 2 */
|
|
|
|
/* USER CODE END USART3_Init 2 */
|
|
}
|
|
8000a5a: bf00 nop
|
|
8000a5c: bd80 pop {r7, pc}
|
|
8000a5e: bf00 nop
|
|
8000a60: 200003a8 .word 0x200003a8
|
|
8000a64: 40004800 .word 0x40004800
|
|
|
|
08000a68 <MX_DMA_Init>:
|
|
|
|
static void MX_DMA_Init(void)
|
|
{
|
|
8000a68: b580 push {r7, lr}
|
|
8000a6a: b082 sub sp, #8
|
|
8000a6c: af00 add r7, sp, #0
|
|
|
|
/* DMA controller clock enable */
|
|
__HAL_RCC_DMA2_CLK_ENABLE();
|
|
8000a6e: 2300 movs r3, #0
|
|
8000a70: 607b str r3, [r7, #4]
|
|
8000a72: 4b2f ldr r3, [pc, #188] @ (8000b30 <MX_DMA_Init+0xc8>)
|
|
8000a74: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a76: 4a2e ldr r2, [pc, #184] @ (8000b30 <MX_DMA_Init+0xc8>)
|
|
8000a78: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8000a7c: 6313 str r3, [r2, #48] @ 0x30
|
|
8000a7e: 4b2c ldr r3, [pc, #176] @ (8000b30 <MX_DMA_Init+0xc8>)
|
|
8000a80: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a82: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8000a86: 607b str r3, [r7, #4]
|
|
8000a88: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_DMA1_CLK_ENABLE();
|
|
8000a8a: 2300 movs r3, #0
|
|
8000a8c: 603b str r3, [r7, #0]
|
|
8000a8e: 4b28 ldr r3, [pc, #160] @ (8000b30 <MX_DMA_Init+0xc8>)
|
|
8000a90: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a92: 4a27 ldr r2, [pc, #156] @ (8000b30 <MX_DMA_Init+0xc8>)
|
|
8000a94: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8000a98: 6313 str r3, [r2, #48] @ 0x30
|
|
8000a9a: 4b25 ldr r3, [pc, #148] @ (8000b30 <MX_DMA_Init+0xc8>)
|
|
8000a9c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a9e: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8000aa2: 603b str r3, [r7, #0]
|
|
8000aa4: 683b ldr r3, [r7, #0]
|
|
|
|
/* DMA interrupt init */
|
|
/* DMA1_Stream0_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);
|
|
8000aa6: 2200 movs r2, #0
|
|
8000aa8: 2100 movs r1, #0
|
|
8000aaa: 200b movs r0, #11
|
|
8000aac: f000 fe41 bl 8001732 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
|
|
8000ab0: 200b movs r0, #11
|
|
8000ab2: f000 fe5a bl 800176a <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream2_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0);
|
|
8000ab6: 2200 movs r2, #0
|
|
8000ab8: 2100 movs r1, #0
|
|
8000aba: 200d movs r0, #13
|
|
8000abc: f000 fe39 bl 8001732 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
|
|
8000ac0: 200d movs r0, #13
|
|
8000ac2: f000 fe52 bl 800176a <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream4_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0);
|
|
8000ac6: 2200 movs r2, #0
|
|
8000ac8: 2100 movs r1, #0
|
|
8000aca: 200f movs r0, #15
|
|
8000acc: f000 fe31 bl 8001732 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);
|
|
8000ad0: 200f movs r0, #15
|
|
8000ad2: f000 fe4a bl 800176a <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream5_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0);
|
|
8000ad6: 2200 movs r2, #0
|
|
8000ad8: 2100 movs r1, #0
|
|
8000ada: 2010 movs r0, #16
|
|
8000adc: f000 fe29 bl 8001732 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
|
|
8000ae0: 2010 movs r0, #16
|
|
8000ae2: f000 fe42 bl 800176a <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream6_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0);
|
|
8000ae6: 2200 movs r2, #0
|
|
8000ae8: 2100 movs r1, #0
|
|
8000aea: 2011 movs r0, #17
|
|
8000aec: f000 fe21 bl 8001732 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn);
|
|
8000af0: 2011 movs r0, #17
|
|
8000af2: f000 fe3a bl 800176a <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream7_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0);
|
|
8000af6: 2200 movs r2, #0
|
|
8000af8: 2100 movs r1, #0
|
|
8000afa: 202f movs r0, #47 @ 0x2f
|
|
8000afc: f000 fe19 bl 8001732 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);
|
|
8000b00: 202f movs r0, #47 @ 0x2f
|
|
8000b02: f000 fe32 bl 800176a <HAL_NVIC_EnableIRQ>
|
|
/* DMA2_Stream2_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0);
|
|
8000b06: 2200 movs r2, #0
|
|
8000b08: 2100 movs r1, #0
|
|
8000b0a: 203a movs r0, #58 @ 0x3a
|
|
8000b0c: f000 fe11 bl 8001732 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
|
|
8000b10: 203a movs r0, #58 @ 0x3a
|
|
8000b12: f000 fe2a bl 800176a <HAL_NVIC_EnableIRQ>
|
|
/* DMA2_Stream7_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0);
|
|
8000b16: 2200 movs r2, #0
|
|
8000b18: 2100 movs r1, #0
|
|
8000b1a: 2046 movs r0, #70 @ 0x46
|
|
8000b1c: f000 fe09 bl 8001732 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
|
|
8000b20: 2046 movs r0, #70 @ 0x46
|
|
8000b22: f000 fe22 bl 800176a <HAL_NVIC_EnableIRQ>
|
|
|
|
}
|
|
8000b26: bf00 nop
|
|
8000b28: 3708 adds r7, #8
|
|
8000b2a: 46bd mov sp, r7
|
|
8000b2c: bd80 pop {r7, pc}
|
|
8000b2e: bf00 nop
|
|
8000b30: 40023800 .word 0x40023800
|
|
|
|
08000b34 <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8000b34: b580 push {r7, lr}
|
|
8000b36: b08a sub sp, #40 @ 0x28
|
|
8000b38: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000b3a: f107 0314 add.w r3, r7, #20
|
|
8000b3e: 2200 movs r2, #0
|
|
8000b40: 601a str r2, [r3, #0]
|
|
8000b42: 605a str r2, [r3, #4]
|
|
8000b44: 609a str r2, [r3, #8]
|
|
8000b46: 60da str r2, [r3, #12]
|
|
8000b48: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
8000b4a: 2300 movs r3, #0
|
|
8000b4c: 613b str r3, [r7, #16]
|
|
8000b4e: 4b45 ldr r3, [pc, #276] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b50: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b52: 4a44 ldr r2, [pc, #272] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b54: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8000b58: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b5a: 4b42 ldr r3, [pc, #264] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b5c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b5e: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8000b62: 613b str r3, [r7, #16]
|
|
8000b64: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000b66: 2300 movs r3, #0
|
|
8000b68: 60fb str r3, [r7, #12]
|
|
8000b6a: 4b3e ldr r3, [pc, #248] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b6c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b6e: 4a3d ldr r2, [pc, #244] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b70: f043 0301 orr.w r3, r3, #1
|
|
8000b74: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b76: 4b3b ldr r3, [pc, #236] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b78: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b7a: f003 0301 and.w r3, r3, #1
|
|
8000b7e: 60fb str r3, [r7, #12]
|
|
8000b80: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8000b82: 2300 movs r3, #0
|
|
8000b84: 60bb str r3, [r7, #8]
|
|
8000b86: 4b37 ldr r3, [pc, #220] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b88: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b8a: 4a36 ldr r2, [pc, #216] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b8c: f043 0304 orr.w r3, r3, #4
|
|
8000b90: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b92: 4b34 ldr r3, [pc, #208] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000b94: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b96: f003 0304 and.w r3, r3, #4
|
|
8000b9a: 60bb str r3, [r7, #8]
|
|
8000b9c: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000b9e: 2300 movs r3, #0
|
|
8000ba0: 607b str r3, [r7, #4]
|
|
8000ba2: 4b30 ldr r3, [pc, #192] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000ba4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000ba6: 4a2f ldr r2, [pc, #188] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000ba8: f043 0302 orr.w r3, r3, #2
|
|
8000bac: 6313 str r3, [r2, #48] @ 0x30
|
|
8000bae: 4b2d ldr r3, [pc, #180] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000bb0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000bb2: f003 0302 and.w r3, r3, #2
|
|
8000bb6: 607b str r3, [r7, #4]
|
|
8000bb8: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8000bba: 2300 movs r3, #0
|
|
8000bbc: 603b str r3, [r7, #0]
|
|
8000bbe: 4b29 ldr r3, [pc, #164] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000bc0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000bc2: 4a28 ldr r2, [pc, #160] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000bc4: f043 0308 orr.w r3, r3, #8
|
|
8000bc8: 6313 str r3, [r2, #48] @ 0x30
|
|
8000bca: 4b26 ldr r3, [pc, #152] @ (8000c64 <MX_GPIO_Init+0x130>)
|
|
8000bcc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000bce: f003 0308 and.w r3, r3, #8
|
|
8000bd2: 603b str r3, [r7, #0]
|
|
8000bd4: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET);
|
|
8000bd6: 2200 movs r2, #0
|
|
8000bd8: f44f 7170 mov.w r1, #960 @ 0x3c0
|
|
8000bdc: 4822 ldr r0, [pc, #136] @ (8000c68 <MX_GPIO_Init+0x134>)
|
|
8000bde: f001 f811 bl 8001c04 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET);
|
|
8000be2: 2200 movs r2, #0
|
|
8000be4: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8000be8: 4820 ldr r0, [pc, #128] @ (8000c6c <MX_GPIO_Init+0x138>)
|
|
8000bea: f001 f80b bl 8001c04 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : PC4 PC5 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
|
|
8000bee: 2330 movs r3, #48 @ 0x30
|
|
8000bf0: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8000bf2: 2300 movs r3, #0
|
|
8000bf4: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
8000bf6: 2302 movs r3, #2
|
|
8000bf8: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8000bfa: f107 0314 add.w r3, r7, #20
|
|
8000bfe: 4619 mov r1, r3
|
|
8000c00: 4819 ldr r0, [pc, #100] @ (8000c68 <MX_GPIO_Init+0x134>)
|
|
8000c02: f000 fe53 bl 80018ac <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PB0 PB1 PB2 PB10 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10;
|
|
8000c06: f240 4307 movw r3, #1031 @ 0x407
|
|
8000c0a: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8000c0c: 2300 movs r3, #0
|
|
8000c0e: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
8000c10: 2302 movs r3, #2
|
|
8000c12: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8000c14: f107 0314 add.w r3, r7, #20
|
|
8000c18: 4619 mov r1, r3
|
|
8000c1a: 4815 ldr r0, [pc, #84] @ (8000c70 <MX_GPIO_Init+0x13c>)
|
|
8000c1c: f000 fe46 bl 80018ac <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PC6 PC7 PC8 PC9 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9;
|
|
8000c20: f44f 7370 mov.w r3, #960 @ 0x3c0
|
|
8000c24: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000c26: 2301 movs r3, #1
|
|
8000c28: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
8000c2a: 2302 movs r3, #2
|
|
8000c2c: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000c2e: 2300 movs r3, #0
|
|
8000c30: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8000c32: f107 0314 add.w r3, r7, #20
|
|
8000c36: 4619 mov r1, r3
|
|
8000c38: 480b ldr r0, [pc, #44] @ (8000c68 <MX_GPIO_Init+0x134>)
|
|
8000c3a: f000 fe37 bl 80018ac <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : PA8 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_8;
|
|
8000c3e: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8000c42: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000c44: 2301 movs r3, #1
|
|
8000c46: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
8000c48: 2302 movs r3, #2
|
|
8000c4a: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000c4c: 2300 movs r3, #0
|
|
8000c4e: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000c50: f107 0314 add.w r3, r7, #20
|
|
8000c54: 4619 mov r1, r3
|
|
8000c56: 4805 ldr r0, [pc, #20] @ (8000c6c <MX_GPIO_Init+0x138>)
|
|
8000c58: f000 fe28 bl 80018ac <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
8000c5c: bf00 nop
|
|
8000c5e: 3728 adds r7, #40 @ 0x28
|
|
8000c60: 46bd mov sp, r7
|
|
8000c62: bd80 pop {r7, pc}
|
|
8000c64: 40023800 .word 0x40023800
|
|
8000c68: 40020800 .word 0x40020800
|
|
8000c6c: 40020000 .word 0x40020000
|
|
8000c70: 40020400 .word 0x40020400
|
|
|
|
08000c74 <HAL_UART_RxCpltCallback>:
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
//UART Message Requests Goes Here
|
|
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart){
|
|
8000c74: b580 push {r7, lr}
|
|
8000c76: b082 sub sp, #8
|
|
8000c78: af00 add r7, sp, #0
|
|
8000c7a: 6078 str r0, [r7, #4]
|
|
if(huart->Instance == USART1){
|
|
8000c7c: 687b ldr r3, [r7, #4]
|
|
8000c7e: 681b ldr r3, [r3, #0]
|
|
8000c80: 4a07 ldr r2, [pc, #28] @ (8000ca0 <HAL_UART_RxCpltCallback+0x2c>)
|
|
8000c82: 4293 cmp r3, r2
|
|
8000c84: d108 bne.n 8000c98 <HAL_UART_RxCpltCallback+0x24>
|
|
handleUARTMessages(UART1_RX_BUFF, huart);
|
|
8000c86: 6879 ldr r1, [r7, #4]
|
|
8000c88: 4806 ldr r0, [pc, #24] @ (8000ca4 <HAL_UART_RxCpltCallback+0x30>)
|
|
8000c8a: f000 f80d bl 8000ca8 <handleUARTMessages>
|
|
HAL_UART_Receive_DMA(huart, UART1_RX_BUFF, UART_RX_BUFF_SIZE);
|
|
8000c8e: 2240 movs r2, #64 @ 0x40
|
|
8000c90: 4904 ldr r1, [pc, #16] @ (8000ca4 <HAL_UART_RxCpltCallback+0x30>)
|
|
8000c92: 6878 ldr r0, [r7, #4]
|
|
8000c94: f004 f99c bl 8004fd0 <HAL_UART_Receive_DMA>
|
|
}
|
|
}
|
|
8000c98: bf00 nop
|
|
8000c9a: 3708 adds r7, #8
|
|
8000c9c: 46bd mov sp, r7
|
|
8000c9e: bd80 pop {r7, pc}
|
|
8000ca0: 40011000 .word 0x40011000
|
|
8000ca4: 200003f0 .word 0x200003f0
|
|
|
|
08000ca8 <handleUARTMessages>:
|
|
|
|
void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender){
|
|
8000ca8: b580 push {r7, lr}
|
|
8000caa: b08c sub sp, #48 @ 0x30
|
|
8000cac: af00 add r7, sp, #0
|
|
8000cae: 6078 str r0, [r7, #4]
|
|
8000cb0: 6039 str r1, [r7, #0]
|
|
UARTMessage msg;
|
|
UARTMessage res;
|
|
|
|
// Parse incoming message
|
|
msg.depth = (data[0]<<8) | data[1];
|
|
8000cb2: 687b ldr r3, [r7, #4]
|
|
8000cb4: 781b ldrb r3, [r3, #0]
|
|
8000cb6: b21b sxth r3, r3
|
|
8000cb8: 021b lsls r3, r3, #8
|
|
8000cba: b21a sxth r2, r3
|
|
8000cbc: 687b ldr r3, [r7, #4]
|
|
8000cbe: 3301 adds r3, #1
|
|
8000cc0: 781b ldrb r3, [r3, #0]
|
|
8000cc2: b21b sxth r3, r3
|
|
8000cc4: 4313 orrs r3, r2
|
|
8000cc6: b21b sxth r3, r3
|
|
8000cc8: b29b uxth r3, r3
|
|
8000cca: 83bb strh r3, [r7, #28]
|
|
msg.msgType = (data[2]<<8) | data[3];
|
|
8000ccc: 687b ldr r3, [r7, #4]
|
|
8000cce: 3302 adds r3, #2
|
|
8000cd0: 781b ldrb r3, [r3, #0]
|
|
8000cd2: b21b sxth r3, r3
|
|
8000cd4: 021b lsls r3, r3, #8
|
|
8000cd6: b21a sxth r2, r3
|
|
8000cd8: 687b ldr r3, [r7, #4]
|
|
8000cda: 3303 adds r3, #3
|
|
8000cdc: 781b ldrb r3, [r3, #0]
|
|
8000cde: b21b sxth r3, r3
|
|
8000ce0: 4313 orrs r3, r2
|
|
8000ce2: b21b sxth r3, r3
|
|
8000ce4: b29b uxth r3, r3
|
|
8000ce6: 83fb strh r3, [r7, #30]
|
|
memcpy(msg.keypress, &data[4], 12);
|
|
8000ce8: 687b ldr r3, [r7, #4]
|
|
8000cea: 1d1a adds r2, r3, #4
|
|
8000cec: f107 0320 add.w r3, r7, #32
|
|
8000cf0: 6810 ldr r0, [r2, #0]
|
|
8000cf2: 6851 ldr r1, [r2, #4]
|
|
8000cf4: 6892 ldr r2, [r2, #8]
|
|
8000cf6: c307 stmia r3!, {r0, r1, r2}
|
|
|
|
switch(msg.msgType){
|
|
8000cf8: 8bfb ldrh r3, [r7, #30]
|
|
8000cfa: 2b01 cmp r3, #1
|
|
8000cfc: d002 beq.n 8000d04 <handleUARTMessages+0x5c>
|
|
8000cfe: 2b10 cmp r3, #16
|
|
8000d00: d01b beq.n 8000d3a <handleUARTMessages+0x92>
|
|
for (int i = 0; i < 12; i++) {
|
|
REPORT.KEYPRESS[i] |= msg.keypress[i];
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
8000d02: e037 b.n 8000d74 <handleUARTMessages+0xcc>
|
|
if (sender->gState == HAL_UART_STATE_READY) {
|
|
8000d04: 683b ldr r3, [r7, #0]
|
|
8000d06: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8000d0a: b2db uxtb r3, r3
|
|
8000d0c: 2b20 cmp r3, #32
|
|
8000d0e: d130 bne.n 8000d72 <handleUARTMessages+0xca>
|
|
res.depth = DEPTH;
|
|
8000d10: 4b1a ldr r3, [pc, #104] @ (8000d7c <handleUARTMessages+0xd4>)
|
|
8000d12: 881b ldrh r3, [r3, #0]
|
|
8000d14: 81bb strh r3, [r7, #12]
|
|
res.msgType = 0x10;
|
|
8000d16: 2310 movs r3, #16
|
|
8000d18: 81fb strh r3, [r7, #14]
|
|
memcpy(res.keypress, &REPORT.KEYPRESS, sizeof(REPORT.KEYPRESS));
|
|
8000d1a: 4a19 ldr r2, [pc, #100] @ (8000d80 <handleUARTMessages+0xd8>)
|
|
8000d1c: f107 0310 add.w r3, r7, #16
|
|
8000d20: 3202 adds r2, #2
|
|
8000d22: 6810 ldr r0, [r2, #0]
|
|
8000d24: 6851 ldr r1, [r2, #4]
|
|
8000d26: 6892 ldr r2, [r2, #8]
|
|
8000d28: c307 stmia r3!, {r0, r1, r2}
|
|
HAL_UART_Transmit_DMA(sender, (uint8_t *)&res, sizeof(res));
|
|
8000d2a: f107 030c add.w r3, r7, #12
|
|
8000d2e: 2210 movs r2, #16
|
|
8000d30: 4619 mov r1, r3
|
|
8000d32: 6838 ldr r0, [r7, #0]
|
|
8000d34: f004 f8d0 bl 8004ed8 <HAL_UART_Transmit_DMA>
|
|
break;
|
|
8000d38: e01b b.n 8000d72 <handleUARTMessages+0xca>
|
|
for (int i = 0; i < 12; i++) {
|
|
8000d3a: 2300 movs r3, #0
|
|
8000d3c: 62fb str r3, [r7, #44] @ 0x2c
|
|
8000d3e: e014 b.n 8000d6a <handleUARTMessages+0xc2>
|
|
REPORT.KEYPRESS[i] |= msg.keypress[i];
|
|
8000d40: 4a0f ldr r2, [pc, #60] @ (8000d80 <handleUARTMessages+0xd8>)
|
|
8000d42: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8000d44: 4413 add r3, r2
|
|
8000d46: 3302 adds r3, #2
|
|
8000d48: 781a ldrb r2, [r3, #0]
|
|
8000d4a: f107 0120 add.w r1, r7, #32
|
|
8000d4e: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8000d50: 440b add r3, r1
|
|
8000d52: 781b ldrb r3, [r3, #0]
|
|
8000d54: 4313 orrs r3, r2
|
|
8000d56: b2d9 uxtb r1, r3
|
|
8000d58: 4a09 ldr r2, [pc, #36] @ (8000d80 <handleUARTMessages+0xd8>)
|
|
8000d5a: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8000d5c: 4413 add r3, r2
|
|
8000d5e: 3302 adds r3, #2
|
|
8000d60: 460a mov r2, r1
|
|
8000d62: 701a strb r2, [r3, #0]
|
|
for (int i = 0; i < 12; i++) {
|
|
8000d64: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8000d66: 3301 adds r3, #1
|
|
8000d68: 62fb str r3, [r7, #44] @ 0x2c
|
|
8000d6a: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8000d6c: 2b0b cmp r3, #11
|
|
8000d6e: dde7 ble.n 8000d40 <handleUARTMessages+0x98>
|
|
break;
|
|
8000d70: e000 b.n 8000d74 <handleUARTMessages+0xcc>
|
|
break;
|
|
8000d72: bf00 nop
|
|
}
|
|
8000d74: bf00 nop
|
|
8000d76: 3730 adds r7, #48 @ 0x30
|
|
8000d78: 46bd mov sp, r7
|
|
8000d7a: bd80 pop {r7, pc}
|
|
8000d7c: 200004fe .word 0x200004fe
|
|
8000d80: 200004f0 .word 0x200004f0
|
|
|
|
08000d84 <addUSBReport>:
|
|
void addUSBReport(uint8_t usageID){
|
|
8000d84: b480 push {r7}
|
|
8000d86: b085 sub sp, #20
|
|
8000d88: af00 add r7, sp, #0
|
|
8000d8a: 4603 mov r3, r0
|
|
8000d8c: 71fb strb r3, [r7, #7]
|
|
if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds
|
|
8000d8e: 79fb ldrb r3, [r7, #7]
|
|
8000d90: 2b03 cmp r3, #3
|
|
8000d92: d922 bls.n 8000dda <addUSBReport+0x56>
|
|
8000d94: 79fb ldrb r3, [r7, #7]
|
|
8000d96: 2b73 cmp r3, #115 @ 0x73
|
|
8000d98: d81f bhi.n 8000dda <addUSBReport+0x56>
|
|
uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit
|
|
8000d9a: 79fb ldrb r3, [r7, #7]
|
|
8000d9c: b29b uxth r3, r3
|
|
8000d9e: 3b04 subs r3, #4
|
|
8000da0: 81fb strh r3, [r7, #14]
|
|
uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array
|
|
8000da2: 89fb ldrh r3, [r7, #14]
|
|
8000da4: 08db lsrs r3, r3, #3
|
|
8000da6: b29b uxth r3, r3
|
|
8000da8: 737b strb r3, [r7, #13]
|
|
uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset
|
|
8000daa: 89fb ldrh r3, [r7, #14]
|
|
8000dac: b2db uxtb r3, r3
|
|
8000dae: f003 0307 and.w r3, r3, #7
|
|
8000db2: 733b strb r3, [r7, #12]
|
|
REPORT.KEYPRESS[byte_index] |= (1 << bit_offset);
|
|
8000db4: 7b7b ldrb r3, [r7, #13]
|
|
8000db6: 4a0c ldr r2, [pc, #48] @ (8000de8 <addUSBReport+0x64>)
|
|
8000db8: 4413 add r3, r2
|
|
8000dba: 789b ldrb r3, [r3, #2]
|
|
8000dbc: b25a sxtb r2, r3
|
|
8000dbe: 7b3b ldrb r3, [r7, #12]
|
|
8000dc0: 2101 movs r1, #1
|
|
8000dc2: fa01 f303 lsl.w r3, r1, r3
|
|
8000dc6: b25b sxtb r3, r3
|
|
8000dc8: 4313 orrs r3, r2
|
|
8000dca: b25a sxtb r2, r3
|
|
8000dcc: 7b7b ldrb r3, [r7, #13]
|
|
8000dce: b2d1 uxtb r1, r2
|
|
8000dd0: 4a05 ldr r2, [pc, #20] @ (8000de8 <addUSBReport+0x64>)
|
|
8000dd2: 4413 add r3, r2
|
|
8000dd4: 460a mov r2, r1
|
|
8000dd6: 709a strb r2, [r3, #2]
|
|
8000dd8: e000 b.n 8000ddc <addUSBReport+0x58>
|
|
if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds
|
|
8000dda: bf00 nop
|
|
}
|
|
8000ddc: 3714 adds r7, #20
|
|
8000dde: 46bd mov sp, r7
|
|
8000de0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000de4: 4770 bx lr
|
|
8000de6: bf00 nop
|
|
8000de8: 200004f0 .word 0x200004f0
|
|
|
|
08000dec <matrixScan>:
|
|
|
|
void matrixScan(void){
|
|
8000dec: b580 push {r7, lr}
|
|
8000dee: b082 sub sp, #8
|
|
8000df0: af00 add r7, sp, #0
|
|
for (uint8_t col = 0; col < COL; col++){
|
|
8000df2: 2300 movs r3, #0
|
|
8000df4: 71fb strb r3, [r7, #7]
|
|
8000df6: e044 b.n 8000e82 <matrixScan+0x96>
|
|
HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET);
|
|
8000df8: 79fb ldrb r3, [r7, #7]
|
|
8000dfa: 4a26 ldr r2, [pc, #152] @ (8000e94 <matrixScan+0xa8>)
|
|
8000dfc: f852 0033 ldr.w r0, [r2, r3, lsl #3]
|
|
8000e00: 79fb ldrb r3, [r7, #7]
|
|
8000e02: 4a24 ldr r2, [pc, #144] @ (8000e94 <matrixScan+0xa8>)
|
|
8000e04: 00db lsls r3, r3, #3
|
|
8000e06: 4413 add r3, r2
|
|
8000e08: 889b ldrh r3, [r3, #4]
|
|
8000e0a: 2201 movs r2, #1
|
|
8000e0c: 4619 mov r1, r3
|
|
8000e0e: f000 fef9 bl 8001c04 <HAL_GPIO_WritePin>
|
|
HAL_Delay(1);
|
|
8000e12: 2001 movs r0, #1
|
|
8000e14: f000 fb8e bl 8001534 <HAL_Delay>
|
|
for(uint8_t row = 0; row < ROW; row++){
|
|
8000e18: 2300 movs r3, #0
|
|
8000e1a: 71bb strb r3, [r7, #6]
|
|
8000e1c: e01e b.n 8000e5c <matrixScan+0x70>
|
|
if(HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN)){
|
|
8000e1e: 79bb ldrb r3, [r7, #6]
|
|
8000e20: 4a1d ldr r2, [pc, #116] @ (8000e98 <matrixScan+0xac>)
|
|
8000e22: f852 2033 ldr.w r2, [r2, r3, lsl #3]
|
|
8000e26: 79bb ldrb r3, [r7, #6]
|
|
8000e28: 491b ldr r1, [pc, #108] @ (8000e98 <matrixScan+0xac>)
|
|
8000e2a: 00db lsls r3, r3, #3
|
|
8000e2c: 440b add r3, r1
|
|
8000e2e: 889b ldrh r3, [r3, #4]
|
|
8000e30: 4619 mov r1, r3
|
|
8000e32: 4610 mov r0, r2
|
|
8000e34: f000 fece bl 8001bd4 <HAL_GPIO_ReadPin>
|
|
8000e38: 4603 mov r3, r0
|
|
8000e3a: 2b00 cmp r3, #0
|
|
8000e3c: d00b beq.n 8000e56 <matrixScan+0x6a>
|
|
addUSBReport(KEYCODES[row][col]);
|
|
8000e3e: 79ba ldrb r2, [r7, #6]
|
|
8000e40: 79f9 ldrb r1, [r7, #7]
|
|
8000e42: 4816 ldr r0, [pc, #88] @ (8000e9c <matrixScan+0xb0>)
|
|
8000e44: 4613 mov r3, r2
|
|
8000e46: 009b lsls r3, r3, #2
|
|
8000e48: 4413 add r3, r2
|
|
8000e4a: 4403 add r3, r0
|
|
8000e4c: 440b add r3, r1
|
|
8000e4e: 781b ldrb r3, [r3, #0]
|
|
8000e50: 4618 mov r0, r3
|
|
8000e52: f7ff ff97 bl 8000d84 <addUSBReport>
|
|
for(uint8_t row = 0; row < ROW; row++){
|
|
8000e56: 79bb ldrb r3, [r7, #6]
|
|
8000e58: 3301 adds r3, #1
|
|
8000e5a: 71bb strb r3, [r7, #6]
|
|
8000e5c: 79bb ldrb r3, [r7, #6]
|
|
8000e5e: 2b05 cmp r3, #5
|
|
8000e60: d9dd bls.n 8000e1e <matrixScan+0x32>
|
|
}
|
|
}
|
|
HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET);
|
|
8000e62: 79fb ldrb r3, [r7, #7]
|
|
8000e64: 4a0b ldr r2, [pc, #44] @ (8000e94 <matrixScan+0xa8>)
|
|
8000e66: f852 0033 ldr.w r0, [r2, r3, lsl #3]
|
|
8000e6a: 79fb ldrb r3, [r7, #7]
|
|
8000e6c: 4a09 ldr r2, [pc, #36] @ (8000e94 <matrixScan+0xa8>)
|
|
8000e6e: 00db lsls r3, r3, #3
|
|
8000e70: 4413 add r3, r2
|
|
8000e72: 889b ldrh r3, [r3, #4]
|
|
8000e74: 2200 movs r2, #0
|
|
8000e76: 4619 mov r1, r3
|
|
8000e78: f000 fec4 bl 8001c04 <HAL_GPIO_WritePin>
|
|
for (uint8_t col = 0; col < COL; col++){
|
|
8000e7c: 79fb ldrb r3, [r7, #7]
|
|
8000e7e: 3301 adds r3, #1
|
|
8000e80: 71fb strb r3, [r7, #7]
|
|
8000e82: 79fb ldrb r3, [r7, #7]
|
|
8000e84: 2b04 cmp r3, #4
|
|
8000e86: d9b7 bls.n 8000df8 <matrixScan+0xc>
|
|
}
|
|
}
|
|
8000e88: bf00 nop
|
|
8000e8a: bf00 nop
|
|
8000e8c: 3708 adds r7, #8
|
|
8000e8e: 46bd mov sp, r7
|
|
8000e90: bd80 pop {r7, pc}
|
|
8000e92: bf00 nop
|
|
8000e94: 20000030 .word 0x20000030
|
|
8000e98: 20000000 .word 0x20000000
|
|
8000e9c: 20000058 .word 0x20000058
|
|
|
|
08000ea0 <resetReport>:
|
|
|
|
void resetReport(void){
|
|
8000ea0: b580 push {r7, lr}
|
|
8000ea2: af00 add r7, sp, #0
|
|
REPORT.MODIFIER = 0;
|
|
8000ea4: 4b04 ldr r3, [pc, #16] @ (8000eb8 <resetReport+0x18>)
|
|
8000ea6: 2200 movs r2, #0
|
|
8000ea8: 701a strb r2, [r3, #0]
|
|
memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS));
|
|
8000eaa: 220c movs r2, #12
|
|
8000eac: 2100 movs r1, #0
|
|
8000eae: 4803 ldr r0, [pc, #12] @ (8000ebc <resetReport+0x1c>)
|
|
8000eb0: f008 fb72 bl 8009598 <memset>
|
|
}
|
|
8000eb4: bf00 nop
|
|
8000eb6: bd80 pop {r7, pc}
|
|
8000eb8: 200004f0 .word 0x200004f0
|
|
8000ebc: 200004f2 .word 0x200004f2
|
|
|
|
08000ec0 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8000ec0: b480 push {r7}
|
|
8000ec2: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8000ec4: b672 cpsid i
|
|
}
|
|
8000ec6: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8000ec8: bf00 nop
|
|
8000eca: e7fd b.n 8000ec8 <Error_Handler+0x8>
|
|
|
|
08000ecc <HAL_MspInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8000ecc: b480 push {r7}
|
|
8000ece: b083 sub sp, #12
|
|
8000ed0: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8000ed2: 2300 movs r3, #0
|
|
8000ed4: 607b str r3, [r7, #4]
|
|
8000ed6: 4b10 ldr r3, [pc, #64] @ (8000f18 <HAL_MspInit+0x4c>)
|
|
8000ed8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000eda: 4a0f ldr r2, [pc, #60] @ (8000f18 <HAL_MspInit+0x4c>)
|
|
8000edc: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8000ee0: 6453 str r3, [r2, #68] @ 0x44
|
|
8000ee2: 4b0d ldr r3, [pc, #52] @ (8000f18 <HAL_MspInit+0x4c>)
|
|
8000ee4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000ee6: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8000eea: 607b str r3, [r7, #4]
|
|
8000eec: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000eee: 2300 movs r3, #0
|
|
8000ef0: 603b str r3, [r7, #0]
|
|
8000ef2: 4b09 ldr r3, [pc, #36] @ (8000f18 <HAL_MspInit+0x4c>)
|
|
8000ef4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000ef6: 4a08 ldr r2, [pc, #32] @ (8000f18 <HAL_MspInit+0x4c>)
|
|
8000ef8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8000efc: 6413 str r3, [r2, #64] @ 0x40
|
|
8000efe: 4b06 ldr r3, [pc, #24] @ (8000f18 <HAL_MspInit+0x4c>)
|
|
8000f00: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000f02: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8000f06: 603b str r3, [r7, #0]
|
|
8000f08: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8000f0a: bf00 nop
|
|
8000f0c: 370c adds r7, #12
|
|
8000f0e: 46bd mov sp, r7
|
|
8000f10: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000f14: 4770 bx lr
|
|
8000f16: bf00 nop
|
|
8000f18: 40023800 .word 0x40023800
|
|
|
|
08000f1c <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
8000f1c: b580 push {r7, lr}
|
|
8000f1e: b08a sub sp, #40 @ 0x28
|
|
8000f20: af00 add r7, sp, #0
|
|
8000f22: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000f24: f107 0314 add.w r3, r7, #20
|
|
8000f28: 2200 movs r2, #0
|
|
8000f2a: 601a str r2, [r3, #0]
|
|
8000f2c: 605a str r2, [r3, #4]
|
|
8000f2e: 609a str r2, [r3, #8]
|
|
8000f30: 60da str r2, [r3, #12]
|
|
8000f32: 611a str r2, [r3, #16]
|
|
if(hi2c->Instance==I2C1)
|
|
8000f34: 687b ldr r3, [r7, #4]
|
|
8000f36: 681b ldr r3, [r3, #0]
|
|
8000f38: 4a19 ldr r2, [pc, #100] @ (8000fa0 <HAL_I2C_MspInit+0x84>)
|
|
8000f3a: 4293 cmp r3, r2
|
|
8000f3c: d12b bne.n 8000f96 <HAL_I2C_MspInit+0x7a>
|
|
{
|
|
/* USER CODE BEGIN I2C1_MspInit 0 */
|
|
|
|
/* USER CODE END I2C1_MspInit 0 */
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000f3e: 2300 movs r3, #0
|
|
8000f40: 613b str r3, [r7, #16]
|
|
8000f42: 4b18 ldr r3, [pc, #96] @ (8000fa4 <HAL_I2C_MspInit+0x88>)
|
|
8000f44: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f46: 4a17 ldr r2, [pc, #92] @ (8000fa4 <HAL_I2C_MspInit+0x88>)
|
|
8000f48: f043 0302 orr.w r3, r3, #2
|
|
8000f4c: 6313 str r3, [r2, #48] @ 0x30
|
|
8000f4e: 4b15 ldr r3, [pc, #84] @ (8000fa4 <HAL_I2C_MspInit+0x88>)
|
|
8000f50: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f52: f003 0302 and.w r3, r3, #2
|
|
8000f56: 613b str r3, [r7, #16]
|
|
8000f58: 693b ldr r3, [r7, #16]
|
|
/**I2C1 GPIO Configuration
|
|
PB6 ------> I2C1_SCL
|
|
PB7 ------> I2C1_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
8000f5a: 23c0 movs r3, #192 @ 0xc0
|
|
8000f5c: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
8000f5e: 2312 movs r3, #18
|
|
8000f60: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000f62: 2300 movs r3, #0
|
|
8000f64: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8000f66: 2303 movs r3, #3
|
|
8000f68: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
|
|
8000f6a: 2304 movs r3, #4
|
|
8000f6c: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8000f6e: f107 0314 add.w r3, r7, #20
|
|
8000f72: 4619 mov r1, r3
|
|
8000f74: 480c ldr r0, [pc, #48] @ (8000fa8 <HAL_I2C_MspInit+0x8c>)
|
|
8000f76: f000 fc99 bl 80018ac <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C1_CLK_ENABLE();
|
|
8000f7a: 2300 movs r3, #0
|
|
8000f7c: 60fb str r3, [r7, #12]
|
|
8000f7e: 4b09 ldr r3, [pc, #36] @ (8000fa4 <HAL_I2C_MspInit+0x88>)
|
|
8000f80: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000f82: 4a08 ldr r2, [pc, #32] @ (8000fa4 <HAL_I2C_MspInit+0x88>)
|
|
8000f84: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8000f88: 6413 str r3, [r2, #64] @ 0x40
|
|
8000f8a: 4b06 ldr r3, [pc, #24] @ (8000fa4 <HAL_I2C_MspInit+0x88>)
|
|
8000f8c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000f8e: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8000f92: 60fb str r3, [r7, #12]
|
|
8000f94: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END I2C1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000f96: bf00 nop
|
|
8000f98: 3728 adds r7, #40 @ 0x28
|
|
8000f9a: 46bd mov sp, r7
|
|
8000f9c: bd80 pop {r7, pc}
|
|
8000f9e: bf00 nop
|
|
8000fa0: 40005400 .word 0x40005400
|
|
8000fa4: 40023800 .word 0x40023800
|
|
8000fa8: 40020400 .word 0x40020400
|
|
|
|
08000fac <HAL_TIM_OC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_oc: TIM_OC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* htim_oc)
|
|
{
|
|
8000fac: b480 push {r7}
|
|
8000fae: b085 sub sp, #20
|
|
8000fb0: af00 add r7, sp, #0
|
|
8000fb2: 6078 str r0, [r7, #4]
|
|
if(htim_oc->Instance==TIM2)
|
|
8000fb4: 687b ldr r3, [r7, #4]
|
|
8000fb6: 681b ldr r3, [r3, #0]
|
|
8000fb8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8000fbc: d10d bne.n 8000fda <HAL_TIM_OC_MspInit+0x2e>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
|
8000fbe: 2300 movs r3, #0
|
|
8000fc0: 60fb str r3, [r7, #12]
|
|
8000fc2: 4b09 ldr r3, [pc, #36] @ (8000fe8 <HAL_TIM_OC_MspInit+0x3c>)
|
|
8000fc4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000fc6: 4a08 ldr r2, [pc, #32] @ (8000fe8 <HAL_TIM_OC_MspInit+0x3c>)
|
|
8000fc8: f043 0301 orr.w r3, r3, #1
|
|
8000fcc: 6413 str r3, [r2, #64] @ 0x40
|
|
8000fce: 4b06 ldr r3, [pc, #24] @ (8000fe8 <HAL_TIM_OC_MspInit+0x3c>)
|
|
8000fd0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000fd2: f003 0301 and.w r3, r3, #1
|
|
8000fd6: 60fb str r3, [r7, #12]
|
|
8000fd8: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END TIM2_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000fda: bf00 nop
|
|
8000fdc: 3714 adds r7, #20
|
|
8000fde: 46bd mov sp, r7
|
|
8000fe0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000fe4: 4770 bx lr
|
|
8000fe6: bf00 nop
|
|
8000fe8: 40023800 .word 0x40023800
|
|
|
|
08000fec <HAL_TIM_Encoder_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_encoder: TIM_Encoder handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
|
|
{
|
|
8000fec: b580 push {r7, lr}
|
|
8000fee: b08a sub sp, #40 @ 0x28
|
|
8000ff0: af00 add r7, sp, #0
|
|
8000ff2: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000ff4: f107 0314 add.w r3, r7, #20
|
|
8000ff8: 2200 movs r2, #0
|
|
8000ffa: 601a str r2, [r3, #0]
|
|
8000ffc: 605a str r2, [r3, #4]
|
|
8000ffe: 609a str r2, [r3, #8]
|
|
8001000: 60da str r2, [r3, #12]
|
|
8001002: 611a str r2, [r3, #16]
|
|
if(htim_encoder->Instance==TIM3)
|
|
8001004: 687b ldr r3, [r7, #4]
|
|
8001006: 681b ldr r3, [r3, #0]
|
|
8001008: 4a19 ldr r2, [pc, #100] @ (8001070 <HAL_TIM_Encoder_MspInit+0x84>)
|
|
800100a: 4293 cmp r3, r2
|
|
800100c: d12b bne.n 8001066 <HAL_TIM_Encoder_MspInit+0x7a>
|
|
{
|
|
/* USER CODE BEGIN TIM3_MspInit 0 */
|
|
|
|
/* USER CODE END TIM3_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
800100e: 2300 movs r3, #0
|
|
8001010: 613b str r3, [r7, #16]
|
|
8001012: 4b18 ldr r3, [pc, #96] @ (8001074 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001014: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001016: 4a17 ldr r2, [pc, #92] @ (8001074 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001018: f043 0302 orr.w r3, r3, #2
|
|
800101c: 6413 str r3, [r2, #64] @ 0x40
|
|
800101e: 4b15 ldr r3, [pc, #84] @ (8001074 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001020: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001022: f003 0302 and.w r3, r3, #2
|
|
8001026: 613b str r3, [r7, #16]
|
|
8001028: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800102a: 2300 movs r3, #0
|
|
800102c: 60fb str r3, [r7, #12]
|
|
800102e: 4b11 ldr r3, [pc, #68] @ (8001074 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001030: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001032: 4a10 ldr r2, [pc, #64] @ (8001074 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001034: f043 0301 orr.w r3, r3, #1
|
|
8001038: 6313 str r3, [r2, #48] @ 0x30
|
|
800103a: 4b0e ldr r3, [pc, #56] @ (8001074 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
800103c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800103e: f003 0301 and.w r3, r3, #1
|
|
8001042: 60fb str r3, [r7, #12]
|
|
8001044: 68fb ldr r3, [r7, #12]
|
|
/**TIM3 GPIO Configuration
|
|
PA6 ------> TIM3_CH1
|
|
PA7 ------> TIM3_CH2
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
8001046: 23c0 movs r3, #192 @ 0xc0
|
|
8001048: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800104a: 2302 movs r3, #2
|
|
800104c: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800104e: 2300 movs r3, #0
|
|
8001050: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001052: 2300 movs r3, #0
|
|
8001054: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
|
|
8001056: 2302 movs r3, #2
|
|
8001058: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800105a: f107 0314 add.w r3, r7, #20
|
|
800105e: 4619 mov r1, r3
|
|
8001060: 4805 ldr r0, [pc, #20] @ (8001078 <HAL_TIM_Encoder_MspInit+0x8c>)
|
|
8001062: f000 fc23 bl 80018ac <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END TIM3_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8001066: bf00 nop
|
|
8001068: 3728 adds r7, #40 @ 0x28
|
|
800106a: 46bd mov sp, r7
|
|
800106c: bd80 pop {r7, pc}
|
|
800106e: bf00 nop
|
|
8001070: 40000400 .word 0x40000400
|
|
8001074: 40023800 .word 0x40023800
|
|
8001078: 40020000 .word 0x40020000
|
|
|
|
0800107c <HAL_TIM_MspPostInit>:
|
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
|
{
|
|
800107c: b580 push {r7, lr}
|
|
800107e: b088 sub sp, #32
|
|
8001080: af00 add r7, sp, #0
|
|
8001082: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001084: f107 030c add.w r3, r7, #12
|
|
8001088: 2200 movs r2, #0
|
|
800108a: 601a str r2, [r3, #0]
|
|
800108c: 605a str r2, [r3, #4]
|
|
800108e: 609a str r2, [r3, #8]
|
|
8001090: 60da str r2, [r3, #12]
|
|
8001092: 611a str r2, [r3, #16]
|
|
if(htim->Instance==TIM2)
|
|
8001094: 687b ldr r3, [r7, #4]
|
|
8001096: 681b ldr r3, [r3, #0]
|
|
8001098: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
800109c: d11d bne.n 80010da <HAL_TIM_MspPostInit+0x5e>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 0 */
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800109e: 2300 movs r3, #0
|
|
80010a0: 60bb str r3, [r7, #8]
|
|
80010a2: 4b10 ldr r3, [pc, #64] @ (80010e4 <HAL_TIM_MspPostInit+0x68>)
|
|
80010a4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80010a6: 4a0f ldr r2, [pc, #60] @ (80010e4 <HAL_TIM_MspPostInit+0x68>)
|
|
80010a8: f043 0301 orr.w r3, r3, #1
|
|
80010ac: 6313 str r3, [r2, #48] @ 0x30
|
|
80010ae: 4b0d ldr r3, [pc, #52] @ (80010e4 <HAL_TIM_MspPostInit+0x68>)
|
|
80010b0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80010b2: f003 0301 and.w r3, r3, #1
|
|
80010b6: 60bb str r3, [r7, #8]
|
|
80010b8: 68bb ldr r3, [r7, #8]
|
|
/**TIM2 GPIO Configuration
|
|
PA5 ------> TIM2_CH1
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_5;
|
|
80010ba: 2320 movs r3, #32
|
|
80010bc: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80010be: 2302 movs r3, #2
|
|
80010c0: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80010c2: 2300 movs r3, #0
|
|
80010c4: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80010c6: 2300 movs r3, #0
|
|
80010c8: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
|
|
80010ca: 2301 movs r3, #1
|
|
80010cc: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80010ce: f107 030c add.w r3, r7, #12
|
|
80010d2: 4619 mov r1, r3
|
|
80010d4: 4804 ldr r0, [pc, #16] @ (80010e8 <HAL_TIM_MspPostInit+0x6c>)
|
|
80010d6: f000 fbe9 bl 80018ac <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM2_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
80010da: bf00 nop
|
|
80010dc: 3720 adds r7, #32
|
|
80010de: 46bd mov sp, r7
|
|
80010e0: bd80 pop {r7, pc}
|
|
80010e2: bf00 nop
|
|
80010e4: 40023800 .word 0x40023800
|
|
80010e8: 40020000 .word 0x40020000
|
|
|
|
080010ec <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
80010ec: b580 push {r7, lr}
|
|
80010ee: b092 sub sp, #72 @ 0x48
|
|
80010f0: af00 add r7, sp, #0
|
|
80010f2: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80010f4: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
80010f8: 2200 movs r2, #0
|
|
80010fa: 601a str r2, [r3, #0]
|
|
80010fc: 605a str r2, [r3, #4]
|
|
80010fe: 609a str r2, [r3, #8]
|
|
8001100: 60da str r2, [r3, #12]
|
|
8001102: 611a str r2, [r3, #16]
|
|
if(huart->Instance==UART4)
|
|
8001104: 687b ldr r3, [r7, #4]
|
|
8001106: 681b ldr r3, [r3, #0]
|
|
8001108: 4a8d ldr r2, [pc, #564] @ (8001340 <HAL_UART_MspInit+0x254>)
|
|
800110a: 4293 cmp r3, r2
|
|
800110c: d12c bne.n 8001168 <HAL_UART_MspInit+0x7c>
|
|
{
|
|
/* USER CODE BEGIN UART4_MspInit 0 */
|
|
|
|
/* USER CODE END UART4_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_UART4_CLK_ENABLE();
|
|
800110e: 2300 movs r3, #0
|
|
8001110: 633b str r3, [r7, #48] @ 0x30
|
|
8001112: 4b8c ldr r3, [pc, #560] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001114: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001116: 4a8b ldr r2, [pc, #556] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001118: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
800111c: 6413 str r3, [r2, #64] @ 0x40
|
|
800111e: 4b89 ldr r3, [pc, #548] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001120: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001122: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8001126: 633b str r3, [r7, #48] @ 0x30
|
|
8001128: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800112a: 2300 movs r3, #0
|
|
800112c: 62fb str r3, [r7, #44] @ 0x2c
|
|
800112e: 4b85 ldr r3, [pc, #532] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001130: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001132: 4a84 ldr r2, [pc, #528] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001134: f043 0301 orr.w r3, r3, #1
|
|
8001138: 6313 str r3, [r2, #48] @ 0x30
|
|
800113a: 4b82 ldr r3, [pc, #520] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
800113c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800113e: f003 0301 and.w r3, r3, #1
|
|
8001142: 62fb str r3, [r7, #44] @ 0x2c
|
|
8001144: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
/**UART4 GPIO Configuration
|
|
PA0-WKUP ------> UART4_TX
|
|
PA1 ------> UART4_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
|
|
8001146: 2303 movs r3, #3
|
|
8001148: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800114a: 2302 movs r3, #2
|
|
800114c: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800114e: 2300 movs r3, #0
|
|
8001150: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001152: 2303 movs r3, #3
|
|
8001154: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
|
|
8001156: 2308 movs r3, #8
|
|
8001158: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800115a: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
800115e: 4619 mov r1, r3
|
|
8001160: 4879 ldr r0, [pc, #484] @ (8001348 <HAL_UART_MspInit+0x25c>)
|
|
8001162: f000 fba3 bl 80018ac <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN USART3_MspInit 1 */
|
|
|
|
/* USER CODE END USART3_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8001166: e0e7 b.n 8001338 <HAL_UART_MspInit+0x24c>
|
|
else if(huart->Instance==UART5)
|
|
8001168: 687b ldr r3, [r7, #4]
|
|
800116a: 681b ldr r3, [r3, #0]
|
|
800116c: 4a77 ldr r2, [pc, #476] @ (800134c <HAL_UART_MspInit+0x260>)
|
|
800116e: 4293 cmp r3, r2
|
|
8001170: d14b bne.n 800120a <HAL_UART_MspInit+0x11e>
|
|
__HAL_RCC_UART5_CLK_ENABLE();
|
|
8001172: 2300 movs r3, #0
|
|
8001174: 62bb str r3, [r7, #40] @ 0x28
|
|
8001176: 4b73 ldr r3, [pc, #460] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001178: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800117a: 4a72 ldr r2, [pc, #456] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
800117c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8001180: 6413 str r3, [r2, #64] @ 0x40
|
|
8001182: 4b70 ldr r3, [pc, #448] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001184: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001186: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
800118a: 62bb str r3, [r7, #40] @ 0x28
|
|
800118c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
800118e: 2300 movs r3, #0
|
|
8001190: 627b str r3, [r7, #36] @ 0x24
|
|
8001192: 4b6c ldr r3, [pc, #432] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001194: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001196: 4a6b ldr r2, [pc, #428] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001198: f043 0304 orr.w r3, r3, #4
|
|
800119c: 6313 str r3, [r2, #48] @ 0x30
|
|
800119e: 4b69 ldr r3, [pc, #420] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
80011a0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80011a2: f003 0304 and.w r3, r3, #4
|
|
80011a6: 627b str r3, [r7, #36] @ 0x24
|
|
80011a8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
80011aa: 2300 movs r3, #0
|
|
80011ac: 623b str r3, [r7, #32]
|
|
80011ae: 4b65 ldr r3, [pc, #404] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
80011b0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80011b2: 4a64 ldr r2, [pc, #400] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
80011b4: f043 0308 orr.w r3, r3, #8
|
|
80011b8: 6313 str r3, [r2, #48] @ 0x30
|
|
80011ba: 4b62 ldr r3, [pc, #392] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
80011bc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80011be: f003 0308 and.w r3, r3, #8
|
|
80011c2: 623b str r3, [r7, #32]
|
|
80011c4: 6a3b ldr r3, [r7, #32]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_12;
|
|
80011c6: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
80011ca: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80011cc: 2302 movs r3, #2
|
|
80011ce: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80011d0: 2300 movs r3, #0
|
|
80011d2: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80011d4: 2303 movs r3, #3
|
|
80011d6: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
|
|
80011d8: 2308 movs r3, #8
|
|
80011da: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80011dc: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
80011e0: 4619 mov r1, r3
|
|
80011e2: 485b ldr r0, [pc, #364] @ (8001350 <HAL_UART_MspInit+0x264>)
|
|
80011e4: f000 fb62 bl 80018ac <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
80011e8: 2304 movs r3, #4
|
|
80011ea: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80011ec: 2302 movs r3, #2
|
|
80011ee: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80011f0: 2300 movs r3, #0
|
|
80011f2: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80011f4: 2303 movs r3, #3
|
|
80011f6: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
|
|
80011f8: 2308 movs r3, #8
|
|
80011fa: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
80011fc: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8001200: 4619 mov r1, r3
|
|
8001202: 4854 ldr r0, [pc, #336] @ (8001354 <HAL_UART_MspInit+0x268>)
|
|
8001204: f000 fb52 bl 80018ac <HAL_GPIO_Init>
|
|
}
|
|
8001208: e096 b.n 8001338 <HAL_UART_MspInit+0x24c>
|
|
else if(huart->Instance==USART1)
|
|
800120a: 687b ldr r3, [r7, #4]
|
|
800120c: 681b ldr r3, [r3, #0]
|
|
800120e: 4a52 ldr r2, [pc, #328] @ (8001358 <HAL_UART_MspInit+0x26c>)
|
|
8001210: 4293 cmp r3, r2
|
|
8001212: d12d bne.n 8001270 <HAL_UART_MspInit+0x184>
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8001214: 2300 movs r3, #0
|
|
8001216: 61fb str r3, [r7, #28]
|
|
8001218: 4b4a ldr r3, [pc, #296] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
800121a: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800121c: 4a49 ldr r2, [pc, #292] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
800121e: f043 0310 orr.w r3, r3, #16
|
|
8001222: 6453 str r3, [r2, #68] @ 0x44
|
|
8001224: 4b47 ldr r3, [pc, #284] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001226: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001228: f003 0310 and.w r3, r3, #16
|
|
800122c: 61fb str r3, [r7, #28]
|
|
800122e: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001230: 2300 movs r3, #0
|
|
8001232: 61bb str r3, [r7, #24]
|
|
8001234: 4b43 ldr r3, [pc, #268] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001236: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001238: 4a42 ldr r2, [pc, #264] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
800123a: f043 0301 orr.w r3, r3, #1
|
|
800123e: 6313 str r3, [r2, #48] @ 0x30
|
|
8001240: 4b40 ldr r3, [pc, #256] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001242: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001244: f003 0301 and.w r3, r3, #1
|
|
8001248: 61bb str r3, [r7, #24]
|
|
800124a: 69bb ldr r3, [r7, #24]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
|
|
800124c: f44f 63c0 mov.w r3, #1536 @ 0x600
|
|
8001250: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001252: 2302 movs r3, #2
|
|
8001254: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001256: 2300 movs r3, #0
|
|
8001258: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800125a: 2303 movs r3, #3
|
|
800125c: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
800125e: 2307 movs r3, #7
|
|
8001260: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001262: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8001266: 4619 mov r1, r3
|
|
8001268: 4837 ldr r0, [pc, #220] @ (8001348 <HAL_UART_MspInit+0x25c>)
|
|
800126a: f000 fb1f bl 80018ac <HAL_GPIO_Init>
|
|
}
|
|
800126e: e063 b.n 8001338 <HAL_UART_MspInit+0x24c>
|
|
else if(huart->Instance==USART2)
|
|
8001270: 687b ldr r3, [r7, #4]
|
|
8001272: 681b ldr r3, [r3, #0]
|
|
8001274: 4a39 ldr r2, [pc, #228] @ (800135c <HAL_UART_MspInit+0x270>)
|
|
8001276: 4293 cmp r3, r2
|
|
8001278: d12c bne.n 80012d4 <HAL_UART_MspInit+0x1e8>
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
800127a: 2300 movs r3, #0
|
|
800127c: 617b str r3, [r7, #20]
|
|
800127e: 4b31 ldr r3, [pc, #196] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001280: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001282: 4a30 ldr r2, [pc, #192] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001284: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8001288: 6413 str r3, [r2, #64] @ 0x40
|
|
800128a: 4b2e ldr r3, [pc, #184] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
800128c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800128e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001292: 617b str r3, [r7, #20]
|
|
8001294: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001296: 2300 movs r3, #0
|
|
8001298: 613b str r3, [r7, #16]
|
|
800129a: 4b2a ldr r3, [pc, #168] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
800129c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800129e: 4a29 ldr r2, [pc, #164] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
80012a0: f043 0301 orr.w r3, r3, #1
|
|
80012a4: 6313 str r3, [r2, #48] @ 0x30
|
|
80012a6: 4b27 ldr r3, [pc, #156] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
80012a8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80012aa: f003 0301 and.w r3, r3, #1
|
|
80012ae: 613b str r3, [r7, #16]
|
|
80012b0: 693b ldr r3, [r7, #16]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
|
|
80012b2: 230c movs r3, #12
|
|
80012b4: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80012b6: 2302 movs r3, #2
|
|
80012b8: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80012ba: 2300 movs r3, #0
|
|
80012bc: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80012be: 2303 movs r3, #3
|
|
80012c0: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
|
80012c2: 2307 movs r3, #7
|
|
80012c4: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80012c6: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
80012ca: 4619 mov r1, r3
|
|
80012cc: 481e ldr r0, [pc, #120] @ (8001348 <HAL_UART_MspInit+0x25c>)
|
|
80012ce: f000 faed bl 80018ac <HAL_GPIO_Init>
|
|
}
|
|
80012d2: e031 b.n 8001338 <HAL_UART_MspInit+0x24c>
|
|
else if(huart->Instance==USART3)
|
|
80012d4: 687b ldr r3, [r7, #4]
|
|
80012d6: 681b ldr r3, [r3, #0]
|
|
80012d8: 4a21 ldr r2, [pc, #132] @ (8001360 <HAL_UART_MspInit+0x274>)
|
|
80012da: 4293 cmp r3, r2
|
|
80012dc: d12c bne.n 8001338 <HAL_UART_MspInit+0x24c>
|
|
__HAL_RCC_USART3_CLK_ENABLE();
|
|
80012de: 2300 movs r3, #0
|
|
80012e0: 60fb str r3, [r7, #12]
|
|
80012e2: 4b18 ldr r3, [pc, #96] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
80012e4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80012e6: 4a17 ldr r2, [pc, #92] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
80012e8: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
80012ec: 6413 str r3, [r2, #64] @ 0x40
|
|
80012ee: 4b15 ldr r3, [pc, #84] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
80012f0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80012f2: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
80012f6: 60fb str r3, [r7, #12]
|
|
80012f8: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
80012fa: 2300 movs r3, #0
|
|
80012fc: 60bb str r3, [r7, #8]
|
|
80012fe: 4b11 ldr r3, [pc, #68] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001300: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001302: 4a10 ldr r2, [pc, #64] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
8001304: f043 0304 orr.w r3, r3, #4
|
|
8001308: 6313 str r3, [r2, #48] @ 0x30
|
|
800130a: 4b0e ldr r3, [pc, #56] @ (8001344 <HAL_UART_MspInit+0x258>)
|
|
800130c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800130e: f003 0304 and.w r3, r3, #4
|
|
8001312: 60bb str r3, [r7, #8]
|
|
8001314: 68bb ldr r3, [r7, #8]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
|
|
8001316: f44f 6340 mov.w r3, #3072 @ 0xc00
|
|
800131a: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800131c: 2302 movs r3, #2
|
|
800131e: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001320: 2300 movs r3, #0
|
|
8001322: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001324: 2303 movs r3, #3
|
|
8001326: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
|
|
8001328: 2307 movs r3, #7
|
|
800132a: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
800132c: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8001330: 4619 mov r1, r3
|
|
8001332: 4807 ldr r0, [pc, #28] @ (8001350 <HAL_UART_MspInit+0x264>)
|
|
8001334: f000 faba bl 80018ac <HAL_GPIO_Init>
|
|
}
|
|
8001338: bf00 nop
|
|
800133a: 3748 adds r7, #72 @ 0x48
|
|
800133c: 46bd mov sp, r7
|
|
800133e: bd80 pop {r7, pc}
|
|
8001340: 40004c00 .word 0x40004c00
|
|
8001344: 40023800 .word 0x40023800
|
|
8001348: 40020000 .word 0x40020000
|
|
800134c: 40005000 .word 0x40005000
|
|
8001350: 40020800 .word 0x40020800
|
|
8001354: 40020c00 .word 0x40020c00
|
|
8001358: 40011000 .word 0x40011000
|
|
800135c: 40004400 .word 0x40004400
|
|
8001360: 40004800 .word 0x40004800
|
|
|
|
08001364 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8001364: b480 push {r7}
|
|
8001366: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8001368: bf00 nop
|
|
800136a: e7fd b.n 8001368 <NMI_Handler+0x4>
|
|
|
|
0800136c <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
800136c: b480 push {r7}
|
|
800136e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8001370: bf00 nop
|
|
8001372: e7fd b.n 8001370 <HardFault_Handler+0x4>
|
|
|
|
08001374 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8001374: b480 push {r7}
|
|
8001376: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8001378: bf00 nop
|
|
800137a: e7fd b.n 8001378 <MemManage_Handler+0x4>
|
|
|
|
0800137c <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pre-fetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
800137c: b480 push {r7}
|
|
800137e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8001380: bf00 nop
|
|
8001382: e7fd b.n 8001380 <BusFault_Handler+0x4>
|
|
|
|
08001384 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8001384: b480 push {r7}
|
|
8001386: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8001388: bf00 nop
|
|
800138a: e7fd b.n 8001388 <UsageFault_Handler+0x4>
|
|
|
|
0800138c <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
800138c: b480 push {r7}
|
|
800138e: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8001390: bf00 nop
|
|
8001392: 46bd mov sp, r7
|
|
8001394: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001398: 4770 bx lr
|
|
|
|
0800139a <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
800139a: b480 push {r7}
|
|
800139c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
800139e: bf00 nop
|
|
80013a0: 46bd mov sp, r7
|
|
80013a2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80013a6: 4770 bx lr
|
|
|
|
080013a8 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
80013a8: b480 push {r7}
|
|
80013aa: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
80013ac: bf00 nop
|
|
80013ae: 46bd mov sp, r7
|
|
80013b0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80013b4: 4770 bx lr
|
|
|
|
080013b6 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
80013b6: b580 push {r7, lr}
|
|
80013b8: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
80013ba: f000 f89b bl 80014f4 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
80013be: bf00 nop
|
|
80013c0: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080013c4 <OTG_FS_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USB On The Go FS global interrupt.
|
|
*/
|
|
void OTG_FS_IRQHandler(void)
|
|
{
|
|
80013c4: b580 push {r7, lr}
|
|
80013c6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN OTG_FS_IRQn 0 */
|
|
|
|
/* USER CODE END OTG_FS_IRQn 0 */
|
|
HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
|
|
80013c8: 4802 ldr r0, [pc, #8] @ (80013d4 <OTG_FS_IRQHandler+0x10>)
|
|
80013ca: f000 fec4 bl 8002156 <HAL_PCD_IRQHandler>
|
|
/* USER CODE BEGIN OTG_FS_IRQn 1 */
|
|
|
|
/* USER CODE END OTG_FS_IRQn 1 */
|
|
}
|
|
80013ce: bf00 nop
|
|
80013d0: bd80 pop {r7, pc}
|
|
80013d2: bf00 nop
|
|
80013d4: 200009e4 .word 0x200009e4
|
|
|
|
080013d8 <SystemInit>:
|
|
* configuration.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
80013d8: b480 push {r7}
|
|
80013da: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
80013dc: 4b06 ldr r3, [pc, #24] @ (80013f8 <SystemInit+0x20>)
|
|
80013de: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80013e2: 4a05 ldr r2, [pc, #20] @ (80013f8 <SystemInit+0x20>)
|
|
80013e4: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
80013e8: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
80013ec: bf00 nop
|
|
80013ee: 46bd mov sp, r7
|
|
80013f0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80013f4: 4770 bx lr
|
|
80013f6: bf00 nop
|
|
80013f8: e000ed00 .word 0xe000ed00
|
|
|
|
080013fc <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* set stack pointer */
|
|
80013fc: f8df d034 ldr.w sp, [pc, #52] @ 8001434 <LoopFillZerobss+0xe>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8001400: f7ff ffea bl 80013d8 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8001404: 480c ldr r0, [pc, #48] @ (8001438 <LoopFillZerobss+0x12>)
|
|
ldr r1, =_edata
|
|
8001406: 490d ldr r1, [pc, #52] @ (800143c <LoopFillZerobss+0x16>)
|
|
ldr r2, =_sidata
|
|
8001408: 4a0d ldr r2, [pc, #52] @ (8001440 <LoopFillZerobss+0x1a>)
|
|
movs r3, #0
|
|
800140a: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
800140c: e002 b.n 8001414 <LoopCopyDataInit>
|
|
|
|
0800140e <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
800140e: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8001410: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8001412: 3304 adds r3, #4
|
|
|
|
08001414 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8001414: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8001416: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8001418: d3f9 bcc.n 800140e <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
800141a: 4a0a ldr r2, [pc, #40] @ (8001444 <LoopFillZerobss+0x1e>)
|
|
ldr r4, =_ebss
|
|
800141c: 4c0a ldr r4, [pc, #40] @ (8001448 <LoopFillZerobss+0x22>)
|
|
movs r3, #0
|
|
800141e: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8001420: e001 b.n 8001426 <LoopFillZerobss>
|
|
|
|
08001422 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8001422: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8001424: 3204 adds r2, #4
|
|
|
|
08001426 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8001426: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8001428: d3fb bcc.n 8001422 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
800142a: f008 f8bd bl 80095a8 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
800142e: f7ff f87f bl 8000530 <main>
|
|
bx lr
|
|
8001432: 4770 bx lr
|
|
ldr sp, =_estack /* set stack pointer */
|
|
8001434: 20020000 .word 0x20020000
|
|
ldr r0, =_sdata
|
|
8001438: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
800143c: 20000188 .word 0x20000188
|
|
ldr r2, =_sidata
|
|
8001440: 0800966c .word 0x0800966c
|
|
ldr r2, =_sbss
|
|
8001444: 20000188 .word 0x20000188
|
|
ldr r4, =_ebss
|
|
8001448: 20000edc .word 0x20000edc
|
|
|
|
0800144c <ADC_IRQHandler>:
|
|
* @retval None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
800144c: e7fe b.n 800144c <ADC_IRQHandler>
|
|
...
|
|
|
|
08001450 <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8001450: b580 push {r7, lr}
|
|
8001452: af00 add r7, sp, #0
|
|
/* Configure Flash prefetch, Instruction cache, Data cache */
|
|
#if (INSTRUCTION_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
|
|
8001454: 4b0e ldr r3, [pc, #56] @ (8001490 <HAL_Init+0x40>)
|
|
8001456: 681b ldr r3, [r3, #0]
|
|
8001458: 4a0d ldr r2, [pc, #52] @ (8001490 <HAL_Init+0x40>)
|
|
800145a: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
800145e: 6013 str r3, [r2, #0]
|
|
#endif /* INSTRUCTION_CACHE_ENABLE */
|
|
|
|
#if (DATA_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_DATA_CACHE_ENABLE();
|
|
8001460: 4b0b ldr r3, [pc, #44] @ (8001490 <HAL_Init+0x40>)
|
|
8001462: 681b ldr r3, [r3, #0]
|
|
8001464: 4a0a ldr r2, [pc, #40] @ (8001490 <HAL_Init+0x40>)
|
|
8001466: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
800146a: 6013 str r3, [r2, #0]
|
|
#endif /* DATA_CACHE_ENABLE */
|
|
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
800146c: 4b08 ldr r3, [pc, #32] @ (8001490 <HAL_Init+0x40>)
|
|
800146e: 681b ldr r3, [r3, #0]
|
|
8001470: 4a07 ldr r2, [pc, #28] @ (8001490 <HAL_Init+0x40>)
|
|
8001472: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8001476: 6013 str r3, [r2, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8001478: 2003 movs r0, #3
|
|
800147a: f000 f94f bl 800171c <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
800147e: 200f movs r0, #15
|
|
8001480: f000 f808 bl 8001494 <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8001484: f7ff fd22 bl 8000ecc <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8001488: 2300 movs r3, #0
|
|
}
|
|
800148a: 4618 mov r0, r3
|
|
800148c: bd80 pop {r7, pc}
|
|
800148e: bf00 nop
|
|
8001490: 40023c00 .word 0x40023c00
|
|
|
|
08001494 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8001494: b580 push {r7, lr}
|
|
8001496: b082 sub sp, #8
|
|
8001498: af00 add r7, sp, #0
|
|
800149a: 6078 str r0, [r7, #4]
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
800149c: 4b12 ldr r3, [pc, #72] @ (80014e8 <HAL_InitTick+0x54>)
|
|
800149e: 681a ldr r2, [r3, #0]
|
|
80014a0: 4b12 ldr r3, [pc, #72] @ (80014ec <HAL_InitTick+0x58>)
|
|
80014a2: 781b ldrb r3, [r3, #0]
|
|
80014a4: 4619 mov r1, r3
|
|
80014a6: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
80014aa: fbb3 f3f1 udiv r3, r3, r1
|
|
80014ae: fbb2 f3f3 udiv r3, r2, r3
|
|
80014b2: 4618 mov r0, r3
|
|
80014b4: f000 f967 bl 8001786 <HAL_SYSTICK_Config>
|
|
80014b8: 4603 mov r3, r0
|
|
80014ba: 2b00 cmp r3, #0
|
|
80014bc: d001 beq.n 80014c2 <HAL_InitTick+0x2e>
|
|
{
|
|
return HAL_ERROR;
|
|
80014be: 2301 movs r3, #1
|
|
80014c0: e00e b.n 80014e0 <HAL_InitTick+0x4c>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
80014c2: 687b ldr r3, [r7, #4]
|
|
80014c4: 2b0f cmp r3, #15
|
|
80014c6: d80a bhi.n 80014de <HAL_InitTick+0x4a>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
80014c8: 2200 movs r2, #0
|
|
80014ca: 6879 ldr r1, [r7, #4]
|
|
80014cc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80014d0: f000 f92f bl 8001732 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
80014d4: 4a06 ldr r2, [pc, #24] @ (80014f0 <HAL_InitTick+0x5c>)
|
|
80014d6: 687b ldr r3, [r7, #4]
|
|
80014d8: 6013 str r3, [r2, #0]
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80014da: 2300 movs r3, #0
|
|
80014dc: e000 b.n 80014e0 <HAL_InitTick+0x4c>
|
|
return HAL_ERROR;
|
|
80014de: 2301 movs r3, #1
|
|
}
|
|
80014e0: 4618 mov r0, r3
|
|
80014e2: 3708 adds r7, #8
|
|
80014e4: 46bd mov sp, r7
|
|
80014e6: bd80 pop {r7, pc}
|
|
80014e8: 20000078 .word 0x20000078
|
|
80014ec: 20000080 .word 0x20000080
|
|
80014f0: 2000007c .word 0x2000007c
|
|
|
|
080014f4 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
80014f4: b480 push {r7}
|
|
80014f6: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
80014f8: 4b06 ldr r3, [pc, #24] @ (8001514 <HAL_IncTick+0x20>)
|
|
80014fa: 781b ldrb r3, [r3, #0]
|
|
80014fc: 461a mov r2, r3
|
|
80014fe: 4b06 ldr r3, [pc, #24] @ (8001518 <HAL_IncTick+0x24>)
|
|
8001500: 681b ldr r3, [r3, #0]
|
|
8001502: 4413 add r3, r2
|
|
8001504: 4a04 ldr r2, [pc, #16] @ (8001518 <HAL_IncTick+0x24>)
|
|
8001506: 6013 str r3, [r2, #0]
|
|
}
|
|
8001508: bf00 nop
|
|
800150a: 46bd mov sp, r7
|
|
800150c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001510: 4770 bx lr
|
|
8001512: bf00 nop
|
|
8001514: 20000080 .word 0x20000080
|
|
8001518: 20000500 .word 0x20000500
|
|
|
|
0800151c <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
800151c: b480 push {r7}
|
|
800151e: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8001520: 4b03 ldr r3, [pc, #12] @ (8001530 <HAL_GetTick+0x14>)
|
|
8001522: 681b ldr r3, [r3, #0]
|
|
}
|
|
8001524: 4618 mov r0, r3
|
|
8001526: 46bd mov sp, r7
|
|
8001528: f85d 7b04 ldr.w r7, [sp], #4
|
|
800152c: 4770 bx lr
|
|
800152e: bf00 nop
|
|
8001530: 20000500 .word 0x20000500
|
|
|
|
08001534 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8001534: b580 push {r7, lr}
|
|
8001536: b084 sub sp, #16
|
|
8001538: af00 add r7, sp, #0
|
|
800153a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
800153c: f7ff ffee bl 800151c <HAL_GetTick>
|
|
8001540: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8001542: 687b ldr r3, [r7, #4]
|
|
8001544: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8001546: 68fb ldr r3, [r7, #12]
|
|
8001548: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800154c: d005 beq.n 800155a <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
800154e: 4b0a ldr r3, [pc, #40] @ (8001578 <HAL_Delay+0x44>)
|
|
8001550: 781b ldrb r3, [r3, #0]
|
|
8001552: 461a mov r2, r3
|
|
8001554: 68fb ldr r3, [r7, #12]
|
|
8001556: 4413 add r3, r2
|
|
8001558: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while((HAL_GetTick() - tickstart) < wait)
|
|
800155a: bf00 nop
|
|
800155c: f7ff ffde bl 800151c <HAL_GetTick>
|
|
8001560: 4602 mov r2, r0
|
|
8001562: 68bb ldr r3, [r7, #8]
|
|
8001564: 1ad3 subs r3, r2, r3
|
|
8001566: 68fa ldr r2, [r7, #12]
|
|
8001568: 429a cmp r2, r3
|
|
800156a: d8f7 bhi.n 800155c <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
800156c: bf00 nop
|
|
800156e: bf00 nop
|
|
8001570: 3710 adds r7, #16
|
|
8001572: 46bd mov sp, r7
|
|
8001574: bd80 pop {r7, pc}
|
|
8001576: bf00 nop
|
|
8001578: 20000080 .word 0x20000080
|
|
|
|
0800157c <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
800157c: b480 push {r7}
|
|
800157e: b085 sub sp, #20
|
|
8001580: af00 add r7, sp, #0
|
|
8001582: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8001584: 687b ldr r3, [r7, #4]
|
|
8001586: f003 0307 and.w r3, r3, #7
|
|
800158a: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
800158c: 4b0c ldr r3, [pc, #48] @ (80015c0 <__NVIC_SetPriorityGrouping+0x44>)
|
|
800158e: 68db ldr r3, [r3, #12]
|
|
8001590: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
8001592: 68ba ldr r2, [r7, #8]
|
|
8001594: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
8001598: 4013 ands r3, r2
|
|
800159a: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
800159c: 68fb ldr r3, [r7, #12]
|
|
800159e: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80015a0: 68bb ldr r3, [r7, #8]
|
|
80015a2: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80015a4: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80015a8: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80015ac: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80015ae: 4a04 ldr r2, [pc, #16] @ (80015c0 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80015b0: 68bb ldr r3, [r7, #8]
|
|
80015b2: 60d3 str r3, [r2, #12]
|
|
}
|
|
80015b4: bf00 nop
|
|
80015b6: 3714 adds r7, #20
|
|
80015b8: 46bd mov sp, r7
|
|
80015ba: f85d 7b04 ldr.w r7, [sp], #4
|
|
80015be: 4770 bx lr
|
|
80015c0: e000ed00 .word 0xe000ed00
|
|
|
|
080015c4 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
80015c4: b480 push {r7}
|
|
80015c6: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
80015c8: 4b04 ldr r3, [pc, #16] @ (80015dc <__NVIC_GetPriorityGrouping+0x18>)
|
|
80015ca: 68db ldr r3, [r3, #12]
|
|
80015cc: 0a1b lsrs r3, r3, #8
|
|
80015ce: f003 0307 and.w r3, r3, #7
|
|
}
|
|
80015d2: 4618 mov r0, r3
|
|
80015d4: 46bd mov sp, r7
|
|
80015d6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80015da: 4770 bx lr
|
|
80015dc: e000ed00 .word 0xe000ed00
|
|
|
|
080015e0 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
80015e0: b480 push {r7}
|
|
80015e2: b083 sub sp, #12
|
|
80015e4: af00 add r7, sp, #0
|
|
80015e6: 4603 mov r3, r0
|
|
80015e8: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
80015ea: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80015ee: 2b00 cmp r3, #0
|
|
80015f0: db0b blt.n 800160a <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
80015f2: 79fb ldrb r3, [r7, #7]
|
|
80015f4: f003 021f and.w r2, r3, #31
|
|
80015f8: 4907 ldr r1, [pc, #28] @ (8001618 <__NVIC_EnableIRQ+0x38>)
|
|
80015fa: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80015fe: 095b lsrs r3, r3, #5
|
|
8001600: 2001 movs r0, #1
|
|
8001602: fa00 f202 lsl.w r2, r0, r2
|
|
8001606: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
800160a: bf00 nop
|
|
800160c: 370c adds r7, #12
|
|
800160e: 46bd mov sp, r7
|
|
8001610: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001614: 4770 bx lr
|
|
8001616: bf00 nop
|
|
8001618: e000e100 .word 0xe000e100
|
|
|
|
0800161c <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
800161c: b480 push {r7}
|
|
800161e: b083 sub sp, #12
|
|
8001620: af00 add r7, sp, #0
|
|
8001622: 4603 mov r3, r0
|
|
8001624: 6039 str r1, [r7, #0]
|
|
8001626: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001628: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800162c: 2b00 cmp r3, #0
|
|
800162e: db0a blt.n 8001646 <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001630: 683b ldr r3, [r7, #0]
|
|
8001632: b2da uxtb r2, r3
|
|
8001634: 490c ldr r1, [pc, #48] @ (8001668 <__NVIC_SetPriority+0x4c>)
|
|
8001636: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800163a: 0112 lsls r2, r2, #4
|
|
800163c: b2d2 uxtb r2, r2
|
|
800163e: 440b add r3, r1
|
|
8001640: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8001644: e00a b.n 800165c <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001646: 683b ldr r3, [r7, #0]
|
|
8001648: b2da uxtb r2, r3
|
|
800164a: 4908 ldr r1, [pc, #32] @ (800166c <__NVIC_SetPriority+0x50>)
|
|
800164c: 79fb ldrb r3, [r7, #7]
|
|
800164e: f003 030f and.w r3, r3, #15
|
|
8001652: 3b04 subs r3, #4
|
|
8001654: 0112 lsls r2, r2, #4
|
|
8001656: b2d2 uxtb r2, r2
|
|
8001658: 440b add r3, r1
|
|
800165a: 761a strb r2, [r3, #24]
|
|
}
|
|
800165c: bf00 nop
|
|
800165e: 370c adds r7, #12
|
|
8001660: 46bd mov sp, r7
|
|
8001662: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001666: 4770 bx lr
|
|
8001668: e000e100 .word 0xe000e100
|
|
800166c: e000ed00 .word 0xe000ed00
|
|
|
|
08001670 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001670: b480 push {r7}
|
|
8001672: b089 sub sp, #36 @ 0x24
|
|
8001674: af00 add r7, sp, #0
|
|
8001676: 60f8 str r0, [r7, #12]
|
|
8001678: 60b9 str r1, [r7, #8]
|
|
800167a: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
800167c: 68fb ldr r3, [r7, #12]
|
|
800167e: f003 0307 and.w r3, r3, #7
|
|
8001682: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8001684: 69fb ldr r3, [r7, #28]
|
|
8001686: f1c3 0307 rsb r3, r3, #7
|
|
800168a: 2b04 cmp r3, #4
|
|
800168c: bf28 it cs
|
|
800168e: 2304 movcs r3, #4
|
|
8001690: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8001692: 69fb ldr r3, [r7, #28]
|
|
8001694: 3304 adds r3, #4
|
|
8001696: 2b06 cmp r3, #6
|
|
8001698: d902 bls.n 80016a0 <NVIC_EncodePriority+0x30>
|
|
800169a: 69fb ldr r3, [r7, #28]
|
|
800169c: 3b03 subs r3, #3
|
|
800169e: e000 b.n 80016a2 <NVIC_EncodePriority+0x32>
|
|
80016a0: 2300 movs r3, #0
|
|
80016a2: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80016a4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80016a8: 69bb ldr r3, [r7, #24]
|
|
80016aa: fa02 f303 lsl.w r3, r2, r3
|
|
80016ae: 43da mvns r2, r3
|
|
80016b0: 68bb ldr r3, [r7, #8]
|
|
80016b2: 401a ands r2, r3
|
|
80016b4: 697b ldr r3, [r7, #20]
|
|
80016b6: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80016b8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
80016bc: 697b ldr r3, [r7, #20]
|
|
80016be: fa01 f303 lsl.w r3, r1, r3
|
|
80016c2: 43d9 mvns r1, r3
|
|
80016c4: 687b ldr r3, [r7, #4]
|
|
80016c6: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80016c8: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
80016ca: 4618 mov r0, r3
|
|
80016cc: 3724 adds r7, #36 @ 0x24
|
|
80016ce: 46bd mov sp, r7
|
|
80016d0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80016d4: 4770 bx lr
|
|
...
|
|
|
|
080016d8 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
80016d8: b580 push {r7, lr}
|
|
80016da: b082 sub sp, #8
|
|
80016dc: af00 add r7, sp, #0
|
|
80016de: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
80016e0: 687b ldr r3, [r7, #4]
|
|
80016e2: 3b01 subs r3, #1
|
|
80016e4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
80016e8: d301 bcc.n 80016ee <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
80016ea: 2301 movs r3, #1
|
|
80016ec: e00f b.n 800170e <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
80016ee: 4a0a ldr r2, [pc, #40] @ (8001718 <SysTick_Config+0x40>)
|
|
80016f0: 687b ldr r3, [r7, #4]
|
|
80016f2: 3b01 subs r3, #1
|
|
80016f4: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
80016f6: 210f movs r1, #15
|
|
80016f8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80016fc: f7ff ff8e bl 800161c <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8001700: 4b05 ldr r3, [pc, #20] @ (8001718 <SysTick_Config+0x40>)
|
|
8001702: 2200 movs r2, #0
|
|
8001704: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8001706: 4b04 ldr r3, [pc, #16] @ (8001718 <SysTick_Config+0x40>)
|
|
8001708: 2207 movs r2, #7
|
|
800170a: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
800170c: 2300 movs r3, #0
|
|
}
|
|
800170e: 4618 mov r0, r3
|
|
8001710: 3708 adds r7, #8
|
|
8001712: 46bd mov sp, r7
|
|
8001714: bd80 pop {r7, pc}
|
|
8001716: bf00 nop
|
|
8001718: e000e010 .word 0xe000e010
|
|
|
|
0800171c <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
800171c: b580 push {r7, lr}
|
|
800171e: b082 sub sp, #8
|
|
8001720: af00 add r7, sp, #0
|
|
8001722: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8001724: 6878 ldr r0, [r7, #4]
|
|
8001726: f7ff ff29 bl 800157c <__NVIC_SetPriorityGrouping>
|
|
}
|
|
800172a: bf00 nop
|
|
800172c: 3708 adds r7, #8
|
|
800172e: 46bd mov sp, r7
|
|
8001730: bd80 pop {r7, pc}
|
|
|
|
08001732 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001732: b580 push {r7, lr}
|
|
8001734: b086 sub sp, #24
|
|
8001736: af00 add r7, sp, #0
|
|
8001738: 4603 mov r3, r0
|
|
800173a: 60b9 str r1, [r7, #8]
|
|
800173c: 607a str r2, [r7, #4]
|
|
800173e: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
8001740: 2300 movs r3, #0
|
|
8001742: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8001744: f7ff ff3e bl 80015c4 <__NVIC_GetPriorityGrouping>
|
|
8001748: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
800174a: 687a ldr r2, [r7, #4]
|
|
800174c: 68b9 ldr r1, [r7, #8]
|
|
800174e: 6978 ldr r0, [r7, #20]
|
|
8001750: f7ff ff8e bl 8001670 <NVIC_EncodePriority>
|
|
8001754: 4602 mov r2, r0
|
|
8001756: f997 300f ldrsb.w r3, [r7, #15]
|
|
800175a: 4611 mov r1, r2
|
|
800175c: 4618 mov r0, r3
|
|
800175e: f7ff ff5d bl 800161c <__NVIC_SetPriority>
|
|
}
|
|
8001762: bf00 nop
|
|
8001764: 3718 adds r7, #24
|
|
8001766: 46bd mov sp, r7
|
|
8001768: bd80 pop {r7, pc}
|
|
|
|
0800176a <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
800176a: b580 push {r7, lr}
|
|
800176c: b082 sub sp, #8
|
|
800176e: af00 add r7, sp, #0
|
|
8001770: 4603 mov r3, r0
|
|
8001772: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8001774: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001778: 4618 mov r0, r3
|
|
800177a: f7ff ff31 bl 80015e0 <__NVIC_EnableIRQ>
|
|
}
|
|
800177e: bf00 nop
|
|
8001780: 3708 adds r7, #8
|
|
8001782: 46bd mov sp, r7
|
|
8001784: bd80 pop {r7, pc}
|
|
|
|
08001786 <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
8001786: b580 push {r7, lr}
|
|
8001788: b082 sub sp, #8
|
|
800178a: af00 add r7, sp, #0
|
|
800178c: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
800178e: 6878 ldr r0, [r7, #4]
|
|
8001790: f7ff ffa2 bl 80016d8 <SysTick_Config>
|
|
8001794: 4603 mov r3, r0
|
|
}
|
|
8001796: 4618 mov r0, r3
|
|
8001798: 3708 adds r7, #8
|
|
800179a: 46bd mov sp, r7
|
|
800179c: bd80 pop {r7, pc}
|
|
|
|
0800179e <HAL_DMA_Start_IT>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
800179e: b580 push {r7, lr}
|
|
80017a0: b086 sub sp, #24
|
|
80017a2: af00 add r7, sp, #0
|
|
80017a4: 60f8 str r0, [r7, #12]
|
|
80017a6: 60b9 str r1, [r7, #8]
|
|
80017a8: 607a str r2, [r7, #4]
|
|
80017aa: 603b str r3, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80017ac: 2300 movs r3, #0
|
|
80017ae: 75fb strb r3, [r7, #23]
|
|
|
|
/* calculate DMA base and stream number */
|
|
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
|
|
80017b0: 68fb ldr r3, [r7, #12]
|
|
80017b2: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80017b4: 613b str r3, [r7, #16]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma);
|
|
80017b6: 68fb ldr r3, [r7, #12]
|
|
80017b8: f893 3034 ldrb.w r3, [r3, #52] @ 0x34
|
|
80017bc: 2b01 cmp r3, #1
|
|
80017be: d101 bne.n 80017c4 <HAL_DMA_Start_IT+0x26>
|
|
80017c0: 2302 movs r3, #2
|
|
80017c2: e040 b.n 8001846 <HAL_DMA_Start_IT+0xa8>
|
|
80017c4: 68fb ldr r3, [r7, #12]
|
|
80017c6: 2201 movs r2, #1
|
|
80017c8: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
if(HAL_DMA_STATE_READY == hdma->State)
|
|
80017cc: 68fb ldr r3, [r7, #12]
|
|
80017ce: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
|
|
80017d2: b2db uxtb r3, r3
|
|
80017d4: 2b01 cmp r3, #1
|
|
80017d6: d12f bne.n 8001838 <HAL_DMA_Start_IT+0x9a>
|
|
{
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
80017d8: 68fb ldr r3, [r7, #12]
|
|
80017da: 2202 movs r2, #2
|
|
80017dc: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Initialize the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
80017e0: 68fb ldr r3, [r7, #12]
|
|
80017e2: 2200 movs r2, #0
|
|
80017e4: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Configure the source, destination address and the data length */
|
|
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
|
80017e6: 683b ldr r3, [r7, #0]
|
|
80017e8: 687a ldr r2, [r7, #4]
|
|
80017ea: 68b9 ldr r1, [r7, #8]
|
|
80017ec: 68f8 ldr r0, [r7, #12]
|
|
80017ee: f000 f82e bl 800184e <DMA_SetConfig>
|
|
|
|
/* Clear all interrupt flags at correct offset within the register */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
80017f2: 68fb ldr r3, [r7, #12]
|
|
80017f4: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80017f6: 223f movs r2, #63 @ 0x3f
|
|
80017f8: 409a lsls r2, r3
|
|
80017fa: 693b ldr r3, [r7, #16]
|
|
80017fc: 609a str r2, [r3, #8]
|
|
|
|
/* Enable Common interrupts*/
|
|
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
|
|
80017fe: 68fb ldr r3, [r7, #12]
|
|
8001800: 681b ldr r3, [r3, #0]
|
|
8001802: 681a ldr r2, [r3, #0]
|
|
8001804: 68fb ldr r3, [r7, #12]
|
|
8001806: 681b ldr r3, [r3, #0]
|
|
8001808: f042 0216 orr.w r2, r2, #22
|
|
800180c: 601a str r2, [r3, #0]
|
|
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
800180e: 68fb ldr r3, [r7, #12]
|
|
8001810: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001812: 2b00 cmp r3, #0
|
|
8001814: d007 beq.n 8001826 <HAL_DMA_Start_IT+0x88>
|
|
{
|
|
hdma->Instance->CR |= DMA_IT_HT;
|
|
8001816: 68fb ldr r3, [r7, #12]
|
|
8001818: 681b ldr r3, [r3, #0]
|
|
800181a: 681a ldr r2, [r3, #0]
|
|
800181c: 68fb ldr r3, [r7, #12]
|
|
800181e: 681b ldr r3, [r3, #0]
|
|
8001820: f042 0208 orr.w r2, r2, #8
|
|
8001824: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_DMA_ENABLE(hdma);
|
|
8001826: 68fb ldr r3, [r7, #12]
|
|
8001828: 681b ldr r3, [r3, #0]
|
|
800182a: 681a ldr r2, [r3, #0]
|
|
800182c: 68fb ldr r3, [r7, #12]
|
|
800182e: 681b ldr r3, [r3, #0]
|
|
8001830: f042 0201 orr.w r2, r2, #1
|
|
8001834: 601a str r2, [r3, #0]
|
|
8001836: e005 b.n 8001844 <HAL_DMA_Start_IT+0xa6>
|
|
}
|
|
else
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001838: 68fb ldr r3, [r7, #12]
|
|
800183a: 2200 movs r2, #0
|
|
800183c: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
/* Return error status */
|
|
status = HAL_BUSY;
|
|
8001840: 2302 movs r3, #2
|
|
8001842: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return status;
|
|
8001844: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8001846: 4618 mov r0, r3
|
|
8001848: 3718 adds r7, #24
|
|
800184a: 46bd mov sp, r7
|
|
800184c: bd80 pop {r7, pc}
|
|
|
|
0800184e <DMA_SetConfig>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
800184e: b480 push {r7}
|
|
8001850: b085 sub sp, #20
|
|
8001852: af00 add r7, sp, #0
|
|
8001854: 60f8 str r0, [r7, #12]
|
|
8001856: 60b9 str r1, [r7, #8]
|
|
8001858: 607a str r2, [r7, #4]
|
|
800185a: 603b str r3, [r7, #0]
|
|
/* Clear DBM bit */
|
|
hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
|
|
800185c: 68fb ldr r3, [r7, #12]
|
|
800185e: 681b ldr r3, [r3, #0]
|
|
8001860: 681a ldr r2, [r3, #0]
|
|
8001862: 68fb ldr r3, [r7, #12]
|
|
8001864: 681b ldr r3, [r3, #0]
|
|
8001866: f422 2280 bic.w r2, r2, #262144 @ 0x40000
|
|
800186a: 601a str r2, [r3, #0]
|
|
|
|
/* Configure DMA Stream data length */
|
|
hdma->Instance->NDTR = DataLength;
|
|
800186c: 68fb ldr r3, [r7, #12]
|
|
800186e: 681b ldr r3, [r3, #0]
|
|
8001870: 683a ldr r2, [r7, #0]
|
|
8001872: 605a str r2, [r3, #4]
|
|
|
|
/* Memory to Peripheral */
|
|
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
|
8001874: 68fb ldr r3, [r7, #12]
|
|
8001876: 689b ldr r3, [r3, #8]
|
|
8001878: 2b40 cmp r3, #64 @ 0x40
|
|
800187a: d108 bne.n 800188e <DMA_SetConfig+0x40>
|
|
{
|
|
/* Configure DMA Stream destination address */
|
|
hdma->Instance->PAR = DstAddress;
|
|
800187c: 68fb ldr r3, [r7, #12]
|
|
800187e: 681b ldr r3, [r3, #0]
|
|
8001880: 687a ldr r2, [r7, #4]
|
|
8001882: 609a str r2, [r3, #8]
|
|
|
|
/* Configure DMA Stream source address */
|
|
hdma->Instance->M0AR = SrcAddress;
|
|
8001884: 68fb ldr r3, [r7, #12]
|
|
8001886: 681b ldr r3, [r3, #0]
|
|
8001888: 68ba ldr r2, [r7, #8]
|
|
800188a: 60da str r2, [r3, #12]
|
|
hdma->Instance->PAR = SrcAddress;
|
|
|
|
/* Configure DMA Stream destination address */
|
|
hdma->Instance->M0AR = DstAddress;
|
|
}
|
|
}
|
|
800188c: e007 b.n 800189e <DMA_SetConfig+0x50>
|
|
hdma->Instance->PAR = SrcAddress;
|
|
800188e: 68fb ldr r3, [r7, #12]
|
|
8001890: 681b ldr r3, [r3, #0]
|
|
8001892: 68ba ldr r2, [r7, #8]
|
|
8001894: 609a str r2, [r3, #8]
|
|
hdma->Instance->M0AR = DstAddress;
|
|
8001896: 68fb ldr r3, [r7, #12]
|
|
8001898: 681b ldr r3, [r3, #0]
|
|
800189a: 687a ldr r2, [r7, #4]
|
|
800189c: 60da str r2, [r3, #12]
|
|
}
|
|
800189e: bf00 nop
|
|
80018a0: 3714 adds r7, #20
|
|
80018a2: 46bd mov sp, r7
|
|
80018a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80018a8: 4770 bx lr
|
|
...
|
|
|
|
080018ac <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
80018ac: b480 push {r7}
|
|
80018ae: b089 sub sp, #36 @ 0x24
|
|
80018b0: af00 add r7, sp, #0
|
|
80018b2: 6078 str r0, [r7, #4]
|
|
80018b4: 6039 str r1, [r7, #0]
|
|
uint32_t position;
|
|
uint32_t ioposition = 0x00U;
|
|
80018b6: 2300 movs r3, #0
|
|
80018b8: 617b str r3, [r7, #20]
|
|
uint32_t iocurrent = 0x00U;
|
|
80018ba: 2300 movs r3, #0
|
|
80018bc: 613b str r3, [r7, #16]
|
|
uint32_t temp = 0x00U;
|
|
80018be: 2300 movs r3, #0
|
|
80018c0: 61bb str r3, [r7, #24]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
80018c2: 2300 movs r3, #0
|
|
80018c4: 61fb str r3, [r7, #28]
|
|
80018c6: e165 b.n 8001b94 <HAL_GPIO_Init+0x2e8>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = 0x01U << position;
|
|
80018c8: 2201 movs r2, #1
|
|
80018ca: 69fb ldr r3, [r7, #28]
|
|
80018cc: fa02 f303 lsl.w r3, r2, r3
|
|
80018d0: 617b str r3, [r7, #20]
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
80018d2: 683b ldr r3, [r7, #0]
|
|
80018d4: 681b ldr r3, [r3, #0]
|
|
80018d6: 697a ldr r2, [r7, #20]
|
|
80018d8: 4013 ands r3, r2
|
|
80018da: 613b str r3, [r7, #16]
|
|
|
|
if(iocurrent == ioposition)
|
|
80018dc: 693a ldr r2, [r7, #16]
|
|
80018de: 697b ldr r3, [r7, #20]
|
|
80018e0: 429a cmp r2, r3
|
|
80018e2: f040 8154 bne.w 8001b8e <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
80018e6: 683b ldr r3, [r7, #0]
|
|
80018e8: 685b ldr r3, [r3, #4]
|
|
80018ea: f003 0303 and.w r3, r3, #3
|
|
80018ee: 2b01 cmp r3, #1
|
|
80018f0: d005 beq.n 80018fe <HAL_GPIO_Init+0x52>
|
|
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
80018f2: 683b ldr r3, [r7, #0]
|
|
80018f4: 685b ldr r3, [r3, #4]
|
|
80018f6: f003 0303 and.w r3, r3, #3
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
80018fa: 2b02 cmp r3, #2
|
|
80018fc: d130 bne.n 8001960 <HAL_GPIO_Init+0xb4>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
80018fe: 687b ldr r3, [r7, #4]
|
|
8001900: 689b ldr r3, [r3, #8]
|
|
8001902: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
|
8001904: 69fb ldr r3, [r7, #28]
|
|
8001906: 005b lsls r3, r3, #1
|
|
8001908: 2203 movs r2, #3
|
|
800190a: fa02 f303 lsl.w r3, r2, r3
|
|
800190e: 43db mvns r3, r3
|
|
8001910: 69ba ldr r2, [r7, #24]
|
|
8001912: 4013 ands r3, r2
|
|
8001914: 61bb str r3, [r7, #24]
|
|
temp |= (GPIO_Init->Speed << (position * 2U));
|
|
8001916: 683b ldr r3, [r7, #0]
|
|
8001918: 68da ldr r2, [r3, #12]
|
|
800191a: 69fb ldr r3, [r7, #28]
|
|
800191c: 005b lsls r3, r3, #1
|
|
800191e: fa02 f303 lsl.w r3, r2, r3
|
|
8001922: 69ba ldr r2, [r7, #24]
|
|
8001924: 4313 orrs r3, r2
|
|
8001926: 61bb str r3, [r7, #24]
|
|
GPIOx->OSPEEDR = temp;
|
|
8001928: 687b ldr r3, [r7, #4]
|
|
800192a: 69ba ldr r2, [r7, #24]
|
|
800192c: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
800192e: 687b ldr r3, [r7, #4]
|
|
8001930: 685b ldr r3, [r3, #4]
|
|
8001932: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
8001934: 2201 movs r2, #1
|
|
8001936: 69fb ldr r3, [r7, #28]
|
|
8001938: fa02 f303 lsl.w r3, r2, r3
|
|
800193c: 43db mvns r3, r3
|
|
800193e: 69ba ldr r2, [r7, #24]
|
|
8001940: 4013 ands r3, r2
|
|
8001942: 61bb str r3, [r7, #24]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8001944: 683b ldr r3, [r7, #0]
|
|
8001946: 685b ldr r3, [r3, #4]
|
|
8001948: 091b lsrs r3, r3, #4
|
|
800194a: f003 0201 and.w r2, r3, #1
|
|
800194e: 69fb ldr r3, [r7, #28]
|
|
8001950: fa02 f303 lsl.w r3, r2, r3
|
|
8001954: 69ba ldr r2, [r7, #24]
|
|
8001956: 4313 orrs r3, r2
|
|
8001958: 61bb str r3, [r7, #24]
|
|
GPIOx->OTYPER = temp;
|
|
800195a: 687b ldr r3, [r7, #4]
|
|
800195c: 69ba ldr r2, [r7, #24]
|
|
800195e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
8001960: 683b ldr r3, [r7, #0]
|
|
8001962: 685b ldr r3, [r3, #4]
|
|
8001964: f003 0303 and.w r3, r3, #3
|
|
8001968: 2b03 cmp r3, #3
|
|
800196a: d017 beq.n 800199c <HAL_GPIO_Init+0xf0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
800196c: 687b ldr r3, [r7, #4]
|
|
800196e: 68db ldr r3, [r3, #12]
|
|
8001970: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
|
8001972: 69fb ldr r3, [r7, #28]
|
|
8001974: 005b lsls r3, r3, #1
|
|
8001976: 2203 movs r2, #3
|
|
8001978: fa02 f303 lsl.w r3, r2, r3
|
|
800197c: 43db mvns r3, r3
|
|
800197e: 69ba ldr r2, [r7, #24]
|
|
8001980: 4013 ands r3, r2
|
|
8001982: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
8001984: 683b ldr r3, [r7, #0]
|
|
8001986: 689a ldr r2, [r3, #8]
|
|
8001988: 69fb ldr r3, [r7, #28]
|
|
800198a: 005b lsls r3, r3, #1
|
|
800198c: fa02 f303 lsl.w r3, r2, r3
|
|
8001990: 69ba ldr r2, [r7, #24]
|
|
8001992: 4313 orrs r3, r2
|
|
8001994: 61bb str r3, [r7, #24]
|
|
GPIOx->PUPDR = temp;
|
|
8001996: 687b ldr r3, [r7, #4]
|
|
8001998: 69ba ldr r2, [r7, #24]
|
|
800199a: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
800199c: 683b ldr r3, [r7, #0]
|
|
800199e: 685b ldr r3, [r3, #4]
|
|
80019a0: f003 0303 and.w r3, r3, #3
|
|
80019a4: 2b02 cmp r3, #2
|
|
80019a6: d123 bne.n 80019f0 <HAL_GPIO_Init+0x144>
|
|
{
|
|
/* Check the Alternate function parameter */
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3U];
|
|
80019a8: 69fb ldr r3, [r7, #28]
|
|
80019aa: 08da lsrs r2, r3, #3
|
|
80019ac: 687b ldr r3, [r7, #4]
|
|
80019ae: 3208 adds r2, #8
|
|
80019b0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80019b4: 61bb str r3, [r7, #24]
|
|
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
|
|
80019b6: 69fb ldr r3, [r7, #28]
|
|
80019b8: f003 0307 and.w r3, r3, #7
|
|
80019bc: 009b lsls r3, r3, #2
|
|
80019be: 220f movs r2, #15
|
|
80019c0: fa02 f303 lsl.w r3, r2, r3
|
|
80019c4: 43db mvns r3, r3
|
|
80019c6: 69ba ldr r2, [r7, #24]
|
|
80019c8: 4013 ands r3, r2
|
|
80019ca: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
|
|
80019cc: 683b ldr r3, [r7, #0]
|
|
80019ce: 691a ldr r2, [r3, #16]
|
|
80019d0: 69fb ldr r3, [r7, #28]
|
|
80019d2: f003 0307 and.w r3, r3, #7
|
|
80019d6: 009b lsls r3, r3, #2
|
|
80019d8: fa02 f303 lsl.w r3, r2, r3
|
|
80019dc: 69ba ldr r2, [r7, #24]
|
|
80019de: 4313 orrs r3, r2
|
|
80019e0: 61bb str r3, [r7, #24]
|
|
GPIOx->AFR[position >> 3U] = temp;
|
|
80019e2: 69fb ldr r3, [r7, #28]
|
|
80019e4: 08da lsrs r2, r3, #3
|
|
80019e6: 687b ldr r3, [r7, #4]
|
|
80019e8: 3208 adds r2, #8
|
|
80019ea: 69b9 ldr r1, [r7, #24]
|
|
80019ec: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
80019f0: 687b ldr r3, [r7, #4]
|
|
80019f2: 681b ldr r3, [r3, #0]
|
|
80019f4: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
|
80019f6: 69fb ldr r3, [r7, #28]
|
|
80019f8: 005b lsls r3, r3, #1
|
|
80019fa: 2203 movs r2, #3
|
|
80019fc: fa02 f303 lsl.w r3, r2, r3
|
|
8001a00: 43db mvns r3, r3
|
|
8001a02: 69ba ldr r2, [r7, #24]
|
|
8001a04: 4013 ands r3, r2
|
|
8001a06: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
|
8001a08: 683b ldr r3, [r7, #0]
|
|
8001a0a: 685b ldr r3, [r3, #4]
|
|
8001a0c: f003 0203 and.w r2, r3, #3
|
|
8001a10: 69fb ldr r3, [r7, #28]
|
|
8001a12: 005b lsls r3, r3, #1
|
|
8001a14: fa02 f303 lsl.w r3, r2, r3
|
|
8001a18: 69ba ldr r2, [r7, #24]
|
|
8001a1a: 4313 orrs r3, r2
|
|
8001a1c: 61bb str r3, [r7, #24]
|
|
GPIOx->MODER = temp;
|
|
8001a1e: 687b ldr r3, [r7, #4]
|
|
8001a20: 69ba ldr r2, [r7, #24]
|
|
8001a22: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
|
|
8001a24: 683b ldr r3, [r7, #0]
|
|
8001a26: 685b ldr r3, [r3, #4]
|
|
8001a28: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8001a2c: 2b00 cmp r3, #0
|
|
8001a2e: f000 80ae beq.w 8001b8e <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8001a32: 2300 movs r3, #0
|
|
8001a34: 60fb str r3, [r7, #12]
|
|
8001a36: 4b5d ldr r3, [pc, #372] @ (8001bac <HAL_GPIO_Init+0x300>)
|
|
8001a38: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001a3a: 4a5c ldr r2, [pc, #368] @ (8001bac <HAL_GPIO_Init+0x300>)
|
|
8001a3c: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8001a40: 6453 str r3, [r2, #68] @ 0x44
|
|
8001a42: 4b5a ldr r3, [pc, #360] @ (8001bac <HAL_GPIO_Init+0x300>)
|
|
8001a44: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001a46: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8001a4a: 60fb str r3, [r7, #12]
|
|
8001a4c: 68fb ldr r3, [r7, #12]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2U];
|
|
8001a4e: 4a58 ldr r2, [pc, #352] @ (8001bb0 <HAL_GPIO_Init+0x304>)
|
|
8001a50: 69fb ldr r3, [r7, #28]
|
|
8001a52: 089b lsrs r3, r3, #2
|
|
8001a54: 3302 adds r3, #2
|
|
8001a56: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8001a5a: 61bb str r3, [r7, #24]
|
|
temp &= ~(0x0FU << (4U * (position & 0x03U)));
|
|
8001a5c: 69fb ldr r3, [r7, #28]
|
|
8001a5e: f003 0303 and.w r3, r3, #3
|
|
8001a62: 009b lsls r3, r3, #2
|
|
8001a64: 220f movs r2, #15
|
|
8001a66: fa02 f303 lsl.w r3, r2, r3
|
|
8001a6a: 43db mvns r3, r3
|
|
8001a6c: 69ba ldr r2, [r7, #24]
|
|
8001a6e: 4013 ands r3, r2
|
|
8001a70: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
|
|
8001a72: 687b ldr r3, [r7, #4]
|
|
8001a74: 4a4f ldr r2, [pc, #316] @ (8001bb4 <HAL_GPIO_Init+0x308>)
|
|
8001a76: 4293 cmp r3, r2
|
|
8001a78: d025 beq.n 8001ac6 <HAL_GPIO_Init+0x21a>
|
|
8001a7a: 687b ldr r3, [r7, #4]
|
|
8001a7c: 4a4e ldr r2, [pc, #312] @ (8001bb8 <HAL_GPIO_Init+0x30c>)
|
|
8001a7e: 4293 cmp r3, r2
|
|
8001a80: d01f beq.n 8001ac2 <HAL_GPIO_Init+0x216>
|
|
8001a82: 687b ldr r3, [r7, #4]
|
|
8001a84: 4a4d ldr r2, [pc, #308] @ (8001bbc <HAL_GPIO_Init+0x310>)
|
|
8001a86: 4293 cmp r3, r2
|
|
8001a88: d019 beq.n 8001abe <HAL_GPIO_Init+0x212>
|
|
8001a8a: 687b ldr r3, [r7, #4]
|
|
8001a8c: 4a4c ldr r2, [pc, #304] @ (8001bc0 <HAL_GPIO_Init+0x314>)
|
|
8001a8e: 4293 cmp r3, r2
|
|
8001a90: d013 beq.n 8001aba <HAL_GPIO_Init+0x20e>
|
|
8001a92: 687b ldr r3, [r7, #4]
|
|
8001a94: 4a4b ldr r2, [pc, #300] @ (8001bc4 <HAL_GPIO_Init+0x318>)
|
|
8001a96: 4293 cmp r3, r2
|
|
8001a98: d00d beq.n 8001ab6 <HAL_GPIO_Init+0x20a>
|
|
8001a9a: 687b ldr r3, [r7, #4]
|
|
8001a9c: 4a4a ldr r2, [pc, #296] @ (8001bc8 <HAL_GPIO_Init+0x31c>)
|
|
8001a9e: 4293 cmp r3, r2
|
|
8001aa0: d007 beq.n 8001ab2 <HAL_GPIO_Init+0x206>
|
|
8001aa2: 687b ldr r3, [r7, #4]
|
|
8001aa4: 4a49 ldr r2, [pc, #292] @ (8001bcc <HAL_GPIO_Init+0x320>)
|
|
8001aa6: 4293 cmp r3, r2
|
|
8001aa8: d101 bne.n 8001aae <HAL_GPIO_Init+0x202>
|
|
8001aaa: 2306 movs r3, #6
|
|
8001aac: e00c b.n 8001ac8 <HAL_GPIO_Init+0x21c>
|
|
8001aae: 2307 movs r3, #7
|
|
8001ab0: e00a b.n 8001ac8 <HAL_GPIO_Init+0x21c>
|
|
8001ab2: 2305 movs r3, #5
|
|
8001ab4: e008 b.n 8001ac8 <HAL_GPIO_Init+0x21c>
|
|
8001ab6: 2304 movs r3, #4
|
|
8001ab8: e006 b.n 8001ac8 <HAL_GPIO_Init+0x21c>
|
|
8001aba: 2303 movs r3, #3
|
|
8001abc: e004 b.n 8001ac8 <HAL_GPIO_Init+0x21c>
|
|
8001abe: 2302 movs r3, #2
|
|
8001ac0: e002 b.n 8001ac8 <HAL_GPIO_Init+0x21c>
|
|
8001ac2: 2301 movs r3, #1
|
|
8001ac4: e000 b.n 8001ac8 <HAL_GPIO_Init+0x21c>
|
|
8001ac6: 2300 movs r3, #0
|
|
8001ac8: 69fa ldr r2, [r7, #28]
|
|
8001aca: f002 0203 and.w r2, r2, #3
|
|
8001ace: 0092 lsls r2, r2, #2
|
|
8001ad0: 4093 lsls r3, r2
|
|
8001ad2: 69ba ldr r2, [r7, #24]
|
|
8001ad4: 4313 orrs r3, r2
|
|
8001ad6: 61bb str r3, [r7, #24]
|
|
SYSCFG->EXTICR[position >> 2U] = temp;
|
|
8001ad8: 4935 ldr r1, [pc, #212] @ (8001bb0 <HAL_GPIO_Init+0x304>)
|
|
8001ada: 69fb ldr r3, [r7, #28]
|
|
8001adc: 089b lsrs r3, r3, #2
|
|
8001ade: 3302 adds r3, #2
|
|
8001ae0: 69ba ldr r2, [r7, #24]
|
|
8001ae2: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR;
|
|
8001ae6: 4b3a ldr r3, [pc, #232] @ (8001bd0 <HAL_GPIO_Init+0x324>)
|
|
8001ae8: 689b ldr r3, [r3, #8]
|
|
8001aea: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001aec: 693b ldr r3, [r7, #16]
|
|
8001aee: 43db mvns r3, r3
|
|
8001af0: 69ba ldr r2, [r7, #24]
|
|
8001af2: 4013 ands r3, r2
|
|
8001af4: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
|
|
8001af6: 683b ldr r3, [r7, #0]
|
|
8001af8: 685b ldr r3, [r3, #4]
|
|
8001afa: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8001afe: 2b00 cmp r3, #0
|
|
8001b00: d003 beq.n 8001b0a <HAL_GPIO_Init+0x25e>
|
|
{
|
|
temp |= iocurrent;
|
|
8001b02: 69ba ldr r2, [r7, #24]
|
|
8001b04: 693b ldr r3, [r7, #16]
|
|
8001b06: 4313 orrs r3, r2
|
|
8001b08: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->RTSR = temp;
|
|
8001b0a: 4a31 ldr r2, [pc, #196] @ (8001bd0 <HAL_GPIO_Init+0x324>)
|
|
8001b0c: 69bb ldr r3, [r7, #24]
|
|
8001b0e: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR;
|
|
8001b10: 4b2f ldr r3, [pc, #188] @ (8001bd0 <HAL_GPIO_Init+0x324>)
|
|
8001b12: 68db ldr r3, [r3, #12]
|
|
8001b14: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001b16: 693b ldr r3, [r7, #16]
|
|
8001b18: 43db mvns r3, r3
|
|
8001b1a: 69ba ldr r2, [r7, #24]
|
|
8001b1c: 4013 ands r3, r2
|
|
8001b1e: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
|
|
8001b20: 683b ldr r3, [r7, #0]
|
|
8001b22: 685b ldr r3, [r3, #4]
|
|
8001b24: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8001b28: 2b00 cmp r3, #0
|
|
8001b2a: d003 beq.n 8001b34 <HAL_GPIO_Init+0x288>
|
|
{
|
|
temp |= iocurrent;
|
|
8001b2c: 69ba ldr r2, [r7, #24]
|
|
8001b2e: 693b ldr r3, [r7, #16]
|
|
8001b30: 4313 orrs r3, r2
|
|
8001b32: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->FTSR = temp;
|
|
8001b34: 4a26 ldr r2, [pc, #152] @ (8001bd0 <HAL_GPIO_Init+0x324>)
|
|
8001b36: 69bb ldr r3, [r7, #24]
|
|
8001b38: 60d3 str r3, [r2, #12]
|
|
|
|
temp = EXTI->EMR;
|
|
8001b3a: 4b25 ldr r3, [pc, #148] @ (8001bd0 <HAL_GPIO_Init+0x324>)
|
|
8001b3c: 685b ldr r3, [r3, #4]
|
|
8001b3e: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001b40: 693b ldr r3, [r7, #16]
|
|
8001b42: 43db mvns r3, r3
|
|
8001b44: 69ba ldr r2, [r7, #24]
|
|
8001b46: 4013 ands r3, r2
|
|
8001b48: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
|
|
8001b4a: 683b ldr r3, [r7, #0]
|
|
8001b4c: 685b ldr r3, [r3, #4]
|
|
8001b4e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001b52: 2b00 cmp r3, #0
|
|
8001b54: d003 beq.n 8001b5e <HAL_GPIO_Init+0x2b2>
|
|
{
|
|
temp |= iocurrent;
|
|
8001b56: 69ba ldr r2, [r7, #24]
|
|
8001b58: 693b ldr r3, [r7, #16]
|
|
8001b5a: 4313 orrs r3, r2
|
|
8001b5c: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->EMR = temp;
|
|
8001b5e: 4a1c ldr r2, [pc, #112] @ (8001bd0 <HAL_GPIO_Init+0x324>)
|
|
8001b60: 69bb ldr r3, [r7, #24]
|
|
8001b62: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR;
|
|
8001b64: 4b1a ldr r3, [pc, #104] @ (8001bd0 <HAL_GPIO_Init+0x324>)
|
|
8001b66: 681b ldr r3, [r3, #0]
|
|
8001b68: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001b6a: 693b ldr r3, [r7, #16]
|
|
8001b6c: 43db mvns r3, r3
|
|
8001b6e: 69ba ldr r2, [r7, #24]
|
|
8001b70: 4013 ands r3, r2
|
|
8001b72: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
|
|
8001b74: 683b ldr r3, [r7, #0]
|
|
8001b76: 685b ldr r3, [r3, #4]
|
|
8001b78: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8001b7c: 2b00 cmp r3, #0
|
|
8001b7e: d003 beq.n 8001b88 <HAL_GPIO_Init+0x2dc>
|
|
{
|
|
temp |= iocurrent;
|
|
8001b80: 69ba ldr r2, [r7, #24]
|
|
8001b82: 693b ldr r3, [r7, #16]
|
|
8001b84: 4313 orrs r3, r2
|
|
8001b86: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->IMR = temp;
|
|
8001b88: 4a11 ldr r2, [pc, #68] @ (8001bd0 <HAL_GPIO_Init+0x324>)
|
|
8001b8a: 69bb ldr r3, [r7, #24]
|
|
8001b8c: 6013 str r3, [r2, #0]
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
8001b8e: 69fb ldr r3, [r7, #28]
|
|
8001b90: 3301 adds r3, #1
|
|
8001b92: 61fb str r3, [r7, #28]
|
|
8001b94: 69fb ldr r3, [r7, #28]
|
|
8001b96: 2b0f cmp r3, #15
|
|
8001b98: f67f ae96 bls.w 80018c8 <HAL_GPIO_Init+0x1c>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8001b9c: bf00 nop
|
|
8001b9e: bf00 nop
|
|
8001ba0: 3724 adds r7, #36 @ 0x24
|
|
8001ba2: 46bd mov sp, r7
|
|
8001ba4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001ba8: 4770 bx lr
|
|
8001baa: bf00 nop
|
|
8001bac: 40023800 .word 0x40023800
|
|
8001bb0: 40013800 .word 0x40013800
|
|
8001bb4: 40020000 .word 0x40020000
|
|
8001bb8: 40020400 .word 0x40020400
|
|
8001bbc: 40020800 .word 0x40020800
|
|
8001bc0: 40020c00 .word 0x40020c00
|
|
8001bc4: 40021000 .word 0x40021000
|
|
8001bc8: 40021400 .word 0x40021400
|
|
8001bcc: 40021800 .word 0x40021800
|
|
8001bd0: 40013c00 .word 0x40013c00
|
|
|
|
08001bd4 <HAL_GPIO_ReadPin>:
|
|
* @param GPIO_Pin specifies the port bit to read.
|
|
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
|
* @retval The input port pin value.
|
|
*/
|
|
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
8001bd4: b480 push {r7}
|
|
8001bd6: b085 sub sp, #20
|
|
8001bd8: af00 add r7, sp, #0
|
|
8001bda: 6078 str r0, [r7, #4]
|
|
8001bdc: 460b mov r3, r1
|
|
8001bde: 807b strh r3, [r7, #2]
|
|
GPIO_PinState bitstatus;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
|
8001be0: 687b ldr r3, [r7, #4]
|
|
8001be2: 691a ldr r2, [r3, #16]
|
|
8001be4: 887b ldrh r3, [r7, #2]
|
|
8001be6: 4013 ands r3, r2
|
|
8001be8: 2b00 cmp r3, #0
|
|
8001bea: d002 beq.n 8001bf2 <HAL_GPIO_ReadPin+0x1e>
|
|
{
|
|
bitstatus = GPIO_PIN_SET;
|
|
8001bec: 2301 movs r3, #1
|
|
8001bee: 73fb strb r3, [r7, #15]
|
|
8001bf0: e001 b.n 8001bf6 <HAL_GPIO_ReadPin+0x22>
|
|
}
|
|
else
|
|
{
|
|
bitstatus = GPIO_PIN_RESET;
|
|
8001bf2: 2300 movs r3, #0
|
|
8001bf4: 73fb strb r3, [r7, #15]
|
|
}
|
|
return bitstatus;
|
|
8001bf6: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001bf8: 4618 mov r0, r3
|
|
8001bfa: 3714 adds r7, #20
|
|
8001bfc: 46bd mov sp, r7
|
|
8001bfe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001c02: 4770 bx lr
|
|
|
|
08001c04 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8001c04: b480 push {r7}
|
|
8001c06: b083 sub sp, #12
|
|
8001c08: af00 add r7, sp, #0
|
|
8001c0a: 6078 str r0, [r7, #4]
|
|
8001c0c: 460b mov r3, r1
|
|
8001c0e: 807b strh r3, [r7, #2]
|
|
8001c10: 4613 mov r3, r2
|
|
8001c12: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8001c14: 787b ldrb r3, [r7, #1]
|
|
8001c16: 2b00 cmp r3, #0
|
|
8001c18: d003 beq.n 8001c22 <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = GPIO_Pin;
|
|
8001c1a: 887a ldrh r2, [r7, #2]
|
|
8001c1c: 687b ldr r3, [r7, #4]
|
|
8001c1e: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
}
|
|
}
|
|
8001c20: e003 b.n 8001c2a <HAL_GPIO_WritePin+0x26>
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
8001c22: 887b ldrh r3, [r7, #2]
|
|
8001c24: 041a lsls r2, r3, #16
|
|
8001c26: 687b ldr r3, [r7, #4]
|
|
8001c28: 619a str r2, [r3, #24]
|
|
}
|
|
8001c2a: bf00 nop
|
|
8001c2c: 370c adds r7, #12
|
|
8001c2e: 46bd mov sp, r7
|
|
8001c30: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001c34: 4770 bx lr
|
|
...
|
|
|
|
08001c38 <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8001c38: b580 push {r7, lr}
|
|
8001c3a: b084 sub sp, #16
|
|
8001c3c: af00 add r7, sp, #0
|
|
8001c3e: 6078 str r0, [r7, #4]
|
|
uint32_t freqrange;
|
|
uint32_t pclk1;
|
|
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8001c40: 687b ldr r3, [r7, #4]
|
|
8001c42: 2b00 cmp r3, #0
|
|
8001c44: d101 bne.n 8001c4a <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001c46: 2301 movs r3, #1
|
|
8001c48: e12b b.n 8001ea2 <HAL_I2C_Init+0x26a>
|
|
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
8001c4a: 687b ldr r3, [r7, #4]
|
|
8001c4c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8001c50: b2db uxtb r3, r3
|
|
8001c52: 2b00 cmp r3, #0
|
|
8001c54: d106 bne.n 8001c64 <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
8001c56: 687b ldr r3, [r7, #4]
|
|
8001c58: 2200 movs r2, #0
|
|
8001c5a: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_I2C_MspInit(hi2c);
|
|
8001c5e: 6878 ldr r0, [r7, #4]
|
|
8001c60: f7ff f95c bl 8000f1c <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8001c64: 687b ldr r3, [r7, #4]
|
|
8001c66: 2224 movs r2, #36 @ 0x24
|
|
8001c68: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8001c6c: 687b ldr r3, [r7, #4]
|
|
8001c6e: 681b ldr r3, [r3, #0]
|
|
8001c70: 681a ldr r2, [r3, #0]
|
|
8001c72: 687b ldr r3, [r7, #4]
|
|
8001c74: 681b ldr r3, [r3, #0]
|
|
8001c76: f022 0201 bic.w r2, r2, #1
|
|
8001c7a: 601a str r2, [r3, #0]
|
|
|
|
/*Reset I2C*/
|
|
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
|
|
8001c7c: 687b ldr r3, [r7, #4]
|
|
8001c7e: 681b ldr r3, [r3, #0]
|
|
8001c80: 681a ldr r2, [r3, #0]
|
|
8001c82: 687b ldr r3, [r7, #4]
|
|
8001c84: 681b ldr r3, [r3, #0]
|
|
8001c86: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
8001c8a: 601a str r2, [r3, #0]
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
|
|
8001c8c: 687b ldr r3, [r7, #4]
|
|
8001c8e: 681b ldr r3, [r3, #0]
|
|
8001c90: 681a ldr r2, [r3, #0]
|
|
8001c92: 687b ldr r3, [r7, #4]
|
|
8001c94: 681b ldr r3, [r3, #0]
|
|
8001c96: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8001c9a: 601a str r2, [r3, #0]
|
|
|
|
/* Get PCLK1 frequency */
|
|
pclk1 = HAL_RCC_GetPCLK1Freq();
|
|
8001c9c: f001 fc88 bl 80035b0 <HAL_RCC_GetPCLK1Freq>
|
|
8001ca0: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check the minimum allowed PCLK1 frequency */
|
|
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
|
|
8001ca2: 687b ldr r3, [r7, #4]
|
|
8001ca4: 685b ldr r3, [r3, #4]
|
|
8001ca6: 4a81 ldr r2, [pc, #516] @ (8001eac <HAL_I2C_Init+0x274>)
|
|
8001ca8: 4293 cmp r3, r2
|
|
8001caa: d807 bhi.n 8001cbc <HAL_I2C_Init+0x84>
|
|
8001cac: 68fb ldr r3, [r7, #12]
|
|
8001cae: 4a80 ldr r2, [pc, #512] @ (8001eb0 <HAL_I2C_Init+0x278>)
|
|
8001cb0: 4293 cmp r3, r2
|
|
8001cb2: bf94 ite ls
|
|
8001cb4: 2301 movls r3, #1
|
|
8001cb6: 2300 movhi r3, #0
|
|
8001cb8: b2db uxtb r3, r3
|
|
8001cba: e006 b.n 8001cca <HAL_I2C_Init+0x92>
|
|
8001cbc: 68fb ldr r3, [r7, #12]
|
|
8001cbe: 4a7d ldr r2, [pc, #500] @ (8001eb4 <HAL_I2C_Init+0x27c>)
|
|
8001cc0: 4293 cmp r3, r2
|
|
8001cc2: bf94 ite ls
|
|
8001cc4: 2301 movls r3, #1
|
|
8001cc6: 2300 movhi r3, #0
|
|
8001cc8: b2db uxtb r3, r3
|
|
8001cca: 2b00 cmp r3, #0
|
|
8001ccc: d001 beq.n 8001cd2 <HAL_I2C_Init+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
8001cce: 2301 movs r3, #1
|
|
8001cd0: e0e7 b.n 8001ea2 <HAL_I2C_Init+0x26a>
|
|
}
|
|
|
|
/* Calculate frequency range */
|
|
freqrange = I2C_FREQRANGE(pclk1);
|
|
8001cd2: 68fb ldr r3, [r7, #12]
|
|
8001cd4: 4a78 ldr r2, [pc, #480] @ (8001eb8 <HAL_I2C_Init+0x280>)
|
|
8001cd6: fba2 2303 umull r2, r3, r2, r3
|
|
8001cda: 0c9b lsrs r3, r3, #18
|
|
8001cdc: 60bb str r3, [r7, #8]
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
|
|
8001cde: 687b ldr r3, [r7, #4]
|
|
8001ce0: 681b ldr r3, [r3, #0]
|
|
8001ce2: 685b ldr r3, [r3, #4]
|
|
8001ce4: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
8001ce8: 687b ldr r3, [r7, #4]
|
|
8001cea: 681b ldr r3, [r3, #0]
|
|
8001cec: 68ba ldr r2, [r7, #8]
|
|
8001cee: 430a orrs r2, r1
|
|
8001cf0: 605a str r2, [r3, #4]
|
|
|
|
/*---------------------------- I2Cx TRISE Configuration --------------------*/
|
|
/* Configure I2Cx: Rise Time */
|
|
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
|
|
8001cf2: 687b ldr r3, [r7, #4]
|
|
8001cf4: 681b ldr r3, [r3, #0]
|
|
8001cf6: 6a1b ldr r3, [r3, #32]
|
|
8001cf8: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
8001cfc: 687b ldr r3, [r7, #4]
|
|
8001cfe: 685b ldr r3, [r3, #4]
|
|
8001d00: 4a6a ldr r2, [pc, #424] @ (8001eac <HAL_I2C_Init+0x274>)
|
|
8001d02: 4293 cmp r3, r2
|
|
8001d04: d802 bhi.n 8001d0c <HAL_I2C_Init+0xd4>
|
|
8001d06: 68bb ldr r3, [r7, #8]
|
|
8001d08: 3301 adds r3, #1
|
|
8001d0a: e009 b.n 8001d20 <HAL_I2C_Init+0xe8>
|
|
8001d0c: 68bb ldr r3, [r7, #8]
|
|
8001d0e: f44f 7296 mov.w r2, #300 @ 0x12c
|
|
8001d12: fb02 f303 mul.w r3, r2, r3
|
|
8001d16: 4a69 ldr r2, [pc, #420] @ (8001ebc <HAL_I2C_Init+0x284>)
|
|
8001d18: fba2 2303 umull r2, r3, r2, r3
|
|
8001d1c: 099b lsrs r3, r3, #6
|
|
8001d1e: 3301 adds r3, #1
|
|
8001d20: 687a ldr r2, [r7, #4]
|
|
8001d22: 6812 ldr r2, [r2, #0]
|
|
8001d24: 430b orrs r3, r1
|
|
8001d26: 6213 str r3, [r2, #32]
|
|
|
|
/*---------------------------- I2Cx CCR Configuration ----------------------*/
|
|
/* Configure I2Cx: Speed */
|
|
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
|
|
8001d28: 687b ldr r3, [r7, #4]
|
|
8001d2a: 681b ldr r3, [r3, #0]
|
|
8001d2c: 69db ldr r3, [r3, #28]
|
|
8001d2e: f423 424f bic.w r2, r3, #52992 @ 0xcf00
|
|
8001d32: f022 02ff bic.w r2, r2, #255 @ 0xff
|
|
8001d36: 687b ldr r3, [r7, #4]
|
|
8001d38: 685b ldr r3, [r3, #4]
|
|
8001d3a: 495c ldr r1, [pc, #368] @ (8001eac <HAL_I2C_Init+0x274>)
|
|
8001d3c: 428b cmp r3, r1
|
|
8001d3e: d819 bhi.n 8001d74 <HAL_I2C_Init+0x13c>
|
|
8001d40: 68fb ldr r3, [r7, #12]
|
|
8001d42: 1e59 subs r1, r3, #1
|
|
8001d44: 687b ldr r3, [r7, #4]
|
|
8001d46: 685b ldr r3, [r3, #4]
|
|
8001d48: 005b lsls r3, r3, #1
|
|
8001d4a: fbb1 f3f3 udiv r3, r1, r3
|
|
8001d4e: 1c59 adds r1, r3, #1
|
|
8001d50: f640 73fc movw r3, #4092 @ 0xffc
|
|
8001d54: 400b ands r3, r1
|
|
8001d56: 2b00 cmp r3, #0
|
|
8001d58: d00a beq.n 8001d70 <HAL_I2C_Init+0x138>
|
|
8001d5a: 68fb ldr r3, [r7, #12]
|
|
8001d5c: 1e59 subs r1, r3, #1
|
|
8001d5e: 687b ldr r3, [r7, #4]
|
|
8001d60: 685b ldr r3, [r3, #4]
|
|
8001d62: 005b lsls r3, r3, #1
|
|
8001d64: fbb1 f3f3 udiv r3, r1, r3
|
|
8001d68: 3301 adds r3, #1
|
|
8001d6a: f3c3 030b ubfx r3, r3, #0, #12
|
|
8001d6e: e051 b.n 8001e14 <HAL_I2C_Init+0x1dc>
|
|
8001d70: 2304 movs r3, #4
|
|
8001d72: e04f b.n 8001e14 <HAL_I2C_Init+0x1dc>
|
|
8001d74: 687b ldr r3, [r7, #4]
|
|
8001d76: 689b ldr r3, [r3, #8]
|
|
8001d78: 2b00 cmp r3, #0
|
|
8001d7a: d111 bne.n 8001da0 <HAL_I2C_Init+0x168>
|
|
8001d7c: 68fb ldr r3, [r7, #12]
|
|
8001d7e: 1e58 subs r0, r3, #1
|
|
8001d80: 687b ldr r3, [r7, #4]
|
|
8001d82: 6859 ldr r1, [r3, #4]
|
|
8001d84: 460b mov r3, r1
|
|
8001d86: 005b lsls r3, r3, #1
|
|
8001d88: 440b add r3, r1
|
|
8001d8a: fbb0 f3f3 udiv r3, r0, r3
|
|
8001d8e: 3301 adds r3, #1
|
|
8001d90: f3c3 030b ubfx r3, r3, #0, #12
|
|
8001d94: 2b00 cmp r3, #0
|
|
8001d96: bf0c ite eq
|
|
8001d98: 2301 moveq r3, #1
|
|
8001d9a: 2300 movne r3, #0
|
|
8001d9c: b2db uxtb r3, r3
|
|
8001d9e: e012 b.n 8001dc6 <HAL_I2C_Init+0x18e>
|
|
8001da0: 68fb ldr r3, [r7, #12]
|
|
8001da2: 1e58 subs r0, r3, #1
|
|
8001da4: 687b ldr r3, [r7, #4]
|
|
8001da6: 6859 ldr r1, [r3, #4]
|
|
8001da8: 460b mov r3, r1
|
|
8001daa: 009b lsls r3, r3, #2
|
|
8001dac: 440b add r3, r1
|
|
8001dae: 0099 lsls r1, r3, #2
|
|
8001db0: 440b add r3, r1
|
|
8001db2: fbb0 f3f3 udiv r3, r0, r3
|
|
8001db6: 3301 adds r3, #1
|
|
8001db8: f3c3 030b ubfx r3, r3, #0, #12
|
|
8001dbc: 2b00 cmp r3, #0
|
|
8001dbe: bf0c ite eq
|
|
8001dc0: 2301 moveq r3, #1
|
|
8001dc2: 2300 movne r3, #0
|
|
8001dc4: b2db uxtb r3, r3
|
|
8001dc6: 2b00 cmp r3, #0
|
|
8001dc8: d001 beq.n 8001dce <HAL_I2C_Init+0x196>
|
|
8001dca: 2301 movs r3, #1
|
|
8001dcc: e022 b.n 8001e14 <HAL_I2C_Init+0x1dc>
|
|
8001dce: 687b ldr r3, [r7, #4]
|
|
8001dd0: 689b ldr r3, [r3, #8]
|
|
8001dd2: 2b00 cmp r3, #0
|
|
8001dd4: d10e bne.n 8001df4 <HAL_I2C_Init+0x1bc>
|
|
8001dd6: 68fb ldr r3, [r7, #12]
|
|
8001dd8: 1e58 subs r0, r3, #1
|
|
8001dda: 687b ldr r3, [r7, #4]
|
|
8001ddc: 6859 ldr r1, [r3, #4]
|
|
8001dde: 460b mov r3, r1
|
|
8001de0: 005b lsls r3, r3, #1
|
|
8001de2: 440b add r3, r1
|
|
8001de4: fbb0 f3f3 udiv r3, r0, r3
|
|
8001de8: 3301 adds r3, #1
|
|
8001dea: f3c3 030b ubfx r3, r3, #0, #12
|
|
8001dee: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8001df2: e00f b.n 8001e14 <HAL_I2C_Init+0x1dc>
|
|
8001df4: 68fb ldr r3, [r7, #12]
|
|
8001df6: 1e58 subs r0, r3, #1
|
|
8001df8: 687b ldr r3, [r7, #4]
|
|
8001dfa: 6859 ldr r1, [r3, #4]
|
|
8001dfc: 460b mov r3, r1
|
|
8001dfe: 009b lsls r3, r3, #2
|
|
8001e00: 440b add r3, r1
|
|
8001e02: 0099 lsls r1, r3, #2
|
|
8001e04: 440b add r3, r1
|
|
8001e06: fbb0 f3f3 udiv r3, r0, r3
|
|
8001e0a: 3301 adds r3, #1
|
|
8001e0c: f3c3 030b ubfx r3, r3, #0, #12
|
|
8001e10: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8001e14: 6879 ldr r1, [r7, #4]
|
|
8001e16: 6809 ldr r1, [r1, #0]
|
|
8001e18: 4313 orrs r3, r2
|
|
8001e1a: 61cb str r3, [r1, #28]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
|
|
8001e1c: 687b ldr r3, [r7, #4]
|
|
8001e1e: 681b ldr r3, [r3, #0]
|
|
8001e20: 681b ldr r3, [r3, #0]
|
|
8001e22: f023 01c0 bic.w r1, r3, #192 @ 0xc0
|
|
8001e26: 687b ldr r3, [r7, #4]
|
|
8001e28: 69da ldr r2, [r3, #28]
|
|
8001e2a: 687b ldr r3, [r7, #4]
|
|
8001e2c: 6a1b ldr r3, [r3, #32]
|
|
8001e2e: 431a orrs r2, r3
|
|
8001e30: 687b ldr r3, [r7, #4]
|
|
8001e32: 681b ldr r3, [r3, #0]
|
|
8001e34: 430a orrs r2, r1
|
|
8001e36: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Configure I2Cx: Own Address1 and addressing mode */
|
|
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
|
|
8001e38: 687b ldr r3, [r7, #4]
|
|
8001e3a: 681b ldr r3, [r3, #0]
|
|
8001e3c: 689b ldr r3, [r3, #8]
|
|
8001e3e: f423 4303 bic.w r3, r3, #33536 @ 0x8300
|
|
8001e42: f023 03ff bic.w r3, r3, #255 @ 0xff
|
|
8001e46: 687a ldr r2, [r7, #4]
|
|
8001e48: 6911 ldr r1, [r2, #16]
|
|
8001e4a: 687a ldr r2, [r7, #4]
|
|
8001e4c: 68d2 ldr r2, [r2, #12]
|
|
8001e4e: 4311 orrs r1, r2
|
|
8001e50: 687a ldr r2, [r7, #4]
|
|
8001e52: 6812 ldr r2, [r2, #0]
|
|
8001e54: 430b orrs r3, r1
|
|
8001e56: 6093 str r3, [r2, #8]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
|
|
8001e58: 687b ldr r3, [r7, #4]
|
|
8001e5a: 681b ldr r3, [r3, #0]
|
|
8001e5c: 68db ldr r3, [r3, #12]
|
|
8001e5e: f023 01ff bic.w r1, r3, #255 @ 0xff
|
|
8001e62: 687b ldr r3, [r7, #4]
|
|
8001e64: 695a ldr r2, [r3, #20]
|
|
8001e66: 687b ldr r3, [r7, #4]
|
|
8001e68: 699b ldr r3, [r3, #24]
|
|
8001e6a: 431a orrs r2, r3
|
|
8001e6c: 687b ldr r3, [r7, #4]
|
|
8001e6e: 681b ldr r3, [r3, #0]
|
|
8001e70: 430a orrs r2, r1
|
|
8001e72: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8001e74: 687b ldr r3, [r7, #4]
|
|
8001e76: 681b ldr r3, [r3, #0]
|
|
8001e78: 681a ldr r2, [r3, #0]
|
|
8001e7a: 687b ldr r3, [r7, #4]
|
|
8001e7c: 681b ldr r3, [r3, #0]
|
|
8001e7e: f042 0201 orr.w r2, r2, #1
|
|
8001e82: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8001e84: 687b ldr r3, [r7, #4]
|
|
8001e86: 2200 movs r2, #0
|
|
8001e88: 641a str r2, [r3, #64] @ 0x40
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8001e8a: 687b ldr r3, [r7, #4]
|
|
8001e8c: 2220 movs r2, #32
|
|
8001e8e: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8001e92: 687b ldr r3, [r7, #4]
|
|
8001e94: 2200 movs r2, #0
|
|
8001e96: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8001e98: 687b ldr r3, [r7, #4]
|
|
8001e9a: 2200 movs r2, #0
|
|
8001e9c: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
|
|
return HAL_OK;
|
|
8001ea0: 2300 movs r3, #0
|
|
}
|
|
8001ea2: 4618 mov r0, r3
|
|
8001ea4: 3710 adds r7, #16
|
|
8001ea6: 46bd mov sp, r7
|
|
8001ea8: bd80 pop {r7, pc}
|
|
8001eaa: bf00 nop
|
|
8001eac: 000186a0 .word 0x000186a0
|
|
8001eb0: 001e847f .word 0x001e847f
|
|
8001eb4: 003d08ff .word 0x003d08ff
|
|
8001eb8: 431bde83 .word 0x431bde83
|
|
8001ebc: 10624dd3 .word 0x10624dd3
|
|
|
|
08001ec0 <HAL_PCD_Init>:
|
|
* parameters in the PCD_InitTypeDef and initialize the associated handle.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8001ec0: b580 push {r7, lr}
|
|
8001ec2: b086 sub sp, #24
|
|
8001ec4: af02 add r7, sp, #8
|
|
8001ec6: 6078 str r0, [r7, #4]
|
|
const USB_OTG_GlobalTypeDef *USBx;
|
|
#endif /* defined (USB_OTG_FS) */
|
|
uint8_t i;
|
|
|
|
/* Check the PCD handle allocation */
|
|
if (hpcd == NULL)
|
|
8001ec8: 687b ldr r3, [r7, #4]
|
|
8001eca: 2b00 cmp r3, #0
|
|
8001ecc: d101 bne.n 8001ed2 <HAL_PCD_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001ece: 2301 movs r3, #1
|
|
8001ed0: e108 b.n 80020e4 <HAL_PCD_Init+0x224>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
|
|
|
|
#if defined (USB_OTG_FS)
|
|
USBx = hpcd->Instance;
|
|
8001ed2: 687b ldr r3, [r7, #4]
|
|
8001ed4: 681b ldr r3, [r3, #0]
|
|
8001ed6: 60bb str r3, [r7, #8]
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
if (hpcd->State == HAL_PCD_STATE_RESET)
|
|
8001ed8: 687b ldr r3, [r7, #4]
|
|
8001eda: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495
|
|
8001ede: b2db uxtb r3, r3
|
|
8001ee0: 2b00 cmp r3, #0
|
|
8001ee2: d106 bne.n 8001ef2 <HAL_PCD_Init+0x32>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hpcd->Lock = HAL_UNLOCKED;
|
|
8001ee4: 687b ldr r3, [r7, #4]
|
|
8001ee6: 2200 movs r2, #0
|
|
8001ee8: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
/* Init the low level hardware */
|
|
hpcd->MspInitCallback(hpcd);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_PCD_MspInit(hpcd);
|
|
8001eec: 6878 ldr r0, [r7, #4]
|
|
8001eee: f006 ffed bl 8008ecc <HAL_PCD_MspInit>
|
|
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
hpcd->State = HAL_PCD_STATE_BUSY;
|
|
8001ef2: 687b ldr r3, [r7, #4]
|
|
8001ef4: 2203 movs r2, #3
|
|
8001ef6: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
|
|
#if defined (USB_OTG_FS)
|
|
/* Disable DMA mode for FS instance */
|
|
if (USBx == USB_OTG_FS)
|
|
8001efa: 68bb ldr r3, [r7, #8]
|
|
8001efc: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8001f00: d102 bne.n 8001f08 <HAL_PCD_Init+0x48>
|
|
{
|
|
hpcd->Init.dma_enable = 0U;
|
|
8001f02: 687b ldr r3, [r7, #4]
|
|
8001f04: 2200 movs r2, #0
|
|
8001f06: 719a strb r2, [r3, #6]
|
|
}
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
/* Disable the Interrupts */
|
|
__HAL_PCD_DISABLE(hpcd);
|
|
8001f08: 687b ldr r3, [r7, #4]
|
|
8001f0a: 681b ldr r3, [r3, #0]
|
|
8001f0c: 4618 mov r0, r3
|
|
8001f0e: f003 fece bl 8005cae <USB_DisableGlobalInt>
|
|
|
|
/*Init the Core (common init.) */
|
|
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8001f12: 687b ldr r3, [r7, #4]
|
|
8001f14: 6818 ldr r0, [r3, #0]
|
|
8001f16: 687b ldr r3, [r7, #4]
|
|
8001f18: 7c1a ldrb r2, [r3, #16]
|
|
8001f1a: f88d 2000 strb.w r2, [sp]
|
|
8001f1e: 3304 adds r3, #4
|
|
8001f20: cb0e ldmia r3, {r1, r2, r3}
|
|
8001f22: f003 fdad bl 8005a80 <USB_CoreInit>
|
|
8001f26: 4603 mov r3, r0
|
|
8001f28: 2b00 cmp r3, #0
|
|
8001f2a: d005 beq.n 8001f38 <HAL_PCD_Init+0x78>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8001f2c: 687b ldr r3, [r7, #4]
|
|
8001f2e: 2202 movs r2, #2
|
|
8001f30: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8001f34: 2301 movs r3, #1
|
|
8001f36: e0d5 b.n 80020e4 <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
/* Force Device Mode */
|
|
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
|
|
8001f38: 687b ldr r3, [r7, #4]
|
|
8001f3a: 681b ldr r3, [r3, #0]
|
|
8001f3c: 2100 movs r1, #0
|
|
8001f3e: 4618 mov r0, r3
|
|
8001f40: f003 fec6 bl 8005cd0 <USB_SetCurrentMode>
|
|
8001f44: 4603 mov r3, r0
|
|
8001f46: 2b00 cmp r3, #0
|
|
8001f48: d005 beq.n 8001f56 <HAL_PCD_Init+0x96>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8001f4a: 687b ldr r3, [r7, #4]
|
|
8001f4c: 2202 movs r2, #2
|
|
8001f4e: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8001f52: 2301 movs r3, #1
|
|
8001f54: e0c6 b.n 80020e4 <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
/* Init endpoints structures */
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001f56: 2300 movs r3, #0
|
|
8001f58: 73fb strb r3, [r7, #15]
|
|
8001f5a: e04a b.n 8001ff2 <HAL_PCD_Init+0x132>
|
|
{
|
|
/* Init ep structure */
|
|
hpcd->IN_ep[i].is_in = 1U;
|
|
8001f5c: 7bfa ldrb r2, [r7, #15]
|
|
8001f5e: 6879 ldr r1, [r7, #4]
|
|
8001f60: 4613 mov r3, r2
|
|
8001f62: 00db lsls r3, r3, #3
|
|
8001f64: 4413 add r3, r2
|
|
8001f66: 009b lsls r3, r3, #2
|
|
8001f68: 440b add r3, r1
|
|
8001f6a: 3315 adds r3, #21
|
|
8001f6c: 2201 movs r2, #1
|
|
8001f6e: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].num = i;
|
|
8001f70: 7bfa ldrb r2, [r7, #15]
|
|
8001f72: 6879 ldr r1, [r7, #4]
|
|
8001f74: 4613 mov r3, r2
|
|
8001f76: 00db lsls r3, r3, #3
|
|
8001f78: 4413 add r3, r2
|
|
8001f7a: 009b lsls r3, r3, #2
|
|
8001f7c: 440b add r3, r1
|
|
8001f7e: 3314 adds r3, #20
|
|
8001f80: 7bfa ldrb r2, [r7, #15]
|
|
8001f82: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].tx_fifo_num = i;
|
|
8001f84: 7bfa ldrb r2, [r7, #15]
|
|
8001f86: 7bfb ldrb r3, [r7, #15]
|
|
8001f88: b298 uxth r0, r3
|
|
8001f8a: 6879 ldr r1, [r7, #4]
|
|
8001f8c: 4613 mov r3, r2
|
|
8001f8e: 00db lsls r3, r3, #3
|
|
8001f90: 4413 add r3, r2
|
|
8001f92: 009b lsls r3, r3, #2
|
|
8001f94: 440b add r3, r1
|
|
8001f96: 332e adds r3, #46 @ 0x2e
|
|
8001f98: 4602 mov r2, r0
|
|
8001f9a: 801a strh r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
|
|
8001f9c: 7bfa ldrb r2, [r7, #15]
|
|
8001f9e: 6879 ldr r1, [r7, #4]
|
|
8001fa0: 4613 mov r3, r2
|
|
8001fa2: 00db lsls r3, r3, #3
|
|
8001fa4: 4413 add r3, r2
|
|
8001fa6: 009b lsls r3, r3, #2
|
|
8001fa8: 440b add r3, r1
|
|
8001faa: 3318 adds r3, #24
|
|
8001fac: 2200 movs r2, #0
|
|
8001fae: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].maxpacket = 0U;
|
|
8001fb0: 7bfa ldrb r2, [r7, #15]
|
|
8001fb2: 6879 ldr r1, [r7, #4]
|
|
8001fb4: 4613 mov r3, r2
|
|
8001fb6: 00db lsls r3, r3, #3
|
|
8001fb8: 4413 add r3, r2
|
|
8001fba: 009b lsls r3, r3, #2
|
|
8001fbc: 440b add r3, r1
|
|
8001fbe: 331c adds r3, #28
|
|
8001fc0: 2200 movs r2, #0
|
|
8001fc2: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_buff = 0U;
|
|
8001fc4: 7bfa ldrb r2, [r7, #15]
|
|
8001fc6: 6879 ldr r1, [r7, #4]
|
|
8001fc8: 4613 mov r3, r2
|
|
8001fca: 00db lsls r3, r3, #3
|
|
8001fcc: 4413 add r3, r2
|
|
8001fce: 009b lsls r3, r3, #2
|
|
8001fd0: 440b add r3, r1
|
|
8001fd2: 3320 adds r3, #32
|
|
8001fd4: 2200 movs r2, #0
|
|
8001fd6: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_len = 0U;
|
|
8001fd8: 7bfa ldrb r2, [r7, #15]
|
|
8001fda: 6879 ldr r1, [r7, #4]
|
|
8001fdc: 4613 mov r3, r2
|
|
8001fde: 00db lsls r3, r3, #3
|
|
8001fe0: 4413 add r3, r2
|
|
8001fe2: 009b lsls r3, r3, #2
|
|
8001fe4: 440b add r3, r1
|
|
8001fe6: 3324 adds r3, #36 @ 0x24
|
|
8001fe8: 2200 movs r2, #0
|
|
8001fea: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001fec: 7bfb ldrb r3, [r7, #15]
|
|
8001fee: 3301 adds r3, #1
|
|
8001ff0: 73fb strb r3, [r7, #15]
|
|
8001ff2: 687b ldr r3, [r7, #4]
|
|
8001ff4: 791b ldrb r3, [r3, #4]
|
|
8001ff6: 7bfa ldrb r2, [r7, #15]
|
|
8001ff8: 429a cmp r2, r3
|
|
8001ffa: d3af bcc.n 8001f5c <HAL_PCD_Init+0x9c>
|
|
}
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001ffc: 2300 movs r3, #0
|
|
8001ffe: 73fb strb r3, [r7, #15]
|
|
8002000: e044 b.n 800208c <HAL_PCD_Init+0x1cc>
|
|
{
|
|
hpcd->OUT_ep[i].is_in = 0U;
|
|
8002002: 7bfa ldrb r2, [r7, #15]
|
|
8002004: 6879 ldr r1, [r7, #4]
|
|
8002006: 4613 mov r3, r2
|
|
8002008: 00db lsls r3, r3, #3
|
|
800200a: 4413 add r3, r2
|
|
800200c: 009b lsls r3, r3, #2
|
|
800200e: 440b add r3, r1
|
|
8002010: f203 2355 addw r3, r3, #597 @ 0x255
|
|
8002014: 2200 movs r2, #0
|
|
8002016: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].num = i;
|
|
8002018: 7bfa ldrb r2, [r7, #15]
|
|
800201a: 6879 ldr r1, [r7, #4]
|
|
800201c: 4613 mov r3, r2
|
|
800201e: 00db lsls r3, r3, #3
|
|
8002020: 4413 add r3, r2
|
|
8002022: 009b lsls r3, r3, #2
|
|
8002024: 440b add r3, r1
|
|
8002026: f503 7315 add.w r3, r3, #596 @ 0x254
|
|
800202a: 7bfa ldrb r2, [r7, #15]
|
|
800202c: 701a strb r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
|
|
800202e: 7bfa ldrb r2, [r7, #15]
|
|
8002030: 6879 ldr r1, [r7, #4]
|
|
8002032: 4613 mov r3, r2
|
|
8002034: 00db lsls r3, r3, #3
|
|
8002036: 4413 add r3, r2
|
|
8002038: 009b lsls r3, r3, #2
|
|
800203a: 440b add r3, r1
|
|
800203c: f503 7316 add.w r3, r3, #600 @ 0x258
|
|
8002040: 2200 movs r2, #0
|
|
8002042: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].maxpacket = 0U;
|
|
8002044: 7bfa ldrb r2, [r7, #15]
|
|
8002046: 6879 ldr r1, [r7, #4]
|
|
8002048: 4613 mov r3, r2
|
|
800204a: 00db lsls r3, r3, #3
|
|
800204c: 4413 add r3, r2
|
|
800204e: 009b lsls r3, r3, #2
|
|
8002050: 440b add r3, r1
|
|
8002052: f503 7317 add.w r3, r3, #604 @ 0x25c
|
|
8002056: 2200 movs r2, #0
|
|
8002058: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_buff = 0U;
|
|
800205a: 7bfa ldrb r2, [r7, #15]
|
|
800205c: 6879 ldr r1, [r7, #4]
|
|
800205e: 4613 mov r3, r2
|
|
8002060: 00db lsls r3, r3, #3
|
|
8002062: 4413 add r3, r2
|
|
8002064: 009b lsls r3, r3, #2
|
|
8002066: 440b add r3, r1
|
|
8002068: f503 7318 add.w r3, r3, #608 @ 0x260
|
|
800206c: 2200 movs r2, #0
|
|
800206e: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_len = 0U;
|
|
8002070: 7bfa ldrb r2, [r7, #15]
|
|
8002072: 6879 ldr r1, [r7, #4]
|
|
8002074: 4613 mov r3, r2
|
|
8002076: 00db lsls r3, r3, #3
|
|
8002078: 4413 add r3, r2
|
|
800207a: 009b lsls r3, r3, #2
|
|
800207c: 440b add r3, r1
|
|
800207e: f503 7319 add.w r3, r3, #612 @ 0x264
|
|
8002082: 2200 movs r2, #0
|
|
8002084: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8002086: 7bfb ldrb r3, [r7, #15]
|
|
8002088: 3301 adds r3, #1
|
|
800208a: 73fb strb r3, [r7, #15]
|
|
800208c: 687b ldr r3, [r7, #4]
|
|
800208e: 791b ldrb r3, [r3, #4]
|
|
8002090: 7bfa ldrb r2, [r7, #15]
|
|
8002092: 429a cmp r2, r3
|
|
8002094: d3b5 bcc.n 8002002 <HAL_PCD_Init+0x142>
|
|
}
|
|
|
|
/* Init Device */
|
|
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8002096: 687b ldr r3, [r7, #4]
|
|
8002098: 6818 ldr r0, [r3, #0]
|
|
800209a: 687b ldr r3, [r7, #4]
|
|
800209c: 7c1a ldrb r2, [r3, #16]
|
|
800209e: f88d 2000 strb.w r2, [sp]
|
|
80020a2: 3304 adds r3, #4
|
|
80020a4: cb0e ldmia r3, {r1, r2, r3}
|
|
80020a6: f003 fe5f bl 8005d68 <USB_DevInit>
|
|
80020aa: 4603 mov r3, r0
|
|
80020ac: 2b00 cmp r3, #0
|
|
80020ae: d005 beq.n 80020bc <HAL_PCD_Init+0x1fc>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
80020b0: 687b ldr r3, [r7, #4]
|
|
80020b2: 2202 movs r2, #2
|
|
80020b4: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
80020b8: 2301 movs r3, #1
|
|
80020ba: e013 b.n 80020e4 <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
hpcd->USB_Address = 0U;
|
|
80020bc: 687b ldr r3, [r7, #4]
|
|
80020be: 2200 movs r2, #0
|
|
80020c0: 745a strb r2, [r3, #17]
|
|
hpcd->State = HAL_PCD_STATE_READY;
|
|
80020c2: 687b ldr r3, [r7, #4]
|
|
80020c4: 2201 movs r2, #1
|
|
80020c6: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* Activate LPM */
|
|
if (hpcd->Init.lpm_enable == 1U)
|
|
80020ca: 687b ldr r3, [r7, #4]
|
|
80020cc: 7b1b ldrb r3, [r3, #12]
|
|
80020ce: 2b01 cmp r3, #1
|
|
80020d0: d102 bne.n 80020d8 <HAL_PCD_Init+0x218>
|
|
{
|
|
(void)HAL_PCDEx_ActivateLPM(hpcd);
|
|
80020d2: 6878 ldr r0, [r7, #4]
|
|
80020d4: f001 f956 bl 8003384 <HAL_PCDEx_ActivateLPM>
|
|
}
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
(void)USB_DevDisconnect(hpcd->Instance);
|
|
80020d8: 687b ldr r3, [r7, #4]
|
|
80020da: 681b ldr r3, [r3, #0]
|
|
80020dc: 4618 mov r0, r3
|
|
80020de: f004 fe9c bl 8006e1a <USB_DevDisconnect>
|
|
|
|
return HAL_OK;
|
|
80020e2: 2300 movs r3, #0
|
|
}
|
|
80020e4: 4618 mov r0, r3
|
|
80020e6: 3710 adds r7, #16
|
|
80020e8: 46bd mov sp, r7
|
|
80020ea: bd80 pop {r7, pc}
|
|
|
|
080020ec <HAL_PCD_Start>:
|
|
* @brief Start the USB device
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
80020ec: b580 push {r7, lr}
|
|
80020ee: b084 sub sp, #16
|
|
80020f0: af00 add r7, sp, #0
|
|
80020f2: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
80020f4: 687b ldr r3, [r7, #4]
|
|
80020f6: 681b ldr r3, [r3, #0]
|
|
80020f8: 60fb str r3, [r7, #12]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
80020fa: 687b ldr r3, [r7, #4]
|
|
80020fc: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002100: 2b01 cmp r3, #1
|
|
8002102: d101 bne.n 8002108 <HAL_PCD_Start+0x1c>
|
|
8002104: 2302 movs r3, #2
|
|
8002106: e022 b.n 800214e <HAL_PCD_Start+0x62>
|
|
8002108: 687b ldr r3, [r7, #4]
|
|
800210a: 2201 movs r2, #1
|
|
800210c: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
|
|
8002110: 68fb ldr r3, [r7, #12]
|
|
8002112: 68db ldr r3, [r3, #12]
|
|
8002114: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8002118: 2b00 cmp r3, #0
|
|
800211a: d009 beq.n 8002130 <HAL_PCD_Start+0x44>
|
|
(hpcd->Init.battery_charging_enable == 1U))
|
|
800211c: 687b ldr r3, [r7, #4]
|
|
800211e: 7b5b ldrb r3, [r3, #13]
|
|
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
|
|
8002120: 2b01 cmp r3, #1
|
|
8002122: d105 bne.n 8002130 <HAL_PCD_Start+0x44>
|
|
{
|
|
/* Enable USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
8002124: 68fb ldr r3, [r7, #12]
|
|
8002126: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8002128: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
800212c: 68fb ldr r3, [r7, #12]
|
|
800212e: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
|
|
__HAL_PCD_ENABLE(hpcd);
|
|
8002130: 687b ldr r3, [r7, #4]
|
|
8002132: 681b ldr r3, [r3, #0]
|
|
8002134: 4618 mov r0, r3
|
|
8002136: f003 fda9 bl 8005c8c <USB_EnableGlobalInt>
|
|
(void)USB_DevConnect(hpcd->Instance);
|
|
800213a: 687b ldr r3, [r7, #4]
|
|
800213c: 681b ldr r3, [r3, #0]
|
|
800213e: 4618 mov r0, r3
|
|
8002140: f004 fe4a bl 8006dd8 <USB_DevConnect>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002144: 687b ldr r3, [r7, #4]
|
|
8002146: 2200 movs r2, #0
|
|
8002148: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
800214c: 2300 movs r3, #0
|
|
}
|
|
800214e: 4618 mov r0, r3
|
|
8002150: 3710 adds r7, #16
|
|
8002152: 46bd mov sp, r7
|
|
8002154: bd80 pop {r7, pc}
|
|
|
|
08002156 <HAL_PCD_IRQHandler>:
|
|
* @brief Handles PCD interrupt request.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8002156: b590 push {r4, r7, lr}
|
|
8002158: b08d sub sp, #52 @ 0x34
|
|
800215a: af00 add r7, sp, #0
|
|
800215c: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
800215e: 687b ldr r3, [r7, #4]
|
|
8002160: 681b ldr r3, [r3, #0]
|
|
8002162: 623b str r3, [r7, #32]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8002164: 6a3b ldr r3, [r7, #32]
|
|
8002166: 61fb str r3, [r7, #28]
|
|
uint32_t epnum;
|
|
uint32_t fifoemptymsk;
|
|
uint32_t RegVal;
|
|
|
|
/* ensure that we are in device mode */
|
|
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
|
|
8002168: 687b ldr r3, [r7, #4]
|
|
800216a: 681b ldr r3, [r3, #0]
|
|
800216c: 4618 mov r0, r3
|
|
800216e: f004 ff08 bl 8006f82 <USB_GetMode>
|
|
8002172: 4603 mov r3, r0
|
|
8002174: 2b00 cmp r3, #0
|
|
8002176: f040 84b9 bne.w 8002aec <HAL_PCD_IRQHandler+0x996>
|
|
{
|
|
/* avoid spurious interrupt */
|
|
if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
|
|
800217a: 687b ldr r3, [r7, #4]
|
|
800217c: 681b ldr r3, [r3, #0]
|
|
800217e: 4618 mov r0, r3
|
|
8002180: f004 fe6c bl 8006e5c <USB_ReadInterrupts>
|
|
8002184: 4603 mov r3, r0
|
|
8002186: 2b00 cmp r3, #0
|
|
8002188: f000 84af beq.w 8002aea <HAL_PCD_IRQHandler+0x994>
|
|
{
|
|
return;
|
|
}
|
|
|
|
/* store current frame number */
|
|
hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos;
|
|
800218c: 69fb ldr r3, [r7, #28]
|
|
800218e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002192: 689b ldr r3, [r3, #8]
|
|
8002194: 0a1b lsrs r3, r3, #8
|
|
8002196: f3c3 020d ubfx r2, r3, #0, #14
|
|
800219a: 687b ldr r3, [r7, #4]
|
|
800219c: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
|
|
80021a0: 687b ldr r3, [r7, #4]
|
|
80021a2: 681b ldr r3, [r3, #0]
|
|
80021a4: 4618 mov r0, r3
|
|
80021a6: f004 fe59 bl 8006e5c <USB_ReadInterrupts>
|
|
80021aa: 4603 mov r3, r0
|
|
80021ac: f003 0302 and.w r3, r3, #2
|
|
80021b0: 2b02 cmp r3, #2
|
|
80021b2: d107 bne.n 80021c4 <HAL_PCD_IRQHandler+0x6e>
|
|
{
|
|
/* incorrect mode, acknowledge the interrupt */
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
|
|
80021b4: 687b ldr r3, [r7, #4]
|
|
80021b6: 681b ldr r3, [r3, #0]
|
|
80021b8: 695a ldr r2, [r3, #20]
|
|
80021ba: 687b ldr r3, [r7, #4]
|
|
80021bc: 681b ldr r3, [r3, #0]
|
|
80021be: f002 0202 and.w r2, r2, #2
|
|
80021c2: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle RxQLevel Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
|
|
80021c4: 687b ldr r3, [r7, #4]
|
|
80021c6: 681b ldr r3, [r3, #0]
|
|
80021c8: 4618 mov r0, r3
|
|
80021ca: f004 fe47 bl 8006e5c <USB_ReadInterrupts>
|
|
80021ce: 4603 mov r3, r0
|
|
80021d0: f003 0310 and.w r3, r3, #16
|
|
80021d4: 2b10 cmp r3, #16
|
|
80021d6: d161 bne.n 800229c <HAL_PCD_IRQHandler+0x146>
|
|
{
|
|
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
80021d8: 687b ldr r3, [r7, #4]
|
|
80021da: 681b ldr r3, [r3, #0]
|
|
80021dc: 699a ldr r2, [r3, #24]
|
|
80021de: 687b ldr r3, [r7, #4]
|
|
80021e0: 681b ldr r3, [r3, #0]
|
|
80021e2: f022 0210 bic.w r2, r2, #16
|
|
80021e6: 619a str r2, [r3, #24]
|
|
|
|
RegVal = USBx->GRXSTSP;
|
|
80021e8: 6a3b ldr r3, [r7, #32]
|
|
80021ea: 6a1b ldr r3, [r3, #32]
|
|
80021ec: 61bb str r3, [r7, #24]
|
|
|
|
ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM];
|
|
80021ee: 69bb ldr r3, [r7, #24]
|
|
80021f0: f003 020f and.w r2, r3, #15
|
|
80021f4: 4613 mov r3, r2
|
|
80021f6: 00db lsls r3, r3, #3
|
|
80021f8: 4413 add r3, r2
|
|
80021fa: 009b lsls r3, r3, #2
|
|
80021fc: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002200: 687a ldr r2, [r7, #4]
|
|
8002202: 4413 add r3, r2
|
|
8002204: 3304 adds r3, #4
|
|
8002206: 617b str r3, [r7, #20]
|
|
|
|
if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
|
|
8002208: 69bb ldr r3, [r7, #24]
|
|
800220a: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
|
|
800220e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
8002212: d124 bne.n 800225e <HAL_PCD_IRQHandler+0x108>
|
|
{
|
|
if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U)
|
|
8002214: 69ba ldr r2, [r7, #24]
|
|
8002216: f647 73f0 movw r3, #32752 @ 0x7ff0
|
|
800221a: 4013 ands r3, r2
|
|
800221c: 2b00 cmp r3, #0
|
|
800221e: d035 beq.n 800228c <HAL_PCD_IRQHandler+0x136>
|
|
{
|
|
(void)USB_ReadPacket(USBx, ep->xfer_buff,
|
|
8002220: 697b ldr r3, [r7, #20]
|
|
8002222: 68d9 ldr r1, [r3, #12]
|
|
(uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4));
|
|
8002224: 69bb ldr r3, [r7, #24]
|
|
8002226: 091b lsrs r3, r3, #4
|
|
8002228: b29b uxth r3, r3
|
|
(void)USB_ReadPacket(USBx, ep->xfer_buff,
|
|
800222a: f3c3 030a ubfx r3, r3, #0, #11
|
|
800222e: b29b uxth r3, r3
|
|
8002230: 461a mov r2, r3
|
|
8002232: 6a38 ldr r0, [r7, #32]
|
|
8002234: f004 fc7e bl 8006b34 <USB_ReadPacket>
|
|
|
|
ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8002238: 697b ldr r3, [r7, #20]
|
|
800223a: 68da ldr r2, [r3, #12]
|
|
800223c: 69bb ldr r3, [r7, #24]
|
|
800223e: 091b lsrs r3, r3, #4
|
|
8002240: f3c3 030a ubfx r3, r3, #0, #11
|
|
8002244: 441a add r2, r3
|
|
8002246: 697b ldr r3, [r7, #20]
|
|
8002248: 60da str r2, [r3, #12]
|
|
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
800224a: 697b ldr r3, [r7, #20]
|
|
800224c: 695a ldr r2, [r3, #20]
|
|
800224e: 69bb ldr r3, [r7, #24]
|
|
8002250: 091b lsrs r3, r3, #4
|
|
8002252: f3c3 030a ubfx r3, r3, #0, #11
|
|
8002256: 441a add r2, r3
|
|
8002258: 697b ldr r3, [r7, #20]
|
|
800225a: 615a str r2, [r3, #20]
|
|
800225c: e016 b.n 800228c <HAL_PCD_IRQHandler+0x136>
|
|
}
|
|
}
|
|
else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
|
|
800225e: 69bb ldr r3, [r7, #24]
|
|
8002260: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
|
|
8002264: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000
|
|
8002268: d110 bne.n 800228c <HAL_PCD_IRQHandler+0x136>
|
|
{
|
|
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
|
|
800226a: 687b ldr r3, [r7, #4]
|
|
800226c: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8002270: 2208 movs r2, #8
|
|
8002272: 4619 mov r1, r3
|
|
8002274: 6a38 ldr r0, [r7, #32]
|
|
8002276: f004 fc5d bl 8006b34 <USB_ReadPacket>
|
|
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
800227a: 697b ldr r3, [r7, #20]
|
|
800227c: 695a ldr r2, [r3, #20]
|
|
800227e: 69bb ldr r3, [r7, #24]
|
|
8002280: 091b lsrs r3, r3, #4
|
|
8002282: f3c3 030a ubfx r3, r3, #0, #11
|
|
8002286: 441a add r2, r3
|
|
8002288: 697b ldr r3, [r7, #20]
|
|
800228a: 615a str r2, [r3, #20]
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
|
|
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
800228c: 687b ldr r3, [r7, #4]
|
|
800228e: 681b ldr r3, [r3, #0]
|
|
8002290: 699a ldr r2, [r3, #24]
|
|
8002292: 687b ldr r3, [r7, #4]
|
|
8002294: 681b ldr r3, [r3, #0]
|
|
8002296: f042 0210 orr.w r2, r2, #16
|
|
800229a: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
|
|
800229c: 687b ldr r3, [r7, #4]
|
|
800229e: 681b ldr r3, [r3, #0]
|
|
80022a0: 4618 mov r0, r3
|
|
80022a2: f004 fddb bl 8006e5c <USB_ReadInterrupts>
|
|
80022a6: 4603 mov r3, r0
|
|
80022a8: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
80022ac: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
|
|
80022b0: f040 80a7 bne.w 8002402 <HAL_PCD_IRQHandler+0x2ac>
|
|
{
|
|
epnum = 0U;
|
|
80022b4: 2300 movs r3, #0
|
|
80022b6: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Read in the device interrupt bits */
|
|
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
|
|
80022b8: 687b ldr r3, [r7, #4]
|
|
80022ba: 681b ldr r3, [r3, #0]
|
|
80022bc: 4618 mov r0, r3
|
|
80022be: f004 fde0 bl 8006e82 <USB_ReadDevAllOutEpInterrupt>
|
|
80022c2: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
while (ep_intr != 0U)
|
|
80022c4: e099 b.n 80023fa <HAL_PCD_IRQHandler+0x2a4>
|
|
{
|
|
if ((ep_intr & 0x1U) != 0U)
|
|
80022c6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80022c8: f003 0301 and.w r3, r3, #1
|
|
80022cc: 2b00 cmp r3, #0
|
|
80022ce: f000 808e beq.w 80023ee <HAL_PCD_IRQHandler+0x298>
|
|
{
|
|
epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
|
|
80022d2: 687b ldr r3, [r7, #4]
|
|
80022d4: 681b ldr r3, [r3, #0]
|
|
80022d6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80022d8: b2d2 uxtb r2, r2
|
|
80022da: 4611 mov r1, r2
|
|
80022dc: 4618 mov r0, r3
|
|
80022de: f004 fe04 bl 8006eea <USB_ReadDevOutEPInterrupt>
|
|
80022e2: 6138 str r0, [r7, #16]
|
|
|
|
if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
|
|
80022e4: 693b ldr r3, [r7, #16]
|
|
80022e6: f003 0301 and.w r3, r3, #1
|
|
80022ea: 2b00 cmp r3, #0
|
|
80022ec: d00c beq.n 8002308 <HAL_PCD_IRQHandler+0x1b2>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
|
|
80022ee: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80022f0: 015a lsls r2, r3, #5
|
|
80022f2: 69fb ldr r3, [r7, #28]
|
|
80022f4: 4413 add r3, r2
|
|
80022f6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80022fa: 461a mov r2, r3
|
|
80022fc: 2301 movs r3, #1
|
|
80022fe: 6093 str r3, [r2, #8]
|
|
(void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
|
|
8002300: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8002302: 6878 ldr r0, [r7, #4]
|
|
8002304: f000 feb8 bl 8003078 <PCD_EP_OutXfrComplete_int>
|
|
}
|
|
|
|
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
|
|
8002308: 693b ldr r3, [r7, #16]
|
|
800230a: f003 0308 and.w r3, r3, #8
|
|
800230e: 2b00 cmp r3, #0
|
|
8002310: d00c beq.n 800232c <HAL_PCD_IRQHandler+0x1d6>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
|
|
8002312: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002314: 015a lsls r2, r3, #5
|
|
8002316: 69fb ldr r3, [r7, #28]
|
|
8002318: 4413 add r3, r2
|
|
800231a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800231e: 461a mov r2, r3
|
|
8002320: 2308 movs r3, #8
|
|
8002322: 6093 str r3, [r2, #8]
|
|
/* Class B setup phase done for previous decoded setup */
|
|
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
|
|
8002324: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8002326: 6878 ldr r0, [r7, #4]
|
|
8002328: f000 ff8e bl 8003248 <PCD_EP_OutSetupPacket_int>
|
|
}
|
|
|
|
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
|
|
800232c: 693b ldr r3, [r7, #16]
|
|
800232e: f003 0310 and.w r3, r3, #16
|
|
8002332: 2b00 cmp r3, #0
|
|
8002334: d008 beq.n 8002348 <HAL_PCD_IRQHandler+0x1f2>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
|
|
8002336: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002338: 015a lsls r2, r3, #5
|
|
800233a: 69fb ldr r3, [r7, #28]
|
|
800233c: 4413 add r3, r2
|
|
800233e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002342: 461a mov r2, r3
|
|
8002344: 2310 movs r3, #16
|
|
8002346: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear OUT Endpoint disable interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
|
|
8002348: 693b ldr r3, [r7, #16]
|
|
800234a: f003 0302 and.w r3, r3, #2
|
|
800234e: 2b00 cmp r3, #0
|
|
8002350: d030 beq.n 80023b4 <HAL_PCD_IRQHandler+0x25e>
|
|
{
|
|
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF)
|
|
8002352: 6a3b ldr r3, [r7, #32]
|
|
8002354: 695b ldr r3, [r3, #20]
|
|
8002356: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800235a: 2b80 cmp r3, #128 @ 0x80
|
|
800235c: d109 bne.n 8002372 <HAL_PCD_IRQHandler+0x21c>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
|
|
800235e: 69fb ldr r3, [r7, #28]
|
|
8002360: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002364: 685b ldr r3, [r3, #4]
|
|
8002366: 69fa ldr r2, [r7, #28]
|
|
8002368: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
800236c: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8002370: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
ep = &hpcd->OUT_ep[epnum];
|
|
8002372: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002374: 4613 mov r3, r2
|
|
8002376: 00db lsls r3, r3, #3
|
|
8002378: 4413 add r3, r2
|
|
800237a: 009b lsls r3, r3, #2
|
|
800237c: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002380: 687a ldr r2, [r7, #4]
|
|
8002382: 4413 add r3, r2
|
|
8002384: 3304 adds r3, #4
|
|
8002386: 617b str r3, [r7, #20]
|
|
|
|
if (ep->is_iso_incomplete == 1U)
|
|
8002388: 697b ldr r3, [r7, #20]
|
|
800238a: 78db ldrb r3, [r3, #3]
|
|
800238c: 2b01 cmp r3, #1
|
|
800238e: d108 bne.n 80023a2 <HAL_PCD_IRQHandler+0x24c>
|
|
{
|
|
ep->is_iso_incomplete = 0U;
|
|
8002390: 697b ldr r3, [r7, #20]
|
|
8002392: 2200 movs r2, #0
|
|
8002394: 70da strb r2, [r3, #3]
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
8002396: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002398: b2db uxtb r3, r3
|
|
800239a: 4619 mov r1, r3
|
|
800239c: 6878 ldr r0, [r7, #4]
|
|
800239e: f006 feb1 bl 8009104 <HAL_PCD_ISOOUTIncompleteCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
|
|
80023a2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80023a4: 015a lsls r2, r3, #5
|
|
80023a6: 69fb ldr r3, [r7, #28]
|
|
80023a8: 4413 add r3, r2
|
|
80023aa: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80023ae: 461a mov r2, r3
|
|
80023b0: 2302 movs r3, #2
|
|
80023b2: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear Status Phase Received interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
|
|
80023b4: 693b ldr r3, [r7, #16]
|
|
80023b6: f003 0320 and.w r3, r3, #32
|
|
80023ba: 2b00 cmp r3, #0
|
|
80023bc: d008 beq.n 80023d0 <HAL_PCD_IRQHandler+0x27a>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
80023be: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80023c0: 015a lsls r2, r3, #5
|
|
80023c2: 69fb ldr r3, [r7, #28]
|
|
80023c4: 4413 add r3, r2
|
|
80023c6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80023ca: 461a mov r2, r3
|
|
80023cc: 2320 movs r3, #32
|
|
80023ce: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear OUT NAK interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
|
|
80023d0: 693b ldr r3, [r7, #16]
|
|
80023d2: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
80023d6: 2b00 cmp r3, #0
|
|
80023d8: d009 beq.n 80023ee <HAL_PCD_IRQHandler+0x298>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
|
|
80023da: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80023dc: 015a lsls r2, r3, #5
|
|
80023de: 69fb ldr r3, [r7, #28]
|
|
80023e0: 4413 add r3, r2
|
|
80023e2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80023e6: 461a mov r2, r3
|
|
80023e8: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
80023ec: 6093 str r3, [r2, #8]
|
|
}
|
|
}
|
|
epnum++;
|
|
80023ee: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80023f0: 3301 adds r3, #1
|
|
80023f2: 627b str r3, [r7, #36] @ 0x24
|
|
ep_intr >>= 1U;
|
|
80023f4: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80023f6: 085b lsrs r3, r3, #1
|
|
80023f8: 62bb str r3, [r7, #40] @ 0x28
|
|
while (ep_intr != 0U)
|
|
80023fa: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80023fc: 2b00 cmp r3, #0
|
|
80023fe: f47f af62 bne.w 80022c6 <HAL_PCD_IRQHandler+0x170>
|
|
}
|
|
}
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
|
|
8002402: 687b ldr r3, [r7, #4]
|
|
8002404: 681b ldr r3, [r3, #0]
|
|
8002406: 4618 mov r0, r3
|
|
8002408: f004 fd28 bl 8006e5c <USB_ReadInterrupts>
|
|
800240c: 4603 mov r3, r0
|
|
800240e: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8002412: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
8002416: f040 80db bne.w 80025d0 <HAL_PCD_IRQHandler+0x47a>
|
|
{
|
|
/* Read in the device interrupt bits */
|
|
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
|
|
800241a: 687b ldr r3, [r7, #4]
|
|
800241c: 681b ldr r3, [r3, #0]
|
|
800241e: 4618 mov r0, r3
|
|
8002420: f004 fd49 bl 8006eb6 <USB_ReadDevAllInEpInterrupt>
|
|
8002424: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
epnum = 0U;
|
|
8002426: 2300 movs r3, #0
|
|
8002428: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
while (ep_intr != 0U)
|
|
800242a: e0cd b.n 80025c8 <HAL_PCD_IRQHandler+0x472>
|
|
{
|
|
if ((ep_intr & 0x1U) != 0U) /* In ITR */
|
|
800242c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800242e: f003 0301 and.w r3, r3, #1
|
|
8002432: 2b00 cmp r3, #0
|
|
8002434: f000 80c2 beq.w 80025bc <HAL_PCD_IRQHandler+0x466>
|
|
{
|
|
epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
|
|
8002438: 687b ldr r3, [r7, #4]
|
|
800243a: 681b ldr r3, [r3, #0]
|
|
800243c: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800243e: b2d2 uxtb r2, r2
|
|
8002440: 4611 mov r1, r2
|
|
8002442: 4618 mov r0, r3
|
|
8002444: f004 fd6f bl 8006f26 <USB_ReadDevInEPInterrupt>
|
|
8002448: 6138 str r0, [r7, #16]
|
|
|
|
if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
|
|
800244a: 693b ldr r3, [r7, #16]
|
|
800244c: f003 0301 and.w r3, r3, #1
|
|
8002450: 2b00 cmp r3, #0
|
|
8002452: d057 beq.n 8002504 <HAL_PCD_IRQHandler+0x3ae>
|
|
{
|
|
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
|
|
8002454: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002456: f003 030f and.w r3, r3, #15
|
|
800245a: 2201 movs r2, #1
|
|
800245c: fa02 f303 lsl.w r3, r2, r3
|
|
8002460: 60fb str r3, [r7, #12]
|
|
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
|
|
8002462: 69fb ldr r3, [r7, #28]
|
|
8002464: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002468: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
800246a: 68fb ldr r3, [r7, #12]
|
|
800246c: 43db mvns r3, r3
|
|
800246e: 69f9 ldr r1, [r7, #28]
|
|
8002470: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8002474: 4013 ands r3, r2
|
|
8002476: 634b str r3, [r1, #52] @ 0x34
|
|
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
|
|
8002478: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800247a: 015a lsls r2, r3, #5
|
|
800247c: 69fb ldr r3, [r7, #28]
|
|
800247e: 4413 add r3, r2
|
|
8002480: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002484: 461a mov r2, r3
|
|
8002486: 2301 movs r3, #1
|
|
8002488: 6093 str r3, [r2, #8]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
800248a: 687b ldr r3, [r7, #4]
|
|
800248c: 799b ldrb r3, [r3, #6]
|
|
800248e: 2b01 cmp r3, #1
|
|
8002490: d132 bne.n 80024f8 <HAL_PCD_IRQHandler+0x3a2>
|
|
{
|
|
hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
|
|
8002492: 6879 ldr r1, [r7, #4]
|
|
8002494: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002496: 4613 mov r3, r2
|
|
8002498: 00db lsls r3, r3, #3
|
|
800249a: 4413 add r3, r2
|
|
800249c: 009b lsls r3, r3, #2
|
|
800249e: 440b add r3, r1
|
|
80024a0: 3320 adds r3, #32
|
|
80024a2: 6819 ldr r1, [r3, #0]
|
|
80024a4: 6878 ldr r0, [r7, #4]
|
|
80024a6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80024a8: 4613 mov r3, r2
|
|
80024aa: 00db lsls r3, r3, #3
|
|
80024ac: 4413 add r3, r2
|
|
80024ae: 009b lsls r3, r3, #2
|
|
80024b0: 4403 add r3, r0
|
|
80024b2: 331c adds r3, #28
|
|
80024b4: 681b ldr r3, [r3, #0]
|
|
80024b6: 4419 add r1, r3
|
|
80024b8: 6878 ldr r0, [r7, #4]
|
|
80024ba: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80024bc: 4613 mov r3, r2
|
|
80024be: 00db lsls r3, r3, #3
|
|
80024c0: 4413 add r3, r2
|
|
80024c2: 009b lsls r3, r3, #2
|
|
80024c4: 4403 add r3, r0
|
|
80024c6: 3320 adds r3, #32
|
|
80024c8: 6019 str r1, [r3, #0]
|
|
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
|
|
80024ca: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80024cc: 2b00 cmp r3, #0
|
|
80024ce: d113 bne.n 80024f8 <HAL_PCD_IRQHandler+0x3a2>
|
|
80024d0: 6879 ldr r1, [r7, #4]
|
|
80024d2: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80024d4: 4613 mov r3, r2
|
|
80024d6: 00db lsls r3, r3, #3
|
|
80024d8: 4413 add r3, r2
|
|
80024da: 009b lsls r3, r3, #2
|
|
80024dc: 440b add r3, r1
|
|
80024de: 3324 adds r3, #36 @ 0x24
|
|
80024e0: 681b ldr r3, [r3, #0]
|
|
80024e2: 2b00 cmp r3, #0
|
|
80024e4: d108 bne.n 80024f8 <HAL_PCD_IRQHandler+0x3a2>
|
|
{
|
|
/* prepare to rx more setup packets */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
80024e6: 687b ldr r3, [r7, #4]
|
|
80024e8: 6818 ldr r0, [r3, #0]
|
|
80024ea: 687b ldr r3, [r7, #4]
|
|
80024ec: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
80024f0: 461a mov r2, r3
|
|
80024f2: 2101 movs r1, #1
|
|
80024f4: f004 fd76 bl 8006fe4 <USB_EP0_OutStart>
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
|
|
80024f8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80024fa: b2db uxtb r3, r3
|
|
80024fc: 4619 mov r1, r3
|
|
80024fe: 6878 ldr r0, [r7, #4]
|
|
8002500: f006 fd7b bl 8008ffa <HAL_PCD_DataInStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
|
|
8002504: 693b ldr r3, [r7, #16]
|
|
8002506: f003 0308 and.w r3, r3, #8
|
|
800250a: 2b00 cmp r3, #0
|
|
800250c: d008 beq.n 8002520 <HAL_PCD_IRQHandler+0x3ca>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
|
|
800250e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002510: 015a lsls r2, r3, #5
|
|
8002512: 69fb ldr r3, [r7, #28]
|
|
8002514: 4413 add r3, r2
|
|
8002516: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800251a: 461a mov r2, r3
|
|
800251c: 2308 movs r3, #8
|
|
800251e: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
|
|
8002520: 693b ldr r3, [r7, #16]
|
|
8002522: f003 0310 and.w r3, r3, #16
|
|
8002526: 2b00 cmp r3, #0
|
|
8002528: d008 beq.n 800253c <HAL_PCD_IRQHandler+0x3e6>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
|
|
800252a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800252c: 015a lsls r2, r3, #5
|
|
800252e: 69fb ldr r3, [r7, #28]
|
|
8002530: 4413 add r3, r2
|
|
8002532: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002536: 461a mov r2, r3
|
|
8002538: 2310 movs r3, #16
|
|
800253a: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
|
|
800253c: 693b ldr r3, [r7, #16]
|
|
800253e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8002542: 2b00 cmp r3, #0
|
|
8002544: d008 beq.n 8002558 <HAL_PCD_IRQHandler+0x402>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
|
|
8002546: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002548: 015a lsls r2, r3, #5
|
|
800254a: 69fb ldr r3, [r7, #28]
|
|
800254c: 4413 add r3, r2
|
|
800254e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002552: 461a mov r2, r3
|
|
8002554: 2340 movs r3, #64 @ 0x40
|
|
8002556: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
|
|
8002558: 693b ldr r3, [r7, #16]
|
|
800255a: f003 0302 and.w r3, r3, #2
|
|
800255e: 2b00 cmp r3, #0
|
|
8002560: d023 beq.n 80025aa <HAL_PCD_IRQHandler+0x454>
|
|
{
|
|
(void)USB_FlushTxFifo(USBx, epnum);
|
|
8002562: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8002564: 6a38 ldr r0, [r7, #32]
|
|
8002566: f003 fd5d bl 8006024 <USB_FlushTxFifo>
|
|
|
|
ep = &hpcd->IN_ep[epnum];
|
|
800256a: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800256c: 4613 mov r3, r2
|
|
800256e: 00db lsls r3, r3, #3
|
|
8002570: 4413 add r3, r2
|
|
8002572: 009b lsls r3, r3, #2
|
|
8002574: 3310 adds r3, #16
|
|
8002576: 687a ldr r2, [r7, #4]
|
|
8002578: 4413 add r3, r2
|
|
800257a: 3304 adds r3, #4
|
|
800257c: 617b str r3, [r7, #20]
|
|
|
|
if (ep->is_iso_incomplete == 1U)
|
|
800257e: 697b ldr r3, [r7, #20]
|
|
8002580: 78db ldrb r3, [r3, #3]
|
|
8002582: 2b01 cmp r3, #1
|
|
8002584: d108 bne.n 8002598 <HAL_PCD_IRQHandler+0x442>
|
|
{
|
|
ep->is_iso_incomplete = 0U;
|
|
8002586: 697b ldr r3, [r7, #20]
|
|
8002588: 2200 movs r2, #0
|
|
800258a: 70da strb r2, [r3, #3]
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
800258c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800258e: b2db uxtb r3, r3
|
|
8002590: 4619 mov r1, r3
|
|
8002592: 6878 ldr r0, [r7, #4]
|
|
8002594: f006 fdc8 bl 8009128 <HAL_PCD_ISOINIncompleteCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
|
|
8002598: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800259a: 015a lsls r2, r3, #5
|
|
800259c: 69fb ldr r3, [r7, #28]
|
|
800259e: 4413 add r3, r2
|
|
80025a0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80025a4: 461a mov r2, r3
|
|
80025a6: 2302 movs r3, #2
|
|
80025a8: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
|
|
80025aa: 693b ldr r3, [r7, #16]
|
|
80025ac: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80025b0: 2b00 cmp r3, #0
|
|
80025b2: d003 beq.n 80025bc <HAL_PCD_IRQHandler+0x466>
|
|
{
|
|
(void)PCD_WriteEmptyTxFifo(hpcd, epnum);
|
|
80025b4: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
80025b6: 6878 ldr r0, [r7, #4]
|
|
80025b8: f000 fcd2 bl 8002f60 <PCD_WriteEmptyTxFifo>
|
|
}
|
|
}
|
|
epnum++;
|
|
80025bc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80025be: 3301 adds r3, #1
|
|
80025c0: 627b str r3, [r7, #36] @ 0x24
|
|
ep_intr >>= 1U;
|
|
80025c2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80025c4: 085b lsrs r3, r3, #1
|
|
80025c6: 62bb str r3, [r7, #40] @ 0x28
|
|
while (ep_intr != 0U)
|
|
80025c8: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80025ca: 2b00 cmp r3, #0
|
|
80025cc: f47f af2e bne.w 800242c <HAL_PCD_IRQHandler+0x2d6>
|
|
}
|
|
}
|
|
|
|
/* Handle Resume Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
|
|
80025d0: 687b ldr r3, [r7, #4]
|
|
80025d2: 681b ldr r3, [r3, #0]
|
|
80025d4: 4618 mov r0, r3
|
|
80025d6: f004 fc41 bl 8006e5c <USB_ReadInterrupts>
|
|
80025da: 4603 mov r3, r0
|
|
80025dc: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80025e0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80025e4: d122 bne.n 800262c <HAL_PCD_IRQHandler+0x4d6>
|
|
{
|
|
/* Clear the Remote Wake-up Signaling */
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
|
|
80025e6: 69fb ldr r3, [r7, #28]
|
|
80025e8: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80025ec: 685b ldr r3, [r3, #4]
|
|
80025ee: 69fa ldr r2, [r7, #28]
|
|
80025f0: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80025f4: f023 0301 bic.w r3, r3, #1
|
|
80025f8: 6053 str r3, [r2, #4]
|
|
|
|
if (hpcd->LPM_State == LPM_L1)
|
|
80025fa: 687b ldr r3, [r7, #4]
|
|
80025fc: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
|
|
8002600: 2b01 cmp r3, #1
|
|
8002602: d108 bne.n 8002616 <HAL_PCD_IRQHandler+0x4c0>
|
|
{
|
|
hpcd->LPM_State = LPM_L0;
|
|
8002604: 687b ldr r3, [r7, #4]
|
|
8002606: 2200 movs r2, #0
|
|
8002608: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
|
|
#else
|
|
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
|
|
800260c: 2100 movs r1, #0
|
|
800260e: 6878 ldr r0, [r7, #4]
|
|
8002610: f006 ff30 bl 8009474 <HAL_PCDEx_LPM_Callback>
|
|
8002614: e002 b.n 800261c <HAL_PCD_IRQHandler+0x4c6>
|
|
else
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResumeCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResumeCallback(hpcd);
|
|
8002616: 6878 ldr r0, [r7, #4]
|
|
8002618: f006 fd66 bl 80090e8 <HAL_PCD_ResumeCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
|
|
800261c: 687b ldr r3, [r7, #4]
|
|
800261e: 681b ldr r3, [r3, #0]
|
|
8002620: 695a ldr r2, [r3, #20]
|
|
8002622: 687b ldr r3, [r7, #4]
|
|
8002624: 681b ldr r3, [r3, #0]
|
|
8002626: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000
|
|
800262a: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Suspend Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
|
|
800262c: 687b ldr r3, [r7, #4]
|
|
800262e: 681b ldr r3, [r3, #0]
|
|
8002630: 4618 mov r0, r3
|
|
8002632: f004 fc13 bl 8006e5c <USB_ReadInterrupts>
|
|
8002636: 4603 mov r3, r0
|
|
8002638: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
800263c: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8002640: d112 bne.n 8002668 <HAL_PCD_IRQHandler+0x512>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
|
|
8002642: 69fb ldr r3, [r7, #28]
|
|
8002644: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002648: 689b ldr r3, [r3, #8]
|
|
800264a: f003 0301 and.w r3, r3, #1
|
|
800264e: 2b01 cmp r3, #1
|
|
8002650: d102 bne.n 8002658 <HAL_PCD_IRQHandler+0x502>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SuspendCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
8002652: 6878 ldr r0, [r7, #4]
|
|
8002654: f006 fd22 bl 800909c <HAL_PCD_SuspendCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
|
|
8002658: 687b ldr r3, [r7, #4]
|
|
800265a: 681b ldr r3, [r3, #0]
|
|
800265c: 695a ldr r2, [r3, #20]
|
|
800265e: 687b ldr r3, [r7, #4]
|
|
8002660: 681b ldr r3, [r3, #0]
|
|
8002662: f402 6200 and.w r2, r2, #2048 @ 0x800
|
|
8002666: 615a str r2, [r3, #20]
|
|
}
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* Handle LPM Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
|
|
8002668: 687b ldr r3, [r7, #4]
|
|
800266a: 681b ldr r3, [r3, #0]
|
|
800266c: 4618 mov r0, r3
|
|
800266e: f004 fbf5 bl 8006e5c <USB_ReadInterrupts>
|
|
8002672: 4603 mov r3, r0
|
|
8002674: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8002678: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
800267c: d121 bne.n 80026c2 <HAL_PCD_IRQHandler+0x56c>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
|
|
800267e: 687b ldr r3, [r7, #4]
|
|
8002680: 681b ldr r3, [r3, #0]
|
|
8002682: 695a ldr r2, [r3, #20]
|
|
8002684: 687b ldr r3, [r7, #4]
|
|
8002686: 681b ldr r3, [r3, #0]
|
|
8002688: f002 6200 and.w r2, r2, #134217728 @ 0x8000000
|
|
800268c: 615a str r2, [r3, #20]
|
|
|
|
if (hpcd->LPM_State == LPM_L0)
|
|
800268e: 687b ldr r3, [r7, #4]
|
|
8002690: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
|
|
8002694: 2b00 cmp r3, #0
|
|
8002696: d111 bne.n 80026bc <HAL_PCD_IRQHandler+0x566>
|
|
{
|
|
hpcd->LPM_State = LPM_L1;
|
|
8002698: 687b ldr r3, [r7, #4]
|
|
800269a: 2201 movs r2, #1
|
|
800269c: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
|
|
80026a0: 687b ldr r3, [r7, #4]
|
|
80026a2: 681b ldr r3, [r3, #0]
|
|
80026a4: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80026a6: 089b lsrs r3, r3, #2
|
|
80026a8: f003 020f and.w r2, r3, #15
|
|
80026ac: 687b ldr r3, [r7, #4]
|
|
80026ae: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
|
|
#else
|
|
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
|
|
80026b2: 2101 movs r1, #1
|
|
80026b4: 6878 ldr r0, [r7, #4]
|
|
80026b6: f006 fedd bl 8009474 <HAL_PCDEx_LPM_Callback>
|
|
80026ba: e002 b.n 80026c2 <HAL_PCD_IRQHandler+0x56c>
|
|
else
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SuspendCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
80026bc: 6878 ldr r0, [r7, #4]
|
|
80026be: f006 fced bl 800909c <HAL_PCD_SuspendCallback>
|
|
}
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
/* Handle Reset Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
|
|
80026c2: 687b ldr r3, [r7, #4]
|
|
80026c4: 681b ldr r3, [r3, #0]
|
|
80026c6: 4618 mov r0, r3
|
|
80026c8: f004 fbc8 bl 8006e5c <USB_ReadInterrupts>
|
|
80026cc: 4603 mov r3, r0
|
|
80026ce: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
80026d2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
80026d6: f040 80b7 bne.w 8002848 <HAL_PCD_IRQHandler+0x6f2>
|
|
{
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
|
|
80026da: 69fb ldr r3, [r7, #28]
|
|
80026dc: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80026e0: 685b ldr r3, [r3, #4]
|
|
80026e2: 69fa ldr r2, [r7, #28]
|
|
80026e4: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80026e8: f023 0301 bic.w r3, r3, #1
|
|
80026ec: 6053 str r3, [r2, #4]
|
|
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
|
|
80026ee: 687b ldr r3, [r7, #4]
|
|
80026f0: 681b ldr r3, [r3, #0]
|
|
80026f2: 2110 movs r1, #16
|
|
80026f4: 4618 mov r0, r3
|
|
80026f6: f003 fc95 bl 8006024 <USB_FlushTxFifo>
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
80026fa: 2300 movs r3, #0
|
|
80026fc: 62fb str r3, [r7, #44] @ 0x2c
|
|
80026fe: e046 b.n 800278e <HAL_PCD_IRQHandler+0x638>
|
|
{
|
|
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
|
8002700: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002702: 015a lsls r2, r3, #5
|
|
8002704: 69fb ldr r3, [r7, #28]
|
|
8002706: 4413 add r3, r2
|
|
8002708: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800270c: 461a mov r2, r3
|
|
800270e: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
8002712: 6093 str r3, [r2, #8]
|
|
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
|
8002714: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002716: 015a lsls r2, r3, #5
|
|
8002718: 69fb ldr r3, [r7, #28]
|
|
800271a: 4413 add r3, r2
|
|
800271c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002720: 681b ldr r3, [r3, #0]
|
|
8002722: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8002724: 0151 lsls r1, r2, #5
|
|
8002726: 69fa ldr r2, [r7, #28]
|
|
8002728: 440a add r2, r1
|
|
800272a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800272e: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
8002732: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
|
8002734: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002736: 015a lsls r2, r3, #5
|
|
8002738: 69fb ldr r3, [r7, #28]
|
|
800273a: 4413 add r3, r2
|
|
800273c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002740: 461a mov r2, r3
|
|
8002742: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
8002746: 6093 str r3, [r2, #8]
|
|
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
|
8002748: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800274a: 015a lsls r2, r3, #5
|
|
800274c: 69fb ldr r3, [r7, #28]
|
|
800274e: 4413 add r3, r2
|
|
8002750: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002754: 681b ldr r3, [r3, #0]
|
|
8002756: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8002758: 0151 lsls r1, r2, #5
|
|
800275a: 69fa ldr r2, [r7, #28]
|
|
800275c: 440a add r2, r1
|
|
800275e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8002762: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
8002766: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
|
8002768: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800276a: 015a lsls r2, r3, #5
|
|
800276c: 69fb ldr r3, [r7, #28]
|
|
800276e: 4413 add r3, r2
|
|
8002770: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002774: 681b ldr r3, [r3, #0]
|
|
8002776: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8002778: 0151 lsls r1, r2, #5
|
|
800277a: 69fa ldr r2, [r7, #28]
|
|
800277c: 440a add r2, r1
|
|
800277e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8002782: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8002786: 6013 str r3, [r2, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8002788: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800278a: 3301 adds r3, #1
|
|
800278c: 62fb str r3, [r7, #44] @ 0x2c
|
|
800278e: 687b ldr r3, [r7, #4]
|
|
8002790: 791b ldrb r3, [r3, #4]
|
|
8002792: 461a mov r2, r3
|
|
8002794: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002796: 4293 cmp r3, r2
|
|
8002798: d3b2 bcc.n 8002700 <HAL_PCD_IRQHandler+0x5aa>
|
|
}
|
|
USBx_DEVICE->DAINTMSK |= 0x10001U;
|
|
800279a: 69fb ldr r3, [r7, #28]
|
|
800279c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80027a0: 69db ldr r3, [r3, #28]
|
|
80027a2: 69fa ldr r2, [r7, #28]
|
|
80027a4: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80027a8: f043 1301 orr.w r3, r3, #65537 @ 0x10001
|
|
80027ac: 61d3 str r3, [r2, #28]
|
|
|
|
if (hpcd->Init.use_dedicated_ep1 != 0U)
|
|
80027ae: 687b ldr r3, [r7, #4]
|
|
80027b0: 7bdb ldrb r3, [r3, #15]
|
|
80027b2: 2b00 cmp r3, #0
|
|
80027b4: d016 beq.n 80027e4 <HAL_PCD_IRQHandler+0x68e>
|
|
{
|
|
USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
|
|
80027b6: 69fb ldr r3, [r7, #28]
|
|
80027b8: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80027bc: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80027c0: 69fa ldr r2, [r7, #28]
|
|
80027c2: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80027c6: f043 030b orr.w r3, r3, #11
|
|
80027ca: f8c2 3084 str.w r3, [r2, #132] @ 0x84
|
|
USB_OTG_DOEPMSK_XFRCM |
|
|
USB_OTG_DOEPMSK_EPDM;
|
|
|
|
USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
|
|
80027ce: 69fb ldr r3, [r7, #28]
|
|
80027d0: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80027d4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80027d6: 69fa ldr r2, [r7, #28]
|
|
80027d8: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80027dc: f043 030b orr.w r3, r3, #11
|
|
80027e0: 6453 str r3, [r2, #68] @ 0x44
|
|
80027e2: e015 b.n 8002810 <HAL_PCD_IRQHandler+0x6ba>
|
|
USB_OTG_DIEPMSK_XFRCM |
|
|
USB_OTG_DIEPMSK_EPDM;
|
|
}
|
|
else
|
|
{
|
|
USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
|
|
80027e4: 69fb ldr r3, [r7, #28]
|
|
80027e6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80027ea: 695b ldr r3, [r3, #20]
|
|
80027ec: 69fa ldr r2, [r7, #28]
|
|
80027ee: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80027f2: f443 5300 orr.w r3, r3, #8192 @ 0x2000
|
|
80027f6: f043 032b orr.w r3, r3, #43 @ 0x2b
|
|
80027fa: 6153 str r3, [r2, #20]
|
|
USB_OTG_DOEPMSK_XFRCM |
|
|
USB_OTG_DOEPMSK_EPDM |
|
|
USB_OTG_DOEPMSK_OTEPSPRM |
|
|
USB_OTG_DOEPMSK_NAKM;
|
|
|
|
USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
|
|
80027fc: 69fb ldr r3, [r7, #28]
|
|
80027fe: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002802: 691b ldr r3, [r3, #16]
|
|
8002804: 69fa ldr r2, [r7, #28]
|
|
8002806: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
800280a: f043 030b orr.w r3, r3, #11
|
|
800280e: 6113 str r3, [r2, #16]
|
|
USB_OTG_DIEPMSK_XFRCM |
|
|
USB_OTG_DIEPMSK_EPDM;
|
|
}
|
|
|
|
/* Set Default Address to 0 */
|
|
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
|
|
8002810: 69fb ldr r3, [r7, #28]
|
|
8002812: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002816: 681b ldr r3, [r3, #0]
|
|
8002818: 69fa ldr r2, [r7, #28]
|
|
800281a: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
800281e: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
|
|
8002822: 6013 str r3, [r2, #0]
|
|
|
|
/* setup EP0 to receive SETUP packets */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
|
|
8002824: 687b ldr r3, [r7, #4]
|
|
8002826: 6818 ldr r0, [r3, #0]
|
|
8002828: 687b ldr r3, [r7, #4]
|
|
800282a: 7999 ldrb r1, [r3, #6]
|
|
(uint8_t *)hpcd->Setup);
|
|
800282c: 687b ldr r3, [r7, #4]
|
|
800282e: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
|
|
8002832: 461a mov r2, r3
|
|
8002834: f004 fbd6 bl 8006fe4 <USB_EP0_OutStart>
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
|
|
8002838: 687b ldr r3, [r7, #4]
|
|
800283a: 681b ldr r3, [r3, #0]
|
|
800283c: 695a ldr r2, [r3, #20]
|
|
800283e: 687b ldr r3, [r7, #4]
|
|
8002840: 681b ldr r3, [r3, #0]
|
|
8002842: f402 5280 and.w r2, r2, #4096 @ 0x1000
|
|
8002846: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Enumeration done Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
|
|
8002848: 687b ldr r3, [r7, #4]
|
|
800284a: 681b ldr r3, [r3, #0]
|
|
800284c: 4618 mov r0, r3
|
|
800284e: f004 fb05 bl 8006e5c <USB_ReadInterrupts>
|
|
8002852: 4603 mov r3, r0
|
|
8002854: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
8002858: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
800285c: d123 bne.n 80028a6 <HAL_PCD_IRQHandler+0x750>
|
|
{
|
|
(void)USB_ActivateSetup(hpcd->Instance);
|
|
800285e: 687b ldr r3, [r7, #4]
|
|
8002860: 681b ldr r3, [r3, #0]
|
|
8002862: 4618 mov r0, r3
|
|
8002864: f004 fb9b bl 8006f9e <USB_ActivateSetup>
|
|
hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
|
|
8002868: 687b ldr r3, [r7, #4]
|
|
800286a: 681b ldr r3, [r3, #0]
|
|
800286c: 4618 mov r0, r3
|
|
800286e: f003 fc52 bl 8006116 <USB_GetDevSpeed>
|
|
8002872: 4603 mov r3, r0
|
|
8002874: 461a mov r2, r3
|
|
8002876: 687b ldr r3, [r7, #4]
|
|
8002878: 71da strb r2, [r3, #7]
|
|
|
|
/* Set USB Turnaround time */
|
|
(void)USB_SetTurnaroundTime(hpcd->Instance,
|
|
800287a: 687b ldr r3, [r7, #4]
|
|
800287c: 681c ldr r4, [r3, #0]
|
|
800287e: f000 fe8b bl 8003598 <HAL_RCC_GetHCLKFreq>
|
|
8002882: 4601 mov r1, r0
|
|
HAL_RCC_GetHCLKFreq(),
|
|
(uint8_t)hpcd->Init.speed);
|
|
8002884: 687b ldr r3, [r7, #4]
|
|
8002886: 79db ldrb r3, [r3, #7]
|
|
(void)USB_SetTurnaroundTime(hpcd->Instance,
|
|
8002888: 461a mov r2, r3
|
|
800288a: 4620 mov r0, r4
|
|
800288c: f003 f95c bl 8005b48 <USB_SetTurnaroundTime>
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResetCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResetCallback(hpcd);
|
|
8002890: 6878 ldr r0, [r7, #4]
|
|
8002892: f006 fbda bl 800904a <HAL_PCD_ResetCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
|
|
8002896: 687b ldr r3, [r7, #4]
|
|
8002898: 681b ldr r3, [r3, #0]
|
|
800289a: 695a ldr r2, [r3, #20]
|
|
800289c: 687b ldr r3, [r7, #4]
|
|
800289e: 681b ldr r3, [r3, #0]
|
|
80028a0: f402 5200 and.w r2, r2, #8192 @ 0x2000
|
|
80028a4: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle SOF Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
|
|
80028a6: 687b ldr r3, [r7, #4]
|
|
80028a8: 681b ldr r3, [r3, #0]
|
|
80028aa: 4618 mov r0, r3
|
|
80028ac: f004 fad6 bl 8006e5c <USB_ReadInterrupts>
|
|
80028b0: 4603 mov r3, r0
|
|
80028b2: f003 0308 and.w r3, r3, #8
|
|
80028b6: 2b08 cmp r3, #8
|
|
80028b8: d10a bne.n 80028d0 <HAL_PCD_IRQHandler+0x77a>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SOFCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SOFCallback(hpcd);
|
|
80028ba: 6878 ldr r0, [r7, #4]
|
|
80028bc: f006 fbb7 bl 800902e <HAL_PCD_SOFCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
|
|
80028c0: 687b ldr r3, [r7, #4]
|
|
80028c2: 681b ldr r3, [r3, #0]
|
|
80028c4: 695a ldr r2, [r3, #20]
|
|
80028c6: 687b ldr r3, [r7, #4]
|
|
80028c8: 681b ldr r3, [r3, #0]
|
|
80028ca: f002 0208 and.w r2, r2, #8
|
|
80028ce: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Global OUT NAK effective Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF))
|
|
80028d0: 687b ldr r3, [r7, #4]
|
|
80028d2: 681b ldr r3, [r3, #0]
|
|
80028d4: 4618 mov r0, r3
|
|
80028d6: f004 fac1 bl 8006e5c <USB_ReadInterrupts>
|
|
80028da: 4603 mov r3, r0
|
|
80028dc: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80028e0: 2b80 cmp r3, #128 @ 0x80
|
|
80028e2: d123 bne.n 800292c <HAL_PCD_IRQHandler+0x7d6>
|
|
{
|
|
USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM;
|
|
80028e4: 6a3b ldr r3, [r7, #32]
|
|
80028e6: 699b ldr r3, [r3, #24]
|
|
80028e8: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
80028ec: 6a3b ldr r3, [r7, #32]
|
|
80028ee: 619a str r2, [r3, #24]
|
|
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
80028f0: 2301 movs r3, #1
|
|
80028f2: 627b str r3, [r7, #36] @ 0x24
|
|
80028f4: e014 b.n 8002920 <HAL_PCD_IRQHandler+0x7ca>
|
|
{
|
|
if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U)
|
|
80028f6: 6879 ldr r1, [r7, #4]
|
|
80028f8: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80028fa: 4613 mov r3, r2
|
|
80028fc: 00db lsls r3, r3, #3
|
|
80028fe: 4413 add r3, r2
|
|
8002900: 009b lsls r3, r3, #2
|
|
8002902: 440b add r3, r1
|
|
8002904: f203 2357 addw r3, r3, #599 @ 0x257
|
|
8002908: 781b ldrb r3, [r3, #0]
|
|
800290a: 2b01 cmp r3, #1
|
|
800290c: d105 bne.n 800291a <HAL_PCD_IRQHandler+0x7c4>
|
|
{
|
|
/* Abort current transaction and disable the EP */
|
|
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum);
|
|
800290e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002910: b2db uxtb r3, r3
|
|
8002912: 4619 mov r1, r3
|
|
8002914: 6878 ldr r0, [r7, #4]
|
|
8002916: f000 faf2 bl 8002efe <HAL_PCD_EP_Abort>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
800291a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800291c: 3301 adds r3, #1
|
|
800291e: 627b str r3, [r7, #36] @ 0x24
|
|
8002920: 687b ldr r3, [r7, #4]
|
|
8002922: 791b ldrb r3, [r3, #4]
|
|
8002924: 461a mov r2, r3
|
|
8002926: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002928: 4293 cmp r3, r2
|
|
800292a: d3e4 bcc.n 80028f6 <HAL_PCD_IRQHandler+0x7a0>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Handle Incomplete ISO IN Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
|
|
800292c: 687b ldr r3, [r7, #4]
|
|
800292e: 681b ldr r3, [r3, #0]
|
|
8002930: 4618 mov r0, r3
|
|
8002932: f004 fa93 bl 8006e5c <USB_ReadInterrupts>
|
|
8002936: 4603 mov r3, r0
|
|
8002938: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
800293c: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8002940: d13c bne.n 80029bc <HAL_PCD_IRQHandler+0x866>
|
|
{
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
8002942: 2301 movs r3, #1
|
|
8002944: 627b str r3, [r7, #36] @ 0x24
|
|
8002946: e02b b.n 80029a0 <HAL_PCD_IRQHandler+0x84a>
|
|
{
|
|
RegVal = USBx_INEP(epnum)->DIEPCTL;
|
|
8002948: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800294a: 015a lsls r2, r3, #5
|
|
800294c: 69fb ldr r3, [r7, #28]
|
|
800294e: 4413 add r3, r2
|
|
8002950: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002954: 681b ldr r3, [r3, #0]
|
|
8002956: 61bb str r3, [r7, #24]
|
|
|
|
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
8002958: 6879 ldr r1, [r7, #4]
|
|
800295a: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800295c: 4613 mov r3, r2
|
|
800295e: 00db lsls r3, r3, #3
|
|
8002960: 4413 add r3, r2
|
|
8002962: 009b lsls r3, r3, #2
|
|
8002964: 440b add r3, r1
|
|
8002966: 3318 adds r3, #24
|
|
8002968: 781b ldrb r3, [r3, #0]
|
|
800296a: 2b01 cmp r3, #1
|
|
800296c: d115 bne.n 800299a <HAL_PCD_IRQHandler+0x844>
|
|
((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA))
|
|
800296e: 69bb ldr r3, [r7, #24]
|
|
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
8002970: 2b00 cmp r3, #0
|
|
8002972: da12 bge.n 800299a <HAL_PCD_IRQHandler+0x844>
|
|
{
|
|
hpcd->IN_ep[epnum].is_iso_incomplete = 1U;
|
|
8002974: 6879 ldr r1, [r7, #4]
|
|
8002976: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002978: 4613 mov r3, r2
|
|
800297a: 00db lsls r3, r3, #3
|
|
800297c: 4413 add r3, r2
|
|
800297e: 009b lsls r3, r3, #2
|
|
8002980: 440b add r3, r1
|
|
8002982: 3317 adds r3, #23
|
|
8002984: 2201 movs r2, #1
|
|
8002986: 701a strb r2, [r3, #0]
|
|
|
|
/* Abort current transaction and disable the EP */
|
|
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U));
|
|
8002988: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800298a: b2db uxtb r3, r3
|
|
800298c: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8002990: b2db uxtb r3, r3
|
|
8002992: 4619 mov r1, r3
|
|
8002994: 6878 ldr r0, [r7, #4]
|
|
8002996: f000 fab2 bl 8002efe <HAL_PCD_EP_Abort>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
800299a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800299c: 3301 adds r3, #1
|
|
800299e: 627b str r3, [r7, #36] @ 0x24
|
|
80029a0: 687b ldr r3, [r7, #4]
|
|
80029a2: 791b ldrb r3, [r3, #4]
|
|
80029a4: 461a mov r2, r3
|
|
80029a6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80029a8: 4293 cmp r3, r2
|
|
80029aa: d3cd bcc.n 8002948 <HAL_PCD_IRQHandler+0x7f2>
|
|
}
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
|
|
80029ac: 687b ldr r3, [r7, #4]
|
|
80029ae: 681b ldr r3, [r3, #0]
|
|
80029b0: 695a ldr r2, [r3, #20]
|
|
80029b2: 687b ldr r3, [r7, #4]
|
|
80029b4: 681b ldr r3, [r3, #0]
|
|
80029b6: f402 1280 and.w r2, r2, #1048576 @ 0x100000
|
|
80029ba: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Incomplete ISO OUT Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
|
|
80029bc: 687b ldr r3, [r7, #4]
|
|
80029be: 681b ldr r3, [r3, #0]
|
|
80029c0: 4618 mov r0, r3
|
|
80029c2: f004 fa4b bl 8006e5c <USB_ReadInterrupts>
|
|
80029c6: 4603 mov r3, r0
|
|
80029c8: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
80029cc: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
|
|
80029d0: d156 bne.n 8002a80 <HAL_PCD_IRQHandler+0x92a>
|
|
{
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
80029d2: 2301 movs r3, #1
|
|
80029d4: 627b str r3, [r7, #36] @ 0x24
|
|
80029d6: e045 b.n 8002a64 <HAL_PCD_IRQHandler+0x90e>
|
|
{
|
|
RegVal = USBx_OUTEP(epnum)->DOEPCTL;
|
|
80029d8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80029da: 015a lsls r2, r3, #5
|
|
80029dc: 69fb ldr r3, [r7, #28]
|
|
80029de: 4413 add r3, r2
|
|
80029e0: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80029e4: 681b ldr r3, [r3, #0]
|
|
80029e6: 61bb str r3, [r7, #24]
|
|
|
|
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
80029e8: 6879 ldr r1, [r7, #4]
|
|
80029ea: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80029ec: 4613 mov r3, r2
|
|
80029ee: 00db lsls r3, r3, #3
|
|
80029f0: 4413 add r3, r2
|
|
80029f2: 009b lsls r3, r3, #2
|
|
80029f4: 440b add r3, r1
|
|
80029f6: f503 7316 add.w r3, r3, #600 @ 0x258
|
|
80029fa: 781b ldrb r3, [r3, #0]
|
|
80029fc: 2b01 cmp r3, #1
|
|
80029fe: d12e bne.n 8002a5e <HAL_PCD_IRQHandler+0x908>
|
|
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
|
|
8002a00: 69bb ldr r3, [r7, #24]
|
|
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
8002a02: 2b00 cmp r3, #0
|
|
8002a04: da2b bge.n 8002a5e <HAL_PCD_IRQHandler+0x908>
|
|
(((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U)))
|
|
8002a06: 69bb ldr r3, [r7, #24]
|
|
8002a08: 0c1a lsrs r2, r3, #16
|
|
8002a0a: 687b ldr r3, [r7, #4]
|
|
8002a0c: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4
|
|
8002a10: 4053 eors r3, r2
|
|
8002a12: f003 0301 and.w r3, r3, #1
|
|
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
|
|
8002a16: 2b00 cmp r3, #0
|
|
8002a18: d121 bne.n 8002a5e <HAL_PCD_IRQHandler+0x908>
|
|
{
|
|
hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
|
|
8002a1a: 6879 ldr r1, [r7, #4]
|
|
8002a1c: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002a1e: 4613 mov r3, r2
|
|
8002a20: 00db lsls r3, r3, #3
|
|
8002a22: 4413 add r3, r2
|
|
8002a24: 009b lsls r3, r3, #2
|
|
8002a26: 440b add r3, r1
|
|
8002a28: f203 2357 addw r3, r3, #599 @ 0x257
|
|
8002a2c: 2201 movs r2, #1
|
|
8002a2e: 701a strb r2, [r3, #0]
|
|
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM;
|
|
8002a30: 6a3b ldr r3, [r7, #32]
|
|
8002a32: 699b ldr r3, [r3, #24]
|
|
8002a34: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
8002a38: 6a3b ldr r3, [r7, #32]
|
|
8002a3a: 619a str r2, [r3, #24]
|
|
|
|
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U)
|
|
8002a3c: 6a3b ldr r3, [r7, #32]
|
|
8002a3e: 695b ldr r3, [r3, #20]
|
|
8002a40: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002a44: 2b00 cmp r3, #0
|
|
8002a46: d10a bne.n 8002a5e <HAL_PCD_IRQHandler+0x908>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
|
|
8002a48: 69fb ldr r3, [r7, #28]
|
|
8002a4a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002a4e: 685b ldr r3, [r3, #4]
|
|
8002a50: 69fa ldr r2, [r7, #28]
|
|
8002a52: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8002a56: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8002a5a: 6053 str r3, [r2, #4]
|
|
break;
|
|
8002a5c: e008 b.n 8002a70 <HAL_PCD_IRQHandler+0x91a>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
8002a5e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002a60: 3301 adds r3, #1
|
|
8002a62: 627b str r3, [r7, #36] @ 0x24
|
|
8002a64: 687b ldr r3, [r7, #4]
|
|
8002a66: 791b ldrb r3, [r3, #4]
|
|
8002a68: 461a mov r2, r3
|
|
8002a6a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002a6c: 4293 cmp r3, r2
|
|
8002a6e: d3b3 bcc.n 80029d8 <HAL_PCD_IRQHandler+0x882>
|
|
}
|
|
}
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
|
|
8002a70: 687b ldr r3, [r7, #4]
|
|
8002a72: 681b ldr r3, [r3, #0]
|
|
8002a74: 695a ldr r2, [r3, #20]
|
|
8002a76: 687b ldr r3, [r7, #4]
|
|
8002a78: 681b ldr r3, [r3, #0]
|
|
8002a7a: f402 1200 and.w r2, r2, #2097152 @ 0x200000
|
|
8002a7e: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Connection event Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
|
|
8002a80: 687b ldr r3, [r7, #4]
|
|
8002a82: 681b ldr r3, [r3, #0]
|
|
8002a84: 4618 mov r0, r3
|
|
8002a86: f004 f9e9 bl 8006e5c <USB_ReadInterrupts>
|
|
8002a8a: 4603 mov r3, r0
|
|
8002a8c: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
|
|
8002a90: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8002a94: d10a bne.n 8002aac <HAL_PCD_IRQHandler+0x956>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ConnectCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ConnectCallback(hpcd);
|
|
8002a96: 6878 ldr r0, [r7, #4]
|
|
8002a98: f006 fb58 bl 800914c <HAL_PCD_ConnectCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
|
|
8002a9c: 687b ldr r3, [r7, #4]
|
|
8002a9e: 681b ldr r3, [r3, #0]
|
|
8002aa0: 695a ldr r2, [r3, #20]
|
|
8002aa2: 687b ldr r3, [r7, #4]
|
|
8002aa4: 681b ldr r3, [r3, #0]
|
|
8002aa6: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000
|
|
8002aaa: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Disconnection event Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
|
|
8002aac: 687b ldr r3, [r7, #4]
|
|
8002aae: 681b ldr r3, [r3, #0]
|
|
8002ab0: 4618 mov r0, r3
|
|
8002ab2: f004 f9d3 bl 8006e5c <USB_ReadInterrupts>
|
|
8002ab6: 4603 mov r3, r0
|
|
8002ab8: f003 0304 and.w r3, r3, #4
|
|
8002abc: 2b04 cmp r3, #4
|
|
8002abe: d115 bne.n 8002aec <HAL_PCD_IRQHandler+0x996>
|
|
{
|
|
RegVal = hpcd->Instance->GOTGINT;
|
|
8002ac0: 687b ldr r3, [r7, #4]
|
|
8002ac2: 681b ldr r3, [r3, #0]
|
|
8002ac4: 685b ldr r3, [r3, #4]
|
|
8002ac6: 61bb str r3, [r7, #24]
|
|
|
|
if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
|
|
8002ac8: 69bb ldr r3, [r7, #24]
|
|
8002aca: f003 0304 and.w r3, r3, #4
|
|
8002ace: 2b00 cmp r3, #0
|
|
8002ad0: d002 beq.n 8002ad8 <HAL_PCD_IRQHandler+0x982>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DisconnectCallback(hpcd);
|
|
#else
|
|
HAL_PCD_DisconnectCallback(hpcd);
|
|
8002ad2: 6878 ldr r0, [r7, #4]
|
|
8002ad4: f006 fb48 bl 8009168 <HAL_PCD_DisconnectCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
hpcd->Instance->GOTGINT |= RegVal;
|
|
8002ad8: 687b ldr r3, [r7, #4]
|
|
8002ada: 681b ldr r3, [r3, #0]
|
|
8002adc: 6859 ldr r1, [r3, #4]
|
|
8002ade: 687b ldr r3, [r7, #4]
|
|
8002ae0: 681b ldr r3, [r3, #0]
|
|
8002ae2: 69ba ldr r2, [r7, #24]
|
|
8002ae4: 430a orrs r2, r1
|
|
8002ae6: 605a str r2, [r3, #4]
|
|
8002ae8: e000 b.n 8002aec <HAL_PCD_IRQHandler+0x996>
|
|
return;
|
|
8002aea: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
8002aec: 3734 adds r7, #52 @ 0x34
|
|
8002aee: 46bd mov sp, r7
|
|
8002af0: bd90 pop {r4, r7, pc}
|
|
|
|
08002af2 <HAL_PCD_SetAddress>:
|
|
* @param hpcd PCD handle
|
|
* @param address new device address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
|
|
{
|
|
8002af2: b580 push {r7, lr}
|
|
8002af4: b082 sub sp, #8
|
|
8002af6: af00 add r7, sp, #0
|
|
8002af8: 6078 str r0, [r7, #4]
|
|
8002afa: 460b mov r3, r1
|
|
8002afc: 70fb strb r3, [r7, #3]
|
|
__HAL_LOCK(hpcd);
|
|
8002afe: 687b ldr r3, [r7, #4]
|
|
8002b00: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002b04: 2b01 cmp r3, #1
|
|
8002b06: d101 bne.n 8002b0c <HAL_PCD_SetAddress+0x1a>
|
|
8002b08: 2302 movs r3, #2
|
|
8002b0a: e012 b.n 8002b32 <HAL_PCD_SetAddress+0x40>
|
|
8002b0c: 687b ldr r3, [r7, #4]
|
|
8002b0e: 2201 movs r2, #1
|
|
8002b10: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
hpcd->USB_Address = address;
|
|
8002b14: 687b ldr r3, [r7, #4]
|
|
8002b16: 78fa ldrb r2, [r7, #3]
|
|
8002b18: 745a strb r2, [r3, #17]
|
|
(void)USB_SetDevAddress(hpcd->Instance, address);
|
|
8002b1a: 687b ldr r3, [r7, #4]
|
|
8002b1c: 681b ldr r3, [r3, #0]
|
|
8002b1e: 78fa ldrb r2, [r7, #3]
|
|
8002b20: 4611 mov r1, r2
|
|
8002b22: 4618 mov r0, r3
|
|
8002b24: f004 f932 bl 8006d8c <USB_SetDevAddress>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002b28: 687b ldr r3, [r7, #4]
|
|
8002b2a: 2200 movs r2, #0
|
|
8002b2c: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8002b30: 2300 movs r3, #0
|
|
}
|
|
8002b32: 4618 mov r0, r3
|
|
8002b34: 3708 adds r7, #8
|
|
8002b36: 46bd mov sp, r7
|
|
8002b38: bd80 pop {r7, pc}
|
|
|
|
08002b3a <HAL_PCD_EP_Open>:
|
|
* @param ep_type endpoint type
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
|
uint16_t ep_mps, uint8_t ep_type)
|
|
{
|
|
8002b3a: b580 push {r7, lr}
|
|
8002b3c: b084 sub sp, #16
|
|
8002b3e: af00 add r7, sp, #0
|
|
8002b40: 6078 str r0, [r7, #4]
|
|
8002b42: 4608 mov r0, r1
|
|
8002b44: 4611 mov r1, r2
|
|
8002b46: 461a mov r2, r3
|
|
8002b48: 4603 mov r3, r0
|
|
8002b4a: 70fb strb r3, [r7, #3]
|
|
8002b4c: 460b mov r3, r1
|
|
8002b4e: 803b strh r3, [r7, #0]
|
|
8002b50: 4613 mov r3, r2
|
|
8002b52: 70bb strb r3, [r7, #2]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8002b54: 2300 movs r3, #0
|
|
8002b56: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8002b58: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002b5c: 2b00 cmp r3, #0
|
|
8002b5e: da0f bge.n 8002b80 <HAL_PCD_EP_Open+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002b60: 78fb ldrb r3, [r7, #3]
|
|
8002b62: f003 020f and.w r2, r3, #15
|
|
8002b66: 4613 mov r3, r2
|
|
8002b68: 00db lsls r3, r3, #3
|
|
8002b6a: 4413 add r3, r2
|
|
8002b6c: 009b lsls r3, r3, #2
|
|
8002b6e: 3310 adds r3, #16
|
|
8002b70: 687a ldr r2, [r7, #4]
|
|
8002b72: 4413 add r3, r2
|
|
8002b74: 3304 adds r3, #4
|
|
8002b76: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8002b78: 68fb ldr r3, [r7, #12]
|
|
8002b7a: 2201 movs r2, #1
|
|
8002b7c: 705a strb r2, [r3, #1]
|
|
8002b7e: e00f b.n 8002ba0 <HAL_PCD_EP_Open+0x66>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002b80: 78fb ldrb r3, [r7, #3]
|
|
8002b82: f003 020f and.w r2, r3, #15
|
|
8002b86: 4613 mov r3, r2
|
|
8002b88: 00db lsls r3, r3, #3
|
|
8002b8a: 4413 add r3, r2
|
|
8002b8c: 009b lsls r3, r3, #2
|
|
8002b8e: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002b92: 687a ldr r2, [r7, #4]
|
|
8002b94: 4413 add r3, r2
|
|
8002b96: 3304 adds r3, #4
|
|
8002b98: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8002b9a: 68fb ldr r3, [r7, #12]
|
|
8002b9c: 2200 movs r2, #0
|
|
8002b9e: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002ba0: 78fb ldrb r3, [r7, #3]
|
|
8002ba2: f003 030f and.w r3, r3, #15
|
|
8002ba6: b2da uxtb r2, r3
|
|
8002ba8: 68fb ldr r3, [r7, #12]
|
|
8002baa: 701a strb r2, [r3, #0]
|
|
ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
|
|
8002bac: 883b ldrh r3, [r7, #0]
|
|
8002bae: f3c3 020a ubfx r2, r3, #0, #11
|
|
8002bb2: 68fb ldr r3, [r7, #12]
|
|
8002bb4: 609a str r2, [r3, #8]
|
|
ep->type = ep_type;
|
|
8002bb6: 68fb ldr r3, [r7, #12]
|
|
8002bb8: 78ba ldrb r2, [r7, #2]
|
|
8002bba: 711a strb r2, [r3, #4]
|
|
|
|
if (ep->is_in != 0U)
|
|
8002bbc: 68fb ldr r3, [r7, #12]
|
|
8002bbe: 785b ldrb r3, [r3, #1]
|
|
8002bc0: 2b00 cmp r3, #0
|
|
8002bc2: d004 beq.n 8002bce <HAL_PCD_EP_Open+0x94>
|
|
{
|
|
/* Assign a Tx FIFO */
|
|
ep->tx_fifo_num = ep->num;
|
|
8002bc4: 68fb ldr r3, [r7, #12]
|
|
8002bc6: 781b ldrb r3, [r3, #0]
|
|
8002bc8: 461a mov r2, r3
|
|
8002bca: 68fb ldr r3, [r7, #12]
|
|
8002bcc: 835a strh r2, [r3, #26]
|
|
}
|
|
|
|
/* Set initial data PID. */
|
|
if (ep_type == EP_TYPE_BULK)
|
|
8002bce: 78bb ldrb r3, [r7, #2]
|
|
8002bd0: 2b02 cmp r3, #2
|
|
8002bd2: d102 bne.n 8002bda <HAL_PCD_EP_Open+0xa0>
|
|
{
|
|
ep->data_pid_start = 0U;
|
|
8002bd4: 68fb ldr r3, [r7, #12]
|
|
8002bd6: 2200 movs r2, #0
|
|
8002bd8: 715a strb r2, [r3, #5]
|
|
}
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8002bda: 687b ldr r3, [r7, #4]
|
|
8002bdc: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002be0: 2b01 cmp r3, #1
|
|
8002be2: d101 bne.n 8002be8 <HAL_PCD_EP_Open+0xae>
|
|
8002be4: 2302 movs r3, #2
|
|
8002be6: e00e b.n 8002c06 <HAL_PCD_EP_Open+0xcc>
|
|
8002be8: 687b ldr r3, [r7, #4]
|
|
8002bea: 2201 movs r2, #1
|
|
8002bec: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
|
|
8002bf0: 687b ldr r3, [r7, #4]
|
|
8002bf2: 681b ldr r3, [r3, #0]
|
|
8002bf4: 68f9 ldr r1, [r7, #12]
|
|
8002bf6: 4618 mov r0, r3
|
|
8002bf8: f003 fab2 bl 8006160 <USB_ActivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002bfc: 687b ldr r3, [r7, #4]
|
|
8002bfe: 2200 movs r2, #0
|
|
8002c00: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return ret;
|
|
8002c04: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
8002c06: 4618 mov r0, r3
|
|
8002c08: 3710 adds r7, #16
|
|
8002c0a: 46bd mov sp, r7
|
|
8002c0c: bd80 pop {r7, pc}
|
|
|
|
08002c0e <HAL_PCD_EP_Close>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8002c0e: b580 push {r7, lr}
|
|
8002c10: b084 sub sp, #16
|
|
8002c12: af00 add r7, sp, #0
|
|
8002c14: 6078 str r0, [r7, #4]
|
|
8002c16: 460b mov r3, r1
|
|
8002c18: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8002c1a: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002c1e: 2b00 cmp r3, #0
|
|
8002c20: da0f bge.n 8002c42 <HAL_PCD_EP_Close+0x34>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002c22: 78fb ldrb r3, [r7, #3]
|
|
8002c24: f003 020f and.w r2, r3, #15
|
|
8002c28: 4613 mov r3, r2
|
|
8002c2a: 00db lsls r3, r3, #3
|
|
8002c2c: 4413 add r3, r2
|
|
8002c2e: 009b lsls r3, r3, #2
|
|
8002c30: 3310 adds r3, #16
|
|
8002c32: 687a ldr r2, [r7, #4]
|
|
8002c34: 4413 add r3, r2
|
|
8002c36: 3304 adds r3, #4
|
|
8002c38: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8002c3a: 68fb ldr r3, [r7, #12]
|
|
8002c3c: 2201 movs r2, #1
|
|
8002c3e: 705a strb r2, [r3, #1]
|
|
8002c40: e00f b.n 8002c62 <HAL_PCD_EP_Close+0x54>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002c42: 78fb ldrb r3, [r7, #3]
|
|
8002c44: f003 020f and.w r2, r3, #15
|
|
8002c48: 4613 mov r3, r2
|
|
8002c4a: 00db lsls r3, r3, #3
|
|
8002c4c: 4413 add r3, r2
|
|
8002c4e: 009b lsls r3, r3, #2
|
|
8002c50: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002c54: 687a ldr r2, [r7, #4]
|
|
8002c56: 4413 add r3, r2
|
|
8002c58: 3304 adds r3, #4
|
|
8002c5a: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8002c5c: 68fb ldr r3, [r7, #12]
|
|
8002c5e: 2200 movs r2, #0
|
|
8002c60: 705a strb r2, [r3, #1]
|
|
}
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002c62: 78fb ldrb r3, [r7, #3]
|
|
8002c64: f003 030f and.w r3, r3, #15
|
|
8002c68: b2da uxtb r2, r3
|
|
8002c6a: 68fb ldr r3, [r7, #12]
|
|
8002c6c: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8002c6e: 687b ldr r3, [r7, #4]
|
|
8002c70: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002c74: 2b01 cmp r3, #1
|
|
8002c76: d101 bne.n 8002c7c <HAL_PCD_EP_Close+0x6e>
|
|
8002c78: 2302 movs r3, #2
|
|
8002c7a: e00e b.n 8002c9a <HAL_PCD_EP_Close+0x8c>
|
|
8002c7c: 687b ldr r3, [r7, #4]
|
|
8002c7e: 2201 movs r2, #1
|
|
8002c80: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
|
|
8002c84: 687b ldr r3, [r7, #4]
|
|
8002c86: 681b ldr r3, [r3, #0]
|
|
8002c88: 68f9 ldr r1, [r7, #12]
|
|
8002c8a: 4618 mov r0, r3
|
|
8002c8c: f003 faf0 bl 8006270 <USB_DeactivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002c90: 687b ldr r3, [r7, #4]
|
|
8002c92: 2200 movs r2, #0
|
|
8002c94: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
return HAL_OK;
|
|
8002c98: 2300 movs r3, #0
|
|
}
|
|
8002c9a: 4618 mov r0, r3
|
|
8002c9c: 3710 adds r7, #16
|
|
8002c9e: 46bd mov sp, r7
|
|
8002ca0: bd80 pop {r7, pc}
|
|
|
|
08002ca2 <HAL_PCD_EP_Receive>:
|
|
* @param pBuf pointer to the reception buffer
|
|
* @param len amount of data to be received
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
8002ca2: b580 push {r7, lr}
|
|
8002ca4: b086 sub sp, #24
|
|
8002ca6: af00 add r7, sp, #0
|
|
8002ca8: 60f8 str r0, [r7, #12]
|
|
8002caa: 607a str r2, [r7, #4]
|
|
8002cac: 603b str r3, [r7, #0]
|
|
8002cae: 460b mov r3, r1
|
|
8002cb0: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002cb2: 7afb ldrb r3, [r7, #11]
|
|
8002cb4: f003 020f and.w r2, r3, #15
|
|
8002cb8: 4613 mov r3, r2
|
|
8002cba: 00db lsls r3, r3, #3
|
|
8002cbc: 4413 add r3, r2
|
|
8002cbe: 009b lsls r3, r3, #2
|
|
8002cc0: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002cc4: 68fa ldr r2, [r7, #12]
|
|
8002cc6: 4413 add r3, r2
|
|
8002cc8: 3304 adds r3, #4
|
|
8002cca: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
8002ccc: 697b ldr r3, [r7, #20]
|
|
8002cce: 687a ldr r2, [r7, #4]
|
|
8002cd0: 60da str r2, [r3, #12]
|
|
ep->xfer_len = len;
|
|
8002cd2: 697b ldr r3, [r7, #20]
|
|
8002cd4: 683a ldr r2, [r7, #0]
|
|
8002cd6: 611a str r2, [r3, #16]
|
|
ep->xfer_count = 0U;
|
|
8002cd8: 697b ldr r3, [r7, #20]
|
|
8002cda: 2200 movs r2, #0
|
|
8002cdc: 615a str r2, [r3, #20]
|
|
ep->is_in = 0U;
|
|
8002cde: 697b ldr r3, [r7, #20]
|
|
8002ce0: 2200 movs r2, #0
|
|
8002ce2: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002ce4: 7afb ldrb r3, [r7, #11]
|
|
8002ce6: f003 030f and.w r3, r3, #15
|
|
8002cea: b2da uxtb r2, r3
|
|
8002cec: 697b ldr r3, [r7, #20]
|
|
8002cee: 701a strb r2, [r3, #0]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8002cf0: 68fb ldr r3, [r7, #12]
|
|
8002cf2: 799b ldrb r3, [r3, #6]
|
|
8002cf4: 2b01 cmp r3, #1
|
|
8002cf6: d102 bne.n 8002cfe <HAL_PCD_EP_Receive+0x5c>
|
|
{
|
|
ep->dma_addr = (uint32_t)pBuf;
|
|
8002cf8: 687a ldr r2, [r7, #4]
|
|
8002cfa: 697b ldr r3, [r7, #20]
|
|
8002cfc: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
|
|
8002cfe: 68fb ldr r3, [r7, #12]
|
|
8002d00: 6818 ldr r0, [r3, #0]
|
|
8002d02: 68fb ldr r3, [r7, #12]
|
|
8002d04: 799b ldrb r3, [r3, #6]
|
|
8002d06: 461a mov r2, r3
|
|
8002d08: 6979 ldr r1, [r7, #20]
|
|
8002d0a: f003 fb8d bl 8006428 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
8002d0e: 2300 movs r3, #0
|
|
}
|
|
8002d10: 4618 mov r0, r3
|
|
8002d12: 3718 adds r7, #24
|
|
8002d14: 46bd mov sp, r7
|
|
8002d16: bd80 pop {r7, pc}
|
|
|
|
08002d18 <HAL_PCD_EP_Transmit>:
|
|
* @param pBuf pointer to the transmission buffer
|
|
* @param len amount of data to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
8002d18: b580 push {r7, lr}
|
|
8002d1a: b086 sub sp, #24
|
|
8002d1c: af00 add r7, sp, #0
|
|
8002d1e: 60f8 str r0, [r7, #12]
|
|
8002d20: 607a str r2, [r7, #4]
|
|
8002d22: 603b str r3, [r7, #0]
|
|
8002d24: 460b mov r3, r1
|
|
8002d26: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002d28: 7afb ldrb r3, [r7, #11]
|
|
8002d2a: f003 020f and.w r2, r3, #15
|
|
8002d2e: 4613 mov r3, r2
|
|
8002d30: 00db lsls r3, r3, #3
|
|
8002d32: 4413 add r3, r2
|
|
8002d34: 009b lsls r3, r3, #2
|
|
8002d36: 3310 adds r3, #16
|
|
8002d38: 68fa ldr r2, [r7, #12]
|
|
8002d3a: 4413 add r3, r2
|
|
8002d3c: 3304 adds r3, #4
|
|
8002d3e: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
8002d40: 697b ldr r3, [r7, #20]
|
|
8002d42: 687a ldr r2, [r7, #4]
|
|
8002d44: 60da str r2, [r3, #12]
|
|
ep->xfer_len = len;
|
|
8002d46: 697b ldr r3, [r7, #20]
|
|
8002d48: 683a ldr r2, [r7, #0]
|
|
8002d4a: 611a str r2, [r3, #16]
|
|
ep->xfer_count = 0U;
|
|
8002d4c: 697b ldr r3, [r7, #20]
|
|
8002d4e: 2200 movs r2, #0
|
|
8002d50: 615a str r2, [r3, #20]
|
|
ep->is_in = 1U;
|
|
8002d52: 697b ldr r3, [r7, #20]
|
|
8002d54: 2201 movs r2, #1
|
|
8002d56: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002d58: 7afb ldrb r3, [r7, #11]
|
|
8002d5a: f003 030f and.w r3, r3, #15
|
|
8002d5e: b2da uxtb r2, r3
|
|
8002d60: 697b ldr r3, [r7, #20]
|
|
8002d62: 701a strb r2, [r3, #0]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8002d64: 68fb ldr r3, [r7, #12]
|
|
8002d66: 799b ldrb r3, [r3, #6]
|
|
8002d68: 2b01 cmp r3, #1
|
|
8002d6a: d102 bne.n 8002d72 <HAL_PCD_EP_Transmit+0x5a>
|
|
{
|
|
ep->dma_addr = (uint32_t)pBuf;
|
|
8002d6c: 687a ldr r2, [r7, #4]
|
|
8002d6e: 697b ldr r3, [r7, #20]
|
|
8002d70: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
|
|
8002d72: 68fb ldr r3, [r7, #12]
|
|
8002d74: 6818 ldr r0, [r3, #0]
|
|
8002d76: 68fb ldr r3, [r7, #12]
|
|
8002d78: 799b ldrb r3, [r3, #6]
|
|
8002d7a: 461a mov r2, r3
|
|
8002d7c: 6979 ldr r1, [r7, #20]
|
|
8002d7e: f003 fb53 bl 8006428 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
8002d82: 2300 movs r3, #0
|
|
}
|
|
8002d84: 4618 mov r0, r3
|
|
8002d86: 3718 adds r7, #24
|
|
8002d88: 46bd mov sp, r7
|
|
8002d8a: bd80 pop {r7, pc}
|
|
|
|
08002d8c <HAL_PCD_EP_SetStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8002d8c: b580 push {r7, lr}
|
|
8002d8e: b084 sub sp, #16
|
|
8002d90: af00 add r7, sp, #0
|
|
8002d92: 6078 str r0, [r7, #4]
|
|
8002d94: 460b mov r3, r1
|
|
8002d96: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
|
|
8002d98: 78fb ldrb r3, [r7, #3]
|
|
8002d9a: f003 030f and.w r3, r3, #15
|
|
8002d9e: 687a ldr r2, [r7, #4]
|
|
8002da0: 7912 ldrb r2, [r2, #4]
|
|
8002da2: 4293 cmp r3, r2
|
|
8002da4: d901 bls.n 8002daa <HAL_PCD_EP_SetStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8002da6: 2301 movs r3, #1
|
|
8002da8: e04f b.n 8002e4a <HAL_PCD_EP_SetStall+0xbe>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8002daa: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002dae: 2b00 cmp r3, #0
|
|
8002db0: da0f bge.n 8002dd2 <HAL_PCD_EP_SetStall+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002db2: 78fb ldrb r3, [r7, #3]
|
|
8002db4: f003 020f and.w r2, r3, #15
|
|
8002db8: 4613 mov r3, r2
|
|
8002dba: 00db lsls r3, r3, #3
|
|
8002dbc: 4413 add r3, r2
|
|
8002dbe: 009b lsls r3, r3, #2
|
|
8002dc0: 3310 adds r3, #16
|
|
8002dc2: 687a ldr r2, [r7, #4]
|
|
8002dc4: 4413 add r3, r2
|
|
8002dc6: 3304 adds r3, #4
|
|
8002dc8: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8002dca: 68fb ldr r3, [r7, #12]
|
|
8002dcc: 2201 movs r2, #1
|
|
8002dce: 705a strb r2, [r3, #1]
|
|
8002dd0: e00d b.n 8002dee <HAL_PCD_EP_SetStall+0x62>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr];
|
|
8002dd2: 78fa ldrb r2, [r7, #3]
|
|
8002dd4: 4613 mov r3, r2
|
|
8002dd6: 00db lsls r3, r3, #3
|
|
8002dd8: 4413 add r3, r2
|
|
8002dda: 009b lsls r3, r3, #2
|
|
8002ddc: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002de0: 687a ldr r2, [r7, #4]
|
|
8002de2: 4413 add r3, r2
|
|
8002de4: 3304 adds r3, #4
|
|
8002de6: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8002de8: 68fb ldr r3, [r7, #12]
|
|
8002dea: 2200 movs r2, #0
|
|
8002dec: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 1U;
|
|
8002dee: 68fb ldr r3, [r7, #12]
|
|
8002df0: 2201 movs r2, #1
|
|
8002df2: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002df4: 78fb ldrb r3, [r7, #3]
|
|
8002df6: f003 030f and.w r3, r3, #15
|
|
8002dfa: b2da uxtb r2, r3
|
|
8002dfc: 68fb ldr r3, [r7, #12]
|
|
8002dfe: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8002e00: 687b ldr r3, [r7, #4]
|
|
8002e02: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002e06: 2b01 cmp r3, #1
|
|
8002e08: d101 bne.n 8002e0e <HAL_PCD_EP_SetStall+0x82>
|
|
8002e0a: 2302 movs r3, #2
|
|
8002e0c: e01d b.n 8002e4a <HAL_PCD_EP_SetStall+0xbe>
|
|
8002e0e: 687b ldr r3, [r7, #4]
|
|
8002e10: 2201 movs r2, #1
|
|
8002e12: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
(void)USB_EPSetStall(hpcd->Instance, ep);
|
|
8002e16: 687b ldr r3, [r7, #4]
|
|
8002e18: 681b ldr r3, [r3, #0]
|
|
8002e1a: 68f9 ldr r1, [r7, #12]
|
|
8002e1c: 4618 mov r0, r3
|
|
8002e1e: f003 fee1 bl 8006be4 <USB_EPSetStall>
|
|
|
|
if ((ep_addr & EP_ADDR_MSK) == 0U)
|
|
8002e22: 78fb ldrb r3, [r7, #3]
|
|
8002e24: f003 030f and.w r3, r3, #15
|
|
8002e28: 2b00 cmp r3, #0
|
|
8002e2a: d109 bne.n 8002e40 <HAL_PCD_EP_SetStall+0xb4>
|
|
{
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
|
|
8002e2c: 687b ldr r3, [r7, #4]
|
|
8002e2e: 6818 ldr r0, [r3, #0]
|
|
8002e30: 687b ldr r3, [r7, #4]
|
|
8002e32: 7999 ldrb r1, [r3, #6]
|
|
8002e34: 687b ldr r3, [r7, #4]
|
|
8002e36: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8002e3a: 461a mov r2, r3
|
|
8002e3c: f004 f8d2 bl 8006fe4 <USB_EP0_OutStart>
|
|
}
|
|
|
|
__HAL_UNLOCK(hpcd);
|
|
8002e40: 687b ldr r3, [r7, #4]
|
|
8002e42: 2200 movs r2, #0
|
|
8002e44: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8002e48: 2300 movs r3, #0
|
|
}
|
|
8002e4a: 4618 mov r0, r3
|
|
8002e4c: 3710 adds r7, #16
|
|
8002e4e: 46bd mov sp, r7
|
|
8002e50: bd80 pop {r7, pc}
|
|
|
|
08002e52 <HAL_PCD_EP_ClrStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8002e52: b580 push {r7, lr}
|
|
8002e54: b084 sub sp, #16
|
|
8002e56: af00 add r7, sp, #0
|
|
8002e58: 6078 str r0, [r7, #4]
|
|
8002e5a: 460b mov r3, r1
|
|
8002e5c: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
|
|
8002e5e: 78fb ldrb r3, [r7, #3]
|
|
8002e60: f003 030f and.w r3, r3, #15
|
|
8002e64: 687a ldr r2, [r7, #4]
|
|
8002e66: 7912 ldrb r2, [r2, #4]
|
|
8002e68: 4293 cmp r3, r2
|
|
8002e6a: d901 bls.n 8002e70 <HAL_PCD_EP_ClrStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8002e6c: 2301 movs r3, #1
|
|
8002e6e: e042 b.n 8002ef6 <HAL_PCD_EP_ClrStall+0xa4>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8002e70: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002e74: 2b00 cmp r3, #0
|
|
8002e76: da0f bge.n 8002e98 <HAL_PCD_EP_ClrStall+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002e78: 78fb ldrb r3, [r7, #3]
|
|
8002e7a: f003 020f and.w r2, r3, #15
|
|
8002e7e: 4613 mov r3, r2
|
|
8002e80: 00db lsls r3, r3, #3
|
|
8002e82: 4413 add r3, r2
|
|
8002e84: 009b lsls r3, r3, #2
|
|
8002e86: 3310 adds r3, #16
|
|
8002e88: 687a ldr r2, [r7, #4]
|
|
8002e8a: 4413 add r3, r2
|
|
8002e8c: 3304 adds r3, #4
|
|
8002e8e: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8002e90: 68fb ldr r3, [r7, #12]
|
|
8002e92: 2201 movs r2, #1
|
|
8002e94: 705a strb r2, [r3, #1]
|
|
8002e96: e00f b.n 8002eb8 <HAL_PCD_EP_ClrStall+0x66>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002e98: 78fb ldrb r3, [r7, #3]
|
|
8002e9a: f003 020f and.w r2, r3, #15
|
|
8002e9e: 4613 mov r3, r2
|
|
8002ea0: 00db lsls r3, r3, #3
|
|
8002ea2: 4413 add r3, r2
|
|
8002ea4: 009b lsls r3, r3, #2
|
|
8002ea6: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002eaa: 687a ldr r2, [r7, #4]
|
|
8002eac: 4413 add r3, r2
|
|
8002eae: 3304 adds r3, #4
|
|
8002eb0: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8002eb2: 68fb ldr r3, [r7, #12]
|
|
8002eb4: 2200 movs r2, #0
|
|
8002eb6: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 0U;
|
|
8002eb8: 68fb ldr r3, [r7, #12]
|
|
8002eba: 2200 movs r2, #0
|
|
8002ebc: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002ebe: 78fb ldrb r3, [r7, #3]
|
|
8002ec0: f003 030f and.w r3, r3, #15
|
|
8002ec4: b2da uxtb r2, r3
|
|
8002ec6: 68fb ldr r3, [r7, #12]
|
|
8002ec8: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8002eca: 687b ldr r3, [r7, #4]
|
|
8002ecc: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002ed0: 2b01 cmp r3, #1
|
|
8002ed2: d101 bne.n 8002ed8 <HAL_PCD_EP_ClrStall+0x86>
|
|
8002ed4: 2302 movs r3, #2
|
|
8002ed6: e00e b.n 8002ef6 <HAL_PCD_EP_ClrStall+0xa4>
|
|
8002ed8: 687b ldr r3, [r7, #4]
|
|
8002eda: 2201 movs r2, #1
|
|
8002edc: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_EPClearStall(hpcd->Instance, ep);
|
|
8002ee0: 687b ldr r3, [r7, #4]
|
|
8002ee2: 681b ldr r3, [r3, #0]
|
|
8002ee4: 68f9 ldr r1, [r7, #12]
|
|
8002ee6: 4618 mov r0, r3
|
|
8002ee8: f003 feea bl 8006cc0 <USB_EPClearStall>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002eec: 687b ldr r3, [r7, #4]
|
|
8002eee: 2200 movs r2, #0
|
|
8002ef0: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8002ef4: 2300 movs r3, #0
|
|
}
|
|
8002ef6: 4618 mov r0, r3
|
|
8002ef8: 3710 adds r7, #16
|
|
8002efa: 46bd mov sp, r7
|
|
8002efc: bd80 pop {r7, pc}
|
|
|
|
08002efe <HAL_PCD_EP_Abort>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8002efe: b580 push {r7, lr}
|
|
8002f00: b084 sub sp, #16
|
|
8002f02: af00 add r7, sp, #0
|
|
8002f04: 6078 str r0, [r7, #4]
|
|
8002f06: 460b mov r3, r1
|
|
8002f08: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef ret;
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8002f0a: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002f0e: 2b00 cmp r3, #0
|
|
8002f10: da0c bge.n 8002f2c <HAL_PCD_EP_Abort+0x2e>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002f12: 78fb ldrb r3, [r7, #3]
|
|
8002f14: f003 020f and.w r2, r3, #15
|
|
8002f18: 4613 mov r3, r2
|
|
8002f1a: 00db lsls r3, r3, #3
|
|
8002f1c: 4413 add r3, r2
|
|
8002f1e: 009b lsls r3, r3, #2
|
|
8002f20: 3310 adds r3, #16
|
|
8002f22: 687a ldr r2, [r7, #4]
|
|
8002f24: 4413 add r3, r2
|
|
8002f26: 3304 adds r3, #4
|
|
8002f28: 60fb str r3, [r7, #12]
|
|
8002f2a: e00c b.n 8002f46 <HAL_PCD_EP_Abort+0x48>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002f2c: 78fb ldrb r3, [r7, #3]
|
|
8002f2e: f003 020f and.w r2, r3, #15
|
|
8002f32: 4613 mov r3, r2
|
|
8002f34: 00db lsls r3, r3, #3
|
|
8002f36: 4413 add r3, r2
|
|
8002f38: 009b lsls r3, r3, #2
|
|
8002f3a: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002f3e: 687a ldr r2, [r7, #4]
|
|
8002f40: 4413 add r3, r2
|
|
8002f42: 3304 adds r3, #4
|
|
8002f44: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Stop Xfer */
|
|
ret = USB_EPStopXfer(hpcd->Instance, ep);
|
|
8002f46: 687b ldr r3, [r7, #4]
|
|
8002f48: 681b ldr r3, [r3, #0]
|
|
8002f4a: 68f9 ldr r1, [r7, #12]
|
|
8002f4c: 4618 mov r0, r3
|
|
8002f4e: f003 fd09 bl 8006964 <USB_EPStopXfer>
|
|
8002f52: 4603 mov r3, r0
|
|
8002f54: 72fb strb r3, [r7, #11]
|
|
|
|
return ret;
|
|
8002f56: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
8002f58: 4618 mov r0, r3
|
|
8002f5a: 3710 adds r7, #16
|
|
8002f5c: 46bd mov sp, r7
|
|
8002f5e: bd80 pop {r7, pc}
|
|
|
|
08002f60 <PCD_WriteEmptyTxFifo>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8002f60: b580 push {r7, lr}
|
|
8002f62: b08a sub sp, #40 @ 0x28
|
|
8002f64: af02 add r7, sp, #8
|
|
8002f66: 6078 str r0, [r7, #4]
|
|
8002f68: 6039 str r1, [r7, #0]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8002f6a: 687b ldr r3, [r7, #4]
|
|
8002f6c: 681b ldr r3, [r3, #0]
|
|
8002f6e: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8002f70: 697b ldr r3, [r7, #20]
|
|
8002f72: 613b str r3, [r7, #16]
|
|
USB_OTG_EPTypeDef *ep;
|
|
uint32_t len;
|
|
uint32_t len32b;
|
|
uint32_t fifoemptymsk;
|
|
|
|
ep = &hpcd->IN_ep[epnum];
|
|
8002f74: 683a ldr r2, [r7, #0]
|
|
8002f76: 4613 mov r3, r2
|
|
8002f78: 00db lsls r3, r3, #3
|
|
8002f7a: 4413 add r3, r2
|
|
8002f7c: 009b lsls r3, r3, #2
|
|
8002f7e: 3310 adds r3, #16
|
|
8002f80: 687a ldr r2, [r7, #4]
|
|
8002f82: 4413 add r3, r2
|
|
8002f84: 3304 adds r3, #4
|
|
8002f86: 60fb str r3, [r7, #12]
|
|
|
|
if (ep->xfer_count > ep->xfer_len)
|
|
8002f88: 68fb ldr r3, [r7, #12]
|
|
8002f8a: 695a ldr r2, [r3, #20]
|
|
8002f8c: 68fb ldr r3, [r7, #12]
|
|
8002f8e: 691b ldr r3, [r3, #16]
|
|
8002f90: 429a cmp r2, r3
|
|
8002f92: d901 bls.n 8002f98 <PCD_WriteEmptyTxFifo+0x38>
|
|
{
|
|
return HAL_ERROR;
|
|
8002f94: 2301 movs r3, #1
|
|
8002f96: e06b b.n 8003070 <PCD_WriteEmptyTxFifo+0x110>
|
|
}
|
|
|
|
len = ep->xfer_len - ep->xfer_count;
|
|
8002f98: 68fb ldr r3, [r7, #12]
|
|
8002f9a: 691a ldr r2, [r3, #16]
|
|
8002f9c: 68fb ldr r3, [r7, #12]
|
|
8002f9e: 695b ldr r3, [r3, #20]
|
|
8002fa0: 1ad3 subs r3, r2, r3
|
|
8002fa2: 61fb str r3, [r7, #28]
|
|
|
|
if (len > ep->maxpacket)
|
|
8002fa4: 68fb ldr r3, [r7, #12]
|
|
8002fa6: 689b ldr r3, [r3, #8]
|
|
8002fa8: 69fa ldr r2, [r7, #28]
|
|
8002faa: 429a cmp r2, r3
|
|
8002fac: d902 bls.n 8002fb4 <PCD_WriteEmptyTxFifo+0x54>
|
|
{
|
|
len = ep->maxpacket;
|
|
8002fae: 68fb ldr r3, [r7, #12]
|
|
8002fb0: 689b ldr r3, [r3, #8]
|
|
8002fb2: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
len32b = (len + 3U) / 4U;
|
|
8002fb4: 69fb ldr r3, [r7, #28]
|
|
8002fb6: 3303 adds r3, #3
|
|
8002fb8: 089b lsrs r3, r3, #2
|
|
8002fba: 61bb str r3, [r7, #24]
|
|
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8002fbc: e02a b.n 8003014 <PCD_WriteEmptyTxFifo+0xb4>
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
{
|
|
/* Write the FIFO */
|
|
len = ep->xfer_len - ep->xfer_count;
|
|
8002fbe: 68fb ldr r3, [r7, #12]
|
|
8002fc0: 691a ldr r2, [r3, #16]
|
|
8002fc2: 68fb ldr r3, [r7, #12]
|
|
8002fc4: 695b ldr r3, [r3, #20]
|
|
8002fc6: 1ad3 subs r3, r2, r3
|
|
8002fc8: 61fb str r3, [r7, #28]
|
|
|
|
if (len > ep->maxpacket)
|
|
8002fca: 68fb ldr r3, [r7, #12]
|
|
8002fcc: 689b ldr r3, [r3, #8]
|
|
8002fce: 69fa ldr r2, [r7, #28]
|
|
8002fd0: 429a cmp r2, r3
|
|
8002fd2: d902 bls.n 8002fda <PCD_WriteEmptyTxFifo+0x7a>
|
|
{
|
|
len = ep->maxpacket;
|
|
8002fd4: 68fb ldr r3, [r7, #12]
|
|
8002fd6: 689b ldr r3, [r3, #8]
|
|
8002fd8: 61fb str r3, [r7, #28]
|
|
}
|
|
len32b = (len + 3U) / 4U;
|
|
8002fda: 69fb ldr r3, [r7, #28]
|
|
8002fdc: 3303 adds r3, #3
|
|
8002fde: 089b lsrs r3, r3, #2
|
|
8002fe0: 61bb str r3, [r7, #24]
|
|
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
|
|
8002fe2: 68fb ldr r3, [r7, #12]
|
|
8002fe4: 68d9 ldr r1, [r3, #12]
|
|
8002fe6: 683b ldr r3, [r7, #0]
|
|
8002fe8: b2da uxtb r2, r3
|
|
8002fea: 69fb ldr r3, [r7, #28]
|
|
8002fec: b298 uxth r0, r3
|
|
(uint8_t)hpcd->Init.dma_enable);
|
|
8002fee: 687b ldr r3, [r7, #4]
|
|
8002ff0: 799b ldrb r3, [r3, #6]
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
|
|
8002ff2: 9300 str r3, [sp, #0]
|
|
8002ff4: 4603 mov r3, r0
|
|
8002ff6: 6978 ldr r0, [r7, #20]
|
|
8002ff8: f003 fd5e bl 8006ab8 <USB_WritePacket>
|
|
|
|
ep->xfer_buff += len;
|
|
8002ffc: 68fb ldr r3, [r7, #12]
|
|
8002ffe: 68da ldr r2, [r3, #12]
|
|
8003000: 69fb ldr r3, [r7, #28]
|
|
8003002: 441a add r2, r3
|
|
8003004: 68fb ldr r3, [r7, #12]
|
|
8003006: 60da str r2, [r3, #12]
|
|
ep->xfer_count += len;
|
|
8003008: 68fb ldr r3, [r7, #12]
|
|
800300a: 695a ldr r2, [r3, #20]
|
|
800300c: 69fb ldr r3, [r7, #28]
|
|
800300e: 441a add r2, r3
|
|
8003010: 68fb ldr r3, [r7, #12]
|
|
8003012: 615a str r2, [r3, #20]
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8003014: 683b ldr r3, [r7, #0]
|
|
8003016: 015a lsls r2, r3, #5
|
|
8003018: 693b ldr r3, [r7, #16]
|
|
800301a: 4413 add r3, r2
|
|
800301c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8003020: 699b ldr r3, [r3, #24]
|
|
8003022: b29b uxth r3, r3
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
8003024: 69ba ldr r2, [r7, #24]
|
|
8003026: 429a cmp r2, r3
|
|
8003028: d809 bhi.n 800303e <PCD_WriteEmptyTxFifo+0xde>
|
|
800302a: 68fb ldr r3, [r7, #12]
|
|
800302c: 695a ldr r2, [r3, #20]
|
|
800302e: 68fb ldr r3, [r7, #12]
|
|
8003030: 691b ldr r3, [r3, #16]
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8003032: 429a cmp r2, r3
|
|
8003034: d203 bcs.n 800303e <PCD_WriteEmptyTxFifo+0xde>
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
8003036: 68fb ldr r3, [r7, #12]
|
|
8003038: 691b ldr r3, [r3, #16]
|
|
800303a: 2b00 cmp r3, #0
|
|
800303c: d1bf bne.n 8002fbe <PCD_WriteEmptyTxFifo+0x5e>
|
|
}
|
|
|
|
if (ep->xfer_len <= ep->xfer_count)
|
|
800303e: 68fb ldr r3, [r7, #12]
|
|
8003040: 691a ldr r2, [r3, #16]
|
|
8003042: 68fb ldr r3, [r7, #12]
|
|
8003044: 695b ldr r3, [r3, #20]
|
|
8003046: 429a cmp r2, r3
|
|
8003048: d811 bhi.n 800306e <PCD_WriteEmptyTxFifo+0x10e>
|
|
{
|
|
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
|
|
800304a: 683b ldr r3, [r7, #0]
|
|
800304c: f003 030f and.w r3, r3, #15
|
|
8003050: 2201 movs r2, #1
|
|
8003052: fa02 f303 lsl.w r3, r2, r3
|
|
8003056: 60bb str r3, [r7, #8]
|
|
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
|
|
8003058: 693b ldr r3, [r7, #16]
|
|
800305a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800305e: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8003060: 68bb ldr r3, [r7, #8]
|
|
8003062: 43db mvns r3, r3
|
|
8003064: 6939 ldr r1, [r7, #16]
|
|
8003066: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
800306a: 4013 ands r3, r2
|
|
800306c: 634b str r3, [r1, #52] @ 0x34
|
|
}
|
|
|
|
return HAL_OK;
|
|
800306e: 2300 movs r3, #0
|
|
}
|
|
8003070: 4618 mov r0, r3
|
|
8003072: 3720 adds r7, #32
|
|
8003074: 46bd mov sp, r7
|
|
8003076: bd80 pop {r7, pc}
|
|
|
|
08003078 <PCD_EP_OutXfrComplete_int>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8003078: b580 push {r7, lr}
|
|
800307a: b088 sub sp, #32
|
|
800307c: af00 add r7, sp, #0
|
|
800307e: 6078 str r0, [r7, #4]
|
|
8003080: 6039 str r1, [r7, #0]
|
|
USB_OTG_EPTypeDef *ep;
|
|
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8003082: 687b ldr r3, [r7, #4]
|
|
8003084: 681b ldr r3, [r3, #0]
|
|
8003086: 61fb str r3, [r7, #28]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8003088: 69fb ldr r3, [r7, #28]
|
|
800308a: 61bb str r3, [r7, #24]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
800308c: 69fb ldr r3, [r7, #28]
|
|
800308e: 333c adds r3, #60 @ 0x3c
|
|
8003090: 3304 adds r3, #4
|
|
8003092: 681b ldr r3, [r3, #0]
|
|
8003094: 617b str r3, [r7, #20]
|
|
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
|
|
8003096: 683b ldr r3, [r7, #0]
|
|
8003098: 015a lsls r2, r3, #5
|
|
800309a: 69bb ldr r3, [r7, #24]
|
|
800309c: 4413 add r3, r2
|
|
800309e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80030a2: 689b ldr r3, [r3, #8]
|
|
80030a4: 613b str r3, [r7, #16]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
80030a6: 687b ldr r3, [r7, #4]
|
|
80030a8: 799b ldrb r3, [r3, #6]
|
|
80030aa: 2b01 cmp r3, #1
|
|
80030ac: d17b bne.n 80031a6 <PCD_EP_OutXfrComplete_int+0x12e>
|
|
{
|
|
if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
|
|
80030ae: 693b ldr r3, [r7, #16]
|
|
80030b0: f003 0308 and.w r3, r3, #8
|
|
80030b4: 2b00 cmp r3, #0
|
|
80030b6: d015 beq.n 80030e4 <PCD_EP_OutXfrComplete_int+0x6c>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
80030b8: 697b ldr r3, [r7, #20]
|
|
80030ba: 4a61 ldr r2, [pc, #388] @ (8003240 <PCD_EP_OutXfrComplete_int+0x1c8>)
|
|
80030bc: 4293 cmp r3, r2
|
|
80030be: f240 80b9 bls.w 8003234 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
80030c2: 693b ldr r3, [r7, #16]
|
|
80030c4: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
80030c8: 2b00 cmp r3, #0
|
|
80030ca: f000 80b3 beq.w 8003234 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
80030ce: 683b ldr r3, [r7, #0]
|
|
80030d0: 015a lsls r2, r3, #5
|
|
80030d2: 69bb ldr r3, [r7, #24]
|
|
80030d4: 4413 add r3, r2
|
|
80030d6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80030da: 461a mov r2, r3
|
|
80030dc: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
80030e0: 6093 str r3, [r2, #8]
|
|
80030e2: e0a7 b.n 8003234 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
}
|
|
else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
|
|
80030e4: 693b ldr r3, [r7, #16]
|
|
80030e6: f003 0320 and.w r3, r3, #32
|
|
80030ea: 2b00 cmp r3, #0
|
|
80030ec: d009 beq.n 8003102 <PCD_EP_OutXfrComplete_int+0x8a>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
80030ee: 683b ldr r3, [r7, #0]
|
|
80030f0: 015a lsls r2, r3, #5
|
|
80030f2: 69bb ldr r3, [r7, #24]
|
|
80030f4: 4413 add r3, r2
|
|
80030f6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80030fa: 461a mov r2, r3
|
|
80030fc: 2320 movs r3, #32
|
|
80030fe: 6093 str r3, [r2, #8]
|
|
8003100: e098 b.n 8003234 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
|
|
8003102: 693b ldr r3, [r7, #16]
|
|
8003104: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
8003108: 2b00 cmp r3, #0
|
|
800310a: f040 8093 bne.w 8003234 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
800310e: 697b ldr r3, [r7, #20]
|
|
8003110: 4a4b ldr r2, [pc, #300] @ (8003240 <PCD_EP_OutXfrComplete_int+0x1c8>)
|
|
8003112: 4293 cmp r3, r2
|
|
8003114: d90f bls.n 8003136 <PCD_EP_OutXfrComplete_int+0xbe>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
8003116: 693b ldr r3, [r7, #16]
|
|
8003118: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
800311c: 2b00 cmp r3, #0
|
|
800311e: d00a beq.n 8003136 <PCD_EP_OutXfrComplete_int+0xbe>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8003120: 683b ldr r3, [r7, #0]
|
|
8003122: 015a lsls r2, r3, #5
|
|
8003124: 69bb ldr r3, [r7, #24]
|
|
8003126: 4413 add r3, r2
|
|
8003128: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800312c: 461a mov r2, r3
|
|
800312e: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8003132: 6093 str r3, [r2, #8]
|
|
8003134: e07e b.n 8003234 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[epnum];
|
|
8003136: 683a ldr r2, [r7, #0]
|
|
8003138: 4613 mov r3, r2
|
|
800313a: 00db lsls r3, r3, #3
|
|
800313c: 4413 add r3, r2
|
|
800313e: 009b lsls r3, r3, #2
|
|
8003140: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003144: 687a ldr r2, [r7, #4]
|
|
8003146: 4413 add r3, r2
|
|
8003148: 3304 adds r3, #4
|
|
800314a: 60fb str r3, [r7, #12]
|
|
|
|
/* out data packet received over EP */
|
|
ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
|
|
800314c: 68fb ldr r3, [r7, #12]
|
|
800314e: 6a1a ldr r2, [r3, #32]
|
|
8003150: 683b ldr r3, [r7, #0]
|
|
8003152: 0159 lsls r1, r3, #5
|
|
8003154: 69bb ldr r3, [r7, #24]
|
|
8003156: 440b add r3, r1
|
|
8003158: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800315c: 691b ldr r3, [r3, #16]
|
|
800315e: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8003162: 1ad2 subs r2, r2, r3
|
|
8003164: 68fb ldr r3, [r7, #12]
|
|
8003166: 615a str r2, [r3, #20]
|
|
|
|
if (epnum == 0U)
|
|
8003168: 683b ldr r3, [r7, #0]
|
|
800316a: 2b00 cmp r3, #0
|
|
800316c: d114 bne.n 8003198 <PCD_EP_OutXfrComplete_int+0x120>
|
|
{
|
|
if (ep->xfer_len == 0U)
|
|
800316e: 68fb ldr r3, [r7, #12]
|
|
8003170: 691b ldr r3, [r3, #16]
|
|
8003172: 2b00 cmp r3, #0
|
|
8003174: d109 bne.n 800318a <PCD_EP_OutXfrComplete_int+0x112>
|
|
{
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
8003176: 687b ldr r3, [r7, #4]
|
|
8003178: 6818 ldr r0, [r3, #0]
|
|
800317a: 687b ldr r3, [r7, #4]
|
|
800317c: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8003180: 461a mov r2, r3
|
|
8003182: 2101 movs r1, #1
|
|
8003184: f003 ff2e bl 8006fe4 <USB_EP0_OutStart>
|
|
8003188: e006 b.n 8003198 <PCD_EP_OutXfrComplete_int+0x120>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_buff += ep->xfer_count;
|
|
800318a: 68fb ldr r3, [r7, #12]
|
|
800318c: 68da ldr r2, [r3, #12]
|
|
800318e: 68fb ldr r3, [r7, #12]
|
|
8003190: 695b ldr r3, [r3, #20]
|
|
8003192: 441a add r2, r3
|
|
8003194: 68fb ldr r3, [r7, #12]
|
|
8003196: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
8003198: 683b ldr r3, [r7, #0]
|
|
800319a: b2db uxtb r3, r3
|
|
800319c: 4619 mov r1, r3
|
|
800319e: 6878 ldr r0, [r7, #4]
|
|
80031a0: f005 ff10 bl 8008fc4 <HAL_PCD_DataOutStageCallback>
|
|
80031a4: e046 b.n 8003234 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
/* ... */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (gSNPSiD == USB_OTG_CORE_ID_310A)
|
|
80031a6: 697b ldr r3, [r7, #20]
|
|
80031a8: 4a26 ldr r2, [pc, #152] @ (8003244 <PCD_EP_OutXfrComplete_int+0x1cc>)
|
|
80031aa: 4293 cmp r3, r2
|
|
80031ac: d124 bne.n 80031f8 <PCD_EP_OutXfrComplete_int+0x180>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
|
|
80031ae: 693b ldr r3, [r7, #16]
|
|
80031b0: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80031b4: 2b00 cmp r3, #0
|
|
80031b6: d00a beq.n 80031ce <PCD_EP_OutXfrComplete_int+0x156>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
80031b8: 683b ldr r3, [r7, #0]
|
|
80031ba: 015a lsls r2, r3, #5
|
|
80031bc: 69bb ldr r3, [r7, #24]
|
|
80031be: 4413 add r3, r2
|
|
80031c0: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80031c4: 461a mov r2, r3
|
|
80031c6: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
80031ca: 6093 str r3, [r2, #8]
|
|
80031cc: e032 b.n 8003234 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else
|
|
{
|
|
if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
|
|
80031ce: 693b ldr r3, [r7, #16]
|
|
80031d0: f003 0320 and.w r3, r3, #32
|
|
80031d4: 2b00 cmp r3, #0
|
|
80031d6: d008 beq.n 80031ea <PCD_EP_OutXfrComplete_int+0x172>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
80031d8: 683b ldr r3, [r7, #0]
|
|
80031da: 015a lsls r2, r3, #5
|
|
80031dc: 69bb ldr r3, [r7, #24]
|
|
80031de: 4413 add r3, r2
|
|
80031e0: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80031e4: 461a mov r2, r3
|
|
80031e6: 2320 movs r3, #32
|
|
80031e8: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
80031ea: 683b ldr r3, [r7, #0]
|
|
80031ec: b2db uxtb r3, r3
|
|
80031ee: 4619 mov r1, r3
|
|
80031f0: 6878 ldr r0, [r7, #4]
|
|
80031f2: f005 fee7 bl 8008fc4 <HAL_PCD_DataOutStageCallback>
|
|
80031f6: e01d b.n 8003234 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
|
|
80031f8: 683b ldr r3, [r7, #0]
|
|
80031fa: 2b00 cmp r3, #0
|
|
80031fc: d114 bne.n 8003228 <PCD_EP_OutXfrComplete_int+0x1b0>
|
|
80031fe: 6879 ldr r1, [r7, #4]
|
|
8003200: 683a ldr r2, [r7, #0]
|
|
8003202: 4613 mov r3, r2
|
|
8003204: 00db lsls r3, r3, #3
|
|
8003206: 4413 add r3, r2
|
|
8003208: 009b lsls r3, r3, #2
|
|
800320a: 440b add r3, r1
|
|
800320c: f503 7319 add.w r3, r3, #612 @ 0x264
|
|
8003210: 681b ldr r3, [r3, #0]
|
|
8003212: 2b00 cmp r3, #0
|
|
8003214: d108 bne.n 8003228 <PCD_EP_OutXfrComplete_int+0x1b0>
|
|
{
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
|
|
8003216: 687b ldr r3, [r7, #4]
|
|
8003218: 6818 ldr r0, [r3, #0]
|
|
800321a: 687b ldr r3, [r7, #4]
|
|
800321c: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8003220: 461a mov r2, r3
|
|
8003222: 2100 movs r1, #0
|
|
8003224: f003 fede bl 8006fe4 <USB_EP0_OutStart>
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
8003228: 683b ldr r3, [r7, #0]
|
|
800322a: b2db uxtb r3, r3
|
|
800322c: 4619 mov r1, r3
|
|
800322e: 6878 ldr r0, [r7, #4]
|
|
8003230: f005 fec8 bl 8008fc4 <HAL_PCD_DataOutStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003234: 2300 movs r3, #0
|
|
}
|
|
8003236: 4618 mov r0, r3
|
|
8003238: 3720 adds r7, #32
|
|
800323a: 46bd mov sp, r7
|
|
800323c: bd80 pop {r7, pc}
|
|
800323e: bf00 nop
|
|
8003240: 4f54300a .word 0x4f54300a
|
|
8003244: 4f54310a .word 0x4f54310a
|
|
|
|
08003248 <PCD_EP_OutSetupPacket_int>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8003248: b580 push {r7, lr}
|
|
800324a: b086 sub sp, #24
|
|
800324c: af00 add r7, sp, #0
|
|
800324e: 6078 str r0, [r7, #4]
|
|
8003250: 6039 str r1, [r7, #0]
|
|
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8003252: 687b ldr r3, [r7, #4]
|
|
8003254: 681b ldr r3, [r3, #0]
|
|
8003256: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8003258: 697b ldr r3, [r7, #20]
|
|
800325a: 613b str r3, [r7, #16]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
800325c: 697b ldr r3, [r7, #20]
|
|
800325e: 333c adds r3, #60 @ 0x3c
|
|
8003260: 3304 adds r3, #4
|
|
8003262: 681b ldr r3, [r3, #0]
|
|
8003264: 60fb str r3, [r7, #12]
|
|
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
|
|
8003266: 683b ldr r3, [r7, #0]
|
|
8003268: 015a lsls r2, r3, #5
|
|
800326a: 693b ldr r3, [r7, #16]
|
|
800326c: 4413 add r3, r2
|
|
800326e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003272: 689b ldr r3, [r3, #8]
|
|
8003274: 60bb str r3, [r7, #8]
|
|
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8003276: 68fb ldr r3, [r7, #12]
|
|
8003278: 4a15 ldr r2, [pc, #84] @ (80032d0 <PCD_EP_OutSetupPacket_int+0x88>)
|
|
800327a: 4293 cmp r3, r2
|
|
800327c: d90e bls.n 800329c <PCD_EP_OutSetupPacket_int+0x54>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
800327e: 68bb ldr r3, [r7, #8]
|
|
8003280: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8003284: 2b00 cmp r3, #0
|
|
8003286: d009 beq.n 800329c <PCD_EP_OutSetupPacket_int+0x54>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8003288: 683b ldr r3, [r7, #0]
|
|
800328a: 015a lsls r2, r3, #5
|
|
800328c: 693b ldr r3, [r7, #16]
|
|
800328e: 4413 add r3, r2
|
|
8003290: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003294: 461a mov r2, r3
|
|
8003296: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
800329a: 6093 str r3, [r2, #8]
|
|
|
|
/* Inform the upper layer that a setup packet is available */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SetupStageCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SetupStageCallback(hpcd);
|
|
800329c: 6878 ldr r0, [r7, #4]
|
|
800329e: f005 fe7f bl 8008fa0 <HAL_PCD_SetupStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
|
|
80032a2: 68fb ldr r3, [r7, #12]
|
|
80032a4: 4a0a ldr r2, [pc, #40] @ (80032d0 <PCD_EP_OutSetupPacket_int+0x88>)
|
|
80032a6: 4293 cmp r3, r2
|
|
80032a8: d90c bls.n 80032c4 <PCD_EP_OutSetupPacket_int+0x7c>
|
|
80032aa: 687b ldr r3, [r7, #4]
|
|
80032ac: 799b ldrb r3, [r3, #6]
|
|
80032ae: 2b01 cmp r3, #1
|
|
80032b0: d108 bne.n 80032c4 <PCD_EP_OutSetupPacket_int+0x7c>
|
|
{
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
80032b2: 687b ldr r3, [r7, #4]
|
|
80032b4: 6818 ldr r0, [r3, #0]
|
|
80032b6: 687b ldr r3, [r7, #4]
|
|
80032b8: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
80032bc: 461a mov r2, r3
|
|
80032be: 2101 movs r1, #1
|
|
80032c0: f003 fe90 bl 8006fe4 <USB_EP0_OutStart>
|
|
}
|
|
|
|
return HAL_OK;
|
|
80032c4: 2300 movs r3, #0
|
|
}
|
|
80032c6: 4618 mov r0, r3
|
|
80032c8: 3718 adds r7, #24
|
|
80032ca: 46bd mov sp, r7
|
|
80032cc: bd80 pop {r7, pc}
|
|
80032ce: bf00 nop
|
|
80032d0: 4f54300a .word 0x4f54300a
|
|
|
|
080032d4 <HAL_PCDEx_SetTxFiFo>:
|
|
* @param fifo The number of Tx fifo
|
|
* @param size Fifo size
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
|
|
{
|
|
80032d4: b480 push {r7}
|
|
80032d6: b085 sub sp, #20
|
|
80032d8: af00 add r7, sp, #0
|
|
80032da: 6078 str r0, [r7, #4]
|
|
80032dc: 460b mov r3, r1
|
|
80032de: 70fb strb r3, [r7, #3]
|
|
80032e0: 4613 mov r3, r2
|
|
80032e2: 803b strh r3, [r7, #0]
|
|
--> Txn should be configured with the minimum space of 16 words
|
|
The FIFO is used optimally when used TxFIFOs are allocated in the top
|
|
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
|
|
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
|
|
|
|
Tx_Offset = hpcd->Instance->GRXFSIZ;
|
|
80032e4: 687b ldr r3, [r7, #4]
|
|
80032e6: 681b ldr r3, [r3, #0]
|
|
80032e8: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80032ea: 60bb str r3, [r7, #8]
|
|
|
|
if (fifo == 0U)
|
|
80032ec: 78fb ldrb r3, [r7, #3]
|
|
80032ee: 2b00 cmp r3, #0
|
|
80032f0: d107 bne.n 8003302 <HAL_PCDEx_SetTxFiFo+0x2e>
|
|
{
|
|
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
|
|
80032f2: 883b ldrh r3, [r7, #0]
|
|
80032f4: 0419 lsls r1, r3, #16
|
|
80032f6: 687b ldr r3, [r7, #4]
|
|
80032f8: 681b ldr r3, [r3, #0]
|
|
80032fa: 68ba ldr r2, [r7, #8]
|
|
80032fc: 430a orrs r2, r1
|
|
80032fe: 629a str r2, [r3, #40] @ 0x28
|
|
8003300: e028 b.n 8003354 <HAL_PCDEx_SetTxFiFo+0x80>
|
|
}
|
|
else
|
|
{
|
|
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
|
|
8003302: 687b ldr r3, [r7, #4]
|
|
8003304: 681b ldr r3, [r3, #0]
|
|
8003306: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003308: 0c1b lsrs r3, r3, #16
|
|
800330a: 68ba ldr r2, [r7, #8]
|
|
800330c: 4413 add r3, r2
|
|
800330e: 60bb str r3, [r7, #8]
|
|
for (i = 0U; i < (fifo - 1U); i++)
|
|
8003310: 2300 movs r3, #0
|
|
8003312: 73fb strb r3, [r7, #15]
|
|
8003314: e00d b.n 8003332 <HAL_PCDEx_SetTxFiFo+0x5e>
|
|
{
|
|
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
|
|
8003316: 687b ldr r3, [r7, #4]
|
|
8003318: 681a ldr r2, [r3, #0]
|
|
800331a: 7bfb ldrb r3, [r7, #15]
|
|
800331c: 3340 adds r3, #64 @ 0x40
|
|
800331e: 009b lsls r3, r3, #2
|
|
8003320: 4413 add r3, r2
|
|
8003322: 685b ldr r3, [r3, #4]
|
|
8003324: 0c1b lsrs r3, r3, #16
|
|
8003326: 68ba ldr r2, [r7, #8]
|
|
8003328: 4413 add r3, r2
|
|
800332a: 60bb str r3, [r7, #8]
|
|
for (i = 0U; i < (fifo - 1U); i++)
|
|
800332c: 7bfb ldrb r3, [r7, #15]
|
|
800332e: 3301 adds r3, #1
|
|
8003330: 73fb strb r3, [r7, #15]
|
|
8003332: 7bfa ldrb r2, [r7, #15]
|
|
8003334: 78fb ldrb r3, [r7, #3]
|
|
8003336: 3b01 subs r3, #1
|
|
8003338: 429a cmp r2, r3
|
|
800333a: d3ec bcc.n 8003316 <HAL_PCDEx_SetTxFiFo+0x42>
|
|
}
|
|
|
|
/* Multiply Tx_Size by 2 to get higher performance */
|
|
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
|
|
800333c: 883b ldrh r3, [r7, #0]
|
|
800333e: 0418 lsls r0, r3, #16
|
|
8003340: 687b ldr r3, [r7, #4]
|
|
8003342: 6819 ldr r1, [r3, #0]
|
|
8003344: 78fb ldrb r3, [r7, #3]
|
|
8003346: 3b01 subs r3, #1
|
|
8003348: 68ba ldr r2, [r7, #8]
|
|
800334a: 4302 orrs r2, r0
|
|
800334c: 3340 adds r3, #64 @ 0x40
|
|
800334e: 009b lsls r3, r3, #2
|
|
8003350: 440b add r3, r1
|
|
8003352: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003354: 2300 movs r3, #0
|
|
}
|
|
8003356: 4618 mov r0, r3
|
|
8003358: 3714 adds r7, #20
|
|
800335a: 46bd mov sp, r7
|
|
800335c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003360: 4770 bx lr
|
|
|
|
08003362 <HAL_PCDEx_SetRxFiFo>:
|
|
* @param hpcd PCD handle
|
|
* @param size Size of Rx fifo
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
|
|
{
|
|
8003362: b480 push {r7}
|
|
8003364: b083 sub sp, #12
|
|
8003366: af00 add r7, sp, #0
|
|
8003368: 6078 str r0, [r7, #4]
|
|
800336a: 460b mov r3, r1
|
|
800336c: 807b strh r3, [r7, #2]
|
|
hpcd->Instance->GRXFSIZ = size;
|
|
800336e: 687b ldr r3, [r7, #4]
|
|
8003370: 681b ldr r3, [r3, #0]
|
|
8003372: 887a ldrh r2, [r7, #2]
|
|
8003374: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_OK;
|
|
8003376: 2300 movs r3, #0
|
|
}
|
|
8003378: 4618 mov r0, r3
|
|
800337a: 370c adds r7, #12
|
|
800337c: 46bd mov sp, r7
|
|
800337e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003382: 4770 bx lr
|
|
|
|
08003384 <HAL_PCDEx_ActivateLPM>:
|
|
* @brief Activate LPM feature.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8003384: b480 push {r7}
|
|
8003386: b085 sub sp, #20
|
|
8003388: af00 add r7, sp, #0
|
|
800338a: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
800338c: 687b ldr r3, [r7, #4]
|
|
800338e: 681b ldr r3, [r3, #0]
|
|
8003390: 60fb str r3, [r7, #12]
|
|
|
|
hpcd->lpm_active = 1U;
|
|
8003392: 687b ldr r3, [r7, #4]
|
|
8003394: 2201 movs r2, #1
|
|
8003396: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8
|
|
hpcd->LPM_State = LPM_L0;
|
|
800339a: 687b ldr r3, [r7, #4]
|
|
800339c: 2200 movs r2, #0
|
|
800339e: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
|
|
80033a2: 68fb ldr r3, [r7, #12]
|
|
80033a4: 699b ldr r3, [r3, #24]
|
|
80033a6: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000
|
|
80033aa: 68fb ldr r3, [r7, #12]
|
|
80033ac: 619a str r2, [r3, #24]
|
|
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
|
|
80033ae: 68fb ldr r3, [r7, #12]
|
|
80033b0: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80033b2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80033b6: f043 0303 orr.w r3, r3, #3
|
|
80033ba: 68fa ldr r2, [r7, #12]
|
|
80033bc: 6553 str r3, [r2, #84] @ 0x54
|
|
|
|
return HAL_OK;
|
|
80033be: 2300 movs r3, #0
|
|
}
|
|
80033c0: 4618 mov r0, r3
|
|
80033c2: 3714 adds r7, #20
|
|
80033c4: 46bd mov sp, r7
|
|
80033c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80033ca: 4770 bx lr
|
|
|
|
080033cc <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
80033cc: b580 push {r7, lr}
|
|
80033ce: b084 sub sp, #16
|
|
80033d0: af00 add r7, sp, #0
|
|
80033d2: 6078 str r0, [r7, #4]
|
|
80033d4: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
80033d6: 687b ldr r3, [r7, #4]
|
|
80033d8: 2b00 cmp r3, #0
|
|
80033da: d101 bne.n 80033e0 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
80033dc: 2301 movs r3, #1
|
|
80033de: e0cc b.n 800357a <HAL_RCC_ClockConfig+0x1ae>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
80033e0: 4b68 ldr r3, [pc, #416] @ (8003584 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80033e2: 681b ldr r3, [r3, #0]
|
|
80033e4: f003 030f and.w r3, r3, #15
|
|
80033e8: 683a ldr r2, [r7, #0]
|
|
80033ea: 429a cmp r2, r3
|
|
80033ec: d90c bls.n 8003408 <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80033ee: 4b65 ldr r3, [pc, #404] @ (8003584 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80033f0: 683a ldr r2, [r7, #0]
|
|
80033f2: b2d2 uxtb r2, r2
|
|
80033f4: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80033f6: 4b63 ldr r3, [pc, #396] @ (8003584 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80033f8: 681b ldr r3, [r3, #0]
|
|
80033fa: f003 030f and.w r3, r3, #15
|
|
80033fe: 683a ldr r2, [r7, #0]
|
|
8003400: 429a cmp r2, r3
|
|
8003402: d001 beq.n 8003408 <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003404: 2301 movs r3, #1
|
|
8003406: e0b8 b.n 800357a <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8003408: 687b ldr r3, [r7, #4]
|
|
800340a: 681b ldr r3, [r3, #0]
|
|
800340c: f003 0302 and.w r3, r3, #2
|
|
8003410: 2b00 cmp r3, #0
|
|
8003412: d020 beq.n 8003456 <HAL_RCC_ClockConfig+0x8a>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8003414: 687b ldr r3, [r7, #4]
|
|
8003416: 681b ldr r3, [r3, #0]
|
|
8003418: f003 0304 and.w r3, r3, #4
|
|
800341c: 2b00 cmp r3, #0
|
|
800341e: d005 beq.n 800342c <HAL_RCC_ClockConfig+0x60>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
8003420: 4b59 ldr r3, [pc, #356] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003422: 689b ldr r3, [r3, #8]
|
|
8003424: 4a58 ldr r2, [pc, #352] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003426: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
|
|
800342a: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
800342c: 687b ldr r3, [r7, #4]
|
|
800342e: 681b ldr r3, [r3, #0]
|
|
8003430: f003 0308 and.w r3, r3, #8
|
|
8003434: 2b00 cmp r3, #0
|
|
8003436: d005 beq.n 8003444 <HAL_RCC_ClockConfig+0x78>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
8003438: 4b53 ldr r3, [pc, #332] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800343a: 689b ldr r3, [r3, #8]
|
|
800343c: 4a52 ldr r2, [pc, #328] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800343e: f443 4360 orr.w r3, r3, #57344 @ 0xe000
|
|
8003442: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8003444: 4b50 ldr r3, [pc, #320] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003446: 689b ldr r3, [r3, #8]
|
|
8003448: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
800344c: 687b ldr r3, [r7, #4]
|
|
800344e: 689b ldr r3, [r3, #8]
|
|
8003450: 494d ldr r1, [pc, #308] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003452: 4313 orrs r3, r2
|
|
8003454: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8003456: 687b ldr r3, [r7, #4]
|
|
8003458: 681b ldr r3, [r3, #0]
|
|
800345a: f003 0301 and.w r3, r3, #1
|
|
800345e: 2b00 cmp r3, #0
|
|
8003460: d044 beq.n 80034ec <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8003462: 687b ldr r3, [r7, #4]
|
|
8003464: 685b ldr r3, [r3, #4]
|
|
8003466: 2b01 cmp r3, #1
|
|
8003468: d107 bne.n 800347a <HAL_RCC_ClockConfig+0xae>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
800346a: 4b47 ldr r3, [pc, #284] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800346c: 681b ldr r3, [r3, #0]
|
|
800346e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003472: 2b00 cmp r3, #0
|
|
8003474: d119 bne.n 80034aa <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8003476: 2301 movs r3, #1
|
|
8003478: e07f b.n 800357a <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
800347a: 687b ldr r3, [r7, #4]
|
|
800347c: 685b ldr r3, [r3, #4]
|
|
800347e: 2b02 cmp r3, #2
|
|
8003480: d003 beq.n 800348a <HAL_RCC_ClockConfig+0xbe>
|
|
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
|
|
8003482: 687b ldr r3, [r7, #4]
|
|
8003484: 685b ldr r3, [r3, #4]
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
8003486: 2b03 cmp r3, #3
|
|
8003488: d107 bne.n 800349a <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
800348a: 4b3f ldr r3, [pc, #252] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800348c: 681b ldr r3, [r3, #0]
|
|
800348e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003492: 2b00 cmp r3, #0
|
|
8003494: d109 bne.n 80034aa <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8003496: 2301 movs r3, #1
|
|
8003498: e06f b.n 800357a <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
800349a: 4b3b ldr r3, [pc, #236] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800349c: 681b ldr r3, [r3, #0]
|
|
800349e: f003 0302 and.w r3, r3, #2
|
|
80034a2: 2b00 cmp r3, #0
|
|
80034a4: d101 bne.n 80034aa <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
80034a6: 2301 movs r3, #1
|
|
80034a8: e067 b.n 800357a <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
80034aa: 4b37 ldr r3, [pc, #220] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80034ac: 689b ldr r3, [r3, #8]
|
|
80034ae: f023 0203 bic.w r2, r3, #3
|
|
80034b2: 687b ldr r3, [r7, #4]
|
|
80034b4: 685b ldr r3, [r3, #4]
|
|
80034b6: 4934 ldr r1, [pc, #208] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80034b8: 4313 orrs r3, r2
|
|
80034ba: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80034bc: f7fe f82e bl 800151c <HAL_GetTick>
|
|
80034c0: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80034c2: e00a b.n 80034da <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80034c4: f7fe f82a bl 800151c <HAL_GetTick>
|
|
80034c8: 4602 mov r2, r0
|
|
80034ca: 68fb ldr r3, [r7, #12]
|
|
80034cc: 1ad3 subs r3, r2, r3
|
|
80034ce: f241 3288 movw r2, #5000 @ 0x1388
|
|
80034d2: 4293 cmp r3, r2
|
|
80034d4: d901 bls.n 80034da <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80034d6: 2303 movs r3, #3
|
|
80034d8: e04f b.n 800357a <HAL_RCC_ClockConfig+0x1ae>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80034da: 4b2b ldr r3, [pc, #172] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80034dc: 689b ldr r3, [r3, #8]
|
|
80034de: f003 020c and.w r2, r3, #12
|
|
80034e2: 687b ldr r3, [r7, #4]
|
|
80034e4: 685b ldr r3, [r3, #4]
|
|
80034e6: 009b lsls r3, r3, #2
|
|
80034e8: 429a cmp r2, r3
|
|
80034ea: d1eb bne.n 80034c4 <HAL_RCC_ClockConfig+0xf8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
80034ec: 4b25 ldr r3, [pc, #148] @ (8003584 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80034ee: 681b ldr r3, [r3, #0]
|
|
80034f0: f003 030f and.w r3, r3, #15
|
|
80034f4: 683a ldr r2, [r7, #0]
|
|
80034f6: 429a cmp r2, r3
|
|
80034f8: d20c bcs.n 8003514 <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80034fa: 4b22 ldr r3, [pc, #136] @ (8003584 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80034fc: 683a ldr r2, [r7, #0]
|
|
80034fe: b2d2 uxtb r2, r2
|
|
8003500: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8003502: 4b20 ldr r3, [pc, #128] @ (8003584 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8003504: 681b ldr r3, [r3, #0]
|
|
8003506: f003 030f and.w r3, r3, #15
|
|
800350a: 683a ldr r2, [r7, #0]
|
|
800350c: 429a cmp r2, r3
|
|
800350e: d001 beq.n 8003514 <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
return HAL_ERROR;
|
|
8003510: 2301 movs r3, #1
|
|
8003512: e032 b.n 800357a <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8003514: 687b ldr r3, [r7, #4]
|
|
8003516: 681b ldr r3, [r3, #0]
|
|
8003518: f003 0304 and.w r3, r3, #4
|
|
800351c: 2b00 cmp r3, #0
|
|
800351e: d008 beq.n 8003532 <HAL_RCC_ClockConfig+0x166>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8003520: 4b19 ldr r3, [pc, #100] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003522: 689b ldr r3, [r3, #8]
|
|
8003524: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
|
|
8003528: 687b ldr r3, [r7, #4]
|
|
800352a: 68db ldr r3, [r3, #12]
|
|
800352c: 4916 ldr r1, [pc, #88] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800352e: 4313 orrs r3, r2
|
|
8003530: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8003532: 687b ldr r3, [r7, #4]
|
|
8003534: 681b ldr r3, [r3, #0]
|
|
8003536: f003 0308 and.w r3, r3, #8
|
|
800353a: 2b00 cmp r3, #0
|
|
800353c: d009 beq.n 8003552 <HAL_RCC_ClockConfig+0x186>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
800353e: 4b12 ldr r3, [pc, #72] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003540: 689b ldr r3, [r3, #8]
|
|
8003542: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
8003546: 687b ldr r3, [r7, #4]
|
|
8003548: 691b ldr r3, [r3, #16]
|
|
800354a: 00db lsls r3, r3, #3
|
|
800354c: 490e ldr r1, [pc, #56] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800354e: 4313 orrs r3, r2
|
|
8003550: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
8003552: f000 fb7f bl 8003c54 <HAL_RCC_GetSysClockFreq>
|
|
8003556: 4602 mov r2, r0
|
|
8003558: 4b0b ldr r3, [pc, #44] @ (8003588 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800355a: 689b ldr r3, [r3, #8]
|
|
800355c: 091b lsrs r3, r3, #4
|
|
800355e: f003 030f and.w r3, r3, #15
|
|
8003562: 490a ldr r1, [pc, #40] @ (800358c <HAL_RCC_ClockConfig+0x1c0>)
|
|
8003564: 5ccb ldrb r3, [r1, r3]
|
|
8003566: fa22 f303 lsr.w r3, r2, r3
|
|
800356a: 4a09 ldr r2, [pc, #36] @ (8003590 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800356c: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings */
|
|
HAL_InitTick(uwTickPrio);
|
|
800356e: 4b09 ldr r3, [pc, #36] @ (8003594 <HAL_RCC_ClockConfig+0x1c8>)
|
|
8003570: 681b ldr r3, [r3, #0]
|
|
8003572: 4618 mov r0, r3
|
|
8003574: f7fd ff8e bl 8001494 <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
8003578: 2300 movs r3, #0
|
|
}
|
|
800357a: 4618 mov r0, r3
|
|
800357c: 3710 adds r7, #16
|
|
800357e: 46bd mov sp, r7
|
|
8003580: bd80 pop {r7, pc}
|
|
8003582: bf00 nop
|
|
8003584: 40023c00 .word 0x40023c00
|
|
8003588: 40023800 .word 0x40023800
|
|
800358c: 08009644 .word 0x08009644
|
|
8003590: 20000078 .word 0x20000078
|
|
8003594: 2000007c .word 0x2000007c
|
|
|
|
08003598 <HAL_RCC_GetHCLKFreq>:
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8003598: b480 push {r7}
|
|
800359a: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
800359c: 4b03 ldr r3, [pc, #12] @ (80035ac <HAL_RCC_GetHCLKFreq+0x14>)
|
|
800359e: 681b ldr r3, [r3, #0]
|
|
}
|
|
80035a0: 4618 mov r0, r3
|
|
80035a2: 46bd mov sp, r7
|
|
80035a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80035a8: 4770 bx lr
|
|
80035aa: bf00 nop
|
|
80035ac: 20000078 .word 0x20000078
|
|
|
|
080035b0 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
80035b0: b580 push {r7, lr}
|
|
80035b2: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
80035b4: f7ff fff0 bl 8003598 <HAL_RCC_GetHCLKFreq>
|
|
80035b8: 4602 mov r2, r0
|
|
80035ba: 4b05 ldr r3, [pc, #20] @ (80035d0 <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
80035bc: 689b ldr r3, [r3, #8]
|
|
80035be: 0a9b lsrs r3, r3, #10
|
|
80035c0: f003 0307 and.w r3, r3, #7
|
|
80035c4: 4903 ldr r1, [pc, #12] @ (80035d4 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
80035c6: 5ccb ldrb r3, [r1, r3]
|
|
80035c8: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80035cc: 4618 mov r0, r3
|
|
80035ce: bd80 pop {r7, pc}
|
|
80035d0: 40023800 .word 0x40023800
|
|
80035d4: 08009654 .word 0x08009654
|
|
|
|
080035d8 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
80035d8: b580 push {r7, lr}
|
|
80035da: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
80035dc: f7ff ffdc bl 8003598 <HAL_RCC_GetHCLKFreq>
|
|
80035e0: 4602 mov r2, r0
|
|
80035e2: 4b05 ldr r3, [pc, #20] @ (80035f8 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
80035e4: 689b ldr r3, [r3, #8]
|
|
80035e6: 0b5b lsrs r3, r3, #13
|
|
80035e8: f003 0307 and.w r3, r3, #7
|
|
80035ec: 4903 ldr r1, [pc, #12] @ (80035fc <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
80035ee: 5ccb ldrb r3, [r1, r3]
|
|
80035f0: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80035f4: 4618 mov r0, r3
|
|
80035f6: bd80 pop {r7, pc}
|
|
80035f8: 40023800 .word 0x40023800
|
|
80035fc: 08009654 .word 0x08009654
|
|
|
|
08003600 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the backup registers) and RCC_BDCR register are set to their reset values.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8003600: b580 push {r7, lr}
|
|
8003602: b08c sub sp, #48 @ 0x30
|
|
8003604: af00 add r7, sp, #0
|
|
8003606: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
8003608: 2300 movs r3, #0
|
|
800360a: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t tmpreg1 = 0U;
|
|
800360c: 2300 movs r3, #0
|
|
800360e: 623b str r3, [r7, #32]
|
|
uint32_t plli2sp = 0U;
|
|
8003610: 2300 movs r3, #0
|
|
8003612: 61fb str r3, [r7, #28]
|
|
uint32_t plli2sq = 0U;
|
|
8003614: 2300 movs r3, #0
|
|
8003616: 61bb str r3, [r7, #24]
|
|
uint32_t plli2sr = 0U;
|
|
8003618: 2300 movs r3, #0
|
|
800361a: 617b str r3, [r7, #20]
|
|
uint32_t pllsaip = 0U;
|
|
800361c: 2300 movs r3, #0
|
|
800361e: 613b str r3, [r7, #16]
|
|
uint32_t pllsaiq = 0U;
|
|
8003620: 2300 movs r3, #0
|
|
8003622: 60fb str r3, [r7, #12]
|
|
uint32_t plli2sused = 0U;
|
|
8003624: 2300 movs r3, #0
|
|
8003626: 62fb str r3, [r7, #44] @ 0x2c
|
|
uint32_t pllsaiused = 0U;
|
|
8003628: 2300 movs r3, #0
|
|
800362a: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Check the peripheral clock selection parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*------------------------ I2S APB1 configuration --------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
|
|
800362c: 687b ldr r3, [r7, #4]
|
|
800362e: 681b ldr r3, [r3, #0]
|
|
8003630: f003 0301 and.w r3, r3, #1
|
|
8003634: 2b00 cmp r3, #0
|
|
8003636: d010 beq.n 800365a <HAL_RCCEx_PeriphCLKConfig+0x5a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
|
|
|
|
/* Configure I2S Clock source */
|
|
__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
|
|
8003638: 4b6f ldr r3, [pc, #444] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800363a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
800363e: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000
|
|
8003642: 687b ldr r3, [r7, #4]
|
|
8003644: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003646: 496c ldr r1, [pc, #432] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003648: 4313 orrs r3, r2
|
|
800364a: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for I2S */
|
|
if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
|
|
800364e: 687b ldr r3, [r7, #4]
|
|
8003650: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003652: 2b00 cmp r3, #0
|
|
8003654: d101 bne.n 800365a <HAL_RCCEx_PeriphCLKConfig+0x5a>
|
|
{
|
|
plli2sused = 1U;
|
|
8003656: 2301 movs r3, #1
|
|
8003658: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- I2S APB2 configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
|
|
800365a: 687b ldr r3, [r7, #4]
|
|
800365c: 681b ldr r3, [r3, #0]
|
|
800365e: f003 0302 and.w r3, r3, #2
|
|
8003662: 2b00 cmp r3, #0
|
|
8003664: d010 beq.n 8003688 <HAL_RCCEx_PeriphCLKConfig+0x88>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
|
|
|
|
/* Configure I2S Clock source */
|
|
__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
|
|
8003666: 4b64 ldr r3, [pc, #400] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003668: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
800366c: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000
|
|
8003670: 687b ldr r3, [r7, #4]
|
|
8003672: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8003674: 4960 ldr r1, [pc, #384] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003676: 4313 orrs r3, r2
|
|
8003678: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for I2S */
|
|
if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
|
|
800367c: 687b ldr r3, [r7, #4]
|
|
800367e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8003680: 2b00 cmp r3, #0
|
|
8003682: d101 bne.n 8003688 <HAL_RCCEx_PeriphCLKConfig+0x88>
|
|
{
|
|
plli2sused = 1U;
|
|
8003684: 2301 movs r3, #1
|
|
8003686: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*--------------------------- SAI1 configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
|
|
8003688: 687b ldr r3, [r7, #4]
|
|
800368a: 681b ldr r3, [r3, #0]
|
|
800368c: f003 0304 and.w r3, r3, #4
|
|
8003690: 2b00 cmp r3, #0
|
|
8003692: d017 beq.n 80036c4 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
/* Configure SAI1 Clock source */
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
8003694: 4b58 ldr r3, [pc, #352] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003696: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
800369a: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
800369e: 687b ldr r3, [r7, #4]
|
|
80036a0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80036a2: 4955 ldr r1, [pc, #340] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80036a4: 4313 orrs r3, r2
|
|
80036a6: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
|
|
80036aa: 687b ldr r3, [r7, #4]
|
|
80036ac: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80036ae: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
80036b2: d101 bne.n 80036b8 <HAL_RCCEx_PeriphCLKConfig+0xb8>
|
|
{
|
|
plli2sused = 1U;
|
|
80036b4: 2301 movs r3, #1
|
|
80036b6: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
/* Enable the PLLSAI when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
|
|
80036b8: 687b ldr r3, [r7, #4]
|
|
80036ba: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80036bc: 2b00 cmp r3, #0
|
|
80036be: d101 bne.n 80036c4 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|
{
|
|
pllsaiused = 1U;
|
|
80036c0: 2301 movs r3, #1
|
|
80036c2: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*-------------------------- SAI2 configuration ----------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
|
|
80036c4: 687b ldr r3, [r7, #4]
|
|
80036c6: 681b ldr r3, [r3, #0]
|
|
80036c8: f003 0308 and.w r3, r3, #8
|
|
80036cc: 2b00 cmp r3, #0
|
|
80036ce: d017 beq.n 8003700 <HAL_RCCEx_PeriphCLKConfig+0x100>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
|
|
|
|
/* Configure SAI2 Clock source */
|
|
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
|
|
80036d0: 4b49 ldr r3, [pc, #292] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80036d2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80036d6: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
80036da: 687b ldr r3, [r7, #4]
|
|
80036dc: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80036de: 4946 ldr r1, [pc, #280] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80036e0: 4313 orrs r3, r2
|
|
80036e2: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
|
|
/* Enable the PLLI2S when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
|
|
80036e6: 687b ldr r3, [r7, #4]
|
|
80036e8: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80036ea: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80036ee: d101 bne.n 80036f4 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
{
|
|
plli2sused = 1U;
|
|
80036f0: 2301 movs r3, #1
|
|
80036f2: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
/* Enable the PLLSAI when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
|
|
80036f4: 687b ldr r3, [r7, #4]
|
|
80036f6: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80036f8: 2b00 cmp r3, #0
|
|
80036fa: d101 bne.n 8003700 <HAL_RCCEx_PeriphCLKConfig+0x100>
|
|
{
|
|
pllsaiused = 1U;
|
|
80036fc: 2301 movs r3, #1
|
|
80036fe: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- RTC configuration --------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
|
8003700: 687b ldr r3, [r7, #4]
|
|
8003702: 681b ldr r3, [r3, #0]
|
|
8003704: f003 0320 and.w r3, r3, #32
|
|
8003708: 2b00 cmp r3, #0
|
|
800370a: f000 808a beq.w 8003822 <HAL_RCCEx_PeriphCLKConfig+0x222>
|
|
{
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800370e: 2300 movs r3, #0
|
|
8003710: 60bb str r3, [r7, #8]
|
|
8003712: 4b39 ldr r3, [pc, #228] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003714: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003716: 4a38 ldr r2, [pc, #224] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003718: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800371c: 6413 str r3, [r2, #64] @ 0x40
|
|
800371e: 4b36 ldr r3, [pc, #216] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003720: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003722: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003726: 60bb str r3, [r7, #8]
|
|
8003728: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Enable write access to Backup domain */
|
|
PWR->CR |= PWR_CR_DBP;
|
|
800372a: 4b34 ldr r3, [pc, #208] @ (80037fc <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
800372c: 681b ldr r3, [r3, #0]
|
|
800372e: 4a33 ldr r2, [pc, #204] @ (80037fc <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
8003730: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8003734: 6013 str r3, [r2, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003736: f7fd fef1 bl 800151c <HAL_GetTick>
|
|
800373a: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
800373c: e008 b.n 8003750 <HAL_RCCEx_PeriphCLKConfig+0x150>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
800373e: f7fd feed bl 800151c <HAL_GetTick>
|
|
8003742: 4602 mov r2, r0
|
|
8003744: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003746: 1ad3 subs r3, r2, r3
|
|
8003748: 2b02 cmp r3, #2
|
|
800374a: d901 bls.n 8003750 <HAL_RCCEx_PeriphCLKConfig+0x150>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800374c: 2303 movs r3, #3
|
|
800374e: e278 b.n 8003c42 <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
8003750: 4b2a ldr r3, [pc, #168] @ (80037fc <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
8003752: 681b ldr r3, [r3, #0]
|
|
8003754: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003758: 2b00 cmp r3, #0
|
|
800375a: d0f0 beq.n 800373e <HAL_RCCEx_PeriphCLKConfig+0x13e>
|
|
}
|
|
}
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
800375c: 4b26 ldr r3, [pc, #152] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800375e: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003760: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8003764: 623b str r3, [r7, #32]
|
|
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
8003766: 6a3b ldr r3, [r7, #32]
|
|
8003768: 2b00 cmp r3, #0
|
|
800376a: d02f beq.n 80037cc <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
800376c: 687b ldr r3, [r7, #4]
|
|
800376e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003770: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8003774: 6a3a ldr r2, [r7, #32]
|
|
8003776: 429a cmp r2, r3
|
|
8003778: d028 beq.n 80037cc <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
800377a: 4b1f ldr r3, [pc, #124] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800377c: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800377e: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8003782: 623b str r3, [r7, #32]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8003784: 4b1e ldr r3, [pc, #120] @ (8003800 <HAL_RCCEx_PeriphCLKConfig+0x200>)
|
|
8003786: 2201 movs r2, #1
|
|
8003788: 601a str r2, [r3, #0]
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
800378a: 4b1d ldr r3, [pc, #116] @ (8003800 <HAL_RCCEx_PeriphCLKConfig+0x200>)
|
|
800378c: 2200 movs r2, #0
|
|
800378e: 601a str r2, [r3, #0]
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpreg1;
|
|
8003790: 4a19 ldr r2, [pc, #100] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003792: 6a3b ldr r3, [r7, #32]
|
|
8003794: 6713 str r3, [r2, #112] @ 0x70
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
|
|
8003796: 4b18 ldr r3, [pc, #96] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003798: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800379a: f003 0301 and.w r3, r3, #1
|
|
800379e: 2b01 cmp r3, #1
|
|
80037a0: d114 bne.n 80037cc <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80037a2: f7fd febb bl 800151c <HAL_GetTick>
|
|
80037a6: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
80037a8: e00a b.n 80037c0 <HAL_RCCEx_PeriphCLKConfig+0x1c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
80037aa: f7fd feb7 bl 800151c <HAL_GetTick>
|
|
80037ae: 4602 mov r2, r0
|
|
80037b0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80037b2: 1ad3 subs r3, r2, r3
|
|
80037b4: f241 3288 movw r2, #5000 @ 0x1388
|
|
80037b8: 4293 cmp r3, r2
|
|
80037ba: d901 bls.n 80037c0 <HAL_RCCEx_PeriphCLKConfig+0x1c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80037bc: 2303 movs r3, #3
|
|
80037be: e240 b.n 8003c42 <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
80037c0: 4b0d ldr r3, [pc, #52] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80037c2: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80037c4: f003 0302 and.w r3, r3, #2
|
|
80037c8: 2b00 cmp r3, #0
|
|
80037ca: d0ee beq.n 80037aa <HAL_RCCEx_PeriphCLKConfig+0x1aa>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
80037cc: 687b ldr r3, [r7, #4]
|
|
80037ce: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80037d0: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80037d4: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
80037d8: d114 bne.n 8003804 <HAL_RCCEx_PeriphCLKConfig+0x204>
|
|
80037da: 4b07 ldr r3, [pc, #28] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80037dc: 689b ldr r3, [r3, #8]
|
|
80037de: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
|
|
80037e2: 687b ldr r3, [r7, #4]
|
|
80037e4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80037e6: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000
|
|
80037ea: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80037ee: 4902 ldr r1, [pc, #8] @ (80037f8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80037f0: 4313 orrs r3, r2
|
|
80037f2: 608b str r3, [r1, #8]
|
|
80037f4: e00c b.n 8003810 <HAL_RCCEx_PeriphCLKConfig+0x210>
|
|
80037f6: bf00 nop
|
|
80037f8: 40023800 .word 0x40023800
|
|
80037fc: 40007000 .word 0x40007000
|
|
8003800: 42470e40 .word 0x42470e40
|
|
8003804: 4b4a ldr r3, [pc, #296] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003806: 689b ldr r3, [r3, #8]
|
|
8003808: 4a49 ldr r2, [pc, #292] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
800380a: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
|
|
800380e: 6093 str r3, [r2, #8]
|
|
8003810: 4b47 ldr r3, [pc, #284] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003812: 6f1a ldr r2, [r3, #112] @ 0x70
|
|
8003814: 687b ldr r3, [r7, #4]
|
|
8003816: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003818: f3c3 030b ubfx r3, r3, #0, #12
|
|
800381c: 4944 ldr r1, [pc, #272] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
800381e: 4313 orrs r3, r2
|
|
8003820: 670b str r3, [r1, #112] @ 0x70
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- TIM configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
|
|
8003822: 687b ldr r3, [r7, #4]
|
|
8003824: 681b ldr r3, [r3, #0]
|
|
8003826: f003 0310 and.w r3, r3, #16
|
|
800382a: 2b00 cmp r3, #0
|
|
800382c: d004 beq.n 8003838 <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
{
|
|
/* Configure Timer Prescaler */
|
|
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
|
|
800382e: 687b ldr r3, [r7, #4]
|
|
8003830: f893 2058 ldrb.w r2, [r3, #88] @ 0x58
|
|
8003834: 4b3f ldr r3, [pc, #252] @ (8003934 <HAL_RCCEx_PeriphCLKConfig+0x334>)
|
|
8003836: 601a str r2, [r3, #0]
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- FMPI2C1 Configuration -----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
|
|
8003838: 687b ldr r3, [r7, #4]
|
|
800383a: 681b ldr r3, [r3, #0]
|
|
800383c: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8003840: 2b00 cmp r3, #0
|
|
8003842: d00a beq.n 800385a <HAL_RCCEx_PeriphCLKConfig+0x25a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
|
|
|
|
/* Configure the FMPI2C1 clock source */
|
|
__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
|
|
8003844: 4b3a ldr r3, [pc, #232] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003846: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800384a: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
800384e: 687b ldr r3, [r7, #4]
|
|
8003850: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8003852: 4937 ldr r1, [pc, #220] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003854: 4313 orrs r3, r2
|
|
8003856: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*------------------------------ CEC Configuration -------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
|
|
800385a: 687b ldr r3, [r7, #4]
|
|
800385c: 681b ldr r3, [r3, #0]
|
|
800385e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8003862: 2b00 cmp r3, #0
|
|
8003864: d00a beq.n 800387c <HAL_RCCEx_PeriphCLKConfig+0x27c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
|
|
|
|
/* Configure the CEC clock source */
|
|
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
|
|
8003866: 4b32 ldr r3, [pc, #200] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003868: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800386c: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000
|
|
8003870: 687b ldr r3, [r7, #4]
|
|
8003872: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8003874: 492e ldr r1, [pc, #184] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003876: 4313 orrs r3, r2
|
|
8003878: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- CLK48 Configuration ------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
|
|
800387c: 687b ldr r3, [r7, #4]
|
|
800387e: 681b ldr r3, [r3, #0]
|
|
8003880: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003884: 2b00 cmp r3, #0
|
|
8003886: d011 beq.n 80038ac <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
|
|
|
|
/* Configure the CLK48 clock source */
|
|
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
|
|
8003888: 4b29 ldr r3, [pc, #164] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
800388a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800388e: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000
|
|
8003892: 687b ldr r3, [r7, #4]
|
|
8003894: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8003896: 4926 ldr r1, [pc, #152] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003898: 4313 orrs r3, r2
|
|
800389a: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
|
|
/* Enable the PLLSAI when it's used as clock source for CLK48 */
|
|
if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
|
|
800389e: 687b ldr r3, [r7, #4]
|
|
80038a0: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80038a2: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
80038a6: d101 bne.n 80038ac <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
pllsaiused = 1U;
|
|
80038a8: 2301 movs r3, #1
|
|
80038aa: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- SDIO Configuration -------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
|
|
80038ac: 687b ldr r3, [r7, #4]
|
|
80038ae: 681b ldr r3, [r3, #0]
|
|
80038b0: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80038b4: 2b00 cmp r3, #0
|
|
80038b6: d00a beq.n 80038ce <HAL_RCCEx_PeriphCLKConfig+0x2ce>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
|
|
|
|
/* Configure the SDIO clock source */
|
|
__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
|
|
80038b8: 4b1d ldr r3, [pc, #116] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80038ba: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
80038be: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
|
|
80038c2: 687b ldr r3, [r7, #4]
|
|
80038c4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80038c6: 491a ldr r1, [pc, #104] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80038c8: 4313 orrs r3, r2
|
|
80038ca: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*------------------------------ SPDIFRX Configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
|
80038ce: 687b ldr r3, [r7, #4]
|
|
80038d0: 681b ldr r3, [r3, #0]
|
|
80038d2: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80038d6: 2b00 cmp r3, #0
|
|
80038d8: d011 beq.n 80038fe <HAL_RCCEx_PeriphCLKConfig+0x2fe>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
|
|
|
|
/* Configure the SPDIFRX clock source */
|
|
__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
|
|
80038da: 4b15 ldr r3, [pc, #84] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80038dc: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
80038e0: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
|
|
80038e4: 687b ldr r3, [r7, #4]
|
|
80038e6: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80038e8: 4911 ldr r1, [pc, #68] @ (8003930 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80038ea: 4313 orrs r3, r2
|
|
80038ec: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
|
|
if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
|
|
80038f0: 687b ldr r3, [r7, #4]
|
|
80038f2: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80038f4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
80038f8: d101 bne.n 80038fe <HAL_RCCEx_PeriphCLKConfig+0x2fe>
|
|
{
|
|
plli2sused = 1U;
|
|
80038fa: 2301 movs r3, #1
|
|
80038fc: 62fb str r3, [r7, #44] @ 0x2c
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- PLLI2S Configuration ------------------------*/
|
|
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
|
|
I2S on APB2 or SPDIFRX */
|
|
if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
|
|
80038fe: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8003900: 2b01 cmp r3, #1
|
|
8003902: d005 beq.n 8003910 <HAL_RCCEx_PeriphCLKConfig+0x310>
|
|
8003904: 687b ldr r3, [r7, #4]
|
|
8003906: 681b ldr r3, [r3, #0]
|
|
8003908: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
800390c: f040 80ff bne.w 8003b0e <HAL_RCCEx_PeriphCLKConfig+0x50e>
|
|
{
|
|
/* Disable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_DISABLE();
|
|
8003910: 4b09 ldr r3, [pc, #36] @ (8003938 <HAL_RCCEx_PeriphCLKConfig+0x338>)
|
|
8003912: 2200 movs r2, #0
|
|
8003914: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003916: f7fd fe01 bl 800151c <HAL_GetTick>
|
|
800391a: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLI2S is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
800391c: e00e b.n 800393c <HAL_RCCEx_PeriphCLKConfig+0x33c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
800391e: f7fd fdfd bl 800151c <HAL_GetTick>
|
|
8003922: 4602 mov r2, r0
|
|
8003924: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003926: 1ad3 subs r3, r2, r3
|
|
8003928: 2b02 cmp r3, #2
|
|
800392a: d907 bls.n 800393c <HAL_RCCEx_PeriphCLKConfig+0x33c>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
800392c: 2303 movs r3, #3
|
|
800392e: e188 b.n 8003c42 <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
8003930: 40023800 .word 0x40023800
|
|
8003934: 424711e0 .word 0x424711e0
|
|
8003938: 42470068 .word 0x42470068
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
800393c: 4b7e ldr r3, [pc, #504] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800393e: 681b ldr r3, [r3, #0]
|
|
8003940: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8003944: 2b00 cmp r3, #0
|
|
8003946: d1ea bne.n 800391e <HAL_RCCEx_PeriphCLKConfig+0x31e>
|
|
/* check for common PLLI2S Parameters */
|
|
assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
|
|
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
|
|
|
/*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1)
|
|
8003948: 687b ldr r3, [r7, #4]
|
|
800394a: 681b ldr r3, [r3, #0]
|
|
800394c: f003 0301 and.w r3, r3, #1
|
|
8003950: 2b00 cmp r3, #0
|
|
8003952: d003 beq.n 800395c <HAL_RCCEx_PeriphCLKConfig+0x35c>
|
|
&& (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
|
|
8003954: 687b ldr r3, [r7, #4]
|
|
8003956: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003958: 2b00 cmp r3, #0
|
|
800395a: d009 beq.n 8003970 <HAL_RCCEx_PeriphCLKConfig+0x370>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
|
|
800395c: 687b ldr r3, [r7, #4]
|
|
800395e: 681b ldr r3, [r3, #0]
|
|
8003960: f003 0302 and.w r3, r3, #2
|
|
&& (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
|
|
8003964: 2b00 cmp r3, #0
|
|
8003966: d028 beq.n 80039ba <HAL_RCCEx_PeriphCLKConfig+0x3ba>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
|
|
8003968: 687b ldr r3, [r7, #4]
|
|
800396a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800396c: 2b00 cmp r3, #0
|
|
800396e: d124 bne.n 80039ba <HAL_RCCEx_PeriphCLKConfig+0x3ba>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
|
|
/* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
|
|
plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
8003970: 4b71 ldr r3, [pc, #452] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003972: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003976: 0c1b lsrs r3, r3, #16
|
|
8003978: f003 0303 and.w r3, r3, #3
|
|
800397c: 3301 adds r3, #1
|
|
800397e: 005b lsls r3, r3, #1
|
|
8003980: 61fb str r3, [r7, #28]
|
|
plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
|
|
8003982: 4b6d ldr r3, [pc, #436] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003984: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003988: 0e1b lsrs r3, r3, #24
|
|
800398a: f003 030f and.w r3, r3, #15
|
|
800398e: 61bb str r3, [r7, #24]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq,
|
|
8003990: 687b ldr r3, [r7, #4]
|
|
8003992: 685a ldr r2, [r3, #4]
|
|
8003994: 687b ldr r3, [r7, #4]
|
|
8003996: 689b ldr r3, [r3, #8]
|
|
8003998: 019b lsls r3, r3, #6
|
|
800399a: 431a orrs r2, r3
|
|
800399c: 69fb ldr r3, [r7, #28]
|
|
800399e: 085b lsrs r3, r3, #1
|
|
80039a0: 3b01 subs r3, #1
|
|
80039a2: 041b lsls r3, r3, #16
|
|
80039a4: 431a orrs r2, r3
|
|
80039a6: 69bb ldr r3, [r7, #24]
|
|
80039a8: 061b lsls r3, r3, #24
|
|
80039aa: 431a orrs r2, r3
|
|
80039ac: 687b ldr r3, [r7, #4]
|
|
80039ae: 695b ldr r3, [r3, #20]
|
|
80039b0: 071b lsls r3, r3, #28
|
|
80039b2: 4961 ldr r1, [pc, #388] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80039b4: 4313 orrs r3, r2
|
|
80039b6: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SR);
|
|
}
|
|
|
|
/*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
|
|
80039ba: 687b ldr r3, [r7, #4]
|
|
80039bc: 681b ldr r3, [r3, #0]
|
|
80039be: f003 0304 and.w r3, r3, #4
|
|
80039c2: 2b00 cmp r3, #0
|
|
80039c4: d004 beq.n 80039d0 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
|
80039c6: 687b ldr r3, [r7, #4]
|
|
80039c8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80039ca: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
80039ce: d00a beq.n 80039e6 <HAL_RCCEx_PeriphCLKConfig+0x3e6>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
|
80039d0: 687b ldr r3, [r7, #4]
|
|
80039d2: 681b ldr r3, [r3, #0]
|
|
80039d4: f003 0308 and.w r3, r3, #8
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
|
80039d8: 2b00 cmp r3, #0
|
|
80039da: d035 beq.n 8003a48 <HAL_RCCEx_PeriphCLKConfig+0x448>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
|
80039dc: 687b ldr r3, [r7, #4]
|
|
80039de: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80039e0: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80039e4: d130 bne.n 8003a48 <HAL_RCCEx_PeriphCLKConfig+0x448>
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
/* Check for PLLI2S/DIVQ parameters */
|
|
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
|
|
|
|
/* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
|
|
plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
80039e6: 4b54 ldr r3, [pc, #336] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80039e8: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80039ec: 0c1b lsrs r3, r3, #16
|
|
80039ee: f003 0303 and.w r3, r3, #3
|
|
80039f2: 3301 adds r3, #1
|
|
80039f4: 005b lsls r3, r3, #1
|
|
80039f6: 61fb str r3, [r7, #28]
|
|
plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
80039f8: 4b4f ldr r3, [pc, #316] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80039fa: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80039fe: 0f1b lsrs r3, r3, #28
|
|
8003a00: f003 0307 and.w r3, r3, #7
|
|
8003a04: 617b str r3, [r7, #20]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
|
|
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
|
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp,
|
|
8003a06: 687b ldr r3, [r7, #4]
|
|
8003a08: 685a ldr r2, [r3, #4]
|
|
8003a0a: 687b ldr r3, [r7, #4]
|
|
8003a0c: 689b ldr r3, [r3, #8]
|
|
8003a0e: 019b lsls r3, r3, #6
|
|
8003a10: 431a orrs r2, r3
|
|
8003a12: 69fb ldr r3, [r7, #28]
|
|
8003a14: 085b lsrs r3, r3, #1
|
|
8003a16: 3b01 subs r3, #1
|
|
8003a18: 041b lsls r3, r3, #16
|
|
8003a1a: 431a orrs r2, r3
|
|
8003a1c: 687b ldr r3, [r7, #4]
|
|
8003a1e: 691b ldr r3, [r3, #16]
|
|
8003a20: 061b lsls r3, r3, #24
|
|
8003a22: 431a orrs r2, r3
|
|
8003a24: 697b ldr r3, [r7, #20]
|
|
8003a26: 071b lsls r3, r3, #28
|
|
8003a28: 4943 ldr r1, [pc, #268] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003a2a: 4313 orrs r3, r2
|
|
8003a2c: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
|
|
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
|
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
|
|
8003a30: 4b41 ldr r3, [pc, #260] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003a32: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8003a36: f023 021f bic.w r2, r3, #31
|
|
8003a3a: 687b ldr r3, [r7, #4]
|
|
8003a3c: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003a3e: 3b01 subs r3, #1
|
|
8003a40: 493d ldr r1, [pc, #244] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003a42: 4313 orrs r3, r2
|
|
8003a44: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
|
8003a48: 687b ldr r3, [r7, #4]
|
|
8003a4a: 681b ldr r3, [r3, #0]
|
|
8003a4c: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003a50: 2b00 cmp r3, #0
|
|
8003a52: d029 beq.n 8003aa8 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
|
|
&& (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
|
|
8003a54: 687b ldr r3, [r7, #4]
|
|
8003a56: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8003a58: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8003a5c: d124 bne.n 8003aa8 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
|
|
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
|
plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
8003a5e: 4b36 ldr r3, [pc, #216] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003a60: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003a64: 0c1b lsrs r3, r3, #16
|
|
8003a66: f003 0303 and.w r3, r3, #3
|
|
8003a6a: 3301 adds r3, #1
|
|
8003a6c: 005b lsls r3, r3, #1
|
|
8003a6e: 61bb str r3, [r7, #24]
|
|
plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
8003a70: 4b31 ldr r3, [pc, #196] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003a72: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003a76: 0f1b lsrs r3, r3, #28
|
|
8003a78: f003 0307 and.w r3, r3, #7
|
|
8003a7c: 617b str r3, [r7, #20]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP,
|
|
8003a7e: 687b ldr r3, [r7, #4]
|
|
8003a80: 685a ldr r2, [r3, #4]
|
|
8003a82: 687b ldr r3, [r7, #4]
|
|
8003a84: 689b ldr r3, [r3, #8]
|
|
8003a86: 019b lsls r3, r3, #6
|
|
8003a88: 431a orrs r2, r3
|
|
8003a8a: 687b ldr r3, [r7, #4]
|
|
8003a8c: 68db ldr r3, [r3, #12]
|
|
8003a8e: 085b lsrs r3, r3, #1
|
|
8003a90: 3b01 subs r3, #1
|
|
8003a92: 041b lsls r3, r3, #16
|
|
8003a94: 431a orrs r2, r3
|
|
8003a96: 69bb ldr r3, [r7, #24]
|
|
8003a98: 061b lsls r3, r3, #24
|
|
8003a9a: 431a orrs r2, r3
|
|
8003a9c: 697b ldr r3, [r7, #20]
|
|
8003a9e: 071b lsls r3, r3, #28
|
|
8003aa0: 4925 ldr r1, [pc, #148] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003aa2: 4313 orrs r3, r2
|
|
8003aa4: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
plli2sq, plli2sr);
|
|
}
|
|
|
|
/*----------------- In Case of PLLI2S is just selected -----------------*/
|
|
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
|
|
8003aa8: 687b ldr r3, [r7, #4]
|
|
8003aaa: 681b ldr r3, [r3, #0]
|
|
8003aac: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8003ab0: 2b00 cmp r3, #0
|
|
8003ab2: d016 beq.n 8003ae2 <HAL_RCCEx_PeriphCLKConfig+0x4e2>
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP,
|
|
8003ab4: 687b ldr r3, [r7, #4]
|
|
8003ab6: 685a ldr r2, [r3, #4]
|
|
8003ab8: 687b ldr r3, [r7, #4]
|
|
8003aba: 689b ldr r3, [r3, #8]
|
|
8003abc: 019b lsls r3, r3, #6
|
|
8003abe: 431a orrs r2, r3
|
|
8003ac0: 687b ldr r3, [r7, #4]
|
|
8003ac2: 68db ldr r3, [r3, #12]
|
|
8003ac4: 085b lsrs r3, r3, #1
|
|
8003ac6: 3b01 subs r3, #1
|
|
8003ac8: 041b lsls r3, r3, #16
|
|
8003aca: 431a orrs r2, r3
|
|
8003acc: 687b ldr r3, [r7, #4]
|
|
8003ace: 691b ldr r3, [r3, #16]
|
|
8003ad0: 061b lsls r3, r3, #24
|
|
8003ad2: 431a orrs r2, r3
|
|
8003ad4: 687b ldr r3, [r7, #4]
|
|
8003ad6: 695b ldr r3, [r3, #20]
|
|
8003ad8: 071b lsls r3, r3, #28
|
|
8003ada: 4917 ldr r1, [pc, #92] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003adc: 4313 orrs r3, r2
|
|
8003ade: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
|
|
}
|
|
|
|
/* Enable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_ENABLE();
|
|
8003ae2: 4b16 ldr r3, [pc, #88] @ (8003b3c <HAL_RCCEx_PeriphCLKConfig+0x53c>)
|
|
8003ae4: 2201 movs r2, #1
|
|
8003ae6: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003ae8: f7fd fd18 bl 800151c <HAL_GetTick>
|
|
8003aec: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLI2S is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
8003aee: e008 b.n 8003b02 <HAL_RCCEx_PeriphCLKConfig+0x502>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
8003af0: f7fd fd14 bl 800151c <HAL_GetTick>
|
|
8003af4: 4602 mov r2, r0
|
|
8003af6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003af8: 1ad3 subs r3, r2, r3
|
|
8003afa: 2b02 cmp r3, #2
|
|
8003afc: d901 bls.n 8003b02 <HAL_RCCEx_PeriphCLKConfig+0x502>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8003afe: 2303 movs r3, #3
|
|
8003b00: e09f b.n 8003c42 <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
8003b02: 4b0d ldr r3, [pc, #52] @ (8003b38 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003b04: 681b ldr r3, [r3, #0]
|
|
8003b06: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8003b0a: 2b00 cmp r3, #0
|
|
8003b0c: d0f0 beq.n 8003af0 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- PLLSAI Configuration -----------------------*/
|
|
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
|
|
if (pllsaiused == 1U)
|
|
8003b0e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003b10: 2b01 cmp r3, #1
|
|
8003b12: f040 8095 bne.w 8003c40 <HAL_RCCEx_PeriphCLKConfig+0x640>
|
|
{
|
|
/* Disable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_DISABLE();
|
|
8003b16: 4b0a ldr r3, [pc, #40] @ (8003b40 <HAL_RCCEx_PeriphCLKConfig+0x540>)
|
|
8003b18: 2200 movs r2, #0
|
|
8003b1a: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003b1c: f7fd fcfe bl 800151c <HAL_GetTick>
|
|
8003b20: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLSAI is disabled */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
8003b22: e00f b.n 8003b44 <HAL_RCCEx_PeriphCLKConfig+0x544>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
8003b24: f7fd fcfa bl 800151c <HAL_GetTick>
|
|
8003b28: 4602 mov r2, r0
|
|
8003b2a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003b2c: 1ad3 subs r3, r2, r3
|
|
8003b2e: 2b02 cmp r3, #2
|
|
8003b30: d908 bls.n 8003b44 <HAL_RCCEx_PeriphCLKConfig+0x544>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8003b32: 2303 movs r3, #3
|
|
8003b34: e085 b.n 8003c42 <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
8003b36: bf00 nop
|
|
8003b38: 40023800 .word 0x40023800
|
|
8003b3c: 42470068 .word 0x42470068
|
|
8003b40: 42470070 .word 0x42470070
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
8003b44: 4b41 ldr r3, [pc, #260] @ (8003c4c <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003b46: 681b ldr r3, [r3, #0]
|
|
8003b48: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8003b4c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8003b50: d0e8 beq.n 8003b24 <HAL_RCCEx_PeriphCLKConfig+0x524>
|
|
/* Check the PLLSAI division factors */
|
|
assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
|
|
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
|
|
|
|
/*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
|
|
8003b52: 687b ldr r3, [r7, #4]
|
|
8003b54: 681b ldr r3, [r3, #0]
|
|
8003b56: f003 0304 and.w r3, r3, #4
|
|
8003b5a: 2b00 cmp r3, #0
|
|
8003b5c: d003 beq.n 8003b66 <HAL_RCCEx_PeriphCLKConfig+0x566>
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
|
|
8003b5e: 687b ldr r3, [r7, #4]
|
|
8003b60: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8003b62: 2b00 cmp r3, #0
|
|
8003b64: d009 beq.n 8003b7a <HAL_RCCEx_PeriphCLKConfig+0x57a>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
|
8003b66: 687b ldr r3, [r7, #4]
|
|
8003b68: 681b ldr r3, [r3, #0]
|
|
8003b6a: f003 0308 and.w r3, r3, #8
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
|
|
8003b6e: 2b00 cmp r3, #0
|
|
8003b70: d02b beq.n 8003bca <HAL_RCCEx_PeriphCLKConfig+0x5ca>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
|
8003b72: 687b ldr r3, [r7, #4]
|
|
8003b74: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8003b76: 2b00 cmp r3, #0
|
|
8003b78: d127 bne.n 8003bca <HAL_RCCEx_PeriphCLKConfig+0x5ca>
|
|
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
|
|
/* check for PLLSAI/DIVQ Parameter */
|
|
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
|
|
|
|
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
|
|
pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
|
|
8003b7a: 4b34 ldr r3, [pc, #208] @ (8003c4c <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003b7c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003b80: 0c1b lsrs r3, r3, #16
|
|
8003b82: f003 0303 and.w r3, r3, #3
|
|
8003b86: 3301 adds r3, #1
|
|
8003b88: 005b lsls r3, r3, #1
|
|
8003b8a: 613b str r3, [r7, #16]
|
|
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
|
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip,
|
|
8003b8c: 687b ldr r3, [r7, #4]
|
|
8003b8e: 699a ldr r2, [r3, #24]
|
|
8003b90: 687b ldr r3, [r7, #4]
|
|
8003b92: 69db ldr r3, [r3, #28]
|
|
8003b94: 019b lsls r3, r3, #6
|
|
8003b96: 431a orrs r2, r3
|
|
8003b98: 693b ldr r3, [r7, #16]
|
|
8003b9a: 085b lsrs r3, r3, #1
|
|
8003b9c: 3b01 subs r3, #1
|
|
8003b9e: 041b lsls r3, r3, #16
|
|
8003ba0: 431a orrs r2, r3
|
|
8003ba2: 687b ldr r3, [r7, #4]
|
|
8003ba4: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003ba6: 061b lsls r3, r3, #24
|
|
8003ba8: 4928 ldr r1, [pc, #160] @ (8003c4c <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003baa: 4313 orrs r3, r2
|
|
8003bac: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
|
|
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
|
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
|
|
8003bb0: 4b26 ldr r3, [pc, #152] @ (8003c4c <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003bb2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8003bb6: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
|
|
8003bba: 687b ldr r3, [r7, #4]
|
|
8003bbc: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8003bbe: 3b01 subs r3, #1
|
|
8003bc0: 021b lsls r3, r3, #8
|
|
8003bc2: 4922 ldr r1, [pc, #136] @ (8003c4c <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003bc4: 4313 orrs r3, r2
|
|
8003bc6: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/
|
|
/* In Case of PLLI2S is selected as source clock for CLK48 */
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
|
|
8003bca: 687b ldr r3, [r7, #4]
|
|
8003bcc: 681b ldr r3, [r3, #0]
|
|
8003bce: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003bd2: 2b00 cmp r3, #0
|
|
8003bd4: d01d beq.n 8003c12 <HAL_RCCEx_PeriphCLKConfig+0x612>
|
|
&& (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
|
|
8003bd6: 687b ldr r3, [r7, #4]
|
|
8003bd8: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8003bda: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8003bde: d118 bne.n 8003c12 <HAL_RCCEx_PeriphCLKConfig+0x612>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
|
|
/* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
|
pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
|
|
8003be0: 4b1a ldr r3, [pc, #104] @ (8003c4c <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003be2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003be6: 0e1b lsrs r3, r3, #24
|
|
8003be8: f003 030f and.w r3, r3, #15
|
|
8003bec: 60fb str r3, [r7, #12]
|
|
/* Configure the PLLSAI division factors */
|
|
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
|
|
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP,
|
|
8003bee: 687b ldr r3, [r7, #4]
|
|
8003bf0: 699a ldr r2, [r3, #24]
|
|
8003bf2: 687b ldr r3, [r7, #4]
|
|
8003bf4: 69db ldr r3, [r3, #28]
|
|
8003bf6: 019b lsls r3, r3, #6
|
|
8003bf8: 431a orrs r2, r3
|
|
8003bfa: 687b ldr r3, [r7, #4]
|
|
8003bfc: 6a1b ldr r3, [r3, #32]
|
|
8003bfe: 085b lsrs r3, r3, #1
|
|
8003c00: 3b01 subs r3, #1
|
|
8003c02: 041b lsls r3, r3, #16
|
|
8003c04: 431a orrs r2, r3
|
|
8003c06: 68fb ldr r3, [r7, #12]
|
|
8003c08: 061b lsls r3, r3, #24
|
|
8003c0a: 4910 ldr r1, [pc, #64] @ (8003c4c <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003c0c: 4313 orrs r3, r2
|
|
8003c0e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
pllsaiq, 0U);
|
|
}
|
|
|
|
/* Enable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_ENABLE();
|
|
8003c12: 4b0f ldr r3, [pc, #60] @ (8003c50 <HAL_RCCEx_PeriphCLKConfig+0x650>)
|
|
8003c14: 2201 movs r2, #1
|
|
8003c16: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003c18: f7fd fc80 bl 800151c <HAL_GetTick>
|
|
8003c1c: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLSAI is ready */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
8003c1e: e008 b.n 8003c32 <HAL_RCCEx_PeriphCLKConfig+0x632>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
8003c20: f7fd fc7c bl 800151c <HAL_GetTick>
|
|
8003c24: 4602 mov r2, r0
|
|
8003c26: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003c28: 1ad3 subs r3, r2, r3
|
|
8003c2a: 2b02 cmp r3, #2
|
|
8003c2c: d901 bls.n 8003c32 <HAL_RCCEx_PeriphCLKConfig+0x632>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8003c2e: 2303 movs r3, #3
|
|
8003c30: e007 b.n 8003c42 <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
8003c32: 4b06 ldr r3, [pc, #24] @ (8003c4c <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003c34: 681b ldr r3, [r3, #0]
|
|
8003c36: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8003c3a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8003c3e: d1ef bne.n 8003c20 <HAL_RCCEx_PeriphCLKConfig+0x620>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8003c40: 2300 movs r3, #0
|
|
}
|
|
8003c42: 4618 mov r0, r3
|
|
8003c44: 3730 adds r7, #48 @ 0x30
|
|
8003c46: 46bd mov sp, r7
|
|
8003c48: bd80 pop {r7, pc}
|
|
8003c4a: bf00 nop
|
|
8003c4c: 40023800 .word 0x40023800
|
|
8003c50: 42470070 .word 0x42470070
|
|
|
|
08003c54 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8003c54: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8003c58: b0ae sub sp, #184 @ 0xb8
|
|
8003c5a: af00 add r7, sp, #0
|
|
uint32_t pllm = 0U;
|
|
8003c5c: 2300 movs r3, #0
|
|
8003c5e: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
uint32_t pllvco = 0U;
|
|
8003c62: 2300 movs r3, #0
|
|
8003c64: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
uint32_t pllp = 0U;
|
|
8003c68: 2300 movs r3, #0
|
|
8003c6a: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
uint32_t pllr = 0U;
|
|
8003c6e: 2300 movs r3, #0
|
|
8003c70: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
uint32_t sysclockfreq = 0U;
|
|
8003c74: 2300 movs r3, #0
|
|
8003c76: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
8003c7a: 4bcb ldr r3, [pc, #812] @ (8003fa8 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003c7c: 689b ldr r3, [r3, #8]
|
|
8003c7e: f003 030c and.w r3, r3, #12
|
|
8003c82: 2b0c cmp r3, #12
|
|
8003c84: f200 8206 bhi.w 8004094 <HAL_RCC_GetSysClockFreq+0x440>
|
|
8003c88: a201 add r2, pc, #4 @ (adr r2, 8003c90 <HAL_RCC_GetSysClockFreq+0x3c>)
|
|
8003c8a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8003c8e: bf00 nop
|
|
8003c90: 08003cc5 .word 0x08003cc5
|
|
8003c94: 08004095 .word 0x08004095
|
|
8003c98: 08004095 .word 0x08004095
|
|
8003c9c: 08004095 .word 0x08004095
|
|
8003ca0: 08003ccd .word 0x08003ccd
|
|
8003ca4: 08004095 .word 0x08004095
|
|
8003ca8: 08004095 .word 0x08004095
|
|
8003cac: 08004095 .word 0x08004095
|
|
8003cb0: 08003cd5 .word 0x08003cd5
|
|
8003cb4: 08004095 .word 0x08004095
|
|
8003cb8: 08004095 .word 0x08004095
|
|
8003cbc: 08004095 .word 0x08004095
|
|
8003cc0: 08003ec5 .word 0x08003ec5
|
|
{
|
|
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8003cc4: 4bb9 ldr r3, [pc, #740] @ (8003fac <HAL_RCC_GetSysClockFreq+0x358>)
|
|
8003cc6: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8003cca: e1e7 b.n 800409c <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8003ccc: 4bb8 ldr r3, [pc, #736] @ (8003fb0 <HAL_RCC_GetSysClockFreq+0x35c>)
|
|
8003cce: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8003cd2: e1e3 b.n 800409c <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLP */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
8003cd4: 4bb4 ldr r3, [pc, #720] @ (8003fa8 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003cd6: 685b ldr r3, [r3, #4]
|
|
8003cd8: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
8003cdc: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
8003ce0: 4bb1 ldr r3, [pc, #708] @ (8003fa8 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003ce2: 685b ldr r3, [r3, #4]
|
|
8003ce4: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8003ce8: 2b00 cmp r3, #0
|
|
8003cea: d071 beq.n 8003dd0 <HAL_RCC_GetSysClockFreq+0x17c>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8003cec: 4bae ldr r3, [pc, #696] @ (8003fa8 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003cee: 685b ldr r3, [r3, #4]
|
|
8003cf0: 099b lsrs r3, r3, #6
|
|
8003cf2: 2200 movs r2, #0
|
|
8003cf4: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8003cf8: f8c7 209c str.w r2, [r7, #156] @ 0x9c
|
|
8003cfc: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8003d00: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8003d04: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8003d08: 2300 movs r3, #0
|
|
8003d0a: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
8003d0e: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
|
|
8003d12: 4622 mov r2, r4
|
|
8003d14: 462b mov r3, r5
|
|
8003d16: f04f 0000 mov.w r0, #0
|
|
8003d1a: f04f 0100 mov.w r1, #0
|
|
8003d1e: 0159 lsls r1, r3, #5
|
|
8003d20: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8003d24: 0150 lsls r0, r2, #5
|
|
8003d26: 4602 mov r2, r0
|
|
8003d28: 460b mov r3, r1
|
|
8003d2a: 4621 mov r1, r4
|
|
8003d2c: 1a51 subs r1, r2, r1
|
|
8003d2e: 6439 str r1, [r7, #64] @ 0x40
|
|
8003d30: 4629 mov r1, r5
|
|
8003d32: eb63 0301 sbc.w r3, r3, r1
|
|
8003d36: 647b str r3, [r7, #68] @ 0x44
|
|
8003d38: f04f 0200 mov.w r2, #0
|
|
8003d3c: f04f 0300 mov.w r3, #0
|
|
8003d40: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40
|
|
8003d44: 4649 mov r1, r9
|
|
8003d46: 018b lsls r3, r1, #6
|
|
8003d48: 4641 mov r1, r8
|
|
8003d4a: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8003d4e: 4641 mov r1, r8
|
|
8003d50: 018a lsls r2, r1, #6
|
|
8003d52: 4641 mov r1, r8
|
|
8003d54: 1a51 subs r1, r2, r1
|
|
8003d56: 63b9 str r1, [r7, #56] @ 0x38
|
|
8003d58: 4649 mov r1, r9
|
|
8003d5a: eb63 0301 sbc.w r3, r3, r1
|
|
8003d5e: 63fb str r3, [r7, #60] @ 0x3c
|
|
8003d60: f04f 0200 mov.w r2, #0
|
|
8003d64: f04f 0300 mov.w r3, #0
|
|
8003d68: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38
|
|
8003d6c: 4649 mov r1, r9
|
|
8003d6e: 00cb lsls r3, r1, #3
|
|
8003d70: 4641 mov r1, r8
|
|
8003d72: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8003d76: 4641 mov r1, r8
|
|
8003d78: 00ca lsls r2, r1, #3
|
|
8003d7a: 4610 mov r0, r2
|
|
8003d7c: 4619 mov r1, r3
|
|
8003d7e: 4603 mov r3, r0
|
|
8003d80: 4622 mov r2, r4
|
|
8003d82: 189b adds r3, r3, r2
|
|
8003d84: 633b str r3, [r7, #48] @ 0x30
|
|
8003d86: 462b mov r3, r5
|
|
8003d88: 460a mov r2, r1
|
|
8003d8a: eb42 0303 adc.w r3, r2, r3
|
|
8003d8e: 637b str r3, [r7, #52] @ 0x34
|
|
8003d90: f04f 0200 mov.w r2, #0
|
|
8003d94: f04f 0300 mov.w r3, #0
|
|
8003d98: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30
|
|
8003d9c: 4629 mov r1, r5
|
|
8003d9e: 024b lsls r3, r1, #9
|
|
8003da0: 4621 mov r1, r4
|
|
8003da2: ea43 53d1 orr.w r3, r3, r1, lsr #23
|
|
8003da6: 4621 mov r1, r4
|
|
8003da8: 024a lsls r2, r1, #9
|
|
8003daa: 4610 mov r0, r2
|
|
8003dac: 4619 mov r1, r3
|
|
8003dae: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8003db2: 2200 movs r2, #0
|
|
8003db4: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
8003db8: f8c7 208c str.w r2, [r7, #140] @ 0x8c
|
|
8003dbc: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88
|
|
8003dc0: f7fc fa20 bl 8000204 <__aeabi_uldivmod>
|
|
8003dc4: 4602 mov r2, r0
|
|
8003dc6: 460b mov r3, r1
|
|
8003dc8: 4613 mov r3, r2
|
|
8003dca: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8003dce: e067 b.n 8003ea0 <HAL_RCC_GetSysClockFreq+0x24c>
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8003dd0: 4b75 ldr r3, [pc, #468] @ (8003fa8 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003dd2: 685b ldr r3, [r3, #4]
|
|
8003dd4: 099b lsrs r3, r3, #6
|
|
8003dd6: 2200 movs r2, #0
|
|
8003dd8: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8003ddc: f8c7 2084 str.w r2, [r7, #132] @ 0x84
|
|
8003de0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
8003de4: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8003de8: 67bb str r3, [r7, #120] @ 0x78
|
|
8003dea: 2300 movs r3, #0
|
|
8003dec: 67fb str r3, [r7, #124] @ 0x7c
|
|
8003dee: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78
|
|
8003df2: 4622 mov r2, r4
|
|
8003df4: 462b mov r3, r5
|
|
8003df6: f04f 0000 mov.w r0, #0
|
|
8003dfa: f04f 0100 mov.w r1, #0
|
|
8003dfe: 0159 lsls r1, r3, #5
|
|
8003e00: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8003e04: 0150 lsls r0, r2, #5
|
|
8003e06: 4602 mov r2, r0
|
|
8003e08: 460b mov r3, r1
|
|
8003e0a: 4621 mov r1, r4
|
|
8003e0c: 1a51 subs r1, r2, r1
|
|
8003e0e: 62b9 str r1, [r7, #40] @ 0x28
|
|
8003e10: 4629 mov r1, r5
|
|
8003e12: eb63 0301 sbc.w r3, r3, r1
|
|
8003e16: 62fb str r3, [r7, #44] @ 0x2c
|
|
8003e18: f04f 0200 mov.w r2, #0
|
|
8003e1c: f04f 0300 mov.w r3, #0
|
|
8003e20: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28
|
|
8003e24: 4649 mov r1, r9
|
|
8003e26: 018b lsls r3, r1, #6
|
|
8003e28: 4641 mov r1, r8
|
|
8003e2a: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8003e2e: 4641 mov r1, r8
|
|
8003e30: 018a lsls r2, r1, #6
|
|
8003e32: 4641 mov r1, r8
|
|
8003e34: ebb2 0a01 subs.w sl, r2, r1
|
|
8003e38: 4649 mov r1, r9
|
|
8003e3a: eb63 0b01 sbc.w fp, r3, r1
|
|
8003e3e: f04f 0200 mov.w r2, #0
|
|
8003e42: f04f 0300 mov.w r3, #0
|
|
8003e46: ea4f 03cb mov.w r3, fp, lsl #3
|
|
8003e4a: ea43 735a orr.w r3, r3, sl, lsr #29
|
|
8003e4e: ea4f 02ca mov.w r2, sl, lsl #3
|
|
8003e52: 4692 mov sl, r2
|
|
8003e54: 469b mov fp, r3
|
|
8003e56: 4623 mov r3, r4
|
|
8003e58: eb1a 0303 adds.w r3, sl, r3
|
|
8003e5c: 623b str r3, [r7, #32]
|
|
8003e5e: 462b mov r3, r5
|
|
8003e60: eb4b 0303 adc.w r3, fp, r3
|
|
8003e64: 627b str r3, [r7, #36] @ 0x24
|
|
8003e66: f04f 0200 mov.w r2, #0
|
|
8003e6a: f04f 0300 mov.w r3, #0
|
|
8003e6e: e9d7 4508 ldrd r4, r5, [r7, #32]
|
|
8003e72: 4629 mov r1, r5
|
|
8003e74: 028b lsls r3, r1, #10
|
|
8003e76: 4621 mov r1, r4
|
|
8003e78: ea43 5391 orr.w r3, r3, r1, lsr #22
|
|
8003e7c: 4621 mov r1, r4
|
|
8003e7e: 028a lsls r2, r1, #10
|
|
8003e80: 4610 mov r0, r2
|
|
8003e82: 4619 mov r1, r3
|
|
8003e84: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8003e88: 2200 movs r2, #0
|
|
8003e8a: 673b str r3, [r7, #112] @ 0x70
|
|
8003e8c: 677a str r2, [r7, #116] @ 0x74
|
|
8003e8e: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70
|
|
8003e92: f7fc f9b7 bl 8000204 <__aeabi_uldivmod>
|
|
8003e96: 4602 mov r2, r0
|
|
8003e98: 460b mov r3, r1
|
|
8003e9a: 4613 mov r3, r2
|
|
8003e9c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
}
|
|
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
|
|
8003ea0: 4b41 ldr r3, [pc, #260] @ (8003fa8 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003ea2: 685b ldr r3, [r3, #4]
|
|
8003ea4: 0c1b lsrs r3, r3, #16
|
|
8003ea6: f003 0303 and.w r3, r3, #3
|
|
8003eaa: 3301 adds r3, #1
|
|
8003eac: 005b lsls r3, r3, #1
|
|
8003eae: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
|
|
sysclockfreq = pllvco / pllp;
|
|
8003eb2: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
8003eb6: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8003eba: fbb2 f3f3 udiv r3, r2, r3
|
|
8003ebe: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8003ec2: e0eb b.n 800409c <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLR */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
8003ec4: 4b38 ldr r3, [pc, #224] @ (8003fa8 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003ec6: 685b ldr r3, [r3, #4]
|
|
8003ec8: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
8003ecc: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
8003ed0: 4b35 ldr r3, [pc, #212] @ (8003fa8 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003ed2: 685b ldr r3, [r3, #4]
|
|
8003ed4: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8003ed8: 2b00 cmp r3, #0
|
|
8003eda: d06b beq.n 8003fb4 <HAL_RCC_GetSysClockFreq+0x360>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8003edc: 4b32 ldr r3, [pc, #200] @ (8003fa8 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003ede: 685b ldr r3, [r3, #4]
|
|
8003ee0: 099b lsrs r3, r3, #6
|
|
8003ee2: 2200 movs r2, #0
|
|
8003ee4: 66bb str r3, [r7, #104] @ 0x68
|
|
8003ee6: 66fa str r2, [r7, #108] @ 0x6c
|
|
8003ee8: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8003eea: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8003eee: 663b str r3, [r7, #96] @ 0x60
|
|
8003ef0: 2300 movs r3, #0
|
|
8003ef2: 667b str r3, [r7, #100] @ 0x64
|
|
8003ef4: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60
|
|
8003ef8: 4622 mov r2, r4
|
|
8003efa: 462b mov r3, r5
|
|
8003efc: f04f 0000 mov.w r0, #0
|
|
8003f00: f04f 0100 mov.w r1, #0
|
|
8003f04: 0159 lsls r1, r3, #5
|
|
8003f06: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8003f0a: 0150 lsls r0, r2, #5
|
|
8003f0c: 4602 mov r2, r0
|
|
8003f0e: 460b mov r3, r1
|
|
8003f10: 4621 mov r1, r4
|
|
8003f12: 1a51 subs r1, r2, r1
|
|
8003f14: 61b9 str r1, [r7, #24]
|
|
8003f16: 4629 mov r1, r5
|
|
8003f18: eb63 0301 sbc.w r3, r3, r1
|
|
8003f1c: 61fb str r3, [r7, #28]
|
|
8003f1e: f04f 0200 mov.w r2, #0
|
|
8003f22: f04f 0300 mov.w r3, #0
|
|
8003f26: e9d7 ab06 ldrd sl, fp, [r7, #24]
|
|
8003f2a: 4659 mov r1, fp
|
|
8003f2c: 018b lsls r3, r1, #6
|
|
8003f2e: 4651 mov r1, sl
|
|
8003f30: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8003f34: 4651 mov r1, sl
|
|
8003f36: 018a lsls r2, r1, #6
|
|
8003f38: 4651 mov r1, sl
|
|
8003f3a: ebb2 0801 subs.w r8, r2, r1
|
|
8003f3e: 4659 mov r1, fp
|
|
8003f40: eb63 0901 sbc.w r9, r3, r1
|
|
8003f44: f04f 0200 mov.w r2, #0
|
|
8003f48: f04f 0300 mov.w r3, #0
|
|
8003f4c: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8003f50: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8003f54: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
8003f58: 4690 mov r8, r2
|
|
8003f5a: 4699 mov r9, r3
|
|
8003f5c: 4623 mov r3, r4
|
|
8003f5e: eb18 0303 adds.w r3, r8, r3
|
|
8003f62: 613b str r3, [r7, #16]
|
|
8003f64: 462b mov r3, r5
|
|
8003f66: eb49 0303 adc.w r3, r9, r3
|
|
8003f6a: 617b str r3, [r7, #20]
|
|
8003f6c: f04f 0200 mov.w r2, #0
|
|
8003f70: f04f 0300 mov.w r3, #0
|
|
8003f74: e9d7 4504 ldrd r4, r5, [r7, #16]
|
|
8003f78: 4629 mov r1, r5
|
|
8003f7a: 024b lsls r3, r1, #9
|
|
8003f7c: 4621 mov r1, r4
|
|
8003f7e: ea43 53d1 orr.w r3, r3, r1, lsr #23
|
|
8003f82: 4621 mov r1, r4
|
|
8003f84: 024a lsls r2, r1, #9
|
|
8003f86: 4610 mov r0, r2
|
|
8003f88: 4619 mov r1, r3
|
|
8003f8a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8003f8e: 2200 movs r2, #0
|
|
8003f90: 65bb str r3, [r7, #88] @ 0x58
|
|
8003f92: 65fa str r2, [r7, #92] @ 0x5c
|
|
8003f94: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
|
|
8003f98: f7fc f934 bl 8000204 <__aeabi_uldivmod>
|
|
8003f9c: 4602 mov r2, r0
|
|
8003f9e: 460b mov r3, r1
|
|
8003fa0: 4613 mov r3, r2
|
|
8003fa2: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8003fa6: e065 b.n 8004074 <HAL_RCC_GetSysClockFreq+0x420>
|
|
8003fa8: 40023800 .word 0x40023800
|
|
8003fac: 00f42400 .word 0x00f42400
|
|
8003fb0: 007a1200 .word 0x007a1200
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8003fb4: 4b3d ldr r3, [pc, #244] @ (80040ac <HAL_RCC_GetSysClockFreq+0x458>)
|
|
8003fb6: 685b ldr r3, [r3, #4]
|
|
8003fb8: 099b lsrs r3, r3, #6
|
|
8003fba: 2200 movs r2, #0
|
|
8003fbc: 4618 mov r0, r3
|
|
8003fbe: 4611 mov r1, r2
|
|
8003fc0: f3c0 0308 ubfx r3, r0, #0, #9
|
|
8003fc4: 653b str r3, [r7, #80] @ 0x50
|
|
8003fc6: 2300 movs r3, #0
|
|
8003fc8: 657b str r3, [r7, #84] @ 0x54
|
|
8003fca: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50
|
|
8003fce: 4642 mov r2, r8
|
|
8003fd0: 464b mov r3, r9
|
|
8003fd2: f04f 0000 mov.w r0, #0
|
|
8003fd6: f04f 0100 mov.w r1, #0
|
|
8003fda: 0159 lsls r1, r3, #5
|
|
8003fdc: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8003fe0: 0150 lsls r0, r2, #5
|
|
8003fe2: 4602 mov r2, r0
|
|
8003fe4: 460b mov r3, r1
|
|
8003fe6: 4641 mov r1, r8
|
|
8003fe8: 1a51 subs r1, r2, r1
|
|
8003fea: 60b9 str r1, [r7, #8]
|
|
8003fec: 4649 mov r1, r9
|
|
8003fee: eb63 0301 sbc.w r3, r3, r1
|
|
8003ff2: 60fb str r3, [r7, #12]
|
|
8003ff4: f04f 0200 mov.w r2, #0
|
|
8003ff8: f04f 0300 mov.w r3, #0
|
|
8003ffc: e9d7 ab02 ldrd sl, fp, [r7, #8]
|
|
8004000: 4659 mov r1, fp
|
|
8004002: 018b lsls r3, r1, #6
|
|
8004004: 4651 mov r1, sl
|
|
8004006: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
800400a: 4651 mov r1, sl
|
|
800400c: 018a lsls r2, r1, #6
|
|
800400e: 4651 mov r1, sl
|
|
8004010: 1a54 subs r4, r2, r1
|
|
8004012: 4659 mov r1, fp
|
|
8004014: eb63 0501 sbc.w r5, r3, r1
|
|
8004018: f04f 0200 mov.w r2, #0
|
|
800401c: f04f 0300 mov.w r3, #0
|
|
8004020: 00eb lsls r3, r5, #3
|
|
8004022: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
8004026: 00e2 lsls r2, r4, #3
|
|
8004028: 4614 mov r4, r2
|
|
800402a: 461d mov r5, r3
|
|
800402c: 4643 mov r3, r8
|
|
800402e: 18e3 adds r3, r4, r3
|
|
8004030: 603b str r3, [r7, #0]
|
|
8004032: 464b mov r3, r9
|
|
8004034: eb45 0303 adc.w r3, r5, r3
|
|
8004038: 607b str r3, [r7, #4]
|
|
800403a: f04f 0200 mov.w r2, #0
|
|
800403e: f04f 0300 mov.w r3, #0
|
|
8004042: e9d7 4500 ldrd r4, r5, [r7]
|
|
8004046: 4629 mov r1, r5
|
|
8004048: 028b lsls r3, r1, #10
|
|
800404a: 4621 mov r1, r4
|
|
800404c: ea43 5391 orr.w r3, r3, r1, lsr #22
|
|
8004050: 4621 mov r1, r4
|
|
8004052: 028a lsls r2, r1, #10
|
|
8004054: 4610 mov r0, r2
|
|
8004056: 4619 mov r1, r3
|
|
8004058: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
800405c: 2200 movs r2, #0
|
|
800405e: 64bb str r3, [r7, #72] @ 0x48
|
|
8004060: 64fa str r2, [r7, #76] @ 0x4c
|
|
8004062: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
|
|
8004066: f7fc f8cd bl 8000204 <__aeabi_uldivmod>
|
|
800406a: 4602 mov r2, r0
|
|
800406c: 460b mov r3, r1
|
|
800406e: 4613 mov r3, r2
|
|
8004070: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
}
|
|
pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
|
|
8004074: 4b0d ldr r3, [pc, #52] @ (80040ac <HAL_RCC_GetSysClockFreq+0x458>)
|
|
8004076: 685b ldr r3, [r3, #4]
|
|
8004078: 0f1b lsrs r3, r3, #28
|
|
800407a: f003 0307 and.w r3, r3, #7
|
|
800407e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
|
|
sysclockfreq = pllvco / pllr;
|
|
8004082: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
8004086: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
800408a: fbb2 f3f3 udiv r3, r2, r3
|
|
800408e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8004092: e003 b.n 800409c <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
default:
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8004094: 4b06 ldr r3, [pc, #24] @ (80040b0 <HAL_RCC_GetSysClockFreq+0x45c>)
|
|
8004096: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
800409a: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
800409c: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
|
|
}
|
|
80040a0: 4618 mov r0, r3
|
|
80040a2: 37b8 adds r7, #184 @ 0xb8
|
|
80040a4: 46bd mov sp, r7
|
|
80040a6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
80040aa: bf00 nop
|
|
80040ac: 40023800 .word 0x40023800
|
|
80040b0: 00f42400 .word 0x00f42400
|
|
|
|
080040b4 <HAL_RCC_OscConfig>:
|
|
* @note This function add the PLL/PLLR factor management during PLL configuration this feature
|
|
* is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
80040b4: b580 push {r7, lr}
|
|
80040b6: b086 sub sp, #24
|
|
80040b8: af00 add r7, sp, #0
|
|
80040ba: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
80040bc: 687b ldr r3, [r7, #4]
|
|
80040be: 2b00 cmp r3, #0
|
|
80040c0: d101 bne.n 80040c6 <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80040c2: 2301 movs r3, #1
|
|
80040c4: e28d b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
80040c6: 687b ldr r3, [r7, #4]
|
|
80040c8: 681b ldr r3, [r3, #0]
|
|
80040ca: f003 0301 and.w r3, r3, #1
|
|
80040ce: 2b00 cmp r3, #0
|
|
80040d0: f000 8083 beq.w 80041da <HAL_RCC_OscConfig+0x126>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
|
|
#if defined(STM32F446xx)
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
80040d4: 4b94 ldr r3, [pc, #592] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
80040d6: 689b ldr r3, [r3, #8]
|
|
80040d8: f003 030c and.w r3, r3, #12
|
|
80040dc: 2b04 cmp r3, #4
|
|
80040de: d019 beq.n 8004114 <HAL_RCC_OscConfig+0x60>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
80040e0: 4b91 ldr r3, [pc, #580] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
80040e2: 689b ldr r3, [r3, #8]
|
|
80040e4: f003 030c and.w r3, r3, #12
|
|
|| \
|
|
80040e8: 2b08 cmp r3, #8
|
|
80040ea: d106 bne.n 80040fa <HAL_RCC_OscConfig+0x46>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
80040ec: 4b8e ldr r3, [pc, #568] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
80040ee: 685b ldr r3, [r3, #4]
|
|
80040f0: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80040f4: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80040f8: d00c beq.n 8004114 <HAL_RCC_OscConfig+0x60>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
80040fa: 4b8b ldr r3, [pc, #556] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
80040fc: 689b ldr r3, [r3, #8]
|
|
80040fe: f003 030c and.w r3, r3, #12
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
8004102: 2b0c cmp r3, #12
|
|
8004104: d112 bne.n 800412c <HAL_RCC_OscConfig+0x78>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
8004106: 4b88 ldr r3, [pc, #544] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
8004108: 685b ldr r3, [r3, #4]
|
|
800410a: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
800410e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
8004112: d10b bne.n 800412c <HAL_RCC_OscConfig+0x78>
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
#endif /* STM32F446xx */
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8004114: 4b84 ldr r3, [pc, #528] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
8004116: 681b ldr r3, [r3, #0]
|
|
8004118: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800411c: 2b00 cmp r3, #0
|
|
800411e: d05b beq.n 80041d8 <HAL_RCC_OscConfig+0x124>
|
|
8004120: 687b ldr r3, [r7, #4]
|
|
8004122: 685b ldr r3, [r3, #4]
|
|
8004124: 2b00 cmp r3, #0
|
|
8004126: d157 bne.n 80041d8 <HAL_RCC_OscConfig+0x124>
|
|
{
|
|
return HAL_ERROR;
|
|
8004128: 2301 movs r3, #1
|
|
800412a: e25a b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
800412c: 687b ldr r3, [r7, #4]
|
|
800412e: 685b ldr r3, [r3, #4]
|
|
8004130: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8004134: d106 bne.n 8004144 <HAL_RCC_OscConfig+0x90>
|
|
8004136: 4b7c ldr r3, [pc, #496] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
8004138: 681b ldr r3, [r3, #0]
|
|
800413a: 4a7b ldr r2, [pc, #492] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
800413c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004140: 6013 str r3, [r2, #0]
|
|
8004142: e01d b.n 8004180 <HAL_RCC_OscConfig+0xcc>
|
|
8004144: 687b ldr r3, [r7, #4]
|
|
8004146: 685b ldr r3, [r3, #4]
|
|
8004148: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
800414c: d10c bne.n 8004168 <HAL_RCC_OscConfig+0xb4>
|
|
800414e: 4b76 ldr r3, [pc, #472] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
8004150: 681b ldr r3, [r3, #0]
|
|
8004152: 4a75 ldr r2, [pc, #468] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
8004154: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8004158: 6013 str r3, [r2, #0]
|
|
800415a: 4b73 ldr r3, [pc, #460] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
800415c: 681b ldr r3, [r3, #0]
|
|
800415e: 4a72 ldr r2, [pc, #456] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
8004160: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004164: 6013 str r3, [r2, #0]
|
|
8004166: e00b b.n 8004180 <HAL_RCC_OscConfig+0xcc>
|
|
8004168: 4b6f ldr r3, [pc, #444] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
800416a: 681b ldr r3, [r3, #0]
|
|
800416c: 4a6e ldr r2, [pc, #440] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
800416e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8004172: 6013 str r3, [r2, #0]
|
|
8004174: 4b6c ldr r3, [pc, #432] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
8004176: 681b ldr r3, [r3, #0]
|
|
8004178: 4a6b ldr r2, [pc, #428] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
800417a: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
800417e: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
|
|
8004180: 687b ldr r3, [r7, #4]
|
|
8004182: 685b ldr r3, [r3, #4]
|
|
8004184: 2b00 cmp r3, #0
|
|
8004186: d013 beq.n 80041b0 <HAL_RCC_OscConfig+0xfc>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004188: f7fd f9c8 bl 800151c <HAL_GetTick>
|
|
800418c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
800418e: e008 b.n 80041a2 <HAL_RCC_OscConfig+0xee>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8004190: f7fd f9c4 bl 800151c <HAL_GetTick>
|
|
8004194: 4602 mov r2, r0
|
|
8004196: 693b ldr r3, [r7, #16]
|
|
8004198: 1ad3 subs r3, r2, r3
|
|
800419a: 2b64 cmp r3, #100 @ 0x64
|
|
800419c: d901 bls.n 80041a2 <HAL_RCC_OscConfig+0xee>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800419e: 2303 movs r3, #3
|
|
80041a0: e21f b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
80041a2: 4b61 ldr r3, [pc, #388] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
80041a4: 681b ldr r3, [r3, #0]
|
|
80041a6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80041aa: 2b00 cmp r3, #0
|
|
80041ac: d0f0 beq.n 8004190 <HAL_RCC_OscConfig+0xdc>
|
|
80041ae: e014 b.n 80041da <HAL_RCC_OscConfig+0x126>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80041b0: f7fd f9b4 bl 800151c <HAL_GetTick>
|
|
80041b4: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is bypassed or disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
80041b6: e008 b.n 80041ca <HAL_RCC_OscConfig+0x116>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
80041b8: f7fd f9b0 bl 800151c <HAL_GetTick>
|
|
80041bc: 4602 mov r2, r0
|
|
80041be: 693b ldr r3, [r7, #16]
|
|
80041c0: 1ad3 subs r3, r2, r3
|
|
80041c2: 2b64 cmp r3, #100 @ 0x64
|
|
80041c4: d901 bls.n 80041ca <HAL_RCC_OscConfig+0x116>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80041c6: 2303 movs r3, #3
|
|
80041c8: e20b b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
80041ca: 4b57 ldr r3, [pc, #348] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
80041cc: 681b ldr r3, [r3, #0]
|
|
80041ce: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80041d2: 2b00 cmp r3, #0
|
|
80041d4: d1f0 bne.n 80041b8 <HAL_RCC_OscConfig+0x104>
|
|
80041d6: e000 b.n 80041da <HAL_RCC_OscConfig+0x126>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
80041d8: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
80041da: 687b ldr r3, [r7, #4]
|
|
80041dc: 681b ldr r3, [r3, #0]
|
|
80041de: f003 0302 and.w r3, r3, #2
|
|
80041e2: 2b00 cmp r3, #0
|
|
80041e4: d06f beq.n 80042c6 <HAL_RCC_OscConfig+0x212>
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
#if defined(STM32F446xx)
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
|
|
80041e6: 4b50 ldr r3, [pc, #320] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
80041e8: 689b ldr r3, [r3, #8]
|
|
80041ea: f003 030c and.w r3, r3, #12
|
|
80041ee: 2b00 cmp r3, #0
|
|
80041f0: d017 beq.n 8004222 <HAL_RCC_OscConfig+0x16e>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
80041f2: 4b4d ldr r3, [pc, #308] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
80041f4: 689b ldr r3, [r3, #8]
|
|
80041f6: f003 030c and.w r3, r3, #12
|
|
|| \
|
|
80041fa: 2b08 cmp r3, #8
|
|
80041fc: d105 bne.n 800420a <HAL_RCC_OscConfig+0x156>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
80041fe: 4b4a ldr r3, [pc, #296] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
8004200: 685b ldr r3, [r3, #4]
|
|
8004202: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004206: 2b00 cmp r3, #0
|
|
8004208: d00b beq.n 8004222 <HAL_RCC_OscConfig+0x16e>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
800420a: 4b47 ldr r3, [pc, #284] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
800420c: 689b ldr r3, [r3, #8]
|
|
800420e: f003 030c and.w r3, r3, #12
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
8004212: 2b0c cmp r3, #12
|
|
8004214: d11c bne.n 8004250 <HAL_RCC_OscConfig+0x19c>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
8004216: 4b44 ldr r3, [pc, #272] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
8004218: 685b ldr r3, [r3, #4]
|
|
800421a: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
800421e: 2b00 cmp r3, #0
|
|
8004220: d116 bne.n 8004250 <HAL_RCC_OscConfig+0x19c>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
#endif /* STM32F446xx */
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8004222: 4b41 ldr r3, [pc, #260] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
8004224: 681b ldr r3, [r3, #0]
|
|
8004226: f003 0302 and.w r3, r3, #2
|
|
800422a: 2b00 cmp r3, #0
|
|
800422c: d005 beq.n 800423a <HAL_RCC_OscConfig+0x186>
|
|
800422e: 687b ldr r3, [r7, #4]
|
|
8004230: 68db ldr r3, [r3, #12]
|
|
8004232: 2b01 cmp r3, #1
|
|
8004234: d001 beq.n 800423a <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
return HAL_ERROR;
|
|
8004236: 2301 movs r3, #1
|
|
8004238: e1d3 b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
800423a: 4b3b ldr r3, [pc, #236] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
800423c: 681b ldr r3, [r3, #0]
|
|
800423e: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8004242: 687b ldr r3, [r7, #4]
|
|
8004244: 691b ldr r3, [r3, #16]
|
|
8004246: 00db lsls r3, r3, #3
|
|
8004248: 4937 ldr r1, [pc, #220] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
800424a: 4313 orrs r3, r2
|
|
800424c: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
800424e: e03a b.n 80042c6 <HAL_RCC_OscConfig+0x212>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
|
|
8004250: 687b ldr r3, [r7, #4]
|
|
8004252: 68db ldr r3, [r3, #12]
|
|
8004254: 2b00 cmp r3, #0
|
|
8004256: d020 beq.n 800429a <HAL_RCC_OscConfig+0x1e6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8004258: 4b34 ldr r3, [pc, #208] @ (800432c <HAL_RCC_OscConfig+0x278>)
|
|
800425a: 2201 movs r2, #1
|
|
800425c: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800425e: f7fd f95d bl 800151c <HAL_GetTick>
|
|
8004262: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004264: e008 b.n 8004278 <HAL_RCC_OscConfig+0x1c4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8004266: f7fd f959 bl 800151c <HAL_GetTick>
|
|
800426a: 4602 mov r2, r0
|
|
800426c: 693b ldr r3, [r7, #16]
|
|
800426e: 1ad3 subs r3, r2, r3
|
|
8004270: 2b02 cmp r3, #2
|
|
8004272: d901 bls.n 8004278 <HAL_RCC_OscConfig+0x1c4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004274: 2303 movs r3, #3
|
|
8004276: e1b4 b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004278: 4b2b ldr r3, [pc, #172] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
800427a: 681b ldr r3, [r3, #0]
|
|
800427c: f003 0302 and.w r3, r3, #2
|
|
8004280: 2b00 cmp r3, #0
|
|
8004282: d0f0 beq.n 8004266 <HAL_RCC_OscConfig+0x1b2>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8004284: 4b28 ldr r3, [pc, #160] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
8004286: 681b ldr r3, [r3, #0]
|
|
8004288: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
800428c: 687b ldr r3, [r7, #4]
|
|
800428e: 691b ldr r3, [r3, #16]
|
|
8004290: 00db lsls r3, r3, #3
|
|
8004292: 4925 ldr r1, [pc, #148] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
8004294: 4313 orrs r3, r2
|
|
8004296: 600b str r3, [r1, #0]
|
|
8004298: e015 b.n 80042c6 <HAL_RCC_OscConfig+0x212>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
800429a: 4b24 ldr r3, [pc, #144] @ (800432c <HAL_RCC_OscConfig+0x278>)
|
|
800429c: 2200 movs r2, #0
|
|
800429e: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80042a0: f7fd f93c bl 800151c <HAL_GetTick>
|
|
80042a4: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
80042a6: e008 b.n 80042ba <HAL_RCC_OscConfig+0x206>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
80042a8: f7fd f938 bl 800151c <HAL_GetTick>
|
|
80042ac: 4602 mov r2, r0
|
|
80042ae: 693b ldr r3, [r7, #16]
|
|
80042b0: 1ad3 subs r3, r2, r3
|
|
80042b2: 2b02 cmp r3, #2
|
|
80042b4: d901 bls.n 80042ba <HAL_RCC_OscConfig+0x206>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80042b6: 2303 movs r3, #3
|
|
80042b8: e193 b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
80042ba: 4b1b ldr r3, [pc, #108] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
80042bc: 681b ldr r3, [r3, #0]
|
|
80042be: f003 0302 and.w r3, r3, #2
|
|
80042c2: 2b00 cmp r3, #0
|
|
80042c4: d1f0 bne.n 80042a8 <HAL_RCC_OscConfig+0x1f4>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
80042c6: 687b ldr r3, [r7, #4]
|
|
80042c8: 681b ldr r3, [r3, #0]
|
|
80042ca: f003 0308 and.w r3, r3, #8
|
|
80042ce: 2b00 cmp r3, #0
|
|
80042d0: d036 beq.n 8004340 <HAL_RCC_OscConfig+0x28c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
|
|
80042d2: 687b ldr r3, [r7, #4]
|
|
80042d4: 695b ldr r3, [r3, #20]
|
|
80042d6: 2b00 cmp r3, #0
|
|
80042d8: d016 beq.n 8004308 <HAL_RCC_OscConfig+0x254>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
80042da: 4b15 ldr r3, [pc, #84] @ (8004330 <HAL_RCC_OscConfig+0x27c>)
|
|
80042dc: 2201 movs r2, #1
|
|
80042de: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80042e0: f7fd f91c bl 800151c <HAL_GetTick>
|
|
80042e4: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80042e6: e008 b.n 80042fa <HAL_RCC_OscConfig+0x246>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
80042e8: f7fd f918 bl 800151c <HAL_GetTick>
|
|
80042ec: 4602 mov r2, r0
|
|
80042ee: 693b ldr r3, [r7, #16]
|
|
80042f0: 1ad3 subs r3, r2, r3
|
|
80042f2: 2b02 cmp r3, #2
|
|
80042f4: d901 bls.n 80042fa <HAL_RCC_OscConfig+0x246>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80042f6: 2303 movs r3, #3
|
|
80042f8: e173 b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80042fa: 4b0b ldr r3, [pc, #44] @ (8004328 <HAL_RCC_OscConfig+0x274>)
|
|
80042fc: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80042fe: f003 0302 and.w r3, r3, #2
|
|
8004302: 2b00 cmp r3, #0
|
|
8004304: d0f0 beq.n 80042e8 <HAL_RCC_OscConfig+0x234>
|
|
8004306: e01b b.n 8004340 <HAL_RCC_OscConfig+0x28c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8004308: 4b09 ldr r3, [pc, #36] @ (8004330 <HAL_RCC_OscConfig+0x27c>)
|
|
800430a: 2200 movs r2, #0
|
|
800430c: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800430e: f7fd f905 bl 800151c <HAL_GetTick>
|
|
8004312: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8004314: e00e b.n 8004334 <HAL_RCC_OscConfig+0x280>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8004316: f7fd f901 bl 800151c <HAL_GetTick>
|
|
800431a: 4602 mov r2, r0
|
|
800431c: 693b ldr r3, [r7, #16]
|
|
800431e: 1ad3 subs r3, r2, r3
|
|
8004320: 2b02 cmp r3, #2
|
|
8004322: d907 bls.n 8004334 <HAL_RCC_OscConfig+0x280>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004324: 2303 movs r3, #3
|
|
8004326: e15c b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
8004328: 40023800 .word 0x40023800
|
|
800432c: 42470000 .word 0x42470000
|
|
8004330: 42470e80 .word 0x42470e80
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8004334: 4b8a ldr r3, [pc, #552] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004336: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8004338: f003 0302 and.w r3, r3, #2
|
|
800433c: 2b00 cmp r3, #0
|
|
800433e: d1ea bne.n 8004316 <HAL_RCC_OscConfig+0x262>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8004340: 687b ldr r3, [r7, #4]
|
|
8004342: 681b ldr r3, [r3, #0]
|
|
8004344: f003 0304 and.w r3, r3, #4
|
|
8004348: 2b00 cmp r3, #0
|
|
800434a: f000 8097 beq.w 800447c <HAL_RCC_OscConfig+0x3c8>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
800434e: 2300 movs r3, #0
|
|
8004350: 75fb strb r3, [r7, #23]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8004352: 4b83 ldr r3, [pc, #524] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004354: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004356: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800435a: 2b00 cmp r3, #0
|
|
800435c: d10f bne.n 800437e <HAL_RCC_OscConfig+0x2ca>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800435e: 2300 movs r3, #0
|
|
8004360: 60bb str r3, [r7, #8]
|
|
8004362: 4b7f ldr r3, [pc, #508] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004364: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004366: 4a7e ldr r2, [pc, #504] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004368: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800436c: 6413 str r3, [r2, #64] @ 0x40
|
|
800436e: 4b7c ldr r3, [pc, #496] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004370: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004372: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8004376: 60bb str r3, [r7, #8]
|
|
8004378: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
800437a: 2301 movs r3, #1
|
|
800437c: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
800437e: 4b79 ldr r3, [pc, #484] @ (8004564 <HAL_RCC_OscConfig+0x4b0>)
|
|
8004380: 681b ldr r3, [r3, #0]
|
|
8004382: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004386: 2b00 cmp r3, #0
|
|
8004388: d118 bne.n 80043bc <HAL_RCC_OscConfig+0x308>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
800438a: 4b76 ldr r3, [pc, #472] @ (8004564 <HAL_RCC_OscConfig+0x4b0>)
|
|
800438c: 681b ldr r3, [r3, #0]
|
|
800438e: 4a75 ldr r2, [pc, #468] @ (8004564 <HAL_RCC_OscConfig+0x4b0>)
|
|
8004390: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8004394: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8004396: f7fd f8c1 bl 800151c <HAL_GetTick>
|
|
800439a: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
800439c: e008 b.n 80043b0 <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
800439e: f7fd f8bd bl 800151c <HAL_GetTick>
|
|
80043a2: 4602 mov r2, r0
|
|
80043a4: 693b ldr r3, [r7, #16]
|
|
80043a6: 1ad3 subs r3, r2, r3
|
|
80043a8: 2b02 cmp r3, #2
|
|
80043aa: d901 bls.n 80043b0 <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80043ac: 2303 movs r3, #3
|
|
80043ae: e118 b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
80043b0: 4b6c ldr r3, [pc, #432] @ (8004564 <HAL_RCC_OscConfig+0x4b0>)
|
|
80043b2: 681b ldr r3, [r3, #0]
|
|
80043b4: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80043b8: 2b00 cmp r3, #0
|
|
80043ba: d0f0 beq.n 800439e <HAL_RCC_OscConfig+0x2ea>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
80043bc: 687b ldr r3, [r7, #4]
|
|
80043be: 689b ldr r3, [r3, #8]
|
|
80043c0: 2b01 cmp r3, #1
|
|
80043c2: d106 bne.n 80043d2 <HAL_RCC_OscConfig+0x31e>
|
|
80043c4: 4b66 ldr r3, [pc, #408] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
80043c6: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80043c8: 4a65 ldr r2, [pc, #404] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
80043ca: f043 0301 orr.w r3, r3, #1
|
|
80043ce: 6713 str r3, [r2, #112] @ 0x70
|
|
80043d0: e01c b.n 800440c <HAL_RCC_OscConfig+0x358>
|
|
80043d2: 687b ldr r3, [r7, #4]
|
|
80043d4: 689b ldr r3, [r3, #8]
|
|
80043d6: 2b05 cmp r3, #5
|
|
80043d8: d10c bne.n 80043f4 <HAL_RCC_OscConfig+0x340>
|
|
80043da: 4b61 ldr r3, [pc, #388] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
80043dc: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80043de: 4a60 ldr r2, [pc, #384] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
80043e0: f043 0304 orr.w r3, r3, #4
|
|
80043e4: 6713 str r3, [r2, #112] @ 0x70
|
|
80043e6: 4b5e ldr r3, [pc, #376] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
80043e8: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80043ea: 4a5d ldr r2, [pc, #372] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
80043ec: f043 0301 orr.w r3, r3, #1
|
|
80043f0: 6713 str r3, [r2, #112] @ 0x70
|
|
80043f2: e00b b.n 800440c <HAL_RCC_OscConfig+0x358>
|
|
80043f4: 4b5a ldr r3, [pc, #360] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
80043f6: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80043f8: 4a59 ldr r2, [pc, #356] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
80043fa: f023 0301 bic.w r3, r3, #1
|
|
80043fe: 6713 str r3, [r2, #112] @ 0x70
|
|
8004400: 4b57 ldr r3, [pc, #348] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004402: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004404: 4a56 ldr r2, [pc, #344] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004406: f023 0304 bic.w r3, r3, #4
|
|
800440a: 6713 str r3, [r2, #112] @ 0x70
|
|
/* Check the LSE State */
|
|
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
|
|
800440c: 687b ldr r3, [r7, #4]
|
|
800440e: 689b ldr r3, [r3, #8]
|
|
8004410: 2b00 cmp r3, #0
|
|
8004412: d015 beq.n 8004440 <HAL_RCC_OscConfig+0x38c>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004414: f7fd f882 bl 800151c <HAL_GetTick>
|
|
8004418: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
800441a: e00a b.n 8004432 <HAL_RCC_OscConfig+0x37e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800441c: f7fd f87e bl 800151c <HAL_GetTick>
|
|
8004420: 4602 mov r2, r0
|
|
8004422: 693b ldr r3, [r7, #16]
|
|
8004424: 1ad3 subs r3, r2, r3
|
|
8004426: f241 3288 movw r2, #5000 @ 0x1388
|
|
800442a: 4293 cmp r3, r2
|
|
800442c: d901 bls.n 8004432 <HAL_RCC_OscConfig+0x37e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800442e: 2303 movs r3, #3
|
|
8004430: e0d7 b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8004432: 4b4b ldr r3, [pc, #300] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004434: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004436: f003 0302 and.w r3, r3, #2
|
|
800443a: 2b00 cmp r3, #0
|
|
800443c: d0ee beq.n 800441c <HAL_RCC_OscConfig+0x368>
|
|
800443e: e014 b.n 800446a <HAL_RCC_OscConfig+0x3b6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004440: f7fd f86c bl 800151c <HAL_GetTick>
|
|
8004444: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8004446: e00a b.n 800445e <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8004448: f7fd f868 bl 800151c <HAL_GetTick>
|
|
800444c: 4602 mov r2, r0
|
|
800444e: 693b ldr r3, [r7, #16]
|
|
8004450: 1ad3 subs r3, r2, r3
|
|
8004452: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004456: 4293 cmp r3, r2
|
|
8004458: d901 bls.n 800445e <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800445a: 2303 movs r3, #3
|
|
800445c: e0c1 b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
800445e: 4b40 ldr r3, [pc, #256] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004460: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004462: f003 0302 and.w r3, r3, #2
|
|
8004466: 2b00 cmp r3, #0
|
|
8004468: d1ee bne.n 8004448 <HAL_RCC_OscConfig+0x394>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
800446a: 7dfb ldrb r3, [r7, #23]
|
|
800446c: 2b01 cmp r3, #1
|
|
800446e: d105 bne.n 800447c <HAL_RCC_OscConfig+0x3c8>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8004470: 4b3b ldr r3, [pc, #236] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004472: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004474: 4a3a ldr r2, [pc, #232] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004476: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
800447a: 6413 str r3, [r2, #64] @ 0x40
|
|
}
|
|
}
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
800447c: 687b ldr r3, [r7, #4]
|
|
800447e: 699b ldr r3, [r3, #24]
|
|
8004480: 2b00 cmp r3, #0
|
|
8004482: f000 80ad beq.w 80045e0 <HAL_RCC_OscConfig+0x52c>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
|
8004486: 4b36 ldr r3, [pc, #216] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004488: 689b ldr r3, [r3, #8]
|
|
800448a: f003 030c and.w r3, r3, #12
|
|
800448e: 2b08 cmp r3, #8
|
|
8004490: d060 beq.n 8004554 <HAL_RCC_OscConfig+0x4a0>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
8004492: 687b ldr r3, [r7, #4]
|
|
8004494: 699b ldr r3, [r3, #24]
|
|
8004496: 2b02 cmp r3, #2
|
|
8004498: d145 bne.n 8004526 <HAL_RCC_OscConfig+0x472>
|
|
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
800449a: 4b33 ldr r3, [pc, #204] @ (8004568 <HAL_RCC_OscConfig+0x4b4>)
|
|
800449c: 2200 movs r2, #0
|
|
800449e: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80044a0: f7fd f83c bl 800151c <HAL_GetTick>
|
|
80044a4: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80044a6: e008 b.n 80044ba <HAL_RCC_OscConfig+0x406>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80044a8: f7fd f838 bl 800151c <HAL_GetTick>
|
|
80044ac: 4602 mov r2, r0
|
|
80044ae: 693b ldr r3, [r7, #16]
|
|
80044b0: 1ad3 subs r3, r2, r3
|
|
80044b2: 2b02 cmp r3, #2
|
|
80044b4: d901 bls.n 80044ba <HAL_RCC_OscConfig+0x406>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80044b6: 2303 movs r3, #3
|
|
80044b8: e093 b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80044ba: 4b29 ldr r3, [pc, #164] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
80044bc: 681b ldr r3, [r3, #0]
|
|
80044be: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80044c2: 2b00 cmp r3, #0
|
|
80044c4: d1f0 bne.n 80044a8 <HAL_RCC_OscConfig+0x3f4>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
|
|
80044c6: 687b ldr r3, [r7, #4]
|
|
80044c8: 69da ldr r2, [r3, #28]
|
|
80044ca: 687b ldr r3, [r7, #4]
|
|
80044cc: 6a1b ldr r3, [r3, #32]
|
|
80044ce: 431a orrs r2, r3
|
|
80044d0: 687b ldr r3, [r7, #4]
|
|
80044d2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80044d4: 019b lsls r3, r3, #6
|
|
80044d6: 431a orrs r2, r3
|
|
80044d8: 687b ldr r3, [r7, #4]
|
|
80044da: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80044dc: 085b lsrs r3, r3, #1
|
|
80044de: 3b01 subs r3, #1
|
|
80044e0: 041b lsls r3, r3, #16
|
|
80044e2: 431a orrs r2, r3
|
|
80044e4: 687b ldr r3, [r7, #4]
|
|
80044e6: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80044e8: 061b lsls r3, r3, #24
|
|
80044ea: 431a orrs r2, r3
|
|
80044ec: 687b ldr r3, [r7, #4]
|
|
80044ee: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80044f0: 071b lsls r3, r3, #28
|
|
80044f2: 491b ldr r1, [pc, #108] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
80044f4: 4313 orrs r3, r2
|
|
80044f6: 604b str r3, [r1, #4]
|
|
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
|
|
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
80044f8: 4b1b ldr r3, [pc, #108] @ (8004568 <HAL_RCC_OscConfig+0x4b4>)
|
|
80044fa: 2201 movs r2, #1
|
|
80044fc: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80044fe: f7fd f80d bl 800151c <HAL_GetTick>
|
|
8004502: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8004504: e008 b.n 8004518 <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8004506: f7fd f809 bl 800151c <HAL_GetTick>
|
|
800450a: 4602 mov r2, r0
|
|
800450c: 693b ldr r3, [r7, #16]
|
|
800450e: 1ad3 subs r3, r2, r3
|
|
8004510: 2b02 cmp r3, #2
|
|
8004512: d901 bls.n 8004518 <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004514: 2303 movs r3, #3
|
|
8004516: e064 b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8004518: 4b11 ldr r3, [pc, #68] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
800451a: 681b ldr r3, [r3, #0]
|
|
800451c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8004520: 2b00 cmp r3, #0
|
|
8004522: d0f0 beq.n 8004506 <HAL_RCC_OscConfig+0x452>
|
|
8004524: e05c b.n 80045e0 <HAL_RCC_OscConfig+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8004526: 4b10 ldr r3, [pc, #64] @ (8004568 <HAL_RCC_OscConfig+0x4b4>)
|
|
8004528: 2200 movs r2, #0
|
|
800452a: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800452c: f7fc fff6 bl 800151c <HAL_GetTick>
|
|
8004530: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8004532: e008 b.n 8004546 <HAL_RCC_OscConfig+0x492>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8004534: f7fc fff2 bl 800151c <HAL_GetTick>
|
|
8004538: 4602 mov r2, r0
|
|
800453a: 693b ldr r3, [r7, #16]
|
|
800453c: 1ad3 subs r3, r2, r3
|
|
800453e: 2b02 cmp r3, #2
|
|
8004540: d901 bls.n 8004546 <HAL_RCC_OscConfig+0x492>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004542: 2303 movs r3, #3
|
|
8004544: e04d b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8004546: 4b06 ldr r3, [pc, #24] @ (8004560 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004548: 681b ldr r3, [r3, #0]
|
|
800454a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800454e: 2b00 cmp r3, #0
|
|
8004550: d1f0 bne.n 8004534 <HAL_RCC_OscConfig+0x480>
|
|
8004552: e045 b.n 80045e0 <HAL_RCC_OscConfig+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8004554: 687b ldr r3, [r7, #4]
|
|
8004556: 699b ldr r3, [r3, #24]
|
|
8004558: 2b01 cmp r3, #1
|
|
800455a: d107 bne.n 800456c <HAL_RCC_OscConfig+0x4b8>
|
|
{
|
|
return HAL_ERROR;
|
|
800455c: 2301 movs r3, #1
|
|
800455e: e040 b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
8004560: 40023800 .word 0x40023800
|
|
8004564: 40007000 .word 0x40007000
|
|
8004568: 42470060 .word 0x42470060
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->PLLCFGR;
|
|
800456c: 4b1f ldr r3, [pc, #124] @ (80045ec <HAL_RCC_OscConfig+0x538>)
|
|
800456e: 685b ldr r3, [r3, #4]
|
|
8004570: 60fb str r3, [r7, #12]
|
|
#if defined (RCC_PLLCFGR_PLLR)
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
8004572: 687b ldr r3, [r7, #4]
|
|
8004574: 699b ldr r3, [r3, #24]
|
|
8004576: 2b01 cmp r3, #1
|
|
8004578: d030 beq.n 80045dc <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800457a: 68fb ldr r3, [r7, #12]
|
|
800457c: f403 0280 and.w r2, r3, #4194304 @ 0x400000
|
|
8004580: 687b ldr r3, [r7, #4]
|
|
8004582: 69db ldr r3, [r3, #28]
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
8004584: 429a cmp r2, r3
|
|
8004586: d129 bne.n 80045dc <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
8004588: 68fb ldr r3, [r7, #12]
|
|
800458a: f003 023f and.w r2, r3, #63 @ 0x3f
|
|
800458e: 687b ldr r3, [r7, #4]
|
|
8004590: 6a1b ldr r3, [r3, #32]
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8004592: 429a cmp r2, r3
|
|
8004594: d122 bne.n 80045dc <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
8004596: 68fa ldr r2, [r7, #12]
|
|
8004598: f647 73c0 movw r3, #32704 @ 0x7fc0
|
|
800459c: 4013 ands r3, r2
|
|
800459e: 687a ldr r2, [r7, #4]
|
|
80045a0: 6a52 ldr r2, [r2, #36] @ 0x24
|
|
80045a2: 0192 lsls r2, r2, #6
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
80045a4: 4293 cmp r3, r2
|
|
80045a6: d119 bne.n 80045dc <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
80045a8: 68fb ldr r3, [r7, #12]
|
|
80045aa: f403 3240 and.w r2, r3, #196608 @ 0x30000
|
|
80045ae: 687b ldr r3, [r7, #4]
|
|
80045b0: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80045b2: 085b lsrs r3, r3, #1
|
|
80045b4: 3b01 subs r3, #1
|
|
80045b6: 041b lsls r3, r3, #16
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
80045b8: 429a cmp r2, r3
|
|
80045ba: d10f bne.n 80045dc <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
80045bc: 68fb ldr r3, [r7, #12]
|
|
80045be: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
|
|
80045c2: 687b ldr r3, [r7, #4]
|
|
80045c4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80045c6: 061b lsls r3, r3, #24
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
80045c8: 429a cmp r2, r3
|
|
80045ca: d107 bne.n 80045dc <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
|
|
80045cc: 68fb ldr r3, [r7, #12]
|
|
80045ce: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000
|
|
80045d2: 687b ldr r3, [r7, #4]
|
|
80045d4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80045d6: 071b lsls r3, r3, #28
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
80045d8: 429a cmp r2, r3
|
|
80045da: d001 beq.n 80045e0 <HAL_RCC_OscConfig+0x52c>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
|
|
#endif /* RCC_PLLCFGR_PLLR */
|
|
{
|
|
return HAL_ERROR;
|
|
80045dc: 2301 movs r3, #1
|
|
80045de: e000 b.n 80045e2 <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80045e0: 2300 movs r3, #0
|
|
}
|
|
80045e2: 4618 mov r0, r3
|
|
80045e4: 3718 adds r7, #24
|
|
80045e6: 46bd mov sp, r7
|
|
80045e8: bd80 pop {r7, pc}
|
|
80045ea: bf00 nop
|
|
80045ec: 40023800 .word 0x40023800
|
|
|
|
080045f0 <HAL_TIM_OC_Init>:
|
|
* Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
|
|
* @param htim TIM Output Compare handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
80045f0: b580 push {r7, lr}
|
|
80045f2: b082 sub sp, #8
|
|
80045f4: af00 add r7, sp, #0
|
|
80045f6: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
80045f8: 687b ldr r3, [r7, #4]
|
|
80045fa: 2b00 cmp r3, #0
|
|
80045fc: d101 bne.n 8004602 <HAL_TIM_OC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80045fe: 2301 movs r3, #1
|
|
8004600: e041 b.n 8004686 <HAL_TIM_OC_Init+0x96>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8004602: 687b ldr r3, [r7, #4]
|
|
8004604: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8004608: b2db uxtb r3, r3
|
|
800460a: 2b00 cmp r3, #0
|
|
800460c: d106 bne.n 800461c <HAL_TIM_OC_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
800460e: 687b ldr r3, [r7, #4]
|
|
8004610: 2200 movs r2, #0
|
|
8004612: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->OC_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_OC_MspInit(htim);
|
|
8004616: 6878 ldr r0, [r7, #4]
|
|
8004618: f7fc fcc8 bl 8000fac <HAL_TIM_OC_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800461c: 687b ldr r3, [r7, #4]
|
|
800461e: 2202 movs r2, #2
|
|
8004620: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Init the base time for the Output Compare */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8004624: 687b ldr r3, [r7, #4]
|
|
8004626: 681a ldr r2, [r3, #0]
|
|
8004628: 687b ldr r3, [r7, #4]
|
|
800462a: 3304 adds r3, #4
|
|
800462c: 4619 mov r1, r3
|
|
800462e: 4610 mov r0, r2
|
|
8004630: f000 f930 bl 8004894 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8004634: 687b ldr r3, [r7, #4]
|
|
8004636: 2201 movs r2, #1
|
|
8004638: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
800463c: 687b ldr r3, [r7, #4]
|
|
800463e: 2201 movs r2, #1
|
|
8004640: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
8004644: 687b ldr r3, [r7, #4]
|
|
8004646: 2201 movs r2, #1
|
|
8004648: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
800464c: 687b ldr r3, [r7, #4]
|
|
800464e: 2201 movs r2, #1
|
|
8004650: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
8004654: 687b ldr r3, [r7, #4]
|
|
8004656: 2201 movs r2, #1
|
|
8004658: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
800465c: 687b ldr r3, [r7, #4]
|
|
800465e: 2201 movs r2, #1
|
|
8004660: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
8004664: 687b ldr r3, [r7, #4]
|
|
8004666: 2201 movs r2, #1
|
|
8004668: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
800466c: 687b ldr r3, [r7, #4]
|
|
800466e: 2201 movs r2, #1
|
|
8004670: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
8004674: 687b ldr r3, [r7, #4]
|
|
8004676: 2201 movs r2, #1
|
|
8004678: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800467c: 687b ldr r3, [r7, #4]
|
|
800467e: 2201 movs r2, #1
|
|
8004680: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
8004684: 2300 movs r3, #0
|
|
}
|
|
8004686: 4618 mov r0, r3
|
|
8004688: 3708 adds r7, #8
|
|
800468a: 46bd mov sp, r7
|
|
800468c: bd80 pop {r7, pc}
|
|
|
|
0800468e <HAL_TIM_Encoder_Init>:
|
|
* @param htim TIM Encoder Interface handle
|
|
* @param sConfig TIM Encoder Interface configuration structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
|
|
{
|
|
800468e: b580 push {r7, lr}
|
|
8004690: b086 sub sp, #24
|
|
8004692: af00 add r7, sp, #0
|
|
8004694: 6078 str r0, [r7, #4]
|
|
8004696: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
8004698: 687b ldr r3, [r7, #4]
|
|
800469a: 2b00 cmp r3, #0
|
|
800469c: d101 bne.n 80046a2 <HAL_TIM_Encoder_Init+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
800469e: 2301 movs r3, #1
|
|
80046a0: e097 b.n 80047d2 <HAL_TIM_Encoder_Init+0x144>
|
|
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
|
|
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
|
|
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
80046a2: 687b ldr r3, [r7, #4]
|
|
80046a4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
80046a8: b2db uxtb r3, r3
|
|
80046aa: 2b00 cmp r3, #0
|
|
80046ac: d106 bne.n 80046bc <HAL_TIM_Encoder_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
80046ae: 687b ldr r3, [r7, #4]
|
|
80046b0: 2200 movs r2, #0
|
|
80046b2: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Encoder_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_Encoder_MspInit(htim);
|
|
80046b6: 6878 ldr r0, [r7, #4]
|
|
80046b8: f7fc fc98 bl 8000fec <HAL_TIM_Encoder_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80046bc: 687b ldr r3, [r7, #4]
|
|
80046be: 2202 movs r2, #2
|
|
80046c0: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Reset the SMS and ECE bits */
|
|
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
|
|
80046c4: 687b ldr r3, [r7, #4]
|
|
80046c6: 681b ldr r3, [r3, #0]
|
|
80046c8: 689b ldr r3, [r3, #8]
|
|
80046ca: 687a ldr r2, [r7, #4]
|
|
80046cc: 6812 ldr r2, [r2, #0]
|
|
80046ce: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
80046d2: f023 0307 bic.w r3, r3, #7
|
|
80046d6: 6093 str r3, [r2, #8]
|
|
|
|
/* Configure the Time base in the Encoder Mode */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
80046d8: 687b ldr r3, [r7, #4]
|
|
80046da: 681a ldr r2, [r3, #0]
|
|
80046dc: 687b ldr r3, [r7, #4]
|
|
80046de: 3304 adds r3, #4
|
|
80046e0: 4619 mov r1, r3
|
|
80046e2: 4610 mov r0, r2
|
|
80046e4: f000 f8d6 bl 8004894 <TIM_Base_SetConfig>
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80046e8: 687b ldr r3, [r7, #4]
|
|
80046ea: 681b ldr r3, [r3, #0]
|
|
80046ec: 689b ldr r3, [r3, #8]
|
|
80046ee: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmr1 = htim->Instance->CCMR1;
|
|
80046f0: 687b ldr r3, [r7, #4]
|
|
80046f2: 681b ldr r3, [r3, #0]
|
|
80046f4: 699b ldr r3, [r3, #24]
|
|
80046f6: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = htim->Instance->CCER;
|
|
80046f8: 687b ldr r3, [r7, #4]
|
|
80046fa: 681b ldr r3, [r3, #0]
|
|
80046fc: 6a1b ldr r3, [r3, #32]
|
|
80046fe: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the encoder Mode */
|
|
tmpsmcr |= sConfig->EncoderMode;
|
|
8004700: 683b ldr r3, [r7, #0]
|
|
8004702: 681b ldr r3, [r3, #0]
|
|
8004704: 697a ldr r2, [r7, #20]
|
|
8004706: 4313 orrs r3, r2
|
|
8004708: 617b str r3, [r7, #20]
|
|
|
|
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
|
|
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
|
|
800470a: 693b ldr r3, [r7, #16]
|
|
800470c: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004710: f023 0303 bic.w r3, r3, #3
|
|
8004714: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
|
|
8004716: 683b ldr r3, [r7, #0]
|
|
8004718: 689a ldr r2, [r3, #8]
|
|
800471a: 683b ldr r3, [r7, #0]
|
|
800471c: 699b ldr r3, [r3, #24]
|
|
800471e: 021b lsls r3, r3, #8
|
|
8004720: 4313 orrs r3, r2
|
|
8004722: 693a ldr r2, [r7, #16]
|
|
8004724: 4313 orrs r3, r2
|
|
8004726: 613b str r3, [r7, #16]
|
|
|
|
/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
|
|
8004728: 693b ldr r3, [r7, #16]
|
|
800472a: f423 6340 bic.w r3, r3, #3072 @ 0xc00
|
|
800472e: f023 030c bic.w r3, r3, #12
|
|
8004732: 613b str r3, [r7, #16]
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
|
|
8004734: 693b ldr r3, [r7, #16]
|
|
8004736: f423 4370 bic.w r3, r3, #61440 @ 0xf000
|
|
800473a: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
800473e: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
|
|
8004740: 683b ldr r3, [r7, #0]
|
|
8004742: 68da ldr r2, [r3, #12]
|
|
8004744: 683b ldr r3, [r7, #0]
|
|
8004746: 69db ldr r3, [r3, #28]
|
|
8004748: 021b lsls r3, r3, #8
|
|
800474a: 4313 orrs r3, r2
|
|
800474c: 693a ldr r2, [r7, #16]
|
|
800474e: 4313 orrs r3, r2
|
|
8004750: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
|
|
8004752: 683b ldr r3, [r7, #0]
|
|
8004754: 691b ldr r3, [r3, #16]
|
|
8004756: 011a lsls r2, r3, #4
|
|
8004758: 683b ldr r3, [r7, #0]
|
|
800475a: 6a1b ldr r3, [r3, #32]
|
|
800475c: 031b lsls r3, r3, #12
|
|
800475e: 4313 orrs r3, r2
|
|
8004760: 693a ldr r2, [r7, #16]
|
|
8004762: 4313 orrs r3, r2
|
|
8004764: 613b str r3, [r7, #16]
|
|
|
|
/* Set the TI1 and the TI2 Polarities */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
|
|
8004766: 68fb ldr r3, [r7, #12]
|
|
8004768: f023 0322 bic.w r3, r3, #34 @ 0x22
|
|
800476c: 60fb str r3, [r7, #12]
|
|
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
|
|
800476e: 68fb ldr r3, [r7, #12]
|
|
8004770: f023 0388 bic.w r3, r3, #136 @ 0x88
|
|
8004774: 60fb str r3, [r7, #12]
|
|
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
|
|
8004776: 683b ldr r3, [r7, #0]
|
|
8004778: 685a ldr r2, [r3, #4]
|
|
800477a: 683b ldr r3, [r7, #0]
|
|
800477c: 695b ldr r3, [r3, #20]
|
|
800477e: 011b lsls r3, r3, #4
|
|
8004780: 4313 orrs r3, r2
|
|
8004782: 68fa ldr r2, [r7, #12]
|
|
8004784: 4313 orrs r3, r2
|
|
8004786: 60fb str r3, [r7, #12]
|
|
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8004788: 687b ldr r3, [r7, #4]
|
|
800478a: 681b ldr r3, [r3, #0]
|
|
800478c: 697a ldr r2, [r7, #20]
|
|
800478e: 609a str r2, [r3, #8]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
htim->Instance->CCMR1 = tmpccmr1;
|
|
8004790: 687b ldr r3, [r7, #4]
|
|
8004792: 681b ldr r3, [r3, #0]
|
|
8004794: 693a ldr r2, [r7, #16]
|
|
8004796: 619a str r2, [r3, #24]
|
|
|
|
/* Write to TIMx CCER */
|
|
htim->Instance->CCER = tmpccer;
|
|
8004798: 687b ldr r3, [r7, #4]
|
|
800479a: 681b ldr r3, [r3, #0]
|
|
800479c: 68fa ldr r2, [r7, #12]
|
|
800479e: 621a str r2, [r3, #32]
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
80047a0: 687b ldr r3, [r7, #4]
|
|
80047a2: 2201 movs r2, #1
|
|
80047a4: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Set the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
80047a8: 687b ldr r3, [r7, #4]
|
|
80047aa: 2201 movs r2, #1
|
|
80047ac: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
80047b0: 687b ldr r3, [r7, #4]
|
|
80047b2: 2201 movs r2, #1
|
|
80047b4: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
80047b8: 687b ldr r3, [r7, #4]
|
|
80047ba: 2201 movs r2, #1
|
|
80047bc: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
80047c0: 687b ldr r3, [r7, #4]
|
|
80047c2: 2201 movs r2, #1
|
|
80047c4: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80047c8: 687b ldr r3, [r7, #4]
|
|
80047ca: 2201 movs r2, #1
|
|
80047cc: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
80047d0: 2300 movs r3, #0
|
|
}
|
|
80047d2: 4618 mov r0, r3
|
|
80047d4: 3718 adds r7, #24
|
|
80047d6: 46bd mov sp, r7
|
|
80047d8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080047dc <HAL_TIM_OC_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
const TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
80047dc: b580 push {r7, lr}
|
|
80047de: b086 sub sp, #24
|
|
80047e0: af00 add r7, sp, #0
|
|
80047e2: 60f8 str r0, [r7, #12]
|
|
80047e4: 60b9 str r1, [r7, #8]
|
|
80047e6: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80047e8: 2300 movs r3, #0
|
|
80047ea: 75fb strb r3, [r7, #23]
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
80047ec: 68fb ldr r3, [r7, #12]
|
|
80047ee: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
80047f2: 2b01 cmp r3, #1
|
|
80047f4: d101 bne.n 80047fa <HAL_TIM_OC_ConfigChannel+0x1e>
|
|
80047f6: 2302 movs r3, #2
|
|
80047f8: e048 b.n 800488c <HAL_TIM_OC_ConfigChannel+0xb0>
|
|
80047fa: 68fb ldr r3, [r7, #12]
|
|
80047fc: 2201 movs r2, #1
|
|
80047fe: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
switch (Channel)
|
|
8004802: 687b ldr r3, [r7, #4]
|
|
8004804: 2b0c cmp r3, #12
|
|
8004806: d839 bhi.n 800487c <HAL_TIM_OC_ConfigChannel+0xa0>
|
|
8004808: a201 add r2, pc, #4 @ (adr r2, 8004810 <HAL_TIM_OC_ConfigChannel+0x34>)
|
|
800480a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800480e: bf00 nop
|
|
8004810: 08004845 .word 0x08004845
|
|
8004814: 0800487d .word 0x0800487d
|
|
8004818: 0800487d .word 0x0800487d
|
|
800481c: 0800487d .word 0x0800487d
|
|
8004820: 08004853 .word 0x08004853
|
|
8004824: 0800487d .word 0x0800487d
|
|
8004828: 0800487d .word 0x0800487d
|
|
800482c: 0800487d .word 0x0800487d
|
|
8004830: 08004861 .word 0x08004861
|
|
8004834: 0800487d .word 0x0800487d
|
|
8004838: 0800487d .word 0x0800487d
|
|
800483c: 0800487d .word 0x0800487d
|
|
8004840: 0800486f .word 0x0800486f
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 1 in Output Compare */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
8004844: 68fb ldr r3, [r7, #12]
|
|
8004846: 681b ldr r3, [r3, #0]
|
|
8004848: 68b9 ldr r1, [r7, #8]
|
|
800484a: 4618 mov r0, r3
|
|
800484c: f000 f8c8 bl 80049e0 <TIM_OC1_SetConfig>
|
|
break;
|
|
8004850: e017 b.n 8004882 <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 2 in Output Compare */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
8004852: 68fb ldr r3, [r7, #12]
|
|
8004854: 681b ldr r3, [r3, #0]
|
|
8004856: 68b9 ldr r1, [r7, #8]
|
|
8004858: 4618 mov r0, r3
|
|
800485a: f000 f931 bl 8004ac0 <TIM_OC2_SetConfig>
|
|
break;
|
|
800485e: e010 b.n 8004882 <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 3 in Output Compare */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
8004860: 68fb ldr r3, [r7, #12]
|
|
8004862: 681b ldr r3, [r3, #0]
|
|
8004864: 68b9 ldr r1, [r7, #8]
|
|
8004866: 4618 mov r0, r3
|
|
8004868: f000 f9a0 bl 8004bac <TIM_OC3_SetConfig>
|
|
break;
|
|
800486c: e009 b.n 8004882 <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 4 in Output Compare */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
800486e: 68fb ldr r3, [r7, #12]
|
|
8004870: 681b ldr r3, [r3, #0]
|
|
8004872: 68b9 ldr r1, [r7, #8]
|
|
8004874: 4618 mov r0, r3
|
|
8004876: f000 fa0d bl 8004c94 <TIM_OC4_SetConfig>
|
|
break;
|
|
800487a: e002 b.n 8004882 <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
800487c: 2301 movs r3, #1
|
|
800487e: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8004880: bf00 nop
|
|
}
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8004882: 68fb ldr r3, [r7, #12]
|
|
8004884: 2200 movs r2, #0
|
|
8004886: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
800488a: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800488c: 4618 mov r0, r3
|
|
800488e: 3718 adds r7, #24
|
|
8004890: 46bd mov sp, r7
|
|
8004892: bd80 pop {r7, pc}
|
|
|
|
08004894 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8004894: b480 push {r7}
|
|
8004896: b085 sub sp, #20
|
|
8004898: af00 add r7, sp, #0
|
|
800489a: 6078 str r0, [r7, #4]
|
|
800489c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
800489e: 687b ldr r3, [r7, #4]
|
|
80048a0: 681b ldr r3, [r3, #0]
|
|
80048a2: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
80048a4: 687b ldr r3, [r7, #4]
|
|
80048a6: 4a43 ldr r2, [pc, #268] @ (80049b4 <TIM_Base_SetConfig+0x120>)
|
|
80048a8: 4293 cmp r3, r2
|
|
80048aa: d013 beq.n 80048d4 <TIM_Base_SetConfig+0x40>
|
|
80048ac: 687b ldr r3, [r7, #4]
|
|
80048ae: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80048b2: d00f beq.n 80048d4 <TIM_Base_SetConfig+0x40>
|
|
80048b4: 687b ldr r3, [r7, #4]
|
|
80048b6: 4a40 ldr r2, [pc, #256] @ (80049b8 <TIM_Base_SetConfig+0x124>)
|
|
80048b8: 4293 cmp r3, r2
|
|
80048ba: d00b beq.n 80048d4 <TIM_Base_SetConfig+0x40>
|
|
80048bc: 687b ldr r3, [r7, #4]
|
|
80048be: 4a3f ldr r2, [pc, #252] @ (80049bc <TIM_Base_SetConfig+0x128>)
|
|
80048c0: 4293 cmp r3, r2
|
|
80048c2: d007 beq.n 80048d4 <TIM_Base_SetConfig+0x40>
|
|
80048c4: 687b ldr r3, [r7, #4]
|
|
80048c6: 4a3e ldr r2, [pc, #248] @ (80049c0 <TIM_Base_SetConfig+0x12c>)
|
|
80048c8: 4293 cmp r3, r2
|
|
80048ca: d003 beq.n 80048d4 <TIM_Base_SetConfig+0x40>
|
|
80048cc: 687b ldr r3, [r7, #4]
|
|
80048ce: 4a3d ldr r2, [pc, #244] @ (80049c4 <TIM_Base_SetConfig+0x130>)
|
|
80048d0: 4293 cmp r3, r2
|
|
80048d2: d108 bne.n 80048e6 <TIM_Base_SetConfig+0x52>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
80048d4: 68fb ldr r3, [r7, #12]
|
|
80048d6: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80048da: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
80048dc: 683b ldr r3, [r7, #0]
|
|
80048de: 685b ldr r3, [r3, #4]
|
|
80048e0: 68fa ldr r2, [r7, #12]
|
|
80048e2: 4313 orrs r3, r2
|
|
80048e4: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80048e6: 687b ldr r3, [r7, #4]
|
|
80048e8: 4a32 ldr r2, [pc, #200] @ (80049b4 <TIM_Base_SetConfig+0x120>)
|
|
80048ea: 4293 cmp r3, r2
|
|
80048ec: d02b beq.n 8004946 <TIM_Base_SetConfig+0xb2>
|
|
80048ee: 687b ldr r3, [r7, #4]
|
|
80048f0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80048f4: d027 beq.n 8004946 <TIM_Base_SetConfig+0xb2>
|
|
80048f6: 687b ldr r3, [r7, #4]
|
|
80048f8: 4a2f ldr r2, [pc, #188] @ (80049b8 <TIM_Base_SetConfig+0x124>)
|
|
80048fa: 4293 cmp r3, r2
|
|
80048fc: d023 beq.n 8004946 <TIM_Base_SetConfig+0xb2>
|
|
80048fe: 687b ldr r3, [r7, #4]
|
|
8004900: 4a2e ldr r2, [pc, #184] @ (80049bc <TIM_Base_SetConfig+0x128>)
|
|
8004902: 4293 cmp r3, r2
|
|
8004904: d01f beq.n 8004946 <TIM_Base_SetConfig+0xb2>
|
|
8004906: 687b ldr r3, [r7, #4]
|
|
8004908: 4a2d ldr r2, [pc, #180] @ (80049c0 <TIM_Base_SetConfig+0x12c>)
|
|
800490a: 4293 cmp r3, r2
|
|
800490c: d01b beq.n 8004946 <TIM_Base_SetConfig+0xb2>
|
|
800490e: 687b ldr r3, [r7, #4]
|
|
8004910: 4a2c ldr r2, [pc, #176] @ (80049c4 <TIM_Base_SetConfig+0x130>)
|
|
8004912: 4293 cmp r3, r2
|
|
8004914: d017 beq.n 8004946 <TIM_Base_SetConfig+0xb2>
|
|
8004916: 687b ldr r3, [r7, #4]
|
|
8004918: 4a2b ldr r2, [pc, #172] @ (80049c8 <TIM_Base_SetConfig+0x134>)
|
|
800491a: 4293 cmp r3, r2
|
|
800491c: d013 beq.n 8004946 <TIM_Base_SetConfig+0xb2>
|
|
800491e: 687b ldr r3, [r7, #4]
|
|
8004920: 4a2a ldr r2, [pc, #168] @ (80049cc <TIM_Base_SetConfig+0x138>)
|
|
8004922: 4293 cmp r3, r2
|
|
8004924: d00f beq.n 8004946 <TIM_Base_SetConfig+0xb2>
|
|
8004926: 687b ldr r3, [r7, #4]
|
|
8004928: 4a29 ldr r2, [pc, #164] @ (80049d0 <TIM_Base_SetConfig+0x13c>)
|
|
800492a: 4293 cmp r3, r2
|
|
800492c: d00b beq.n 8004946 <TIM_Base_SetConfig+0xb2>
|
|
800492e: 687b ldr r3, [r7, #4]
|
|
8004930: 4a28 ldr r2, [pc, #160] @ (80049d4 <TIM_Base_SetConfig+0x140>)
|
|
8004932: 4293 cmp r3, r2
|
|
8004934: d007 beq.n 8004946 <TIM_Base_SetConfig+0xb2>
|
|
8004936: 687b ldr r3, [r7, #4]
|
|
8004938: 4a27 ldr r2, [pc, #156] @ (80049d8 <TIM_Base_SetConfig+0x144>)
|
|
800493a: 4293 cmp r3, r2
|
|
800493c: d003 beq.n 8004946 <TIM_Base_SetConfig+0xb2>
|
|
800493e: 687b ldr r3, [r7, #4]
|
|
8004940: 4a26 ldr r2, [pc, #152] @ (80049dc <TIM_Base_SetConfig+0x148>)
|
|
8004942: 4293 cmp r3, r2
|
|
8004944: d108 bne.n 8004958 <TIM_Base_SetConfig+0xc4>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
8004946: 68fb ldr r3, [r7, #12]
|
|
8004948: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800494c: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
800494e: 683b ldr r3, [r7, #0]
|
|
8004950: 68db ldr r3, [r3, #12]
|
|
8004952: 68fa ldr r2, [r7, #12]
|
|
8004954: 4313 orrs r3, r2
|
|
8004956: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
8004958: 68fb ldr r3, [r7, #12]
|
|
800495a: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
800495e: 683b ldr r3, [r7, #0]
|
|
8004960: 695b ldr r3, [r3, #20]
|
|
8004962: 4313 orrs r3, r2
|
|
8004964: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
8004966: 683b ldr r3, [r7, #0]
|
|
8004968: 689a ldr r2, [r3, #8]
|
|
800496a: 687b ldr r3, [r7, #4]
|
|
800496c: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
800496e: 683b ldr r3, [r7, #0]
|
|
8004970: 681a ldr r2, [r3, #0]
|
|
8004972: 687b ldr r3, [r7, #4]
|
|
8004974: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
8004976: 687b ldr r3, [r7, #4]
|
|
8004978: 4a0e ldr r2, [pc, #56] @ (80049b4 <TIM_Base_SetConfig+0x120>)
|
|
800497a: 4293 cmp r3, r2
|
|
800497c: d003 beq.n 8004986 <TIM_Base_SetConfig+0xf2>
|
|
800497e: 687b ldr r3, [r7, #4]
|
|
8004980: 4a10 ldr r2, [pc, #64] @ (80049c4 <TIM_Base_SetConfig+0x130>)
|
|
8004982: 4293 cmp r3, r2
|
|
8004984: d103 bne.n 800498e <TIM_Base_SetConfig+0xfa>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
8004986: 683b ldr r3, [r7, #0]
|
|
8004988: 691a ldr r2, [r3, #16]
|
|
800498a: 687b ldr r3, [r7, #4]
|
|
800498c: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Disable Update Event (UEV) with Update Generation (UG)
|
|
by changing Update Request Source (URS) to avoid Update flag (UIF) */
|
|
SET_BIT(TIMx->CR1, TIM_CR1_URS);
|
|
800498e: 687b ldr r3, [r7, #4]
|
|
8004990: 681b ldr r3, [r3, #0]
|
|
8004992: f043 0204 orr.w r2, r3, #4
|
|
8004996: 687b ldr r3, [r7, #4]
|
|
8004998: 601a str r2, [r3, #0]
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
800499a: 687b ldr r3, [r7, #4]
|
|
800499c: 2201 movs r2, #1
|
|
800499e: 615a str r2, [r3, #20]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
80049a0: 687b ldr r3, [r7, #4]
|
|
80049a2: 68fa ldr r2, [r7, #12]
|
|
80049a4: 601a str r2, [r3, #0]
|
|
}
|
|
80049a6: bf00 nop
|
|
80049a8: 3714 adds r7, #20
|
|
80049aa: 46bd mov sp, r7
|
|
80049ac: f85d 7b04 ldr.w r7, [sp], #4
|
|
80049b0: 4770 bx lr
|
|
80049b2: bf00 nop
|
|
80049b4: 40010000 .word 0x40010000
|
|
80049b8: 40000400 .word 0x40000400
|
|
80049bc: 40000800 .word 0x40000800
|
|
80049c0: 40000c00 .word 0x40000c00
|
|
80049c4: 40010400 .word 0x40010400
|
|
80049c8: 40014000 .word 0x40014000
|
|
80049cc: 40014400 .word 0x40014400
|
|
80049d0: 40014800 .word 0x40014800
|
|
80049d4: 40001800 .word 0x40001800
|
|
80049d8: 40001c00 .word 0x40001c00
|
|
80049dc: 40002000 .word 0x40002000
|
|
|
|
080049e0 <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
80049e0: b480 push {r7}
|
|
80049e2: b087 sub sp, #28
|
|
80049e4: af00 add r7, sp, #0
|
|
80049e6: 6078 str r0, [r7, #4]
|
|
80049e8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
80049ea: 687b ldr r3, [r7, #4]
|
|
80049ec: 6a1b ldr r3, [r3, #32]
|
|
80049ee: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
80049f0: 687b ldr r3, [r7, #4]
|
|
80049f2: 6a1b ldr r3, [r3, #32]
|
|
80049f4: f023 0201 bic.w r2, r3, #1
|
|
80049f8: 687b ldr r3, [r7, #4]
|
|
80049fa: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80049fc: 687b ldr r3, [r7, #4]
|
|
80049fe: 685b ldr r3, [r3, #4]
|
|
8004a00: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8004a02: 687b ldr r3, [r7, #4]
|
|
8004a04: 699b ldr r3, [r3, #24]
|
|
8004a06: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
8004a08: 68fb ldr r3, [r7, #12]
|
|
8004a0a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8004a0e: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
8004a10: 68fb ldr r3, [r7, #12]
|
|
8004a12: f023 0303 bic.w r3, r3, #3
|
|
8004a16: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8004a18: 683b ldr r3, [r7, #0]
|
|
8004a1a: 681b ldr r3, [r3, #0]
|
|
8004a1c: 68fa ldr r2, [r7, #12]
|
|
8004a1e: 4313 orrs r3, r2
|
|
8004a20: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
8004a22: 697b ldr r3, [r7, #20]
|
|
8004a24: f023 0302 bic.w r3, r3, #2
|
|
8004a28: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
8004a2a: 683b ldr r3, [r7, #0]
|
|
8004a2c: 689b ldr r3, [r3, #8]
|
|
8004a2e: 697a ldr r2, [r7, #20]
|
|
8004a30: 4313 orrs r3, r2
|
|
8004a32: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
8004a34: 687b ldr r3, [r7, #4]
|
|
8004a36: 4a20 ldr r2, [pc, #128] @ (8004ab8 <TIM_OC1_SetConfig+0xd8>)
|
|
8004a38: 4293 cmp r3, r2
|
|
8004a3a: d003 beq.n 8004a44 <TIM_OC1_SetConfig+0x64>
|
|
8004a3c: 687b ldr r3, [r7, #4]
|
|
8004a3e: 4a1f ldr r2, [pc, #124] @ (8004abc <TIM_OC1_SetConfig+0xdc>)
|
|
8004a40: 4293 cmp r3, r2
|
|
8004a42: d10c bne.n 8004a5e <TIM_OC1_SetConfig+0x7e>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
8004a44: 697b ldr r3, [r7, #20]
|
|
8004a46: f023 0308 bic.w r3, r3, #8
|
|
8004a4a: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
8004a4c: 683b ldr r3, [r7, #0]
|
|
8004a4e: 68db ldr r3, [r3, #12]
|
|
8004a50: 697a ldr r2, [r7, #20]
|
|
8004a52: 4313 orrs r3, r2
|
|
8004a54: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
8004a56: 697b ldr r3, [r7, #20]
|
|
8004a58: f023 0304 bic.w r3, r3, #4
|
|
8004a5c: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004a5e: 687b ldr r3, [r7, #4]
|
|
8004a60: 4a15 ldr r2, [pc, #84] @ (8004ab8 <TIM_OC1_SetConfig+0xd8>)
|
|
8004a62: 4293 cmp r3, r2
|
|
8004a64: d003 beq.n 8004a6e <TIM_OC1_SetConfig+0x8e>
|
|
8004a66: 687b ldr r3, [r7, #4]
|
|
8004a68: 4a14 ldr r2, [pc, #80] @ (8004abc <TIM_OC1_SetConfig+0xdc>)
|
|
8004a6a: 4293 cmp r3, r2
|
|
8004a6c: d111 bne.n 8004a92 <TIM_OC1_SetConfig+0xb2>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
8004a6e: 693b ldr r3, [r7, #16]
|
|
8004a70: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8004a74: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
8004a76: 693b ldr r3, [r7, #16]
|
|
8004a78: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
8004a7c: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
8004a7e: 683b ldr r3, [r7, #0]
|
|
8004a80: 695b ldr r3, [r3, #20]
|
|
8004a82: 693a ldr r2, [r7, #16]
|
|
8004a84: 4313 orrs r3, r2
|
|
8004a86: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
8004a88: 683b ldr r3, [r7, #0]
|
|
8004a8a: 699b ldr r3, [r3, #24]
|
|
8004a8c: 693a ldr r2, [r7, #16]
|
|
8004a8e: 4313 orrs r3, r2
|
|
8004a90: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004a92: 687b ldr r3, [r7, #4]
|
|
8004a94: 693a ldr r2, [r7, #16]
|
|
8004a96: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8004a98: 687b ldr r3, [r7, #4]
|
|
8004a9a: 68fa ldr r2, [r7, #12]
|
|
8004a9c: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
8004a9e: 683b ldr r3, [r7, #0]
|
|
8004aa0: 685a ldr r2, [r3, #4]
|
|
8004aa2: 687b ldr r3, [r7, #4]
|
|
8004aa4: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004aa6: 687b ldr r3, [r7, #4]
|
|
8004aa8: 697a ldr r2, [r7, #20]
|
|
8004aaa: 621a str r2, [r3, #32]
|
|
}
|
|
8004aac: bf00 nop
|
|
8004aae: 371c adds r7, #28
|
|
8004ab0: 46bd mov sp, r7
|
|
8004ab2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004ab6: 4770 bx lr
|
|
8004ab8: 40010000 .word 0x40010000
|
|
8004abc: 40010400 .word 0x40010400
|
|
|
|
08004ac0 <TIM_OC2_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004ac0: b480 push {r7}
|
|
8004ac2: b087 sub sp, #28
|
|
8004ac4: af00 add r7, sp, #0
|
|
8004ac6: 6078 str r0, [r7, #4]
|
|
8004ac8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8004aca: 687b ldr r3, [r7, #4]
|
|
8004acc: 6a1b ldr r3, [r3, #32]
|
|
8004ace: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8004ad0: 687b ldr r3, [r7, #4]
|
|
8004ad2: 6a1b ldr r3, [r3, #32]
|
|
8004ad4: f023 0210 bic.w r2, r3, #16
|
|
8004ad8: 687b ldr r3, [r7, #4]
|
|
8004ada: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8004adc: 687b ldr r3, [r7, #4]
|
|
8004ade: 685b ldr r3, [r3, #4]
|
|
8004ae0: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8004ae2: 687b ldr r3, [r7, #4]
|
|
8004ae4: 699b ldr r3, [r3, #24]
|
|
8004ae6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
8004ae8: 68fb ldr r3, [r7, #12]
|
|
8004aea: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8004aee: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
8004af0: 68fb ldr r3, [r7, #12]
|
|
8004af2: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004af6: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8004af8: 683b ldr r3, [r7, #0]
|
|
8004afa: 681b ldr r3, [r3, #0]
|
|
8004afc: 021b lsls r3, r3, #8
|
|
8004afe: 68fa ldr r2, [r7, #12]
|
|
8004b00: 4313 orrs r3, r2
|
|
8004b02: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
8004b04: 697b ldr r3, [r7, #20]
|
|
8004b06: f023 0320 bic.w r3, r3, #32
|
|
8004b0a: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
8004b0c: 683b ldr r3, [r7, #0]
|
|
8004b0e: 689b ldr r3, [r3, #8]
|
|
8004b10: 011b lsls r3, r3, #4
|
|
8004b12: 697a ldr r2, [r7, #20]
|
|
8004b14: 4313 orrs r3, r2
|
|
8004b16: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
8004b18: 687b ldr r3, [r7, #4]
|
|
8004b1a: 4a22 ldr r2, [pc, #136] @ (8004ba4 <TIM_OC2_SetConfig+0xe4>)
|
|
8004b1c: 4293 cmp r3, r2
|
|
8004b1e: d003 beq.n 8004b28 <TIM_OC2_SetConfig+0x68>
|
|
8004b20: 687b ldr r3, [r7, #4]
|
|
8004b22: 4a21 ldr r2, [pc, #132] @ (8004ba8 <TIM_OC2_SetConfig+0xe8>)
|
|
8004b24: 4293 cmp r3, r2
|
|
8004b26: d10d bne.n 8004b44 <TIM_OC2_SetConfig+0x84>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
8004b28: 697b ldr r3, [r7, #20]
|
|
8004b2a: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8004b2e: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
8004b30: 683b ldr r3, [r7, #0]
|
|
8004b32: 68db ldr r3, [r3, #12]
|
|
8004b34: 011b lsls r3, r3, #4
|
|
8004b36: 697a ldr r2, [r7, #20]
|
|
8004b38: 4313 orrs r3, r2
|
|
8004b3a: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
8004b3c: 697b ldr r3, [r7, #20]
|
|
8004b3e: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8004b42: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004b44: 687b ldr r3, [r7, #4]
|
|
8004b46: 4a17 ldr r2, [pc, #92] @ (8004ba4 <TIM_OC2_SetConfig+0xe4>)
|
|
8004b48: 4293 cmp r3, r2
|
|
8004b4a: d003 beq.n 8004b54 <TIM_OC2_SetConfig+0x94>
|
|
8004b4c: 687b ldr r3, [r7, #4]
|
|
8004b4e: 4a16 ldr r2, [pc, #88] @ (8004ba8 <TIM_OC2_SetConfig+0xe8>)
|
|
8004b50: 4293 cmp r3, r2
|
|
8004b52: d113 bne.n 8004b7c <TIM_OC2_SetConfig+0xbc>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
8004b54: 693b ldr r3, [r7, #16]
|
|
8004b56: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8004b5a: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
8004b5c: 693b ldr r3, [r7, #16]
|
|
8004b5e: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
8004b62: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
8004b64: 683b ldr r3, [r7, #0]
|
|
8004b66: 695b ldr r3, [r3, #20]
|
|
8004b68: 009b lsls r3, r3, #2
|
|
8004b6a: 693a ldr r2, [r7, #16]
|
|
8004b6c: 4313 orrs r3, r2
|
|
8004b6e: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
8004b70: 683b ldr r3, [r7, #0]
|
|
8004b72: 699b ldr r3, [r3, #24]
|
|
8004b74: 009b lsls r3, r3, #2
|
|
8004b76: 693a ldr r2, [r7, #16]
|
|
8004b78: 4313 orrs r3, r2
|
|
8004b7a: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004b7c: 687b ldr r3, [r7, #4]
|
|
8004b7e: 693a ldr r2, [r7, #16]
|
|
8004b80: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8004b82: 687b ldr r3, [r7, #4]
|
|
8004b84: 68fa ldr r2, [r7, #12]
|
|
8004b86: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
8004b88: 683b ldr r3, [r7, #0]
|
|
8004b8a: 685a ldr r2, [r3, #4]
|
|
8004b8c: 687b ldr r3, [r7, #4]
|
|
8004b8e: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004b90: 687b ldr r3, [r7, #4]
|
|
8004b92: 697a ldr r2, [r7, #20]
|
|
8004b94: 621a str r2, [r3, #32]
|
|
}
|
|
8004b96: bf00 nop
|
|
8004b98: 371c adds r7, #28
|
|
8004b9a: 46bd mov sp, r7
|
|
8004b9c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004ba0: 4770 bx lr
|
|
8004ba2: bf00 nop
|
|
8004ba4: 40010000 .word 0x40010000
|
|
8004ba8: 40010400 .word 0x40010400
|
|
|
|
08004bac <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004bac: b480 push {r7}
|
|
8004bae: b087 sub sp, #28
|
|
8004bb0: af00 add r7, sp, #0
|
|
8004bb2: 6078 str r0, [r7, #4]
|
|
8004bb4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8004bb6: 687b ldr r3, [r7, #4]
|
|
8004bb8: 6a1b ldr r3, [r3, #32]
|
|
8004bba: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
8004bbc: 687b ldr r3, [r7, #4]
|
|
8004bbe: 6a1b ldr r3, [r3, #32]
|
|
8004bc0: f423 7280 bic.w r2, r3, #256 @ 0x100
|
|
8004bc4: 687b ldr r3, [r7, #4]
|
|
8004bc6: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8004bc8: 687b ldr r3, [r7, #4]
|
|
8004bca: 685b ldr r3, [r3, #4]
|
|
8004bcc: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8004bce: 687b ldr r3, [r7, #4]
|
|
8004bd0: 69db ldr r3, [r3, #28]
|
|
8004bd2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
8004bd4: 68fb ldr r3, [r7, #12]
|
|
8004bd6: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8004bda: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
8004bdc: 68fb ldr r3, [r7, #12]
|
|
8004bde: f023 0303 bic.w r3, r3, #3
|
|
8004be2: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8004be4: 683b ldr r3, [r7, #0]
|
|
8004be6: 681b ldr r3, [r3, #0]
|
|
8004be8: 68fa ldr r2, [r7, #12]
|
|
8004bea: 4313 orrs r3, r2
|
|
8004bec: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
8004bee: 697b ldr r3, [r7, #20]
|
|
8004bf0: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
8004bf4: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
8004bf6: 683b ldr r3, [r7, #0]
|
|
8004bf8: 689b ldr r3, [r3, #8]
|
|
8004bfa: 021b lsls r3, r3, #8
|
|
8004bfc: 697a ldr r2, [r7, #20]
|
|
8004bfe: 4313 orrs r3, r2
|
|
8004c00: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
8004c02: 687b ldr r3, [r7, #4]
|
|
8004c04: 4a21 ldr r2, [pc, #132] @ (8004c8c <TIM_OC3_SetConfig+0xe0>)
|
|
8004c06: 4293 cmp r3, r2
|
|
8004c08: d003 beq.n 8004c12 <TIM_OC3_SetConfig+0x66>
|
|
8004c0a: 687b ldr r3, [r7, #4]
|
|
8004c0c: 4a20 ldr r2, [pc, #128] @ (8004c90 <TIM_OC3_SetConfig+0xe4>)
|
|
8004c0e: 4293 cmp r3, r2
|
|
8004c10: d10d bne.n 8004c2e <TIM_OC3_SetConfig+0x82>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
8004c12: 697b ldr r3, [r7, #20]
|
|
8004c14: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
8004c18: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
8004c1a: 683b ldr r3, [r7, #0]
|
|
8004c1c: 68db ldr r3, [r3, #12]
|
|
8004c1e: 021b lsls r3, r3, #8
|
|
8004c20: 697a ldr r2, [r7, #20]
|
|
8004c22: 4313 orrs r3, r2
|
|
8004c24: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
8004c26: 697b ldr r3, [r7, #20]
|
|
8004c28: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8004c2c: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004c2e: 687b ldr r3, [r7, #4]
|
|
8004c30: 4a16 ldr r2, [pc, #88] @ (8004c8c <TIM_OC3_SetConfig+0xe0>)
|
|
8004c32: 4293 cmp r3, r2
|
|
8004c34: d003 beq.n 8004c3e <TIM_OC3_SetConfig+0x92>
|
|
8004c36: 687b ldr r3, [r7, #4]
|
|
8004c38: 4a15 ldr r2, [pc, #84] @ (8004c90 <TIM_OC3_SetConfig+0xe4>)
|
|
8004c3a: 4293 cmp r3, r2
|
|
8004c3c: d113 bne.n 8004c66 <TIM_OC3_SetConfig+0xba>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
8004c3e: 693b ldr r3, [r7, #16]
|
|
8004c40: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
8004c44: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
8004c46: 693b ldr r3, [r7, #16]
|
|
8004c48: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
8004c4c: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
8004c4e: 683b ldr r3, [r7, #0]
|
|
8004c50: 695b ldr r3, [r3, #20]
|
|
8004c52: 011b lsls r3, r3, #4
|
|
8004c54: 693a ldr r2, [r7, #16]
|
|
8004c56: 4313 orrs r3, r2
|
|
8004c58: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
8004c5a: 683b ldr r3, [r7, #0]
|
|
8004c5c: 699b ldr r3, [r3, #24]
|
|
8004c5e: 011b lsls r3, r3, #4
|
|
8004c60: 693a ldr r2, [r7, #16]
|
|
8004c62: 4313 orrs r3, r2
|
|
8004c64: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004c66: 687b ldr r3, [r7, #4]
|
|
8004c68: 693a ldr r2, [r7, #16]
|
|
8004c6a: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8004c6c: 687b ldr r3, [r7, #4]
|
|
8004c6e: 68fa ldr r2, [r7, #12]
|
|
8004c70: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
8004c72: 683b ldr r3, [r7, #0]
|
|
8004c74: 685a ldr r2, [r3, #4]
|
|
8004c76: 687b ldr r3, [r7, #4]
|
|
8004c78: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004c7a: 687b ldr r3, [r7, #4]
|
|
8004c7c: 697a ldr r2, [r7, #20]
|
|
8004c7e: 621a str r2, [r3, #32]
|
|
}
|
|
8004c80: bf00 nop
|
|
8004c82: 371c adds r7, #28
|
|
8004c84: 46bd mov sp, r7
|
|
8004c86: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004c8a: 4770 bx lr
|
|
8004c8c: 40010000 .word 0x40010000
|
|
8004c90: 40010400 .word 0x40010400
|
|
|
|
08004c94 <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004c94: b480 push {r7}
|
|
8004c96: b087 sub sp, #28
|
|
8004c98: af00 add r7, sp, #0
|
|
8004c9a: 6078 str r0, [r7, #4]
|
|
8004c9c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8004c9e: 687b ldr r3, [r7, #4]
|
|
8004ca0: 6a1b ldr r3, [r3, #32]
|
|
8004ca2: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
8004ca4: 687b ldr r3, [r7, #4]
|
|
8004ca6: 6a1b ldr r3, [r3, #32]
|
|
8004ca8: f423 5280 bic.w r2, r3, #4096 @ 0x1000
|
|
8004cac: 687b ldr r3, [r7, #4]
|
|
8004cae: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8004cb0: 687b ldr r3, [r7, #4]
|
|
8004cb2: 685b ldr r3, [r3, #4]
|
|
8004cb4: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8004cb6: 687b ldr r3, [r7, #4]
|
|
8004cb8: 69db ldr r3, [r3, #28]
|
|
8004cba: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
8004cbc: 68fb ldr r3, [r7, #12]
|
|
8004cbe: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8004cc2: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
8004cc4: 68fb ldr r3, [r7, #12]
|
|
8004cc6: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004cca: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8004ccc: 683b ldr r3, [r7, #0]
|
|
8004cce: 681b ldr r3, [r3, #0]
|
|
8004cd0: 021b lsls r3, r3, #8
|
|
8004cd2: 68fa ldr r2, [r7, #12]
|
|
8004cd4: 4313 orrs r3, r2
|
|
8004cd6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
8004cd8: 693b ldr r3, [r7, #16]
|
|
8004cda: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
8004cde: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
8004ce0: 683b ldr r3, [r7, #0]
|
|
8004ce2: 689b ldr r3, [r3, #8]
|
|
8004ce4: 031b lsls r3, r3, #12
|
|
8004ce6: 693a ldr r2, [r7, #16]
|
|
8004ce8: 4313 orrs r3, r2
|
|
8004cea: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004cec: 687b ldr r3, [r7, #4]
|
|
8004cee: 4a12 ldr r2, [pc, #72] @ (8004d38 <TIM_OC4_SetConfig+0xa4>)
|
|
8004cf0: 4293 cmp r3, r2
|
|
8004cf2: d003 beq.n 8004cfc <TIM_OC4_SetConfig+0x68>
|
|
8004cf4: 687b ldr r3, [r7, #4]
|
|
8004cf6: 4a11 ldr r2, [pc, #68] @ (8004d3c <TIM_OC4_SetConfig+0xa8>)
|
|
8004cf8: 4293 cmp r3, r2
|
|
8004cfa: d109 bne.n 8004d10 <TIM_OC4_SetConfig+0x7c>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
8004cfc: 697b ldr r3, [r7, #20]
|
|
8004cfe: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8004d02: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
8004d04: 683b ldr r3, [r7, #0]
|
|
8004d06: 695b ldr r3, [r3, #20]
|
|
8004d08: 019b lsls r3, r3, #6
|
|
8004d0a: 697a ldr r2, [r7, #20]
|
|
8004d0c: 4313 orrs r3, r2
|
|
8004d0e: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004d10: 687b ldr r3, [r7, #4]
|
|
8004d12: 697a ldr r2, [r7, #20]
|
|
8004d14: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8004d16: 687b ldr r3, [r7, #4]
|
|
8004d18: 68fa ldr r2, [r7, #12]
|
|
8004d1a: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
8004d1c: 683b ldr r3, [r7, #0]
|
|
8004d1e: 685a ldr r2, [r3, #4]
|
|
8004d20: 687b ldr r3, [r7, #4]
|
|
8004d22: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004d24: 687b ldr r3, [r7, #4]
|
|
8004d26: 693a ldr r2, [r7, #16]
|
|
8004d28: 621a str r2, [r3, #32]
|
|
}
|
|
8004d2a: bf00 nop
|
|
8004d2c: 371c adds r7, #28
|
|
8004d2e: 46bd mov sp, r7
|
|
8004d30: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004d34: 4770 bx lr
|
|
8004d36: bf00 nop
|
|
8004d38: 40010000 .word 0x40010000
|
|
8004d3c: 40010400 .word 0x40010400
|
|
|
|
08004d40 <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
8004d40: b480 push {r7}
|
|
8004d42: b085 sub sp, #20
|
|
8004d44: af00 add r7, sp, #0
|
|
8004d46: 6078 str r0, [r7, #4]
|
|
8004d48: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8004d4a: 687b ldr r3, [r7, #4]
|
|
8004d4c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8004d50: 2b01 cmp r3, #1
|
|
8004d52: d101 bne.n 8004d58 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8004d54: 2302 movs r3, #2
|
|
8004d56: e05a b.n 8004e0e <HAL_TIMEx_MasterConfigSynchronization+0xce>
|
|
8004d58: 687b ldr r3, [r7, #4]
|
|
8004d5a: 2201 movs r2, #1
|
|
8004d5c: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8004d60: 687b ldr r3, [r7, #4]
|
|
8004d62: 2202 movs r2, #2
|
|
8004d64: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8004d68: 687b ldr r3, [r7, #4]
|
|
8004d6a: 681b ldr r3, [r3, #0]
|
|
8004d6c: 685b ldr r3, [r3, #4]
|
|
8004d6e: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8004d70: 687b ldr r3, [r7, #4]
|
|
8004d72: 681b ldr r3, [r3, #0]
|
|
8004d74: 689b ldr r3, [r3, #8]
|
|
8004d76: 60bb str r3, [r7, #8]
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8004d78: 68fb ldr r3, [r7, #12]
|
|
8004d7a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8004d7e: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8004d80: 683b ldr r3, [r7, #0]
|
|
8004d82: 681b ldr r3, [r3, #0]
|
|
8004d84: 68fa ldr r2, [r7, #12]
|
|
8004d86: 4313 orrs r3, r2
|
|
8004d88: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8004d8a: 687b ldr r3, [r7, #4]
|
|
8004d8c: 681b ldr r3, [r3, #0]
|
|
8004d8e: 68fa ldr r2, [r7, #12]
|
|
8004d90: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8004d92: 687b ldr r3, [r7, #4]
|
|
8004d94: 681b ldr r3, [r3, #0]
|
|
8004d96: 4a21 ldr r2, [pc, #132] @ (8004e1c <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
|
|
8004d98: 4293 cmp r3, r2
|
|
8004d9a: d022 beq.n 8004de2 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004d9c: 687b ldr r3, [r7, #4]
|
|
8004d9e: 681b ldr r3, [r3, #0]
|
|
8004da0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8004da4: d01d beq.n 8004de2 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004da6: 687b ldr r3, [r7, #4]
|
|
8004da8: 681b ldr r3, [r3, #0]
|
|
8004daa: 4a1d ldr r2, [pc, #116] @ (8004e20 <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
|
|
8004dac: 4293 cmp r3, r2
|
|
8004dae: d018 beq.n 8004de2 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004db0: 687b ldr r3, [r7, #4]
|
|
8004db2: 681b ldr r3, [r3, #0]
|
|
8004db4: 4a1b ldr r2, [pc, #108] @ (8004e24 <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
|
|
8004db6: 4293 cmp r3, r2
|
|
8004db8: d013 beq.n 8004de2 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004dba: 687b ldr r3, [r7, #4]
|
|
8004dbc: 681b ldr r3, [r3, #0]
|
|
8004dbe: 4a1a ldr r2, [pc, #104] @ (8004e28 <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
|
|
8004dc0: 4293 cmp r3, r2
|
|
8004dc2: d00e beq.n 8004de2 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004dc4: 687b ldr r3, [r7, #4]
|
|
8004dc6: 681b ldr r3, [r3, #0]
|
|
8004dc8: 4a18 ldr r2, [pc, #96] @ (8004e2c <HAL_TIMEx_MasterConfigSynchronization+0xec>)
|
|
8004dca: 4293 cmp r3, r2
|
|
8004dcc: d009 beq.n 8004de2 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004dce: 687b ldr r3, [r7, #4]
|
|
8004dd0: 681b ldr r3, [r3, #0]
|
|
8004dd2: 4a17 ldr r2, [pc, #92] @ (8004e30 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
|
|
8004dd4: 4293 cmp r3, r2
|
|
8004dd6: d004 beq.n 8004de2 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004dd8: 687b ldr r3, [r7, #4]
|
|
8004dda: 681b ldr r3, [r3, #0]
|
|
8004ddc: 4a15 ldr r2, [pc, #84] @ (8004e34 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
|
|
8004dde: 4293 cmp r3, r2
|
|
8004de0: d10c bne.n 8004dfc <HAL_TIMEx_MasterConfigSynchronization+0xbc>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
8004de2: 68bb ldr r3, [r7, #8]
|
|
8004de4: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8004de8: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
8004dea: 683b ldr r3, [r7, #0]
|
|
8004dec: 685b ldr r3, [r3, #4]
|
|
8004dee: 68ba ldr r2, [r7, #8]
|
|
8004df0: 4313 orrs r3, r2
|
|
8004df2: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8004df4: 687b ldr r3, [r7, #4]
|
|
8004df6: 681b ldr r3, [r3, #0]
|
|
8004df8: 68ba ldr r2, [r7, #8]
|
|
8004dfa: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8004dfc: 687b ldr r3, [r7, #4]
|
|
8004dfe: 2201 movs r2, #1
|
|
8004e00: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8004e04: 687b ldr r3, [r7, #4]
|
|
8004e06: 2200 movs r2, #0
|
|
8004e08: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
8004e0c: 2300 movs r3, #0
|
|
}
|
|
8004e0e: 4618 mov r0, r3
|
|
8004e10: 3714 adds r7, #20
|
|
8004e12: 46bd mov sp, r7
|
|
8004e14: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004e18: 4770 bx lr
|
|
8004e1a: bf00 nop
|
|
8004e1c: 40010000 .word 0x40010000
|
|
8004e20: 40000400 .word 0x40000400
|
|
8004e24: 40000800 .word 0x40000800
|
|
8004e28: 40000c00 .word 0x40000c00
|
|
8004e2c: 40010400 .word 0x40010400
|
|
8004e30: 40014000 .word 0x40014000
|
|
8004e34: 40001800 .word 0x40001800
|
|
|
|
08004e38 <HAL_UART_Init>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8004e38: b580 push {r7, lr}
|
|
8004e3a: b082 sub sp, #8
|
|
8004e3c: af00 add r7, sp, #0
|
|
8004e3e: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8004e40: 687b ldr r3, [r7, #4]
|
|
8004e42: 2b00 cmp r3, #0
|
|
8004e44: d101 bne.n 8004e4a <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004e46: 2301 movs r3, #1
|
|
8004e48: e042 b.n 8004ed0 <HAL_UART_Init+0x98>
|
|
assert_param(IS_UART_INSTANCE(huart->Instance));
|
|
}
|
|
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
|
|
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8004e4a: 687b ldr r3, [r7, #4]
|
|
8004e4c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8004e50: b2db uxtb r3, r3
|
|
8004e52: 2b00 cmp r3, #0
|
|
8004e54: d106 bne.n 8004e64 <HAL_UART_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8004e56: 687b ldr r3, [r7, #4]
|
|
8004e58: 2200 movs r2, #0
|
|
8004e5a: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8004e5e: 6878 ldr r0, [r7, #4]
|
|
8004e60: f7fc f944 bl 80010ec <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8004e64: 687b ldr r3, [r7, #4]
|
|
8004e66: 2224 movs r2, #36 @ 0x24
|
|
8004e68: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_UART_DISABLE(huart);
|
|
8004e6c: 687b ldr r3, [r7, #4]
|
|
8004e6e: 681b ldr r3, [r3, #0]
|
|
8004e70: 68da ldr r2, [r3, #12]
|
|
8004e72: 687b ldr r3, [r7, #4]
|
|
8004e74: 681b ldr r3, [r3, #0]
|
|
8004e76: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
8004e7a: 60da str r2, [r3, #12]
|
|
|
|
/* Set the UART Communication parameters */
|
|
UART_SetConfig(huart);
|
|
8004e7c: 6878 ldr r0, [r7, #4]
|
|
8004e7e: f000 fb8b bl 8005598 <UART_SetConfig>
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8004e82: 687b ldr r3, [r7, #4]
|
|
8004e84: 681b ldr r3, [r3, #0]
|
|
8004e86: 691a ldr r2, [r3, #16]
|
|
8004e88: 687b ldr r3, [r7, #4]
|
|
8004e8a: 681b ldr r3, [r3, #0]
|
|
8004e8c: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
8004e90: 611a str r2, [r3, #16]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8004e92: 687b ldr r3, [r7, #4]
|
|
8004e94: 681b ldr r3, [r3, #0]
|
|
8004e96: 695a ldr r2, [r3, #20]
|
|
8004e98: 687b ldr r3, [r7, #4]
|
|
8004e9a: 681b ldr r3, [r3, #0]
|
|
8004e9c: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
8004ea0: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the peripheral */
|
|
__HAL_UART_ENABLE(huart);
|
|
8004ea2: 687b ldr r3, [r7, #4]
|
|
8004ea4: 681b ldr r3, [r3, #0]
|
|
8004ea6: 68da ldr r2, [r3, #12]
|
|
8004ea8: 687b ldr r3, [r7, #4]
|
|
8004eaa: 681b ldr r3, [r3, #0]
|
|
8004eac: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
8004eb0: 60da str r2, [r3, #12]
|
|
|
|
/* Initialize the UART state */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004eb2: 687b ldr r3, [r7, #4]
|
|
8004eb4: 2200 movs r2, #0
|
|
8004eb6: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004eb8: 687b ldr r3, [r7, #4]
|
|
8004eba: 2220 movs r2, #32
|
|
8004ebc: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004ec0: 687b ldr r3, [r7, #4]
|
|
8004ec2: 2220 movs r2, #32
|
|
8004ec4: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8004ec8: 687b ldr r3, [r7, #4]
|
|
8004eca: 2200 movs r2, #0
|
|
8004ecc: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_OK;
|
|
8004ece: 2300 movs r3, #0
|
|
}
|
|
8004ed0: 4618 mov r0, r3
|
|
8004ed2: 3708 adds r7, #8
|
|
8004ed4: 46bd mov sp, r7
|
|
8004ed6: bd80 pop {r7, pc}
|
|
|
|
08004ed8 <HAL_UART_Transmit_DMA>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
|
|
{
|
|
8004ed8: b580 push {r7, lr}
|
|
8004eda: b08c sub sp, #48 @ 0x30
|
|
8004edc: af00 add r7, sp, #0
|
|
8004ede: 60f8 str r0, [r7, #12]
|
|
8004ee0: 60b9 str r1, [r7, #8]
|
|
8004ee2: 4613 mov r3, r2
|
|
8004ee4: 80fb strh r3, [r7, #6]
|
|
const uint32_t *tmp;
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8004ee6: 68fb ldr r3, [r7, #12]
|
|
8004ee8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8004eec: b2db uxtb r3, r3
|
|
8004eee: 2b20 cmp r3, #32
|
|
8004ef0: d162 bne.n 8004fb8 <HAL_UART_Transmit_DMA+0xe0>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8004ef2: 68bb ldr r3, [r7, #8]
|
|
8004ef4: 2b00 cmp r3, #0
|
|
8004ef6: d002 beq.n 8004efe <HAL_UART_Transmit_DMA+0x26>
|
|
8004ef8: 88fb ldrh r3, [r7, #6]
|
|
8004efa: 2b00 cmp r3, #0
|
|
8004efc: d101 bne.n 8004f02 <HAL_UART_Transmit_DMA+0x2a>
|
|
{
|
|
return HAL_ERROR;
|
|
8004efe: 2301 movs r3, #1
|
|
8004f00: e05b b.n 8004fba <HAL_UART_Transmit_DMA+0xe2>
|
|
}
|
|
|
|
huart->pTxBuffPtr = pData;
|
|
8004f02: 68ba ldr r2, [r7, #8]
|
|
8004f04: 68fb ldr r3, [r7, #12]
|
|
8004f06: 621a str r2, [r3, #32]
|
|
huart->TxXferSize = Size;
|
|
8004f08: 68fb ldr r3, [r7, #12]
|
|
8004f0a: 88fa ldrh r2, [r7, #6]
|
|
8004f0c: 849a strh r2, [r3, #36] @ 0x24
|
|
huart->TxXferCount = Size;
|
|
8004f0e: 68fb ldr r3, [r7, #12]
|
|
8004f10: 88fa ldrh r2, [r7, #6]
|
|
8004f12: 84da strh r2, [r3, #38] @ 0x26
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004f14: 68fb ldr r3, [r7, #12]
|
|
8004f16: 2200 movs r2, #0
|
|
8004f18: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
8004f1a: 68fb ldr r3, [r7, #12]
|
|
8004f1c: 2221 movs r2, #33 @ 0x21
|
|
8004f1e: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Set the UART DMA transfer complete callback */
|
|
huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
|
|
8004f22: 68fb ldr r3, [r7, #12]
|
|
8004f24: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004f26: 4a27 ldr r2, [pc, #156] @ (8004fc4 <HAL_UART_Transmit_DMA+0xec>)
|
|
8004f28: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Set the UART DMA Half transfer complete callback */
|
|
huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
|
|
8004f2a: 68fb ldr r3, [r7, #12]
|
|
8004f2c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004f2e: 4a26 ldr r2, [pc, #152] @ (8004fc8 <HAL_UART_Transmit_DMA+0xf0>)
|
|
8004f30: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set the DMA error callback */
|
|
huart->hdmatx->XferErrorCallback = UART_DMAError;
|
|
8004f32: 68fb ldr r3, [r7, #12]
|
|
8004f34: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004f36: 4a25 ldr r2, [pc, #148] @ (8004fcc <HAL_UART_Transmit_DMA+0xf4>)
|
|
8004f38: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Set the DMA abort callback */
|
|
huart->hdmatx->XferAbortCallback = NULL;
|
|
8004f3a: 68fb ldr r3, [r7, #12]
|
|
8004f3c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004f3e: 2200 movs r2, #0
|
|
8004f40: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Enable the UART transmit DMA stream */
|
|
tmp = (const uint32_t *)&pData;
|
|
8004f42: f107 0308 add.w r3, r7, #8
|
|
8004f46: 62fb str r3, [r7, #44] @ 0x2c
|
|
if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK)
|
|
8004f48: 68fb ldr r3, [r7, #12]
|
|
8004f4a: 6b98 ldr r0, [r3, #56] @ 0x38
|
|
8004f4c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8004f4e: 6819 ldr r1, [r3, #0]
|
|
8004f50: 68fb ldr r3, [r7, #12]
|
|
8004f52: 681b ldr r3, [r3, #0]
|
|
8004f54: 3304 adds r3, #4
|
|
8004f56: 461a mov r2, r3
|
|
8004f58: 88fb ldrh r3, [r7, #6]
|
|
8004f5a: f7fc fc20 bl 800179e <HAL_DMA_Start_IT>
|
|
8004f5e: 4603 mov r3, r0
|
|
8004f60: 2b00 cmp r3, #0
|
|
8004f62: d008 beq.n 8004f76 <HAL_UART_Transmit_DMA+0x9e>
|
|
{
|
|
/* Set error code to DMA */
|
|
huart->ErrorCode = HAL_UART_ERROR_DMA;
|
|
8004f64: 68fb ldr r3, [r7, #12]
|
|
8004f66: 2210 movs r2, #16
|
|
8004f68: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Restore huart->gState to ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004f6a: 68fb ldr r3, [r7, #12]
|
|
8004f6c: 2220 movs r2, #32
|
|
8004f6e: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
return HAL_ERROR;
|
|
8004f72: 2301 movs r3, #1
|
|
8004f74: e021 b.n 8004fba <HAL_UART_Transmit_DMA+0xe2>
|
|
}
|
|
/* Clear the TC flag in the SR register by writing 0 to it */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
|
|
8004f76: 68fb ldr r3, [r7, #12]
|
|
8004f78: 681b ldr r3, [r3, #0]
|
|
8004f7a: f06f 0240 mvn.w r2, #64 @ 0x40
|
|
8004f7e: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the DMA transfer for transmit request by setting the DMAT bit
|
|
in the UART CR3 register */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
|
8004f80: 68fb ldr r3, [r7, #12]
|
|
8004f82: 681b ldr r3, [r3, #0]
|
|
8004f84: 3314 adds r3, #20
|
|
8004f86: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004f88: 69bb ldr r3, [r7, #24]
|
|
8004f8a: e853 3f00 ldrex r3, [r3]
|
|
8004f8e: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8004f90: 697b ldr r3, [r7, #20]
|
|
8004f92: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8004f96: 62bb str r3, [r7, #40] @ 0x28
|
|
8004f98: 68fb ldr r3, [r7, #12]
|
|
8004f9a: 681b ldr r3, [r3, #0]
|
|
8004f9c: 3314 adds r3, #20
|
|
8004f9e: 6aba ldr r2, [r7, #40] @ 0x28
|
|
8004fa0: 627a str r2, [r7, #36] @ 0x24
|
|
8004fa2: 623b str r3, [r7, #32]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004fa4: 6a39 ldr r1, [r7, #32]
|
|
8004fa6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8004fa8: e841 2300 strex r3, r2, [r1]
|
|
8004fac: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8004fae: 69fb ldr r3, [r7, #28]
|
|
8004fb0: 2b00 cmp r3, #0
|
|
8004fb2: d1e5 bne.n 8004f80 <HAL_UART_Transmit_DMA+0xa8>
|
|
|
|
return HAL_OK;
|
|
8004fb4: 2300 movs r3, #0
|
|
8004fb6: e000 b.n 8004fba <HAL_UART_Transmit_DMA+0xe2>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004fb8: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004fba: 4618 mov r0, r3
|
|
8004fbc: 3730 adds r7, #48 @ 0x30
|
|
8004fbe: 46bd mov sp, r7
|
|
8004fc0: bd80 pop {r7, pc}
|
|
8004fc2: bf00 nop
|
|
8004fc4: 08005083 .word 0x08005083
|
|
8004fc8: 0800511d .word 0x0800511d
|
|
8004fcc: 080052a1 .word 0x080052a1
|
|
|
|
08004fd0 <HAL_UART_Receive_DMA>:
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
8004fd0: b580 push {r7, lr}
|
|
8004fd2: b084 sub sp, #16
|
|
8004fd4: af00 add r7, sp, #0
|
|
8004fd6: 60f8 str r0, [r7, #12]
|
|
8004fd8: 60b9 str r1, [r7, #8]
|
|
8004fda: 4613 mov r3, r2
|
|
8004fdc: 80fb strh r3, [r7, #6]
|
|
/* Check that a Rx process is not already ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
8004fde: 68fb ldr r3, [r7, #12]
|
|
8004fe0: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
8004fe4: b2db uxtb r3, r3
|
|
8004fe6: 2b20 cmp r3, #32
|
|
8004fe8: d112 bne.n 8005010 <HAL_UART_Receive_DMA+0x40>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8004fea: 68bb ldr r3, [r7, #8]
|
|
8004fec: 2b00 cmp r3, #0
|
|
8004fee: d002 beq.n 8004ff6 <HAL_UART_Receive_DMA+0x26>
|
|
8004ff0: 88fb ldrh r3, [r7, #6]
|
|
8004ff2: 2b00 cmp r3, #0
|
|
8004ff4: d101 bne.n 8004ffa <HAL_UART_Receive_DMA+0x2a>
|
|
{
|
|
return HAL_ERROR;
|
|
8004ff6: 2301 movs r3, #1
|
|
8004ff8: e00b b.n 8005012 <HAL_UART_Receive_DMA+0x42>
|
|
}
|
|
|
|
/* Set Reception type to Standard reception */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004ffa: 68fb ldr r3, [r7, #12]
|
|
8004ffc: 2200 movs r2, #0
|
|
8004ffe: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
return (UART_Start_Receive_DMA(huart, pData, Size));
|
|
8005000: 88fb ldrh r3, [r7, #6]
|
|
8005002: 461a mov r2, r3
|
|
8005004: 68b9 ldr r1, [r7, #8]
|
|
8005006: 68f8 ldr r0, [r7, #12]
|
|
8005008: f000 f994 bl 8005334 <UART_Start_Receive_DMA>
|
|
800500c: 4603 mov r3, r0
|
|
800500e: e000 b.n 8005012 <HAL_UART_Receive_DMA+0x42>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8005010: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8005012: 4618 mov r0, r3
|
|
8005014: 3710 adds r7, #16
|
|
8005016: 46bd mov sp, r7
|
|
8005018: bd80 pop {r7, pc}
|
|
|
|
0800501a <HAL_UART_TxCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800501a: b480 push {r7}
|
|
800501c: b083 sub sp, #12
|
|
800501e: af00 add r7, sp, #0
|
|
8005020: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005022: bf00 nop
|
|
8005024: 370c adds r7, #12
|
|
8005026: 46bd mov sp, r7
|
|
8005028: f85d 7b04 ldr.w r7, [sp], #4
|
|
800502c: 4770 bx lr
|
|
|
|
0800502e <HAL_UART_TxHalfCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800502e: b480 push {r7}
|
|
8005030: b083 sub sp, #12
|
|
8005032: af00 add r7, sp, #0
|
|
8005034: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxHalfCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005036: bf00 nop
|
|
8005038: 370c adds r7, #12
|
|
800503a: 46bd mov sp, r7
|
|
800503c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005040: 4770 bx lr
|
|
|
|
08005042 <HAL_UART_RxHalfCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8005042: b480 push {r7}
|
|
8005044: b083 sub sp, #12
|
|
8005046: af00 add r7, sp, #0
|
|
8005048: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_RxHalfCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800504a: bf00 nop
|
|
800504c: 370c adds r7, #12
|
|
800504e: 46bd mov sp, r7
|
|
8005050: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005054: 4770 bx lr
|
|
|
|
08005056 <HAL_UART_ErrorCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8005056: b480 push {r7}
|
|
8005058: b083 sub sp, #12
|
|
800505a: af00 add r7, sp, #0
|
|
800505c: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_ErrorCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800505e: bf00 nop
|
|
8005060: 370c adds r7, #12
|
|
8005062: 46bd mov sp, r7
|
|
8005064: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005068: 4770 bx lr
|
|
|
|
0800506a <HAL_UARTEx_RxEventCallback>:
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
|
* reception buffer until which, data are available)
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|
{
|
|
800506a: b480 push {r7}
|
|
800506c: b083 sub sp, #12
|
|
800506e: af00 add r7, sp, #0
|
|
8005070: 6078 str r0, [r7, #4]
|
|
8005072: 460b mov r3, r1
|
|
8005074: 807b strh r3, [r7, #2]
|
|
UNUSED(Size);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8005076: bf00 nop
|
|
8005078: 370c adds r7, #12
|
|
800507a: 46bd mov sp, r7
|
|
800507c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005080: 4770 bx lr
|
|
|
|
08005082 <UART_DMATransmitCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8005082: b580 push {r7, lr}
|
|
8005084: b090 sub sp, #64 @ 0x40
|
|
8005086: af00 add r7, sp, #0
|
|
8005088: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
800508a: 687b ldr r3, [r7, #4]
|
|
800508c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800508e: 63fb str r3, [r7, #60] @ 0x3c
|
|
/* DMA Normal mode*/
|
|
if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
|
|
8005090: 687b ldr r3, [r7, #4]
|
|
8005092: 681b ldr r3, [r3, #0]
|
|
8005094: 681b ldr r3, [r3, #0]
|
|
8005096: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800509a: 2b00 cmp r3, #0
|
|
800509c: d137 bne.n 800510e <UART_DMATransmitCplt+0x8c>
|
|
{
|
|
huart->TxXferCount = 0x00U;
|
|
800509e: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80050a0: 2200 movs r2, #0
|
|
80050a2: 84da strh r2, [r3, #38] @ 0x26
|
|
|
|
/* Disable the DMA transfer for transmit request by setting the DMAT bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
|
80050a4: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80050a6: 681b ldr r3, [r3, #0]
|
|
80050a8: 3314 adds r3, #20
|
|
80050aa: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80050ac: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80050ae: e853 3f00 ldrex r3, [r3]
|
|
80050b2: 623b str r3, [r7, #32]
|
|
return(result);
|
|
80050b4: 6a3b ldr r3, [r7, #32]
|
|
80050b6: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
80050ba: 63bb str r3, [r7, #56] @ 0x38
|
|
80050bc: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80050be: 681b ldr r3, [r3, #0]
|
|
80050c0: 3314 adds r3, #20
|
|
80050c2: 6bba ldr r2, [r7, #56] @ 0x38
|
|
80050c4: 633a str r2, [r7, #48] @ 0x30
|
|
80050c6: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80050c8: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80050ca: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80050cc: e841 2300 strex r3, r2, [r1]
|
|
80050d0: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
80050d2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80050d4: 2b00 cmp r3, #0
|
|
80050d6: d1e5 bne.n 80050a4 <UART_DMATransmitCplt+0x22>
|
|
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
80050d8: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80050da: 681b ldr r3, [r3, #0]
|
|
80050dc: 330c adds r3, #12
|
|
80050de: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80050e0: 693b ldr r3, [r7, #16]
|
|
80050e2: e853 3f00 ldrex r3, [r3]
|
|
80050e6: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80050e8: 68fb ldr r3, [r7, #12]
|
|
80050ea: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
80050ee: 637b str r3, [r7, #52] @ 0x34
|
|
80050f0: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80050f2: 681b ldr r3, [r3, #0]
|
|
80050f4: 330c adds r3, #12
|
|
80050f6: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
80050f8: 61fa str r2, [r7, #28]
|
|
80050fa: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80050fc: 69b9 ldr r1, [r7, #24]
|
|
80050fe: 69fa ldr r2, [r7, #28]
|
|
8005100: e841 2300 strex r3, r2, [r1]
|
|
8005104: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8005106: 697b ldr r3, [r7, #20]
|
|
8005108: 2b00 cmp r3, #0
|
|
800510a: d1e5 bne.n 80050d8 <UART_DMATransmitCplt+0x56>
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
800510c: e002 b.n 8005114 <UART_DMATransmitCplt+0x92>
|
|
HAL_UART_TxCpltCallback(huart);
|
|
800510e: 6bf8 ldr r0, [r7, #60] @ 0x3c
|
|
8005110: f7ff ff83 bl 800501a <HAL_UART_TxCpltCallback>
|
|
}
|
|
8005114: bf00 nop
|
|
8005116: 3740 adds r7, #64 @ 0x40
|
|
8005118: 46bd mov sp, r7
|
|
800511a: bd80 pop {r7, pc}
|
|
|
|
0800511c <UART_DMATxHalfCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800511c: b580 push {r7, lr}
|
|
800511e: b084 sub sp, #16
|
|
8005120: af00 add r7, sp, #0
|
|
8005122: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
8005124: 687b ldr r3, [r7, #4]
|
|
8005126: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005128: 60fb str r3, [r7, #12]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxHalfCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxHalfCpltCallback(huart);
|
|
800512a: 68f8 ldr r0, [r7, #12]
|
|
800512c: f7ff ff7f bl 800502e <HAL_UART_TxHalfCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
8005130: bf00 nop
|
|
8005132: 3710 adds r7, #16
|
|
8005134: 46bd mov sp, r7
|
|
8005136: bd80 pop {r7, pc}
|
|
|
|
08005138 <UART_DMAReceiveCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8005138: b580 push {r7, lr}
|
|
800513a: b09c sub sp, #112 @ 0x70
|
|
800513c: af00 add r7, sp, #0
|
|
800513e: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
8005140: 687b ldr r3, [r7, #4]
|
|
8005142: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005144: 66fb str r3, [r7, #108] @ 0x6c
|
|
|
|
/* DMA Normal mode*/
|
|
if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
|
|
8005146: 687b ldr r3, [r7, #4]
|
|
8005148: 681b ldr r3, [r3, #0]
|
|
800514a: 681b ldr r3, [r3, #0]
|
|
800514c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005150: 2b00 cmp r3, #0
|
|
8005152: d172 bne.n 800523a <UART_DMAReceiveCplt+0x102>
|
|
{
|
|
huart->RxXferCount = 0U;
|
|
8005154: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005156: 2200 movs r2, #0
|
|
8005158: 85da strh r2, [r3, #46] @ 0x2e
|
|
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
800515a: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800515c: 681b ldr r3, [r3, #0]
|
|
800515e: 330c adds r3, #12
|
|
8005160: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005162: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8005164: e853 3f00 ldrex r3, [r3]
|
|
8005168: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
800516a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800516c: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8005170: 66bb str r3, [r7, #104] @ 0x68
|
|
8005172: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005174: 681b ldr r3, [r3, #0]
|
|
8005176: 330c adds r3, #12
|
|
8005178: 6eba ldr r2, [r7, #104] @ 0x68
|
|
800517a: 65ba str r2, [r7, #88] @ 0x58
|
|
800517c: 657b str r3, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800517e: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
8005180: 6dba ldr r2, [r7, #88] @ 0x58
|
|
8005182: e841 2300 strex r3, r2, [r1]
|
|
8005186: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
8005188: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
800518a: 2b00 cmp r3, #0
|
|
800518c: d1e5 bne.n 800515a <UART_DMAReceiveCplt+0x22>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800518e: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005190: 681b ldr r3, [r3, #0]
|
|
8005192: 3314 adds r3, #20
|
|
8005194: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005196: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8005198: e853 3f00 ldrex r3, [r3]
|
|
800519c: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
800519e: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80051a0: f023 0301 bic.w r3, r3, #1
|
|
80051a4: 667b str r3, [r7, #100] @ 0x64
|
|
80051a6: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80051a8: 681b ldr r3, [r3, #0]
|
|
80051aa: 3314 adds r3, #20
|
|
80051ac: 6e7a ldr r2, [r7, #100] @ 0x64
|
|
80051ae: 647a str r2, [r7, #68] @ 0x44
|
|
80051b0: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80051b2: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
80051b4: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
80051b6: e841 2300 strex r3, r2, [r1]
|
|
80051ba: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
80051bc: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80051be: 2b00 cmp r3, #0
|
|
80051c0: d1e5 bne.n 800518e <UART_DMAReceiveCplt+0x56>
|
|
|
|
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
80051c2: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80051c4: 681b ldr r3, [r3, #0]
|
|
80051c6: 3314 adds r3, #20
|
|
80051c8: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80051ca: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80051cc: e853 3f00 ldrex r3, [r3]
|
|
80051d0: 623b str r3, [r7, #32]
|
|
return(result);
|
|
80051d2: 6a3b ldr r3, [r7, #32]
|
|
80051d4: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80051d8: 663b str r3, [r7, #96] @ 0x60
|
|
80051da: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80051dc: 681b ldr r3, [r3, #0]
|
|
80051de: 3314 adds r3, #20
|
|
80051e0: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
80051e2: 633a str r2, [r7, #48] @ 0x30
|
|
80051e4: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80051e6: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80051e8: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80051ea: e841 2300 strex r3, r2, [r1]
|
|
80051ee: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
80051f0: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80051f2: 2b00 cmp r3, #0
|
|
80051f4: d1e5 bne.n 80051c2 <UART_DMAReceiveCplt+0x8a>
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80051f6: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80051f8: 2220 movs r2, #32
|
|
80051fa: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80051fe: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005200: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8005202: 2b01 cmp r3, #1
|
|
8005204: d119 bne.n 800523a <UART_DMAReceiveCplt+0x102>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8005206: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005208: 681b ldr r3, [r3, #0]
|
|
800520a: 330c adds r3, #12
|
|
800520c: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800520e: 693b ldr r3, [r7, #16]
|
|
8005210: e853 3f00 ldrex r3, [r3]
|
|
8005214: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8005216: 68fb ldr r3, [r7, #12]
|
|
8005218: f023 0310 bic.w r3, r3, #16
|
|
800521c: 65fb str r3, [r7, #92] @ 0x5c
|
|
800521e: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005220: 681b ldr r3, [r3, #0]
|
|
8005222: 330c adds r3, #12
|
|
8005224: 6dfa ldr r2, [r7, #92] @ 0x5c
|
|
8005226: 61fa str r2, [r7, #28]
|
|
8005228: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800522a: 69b9 ldr r1, [r7, #24]
|
|
800522c: 69fa ldr r2, [r7, #28]
|
|
800522e: e841 2300 strex r3, r2, [r1]
|
|
8005232: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8005234: 697b ldr r3, [r7, #20]
|
|
8005236: 2b00 cmp r3, #0
|
|
8005238: d1e5 bne.n 8005206 <UART_DMAReceiveCplt+0xce>
|
|
}
|
|
}
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
800523a: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800523c: 2200 movs r2, #0
|
|
800523e: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : use Rx Event callback */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8005240: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8005242: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8005244: 2b01 cmp r3, #1
|
|
8005246: d106 bne.n 8005256 <UART_DMAReceiveCplt+0x11e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8005248: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800524a: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
800524c: 4619 mov r1, r3
|
|
800524e: 6ef8 ldr r0, [r7, #108] @ 0x6c
|
|
8005250: f7ff ff0b bl 800506a <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
8005254: e002 b.n 800525c <UART_DMAReceiveCplt+0x124>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8005256: 6ef8 ldr r0, [r7, #108] @ 0x6c
|
|
8005258: f7fb fd0c bl 8000c74 <HAL_UART_RxCpltCallback>
|
|
}
|
|
800525c: bf00 nop
|
|
800525e: 3770 adds r7, #112 @ 0x70
|
|
8005260: 46bd mov sp, r7
|
|
8005262: bd80 pop {r7, pc}
|
|
|
|
08005264 <UART_DMARxHalfCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8005264: b580 push {r7, lr}
|
|
8005266: b084 sub sp, #16
|
|
8005268: af00 add r7, sp, #0
|
|
800526a: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
800526c: 687b ldr r3, [r7, #4]
|
|
800526e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005270: 60fb str r3, [r7, #12]
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Half Transfer */
|
|
huart->RxEventType = HAL_UART_RXEVENT_HT;
|
|
8005272: 68fb ldr r3, [r7, #12]
|
|
8005274: 2201 movs r2, #1
|
|
8005276: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : use Rx Event callback */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8005278: 68fb ldr r3, [r7, #12]
|
|
800527a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800527c: 2b01 cmp r3, #1
|
|
800527e: d108 bne.n 8005292 <UART_DMARxHalfCplt+0x2e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize / 2U);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
|
|
8005280: 68fb ldr r3, [r7, #12]
|
|
8005282: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8005284: 085b lsrs r3, r3, #1
|
|
8005286: b29b uxth r3, r3
|
|
8005288: 4619 mov r1, r3
|
|
800528a: 68f8 ldr r0, [r7, #12]
|
|
800528c: f7ff feed bl 800506a <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx Half complete callback*/
|
|
HAL_UART_RxHalfCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
8005290: e002 b.n 8005298 <UART_DMARxHalfCplt+0x34>
|
|
HAL_UART_RxHalfCpltCallback(huart);
|
|
8005292: 68f8 ldr r0, [r7, #12]
|
|
8005294: f7ff fed5 bl 8005042 <HAL_UART_RxHalfCpltCallback>
|
|
}
|
|
8005298: bf00 nop
|
|
800529a: 3710 adds r7, #16
|
|
800529c: 46bd mov sp, r7
|
|
800529e: bd80 pop {r7, pc}
|
|
|
|
080052a0 <UART_DMAError>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80052a0: b580 push {r7, lr}
|
|
80052a2: b084 sub sp, #16
|
|
80052a4: af00 add r7, sp, #0
|
|
80052a6: 6078 str r0, [r7, #4]
|
|
uint32_t dmarequest = 0x00U;
|
|
80052a8: 2300 movs r3, #0
|
|
80052aa: 60fb str r3, [r7, #12]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
80052ac: 687b ldr r3, [r7, #4]
|
|
80052ae: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80052b0: 60bb str r3, [r7, #8]
|
|
|
|
/* Stop UART DMA Tx request if ongoing */
|
|
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
|
|
80052b2: 68bb ldr r3, [r7, #8]
|
|
80052b4: 681b ldr r3, [r3, #0]
|
|
80052b6: 695b ldr r3, [r3, #20]
|
|
80052b8: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80052bc: 2b80 cmp r3, #128 @ 0x80
|
|
80052be: bf0c ite eq
|
|
80052c0: 2301 moveq r3, #1
|
|
80052c2: 2300 movne r3, #0
|
|
80052c4: b2db uxtb r3, r3
|
|
80052c6: 60fb str r3, [r7, #12]
|
|
if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
|
|
80052c8: 68bb ldr r3, [r7, #8]
|
|
80052ca: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
80052ce: b2db uxtb r3, r3
|
|
80052d0: 2b21 cmp r3, #33 @ 0x21
|
|
80052d2: d108 bne.n 80052e6 <UART_DMAError+0x46>
|
|
80052d4: 68fb ldr r3, [r7, #12]
|
|
80052d6: 2b00 cmp r3, #0
|
|
80052d8: d005 beq.n 80052e6 <UART_DMAError+0x46>
|
|
{
|
|
huart->TxXferCount = 0x00U;
|
|
80052da: 68bb ldr r3, [r7, #8]
|
|
80052dc: 2200 movs r2, #0
|
|
80052de: 84da strh r2, [r3, #38] @ 0x26
|
|
UART_EndTxTransfer(huart);
|
|
80052e0: 68b8 ldr r0, [r7, #8]
|
|
80052e2: f000 f8cd bl 8005480 <UART_EndTxTransfer>
|
|
}
|
|
|
|
/* Stop UART DMA Rx request if ongoing */
|
|
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
|
|
80052e6: 68bb ldr r3, [r7, #8]
|
|
80052e8: 681b ldr r3, [r3, #0]
|
|
80052ea: 695b ldr r3, [r3, #20]
|
|
80052ec: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80052f0: 2b40 cmp r3, #64 @ 0x40
|
|
80052f2: bf0c ite eq
|
|
80052f4: 2301 moveq r3, #1
|
|
80052f6: 2300 movne r3, #0
|
|
80052f8: b2db uxtb r3, r3
|
|
80052fa: 60fb str r3, [r7, #12]
|
|
if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
|
|
80052fc: 68bb ldr r3, [r7, #8]
|
|
80052fe: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
8005302: b2db uxtb r3, r3
|
|
8005304: 2b22 cmp r3, #34 @ 0x22
|
|
8005306: d108 bne.n 800531a <UART_DMAError+0x7a>
|
|
8005308: 68fb ldr r3, [r7, #12]
|
|
800530a: 2b00 cmp r3, #0
|
|
800530c: d005 beq.n 800531a <UART_DMAError+0x7a>
|
|
{
|
|
huart->RxXferCount = 0x00U;
|
|
800530e: 68bb ldr r3, [r7, #8]
|
|
8005310: 2200 movs r2, #0
|
|
8005312: 85da strh r2, [r3, #46] @ 0x2e
|
|
UART_EndRxTransfer(huart);
|
|
8005314: 68b8 ldr r0, [r7, #8]
|
|
8005316: f000 f8db bl 80054d0 <UART_EndRxTransfer>
|
|
}
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_DMA;
|
|
800531a: 68bb ldr r3, [r7, #8]
|
|
800531c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800531e: f043 0210 orr.w r2, r3, #16
|
|
8005322: 68bb ldr r3, [r7, #8]
|
|
8005324: 645a str r2, [r3, #68] @ 0x44
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8005326: 68b8 ldr r0, [r7, #8]
|
|
8005328: f7ff fe95 bl 8005056 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
800532c: bf00 nop
|
|
800532e: 3710 adds r7, #16
|
|
8005330: 46bd mov sp, r7
|
|
8005332: bd80 pop {r7, pc}
|
|
|
|
08005334 <UART_Start_Receive_DMA>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
8005334: b580 push {r7, lr}
|
|
8005336: b098 sub sp, #96 @ 0x60
|
|
8005338: af00 add r7, sp, #0
|
|
800533a: 60f8 str r0, [r7, #12]
|
|
800533c: 60b9 str r1, [r7, #8]
|
|
800533e: 4613 mov r3, r2
|
|
8005340: 80fb strh r3, [r7, #6]
|
|
uint32_t *tmp;
|
|
|
|
huart->pRxBuffPtr = pData;
|
|
8005342: 68ba ldr r2, [r7, #8]
|
|
8005344: 68fb ldr r3, [r7, #12]
|
|
8005346: 629a str r2, [r3, #40] @ 0x28
|
|
huart->RxXferSize = Size;
|
|
8005348: 68fb ldr r3, [r7, #12]
|
|
800534a: 88fa ldrh r2, [r7, #6]
|
|
800534c: 859a strh r2, [r3, #44] @ 0x2c
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800534e: 68fb ldr r3, [r7, #12]
|
|
8005350: 2200 movs r2, #0
|
|
8005352: 645a str r2, [r3, #68] @ 0x44
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
8005354: 68fb ldr r3, [r7, #12]
|
|
8005356: 2222 movs r2, #34 @ 0x22
|
|
8005358: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Set the UART DMA transfer complete callback */
|
|
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
|
|
800535c: 68fb ldr r3, [r7, #12]
|
|
800535e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005360: 4a44 ldr r2, [pc, #272] @ (8005474 <UART_Start_Receive_DMA+0x140>)
|
|
8005362: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Set the UART DMA Half transfer complete callback */
|
|
huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
|
|
8005364: 68fb ldr r3, [r7, #12]
|
|
8005366: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005368: 4a43 ldr r2, [pc, #268] @ (8005478 <UART_Start_Receive_DMA+0x144>)
|
|
800536a: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set the DMA error callback */
|
|
huart->hdmarx->XferErrorCallback = UART_DMAError;
|
|
800536c: 68fb ldr r3, [r7, #12]
|
|
800536e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005370: 4a42 ldr r2, [pc, #264] @ (800547c <UART_Start_Receive_DMA+0x148>)
|
|
8005372: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Set the DMA abort callback */
|
|
huart->hdmarx->XferAbortCallback = NULL;
|
|
8005374: 68fb ldr r3, [r7, #12]
|
|
8005376: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005378: 2200 movs r2, #0
|
|
800537a: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Enable the DMA stream */
|
|
tmp = (uint32_t *)&pData;
|
|
800537c: f107 0308 add.w r3, r7, #8
|
|
8005380: 65fb str r3, [r7, #92] @ 0x5c
|
|
if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK)
|
|
8005382: 68fb ldr r3, [r7, #12]
|
|
8005384: 6bd8 ldr r0, [r3, #60] @ 0x3c
|
|
8005386: 68fb ldr r3, [r7, #12]
|
|
8005388: 681b ldr r3, [r3, #0]
|
|
800538a: 3304 adds r3, #4
|
|
800538c: 4619 mov r1, r3
|
|
800538e: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8005390: 681a ldr r2, [r3, #0]
|
|
8005392: 88fb ldrh r3, [r7, #6]
|
|
8005394: f7fc fa03 bl 800179e <HAL_DMA_Start_IT>
|
|
8005398: 4603 mov r3, r0
|
|
800539a: 2b00 cmp r3, #0
|
|
800539c: d008 beq.n 80053b0 <UART_Start_Receive_DMA+0x7c>
|
|
{
|
|
/* Set error code to DMA */
|
|
huart->ErrorCode = HAL_UART_ERROR_DMA;
|
|
800539e: 68fb ldr r3, [r7, #12]
|
|
80053a0: 2210 movs r2, #16
|
|
80053a2: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Restore huart->RxState to ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80053a4: 68fb ldr r3, [r7, #12]
|
|
80053a6: 2220 movs r2, #32
|
|
80053a8: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
return HAL_ERROR;
|
|
80053ac: 2301 movs r3, #1
|
|
80053ae: e05d b.n 800546c <UART_Start_Receive_DMA+0x138>
|
|
}
|
|
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
|
|
__HAL_UART_CLEAR_OREFLAG(huart);
|
|
80053b0: 2300 movs r3, #0
|
|
80053b2: 613b str r3, [r7, #16]
|
|
80053b4: 68fb ldr r3, [r7, #12]
|
|
80053b6: 681b ldr r3, [r3, #0]
|
|
80053b8: 681b ldr r3, [r3, #0]
|
|
80053ba: 613b str r3, [r7, #16]
|
|
80053bc: 68fb ldr r3, [r7, #12]
|
|
80053be: 681b ldr r3, [r3, #0]
|
|
80053c0: 685b ldr r3, [r3, #4]
|
|
80053c2: 613b str r3, [r7, #16]
|
|
80053c4: 693b ldr r3, [r7, #16]
|
|
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
80053c6: 68fb ldr r3, [r7, #12]
|
|
80053c8: 691b ldr r3, [r3, #16]
|
|
80053ca: 2b00 cmp r3, #0
|
|
80053cc: d019 beq.n 8005402 <UART_Start_Receive_DMA+0xce>
|
|
{
|
|
/* Enable the UART Parity Error Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
80053ce: 68fb ldr r3, [r7, #12]
|
|
80053d0: 681b ldr r3, [r3, #0]
|
|
80053d2: 330c adds r3, #12
|
|
80053d4: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80053d6: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80053d8: e853 3f00 ldrex r3, [r3]
|
|
80053dc: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
80053de: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80053e0: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80053e4: 65bb str r3, [r7, #88] @ 0x58
|
|
80053e6: 68fb ldr r3, [r7, #12]
|
|
80053e8: 681b ldr r3, [r3, #0]
|
|
80053ea: 330c adds r3, #12
|
|
80053ec: 6dba ldr r2, [r7, #88] @ 0x58
|
|
80053ee: 64fa str r2, [r7, #76] @ 0x4c
|
|
80053f0: 64bb str r3, [r7, #72] @ 0x48
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80053f2: 6cb9 ldr r1, [r7, #72] @ 0x48
|
|
80053f4: 6cfa ldr r2, [r7, #76] @ 0x4c
|
|
80053f6: e841 2300 strex r3, r2, [r1]
|
|
80053fa: 647b str r3, [r7, #68] @ 0x44
|
|
return(result);
|
|
80053fc: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
80053fe: 2b00 cmp r3, #0
|
|
8005400: d1e5 bne.n 80053ce <UART_Start_Receive_DMA+0x9a>
|
|
}
|
|
|
|
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8005402: 68fb ldr r3, [r7, #12]
|
|
8005404: 681b ldr r3, [r3, #0]
|
|
8005406: 3314 adds r3, #20
|
|
8005408: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800540a: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800540c: e853 3f00 ldrex r3, [r3]
|
|
8005410: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8005412: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8005414: f043 0301 orr.w r3, r3, #1
|
|
8005418: 657b str r3, [r7, #84] @ 0x54
|
|
800541a: 68fb ldr r3, [r7, #12]
|
|
800541c: 681b ldr r3, [r3, #0]
|
|
800541e: 3314 adds r3, #20
|
|
8005420: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
8005422: 63ba str r2, [r7, #56] @ 0x38
|
|
8005424: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005426: 6b79 ldr r1, [r7, #52] @ 0x34
|
|
8005428: 6bba ldr r2, [r7, #56] @ 0x38
|
|
800542a: e841 2300 strex r3, r2, [r1]
|
|
800542e: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8005430: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8005432: 2b00 cmp r3, #0
|
|
8005434: d1e5 bne.n 8005402 <UART_Start_Receive_DMA+0xce>
|
|
|
|
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8005436: 68fb ldr r3, [r7, #12]
|
|
8005438: 681b ldr r3, [r3, #0]
|
|
800543a: 3314 adds r3, #20
|
|
800543c: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800543e: 69bb ldr r3, [r7, #24]
|
|
8005440: e853 3f00 ldrex r3, [r3]
|
|
8005444: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8005446: 697b ldr r3, [r7, #20]
|
|
8005448: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
800544c: 653b str r3, [r7, #80] @ 0x50
|
|
800544e: 68fb ldr r3, [r7, #12]
|
|
8005450: 681b ldr r3, [r3, #0]
|
|
8005452: 3314 adds r3, #20
|
|
8005454: 6d3a ldr r2, [r7, #80] @ 0x50
|
|
8005456: 627a str r2, [r7, #36] @ 0x24
|
|
8005458: 623b str r3, [r7, #32]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800545a: 6a39 ldr r1, [r7, #32]
|
|
800545c: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800545e: e841 2300 strex r3, r2, [r1]
|
|
8005462: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8005464: 69fb ldr r3, [r7, #28]
|
|
8005466: 2b00 cmp r3, #0
|
|
8005468: d1e5 bne.n 8005436 <UART_Start_Receive_DMA+0x102>
|
|
|
|
return HAL_OK;
|
|
800546a: 2300 movs r3, #0
|
|
}
|
|
800546c: 4618 mov r0, r3
|
|
800546e: 3760 adds r7, #96 @ 0x60
|
|
8005470: 46bd mov sp, r7
|
|
8005472: bd80 pop {r7, pc}
|
|
8005474: 08005139 .word 0x08005139
|
|
8005478: 08005265 .word 0x08005265
|
|
800547c: 080052a1 .word 0x080052a1
|
|
|
|
08005480 <UART_EndTxTransfer>:
|
|
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
8005480: b480 push {r7}
|
|
8005482: b089 sub sp, #36 @ 0x24
|
|
8005484: af00 add r7, sp, #0
|
|
8005486: 6078 str r0, [r7, #4]
|
|
/* Disable TXEIE and TCIE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
|
|
8005488: 687b ldr r3, [r7, #4]
|
|
800548a: 681b ldr r3, [r3, #0]
|
|
800548c: 330c adds r3, #12
|
|
800548e: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005490: 68fb ldr r3, [r7, #12]
|
|
8005492: e853 3f00 ldrex r3, [r3]
|
|
8005496: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8005498: 68bb ldr r3, [r7, #8]
|
|
800549a: f023 03c0 bic.w r3, r3, #192 @ 0xc0
|
|
800549e: 61fb str r3, [r7, #28]
|
|
80054a0: 687b ldr r3, [r7, #4]
|
|
80054a2: 681b ldr r3, [r3, #0]
|
|
80054a4: 330c adds r3, #12
|
|
80054a6: 69fa ldr r2, [r7, #28]
|
|
80054a8: 61ba str r2, [r7, #24]
|
|
80054aa: 617b str r3, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80054ac: 6979 ldr r1, [r7, #20]
|
|
80054ae: 69ba ldr r2, [r7, #24]
|
|
80054b0: e841 2300 strex r3, r2, [r1]
|
|
80054b4: 613b str r3, [r7, #16]
|
|
return(result);
|
|
80054b6: 693b ldr r3, [r7, #16]
|
|
80054b8: 2b00 cmp r3, #0
|
|
80054ba: d1e5 bne.n 8005488 <UART_EndTxTransfer+0x8>
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80054bc: 687b ldr r3, [r7, #4]
|
|
80054be: 2220 movs r2, #32
|
|
80054c0: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
}
|
|
80054c4: bf00 nop
|
|
80054c6: 3724 adds r7, #36 @ 0x24
|
|
80054c8: 46bd mov sp, r7
|
|
80054ca: f85d 7b04 ldr.w r7, [sp], #4
|
|
80054ce: 4770 bx lr
|
|
|
|
080054d0 <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
80054d0: b480 push {r7}
|
|
80054d2: b095 sub sp, #84 @ 0x54
|
|
80054d4: af00 add r7, sp, #0
|
|
80054d6: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
80054d8: 687b ldr r3, [r7, #4]
|
|
80054da: 681b ldr r3, [r3, #0]
|
|
80054dc: 330c adds r3, #12
|
|
80054de: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80054e0: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80054e2: e853 3f00 ldrex r3, [r3]
|
|
80054e6: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
80054e8: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80054ea: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
80054ee: 64fb str r3, [r7, #76] @ 0x4c
|
|
80054f0: 687b ldr r3, [r7, #4]
|
|
80054f2: 681b ldr r3, [r3, #0]
|
|
80054f4: 330c adds r3, #12
|
|
80054f6: 6cfa ldr r2, [r7, #76] @ 0x4c
|
|
80054f8: 643a str r2, [r7, #64] @ 0x40
|
|
80054fa: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80054fc: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
80054fe: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8005500: e841 2300 strex r3, r2, [r1]
|
|
8005504: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8005506: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8005508: 2b00 cmp r3, #0
|
|
800550a: d1e5 bne.n 80054d8 <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800550c: 687b ldr r3, [r7, #4]
|
|
800550e: 681b ldr r3, [r3, #0]
|
|
8005510: 3314 adds r3, #20
|
|
8005512: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005514: 6a3b ldr r3, [r7, #32]
|
|
8005516: e853 3f00 ldrex r3, [r3]
|
|
800551a: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
800551c: 69fb ldr r3, [r7, #28]
|
|
800551e: f023 0301 bic.w r3, r3, #1
|
|
8005522: 64bb str r3, [r7, #72] @ 0x48
|
|
8005524: 687b ldr r3, [r7, #4]
|
|
8005526: 681b ldr r3, [r3, #0]
|
|
8005528: 3314 adds r3, #20
|
|
800552a: 6cba ldr r2, [r7, #72] @ 0x48
|
|
800552c: 62fa str r2, [r7, #44] @ 0x2c
|
|
800552e: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005530: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8005532: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8005534: e841 2300 strex r3, r2, [r1]
|
|
8005538: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
800553a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800553c: 2b00 cmp r3, #0
|
|
800553e: d1e5 bne.n 800550c <UART_EndRxTransfer+0x3c>
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8005540: 687b ldr r3, [r7, #4]
|
|
8005542: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8005544: 2b01 cmp r3, #1
|
|
8005546: d119 bne.n 800557c <UART_EndRxTransfer+0xac>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8005548: 687b ldr r3, [r7, #4]
|
|
800554a: 681b ldr r3, [r3, #0]
|
|
800554c: 330c adds r3, #12
|
|
800554e: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005550: 68fb ldr r3, [r7, #12]
|
|
8005552: e853 3f00 ldrex r3, [r3]
|
|
8005556: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8005558: 68bb ldr r3, [r7, #8]
|
|
800555a: f023 0310 bic.w r3, r3, #16
|
|
800555e: 647b str r3, [r7, #68] @ 0x44
|
|
8005560: 687b ldr r3, [r7, #4]
|
|
8005562: 681b ldr r3, [r3, #0]
|
|
8005564: 330c adds r3, #12
|
|
8005566: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8005568: 61ba str r2, [r7, #24]
|
|
800556a: 617b str r3, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800556c: 6979 ldr r1, [r7, #20]
|
|
800556e: 69ba ldr r2, [r7, #24]
|
|
8005570: e841 2300 strex r3, r2, [r1]
|
|
8005574: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8005576: 693b ldr r3, [r7, #16]
|
|
8005578: 2b00 cmp r3, #0
|
|
800557a: d1e5 bne.n 8005548 <UART_EndRxTransfer+0x78>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800557c: 687b ldr r3, [r7, #4]
|
|
800557e: 2220 movs r2, #32
|
|
8005580: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8005584: 687b ldr r3, [r7, #4]
|
|
8005586: 2200 movs r2, #0
|
|
8005588: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
800558a: bf00 nop
|
|
800558c: 3754 adds r7, #84 @ 0x54
|
|
800558e: 46bd mov sp, r7
|
|
8005590: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005594: 4770 bx lr
|
|
...
|
|
|
|
08005598 <UART_SetConfig>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8005598: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
800559c: b0c0 sub sp, #256 @ 0x100
|
|
800559e: af00 add r7, sp, #0
|
|
80055a0: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4
|
|
assert_param(IS_UART_MODE(huart->Init.Mode));
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits
|
|
according to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
80055a4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055a8: 681b ldr r3, [r3, #0]
|
|
80055aa: 691b ldr r3, [r3, #16]
|
|
80055ac: f423 5040 bic.w r0, r3, #12288 @ 0x3000
|
|
80055b0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055b4: 68d9 ldr r1, [r3, #12]
|
|
80055b6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055ba: 681a ldr r2, [r3, #0]
|
|
80055bc: ea40 0301 orr.w r3, r0, r1
|
|
80055c0: 6113 str r3, [r2, #16]
|
|
Set the M bits according to huart->Init.WordLength value
|
|
Set PCE and PS bits according to huart->Init.Parity value
|
|
Set TE and RE bits according to huart->Init.Mode value
|
|
Set OVER8 bit according to huart->Init.OverSampling value */
|
|
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
|
|
80055c2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055c6: 689a ldr r2, [r3, #8]
|
|
80055c8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055cc: 691b ldr r3, [r3, #16]
|
|
80055ce: 431a orrs r2, r3
|
|
80055d0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055d4: 695b ldr r3, [r3, #20]
|
|
80055d6: 431a orrs r2, r3
|
|
80055d8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055dc: 69db ldr r3, [r3, #28]
|
|
80055de: 4313 orrs r3, r2
|
|
80055e0: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
80055e4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055e8: 681b ldr r3, [r3, #0]
|
|
80055ea: 68db ldr r3, [r3, #12]
|
|
80055ec: f423 4116 bic.w r1, r3, #38400 @ 0x9600
|
|
80055f0: f021 010c bic.w r1, r1, #12
|
|
80055f4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80055f8: 681a ldr r2, [r3, #0]
|
|
80055fa: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
|
|
80055fe: 430b orrs r3, r1
|
|
8005600: 60d3 str r3, [r2, #12]
|
|
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
|
tmpreg);
|
|
|
|
/*-------------------------- USART CR3 Configuration -----------------------*/
|
|
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
|
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
|
8005602: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005606: 681b ldr r3, [r3, #0]
|
|
8005608: 695b ldr r3, [r3, #20]
|
|
800560a: f423 7040 bic.w r0, r3, #768 @ 0x300
|
|
800560e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005612: 6999 ldr r1, [r3, #24]
|
|
8005614: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005618: 681a ldr r2, [r3, #0]
|
|
800561a: ea40 0301 orr.w r3, r0, r1
|
|
800561e: 6153 str r3, [r2, #20]
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#elif defined(USART6)
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6))
|
|
8005620: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005624: 681a ldr r2, [r3, #0]
|
|
8005626: 4b8f ldr r3, [pc, #572] @ (8005864 <UART_SetConfig+0x2cc>)
|
|
8005628: 429a cmp r2, r3
|
|
800562a: d005 beq.n 8005638 <UART_SetConfig+0xa0>
|
|
800562c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005630: 681a ldr r2, [r3, #0]
|
|
8005632: 4b8d ldr r3, [pc, #564] @ (8005868 <UART_SetConfig+0x2d0>)
|
|
8005634: 429a cmp r2, r3
|
|
8005636: d104 bne.n 8005642 <UART_SetConfig+0xaa>
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8005638: f7fd ffce bl 80035d8 <HAL_RCC_GetPCLK2Freq>
|
|
800563c: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
8005640: e003 b.n 800564a <UART_SetConfig+0xb2>
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#endif /* USART6 */
|
|
else
|
|
{
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8005642: f7fd ffb5 bl 80035b0 <HAL_RCC_GetPCLK1Freq>
|
|
8005646: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
}
|
|
/*-------------------------- USART BRR Configuration ---------------------*/
|
|
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
800564a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800564e: 69db ldr r3, [r3, #28]
|
|
8005650: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8005654: f040 810c bne.w 8005870 <UART_SetConfig+0x2d8>
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
|
|
8005658: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
800565c: 2200 movs r2, #0
|
|
800565e: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
|
|
8005662: f8c7 20ec str.w r2, [r7, #236] @ 0xec
|
|
8005666: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8
|
|
800566a: 4622 mov r2, r4
|
|
800566c: 462b mov r3, r5
|
|
800566e: 1891 adds r1, r2, r2
|
|
8005670: 65b9 str r1, [r7, #88] @ 0x58
|
|
8005672: 415b adcs r3, r3
|
|
8005674: 65fb str r3, [r7, #92] @ 0x5c
|
|
8005676: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
|
|
800567a: 4621 mov r1, r4
|
|
800567c: eb12 0801 adds.w r8, r2, r1
|
|
8005680: 4629 mov r1, r5
|
|
8005682: eb43 0901 adc.w r9, r3, r1
|
|
8005686: f04f 0200 mov.w r2, #0
|
|
800568a: f04f 0300 mov.w r3, #0
|
|
800568e: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8005692: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8005696: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
800569a: 4690 mov r8, r2
|
|
800569c: 4699 mov r9, r3
|
|
800569e: 4623 mov r3, r4
|
|
80056a0: eb18 0303 adds.w r3, r8, r3
|
|
80056a4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
80056a8: 462b mov r3, r5
|
|
80056aa: eb49 0303 adc.w r3, r9, r3
|
|
80056ae: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
80056b2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80056b6: 685b ldr r3, [r3, #4]
|
|
80056b8: 2200 movs r2, #0
|
|
80056ba: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
80056be: f8c7 20dc str.w r2, [r7, #220] @ 0xdc
|
|
80056c2: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8
|
|
80056c6: 460b mov r3, r1
|
|
80056c8: 18db adds r3, r3, r3
|
|
80056ca: 653b str r3, [r7, #80] @ 0x50
|
|
80056cc: 4613 mov r3, r2
|
|
80056ce: eb42 0303 adc.w r3, r2, r3
|
|
80056d2: 657b str r3, [r7, #84] @ 0x54
|
|
80056d4: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50
|
|
80056d8: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0
|
|
80056dc: f7fa fd92 bl 8000204 <__aeabi_uldivmod>
|
|
80056e0: 4602 mov r2, r0
|
|
80056e2: 460b mov r3, r1
|
|
80056e4: 4b61 ldr r3, [pc, #388] @ (800586c <UART_SetConfig+0x2d4>)
|
|
80056e6: fba3 2302 umull r2, r3, r3, r2
|
|
80056ea: 095b lsrs r3, r3, #5
|
|
80056ec: 011c lsls r4, r3, #4
|
|
80056ee: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80056f2: 2200 movs r2, #0
|
|
80056f4: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
80056f8: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4
|
|
80056fc: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0
|
|
8005700: 4642 mov r2, r8
|
|
8005702: 464b mov r3, r9
|
|
8005704: 1891 adds r1, r2, r2
|
|
8005706: 64b9 str r1, [r7, #72] @ 0x48
|
|
8005708: 415b adcs r3, r3
|
|
800570a: 64fb str r3, [r7, #76] @ 0x4c
|
|
800570c: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
|
|
8005710: 4641 mov r1, r8
|
|
8005712: eb12 0a01 adds.w sl, r2, r1
|
|
8005716: 4649 mov r1, r9
|
|
8005718: eb43 0b01 adc.w fp, r3, r1
|
|
800571c: f04f 0200 mov.w r2, #0
|
|
8005720: f04f 0300 mov.w r3, #0
|
|
8005724: ea4f 03cb mov.w r3, fp, lsl #3
|
|
8005728: ea43 735a orr.w r3, r3, sl, lsr #29
|
|
800572c: ea4f 02ca mov.w r2, sl, lsl #3
|
|
8005730: 4692 mov sl, r2
|
|
8005732: 469b mov fp, r3
|
|
8005734: 4643 mov r3, r8
|
|
8005736: eb1a 0303 adds.w r3, sl, r3
|
|
800573a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
800573e: 464b mov r3, r9
|
|
8005740: eb4b 0303 adc.w r3, fp, r3
|
|
8005744: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
|
|
8005748: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800574c: 685b ldr r3, [r3, #4]
|
|
800574e: 2200 movs r2, #0
|
|
8005750: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
8005754: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4
|
|
8005758: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0
|
|
800575c: 460b mov r3, r1
|
|
800575e: 18db adds r3, r3, r3
|
|
8005760: 643b str r3, [r7, #64] @ 0x40
|
|
8005762: 4613 mov r3, r2
|
|
8005764: eb42 0303 adc.w r3, r2, r3
|
|
8005768: 647b str r3, [r7, #68] @ 0x44
|
|
800576a: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40
|
|
800576e: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8
|
|
8005772: f7fa fd47 bl 8000204 <__aeabi_uldivmod>
|
|
8005776: 4602 mov r2, r0
|
|
8005778: 460b mov r3, r1
|
|
800577a: 4611 mov r1, r2
|
|
800577c: 4b3b ldr r3, [pc, #236] @ (800586c <UART_SetConfig+0x2d4>)
|
|
800577e: fba3 2301 umull r2, r3, r3, r1
|
|
8005782: 095b lsrs r3, r3, #5
|
|
8005784: 2264 movs r2, #100 @ 0x64
|
|
8005786: fb02 f303 mul.w r3, r2, r3
|
|
800578a: 1acb subs r3, r1, r3
|
|
800578c: 00db lsls r3, r3, #3
|
|
800578e: f103 0232 add.w r2, r3, #50 @ 0x32
|
|
8005792: 4b36 ldr r3, [pc, #216] @ (800586c <UART_SetConfig+0x2d4>)
|
|
8005794: fba3 2302 umull r2, r3, r3, r2
|
|
8005798: 095b lsrs r3, r3, #5
|
|
800579a: 005b lsls r3, r3, #1
|
|
800579c: f403 73f8 and.w r3, r3, #496 @ 0x1f0
|
|
80057a0: 441c add r4, r3
|
|
80057a2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80057a6: 2200 movs r2, #0
|
|
80057a8: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
80057ac: f8c7 20bc str.w r2, [r7, #188] @ 0xbc
|
|
80057b0: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8
|
|
80057b4: 4642 mov r2, r8
|
|
80057b6: 464b mov r3, r9
|
|
80057b8: 1891 adds r1, r2, r2
|
|
80057ba: 63b9 str r1, [r7, #56] @ 0x38
|
|
80057bc: 415b adcs r3, r3
|
|
80057be: 63fb str r3, [r7, #60] @ 0x3c
|
|
80057c0: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38
|
|
80057c4: 4641 mov r1, r8
|
|
80057c6: 1851 adds r1, r2, r1
|
|
80057c8: 6339 str r1, [r7, #48] @ 0x30
|
|
80057ca: 4649 mov r1, r9
|
|
80057cc: 414b adcs r3, r1
|
|
80057ce: 637b str r3, [r7, #52] @ 0x34
|
|
80057d0: f04f 0200 mov.w r2, #0
|
|
80057d4: f04f 0300 mov.w r3, #0
|
|
80057d8: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30
|
|
80057dc: 4659 mov r1, fp
|
|
80057de: 00cb lsls r3, r1, #3
|
|
80057e0: 4651 mov r1, sl
|
|
80057e2: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
80057e6: 4651 mov r1, sl
|
|
80057e8: 00ca lsls r2, r1, #3
|
|
80057ea: 4610 mov r0, r2
|
|
80057ec: 4619 mov r1, r3
|
|
80057ee: 4603 mov r3, r0
|
|
80057f0: 4642 mov r2, r8
|
|
80057f2: 189b adds r3, r3, r2
|
|
80057f4: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
80057f8: 464b mov r3, r9
|
|
80057fa: 460a mov r2, r1
|
|
80057fc: eb42 0303 adc.w r3, r2, r3
|
|
8005800: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8005804: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005808: 685b ldr r3, [r3, #4]
|
|
800580a: 2200 movs r2, #0
|
|
800580c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
8005810: f8c7 20ac str.w r2, [r7, #172] @ 0xac
|
|
8005814: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8
|
|
8005818: 460b mov r3, r1
|
|
800581a: 18db adds r3, r3, r3
|
|
800581c: 62bb str r3, [r7, #40] @ 0x28
|
|
800581e: 4613 mov r3, r2
|
|
8005820: eb42 0303 adc.w r3, r2, r3
|
|
8005824: 62fb str r3, [r7, #44] @ 0x2c
|
|
8005826: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
|
|
800582a: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0
|
|
800582e: f7fa fce9 bl 8000204 <__aeabi_uldivmod>
|
|
8005832: 4602 mov r2, r0
|
|
8005834: 460b mov r3, r1
|
|
8005836: 4b0d ldr r3, [pc, #52] @ (800586c <UART_SetConfig+0x2d4>)
|
|
8005838: fba3 1302 umull r1, r3, r3, r2
|
|
800583c: 095b lsrs r3, r3, #5
|
|
800583e: 2164 movs r1, #100 @ 0x64
|
|
8005840: fb01 f303 mul.w r3, r1, r3
|
|
8005844: 1ad3 subs r3, r2, r3
|
|
8005846: 00db lsls r3, r3, #3
|
|
8005848: 3332 adds r3, #50 @ 0x32
|
|
800584a: 4a08 ldr r2, [pc, #32] @ (800586c <UART_SetConfig+0x2d4>)
|
|
800584c: fba2 2303 umull r2, r3, r2, r3
|
|
8005850: 095b lsrs r3, r3, #5
|
|
8005852: f003 0207 and.w r2, r3, #7
|
|
8005856: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800585a: 681b ldr r3, [r3, #0]
|
|
800585c: 4422 add r2, r4
|
|
800585e: 609a str r2, [r3, #8]
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
}
|
|
}
|
|
8005860: e106 b.n 8005a70 <UART_SetConfig+0x4d8>
|
|
8005862: bf00 nop
|
|
8005864: 40011000 .word 0x40011000
|
|
8005868: 40011400 .word 0x40011400
|
|
800586c: 51eb851f .word 0x51eb851f
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
8005870: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8005874: 2200 movs r2, #0
|
|
8005876: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
800587a: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4
|
|
800587e: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0
|
|
8005882: 4642 mov r2, r8
|
|
8005884: 464b mov r3, r9
|
|
8005886: 1891 adds r1, r2, r2
|
|
8005888: 6239 str r1, [r7, #32]
|
|
800588a: 415b adcs r3, r3
|
|
800588c: 627b str r3, [r7, #36] @ 0x24
|
|
800588e: e9d7 2308 ldrd r2, r3, [r7, #32]
|
|
8005892: 4641 mov r1, r8
|
|
8005894: 1854 adds r4, r2, r1
|
|
8005896: 4649 mov r1, r9
|
|
8005898: eb43 0501 adc.w r5, r3, r1
|
|
800589c: f04f 0200 mov.w r2, #0
|
|
80058a0: f04f 0300 mov.w r3, #0
|
|
80058a4: 00eb lsls r3, r5, #3
|
|
80058a6: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
80058aa: 00e2 lsls r2, r4, #3
|
|
80058ac: 4614 mov r4, r2
|
|
80058ae: 461d mov r5, r3
|
|
80058b0: 4643 mov r3, r8
|
|
80058b2: 18e3 adds r3, r4, r3
|
|
80058b4: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
80058b8: 464b mov r3, r9
|
|
80058ba: eb45 0303 adc.w r3, r5, r3
|
|
80058be: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
80058c2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80058c6: 685b ldr r3, [r3, #4]
|
|
80058c8: 2200 movs r2, #0
|
|
80058ca: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
80058ce: f8c7 2094 str.w r2, [r7, #148] @ 0x94
|
|
80058d2: f04f 0200 mov.w r2, #0
|
|
80058d6: f04f 0300 mov.w r3, #0
|
|
80058da: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
|
|
80058de: 4629 mov r1, r5
|
|
80058e0: 008b lsls r3, r1, #2
|
|
80058e2: 4621 mov r1, r4
|
|
80058e4: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
80058e8: 4621 mov r1, r4
|
|
80058ea: 008a lsls r2, r1, #2
|
|
80058ec: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98
|
|
80058f0: f7fa fc88 bl 8000204 <__aeabi_uldivmod>
|
|
80058f4: 4602 mov r2, r0
|
|
80058f6: 460b mov r3, r1
|
|
80058f8: 4b60 ldr r3, [pc, #384] @ (8005a7c <UART_SetConfig+0x4e4>)
|
|
80058fa: fba3 2302 umull r2, r3, r3, r2
|
|
80058fe: 095b lsrs r3, r3, #5
|
|
8005900: 011c lsls r4, r3, #4
|
|
8005902: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8005906: 2200 movs r2, #0
|
|
8005908: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
800590c: f8c7 208c str.w r2, [r7, #140] @ 0x8c
|
|
8005910: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88
|
|
8005914: 4642 mov r2, r8
|
|
8005916: 464b mov r3, r9
|
|
8005918: 1891 adds r1, r2, r2
|
|
800591a: 61b9 str r1, [r7, #24]
|
|
800591c: 415b adcs r3, r3
|
|
800591e: 61fb str r3, [r7, #28]
|
|
8005920: e9d7 2306 ldrd r2, r3, [r7, #24]
|
|
8005924: 4641 mov r1, r8
|
|
8005926: 1851 adds r1, r2, r1
|
|
8005928: 6139 str r1, [r7, #16]
|
|
800592a: 4649 mov r1, r9
|
|
800592c: 414b adcs r3, r1
|
|
800592e: 617b str r3, [r7, #20]
|
|
8005930: f04f 0200 mov.w r2, #0
|
|
8005934: f04f 0300 mov.w r3, #0
|
|
8005938: e9d7 ab04 ldrd sl, fp, [r7, #16]
|
|
800593c: 4659 mov r1, fp
|
|
800593e: 00cb lsls r3, r1, #3
|
|
8005940: 4651 mov r1, sl
|
|
8005942: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8005946: 4651 mov r1, sl
|
|
8005948: 00ca lsls r2, r1, #3
|
|
800594a: 4610 mov r0, r2
|
|
800594c: 4619 mov r1, r3
|
|
800594e: 4603 mov r3, r0
|
|
8005950: 4642 mov r2, r8
|
|
8005952: 189b adds r3, r3, r2
|
|
8005954: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8005958: 464b mov r3, r9
|
|
800595a: 460a mov r2, r1
|
|
800595c: eb42 0303 adc.w r3, r2, r3
|
|
8005960: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8005964: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005968: 685b ldr r3, [r3, #4]
|
|
800596a: 2200 movs r2, #0
|
|
800596c: 67bb str r3, [r7, #120] @ 0x78
|
|
800596e: 67fa str r2, [r7, #124] @ 0x7c
|
|
8005970: f04f 0200 mov.w r2, #0
|
|
8005974: f04f 0300 mov.w r3, #0
|
|
8005978: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78
|
|
800597c: 4649 mov r1, r9
|
|
800597e: 008b lsls r3, r1, #2
|
|
8005980: 4641 mov r1, r8
|
|
8005982: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8005986: 4641 mov r1, r8
|
|
8005988: 008a lsls r2, r1, #2
|
|
800598a: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80
|
|
800598e: f7fa fc39 bl 8000204 <__aeabi_uldivmod>
|
|
8005992: 4602 mov r2, r0
|
|
8005994: 460b mov r3, r1
|
|
8005996: 4611 mov r1, r2
|
|
8005998: 4b38 ldr r3, [pc, #224] @ (8005a7c <UART_SetConfig+0x4e4>)
|
|
800599a: fba3 2301 umull r2, r3, r3, r1
|
|
800599e: 095b lsrs r3, r3, #5
|
|
80059a0: 2264 movs r2, #100 @ 0x64
|
|
80059a2: fb02 f303 mul.w r3, r2, r3
|
|
80059a6: 1acb subs r3, r1, r3
|
|
80059a8: 011b lsls r3, r3, #4
|
|
80059aa: 3332 adds r3, #50 @ 0x32
|
|
80059ac: 4a33 ldr r2, [pc, #204] @ (8005a7c <UART_SetConfig+0x4e4>)
|
|
80059ae: fba2 2303 umull r2, r3, r2, r3
|
|
80059b2: 095b lsrs r3, r3, #5
|
|
80059b4: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
80059b8: 441c add r4, r3
|
|
80059ba: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80059be: 2200 movs r2, #0
|
|
80059c0: 673b str r3, [r7, #112] @ 0x70
|
|
80059c2: 677a str r2, [r7, #116] @ 0x74
|
|
80059c4: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70
|
|
80059c8: 4642 mov r2, r8
|
|
80059ca: 464b mov r3, r9
|
|
80059cc: 1891 adds r1, r2, r2
|
|
80059ce: 60b9 str r1, [r7, #8]
|
|
80059d0: 415b adcs r3, r3
|
|
80059d2: 60fb str r3, [r7, #12]
|
|
80059d4: e9d7 2302 ldrd r2, r3, [r7, #8]
|
|
80059d8: 4641 mov r1, r8
|
|
80059da: 1851 adds r1, r2, r1
|
|
80059dc: 6039 str r1, [r7, #0]
|
|
80059de: 4649 mov r1, r9
|
|
80059e0: 414b adcs r3, r1
|
|
80059e2: 607b str r3, [r7, #4]
|
|
80059e4: f04f 0200 mov.w r2, #0
|
|
80059e8: f04f 0300 mov.w r3, #0
|
|
80059ec: e9d7 ab00 ldrd sl, fp, [r7]
|
|
80059f0: 4659 mov r1, fp
|
|
80059f2: 00cb lsls r3, r1, #3
|
|
80059f4: 4651 mov r1, sl
|
|
80059f6: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
80059fa: 4651 mov r1, sl
|
|
80059fc: 00ca lsls r2, r1, #3
|
|
80059fe: 4610 mov r0, r2
|
|
8005a00: 4619 mov r1, r3
|
|
8005a02: 4603 mov r3, r0
|
|
8005a04: 4642 mov r2, r8
|
|
8005a06: 189b adds r3, r3, r2
|
|
8005a08: 66bb str r3, [r7, #104] @ 0x68
|
|
8005a0a: 464b mov r3, r9
|
|
8005a0c: 460a mov r2, r1
|
|
8005a0e: eb42 0303 adc.w r3, r2, r3
|
|
8005a12: 66fb str r3, [r7, #108] @ 0x6c
|
|
8005a14: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005a18: 685b ldr r3, [r3, #4]
|
|
8005a1a: 2200 movs r2, #0
|
|
8005a1c: 663b str r3, [r7, #96] @ 0x60
|
|
8005a1e: 667a str r2, [r7, #100] @ 0x64
|
|
8005a20: f04f 0200 mov.w r2, #0
|
|
8005a24: f04f 0300 mov.w r3, #0
|
|
8005a28: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60
|
|
8005a2c: 4649 mov r1, r9
|
|
8005a2e: 008b lsls r3, r1, #2
|
|
8005a30: 4641 mov r1, r8
|
|
8005a32: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8005a36: 4641 mov r1, r8
|
|
8005a38: 008a lsls r2, r1, #2
|
|
8005a3a: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68
|
|
8005a3e: f7fa fbe1 bl 8000204 <__aeabi_uldivmod>
|
|
8005a42: 4602 mov r2, r0
|
|
8005a44: 460b mov r3, r1
|
|
8005a46: 4b0d ldr r3, [pc, #52] @ (8005a7c <UART_SetConfig+0x4e4>)
|
|
8005a48: fba3 1302 umull r1, r3, r3, r2
|
|
8005a4c: 095b lsrs r3, r3, #5
|
|
8005a4e: 2164 movs r1, #100 @ 0x64
|
|
8005a50: fb01 f303 mul.w r3, r1, r3
|
|
8005a54: 1ad3 subs r3, r2, r3
|
|
8005a56: 011b lsls r3, r3, #4
|
|
8005a58: 3332 adds r3, #50 @ 0x32
|
|
8005a5a: 4a08 ldr r2, [pc, #32] @ (8005a7c <UART_SetConfig+0x4e4>)
|
|
8005a5c: fba2 2303 umull r2, r3, r2, r3
|
|
8005a60: 095b lsrs r3, r3, #5
|
|
8005a62: f003 020f and.w r2, r3, #15
|
|
8005a66: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005a6a: 681b ldr r3, [r3, #0]
|
|
8005a6c: 4422 add r2, r4
|
|
8005a6e: 609a str r2, [r3, #8]
|
|
}
|
|
8005a70: bf00 nop
|
|
8005a72: f507 7780 add.w r7, r7, #256 @ 0x100
|
|
8005a76: 46bd mov sp, r7
|
|
8005a78: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8005a7c: 51eb851f .word 0x51eb851f
|
|
|
|
08005a80 <USB_CoreInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8005a80: b084 sub sp, #16
|
|
8005a82: b580 push {r7, lr}
|
|
8005a84: b084 sub sp, #16
|
|
8005a86: af00 add r7, sp, #0
|
|
8005a88: 6078 str r0, [r7, #4]
|
|
8005a8a: f107 001c add.w r0, r7, #28
|
|
8005a8e: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret;
|
|
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
|
|
8005a92: f897 3021 ldrb.w r3, [r7, #33] @ 0x21
|
|
8005a96: 2b01 cmp r3, #1
|
|
8005a98: d123 bne.n 8005ae2 <USB_CoreInit+0x62>
|
|
{
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
8005a9a: 687b ldr r3, [r7, #4]
|
|
8005a9c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005a9e: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
8005aa2: 687b ldr r3, [r7, #4]
|
|
8005aa4: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Init The ULPI Interface */
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
|
|
8005aa6: 687b ldr r3, [r7, #4]
|
|
8005aa8: 68db ldr r3, [r3, #12]
|
|
8005aaa: f423 0384 bic.w r3, r3, #4325376 @ 0x420000
|
|
8005aae: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005ab2: 687a ldr r2, [r7, #4]
|
|
8005ab4: 60d3 str r3, [r2, #12]
|
|
|
|
/* Select vbus source */
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
|
|
8005ab6: 687b ldr r3, [r7, #4]
|
|
8005ab8: 68db ldr r3, [r3, #12]
|
|
8005aba: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
8005abe: 687b ldr r3, [r7, #4]
|
|
8005ac0: 60da str r2, [r3, #12]
|
|
if (cfg.use_external_vbus == 1U)
|
|
8005ac2: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8005ac6: 2b01 cmp r3, #1
|
|
8005ac8: d105 bne.n 8005ad6 <USB_CoreInit+0x56>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
|
|
8005aca: 687b ldr r3, [r7, #4]
|
|
8005acc: 68db ldr r3, [r3, #12]
|
|
8005ace: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
|
|
8005ad2: 687b ldr r3, [r7, #4]
|
|
8005ad4: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
8005ad6: 6878 ldr r0, [r7, #4]
|
|
8005ad8: f001 fae2 bl 80070a0 <USB_CoreReset>
|
|
8005adc: 4603 mov r3, r0
|
|
8005ade: 73fb strb r3, [r7, #15]
|
|
8005ae0: e01b b.n 8005b1a <USB_CoreInit+0x9a>
|
|
}
|
|
else /* FS interface (embedded Phy) */
|
|
{
|
|
/* Select FS Embedded PHY */
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
|
|
8005ae2: 687b ldr r3, [r7, #4]
|
|
8005ae4: 68db ldr r3, [r3, #12]
|
|
8005ae6: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
8005aea: 687b ldr r3, [r7, #4]
|
|
8005aec: 60da str r2, [r3, #12]
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
8005aee: 6878 ldr r0, [r7, #4]
|
|
8005af0: f001 fad6 bl 80070a0 <USB_CoreReset>
|
|
8005af4: 4603 mov r3, r0
|
|
8005af6: 73fb strb r3, [r7, #15]
|
|
|
|
if (cfg.battery_charging_enable == 0U)
|
|
8005af8: f897 3025 ldrb.w r3, [r7, #37] @ 0x25
|
|
8005afc: 2b00 cmp r3, #0
|
|
8005afe: d106 bne.n 8005b0e <USB_CoreInit+0x8e>
|
|
{
|
|
/* Activate the USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
8005b00: 687b ldr r3, [r7, #4]
|
|
8005b02: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005b04: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
8005b08: 687b ldr r3, [r7, #4]
|
|
8005b0a: 639a str r2, [r3, #56] @ 0x38
|
|
8005b0c: e005 b.n 8005b1a <USB_CoreInit+0x9a>
|
|
}
|
|
else
|
|
{
|
|
/* Deactivate the USB Transceiver */
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
8005b0e: 687b ldr r3, [r7, #4]
|
|
8005b10: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005b12: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
8005b16: 687b ldr r3, [r7, #4]
|
|
8005b18: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
}
|
|
|
|
if (cfg.dma_enable == 1U)
|
|
8005b1a: 7fbb ldrb r3, [r7, #30]
|
|
8005b1c: 2b01 cmp r3, #1
|
|
8005b1e: d10b bne.n 8005b38 <USB_CoreInit+0xb8>
|
|
{
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
|
|
8005b20: 687b ldr r3, [r7, #4]
|
|
8005b22: 689b ldr r3, [r3, #8]
|
|
8005b24: f043 0206 orr.w r2, r3, #6
|
|
8005b28: 687b ldr r3, [r7, #4]
|
|
8005b2a: 609a str r2, [r3, #8]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
|
|
8005b2c: 687b ldr r3, [r7, #4]
|
|
8005b2e: 689b ldr r3, [r3, #8]
|
|
8005b30: f043 0220 orr.w r2, r3, #32
|
|
8005b34: 687b ldr r3, [r7, #4]
|
|
8005b36: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
return ret;
|
|
8005b38: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8005b3a: 4618 mov r0, r3
|
|
8005b3c: 3710 adds r7, #16
|
|
8005b3e: 46bd mov sp, r7
|
|
8005b40: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
8005b44: b004 add sp, #16
|
|
8005b46: 4770 bx lr
|
|
|
|
08005b48 <USB_SetTurnaroundTime>:
|
|
* @param hclk: AHB clock frequency
|
|
* @retval USB turnaround time In PHY Clocks number
|
|
*/
|
|
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
|
|
uint32_t hclk, uint8_t speed)
|
|
{
|
|
8005b48: b480 push {r7}
|
|
8005b4a: b087 sub sp, #28
|
|
8005b4c: af00 add r7, sp, #0
|
|
8005b4e: 60f8 str r0, [r7, #12]
|
|
8005b50: 60b9 str r1, [r7, #8]
|
|
8005b52: 4613 mov r3, r2
|
|
8005b54: 71fb strb r3, [r7, #7]
|
|
|
|
/* The USBTRD is configured according to the tables below, depending on AHB frequency
|
|
used by application. In the low AHB frequency range it is used to stretch enough the USB response
|
|
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
|
|
latency to the Data FIFO */
|
|
if (speed == USBD_FS_SPEED)
|
|
8005b56: 79fb ldrb r3, [r7, #7]
|
|
8005b58: 2b02 cmp r3, #2
|
|
8005b5a: d165 bne.n 8005c28 <USB_SetTurnaroundTime+0xe0>
|
|
{
|
|
if ((hclk >= 14200000U) && (hclk < 15000000U))
|
|
8005b5c: 68bb ldr r3, [r7, #8]
|
|
8005b5e: 4a41 ldr r2, [pc, #260] @ (8005c64 <USB_SetTurnaroundTime+0x11c>)
|
|
8005b60: 4293 cmp r3, r2
|
|
8005b62: d906 bls.n 8005b72 <USB_SetTurnaroundTime+0x2a>
|
|
8005b64: 68bb ldr r3, [r7, #8]
|
|
8005b66: 4a40 ldr r2, [pc, #256] @ (8005c68 <USB_SetTurnaroundTime+0x120>)
|
|
8005b68: 4293 cmp r3, r2
|
|
8005b6a: d202 bcs.n 8005b72 <USB_SetTurnaroundTime+0x2a>
|
|
{
|
|
/* hclk Clock Range between 14.2-15 MHz */
|
|
UsbTrd = 0xFU;
|
|
8005b6c: 230f movs r3, #15
|
|
8005b6e: 617b str r3, [r7, #20]
|
|
8005b70: e062 b.n 8005c38 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 15000000U) && (hclk < 16000000U))
|
|
8005b72: 68bb ldr r3, [r7, #8]
|
|
8005b74: 4a3c ldr r2, [pc, #240] @ (8005c68 <USB_SetTurnaroundTime+0x120>)
|
|
8005b76: 4293 cmp r3, r2
|
|
8005b78: d306 bcc.n 8005b88 <USB_SetTurnaroundTime+0x40>
|
|
8005b7a: 68bb ldr r3, [r7, #8]
|
|
8005b7c: 4a3b ldr r2, [pc, #236] @ (8005c6c <USB_SetTurnaroundTime+0x124>)
|
|
8005b7e: 4293 cmp r3, r2
|
|
8005b80: d202 bcs.n 8005b88 <USB_SetTurnaroundTime+0x40>
|
|
{
|
|
/* hclk Clock Range between 15-16 MHz */
|
|
UsbTrd = 0xEU;
|
|
8005b82: 230e movs r3, #14
|
|
8005b84: 617b str r3, [r7, #20]
|
|
8005b86: e057 b.n 8005c38 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 16000000U) && (hclk < 17200000U))
|
|
8005b88: 68bb ldr r3, [r7, #8]
|
|
8005b8a: 4a38 ldr r2, [pc, #224] @ (8005c6c <USB_SetTurnaroundTime+0x124>)
|
|
8005b8c: 4293 cmp r3, r2
|
|
8005b8e: d306 bcc.n 8005b9e <USB_SetTurnaroundTime+0x56>
|
|
8005b90: 68bb ldr r3, [r7, #8]
|
|
8005b92: 4a37 ldr r2, [pc, #220] @ (8005c70 <USB_SetTurnaroundTime+0x128>)
|
|
8005b94: 4293 cmp r3, r2
|
|
8005b96: d202 bcs.n 8005b9e <USB_SetTurnaroundTime+0x56>
|
|
{
|
|
/* hclk Clock Range between 16-17.2 MHz */
|
|
UsbTrd = 0xDU;
|
|
8005b98: 230d movs r3, #13
|
|
8005b9a: 617b str r3, [r7, #20]
|
|
8005b9c: e04c b.n 8005c38 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 17200000U) && (hclk < 18500000U))
|
|
8005b9e: 68bb ldr r3, [r7, #8]
|
|
8005ba0: 4a33 ldr r2, [pc, #204] @ (8005c70 <USB_SetTurnaroundTime+0x128>)
|
|
8005ba2: 4293 cmp r3, r2
|
|
8005ba4: d306 bcc.n 8005bb4 <USB_SetTurnaroundTime+0x6c>
|
|
8005ba6: 68bb ldr r3, [r7, #8]
|
|
8005ba8: 4a32 ldr r2, [pc, #200] @ (8005c74 <USB_SetTurnaroundTime+0x12c>)
|
|
8005baa: 4293 cmp r3, r2
|
|
8005bac: d802 bhi.n 8005bb4 <USB_SetTurnaroundTime+0x6c>
|
|
{
|
|
/* hclk Clock Range between 17.2-18.5 MHz */
|
|
UsbTrd = 0xCU;
|
|
8005bae: 230c movs r3, #12
|
|
8005bb0: 617b str r3, [r7, #20]
|
|
8005bb2: e041 b.n 8005c38 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 18500000U) && (hclk < 20000000U))
|
|
8005bb4: 68bb ldr r3, [r7, #8]
|
|
8005bb6: 4a2f ldr r2, [pc, #188] @ (8005c74 <USB_SetTurnaroundTime+0x12c>)
|
|
8005bb8: 4293 cmp r3, r2
|
|
8005bba: d906 bls.n 8005bca <USB_SetTurnaroundTime+0x82>
|
|
8005bbc: 68bb ldr r3, [r7, #8]
|
|
8005bbe: 4a2e ldr r2, [pc, #184] @ (8005c78 <USB_SetTurnaroundTime+0x130>)
|
|
8005bc0: 4293 cmp r3, r2
|
|
8005bc2: d802 bhi.n 8005bca <USB_SetTurnaroundTime+0x82>
|
|
{
|
|
/* hclk Clock Range between 18.5-20 MHz */
|
|
UsbTrd = 0xBU;
|
|
8005bc4: 230b movs r3, #11
|
|
8005bc6: 617b str r3, [r7, #20]
|
|
8005bc8: e036 b.n 8005c38 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 20000000U) && (hclk < 21800000U))
|
|
8005bca: 68bb ldr r3, [r7, #8]
|
|
8005bcc: 4a2a ldr r2, [pc, #168] @ (8005c78 <USB_SetTurnaroundTime+0x130>)
|
|
8005bce: 4293 cmp r3, r2
|
|
8005bd0: d906 bls.n 8005be0 <USB_SetTurnaroundTime+0x98>
|
|
8005bd2: 68bb ldr r3, [r7, #8]
|
|
8005bd4: 4a29 ldr r2, [pc, #164] @ (8005c7c <USB_SetTurnaroundTime+0x134>)
|
|
8005bd6: 4293 cmp r3, r2
|
|
8005bd8: d802 bhi.n 8005be0 <USB_SetTurnaroundTime+0x98>
|
|
{
|
|
/* hclk Clock Range between 20-21.8 MHz */
|
|
UsbTrd = 0xAU;
|
|
8005bda: 230a movs r3, #10
|
|
8005bdc: 617b str r3, [r7, #20]
|
|
8005bde: e02b b.n 8005c38 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 21800000U) && (hclk < 24000000U))
|
|
8005be0: 68bb ldr r3, [r7, #8]
|
|
8005be2: 4a26 ldr r2, [pc, #152] @ (8005c7c <USB_SetTurnaroundTime+0x134>)
|
|
8005be4: 4293 cmp r3, r2
|
|
8005be6: d906 bls.n 8005bf6 <USB_SetTurnaroundTime+0xae>
|
|
8005be8: 68bb ldr r3, [r7, #8]
|
|
8005bea: 4a25 ldr r2, [pc, #148] @ (8005c80 <USB_SetTurnaroundTime+0x138>)
|
|
8005bec: 4293 cmp r3, r2
|
|
8005bee: d202 bcs.n 8005bf6 <USB_SetTurnaroundTime+0xae>
|
|
{
|
|
/* hclk Clock Range between 21.8-24 MHz */
|
|
UsbTrd = 0x9U;
|
|
8005bf0: 2309 movs r3, #9
|
|
8005bf2: 617b str r3, [r7, #20]
|
|
8005bf4: e020 b.n 8005c38 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 24000000U) && (hclk < 27700000U))
|
|
8005bf6: 68bb ldr r3, [r7, #8]
|
|
8005bf8: 4a21 ldr r2, [pc, #132] @ (8005c80 <USB_SetTurnaroundTime+0x138>)
|
|
8005bfa: 4293 cmp r3, r2
|
|
8005bfc: d306 bcc.n 8005c0c <USB_SetTurnaroundTime+0xc4>
|
|
8005bfe: 68bb ldr r3, [r7, #8]
|
|
8005c00: 4a20 ldr r2, [pc, #128] @ (8005c84 <USB_SetTurnaroundTime+0x13c>)
|
|
8005c02: 4293 cmp r3, r2
|
|
8005c04: d802 bhi.n 8005c0c <USB_SetTurnaroundTime+0xc4>
|
|
{
|
|
/* hclk Clock Range between 24-27.7 MHz */
|
|
UsbTrd = 0x8U;
|
|
8005c06: 2308 movs r3, #8
|
|
8005c08: 617b str r3, [r7, #20]
|
|
8005c0a: e015 b.n 8005c38 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 27700000U) && (hclk < 32000000U))
|
|
8005c0c: 68bb ldr r3, [r7, #8]
|
|
8005c0e: 4a1d ldr r2, [pc, #116] @ (8005c84 <USB_SetTurnaroundTime+0x13c>)
|
|
8005c10: 4293 cmp r3, r2
|
|
8005c12: d906 bls.n 8005c22 <USB_SetTurnaroundTime+0xda>
|
|
8005c14: 68bb ldr r3, [r7, #8]
|
|
8005c16: 4a1c ldr r2, [pc, #112] @ (8005c88 <USB_SetTurnaroundTime+0x140>)
|
|
8005c18: 4293 cmp r3, r2
|
|
8005c1a: d202 bcs.n 8005c22 <USB_SetTurnaroundTime+0xda>
|
|
{
|
|
/* hclk Clock Range between 27.7-32 MHz */
|
|
UsbTrd = 0x7U;
|
|
8005c1c: 2307 movs r3, #7
|
|
8005c1e: 617b str r3, [r7, #20]
|
|
8005c20: e00a b.n 8005c38 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else /* if(hclk >= 32000000) */
|
|
{
|
|
/* hclk Clock Range between 32-200 MHz */
|
|
UsbTrd = 0x6U;
|
|
8005c22: 2306 movs r3, #6
|
|
8005c24: 617b str r3, [r7, #20]
|
|
8005c26: e007 b.n 8005c38 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
}
|
|
else if (speed == USBD_HS_SPEED)
|
|
8005c28: 79fb ldrb r3, [r7, #7]
|
|
8005c2a: 2b00 cmp r3, #0
|
|
8005c2c: d102 bne.n 8005c34 <USB_SetTurnaroundTime+0xec>
|
|
{
|
|
UsbTrd = USBD_HS_TRDT_VALUE;
|
|
8005c2e: 2309 movs r3, #9
|
|
8005c30: 617b str r3, [r7, #20]
|
|
8005c32: e001 b.n 8005c38 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else
|
|
{
|
|
UsbTrd = USBD_DEFAULT_TRDT_VALUE;
|
|
8005c34: 2309 movs r3, #9
|
|
8005c36: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
|
|
8005c38: 68fb ldr r3, [r7, #12]
|
|
8005c3a: 68db ldr r3, [r3, #12]
|
|
8005c3c: f423 5270 bic.w r2, r3, #15360 @ 0x3c00
|
|
8005c40: 68fb ldr r3, [r7, #12]
|
|
8005c42: 60da str r2, [r3, #12]
|
|
USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
|
|
8005c44: 68fb ldr r3, [r7, #12]
|
|
8005c46: 68da ldr r2, [r3, #12]
|
|
8005c48: 697b ldr r3, [r7, #20]
|
|
8005c4a: 029b lsls r3, r3, #10
|
|
8005c4c: f403 5370 and.w r3, r3, #15360 @ 0x3c00
|
|
8005c50: 431a orrs r2, r3
|
|
8005c52: 68fb ldr r3, [r7, #12]
|
|
8005c54: 60da str r2, [r3, #12]
|
|
|
|
return HAL_OK;
|
|
8005c56: 2300 movs r3, #0
|
|
}
|
|
8005c58: 4618 mov r0, r3
|
|
8005c5a: 371c adds r7, #28
|
|
8005c5c: 46bd mov sp, r7
|
|
8005c5e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005c62: 4770 bx lr
|
|
8005c64: 00d8acbf .word 0x00d8acbf
|
|
8005c68: 00e4e1c0 .word 0x00e4e1c0
|
|
8005c6c: 00f42400 .word 0x00f42400
|
|
8005c70: 01067380 .word 0x01067380
|
|
8005c74: 011a499f .word 0x011a499f
|
|
8005c78: 01312cff .word 0x01312cff
|
|
8005c7c: 014ca43f .word 0x014ca43f
|
|
8005c80: 016e3600 .word 0x016e3600
|
|
8005c84: 01a6ab1f .word 0x01a6ab1f
|
|
8005c88: 01e84800 .word 0x01e84800
|
|
|
|
08005c8c <USB_EnableGlobalInt>:
|
|
* Enables the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8005c8c: b480 push {r7}
|
|
8005c8e: b083 sub sp, #12
|
|
8005c90: af00 add r7, sp, #0
|
|
8005c92: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
|
|
8005c94: 687b ldr r3, [r7, #4]
|
|
8005c96: 689b ldr r3, [r3, #8]
|
|
8005c98: f043 0201 orr.w r2, r3, #1
|
|
8005c9c: 687b ldr r3, [r7, #4]
|
|
8005c9e: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
8005ca0: 2300 movs r3, #0
|
|
}
|
|
8005ca2: 4618 mov r0, r3
|
|
8005ca4: 370c adds r7, #12
|
|
8005ca6: 46bd mov sp, r7
|
|
8005ca8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005cac: 4770 bx lr
|
|
|
|
08005cae <USB_DisableGlobalInt>:
|
|
* Disable the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8005cae: b480 push {r7}
|
|
8005cb0: b083 sub sp, #12
|
|
8005cb2: af00 add r7, sp, #0
|
|
8005cb4: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
|
|
8005cb6: 687b ldr r3, [r7, #4]
|
|
8005cb8: 689b ldr r3, [r3, #8]
|
|
8005cba: f023 0201 bic.w r2, r3, #1
|
|
8005cbe: 687b ldr r3, [r7, #4]
|
|
8005cc0: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
8005cc2: 2300 movs r3, #0
|
|
}
|
|
8005cc4: 4618 mov r0, r3
|
|
8005cc6: 370c adds r7, #12
|
|
8005cc8: 46bd mov sp, r7
|
|
8005cca: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005cce: 4770 bx lr
|
|
|
|
08005cd0 <USB_SetCurrentMode>:
|
|
* @arg USB_DEVICE_MODE Peripheral mode
|
|
* @arg USB_HOST_MODE Host mode
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
|
|
{
|
|
8005cd0: b580 push {r7, lr}
|
|
8005cd2: b084 sub sp, #16
|
|
8005cd4: af00 add r7, sp, #0
|
|
8005cd6: 6078 str r0, [r7, #4]
|
|
8005cd8: 460b mov r3, r1
|
|
8005cda: 70fb strb r3, [r7, #3]
|
|
uint32_t ms = 0U;
|
|
8005cdc: 2300 movs r3, #0
|
|
8005cde: 60fb str r3, [r7, #12]
|
|
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
|
|
8005ce0: 687b ldr r3, [r7, #4]
|
|
8005ce2: 68db ldr r3, [r3, #12]
|
|
8005ce4: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000
|
|
8005ce8: 687b ldr r3, [r7, #4]
|
|
8005cea: 60da str r2, [r3, #12]
|
|
|
|
if (mode == USB_HOST_MODE)
|
|
8005cec: 78fb ldrb r3, [r7, #3]
|
|
8005cee: 2b01 cmp r3, #1
|
|
8005cf0: d115 bne.n 8005d1e <USB_SetCurrentMode+0x4e>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
|
|
8005cf2: 687b ldr r3, [r7, #4]
|
|
8005cf4: 68db ldr r3, [r3, #12]
|
|
8005cf6: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000
|
|
8005cfa: 687b ldr r3, [r7, #4]
|
|
8005cfc: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
8005cfe: 200a movs r0, #10
|
|
8005d00: f7fb fc18 bl 8001534 <HAL_Delay>
|
|
ms += 10U;
|
|
8005d04: 68fb ldr r3, [r7, #12]
|
|
8005d06: 330a adds r3, #10
|
|
8005d08: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
8005d0a: 6878 ldr r0, [r7, #4]
|
|
8005d0c: f001 f939 bl 8006f82 <USB_GetMode>
|
|
8005d10: 4603 mov r3, r0
|
|
8005d12: 2b01 cmp r3, #1
|
|
8005d14: d01e beq.n 8005d54 <USB_SetCurrentMode+0x84>
|
|
8005d16: 68fb ldr r3, [r7, #12]
|
|
8005d18: 2bc7 cmp r3, #199 @ 0xc7
|
|
8005d1a: d9f0 bls.n 8005cfe <USB_SetCurrentMode+0x2e>
|
|
8005d1c: e01a b.n 8005d54 <USB_SetCurrentMode+0x84>
|
|
}
|
|
else if (mode == USB_DEVICE_MODE)
|
|
8005d1e: 78fb ldrb r3, [r7, #3]
|
|
8005d20: 2b00 cmp r3, #0
|
|
8005d22: d115 bne.n 8005d50 <USB_SetCurrentMode+0x80>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
|
|
8005d24: 687b ldr r3, [r7, #4]
|
|
8005d26: 68db ldr r3, [r3, #12]
|
|
8005d28: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000
|
|
8005d2c: 687b ldr r3, [r7, #4]
|
|
8005d2e: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
8005d30: 200a movs r0, #10
|
|
8005d32: f7fb fbff bl 8001534 <HAL_Delay>
|
|
ms += 10U;
|
|
8005d36: 68fb ldr r3, [r7, #12]
|
|
8005d38: 330a adds r3, #10
|
|
8005d3a: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
8005d3c: 6878 ldr r0, [r7, #4]
|
|
8005d3e: f001 f920 bl 8006f82 <USB_GetMode>
|
|
8005d42: 4603 mov r3, r0
|
|
8005d44: 2b00 cmp r3, #0
|
|
8005d46: d005 beq.n 8005d54 <USB_SetCurrentMode+0x84>
|
|
8005d48: 68fb ldr r3, [r7, #12]
|
|
8005d4a: 2bc7 cmp r3, #199 @ 0xc7
|
|
8005d4c: d9f0 bls.n 8005d30 <USB_SetCurrentMode+0x60>
|
|
8005d4e: e001 b.n 8005d54 <USB_SetCurrentMode+0x84>
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
8005d50: 2301 movs r3, #1
|
|
8005d52: e005 b.n 8005d60 <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
|
|
8005d54: 68fb ldr r3, [r7, #12]
|
|
8005d56: 2bc8 cmp r3, #200 @ 0xc8
|
|
8005d58: d101 bne.n 8005d5e <USB_SetCurrentMode+0x8e>
|
|
{
|
|
return HAL_ERROR;
|
|
8005d5a: 2301 movs r3, #1
|
|
8005d5c: e000 b.n 8005d60 <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8005d5e: 2300 movs r3, #0
|
|
}
|
|
8005d60: 4618 mov r0, r3
|
|
8005d62: 3710 adds r7, #16
|
|
8005d64: 46bd mov sp, r7
|
|
8005d66: bd80 pop {r7, pc}
|
|
|
|
08005d68 <USB_DevInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8005d68: b084 sub sp, #16
|
|
8005d6a: b580 push {r7, lr}
|
|
8005d6c: b086 sub sp, #24
|
|
8005d6e: af00 add r7, sp, #0
|
|
8005d70: 6078 str r0, [r7, #4]
|
|
8005d72: f107 0024 add.w r0, r7, #36 @ 0x24
|
|
8005d76: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8005d7a: 2300 movs r3, #0
|
|
8005d7c: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8005d7e: 687b ldr r3, [r7, #4]
|
|
8005d80: 60fb str r3, [r7, #12]
|
|
uint32_t i;
|
|
|
|
for (i = 0U; i < 15U; i++)
|
|
8005d82: 2300 movs r3, #0
|
|
8005d84: 613b str r3, [r7, #16]
|
|
8005d86: e009 b.n 8005d9c <USB_DevInit+0x34>
|
|
{
|
|
USBx->DIEPTXF[i] = 0U;
|
|
8005d88: 687a ldr r2, [r7, #4]
|
|
8005d8a: 693b ldr r3, [r7, #16]
|
|
8005d8c: 3340 adds r3, #64 @ 0x40
|
|
8005d8e: 009b lsls r3, r3, #2
|
|
8005d90: 4413 add r3, r2
|
|
8005d92: 2200 movs r2, #0
|
|
8005d94: 605a str r2, [r3, #4]
|
|
for (i = 0U; i < 15U; i++)
|
|
8005d96: 693b ldr r3, [r7, #16]
|
|
8005d98: 3301 adds r3, #1
|
|
8005d9a: 613b str r3, [r7, #16]
|
|
8005d9c: 693b ldr r3, [r7, #16]
|
|
8005d9e: 2b0e cmp r3, #14
|
|
8005da0: d9f2 bls.n 8005d88 <USB_DevInit+0x20>
|
|
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* VBUS Sensing setup */
|
|
if (cfg.vbus_sensing_enable == 0U)
|
|
8005da2: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
8005da6: 2b00 cmp r3, #0
|
|
8005da8: d11c bne.n 8005de4 <USB_DevInit+0x7c>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
8005daa: 68fb ldr r3, [r7, #12]
|
|
8005dac: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005db0: 685b ldr r3, [r3, #4]
|
|
8005db2: 68fa ldr r2, [r7, #12]
|
|
8005db4: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8005db8: f043 0302 orr.w r3, r3, #2
|
|
8005dbc: 6053 str r3, [r2, #4]
|
|
|
|
/* Deactivate VBUS Sensing B */
|
|
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
|
|
8005dbe: 687b ldr r3, [r7, #4]
|
|
8005dc0: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005dc2: f423 1200 bic.w r2, r3, #2097152 @ 0x200000
|
|
8005dc6: 687b ldr r3, [r7, #4]
|
|
8005dc8: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* B-peripheral session valid override enable */
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
|
|
8005dca: 687b ldr r3, [r7, #4]
|
|
8005dcc: 681b ldr r3, [r3, #0]
|
|
8005dce: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
8005dd2: 687b ldr r3, [r7, #4]
|
|
8005dd4: 601a str r2, [r3, #0]
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
|
|
8005dd6: 687b ldr r3, [r7, #4]
|
|
8005dd8: 681b ldr r3, [r3, #0]
|
|
8005dda: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
8005dde: 687b ldr r3, [r7, #4]
|
|
8005de0: 601a str r2, [r3, #0]
|
|
8005de2: e005 b.n 8005df0 <USB_DevInit+0x88>
|
|
}
|
|
else
|
|
{
|
|
/* Enable HW VBUS sensing */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
|
|
8005de4: 687b ldr r3, [r7, #4]
|
|
8005de6: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005de8: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
|
|
8005dec: 687b ldr r3, [r7, #4]
|
|
8005dee: 639a str r2, [r3, #56] @ 0x38
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
|
|
/* Restart the Phy Clock */
|
|
USBx_PCGCCTL = 0U;
|
|
8005df0: 68fb ldr r3, [r7, #12]
|
|
8005df2: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
8005df6: 461a mov r2, r3
|
|
8005df8: 2300 movs r3, #0
|
|
8005dfa: 6013 str r3, [r2, #0]
|
|
|
|
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
|
|
8005dfc: f897 3029 ldrb.w r3, [r7, #41] @ 0x29
|
|
8005e00: 2b01 cmp r3, #1
|
|
8005e02: d10d bne.n 8005e20 <USB_DevInit+0xb8>
|
|
{
|
|
if (cfg.speed == USBD_HS_SPEED)
|
|
8005e04: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8005e08: 2b00 cmp r3, #0
|
|
8005e0a: d104 bne.n 8005e16 <USB_DevInit+0xae>
|
|
{
|
|
/* Set Core speed to High speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
|
|
8005e0c: 2100 movs r1, #0
|
|
8005e0e: 6878 ldr r0, [r7, #4]
|
|
8005e10: f000 f968 bl 80060e4 <USB_SetDevSpeed>
|
|
8005e14: e008 b.n 8005e28 <USB_DevInit+0xc0>
|
|
}
|
|
else
|
|
{
|
|
/* Set Core speed to Full speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
|
|
8005e16: 2101 movs r1, #1
|
|
8005e18: 6878 ldr r0, [r7, #4]
|
|
8005e1a: f000 f963 bl 80060e4 <USB_SetDevSpeed>
|
|
8005e1e: e003 b.n 8005e28 <USB_DevInit+0xc0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set Core speed to Full speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
|
|
8005e20: 2103 movs r1, #3
|
|
8005e22: 6878 ldr r0, [r7, #4]
|
|
8005e24: f000 f95e bl 80060e4 <USB_SetDevSpeed>
|
|
}
|
|
|
|
/* Flush the FIFOs */
|
|
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
|
|
8005e28: 2110 movs r1, #16
|
|
8005e2a: 6878 ldr r0, [r7, #4]
|
|
8005e2c: f000 f8fa bl 8006024 <USB_FlushTxFifo>
|
|
8005e30: 4603 mov r3, r0
|
|
8005e32: 2b00 cmp r3, #0
|
|
8005e34: d001 beq.n 8005e3a <USB_DevInit+0xd2>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005e36: 2301 movs r3, #1
|
|
8005e38: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (USB_FlushRxFifo(USBx) != HAL_OK)
|
|
8005e3a: 6878 ldr r0, [r7, #4]
|
|
8005e3c: f000 f924 bl 8006088 <USB_FlushRxFifo>
|
|
8005e40: 4603 mov r3, r0
|
|
8005e42: 2b00 cmp r3, #0
|
|
8005e44: d001 beq.n 8005e4a <USB_DevInit+0xe2>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005e46: 2301 movs r3, #1
|
|
8005e48: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Clear all pending Device Interrupts */
|
|
USBx_DEVICE->DIEPMSK = 0U;
|
|
8005e4a: 68fb ldr r3, [r7, #12]
|
|
8005e4c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005e50: 461a mov r2, r3
|
|
8005e52: 2300 movs r3, #0
|
|
8005e54: 6113 str r3, [r2, #16]
|
|
USBx_DEVICE->DOEPMSK = 0U;
|
|
8005e56: 68fb ldr r3, [r7, #12]
|
|
8005e58: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005e5c: 461a mov r2, r3
|
|
8005e5e: 2300 movs r3, #0
|
|
8005e60: 6153 str r3, [r2, #20]
|
|
USBx_DEVICE->DAINTMSK = 0U;
|
|
8005e62: 68fb ldr r3, [r7, #12]
|
|
8005e64: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005e68: 461a mov r2, r3
|
|
8005e6a: 2300 movs r3, #0
|
|
8005e6c: 61d3 str r3, [r2, #28]
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8005e6e: 2300 movs r3, #0
|
|
8005e70: 613b str r3, [r7, #16]
|
|
8005e72: e043 b.n 8005efc <USB_DevInit+0x194>
|
|
{
|
|
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
8005e74: 693b ldr r3, [r7, #16]
|
|
8005e76: 015a lsls r2, r3, #5
|
|
8005e78: 68fb ldr r3, [r7, #12]
|
|
8005e7a: 4413 add r3, r2
|
|
8005e7c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005e80: 681b ldr r3, [r3, #0]
|
|
8005e82: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8005e86: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8005e8a: d118 bne.n 8005ebe <USB_DevInit+0x156>
|
|
{
|
|
if (i == 0U)
|
|
8005e8c: 693b ldr r3, [r7, #16]
|
|
8005e8e: 2b00 cmp r3, #0
|
|
8005e90: d10a bne.n 8005ea8 <USB_DevInit+0x140>
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
|
|
8005e92: 693b ldr r3, [r7, #16]
|
|
8005e94: 015a lsls r2, r3, #5
|
|
8005e96: 68fb ldr r3, [r7, #12]
|
|
8005e98: 4413 add r3, r2
|
|
8005e9a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005e9e: 461a mov r2, r3
|
|
8005ea0: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
8005ea4: 6013 str r3, [r2, #0]
|
|
8005ea6: e013 b.n 8005ed0 <USB_DevInit+0x168>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
|
|
8005ea8: 693b ldr r3, [r7, #16]
|
|
8005eaa: 015a lsls r2, r3, #5
|
|
8005eac: 68fb ldr r3, [r7, #12]
|
|
8005eae: 4413 add r3, r2
|
|
8005eb0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005eb4: 461a mov r2, r3
|
|
8005eb6: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
8005eba: 6013 str r3, [r2, #0]
|
|
8005ebc: e008 b.n 8005ed0 <USB_DevInit+0x168>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = 0U;
|
|
8005ebe: 693b ldr r3, [r7, #16]
|
|
8005ec0: 015a lsls r2, r3, #5
|
|
8005ec2: 68fb ldr r3, [r7, #12]
|
|
8005ec4: 4413 add r3, r2
|
|
8005ec6: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005eca: 461a mov r2, r3
|
|
8005ecc: 2300 movs r3, #0
|
|
8005ece: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_INEP(i)->DIEPTSIZ = 0U;
|
|
8005ed0: 693b ldr r3, [r7, #16]
|
|
8005ed2: 015a lsls r2, r3, #5
|
|
8005ed4: 68fb ldr r3, [r7, #12]
|
|
8005ed6: 4413 add r3, r2
|
|
8005ed8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005edc: 461a mov r2, r3
|
|
8005ede: 2300 movs r3, #0
|
|
8005ee0: 6113 str r3, [r2, #16]
|
|
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
|
8005ee2: 693b ldr r3, [r7, #16]
|
|
8005ee4: 015a lsls r2, r3, #5
|
|
8005ee6: 68fb ldr r3, [r7, #12]
|
|
8005ee8: 4413 add r3, r2
|
|
8005eea: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005eee: 461a mov r2, r3
|
|
8005ef0: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
8005ef4: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8005ef6: 693b ldr r3, [r7, #16]
|
|
8005ef8: 3301 adds r3, #1
|
|
8005efa: 613b str r3, [r7, #16]
|
|
8005efc: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
8005f00: 461a mov r2, r3
|
|
8005f02: 693b ldr r3, [r7, #16]
|
|
8005f04: 4293 cmp r3, r2
|
|
8005f06: d3b5 bcc.n 8005e74 <USB_DevInit+0x10c>
|
|
}
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8005f08: 2300 movs r3, #0
|
|
8005f0a: 613b str r3, [r7, #16]
|
|
8005f0c: e043 b.n 8005f96 <USB_DevInit+0x22e>
|
|
{
|
|
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
8005f0e: 693b ldr r3, [r7, #16]
|
|
8005f10: 015a lsls r2, r3, #5
|
|
8005f12: 68fb ldr r3, [r7, #12]
|
|
8005f14: 4413 add r3, r2
|
|
8005f16: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005f1a: 681b ldr r3, [r3, #0]
|
|
8005f1c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8005f20: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8005f24: d118 bne.n 8005f58 <USB_DevInit+0x1f0>
|
|
{
|
|
if (i == 0U)
|
|
8005f26: 693b ldr r3, [r7, #16]
|
|
8005f28: 2b00 cmp r3, #0
|
|
8005f2a: d10a bne.n 8005f42 <USB_DevInit+0x1da>
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
|
|
8005f2c: 693b ldr r3, [r7, #16]
|
|
8005f2e: 015a lsls r2, r3, #5
|
|
8005f30: 68fb ldr r3, [r7, #12]
|
|
8005f32: 4413 add r3, r2
|
|
8005f34: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005f38: 461a mov r2, r3
|
|
8005f3a: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
8005f3e: 6013 str r3, [r2, #0]
|
|
8005f40: e013 b.n 8005f6a <USB_DevInit+0x202>
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
|
|
8005f42: 693b ldr r3, [r7, #16]
|
|
8005f44: 015a lsls r2, r3, #5
|
|
8005f46: 68fb ldr r3, [r7, #12]
|
|
8005f48: 4413 add r3, r2
|
|
8005f4a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005f4e: 461a mov r2, r3
|
|
8005f50: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
8005f54: 6013 str r3, [r2, #0]
|
|
8005f56: e008 b.n 8005f6a <USB_DevInit+0x202>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = 0U;
|
|
8005f58: 693b ldr r3, [r7, #16]
|
|
8005f5a: 015a lsls r2, r3, #5
|
|
8005f5c: 68fb ldr r3, [r7, #12]
|
|
8005f5e: 4413 add r3, r2
|
|
8005f60: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005f64: 461a mov r2, r3
|
|
8005f66: 2300 movs r3, #0
|
|
8005f68: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_OUTEP(i)->DOEPTSIZ = 0U;
|
|
8005f6a: 693b ldr r3, [r7, #16]
|
|
8005f6c: 015a lsls r2, r3, #5
|
|
8005f6e: 68fb ldr r3, [r7, #12]
|
|
8005f70: 4413 add r3, r2
|
|
8005f72: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005f76: 461a mov r2, r3
|
|
8005f78: 2300 movs r3, #0
|
|
8005f7a: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
|
8005f7c: 693b ldr r3, [r7, #16]
|
|
8005f7e: 015a lsls r2, r3, #5
|
|
8005f80: 68fb ldr r3, [r7, #12]
|
|
8005f82: 4413 add r3, r2
|
|
8005f84: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005f88: 461a mov r2, r3
|
|
8005f8a: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
8005f8e: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8005f90: 693b ldr r3, [r7, #16]
|
|
8005f92: 3301 adds r3, #1
|
|
8005f94: 613b str r3, [r7, #16]
|
|
8005f96: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
8005f9a: 461a mov r2, r3
|
|
8005f9c: 693b ldr r3, [r7, #16]
|
|
8005f9e: 4293 cmp r3, r2
|
|
8005fa0: d3b5 bcc.n 8005f0e <USB_DevInit+0x1a6>
|
|
}
|
|
|
|
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
|
|
8005fa2: 68fb ldr r3, [r7, #12]
|
|
8005fa4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005fa8: 691b ldr r3, [r3, #16]
|
|
8005faa: 68fa ldr r2, [r7, #12]
|
|
8005fac: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8005fb0: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8005fb4: 6113 str r3, [r2, #16]
|
|
|
|
/* Disable all interrupts. */
|
|
USBx->GINTMSK = 0U;
|
|
8005fb6: 687b ldr r3, [r7, #4]
|
|
8005fb8: 2200 movs r2, #0
|
|
8005fba: 619a str r2, [r3, #24]
|
|
|
|
/* Clear any pending interrupts */
|
|
USBx->GINTSTS = 0xBFFFFFFFU;
|
|
8005fbc: 687b ldr r3, [r7, #4]
|
|
8005fbe: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000
|
|
8005fc2: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the common interrupts */
|
|
if (cfg.dma_enable == 0U)
|
|
8005fc4: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
|
|
8005fc8: 2b00 cmp r3, #0
|
|
8005fca: d105 bne.n 8005fd8 <USB_DevInit+0x270>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
|
|
8005fcc: 687b ldr r3, [r7, #4]
|
|
8005fce: 699b ldr r3, [r3, #24]
|
|
8005fd0: f043 0210 orr.w r2, r3, #16
|
|
8005fd4: 687b ldr r3, [r7, #4]
|
|
8005fd6: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
/* Enable interrupts matching to the Device mode ONLY */
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
|
|
8005fd8: 687b ldr r3, [r7, #4]
|
|
8005fda: 699a ldr r2, [r3, #24]
|
|
8005fdc: 4b10 ldr r3, [pc, #64] @ (8006020 <USB_DevInit+0x2b8>)
|
|
8005fde: 4313 orrs r3, r2
|
|
8005fe0: 687a ldr r2, [r7, #4]
|
|
8005fe2: 6193 str r3, [r2, #24]
|
|
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
|
|
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
|
|
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
|
|
|
|
if (cfg.Sof_enable != 0U)
|
|
8005fe4: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
8005fe8: 2b00 cmp r3, #0
|
|
8005fea: d005 beq.n 8005ff8 <USB_DevInit+0x290>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
|
|
8005fec: 687b ldr r3, [r7, #4]
|
|
8005fee: 699b ldr r3, [r3, #24]
|
|
8005ff0: f043 0208 orr.w r2, r3, #8
|
|
8005ff4: 687b ldr r3, [r7, #4]
|
|
8005ff6: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (cfg.vbus_sensing_enable == 1U)
|
|
8005ff8: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
8005ffc: 2b01 cmp r3, #1
|
|
8005ffe: d107 bne.n 8006010 <USB_DevInit+0x2a8>
|
|
{
|
|
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
|
|
8006000: 687b ldr r3, [r7, #4]
|
|
8006002: 699b ldr r3, [r3, #24]
|
|
8006004: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8006008: f043 0304 orr.w r3, r3, #4
|
|
800600c: 687a ldr r2, [r7, #4]
|
|
800600e: 6193 str r3, [r2, #24]
|
|
}
|
|
|
|
return ret;
|
|
8006010: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8006012: 4618 mov r0, r3
|
|
8006014: 3718 adds r7, #24
|
|
8006016: 46bd mov sp, r7
|
|
8006018: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
800601c: b004 add sp, #16
|
|
800601e: 4770 bx lr
|
|
8006020: 803c3800 .word 0x803c3800
|
|
|
|
08006024 <USB_FlushTxFifo>:
|
|
* This parameter can be a value from 1 to 15
|
|
15 means Flush all Tx FIFOs
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
|
|
{
|
|
8006024: b480 push {r7}
|
|
8006026: b085 sub sp, #20
|
|
8006028: af00 add r7, sp, #0
|
|
800602a: 6078 str r0, [r7, #4]
|
|
800602c: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
800602e: 2300 movs r3, #0
|
|
8006030: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
8006032: 68fb ldr r3, [r7, #12]
|
|
8006034: 3301 adds r3, #1
|
|
8006036: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8006038: 68fb ldr r3, [r7, #12]
|
|
800603a: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800603e: d901 bls.n 8006044 <USB_FlushTxFifo+0x20>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8006040: 2303 movs r3, #3
|
|
8006042: e01b b.n 800607c <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
8006044: 687b ldr r3, [r7, #4]
|
|
8006046: 691b ldr r3, [r3, #16]
|
|
8006048: 2b00 cmp r3, #0
|
|
800604a: daf2 bge.n 8006032 <USB_FlushTxFifo+0xe>
|
|
|
|
/* Flush TX Fifo */
|
|
count = 0U;
|
|
800604c: 2300 movs r3, #0
|
|
800604e: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
|
|
8006050: 683b ldr r3, [r7, #0]
|
|
8006052: 019b lsls r3, r3, #6
|
|
8006054: f043 0220 orr.w r2, r3, #32
|
|
8006058: 687b ldr r3, [r7, #4]
|
|
800605a: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
800605c: 68fb ldr r3, [r7, #12]
|
|
800605e: 3301 adds r3, #1
|
|
8006060: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8006062: 68fb ldr r3, [r7, #12]
|
|
8006064: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8006068: d901 bls.n 800606e <USB_FlushTxFifo+0x4a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800606a: 2303 movs r3, #3
|
|
800606c: e006 b.n 800607c <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
|
|
800606e: 687b ldr r3, [r7, #4]
|
|
8006070: 691b ldr r3, [r3, #16]
|
|
8006072: f003 0320 and.w r3, r3, #32
|
|
8006076: 2b20 cmp r3, #32
|
|
8006078: d0f0 beq.n 800605c <USB_FlushTxFifo+0x38>
|
|
|
|
return HAL_OK;
|
|
800607a: 2300 movs r3, #0
|
|
}
|
|
800607c: 4618 mov r0, r3
|
|
800607e: 3714 adds r7, #20
|
|
8006080: 46bd mov sp, r7
|
|
8006082: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006086: 4770 bx lr
|
|
|
|
08006088 <USB_FlushRxFifo>:
|
|
* @brief USB_FlushRxFifo Flush Rx FIFO
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006088: b480 push {r7}
|
|
800608a: b085 sub sp, #20
|
|
800608c: af00 add r7, sp, #0
|
|
800608e: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
8006090: 2300 movs r3, #0
|
|
8006092: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
8006094: 68fb ldr r3, [r7, #12]
|
|
8006096: 3301 adds r3, #1
|
|
8006098: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800609a: 68fb ldr r3, [r7, #12]
|
|
800609c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80060a0: d901 bls.n 80060a6 <USB_FlushRxFifo+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80060a2: 2303 movs r3, #3
|
|
80060a4: e018 b.n 80060d8 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
80060a6: 687b ldr r3, [r7, #4]
|
|
80060a8: 691b ldr r3, [r3, #16]
|
|
80060aa: 2b00 cmp r3, #0
|
|
80060ac: daf2 bge.n 8006094 <USB_FlushRxFifo+0xc>
|
|
|
|
/* Flush RX Fifo */
|
|
count = 0U;
|
|
80060ae: 2300 movs r3, #0
|
|
80060b0: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
|
|
80060b2: 687b ldr r3, [r7, #4]
|
|
80060b4: 2210 movs r2, #16
|
|
80060b6: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
80060b8: 68fb ldr r3, [r7, #12]
|
|
80060ba: 3301 adds r3, #1
|
|
80060bc: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80060be: 68fb ldr r3, [r7, #12]
|
|
80060c0: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80060c4: d901 bls.n 80060ca <USB_FlushRxFifo+0x42>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80060c6: 2303 movs r3, #3
|
|
80060c8: e006 b.n 80060d8 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
|
|
80060ca: 687b ldr r3, [r7, #4]
|
|
80060cc: 691b ldr r3, [r3, #16]
|
|
80060ce: f003 0310 and.w r3, r3, #16
|
|
80060d2: 2b10 cmp r3, #16
|
|
80060d4: d0f0 beq.n 80060b8 <USB_FlushRxFifo+0x30>
|
|
|
|
return HAL_OK;
|
|
80060d6: 2300 movs r3, #0
|
|
}
|
|
80060d8: 4618 mov r0, r3
|
|
80060da: 3714 adds r7, #20
|
|
80060dc: 46bd mov sp, r7
|
|
80060de: f85d 7b04 ldr.w r7, [sp], #4
|
|
80060e2: 4770 bx lr
|
|
|
|
080060e4 <USB_SetDevSpeed>:
|
|
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
|
|
* @arg USB_OTG_SPEED_FULL: Full speed mode
|
|
* @retval Hal status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
|
|
{
|
|
80060e4: b480 push {r7}
|
|
80060e6: b085 sub sp, #20
|
|
80060e8: af00 add r7, sp, #0
|
|
80060ea: 6078 str r0, [r7, #4]
|
|
80060ec: 460b mov r3, r1
|
|
80060ee: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80060f0: 687b ldr r3, [r7, #4]
|
|
80060f2: 60fb str r3, [r7, #12]
|
|
|
|
USBx_DEVICE->DCFG |= speed;
|
|
80060f4: 68fb ldr r3, [r7, #12]
|
|
80060f6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80060fa: 681a ldr r2, [r3, #0]
|
|
80060fc: 78fb ldrb r3, [r7, #3]
|
|
80060fe: 68f9 ldr r1, [r7, #12]
|
|
8006100: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8006104: 4313 orrs r3, r2
|
|
8006106: 600b str r3, [r1, #0]
|
|
return HAL_OK;
|
|
8006108: 2300 movs r3, #0
|
|
}
|
|
800610a: 4618 mov r0, r3
|
|
800610c: 3714 adds r7, #20
|
|
800610e: 46bd mov sp, r7
|
|
8006110: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006114: 4770 bx lr
|
|
|
|
08006116 <USB_GetDevSpeed>:
|
|
* This parameter can be one of these values:
|
|
* @arg USBD_HS_SPEED: High speed mode
|
|
* @arg USBD_FS_SPEED: Full speed mode
|
|
*/
|
|
uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006116: b480 push {r7}
|
|
8006118: b087 sub sp, #28
|
|
800611a: af00 add r7, sp, #0
|
|
800611c: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800611e: 687b ldr r3, [r7, #4]
|
|
8006120: 613b str r3, [r7, #16]
|
|
uint8_t speed;
|
|
uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
|
|
8006122: 693b ldr r3, [r7, #16]
|
|
8006124: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006128: 689b ldr r3, [r3, #8]
|
|
800612a: f003 0306 and.w r3, r3, #6
|
|
800612e: 60fb str r3, [r7, #12]
|
|
|
|
if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
|
|
8006130: 68fb ldr r3, [r7, #12]
|
|
8006132: 2b00 cmp r3, #0
|
|
8006134: d102 bne.n 800613c <USB_GetDevSpeed+0x26>
|
|
{
|
|
speed = USBD_HS_SPEED;
|
|
8006136: 2300 movs r3, #0
|
|
8006138: 75fb strb r3, [r7, #23]
|
|
800613a: e00a b.n 8006152 <USB_GetDevSpeed+0x3c>
|
|
}
|
|
else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
|
|
800613c: 68fb ldr r3, [r7, #12]
|
|
800613e: 2b02 cmp r3, #2
|
|
8006140: d002 beq.n 8006148 <USB_GetDevSpeed+0x32>
|
|
8006142: 68fb ldr r3, [r7, #12]
|
|
8006144: 2b06 cmp r3, #6
|
|
8006146: d102 bne.n 800614e <USB_GetDevSpeed+0x38>
|
|
(DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
|
|
{
|
|
speed = USBD_FS_SPEED;
|
|
8006148: 2302 movs r3, #2
|
|
800614a: 75fb strb r3, [r7, #23]
|
|
800614c: e001 b.n 8006152 <USB_GetDevSpeed+0x3c>
|
|
}
|
|
else
|
|
{
|
|
speed = 0xFU;
|
|
800614e: 230f movs r3, #15
|
|
8006150: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return speed;
|
|
8006152: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8006154: 4618 mov r0, r3
|
|
8006156: 371c adds r7, #28
|
|
8006158: 46bd mov sp, r7
|
|
800615a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800615e: 4770 bx lr
|
|
|
|
08006160 <USB_ActivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8006160: b480 push {r7}
|
|
8006162: b085 sub sp, #20
|
|
8006164: af00 add r7, sp, #0
|
|
8006166: 6078 str r0, [r7, #4]
|
|
8006168: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800616a: 687b ldr r3, [r7, #4]
|
|
800616c: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
800616e: 683b ldr r3, [r7, #0]
|
|
8006170: 781b ldrb r3, [r3, #0]
|
|
8006172: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
8006174: 683b ldr r3, [r7, #0]
|
|
8006176: 785b ldrb r3, [r3, #1]
|
|
8006178: 2b01 cmp r3, #1
|
|
800617a: d13a bne.n 80061f2 <USB_ActivateEndpoint+0x92>
|
|
{
|
|
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
|
|
800617c: 68fb ldr r3, [r7, #12]
|
|
800617e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006182: 69da ldr r2, [r3, #28]
|
|
8006184: 683b ldr r3, [r7, #0]
|
|
8006186: 781b ldrb r3, [r3, #0]
|
|
8006188: f003 030f and.w r3, r3, #15
|
|
800618c: 2101 movs r1, #1
|
|
800618e: fa01 f303 lsl.w r3, r1, r3
|
|
8006192: b29b uxth r3, r3
|
|
8006194: 68f9 ldr r1, [r7, #12]
|
|
8006196: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
800619a: 4313 orrs r3, r2
|
|
800619c: 61cb str r3, [r1, #28]
|
|
|
|
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
|
|
800619e: 68bb ldr r3, [r7, #8]
|
|
80061a0: 015a lsls r2, r3, #5
|
|
80061a2: 68fb ldr r3, [r7, #12]
|
|
80061a4: 4413 add r3, r2
|
|
80061a6: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80061aa: 681b ldr r3, [r3, #0]
|
|
80061ac: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80061b0: 2b00 cmp r3, #0
|
|
80061b2: d155 bne.n 8006260 <USB_ActivateEndpoint+0x100>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
80061b4: 68bb ldr r3, [r7, #8]
|
|
80061b6: 015a lsls r2, r3, #5
|
|
80061b8: 68fb ldr r3, [r7, #12]
|
|
80061ba: 4413 add r3, r2
|
|
80061bc: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80061c0: 681a ldr r2, [r3, #0]
|
|
80061c2: 683b ldr r3, [r7, #0]
|
|
80061c4: 689b ldr r3, [r3, #8]
|
|
80061c6: f3c3 010a ubfx r1, r3, #0, #11
|
|
((uint32_t)ep->type << 18) | (epnum << 22) |
|
|
80061ca: 683b ldr r3, [r7, #0]
|
|
80061cc: 791b ldrb r3, [r3, #4]
|
|
80061ce: 049b lsls r3, r3, #18
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
80061d0: 4319 orrs r1, r3
|
|
((uint32_t)ep->type << 18) | (epnum << 22) |
|
|
80061d2: 68bb ldr r3, [r7, #8]
|
|
80061d4: 059b lsls r3, r3, #22
|
|
80061d6: 430b orrs r3, r1
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
80061d8: 4313 orrs r3, r2
|
|
80061da: 68ba ldr r2, [r7, #8]
|
|
80061dc: 0151 lsls r1, r2, #5
|
|
80061de: 68fa ldr r2, [r7, #12]
|
|
80061e0: 440a add r2, r1
|
|
80061e2: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80061e6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80061ea: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80061ee: 6013 str r3, [r2, #0]
|
|
80061f0: e036 b.n 8006260 <USB_ActivateEndpoint+0x100>
|
|
USB_OTG_DIEPCTL_USBAEP;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
|
|
80061f2: 68fb ldr r3, [r7, #12]
|
|
80061f4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80061f8: 69da ldr r2, [r3, #28]
|
|
80061fa: 683b ldr r3, [r7, #0]
|
|
80061fc: 781b ldrb r3, [r3, #0]
|
|
80061fe: f003 030f and.w r3, r3, #15
|
|
8006202: 2101 movs r1, #1
|
|
8006204: fa01 f303 lsl.w r3, r1, r3
|
|
8006208: 041b lsls r3, r3, #16
|
|
800620a: 68f9 ldr r1, [r7, #12]
|
|
800620c: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8006210: 4313 orrs r3, r2
|
|
8006212: 61cb str r3, [r1, #28]
|
|
|
|
if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
|
|
8006214: 68bb ldr r3, [r7, #8]
|
|
8006216: 015a lsls r2, r3, #5
|
|
8006218: 68fb ldr r3, [r7, #12]
|
|
800621a: 4413 add r3, r2
|
|
800621c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006220: 681b ldr r3, [r3, #0]
|
|
8006222: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8006226: 2b00 cmp r3, #0
|
|
8006228: d11a bne.n 8006260 <USB_ActivateEndpoint+0x100>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
|
|
800622a: 68bb ldr r3, [r7, #8]
|
|
800622c: 015a lsls r2, r3, #5
|
|
800622e: 68fb ldr r3, [r7, #12]
|
|
8006230: 4413 add r3, r2
|
|
8006232: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006236: 681a ldr r2, [r3, #0]
|
|
8006238: 683b ldr r3, [r7, #0]
|
|
800623a: 689b ldr r3, [r3, #8]
|
|
800623c: f3c3 010a ubfx r1, r3, #0, #11
|
|
((uint32_t)ep->type << 18) |
|
|
8006240: 683b ldr r3, [r7, #0]
|
|
8006242: 791b ldrb r3, [r3, #4]
|
|
8006244: 049b lsls r3, r3, #18
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
|
|
8006246: 430b orrs r3, r1
|
|
8006248: 4313 orrs r3, r2
|
|
800624a: 68ba ldr r2, [r7, #8]
|
|
800624c: 0151 lsls r1, r2, #5
|
|
800624e: 68fa ldr r2, [r7, #12]
|
|
8006250: 440a add r2, r1
|
|
8006252: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006256: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800625a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800625e: 6013 str r3, [r2, #0]
|
|
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DOEPCTL_USBAEP;
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8006260: 2300 movs r3, #0
|
|
}
|
|
8006262: 4618 mov r0, r3
|
|
8006264: 3714 adds r7, #20
|
|
8006266: 46bd mov sp, r7
|
|
8006268: f85d 7b04 ldr.w r7, [sp], #4
|
|
800626c: 4770 bx lr
|
|
...
|
|
|
|
08006270 <USB_DeactivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8006270: b480 push {r7}
|
|
8006272: b085 sub sp, #20
|
|
8006274: af00 add r7, sp, #0
|
|
8006276: 6078 str r0, [r7, #4]
|
|
8006278: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800627a: 687b ldr r3, [r7, #4]
|
|
800627c: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
800627e: 683b ldr r3, [r7, #0]
|
|
8006280: 781b ldrb r3, [r3, #0]
|
|
8006282: 60bb str r3, [r7, #8]
|
|
|
|
/* Read DEPCTLn register */
|
|
if (ep->is_in == 1U)
|
|
8006284: 683b ldr r3, [r7, #0]
|
|
8006286: 785b ldrb r3, [r3, #1]
|
|
8006288: 2b01 cmp r3, #1
|
|
800628a: d161 bne.n 8006350 <USB_DeactivateEndpoint+0xe0>
|
|
{
|
|
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
800628c: 68bb ldr r3, [r7, #8]
|
|
800628e: 015a lsls r2, r3, #5
|
|
8006290: 68fb ldr r3, [r7, #12]
|
|
8006292: 4413 add r3, r2
|
|
8006294: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006298: 681b ldr r3, [r3, #0]
|
|
800629a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
800629e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80062a2: d11f bne.n 80062e4 <USB_DeactivateEndpoint+0x74>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
|
|
80062a4: 68bb ldr r3, [r7, #8]
|
|
80062a6: 015a lsls r2, r3, #5
|
|
80062a8: 68fb ldr r3, [r7, #12]
|
|
80062aa: 4413 add r3, r2
|
|
80062ac: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80062b0: 681b ldr r3, [r3, #0]
|
|
80062b2: 68ba ldr r2, [r7, #8]
|
|
80062b4: 0151 lsls r1, r2, #5
|
|
80062b6: 68fa ldr r2, [r7, #12]
|
|
80062b8: 440a add r2, r1
|
|
80062ba: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80062be: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
80062c2: 6013 str r3, [r2, #0]
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
|
|
80062c4: 68bb ldr r3, [r7, #8]
|
|
80062c6: 015a lsls r2, r3, #5
|
|
80062c8: 68fb ldr r3, [r7, #12]
|
|
80062ca: 4413 add r3, r2
|
|
80062cc: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80062d0: 681b ldr r3, [r3, #0]
|
|
80062d2: 68ba ldr r2, [r7, #8]
|
|
80062d4: 0151 lsls r1, r2, #5
|
|
80062d6: 68fa ldr r2, [r7, #12]
|
|
80062d8: 440a add r2, r1
|
|
80062da: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80062de: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80062e2: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
|
|
80062e4: 68fb ldr r3, [r7, #12]
|
|
80062e6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80062ea: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
80062ec: 683b ldr r3, [r7, #0]
|
|
80062ee: 781b ldrb r3, [r3, #0]
|
|
80062f0: f003 030f and.w r3, r3, #15
|
|
80062f4: 2101 movs r1, #1
|
|
80062f6: fa01 f303 lsl.w r3, r1, r3
|
|
80062fa: b29b uxth r3, r3
|
|
80062fc: 43db mvns r3, r3
|
|
80062fe: 68f9 ldr r1, [r7, #12]
|
|
8006300: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8006304: 4013 ands r3, r2
|
|
8006306: 63cb str r3, [r1, #60] @ 0x3c
|
|
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
|
|
8006308: 68fb ldr r3, [r7, #12]
|
|
800630a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800630e: 69da ldr r2, [r3, #28]
|
|
8006310: 683b ldr r3, [r7, #0]
|
|
8006312: 781b ldrb r3, [r3, #0]
|
|
8006314: f003 030f and.w r3, r3, #15
|
|
8006318: 2101 movs r1, #1
|
|
800631a: fa01 f303 lsl.w r3, r1, r3
|
|
800631e: b29b uxth r3, r3
|
|
8006320: 43db mvns r3, r3
|
|
8006322: 68f9 ldr r1, [r7, #12]
|
|
8006324: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8006328: 4013 ands r3, r2
|
|
800632a: 61cb str r3, [r1, #28]
|
|
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
|
|
800632c: 68bb ldr r3, [r7, #8]
|
|
800632e: 015a lsls r2, r3, #5
|
|
8006330: 68fb ldr r3, [r7, #12]
|
|
8006332: 4413 add r3, r2
|
|
8006334: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006338: 681a ldr r2, [r3, #0]
|
|
800633a: 68bb ldr r3, [r7, #8]
|
|
800633c: 0159 lsls r1, r3, #5
|
|
800633e: 68fb ldr r3, [r7, #12]
|
|
8006340: 440b add r3, r1
|
|
8006342: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006346: 4619 mov r1, r3
|
|
8006348: 4b35 ldr r3, [pc, #212] @ (8006420 <USB_DeactivateEndpoint+0x1b0>)
|
|
800634a: 4013 ands r3, r2
|
|
800634c: 600b str r3, [r1, #0]
|
|
800634e: e060 b.n 8006412 <USB_DeactivateEndpoint+0x1a2>
|
|
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DIEPCTL_EPTYP);
|
|
}
|
|
else
|
|
{
|
|
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
8006350: 68bb ldr r3, [r7, #8]
|
|
8006352: 015a lsls r2, r3, #5
|
|
8006354: 68fb ldr r3, [r7, #12]
|
|
8006356: 4413 add r3, r2
|
|
8006358: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800635c: 681b ldr r3, [r3, #0]
|
|
800635e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006362: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8006366: d11f bne.n 80063a8 <USB_DeactivateEndpoint+0x138>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
|
8006368: 68bb ldr r3, [r7, #8]
|
|
800636a: 015a lsls r2, r3, #5
|
|
800636c: 68fb ldr r3, [r7, #12]
|
|
800636e: 4413 add r3, r2
|
|
8006370: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006374: 681b ldr r3, [r3, #0]
|
|
8006376: 68ba ldr r2, [r7, #8]
|
|
8006378: 0151 lsls r1, r2, #5
|
|
800637a: 68fa ldr r2, [r7, #12]
|
|
800637c: 440a add r2, r1
|
|
800637e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006382: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8006386: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
|
|
8006388: 68bb ldr r3, [r7, #8]
|
|
800638a: 015a lsls r2, r3, #5
|
|
800638c: 68fb ldr r3, [r7, #12]
|
|
800638e: 4413 add r3, r2
|
|
8006390: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006394: 681b ldr r3, [r3, #0]
|
|
8006396: 68ba ldr r2, [r7, #8]
|
|
8006398: 0151 lsls r1, r2, #5
|
|
800639a: 68fa ldr r2, [r7, #12]
|
|
800639c: 440a add r2, r1
|
|
800639e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
80063a2: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80063a6: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
|
|
80063a8: 68fb ldr r3, [r7, #12]
|
|
80063aa: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80063ae: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
80063b0: 683b ldr r3, [r7, #0]
|
|
80063b2: 781b ldrb r3, [r3, #0]
|
|
80063b4: f003 030f and.w r3, r3, #15
|
|
80063b8: 2101 movs r1, #1
|
|
80063ba: fa01 f303 lsl.w r3, r1, r3
|
|
80063be: 041b lsls r3, r3, #16
|
|
80063c0: 43db mvns r3, r3
|
|
80063c2: 68f9 ldr r1, [r7, #12]
|
|
80063c4: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80063c8: 4013 ands r3, r2
|
|
80063ca: 63cb str r3, [r1, #60] @ 0x3c
|
|
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
|
|
80063cc: 68fb ldr r3, [r7, #12]
|
|
80063ce: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80063d2: 69da ldr r2, [r3, #28]
|
|
80063d4: 683b ldr r3, [r7, #0]
|
|
80063d6: 781b ldrb r3, [r3, #0]
|
|
80063d8: f003 030f and.w r3, r3, #15
|
|
80063dc: 2101 movs r1, #1
|
|
80063de: fa01 f303 lsl.w r3, r1, r3
|
|
80063e2: 041b lsls r3, r3, #16
|
|
80063e4: 43db mvns r3, r3
|
|
80063e6: 68f9 ldr r1, [r7, #12]
|
|
80063e8: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80063ec: 4013 ands r3, r2
|
|
80063ee: 61cb str r3, [r1, #28]
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
|
|
80063f0: 68bb ldr r3, [r7, #8]
|
|
80063f2: 015a lsls r2, r3, #5
|
|
80063f4: 68fb ldr r3, [r7, #12]
|
|
80063f6: 4413 add r3, r2
|
|
80063f8: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80063fc: 681a ldr r2, [r3, #0]
|
|
80063fe: 68bb ldr r3, [r7, #8]
|
|
8006400: 0159 lsls r1, r3, #5
|
|
8006402: 68fb ldr r3, [r7, #12]
|
|
8006404: 440b add r3, r1
|
|
8006406: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800640a: 4619 mov r1, r3
|
|
800640c: 4b05 ldr r3, [pc, #20] @ (8006424 <USB_DeactivateEndpoint+0x1b4>)
|
|
800640e: 4013 ands r3, r2
|
|
8006410: 600b str r3, [r1, #0]
|
|
USB_OTG_DOEPCTL_MPSIZ |
|
|
USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DOEPCTL_EPTYP);
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006412: 2300 movs r3, #0
|
|
}
|
|
8006414: 4618 mov r0, r3
|
|
8006416: 3714 adds r7, #20
|
|
8006418: 46bd mov sp, r7
|
|
800641a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800641e: 4770 bx lr
|
|
8006420: ec337800 .word 0xec337800
|
|
8006424: eff37800 .word 0xeff37800
|
|
|
|
08006428 <USB_EPStartXfer>:
|
|
* 0 : DMA feature not used
|
|
* 1 : DMA feature used
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
|
|
{
|
|
8006428: b580 push {r7, lr}
|
|
800642a: b08a sub sp, #40 @ 0x28
|
|
800642c: af02 add r7, sp, #8
|
|
800642e: 60f8 str r0, [r7, #12]
|
|
8006430: 60b9 str r1, [r7, #8]
|
|
8006432: 4613 mov r3, r2
|
|
8006434: 71fb strb r3, [r7, #7]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006436: 68fb ldr r3, [r7, #12]
|
|
8006438: 61fb str r3, [r7, #28]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
800643a: 68bb ldr r3, [r7, #8]
|
|
800643c: 781b ldrb r3, [r3, #0]
|
|
800643e: 61bb str r3, [r7, #24]
|
|
uint16_t pktcnt;
|
|
|
|
/* IN endpoint */
|
|
if (ep->is_in == 1U)
|
|
8006440: 68bb ldr r3, [r7, #8]
|
|
8006442: 785b ldrb r3, [r3, #1]
|
|
8006444: 2b01 cmp r3, #1
|
|
8006446: f040 817f bne.w 8006748 <USB_EPStartXfer+0x320>
|
|
{
|
|
/* Zero Length Packet? */
|
|
if (ep->xfer_len == 0U)
|
|
800644a: 68bb ldr r3, [r7, #8]
|
|
800644c: 691b ldr r3, [r3, #16]
|
|
800644e: 2b00 cmp r3, #0
|
|
8006450: d132 bne.n 80064b8 <USB_EPStartXfer+0x90>
|
|
{
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
|
8006452: 69bb ldr r3, [r7, #24]
|
|
8006454: 015a lsls r2, r3, #5
|
|
8006456: 69fb ldr r3, [r7, #28]
|
|
8006458: 4413 add r3, r2
|
|
800645a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800645e: 691b ldr r3, [r3, #16]
|
|
8006460: 69ba ldr r2, [r7, #24]
|
|
8006462: 0151 lsls r1, r2, #5
|
|
8006464: 69fa ldr r2, [r7, #28]
|
|
8006466: 440a add r2, r1
|
|
8006468: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800646c: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
8006470: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
8006474: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
|
|
8006476: 69bb ldr r3, [r7, #24]
|
|
8006478: 015a lsls r2, r3, #5
|
|
800647a: 69fb ldr r3, [r7, #28]
|
|
800647c: 4413 add r3, r2
|
|
800647e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006482: 691b ldr r3, [r3, #16]
|
|
8006484: 69ba ldr r2, [r7, #24]
|
|
8006486: 0151 lsls r1, r2, #5
|
|
8006488: 69fa ldr r2, [r7, #28]
|
|
800648a: 440a add r2, r1
|
|
800648c: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006490: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8006494: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
|
8006496: 69bb ldr r3, [r7, #24]
|
|
8006498: 015a lsls r2, r3, #5
|
|
800649a: 69fb ldr r3, [r7, #28]
|
|
800649c: 4413 add r3, r2
|
|
800649e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80064a2: 691b ldr r3, [r3, #16]
|
|
80064a4: 69ba ldr r2, [r7, #24]
|
|
80064a6: 0151 lsls r1, r2, #5
|
|
80064a8: 69fa ldr r2, [r7, #28]
|
|
80064aa: 440a add r2, r1
|
|
80064ac: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80064b0: 0cdb lsrs r3, r3, #19
|
|
80064b2: 04db lsls r3, r3, #19
|
|
80064b4: 6113 str r3, [r2, #16]
|
|
80064b6: e097 b.n 80065e8 <USB_EPStartXfer+0x1c0>
|
|
/* Program the transfer size and packet count
|
|
* as follows: xfersize = N * maxpacket +
|
|
* short_packet pktcnt = N + (short_packet
|
|
* exist ? 1 : 0)
|
|
*/
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
|
80064b8: 69bb ldr r3, [r7, #24]
|
|
80064ba: 015a lsls r2, r3, #5
|
|
80064bc: 69fb ldr r3, [r7, #28]
|
|
80064be: 4413 add r3, r2
|
|
80064c0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80064c4: 691b ldr r3, [r3, #16]
|
|
80064c6: 69ba ldr r2, [r7, #24]
|
|
80064c8: 0151 lsls r1, r2, #5
|
|
80064ca: 69fa ldr r2, [r7, #28]
|
|
80064cc: 440a add r2, r1
|
|
80064ce: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80064d2: 0cdb lsrs r3, r3, #19
|
|
80064d4: 04db lsls r3, r3, #19
|
|
80064d6: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
|
80064d8: 69bb ldr r3, [r7, #24]
|
|
80064da: 015a lsls r2, r3, #5
|
|
80064dc: 69fb ldr r3, [r7, #28]
|
|
80064de: 4413 add r3, r2
|
|
80064e0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80064e4: 691b ldr r3, [r3, #16]
|
|
80064e6: 69ba ldr r2, [r7, #24]
|
|
80064e8: 0151 lsls r1, r2, #5
|
|
80064ea: 69fa ldr r2, [r7, #28]
|
|
80064ec: 440a add r2, r1
|
|
80064ee: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80064f2: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
80064f6: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
80064fa: 6113 str r3, [r2, #16]
|
|
|
|
if (epnum == 0U)
|
|
80064fc: 69bb ldr r3, [r7, #24]
|
|
80064fe: 2b00 cmp r3, #0
|
|
8006500: d11a bne.n 8006538 <USB_EPStartXfer+0x110>
|
|
{
|
|
if (ep->xfer_len > ep->maxpacket)
|
|
8006502: 68bb ldr r3, [r7, #8]
|
|
8006504: 691a ldr r2, [r3, #16]
|
|
8006506: 68bb ldr r3, [r7, #8]
|
|
8006508: 689b ldr r3, [r3, #8]
|
|
800650a: 429a cmp r2, r3
|
|
800650c: d903 bls.n 8006516 <USB_EPStartXfer+0xee>
|
|
{
|
|
ep->xfer_len = ep->maxpacket;
|
|
800650e: 68bb ldr r3, [r7, #8]
|
|
8006510: 689a ldr r2, [r3, #8]
|
|
8006512: 68bb ldr r3, [r7, #8]
|
|
8006514: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
|
|
8006516: 69bb ldr r3, [r7, #24]
|
|
8006518: 015a lsls r2, r3, #5
|
|
800651a: 69fb ldr r3, [r7, #28]
|
|
800651c: 4413 add r3, r2
|
|
800651e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006522: 691b ldr r3, [r3, #16]
|
|
8006524: 69ba ldr r2, [r7, #24]
|
|
8006526: 0151 lsls r1, r2, #5
|
|
8006528: 69fa ldr r2, [r7, #28]
|
|
800652a: 440a add r2, r1
|
|
800652c: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006530: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8006534: 6113 str r3, [r2, #16]
|
|
8006536: e044 b.n 80065c2 <USB_EPStartXfer+0x19a>
|
|
}
|
|
else
|
|
{
|
|
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
|
|
8006538: 68bb ldr r3, [r7, #8]
|
|
800653a: 691a ldr r2, [r3, #16]
|
|
800653c: 68bb ldr r3, [r7, #8]
|
|
800653e: 689b ldr r3, [r3, #8]
|
|
8006540: 4413 add r3, r2
|
|
8006542: 1e5a subs r2, r3, #1
|
|
8006544: 68bb ldr r3, [r7, #8]
|
|
8006546: 689b ldr r3, [r3, #8]
|
|
8006548: fbb2 f3f3 udiv r3, r2, r3
|
|
800654c: 82fb strh r3, [r7, #22]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19));
|
|
800654e: 69bb ldr r3, [r7, #24]
|
|
8006550: 015a lsls r2, r3, #5
|
|
8006552: 69fb ldr r3, [r7, #28]
|
|
8006554: 4413 add r3, r2
|
|
8006556: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800655a: 691a ldr r2, [r3, #16]
|
|
800655c: 8afb ldrh r3, [r7, #22]
|
|
800655e: 04d9 lsls r1, r3, #19
|
|
8006560: 4ba4 ldr r3, [pc, #656] @ (80067f4 <USB_EPStartXfer+0x3cc>)
|
|
8006562: 400b ands r3, r1
|
|
8006564: 69b9 ldr r1, [r7, #24]
|
|
8006566: 0148 lsls r0, r1, #5
|
|
8006568: 69f9 ldr r1, [r7, #28]
|
|
800656a: 4401 add r1, r0
|
|
800656c: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
8006570: 4313 orrs r3, r2
|
|
8006572: 610b str r3, [r1, #16]
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
8006574: 68bb ldr r3, [r7, #8]
|
|
8006576: 791b ldrb r3, [r3, #4]
|
|
8006578: 2b01 cmp r3, #1
|
|
800657a: d122 bne.n 80065c2 <USB_EPStartXfer+0x19a>
|
|
{
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
|
|
800657c: 69bb ldr r3, [r7, #24]
|
|
800657e: 015a lsls r2, r3, #5
|
|
8006580: 69fb ldr r3, [r7, #28]
|
|
8006582: 4413 add r3, r2
|
|
8006584: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006588: 691b ldr r3, [r3, #16]
|
|
800658a: 69ba ldr r2, [r7, #24]
|
|
800658c: 0151 lsls r1, r2, #5
|
|
800658e: 69fa ldr r2, [r7, #28]
|
|
8006590: 440a add r2, r1
|
|
8006592: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006596: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000
|
|
800659a: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29));
|
|
800659c: 69bb ldr r3, [r7, #24]
|
|
800659e: 015a lsls r2, r3, #5
|
|
80065a0: 69fb ldr r3, [r7, #28]
|
|
80065a2: 4413 add r3, r2
|
|
80065a4: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80065a8: 691a ldr r2, [r3, #16]
|
|
80065aa: 8afb ldrh r3, [r7, #22]
|
|
80065ac: 075b lsls r3, r3, #29
|
|
80065ae: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000
|
|
80065b2: 69b9 ldr r1, [r7, #24]
|
|
80065b4: 0148 lsls r0, r1, #5
|
|
80065b6: 69f9 ldr r1, [r7, #28]
|
|
80065b8: 4401 add r1, r0
|
|
80065ba: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
80065be: 4313 orrs r3, r2
|
|
80065c0: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
|
|
80065c2: 69bb ldr r3, [r7, #24]
|
|
80065c4: 015a lsls r2, r3, #5
|
|
80065c6: 69fb ldr r3, [r7, #28]
|
|
80065c8: 4413 add r3, r2
|
|
80065ca: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80065ce: 691a ldr r2, [r3, #16]
|
|
80065d0: 68bb ldr r3, [r7, #8]
|
|
80065d2: 691b ldr r3, [r3, #16]
|
|
80065d4: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80065d8: 69b9 ldr r1, [r7, #24]
|
|
80065da: 0148 lsls r0, r1, #5
|
|
80065dc: 69f9 ldr r1, [r7, #28]
|
|
80065de: 4401 add r1, r0
|
|
80065e0: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
80065e4: 4313 orrs r3, r2
|
|
80065e6: 610b str r3, [r1, #16]
|
|
}
|
|
|
|
if (dma == 1U)
|
|
80065e8: 79fb ldrb r3, [r7, #7]
|
|
80065ea: 2b01 cmp r3, #1
|
|
80065ec: d14b bne.n 8006686 <USB_EPStartXfer+0x25e>
|
|
{
|
|
if ((uint32_t)ep->dma_addr != 0U)
|
|
80065ee: 68bb ldr r3, [r7, #8]
|
|
80065f0: 69db ldr r3, [r3, #28]
|
|
80065f2: 2b00 cmp r3, #0
|
|
80065f4: d009 beq.n 800660a <USB_EPStartXfer+0x1e2>
|
|
{
|
|
USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
|
|
80065f6: 69bb ldr r3, [r7, #24]
|
|
80065f8: 015a lsls r2, r3, #5
|
|
80065fa: 69fb ldr r3, [r7, #28]
|
|
80065fc: 4413 add r3, r2
|
|
80065fe: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006602: 461a mov r2, r3
|
|
8006604: 68bb ldr r3, [r7, #8]
|
|
8006606: 69db ldr r3, [r3, #28]
|
|
8006608: 6153 str r3, [r2, #20]
|
|
}
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
800660a: 68bb ldr r3, [r7, #8]
|
|
800660c: 791b ldrb r3, [r3, #4]
|
|
800660e: 2b01 cmp r3, #1
|
|
8006610: d128 bne.n 8006664 <USB_EPStartXfer+0x23c>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
8006612: 69fb ldr r3, [r7, #28]
|
|
8006614: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006618: 689b ldr r3, [r3, #8]
|
|
800661a: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800661e: 2b00 cmp r3, #0
|
|
8006620: d110 bne.n 8006644 <USB_EPStartXfer+0x21c>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
|
|
8006622: 69bb ldr r3, [r7, #24]
|
|
8006624: 015a lsls r2, r3, #5
|
|
8006626: 69fb ldr r3, [r7, #28]
|
|
8006628: 4413 add r3, r2
|
|
800662a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800662e: 681b ldr r3, [r3, #0]
|
|
8006630: 69ba ldr r2, [r7, #24]
|
|
8006632: 0151 lsls r1, r2, #5
|
|
8006634: 69fa ldr r2, [r7, #28]
|
|
8006636: 440a add r2, r1
|
|
8006638: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800663c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8006640: 6013 str r3, [r2, #0]
|
|
8006642: e00f b.n 8006664 <USB_EPStartXfer+0x23c>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
|
8006644: 69bb ldr r3, [r7, #24]
|
|
8006646: 015a lsls r2, r3, #5
|
|
8006648: 69fb ldr r3, [r7, #28]
|
|
800664a: 4413 add r3, r2
|
|
800664c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006650: 681b ldr r3, [r3, #0]
|
|
8006652: 69ba ldr r2, [r7, #24]
|
|
8006654: 0151 lsls r1, r2, #5
|
|
8006656: 69fa ldr r2, [r7, #28]
|
|
8006658: 440a add r2, r1
|
|
800665a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800665e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006662: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
/* EP enable, IN data in FIFO */
|
|
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
|
8006664: 69bb ldr r3, [r7, #24]
|
|
8006666: 015a lsls r2, r3, #5
|
|
8006668: 69fb ldr r3, [r7, #28]
|
|
800666a: 4413 add r3, r2
|
|
800666c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006670: 681b ldr r3, [r3, #0]
|
|
8006672: 69ba ldr r2, [r7, #24]
|
|
8006674: 0151 lsls r1, r2, #5
|
|
8006676: 69fa ldr r2, [r7, #28]
|
|
8006678: 440a add r2, r1
|
|
800667a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800667e: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
8006682: 6013 str r3, [r2, #0]
|
|
8006684: e166 b.n 8006954 <USB_EPStartXfer+0x52c>
|
|
}
|
|
else
|
|
{
|
|
/* EP enable, IN data in FIFO */
|
|
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
|
8006686: 69bb ldr r3, [r7, #24]
|
|
8006688: 015a lsls r2, r3, #5
|
|
800668a: 69fb ldr r3, [r7, #28]
|
|
800668c: 4413 add r3, r2
|
|
800668e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006692: 681b ldr r3, [r3, #0]
|
|
8006694: 69ba ldr r2, [r7, #24]
|
|
8006696: 0151 lsls r1, r2, #5
|
|
8006698: 69fa ldr r2, [r7, #28]
|
|
800669a: 440a add r2, r1
|
|
800669c: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80066a0: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
80066a4: 6013 str r3, [r2, #0]
|
|
|
|
if (ep->type != EP_TYPE_ISOC)
|
|
80066a6: 68bb ldr r3, [r7, #8]
|
|
80066a8: 791b ldrb r3, [r3, #4]
|
|
80066aa: 2b01 cmp r3, #1
|
|
80066ac: d015 beq.n 80066da <USB_EPStartXfer+0x2b2>
|
|
{
|
|
/* Enable the Tx FIFO Empty Interrupt for this EP */
|
|
if (ep->xfer_len > 0U)
|
|
80066ae: 68bb ldr r3, [r7, #8]
|
|
80066b0: 691b ldr r3, [r3, #16]
|
|
80066b2: 2b00 cmp r3, #0
|
|
80066b4: f000 814e beq.w 8006954 <USB_EPStartXfer+0x52c>
|
|
{
|
|
USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
|
|
80066b8: 69fb ldr r3, [r7, #28]
|
|
80066ba: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80066be: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80066c0: 68bb ldr r3, [r7, #8]
|
|
80066c2: 781b ldrb r3, [r3, #0]
|
|
80066c4: f003 030f and.w r3, r3, #15
|
|
80066c8: 2101 movs r1, #1
|
|
80066ca: fa01 f303 lsl.w r3, r1, r3
|
|
80066ce: 69f9 ldr r1, [r7, #28]
|
|
80066d0: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80066d4: 4313 orrs r3, r2
|
|
80066d6: 634b str r3, [r1, #52] @ 0x34
|
|
80066d8: e13c b.n 8006954 <USB_EPStartXfer+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
80066da: 69fb ldr r3, [r7, #28]
|
|
80066dc: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80066e0: 689b ldr r3, [r3, #8]
|
|
80066e2: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80066e6: 2b00 cmp r3, #0
|
|
80066e8: d110 bne.n 800670c <USB_EPStartXfer+0x2e4>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
|
|
80066ea: 69bb ldr r3, [r7, #24]
|
|
80066ec: 015a lsls r2, r3, #5
|
|
80066ee: 69fb ldr r3, [r7, #28]
|
|
80066f0: 4413 add r3, r2
|
|
80066f2: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80066f6: 681b ldr r3, [r3, #0]
|
|
80066f8: 69ba ldr r2, [r7, #24]
|
|
80066fa: 0151 lsls r1, r2, #5
|
|
80066fc: 69fa ldr r2, [r7, #28]
|
|
80066fe: 440a add r2, r1
|
|
8006700: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006704: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8006708: 6013 str r3, [r2, #0]
|
|
800670a: e00f b.n 800672c <USB_EPStartXfer+0x304>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
|
800670c: 69bb ldr r3, [r7, #24]
|
|
800670e: 015a lsls r2, r3, #5
|
|
8006710: 69fb ldr r3, [r7, #28]
|
|
8006712: 4413 add r3, r2
|
|
8006714: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006718: 681b ldr r3, [r3, #0]
|
|
800671a: 69ba ldr r2, [r7, #24]
|
|
800671c: 0151 lsls r1, r2, #5
|
|
800671e: 69fa ldr r2, [r7, #28]
|
|
8006720: 440a add r2, r1
|
|
8006722: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006726: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800672a: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
|
|
800672c: 68bb ldr r3, [r7, #8]
|
|
800672e: 68d9 ldr r1, [r3, #12]
|
|
8006730: 68bb ldr r3, [r7, #8]
|
|
8006732: 781a ldrb r2, [r3, #0]
|
|
8006734: 68bb ldr r3, [r7, #8]
|
|
8006736: 691b ldr r3, [r3, #16]
|
|
8006738: b298 uxth r0, r3
|
|
800673a: 79fb ldrb r3, [r7, #7]
|
|
800673c: 9300 str r3, [sp, #0]
|
|
800673e: 4603 mov r3, r0
|
|
8006740: 68f8 ldr r0, [r7, #12]
|
|
8006742: f000 f9b9 bl 8006ab8 <USB_WritePacket>
|
|
8006746: e105 b.n 8006954 <USB_EPStartXfer+0x52c>
|
|
{
|
|
/* Program the transfer size and packet count as follows:
|
|
* pktcnt = N
|
|
* xfersize = N * maxpacket
|
|
*/
|
|
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
|
|
8006748: 69bb ldr r3, [r7, #24]
|
|
800674a: 015a lsls r2, r3, #5
|
|
800674c: 69fb ldr r3, [r7, #28]
|
|
800674e: 4413 add r3, r2
|
|
8006750: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006754: 691b ldr r3, [r3, #16]
|
|
8006756: 69ba ldr r2, [r7, #24]
|
|
8006758: 0151 lsls r1, r2, #5
|
|
800675a: 69fa ldr r2, [r7, #28]
|
|
800675c: 440a add r2, r1
|
|
800675e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006762: 0cdb lsrs r3, r3, #19
|
|
8006764: 04db lsls r3, r3, #19
|
|
8006766: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
|
|
8006768: 69bb ldr r3, [r7, #24]
|
|
800676a: 015a lsls r2, r3, #5
|
|
800676c: 69fb ldr r3, [r7, #28]
|
|
800676e: 4413 add r3, r2
|
|
8006770: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006774: 691b ldr r3, [r3, #16]
|
|
8006776: 69ba ldr r2, [r7, #24]
|
|
8006778: 0151 lsls r1, r2, #5
|
|
800677a: 69fa ldr r2, [r7, #28]
|
|
800677c: 440a add r2, r1
|
|
800677e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006782: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
8006786: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
800678a: 6113 str r3, [r2, #16]
|
|
|
|
if (epnum == 0U)
|
|
800678c: 69bb ldr r3, [r7, #24]
|
|
800678e: 2b00 cmp r3, #0
|
|
8006790: d132 bne.n 80067f8 <USB_EPStartXfer+0x3d0>
|
|
{
|
|
if (ep->xfer_len > 0U)
|
|
8006792: 68bb ldr r3, [r7, #8]
|
|
8006794: 691b ldr r3, [r3, #16]
|
|
8006796: 2b00 cmp r3, #0
|
|
8006798: d003 beq.n 80067a2 <USB_EPStartXfer+0x37a>
|
|
{
|
|
ep->xfer_len = ep->maxpacket;
|
|
800679a: 68bb ldr r3, [r7, #8]
|
|
800679c: 689a ldr r2, [r3, #8]
|
|
800679e: 68bb ldr r3, [r7, #8]
|
|
80067a0: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
/* Store transfer size, for EP0 this is equal to endpoint max packet size */
|
|
ep->xfer_size = ep->maxpacket;
|
|
80067a2: 68bb ldr r3, [r7, #8]
|
|
80067a4: 689a ldr r2, [r3, #8]
|
|
80067a6: 68bb ldr r3, [r7, #8]
|
|
80067a8: 621a str r2, [r3, #32]
|
|
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
|
|
80067aa: 69bb ldr r3, [r7, #24]
|
|
80067ac: 015a lsls r2, r3, #5
|
|
80067ae: 69fb ldr r3, [r7, #28]
|
|
80067b0: 4413 add r3, r2
|
|
80067b2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80067b6: 691a ldr r2, [r3, #16]
|
|
80067b8: 68bb ldr r3, [r7, #8]
|
|
80067ba: 6a1b ldr r3, [r3, #32]
|
|
80067bc: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80067c0: 69b9 ldr r1, [r7, #24]
|
|
80067c2: 0148 lsls r0, r1, #5
|
|
80067c4: 69f9 ldr r1, [r7, #28]
|
|
80067c6: 4401 add r1, r0
|
|
80067c8: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
80067cc: 4313 orrs r3, r2
|
|
80067ce: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
80067d0: 69bb ldr r3, [r7, #24]
|
|
80067d2: 015a lsls r2, r3, #5
|
|
80067d4: 69fb ldr r3, [r7, #28]
|
|
80067d6: 4413 add r3, r2
|
|
80067d8: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80067dc: 691b ldr r3, [r3, #16]
|
|
80067de: 69ba ldr r2, [r7, #24]
|
|
80067e0: 0151 lsls r1, r2, #5
|
|
80067e2: 69fa ldr r2, [r7, #28]
|
|
80067e4: 440a add r2, r1
|
|
80067e6: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
80067ea: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
80067ee: 6113 str r3, [r2, #16]
|
|
80067f0: e062 b.n 80068b8 <USB_EPStartXfer+0x490>
|
|
80067f2: bf00 nop
|
|
80067f4: 1ff80000 .word 0x1ff80000
|
|
}
|
|
else
|
|
{
|
|
if (ep->xfer_len == 0U)
|
|
80067f8: 68bb ldr r3, [r7, #8]
|
|
80067fa: 691b ldr r3, [r3, #16]
|
|
80067fc: 2b00 cmp r3, #0
|
|
80067fe: d123 bne.n 8006848 <USB_EPStartXfer+0x420>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
|
|
8006800: 69bb ldr r3, [r7, #24]
|
|
8006802: 015a lsls r2, r3, #5
|
|
8006804: 69fb ldr r3, [r7, #28]
|
|
8006806: 4413 add r3, r2
|
|
8006808: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800680c: 691a ldr r2, [r3, #16]
|
|
800680e: 68bb ldr r3, [r7, #8]
|
|
8006810: 689b ldr r3, [r3, #8]
|
|
8006812: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8006816: 69b9 ldr r1, [r7, #24]
|
|
8006818: 0148 lsls r0, r1, #5
|
|
800681a: 69f9 ldr r1, [r7, #28]
|
|
800681c: 4401 add r1, r0
|
|
800681e: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
8006822: 4313 orrs r3, r2
|
|
8006824: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
8006826: 69bb ldr r3, [r7, #24]
|
|
8006828: 015a lsls r2, r3, #5
|
|
800682a: 69fb ldr r3, [r7, #28]
|
|
800682c: 4413 add r3, r2
|
|
800682e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006832: 691b ldr r3, [r3, #16]
|
|
8006834: 69ba ldr r2, [r7, #24]
|
|
8006836: 0151 lsls r1, r2, #5
|
|
8006838: 69fa ldr r2, [r7, #28]
|
|
800683a: 440a add r2, r1
|
|
800683c: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006840: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8006844: 6113 str r3, [r2, #16]
|
|
8006846: e037 b.n 80068b8 <USB_EPStartXfer+0x490>
|
|
}
|
|
else
|
|
{
|
|
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
|
|
8006848: 68bb ldr r3, [r7, #8]
|
|
800684a: 691a ldr r2, [r3, #16]
|
|
800684c: 68bb ldr r3, [r7, #8]
|
|
800684e: 689b ldr r3, [r3, #8]
|
|
8006850: 4413 add r3, r2
|
|
8006852: 1e5a subs r2, r3, #1
|
|
8006854: 68bb ldr r3, [r7, #8]
|
|
8006856: 689b ldr r3, [r3, #8]
|
|
8006858: fbb2 f3f3 udiv r3, r2, r3
|
|
800685c: 82fb strh r3, [r7, #22]
|
|
ep->xfer_size = ep->maxpacket * pktcnt;
|
|
800685e: 68bb ldr r3, [r7, #8]
|
|
8006860: 689b ldr r3, [r3, #8]
|
|
8006862: 8afa ldrh r2, [r7, #22]
|
|
8006864: fb03 f202 mul.w r2, r3, r2
|
|
8006868: 68bb ldr r3, [r7, #8]
|
|
800686a: 621a str r2, [r3, #32]
|
|
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
|
|
800686c: 69bb ldr r3, [r7, #24]
|
|
800686e: 015a lsls r2, r3, #5
|
|
8006870: 69fb ldr r3, [r7, #28]
|
|
8006872: 4413 add r3, r2
|
|
8006874: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006878: 691a ldr r2, [r3, #16]
|
|
800687a: 8afb ldrh r3, [r7, #22]
|
|
800687c: 04d9 lsls r1, r3, #19
|
|
800687e: 4b38 ldr r3, [pc, #224] @ (8006960 <USB_EPStartXfer+0x538>)
|
|
8006880: 400b ands r3, r1
|
|
8006882: 69b9 ldr r1, [r7, #24]
|
|
8006884: 0148 lsls r0, r1, #5
|
|
8006886: 69f9 ldr r1, [r7, #28]
|
|
8006888: 4401 add r1, r0
|
|
800688a: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
800688e: 4313 orrs r3, r2
|
|
8006890: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size;
|
|
8006892: 69bb ldr r3, [r7, #24]
|
|
8006894: 015a lsls r2, r3, #5
|
|
8006896: 69fb ldr r3, [r7, #28]
|
|
8006898: 4413 add r3, r2
|
|
800689a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800689e: 691a ldr r2, [r3, #16]
|
|
80068a0: 68bb ldr r3, [r7, #8]
|
|
80068a2: 6a1b ldr r3, [r3, #32]
|
|
80068a4: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80068a8: 69b9 ldr r1, [r7, #24]
|
|
80068aa: 0148 lsls r0, r1, #5
|
|
80068ac: 69f9 ldr r1, [r7, #28]
|
|
80068ae: 4401 add r1, r0
|
|
80068b0: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
80068b4: 4313 orrs r3, r2
|
|
80068b6: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
if (dma == 1U)
|
|
80068b8: 79fb ldrb r3, [r7, #7]
|
|
80068ba: 2b01 cmp r3, #1
|
|
80068bc: d10d bne.n 80068da <USB_EPStartXfer+0x4b2>
|
|
{
|
|
if ((uint32_t)ep->xfer_buff != 0U)
|
|
80068be: 68bb ldr r3, [r7, #8]
|
|
80068c0: 68db ldr r3, [r3, #12]
|
|
80068c2: 2b00 cmp r3, #0
|
|
80068c4: d009 beq.n 80068da <USB_EPStartXfer+0x4b2>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
|
|
80068c6: 68bb ldr r3, [r7, #8]
|
|
80068c8: 68d9 ldr r1, [r3, #12]
|
|
80068ca: 69bb ldr r3, [r7, #24]
|
|
80068cc: 015a lsls r2, r3, #5
|
|
80068ce: 69fb ldr r3, [r7, #28]
|
|
80068d0: 4413 add r3, r2
|
|
80068d2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80068d6: 460a mov r2, r1
|
|
80068d8: 615a str r2, [r3, #20]
|
|
}
|
|
}
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
80068da: 68bb ldr r3, [r7, #8]
|
|
80068dc: 791b ldrb r3, [r3, #4]
|
|
80068de: 2b01 cmp r3, #1
|
|
80068e0: d128 bne.n 8006934 <USB_EPStartXfer+0x50c>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
80068e2: 69fb ldr r3, [r7, #28]
|
|
80068e4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80068e8: 689b ldr r3, [r3, #8]
|
|
80068ea: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80068ee: 2b00 cmp r3, #0
|
|
80068f0: d110 bne.n 8006914 <USB_EPStartXfer+0x4ec>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
|
|
80068f2: 69bb ldr r3, [r7, #24]
|
|
80068f4: 015a lsls r2, r3, #5
|
|
80068f6: 69fb ldr r3, [r7, #28]
|
|
80068f8: 4413 add r3, r2
|
|
80068fa: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80068fe: 681b ldr r3, [r3, #0]
|
|
8006900: 69ba ldr r2, [r7, #24]
|
|
8006902: 0151 lsls r1, r2, #5
|
|
8006904: 69fa ldr r2, [r7, #28]
|
|
8006906: 440a add r2, r1
|
|
8006908: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800690c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8006910: 6013 str r3, [r2, #0]
|
|
8006912: e00f b.n 8006934 <USB_EPStartXfer+0x50c>
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
|
|
8006914: 69bb ldr r3, [r7, #24]
|
|
8006916: 015a lsls r2, r3, #5
|
|
8006918: 69fb ldr r3, [r7, #28]
|
|
800691a: 4413 add r3, r2
|
|
800691c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006920: 681b ldr r3, [r3, #0]
|
|
8006922: 69ba ldr r2, [r7, #24]
|
|
8006924: 0151 lsls r1, r2, #5
|
|
8006926: 69fa ldr r2, [r7, #28]
|
|
8006928: 440a add r2, r1
|
|
800692a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800692e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006932: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
/* EP enable */
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
|
|
8006934: 69bb ldr r3, [r7, #24]
|
|
8006936: 015a lsls r2, r3, #5
|
|
8006938: 69fb ldr r3, [r7, #28]
|
|
800693a: 4413 add r3, r2
|
|
800693c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006940: 681b ldr r3, [r3, #0]
|
|
8006942: 69ba ldr r2, [r7, #24]
|
|
8006944: 0151 lsls r1, r2, #5
|
|
8006946: 69fa ldr r2, [r7, #28]
|
|
8006948: 440a add r2, r1
|
|
800694a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800694e: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
8006952: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006954: 2300 movs r3, #0
|
|
}
|
|
8006956: 4618 mov r0, r3
|
|
8006958: 3720 adds r7, #32
|
|
800695a: 46bd mov sp, r7
|
|
800695c: bd80 pop {r7, pc}
|
|
800695e: bf00 nop
|
|
8006960: 1ff80000 .word 0x1ff80000
|
|
|
|
08006964 <USB_EPStopXfer>:
|
|
* @param USBx usb device instance
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8006964: b480 push {r7}
|
|
8006966: b087 sub sp, #28
|
|
8006968: af00 add r7, sp, #0
|
|
800696a: 6078 str r0, [r7, #4]
|
|
800696c: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
800696e: 2300 movs r3, #0
|
|
8006970: 60fb str r3, [r7, #12]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8006972: 2300 movs r3, #0
|
|
8006974: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006976: 687b ldr r3, [r7, #4]
|
|
8006978: 613b str r3, [r7, #16]
|
|
|
|
/* IN endpoint */
|
|
if (ep->is_in == 1U)
|
|
800697a: 683b ldr r3, [r7, #0]
|
|
800697c: 785b ldrb r3, [r3, #1]
|
|
800697e: 2b01 cmp r3, #1
|
|
8006980: d14a bne.n 8006a18 <USB_EPStopXfer+0xb4>
|
|
{
|
|
/* EP enable, IN data in FIFO */
|
|
if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
8006982: 683b ldr r3, [r7, #0]
|
|
8006984: 781b ldrb r3, [r3, #0]
|
|
8006986: 015a lsls r2, r3, #5
|
|
8006988: 693b ldr r3, [r7, #16]
|
|
800698a: 4413 add r3, r2
|
|
800698c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006990: 681b ldr r3, [r3, #0]
|
|
8006992: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006996: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800699a: f040 8086 bne.w 8006aaa <USB_EPStopXfer+0x146>
|
|
{
|
|
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
|
|
800699e: 683b ldr r3, [r7, #0]
|
|
80069a0: 781b ldrb r3, [r3, #0]
|
|
80069a2: 015a lsls r2, r3, #5
|
|
80069a4: 693b ldr r3, [r7, #16]
|
|
80069a6: 4413 add r3, r2
|
|
80069a8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80069ac: 681b ldr r3, [r3, #0]
|
|
80069ae: 683a ldr r2, [r7, #0]
|
|
80069b0: 7812 ldrb r2, [r2, #0]
|
|
80069b2: 0151 lsls r1, r2, #5
|
|
80069b4: 693a ldr r2, [r7, #16]
|
|
80069b6: 440a add r2, r1
|
|
80069b8: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80069bc: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
80069c0: 6013 str r3, [r2, #0]
|
|
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
|
|
80069c2: 683b ldr r3, [r7, #0]
|
|
80069c4: 781b ldrb r3, [r3, #0]
|
|
80069c6: 015a lsls r2, r3, #5
|
|
80069c8: 693b ldr r3, [r7, #16]
|
|
80069ca: 4413 add r3, r2
|
|
80069cc: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80069d0: 681b ldr r3, [r3, #0]
|
|
80069d2: 683a ldr r2, [r7, #0]
|
|
80069d4: 7812 ldrb r2, [r2, #0]
|
|
80069d6: 0151 lsls r1, r2, #5
|
|
80069d8: 693a ldr r2, [r7, #16]
|
|
80069da: 440a add r2, r1
|
|
80069dc: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80069e0: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80069e4: 6013 str r3, [r2, #0]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
80069e6: 68fb ldr r3, [r7, #12]
|
|
80069e8: 3301 adds r3, #1
|
|
80069ea: 60fb str r3, [r7, #12]
|
|
|
|
if (count > 10000U)
|
|
80069ec: 68fb ldr r3, [r7, #12]
|
|
80069ee: f242 7210 movw r2, #10000 @ 0x2710
|
|
80069f2: 4293 cmp r3, r2
|
|
80069f4: d902 bls.n 80069fc <USB_EPStopXfer+0x98>
|
|
{
|
|
ret = HAL_ERROR;
|
|
80069f6: 2301 movs r3, #1
|
|
80069f8: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80069fa: e056 b.n 8006aaa <USB_EPStopXfer+0x146>
|
|
}
|
|
} while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA);
|
|
80069fc: 683b ldr r3, [r7, #0]
|
|
80069fe: 781b ldrb r3, [r3, #0]
|
|
8006a00: 015a lsls r2, r3, #5
|
|
8006a02: 693b ldr r3, [r7, #16]
|
|
8006a04: 4413 add r3, r2
|
|
8006a06: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006a0a: 681b ldr r3, [r3, #0]
|
|
8006a0c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006a10: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8006a14: d0e7 beq.n 80069e6 <USB_EPStopXfer+0x82>
|
|
8006a16: e048 b.n 8006aaa <USB_EPStopXfer+0x146>
|
|
}
|
|
}
|
|
else /* OUT endpoint */
|
|
{
|
|
if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
8006a18: 683b ldr r3, [r7, #0]
|
|
8006a1a: 781b ldrb r3, [r3, #0]
|
|
8006a1c: 015a lsls r2, r3, #5
|
|
8006a1e: 693b ldr r3, [r7, #16]
|
|
8006a20: 4413 add r3, r2
|
|
8006a22: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006a26: 681b ldr r3, [r3, #0]
|
|
8006a28: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006a2c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8006a30: d13b bne.n 8006aaa <USB_EPStopXfer+0x146>
|
|
{
|
|
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
|
|
8006a32: 683b ldr r3, [r7, #0]
|
|
8006a34: 781b ldrb r3, [r3, #0]
|
|
8006a36: 015a lsls r2, r3, #5
|
|
8006a38: 693b ldr r3, [r7, #16]
|
|
8006a3a: 4413 add r3, r2
|
|
8006a3c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006a40: 681b ldr r3, [r3, #0]
|
|
8006a42: 683a ldr r2, [r7, #0]
|
|
8006a44: 7812 ldrb r2, [r2, #0]
|
|
8006a46: 0151 lsls r1, r2, #5
|
|
8006a48: 693a ldr r2, [r7, #16]
|
|
8006a4a: 440a add r2, r1
|
|
8006a4c: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006a50: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8006a54: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
|
|
8006a56: 683b ldr r3, [r7, #0]
|
|
8006a58: 781b ldrb r3, [r3, #0]
|
|
8006a5a: 015a lsls r2, r3, #5
|
|
8006a5c: 693b ldr r3, [r7, #16]
|
|
8006a5e: 4413 add r3, r2
|
|
8006a60: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006a64: 681b ldr r3, [r3, #0]
|
|
8006a66: 683a ldr r2, [r7, #0]
|
|
8006a68: 7812 ldrb r2, [r2, #0]
|
|
8006a6a: 0151 lsls r1, r2, #5
|
|
8006a6c: 693a ldr r2, [r7, #16]
|
|
8006a6e: 440a add r2, r1
|
|
8006a70: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006a74: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8006a78: 6013 str r3, [r2, #0]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8006a7a: 68fb ldr r3, [r7, #12]
|
|
8006a7c: 3301 adds r3, #1
|
|
8006a7e: 60fb str r3, [r7, #12]
|
|
|
|
if (count > 10000U)
|
|
8006a80: 68fb ldr r3, [r7, #12]
|
|
8006a82: f242 7210 movw r2, #10000 @ 0x2710
|
|
8006a86: 4293 cmp r3, r2
|
|
8006a88: d902 bls.n 8006a90 <USB_EPStopXfer+0x12c>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006a8a: 2301 movs r3, #1
|
|
8006a8c: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8006a8e: e00c b.n 8006aaa <USB_EPStopXfer+0x146>
|
|
}
|
|
} while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA);
|
|
8006a90: 683b ldr r3, [r7, #0]
|
|
8006a92: 781b ldrb r3, [r3, #0]
|
|
8006a94: 015a lsls r2, r3, #5
|
|
8006a96: 693b ldr r3, [r7, #16]
|
|
8006a98: 4413 add r3, r2
|
|
8006a9a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006a9e: 681b ldr r3, [r3, #0]
|
|
8006aa0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006aa4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8006aa8: d0e7 beq.n 8006a7a <USB_EPStopXfer+0x116>
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
8006aaa: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8006aac: 4618 mov r0, r3
|
|
8006aae: 371c adds r7, #28
|
|
8006ab0: 46bd mov sp, r7
|
|
8006ab2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006ab6: 4770 bx lr
|
|
|
|
08006ab8 <USB_WritePacket>:
|
|
* 1 : DMA feature used
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
|
|
uint8_t ch_ep_num, uint16_t len, uint8_t dma)
|
|
{
|
|
8006ab8: b480 push {r7}
|
|
8006aba: b089 sub sp, #36 @ 0x24
|
|
8006abc: af00 add r7, sp, #0
|
|
8006abe: 60f8 str r0, [r7, #12]
|
|
8006ac0: 60b9 str r1, [r7, #8]
|
|
8006ac2: 4611 mov r1, r2
|
|
8006ac4: 461a mov r2, r3
|
|
8006ac6: 460b mov r3, r1
|
|
8006ac8: 71fb strb r3, [r7, #7]
|
|
8006aca: 4613 mov r3, r2
|
|
8006acc: 80bb strh r3, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006ace: 68fb ldr r3, [r7, #12]
|
|
8006ad0: 617b str r3, [r7, #20]
|
|
uint8_t *pSrc = src;
|
|
8006ad2: 68bb ldr r3, [r7, #8]
|
|
8006ad4: 61fb str r3, [r7, #28]
|
|
uint32_t count32b;
|
|
uint32_t i;
|
|
|
|
if (dma == 0U)
|
|
8006ad6: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8006ada: 2b00 cmp r3, #0
|
|
8006adc: d123 bne.n 8006b26 <USB_WritePacket+0x6e>
|
|
{
|
|
count32b = ((uint32_t)len + 3U) / 4U;
|
|
8006ade: 88bb ldrh r3, [r7, #4]
|
|
8006ae0: 3303 adds r3, #3
|
|
8006ae2: 089b lsrs r3, r3, #2
|
|
8006ae4: 613b str r3, [r7, #16]
|
|
for (i = 0U; i < count32b; i++)
|
|
8006ae6: 2300 movs r3, #0
|
|
8006ae8: 61bb str r3, [r7, #24]
|
|
8006aea: e018 b.n 8006b1e <USB_WritePacket+0x66>
|
|
{
|
|
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
|
|
8006aec: 79fb ldrb r3, [r7, #7]
|
|
8006aee: 031a lsls r2, r3, #12
|
|
8006af0: 697b ldr r3, [r7, #20]
|
|
8006af2: 4413 add r3, r2
|
|
8006af4: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8006af8: 461a mov r2, r3
|
|
8006afa: 69fb ldr r3, [r7, #28]
|
|
8006afc: 681b ldr r3, [r3, #0]
|
|
8006afe: 6013 str r3, [r2, #0]
|
|
pSrc++;
|
|
8006b00: 69fb ldr r3, [r7, #28]
|
|
8006b02: 3301 adds r3, #1
|
|
8006b04: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8006b06: 69fb ldr r3, [r7, #28]
|
|
8006b08: 3301 adds r3, #1
|
|
8006b0a: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8006b0c: 69fb ldr r3, [r7, #28]
|
|
8006b0e: 3301 adds r3, #1
|
|
8006b10: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8006b12: 69fb ldr r3, [r7, #28]
|
|
8006b14: 3301 adds r3, #1
|
|
8006b16: 61fb str r3, [r7, #28]
|
|
for (i = 0U; i < count32b; i++)
|
|
8006b18: 69bb ldr r3, [r7, #24]
|
|
8006b1a: 3301 adds r3, #1
|
|
8006b1c: 61bb str r3, [r7, #24]
|
|
8006b1e: 69ba ldr r2, [r7, #24]
|
|
8006b20: 693b ldr r3, [r7, #16]
|
|
8006b22: 429a cmp r2, r3
|
|
8006b24: d3e2 bcc.n 8006aec <USB_WritePacket+0x34>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006b26: 2300 movs r3, #0
|
|
}
|
|
8006b28: 4618 mov r0, r3
|
|
8006b2a: 3724 adds r7, #36 @ 0x24
|
|
8006b2c: 46bd mov sp, r7
|
|
8006b2e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006b32: 4770 bx lr
|
|
|
|
08006b34 <USB_ReadPacket>:
|
|
* @param dest source pointer
|
|
* @param len Number of bytes to read
|
|
* @retval pointer to destination buffer
|
|
*/
|
|
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
|
|
{
|
|
8006b34: b480 push {r7}
|
|
8006b36: b08b sub sp, #44 @ 0x2c
|
|
8006b38: af00 add r7, sp, #0
|
|
8006b3a: 60f8 str r0, [r7, #12]
|
|
8006b3c: 60b9 str r1, [r7, #8]
|
|
8006b3e: 4613 mov r3, r2
|
|
8006b40: 80fb strh r3, [r7, #6]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006b42: 68fb ldr r3, [r7, #12]
|
|
8006b44: 61bb str r3, [r7, #24]
|
|
uint8_t *pDest = dest;
|
|
8006b46: 68bb ldr r3, [r7, #8]
|
|
8006b48: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t pData;
|
|
uint32_t i;
|
|
uint32_t count32b = (uint32_t)len >> 2U;
|
|
8006b4a: 88fb ldrh r3, [r7, #6]
|
|
8006b4c: 089b lsrs r3, r3, #2
|
|
8006b4e: b29b uxth r3, r3
|
|
8006b50: 617b str r3, [r7, #20]
|
|
uint16_t remaining_bytes = len % 4U;
|
|
8006b52: 88fb ldrh r3, [r7, #6]
|
|
8006b54: f003 0303 and.w r3, r3, #3
|
|
8006b58: 83fb strh r3, [r7, #30]
|
|
|
|
for (i = 0U; i < count32b; i++)
|
|
8006b5a: 2300 movs r3, #0
|
|
8006b5c: 623b str r3, [r7, #32]
|
|
8006b5e: e014 b.n 8006b8a <USB_ReadPacket+0x56>
|
|
{
|
|
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
|
|
8006b60: 69bb ldr r3, [r7, #24]
|
|
8006b62: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8006b66: 681a ldr r2, [r3, #0]
|
|
8006b68: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006b6a: 601a str r2, [r3, #0]
|
|
pDest++;
|
|
8006b6c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006b6e: 3301 adds r3, #1
|
|
8006b70: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8006b72: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006b74: 3301 adds r3, #1
|
|
8006b76: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8006b78: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006b7a: 3301 adds r3, #1
|
|
8006b7c: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8006b7e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006b80: 3301 adds r3, #1
|
|
8006b82: 627b str r3, [r7, #36] @ 0x24
|
|
for (i = 0U; i < count32b; i++)
|
|
8006b84: 6a3b ldr r3, [r7, #32]
|
|
8006b86: 3301 adds r3, #1
|
|
8006b88: 623b str r3, [r7, #32]
|
|
8006b8a: 6a3a ldr r2, [r7, #32]
|
|
8006b8c: 697b ldr r3, [r7, #20]
|
|
8006b8e: 429a cmp r2, r3
|
|
8006b90: d3e6 bcc.n 8006b60 <USB_ReadPacket+0x2c>
|
|
}
|
|
|
|
/* When Number of data is not word aligned, read the remaining byte */
|
|
if (remaining_bytes != 0U)
|
|
8006b92: 8bfb ldrh r3, [r7, #30]
|
|
8006b94: 2b00 cmp r3, #0
|
|
8006b96: d01e beq.n 8006bd6 <USB_ReadPacket+0xa2>
|
|
{
|
|
i = 0U;
|
|
8006b98: 2300 movs r3, #0
|
|
8006b9a: 623b str r3, [r7, #32]
|
|
__UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
|
|
8006b9c: 69bb ldr r3, [r7, #24]
|
|
8006b9e: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8006ba2: 461a mov r2, r3
|
|
8006ba4: f107 0310 add.w r3, r7, #16
|
|
8006ba8: 6812 ldr r2, [r2, #0]
|
|
8006baa: 601a str r2, [r3, #0]
|
|
|
|
do
|
|
{
|
|
*(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
|
|
8006bac: 693a ldr r2, [r7, #16]
|
|
8006bae: 6a3b ldr r3, [r7, #32]
|
|
8006bb0: b2db uxtb r3, r3
|
|
8006bb2: 00db lsls r3, r3, #3
|
|
8006bb4: fa22 f303 lsr.w r3, r2, r3
|
|
8006bb8: b2da uxtb r2, r3
|
|
8006bba: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006bbc: 701a strb r2, [r3, #0]
|
|
i++;
|
|
8006bbe: 6a3b ldr r3, [r7, #32]
|
|
8006bc0: 3301 adds r3, #1
|
|
8006bc2: 623b str r3, [r7, #32]
|
|
pDest++;
|
|
8006bc4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006bc6: 3301 adds r3, #1
|
|
8006bc8: 627b str r3, [r7, #36] @ 0x24
|
|
remaining_bytes--;
|
|
8006bca: 8bfb ldrh r3, [r7, #30]
|
|
8006bcc: 3b01 subs r3, #1
|
|
8006bce: 83fb strh r3, [r7, #30]
|
|
} while (remaining_bytes != 0U);
|
|
8006bd0: 8bfb ldrh r3, [r7, #30]
|
|
8006bd2: 2b00 cmp r3, #0
|
|
8006bd4: d1ea bne.n 8006bac <USB_ReadPacket+0x78>
|
|
}
|
|
|
|
return ((void *)pDest);
|
|
8006bd6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
}
|
|
8006bd8: 4618 mov r0, r3
|
|
8006bda: 372c adds r7, #44 @ 0x2c
|
|
8006bdc: 46bd mov sp, r7
|
|
8006bde: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006be2: 4770 bx lr
|
|
|
|
08006be4 <USB_EPSetStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8006be4: b480 push {r7}
|
|
8006be6: b085 sub sp, #20
|
|
8006be8: af00 add r7, sp, #0
|
|
8006bea: 6078 str r0, [r7, #4]
|
|
8006bec: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006bee: 687b ldr r3, [r7, #4]
|
|
8006bf0: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8006bf2: 683b ldr r3, [r7, #0]
|
|
8006bf4: 781b ldrb r3, [r3, #0]
|
|
8006bf6: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
8006bf8: 683b ldr r3, [r7, #0]
|
|
8006bfa: 785b ldrb r3, [r3, #1]
|
|
8006bfc: 2b01 cmp r3, #1
|
|
8006bfe: d12c bne.n 8006c5a <USB_EPSetStall+0x76>
|
|
{
|
|
if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
|
|
8006c00: 68bb ldr r3, [r7, #8]
|
|
8006c02: 015a lsls r2, r3, #5
|
|
8006c04: 68fb ldr r3, [r7, #12]
|
|
8006c06: 4413 add r3, r2
|
|
8006c08: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006c0c: 681b ldr r3, [r3, #0]
|
|
8006c0e: 2b00 cmp r3, #0
|
|
8006c10: db12 blt.n 8006c38 <USB_EPSetStall+0x54>
|
|
8006c12: 68bb ldr r3, [r7, #8]
|
|
8006c14: 2b00 cmp r3, #0
|
|
8006c16: d00f beq.n 8006c38 <USB_EPSetStall+0x54>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
|
|
8006c18: 68bb ldr r3, [r7, #8]
|
|
8006c1a: 015a lsls r2, r3, #5
|
|
8006c1c: 68fb ldr r3, [r7, #12]
|
|
8006c1e: 4413 add r3, r2
|
|
8006c20: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006c24: 681b ldr r3, [r3, #0]
|
|
8006c26: 68ba ldr r2, [r7, #8]
|
|
8006c28: 0151 lsls r1, r2, #5
|
|
8006c2a: 68fa ldr r2, [r7, #12]
|
|
8006c2c: 440a add r2, r1
|
|
8006c2e: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006c32: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8006c36: 6013 str r3, [r2, #0]
|
|
}
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
|
|
8006c38: 68bb ldr r3, [r7, #8]
|
|
8006c3a: 015a lsls r2, r3, #5
|
|
8006c3c: 68fb ldr r3, [r7, #12]
|
|
8006c3e: 4413 add r3, r2
|
|
8006c40: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006c44: 681b ldr r3, [r3, #0]
|
|
8006c46: 68ba ldr r2, [r7, #8]
|
|
8006c48: 0151 lsls r1, r2, #5
|
|
8006c4a: 68fa ldr r2, [r7, #12]
|
|
8006c4c: 440a add r2, r1
|
|
8006c4e: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006c52: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8006c56: 6013 str r3, [r2, #0]
|
|
8006c58: e02b b.n 8006cb2 <USB_EPSetStall+0xce>
|
|
}
|
|
else
|
|
{
|
|
if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
|
|
8006c5a: 68bb ldr r3, [r7, #8]
|
|
8006c5c: 015a lsls r2, r3, #5
|
|
8006c5e: 68fb ldr r3, [r7, #12]
|
|
8006c60: 4413 add r3, r2
|
|
8006c62: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006c66: 681b ldr r3, [r3, #0]
|
|
8006c68: 2b00 cmp r3, #0
|
|
8006c6a: db12 blt.n 8006c92 <USB_EPSetStall+0xae>
|
|
8006c6c: 68bb ldr r3, [r7, #8]
|
|
8006c6e: 2b00 cmp r3, #0
|
|
8006c70: d00f beq.n 8006c92 <USB_EPSetStall+0xae>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
|
|
8006c72: 68bb ldr r3, [r7, #8]
|
|
8006c74: 015a lsls r2, r3, #5
|
|
8006c76: 68fb ldr r3, [r7, #12]
|
|
8006c78: 4413 add r3, r2
|
|
8006c7a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006c7e: 681b ldr r3, [r3, #0]
|
|
8006c80: 68ba ldr r2, [r7, #8]
|
|
8006c82: 0151 lsls r1, r2, #5
|
|
8006c84: 68fa ldr r2, [r7, #12]
|
|
8006c86: 440a add r2, r1
|
|
8006c88: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006c8c: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8006c90: 6013 str r3, [r2, #0]
|
|
}
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
|
|
8006c92: 68bb ldr r3, [r7, #8]
|
|
8006c94: 015a lsls r2, r3, #5
|
|
8006c96: 68fb ldr r3, [r7, #12]
|
|
8006c98: 4413 add r3, r2
|
|
8006c9a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006c9e: 681b ldr r3, [r3, #0]
|
|
8006ca0: 68ba ldr r2, [r7, #8]
|
|
8006ca2: 0151 lsls r1, r2, #5
|
|
8006ca4: 68fa ldr r2, [r7, #12]
|
|
8006ca6: 440a add r2, r1
|
|
8006ca8: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006cac: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8006cb0: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006cb2: 2300 movs r3, #0
|
|
}
|
|
8006cb4: 4618 mov r0, r3
|
|
8006cb6: 3714 adds r7, #20
|
|
8006cb8: 46bd mov sp, r7
|
|
8006cba: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006cbe: 4770 bx lr
|
|
|
|
08006cc0 <USB_EPClearStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8006cc0: b480 push {r7}
|
|
8006cc2: b085 sub sp, #20
|
|
8006cc4: af00 add r7, sp, #0
|
|
8006cc6: 6078 str r0, [r7, #4]
|
|
8006cc8: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006cca: 687b ldr r3, [r7, #4]
|
|
8006ccc: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8006cce: 683b ldr r3, [r7, #0]
|
|
8006cd0: 781b ldrb r3, [r3, #0]
|
|
8006cd2: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
8006cd4: 683b ldr r3, [r7, #0]
|
|
8006cd6: 785b ldrb r3, [r3, #1]
|
|
8006cd8: 2b01 cmp r3, #1
|
|
8006cda: d128 bne.n 8006d2e <USB_EPClearStall+0x6e>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
|
8006cdc: 68bb ldr r3, [r7, #8]
|
|
8006cde: 015a lsls r2, r3, #5
|
|
8006ce0: 68fb ldr r3, [r7, #12]
|
|
8006ce2: 4413 add r3, r2
|
|
8006ce4: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006ce8: 681b ldr r3, [r3, #0]
|
|
8006cea: 68ba ldr r2, [r7, #8]
|
|
8006cec: 0151 lsls r1, r2, #5
|
|
8006cee: 68fa ldr r2, [r7, #12]
|
|
8006cf0: 440a add r2, r1
|
|
8006cf2: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006cf6: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
8006cfa: 6013 str r3, [r2, #0]
|
|
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
|
|
8006cfc: 683b ldr r3, [r7, #0]
|
|
8006cfe: 791b ldrb r3, [r3, #4]
|
|
8006d00: 2b03 cmp r3, #3
|
|
8006d02: d003 beq.n 8006d0c <USB_EPClearStall+0x4c>
|
|
8006d04: 683b ldr r3, [r7, #0]
|
|
8006d06: 791b ldrb r3, [r3, #4]
|
|
8006d08: 2b02 cmp r3, #2
|
|
8006d0a: d138 bne.n 8006d7e <USB_EPClearStall+0xbe>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
|
|
8006d0c: 68bb ldr r3, [r7, #8]
|
|
8006d0e: 015a lsls r2, r3, #5
|
|
8006d10: 68fb ldr r3, [r7, #12]
|
|
8006d12: 4413 add r3, r2
|
|
8006d14: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006d18: 681b ldr r3, [r3, #0]
|
|
8006d1a: 68ba ldr r2, [r7, #8]
|
|
8006d1c: 0151 lsls r1, r2, #5
|
|
8006d1e: 68fa ldr r2, [r7, #12]
|
|
8006d20: 440a add r2, r1
|
|
8006d22: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006d26: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006d2a: 6013 str r3, [r2, #0]
|
|
8006d2c: e027 b.n 8006d7e <USB_EPClearStall+0xbe>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
|
8006d2e: 68bb ldr r3, [r7, #8]
|
|
8006d30: 015a lsls r2, r3, #5
|
|
8006d32: 68fb ldr r3, [r7, #12]
|
|
8006d34: 4413 add r3, r2
|
|
8006d36: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006d3a: 681b ldr r3, [r3, #0]
|
|
8006d3c: 68ba ldr r2, [r7, #8]
|
|
8006d3e: 0151 lsls r1, r2, #5
|
|
8006d40: 68fa ldr r2, [r7, #12]
|
|
8006d42: 440a add r2, r1
|
|
8006d44: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006d48: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
8006d4c: 6013 str r3, [r2, #0]
|
|
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
|
|
8006d4e: 683b ldr r3, [r7, #0]
|
|
8006d50: 791b ldrb r3, [r3, #4]
|
|
8006d52: 2b03 cmp r3, #3
|
|
8006d54: d003 beq.n 8006d5e <USB_EPClearStall+0x9e>
|
|
8006d56: 683b ldr r3, [r7, #0]
|
|
8006d58: 791b ldrb r3, [r3, #4]
|
|
8006d5a: 2b02 cmp r3, #2
|
|
8006d5c: d10f bne.n 8006d7e <USB_EPClearStall+0xbe>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
|
|
8006d5e: 68bb ldr r3, [r7, #8]
|
|
8006d60: 015a lsls r2, r3, #5
|
|
8006d62: 68fb ldr r3, [r7, #12]
|
|
8006d64: 4413 add r3, r2
|
|
8006d66: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006d6a: 681b ldr r3, [r3, #0]
|
|
8006d6c: 68ba ldr r2, [r7, #8]
|
|
8006d6e: 0151 lsls r1, r2, #5
|
|
8006d70: 68fa ldr r2, [r7, #12]
|
|
8006d72: 440a add r2, r1
|
|
8006d74: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006d78: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006d7c: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8006d7e: 2300 movs r3, #0
|
|
}
|
|
8006d80: 4618 mov r0, r3
|
|
8006d82: 3714 adds r7, #20
|
|
8006d84: 46bd mov sp, r7
|
|
8006d86: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006d8a: 4770 bx lr
|
|
|
|
08006d8c <USB_SetDevAddress>:
|
|
* @param address new device address to be assigned
|
|
* This parameter can be a value from 0 to 255
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
|
|
{
|
|
8006d8c: b480 push {r7}
|
|
8006d8e: b085 sub sp, #20
|
|
8006d90: af00 add r7, sp, #0
|
|
8006d92: 6078 str r0, [r7, #4]
|
|
8006d94: 460b mov r3, r1
|
|
8006d96: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006d98: 687b ldr r3, [r7, #4]
|
|
8006d9a: 60fb str r3, [r7, #12]
|
|
|
|
USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
|
|
8006d9c: 68fb ldr r3, [r7, #12]
|
|
8006d9e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006da2: 681b ldr r3, [r3, #0]
|
|
8006da4: 68fa ldr r2, [r7, #12]
|
|
8006da6: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8006daa: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
|
|
8006dae: 6013 str r3, [r2, #0]
|
|
USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
|
|
8006db0: 68fb ldr r3, [r7, #12]
|
|
8006db2: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006db6: 681a ldr r2, [r3, #0]
|
|
8006db8: 78fb ldrb r3, [r7, #3]
|
|
8006dba: 011b lsls r3, r3, #4
|
|
8006dbc: f403 63fe and.w r3, r3, #2032 @ 0x7f0
|
|
8006dc0: 68f9 ldr r1, [r7, #12]
|
|
8006dc2: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8006dc6: 4313 orrs r3, r2
|
|
8006dc8: 600b str r3, [r1, #0]
|
|
|
|
return HAL_OK;
|
|
8006dca: 2300 movs r3, #0
|
|
}
|
|
8006dcc: 4618 mov r0, r3
|
|
8006dce: 3714 adds r7, #20
|
|
8006dd0: 46bd mov sp, r7
|
|
8006dd2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006dd6: 4770 bx lr
|
|
|
|
08006dd8 <USB_DevConnect>:
|
|
* @brief USB_DevConnect : Connect the USB device by enabling Rpu
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006dd8: b480 push {r7}
|
|
8006dda: b085 sub sp, #20
|
|
8006ddc: af00 add r7, sp, #0
|
|
8006dde: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006de0: 687b ldr r3, [r7, #4]
|
|
8006de2: 60fb str r3, [r7, #12]
|
|
|
|
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
|
|
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
|
|
8006de4: 68fb ldr r3, [r7, #12]
|
|
8006de6: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
8006dea: 681b ldr r3, [r3, #0]
|
|
8006dec: 68fa ldr r2, [r7, #12]
|
|
8006dee: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
8006df2: f023 0303 bic.w r3, r3, #3
|
|
8006df6: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
|
|
8006df8: 68fb ldr r3, [r7, #12]
|
|
8006dfa: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006dfe: 685b ldr r3, [r3, #4]
|
|
8006e00: 68fa ldr r2, [r7, #12]
|
|
8006e02: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8006e06: f023 0302 bic.w r3, r3, #2
|
|
8006e0a: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
8006e0c: 2300 movs r3, #0
|
|
}
|
|
8006e0e: 4618 mov r0, r3
|
|
8006e10: 3714 adds r7, #20
|
|
8006e12: 46bd mov sp, r7
|
|
8006e14: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006e18: 4770 bx lr
|
|
|
|
08006e1a <USB_DevDisconnect>:
|
|
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006e1a: b480 push {r7}
|
|
8006e1c: b085 sub sp, #20
|
|
8006e1e: af00 add r7, sp, #0
|
|
8006e20: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006e22: 687b ldr r3, [r7, #4]
|
|
8006e24: 60fb str r3, [r7, #12]
|
|
|
|
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
|
|
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
|
|
8006e26: 68fb ldr r3, [r7, #12]
|
|
8006e28: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
8006e2c: 681b ldr r3, [r3, #0]
|
|
8006e2e: 68fa ldr r2, [r7, #12]
|
|
8006e30: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
8006e34: f023 0303 bic.w r3, r3, #3
|
|
8006e38: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
8006e3a: 68fb ldr r3, [r7, #12]
|
|
8006e3c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006e40: 685b ldr r3, [r3, #4]
|
|
8006e42: 68fa ldr r2, [r7, #12]
|
|
8006e44: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8006e48: f043 0302 orr.w r3, r3, #2
|
|
8006e4c: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
8006e4e: 2300 movs r3, #0
|
|
}
|
|
8006e50: 4618 mov r0, r3
|
|
8006e52: 3714 adds r7, #20
|
|
8006e54: 46bd mov sp, r7
|
|
8006e56: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006e5a: 4770 bx lr
|
|
|
|
08006e5c <USB_ReadInterrupts>:
|
|
* @brief USB_ReadInterrupts: return the global USB interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Global Interrupt status
|
|
*/
|
|
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
|
|
{
|
|
8006e5c: b480 push {r7}
|
|
8006e5e: b085 sub sp, #20
|
|
8006e60: af00 add r7, sp, #0
|
|
8006e62: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx->GINTSTS;
|
|
8006e64: 687b ldr r3, [r7, #4]
|
|
8006e66: 695b ldr r3, [r3, #20]
|
|
8006e68: 60fb str r3, [r7, #12]
|
|
tmpreg &= USBx->GINTMSK;
|
|
8006e6a: 687b ldr r3, [r7, #4]
|
|
8006e6c: 699b ldr r3, [r3, #24]
|
|
8006e6e: 68fa ldr r2, [r7, #12]
|
|
8006e70: 4013 ands r3, r2
|
|
8006e72: 60fb str r3, [r7, #12]
|
|
|
|
return tmpreg;
|
|
8006e74: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8006e76: 4618 mov r0, r3
|
|
8006e78: 3714 adds r7, #20
|
|
8006e7a: 46bd mov sp, r7
|
|
8006e7c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006e80: 4770 bx lr
|
|
|
|
08006e82 <USB_ReadDevAllOutEpInterrupt>:
|
|
* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Device OUT EP interrupt status
|
|
*/
|
|
uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006e82: b480 push {r7}
|
|
8006e84: b085 sub sp, #20
|
|
8006e86: af00 add r7, sp, #0
|
|
8006e88: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006e8a: 687b ldr r3, [r7, #4]
|
|
8006e8c: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_DEVICE->DAINT;
|
|
8006e8e: 68fb ldr r3, [r7, #12]
|
|
8006e90: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006e94: 699b ldr r3, [r3, #24]
|
|
8006e96: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DAINTMSK;
|
|
8006e98: 68fb ldr r3, [r7, #12]
|
|
8006e9a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006e9e: 69db ldr r3, [r3, #28]
|
|
8006ea0: 68ba ldr r2, [r7, #8]
|
|
8006ea2: 4013 ands r3, r2
|
|
8006ea4: 60bb str r3, [r7, #8]
|
|
|
|
return ((tmpreg & 0xffff0000U) >> 16);
|
|
8006ea6: 68bb ldr r3, [r7, #8]
|
|
8006ea8: 0c1b lsrs r3, r3, #16
|
|
}
|
|
8006eaa: 4618 mov r0, r3
|
|
8006eac: 3714 adds r7, #20
|
|
8006eae: 46bd mov sp, r7
|
|
8006eb0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006eb4: 4770 bx lr
|
|
|
|
08006eb6 <USB_ReadDevAllInEpInterrupt>:
|
|
* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Device IN EP interrupt status
|
|
*/
|
|
uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006eb6: b480 push {r7}
|
|
8006eb8: b085 sub sp, #20
|
|
8006eba: af00 add r7, sp, #0
|
|
8006ebc: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006ebe: 687b ldr r3, [r7, #4]
|
|
8006ec0: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_DEVICE->DAINT;
|
|
8006ec2: 68fb ldr r3, [r7, #12]
|
|
8006ec4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006ec8: 699b ldr r3, [r3, #24]
|
|
8006eca: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DAINTMSK;
|
|
8006ecc: 68fb ldr r3, [r7, #12]
|
|
8006ece: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006ed2: 69db ldr r3, [r3, #28]
|
|
8006ed4: 68ba ldr r2, [r7, #8]
|
|
8006ed6: 4013 ands r3, r2
|
|
8006ed8: 60bb str r3, [r7, #8]
|
|
|
|
return ((tmpreg & 0xFFFFU));
|
|
8006eda: 68bb ldr r3, [r7, #8]
|
|
8006edc: b29b uxth r3, r3
|
|
}
|
|
8006ede: 4618 mov r0, r3
|
|
8006ee0: 3714 adds r7, #20
|
|
8006ee2: 46bd mov sp, r7
|
|
8006ee4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006ee8: 4770 bx lr
|
|
|
|
08006eea <USB_ReadDevOutEPInterrupt>:
|
|
* @param epnum endpoint number
|
|
* This parameter can be a value from 0 to 15
|
|
* @retval Device OUT EP Interrupt register
|
|
*/
|
|
uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
|
|
{
|
|
8006eea: b480 push {r7}
|
|
8006eec: b085 sub sp, #20
|
|
8006eee: af00 add r7, sp, #0
|
|
8006ef0: 6078 str r0, [r7, #4]
|
|
8006ef2: 460b mov r3, r1
|
|
8006ef4: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006ef6: 687b ldr r3, [r7, #4]
|
|
8006ef8: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
|
|
8006efa: 78fb ldrb r3, [r7, #3]
|
|
8006efc: 015a lsls r2, r3, #5
|
|
8006efe: 68fb ldr r3, [r7, #12]
|
|
8006f00: 4413 add r3, r2
|
|
8006f02: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006f06: 689b ldr r3, [r3, #8]
|
|
8006f08: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DOEPMSK;
|
|
8006f0a: 68fb ldr r3, [r7, #12]
|
|
8006f0c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006f10: 695b ldr r3, [r3, #20]
|
|
8006f12: 68ba ldr r2, [r7, #8]
|
|
8006f14: 4013 ands r3, r2
|
|
8006f16: 60bb str r3, [r7, #8]
|
|
|
|
return tmpreg;
|
|
8006f18: 68bb ldr r3, [r7, #8]
|
|
}
|
|
8006f1a: 4618 mov r0, r3
|
|
8006f1c: 3714 adds r7, #20
|
|
8006f1e: 46bd mov sp, r7
|
|
8006f20: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f24: 4770 bx lr
|
|
|
|
08006f26 <USB_ReadDevInEPInterrupt>:
|
|
* @param epnum endpoint number
|
|
* This parameter can be a value from 0 to 15
|
|
* @retval Device IN EP Interrupt register
|
|
*/
|
|
uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
|
|
{
|
|
8006f26: b480 push {r7}
|
|
8006f28: b087 sub sp, #28
|
|
8006f2a: af00 add r7, sp, #0
|
|
8006f2c: 6078 str r0, [r7, #4]
|
|
8006f2e: 460b mov r3, r1
|
|
8006f30: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006f32: 687b ldr r3, [r7, #4]
|
|
8006f34: 617b str r3, [r7, #20]
|
|
uint32_t tmpreg;
|
|
uint32_t msk;
|
|
uint32_t emp;
|
|
|
|
msk = USBx_DEVICE->DIEPMSK;
|
|
8006f36: 697b ldr r3, [r7, #20]
|
|
8006f38: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006f3c: 691b ldr r3, [r3, #16]
|
|
8006f3e: 613b str r3, [r7, #16]
|
|
emp = USBx_DEVICE->DIEPEMPMSK;
|
|
8006f40: 697b ldr r3, [r7, #20]
|
|
8006f42: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006f46: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8006f48: 60fb str r3, [r7, #12]
|
|
msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
|
|
8006f4a: 78fb ldrb r3, [r7, #3]
|
|
8006f4c: f003 030f and.w r3, r3, #15
|
|
8006f50: 68fa ldr r2, [r7, #12]
|
|
8006f52: fa22 f303 lsr.w r3, r2, r3
|
|
8006f56: 01db lsls r3, r3, #7
|
|
8006f58: b2db uxtb r3, r3
|
|
8006f5a: 693a ldr r2, [r7, #16]
|
|
8006f5c: 4313 orrs r3, r2
|
|
8006f5e: 613b str r3, [r7, #16]
|
|
tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
|
|
8006f60: 78fb ldrb r3, [r7, #3]
|
|
8006f62: 015a lsls r2, r3, #5
|
|
8006f64: 697b ldr r3, [r7, #20]
|
|
8006f66: 4413 add r3, r2
|
|
8006f68: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006f6c: 689b ldr r3, [r3, #8]
|
|
8006f6e: 693a ldr r2, [r7, #16]
|
|
8006f70: 4013 ands r3, r2
|
|
8006f72: 60bb str r3, [r7, #8]
|
|
|
|
return tmpreg;
|
|
8006f74: 68bb ldr r3, [r7, #8]
|
|
}
|
|
8006f76: 4618 mov r0, r3
|
|
8006f78: 371c adds r7, #28
|
|
8006f7a: 46bd mov sp, r7
|
|
8006f7c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f80: 4770 bx lr
|
|
|
|
08006f82 <USB_GetMode>:
|
|
* This parameter can be one of these values:
|
|
* 1 : Host
|
|
* 0 : Device
|
|
*/
|
|
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006f82: b480 push {r7}
|
|
8006f84: b083 sub sp, #12
|
|
8006f86: af00 add r7, sp, #0
|
|
8006f88: 6078 str r0, [r7, #4]
|
|
return ((USBx->GINTSTS) & 0x1U);
|
|
8006f8a: 687b ldr r3, [r7, #4]
|
|
8006f8c: 695b ldr r3, [r3, #20]
|
|
8006f8e: f003 0301 and.w r3, r3, #1
|
|
}
|
|
8006f92: 4618 mov r0, r3
|
|
8006f94: 370c adds r7, #12
|
|
8006f96: 46bd mov sp, r7
|
|
8006f98: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f9c: 4770 bx lr
|
|
|
|
08006f9e <USB_ActivateSetup>:
|
|
* @brief Activate EP0 for Setup transactions
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006f9e: b480 push {r7}
|
|
8006fa0: b085 sub sp, #20
|
|
8006fa2: af00 add r7, sp, #0
|
|
8006fa4: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006fa6: 687b ldr r3, [r7, #4]
|
|
8006fa8: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the MPS of the IN EP0 to 64 bytes */
|
|
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
|
|
8006faa: 68fb ldr r3, [r7, #12]
|
|
8006fac: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006fb0: 681b ldr r3, [r3, #0]
|
|
8006fb2: 68fa ldr r2, [r7, #12]
|
|
8006fb4: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006fb8: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
|
|
8006fbc: f023 0307 bic.w r3, r3, #7
|
|
8006fc0: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
|
|
8006fc2: 68fb ldr r3, [r7, #12]
|
|
8006fc4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006fc8: 685b ldr r3, [r3, #4]
|
|
8006fca: 68fa ldr r2, [r7, #12]
|
|
8006fcc: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8006fd0: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8006fd4: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
8006fd6: 2300 movs r3, #0
|
|
}
|
|
8006fd8: 4618 mov r0, r3
|
|
8006fda: 3714 adds r7, #20
|
|
8006fdc: 46bd mov sp, r7
|
|
8006fde: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006fe2: 4770 bx lr
|
|
|
|
08006fe4 <USB_EP0_OutStart>:
|
|
* 1 : DMA feature used
|
|
* @param psetup pointer to setup packet
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup)
|
|
{
|
|
8006fe4: b480 push {r7}
|
|
8006fe6: b087 sub sp, #28
|
|
8006fe8: af00 add r7, sp, #0
|
|
8006fea: 60f8 str r0, [r7, #12]
|
|
8006fec: 460b mov r3, r1
|
|
8006fee: 607a str r2, [r7, #4]
|
|
8006ff0: 72fb strb r3, [r7, #11]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006ff2: 68fb ldr r3, [r7, #12]
|
|
8006ff4: 617b str r3, [r7, #20]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
8006ff6: 68fb ldr r3, [r7, #12]
|
|
8006ff8: 333c adds r3, #60 @ 0x3c
|
|
8006ffa: 3304 adds r3, #4
|
|
8006ffc: 681b ldr r3, [r3, #0]
|
|
8006ffe: 613b str r3, [r7, #16]
|
|
|
|
if (gSNPSiD > USB_OTG_CORE_ID_300A)
|
|
8007000: 693b ldr r3, [r7, #16]
|
|
8007002: 4a26 ldr r2, [pc, #152] @ (800709c <USB_EP0_OutStart+0xb8>)
|
|
8007004: 4293 cmp r3, r2
|
|
8007006: d90a bls.n 800701e <USB_EP0_OutStart+0x3a>
|
|
{
|
|
if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
8007008: 697b ldr r3, [r7, #20]
|
|
800700a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800700e: 681b ldr r3, [r3, #0]
|
|
8007010: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007014: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8007018: d101 bne.n 800701e <USB_EP0_OutStart+0x3a>
|
|
{
|
|
return HAL_OK;
|
|
800701a: 2300 movs r3, #0
|
|
800701c: e037 b.n 800708e <USB_EP0_OutStart+0xaa>
|
|
}
|
|
}
|
|
|
|
USBx_OUTEP(0U)->DOEPTSIZ = 0U;
|
|
800701e: 697b ldr r3, [r7, #20]
|
|
8007020: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007024: 461a mov r2, r3
|
|
8007026: 2300 movs r3, #0
|
|
8007028: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
800702a: 697b ldr r3, [r7, #20]
|
|
800702c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007030: 691b ldr r3, [r3, #16]
|
|
8007032: 697a ldr r2, [r7, #20]
|
|
8007034: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007038: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
800703c: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
|
|
800703e: 697b ldr r3, [r7, #20]
|
|
8007040: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007044: 691b ldr r3, [r3, #16]
|
|
8007046: 697a ldr r2, [r7, #20]
|
|
8007048: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800704c: f043 0318 orr.w r3, r3, #24
|
|
8007050: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
|
|
8007052: 697b ldr r3, [r7, #20]
|
|
8007054: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007058: 691b ldr r3, [r3, #16]
|
|
800705a: 697a ldr r2, [r7, #20]
|
|
800705c: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007060: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000
|
|
8007064: 6113 str r3, [r2, #16]
|
|
|
|
if (dma == 1U)
|
|
8007066: 7afb ldrb r3, [r7, #11]
|
|
8007068: 2b01 cmp r3, #1
|
|
800706a: d10f bne.n 800708c <USB_EP0_OutStart+0xa8>
|
|
{
|
|
USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
|
|
800706c: 697b ldr r3, [r7, #20]
|
|
800706e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007072: 461a mov r2, r3
|
|
8007074: 687b ldr r3, [r7, #4]
|
|
8007076: 6153 str r3, [r2, #20]
|
|
/* EP enable */
|
|
USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
|
|
8007078: 697b ldr r3, [r7, #20]
|
|
800707a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800707e: 681b ldr r3, [r3, #0]
|
|
8007080: 697a ldr r2, [r7, #20]
|
|
8007082: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007086: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000
|
|
800708a: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
800708c: 2300 movs r3, #0
|
|
}
|
|
800708e: 4618 mov r0, r3
|
|
8007090: 371c adds r7, #28
|
|
8007092: 46bd mov sp, r7
|
|
8007094: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007098: 4770 bx lr
|
|
800709a: bf00 nop
|
|
800709c: 4f54300a .word 0x4f54300a
|
|
|
|
080070a0 <USB_CoreReset>:
|
|
* @brief Reset the USB Core (needed after USB clock settings change)
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80070a0: b480 push {r7}
|
|
80070a2: b085 sub sp, #20
|
|
80070a4: af00 add r7, sp, #0
|
|
80070a6: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
80070a8: 2300 movs r3, #0
|
|
80070aa: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
80070ac: 68fb ldr r3, [r7, #12]
|
|
80070ae: 3301 adds r3, #1
|
|
80070b0: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80070b2: 68fb ldr r3, [r7, #12]
|
|
80070b4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80070b8: d901 bls.n 80070be <USB_CoreReset+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80070ba: 2303 movs r3, #3
|
|
80070bc: e022 b.n 8007104 <USB_CoreReset+0x64>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
80070be: 687b ldr r3, [r7, #4]
|
|
80070c0: 691b ldr r3, [r3, #16]
|
|
80070c2: 2b00 cmp r3, #0
|
|
80070c4: daf2 bge.n 80070ac <USB_CoreReset+0xc>
|
|
|
|
count = 10U;
|
|
80070c6: 230a movs r3, #10
|
|
80070c8: 60fb str r3, [r7, #12]
|
|
|
|
/* few cycles before setting core reset */
|
|
while (count > 0U)
|
|
80070ca: e002 b.n 80070d2 <USB_CoreReset+0x32>
|
|
{
|
|
count--;
|
|
80070cc: 68fb ldr r3, [r7, #12]
|
|
80070ce: 3b01 subs r3, #1
|
|
80070d0: 60fb str r3, [r7, #12]
|
|
while (count > 0U)
|
|
80070d2: 68fb ldr r3, [r7, #12]
|
|
80070d4: 2b00 cmp r3, #0
|
|
80070d6: d1f9 bne.n 80070cc <USB_CoreReset+0x2c>
|
|
}
|
|
|
|
/* Core Soft Reset */
|
|
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
|
|
80070d8: 687b ldr r3, [r7, #4]
|
|
80070da: 691b ldr r3, [r3, #16]
|
|
80070dc: f043 0201 orr.w r2, r3, #1
|
|
80070e0: 687b ldr r3, [r7, #4]
|
|
80070e2: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
80070e4: 68fb ldr r3, [r7, #12]
|
|
80070e6: 3301 adds r3, #1
|
|
80070e8: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80070ea: 68fb ldr r3, [r7, #12]
|
|
80070ec: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80070f0: d901 bls.n 80070f6 <USB_CoreReset+0x56>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80070f2: 2303 movs r3, #3
|
|
80070f4: e006 b.n 8007104 <USB_CoreReset+0x64>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
|
|
80070f6: 687b ldr r3, [r7, #4]
|
|
80070f8: 691b ldr r3, [r3, #16]
|
|
80070fa: f003 0301 and.w r3, r3, #1
|
|
80070fe: 2b01 cmp r3, #1
|
|
8007100: d0f0 beq.n 80070e4 <USB_CoreReset+0x44>
|
|
|
|
return HAL_OK;
|
|
8007102: 2300 movs r3, #0
|
|
}
|
|
8007104: 4618 mov r0, r3
|
|
8007106: 3714 adds r7, #20
|
|
8007108: 46bd mov sp, r7
|
|
800710a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800710e: 4770 bx lr
|
|
|
|
08007110 <USBD_HID_Init>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8007110: b580 push {r7, lr}
|
|
8007112: b084 sub sp, #16
|
|
8007114: af00 add r7, sp, #0
|
|
8007116: 6078 str r0, [r7, #4]
|
|
8007118: 460b mov r3, r1
|
|
800711a: 70fb strb r3, [r7, #3]
|
|
UNUSED(cfgidx);
|
|
|
|
USBD_HID_HandleTypeDef *hhid;
|
|
|
|
hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef));
|
|
800711c: 2010 movs r0, #16
|
|
800711e: f002 f9f7 bl 8009510 <USBD_static_malloc>
|
|
8007122: 60f8 str r0, [r7, #12]
|
|
|
|
if (hhid == NULL)
|
|
8007124: 68fb ldr r3, [r7, #12]
|
|
8007126: 2b00 cmp r3, #0
|
|
8007128: d109 bne.n 800713e <USBD_HID_Init+0x2e>
|
|
{
|
|
pdev->pClassDataCmsit[pdev->classId] = NULL;
|
|
800712a: 687b ldr r3, [r7, #4]
|
|
800712c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007130: 687b ldr r3, [r7, #4]
|
|
8007132: 32b0 adds r2, #176 @ 0xb0
|
|
8007134: 2100 movs r1, #0
|
|
8007136: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
return (uint8_t)USBD_EMEM;
|
|
800713a: 2302 movs r3, #2
|
|
800713c: e048 b.n 80071d0 <USBD_HID_Init+0xc0>
|
|
}
|
|
|
|
pdev->pClassDataCmsit[pdev->classId] = (void *)hhid;
|
|
800713e: 687b ldr r3, [r7, #4]
|
|
8007140: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007144: 687b ldr r3, [r7, #4]
|
|
8007146: 32b0 adds r2, #176 @ 0xb0
|
|
8007148: 68f9 ldr r1, [r7, #12]
|
|
800714a: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
|
|
800714e: 687b ldr r3, [r7, #4]
|
|
8007150: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007154: 687b ldr r3, [r7, #4]
|
|
8007156: 32b0 adds r2, #176 @ 0xb0
|
|
8007158: f853 2022 ldr.w r2, [r3, r2, lsl #2]
|
|
800715c: 687b ldr r3, [r7, #4]
|
|
800715e: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
|
|
#ifdef USE_USBD_COMPOSITE
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8007162: 687b ldr r3, [r7, #4]
|
|
8007164: 7c1b ldrb r3, [r3, #16]
|
|
8007166: 2b00 cmp r3, #0
|
|
8007168: d10d bne.n 8007186 <USBD_HID_Init+0x76>
|
|
{
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL;
|
|
800716a: 4b1b ldr r3, [pc, #108] @ (80071d8 <USBD_HID_Init+0xc8>)
|
|
800716c: 781b ldrb r3, [r3, #0]
|
|
800716e: f003 020f and.w r2, r3, #15
|
|
8007172: 6879 ldr r1, [r7, #4]
|
|
8007174: 4613 mov r3, r2
|
|
8007176: 009b lsls r3, r3, #2
|
|
8007178: 4413 add r3, r2
|
|
800717a: 009b lsls r3, r3, #2
|
|
800717c: 440b add r3, r1
|
|
800717e: 331c adds r3, #28
|
|
8007180: 2207 movs r2, #7
|
|
8007182: 601a str r2, [r3, #0]
|
|
8007184: e00c b.n 80071a0 <USBD_HID_Init+0x90>
|
|
}
|
|
else /* LOW and FULL-speed endpoints */
|
|
{
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL;
|
|
8007186: 4b14 ldr r3, [pc, #80] @ (80071d8 <USBD_HID_Init+0xc8>)
|
|
8007188: 781b ldrb r3, [r3, #0]
|
|
800718a: f003 020f and.w r2, r3, #15
|
|
800718e: 6879 ldr r1, [r7, #4]
|
|
8007190: 4613 mov r3, r2
|
|
8007192: 009b lsls r3, r3, #2
|
|
8007194: 4413 add r3, r2
|
|
8007196: 009b lsls r3, r3, #2
|
|
8007198: 440b add r3, r1
|
|
800719a: 331c adds r3, #28
|
|
800719c: 220a movs r2, #10
|
|
800719e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Open EP IN */
|
|
(void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE);
|
|
80071a0: 4b0d ldr r3, [pc, #52] @ (80071d8 <USBD_HID_Init+0xc8>)
|
|
80071a2: 7819 ldrb r1, [r3, #0]
|
|
80071a4: 230e movs r3, #14
|
|
80071a6: 2203 movs r2, #3
|
|
80071a8: 6878 ldr r0, [r7, #4]
|
|
80071aa: f002 f852 bl 8009252 <USBD_LL_OpenEP>
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U;
|
|
80071ae: 4b0a ldr r3, [pc, #40] @ (80071d8 <USBD_HID_Init+0xc8>)
|
|
80071b0: 781b ldrb r3, [r3, #0]
|
|
80071b2: f003 020f and.w r2, r3, #15
|
|
80071b6: 6879 ldr r1, [r7, #4]
|
|
80071b8: 4613 mov r3, r2
|
|
80071ba: 009b lsls r3, r3, #2
|
|
80071bc: 4413 add r3, r2
|
|
80071be: 009b lsls r3, r3, #2
|
|
80071c0: 440b add r3, r1
|
|
80071c2: 3323 adds r3, #35 @ 0x23
|
|
80071c4: 2201 movs r2, #1
|
|
80071c6: 701a strb r2, [r3, #0]
|
|
|
|
hhid->state = USBD_HID_IDLE;
|
|
80071c8: 68fb ldr r3, [r7, #12]
|
|
80071ca: 2200 movs r2, #0
|
|
80071cc: 731a strb r2, [r3, #12]
|
|
|
|
return (uint8_t)USBD_OK;
|
|
80071ce: 2300 movs r3, #0
|
|
}
|
|
80071d0: 4618 mov r0, r3
|
|
80071d2: 3710 adds r7, #16
|
|
80071d4: 46bd mov sp, r7
|
|
80071d6: bd80 pop {r7, pc}
|
|
80071d8: 20000125 .word 0x20000125
|
|
|
|
080071dc <USBD_HID_DeInit>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
80071dc: b580 push {r7, lr}
|
|
80071de: b082 sub sp, #8
|
|
80071e0: af00 add r7, sp, #0
|
|
80071e2: 6078 str r0, [r7, #4]
|
|
80071e4: 460b mov r3, r1
|
|
80071e6: 70fb strb r3, [r7, #3]
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Close HID EPs */
|
|
(void)USBD_LL_CloseEP(pdev, HIDInEpAdd);
|
|
80071e8: 4b1f ldr r3, [pc, #124] @ (8007268 <USBD_HID_DeInit+0x8c>)
|
|
80071ea: 781b ldrb r3, [r3, #0]
|
|
80071ec: 4619 mov r1, r3
|
|
80071ee: 6878 ldr r0, [r7, #4]
|
|
80071f0: f002 f855 bl 800929e <USBD_LL_CloseEP>
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U;
|
|
80071f4: 4b1c ldr r3, [pc, #112] @ (8007268 <USBD_HID_DeInit+0x8c>)
|
|
80071f6: 781b ldrb r3, [r3, #0]
|
|
80071f8: f003 020f and.w r2, r3, #15
|
|
80071fc: 6879 ldr r1, [r7, #4]
|
|
80071fe: 4613 mov r3, r2
|
|
8007200: 009b lsls r3, r3, #2
|
|
8007202: 4413 add r3, r2
|
|
8007204: 009b lsls r3, r3, #2
|
|
8007206: 440b add r3, r1
|
|
8007208: 3323 adds r3, #35 @ 0x23
|
|
800720a: 2200 movs r2, #0
|
|
800720c: 701a strb r2, [r3, #0]
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U;
|
|
800720e: 4b16 ldr r3, [pc, #88] @ (8007268 <USBD_HID_DeInit+0x8c>)
|
|
8007210: 781b ldrb r3, [r3, #0]
|
|
8007212: f003 020f and.w r2, r3, #15
|
|
8007216: 6879 ldr r1, [r7, #4]
|
|
8007218: 4613 mov r3, r2
|
|
800721a: 009b lsls r3, r3, #2
|
|
800721c: 4413 add r3, r2
|
|
800721e: 009b lsls r3, r3, #2
|
|
8007220: 440b add r3, r1
|
|
8007222: 331c adds r3, #28
|
|
8007224: 2200 movs r2, #0
|
|
8007226: 601a str r2, [r3, #0]
|
|
|
|
/* Free allocated memory */
|
|
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
|
|
8007228: 687b ldr r3, [r7, #4]
|
|
800722a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800722e: 687b ldr r3, [r7, #4]
|
|
8007230: 32b0 adds r2, #176 @ 0xb0
|
|
8007232: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007236: 2b00 cmp r3, #0
|
|
8007238: d011 beq.n 800725e <USBD_HID_DeInit+0x82>
|
|
{
|
|
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
|
|
800723a: 687b ldr r3, [r7, #4]
|
|
800723c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007240: 687b ldr r3, [r7, #4]
|
|
8007242: 32b0 adds r2, #176 @ 0xb0
|
|
8007244: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007248: 4618 mov r0, r3
|
|
800724a: f002 f96f bl 800952c <USBD_static_free>
|
|
pdev->pClassDataCmsit[pdev->classId] = NULL;
|
|
800724e: 687b ldr r3, [r7, #4]
|
|
8007250: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007254: 687b ldr r3, [r7, #4]
|
|
8007256: 32b0 adds r2, #176 @ 0xb0
|
|
8007258: 2100 movs r1, #0
|
|
800725a: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
800725e: 2300 movs r3, #0
|
|
}
|
|
8007260: 4618 mov r0, r3
|
|
8007262: 3708 adds r7, #8
|
|
8007264: 46bd mov sp, r7
|
|
8007266: bd80 pop {r7, pc}
|
|
8007268: 20000125 .word 0x20000125
|
|
|
|
0800726c <USBD_HID_Setup>:
|
|
* @param pdev: instance
|
|
* @param req: usb requests
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
800726c: b580 push {r7, lr}
|
|
800726e: b086 sub sp, #24
|
|
8007270: af00 add r7, sp, #0
|
|
8007272: 6078 str r0, [r7, #4]
|
|
8007274: 6039 str r1, [r7, #0]
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
8007276: 687b ldr r3, [r7, #4]
|
|
8007278: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800727c: 687b ldr r3, [r7, #4]
|
|
800727e: 32b0 adds r2, #176 @ 0xb0
|
|
8007280: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007284: 60fb str r3, [r7, #12]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007286: 2300 movs r3, #0
|
|
8007288: 75fb strb r3, [r7, #23]
|
|
uint16_t len;
|
|
uint8_t *pbuf;
|
|
uint16_t status_info = 0U;
|
|
800728a: 2300 movs r3, #0
|
|
800728c: 817b strh r3, [r7, #10]
|
|
|
|
if (hhid == NULL)
|
|
800728e: 68fb ldr r3, [r7, #12]
|
|
8007290: 2b00 cmp r3, #0
|
|
8007292: d101 bne.n 8007298 <USBD_HID_Setup+0x2c>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
8007294: 2303 movs r3, #3
|
|
8007296: e0e8 b.n 800746a <USBD_HID_Setup+0x1fe>
|
|
}
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8007298: 683b ldr r3, [r7, #0]
|
|
800729a: 781b ldrb r3, [r3, #0]
|
|
800729c: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
80072a0: 2b00 cmp r3, #0
|
|
80072a2: d046 beq.n 8007332 <USBD_HID_Setup+0xc6>
|
|
80072a4: 2b20 cmp r3, #32
|
|
80072a6: f040 80d8 bne.w 800745a <USBD_HID_Setup+0x1ee>
|
|
{
|
|
case USB_REQ_TYPE_CLASS :
|
|
switch (req->bRequest)
|
|
80072aa: 683b ldr r3, [r7, #0]
|
|
80072ac: 785b ldrb r3, [r3, #1]
|
|
80072ae: 3b02 subs r3, #2
|
|
80072b0: 2b09 cmp r3, #9
|
|
80072b2: d836 bhi.n 8007322 <USBD_HID_Setup+0xb6>
|
|
80072b4: a201 add r2, pc, #4 @ (adr r2, 80072bc <USBD_HID_Setup+0x50>)
|
|
80072b6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80072ba: bf00 nop
|
|
80072bc: 08007313 .word 0x08007313
|
|
80072c0: 080072f3 .word 0x080072f3
|
|
80072c4: 08007323 .word 0x08007323
|
|
80072c8: 08007323 .word 0x08007323
|
|
80072cc: 08007323 .word 0x08007323
|
|
80072d0: 08007323 .word 0x08007323
|
|
80072d4: 08007323 .word 0x08007323
|
|
80072d8: 08007323 .word 0x08007323
|
|
80072dc: 08007301 .word 0x08007301
|
|
80072e0: 080072e5 .word 0x080072e5
|
|
{
|
|
case USBD_HID_REQ_SET_PROTOCOL:
|
|
hhid->Protocol = (uint8_t)(req->wValue);
|
|
80072e4: 683b ldr r3, [r7, #0]
|
|
80072e6: 885b ldrh r3, [r3, #2]
|
|
80072e8: b2db uxtb r3, r3
|
|
80072ea: 461a mov r2, r3
|
|
80072ec: 68fb ldr r3, [r7, #12]
|
|
80072ee: 601a str r2, [r3, #0]
|
|
break;
|
|
80072f0: e01e b.n 8007330 <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_GET_PROTOCOL:
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U);
|
|
80072f2: 68fb ldr r3, [r7, #12]
|
|
80072f4: 2201 movs r2, #1
|
|
80072f6: 4619 mov r1, r3
|
|
80072f8: 6878 ldr r0, [r7, #4]
|
|
80072fa: f001 fc39 bl 8008b70 <USBD_CtlSendData>
|
|
break;
|
|
80072fe: e017 b.n 8007330 <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_SET_IDLE:
|
|
hhid->IdleState = (uint8_t)(req->wValue >> 8);
|
|
8007300: 683b ldr r3, [r7, #0]
|
|
8007302: 885b ldrh r3, [r3, #2]
|
|
8007304: 0a1b lsrs r3, r3, #8
|
|
8007306: b29b uxth r3, r3
|
|
8007308: b2db uxtb r3, r3
|
|
800730a: 461a mov r2, r3
|
|
800730c: 68fb ldr r3, [r7, #12]
|
|
800730e: 605a str r2, [r3, #4]
|
|
break;
|
|
8007310: e00e b.n 8007330 <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_GET_IDLE:
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U);
|
|
8007312: 68fb ldr r3, [r7, #12]
|
|
8007314: 3304 adds r3, #4
|
|
8007316: 2201 movs r2, #1
|
|
8007318: 4619 mov r1, r3
|
|
800731a: 6878 ldr r0, [r7, #4]
|
|
800731c: f001 fc28 bl 8008b70 <USBD_CtlSendData>
|
|
break;
|
|
8007320: e006 b.n 8007330 <USBD_HID_Setup+0xc4>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007322: 6839 ldr r1, [r7, #0]
|
|
8007324: 6878 ldr r0, [r7, #4]
|
|
8007326: f001 fba6 bl 8008a76 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
800732a: 2303 movs r3, #3
|
|
800732c: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800732e: bf00 nop
|
|
}
|
|
break;
|
|
8007330: e09a b.n 8007468 <USBD_HID_Setup+0x1fc>
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
8007332: 683b ldr r3, [r7, #0]
|
|
8007334: 785b ldrb r3, [r3, #1]
|
|
8007336: 2b0b cmp r3, #11
|
|
8007338: f200 8086 bhi.w 8007448 <USBD_HID_Setup+0x1dc>
|
|
800733c: a201 add r2, pc, #4 @ (adr r2, 8007344 <USBD_HID_Setup+0xd8>)
|
|
800733e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8007342: bf00 nop
|
|
8007344: 08007375 .word 0x08007375
|
|
8007348: 08007457 .word 0x08007457
|
|
800734c: 08007449 .word 0x08007449
|
|
8007350: 08007449 .word 0x08007449
|
|
8007354: 08007449 .word 0x08007449
|
|
8007358: 08007449 .word 0x08007449
|
|
800735c: 0800739f .word 0x0800739f
|
|
8007360: 08007449 .word 0x08007449
|
|
8007364: 08007449 .word 0x08007449
|
|
8007368: 08007449 .word 0x08007449
|
|
800736c: 080073f7 .word 0x080073f7
|
|
8007370: 08007421 .word 0x08007421
|
|
{
|
|
case USB_REQ_GET_STATUS:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007374: 687b ldr r3, [r7, #4]
|
|
8007376: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
800737a: b2db uxtb r3, r3
|
|
800737c: 2b03 cmp r3, #3
|
|
800737e: d107 bne.n 8007390 <USBD_HID_Setup+0x124>
|
|
{
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
|
|
8007380: f107 030a add.w r3, r7, #10
|
|
8007384: 2202 movs r2, #2
|
|
8007386: 4619 mov r1, r3
|
|
8007388: 6878 ldr r0, [r7, #4]
|
|
800738a: f001 fbf1 bl 8008b70 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
800738e: e063 b.n 8007458 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
8007390: 6839 ldr r1, [r7, #0]
|
|
8007392: 6878 ldr r0, [r7, #4]
|
|
8007394: f001 fb6f bl 8008a76 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8007398: 2303 movs r3, #3
|
|
800739a: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800739c: e05c b.n 8007458 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
if ((req->wValue >> 8) == HID_REPORT_DESC)
|
|
800739e: 683b ldr r3, [r7, #0]
|
|
80073a0: 885b ldrh r3, [r3, #2]
|
|
80073a2: 0a1b lsrs r3, r3, #8
|
|
80073a4: b29b uxth r3, r3
|
|
80073a6: 2b22 cmp r3, #34 @ 0x22
|
|
80073a8: d108 bne.n 80073bc <USBD_HID_Setup+0x150>
|
|
{
|
|
len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength);
|
|
80073aa: 683b ldr r3, [r7, #0]
|
|
80073ac: 88db ldrh r3, [r3, #6]
|
|
80073ae: 2b2d cmp r3, #45 @ 0x2d
|
|
80073b0: bf28 it cs
|
|
80073b2: 232d movcs r3, #45 @ 0x2d
|
|
80073b4: 82bb strh r3, [r7, #20]
|
|
pbuf = HID_MOUSE_ReportDesc;
|
|
80073b6: 4b2f ldr r3, [pc, #188] @ (8007474 <USBD_HID_Setup+0x208>)
|
|
80073b8: 613b str r3, [r7, #16]
|
|
80073ba: e015 b.n 80073e8 <USBD_HID_Setup+0x17c>
|
|
}
|
|
else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE)
|
|
80073bc: 683b ldr r3, [r7, #0]
|
|
80073be: 885b ldrh r3, [r3, #2]
|
|
80073c0: 0a1b lsrs r3, r3, #8
|
|
80073c2: b29b uxth r3, r3
|
|
80073c4: 2b21 cmp r3, #33 @ 0x21
|
|
80073c6: d108 bne.n 80073da <USBD_HID_Setup+0x16e>
|
|
{
|
|
pbuf = USBD_HID_Desc;
|
|
80073c8: 4b2b ldr r3, [pc, #172] @ (8007478 <USBD_HID_Setup+0x20c>)
|
|
80073ca: 613b str r3, [r7, #16]
|
|
len = MIN(USB_HID_DESC_SIZ, req->wLength);
|
|
80073cc: 683b ldr r3, [r7, #0]
|
|
80073ce: 88db ldrh r3, [r3, #6]
|
|
80073d0: 2b09 cmp r3, #9
|
|
80073d2: bf28 it cs
|
|
80073d4: 2309 movcs r3, #9
|
|
80073d6: 82bb strh r3, [r7, #20]
|
|
80073d8: e006 b.n 80073e8 <USBD_HID_Setup+0x17c>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80073da: 6839 ldr r1, [r7, #0]
|
|
80073dc: 6878 ldr r0, [r7, #4]
|
|
80073de: f001 fb4a bl 8008a76 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
80073e2: 2303 movs r3, #3
|
|
80073e4: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80073e6: e037 b.n 8007458 <USBD_HID_Setup+0x1ec>
|
|
}
|
|
(void)USBD_CtlSendData(pdev, pbuf, len);
|
|
80073e8: 8abb ldrh r3, [r7, #20]
|
|
80073ea: 461a mov r2, r3
|
|
80073ec: 6939 ldr r1, [r7, #16]
|
|
80073ee: 6878 ldr r0, [r7, #4]
|
|
80073f0: f001 fbbe bl 8008b70 <USBD_CtlSendData>
|
|
break;
|
|
80073f4: e030 b.n 8007458 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_GET_INTERFACE :
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80073f6: 687b ldr r3, [r7, #4]
|
|
80073f8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80073fc: b2db uxtb r3, r3
|
|
80073fe: 2b03 cmp r3, #3
|
|
8007400: d107 bne.n 8007412 <USBD_HID_Setup+0x1a6>
|
|
{
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U);
|
|
8007402: 68fb ldr r3, [r7, #12]
|
|
8007404: 3308 adds r3, #8
|
|
8007406: 2201 movs r2, #1
|
|
8007408: 4619 mov r1, r3
|
|
800740a: 6878 ldr r0, [r7, #4]
|
|
800740c: f001 fbb0 bl 8008b70 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
8007410: e022 b.n 8007458 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
8007412: 6839 ldr r1, [r7, #0]
|
|
8007414: 6878 ldr r0, [r7, #4]
|
|
8007416: f001 fb2e bl 8008a76 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
800741a: 2303 movs r3, #3
|
|
800741c: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800741e: e01b b.n 8007458 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_SET_INTERFACE:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007420: 687b ldr r3, [r7, #4]
|
|
8007422: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007426: b2db uxtb r3, r3
|
|
8007428: 2b03 cmp r3, #3
|
|
800742a: d106 bne.n 800743a <USBD_HID_Setup+0x1ce>
|
|
{
|
|
hhid->AltSetting = (uint8_t)(req->wValue);
|
|
800742c: 683b ldr r3, [r7, #0]
|
|
800742e: 885b ldrh r3, [r3, #2]
|
|
8007430: b2db uxtb r3, r3
|
|
8007432: 461a mov r2, r3
|
|
8007434: 68fb ldr r3, [r7, #12]
|
|
8007436: 609a str r2, [r3, #8]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
8007438: e00e b.n 8007458 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
800743a: 6839 ldr r1, [r7, #0]
|
|
800743c: 6878 ldr r0, [r7, #4]
|
|
800743e: f001 fb1a bl 8008a76 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8007442: 2303 movs r3, #3
|
|
8007444: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007446: e007 b.n 8007458 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
break;
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007448: 6839 ldr r1, [r7, #0]
|
|
800744a: 6878 ldr r0, [r7, #4]
|
|
800744c: f001 fb13 bl 8008a76 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8007450: 2303 movs r3, #3
|
|
8007452: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007454: e000 b.n 8007458 <USBD_HID_Setup+0x1ec>
|
|
break;
|
|
8007456: bf00 nop
|
|
}
|
|
break;
|
|
8007458: e006 b.n 8007468 <USBD_HID_Setup+0x1fc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800745a: 6839 ldr r1, [r7, #0]
|
|
800745c: 6878 ldr r0, [r7, #4]
|
|
800745e: f001 fb0a bl 8008a76 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8007462: 2303 movs r3, #3
|
|
8007464: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007466: bf00 nop
|
|
}
|
|
|
|
return (uint8_t)ret;
|
|
8007468: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800746a: 4618 mov r0, r3
|
|
800746c: 3718 adds r7, #24
|
|
800746e: 46bd mov sp, r7
|
|
8007470: bd80 pop {r7, pc}
|
|
8007472: bf00 nop
|
|
8007474: 200000f8 .word 0x200000f8
|
|
8007478: 200000e0 .word 0x200000e0
|
|
|
|
0800747c <USBD_HID_SendReport>:
|
|
uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId)
|
|
{
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId];
|
|
#else
|
|
uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
|
|
{
|
|
800747c: b580 push {r7, lr}
|
|
800747e: b086 sub sp, #24
|
|
8007480: af00 add r7, sp, #0
|
|
8007482: 60f8 str r0, [r7, #12]
|
|
8007484: 60b9 str r1, [r7, #8]
|
|
8007486: 4613 mov r3, r2
|
|
8007488: 80fb strh r3, [r7, #6]
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
800748a: 68fb ldr r3, [r7, #12]
|
|
800748c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007490: 68fb ldr r3, [r7, #12]
|
|
8007492: 32b0 adds r2, #176 @ 0xb0
|
|
8007494: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007498: 617b str r3, [r7, #20]
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (hhid == NULL)
|
|
800749a: 697b ldr r3, [r7, #20]
|
|
800749c: 2b00 cmp r3, #0
|
|
800749e: d101 bne.n 80074a4 <USBD_HID_SendReport+0x28>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
80074a0: 2303 movs r3, #3
|
|
80074a2: e014 b.n 80074ce <USBD_HID_SendReport+0x52>
|
|
#ifdef USE_USBD_COMPOSITE
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80074a4: 68fb ldr r3, [r7, #12]
|
|
80074a6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80074aa: b2db uxtb r3, r3
|
|
80074ac: 2b03 cmp r3, #3
|
|
80074ae: d10d bne.n 80074cc <USBD_HID_SendReport+0x50>
|
|
{
|
|
if (hhid->state == USBD_HID_IDLE)
|
|
80074b0: 697b ldr r3, [r7, #20]
|
|
80074b2: 7b1b ldrb r3, [r3, #12]
|
|
80074b4: 2b00 cmp r3, #0
|
|
80074b6: d109 bne.n 80074cc <USBD_HID_SendReport+0x50>
|
|
{
|
|
hhid->state = USBD_HID_BUSY;
|
|
80074b8: 697b ldr r3, [r7, #20]
|
|
80074ba: 2201 movs r2, #1
|
|
80074bc: 731a strb r2, [r3, #12]
|
|
(void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len);
|
|
80074be: 4b06 ldr r3, [pc, #24] @ (80074d8 <USBD_HID_SendReport+0x5c>)
|
|
80074c0: 7819 ldrb r1, [r3, #0]
|
|
80074c2: 88fb ldrh r3, [r7, #6]
|
|
80074c4: 68ba ldr r2, [r7, #8]
|
|
80074c6: 68f8 ldr r0, [r7, #12]
|
|
80074c8: f001 ff91 bl 80093ee <USBD_LL_Transmit>
|
|
}
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
80074cc: 2300 movs r3, #0
|
|
}
|
|
80074ce: 4618 mov r0, r3
|
|
80074d0: 3718 adds r7, #24
|
|
80074d2: 46bd mov sp, r7
|
|
80074d4: bd80 pop {r7, pc}
|
|
80074d6: bf00 nop
|
|
80074d8: 20000125 .word 0x20000125
|
|
|
|
080074dc <USBD_HID_GetPollingInterval>:
|
|
* return polling interval from endpoint descriptor
|
|
* @param pdev: device instance
|
|
* @retval polling interval
|
|
*/
|
|
uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80074dc: b480 push {r7}
|
|
80074de: b085 sub sp, #20
|
|
80074e0: af00 add r7, sp, #0
|
|
80074e2: 6078 str r0, [r7, #4]
|
|
uint32_t polling_interval;
|
|
|
|
/* HIGH-speed endpoints */
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
80074e4: 687b ldr r3, [r7, #4]
|
|
80074e6: 7c1b ldrb r3, [r3, #16]
|
|
80074e8: 2b00 cmp r3, #0
|
|
80074ea: d102 bne.n 80074f2 <USBD_HID_GetPollingInterval+0x16>
|
|
{
|
|
/* Sets the data transfer polling interval for high speed transfers.
|
|
Values between 1..16 are allowed. Values correspond to interval
|
|
of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */
|
|
polling_interval = (((1U << (HID_HS_BINTERVAL - 1U))) / 8U);
|
|
80074ec: 2308 movs r3, #8
|
|
80074ee: 60fb str r3, [r7, #12]
|
|
80074f0: e001 b.n 80074f6 <USBD_HID_GetPollingInterval+0x1a>
|
|
}
|
|
else /* LOW and FULL-speed endpoints */
|
|
{
|
|
/* Sets the data transfer polling interval for low and full
|
|
speed transfers */
|
|
polling_interval = HID_FS_BINTERVAL;
|
|
80074f2: 230a movs r3, #10
|
|
80074f4: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return ((uint32_t)(polling_interval));
|
|
80074f6: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80074f8: 4618 mov r0, r3
|
|
80074fa: 3714 adds r7, #20
|
|
80074fc: 46bd mov sp, r7
|
|
80074fe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007502: 4770 bx lr
|
|
|
|
08007504 <USBD_HID_GetFSCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length)
|
|
{
|
|
8007504: b580 push {r7, lr}
|
|
8007506: b084 sub sp, #16
|
|
8007508: af00 add r7, sp, #0
|
|
800750a: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
800750c: 2181 movs r1, #129 @ 0x81
|
|
800750e: 4809 ldr r0, [pc, #36] @ (8007534 <USBD_HID_GetFSCfgDesc+0x30>)
|
|
8007510: f000 fc4e bl 8007db0 <USBD_GetEpDesc>
|
|
8007514: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
8007516: 68fb ldr r3, [r7, #12]
|
|
8007518: 2b00 cmp r3, #0
|
|
800751a: d002 beq.n 8007522 <USBD_HID_GetFSCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_FS_BINTERVAL;
|
|
800751c: 68fb ldr r3, [r7, #12]
|
|
800751e: 220a movs r2, #10
|
|
8007520: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
8007522: 687b ldr r3, [r7, #4]
|
|
8007524: 2222 movs r2, #34 @ 0x22
|
|
8007526: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
8007528: 4b02 ldr r3, [pc, #8] @ (8007534 <USBD_HID_GetFSCfgDesc+0x30>)
|
|
}
|
|
800752a: 4618 mov r0, r3
|
|
800752c: 3710 adds r7, #16
|
|
800752e: 46bd mov sp, r7
|
|
8007530: bd80 pop {r7, pc}
|
|
8007532: bf00 nop
|
|
8007534: 200000bc .word 0x200000bc
|
|
|
|
08007538 <USBD_HID_GetHSCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length)
|
|
{
|
|
8007538: b580 push {r7, lr}
|
|
800753a: b084 sub sp, #16
|
|
800753c: af00 add r7, sp, #0
|
|
800753e: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
8007540: 2181 movs r1, #129 @ 0x81
|
|
8007542: 4809 ldr r0, [pc, #36] @ (8007568 <USBD_HID_GetHSCfgDesc+0x30>)
|
|
8007544: f000 fc34 bl 8007db0 <USBD_GetEpDesc>
|
|
8007548: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
800754a: 68fb ldr r3, [r7, #12]
|
|
800754c: 2b00 cmp r3, #0
|
|
800754e: d002 beq.n 8007556 <USBD_HID_GetHSCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_HS_BINTERVAL;
|
|
8007550: 68fb ldr r3, [r7, #12]
|
|
8007552: 2207 movs r2, #7
|
|
8007554: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
8007556: 687b ldr r3, [r7, #4]
|
|
8007558: 2222 movs r2, #34 @ 0x22
|
|
800755a: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
800755c: 4b02 ldr r3, [pc, #8] @ (8007568 <USBD_HID_GetHSCfgDesc+0x30>)
|
|
}
|
|
800755e: 4618 mov r0, r3
|
|
8007560: 3710 adds r7, #16
|
|
8007562: 46bd mov sp, r7
|
|
8007564: bd80 pop {r7, pc}
|
|
8007566: bf00 nop
|
|
8007568: 200000bc .word 0x200000bc
|
|
|
|
0800756c <USBD_HID_GetOtherSpeedCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length)
|
|
{
|
|
800756c: b580 push {r7, lr}
|
|
800756e: b084 sub sp, #16
|
|
8007570: af00 add r7, sp, #0
|
|
8007572: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
8007574: 2181 movs r1, #129 @ 0x81
|
|
8007576: 4809 ldr r0, [pc, #36] @ (800759c <USBD_HID_GetOtherSpeedCfgDesc+0x30>)
|
|
8007578: f000 fc1a bl 8007db0 <USBD_GetEpDesc>
|
|
800757c: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
800757e: 68fb ldr r3, [r7, #12]
|
|
8007580: 2b00 cmp r3, #0
|
|
8007582: d002 beq.n 800758a <USBD_HID_GetOtherSpeedCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_FS_BINTERVAL;
|
|
8007584: 68fb ldr r3, [r7, #12]
|
|
8007586: 220a movs r2, #10
|
|
8007588: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
800758a: 687b ldr r3, [r7, #4]
|
|
800758c: 2222 movs r2, #34 @ 0x22
|
|
800758e: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
8007590: 4b02 ldr r3, [pc, #8] @ (800759c <USBD_HID_GetOtherSpeedCfgDesc+0x30>)
|
|
}
|
|
8007592: 4618 mov r0, r3
|
|
8007594: 3710 adds r7, #16
|
|
8007596: 46bd mov sp, r7
|
|
8007598: bd80 pop {r7, pc}
|
|
800759a: bf00 nop
|
|
800759c: 200000bc .word 0x200000bc
|
|
|
|
080075a0 <USBD_HID_DataIn>:
|
|
* @param pdev: device instance
|
|
* @param epnum: endpoint index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
|
|
{
|
|
80075a0: b480 push {r7}
|
|
80075a2: b083 sub sp, #12
|
|
80075a4: af00 add r7, sp, #0
|
|
80075a6: 6078 str r0, [r7, #4]
|
|
80075a8: 460b mov r3, r1
|
|
80075aa: 70fb strb r3, [r7, #3]
|
|
UNUSED(epnum);
|
|
/* Ensure that the FIFO is empty before a new transfer, this condition could
|
|
be caused by a new transfer before the end of the previous transfer */
|
|
((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE;
|
|
80075ac: 687b ldr r3, [r7, #4]
|
|
80075ae: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80075b2: 687b ldr r3, [r7, #4]
|
|
80075b4: 32b0 adds r2, #176 @ 0xb0
|
|
80075b6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80075ba: 2200 movs r2, #0
|
|
80075bc: 731a strb r2, [r3, #12]
|
|
|
|
return (uint8_t)USBD_OK;
|
|
80075be: 2300 movs r3, #0
|
|
}
|
|
80075c0: 4618 mov r0, r3
|
|
80075c2: 370c adds r7, #12
|
|
80075c4: 46bd mov sp, r7
|
|
80075c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80075ca: 4770 bx lr
|
|
|
|
080075cc <USBD_HID_GetDeviceQualifierDesc>:
|
|
* return Device Qualifier descriptor
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length)
|
|
{
|
|
80075cc: b480 push {r7}
|
|
80075ce: b083 sub sp, #12
|
|
80075d0: af00 add r7, sp, #0
|
|
80075d2: 6078 str r0, [r7, #4]
|
|
*length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc);
|
|
80075d4: 687b ldr r3, [r7, #4]
|
|
80075d6: 220a movs r2, #10
|
|
80075d8: 801a strh r2, [r3, #0]
|
|
|
|
return USBD_HID_DeviceQualifierDesc;
|
|
80075da: 4b03 ldr r3, [pc, #12] @ (80075e8 <USBD_HID_GetDeviceQualifierDesc+0x1c>)
|
|
}
|
|
80075dc: 4618 mov r0, r3
|
|
80075de: 370c adds r7, #12
|
|
80075e0: 46bd mov sp, r7
|
|
80075e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80075e6: 4770 bx lr
|
|
80075e8: 200000ec .word 0x200000ec
|
|
|
|
080075ec <USBD_Init>:
|
|
* @param id: Low level core index
|
|
* @retval status: USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
|
|
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
|
|
{
|
|
80075ec: b580 push {r7, lr}
|
|
80075ee: b086 sub sp, #24
|
|
80075f0: af00 add r7, sp, #0
|
|
80075f2: 60f8 str r0, [r7, #12]
|
|
80075f4: 60b9 str r1, [r7, #8]
|
|
80075f6: 4613 mov r3, r2
|
|
80075f8: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef ret;
|
|
|
|
/* Check whether the USB Host handle is valid */
|
|
if (pdev == NULL)
|
|
80075fa: 68fb ldr r3, [r7, #12]
|
|
80075fc: 2b00 cmp r3, #0
|
|
80075fe: d101 bne.n 8007604 <USBD_Init+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Device handle");
|
|
#endif /* (USBD_DEBUG_LEVEL > 1U) */
|
|
return USBD_FAIL;
|
|
8007600: 2303 movs r3, #3
|
|
8007602: e01f b.n 8007644 <USBD_Init+0x58>
|
|
pdev->NumClasses = 0;
|
|
pdev->classId = 0;
|
|
}
|
|
#else
|
|
/* Unlink previous class*/
|
|
pdev->pClass[0] = NULL;
|
|
8007604: 68fb ldr r3, [r7, #12]
|
|
8007606: 2200 movs r2, #0
|
|
8007608: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
pdev->pUserData[0] = NULL;
|
|
800760c: 68fb ldr r3, [r7, #12]
|
|
800760e: 2200 movs r2, #0
|
|
8007610: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
pdev->pConfDesc = NULL;
|
|
8007614: 68fb ldr r3, [r7, #12]
|
|
8007616: 2200 movs r2, #0
|
|
8007618: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
|
|
/* Assign USBD Descriptors */
|
|
if (pdesc != NULL)
|
|
800761c: 68bb ldr r3, [r7, #8]
|
|
800761e: 2b00 cmp r3, #0
|
|
8007620: d003 beq.n 800762a <USBD_Init+0x3e>
|
|
{
|
|
pdev->pDesc = pdesc;
|
|
8007622: 68fb ldr r3, [r7, #12]
|
|
8007624: 68ba ldr r2, [r7, #8]
|
|
8007626: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
|
|
}
|
|
|
|
/* Set Device initial State */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
800762a: 68fb ldr r3, [r7, #12]
|
|
800762c: 2201 movs r2, #1
|
|
800762e: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->id = id;
|
|
8007632: 68fb ldr r3, [r7, #12]
|
|
8007634: 79fa ldrb r2, [r7, #7]
|
|
8007636: 701a strb r2, [r3, #0]
|
|
|
|
/* Initialize low level driver */
|
|
ret = USBD_LL_Init(pdev);
|
|
8007638: 68f8 ldr r0, [r7, #12]
|
|
800763a: f001 fda3 bl 8009184 <USBD_LL_Init>
|
|
800763e: 4603 mov r3, r0
|
|
8007640: 75fb strb r3, [r7, #23]
|
|
|
|
return ret;
|
|
8007642: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8007644: 4618 mov r0, r3
|
|
8007646: 3718 adds r7, #24
|
|
8007648: 46bd mov sp, r7
|
|
800764a: bd80 pop {r7, pc}
|
|
|
|
0800764c <USBD_RegisterClass>:
|
|
* @param pdev: Device Handle
|
|
* @param pclass: Class handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
|
|
{
|
|
800764c: b580 push {r7, lr}
|
|
800764e: b084 sub sp, #16
|
|
8007650: af00 add r7, sp, #0
|
|
8007652: 6078 str r0, [r7, #4]
|
|
8007654: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
8007656: 2300 movs r3, #0
|
|
8007658: 81fb strh r3, [r7, #14]
|
|
|
|
if (pclass == NULL)
|
|
800765a: 683b ldr r3, [r7, #0]
|
|
800765c: 2b00 cmp r3, #0
|
|
800765e: d101 bne.n 8007664 <USBD_RegisterClass+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Class handle");
|
|
#endif /* (USBD_DEBUG_LEVEL > 1U) */
|
|
return USBD_FAIL;
|
|
8007660: 2303 movs r3, #3
|
|
8007662: e025 b.n 80076b0 <USBD_RegisterClass+0x64>
|
|
}
|
|
|
|
/* link the class to the USB Device handle */
|
|
pdev->pClass[0] = pclass;
|
|
8007664: 687b ldr r3, [r7, #4]
|
|
8007666: 683a ldr r2, [r7, #0]
|
|
8007668: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL)
|
|
{
|
|
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len);
|
|
}
|
|
#else /* Default USE_USB_FS */
|
|
if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL)
|
|
800766c: 687b ldr r3, [r7, #4]
|
|
800766e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007672: 687b ldr r3, [r7, #4]
|
|
8007674: 32ae adds r2, #174 @ 0xae
|
|
8007676: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800767a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800767c: 2b00 cmp r3, #0
|
|
800767e: d00f beq.n 80076a0 <USBD_RegisterClass+0x54>
|
|
{
|
|
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len);
|
|
8007680: 687b ldr r3, [r7, #4]
|
|
8007682: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007686: 687b ldr r3, [r7, #4]
|
|
8007688: 32ae adds r2, #174 @ 0xae
|
|
800768a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800768e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007690: f107 020e add.w r2, r7, #14
|
|
8007694: 4610 mov r0, r2
|
|
8007696: 4798 blx r3
|
|
8007698: 4602 mov r2, r0
|
|
800769a: 687b ldr r3, [r7, #4]
|
|
800769c: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
}
|
|
#endif /* USE_USB_FS */
|
|
|
|
/* Increment the NumClasses */
|
|
pdev->NumClasses++;
|
|
80076a0: 687b ldr r3, [r7, #4]
|
|
80076a2: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
80076a6: 1c5a adds r2, r3, #1
|
|
80076a8: 687b ldr r3, [r7, #4]
|
|
80076aa: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8
|
|
|
|
return USBD_OK;
|
|
80076ae: 2300 movs r3, #0
|
|
}
|
|
80076b0: 4618 mov r0, r3
|
|
80076b2: 3710 adds r7, #16
|
|
80076b4: 46bd mov sp, r7
|
|
80076b6: bd80 pop {r7, pc}
|
|
|
|
080076b8 <USBD_Start>:
|
|
* Start the USB Device Core.
|
|
* @param pdev: Device Handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80076b8: b580 push {r7, lr}
|
|
80076ba: b082 sub sp, #8
|
|
80076bc: af00 add r7, sp, #0
|
|
80076be: 6078 str r0, [r7, #4]
|
|
#ifdef USE_USBD_COMPOSITE
|
|
pdev->classId = 0U;
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Start the low level driver */
|
|
return USBD_LL_Start(pdev);
|
|
80076c0: 6878 ldr r0, [r7, #4]
|
|
80076c2: f001 fdab bl 800921c <USBD_LL_Start>
|
|
80076c6: 4603 mov r3, r0
|
|
}
|
|
80076c8: 4618 mov r0, r3
|
|
80076ca: 3708 adds r7, #8
|
|
80076cc: 46bd mov sp, r7
|
|
80076ce: bd80 pop {r7, pc}
|
|
|
|
080076d0 <USBD_RunTestMode>:
|
|
* Launch test mode process
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80076d0: b480 push {r7}
|
|
80076d2: b083 sub sp, #12
|
|
80076d4: af00 add r7, sp, #0
|
|
80076d6: 6078 str r0, [r7, #4]
|
|
return ret;
|
|
#else
|
|
/* Prevent unused argument compilation warning */
|
|
UNUSED(pdev);
|
|
|
|
return USBD_OK;
|
|
80076d8: 2300 movs r3, #0
|
|
#endif /* USBD_HS_TESTMODE_ENABLE */
|
|
}
|
|
80076da: 4618 mov r0, r3
|
|
80076dc: 370c adds r7, #12
|
|
80076de: 46bd mov sp, r7
|
|
80076e0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80076e4: 4770 bx lr
|
|
|
|
080076e6 <USBD_SetClassConfig>:
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
|
|
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
80076e6: b580 push {r7, lr}
|
|
80076e8: b084 sub sp, #16
|
|
80076ea: af00 add r7, sp, #0
|
|
80076ec: 6078 str r0, [r7, #4]
|
|
80076ee: 460b mov r3, r1
|
|
80076f0: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80076f2: 2300 movs r3, #0
|
|
80076f4: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
80076f6: 687b ldr r3, [r7, #4]
|
|
80076f8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80076fc: 2b00 cmp r3, #0
|
|
80076fe: d009 beq.n 8007714 <USBD_SetClassConfig+0x2e>
|
|
{
|
|
/* Set configuration and Start the Class */
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx);
|
|
8007700: 687b ldr r3, [r7, #4]
|
|
8007702: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007706: 681b ldr r3, [r3, #0]
|
|
8007708: 78fa ldrb r2, [r7, #3]
|
|
800770a: 4611 mov r1, r2
|
|
800770c: 6878 ldr r0, [r7, #4]
|
|
800770e: 4798 blx r3
|
|
8007710: 4603 mov r3, r0
|
|
8007712: 73fb strb r3, [r7, #15]
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8007714: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007716: 4618 mov r0, r3
|
|
8007718: 3710 adds r7, #16
|
|
800771a: 46bd mov sp, r7
|
|
800771c: bd80 pop {r7, pc}
|
|
|
|
0800771e <USBD_ClrClassConfig>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
800771e: b580 push {r7, lr}
|
|
8007720: b084 sub sp, #16
|
|
8007722: af00 add r7, sp, #0
|
|
8007724: 6078 str r0, [r7, #4]
|
|
8007726: 460b mov r3, r1
|
|
8007728: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
800772a: 2300 movs r3, #0
|
|
800772c: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
/* Clear configuration and De-initialize the Class process */
|
|
if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U)
|
|
800772e: 687b ldr r3, [r7, #4]
|
|
8007730: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007734: 685b ldr r3, [r3, #4]
|
|
8007736: 78fa ldrb r2, [r7, #3]
|
|
8007738: 4611 mov r1, r2
|
|
800773a: 6878 ldr r0, [r7, #4]
|
|
800773c: 4798 blx r3
|
|
800773e: 4603 mov r3, r0
|
|
8007740: 2b00 cmp r3, #0
|
|
8007742: d001 beq.n 8007748 <USBD_ClrClassConfig+0x2a>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8007744: 2303 movs r3, #3
|
|
8007746: 73fb strb r3, [r7, #15]
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8007748: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800774a: 4618 mov r0, r3
|
|
800774c: 3710 adds r7, #16
|
|
800774e: 46bd mov sp, r7
|
|
8007750: bd80 pop {r7, pc}
|
|
|
|
08007752 <USBD_LL_SetupStage>:
|
|
* @param pdev: device instance
|
|
* @param psetup: setup packet buffer pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
|
|
{
|
|
8007752: b580 push {r7, lr}
|
|
8007754: b084 sub sp, #16
|
|
8007756: af00 add r7, sp, #0
|
|
8007758: 6078 str r0, [r7, #4]
|
|
800775a: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret;
|
|
|
|
USBD_ParseSetupRequest(&pdev->request, psetup);
|
|
800775c: 687b ldr r3, [r7, #4]
|
|
800775e: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8007762: 6839 ldr r1, [r7, #0]
|
|
8007764: 4618 mov r0, r3
|
|
8007766: f001 f94c bl 8008a02 <USBD_ParseSetupRequest>
|
|
|
|
pdev->ep0_state = USBD_EP0_SETUP;
|
|
800776a: 687b ldr r3, [r7, #4]
|
|
800776c: 2201 movs r2, #1
|
|
800776e: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
pdev->ep0_data_len = pdev->request.wLength;
|
|
8007772: 687b ldr r3, [r7, #4]
|
|
8007774: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0
|
|
8007778: 461a mov r2, r3
|
|
800777a: 687b ldr r3, [r7, #4]
|
|
800777c: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
8007780: 687b ldr r3, [r7, #4]
|
|
8007782: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8007786: f003 031f and.w r3, r3, #31
|
|
800778a: 2b02 cmp r3, #2
|
|
800778c: d01a beq.n 80077c4 <USBD_LL_SetupStage+0x72>
|
|
800778e: 2b02 cmp r3, #2
|
|
8007790: d822 bhi.n 80077d8 <USBD_LL_SetupStage+0x86>
|
|
8007792: 2b00 cmp r3, #0
|
|
8007794: d002 beq.n 800779c <USBD_LL_SetupStage+0x4a>
|
|
8007796: 2b01 cmp r3, #1
|
|
8007798: d00a beq.n 80077b0 <USBD_LL_SetupStage+0x5e>
|
|
800779a: e01d b.n 80077d8 <USBD_LL_SetupStage+0x86>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
ret = USBD_StdDevReq(pdev, &pdev->request);
|
|
800779c: 687b ldr r3, [r7, #4]
|
|
800779e: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
80077a2: 4619 mov r1, r3
|
|
80077a4: 6878 ldr r0, [r7, #4]
|
|
80077a6: f000 fb77 bl 8007e98 <USBD_StdDevReq>
|
|
80077aa: 4603 mov r3, r0
|
|
80077ac: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80077ae: e020 b.n 80077f2 <USBD_LL_SetupStage+0xa0>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
ret = USBD_StdItfReq(pdev, &pdev->request);
|
|
80077b0: 687b ldr r3, [r7, #4]
|
|
80077b2: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
80077b6: 4619 mov r1, r3
|
|
80077b8: 6878 ldr r0, [r7, #4]
|
|
80077ba: f000 fbdf bl 8007f7c <USBD_StdItfReq>
|
|
80077be: 4603 mov r3, r0
|
|
80077c0: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80077c2: e016 b.n 80077f2 <USBD_LL_SetupStage+0xa0>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
ret = USBD_StdEPReq(pdev, &pdev->request);
|
|
80077c4: 687b ldr r3, [r7, #4]
|
|
80077c6: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
80077ca: 4619 mov r1, r3
|
|
80077cc: 6878 ldr r0, [r7, #4]
|
|
80077ce: f000 fc41 bl 8008054 <USBD_StdEPReq>
|
|
80077d2: 4603 mov r3, r0
|
|
80077d4: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80077d6: e00c b.n 80077f2 <USBD_LL_SetupStage+0xa0>
|
|
|
|
default:
|
|
ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
|
|
80077d8: 687b ldr r3, [r7, #4]
|
|
80077da: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
80077de: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
80077e2: b2db uxtb r3, r3
|
|
80077e4: 4619 mov r1, r3
|
|
80077e6: 6878 ldr r0, [r7, #4]
|
|
80077e8: f001 fd78 bl 80092dc <USBD_LL_StallEP>
|
|
80077ec: 4603 mov r3, r0
|
|
80077ee: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80077f0: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
80077f2: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80077f4: 4618 mov r0, r3
|
|
80077f6: 3710 adds r7, #16
|
|
80077f8: 46bd mov sp, r7
|
|
80077fa: bd80 pop {r7, pc}
|
|
|
|
080077fc <USBD_LL_DataOutStage>:
|
|
* @param pdata: data pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
80077fc: b580 push {r7, lr}
|
|
80077fe: b086 sub sp, #24
|
|
8007800: af00 add r7, sp, #0
|
|
8007802: 60f8 str r0, [r7, #12]
|
|
8007804: 460b mov r3, r1
|
|
8007806: 607a str r2, [r7, #4]
|
|
8007808: 72fb strb r3, [r7, #11]
|
|
USBD_EndpointTypeDef *pep;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
800780a: 2300 movs r3, #0
|
|
800780c: 75fb strb r3, [r7, #23]
|
|
uint8_t idx;
|
|
|
|
UNUSED(pdata);
|
|
|
|
if (epnum == 0U)
|
|
800780e: 7afb ldrb r3, [r7, #11]
|
|
8007810: 2b00 cmp r3, #0
|
|
8007812: d177 bne.n 8007904 <USBD_LL_DataOutStage+0x108>
|
|
{
|
|
pep = &pdev->ep_out[0];
|
|
8007814: 68fb ldr r3, [r7, #12]
|
|
8007816: f503 73aa add.w r3, r3, #340 @ 0x154
|
|
800781a: 613b str r3, [r7, #16]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
|
|
800781c: 68fb ldr r3, [r7, #12]
|
|
800781e: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
8007822: 2b03 cmp r3, #3
|
|
8007824: f040 80a1 bne.w 800796a <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
8007828: 693b ldr r3, [r7, #16]
|
|
800782a: 685b ldr r3, [r3, #4]
|
|
800782c: 693a ldr r2, [r7, #16]
|
|
800782e: 8992 ldrh r2, [r2, #12]
|
|
8007830: 4293 cmp r3, r2
|
|
8007832: d91c bls.n 800786e <USBD_LL_DataOutStage+0x72>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
8007834: 693b ldr r3, [r7, #16]
|
|
8007836: 685b ldr r3, [r3, #4]
|
|
8007838: 693a ldr r2, [r7, #16]
|
|
800783a: 8992 ldrh r2, [r2, #12]
|
|
800783c: 1a9a subs r2, r3, r2
|
|
800783e: 693b ldr r3, [r7, #16]
|
|
8007840: 605a str r2, [r3, #4]
|
|
pep->pbuffer += pep->maxpacket;
|
|
8007842: 693b ldr r3, [r7, #16]
|
|
8007844: 691b ldr r3, [r3, #16]
|
|
8007846: 693a ldr r2, [r7, #16]
|
|
8007848: 8992 ldrh r2, [r2, #12]
|
|
800784a: 441a add r2, r3
|
|
800784c: 693b ldr r3, [r7, #16]
|
|
800784e: 611a str r2, [r3, #16]
|
|
|
|
(void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket));
|
|
8007850: 693b ldr r3, [r7, #16]
|
|
8007852: 6919 ldr r1, [r3, #16]
|
|
8007854: 693b ldr r3, [r7, #16]
|
|
8007856: 899b ldrh r3, [r3, #12]
|
|
8007858: 461a mov r2, r3
|
|
800785a: 693b ldr r3, [r7, #16]
|
|
800785c: 685b ldr r3, [r3, #4]
|
|
800785e: 4293 cmp r3, r2
|
|
8007860: bf38 it cc
|
|
8007862: 4613 movcc r3, r2
|
|
8007864: 461a mov r2, r3
|
|
8007866: 68f8 ldr r0, [r7, #12]
|
|
8007868: f001 f9b1 bl 8008bce <USBD_CtlContinueRx>
|
|
800786c: e07d b.n 800796a <USBD_LL_DataOutStage+0x16e>
|
|
}
|
|
else
|
|
{
|
|
/* Find the class ID relative to the current request */
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
800786e: 68fb ldr r3, [r7, #12]
|
|
8007870: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8007874: f003 031f and.w r3, r3, #31
|
|
8007878: 2b02 cmp r3, #2
|
|
800787a: d014 beq.n 80078a6 <USBD_LL_DataOutStage+0xaa>
|
|
800787c: 2b02 cmp r3, #2
|
|
800787e: d81d bhi.n 80078bc <USBD_LL_DataOutStage+0xc0>
|
|
8007880: 2b00 cmp r3, #0
|
|
8007882: d002 beq.n 800788a <USBD_LL_DataOutStage+0x8e>
|
|
8007884: 2b01 cmp r3, #1
|
|
8007886: d003 beq.n 8007890 <USBD_LL_DataOutStage+0x94>
|
|
8007888: e018 b.n 80078bc <USBD_LL_DataOutStage+0xc0>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
/* Device requests must be managed by the first instantiated class
|
|
(or duplicated by all classes for simplicity) */
|
|
idx = 0U;
|
|
800788a: 2300 movs r3, #0
|
|
800788c: 75bb strb r3, [r7, #22]
|
|
break;
|
|
800788e: e018 b.n 80078c2 <USBD_LL_DataOutStage+0xc6>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex));
|
|
8007890: 68fb ldr r3, [r7, #12]
|
|
8007892: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
8007896: b2db uxtb r3, r3
|
|
8007898: 4619 mov r1, r3
|
|
800789a: 68f8 ldr r0, [r7, #12]
|
|
800789c: f000 fa6e bl 8007d7c <USBD_CoreFindIF>
|
|
80078a0: 4603 mov r3, r0
|
|
80078a2: 75bb strb r3, [r7, #22]
|
|
break;
|
|
80078a4: e00d b.n 80078c2 <USBD_LL_DataOutStage+0xc6>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex));
|
|
80078a6: 68fb ldr r3, [r7, #12]
|
|
80078a8: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
80078ac: b2db uxtb r3, r3
|
|
80078ae: 4619 mov r1, r3
|
|
80078b0: 68f8 ldr r0, [r7, #12]
|
|
80078b2: f000 fa70 bl 8007d96 <USBD_CoreFindEP>
|
|
80078b6: 4603 mov r3, r0
|
|
80078b8: 75bb strb r3, [r7, #22]
|
|
break;
|
|
80078ba: e002 b.n 80078c2 <USBD_LL_DataOutStage+0xc6>
|
|
|
|
default:
|
|
/* Back to the first class in case of doubt */
|
|
idx = 0U;
|
|
80078bc: 2300 movs r3, #0
|
|
80078be: 75bb strb r3, [r7, #22]
|
|
break;
|
|
80078c0: bf00 nop
|
|
}
|
|
|
|
if (idx < USBD_MAX_SUPPORTED_CLASS)
|
|
80078c2: 7dbb ldrb r3, [r7, #22]
|
|
80078c4: 2b00 cmp r3, #0
|
|
80078c6: d119 bne.n 80078fc <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
/* Setup the class ID and route the request to the relative class function */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80078c8: 68fb ldr r3, [r7, #12]
|
|
80078ca: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80078ce: b2db uxtb r3, r3
|
|
80078d0: 2b03 cmp r3, #3
|
|
80078d2: d113 bne.n 80078fc <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
if (pdev->pClass[idx]->EP0_RxReady != NULL)
|
|
80078d4: 7dba ldrb r2, [r7, #22]
|
|
80078d6: 68fb ldr r3, [r7, #12]
|
|
80078d8: 32ae adds r2, #174 @ 0xae
|
|
80078da: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80078de: 691b ldr r3, [r3, #16]
|
|
80078e0: 2b00 cmp r3, #0
|
|
80078e2: d00b beq.n 80078fc <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
pdev->classId = idx;
|
|
80078e4: 7dba ldrb r2, [r7, #22]
|
|
80078e6: 68fb ldr r3, [r7, #12]
|
|
80078e8: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
pdev->pClass[idx]->EP0_RxReady(pdev);
|
|
80078ec: 7dba ldrb r2, [r7, #22]
|
|
80078ee: 68fb ldr r3, [r7, #12]
|
|
80078f0: 32ae adds r2, #174 @ 0xae
|
|
80078f2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80078f6: 691b ldr r3, [r3, #16]
|
|
80078f8: 68f8 ldr r0, [r7, #12]
|
|
80078fa: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80078fc: 68f8 ldr r0, [r7, #12]
|
|
80078fe: f001 f977 bl 8008bf0 <USBD_CtlSendStatus>
|
|
8007902: e032 b.n 800796a <USBD_LL_DataOutStage+0x16e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU));
|
|
8007904: 7afb ldrb r3, [r7, #11]
|
|
8007906: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
800790a: b2db uxtb r3, r3
|
|
800790c: 4619 mov r1, r3
|
|
800790e: 68f8 ldr r0, [r7, #12]
|
|
8007910: f000 fa41 bl 8007d96 <USBD_CoreFindEP>
|
|
8007914: 4603 mov r3, r0
|
|
8007916: 75bb strb r3, [r7, #22]
|
|
|
|
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8007918: 7dbb ldrb r3, [r7, #22]
|
|
800791a: 2bff cmp r3, #255 @ 0xff
|
|
800791c: d025 beq.n 800796a <USBD_LL_DataOutStage+0x16e>
|
|
800791e: 7dbb ldrb r3, [r7, #22]
|
|
8007920: 2b00 cmp r3, #0
|
|
8007922: d122 bne.n 800796a <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007924: 68fb ldr r3, [r7, #12]
|
|
8007926: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
800792a: b2db uxtb r3, r3
|
|
800792c: 2b03 cmp r3, #3
|
|
800792e: d117 bne.n 8007960 <USBD_LL_DataOutStage+0x164>
|
|
{
|
|
if (pdev->pClass[idx]->DataOut != NULL)
|
|
8007930: 7dba ldrb r2, [r7, #22]
|
|
8007932: 68fb ldr r3, [r7, #12]
|
|
8007934: 32ae adds r2, #174 @ 0xae
|
|
8007936: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800793a: 699b ldr r3, [r3, #24]
|
|
800793c: 2b00 cmp r3, #0
|
|
800793e: d00f beq.n 8007960 <USBD_LL_DataOutStage+0x164>
|
|
{
|
|
pdev->classId = idx;
|
|
8007940: 7dba ldrb r2, [r7, #22]
|
|
8007942: 68fb ldr r3, [r7, #12]
|
|
8007944: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum);
|
|
8007948: 7dba ldrb r2, [r7, #22]
|
|
800794a: 68fb ldr r3, [r7, #12]
|
|
800794c: 32ae adds r2, #174 @ 0xae
|
|
800794e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007952: 699b ldr r3, [r3, #24]
|
|
8007954: 7afa ldrb r2, [r7, #11]
|
|
8007956: 4611 mov r1, r2
|
|
8007958: 68f8 ldr r0, [r7, #12]
|
|
800795a: 4798 blx r3
|
|
800795c: 4603 mov r3, r0
|
|
800795e: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
if (ret != USBD_OK)
|
|
8007960: 7dfb ldrb r3, [r7, #23]
|
|
8007962: 2b00 cmp r3, #0
|
|
8007964: d001 beq.n 800796a <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
return ret;
|
|
8007966: 7dfb ldrb r3, [r7, #23]
|
|
8007968: e000 b.n 800796c <USBD_LL_DataOutStage+0x170>
|
|
}
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
800796a: 2300 movs r3, #0
|
|
}
|
|
800796c: 4618 mov r0, r3
|
|
800796e: 3718 adds r7, #24
|
|
8007970: 46bd mov sp, r7
|
|
8007972: bd80 pop {r7, pc}
|
|
|
|
08007974 <USBD_LL_DataInStage>:
|
|
* @param pdata: data pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
8007974: b580 push {r7, lr}
|
|
8007976: b086 sub sp, #24
|
|
8007978: af00 add r7, sp, #0
|
|
800797a: 60f8 str r0, [r7, #12]
|
|
800797c: 460b mov r3, r1
|
|
800797e: 607a str r2, [r7, #4]
|
|
8007980: 72fb strb r3, [r7, #11]
|
|
USBD_StatusTypeDef ret;
|
|
uint8_t idx;
|
|
|
|
UNUSED(pdata);
|
|
|
|
if (epnum == 0U)
|
|
8007982: 7afb ldrb r3, [r7, #11]
|
|
8007984: 2b00 cmp r3, #0
|
|
8007986: d178 bne.n 8007a7a <USBD_LL_DataInStage+0x106>
|
|
{
|
|
pep = &pdev->ep_in[0];
|
|
8007988: 68fb ldr r3, [r7, #12]
|
|
800798a: 3314 adds r3, #20
|
|
800798c: 613b str r3, [r7, #16]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_IN)
|
|
800798e: 68fb ldr r3, [r7, #12]
|
|
8007990: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
8007994: 2b02 cmp r3, #2
|
|
8007996: d163 bne.n 8007a60 <USBD_LL_DataInStage+0xec>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
8007998: 693b ldr r3, [r7, #16]
|
|
800799a: 685b ldr r3, [r3, #4]
|
|
800799c: 693a ldr r2, [r7, #16]
|
|
800799e: 8992 ldrh r2, [r2, #12]
|
|
80079a0: 4293 cmp r3, r2
|
|
80079a2: d91c bls.n 80079de <USBD_LL_DataInStage+0x6a>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
80079a4: 693b ldr r3, [r7, #16]
|
|
80079a6: 685b ldr r3, [r3, #4]
|
|
80079a8: 693a ldr r2, [r7, #16]
|
|
80079aa: 8992 ldrh r2, [r2, #12]
|
|
80079ac: 1a9a subs r2, r3, r2
|
|
80079ae: 693b ldr r3, [r7, #16]
|
|
80079b0: 605a str r2, [r3, #4]
|
|
pep->pbuffer += pep->maxpacket;
|
|
80079b2: 693b ldr r3, [r7, #16]
|
|
80079b4: 691b ldr r3, [r3, #16]
|
|
80079b6: 693a ldr r2, [r7, #16]
|
|
80079b8: 8992 ldrh r2, [r2, #12]
|
|
80079ba: 441a add r2, r3
|
|
80079bc: 693b ldr r3, [r7, #16]
|
|
80079be: 611a str r2, [r3, #16]
|
|
|
|
(void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length);
|
|
80079c0: 693b ldr r3, [r7, #16]
|
|
80079c2: 6919 ldr r1, [r3, #16]
|
|
80079c4: 693b ldr r3, [r7, #16]
|
|
80079c6: 685b ldr r3, [r3, #4]
|
|
80079c8: 461a mov r2, r3
|
|
80079ca: 68f8 ldr r0, [r7, #12]
|
|
80079cc: f001 f8ee bl 8008bac <USBD_CtlContinueSendData>
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
80079d0: 2300 movs r3, #0
|
|
80079d2: 2200 movs r2, #0
|
|
80079d4: 2100 movs r1, #0
|
|
80079d6: 68f8 ldr r0, [r7, #12]
|
|
80079d8: f001 fd2a bl 8009430 <USBD_LL_PrepareReceive>
|
|
80079dc: e040 b.n 8007a60 <USBD_LL_DataInStage+0xec>
|
|
}
|
|
else
|
|
{
|
|
/* last packet is MPS multiple, so send ZLP packet */
|
|
if ((pep->maxpacket == pep->rem_length) &&
|
|
80079de: 693b ldr r3, [r7, #16]
|
|
80079e0: 899b ldrh r3, [r3, #12]
|
|
80079e2: 461a mov r2, r3
|
|
80079e4: 693b ldr r3, [r7, #16]
|
|
80079e6: 685b ldr r3, [r3, #4]
|
|
80079e8: 429a cmp r2, r3
|
|
80079ea: d11c bne.n 8007a26 <USBD_LL_DataInStage+0xb2>
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
80079ec: 693b ldr r3, [r7, #16]
|
|
80079ee: 681b ldr r3, [r3, #0]
|
|
80079f0: 693a ldr r2, [r7, #16]
|
|
80079f2: 8992 ldrh r2, [r2, #12]
|
|
if ((pep->maxpacket == pep->rem_length) &&
|
|
80079f4: 4293 cmp r3, r2
|
|
80079f6: d316 bcc.n 8007a26 <USBD_LL_DataInStage+0xb2>
|
|
(pep->total_length < pdev->ep0_data_len))
|
|
80079f8: 693b ldr r3, [r7, #16]
|
|
80079fa: 681a ldr r2, [r3, #0]
|
|
80079fc: 68fb ldr r3, [r7, #12]
|
|
80079fe: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
8007a02: 429a cmp r2, r3
|
|
8007a04: d20f bcs.n 8007a26 <USBD_LL_DataInStage+0xb2>
|
|
{
|
|
(void)USBD_CtlContinueSendData(pdev, NULL, 0U);
|
|
8007a06: 2200 movs r2, #0
|
|
8007a08: 2100 movs r1, #0
|
|
8007a0a: 68f8 ldr r0, [r7, #12]
|
|
8007a0c: f001 f8ce bl 8008bac <USBD_CtlContinueSendData>
|
|
pdev->ep0_data_len = 0U;
|
|
8007a10: 68fb ldr r3, [r7, #12]
|
|
8007a12: 2200 movs r2, #0
|
|
8007a14: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8007a18: 2300 movs r3, #0
|
|
8007a1a: 2200 movs r2, #0
|
|
8007a1c: 2100 movs r1, #0
|
|
8007a1e: 68f8 ldr r0, [r7, #12]
|
|
8007a20: f001 fd06 bl 8009430 <USBD_LL_PrepareReceive>
|
|
8007a24: e01c b.n 8007a60 <USBD_LL_DataInStage+0xec>
|
|
}
|
|
else
|
|
{
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007a26: 68fb ldr r3, [r7, #12]
|
|
8007a28: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007a2c: b2db uxtb r3, r3
|
|
8007a2e: 2b03 cmp r3, #3
|
|
8007a30: d10f bne.n 8007a52 <USBD_LL_DataInStage+0xde>
|
|
{
|
|
if (pdev->pClass[0]->EP0_TxSent != NULL)
|
|
8007a32: 68fb ldr r3, [r7, #12]
|
|
8007a34: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007a38: 68db ldr r3, [r3, #12]
|
|
8007a3a: 2b00 cmp r3, #0
|
|
8007a3c: d009 beq.n 8007a52 <USBD_LL_DataInStage+0xde>
|
|
{
|
|
pdev->classId = 0U;
|
|
8007a3e: 68fb ldr r3, [r7, #12]
|
|
8007a40: 2200 movs r2, #0
|
|
8007a42: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
pdev->pClass[0]->EP0_TxSent(pdev);
|
|
8007a46: 68fb ldr r3, [r7, #12]
|
|
8007a48: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007a4c: 68db ldr r3, [r3, #12]
|
|
8007a4e: 68f8 ldr r0, [r7, #12]
|
|
8007a50: 4798 blx r3
|
|
}
|
|
}
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8007a52: 2180 movs r1, #128 @ 0x80
|
|
8007a54: 68f8 ldr r0, [r7, #12]
|
|
8007a56: f001 fc41 bl 80092dc <USBD_LL_StallEP>
|
|
(void)USBD_CtlReceiveStatus(pdev);
|
|
8007a5a: 68f8 ldr r0, [r7, #12]
|
|
8007a5c: f001 f8db bl 8008c16 <USBD_CtlReceiveStatus>
|
|
}
|
|
}
|
|
}
|
|
|
|
if (pdev->dev_test_mode != 0U)
|
|
8007a60: 68fb ldr r3, [r7, #12]
|
|
8007a62: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
|
|
8007a66: 2b00 cmp r3, #0
|
|
8007a68: d03a beq.n 8007ae0 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
(void)USBD_RunTestMode(pdev);
|
|
8007a6a: 68f8 ldr r0, [r7, #12]
|
|
8007a6c: f7ff fe30 bl 80076d0 <USBD_RunTestMode>
|
|
pdev->dev_test_mode = 0U;
|
|
8007a70: 68fb ldr r3, [r7, #12]
|
|
8007a72: 2200 movs r2, #0
|
|
8007a74: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
8007a78: e032 b.n 8007ae0 <USBD_LL_DataInStage+0x16c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U));
|
|
8007a7a: 7afb ldrb r3, [r7, #11]
|
|
8007a7c: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8007a80: b2db uxtb r3, r3
|
|
8007a82: 4619 mov r1, r3
|
|
8007a84: 68f8 ldr r0, [r7, #12]
|
|
8007a86: f000 f986 bl 8007d96 <USBD_CoreFindEP>
|
|
8007a8a: 4603 mov r3, r0
|
|
8007a8c: 75fb strb r3, [r7, #23]
|
|
|
|
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8007a8e: 7dfb ldrb r3, [r7, #23]
|
|
8007a90: 2bff cmp r3, #255 @ 0xff
|
|
8007a92: d025 beq.n 8007ae0 <USBD_LL_DataInStage+0x16c>
|
|
8007a94: 7dfb ldrb r3, [r7, #23]
|
|
8007a96: 2b00 cmp r3, #0
|
|
8007a98: d122 bne.n 8007ae0 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007a9a: 68fb ldr r3, [r7, #12]
|
|
8007a9c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007aa0: b2db uxtb r3, r3
|
|
8007aa2: 2b03 cmp r3, #3
|
|
8007aa4: d11c bne.n 8007ae0 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
if (pdev->pClass[idx]->DataIn != NULL)
|
|
8007aa6: 7dfa ldrb r2, [r7, #23]
|
|
8007aa8: 68fb ldr r3, [r7, #12]
|
|
8007aaa: 32ae adds r2, #174 @ 0xae
|
|
8007aac: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007ab0: 695b ldr r3, [r3, #20]
|
|
8007ab2: 2b00 cmp r3, #0
|
|
8007ab4: d014 beq.n 8007ae0 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
pdev->classId = idx;
|
|
8007ab6: 7dfa ldrb r2, [r7, #23]
|
|
8007ab8: 68fb ldr r3, [r7, #12]
|
|
8007aba: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum);
|
|
8007abe: 7dfa ldrb r2, [r7, #23]
|
|
8007ac0: 68fb ldr r3, [r7, #12]
|
|
8007ac2: 32ae adds r2, #174 @ 0xae
|
|
8007ac4: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007ac8: 695b ldr r3, [r3, #20]
|
|
8007aca: 7afa ldrb r2, [r7, #11]
|
|
8007acc: 4611 mov r1, r2
|
|
8007ace: 68f8 ldr r0, [r7, #12]
|
|
8007ad0: 4798 blx r3
|
|
8007ad2: 4603 mov r3, r0
|
|
8007ad4: 75bb strb r3, [r7, #22]
|
|
|
|
if (ret != USBD_OK)
|
|
8007ad6: 7dbb ldrb r3, [r7, #22]
|
|
8007ad8: 2b00 cmp r3, #0
|
|
8007ada: d001 beq.n 8007ae0 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
return ret;
|
|
8007adc: 7dbb ldrb r3, [r7, #22]
|
|
8007ade: e000 b.n 8007ae2 <USBD_LL_DataInStage+0x16e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007ae0: 2300 movs r3, #0
|
|
}
|
|
8007ae2: 4618 mov r0, r3
|
|
8007ae4: 3718 adds r7, #24
|
|
8007ae6: 46bd mov sp, r7
|
|
8007ae8: bd80 pop {r7, pc}
|
|
|
|
08007aea <USBD_LL_Reset>:
|
|
* Handle Reset event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007aea: b580 push {r7, lr}
|
|
8007aec: b084 sub sp, #16
|
|
8007aee: af00 add r7, sp, #0
|
|
8007af0: 6078 str r0, [r7, #4]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007af2: 2300 movs r3, #0
|
|
8007af4: 73fb strb r3, [r7, #15]
|
|
|
|
/* Upon Reset call user call back */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8007af6: 687b ldr r3, [r7, #4]
|
|
8007af8: 2201 movs r2, #1
|
|
8007afa: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->ep0_state = USBD_EP0_IDLE;
|
|
8007afe: 687b ldr r3, [r7, #4]
|
|
8007b00: 2200 movs r2, #0
|
|
8007b02: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->dev_config = 0U;
|
|
8007b06: 687b ldr r3, [r7, #4]
|
|
8007b08: 2200 movs r2, #0
|
|
8007b0a: 605a str r2, [r3, #4]
|
|
pdev->dev_remote_wakeup = 0U;
|
|
8007b0c: 687b ldr r3, [r7, #4]
|
|
8007b0e: 2200 movs r2, #0
|
|
8007b10: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
pdev->dev_test_mode = 0U;
|
|
8007b14: 687b ldr r3, [r7, #4]
|
|
8007b16: 2200 movs r2, #0
|
|
8007b18: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
|
|
if (pdev->pClass[0] != NULL)
|
|
8007b1c: 687b ldr r3, [r7, #4]
|
|
8007b1e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007b22: 2b00 cmp r3, #0
|
|
8007b24: d014 beq.n 8007b50 <USBD_LL_Reset+0x66>
|
|
{
|
|
if (pdev->pClass[0]->DeInit != NULL)
|
|
8007b26: 687b ldr r3, [r7, #4]
|
|
8007b28: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007b2c: 685b ldr r3, [r3, #4]
|
|
8007b2e: 2b00 cmp r3, #0
|
|
8007b30: d00e beq.n 8007b50 <USBD_LL_Reset+0x66>
|
|
{
|
|
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK)
|
|
8007b32: 687b ldr r3, [r7, #4]
|
|
8007b34: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007b38: 685b ldr r3, [r3, #4]
|
|
8007b3a: 687a ldr r2, [r7, #4]
|
|
8007b3c: 6852 ldr r2, [r2, #4]
|
|
8007b3e: b2d2 uxtb r2, r2
|
|
8007b40: 4611 mov r1, r2
|
|
8007b42: 6878 ldr r0, [r7, #4]
|
|
8007b44: 4798 blx r3
|
|
8007b46: 4603 mov r3, r0
|
|
8007b48: 2b00 cmp r3, #0
|
|
8007b4a: d001 beq.n 8007b50 <USBD_LL_Reset+0x66>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8007b4c: 2303 movs r3, #3
|
|
8007b4e: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Open EP0 OUT */
|
|
(void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
8007b50: 2340 movs r3, #64 @ 0x40
|
|
8007b52: 2200 movs r2, #0
|
|
8007b54: 2100 movs r1, #0
|
|
8007b56: 6878 ldr r0, [r7, #4]
|
|
8007b58: f001 fb7b bl 8009252 <USBD_LL_OpenEP>
|
|
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
|
|
8007b5c: 687b ldr r3, [r7, #4]
|
|
8007b5e: 2201 movs r2, #1
|
|
8007b60: f883 2163 strb.w r2, [r3, #355] @ 0x163
|
|
|
|
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
8007b64: 687b ldr r3, [r7, #4]
|
|
8007b66: 2240 movs r2, #64 @ 0x40
|
|
8007b68: f8a3 2160 strh.w r2, [r3, #352] @ 0x160
|
|
|
|
/* Open EP0 IN */
|
|
(void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
8007b6c: 2340 movs r3, #64 @ 0x40
|
|
8007b6e: 2200 movs r2, #0
|
|
8007b70: 2180 movs r1, #128 @ 0x80
|
|
8007b72: 6878 ldr r0, [r7, #4]
|
|
8007b74: f001 fb6d bl 8009252 <USBD_LL_OpenEP>
|
|
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
|
|
8007b78: 687b ldr r3, [r7, #4]
|
|
8007b7a: 2201 movs r2, #1
|
|
8007b7c: f883 2023 strb.w r2, [r3, #35] @ 0x23
|
|
|
|
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
8007b80: 687b ldr r3, [r7, #4]
|
|
8007b82: 2240 movs r2, #64 @ 0x40
|
|
8007b84: 841a strh r2, [r3, #32]
|
|
|
|
return ret;
|
|
8007b86: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007b88: 4618 mov r0, r3
|
|
8007b8a: 3710 adds r7, #16
|
|
8007b8c: 46bd mov sp, r7
|
|
8007b8e: bd80 pop {r7, pc}
|
|
|
|
08007b90 <USBD_LL_SetSpeed>:
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
|
|
USBD_SpeedTypeDef speed)
|
|
{
|
|
8007b90: b480 push {r7}
|
|
8007b92: b083 sub sp, #12
|
|
8007b94: af00 add r7, sp, #0
|
|
8007b96: 6078 str r0, [r7, #4]
|
|
8007b98: 460b mov r3, r1
|
|
8007b9a: 70fb strb r3, [r7, #3]
|
|
pdev->dev_speed = speed;
|
|
8007b9c: 687b ldr r3, [r7, #4]
|
|
8007b9e: 78fa ldrb r2, [r7, #3]
|
|
8007ba0: 741a strb r2, [r3, #16]
|
|
|
|
return USBD_OK;
|
|
8007ba2: 2300 movs r3, #0
|
|
}
|
|
8007ba4: 4618 mov r0, r3
|
|
8007ba6: 370c adds r7, #12
|
|
8007ba8: 46bd mov sp, r7
|
|
8007baa: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007bae: 4770 bx lr
|
|
|
|
08007bb0 <USBD_LL_Suspend>:
|
|
* Handle Suspend event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007bb0: b480 push {r7}
|
|
8007bb2: b083 sub sp, #12
|
|
8007bb4: af00 add r7, sp, #0
|
|
8007bb6: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state != USBD_STATE_SUSPENDED)
|
|
8007bb8: 687b ldr r3, [r7, #4]
|
|
8007bba: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007bbe: b2db uxtb r3, r3
|
|
8007bc0: 2b04 cmp r3, #4
|
|
8007bc2: d006 beq.n 8007bd2 <USBD_LL_Suspend+0x22>
|
|
{
|
|
pdev->dev_old_state = pdev->dev_state;
|
|
8007bc4: 687b ldr r3, [r7, #4]
|
|
8007bc6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007bca: b2da uxtb r2, r3
|
|
8007bcc: 687b ldr r3, [r7, #4]
|
|
8007bce: f883 229d strb.w r2, [r3, #669] @ 0x29d
|
|
}
|
|
|
|
pdev->dev_state = USBD_STATE_SUSPENDED;
|
|
8007bd2: 687b ldr r3, [r7, #4]
|
|
8007bd4: 2204 movs r2, #4
|
|
8007bd6: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
|
|
return USBD_OK;
|
|
8007bda: 2300 movs r3, #0
|
|
}
|
|
8007bdc: 4618 mov r0, r3
|
|
8007bde: 370c adds r7, #12
|
|
8007be0: 46bd mov sp, r7
|
|
8007be2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007be6: 4770 bx lr
|
|
|
|
08007be8 <USBD_LL_Resume>:
|
|
* Handle Resume event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007be8: b480 push {r7}
|
|
8007bea: b083 sub sp, #12
|
|
8007bec: af00 add r7, sp, #0
|
|
8007bee: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state == USBD_STATE_SUSPENDED)
|
|
8007bf0: 687b ldr r3, [r7, #4]
|
|
8007bf2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007bf6: b2db uxtb r3, r3
|
|
8007bf8: 2b04 cmp r3, #4
|
|
8007bfa: d106 bne.n 8007c0a <USBD_LL_Resume+0x22>
|
|
{
|
|
pdev->dev_state = pdev->dev_old_state;
|
|
8007bfc: 687b ldr r3, [r7, #4]
|
|
8007bfe: f893 329d ldrb.w r3, [r3, #669] @ 0x29d
|
|
8007c02: b2da uxtb r2, r3
|
|
8007c04: 687b ldr r3, [r7, #4]
|
|
8007c06: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007c0a: 2300 movs r3, #0
|
|
}
|
|
8007c0c: 4618 mov r0, r3
|
|
8007c0e: 370c adds r7, #12
|
|
8007c10: 46bd mov sp, r7
|
|
8007c12: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007c16: 4770 bx lr
|
|
|
|
08007c18 <USBD_LL_SOF>:
|
|
* Handle SOF event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007c18: b580 push {r7, lr}
|
|
8007c1a: b082 sub sp, #8
|
|
8007c1c: af00 add r7, sp, #0
|
|
8007c1e: 6078 str r0, [r7, #4]
|
|
/* The SOF event can be distributed for all classes that support it */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007c20: 687b ldr r3, [r7, #4]
|
|
8007c22: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007c26: b2db uxtb r3, r3
|
|
8007c28: 2b03 cmp r3, #3
|
|
8007c2a: d110 bne.n 8007c4e <USBD_LL_SOF+0x36>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
8007c2c: 687b ldr r3, [r7, #4]
|
|
8007c2e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007c32: 2b00 cmp r3, #0
|
|
8007c34: d00b beq.n 8007c4e <USBD_LL_SOF+0x36>
|
|
{
|
|
if (pdev->pClass[0]->SOF != NULL)
|
|
8007c36: 687b ldr r3, [r7, #4]
|
|
8007c38: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007c3c: 69db ldr r3, [r3, #28]
|
|
8007c3e: 2b00 cmp r3, #0
|
|
8007c40: d005 beq.n 8007c4e <USBD_LL_SOF+0x36>
|
|
{
|
|
(void)pdev->pClass[0]->SOF(pdev);
|
|
8007c42: 687b ldr r3, [r7, #4]
|
|
8007c44: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007c48: 69db ldr r3, [r3, #28]
|
|
8007c4a: 6878 ldr r0, [r7, #4]
|
|
8007c4c: 4798 blx r3
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007c4e: 2300 movs r3, #0
|
|
}
|
|
8007c50: 4618 mov r0, r3
|
|
8007c52: 3708 adds r7, #8
|
|
8007c54: 46bd mov sp, r7
|
|
8007c56: bd80 pop {r7, pc}
|
|
|
|
08007c58 <USBD_LL_IsoINIncomplete>:
|
|
* @param epnum: Endpoint number
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum)
|
|
{
|
|
8007c58: b580 push {r7, lr}
|
|
8007c5a: b082 sub sp, #8
|
|
8007c5c: af00 add r7, sp, #0
|
|
8007c5e: 6078 str r0, [r7, #4]
|
|
8007c60: 460b mov r3, r1
|
|
8007c62: 70fb strb r3, [r7, #3]
|
|
if (pdev->pClass[pdev->classId] == NULL)
|
|
8007c64: 687b ldr r3, [r7, #4]
|
|
8007c66: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007c6a: 687b ldr r3, [r7, #4]
|
|
8007c6c: 32ae adds r2, #174 @ 0xae
|
|
8007c6e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007c72: 2b00 cmp r3, #0
|
|
8007c74: d101 bne.n 8007c7a <USBD_LL_IsoINIncomplete+0x22>
|
|
{
|
|
return USBD_FAIL;
|
|
8007c76: 2303 movs r3, #3
|
|
8007c78: e01c b.n 8007cb4 <USBD_LL_IsoINIncomplete+0x5c>
|
|
}
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007c7a: 687b ldr r3, [r7, #4]
|
|
8007c7c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007c80: b2db uxtb r3, r3
|
|
8007c82: 2b03 cmp r3, #3
|
|
8007c84: d115 bne.n 8007cb2 <USBD_LL_IsoINIncomplete+0x5a>
|
|
{
|
|
if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL)
|
|
8007c86: 687b ldr r3, [r7, #4]
|
|
8007c88: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007c8c: 687b ldr r3, [r7, #4]
|
|
8007c8e: 32ae adds r2, #174 @ 0xae
|
|
8007c90: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007c94: 6a1b ldr r3, [r3, #32]
|
|
8007c96: 2b00 cmp r3, #0
|
|
8007c98: d00b beq.n 8007cb2 <USBD_LL_IsoINIncomplete+0x5a>
|
|
{
|
|
(void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum);
|
|
8007c9a: 687b ldr r3, [r7, #4]
|
|
8007c9c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007ca0: 687b ldr r3, [r7, #4]
|
|
8007ca2: 32ae adds r2, #174 @ 0xae
|
|
8007ca4: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007ca8: 6a1b ldr r3, [r3, #32]
|
|
8007caa: 78fa ldrb r2, [r7, #3]
|
|
8007cac: 4611 mov r1, r2
|
|
8007cae: 6878 ldr r0, [r7, #4]
|
|
8007cb0: 4798 blx r3
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007cb2: 2300 movs r3, #0
|
|
}
|
|
8007cb4: 4618 mov r0, r3
|
|
8007cb6: 3708 adds r7, #8
|
|
8007cb8: 46bd mov sp, r7
|
|
8007cba: bd80 pop {r7, pc}
|
|
|
|
08007cbc <USBD_LL_IsoOUTIncomplete>:
|
|
* @param epnum: Endpoint number
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum)
|
|
{
|
|
8007cbc: b580 push {r7, lr}
|
|
8007cbe: b082 sub sp, #8
|
|
8007cc0: af00 add r7, sp, #0
|
|
8007cc2: 6078 str r0, [r7, #4]
|
|
8007cc4: 460b mov r3, r1
|
|
8007cc6: 70fb strb r3, [r7, #3]
|
|
if (pdev->pClass[pdev->classId] == NULL)
|
|
8007cc8: 687b ldr r3, [r7, #4]
|
|
8007cca: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007cce: 687b ldr r3, [r7, #4]
|
|
8007cd0: 32ae adds r2, #174 @ 0xae
|
|
8007cd2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007cd6: 2b00 cmp r3, #0
|
|
8007cd8: d101 bne.n 8007cde <USBD_LL_IsoOUTIncomplete+0x22>
|
|
{
|
|
return USBD_FAIL;
|
|
8007cda: 2303 movs r3, #3
|
|
8007cdc: e01c b.n 8007d18 <USBD_LL_IsoOUTIncomplete+0x5c>
|
|
}
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007cde: 687b ldr r3, [r7, #4]
|
|
8007ce0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007ce4: b2db uxtb r3, r3
|
|
8007ce6: 2b03 cmp r3, #3
|
|
8007ce8: d115 bne.n 8007d16 <USBD_LL_IsoOUTIncomplete+0x5a>
|
|
{
|
|
if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL)
|
|
8007cea: 687b ldr r3, [r7, #4]
|
|
8007cec: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007cf0: 687b ldr r3, [r7, #4]
|
|
8007cf2: 32ae adds r2, #174 @ 0xae
|
|
8007cf4: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007cf8: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007cfa: 2b00 cmp r3, #0
|
|
8007cfc: d00b beq.n 8007d16 <USBD_LL_IsoOUTIncomplete+0x5a>
|
|
{
|
|
(void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum);
|
|
8007cfe: 687b ldr r3, [r7, #4]
|
|
8007d00: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007d04: 687b ldr r3, [r7, #4]
|
|
8007d06: 32ae adds r2, #174 @ 0xae
|
|
8007d08: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007d0c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007d0e: 78fa ldrb r2, [r7, #3]
|
|
8007d10: 4611 mov r1, r2
|
|
8007d12: 6878 ldr r0, [r7, #4]
|
|
8007d14: 4798 blx r3
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007d16: 2300 movs r3, #0
|
|
}
|
|
8007d18: 4618 mov r0, r3
|
|
8007d1a: 3708 adds r7, #8
|
|
8007d1c: 46bd mov sp, r7
|
|
8007d1e: bd80 pop {r7, pc}
|
|
|
|
08007d20 <USBD_LL_DevConnected>:
|
|
* Handle device connection event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007d20: b480 push {r7}
|
|
8007d22: b083 sub sp, #12
|
|
8007d24: af00 add r7, sp, #0
|
|
8007d26: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument compilation warning */
|
|
UNUSED(pdev);
|
|
|
|
return USBD_OK;
|
|
8007d28: 2300 movs r3, #0
|
|
}
|
|
8007d2a: 4618 mov r0, r3
|
|
8007d2c: 370c adds r7, #12
|
|
8007d2e: 46bd mov sp, r7
|
|
8007d30: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007d34: 4770 bx lr
|
|
|
|
08007d36 <USBD_LL_DevDisconnected>:
|
|
* Handle device disconnection event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007d36: b580 push {r7, lr}
|
|
8007d38: b084 sub sp, #16
|
|
8007d3a: af00 add r7, sp, #0
|
|
8007d3c: 6078 str r0, [r7, #4]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007d3e: 2300 movs r3, #0
|
|
8007d40: 73fb strb r3, [r7, #15]
|
|
|
|
/* Free Class Resources */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8007d42: 687b ldr r3, [r7, #4]
|
|
8007d44: 2201 movs r2, #1
|
|
8007d46: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
8007d4a: 687b ldr r3, [r7, #4]
|
|
8007d4c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007d50: 2b00 cmp r3, #0
|
|
8007d52: d00e beq.n 8007d72 <USBD_LL_DevDisconnected+0x3c>
|
|
{
|
|
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U)
|
|
8007d54: 687b ldr r3, [r7, #4]
|
|
8007d56: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007d5a: 685b ldr r3, [r3, #4]
|
|
8007d5c: 687a ldr r2, [r7, #4]
|
|
8007d5e: 6852 ldr r2, [r2, #4]
|
|
8007d60: b2d2 uxtb r2, r2
|
|
8007d62: 4611 mov r1, r2
|
|
8007d64: 6878 ldr r0, [r7, #4]
|
|
8007d66: 4798 blx r3
|
|
8007d68: 4603 mov r3, r0
|
|
8007d6a: 2b00 cmp r3, #0
|
|
8007d6c: d001 beq.n 8007d72 <USBD_LL_DevDisconnected+0x3c>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8007d6e: 2303 movs r3, #3
|
|
8007d70: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8007d72: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007d74: 4618 mov r0, r3
|
|
8007d76: 3710 adds r7, #16
|
|
8007d78: 46bd mov sp, r7
|
|
8007d7a: bd80 pop {r7, pc}
|
|
|
|
08007d7c <USBD_CoreFindIF>:
|
|
* @param pdev: device instance
|
|
* @param index : selected interface number
|
|
* @retval index of the class using the selected interface number. OxFF if no class found.
|
|
*/
|
|
uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index)
|
|
{
|
|
8007d7c: b480 push {r7}
|
|
8007d7e: b083 sub sp, #12
|
|
8007d80: af00 add r7, sp, #0
|
|
8007d82: 6078 str r0, [r7, #4]
|
|
8007d84: 460b mov r3, r1
|
|
8007d86: 70fb strb r3, [r7, #3]
|
|
return 0xFFU;
|
|
#else
|
|
UNUSED(pdev);
|
|
UNUSED(index);
|
|
|
|
return 0x00U;
|
|
8007d88: 2300 movs r3, #0
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
8007d8a: 4618 mov r0, r3
|
|
8007d8c: 370c adds r7, #12
|
|
8007d8e: 46bd mov sp, r7
|
|
8007d90: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007d94: 4770 bx lr
|
|
|
|
08007d96 <USBD_CoreFindEP>:
|
|
* @param pdev: device instance
|
|
* @param index : selected endpoint number
|
|
* @retval index of the class using the selected endpoint number. 0xFF if no class found.
|
|
*/
|
|
uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index)
|
|
{
|
|
8007d96: b480 push {r7}
|
|
8007d98: b083 sub sp, #12
|
|
8007d9a: af00 add r7, sp, #0
|
|
8007d9c: 6078 str r0, [r7, #4]
|
|
8007d9e: 460b mov r3, r1
|
|
8007da0: 70fb strb r3, [r7, #3]
|
|
return 0xFFU;
|
|
#else
|
|
UNUSED(pdev);
|
|
UNUSED(index);
|
|
|
|
return 0x00U;
|
|
8007da2: 2300 movs r3, #0
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
8007da4: 4618 mov r0, r3
|
|
8007da6: 370c adds r7, #12
|
|
8007da8: 46bd mov sp, r7
|
|
8007daa: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007dae: 4770 bx lr
|
|
|
|
08007db0 <USBD_GetEpDesc>:
|
|
* @param pConfDesc: pointer to Bos descriptor
|
|
* @param EpAddr: endpoint address
|
|
* @retval pointer to video endpoint descriptor
|
|
*/
|
|
void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr)
|
|
{
|
|
8007db0: b580 push {r7, lr}
|
|
8007db2: b086 sub sp, #24
|
|
8007db4: af00 add r7, sp, #0
|
|
8007db6: 6078 str r0, [r7, #4]
|
|
8007db8: 460b mov r3, r1
|
|
8007dba: 70fb strb r3, [r7, #3]
|
|
USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc;
|
|
8007dbc: 687b ldr r3, [r7, #4]
|
|
8007dbe: 617b str r3, [r7, #20]
|
|
USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc;
|
|
8007dc0: 687b ldr r3, [r7, #4]
|
|
8007dc2: 60fb str r3, [r7, #12]
|
|
USBD_EpDescTypeDef *pEpDesc = NULL;
|
|
8007dc4: 2300 movs r3, #0
|
|
8007dc6: 613b str r3, [r7, #16]
|
|
uint16_t ptr;
|
|
|
|
if (desc->wTotalLength > desc->bLength)
|
|
8007dc8: 68fb ldr r3, [r7, #12]
|
|
8007dca: 885b ldrh r3, [r3, #2]
|
|
8007dcc: b29b uxth r3, r3
|
|
8007dce: 68fa ldr r2, [r7, #12]
|
|
8007dd0: 7812 ldrb r2, [r2, #0]
|
|
8007dd2: 4293 cmp r3, r2
|
|
8007dd4: d91f bls.n 8007e16 <USBD_GetEpDesc+0x66>
|
|
{
|
|
ptr = desc->bLength;
|
|
8007dd6: 68fb ldr r3, [r7, #12]
|
|
8007dd8: 781b ldrb r3, [r3, #0]
|
|
8007dda: 817b strh r3, [r7, #10]
|
|
|
|
while (ptr < desc->wTotalLength)
|
|
8007ddc: e013 b.n 8007e06 <USBD_GetEpDesc+0x56>
|
|
{
|
|
pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr);
|
|
8007dde: f107 030a add.w r3, r7, #10
|
|
8007de2: 4619 mov r1, r3
|
|
8007de4: 6978 ldr r0, [r7, #20]
|
|
8007de6: f000 f81b bl 8007e20 <USBD_GetNextDesc>
|
|
8007dea: 6178 str r0, [r7, #20]
|
|
|
|
if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT)
|
|
8007dec: 697b ldr r3, [r7, #20]
|
|
8007dee: 785b ldrb r3, [r3, #1]
|
|
8007df0: 2b05 cmp r3, #5
|
|
8007df2: d108 bne.n 8007e06 <USBD_GetEpDesc+0x56>
|
|
{
|
|
pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc;
|
|
8007df4: 697b ldr r3, [r7, #20]
|
|
8007df6: 613b str r3, [r7, #16]
|
|
|
|
if (pEpDesc->bEndpointAddress == EpAddr)
|
|
8007df8: 693b ldr r3, [r7, #16]
|
|
8007dfa: 789b ldrb r3, [r3, #2]
|
|
8007dfc: 78fa ldrb r2, [r7, #3]
|
|
8007dfe: 429a cmp r2, r3
|
|
8007e00: d008 beq.n 8007e14 <USBD_GetEpDesc+0x64>
|
|
{
|
|
break;
|
|
}
|
|
else
|
|
{
|
|
pEpDesc = NULL;
|
|
8007e02: 2300 movs r3, #0
|
|
8007e04: 613b str r3, [r7, #16]
|
|
while (ptr < desc->wTotalLength)
|
|
8007e06: 68fb ldr r3, [r7, #12]
|
|
8007e08: 885b ldrh r3, [r3, #2]
|
|
8007e0a: b29a uxth r2, r3
|
|
8007e0c: 897b ldrh r3, [r7, #10]
|
|
8007e0e: 429a cmp r2, r3
|
|
8007e10: d8e5 bhi.n 8007dde <USBD_GetEpDesc+0x2e>
|
|
8007e12: e000 b.n 8007e16 <USBD_GetEpDesc+0x66>
|
|
break;
|
|
8007e14: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return (void *)pEpDesc;
|
|
8007e16: 693b ldr r3, [r7, #16]
|
|
}
|
|
8007e18: 4618 mov r0, r3
|
|
8007e1a: 3718 adds r7, #24
|
|
8007e1c: 46bd mov sp, r7
|
|
8007e1e: bd80 pop {r7, pc}
|
|
|
|
08007e20 <USBD_GetNextDesc>:
|
|
* @param buf: Buffer where the descriptor is available
|
|
* @param ptr: data pointer inside the descriptor
|
|
* @retval next header
|
|
*/
|
|
USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr)
|
|
{
|
|
8007e20: b480 push {r7}
|
|
8007e22: b085 sub sp, #20
|
|
8007e24: af00 add r7, sp, #0
|
|
8007e26: 6078 str r0, [r7, #4]
|
|
8007e28: 6039 str r1, [r7, #0]
|
|
USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf;
|
|
8007e2a: 687b ldr r3, [r7, #4]
|
|
8007e2c: 60fb str r3, [r7, #12]
|
|
|
|
*ptr += pnext->bLength;
|
|
8007e2e: 683b ldr r3, [r7, #0]
|
|
8007e30: 881b ldrh r3, [r3, #0]
|
|
8007e32: 68fa ldr r2, [r7, #12]
|
|
8007e34: 7812 ldrb r2, [r2, #0]
|
|
8007e36: 4413 add r3, r2
|
|
8007e38: b29a uxth r2, r3
|
|
8007e3a: 683b ldr r3, [r7, #0]
|
|
8007e3c: 801a strh r2, [r3, #0]
|
|
pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength);
|
|
8007e3e: 68fb ldr r3, [r7, #12]
|
|
8007e40: 781b ldrb r3, [r3, #0]
|
|
8007e42: 461a mov r2, r3
|
|
8007e44: 687b ldr r3, [r7, #4]
|
|
8007e46: 4413 add r3, r2
|
|
8007e48: 60fb str r3, [r7, #12]
|
|
|
|
return (pnext);
|
|
8007e4a: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8007e4c: 4618 mov r0, r3
|
|
8007e4e: 3714 adds r7, #20
|
|
8007e50: 46bd mov sp, r7
|
|
8007e52: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007e56: 4770 bx lr
|
|
|
|
08007e58 <SWAPBYTE>:
|
|
|
|
/** @defgroup USBD_DEF_Exported_Macros
|
|
* @{
|
|
*/
|
|
__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
|
|
{
|
|
8007e58: b480 push {r7}
|
|
8007e5a: b087 sub sp, #28
|
|
8007e5c: af00 add r7, sp, #0
|
|
8007e5e: 6078 str r0, [r7, #4]
|
|
uint16_t _SwapVal;
|
|
uint16_t _Byte1;
|
|
uint16_t _Byte2;
|
|
uint8_t *_pbuff = addr;
|
|
8007e60: 687b ldr r3, [r7, #4]
|
|
8007e62: 617b str r3, [r7, #20]
|
|
|
|
_Byte1 = *(uint8_t *)_pbuff;
|
|
8007e64: 697b ldr r3, [r7, #20]
|
|
8007e66: 781b ldrb r3, [r3, #0]
|
|
8007e68: 827b strh r3, [r7, #18]
|
|
_pbuff++;
|
|
8007e6a: 697b ldr r3, [r7, #20]
|
|
8007e6c: 3301 adds r3, #1
|
|
8007e6e: 617b str r3, [r7, #20]
|
|
_Byte2 = *(uint8_t *)_pbuff;
|
|
8007e70: 697b ldr r3, [r7, #20]
|
|
8007e72: 781b ldrb r3, [r3, #0]
|
|
8007e74: 823b strh r3, [r7, #16]
|
|
|
|
_SwapVal = (_Byte2 << 8) | _Byte1;
|
|
8007e76: f9b7 3010 ldrsh.w r3, [r7, #16]
|
|
8007e7a: 021b lsls r3, r3, #8
|
|
8007e7c: b21a sxth r2, r3
|
|
8007e7e: f9b7 3012 ldrsh.w r3, [r7, #18]
|
|
8007e82: 4313 orrs r3, r2
|
|
8007e84: b21b sxth r3, r3
|
|
8007e86: 81fb strh r3, [r7, #14]
|
|
|
|
return _SwapVal;
|
|
8007e88: 89fb ldrh r3, [r7, #14]
|
|
}
|
|
8007e8a: 4618 mov r0, r3
|
|
8007e8c: 371c adds r7, #28
|
|
8007e8e: 46bd mov sp, r7
|
|
8007e90: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007e94: 4770 bx lr
|
|
...
|
|
|
|
08007e98 <USBD_StdDevReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007e98: b580 push {r7, lr}
|
|
8007e9a: b084 sub sp, #16
|
|
8007e9c: af00 add r7, sp, #0
|
|
8007e9e: 6078 str r0, [r7, #4]
|
|
8007ea0: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007ea2: 2300 movs r3, #0
|
|
8007ea4: 73fb strb r3, [r7, #15]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8007ea6: 683b ldr r3, [r7, #0]
|
|
8007ea8: 781b ldrb r3, [r3, #0]
|
|
8007eaa: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8007eae: 2b40 cmp r3, #64 @ 0x40
|
|
8007eb0: d005 beq.n 8007ebe <USBD_StdDevReq+0x26>
|
|
8007eb2: 2b40 cmp r3, #64 @ 0x40
|
|
8007eb4: d857 bhi.n 8007f66 <USBD_StdDevReq+0xce>
|
|
8007eb6: 2b00 cmp r3, #0
|
|
8007eb8: d00f beq.n 8007eda <USBD_StdDevReq+0x42>
|
|
8007eba: 2b20 cmp r3, #32
|
|
8007ebc: d153 bne.n 8007f66 <USBD_StdDevReq+0xce>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req);
|
|
8007ebe: 687b ldr r3, [r7, #4]
|
|
8007ec0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007ec4: 687b ldr r3, [r7, #4]
|
|
8007ec6: 32ae adds r2, #174 @ 0xae
|
|
8007ec8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007ecc: 689b ldr r3, [r3, #8]
|
|
8007ece: 6839 ldr r1, [r7, #0]
|
|
8007ed0: 6878 ldr r0, [r7, #4]
|
|
8007ed2: 4798 blx r3
|
|
8007ed4: 4603 mov r3, r0
|
|
8007ed6: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8007ed8: e04a b.n 8007f70 <USBD_StdDevReq+0xd8>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
8007eda: 683b ldr r3, [r7, #0]
|
|
8007edc: 785b ldrb r3, [r3, #1]
|
|
8007ede: 2b09 cmp r3, #9
|
|
8007ee0: d83b bhi.n 8007f5a <USBD_StdDevReq+0xc2>
|
|
8007ee2: a201 add r2, pc, #4 @ (adr r2, 8007ee8 <USBD_StdDevReq+0x50>)
|
|
8007ee4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8007ee8: 08007f3d .word 0x08007f3d
|
|
8007eec: 08007f51 .word 0x08007f51
|
|
8007ef0: 08007f5b .word 0x08007f5b
|
|
8007ef4: 08007f47 .word 0x08007f47
|
|
8007ef8: 08007f5b .word 0x08007f5b
|
|
8007efc: 08007f1b .word 0x08007f1b
|
|
8007f00: 08007f11 .word 0x08007f11
|
|
8007f04: 08007f5b .word 0x08007f5b
|
|
8007f08: 08007f33 .word 0x08007f33
|
|
8007f0c: 08007f25 .word 0x08007f25
|
|
{
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
USBD_GetDescriptor(pdev, req);
|
|
8007f10: 6839 ldr r1, [r7, #0]
|
|
8007f12: 6878 ldr r0, [r7, #4]
|
|
8007f14: f000 fa3e bl 8008394 <USBD_GetDescriptor>
|
|
break;
|
|
8007f18: e024 b.n 8007f64 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_ADDRESS:
|
|
USBD_SetAddress(pdev, req);
|
|
8007f1a: 6839 ldr r1, [r7, #0]
|
|
8007f1c: 6878 ldr r0, [r7, #4]
|
|
8007f1e: f000 fbcd bl 80086bc <USBD_SetAddress>
|
|
break;
|
|
8007f22: e01f b.n 8007f64 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_CONFIGURATION:
|
|
ret = USBD_SetConfig(pdev, req);
|
|
8007f24: 6839 ldr r1, [r7, #0]
|
|
8007f26: 6878 ldr r0, [r7, #4]
|
|
8007f28: f000 fc0c bl 8008744 <USBD_SetConfig>
|
|
8007f2c: 4603 mov r3, r0
|
|
8007f2e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8007f30: e018 b.n 8007f64 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_GET_CONFIGURATION:
|
|
USBD_GetConfig(pdev, req);
|
|
8007f32: 6839 ldr r1, [r7, #0]
|
|
8007f34: 6878 ldr r0, [r7, #4]
|
|
8007f36: f000 fcaf bl 8008898 <USBD_GetConfig>
|
|
break;
|
|
8007f3a: e013 b.n 8007f64 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
USBD_GetStatus(pdev, req);
|
|
8007f3c: 6839 ldr r1, [r7, #0]
|
|
8007f3e: 6878 ldr r0, [r7, #4]
|
|
8007f40: f000 fce0 bl 8008904 <USBD_GetStatus>
|
|
break;
|
|
8007f44: e00e b.n 8007f64 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_FEATURE:
|
|
USBD_SetFeature(pdev, req);
|
|
8007f46: 6839 ldr r1, [r7, #0]
|
|
8007f48: 6878 ldr r0, [r7, #4]
|
|
8007f4a: f000 fd0f bl 800896c <USBD_SetFeature>
|
|
break;
|
|
8007f4e: e009 b.n 8007f64 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
USBD_ClrFeature(pdev, req);
|
|
8007f50: 6839 ldr r1, [r7, #0]
|
|
8007f52: 6878 ldr r0, [r7, #4]
|
|
8007f54: f000 fd33 bl 80089be <USBD_ClrFeature>
|
|
break;
|
|
8007f58: e004 b.n 8007f64 <USBD_StdDevReq+0xcc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007f5a: 6839 ldr r1, [r7, #0]
|
|
8007f5c: 6878 ldr r0, [r7, #4]
|
|
8007f5e: f000 fd8a bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
8007f62: bf00 nop
|
|
}
|
|
break;
|
|
8007f64: e004 b.n 8007f70 <USBD_StdDevReq+0xd8>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007f66: 6839 ldr r1, [r7, #0]
|
|
8007f68: 6878 ldr r0, [r7, #4]
|
|
8007f6a: f000 fd84 bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
8007f6e: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8007f70: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007f72: 4618 mov r0, r3
|
|
8007f74: 3710 adds r7, #16
|
|
8007f76: 46bd mov sp, r7
|
|
8007f78: bd80 pop {r7, pc}
|
|
8007f7a: bf00 nop
|
|
|
|
08007f7c <USBD_StdItfReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007f7c: b580 push {r7, lr}
|
|
8007f7e: b084 sub sp, #16
|
|
8007f80: af00 add r7, sp, #0
|
|
8007f82: 6078 str r0, [r7, #4]
|
|
8007f84: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007f86: 2300 movs r3, #0
|
|
8007f88: 73fb strb r3, [r7, #15]
|
|
uint8_t idx;
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8007f8a: 683b ldr r3, [r7, #0]
|
|
8007f8c: 781b ldrb r3, [r3, #0]
|
|
8007f8e: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8007f92: 2b40 cmp r3, #64 @ 0x40
|
|
8007f94: d005 beq.n 8007fa2 <USBD_StdItfReq+0x26>
|
|
8007f96: 2b40 cmp r3, #64 @ 0x40
|
|
8007f98: d852 bhi.n 8008040 <USBD_StdItfReq+0xc4>
|
|
8007f9a: 2b00 cmp r3, #0
|
|
8007f9c: d001 beq.n 8007fa2 <USBD_StdItfReq+0x26>
|
|
8007f9e: 2b20 cmp r3, #32
|
|
8007fa0: d14e bne.n 8008040 <USBD_StdItfReq+0xc4>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (pdev->dev_state)
|
|
8007fa2: 687b ldr r3, [r7, #4]
|
|
8007fa4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007fa8: b2db uxtb r3, r3
|
|
8007faa: 3b01 subs r3, #1
|
|
8007fac: 2b02 cmp r3, #2
|
|
8007fae: d840 bhi.n 8008032 <USBD_StdItfReq+0xb6>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
|
|
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
|
|
8007fb0: 683b ldr r3, [r7, #0]
|
|
8007fb2: 889b ldrh r3, [r3, #4]
|
|
8007fb4: b2db uxtb r3, r3
|
|
8007fb6: 2b01 cmp r3, #1
|
|
8007fb8: d836 bhi.n 8008028 <USBD_StdItfReq+0xac>
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex));
|
|
8007fba: 683b ldr r3, [r7, #0]
|
|
8007fbc: 889b ldrh r3, [r3, #4]
|
|
8007fbe: b2db uxtb r3, r3
|
|
8007fc0: 4619 mov r1, r3
|
|
8007fc2: 6878 ldr r0, [r7, #4]
|
|
8007fc4: f7ff feda bl 8007d7c <USBD_CoreFindIF>
|
|
8007fc8: 4603 mov r3, r0
|
|
8007fca: 73bb strb r3, [r7, #14]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8007fcc: 7bbb ldrb r3, [r7, #14]
|
|
8007fce: 2bff cmp r3, #255 @ 0xff
|
|
8007fd0: d01d beq.n 800800e <USBD_StdItfReq+0x92>
|
|
8007fd2: 7bbb ldrb r3, [r7, #14]
|
|
8007fd4: 2b00 cmp r3, #0
|
|
8007fd6: d11a bne.n 800800e <USBD_StdItfReq+0x92>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8007fd8: 7bba ldrb r2, [r7, #14]
|
|
8007fda: 687b ldr r3, [r7, #4]
|
|
8007fdc: 32ae adds r2, #174 @ 0xae
|
|
8007fde: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007fe2: 689b ldr r3, [r3, #8]
|
|
8007fe4: 2b00 cmp r3, #0
|
|
8007fe6: d00f beq.n 8008008 <USBD_StdItfReq+0x8c>
|
|
{
|
|
pdev->classId = idx;
|
|
8007fe8: 7bba ldrb r2, [r7, #14]
|
|
8007fea: 687b ldr r3, [r7, #4]
|
|
8007fec: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
|
|
8007ff0: 7bba ldrb r2, [r7, #14]
|
|
8007ff2: 687b ldr r3, [r7, #4]
|
|
8007ff4: 32ae adds r2, #174 @ 0xae
|
|
8007ff6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007ffa: 689b ldr r3, [r3, #8]
|
|
8007ffc: 6839 ldr r1, [r7, #0]
|
|
8007ffe: 6878 ldr r0, [r7, #4]
|
|
8008000: 4798 blx r3
|
|
8008002: 4603 mov r3, r0
|
|
8008004: 73fb strb r3, [r7, #15]
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8008006: e004 b.n 8008012 <USBD_StdItfReq+0x96>
|
|
}
|
|
else
|
|
{
|
|
/* should never reach this condition */
|
|
ret = USBD_FAIL;
|
|
8008008: 2303 movs r3, #3
|
|
800800a: 73fb strb r3, [r7, #15]
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
800800c: e001 b.n 8008012 <USBD_StdItfReq+0x96>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* No relative interface found */
|
|
ret = USBD_FAIL;
|
|
800800e: 2303 movs r3, #3
|
|
8008010: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
if ((req->wLength == 0U) && (ret == USBD_OK))
|
|
8008012: 683b ldr r3, [r7, #0]
|
|
8008014: 88db ldrh r3, [r3, #6]
|
|
8008016: 2b00 cmp r3, #0
|
|
8008018: d110 bne.n 800803c <USBD_StdItfReq+0xc0>
|
|
800801a: 7bfb ldrb r3, [r7, #15]
|
|
800801c: 2b00 cmp r3, #0
|
|
800801e: d10d bne.n 800803c <USBD_StdItfReq+0xc0>
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8008020: 6878 ldr r0, [r7, #4]
|
|
8008022: f000 fde5 bl 8008bf0 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
8008026: e009 b.n 800803c <USBD_StdItfReq+0xc0>
|
|
USBD_CtlError(pdev, req);
|
|
8008028: 6839 ldr r1, [r7, #0]
|
|
800802a: 6878 ldr r0, [r7, #4]
|
|
800802c: f000 fd23 bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
8008030: e004 b.n 800803c <USBD_StdItfReq+0xc0>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008032: 6839 ldr r1, [r7, #0]
|
|
8008034: 6878 ldr r0, [r7, #4]
|
|
8008036: f000 fd1e bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
800803a: e000 b.n 800803e <USBD_StdItfReq+0xc2>
|
|
break;
|
|
800803c: bf00 nop
|
|
}
|
|
break;
|
|
800803e: e004 b.n 800804a <USBD_StdItfReq+0xce>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008040: 6839 ldr r1, [r7, #0]
|
|
8008042: 6878 ldr r0, [r7, #4]
|
|
8008044: f000 fd17 bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
8008048: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
800804a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800804c: 4618 mov r0, r3
|
|
800804e: 3710 adds r7, #16
|
|
8008050: 46bd mov sp, r7
|
|
8008052: bd80 pop {r7, pc}
|
|
|
|
08008054 <USBD_StdEPReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008054: b580 push {r7, lr}
|
|
8008056: b084 sub sp, #16
|
|
8008058: af00 add r7, sp, #0
|
|
800805a: 6078 str r0, [r7, #4]
|
|
800805c: 6039 str r1, [r7, #0]
|
|
USBD_EndpointTypeDef *pep;
|
|
uint8_t ep_addr;
|
|
uint8_t idx;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
800805e: 2300 movs r3, #0
|
|
8008060: 73fb strb r3, [r7, #15]
|
|
|
|
ep_addr = LOBYTE(req->wIndex);
|
|
8008062: 683b ldr r3, [r7, #0]
|
|
8008064: 889b ldrh r3, [r3, #4]
|
|
8008066: 73bb strb r3, [r7, #14]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8008068: 683b ldr r3, [r7, #0]
|
|
800806a: 781b ldrb r3, [r3, #0]
|
|
800806c: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8008070: 2b40 cmp r3, #64 @ 0x40
|
|
8008072: d007 beq.n 8008084 <USBD_StdEPReq+0x30>
|
|
8008074: 2b40 cmp r3, #64 @ 0x40
|
|
8008076: f200 8181 bhi.w 800837c <USBD_StdEPReq+0x328>
|
|
800807a: 2b00 cmp r3, #0
|
|
800807c: d02a beq.n 80080d4 <USBD_StdEPReq+0x80>
|
|
800807e: 2b20 cmp r3, #32
|
|
8008080: f040 817c bne.w 800837c <USBD_StdEPReq+0x328>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
/* Get the class index relative to this endpoint */
|
|
idx = USBD_CoreFindEP(pdev, ep_addr);
|
|
8008084: 7bbb ldrb r3, [r7, #14]
|
|
8008086: 4619 mov r1, r3
|
|
8008088: 6878 ldr r0, [r7, #4]
|
|
800808a: f7ff fe84 bl 8007d96 <USBD_CoreFindEP>
|
|
800808e: 4603 mov r3, r0
|
|
8008090: 737b strb r3, [r7, #13]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8008092: 7b7b ldrb r3, [r7, #13]
|
|
8008094: 2bff cmp r3, #255 @ 0xff
|
|
8008096: f000 8176 beq.w 8008386 <USBD_StdEPReq+0x332>
|
|
800809a: 7b7b ldrb r3, [r7, #13]
|
|
800809c: 2b00 cmp r3, #0
|
|
800809e: f040 8172 bne.w 8008386 <USBD_StdEPReq+0x332>
|
|
{
|
|
pdev->classId = idx;
|
|
80080a2: 7b7a ldrb r2, [r7, #13]
|
|
80080a4: 687b ldr r3, [r7, #4]
|
|
80080a6: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
80080aa: 7b7a ldrb r2, [r7, #13]
|
|
80080ac: 687b ldr r3, [r7, #4]
|
|
80080ae: 32ae adds r2, #174 @ 0xae
|
|
80080b0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80080b4: 689b ldr r3, [r3, #8]
|
|
80080b6: 2b00 cmp r3, #0
|
|
80080b8: f000 8165 beq.w 8008386 <USBD_StdEPReq+0x332>
|
|
{
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req);
|
|
80080bc: 7b7a ldrb r2, [r7, #13]
|
|
80080be: 687b ldr r3, [r7, #4]
|
|
80080c0: 32ae adds r2, #174 @ 0xae
|
|
80080c2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80080c6: 689b ldr r3, [r3, #8]
|
|
80080c8: 6839 ldr r1, [r7, #0]
|
|
80080ca: 6878 ldr r0, [r7, #4]
|
|
80080cc: 4798 blx r3
|
|
80080ce: 4603 mov r3, r0
|
|
80080d0: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
80080d2: e158 b.n 8008386 <USBD_StdEPReq+0x332>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
80080d4: 683b ldr r3, [r7, #0]
|
|
80080d6: 785b ldrb r3, [r3, #1]
|
|
80080d8: 2b03 cmp r3, #3
|
|
80080da: d008 beq.n 80080ee <USBD_StdEPReq+0x9a>
|
|
80080dc: 2b03 cmp r3, #3
|
|
80080de: f300 8147 bgt.w 8008370 <USBD_StdEPReq+0x31c>
|
|
80080e2: 2b00 cmp r3, #0
|
|
80080e4: f000 809b beq.w 800821e <USBD_StdEPReq+0x1ca>
|
|
80080e8: 2b01 cmp r3, #1
|
|
80080ea: d03c beq.n 8008166 <USBD_StdEPReq+0x112>
|
|
80080ec: e140 b.n 8008370 <USBD_StdEPReq+0x31c>
|
|
{
|
|
case USB_REQ_SET_FEATURE:
|
|
switch (pdev->dev_state)
|
|
80080ee: 687b ldr r3, [r7, #4]
|
|
80080f0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80080f4: b2db uxtb r3, r3
|
|
80080f6: 2b02 cmp r3, #2
|
|
80080f8: d002 beq.n 8008100 <USBD_StdEPReq+0xac>
|
|
80080fa: 2b03 cmp r3, #3
|
|
80080fc: d016 beq.n 800812c <USBD_StdEPReq+0xd8>
|
|
80080fe: e02c b.n 800815a <USBD_StdEPReq+0x106>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
8008100: 7bbb ldrb r3, [r7, #14]
|
|
8008102: 2b00 cmp r3, #0
|
|
8008104: d00d beq.n 8008122 <USBD_StdEPReq+0xce>
|
|
8008106: 7bbb ldrb r3, [r7, #14]
|
|
8008108: 2b80 cmp r3, #128 @ 0x80
|
|
800810a: d00a beq.n 8008122 <USBD_StdEPReq+0xce>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
800810c: 7bbb ldrb r3, [r7, #14]
|
|
800810e: 4619 mov r1, r3
|
|
8008110: 6878 ldr r0, [r7, #4]
|
|
8008112: f001 f8e3 bl 80092dc <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8008116: 2180 movs r1, #128 @ 0x80
|
|
8008118: 6878 ldr r0, [r7, #4]
|
|
800811a: f001 f8df bl 80092dc <USBD_LL_StallEP>
|
|
800811e: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
8008120: e020 b.n 8008164 <USBD_StdEPReq+0x110>
|
|
USBD_CtlError(pdev, req);
|
|
8008122: 6839 ldr r1, [r7, #0]
|
|
8008124: 6878 ldr r0, [r7, #4]
|
|
8008126: f000 fca6 bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
800812a: e01b b.n 8008164 <USBD_StdEPReq+0x110>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
800812c: 683b ldr r3, [r7, #0]
|
|
800812e: 885b ldrh r3, [r3, #2]
|
|
8008130: 2b00 cmp r3, #0
|
|
8008132: d10e bne.n 8008152 <USBD_StdEPReq+0xfe>
|
|
{
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U))
|
|
8008134: 7bbb ldrb r3, [r7, #14]
|
|
8008136: 2b00 cmp r3, #0
|
|
8008138: d00b beq.n 8008152 <USBD_StdEPReq+0xfe>
|
|
800813a: 7bbb ldrb r3, [r7, #14]
|
|
800813c: 2b80 cmp r3, #128 @ 0x80
|
|
800813e: d008 beq.n 8008152 <USBD_StdEPReq+0xfe>
|
|
8008140: 683b ldr r3, [r7, #0]
|
|
8008142: 88db ldrh r3, [r3, #6]
|
|
8008144: 2b00 cmp r3, #0
|
|
8008146: d104 bne.n 8008152 <USBD_StdEPReq+0xfe>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
8008148: 7bbb ldrb r3, [r7, #14]
|
|
800814a: 4619 mov r1, r3
|
|
800814c: 6878 ldr r0, [r7, #4]
|
|
800814e: f001 f8c5 bl 80092dc <USBD_LL_StallEP>
|
|
}
|
|
}
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8008152: 6878 ldr r0, [r7, #4]
|
|
8008154: f000 fd4c bl 8008bf0 <USBD_CtlSendStatus>
|
|
|
|
break;
|
|
8008158: e004 b.n 8008164 <USBD_StdEPReq+0x110>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800815a: 6839 ldr r1, [r7, #0]
|
|
800815c: 6878 ldr r0, [r7, #4]
|
|
800815e: f000 fc8a bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
8008162: bf00 nop
|
|
}
|
|
break;
|
|
8008164: e109 b.n 800837a <USBD_StdEPReq+0x326>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
|
|
switch (pdev->dev_state)
|
|
8008166: 687b ldr r3, [r7, #4]
|
|
8008168: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
800816c: b2db uxtb r3, r3
|
|
800816e: 2b02 cmp r3, #2
|
|
8008170: d002 beq.n 8008178 <USBD_StdEPReq+0x124>
|
|
8008172: 2b03 cmp r3, #3
|
|
8008174: d016 beq.n 80081a4 <USBD_StdEPReq+0x150>
|
|
8008176: e04b b.n 8008210 <USBD_StdEPReq+0x1bc>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
8008178: 7bbb ldrb r3, [r7, #14]
|
|
800817a: 2b00 cmp r3, #0
|
|
800817c: d00d beq.n 800819a <USBD_StdEPReq+0x146>
|
|
800817e: 7bbb ldrb r3, [r7, #14]
|
|
8008180: 2b80 cmp r3, #128 @ 0x80
|
|
8008182: d00a beq.n 800819a <USBD_StdEPReq+0x146>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
8008184: 7bbb ldrb r3, [r7, #14]
|
|
8008186: 4619 mov r1, r3
|
|
8008188: 6878 ldr r0, [r7, #4]
|
|
800818a: f001 f8a7 bl 80092dc <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
800818e: 2180 movs r1, #128 @ 0x80
|
|
8008190: 6878 ldr r0, [r7, #4]
|
|
8008192: f001 f8a3 bl 80092dc <USBD_LL_StallEP>
|
|
8008196: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
8008198: e040 b.n 800821c <USBD_StdEPReq+0x1c8>
|
|
USBD_CtlError(pdev, req);
|
|
800819a: 6839 ldr r1, [r7, #0]
|
|
800819c: 6878 ldr r0, [r7, #4]
|
|
800819e: f000 fc6a bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
80081a2: e03b b.n 800821c <USBD_StdEPReq+0x1c8>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
80081a4: 683b ldr r3, [r7, #0]
|
|
80081a6: 885b ldrh r3, [r3, #2]
|
|
80081a8: 2b00 cmp r3, #0
|
|
80081aa: d136 bne.n 800821a <USBD_StdEPReq+0x1c6>
|
|
{
|
|
if ((ep_addr & 0x7FU) != 0x00U)
|
|
80081ac: 7bbb ldrb r3, [r7, #14]
|
|
80081ae: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
80081b2: 2b00 cmp r3, #0
|
|
80081b4: d004 beq.n 80081c0 <USBD_StdEPReq+0x16c>
|
|
{
|
|
(void)USBD_LL_ClearStallEP(pdev, ep_addr);
|
|
80081b6: 7bbb ldrb r3, [r7, #14]
|
|
80081b8: 4619 mov r1, r3
|
|
80081ba: 6878 ldr r0, [r7, #4]
|
|
80081bc: f001 f8ad bl 800931a <USBD_LL_ClearStallEP>
|
|
}
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80081c0: 6878 ldr r0, [r7, #4]
|
|
80081c2: f000 fd15 bl 8008bf0 <USBD_CtlSendStatus>
|
|
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, ep_addr);
|
|
80081c6: 7bbb ldrb r3, [r7, #14]
|
|
80081c8: 4619 mov r1, r3
|
|
80081ca: 6878 ldr r0, [r7, #4]
|
|
80081cc: f7ff fde3 bl 8007d96 <USBD_CoreFindEP>
|
|
80081d0: 4603 mov r3, r0
|
|
80081d2: 737b strb r3, [r7, #13]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
80081d4: 7b7b ldrb r3, [r7, #13]
|
|
80081d6: 2bff cmp r3, #255 @ 0xff
|
|
80081d8: d01f beq.n 800821a <USBD_StdEPReq+0x1c6>
|
|
80081da: 7b7b ldrb r3, [r7, #13]
|
|
80081dc: 2b00 cmp r3, #0
|
|
80081de: d11c bne.n 800821a <USBD_StdEPReq+0x1c6>
|
|
{
|
|
pdev->classId = idx;
|
|
80081e0: 7b7a ldrb r2, [r7, #13]
|
|
80081e2: 687b ldr r3, [r7, #4]
|
|
80081e4: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
80081e8: 7b7a ldrb r2, [r7, #13]
|
|
80081ea: 687b ldr r3, [r7, #4]
|
|
80081ec: 32ae adds r2, #174 @ 0xae
|
|
80081ee: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80081f2: 689b ldr r3, [r3, #8]
|
|
80081f4: 2b00 cmp r3, #0
|
|
80081f6: d010 beq.n 800821a <USBD_StdEPReq+0x1c6>
|
|
{
|
|
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
|
|
80081f8: 7b7a ldrb r2, [r7, #13]
|
|
80081fa: 687b ldr r3, [r7, #4]
|
|
80081fc: 32ae adds r2, #174 @ 0xae
|
|
80081fe: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008202: 689b ldr r3, [r3, #8]
|
|
8008204: 6839 ldr r1, [r7, #0]
|
|
8008206: 6878 ldr r0, [r7, #4]
|
|
8008208: 4798 blx r3
|
|
800820a: 4603 mov r3, r0
|
|
800820c: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
800820e: e004 b.n 800821a <USBD_StdEPReq+0x1c6>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008210: 6839 ldr r1, [r7, #0]
|
|
8008212: 6878 ldr r0, [r7, #4]
|
|
8008214: f000 fc2f bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
8008218: e000 b.n 800821c <USBD_StdEPReq+0x1c8>
|
|
break;
|
|
800821a: bf00 nop
|
|
}
|
|
break;
|
|
800821c: e0ad b.n 800837a <USBD_StdEPReq+0x326>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
switch (pdev->dev_state)
|
|
800821e: 687b ldr r3, [r7, #4]
|
|
8008220: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008224: b2db uxtb r3, r3
|
|
8008226: 2b02 cmp r3, #2
|
|
8008228: d002 beq.n 8008230 <USBD_StdEPReq+0x1dc>
|
|
800822a: 2b03 cmp r3, #3
|
|
800822c: d033 beq.n 8008296 <USBD_StdEPReq+0x242>
|
|
800822e: e099 b.n 8008364 <USBD_StdEPReq+0x310>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
8008230: 7bbb ldrb r3, [r7, #14]
|
|
8008232: 2b00 cmp r3, #0
|
|
8008234: d007 beq.n 8008246 <USBD_StdEPReq+0x1f2>
|
|
8008236: 7bbb ldrb r3, [r7, #14]
|
|
8008238: 2b80 cmp r3, #128 @ 0x80
|
|
800823a: d004 beq.n 8008246 <USBD_StdEPReq+0x1f2>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
800823c: 6839 ldr r1, [r7, #0]
|
|
800823e: 6878 ldr r0, [r7, #4]
|
|
8008240: f000 fc19 bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
8008244: e093 b.n 800836e <USBD_StdEPReq+0x31a>
|
|
}
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
8008246: f997 300e ldrsb.w r3, [r7, #14]
|
|
800824a: 2b00 cmp r3, #0
|
|
800824c: da0b bge.n 8008266 <USBD_StdEPReq+0x212>
|
|
800824e: 7bbb ldrb r3, [r7, #14]
|
|
8008250: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
8008254: 4613 mov r3, r2
|
|
8008256: 009b lsls r3, r3, #2
|
|
8008258: 4413 add r3, r2
|
|
800825a: 009b lsls r3, r3, #2
|
|
800825c: 3310 adds r3, #16
|
|
800825e: 687a ldr r2, [r7, #4]
|
|
8008260: 4413 add r3, r2
|
|
8008262: 3304 adds r3, #4
|
|
8008264: e00b b.n 800827e <USBD_StdEPReq+0x22a>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
8008266: 7bbb ldrb r3, [r7, #14]
|
|
8008268: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
800826c: 4613 mov r3, r2
|
|
800826e: 009b lsls r3, r3, #2
|
|
8008270: 4413 add r3, r2
|
|
8008272: 009b lsls r3, r3, #2
|
|
8008274: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8008278: 687a ldr r2, [r7, #4]
|
|
800827a: 4413 add r3, r2
|
|
800827c: 3304 adds r3, #4
|
|
800827e: 60bb str r3, [r7, #8]
|
|
|
|
pep->status = 0x0000U;
|
|
8008280: 68bb ldr r3, [r7, #8]
|
|
8008282: 2200 movs r2, #0
|
|
8008284: 739a strb r2, [r3, #14]
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
|
|
8008286: 68bb ldr r3, [r7, #8]
|
|
8008288: 330e adds r3, #14
|
|
800828a: 2202 movs r2, #2
|
|
800828c: 4619 mov r1, r3
|
|
800828e: 6878 ldr r0, [r7, #4]
|
|
8008290: f000 fc6e bl 8008b70 <USBD_CtlSendData>
|
|
break;
|
|
8008294: e06b b.n 800836e <USBD_StdEPReq+0x31a>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8008296: f997 300e ldrsb.w r3, [r7, #14]
|
|
800829a: 2b00 cmp r3, #0
|
|
800829c: da11 bge.n 80082c2 <USBD_StdEPReq+0x26e>
|
|
{
|
|
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
|
|
800829e: 7bbb ldrb r3, [r7, #14]
|
|
80082a0: f003 020f and.w r2, r3, #15
|
|
80082a4: 6879 ldr r1, [r7, #4]
|
|
80082a6: 4613 mov r3, r2
|
|
80082a8: 009b lsls r3, r3, #2
|
|
80082aa: 4413 add r3, r2
|
|
80082ac: 009b lsls r3, r3, #2
|
|
80082ae: 440b add r3, r1
|
|
80082b0: 3323 adds r3, #35 @ 0x23
|
|
80082b2: 781b ldrb r3, [r3, #0]
|
|
80082b4: 2b00 cmp r3, #0
|
|
80082b6: d117 bne.n 80082e8 <USBD_StdEPReq+0x294>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80082b8: 6839 ldr r1, [r7, #0]
|
|
80082ba: 6878 ldr r0, [r7, #4]
|
|
80082bc: f000 fbdb bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
80082c0: e055 b.n 800836e <USBD_StdEPReq+0x31a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
|
|
80082c2: 7bbb ldrb r3, [r7, #14]
|
|
80082c4: f003 020f and.w r2, r3, #15
|
|
80082c8: 6879 ldr r1, [r7, #4]
|
|
80082ca: 4613 mov r3, r2
|
|
80082cc: 009b lsls r3, r3, #2
|
|
80082ce: 4413 add r3, r2
|
|
80082d0: 009b lsls r3, r3, #2
|
|
80082d2: 440b add r3, r1
|
|
80082d4: f203 1363 addw r3, r3, #355 @ 0x163
|
|
80082d8: 781b ldrb r3, [r3, #0]
|
|
80082da: 2b00 cmp r3, #0
|
|
80082dc: d104 bne.n 80082e8 <USBD_StdEPReq+0x294>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80082de: 6839 ldr r1, [r7, #0]
|
|
80082e0: 6878 ldr r0, [r7, #4]
|
|
80082e2: f000 fbc8 bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
80082e6: e042 b.n 800836e <USBD_StdEPReq+0x31a>
|
|
}
|
|
}
|
|
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
80082e8: f997 300e ldrsb.w r3, [r7, #14]
|
|
80082ec: 2b00 cmp r3, #0
|
|
80082ee: da0b bge.n 8008308 <USBD_StdEPReq+0x2b4>
|
|
80082f0: 7bbb ldrb r3, [r7, #14]
|
|
80082f2: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
80082f6: 4613 mov r3, r2
|
|
80082f8: 009b lsls r3, r3, #2
|
|
80082fa: 4413 add r3, r2
|
|
80082fc: 009b lsls r3, r3, #2
|
|
80082fe: 3310 adds r3, #16
|
|
8008300: 687a ldr r2, [r7, #4]
|
|
8008302: 4413 add r3, r2
|
|
8008304: 3304 adds r3, #4
|
|
8008306: e00b b.n 8008320 <USBD_StdEPReq+0x2cc>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
8008308: 7bbb ldrb r3, [r7, #14]
|
|
800830a: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
800830e: 4613 mov r3, r2
|
|
8008310: 009b lsls r3, r3, #2
|
|
8008312: 4413 add r3, r2
|
|
8008314: 009b lsls r3, r3, #2
|
|
8008316: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
800831a: 687a ldr r2, [r7, #4]
|
|
800831c: 4413 add r3, r2
|
|
800831e: 3304 adds r3, #4
|
|
8008320: 60bb str r3, [r7, #8]
|
|
|
|
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
|
|
8008322: 7bbb ldrb r3, [r7, #14]
|
|
8008324: 2b00 cmp r3, #0
|
|
8008326: d002 beq.n 800832e <USBD_StdEPReq+0x2da>
|
|
8008328: 7bbb ldrb r3, [r7, #14]
|
|
800832a: 2b80 cmp r3, #128 @ 0x80
|
|
800832c: d103 bne.n 8008336 <USBD_StdEPReq+0x2e2>
|
|
{
|
|
pep->status = 0x0000U;
|
|
800832e: 68bb ldr r3, [r7, #8]
|
|
8008330: 2200 movs r2, #0
|
|
8008332: 739a strb r2, [r3, #14]
|
|
8008334: e00e b.n 8008354 <USBD_StdEPReq+0x300>
|
|
}
|
|
else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U)
|
|
8008336: 7bbb ldrb r3, [r7, #14]
|
|
8008338: 4619 mov r1, r3
|
|
800833a: 6878 ldr r0, [r7, #4]
|
|
800833c: f001 f80c bl 8009358 <USBD_LL_IsStallEP>
|
|
8008340: 4603 mov r3, r0
|
|
8008342: 2b00 cmp r3, #0
|
|
8008344: d003 beq.n 800834e <USBD_StdEPReq+0x2fa>
|
|
{
|
|
pep->status = 0x0001U;
|
|
8008346: 68bb ldr r3, [r7, #8]
|
|
8008348: 2201 movs r2, #1
|
|
800834a: 739a strb r2, [r3, #14]
|
|
800834c: e002 b.n 8008354 <USBD_StdEPReq+0x300>
|
|
}
|
|
else
|
|
{
|
|
pep->status = 0x0000U;
|
|
800834e: 68bb ldr r3, [r7, #8]
|
|
8008350: 2200 movs r2, #0
|
|
8008352: 739a strb r2, [r3, #14]
|
|
}
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
|
|
8008354: 68bb ldr r3, [r7, #8]
|
|
8008356: 330e adds r3, #14
|
|
8008358: 2202 movs r2, #2
|
|
800835a: 4619 mov r1, r3
|
|
800835c: 6878 ldr r0, [r7, #4]
|
|
800835e: f000 fc07 bl 8008b70 <USBD_CtlSendData>
|
|
break;
|
|
8008362: e004 b.n 800836e <USBD_StdEPReq+0x31a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008364: 6839 ldr r1, [r7, #0]
|
|
8008366: 6878 ldr r0, [r7, #4]
|
|
8008368: f000 fb85 bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
800836c: bf00 nop
|
|
}
|
|
break;
|
|
800836e: e004 b.n 800837a <USBD_StdEPReq+0x326>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008370: 6839 ldr r1, [r7, #0]
|
|
8008372: 6878 ldr r0, [r7, #4]
|
|
8008374: f000 fb7f bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
8008378: bf00 nop
|
|
}
|
|
break;
|
|
800837a: e005 b.n 8008388 <USBD_StdEPReq+0x334>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800837c: 6839 ldr r1, [r7, #0]
|
|
800837e: 6878 ldr r0, [r7, #4]
|
|
8008380: f000 fb79 bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
8008384: e000 b.n 8008388 <USBD_StdEPReq+0x334>
|
|
break;
|
|
8008386: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8008388: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800838a: 4618 mov r0, r3
|
|
800838c: 3710 adds r7, #16
|
|
800838e: 46bd mov sp, r7
|
|
8008390: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08008394 <USBD_GetDescriptor>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008394: b580 push {r7, lr}
|
|
8008396: b084 sub sp, #16
|
|
8008398: af00 add r7, sp, #0
|
|
800839a: 6078 str r0, [r7, #4]
|
|
800839c: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
800839e: 2300 movs r3, #0
|
|
80083a0: 813b strh r3, [r7, #8]
|
|
uint8_t *pbuf = NULL;
|
|
80083a2: 2300 movs r3, #0
|
|
80083a4: 60fb str r3, [r7, #12]
|
|
uint8_t err = 0U;
|
|
80083a6: 2300 movs r3, #0
|
|
80083a8: 72fb strb r3, [r7, #11]
|
|
|
|
switch (req->wValue >> 8)
|
|
80083aa: 683b ldr r3, [r7, #0]
|
|
80083ac: 885b ldrh r3, [r3, #2]
|
|
80083ae: 0a1b lsrs r3, r3, #8
|
|
80083b0: b29b uxth r3, r3
|
|
80083b2: 3b01 subs r3, #1
|
|
80083b4: 2b0e cmp r3, #14
|
|
80083b6: f200 8152 bhi.w 800865e <USBD_GetDescriptor+0x2ca>
|
|
80083ba: a201 add r2, pc, #4 @ (adr r2, 80083c0 <USBD_GetDescriptor+0x2c>)
|
|
80083bc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80083c0: 08008431 .word 0x08008431
|
|
80083c4: 08008449 .word 0x08008449
|
|
80083c8: 08008489 .word 0x08008489
|
|
80083cc: 0800865f .word 0x0800865f
|
|
80083d0: 0800865f .word 0x0800865f
|
|
80083d4: 080085ff .word 0x080085ff
|
|
80083d8: 0800862b .word 0x0800862b
|
|
80083dc: 0800865f .word 0x0800865f
|
|
80083e0: 0800865f .word 0x0800865f
|
|
80083e4: 0800865f .word 0x0800865f
|
|
80083e8: 0800865f .word 0x0800865f
|
|
80083ec: 0800865f .word 0x0800865f
|
|
80083f0: 0800865f .word 0x0800865f
|
|
80083f4: 0800865f .word 0x0800865f
|
|
80083f8: 080083fd .word 0x080083fd
|
|
{
|
|
#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U))
|
|
case USB_DESC_TYPE_BOS:
|
|
if (pdev->pDesc->GetBOSDescriptor != NULL)
|
|
80083fc: 687b ldr r3, [r7, #4]
|
|
80083fe: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008402: 69db ldr r3, [r3, #28]
|
|
8008404: 2b00 cmp r3, #0
|
|
8008406: d00b beq.n 8008420 <USBD_GetDescriptor+0x8c>
|
|
{
|
|
pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
|
|
8008408: 687b ldr r3, [r7, #4]
|
|
800840a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800840e: 69db ldr r3, [r3, #28]
|
|
8008410: 687a ldr r2, [r7, #4]
|
|
8008412: 7c12 ldrb r2, [r2, #16]
|
|
8008414: f107 0108 add.w r1, r7, #8
|
|
8008418: 4610 mov r0, r2
|
|
800841a: 4798 blx r3
|
|
800841c: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800841e: e126 b.n 800866e <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
8008420: 6839 ldr r1, [r7, #0]
|
|
8008422: 6878 ldr r0, [r7, #4]
|
|
8008424: f000 fb27 bl 8008a76 <USBD_CtlError>
|
|
err++;
|
|
8008428: 7afb ldrb r3, [r7, #11]
|
|
800842a: 3301 adds r3, #1
|
|
800842c: 72fb strb r3, [r7, #11]
|
|
break;
|
|
800842e: e11e b.n 800866e <USBD_GetDescriptor+0x2da>
|
|
#endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */
|
|
case USB_DESC_TYPE_DEVICE:
|
|
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
|
|
8008430: 687b ldr r3, [r7, #4]
|
|
8008432: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008436: 681b ldr r3, [r3, #0]
|
|
8008438: 687a ldr r2, [r7, #4]
|
|
800843a: 7c12 ldrb r2, [r2, #16]
|
|
800843c: f107 0108 add.w r1, r7, #8
|
|
8008440: 4610 mov r0, r2
|
|
8008442: 4798 blx r3
|
|
8008444: 60f8 str r0, [r7, #12]
|
|
break;
|
|
8008446: e112 b.n 800866e <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8008448: 687b ldr r3, [r7, #4]
|
|
800844a: 7c1b ldrb r3, [r3, #16]
|
|
800844c: 2b00 cmp r3, #0
|
|
800844e: d10d bne.n 800846c <USBD_GetDescriptor+0xd8>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len);
|
|
8008450: 687b ldr r3, [r7, #4]
|
|
8008452: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008456: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8008458: f107 0208 add.w r2, r7, #8
|
|
800845c: 4610 mov r0, r2
|
|
800845e: 4798 blx r3
|
|
8008460: 60f8 str r0, [r7, #12]
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
8008462: 68fb ldr r3, [r7, #12]
|
|
8008464: 3301 adds r3, #1
|
|
8008466: 2202 movs r2, #2
|
|
8008468: 701a strb r2, [r3, #0]
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
}
|
|
break;
|
|
800846a: e100 b.n 800866e <USBD_GetDescriptor+0x2da>
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
|
|
800846c: 687b ldr r3, [r7, #4]
|
|
800846e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008472: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8008474: f107 0208 add.w r2, r7, #8
|
|
8008478: 4610 mov r0, r2
|
|
800847a: 4798 blx r3
|
|
800847c: 60f8 str r0, [r7, #12]
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
800847e: 68fb ldr r3, [r7, #12]
|
|
8008480: 3301 adds r3, #1
|
|
8008482: 2202 movs r2, #2
|
|
8008484: 701a strb r2, [r3, #0]
|
|
break;
|
|
8008486: e0f2 b.n 800866e <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_STRING:
|
|
switch ((uint8_t)(req->wValue))
|
|
8008488: 683b ldr r3, [r7, #0]
|
|
800848a: 885b ldrh r3, [r3, #2]
|
|
800848c: b2db uxtb r3, r3
|
|
800848e: 2b05 cmp r3, #5
|
|
8008490: f200 80ac bhi.w 80085ec <USBD_GetDescriptor+0x258>
|
|
8008494: a201 add r2, pc, #4 @ (adr r2, 800849c <USBD_GetDescriptor+0x108>)
|
|
8008496: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800849a: bf00 nop
|
|
800849c: 080084b5 .word 0x080084b5
|
|
80084a0: 080084e9 .word 0x080084e9
|
|
80084a4: 0800851d .word 0x0800851d
|
|
80084a8: 08008551 .word 0x08008551
|
|
80084ac: 08008585 .word 0x08008585
|
|
80084b0: 080085b9 .word 0x080085b9
|
|
{
|
|
case USBD_IDX_LANGID_STR:
|
|
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
|
|
80084b4: 687b ldr r3, [r7, #4]
|
|
80084b6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80084ba: 685b ldr r3, [r3, #4]
|
|
80084bc: 2b00 cmp r3, #0
|
|
80084be: d00b beq.n 80084d8 <USBD_GetDescriptor+0x144>
|
|
{
|
|
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
|
|
80084c0: 687b ldr r3, [r7, #4]
|
|
80084c2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80084c6: 685b ldr r3, [r3, #4]
|
|
80084c8: 687a ldr r2, [r7, #4]
|
|
80084ca: 7c12 ldrb r2, [r2, #16]
|
|
80084cc: f107 0108 add.w r1, r7, #8
|
|
80084d0: 4610 mov r0, r2
|
|
80084d2: 4798 blx r3
|
|
80084d4: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80084d6: e091 b.n 80085fc <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
80084d8: 6839 ldr r1, [r7, #0]
|
|
80084da: 6878 ldr r0, [r7, #4]
|
|
80084dc: f000 facb bl 8008a76 <USBD_CtlError>
|
|
err++;
|
|
80084e0: 7afb ldrb r3, [r7, #11]
|
|
80084e2: 3301 adds r3, #1
|
|
80084e4: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80084e6: e089 b.n 80085fc <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_MFC_STR:
|
|
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
|
|
80084e8: 687b ldr r3, [r7, #4]
|
|
80084ea: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80084ee: 689b ldr r3, [r3, #8]
|
|
80084f0: 2b00 cmp r3, #0
|
|
80084f2: d00b beq.n 800850c <USBD_GetDescriptor+0x178>
|
|
{
|
|
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
|
|
80084f4: 687b ldr r3, [r7, #4]
|
|
80084f6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80084fa: 689b ldr r3, [r3, #8]
|
|
80084fc: 687a ldr r2, [r7, #4]
|
|
80084fe: 7c12 ldrb r2, [r2, #16]
|
|
8008500: f107 0108 add.w r1, r7, #8
|
|
8008504: 4610 mov r0, r2
|
|
8008506: 4798 blx r3
|
|
8008508: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800850a: e077 b.n 80085fc <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
800850c: 6839 ldr r1, [r7, #0]
|
|
800850e: 6878 ldr r0, [r7, #4]
|
|
8008510: f000 fab1 bl 8008a76 <USBD_CtlError>
|
|
err++;
|
|
8008514: 7afb ldrb r3, [r7, #11]
|
|
8008516: 3301 adds r3, #1
|
|
8008518: 72fb strb r3, [r7, #11]
|
|
break;
|
|
800851a: e06f b.n 80085fc <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_PRODUCT_STR:
|
|
if (pdev->pDesc->GetProductStrDescriptor != NULL)
|
|
800851c: 687b ldr r3, [r7, #4]
|
|
800851e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008522: 68db ldr r3, [r3, #12]
|
|
8008524: 2b00 cmp r3, #0
|
|
8008526: d00b beq.n 8008540 <USBD_GetDescriptor+0x1ac>
|
|
{
|
|
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
|
|
8008528: 687b ldr r3, [r7, #4]
|
|
800852a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800852e: 68db ldr r3, [r3, #12]
|
|
8008530: 687a ldr r2, [r7, #4]
|
|
8008532: 7c12 ldrb r2, [r2, #16]
|
|
8008534: f107 0108 add.w r1, r7, #8
|
|
8008538: 4610 mov r0, r2
|
|
800853a: 4798 blx r3
|
|
800853c: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800853e: e05d b.n 80085fc <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8008540: 6839 ldr r1, [r7, #0]
|
|
8008542: 6878 ldr r0, [r7, #4]
|
|
8008544: f000 fa97 bl 8008a76 <USBD_CtlError>
|
|
err++;
|
|
8008548: 7afb ldrb r3, [r7, #11]
|
|
800854a: 3301 adds r3, #1
|
|
800854c: 72fb strb r3, [r7, #11]
|
|
break;
|
|
800854e: e055 b.n 80085fc <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_SERIAL_STR:
|
|
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
|
|
8008550: 687b ldr r3, [r7, #4]
|
|
8008552: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008556: 691b ldr r3, [r3, #16]
|
|
8008558: 2b00 cmp r3, #0
|
|
800855a: d00b beq.n 8008574 <USBD_GetDescriptor+0x1e0>
|
|
{
|
|
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
|
|
800855c: 687b ldr r3, [r7, #4]
|
|
800855e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008562: 691b ldr r3, [r3, #16]
|
|
8008564: 687a ldr r2, [r7, #4]
|
|
8008566: 7c12 ldrb r2, [r2, #16]
|
|
8008568: f107 0108 add.w r1, r7, #8
|
|
800856c: 4610 mov r0, r2
|
|
800856e: 4798 blx r3
|
|
8008570: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8008572: e043 b.n 80085fc <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8008574: 6839 ldr r1, [r7, #0]
|
|
8008576: 6878 ldr r0, [r7, #4]
|
|
8008578: f000 fa7d bl 8008a76 <USBD_CtlError>
|
|
err++;
|
|
800857c: 7afb ldrb r3, [r7, #11]
|
|
800857e: 3301 adds r3, #1
|
|
8008580: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8008582: e03b b.n 80085fc <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_CONFIG_STR:
|
|
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
|
|
8008584: 687b ldr r3, [r7, #4]
|
|
8008586: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800858a: 695b ldr r3, [r3, #20]
|
|
800858c: 2b00 cmp r3, #0
|
|
800858e: d00b beq.n 80085a8 <USBD_GetDescriptor+0x214>
|
|
{
|
|
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
|
|
8008590: 687b ldr r3, [r7, #4]
|
|
8008592: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8008596: 695b ldr r3, [r3, #20]
|
|
8008598: 687a ldr r2, [r7, #4]
|
|
800859a: 7c12 ldrb r2, [r2, #16]
|
|
800859c: f107 0108 add.w r1, r7, #8
|
|
80085a0: 4610 mov r0, r2
|
|
80085a2: 4798 blx r3
|
|
80085a4: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80085a6: e029 b.n 80085fc <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
80085a8: 6839 ldr r1, [r7, #0]
|
|
80085aa: 6878 ldr r0, [r7, #4]
|
|
80085ac: f000 fa63 bl 8008a76 <USBD_CtlError>
|
|
err++;
|
|
80085b0: 7afb ldrb r3, [r7, #11]
|
|
80085b2: 3301 adds r3, #1
|
|
80085b4: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80085b6: e021 b.n 80085fc <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_INTERFACE_STR:
|
|
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
|
|
80085b8: 687b ldr r3, [r7, #4]
|
|
80085ba: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80085be: 699b ldr r3, [r3, #24]
|
|
80085c0: 2b00 cmp r3, #0
|
|
80085c2: d00b beq.n 80085dc <USBD_GetDescriptor+0x248>
|
|
{
|
|
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
|
|
80085c4: 687b ldr r3, [r7, #4]
|
|
80085c6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80085ca: 699b ldr r3, [r3, #24]
|
|
80085cc: 687a ldr r2, [r7, #4]
|
|
80085ce: 7c12 ldrb r2, [r2, #16]
|
|
80085d0: f107 0108 add.w r1, r7, #8
|
|
80085d4: 4610 mov r0, r2
|
|
80085d6: 4798 blx r3
|
|
80085d8: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80085da: e00f b.n 80085fc <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
80085dc: 6839 ldr r1, [r7, #0]
|
|
80085de: 6878 ldr r0, [r7, #4]
|
|
80085e0: f000 fa49 bl 8008a76 <USBD_CtlError>
|
|
err++;
|
|
80085e4: 7afb ldrb r3, [r7, #11]
|
|
80085e6: 3301 adds r3, #1
|
|
80085e8: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80085ea: e007 b.n 80085fc <USBD_GetDescriptor+0x268>
|
|
err++;
|
|
}
|
|
#endif /* USBD_SUPPORT_USER_STRING_DESC */
|
|
|
|
#if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U))
|
|
USBD_CtlError(pdev, req);
|
|
80085ec: 6839 ldr r1, [r7, #0]
|
|
80085ee: 6878 ldr r0, [r7, #4]
|
|
80085f0: f000 fa41 bl 8008a76 <USBD_CtlError>
|
|
err++;
|
|
80085f4: 7afb ldrb r3, [r7, #11]
|
|
80085f6: 3301 adds r3, #1
|
|
80085f8: 72fb strb r3, [r7, #11]
|
|
#endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */
|
|
break;
|
|
80085fa: bf00 nop
|
|
}
|
|
break;
|
|
80085fc: e037 b.n 800866e <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_DEVICE_QUALIFIER:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
80085fe: 687b ldr r3, [r7, #4]
|
|
8008600: 7c1b ldrb r3, [r3, #16]
|
|
8008602: 2b00 cmp r3, #0
|
|
8008604: d109 bne.n 800861a <USBD_GetDescriptor+0x286>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len);
|
|
8008606: 687b ldr r3, [r7, #4]
|
|
8008608: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
800860c: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800860e: f107 0208 add.w r2, r7, #8
|
|
8008612: 4610 mov r0, r2
|
|
8008614: 4798 blx r3
|
|
8008616: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8008618: e029 b.n 800866e <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
800861a: 6839 ldr r1, [r7, #0]
|
|
800861c: 6878 ldr r0, [r7, #4]
|
|
800861e: f000 fa2a bl 8008a76 <USBD_CtlError>
|
|
err++;
|
|
8008622: 7afb ldrb r3, [r7, #11]
|
|
8008624: 3301 adds r3, #1
|
|
8008626: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8008628: e021 b.n 800866e <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
800862a: 687b ldr r3, [r7, #4]
|
|
800862c: 7c1b ldrb r3, [r3, #16]
|
|
800862e: 2b00 cmp r3, #0
|
|
8008630: d10d bne.n 800864e <USBD_GetDescriptor+0x2ba>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len);
|
|
8008632: 687b ldr r3, [r7, #4]
|
|
8008634: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008638: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800863a: f107 0208 add.w r2, r7, #8
|
|
800863e: 4610 mov r0, r2
|
|
8008640: 4798 blx r3
|
|
8008642: 60f8 str r0, [r7, #12]
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
|
|
8008644: 68fb ldr r3, [r7, #12]
|
|
8008646: 3301 adds r3, #1
|
|
8008648: 2207 movs r2, #7
|
|
800864a: 701a strb r2, [r3, #0]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800864c: e00f b.n 800866e <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
800864e: 6839 ldr r1, [r7, #0]
|
|
8008650: 6878 ldr r0, [r7, #4]
|
|
8008652: f000 fa10 bl 8008a76 <USBD_CtlError>
|
|
err++;
|
|
8008656: 7afb ldrb r3, [r7, #11]
|
|
8008658: 3301 adds r3, #1
|
|
800865a: 72fb strb r3, [r7, #11]
|
|
break;
|
|
800865c: e007 b.n 800866e <USBD_GetDescriptor+0x2da>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800865e: 6839 ldr r1, [r7, #0]
|
|
8008660: 6878 ldr r0, [r7, #4]
|
|
8008662: f000 fa08 bl 8008a76 <USBD_CtlError>
|
|
err++;
|
|
8008666: 7afb ldrb r3, [r7, #11]
|
|
8008668: 3301 adds r3, #1
|
|
800866a: 72fb strb r3, [r7, #11]
|
|
break;
|
|
800866c: bf00 nop
|
|
}
|
|
|
|
if (err != 0U)
|
|
800866e: 7afb ldrb r3, [r7, #11]
|
|
8008670: 2b00 cmp r3, #0
|
|
8008672: d11e bne.n 80086b2 <USBD_GetDescriptor+0x31e>
|
|
{
|
|
return;
|
|
}
|
|
|
|
if (req->wLength != 0U)
|
|
8008674: 683b ldr r3, [r7, #0]
|
|
8008676: 88db ldrh r3, [r3, #6]
|
|
8008678: 2b00 cmp r3, #0
|
|
800867a: d016 beq.n 80086aa <USBD_GetDescriptor+0x316>
|
|
{
|
|
if (len != 0U)
|
|
800867c: 893b ldrh r3, [r7, #8]
|
|
800867e: 2b00 cmp r3, #0
|
|
8008680: d00e beq.n 80086a0 <USBD_GetDescriptor+0x30c>
|
|
{
|
|
len = MIN(len, req->wLength);
|
|
8008682: 683b ldr r3, [r7, #0]
|
|
8008684: 88da ldrh r2, [r3, #6]
|
|
8008686: 893b ldrh r3, [r7, #8]
|
|
8008688: 4293 cmp r3, r2
|
|
800868a: bf28 it cs
|
|
800868c: 4613 movcs r3, r2
|
|
800868e: b29b uxth r3, r3
|
|
8008690: 813b strh r3, [r7, #8]
|
|
(void)USBD_CtlSendData(pdev, pbuf, len);
|
|
8008692: 893b ldrh r3, [r7, #8]
|
|
8008694: 461a mov r2, r3
|
|
8008696: 68f9 ldr r1, [r7, #12]
|
|
8008698: 6878 ldr r0, [r7, #4]
|
|
800869a: f000 fa69 bl 8008b70 <USBD_CtlSendData>
|
|
800869e: e009 b.n 80086b4 <USBD_GetDescriptor+0x320>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80086a0: 6839 ldr r1, [r7, #0]
|
|
80086a2: 6878 ldr r0, [r7, #4]
|
|
80086a4: f000 f9e7 bl 8008a76 <USBD_CtlError>
|
|
80086a8: e004 b.n 80086b4 <USBD_GetDescriptor+0x320>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80086aa: 6878 ldr r0, [r7, #4]
|
|
80086ac: f000 faa0 bl 8008bf0 <USBD_CtlSendStatus>
|
|
80086b0: e000 b.n 80086b4 <USBD_GetDescriptor+0x320>
|
|
return;
|
|
80086b2: bf00 nop
|
|
}
|
|
}
|
|
80086b4: 3710 adds r7, #16
|
|
80086b6: 46bd mov sp, r7
|
|
80086b8: bd80 pop {r7, pc}
|
|
80086ba: bf00 nop
|
|
|
|
080086bc <USBD_SetAddress>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
80086bc: b580 push {r7, lr}
|
|
80086be: b084 sub sp, #16
|
|
80086c0: af00 add r7, sp, #0
|
|
80086c2: 6078 str r0, [r7, #4]
|
|
80086c4: 6039 str r1, [r7, #0]
|
|
uint8_t dev_addr;
|
|
|
|
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
|
|
80086c6: 683b ldr r3, [r7, #0]
|
|
80086c8: 889b ldrh r3, [r3, #4]
|
|
80086ca: 2b00 cmp r3, #0
|
|
80086cc: d131 bne.n 8008732 <USBD_SetAddress+0x76>
|
|
80086ce: 683b ldr r3, [r7, #0]
|
|
80086d0: 88db ldrh r3, [r3, #6]
|
|
80086d2: 2b00 cmp r3, #0
|
|
80086d4: d12d bne.n 8008732 <USBD_SetAddress+0x76>
|
|
80086d6: 683b ldr r3, [r7, #0]
|
|
80086d8: 885b ldrh r3, [r3, #2]
|
|
80086da: 2b7f cmp r3, #127 @ 0x7f
|
|
80086dc: d829 bhi.n 8008732 <USBD_SetAddress+0x76>
|
|
{
|
|
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
|
|
80086de: 683b ldr r3, [r7, #0]
|
|
80086e0: 885b ldrh r3, [r3, #2]
|
|
80086e2: b2db uxtb r3, r3
|
|
80086e4: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
80086e8: 73fb strb r3, [r7, #15]
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80086ea: 687b ldr r3, [r7, #4]
|
|
80086ec: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80086f0: b2db uxtb r3, r3
|
|
80086f2: 2b03 cmp r3, #3
|
|
80086f4: d104 bne.n 8008700 <USBD_SetAddress+0x44>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80086f6: 6839 ldr r1, [r7, #0]
|
|
80086f8: 6878 ldr r0, [r7, #4]
|
|
80086fa: f000 f9bc bl 8008a76 <USBD_CtlError>
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80086fe: e01d b.n 800873c <USBD_SetAddress+0x80>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_address = dev_addr;
|
|
8008700: 687b ldr r3, [r7, #4]
|
|
8008702: 7bfa ldrb r2, [r7, #15]
|
|
8008704: f883 229e strb.w r2, [r3, #670] @ 0x29e
|
|
(void)USBD_LL_SetUSBAddress(pdev, dev_addr);
|
|
8008708: 7bfb ldrb r3, [r7, #15]
|
|
800870a: 4619 mov r1, r3
|
|
800870c: 6878 ldr r0, [r7, #4]
|
|
800870e: f000 fe4f bl 80093b0 <USBD_LL_SetUSBAddress>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8008712: 6878 ldr r0, [r7, #4]
|
|
8008714: f000 fa6c bl 8008bf0 <USBD_CtlSendStatus>
|
|
|
|
if (dev_addr != 0U)
|
|
8008718: 7bfb ldrb r3, [r7, #15]
|
|
800871a: 2b00 cmp r3, #0
|
|
800871c: d004 beq.n 8008728 <USBD_SetAddress+0x6c>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
800871e: 687b ldr r3, [r7, #4]
|
|
8008720: 2202 movs r2, #2
|
|
8008722: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008726: e009 b.n 800873c <USBD_SetAddress+0x80>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8008728: 687b ldr r3, [r7, #4]
|
|
800872a: 2201 movs r2, #1
|
|
800872c: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008730: e004 b.n 800873c <USBD_SetAddress+0x80>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008732: 6839 ldr r1, [r7, #0]
|
|
8008734: 6878 ldr r0, [r7, #4]
|
|
8008736: f000 f99e bl 8008a76 <USBD_CtlError>
|
|
}
|
|
}
|
|
800873a: bf00 nop
|
|
800873c: bf00 nop
|
|
800873e: 3710 adds r7, #16
|
|
8008740: 46bd mov sp, r7
|
|
8008742: bd80 pop {r7, pc}
|
|
|
|
08008744 <USBD_SetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008744: b580 push {r7, lr}
|
|
8008746: b084 sub sp, #16
|
|
8008748: af00 add r7, sp, #0
|
|
800874a: 6078 str r0, [r7, #4]
|
|
800874c: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
800874e: 2300 movs r3, #0
|
|
8008750: 73fb strb r3, [r7, #15]
|
|
static uint8_t cfgidx;
|
|
|
|
cfgidx = (uint8_t)(req->wValue);
|
|
8008752: 683b ldr r3, [r7, #0]
|
|
8008754: 885b ldrh r3, [r3, #2]
|
|
8008756: b2da uxtb r2, r3
|
|
8008758: 4b4e ldr r3, [pc, #312] @ (8008894 <USBD_SetConfig+0x150>)
|
|
800875a: 701a strb r2, [r3, #0]
|
|
|
|
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
|
|
800875c: 4b4d ldr r3, [pc, #308] @ (8008894 <USBD_SetConfig+0x150>)
|
|
800875e: 781b ldrb r3, [r3, #0]
|
|
8008760: 2b01 cmp r3, #1
|
|
8008762: d905 bls.n 8008770 <USBD_SetConfig+0x2c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008764: 6839 ldr r1, [r7, #0]
|
|
8008766: 6878 ldr r0, [r7, #4]
|
|
8008768: f000 f985 bl 8008a76 <USBD_CtlError>
|
|
return USBD_FAIL;
|
|
800876c: 2303 movs r3, #3
|
|
800876e: e08c b.n 800888a <USBD_SetConfig+0x146>
|
|
}
|
|
|
|
switch (pdev->dev_state)
|
|
8008770: 687b ldr r3, [r7, #4]
|
|
8008772: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008776: b2db uxtb r3, r3
|
|
8008778: 2b02 cmp r3, #2
|
|
800877a: d002 beq.n 8008782 <USBD_SetConfig+0x3e>
|
|
800877c: 2b03 cmp r3, #3
|
|
800877e: d029 beq.n 80087d4 <USBD_SetConfig+0x90>
|
|
8008780: e075 b.n 800886e <USBD_SetConfig+0x12a>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if (cfgidx != 0U)
|
|
8008782: 4b44 ldr r3, [pc, #272] @ (8008894 <USBD_SetConfig+0x150>)
|
|
8008784: 781b ldrb r3, [r3, #0]
|
|
8008786: 2b00 cmp r3, #0
|
|
8008788: d020 beq.n 80087cc <USBD_SetConfig+0x88>
|
|
{
|
|
pdev->dev_config = cfgidx;
|
|
800878a: 4b42 ldr r3, [pc, #264] @ (8008894 <USBD_SetConfig+0x150>)
|
|
800878c: 781b ldrb r3, [r3, #0]
|
|
800878e: 461a mov r2, r3
|
|
8008790: 687b ldr r3, [r7, #4]
|
|
8008792: 605a str r2, [r3, #4]
|
|
|
|
ret = USBD_SetClassConfig(pdev, cfgidx);
|
|
8008794: 4b3f ldr r3, [pc, #252] @ (8008894 <USBD_SetConfig+0x150>)
|
|
8008796: 781b ldrb r3, [r3, #0]
|
|
8008798: 4619 mov r1, r3
|
|
800879a: 6878 ldr r0, [r7, #4]
|
|
800879c: f7fe ffa3 bl 80076e6 <USBD_SetClassConfig>
|
|
80087a0: 4603 mov r3, r0
|
|
80087a2: 73fb strb r3, [r7, #15]
|
|
|
|
if (ret != USBD_OK)
|
|
80087a4: 7bfb ldrb r3, [r7, #15]
|
|
80087a6: 2b00 cmp r3, #0
|
|
80087a8: d008 beq.n 80087bc <USBD_SetConfig+0x78>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80087aa: 6839 ldr r1, [r7, #0]
|
|
80087ac: 6878 ldr r0, [r7, #4]
|
|
80087ae: f000 f962 bl 8008a76 <USBD_CtlError>
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
80087b2: 687b ldr r3, [r7, #4]
|
|
80087b4: 2202 movs r2, #2
|
|
80087b6: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
80087ba: e065 b.n 8008888 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80087bc: 6878 ldr r0, [r7, #4]
|
|
80087be: f000 fa17 bl 8008bf0 <USBD_CtlSendStatus>
|
|
pdev->dev_state = USBD_STATE_CONFIGURED;
|
|
80087c2: 687b ldr r3, [r7, #4]
|
|
80087c4: 2203 movs r2, #3
|
|
80087c6: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
break;
|
|
80087ca: e05d b.n 8008888 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80087cc: 6878 ldr r0, [r7, #4]
|
|
80087ce: f000 fa0f bl 8008bf0 <USBD_CtlSendStatus>
|
|
break;
|
|
80087d2: e059 b.n 8008888 <USBD_SetConfig+0x144>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (cfgidx == 0U)
|
|
80087d4: 4b2f ldr r3, [pc, #188] @ (8008894 <USBD_SetConfig+0x150>)
|
|
80087d6: 781b ldrb r3, [r3, #0]
|
|
80087d8: 2b00 cmp r3, #0
|
|
80087da: d112 bne.n 8008802 <USBD_SetConfig+0xbe>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
80087dc: 687b ldr r3, [r7, #4]
|
|
80087de: 2202 movs r2, #2
|
|
80087e0: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->dev_config = cfgidx;
|
|
80087e4: 4b2b ldr r3, [pc, #172] @ (8008894 <USBD_SetConfig+0x150>)
|
|
80087e6: 781b ldrb r3, [r3, #0]
|
|
80087e8: 461a mov r2, r3
|
|
80087ea: 687b ldr r3, [r7, #4]
|
|
80087ec: 605a str r2, [r3, #4]
|
|
(void)USBD_ClrClassConfig(pdev, cfgidx);
|
|
80087ee: 4b29 ldr r3, [pc, #164] @ (8008894 <USBD_SetConfig+0x150>)
|
|
80087f0: 781b ldrb r3, [r3, #0]
|
|
80087f2: 4619 mov r1, r3
|
|
80087f4: 6878 ldr r0, [r7, #4]
|
|
80087f6: f7fe ff92 bl 800771e <USBD_ClrClassConfig>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80087fa: 6878 ldr r0, [r7, #4]
|
|
80087fc: f000 f9f8 bl 8008bf0 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
8008800: e042 b.n 8008888 <USBD_SetConfig+0x144>
|
|
else if (cfgidx != pdev->dev_config)
|
|
8008802: 4b24 ldr r3, [pc, #144] @ (8008894 <USBD_SetConfig+0x150>)
|
|
8008804: 781b ldrb r3, [r3, #0]
|
|
8008806: 461a mov r2, r3
|
|
8008808: 687b ldr r3, [r7, #4]
|
|
800880a: 685b ldr r3, [r3, #4]
|
|
800880c: 429a cmp r2, r3
|
|
800880e: d02a beq.n 8008866 <USBD_SetConfig+0x122>
|
|
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
8008810: 687b ldr r3, [r7, #4]
|
|
8008812: 685b ldr r3, [r3, #4]
|
|
8008814: b2db uxtb r3, r3
|
|
8008816: 4619 mov r1, r3
|
|
8008818: 6878 ldr r0, [r7, #4]
|
|
800881a: f7fe ff80 bl 800771e <USBD_ClrClassConfig>
|
|
pdev->dev_config = cfgidx;
|
|
800881e: 4b1d ldr r3, [pc, #116] @ (8008894 <USBD_SetConfig+0x150>)
|
|
8008820: 781b ldrb r3, [r3, #0]
|
|
8008822: 461a mov r2, r3
|
|
8008824: 687b ldr r3, [r7, #4]
|
|
8008826: 605a str r2, [r3, #4]
|
|
ret = USBD_SetClassConfig(pdev, cfgidx);
|
|
8008828: 4b1a ldr r3, [pc, #104] @ (8008894 <USBD_SetConfig+0x150>)
|
|
800882a: 781b ldrb r3, [r3, #0]
|
|
800882c: 4619 mov r1, r3
|
|
800882e: 6878 ldr r0, [r7, #4]
|
|
8008830: f7fe ff59 bl 80076e6 <USBD_SetClassConfig>
|
|
8008834: 4603 mov r3, r0
|
|
8008836: 73fb strb r3, [r7, #15]
|
|
if (ret != USBD_OK)
|
|
8008838: 7bfb ldrb r3, [r7, #15]
|
|
800883a: 2b00 cmp r3, #0
|
|
800883c: d00f beq.n 800885e <USBD_SetConfig+0x11a>
|
|
USBD_CtlError(pdev, req);
|
|
800883e: 6839 ldr r1, [r7, #0]
|
|
8008840: 6878 ldr r0, [r7, #4]
|
|
8008842: f000 f918 bl 8008a76 <USBD_CtlError>
|
|
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
8008846: 687b ldr r3, [r7, #4]
|
|
8008848: 685b ldr r3, [r3, #4]
|
|
800884a: b2db uxtb r3, r3
|
|
800884c: 4619 mov r1, r3
|
|
800884e: 6878 ldr r0, [r7, #4]
|
|
8008850: f7fe ff65 bl 800771e <USBD_ClrClassConfig>
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8008854: 687b ldr r3, [r7, #4]
|
|
8008856: 2202 movs r2, #2
|
|
8008858: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
break;
|
|
800885c: e014 b.n 8008888 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800885e: 6878 ldr r0, [r7, #4]
|
|
8008860: f000 f9c6 bl 8008bf0 <USBD_CtlSendStatus>
|
|
break;
|
|
8008864: e010 b.n 8008888 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8008866: 6878 ldr r0, [r7, #4]
|
|
8008868: f000 f9c2 bl 8008bf0 <USBD_CtlSendStatus>
|
|
break;
|
|
800886c: e00c b.n 8008888 <USBD_SetConfig+0x144>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800886e: 6839 ldr r1, [r7, #0]
|
|
8008870: 6878 ldr r0, [r7, #4]
|
|
8008872: f000 f900 bl 8008a76 <USBD_CtlError>
|
|
(void)USBD_ClrClassConfig(pdev, cfgidx);
|
|
8008876: 4b07 ldr r3, [pc, #28] @ (8008894 <USBD_SetConfig+0x150>)
|
|
8008878: 781b ldrb r3, [r3, #0]
|
|
800887a: 4619 mov r1, r3
|
|
800887c: 6878 ldr r0, [r7, #4]
|
|
800887e: f7fe ff4e bl 800771e <USBD_ClrClassConfig>
|
|
ret = USBD_FAIL;
|
|
8008882: 2303 movs r3, #3
|
|
8008884: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8008886: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8008888: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800888a: 4618 mov r0, r3
|
|
800888c: 3710 adds r7, #16
|
|
800888e: 46bd mov sp, r7
|
|
8008890: bd80 pop {r7, pc}
|
|
8008892: bf00 nop
|
|
8008894: 20000504 .word 0x20000504
|
|
|
|
08008898 <USBD_GetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008898: b580 push {r7, lr}
|
|
800889a: b082 sub sp, #8
|
|
800889c: af00 add r7, sp, #0
|
|
800889e: 6078 str r0, [r7, #4]
|
|
80088a0: 6039 str r1, [r7, #0]
|
|
if (req->wLength != 1U)
|
|
80088a2: 683b ldr r3, [r7, #0]
|
|
80088a4: 88db ldrh r3, [r3, #6]
|
|
80088a6: 2b01 cmp r3, #1
|
|
80088a8: d004 beq.n 80088b4 <USBD_GetConfig+0x1c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80088aa: 6839 ldr r1, [r7, #0]
|
|
80088ac: 6878 ldr r0, [r7, #4]
|
|
80088ae: f000 f8e2 bl 8008a76 <USBD_CtlError>
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
80088b2: e023 b.n 80088fc <USBD_GetConfig+0x64>
|
|
switch (pdev->dev_state)
|
|
80088b4: 687b ldr r3, [r7, #4]
|
|
80088b6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80088ba: b2db uxtb r3, r3
|
|
80088bc: 2b02 cmp r3, #2
|
|
80088be: dc02 bgt.n 80088c6 <USBD_GetConfig+0x2e>
|
|
80088c0: 2b00 cmp r3, #0
|
|
80088c2: dc03 bgt.n 80088cc <USBD_GetConfig+0x34>
|
|
80088c4: e015 b.n 80088f2 <USBD_GetConfig+0x5a>
|
|
80088c6: 2b03 cmp r3, #3
|
|
80088c8: d00b beq.n 80088e2 <USBD_GetConfig+0x4a>
|
|
80088ca: e012 b.n 80088f2 <USBD_GetConfig+0x5a>
|
|
pdev->dev_default_config = 0U;
|
|
80088cc: 687b ldr r3, [r7, #4]
|
|
80088ce: 2200 movs r2, #0
|
|
80088d0: 609a str r2, [r3, #8]
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
|
|
80088d2: 687b ldr r3, [r7, #4]
|
|
80088d4: 3308 adds r3, #8
|
|
80088d6: 2201 movs r2, #1
|
|
80088d8: 4619 mov r1, r3
|
|
80088da: 6878 ldr r0, [r7, #4]
|
|
80088dc: f000 f948 bl 8008b70 <USBD_CtlSendData>
|
|
break;
|
|
80088e0: e00c b.n 80088fc <USBD_GetConfig+0x64>
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U);
|
|
80088e2: 687b ldr r3, [r7, #4]
|
|
80088e4: 3304 adds r3, #4
|
|
80088e6: 2201 movs r2, #1
|
|
80088e8: 4619 mov r1, r3
|
|
80088ea: 6878 ldr r0, [r7, #4]
|
|
80088ec: f000 f940 bl 8008b70 <USBD_CtlSendData>
|
|
break;
|
|
80088f0: e004 b.n 80088fc <USBD_GetConfig+0x64>
|
|
USBD_CtlError(pdev, req);
|
|
80088f2: 6839 ldr r1, [r7, #0]
|
|
80088f4: 6878 ldr r0, [r7, #4]
|
|
80088f6: f000 f8be bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
80088fa: bf00 nop
|
|
}
|
|
80088fc: bf00 nop
|
|
80088fe: 3708 adds r7, #8
|
|
8008900: 46bd mov sp, r7
|
|
8008902: bd80 pop {r7, pc}
|
|
|
|
08008904 <USBD_GetStatus>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008904: b580 push {r7, lr}
|
|
8008906: b082 sub sp, #8
|
|
8008908: af00 add r7, sp, #0
|
|
800890a: 6078 str r0, [r7, #4]
|
|
800890c: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
800890e: 687b ldr r3, [r7, #4]
|
|
8008910: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008914: b2db uxtb r3, r3
|
|
8008916: 3b01 subs r3, #1
|
|
8008918: 2b02 cmp r3, #2
|
|
800891a: d81e bhi.n 800895a <USBD_GetStatus+0x56>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wLength != 0x2U)
|
|
800891c: 683b ldr r3, [r7, #0]
|
|
800891e: 88db ldrh r3, [r3, #6]
|
|
8008920: 2b02 cmp r3, #2
|
|
8008922: d004 beq.n 800892e <USBD_GetStatus+0x2a>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008924: 6839 ldr r1, [r7, #0]
|
|
8008926: 6878 ldr r0, [r7, #4]
|
|
8008928: f000 f8a5 bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
800892c: e01a b.n 8008964 <USBD_GetStatus+0x60>
|
|
}
|
|
|
|
#if (USBD_SELF_POWERED == 1U)
|
|
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
|
|
800892e: 687b ldr r3, [r7, #4]
|
|
8008930: 2201 movs r2, #1
|
|
8008932: 60da str r2, [r3, #12]
|
|
#else
|
|
pdev->dev_config_status = 0U;
|
|
#endif /* USBD_SELF_POWERED */
|
|
|
|
if (pdev->dev_remote_wakeup != 0U)
|
|
8008934: 687b ldr r3, [r7, #4]
|
|
8008936: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
|
|
800893a: 2b00 cmp r3, #0
|
|
800893c: d005 beq.n 800894a <USBD_GetStatus+0x46>
|
|
{
|
|
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
|
|
800893e: 687b ldr r3, [r7, #4]
|
|
8008940: 68db ldr r3, [r3, #12]
|
|
8008942: f043 0202 orr.w r2, r3, #2
|
|
8008946: 687b ldr r3, [r7, #4]
|
|
8008948: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U);
|
|
800894a: 687b ldr r3, [r7, #4]
|
|
800894c: 330c adds r3, #12
|
|
800894e: 2202 movs r2, #2
|
|
8008950: 4619 mov r1, r3
|
|
8008952: 6878 ldr r0, [r7, #4]
|
|
8008954: f000 f90c bl 8008b70 <USBD_CtlSendData>
|
|
break;
|
|
8008958: e004 b.n 8008964 <USBD_GetStatus+0x60>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800895a: 6839 ldr r1, [r7, #0]
|
|
800895c: 6878 ldr r0, [r7, #4]
|
|
800895e: f000 f88a bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
8008962: bf00 nop
|
|
}
|
|
}
|
|
8008964: bf00 nop
|
|
8008966: 3708 adds r7, #8
|
|
8008968: 46bd mov sp, r7
|
|
800896a: bd80 pop {r7, pc}
|
|
|
|
0800896c <USBD_SetFeature>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
800896c: b580 push {r7, lr}
|
|
800896e: b082 sub sp, #8
|
|
8008970: af00 add r7, sp, #0
|
|
8008972: 6078 str r0, [r7, #4]
|
|
8008974: 6039 str r1, [r7, #0]
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
8008976: 683b ldr r3, [r7, #0]
|
|
8008978: 885b ldrh r3, [r3, #2]
|
|
800897a: 2b01 cmp r3, #1
|
|
800897c: d107 bne.n 800898e <USBD_SetFeature+0x22>
|
|
{
|
|
pdev->dev_remote_wakeup = 1U;
|
|
800897e: 687b ldr r3, [r7, #4]
|
|
8008980: 2201 movs r2, #1
|
|
8008982: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8008986: 6878 ldr r0, [r7, #4]
|
|
8008988: f000 f932 bl 8008bf0 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
}
|
|
800898c: e013 b.n 80089b6 <USBD_SetFeature+0x4a>
|
|
else if (req->wValue == USB_FEATURE_TEST_MODE)
|
|
800898e: 683b ldr r3, [r7, #0]
|
|
8008990: 885b ldrh r3, [r3, #2]
|
|
8008992: 2b02 cmp r3, #2
|
|
8008994: d10b bne.n 80089ae <USBD_SetFeature+0x42>
|
|
pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8);
|
|
8008996: 683b ldr r3, [r7, #0]
|
|
8008998: 889b ldrh r3, [r3, #4]
|
|
800899a: 0a1b lsrs r3, r3, #8
|
|
800899c: b29b uxth r3, r3
|
|
800899e: b2da uxtb r2, r3
|
|
80089a0: 687b ldr r3, [r7, #4]
|
|
80089a2: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80089a6: 6878 ldr r0, [r7, #4]
|
|
80089a8: f000 f922 bl 8008bf0 <USBD_CtlSendStatus>
|
|
}
|
|
80089ac: e003 b.n 80089b6 <USBD_SetFeature+0x4a>
|
|
USBD_CtlError(pdev, req);
|
|
80089ae: 6839 ldr r1, [r7, #0]
|
|
80089b0: 6878 ldr r0, [r7, #4]
|
|
80089b2: f000 f860 bl 8008a76 <USBD_CtlError>
|
|
}
|
|
80089b6: bf00 nop
|
|
80089b8: 3708 adds r7, #8
|
|
80089ba: 46bd mov sp, r7
|
|
80089bc: bd80 pop {r7, pc}
|
|
|
|
080089be <USBD_ClrFeature>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
80089be: b580 push {r7, lr}
|
|
80089c0: b082 sub sp, #8
|
|
80089c2: af00 add r7, sp, #0
|
|
80089c4: 6078 str r0, [r7, #4]
|
|
80089c6: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
80089c8: 687b ldr r3, [r7, #4]
|
|
80089ca: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80089ce: b2db uxtb r3, r3
|
|
80089d0: 3b01 subs r3, #1
|
|
80089d2: 2b02 cmp r3, #2
|
|
80089d4: d80b bhi.n 80089ee <USBD_ClrFeature+0x30>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
80089d6: 683b ldr r3, [r7, #0]
|
|
80089d8: 885b ldrh r3, [r3, #2]
|
|
80089da: 2b01 cmp r3, #1
|
|
80089dc: d10c bne.n 80089f8 <USBD_ClrFeature+0x3a>
|
|
{
|
|
pdev->dev_remote_wakeup = 0U;
|
|
80089de: 687b ldr r3, [r7, #4]
|
|
80089e0: 2200 movs r2, #0
|
|
80089e2: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80089e6: 6878 ldr r0, [r7, #4]
|
|
80089e8: f000 f902 bl 8008bf0 <USBD_CtlSendStatus>
|
|
}
|
|
break;
|
|
80089ec: e004 b.n 80089f8 <USBD_ClrFeature+0x3a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80089ee: 6839 ldr r1, [r7, #0]
|
|
80089f0: 6878 ldr r0, [r7, #4]
|
|
80089f2: f000 f840 bl 8008a76 <USBD_CtlError>
|
|
break;
|
|
80089f6: e000 b.n 80089fa <USBD_ClrFeature+0x3c>
|
|
break;
|
|
80089f8: bf00 nop
|
|
}
|
|
}
|
|
80089fa: bf00 nop
|
|
80089fc: 3708 adds r7, #8
|
|
80089fe: 46bd mov sp, r7
|
|
8008a00: bd80 pop {r7, pc}
|
|
|
|
08008a02 <USBD_ParseSetupRequest>:
|
|
* @param req: usb request
|
|
* @param pdata: setup data pointer
|
|
* @retval None
|
|
*/
|
|
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
|
|
{
|
|
8008a02: b580 push {r7, lr}
|
|
8008a04: b084 sub sp, #16
|
|
8008a06: af00 add r7, sp, #0
|
|
8008a08: 6078 str r0, [r7, #4]
|
|
8008a0a: 6039 str r1, [r7, #0]
|
|
uint8_t *pbuff = pdata;
|
|
8008a0c: 683b ldr r3, [r7, #0]
|
|
8008a0e: 60fb str r3, [r7, #12]
|
|
|
|
req->bmRequest = *(uint8_t *)(pbuff);
|
|
8008a10: 68fb ldr r3, [r7, #12]
|
|
8008a12: 781a ldrb r2, [r3, #0]
|
|
8008a14: 687b ldr r3, [r7, #4]
|
|
8008a16: 701a strb r2, [r3, #0]
|
|
|
|
pbuff++;
|
|
8008a18: 68fb ldr r3, [r7, #12]
|
|
8008a1a: 3301 adds r3, #1
|
|
8008a1c: 60fb str r3, [r7, #12]
|
|
req->bRequest = *(uint8_t *)(pbuff);
|
|
8008a1e: 68fb ldr r3, [r7, #12]
|
|
8008a20: 781a ldrb r2, [r3, #0]
|
|
8008a22: 687b ldr r3, [r7, #4]
|
|
8008a24: 705a strb r2, [r3, #1]
|
|
|
|
pbuff++;
|
|
8008a26: 68fb ldr r3, [r7, #12]
|
|
8008a28: 3301 adds r3, #1
|
|
8008a2a: 60fb str r3, [r7, #12]
|
|
req->wValue = SWAPBYTE(pbuff);
|
|
8008a2c: 68f8 ldr r0, [r7, #12]
|
|
8008a2e: f7ff fa13 bl 8007e58 <SWAPBYTE>
|
|
8008a32: 4603 mov r3, r0
|
|
8008a34: 461a mov r2, r3
|
|
8008a36: 687b ldr r3, [r7, #4]
|
|
8008a38: 805a strh r2, [r3, #2]
|
|
|
|
pbuff++;
|
|
8008a3a: 68fb ldr r3, [r7, #12]
|
|
8008a3c: 3301 adds r3, #1
|
|
8008a3e: 60fb str r3, [r7, #12]
|
|
pbuff++;
|
|
8008a40: 68fb ldr r3, [r7, #12]
|
|
8008a42: 3301 adds r3, #1
|
|
8008a44: 60fb str r3, [r7, #12]
|
|
req->wIndex = SWAPBYTE(pbuff);
|
|
8008a46: 68f8 ldr r0, [r7, #12]
|
|
8008a48: f7ff fa06 bl 8007e58 <SWAPBYTE>
|
|
8008a4c: 4603 mov r3, r0
|
|
8008a4e: 461a mov r2, r3
|
|
8008a50: 687b ldr r3, [r7, #4]
|
|
8008a52: 809a strh r2, [r3, #4]
|
|
|
|
pbuff++;
|
|
8008a54: 68fb ldr r3, [r7, #12]
|
|
8008a56: 3301 adds r3, #1
|
|
8008a58: 60fb str r3, [r7, #12]
|
|
pbuff++;
|
|
8008a5a: 68fb ldr r3, [r7, #12]
|
|
8008a5c: 3301 adds r3, #1
|
|
8008a5e: 60fb str r3, [r7, #12]
|
|
req->wLength = SWAPBYTE(pbuff);
|
|
8008a60: 68f8 ldr r0, [r7, #12]
|
|
8008a62: f7ff f9f9 bl 8007e58 <SWAPBYTE>
|
|
8008a66: 4603 mov r3, r0
|
|
8008a68: 461a mov r2, r3
|
|
8008a6a: 687b ldr r3, [r7, #4]
|
|
8008a6c: 80da strh r2, [r3, #6]
|
|
}
|
|
8008a6e: bf00 nop
|
|
8008a70: 3710 adds r7, #16
|
|
8008a72: 46bd mov sp, r7
|
|
8008a74: bd80 pop {r7, pc}
|
|
|
|
08008a76 <USBD_CtlError>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008a76: b580 push {r7, lr}
|
|
8008a78: b082 sub sp, #8
|
|
8008a7a: af00 add r7, sp, #0
|
|
8008a7c: 6078 str r0, [r7, #4]
|
|
8008a7e: 6039 str r1, [r7, #0]
|
|
UNUSED(req);
|
|
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8008a80: 2180 movs r1, #128 @ 0x80
|
|
8008a82: 6878 ldr r0, [r7, #4]
|
|
8008a84: f000 fc2a bl 80092dc <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0U);
|
|
8008a88: 2100 movs r1, #0
|
|
8008a8a: 6878 ldr r0, [r7, #4]
|
|
8008a8c: f000 fc26 bl 80092dc <USBD_LL_StallEP>
|
|
}
|
|
8008a90: bf00 nop
|
|
8008a92: 3708 adds r7, #8
|
|
8008a94: 46bd mov sp, r7
|
|
8008a96: bd80 pop {r7, pc}
|
|
|
|
08008a98 <USBD_GetString>:
|
|
* @param unicode : Formatted string buffer (unicode)
|
|
* @param len : descriptor length
|
|
* @retval None
|
|
*/
|
|
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
|
|
{
|
|
8008a98: b580 push {r7, lr}
|
|
8008a9a: b086 sub sp, #24
|
|
8008a9c: af00 add r7, sp, #0
|
|
8008a9e: 60f8 str r0, [r7, #12]
|
|
8008aa0: 60b9 str r1, [r7, #8]
|
|
8008aa2: 607a str r2, [r7, #4]
|
|
uint8_t idx = 0U;
|
|
8008aa4: 2300 movs r3, #0
|
|
8008aa6: 75fb strb r3, [r7, #23]
|
|
uint8_t *pdesc;
|
|
|
|
if (desc == NULL)
|
|
8008aa8: 68fb ldr r3, [r7, #12]
|
|
8008aaa: 2b00 cmp r3, #0
|
|
8008aac: d042 beq.n 8008b34 <USBD_GetString+0x9c>
|
|
{
|
|
return;
|
|
}
|
|
|
|
pdesc = desc;
|
|
8008aae: 68fb ldr r3, [r7, #12]
|
|
8008ab0: 613b str r3, [r7, #16]
|
|
*len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U);
|
|
8008ab2: 6938 ldr r0, [r7, #16]
|
|
8008ab4: f000 f842 bl 8008b3c <USBD_GetLen>
|
|
8008ab8: 4603 mov r3, r0
|
|
8008aba: 3301 adds r3, #1
|
|
8008abc: 005b lsls r3, r3, #1
|
|
8008abe: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8008ac2: d808 bhi.n 8008ad6 <USBD_GetString+0x3e>
|
|
8008ac4: 6938 ldr r0, [r7, #16]
|
|
8008ac6: f000 f839 bl 8008b3c <USBD_GetLen>
|
|
8008aca: 4603 mov r3, r0
|
|
8008acc: 3301 adds r3, #1
|
|
8008ace: b29b uxth r3, r3
|
|
8008ad0: 005b lsls r3, r3, #1
|
|
8008ad2: b29a uxth r2, r3
|
|
8008ad4: e001 b.n 8008ada <USBD_GetString+0x42>
|
|
8008ad6: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8008ada: 687b ldr r3, [r7, #4]
|
|
8008adc: 801a strh r2, [r3, #0]
|
|
|
|
unicode[idx] = *(uint8_t *)len;
|
|
8008ade: 7dfb ldrb r3, [r7, #23]
|
|
8008ae0: 68ba ldr r2, [r7, #8]
|
|
8008ae2: 4413 add r3, r2
|
|
8008ae4: 687a ldr r2, [r7, #4]
|
|
8008ae6: 7812 ldrb r2, [r2, #0]
|
|
8008ae8: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8008aea: 7dfb ldrb r3, [r7, #23]
|
|
8008aec: 3301 adds r3, #1
|
|
8008aee: 75fb strb r3, [r7, #23]
|
|
unicode[idx] = USB_DESC_TYPE_STRING;
|
|
8008af0: 7dfb ldrb r3, [r7, #23]
|
|
8008af2: 68ba ldr r2, [r7, #8]
|
|
8008af4: 4413 add r3, r2
|
|
8008af6: 2203 movs r2, #3
|
|
8008af8: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8008afa: 7dfb ldrb r3, [r7, #23]
|
|
8008afc: 3301 adds r3, #1
|
|
8008afe: 75fb strb r3, [r7, #23]
|
|
|
|
while (*pdesc != (uint8_t)'\0')
|
|
8008b00: e013 b.n 8008b2a <USBD_GetString+0x92>
|
|
{
|
|
unicode[idx] = *pdesc;
|
|
8008b02: 7dfb ldrb r3, [r7, #23]
|
|
8008b04: 68ba ldr r2, [r7, #8]
|
|
8008b06: 4413 add r3, r2
|
|
8008b08: 693a ldr r2, [r7, #16]
|
|
8008b0a: 7812 ldrb r2, [r2, #0]
|
|
8008b0c: 701a strb r2, [r3, #0]
|
|
pdesc++;
|
|
8008b0e: 693b ldr r3, [r7, #16]
|
|
8008b10: 3301 adds r3, #1
|
|
8008b12: 613b str r3, [r7, #16]
|
|
idx++;
|
|
8008b14: 7dfb ldrb r3, [r7, #23]
|
|
8008b16: 3301 adds r3, #1
|
|
8008b18: 75fb strb r3, [r7, #23]
|
|
|
|
unicode[idx] = 0U;
|
|
8008b1a: 7dfb ldrb r3, [r7, #23]
|
|
8008b1c: 68ba ldr r2, [r7, #8]
|
|
8008b1e: 4413 add r3, r2
|
|
8008b20: 2200 movs r2, #0
|
|
8008b22: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8008b24: 7dfb ldrb r3, [r7, #23]
|
|
8008b26: 3301 adds r3, #1
|
|
8008b28: 75fb strb r3, [r7, #23]
|
|
while (*pdesc != (uint8_t)'\0')
|
|
8008b2a: 693b ldr r3, [r7, #16]
|
|
8008b2c: 781b ldrb r3, [r3, #0]
|
|
8008b2e: 2b00 cmp r3, #0
|
|
8008b30: d1e7 bne.n 8008b02 <USBD_GetString+0x6a>
|
|
8008b32: e000 b.n 8008b36 <USBD_GetString+0x9e>
|
|
return;
|
|
8008b34: bf00 nop
|
|
}
|
|
}
|
|
8008b36: 3718 adds r7, #24
|
|
8008b38: 46bd mov sp, r7
|
|
8008b3a: bd80 pop {r7, pc}
|
|
|
|
08008b3c <USBD_GetLen>:
|
|
* return the string length
|
|
* @param buf : pointer to the ascii string buffer
|
|
* @retval string length
|
|
*/
|
|
static uint8_t USBD_GetLen(uint8_t *buf)
|
|
{
|
|
8008b3c: b480 push {r7}
|
|
8008b3e: b085 sub sp, #20
|
|
8008b40: af00 add r7, sp, #0
|
|
8008b42: 6078 str r0, [r7, #4]
|
|
uint8_t len = 0U;
|
|
8008b44: 2300 movs r3, #0
|
|
8008b46: 73fb strb r3, [r7, #15]
|
|
uint8_t *pbuff = buf;
|
|
8008b48: 687b ldr r3, [r7, #4]
|
|
8008b4a: 60bb str r3, [r7, #8]
|
|
|
|
while (*pbuff != (uint8_t)'\0')
|
|
8008b4c: e005 b.n 8008b5a <USBD_GetLen+0x1e>
|
|
{
|
|
len++;
|
|
8008b4e: 7bfb ldrb r3, [r7, #15]
|
|
8008b50: 3301 adds r3, #1
|
|
8008b52: 73fb strb r3, [r7, #15]
|
|
pbuff++;
|
|
8008b54: 68bb ldr r3, [r7, #8]
|
|
8008b56: 3301 adds r3, #1
|
|
8008b58: 60bb str r3, [r7, #8]
|
|
while (*pbuff != (uint8_t)'\0')
|
|
8008b5a: 68bb ldr r3, [r7, #8]
|
|
8008b5c: 781b ldrb r3, [r3, #0]
|
|
8008b5e: 2b00 cmp r3, #0
|
|
8008b60: d1f5 bne.n 8008b4e <USBD_GetLen+0x12>
|
|
}
|
|
|
|
return len;
|
|
8008b62: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008b64: 4618 mov r0, r3
|
|
8008b66: 3714 adds r7, #20
|
|
8008b68: 46bd mov sp, r7
|
|
8008b6a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008b6e: 4770 bx lr
|
|
|
|
08008b70 <USBD_CtlSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8008b70: b580 push {r7, lr}
|
|
8008b72: b084 sub sp, #16
|
|
8008b74: af00 add r7, sp, #0
|
|
8008b76: 60f8 str r0, [r7, #12]
|
|
8008b78: 60b9 str r1, [r7, #8]
|
|
8008b7a: 607a str r2, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_DATA_IN;
|
|
8008b7c: 68fb ldr r3, [r7, #12]
|
|
8008b7e: 2202 movs r2, #2
|
|
8008b80: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->ep_in[0].total_length = len;
|
|
8008b84: 68fb ldr r3, [r7, #12]
|
|
8008b86: 687a ldr r2, [r7, #4]
|
|
8008b88: 615a str r2, [r3, #20]
|
|
pdev->ep_in[0].pbuffer = pbuf;
|
|
8008b8a: 68fb ldr r3, [r7, #12]
|
|
8008b8c: 68ba ldr r2, [r7, #8]
|
|
8008b8e: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
|
|
pdev->ep_in[0].rem_length = 0U;
|
|
#else
|
|
pdev->ep_in[0].rem_length = len;
|
|
8008b90: 68fb ldr r3, [r7, #12]
|
|
8008b92: 687a ldr r2, [r7, #4]
|
|
8008b94: 619a str r2, [r3, #24]
|
|
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
8008b96: 687b ldr r3, [r7, #4]
|
|
8008b98: 68ba ldr r2, [r7, #8]
|
|
8008b9a: 2100 movs r1, #0
|
|
8008b9c: 68f8 ldr r0, [r7, #12]
|
|
8008b9e: f000 fc26 bl 80093ee <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8008ba2: 2300 movs r3, #0
|
|
}
|
|
8008ba4: 4618 mov r0, r3
|
|
8008ba6: 3710 adds r7, #16
|
|
8008ba8: 46bd mov sp, r7
|
|
8008baa: bd80 pop {r7, pc}
|
|
|
|
08008bac <USBD_CtlContinueSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8008bac: b580 push {r7, lr}
|
|
8008bae: b084 sub sp, #16
|
|
8008bb0: af00 add r7, sp, #0
|
|
8008bb2: 60f8 str r0, [r7, #12]
|
|
8008bb4: 60b9 str r1, [r7, #8]
|
|
8008bb6: 607a str r2, [r7, #4]
|
|
/* Start the next transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
8008bb8: 687b ldr r3, [r7, #4]
|
|
8008bba: 68ba ldr r2, [r7, #8]
|
|
8008bbc: 2100 movs r1, #0
|
|
8008bbe: 68f8 ldr r0, [r7, #12]
|
|
8008bc0: f000 fc15 bl 80093ee <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8008bc4: 2300 movs r3, #0
|
|
}
|
|
8008bc6: 4618 mov r0, r3
|
|
8008bc8: 3710 adds r7, #16
|
|
8008bca: 46bd mov sp, r7
|
|
8008bcc: bd80 pop {r7, pc}
|
|
|
|
08008bce <USBD_CtlContinueRx>:
|
|
* @param len: length of data to be received
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8008bce: b580 push {r7, lr}
|
|
8008bd0: b084 sub sp, #16
|
|
8008bd2: af00 add r7, sp, #0
|
|
8008bd4: 60f8 str r0, [r7, #12]
|
|
8008bd6: 60b9 str r1, [r7, #8]
|
|
8008bd8: 607a str r2, [r7, #4]
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
|
|
8008bda: 687b ldr r3, [r7, #4]
|
|
8008bdc: 68ba ldr r2, [r7, #8]
|
|
8008bde: 2100 movs r1, #0
|
|
8008be0: 68f8 ldr r0, [r7, #12]
|
|
8008be2: f000 fc25 bl 8009430 <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8008be6: 2300 movs r3, #0
|
|
}
|
|
8008be8: 4618 mov r0, r3
|
|
8008bea: 3710 adds r7, #16
|
|
8008bec: 46bd mov sp, r7
|
|
8008bee: bd80 pop {r7, pc}
|
|
|
|
08008bf0 <USBD_CtlSendStatus>:
|
|
* send zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008bf0: b580 push {r7, lr}
|
|
8008bf2: b082 sub sp, #8
|
|
8008bf4: af00 add r7, sp, #0
|
|
8008bf6: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_IN;
|
|
8008bf8: 687b ldr r3, [r7, #4]
|
|
8008bfa: 2204 movs r2, #4
|
|
8008bfc: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
|
|
8008c00: 2300 movs r3, #0
|
|
8008c02: 2200 movs r2, #0
|
|
8008c04: 2100 movs r1, #0
|
|
8008c06: 6878 ldr r0, [r7, #4]
|
|
8008c08: f000 fbf1 bl 80093ee <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8008c0c: 2300 movs r3, #0
|
|
}
|
|
8008c0e: 4618 mov r0, r3
|
|
8008c10: 3708 adds r7, #8
|
|
8008c12: 46bd mov sp, r7
|
|
8008c14: bd80 pop {r7, pc}
|
|
|
|
08008c16 <USBD_CtlReceiveStatus>:
|
|
* receive zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008c16: b580 push {r7, lr}
|
|
8008c18: b082 sub sp, #8
|
|
8008c1a: af00 add r7, sp, #0
|
|
8008c1c: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_OUT;
|
|
8008c1e: 687b ldr r3, [r7, #4]
|
|
8008c20: 2205 movs r2, #5
|
|
8008c22: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8008c26: 2300 movs r3, #0
|
|
8008c28: 2200 movs r2, #0
|
|
8008c2a: 2100 movs r1, #0
|
|
8008c2c: 6878 ldr r0, [r7, #4]
|
|
8008c2e: f000 fbff bl 8009430 <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8008c32: 2300 movs r3, #0
|
|
}
|
|
8008c34: 4618 mov r0, r3
|
|
8008c36: 3708 adds r7, #8
|
|
8008c38: 46bd mov sp, r7
|
|
8008c3a: bd80 pop {r7, pc}
|
|
|
|
08008c3c <MX_USB_DEVICE_Init>:
|
|
/**
|
|
* Init USB device Library, add supported class and start the library
|
|
* @retval None
|
|
*/
|
|
void MX_USB_DEVICE_Init(void)
|
|
{
|
|
8008c3c: b580 push {r7, lr}
|
|
8008c3e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
|
|
|
|
/* USER CODE END USB_DEVICE_Init_PreTreatment */
|
|
|
|
/* Init Device Library, add supported class and start the library. */
|
|
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
|
|
8008c40: 2200 movs r2, #0
|
|
8008c42: 490e ldr r1, [pc, #56] @ (8008c7c <MX_USB_DEVICE_Init+0x40>)
|
|
8008c44: 480e ldr r0, [pc, #56] @ (8008c80 <MX_USB_DEVICE_Init+0x44>)
|
|
8008c46: f7fe fcd1 bl 80075ec <USBD_Init>
|
|
8008c4a: 4603 mov r3, r0
|
|
8008c4c: 2b00 cmp r3, #0
|
|
8008c4e: d001 beq.n 8008c54 <MX_USB_DEVICE_Init+0x18>
|
|
{
|
|
Error_Handler();
|
|
8008c50: f7f8 f936 bl 8000ec0 <Error_Handler>
|
|
}
|
|
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK)
|
|
8008c54: 490b ldr r1, [pc, #44] @ (8008c84 <MX_USB_DEVICE_Init+0x48>)
|
|
8008c56: 480a ldr r0, [pc, #40] @ (8008c80 <MX_USB_DEVICE_Init+0x44>)
|
|
8008c58: f7fe fcf8 bl 800764c <USBD_RegisterClass>
|
|
8008c5c: 4603 mov r3, r0
|
|
8008c5e: 2b00 cmp r3, #0
|
|
8008c60: d001 beq.n 8008c66 <MX_USB_DEVICE_Init+0x2a>
|
|
{
|
|
Error_Handler();
|
|
8008c62: f7f8 f92d bl 8000ec0 <Error_Handler>
|
|
}
|
|
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
|
|
8008c66: 4806 ldr r0, [pc, #24] @ (8008c80 <MX_USB_DEVICE_Init+0x44>)
|
|
8008c68: f7fe fd26 bl 80076b8 <USBD_Start>
|
|
8008c6c: 4603 mov r3, r0
|
|
8008c6e: 2b00 cmp r3, #0
|
|
8008c70: d001 beq.n 8008c76 <MX_USB_DEVICE_Init+0x3a>
|
|
{
|
|
Error_Handler();
|
|
8008c72: f7f8 f925 bl 8000ec0 <Error_Handler>
|
|
}
|
|
|
|
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
|
|
|
|
/* USER CODE END USB_DEVICE_Init_PostTreatment */
|
|
}
|
|
8008c76: bf00 nop
|
|
8008c78: bd80 pop {r7, pc}
|
|
8008c7a: bf00 nop
|
|
8008c7c: 20000128 .word 0x20000128
|
|
8008c80: 20000508 .word 0x20000508
|
|
8008c84: 20000084 .word 0x20000084
|
|
|
|
08008c88 <USBD_FS_DeviceDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008c88: b480 push {r7}
|
|
8008c8a: b083 sub sp, #12
|
|
8008c8c: af00 add r7, sp, #0
|
|
8008c8e: 4603 mov r3, r0
|
|
8008c90: 6039 str r1, [r7, #0]
|
|
8008c92: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_FS_DeviceDesc);
|
|
8008c94: 683b ldr r3, [r7, #0]
|
|
8008c96: 2212 movs r2, #18
|
|
8008c98: 801a strh r2, [r3, #0]
|
|
return USBD_FS_DeviceDesc;
|
|
8008c9a: 4b03 ldr r3, [pc, #12] @ (8008ca8 <USBD_FS_DeviceDescriptor+0x20>)
|
|
}
|
|
8008c9c: 4618 mov r0, r3
|
|
8008c9e: 370c adds r7, #12
|
|
8008ca0: 46bd mov sp, r7
|
|
8008ca2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008ca6: 4770 bx lr
|
|
8008ca8: 20000148 .word 0x20000148
|
|
|
|
08008cac <USBD_FS_LangIDStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008cac: b480 push {r7}
|
|
8008cae: b083 sub sp, #12
|
|
8008cb0: af00 add r7, sp, #0
|
|
8008cb2: 4603 mov r3, r0
|
|
8008cb4: 6039 str r1, [r7, #0]
|
|
8008cb6: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_LangIDDesc);
|
|
8008cb8: 683b ldr r3, [r7, #0]
|
|
8008cba: 2204 movs r2, #4
|
|
8008cbc: 801a strh r2, [r3, #0]
|
|
return USBD_LangIDDesc;
|
|
8008cbe: 4b03 ldr r3, [pc, #12] @ (8008ccc <USBD_FS_LangIDStrDescriptor+0x20>)
|
|
}
|
|
8008cc0: 4618 mov r0, r3
|
|
8008cc2: 370c adds r7, #12
|
|
8008cc4: 46bd mov sp, r7
|
|
8008cc6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008cca: 4770 bx lr
|
|
8008ccc: 20000168 .word 0x20000168
|
|
|
|
08008cd0 <USBD_FS_ProductStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008cd0: b580 push {r7, lr}
|
|
8008cd2: b082 sub sp, #8
|
|
8008cd4: af00 add r7, sp, #0
|
|
8008cd6: 4603 mov r3, r0
|
|
8008cd8: 6039 str r1, [r7, #0]
|
|
8008cda: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
8008cdc: 79fb ldrb r3, [r7, #7]
|
|
8008cde: 2b00 cmp r3, #0
|
|
8008ce0: d105 bne.n 8008cee <USBD_FS_ProductStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
|
|
8008ce2: 683a ldr r2, [r7, #0]
|
|
8008ce4: 4907 ldr r1, [pc, #28] @ (8008d04 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
8008ce6: 4808 ldr r0, [pc, #32] @ (8008d08 <USBD_FS_ProductStrDescriptor+0x38>)
|
|
8008ce8: f7ff fed6 bl 8008a98 <USBD_GetString>
|
|
8008cec: e004 b.n 8008cf8 <USBD_FS_ProductStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
|
|
8008cee: 683a ldr r2, [r7, #0]
|
|
8008cf0: 4904 ldr r1, [pc, #16] @ (8008d04 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
8008cf2: 4805 ldr r0, [pc, #20] @ (8008d08 <USBD_FS_ProductStrDescriptor+0x38>)
|
|
8008cf4: f7ff fed0 bl 8008a98 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8008cf8: 4b02 ldr r3, [pc, #8] @ (8008d04 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
}
|
|
8008cfa: 4618 mov r0, r3
|
|
8008cfc: 3708 adds r7, #8
|
|
8008cfe: 46bd mov sp, r7
|
|
8008d00: bd80 pop {r7, pc}
|
|
8008d02: bf00 nop
|
|
8008d04: 200007e4 .word 0x200007e4
|
|
8008d08: 08009608 .word 0x08009608
|
|
|
|
08008d0c <USBD_FS_ManufacturerStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008d0c: b580 push {r7, lr}
|
|
8008d0e: b082 sub sp, #8
|
|
8008d10: af00 add r7, sp, #0
|
|
8008d12: 4603 mov r3, r0
|
|
8008d14: 6039 str r1, [r7, #0]
|
|
8008d16: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
|
|
8008d18: 683a ldr r2, [r7, #0]
|
|
8008d1a: 4904 ldr r1, [pc, #16] @ (8008d2c <USBD_FS_ManufacturerStrDescriptor+0x20>)
|
|
8008d1c: 4804 ldr r0, [pc, #16] @ (8008d30 <USBD_FS_ManufacturerStrDescriptor+0x24>)
|
|
8008d1e: f7ff febb bl 8008a98 <USBD_GetString>
|
|
return USBD_StrDesc;
|
|
8008d22: 4b02 ldr r3, [pc, #8] @ (8008d2c <USBD_FS_ManufacturerStrDescriptor+0x20>)
|
|
}
|
|
8008d24: 4618 mov r0, r3
|
|
8008d26: 3708 adds r7, #8
|
|
8008d28: 46bd mov sp, r7
|
|
8008d2a: bd80 pop {r7, pc}
|
|
8008d2c: 200007e4 .word 0x200007e4
|
|
8008d30: 0800961c .word 0x0800961c
|
|
|
|
08008d34 <USBD_FS_SerialStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008d34: b580 push {r7, lr}
|
|
8008d36: b082 sub sp, #8
|
|
8008d38: af00 add r7, sp, #0
|
|
8008d3a: 4603 mov r3, r0
|
|
8008d3c: 6039 str r1, [r7, #0]
|
|
8008d3e: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = USB_SIZ_STRING_SERIAL;
|
|
8008d40: 683b ldr r3, [r7, #0]
|
|
8008d42: 221a movs r2, #26
|
|
8008d44: 801a strh r2, [r3, #0]
|
|
|
|
/* Update the serial number string descriptor with the data from the unique
|
|
* ID */
|
|
Get_SerialNum();
|
|
8008d46: f000 f855 bl 8008df4 <Get_SerialNum>
|
|
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
|
|
|
|
/* USER CODE END USBD_FS_SerialStrDescriptor */
|
|
return (uint8_t *) USBD_StringSerial;
|
|
8008d4a: 4b02 ldr r3, [pc, #8] @ (8008d54 <USBD_FS_SerialStrDescriptor+0x20>)
|
|
}
|
|
8008d4c: 4618 mov r0, r3
|
|
8008d4e: 3708 adds r7, #8
|
|
8008d50: 46bd mov sp, r7
|
|
8008d52: bd80 pop {r7, pc}
|
|
8008d54: 2000016c .word 0x2000016c
|
|
|
|
08008d58 <USBD_FS_ConfigStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008d58: b580 push {r7, lr}
|
|
8008d5a: b082 sub sp, #8
|
|
8008d5c: af00 add r7, sp, #0
|
|
8008d5e: 4603 mov r3, r0
|
|
8008d60: 6039 str r1, [r7, #0]
|
|
8008d62: 71fb strb r3, [r7, #7]
|
|
if(speed == USBD_SPEED_HIGH)
|
|
8008d64: 79fb ldrb r3, [r7, #7]
|
|
8008d66: 2b00 cmp r3, #0
|
|
8008d68: d105 bne.n 8008d76 <USBD_FS_ConfigStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
|
|
8008d6a: 683a ldr r2, [r7, #0]
|
|
8008d6c: 4907 ldr r1, [pc, #28] @ (8008d8c <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
8008d6e: 4808 ldr r0, [pc, #32] @ (8008d90 <USBD_FS_ConfigStrDescriptor+0x38>)
|
|
8008d70: f7ff fe92 bl 8008a98 <USBD_GetString>
|
|
8008d74: e004 b.n 8008d80 <USBD_FS_ConfigStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
|
|
8008d76: 683a ldr r2, [r7, #0]
|
|
8008d78: 4904 ldr r1, [pc, #16] @ (8008d8c <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
8008d7a: 4805 ldr r0, [pc, #20] @ (8008d90 <USBD_FS_ConfigStrDescriptor+0x38>)
|
|
8008d7c: f7ff fe8c bl 8008a98 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8008d80: 4b02 ldr r3, [pc, #8] @ (8008d8c <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
}
|
|
8008d82: 4618 mov r0, r3
|
|
8008d84: 3708 adds r7, #8
|
|
8008d86: 46bd mov sp, r7
|
|
8008d88: bd80 pop {r7, pc}
|
|
8008d8a: bf00 nop
|
|
8008d8c: 200007e4 .word 0x200007e4
|
|
8008d90: 08009628 .word 0x08009628
|
|
|
|
08008d94 <USBD_FS_InterfaceStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008d94: b580 push {r7, lr}
|
|
8008d96: b082 sub sp, #8
|
|
8008d98: af00 add r7, sp, #0
|
|
8008d9a: 4603 mov r3, r0
|
|
8008d9c: 6039 str r1, [r7, #0]
|
|
8008d9e: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
8008da0: 79fb ldrb r3, [r7, #7]
|
|
8008da2: 2b00 cmp r3, #0
|
|
8008da4: d105 bne.n 8008db2 <USBD_FS_InterfaceStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
|
|
8008da6: 683a ldr r2, [r7, #0]
|
|
8008da8: 4907 ldr r1, [pc, #28] @ (8008dc8 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
8008daa: 4808 ldr r0, [pc, #32] @ (8008dcc <USBD_FS_InterfaceStrDescriptor+0x38>)
|
|
8008dac: f7ff fe74 bl 8008a98 <USBD_GetString>
|
|
8008db0: e004 b.n 8008dbc <USBD_FS_InterfaceStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
|
|
8008db2: 683a ldr r2, [r7, #0]
|
|
8008db4: 4904 ldr r1, [pc, #16] @ (8008dc8 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
8008db6: 4805 ldr r0, [pc, #20] @ (8008dcc <USBD_FS_InterfaceStrDescriptor+0x38>)
|
|
8008db8: f7ff fe6e bl 8008a98 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8008dbc: 4b02 ldr r3, [pc, #8] @ (8008dc8 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
}
|
|
8008dbe: 4618 mov r0, r3
|
|
8008dc0: 3708 adds r7, #8
|
|
8008dc2: 46bd mov sp, r7
|
|
8008dc4: bd80 pop {r7, pc}
|
|
8008dc6: bf00 nop
|
|
8008dc8: 200007e4 .word 0x200007e4
|
|
8008dcc: 08009634 .word 0x08009634
|
|
|
|
08008dd0 <USBD_FS_USR_BOSDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008dd0: b480 push {r7}
|
|
8008dd2: b083 sub sp, #12
|
|
8008dd4: af00 add r7, sp, #0
|
|
8008dd6: 4603 mov r3, r0
|
|
8008dd8: 6039 str r1, [r7, #0]
|
|
8008dda: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_FS_BOSDesc);
|
|
8008ddc: 683b ldr r3, [r7, #0]
|
|
8008dde: 220c movs r2, #12
|
|
8008de0: 801a strh r2, [r3, #0]
|
|
return (uint8_t*)USBD_FS_BOSDesc;
|
|
8008de2: 4b03 ldr r3, [pc, #12] @ (8008df0 <USBD_FS_USR_BOSDescriptor+0x20>)
|
|
}
|
|
8008de4: 4618 mov r0, r3
|
|
8008de6: 370c adds r7, #12
|
|
8008de8: 46bd mov sp, r7
|
|
8008dea: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008dee: 4770 bx lr
|
|
8008df0: 2000015c .word 0x2000015c
|
|
|
|
08008df4 <Get_SerialNum>:
|
|
* @brief Create the serial number string descriptor
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void Get_SerialNum(void)
|
|
{
|
|
8008df4: b580 push {r7, lr}
|
|
8008df6: b084 sub sp, #16
|
|
8008df8: af00 add r7, sp, #0
|
|
uint32_t deviceserial0;
|
|
uint32_t deviceserial1;
|
|
uint32_t deviceserial2;
|
|
|
|
deviceserial0 = *(uint32_t *) DEVICE_ID1;
|
|
8008dfa: 4b0f ldr r3, [pc, #60] @ (8008e38 <Get_SerialNum+0x44>)
|
|
8008dfc: 681b ldr r3, [r3, #0]
|
|
8008dfe: 60fb str r3, [r7, #12]
|
|
deviceserial1 = *(uint32_t *) DEVICE_ID2;
|
|
8008e00: 4b0e ldr r3, [pc, #56] @ (8008e3c <Get_SerialNum+0x48>)
|
|
8008e02: 681b ldr r3, [r3, #0]
|
|
8008e04: 60bb str r3, [r7, #8]
|
|
deviceserial2 = *(uint32_t *) DEVICE_ID3;
|
|
8008e06: 4b0e ldr r3, [pc, #56] @ (8008e40 <Get_SerialNum+0x4c>)
|
|
8008e08: 681b ldr r3, [r3, #0]
|
|
8008e0a: 607b str r3, [r7, #4]
|
|
|
|
deviceserial0 += deviceserial2;
|
|
8008e0c: 68fa ldr r2, [r7, #12]
|
|
8008e0e: 687b ldr r3, [r7, #4]
|
|
8008e10: 4413 add r3, r2
|
|
8008e12: 60fb str r3, [r7, #12]
|
|
|
|
if (deviceserial0 != 0)
|
|
8008e14: 68fb ldr r3, [r7, #12]
|
|
8008e16: 2b00 cmp r3, #0
|
|
8008e18: d009 beq.n 8008e2e <Get_SerialNum+0x3a>
|
|
{
|
|
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
|
|
8008e1a: 2208 movs r2, #8
|
|
8008e1c: 4909 ldr r1, [pc, #36] @ (8008e44 <Get_SerialNum+0x50>)
|
|
8008e1e: 68f8 ldr r0, [r7, #12]
|
|
8008e20: f000 f814 bl 8008e4c <IntToUnicode>
|
|
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
|
|
8008e24: 2204 movs r2, #4
|
|
8008e26: 4908 ldr r1, [pc, #32] @ (8008e48 <Get_SerialNum+0x54>)
|
|
8008e28: 68b8 ldr r0, [r7, #8]
|
|
8008e2a: f000 f80f bl 8008e4c <IntToUnicode>
|
|
}
|
|
}
|
|
8008e2e: bf00 nop
|
|
8008e30: 3710 adds r7, #16
|
|
8008e32: 46bd mov sp, r7
|
|
8008e34: bd80 pop {r7, pc}
|
|
8008e36: bf00 nop
|
|
8008e38: 1fff7a10 .word 0x1fff7a10
|
|
8008e3c: 1fff7a14 .word 0x1fff7a14
|
|
8008e40: 1fff7a18 .word 0x1fff7a18
|
|
8008e44: 2000016e .word 0x2000016e
|
|
8008e48: 2000017e .word 0x2000017e
|
|
|
|
08008e4c <IntToUnicode>:
|
|
* @param pbuf: pointer to the buffer
|
|
* @param len: buffer length
|
|
* @retval None
|
|
*/
|
|
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
|
|
{
|
|
8008e4c: b480 push {r7}
|
|
8008e4e: b087 sub sp, #28
|
|
8008e50: af00 add r7, sp, #0
|
|
8008e52: 60f8 str r0, [r7, #12]
|
|
8008e54: 60b9 str r1, [r7, #8]
|
|
8008e56: 4613 mov r3, r2
|
|
8008e58: 71fb strb r3, [r7, #7]
|
|
uint8_t idx = 0;
|
|
8008e5a: 2300 movs r3, #0
|
|
8008e5c: 75fb strb r3, [r7, #23]
|
|
|
|
for (idx = 0; idx < len; idx++)
|
|
8008e5e: 2300 movs r3, #0
|
|
8008e60: 75fb strb r3, [r7, #23]
|
|
8008e62: e027 b.n 8008eb4 <IntToUnicode+0x68>
|
|
{
|
|
if (((value >> 28)) < 0xA)
|
|
8008e64: 68fb ldr r3, [r7, #12]
|
|
8008e66: 0f1b lsrs r3, r3, #28
|
|
8008e68: 2b09 cmp r3, #9
|
|
8008e6a: d80b bhi.n 8008e84 <IntToUnicode+0x38>
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + '0';
|
|
8008e6c: 68fb ldr r3, [r7, #12]
|
|
8008e6e: 0f1b lsrs r3, r3, #28
|
|
8008e70: b2da uxtb r2, r3
|
|
8008e72: 7dfb ldrb r3, [r7, #23]
|
|
8008e74: 005b lsls r3, r3, #1
|
|
8008e76: 4619 mov r1, r3
|
|
8008e78: 68bb ldr r3, [r7, #8]
|
|
8008e7a: 440b add r3, r1
|
|
8008e7c: 3230 adds r2, #48 @ 0x30
|
|
8008e7e: b2d2 uxtb r2, r2
|
|
8008e80: 701a strb r2, [r3, #0]
|
|
8008e82: e00a b.n 8008e9a <IntToUnicode+0x4e>
|
|
}
|
|
else
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
|
|
8008e84: 68fb ldr r3, [r7, #12]
|
|
8008e86: 0f1b lsrs r3, r3, #28
|
|
8008e88: b2da uxtb r2, r3
|
|
8008e8a: 7dfb ldrb r3, [r7, #23]
|
|
8008e8c: 005b lsls r3, r3, #1
|
|
8008e8e: 4619 mov r1, r3
|
|
8008e90: 68bb ldr r3, [r7, #8]
|
|
8008e92: 440b add r3, r1
|
|
8008e94: 3237 adds r2, #55 @ 0x37
|
|
8008e96: b2d2 uxtb r2, r2
|
|
8008e98: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
value = value << 4;
|
|
8008e9a: 68fb ldr r3, [r7, #12]
|
|
8008e9c: 011b lsls r3, r3, #4
|
|
8008e9e: 60fb str r3, [r7, #12]
|
|
|
|
pbuf[2 * idx + 1] = 0;
|
|
8008ea0: 7dfb ldrb r3, [r7, #23]
|
|
8008ea2: 005b lsls r3, r3, #1
|
|
8008ea4: 3301 adds r3, #1
|
|
8008ea6: 68ba ldr r2, [r7, #8]
|
|
8008ea8: 4413 add r3, r2
|
|
8008eaa: 2200 movs r2, #0
|
|
8008eac: 701a strb r2, [r3, #0]
|
|
for (idx = 0; idx < len; idx++)
|
|
8008eae: 7dfb ldrb r3, [r7, #23]
|
|
8008eb0: 3301 adds r3, #1
|
|
8008eb2: 75fb strb r3, [r7, #23]
|
|
8008eb4: 7dfa ldrb r2, [r7, #23]
|
|
8008eb6: 79fb ldrb r3, [r7, #7]
|
|
8008eb8: 429a cmp r2, r3
|
|
8008eba: d3d3 bcc.n 8008e64 <IntToUnicode+0x18>
|
|
}
|
|
}
|
|
8008ebc: bf00 nop
|
|
8008ebe: bf00 nop
|
|
8008ec0: 371c adds r7, #28
|
|
8008ec2: 46bd mov sp, r7
|
|
8008ec4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008ec8: 4770 bx lr
|
|
...
|
|
|
|
08008ecc <HAL_PCD_MspInit>:
|
|
LL Driver Callbacks (PCD -> USB Device Library)
|
|
*******************************************************************************/
|
|
/* MSP Init */
|
|
|
|
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
|
|
{
|
|
8008ecc: b580 push {r7, lr}
|
|
8008ece: b0a0 sub sp, #128 @ 0x80
|
|
8008ed0: af00 add r7, sp, #0
|
|
8008ed2: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8008ed4: f107 036c add.w r3, r7, #108 @ 0x6c
|
|
8008ed8: 2200 movs r2, #0
|
|
8008eda: 601a str r2, [r3, #0]
|
|
8008edc: 605a str r2, [r3, #4]
|
|
8008ede: 609a str r2, [r3, #8]
|
|
8008ee0: 60da str r2, [r3, #12]
|
|
8008ee2: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
8008ee4: f107 0310 add.w r3, r7, #16
|
|
8008ee8: 225c movs r2, #92 @ 0x5c
|
|
8008eea: 2100 movs r1, #0
|
|
8008eec: 4618 mov r0, r3
|
|
8008eee: f000 fb53 bl 8009598 <memset>
|
|
if(pcdHandle->Instance==USB_OTG_FS)
|
|
8008ef2: 687b ldr r3, [r7, #4]
|
|
8008ef4: 681b ldr r3, [r3, #0]
|
|
8008ef6: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8008efa: d149 bne.n 8008f90 <HAL_PCD_MspInit+0xc4>
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
|
|
8008efc: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8008f00: 613b str r3, [r7, #16]
|
|
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ;
|
|
8008f02: 2300 movs r3, #0
|
|
8008f04: 667b str r3, [r7, #100] @ 0x64
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
8008f06: f107 0310 add.w r3, r7, #16
|
|
8008f0a: 4618 mov r0, r3
|
|
8008f0c: f7fa fb78 bl 8003600 <HAL_RCCEx_PeriphCLKConfig>
|
|
8008f10: 4603 mov r3, r0
|
|
8008f12: 2b00 cmp r3, #0
|
|
8008f14: d001 beq.n 8008f1a <HAL_PCD_MspInit+0x4e>
|
|
{
|
|
Error_Handler();
|
|
8008f16: f7f7 ffd3 bl 8000ec0 <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8008f1a: 2300 movs r3, #0
|
|
8008f1c: 60fb str r3, [r7, #12]
|
|
8008f1e: 4b1e ldr r3, [pc, #120] @ (8008f98 <HAL_PCD_MspInit+0xcc>)
|
|
8008f20: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8008f22: 4a1d ldr r2, [pc, #116] @ (8008f98 <HAL_PCD_MspInit+0xcc>)
|
|
8008f24: f043 0301 orr.w r3, r3, #1
|
|
8008f28: 6313 str r3, [r2, #48] @ 0x30
|
|
8008f2a: 4b1b ldr r3, [pc, #108] @ (8008f98 <HAL_PCD_MspInit+0xcc>)
|
|
8008f2c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8008f2e: f003 0301 and.w r3, r3, #1
|
|
8008f32: 60fb str r3, [r7, #12]
|
|
8008f34: 68fb ldr r3, [r7, #12]
|
|
/**USB_OTG_FS GPIO Configuration
|
|
PA11 ------> USB_OTG_FS_DM
|
|
PA12 ------> USB_OTG_FS_DP
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
|
|
8008f36: f44f 53c0 mov.w r3, #6144 @ 0x1800
|
|
8008f3a: 66fb str r3, [r7, #108] @ 0x6c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8008f3c: 2302 movs r3, #2
|
|
8008f3e: 673b str r3, [r7, #112] @ 0x70
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8008f40: 2300 movs r3, #0
|
|
8008f42: 677b str r3, [r7, #116] @ 0x74
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8008f44: 2303 movs r3, #3
|
|
8008f46: 67bb str r3, [r7, #120] @ 0x78
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
|
|
8008f48: 230a movs r3, #10
|
|
8008f4a: 67fb str r3, [r7, #124] @ 0x7c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8008f4c: f107 036c add.w r3, r7, #108 @ 0x6c
|
|
8008f50: 4619 mov r1, r3
|
|
8008f52: 4812 ldr r0, [pc, #72] @ (8008f9c <HAL_PCD_MspInit+0xd0>)
|
|
8008f54: f7f8 fcaa bl 80018ac <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
|
|
8008f58: 4b0f ldr r3, [pc, #60] @ (8008f98 <HAL_PCD_MspInit+0xcc>)
|
|
8008f5a: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8008f5c: 4a0e ldr r2, [pc, #56] @ (8008f98 <HAL_PCD_MspInit+0xcc>)
|
|
8008f5e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8008f62: 6353 str r3, [r2, #52] @ 0x34
|
|
8008f64: 2300 movs r3, #0
|
|
8008f66: 60bb str r3, [r7, #8]
|
|
8008f68: 4b0b ldr r3, [pc, #44] @ (8008f98 <HAL_PCD_MspInit+0xcc>)
|
|
8008f6a: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008f6c: 4a0a ldr r2, [pc, #40] @ (8008f98 <HAL_PCD_MspInit+0xcc>)
|
|
8008f6e: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8008f72: 6453 str r3, [r2, #68] @ 0x44
|
|
8008f74: 4b08 ldr r3, [pc, #32] @ (8008f98 <HAL_PCD_MspInit+0xcc>)
|
|
8008f76: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008f78: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8008f7c: 60bb str r3, [r7, #8]
|
|
8008f7e: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Peripheral interrupt init */
|
|
HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
|
|
8008f80: 2200 movs r2, #0
|
|
8008f82: 2100 movs r1, #0
|
|
8008f84: 2043 movs r0, #67 @ 0x43
|
|
8008f86: f7f8 fbd4 bl 8001732 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
|
|
8008f8a: 2043 movs r0, #67 @ 0x43
|
|
8008f8c: f7f8 fbed bl 800176a <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 1 */
|
|
}
|
|
}
|
|
8008f90: bf00 nop
|
|
8008f92: 3780 adds r7, #128 @ 0x80
|
|
8008f94: 46bd mov sp, r7
|
|
8008f96: bd80 pop {r7, pc}
|
|
8008f98: 40023800 .word 0x40023800
|
|
8008f9c: 40020000 .word 0x40020000
|
|
|
|
08008fa0 <HAL_PCD_SetupStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8008fa0: b580 push {r7, lr}
|
|
8008fa2: b082 sub sp, #8
|
|
8008fa4: af00 add r7, sp, #0
|
|
8008fa6: 6078 str r0, [r7, #4]
|
|
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
|
|
8008fa8: 687b ldr r3, [r7, #4]
|
|
8008faa: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0
|
|
8008fae: 687b ldr r3, [r7, #4]
|
|
8008fb0: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8008fb4: 4619 mov r1, r3
|
|
8008fb6: 4610 mov r0, r2
|
|
8008fb8: f7fe fbcb bl 8007752 <USBD_LL_SetupStage>
|
|
}
|
|
8008fbc: bf00 nop
|
|
8008fbe: 3708 adds r7, #8
|
|
8008fc0: 46bd mov sp, r7
|
|
8008fc2: bd80 pop {r7, pc}
|
|
|
|
08008fc4 <HAL_PCD_DataOutStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8008fc4: b580 push {r7, lr}
|
|
8008fc6: b082 sub sp, #8
|
|
8008fc8: af00 add r7, sp, #0
|
|
8008fca: 6078 str r0, [r7, #4]
|
|
8008fcc: 460b mov r3, r1
|
|
8008fce: 70fb strb r3, [r7, #3]
|
|
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
|
|
8008fd0: 687b ldr r3, [r7, #4]
|
|
8008fd2: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
|
|
8008fd6: 78fa ldrb r2, [r7, #3]
|
|
8008fd8: 6879 ldr r1, [r7, #4]
|
|
8008fda: 4613 mov r3, r2
|
|
8008fdc: 00db lsls r3, r3, #3
|
|
8008fde: 4413 add r3, r2
|
|
8008fe0: 009b lsls r3, r3, #2
|
|
8008fe2: 440b add r3, r1
|
|
8008fe4: f503 7318 add.w r3, r3, #608 @ 0x260
|
|
8008fe8: 681a ldr r2, [r3, #0]
|
|
8008fea: 78fb ldrb r3, [r7, #3]
|
|
8008fec: 4619 mov r1, r3
|
|
8008fee: f7fe fc05 bl 80077fc <USBD_LL_DataOutStage>
|
|
}
|
|
8008ff2: bf00 nop
|
|
8008ff4: 3708 adds r7, #8
|
|
8008ff6: 46bd mov sp, r7
|
|
8008ff8: bd80 pop {r7, pc}
|
|
|
|
08008ffa <HAL_PCD_DataInStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8008ffa: b580 push {r7, lr}
|
|
8008ffc: b082 sub sp, #8
|
|
8008ffe: af00 add r7, sp, #0
|
|
8009000: 6078 str r0, [r7, #4]
|
|
8009002: 460b mov r3, r1
|
|
8009004: 70fb strb r3, [r7, #3]
|
|
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
|
|
8009006: 687b ldr r3, [r7, #4]
|
|
8009008: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
|
|
800900c: 78fa ldrb r2, [r7, #3]
|
|
800900e: 6879 ldr r1, [r7, #4]
|
|
8009010: 4613 mov r3, r2
|
|
8009012: 00db lsls r3, r3, #3
|
|
8009014: 4413 add r3, r2
|
|
8009016: 009b lsls r3, r3, #2
|
|
8009018: 440b add r3, r1
|
|
800901a: 3320 adds r3, #32
|
|
800901c: 681a ldr r2, [r3, #0]
|
|
800901e: 78fb ldrb r3, [r7, #3]
|
|
8009020: 4619 mov r1, r3
|
|
8009022: f7fe fca7 bl 8007974 <USBD_LL_DataInStage>
|
|
}
|
|
8009026: bf00 nop
|
|
8009028: 3708 adds r7, #8
|
|
800902a: 46bd mov sp, r7
|
|
800902c: bd80 pop {r7, pc}
|
|
|
|
0800902e <HAL_PCD_SOFCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800902e: b580 push {r7, lr}
|
|
8009030: b082 sub sp, #8
|
|
8009032: af00 add r7, sp, #0
|
|
8009034: 6078 str r0, [r7, #4]
|
|
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
|
|
8009036: 687b ldr r3, [r7, #4]
|
|
8009038: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800903c: 4618 mov r0, r3
|
|
800903e: f7fe fdeb bl 8007c18 <USBD_LL_SOF>
|
|
}
|
|
8009042: bf00 nop
|
|
8009044: 3708 adds r7, #8
|
|
8009046: 46bd mov sp, r7
|
|
8009048: bd80 pop {r7, pc}
|
|
|
|
0800904a <HAL_PCD_ResetCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800904a: b580 push {r7, lr}
|
|
800904c: b084 sub sp, #16
|
|
800904e: af00 add r7, sp, #0
|
|
8009050: 6078 str r0, [r7, #4]
|
|
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
|
|
8009052: 2301 movs r3, #1
|
|
8009054: 73fb strb r3, [r7, #15]
|
|
|
|
if ( hpcd->Init.speed == PCD_SPEED_HIGH)
|
|
8009056: 687b ldr r3, [r7, #4]
|
|
8009058: 79db ldrb r3, [r3, #7]
|
|
800905a: 2b00 cmp r3, #0
|
|
800905c: d102 bne.n 8009064 <HAL_PCD_ResetCallback+0x1a>
|
|
{
|
|
speed = USBD_SPEED_HIGH;
|
|
800905e: 2300 movs r3, #0
|
|
8009060: 73fb strb r3, [r7, #15]
|
|
8009062: e008 b.n 8009076 <HAL_PCD_ResetCallback+0x2c>
|
|
}
|
|
else if ( hpcd->Init.speed == PCD_SPEED_FULL)
|
|
8009064: 687b ldr r3, [r7, #4]
|
|
8009066: 79db ldrb r3, [r3, #7]
|
|
8009068: 2b02 cmp r3, #2
|
|
800906a: d102 bne.n 8009072 <HAL_PCD_ResetCallback+0x28>
|
|
{
|
|
speed = USBD_SPEED_FULL;
|
|
800906c: 2301 movs r3, #1
|
|
800906e: 73fb strb r3, [r7, #15]
|
|
8009070: e001 b.n 8009076 <HAL_PCD_ResetCallback+0x2c>
|
|
}
|
|
else
|
|
{
|
|
Error_Handler();
|
|
8009072: f7f7 ff25 bl 8000ec0 <Error_Handler>
|
|
}
|
|
/* Set Speed. */
|
|
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
|
|
8009076: 687b ldr r3, [r7, #4]
|
|
8009078: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800907c: 7bfa ldrb r2, [r7, #15]
|
|
800907e: 4611 mov r1, r2
|
|
8009080: 4618 mov r0, r3
|
|
8009082: f7fe fd85 bl 8007b90 <USBD_LL_SetSpeed>
|
|
|
|
/* Reset Device. */
|
|
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
|
|
8009086: 687b ldr r3, [r7, #4]
|
|
8009088: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800908c: 4618 mov r0, r3
|
|
800908e: f7fe fd2c bl 8007aea <USBD_LL_Reset>
|
|
}
|
|
8009092: bf00 nop
|
|
8009094: 3710 adds r7, #16
|
|
8009096: 46bd mov sp, r7
|
|
8009098: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800909c <HAL_PCD_SuspendCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800909c: b580 push {r7, lr}
|
|
800909e: b082 sub sp, #8
|
|
80090a0: af00 add r7, sp, #0
|
|
80090a2: 6078 str r0, [r7, #4]
|
|
/* Inform USB library that core enters in suspend Mode. */
|
|
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
|
|
80090a4: 687b ldr r3, [r7, #4]
|
|
80090a6: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
80090aa: 4618 mov r0, r3
|
|
80090ac: f7fe fd80 bl 8007bb0 <USBD_LL_Suspend>
|
|
__HAL_PCD_GATE_PHYCLOCK(hpcd);
|
|
80090b0: 687b ldr r3, [r7, #4]
|
|
80090b2: 681b ldr r3, [r3, #0]
|
|
80090b4: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80090b8: 681b ldr r3, [r3, #0]
|
|
80090ba: 687a ldr r2, [r7, #4]
|
|
80090bc: 6812 ldr r2, [r2, #0]
|
|
80090be: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
80090c2: f043 0301 orr.w r3, r3, #1
|
|
80090c6: 6013 str r3, [r2, #0]
|
|
/* Enter in STOP mode. */
|
|
/* USER CODE BEGIN 2 */
|
|
if (hpcd->Init.low_power_enable)
|
|
80090c8: 687b ldr r3, [r7, #4]
|
|
80090ca: 7adb ldrb r3, [r3, #11]
|
|
80090cc: 2b00 cmp r3, #0
|
|
80090ce: d005 beq.n 80090dc <HAL_PCD_SuspendCallback+0x40>
|
|
{
|
|
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
80090d0: 4b04 ldr r3, [pc, #16] @ (80090e4 <HAL_PCD_SuspendCallback+0x48>)
|
|
80090d2: 691b ldr r3, [r3, #16]
|
|
80090d4: 4a03 ldr r2, [pc, #12] @ (80090e4 <HAL_PCD_SuspendCallback+0x48>)
|
|
80090d6: f043 0306 orr.w r3, r3, #6
|
|
80090da: 6113 str r3, [r2, #16]
|
|
}
|
|
/* USER CODE END 2 */
|
|
}
|
|
80090dc: bf00 nop
|
|
80090de: 3708 adds r7, #8
|
|
80090e0: 46bd mov sp, r7
|
|
80090e2: bd80 pop {r7, pc}
|
|
80090e4: e000ed00 .word 0xe000ed00
|
|
|
|
080090e8 <HAL_PCD_ResumeCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
80090e8: b580 push {r7, lr}
|
|
80090ea: b082 sub sp, #8
|
|
80090ec: af00 add r7, sp, #0
|
|
80090ee: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN 3 */
|
|
|
|
/* USER CODE END 3 */
|
|
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
|
|
80090f0: 687b ldr r3, [r7, #4]
|
|
80090f2: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
80090f6: 4618 mov r0, r3
|
|
80090f8: f7fe fd76 bl 8007be8 <USBD_LL_Resume>
|
|
}
|
|
80090fc: bf00 nop
|
|
80090fe: 3708 adds r7, #8
|
|
8009100: 46bd mov sp, r7
|
|
8009102: bd80 pop {r7, pc}
|
|
|
|
08009104 <HAL_PCD_ISOOUTIncompleteCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009104: b580 push {r7, lr}
|
|
8009106: b082 sub sp, #8
|
|
8009108: af00 add r7, sp, #0
|
|
800910a: 6078 str r0, [r7, #4]
|
|
800910c: 460b mov r3, r1
|
|
800910e: 70fb strb r3, [r7, #3]
|
|
USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
|
|
8009110: 687b ldr r3, [r7, #4]
|
|
8009112: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
8009116: 78fa ldrb r2, [r7, #3]
|
|
8009118: 4611 mov r1, r2
|
|
800911a: 4618 mov r0, r3
|
|
800911c: f7fe fdce bl 8007cbc <USBD_LL_IsoOUTIncomplete>
|
|
}
|
|
8009120: bf00 nop
|
|
8009122: 3708 adds r7, #8
|
|
8009124: 46bd mov sp, r7
|
|
8009126: bd80 pop {r7, pc}
|
|
|
|
08009128 <HAL_PCD_ISOINIncompleteCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009128: b580 push {r7, lr}
|
|
800912a: b082 sub sp, #8
|
|
800912c: af00 add r7, sp, #0
|
|
800912e: 6078 str r0, [r7, #4]
|
|
8009130: 460b mov r3, r1
|
|
8009132: 70fb strb r3, [r7, #3]
|
|
USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
|
|
8009134: 687b ldr r3, [r7, #4]
|
|
8009136: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800913a: 78fa ldrb r2, [r7, #3]
|
|
800913c: 4611 mov r1, r2
|
|
800913e: 4618 mov r0, r3
|
|
8009140: f7fe fd8a bl 8007c58 <USBD_LL_IsoINIncomplete>
|
|
}
|
|
8009144: bf00 nop
|
|
8009146: 3708 adds r7, #8
|
|
8009148: 46bd mov sp, r7
|
|
800914a: bd80 pop {r7, pc}
|
|
|
|
0800914c <HAL_PCD_ConnectCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800914c: b580 push {r7, lr}
|
|
800914e: b082 sub sp, #8
|
|
8009150: af00 add r7, sp, #0
|
|
8009152: 6078 str r0, [r7, #4]
|
|
USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
|
|
8009154: 687b ldr r3, [r7, #4]
|
|
8009156: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800915a: 4618 mov r0, r3
|
|
800915c: f7fe fde0 bl 8007d20 <USBD_LL_DevConnected>
|
|
}
|
|
8009160: bf00 nop
|
|
8009162: 3708 adds r7, #8
|
|
8009164: 46bd mov sp, r7
|
|
8009166: bd80 pop {r7, pc}
|
|
|
|
08009168 <HAL_PCD_DisconnectCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8009168: b580 push {r7, lr}
|
|
800916a: b082 sub sp, #8
|
|
800916c: af00 add r7, sp, #0
|
|
800916e: 6078 str r0, [r7, #4]
|
|
USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
|
|
8009170: 687b ldr r3, [r7, #4]
|
|
8009172: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
8009176: 4618 mov r0, r3
|
|
8009178: f7fe fddd bl 8007d36 <USBD_LL_DevDisconnected>
|
|
}
|
|
800917c: bf00 nop
|
|
800917e: 3708 adds r7, #8
|
|
8009180: 46bd mov sp, r7
|
|
8009182: bd80 pop {r7, pc}
|
|
|
|
08009184 <USBD_LL_Init>:
|
|
* @brief Initializes the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8009184: b580 push {r7, lr}
|
|
8009186: b082 sub sp, #8
|
|
8009188: af00 add r7, sp, #0
|
|
800918a: 6078 str r0, [r7, #4]
|
|
/* Init USB Ip. */
|
|
if (pdev->id == DEVICE_FS) {
|
|
800918c: 687b ldr r3, [r7, #4]
|
|
800918e: 781b ldrb r3, [r3, #0]
|
|
8009190: 2b00 cmp r3, #0
|
|
8009192: d13c bne.n 800920e <USBD_LL_Init+0x8a>
|
|
/* Link the driver to the stack. */
|
|
hpcd_USB_OTG_FS.pData = pdev;
|
|
8009194: 4a20 ldr r2, [pc, #128] @ (8009218 <USBD_LL_Init+0x94>)
|
|
8009196: 687b ldr r3, [r7, #4]
|
|
8009198: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0
|
|
pdev->pData = &hpcd_USB_OTG_FS;
|
|
800919c: 687b ldr r3, [r7, #4]
|
|
800919e: 4a1e ldr r2, [pc, #120] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091a0: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8
|
|
|
|
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
|
|
80091a4: 4b1c ldr r3, [pc, #112] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091a6: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
|
|
80091aa: 601a str r2, [r3, #0]
|
|
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
|
|
80091ac: 4b1a ldr r3, [pc, #104] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091ae: 2206 movs r2, #6
|
|
80091b0: 711a strb r2, [r3, #4]
|
|
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
|
|
80091b2: 4b19 ldr r3, [pc, #100] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091b4: 2202 movs r2, #2
|
|
80091b6: 71da strb r2, [r3, #7]
|
|
hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
|
|
80091b8: 4b17 ldr r3, [pc, #92] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091ba: 2200 movs r2, #0
|
|
80091bc: 719a strb r2, [r3, #6]
|
|
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
|
|
80091be: 4b16 ldr r3, [pc, #88] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091c0: 2202 movs r2, #2
|
|
80091c2: 725a strb r2, [r3, #9]
|
|
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
|
|
80091c4: 4b14 ldr r3, [pc, #80] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091c6: 2200 movs r2, #0
|
|
80091c8: 729a strb r2, [r3, #10]
|
|
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
|
|
80091ca: 4b13 ldr r3, [pc, #76] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091cc: 2200 movs r2, #0
|
|
80091ce: 72da strb r2, [r3, #11]
|
|
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
|
|
80091d0: 4b11 ldr r3, [pc, #68] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091d2: 2200 movs r2, #0
|
|
80091d4: 731a strb r2, [r3, #12]
|
|
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
|
|
80091d6: 4b10 ldr r3, [pc, #64] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091d8: 2200 movs r2, #0
|
|
80091da: 739a strb r2, [r3, #14]
|
|
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
|
|
80091dc: 4b0e ldr r3, [pc, #56] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091de: 2200 movs r2, #0
|
|
80091e0: 73da strb r2, [r3, #15]
|
|
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
|
|
80091e2: 480d ldr r0, [pc, #52] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091e4: f7f8 fe6c bl 8001ec0 <HAL_PCD_Init>
|
|
80091e8: 4603 mov r3, r0
|
|
80091ea: 2b00 cmp r3, #0
|
|
80091ec: d001 beq.n 80091f2 <USBD_LL_Init+0x6e>
|
|
{
|
|
Error_Handler( );
|
|
80091ee: f7f7 fe67 bl 8000ec0 <Error_Handler>
|
|
HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback);
|
|
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback);
|
|
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
|
|
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
|
|
80091f2: 2180 movs r1, #128 @ 0x80
|
|
80091f4: 4808 ldr r0, [pc, #32] @ (8009218 <USBD_LL_Init+0x94>)
|
|
80091f6: f7fa f8b4 bl 8003362 <HAL_PCDEx_SetRxFiFo>
|
|
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
|
|
80091fa: 2240 movs r2, #64 @ 0x40
|
|
80091fc: 2100 movs r1, #0
|
|
80091fe: 4806 ldr r0, [pc, #24] @ (8009218 <USBD_LL_Init+0x94>)
|
|
8009200: f7fa f868 bl 80032d4 <HAL_PCDEx_SetTxFiFo>
|
|
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
|
|
8009204: 2280 movs r2, #128 @ 0x80
|
|
8009206: 2101 movs r1, #1
|
|
8009208: 4803 ldr r0, [pc, #12] @ (8009218 <USBD_LL_Init+0x94>)
|
|
800920a: f7fa f863 bl 80032d4 <HAL_PCDEx_SetTxFiFo>
|
|
}
|
|
return USBD_OK;
|
|
800920e: 2300 movs r3, #0
|
|
}
|
|
8009210: 4618 mov r0, r3
|
|
8009212: 3708 adds r7, #8
|
|
8009214: 46bd mov sp, r7
|
|
8009216: bd80 pop {r7, pc}
|
|
8009218: 200009e4 .word 0x200009e4
|
|
|
|
0800921c <USBD_LL_Start>:
|
|
* @brief Starts the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
800921c: b580 push {r7, lr}
|
|
800921e: b084 sub sp, #16
|
|
8009220: af00 add r7, sp, #0
|
|
8009222: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8009224: 2300 movs r3, #0
|
|
8009226: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009228: 2300 movs r3, #0
|
|
800922a: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_Start(pdev->pData);
|
|
800922c: 687b ldr r3, [r7, #4]
|
|
800922e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
8009232: 4618 mov r0, r3
|
|
8009234: f7f8 ff5a bl 80020ec <HAL_PCD_Start>
|
|
8009238: 4603 mov r3, r0
|
|
800923a: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800923c: 7bfb ldrb r3, [r7, #15]
|
|
800923e: 4618 mov r0, r3
|
|
8009240: f000 f97e bl 8009540 <USBD_Get_USB_Status>
|
|
8009244: 4603 mov r3, r0
|
|
8009246: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8009248: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800924a: 4618 mov r0, r3
|
|
800924c: 3710 adds r7, #16
|
|
800924e: 46bd mov sp, r7
|
|
8009250: bd80 pop {r7, pc}
|
|
|
|
08009252 <USBD_LL_OpenEP>:
|
|
* @param ep_type: Endpoint type
|
|
* @param ep_mps: Endpoint max packet size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
|
|
{
|
|
8009252: b580 push {r7, lr}
|
|
8009254: b084 sub sp, #16
|
|
8009256: af00 add r7, sp, #0
|
|
8009258: 6078 str r0, [r7, #4]
|
|
800925a: 4608 mov r0, r1
|
|
800925c: 4611 mov r1, r2
|
|
800925e: 461a mov r2, r3
|
|
8009260: 4603 mov r3, r0
|
|
8009262: 70fb strb r3, [r7, #3]
|
|
8009264: 460b mov r3, r1
|
|
8009266: 70bb strb r3, [r7, #2]
|
|
8009268: 4613 mov r3, r2
|
|
800926a: 803b strh r3, [r7, #0]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800926c: 2300 movs r3, #0
|
|
800926e: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009270: 2300 movs r3, #0
|
|
8009272: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
|
|
8009274: 687b ldr r3, [r7, #4]
|
|
8009276: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
800927a: 78bb ldrb r3, [r7, #2]
|
|
800927c: 883a ldrh r2, [r7, #0]
|
|
800927e: 78f9 ldrb r1, [r7, #3]
|
|
8009280: f7f9 fc5b bl 8002b3a <HAL_PCD_EP_Open>
|
|
8009284: 4603 mov r3, r0
|
|
8009286: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009288: 7bfb ldrb r3, [r7, #15]
|
|
800928a: 4618 mov r0, r3
|
|
800928c: f000 f958 bl 8009540 <USBD_Get_USB_Status>
|
|
8009290: 4603 mov r3, r0
|
|
8009292: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8009294: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8009296: 4618 mov r0, r3
|
|
8009298: 3710 adds r7, #16
|
|
800929a: 46bd mov sp, r7
|
|
800929c: bd80 pop {r7, pc}
|
|
|
|
0800929e <USBD_LL_CloseEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
800929e: b580 push {r7, lr}
|
|
80092a0: b084 sub sp, #16
|
|
80092a2: af00 add r7, sp, #0
|
|
80092a4: 6078 str r0, [r7, #4]
|
|
80092a6: 460b mov r3, r1
|
|
80092a8: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80092aa: 2300 movs r3, #0
|
|
80092ac: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80092ae: 2300 movs r3, #0
|
|
80092b0: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
|
|
80092b2: 687b ldr r3, [r7, #4]
|
|
80092b4: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
80092b8: 78fa ldrb r2, [r7, #3]
|
|
80092ba: 4611 mov r1, r2
|
|
80092bc: 4618 mov r0, r3
|
|
80092be: f7f9 fca6 bl 8002c0e <HAL_PCD_EP_Close>
|
|
80092c2: 4603 mov r3, r0
|
|
80092c4: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80092c6: 7bfb ldrb r3, [r7, #15]
|
|
80092c8: 4618 mov r0, r3
|
|
80092ca: f000 f939 bl 8009540 <USBD_Get_USB_Status>
|
|
80092ce: 4603 mov r3, r0
|
|
80092d0: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
80092d2: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
80092d4: 4618 mov r0, r3
|
|
80092d6: 3710 adds r7, #16
|
|
80092d8: 46bd mov sp, r7
|
|
80092da: bd80 pop {r7, pc}
|
|
|
|
080092dc <USBD_LL_StallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
80092dc: b580 push {r7, lr}
|
|
80092de: b084 sub sp, #16
|
|
80092e0: af00 add r7, sp, #0
|
|
80092e2: 6078 str r0, [r7, #4]
|
|
80092e4: 460b mov r3, r1
|
|
80092e6: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80092e8: 2300 movs r3, #0
|
|
80092ea: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80092ec: 2300 movs r3, #0
|
|
80092ee: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
|
|
80092f0: 687b ldr r3, [r7, #4]
|
|
80092f2: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
80092f6: 78fa ldrb r2, [r7, #3]
|
|
80092f8: 4611 mov r1, r2
|
|
80092fa: 4618 mov r0, r3
|
|
80092fc: f7f9 fd46 bl 8002d8c <HAL_PCD_EP_SetStall>
|
|
8009300: 4603 mov r3, r0
|
|
8009302: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009304: 7bfb ldrb r3, [r7, #15]
|
|
8009306: 4618 mov r0, r3
|
|
8009308: f000 f91a bl 8009540 <USBD_Get_USB_Status>
|
|
800930c: 4603 mov r3, r0
|
|
800930e: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8009310: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8009312: 4618 mov r0, r3
|
|
8009314: 3710 adds r7, #16
|
|
8009316: 46bd mov sp, r7
|
|
8009318: bd80 pop {r7, pc}
|
|
|
|
0800931a <USBD_LL_ClearStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
800931a: b580 push {r7, lr}
|
|
800931c: b084 sub sp, #16
|
|
800931e: af00 add r7, sp, #0
|
|
8009320: 6078 str r0, [r7, #4]
|
|
8009322: 460b mov r3, r1
|
|
8009324: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8009326: 2300 movs r3, #0
|
|
8009328: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800932a: 2300 movs r3, #0
|
|
800932c: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
|
|
800932e: 687b ldr r3, [r7, #4]
|
|
8009330: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
8009334: 78fa ldrb r2, [r7, #3]
|
|
8009336: 4611 mov r1, r2
|
|
8009338: 4618 mov r0, r3
|
|
800933a: f7f9 fd8a bl 8002e52 <HAL_PCD_EP_ClrStall>
|
|
800933e: 4603 mov r3, r0
|
|
8009340: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8009342: 7bfb ldrb r3, [r7, #15]
|
|
8009344: 4618 mov r0, r3
|
|
8009346: f000 f8fb bl 8009540 <USBD_Get_USB_Status>
|
|
800934a: 4603 mov r3, r0
|
|
800934c: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800934e: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8009350: 4618 mov r0, r3
|
|
8009352: 3710 adds r7, #16
|
|
8009354: 46bd mov sp, r7
|
|
8009356: bd80 pop {r7, pc}
|
|
|
|
08009358 <USBD_LL_IsStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval Stall (1: Yes, 0: No)
|
|
*/
|
|
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
8009358: b480 push {r7}
|
|
800935a: b085 sub sp, #20
|
|
800935c: af00 add r7, sp, #0
|
|
800935e: 6078 str r0, [r7, #4]
|
|
8009360: 460b mov r3, r1
|
|
8009362: 70fb strb r3, [r7, #3]
|
|
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
|
|
8009364: 687b ldr r3, [r7, #4]
|
|
8009366: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800936a: 60fb str r3, [r7, #12]
|
|
|
|
if((ep_addr & 0x80) == 0x80)
|
|
800936c: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8009370: 2b00 cmp r3, #0
|
|
8009372: da0b bge.n 800938c <USBD_LL_IsStallEP+0x34>
|
|
{
|
|
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
|
|
8009374: 78fb ldrb r3, [r7, #3]
|
|
8009376: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
800937a: 68f9 ldr r1, [r7, #12]
|
|
800937c: 4613 mov r3, r2
|
|
800937e: 00db lsls r3, r3, #3
|
|
8009380: 4413 add r3, r2
|
|
8009382: 009b lsls r3, r3, #2
|
|
8009384: 440b add r3, r1
|
|
8009386: 3316 adds r3, #22
|
|
8009388: 781b ldrb r3, [r3, #0]
|
|
800938a: e00b b.n 80093a4 <USBD_LL_IsStallEP+0x4c>
|
|
}
|
|
else
|
|
{
|
|
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
|
|
800938c: 78fb ldrb r3, [r7, #3]
|
|
800938e: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
8009392: 68f9 ldr r1, [r7, #12]
|
|
8009394: 4613 mov r3, r2
|
|
8009396: 00db lsls r3, r3, #3
|
|
8009398: 4413 add r3, r2
|
|
800939a: 009b lsls r3, r3, #2
|
|
800939c: 440b add r3, r1
|
|
800939e: f203 2356 addw r3, r3, #598 @ 0x256
|
|
80093a2: 781b ldrb r3, [r3, #0]
|
|
}
|
|
}
|
|
80093a4: 4618 mov r0, r3
|
|
80093a6: 3714 adds r7, #20
|
|
80093a8: 46bd mov sp, r7
|
|
80093aa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80093ae: 4770 bx lr
|
|
|
|
080093b0 <USBD_LL_SetUSBAddress>:
|
|
* @param pdev: Device handle
|
|
* @param dev_addr: Device address
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
|
|
{
|
|
80093b0: b580 push {r7, lr}
|
|
80093b2: b084 sub sp, #16
|
|
80093b4: af00 add r7, sp, #0
|
|
80093b6: 6078 str r0, [r7, #4]
|
|
80093b8: 460b mov r3, r1
|
|
80093ba: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80093bc: 2300 movs r3, #0
|
|
80093be: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80093c0: 2300 movs r3, #0
|
|
80093c2: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
|
|
80093c4: 687b ldr r3, [r7, #4]
|
|
80093c6: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
80093ca: 78fa ldrb r2, [r7, #3]
|
|
80093cc: 4611 mov r1, r2
|
|
80093ce: 4618 mov r0, r3
|
|
80093d0: f7f9 fb8f bl 8002af2 <HAL_PCD_SetAddress>
|
|
80093d4: 4603 mov r3, r0
|
|
80093d6: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80093d8: 7bfb ldrb r3, [r7, #15]
|
|
80093da: 4618 mov r0, r3
|
|
80093dc: f000 f8b0 bl 8009540 <USBD_Get_USB_Status>
|
|
80093e0: 4603 mov r3, r0
|
|
80093e2: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
80093e4: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
80093e6: 4618 mov r0, r3
|
|
80093e8: 3710 adds r7, #16
|
|
80093ea: 46bd mov sp, r7
|
|
80093ec: bd80 pop {r7, pc}
|
|
|
|
080093ee <USBD_LL_Transmit>:
|
|
* @param pbuf: Pointer to data to be sent
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
|
|
{
|
|
80093ee: b580 push {r7, lr}
|
|
80093f0: b086 sub sp, #24
|
|
80093f2: af00 add r7, sp, #0
|
|
80093f4: 60f8 str r0, [r7, #12]
|
|
80093f6: 607a str r2, [r7, #4]
|
|
80093f8: 603b str r3, [r7, #0]
|
|
80093fa: 460b mov r3, r1
|
|
80093fc: 72fb strb r3, [r7, #11]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80093fe: 2300 movs r3, #0
|
|
8009400: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009402: 2300 movs r3, #0
|
|
8009404: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
|
|
8009406: 68fb ldr r3, [r7, #12]
|
|
8009408: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
800940c: 7af9 ldrb r1, [r7, #11]
|
|
800940e: 683b ldr r3, [r7, #0]
|
|
8009410: 687a ldr r2, [r7, #4]
|
|
8009412: f7f9 fc81 bl 8002d18 <HAL_PCD_EP_Transmit>
|
|
8009416: 4603 mov r3, r0
|
|
8009418: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800941a: 7dfb ldrb r3, [r7, #23]
|
|
800941c: 4618 mov r0, r3
|
|
800941e: f000 f88f bl 8009540 <USBD_Get_USB_Status>
|
|
8009422: 4603 mov r3, r0
|
|
8009424: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
8009426: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
8009428: 4618 mov r0, r3
|
|
800942a: 3718 adds r7, #24
|
|
800942c: 46bd mov sp, r7
|
|
800942e: bd80 pop {r7, pc}
|
|
|
|
08009430 <USBD_LL_PrepareReceive>:
|
|
* @param pbuf: Pointer to data to be received
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
|
|
{
|
|
8009430: b580 push {r7, lr}
|
|
8009432: b086 sub sp, #24
|
|
8009434: af00 add r7, sp, #0
|
|
8009436: 60f8 str r0, [r7, #12]
|
|
8009438: 607a str r2, [r7, #4]
|
|
800943a: 603b str r3, [r7, #0]
|
|
800943c: 460b mov r3, r1
|
|
800943e: 72fb strb r3, [r7, #11]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8009440: 2300 movs r3, #0
|
|
8009442: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8009444: 2300 movs r3, #0
|
|
8009446: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
|
|
8009448: 68fb ldr r3, [r7, #12]
|
|
800944a: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
800944e: 7af9 ldrb r1, [r7, #11]
|
|
8009450: 683b ldr r3, [r7, #0]
|
|
8009452: 687a ldr r2, [r7, #4]
|
|
8009454: f7f9 fc25 bl 8002ca2 <HAL_PCD_EP_Receive>
|
|
8009458: 4603 mov r3, r0
|
|
800945a: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800945c: 7dfb ldrb r3, [r7, #23]
|
|
800945e: 4618 mov r0, r3
|
|
8009460: f000 f86e bl 8009540 <USBD_Get_USB_Status>
|
|
8009464: 4603 mov r3, r0
|
|
8009466: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
8009468: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
800946a: 4618 mov r0, r3
|
|
800946c: 3718 adds r7, #24
|
|
800946e: 46bd mov sp, r7
|
|
8009470: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08009474 <HAL_PCDEx_LPM_Callback>:
|
|
* @param hpcd: PCD handle
|
|
* @param msg: LPM message
|
|
* @retval None
|
|
*/
|
|
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
|
|
{
|
|
8009474: b580 push {r7, lr}
|
|
8009476: b082 sub sp, #8
|
|
8009478: af00 add r7, sp, #0
|
|
800947a: 6078 str r0, [r7, #4]
|
|
800947c: 460b mov r3, r1
|
|
800947e: 70fb strb r3, [r7, #3]
|
|
switch (msg)
|
|
8009480: 78fb ldrb r3, [r7, #3]
|
|
8009482: 2b00 cmp r3, #0
|
|
8009484: d002 beq.n 800948c <HAL_PCDEx_LPM_Callback+0x18>
|
|
8009486: 2b01 cmp r3, #1
|
|
8009488: d01f beq.n 80094ca <HAL_PCDEx_LPM_Callback+0x56>
|
|
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
800948a: e03b b.n 8009504 <HAL_PCDEx_LPM_Callback+0x90>
|
|
if (hpcd->Init.low_power_enable)
|
|
800948c: 687b ldr r3, [r7, #4]
|
|
800948e: 7adb ldrb r3, [r3, #11]
|
|
8009490: 2b00 cmp r3, #0
|
|
8009492: d007 beq.n 80094a4 <HAL_PCDEx_LPM_Callback+0x30>
|
|
SystemClock_Config();
|
|
8009494: f7f7 f8d0 bl 8000638 <SystemClock_Config>
|
|
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
8009498: 4b1c ldr r3, [pc, #112] @ (800950c <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800949a: 691b ldr r3, [r3, #16]
|
|
800949c: 4a1b ldr r2, [pc, #108] @ (800950c <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800949e: f023 0306 bic.w r3, r3, #6
|
|
80094a2: 6113 str r3, [r2, #16]
|
|
__HAL_PCD_UNGATE_PHYCLOCK(hpcd);
|
|
80094a4: 687b ldr r3, [r7, #4]
|
|
80094a6: 681b ldr r3, [r3, #0]
|
|
80094a8: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80094ac: 681b ldr r3, [r3, #0]
|
|
80094ae: 687a ldr r2, [r7, #4]
|
|
80094b0: 6812 ldr r2, [r2, #0]
|
|
80094b2: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
80094b6: f023 0301 bic.w r3, r3, #1
|
|
80094ba: 6013 str r3, [r2, #0]
|
|
USBD_LL_Resume(hpcd->pData);
|
|
80094bc: 687b ldr r3, [r7, #4]
|
|
80094be: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
80094c2: 4618 mov r0, r3
|
|
80094c4: f7fe fb90 bl 8007be8 <USBD_LL_Resume>
|
|
break;
|
|
80094c8: e01c b.n 8009504 <HAL_PCDEx_LPM_Callback+0x90>
|
|
__HAL_PCD_GATE_PHYCLOCK(hpcd);
|
|
80094ca: 687b ldr r3, [r7, #4]
|
|
80094cc: 681b ldr r3, [r3, #0]
|
|
80094ce: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80094d2: 681b ldr r3, [r3, #0]
|
|
80094d4: 687a ldr r2, [r7, #4]
|
|
80094d6: 6812 ldr r2, [r2, #0]
|
|
80094d8: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
80094dc: f043 0301 orr.w r3, r3, #1
|
|
80094e0: 6013 str r3, [r2, #0]
|
|
USBD_LL_Suspend(hpcd->pData);
|
|
80094e2: 687b ldr r3, [r7, #4]
|
|
80094e4: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
80094e8: 4618 mov r0, r3
|
|
80094ea: f7fe fb61 bl 8007bb0 <USBD_LL_Suspend>
|
|
if (hpcd->Init.low_power_enable)
|
|
80094ee: 687b ldr r3, [r7, #4]
|
|
80094f0: 7adb ldrb r3, [r3, #11]
|
|
80094f2: 2b00 cmp r3, #0
|
|
80094f4: d005 beq.n 8009502 <HAL_PCDEx_LPM_Callback+0x8e>
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
80094f6: 4b05 ldr r3, [pc, #20] @ (800950c <HAL_PCDEx_LPM_Callback+0x98>)
|
|
80094f8: 691b ldr r3, [r3, #16]
|
|
80094fa: 4a04 ldr r2, [pc, #16] @ (800950c <HAL_PCDEx_LPM_Callback+0x98>)
|
|
80094fc: f043 0306 orr.w r3, r3, #6
|
|
8009500: 6113 str r3, [r2, #16]
|
|
break;
|
|
8009502: bf00 nop
|
|
}
|
|
8009504: bf00 nop
|
|
8009506: 3708 adds r7, #8
|
|
8009508: 46bd mov sp, r7
|
|
800950a: bd80 pop {r7, pc}
|
|
800950c: e000ed00 .word 0xe000ed00
|
|
|
|
08009510 <USBD_static_malloc>:
|
|
* @brief Static single allocation.
|
|
* @param size: Size of allocated memory
|
|
* @retval None
|
|
*/
|
|
void *USBD_static_malloc(uint32_t size)
|
|
{
|
|
8009510: b480 push {r7}
|
|
8009512: b083 sub sp, #12
|
|
8009514: af00 add r7, sp, #0
|
|
8009516: 6078 str r0, [r7, #4]
|
|
static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */
|
|
return mem;
|
|
8009518: 4b03 ldr r3, [pc, #12] @ (8009528 <USBD_static_malloc+0x18>)
|
|
}
|
|
800951a: 4618 mov r0, r3
|
|
800951c: 370c adds r7, #12
|
|
800951e: 46bd mov sp, r7
|
|
8009520: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009524: 4770 bx lr
|
|
8009526: bf00 nop
|
|
8009528: 20000ec8 .word 0x20000ec8
|
|
|
|
0800952c <USBD_static_free>:
|
|
* @brief Dummy memory free
|
|
* @param p: Pointer to allocated memory address
|
|
* @retval None
|
|
*/
|
|
void USBD_static_free(void *p)
|
|
{
|
|
800952c: b480 push {r7}
|
|
800952e: b083 sub sp, #12
|
|
8009530: af00 add r7, sp, #0
|
|
8009532: 6078 str r0, [r7, #4]
|
|
|
|
}
|
|
8009534: bf00 nop
|
|
8009536: 370c adds r7, #12
|
|
8009538: 46bd mov sp, r7
|
|
800953a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800953e: 4770 bx lr
|
|
|
|
08009540 <USBD_Get_USB_Status>:
|
|
* @brief Returns the USB status depending on the HAL status:
|
|
* @param hal_status: HAL status
|
|
* @retval USB status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
|
|
{
|
|
8009540: b480 push {r7}
|
|
8009542: b085 sub sp, #20
|
|
8009544: af00 add r7, sp, #0
|
|
8009546: 4603 mov r3, r0
|
|
8009548: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800954a: 2300 movs r3, #0
|
|
800954c: 73fb strb r3, [r7, #15]
|
|
|
|
switch (hal_status)
|
|
800954e: 79fb ldrb r3, [r7, #7]
|
|
8009550: 2b03 cmp r3, #3
|
|
8009552: d817 bhi.n 8009584 <USBD_Get_USB_Status+0x44>
|
|
8009554: a201 add r2, pc, #4 @ (adr r2, 800955c <USBD_Get_USB_Status+0x1c>)
|
|
8009556: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800955a: bf00 nop
|
|
800955c: 0800956d .word 0x0800956d
|
|
8009560: 08009573 .word 0x08009573
|
|
8009564: 08009579 .word 0x08009579
|
|
8009568: 0800957f .word 0x0800957f
|
|
{
|
|
case HAL_OK :
|
|
usb_status = USBD_OK;
|
|
800956c: 2300 movs r3, #0
|
|
800956e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009570: e00b b.n 800958a <USBD_Get_USB_Status+0x4a>
|
|
case HAL_ERROR :
|
|
usb_status = USBD_FAIL;
|
|
8009572: 2303 movs r3, #3
|
|
8009574: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009576: e008 b.n 800958a <USBD_Get_USB_Status+0x4a>
|
|
case HAL_BUSY :
|
|
usb_status = USBD_BUSY;
|
|
8009578: 2301 movs r3, #1
|
|
800957a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800957c: e005 b.n 800958a <USBD_Get_USB_Status+0x4a>
|
|
case HAL_TIMEOUT :
|
|
usb_status = USBD_FAIL;
|
|
800957e: 2303 movs r3, #3
|
|
8009580: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009582: e002 b.n 800958a <USBD_Get_USB_Status+0x4a>
|
|
default :
|
|
usb_status = USBD_FAIL;
|
|
8009584: 2303 movs r3, #3
|
|
8009586: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009588: bf00 nop
|
|
}
|
|
return usb_status;
|
|
800958a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800958c: 4618 mov r0, r3
|
|
800958e: 3714 adds r7, #20
|
|
8009590: 46bd mov sp, r7
|
|
8009592: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009596: 4770 bx lr
|
|
|
|
08009598 <memset>:
|
|
8009598: 4402 add r2, r0
|
|
800959a: 4603 mov r3, r0
|
|
800959c: 4293 cmp r3, r2
|
|
800959e: d100 bne.n 80095a2 <memset+0xa>
|
|
80095a0: 4770 bx lr
|
|
80095a2: f803 1b01 strb.w r1, [r3], #1
|
|
80095a6: e7f9 b.n 800959c <memset+0x4>
|
|
|
|
080095a8 <__libc_init_array>:
|
|
80095a8: b570 push {r4, r5, r6, lr}
|
|
80095aa: 4d0d ldr r5, [pc, #52] @ (80095e0 <__libc_init_array+0x38>)
|
|
80095ac: 4c0d ldr r4, [pc, #52] @ (80095e4 <__libc_init_array+0x3c>)
|
|
80095ae: 1b64 subs r4, r4, r5
|
|
80095b0: 10a4 asrs r4, r4, #2
|
|
80095b2: 2600 movs r6, #0
|
|
80095b4: 42a6 cmp r6, r4
|
|
80095b6: d109 bne.n 80095cc <__libc_init_array+0x24>
|
|
80095b8: 4d0b ldr r5, [pc, #44] @ (80095e8 <__libc_init_array+0x40>)
|
|
80095ba: 4c0c ldr r4, [pc, #48] @ (80095ec <__libc_init_array+0x44>)
|
|
80095bc: f000 f818 bl 80095f0 <_init>
|
|
80095c0: 1b64 subs r4, r4, r5
|
|
80095c2: 10a4 asrs r4, r4, #2
|
|
80095c4: 2600 movs r6, #0
|
|
80095c6: 42a6 cmp r6, r4
|
|
80095c8: d105 bne.n 80095d6 <__libc_init_array+0x2e>
|
|
80095ca: bd70 pop {r4, r5, r6, pc}
|
|
80095cc: f855 3b04 ldr.w r3, [r5], #4
|
|
80095d0: 4798 blx r3
|
|
80095d2: 3601 adds r6, #1
|
|
80095d4: e7ee b.n 80095b4 <__libc_init_array+0xc>
|
|
80095d6: f855 3b04 ldr.w r3, [r5], #4
|
|
80095da: 4798 blx r3
|
|
80095dc: 3601 adds r6, #1
|
|
80095de: e7f2 b.n 80095c6 <__libc_init_array+0x1e>
|
|
80095e0: 08009664 .word 0x08009664
|
|
80095e4: 08009664 .word 0x08009664
|
|
80095e8: 08009664 .word 0x08009664
|
|
80095ec: 08009668 .word 0x08009668
|
|
|
|
080095f0 <_init>:
|
|
80095f0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80095f2: bf00 nop
|
|
80095f4: bcf8 pop {r3, r4, r5, r6, r7}
|
|
80095f6: bc08 pop {r3}
|
|
80095f8: 469e mov lr, r3
|
|
80095fa: 4770 bx lr
|
|
|
|
080095fc <_fini>:
|
|
80095fc: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80095fe: bf00 nop
|
|
8009600: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8009602: bc08 pop {r3}
|
|
8009604: 469e mov lr, r3
|
|
8009606: 4770 bx lr
|