29151 lines
1.0 MiB
29151 lines
1.0 MiB
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modularkbd.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000001c4 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 0000ad08 080001c4 080001c4 000011c4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 0000005c 0800aecc 0800aecc 0000becc 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 0800af28 0800af28 0000c1a0 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 0800af28 0800af28 0000bf28 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 0800af30 0800af30 0000c1a0 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 0800af30 0800af30 0000bf30 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 0800af34 0800af34 0000bf34 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 000001a0 20000000 0800af38 0000c000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 000015bc 200001a0 0800b0d8 0000c1a0 2**2
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ALLOC
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10 ._user_heap_stack 00000604 2000175c 0800b0d8 0000c75c 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0000c1a0 2**0
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CONTENTS, READONLY
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12 .debug_info 0001b5ee 00000000 00000000 0000c1d0 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00004090 00000000 00000000 000277be 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 000017b0 00000000 00000000 0002b850 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 00001266 00000000 00000000 0002d000 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 0002607b 00000000 00000000 0002e266 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 0001e8b0 00000000 00000000 000542e1 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000d8013 00000000 00000000 00072b91 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 0014aba4 2**0
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CONTENTS, READONLY
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20 .debug_frame 000063a4 00000000 00000000 0014abe8 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000062 00000000 00000000 00150f8c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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080001c4 <__do_global_dtors_aux>:
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80001c4: b510 push {r4, lr}
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80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>)
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80001c8: 7823 ldrb r3, [r4, #0]
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80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16>
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80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>)
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80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12>
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80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>)
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80001d2: f3af 8000 nop.w
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80001d6: 2301 movs r3, #1
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80001d8: 7023 strb r3, [r4, #0]
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80001da: bd10 pop {r4, pc}
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80001dc: 200001a0 .word 0x200001a0
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80001e0: 00000000 .word 0x00000000
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80001e4: 0800aeb4 .word 0x0800aeb4
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080001e8 <frame_dummy>:
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80001e8: b508 push {r3, lr}
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80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 <frame_dummy+0x10>)
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80001ec: b11b cbz r3, 80001f6 <frame_dummy+0xe>
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80001ee: 4903 ldr r1, [pc, #12] @ (80001fc <frame_dummy+0x14>)
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80001f0: 4803 ldr r0, [pc, #12] @ (8000200 <frame_dummy+0x18>)
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80001f2: f3af 8000 nop.w
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80001f6: bd08 pop {r3, pc}
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80001f8: 00000000 .word 0x00000000
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80001fc: 200001a4 .word 0x200001a4
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8000200: 0800aeb4 .word 0x0800aeb4
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08000204 <__aeabi_uldivmod>:
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8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18>
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8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18>
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8000208: 2900 cmp r1, #0
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800020a: bf08 it eq
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800020c: 2800 cmpeq r0, #0
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800020e: bf1c itt ne
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8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
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8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
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8000218: f000 b988 b.w 800052c <__aeabi_idiv0>
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800021c: f1ad 0c08 sub.w ip, sp, #8
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8000220: e96d ce04 strd ip, lr, [sp, #-16]!
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8000224: f000 f806 bl 8000234 <__udivmoddi4>
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8000228: f8dd e004 ldr.w lr, [sp, #4]
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800022c: e9dd 2302 ldrd r2, r3, [sp, #8]
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8000230: b004 add sp, #16
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8000232: 4770 bx lr
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08000234 <__udivmoddi4>:
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8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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8000238: 9d08 ldr r5, [sp, #32]
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800023a: 468e mov lr, r1
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800023c: 4604 mov r4, r0
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800023e: 4688 mov r8, r1
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8000240: 2b00 cmp r3, #0
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8000242: d14a bne.n 80002da <__udivmoddi4+0xa6>
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8000244: 428a cmp r2, r1
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8000246: 4617 mov r7, r2
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8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc>
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800024a: fab2 f682 clz r6, r2
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800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30>
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8000250: f1c6 0320 rsb r3, r6, #32
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8000254: fa01 f806 lsl.w r8, r1, r6
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8000258: fa20 f303 lsr.w r3, r0, r3
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800025c: 40b7 lsls r7, r6
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800025e: ea43 0808 orr.w r8, r3, r8
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8000262: 40b4 lsls r4, r6
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8000264: ea4f 4e17 mov.w lr, r7, lsr #16
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8000268: fa1f fc87 uxth.w ip, r7
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800026c: fbb8 f1fe udiv r1, r8, lr
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8000270: 0c23 lsrs r3, r4, #16
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8000272: fb0e 8811 mls r8, lr, r1, r8
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8000276: ea43 4308 orr.w r3, r3, r8, lsl #16
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800027a: fb01 f20c mul.w r2, r1, ip
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800027e: 429a cmp r2, r3
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8000280: d909 bls.n 8000296 <__udivmoddi4+0x62>
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8000282: 18fb adds r3, r7, r3
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8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
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8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c>
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800028c: 429a cmp r2, r3
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800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c>
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8000292: 3902 subs r1, #2
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8000294: 443b add r3, r7
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8000296: 1a9a subs r2, r3, r2
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8000298: b2a3 uxth r3, r4
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800029a: fbb2 f0fe udiv r0, r2, lr
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800029e: fb0e 2210 mls r2, lr, r0, r2
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80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16
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80002a6: fb00 fc0c mul.w ip, r0, ip
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80002aa: 459c cmp ip, r3
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80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e>
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80002ae: 18fb adds r3, r7, r3
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80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
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80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230>
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80002b8: 459c cmp ip, r3
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80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230>
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80002be: 443b add r3, r7
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80002c0: 3802 subs r0, #2
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80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16
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80002c6: eba3 030c sub.w r3, r3, ip
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80002ca: 2100 movs r1, #0
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80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2>
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80002ce: 40f3 lsrs r3, r6
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80002d0: 2200 movs r2, #0
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80002d2: e9c5 3200 strd r3, r2, [r5]
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80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002da: 428b cmp r3, r1
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80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6>
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80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0>
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80002e0: e9c5 0100 strd r0, r1, [r5]
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80002e4: 2100 movs r1, #0
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80002e6: 4608 mov r0, r1
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80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2>
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80002ea: fab3 f183 clz r1, r3
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80002ee: 2900 cmp r1, #0
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80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c>
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80002f2: 4573 cmp r3, lr
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80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8>
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80002f6: 4282 cmp r2, r0
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80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2>
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80002fc: 1a84 subs r4, r0, r2
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80002fe: eb6e 0203 sbc.w r2, lr, r3
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8000302: 2001 movs r0, #1
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8000304: 4690 mov r8, r2
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8000306: 2d00 cmp r5, #0
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8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2>
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800030a: e9c5 4800 strd r4, r8, [r5]
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800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2>
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8000310: 2a00 cmp r2, #0
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8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202>
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8000316: fab2 f682 clz r6, r2
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800031a: 2e00 cmp r6, #0
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800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234>
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8000320: 1a8a subs r2, r1, r2
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8000322: 0c03 lsrs r3, r0, #16
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8000324: ea4f 4e17 mov.w lr, r7, lsr #16
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8000328: b280 uxth r0, r0
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800032a: b2bc uxth r4, r7
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800032c: 2101 movs r1, #1
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800032e: fbb2 fcfe udiv ip, r2, lr
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8000332: fb0e 221c mls r2, lr, ip, r2
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8000336: ea43 4302 orr.w r3, r3, r2, lsl #16
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800033a: fb04 f20c mul.w r2, r4, ip
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800033e: 429a cmp r2, r3
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8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e>
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8000342: 18fb adds r3, r7, r3
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8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
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8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c>
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800034a: 429a cmp r2, r3
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800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc>
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8000350: 46c4 mov ip, r8
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8000352: 1a9b subs r3, r3, r2
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8000354: fbb3 f2fe udiv r2, r3, lr
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8000358: fb0e 3312 mls r3, lr, r2, r3
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800035c: ea40 4303 orr.w r3, r0, r3, lsl #16
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8000360: fb02 f404 mul.w r4, r2, r4
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8000364: 429c cmp r4, r3
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8000366: d907 bls.n 8000378 <__udivmoddi4+0x144>
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8000368: 18fb adds r3, r7, r3
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800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
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800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142>
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8000370: 429c cmp r4, r3
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8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6>
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8000376: 4602 mov r2, r0
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8000378: 1b1b subs r3, r3, r4
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800037a: ea42 400c orr.w r0, r2, ip, lsl #16
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800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98>
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8000380: f1c1 0620 rsb r6, r1, #32
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8000384: 408b lsls r3, r1
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8000386: fa22 f706 lsr.w r7, r2, r6
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800038a: 431f orrs r7, r3
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800038c: fa0e f401 lsl.w r4, lr, r1
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8000390: fa20 f306 lsr.w r3, r0, r6
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8000394: fa2e fe06 lsr.w lr, lr, r6
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8000398: ea4f 4917 mov.w r9, r7, lsr #16
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800039c: 4323 orrs r3, r4
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800039e: fa00 f801 lsl.w r8, r0, r1
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80003a2: fa1f fc87 uxth.w ip, r7
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80003a6: fbbe f0f9 udiv r0, lr, r9
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80003aa: 0c1c lsrs r4, r3, #16
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80003ac: fb09 ee10 mls lr, r9, r0, lr
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80003b0: ea44 440e orr.w r4, r4, lr, lsl #16
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80003b4: fb00 fe0c mul.w lr, r0, ip
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80003b8: 45a6 cmp lr, r4
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80003ba: fa02 f201 lsl.w r2, r2, r1
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80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0>
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80003c0: 193c adds r4, r7, r4
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80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
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80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce>
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80003ca: 45a6 cmp lr, r4
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80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce>
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80003d0: 3802 subs r0, #2
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80003d2: 443c add r4, r7
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80003d4: eba4 040e sub.w r4, r4, lr
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80003d8: fa1f fe83 uxth.w lr, r3
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80003dc: fbb4 f3f9 udiv r3, r4, r9
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80003e0: fb09 4413 mls r4, r9, r3, r4
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80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16
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80003e8: fb03 fc0c mul.w ip, r3, ip
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80003ec: 45a4 cmp ip, r4
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80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce>
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80003f0: 193c adds r4, r7, r4
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80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
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80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca>
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80003fa: 45a4 cmp ip, r4
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80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca>
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80003fe: 3b02 subs r3, #2
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8000400: 443c add r4, r7
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8000402: ea43 4000 orr.w r0, r3, r0, lsl #16
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8000406: eba4 040c sub.w r4, r4, ip
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800040a: fba0 ec02 umull lr, ip, r0, r2
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800040e: 4564 cmp r4, ip
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8000410: 4673 mov r3, lr
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8000412: 46e1 mov r9, ip
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8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8>
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8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4>
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8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe>
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800041a: ebb8 0203 subs.w r2, r8, r3
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800041e: eb64 0409 sbc.w r4, r4, r9
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8000422: fa04 f606 lsl.w r6, r4, r6
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8000426: fa22 f301 lsr.w r3, r2, r1
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800042a: 431e orrs r6, r3
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800042c: 40cc lsrs r4, r1
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800042e: e9c5 6400 strd r6, r4, [r5]
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8000432: 2100 movs r1, #0
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8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2>
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8000436: fbb1 fcf2 udiv ip, r1, r2
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800043a: 0c01 lsrs r1, r0, #16
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800043c: ea41 410e orr.w r1, r1, lr, lsl #16
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8000440: b280 uxth r0, r0
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8000442: ea40 4201 orr.w r2, r0, r1, lsl #16
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8000446: 463b mov r3, r7
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8000448: 4638 mov r0, r7
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800044a: 463c mov r4, r7
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800044c: 46b8 mov r8, r7
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800044e: 46be mov lr, r7
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8000450: 2620 movs r6, #32
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8000452: fbb1 f1f7 udiv r1, r1, r7
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8000456: eba2 0208 sub.w r2, r2, r8
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800045a: ea41 410c orr.w r1, r1, ip, lsl #16
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800045e: e766 b.n 800032e <__udivmoddi4+0xfa>
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8000460: 4601 mov r1, r0
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8000462: e718 b.n 8000296 <__udivmoddi4+0x62>
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8000464: 4610 mov r0, r2
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8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e>
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8000468: f1c6 0220 rsb r2, r6, #32
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800046c: fa2e f302 lsr.w r3, lr, r2
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8000470: 40b7 lsls r7, r6
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8000472: 40b1 lsls r1, r6
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8000474: fa20 f202 lsr.w r2, r0, r2
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8000478: ea4f 4e17 mov.w lr, r7, lsr #16
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800047c: 430a orrs r2, r1
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800047e: fbb3 f8fe udiv r8, r3, lr
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8000482: b2bc uxth r4, r7
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8000484: fb0e 3318 mls r3, lr, r8, r3
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8000488: 0c11 lsrs r1, r2, #16
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800048a: ea41 4103 orr.w r1, r1, r3, lsl #16
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800048e: fb08 f904 mul.w r9, r8, r4
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8000492: 40b0 lsls r0, r6
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8000494: 4589 cmp r9, r1
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8000496: ea4f 4310 mov.w r3, r0, lsr #16
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800049a: b280 uxth r0, r0
|
|
800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8>
|
|
800049e: 1879 adds r1, r7, r1
|
|
80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276>
|
|
80004a6: 4589 cmp r9, r1
|
|
80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6>
|
|
80004aa: eba1 0109 sub.w r1, r1, r9
|
|
80004ae: fbb1 f9fe udiv r9, r1, lr
|
|
80004b2: fb09 f804 mul.w r8, r9, r4
|
|
80004b6: fb0e 1119 mls r1, lr, r9, r1
|
|
80004ba: b292 uxth r2, r2
|
|
80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
80004c0: 4542 cmp r2, r8
|
|
80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4>
|
|
80004c4: 18ba adds r2, r7, r2
|
|
80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222>
|
|
80004cc: 4542 cmp r2, r8
|
|
80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222>
|
|
80004d0: f1a9 0102 sub.w r1, r9, #2
|
|
80004d4: 443a add r2, r7
|
|
80004d6: e7be b.n 8000456 <__udivmoddi4+0x222>
|
|
80004d8: 45f0 cmp r8, lr
|
|
80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4>
|
|
80004dc: ebbe 0302 subs.w r3, lr, r2
|
|
80004e0: eb6c 0c07 sbc.w ip, ip, r7
|
|
80004e4: 3801 subs r0, #1
|
|
80004e6: 46e1 mov r9, ip
|
|
80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4>
|
|
80004ea: eba7 0909 sub.w r9, r7, r9
|
|
80004ee: 4449 add r1, r9
|
|
80004f0: f1a8 0c02 sub.w ip, r8, #2
|
|
80004f4: fbb1 f9fe udiv r9, r1, lr
|
|
80004f8: fb09 f804 mul.w r8, r9, r4
|
|
80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282>
|
|
80004fe: 4673 mov r3, lr
|
|
8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce>
|
|
8000502: 4650 mov r0, sl
|
|
8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0>
|
|
8000506: 4608 mov r0, r1
|
|
8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2>
|
|
800050a: 443b add r3, r7
|
|
800050c: 3a02 subs r2, #2
|
|
800050e: e733 b.n 8000378 <__udivmoddi4+0x144>
|
|
8000510: f1ac 0c02 sub.w ip, ip, #2
|
|
8000514: 443b add r3, r7
|
|
8000516: e71c b.n 8000352 <__udivmoddi4+0x11e>
|
|
8000518: 4649 mov r1, r9
|
|
800051a: e79c b.n 8000456 <__udivmoddi4+0x222>
|
|
800051c: eba1 0109 sub.w r1, r1, r9
|
|
8000520: 46c4 mov ip, r8
|
|
8000522: fbb1 f9fe udiv r9, r1, lr
|
|
8000526: fb09 f804 mul.w r8, r9, r4
|
|
800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282>
|
|
|
|
0800052c <__aeabi_idiv0>:
|
|
800052c: 4770 bx lr
|
|
800052e: bf00 nop
|
|
|
|
08000530 <MX_DMA_Init>:
|
|
|
|
/**
|
|
* Enable DMA controller clock
|
|
*/
|
|
void MX_DMA_Init(void)
|
|
{
|
|
8000530: b580 push {r7, lr}
|
|
8000532: b082 sub sp, #8
|
|
8000534: af00 add r7, sp, #0
|
|
|
|
/* DMA controller clock enable */
|
|
__HAL_RCC_DMA1_CLK_ENABLE();
|
|
8000536: 2300 movs r3, #0
|
|
8000538: 607b str r3, [r7, #4]
|
|
800053a: 4b2f ldr r3, [pc, #188] @ (80005f8 <MX_DMA_Init+0xc8>)
|
|
800053c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800053e: 4a2e ldr r2, [pc, #184] @ (80005f8 <MX_DMA_Init+0xc8>)
|
|
8000540: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8000544: 6313 str r3, [r2, #48] @ 0x30
|
|
8000546: 4b2c ldr r3, [pc, #176] @ (80005f8 <MX_DMA_Init+0xc8>)
|
|
8000548: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800054a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
800054e: 607b str r3, [r7, #4]
|
|
8000550: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_DMA2_CLK_ENABLE();
|
|
8000552: 2300 movs r3, #0
|
|
8000554: 603b str r3, [r7, #0]
|
|
8000556: 4b28 ldr r3, [pc, #160] @ (80005f8 <MX_DMA_Init+0xc8>)
|
|
8000558: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800055a: 4a27 ldr r2, [pc, #156] @ (80005f8 <MX_DMA_Init+0xc8>)
|
|
800055c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8000560: 6313 str r3, [r2, #48] @ 0x30
|
|
8000562: 4b25 ldr r3, [pc, #148] @ (80005f8 <MX_DMA_Init+0xc8>)
|
|
8000564: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000566: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
800056a: 603b str r3, [r7, #0]
|
|
800056c: 683b ldr r3, [r7, #0]
|
|
|
|
/* DMA interrupt init */
|
|
/* DMA1_Stream0_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);
|
|
800056e: 2200 movs r2, #0
|
|
8000570: 2100 movs r1, #0
|
|
8000572: 200b movs r0, #11
|
|
8000574: f001 fd3d bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
|
|
8000578: 200b movs r0, #11
|
|
800057a: f001 fd56 bl 800202a <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream2_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0);
|
|
800057e: 2200 movs r2, #0
|
|
8000580: 2100 movs r1, #0
|
|
8000582: 200d movs r0, #13
|
|
8000584: f001 fd35 bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
|
|
8000588: 200d movs r0, #13
|
|
800058a: f001 fd4e bl 800202a <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream4_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0);
|
|
800058e: 2200 movs r2, #0
|
|
8000590: 2100 movs r1, #0
|
|
8000592: 200f movs r0, #15
|
|
8000594: f001 fd2d bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);
|
|
8000598: 200f movs r0, #15
|
|
800059a: f001 fd46 bl 800202a <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream5_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0);
|
|
800059e: 2200 movs r2, #0
|
|
80005a0: 2100 movs r1, #0
|
|
80005a2: 2010 movs r0, #16
|
|
80005a4: f001 fd25 bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
|
|
80005a8: 2010 movs r0, #16
|
|
80005aa: f001 fd3e bl 800202a <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream6_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0);
|
|
80005ae: 2200 movs r2, #0
|
|
80005b0: 2100 movs r1, #0
|
|
80005b2: 2011 movs r0, #17
|
|
80005b4: f001 fd1d bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn);
|
|
80005b8: 2011 movs r0, #17
|
|
80005ba: f001 fd36 bl 800202a <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream7_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0);
|
|
80005be: 2200 movs r2, #0
|
|
80005c0: 2100 movs r1, #0
|
|
80005c2: 202f movs r0, #47 @ 0x2f
|
|
80005c4: f001 fd15 bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);
|
|
80005c8: 202f movs r0, #47 @ 0x2f
|
|
80005ca: f001 fd2e bl 800202a <HAL_NVIC_EnableIRQ>
|
|
/* DMA2_Stream2_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0);
|
|
80005ce: 2200 movs r2, #0
|
|
80005d0: 2100 movs r1, #0
|
|
80005d2: 203a movs r0, #58 @ 0x3a
|
|
80005d4: f001 fd0d bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
|
|
80005d8: 203a movs r0, #58 @ 0x3a
|
|
80005da: f001 fd26 bl 800202a <HAL_NVIC_EnableIRQ>
|
|
/* DMA2_Stream7_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0);
|
|
80005de: 2200 movs r2, #0
|
|
80005e0: 2100 movs r1, #0
|
|
80005e2: 2046 movs r0, #70 @ 0x46
|
|
80005e4: f001 fd05 bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
|
|
80005e8: 2046 movs r0, #70 @ 0x46
|
|
80005ea: f001 fd1e bl 800202a <HAL_NVIC_EnableIRQ>
|
|
|
|
}
|
|
80005ee: bf00 nop
|
|
80005f0: 3708 adds r7, #8
|
|
80005f2: 46bd mov sp, r7
|
|
80005f4: bd80 pop {r7, pc}
|
|
80005f6: bf00 nop
|
|
80005f8: 40023800 .word 0x40023800
|
|
|
|
080005fc <MX_GPIO_Init>:
|
|
* Output
|
|
* EVENT_OUT
|
|
* EXTI
|
|
*/
|
|
void MX_GPIO_Init(void)
|
|
{
|
|
80005fc: b580 push {r7, lr}
|
|
80005fe: b08a sub sp, #40 @ 0x28
|
|
8000600: af00 add r7, sp, #0
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000602: f107 0314 add.w r3, r7, #20
|
|
8000606: 2200 movs r2, #0
|
|
8000608: 601a str r2, [r3, #0]
|
|
800060a: 605a str r2, [r3, #4]
|
|
800060c: 609a str r2, [r3, #8]
|
|
800060e: 60da str r2, [r3, #12]
|
|
8000610: 611a str r2, [r3, #16]
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
8000612: 2300 movs r3, #0
|
|
8000614: 613b str r3, [r7, #16]
|
|
8000616: 4b45 ldr r3, [pc, #276] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000618: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800061a: 4a44 ldr r2, [pc, #272] @ (800072c <MX_GPIO_Init+0x130>)
|
|
800061c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8000620: 6313 str r3, [r2, #48] @ 0x30
|
|
8000622: 4b42 ldr r3, [pc, #264] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000624: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000626: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800062a: 613b str r3, [r7, #16]
|
|
800062c: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800062e: 2300 movs r3, #0
|
|
8000630: 60fb str r3, [r7, #12]
|
|
8000632: 4b3e ldr r3, [pc, #248] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000634: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000636: 4a3d ldr r2, [pc, #244] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000638: f043 0301 orr.w r3, r3, #1
|
|
800063c: 6313 str r3, [r2, #48] @ 0x30
|
|
800063e: 4b3b ldr r3, [pc, #236] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000640: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000642: f003 0301 and.w r3, r3, #1
|
|
8000646: 60fb str r3, [r7, #12]
|
|
8000648: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
800064a: 2300 movs r3, #0
|
|
800064c: 60bb str r3, [r7, #8]
|
|
800064e: 4b37 ldr r3, [pc, #220] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000650: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000652: 4a36 ldr r2, [pc, #216] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000654: f043 0304 orr.w r3, r3, #4
|
|
8000658: 6313 str r3, [r2, #48] @ 0x30
|
|
800065a: 4b34 ldr r3, [pc, #208] @ (800072c <MX_GPIO_Init+0x130>)
|
|
800065c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800065e: f003 0304 and.w r3, r3, #4
|
|
8000662: 60bb str r3, [r7, #8]
|
|
8000664: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000666: 2300 movs r3, #0
|
|
8000668: 607b str r3, [r7, #4]
|
|
800066a: 4b30 ldr r3, [pc, #192] @ (800072c <MX_GPIO_Init+0x130>)
|
|
800066c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800066e: 4a2f ldr r2, [pc, #188] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000670: f043 0302 orr.w r3, r3, #2
|
|
8000674: 6313 str r3, [r2, #48] @ 0x30
|
|
8000676: 4b2d ldr r3, [pc, #180] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000678: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800067a: f003 0302 and.w r3, r3, #2
|
|
800067e: 607b str r3, [r7, #4]
|
|
8000680: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8000682: 2300 movs r3, #0
|
|
8000684: 603b str r3, [r7, #0]
|
|
8000686: 4b29 ldr r3, [pc, #164] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000688: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800068a: 4a28 ldr r2, [pc, #160] @ (800072c <MX_GPIO_Init+0x130>)
|
|
800068c: f043 0308 orr.w r3, r3, #8
|
|
8000690: 6313 str r3, [r2, #48] @ 0x30
|
|
8000692: 4b26 ldr r3, [pc, #152] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000694: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000696: f003 0308 and.w r3, r3, #8
|
|
800069a: 603b str r3, [r7, #0]
|
|
800069c: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET);
|
|
800069e: 2200 movs r2, #0
|
|
80006a0: f44f 7170 mov.w r1, #960 @ 0x3c0
|
|
80006a4: 4822 ldr r0, [pc, #136] @ (8000730 <MX_GPIO_Init+0x134>)
|
|
80006a6: f002 fa89 bl 8002bbc <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET);
|
|
80006aa: 2200 movs r2, #0
|
|
80006ac: f44f 7180 mov.w r1, #256 @ 0x100
|
|
80006b0: 4820 ldr r0, [pc, #128] @ (8000734 <MX_GPIO_Init+0x138>)
|
|
80006b2: f002 fa83 bl 8002bbc <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : PC4 PC5 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
|
|
80006b6: 2330 movs r3, #48 @ 0x30
|
|
80006b8: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
80006ba: 2300 movs r3, #0
|
|
80006bc: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
80006be: 2302 movs r3, #2
|
|
80006c0: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80006c2: f107 0314 add.w r3, r7, #20
|
|
80006c6: 4619 mov r1, r3
|
|
80006c8: 4819 ldr r0, [pc, #100] @ (8000730 <MX_GPIO_Init+0x134>)
|
|
80006ca: f002 f8cb bl 8002864 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PB0 PB1 PB2 PB10 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10;
|
|
80006ce: f240 4307 movw r3, #1031 @ 0x407
|
|
80006d2: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
80006d4: 2300 movs r3, #0
|
|
80006d6: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
80006d8: 2302 movs r3, #2
|
|
80006da: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80006dc: f107 0314 add.w r3, r7, #20
|
|
80006e0: 4619 mov r1, r3
|
|
80006e2: 4815 ldr r0, [pc, #84] @ (8000738 <MX_GPIO_Init+0x13c>)
|
|
80006e4: f002 f8be bl 8002864 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PC6 PC7 PC8 PC9 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9;
|
|
80006e8: f44f 7370 mov.w r3, #960 @ 0x3c0
|
|
80006ec: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80006ee: 2301 movs r3, #1
|
|
80006f0: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80006f2: 2300 movs r3, #0
|
|
80006f4: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80006f6: 2300 movs r3, #0
|
|
80006f8: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80006fa: f107 0314 add.w r3, r7, #20
|
|
80006fe: 4619 mov r1, r3
|
|
8000700: 480b ldr r0, [pc, #44] @ (8000730 <MX_GPIO_Init+0x134>)
|
|
8000702: f002 f8af bl 8002864 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : PA8 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_8;
|
|
8000706: f44f 7380 mov.w r3, #256 @ 0x100
|
|
800070a: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
800070c: 2301 movs r3, #1
|
|
800070e: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000710: 2300 movs r3, #0
|
|
8000712: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000714: 2300 movs r3, #0
|
|
8000716: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000718: f107 0314 add.w r3, r7, #20
|
|
800071c: 4619 mov r1, r3
|
|
800071e: 4805 ldr r0, [pc, #20] @ (8000734 <MX_GPIO_Init+0x138>)
|
|
8000720: f002 f8a0 bl 8002864 <HAL_GPIO_Init>
|
|
|
|
}
|
|
8000724: bf00 nop
|
|
8000726: 3728 adds r7, #40 @ 0x28
|
|
8000728: 46bd mov sp, r7
|
|
800072a: bd80 pop {r7, pc}
|
|
800072c: 40023800 .word 0x40023800
|
|
8000730: 40020800 .word 0x40020800
|
|
8000734: 40020000 .word 0x40020000
|
|
8000738: 40020400 .word 0x40020400
|
|
|
|
0800073c <MX_I2C1_Init>:
|
|
|
|
I2C_HandleTypeDef hi2c1;
|
|
|
|
/* I2C1 init function */
|
|
void MX_I2C1_Init(void)
|
|
{
|
|
800073c: b580 push {r7, lr}
|
|
800073e: af00 add r7, sp, #0
|
|
/* USER CODE END I2C1_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C1_Init 1 */
|
|
|
|
/* USER CODE END I2C1_Init 1 */
|
|
hi2c1.Instance = I2C1;
|
|
8000740: 4b12 ldr r3, [pc, #72] @ (800078c <MX_I2C1_Init+0x50>)
|
|
8000742: 4a13 ldr r2, [pc, #76] @ (8000790 <MX_I2C1_Init+0x54>)
|
|
8000744: 601a str r2, [r3, #0]
|
|
hi2c1.Init.ClockSpeed = 100000;
|
|
8000746: 4b11 ldr r3, [pc, #68] @ (800078c <MX_I2C1_Init+0x50>)
|
|
8000748: 4a12 ldr r2, [pc, #72] @ (8000794 <MX_I2C1_Init+0x58>)
|
|
800074a: 605a str r2, [r3, #4]
|
|
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
|
|
800074c: 4b0f ldr r3, [pc, #60] @ (800078c <MX_I2C1_Init+0x50>)
|
|
800074e: 2200 movs r2, #0
|
|
8000750: 609a str r2, [r3, #8]
|
|
hi2c1.Init.OwnAddress1 = 0;
|
|
8000752: 4b0e ldr r3, [pc, #56] @ (800078c <MX_I2C1_Init+0x50>)
|
|
8000754: 2200 movs r2, #0
|
|
8000756: 60da str r2, [r3, #12]
|
|
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
8000758: 4b0c ldr r3, [pc, #48] @ (800078c <MX_I2C1_Init+0x50>)
|
|
800075a: f44f 4280 mov.w r2, #16384 @ 0x4000
|
|
800075e: 611a str r2, [r3, #16]
|
|
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8000760: 4b0a ldr r3, [pc, #40] @ (800078c <MX_I2C1_Init+0x50>)
|
|
8000762: 2200 movs r2, #0
|
|
8000764: 615a str r2, [r3, #20]
|
|
hi2c1.Init.OwnAddress2 = 0;
|
|
8000766: 4b09 ldr r3, [pc, #36] @ (800078c <MX_I2C1_Init+0x50>)
|
|
8000768: 2200 movs r2, #0
|
|
800076a: 619a str r2, [r3, #24]
|
|
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
800076c: 4b07 ldr r3, [pc, #28] @ (800078c <MX_I2C1_Init+0x50>)
|
|
800076e: 2200 movs r2, #0
|
|
8000770: 61da str r2, [r3, #28]
|
|
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8000772: 4b06 ldr r3, [pc, #24] @ (800078c <MX_I2C1_Init+0x50>)
|
|
8000774: 2200 movs r2, #0
|
|
8000776: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
|
|
8000778: 4804 ldr r0, [pc, #16] @ (800078c <MX_I2C1_Init+0x50>)
|
|
800077a: f002 fa39 bl 8002bf0 <HAL_I2C_Init>
|
|
800077e: 4603 mov r3, r0
|
|
8000780: 2b00 cmp r3, #0
|
|
8000782: d001 beq.n 8000788 <MX_I2C1_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8000784: f000 fcf2 bl 800116c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C1_Init 2 */
|
|
|
|
/* USER CODE END I2C1_Init 2 */
|
|
|
|
}
|
|
8000788: bf00 nop
|
|
800078a: bd80 pop {r7, pc}
|
|
800078c: 200001bc .word 0x200001bc
|
|
8000790: 40005400 .word 0x40005400
|
|
8000794: 000186a0 .word 0x000186a0
|
|
|
|
08000798 <HAL_I2C_MspInit>:
|
|
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
|
|
{
|
|
8000798: b580 push {r7, lr}
|
|
800079a: b08a sub sp, #40 @ 0x28
|
|
800079c: af00 add r7, sp, #0
|
|
800079e: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80007a0: f107 0314 add.w r3, r7, #20
|
|
80007a4: 2200 movs r2, #0
|
|
80007a6: 601a str r2, [r3, #0]
|
|
80007a8: 605a str r2, [r3, #4]
|
|
80007aa: 609a str r2, [r3, #8]
|
|
80007ac: 60da str r2, [r3, #12]
|
|
80007ae: 611a str r2, [r3, #16]
|
|
if(i2cHandle->Instance==I2C1)
|
|
80007b0: 687b ldr r3, [r7, #4]
|
|
80007b2: 681b ldr r3, [r3, #0]
|
|
80007b4: 4a19 ldr r2, [pc, #100] @ (800081c <HAL_I2C_MspInit+0x84>)
|
|
80007b6: 4293 cmp r3, r2
|
|
80007b8: d12b bne.n 8000812 <HAL_I2C_MspInit+0x7a>
|
|
{
|
|
/* USER CODE BEGIN I2C1_MspInit 0 */
|
|
|
|
/* USER CODE END I2C1_MspInit 0 */
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80007ba: 2300 movs r3, #0
|
|
80007bc: 613b str r3, [r7, #16]
|
|
80007be: 4b18 ldr r3, [pc, #96] @ (8000820 <HAL_I2C_MspInit+0x88>)
|
|
80007c0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80007c2: 4a17 ldr r2, [pc, #92] @ (8000820 <HAL_I2C_MspInit+0x88>)
|
|
80007c4: f043 0302 orr.w r3, r3, #2
|
|
80007c8: 6313 str r3, [r2, #48] @ 0x30
|
|
80007ca: 4b15 ldr r3, [pc, #84] @ (8000820 <HAL_I2C_MspInit+0x88>)
|
|
80007cc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80007ce: f003 0302 and.w r3, r3, #2
|
|
80007d2: 613b str r3, [r7, #16]
|
|
80007d4: 693b ldr r3, [r7, #16]
|
|
/**I2C1 GPIO Configuration
|
|
PB6 ------> I2C1_SCL
|
|
PB7 ------> I2C1_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
80007d6: 23c0 movs r3, #192 @ 0xc0
|
|
80007d8: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
80007da: 2312 movs r3, #18
|
|
80007dc: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80007de: 2300 movs r3, #0
|
|
80007e0: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80007e2: 2303 movs r3, #3
|
|
80007e4: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
|
|
80007e6: 2304 movs r3, #4
|
|
80007e8: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80007ea: f107 0314 add.w r3, r7, #20
|
|
80007ee: 4619 mov r1, r3
|
|
80007f0: 480c ldr r0, [pc, #48] @ (8000824 <HAL_I2C_MspInit+0x8c>)
|
|
80007f2: f002 f837 bl 8002864 <HAL_GPIO_Init>
|
|
|
|
/* I2C1 clock enable */
|
|
__HAL_RCC_I2C1_CLK_ENABLE();
|
|
80007f6: 2300 movs r3, #0
|
|
80007f8: 60fb str r3, [r7, #12]
|
|
80007fa: 4b09 ldr r3, [pc, #36] @ (8000820 <HAL_I2C_MspInit+0x88>)
|
|
80007fc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80007fe: 4a08 ldr r2, [pc, #32] @ (8000820 <HAL_I2C_MspInit+0x88>)
|
|
8000800: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8000804: 6413 str r3, [r2, #64] @ 0x40
|
|
8000806: 4b06 ldr r3, [pc, #24] @ (8000820 <HAL_I2C_MspInit+0x88>)
|
|
8000808: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800080a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
800080e: 60fb str r3, [r7, #12]
|
|
8000810: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN I2C1_MspInit 1 */
|
|
|
|
/* USER CODE END I2C1_MspInit 1 */
|
|
}
|
|
}
|
|
8000812: bf00 nop
|
|
8000814: 3728 adds r7, #40 @ 0x28
|
|
8000816: 46bd mov sp, r7
|
|
8000818: bd80 pop {r7, pc}
|
|
800081a: bf00 nop
|
|
800081c: 40005400 .word 0x40005400
|
|
8000820: 40023800 .word 0x40023800
|
|
8000824: 40020400 .word 0x40020400
|
|
|
|
08000828 <pq_init>:
|
|
volatile uint8_t tail; // accessed in ISR
|
|
volatile uint8_t count; // optional, only if needed
|
|
} PacketQueue;
|
|
|
|
// Initialize
|
|
void pq_init(PacketQueue *q){
|
|
8000828: b480 push {r7}
|
|
800082a: b083 sub sp, #12
|
|
800082c: af00 add r7, sp, #0
|
|
800082e: 6078 str r0, [r7, #4]
|
|
q->head = 0;
|
|
8000830: 687b ldr r3, [r7, #4]
|
|
8000832: 2200 movs r2, #0
|
|
8000834: f883 2180 strb.w r2, [r3, #384] @ 0x180
|
|
q->tail = 0;
|
|
8000838: 687b ldr r3, [r7, #4]
|
|
800083a: 2200 movs r2, #0
|
|
800083c: f883 2181 strb.w r2, [r3, #385] @ 0x181
|
|
q->count = 0;
|
|
8000840: 687b ldr r3, [r7, #4]
|
|
8000842: 2200 movs r2, #0
|
|
8000844: f883 2182 strb.w r2, [r3, #386] @ 0x182
|
|
}
|
|
8000848: bf00 nop
|
|
800084a: 370c adds r7, #12
|
|
800084c: 46bd mov sp, r7
|
|
800084e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000852: 4770 bx lr
|
|
|
|
08000854 <pq_push>:
|
|
|
|
// Called from ISR
|
|
bool pq_push(PacketQueue *q, const uint8_t packet[PACKET_SIZE]){
|
|
8000854: b580 push {r7, lr}
|
|
8000856: b084 sub sp, #16
|
|
8000858: af00 add r7, sp, #0
|
|
800085a: 6078 str r0, [r7, #4]
|
|
800085c: 6039 str r1, [r7, #0]
|
|
uint8_t nextTail = (q->tail + 1) % QUEUE_CAPACITY;
|
|
800085e: 687b ldr r3, [r7, #4]
|
|
8000860: f893 3181 ldrb.w r3, [r3, #385] @ 0x181
|
|
8000864: b2db uxtb r3, r3
|
|
8000866: 3301 adds r3, #1
|
|
8000868: 425a negs r2, r3
|
|
800086a: f003 031f and.w r3, r3, #31
|
|
800086e: f002 021f and.w r2, r2, #31
|
|
8000872: bf58 it pl
|
|
8000874: 4253 negpl r3, r2
|
|
8000876: 73fb strb r3, [r7, #15]
|
|
if(nextTail == q->head) return false; // queue full
|
|
8000878: 687b ldr r3, [r7, #4]
|
|
800087a: f893 3180 ldrb.w r3, [r3, #384] @ 0x180
|
|
800087e: b2db uxtb r3, r3
|
|
8000880: 7bfa ldrb r2, [r7, #15]
|
|
8000882: 429a cmp r2, r3
|
|
8000884: d101 bne.n 800088a <pq_push+0x36>
|
|
8000886: 2300 movs r3, #0
|
|
8000888: e014 b.n 80008b4 <pq_push+0x60>
|
|
|
|
memcpy(q->data[q->tail], packet, PACKET_SIZE);
|
|
800088a: 687b ldr r3, [r7, #4]
|
|
800088c: f893 3181 ldrb.w r3, [r3, #385] @ 0x181
|
|
8000890: b2db uxtb r3, r3
|
|
8000892: 461a mov r2, r3
|
|
8000894: 4613 mov r3, r2
|
|
8000896: 005b lsls r3, r3, #1
|
|
8000898: 4413 add r3, r2
|
|
800089a: 009b lsls r3, r3, #2
|
|
800089c: 687a ldr r2, [r7, #4]
|
|
800089e: 4413 add r3, r2
|
|
80008a0: 220c movs r2, #12
|
|
80008a2: 6839 ldr r1, [r7, #0]
|
|
80008a4: 4618 mov r0, r3
|
|
80008a6: f00a faf7 bl 800ae98 <memcpy>
|
|
q->tail = nextTail;
|
|
80008aa: 687b ldr r3, [r7, #4]
|
|
80008ac: 7bfa ldrb r2, [r7, #15]
|
|
80008ae: f883 2181 strb.w r2, [r3, #385] @ 0x181
|
|
return true;
|
|
80008b2: 2301 movs r3, #1
|
|
}
|
|
80008b4: 4618 mov r0, r3
|
|
80008b6: 3710 adds r7, #16
|
|
80008b8: 46bd mov sp, r7
|
|
80008ba: bd80 pop {r7, pc}
|
|
|
|
080008bc <pq_pop>:
|
|
|
|
// Called from main
|
|
bool pq_pop(PacketQueue *q, uint8_t out_packet[PACKET_SIZE]){
|
|
80008bc: b580 push {r7, lr}
|
|
80008be: b082 sub sp, #8
|
|
80008c0: af00 add r7, sp, #0
|
|
80008c2: 6078 str r0, [r7, #4]
|
|
80008c4: 6039 str r1, [r7, #0]
|
|
if(q->head == q->tail) return false; // queue empty
|
|
80008c6: 687b ldr r3, [r7, #4]
|
|
80008c8: f893 3180 ldrb.w r3, [r3, #384] @ 0x180
|
|
80008cc: b2da uxtb r2, r3
|
|
80008ce: 687b ldr r3, [r7, #4]
|
|
80008d0: f893 3181 ldrb.w r3, [r3, #385] @ 0x181
|
|
80008d4: b2db uxtb r3, r3
|
|
80008d6: 429a cmp r2, r3
|
|
80008d8: d101 bne.n 80008de <pq_pop+0x22>
|
|
80008da: 2300 movs r3, #0
|
|
80008dc: e020 b.n 8000920 <pq_pop+0x64>
|
|
|
|
memcpy(out_packet, q->data[q->head], PACKET_SIZE);
|
|
80008de: 687b ldr r3, [r7, #4]
|
|
80008e0: f893 3180 ldrb.w r3, [r3, #384] @ 0x180
|
|
80008e4: b2db uxtb r3, r3
|
|
80008e6: 461a mov r2, r3
|
|
80008e8: 4613 mov r3, r2
|
|
80008ea: 005b lsls r3, r3, #1
|
|
80008ec: 4413 add r3, r2
|
|
80008ee: 009b lsls r3, r3, #2
|
|
80008f0: 687a ldr r2, [r7, #4]
|
|
80008f2: 4413 add r3, r2
|
|
80008f4: 220c movs r2, #12
|
|
80008f6: 4619 mov r1, r3
|
|
80008f8: 6838 ldr r0, [r7, #0]
|
|
80008fa: f00a facd bl 800ae98 <memcpy>
|
|
q->head = (q->head + 1) % QUEUE_CAPACITY;
|
|
80008fe: 687b ldr r3, [r7, #4]
|
|
8000900: f893 3180 ldrb.w r3, [r3, #384] @ 0x180
|
|
8000904: b2db uxtb r3, r3
|
|
8000906: 3301 adds r3, #1
|
|
8000908: 425a negs r2, r3
|
|
800090a: f003 031f and.w r3, r3, #31
|
|
800090e: f002 021f and.w r2, r2, #31
|
|
8000912: bf58 it pl
|
|
8000914: 4253 negpl r3, r2
|
|
8000916: b2da uxtb r2, r3
|
|
8000918: 687b ldr r3, [r7, #4]
|
|
800091a: f883 2180 strb.w r2, [r3, #384] @ 0x180
|
|
return true;
|
|
800091e: 2301 movs r3, #1
|
|
}
|
|
8000920: 4618 mov r0, r3
|
|
8000922: 3708 adds r7, #8
|
|
8000924: 46bd mov sp, r7
|
|
8000926: bd80 pop {r7, pc}
|
|
|
|
08000928 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8000928: b580 push {r7, lr}
|
|
800092a: b088 sub sp, #32
|
|
800092c: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
800092e: f001 f9ef bl 8001d10 <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8000932: f000 f96b bl 8000c0c <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8000936: f7ff fe61 bl 80005fc <MX_GPIO_Init>
|
|
MX_DMA_Init();
|
|
800093a: f7ff fdf9 bl 8000530 <MX_DMA_Init>
|
|
MX_TIM2_Init();
|
|
800093e: f000 fd07 bl 8001350 <MX_TIM2_Init>
|
|
MX_TIM3_Init();
|
|
8000942: f000 fd5d bl 8001400 <MX_TIM3_Init>
|
|
MX_UART4_Init();
|
|
8000946: f000 fe4f bl 80015e8 <MX_UART4_Init>
|
|
MX_UART5_Init();
|
|
800094a: f000 fe77 bl 800163c <MX_UART5_Init>
|
|
MX_USART1_UART_Init();
|
|
800094e: f000 fe9f bl 8001690 <MX_USART1_UART_Init>
|
|
MX_USART2_UART_Init();
|
|
8000952: f000 fec7 bl 80016e4 <MX_USART2_UART_Init>
|
|
MX_I2C1_Init();
|
|
8000956: f7ff fef1 bl 800073c <MX_I2C1_Init>
|
|
MX_USB_DEVICE_Init();
|
|
800095a: f009 fdc3 bl 800a4e4 <MX_USB_DEVICE_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
|
|
//Enable UART RX DMA for all ports
|
|
HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage));
|
|
800095e: 2210 movs r2, #16
|
|
8000960: 4953 ldr r1, [pc, #332] @ (8000ab0 <main+0x188>)
|
|
8000962: 4854 ldr r0, [pc, #336] @ (8000ab4 <main+0x18c>)
|
|
8000964: f005 fbc4 bl 80060f0 <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage));
|
|
8000968: 2210 movs r2, #16
|
|
800096a: 4953 ldr r1, [pc, #332] @ (8000ab8 <main+0x190>)
|
|
800096c: 4853 ldr r0, [pc, #332] @ (8000abc <main+0x194>)
|
|
800096e: f005 fbbf bl 80060f0 <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage));
|
|
8000972: 2210 movs r2, #16
|
|
8000974: 4952 ldr r1, [pc, #328] @ (8000ac0 <main+0x198>)
|
|
8000976: 4853 ldr r0, [pc, #332] @ (8000ac4 <main+0x19c>)
|
|
8000978: f005 fbba bl 80060f0 <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage));
|
|
800097c: 2210 movs r2, #16
|
|
800097e: 4952 ldr r1, [pc, #328] @ (8000ac8 <main+0x1a0>)
|
|
8000980: 4852 ldr r0, [pc, #328] @ (8000acc <main+0x1a4>)
|
|
8000982: f005 fbb5 bl 80060f0 <HAL_UART_Receive_DMA>
|
|
|
|
// Start TIM3 encoder (PA6/PA7) so we can read encoder delta
|
|
HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL);
|
|
8000986: 213c movs r1, #60 @ 0x3c
|
|
8000988: 4851 ldr r0, [pc, #324] @ (8000ad0 <main+0x1a8>)
|
|
800098a: f004 ff02 bl 8005792 <HAL_TIM_Encoder_Start>
|
|
LAST_ENCODER_COUNT = __HAL_TIM_GET_COUNTER(&htim3);
|
|
800098e: 4b50 ldr r3, [pc, #320] @ (8000ad0 <main+0x1a8>)
|
|
8000990: 681b ldr r3, [r3, #0]
|
|
8000992: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8000994: 461a mov r2, r3
|
|
8000996: 4b4f ldr r3, [pc, #316] @ (8000ad4 <main+0x1ac>)
|
|
8000998: 601a str r2, [r3, #0]
|
|
|
|
//Prealloc Kestate matrix
|
|
memset(KEYSTATE, 0, sizeof(KEYSTATE));
|
|
800099a: 221e movs r2, #30
|
|
800099c: 2100 movs r1, #0
|
|
800099e: 484e ldr r0, [pc, #312] @ (8000ad8 <main+0x1b0>)
|
|
80009a0: f00a fa4e bl 800ae40 <memset>
|
|
pq_init(&huart1q);
|
|
80009a4: 484d ldr r0, [pc, #308] @ (8000adc <main+0x1b4>)
|
|
80009a6: f7ff ff3f bl 8000828 <pq_init>
|
|
pq_init(&huart2q);
|
|
80009aa: 484d ldr r0, [pc, #308] @ (8000ae0 <main+0x1b8>)
|
|
80009ac: f7ff ff3c bl 8000828 <pq_init>
|
|
pq_init(&huart4q);
|
|
80009b0: 484c ldr r0, [pc, #304] @ (8000ae4 <main+0x1bc>)
|
|
80009b2: f7ff ff39 bl 8000828 <pq_init>
|
|
pq_init(&huart5q);
|
|
80009b6: 484c ldr r0, [pc, #304] @ (8000ae8 <main+0x1c0>)
|
|
80009b8: f7ff ff36 bl 8000828 <pq_init>
|
|
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
switch (MODE){
|
|
80009bc: 4b4b ldr r3, [pc, #300] @ (8000aec <main+0x1c4>)
|
|
80009be: 781b ldrb r3, [r3, #0]
|
|
80009c0: b2db uxtb r3, r3
|
|
80009c2: 2b02 cmp r3, #2
|
|
80009c4: d006 beq.n 80009d4 <main+0xac>
|
|
80009c6: 2b02 cmp r3, #2
|
|
80009c8: dc6a bgt.n 8000aa0 <main+0x178>
|
|
80009ca: 2b00 cmp r3, #0
|
|
80009cc: d025 beq.n 8000a1a <main+0xf2>
|
|
80009ce: 2b01 cmp r3, #1
|
|
80009d0: d05a beq.n 8000a88 <main+0x160>
|
|
//encoderProcess();
|
|
USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT));
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
80009d2: e065 b.n 8000aa0 <main+0x178>
|
|
KEYSTATE_CHANGED_FLAG = 1;
|
|
80009d4: 4b46 ldr r3, [pc, #280] @ (8000af0 <main+0x1c8>)
|
|
80009d6: 2201 movs r2, #1
|
|
80009d8: 701a strb r2, [r3, #0]
|
|
resetReport();
|
|
80009da: f000 fbbb bl 8001154 <resetReport>
|
|
matrixScan();
|
|
80009de: f000 fb41 bl 8001064 <matrixScan>
|
|
mergeChild();
|
|
80009e2: f000 f88f bl 8000b04 <mergeChild>
|
|
if(KEYSTATE_CHANGED_FLAG == 1){
|
|
80009e6: 4b42 ldr r3, [pc, #264] @ (8000af0 <main+0x1c8>)
|
|
80009e8: 781b ldrb r3, [r3, #0]
|
|
80009ea: 2b01 cmp r3, #1
|
|
80009ec: d15a bne.n 8000aa4 <main+0x17c>
|
|
UARTREPORT.DEPTH = DEPTH;
|
|
80009ee: 4b41 ldr r3, [pc, #260] @ (8000af4 <main+0x1cc>)
|
|
80009f0: 881b ldrh r3, [r3, #0]
|
|
80009f2: 823b strh r3, [r7, #16]
|
|
UARTREPORT.TYPE = 0xEE;
|
|
80009f4: 23ee movs r3, #238 @ 0xee
|
|
80009f6: 827b strh r3, [r7, #18]
|
|
memcpy(UARTREPORT.KEYPRESS, REPORT.KEYPRESS, sizeof(UARTREPORT.KEYPRESS));
|
|
80009f8: 4a3f ldr r2, [pc, #252] @ (8000af8 <main+0x1d0>)
|
|
80009fa: f107 0314 add.w r3, r7, #20
|
|
80009fe: 3202 adds r2, #2
|
|
8000a00: 6810 ldr r0, [r2, #0]
|
|
8000a02: 6851 ldr r1, [r2, #4]
|
|
8000a04: 6892 ldr r2, [r2, #8]
|
|
8000a06: c307 stmia r3!, {r0, r1, r2}
|
|
HAL_UART_Transmit_DMA(PARENT, (uint8_t*)&UARTREPORT, sizeof(UARTREPORT));
|
|
8000a08: 4b3c ldr r3, [pc, #240] @ (8000afc <main+0x1d4>)
|
|
8000a0a: 681b ldr r3, [r3, #0]
|
|
8000a0c: f107 0110 add.w r1, r7, #16
|
|
8000a10: 2210 movs r2, #16
|
|
8000a12: 4618 mov r0, r3
|
|
8000a14: f005 faf0 bl 8005ff8 <HAL_UART_Transmit_DMA>
|
|
break;
|
|
8000a18: e044 b.n 8000aa4 <main+0x17c>
|
|
if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){
|
|
8000a1a: 4b39 ldr r3, [pc, #228] @ (8000b00 <main+0x1d8>)
|
|
8000a1c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8000a20: b2db uxtb r3, r3
|
|
8000a22: 2b03 cmp r3, #3
|
|
8000a24: d106 bne.n 8000a34 <main+0x10c>
|
|
MODE = MODE_MAINBOARD;
|
|
8000a26: 4b31 ldr r3, [pc, #196] @ (8000aec <main+0x1c4>)
|
|
8000a28: 2201 movs r2, #1
|
|
8000a2a: 701a strb r2, [r3, #0]
|
|
DEPTH = 0;
|
|
8000a2c: 4b31 ldr r3, [pc, #196] @ (8000af4 <main+0x1cc>)
|
|
8000a2e: 2200 movs r2, #0
|
|
8000a30: 801a strh r2, [r3, #0]
|
|
break;
|
|
8000a32: e038 b.n 8000aa6 <main+0x17e>
|
|
REQ.DEPTH = 0;
|
|
8000a34: 2300 movs r3, #0
|
|
8000a36: 803b strh r3, [r7, #0]
|
|
REQ.TYPE = 0xFF; //Message code for request is 0xFF
|
|
8000a38: 23ff movs r3, #255 @ 0xff
|
|
8000a3a: 807b strh r3, [r7, #2]
|
|
memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS));
|
|
8000a3c: 463b mov r3, r7
|
|
8000a3e: 3304 adds r3, #4
|
|
8000a40: 220c movs r2, #12
|
|
8000a42: 2100 movs r1, #0
|
|
8000a44: 4618 mov r0, r3
|
|
8000a46: f00a f9fb bl 800ae40 <memset>
|
|
HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ));
|
|
8000a4a: 463b mov r3, r7
|
|
8000a4c: 2210 movs r2, #16
|
|
8000a4e: 4619 mov r1, r3
|
|
8000a50: 4818 ldr r0, [pc, #96] @ (8000ab4 <main+0x18c>)
|
|
8000a52: f005 fad1 bl 8005ff8 <HAL_UART_Transmit_DMA>
|
|
HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ));
|
|
8000a56: 463b mov r3, r7
|
|
8000a58: 2210 movs r2, #16
|
|
8000a5a: 4619 mov r1, r3
|
|
8000a5c: 4817 ldr r0, [pc, #92] @ (8000abc <main+0x194>)
|
|
8000a5e: f005 facb bl 8005ff8 <HAL_UART_Transmit_DMA>
|
|
HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ));
|
|
8000a62: 463b mov r3, r7
|
|
8000a64: 2210 movs r2, #16
|
|
8000a66: 4619 mov r1, r3
|
|
8000a68: 4816 ldr r0, [pc, #88] @ (8000ac4 <main+0x19c>)
|
|
8000a6a: f005 fac5 bl 8005ff8 <HAL_UART_Transmit_DMA>
|
|
HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ));
|
|
8000a6e: 463b mov r3, r7
|
|
8000a70: 2210 movs r2, #16
|
|
8000a72: 4619 mov r1, r3
|
|
8000a74: 4815 ldr r0, [pc, #84] @ (8000acc <main+0x1a4>)
|
|
8000a76: f005 fabf bl 8005ff8 <HAL_UART_Transmit_DMA>
|
|
HAL_Delay(500);
|
|
8000a7a: f44f 70fa mov.w r0, #500 @ 0x1f4
|
|
8000a7e: f001 f9b9 bl 8001df4 <HAL_Delay>
|
|
findBestParent(); //So true...
|
|
8000a82: f000 f9d7 bl 8000e34 <findBestParent>
|
|
break;
|
|
8000a86: e00e b.n 8000aa6 <main+0x17e>
|
|
resetReport();
|
|
8000a88: f000 fb64 bl 8001154 <resetReport>
|
|
matrixScan();//Something related to this making the key stick. Likely due to race conditions
|
|
8000a8c: f000 faea bl 8001064 <matrixScan>
|
|
mergeChild();
|
|
8000a90: f000 f838 bl 8000b04 <mergeChild>
|
|
USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT));
|
|
8000a94: 220e movs r2, #14
|
|
8000a96: 4918 ldr r1, [pc, #96] @ (8000af8 <main+0x1d0>)
|
|
8000a98: 4819 ldr r0, [pc, #100] @ (8000b00 <main+0x1d8>)
|
|
8000a9a: f008 f957 bl 8008d4c <USBD_HID_SendReport>
|
|
break;
|
|
8000a9e: e002 b.n 8000aa6 <main+0x17e>
|
|
break;
|
|
8000aa0: bf00 nop
|
|
8000aa2: e000 b.n 8000aa6 <main+0x17e>
|
|
break;
|
|
8000aa4: bf00 nop
|
|
}
|
|
|
|
HAL_Delay(20);
|
|
8000aa6: 2014 movs r0, #20
|
|
8000aa8: f001 f9a4 bl 8001df4 <HAL_Delay>
|
|
switch (MODE){
|
|
8000aac: e786 b.n 80009bc <main+0x94>
|
|
8000aae: bf00 nop
|
|
8000ab0: 20000230 .word 0x20000230
|
|
8000ab4: 200009f0 .word 0x200009f0
|
|
8000ab8: 20000240 .word 0x20000240
|
|
8000abc: 20000a38 .word 0x20000a38
|
|
8000ac0: 20000250 .word 0x20000250
|
|
8000ac4: 20000960 .word 0x20000960
|
|
8000ac8: 20000220 .word 0x20000220
|
|
8000acc: 200009a8 .word 0x200009a8
|
|
8000ad0: 20000918 .word 0x20000918
|
|
8000ad4: 2000028c .word 0x2000028c
|
|
8000ad8: 2000026c .word 0x2000026c
|
|
8000adc: 200002c0 .word 0x200002c0
|
|
8000ae0: 20000444 .word 0x20000444
|
|
8000ae4: 200005c8 .word 0x200005c8
|
|
8000ae8: 2000074c .word 0x2000074c
|
|
8000aec: 2000028a .word 0x2000028a
|
|
8000af0: 20000268 .word 0x20000268
|
|
8000af4: 20000260 .word 0x20000260
|
|
8000af8: 20000210 .word 0x20000210
|
|
8000afc: 20000264 .word 0x20000264
|
|
8000b00: 20000d88 .word 0x20000d88
|
|
|
|
08000b04 <mergeChild>:
|
|
/* USER CODE BEGIN 3 */
|
|
}
|
|
/* USER CODE END 3 */
|
|
}
|
|
|
|
void mergeChild(){
|
|
8000b04: b590 push {r4, r7, lr}
|
|
8000b06: b087 sub sp, #28
|
|
8000b08: af00 add r7, sp, #0
|
|
uint8_t packet[12];
|
|
if (pq_pop(&huart1q, packet)) {
|
|
8000b0a: 1d3b adds r3, r7, #4
|
|
8000b0c: 4619 mov r1, r3
|
|
8000b0e: 4838 ldr r0, [pc, #224] @ (8000bf0 <mergeChild+0xec>)
|
|
8000b10: f7ff fed4 bl 80008bc <pq_pop>
|
|
8000b14: 4603 mov r3, r0
|
|
8000b16: 2b00 cmp r3, #0
|
|
8000b18: d008 beq.n 8000b2c <mergeChild+0x28>
|
|
memcpy(UART_KEYSTATE[1], packet, 12);
|
|
8000b1a: 4b36 ldr r3, [pc, #216] @ (8000bf4 <mergeChild+0xf0>)
|
|
8000b1c: 330c adds r3, #12
|
|
8000b1e: 1d3a adds r2, r7, #4
|
|
8000b20: ca07 ldmia r2, {r0, r1, r2}
|
|
8000b22: e883 0007 stmia.w r3, {r0, r1, r2}
|
|
KEYSTATE_CHANGED_FLAG = 1;
|
|
8000b26: 4b34 ldr r3, [pc, #208] @ (8000bf8 <mergeChild+0xf4>)
|
|
8000b28: 2201 movs r2, #1
|
|
8000b2a: 701a strb r2, [r3, #0]
|
|
}
|
|
if (pq_pop(&huart2q, packet)) {
|
|
8000b2c: 1d3b adds r3, r7, #4
|
|
8000b2e: 4619 mov r1, r3
|
|
8000b30: 4832 ldr r0, [pc, #200] @ (8000bfc <mergeChild+0xf8>)
|
|
8000b32: f7ff fec3 bl 80008bc <pq_pop>
|
|
8000b36: 4603 mov r3, r0
|
|
8000b38: 2b00 cmp r3, #0
|
|
8000b3a: d008 beq.n 8000b4e <mergeChild+0x4a>
|
|
memcpy(UART_KEYSTATE[2], packet, 12);
|
|
8000b3c: 4b2d ldr r3, [pc, #180] @ (8000bf4 <mergeChild+0xf0>)
|
|
8000b3e: 3318 adds r3, #24
|
|
8000b40: 1d3a adds r2, r7, #4
|
|
8000b42: ca07 ldmia r2, {r0, r1, r2}
|
|
8000b44: e883 0007 stmia.w r3, {r0, r1, r2}
|
|
KEYSTATE_CHANGED_FLAG = 1;
|
|
8000b48: 4b2b ldr r3, [pc, #172] @ (8000bf8 <mergeChild+0xf4>)
|
|
8000b4a: 2201 movs r2, #1
|
|
8000b4c: 701a strb r2, [r3, #0]
|
|
}
|
|
if (pq_pop(&huart4q, packet)) {
|
|
8000b4e: 1d3b adds r3, r7, #4
|
|
8000b50: 4619 mov r1, r3
|
|
8000b52: 482b ldr r0, [pc, #172] @ (8000c00 <mergeChild+0xfc>)
|
|
8000b54: f7ff feb2 bl 80008bc <pq_pop>
|
|
8000b58: 4603 mov r3, r0
|
|
8000b5a: 2b00 cmp r3, #0
|
|
8000b5c: d008 beq.n 8000b70 <mergeChild+0x6c>
|
|
memcpy(UART_KEYSTATE[3], packet, 12);
|
|
8000b5e: 4b25 ldr r3, [pc, #148] @ (8000bf4 <mergeChild+0xf0>)
|
|
8000b60: 3324 adds r3, #36 @ 0x24
|
|
8000b62: 1d3a adds r2, r7, #4
|
|
8000b64: ca07 ldmia r2, {r0, r1, r2}
|
|
8000b66: e883 0007 stmia.w r3, {r0, r1, r2}
|
|
KEYSTATE_CHANGED_FLAG = 1;
|
|
8000b6a: 4b23 ldr r3, [pc, #140] @ (8000bf8 <mergeChild+0xf4>)
|
|
8000b6c: 2201 movs r2, #1
|
|
8000b6e: 701a strb r2, [r3, #0]
|
|
}
|
|
if (pq_pop(&huart5q, packet)) {
|
|
8000b70: 1d3b adds r3, r7, #4
|
|
8000b72: 4619 mov r1, r3
|
|
8000b74: 4823 ldr r0, [pc, #140] @ (8000c04 <mergeChild+0x100>)
|
|
8000b76: f7ff fea1 bl 80008bc <pq_pop>
|
|
8000b7a: 4603 mov r3, r0
|
|
8000b7c: 2b00 cmp r3, #0
|
|
8000b7e: d009 beq.n 8000b94 <mergeChild+0x90>
|
|
memcpy(UART_KEYSTATE[0], packet, 12);
|
|
8000b80: 4b1c ldr r3, [pc, #112] @ (8000bf4 <mergeChild+0xf0>)
|
|
8000b82: 461c mov r4, r3
|
|
8000b84: 1d3b adds r3, r7, #4
|
|
8000b86: e893 0007 ldmia.w r3, {r0, r1, r2}
|
|
8000b8a: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
KEYSTATE_CHANGED_FLAG = 1;
|
|
8000b8e: 4b1a ldr r3, [pc, #104] @ (8000bf8 <mergeChild+0xf4>)
|
|
8000b90: 2201 movs r2, #1
|
|
8000b92: 701a strb r2, [r3, #0]
|
|
}
|
|
for(int i = 0; i < 4; i++){
|
|
8000b94: 2300 movs r3, #0
|
|
8000b96: 617b str r3, [r7, #20]
|
|
8000b98: e022 b.n 8000be0 <mergeChild+0xdc>
|
|
for(int j = 0; j < 12; j++){
|
|
8000b9a: 2300 movs r3, #0
|
|
8000b9c: 613b str r3, [r7, #16]
|
|
8000b9e: e019 b.n 8000bd4 <mergeChild+0xd0>
|
|
REPORT.KEYPRESS[j] |= UART_KEYSTATE[i][j];
|
|
8000ba0: 4a19 ldr r2, [pc, #100] @ (8000c08 <mergeChild+0x104>)
|
|
8000ba2: 693b ldr r3, [r7, #16]
|
|
8000ba4: 4413 add r3, r2
|
|
8000ba6: 3302 adds r3, #2
|
|
8000ba8: 7819 ldrb r1, [r3, #0]
|
|
8000baa: 4812 ldr r0, [pc, #72] @ (8000bf4 <mergeChild+0xf0>)
|
|
8000bac: 697a ldr r2, [r7, #20]
|
|
8000bae: 4613 mov r3, r2
|
|
8000bb0: 005b lsls r3, r3, #1
|
|
8000bb2: 4413 add r3, r2
|
|
8000bb4: 009b lsls r3, r3, #2
|
|
8000bb6: 18c2 adds r2, r0, r3
|
|
8000bb8: 693b ldr r3, [r7, #16]
|
|
8000bba: 4413 add r3, r2
|
|
8000bbc: 781b ldrb r3, [r3, #0]
|
|
8000bbe: 430b orrs r3, r1
|
|
8000bc0: b2d9 uxtb r1, r3
|
|
8000bc2: 4a11 ldr r2, [pc, #68] @ (8000c08 <mergeChild+0x104>)
|
|
8000bc4: 693b ldr r3, [r7, #16]
|
|
8000bc6: 4413 add r3, r2
|
|
8000bc8: 3302 adds r3, #2
|
|
8000bca: 460a mov r2, r1
|
|
8000bcc: 701a strb r2, [r3, #0]
|
|
for(int j = 0; j < 12; j++){
|
|
8000bce: 693b ldr r3, [r7, #16]
|
|
8000bd0: 3301 adds r3, #1
|
|
8000bd2: 613b str r3, [r7, #16]
|
|
8000bd4: 693b ldr r3, [r7, #16]
|
|
8000bd6: 2b0b cmp r3, #11
|
|
8000bd8: dde2 ble.n 8000ba0 <mergeChild+0x9c>
|
|
for(int i = 0; i < 4; i++){
|
|
8000bda: 697b ldr r3, [r7, #20]
|
|
8000bdc: 3301 adds r3, #1
|
|
8000bde: 617b str r3, [r7, #20]
|
|
8000be0: 697b ldr r3, [r7, #20]
|
|
8000be2: 2b03 cmp r3, #3
|
|
8000be4: ddd9 ble.n 8000b9a <mergeChild+0x96>
|
|
}
|
|
}
|
|
}
|
|
8000be6: bf00 nop
|
|
8000be8: bf00 nop
|
|
8000bea: 371c adds r7, #28
|
|
8000bec: 46bd mov sp, r7
|
|
8000bee: bd90 pop {r4, r7, pc}
|
|
8000bf0: 200002c0 .word 0x200002c0
|
|
8000bf4: 20000290 .word 0x20000290
|
|
8000bf8: 20000268 .word 0x20000268
|
|
8000bfc: 20000444 .word 0x20000444
|
|
8000c00: 200005c8 .word 0x200005c8
|
|
8000c04: 2000074c .word 0x2000074c
|
|
8000c08: 20000210 .word 0x20000210
|
|
|
|
08000c0c <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8000c0c: b580 push {r7, lr}
|
|
8000c0e: b094 sub sp, #80 @ 0x50
|
|
8000c10: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
8000c12: f107 031c add.w r3, r7, #28
|
|
8000c16: 2234 movs r2, #52 @ 0x34
|
|
8000c18: 2100 movs r1, #0
|
|
8000c1a: 4618 mov r0, r3
|
|
8000c1c: f00a f910 bl 800ae40 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
8000c20: f107 0308 add.w r3, r7, #8
|
|
8000c24: 2200 movs r2, #0
|
|
8000c26: 601a str r2, [r3, #0]
|
|
8000c28: 605a str r2, [r3, #4]
|
|
8000c2a: 609a str r2, [r3, #8]
|
|
8000c2c: 60da str r2, [r3, #12]
|
|
8000c2e: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator out put voltage
|
|
*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000c30: 2300 movs r3, #0
|
|
8000c32: 607b str r3, [r7, #4]
|
|
8000c34: 4b29 ldr r3, [pc, #164] @ (8000cdc <SystemClock_Config+0xd0>)
|
|
8000c36: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000c38: 4a28 ldr r2, [pc, #160] @ (8000cdc <SystemClock_Config+0xd0>)
|
|
8000c3a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8000c3e: 6413 str r3, [r2, #64] @ 0x40
|
|
8000c40: 4b26 ldr r3, [pc, #152] @ (8000cdc <SystemClock_Config+0xd0>)
|
|
8000c42: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000c44: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8000c48: 607b str r3, [r7, #4]
|
|
8000c4a: 687b ldr r3, [r7, #4]
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
|
|
8000c4c: 2300 movs r3, #0
|
|
8000c4e: 603b str r3, [r7, #0]
|
|
8000c50: 4b23 ldr r3, [pc, #140] @ (8000ce0 <SystemClock_Config+0xd4>)
|
|
8000c52: 681b ldr r3, [r3, #0]
|
|
8000c54: f423 4340 bic.w r3, r3, #49152 @ 0xc000
|
|
8000c58: 4a21 ldr r2, [pc, #132] @ (8000ce0 <SystemClock_Config+0xd4>)
|
|
8000c5a: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8000c5e: 6013 str r3, [r2, #0]
|
|
8000c60: 4b1f ldr r3, [pc, #124] @ (8000ce0 <SystemClock_Config+0xd4>)
|
|
8000c62: 681b ldr r3, [r3, #0]
|
|
8000c64: f403 4340 and.w r3, r3, #49152 @ 0xc000
|
|
8000c68: 603b str r3, [r7, #0]
|
|
8000c6a: 683b ldr r3, [r7, #0]
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
8000c6c: 2301 movs r3, #1
|
|
8000c6e: 61fb str r3, [r7, #28]
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
8000c70: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
8000c74: 623b str r3, [r7, #32]
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
8000c76: 2302 movs r3, #2
|
|
8000c78: 637b str r3, [r7, #52] @ 0x34
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
8000c7a: f44f 0380 mov.w r3, #4194304 @ 0x400000
|
|
8000c7e: 63bb str r3, [r7, #56] @ 0x38
|
|
RCC_OscInitStruct.PLL.PLLM = 4;
|
|
8000c80: 2304 movs r3, #4
|
|
8000c82: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.PLL.PLLN = 96;
|
|
8000c84: 2360 movs r3, #96 @ 0x60
|
|
8000c86: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
8000c88: 2302 movs r3, #2
|
|
8000c8a: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLQ = 4;
|
|
8000c8c: 2304 movs r3, #4
|
|
8000c8e: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLR = 2;
|
|
8000c90: 2302 movs r3, #2
|
|
8000c92: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8000c94: f107 031c add.w r3, r7, #28
|
|
8000c98: 4618 mov r0, r3
|
|
8000c9a: f004 f9e7 bl 800506c <HAL_RCC_OscConfig>
|
|
8000c9e: 4603 mov r3, r0
|
|
8000ca0: 2b00 cmp r3, #0
|
|
8000ca2: d001 beq.n 8000ca8 <SystemClock_Config+0x9c>
|
|
{
|
|
Error_Handler();
|
|
8000ca4: f000 fa62 bl 800116c <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
8000ca8: 230f movs r3, #15
|
|
8000caa: 60bb str r3, [r7, #8]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
8000cac: 2302 movs r3, #2
|
|
8000cae: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
|
|
8000cb0: 2380 movs r3, #128 @ 0x80
|
|
8000cb2: 613b str r3, [r7, #16]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
|
|
8000cb4: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8000cb8: 617b str r3, [r7, #20]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
8000cba: 2300 movs r3, #0
|
|
8000cbc: 61bb str r3, [r7, #24]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
|
|
8000cbe: f107 0308 add.w r3, r7, #8
|
|
8000cc2: 2101 movs r1, #1
|
|
8000cc4: 4618 mov r0, r3
|
|
8000cc6: f003 fb5d bl 8004384 <HAL_RCC_ClockConfig>
|
|
8000cca: 4603 mov r3, r0
|
|
8000ccc: 2b00 cmp r3, #0
|
|
8000cce: d001 beq.n 8000cd4 <SystemClock_Config+0xc8>
|
|
{
|
|
Error_Handler();
|
|
8000cd0: f000 fa4c bl 800116c <Error_Handler>
|
|
}
|
|
}
|
|
8000cd4: bf00 nop
|
|
8000cd6: 3750 adds r7, #80 @ 0x50
|
|
8000cd8: 46bd mov sp, r7
|
|
8000cda: bd80 pop {r7, pc}
|
|
8000cdc: 40023800 .word 0x40023800
|
|
8000ce0: 40007000 .word 0x40007000
|
|
|
|
08000ce4 <HAL_UART_RxCpltCallback>:
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
// UART Message Requests Goes Here
|
|
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) {
|
|
8000ce4: b580 push {r7, lr}
|
|
8000ce6: b082 sub sp, #8
|
|
8000ce8: af00 add r7, sp, #0
|
|
8000cea: 6078 str r0, [r7, #4]
|
|
if (huart->Instance == USART1) {
|
|
8000cec: 687b ldr r3, [r7, #4]
|
|
8000cee: 681b ldr r3, [r3, #0]
|
|
8000cf0: 4a1e ldr r2, [pc, #120] @ (8000d6c <HAL_UART_RxCpltCallback+0x88>)
|
|
8000cf2: 4293 cmp r3, r2
|
|
8000cf4: d109 bne.n 8000d0a <HAL_UART_RxCpltCallback+0x26>
|
|
handleUARTMessages((uint8_t*)&RX1Msg, &huart1);
|
|
8000cf6: 491e ldr r1, [pc, #120] @ (8000d70 <HAL_UART_RxCpltCallback+0x8c>)
|
|
8000cf8: 481e ldr r0, [pc, #120] @ (8000d74 <HAL_UART_RxCpltCallback+0x90>)
|
|
8000cfa: f000 f8dd bl 8000eb8 <handleUARTMessages>
|
|
HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage));
|
|
8000cfe: 2210 movs r2, #16
|
|
8000d00: 491c ldr r1, [pc, #112] @ (8000d74 <HAL_UART_RxCpltCallback+0x90>)
|
|
8000d02: 481b ldr r0, [pc, #108] @ (8000d70 <HAL_UART_RxCpltCallback+0x8c>)
|
|
8000d04: f005 f9f4 bl 80060f0 <HAL_UART_Receive_DMA>
|
|
}
|
|
else if (huart->Instance == UART5) {
|
|
handleUARTMessages((uint8_t*)&RX5Msg, &huart5);
|
|
HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage));
|
|
}
|
|
}
|
|
8000d08: e02b b.n 8000d62 <HAL_UART_RxCpltCallback+0x7e>
|
|
else if (huart->Instance == USART2) {
|
|
8000d0a: 687b ldr r3, [r7, #4]
|
|
8000d0c: 681b ldr r3, [r3, #0]
|
|
8000d0e: 4a1a ldr r2, [pc, #104] @ (8000d78 <HAL_UART_RxCpltCallback+0x94>)
|
|
8000d10: 4293 cmp r3, r2
|
|
8000d12: d109 bne.n 8000d28 <HAL_UART_RxCpltCallback+0x44>
|
|
handleUARTMessages((uint8_t*)&RX2Msg, &huart2);
|
|
8000d14: 4919 ldr r1, [pc, #100] @ (8000d7c <HAL_UART_RxCpltCallback+0x98>)
|
|
8000d16: 481a ldr r0, [pc, #104] @ (8000d80 <HAL_UART_RxCpltCallback+0x9c>)
|
|
8000d18: f000 f8ce bl 8000eb8 <handleUARTMessages>
|
|
HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage));
|
|
8000d1c: 2210 movs r2, #16
|
|
8000d1e: 4918 ldr r1, [pc, #96] @ (8000d80 <HAL_UART_RxCpltCallback+0x9c>)
|
|
8000d20: 4816 ldr r0, [pc, #88] @ (8000d7c <HAL_UART_RxCpltCallback+0x98>)
|
|
8000d22: f005 f9e5 bl 80060f0 <HAL_UART_Receive_DMA>
|
|
}
|
|
8000d26: e01c b.n 8000d62 <HAL_UART_RxCpltCallback+0x7e>
|
|
else if (huart->Instance == UART4) {
|
|
8000d28: 687b ldr r3, [r7, #4]
|
|
8000d2a: 681b ldr r3, [r3, #0]
|
|
8000d2c: 4a15 ldr r2, [pc, #84] @ (8000d84 <HAL_UART_RxCpltCallback+0xa0>)
|
|
8000d2e: 4293 cmp r3, r2
|
|
8000d30: d109 bne.n 8000d46 <HAL_UART_RxCpltCallback+0x62>
|
|
handleUARTMessages((uint8_t*)&RX4Msg, &huart4);
|
|
8000d32: 4915 ldr r1, [pc, #84] @ (8000d88 <HAL_UART_RxCpltCallback+0xa4>)
|
|
8000d34: 4815 ldr r0, [pc, #84] @ (8000d8c <HAL_UART_RxCpltCallback+0xa8>)
|
|
8000d36: f000 f8bf bl 8000eb8 <handleUARTMessages>
|
|
HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage));
|
|
8000d3a: 2210 movs r2, #16
|
|
8000d3c: 4913 ldr r1, [pc, #76] @ (8000d8c <HAL_UART_RxCpltCallback+0xa8>)
|
|
8000d3e: 4812 ldr r0, [pc, #72] @ (8000d88 <HAL_UART_RxCpltCallback+0xa4>)
|
|
8000d40: f005 f9d6 bl 80060f0 <HAL_UART_Receive_DMA>
|
|
}
|
|
8000d44: e00d b.n 8000d62 <HAL_UART_RxCpltCallback+0x7e>
|
|
else if (huart->Instance == UART5) {
|
|
8000d46: 687b ldr r3, [r7, #4]
|
|
8000d48: 681b ldr r3, [r3, #0]
|
|
8000d4a: 4a11 ldr r2, [pc, #68] @ (8000d90 <HAL_UART_RxCpltCallback+0xac>)
|
|
8000d4c: 4293 cmp r3, r2
|
|
8000d4e: d108 bne.n 8000d62 <HAL_UART_RxCpltCallback+0x7e>
|
|
handleUARTMessages((uint8_t*)&RX5Msg, &huart5);
|
|
8000d50: 4910 ldr r1, [pc, #64] @ (8000d94 <HAL_UART_RxCpltCallback+0xb0>)
|
|
8000d52: 4811 ldr r0, [pc, #68] @ (8000d98 <HAL_UART_RxCpltCallback+0xb4>)
|
|
8000d54: f000 f8b0 bl 8000eb8 <handleUARTMessages>
|
|
HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage));
|
|
8000d58: 2210 movs r2, #16
|
|
8000d5a: 490f ldr r1, [pc, #60] @ (8000d98 <HAL_UART_RxCpltCallback+0xb4>)
|
|
8000d5c: 480d ldr r0, [pc, #52] @ (8000d94 <HAL_UART_RxCpltCallback+0xb0>)
|
|
8000d5e: f005 f9c7 bl 80060f0 <HAL_UART_Receive_DMA>
|
|
}
|
|
8000d62: bf00 nop
|
|
8000d64: 3708 adds r7, #8
|
|
8000d66: 46bd mov sp, r7
|
|
8000d68: bd80 pop {r7, pc}
|
|
8000d6a: bf00 nop
|
|
8000d6c: 40011000 .word 0x40011000
|
|
8000d70: 200009f0 .word 0x200009f0
|
|
8000d74: 20000230 .word 0x20000230
|
|
8000d78: 40004400 .word 0x40004400
|
|
8000d7c: 20000a38 .word 0x20000a38
|
|
8000d80: 20000240 .word 0x20000240
|
|
8000d84: 40004c00 .word 0x40004c00
|
|
8000d88: 20000960 .word 0x20000960
|
|
8000d8c: 20000250 .word 0x20000250
|
|
8000d90: 40005000 .word 0x40005000
|
|
8000d94: 200009a8 .word 0x200009a8
|
|
8000d98: 20000220 .word 0x20000220
|
|
|
|
08000d9c <HAL_UART_ErrorCallback>:
|
|
|
|
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
|
|
8000d9c: b580 push {r7, lr}
|
|
8000d9e: b082 sub sp, #8
|
|
8000da0: af00 add r7, sp, #0
|
|
8000da2: 6078 str r0, [r7, #4]
|
|
// Restart DMA on error
|
|
if (huart->Instance == USART1) {
|
|
8000da4: 687b ldr r3, [r7, #4]
|
|
8000da6: 681b ldr r3, [r3, #0]
|
|
8000da8: 4a16 ldr r2, [pc, #88] @ (8000e04 <HAL_UART_ErrorCallback+0x68>)
|
|
8000daa: 4293 cmp r3, r2
|
|
8000dac: d105 bne.n 8000dba <HAL_UART_ErrorCallback+0x1e>
|
|
HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage));
|
|
8000dae: 2210 movs r2, #16
|
|
8000db0: 4915 ldr r1, [pc, #84] @ (8000e08 <HAL_UART_ErrorCallback+0x6c>)
|
|
8000db2: 4816 ldr r0, [pc, #88] @ (8000e0c <HAL_UART_ErrorCallback+0x70>)
|
|
8000db4: f005 f99c bl 80060f0 <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage));
|
|
}
|
|
else if (huart->Instance == UART5) {
|
|
HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage));
|
|
}
|
|
}
|
|
8000db8: e01f b.n 8000dfa <HAL_UART_ErrorCallback+0x5e>
|
|
else if (huart->Instance == USART2) {
|
|
8000dba: 687b ldr r3, [r7, #4]
|
|
8000dbc: 681b ldr r3, [r3, #0]
|
|
8000dbe: 4a14 ldr r2, [pc, #80] @ (8000e10 <HAL_UART_ErrorCallback+0x74>)
|
|
8000dc0: 4293 cmp r3, r2
|
|
8000dc2: d105 bne.n 8000dd0 <HAL_UART_ErrorCallback+0x34>
|
|
HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage));
|
|
8000dc4: 2210 movs r2, #16
|
|
8000dc6: 4913 ldr r1, [pc, #76] @ (8000e14 <HAL_UART_ErrorCallback+0x78>)
|
|
8000dc8: 4813 ldr r0, [pc, #76] @ (8000e18 <HAL_UART_ErrorCallback+0x7c>)
|
|
8000dca: f005 f991 bl 80060f0 <HAL_UART_Receive_DMA>
|
|
}
|
|
8000dce: e014 b.n 8000dfa <HAL_UART_ErrorCallback+0x5e>
|
|
else if (huart->Instance == UART4) {
|
|
8000dd0: 687b ldr r3, [r7, #4]
|
|
8000dd2: 681b ldr r3, [r3, #0]
|
|
8000dd4: 4a11 ldr r2, [pc, #68] @ (8000e1c <HAL_UART_ErrorCallback+0x80>)
|
|
8000dd6: 4293 cmp r3, r2
|
|
8000dd8: d105 bne.n 8000de6 <HAL_UART_ErrorCallback+0x4a>
|
|
HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage));
|
|
8000dda: 2210 movs r2, #16
|
|
8000ddc: 4910 ldr r1, [pc, #64] @ (8000e20 <HAL_UART_ErrorCallback+0x84>)
|
|
8000dde: 4811 ldr r0, [pc, #68] @ (8000e24 <HAL_UART_ErrorCallback+0x88>)
|
|
8000de0: f005 f986 bl 80060f0 <HAL_UART_Receive_DMA>
|
|
}
|
|
8000de4: e009 b.n 8000dfa <HAL_UART_ErrorCallback+0x5e>
|
|
else if (huart->Instance == UART5) {
|
|
8000de6: 687b ldr r3, [r7, #4]
|
|
8000de8: 681b ldr r3, [r3, #0]
|
|
8000dea: 4a0f ldr r2, [pc, #60] @ (8000e28 <HAL_UART_ErrorCallback+0x8c>)
|
|
8000dec: 4293 cmp r3, r2
|
|
8000dee: d104 bne.n 8000dfa <HAL_UART_ErrorCallback+0x5e>
|
|
HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage));
|
|
8000df0: 2210 movs r2, #16
|
|
8000df2: 490e ldr r1, [pc, #56] @ (8000e2c <HAL_UART_ErrorCallback+0x90>)
|
|
8000df4: 480e ldr r0, [pc, #56] @ (8000e30 <HAL_UART_ErrorCallback+0x94>)
|
|
8000df6: f005 f97b bl 80060f0 <HAL_UART_Receive_DMA>
|
|
}
|
|
8000dfa: bf00 nop
|
|
8000dfc: 3708 adds r7, #8
|
|
8000dfe: 46bd mov sp, r7
|
|
8000e00: bd80 pop {r7, pc}
|
|
8000e02: bf00 nop
|
|
8000e04: 40011000 .word 0x40011000
|
|
8000e08: 20000230 .word 0x20000230
|
|
8000e0c: 200009f0 .word 0x200009f0
|
|
8000e10: 40004400 .word 0x40004400
|
|
8000e14: 20000240 .word 0x20000240
|
|
8000e18: 20000a38 .word 0x20000a38
|
|
8000e1c: 40004c00 .word 0x40004c00
|
|
8000e20: 20000250 .word 0x20000250
|
|
8000e24: 20000960 .word 0x20000960
|
|
8000e28: 40005000 .word 0x40005000
|
|
8000e2c: 20000220 .word 0x20000220
|
|
8000e30: 200009a8 .word 0x200009a8
|
|
|
|
08000e34 <findBestParent>:
|
|
|
|
|
|
|
|
void findBestParent(){
|
|
8000e34: b580 push {r7, lr}
|
|
8000e36: b084 sub sp, #16
|
|
8000e38: af00 add r7, sp, #0
|
|
//Find least depth parent
|
|
uint16_t least_val = 0xFF;
|
|
8000e3a: 23ff movs r3, #255 @ 0xff
|
|
8000e3c: 81fb strh r3, [r7, #14]
|
|
UART_HandleTypeDef* least_port = NULL;
|
|
8000e3e: 2300 movs r3, #0
|
|
8000e40: 60bb str r3, [r7, #8]
|
|
for(uint8_t i = 0; i < 4; i++){
|
|
8000e42: 2300 movs r3, #0
|
|
8000e44: 71fb strb r3, [r7, #7]
|
|
8000e46: e013 b.n 8000e70 <findBestParent+0x3c>
|
|
if(PORT_DEPTH[i]<least_val){
|
|
8000e48: 79fb ldrb r3, [r7, #7]
|
|
8000e4a: 4a16 ldr r2, [pc, #88] @ (8000ea4 <findBestParent+0x70>)
|
|
8000e4c: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8000e50: 89fa ldrh r2, [r7, #14]
|
|
8000e52: 429a cmp r2, r3
|
|
8000e54: d909 bls.n 8000e6a <findBestParent+0x36>
|
|
least_port = PORTS[i];
|
|
8000e56: 79fb ldrb r3, [r7, #7]
|
|
8000e58: 4a13 ldr r2, [pc, #76] @ (8000ea8 <findBestParent+0x74>)
|
|
8000e5a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8000e5e: 60bb str r3, [r7, #8]
|
|
least_val = PORT_DEPTH[i];
|
|
8000e60: 79fb ldrb r3, [r7, #7]
|
|
8000e62: 4a10 ldr r2, [pc, #64] @ (8000ea4 <findBestParent+0x70>)
|
|
8000e64: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8000e68: 81fb strh r3, [r7, #14]
|
|
for(uint8_t i = 0; i < 4; i++){
|
|
8000e6a: 79fb ldrb r3, [r7, #7]
|
|
8000e6c: 3301 adds r3, #1
|
|
8000e6e: 71fb strb r3, [r7, #7]
|
|
8000e70: 79fb ldrb r3, [r7, #7]
|
|
8000e72: 2b03 cmp r3, #3
|
|
8000e74: d9e8 bls.n 8000e48 <findBestParent+0x14>
|
|
}
|
|
}
|
|
|
|
//Assign if valid
|
|
if(least_val < 0xFF){
|
|
8000e76: 89fb ldrh r3, [r7, #14]
|
|
8000e78: 2bfe cmp r3, #254 @ 0xfe
|
|
8000e7a: d80e bhi.n 8000e9a <findBestParent+0x66>
|
|
PARENT = least_port;
|
|
8000e7c: 4a0b ldr r2, [pc, #44] @ (8000eac <findBestParent+0x78>)
|
|
8000e7e: 68bb ldr r3, [r7, #8]
|
|
8000e80: 6013 str r3, [r2, #0]
|
|
DEPTH = least_val + 1;
|
|
8000e82: 89fb ldrh r3, [r7, #14]
|
|
8000e84: 3301 adds r3, #1
|
|
8000e86: b29a uxth r2, r3
|
|
8000e88: 4b09 ldr r3, [pc, #36] @ (8000eb0 <findBestParent+0x7c>)
|
|
8000e8a: 801a strh r2, [r3, #0]
|
|
MODE = MODE_ACTIVE;
|
|
8000e8c: 4b09 ldr r3, [pc, #36] @ (8000eb4 <findBestParent+0x80>)
|
|
8000e8e: 2202 movs r2, #2
|
|
8000e90: 701a strb r2, [r3, #0]
|
|
HAL_Delay(500);
|
|
8000e92: f44f 70fa mov.w r0, #500 @ 0x1f4
|
|
8000e96: f000 ffad bl 8001df4 <HAL_Delay>
|
|
}
|
|
}
|
|
8000e9a: bf00 nop
|
|
8000e9c: 3710 adds r7, #16
|
|
8000e9e: 46bd mov sp, r7
|
|
8000ea0: bd80 pop {r7, pc}
|
|
8000ea2: bf00 nop
|
|
8000ea4: 20000078 .word 0x20000078
|
|
8000ea8: 20000080 .word 0x20000080
|
|
8000eac: 20000264 .word 0x20000264
|
|
8000eb0: 20000260 .word 0x20000260
|
|
8000eb4: 2000028a .word 0x2000028a
|
|
|
|
08000eb8 <handleUARTMessages>:
|
|
|
|
// Called when UART RX interrupt completes
|
|
void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender) {
|
|
8000eb8: b590 push {r4, r7, lr}
|
|
8000eba: b08b sub sp, #44 @ 0x2c
|
|
8000ebc: af00 add r7, sp, #0
|
|
8000ebe: 6078 str r0, [r7, #4]
|
|
8000ec0: 6039 str r1, [r7, #0]
|
|
UARTMessage msg;
|
|
UARTMessage reply;
|
|
|
|
// Parse incoming message into struct
|
|
memcpy(&msg, data, sizeof(UARTMessage));
|
|
8000ec2: 687b ldr r3, [r7, #4]
|
|
8000ec4: f107 0418 add.w r4, r7, #24
|
|
8000ec8: 6818 ldr r0, [r3, #0]
|
|
8000eca: 6859 ldr r1, [r3, #4]
|
|
8000ecc: 689a ldr r2, [r3, #8]
|
|
8000ece: 68db ldr r3, [r3, #12]
|
|
8000ed0: c40f stmia r4!, {r0, r1, r2, r3}
|
|
|
|
switch(msg.TYPE) {
|
|
8000ed2: 8b7b ldrh r3, [r7, #26]
|
|
8000ed4: 2bff cmp r3, #255 @ 0xff
|
|
8000ed6: d026 beq.n 8000f26 <handleUARTMessages+0x6e>
|
|
8000ed8: 2bff cmp r3, #255 @ 0xff
|
|
8000eda: dc6e bgt.n 8000fba <handleUARTMessages+0x102>
|
|
8000edc: 2baa cmp r3, #170 @ 0xaa
|
|
8000ede: d002 beq.n 8000ee6 <handleUARTMessages+0x2e>
|
|
8000ee0: 2bee cmp r3, #238 @ 0xee
|
|
8000ee2: d03a beq.n 8000f5a <handleUARTMessages+0xa2>
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
8000ee4: e069 b.n 8000fba <handleUARTMessages+0x102>
|
|
if(sender == &huart5) {
|
|
8000ee6: 683b ldr r3, [r7, #0]
|
|
8000ee8: 4a39 ldr r2, [pc, #228] @ (8000fd0 <handleUARTMessages+0x118>)
|
|
8000eea: 4293 cmp r3, r2
|
|
8000eec: d103 bne.n 8000ef6 <handleUARTMessages+0x3e>
|
|
PORT_DEPTH[0] = msg.DEPTH;
|
|
8000eee: 8b3a ldrh r2, [r7, #24]
|
|
8000ef0: 4b38 ldr r3, [pc, #224] @ (8000fd4 <handleUARTMessages+0x11c>)
|
|
8000ef2: 801a strh r2, [r3, #0]
|
|
break;
|
|
8000ef4: e063 b.n 8000fbe <handleUARTMessages+0x106>
|
|
} else if(sender == &huart1) {
|
|
8000ef6: 683b ldr r3, [r7, #0]
|
|
8000ef8: 4a37 ldr r2, [pc, #220] @ (8000fd8 <handleUARTMessages+0x120>)
|
|
8000efa: 4293 cmp r3, r2
|
|
8000efc: d103 bne.n 8000f06 <handleUARTMessages+0x4e>
|
|
PORT_DEPTH[1] = msg.DEPTH;
|
|
8000efe: 8b3a ldrh r2, [r7, #24]
|
|
8000f00: 4b34 ldr r3, [pc, #208] @ (8000fd4 <handleUARTMessages+0x11c>)
|
|
8000f02: 805a strh r2, [r3, #2]
|
|
break;
|
|
8000f04: e05b b.n 8000fbe <handleUARTMessages+0x106>
|
|
} else if(sender == &huart2) {
|
|
8000f06: 683b ldr r3, [r7, #0]
|
|
8000f08: 4a34 ldr r2, [pc, #208] @ (8000fdc <handleUARTMessages+0x124>)
|
|
8000f0a: 4293 cmp r3, r2
|
|
8000f0c: d103 bne.n 8000f16 <handleUARTMessages+0x5e>
|
|
PORT_DEPTH[2] = msg.DEPTH;
|
|
8000f0e: 8b3a ldrh r2, [r7, #24]
|
|
8000f10: 4b30 ldr r3, [pc, #192] @ (8000fd4 <handleUARTMessages+0x11c>)
|
|
8000f12: 809a strh r2, [r3, #4]
|
|
break;
|
|
8000f14: e053 b.n 8000fbe <handleUARTMessages+0x106>
|
|
} else if(sender == &huart4) {
|
|
8000f16: 683b ldr r3, [r7, #0]
|
|
8000f18: 4a31 ldr r2, [pc, #196] @ (8000fe0 <handleUARTMessages+0x128>)
|
|
8000f1a: 4293 cmp r3, r2
|
|
8000f1c: d14f bne.n 8000fbe <handleUARTMessages+0x106>
|
|
PORT_DEPTH[3] = msg.DEPTH;
|
|
8000f1e: 8b3a ldrh r2, [r7, #24]
|
|
8000f20: 4b2c ldr r3, [pc, #176] @ (8000fd4 <handleUARTMessages+0x11c>)
|
|
8000f22: 80da strh r2, [r3, #6]
|
|
break;
|
|
8000f24: e04b b.n 8000fbe <handleUARTMessages+0x106>
|
|
if(MODE!=MODE_INACTIVE){
|
|
8000f26: 4b2f ldr r3, [pc, #188] @ (8000fe4 <handleUARTMessages+0x12c>)
|
|
8000f28: 781b ldrb r3, [r3, #0]
|
|
8000f2a: b2db uxtb r3, r3
|
|
8000f2c: 2b00 cmp r3, #0
|
|
8000f2e: d048 beq.n 8000fc2 <handleUARTMessages+0x10a>
|
|
reply.TYPE = 0xAA;
|
|
8000f30: 23aa movs r3, #170 @ 0xaa
|
|
8000f32: 817b strh r3, [r7, #10]
|
|
reply.DEPTH = DEPTH; // use your local DEPTH
|
|
8000f34: 4b2c ldr r3, [pc, #176] @ (8000fe8 <handleUARTMessages+0x130>)
|
|
8000f36: 881b ldrh r3, [r3, #0]
|
|
8000f38: 813b strh r3, [r7, #8]
|
|
memset(reply.KEYPRESS, 0, sizeof(reply.KEYPRESS));
|
|
8000f3a: f107 0308 add.w r3, r7, #8
|
|
8000f3e: 3304 adds r3, #4
|
|
8000f40: 220c movs r2, #12
|
|
8000f42: 2100 movs r1, #0
|
|
8000f44: 4618 mov r0, r3
|
|
8000f46: f009 ff7b bl 800ae40 <memset>
|
|
HAL_UART_Transmit_DMA(sender, (uint8_t*)&reply, sizeof(reply));
|
|
8000f4a: f107 0308 add.w r3, r7, #8
|
|
8000f4e: 2210 movs r2, #16
|
|
8000f50: 4619 mov r1, r3
|
|
8000f52: 6838 ldr r0, [r7, #0]
|
|
8000f54: f005 f850 bl 8005ff8 <HAL_UART_Transmit_DMA>
|
|
break;
|
|
8000f58: e033 b.n 8000fc2 <handleUARTMessages+0x10a>
|
|
if(sender == &huart5) {
|
|
8000f5a: 683b ldr r3, [r7, #0]
|
|
8000f5c: 4a1c ldr r2, [pc, #112] @ (8000fd0 <handleUARTMessages+0x118>)
|
|
8000f5e: 4293 cmp r3, r2
|
|
8000f60: d107 bne.n 8000f72 <handleUARTMessages+0xba>
|
|
pq_push(&huart5q, msg.KEYPRESS);
|
|
8000f62: f107 0318 add.w r3, r7, #24
|
|
8000f66: 3304 adds r3, #4
|
|
8000f68: 4619 mov r1, r3
|
|
8000f6a: 4820 ldr r0, [pc, #128] @ (8000fec <handleUARTMessages+0x134>)
|
|
8000f6c: f7ff fc72 bl 8000854 <pq_push>
|
|
break;
|
|
8000f70: e029 b.n 8000fc6 <handleUARTMessages+0x10e>
|
|
} else if(sender == &huart1) {
|
|
8000f72: 683b ldr r3, [r7, #0]
|
|
8000f74: 4a18 ldr r2, [pc, #96] @ (8000fd8 <handleUARTMessages+0x120>)
|
|
8000f76: 4293 cmp r3, r2
|
|
8000f78: d107 bne.n 8000f8a <handleUARTMessages+0xd2>
|
|
pq_push(&huart1q, msg.KEYPRESS);
|
|
8000f7a: f107 0318 add.w r3, r7, #24
|
|
8000f7e: 3304 adds r3, #4
|
|
8000f80: 4619 mov r1, r3
|
|
8000f82: 481b ldr r0, [pc, #108] @ (8000ff0 <handleUARTMessages+0x138>)
|
|
8000f84: f7ff fc66 bl 8000854 <pq_push>
|
|
break;
|
|
8000f88: e01d b.n 8000fc6 <handleUARTMessages+0x10e>
|
|
} else if(sender == &huart2) {
|
|
8000f8a: 683b ldr r3, [r7, #0]
|
|
8000f8c: 4a13 ldr r2, [pc, #76] @ (8000fdc <handleUARTMessages+0x124>)
|
|
8000f8e: 4293 cmp r3, r2
|
|
8000f90: d107 bne.n 8000fa2 <handleUARTMessages+0xea>
|
|
pq_push(&huart2q, msg.KEYPRESS);
|
|
8000f92: f107 0318 add.w r3, r7, #24
|
|
8000f96: 3304 adds r3, #4
|
|
8000f98: 4619 mov r1, r3
|
|
8000f9a: 4816 ldr r0, [pc, #88] @ (8000ff4 <handleUARTMessages+0x13c>)
|
|
8000f9c: f7ff fc5a bl 8000854 <pq_push>
|
|
break;
|
|
8000fa0: e011 b.n 8000fc6 <handleUARTMessages+0x10e>
|
|
} else if(sender == &huart4) {
|
|
8000fa2: 683b ldr r3, [r7, #0]
|
|
8000fa4: 4a0e ldr r2, [pc, #56] @ (8000fe0 <handleUARTMessages+0x128>)
|
|
8000fa6: 4293 cmp r3, r2
|
|
8000fa8: d10d bne.n 8000fc6 <handleUARTMessages+0x10e>
|
|
pq_push(&huart4q, msg.KEYPRESS);
|
|
8000faa: f107 0318 add.w r3, r7, #24
|
|
8000fae: 3304 adds r3, #4
|
|
8000fb0: 4619 mov r1, r3
|
|
8000fb2: 4811 ldr r0, [pc, #68] @ (8000ff8 <handleUARTMessages+0x140>)
|
|
8000fb4: f7ff fc4e bl 8000854 <pq_push>
|
|
break;
|
|
8000fb8: e005 b.n 8000fc6 <handleUARTMessages+0x10e>
|
|
break;
|
|
8000fba: bf00 nop
|
|
8000fbc: e004 b.n 8000fc8 <handleUARTMessages+0x110>
|
|
break;
|
|
8000fbe: bf00 nop
|
|
8000fc0: e002 b.n 8000fc8 <handleUARTMessages+0x110>
|
|
break;
|
|
8000fc2: bf00 nop
|
|
8000fc4: e000 b.n 8000fc8 <handleUARTMessages+0x110>
|
|
break;
|
|
8000fc6: bf00 nop
|
|
|
|
}
|
|
}
|
|
8000fc8: bf00 nop
|
|
8000fca: 372c adds r7, #44 @ 0x2c
|
|
8000fcc: 46bd mov sp, r7
|
|
8000fce: bd90 pop {r4, r7, pc}
|
|
8000fd0: 200009a8 .word 0x200009a8
|
|
8000fd4: 20000078 .word 0x20000078
|
|
8000fd8: 200009f0 .word 0x200009f0
|
|
8000fdc: 20000a38 .word 0x20000a38
|
|
8000fe0: 20000960 .word 0x20000960
|
|
8000fe4: 2000028a .word 0x2000028a
|
|
8000fe8: 20000260 .word 0x20000260
|
|
8000fec: 2000074c .word 0x2000074c
|
|
8000ff0: 200002c0 .word 0x200002c0
|
|
8000ff4: 20000444 .word 0x20000444
|
|
8000ff8: 200005c8 .word 0x200005c8
|
|
|
|
08000ffc <addUSBReport>:
|
|
|
|
|
|
void addUSBReport(uint8_t usageID){
|
|
8000ffc: b480 push {r7}
|
|
8000ffe: b085 sub sp, #20
|
|
8001000: af00 add r7, sp, #0
|
|
8001002: 4603 mov r3, r0
|
|
8001004: 71fb strb r3, [r7, #7]
|
|
if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds
|
|
8001006: 79fb ldrb r3, [r7, #7]
|
|
8001008: 2b03 cmp r3, #3
|
|
800100a: d922 bls.n 8001052 <addUSBReport+0x56>
|
|
800100c: 79fb ldrb r3, [r7, #7]
|
|
800100e: 2b73 cmp r3, #115 @ 0x73
|
|
8001010: d81f bhi.n 8001052 <addUSBReport+0x56>
|
|
uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit
|
|
8001012: 79fb ldrb r3, [r7, #7]
|
|
8001014: b29b uxth r3, r3
|
|
8001016: 3b04 subs r3, #4
|
|
8001018: 81fb strh r3, [r7, #14]
|
|
uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array
|
|
800101a: 89fb ldrh r3, [r7, #14]
|
|
800101c: 08db lsrs r3, r3, #3
|
|
800101e: b29b uxth r3, r3
|
|
8001020: 737b strb r3, [r7, #13]
|
|
uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset
|
|
8001022: 89fb ldrh r3, [r7, #14]
|
|
8001024: b2db uxtb r3, r3
|
|
8001026: f003 0307 and.w r3, r3, #7
|
|
800102a: 733b strb r3, [r7, #12]
|
|
REPORT.KEYPRESS[byte_index] |= (1 << bit_offset);
|
|
800102c: 7b7b ldrb r3, [r7, #13]
|
|
800102e: 4a0c ldr r2, [pc, #48] @ (8001060 <addUSBReport+0x64>)
|
|
8001030: 4413 add r3, r2
|
|
8001032: 789b ldrb r3, [r3, #2]
|
|
8001034: b25a sxtb r2, r3
|
|
8001036: 7b3b ldrb r3, [r7, #12]
|
|
8001038: 2101 movs r1, #1
|
|
800103a: fa01 f303 lsl.w r3, r1, r3
|
|
800103e: b25b sxtb r3, r3
|
|
8001040: 4313 orrs r3, r2
|
|
8001042: b25a sxtb r2, r3
|
|
8001044: 7b7b ldrb r3, [r7, #13]
|
|
8001046: b2d1 uxtb r1, r2
|
|
8001048: 4a05 ldr r2, [pc, #20] @ (8001060 <addUSBReport+0x64>)
|
|
800104a: 4413 add r3, r2
|
|
800104c: 460a mov r2, r1
|
|
800104e: 709a strb r2, [r3, #2]
|
|
8001050: e000 b.n 8001054 <addUSBReport+0x58>
|
|
if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds
|
|
8001052: bf00 nop
|
|
}
|
|
8001054: 3714 adds r7, #20
|
|
8001056: 46bd mov sp, r7
|
|
8001058: f85d 7b04 ldr.w r7, [sp], #4
|
|
800105c: 4770 bx lr
|
|
800105e: bf00 nop
|
|
8001060: 20000210 .word 0x20000210
|
|
|
|
08001064 <matrixScan>:
|
|
|
|
void matrixScan(void){
|
|
8001064: b580 push {r7, lr}
|
|
8001066: b082 sub sp, #8
|
|
8001068: af00 add r7, sp, #0
|
|
|
|
for (uint8_t col = 0; col < COL; col++){
|
|
800106a: 2300 movs r3, #0
|
|
800106c: 71fb strb r3, [r7, #7]
|
|
800106e: e05f b.n 8001130 <matrixScan+0xcc>
|
|
HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET);
|
|
8001070: 79fb ldrb r3, [r7, #7]
|
|
8001072: 4a33 ldr r2, [pc, #204] @ (8001140 <matrixScan+0xdc>)
|
|
8001074: f852 0033 ldr.w r0, [r2, r3, lsl #3]
|
|
8001078: 79fb ldrb r3, [r7, #7]
|
|
800107a: 4a31 ldr r2, [pc, #196] @ (8001140 <matrixScan+0xdc>)
|
|
800107c: 00db lsls r3, r3, #3
|
|
800107e: 4413 add r3, r2
|
|
8001080: 889b ldrh r3, [r3, #4]
|
|
8001082: 2201 movs r2, #1
|
|
8001084: 4619 mov r1, r3
|
|
8001086: f001 fd99 bl 8002bbc <HAL_GPIO_WritePin>
|
|
HAL_Delay(1);
|
|
800108a: 2001 movs r0, #1
|
|
800108c: f000 feb2 bl 8001df4 <HAL_Delay>
|
|
for(uint8_t row = 0; row < ROW; row++){
|
|
8001090: 2300 movs r3, #0
|
|
8001092: 71bb strb r3, [r7, #6]
|
|
8001094: e039 b.n 800110a <matrixScan+0xa6>
|
|
uint8_t new_key = HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN);
|
|
8001096: 79bb ldrb r3, [r7, #6]
|
|
8001098: 4a2a ldr r2, [pc, #168] @ (8001144 <matrixScan+0xe0>)
|
|
800109a: f852 2033 ldr.w r2, [r2, r3, lsl #3]
|
|
800109e: 79bb ldrb r3, [r7, #6]
|
|
80010a0: 4928 ldr r1, [pc, #160] @ (8001144 <matrixScan+0xe0>)
|
|
80010a2: 00db lsls r3, r3, #3
|
|
80010a4: 440b add r3, r1
|
|
80010a6: 889b ldrh r3, [r3, #4]
|
|
80010a8: 4619 mov r1, r3
|
|
80010aa: 4610 mov r0, r2
|
|
80010ac: f001 fd6e bl 8002b8c <HAL_GPIO_ReadPin>
|
|
80010b0: 4603 mov r3, r0
|
|
80010b2: 717b strb r3, [r7, #5]
|
|
if(new_key != KEYSTATE[row][col]){
|
|
80010b4: 79ba ldrb r2, [r7, #6]
|
|
80010b6: 79f9 ldrb r1, [r7, #7]
|
|
80010b8: 4823 ldr r0, [pc, #140] @ (8001148 <matrixScan+0xe4>)
|
|
80010ba: 4613 mov r3, r2
|
|
80010bc: 009b lsls r3, r3, #2
|
|
80010be: 4413 add r3, r2
|
|
80010c0: 4403 add r3, r0
|
|
80010c2: 440b add r3, r1
|
|
80010c4: 781b ldrb r3, [r3, #0]
|
|
80010c6: 797a ldrb r2, [r7, #5]
|
|
80010c8: 429a cmp r2, r3
|
|
80010ca: d00c beq.n 80010e6 <matrixScan+0x82>
|
|
KEYSTATE_CHANGED_FLAG = 1;
|
|
80010cc: 4b1f ldr r3, [pc, #124] @ (800114c <matrixScan+0xe8>)
|
|
80010ce: 2201 movs r2, #1
|
|
80010d0: 701a strb r2, [r3, #0]
|
|
KEYSTATE[row][col] = new_key;
|
|
80010d2: 79ba ldrb r2, [r7, #6]
|
|
80010d4: 79f9 ldrb r1, [r7, #7]
|
|
80010d6: 481c ldr r0, [pc, #112] @ (8001148 <matrixScan+0xe4>)
|
|
80010d8: 4613 mov r3, r2
|
|
80010da: 009b lsls r3, r3, #2
|
|
80010dc: 4413 add r3, r2
|
|
80010de: 4403 add r3, r0
|
|
80010e0: 440b add r3, r1
|
|
80010e2: 797a ldrb r2, [r7, #5]
|
|
80010e4: 701a strb r2, [r3, #0]
|
|
}
|
|
if(new_key){
|
|
80010e6: 797b ldrb r3, [r7, #5]
|
|
80010e8: 2b00 cmp r3, #0
|
|
80010ea: d00b beq.n 8001104 <matrixScan+0xa0>
|
|
addUSBReport(KEYCODES[row][col]);
|
|
80010ec: 79ba ldrb r2, [r7, #6]
|
|
80010ee: 79f9 ldrb r1, [r7, #7]
|
|
80010f0: 4817 ldr r0, [pc, #92] @ (8001150 <matrixScan+0xec>)
|
|
80010f2: 4613 mov r3, r2
|
|
80010f4: 009b lsls r3, r3, #2
|
|
80010f6: 4413 add r3, r2
|
|
80010f8: 4403 add r3, r0
|
|
80010fa: 440b add r3, r1
|
|
80010fc: 781b ldrb r3, [r3, #0]
|
|
80010fe: 4618 mov r0, r3
|
|
8001100: f7ff ff7c bl 8000ffc <addUSBReport>
|
|
for(uint8_t row = 0; row < ROW; row++){
|
|
8001104: 79bb ldrb r3, [r7, #6]
|
|
8001106: 3301 adds r3, #1
|
|
8001108: 71bb strb r3, [r7, #6]
|
|
800110a: 79bb ldrb r3, [r7, #6]
|
|
800110c: 2b05 cmp r3, #5
|
|
800110e: d9c2 bls.n 8001096 <matrixScan+0x32>
|
|
}
|
|
}
|
|
HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET);
|
|
8001110: 79fb ldrb r3, [r7, #7]
|
|
8001112: 4a0b ldr r2, [pc, #44] @ (8001140 <matrixScan+0xdc>)
|
|
8001114: f852 0033 ldr.w r0, [r2, r3, lsl #3]
|
|
8001118: 79fb ldrb r3, [r7, #7]
|
|
800111a: 4a09 ldr r2, [pc, #36] @ (8001140 <matrixScan+0xdc>)
|
|
800111c: 00db lsls r3, r3, #3
|
|
800111e: 4413 add r3, r2
|
|
8001120: 889b ldrh r3, [r3, #4]
|
|
8001122: 2200 movs r2, #0
|
|
8001124: 4619 mov r1, r3
|
|
8001126: f001 fd49 bl 8002bbc <HAL_GPIO_WritePin>
|
|
for (uint8_t col = 0; col < COL; col++){
|
|
800112a: 79fb ldrb r3, [r7, #7]
|
|
800112c: 3301 adds r3, #1
|
|
800112e: 71fb strb r3, [r7, #7]
|
|
8001130: 79fb ldrb r3, [r7, #7]
|
|
8001132: 2b04 cmp r3, #4
|
|
8001134: d99c bls.n 8001070 <matrixScan+0xc>
|
|
}
|
|
|
|
}
|
|
8001136: bf00 nop
|
|
8001138: bf00 nop
|
|
800113a: 3708 adds r7, #8
|
|
800113c: 46bd mov sp, r7
|
|
800113e: bd80 pop {r7, pc}
|
|
8001140: 20000030 .word 0x20000030
|
|
8001144: 20000000 .word 0x20000000
|
|
8001148: 2000026c .word 0x2000026c
|
|
800114c: 20000268 .word 0x20000268
|
|
8001150: 20000058 .word 0x20000058
|
|
|
|
08001154 <resetReport>:
|
|
}
|
|
}
|
|
LAST_ENCODER_COUNT = cnt;
|
|
}
|
|
|
|
void resetReport(void){
|
|
8001154: b580 push {r7, lr}
|
|
8001156: af00 add r7, sp, #0
|
|
memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS));
|
|
8001158: 220c movs r2, #12
|
|
800115a: 2100 movs r1, #0
|
|
800115c: 4802 ldr r0, [pc, #8] @ (8001168 <resetReport+0x14>)
|
|
800115e: f009 fe6f bl 800ae40 <memset>
|
|
}
|
|
8001162: bf00 nop
|
|
8001164: bd80 pop {r7, pc}
|
|
8001166: bf00 nop
|
|
8001168: 20000212 .word 0x20000212
|
|
|
|
0800116c <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
800116c: b480 push {r7}
|
|
800116e: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8001170: b672 cpsid i
|
|
}
|
|
8001172: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8001174: bf00 nop
|
|
8001176: e7fd b.n 8001174 <Error_Handler+0x8>
|
|
|
|
08001178 <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8001178: b480 push {r7}
|
|
800117a: b083 sub sp, #12
|
|
800117c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
800117e: 2300 movs r3, #0
|
|
8001180: 607b str r3, [r7, #4]
|
|
8001182: 4b10 ldr r3, [pc, #64] @ (80011c4 <HAL_MspInit+0x4c>)
|
|
8001184: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001186: 4a0f ldr r2, [pc, #60] @ (80011c4 <HAL_MspInit+0x4c>)
|
|
8001188: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
800118c: 6453 str r3, [r2, #68] @ 0x44
|
|
800118e: 4b0d ldr r3, [pc, #52] @ (80011c4 <HAL_MspInit+0x4c>)
|
|
8001190: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001192: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8001196: 607b str r3, [r7, #4]
|
|
8001198: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800119a: 2300 movs r3, #0
|
|
800119c: 603b str r3, [r7, #0]
|
|
800119e: 4b09 ldr r3, [pc, #36] @ (80011c4 <HAL_MspInit+0x4c>)
|
|
80011a0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80011a2: 4a08 ldr r2, [pc, #32] @ (80011c4 <HAL_MspInit+0x4c>)
|
|
80011a4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80011a8: 6413 str r3, [r2, #64] @ 0x40
|
|
80011aa: 4b06 ldr r3, [pc, #24] @ (80011c4 <HAL_MspInit+0x4c>)
|
|
80011ac: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80011ae: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80011b2: 603b str r3, [r7, #0]
|
|
80011b4: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
80011b6: bf00 nop
|
|
80011b8: 370c adds r7, #12
|
|
80011ba: 46bd mov sp, r7
|
|
80011bc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80011c0: 4770 bx lr
|
|
80011c2: bf00 nop
|
|
80011c4: 40023800 .word 0x40023800
|
|
|
|
080011c8 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
80011c8: b480 push {r7}
|
|
80011ca: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
80011cc: bf00 nop
|
|
80011ce: e7fd b.n 80011cc <NMI_Handler+0x4>
|
|
|
|
080011d0 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
80011d0: b480 push {r7}
|
|
80011d2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
80011d4: bf00 nop
|
|
80011d6: e7fd b.n 80011d4 <HardFault_Handler+0x4>
|
|
|
|
080011d8 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
80011d8: b480 push {r7}
|
|
80011da: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
80011dc: bf00 nop
|
|
80011de: e7fd b.n 80011dc <MemManage_Handler+0x4>
|
|
|
|
080011e0 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pre-fetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
80011e0: b480 push {r7}
|
|
80011e2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
80011e4: bf00 nop
|
|
80011e6: e7fd b.n 80011e4 <BusFault_Handler+0x4>
|
|
|
|
080011e8 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
80011e8: b480 push {r7}
|
|
80011ea: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
80011ec: bf00 nop
|
|
80011ee: e7fd b.n 80011ec <UsageFault_Handler+0x4>
|
|
|
|
080011f0 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
80011f0: b480 push {r7}
|
|
80011f2: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
80011f4: bf00 nop
|
|
80011f6: 46bd mov sp, r7
|
|
80011f8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80011fc: 4770 bx lr
|
|
|
|
080011fe <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
80011fe: b480 push {r7}
|
|
8001200: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8001202: bf00 nop
|
|
8001204: 46bd mov sp, r7
|
|
8001206: f85d 7b04 ldr.w r7, [sp], #4
|
|
800120a: 4770 bx lr
|
|
|
|
0800120c <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
800120c: b480 push {r7}
|
|
800120e: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8001210: bf00 nop
|
|
8001212: 46bd mov sp, r7
|
|
8001214: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001218: 4770 bx lr
|
|
|
|
0800121a <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
800121a: b580 push {r7, lr}
|
|
800121c: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
800121e: f000 fdc9 bl 8001db4 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8001222: bf00 nop
|
|
8001224: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001228 <DMA1_Stream0_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 stream0 global interrupt.
|
|
*/
|
|
void DMA1_Stream0_IRQHandler(void)
|
|
{
|
|
8001228: b580 push {r7, lr}
|
|
800122a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Stream0_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_uart5_rx);
|
|
800122c: 4802 ldr r0, [pc, #8] @ (8001238 <DMA1_Stream0_IRQHandler+0x10>)
|
|
800122e: f001 f8af bl 8002390 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Stream0_IRQn 1 */
|
|
}
|
|
8001232: bf00 nop
|
|
8001234: bd80 pop {r7, pc}
|
|
8001236: bf00 nop
|
|
8001238: 20000b40 .word 0x20000b40
|
|
|
|
0800123c <DMA1_Stream2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 stream2 global interrupt.
|
|
*/
|
|
void DMA1_Stream2_IRQHandler(void)
|
|
{
|
|
800123c: b580 push {r7, lr}
|
|
800123e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Stream2_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Stream2_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_uart4_rx);
|
|
8001240: 4802 ldr r0, [pc, #8] @ (800124c <DMA1_Stream2_IRQHandler+0x10>)
|
|
8001242: f001 f8a5 bl 8002390 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Stream2_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Stream2_IRQn 1 */
|
|
}
|
|
8001246: bf00 nop
|
|
8001248: bd80 pop {r7, pc}
|
|
800124a: bf00 nop
|
|
800124c: 20000a80 .word 0x20000a80
|
|
|
|
08001250 <DMA1_Stream4_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 stream4 global interrupt.
|
|
*/
|
|
void DMA1_Stream4_IRQHandler(void)
|
|
{
|
|
8001250: b580 push {r7, lr}
|
|
8001252: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Stream4_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Stream4_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_uart4_tx);
|
|
8001254: 4802 ldr r0, [pc, #8] @ (8001260 <DMA1_Stream4_IRQHandler+0x10>)
|
|
8001256: f001 f89b bl 8002390 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Stream4_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Stream4_IRQn 1 */
|
|
}
|
|
800125a: bf00 nop
|
|
800125c: bd80 pop {r7, pc}
|
|
800125e: bf00 nop
|
|
8001260: 20000ae0 .word 0x20000ae0
|
|
|
|
08001264 <DMA1_Stream5_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 stream5 global interrupt.
|
|
*/
|
|
void DMA1_Stream5_IRQHandler(void)
|
|
{
|
|
8001264: b580 push {r7, lr}
|
|
8001266: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Stream5_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_usart2_rx);
|
|
8001268: 4802 ldr r0, [pc, #8] @ (8001274 <DMA1_Stream5_IRQHandler+0x10>)
|
|
800126a: f001 f891 bl 8002390 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Stream5_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Stream5_IRQn 1 */
|
|
}
|
|
800126e: bf00 nop
|
|
8001270: bd80 pop {r7, pc}
|
|
8001272: bf00 nop
|
|
8001274: 20000cc0 .word 0x20000cc0
|
|
|
|
08001278 <DMA1_Stream6_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 stream6 global interrupt.
|
|
*/
|
|
void DMA1_Stream6_IRQHandler(void)
|
|
{
|
|
8001278: b580 push {r7, lr}
|
|
800127a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Stream6_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Stream6_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_usart2_tx);
|
|
800127c: 4802 ldr r0, [pc, #8] @ (8001288 <DMA1_Stream6_IRQHandler+0x10>)
|
|
800127e: f001 f887 bl 8002390 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Stream6_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Stream6_IRQn 1 */
|
|
}
|
|
8001282: bf00 nop
|
|
8001284: bd80 pop {r7, pc}
|
|
8001286: bf00 nop
|
|
8001288: 20000d20 .word 0x20000d20
|
|
|
|
0800128c <USART1_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USART1 global interrupt.
|
|
*/
|
|
void USART1_IRQHandler(void)
|
|
{
|
|
800128c: b580 push {r7, lr}
|
|
800128e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USART1_IRQn 0 */
|
|
|
|
/* USER CODE END USART1_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart1);
|
|
8001290: 4802 ldr r0, [pc, #8] @ (800129c <USART1_IRQHandler+0x10>)
|
|
8001292: f004 ff53 bl 800613c <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN USART1_IRQn 1 */
|
|
|
|
/* USER CODE END USART1_IRQn 1 */
|
|
}
|
|
8001296: bf00 nop
|
|
8001298: bd80 pop {r7, pc}
|
|
800129a: bf00 nop
|
|
800129c: 200009f0 .word 0x200009f0
|
|
|
|
080012a0 <USART2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USART2 global interrupt.
|
|
*/
|
|
void USART2_IRQHandler(void)
|
|
{
|
|
80012a0: b580 push {r7, lr}
|
|
80012a2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USART2_IRQn 0 */
|
|
|
|
/* USER CODE END USART2_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart2);
|
|
80012a4: 4802 ldr r0, [pc, #8] @ (80012b0 <USART2_IRQHandler+0x10>)
|
|
80012a6: f004 ff49 bl 800613c <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN USART2_IRQn 1 */
|
|
|
|
/* USER CODE END USART2_IRQn 1 */
|
|
}
|
|
80012aa: bf00 nop
|
|
80012ac: bd80 pop {r7, pc}
|
|
80012ae: bf00 nop
|
|
80012b0: 20000a38 .word 0x20000a38
|
|
|
|
080012b4 <DMA1_Stream7_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 stream7 global interrupt.
|
|
*/
|
|
void DMA1_Stream7_IRQHandler(void)
|
|
{
|
|
80012b4: b580 push {r7, lr}
|
|
80012b6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Stream7_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Stream7_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_uart5_tx);
|
|
80012b8: 4802 ldr r0, [pc, #8] @ (80012c4 <DMA1_Stream7_IRQHandler+0x10>)
|
|
80012ba: f001 f869 bl 8002390 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Stream7_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Stream7_IRQn 1 */
|
|
}
|
|
80012be: bf00 nop
|
|
80012c0: bd80 pop {r7, pc}
|
|
80012c2: bf00 nop
|
|
80012c4: 20000ba0 .word 0x20000ba0
|
|
|
|
080012c8 <UART4_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles UART4 global interrupt.
|
|
*/
|
|
void UART4_IRQHandler(void)
|
|
{
|
|
80012c8: b580 push {r7, lr}
|
|
80012ca: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UART4_IRQn 0 */
|
|
|
|
/* USER CODE END UART4_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart4);
|
|
80012cc: 4802 ldr r0, [pc, #8] @ (80012d8 <UART4_IRQHandler+0x10>)
|
|
80012ce: f004 ff35 bl 800613c <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN UART4_IRQn 1 */
|
|
|
|
/* USER CODE END UART4_IRQn 1 */
|
|
}
|
|
80012d2: bf00 nop
|
|
80012d4: bd80 pop {r7, pc}
|
|
80012d6: bf00 nop
|
|
80012d8: 20000960 .word 0x20000960
|
|
|
|
080012dc <UART5_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles UART5 global interrupt.
|
|
*/
|
|
void UART5_IRQHandler(void)
|
|
{
|
|
80012dc: b580 push {r7, lr}
|
|
80012de: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UART5_IRQn 0 */
|
|
|
|
/* USER CODE END UART5_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart5);
|
|
80012e0: 4802 ldr r0, [pc, #8] @ (80012ec <UART5_IRQHandler+0x10>)
|
|
80012e2: f004 ff2b bl 800613c <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN UART5_IRQn 1 */
|
|
|
|
/* USER CODE END UART5_IRQn 1 */
|
|
}
|
|
80012e6: bf00 nop
|
|
80012e8: bd80 pop {r7, pc}
|
|
80012ea: bf00 nop
|
|
80012ec: 200009a8 .word 0x200009a8
|
|
|
|
080012f0 <DMA2_Stream2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA2 stream2 global interrupt.
|
|
*/
|
|
void DMA2_Stream2_IRQHandler(void)
|
|
{
|
|
80012f0: b580 push {r7, lr}
|
|
80012f2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA2_Stream2_IRQn 0 */
|
|
|
|
/* USER CODE END DMA2_Stream2_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_usart1_rx);
|
|
80012f4: 4802 ldr r0, [pc, #8] @ (8001300 <DMA2_Stream2_IRQHandler+0x10>)
|
|
80012f6: f001 f84b bl 8002390 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA2_Stream2_IRQn 1 */
|
|
|
|
/* USER CODE END DMA2_Stream2_IRQn 1 */
|
|
}
|
|
80012fa: bf00 nop
|
|
80012fc: bd80 pop {r7, pc}
|
|
80012fe: bf00 nop
|
|
8001300: 20000c00 .word 0x20000c00
|
|
|
|
08001304 <OTG_FS_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USB On The Go FS global interrupt.
|
|
*/
|
|
void OTG_FS_IRQHandler(void)
|
|
{
|
|
8001304: b580 push {r7, lr}
|
|
8001306: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN OTG_FS_IRQn 0 */
|
|
|
|
/* USER CODE END OTG_FS_IRQn 0 */
|
|
HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
|
|
8001308: 4802 ldr r0, [pc, #8] @ (8001314 <OTG_FS_IRQHandler+0x10>)
|
|
800130a: f001 ff00 bl 800310e <HAL_PCD_IRQHandler>
|
|
/* USER CODE BEGIN OTG_FS_IRQn 1 */
|
|
|
|
/* USER CODE END OTG_FS_IRQn 1 */
|
|
}
|
|
800130e: bf00 nop
|
|
8001310: bd80 pop {r7, pc}
|
|
8001312: bf00 nop
|
|
8001314: 20001264 .word 0x20001264
|
|
|
|
08001318 <DMA2_Stream7_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA2 stream7 global interrupt.
|
|
*/
|
|
void DMA2_Stream7_IRQHandler(void)
|
|
{
|
|
8001318: b580 push {r7, lr}
|
|
800131a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
|
|
|
|
/* USER CODE END DMA2_Stream7_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_usart1_tx);
|
|
800131c: 4802 ldr r0, [pc, #8] @ (8001328 <DMA2_Stream7_IRQHandler+0x10>)
|
|
800131e: f001 f837 bl 8002390 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA2_Stream7_IRQn 1 */
|
|
|
|
/* USER CODE END DMA2_Stream7_IRQn 1 */
|
|
}
|
|
8001322: bf00 nop
|
|
8001324: bd80 pop {r7, pc}
|
|
8001326: bf00 nop
|
|
8001328: 20000c60 .word 0x20000c60
|
|
|
|
0800132c <SystemInit>:
|
|
* configuration.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
800132c: b480 push {r7}
|
|
800132e: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
8001330: 4b06 ldr r3, [pc, #24] @ (800134c <SystemInit+0x20>)
|
|
8001332: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8001336: 4a05 ldr r2, [pc, #20] @ (800134c <SystemInit+0x20>)
|
|
8001338: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
800133c: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
8001340: bf00 nop
|
|
8001342: 46bd mov sp, r7
|
|
8001344: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001348: 4770 bx lr
|
|
800134a: bf00 nop
|
|
800134c: e000ed00 .word 0xe000ed00
|
|
|
|
08001350 <MX_TIM2_Init>:
|
|
TIM_HandleTypeDef htim2;
|
|
TIM_HandleTypeDef htim3;
|
|
|
|
/* TIM2 init function */
|
|
void MX_TIM2_Init(void)
|
|
{
|
|
8001350: b580 push {r7, lr}
|
|
8001352: b08a sub sp, #40 @ 0x28
|
|
8001354: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM2_Init 0 */
|
|
|
|
/* USER CODE END TIM2_Init 0 */
|
|
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8001356: f107 0320 add.w r3, r7, #32
|
|
800135a: 2200 movs r2, #0
|
|
800135c: 601a str r2, [r3, #0]
|
|
800135e: 605a str r2, [r3, #4]
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
8001360: 1d3b adds r3, r7, #4
|
|
8001362: 2200 movs r2, #0
|
|
8001364: 601a str r2, [r3, #0]
|
|
8001366: 605a str r2, [r3, #4]
|
|
8001368: 609a str r2, [r3, #8]
|
|
800136a: 60da str r2, [r3, #12]
|
|
800136c: 611a str r2, [r3, #16]
|
|
800136e: 615a str r2, [r3, #20]
|
|
8001370: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE BEGIN TIM2_Init 1 */
|
|
|
|
/* USER CODE END TIM2_Init 1 */
|
|
htim2.Instance = TIM2;
|
|
8001372: 4b22 ldr r3, [pc, #136] @ (80013fc <MX_TIM2_Init+0xac>)
|
|
8001374: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
|
|
8001378: 601a str r2, [r3, #0]
|
|
htim2.Init.Prescaler = 0;
|
|
800137a: 4b20 ldr r3, [pc, #128] @ (80013fc <MX_TIM2_Init+0xac>)
|
|
800137c: 2200 movs r2, #0
|
|
800137e: 605a str r2, [r3, #4]
|
|
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8001380: 4b1e ldr r3, [pc, #120] @ (80013fc <MX_TIM2_Init+0xac>)
|
|
8001382: 2200 movs r2, #0
|
|
8001384: 609a str r2, [r3, #8]
|
|
htim2.Init.Period = 4294967295;
|
|
8001386: 4b1d ldr r3, [pc, #116] @ (80013fc <MX_TIM2_Init+0xac>)
|
|
8001388: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800138c: 60da str r2, [r3, #12]
|
|
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
800138e: 4b1b ldr r3, [pc, #108] @ (80013fc <MX_TIM2_Init+0xac>)
|
|
8001390: 2200 movs r2, #0
|
|
8001392: 611a str r2, [r3, #16]
|
|
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8001394: 4b19 ldr r3, [pc, #100] @ (80013fc <MX_TIM2_Init+0xac>)
|
|
8001396: 2200 movs r2, #0
|
|
8001398: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_OC_Init(&htim2) != HAL_OK)
|
|
800139a: 4818 ldr r0, [pc, #96] @ (80013fc <MX_TIM2_Init+0xac>)
|
|
800139c: f004 f904 bl 80055a8 <HAL_TIM_OC_Init>
|
|
80013a0: 4603 mov r3, r0
|
|
80013a2: 2b00 cmp r3, #0
|
|
80013a4: d001 beq.n 80013aa <MX_TIM2_Init+0x5a>
|
|
{
|
|
Error_Handler();
|
|
80013a6: f7ff fee1 bl 800116c <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
80013aa: 2300 movs r3, #0
|
|
80013ac: 623b str r3, [r7, #32]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
80013ae: 2300 movs r3, #0
|
|
80013b0: 627b str r3, [r7, #36] @ 0x24
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
|
|
80013b2: f107 0320 add.w r3, r7, #32
|
|
80013b6: 4619 mov r1, r3
|
|
80013b8: 4810 ldr r0, [pc, #64] @ (80013fc <MX_TIM2_Init+0xac>)
|
|
80013ba: f004 fd51 bl 8005e60 <HAL_TIMEx_MasterConfigSynchronization>
|
|
80013be: 4603 mov r3, r0
|
|
80013c0: 2b00 cmp r3, #0
|
|
80013c2: d001 beq.n 80013c8 <MX_TIM2_Init+0x78>
|
|
{
|
|
Error_Handler();
|
|
80013c4: f7ff fed2 bl 800116c <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE;
|
|
80013c8: 2350 movs r3, #80 @ 0x50
|
|
80013ca: 607b str r3, [r7, #4]
|
|
sConfigOC.Pulse = 0;
|
|
80013cc: 2300 movs r3, #0
|
|
80013ce: 60bb str r3, [r7, #8]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
80013d0: 2300 movs r3, #0
|
|
80013d2: 60fb str r3, [r7, #12]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
80013d4: 2300 movs r3, #0
|
|
80013d6: 617b str r3, [r7, #20]
|
|
if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
80013d8: 1d3b adds r3, r7, #4
|
|
80013da: 2200 movs r2, #0
|
|
80013dc: 4619 mov r1, r3
|
|
80013de: 4807 ldr r0, [pc, #28] @ (80013fc <MX_TIM2_Init+0xac>)
|
|
80013e0: f004 fa66 bl 80058b0 <HAL_TIM_OC_ConfigChannel>
|
|
80013e4: 4603 mov r3, r0
|
|
80013e6: 2b00 cmp r3, #0
|
|
80013e8: d001 beq.n 80013ee <MX_TIM2_Init+0x9e>
|
|
{
|
|
Error_Handler();
|
|
80013ea: f7ff febf bl 800116c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM2_Init 2 */
|
|
|
|
/* USER CODE END TIM2_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim2);
|
|
80013ee: 4803 ldr r0, [pc, #12] @ (80013fc <MX_TIM2_Init+0xac>)
|
|
80013f0: f000 f8c2 bl 8001578 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
80013f4: bf00 nop
|
|
80013f6: 3728 adds r7, #40 @ 0x28
|
|
80013f8: 46bd mov sp, r7
|
|
80013fa: bd80 pop {r7, pc}
|
|
80013fc: 200008d0 .word 0x200008d0
|
|
|
|
08001400 <MX_TIM3_Init>:
|
|
/* TIM3 init function */
|
|
void MX_TIM3_Init(void)
|
|
{
|
|
8001400: b580 push {r7, lr}
|
|
8001402: b08c sub sp, #48 @ 0x30
|
|
8001404: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM3_Init 0 */
|
|
|
|
/* USER CODE END TIM3_Init 0 */
|
|
|
|
TIM_Encoder_InitTypeDef sConfig = {0};
|
|
8001406: f107 030c add.w r3, r7, #12
|
|
800140a: 2224 movs r2, #36 @ 0x24
|
|
800140c: 2100 movs r1, #0
|
|
800140e: 4618 mov r0, r3
|
|
8001410: f009 fd16 bl 800ae40 <memset>
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8001414: 1d3b adds r3, r7, #4
|
|
8001416: 2200 movs r2, #0
|
|
8001418: 601a str r2, [r3, #0]
|
|
800141a: 605a str r2, [r3, #4]
|
|
|
|
/* USER CODE BEGIN TIM3_Init 1 */
|
|
|
|
/* USER CODE END TIM3_Init 1 */
|
|
htim3.Instance = TIM3;
|
|
800141c: 4b20 ldr r3, [pc, #128] @ (80014a0 <MX_TIM3_Init+0xa0>)
|
|
800141e: 4a21 ldr r2, [pc, #132] @ (80014a4 <MX_TIM3_Init+0xa4>)
|
|
8001420: 601a str r2, [r3, #0]
|
|
htim3.Init.Prescaler = 0;
|
|
8001422: 4b1f ldr r3, [pc, #124] @ (80014a0 <MX_TIM3_Init+0xa0>)
|
|
8001424: 2200 movs r2, #0
|
|
8001426: 605a str r2, [r3, #4]
|
|
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8001428: 4b1d ldr r3, [pc, #116] @ (80014a0 <MX_TIM3_Init+0xa0>)
|
|
800142a: 2200 movs r2, #0
|
|
800142c: 609a str r2, [r3, #8]
|
|
htim3.Init.Period = 65535;
|
|
800142e: 4b1c ldr r3, [pc, #112] @ (80014a0 <MX_TIM3_Init+0xa0>)
|
|
8001430: f64f 72ff movw r2, #65535 @ 0xffff
|
|
8001434: 60da str r2, [r3, #12]
|
|
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8001436: 4b1a ldr r3, [pc, #104] @ (80014a0 <MX_TIM3_Init+0xa0>)
|
|
8001438: 2200 movs r2, #0
|
|
800143a: 611a str r2, [r3, #16]
|
|
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
800143c: 4b18 ldr r3, [pc, #96] @ (80014a0 <MX_TIM3_Init+0xa0>)
|
|
800143e: 2200 movs r2, #0
|
|
8001440: 619a str r2, [r3, #24]
|
|
sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
|
|
8001442: 2301 movs r3, #1
|
|
8001444: 60fb str r3, [r7, #12]
|
|
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
|
|
8001446: 2300 movs r3, #0
|
|
8001448: 613b str r3, [r7, #16]
|
|
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
|
|
800144a: 2301 movs r3, #1
|
|
800144c: 617b str r3, [r7, #20]
|
|
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
|
|
800144e: 2300 movs r3, #0
|
|
8001450: 61bb str r3, [r7, #24]
|
|
sConfig.IC1Filter = 0;
|
|
8001452: 2300 movs r3, #0
|
|
8001454: 61fb str r3, [r7, #28]
|
|
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
|
|
8001456: 2300 movs r3, #0
|
|
8001458: 623b str r3, [r7, #32]
|
|
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
|
|
800145a: 2301 movs r3, #1
|
|
800145c: 627b str r3, [r7, #36] @ 0x24
|
|
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
|
|
800145e: 2300 movs r3, #0
|
|
8001460: 62bb str r3, [r7, #40] @ 0x28
|
|
sConfig.IC2Filter = 0;
|
|
8001462: 2300 movs r3, #0
|
|
8001464: 62fb str r3, [r7, #44] @ 0x2c
|
|
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
|
|
8001466: f107 030c add.w r3, r7, #12
|
|
800146a: 4619 mov r1, r3
|
|
800146c: 480c ldr r0, [pc, #48] @ (80014a0 <MX_TIM3_Init+0xa0>)
|
|
800146e: f004 f8ea bl 8005646 <HAL_TIM_Encoder_Init>
|
|
8001472: 4603 mov r3, r0
|
|
8001474: 2b00 cmp r3, #0
|
|
8001476: d001 beq.n 800147c <MX_TIM3_Init+0x7c>
|
|
{
|
|
Error_Handler();
|
|
8001478: f7ff fe78 bl 800116c <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
800147c: 2300 movs r3, #0
|
|
800147e: 607b str r3, [r7, #4]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8001480: 2300 movs r3, #0
|
|
8001482: 60bb str r3, [r7, #8]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
|
8001484: 1d3b adds r3, r7, #4
|
|
8001486: 4619 mov r1, r3
|
|
8001488: 4805 ldr r0, [pc, #20] @ (80014a0 <MX_TIM3_Init+0xa0>)
|
|
800148a: f004 fce9 bl 8005e60 <HAL_TIMEx_MasterConfigSynchronization>
|
|
800148e: 4603 mov r3, r0
|
|
8001490: 2b00 cmp r3, #0
|
|
8001492: d001 beq.n 8001498 <MX_TIM3_Init+0x98>
|
|
{
|
|
Error_Handler();
|
|
8001494: f7ff fe6a bl 800116c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM3_Init 2 */
|
|
|
|
/* USER CODE END TIM3_Init 2 */
|
|
|
|
}
|
|
8001498: bf00 nop
|
|
800149a: 3730 adds r7, #48 @ 0x30
|
|
800149c: 46bd mov sp, r7
|
|
800149e: bd80 pop {r7, pc}
|
|
80014a0: 20000918 .word 0x20000918
|
|
80014a4: 40000400 .word 0x40000400
|
|
|
|
080014a8 <HAL_TIM_OC_MspInit>:
|
|
|
|
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle)
|
|
{
|
|
80014a8: b480 push {r7}
|
|
80014aa: b085 sub sp, #20
|
|
80014ac: af00 add r7, sp, #0
|
|
80014ae: 6078 str r0, [r7, #4]
|
|
|
|
if(tim_ocHandle->Instance==TIM2)
|
|
80014b0: 687b ldr r3, [r7, #4]
|
|
80014b2: 681b ldr r3, [r3, #0]
|
|
80014b4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80014b8: d10d bne.n 80014d6 <HAL_TIM_OC_MspInit+0x2e>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspInit 0 */
|
|
/* TIM2 clock enable */
|
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
|
80014ba: 2300 movs r3, #0
|
|
80014bc: 60fb str r3, [r7, #12]
|
|
80014be: 4b09 ldr r3, [pc, #36] @ (80014e4 <HAL_TIM_OC_MspInit+0x3c>)
|
|
80014c0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80014c2: 4a08 ldr r2, [pc, #32] @ (80014e4 <HAL_TIM_OC_MspInit+0x3c>)
|
|
80014c4: f043 0301 orr.w r3, r3, #1
|
|
80014c8: 6413 str r3, [r2, #64] @ 0x40
|
|
80014ca: 4b06 ldr r3, [pc, #24] @ (80014e4 <HAL_TIM_OC_MspInit+0x3c>)
|
|
80014cc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80014ce: f003 0301 and.w r3, r3, #1
|
|
80014d2: 60fb str r3, [r7, #12]
|
|
80014d4: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN TIM2_MspInit 1 */
|
|
|
|
/* USER CODE END TIM2_MspInit 1 */
|
|
}
|
|
}
|
|
80014d6: bf00 nop
|
|
80014d8: 3714 adds r7, #20
|
|
80014da: 46bd mov sp, r7
|
|
80014dc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80014e0: 4770 bx lr
|
|
80014e2: bf00 nop
|
|
80014e4: 40023800 .word 0x40023800
|
|
|
|
080014e8 <HAL_TIM_Encoder_MspInit>:
|
|
|
|
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle)
|
|
{
|
|
80014e8: b580 push {r7, lr}
|
|
80014ea: b08a sub sp, #40 @ 0x28
|
|
80014ec: af00 add r7, sp, #0
|
|
80014ee: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80014f0: f107 0314 add.w r3, r7, #20
|
|
80014f4: 2200 movs r2, #0
|
|
80014f6: 601a str r2, [r3, #0]
|
|
80014f8: 605a str r2, [r3, #4]
|
|
80014fa: 609a str r2, [r3, #8]
|
|
80014fc: 60da str r2, [r3, #12]
|
|
80014fe: 611a str r2, [r3, #16]
|
|
if(tim_encoderHandle->Instance==TIM3)
|
|
8001500: 687b ldr r3, [r7, #4]
|
|
8001502: 681b ldr r3, [r3, #0]
|
|
8001504: 4a19 ldr r2, [pc, #100] @ (800156c <HAL_TIM_Encoder_MspInit+0x84>)
|
|
8001506: 4293 cmp r3, r2
|
|
8001508: d12b bne.n 8001562 <HAL_TIM_Encoder_MspInit+0x7a>
|
|
{
|
|
/* USER CODE BEGIN TIM3_MspInit 0 */
|
|
|
|
/* USER CODE END TIM3_MspInit 0 */
|
|
/* TIM3 clock enable */
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
800150a: 2300 movs r3, #0
|
|
800150c: 613b str r3, [r7, #16]
|
|
800150e: 4b18 ldr r3, [pc, #96] @ (8001570 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001510: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001512: 4a17 ldr r2, [pc, #92] @ (8001570 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001514: f043 0302 orr.w r3, r3, #2
|
|
8001518: 6413 str r3, [r2, #64] @ 0x40
|
|
800151a: 4b15 ldr r3, [pc, #84] @ (8001570 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
800151c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800151e: f003 0302 and.w r3, r3, #2
|
|
8001522: 613b str r3, [r7, #16]
|
|
8001524: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001526: 2300 movs r3, #0
|
|
8001528: 60fb str r3, [r7, #12]
|
|
800152a: 4b11 ldr r3, [pc, #68] @ (8001570 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
800152c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800152e: 4a10 ldr r2, [pc, #64] @ (8001570 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001530: f043 0301 orr.w r3, r3, #1
|
|
8001534: 6313 str r3, [r2, #48] @ 0x30
|
|
8001536: 4b0e ldr r3, [pc, #56] @ (8001570 <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001538: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800153a: f003 0301 and.w r3, r3, #1
|
|
800153e: 60fb str r3, [r7, #12]
|
|
8001540: 68fb ldr r3, [r7, #12]
|
|
/**TIM3 GPIO Configuration
|
|
PA6 ------> TIM3_CH1
|
|
PA7 ------> TIM3_CH2
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
8001542: 23c0 movs r3, #192 @ 0xc0
|
|
8001544: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001546: 2302 movs r3, #2
|
|
8001548: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800154a: 2300 movs r3, #0
|
|
800154c: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800154e: 2300 movs r3, #0
|
|
8001550: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
|
|
8001552: 2302 movs r3, #2
|
|
8001554: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001556: f107 0314 add.w r3, r7, #20
|
|
800155a: 4619 mov r1, r3
|
|
800155c: 4805 ldr r0, [pc, #20] @ (8001574 <HAL_TIM_Encoder_MspInit+0x8c>)
|
|
800155e: f001 f981 bl 8002864 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN TIM3_MspInit 1 */
|
|
|
|
/* USER CODE END TIM3_MspInit 1 */
|
|
}
|
|
}
|
|
8001562: bf00 nop
|
|
8001564: 3728 adds r7, #40 @ 0x28
|
|
8001566: 46bd mov sp, r7
|
|
8001568: bd80 pop {r7, pc}
|
|
800156a: bf00 nop
|
|
800156c: 40000400 .word 0x40000400
|
|
8001570: 40023800 .word 0x40023800
|
|
8001574: 40020000 .word 0x40020000
|
|
|
|
08001578 <HAL_TIM_MspPostInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
|
|
{
|
|
8001578: b580 push {r7, lr}
|
|
800157a: b088 sub sp, #32
|
|
800157c: af00 add r7, sp, #0
|
|
800157e: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001580: f107 030c add.w r3, r7, #12
|
|
8001584: 2200 movs r2, #0
|
|
8001586: 601a str r2, [r3, #0]
|
|
8001588: 605a str r2, [r3, #4]
|
|
800158a: 609a str r2, [r3, #8]
|
|
800158c: 60da str r2, [r3, #12]
|
|
800158e: 611a str r2, [r3, #16]
|
|
if(timHandle->Instance==TIM2)
|
|
8001590: 687b ldr r3, [r7, #4]
|
|
8001592: 681b ldr r3, [r3, #0]
|
|
8001594: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8001598: d11d bne.n 80015d6 <HAL_TIM_MspPostInit+0x5e>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 0 */
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800159a: 2300 movs r3, #0
|
|
800159c: 60bb str r3, [r7, #8]
|
|
800159e: 4b10 ldr r3, [pc, #64] @ (80015e0 <HAL_TIM_MspPostInit+0x68>)
|
|
80015a0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80015a2: 4a0f ldr r2, [pc, #60] @ (80015e0 <HAL_TIM_MspPostInit+0x68>)
|
|
80015a4: f043 0301 orr.w r3, r3, #1
|
|
80015a8: 6313 str r3, [r2, #48] @ 0x30
|
|
80015aa: 4b0d ldr r3, [pc, #52] @ (80015e0 <HAL_TIM_MspPostInit+0x68>)
|
|
80015ac: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80015ae: f003 0301 and.w r3, r3, #1
|
|
80015b2: 60bb str r3, [r7, #8]
|
|
80015b4: 68bb ldr r3, [r7, #8]
|
|
/**TIM2 GPIO Configuration
|
|
PA5 ------> TIM2_CH1
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_5;
|
|
80015b6: 2320 movs r3, #32
|
|
80015b8: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80015ba: 2302 movs r3, #2
|
|
80015bc: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80015be: 2300 movs r3, #0
|
|
80015c0: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80015c2: 2300 movs r3, #0
|
|
80015c4: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
|
|
80015c6: 2301 movs r3, #1
|
|
80015c8: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80015ca: f107 030c add.w r3, r7, #12
|
|
80015ce: 4619 mov r1, r3
|
|
80015d0: 4804 ldr r0, [pc, #16] @ (80015e4 <HAL_TIM_MspPostInit+0x6c>)
|
|
80015d2: f001 f947 bl 8002864 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM2_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
80015d6: bf00 nop
|
|
80015d8: 3720 adds r7, #32
|
|
80015da: 46bd mov sp, r7
|
|
80015dc: bd80 pop {r7, pc}
|
|
80015de: bf00 nop
|
|
80015e0: 40023800 .word 0x40023800
|
|
80015e4: 40020000 .word 0x40020000
|
|
|
|
080015e8 <MX_UART4_Init>:
|
|
DMA_HandleTypeDef hdma_usart2_rx;
|
|
DMA_HandleTypeDef hdma_usart2_tx;
|
|
|
|
/* UART4 init function */
|
|
void MX_UART4_Init(void)
|
|
{
|
|
80015e8: b580 push {r7, lr}
|
|
80015ea: af00 add r7, sp, #0
|
|
/* USER CODE END UART4_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART4_Init 1 */
|
|
|
|
/* USER CODE END UART4_Init 1 */
|
|
huart4.Instance = UART4;
|
|
80015ec: 4b11 ldr r3, [pc, #68] @ (8001634 <MX_UART4_Init+0x4c>)
|
|
80015ee: 4a12 ldr r2, [pc, #72] @ (8001638 <MX_UART4_Init+0x50>)
|
|
80015f0: 601a str r2, [r3, #0]
|
|
huart4.Init.BaudRate = 115200;
|
|
80015f2: 4b10 ldr r3, [pc, #64] @ (8001634 <MX_UART4_Init+0x4c>)
|
|
80015f4: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
80015f8: 605a str r2, [r3, #4]
|
|
huart4.Init.WordLength = UART_WORDLENGTH_8B;
|
|
80015fa: 4b0e ldr r3, [pc, #56] @ (8001634 <MX_UART4_Init+0x4c>)
|
|
80015fc: 2200 movs r2, #0
|
|
80015fe: 609a str r2, [r3, #8]
|
|
huart4.Init.StopBits = UART_STOPBITS_1;
|
|
8001600: 4b0c ldr r3, [pc, #48] @ (8001634 <MX_UART4_Init+0x4c>)
|
|
8001602: 2200 movs r2, #0
|
|
8001604: 60da str r2, [r3, #12]
|
|
huart4.Init.Parity = UART_PARITY_NONE;
|
|
8001606: 4b0b ldr r3, [pc, #44] @ (8001634 <MX_UART4_Init+0x4c>)
|
|
8001608: 2200 movs r2, #0
|
|
800160a: 611a str r2, [r3, #16]
|
|
huart4.Init.Mode = UART_MODE_TX_RX;
|
|
800160c: 4b09 ldr r3, [pc, #36] @ (8001634 <MX_UART4_Init+0x4c>)
|
|
800160e: 220c movs r2, #12
|
|
8001610: 615a str r2, [r3, #20]
|
|
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8001612: 4b08 ldr r3, [pc, #32] @ (8001634 <MX_UART4_Init+0x4c>)
|
|
8001614: 2200 movs r2, #0
|
|
8001616: 619a str r2, [r3, #24]
|
|
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8001618: 4b06 ldr r3, [pc, #24] @ (8001634 <MX_UART4_Init+0x4c>)
|
|
800161a: 2200 movs r2, #0
|
|
800161c: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart4) != HAL_OK)
|
|
800161e: 4805 ldr r0, [pc, #20] @ (8001634 <MX_UART4_Init+0x4c>)
|
|
8001620: f004 fc9a bl 8005f58 <HAL_UART_Init>
|
|
8001624: 4603 mov r3, r0
|
|
8001626: 2b00 cmp r3, #0
|
|
8001628: d001 beq.n 800162e <MX_UART4_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
800162a: f7ff fd9f bl 800116c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART4_Init 2 */
|
|
|
|
/* USER CODE END UART4_Init 2 */
|
|
|
|
}
|
|
800162e: bf00 nop
|
|
8001630: bd80 pop {r7, pc}
|
|
8001632: bf00 nop
|
|
8001634: 20000960 .word 0x20000960
|
|
8001638: 40004c00 .word 0x40004c00
|
|
|
|
0800163c <MX_UART5_Init>:
|
|
/* UART5 init function */
|
|
void MX_UART5_Init(void)
|
|
{
|
|
800163c: b580 push {r7, lr}
|
|
800163e: af00 add r7, sp, #0
|
|
/* USER CODE END UART5_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART5_Init 1 */
|
|
|
|
/* USER CODE END UART5_Init 1 */
|
|
huart5.Instance = UART5;
|
|
8001640: 4b11 ldr r3, [pc, #68] @ (8001688 <MX_UART5_Init+0x4c>)
|
|
8001642: 4a12 ldr r2, [pc, #72] @ (800168c <MX_UART5_Init+0x50>)
|
|
8001644: 601a str r2, [r3, #0]
|
|
huart5.Init.BaudRate = 115200;
|
|
8001646: 4b10 ldr r3, [pc, #64] @ (8001688 <MX_UART5_Init+0x4c>)
|
|
8001648: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
800164c: 605a str r2, [r3, #4]
|
|
huart5.Init.WordLength = UART_WORDLENGTH_8B;
|
|
800164e: 4b0e ldr r3, [pc, #56] @ (8001688 <MX_UART5_Init+0x4c>)
|
|
8001650: 2200 movs r2, #0
|
|
8001652: 609a str r2, [r3, #8]
|
|
huart5.Init.StopBits = UART_STOPBITS_1;
|
|
8001654: 4b0c ldr r3, [pc, #48] @ (8001688 <MX_UART5_Init+0x4c>)
|
|
8001656: 2200 movs r2, #0
|
|
8001658: 60da str r2, [r3, #12]
|
|
huart5.Init.Parity = UART_PARITY_NONE;
|
|
800165a: 4b0b ldr r3, [pc, #44] @ (8001688 <MX_UART5_Init+0x4c>)
|
|
800165c: 2200 movs r2, #0
|
|
800165e: 611a str r2, [r3, #16]
|
|
huart5.Init.Mode = UART_MODE_TX_RX;
|
|
8001660: 4b09 ldr r3, [pc, #36] @ (8001688 <MX_UART5_Init+0x4c>)
|
|
8001662: 220c movs r2, #12
|
|
8001664: 615a str r2, [r3, #20]
|
|
huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8001666: 4b08 ldr r3, [pc, #32] @ (8001688 <MX_UART5_Init+0x4c>)
|
|
8001668: 2200 movs r2, #0
|
|
800166a: 619a str r2, [r3, #24]
|
|
huart5.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
800166c: 4b06 ldr r3, [pc, #24] @ (8001688 <MX_UART5_Init+0x4c>)
|
|
800166e: 2200 movs r2, #0
|
|
8001670: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart5) != HAL_OK)
|
|
8001672: 4805 ldr r0, [pc, #20] @ (8001688 <MX_UART5_Init+0x4c>)
|
|
8001674: f004 fc70 bl 8005f58 <HAL_UART_Init>
|
|
8001678: 4603 mov r3, r0
|
|
800167a: 2b00 cmp r3, #0
|
|
800167c: d001 beq.n 8001682 <MX_UART5_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
800167e: f7ff fd75 bl 800116c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART5_Init 2 */
|
|
|
|
/* USER CODE END UART5_Init 2 */
|
|
|
|
}
|
|
8001682: bf00 nop
|
|
8001684: bd80 pop {r7, pc}
|
|
8001686: bf00 nop
|
|
8001688: 200009a8 .word 0x200009a8
|
|
800168c: 40005000 .word 0x40005000
|
|
|
|
08001690 <MX_USART1_UART_Init>:
|
|
/* USART1 init function */
|
|
|
|
void MX_USART1_UART_Init(void)
|
|
{
|
|
8001690: b580 push {r7, lr}
|
|
8001692: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
8001694: 4b11 ldr r3, [pc, #68] @ (80016dc <MX_USART1_UART_Init+0x4c>)
|
|
8001696: 4a12 ldr r2, [pc, #72] @ (80016e0 <MX_USART1_UART_Init+0x50>)
|
|
8001698: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
800169a: 4b10 ldr r3, [pc, #64] @ (80016dc <MX_USART1_UART_Init+0x4c>)
|
|
800169c: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
80016a0: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
80016a2: 4b0e ldr r3, [pc, #56] @ (80016dc <MX_USART1_UART_Init+0x4c>)
|
|
80016a4: 2200 movs r2, #0
|
|
80016a6: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
80016a8: 4b0c ldr r3, [pc, #48] @ (80016dc <MX_USART1_UART_Init+0x4c>)
|
|
80016aa: 2200 movs r2, #0
|
|
80016ac: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
80016ae: 4b0b ldr r3, [pc, #44] @ (80016dc <MX_USART1_UART_Init+0x4c>)
|
|
80016b0: 2200 movs r2, #0
|
|
80016b2: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
80016b4: 4b09 ldr r3, [pc, #36] @ (80016dc <MX_USART1_UART_Init+0x4c>)
|
|
80016b6: 220c movs r2, #12
|
|
80016b8: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80016ba: 4b08 ldr r3, [pc, #32] @ (80016dc <MX_USART1_UART_Init+0x4c>)
|
|
80016bc: 2200 movs r2, #0
|
|
80016be: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80016c0: 4b06 ldr r3, [pc, #24] @ (80016dc <MX_USART1_UART_Init+0x4c>)
|
|
80016c2: 2200 movs r2, #0
|
|
80016c4: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
80016c6: 4805 ldr r0, [pc, #20] @ (80016dc <MX_USART1_UART_Init+0x4c>)
|
|
80016c8: f004 fc46 bl 8005f58 <HAL_UART_Init>
|
|
80016cc: 4603 mov r3, r0
|
|
80016ce: 2b00 cmp r3, #0
|
|
80016d0: d001 beq.n 80016d6 <MX_USART1_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
80016d2: f7ff fd4b bl 800116c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
80016d6: bf00 nop
|
|
80016d8: bd80 pop {r7, pc}
|
|
80016da: bf00 nop
|
|
80016dc: 200009f0 .word 0x200009f0
|
|
80016e0: 40011000 .word 0x40011000
|
|
|
|
080016e4 <MX_USART2_UART_Init>:
|
|
/* USART2 init function */
|
|
|
|
void MX_USART2_UART_Init(void)
|
|
{
|
|
80016e4: b580 push {r7, lr}
|
|
80016e6: af00 add r7, sp, #0
|
|
/* USER CODE END USART2_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
|
|
|
/* USER CODE END USART2_Init 1 */
|
|
huart2.Instance = USART2;
|
|
80016e8: 4b11 ldr r3, [pc, #68] @ (8001730 <MX_USART2_UART_Init+0x4c>)
|
|
80016ea: 4a12 ldr r2, [pc, #72] @ (8001734 <MX_USART2_UART_Init+0x50>)
|
|
80016ec: 601a str r2, [r3, #0]
|
|
huart2.Init.BaudRate = 115200;
|
|
80016ee: 4b10 ldr r3, [pc, #64] @ (8001730 <MX_USART2_UART_Init+0x4c>)
|
|
80016f0: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
80016f4: 605a str r2, [r3, #4]
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
80016f6: 4b0e ldr r3, [pc, #56] @ (8001730 <MX_USART2_UART_Init+0x4c>)
|
|
80016f8: 2200 movs r2, #0
|
|
80016fa: 609a str r2, [r3, #8]
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
80016fc: 4b0c ldr r3, [pc, #48] @ (8001730 <MX_USART2_UART_Init+0x4c>)
|
|
80016fe: 2200 movs r2, #0
|
|
8001700: 60da str r2, [r3, #12]
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
8001702: 4b0b ldr r3, [pc, #44] @ (8001730 <MX_USART2_UART_Init+0x4c>)
|
|
8001704: 2200 movs r2, #0
|
|
8001706: 611a str r2, [r3, #16]
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
8001708: 4b09 ldr r3, [pc, #36] @ (8001730 <MX_USART2_UART_Init+0x4c>)
|
|
800170a: 220c movs r2, #12
|
|
800170c: 615a str r2, [r3, #20]
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
800170e: 4b08 ldr r3, [pc, #32] @ (8001730 <MX_USART2_UART_Init+0x4c>)
|
|
8001710: 2200 movs r2, #0
|
|
8001712: 619a str r2, [r3, #24]
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8001714: 4b06 ldr r3, [pc, #24] @ (8001730 <MX_USART2_UART_Init+0x4c>)
|
|
8001716: 2200 movs r2, #0
|
|
8001718: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
|
800171a: 4805 ldr r0, [pc, #20] @ (8001730 <MX_USART2_UART_Init+0x4c>)
|
|
800171c: f004 fc1c bl 8005f58 <HAL_UART_Init>
|
|
8001720: 4603 mov r3, r0
|
|
8001722: 2b00 cmp r3, #0
|
|
8001724: d001 beq.n 800172a <MX_USART2_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8001726: f7ff fd21 bl 800116c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
|
|
|
/* USER CODE END USART2_Init 2 */
|
|
|
|
}
|
|
800172a: bf00 nop
|
|
800172c: bd80 pop {r7, pc}
|
|
800172e: bf00 nop
|
|
8001730: 20000a38 .word 0x20000a38
|
|
8001734: 40004400 .word 0x40004400
|
|
|
|
08001738 <HAL_UART_MspInit>:
|
|
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
|
|
{
|
|
8001738: b580 push {r7, lr}
|
|
800173a: b090 sub sp, #64 @ 0x40
|
|
800173c: af00 add r7, sp, #0
|
|
800173e: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001740: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
8001744: 2200 movs r2, #0
|
|
8001746: 601a str r2, [r3, #0]
|
|
8001748: 605a str r2, [r3, #4]
|
|
800174a: 609a str r2, [r3, #8]
|
|
800174c: 60da str r2, [r3, #12]
|
|
800174e: 611a str r2, [r3, #16]
|
|
if(uartHandle->Instance==UART4)
|
|
8001750: 687b ldr r3, [r7, #4]
|
|
8001752: 681b ldr r3, [r3, #0]
|
|
8001754: 4a4a ldr r2, [pc, #296] @ (8001880 <HAL_UART_MspInit+0x148>)
|
|
8001756: 4293 cmp r3, r2
|
|
8001758: f040 80a0 bne.w 800189c <HAL_UART_MspInit+0x164>
|
|
{
|
|
/* USER CODE BEGIN UART4_MspInit 0 */
|
|
|
|
/* USER CODE END UART4_MspInit 0 */
|
|
/* UART4 clock enable */
|
|
__HAL_RCC_UART4_CLK_ENABLE();
|
|
800175c: 2300 movs r3, #0
|
|
800175e: 62bb str r3, [r7, #40] @ 0x28
|
|
8001760: 4b48 ldr r3, [pc, #288] @ (8001884 <HAL_UART_MspInit+0x14c>)
|
|
8001762: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001764: 4a47 ldr r2, [pc, #284] @ (8001884 <HAL_UART_MspInit+0x14c>)
|
|
8001766: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
800176a: 6413 str r3, [r2, #64] @ 0x40
|
|
800176c: 4b45 ldr r3, [pc, #276] @ (8001884 <HAL_UART_MspInit+0x14c>)
|
|
800176e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001770: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8001774: 62bb str r3, [r7, #40] @ 0x28
|
|
8001776: 6abb ldr r3, [r7, #40] @ 0x28
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001778: 2300 movs r3, #0
|
|
800177a: 627b str r3, [r7, #36] @ 0x24
|
|
800177c: 4b41 ldr r3, [pc, #260] @ (8001884 <HAL_UART_MspInit+0x14c>)
|
|
800177e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001780: 4a40 ldr r2, [pc, #256] @ (8001884 <HAL_UART_MspInit+0x14c>)
|
|
8001782: f043 0301 orr.w r3, r3, #1
|
|
8001786: 6313 str r3, [r2, #48] @ 0x30
|
|
8001788: 4b3e ldr r3, [pc, #248] @ (8001884 <HAL_UART_MspInit+0x14c>)
|
|
800178a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800178c: f003 0301 and.w r3, r3, #1
|
|
8001790: 627b str r3, [r7, #36] @ 0x24
|
|
8001792: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
/**UART4 GPIO Configuration
|
|
PA0-WKUP ------> UART4_TX
|
|
PA1 ------> UART4_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
|
|
8001794: 2303 movs r3, #3
|
|
8001796: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001798: 2302 movs r3, #2
|
|
800179a: 633b str r3, [r7, #48] @ 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800179c: 2300 movs r3, #0
|
|
800179e: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80017a0: 2303 movs r3, #3
|
|
80017a2: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
|
|
80017a4: 2308 movs r3, #8
|
|
80017a6: 63fb str r3, [r7, #60] @ 0x3c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80017a8: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
80017ac: 4619 mov r1, r3
|
|
80017ae: 4836 ldr r0, [pc, #216] @ (8001888 <HAL_UART_MspInit+0x150>)
|
|
80017b0: f001 f858 bl 8002864 <HAL_GPIO_Init>
|
|
|
|
/* UART4 DMA Init */
|
|
/* UART4_RX Init */
|
|
hdma_uart4_rx.Instance = DMA1_Stream2;
|
|
80017b4: 4b35 ldr r3, [pc, #212] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
80017b6: 4a36 ldr r2, [pc, #216] @ (8001890 <HAL_UART_MspInit+0x158>)
|
|
80017b8: 601a str r2, [r3, #0]
|
|
hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4;
|
|
80017ba: 4b34 ldr r3, [pc, #208] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
80017bc: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
80017c0: 605a str r2, [r3, #4]
|
|
hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
80017c2: 4b32 ldr r3, [pc, #200] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
80017c4: 2200 movs r2, #0
|
|
80017c6: 609a str r2, [r3, #8]
|
|
hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
80017c8: 4b30 ldr r3, [pc, #192] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
80017ca: 2200 movs r2, #0
|
|
80017cc: 60da str r2, [r3, #12]
|
|
hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE;
|
|
80017ce: 4b2f ldr r3, [pc, #188] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
80017d0: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
80017d4: 611a str r2, [r3, #16]
|
|
hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
80017d6: 4b2d ldr r3, [pc, #180] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
80017d8: 2200 movs r2, #0
|
|
80017da: 615a str r2, [r3, #20]
|
|
hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
80017dc: 4b2b ldr r3, [pc, #172] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
80017de: 2200 movs r2, #0
|
|
80017e0: 619a str r2, [r3, #24]
|
|
hdma_uart4_rx.Init.Mode = DMA_NORMAL;
|
|
80017e2: 4b2a ldr r3, [pc, #168] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
80017e4: 2200 movs r2, #0
|
|
80017e6: 61da str r2, [r3, #28]
|
|
hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW;
|
|
80017e8: 4b28 ldr r3, [pc, #160] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
80017ea: 2200 movs r2, #0
|
|
80017ec: 621a str r2, [r3, #32]
|
|
hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
80017ee: 4b27 ldr r3, [pc, #156] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
80017f0: 2200 movs r2, #0
|
|
80017f2: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK)
|
|
80017f4: 4825 ldr r0, [pc, #148] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
80017f6: f000 fc33 bl 8002060 <HAL_DMA_Init>
|
|
80017fa: 4603 mov r3, r0
|
|
80017fc: 2b00 cmp r3, #0
|
|
80017fe: d001 beq.n 8001804 <HAL_UART_MspInit+0xcc>
|
|
{
|
|
Error_Handler();
|
|
8001800: f7ff fcb4 bl 800116c <Error_Handler>
|
|
}
|
|
|
|
__HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx);
|
|
8001804: 687b ldr r3, [r7, #4]
|
|
8001806: 4a21 ldr r2, [pc, #132] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
8001808: 63da str r2, [r3, #60] @ 0x3c
|
|
800180a: 4a20 ldr r2, [pc, #128] @ (800188c <HAL_UART_MspInit+0x154>)
|
|
800180c: 687b ldr r3, [r7, #4]
|
|
800180e: 6393 str r3, [r2, #56] @ 0x38
|
|
|
|
/* UART4_TX Init */
|
|
hdma_uart4_tx.Instance = DMA1_Stream4;
|
|
8001810: 4b20 ldr r3, [pc, #128] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
8001812: 4a21 ldr r2, [pc, #132] @ (8001898 <HAL_UART_MspInit+0x160>)
|
|
8001814: 601a str r2, [r3, #0]
|
|
hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4;
|
|
8001816: 4b1f ldr r3, [pc, #124] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
8001818: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
800181c: 605a str r2, [r3, #4]
|
|
hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
800181e: 4b1d ldr r3, [pc, #116] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
8001820: 2240 movs r2, #64 @ 0x40
|
|
8001822: 609a str r2, [r3, #8]
|
|
hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
8001824: 4b1b ldr r3, [pc, #108] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
8001826: 2200 movs r2, #0
|
|
8001828: 60da str r2, [r3, #12]
|
|
hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
800182a: 4b1a ldr r3, [pc, #104] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
800182c: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001830: 611a str r2, [r3, #16]
|
|
hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
8001832: 4b18 ldr r3, [pc, #96] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
8001834: 2200 movs r2, #0
|
|
8001836: 615a str r2, [r3, #20]
|
|
hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
8001838: 4b16 ldr r3, [pc, #88] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
800183a: 2200 movs r2, #0
|
|
800183c: 619a str r2, [r3, #24]
|
|
hdma_uart4_tx.Init.Mode = DMA_NORMAL;
|
|
800183e: 4b15 ldr r3, [pc, #84] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
8001840: 2200 movs r2, #0
|
|
8001842: 61da str r2, [r3, #28]
|
|
hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW;
|
|
8001844: 4b13 ldr r3, [pc, #76] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
8001846: 2200 movs r2, #0
|
|
8001848: 621a str r2, [r3, #32]
|
|
hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
800184a: 4b12 ldr r3, [pc, #72] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
800184c: 2200 movs r2, #0
|
|
800184e: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK)
|
|
8001850: 4810 ldr r0, [pc, #64] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
8001852: f000 fc05 bl 8002060 <HAL_DMA_Init>
|
|
8001856: 4603 mov r3, r0
|
|
8001858: 2b00 cmp r3, #0
|
|
800185a: d001 beq.n 8001860 <HAL_UART_MspInit+0x128>
|
|
{
|
|
Error_Handler();
|
|
800185c: f7ff fc86 bl 800116c <Error_Handler>
|
|
}
|
|
|
|
__HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx);
|
|
8001860: 687b ldr r3, [r7, #4]
|
|
8001862: 4a0c ldr r2, [pc, #48] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
8001864: 639a str r2, [r3, #56] @ 0x38
|
|
8001866: 4a0b ldr r2, [pc, #44] @ (8001894 <HAL_UART_MspInit+0x15c>)
|
|
8001868: 687b ldr r3, [r7, #4]
|
|
800186a: 6393 str r3, [r2, #56] @ 0x38
|
|
|
|
/* UART4 interrupt Init */
|
|
HAL_NVIC_SetPriority(UART4_IRQn, 5, 0);
|
|
800186c: 2200 movs r2, #0
|
|
800186e: 2105 movs r1, #5
|
|
8001870: 2034 movs r0, #52 @ 0x34
|
|
8001872: f000 fbbe bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(UART4_IRQn);
|
|
8001876: 2034 movs r0, #52 @ 0x34
|
|
8001878: f000 fbd7 bl 800202a <HAL_NVIC_EnableIRQ>
|
|
HAL_NVIC_EnableIRQ(USART2_IRQn);
|
|
/* USER CODE BEGIN USART2_MspInit 1 */
|
|
|
|
/* USER CODE END USART2_MspInit 1 */
|
|
}
|
|
}
|
|
800187c: e202 b.n 8001c84 <HAL_UART_MspInit+0x54c>
|
|
800187e: bf00 nop
|
|
8001880: 40004c00 .word 0x40004c00
|
|
8001884: 40023800 .word 0x40023800
|
|
8001888: 40020000 .word 0x40020000
|
|
800188c: 20000a80 .word 0x20000a80
|
|
8001890: 40026040 .word 0x40026040
|
|
8001894: 20000ae0 .word 0x20000ae0
|
|
8001898: 40026070 .word 0x40026070
|
|
else if(uartHandle->Instance==UART5)
|
|
800189c: 687b ldr r3, [r7, #4]
|
|
800189e: 681b ldr r3, [r3, #0]
|
|
80018a0: 4a59 ldr r2, [pc, #356] @ (8001a08 <HAL_UART_MspInit+0x2d0>)
|
|
80018a2: 4293 cmp r3, r2
|
|
80018a4: f040 80c0 bne.w 8001a28 <HAL_UART_MspInit+0x2f0>
|
|
__HAL_RCC_UART5_CLK_ENABLE();
|
|
80018a8: 2300 movs r3, #0
|
|
80018aa: 623b str r3, [r7, #32]
|
|
80018ac: 4b57 ldr r3, [pc, #348] @ (8001a0c <HAL_UART_MspInit+0x2d4>)
|
|
80018ae: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80018b0: 4a56 ldr r2, [pc, #344] @ (8001a0c <HAL_UART_MspInit+0x2d4>)
|
|
80018b2: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
80018b6: 6413 str r3, [r2, #64] @ 0x40
|
|
80018b8: 4b54 ldr r3, [pc, #336] @ (8001a0c <HAL_UART_MspInit+0x2d4>)
|
|
80018ba: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80018bc: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
80018c0: 623b str r3, [r7, #32]
|
|
80018c2: 6a3b ldr r3, [r7, #32]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
80018c4: 2300 movs r3, #0
|
|
80018c6: 61fb str r3, [r7, #28]
|
|
80018c8: 4b50 ldr r3, [pc, #320] @ (8001a0c <HAL_UART_MspInit+0x2d4>)
|
|
80018ca: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80018cc: 4a4f ldr r2, [pc, #316] @ (8001a0c <HAL_UART_MspInit+0x2d4>)
|
|
80018ce: f043 0304 orr.w r3, r3, #4
|
|
80018d2: 6313 str r3, [r2, #48] @ 0x30
|
|
80018d4: 4b4d ldr r3, [pc, #308] @ (8001a0c <HAL_UART_MspInit+0x2d4>)
|
|
80018d6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80018d8: f003 0304 and.w r3, r3, #4
|
|
80018dc: 61fb str r3, [r7, #28]
|
|
80018de: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
80018e0: 2300 movs r3, #0
|
|
80018e2: 61bb str r3, [r7, #24]
|
|
80018e4: 4b49 ldr r3, [pc, #292] @ (8001a0c <HAL_UART_MspInit+0x2d4>)
|
|
80018e6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80018e8: 4a48 ldr r2, [pc, #288] @ (8001a0c <HAL_UART_MspInit+0x2d4>)
|
|
80018ea: f043 0308 orr.w r3, r3, #8
|
|
80018ee: 6313 str r3, [r2, #48] @ 0x30
|
|
80018f0: 4b46 ldr r3, [pc, #280] @ (8001a0c <HAL_UART_MspInit+0x2d4>)
|
|
80018f2: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80018f4: f003 0308 and.w r3, r3, #8
|
|
80018f8: 61bb str r3, [r7, #24]
|
|
80018fa: 69bb ldr r3, [r7, #24]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_12;
|
|
80018fc: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8001900: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001902: 2302 movs r3, #2
|
|
8001904: 633b str r3, [r7, #48] @ 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001906: 2300 movs r3, #0
|
|
8001908: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800190a: 2303 movs r3, #3
|
|
800190c: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
|
|
800190e: 2308 movs r3, #8
|
|
8001910: 63fb str r3, [r7, #60] @ 0x3c
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8001912: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
8001916: 4619 mov r1, r3
|
|
8001918: 483d ldr r0, [pc, #244] @ (8001a10 <HAL_UART_MspInit+0x2d8>)
|
|
800191a: f000 ffa3 bl 8002864 <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
800191e: 2304 movs r3, #4
|
|
8001920: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001922: 2302 movs r3, #2
|
|
8001924: 633b str r3, [r7, #48] @ 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001926: 2300 movs r3, #0
|
|
8001928: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800192a: 2303 movs r3, #3
|
|
800192c: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
|
|
800192e: 2308 movs r3, #8
|
|
8001930: 63fb str r3, [r7, #60] @ 0x3c
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8001932: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
8001936: 4619 mov r1, r3
|
|
8001938: 4836 ldr r0, [pc, #216] @ (8001a14 <HAL_UART_MspInit+0x2dc>)
|
|
800193a: f000 ff93 bl 8002864 <HAL_GPIO_Init>
|
|
hdma_uart5_rx.Instance = DMA1_Stream0;
|
|
800193e: 4b36 ldr r3, [pc, #216] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
8001940: 4a36 ldr r2, [pc, #216] @ (8001a1c <HAL_UART_MspInit+0x2e4>)
|
|
8001942: 601a str r2, [r3, #0]
|
|
hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4;
|
|
8001944: 4b34 ldr r3, [pc, #208] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
8001946: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
800194a: 605a str r2, [r3, #4]
|
|
hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
800194c: 4b32 ldr r3, [pc, #200] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
800194e: 2200 movs r2, #0
|
|
8001950: 609a str r2, [r3, #8]
|
|
hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
8001952: 4b31 ldr r3, [pc, #196] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
8001954: 2200 movs r2, #0
|
|
8001956: 60da str r2, [r3, #12]
|
|
hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8001958: 4b2f ldr r3, [pc, #188] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
800195a: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
800195e: 611a str r2, [r3, #16]
|
|
hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
8001960: 4b2d ldr r3, [pc, #180] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
8001962: 2200 movs r2, #0
|
|
8001964: 615a str r2, [r3, #20]
|
|
hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
8001966: 4b2c ldr r3, [pc, #176] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
8001968: 2200 movs r2, #0
|
|
800196a: 619a str r2, [r3, #24]
|
|
hdma_uart5_rx.Init.Mode = DMA_NORMAL;
|
|
800196c: 4b2a ldr r3, [pc, #168] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
800196e: 2200 movs r2, #0
|
|
8001970: 61da str r2, [r3, #28]
|
|
hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW;
|
|
8001972: 4b29 ldr r3, [pc, #164] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
8001974: 2200 movs r2, #0
|
|
8001976: 621a str r2, [r3, #32]
|
|
hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
8001978: 4b27 ldr r3, [pc, #156] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
800197a: 2200 movs r2, #0
|
|
800197c: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK)
|
|
800197e: 4826 ldr r0, [pc, #152] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
8001980: f000 fb6e bl 8002060 <HAL_DMA_Init>
|
|
8001984: 4603 mov r3, r0
|
|
8001986: 2b00 cmp r3, #0
|
|
8001988: d001 beq.n 800198e <HAL_UART_MspInit+0x256>
|
|
Error_Handler();
|
|
800198a: f7ff fbef bl 800116c <Error_Handler>
|
|
__HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx);
|
|
800198e: 687b ldr r3, [r7, #4]
|
|
8001990: 4a21 ldr r2, [pc, #132] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
8001992: 63da str r2, [r3, #60] @ 0x3c
|
|
8001994: 4a20 ldr r2, [pc, #128] @ (8001a18 <HAL_UART_MspInit+0x2e0>)
|
|
8001996: 687b ldr r3, [r7, #4]
|
|
8001998: 6393 str r3, [r2, #56] @ 0x38
|
|
hdma_uart5_tx.Instance = DMA1_Stream7;
|
|
800199a: 4b21 ldr r3, [pc, #132] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
800199c: 4a21 ldr r2, [pc, #132] @ (8001a24 <HAL_UART_MspInit+0x2ec>)
|
|
800199e: 601a str r2, [r3, #0]
|
|
hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4;
|
|
80019a0: 4b1f ldr r3, [pc, #124] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
80019a2: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
80019a6: 605a str r2, [r3, #4]
|
|
hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
80019a8: 4b1d ldr r3, [pc, #116] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
80019aa: 2240 movs r2, #64 @ 0x40
|
|
80019ac: 609a str r2, [r3, #8]
|
|
hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
80019ae: 4b1c ldr r3, [pc, #112] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
80019b0: 2200 movs r2, #0
|
|
80019b2: 60da str r2, [r3, #12]
|
|
hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
80019b4: 4b1a ldr r3, [pc, #104] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
80019b6: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
80019ba: 611a str r2, [r3, #16]
|
|
hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
80019bc: 4b18 ldr r3, [pc, #96] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
80019be: 2200 movs r2, #0
|
|
80019c0: 615a str r2, [r3, #20]
|
|
hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
80019c2: 4b17 ldr r3, [pc, #92] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
80019c4: 2200 movs r2, #0
|
|
80019c6: 619a str r2, [r3, #24]
|
|
hdma_uart5_tx.Init.Mode = DMA_NORMAL;
|
|
80019c8: 4b15 ldr r3, [pc, #84] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
80019ca: 2200 movs r2, #0
|
|
80019cc: 61da str r2, [r3, #28]
|
|
hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW;
|
|
80019ce: 4b14 ldr r3, [pc, #80] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
80019d0: 2200 movs r2, #0
|
|
80019d2: 621a str r2, [r3, #32]
|
|
hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
80019d4: 4b12 ldr r3, [pc, #72] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
80019d6: 2200 movs r2, #0
|
|
80019d8: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK)
|
|
80019da: 4811 ldr r0, [pc, #68] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
80019dc: f000 fb40 bl 8002060 <HAL_DMA_Init>
|
|
80019e0: 4603 mov r3, r0
|
|
80019e2: 2b00 cmp r3, #0
|
|
80019e4: d001 beq.n 80019ea <HAL_UART_MspInit+0x2b2>
|
|
Error_Handler();
|
|
80019e6: f7ff fbc1 bl 800116c <Error_Handler>
|
|
__HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx);
|
|
80019ea: 687b ldr r3, [r7, #4]
|
|
80019ec: 4a0c ldr r2, [pc, #48] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
80019ee: 639a str r2, [r3, #56] @ 0x38
|
|
80019f0: 4a0b ldr r2, [pc, #44] @ (8001a20 <HAL_UART_MspInit+0x2e8>)
|
|
80019f2: 687b ldr r3, [r7, #4]
|
|
80019f4: 6393 str r3, [r2, #56] @ 0x38
|
|
HAL_NVIC_SetPriority(UART5_IRQn, 5, 0);
|
|
80019f6: 2200 movs r2, #0
|
|
80019f8: 2105 movs r1, #5
|
|
80019fa: 2035 movs r0, #53 @ 0x35
|
|
80019fc: f000 faf9 bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(UART5_IRQn);
|
|
8001a00: 2035 movs r0, #53 @ 0x35
|
|
8001a02: f000 fb12 bl 800202a <HAL_NVIC_EnableIRQ>
|
|
}
|
|
8001a06: e13d b.n 8001c84 <HAL_UART_MspInit+0x54c>
|
|
8001a08: 40005000 .word 0x40005000
|
|
8001a0c: 40023800 .word 0x40023800
|
|
8001a10: 40020800 .word 0x40020800
|
|
8001a14: 40020c00 .word 0x40020c00
|
|
8001a18: 20000b40 .word 0x20000b40
|
|
8001a1c: 40026010 .word 0x40026010
|
|
8001a20: 20000ba0 .word 0x20000ba0
|
|
8001a24: 400260b8 .word 0x400260b8
|
|
else if(uartHandle->Instance==USART1)
|
|
8001a28: 687b ldr r3, [r7, #4]
|
|
8001a2a: 681b ldr r3, [r3, #0]
|
|
8001a2c: 4a97 ldr r2, [pc, #604] @ (8001c8c <HAL_UART_MspInit+0x554>)
|
|
8001a2e: 4293 cmp r3, r2
|
|
8001a30: f040 8092 bne.w 8001b58 <HAL_UART_MspInit+0x420>
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8001a34: 2300 movs r3, #0
|
|
8001a36: 617b str r3, [r7, #20]
|
|
8001a38: 4b95 ldr r3, [pc, #596] @ (8001c90 <HAL_UART_MspInit+0x558>)
|
|
8001a3a: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001a3c: 4a94 ldr r2, [pc, #592] @ (8001c90 <HAL_UART_MspInit+0x558>)
|
|
8001a3e: f043 0310 orr.w r3, r3, #16
|
|
8001a42: 6453 str r3, [r2, #68] @ 0x44
|
|
8001a44: 4b92 ldr r3, [pc, #584] @ (8001c90 <HAL_UART_MspInit+0x558>)
|
|
8001a46: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001a48: f003 0310 and.w r3, r3, #16
|
|
8001a4c: 617b str r3, [r7, #20]
|
|
8001a4e: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001a50: 2300 movs r3, #0
|
|
8001a52: 613b str r3, [r7, #16]
|
|
8001a54: 4b8e ldr r3, [pc, #568] @ (8001c90 <HAL_UART_MspInit+0x558>)
|
|
8001a56: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001a58: 4a8d ldr r2, [pc, #564] @ (8001c90 <HAL_UART_MspInit+0x558>)
|
|
8001a5a: f043 0301 orr.w r3, r3, #1
|
|
8001a5e: 6313 str r3, [r2, #48] @ 0x30
|
|
8001a60: 4b8b ldr r3, [pc, #556] @ (8001c90 <HAL_UART_MspInit+0x558>)
|
|
8001a62: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001a64: f003 0301 and.w r3, r3, #1
|
|
8001a68: 613b str r3, [r7, #16]
|
|
8001a6a: 693b ldr r3, [r7, #16]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
|
|
8001a6c: f44f 63c0 mov.w r3, #1536 @ 0x600
|
|
8001a70: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001a72: 2302 movs r3, #2
|
|
8001a74: 633b str r3, [r7, #48] @ 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001a76: 2300 movs r3, #0
|
|
8001a78: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001a7a: 2303 movs r3, #3
|
|
8001a7c: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
8001a7e: 2307 movs r3, #7
|
|
8001a80: 63fb str r3, [r7, #60] @ 0x3c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001a82: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
8001a86: 4619 mov r1, r3
|
|
8001a88: 4882 ldr r0, [pc, #520] @ (8001c94 <HAL_UART_MspInit+0x55c>)
|
|
8001a8a: f000 feeb bl 8002864 <HAL_GPIO_Init>
|
|
hdma_usart1_rx.Instance = DMA2_Stream2;
|
|
8001a8e: 4b82 ldr r3, [pc, #520] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001a90: 4a82 ldr r2, [pc, #520] @ (8001c9c <HAL_UART_MspInit+0x564>)
|
|
8001a92: 601a str r2, [r3, #0]
|
|
hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4;
|
|
8001a94: 4b80 ldr r3, [pc, #512] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001a96: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
8001a9a: 605a str r2, [r3, #4]
|
|
hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
8001a9c: 4b7e ldr r3, [pc, #504] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001a9e: 2200 movs r2, #0
|
|
8001aa0: 609a str r2, [r3, #8]
|
|
hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
8001aa2: 4b7d ldr r3, [pc, #500] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001aa4: 2200 movs r2, #0
|
|
8001aa6: 60da str r2, [r3, #12]
|
|
hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8001aa8: 4b7b ldr r3, [pc, #492] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001aaa: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001aae: 611a str r2, [r3, #16]
|
|
hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
8001ab0: 4b79 ldr r3, [pc, #484] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001ab2: 2200 movs r2, #0
|
|
8001ab4: 615a str r2, [r3, #20]
|
|
hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
8001ab6: 4b78 ldr r3, [pc, #480] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001ab8: 2200 movs r2, #0
|
|
8001aba: 619a str r2, [r3, #24]
|
|
hdma_usart1_rx.Init.Mode = DMA_NORMAL;
|
|
8001abc: 4b76 ldr r3, [pc, #472] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001abe: 2200 movs r2, #0
|
|
8001ac0: 61da str r2, [r3, #28]
|
|
hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
|
|
8001ac2: 4b75 ldr r3, [pc, #468] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001ac4: 2200 movs r2, #0
|
|
8001ac6: 621a str r2, [r3, #32]
|
|
hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
8001ac8: 4b73 ldr r3, [pc, #460] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001aca: 2200 movs r2, #0
|
|
8001acc: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
|
|
8001ace: 4872 ldr r0, [pc, #456] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001ad0: f000 fac6 bl 8002060 <HAL_DMA_Init>
|
|
8001ad4: 4603 mov r3, r0
|
|
8001ad6: 2b00 cmp r3, #0
|
|
8001ad8: d001 beq.n 8001ade <HAL_UART_MspInit+0x3a6>
|
|
Error_Handler();
|
|
8001ada: f7ff fb47 bl 800116c <Error_Handler>
|
|
__HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx);
|
|
8001ade: 687b ldr r3, [r7, #4]
|
|
8001ae0: 4a6d ldr r2, [pc, #436] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001ae2: 63da str r2, [r3, #60] @ 0x3c
|
|
8001ae4: 4a6c ldr r2, [pc, #432] @ (8001c98 <HAL_UART_MspInit+0x560>)
|
|
8001ae6: 687b ldr r3, [r7, #4]
|
|
8001ae8: 6393 str r3, [r2, #56] @ 0x38
|
|
hdma_usart1_tx.Instance = DMA2_Stream7;
|
|
8001aea: 4b6d ldr r3, [pc, #436] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001aec: 4a6d ldr r2, [pc, #436] @ (8001ca4 <HAL_UART_MspInit+0x56c>)
|
|
8001aee: 601a str r2, [r3, #0]
|
|
hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4;
|
|
8001af0: 4b6b ldr r3, [pc, #428] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001af2: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
8001af6: 605a str r2, [r3, #4]
|
|
hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
8001af8: 4b69 ldr r3, [pc, #420] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001afa: 2240 movs r2, #64 @ 0x40
|
|
8001afc: 609a str r2, [r3, #8]
|
|
hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
8001afe: 4b68 ldr r3, [pc, #416] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001b00: 2200 movs r2, #0
|
|
8001b02: 60da str r2, [r3, #12]
|
|
hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8001b04: 4b66 ldr r3, [pc, #408] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001b06: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001b0a: 611a str r2, [r3, #16]
|
|
hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
8001b0c: 4b64 ldr r3, [pc, #400] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001b0e: 2200 movs r2, #0
|
|
8001b10: 615a str r2, [r3, #20]
|
|
hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
8001b12: 4b63 ldr r3, [pc, #396] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001b14: 2200 movs r2, #0
|
|
8001b16: 619a str r2, [r3, #24]
|
|
hdma_usart1_tx.Init.Mode = DMA_NORMAL;
|
|
8001b18: 4b61 ldr r3, [pc, #388] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001b1a: 2200 movs r2, #0
|
|
8001b1c: 61da str r2, [r3, #28]
|
|
hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
|
|
8001b1e: 4b60 ldr r3, [pc, #384] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001b20: 2200 movs r2, #0
|
|
8001b22: 621a str r2, [r3, #32]
|
|
hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
8001b24: 4b5e ldr r3, [pc, #376] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001b26: 2200 movs r2, #0
|
|
8001b28: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
|
|
8001b2a: 485d ldr r0, [pc, #372] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001b2c: f000 fa98 bl 8002060 <HAL_DMA_Init>
|
|
8001b30: 4603 mov r3, r0
|
|
8001b32: 2b00 cmp r3, #0
|
|
8001b34: d001 beq.n 8001b3a <HAL_UART_MspInit+0x402>
|
|
Error_Handler();
|
|
8001b36: f7ff fb19 bl 800116c <Error_Handler>
|
|
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx);
|
|
8001b3a: 687b ldr r3, [r7, #4]
|
|
8001b3c: 4a58 ldr r2, [pc, #352] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001b3e: 639a str r2, [r3, #56] @ 0x38
|
|
8001b40: 4a57 ldr r2, [pc, #348] @ (8001ca0 <HAL_UART_MspInit+0x568>)
|
|
8001b42: 687b ldr r3, [r7, #4]
|
|
8001b44: 6393 str r3, [r2, #56] @ 0x38
|
|
HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
|
|
8001b46: 2200 movs r2, #0
|
|
8001b48: 2105 movs r1, #5
|
|
8001b4a: 2025 movs r0, #37 @ 0x25
|
|
8001b4c: f000 fa51 bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USART1_IRQn);
|
|
8001b50: 2025 movs r0, #37 @ 0x25
|
|
8001b52: f000 fa6a bl 800202a <HAL_NVIC_EnableIRQ>
|
|
}
|
|
8001b56: e095 b.n 8001c84 <HAL_UART_MspInit+0x54c>
|
|
else if(uartHandle->Instance==USART2)
|
|
8001b58: 687b ldr r3, [r7, #4]
|
|
8001b5a: 681b ldr r3, [r3, #0]
|
|
8001b5c: 4a52 ldr r2, [pc, #328] @ (8001ca8 <HAL_UART_MspInit+0x570>)
|
|
8001b5e: 4293 cmp r3, r2
|
|
8001b60: f040 8090 bne.w 8001c84 <HAL_UART_MspInit+0x54c>
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
8001b64: 2300 movs r3, #0
|
|
8001b66: 60fb str r3, [r7, #12]
|
|
8001b68: 4b49 ldr r3, [pc, #292] @ (8001c90 <HAL_UART_MspInit+0x558>)
|
|
8001b6a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001b6c: 4a48 ldr r2, [pc, #288] @ (8001c90 <HAL_UART_MspInit+0x558>)
|
|
8001b6e: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8001b72: 6413 str r3, [r2, #64] @ 0x40
|
|
8001b74: 4b46 ldr r3, [pc, #280] @ (8001c90 <HAL_UART_MspInit+0x558>)
|
|
8001b76: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001b78: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001b7c: 60fb str r3, [r7, #12]
|
|
8001b7e: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001b80: 2300 movs r3, #0
|
|
8001b82: 60bb str r3, [r7, #8]
|
|
8001b84: 4b42 ldr r3, [pc, #264] @ (8001c90 <HAL_UART_MspInit+0x558>)
|
|
8001b86: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001b88: 4a41 ldr r2, [pc, #260] @ (8001c90 <HAL_UART_MspInit+0x558>)
|
|
8001b8a: f043 0301 orr.w r3, r3, #1
|
|
8001b8e: 6313 str r3, [r2, #48] @ 0x30
|
|
8001b90: 4b3f ldr r3, [pc, #252] @ (8001c90 <HAL_UART_MspInit+0x558>)
|
|
8001b92: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001b94: f003 0301 and.w r3, r3, #1
|
|
8001b98: 60bb str r3, [r7, #8]
|
|
8001b9a: 68bb ldr r3, [r7, #8]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
|
|
8001b9c: 230c movs r3, #12
|
|
8001b9e: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001ba0: 2302 movs r3, #2
|
|
8001ba2: 633b str r3, [r7, #48] @ 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001ba4: 2300 movs r3, #0
|
|
8001ba6: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001ba8: 2303 movs r3, #3
|
|
8001baa: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
|
8001bac: 2307 movs r3, #7
|
|
8001bae: 63fb str r3, [r7, #60] @ 0x3c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001bb0: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
8001bb4: 4619 mov r1, r3
|
|
8001bb6: 4837 ldr r0, [pc, #220] @ (8001c94 <HAL_UART_MspInit+0x55c>)
|
|
8001bb8: f000 fe54 bl 8002864 <HAL_GPIO_Init>
|
|
hdma_usart2_rx.Instance = DMA1_Stream5;
|
|
8001bbc: 4b3b ldr r3, [pc, #236] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001bbe: 4a3c ldr r2, [pc, #240] @ (8001cb0 <HAL_UART_MspInit+0x578>)
|
|
8001bc0: 601a str r2, [r3, #0]
|
|
hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4;
|
|
8001bc2: 4b3a ldr r3, [pc, #232] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001bc4: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
8001bc8: 605a str r2, [r3, #4]
|
|
hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
8001bca: 4b38 ldr r3, [pc, #224] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001bcc: 2200 movs r2, #0
|
|
8001bce: 609a str r2, [r3, #8]
|
|
hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
8001bd0: 4b36 ldr r3, [pc, #216] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001bd2: 2200 movs r2, #0
|
|
8001bd4: 60da str r2, [r3, #12]
|
|
hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8001bd6: 4b35 ldr r3, [pc, #212] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001bd8: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001bdc: 611a str r2, [r3, #16]
|
|
hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
8001bde: 4b33 ldr r3, [pc, #204] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001be0: 2200 movs r2, #0
|
|
8001be2: 615a str r2, [r3, #20]
|
|
hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
8001be4: 4b31 ldr r3, [pc, #196] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001be6: 2200 movs r2, #0
|
|
8001be8: 619a str r2, [r3, #24]
|
|
hdma_usart2_rx.Init.Mode = DMA_NORMAL;
|
|
8001bea: 4b30 ldr r3, [pc, #192] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001bec: 2200 movs r2, #0
|
|
8001bee: 61da str r2, [r3, #28]
|
|
hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW;
|
|
8001bf0: 4b2e ldr r3, [pc, #184] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001bf2: 2200 movs r2, #0
|
|
8001bf4: 621a str r2, [r3, #32]
|
|
hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
8001bf6: 4b2d ldr r3, [pc, #180] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001bf8: 2200 movs r2, #0
|
|
8001bfa: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
|
|
8001bfc: 482b ldr r0, [pc, #172] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001bfe: f000 fa2f bl 8002060 <HAL_DMA_Init>
|
|
8001c02: 4603 mov r3, r0
|
|
8001c04: 2b00 cmp r3, #0
|
|
8001c06: d001 beq.n 8001c0c <HAL_UART_MspInit+0x4d4>
|
|
Error_Handler();
|
|
8001c08: f7ff fab0 bl 800116c <Error_Handler>
|
|
__HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx);
|
|
8001c0c: 687b ldr r3, [r7, #4]
|
|
8001c0e: 4a27 ldr r2, [pc, #156] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001c10: 63da str r2, [r3, #60] @ 0x3c
|
|
8001c12: 4a26 ldr r2, [pc, #152] @ (8001cac <HAL_UART_MspInit+0x574>)
|
|
8001c14: 687b ldr r3, [r7, #4]
|
|
8001c16: 6393 str r3, [r2, #56] @ 0x38
|
|
hdma_usart2_tx.Instance = DMA1_Stream6;
|
|
8001c18: 4b26 ldr r3, [pc, #152] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c1a: 4a27 ldr r2, [pc, #156] @ (8001cb8 <HAL_UART_MspInit+0x580>)
|
|
8001c1c: 601a str r2, [r3, #0]
|
|
hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4;
|
|
8001c1e: 4b25 ldr r3, [pc, #148] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c20: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
8001c24: 605a str r2, [r3, #4]
|
|
hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
8001c26: 4b23 ldr r3, [pc, #140] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c28: 2240 movs r2, #64 @ 0x40
|
|
8001c2a: 609a str r2, [r3, #8]
|
|
hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
8001c2c: 4b21 ldr r3, [pc, #132] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c2e: 2200 movs r2, #0
|
|
8001c30: 60da str r2, [r3, #12]
|
|
hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8001c32: 4b20 ldr r3, [pc, #128] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c34: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001c38: 611a str r2, [r3, #16]
|
|
hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
8001c3a: 4b1e ldr r3, [pc, #120] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c3c: 2200 movs r2, #0
|
|
8001c3e: 615a str r2, [r3, #20]
|
|
hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
8001c40: 4b1c ldr r3, [pc, #112] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c42: 2200 movs r2, #0
|
|
8001c44: 619a str r2, [r3, #24]
|
|
hdma_usart2_tx.Init.Mode = DMA_NORMAL;
|
|
8001c46: 4b1b ldr r3, [pc, #108] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c48: 2200 movs r2, #0
|
|
8001c4a: 61da str r2, [r3, #28]
|
|
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW;
|
|
8001c4c: 4b19 ldr r3, [pc, #100] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c4e: 2200 movs r2, #0
|
|
8001c50: 621a str r2, [r3, #32]
|
|
hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
8001c52: 4b18 ldr r3, [pc, #96] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c54: 2200 movs r2, #0
|
|
8001c56: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
|
|
8001c58: 4816 ldr r0, [pc, #88] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c5a: f000 fa01 bl 8002060 <HAL_DMA_Init>
|
|
8001c5e: 4603 mov r3, r0
|
|
8001c60: 2b00 cmp r3, #0
|
|
8001c62: d001 beq.n 8001c68 <HAL_UART_MspInit+0x530>
|
|
Error_Handler();
|
|
8001c64: f7ff fa82 bl 800116c <Error_Handler>
|
|
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx);
|
|
8001c68: 687b ldr r3, [r7, #4]
|
|
8001c6a: 4a12 ldr r2, [pc, #72] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c6c: 639a str r2, [r3, #56] @ 0x38
|
|
8001c6e: 4a11 ldr r2, [pc, #68] @ (8001cb4 <HAL_UART_MspInit+0x57c>)
|
|
8001c70: 687b ldr r3, [r7, #4]
|
|
8001c72: 6393 str r3, [r2, #56] @ 0x38
|
|
HAL_NVIC_SetPriority(USART2_IRQn, 5, 0);
|
|
8001c74: 2200 movs r2, #0
|
|
8001c76: 2105 movs r1, #5
|
|
8001c78: 2026 movs r0, #38 @ 0x26
|
|
8001c7a: f000 f9ba bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USART2_IRQn);
|
|
8001c7e: 2026 movs r0, #38 @ 0x26
|
|
8001c80: f000 f9d3 bl 800202a <HAL_NVIC_EnableIRQ>
|
|
}
|
|
8001c84: bf00 nop
|
|
8001c86: 3740 adds r7, #64 @ 0x40
|
|
8001c88: 46bd mov sp, r7
|
|
8001c8a: bd80 pop {r7, pc}
|
|
8001c8c: 40011000 .word 0x40011000
|
|
8001c90: 40023800 .word 0x40023800
|
|
8001c94: 40020000 .word 0x40020000
|
|
8001c98: 20000c00 .word 0x20000c00
|
|
8001c9c: 40026440 .word 0x40026440
|
|
8001ca0: 20000c60 .word 0x20000c60
|
|
8001ca4: 400264b8 .word 0x400264b8
|
|
8001ca8: 40004400 .word 0x40004400
|
|
8001cac: 20000cc0 .word 0x20000cc0
|
|
8001cb0: 40026088 .word 0x40026088
|
|
8001cb4: 20000d20 .word 0x20000d20
|
|
8001cb8: 400260a0 .word 0x400260a0
|
|
|
|
08001cbc <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* set stack pointer */
|
|
8001cbc: f8df d034 ldr.w sp, [pc, #52] @ 8001cf4 <LoopFillZerobss+0xe>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8001cc0: f7ff fb34 bl 800132c <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8001cc4: 480c ldr r0, [pc, #48] @ (8001cf8 <LoopFillZerobss+0x12>)
|
|
ldr r1, =_edata
|
|
8001cc6: 490d ldr r1, [pc, #52] @ (8001cfc <LoopFillZerobss+0x16>)
|
|
ldr r2, =_sidata
|
|
8001cc8: 4a0d ldr r2, [pc, #52] @ (8001d00 <LoopFillZerobss+0x1a>)
|
|
movs r3, #0
|
|
8001cca: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
8001ccc: e002 b.n 8001cd4 <LoopCopyDataInit>
|
|
|
|
08001cce <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
8001cce: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8001cd0: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8001cd2: 3304 adds r3, #4
|
|
|
|
08001cd4 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8001cd4: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8001cd6: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8001cd8: d3f9 bcc.n 8001cce <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
8001cda: 4a0a ldr r2, [pc, #40] @ (8001d04 <LoopFillZerobss+0x1e>)
|
|
ldr r4, =_ebss
|
|
8001cdc: 4c0a ldr r4, [pc, #40] @ (8001d08 <LoopFillZerobss+0x22>)
|
|
movs r3, #0
|
|
8001cde: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8001ce0: e001 b.n 8001ce6 <LoopFillZerobss>
|
|
|
|
08001ce2 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8001ce2: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8001ce4: 3204 adds r2, #4
|
|
|
|
08001ce6 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8001ce6: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8001ce8: d3fb bcc.n 8001ce2 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8001cea: f009 f8b1 bl 800ae50 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
8001cee: f7fe fe1b bl 8000928 <main>
|
|
bx lr
|
|
8001cf2: 4770 bx lr
|
|
ldr sp, =_estack /* set stack pointer */
|
|
8001cf4: 20020000 .word 0x20020000
|
|
ldr r0, =_sdata
|
|
8001cf8: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
8001cfc: 200001a0 .word 0x200001a0
|
|
ldr r2, =_sidata
|
|
8001d00: 0800af38 .word 0x0800af38
|
|
ldr r2, =_sbss
|
|
8001d04: 200001a0 .word 0x200001a0
|
|
ldr r4, =_ebss
|
|
8001d08: 2000175c .word 0x2000175c
|
|
|
|
08001d0c <ADC_IRQHandler>:
|
|
* @retval None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8001d0c: e7fe b.n 8001d0c <ADC_IRQHandler>
|
|
...
|
|
|
|
08001d10 <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8001d10: b580 push {r7, lr}
|
|
8001d12: af00 add r7, sp, #0
|
|
/* Configure Flash prefetch, Instruction cache, Data cache */
|
|
#if (INSTRUCTION_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
|
|
8001d14: 4b0e ldr r3, [pc, #56] @ (8001d50 <HAL_Init+0x40>)
|
|
8001d16: 681b ldr r3, [r3, #0]
|
|
8001d18: 4a0d ldr r2, [pc, #52] @ (8001d50 <HAL_Init+0x40>)
|
|
8001d1a: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8001d1e: 6013 str r3, [r2, #0]
|
|
#endif /* INSTRUCTION_CACHE_ENABLE */
|
|
|
|
#if (DATA_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_DATA_CACHE_ENABLE();
|
|
8001d20: 4b0b ldr r3, [pc, #44] @ (8001d50 <HAL_Init+0x40>)
|
|
8001d22: 681b ldr r3, [r3, #0]
|
|
8001d24: 4a0a ldr r2, [pc, #40] @ (8001d50 <HAL_Init+0x40>)
|
|
8001d26: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8001d2a: 6013 str r3, [r2, #0]
|
|
#endif /* DATA_CACHE_ENABLE */
|
|
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
8001d2c: 4b08 ldr r3, [pc, #32] @ (8001d50 <HAL_Init+0x40>)
|
|
8001d2e: 681b ldr r3, [r3, #0]
|
|
8001d30: 4a07 ldr r2, [pc, #28] @ (8001d50 <HAL_Init+0x40>)
|
|
8001d32: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8001d36: 6013 str r3, [r2, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8001d38: 2003 movs r0, #3
|
|
8001d3a: f000 f94f bl 8001fdc <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
8001d3e: 200f movs r0, #15
|
|
8001d40: f000 f808 bl 8001d54 <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8001d44: f7ff fa18 bl 8001178 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8001d48: 2300 movs r3, #0
|
|
}
|
|
8001d4a: 4618 mov r0, r3
|
|
8001d4c: bd80 pop {r7, pc}
|
|
8001d4e: bf00 nop
|
|
8001d50: 40023c00 .word 0x40023c00
|
|
|
|
08001d54 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8001d54: b580 push {r7, lr}
|
|
8001d56: b082 sub sp, #8
|
|
8001d58: af00 add r7, sp, #0
|
|
8001d5a: 6078 str r0, [r7, #4]
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
8001d5c: 4b12 ldr r3, [pc, #72] @ (8001da8 <HAL_InitTick+0x54>)
|
|
8001d5e: 681a ldr r2, [r3, #0]
|
|
8001d60: 4b12 ldr r3, [pc, #72] @ (8001dac <HAL_InitTick+0x58>)
|
|
8001d62: 781b ldrb r3, [r3, #0]
|
|
8001d64: 4619 mov r1, r3
|
|
8001d66: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8001d6a: fbb3 f3f1 udiv r3, r3, r1
|
|
8001d6e: fbb2 f3f3 udiv r3, r2, r3
|
|
8001d72: 4618 mov r0, r3
|
|
8001d74: f000 f967 bl 8002046 <HAL_SYSTICK_Config>
|
|
8001d78: 4603 mov r3, r0
|
|
8001d7a: 2b00 cmp r3, #0
|
|
8001d7c: d001 beq.n 8001d82 <HAL_InitTick+0x2e>
|
|
{
|
|
return HAL_ERROR;
|
|
8001d7e: 2301 movs r3, #1
|
|
8001d80: e00e b.n 8001da0 <HAL_InitTick+0x4c>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8001d82: 687b ldr r3, [r7, #4]
|
|
8001d84: 2b0f cmp r3, #15
|
|
8001d86: d80a bhi.n 8001d9e <HAL_InitTick+0x4a>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
8001d88: 2200 movs r2, #0
|
|
8001d8a: 6879 ldr r1, [r7, #4]
|
|
8001d8c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8001d90: f000 f92f bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8001d94: 4a06 ldr r2, [pc, #24] @ (8001db0 <HAL_InitTick+0x5c>)
|
|
8001d96: 687b ldr r3, [r7, #4]
|
|
8001d98: 6013 str r3, [r2, #0]
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8001d9a: 2300 movs r3, #0
|
|
8001d9c: e000 b.n 8001da0 <HAL_InitTick+0x4c>
|
|
return HAL_ERROR;
|
|
8001d9e: 2301 movs r3, #1
|
|
}
|
|
8001da0: 4618 mov r0, r3
|
|
8001da2: 3708 adds r7, #8
|
|
8001da4: 46bd mov sp, r7
|
|
8001da6: bd80 pop {r7, pc}
|
|
8001da8: 20000090 .word 0x20000090
|
|
8001dac: 20000098 .word 0x20000098
|
|
8001db0: 20000094 .word 0x20000094
|
|
|
|
08001db4 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8001db4: b480 push {r7}
|
|
8001db6: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
8001db8: 4b06 ldr r3, [pc, #24] @ (8001dd4 <HAL_IncTick+0x20>)
|
|
8001dba: 781b ldrb r3, [r3, #0]
|
|
8001dbc: 461a mov r2, r3
|
|
8001dbe: 4b06 ldr r3, [pc, #24] @ (8001dd8 <HAL_IncTick+0x24>)
|
|
8001dc0: 681b ldr r3, [r3, #0]
|
|
8001dc2: 4413 add r3, r2
|
|
8001dc4: 4a04 ldr r2, [pc, #16] @ (8001dd8 <HAL_IncTick+0x24>)
|
|
8001dc6: 6013 str r3, [r2, #0]
|
|
}
|
|
8001dc8: bf00 nop
|
|
8001dca: 46bd mov sp, r7
|
|
8001dcc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001dd0: 4770 bx lr
|
|
8001dd2: bf00 nop
|
|
8001dd4: 20000098 .word 0x20000098
|
|
8001dd8: 20000d80 .word 0x20000d80
|
|
|
|
08001ddc <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8001ddc: b480 push {r7}
|
|
8001dde: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8001de0: 4b03 ldr r3, [pc, #12] @ (8001df0 <HAL_GetTick+0x14>)
|
|
8001de2: 681b ldr r3, [r3, #0]
|
|
}
|
|
8001de4: 4618 mov r0, r3
|
|
8001de6: 46bd mov sp, r7
|
|
8001de8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001dec: 4770 bx lr
|
|
8001dee: bf00 nop
|
|
8001df0: 20000d80 .word 0x20000d80
|
|
|
|
08001df4 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8001df4: b580 push {r7, lr}
|
|
8001df6: b084 sub sp, #16
|
|
8001df8: af00 add r7, sp, #0
|
|
8001dfa: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8001dfc: f7ff ffee bl 8001ddc <HAL_GetTick>
|
|
8001e00: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8001e02: 687b ldr r3, [r7, #4]
|
|
8001e04: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8001e06: 68fb ldr r3, [r7, #12]
|
|
8001e08: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8001e0c: d005 beq.n 8001e1a <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
8001e0e: 4b0a ldr r3, [pc, #40] @ (8001e38 <HAL_Delay+0x44>)
|
|
8001e10: 781b ldrb r3, [r3, #0]
|
|
8001e12: 461a mov r2, r3
|
|
8001e14: 68fb ldr r3, [r7, #12]
|
|
8001e16: 4413 add r3, r2
|
|
8001e18: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while((HAL_GetTick() - tickstart) < wait)
|
|
8001e1a: bf00 nop
|
|
8001e1c: f7ff ffde bl 8001ddc <HAL_GetTick>
|
|
8001e20: 4602 mov r2, r0
|
|
8001e22: 68bb ldr r3, [r7, #8]
|
|
8001e24: 1ad3 subs r3, r2, r3
|
|
8001e26: 68fa ldr r2, [r7, #12]
|
|
8001e28: 429a cmp r2, r3
|
|
8001e2a: d8f7 bhi.n 8001e1c <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
8001e2c: bf00 nop
|
|
8001e2e: bf00 nop
|
|
8001e30: 3710 adds r7, #16
|
|
8001e32: 46bd mov sp, r7
|
|
8001e34: bd80 pop {r7, pc}
|
|
8001e36: bf00 nop
|
|
8001e38: 20000098 .word 0x20000098
|
|
|
|
08001e3c <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001e3c: b480 push {r7}
|
|
8001e3e: b085 sub sp, #20
|
|
8001e40: af00 add r7, sp, #0
|
|
8001e42: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8001e44: 687b ldr r3, [r7, #4]
|
|
8001e46: f003 0307 and.w r3, r3, #7
|
|
8001e4a: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
8001e4c: 4b0c ldr r3, [pc, #48] @ (8001e80 <__NVIC_SetPriorityGrouping+0x44>)
|
|
8001e4e: 68db ldr r3, [r3, #12]
|
|
8001e50: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
8001e52: 68ba ldr r2, [r7, #8]
|
|
8001e54: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
8001e58: 4013 ands r3, r2
|
|
8001e5a: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
8001e5c: 68fb ldr r3, [r7, #12]
|
|
8001e5e: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
8001e60: 68bb ldr r3, [r7, #8]
|
|
8001e62: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
8001e64: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
8001e68: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8001e6c: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
8001e6e: 4a04 ldr r2, [pc, #16] @ (8001e80 <__NVIC_SetPriorityGrouping+0x44>)
|
|
8001e70: 68bb ldr r3, [r7, #8]
|
|
8001e72: 60d3 str r3, [r2, #12]
|
|
}
|
|
8001e74: bf00 nop
|
|
8001e76: 3714 adds r7, #20
|
|
8001e78: 46bd mov sp, r7
|
|
8001e7a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001e7e: 4770 bx lr
|
|
8001e80: e000ed00 .word 0xe000ed00
|
|
|
|
08001e84 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8001e84: b480 push {r7}
|
|
8001e86: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8001e88: 4b04 ldr r3, [pc, #16] @ (8001e9c <__NVIC_GetPriorityGrouping+0x18>)
|
|
8001e8a: 68db ldr r3, [r3, #12]
|
|
8001e8c: 0a1b lsrs r3, r3, #8
|
|
8001e8e: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8001e92: 4618 mov r0, r3
|
|
8001e94: 46bd mov sp, r7
|
|
8001e96: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001e9a: 4770 bx lr
|
|
8001e9c: e000ed00 .word 0xe000ed00
|
|
|
|
08001ea0 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001ea0: b480 push {r7}
|
|
8001ea2: b083 sub sp, #12
|
|
8001ea4: af00 add r7, sp, #0
|
|
8001ea6: 4603 mov r3, r0
|
|
8001ea8: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001eaa: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001eae: 2b00 cmp r3, #0
|
|
8001eb0: db0b blt.n 8001eca <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8001eb2: 79fb ldrb r3, [r7, #7]
|
|
8001eb4: f003 021f and.w r2, r3, #31
|
|
8001eb8: 4907 ldr r1, [pc, #28] @ (8001ed8 <__NVIC_EnableIRQ+0x38>)
|
|
8001eba: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001ebe: 095b lsrs r3, r3, #5
|
|
8001ec0: 2001 movs r0, #1
|
|
8001ec2: fa00 f202 lsl.w r2, r0, r2
|
|
8001ec6: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
8001eca: bf00 nop
|
|
8001ecc: 370c adds r7, #12
|
|
8001ece: 46bd mov sp, r7
|
|
8001ed0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001ed4: 4770 bx lr
|
|
8001ed6: bf00 nop
|
|
8001ed8: e000e100 .word 0xe000e100
|
|
|
|
08001edc <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8001edc: b480 push {r7}
|
|
8001ede: b083 sub sp, #12
|
|
8001ee0: af00 add r7, sp, #0
|
|
8001ee2: 4603 mov r3, r0
|
|
8001ee4: 6039 str r1, [r7, #0]
|
|
8001ee6: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001ee8: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001eec: 2b00 cmp r3, #0
|
|
8001eee: db0a blt.n 8001f06 <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001ef0: 683b ldr r3, [r7, #0]
|
|
8001ef2: b2da uxtb r2, r3
|
|
8001ef4: 490c ldr r1, [pc, #48] @ (8001f28 <__NVIC_SetPriority+0x4c>)
|
|
8001ef6: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001efa: 0112 lsls r2, r2, #4
|
|
8001efc: b2d2 uxtb r2, r2
|
|
8001efe: 440b add r3, r1
|
|
8001f00: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8001f04: e00a b.n 8001f1c <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001f06: 683b ldr r3, [r7, #0]
|
|
8001f08: b2da uxtb r2, r3
|
|
8001f0a: 4908 ldr r1, [pc, #32] @ (8001f2c <__NVIC_SetPriority+0x50>)
|
|
8001f0c: 79fb ldrb r3, [r7, #7]
|
|
8001f0e: f003 030f and.w r3, r3, #15
|
|
8001f12: 3b04 subs r3, #4
|
|
8001f14: 0112 lsls r2, r2, #4
|
|
8001f16: b2d2 uxtb r2, r2
|
|
8001f18: 440b add r3, r1
|
|
8001f1a: 761a strb r2, [r3, #24]
|
|
}
|
|
8001f1c: bf00 nop
|
|
8001f1e: 370c adds r7, #12
|
|
8001f20: 46bd mov sp, r7
|
|
8001f22: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001f26: 4770 bx lr
|
|
8001f28: e000e100 .word 0xe000e100
|
|
8001f2c: e000ed00 .word 0xe000ed00
|
|
|
|
08001f30 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001f30: b480 push {r7}
|
|
8001f32: b089 sub sp, #36 @ 0x24
|
|
8001f34: af00 add r7, sp, #0
|
|
8001f36: 60f8 str r0, [r7, #12]
|
|
8001f38: 60b9 str r1, [r7, #8]
|
|
8001f3a: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8001f3c: 68fb ldr r3, [r7, #12]
|
|
8001f3e: f003 0307 and.w r3, r3, #7
|
|
8001f42: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8001f44: 69fb ldr r3, [r7, #28]
|
|
8001f46: f1c3 0307 rsb r3, r3, #7
|
|
8001f4a: 2b04 cmp r3, #4
|
|
8001f4c: bf28 it cs
|
|
8001f4e: 2304 movcs r3, #4
|
|
8001f50: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8001f52: 69fb ldr r3, [r7, #28]
|
|
8001f54: 3304 adds r3, #4
|
|
8001f56: 2b06 cmp r3, #6
|
|
8001f58: d902 bls.n 8001f60 <NVIC_EncodePriority+0x30>
|
|
8001f5a: 69fb ldr r3, [r7, #28]
|
|
8001f5c: 3b03 subs r3, #3
|
|
8001f5e: e000 b.n 8001f62 <NVIC_EncodePriority+0x32>
|
|
8001f60: 2300 movs r3, #0
|
|
8001f62: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8001f64: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8001f68: 69bb ldr r3, [r7, #24]
|
|
8001f6a: fa02 f303 lsl.w r3, r2, r3
|
|
8001f6e: 43da mvns r2, r3
|
|
8001f70: 68bb ldr r3, [r7, #8]
|
|
8001f72: 401a ands r2, r3
|
|
8001f74: 697b ldr r3, [r7, #20]
|
|
8001f76: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8001f78: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8001f7c: 697b ldr r3, [r7, #20]
|
|
8001f7e: fa01 f303 lsl.w r3, r1, r3
|
|
8001f82: 43d9 mvns r1, r3
|
|
8001f84: 687b ldr r3, [r7, #4]
|
|
8001f86: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8001f88: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
8001f8a: 4618 mov r0, r3
|
|
8001f8c: 3724 adds r7, #36 @ 0x24
|
|
8001f8e: 46bd mov sp, r7
|
|
8001f90: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001f94: 4770 bx lr
|
|
...
|
|
|
|
08001f98 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
8001f98: b580 push {r7, lr}
|
|
8001f9a: b082 sub sp, #8
|
|
8001f9c: af00 add r7, sp, #0
|
|
8001f9e: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8001fa0: 687b ldr r3, [r7, #4]
|
|
8001fa2: 3b01 subs r3, #1
|
|
8001fa4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8001fa8: d301 bcc.n 8001fae <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
8001faa: 2301 movs r3, #1
|
|
8001fac: e00f b.n 8001fce <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8001fae: 4a0a ldr r2, [pc, #40] @ (8001fd8 <SysTick_Config+0x40>)
|
|
8001fb0: 687b ldr r3, [r7, #4]
|
|
8001fb2: 3b01 subs r3, #1
|
|
8001fb4: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8001fb6: 210f movs r1, #15
|
|
8001fb8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8001fbc: f7ff ff8e bl 8001edc <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8001fc0: 4b05 ldr r3, [pc, #20] @ (8001fd8 <SysTick_Config+0x40>)
|
|
8001fc2: 2200 movs r2, #0
|
|
8001fc4: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8001fc6: 4b04 ldr r3, [pc, #16] @ (8001fd8 <SysTick_Config+0x40>)
|
|
8001fc8: 2207 movs r2, #7
|
|
8001fca: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8001fcc: 2300 movs r3, #0
|
|
}
|
|
8001fce: 4618 mov r0, r3
|
|
8001fd0: 3708 adds r7, #8
|
|
8001fd2: 46bd mov sp, r7
|
|
8001fd4: bd80 pop {r7, pc}
|
|
8001fd6: bf00 nop
|
|
8001fd8: e000e010 .word 0xe000e010
|
|
|
|
08001fdc <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001fdc: b580 push {r7, lr}
|
|
8001fde: b082 sub sp, #8
|
|
8001fe0: af00 add r7, sp, #0
|
|
8001fe2: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8001fe4: 6878 ldr r0, [r7, #4]
|
|
8001fe6: f7ff ff29 bl 8001e3c <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8001fea: bf00 nop
|
|
8001fec: 3708 adds r7, #8
|
|
8001fee: 46bd mov sp, r7
|
|
8001ff0: bd80 pop {r7, pc}
|
|
|
|
08001ff2 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001ff2: b580 push {r7, lr}
|
|
8001ff4: b086 sub sp, #24
|
|
8001ff6: af00 add r7, sp, #0
|
|
8001ff8: 4603 mov r3, r0
|
|
8001ffa: 60b9 str r1, [r7, #8]
|
|
8001ffc: 607a str r2, [r7, #4]
|
|
8001ffe: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
8002000: 2300 movs r3, #0
|
|
8002002: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8002004: f7ff ff3e bl 8001e84 <__NVIC_GetPriorityGrouping>
|
|
8002008: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
800200a: 687a ldr r2, [r7, #4]
|
|
800200c: 68b9 ldr r1, [r7, #8]
|
|
800200e: 6978 ldr r0, [r7, #20]
|
|
8002010: f7ff ff8e bl 8001f30 <NVIC_EncodePriority>
|
|
8002014: 4602 mov r2, r0
|
|
8002016: f997 300f ldrsb.w r3, [r7, #15]
|
|
800201a: 4611 mov r1, r2
|
|
800201c: 4618 mov r0, r3
|
|
800201e: f7ff ff5d bl 8001edc <__NVIC_SetPriority>
|
|
}
|
|
8002022: bf00 nop
|
|
8002024: 3718 adds r7, #24
|
|
8002026: 46bd mov sp, r7
|
|
8002028: bd80 pop {r7, pc}
|
|
|
|
0800202a <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
800202a: b580 push {r7, lr}
|
|
800202c: b082 sub sp, #8
|
|
800202e: af00 add r7, sp, #0
|
|
8002030: 4603 mov r3, r0
|
|
8002032: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8002034: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8002038: 4618 mov r0, r3
|
|
800203a: f7ff ff31 bl 8001ea0 <__NVIC_EnableIRQ>
|
|
}
|
|
800203e: bf00 nop
|
|
8002040: 3708 adds r7, #8
|
|
8002042: 46bd mov sp, r7
|
|
8002044: bd80 pop {r7, pc}
|
|
|
|
08002046 <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
8002046: b580 push {r7, lr}
|
|
8002048: b082 sub sp, #8
|
|
800204a: af00 add r7, sp, #0
|
|
800204c: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
800204e: 6878 ldr r0, [r7, #4]
|
|
8002050: f7ff ffa2 bl 8001f98 <SysTick_Config>
|
|
8002054: 4603 mov r3, r0
|
|
}
|
|
8002056: 4618 mov r0, r3
|
|
8002058: 3708 adds r7, #8
|
|
800205a: 46bd mov sp, r7
|
|
800205c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08002060 <HAL_DMA_Init>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8002060: b580 push {r7, lr}
|
|
8002062: b086 sub sp, #24
|
|
8002064: af00 add r7, sp, #0
|
|
8002066: 6078 str r0, [r7, #4]
|
|
uint32_t tmp = 0U;
|
|
8002068: 2300 movs r3, #0
|
|
800206a: 617b str r3, [r7, #20]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
800206c: f7ff feb6 bl 8001ddc <HAL_GetTick>
|
|
8002070: 6138 str r0, [r7, #16]
|
|
DMA_Base_Registers *regs;
|
|
|
|
/* Check the DMA peripheral state */
|
|
if(hdma == NULL)
|
|
8002072: 687b ldr r3, [r7, #4]
|
|
8002074: 2b00 cmp r3, #0
|
|
8002076: d101 bne.n 800207c <HAL_DMA_Init+0x1c>
|
|
{
|
|
return HAL_ERROR;
|
|
8002078: 2301 movs r3, #1
|
|
800207a: e099 b.n 80021b0 <HAL_DMA_Init+0x150>
|
|
assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
|
|
assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
|
|
}
|
|
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
800207c: 687b ldr r3, [r7, #4]
|
|
800207e: 2202 movs r2, #2
|
|
8002080: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Allocate lock resource */
|
|
__HAL_UNLOCK(hdma);
|
|
8002084: 687b ldr r3, [r7, #4]
|
|
8002086: 2200 movs r2, #0
|
|
8002088: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
800208c: 687b ldr r3, [r7, #4]
|
|
800208e: 681b ldr r3, [r3, #0]
|
|
8002090: 681a ldr r2, [r3, #0]
|
|
8002092: 687b ldr r3, [r7, #4]
|
|
8002094: 681b ldr r3, [r3, #0]
|
|
8002096: f022 0201 bic.w r2, r2, #1
|
|
800209a: 601a str r2, [r3, #0]
|
|
|
|
/* Check if the DMA Stream is effectively disabled */
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
|
|
800209c: e00f b.n 80020be <HAL_DMA_Init+0x5e>
|
|
{
|
|
/* Check for the Timeout */
|
|
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
|
|
800209e: f7ff fe9d bl 8001ddc <HAL_GetTick>
|
|
80020a2: 4602 mov r2, r0
|
|
80020a4: 693b ldr r3, [r7, #16]
|
|
80020a6: 1ad3 subs r3, r2, r3
|
|
80020a8: 2b05 cmp r3, #5
|
|
80020aa: d908 bls.n 80020be <HAL_DMA_Init+0x5e>
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
|
80020ac: 687b ldr r3, [r7, #4]
|
|
80020ae: 2220 movs r2, #32
|
|
80020b0: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_TIMEOUT;
|
|
80020b2: 687b ldr r3, [r7, #4]
|
|
80020b4: 2203 movs r2, #3
|
|
80020b6: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
return HAL_TIMEOUT;
|
|
80020ba: 2303 movs r3, #3
|
|
80020bc: e078 b.n 80021b0 <HAL_DMA_Init+0x150>
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
|
|
80020be: 687b ldr r3, [r7, #4]
|
|
80020c0: 681b ldr r3, [r3, #0]
|
|
80020c2: 681b ldr r3, [r3, #0]
|
|
80020c4: f003 0301 and.w r3, r3, #1
|
|
80020c8: 2b00 cmp r3, #0
|
|
80020ca: d1e8 bne.n 800209e <HAL_DMA_Init+0x3e>
|
|
}
|
|
}
|
|
|
|
/* Get the CR register value */
|
|
tmp = hdma->Instance->CR;
|
|
80020cc: 687b ldr r3, [r7, #4]
|
|
80020ce: 681b ldr r3, [r3, #0]
|
|
80020d0: 681b ldr r3, [r3, #0]
|
|
80020d2: 617b str r3, [r7, #20]
|
|
|
|
/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
|
|
tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
|
|
80020d4: 697a ldr r2, [r7, #20]
|
|
80020d6: 4b38 ldr r3, [pc, #224] @ (80021b8 <HAL_DMA_Init+0x158>)
|
|
80020d8: 4013 ands r3, r2
|
|
80020da: 617b str r3, [r7, #20]
|
|
DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
|
|
DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
|
|
DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
|
|
|
|
/* Prepare the DMA Stream configuration */
|
|
tmp |= hdma->Init.Channel | hdma->Init.Direction |
|
|
80020dc: 687b ldr r3, [r7, #4]
|
|
80020de: 685a ldr r2, [r3, #4]
|
|
80020e0: 687b ldr r3, [r7, #4]
|
|
80020e2: 689b ldr r3, [r3, #8]
|
|
80020e4: 431a orrs r2, r3
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
80020e6: 687b ldr r3, [r7, #4]
|
|
80020e8: 68db ldr r3, [r3, #12]
|
|
tmp |= hdma->Init.Channel | hdma->Init.Direction |
|
|
80020ea: 431a orrs r2, r3
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
80020ec: 687b ldr r3, [r7, #4]
|
|
80020ee: 691b ldr r3, [r3, #16]
|
|
80020f0: 431a orrs r2, r3
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
80020f2: 687b ldr r3, [r7, #4]
|
|
80020f4: 695b ldr r3, [r3, #20]
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
80020f6: 431a orrs r2, r3
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
80020f8: 687b ldr r3, [r7, #4]
|
|
80020fa: 699b ldr r3, [r3, #24]
|
|
80020fc: 431a orrs r2, r3
|
|
hdma->Init.Mode | hdma->Init.Priority;
|
|
80020fe: 687b ldr r3, [r7, #4]
|
|
8002100: 69db ldr r3, [r3, #28]
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
8002102: 431a orrs r2, r3
|
|
hdma->Init.Mode | hdma->Init.Priority;
|
|
8002104: 687b ldr r3, [r7, #4]
|
|
8002106: 6a1b ldr r3, [r3, #32]
|
|
8002108: 4313 orrs r3, r2
|
|
tmp |= hdma->Init.Channel | hdma->Init.Direction |
|
|
800210a: 697a ldr r2, [r7, #20]
|
|
800210c: 4313 orrs r3, r2
|
|
800210e: 617b str r3, [r7, #20]
|
|
|
|
/* the Memory burst and peripheral burst are not used when the FIFO is disabled */
|
|
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
|
|
8002110: 687b ldr r3, [r7, #4]
|
|
8002112: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8002114: 2b04 cmp r3, #4
|
|
8002116: d107 bne.n 8002128 <HAL_DMA_Init+0xc8>
|
|
{
|
|
/* Get memory burst and peripheral burst */
|
|
tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
|
|
8002118: 687b ldr r3, [r7, #4]
|
|
800211a: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800211c: 687b ldr r3, [r7, #4]
|
|
800211e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8002120: 4313 orrs r3, r2
|
|
8002122: 697a ldr r2, [r7, #20]
|
|
8002124: 4313 orrs r3, r2
|
|
8002126: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to DMA Stream CR register */
|
|
hdma->Instance->CR = tmp;
|
|
8002128: 687b ldr r3, [r7, #4]
|
|
800212a: 681b ldr r3, [r3, #0]
|
|
800212c: 697a ldr r2, [r7, #20]
|
|
800212e: 601a str r2, [r3, #0]
|
|
|
|
/* Get the FCR register value */
|
|
tmp = hdma->Instance->FCR;
|
|
8002130: 687b ldr r3, [r7, #4]
|
|
8002132: 681b ldr r3, [r3, #0]
|
|
8002134: 695b ldr r3, [r3, #20]
|
|
8002136: 617b str r3, [r7, #20]
|
|
|
|
/* Clear Direct mode and FIFO threshold bits */
|
|
tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
|
|
8002138: 697b ldr r3, [r7, #20]
|
|
800213a: f023 0307 bic.w r3, r3, #7
|
|
800213e: 617b str r3, [r7, #20]
|
|
|
|
/* Prepare the DMA Stream FIFO configuration */
|
|
tmp |= hdma->Init.FIFOMode;
|
|
8002140: 687b ldr r3, [r7, #4]
|
|
8002142: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8002144: 697a ldr r2, [r7, #20]
|
|
8002146: 4313 orrs r3, r2
|
|
8002148: 617b str r3, [r7, #20]
|
|
|
|
/* The FIFO threshold is not used when the FIFO mode is disabled */
|
|
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
|
|
800214a: 687b ldr r3, [r7, #4]
|
|
800214c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800214e: 2b04 cmp r3, #4
|
|
8002150: d117 bne.n 8002182 <HAL_DMA_Init+0x122>
|
|
{
|
|
/* Get the FIFO threshold */
|
|
tmp |= hdma->Init.FIFOThreshold;
|
|
8002152: 687b ldr r3, [r7, #4]
|
|
8002154: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002156: 697a ldr r2, [r7, #20]
|
|
8002158: 4313 orrs r3, r2
|
|
800215a: 617b str r3, [r7, #20]
|
|
|
|
/* Check compatibility between FIFO threshold level and size of the memory burst */
|
|
/* for INCR4, INCR8, INCR16 bursts */
|
|
if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
|
|
800215c: 687b ldr r3, [r7, #4]
|
|
800215e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8002160: 2b00 cmp r3, #0
|
|
8002162: d00e beq.n 8002182 <HAL_DMA_Init+0x122>
|
|
{
|
|
if (DMA_CheckFifoParam(hdma) != HAL_OK)
|
|
8002164: 6878 ldr r0, [r7, #4]
|
|
8002166: f000 fb01 bl 800276c <DMA_CheckFifoParam>
|
|
800216a: 4603 mov r3, r0
|
|
800216c: 2b00 cmp r3, #0
|
|
800216e: d008 beq.n 8002182 <HAL_DMA_Init+0x122>
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
|
|
8002170: 687b ldr r3, [r7, #4]
|
|
8002172: 2240 movs r2, #64 @ 0x40
|
|
8002174: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8002176: 687b ldr r3, [r7, #4]
|
|
8002178: 2201 movs r2, #1
|
|
800217a: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
return HAL_ERROR;
|
|
800217e: 2301 movs r3, #1
|
|
8002180: e016 b.n 80021b0 <HAL_DMA_Init+0x150>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Write to DMA Stream FCR */
|
|
hdma->Instance->FCR = tmp;
|
|
8002182: 687b ldr r3, [r7, #4]
|
|
8002184: 681b ldr r3, [r3, #0]
|
|
8002186: 697a ldr r2, [r7, #20]
|
|
8002188: 615a str r2, [r3, #20]
|
|
|
|
/* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
|
|
DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
|
|
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
|
|
800218a: 6878 ldr r0, [r7, #4]
|
|
800218c: f000 fab8 bl 8002700 <DMA_CalcBaseAndBitshift>
|
|
8002190: 4603 mov r3, r0
|
|
8002192: 60fb str r3, [r7, #12]
|
|
|
|
/* Clear all interrupt flags */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
8002194: 687b ldr r3, [r7, #4]
|
|
8002196: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002198: 223f movs r2, #63 @ 0x3f
|
|
800219a: 409a lsls r2, r3
|
|
800219c: 68fb ldr r3, [r7, #12]
|
|
800219e: 609a str r2, [r3, #8]
|
|
|
|
/* Initialize the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
80021a0: 687b ldr r3, [r7, #4]
|
|
80021a2: 2200 movs r2, #0
|
|
80021a4: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Initialize the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80021a6: 687b ldr r3, [r7, #4]
|
|
80021a8: 2201 movs r2, #1
|
|
80021aa: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
return HAL_OK;
|
|
80021ae: 2300 movs r3, #0
|
|
}
|
|
80021b0: 4618 mov r0, r3
|
|
80021b2: 3718 adds r7, #24
|
|
80021b4: 46bd mov sp, r7
|
|
80021b6: bd80 pop {r7, pc}
|
|
80021b8: f010803f .word 0xf010803f
|
|
|
|
080021bc <HAL_DMA_Start_IT>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
80021bc: b580 push {r7, lr}
|
|
80021be: b086 sub sp, #24
|
|
80021c0: af00 add r7, sp, #0
|
|
80021c2: 60f8 str r0, [r7, #12]
|
|
80021c4: 60b9 str r1, [r7, #8]
|
|
80021c6: 607a str r2, [r7, #4]
|
|
80021c8: 603b str r3, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80021ca: 2300 movs r3, #0
|
|
80021cc: 75fb strb r3, [r7, #23]
|
|
|
|
/* calculate DMA base and stream number */
|
|
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
|
|
80021ce: 68fb ldr r3, [r7, #12]
|
|
80021d0: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80021d2: 613b str r3, [r7, #16]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma);
|
|
80021d4: 68fb ldr r3, [r7, #12]
|
|
80021d6: f893 3034 ldrb.w r3, [r3, #52] @ 0x34
|
|
80021da: 2b01 cmp r3, #1
|
|
80021dc: d101 bne.n 80021e2 <HAL_DMA_Start_IT+0x26>
|
|
80021de: 2302 movs r3, #2
|
|
80021e0: e040 b.n 8002264 <HAL_DMA_Start_IT+0xa8>
|
|
80021e2: 68fb ldr r3, [r7, #12]
|
|
80021e4: 2201 movs r2, #1
|
|
80021e6: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
if(HAL_DMA_STATE_READY == hdma->State)
|
|
80021ea: 68fb ldr r3, [r7, #12]
|
|
80021ec: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
|
|
80021f0: b2db uxtb r3, r3
|
|
80021f2: 2b01 cmp r3, #1
|
|
80021f4: d12f bne.n 8002256 <HAL_DMA_Start_IT+0x9a>
|
|
{
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
80021f6: 68fb ldr r3, [r7, #12]
|
|
80021f8: 2202 movs r2, #2
|
|
80021fa: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Initialize the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
80021fe: 68fb ldr r3, [r7, #12]
|
|
8002200: 2200 movs r2, #0
|
|
8002202: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Configure the source, destination address and the data length */
|
|
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
|
8002204: 683b ldr r3, [r7, #0]
|
|
8002206: 687a ldr r2, [r7, #4]
|
|
8002208: 68b9 ldr r1, [r7, #8]
|
|
800220a: 68f8 ldr r0, [r7, #12]
|
|
800220c: f000 fa4a bl 80026a4 <DMA_SetConfig>
|
|
|
|
/* Clear all interrupt flags at correct offset within the register */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
8002210: 68fb ldr r3, [r7, #12]
|
|
8002212: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002214: 223f movs r2, #63 @ 0x3f
|
|
8002216: 409a lsls r2, r3
|
|
8002218: 693b ldr r3, [r7, #16]
|
|
800221a: 609a str r2, [r3, #8]
|
|
|
|
/* Enable Common interrupts*/
|
|
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
|
|
800221c: 68fb ldr r3, [r7, #12]
|
|
800221e: 681b ldr r3, [r3, #0]
|
|
8002220: 681a ldr r2, [r3, #0]
|
|
8002222: 68fb ldr r3, [r7, #12]
|
|
8002224: 681b ldr r3, [r3, #0]
|
|
8002226: f042 0216 orr.w r2, r2, #22
|
|
800222a: 601a str r2, [r3, #0]
|
|
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
800222c: 68fb ldr r3, [r7, #12]
|
|
800222e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002230: 2b00 cmp r3, #0
|
|
8002232: d007 beq.n 8002244 <HAL_DMA_Start_IT+0x88>
|
|
{
|
|
hdma->Instance->CR |= DMA_IT_HT;
|
|
8002234: 68fb ldr r3, [r7, #12]
|
|
8002236: 681b ldr r3, [r3, #0]
|
|
8002238: 681a ldr r2, [r3, #0]
|
|
800223a: 68fb ldr r3, [r7, #12]
|
|
800223c: 681b ldr r3, [r3, #0]
|
|
800223e: f042 0208 orr.w r2, r2, #8
|
|
8002242: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_DMA_ENABLE(hdma);
|
|
8002244: 68fb ldr r3, [r7, #12]
|
|
8002246: 681b ldr r3, [r3, #0]
|
|
8002248: 681a ldr r2, [r3, #0]
|
|
800224a: 68fb ldr r3, [r7, #12]
|
|
800224c: 681b ldr r3, [r3, #0]
|
|
800224e: f042 0201 orr.w r2, r2, #1
|
|
8002252: 601a str r2, [r3, #0]
|
|
8002254: e005 b.n 8002262 <HAL_DMA_Start_IT+0xa6>
|
|
}
|
|
else
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8002256: 68fb ldr r3, [r7, #12]
|
|
8002258: 2200 movs r2, #0
|
|
800225a: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
/* Return error status */
|
|
status = HAL_BUSY;
|
|
800225e: 2302 movs r3, #2
|
|
8002260: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return status;
|
|
8002262: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8002264: 4618 mov r0, r3
|
|
8002266: 3718 adds r7, #24
|
|
8002268: 46bd mov sp, r7
|
|
800226a: bd80 pop {r7, pc}
|
|
|
|
0800226c <HAL_DMA_Abort>:
|
|
* and the Stream will be effectively disabled only after the transfer of
|
|
* this single data is finished.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800226c: b580 push {r7, lr}
|
|
800226e: b084 sub sp, #16
|
|
8002270: af00 add r7, sp, #0
|
|
8002272: 6078 str r0, [r7, #4]
|
|
/* calculate DMA base and stream number */
|
|
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
|
|
8002274: 687b ldr r3, [r7, #4]
|
|
8002276: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002278: 60fb str r3, [r7, #12]
|
|
|
|
uint32_t tickstart = HAL_GetTick();
|
|
800227a: f7ff fdaf bl 8001ddc <HAL_GetTick>
|
|
800227e: 60b8 str r0, [r7, #8]
|
|
|
|
if(hdma->State != HAL_DMA_STATE_BUSY)
|
|
8002280: 687b ldr r3, [r7, #4]
|
|
8002282: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
|
|
8002286: b2db uxtb r3, r3
|
|
8002288: 2b02 cmp r3, #2
|
|
800228a: d008 beq.n 800229e <HAL_DMA_Abort+0x32>
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
800228c: 687b ldr r3, [r7, #4]
|
|
800228e: 2280 movs r2, #128 @ 0x80
|
|
8002290: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8002292: 687b ldr r3, [r7, #4]
|
|
8002294: 2200 movs r2, #0
|
|
8002296: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_ERROR;
|
|
800229a: 2301 movs r3, #1
|
|
800229c: e052 b.n 8002344 <HAL_DMA_Abort+0xd8>
|
|
}
|
|
else
|
|
{
|
|
/* Disable all the transfer interrupts */
|
|
hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
|
|
800229e: 687b ldr r3, [r7, #4]
|
|
80022a0: 681b ldr r3, [r3, #0]
|
|
80022a2: 681a ldr r2, [r3, #0]
|
|
80022a4: 687b ldr r3, [r7, #4]
|
|
80022a6: 681b ldr r3, [r3, #0]
|
|
80022a8: f022 0216 bic.w r2, r2, #22
|
|
80022ac: 601a str r2, [r3, #0]
|
|
hdma->Instance->FCR &= ~(DMA_IT_FE);
|
|
80022ae: 687b ldr r3, [r7, #4]
|
|
80022b0: 681b ldr r3, [r3, #0]
|
|
80022b2: 695a ldr r2, [r3, #20]
|
|
80022b4: 687b ldr r3, [r7, #4]
|
|
80022b6: 681b ldr r3, [r3, #0]
|
|
80022b8: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
80022bc: 615a str r2, [r3, #20]
|
|
|
|
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
|
|
80022be: 687b ldr r3, [r7, #4]
|
|
80022c0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80022c2: 2b00 cmp r3, #0
|
|
80022c4: d103 bne.n 80022ce <HAL_DMA_Abort+0x62>
|
|
80022c6: 687b ldr r3, [r7, #4]
|
|
80022c8: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
80022ca: 2b00 cmp r3, #0
|
|
80022cc: d007 beq.n 80022de <HAL_DMA_Abort+0x72>
|
|
{
|
|
hdma->Instance->CR &= ~(DMA_IT_HT);
|
|
80022ce: 687b ldr r3, [r7, #4]
|
|
80022d0: 681b ldr r3, [r3, #0]
|
|
80022d2: 681a ldr r2, [r3, #0]
|
|
80022d4: 687b ldr r3, [r7, #4]
|
|
80022d6: 681b ldr r3, [r3, #0]
|
|
80022d8: f022 0208 bic.w r2, r2, #8
|
|
80022dc: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Disable the stream */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
80022de: 687b ldr r3, [r7, #4]
|
|
80022e0: 681b ldr r3, [r3, #0]
|
|
80022e2: 681a ldr r2, [r3, #0]
|
|
80022e4: 687b ldr r3, [r7, #4]
|
|
80022e6: 681b ldr r3, [r3, #0]
|
|
80022e8: f022 0201 bic.w r2, r2, #1
|
|
80022ec: 601a str r2, [r3, #0]
|
|
|
|
/* Check if the DMA Stream is effectively disabled */
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
|
|
80022ee: e013 b.n 8002318 <HAL_DMA_Abort+0xac>
|
|
{
|
|
/* Check for the Timeout */
|
|
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
|
|
80022f0: f7ff fd74 bl 8001ddc <HAL_GetTick>
|
|
80022f4: 4602 mov r2, r0
|
|
80022f6: 68bb ldr r3, [r7, #8]
|
|
80022f8: 1ad3 subs r3, r2, r3
|
|
80022fa: 2b05 cmp r3, #5
|
|
80022fc: d90c bls.n 8002318 <HAL_DMA_Abort+0xac>
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
|
80022fe: 687b ldr r3, [r7, #4]
|
|
8002300: 2220 movs r2, #32
|
|
8002302: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_TIMEOUT;
|
|
8002304: 687b ldr r3, [r7, #4]
|
|
8002306: 2203 movs r2, #3
|
|
8002308: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
800230c: 687b ldr r3, [r7, #4]
|
|
800230e: 2200 movs r2, #0
|
|
8002310: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_TIMEOUT;
|
|
8002314: 2303 movs r3, #3
|
|
8002316: e015 b.n 8002344 <HAL_DMA_Abort+0xd8>
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
|
|
8002318: 687b ldr r3, [r7, #4]
|
|
800231a: 681b ldr r3, [r3, #0]
|
|
800231c: 681b ldr r3, [r3, #0]
|
|
800231e: f003 0301 and.w r3, r3, #1
|
|
8002322: 2b00 cmp r3, #0
|
|
8002324: d1e4 bne.n 80022f0 <HAL_DMA_Abort+0x84>
|
|
}
|
|
}
|
|
|
|
/* Clear all interrupt flags at correct offset within the register */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
8002326: 687b ldr r3, [r7, #4]
|
|
8002328: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800232a: 223f movs r2, #63 @ 0x3f
|
|
800232c: 409a lsls r2, r3
|
|
800232e: 68fb ldr r3, [r7, #12]
|
|
8002330: 609a str r2, [r3, #8]
|
|
|
|
/* Change the DMA state*/
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8002332: 687b ldr r3, [r7, #4]
|
|
8002334: 2201 movs r2, #1
|
|
8002336: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
800233a: 687b ldr r3, [r7, #4]
|
|
800233c: 2200 movs r2, #0
|
|
800233e: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
}
|
|
return HAL_OK;
|
|
8002342: 2300 movs r3, #0
|
|
}
|
|
8002344: 4618 mov r0, r3
|
|
8002346: 3710 adds r7, #16
|
|
8002348: 46bd mov sp, r7
|
|
800234a: bd80 pop {r7, pc}
|
|
|
|
0800234c <HAL_DMA_Abort_IT>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800234c: b480 push {r7}
|
|
800234e: b083 sub sp, #12
|
|
8002350: af00 add r7, sp, #0
|
|
8002352: 6078 str r0, [r7, #4]
|
|
if(hdma->State != HAL_DMA_STATE_BUSY)
|
|
8002354: 687b ldr r3, [r7, #4]
|
|
8002356: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
|
|
800235a: b2db uxtb r3, r3
|
|
800235c: 2b02 cmp r3, #2
|
|
800235e: d004 beq.n 800236a <HAL_DMA_Abort_IT+0x1e>
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8002360: 687b ldr r3, [r7, #4]
|
|
8002362: 2280 movs r2, #128 @ 0x80
|
|
8002364: 655a str r2, [r3, #84] @ 0x54
|
|
return HAL_ERROR;
|
|
8002366: 2301 movs r3, #1
|
|
8002368: e00c b.n 8002384 <HAL_DMA_Abort_IT+0x38>
|
|
}
|
|
else
|
|
{
|
|
/* Set Abort State */
|
|
hdma->State = HAL_DMA_STATE_ABORT;
|
|
800236a: 687b ldr r3, [r7, #4]
|
|
800236c: 2205 movs r2, #5
|
|
800236e: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Disable the stream */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8002372: 687b ldr r3, [r7, #4]
|
|
8002374: 681b ldr r3, [r3, #0]
|
|
8002376: 681a ldr r2, [r3, #0]
|
|
8002378: 687b ldr r3, [r7, #4]
|
|
800237a: 681b ldr r3, [r3, #0]
|
|
800237c: f022 0201 bic.w r2, r2, #1
|
|
8002380: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8002382: 2300 movs r3, #0
|
|
}
|
|
8002384: 4618 mov r0, r3
|
|
8002386: 370c adds r7, #12
|
|
8002388: 46bd mov sp, r7
|
|
800238a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800238e: 4770 bx lr
|
|
|
|
08002390 <HAL_DMA_IRQHandler>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval None
|
|
*/
|
|
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8002390: b580 push {r7, lr}
|
|
8002392: b086 sub sp, #24
|
|
8002394: af00 add r7, sp, #0
|
|
8002396: 6078 str r0, [r7, #4]
|
|
uint32_t tmpisr;
|
|
__IO uint32_t count = 0U;
|
|
8002398: 2300 movs r3, #0
|
|
800239a: 60bb str r3, [r7, #8]
|
|
uint32_t timeout = SystemCoreClock / 9600U;
|
|
800239c: 4b8e ldr r3, [pc, #568] @ (80025d8 <HAL_DMA_IRQHandler+0x248>)
|
|
800239e: 681b ldr r3, [r3, #0]
|
|
80023a0: 4a8e ldr r2, [pc, #568] @ (80025dc <HAL_DMA_IRQHandler+0x24c>)
|
|
80023a2: fba2 2303 umull r2, r3, r2, r3
|
|
80023a6: 0a9b lsrs r3, r3, #10
|
|
80023a8: 617b str r3, [r7, #20]
|
|
|
|
/* calculate DMA base and stream number */
|
|
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
|
|
80023aa: 687b ldr r3, [r7, #4]
|
|
80023ac: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80023ae: 613b str r3, [r7, #16]
|
|
|
|
tmpisr = regs->ISR;
|
|
80023b0: 693b ldr r3, [r7, #16]
|
|
80023b2: 681b ldr r3, [r3, #0]
|
|
80023b4: 60fb str r3, [r7, #12]
|
|
|
|
/* Transfer Error Interrupt management ***************************************/
|
|
if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
|
|
80023b6: 687b ldr r3, [r7, #4]
|
|
80023b8: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80023ba: 2208 movs r2, #8
|
|
80023bc: 409a lsls r2, r3
|
|
80023be: 68fb ldr r3, [r7, #12]
|
|
80023c0: 4013 ands r3, r2
|
|
80023c2: 2b00 cmp r3, #0
|
|
80023c4: d01a beq.n 80023fc <HAL_DMA_IRQHandler+0x6c>
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
|
|
80023c6: 687b ldr r3, [r7, #4]
|
|
80023c8: 681b ldr r3, [r3, #0]
|
|
80023ca: 681b ldr r3, [r3, #0]
|
|
80023cc: f003 0304 and.w r3, r3, #4
|
|
80023d0: 2b00 cmp r3, #0
|
|
80023d2: d013 beq.n 80023fc <HAL_DMA_IRQHandler+0x6c>
|
|
{
|
|
/* Disable the transfer error interrupt */
|
|
hdma->Instance->CR &= ~(DMA_IT_TE);
|
|
80023d4: 687b ldr r3, [r7, #4]
|
|
80023d6: 681b ldr r3, [r3, #0]
|
|
80023d8: 681a ldr r2, [r3, #0]
|
|
80023da: 687b ldr r3, [r7, #4]
|
|
80023dc: 681b ldr r3, [r3, #0]
|
|
80023de: f022 0204 bic.w r2, r2, #4
|
|
80023e2: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the transfer error flag */
|
|
regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
|
|
80023e4: 687b ldr r3, [r7, #4]
|
|
80023e6: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80023e8: 2208 movs r2, #8
|
|
80023ea: 409a lsls r2, r3
|
|
80023ec: 693b ldr r3, [r7, #16]
|
|
80023ee: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
|
|
80023f0: 687b ldr r3, [r7, #4]
|
|
80023f2: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80023f4: f043 0201 orr.w r2, r3, #1
|
|
80023f8: 687b ldr r3, [r7, #4]
|
|
80023fa: 655a str r2, [r3, #84] @ 0x54
|
|
}
|
|
}
|
|
/* FIFO Error Interrupt management ******************************************/
|
|
if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
|
|
80023fc: 687b ldr r3, [r7, #4]
|
|
80023fe: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002400: 2201 movs r2, #1
|
|
8002402: 409a lsls r2, r3
|
|
8002404: 68fb ldr r3, [r7, #12]
|
|
8002406: 4013 ands r3, r2
|
|
8002408: 2b00 cmp r3, #0
|
|
800240a: d012 beq.n 8002432 <HAL_DMA_IRQHandler+0xa2>
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
|
|
800240c: 687b ldr r3, [r7, #4]
|
|
800240e: 681b ldr r3, [r3, #0]
|
|
8002410: 695b ldr r3, [r3, #20]
|
|
8002412: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002416: 2b00 cmp r3, #0
|
|
8002418: d00b beq.n 8002432 <HAL_DMA_IRQHandler+0xa2>
|
|
{
|
|
/* Clear the FIFO error flag */
|
|
regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
|
|
800241a: 687b ldr r3, [r7, #4]
|
|
800241c: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800241e: 2201 movs r2, #1
|
|
8002420: 409a lsls r2, r3
|
|
8002422: 693b ldr r3, [r7, #16]
|
|
8002424: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
|
|
8002426: 687b ldr r3, [r7, #4]
|
|
8002428: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800242a: f043 0202 orr.w r2, r3, #2
|
|
800242e: 687b ldr r3, [r7, #4]
|
|
8002430: 655a str r2, [r3, #84] @ 0x54
|
|
}
|
|
}
|
|
/* Direct Mode Error Interrupt management ***********************************/
|
|
if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
|
|
8002432: 687b ldr r3, [r7, #4]
|
|
8002434: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002436: 2204 movs r2, #4
|
|
8002438: 409a lsls r2, r3
|
|
800243a: 68fb ldr r3, [r7, #12]
|
|
800243c: 4013 ands r3, r2
|
|
800243e: 2b00 cmp r3, #0
|
|
8002440: d012 beq.n 8002468 <HAL_DMA_IRQHandler+0xd8>
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
|
|
8002442: 687b ldr r3, [r7, #4]
|
|
8002444: 681b ldr r3, [r3, #0]
|
|
8002446: 681b ldr r3, [r3, #0]
|
|
8002448: f003 0302 and.w r3, r3, #2
|
|
800244c: 2b00 cmp r3, #0
|
|
800244e: d00b beq.n 8002468 <HAL_DMA_IRQHandler+0xd8>
|
|
{
|
|
/* Clear the direct mode error flag */
|
|
regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
|
|
8002450: 687b ldr r3, [r7, #4]
|
|
8002452: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002454: 2204 movs r2, #4
|
|
8002456: 409a lsls r2, r3
|
|
8002458: 693b ldr r3, [r7, #16]
|
|
800245a: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
|
|
800245c: 687b ldr r3, [r7, #4]
|
|
800245e: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8002460: f043 0204 orr.w r2, r3, #4
|
|
8002464: 687b ldr r3, [r7, #4]
|
|
8002466: 655a str r2, [r3, #84] @ 0x54
|
|
}
|
|
}
|
|
/* Half Transfer Complete Interrupt management ******************************/
|
|
if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
|
|
8002468: 687b ldr r3, [r7, #4]
|
|
800246a: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800246c: 2210 movs r2, #16
|
|
800246e: 409a lsls r2, r3
|
|
8002470: 68fb ldr r3, [r7, #12]
|
|
8002472: 4013 ands r3, r2
|
|
8002474: 2b00 cmp r3, #0
|
|
8002476: d043 beq.n 8002500 <HAL_DMA_IRQHandler+0x170>
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
|
|
8002478: 687b ldr r3, [r7, #4]
|
|
800247a: 681b ldr r3, [r3, #0]
|
|
800247c: 681b ldr r3, [r3, #0]
|
|
800247e: f003 0308 and.w r3, r3, #8
|
|
8002482: 2b00 cmp r3, #0
|
|
8002484: d03c beq.n 8002500 <HAL_DMA_IRQHandler+0x170>
|
|
{
|
|
/* Clear the half transfer complete flag */
|
|
regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
|
|
8002486: 687b ldr r3, [r7, #4]
|
|
8002488: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800248a: 2210 movs r2, #16
|
|
800248c: 409a lsls r2, r3
|
|
800248e: 693b ldr r3, [r7, #16]
|
|
8002490: 609a str r2, [r3, #8]
|
|
|
|
/* Multi_Buffering mode enabled */
|
|
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
|
|
8002492: 687b ldr r3, [r7, #4]
|
|
8002494: 681b ldr r3, [r3, #0]
|
|
8002496: 681b ldr r3, [r3, #0]
|
|
8002498: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
800249c: 2b00 cmp r3, #0
|
|
800249e: d018 beq.n 80024d2 <HAL_DMA_IRQHandler+0x142>
|
|
{
|
|
/* Current memory buffer used is Memory 0 */
|
|
if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
|
|
80024a0: 687b ldr r3, [r7, #4]
|
|
80024a2: 681b ldr r3, [r3, #0]
|
|
80024a4: 681b ldr r3, [r3, #0]
|
|
80024a6: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
80024aa: 2b00 cmp r3, #0
|
|
80024ac: d108 bne.n 80024c0 <HAL_DMA_IRQHandler+0x130>
|
|
{
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
80024ae: 687b ldr r3, [r7, #4]
|
|
80024b0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80024b2: 2b00 cmp r3, #0
|
|
80024b4: d024 beq.n 8002500 <HAL_DMA_IRQHandler+0x170>
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferHalfCpltCallback(hdma);
|
|
80024b6: 687b ldr r3, [r7, #4]
|
|
80024b8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80024ba: 6878 ldr r0, [r7, #4]
|
|
80024bc: 4798 blx r3
|
|
80024be: e01f b.n 8002500 <HAL_DMA_IRQHandler+0x170>
|
|
}
|
|
}
|
|
/* Current memory buffer used is Memory 1 */
|
|
else
|
|
{
|
|
if(hdma->XferM1HalfCpltCallback != NULL)
|
|
80024c0: 687b ldr r3, [r7, #4]
|
|
80024c2: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
80024c4: 2b00 cmp r3, #0
|
|
80024c6: d01b beq.n 8002500 <HAL_DMA_IRQHandler+0x170>
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferM1HalfCpltCallback(hdma);
|
|
80024c8: 687b ldr r3, [r7, #4]
|
|
80024ca: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
80024cc: 6878 ldr r0, [r7, #4]
|
|
80024ce: 4798 blx r3
|
|
80024d0: e016 b.n 8002500 <HAL_DMA_IRQHandler+0x170>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
|
if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
|
|
80024d2: 687b ldr r3, [r7, #4]
|
|
80024d4: 681b ldr r3, [r3, #0]
|
|
80024d6: 681b ldr r3, [r3, #0]
|
|
80024d8: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80024dc: 2b00 cmp r3, #0
|
|
80024de: d107 bne.n 80024f0 <HAL_DMA_IRQHandler+0x160>
|
|
{
|
|
/* Disable the half transfer interrupt */
|
|
hdma->Instance->CR &= ~(DMA_IT_HT);
|
|
80024e0: 687b ldr r3, [r7, #4]
|
|
80024e2: 681b ldr r3, [r3, #0]
|
|
80024e4: 681a ldr r2, [r3, #0]
|
|
80024e6: 687b ldr r3, [r7, #4]
|
|
80024e8: 681b ldr r3, [r3, #0]
|
|
80024ea: f022 0208 bic.w r2, r2, #8
|
|
80024ee: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
80024f0: 687b ldr r3, [r7, #4]
|
|
80024f2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80024f4: 2b00 cmp r3, #0
|
|
80024f6: d003 beq.n 8002500 <HAL_DMA_IRQHandler+0x170>
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferHalfCpltCallback(hdma);
|
|
80024f8: 687b ldr r3, [r7, #4]
|
|
80024fa: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80024fc: 6878 ldr r0, [r7, #4]
|
|
80024fe: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/* Transfer Complete Interrupt management ***********************************/
|
|
if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
|
|
8002500: 687b ldr r3, [r7, #4]
|
|
8002502: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002504: 2220 movs r2, #32
|
|
8002506: 409a lsls r2, r3
|
|
8002508: 68fb ldr r3, [r7, #12]
|
|
800250a: 4013 ands r3, r2
|
|
800250c: 2b00 cmp r3, #0
|
|
800250e: f000 808f beq.w 8002630 <HAL_DMA_IRQHandler+0x2a0>
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
|
|
8002512: 687b ldr r3, [r7, #4]
|
|
8002514: 681b ldr r3, [r3, #0]
|
|
8002516: 681b ldr r3, [r3, #0]
|
|
8002518: f003 0310 and.w r3, r3, #16
|
|
800251c: 2b00 cmp r3, #0
|
|
800251e: f000 8087 beq.w 8002630 <HAL_DMA_IRQHandler+0x2a0>
|
|
{
|
|
/* Clear the transfer complete flag */
|
|
regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
|
|
8002522: 687b ldr r3, [r7, #4]
|
|
8002524: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002526: 2220 movs r2, #32
|
|
8002528: 409a lsls r2, r3
|
|
800252a: 693b ldr r3, [r7, #16]
|
|
800252c: 609a str r2, [r3, #8]
|
|
|
|
if(HAL_DMA_STATE_ABORT == hdma->State)
|
|
800252e: 687b ldr r3, [r7, #4]
|
|
8002530: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
|
|
8002534: b2db uxtb r3, r3
|
|
8002536: 2b05 cmp r3, #5
|
|
8002538: d136 bne.n 80025a8 <HAL_DMA_IRQHandler+0x218>
|
|
{
|
|
/* Disable all the transfer interrupts */
|
|
hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
|
|
800253a: 687b ldr r3, [r7, #4]
|
|
800253c: 681b ldr r3, [r3, #0]
|
|
800253e: 681a ldr r2, [r3, #0]
|
|
8002540: 687b ldr r3, [r7, #4]
|
|
8002542: 681b ldr r3, [r3, #0]
|
|
8002544: f022 0216 bic.w r2, r2, #22
|
|
8002548: 601a str r2, [r3, #0]
|
|
hdma->Instance->FCR &= ~(DMA_IT_FE);
|
|
800254a: 687b ldr r3, [r7, #4]
|
|
800254c: 681b ldr r3, [r3, #0]
|
|
800254e: 695a ldr r2, [r3, #20]
|
|
8002550: 687b ldr r3, [r7, #4]
|
|
8002552: 681b ldr r3, [r3, #0]
|
|
8002554: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
8002558: 615a str r2, [r3, #20]
|
|
|
|
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
|
|
800255a: 687b ldr r3, [r7, #4]
|
|
800255c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800255e: 2b00 cmp r3, #0
|
|
8002560: d103 bne.n 800256a <HAL_DMA_IRQHandler+0x1da>
|
|
8002562: 687b ldr r3, [r7, #4]
|
|
8002564: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8002566: 2b00 cmp r3, #0
|
|
8002568: d007 beq.n 800257a <HAL_DMA_IRQHandler+0x1ea>
|
|
{
|
|
hdma->Instance->CR &= ~(DMA_IT_HT);
|
|
800256a: 687b ldr r3, [r7, #4]
|
|
800256c: 681b ldr r3, [r3, #0]
|
|
800256e: 681a ldr r2, [r3, #0]
|
|
8002570: 687b ldr r3, [r7, #4]
|
|
8002572: 681b ldr r3, [r3, #0]
|
|
8002574: f022 0208 bic.w r2, r2, #8
|
|
8002578: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Clear all interrupt flags at correct offset within the register */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
800257a: 687b ldr r3, [r7, #4]
|
|
800257c: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800257e: 223f movs r2, #63 @ 0x3f
|
|
8002580: 409a lsls r2, r3
|
|
8002582: 693b ldr r3, [r7, #16]
|
|
8002584: 609a str r2, [r3, #8]
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8002586: 687b ldr r3, [r7, #4]
|
|
8002588: 2201 movs r2, #1
|
|
800258a: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
800258e: 687b ldr r3, [r7, #4]
|
|
8002590: 2200 movs r2, #0
|
|
8002592: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
if(hdma->XferAbortCallback != NULL)
|
|
8002596: 687b ldr r3, [r7, #4]
|
|
8002598: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
800259a: 2b00 cmp r3, #0
|
|
800259c: d07e beq.n 800269c <HAL_DMA_IRQHandler+0x30c>
|
|
{
|
|
hdma->XferAbortCallback(hdma);
|
|
800259e: 687b ldr r3, [r7, #4]
|
|
80025a0: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80025a2: 6878 ldr r0, [r7, #4]
|
|
80025a4: 4798 blx r3
|
|
}
|
|
return;
|
|
80025a6: e079 b.n 800269c <HAL_DMA_IRQHandler+0x30c>
|
|
}
|
|
|
|
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
|
|
80025a8: 687b ldr r3, [r7, #4]
|
|
80025aa: 681b ldr r3, [r3, #0]
|
|
80025ac: 681b ldr r3, [r3, #0]
|
|
80025ae: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
80025b2: 2b00 cmp r3, #0
|
|
80025b4: d01d beq.n 80025f2 <HAL_DMA_IRQHandler+0x262>
|
|
{
|
|
/* Current memory buffer used is Memory 0 */
|
|
if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
|
|
80025b6: 687b ldr r3, [r7, #4]
|
|
80025b8: 681b ldr r3, [r3, #0]
|
|
80025ba: 681b ldr r3, [r3, #0]
|
|
80025bc: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
80025c0: 2b00 cmp r3, #0
|
|
80025c2: d10d bne.n 80025e0 <HAL_DMA_IRQHandler+0x250>
|
|
{
|
|
if(hdma->XferM1CpltCallback != NULL)
|
|
80025c4: 687b ldr r3, [r7, #4]
|
|
80025c6: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80025c8: 2b00 cmp r3, #0
|
|
80025ca: d031 beq.n 8002630 <HAL_DMA_IRQHandler+0x2a0>
|
|
{
|
|
/* Transfer complete Callback for memory1 */
|
|
hdma->XferM1CpltCallback(hdma);
|
|
80025cc: 687b ldr r3, [r7, #4]
|
|
80025ce: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80025d0: 6878 ldr r0, [r7, #4]
|
|
80025d2: 4798 blx r3
|
|
80025d4: e02c b.n 8002630 <HAL_DMA_IRQHandler+0x2a0>
|
|
80025d6: bf00 nop
|
|
80025d8: 20000090 .word 0x20000090
|
|
80025dc: 1b4e81b5 .word 0x1b4e81b5
|
|
}
|
|
}
|
|
/* Current memory buffer used is Memory 1 */
|
|
else
|
|
{
|
|
if(hdma->XferCpltCallback != NULL)
|
|
80025e0: 687b ldr r3, [r7, #4]
|
|
80025e2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80025e4: 2b00 cmp r3, #0
|
|
80025e6: d023 beq.n 8002630 <HAL_DMA_IRQHandler+0x2a0>
|
|
{
|
|
/* Transfer complete Callback for memory0 */
|
|
hdma->XferCpltCallback(hdma);
|
|
80025e8: 687b ldr r3, [r7, #4]
|
|
80025ea: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80025ec: 6878 ldr r0, [r7, #4]
|
|
80025ee: 4798 blx r3
|
|
80025f0: e01e b.n 8002630 <HAL_DMA_IRQHandler+0x2a0>
|
|
}
|
|
}
|
|
/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
|
|
else
|
|
{
|
|
if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
|
|
80025f2: 687b ldr r3, [r7, #4]
|
|
80025f4: 681b ldr r3, [r3, #0]
|
|
80025f6: 681b ldr r3, [r3, #0]
|
|
80025f8: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80025fc: 2b00 cmp r3, #0
|
|
80025fe: d10f bne.n 8002620 <HAL_DMA_IRQHandler+0x290>
|
|
{
|
|
/* Disable the transfer complete interrupt */
|
|
hdma->Instance->CR &= ~(DMA_IT_TC);
|
|
8002600: 687b ldr r3, [r7, #4]
|
|
8002602: 681b ldr r3, [r3, #0]
|
|
8002604: 681a ldr r2, [r3, #0]
|
|
8002606: 687b ldr r3, [r7, #4]
|
|
8002608: 681b ldr r3, [r3, #0]
|
|
800260a: f022 0210 bic.w r2, r2, #16
|
|
800260e: 601a str r2, [r3, #0]
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8002610: 687b ldr r3, [r7, #4]
|
|
8002612: 2201 movs r2, #1
|
|
8002614: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8002618: 687b ldr r3, [r7, #4]
|
|
800261a: 2200 movs r2, #0
|
|
800261c: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
}
|
|
|
|
if(hdma->XferCpltCallback != NULL)
|
|
8002620: 687b ldr r3, [r7, #4]
|
|
8002622: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8002624: 2b00 cmp r3, #0
|
|
8002626: d003 beq.n 8002630 <HAL_DMA_IRQHandler+0x2a0>
|
|
{
|
|
/* Transfer complete callback */
|
|
hdma->XferCpltCallback(hdma);
|
|
8002628: 687b ldr r3, [r7, #4]
|
|
800262a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800262c: 6878 ldr r0, [r7, #4]
|
|
800262e: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
|
|
/* manage error case */
|
|
if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
|
|
8002630: 687b ldr r3, [r7, #4]
|
|
8002632: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8002634: 2b00 cmp r3, #0
|
|
8002636: d032 beq.n 800269e <HAL_DMA_IRQHandler+0x30e>
|
|
{
|
|
if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
|
|
8002638: 687b ldr r3, [r7, #4]
|
|
800263a: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800263c: f003 0301 and.w r3, r3, #1
|
|
8002640: 2b00 cmp r3, #0
|
|
8002642: d022 beq.n 800268a <HAL_DMA_IRQHandler+0x2fa>
|
|
{
|
|
hdma->State = HAL_DMA_STATE_ABORT;
|
|
8002644: 687b ldr r3, [r7, #4]
|
|
8002646: 2205 movs r2, #5
|
|
8002648: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Disable the stream */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
800264c: 687b ldr r3, [r7, #4]
|
|
800264e: 681b ldr r3, [r3, #0]
|
|
8002650: 681a ldr r2, [r3, #0]
|
|
8002652: 687b ldr r3, [r7, #4]
|
|
8002654: 681b ldr r3, [r3, #0]
|
|
8002656: f022 0201 bic.w r2, r2, #1
|
|
800265a: 601a str r2, [r3, #0]
|
|
|
|
do
|
|
{
|
|
if (++count > timeout)
|
|
800265c: 68bb ldr r3, [r7, #8]
|
|
800265e: 3301 adds r3, #1
|
|
8002660: 60bb str r3, [r7, #8]
|
|
8002662: 697a ldr r2, [r7, #20]
|
|
8002664: 429a cmp r2, r3
|
|
8002666: d307 bcc.n 8002678 <HAL_DMA_IRQHandler+0x2e8>
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
|
|
8002668: 687b ldr r3, [r7, #4]
|
|
800266a: 681b ldr r3, [r3, #0]
|
|
800266c: 681b ldr r3, [r3, #0]
|
|
800266e: f003 0301 and.w r3, r3, #1
|
|
8002672: 2b00 cmp r3, #0
|
|
8002674: d1f2 bne.n 800265c <HAL_DMA_IRQHandler+0x2cc>
|
|
8002676: e000 b.n 800267a <HAL_DMA_IRQHandler+0x2ea>
|
|
break;
|
|
8002678: bf00 nop
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
800267a: 687b ldr r3, [r7, #4]
|
|
800267c: 2201 movs r2, #1
|
|
800267e: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8002682: 687b ldr r3, [r7, #4]
|
|
8002684: 2200 movs r2, #0
|
|
8002686: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
}
|
|
|
|
if(hdma->XferErrorCallback != NULL)
|
|
800268a: 687b ldr r3, [r7, #4]
|
|
800268c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800268e: 2b00 cmp r3, #0
|
|
8002690: d005 beq.n 800269e <HAL_DMA_IRQHandler+0x30e>
|
|
{
|
|
/* Transfer error callback */
|
|
hdma->XferErrorCallback(hdma);
|
|
8002692: 687b ldr r3, [r7, #4]
|
|
8002694: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002696: 6878 ldr r0, [r7, #4]
|
|
8002698: 4798 blx r3
|
|
800269a: e000 b.n 800269e <HAL_DMA_IRQHandler+0x30e>
|
|
return;
|
|
800269c: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
800269e: 3718 adds r7, #24
|
|
80026a0: 46bd mov sp, r7
|
|
80026a2: bd80 pop {r7, pc}
|
|
|
|
080026a4 <DMA_SetConfig>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
80026a4: b480 push {r7}
|
|
80026a6: b085 sub sp, #20
|
|
80026a8: af00 add r7, sp, #0
|
|
80026aa: 60f8 str r0, [r7, #12]
|
|
80026ac: 60b9 str r1, [r7, #8]
|
|
80026ae: 607a str r2, [r7, #4]
|
|
80026b0: 603b str r3, [r7, #0]
|
|
/* Clear DBM bit */
|
|
hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
|
|
80026b2: 68fb ldr r3, [r7, #12]
|
|
80026b4: 681b ldr r3, [r3, #0]
|
|
80026b6: 681a ldr r2, [r3, #0]
|
|
80026b8: 68fb ldr r3, [r7, #12]
|
|
80026ba: 681b ldr r3, [r3, #0]
|
|
80026bc: f422 2280 bic.w r2, r2, #262144 @ 0x40000
|
|
80026c0: 601a str r2, [r3, #0]
|
|
|
|
/* Configure DMA Stream data length */
|
|
hdma->Instance->NDTR = DataLength;
|
|
80026c2: 68fb ldr r3, [r7, #12]
|
|
80026c4: 681b ldr r3, [r3, #0]
|
|
80026c6: 683a ldr r2, [r7, #0]
|
|
80026c8: 605a str r2, [r3, #4]
|
|
|
|
/* Memory to Peripheral */
|
|
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
|
80026ca: 68fb ldr r3, [r7, #12]
|
|
80026cc: 689b ldr r3, [r3, #8]
|
|
80026ce: 2b40 cmp r3, #64 @ 0x40
|
|
80026d0: d108 bne.n 80026e4 <DMA_SetConfig+0x40>
|
|
{
|
|
/* Configure DMA Stream destination address */
|
|
hdma->Instance->PAR = DstAddress;
|
|
80026d2: 68fb ldr r3, [r7, #12]
|
|
80026d4: 681b ldr r3, [r3, #0]
|
|
80026d6: 687a ldr r2, [r7, #4]
|
|
80026d8: 609a str r2, [r3, #8]
|
|
|
|
/* Configure DMA Stream source address */
|
|
hdma->Instance->M0AR = SrcAddress;
|
|
80026da: 68fb ldr r3, [r7, #12]
|
|
80026dc: 681b ldr r3, [r3, #0]
|
|
80026de: 68ba ldr r2, [r7, #8]
|
|
80026e0: 60da str r2, [r3, #12]
|
|
hdma->Instance->PAR = SrcAddress;
|
|
|
|
/* Configure DMA Stream destination address */
|
|
hdma->Instance->M0AR = DstAddress;
|
|
}
|
|
}
|
|
80026e2: e007 b.n 80026f4 <DMA_SetConfig+0x50>
|
|
hdma->Instance->PAR = SrcAddress;
|
|
80026e4: 68fb ldr r3, [r7, #12]
|
|
80026e6: 681b ldr r3, [r3, #0]
|
|
80026e8: 68ba ldr r2, [r7, #8]
|
|
80026ea: 609a str r2, [r3, #8]
|
|
hdma->Instance->M0AR = DstAddress;
|
|
80026ec: 68fb ldr r3, [r7, #12]
|
|
80026ee: 681b ldr r3, [r3, #0]
|
|
80026f0: 687a ldr r2, [r7, #4]
|
|
80026f2: 60da str r2, [r3, #12]
|
|
}
|
|
80026f4: bf00 nop
|
|
80026f6: 3714 adds r7, #20
|
|
80026f8: 46bd mov sp, r7
|
|
80026fa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80026fe: 4770 bx lr
|
|
|
|
08002700 <DMA_CalcBaseAndBitshift>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval Stream base address
|
|
*/
|
|
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8002700: b480 push {r7}
|
|
8002702: b085 sub sp, #20
|
|
8002704: af00 add r7, sp, #0
|
|
8002706: 6078 str r0, [r7, #4]
|
|
uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
|
|
8002708: 687b ldr r3, [r7, #4]
|
|
800270a: 681b ldr r3, [r3, #0]
|
|
800270c: b2db uxtb r3, r3
|
|
800270e: 3b10 subs r3, #16
|
|
8002710: 4a14 ldr r2, [pc, #80] @ (8002764 <DMA_CalcBaseAndBitshift+0x64>)
|
|
8002712: fba2 2303 umull r2, r3, r2, r3
|
|
8002716: 091b lsrs r3, r3, #4
|
|
8002718: 60fb str r3, [r7, #12]
|
|
|
|
/* lookup table for necessary bitshift of flags within status registers */
|
|
static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
|
|
hdma->StreamIndex = flagBitshiftOffset[stream_number];
|
|
800271a: 4a13 ldr r2, [pc, #76] @ (8002768 <DMA_CalcBaseAndBitshift+0x68>)
|
|
800271c: 68fb ldr r3, [r7, #12]
|
|
800271e: 4413 add r3, r2
|
|
8002720: 781b ldrb r3, [r3, #0]
|
|
8002722: 461a mov r2, r3
|
|
8002724: 687b ldr r3, [r7, #4]
|
|
8002726: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
if (stream_number > 3U)
|
|
8002728: 68fb ldr r3, [r7, #12]
|
|
800272a: 2b03 cmp r3, #3
|
|
800272c: d909 bls.n 8002742 <DMA_CalcBaseAndBitshift+0x42>
|
|
{
|
|
/* return pointer to HISR and HIFCR */
|
|
hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
|
|
800272e: 687b ldr r3, [r7, #4]
|
|
8002730: 681b ldr r3, [r3, #0]
|
|
8002732: f423 737f bic.w r3, r3, #1020 @ 0x3fc
|
|
8002736: f023 0303 bic.w r3, r3, #3
|
|
800273a: 1d1a adds r2, r3, #4
|
|
800273c: 687b ldr r3, [r7, #4]
|
|
800273e: 659a str r2, [r3, #88] @ 0x58
|
|
8002740: e007 b.n 8002752 <DMA_CalcBaseAndBitshift+0x52>
|
|
}
|
|
else
|
|
{
|
|
/* return pointer to LISR and LIFCR */
|
|
hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
|
|
8002742: 687b ldr r3, [r7, #4]
|
|
8002744: 681b ldr r3, [r3, #0]
|
|
8002746: f423 737f bic.w r3, r3, #1020 @ 0x3fc
|
|
800274a: f023 0303 bic.w r3, r3, #3
|
|
800274e: 687a ldr r2, [r7, #4]
|
|
8002750: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
|
|
return hdma->StreamBaseAddress;
|
|
8002752: 687b ldr r3, [r7, #4]
|
|
8002754: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
}
|
|
8002756: 4618 mov r0, r3
|
|
8002758: 3714 adds r7, #20
|
|
800275a: 46bd mov sp, r7
|
|
800275c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002760: 4770 bx lr
|
|
8002762: bf00 nop
|
|
8002764: aaaaaaab .word 0xaaaaaaab
|
|
8002768: 0800af20 .word 0x0800af20
|
|
|
|
0800276c <DMA_CheckFifoParam>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800276c: b480 push {r7}
|
|
800276e: b085 sub sp, #20
|
|
8002770: af00 add r7, sp, #0
|
|
8002772: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8002774: 2300 movs r3, #0
|
|
8002776: 73fb strb r3, [r7, #15]
|
|
uint32_t tmp = hdma->Init.FIFOThreshold;
|
|
8002778: 687b ldr r3, [r7, #4]
|
|
800277a: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800277c: 60bb str r3, [r7, #8]
|
|
|
|
/* Memory Data size equal to Byte */
|
|
if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
|
|
800277e: 687b ldr r3, [r7, #4]
|
|
8002780: 699b ldr r3, [r3, #24]
|
|
8002782: 2b00 cmp r3, #0
|
|
8002784: d11f bne.n 80027c6 <DMA_CheckFifoParam+0x5a>
|
|
{
|
|
switch (tmp)
|
|
8002786: 68bb ldr r3, [r7, #8]
|
|
8002788: 2b03 cmp r3, #3
|
|
800278a: d856 bhi.n 800283a <DMA_CheckFifoParam+0xce>
|
|
800278c: a201 add r2, pc, #4 @ (adr r2, 8002794 <DMA_CheckFifoParam+0x28>)
|
|
800278e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8002792: bf00 nop
|
|
8002794: 080027a5 .word 0x080027a5
|
|
8002798: 080027b7 .word 0x080027b7
|
|
800279c: 080027a5 .word 0x080027a5
|
|
80027a0: 0800283b .word 0x0800283b
|
|
{
|
|
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
|
|
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
|
|
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
|
|
80027a4: 687b ldr r3, [r7, #4]
|
|
80027a6: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80027a8: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
80027ac: 2b00 cmp r3, #0
|
|
80027ae: d046 beq.n 800283e <DMA_CheckFifoParam+0xd2>
|
|
{
|
|
status = HAL_ERROR;
|
|
80027b0: 2301 movs r3, #1
|
|
80027b2: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
80027b4: e043 b.n 800283e <DMA_CheckFifoParam+0xd2>
|
|
case DMA_FIFO_THRESHOLD_HALFFULL:
|
|
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
|
|
80027b6: 687b ldr r3, [r7, #4]
|
|
80027b8: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80027ba: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000
|
|
80027be: d140 bne.n 8002842 <DMA_CheckFifoParam+0xd6>
|
|
{
|
|
status = HAL_ERROR;
|
|
80027c0: 2301 movs r3, #1
|
|
80027c2: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
80027c4: e03d b.n 8002842 <DMA_CheckFifoParam+0xd6>
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Memory Data size equal to Half-Word */
|
|
else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
|
|
80027c6: 687b ldr r3, [r7, #4]
|
|
80027c8: 699b ldr r3, [r3, #24]
|
|
80027ca: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
80027ce: d121 bne.n 8002814 <DMA_CheckFifoParam+0xa8>
|
|
{
|
|
switch (tmp)
|
|
80027d0: 68bb ldr r3, [r7, #8]
|
|
80027d2: 2b03 cmp r3, #3
|
|
80027d4: d837 bhi.n 8002846 <DMA_CheckFifoParam+0xda>
|
|
80027d6: a201 add r2, pc, #4 @ (adr r2, 80027dc <DMA_CheckFifoParam+0x70>)
|
|
80027d8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80027dc: 080027ed .word 0x080027ed
|
|
80027e0: 080027f3 .word 0x080027f3
|
|
80027e4: 080027ed .word 0x080027ed
|
|
80027e8: 08002805 .word 0x08002805
|
|
{
|
|
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
|
|
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
|
|
status = HAL_ERROR;
|
|
80027ec: 2301 movs r3, #1
|
|
80027ee: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80027f0: e030 b.n 8002854 <DMA_CheckFifoParam+0xe8>
|
|
case DMA_FIFO_THRESHOLD_HALFFULL:
|
|
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
|
|
80027f2: 687b ldr r3, [r7, #4]
|
|
80027f4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80027f6: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
80027fa: 2b00 cmp r3, #0
|
|
80027fc: d025 beq.n 800284a <DMA_CheckFifoParam+0xde>
|
|
{
|
|
status = HAL_ERROR;
|
|
80027fe: 2301 movs r3, #1
|
|
8002800: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8002802: e022 b.n 800284a <DMA_CheckFifoParam+0xde>
|
|
case DMA_FIFO_THRESHOLD_FULL:
|
|
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
|
|
8002804: 687b ldr r3, [r7, #4]
|
|
8002806: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8002808: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000
|
|
800280c: d11f bne.n 800284e <DMA_CheckFifoParam+0xe2>
|
|
{
|
|
status = HAL_ERROR;
|
|
800280e: 2301 movs r3, #1
|
|
8002810: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8002812: e01c b.n 800284e <DMA_CheckFifoParam+0xe2>
|
|
}
|
|
|
|
/* Memory Data size equal to Word */
|
|
else
|
|
{
|
|
switch (tmp)
|
|
8002814: 68bb ldr r3, [r7, #8]
|
|
8002816: 2b02 cmp r3, #2
|
|
8002818: d903 bls.n 8002822 <DMA_CheckFifoParam+0xb6>
|
|
800281a: 68bb ldr r3, [r7, #8]
|
|
800281c: 2b03 cmp r3, #3
|
|
800281e: d003 beq.n 8002828 <DMA_CheckFifoParam+0xbc>
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
8002820: e018 b.n 8002854 <DMA_CheckFifoParam+0xe8>
|
|
status = HAL_ERROR;
|
|
8002822: 2301 movs r3, #1
|
|
8002824: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8002826: e015 b.n 8002854 <DMA_CheckFifoParam+0xe8>
|
|
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
|
|
8002828: 687b ldr r3, [r7, #4]
|
|
800282a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800282c: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
8002830: 2b00 cmp r3, #0
|
|
8002832: d00e beq.n 8002852 <DMA_CheckFifoParam+0xe6>
|
|
status = HAL_ERROR;
|
|
8002834: 2301 movs r3, #1
|
|
8002836: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8002838: e00b b.n 8002852 <DMA_CheckFifoParam+0xe6>
|
|
break;
|
|
800283a: bf00 nop
|
|
800283c: e00a b.n 8002854 <DMA_CheckFifoParam+0xe8>
|
|
break;
|
|
800283e: bf00 nop
|
|
8002840: e008 b.n 8002854 <DMA_CheckFifoParam+0xe8>
|
|
break;
|
|
8002842: bf00 nop
|
|
8002844: e006 b.n 8002854 <DMA_CheckFifoParam+0xe8>
|
|
break;
|
|
8002846: bf00 nop
|
|
8002848: e004 b.n 8002854 <DMA_CheckFifoParam+0xe8>
|
|
break;
|
|
800284a: bf00 nop
|
|
800284c: e002 b.n 8002854 <DMA_CheckFifoParam+0xe8>
|
|
break;
|
|
800284e: bf00 nop
|
|
8002850: e000 b.n 8002854 <DMA_CheckFifoParam+0xe8>
|
|
break;
|
|
8002852: bf00 nop
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8002854: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8002856: 4618 mov r0, r3
|
|
8002858: 3714 adds r7, #20
|
|
800285a: 46bd mov sp, r7
|
|
800285c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002860: 4770 bx lr
|
|
8002862: bf00 nop
|
|
|
|
08002864 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8002864: b480 push {r7}
|
|
8002866: b089 sub sp, #36 @ 0x24
|
|
8002868: af00 add r7, sp, #0
|
|
800286a: 6078 str r0, [r7, #4]
|
|
800286c: 6039 str r1, [r7, #0]
|
|
uint32_t position;
|
|
uint32_t ioposition = 0x00U;
|
|
800286e: 2300 movs r3, #0
|
|
8002870: 617b str r3, [r7, #20]
|
|
uint32_t iocurrent = 0x00U;
|
|
8002872: 2300 movs r3, #0
|
|
8002874: 613b str r3, [r7, #16]
|
|
uint32_t temp = 0x00U;
|
|
8002876: 2300 movs r3, #0
|
|
8002878: 61bb str r3, [r7, #24]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
800287a: 2300 movs r3, #0
|
|
800287c: 61fb str r3, [r7, #28]
|
|
800287e: e165 b.n 8002b4c <HAL_GPIO_Init+0x2e8>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = 0x01U << position;
|
|
8002880: 2201 movs r2, #1
|
|
8002882: 69fb ldr r3, [r7, #28]
|
|
8002884: fa02 f303 lsl.w r3, r2, r3
|
|
8002888: 617b str r3, [r7, #20]
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
800288a: 683b ldr r3, [r7, #0]
|
|
800288c: 681b ldr r3, [r3, #0]
|
|
800288e: 697a ldr r2, [r7, #20]
|
|
8002890: 4013 ands r3, r2
|
|
8002892: 613b str r3, [r7, #16]
|
|
|
|
if(iocurrent == ioposition)
|
|
8002894: 693a ldr r2, [r7, #16]
|
|
8002896: 697b ldr r3, [r7, #20]
|
|
8002898: 429a cmp r2, r3
|
|
800289a: f040 8154 bne.w 8002b46 <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
800289e: 683b ldr r3, [r7, #0]
|
|
80028a0: 685b ldr r3, [r3, #4]
|
|
80028a2: f003 0303 and.w r3, r3, #3
|
|
80028a6: 2b01 cmp r3, #1
|
|
80028a8: d005 beq.n 80028b6 <HAL_GPIO_Init+0x52>
|
|
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
80028aa: 683b ldr r3, [r7, #0]
|
|
80028ac: 685b ldr r3, [r3, #4]
|
|
80028ae: f003 0303 and.w r3, r3, #3
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
80028b2: 2b02 cmp r3, #2
|
|
80028b4: d130 bne.n 8002918 <HAL_GPIO_Init+0xb4>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
80028b6: 687b ldr r3, [r7, #4]
|
|
80028b8: 689b ldr r3, [r3, #8]
|
|
80028ba: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
|
80028bc: 69fb ldr r3, [r7, #28]
|
|
80028be: 005b lsls r3, r3, #1
|
|
80028c0: 2203 movs r2, #3
|
|
80028c2: fa02 f303 lsl.w r3, r2, r3
|
|
80028c6: 43db mvns r3, r3
|
|
80028c8: 69ba ldr r2, [r7, #24]
|
|
80028ca: 4013 ands r3, r2
|
|
80028cc: 61bb str r3, [r7, #24]
|
|
temp |= (GPIO_Init->Speed << (position * 2U));
|
|
80028ce: 683b ldr r3, [r7, #0]
|
|
80028d0: 68da ldr r2, [r3, #12]
|
|
80028d2: 69fb ldr r3, [r7, #28]
|
|
80028d4: 005b lsls r3, r3, #1
|
|
80028d6: fa02 f303 lsl.w r3, r2, r3
|
|
80028da: 69ba ldr r2, [r7, #24]
|
|
80028dc: 4313 orrs r3, r2
|
|
80028de: 61bb str r3, [r7, #24]
|
|
GPIOx->OSPEEDR = temp;
|
|
80028e0: 687b ldr r3, [r7, #4]
|
|
80028e2: 69ba ldr r2, [r7, #24]
|
|
80028e4: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
80028e6: 687b ldr r3, [r7, #4]
|
|
80028e8: 685b ldr r3, [r3, #4]
|
|
80028ea: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
80028ec: 2201 movs r2, #1
|
|
80028ee: 69fb ldr r3, [r7, #28]
|
|
80028f0: fa02 f303 lsl.w r3, r2, r3
|
|
80028f4: 43db mvns r3, r3
|
|
80028f6: 69ba ldr r2, [r7, #24]
|
|
80028f8: 4013 ands r3, r2
|
|
80028fa: 61bb str r3, [r7, #24]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
80028fc: 683b ldr r3, [r7, #0]
|
|
80028fe: 685b ldr r3, [r3, #4]
|
|
8002900: 091b lsrs r3, r3, #4
|
|
8002902: f003 0201 and.w r2, r3, #1
|
|
8002906: 69fb ldr r3, [r7, #28]
|
|
8002908: fa02 f303 lsl.w r3, r2, r3
|
|
800290c: 69ba ldr r2, [r7, #24]
|
|
800290e: 4313 orrs r3, r2
|
|
8002910: 61bb str r3, [r7, #24]
|
|
GPIOx->OTYPER = temp;
|
|
8002912: 687b ldr r3, [r7, #4]
|
|
8002914: 69ba ldr r2, [r7, #24]
|
|
8002916: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
8002918: 683b ldr r3, [r7, #0]
|
|
800291a: 685b ldr r3, [r3, #4]
|
|
800291c: f003 0303 and.w r3, r3, #3
|
|
8002920: 2b03 cmp r3, #3
|
|
8002922: d017 beq.n 8002954 <HAL_GPIO_Init+0xf0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
8002924: 687b ldr r3, [r7, #4]
|
|
8002926: 68db ldr r3, [r3, #12]
|
|
8002928: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
|
800292a: 69fb ldr r3, [r7, #28]
|
|
800292c: 005b lsls r3, r3, #1
|
|
800292e: 2203 movs r2, #3
|
|
8002930: fa02 f303 lsl.w r3, r2, r3
|
|
8002934: 43db mvns r3, r3
|
|
8002936: 69ba ldr r2, [r7, #24]
|
|
8002938: 4013 ands r3, r2
|
|
800293a: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
800293c: 683b ldr r3, [r7, #0]
|
|
800293e: 689a ldr r2, [r3, #8]
|
|
8002940: 69fb ldr r3, [r7, #28]
|
|
8002942: 005b lsls r3, r3, #1
|
|
8002944: fa02 f303 lsl.w r3, r2, r3
|
|
8002948: 69ba ldr r2, [r7, #24]
|
|
800294a: 4313 orrs r3, r2
|
|
800294c: 61bb str r3, [r7, #24]
|
|
GPIOx->PUPDR = temp;
|
|
800294e: 687b ldr r3, [r7, #4]
|
|
8002950: 69ba ldr r2, [r7, #24]
|
|
8002952: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8002954: 683b ldr r3, [r7, #0]
|
|
8002956: 685b ldr r3, [r3, #4]
|
|
8002958: f003 0303 and.w r3, r3, #3
|
|
800295c: 2b02 cmp r3, #2
|
|
800295e: d123 bne.n 80029a8 <HAL_GPIO_Init+0x144>
|
|
{
|
|
/* Check the Alternate function parameter */
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3U];
|
|
8002960: 69fb ldr r3, [r7, #28]
|
|
8002962: 08da lsrs r2, r3, #3
|
|
8002964: 687b ldr r3, [r7, #4]
|
|
8002966: 3208 adds r2, #8
|
|
8002968: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800296c: 61bb str r3, [r7, #24]
|
|
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
|
|
800296e: 69fb ldr r3, [r7, #28]
|
|
8002970: f003 0307 and.w r3, r3, #7
|
|
8002974: 009b lsls r3, r3, #2
|
|
8002976: 220f movs r2, #15
|
|
8002978: fa02 f303 lsl.w r3, r2, r3
|
|
800297c: 43db mvns r3, r3
|
|
800297e: 69ba ldr r2, [r7, #24]
|
|
8002980: 4013 ands r3, r2
|
|
8002982: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
|
|
8002984: 683b ldr r3, [r7, #0]
|
|
8002986: 691a ldr r2, [r3, #16]
|
|
8002988: 69fb ldr r3, [r7, #28]
|
|
800298a: f003 0307 and.w r3, r3, #7
|
|
800298e: 009b lsls r3, r3, #2
|
|
8002990: fa02 f303 lsl.w r3, r2, r3
|
|
8002994: 69ba ldr r2, [r7, #24]
|
|
8002996: 4313 orrs r3, r2
|
|
8002998: 61bb str r3, [r7, #24]
|
|
GPIOx->AFR[position >> 3U] = temp;
|
|
800299a: 69fb ldr r3, [r7, #28]
|
|
800299c: 08da lsrs r2, r3, #3
|
|
800299e: 687b ldr r3, [r7, #4]
|
|
80029a0: 3208 adds r2, #8
|
|
80029a2: 69b9 ldr r1, [r7, #24]
|
|
80029a4: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
80029a8: 687b ldr r3, [r7, #4]
|
|
80029aa: 681b ldr r3, [r3, #0]
|
|
80029ac: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
|
80029ae: 69fb ldr r3, [r7, #28]
|
|
80029b0: 005b lsls r3, r3, #1
|
|
80029b2: 2203 movs r2, #3
|
|
80029b4: fa02 f303 lsl.w r3, r2, r3
|
|
80029b8: 43db mvns r3, r3
|
|
80029ba: 69ba ldr r2, [r7, #24]
|
|
80029bc: 4013 ands r3, r2
|
|
80029be: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
|
80029c0: 683b ldr r3, [r7, #0]
|
|
80029c2: 685b ldr r3, [r3, #4]
|
|
80029c4: f003 0203 and.w r2, r3, #3
|
|
80029c8: 69fb ldr r3, [r7, #28]
|
|
80029ca: 005b lsls r3, r3, #1
|
|
80029cc: fa02 f303 lsl.w r3, r2, r3
|
|
80029d0: 69ba ldr r2, [r7, #24]
|
|
80029d2: 4313 orrs r3, r2
|
|
80029d4: 61bb str r3, [r7, #24]
|
|
GPIOx->MODER = temp;
|
|
80029d6: 687b ldr r3, [r7, #4]
|
|
80029d8: 69ba ldr r2, [r7, #24]
|
|
80029da: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
|
|
80029dc: 683b ldr r3, [r7, #0]
|
|
80029de: 685b ldr r3, [r3, #4]
|
|
80029e0: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
80029e4: 2b00 cmp r3, #0
|
|
80029e6: f000 80ae beq.w 8002b46 <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
80029ea: 2300 movs r3, #0
|
|
80029ec: 60fb str r3, [r7, #12]
|
|
80029ee: 4b5d ldr r3, [pc, #372] @ (8002b64 <HAL_GPIO_Init+0x300>)
|
|
80029f0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80029f2: 4a5c ldr r2, [pc, #368] @ (8002b64 <HAL_GPIO_Init+0x300>)
|
|
80029f4: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
80029f8: 6453 str r3, [r2, #68] @ 0x44
|
|
80029fa: 4b5a ldr r3, [pc, #360] @ (8002b64 <HAL_GPIO_Init+0x300>)
|
|
80029fc: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80029fe: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8002a02: 60fb str r3, [r7, #12]
|
|
8002a04: 68fb ldr r3, [r7, #12]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2U];
|
|
8002a06: 4a58 ldr r2, [pc, #352] @ (8002b68 <HAL_GPIO_Init+0x304>)
|
|
8002a08: 69fb ldr r3, [r7, #28]
|
|
8002a0a: 089b lsrs r3, r3, #2
|
|
8002a0c: 3302 adds r3, #2
|
|
8002a0e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8002a12: 61bb str r3, [r7, #24]
|
|
temp &= ~(0x0FU << (4U * (position & 0x03U)));
|
|
8002a14: 69fb ldr r3, [r7, #28]
|
|
8002a16: f003 0303 and.w r3, r3, #3
|
|
8002a1a: 009b lsls r3, r3, #2
|
|
8002a1c: 220f movs r2, #15
|
|
8002a1e: fa02 f303 lsl.w r3, r2, r3
|
|
8002a22: 43db mvns r3, r3
|
|
8002a24: 69ba ldr r2, [r7, #24]
|
|
8002a26: 4013 ands r3, r2
|
|
8002a28: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
|
|
8002a2a: 687b ldr r3, [r7, #4]
|
|
8002a2c: 4a4f ldr r2, [pc, #316] @ (8002b6c <HAL_GPIO_Init+0x308>)
|
|
8002a2e: 4293 cmp r3, r2
|
|
8002a30: d025 beq.n 8002a7e <HAL_GPIO_Init+0x21a>
|
|
8002a32: 687b ldr r3, [r7, #4]
|
|
8002a34: 4a4e ldr r2, [pc, #312] @ (8002b70 <HAL_GPIO_Init+0x30c>)
|
|
8002a36: 4293 cmp r3, r2
|
|
8002a38: d01f beq.n 8002a7a <HAL_GPIO_Init+0x216>
|
|
8002a3a: 687b ldr r3, [r7, #4]
|
|
8002a3c: 4a4d ldr r2, [pc, #308] @ (8002b74 <HAL_GPIO_Init+0x310>)
|
|
8002a3e: 4293 cmp r3, r2
|
|
8002a40: d019 beq.n 8002a76 <HAL_GPIO_Init+0x212>
|
|
8002a42: 687b ldr r3, [r7, #4]
|
|
8002a44: 4a4c ldr r2, [pc, #304] @ (8002b78 <HAL_GPIO_Init+0x314>)
|
|
8002a46: 4293 cmp r3, r2
|
|
8002a48: d013 beq.n 8002a72 <HAL_GPIO_Init+0x20e>
|
|
8002a4a: 687b ldr r3, [r7, #4]
|
|
8002a4c: 4a4b ldr r2, [pc, #300] @ (8002b7c <HAL_GPIO_Init+0x318>)
|
|
8002a4e: 4293 cmp r3, r2
|
|
8002a50: d00d beq.n 8002a6e <HAL_GPIO_Init+0x20a>
|
|
8002a52: 687b ldr r3, [r7, #4]
|
|
8002a54: 4a4a ldr r2, [pc, #296] @ (8002b80 <HAL_GPIO_Init+0x31c>)
|
|
8002a56: 4293 cmp r3, r2
|
|
8002a58: d007 beq.n 8002a6a <HAL_GPIO_Init+0x206>
|
|
8002a5a: 687b ldr r3, [r7, #4]
|
|
8002a5c: 4a49 ldr r2, [pc, #292] @ (8002b84 <HAL_GPIO_Init+0x320>)
|
|
8002a5e: 4293 cmp r3, r2
|
|
8002a60: d101 bne.n 8002a66 <HAL_GPIO_Init+0x202>
|
|
8002a62: 2306 movs r3, #6
|
|
8002a64: e00c b.n 8002a80 <HAL_GPIO_Init+0x21c>
|
|
8002a66: 2307 movs r3, #7
|
|
8002a68: e00a b.n 8002a80 <HAL_GPIO_Init+0x21c>
|
|
8002a6a: 2305 movs r3, #5
|
|
8002a6c: e008 b.n 8002a80 <HAL_GPIO_Init+0x21c>
|
|
8002a6e: 2304 movs r3, #4
|
|
8002a70: e006 b.n 8002a80 <HAL_GPIO_Init+0x21c>
|
|
8002a72: 2303 movs r3, #3
|
|
8002a74: e004 b.n 8002a80 <HAL_GPIO_Init+0x21c>
|
|
8002a76: 2302 movs r3, #2
|
|
8002a78: e002 b.n 8002a80 <HAL_GPIO_Init+0x21c>
|
|
8002a7a: 2301 movs r3, #1
|
|
8002a7c: e000 b.n 8002a80 <HAL_GPIO_Init+0x21c>
|
|
8002a7e: 2300 movs r3, #0
|
|
8002a80: 69fa ldr r2, [r7, #28]
|
|
8002a82: f002 0203 and.w r2, r2, #3
|
|
8002a86: 0092 lsls r2, r2, #2
|
|
8002a88: 4093 lsls r3, r2
|
|
8002a8a: 69ba ldr r2, [r7, #24]
|
|
8002a8c: 4313 orrs r3, r2
|
|
8002a8e: 61bb str r3, [r7, #24]
|
|
SYSCFG->EXTICR[position >> 2U] = temp;
|
|
8002a90: 4935 ldr r1, [pc, #212] @ (8002b68 <HAL_GPIO_Init+0x304>)
|
|
8002a92: 69fb ldr r3, [r7, #28]
|
|
8002a94: 089b lsrs r3, r3, #2
|
|
8002a96: 3302 adds r3, #2
|
|
8002a98: 69ba ldr r2, [r7, #24]
|
|
8002a9a: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR;
|
|
8002a9e: 4b3a ldr r3, [pc, #232] @ (8002b88 <HAL_GPIO_Init+0x324>)
|
|
8002aa0: 689b ldr r3, [r3, #8]
|
|
8002aa2: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8002aa4: 693b ldr r3, [r7, #16]
|
|
8002aa6: 43db mvns r3, r3
|
|
8002aa8: 69ba ldr r2, [r7, #24]
|
|
8002aaa: 4013 ands r3, r2
|
|
8002aac: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
|
|
8002aae: 683b ldr r3, [r7, #0]
|
|
8002ab0: 685b ldr r3, [r3, #4]
|
|
8002ab2: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8002ab6: 2b00 cmp r3, #0
|
|
8002ab8: d003 beq.n 8002ac2 <HAL_GPIO_Init+0x25e>
|
|
{
|
|
temp |= iocurrent;
|
|
8002aba: 69ba ldr r2, [r7, #24]
|
|
8002abc: 693b ldr r3, [r7, #16]
|
|
8002abe: 4313 orrs r3, r2
|
|
8002ac0: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->RTSR = temp;
|
|
8002ac2: 4a31 ldr r2, [pc, #196] @ (8002b88 <HAL_GPIO_Init+0x324>)
|
|
8002ac4: 69bb ldr r3, [r7, #24]
|
|
8002ac6: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR;
|
|
8002ac8: 4b2f ldr r3, [pc, #188] @ (8002b88 <HAL_GPIO_Init+0x324>)
|
|
8002aca: 68db ldr r3, [r3, #12]
|
|
8002acc: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8002ace: 693b ldr r3, [r7, #16]
|
|
8002ad0: 43db mvns r3, r3
|
|
8002ad2: 69ba ldr r2, [r7, #24]
|
|
8002ad4: 4013 ands r3, r2
|
|
8002ad6: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
|
|
8002ad8: 683b ldr r3, [r7, #0]
|
|
8002ada: 685b ldr r3, [r3, #4]
|
|
8002adc: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8002ae0: 2b00 cmp r3, #0
|
|
8002ae2: d003 beq.n 8002aec <HAL_GPIO_Init+0x288>
|
|
{
|
|
temp |= iocurrent;
|
|
8002ae4: 69ba ldr r2, [r7, #24]
|
|
8002ae6: 693b ldr r3, [r7, #16]
|
|
8002ae8: 4313 orrs r3, r2
|
|
8002aea: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->FTSR = temp;
|
|
8002aec: 4a26 ldr r2, [pc, #152] @ (8002b88 <HAL_GPIO_Init+0x324>)
|
|
8002aee: 69bb ldr r3, [r7, #24]
|
|
8002af0: 60d3 str r3, [r2, #12]
|
|
|
|
temp = EXTI->EMR;
|
|
8002af2: 4b25 ldr r3, [pc, #148] @ (8002b88 <HAL_GPIO_Init+0x324>)
|
|
8002af4: 685b ldr r3, [r3, #4]
|
|
8002af6: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8002af8: 693b ldr r3, [r7, #16]
|
|
8002afa: 43db mvns r3, r3
|
|
8002afc: 69ba ldr r2, [r7, #24]
|
|
8002afe: 4013 ands r3, r2
|
|
8002b00: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
|
|
8002b02: 683b ldr r3, [r7, #0]
|
|
8002b04: 685b ldr r3, [r3, #4]
|
|
8002b06: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8002b0a: 2b00 cmp r3, #0
|
|
8002b0c: d003 beq.n 8002b16 <HAL_GPIO_Init+0x2b2>
|
|
{
|
|
temp |= iocurrent;
|
|
8002b0e: 69ba ldr r2, [r7, #24]
|
|
8002b10: 693b ldr r3, [r7, #16]
|
|
8002b12: 4313 orrs r3, r2
|
|
8002b14: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->EMR = temp;
|
|
8002b16: 4a1c ldr r2, [pc, #112] @ (8002b88 <HAL_GPIO_Init+0x324>)
|
|
8002b18: 69bb ldr r3, [r7, #24]
|
|
8002b1a: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR;
|
|
8002b1c: 4b1a ldr r3, [pc, #104] @ (8002b88 <HAL_GPIO_Init+0x324>)
|
|
8002b1e: 681b ldr r3, [r3, #0]
|
|
8002b20: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8002b22: 693b ldr r3, [r7, #16]
|
|
8002b24: 43db mvns r3, r3
|
|
8002b26: 69ba ldr r2, [r7, #24]
|
|
8002b28: 4013 ands r3, r2
|
|
8002b2a: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
|
|
8002b2c: 683b ldr r3, [r7, #0]
|
|
8002b2e: 685b ldr r3, [r3, #4]
|
|
8002b30: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8002b34: 2b00 cmp r3, #0
|
|
8002b36: d003 beq.n 8002b40 <HAL_GPIO_Init+0x2dc>
|
|
{
|
|
temp |= iocurrent;
|
|
8002b38: 69ba ldr r2, [r7, #24]
|
|
8002b3a: 693b ldr r3, [r7, #16]
|
|
8002b3c: 4313 orrs r3, r2
|
|
8002b3e: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->IMR = temp;
|
|
8002b40: 4a11 ldr r2, [pc, #68] @ (8002b88 <HAL_GPIO_Init+0x324>)
|
|
8002b42: 69bb ldr r3, [r7, #24]
|
|
8002b44: 6013 str r3, [r2, #0]
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
8002b46: 69fb ldr r3, [r7, #28]
|
|
8002b48: 3301 adds r3, #1
|
|
8002b4a: 61fb str r3, [r7, #28]
|
|
8002b4c: 69fb ldr r3, [r7, #28]
|
|
8002b4e: 2b0f cmp r3, #15
|
|
8002b50: f67f ae96 bls.w 8002880 <HAL_GPIO_Init+0x1c>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8002b54: bf00 nop
|
|
8002b56: bf00 nop
|
|
8002b58: 3724 adds r7, #36 @ 0x24
|
|
8002b5a: 46bd mov sp, r7
|
|
8002b5c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002b60: 4770 bx lr
|
|
8002b62: bf00 nop
|
|
8002b64: 40023800 .word 0x40023800
|
|
8002b68: 40013800 .word 0x40013800
|
|
8002b6c: 40020000 .word 0x40020000
|
|
8002b70: 40020400 .word 0x40020400
|
|
8002b74: 40020800 .word 0x40020800
|
|
8002b78: 40020c00 .word 0x40020c00
|
|
8002b7c: 40021000 .word 0x40021000
|
|
8002b80: 40021400 .word 0x40021400
|
|
8002b84: 40021800 .word 0x40021800
|
|
8002b88: 40013c00 .word 0x40013c00
|
|
|
|
08002b8c <HAL_GPIO_ReadPin>:
|
|
* @param GPIO_Pin specifies the port bit to read.
|
|
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
|
* @retval The input port pin value.
|
|
*/
|
|
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
8002b8c: b480 push {r7}
|
|
8002b8e: b085 sub sp, #20
|
|
8002b90: af00 add r7, sp, #0
|
|
8002b92: 6078 str r0, [r7, #4]
|
|
8002b94: 460b mov r3, r1
|
|
8002b96: 807b strh r3, [r7, #2]
|
|
GPIO_PinState bitstatus;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
|
8002b98: 687b ldr r3, [r7, #4]
|
|
8002b9a: 691a ldr r2, [r3, #16]
|
|
8002b9c: 887b ldrh r3, [r7, #2]
|
|
8002b9e: 4013 ands r3, r2
|
|
8002ba0: 2b00 cmp r3, #0
|
|
8002ba2: d002 beq.n 8002baa <HAL_GPIO_ReadPin+0x1e>
|
|
{
|
|
bitstatus = GPIO_PIN_SET;
|
|
8002ba4: 2301 movs r3, #1
|
|
8002ba6: 73fb strb r3, [r7, #15]
|
|
8002ba8: e001 b.n 8002bae <HAL_GPIO_ReadPin+0x22>
|
|
}
|
|
else
|
|
{
|
|
bitstatus = GPIO_PIN_RESET;
|
|
8002baa: 2300 movs r3, #0
|
|
8002bac: 73fb strb r3, [r7, #15]
|
|
}
|
|
return bitstatus;
|
|
8002bae: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8002bb0: 4618 mov r0, r3
|
|
8002bb2: 3714 adds r7, #20
|
|
8002bb4: 46bd mov sp, r7
|
|
8002bb6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002bba: 4770 bx lr
|
|
|
|
08002bbc <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8002bbc: b480 push {r7}
|
|
8002bbe: b083 sub sp, #12
|
|
8002bc0: af00 add r7, sp, #0
|
|
8002bc2: 6078 str r0, [r7, #4]
|
|
8002bc4: 460b mov r3, r1
|
|
8002bc6: 807b strh r3, [r7, #2]
|
|
8002bc8: 4613 mov r3, r2
|
|
8002bca: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8002bcc: 787b ldrb r3, [r7, #1]
|
|
8002bce: 2b00 cmp r3, #0
|
|
8002bd0: d003 beq.n 8002bda <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = GPIO_Pin;
|
|
8002bd2: 887a ldrh r2, [r7, #2]
|
|
8002bd4: 687b ldr r3, [r7, #4]
|
|
8002bd6: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
}
|
|
}
|
|
8002bd8: e003 b.n 8002be2 <HAL_GPIO_WritePin+0x26>
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
8002bda: 887b ldrh r3, [r7, #2]
|
|
8002bdc: 041a lsls r2, r3, #16
|
|
8002bde: 687b ldr r3, [r7, #4]
|
|
8002be0: 619a str r2, [r3, #24]
|
|
}
|
|
8002be2: bf00 nop
|
|
8002be4: 370c adds r7, #12
|
|
8002be6: 46bd mov sp, r7
|
|
8002be8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002bec: 4770 bx lr
|
|
...
|
|
|
|
08002bf0 <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8002bf0: b580 push {r7, lr}
|
|
8002bf2: b084 sub sp, #16
|
|
8002bf4: af00 add r7, sp, #0
|
|
8002bf6: 6078 str r0, [r7, #4]
|
|
uint32_t freqrange;
|
|
uint32_t pclk1;
|
|
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8002bf8: 687b ldr r3, [r7, #4]
|
|
8002bfa: 2b00 cmp r3, #0
|
|
8002bfc: d101 bne.n 8002c02 <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8002bfe: 2301 movs r3, #1
|
|
8002c00: e12b b.n 8002e5a <HAL_I2C_Init+0x26a>
|
|
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
8002c02: 687b ldr r3, [r7, #4]
|
|
8002c04: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8002c08: b2db uxtb r3, r3
|
|
8002c0a: 2b00 cmp r3, #0
|
|
8002c0c: d106 bne.n 8002c1c <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
8002c0e: 687b ldr r3, [r7, #4]
|
|
8002c10: 2200 movs r2, #0
|
|
8002c12: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_I2C_MspInit(hi2c);
|
|
8002c16: 6878 ldr r0, [r7, #4]
|
|
8002c18: f7fd fdbe bl 8000798 <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8002c1c: 687b ldr r3, [r7, #4]
|
|
8002c1e: 2224 movs r2, #36 @ 0x24
|
|
8002c20: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8002c24: 687b ldr r3, [r7, #4]
|
|
8002c26: 681b ldr r3, [r3, #0]
|
|
8002c28: 681a ldr r2, [r3, #0]
|
|
8002c2a: 687b ldr r3, [r7, #4]
|
|
8002c2c: 681b ldr r3, [r3, #0]
|
|
8002c2e: f022 0201 bic.w r2, r2, #1
|
|
8002c32: 601a str r2, [r3, #0]
|
|
|
|
/*Reset I2C*/
|
|
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
|
|
8002c34: 687b ldr r3, [r7, #4]
|
|
8002c36: 681b ldr r3, [r3, #0]
|
|
8002c38: 681a ldr r2, [r3, #0]
|
|
8002c3a: 687b ldr r3, [r7, #4]
|
|
8002c3c: 681b ldr r3, [r3, #0]
|
|
8002c3e: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
8002c42: 601a str r2, [r3, #0]
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
|
|
8002c44: 687b ldr r3, [r7, #4]
|
|
8002c46: 681b ldr r3, [r3, #0]
|
|
8002c48: 681a ldr r2, [r3, #0]
|
|
8002c4a: 687b ldr r3, [r7, #4]
|
|
8002c4c: 681b ldr r3, [r3, #0]
|
|
8002c4e: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8002c52: 601a str r2, [r3, #0]
|
|
|
|
/* Get PCLK1 frequency */
|
|
pclk1 = HAL_RCC_GetPCLK1Freq();
|
|
8002c54: f001 fc88 bl 8004568 <HAL_RCC_GetPCLK1Freq>
|
|
8002c58: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check the minimum allowed PCLK1 frequency */
|
|
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
|
|
8002c5a: 687b ldr r3, [r7, #4]
|
|
8002c5c: 685b ldr r3, [r3, #4]
|
|
8002c5e: 4a81 ldr r2, [pc, #516] @ (8002e64 <HAL_I2C_Init+0x274>)
|
|
8002c60: 4293 cmp r3, r2
|
|
8002c62: d807 bhi.n 8002c74 <HAL_I2C_Init+0x84>
|
|
8002c64: 68fb ldr r3, [r7, #12]
|
|
8002c66: 4a80 ldr r2, [pc, #512] @ (8002e68 <HAL_I2C_Init+0x278>)
|
|
8002c68: 4293 cmp r3, r2
|
|
8002c6a: bf94 ite ls
|
|
8002c6c: 2301 movls r3, #1
|
|
8002c6e: 2300 movhi r3, #0
|
|
8002c70: b2db uxtb r3, r3
|
|
8002c72: e006 b.n 8002c82 <HAL_I2C_Init+0x92>
|
|
8002c74: 68fb ldr r3, [r7, #12]
|
|
8002c76: 4a7d ldr r2, [pc, #500] @ (8002e6c <HAL_I2C_Init+0x27c>)
|
|
8002c78: 4293 cmp r3, r2
|
|
8002c7a: bf94 ite ls
|
|
8002c7c: 2301 movls r3, #1
|
|
8002c7e: 2300 movhi r3, #0
|
|
8002c80: b2db uxtb r3, r3
|
|
8002c82: 2b00 cmp r3, #0
|
|
8002c84: d001 beq.n 8002c8a <HAL_I2C_Init+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
8002c86: 2301 movs r3, #1
|
|
8002c88: e0e7 b.n 8002e5a <HAL_I2C_Init+0x26a>
|
|
}
|
|
|
|
/* Calculate frequency range */
|
|
freqrange = I2C_FREQRANGE(pclk1);
|
|
8002c8a: 68fb ldr r3, [r7, #12]
|
|
8002c8c: 4a78 ldr r2, [pc, #480] @ (8002e70 <HAL_I2C_Init+0x280>)
|
|
8002c8e: fba2 2303 umull r2, r3, r2, r3
|
|
8002c92: 0c9b lsrs r3, r3, #18
|
|
8002c94: 60bb str r3, [r7, #8]
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
|
|
8002c96: 687b ldr r3, [r7, #4]
|
|
8002c98: 681b ldr r3, [r3, #0]
|
|
8002c9a: 685b ldr r3, [r3, #4]
|
|
8002c9c: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
8002ca0: 687b ldr r3, [r7, #4]
|
|
8002ca2: 681b ldr r3, [r3, #0]
|
|
8002ca4: 68ba ldr r2, [r7, #8]
|
|
8002ca6: 430a orrs r2, r1
|
|
8002ca8: 605a str r2, [r3, #4]
|
|
|
|
/*---------------------------- I2Cx TRISE Configuration --------------------*/
|
|
/* Configure I2Cx: Rise Time */
|
|
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
|
|
8002caa: 687b ldr r3, [r7, #4]
|
|
8002cac: 681b ldr r3, [r3, #0]
|
|
8002cae: 6a1b ldr r3, [r3, #32]
|
|
8002cb0: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
8002cb4: 687b ldr r3, [r7, #4]
|
|
8002cb6: 685b ldr r3, [r3, #4]
|
|
8002cb8: 4a6a ldr r2, [pc, #424] @ (8002e64 <HAL_I2C_Init+0x274>)
|
|
8002cba: 4293 cmp r3, r2
|
|
8002cbc: d802 bhi.n 8002cc4 <HAL_I2C_Init+0xd4>
|
|
8002cbe: 68bb ldr r3, [r7, #8]
|
|
8002cc0: 3301 adds r3, #1
|
|
8002cc2: e009 b.n 8002cd8 <HAL_I2C_Init+0xe8>
|
|
8002cc4: 68bb ldr r3, [r7, #8]
|
|
8002cc6: f44f 7296 mov.w r2, #300 @ 0x12c
|
|
8002cca: fb02 f303 mul.w r3, r2, r3
|
|
8002cce: 4a69 ldr r2, [pc, #420] @ (8002e74 <HAL_I2C_Init+0x284>)
|
|
8002cd0: fba2 2303 umull r2, r3, r2, r3
|
|
8002cd4: 099b lsrs r3, r3, #6
|
|
8002cd6: 3301 adds r3, #1
|
|
8002cd8: 687a ldr r2, [r7, #4]
|
|
8002cda: 6812 ldr r2, [r2, #0]
|
|
8002cdc: 430b orrs r3, r1
|
|
8002cde: 6213 str r3, [r2, #32]
|
|
|
|
/*---------------------------- I2Cx CCR Configuration ----------------------*/
|
|
/* Configure I2Cx: Speed */
|
|
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
|
|
8002ce0: 687b ldr r3, [r7, #4]
|
|
8002ce2: 681b ldr r3, [r3, #0]
|
|
8002ce4: 69db ldr r3, [r3, #28]
|
|
8002ce6: f423 424f bic.w r2, r3, #52992 @ 0xcf00
|
|
8002cea: f022 02ff bic.w r2, r2, #255 @ 0xff
|
|
8002cee: 687b ldr r3, [r7, #4]
|
|
8002cf0: 685b ldr r3, [r3, #4]
|
|
8002cf2: 495c ldr r1, [pc, #368] @ (8002e64 <HAL_I2C_Init+0x274>)
|
|
8002cf4: 428b cmp r3, r1
|
|
8002cf6: d819 bhi.n 8002d2c <HAL_I2C_Init+0x13c>
|
|
8002cf8: 68fb ldr r3, [r7, #12]
|
|
8002cfa: 1e59 subs r1, r3, #1
|
|
8002cfc: 687b ldr r3, [r7, #4]
|
|
8002cfe: 685b ldr r3, [r3, #4]
|
|
8002d00: 005b lsls r3, r3, #1
|
|
8002d02: fbb1 f3f3 udiv r3, r1, r3
|
|
8002d06: 1c59 adds r1, r3, #1
|
|
8002d08: f640 73fc movw r3, #4092 @ 0xffc
|
|
8002d0c: 400b ands r3, r1
|
|
8002d0e: 2b00 cmp r3, #0
|
|
8002d10: d00a beq.n 8002d28 <HAL_I2C_Init+0x138>
|
|
8002d12: 68fb ldr r3, [r7, #12]
|
|
8002d14: 1e59 subs r1, r3, #1
|
|
8002d16: 687b ldr r3, [r7, #4]
|
|
8002d18: 685b ldr r3, [r3, #4]
|
|
8002d1a: 005b lsls r3, r3, #1
|
|
8002d1c: fbb1 f3f3 udiv r3, r1, r3
|
|
8002d20: 3301 adds r3, #1
|
|
8002d22: f3c3 030b ubfx r3, r3, #0, #12
|
|
8002d26: e051 b.n 8002dcc <HAL_I2C_Init+0x1dc>
|
|
8002d28: 2304 movs r3, #4
|
|
8002d2a: e04f b.n 8002dcc <HAL_I2C_Init+0x1dc>
|
|
8002d2c: 687b ldr r3, [r7, #4]
|
|
8002d2e: 689b ldr r3, [r3, #8]
|
|
8002d30: 2b00 cmp r3, #0
|
|
8002d32: d111 bne.n 8002d58 <HAL_I2C_Init+0x168>
|
|
8002d34: 68fb ldr r3, [r7, #12]
|
|
8002d36: 1e58 subs r0, r3, #1
|
|
8002d38: 687b ldr r3, [r7, #4]
|
|
8002d3a: 6859 ldr r1, [r3, #4]
|
|
8002d3c: 460b mov r3, r1
|
|
8002d3e: 005b lsls r3, r3, #1
|
|
8002d40: 440b add r3, r1
|
|
8002d42: fbb0 f3f3 udiv r3, r0, r3
|
|
8002d46: 3301 adds r3, #1
|
|
8002d48: f3c3 030b ubfx r3, r3, #0, #12
|
|
8002d4c: 2b00 cmp r3, #0
|
|
8002d4e: bf0c ite eq
|
|
8002d50: 2301 moveq r3, #1
|
|
8002d52: 2300 movne r3, #0
|
|
8002d54: b2db uxtb r3, r3
|
|
8002d56: e012 b.n 8002d7e <HAL_I2C_Init+0x18e>
|
|
8002d58: 68fb ldr r3, [r7, #12]
|
|
8002d5a: 1e58 subs r0, r3, #1
|
|
8002d5c: 687b ldr r3, [r7, #4]
|
|
8002d5e: 6859 ldr r1, [r3, #4]
|
|
8002d60: 460b mov r3, r1
|
|
8002d62: 009b lsls r3, r3, #2
|
|
8002d64: 440b add r3, r1
|
|
8002d66: 0099 lsls r1, r3, #2
|
|
8002d68: 440b add r3, r1
|
|
8002d6a: fbb0 f3f3 udiv r3, r0, r3
|
|
8002d6e: 3301 adds r3, #1
|
|
8002d70: f3c3 030b ubfx r3, r3, #0, #12
|
|
8002d74: 2b00 cmp r3, #0
|
|
8002d76: bf0c ite eq
|
|
8002d78: 2301 moveq r3, #1
|
|
8002d7a: 2300 movne r3, #0
|
|
8002d7c: b2db uxtb r3, r3
|
|
8002d7e: 2b00 cmp r3, #0
|
|
8002d80: d001 beq.n 8002d86 <HAL_I2C_Init+0x196>
|
|
8002d82: 2301 movs r3, #1
|
|
8002d84: e022 b.n 8002dcc <HAL_I2C_Init+0x1dc>
|
|
8002d86: 687b ldr r3, [r7, #4]
|
|
8002d88: 689b ldr r3, [r3, #8]
|
|
8002d8a: 2b00 cmp r3, #0
|
|
8002d8c: d10e bne.n 8002dac <HAL_I2C_Init+0x1bc>
|
|
8002d8e: 68fb ldr r3, [r7, #12]
|
|
8002d90: 1e58 subs r0, r3, #1
|
|
8002d92: 687b ldr r3, [r7, #4]
|
|
8002d94: 6859 ldr r1, [r3, #4]
|
|
8002d96: 460b mov r3, r1
|
|
8002d98: 005b lsls r3, r3, #1
|
|
8002d9a: 440b add r3, r1
|
|
8002d9c: fbb0 f3f3 udiv r3, r0, r3
|
|
8002da0: 3301 adds r3, #1
|
|
8002da2: f3c3 030b ubfx r3, r3, #0, #12
|
|
8002da6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8002daa: e00f b.n 8002dcc <HAL_I2C_Init+0x1dc>
|
|
8002dac: 68fb ldr r3, [r7, #12]
|
|
8002dae: 1e58 subs r0, r3, #1
|
|
8002db0: 687b ldr r3, [r7, #4]
|
|
8002db2: 6859 ldr r1, [r3, #4]
|
|
8002db4: 460b mov r3, r1
|
|
8002db6: 009b lsls r3, r3, #2
|
|
8002db8: 440b add r3, r1
|
|
8002dba: 0099 lsls r1, r3, #2
|
|
8002dbc: 440b add r3, r1
|
|
8002dbe: fbb0 f3f3 udiv r3, r0, r3
|
|
8002dc2: 3301 adds r3, #1
|
|
8002dc4: f3c3 030b ubfx r3, r3, #0, #12
|
|
8002dc8: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8002dcc: 6879 ldr r1, [r7, #4]
|
|
8002dce: 6809 ldr r1, [r1, #0]
|
|
8002dd0: 4313 orrs r3, r2
|
|
8002dd2: 61cb str r3, [r1, #28]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
|
|
8002dd4: 687b ldr r3, [r7, #4]
|
|
8002dd6: 681b ldr r3, [r3, #0]
|
|
8002dd8: 681b ldr r3, [r3, #0]
|
|
8002dda: f023 01c0 bic.w r1, r3, #192 @ 0xc0
|
|
8002dde: 687b ldr r3, [r7, #4]
|
|
8002de0: 69da ldr r2, [r3, #28]
|
|
8002de2: 687b ldr r3, [r7, #4]
|
|
8002de4: 6a1b ldr r3, [r3, #32]
|
|
8002de6: 431a orrs r2, r3
|
|
8002de8: 687b ldr r3, [r7, #4]
|
|
8002dea: 681b ldr r3, [r3, #0]
|
|
8002dec: 430a orrs r2, r1
|
|
8002dee: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Configure I2Cx: Own Address1 and addressing mode */
|
|
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
|
|
8002df0: 687b ldr r3, [r7, #4]
|
|
8002df2: 681b ldr r3, [r3, #0]
|
|
8002df4: 689b ldr r3, [r3, #8]
|
|
8002df6: f423 4303 bic.w r3, r3, #33536 @ 0x8300
|
|
8002dfa: f023 03ff bic.w r3, r3, #255 @ 0xff
|
|
8002dfe: 687a ldr r2, [r7, #4]
|
|
8002e00: 6911 ldr r1, [r2, #16]
|
|
8002e02: 687a ldr r2, [r7, #4]
|
|
8002e04: 68d2 ldr r2, [r2, #12]
|
|
8002e06: 4311 orrs r1, r2
|
|
8002e08: 687a ldr r2, [r7, #4]
|
|
8002e0a: 6812 ldr r2, [r2, #0]
|
|
8002e0c: 430b orrs r3, r1
|
|
8002e0e: 6093 str r3, [r2, #8]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
|
|
8002e10: 687b ldr r3, [r7, #4]
|
|
8002e12: 681b ldr r3, [r3, #0]
|
|
8002e14: 68db ldr r3, [r3, #12]
|
|
8002e16: f023 01ff bic.w r1, r3, #255 @ 0xff
|
|
8002e1a: 687b ldr r3, [r7, #4]
|
|
8002e1c: 695a ldr r2, [r3, #20]
|
|
8002e1e: 687b ldr r3, [r7, #4]
|
|
8002e20: 699b ldr r3, [r3, #24]
|
|
8002e22: 431a orrs r2, r3
|
|
8002e24: 687b ldr r3, [r7, #4]
|
|
8002e26: 681b ldr r3, [r3, #0]
|
|
8002e28: 430a orrs r2, r1
|
|
8002e2a: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8002e2c: 687b ldr r3, [r7, #4]
|
|
8002e2e: 681b ldr r3, [r3, #0]
|
|
8002e30: 681a ldr r2, [r3, #0]
|
|
8002e32: 687b ldr r3, [r7, #4]
|
|
8002e34: 681b ldr r3, [r3, #0]
|
|
8002e36: f042 0201 orr.w r2, r2, #1
|
|
8002e3a: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8002e3c: 687b ldr r3, [r7, #4]
|
|
8002e3e: 2200 movs r2, #0
|
|
8002e40: 641a str r2, [r3, #64] @ 0x40
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8002e42: 687b ldr r3, [r7, #4]
|
|
8002e44: 2220 movs r2, #32
|
|
8002e46: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8002e4a: 687b ldr r3, [r7, #4]
|
|
8002e4c: 2200 movs r2, #0
|
|
8002e4e: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8002e50: 687b ldr r3, [r7, #4]
|
|
8002e52: 2200 movs r2, #0
|
|
8002e54: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
|
|
return HAL_OK;
|
|
8002e58: 2300 movs r3, #0
|
|
}
|
|
8002e5a: 4618 mov r0, r3
|
|
8002e5c: 3710 adds r7, #16
|
|
8002e5e: 46bd mov sp, r7
|
|
8002e60: bd80 pop {r7, pc}
|
|
8002e62: bf00 nop
|
|
8002e64: 000186a0 .word 0x000186a0
|
|
8002e68: 001e847f .word 0x001e847f
|
|
8002e6c: 003d08ff .word 0x003d08ff
|
|
8002e70: 431bde83 .word 0x431bde83
|
|
8002e74: 10624dd3 .word 0x10624dd3
|
|
|
|
08002e78 <HAL_PCD_Init>:
|
|
* parameters in the PCD_InitTypeDef and initialize the associated handle.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8002e78: b580 push {r7, lr}
|
|
8002e7a: b086 sub sp, #24
|
|
8002e7c: af02 add r7, sp, #8
|
|
8002e7e: 6078 str r0, [r7, #4]
|
|
const USB_OTG_GlobalTypeDef *USBx;
|
|
#endif /* defined (USB_OTG_FS) */
|
|
uint8_t i;
|
|
|
|
/* Check the PCD handle allocation */
|
|
if (hpcd == NULL)
|
|
8002e80: 687b ldr r3, [r7, #4]
|
|
8002e82: 2b00 cmp r3, #0
|
|
8002e84: d101 bne.n 8002e8a <HAL_PCD_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8002e86: 2301 movs r3, #1
|
|
8002e88: e108 b.n 800309c <HAL_PCD_Init+0x224>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
|
|
|
|
#if defined (USB_OTG_FS)
|
|
USBx = hpcd->Instance;
|
|
8002e8a: 687b ldr r3, [r7, #4]
|
|
8002e8c: 681b ldr r3, [r3, #0]
|
|
8002e8e: 60bb str r3, [r7, #8]
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
if (hpcd->State == HAL_PCD_STATE_RESET)
|
|
8002e90: 687b ldr r3, [r7, #4]
|
|
8002e92: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495
|
|
8002e96: b2db uxtb r3, r3
|
|
8002e98: 2b00 cmp r3, #0
|
|
8002e9a: d106 bne.n 8002eaa <HAL_PCD_Init+0x32>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hpcd->Lock = HAL_UNLOCKED;
|
|
8002e9c: 687b ldr r3, [r7, #4]
|
|
8002e9e: 2200 movs r2, #0
|
|
8002ea0: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
/* Init the low level hardware */
|
|
hpcd->MspInitCallback(hpcd);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_PCD_MspInit(hpcd);
|
|
8002ea4: 6878 ldr r0, [r7, #4]
|
|
8002ea6: f007 fc65 bl 800a774 <HAL_PCD_MspInit>
|
|
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
hpcd->State = HAL_PCD_STATE_BUSY;
|
|
8002eaa: 687b ldr r3, [r7, #4]
|
|
8002eac: 2203 movs r2, #3
|
|
8002eae: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
|
|
#if defined (USB_OTG_FS)
|
|
/* Disable DMA mode for FS instance */
|
|
if (USBx == USB_OTG_FS)
|
|
8002eb2: 68bb ldr r3, [r7, #8]
|
|
8002eb4: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8002eb8: d102 bne.n 8002ec0 <HAL_PCD_Init+0x48>
|
|
{
|
|
hpcd->Init.dma_enable = 0U;
|
|
8002eba: 687b ldr r3, [r7, #4]
|
|
8002ebc: 2200 movs r2, #0
|
|
8002ebe: 719a strb r2, [r3, #6]
|
|
}
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
/* Disable the Interrupts */
|
|
__HAL_PCD_DISABLE(hpcd);
|
|
8002ec0: 687b ldr r3, [r7, #4]
|
|
8002ec2: 681b ldr r3, [r3, #0]
|
|
8002ec4: 4618 mov r0, r3
|
|
8002ec6: f004 fb5a bl 800757e <USB_DisableGlobalInt>
|
|
|
|
/*Init the Core (common init.) */
|
|
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8002eca: 687b ldr r3, [r7, #4]
|
|
8002ecc: 6818 ldr r0, [r3, #0]
|
|
8002ece: 687b ldr r3, [r7, #4]
|
|
8002ed0: 7c1a ldrb r2, [r3, #16]
|
|
8002ed2: f88d 2000 strb.w r2, [sp]
|
|
8002ed6: 3304 adds r3, #4
|
|
8002ed8: cb0e ldmia r3, {r1, r2, r3}
|
|
8002eda: f004 fa39 bl 8007350 <USB_CoreInit>
|
|
8002ede: 4603 mov r3, r0
|
|
8002ee0: 2b00 cmp r3, #0
|
|
8002ee2: d005 beq.n 8002ef0 <HAL_PCD_Init+0x78>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8002ee4: 687b ldr r3, [r7, #4]
|
|
8002ee6: 2202 movs r2, #2
|
|
8002ee8: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8002eec: 2301 movs r3, #1
|
|
8002eee: e0d5 b.n 800309c <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
/* Force Device Mode */
|
|
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
|
|
8002ef0: 687b ldr r3, [r7, #4]
|
|
8002ef2: 681b ldr r3, [r3, #0]
|
|
8002ef4: 2100 movs r1, #0
|
|
8002ef6: 4618 mov r0, r3
|
|
8002ef8: f004 fb52 bl 80075a0 <USB_SetCurrentMode>
|
|
8002efc: 4603 mov r3, r0
|
|
8002efe: 2b00 cmp r3, #0
|
|
8002f00: d005 beq.n 8002f0e <HAL_PCD_Init+0x96>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8002f02: 687b ldr r3, [r7, #4]
|
|
8002f04: 2202 movs r2, #2
|
|
8002f06: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8002f0a: 2301 movs r3, #1
|
|
8002f0c: e0c6 b.n 800309c <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
/* Init endpoints structures */
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8002f0e: 2300 movs r3, #0
|
|
8002f10: 73fb strb r3, [r7, #15]
|
|
8002f12: e04a b.n 8002faa <HAL_PCD_Init+0x132>
|
|
{
|
|
/* Init ep structure */
|
|
hpcd->IN_ep[i].is_in = 1U;
|
|
8002f14: 7bfa ldrb r2, [r7, #15]
|
|
8002f16: 6879 ldr r1, [r7, #4]
|
|
8002f18: 4613 mov r3, r2
|
|
8002f1a: 00db lsls r3, r3, #3
|
|
8002f1c: 4413 add r3, r2
|
|
8002f1e: 009b lsls r3, r3, #2
|
|
8002f20: 440b add r3, r1
|
|
8002f22: 3315 adds r3, #21
|
|
8002f24: 2201 movs r2, #1
|
|
8002f26: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].num = i;
|
|
8002f28: 7bfa ldrb r2, [r7, #15]
|
|
8002f2a: 6879 ldr r1, [r7, #4]
|
|
8002f2c: 4613 mov r3, r2
|
|
8002f2e: 00db lsls r3, r3, #3
|
|
8002f30: 4413 add r3, r2
|
|
8002f32: 009b lsls r3, r3, #2
|
|
8002f34: 440b add r3, r1
|
|
8002f36: 3314 adds r3, #20
|
|
8002f38: 7bfa ldrb r2, [r7, #15]
|
|
8002f3a: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].tx_fifo_num = i;
|
|
8002f3c: 7bfa ldrb r2, [r7, #15]
|
|
8002f3e: 7bfb ldrb r3, [r7, #15]
|
|
8002f40: b298 uxth r0, r3
|
|
8002f42: 6879 ldr r1, [r7, #4]
|
|
8002f44: 4613 mov r3, r2
|
|
8002f46: 00db lsls r3, r3, #3
|
|
8002f48: 4413 add r3, r2
|
|
8002f4a: 009b lsls r3, r3, #2
|
|
8002f4c: 440b add r3, r1
|
|
8002f4e: 332e adds r3, #46 @ 0x2e
|
|
8002f50: 4602 mov r2, r0
|
|
8002f52: 801a strh r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
|
|
8002f54: 7bfa ldrb r2, [r7, #15]
|
|
8002f56: 6879 ldr r1, [r7, #4]
|
|
8002f58: 4613 mov r3, r2
|
|
8002f5a: 00db lsls r3, r3, #3
|
|
8002f5c: 4413 add r3, r2
|
|
8002f5e: 009b lsls r3, r3, #2
|
|
8002f60: 440b add r3, r1
|
|
8002f62: 3318 adds r3, #24
|
|
8002f64: 2200 movs r2, #0
|
|
8002f66: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].maxpacket = 0U;
|
|
8002f68: 7bfa ldrb r2, [r7, #15]
|
|
8002f6a: 6879 ldr r1, [r7, #4]
|
|
8002f6c: 4613 mov r3, r2
|
|
8002f6e: 00db lsls r3, r3, #3
|
|
8002f70: 4413 add r3, r2
|
|
8002f72: 009b lsls r3, r3, #2
|
|
8002f74: 440b add r3, r1
|
|
8002f76: 331c adds r3, #28
|
|
8002f78: 2200 movs r2, #0
|
|
8002f7a: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_buff = 0U;
|
|
8002f7c: 7bfa ldrb r2, [r7, #15]
|
|
8002f7e: 6879 ldr r1, [r7, #4]
|
|
8002f80: 4613 mov r3, r2
|
|
8002f82: 00db lsls r3, r3, #3
|
|
8002f84: 4413 add r3, r2
|
|
8002f86: 009b lsls r3, r3, #2
|
|
8002f88: 440b add r3, r1
|
|
8002f8a: 3320 adds r3, #32
|
|
8002f8c: 2200 movs r2, #0
|
|
8002f8e: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_len = 0U;
|
|
8002f90: 7bfa ldrb r2, [r7, #15]
|
|
8002f92: 6879 ldr r1, [r7, #4]
|
|
8002f94: 4613 mov r3, r2
|
|
8002f96: 00db lsls r3, r3, #3
|
|
8002f98: 4413 add r3, r2
|
|
8002f9a: 009b lsls r3, r3, #2
|
|
8002f9c: 440b add r3, r1
|
|
8002f9e: 3324 adds r3, #36 @ 0x24
|
|
8002fa0: 2200 movs r2, #0
|
|
8002fa2: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8002fa4: 7bfb ldrb r3, [r7, #15]
|
|
8002fa6: 3301 adds r3, #1
|
|
8002fa8: 73fb strb r3, [r7, #15]
|
|
8002faa: 687b ldr r3, [r7, #4]
|
|
8002fac: 791b ldrb r3, [r3, #4]
|
|
8002fae: 7bfa ldrb r2, [r7, #15]
|
|
8002fb0: 429a cmp r2, r3
|
|
8002fb2: d3af bcc.n 8002f14 <HAL_PCD_Init+0x9c>
|
|
}
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8002fb4: 2300 movs r3, #0
|
|
8002fb6: 73fb strb r3, [r7, #15]
|
|
8002fb8: e044 b.n 8003044 <HAL_PCD_Init+0x1cc>
|
|
{
|
|
hpcd->OUT_ep[i].is_in = 0U;
|
|
8002fba: 7bfa ldrb r2, [r7, #15]
|
|
8002fbc: 6879 ldr r1, [r7, #4]
|
|
8002fbe: 4613 mov r3, r2
|
|
8002fc0: 00db lsls r3, r3, #3
|
|
8002fc2: 4413 add r3, r2
|
|
8002fc4: 009b lsls r3, r3, #2
|
|
8002fc6: 440b add r3, r1
|
|
8002fc8: f203 2355 addw r3, r3, #597 @ 0x255
|
|
8002fcc: 2200 movs r2, #0
|
|
8002fce: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].num = i;
|
|
8002fd0: 7bfa ldrb r2, [r7, #15]
|
|
8002fd2: 6879 ldr r1, [r7, #4]
|
|
8002fd4: 4613 mov r3, r2
|
|
8002fd6: 00db lsls r3, r3, #3
|
|
8002fd8: 4413 add r3, r2
|
|
8002fda: 009b lsls r3, r3, #2
|
|
8002fdc: 440b add r3, r1
|
|
8002fde: f503 7315 add.w r3, r3, #596 @ 0x254
|
|
8002fe2: 7bfa ldrb r2, [r7, #15]
|
|
8002fe4: 701a strb r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
|
|
8002fe6: 7bfa ldrb r2, [r7, #15]
|
|
8002fe8: 6879 ldr r1, [r7, #4]
|
|
8002fea: 4613 mov r3, r2
|
|
8002fec: 00db lsls r3, r3, #3
|
|
8002fee: 4413 add r3, r2
|
|
8002ff0: 009b lsls r3, r3, #2
|
|
8002ff2: 440b add r3, r1
|
|
8002ff4: f503 7316 add.w r3, r3, #600 @ 0x258
|
|
8002ff8: 2200 movs r2, #0
|
|
8002ffa: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].maxpacket = 0U;
|
|
8002ffc: 7bfa ldrb r2, [r7, #15]
|
|
8002ffe: 6879 ldr r1, [r7, #4]
|
|
8003000: 4613 mov r3, r2
|
|
8003002: 00db lsls r3, r3, #3
|
|
8003004: 4413 add r3, r2
|
|
8003006: 009b lsls r3, r3, #2
|
|
8003008: 440b add r3, r1
|
|
800300a: f503 7317 add.w r3, r3, #604 @ 0x25c
|
|
800300e: 2200 movs r2, #0
|
|
8003010: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_buff = 0U;
|
|
8003012: 7bfa ldrb r2, [r7, #15]
|
|
8003014: 6879 ldr r1, [r7, #4]
|
|
8003016: 4613 mov r3, r2
|
|
8003018: 00db lsls r3, r3, #3
|
|
800301a: 4413 add r3, r2
|
|
800301c: 009b lsls r3, r3, #2
|
|
800301e: 440b add r3, r1
|
|
8003020: f503 7318 add.w r3, r3, #608 @ 0x260
|
|
8003024: 2200 movs r2, #0
|
|
8003026: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_len = 0U;
|
|
8003028: 7bfa ldrb r2, [r7, #15]
|
|
800302a: 6879 ldr r1, [r7, #4]
|
|
800302c: 4613 mov r3, r2
|
|
800302e: 00db lsls r3, r3, #3
|
|
8003030: 4413 add r3, r2
|
|
8003032: 009b lsls r3, r3, #2
|
|
8003034: 440b add r3, r1
|
|
8003036: f503 7319 add.w r3, r3, #612 @ 0x264
|
|
800303a: 2200 movs r2, #0
|
|
800303c: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
800303e: 7bfb ldrb r3, [r7, #15]
|
|
8003040: 3301 adds r3, #1
|
|
8003042: 73fb strb r3, [r7, #15]
|
|
8003044: 687b ldr r3, [r7, #4]
|
|
8003046: 791b ldrb r3, [r3, #4]
|
|
8003048: 7bfa ldrb r2, [r7, #15]
|
|
800304a: 429a cmp r2, r3
|
|
800304c: d3b5 bcc.n 8002fba <HAL_PCD_Init+0x142>
|
|
}
|
|
|
|
/* Init Device */
|
|
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
800304e: 687b ldr r3, [r7, #4]
|
|
8003050: 6818 ldr r0, [r3, #0]
|
|
8003052: 687b ldr r3, [r7, #4]
|
|
8003054: 7c1a ldrb r2, [r3, #16]
|
|
8003056: f88d 2000 strb.w r2, [sp]
|
|
800305a: 3304 adds r3, #4
|
|
800305c: cb0e ldmia r3, {r1, r2, r3}
|
|
800305e: f004 faeb bl 8007638 <USB_DevInit>
|
|
8003062: 4603 mov r3, r0
|
|
8003064: 2b00 cmp r3, #0
|
|
8003066: d005 beq.n 8003074 <HAL_PCD_Init+0x1fc>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8003068: 687b ldr r3, [r7, #4]
|
|
800306a: 2202 movs r2, #2
|
|
800306c: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8003070: 2301 movs r3, #1
|
|
8003072: e013 b.n 800309c <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
hpcd->USB_Address = 0U;
|
|
8003074: 687b ldr r3, [r7, #4]
|
|
8003076: 2200 movs r2, #0
|
|
8003078: 745a strb r2, [r3, #17]
|
|
hpcd->State = HAL_PCD_STATE_READY;
|
|
800307a: 687b ldr r3, [r7, #4]
|
|
800307c: 2201 movs r2, #1
|
|
800307e: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* Activate LPM */
|
|
if (hpcd->Init.lpm_enable == 1U)
|
|
8003082: 687b ldr r3, [r7, #4]
|
|
8003084: 7b1b ldrb r3, [r3, #12]
|
|
8003086: 2b01 cmp r3, #1
|
|
8003088: d102 bne.n 8003090 <HAL_PCD_Init+0x218>
|
|
{
|
|
(void)HAL_PCDEx_ActivateLPM(hpcd);
|
|
800308a: 6878 ldr r0, [r7, #4]
|
|
800308c: f001 f956 bl 800433c <HAL_PCDEx_ActivateLPM>
|
|
}
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
(void)USB_DevDisconnect(hpcd->Instance);
|
|
8003090: 687b ldr r3, [r7, #4]
|
|
8003092: 681b ldr r3, [r3, #0]
|
|
8003094: 4618 mov r0, r3
|
|
8003096: f005 fb28 bl 80086ea <USB_DevDisconnect>
|
|
|
|
return HAL_OK;
|
|
800309a: 2300 movs r3, #0
|
|
}
|
|
800309c: 4618 mov r0, r3
|
|
800309e: 3710 adds r7, #16
|
|
80030a0: 46bd mov sp, r7
|
|
80030a2: bd80 pop {r7, pc}
|
|
|
|
080030a4 <HAL_PCD_Start>:
|
|
* @brief Start the USB device
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
80030a4: b580 push {r7, lr}
|
|
80030a6: b084 sub sp, #16
|
|
80030a8: af00 add r7, sp, #0
|
|
80030aa: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
80030ac: 687b ldr r3, [r7, #4]
|
|
80030ae: 681b ldr r3, [r3, #0]
|
|
80030b0: 60fb str r3, [r7, #12]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
80030b2: 687b ldr r3, [r7, #4]
|
|
80030b4: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
80030b8: 2b01 cmp r3, #1
|
|
80030ba: d101 bne.n 80030c0 <HAL_PCD_Start+0x1c>
|
|
80030bc: 2302 movs r3, #2
|
|
80030be: e022 b.n 8003106 <HAL_PCD_Start+0x62>
|
|
80030c0: 687b ldr r3, [r7, #4]
|
|
80030c2: 2201 movs r2, #1
|
|
80030c4: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
|
|
80030c8: 68fb ldr r3, [r7, #12]
|
|
80030ca: 68db ldr r3, [r3, #12]
|
|
80030cc: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80030d0: 2b00 cmp r3, #0
|
|
80030d2: d009 beq.n 80030e8 <HAL_PCD_Start+0x44>
|
|
(hpcd->Init.battery_charging_enable == 1U))
|
|
80030d4: 687b ldr r3, [r7, #4]
|
|
80030d6: 7b5b ldrb r3, [r3, #13]
|
|
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
|
|
80030d8: 2b01 cmp r3, #1
|
|
80030da: d105 bne.n 80030e8 <HAL_PCD_Start+0x44>
|
|
{
|
|
/* Enable USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
80030dc: 68fb ldr r3, [r7, #12]
|
|
80030de: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80030e0: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
80030e4: 68fb ldr r3, [r7, #12]
|
|
80030e6: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
|
|
__HAL_PCD_ENABLE(hpcd);
|
|
80030e8: 687b ldr r3, [r7, #4]
|
|
80030ea: 681b ldr r3, [r3, #0]
|
|
80030ec: 4618 mov r0, r3
|
|
80030ee: f004 fa35 bl 800755c <USB_EnableGlobalInt>
|
|
(void)USB_DevConnect(hpcd->Instance);
|
|
80030f2: 687b ldr r3, [r7, #4]
|
|
80030f4: 681b ldr r3, [r3, #0]
|
|
80030f6: 4618 mov r0, r3
|
|
80030f8: f005 fad6 bl 80086a8 <USB_DevConnect>
|
|
__HAL_UNLOCK(hpcd);
|
|
80030fc: 687b ldr r3, [r7, #4]
|
|
80030fe: 2200 movs r2, #0
|
|
8003100: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8003104: 2300 movs r3, #0
|
|
}
|
|
8003106: 4618 mov r0, r3
|
|
8003108: 3710 adds r7, #16
|
|
800310a: 46bd mov sp, r7
|
|
800310c: bd80 pop {r7, pc}
|
|
|
|
0800310e <HAL_PCD_IRQHandler>:
|
|
* @brief Handles PCD interrupt request.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
800310e: b590 push {r4, r7, lr}
|
|
8003110: b08d sub sp, #52 @ 0x34
|
|
8003112: af00 add r7, sp, #0
|
|
8003114: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8003116: 687b ldr r3, [r7, #4]
|
|
8003118: 681b ldr r3, [r3, #0]
|
|
800311a: 623b str r3, [r7, #32]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800311c: 6a3b ldr r3, [r7, #32]
|
|
800311e: 61fb str r3, [r7, #28]
|
|
uint32_t epnum;
|
|
uint32_t fifoemptymsk;
|
|
uint32_t RegVal;
|
|
|
|
/* ensure that we are in device mode */
|
|
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
|
|
8003120: 687b ldr r3, [r7, #4]
|
|
8003122: 681b ldr r3, [r3, #0]
|
|
8003124: 4618 mov r0, r3
|
|
8003126: f005 fb94 bl 8008852 <USB_GetMode>
|
|
800312a: 4603 mov r3, r0
|
|
800312c: 2b00 cmp r3, #0
|
|
800312e: f040 84b9 bne.w 8003aa4 <HAL_PCD_IRQHandler+0x996>
|
|
{
|
|
/* avoid spurious interrupt */
|
|
if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
|
|
8003132: 687b ldr r3, [r7, #4]
|
|
8003134: 681b ldr r3, [r3, #0]
|
|
8003136: 4618 mov r0, r3
|
|
8003138: f005 faf8 bl 800872c <USB_ReadInterrupts>
|
|
800313c: 4603 mov r3, r0
|
|
800313e: 2b00 cmp r3, #0
|
|
8003140: f000 84af beq.w 8003aa2 <HAL_PCD_IRQHandler+0x994>
|
|
{
|
|
return;
|
|
}
|
|
|
|
/* store current frame number */
|
|
hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos;
|
|
8003144: 69fb ldr r3, [r7, #28]
|
|
8003146: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800314a: 689b ldr r3, [r3, #8]
|
|
800314c: 0a1b lsrs r3, r3, #8
|
|
800314e: f3c3 020d ubfx r2, r3, #0, #14
|
|
8003152: 687b ldr r3, [r7, #4]
|
|
8003154: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
|
|
8003158: 687b ldr r3, [r7, #4]
|
|
800315a: 681b ldr r3, [r3, #0]
|
|
800315c: 4618 mov r0, r3
|
|
800315e: f005 fae5 bl 800872c <USB_ReadInterrupts>
|
|
8003162: 4603 mov r3, r0
|
|
8003164: f003 0302 and.w r3, r3, #2
|
|
8003168: 2b02 cmp r3, #2
|
|
800316a: d107 bne.n 800317c <HAL_PCD_IRQHandler+0x6e>
|
|
{
|
|
/* incorrect mode, acknowledge the interrupt */
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
|
|
800316c: 687b ldr r3, [r7, #4]
|
|
800316e: 681b ldr r3, [r3, #0]
|
|
8003170: 695a ldr r2, [r3, #20]
|
|
8003172: 687b ldr r3, [r7, #4]
|
|
8003174: 681b ldr r3, [r3, #0]
|
|
8003176: f002 0202 and.w r2, r2, #2
|
|
800317a: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle RxQLevel Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
|
|
800317c: 687b ldr r3, [r7, #4]
|
|
800317e: 681b ldr r3, [r3, #0]
|
|
8003180: 4618 mov r0, r3
|
|
8003182: f005 fad3 bl 800872c <USB_ReadInterrupts>
|
|
8003186: 4603 mov r3, r0
|
|
8003188: f003 0310 and.w r3, r3, #16
|
|
800318c: 2b10 cmp r3, #16
|
|
800318e: d161 bne.n 8003254 <HAL_PCD_IRQHandler+0x146>
|
|
{
|
|
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
8003190: 687b ldr r3, [r7, #4]
|
|
8003192: 681b ldr r3, [r3, #0]
|
|
8003194: 699a ldr r2, [r3, #24]
|
|
8003196: 687b ldr r3, [r7, #4]
|
|
8003198: 681b ldr r3, [r3, #0]
|
|
800319a: f022 0210 bic.w r2, r2, #16
|
|
800319e: 619a str r2, [r3, #24]
|
|
|
|
RegVal = USBx->GRXSTSP;
|
|
80031a0: 6a3b ldr r3, [r7, #32]
|
|
80031a2: 6a1b ldr r3, [r3, #32]
|
|
80031a4: 61bb str r3, [r7, #24]
|
|
|
|
ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM];
|
|
80031a6: 69bb ldr r3, [r7, #24]
|
|
80031a8: f003 020f and.w r2, r3, #15
|
|
80031ac: 4613 mov r3, r2
|
|
80031ae: 00db lsls r3, r3, #3
|
|
80031b0: 4413 add r3, r2
|
|
80031b2: 009b lsls r3, r3, #2
|
|
80031b4: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
80031b8: 687a ldr r2, [r7, #4]
|
|
80031ba: 4413 add r3, r2
|
|
80031bc: 3304 adds r3, #4
|
|
80031be: 617b str r3, [r7, #20]
|
|
|
|
if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
|
|
80031c0: 69bb ldr r3, [r7, #24]
|
|
80031c2: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
|
|
80031c6: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
80031ca: d124 bne.n 8003216 <HAL_PCD_IRQHandler+0x108>
|
|
{
|
|
if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U)
|
|
80031cc: 69ba ldr r2, [r7, #24]
|
|
80031ce: f647 73f0 movw r3, #32752 @ 0x7ff0
|
|
80031d2: 4013 ands r3, r2
|
|
80031d4: 2b00 cmp r3, #0
|
|
80031d6: d035 beq.n 8003244 <HAL_PCD_IRQHandler+0x136>
|
|
{
|
|
(void)USB_ReadPacket(USBx, ep->xfer_buff,
|
|
80031d8: 697b ldr r3, [r7, #20]
|
|
80031da: 68d9 ldr r1, [r3, #12]
|
|
(uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4));
|
|
80031dc: 69bb ldr r3, [r7, #24]
|
|
80031de: 091b lsrs r3, r3, #4
|
|
80031e0: b29b uxth r3, r3
|
|
(void)USB_ReadPacket(USBx, ep->xfer_buff,
|
|
80031e2: f3c3 030a ubfx r3, r3, #0, #11
|
|
80031e6: b29b uxth r3, r3
|
|
80031e8: 461a mov r2, r3
|
|
80031ea: 6a38 ldr r0, [r7, #32]
|
|
80031ec: f005 f90a bl 8008404 <USB_ReadPacket>
|
|
|
|
ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
80031f0: 697b ldr r3, [r7, #20]
|
|
80031f2: 68da ldr r2, [r3, #12]
|
|
80031f4: 69bb ldr r3, [r7, #24]
|
|
80031f6: 091b lsrs r3, r3, #4
|
|
80031f8: f3c3 030a ubfx r3, r3, #0, #11
|
|
80031fc: 441a add r2, r3
|
|
80031fe: 697b ldr r3, [r7, #20]
|
|
8003200: 60da str r2, [r3, #12]
|
|
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8003202: 697b ldr r3, [r7, #20]
|
|
8003204: 695a ldr r2, [r3, #20]
|
|
8003206: 69bb ldr r3, [r7, #24]
|
|
8003208: 091b lsrs r3, r3, #4
|
|
800320a: f3c3 030a ubfx r3, r3, #0, #11
|
|
800320e: 441a add r2, r3
|
|
8003210: 697b ldr r3, [r7, #20]
|
|
8003212: 615a str r2, [r3, #20]
|
|
8003214: e016 b.n 8003244 <HAL_PCD_IRQHandler+0x136>
|
|
}
|
|
}
|
|
else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
|
|
8003216: 69bb ldr r3, [r7, #24]
|
|
8003218: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
|
|
800321c: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000
|
|
8003220: d110 bne.n 8003244 <HAL_PCD_IRQHandler+0x136>
|
|
{
|
|
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
|
|
8003222: 687b ldr r3, [r7, #4]
|
|
8003224: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8003228: 2208 movs r2, #8
|
|
800322a: 4619 mov r1, r3
|
|
800322c: 6a38 ldr r0, [r7, #32]
|
|
800322e: f005 f8e9 bl 8008404 <USB_ReadPacket>
|
|
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8003232: 697b ldr r3, [r7, #20]
|
|
8003234: 695a ldr r2, [r3, #20]
|
|
8003236: 69bb ldr r3, [r7, #24]
|
|
8003238: 091b lsrs r3, r3, #4
|
|
800323a: f3c3 030a ubfx r3, r3, #0, #11
|
|
800323e: 441a add r2, r3
|
|
8003240: 697b ldr r3, [r7, #20]
|
|
8003242: 615a str r2, [r3, #20]
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
|
|
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
8003244: 687b ldr r3, [r7, #4]
|
|
8003246: 681b ldr r3, [r3, #0]
|
|
8003248: 699a ldr r2, [r3, #24]
|
|
800324a: 687b ldr r3, [r7, #4]
|
|
800324c: 681b ldr r3, [r3, #0]
|
|
800324e: f042 0210 orr.w r2, r2, #16
|
|
8003252: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
|
|
8003254: 687b ldr r3, [r7, #4]
|
|
8003256: 681b ldr r3, [r3, #0]
|
|
8003258: 4618 mov r0, r3
|
|
800325a: f005 fa67 bl 800872c <USB_ReadInterrupts>
|
|
800325e: 4603 mov r3, r0
|
|
8003260: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8003264: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
|
|
8003268: f040 80a7 bne.w 80033ba <HAL_PCD_IRQHandler+0x2ac>
|
|
{
|
|
epnum = 0U;
|
|
800326c: 2300 movs r3, #0
|
|
800326e: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Read in the device interrupt bits */
|
|
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
|
|
8003270: 687b ldr r3, [r7, #4]
|
|
8003272: 681b ldr r3, [r3, #0]
|
|
8003274: 4618 mov r0, r3
|
|
8003276: f005 fa6c bl 8008752 <USB_ReadDevAllOutEpInterrupt>
|
|
800327a: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
while (ep_intr != 0U)
|
|
800327c: e099 b.n 80033b2 <HAL_PCD_IRQHandler+0x2a4>
|
|
{
|
|
if ((ep_intr & 0x1U) != 0U)
|
|
800327e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003280: f003 0301 and.w r3, r3, #1
|
|
8003284: 2b00 cmp r3, #0
|
|
8003286: f000 808e beq.w 80033a6 <HAL_PCD_IRQHandler+0x298>
|
|
{
|
|
epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
|
|
800328a: 687b ldr r3, [r7, #4]
|
|
800328c: 681b ldr r3, [r3, #0]
|
|
800328e: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8003290: b2d2 uxtb r2, r2
|
|
8003292: 4611 mov r1, r2
|
|
8003294: 4618 mov r0, r3
|
|
8003296: f005 fa90 bl 80087ba <USB_ReadDevOutEPInterrupt>
|
|
800329a: 6138 str r0, [r7, #16]
|
|
|
|
if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
|
|
800329c: 693b ldr r3, [r7, #16]
|
|
800329e: f003 0301 and.w r3, r3, #1
|
|
80032a2: 2b00 cmp r3, #0
|
|
80032a4: d00c beq.n 80032c0 <HAL_PCD_IRQHandler+0x1b2>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
|
|
80032a6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80032a8: 015a lsls r2, r3, #5
|
|
80032aa: 69fb ldr r3, [r7, #28]
|
|
80032ac: 4413 add r3, r2
|
|
80032ae: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80032b2: 461a mov r2, r3
|
|
80032b4: 2301 movs r3, #1
|
|
80032b6: 6093 str r3, [r2, #8]
|
|
(void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
|
|
80032b8: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
80032ba: 6878 ldr r0, [r7, #4]
|
|
80032bc: f000 feb8 bl 8004030 <PCD_EP_OutXfrComplete_int>
|
|
}
|
|
|
|
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
|
|
80032c0: 693b ldr r3, [r7, #16]
|
|
80032c2: f003 0308 and.w r3, r3, #8
|
|
80032c6: 2b00 cmp r3, #0
|
|
80032c8: d00c beq.n 80032e4 <HAL_PCD_IRQHandler+0x1d6>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
|
|
80032ca: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80032cc: 015a lsls r2, r3, #5
|
|
80032ce: 69fb ldr r3, [r7, #28]
|
|
80032d0: 4413 add r3, r2
|
|
80032d2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80032d6: 461a mov r2, r3
|
|
80032d8: 2308 movs r3, #8
|
|
80032da: 6093 str r3, [r2, #8]
|
|
/* Class B setup phase done for previous decoded setup */
|
|
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
|
|
80032dc: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
80032de: 6878 ldr r0, [r7, #4]
|
|
80032e0: f000 ff8e bl 8004200 <PCD_EP_OutSetupPacket_int>
|
|
}
|
|
|
|
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
|
|
80032e4: 693b ldr r3, [r7, #16]
|
|
80032e6: f003 0310 and.w r3, r3, #16
|
|
80032ea: 2b00 cmp r3, #0
|
|
80032ec: d008 beq.n 8003300 <HAL_PCD_IRQHandler+0x1f2>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
|
|
80032ee: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80032f0: 015a lsls r2, r3, #5
|
|
80032f2: 69fb ldr r3, [r7, #28]
|
|
80032f4: 4413 add r3, r2
|
|
80032f6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80032fa: 461a mov r2, r3
|
|
80032fc: 2310 movs r3, #16
|
|
80032fe: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear OUT Endpoint disable interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
|
|
8003300: 693b ldr r3, [r7, #16]
|
|
8003302: f003 0302 and.w r3, r3, #2
|
|
8003306: 2b00 cmp r3, #0
|
|
8003308: d030 beq.n 800336c <HAL_PCD_IRQHandler+0x25e>
|
|
{
|
|
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF)
|
|
800330a: 6a3b ldr r3, [r7, #32]
|
|
800330c: 695b ldr r3, [r3, #20]
|
|
800330e: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8003312: 2b80 cmp r3, #128 @ 0x80
|
|
8003314: d109 bne.n 800332a <HAL_PCD_IRQHandler+0x21c>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
|
|
8003316: 69fb ldr r3, [r7, #28]
|
|
8003318: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800331c: 685b ldr r3, [r3, #4]
|
|
800331e: 69fa ldr r2, [r7, #28]
|
|
8003320: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8003324: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8003328: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
ep = &hpcd->OUT_ep[epnum];
|
|
800332a: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800332c: 4613 mov r3, r2
|
|
800332e: 00db lsls r3, r3, #3
|
|
8003330: 4413 add r3, r2
|
|
8003332: 009b lsls r3, r3, #2
|
|
8003334: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003338: 687a ldr r2, [r7, #4]
|
|
800333a: 4413 add r3, r2
|
|
800333c: 3304 adds r3, #4
|
|
800333e: 617b str r3, [r7, #20]
|
|
|
|
if (ep->is_iso_incomplete == 1U)
|
|
8003340: 697b ldr r3, [r7, #20]
|
|
8003342: 78db ldrb r3, [r3, #3]
|
|
8003344: 2b01 cmp r3, #1
|
|
8003346: d108 bne.n 800335a <HAL_PCD_IRQHandler+0x24c>
|
|
{
|
|
ep->is_iso_incomplete = 0U;
|
|
8003348: 697b ldr r3, [r7, #20]
|
|
800334a: 2200 movs r2, #0
|
|
800334c: 70da strb r2, [r3, #3]
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
800334e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003350: b2db uxtb r3, r3
|
|
8003352: 4619 mov r1, r3
|
|
8003354: 6878 ldr r0, [r7, #4]
|
|
8003356: f007 fb29 bl 800a9ac <HAL_PCD_ISOOUTIncompleteCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
|
|
800335a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800335c: 015a lsls r2, r3, #5
|
|
800335e: 69fb ldr r3, [r7, #28]
|
|
8003360: 4413 add r3, r2
|
|
8003362: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003366: 461a mov r2, r3
|
|
8003368: 2302 movs r3, #2
|
|
800336a: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear Status Phase Received interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
|
|
800336c: 693b ldr r3, [r7, #16]
|
|
800336e: f003 0320 and.w r3, r3, #32
|
|
8003372: 2b00 cmp r3, #0
|
|
8003374: d008 beq.n 8003388 <HAL_PCD_IRQHandler+0x27a>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
8003376: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003378: 015a lsls r2, r3, #5
|
|
800337a: 69fb ldr r3, [r7, #28]
|
|
800337c: 4413 add r3, r2
|
|
800337e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003382: 461a mov r2, r3
|
|
8003384: 2320 movs r3, #32
|
|
8003386: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear OUT NAK interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
|
|
8003388: 693b ldr r3, [r7, #16]
|
|
800338a: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
800338e: 2b00 cmp r3, #0
|
|
8003390: d009 beq.n 80033a6 <HAL_PCD_IRQHandler+0x298>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
|
|
8003392: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003394: 015a lsls r2, r3, #5
|
|
8003396: 69fb ldr r3, [r7, #28]
|
|
8003398: 4413 add r3, r2
|
|
800339a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800339e: 461a mov r2, r3
|
|
80033a0: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
80033a4: 6093 str r3, [r2, #8]
|
|
}
|
|
}
|
|
epnum++;
|
|
80033a6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80033a8: 3301 adds r3, #1
|
|
80033aa: 627b str r3, [r7, #36] @ 0x24
|
|
ep_intr >>= 1U;
|
|
80033ac: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80033ae: 085b lsrs r3, r3, #1
|
|
80033b0: 62bb str r3, [r7, #40] @ 0x28
|
|
while (ep_intr != 0U)
|
|
80033b2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80033b4: 2b00 cmp r3, #0
|
|
80033b6: f47f af62 bne.w 800327e <HAL_PCD_IRQHandler+0x170>
|
|
}
|
|
}
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
|
|
80033ba: 687b ldr r3, [r7, #4]
|
|
80033bc: 681b ldr r3, [r3, #0]
|
|
80033be: 4618 mov r0, r3
|
|
80033c0: f005 f9b4 bl 800872c <USB_ReadInterrupts>
|
|
80033c4: 4603 mov r3, r0
|
|
80033c6: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
80033ca: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
80033ce: f040 80db bne.w 8003588 <HAL_PCD_IRQHandler+0x47a>
|
|
{
|
|
/* Read in the device interrupt bits */
|
|
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
|
|
80033d2: 687b ldr r3, [r7, #4]
|
|
80033d4: 681b ldr r3, [r3, #0]
|
|
80033d6: 4618 mov r0, r3
|
|
80033d8: f005 f9d5 bl 8008786 <USB_ReadDevAllInEpInterrupt>
|
|
80033dc: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
epnum = 0U;
|
|
80033de: 2300 movs r3, #0
|
|
80033e0: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
while (ep_intr != 0U)
|
|
80033e2: e0cd b.n 8003580 <HAL_PCD_IRQHandler+0x472>
|
|
{
|
|
if ((ep_intr & 0x1U) != 0U) /* In ITR */
|
|
80033e4: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80033e6: f003 0301 and.w r3, r3, #1
|
|
80033ea: 2b00 cmp r3, #0
|
|
80033ec: f000 80c2 beq.w 8003574 <HAL_PCD_IRQHandler+0x466>
|
|
{
|
|
epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
|
|
80033f0: 687b ldr r3, [r7, #4]
|
|
80033f2: 681b ldr r3, [r3, #0]
|
|
80033f4: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80033f6: b2d2 uxtb r2, r2
|
|
80033f8: 4611 mov r1, r2
|
|
80033fa: 4618 mov r0, r3
|
|
80033fc: f005 f9fb bl 80087f6 <USB_ReadDevInEPInterrupt>
|
|
8003400: 6138 str r0, [r7, #16]
|
|
|
|
if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
|
|
8003402: 693b ldr r3, [r7, #16]
|
|
8003404: f003 0301 and.w r3, r3, #1
|
|
8003408: 2b00 cmp r3, #0
|
|
800340a: d057 beq.n 80034bc <HAL_PCD_IRQHandler+0x3ae>
|
|
{
|
|
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
|
|
800340c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800340e: f003 030f and.w r3, r3, #15
|
|
8003412: 2201 movs r2, #1
|
|
8003414: fa02 f303 lsl.w r3, r2, r3
|
|
8003418: 60fb str r3, [r7, #12]
|
|
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
|
|
800341a: 69fb ldr r3, [r7, #28]
|
|
800341c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8003420: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8003422: 68fb ldr r3, [r7, #12]
|
|
8003424: 43db mvns r3, r3
|
|
8003426: 69f9 ldr r1, [r7, #28]
|
|
8003428: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
800342c: 4013 ands r3, r2
|
|
800342e: 634b str r3, [r1, #52] @ 0x34
|
|
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
|
|
8003430: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003432: 015a lsls r2, r3, #5
|
|
8003434: 69fb ldr r3, [r7, #28]
|
|
8003436: 4413 add r3, r2
|
|
8003438: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800343c: 461a mov r2, r3
|
|
800343e: 2301 movs r3, #1
|
|
8003440: 6093 str r3, [r2, #8]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8003442: 687b ldr r3, [r7, #4]
|
|
8003444: 799b ldrb r3, [r3, #6]
|
|
8003446: 2b01 cmp r3, #1
|
|
8003448: d132 bne.n 80034b0 <HAL_PCD_IRQHandler+0x3a2>
|
|
{
|
|
hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
|
|
800344a: 6879 ldr r1, [r7, #4]
|
|
800344c: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800344e: 4613 mov r3, r2
|
|
8003450: 00db lsls r3, r3, #3
|
|
8003452: 4413 add r3, r2
|
|
8003454: 009b lsls r3, r3, #2
|
|
8003456: 440b add r3, r1
|
|
8003458: 3320 adds r3, #32
|
|
800345a: 6819 ldr r1, [r3, #0]
|
|
800345c: 6878 ldr r0, [r7, #4]
|
|
800345e: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8003460: 4613 mov r3, r2
|
|
8003462: 00db lsls r3, r3, #3
|
|
8003464: 4413 add r3, r2
|
|
8003466: 009b lsls r3, r3, #2
|
|
8003468: 4403 add r3, r0
|
|
800346a: 331c adds r3, #28
|
|
800346c: 681b ldr r3, [r3, #0]
|
|
800346e: 4419 add r1, r3
|
|
8003470: 6878 ldr r0, [r7, #4]
|
|
8003472: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8003474: 4613 mov r3, r2
|
|
8003476: 00db lsls r3, r3, #3
|
|
8003478: 4413 add r3, r2
|
|
800347a: 009b lsls r3, r3, #2
|
|
800347c: 4403 add r3, r0
|
|
800347e: 3320 adds r3, #32
|
|
8003480: 6019 str r1, [r3, #0]
|
|
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
|
|
8003482: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003484: 2b00 cmp r3, #0
|
|
8003486: d113 bne.n 80034b0 <HAL_PCD_IRQHandler+0x3a2>
|
|
8003488: 6879 ldr r1, [r7, #4]
|
|
800348a: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800348c: 4613 mov r3, r2
|
|
800348e: 00db lsls r3, r3, #3
|
|
8003490: 4413 add r3, r2
|
|
8003492: 009b lsls r3, r3, #2
|
|
8003494: 440b add r3, r1
|
|
8003496: 3324 adds r3, #36 @ 0x24
|
|
8003498: 681b ldr r3, [r3, #0]
|
|
800349a: 2b00 cmp r3, #0
|
|
800349c: d108 bne.n 80034b0 <HAL_PCD_IRQHandler+0x3a2>
|
|
{
|
|
/* prepare to rx more setup packets */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
800349e: 687b ldr r3, [r7, #4]
|
|
80034a0: 6818 ldr r0, [r3, #0]
|
|
80034a2: 687b ldr r3, [r7, #4]
|
|
80034a4: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
80034a8: 461a mov r2, r3
|
|
80034aa: 2101 movs r1, #1
|
|
80034ac: f005 fa02 bl 80088b4 <USB_EP0_OutStart>
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
|
|
80034b0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80034b2: b2db uxtb r3, r3
|
|
80034b4: 4619 mov r1, r3
|
|
80034b6: 6878 ldr r0, [r7, #4]
|
|
80034b8: f007 f9f3 bl 800a8a2 <HAL_PCD_DataInStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
|
|
80034bc: 693b ldr r3, [r7, #16]
|
|
80034be: f003 0308 and.w r3, r3, #8
|
|
80034c2: 2b00 cmp r3, #0
|
|
80034c4: d008 beq.n 80034d8 <HAL_PCD_IRQHandler+0x3ca>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
|
|
80034c6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80034c8: 015a lsls r2, r3, #5
|
|
80034ca: 69fb ldr r3, [r7, #28]
|
|
80034cc: 4413 add r3, r2
|
|
80034ce: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80034d2: 461a mov r2, r3
|
|
80034d4: 2308 movs r3, #8
|
|
80034d6: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
|
|
80034d8: 693b ldr r3, [r7, #16]
|
|
80034da: f003 0310 and.w r3, r3, #16
|
|
80034de: 2b00 cmp r3, #0
|
|
80034e0: d008 beq.n 80034f4 <HAL_PCD_IRQHandler+0x3e6>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
|
|
80034e2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80034e4: 015a lsls r2, r3, #5
|
|
80034e6: 69fb ldr r3, [r7, #28]
|
|
80034e8: 4413 add r3, r2
|
|
80034ea: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80034ee: 461a mov r2, r3
|
|
80034f0: 2310 movs r3, #16
|
|
80034f2: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
|
|
80034f4: 693b ldr r3, [r7, #16]
|
|
80034f6: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80034fa: 2b00 cmp r3, #0
|
|
80034fc: d008 beq.n 8003510 <HAL_PCD_IRQHandler+0x402>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
|
|
80034fe: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003500: 015a lsls r2, r3, #5
|
|
8003502: 69fb ldr r3, [r7, #28]
|
|
8003504: 4413 add r3, r2
|
|
8003506: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800350a: 461a mov r2, r3
|
|
800350c: 2340 movs r3, #64 @ 0x40
|
|
800350e: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
|
|
8003510: 693b ldr r3, [r7, #16]
|
|
8003512: f003 0302 and.w r3, r3, #2
|
|
8003516: 2b00 cmp r3, #0
|
|
8003518: d023 beq.n 8003562 <HAL_PCD_IRQHandler+0x454>
|
|
{
|
|
(void)USB_FlushTxFifo(USBx, epnum);
|
|
800351a: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
800351c: 6a38 ldr r0, [r7, #32]
|
|
800351e: f004 f9e9 bl 80078f4 <USB_FlushTxFifo>
|
|
|
|
ep = &hpcd->IN_ep[epnum];
|
|
8003522: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8003524: 4613 mov r3, r2
|
|
8003526: 00db lsls r3, r3, #3
|
|
8003528: 4413 add r3, r2
|
|
800352a: 009b lsls r3, r3, #2
|
|
800352c: 3310 adds r3, #16
|
|
800352e: 687a ldr r2, [r7, #4]
|
|
8003530: 4413 add r3, r2
|
|
8003532: 3304 adds r3, #4
|
|
8003534: 617b str r3, [r7, #20]
|
|
|
|
if (ep->is_iso_incomplete == 1U)
|
|
8003536: 697b ldr r3, [r7, #20]
|
|
8003538: 78db ldrb r3, [r3, #3]
|
|
800353a: 2b01 cmp r3, #1
|
|
800353c: d108 bne.n 8003550 <HAL_PCD_IRQHandler+0x442>
|
|
{
|
|
ep->is_iso_incomplete = 0U;
|
|
800353e: 697b ldr r3, [r7, #20]
|
|
8003540: 2200 movs r2, #0
|
|
8003542: 70da strb r2, [r3, #3]
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
8003544: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003546: b2db uxtb r3, r3
|
|
8003548: 4619 mov r1, r3
|
|
800354a: 6878 ldr r0, [r7, #4]
|
|
800354c: f007 fa40 bl 800a9d0 <HAL_PCD_ISOINIncompleteCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
|
|
8003550: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003552: 015a lsls r2, r3, #5
|
|
8003554: 69fb ldr r3, [r7, #28]
|
|
8003556: 4413 add r3, r2
|
|
8003558: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800355c: 461a mov r2, r3
|
|
800355e: 2302 movs r3, #2
|
|
8003560: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
|
|
8003562: 693b ldr r3, [r7, #16]
|
|
8003564: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8003568: 2b00 cmp r3, #0
|
|
800356a: d003 beq.n 8003574 <HAL_PCD_IRQHandler+0x466>
|
|
{
|
|
(void)PCD_WriteEmptyTxFifo(hpcd, epnum);
|
|
800356c: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
800356e: 6878 ldr r0, [r7, #4]
|
|
8003570: f000 fcd2 bl 8003f18 <PCD_WriteEmptyTxFifo>
|
|
}
|
|
}
|
|
epnum++;
|
|
8003574: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003576: 3301 adds r3, #1
|
|
8003578: 627b str r3, [r7, #36] @ 0x24
|
|
ep_intr >>= 1U;
|
|
800357a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800357c: 085b lsrs r3, r3, #1
|
|
800357e: 62bb str r3, [r7, #40] @ 0x28
|
|
while (ep_intr != 0U)
|
|
8003580: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003582: 2b00 cmp r3, #0
|
|
8003584: f47f af2e bne.w 80033e4 <HAL_PCD_IRQHandler+0x2d6>
|
|
}
|
|
}
|
|
|
|
/* Handle Resume Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
|
|
8003588: 687b ldr r3, [r7, #4]
|
|
800358a: 681b ldr r3, [r3, #0]
|
|
800358c: 4618 mov r0, r3
|
|
800358e: f005 f8cd bl 800872c <USB_ReadInterrupts>
|
|
8003592: 4603 mov r3, r0
|
|
8003594: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8003598: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800359c: d122 bne.n 80035e4 <HAL_PCD_IRQHandler+0x4d6>
|
|
{
|
|
/* Clear the Remote Wake-up Signaling */
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
|
|
800359e: 69fb ldr r3, [r7, #28]
|
|
80035a0: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80035a4: 685b ldr r3, [r3, #4]
|
|
80035a6: 69fa ldr r2, [r7, #28]
|
|
80035a8: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80035ac: f023 0301 bic.w r3, r3, #1
|
|
80035b0: 6053 str r3, [r2, #4]
|
|
|
|
if (hpcd->LPM_State == LPM_L1)
|
|
80035b2: 687b ldr r3, [r7, #4]
|
|
80035b4: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
|
|
80035b8: 2b01 cmp r3, #1
|
|
80035ba: d108 bne.n 80035ce <HAL_PCD_IRQHandler+0x4c0>
|
|
{
|
|
hpcd->LPM_State = LPM_L0;
|
|
80035bc: 687b ldr r3, [r7, #4]
|
|
80035be: 2200 movs r2, #0
|
|
80035c0: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
|
|
#else
|
|
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
|
|
80035c4: 2100 movs r1, #0
|
|
80035c6: 6878 ldr r0, [r7, #4]
|
|
80035c8: f007 fba8 bl 800ad1c <HAL_PCDEx_LPM_Callback>
|
|
80035cc: e002 b.n 80035d4 <HAL_PCD_IRQHandler+0x4c6>
|
|
else
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResumeCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResumeCallback(hpcd);
|
|
80035ce: 6878 ldr r0, [r7, #4]
|
|
80035d0: f007 f9de bl 800a990 <HAL_PCD_ResumeCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
|
|
80035d4: 687b ldr r3, [r7, #4]
|
|
80035d6: 681b ldr r3, [r3, #0]
|
|
80035d8: 695a ldr r2, [r3, #20]
|
|
80035da: 687b ldr r3, [r7, #4]
|
|
80035dc: 681b ldr r3, [r3, #0]
|
|
80035de: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000
|
|
80035e2: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Suspend Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
|
|
80035e4: 687b ldr r3, [r7, #4]
|
|
80035e6: 681b ldr r3, [r3, #0]
|
|
80035e8: 4618 mov r0, r3
|
|
80035ea: f005 f89f bl 800872c <USB_ReadInterrupts>
|
|
80035ee: 4603 mov r3, r0
|
|
80035f0: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80035f4: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
80035f8: d112 bne.n 8003620 <HAL_PCD_IRQHandler+0x512>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
|
|
80035fa: 69fb ldr r3, [r7, #28]
|
|
80035fc: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8003600: 689b ldr r3, [r3, #8]
|
|
8003602: f003 0301 and.w r3, r3, #1
|
|
8003606: 2b01 cmp r3, #1
|
|
8003608: d102 bne.n 8003610 <HAL_PCD_IRQHandler+0x502>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SuspendCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
800360a: 6878 ldr r0, [r7, #4]
|
|
800360c: f007 f99a bl 800a944 <HAL_PCD_SuspendCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
|
|
8003610: 687b ldr r3, [r7, #4]
|
|
8003612: 681b ldr r3, [r3, #0]
|
|
8003614: 695a ldr r2, [r3, #20]
|
|
8003616: 687b ldr r3, [r7, #4]
|
|
8003618: 681b ldr r3, [r3, #0]
|
|
800361a: f402 6200 and.w r2, r2, #2048 @ 0x800
|
|
800361e: 615a str r2, [r3, #20]
|
|
}
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* Handle LPM Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
|
|
8003620: 687b ldr r3, [r7, #4]
|
|
8003622: 681b ldr r3, [r3, #0]
|
|
8003624: 4618 mov r0, r3
|
|
8003626: f005 f881 bl 800872c <USB_ReadInterrupts>
|
|
800362a: 4603 mov r3, r0
|
|
800362c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8003630: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8003634: d121 bne.n 800367a <HAL_PCD_IRQHandler+0x56c>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
|
|
8003636: 687b ldr r3, [r7, #4]
|
|
8003638: 681b ldr r3, [r3, #0]
|
|
800363a: 695a ldr r2, [r3, #20]
|
|
800363c: 687b ldr r3, [r7, #4]
|
|
800363e: 681b ldr r3, [r3, #0]
|
|
8003640: f002 6200 and.w r2, r2, #134217728 @ 0x8000000
|
|
8003644: 615a str r2, [r3, #20]
|
|
|
|
if (hpcd->LPM_State == LPM_L0)
|
|
8003646: 687b ldr r3, [r7, #4]
|
|
8003648: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
|
|
800364c: 2b00 cmp r3, #0
|
|
800364e: d111 bne.n 8003674 <HAL_PCD_IRQHandler+0x566>
|
|
{
|
|
hpcd->LPM_State = LPM_L1;
|
|
8003650: 687b ldr r3, [r7, #4]
|
|
8003652: 2201 movs r2, #1
|
|
8003654: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
|
|
8003658: 687b ldr r3, [r7, #4]
|
|
800365a: 681b ldr r3, [r3, #0]
|
|
800365c: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800365e: 089b lsrs r3, r3, #2
|
|
8003660: f003 020f and.w r2, r3, #15
|
|
8003664: 687b ldr r3, [r7, #4]
|
|
8003666: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
|
|
#else
|
|
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
|
|
800366a: 2101 movs r1, #1
|
|
800366c: 6878 ldr r0, [r7, #4]
|
|
800366e: f007 fb55 bl 800ad1c <HAL_PCDEx_LPM_Callback>
|
|
8003672: e002 b.n 800367a <HAL_PCD_IRQHandler+0x56c>
|
|
else
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SuspendCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
8003674: 6878 ldr r0, [r7, #4]
|
|
8003676: f007 f965 bl 800a944 <HAL_PCD_SuspendCallback>
|
|
}
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
/* Handle Reset Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
|
|
800367a: 687b ldr r3, [r7, #4]
|
|
800367c: 681b ldr r3, [r3, #0]
|
|
800367e: 4618 mov r0, r3
|
|
8003680: f005 f854 bl 800872c <USB_ReadInterrupts>
|
|
8003684: 4603 mov r3, r0
|
|
8003686: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
800368a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
800368e: f040 80b7 bne.w 8003800 <HAL_PCD_IRQHandler+0x6f2>
|
|
{
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
|
|
8003692: 69fb ldr r3, [r7, #28]
|
|
8003694: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8003698: 685b ldr r3, [r3, #4]
|
|
800369a: 69fa ldr r2, [r7, #28]
|
|
800369c: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80036a0: f023 0301 bic.w r3, r3, #1
|
|
80036a4: 6053 str r3, [r2, #4]
|
|
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
|
|
80036a6: 687b ldr r3, [r7, #4]
|
|
80036a8: 681b ldr r3, [r3, #0]
|
|
80036aa: 2110 movs r1, #16
|
|
80036ac: 4618 mov r0, r3
|
|
80036ae: f004 f921 bl 80078f4 <USB_FlushTxFifo>
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
80036b2: 2300 movs r3, #0
|
|
80036b4: 62fb str r3, [r7, #44] @ 0x2c
|
|
80036b6: e046 b.n 8003746 <HAL_PCD_IRQHandler+0x638>
|
|
{
|
|
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
|
80036b8: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80036ba: 015a lsls r2, r3, #5
|
|
80036bc: 69fb ldr r3, [r7, #28]
|
|
80036be: 4413 add r3, r2
|
|
80036c0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80036c4: 461a mov r2, r3
|
|
80036c6: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
80036ca: 6093 str r3, [r2, #8]
|
|
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
|
80036cc: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80036ce: 015a lsls r2, r3, #5
|
|
80036d0: 69fb ldr r3, [r7, #28]
|
|
80036d2: 4413 add r3, r2
|
|
80036d4: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80036d8: 681b ldr r3, [r3, #0]
|
|
80036da: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
80036dc: 0151 lsls r1, r2, #5
|
|
80036de: 69fa ldr r2, [r7, #28]
|
|
80036e0: 440a add r2, r1
|
|
80036e2: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80036e6: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
80036ea: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
|
80036ec: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80036ee: 015a lsls r2, r3, #5
|
|
80036f0: 69fb ldr r3, [r7, #28]
|
|
80036f2: 4413 add r3, r2
|
|
80036f4: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80036f8: 461a mov r2, r3
|
|
80036fa: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
80036fe: 6093 str r3, [r2, #8]
|
|
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
|
8003700: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8003702: 015a lsls r2, r3, #5
|
|
8003704: 69fb ldr r3, [r7, #28]
|
|
8003706: 4413 add r3, r2
|
|
8003708: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800370c: 681b ldr r3, [r3, #0]
|
|
800370e: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8003710: 0151 lsls r1, r2, #5
|
|
8003712: 69fa ldr r2, [r7, #28]
|
|
8003714: 440a add r2, r1
|
|
8003716: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800371a: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
800371e: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
|
8003720: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8003722: 015a lsls r2, r3, #5
|
|
8003724: 69fb ldr r3, [r7, #28]
|
|
8003726: 4413 add r3, r2
|
|
8003728: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800372c: 681b ldr r3, [r3, #0]
|
|
800372e: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8003730: 0151 lsls r1, r2, #5
|
|
8003732: 69fa ldr r2, [r7, #28]
|
|
8003734: 440a add r2, r1
|
|
8003736: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800373a: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
800373e: 6013 str r3, [r2, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8003740: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8003742: 3301 adds r3, #1
|
|
8003744: 62fb str r3, [r7, #44] @ 0x2c
|
|
8003746: 687b ldr r3, [r7, #4]
|
|
8003748: 791b ldrb r3, [r3, #4]
|
|
800374a: 461a mov r2, r3
|
|
800374c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800374e: 4293 cmp r3, r2
|
|
8003750: d3b2 bcc.n 80036b8 <HAL_PCD_IRQHandler+0x5aa>
|
|
}
|
|
USBx_DEVICE->DAINTMSK |= 0x10001U;
|
|
8003752: 69fb ldr r3, [r7, #28]
|
|
8003754: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8003758: 69db ldr r3, [r3, #28]
|
|
800375a: 69fa ldr r2, [r7, #28]
|
|
800375c: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8003760: f043 1301 orr.w r3, r3, #65537 @ 0x10001
|
|
8003764: 61d3 str r3, [r2, #28]
|
|
|
|
if (hpcd->Init.use_dedicated_ep1 != 0U)
|
|
8003766: 687b ldr r3, [r7, #4]
|
|
8003768: 7bdb ldrb r3, [r3, #15]
|
|
800376a: 2b00 cmp r3, #0
|
|
800376c: d016 beq.n 800379c <HAL_PCD_IRQHandler+0x68e>
|
|
{
|
|
USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
|
|
800376e: 69fb ldr r3, [r7, #28]
|
|
8003770: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8003774: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003778: 69fa ldr r2, [r7, #28]
|
|
800377a: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
800377e: f043 030b orr.w r3, r3, #11
|
|
8003782: f8c2 3084 str.w r3, [r2, #132] @ 0x84
|
|
USB_OTG_DOEPMSK_XFRCM |
|
|
USB_OTG_DOEPMSK_EPDM;
|
|
|
|
USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
|
|
8003786: 69fb ldr r3, [r7, #28]
|
|
8003788: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800378c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800378e: 69fa ldr r2, [r7, #28]
|
|
8003790: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8003794: f043 030b orr.w r3, r3, #11
|
|
8003798: 6453 str r3, [r2, #68] @ 0x44
|
|
800379a: e015 b.n 80037c8 <HAL_PCD_IRQHandler+0x6ba>
|
|
USB_OTG_DIEPMSK_XFRCM |
|
|
USB_OTG_DIEPMSK_EPDM;
|
|
}
|
|
else
|
|
{
|
|
USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
|
|
800379c: 69fb ldr r3, [r7, #28]
|
|
800379e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80037a2: 695b ldr r3, [r3, #20]
|
|
80037a4: 69fa ldr r2, [r7, #28]
|
|
80037a6: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80037aa: f443 5300 orr.w r3, r3, #8192 @ 0x2000
|
|
80037ae: f043 032b orr.w r3, r3, #43 @ 0x2b
|
|
80037b2: 6153 str r3, [r2, #20]
|
|
USB_OTG_DOEPMSK_XFRCM |
|
|
USB_OTG_DOEPMSK_EPDM |
|
|
USB_OTG_DOEPMSK_OTEPSPRM |
|
|
USB_OTG_DOEPMSK_NAKM;
|
|
|
|
USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
|
|
80037b4: 69fb ldr r3, [r7, #28]
|
|
80037b6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80037ba: 691b ldr r3, [r3, #16]
|
|
80037bc: 69fa ldr r2, [r7, #28]
|
|
80037be: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80037c2: f043 030b orr.w r3, r3, #11
|
|
80037c6: 6113 str r3, [r2, #16]
|
|
USB_OTG_DIEPMSK_XFRCM |
|
|
USB_OTG_DIEPMSK_EPDM;
|
|
}
|
|
|
|
/* Set Default Address to 0 */
|
|
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
|
|
80037c8: 69fb ldr r3, [r7, #28]
|
|
80037ca: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80037ce: 681b ldr r3, [r3, #0]
|
|
80037d0: 69fa ldr r2, [r7, #28]
|
|
80037d2: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80037d6: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
|
|
80037da: 6013 str r3, [r2, #0]
|
|
|
|
/* setup EP0 to receive SETUP packets */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
|
|
80037dc: 687b ldr r3, [r7, #4]
|
|
80037de: 6818 ldr r0, [r3, #0]
|
|
80037e0: 687b ldr r3, [r7, #4]
|
|
80037e2: 7999 ldrb r1, [r3, #6]
|
|
(uint8_t *)hpcd->Setup);
|
|
80037e4: 687b ldr r3, [r7, #4]
|
|
80037e6: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
|
|
80037ea: 461a mov r2, r3
|
|
80037ec: f005 f862 bl 80088b4 <USB_EP0_OutStart>
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
|
|
80037f0: 687b ldr r3, [r7, #4]
|
|
80037f2: 681b ldr r3, [r3, #0]
|
|
80037f4: 695a ldr r2, [r3, #20]
|
|
80037f6: 687b ldr r3, [r7, #4]
|
|
80037f8: 681b ldr r3, [r3, #0]
|
|
80037fa: f402 5280 and.w r2, r2, #4096 @ 0x1000
|
|
80037fe: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Enumeration done Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
|
|
8003800: 687b ldr r3, [r7, #4]
|
|
8003802: 681b ldr r3, [r3, #0]
|
|
8003804: 4618 mov r0, r3
|
|
8003806: f004 ff91 bl 800872c <USB_ReadInterrupts>
|
|
800380a: 4603 mov r3, r0
|
|
800380c: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
8003810: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
8003814: d123 bne.n 800385e <HAL_PCD_IRQHandler+0x750>
|
|
{
|
|
(void)USB_ActivateSetup(hpcd->Instance);
|
|
8003816: 687b ldr r3, [r7, #4]
|
|
8003818: 681b ldr r3, [r3, #0]
|
|
800381a: 4618 mov r0, r3
|
|
800381c: f005 f827 bl 800886e <USB_ActivateSetup>
|
|
hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
|
|
8003820: 687b ldr r3, [r7, #4]
|
|
8003822: 681b ldr r3, [r3, #0]
|
|
8003824: 4618 mov r0, r3
|
|
8003826: f004 f8de bl 80079e6 <USB_GetDevSpeed>
|
|
800382a: 4603 mov r3, r0
|
|
800382c: 461a mov r2, r3
|
|
800382e: 687b ldr r3, [r7, #4]
|
|
8003830: 71da strb r2, [r3, #7]
|
|
|
|
/* Set USB Turnaround time */
|
|
(void)USB_SetTurnaroundTime(hpcd->Instance,
|
|
8003832: 687b ldr r3, [r7, #4]
|
|
8003834: 681c ldr r4, [r3, #0]
|
|
8003836: f000 fe8b bl 8004550 <HAL_RCC_GetHCLKFreq>
|
|
800383a: 4601 mov r1, r0
|
|
HAL_RCC_GetHCLKFreq(),
|
|
(uint8_t)hpcd->Init.speed);
|
|
800383c: 687b ldr r3, [r7, #4]
|
|
800383e: 79db ldrb r3, [r3, #7]
|
|
(void)USB_SetTurnaroundTime(hpcd->Instance,
|
|
8003840: 461a mov r2, r3
|
|
8003842: 4620 mov r0, r4
|
|
8003844: f003 fde8 bl 8007418 <USB_SetTurnaroundTime>
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResetCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResetCallback(hpcd);
|
|
8003848: 6878 ldr r0, [r7, #4]
|
|
800384a: f007 f852 bl 800a8f2 <HAL_PCD_ResetCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
|
|
800384e: 687b ldr r3, [r7, #4]
|
|
8003850: 681b ldr r3, [r3, #0]
|
|
8003852: 695a ldr r2, [r3, #20]
|
|
8003854: 687b ldr r3, [r7, #4]
|
|
8003856: 681b ldr r3, [r3, #0]
|
|
8003858: f402 5200 and.w r2, r2, #8192 @ 0x2000
|
|
800385c: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle SOF Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
|
|
800385e: 687b ldr r3, [r7, #4]
|
|
8003860: 681b ldr r3, [r3, #0]
|
|
8003862: 4618 mov r0, r3
|
|
8003864: f004 ff62 bl 800872c <USB_ReadInterrupts>
|
|
8003868: 4603 mov r3, r0
|
|
800386a: f003 0308 and.w r3, r3, #8
|
|
800386e: 2b08 cmp r3, #8
|
|
8003870: d10a bne.n 8003888 <HAL_PCD_IRQHandler+0x77a>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SOFCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SOFCallback(hpcd);
|
|
8003872: 6878 ldr r0, [r7, #4]
|
|
8003874: f007 f82f bl 800a8d6 <HAL_PCD_SOFCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
|
|
8003878: 687b ldr r3, [r7, #4]
|
|
800387a: 681b ldr r3, [r3, #0]
|
|
800387c: 695a ldr r2, [r3, #20]
|
|
800387e: 687b ldr r3, [r7, #4]
|
|
8003880: 681b ldr r3, [r3, #0]
|
|
8003882: f002 0208 and.w r2, r2, #8
|
|
8003886: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Global OUT NAK effective Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF))
|
|
8003888: 687b ldr r3, [r7, #4]
|
|
800388a: 681b ldr r3, [r3, #0]
|
|
800388c: 4618 mov r0, r3
|
|
800388e: f004 ff4d bl 800872c <USB_ReadInterrupts>
|
|
8003892: 4603 mov r3, r0
|
|
8003894: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8003898: 2b80 cmp r3, #128 @ 0x80
|
|
800389a: d123 bne.n 80038e4 <HAL_PCD_IRQHandler+0x7d6>
|
|
{
|
|
USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM;
|
|
800389c: 6a3b ldr r3, [r7, #32]
|
|
800389e: 699b ldr r3, [r3, #24]
|
|
80038a0: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
80038a4: 6a3b ldr r3, [r7, #32]
|
|
80038a6: 619a str r2, [r3, #24]
|
|
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
80038a8: 2301 movs r3, #1
|
|
80038aa: 627b str r3, [r7, #36] @ 0x24
|
|
80038ac: e014 b.n 80038d8 <HAL_PCD_IRQHandler+0x7ca>
|
|
{
|
|
if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U)
|
|
80038ae: 6879 ldr r1, [r7, #4]
|
|
80038b0: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80038b2: 4613 mov r3, r2
|
|
80038b4: 00db lsls r3, r3, #3
|
|
80038b6: 4413 add r3, r2
|
|
80038b8: 009b lsls r3, r3, #2
|
|
80038ba: 440b add r3, r1
|
|
80038bc: f203 2357 addw r3, r3, #599 @ 0x257
|
|
80038c0: 781b ldrb r3, [r3, #0]
|
|
80038c2: 2b01 cmp r3, #1
|
|
80038c4: d105 bne.n 80038d2 <HAL_PCD_IRQHandler+0x7c4>
|
|
{
|
|
/* Abort current transaction and disable the EP */
|
|
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum);
|
|
80038c6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80038c8: b2db uxtb r3, r3
|
|
80038ca: 4619 mov r1, r3
|
|
80038cc: 6878 ldr r0, [r7, #4]
|
|
80038ce: f000 faf2 bl 8003eb6 <HAL_PCD_EP_Abort>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
80038d2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80038d4: 3301 adds r3, #1
|
|
80038d6: 627b str r3, [r7, #36] @ 0x24
|
|
80038d8: 687b ldr r3, [r7, #4]
|
|
80038da: 791b ldrb r3, [r3, #4]
|
|
80038dc: 461a mov r2, r3
|
|
80038de: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80038e0: 4293 cmp r3, r2
|
|
80038e2: d3e4 bcc.n 80038ae <HAL_PCD_IRQHandler+0x7a0>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Handle Incomplete ISO IN Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
|
|
80038e4: 687b ldr r3, [r7, #4]
|
|
80038e6: 681b ldr r3, [r3, #0]
|
|
80038e8: 4618 mov r0, r3
|
|
80038ea: f004 ff1f bl 800872c <USB_ReadInterrupts>
|
|
80038ee: 4603 mov r3, r0
|
|
80038f0: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
80038f4: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
80038f8: d13c bne.n 8003974 <HAL_PCD_IRQHandler+0x866>
|
|
{
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
80038fa: 2301 movs r3, #1
|
|
80038fc: 627b str r3, [r7, #36] @ 0x24
|
|
80038fe: e02b b.n 8003958 <HAL_PCD_IRQHandler+0x84a>
|
|
{
|
|
RegVal = USBx_INEP(epnum)->DIEPCTL;
|
|
8003900: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003902: 015a lsls r2, r3, #5
|
|
8003904: 69fb ldr r3, [r7, #28]
|
|
8003906: 4413 add r3, r2
|
|
8003908: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800390c: 681b ldr r3, [r3, #0]
|
|
800390e: 61bb str r3, [r7, #24]
|
|
|
|
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
8003910: 6879 ldr r1, [r7, #4]
|
|
8003912: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8003914: 4613 mov r3, r2
|
|
8003916: 00db lsls r3, r3, #3
|
|
8003918: 4413 add r3, r2
|
|
800391a: 009b lsls r3, r3, #2
|
|
800391c: 440b add r3, r1
|
|
800391e: 3318 adds r3, #24
|
|
8003920: 781b ldrb r3, [r3, #0]
|
|
8003922: 2b01 cmp r3, #1
|
|
8003924: d115 bne.n 8003952 <HAL_PCD_IRQHandler+0x844>
|
|
((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA))
|
|
8003926: 69bb ldr r3, [r7, #24]
|
|
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
8003928: 2b00 cmp r3, #0
|
|
800392a: da12 bge.n 8003952 <HAL_PCD_IRQHandler+0x844>
|
|
{
|
|
hpcd->IN_ep[epnum].is_iso_incomplete = 1U;
|
|
800392c: 6879 ldr r1, [r7, #4]
|
|
800392e: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8003930: 4613 mov r3, r2
|
|
8003932: 00db lsls r3, r3, #3
|
|
8003934: 4413 add r3, r2
|
|
8003936: 009b lsls r3, r3, #2
|
|
8003938: 440b add r3, r1
|
|
800393a: 3317 adds r3, #23
|
|
800393c: 2201 movs r2, #1
|
|
800393e: 701a strb r2, [r3, #0]
|
|
|
|
/* Abort current transaction and disable the EP */
|
|
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U));
|
|
8003940: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003942: b2db uxtb r3, r3
|
|
8003944: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8003948: b2db uxtb r3, r3
|
|
800394a: 4619 mov r1, r3
|
|
800394c: 6878 ldr r0, [r7, #4]
|
|
800394e: f000 fab2 bl 8003eb6 <HAL_PCD_EP_Abort>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
8003952: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003954: 3301 adds r3, #1
|
|
8003956: 627b str r3, [r7, #36] @ 0x24
|
|
8003958: 687b ldr r3, [r7, #4]
|
|
800395a: 791b ldrb r3, [r3, #4]
|
|
800395c: 461a mov r2, r3
|
|
800395e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003960: 4293 cmp r3, r2
|
|
8003962: d3cd bcc.n 8003900 <HAL_PCD_IRQHandler+0x7f2>
|
|
}
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
|
|
8003964: 687b ldr r3, [r7, #4]
|
|
8003966: 681b ldr r3, [r3, #0]
|
|
8003968: 695a ldr r2, [r3, #20]
|
|
800396a: 687b ldr r3, [r7, #4]
|
|
800396c: 681b ldr r3, [r3, #0]
|
|
800396e: f402 1280 and.w r2, r2, #1048576 @ 0x100000
|
|
8003972: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Incomplete ISO OUT Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
|
|
8003974: 687b ldr r3, [r7, #4]
|
|
8003976: 681b ldr r3, [r3, #0]
|
|
8003978: 4618 mov r0, r3
|
|
800397a: f004 fed7 bl 800872c <USB_ReadInterrupts>
|
|
800397e: 4603 mov r3, r0
|
|
8003980: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8003984: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
|
|
8003988: d156 bne.n 8003a38 <HAL_PCD_IRQHandler+0x92a>
|
|
{
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
800398a: 2301 movs r3, #1
|
|
800398c: 627b str r3, [r7, #36] @ 0x24
|
|
800398e: e045 b.n 8003a1c <HAL_PCD_IRQHandler+0x90e>
|
|
{
|
|
RegVal = USBx_OUTEP(epnum)->DOEPCTL;
|
|
8003990: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003992: 015a lsls r2, r3, #5
|
|
8003994: 69fb ldr r3, [r7, #28]
|
|
8003996: 4413 add r3, r2
|
|
8003998: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800399c: 681b ldr r3, [r3, #0]
|
|
800399e: 61bb str r3, [r7, #24]
|
|
|
|
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
80039a0: 6879 ldr r1, [r7, #4]
|
|
80039a2: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80039a4: 4613 mov r3, r2
|
|
80039a6: 00db lsls r3, r3, #3
|
|
80039a8: 4413 add r3, r2
|
|
80039aa: 009b lsls r3, r3, #2
|
|
80039ac: 440b add r3, r1
|
|
80039ae: f503 7316 add.w r3, r3, #600 @ 0x258
|
|
80039b2: 781b ldrb r3, [r3, #0]
|
|
80039b4: 2b01 cmp r3, #1
|
|
80039b6: d12e bne.n 8003a16 <HAL_PCD_IRQHandler+0x908>
|
|
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
|
|
80039b8: 69bb ldr r3, [r7, #24]
|
|
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
80039ba: 2b00 cmp r3, #0
|
|
80039bc: da2b bge.n 8003a16 <HAL_PCD_IRQHandler+0x908>
|
|
(((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U)))
|
|
80039be: 69bb ldr r3, [r7, #24]
|
|
80039c0: 0c1a lsrs r2, r3, #16
|
|
80039c2: 687b ldr r3, [r7, #4]
|
|
80039c4: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4
|
|
80039c8: 4053 eors r3, r2
|
|
80039ca: f003 0301 and.w r3, r3, #1
|
|
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
|
|
80039ce: 2b00 cmp r3, #0
|
|
80039d0: d121 bne.n 8003a16 <HAL_PCD_IRQHandler+0x908>
|
|
{
|
|
hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
|
|
80039d2: 6879 ldr r1, [r7, #4]
|
|
80039d4: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80039d6: 4613 mov r3, r2
|
|
80039d8: 00db lsls r3, r3, #3
|
|
80039da: 4413 add r3, r2
|
|
80039dc: 009b lsls r3, r3, #2
|
|
80039de: 440b add r3, r1
|
|
80039e0: f203 2357 addw r3, r3, #599 @ 0x257
|
|
80039e4: 2201 movs r2, #1
|
|
80039e6: 701a strb r2, [r3, #0]
|
|
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM;
|
|
80039e8: 6a3b ldr r3, [r7, #32]
|
|
80039ea: 699b ldr r3, [r3, #24]
|
|
80039ec: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
80039f0: 6a3b ldr r3, [r7, #32]
|
|
80039f2: 619a str r2, [r3, #24]
|
|
|
|
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U)
|
|
80039f4: 6a3b ldr r3, [r7, #32]
|
|
80039f6: 695b ldr r3, [r3, #20]
|
|
80039f8: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80039fc: 2b00 cmp r3, #0
|
|
80039fe: d10a bne.n 8003a16 <HAL_PCD_IRQHandler+0x908>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
|
|
8003a00: 69fb ldr r3, [r7, #28]
|
|
8003a02: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8003a06: 685b ldr r3, [r3, #4]
|
|
8003a08: 69fa ldr r2, [r7, #28]
|
|
8003a0a: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8003a0e: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8003a12: 6053 str r3, [r2, #4]
|
|
break;
|
|
8003a14: e008 b.n 8003a28 <HAL_PCD_IRQHandler+0x91a>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
8003a16: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003a18: 3301 adds r3, #1
|
|
8003a1a: 627b str r3, [r7, #36] @ 0x24
|
|
8003a1c: 687b ldr r3, [r7, #4]
|
|
8003a1e: 791b ldrb r3, [r3, #4]
|
|
8003a20: 461a mov r2, r3
|
|
8003a22: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003a24: 4293 cmp r3, r2
|
|
8003a26: d3b3 bcc.n 8003990 <HAL_PCD_IRQHandler+0x882>
|
|
}
|
|
}
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
|
|
8003a28: 687b ldr r3, [r7, #4]
|
|
8003a2a: 681b ldr r3, [r3, #0]
|
|
8003a2c: 695a ldr r2, [r3, #20]
|
|
8003a2e: 687b ldr r3, [r7, #4]
|
|
8003a30: 681b ldr r3, [r3, #0]
|
|
8003a32: f402 1200 and.w r2, r2, #2097152 @ 0x200000
|
|
8003a36: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Connection event Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
|
|
8003a38: 687b ldr r3, [r7, #4]
|
|
8003a3a: 681b ldr r3, [r3, #0]
|
|
8003a3c: 4618 mov r0, r3
|
|
8003a3e: f004 fe75 bl 800872c <USB_ReadInterrupts>
|
|
8003a42: 4603 mov r3, r0
|
|
8003a44: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
|
|
8003a48: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8003a4c: d10a bne.n 8003a64 <HAL_PCD_IRQHandler+0x956>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ConnectCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ConnectCallback(hpcd);
|
|
8003a4e: 6878 ldr r0, [r7, #4]
|
|
8003a50: f006 ffd0 bl 800a9f4 <HAL_PCD_ConnectCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
|
|
8003a54: 687b ldr r3, [r7, #4]
|
|
8003a56: 681b ldr r3, [r3, #0]
|
|
8003a58: 695a ldr r2, [r3, #20]
|
|
8003a5a: 687b ldr r3, [r7, #4]
|
|
8003a5c: 681b ldr r3, [r3, #0]
|
|
8003a5e: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000
|
|
8003a62: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Disconnection event Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
|
|
8003a64: 687b ldr r3, [r7, #4]
|
|
8003a66: 681b ldr r3, [r3, #0]
|
|
8003a68: 4618 mov r0, r3
|
|
8003a6a: f004 fe5f bl 800872c <USB_ReadInterrupts>
|
|
8003a6e: 4603 mov r3, r0
|
|
8003a70: f003 0304 and.w r3, r3, #4
|
|
8003a74: 2b04 cmp r3, #4
|
|
8003a76: d115 bne.n 8003aa4 <HAL_PCD_IRQHandler+0x996>
|
|
{
|
|
RegVal = hpcd->Instance->GOTGINT;
|
|
8003a78: 687b ldr r3, [r7, #4]
|
|
8003a7a: 681b ldr r3, [r3, #0]
|
|
8003a7c: 685b ldr r3, [r3, #4]
|
|
8003a7e: 61bb str r3, [r7, #24]
|
|
|
|
if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
|
|
8003a80: 69bb ldr r3, [r7, #24]
|
|
8003a82: f003 0304 and.w r3, r3, #4
|
|
8003a86: 2b00 cmp r3, #0
|
|
8003a88: d002 beq.n 8003a90 <HAL_PCD_IRQHandler+0x982>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DisconnectCallback(hpcd);
|
|
#else
|
|
HAL_PCD_DisconnectCallback(hpcd);
|
|
8003a8a: 6878 ldr r0, [r7, #4]
|
|
8003a8c: f006 ffc0 bl 800aa10 <HAL_PCD_DisconnectCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
hpcd->Instance->GOTGINT |= RegVal;
|
|
8003a90: 687b ldr r3, [r7, #4]
|
|
8003a92: 681b ldr r3, [r3, #0]
|
|
8003a94: 6859 ldr r1, [r3, #4]
|
|
8003a96: 687b ldr r3, [r7, #4]
|
|
8003a98: 681b ldr r3, [r3, #0]
|
|
8003a9a: 69ba ldr r2, [r7, #24]
|
|
8003a9c: 430a orrs r2, r1
|
|
8003a9e: 605a str r2, [r3, #4]
|
|
8003aa0: e000 b.n 8003aa4 <HAL_PCD_IRQHandler+0x996>
|
|
return;
|
|
8003aa2: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
8003aa4: 3734 adds r7, #52 @ 0x34
|
|
8003aa6: 46bd mov sp, r7
|
|
8003aa8: bd90 pop {r4, r7, pc}
|
|
|
|
08003aaa <HAL_PCD_SetAddress>:
|
|
* @param hpcd PCD handle
|
|
* @param address new device address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
|
|
{
|
|
8003aaa: b580 push {r7, lr}
|
|
8003aac: b082 sub sp, #8
|
|
8003aae: af00 add r7, sp, #0
|
|
8003ab0: 6078 str r0, [r7, #4]
|
|
8003ab2: 460b mov r3, r1
|
|
8003ab4: 70fb strb r3, [r7, #3]
|
|
__HAL_LOCK(hpcd);
|
|
8003ab6: 687b ldr r3, [r7, #4]
|
|
8003ab8: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8003abc: 2b01 cmp r3, #1
|
|
8003abe: d101 bne.n 8003ac4 <HAL_PCD_SetAddress+0x1a>
|
|
8003ac0: 2302 movs r3, #2
|
|
8003ac2: e012 b.n 8003aea <HAL_PCD_SetAddress+0x40>
|
|
8003ac4: 687b ldr r3, [r7, #4]
|
|
8003ac6: 2201 movs r2, #1
|
|
8003ac8: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
hpcd->USB_Address = address;
|
|
8003acc: 687b ldr r3, [r7, #4]
|
|
8003ace: 78fa ldrb r2, [r7, #3]
|
|
8003ad0: 745a strb r2, [r3, #17]
|
|
(void)USB_SetDevAddress(hpcd->Instance, address);
|
|
8003ad2: 687b ldr r3, [r7, #4]
|
|
8003ad4: 681b ldr r3, [r3, #0]
|
|
8003ad6: 78fa ldrb r2, [r7, #3]
|
|
8003ad8: 4611 mov r1, r2
|
|
8003ada: 4618 mov r0, r3
|
|
8003adc: f004 fdbe bl 800865c <USB_SetDevAddress>
|
|
__HAL_UNLOCK(hpcd);
|
|
8003ae0: 687b ldr r3, [r7, #4]
|
|
8003ae2: 2200 movs r2, #0
|
|
8003ae4: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8003ae8: 2300 movs r3, #0
|
|
}
|
|
8003aea: 4618 mov r0, r3
|
|
8003aec: 3708 adds r7, #8
|
|
8003aee: 46bd mov sp, r7
|
|
8003af0: bd80 pop {r7, pc}
|
|
|
|
08003af2 <HAL_PCD_EP_Open>:
|
|
* @param ep_type endpoint type
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
|
uint16_t ep_mps, uint8_t ep_type)
|
|
{
|
|
8003af2: b580 push {r7, lr}
|
|
8003af4: b084 sub sp, #16
|
|
8003af6: af00 add r7, sp, #0
|
|
8003af8: 6078 str r0, [r7, #4]
|
|
8003afa: 4608 mov r0, r1
|
|
8003afc: 4611 mov r1, r2
|
|
8003afe: 461a mov r2, r3
|
|
8003b00: 4603 mov r3, r0
|
|
8003b02: 70fb strb r3, [r7, #3]
|
|
8003b04: 460b mov r3, r1
|
|
8003b06: 803b strh r3, [r7, #0]
|
|
8003b08: 4613 mov r3, r2
|
|
8003b0a: 70bb strb r3, [r7, #2]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8003b0c: 2300 movs r3, #0
|
|
8003b0e: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8003b10: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8003b14: 2b00 cmp r3, #0
|
|
8003b16: da0f bge.n 8003b38 <HAL_PCD_EP_Open+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8003b18: 78fb ldrb r3, [r7, #3]
|
|
8003b1a: f003 020f and.w r2, r3, #15
|
|
8003b1e: 4613 mov r3, r2
|
|
8003b20: 00db lsls r3, r3, #3
|
|
8003b22: 4413 add r3, r2
|
|
8003b24: 009b lsls r3, r3, #2
|
|
8003b26: 3310 adds r3, #16
|
|
8003b28: 687a ldr r2, [r7, #4]
|
|
8003b2a: 4413 add r3, r2
|
|
8003b2c: 3304 adds r3, #4
|
|
8003b2e: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8003b30: 68fb ldr r3, [r7, #12]
|
|
8003b32: 2201 movs r2, #1
|
|
8003b34: 705a strb r2, [r3, #1]
|
|
8003b36: e00f b.n 8003b58 <HAL_PCD_EP_Open+0x66>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8003b38: 78fb ldrb r3, [r7, #3]
|
|
8003b3a: f003 020f and.w r2, r3, #15
|
|
8003b3e: 4613 mov r3, r2
|
|
8003b40: 00db lsls r3, r3, #3
|
|
8003b42: 4413 add r3, r2
|
|
8003b44: 009b lsls r3, r3, #2
|
|
8003b46: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003b4a: 687a ldr r2, [r7, #4]
|
|
8003b4c: 4413 add r3, r2
|
|
8003b4e: 3304 adds r3, #4
|
|
8003b50: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8003b52: 68fb ldr r3, [r7, #12]
|
|
8003b54: 2200 movs r2, #0
|
|
8003b56: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8003b58: 78fb ldrb r3, [r7, #3]
|
|
8003b5a: f003 030f and.w r3, r3, #15
|
|
8003b5e: b2da uxtb r2, r3
|
|
8003b60: 68fb ldr r3, [r7, #12]
|
|
8003b62: 701a strb r2, [r3, #0]
|
|
ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
|
|
8003b64: 883b ldrh r3, [r7, #0]
|
|
8003b66: f3c3 020a ubfx r2, r3, #0, #11
|
|
8003b6a: 68fb ldr r3, [r7, #12]
|
|
8003b6c: 609a str r2, [r3, #8]
|
|
ep->type = ep_type;
|
|
8003b6e: 68fb ldr r3, [r7, #12]
|
|
8003b70: 78ba ldrb r2, [r7, #2]
|
|
8003b72: 711a strb r2, [r3, #4]
|
|
|
|
if (ep->is_in != 0U)
|
|
8003b74: 68fb ldr r3, [r7, #12]
|
|
8003b76: 785b ldrb r3, [r3, #1]
|
|
8003b78: 2b00 cmp r3, #0
|
|
8003b7a: d004 beq.n 8003b86 <HAL_PCD_EP_Open+0x94>
|
|
{
|
|
/* Assign a Tx FIFO */
|
|
ep->tx_fifo_num = ep->num;
|
|
8003b7c: 68fb ldr r3, [r7, #12]
|
|
8003b7e: 781b ldrb r3, [r3, #0]
|
|
8003b80: 461a mov r2, r3
|
|
8003b82: 68fb ldr r3, [r7, #12]
|
|
8003b84: 835a strh r2, [r3, #26]
|
|
}
|
|
|
|
/* Set initial data PID. */
|
|
if (ep_type == EP_TYPE_BULK)
|
|
8003b86: 78bb ldrb r3, [r7, #2]
|
|
8003b88: 2b02 cmp r3, #2
|
|
8003b8a: d102 bne.n 8003b92 <HAL_PCD_EP_Open+0xa0>
|
|
{
|
|
ep->data_pid_start = 0U;
|
|
8003b8c: 68fb ldr r3, [r7, #12]
|
|
8003b8e: 2200 movs r2, #0
|
|
8003b90: 715a strb r2, [r3, #5]
|
|
}
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8003b92: 687b ldr r3, [r7, #4]
|
|
8003b94: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8003b98: 2b01 cmp r3, #1
|
|
8003b9a: d101 bne.n 8003ba0 <HAL_PCD_EP_Open+0xae>
|
|
8003b9c: 2302 movs r3, #2
|
|
8003b9e: e00e b.n 8003bbe <HAL_PCD_EP_Open+0xcc>
|
|
8003ba0: 687b ldr r3, [r7, #4]
|
|
8003ba2: 2201 movs r2, #1
|
|
8003ba4: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
|
|
8003ba8: 687b ldr r3, [r7, #4]
|
|
8003baa: 681b ldr r3, [r3, #0]
|
|
8003bac: 68f9 ldr r1, [r7, #12]
|
|
8003bae: 4618 mov r0, r3
|
|
8003bb0: f003 ff3e bl 8007a30 <USB_ActivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
8003bb4: 687b ldr r3, [r7, #4]
|
|
8003bb6: 2200 movs r2, #0
|
|
8003bb8: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return ret;
|
|
8003bbc: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
8003bbe: 4618 mov r0, r3
|
|
8003bc0: 3710 adds r7, #16
|
|
8003bc2: 46bd mov sp, r7
|
|
8003bc4: bd80 pop {r7, pc}
|
|
|
|
08003bc6 <HAL_PCD_EP_Close>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8003bc6: b580 push {r7, lr}
|
|
8003bc8: b084 sub sp, #16
|
|
8003bca: af00 add r7, sp, #0
|
|
8003bcc: 6078 str r0, [r7, #4]
|
|
8003bce: 460b mov r3, r1
|
|
8003bd0: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8003bd2: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8003bd6: 2b00 cmp r3, #0
|
|
8003bd8: da0f bge.n 8003bfa <HAL_PCD_EP_Close+0x34>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8003bda: 78fb ldrb r3, [r7, #3]
|
|
8003bdc: f003 020f and.w r2, r3, #15
|
|
8003be0: 4613 mov r3, r2
|
|
8003be2: 00db lsls r3, r3, #3
|
|
8003be4: 4413 add r3, r2
|
|
8003be6: 009b lsls r3, r3, #2
|
|
8003be8: 3310 adds r3, #16
|
|
8003bea: 687a ldr r2, [r7, #4]
|
|
8003bec: 4413 add r3, r2
|
|
8003bee: 3304 adds r3, #4
|
|
8003bf0: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8003bf2: 68fb ldr r3, [r7, #12]
|
|
8003bf4: 2201 movs r2, #1
|
|
8003bf6: 705a strb r2, [r3, #1]
|
|
8003bf8: e00f b.n 8003c1a <HAL_PCD_EP_Close+0x54>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8003bfa: 78fb ldrb r3, [r7, #3]
|
|
8003bfc: f003 020f and.w r2, r3, #15
|
|
8003c00: 4613 mov r3, r2
|
|
8003c02: 00db lsls r3, r3, #3
|
|
8003c04: 4413 add r3, r2
|
|
8003c06: 009b lsls r3, r3, #2
|
|
8003c08: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003c0c: 687a ldr r2, [r7, #4]
|
|
8003c0e: 4413 add r3, r2
|
|
8003c10: 3304 adds r3, #4
|
|
8003c12: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8003c14: 68fb ldr r3, [r7, #12]
|
|
8003c16: 2200 movs r2, #0
|
|
8003c18: 705a strb r2, [r3, #1]
|
|
}
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8003c1a: 78fb ldrb r3, [r7, #3]
|
|
8003c1c: f003 030f and.w r3, r3, #15
|
|
8003c20: b2da uxtb r2, r3
|
|
8003c22: 68fb ldr r3, [r7, #12]
|
|
8003c24: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8003c26: 687b ldr r3, [r7, #4]
|
|
8003c28: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8003c2c: 2b01 cmp r3, #1
|
|
8003c2e: d101 bne.n 8003c34 <HAL_PCD_EP_Close+0x6e>
|
|
8003c30: 2302 movs r3, #2
|
|
8003c32: e00e b.n 8003c52 <HAL_PCD_EP_Close+0x8c>
|
|
8003c34: 687b ldr r3, [r7, #4]
|
|
8003c36: 2201 movs r2, #1
|
|
8003c38: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
|
|
8003c3c: 687b ldr r3, [r7, #4]
|
|
8003c3e: 681b ldr r3, [r3, #0]
|
|
8003c40: 68f9 ldr r1, [r7, #12]
|
|
8003c42: 4618 mov r0, r3
|
|
8003c44: f003 ff7c bl 8007b40 <USB_DeactivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
8003c48: 687b ldr r3, [r7, #4]
|
|
8003c4a: 2200 movs r2, #0
|
|
8003c4c: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
return HAL_OK;
|
|
8003c50: 2300 movs r3, #0
|
|
}
|
|
8003c52: 4618 mov r0, r3
|
|
8003c54: 3710 adds r7, #16
|
|
8003c56: 46bd mov sp, r7
|
|
8003c58: bd80 pop {r7, pc}
|
|
|
|
08003c5a <HAL_PCD_EP_Receive>:
|
|
* @param pBuf pointer to the reception buffer
|
|
* @param len amount of data to be received
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
8003c5a: b580 push {r7, lr}
|
|
8003c5c: b086 sub sp, #24
|
|
8003c5e: af00 add r7, sp, #0
|
|
8003c60: 60f8 str r0, [r7, #12]
|
|
8003c62: 607a str r2, [r7, #4]
|
|
8003c64: 603b str r3, [r7, #0]
|
|
8003c66: 460b mov r3, r1
|
|
8003c68: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8003c6a: 7afb ldrb r3, [r7, #11]
|
|
8003c6c: f003 020f and.w r2, r3, #15
|
|
8003c70: 4613 mov r3, r2
|
|
8003c72: 00db lsls r3, r3, #3
|
|
8003c74: 4413 add r3, r2
|
|
8003c76: 009b lsls r3, r3, #2
|
|
8003c78: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003c7c: 68fa ldr r2, [r7, #12]
|
|
8003c7e: 4413 add r3, r2
|
|
8003c80: 3304 adds r3, #4
|
|
8003c82: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
8003c84: 697b ldr r3, [r7, #20]
|
|
8003c86: 687a ldr r2, [r7, #4]
|
|
8003c88: 60da str r2, [r3, #12]
|
|
ep->xfer_len = len;
|
|
8003c8a: 697b ldr r3, [r7, #20]
|
|
8003c8c: 683a ldr r2, [r7, #0]
|
|
8003c8e: 611a str r2, [r3, #16]
|
|
ep->xfer_count = 0U;
|
|
8003c90: 697b ldr r3, [r7, #20]
|
|
8003c92: 2200 movs r2, #0
|
|
8003c94: 615a str r2, [r3, #20]
|
|
ep->is_in = 0U;
|
|
8003c96: 697b ldr r3, [r7, #20]
|
|
8003c98: 2200 movs r2, #0
|
|
8003c9a: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8003c9c: 7afb ldrb r3, [r7, #11]
|
|
8003c9e: f003 030f and.w r3, r3, #15
|
|
8003ca2: b2da uxtb r2, r3
|
|
8003ca4: 697b ldr r3, [r7, #20]
|
|
8003ca6: 701a strb r2, [r3, #0]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8003ca8: 68fb ldr r3, [r7, #12]
|
|
8003caa: 799b ldrb r3, [r3, #6]
|
|
8003cac: 2b01 cmp r3, #1
|
|
8003cae: d102 bne.n 8003cb6 <HAL_PCD_EP_Receive+0x5c>
|
|
{
|
|
ep->dma_addr = (uint32_t)pBuf;
|
|
8003cb0: 687a ldr r2, [r7, #4]
|
|
8003cb2: 697b ldr r3, [r7, #20]
|
|
8003cb4: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
|
|
8003cb6: 68fb ldr r3, [r7, #12]
|
|
8003cb8: 6818 ldr r0, [r3, #0]
|
|
8003cba: 68fb ldr r3, [r7, #12]
|
|
8003cbc: 799b ldrb r3, [r3, #6]
|
|
8003cbe: 461a mov r2, r3
|
|
8003cc0: 6979 ldr r1, [r7, #20]
|
|
8003cc2: f004 f819 bl 8007cf8 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
8003cc6: 2300 movs r3, #0
|
|
}
|
|
8003cc8: 4618 mov r0, r3
|
|
8003cca: 3718 adds r7, #24
|
|
8003ccc: 46bd mov sp, r7
|
|
8003cce: bd80 pop {r7, pc}
|
|
|
|
08003cd0 <HAL_PCD_EP_Transmit>:
|
|
* @param pBuf pointer to the transmission buffer
|
|
* @param len amount of data to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
8003cd0: b580 push {r7, lr}
|
|
8003cd2: b086 sub sp, #24
|
|
8003cd4: af00 add r7, sp, #0
|
|
8003cd6: 60f8 str r0, [r7, #12]
|
|
8003cd8: 607a str r2, [r7, #4]
|
|
8003cda: 603b str r3, [r7, #0]
|
|
8003cdc: 460b mov r3, r1
|
|
8003cde: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8003ce0: 7afb ldrb r3, [r7, #11]
|
|
8003ce2: f003 020f and.w r2, r3, #15
|
|
8003ce6: 4613 mov r3, r2
|
|
8003ce8: 00db lsls r3, r3, #3
|
|
8003cea: 4413 add r3, r2
|
|
8003cec: 009b lsls r3, r3, #2
|
|
8003cee: 3310 adds r3, #16
|
|
8003cf0: 68fa ldr r2, [r7, #12]
|
|
8003cf2: 4413 add r3, r2
|
|
8003cf4: 3304 adds r3, #4
|
|
8003cf6: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
8003cf8: 697b ldr r3, [r7, #20]
|
|
8003cfa: 687a ldr r2, [r7, #4]
|
|
8003cfc: 60da str r2, [r3, #12]
|
|
ep->xfer_len = len;
|
|
8003cfe: 697b ldr r3, [r7, #20]
|
|
8003d00: 683a ldr r2, [r7, #0]
|
|
8003d02: 611a str r2, [r3, #16]
|
|
ep->xfer_count = 0U;
|
|
8003d04: 697b ldr r3, [r7, #20]
|
|
8003d06: 2200 movs r2, #0
|
|
8003d08: 615a str r2, [r3, #20]
|
|
ep->is_in = 1U;
|
|
8003d0a: 697b ldr r3, [r7, #20]
|
|
8003d0c: 2201 movs r2, #1
|
|
8003d0e: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8003d10: 7afb ldrb r3, [r7, #11]
|
|
8003d12: f003 030f and.w r3, r3, #15
|
|
8003d16: b2da uxtb r2, r3
|
|
8003d18: 697b ldr r3, [r7, #20]
|
|
8003d1a: 701a strb r2, [r3, #0]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8003d1c: 68fb ldr r3, [r7, #12]
|
|
8003d1e: 799b ldrb r3, [r3, #6]
|
|
8003d20: 2b01 cmp r3, #1
|
|
8003d22: d102 bne.n 8003d2a <HAL_PCD_EP_Transmit+0x5a>
|
|
{
|
|
ep->dma_addr = (uint32_t)pBuf;
|
|
8003d24: 687a ldr r2, [r7, #4]
|
|
8003d26: 697b ldr r3, [r7, #20]
|
|
8003d28: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
|
|
8003d2a: 68fb ldr r3, [r7, #12]
|
|
8003d2c: 6818 ldr r0, [r3, #0]
|
|
8003d2e: 68fb ldr r3, [r7, #12]
|
|
8003d30: 799b ldrb r3, [r3, #6]
|
|
8003d32: 461a mov r2, r3
|
|
8003d34: 6979 ldr r1, [r7, #20]
|
|
8003d36: f003 ffdf bl 8007cf8 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
8003d3a: 2300 movs r3, #0
|
|
}
|
|
8003d3c: 4618 mov r0, r3
|
|
8003d3e: 3718 adds r7, #24
|
|
8003d40: 46bd mov sp, r7
|
|
8003d42: bd80 pop {r7, pc}
|
|
|
|
08003d44 <HAL_PCD_EP_SetStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8003d44: b580 push {r7, lr}
|
|
8003d46: b084 sub sp, #16
|
|
8003d48: af00 add r7, sp, #0
|
|
8003d4a: 6078 str r0, [r7, #4]
|
|
8003d4c: 460b mov r3, r1
|
|
8003d4e: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
|
|
8003d50: 78fb ldrb r3, [r7, #3]
|
|
8003d52: f003 030f and.w r3, r3, #15
|
|
8003d56: 687a ldr r2, [r7, #4]
|
|
8003d58: 7912 ldrb r2, [r2, #4]
|
|
8003d5a: 4293 cmp r3, r2
|
|
8003d5c: d901 bls.n 8003d62 <HAL_PCD_EP_SetStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8003d5e: 2301 movs r3, #1
|
|
8003d60: e04f b.n 8003e02 <HAL_PCD_EP_SetStall+0xbe>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8003d62: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8003d66: 2b00 cmp r3, #0
|
|
8003d68: da0f bge.n 8003d8a <HAL_PCD_EP_SetStall+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8003d6a: 78fb ldrb r3, [r7, #3]
|
|
8003d6c: f003 020f and.w r2, r3, #15
|
|
8003d70: 4613 mov r3, r2
|
|
8003d72: 00db lsls r3, r3, #3
|
|
8003d74: 4413 add r3, r2
|
|
8003d76: 009b lsls r3, r3, #2
|
|
8003d78: 3310 adds r3, #16
|
|
8003d7a: 687a ldr r2, [r7, #4]
|
|
8003d7c: 4413 add r3, r2
|
|
8003d7e: 3304 adds r3, #4
|
|
8003d80: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8003d82: 68fb ldr r3, [r7, #12]
|
|
8003d84: 2201 movs r2, #1
|
|
8003d86: 705a strb r2, [r3, #1]
|
|
8003d88: e00d b.n 8003da6 <HAL_PCD_EP_SetStall+0x62>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr];
|
|
8003d8a: 78fa ldrb r2, [r7, #3]
|
|
8003d8c: 4613 mov r3, r2
|
|
8003d8e: 00db lsls r3, r3, #3
|
|
8003d90: 4413 add r3, r2
|
|
8003d92: 009b lsls r3, r3, #2
|
|
8003d94: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003d98: 687a ldr r2, [r7, #4]
|
|
8003d9a: 4413 add r3, r2
|
|
8003d9c: 3304 adds r3, #4
|
|
8003d9e: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8003da0: 68fb ldr r3, [r7, #12]
|
|
8003da2: 2200 movs r2, #0
|
|
8003da4: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 1U;
|
|
8003da6: 68fb ldr r3, [r7, #12]
|
|
8003da8: 2201 movs r2, #1
|
|
8003daa: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8003dac: 78fb ldrb r3, [r7, #3]
|
|
8003dae: f003 030f and.w r3, r3, #15
|
|
8003db2: b2da uxtb r2, r3
|
|
8003db4: 68fb ldr r3, [r7, #12]
|
|
8003db6: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8003db8: 687b ldr r3, [r7, #4]
|
|
8003dba: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8003dbe: 2b01 cmp r3, #1
|
|
8003dc0: d101 bne.n 8003dc6 <HAL_PCD_EP_SetStall+0x82>
|
|
8003dc2: 2302 movs r3, #2
|
|
8003dc4: e01d b.n 8003e02 <HAL_PCD_EP_SetStall+0xbe>
|
|
8003dc6: 687b ldr r3, [r7, #4]
|
|
8003dc8: 2201 movs r2, #1
|
|
8003dca: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
(void)USB_EPSetStall(hpcd->Instance, ep);
|
|
8003dce: 687b ldr r3, [r7, #4]
|
|
8003dd0: 681b ldr r3, [r3, #0]
|
|
8003dd2: 68f9 ldr r1, [r7, #12]
|
|
8003dd4: 4618 mov r0, r3
|
|
8003dd6: f004 fb6d bl 80084b4 <USB_EPSetStall>
|
|
|
|
if ((ep_addr & EP_ADDR_MSK) == 0U)
|
|
8003dda: 78fb ldrb r3, [r7, #3]
|
|
8003ddc: f003 030f and.w r3, r3, #15
|
|
8003de0: 2b00 cmp r3, #0
|
|
8003de2: d109 bne.n 8003df8 <HAL_PCD_EP_SetStall+0xb4>
|
|
{
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
|
|
8003de4: 687b ldr r3, [r7, #4]
|
|
8003de6: 6818 ldr r0, [r3, #0]
|
|
8003de8: 687b ldr r3, [r7, #4]
|
|
8003dea: 7999 ldrb r1, [r3, #6]
|
|
8003dec: 687b ldr r3, [r7, #4]
|
|
8003dee: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8003df2: 461a mov r2, r3
|
|
8003df4: f004 fd5e bl 80088b4 <USB_EP0_OutStart>
|
|
}
|
|
|
|
__HAL_UNLOCK(hpcd);
|
|
8003df8: 687b ldr r3, [r7, #4]
|
|
8003dfa: 2200 movs r2, #0
|
|
8003dfc: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8003e00: 2300 movs r3, #0
|
|
}
|
|
8003e02: 4618 mov r0, r3
|
|
8003e04: 3710 adds r7, #16
|
|
8003e06: 46bd mov sp, r7
|
|
8003e08: bd80 pop {r7, pc}
|
|
|
|
08003e0a <HAL_PCD_EP_ClrStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8003e0a: b580 push {r7, lr}
|
|
8003e0c: b084 sub sp, #16
|
|
8003e0e: af00 add r7, sp, #0
|
|
8003e10: 6078 str r0, [r7, #4]
|
|
8003e12: 460b mov r3, r1
|
|
8003e14: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
|
|
8003e16: 78fb ldrb r3, [r7, #3]
|
|
8003e18: f003 030f and.w r3, r3, #15
|
|
8003e1c: 687a ldr r2, [r7, #4]
|
|
8003e1e: 7912 ldrb r2, [r2, #4]
|
|
8003e20: 4293 cmp r3, r2
|
|
8003e22: d901 bls.n 8003e28 <HAL_PCD_EP_ClrStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8003e24: 2301 movs r3, #1
|
|
8003e26: e042 b.n 8003eae <HAL_PCD_EP_ClrStall+0xa4>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8003e28: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8003e2c: 2b00 cmp r3, #0
|
|
8003e2e: da0f bge.n 8003e50 <HAL_PCD_EP_ClrStall+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8003e30: 78fb ldrb r3, [r7, #3]
|
|
8003e32: f003 020f and.w r2, r3, #15
|
|
8003e36: 4613 mov r3, r2
|
|
8003e38: 00db lsls r3, r3, #3
|
|
8003e3a: 4413 add r3, r2
|
|
8003e3c: 009b lsls r3, r3, #2
|
|
8003e3e: 3310 adds r3, #16
|
|
8003e40: 687a ldr r2, [r7, #4]
|
|
8003e42: 4413 add r3, r2
|
|
8003e44: 3304 adds r3, #4
|
|
8003e46: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8003e48: 68fb ldr r3, [r7, #12]
|
|
8003e4a: 2201 movs r2, #1
|
|
8003e4c: 705a strb r2, [r3, #1]
|
|
8003e4e: e00f b.n 8003e70 <HAL_PCD_EP_ClrStall+0x66>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8003e50: 78fb ldrb r3, [r7, #3]
|
|
8003e52: f003 020f and.w r2, r3, #15
|
|
8003e56: 4613 mov r3, r2
|
|
8003e58: 00db lsls r3, r3, #3
|
|
8003e5a: 4413 add r3, r2
|
|
8003e5c: 009b lsls r3, r3, #2
|
|
8003e5e: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003e62: 687a ldr r2, [r7, #4]
|
|
8003e64: 4413 add r3, r2
|
|
8003e66: 3304 adds r3, #4
|
|
8003e68: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8003e6a: 68fb ldr r3, [r7, #12]
|
|
8003e6c: 2200 movs r2, #0
|
|
8003e6e: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 0U;
|
|
8003e70: 68fb ldr r3, [r7, #12]
|
|
8003e72: 2200 movs r2, #0
|
|
8003e74: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8003e76: 78fb ldrb r3, [r7, #3]
|
|
8003e78: f003 030f and.w r3, r3, #15
|
|
8003e7c: b2da uxtb r2, r3
|
|
8003e7e: 68fb ldr r3, [r7, #12]
|
|
8003e80: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8003e82: 687b ldr r3, [r7, #4]
|
|
8003e84: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8003e88: 2b01 cmp r3, #1
|
|
8003e8a: d101 bne.n 8003e90 <HAL_PCD_EP_ClrStall+0x86>
|
|
8003e8c: 2302 movs r3, #2
|
|
8003e8e: e00e b.n 8003eae <HAL_PCD_EP_ClrStall+0xa4>
|
|
8003e90: 687b ldr r3, [r7, #4]
|
|
8003e92: 2201 movs r2, #1
|
|
8003e94: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_EPClearStall(hpcd->Instance, ep);
|
|
8003e98: 687b ldr r3, [r7, #4]
|
|
8003e9a: 681b ldr r3, [r3, #0]
|
|
8003e9c: 68f9 ldr r1, [r7, #12]
|
|
8003e9e: 4618 mov r0, r3
|
|
8003ea0: f004 fb76 bl 8008590 <USB_EPClearStall>
|
|
__HAL_UNLOCK(hpcd);
|
|
8003ea4: 687b ldr r3, [r7, #4]
|
|
8003ea6: 2200 movs r2, #0
|
|
8003ea8: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8003eac: 2300 movs r3, #0
|
|
}
|
|
8003eae: 4618 mov r0, r3
|
|
8003eb0: 3710 adds r7, #16
|
|
8003eb2: 46bd mov sp, r7
|
|
8003eb4: bd80 pop {r7, pc}
|
|
|
|
08003eb6 <HAL_PCD_EP_Abort>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8003eb6: b580 push {r7, lr}
|
|
8003eb8: b084 sub sp, #16
|
|
8003eba: af00 add r7, sp, #0
|
|
8003ebc: 6078 str r0, [r7, #4]
|
|
8003ebe: 460b mov r3, r1
|
|
8003ec0: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef ret;
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8003ec2: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8003ec6: 2b00 cmp r3, #0
|
|
8003ec8: da0c bge.n 8003ee4 <HAL_PCD_EP_Abort+0x2e>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8003eca: 78fb ldrb r3, [r7, #3]
|
|
8003ecc: f003 020f and.w r2, r3, #15
|
|
8003ed0: 4613 mov r3, r2
|
|
8003ed2: 00db lsls r3, r3, #3
|
|
8003ed4: 4413 add r3, r2
|
|
8003ed6: 009b lsls r3, r3, #2
|
|
8003ed8: 3310 adds r3, #16
|
|
8003eda: 687a ldr r2, [r7, #4]
|
|
8003edc: 4413 add r3, r2
|
|
8003ede: 3304 adds r3, #4
|
|
8003ee0: 60fb str r3, [r7, #12]
|
|
8003ee2: e00c b.n 8003efe <HAL_PCD_EP_Abort+0x48>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8003ee4: 78fb ldrb r3, [r7, #3]
|
|
8003ee6: f003 020f and.w r2, r3, #15
|
|
8003eea: 4613 mov r3, r2
|
|
8003eec: 00db lsls r3, r3, #3
|
|
8003eee: 4413 add r3, r2
|
|
8003ef0: 009b lsls r3, r3, #2
|
|
8003ef2: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003ef6: 687a ldr r2, [r7, #4]
|
|
8003ef8: 4413 add r3, r2
|
|
8003efa: 3304 adds r3, #4
|
|
8003efc: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Stop Xfer */
|
|
ret = USB_EPStopXfer(hpcd->Instance, ep);
|
|
8003efe: 687b ldr r3, [r7, #4]
|
|
8003f00: 681b ldr r3, [r3, #0]
|
|
8003f02: 68f9 ldr r1, [r7, #12]
|
|
8003f04: 4618 mov r0, r3
|
|
8003f06: f004 f995 bl 8008234 <USB_EPStopXfer>
|
|
8003f0a: 4603 mov r3, r0
|
|
8003f0c: 72fb strb r3, [r7, #11]
|
|
|
|
return ret;
|
|
8003f0e: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
8003f10: 4618 mov r0, r3
|
|
8003f12: 3710 adds r7, #16
|
|
8003f14: 46bd mov sp, r7
|
|
8003f16: bd80 pop {r7, pc}
|
|
|
|
08003f18 <PCD_WriteEmptyTxFifo>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8003f18: b580 push {r7, lr}
|
|
8003f1a: b08a sub sp, #40 @ 0x28
|
|
8003f1c: af02 add r7, sp, #8
|
|
8003f1e: 6078 str r0, [r7, #4]
|
|
8003f20: 6039 str r1, [r7, #0]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8003f22: 687b ldr r3, [r7, #4]
|
|
8003f24: 681b ldr r3, [r3, #0]
|
|
8003f26: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8003f28: 697b ldr r3, [r7, #20]
|
|
8003f2a: 613b str r3, [r7, #16]
|
|
USB_OTG_EPTypeDef *ep;
|
|
uint32_t len;
|
|
uint32_t len32b;
|
|
uint32_t fifoemptymsk;
|
|
|
|
ep = &hpcd->IN_ep[epnum];
|
|
8003f2c: 683a ldr r2, [r7, #0]
|
|
8003f2e: 4613 mov r3, r2
|
|
8003f30: 00db lsls r3, r3, #3
|
|
8003f32: 4413 add r3, r2
|
|
8003f34: 009b lsls r3, r3, #2
|
|
8003f36: 3310 adds r3, #16
|
|
8003f38: 687a ldr r2, [r7, #4]
|
|
8003f3a: 4413 add r3, r2
|
|
8003f3c: 3304 adds r3, #4
|
|
8003f3e: 60fb str r3, [r7, #12]
|
|
|
|
if (ep->xfer_count > ep->xfer_len)
|
|
8003f40: 68fb ldr r3, [r7, #12]
|
|
8003f42: 695a ldr r2, [r3, #20]
|
|
8003f44: 68fb ldr r3, [r7, #12]
|
|
8003f46: 691b ldr r3, [r3, #16]
|
|
8003f48: 429a cmp r2, r3
|
|
8003f4a: d901 bls.n 8003f50 <PCD_WriteEmptyTxFifo+0x38>
|
|
{
|
|
return HAL_ERROR;
|
|
8003f4c: 2301 movs r3, #1
|
|
8003f4e: e06b b.n 8004028 <PCD_WriteEmptyTxFifo+0x110>
|
|
}
|
|
|
|
len = ep->xfer_len - ep->xfer_count;
|
|
8003f50: 68fb ldr r3, [r7, #12]
|
|
8003f52: 691a ldr r2, [r3, #16]
|
|
8003f54: 68fb ldr r3, [r7, #12]
|
|
8003f56: 695b ldr r3, [r3, #20]
|
|
8003f58: 1ad3 subs r3, r2, r3
|
|
8003f5a: 61fb str r3, [r7, #28]
|
|
|
|
if (len > ep->maxpacket)
|
|
8003f5c: 68fb ldr r3, [r7, #12]
|
|
8003f5e: 689b ldr r3, [r3, #8]
|
|
8003f60: 69fa ldr r2, [r7, #28]
|
|
8003f62: 429a cmp r2, r3
|
|
8003f64: d902 bls.n 8003f6c <PCD_WriteEmptyTxFifo+0x54>
|
|
{
|
|
len = ep->maxpacket;
|
|
8003f66: 68fb ldr r3, [r7, #12]
|
|
8003f68: 689b ldr r3, [r3, #8]
|
|
8003f6a: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
len32b = (len + 3U) / 4U;
|
|
8003f6c: 69fb ldr r3, [r7, #28]
|
|
8003f6e: 3303 adds r3, #3
|
|
8003f70: 089b lsrs r3, r3, #2
|
|
8003f72: 61bb str r3, [r7, #24]
|
|
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8003f74: e02a b.n 8003fcc <PCD_WriteEmptyTxFifo+0xb4>
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
{
|
|
/* Write the FIFO */
|
|
len = ep->xfer_len - ep->xfer_count;
|
|
8003f76: 68fb ldr r3, [r7, #12]
|
|
8003f78: 691a ldr r2, [r3, #16]
|
|
8003f7a: 68fb ldr r3, [r7, #12]
|
|
8003f7c: 695b ldr r3, [r3, #20]
|
|
8003f7e: 1ad3 subs r3, r2, r3
|
|
8003f80: 61fb str r3, [r7, #28]
|
|
|
|
if (len > ep->maxpacket)
|
|
8003f82: 68fb ldr r3, [r7, #12]
|
|
8003f84: 689b ldr r3, [r3, #8]
|
|
8003f86: 69fa ldr r2, [r7, #28]
|
|
8003f88: 429a cmp r2, r3
|
|
8003f8a: d902 bls.n 8003f92 <PCD_WriteEmptyTxFifo+0x7a>
|
|
{
|
|
len = ep->maxpacket;
|
|
8003f8c: 68fb ldr r3, [r7, #12]
|
|
8003f8e: 689b ldr r3, [r3, #8]
|
|
8003f90: 61fb str r3, [r7, #28]
|
|
}
|
|
len32b = (len + 3U) / 4U;
|
|
8003f92: 69fb ldr r3, [r7, #28]
|
|
8003f94: 3303 adds r3, #3
|
|
8003f96: 089b lsrs r3, r3, #2
|
|
8003f98: 61bb str r3, [r7, #24]
|
|
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
|
|
8003f9a: 68fb ldr r3, [r7, #12]
|
|
8003f9c: 68d9 ldr r1, [r3, #12]
|
|
8003f9e: 683b ldr r3, [r7, #0]
|
|
8003fa0: b2da uxtb r2, r3
|
|
8003fa2: 69fb ldr r3, [r7, #28]
|
|
8003fa4: b298 uxth r0, r3
|
|
(uint8_t)hpcd->Init.dma_enable);
|
|
8003fa6: 687b ldr r3, [r7, #4]
|
|
8003fa8: 799b ldrb r3, [r3, #6]
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
|
|
8003faa: 9300 str r3, [sp, #0]
|
|
8003fac: 4603 mov r3, r0
|
|
8003fae: 6978 ldr r0, [r7, #20]
|
|
8003fb0: f004 f9ea bl 8008388 <USB_WritePacket>
|
|
|
|
ep->xfer_buff += len;
|
|
8003fb4: 68fb ldr r3, [r7, #12]
|
|
8003fb6: 68da ldr r2, [r3, #12]
|
|
8003fb8: 69fb ldr r3, [r7, #28]
|
|
8003fba: 441a add r2, r3
|
|
8003fbc: 68fb ldr r3, [r7, #12]
|
|
8003fbe: 60da str r2, [r3, #12]
|
|
ep->xfer_count += len;
|
|
8003fc0: 68fb ldr r3, [r7, #12]
|
|
8003fc2: 695a ldr r2, [r3, #20]
|
|
8003fc4: 69fb ldr r3, [r7, #28]
|
|
8003fc6: 441a add r2, r3
|
|
8003fc8: 68fb ldr r3, [r7, #12]
|
|
8003fca: 615a str r2, [r3, #20]
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8003fcc: 683b ldr r3, [r7, #0]
|
|
8003fce: 015a lsls r2, r3, #5
|
|
8003fd0: 693b ldr r3, [r7, #16]
|
|
8003fd2: 4413 add r3, r2
|
|
8003fd4: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8003fd8: 699b ldr r3, [r3, #24]
|
|
8003fda: b29b uxth r3, r3
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
8003fdc: 69ba ldr r2, [r7, #24]
|
|
8003fde: 429a cmp r2, r3
|
|
8003fe0: d809 bhi.n 8003ff6 <PCD_WriteEmptyTxFifo+0xde>
|
|
8003fe2: 68fb ldr r3, [r7, #12]
|
|
8003fe4: 695a ldr r2, [r3, #20]
|
|
8003fe6: 68fb ldr r3, [r7, #12]
|
|
8003fe8: 691b ldr r3, [r3, #16]
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8003fea: 429a cmp r2, r3
|
|
8003fec: d203 bcs.n 8003ff6 <PCD_WriteEmptyTxFifo+0xde>
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
8003fee: 68fb ldr r3, [r7, #12]
|
|
8003ff0: 691b ldr r3, [r3, #16]
|
|
8003ff2: 2b00 cmp r3, #0
|
|
8003ff4: d1bf bne.n 8003f76 <PCD_WriteEmptyTxFifo+0x5e>
|
|
}
|
|
|
|
if (ep->xfer_len <= ep->xfer_count)
|
|
8003ff6: 68fb ldr r3, [r7, #12]
|
|
8003ff8: 691a ldr r2, [r3, #16]
|
|
8003ffa: 68fb ldr r3, [r7, #12]
|
|
8003ffc: 695b ldr r3, [r3, #20]
|
|
8003ffe: 429a cmp r2, r3
|
|
8004000: d811 bhi.n 8004026 <PCD_WriteEmptyTxFifo+0x10e>
|
|
{
|
|
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
|
|
8004002: 683b ldr r3, [r7, #0]
|
|
8004004: f003 030f and.w r3, r3, #15
|
|
8004008: 2201 movs r2, #1
|
|
800400a: fa02 f303 lsl.w r3, r2, r3
|
|
800400e: 60bb str r3, [r7, #8]
|
|
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
|
|
8004010: 693b ldr r3, [r7, #16]
|
|
8004012: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8004016: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8004018: 68bb ldr r3, [r7, #8]
|
|
800401a: 43db mvns r3, r3
|
|
800401c: 6939 ldr r1, [r7, #16]
|
|
800401e: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8004022: 4013 ands r3, r2
|
|
8004024: 634b str r3, [r1, #52] @ 0x34
|
|
}
|
|
|
|
return HAL_OK;
|
|
8004026: 2300 movs r3, #0
|
|
}
|
|
8004028: 4618 mov r0, r3
|
|
800402a: 3720 adds r7, #32
|
|
800402c: 46bd mov sp, r7
|
|
800402e: bd80 pop {r7, pc}
|
|
|
|
08004030 <PCD_EP_OutXfrComplete_int>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8004030: b580 push {r7, lr}
|
|
8004032: b088 sub sp, #32
|
|
8004034: af00 add r7, sp, #0
|
|
8004036: 6078 str r0, [r7, #4]
|
|
8004038: 6039 str r1, [r7, #0]
|
|
USB_OTG_EPTypeDef *ep;
|
|
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
800403a: 687b ldr r3, [r7, #4]
|
|
800403c: 681b ldr r3, [r3, #0]
|
|
800403e: 61fb str r3, [r7, #28]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8004040: 69fb ldr r3, [r7, #28]
|
|
8004042: 61bb str r3, [r7, #24]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
8004044: 69fb ldr r3, [r7, #28]
|
|
8004046: 333c adds r3, #60 @ 0x3c
|
|
8004048: 3304 adds r3, #4
|
|
800404a: 681b ldr r3, [r3, #0]
|
|
800404c: 617b str r3, [r7, #20]
|
|
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
|
|
800404e: 683b ldr r3, [r7, #0]
|
|
8004050: 015a lsls r2, r3, #5
|
|
8004052: 69bb ldr r3, [r7, #24]
|
|
8004054: 4413 add r3, r2
|
|
8004056: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800405a: 689b ldr r3, [r3, #8]
|
|
800405c: 613b str r3, [r7, #16]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
800405e: 687b ldr r3, [r7, #4]
|
|
8004060: 799b ldrb r3, [r3, #6]
|
|
8004062: 2b01 cmp r3, #1
|
|
8004064: d17b bne.n 800415e <PCD_EP_OutXfrComplete_int+0x12e>
|
|
{
|
|
if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
|
|
8004066: 693b ldr r3, [r7, #16]
|
|
8004068: f003 0308 and.w r3, r3, #8
|
|
800406c: 2b00 cmp r3, #0
|
|
800406e: d015 beq.n 800409c <PCD_EP_OutXfrComplete_int+0x6c>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8004070: 697b ldr r3, [r7, #20]
|
|
8004072: 4a61 ldr r2, [pc, #388] @ (80041f8 <PCD_EP_OutXfrComplete_int+0x1c8>)
|
|
8004074: 4293 cmp r3, r2
|
|
8004076: f240 80b9 bls.w 80041ec <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
800407a: 693b ldr r3, [r7, #16]
|
|
800407c: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8004080: 2b00 cmp r3, #0
|
|
8004082: f000 80b3 beq.w 80041ec <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8004086: 683b ldr r3, [r7, #0]
|
|
8004088: 015a lsls r2, r3, #5
|
|
800408a: 69bb ldr r3, [r7, #24]
|
|
800408c: 4413 add r3, r2
|
|
800408e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8004092: 461a mov r2, r3
|
|
8004094: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8004098: 6093 str r3, [r2, #8]
|
|
800409a: e0a7 b.n 80041ec <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
}
|
|
else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
|
|
800409c: 693b ldr r3, [r7, #16]
|
|
800409e: f003 0320 and.w r3, r3, #32
|
|
80040a2: 2b00 cmp r3, #0
|
|
80040a4: d009 beq.n 80040ba <PCD_EP_OutXfrComplete_int+0x8a>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
80040a6: 683b ldr r3, [r7, #0]
|
|
80040a8: 015a lsls r2, r3, #5
|
|
80040aa: 69bb ldr r3, [r7, #24]
|
|
80040ac: 4413 add r3, r2
|
|
80040ae: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80040b2: 461a mov r2, r3
|
|
80040b4: 2320 movs r3, #32
|
|
80040b6: 6093 str r3, [r2, #8]
|
|
80040b8: e098 b.n 80041ec <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
|
|
80040ba: 693b ldr r3, [r7, #16]
|
|
80040bc: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
80040c0: 2b00 cmp r3, #0
|
|
80040c2: f040 8093 bne.w 80041ec <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
80040c6: 697b ldr r3, [r7, #20]
|
|
80040c8: 4a4b ldr r2, [pc, #300] @ (80041f8 <PCD_EP_OutXfrComplete_int+0x1c8>)
|
|
80040ca: 4293 cmp r3, r2
|
|
80040cc: d90f bls.n 80040ee <PCD_EP_OutXfrComplete_int+0xbe>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
80040ce: 693b ldr r3, [r7, #16]
|
|
80040d0: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
80040d4: 2b00 cmp r3, #0
|
|
80040d6: d00a beq.n 80040ee <PCD_EP_OutXfrComplete_int+0xbe>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
80040d8: 683b ldr r3, [r7, #0]
|
|
80040da: 015a lsls r2, r3, #5
|
|
80040dc: 69bb ldr r3, [r7, #24]
|
|
80040de: 4413 add r3, r2
|
|
80040e0: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80040e4: 461a mov r2, r3
|
|
80040e6: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
80040ea: 6093 str r3, [r2, #8]
|
|
80040ec: e07e b.n 80041ec <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[epnum];
|
|
80040ee: 683a ldr r2, [r7, #0]
|
|
80040f0: 4613 mov r3, r2
|
|
80040f2: 00db lsls r3, r3, #3
|
|
80040f4: 4413 add r3, r2
|
|
80040f6: 009b lsls r3, r3, #2
|
|
80040f8: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
80040fc: 687a ldr r2, [r7, #4]
|
|
80040fe: 4413 add r3, r2
|
|
8004100: 3304 adds r3, #4
|
|
8004102: 60fb str r3, [r7, #12]
|
|
|
|
/* out data packet received over EP */
|
|
ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
|
|
8004104: 68fb ldr r3, [r7, #12]
|
|
8004106: 6a1a ldr r2, [r3, #32]
|
|
8004108: 683b ldr r3, [r7, #0]
|
|
800410a: 0159 lsls r1, r3, #5
|
|
800410c: 69bb ldr r3, [r7, #24]
|
|
800410e: 440b add r3, r1
|
|
8004110: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8004114: 691b ldr r3, [r3, #16]
|
|
8004116: f3c3 0312 ubfx r3, r3, #0, #19
|
|
800411a: 1ad2 subs r2, r2, r3
|
|
800411c: 68fb ldr r3, [r7, #12]
|
|
800411e: 615a str r2, [r3, #20]
|
|
|
|
if (epnum == 0U)
|
|
8004120: 683b ldr r3, [r7, #0]
|
|
8004122: 2b00 cmp r3, #0
|
|
8004124: d114 bne.n 8004150 <PCD_EP_OutXfrComplete_int+0x120>
|
|
{
|
|
if (ep->xfer_len == 0U)
|
|
8004126: 68fb ldr r3, [r7, #12]
|
|
8004128: 691b ldr r3, [r3, #16]
|
|
800412a: 2b00 cmp r3, #0
|
|
800412c: d109 bne.n 8004142 <PCD_EP_OutXfrComplete_int+0x112>
|
|
{
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
800412e: 687b ldr r3, [r7, #4]
|
|
8004130: 6818 ldr r0, [r3, #0]
|
|
8004132: 687b ldr r3, [r7, #4]
|
|
8004134: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8004138: 461a mov r2, r3
|
|
800413a: 2101 movs r1, #1
|
|
800413c: f004 fbba bl 80088b4 <USB_EP0_OutStart>
|
|
8004140: e006 b.n 8004150 <PCD_EP_OutXfrComplete_int+0x120>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_buff += ep->xfer_count;
|
|
8004142: 68fb ldr r3, [r7, #12]
|
|
8004144: 68da ldr r2, [r3, #12]
|
|
8004146: 68fb ldr r3, [r7, #12]
|
|
8004148: 695b ldr r3, [r3, #20]
|
|
800414a: 441a add r2, r3
|
|
800414c: 68fb ldr r3, [r7, #12]
|
|
800414e: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
8004150: 683b ldr r3, [r7, #0]
|
|
8004152: b2db uxtb r3, r3
|
|
8004154: 4619 mov r1, r3
|
|
8004156: 6878 ldr r0, [r7, #4]
|
|
8004158: f006 fb88 bl 800a86c <HAL_PCD_DataOutStageCallback>
|
|
800415c: e046 b.n 80041ec <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
/* ... */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (gSNPSiD == USB_OTG_CORE_ID_310A)
|
|
800415e: 697b ldr r3, [r7, #20]
|
|
8004160: 4a26 ldr r2, [pc, #152] @ (80041fc <PCD_EP_OutXfrComplete_int+0x1cc>)
|
|
8004162: 4293 cmp r3, r2
|
|
8004164: d124 bne.n 80041b0 <PCD_EP_OutXfrComplete_int+0x180>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
|
|
8004166: 693b ldr r3, [r7, #16]
|
|
8004168: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
800416c: 2b00 cmp r3, #0
|
|
800416e: d00a beq.n 8004186 <PCD_EP_OutXfrComplete_int+0x156>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8004170: 683b ldr r3, [r7, #0]
|
|
8004172: 015a lsls r2, r3, #5
|
|
8004174: 69bb ldr r3, [r7, #24]
|
|
8004176: 4413 add r3, r2
|
|
8004178: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800417c: 461a mov r2, r3
|
|
800417e: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8004182: 6093 str r3, [r2, #8]
|
|
8004184: e032 b.n 80041ec <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else
|
|
{
|
|
if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
|
|
8004186: 693b ldr r3, [r7, #16]
|
|
8004188: f003 0320 and.w r3, r3, #32
|
|
800418c: 2b00 cmp r3, #0
|
|
800418e: d008 beq.n 80041a2 <PCD_EP_OutXfrComplete_int+0x172>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
8004190: 683b ldr r3, [r7, #0]
|
|
8004192: 015a lsls r2, r3, #5
|
|
8004194: 69bb ldr r3, [r7, #24]
|
|
8004196: 4413 add r3, r2
|
|
8004198: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800419c: 461a mov r2, r3
|
|
800419e: 2320 movs r3, #32
|
|
80041a0: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
80041a2: 683b ldr r3, [r7, #0]
|
|
80041a4: b2db uxtb r3, r3
|
|
80041a6: 4619 mov r1, r3
|
|
80041a8: 6878 ldr r0, [r7, #4]
|
|
80041aa: f006 fb5f bl 800a86c <HAL_PCD_DataOutStageCallback>
|
|
80041ae: e01d b.n 80041ec <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
|
|
80041b0: 683b ldr r3, [r7, #0]
|
|
80041b2: 2b00 cmp r3, #0
|
|
80041b4: d114 bne.n 80041e0 <PCD_EP_OutXfrComplete_int+0x1b0>
|
|
80041b6: 6879 ldr r1, [r7, #4]
|
|
80041b8: 683a ldr r2, [r7, #0]
|
|
80041ba: 4613 mov r3, r2
|
|
80041bc: 00db lsls r3, r3, #3
|
|
80041be: 4413 add r3, r2
|
|
80041c0: 009b lsls r3, r3, #2
|
|
80041c2: 440b add r3, r1
|
|
80041c4: f503 7319 add.w r3, r3, #612 @ 0x264
|
|
80041c8: 681b ldr r3, [r3, #0]
|
|
80041ca: 2b00 cmp r3, #0
|
|
80041cc: d108 bne.n 80041e0 <PCD_EP_OutXfrComplete_int+0x1b0>
|
|
{
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
|
|
80041ce: 687b ldr r3, [r7, #4]
|
|
80041d0: 6818 ldr r0, [r3, #0]
|
|
80041d2: 687b ldr r3, [r7, #4]
|
|
80041d4: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
80041d8: 461a mov r2, r3
|
|
80041da: 2100 movs r1, #0
|
|
80041dc: f004 fb6a bl 80088b4 <USB_EP0_OutStart>
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
80041e0: 683b ldr r3, [r7, #0]
|
|
80041e2: b2db uxtb r3, r3
|
|
80041e4: 4619 mov r1, r3
|
|
80041e6: 6878 ldr r0, [r7, #4]
|
|
80041e8: f006 fb40 bl 800a86c <HAL_PCD_DataOutStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
80041ec: 2300 movs r3, #0
|
|
}
|
|
80041ee: 4618 mov r0, r3
|
|
80041f0: 3720 adds r7, #32
|
|
80041f2: 46bd mov sp, r7
|
|
80041f4: bd80 pop {r7, pc}
|
|
80041f6: bf00 nop
|
|
80041f8: 4f54300a .word 0x4f54300a
|
|
80041fc: 4f54310a .word 0x4f54310a
|
|
|
|
08004200 <PCD_EP_OutSetupPacket_int>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8004200: b580 push {r7, lr}
|
|
8004202: b086 sub sp, #24
|
|
8004204: af00 add r7, sp, #0
|
|
8004206: 6078 str r0, [r7, #4]
|
|
8004208: 6039 str r1, [r7, #0]
|
|
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
800420a: 687b ldr r3, [r7, #4]
|
|
800420c: 681b ldr r3, [r3, #0]
|
|
800420e: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8004210: 697b ldr r3, [r7, #20]
|
|
8004212: 613b str r3, [r7, #16]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
8004214: 697b ldr r3, [r7, #20]
|
|
8004216: 333c adds r3, #60 @ 0x3c
|
|
8004218: 3304 adds r3, #4
|
|
800421a: 681b ldr r3, [r3, #0]
|
|
800421c: 60fb str r3, [r7, #12]
|
|
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
|
|
800421e: 683b ldr r3, [r7, #0]
|
|
8004220: 015a lsls r2, r3, #5
|
|
8004222: 693b ldr r3, [r7, #16]
|
|
8004224: 4413 add r3, r2
|
|
8004226: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800422a: 689b ldr r3, [r3, #8]
|
|
800422c: 60bb str r3, [r7, #8]
|
|
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
800422e: 68fb ldr r3, [r7, #12]
|
|
8004230: 4a15 ldr r2, [pc, #84] @ (8004288 <PCD_EP_OutSetupPacket_int+0x88>)
|
|
8004232: 4293 cmp r3, r2
|
|
8004234: d90e bls.n 8004254 <PCD_EP_OutSetupPacket_int+0x54>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
8004236: 68bb ldr r3, [r7, #8]
|
|
8004238: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
800423c: 2b00 cmp r3, #0
|
|
800423e: d009 beq.n 8004254 <PCD_EP_OutSetupPacket_int+0x54>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8004240: 683b ldr r3, [r7, #0]
|
|
8004242: 015a lsls r2, r3, #5
|
|
8004244: 693b ldr r3, [r7, #16]
|
|
8004246: 4413 add r3, r2
|
|
8004248: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800424c: 461a mov r2, r3
|
|
800424e: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8004252: 6093 str r3, [r2, #8]
|
|
|
|
/* Inform the upper layer that a setup packet is available */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SetupStageCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SetupStageCallback(hpcd);
|
|
8004254: 6878 ldr r0, [r7, #4]
|
|
8004256: f006 faf7 bl 800a848 <HAL_PCD_SetupStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
|
|
800425a: 68fb ldr r3, [r7, #12]
|
|
800425c: 4a0a ldr r2, [pc, #40] @ (8004288 <PCD_EP_OutSetupPacket_int+0x88>)
|
|
800425e: 4293 cmp r3, r2
|
|
8004260: d90c bls.n 800427c <PCD_EP_OutSetupPacket_int+0x7c>
|
|
8004262: 687b ldr r3, [r7, #4]
|
|
8004264: 799b ldrb r3, [r3, #6]
|
|
8004266: 2b01 cmp r3, #1
|
|
8004268: d108 bne.n 800427c <PCD_EP_OutSetupPacket_int+0x7c>
|
|
{
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
800426a: 687b ldr r3, [r7, #4]
|
|
800426c: 6818 ldr r0, [r3, #0]
|
|
800426e: 687b ldr r3, [r7, #4]
|
|
8004270: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8004274: 461a mov r2, r3
|
|
8004276: 2101 movs r1, #1
|
|
8004278: f004 fb1c bl 80088b4 <USB_EP0_OutStart>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800427c: 2300 movs r3, #0
|
|
}
|
|
800427e: 4618 mov r0, r3
|
|
8004280: 3718 adds r7, #24
|
|
8004282: 46bd mov sp, r7
|
|
8004284: bd80 pop {r7, pc}
|
|
8004286: bf00 nop
|
|
8004288: 4f54300a .word 0x4f54300a
|
|
|
|
0800428c <HAL_PCDEx_SetTxFiFo>:
|
|
* @param fifo The number of Tx fifo
|
|
* @param size Fifo size
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
|
|
{
|
|
800428c: b480 push {r7}
|
|
800428e: b085 sub sp, #20
|
|
8004290: af00 add r7, sp, #0
|
|
8004292: 6078 str r0, [r7, #4]
|
|
8004294: 460b mov r3, r1
|
|
8004296: 70fb strb r3, [r7, #3]
|
|
8004298: 4613 mov r3, r2
|
|
800429a: 803b strh r3, [r7, #0]
|
|
--> Txn should be configured with the minimum space of 16 words
|
|
The FIFO is used optimally when used TxFIFOs are allocated in the top
|
|
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
|
|
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
|
|
|
|
Tx_Offset = hpcd->Instance->GRXFSIZ;
|
|
800429c: 687b ldr r3, [r7, #4]
|
|
800429e: 681b ldr r3, [r3, #0]
|
|
80042a0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80042a2: 60bb str r3, [r7, #8]
|
|
|
|
if (fifo == 0U)
|
|
80042a4: 78fb ldrb r3, [r7, #3]
|
|
80042a6: 2b00 cmp r3, #0
|
|
80042a8: d107 bne.n 80042ba <HAL_PCDEx_SetTxFiFo+0x2e>
|
|
{
|
|
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
|
|
80042aa: 883b ldrh r3, [r7, #0]
|
|
80042ac: 0419 lsls r1, r3, #16
|
|
80042ae: 687b ldr r3, [r7, #4]
|
|
80042b0: 681b ldr r3, [r3, #0]
|
|
80042b2: 68ba ldr r2, [r7, #8]
|
|
80042b4: 430a orrs r2, r1
|
|
80042b6: 629a str r2, [r3, #40] @ 0x28
|
|
80042b8: e028 b.n 800430c <HAL_PCDEx_SetTxFiFo+0x80>
|
|
}
|
|
else
|
|
{
|
|
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
|
|
80042ba: 687b ldr r3, [r7, #4]
|
|
80042bc: 681b ldr r3, [r3, #0]
|
|
80042be: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80042c0: 0c1b lsrs r3, r3, #16
|
|
80042c2: 68ba ldr r2, [r7, #8]
|
|
80042c4: 4413 add r3, r2
|
|
80042c6: 60bb str r3, [r7, #8]
|
|
for (i = 0U; i < (fifo - 1U); i++)
|
|
80042c8: 2300 movs r3, #0
|
|
80042ca: 73fb strb r3, [r7, #15]
|
|
80042cc: e00d b.n 80042ea <HAL_PCDEx_SetTxFiFo+0x5e>
|
|
{
|
|
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
|
|
80042ce: 687b ldr r3, [r7, #4]
|
|
80042d0: 681a ldr r2, [r3, #0]
|
|
80042d2: 7bfb ldrb r3, [r7, #15]
|
|
80042d4: 3340 adds r3, #64 @ 0x40
|
|
80042d6: 009b lsls r3, r3, #2
|
|
80042d8: 4413 add r3, r2
|
|
80042da: 685b ldr r3, [r3, #4]
|
|
80042dc: 0c1b lsrs r3, r3, #16
|
|
80042de: 68ba ldr r2, [r7, #8]
|
|
80042e0: 4413 add r3, r2
|
|
80042e2: 60bb str r3, [r7, #8]
|
|
for (i = 0U; i < (fifo - 1U); i++)
|
|
80042e4: 7bfb ldrb r3, [r7, #15]
|
|
80042e6: 3301 adds r3, #1
|
|
80042e8: 73fb strb r3, [r7, #15]
|
|
80042ea: 7bfa ldrb r2, [r7, #15]
|
|
80042ec: 78fb ldrb r3, [r7, #3]
|
|
80042ee: 3b01 subs r3, #1
|
|
80042f0: 429a cmp r2, r3
|
|
80042f2: d3ec bcc.n 80042ce <HAL_PCDEx_SetTxFiFo+0x42>
|
|
}
|
|
|
|
/* Multiply Tx_Size by 2 to get higher performance */
|
|
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
|
|
80042f4: 883b ldrh r3, [r7, #0]
|
|
80042f6: 0418 lsls r0, r3, #16
|
|
80042f8: 687b ldr r3, [r7, #4]
|
|
80042fa: 6819 ldr r1, [r3, #0]
|
|
80042fc: 78fb ldrb r3, [r7, #3]
|
|
80042fe: 3b01 subs r3, #1
|
|
8004300: 68ba ldr r2, [r7, #8]
|
|
8004302: 4302 orrs r2, r0
|
|
8004304: 3340 adds r3, #64 @ 0x40
|
|
8004306: 009b lsls r3, r3, #2
|
|
8004308: 440b add r3, r1
|
|
800430a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
return HAL_OK;
|
|
800430c: 2300 movs r3, #0
|
|
}
|
|
800430e: 4618 mov r0, r3
|
|
8004310: 3714 adds r7, #20
|
|
8004312: 46bd mov sp, r7
|
|
8004314: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004318: 4770 bx lr
|
|
|
|
0800431a <HAL_PCDEx_SetRxFiFo>:
|
|
* @param hpcd PCD handle
|
|
* @param size Size of Rx fifo
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
|
|
{
|
|
800431a: b480 push {r7}
|
|
800431c: b083 sub sp, #12
|
|
800431e: af00 add r7, sp, #0
|
|
8004320: 6078 str r0, [r7, #4]
|
|
8004322: 460b mov r3, r1
|
|
8004324: 807b strh r3, [r7, #2]
|
|
hpcd->Instance->GRXFSIZ = size;
|
|
8004326: 687b ldr r3, [r7, #4]
|
|
8004328: 681b ldr r3, [r3, #0]
|
|
800432a: 887a ldrh r2, [r7, #2]
|
|
800432c: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_OK;
|
|
800432e: 2300 movs r3, #0
|
|
}
|
|
8004330: 4618 mov r0, r3
|
|
8004332: 370c adds r7, #12
|
|
8004334: 46bd mov sp, r7
|
|
8004336: f85d 7b04 ldr.w r7, [sp], #4
|
|
800433a: 4770 bx lr
|
|
|
|
0800433c <HAL_PCDEx_ActivateLPM>:
|
|
* @brief Activate LPM feature.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
800433c: b480 push {r7}
|
|
800433e: b085 sub sp, #20
|
|
8004340: af00 add r7, sp, #0
|
|
8004342: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8004344: 687b ldr r3, [r7, #4]
|
|
8004346: 681b ldr r3, [r3, #0]
|
|
8004348: 60fb str r3, [r7, #12]
|
|
|
|
hpcd->lpm_active = 1U;
|
|
800434a: 687b ldr r3, [r7, #4]
|
|
800434c: 2201 movs r2, #1
|
|
800434e: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8
|
|
hpcd->LPM_State = LPM_L0;
|
|
8004352: 687b ldr r3, [r7, #4]
|
|
8004354: 2200 movs r2, #0
|
|
8004356: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
|
|
800435a: 68fb ldr r3, [r7, #12]
|
|
800435c: 699b ldr r3, [r3, #24]
|
|
800435e: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000
|
|
8004362: 68fb ldr r3, [r7, #12]
|
|
8004364: 619a str r2, [r3, #24]
|
|
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
|
|
8004366: 68fb ldr r3, [r7, #12]
|
|
8004368: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800436a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800436e: f043 0303 orr.w r3, r3, #3
|
|
8004372: 68fa ldr r2, [r7, #12]
|
|
8004374: 6553 str r3, [r2, #84] @ 0x54
|
|
|
|
return HAL_OK;
|
|
8004376: 2300 movs r3, #0
|
|
}
|
|
8004378: 4618 mov r0, r3
|
|
800437a: 3714 adds r7, #20
|
|
800437c: 46bd mov sp, r7
|
|
800437e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004382: 4770 bx lr
|
|
|
|
08004384 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8004384: b580 push {r7, lr}
|
|
8004386: b084 sub sp, #16
|
|
8004388: af00 add r7, sp, #0
|
|
800438a: 6078 str r0, [r7, #4]
|
|
800438c: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
800438e: 687b ldr r3, [r7, #4]
|
|
8004390: 2b00 cmp r3, #0
|
|
8004392: d101 bne.n 8004398 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8004394: 2301 movs r3, #1
|
|
8004396: e0cc b.n 8004532 <HAL_RCC_ClockConfig+0x1ae>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8004398: 4b68 ldr r3, [pc, #416] @ (800453c <HAL_RCC_ClockConfig+0x1b8>)
|
|
800439a: 681b ldr r3, [r3, #0]
|
|
800439c: f003 030f and.w r3, r3, #15
|
|
80043a0: 683a ldr r2, [r7, #0]
|
|
80043a2: 429a cmp r2, r3
|
|
80043a4: d90c bls.n 80043c0 <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80043a6: 4b65 ldr r3, [pc, #404] @ (800453c <HAL_RCC_ClockConfig+0x1b8>)
|
|
80043a8: 683a ldr r2, [r7, #0]
|
|
80043aa: b2d2 uxtb r2, r2
|
|
80043ac: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80043ae: 4b63 ldr r3, [pc, #396] @ (800453c <HAL_RCC_ClockConfig+0x1b8>)
|
|
80043b0: 681b ldr r3, [r3, #0]
|
|
80043b2: f003 030f and.w r3, r3, #15
|
|
80043b6: 683a ldr r2, [r7, #0]
|
|
80043b8: 429a cmp r2, r3
|
|
80043ba: d001 beq.n 80043c0 <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
return HAL_ERROR;
|
|
80043bc: 2301 movs r3, #1
|
|
80043be: e0b8 b.n 8004532 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
80043c0: 687b ldr r3, [r7, #4]
|
|
80043c2: 681b ldr r3, [r3, #0]
|
|
80043c4: f003 0302 and.w r3, r3, #2
|
|
80043c8: 2b00 cmp r3, #0
|
|
80043ca: d020 beq.n 800440e <HAL_RCC_ClockConfig+0x8a>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
80043cc: 687b ldr r3, [r7, #4]
|
|
80043ce: 681b ldr r3, [r3, #0]
|
|
80043d0: f003 0304 and.w r3, r3, #4
|
|
80043d4: 2b00 cmp r3, #0
|
|
80043d6: d005 beq.n 80043e4 <HAL_RCC_ClockConfig+0x60>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
80043d8: 4b59 ldr r3, [pc, #356] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80043da: 689b ldr r3, [r3, #8]
|
|
80043dc: 4a58 ldr r2, [pc, #352] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80043de: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
|
|
80043e2: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
80043e4: 687b ldr r3, [r7, #4]
|
|
80043e6: 681b ldr r3, [r3, #0]
|
|
80043e8: f003 0308 and.w r3, r3, #8
|
|
80043ec: 2b00 cmp r3, #0
|
|
80043ee: d005 beq.n 80043fc <HAL_RCC_ClockConfig+0x78>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
80043f0: 4b53 ldr r3, [pc, #332] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80043f2: 689b ldr r3, [r3, #8]
|
|
80043f4: 4a52 ldr r2, [pc, #328] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80043f6: f443 4360 orr.w r3, r3, #57344 @ 0xe000
|
|
80043fa: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
80043fc: 4b50 ldr r3, [pc, #320] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80043fe: 689b ldr r3, [r3, #8]
|
|
8004400: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8004404: 687b ldr r3, [r7, #4]
|
|
8004406: 689b ldr r3, [r3, #8]
|
|
8004408: 494d ldr r1, [pc, #308] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800440a: 4313 orrs r3, r2
|
|
800440c: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
800440e: 687b ldr r3, [r7, #4]
|
|
8004410: 681b ldr r3, [r3, #0]
|
|
8004412: f003 0301 and.w r3, r3, #1
|
|
8004416: 2b00 cmp r3, #0
|
|
8004418: d044 beq.n 80044a4 <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
800441a: 687b ldr r3, [r7, #4]
|
|
800441c: 685b ldr r3, [r3, #4]
|
|
800441e: 2b01 cmp r3, #1
|
|
8004420: d107 bne.n 8004432 <HAL_RCC_ClockConfig+0xae>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8004422: 4b47 ldr r3, [pc, #284] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004424: 681b ldr r3, [r3, #0]
|
|
8004426: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800442a: 2b00 cmp r3, #0
|
|
800442c: d119 bne.n 8004462 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
800442e: 2301 movs r3, #1
|
|
8004430: e07f b.n 8004532 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
8004432: 687b ldr r3, [r7, #4]
|
|
8004434: 685b ldr r3, [r3, #4]
|
|
8004436: 2b02 cmp r3, #2
|
|
8004438: d003 beq.n 8004442 <HAL_RCC_ClockConfig+0xbe>
|
|
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
|
|
800443a: 687b ldr r3, [r7, #4]
|
|
800443c: 685b ldr r3, [r3, #4]
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
800443e: 2b03 cmp r3, #3
|
|
8004440: d107 bne.n 8004452 <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8004442: 4b3f ldr r3, [pc, #252] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004444: 681b ldr r3, [r3, #0]
|
|
8004446: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800444a: 2b00 cmp r3, #0
|
|
800444c: d109 bne.n 8004462 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
800444e: 2301 movs r3, #1
|
|
8004450: e06f b.n 8004532 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004452: 4b3b ldr r3, [pc, #236] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004454: 681b ldr r3, [r3, #0]
|
|
8004456: f003 0302 and.w r3, r3, #2
|
|
800445a: 2b00 cmp r3, #0
|
|
800445c: d101 bne.n 8004462 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
800445e: 2301 movs r3, #1
|
|
8004460: e067 b.n 8004532 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
8004462: 4b37 ldr r3, [pc, #220] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004464: 689b ldr r3, [r3, #8]
|
|
8004466: f023 0203 bic.w r2, r3, #3
|
|
800446a: 687b ldr r3, [r7, #4]
|
|
800446c: 685b ldr r3, [r3, #4]
|
|
800446e: 4934 ldr r1, [pc, #208] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004470: 4313 orrs r3, r2
|
|
8004472: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004474: f7fd fcb2 bl 8001ddc <HAL_GetTick>
|
|
8004478: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800447a: e00a b.n 8004492 <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
800447c: f7fd fcae bl 8001ddc <HAL_GetTick>
|
|
8004480: 4602 mov r2, r0
|
|
8004482: 68fb ldr r3, [r7, #12]
|
|
8004484: 1ad3 subs r3, r2, r3
|
|
8004486: f241 3288 movw r2, #5000 @ 0x1388
|
|
800448a: 4293 cmp r3, r2
|
|
800448c: d901 bls.n 8004492 <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800448e: 2303 movs r3, #3
|
|
8004490: e04f b.n 8004532 <HAL_RCC_ClockConfig+0x1ae>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8004492: 4b2b ldr r3, [pc, #172] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004494: 689b ldr r3, [r3, #8]
|
|
8004496: f003 020c and.w r2, r3, #12
|
|
800449a: 687b ldr r3, [r7, #4]
|
|
800449c: 685b ldr r3, [r3, #4]
|
|
800449e: 009b lsls r3, r3, #2
|
|
80044a0: 429a cmp r2, r3
|
|
80044a2: d1eb bne.n 800447c <HAL_RCC_ClockConfig+0xf8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
80044a4: 4b25 ldr r3, [pc, #148] @ (800453c <HAL_RCC_ClockConfig+0x1b8>)
|
|
80044a6: 681b ldr r3, [r3, #0]
|
|
80044a8: f003 030f and.w r3, r3, #15
|
|
80044ac: 683a ldr r2, [r7, #0]
|
|
80044ae: 429a cmp r2, r3
|
|
80044b0: d20c bcs.n 80044cc <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80044b2: 4b22 ldr r3, [pc, #136] @ (800453c <HAL_RCC_ClockConfig+0x1b8>)
|
|
80044b4: 683a ldr r2, [r7, #0]
|
|
80044b6: b2d2 uxtb r2, r2
|
|
80044b8: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80044ba: 4b20 ldr r3, [pc, #128] @ (800453c <HAL_RCC_ClockConfig+0x1b8>)
|
|
80044bc: 681b ldr r3, [r3, #0]
|
|
80044be: f003 030f and.w r3, r3, #15
|
|
80044c2: 683a ldr r2, [r7, #0]
|
|
80044c4: 429a cmp r2, r3
|
|
80044c6: d001 beq.n 80044cc <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
return HAL_ERROR;
|
|
80044c8: 2301 movs r3, #1
|
|
80044ca: e032 b.n 8004532 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
80044cc: 687b ldr r3, [r7, #4]
|
|
80044ce: 681b ldr r3, [r3, #0]
|
|
80044d0: f003 0304 and.w r3, r3, #4
|
|
80044d4: 2b00 cmp r3, #0
|
|
80044d6: d008 beq.n 80044ea <HAL_RCC_ClockConfig+0x166>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
80044d8: 4b19 ldr r3, [pc, #100] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80044da: 689b ldr r3, [r3, #8]
|
|
80044dc: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
|
|
80044e0: 687b ldr r3, [r7, #4]
|
|
80044e2: 68db ldr r3, [r3, #12]
|
|
80044e4: 4916 ldr r1, [pc, #88] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80044e6: 4313 orrs r3, r2
|
|
80044e8: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
80044ea: 687b ldr r3, [r7, #4]
|
|
80044ec: 681b ldr r3, [r3, #0]
|
|
80044ee: f003 0308 and.w r3, r3, #8
|
|
80044f2: 2b00 cmp r3, #0
|
|
80044f4: d009 beq.n 800450a <HAL_RCC_ClockConfig+0x186>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
80044f6: 4b12 ldr r3, [pc, #72] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
80044f8: 689b ldr r3, [r3, #8]
|
|
80044fa: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
80044fe: 687b ldr r3, [r7, #4]
|
|
8004500: 691b ldr r3, [r3, #16]
|
|
8004502: 00db lsls r3, r3, #3
|
|
8004504: 490e ldr r1, [pc, #56] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004506: 4313 orrs r3, r2
|
|
8004508: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
800450a: f000 fb7f bl 8004c0c <HAL_RCC_GetSysClockFreq>
|
|
800450e: 4602 mov r2, r0
|
|
8004510: 4b0b ldr r3, [pc, #44] @ (8004540 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004512: 689b ldr r3, [r3, #8]
|
|
8004514: 091b lsrs r3, r3, #4
|
|
8004516: f003 030f and.w r3, r3, #15
|
|
800451a: 490a ldr r1, [pc, #40] @ (8004544 <HAL_RCC_ClockConfig+0x1c0>)
|
|
800451c: 5ccb ldrb r3, [r1, r3]
|
|
800451e: fa22 f303 lsr.w r3, r2, r3
|
|
8004522: 4a09 ldr r2, [pc, #36] @ (8004548 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004524: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings */
|
|
HAL_InitTick(uwTickPrio);
|
|
8004526: 4b09 ldr r3, [pc, #36] @ (800454c <HAL_RCC_ClockConfig+0x1c8>)
|
|
8004528: 681b ldr r3, [r3, #0]
|
|
800452a: 4618 mov r0, r3
|
|
800452c: f7fd fc12 bl 8001d54 <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
8004530: 2300 movs r3, #0
|
|
}
|
|
8004532: 4618 mov r0, r3
|
|
8004534: 3710 adds r7, #16
|
|
8004536: 46bd mov sp, r7
|
|
8004538: bd80 pop {r7, pc}
|
|
800453a: bf00 nop
|
|
800453c: 40023c00 .word 0x40023c00
|
|
8004540: 40023800 .word 0x40023800
|
|
8004544: 0800af08 .word 0x0800af08
|
|
8004548: 20000090 .word 0x20000090
|
|
800454c: 20000094 .word 0x20000094
|
|
|
|
08004550 <HAL_RCC_GetHCLKFreq>:
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8004550: b480 push {r7}
|
|
8004552: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
8004554: 4b03 ldr r3, [pc, #12] @ (8004564 <HAL_RCC_GetHCLKFreq+0x14>)
|
|
8004556: 681b ldr r3, [r3, #0]
|
|
}
|
|
8004558: 4618 mov r0, r3
|
|
800455a: 46bd mov sp, r7
|
|
800455c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004560: 4770 bx lr
|
|
8004562: bf00 nop
|
|
8004564: 20000090 .word 0x20000090
|
|
|
|
08004568 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
8004568: b580 push {r7, lr}
|
|
800456a: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
800456c: f7ff fff0 bl 8004550 <HAL_RCC_GetHCLKFreq>
|
|
8004570: 4602 mov r2, r0
|
|
8004572: 4b05 ldr r3, [pc, #20] @ (8004588 <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
8004574: 689b ldr r3, [r3, #8]
|
|
8004576: 0a9b lsrs r3, r3, #10
|
|
8004578: f003 0307 and.w r3, r3, #7
|
|
800457c: 4903 ldr r1, [pc, #12] @ (800458c <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
800457e: 5ccb ldrb r3, [r1, r3]
|
|
8004580: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
8004584: 4618 mov r0, r3
|
|
8004586: bd80 pop {r7, pc}
|
|
8004588: 40023800 .word 0x40023800
|
|
800458c: 0800af18 .word 0x0800af18
|
|
|
|
08004590 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
8004590: b580 push {r7, lr}
|
|
8004592: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
8004594: f7ff ffdc bl 8004550 <HAL_RCC_GetHCLKFreq>
|
|
8004598: 4602 mov r2, r0
|
|
800459a: 4b05 ldr r3, [pc, #20] @ (80045b0 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
800459c: 689b ldr r3, [r3, #8]
|
|
800459e: 0b5b lsrs r3, r3, #13
|
|
80045a0: f003 0307 and.w r3, r3, #7
|
|
80045a4: 4903 ldr r1, [pc, #12] @ (80045b4 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
80045a6: 5ccb ldrb r3, [r1, r3]
|
|
80045a8: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80045ac: 4618 mov r0, r3
|
|
80045ae: bd80 pop {r7, pc}
|
|
80045b0: 40023800 .word 0x40023800
|
|
80045b4: 0800af18 .word 0x0800af18
|
|
|
|
080045b8 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the backup registers) and RCC_BDCR register are set to their reset values.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
80045b8: b580 push {r7, lr}
|
|
80045ba: b08c sub sp, #48 @ 0x30
|
|
80045bc: af00 add r7, sp, #0
|
|
80045be: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
80045c0: 2300 movs r3, #0
|
|
80045c2: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t tmpreg1 = 0U;
|
|
80045c4: 2300 movs r3, #0
|
|
80045c6: 623b str r3, [r7, #32]
|
|
uint32_t plli2sp = 0U;
|
|
80045c8: 2300 movs r3, #0
|
|
80045ca: 61fb str r3, [r7, #28]
|
|
uint32_t plli2sq = 0U;
|
|
80045cc: 2300 movs r3, #0
|
|
80045ce: 61bb str r3, [r7, #24]
|
|
uint32_t plli2sr = 0U;
|
|
80045d0: 2300 movs r3, #0
|
|
80045d2: 617b str r3, [r7, #20]
|
|
uint32_t pllsaip = 0U;
|
|
80045d4: 2300 movs r3, #0
|
|
80045d6: 613b str r3, [r7, #16]
|
|
uint32_t pllsaiq = 0U;
|
|
80045d8: 2300 movs r3, #0
|
|
80045da: 60fb str r3, [r7, #12]
|
|
uint32_t plli2sused = 0U;
|
|
80045dc: 2300 movs r3, #0
|
|
80045de: 62fb str r3, [r7, #44] @ 0x2c
|
|
uint32_t pllsaiused = 0U;
|
|
80045e0: 2300 movs r3, #0
|
|
80045e2: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Check the peripheral clock selection parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*------------------------ I2S APB1 configuration --------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
|
|
80045e4: 687b ldr r3, [r7, #4]
|
|
80045e6: 681b ldr r3, [r3, #0]
|
|
80045e8: f003 0301 and.w r3, r3, #1
|
|
80045ec: 2b00 cmp r3, #0
|
|
80045ee: d010 beq.n 8004612 <HAL_RCCEx_PeriphCLKConfig+0x5a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
|
|
|
|
/* Configure I2S Clock source */
|
|
__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
|
|
80045f0: 4b6f ldr r3, [pc, #444] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80045f2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80045f6: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000
|
|
80045fa: 687b ldr r3, [r7, #4]
|
|
80045fc: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80045fe: 496c ldr r1, [pc, #432] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004600: 4313 orrs r3, r2
|
|
8004602: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for I2S */
|
|
if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
|
|
8004606: 687b ldr r3, [r7, #4]
|
|
8004608: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800460a: 2b00 cmp r3, #0
|
|
800460c: d101 bne.n 8004612 <HAL_RCCEx_PeriphCLKConfig+0x5a>
|
|
{
|
|
plli2sused = 1U;
|
|
800460e: 2301 movs r3, #1
|
|
8004610: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- I2S APB2 configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
|
|
8004612: 687b ldr r3, [r7, #4]
|
|
8004614: 681b ldr r3, [r3, #0]
|
|
8004616: f003 0302 and.w r3, r3, #2
|
|
800461a: 2b00 cmp r3, #0
|
|
800461c: d010 beq.n 8004640 <HAL_RCCEx_PeriphCLKConfig+0x88>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
|
|
|
|
/* Configure I2S Clock source */
|
|
__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
|
|
800461e: 4b64 ldr r3, [pc, #400] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004620: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8004624: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000
|
|
8004628: 687b ldr r3, [r7, #4]
|
|
800462a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800462c: 4960 ldr r1, [pc, #384] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800462e: 4313 orrs r3, r2
|
|
8004630: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for I2S */
|
|
if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
|
|
8004634: 687b ldr r3, [r7, #4]
|
|
8004636: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8004638: 2b00 cmp r3, #0
|
|
800463a: d101 bne.n 8004640 <HAL_RCCEx_PeriphCLKConfig+0x88>
|
|
{
|
|
plli2sused = 1U;
|
|
800463c: 2301 movs r3, #1
|
|
800463e: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*--------------------------- SAI1 configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
|
|
8004640: 687b ldr r3, [r7, #4]
|
|
8004642: 681b ldr r3, [r3, #0]
|
|
8004644: f003 0304 and.w r3, r3, #4
|
|
8004648: 2b00 cmp r3, #0
|
|
800464a: d017 beq.n 800467c <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
/* Configure SAI1 Clock source */
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
800464c: 4b58 ldr r3, [pc, #352] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800464e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8004652: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
8004656: 687b ldr r3, [r7, #4]
|
|
8004658: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800465a: 4955 ldr r1, [pc, #340] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800465c: 4313 orrs r3, r2
|
|
800465e: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
|
|
8004662: 687b ldr r3, [r7, #4]
|
|
8004664: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8004666: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
800466a: d101 bne.n 8004670 <HAL_RCCEx_PeriphCLKConfig+0xb8>
|
|
{
|
|
plli2sused = 1U;
|
|
800466c: 2301 movs r3, #1
|
|
800466e: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
/* Enable the PLLSAI when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
|
|
8004670: 687b ldr r3, [r7, #4]
|
|
8004672: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8004674: 2b00 cmp r3, #0
|
|
8004676: d101 bne.n 800467c <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|
{
|
|
pllsaiused = 1U;
|
|
8004678: 2301 movs r3, #1
|
|
800467a: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*-------------------------- SAI2 configuration ----------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
|
|
800467c: 687b ldr r3, [r7, #4]
|
|
800467e: 681b ldr r3, [r3, #0]
|
|
8004680: f003 0308 and.w r3, r3, #8
|
|
8004684: 2b00 cmp r3, #0
|
|
8004686: d017 beq.n 80046b8 <HAL_RCCEx_PeriphCLKConfig+0x100>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
|
|
|
|
/* Configure SAI2 Clock source */
|
|
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
|
|
8004688: 4b49 ldr r3, [pc, #292] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800468a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
800468e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
8004692: 687b ldr r3, [r7, #4]
|
|
8004694: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8004696: 4946 ldr r1, [pc, #280] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004698: 4313 orrs r3, r2
|
|
800469a: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
|
|
/* Enable the PLLI2S when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
|
|
800469e: 687b ldr r3, [r7, #4]
|
|
80046a0: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80046a2: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80046a6: d101 bne.n 80046ac <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
{
|
|
plli2sused = 1U;
|
|
80046a8: 2301 movs r3, #1
|
|
80046aa: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
/* Enable the PLLSAI when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
|
|
80046ac: 687b ldr r3, [r7, #4]
|
|
80046ae: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80046b0: 2b00 cmp r3, #0
|
|
80046b2: d101 bne.n 80046b8 <HAL_RCCEx_PeriphCLKConfig+0x100>
|
|
{
|
|
pllsaiused = 1U;
|
|
80046b4: 2301 movs r3, #1
|
|
80046b6: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- RTC configuration --------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
|
80046b8: 687b ldr r3, [r7, #4]
|
|
80046ba: 681b ldr r3, [r3, #0]
|
|
80046bc: f003 0320 and.w r3, r3, #32
|
|
80046c0: 2b00 cmp r3, #0
|
|
80046c2: f000 808a beq.w 80047da <HAL_RCCEx_PeriphCLKConfig+0x222>
|
|
{
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80046c6: 2300 movs r3, #0
|
|
80046c8: 60bb str r3, [r7, #8]
|
|
80046ca: 4b39 ldr r3, [pc, #228] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80046cc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80046ce: 4a38 ldr r2, [pc, #224] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80046d0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80046d4: 6413 str r3, [r2, #64] @ 0x40
|
|
80046d6: 4b36 ldr r3, [pc, #216] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80046d8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80046da: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80046de: 60bb str r3, [r7, #8]
|
|
80046e0: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Enable write access to Backup domain */
|
|
PWR->CR |= PWR_CR_DBP;
|
|
80046e2: 4b34 ldr r3, [pc, #208] @ (80047b4 <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
80046e4: 681b ldr r3, [r3, #0]
|
|
80046e6: 4a33 ldr r2, [pc, #204] @ (80047b4 <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
80046e8: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80046ec: 6013 str r3, [r2, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80046ee: f7fd fb75 bl 8001ddc <HAL_GetTick>
|
|
80046f2: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
80046f4: e008 b.n 8004708 <HAL_RCCEx_PeriphCLKConfig+0x150>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
80046f6: f7fd fb71 bl 8001ddc <HAL_GetTick>
|
|
80046fa: 4602 mov r2, r0
|
|
80046fc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80046fe: 1ad3 subs r3, r2, r3
|
|
8004700: 2b02 cmp r3, #2
|
|
8004702: d901 bls.n 8004708 <HAL_RCCEx_PeriphCLKConfig+0x150>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004704: 2303 movs r3, #3
|
|
8004706: e278 b.n 8004bfa <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
8004708: 4b2a ldr r3, [pc, #168] @ (80047b4 <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
800470a: 681b ldr r3, [r3, #0]
|
|
800470c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004710: 2b00 cmp r3, #0
|
|
8004712: d0f0 beq.n 80046f6 <HAL_RCCEx_PeriphCLKConfig+0x13e>
|
|
}
|
|
}
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
8004714: 4b26 ldr r3, [pc, #152] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004716: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004718: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
800471c: 623b str r3, [r7, #32]
|
|
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
800471e: 6a3b ldr r3, [r7, #32]
|
|
8004720: 2b00 cmp r3, #0
|
|
8004722: d02f beq.n 8004784 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
8004724: 687b ldr r3, [r7, #4]
|
|
8004726: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004728: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
800472c: 6a3a ldr r2, [r7, #32]
|
|
800472e: 429a cmp r2, r3
|
|
8004730: d028 beq.n 8004784 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
8004732: 4b1f ldr r3, [pc, #124] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004734: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004736: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800473a: 623b str r3, [r7, #32]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
800473c: 4b1e ldr r3, [pc, #120] @ (80047b8 <HAL_RCCEx_PeriphCLKConfig+0x200>)
|
|
800473e: 2201 movs r2, #1
|
|
8004740: 601a str r2, [r3, #0]
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8004742: 4b1d ldr r3, [pc, #116] @ (80047b8 <HAL_RCCEx_PeriphCLKConfig+0x200>)
|
|
8004744: 2200 movs r2, #0
|
|
8004746: 601a str r2, [r3, #0]
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpreg1;
|
|
8004748: 4a19 ldr r2, [pc, #100] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800474a: 6a3b ldr r3, [r7, #32]
|
|
800474c: 6713 str r3, [r2, #112] @ 0x70
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
|
|
800474e: 4b18 ldr r3, [pc, #96] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004750: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004752: f003 0301 and.w r3, r3, #1
|
|
8004756: 2b01 cmp r3, #1
|
|
8004758: d114 bne.n 8004784 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800475a: f7fd fb3f bl 8001ddc <HAL_GetTick>
|
|
800475e: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8004760: e00a b.n 8004778 <HAL_RCCEx_PeriphCLKConfig+0x1c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8004762: f7fd fb3b bl 8001ddc <HAL_GetTick>
|
|
8004766: 4602 mov r2, r0
|
|
8004768: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800476a: 1ad3 subs r3, r2, r3
|
|
800476c: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004770: 4293 cmp r3, r2
|
|
8004772: d901 bls.n 8004778 <HAL_RCCEx_PeriphCLKConfig+0x1c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004774: 2303 movs r3, #3
|
|
8004776: e240 b.n 8004bfa <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8004778: 4b0d ldr r3, [pc, #52] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800477a: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800477c: f003 0302 and.w r3, r3, #2
|
|
8004780: 2b00 cmp r3, #0
|
|
8004782: d0ee beq.n 8004762 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
8004784: 687b ldr r3, [r7, #4]
|
|
8004786: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004788: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
800478c: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
8004790: d114 bne.n 80047bc <HAL_RCCEx_PeriphCLKConfig+0x204>
|
|
8004792: 4b07 ldr r3, [pc, #28] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004794: 689b ldr r3, [r3, #8]
|
|
8004796: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
|
|
800479a: 687b ldr r3, [r7, #4]
|
|
800479c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800479e: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000
|
|
80047a2: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80047a6: 4902 ldr r1, [pc, #8] @ (80047b0 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80047a8: 4313 orrs r3, r2
|
|
80047aa: 608b str r3, [r1, #8]
|
|
80047ac: e00c b.n 80047c8 <HAL_RCCEx_PeriphCLKConfig+0x210>
|
|
80047ae: bf00 nop
|
|
80047b0: 40023800 .word 0x40023800
|
|
80047b4: 40007000 .word 0x40007000
|
|
80047b8: 42470e40 .word 0x42470e40
|
|
80047bc: 4b4a ldr r3, [pc, #296] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80047be: 689b ldr r3, [r3, #8]
|
|
80047c0: 4a49 ldr r2, [pc, #292] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80047c2: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
|
|
80047c6: 6093 str r3, [r2, #8]
|
|
80047c8: 4b47 ldr r3, [pc, #284] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80047ca: 6f1a ldr r2, [r3, #112] @ 0x70
|
|
80047cc: 687b ldr r3, [r7, #4]
|
|
80047ce: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80047d0: f3c3 030b ubfx r3, r3, #0, #12
|
|
80047d4: 4944 ldr r1, [pc, #272] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80047d6: 4313 orrs r3, r2
|
|
80047d8: 670b str r3, [r1, #112] @ 0x70
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- TIM configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
|
|
80047da: 687b ldr r3, [r7, #4]
|
|
80047dc: 681b ldr r3, [r3, #0]
|
|
80047de: f003 0310 and.w r3, r3, #16
|
|
80047e2: 2b00 cmp r3, #0
|
|
80047e4: d004 beq.n 80047f0 <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
{
|
|
/* Configure Timer Prescaler */
|
|
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
|
|
80047e6: 687b ldr r3, [r7, #4]
|
|
80047e8: f893 2058 ldrb.w r2, [r3, #88] @ 0x58
|
|
80047ec: 4b3f ldr r3, [pc, #252] @ (80048ec <HAL_RCCEx_PeriphCLKConfig+0x334>)
|
|
80047ee: 601a str r2, [r3, #0]
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- FMPI2C1 Configuration -----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
|
|
80047f0: 687b ldr r3, [r7, #4]
|
|
80047f2: 681b ldr r3, [r3, #0]
|
|
80047f4: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80047f8: 2b00 cmp r3, #0
|
|
80047fa: d00a beq.n 8004812 <HAL_RCCEx_PeriphCLKConfig+0x25a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
|
|
|
|
/* Configure the FMPI2C1 clock source */
|
|
__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
|
|
80047fc: 4b3a ldr r3, [pc, #232] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80047fe: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8004802: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
8004806: 687b ldr r3, [r7, #4]
|
|
8004808: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800480a: 4937 ldr r1, [pc, #220] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
800480c: 4313 orrs r3, r2
|
|
800480e: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*------------------------------ CEC Configuration -------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
|
|
8004812: 687b ldr r3, [r7, #4]
|
|
8004814: 681b ldr r3, [r3, #0]
|
|
8004816: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800481a: 2b00 cmp r3, #0
|
|
800481c: d00a beq.n 8004834 <HAL_RCCEx_PeriphCLKConfig+0x27c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
|
|
|
|
/* Configure the CEC clock source */
|
|
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
|
|
800481e: 4b32 ldr r3, [pc, #200] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8004820: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8004824: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000
|
|
8004828: 687b ldr r3, [r7, #4]
|
|
800482a: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800482c: 492e ldr r1, [pc, #184] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
800482e: 4313 orrs r3, r2
|
|
8004830: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- CLK48 Configuration ------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
|
|
8004834: 687b ldr r3, [r7, #4]
|
|
8004836: 681b ldr r3, [r3, #0]
|
|
8004838: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800483c: 2b00 cmp r3, #0
|
|
800483e: d011 beq.n 8004864 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
|
|
|
|
/* Configure the CLK48 clock source */
|
|
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
|
|
8004840: 4b29 ldr r3, [pc, #164] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8004842: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8004846: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000
|
|
800484a: 687b ldr r3, [r7, #4]
|
|
800484c: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800484e: 4926 ldr r1, [pc, #152] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8004850: 4313 orrs r3, r2
|
|
8004852: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
|
|
/* Enable the PLLSAI when it's used as clock source for CLK48 */
|
|
if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
|
|
8004856: 687b ldr r3, [r7, #4]
|
|
8004858: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800485a: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
800485e: d101 bne.n 8004864 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
pllsaiused = 1U;
|
|
8004860: 2301 movs r3, #1
|
|
8004862: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- SDIO Configuration -------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
|
|
8004864: 687b ldr r3, [r7, #4]
|
|
8004866: 681b ldr r3, [r3, #0]
|
|
8004868: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
800486c: 2b00 cmp r3, #0
|
|
800486e: d00a beq.n 8004886 <HAL_RCCEx_PeriphCLKConfig+0x2ce>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
|
|
|
|
/* Configure the SDIO clock source */
|
|
__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
|
|
8004870: 4b1d ldr r3, [pc, #116] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8004872: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8004876: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
|
|
800487a: 687b ldr r3, [r7, #4]
|
|
800487c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800487e: 491a ldr r1, [pc, #104] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8004880: 4313 orrs r3, r2
|
|
8004882: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*------------------------------ SPDIFRX Configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
|
8004886: 687b ldr r3, [r7, #4]
|
|
8004888: 681b ldr r3, [r3, #0]
|
|
800488a: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800488e: 2b00 cmp r3, #0
|
|
8004890: d011 beq.n 80048b6 <HAL_RCCEx_PeriphCLKConfig+0x2fe>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
|
|
|
|
/* Configure the SPDIFRX clock source */
|
|
__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
|
|
8004892: 4b15 ldr r3, [pc, #84] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8004894: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8004898: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
|
|
800489c: 687b ldr r3, [r7, #4]
|
|
800489e: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80048a0: 4911 ldr r1, [pc, #68] @ (80048e8 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80048a2: 4313 orrs r3, r2
|
|
80048a4: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
|
|
if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
|
|
80048a8: 687b ldr r3, [r7, #4]
|
|
80048aa: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80048ac: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
80048b0: d101 bne.n 80048b6 <HAL_RCCEx_PeriphCLKConfig+0x2fe>
|
|
{
|
|
plli2sused = 1U;
|
|
80048b2: 2301 movs r3, #1
|
|
80048b4: 62fb str r3, [r7, #44] @ 0x2c
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- PLLI2S Configuration ------------------------*/
|
|
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
|
|
I2S on APB2 or SPDIFRX */
|
|
if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
|
|
80048b6: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80048b8: 2b01 cmp r3, #1
|
|
80048ba: d005 beq.n 80048c8 <HAL_RCCEx_PeriphCLKConfig+0x310>
|
|
80048bc: 687b ldr r3, [r7, #4]
|
|
80048be: 681b ldr r3, [r3, #0]
|
|
80048c0: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
80048c4: f040 80ff bne.w 8004ac6 <HAL_RCCEx_PeriphCLKConfig+0x50e>
|
|
{
|
|
/* Disable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_DISABLE();
|
|
80048c8: 4b09 ldr r3, [pc, #36] @ (80048f0 <HAL_RCCEx_PeriphCLKConfig+0x338>)
|
|
80048ca: 2200 movs r2, #0
|
|
80048cc: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80048ce: f7fd fa85 bl 8001ddc <HAL_GetTick>
|
|
80048d2: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLI2S is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
80048d4: e00e b.n 80048f4 <HAL_RCCEx_PeriphCLKConfig+0x33c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
80048d6: f7fd fa81 bl 8001ddc <HAL_GetTick>
|
|
80048da: 4602 mov r2, r0
|
|
80048dc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80048de: 1ad3 subs r3, r2, r3
|
|
80048e0: 2b02 cmp r3, #2
|
|
80048e2: d907 bls.n 80048f4 <HAL_RCCEx_PeriphCLKConfig+0x33c>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
80048e4: 2303 movs r3, #3
|
|
80048e6: e188 b.n 8004bfa <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
80048e8: 40023800 .word 0x40023800
|
|
80048ec: 424711e0 .word 0x424711e0
|
|
80048f0: 42470068 .word 0x42470068
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
80048f4: 4b7e ldr r3, [pc, #504] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80048f6: 681b ldr r3, [r3, #0]
|
|
80048f8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
80048fc: 2b00 cmp r3, #0
|
|
80048fe: d1ea bne.n 80048d6 <HAL_RCCEx_PeriphCLKConfig+0x31e>
|
|
/* check for common PLLI2S Parameters */
|
|
assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
|
|
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
|
|
|
/*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1)
|
|
8004900: 687b ldr r3, [r7, #4]
|
|
8004902: 681b ldr r3, [r3, #0]
|
|
8004904: f003 0301 and.w r3, r3, #1
|
|
8004908: 2b00 cmp r3, #0
|
|
800490a: d003 beq.n 8004914 <HAL_RCCEx_PeriphCLKConfig+0x35c>
|
|
&& (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
|
|
800490c: 687b ldr r3, [r7, #4]
|
|
800490e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004910: 2b00 cmp r3, #0
|
|
8004912: d009 beq.n 8004928 <HAL_RCCEx_PeriphCLKConfig+0x370>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
|
|
8004914: 687b ldr r3, [r7, #4]
|
|
8004916: 681b ldr r3, [r3, #0]
|
|
8004918: f003 0302 and.w r3, r3, #2
|
|
&& (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
|
|
800491c: 2b00 cmp r3, #0
|
|
800491e: d028 beq.n 8004972 <HAL_RCCEx_PeriphCLKConfig+0x3ba>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
|
|
8004920: 687b ldr r3, [r7, #4]
|
|
8004922: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8004924: 2b00 cmp r3, #0
|
|
8004926: d124 bne.n 8004972 <HAL_RCCEx_PeriphCLKConfig+0x3ba>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
|
|
/* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
|
|
plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
8004928: 4b71 ldr r3, [pc, #452] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800492a: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
800492e: 0c1b lsrs r3, r3, #16
|
|
8004930: f003 0303 and.w r3, r3, #3
|
|
8004934: 3301 adds r3, #1
|
|
8004936: 005b lsls r3, r3, #1
|
|
8004938: 61fb str r3, [r7, #28]
|
|
plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
|
|
800493a: 4b6d ldr r3, [pc, #436] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800493c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8004940: 0e1b lsrs r3, r3, #24
|
|
8004942: f003 030f and.w r3, r3, #15
|
|
8004946: 61bb str r3, [r7, #24]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq,
|
|
8004948: 687b ldr r3, [r7, #4]
|
|
800494a: 685a ldr r2, [r3, #4]
|
|
800494c: 687b ldr r3, [r7, #4]
|
|
800494e: 689b ldr r3, [r3, #8]
|
|
8004950: 019b lsls r3, r3, #6
|
|
8004952: 431a orrs r2, r3
|
|
8004954: 69fb ldr r3, [r7, #28]
|
|
8004956: 085b lsrs r3, r3, #1
|
|
8004958: 3b01 subs r3, #1
|
|
800495a: 041b lsls r3, r3, #16
|
|
800495c: 431a orrs r2, r3
|
|
800495e: 69bb ldr r3, [r7, #24]
|
|
8004960: 061b lsls r3, r3, #24
|
|
8004962: 431a orrs r2, r3
|
|
8004964: 687b ldr r3, [r7, #4]
|
|
8004966: 695b ldr r3, [r3, #20]
|
|
8004968: 071b lsls r3, r3, #28
|
|
800496a: 4961 ldr r1, [pc, #388] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800496c: 4313 orrs r3, r2
|
|
800496e: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SR);
|
|
}
|
|
|
|
/*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
|
|
8004972: 687b ldr r3, [r7, #4]
|
|
8004974: 681b ldr r3, [r3, #0]
|
|
8004976: f003 0304 and.w r3, r3, #4
|
|
800497a: 2b00 cmp r3, #0
|
|
800497c: d004 beq.n 8004988 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
|
800497e: 687b ldr r3, [r7, #4]
|
|
8004980: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8004982: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8004986: d00a beq.n 800499e <HAL_RCCEx_PeriphCLKConfig+0x3e6>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
|
8004988: 687b ldr r3, [r7, #4]
|
|
800498a: 681b ldr r3, [r3, #0]
|
|
800498c: f003 0308 and.w r3, r3, #8
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
|
8004990: 2b00 cmp r3, #0
|
|
8004992: d035 beq.n 8004a00 <HAL_RCCEx_PeriphCLKConfig+0x448>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
|
8004994: 687b ldr r3, [r7, #4]
|
|
8004996: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8004998: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
800499c: d130 bne.n 8004a00 <HAL_RCCEx_PeriphCLKConfig+0x448>
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
/* Check for PLLI2S/DIVQ parameters */
|
|
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
|
|
|
|
/* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
|
|
plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
800499e: 4b54 ldr r3, [pc, #336] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80049a0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80049a4: 0c1b lsrs r3, r3, #16
|
|
80049a6: f003 0303 and.w r3, r3, #3
|
|
80049aa: 3301 adds r3, #1
|
|
80049ac: 005b lsls r3, r3, #1
|
|
80049ae: 61fb str r3, [r7, #28]
|
|
plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
80049b0: 4b4f ldr r3, [pc, #316] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80049b2: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80049b6: 0f1b lsrs r3, r3, #28
|
|
80049b8: f003 0307 and.w r3, r3, #7
|
|
80049bc: 617b str r3, [r7, #20]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
|
|
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
|
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp,
|
|
80049be: 687b ldr r3, [r7, #4]
|
|
80049c0: 685a ldr r2, [r3, #4]
|
|
80049c2: 687b ldr r3, [r7, #4]
|
|
80049c4: 689b ldr r3, [r3, #8]
|
|
80049c6: 019b lsls r3, r3, #6
|
|
80049c8: 431a orrs r2, r3
|
|
80049ca: 69fb ldr r3, [r7, #28]
|
|
80049cc: 085b lsrs r3, r3, #1
|
|
80049ce: 3b01 subs r3, #1
|
|
80049d0: 041b lsls r3, r3, #16
|
|
80049d2: 431a orrs r2, r3
|
|
80049d4: 687b ldr r3, [r7, #4]
|
|
80049d6: 691b ldr r3, [r3, #16]
|
|
80049d8: 061b lsls r3, r3, #24
|
|
80049da: 431a orrs r2, r3
|
|
80049dc: 697b ldr r3, [r7, #20]
|
|
80049de: 071b lsls r3, r3, #28
|
|
80049e0: 4943 ldr r1, [pc, #268] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80049e2: 4313 orrs r3, r2
|
|
80049e4: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
|
|
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
|
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
|
|
80049e8: 4b41 ldr r3, [pc, #260] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80049ea: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80049ee: f023 021f bic.w r2, r3, #31
|
|
80049f2: 687b ldr r3, [r7, #4]
|
|
80049f4: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80049f6: 3b01 subs r3, #1
|
|
80049f8: 493d ldr r1, [pc, #244] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80049fa: 4313 orrs r3, r2
|
|
80049fc: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
|
8004a00: 687b ldr r3, [r7, #4]
|
|
8004a02: 681b ldr r3, [r3, #0]
|
|
8004a04: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8004a08: 2b00 cmp r3, #0
|
|
8004a0a: d029 beq.n 8004a60 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
|
|
&& (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
|
|
8004a0c: 687b ldr r3, [r7, #4]
|
|
8004a0e: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8004a10: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8004a14: d124 bne.n 8004a60 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
|
|
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
|
plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
8004a16: 4b36 ldr r3, [pc, #216] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004a18: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8004a1c: 0c1b lsrs r3, r3, #16
|
|
8004a1e: f003 0303 and.w r3, r3, #3
|
|
8004a22: 3301 adds r3, #1
|
|
8004a24: 005b lsls r3, r3, #1
|
|
8004a26: 61bb str r3, [r7, #24]
|
|
plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
8004a28: 4b31 ldr r3, [pc, #196] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004a2a: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8004a2e: 0f1b lsrs r3, r3, #28
|
|
8004a30: f003 0307 and.w r3, r3, #7
|
|
8004a34: 617b str r3, [r7, #20]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP,
|
|
8004a36: 687b ldr r3, [r7, #4]
|
|
8004a38: 685a ldr r2, [r3, #4]
|
|
8004a3a: 687b ldr r3, [r7, #4]
|
|
8004a3c: 689b ldr r3, [r3, #8]
|
|
8004a3e: 019b lsls r3, r3, #6
|
|
8004a40: 431a orrs r2, r3
|
|
8004a42: 687b ldr r3, [r7, #4]
|
|
8004a44: 68db ldr r3, [r3, #12]
|
|
8004a46: 085b lsrs r3, r3, #1
|
|
8004a48: 3b01 subs r3, #1
|
|
8004a4a: 041b lsls r3, r3, #16
|
|
8004a4c: 431a orrs r2, r3
|
|
8004a4e: 69bb ldr r3, [r7, #24]
|
|
8004a50: 061b lsls r3, r3, #24
|
|
8004a52: 431a orrs r2, r3
|
|
8004a54: 697b ldr r3, [r7, #20]
|
|
8004a56: 071b lsls r3, r3, #28
|
|
8004a58: 4925 ldr r1, [pc, #148] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004a5a: 4313 orrs r3, r2
|
|
8004a5c: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
plli2sq, plli2sr);
|
|
}
|
|
|
|
/*----------------- In Case of PLLI2S is just selected -----------------*/
|
|
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
|
|
8004a60: 687b ldr r3, [r7, #4]
|
|
8004a62: 681b ldr r3, [r3, #0]
|
|
8004a64: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8004a68: 2b00 cmp r3, #0
|
|
8004a6a: d016 beq.n 8004a9a <HAL_RCCEx_PeriphCLKConfig+0x4e2>
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP,
|
|
8004a6c: 687b ldr r3, [r7, #4]
|
|
8004a6e: 685a ldr r2, [r3, #4]
|
|
8004a70: 687b ldr r3, [r7, #4]
|
|
8004a72: 689b ldr r3, [r3, #8]
|
|
8004a74: 019b lsls r3, r3, #6
|
|
8004a76: 431a orrs r2, r3
|
|
8004a78: 687b ldr r3, [r7, #4]
|
|
8004a7a: 68db ldr r3, [r3, #12]
|
|
8004a7c: 085b lsrs r3, r3, #1
|
|
8004a7e: 3b01 subs r3, #1
|
|
8004a80: 041b lsls r3, r3, #16
|
|
8004a82: 431a orrs r2, r3
|
|
8004a84: 687b ldr r3, [r7, #4]
|
|
8004a86: 691b ldr r3, [r3, #16]
|
|
8004a88: 061b lsls r3, r3, #24
|
|
8004a8a: 431a orrs r2, r3
|
|
8004a8c: 687b ldr r3, [r7, #4]
|
|
8004a8e: 695b ldr r3, [r3, #20]
|
|
8004a90: 071b lsls r3, r3, #28
|
|
8004a92: 4917 ldr r1, [pc, #92] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004a94: 4313 orrs r3, r2
|
|
8004a96: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
|
|
}
|
|
|
|
/* Enable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_ENABLE();
|
|
8004a9a: 4b16 ldr r3, [pc, #88] @ (8004af4 <HAL_RCCEx_PeriphCLKConfig+0x53c>)
|
|
8004a9c: 2201 movs r2, #1
|
|
8004a9e: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8004aa0: f7fd f99c bl 8001ddc <HAL_GetTick>
|
|
8004aa4: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLI2S is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
8004aa6: e008 b.n 8004aba <HAL_RCCEx_PeriphCLKConfig+0x502>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
8004aa8: f7fd f998 bl 8001ddc <HAL_GetTick>
|
|
8004aac: 4602 mov r2, r0
|
|
8004aae: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004ab0: 1ad3 subs r3, r2, r3
|
|
8004ab2: 2b02 cmp r3, #2
|
|
8004ab4: d901 bls.n 8004aba <HAL_RCCEx_PeriphCLKConfig+0x502>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8004ab6: 2303 movs r3, #3
|
|
8004ab8: e09f b.n 8004bfa <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
8004aba: 4b0d ldr r3, [pc, #52] @ (8004af0 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004abc: 681b ldr r3, [r3, #0]
|
|
8004abe: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8004ac2: 2b00 cmp r3, #0
|
|
8004ac4: d0f0 beq.n 8004aa8 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- PLLSAI Configuration -----------------------*/
|
|
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
|
|
if (pllsaiused == 1U)
|
|
8004ac6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8004ac8: 2b01 cmp r3, #1
|
|
8004aca: f040 8095 bne.w 8004bf8 <HAL_RCCEx_PeriphCLKConfig+0x640>
|
|
{
|
|
/* Disable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_DISABLE();
|
|
8004ace: 4b0a ldr r3, [pc, #40] @ (8004af8 <HAL_RCCEx_PeriphCLKConfig+0x540>)
|
|
8004ad0: 2200 movs r2, #0
|
|
8004ad2: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8004ad4: f7fd f982 bl 8001ddc <HAL_GetTick>
|
|
8004ad8: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLSAI is disabled */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
8004ada: e00f b.n 8004afc <HAL_RCCEx_PeriphCLKConfig+0x544>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
8004adc: f7fd f97e bl 8001ddc <HAL_GetTick>
|
|
8004ae0: 4602 mov r2, r0
|
|
8004ae2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004ae4: 1ad3 subs r3, r2, r3
|
|
8004ae6: 2b02 cmp r3, #2
|
|
8004ae8: d908 bls.n 8004afc <HAL_RCCEx_PeriphCLKConfig+0x544>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8004aea: 2303 movs r3, #3
|
|
8004aec: e085 b.n 8004bfa <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
8004aee: bf00 nop
|
|
8004af0: 40023800 .word 0x40023800
|
|
8004af4: 42470068 .word 0x42470068
|
|
8004af8: 42470070 .word 0x42470070
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
8004afc: 4b41 ldr r3, [pc, #260] @ (8004c04 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8004afe: 681b ldr r3, [r3, #0]
|
|
8004b00: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8004b04: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8004b08: d0e8 beq.n 8004adc <HAL_RCCEx_PeriphCLKConfig+0x524>
|
|
/* Check the PLLSAI division factors */
|
|
assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
|
|
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
|
|
|
|
/*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
|
|
8004b0a: 687b ldr r3, [r7, #4]
|
|
8004b0c: 681b ldr r3, [r3, #0]
|
|
8004b0e: f003 0304 and.w r3, r3, #4
|
|
8004b12: 2b00 cmp r3, #0
|
|
8004b14: d003 beq.n 8004b1e <HAL_RCCEx_PeriphCLKConfig+0x566>
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
|
|
8004b16: 687b ldr r3, [r7, #4]
|
|
8004b18: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8004b1a: 2b00 cmp r3, #0
|
|
8004b1c: d009 beq.n 8004b32 <HAL_RCCEx_PeriphCLKConfig+0x57a>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
|
8004b1e: 687b ldr r3, [r7, #4]
|
|
8004b20: 681b ldr r3, [r3, #0]
|
|
8004b22: f003 0308 and.w r3, r3, #8
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
|
|
8004b26: 2b00 cmp r3, #0
|
|
8004b28: d02b beq.n 8004b82 <HAL_RCCEx_PeriphCLKConfig+0x5ca>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
|
8004b2a: 687b ldr r3, [r7, #4]
|
|
8004b2c: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8004b2e: 2b00 cmp r3, #0
|
|
8004b30: d127 bne.n 8004b82 <HAL_RCCEx_PeriphCLKConfig+0x5ca>
|
|
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
|
|
/* check for PLLSAI/DIVQ Parameter */
|
|
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
|
|
|
|
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
|
|
pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
|
|
8004b32: 4b34 ldr r3, [pc, #208] @ (8004c04 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8004b34: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004b38: 0c1b lsrs r3, r3, #16
|
|
8004b3a: f003 0303 and.w r3, r3, #3
|
|
8004b3e: 3301 adds r3, #1
|
|
8004b40: 005b lsls r3, r3, #1
|
|
8004b42: 613b str r3, [r7, #16]
|
|
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
|
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip,
|
|
8004b44: 687b ldr r3, [r7, #4]
|
|
8004b46: 699a ldr r2, [r3, #24]
|
|
8004b48: 687b ldr r3, [r7, #4]
|
|
8004b4a: 69db ldr r3, [r3, #28]
|
|
8004b4c: 019b lsls r3, r3, #6
|
|
8004b4e: 431a orrs r2, r3
|
|
8004b50: 693b ldr r3, [r7, #16]
|
|
8004b52: 085b lsrs r3, r3, #1
|
|
8004b54: 3b01 subs r3, #1
|
|
8004b56: 041b lsls r3, r3, #16
|
|
8004b58: 431a orrs r2, r3
|
|
8004b5a: 687b ldr r3, [r7, #4]
|
|
8004b5c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004b5e: 061b lsls r3, r3, #24
|
|
8004b60: 4928 ldr r1, [pc, #160] @ (8004c04 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8004b62: 4313 orrs r3, r2
|
|
8004b64: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
|
|
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
|
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
|
|
8004b68: 4b26 ldr r3, [pc, #152] @ (8004c04 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8004b6a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8004b6e: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
|
|
8004b72: 687b ldr r3, [r7, #4]
|
|
8004b74: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004b76: 3b01 subs r3, #1
|
|
8004b78: 021b lsls r3, r3, #8
|
|
8004b7a: 4922 ldr r1, [pc, #136] @ (8004c04 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8004b7c: 4313 orrs r3, r2
|
|
8004b7e: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/
|
|
/* In Case of PLLI2S is selected as source clock for CLK48 */
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
|
|
8004b82: 687b ldr r3, [r7, #4]
|
|
8004b84: 681b ldr r3, [r3, #0]
|
|
8004b86: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004b8a: 2b00 cmp r3, #0
|
|
8004b8c: d01d beq.n 8004bca <HAL_RCCEx_PeriphCLKConfig+0x612>
|
|
&& (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
|
|
8004b8e: 687b ldr r3, [r7, #4]
|
|
8004b90: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8004b92: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8004b96: d118 bne.n 8004bca <HAL_RCCEx_PeriphCLKConfig+0x612>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
|
|
/* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
|
pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
|
|
8004b98: 4b1a ldr r3, [pc, #104] @ (8004c04 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8004b9a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004b9e: 0e1b lsrs r3, r3, #24
|
|
8004ba0: f003 030f and.w r3, r3, #15
|
|
8004ba4: 60fb str r3, [r7, #12]
|
|
/* Configure the PLLSAI division factors */
|
|
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
|
|
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP,
|
|
8004ba6: 687b ldr r3, [r7, #4]
|
|
8004ba8: 699a ldr r2, [r3, #24]
|
|
8004baa: 687b ldr r3, [r7, #4]
|
|
8004bac: 69db ldr r3, [r3, #28]
|
|
8004bae: 019b lsls r3, r3, #6
|
|
8004bb0: 431a orrs r2, r3
|
|
8004bb2: 687b ldr r3, [r7, #4]
|
|
8004bb4: 6a1b ldr r3, [r3, #32]
|
|
8004bb6: 085b lsrs r3, r3, #1
|
|
8004bb8: 3b01 subs r3, #1
|
|
8004bba: 041b lsls r3, r3, #16
|
|
8004bbc: 431a orrs r2, r3
|
|
8004bbe: 68fb ldr r3, [r7, #12]
|
|
8004bc0: 061b lsls r3, r3, #24
|
|
8004bc2: 4910 ldr r1, [pc, #64] @ (8004c04 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8004bc4: 4313 orrs r3, r2
|
|
8004bc6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
pllsaiq, 0U);
|
|
}
|
|
|
|
/* Enable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_ENABLE();
|
|
8004bca: 4b0f ldr r3, [pc, #60] @ (8004c08 <HAL_RCCEx_PeriphCLKConfig+0x650>)
|
|
8004bcc: 2201 movs r2, #1
|
|
8004bce: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8004bd0: f7fd f904 bl 8001ddc <HAL_GetTick>
|
|
8004bd4: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLSAI is ready */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
8004bd6: e008 b.n 8004bea <HAL_RCCEx_PeriphCLKConfig+0x632>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
8004bd8: f7fd f900 bl 8001ddc <HAL_GetTick>
|
|
8004bdc: 4602 mov r2, r0
|
|
8004bde: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004be0: 1ad3 subs r3, r2, r3
|
|
8004be2: 2b02 cmp r3, #2
|
|
8004be4: d901 bls.n 8004bea <HAL_RCCEx_PeriphCLKConfig+0x632>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8004be6: 2303 movs r3, #3
|
|
8004be8: e007 b.n 8004bfa <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
8004bea: 4b06 ldr r3, [pc, #24] @ (8004c04 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8004bec: 681b ldr r3, [r3, #0]
|
|
8004bee: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8004bf2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8004bf6: d1ef bne.n 8004bd8 <HAL_RCCEx_PeriphCLKConfig+0x620>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8004bf8: 2300 movs r3, #0
|
|
}
|
|
8004bfa: 4618 mov r0, r3
|
|
8004bfc: 3730 adds r7, #48 @ 0x30
|
|
8004bfe: 46bd mov sp, r7
|
|
8004c00: bd80 pop {r7, pc}
|
|
8004c02: bf00 nop
|
|
8004c04: 40023800 .word 0x40023800
|
|
8004c08: 42470070 .word 0x42470070
|
|
|
|
08004c0c <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8004c0c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8004c10: b0ae sub sp, #184 @ 0xb8
|
|
8004c12: af00 add r7, sp, #0
|
|
uint32_t pllm = 0U;
|
|
8004c14: 2300 movs r3, #0
|
|
8004c16: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
uint32_t pllvco = 0U;
|
|
8004c1a: 2300 movs r3, #0
|
|
8004c1c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
uint32_t pllp = 0U;
|
|
8004c20: 2300 movs r3, #0
|
|
8004c22: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
uint32_t pllr = 0U;
|
|
8004c26: 2300 movs r3, #0
|
|
8004c28: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
uint32_t sysclockfreq = 0U;
|
|
8004c2c: 2300 movs r3, #0
|
|
8004c2e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
8004c32: 4bcb ldr r3, [pc, #812] @ (8004f60 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004c34: 689b ldr r3, [r3, #8]
|
|
8004c36: f003 030c and.w r3, r3, #12
|
|
8004c3a: 2b0c cmp r3, #12
|
|
8004c3c: f200 8206 bhi.w 800504c <HAL_RCC_GetSysClockFreq+0x440>
|
|
8004c40: a201 add r2, pc, #4 @ (adr r2, 8004c48 <HAL_RCC_GetSysClockFreq+0x3c>)
|
|
8004c42: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8004c46: bf00 nop
|
|
8004c48: 08004c7d .word 0x08004c7d
|
|
8004c4c: 0800504d .word 0x0800504d
|
|
8004c50: 0800504d .word 0x0800504d
|
|
8004c54: 0800504d .word 0x0800504d
|
|
8004c58: 08004c85 .word 0x08004c85
|
|
8004c5c: 0800504d .word 0x0800504d
|
|
8004c60: 0800504d .word 0x0800504d
|
|
8004c64: 0800504d .word 0x0800504d
|
|
8004c68: 08004c8d .word 0x08004c8d
|
|
8004c6c: 0800504d .word 0x0800504d
|
|
8004c70: 0800504d .word 0x0800504d
|
|
8004c74: 0800504d .word 0x0800504d
|
|
8004c78: 08004e7d .word 0x08004e7d
|
|
{
|
|
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8004c7c: 4bb9 ldr r3, [pc, #740] @ (8004f64 <HAL_RCC_GetSysClockFreq+0x358>)
|
|
8004c7e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8004c82: e1e7 b.n 8005054 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8004c84: 4bb8 ldr r3, [pc, #736] @ (8004f68 <HAL_RCC_GetSysClockFreq+0x35c>)
|
|
8004c86: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8004c8a: e1e3 b.n 8005054 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLP */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
8004c8c: 4bb4 ldr r3, [pc, #720] @ (8004f60 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004c8e: 685b ldr r3, [r3, #4]
|
|
8004c90: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
8004c94: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
8004c98: 4bb1 ldr r3, [pc, #708] @ (8004f60 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004c9a: 685b ldr r3, [r3, #4]
|
|
8004c9c: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004ca0: 2b00 cmp r3, #0
|
|
8004ca2: d071 beq.n 8004d88 <HAL_RCC_GetSysClockFreq+0x17c>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8004ca4: 4bae ldr r3, [pc, #696] @ (8004f60 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004ca6: 685b ldr r3, [r3, #4]
|
|
8004ca8: 099b lsrs r3, r3, #6
|
|
8004caa: 2200 movs r2, #0
|
|
8004cac: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8004cb0: f8c7 209c str.w r2, [r7, #156] @ 0x9c
|
|
8004cb4: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8004cb8: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8004cbc: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8004cc0: 2300 movs r3, #0
|
|
8004cc2: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
8004cc6: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
|
|
8004cca: 4622 mov r2, r4
|
|
8004ccc: 462b mov r3, r5
|
|
8004cce: f04f 0000 mov.w r0, #0
|
|
8004cd2: f04f 0100 mov.w r1, #0
|
|
8004cd6: 0159 lsls r1, r3, #5
|
|
8004cd8: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8004cdc: 0150 lsls r0, r2, #5
|
|
8004cde: 4602 mov r2, r0
|
|
8004ce0: 460b mov r3, r1
|
|
8004ce2: 4621 mov r1, r4
|
|
8004ce4: 1a51 subs r1, r2, r1
|
|
8004ce6: 6439 str r1, [r7, #64] @ 0x40
|
|
8004ce8: 4629 mov r1, r5
|
|
8004cea: eb63 0301 sbc.w r3, r3, r1
|
|
8004cee: 647b str r3, [r7, #68] @ 0x44
|
|
8004cf0: f04f 0200 mov.w r2, #0
|
|
8004cf4: f04f 0300 mov.w r3, #0
|
|
8004cf8: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40
|
|
8004cfc: 4649 mov r1, r9
|
|
8004cfe: 018b lsls r3, r1, #6
|
|
8004d00: 4641 mov r1, r8
|
|
8004d02: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8004d06: 4641 mov r1, r8
|
|
8004d08: 018a lsls r2, r1, #6
|
|
8004d0a: 4641 mov r1, r8
|
|
8004d0c: 1a51 subs r1, r2, r1
|
|
8004d0e: 63b9 str r1, [r7, #56] @ 0x38
|
|
8004d10: 4649 mov r1, r9
|
|
8004d12: eb63 0301 sbc.w r3, r3, r1
|
|
8004d16: 63fb str r3, [r7, #60] @ 0x3c
|
|
8004d18: f04f 0200 mov.w r2, #0
|
|
8004d1c: f04f 0300 mov.w r3, #0
|
|
8004d20: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38
|
|
8004d24: 4649 mov r1, r9
|
|
8004d26: 00cb lsls r3, r1, #3
|
|
8004d28: 4641 mov r1, r8
|
|
8004d2a: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8004d2e: 4641 mov r1, r8
|
|
8004d30: 00ca lsls r2, r1, #3
|
|
8004d32: 4610 mov r0, r2
|
|
8004d34: 4619 mov r1, r3
|
|
8004d36: 4603 mov r3, r0
|
|
8004d38: 4622 mov r2, r4
|
|
8004d3a: 189b adds r3, r3, r2
|
|
8004d3c: 633b str r3, [r7, #48] @ 0x30
|
|
8004d3e: 462b mov r3, r5
|
|
8004d40: 460a mov r2, r1
|
|
8004d42: eb42 0303 adc.w r3, r2, r3
|
|
8004d46: 637b str r3, [r7, #52] @ 0x34
|
|
8004d48: f04f 0200 mov.w r2, #0
|
|
8004d4c: f04f 0300 mov.w r3, #0
|
|
8004d50: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30
|
|
8004d54: 4629 mov r1, r5
|
|
8004d56: 024b lsls r3, r1, #9
|
|
8004d58: 4621 mov r1, r4
|
|
8004d5a: ea43 53d1 orr.w r3, r3, r1, lsr #23
|
|
8004d5e: 4621 mov r1, r4
|
|
8004d60: 024a lsls r2, r1, #9
|
|
8004d62: 4610 mov r0, r2
|
|
8004d64: 4619 mov r1, r3
|
|
8004d66: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8004d6a: 2200 movs r2, #0
|
|
8004d6c: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
8004d70: f8c7 208c str.w r2, [r7, #140] @ 0x8c
|
|
8004d74: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88
|
|
8004d78: f7fb fa44 bl 8000204 <__aeabi_uldivmod>
|
|
8004d7c: 4602 mov r2, r0
|
|
8004d7e: 460b mov r3, r1
|
|
8004d80: 4613 mov r3, r2
|
|
8004d82: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8004d86: e067 b.n 8004e58 <HAL_RCC_GetSysClockFreq+0x24c>
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8004d88: 4b75 ldr r3, [pc, #468] @ (8004f60 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004d8a: 685b ldr r3, [r3, #4]
|
|
8004d8c: 099b lsrs r3, r3, #6
|
|
8004d8e: 2200 movs r2, #0
|
|
8004d90: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8004d94: f8c7 2084 str.w r2, [r7, #132] @ 0x84
|
|
8004d98: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
8004d9c: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8004da0: 67bb str r3, [r7, #120] @ 0x78
|
|
8004da2: 2300 movs r3, #0
|
|
8004da4: 67fb str r3, [r7, #124] @ 0x7c
|
|
8004da6: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78
|
|
8004daa: 4622 mov r2, r4
|
|
8004dac: 462b mov r3, r5
|
|
8004dae: f04f 0000 mov.w r0, #0
|
|
8004db2: f04f 0100 mov.w r1, #0
|
|
8004db6: 0159 lsls r1, r3, #5
|
|
8004db8: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8004dbc: 0150 lsls r0, r2, #5
|
|
8004dbe: 4602 mov r2, r0
|
|
8004dc0: 460b mov r3, r1
|
|
8004dc2: 4621 mov r1, r4
|
|
8004dc4: 1a51 subs r1, r2, r1
|
|
8004dc6: 62b9 str r1, [r7, #40] @ 0x28
|
|
8004dc8: 4629 mov r1, r5
|
|
8004dca: eb63 0301 sbc.w r3, r3, r1
|
|
8004dce: 62fb str r3, [r7, #44] @ 0x2c
|
|
8004dd0: f04f 0200 mov.w r2, #0
|
|
8004dd4: f04f 0300 mov.w r3, #0
|
|
8004dd8: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28
|
|
8004ddc: 4649 mov r1, r9
|
|
8004dde: 018b lsls r3, r1, #6
|
|
8004de0: 4641 mov r1, r8
|
|
8004de2: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8004de6: 4641 mov r1, r8
|
|
8004de8: 018a lsls r2, r1, #6
|
|
8004dea: 4641 mov r1, r8
|
|
8004dec: ebb2 0a01 subs.w sl, r2, r1
|
|
8004df0: 4649 mov r1, r9
|
|
8004df2: eb63 0b01 sbc.w fp, r3, r1
|
|
8004df6: f04f 0200 mov.w r2, #0
|
|
8004dfa: f04f 0300 mov.w r3, #0
|
|
8004dfe: ea4f 03cb mov.w r3, fp, lsl #3
|
|
8004e02: ea43 735a orr.w r3, r3, sl, lsr #29
|
|
8004e06: ea4f 02ca mov.w r2, sl, lsl #3
|
|
8004e0a: 4692 mov sl, r2
|
|
8004e0c: 469b mov fp, r3
|
|
8004e0e: 4623 mov r3, r4
|
|
8004e10: eb1a 0303 adds.w r3, sl, r3
|
|
8004e14: 623b str r3, [r7, #32]
|
|
8004e16: 462b mov r3, r5
|
|
8004e18: eb4b 0303 adc.w r3, fp, r3
|
|
8004e1c: 627b str r3, [r7, #36] @ 0x24
|
|
8004e1e: f04f 0200 mov.w r2, #0
|
|
8004e22: f04f 0300 mov.w r3, #0
|
|
8004e26: e9d7 4508 ldrd r4, r5, [r7, #32]
|
|
8004e2a: 4629 mov r1, r5
|
|
8004e2c: 028b lsls r3, r1, #10
|
|
8004e2e: 4621 mov r1, r4
|
|
8004e30: ea43 5391 orr.w r3, r3, r1, lsr #22
|
|
8004e34: 4621 mov r1, r4
|
|
8004e36: 028a lsls r2, r1, #10
|
|
8004e38: 4610 mov r0, r2
|
|
8004e3a: 4619 mov r1, r3
|
|
8004e3c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8004e40: 2200 movs r2, #0
|
|
8004e42: 673b str r3, [r7, #112] @ 0x70
|
|
8004e44: 677a str r2, [r7, #116] @ 0x74
|
|
8004e46: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70
|
|
8004e4a: f7fb f9db bl 8000204 <__aeabi_uldivmod>
|
|
8004e4e: 4602 mov r2, r0
|
|
8004e50: 460b mov r3, r1
|
|
8004e52: 4613 mov r3, r2
|
|
8004e54: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
}
|
|
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
|
|
8004e58: 4b41 ldr r3, [pc, #260] @ (8004f60 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004e5a: 685b ldr r3, [r3, #4]
|
|
8004e5c: 0c1b lsrs r3, r3, #16
|
|
8004e5e: f003 0303 and.w r3, r3, #3
|
|
8004e62: 3301 adds r3, #1
|
|
8004e64: 005b lsls r3, r3, #1
|
|
8004e66: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
|
|
sysclockfreq = pllvco / pllp;
|
|
8004e6a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
8004e6e: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8004e72: fbb2 f3f3 udiv r3, r2, r3
|
|
8004e76: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8004e7a: e0eb b.n 8005054 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLR */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
8004e7c: 4b38 ldr r3, [pc, #224] @ (8004f60 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004e7e: 685b ldr r3, [r3, #4]
|
|
8004e80: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
8004e84: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
8004e88: 4b35 ldr r3, [pc, #212] @ (8004f60 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004e8a: 685b ldr r3, [r3, #4]
|
|
8004e8c: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004e90: 2b00 cmp r3, #0
|
|
8004e92: d06b beq.n 8004f6c <HAL_RCC_GetSysClockFreq+0x360>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8004e94: 4b32 ldr r3, [pc, #200] @ (8004f60 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004e96: 685b ldr r3, [r3, #4]
|
|
8004e98: 099b lsrs r3, r3, #6
|
|
8004e9a: 2200 movs r2, #0
|
|
8004e9c: 66bb str r3, [r7, #104] @ 0x68
|
|
8004e9e: 66fa str r2, [r7, #108] @ 0x6c
|
|
8004ea0: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8004ea2: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8004ea6: 663b str r3, [r7, #96] @ 0x60
|
|
8004ea8: 2300 movs r3, #0
|
|
8004eaa: 667b str r3, [r7, #100] @ 0x64
|
|
8004eac: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60
|
|
8004eb0: 4622 mov r2, r4
|
|
8004eb2: 462b mov r3, r5
|
|
8004eb4: f04f 0000 mov.w r0, #0
|
|
8004eb8: f04f 0100 mov.w r1, #0
|
|
8004ebc: 0159 lsls r1, r3, #5
|
|
8004ebe: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8004ec2: 0150 lsls r0, r2, #5
|
|
8004ec4: 4602 mov r2, r0
|
|
8004ec6: 460b mov r3, r1
|
|
8004ec8: 4621 mov r1, r4
|
|
8004eca: 1a51 subs r1, r2, r1
|
|
8004ecc: 61b9 str r1, [r7, #24]
|
|
8004ece: 4629 mov r1, r5
|
|
8004ed0: eb63 0301 sbc.w r3, r3, r1
|
|
8004ed4: 61fb str r3, [r7, #28]
|
|
8004ed6: f04f 0200 mov.w r2, #0
|
|
8004eda: f04f 0300 mov.w r3, #0
|
|
8004ede: e9d7 ab06 ldrd sl, fp, [r7, #24]
|
|
8004ee2: 4659 mov r1, fp
|
|
8004ee4: 018b lsls r3, r1, #6
|
|
8004ee6: 4651 mov r1, sl
|
|
8004ee8: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8004eec: 4651 mov r1, sl
|
|
8004eee: 018a lsls r2, r1, #6
|
|
8004ef0: 4651 mov r1, sl
|
|
8004ef2: ebb2 0801 subs.w r8, r2, r1
|
|
8004ef6: 4659 mov r1, fp
|
|
8004ef8: eb63 0901 sbc.w r9, r3, r1
|
|
8004efc: f04f 0200 mov.w r2, #0
|
|
8004f00: f04f 0300 mov.w r3, #0
|
|
8004f04: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8004f08: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8004f0c: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
8004f10: 4690 mov r8, r2
|
|
8004f12: 4699 mov r9, r3
|
|
8004f14: 4623 mov r3, r4
|
|
8004f16: eb18 0303 adds.w r3, r8, r3
|
|
8004f1a: 613b str r3, [r7, #16]
|
|
8004f1c: 462b mov r3, r5
|
|
8004f1e: eb49 0303 adc.w r3, r9, r3
|
|
8004f22: 617b str r3, [r7, #20]
|
|
8004f24: f04f 0200 mov.w r2, #0
|
|
8004f28: f04f 0300 mov.w r3, #0
|
|
8004f2c: e9d7 4504 ldrd r4, r5, [r7, #16]
|
|
8004f30: 4629 mov r1, r5
|
|
8004f32: 024b lsls r3, r1, #9
|
|
8004f34: 4621 mov r1, r4
|
|
8004f36: ea43 53d1 orr.w r3, r3, r1, lsr #23
|
|
8004f3a: 4621 mov r1, r4
|
|
8004f3c: 024a lsls r2, r1, #9
|
|
8004f3e: 4610 mov r0, r2
|
|
8004f40: 4619 mov r1, r3
|
|
8004f42: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8004f46: 2200 movs r2, #0
|
|
8004f48: 65bb str r3, [r7, #88] @ 0x58
|
|
8004f4a: 65fa str r2, [r7, #92] @ 0x5c
|
|
8004f4c: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
|
|
8004f50: f7fb f958 bl 8000204 <__aeabi_uldivmod>
|
|
8004f54: 4602 mov r2, r0
|
|
8004f56: 460b mov r3, r1
|
|
8004f58: 4613 mov r3, r2
|
|
8004f5a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8004f5e: e065 b.n 800502c <HAL_RCC_GetSysClockFreq+0x420>
|
|
8004f60: 40023800 .word 0x40023800
|
|
8004f64: 00f42400 .word 0x00f42400
|
|
8004f68: 007a1200 .word 0x007a1200
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8004f6c: 4b3d ldr r3, [pc, #244] @ (8005064 <HAL_RCC_GetSysClockFreq+0x458>)
|
|
8004f6e: 685b ldr r3, [r3, #4]
|
|
8004f70: 099b lsrs r3, r3, #6
|
|
8004f72: 2200 movs r2, #0
|
|
8004f74: 4618 mov r0, r3
|
|
8004f76: 4611 mov r1, r2
|
|
8004f78: f3c0 0308 ubfx r3, r0, #0, #9
|
|
8004f7c: 653b str r3, [r7, #80] @ 0x50
|
|
8004f7e: 2300 movs r3, #0
|
|
8004f80: 657b str r3, [r7, #84] @ 0x54
|
|
8004f82: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50
|
|
8004f86: 4642 mov r2, r8
|
|
8004f88: 464b mov r3, r9
|
|
8004f8a: f04f 0000 mov.w r0, #0
|
|
8004f8e: f04f 0100 mov.w r1, #0
|
|
8004f92: 0159 lsls r1, r3, #5
|
|
8004f94: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8004f98: 0150 lsls r0, r2, #5
|
|
8004f9a: 4602 mov r2, r0
|
|
8004f9c: 460b mov r3, r1
|
|
8004f9e: 4641 mov r1, r8
|
|
8004fa0: 1a51 subs r1, r2, r1
|
|
8004fa2: 60b9 str r1, [r7, #8]
|
|
8004fa4: 4649 mov r1, r9
|
|
8004fa6: eb63 0301 sbc.w r3, r3, r1
|
|
8004faa: 60fb str r3, [r7, #12]
|
|
8004fac: f04f 0200 mov.w r2, #0
|
|
8004fb0: f04f 0300 mov.w r3, #0
|
|
8004fb4: e9d7 ab02 ldrd sl, fp, [r7, #8]
|
|
8004fb8: 4659 mov r1, fp
|
|
8004fba: 018b lsls r3, r1, #6
|
|
8004fbc: 4651 mov r1, sl
|
|
8004fbe: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8004fc2: 4651 mov r1, sl
|
|
8004fc4: 018a lsls r2, r1, #6
|
|
8004fc6: 4651 mov r1, sl
|
|
8004fc8: 1a54 subs r4, r2, r1
|
|
8004fca: 4659 mov r1, fp
|
|
8004fcc: eb63 0501 sbc.w r5, r3, r1
|
|
8004fd0: f04f 0200 mov.w r2, #0
|
|
8004fd4: f04f 0300 mov.w r3, #0
|
|
8004fd8: 00eb lsls r3, r5, #3
|
|
8004fda: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
8004fde: 00e2 lsls r2, r4, #3
|
|
8004fe0: 4614 mov r4, r2
|
|
8004fe2: 461d mov r5, r3
|
|
8004fe4: 4643 mov r3, r8
|
|
8004fe6: 18e3 adds r3, r4, r3
|
|
8004fe8: 603b str r3, [r7, #0]
|
|
8004fea: 464b mov r3, r9
|
|
8004fec: eb45 0303 adc.w r3, r5, r3
|
|
8004ff0: 607b str r3, [r7, #4]
|
|
8004ff2: f04f 0200 mov.w r2, #0
|
|
8004ff6: f04f 0300 mov.w r3, #0
|
|
8004ffa: e9d7 4500 ldrd r4, r5, [r7]
|
|
8004ffe: 4629 mov r1, r5
|
|
8005000: 028b lsls r3, r1, #10
|
|
8005002: 4621 mov r1, r4
|
|
8005004: ea43 5391 orr.w r3, r3, r1, lsr #22
|
|
8005008: 4621 mov r1, r4
|
|
800500a: 028a lsls r2, r1, #10
|
|
800500c: 4610 mov r0, r2
|
|
800500e: 4619 mov r1, r3
|
|
8005010: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8005014: 2200 movs r2, #0
|
|
8005016: 64bb str r3, [r7, #72] @ 0x48
|
|
8005018: 64fa str r2, [r7, #76] @ 0x4c
|
|
800501a: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
|
|
800501e: f7fb f8f1 bl 8000204 <__aeabi_uldivmod>
|
|
8005022: 4602 mov r2, r0
|
|
8005024: 460b mov r3, r1
|
|
8005026: 4613 mov r3, r2
|
|
8005028: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
}
|
|
pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
|
|
800502c: 4b0d ldr r3, [pc, #52] @ (8005064 <HAL_RCC_GetSysClockFreq+0x458>)
|
|
800502e: 685b ldr r3, [r3, #4]
|
|
8005030: 0f1b lsrs r3, r3, #28
|
|
8005032: f003 0307 and.w r3, r3, #7
|
|
8005036: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
|
|
sysclockfreq = pllvco / pllr;
|
|
800503a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
800503e: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
8005042: fbb2 f3f3 udiv r3, r2, r3
|
|
8005046: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
800504a: e003 b.n 8005054 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
default:
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
800504c: 4b06 ldr r3, [pc, #24] @ (8005068 <HAL_RCC_GetSysClockFreq+0x45c>)
|
|
800504e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8005052: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8005054: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
|
|
}
|
|
8005058: 4618 mov r0, r3
|
|
800505a: 37b8 adds r7, #184 @ 0xb8
|
|
800505c: 46bd mov sp, r7
|
|
800505e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8005062: bf00 nop
|
|
8005064: 40023800 .word 0x40023800
|
|
8005068: 00f42400 .word 0x00f42400
|
|
|
|
0800506c <HAL_RCC_OscConfig>:
|
|
* @note This function add the PLL/PLLR factor management during PLL configuration this feature
|
|
* is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
800506c: b580 push {r7, lr}
|
|
800506e: b086 sub sp, #24
|
|
8005070: af00 add r7, sp, #0
|
|
8005072: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8005074: 687b ldr r3, [r7, #4]
|
|
8005076: 2b00 cmp r3, #0
|
|
8005078: d101 bne.n 800507e <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800507a: 2301 movs r3, #1
|
|
800507c: e28d b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
800507e: 687b ldr r3, [r7, #4]
|
|
8005080: 681b ldr r3, [r3, #0]
|
|
8005082: f003 0301 and.w r3, r3, #1
|
|
8005086: 2b00 cmp r3, #0
|
|
8005088: f000 8083 beq.w 8005192 <HAL_RCC_OscConfig+0x126>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
|
|
#if defined(STM32F446xx)
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
800508c: 4b94 ldr r3, [pc, #592] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
800508e: 689b ldr r3, [r3, #8]
|
|
8005090: f003 030c and.w r3, r3, #12
|
|
8005094: 2b04 cmp r3, #4
|
|
8005096: d019 beq.n 80050cc <HAL_RCC_OscConfig+0x60>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
8005098: 4b91 ldr r3, [pc, #580] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
800509a: 689b ldr r3, [r3, #8]
|
|
800509c: f003 030c and.w r3, r3, #12
|
|
|| \
|
|
80050a0: 2b08 cmp r3, #8
|
|
80050a2: d106 bne.n 80050b2 <HAL_RCC_OscConfig+0x46>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
80050a4: 4b8e ldr r3, [pc, #568] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80050a6: 685b ldr r3, [r3, #4]
|
|
80050a8: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80050ac: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80050b0: d00c beq.n 80050cc <HAL_RCC_OscConfig+0x60>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
80050b2: 4b8b ldr r3, [pc, #556] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80050b4: 689b ldr r3, [r3, #8]
|
|
80050b6: f003 030c and.w r3, r3, #12
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
80050ba: 2b0c cmp r3, #12
|
|
80050bc: d112 bne.n 80050e4 <HAL_RCC_OscConfig+0x78>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
80050be: 4b88 ldr r3, [pc, #544] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80050c0: 685b ldr r3, [r3, #4]
|
|
80050c2: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80050c6: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80050ca: d10b bne.n 80050e4 <HAL_RCC_OscConfig+0x78>
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
#endif /* STM32F446xx */
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
80050cc: 4b84 ldr r3, [pc, #528] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80050ce: 681b ldr r3, [r3, #0]
|
|
80050d0: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80050d4: 2b00 cmp r3, #0
|
|
80050d6: d05b beq.n 8005190 <HAL_RCC_OscConfig+0x124>
|
|
80050d8: 687b ldr r3, [r7, #4]
|
|
80050da: 685b ldr r3, [r3, #4]
|
|
80050dc: 2b00 cmp r3, #0
|
|
80050de: d157 bne.n 8005190 <HAL_RCC_OscConfig+0x124>
|
|
{
|
|
return HAL_ERROR;
|
|
80050e0: 2301 movs r3, #1
|
|
80050e2: e25a b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
80050e4: 687b ldr r3, [r7, #4]
|
|
80050e6: 685b ldr r3, [r3, #4]
|
|
80050e8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
80050ec: d106 bne.n 80050fc <HAL_RCC_OscConfig+0x90>
|
|
80050ee: 4b7c ldr r3, [pc, #496] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80050f0: 681b ldr r3, [r3, #0]
|
|
80050f2: 4a7b ldr r2, [pc, #492] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80050f4: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
80050f8: 6013 str r3, [r2, #0]
|
|
80050fa: e01d b.n 8005138 <HAL_RCC_OscConfig+0xcc>
|
|
80050fc: 687b ldr r3, [r7, #4]
|
|
80050fe: 685b ldr r3, [r3, #4]
|
|
8005100: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8005104: d10c bne.n 8005120 <HAL_RCC_OscConfig+0xb4>
|
|
8005106: 4b76 ldr r3, [pc, #472] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
8005108: 681b ldr r3, [r3, #0]
|
|
800510a: 4a75 ldr r2, [pc, #468] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
800510c: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8005110: 6013 str r3, [r2, #0]
|
|
8005112: 4b73 ldr r3, [pc, #460] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
8005114: 681b ldr r3, [r3, #0]
|
|
8005116: 4a72 ldr r2, [pc, #456] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
8005118: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800511c: 6013 str r3, [r2, #0]
|
|
800511e: e00b b.n 8005138 <HAL_RCC_OscConfig+0xcc>
|
|
8005120: 4b6f ldr r3, [pc, #444] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
8005122: 681b ldr r3, [r3, #0]
|
|
8005124: 4a6e ldr r2, [pc, #440] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
8005126: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800512a: 6013 str r3, [r2, #0]
|
|
800512c: 4b6c ldr r3, [pc, #432] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
800512e: 681b ldr r3, [r3, #0]
|
|
8005130: 4a6b ldr r2, [pc, #428] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
8005132: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8005136: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
|
|
8005138: 687b ldr r3, [r7, #4]
|
|
800513a: 685b ldr r3, [r3, #4]
|
|
800513c: 2b00 cmp r3, #0
|
|
800513e: d013 beq.n 8005168 <HAL_RCC_OscConfig+0xfc>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005140: f7fc fe4c bl 8001ddc <HAL_GetTick>
|
|
8005144: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8005146: e008 b.n 800515a <HAL_RCC_OscConfig+0xee>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8005148: f7fc fe48 bl 8001ddc <HAL_GetTick>
|
|
800514c: 4602 mov r2, r0
|
|
800514e: 693b ldr r3, [r7, #16]
|
|
8005150: 1ad3 subs r3, r2, r3
|
|
8005152: 2b64 cmp r3, #100 @ 0x64
|
|
8005154: d901 bls.n 800515a <HAL_RCC_OscConfig+0xee>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005156: 2303 movs r3, #3
|
|
8005158: e21f b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
800515a: 4b61 ldr r3, [pc, #388] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
800515c: 681b ldr r3, [r3, #0]
|
|
800515e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8005162: 2b00 cmp r3, #0
|
|
8005164: d0f0 beq.n 8005148 <HAL_RCC_OscConfig+0xdc>
|
|
8005166: e014 b.n 8005192 <HAL_RCC_OscConfig+0x126>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005168: f7fc fe38 bl 8001ddc <HAL_GetTick>
|
|
800516c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is bypassed or disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
800516e: e008 b.n 8005182 <HAL_RCC_OscConfig+0x116>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8005170: f7fc fe34 bl 8001ddc <HAL_GetTick>
|
|
8005174: 4602 mov r2, r0
|
|
8005176: 693b ldr r3, [r7, #16]
|
|
8005178: 1ad3 subs r3, r2, r3
|
|
800517a: 2b64 cmp r3, #100 @ 0x64
|
|
800517c: d901 bls.n 8005182 <HAL_RCC_OscConfig+0x116>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800517e: 2303 movs r3, #3
|
|
8005180: e20b b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8005182: 4b57 ldr r3, [pc, #348] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
8005184: 681b ldr r3, [r3, #0]
|
|
8005186: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800518a: 2b00 cmp r3, #0
|
|
800518c: d1f0 bne.n 8005170 <HAL_RCC_OscConfig+0x104>
|
|
800518e: e000 b.n 8005192 <HAL_RCC_OscConfig+0x126>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8005190: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8005192: 687b ldr r3, [r7, #4]
|
|
8005194: 681b ldr r3, [r3, #0]
|
|
8005196: f003 0302 and.w r3, r3, #2
|
|
800519a: 2b00 cmp r3, #0
|
|
800519c: d06f beq.n 800527e <HAL_RCC_OscConfig+0x212>
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
#if defined(STM32F446xx)
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
|
|
800519e: 4b50 ldr r3, [pc, #320] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80051a0: 689b ldr r3, [r3, #8]
|
|
80051a2: f003 030c and.w r3, r3, #12
|
|
80051a6: 2b00 cmp r3, #0
|
|
80051a8: d017 beq.n 80051da <HAL_RCC_OscConfig+0x16e>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
80051aa: 4b4d ldr r3, [pc, #308] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80051ac: 689b ldr r3, [r3, #8]
|
|
80051ae: f003 030c and.w r3, r3, #12
|
|
|| \
|
|
80051b2: 2b08 cmp r3, #8
|
|
80051b4: d105 bne.n 80051c2 <HAL_RCC_OscConfig+0x156>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
80051b6: 4b4a ldr r3, [pc, #296] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80051b8: 685b ldr r3, [r3, #4]
|
|
80051ba: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80051be: 2b00 cmp r3, #0
|
|
80051c0: d00b beq.n 80051da <HAL_RCC_OscConfig+0x16e>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
80051c2: 4b47 ldr r3, [pc, #284] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80051c4: 689b ldr r3, [r3, #8]
|
|
80051c6: f003 030c and.w r3, r3, #12
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
80051ca: 2b0c cmp r3, #12
|
|
80051cc: d11c bne.n 8005208 <HAL_RCC_OscConfig+0x19c>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
80051ce: 4b44 ldr r3, [pc, #272] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80051d0: 685b ldr r3, [r3, #4]
|
|
80051d2: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80051d6: 2b00 cmp r3, #0
|
|
80051d8: d116 bne.n 8005208 <HAL_RCC_OscConfig+0x19c>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
#endif /* STM32F446xx */
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
80051da: 4b41 ldr r3, [pc, #260] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80051dc: 681b ldr r3, [r3, #0]
|
|
80051de: f003 0302 and.w r3, r3, #2
|
|
80051e2: 2b00 cmp r3, #0
|
|
80051e4: d005 beq.n 80051f2 <HAL_RCC_OscConfig+0x186>
|
|
80051e6: 687b ldr r3, [r7, #4]
|
|
80051e8: 68db ldr r3, [r3, #12]
|
|
80051ea: 2b01 cmp r3, #1
|
|
80051ec: d001 beq.n 80051f2 <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
return HAL_ERROR;
|
|
80051ee: 2301 movs r3, #1
|
|
80051f0: e1d3 b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
80051f2: 4b3b ldr r3, [pc, #236] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80051f4: 681b ldr r3, [r3, #0]
|
|
80051f6: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
80051fa: 687b ldr r3, [r7, #4]
|
|
80051fc: 691b ldr r3, [r3, #16]
|
|
80051fe: 00db lsls r3, r3, #3
|
|
8005200: 4937 ldr r1, [pc, #220] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
8005202: 4313 orrs r3, r2
|
|
8005204: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8005206: e03a b.n 800527e <HAL_RCC_OscConfig+0x212>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
|
|
8005208: 687b ldr r3, [r7, #4]
|
|
800520a: 68db ldr r3, [r3, #12]
|
|
800520c: 2b00 cmp r3, #0
|
|
800520e: d020 beq.n 8005252 <HAL_RCC_OscConfig+0x1e6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8005210: 4b34 ldr r3, [pc, #208] @ (80052e4 <HAL_RCC_OscConfig+0x278>)
|
|
8005212: 2201 movs r2, #1
|
|
8005214: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005216: f7fc fde1 bl 8001ddc <HAL_GetTick>
|
|
800521a: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
800521c: e008 b.n 8005230 <HAL_RCC_OscConfig+0x1c4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
800521e: f7fc fddd bl 8001ddc <HAL_GetTick>
|
|
8005222: 4602 mov r2, r0
|
|
8005224: 693b ldr r3, [r7, #16]
|
|
8005226: 1ad3 subs r3, r2, r3
|
|
8005228: 2b02 cmp r3, #2
|
|
800522a: d901 bls.n 8005230 <HAL_RCC_OscConfig+0x1c4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800522c: 2303 movs r3, #3
|
|
800522e: e1b4 b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8005230: 4b2b ldr r3, [pc, #172] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
8005232: 681b ldr r3, [r3, #0]
|
|
8005234: f003 0302 and.w r3, r3, #2
|
|
8005238: 2b00 cmp r3, #0
|
|
800523a: d0f0 beq.n 800521e <HAL_RCC_OscConfig+0x1b2>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
800523c: 4b28 ldr r3, [pc, #160] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
800523e: 681b ldr r3, [r3, #0]
|
|
8005240: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8005244: 687b ldr r3, [r7, #4]
|
|
8005246: 691b ldr r3, [r3, #16]
|
|
8005248: 00db lsls r3, r3, #3
|
|
800524a: 4925 ldr r1, [pc, #148] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
800524c: 4313 orrs r3, r2
|
|
800524e: 600b str r3, [r1, #0]
|
|
8005250: e015 b.n 800527e <HAL_RCC_OscConfig+0x212>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8005252: 4b24 ldr r3, [pc, #144] @ (80052e4 <HAL_RCC_OscConfig+0x278>)
|
|
8005254: 2200 movs r2, #0
|
|
8005256: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005258: f7fc fdc0 bl 8001ddc <HAL_GetTick>
|
|
800525c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
800525e: e008 b.n 8005272 <HAL_RCC_OscConfig+0x206>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8005260: f7fc fdbc bl 8001ddc <HAL_GetTick>
|
|
8005264: 4602 mov r2, r0
|
|
8005266: 693b ldr r3, [r7, #16]
|
|
8005268: 1ad3 subs r3, r2, r3
|
|
800526a: 2b02 cmp r3, #2
|
|
800526c: d901 bls.n 8005272 <HAL_RCC_OscConfig+0x206>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800526e: 2303 movs r3, #3
|
|
8005270: e193 b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8005272: 4b1b ldr r3, [pc, #108] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
8005274: 681b ldr r3, [r3, #0]
|
|
8005276: f003 0302 and.w r3, r3, #2
|
|
800527a: 2b00 cmp r3, #0
|
|
800527c: d1f0 bne.n 8005260 <HAL_RCC_OscConfig+0x1f4>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
800527e: 687b ldr r3, [r7, #4]
|
|
8005280: 681b ldr r3, [r3, #0]
|
|
8005282: f003 0308 and.w r3, r3, #8
|
|
8005286: 2b00 cmp r3, #0
|
|
8005288: d036 beq.n 80052f8 <HAL_RCC_OscConfig+0x28c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
|
|
800528a: 687b ldr r3, [r7, #4]
|
|
800528c: 695b ldr r3, [r3, #20]
|
|
800528e: 2b00 cmp r3, #0
|
|
8005290: d016 beq.n 80052c0 <HAL_RCC_OscConfig+0x254>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8005292: 4b15 ldr r3, [pc, #84] @ (80052e8 <HAL_RCC_OscConfig+0x27c>)
|
|
8005294: 2201 movs r2, #1
|
|
8005296: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005298: f7fc fda0 bl 8001ddc <HAL_GetTick>
|
|
800529c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
800529e: e008 b.n 80052b2 <HAL_RCC_OscConfig+0x246>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
80052a0: f7fc fd9c bl 8001ddc <HAL_GetTick>
|
|
80052a4: 4602 mov r2, r0
|
|
80052a6: 693b ldr r3, [r7, #16]
|
|
80052a8: 1ad3 subs r3, r2, r3
|
|
80052aa: 2b02 cmp r3, #2
|
|
80052ac: d901 bls.n 80052b2 <HAL_RCC_OscConfig+0x246>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80052ae: 2303 movs r3, #3
|
|
80052b0: e173 b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80052b2: 4b0b ldr r3, [pc, #44] @ (80052e0 <HAL_RCC_OscConfig+0x274>)
|
|
80052b4: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80052b6: f003 0302 and.w r3, r3, #2
|
|
80052ba: 2b00 cmp r3, #0
|
|
80052bc: d0f0 beq.n 80052a0 <HAL_RCC_OscConfig+0x234>
|
|
80052be: e01b b.n 80052f8 <HAL_RCC_OscConfig+0x28c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
80052c0: 4b09 ldr r3, [pc, #36] @ (80052e8 <HAL_RCC_OscConfig+0x27c>)
|
|
80052c2: 2200 movs r2, #0
|
|
80052c4: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80052c6: f7fc fd89 bl 8001ddc <HAL_GetTick>
|
|
80052ca: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
80052cc: e00e b.n 80052ec <HAL_RCC_OscConfig+0x280>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
80052ce: f7fc fd85 bl 8001ddc <HAL_GetTick>
|
|
80052d2: 4602 mov r2, r0
|
|
80052d4: 693b ldr r3, [r7, #16]
|
|
80052d6: 1ad3 subs r3, r2, r3
|
|
80052d8: 2b02 cmp r3, #2
|
|
80052da: d907 bls.n 80052ec <HAL_RCC_OscConfig+0x280>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80052dc: 2303 movs r3, #3
|
|
80052de: e15c b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
80052e0: 40023800 .word 0x40023800
|
|
80052e4: 42470000 .word 0x42470000
|
|
80052e8: 42470e80 .word 0x42470e80
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
80052ec: 4b8a ldr r3, [pc, #552] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
80052ee: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80052f0: f003 0302 and.w r3, r3, #2
|
|
80052f4: 2b00 cmp r3, #0
|
|
80052f6: d1ea bne.n 80052ce <HAL_RCC_OscConfig+0x262>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
80052f8: 687b ldr r3, [r7, #4]
|
|
80052fa: 681b ldr r3, [r3, #0]
|
|
80052fc: f003 0304 and.w r3, r3, #4
|
|
8005300: 2b00 cmp r3, #0
|
|
8005302: f000 8097 beq.w 8005434 <HAL_RCC_OscConfig+0x3c8>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8005306: 2300 movs r3, #0
|
|
8005308: 75fb strb r3, [r7, #23]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
800530a: 4b83 ldr r3, [pc, #524] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
800530c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800530e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8005312: 2b00 cmp r3, #0
|
|
8005314: d10f bne.n 8005336 <HAL_RCC_OscConfig+0x2ca>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8005316: 2300 movs r3, #0
|
|
8005318: 60bb str r3, [r7, #8]
|
|
800531a: 4b7f ldr r3, [pc, #508] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
800531c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800531e: 4a7e ldr r2, [pc, #504] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
8005320: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8005324: 6413 str r3, [r2, #64] @ 0x40
|
|
8005326: 4b7c ldr r3, [pc, #496] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
8005328: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800532a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800532e: 60bb str r3, [r7, #8]
|
|
8005330: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8005332: 2301 movs r3, #1
|
|
8005334: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8005336: 4b79 ldr r3, [pc, #484] @ (800551c <HAL_RCC_OscConfig+0x4b0>)
|
|
8005338: 681b ldr r3, [r3, #0]
|
|
800533a: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800533e: 2b00 cmp r3, #0
|
|
8005340: d118 bne.n 8005374 <HAL_RCC_OscConfig+0x308>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
8005342: 4b76 ldr r3, [pc, #472] @ (800551c <HAL_RCC_OscConfig+0x4b0>)
|
|
8005344: 681b ldr r3, [r3, #0]
|
|
8005346: 4a75 ldr r2, [pc, #468] @ (800551c <HAL_RCC_OscConfig+0x4b0>)
|
|
8005348: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
800534c: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
800534e: f7fc fd45 bl 8001ddc <HAL_GetTick>
|
|
8005352: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8005354: e008 b.n 8005368 <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8005356: f7fc fd41 bl 8001ddc <HAL_GetTick>
|
|
800535a: 4602 mov r2, r0
|
|
800535c: 693b ldr r3, [r7, #16]
|
|
800535e: 1ad3 subs r3, r2, r3
|
|
8005360: 2b02 cmp r3, #2
|
|
8005362: d901 bls.n 8005368 <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005364: 2303 movs r3, #3
|
|
8005366: e118 b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8005368: 4b6c ldr r3, [pc, #432] @ (800551c <HAL_RCC_OscConfig+0x4b0>)
|
|
800536a: 681b ldr r3, [r3, #0]
|
|
800536c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005370: 2b00 cmp r3, #0
|
|
8005372: d0f0 beq.n 8005356 <HAL_RCC_OscConfig+0x2ea>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8005374: 687b ldr r3, [r7, #4]
|
|
8005376: 689b ldr r3, [r3, #8]
|
|
8005378: 2b01 cmp r3, #1
|
|
800537a: d106 bne.n 800538a <HAL_RCC_OscConfig+0x31e>
|
|
800537c: 4b66 ldr r3, [pc, #408] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
800537e: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8005380: 4a65 ldr r2, [pc, #404] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
8005382: f043 0301 orr.w r3, r3, #1
|
|
8005386: 6713 str r3, [r2, #112] @ 0x70
|
|
8005388: e01c b.n 80053c4 <HAL_RCC_OscConfig+0x358>
|
|
800538a: 687b ldr r3, [r7, #4]
|
|
800538c: 689b ldr r3, [r3, #8]
|
|
800538e: 2b05 cmp r3, #5
|
|
8005390: d10c bne.n 80053ac <HAL_RCC_OscConfig+0x340>
|
|
8005392: 4b61 ldr r3, [pc, #388] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
8005394: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8005396: 4a60 ldr r2, [pc, #384] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
8005398: f043 0304 orr.w r3, r3, #4
|
|
800539c: 6713 str r3, [r2, #112] @ 0x70
|
|
800539e: 4b5e ldr r3, [pc, #376] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
80053a0: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80053a2: 4a5d ldr r2, [pc, #372] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
80053a4: f043 0301 orr.w r3, r3, #1
|
|
80053a8: 6713 str r3, [r2, #112] @ 0x70
|
|
80053aa: e00b b.n 80053c4 <HAL_RCC_OscConfig+0x358>
|
|
80053ac: 4b5a ldr r3, [pc, #360] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
80053ae: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80053b0: 4a59 ldr r2, [pc, #356] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
80053b2: f023 0301 bic.w r3, r3, #1
|
|
80053b6: 6713 str r3, [r2, #112] @ 0x70
|
|
80053b8: 4b57 ldr r3, [pc, #348] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
80053ba: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80053bc: 4a56 ldr r2, [pc, #344] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
80053be: f023 0304 bic.w r3, r3, #4
|
|
80053c2: 6713 str r3, [r2, #112] @ 0x70
|
|
/* Check the LSE State */
|
|
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
|
|
80053c4: 687b ldr r3, [r7, #4]
|
|
80053c6: 689b ldr r3, [r3, #8]
|
|
80053c8: 2b00 cmp r3, #0
|
|
80053ca: d015 beq.n 80053f8 <HAL_RCC_OscConfig+0x38c>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80053cc: f7fc fd06 bl 8001ddc <HAL_GetTick>
|
|
80053d0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
80053d2: e00a b.n 80053ea <HAL_RCC_OscConfig+0x37e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
80053d4: f7fc fd02 bl 8001ddc <HAL_GetTick>
|
|
80053d8: 4602 mov r2, r0
|
|
80053da: 693b ldr r3, [r7, #16]
|
|
80053dc: 1ad3 subs r3, r2, r3
|
|
80053de: f241 3288 movw r2, #5000 @ 0x1388
|
|
80053e2: 4293 cmp r3, r2
|
|
80053e4: d901 bls.n 80053ea <HAL_RCC_OscConfig+0x37e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80053e6: 2303 movs r3, #3
|
|
80053e8: e0d7 b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
80053ea: 4b4b ldr r3, [pc, #300] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
80053ec: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80053ee: f003 0302 and.w r3, r3, #2
|
|
80053f2: 2b00 cmp r3, #0
|
|
80053f4: d0ee beq.n 80053d4 <HAL_RCC_OscConfig+0x368>
|
|
80053f6: e014 b.n 8005422 <HAL_RCC_OscConfig+0x3b6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80053f8: f7fc fcf0 bl 8001ddc <HAL_GetTick>
|
|
80053fc: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
80053fe: e00a b.n 8005416 <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8005400: f7fc fcec bl 8001ddc <HAL_GetTick>
|
|
8005404: 4602 mov r2, r0
|
|
8005406: 693b ldr r3, [r7, #16]
|
|
8005408: 1ad3 subs r3, r2, r3
|
|
800540a: f241 3288 movw r2, #5000 @ 0x1388
|
|
800540e: 4293 cmp r3, r2
|
|
8005410: d901 bls.n 8005416 <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005412: 2303 movs r3, #3
|
|
8005414: e0c1 b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8005416: 4b40 ldr r3, [pc, #256] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
8005418: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800541a: f003 0302 and.w r3, r3, #2
|
|
800541e: 2b00 cmp r3, #0
|
|
8005420: d1ee bne.n 8005400 <HAL_RCC_OscConfig+0x394>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
8005422: 7dfb ldrb r3, [r7, #23]
|
|
8005424: 2b01 cmp r3, #1
|
|
8005426: d105 bne.n 8005434 <HAL_RCC_OscConfig+0x3c8>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8005428: 4b3b ldr r3, [pc, #236] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
800542a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800542c: 4a3a ldr r2, [pc, #232] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
800542e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8005432: 6413 str r3, [r2, #64] @ 0x40
|
|
}
|
|
}
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8005434: 687b ldr r3, [r7, #4]
|
|
8005436: 699b ldr r3, [r3, #24]
|
|
8005438: 2b00 cmp r3, #0
|
|
800543a: f000 80ad beq.w 8005598 <HAL_RCC_OscConfig+0x52c>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
|
800543e: 4b36 ldr r3, [pc, #216] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
8005440: 689b ldr r3, [r3, #8]
|
|
8005442: f003 030c and.w r3, r3, #12
|
|
8005446: 2b08 cmp r3, #8
|
|
8005448: d060 beq.n 800550c <HAL_RCC_OscConfig+0x4a0>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
800544a: 687b ldr r3, [r7, #4]
|
|
800544c: 699b ldr r3, [r3, #24]
|
|
800544e: 2b02 cmp r3, #2
|
|
8005450: d145 bne.n 80054de <HAL_RCC_OscConfig+0x472>
|
|
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8005452: 4b33 ldr r3, [pc, #204] @ (8005520 <HAL_RCC_OscConfig+0x4b4>)
|
|
8005454: 2200 movs r2, #0
|
|
8005456: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005458: f7fc fcc0 bl 8001ddc <HAL_GetTick>
|
|
800545c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
800545e: e008 b.n 8005472 <HAL_RCC_OscConfig+0x406>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8005460: f7fc fcbc bl 8001ddc <HAL_GetTick>
|
|
8005464: 4602 mov r2, r0
|
|
8005466: 693b ldr r3, [r7, #16]
|
|
8005468: 1ad3 subs r3, r2, r3
|
|
800546a: 2b02 cmp r3, #2
|
|
800546c: d901 bls.n 8005472 <HAL_RCC_OscConfig+0x406>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800546e: 2303 movs r3, #3
|
|
8005470: e093 b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8005472: 4b29 ldr r3, [pc, #164] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
8005474: 681b ldr r3, [r3, #0]
|
|
8005476: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800547a: 2b00 cmp r3, #0
|
|
800547c: d1f0 bne.n 8005460 <HAL_RCC_OscConfig+0x3f4>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
|
|
800547e: 687b ldr r3, [r7, #4]
|
|
8005480: 69da ldr r2, [r3, #28]
|
|
8005482: 687b ldr r3, [r7, #4]
|
|
8005484: 6a1b ldr r3, [r3, #32]
|
|
8005486: 431a orrs r2, r3
|
|
8005488: 687b ldr r3, [r7, #4]
|
|
800548a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800548c: 019b lsls r3, r3, #6
|
|
800548e: 431a orrs r2, r3
|
|
8005490: 687b ldr r3, [r7, #4]
|
|
8005492: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005494: 085b lsrs r3, r3, #1
|
|
8005496: 3b01 subs r3, #1
|
|
8005498: 041b lsls r3, r3, #16
|
|
800549a: 431a orrs r2, r3
|
|
800549c: 687b ldr r3, [r7, #4]
|
|
800549e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80054a0: 061b lsls r3, r3, #24
|
|
80054a2: 431a orrs r2, r3
|
|
80054a4: 687b ldr r3, [r7, #4]
|
|
80054a6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80054a8: 071b lsls r3, r3, #28
|
|
80054aa: 491b ldr r1, [pc, #108] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
80054ac: 4313 orrs r3, r2
|
|
80054ae: 604b str r3, [r1, #4]
|
|
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
|
|
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
80054b0: 4b1b ldr r3, [pc, #108] @ (8005520 <HAL_RCC_OscConfig+0x4b4>)
|
|
80054b2: 2201 movs r2, #1
|
|
80054b4: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80054b6: f7fc fc91 bl 8001ddc <HAL_GetTick>
|
|
80054ba: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
80054bc: e008 b.n 80054d0 <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80054be: f7fc fc8d bl 8001ddc <HAL_GetTick>
|
|
80054c2: 4602 mov r2, r0
|
|
80054c4: 693b ldr r3, [r7, #16]
|
|
80054c6: 1ad3 subs r3, r2, r3
|
|
80054c8: 2b02 cmp r3, #2
|
|
80054ca: d901 bls.n 80054d0 <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80054cc: 2303 movs r3, #3
|
|
80054ce: e064 b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
80054d0: 4b11 ldr r3, [pc, #68] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
80054d2: 681b ldr r3, [r3, #0]
|
|
80054d4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80054d8: 2b00 cmp r3, #0
|
|
80054da: d0f0 beq.n 80054be <HAL_RCC_OscConfig+0x452>
|
|
80054dc: e05c b.n 8005598 <HAL_RCC_OscConfig+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
80054de: 4b10 ldr r3, [pc, #64] @ (8005520 <HAL_RCC_OscConfig+0x4b4>)
|
|
80054e0: 2200 movs r2, #0
|
|
80054e2: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80054e4: f7fc fc7a bl 8001ddc <HAL_GetTick>
|
|
80054e8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80054ea: e008 b.n 80054fe <HAL_RCC_OscConfig+0x492>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80054ec: f7fc fc76 bl 8001ddc <HAL_GetTick>
|
|
80054f0: 4602 mov r2, r0
|
|
80054f2: 693b ldr r3, [r7, #16]
|
|
80054f4: 1ad3 subs r3, r2, r3
|
|
80054f6: 2b02 cmp r3, #2
|
|
80054f8: d901 bls.n 80054fe <HAL_RCC_OscConfig+0x492>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80054fa: 2303 movs r3, #3
|
|
80054fc: e04d b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80054fe: 4b06 ldr r3, [pc, #24] @ (8005518 <HAL_RCC_OscConfig+0x4ac>)
|
|
8005500: 681b ldr r3, [r3, #0]
|
|
8005502: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8005506: 2b00 cmp r3, #0
|
|
8005508: d1f0 bne.n 80054ec <HAL_RCC_OscConfig+0x480>
|
|
800550a: e045 b.n 8005598 <HAL_RCC_OscConfig+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
800550c: 687b ldr r3, [r7, #4]
|
|
800550e: 699b ldr r3, [r3, #24]
|
|
8005510: 2b01 cmp r3, #1
|
|
8005512: d107 bne.n 8005524 <HAL_RCC_OscConfig+0x4b8>
|
|
{
|
|
return HAL_ERROR;
|
|
8005514: 2301 movs r3, #1
|
|
8005516: e040 b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
8005518: 40023800 .word 0x40023800
|
|
800551c: 40007000 .word 0x40007000
|
|
8005520: 42470060 .word 0x42470060
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->PLLCFGR;
|
|
8005524: 4b1f ldr r3, [pc, #124] @ (80055a4 <HAL_RCC_OscConfig+0x538>)
|
|
8005526: 685b ldr r3, [r3, #4]
|
|
8005528: 60fb str r3, [r7, #12]
|
|
#if defined (RCC_PLLCFGR_PLLR)
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
800552a: 687b ldr r3, [r7, #4]
|
|
800552c: 699b ldr r3, [r3, #24]
|
|
800552e: 2b01 cmp r3, #1
|
|
8005530: d030 beq.n 8005594 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8005532: 68fb ldr r3, [r7, #12]
|
|
8005534: f403 0280 and.w r2, r3, #4194304 @ 0x400000
|
|
8005538: 687b ldr r3, [r7, #4]
|
|
800553a: 69db ldr r3, [r3, #28]
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
800553c: 429a cmp r2, r3
|
|
800553e: d129 bne.n 8005594 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
8005540: 68fb ldr r3, [r7, #12]
|
|
8005542: f003 023f and.w r2, r3, #63 @ 0x3f
|
|
8005546: 687b ldr r3, [r7, #4]
|
|
8005548: 6a1b ldr r3, [r3, #32]
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800554a: 429a cmp r2, r3
|
|
800554c: d122 bne.n 8005594 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
800554e: 68fa ldr r2, [r7, #12]
|
|
8005550: f647 73c0 movw r3, #32704 @ 0x7fc0
|
|
8005554: 4013 ands r3, r2
|
|
8005556: 687a ldr r2, [r7, #4]
|
|
8005558: 6a52 ldr r2, [r2, #36] @ 0x24
|
|
800555a: 0192 lsls r2, r2, #6
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
800555c: 4293 cmp r3, r2
|
|
800555e: d119 bne.n 8005594 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
8005560: 68fb ldr r3, [r7, #12]
|
|
8005562: f403 3240 and.w r2, r3, #196608 @ 0x30000
|
|
8005566: 687b ldr r3, [r7, #4]
|
|
8005568: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800556a: 085b lsrs r3, r3, #1
|
|
800556c: 3b01 subs r3, #1
|
|
800556e: 041b lsls r3, r3, #16
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
8005570: 429a cmp r2, r3
|
|
8005572: d10f bne.n 8005594 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
8005574: 68fb ldr r3, [r7, #12]
|
|
8005576: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
|
|
800557a: 687b ldr r3, [r7, #4]
|
|
800557c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800557e: 061b lsls r3, r3, #24
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
8005580: 429a cmp r2, r3
|
|
8005582: d107 bne.n 8005594 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
|
|
8005584: 68fb ldr r3, [r7, #12]
|
|
8005586: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000
|
|
800558a: 687b ldr r3, [r7, #4]
|
|
800558c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800558e: 071b lsls r3, r3, #28
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
8005590: 429a cmp r2, r3
|
|
8005592: d001 beq.n 8005598 <HAL_RCC_OscConfig+0x52c>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
|
|
#endif /* RCC_PLLCFGR_PLLR */
|
|
{
|
|
return HAL_ERROR;
|
|
8005594: 2301 movs r3, #1
|
|
8005596: e000 b.n 800559a <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8005598: 2300 movs r3, #0
|
|
}
|
|
800559a: 4618 mov r0, r3
|
|
800559c: 3718 adds r7, #24
|
|
800559e: 46bd mov sp, r7
|
|
80055a0: bd80 pop {r7, pc}
|
|
80055a2: bf00 nop
|
|
80055a4: 40023800 .word 0x40023800
|
|
|
|
080055a8 <HAL_TIM_OC_Init>:
|
|
* Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
|
|
* @param htim TIM Output Compare handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
80055a8: b580 push {r7, lr}
|
|
80055aa: b082 sub sp, #8
|
|
80055ac: af00 add r7, sp, #0
|
|
80055ae: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
80055b0: 687b ldr r3, [r7, #4]
|
|
80055b2: 2b00 cmp r3, #0
|
|
80055b4: d101 bne.n 80055ba <HAL_TIM_OC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80055b6: 2301 movs r3, #1
|
|
80055b8: e041 b.n 800563e <HAL_TIM_OC_Init+0x96>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
80055ba: 687b ldr r3, [r7, #4]
|
|
80055bc: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
80055c0: b2db uxtb r3, r3
|
|
80055c2: 2b00 cmp r3, #0
|
|
80055c4: d106 bne.n 80055d4 <HAL_TIM_OC_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
80055c6: 687b ldr r3, [r7, #4]
|
|
80055c8: 2200 movs r2, #0
|
|
80055ca: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->OC_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_OC_MspInit(htim);
|
|
80055ce: 6878 ldr r0, [r7, #4]
|
|
80055d0: f7fb ff6a bl 80014a8 <HAL_TIM_OC_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80055d4: 687b ldr r3, [r7, #4]
|
|
80055d6: 2202 movs r2, #2
|
|
80055d8: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Init the base time for the Output Compare */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
80055dc: 687b ldr r3, [r7, #4]
|
|
80055de: 681a ldr r2, [r3, #0]
|
|
80055e0: 687b ldr r3, [r7, #4]
|
|
80055e2: 3304 adds r3, #4
|
|
80055e4: 4619 mov r1, r3
|
|
80055e6: 4610 mov r0, r2
|
|
80055e8: f000 f9be bl 8005968 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
80055ec: 687b ldr r3, [r7, #4]
|
|
80055ee: 2201 movs r2, #1
|
|
80055f0: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
80055f4: 687b ldr r3, [r7, #4]
|
|
80055f6: 2201 movs r2, #1
|
|
80055f8: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
80055fc: 687b ldr r3, [r7, #4]
|
|
80055fe: 2201 movs r2, #1
|
|
8005600: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
8005604: 687b ldr r3, [r7, #4]
|
|
8005606: 2201 movs r2, #1
|
|
8005608: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
800560c: 687b ldr r3, [r7, #4]
|
|
800560e: 2201 movs r2, #1
|
|
8005610: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8005614: 687b ldr r3, [r7, #4]
|
|
8005616: 2201 movs r2, #1
|
|
8005618: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
800561c: 687b ldr r3, [r7, #4]
|
|
800561e: 2201 movs r2, #1
|
|
8005620: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
8005624: 687b ldr r3, [r7, #4]
|
|
8005626: 2201 movs r2, #1
|
|
8005628: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
800562c: 687b ldr r3, [r7, #4]
|
|
800562e: 2201 movs r2, #1
|
|
8005630: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005634: 687b ldr r3, [r7, #4]
|
|
8005636: 2201 movs r2, #1
|
|
8005638: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
800563c: 2300 movs r3, #0
|
|
}
|
|
800563e: 4618 mov r0, r3
|
|
8005640: 3708 adds r7, #8
|
|
8005642: 46bd mov sp, r7
|
|
8005644: bd80 pop {r7, pc}
|
|
|
|
08005646 <HAL_TIM_Encoder_Init>:
|
|
* @param htim TIM Encoder Interface handle
|
|
* @param sConfig TIM Encoder Interface configuration structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
|
|
{
|
|
8005646: b580 push {r7, lr}
|
|
8005648: b086 sub sp, #24
|
|
800564a: af00 add r7, sp, #0
|
|
800564c: 6078 str r0, [r7, #4]
|
|
800564e: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
8005650: 687b ldr r3, [r7, #4]
|
|
8005652: 2b00 cmp r3, #0
|
|
8005654: d101 bne.n 800565a <HAL_TIM_Encoder_Init+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8005656: 2301 movs r3, #1
|
|
8005658: e097 b.n 800578a <HAL_TIM_Encoder_Init+0x144>
|
|
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
|
|
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
|
|
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
800565a: 687b ldr r3, [r7, #4]
|
|
800565c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8005660: b2db uxtb r3, r3
|
|
8005662: 2b00 cmp r3, #0
|
|
8005664: d106 bne.n 8005674 <HAL_TIM_Encoder_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8005666: 687b ldr r3, [r7, #4]
|
|
8005668: 2200 movs r2, #0
|
|
800566a: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Encoder_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_Encoder_MspInit(htim);
|
|
800566e: 6878 ldr r0, [r7, #4]
|
|
8005670: f7fb ff3a bl 80014e8 <HAL_TIM_Encoder_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005674: 687b ldr r3, [r7, #4]
|
|
8005676: 2202 movs r2, #2
|
|
8005678: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Reset the SMS and ECE bits */
|
|
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
|
|
800567c: 687b ldr r3, [r7, #4]
|
|
800567e: 681b ldr r3, [r3, #0]
|
|
8005680: 689b ldr r3, [r3, #8]
|
|
8005682: 687a ldr r2, [r7, #4]
|
|
8005684: 6812 ldr r2, [r2, #0]
|
|
8005686: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800568a: f023 0307 bic.w r3, r3, #7
|
|
800568e: 6093 str r3, [r2, #8]
|
|
|
|
/* Configure the Time base in the Encoder Mode */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8005690: 687b ldr r3, [r7, #4]
|
|
8005692: 681a ldr r2, [r3, #0]
|
|
8005694: 687b ldr r3, [r7, #4]
|
|
8005696: 3304 adds r3, #4
|
|
8005698: 4619 mov r1, r3
|
|
800569a: 4610 mov r0, r2
|
|
800569c: f000 f964 bl 8005968 <TIM_Base_SetConfig>
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80056a0: 687b ldr r3, [r7, #4]
|
|
80056a2: 681b ldr r3, [r3, #0]
|
|
80056a4: 689b ldr r3, [r3, #8]
|
|
80056a6: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmr1 = htim->Instance->CCMR1;
|
|
80056a8: 687b ldr r3, [r7, #4]
|
|
80056aa: 681b ldr r3, [r3, #0]
|
|
80056ac: 699b ldr r3, [r3, #24]
|
|
80056ae: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = htim->Instance->CCER;
|
|
80056b0: 687b ldr r3, [r7, #4]
|
|
80056b2: 681b ldr r3, [r3, #0]
|
|
80056b4: 6a1b ldr r3, [r3, #32]
|
|
80056b6: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the encoder Mode */
|
|
tmpsmcr |= sConfig->EncoderMode;
|
|
80056b8: 683b ldr r3, [r7, #0]
|
|
80056ba: 681b ldr r3, [r3, #0]
|
|
80056bc: 697a ldr r2, [r7, #20]
|
|
80056be: 4313 orrs r3, r2
|
|
80056c0: 617b str r3, [r7, #20]
|
|
|
|
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
|
|
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
|
|
80056c2: 693b ldr r3, [r7, #16]
|
|
80056c4: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80056c8: f023 0303 bic.w r3, r3, #3
|
|
80056cc: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
|
|
80056ce: 683b ldr r3, [r7, #0]
|
|
80056d0: 689a ldr r2, [r3, #8]
|
|
80056d2: 683b ldr r3, [r7, #0]
|
|
80056d4: 699b ldr r3, [r3, #24]
|
|
80056d6: 021b lsls r3, r3, #8
|
|
80056d8: 4313 orrs r3, r2
|
|
80056da: 693a ldr r2, [r7, #16]
|
|
80056dc: 4313 orrs r3, r2
|
|
80056de: 613b str r3, [r7, #16]
|
|
|
|
/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
|
|
80056e0: 693b ldr r3, [r7, #16]
|
|
80056e2: f423 6340 bic.w r3, r3, #3072 @ 0xc00
|
|
80056e6: f023 030c bic.w r3, r3, #12
|
|
80056ea: 613b str r3, [r7, #16]
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
|
|
80056ec: 693b ldr r3, [r7, #16]
|
|
80056ee: f423 4370 bic.w r3, r3, #61440 @ 0xf000
|
|
80056f2: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
80056f6: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
|
|
80056f8: 683b ldr r3, [r7, #0]
|
|
80056fa: 68da ldr r2, [r3, #12]
|
|
80056fc: 683b ldr r3, [r7, #0]
|
|
80056fe: 69db ldr r3, [r3, #28]
|
|
8005700: 021b lsls r3, r3, #8
|
|
8005702: 4313 orrs r3, r2
|
|
8005704: 693a ldr r2, [r7, #16]
|
|
8005706: 4313 orrs r3, r2
|
|
8005708: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
|
|
800570a: 683b ldr r3, [r7, #0]
|
|
800570c: 691b ldr r3, [r3, #16]
|
|
800570e: 011a lsls r2, r3, #4
|
|
8005710: 683b ldr r3, [r7, #0]
|
|
8005712: 6a1b ldr r3, [r3, #32]
|
|
8005714: 031b lsls r3, r3, #12
|
|
8005716: 4313 orrs r3, r2
|
|
8005718: 693a ldr r2, [r7, #16]
|
|
800571a: 4313 orrs r3, r2
|
|
800571c: 613b str r3, [r7, #16]
|
|
|
|
/* Set the TI1 and the TI2 Polarities */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
|
|
800571e: 68fb ldr r3, [r7, #12]
|
|
8005720: f023 0322 bic.w r3, r3, #34 @ 0x22
|
|
8005724: 60fb str r3, [r7, #12]
|
|
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
|
|
8005726: 68fb ldr r3, [r7, #12]
|
|
8005728: f023 0388 bic.w r3, r3, #136 @ 0x88
|
|
800572c: 60fb str r3, [r7, #12]
|
|
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
|
|
800572e: 683b ldr r3, [r7, #0]
|
|
8005730: 685a ldr r2, [r3, #4]
|
|
8005732: 683b ldr r3, [r7, #0]
|
|
8005734: 695b ldr r3, [r3, #20]
|
|
8005736: 011b lsls r3, r3, #4
|
|
8005738: 4313 orrs r3, r2
|
|
800573a: 68fa ldr r2, [r7, #12]
|
|
800573c: 4313 orrs r3, r2
|
|
800573e: 60fb str r3, [r7, #12]
|
|
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8005740: 687b ldr r3, [r7, #4]
|
|
8005742: 681b ldr r3, [r3, #0]
|
|
8005744: 697a ldr r2, [r7, #20]
|
|
8005746: 609a str r2, [r3, #8]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
htim->Instance->CCMR1 = tmpccmr1;
|
|
8005748: 687b ldr r3, [r7, #4]
|
|
800574a: 681b ldr r3, [r3, #0]
|
|
800574c: 693a ldr r2, [r7, #16]
|
|
800574e: 619a str r2, [r3, #24]
|
|
|
|
/* Write to TIMx CCER */
|
|
htim->Instance->CCER = tmpccer;
|
|
8005750: 687b ldr r3, [r7, #4]
|
|
8005752: 681b ldr r3, [r3, #0]
|
|
8005754: 68fa ldr r2, [r7, #12]
|
|
8005756: 621a str r2, [r3, #32]
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8005758: 687b ldr r3, [r7, #4]
|
|
800575a: 2201 movs r2, #1
|
|
800575c: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Set the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
8005760: 687b ldr r3, [r7, #4]
|
|
8005762: 2201 movs r2, #1
|
|
8005764: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
8005768: 687b ldr r3, [r7, #4]
|
|
800576a: 2201 movs r2, #1
|
|
800576c: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
8005770: 687b ldr r3, [r7, #4]
|
|
8005772: 2201 movs r2, #1
|
|
8005774: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
8005778: 687b ldr r3, [r7, #4]
|
|
800577a: 2201 movs r2, #1
|
|
800577c: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005780: 687b ldr r3, [r7, #4]
|
|
8005782: 2201 movs r2, #1
|
|
8005784: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
8005788: 2300 movs r3, #0
|
|
}
|
|
800578a: 4618 mov r0, r3
|
|
800578c: 3718 adds r7, #24
|
|
800578e: 46bd mov sp, r7
|
|
8005790: bd80 pop {r7, pc}
|
|
|
|
08005792 <HAL_TIM_Encoder_Start>:
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
8005792: b580 push {r7, lr}
|
|
8005794: b084 sub sp, #16
|
|
8005796: af00 add r7, sp, #0
|
|
8005798: 6078 str r0, [r7, #4]
|
|
800579a: 6039 str r1, [r7, #0]
|
|
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
|
|
800579c: 687b ldr r3, [r7, #4]
|
|
800579e: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
|
|
80057a2: 73fb strb r3, [r7, #15]
|
|
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
|
|
80057a4: 687b ldr r3, [r7, #4]
|
|
80057a6: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
|
|
80057aa: 73bb strb r3, [r7, #14]
|
|
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
|
|
80057ac: 687b ldr r3, [r7, #4]
|
|
80057ae: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
80057b2: 737b strb r3, [r7, #13]
|
|
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
|
|
80057b4: 687b ldr r3, [r7, #4]
|
|
80057b6: f893 3043 ldrb.w r3, [r3, #67] @ 0x43
|
|
80057ba: 733b strb r3, [r7, #12]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
|
|
|
|
/* Set the TIM channel(s) state */
|
|
if (Channel == TIM_CHANNEL_1)
|
|
80057bc: 683b ldr r3, [r7, #0]
|
|
80057be: 2b00 cmp r3, #0
|
|
80057c0: d110 bne.n 80057e4 <HAL_TIM_Encoder_Start+0x52>
|
|
{
|
|
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
80057c2: 7bfb ldrb r3, [r7, #15]
|
|
80057c4: 2b01 cmp r3, #1
|
|
80057c6: d102 bne.n 80057ce <HAL_TIM_Encoder_Start+0x3c>
|
|
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
|
|
80057c8: 7b7b ldrb r3, [r7, #13]
|
|
80057ca: 2b01 cmp r3, #1
|
|
80057cc: d001 beq.n 80057d2 <HAL_TIM_Encoder_Start+0x40>
|
|
{
|
|
return HAL_ERROR;
|
|
80057ce: 2301 movs r3, #1
|
|
80057d0: e069 b.n 80058a6 <HAL_TIM_Encoder_Start+0x114>
|
|
}
|
|
else
|
|
{
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
80057d2: 687b ldr r3, [r7, #4]
|
|
80057d4: 2202 movs r2, #2
|
|
80057d6: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
80057da: 687b ldr r3, [r7, #4]
|
|
80057dc: 2202 movs r2, #2
|
|
80057de: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
80057e2: e031 b.n 8005848 <HAL_TIM_Encoder_Start+0xb6>
|
|
}
|
|
}
|
|
else if (Channel == TIM_CHANNEL_2)
|
|
80057e4: 683b ldr r3, [r7, #0]
|
|
80057e6: 2b04 cmp r3, #4
|
|
80057e8: d110 bne.n 800580c <HAL_TIM_Encoder_Start+0x7a>
|
|
{
|
|
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
80057ea: 7bbb ldrb r3, [r7, #14]
|
|
80057ec: 2b01 cmp r3, #1
|
|
80057ee: d102 bne.n 80057f6 <HAL_TIM_Encoder_Start+0x64>
|
|
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
|
|
80057f0: 7b3b ldrb r3, [r7, #12]
|
|
80057f2: 2b01 cmp r3, #1
|
|
80057f4: d001 beq.n 80057fa <HAL_TIM_Encoder_Start+0x68>
|
|
{
|
|
return HAL_ERROR;
|
|
80057f6: 2301 movs r3, #1
|
|
80057f8: e055 b.n 80058a6 <HAL_TIM_Encoder_Start+0x114>
|
|
}
|
|
else
|
|
{
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
80057fa: 687b ldr r3, [r7, #4]
|
|
80057fc: 2202 movs r2, #2
|
|
80057fe: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8005802: 687b ldr r3, [r7, #4]
|
|
8005804: 2202 movs r2, #2
|
|
8005806: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
800580a: e01d b.n 8005848 <HAL_TIM_Encoder_Start+0xb6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
800580c: 7bfb ldrb r3, [r7, #15]
|
|
800580e: 2b01 cmp r3, #1
|
|
8005810: d108 bne.n 8005824 <HAL_TIM_Encoder_Start+0x92>
|
|
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
8005812: 7bbb ldrb r3, [r7, #14]
|
|
8005814: 2b01 cmp r3, #1
|
|
8005816: d105 bne.n 8005824 <HAL_TIM_Encoder_Start+0x92>
|
|
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
8005818: 7b7b ldrb r3, [r7, #13]
|
|
800581a: 2b01 cmp r3, #1
|
|
800581c: d102 bne.n 8005824 <HAL_TIM_Encoder_Start+0x92>
|
|
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
|
|
800581e: 7b3b ldrb r3, [r7, #12]
|
|
8005820: 2b01 cmp r3, #1
|
|
8005822: d001 beq.n 8005828 <HAL_TIM_Encoder_Start+0x96>
|
|
{
|
|
return HAL_ERROR;
|
|
8005824: 2301 movs r3, #1
|
|
8005826: e03e b.n 80058a6 <HAL_TIM_Encoder_Start+0x114>
|
|
}
|
|
else
|
|
{
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8005828: 687b ldr r3, [r7, #4]
|
|
800582a: 2202 movs r2, #2
|
|
800582c: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8005830: 687b ldr r3, [r7, #4]
|
|
8005832: 2202 movs r2, #2
|
|
8005834: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8005838: 687b ldr r3, [r7, #4]
|
|
800583a: 2202 movs r2, #2
|
|
800583c: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8005840: 687b ldr r3, [r7, #4]
|
|
8005842: 2202 movs r2, #2
|
|
8005844: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
}
|
|
}
|
|
|
|
/* Enable the encoder interface channels */
|
|
switch (Channel)
|
|
8005848: 683b ldr r3, [r7, #0]
|
|
800584a: 2b00 cmp r3, #0
|
|
800584c: d003 beq.n 8005856 <HAL_TIM_Encoder_Start+0xc4>
|
|
800584e: 683b ldr r3, [r7, #0]
|
|
8005850: 2b04 cmp r3, #4
|
|
8005852: d008 beq.n 8005866 <HAL_TIM_Encoder_Start+0xd4>
|
|
8005854: e00f b.n 8005876 <HAL_TIM_Encoder_Start+0xe4>
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
8005856: 687b ldr r3, [r7, #4]
|
|
8005858: 681b ldr r3, [r3, #0]
|
|
800585a: 2201 movs r2, #1
|
|
800585c: 2100 movs r1, #0
|
|
800585e: 4618 mov r0, r3
|
|
8005860: f000 fad8 bl 8005e14 <TIM_CCxChannelCmd>
|
|
break;
|
|
8005864: e016 b.n 8005894 <HAL_TIM_Encoder_Start+0x102>
|
|
}
|
|
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
8005866: 687b ldr r3, [r7, #4]
|
|
8005868: 681b ldr r3, [r3, #0]
|
|
800586a: 2201 movs r2, #1
|
|
800586c: 2104 movs r1, #4
|
|
800586e: 4618 mov r0, r3
|
|
8005870: f000 fad0 bl 8005e14 <TIM_CCxChannelCmd>
|
|
break;
|
|
8005874: e00e b.n 8005894 <HAL_TIM_Encoder_Start+0x102>
|
|
}
|
|
|
|
default :
|
|
{
|
|
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
8005876: 687b ldr r3, [r7, #4]
|
|
8005878: 681b ldr r3, [r3, #0]
|
|
800587a: 2201 movs r2, #1
|
|
800587c: 2100 movs r1, #0
|
|
800587e: 4618 mov r0, r3
|
|
8005880: f000 fac8 bl 8005e14 <TIM_CCxChannelCmd>
|
|
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
8005884: 687b ldr r3, [r7, #4]
|
|
8005886: 681b ldr r3, [r3, #0]
|
|
8005888: 2201 movs r2, #1
|
|
800588a: 2104 movs r1, #4
|
|
800588c: 4618 mov r0, r3
|
|
800588e: f000 fac1 bl 8005e14 <TIM_CCxChannelCmd>
|
|
break;
|
|
8005892: bf00 nop
|
|
}
|
|
}
|
|
/* Enable the Peripheral */
|
|
__HAL_TIM_ENABLE(htim);
|
|
8005894: 687b ldr r3, [r7, #4]
|
|
8005896: 681b ldr r3, [r3, #0]
|
|
8005898: 681a ldr r2, [r3, #0]
|
|
800589a: 687b ldr r3, [r7, #4]
|
|
800589c: 681b ldr r3, [r3, #0]
|
|
800589e: f042 0201 orr.w r2, r2, #1
|
|
80058a2: 601a str r2, [r3, #0]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80058a4: 2300 movs r3, #0
|
|
}
|
|
80058a6: 4618 mov r0, r3
|
|
80058a8: 3710 adds r7, #16
|
|
80058aa: 46bd mov sp, r7
|
|
80058ac: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080058b0 <HAL_TIM_OC_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
const TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
80058b0: b580 push {r7, lr}
|
|
80058b2: b086 sub sp, #24
|
|
80058b4: af00 add r7, sp, #0
|
|
80058b6: 60f8 str r0, [r7, #12]
|
|
80058b8: 60b9 str r1, [r7, #8]
|
|
80058ba: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80058bc: 2300 movs r3, #0
|
|
80058be: 75fb strb r3, [r7, #23]
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
80058c0: 68fb ldr r3, [r7, #12]
|
|
80058c2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
80058c6: 2b01 cmp r3, #1
|
|
80058c8: d101 bne.n 80058ce <HAL_TIM_OC_ConfigChannel+0x1e>
|
|
80058ca: 2302 movs r3, #2
|
|
80058cc: e048 b.n 8005960 <HAL_TIM_OC_ConfigChannel+0xb0>
|
|
80058ce: 68fb ldr r3, [r7, #12]
|
|
80058d0: 2201 movs r2, #1
|
|
80058d2: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
switch (Channel)
|
|
80058d6: 687b ldr r3, [r7, #4]
|
|
80058d8: 2b0c cmp r3, #12
|
|
80058da: d839 bhi.n 8005950 <HAL_TIM_OC_ConfigChannel+0xa0>
|
|
80058dc: a201 add r2, pc, #4 @ (adr r2, 80058e4 <HAL_TIM_OC_ConfigChannel+0x34>)
|
|
80058de: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80058e2: bf00 nop
|
|
80058e4: 08005919 .word 0x08005919
|
|
80058e8: 08005951 .word 0x08005951
|
|
80058ec: 08005951 .word 0x08005951
|
|
80058f0: 08005951 .word 0x08005951
|
|
80058f4: 08005927 .word 0x08005927
|
|
80058f8: 08005951 .word 0x08005951
|
|
80058fc: 08005951 .word 0x08005951
|
|
8005900: 08005951 .word 0x08005951
|
|
8005904: 08005935 .word 0x08005935
|
|
8005908: 08005951 .word 0x08005951
|
|
800590c: 08005951 .word 0x08005951
|
|
8005910: 08005951 .word 0x08005951
|
|
8005914: 08005943 .word 0x08005943
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 1 in Output Compare */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
8005918: 68fb ldr r3, [r7, #12]
|
|
800591a: 681b ldr r3, [r3, #0]
|
|
800591c: 68b9 ldr r1, [r7, #8]
|
|
800591e: 4618 mov r0, r3
|
|
8005920: f000 f8c8 bl 8005ab4 <TIM_OC1_SetConfig>
|
|
break;
|
|
8005924: e017 b.n 8005956 <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 2 in Output Compare */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
8005926: 68fb ldr r3, [r7, #12]
|
|
8005928: 681b ldr r3, [r3, #0]
|
|
800592a: 68b9 ldr r1, [r7, #8]
|
|
800592c: 4618 mov r0, r3
|
|
800592e: f000 f931 bl 8005b94 <TIM_OC2_SetConfig>
|
|
break;
|
|
8005932: e010 b.n 8005956 <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 3 in Output Compare */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
8005934: 68fb ldr r3, [r7, #12]
|
|
8005936: 681b ldr r3, [r3, #0]
|
|
8005938: 68b9 ldr r1, [r7, #8]
|
|
800593a: 4618 mov r0, r3
|
|
800593c: f000 f9a0 bl 8005c80 <TIM_OC3_SetConfig>
|
|
break;
|
|
8005940: e009 b.n 8005956 <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 4 in Output Compare */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
8005942: 68fb ldr r3, [r7, #12]
|
|
8005944: 681b ldr r3, [r3, #0]
|
|
8005946: 68b9 ldr r1, [r7, #8]
|
|
8005948: 4618 mov r0, r3
|
|
800594a: f000 fa0d bl 8005d68 <TIM_OC4_SetConfig>
|
|
break;
|
|
800594e: e002 b.n 8005956 <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
8005950: 2301 movs r3, #1
|
|
8005952: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8005954: bf00 nop
|
|
}
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8005956: 68fb ldr r3, [r7, #12]
|
|
8005958: 2200 movs r2, #0
|
|
800595a: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
800595e: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8005960: 4618 mov r0, r3
|
|
8005962: 3718 adds r7, #24
|
|
8005964: 46bd mov sp, r7
|
|
8005966: bd80 pop {r7, pc}
|
|
|
|
08005968 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8005968: b480 push {r7}
|
|
800596a: b085 sub sp, #20
|
|
800596c: af00 add r7, sp, #0
|
|
800596e: 6078 str r0, [r7, #4]
|
|
8005970: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
8005972: 687b ldr r3, [r7, #4]
|
|
8005974: 681b ldr r3, [r3, #0]
|
|
8005976: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8005978: 687b ldr r3, [r7, #4]
|
|
800597a: 4a43 ldr r2, [pc, #268] @ (8005a88 <TIM_Base_SetConfig+0x120>)
|
|
800597c: 4293 cmp r3, r2
|
|
800597e: d013 beq.n 80059a8 <TIM_Base_SetConfig+0x40>
|
|
8005980: 687b ldr r3, [r7, #4]
|
|
8005982: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8005986: d00f beq.n 80059a8 <TIM_Base_SetConfig+0x40>
|
|
8005988: 687b ldr r3, [r7, #4]
|
|
800598a: 4a40 ldr r2, [pc, #256] @ (8005a8c <TIM_Base_SetConfig+0x124>)
|
|
800598c: 4293 cmp r3, r2
|
|
800598e: d00b beq.n 80059a8 <TIM_Base_SetConfig+0x40>
|
|
8005990: 687b ldr r3, [r7, #4]
|
|
8005992: 4a3f ldr r2, [pc, #252] @ (8005a90 <TIM_Base_SetConfig+0x128>)
|
|
8005994: 4293 cmp r3, r2
|
|
8005996: d007 beq.n 80059a8 <TIM_Base_SetConfig+0x40>
|
|
8005998: 687b ldr r3, [r7, #4]
|
|
800599a: 4a3e ldr r2, [pc, #248] @ (8005a94 <TIM_Base_SetConfig+0x12c>)
|
|
800599c: 4293 cmp r3, r2
|
|
800599e: d003 beq.n 80059a8 <TIM_Base_SetConfig+0x40>
|
|
80059a0: 687b ldr r3, [r7, #4]
|
|
80059a2: 4a3d ldr r2, [pc, #244] @ (8005a98 <TIM_Base_SetConfig+0x130>)
|
|
80059a4: 4293 cmp r3, r2
|
|
80059a6: d108 bne.n 80059ba <TIM_Base_SetConfig+0x52>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
80059a8: 68fb ldr r3, [r7, #12]
|
|
80059aa: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80059ae: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
80059b0: 683b ldr r3, [r7, #0]
|
|
80059b2: 685b ldr r3, [r3, #4]
|
|
80059b4: 68fa ldr r2, [r7, #12]
|
|
80059b6: 4313 orrs r3, r2
|
|
80059b8: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80059ba: 687b ldr r3, [r7, #4]
|
|
80059bc: 4a32 ldr r2, [pc, #200] @ (8005a88 <TIM_Base_SetConfig+0x120>)
|
|
80059be: 4293 cmp r3, r2
|
|
80059c0: d02b beq.n 8005a1a <TIM_Base_SetConfig+0xb2>
|
|
80059c2: 687b ldr r3, [r7, #4]
|
|
80059c4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80059c8: d027 beq.n 8005a1a <TIM_Base_SetConfig+0xb2>
|
|
80059ca: 687b ldr r3, [r7, #4]
|
|
80059cc: 4a2f ldr r2, [pc, #188] @ (8005a8c <TIM_Base_SetConfig+0x124>)
|
|
80059ce: 4293 cmp r3, r2
|
|
80059d0: d023 beq.n 8005a1a <TIM_Base_SetConfig+0xb2>
|
|
80059d2: 687b ldr r3, [r7, #4]
|
|
80059d4: 4a2e ldr r2, [pc, #184] @ (8005a90 <TIM_Base_SetConfig+0x128>)
|
|
80059d6: 4293 cmp r3, r2
|
|
80059d8: d01f beq.n 8005a1a <TIM_Base_SetConfig+0xb2>
|
|
80059da: 687b ldr r3, [r7, #4]
|
|
80059dc: 4a2d ldr r2, [pc, #180] @ (8005a94 <TIM_Base_SetConfig+0x12c>)
|
|
80059de: 4293 cmp r3, r2
|
|
80059e0: d01b beq.n 8005a1a <TIM_Base_SetConfig+0xb2>
|
|
80059e2: 687b ldr r3, [r7, #4]
|
|
80059e4: 4a2c ldr r2, [pc, #176] @ (8005a98 <TIM_Base_SetConfig+0x130>)
|
|
80059e6: 4293 cmp r3, r2
|
|
80059e8: d017 beq.n 8005a1a <TIM_Base_SetConfig+0xb2>
|
|
80059ea: 687b ldr r3, [r7, #4]
|
|
80059ec: 4a2b ldr r2, [pc, #172] @ (8005a9c <TIM_Base_SetConfig+0x134>)
|
|
80059ee: 4293 cmp r3, r2
|
|
80059f0: d013 beq.n 8005a1a <TIM_Base_SetConfig+0xb2>
|
|
80059f2: 687b ldr r3, [r7, #4]
|
|
80059f4: 4a2a ldr r2, [pc, #168] @ (8005aa0 <TIM_Base_SetConfig+0x138>)
|
|
80059f6: 4293 cmp r3, r2
|
|
80059f8: d00f beq.n 8005a1a <TIM_Base_SetConfig+0xb2>
|
|
80059fa: 687b ldr r3, [r7, #4]
|
|
80059fc: 4a29 ldr r2, [pc, #164] @ (8005aa4 <TIM_Base_SetConfig+0x13c>)
|
|
80059fe: 4293 cmp r3, r2
|
|
8005a00: d00b beq.n 8005a1a <TIM_Base_SetConfig+0xb2>
|
|
8005a02: 687b ldr r3, [r7, #4]
|
|
8005a04: 4a28 ldr r2, [pc, #160] @ (8005aa8 <TIM_Base_SetConfig+0x140>)
|
|
8005a06: 4293 cmp r3, r2
|
|
8005a08: d007 beq.n 8005a1a <TIM_Base_SetConfig+0xb2>
|
|
8005a0a: 687b ldr r3, [r7, #4]
|
|
8005a0c: 4a27 ldr r2, [pc, #156] @ (8005aac <TIM_Base_SetConfig+0x144>)
|
|
8005a0e: 4293 cmp r3, r2
|
|
8005a10: d003 beq.n 8005a1a <TIM_Base_SetConfig+0xb2>
|
|
8005a12: 687b ldr r3, [r7, #4]
|
|
8005a14: 4a26 ldr r2, [pc, #152] @ (8005ab0 <TIM_Base_SetConfig+0x148>)
|
|
8005a16: 4293 cmp r3, r2
|
|
8005a18: d108 bne.n 8005a2c <TIM_Base_SetConfig+0xc4>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
8005a1a: 68fb ldr r3, [r7, #12]
|
|
8005a1c: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8005a20: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
8005a22: 683b ldr r3, [r7, #0]
|
|
8005a24: 68db ldr r3, [r3, #12]
|
|
8005a26: 68fa ldr r2, [r7, #12]
|
|
8005a28: 4313 orrs r3, r2
|
|
8005a2a: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
8005a2c: 68fb ldr r3, [r7, #12]
|
|
8005a2e: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
8005a32: 683b ldr r3, [r7, #0]
|
|
8005a34: 695b ldr r3, [r3, #20]
|
|
8005a36: 4313 orrs r3, r2
|
|
8005a38: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
8005a3a: 683b ldr r3, [r7, #0]
|
|
8005a3c: 689a ldr r2, [r3, #8]
|
|
8005a3e: 687b ldr r3, [r7, #4]
|
|
8005a40: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
8005a42: 683b ldr r3, [r7, #0]
|
|
8005a44: 681a ldr r2, [r3, #0]
|
|
8005a46: 687b ldr r3, [r7, #4]
|
|
8005a48: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
8005a4a: 687b ldr r3, [r7, #4]
|
|
8005a4c: 4a0e ldr r2, [pc, #56] @ (8005a88 <TIM_Base_SetConfig+0x120>)
|
|
8005a4e: 4293 cmp r3, r2
|
|
8005a50: d003 beq.n 8005a5a <TIM_Base_SetConfig+0xf2>
|
|
8005a52: 687b ldr r3, [r7, #4]
|
|
8005a54: 4a10 ldr r2, [pc, #64] @ (8005a98 <TIM_Base_SetConfig+0x130>)
|
|
8005a56: 4293 cmp r3, r2
|
|
8005a58: d103 bne.n 8005a62 <TIM_Base_SetConfig+0xfa>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
8005a5a: 683b ldr r3, [r7, #0]
|
|
8005a5c: 691a ldr r2, [r3, #16]
|
|
8005a5e: 687b ldr r3, [r7, #4]
|
|
8005a60: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Disable Update Event (UEV) with Update Generation (UG)
|
|
by changing Update Request Source (URS) to avoid Update flag (UIF) */
|
|
SET_BIT(TIMx->CR1, TIM_CR1_URS);
|
|
8005a62: 687b ldr r3, [r7, #4]
|
|
8005a64: 681b ldr r3, [r3, #0]
|
|
8005a66: f043 0204 orr.w r2, r3, #4
|
|
8005a6a: 687b ldr r3, [r7, #4]
|
|
8005a6c: 601a str r2, [r3, #0]
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
8005a6e: 687b ldr r3, [r7, #4]
|
|
8005a70: 2201 movs r2, #1
|
|
8005a72: 615a str r2, [r3, #20]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
8005a74: 687b ldr r3, [r7, #4]
|
|
8005a76: 68fa ldr r2, [r7, #12]
|
|
8005a78: 601a str r2, [r3, #0]
|
|
}
|
|
8005a7a: bf00 nop
|
|
8005a7c: 3714 adds r7, #20
|
|
8005a7e: 46bd mov sp, r7
|
|
8005a80: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005a84: 4770 bx lr
|
|
8005a86: bf00 nop
|
|
8005a88: 40010000 .word 0x40010000
|
|
8005a8c: 40000400 .word 0x40000400
|
|
8005a90: 40000800 .word 0x40000800
|
|
8005a94: 40000c00 .word 0x40000c00
|
|
8005a98: 40010400 .word 0x40010400
|
|
8005a9c: 40014000 .word 0x40014000
|
|
8005aa0: 40014400 .word 0x40014400
|
|
8005aa4: 40014800 .word 0x40014800
|
|
8005aa8: 40001800 .word 0x40001800
|
|
8005aac: 40001c00 .word 0x40001c00
|
|
8005ab0: 40002000 .word 0x40002000
|
|
|
|
08005ab4 <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8005ab4: b480 push {r7}
|
|
8005ab6: b087 sub sp, #28
|
|
8005ab8: af00 add r7, sp, #0
|
|
8005aba: 6078 str r0, [r7, #4]
|
|
8005abc: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8005abe: 687b ldr r3, [r7, #4]
|
|
8005ac0: 6a1b ldr r3, [r3, #32]
|
|
8005ac2: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
8005ac4: 687b ldr r3, [r7, #4]
|
|
8005ac6: 6a1b ldr r3, [r3, #32]
|
|
8005ac8: f023 0201 bic.w r2, r3, #1
|
|
8005acc: 687b ldr r3, [r7, #4]
|
|
8005ace: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8005ad0: 687b ldr r3, [r7, #4]
|
|
8005ad2: 685b ldr r3, [r3, #4]
|
|
8005ad4: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8005ad6: 687b ldr r3, [r7, #4]
|
|
8005ad8: 699b ldr r3, [r3, #24]
|
|
8005ada: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
8005adc: 68fb ldr r3, [r7, #12]
|
|
8005ade: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005ae2: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
8005ae4: 68fb ldr r3, [r7, #12]
|
|
8005ae6: f023 0303 bic.w r3, r3, #3
|
|
8005aea: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8005aec: 683b ldr r3, [r7, #0]
|
|
8005aee: 681b ldr r3, [r3, #0]
|
|
8005af0: 68fa ldr r2, [r7, #12]
|
|
8005af2: 4313 orrs r3, r2
|
|
8005af4: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
8005af6: 697b ldr r3, [r7, #20]
|
|
8005af8: f023 0302 bic.w r3, r3, #2
|
|
8005afc: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
8005afe: 683b ldr r3, [r7, #0]
|
|
8005b00: 689b ldr r3, [r3, #8]
|
|
8005b02: 697a ldr r2, [r7, #20]
|
|
8005b04: 4313 orrs r3, r2
|
|
8005b06: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
8005b08: 687b ldr r3, [r7, #4]
|
|
8005b0a: 4a20 ldr r2, [pc, #128] @ (8005b8c <TIM_OC1_SetConfig+0xd8>)
|
|
8005b0c: 4293 cmp r3, r2
|
|
8005b0e: d003 beq.n 8005b18 <TIM_OC1_SetConfig+0x64>
|
|
8005b10: 687b ldr r3, [r7, #4]
|
|
8005b12: 4a1f ldr r2, [pc, #124] @ (8005b90 <TIM_OC1_SetConfig+0xdc>)
|
|
8005b14: 4293 cmp r3, r2
|
|
8005b16: d10c bne.n 8005b32 <TIM_OC1_SetConfig+0x7e>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
8005b18: 697b ldr r3, [r7, #20]
|
|
8005b1a: f023 0308 bic.w r3, r3, #8
|
|
8005b1e: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
8005b20: 683b ldr r3, [r7, #0]
|
|
8005b22: 68db ldr r3, [r3, #12]
|
|
8005b24: 697a ldr r2, [r7, #20]
|
|
8005b26: 4313 orrs r3, r2
|
|
8005b28: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
8005b2a: 697b ldr r3, [r7, #20]
|
|
8005b2c: f023 0304 bic.w r3, r3, #4
|
|
8005b30: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8005b32: 687b ldr r3, [r7, #4]
|
|
8005b34: 4a15 ldr r2, [pc, #84] @ (8005b8c <TIM_OC1_SetConfig+0xd8>)
|
|
8005b36: 4293 cmp r3, r2
|
|
8005b38: d003 beq.n 8005b42 <TIM_OC1_SetConfig+0x8e>
|
|
8005b3a: 687b ldr r3, [r7, #4]
|
|
8005b3c: 4a14 ldr r2, [pc, #80] @ (8005b90 <TIM_OC1_SetConfig+0xdc>)
|
|
8005b3e: 4293 cmp r3, r2
|
|
8005b40: d111 bne.n 8005b66 <TIM_OC1_SetConfig+0xb2>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
8005b42: 693b ldr r3, [r7, #16]
|
|
8005b44: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8005b48: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
8005b4a: 693b ldr r3, [r7, #16]
|
|
8005b4c: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
8005b50: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
8005b52: 683b ldr r3, [r7, #0]
|
|
8005b54: 695b ldr r3, [r3, #20]
|
|
8005b56: 693a ldr r2, [r7, #16]
|
|
8005b58: 4313 orrs r3, r2
|
|
8005b5a: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
8005b5c: 683b ldr r3, [r7, #0]
|
|
8005b5e: 699b ldr r3, [r3, #24]
|
|
8005b60: 693a ldr r2, [r7, #16]
|
|
8005b62: 4313 orrs r3, r2
|
|
8005b64: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005b66: 687b ldr r3, [r7, #4]
|
|
8005b68: 693a ldr r2, [r7, #16]
|
|
8005b6a: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8005b6c: 687b ldr r3, [r7, #4]
|
|
8005b6e: 68fa ldr r2, [r7, #12]
|
|
8005b70: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
8005b72: 683b ldr r3, [r7, #0]
|
|
8005b74: 685a ldr r2, [r3, #4]
|
|
8005b76: 687b ldr r3, [r7, #4]
|
|
8005b78: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8005b7a: 687b ldr r3, [r7, #4]
|
|
8005b7c: 697a ldr r2, [r7, #20]
|
|
8005b7e: 621a str r2, [r3, #32]
|
|
}
|
|
8005b80: bf00 nop
|
|
8005b82: 371c adds r7, #28
|
|
8005b84: 46bd mov sp, r7
|
|
8005b86: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005b8a: 4770 bx lr
|
|
8005b8c: 40010000 .word 0x40010000
|
|
8005b90: 40010400 .word 0x40010400
|
|
|
|
08005b94 <TIM_OC2_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8005b94: b480 push {r7}
|
|
8005b96: b087 sub sp, #28
|
|
8005b98: af00 add r7, sp, #0
|
|
8005b9a: 6078 str r0, [r7, #4]
|
|
8005b9c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8005b9e: 687b ldr r3, [r7, #4]
|
|
8005ba0: 6a1b ldr r3, [r3, #32]
|
|
8005ba2: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8005ba4: 687b ldr r3, [r7, #4]
|
|
8005ba6: 6a1b ldr r3, [r3, #32]
|
|
8005ba8: f023 0210 bic.w r2, r3, #16
|
|
8005bac: 687b ldr r3, [r7, #4]
|
|
8005bae: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8005bb0: 687b ldr r3, [r7, #4]
|
|
8005bb2: 685b ldr r3, [r3, #4]
|
|
8005bb4: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8005bb6: 687b ldr r3, [r7, #4]
|
|
8005bb8: 699b ldr r3, [r3, #24]
|
|
8005bba: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
8005bbc: 68fb ldr r3, [r7, #12]
|
|
8005bbe: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005bc2: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
8005bc4: 68fb ldr r3, [r7, #12]
|
|
8005bc6: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8005bca: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8005bcc: 683b ldr r3, [r7, #0]
|
|
8005bce: 681b ldr r3, [r3, #0]
|
|
8005bd0: 021b lsls r3, r3, #8
|
|
8005bd2: 68fa ldr r2, [r7, #12]
|
|
8005bd4: 4313 orrs r3, r2
|
|
8005bd6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
8005bd8: 697b ldr r3, [r7, #20]
|
|
8005bda: f023 0320 bic.w r3, r3, #32
|
|
8005bde: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
8005be0: 683b ldr r3, [r7, #0]
|
|
8005be2: 689b ldr r3, [r3, #8]
|
|
8005be4: 011b lsls r3, r3, #4
|
|
8005be6: 697a ldr r2, [r7, #20]
|
|
8005be8: 4313 orrs r3, r2
|
|
8005bea: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
8005bec: 687b ldr r3, [r7, #4]
|
|
8005bee: 4a22 ldr r2, [pc, #136] @ (8005c78 <TIM_OC2_SetConfig+0xe4>)
|
|
8005bf0: 4293 cmp r3, r2
|
|
8005bf2: d003 beq.n 8005bfc <TIM_OC2_SetConfig+0x68>
|
|
8005bf4: 687b ldr r3, [r7, #4]
|
|
8005bf6: 4a21 ldr r2, [pc, #132] @ (8005c7c <TIM_OC2_SetConfig+0xe8>)
|
|
8005bf8: 4293 cmp r3, r2
|
|
8005bfa: d10d bne.n 8005c18 <TIM_OC2_SetConfig+0x84>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
8005bfc: 697b ldr r3, [r7, #20]
|
|
8005bfe: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8005c02: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
8005c04: 683b ldr r3, [r7, #0]
|
|
8005c06: 68db ldr r3, [r3, #12]
|
|
8005c08: 011b lsls r3, r3, #4
|
|
8005c0a: 697a ldr r2, [r7, #20]
|
|
8005c0c: 4313 orrs r3, r2
|
|
8005c0e: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
8005c10: 697b ldr r3, [r7, #20]
|
|
8005c12: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005c16: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8005c18: 687b ldr r3, [r7, #4]
|
|
8005c1a: 4a17 ldr r2, [pc, #92] @ (8005c78 <TIM_OC2_SetConfig+0xe4>)
|
|
8005c1c: 4293 cmp r3, r2
|
|
8005c1e: d003 beq.n 8005c28 <TIM_OC2_SetConfig+0x94>
|
|
8005c20: 687b ldr r3, [r7, #4]
|
|
8005c22: 4a16 ldr r2, [pc, #88] @ (8005c7c <TIM_OC2_SetConfig+0xe8>)
|
|
8005c24: 4293 cmp r3, r2
|
|
8005c26: d113 bne.n 8005c50 <TIM_OC2_SetConfig+0xbc>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
8005c28: 693b ldr r3, [r7, #16]
|
|
8005c2a: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8005c2e: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
8005c30: 693b ldr r3, [r7, #16]
|
|
8005c32: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
8005c36: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
8005c38: 683b ldr r3, [r7, #0]
|
|
8005c3a: 695b ldr r3, [r3, #20]
|
|
8005c3c: 009b lsls r3, r3, #2
|
|
8005c3e: 693a ldr r2, [r7, #16]
|
|
8005c40: 4313 orrs r3, r2
|
|
8005c42: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
8005c44: 683b ldr r3, [r7, #0]
|
|
8005c46: 699b ldr r3, [r3, #24]
|
|
8005c48: 009b lsls r3, r3, #2
|
|
8005c4a: 693a ldr r2, [r7, #16]
|
|
8005c4c: 4313 orrs r3, r2
|
|
8005c4e: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005c50: 687b ldr r3, [r7, #4]
|
|
8005c52: 693a ldr r2, [r7, #16]
|
|
8005c54: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8005c56: 687b ldr r3, [r7, #4]
|
|
8005c58: 68fa ldr r2, [r7, #12]
|
|
8005c5a: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
8005c5c: 683b ldr r3, [r7, #0]
|
|
8005c5e: 685a ldr r2, [r3, #4]
|
|
8005c60: 687b ldr r3, [r7, #4]
|
|
8005c62: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8005c64: 687b ldr r3, [r7, #4]
|
|
8005c66: 697a ldr r2, [r7, #20]
|
|
8005c68: 621a str r2, [r3, #32]
|
|
}
|
|
8005c6a: bf00 nop
|
|
8005c6c: 371c adds r7, #28
|
|
8005c6e: 46bd mov sp, r7
|
|
8005c70: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005c74: 4770 bx lr
|
|
8005c76: bf00 nop
|
|
8005c78: 40010000 .word 0x40010000
|
|
8005c7c: 40010400 .word 0x40010400
|
|
|
|
08005c80 <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8005c80: b480 push {r7}
|
|
8005c82: b087 sub sp, #28
|
|
8005c84: af00 add r7, sp, #0
|
|
8005c86: 6078 str r0, [r7, #4]
|
|
8005c88: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8005c8a: 687b ldr r3, [r7, #4]
|
|
8005c8c: 6a1b ldr r3, [r3, #32]
|
|
8005c8e: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
8005c90: 687b ldr r3, [r7, #4]
|
|
8005c92: 6a1b ldr r3, [r3, #32]
|
|
8005c94: f423 7280 bic.w r2, r3, #256 @ 0x100
|
|
8005c98: 687b ldr r3, [r7, #4]
|
|
8005c9a: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8005c9c: 687b ldr r3, [r7, #4]
|
|
8005c9e: 685b ldr r3, [r3, #4]
|
|
8005ca0: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8005ca2: 687b ldr r3, [r7, #4]
|
|
8005ca4: 69db ldr r3, [r3, #28]
|
|
8005ca6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
8005ca8: 68fb ldr r3, [r7, #12]
|
|
8005caa: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005cae: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
8005cb0: 68fb ldr r3, [r7, #12]
|
|
8005cb2: f023 0303 bic.w r3, r3, #3
|
|
8005cb6: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8005cb8: 683b ldr r3, [r7, #0]
|
|
8005cba: 681b ldr r3, [r3, #0]
|
|
8005cbc: 68fa ldr r2, [r7, #12]
|
|
8005cbe: 4313 orrs r3, r2
|
|
8005cc0: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
8005cc2: 697b ldr r3, [r7, #20]
|
|
8005cc4: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
8005cc8: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
8005cca: 683b ldr r3, [r7, #0]
|
|
8005ccc: 689b ldr r3, [r3, #8]
|
|
8005cce: 021b lsls r3, r3, #8
|
|
8005cd0: 697a ldr r2, [r7, #20]
|
|
8005cd2: 4313 orrs r3, r2
|
|
8005cd4: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
8005cd6: 687b ldr r3, [r7, #4]
|
|
8005cd8: 4a21 ldr r2, [pc, #132] @ (8005d60 <TIM_OC3_SetConfig+0xe0>)
|
|
8005cda: 4293 cmp r3, r2
|
|
8005cdc: d003 beq.n 8005ce6 <TIM_OC3_SetConfig+0x66>
|
|
8005cde: 687b ldr r3, [r7, #4]
|
|
8005ce0: 4a20 ldr r2, [pc, #128] @ (8005d64 <TIM_OC3_SetConfig+0xe4>)
|
|
8005ce2: 4293 cmp r3, r2
|
|
8005ce4: d10d bne.n 8005d02 <TIM_OC3_SetConfig+0x82>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
8005ce6: 697b ldr r3, [r7, #20]
|
|
8005ce8: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
8005cec: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
8005cee: 683b ldr r3, [r7, #0]
|
|
8005cf0: 68db ldr r3, [r3, #12]
|
|
8005cf2: 021b lsls r3, r3, #8
|
|
8005cf4: 697a ldr r2, [r7, #20]
|
|
8005cf6: 4313 orrs r3, r2
|
|
8005cf8: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
8005cfa: 697b ldr r3, [r7, #20]
|
|
8005cfc: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8005d00: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8005d02: 687b ldr r3, [r7, #4]
|
|
8005d04: 4a16 ldr r2, [pc, #88] @ (8005d60 <TIM_OC3_SetConfig+0xe0>)
|
|
8005d06: 4293 cmp r3, r2
|
|
8005d08: d003 beq.n 8005d12 <TIM_OC3_SetConfig+0x92>
|
|
8005d0a: 687b ldr r3, [r7, #4]
|
|
8005d0c: 4a15 ldr r2, [pc, #84] @ (8005d64 <TIM_OC3_SetConfig+0xe4>)
|
|
8005d0e: 4293 cmp r3, r2
|
|
8005d10: d113 bne.n 8005d3a <TIM_OC3_SetConfig+0xba>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
8005d12: 693b ldr r3, [r7, #16]
|
|
8005d14: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
8005d18: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
8005d1a: 693b ldr r3, [r7, #16]
|
|
8005d1c: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
8005d20: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
8005d22: 683b ldr r3, [r7, #0]
|
|
8005d24: 695b ldr r3, [r3, #20]
|
|
8005d26: 011b lsls r3, r3, #4
|
|
8005d28: 693a ldr r2, [r7, #16]
|
|
8005d2a: 4313 orrs r3, r2
|
|
8005d2c: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
8005d2e: 683b ldr r3, [r7, #0]
|
|
8005d30: 699b ldr r3, [r3, #24]
|
|
8005d32: 011b lsls r3, r3, #4
|
|
8005d34: 693a ldr r2, [r7, #16]
|
|
8005d36: 4313 orrs r3, r2
|
|
8005d38: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005d3a: 687b ldr r3, [r7, #4]
|
|
8005d3c: 693a ldr r2, [r7, #16]
|
|
8005d3e: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8005d40: 687b ldr r3, [r7, #4]
|
|
8005d42: 68fa ldr r2, [r7, #12]
|
|
8005d44: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
8005d46: 683b ldr r3, [r7, #0]
|
|
8005d48: 685a ldr r2, [r3, #4]
|
|
8005d4a: 687b ldr r3, [r7, #4]
|
|
8005d4c: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8005d4e: 687b ldr r3, [r7, #4]
|
|
8005d50: 697a ldr r2, [r7, #20]
|
|
8005d52: 621a str r2, [r3, #32]
|
|
}
|
|
8005d54: bf00 nop
|
|
8005d56: 371c adds r7, #28
|
|
8005d58: 46bd mov sp, r7
|
|
8005d5a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005d5e: 4770 bx lr
|
|
8005d60: 40010000 .word 0x40010000
|
|
8005d64: 40010400 .word 0x40010400
|
|
|
|
08005d68 <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8005d68: b480 push {r7}
|
|
8005d6a: b087 sub sp, #28
|
|
8005d6c: af00 add r7, sp, #0
|
|
8005d6e: 6078 str r0, [r7, #4]
|
|
8005d70: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8005d72: 687b ldr r3, [r7, #4]
|
|
8005d74: 6a1b ldr r3, [r3, #32]
|
|
8005d76: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
8005d78: 687b ldr r3, [r7, #4]
|
|
8005d7a: 6a1b ldr r3, [r3, #32]
|
|
8005d7c: f423 5280 bic.w r2, r3, #4096 @ 0x1000
|
|
8005d80: 687b ldr r3, [r7, #4]
|
|
8005d82: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8005d84: 687b ldr r3, [r7, #4]
|
|
8005d86: 685b ldr r3, [r3, #4]
|
|
8005d88: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8005d8a: 687b ldr r3, [r7, #4]
|
|
8005d8c: 69db ldr r3, [r3, #28]
|
|
8005d8e: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
8005d90: 68fb ldr r3, [r7, #12]
|
|
8005d92: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8005d96: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
8005d98: 68fb ldr r3, [r7, #12]
|
|
8005d9a: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8005d9e: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8005da0: 683b ldr r3, [r7, #0]
|
|
8005da2: 681b ldr r3, [r3, #0]
|
|
8005da4: 021b lsls r3, r3, #8
|
|
8005da6: 68fa ldr r2, [r7, #12]
|
|
8005da8: 4313 orrs r3, r2
|
|
8005daa: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
8005dac: 693b ldr r3, [r7, #16]
|
|
8005dae: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
8005db2: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
8005db4: 683b ldr r3, [r7, #0]
|
|
8005db6: 689b ldr r3, [r3, #8]
|
|
8005db8: 031b lsls r3, r3, #12
|
|
8005dba: 693a ldr r2, [r7, #16]
|
|
8005dbc: 4313 orrs r3, r2
|
|
8005dbe: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8005dc0: 687b ldr r3, [r7, #4]
|
|
8005dc2: 4a12 ldr r2, [pc, #72] @ (8005e0c <TIM_OC4_SetConfig+0xa4>)
|
|
8005dc4: 4293 cmp r3, r2
|
|
8005dc6: d003 beq.n 8005dd0 <TIM_OC4_SetConfig+0x68>
|
|
8005dc8: 687b ldr r3, [r7, #4]
|
|
8005dca: 4a11 ldr r2, [pc, #68] @ (8005e10 <TIM_OC4_SetConfig+0xa8>)
|
|
8005dcc: 4293 cmp r3, r2
|
|
8005dce: d109 bne.n 8005de4 <TIM_OC4_SetConfig+0x7c>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
8005dd0: 697b ldr r3, [r7, #20]
|
|
8005dd2: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8005dd6: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
8005dd8: 683b ldr r3, [r7, #0]
|
|
8005dda: 695b ldr r3, [r3, #20]
|
|
8005ddc: 019b lsls r3, r3, #6
|
|
8005dde: 697a ldr r2, [r7, #20]
|
|
8005de0: 4313 orrs r3, r2
|
|
8005de2: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005de4: 687b ldr r3, [r7, #4]
|
|
8005de6: 697a ldr r2, [r7, #20]
|
|
8005de8: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8005dea: 687b ldr r3, [r7, #4]
|
|
8005dec: 68fa ldr r2, [r7, #12]
|
|
8005dee: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
8005df0: 683b ldr r3, [r7, #0]
|
|
8005df2: 685a ldr r2, [r3, #4]
|
|
8005df4: 687b ldr r3, [r7, #4]
|
|
8005df6: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8005df8: 687b ldr r3, [r7, #4]
|
|
8005dfa: 693a ldr r2, [r7, #16]
|
|
8005dfc: 621a str r2, [r3, #32]
|
|
}
|
|
8005dfe: bf00 nop
|
|
8005e00: 371c adds r7, #28
|
|
8005e02: 46bd mov sp, r7
|
|
8005e04: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005e08: 4770 bx lr
|
|
8005e0a: bf00 nop
|
|
8005e0c: 40010000 .word 0x40010000
|
|
8005e10: 40010400 .word 0x40010400
|
|
|
|
08005e14 <TIM_CCxChannelCmd>:
|
|
* @param ChannelState specifies the TIM Channel CCxE bit new state.
|
|
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
|
|
* @retval None
|
|
*/
|
|
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
|
|
{
|
|
8005e14: b480 push {r7}
|
|
8005e16: b087 sub sp, #28
|
|
8005e18: af00 add r7, sp, #0
|
|
8005e1a: 60f8 str r0, [r7, #12]
|
|
8005e1c: 60b9 str r1, [r7, #8]
|
|
8005e1e: 607a str r2, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
|
|
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
|
8005e20: 68bb ldr r3, [r7, #8]
|
|
8005e22: f003 031f and.w r3, r3, #31
|
|
8005e26: 2201 movs r2, #1
|
|
8005e28: fa02 f303 lsl.w r3, r2, r3
|
|
8005e2c: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the CCxE Bit */
|
|
TIMx->CCER &= ~tmp;
|
|
8005e2e: 68fb ldr r3, [r7, #12]
|
|
8005e30: 6a1a ldr r2, [r3, #32]
|
|
8005e32: 697b ldr r3, [r7, #20]
|
|
8005e34: 43db mvns r3, r3
|
|
8005e36: 401a ands r2, r3
|
|
8005e38: 68fb ldr r3, [r7, #12]
|
|
8005e3a: 621a str r2, [r3, #32]
|
|
|
|
/* Set or reset the CCxE Bit */
|
|
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
|
8005e3c: 68fb ldr r3, [r7, #12]
|
|
8005e3e: 6a1a ldr r2, [r3, #32]
|
|
8005e40: 68bb ldr r3, [r7, #8]
|
|
8005e42: f003 031f and.w r3, r3, #31
|
|
8005e46: 6879 ldr r1, [r7, #4]
|
|
8005e48: fa01 f303 lsl.w r3, r1, r3
|
|
8005e4c: 431a orrs r2, r3
|
|
8005e4e: 68fb ldr r3, [r7, #12]
|
|
8005e50: 621a str r2, [r3, #32]
|
|
}
|
|
8005e52: bf00 nop
|
|
8005e54: 371c adds r7, #28
|
|
8005e56: 46bd mov sp, r7
|
|
8005e58: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005e5c: 4770 bx lr
|
|
...
|
|
|
|
08005e60 <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
8005e60: b480 push {r7}
|
|
8005e62: b085 sub sp, #20
|
|
8005e64: af00 add r7, sp, #0
|
|
8005e66: 6078 str r0, [r7, #4]
|
|
8005e68: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8005e6a: 687b ldr r3, [r7, #4]
|
|
8005e6c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8005e70: 2b01 cmp r3, #1
|
|
8005e72: d101 bne.n 8005e78 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8005e74: 2302 movs r3, #2
|
|
8005e76: e05a b.n 8005f2e <HAL_TIMEx_MasterConfigSynchronization+0xce>
|
|
8005e78: 687b ldr r3, [r7, #4]
|
|
8005e7a: 2201 movs r2, #1
|
|
8005e7c: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005e80: 687b ldr r3, [r7, #4]
|
|
8005e82: 2202 movs r2, #2
|
|
8005e84: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8005e88: 687b ldr r3, [r7, #4]
|
|
8005e8a: 681b ldr r3, [r3, #0]
|
|
8005e8c: 685b ldr r3, [r3, #4]
|
|
8005e8e: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8005e90: 687b ldr r3, [r7, #4]
|
|
8005e92: 681b ldr r3, [r3, #0]
|
|
8005e94: 689b ldr r3, [r3, #8]
|
|
8005e96: 60bb str r3, [r7, #8]
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8005e98: 68fb ldr r3, [r7, #12]
|
|
8005e9a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005e9e: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8005ea0: 683b ldr r3, [r7, #0]
|
|
8005ea2: 681b ldr r3, [r3, #0]
|
|
8005ea4: 68fa ldr r2, [r7, #12]
|
|
8005ea6: 4313 orrs r3, r2
|
|
8005ea8: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8005eaa: 687b ldr r3, [r7, #4]
|
|
8005eac: 681b ldr r3, [r3, #0]
|
|
8005eae: 68fa ldr r2, [r7, #12]
|
|
8005eb0: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8005eb2: 687b ldr r3, [r7, #4]
|
|
8005eb4: 681b ldr r3, [r3, #0]
|
|
8005eb6: 4a21 ldr r2, [pc, #132] @ (8005f3c <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
|
|
8005eb8: 4293 cmp r3, r2
|
|
8005eba: d022 beq.n 8005f02 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005ebc: 687b ldr r3, [r7, #4]
|
|
8005ebe: 681b ldr r3, [r3, #0]
|
|
8005ec0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8005ec4: d01d beq.n 8005f02 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005ec6: 687b ldr r3, [r7, #4]
|
|
8005ec8: 681b ldr r3, [r3, #0]
|
|
8005eca: 4a1d ldr r2, [pc, #116] @ (8005f40 <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
|
|
8005ecc: 4293 cmp r3, r2
|
|
8005ece: d018 beq.n 8005f02 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005ed0: 687b ldr r3, [r7, #4]
|
|
8005ed2: 681b ldr r3, [r3, #0]
|
|
8005ed4: 4a1b ldr r2, [pc, #108] @ (8005f44 <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
|
|
8005ed6: 4293 cmp r3, r2
|
|
8005ed8: d013 beq.n 8005f02 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005eda: 687b ldr r3, [r7, #4]
|
|
8005edc: 681b ldr r3, [r3, #0]
|
|
8005ede: 4a1a ldr r2, [pc, #104] @ (8005f48 <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
|
|
8005ee0: 4293 cmp r3, r2
|
|
8005ee2: d00e beq.n 8005f02 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005ee4: 687b ldr r3, [r7, #4]
|
|
8005ee6: 681b ldr r3, [r3, #0]
|
|
8005ee8: 4a18 ldr r2, [pc, #96] @ (8005f4c <HAL_TIMEx_MasterConfigSynchronization+0xec>)
|
|
8005eea: 4293 cmp r3, r2
|
|
8005eec: d009 beq.n 8005f02 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005eee: 687b ldr r3, [r7, #4]
|
|
8005ef0: 681b ldr r3, [r3, #0]
|
|
8005ef2: 4a17 ldr r2, [pc, #92] @ (8005f50 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
|
|
8005ef4: 4293 cmp r3, r2
|
|
8005ef6: d004 beq.n 8005f02 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005ef8: 687b ldr r3, [r7, #4]
|
|
8005efa: 681b ldr r3, [r3, #0]
|
|
8005efc: 4a15 ldr r2, [pc, #84] @ (8005f54 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
|
|
8005efe: 4293 cmp r3, r2
|
|
8005f00: d10c bne.n 8005f1c <HAL_TIMEx_MasterConfigSynchronization+0xbc>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
8005f02: 68bb ldr r3, [r7, #8]
|
|
8005f04: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8005f08: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
8005f0a: 683b ldr r3, [r7, #0]
|
|
8005f0c: 685b ldr r3, [r3, #4]
|
|
8005f0e: 68ba ldr r2, [r7, #8]
|
|
8005f10: 4313 orrs r3, r2
|
|
8005f12: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8005f14: 687b ldr r3, [r7, #4]
|
|
8005f16: 681b ldr r3, [r3, #0]
|
|
8005f18: 68ba ldr r2, [r7, #8]
|
|
8005f1a: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005f1c: 687b ldr r3, [r7, #4]
|
|
8005f1e: 2201 movs r2, #1
|
|
8005f20: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8005f24: 687b ldr r3, [r7, #4]
|
|
8005f26: 2200 movs r2, #0
|
|
8005f28: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
8005f2c: 2300 movs r3, #0
|
|
}
|
|
8005f2e: 4618 mov r0, r3
|
|
8005f30: 3714 adds r7, #20
|
|
8005f32: 46bd mov sp, r7
|
|
8005f34: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005f38: 4770 bx lr
|
|
8005f3a: bf00 nop
|
|
8005f3c: 40010000 .word 0x40010000
|
|
8005f40: 40000400 .word 0x40000400
|
|
8005f44: 40000800 .word 0x40000800
|
|
8005f48: 40000c00 .word 0x40000c00
|
|
8005f4c: 40010400 .word 0x40010400
|
|
8005f50: 40014000 .word 0x40014000
|
|
8005f54: 40001800 .word 0x40001800
|
|
|
|
08005f58 <HAL_UART_Init>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8005f58: b580 push {r7, lr}
|
|
8005f5a: b082 sub sp, #8
|
|
8005f5c: af00 add r7, sp, #0
|
|
8005f5e: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8005f60: 687b ldr r3, [r7, #4]
|
|
8005f62: 2b00 cmp r3, #0
|
|
8005f64: d101 bne.n 8005f6a <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8005f66: 2301 movs r3, #1
|
|
8005f68: e042 b.n 8005ff0 <HAL_UART_Init+0x98>
|
|
assert_param(IS_UART_INSTANCE(huart->Instance));
|
|
}
|
|
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
|
|
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8005f6a: 687b ldr r3, [r7, #4]
|
|
8005f6c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8005f70: b2db uxtb r3, r3
|
|
8005f72: 2b00 cmp r3, #0
|
|
8005f74: d106 bne.n 8005f84 <HAL_UART_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8005f76: 687b ldr r3, [r7, #4]
|
|
8005f78: 2200 movs r2, #0
|
|
8005f7a: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8005f7e: 6878 ldr r0, [r7, #4]
|
|
8005f80: f7fb fbda bl 8001738 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8005f84: 687b ldr r3, [r7, #4]
|
|
8005f86: 2224 movs r2, #36 @ 0x24
|
|
8005f88: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_UART_DISABLE(huart);
|
|
8005f8c: 687b ldr r3, [r7, #4]
|
|
8005f8e: 681b ldr r3, [r3, #0]
|
|
8005f90: 68da ldr r2, [r3, #12]
|
|
8005f92: 687b ldr r3, [r7, #4]
|
|
8005f94: 681b ldr r3, [r3, #0]
|
|
8005f96: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
8005f9a: 60da str r2, [r3, #12]
|
|
|
|
/* Set the UART Communication parameters */
|
|
UART_SetConfig(huart);
|
|
8005f9c: 6878 ldr r0, [r7, #4]
|
|
8005f9e: f000 ff63 bl 8006e68 <UART_SetConfig>
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8005fa2: 687b ldr r3, [r7, #4]
|
|
8005fa4: 681b ldr r3, [r3, #0]
|
|
8005fa6: 691a ldr r2, [r3, #16]
|
|
8005fa8: 687b ldr r3, [r7, #4]
|
|
8005faa: 681b ldr r3, [r3, #0]
|
|
8005fac: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
8005fb0: 611a str r2, [r3, #16]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8005fb2: 687b ldr r3, [r7, #4]
|
|
8005fb4: 681b ldr r3, [r3, #0]
|
|
8005fb6: 695a ldr r2, [r3, #20]
|
|
8005fb8: 687b ldr r3, [r7, #4]
|
|
8005fba: 681b ldr r3, [r3, #0]
|
|
8005fbc: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
8005fc0: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the peripheral */
|
|
__HAL_UART_ENABLE(huart);
|
|
8005fc2: 687b ldr r3, [r7, #4]
|
|
8005fc4: 681b ldr r3, [r3, #0]
|
|
8005fc6: 68da ldr r2, [r3, #12]
|
|
8005fc8: 687b ldr r3, [r7, #4]
|
|
8005fca: 681b ldr r3, [r3, #0]
|
|
8005fcc: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
8005fd0: 60da str r2, [r3, #12]
|
|
|
|
/* Initialize the UART state */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8005fd2: 687b ldr r3, [r7, #4]
|
|
8005fd4: 2200 movs r2, #0
|
|
8005fd6: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005fd8: 687b ldr r3, [r7, #4]
|
|
8005fda: 2220 movs r2, #32
|
|
8005fdc: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8005fe0: 687b ldr r3, [r7, #4]
|
|
8005fe2: 2220 movs r2, #32
|
|
8005fe4: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8005fe8: 687b ldr r3, [r7, #4]
|
|
8005fea: 2200 movs r2, #0
|
|
8005fec: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_OK;
|
|
8005fee: 2300 movs r3, #0
|
|
}
|
|
8005ff0: 4618 mov r0, r3
|
|
8005ff2: 3708 adds r7, #8
|
|
8005ff4: 46bd mov sp, r7
|
|
8005ff6: bd80 pop {r7, pc}
|
|
|
|
08005ff8 <HAL_UART_Transmit_DMA>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
|
|
{
|
|
8005ff8: b580 push {r7, lr}
|
|
8005ffa: b08c sub sp, #48 @ 0x30
|
|
8005ffc: af00 add r7, sp, #0
|
|
8005ffe: 60f8 str r0, [r7, #12]
|
|
8006000: 60b9 str r1, [r7, #8]
|
|
8006002: 4613 mov r3, r2
|
|
8006004: 80fb strh r3, [r7, #6]
|
|
const uint32_t *tmp;
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8006006: 68fb ldr r3, [r7, #12]
|
|
8006008: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
800600c: b2db uxtb r3, r3
|
|
800600e: 2b20 cmp r3, #32
|
|
8006010: d162 bne.n 80060d8 <HAL_UART_Transmit_DMA+0xe0>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8006012: 68bb ldr r3, [r7, #8]
|
|
8006014: 2b00 cmp r3, #0
|
|
8006016: d002 beq.n 800601e <HAL_UART_Transmit_DMA+0x26>
|
|
8006018: 88fb ldrh r3, [r7, #6]
|
|
800601a: 2b00 cmp r3, #0
|
|
800601c: d101 bne.n 8006022 <HAL_UART_Transmit_DMA+0x2a>
|
|
{
|
|
return HAL_ERROR;
|
|
800601e: 2301 movs r3, #1
|
|
8006020: e05b b.n 80060da <HAL_UART_Transmit_DMA+0xe2>
|
|
}
|
|
|
|
huart->pTxBuffPtr = pData;
|
|
8006022: 68ba ldr r2, [r7, #8]
|
|
8006024: 68fb ldr r3, [r7, #12]
|
|
8006026: 621a str r2, [r3, #32]
|
|
huart->TxXferSize = Size;
|
|
8006028: 68fb ldr r3, [r7, #12]
|
|
800602a: 88fa ldrh r2, [r7, #6]
|
|
800602c: 849a strh r2, [r3, #36] @ 0x24
|
|
huart->TxXferCount = Size;
|
|
800602e: 68fb ldr r3, [r7, #12]
|
|
8006030: 88fa ldrh r2, [r7, #6]
|
|
8006032: 84da strh r2, [r3, #38] @ 0x26
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8006034: 68fb ldr r3, [r7, #12]
|
|
8006036: 2200 movs r2, #0
|
|
8006038: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
800603a: 68fb ldr r3, [r7, #12]
|
|
800603c: 2221 movs r2, #33 @ 0x21
|
|
800603e: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Set the UART DMA transfer complete callback */
|
|
huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
|
|
8006042: 68fb ldr r3, [r7, #12]
|
|
8006044: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006046: 4a27 ldr r2, [pc, #156] @ (80060e4 <HAL_UART_Transmit_DMA+0xec>)
|
|
8006048: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Set the UART DMA Half transfer complete callback */
|
|
huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
|
|
800604a: 68fb ldr r3, [r7, #12]
|
|
800604c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800604e: 4a26 ldr r2, [pc, #152] @ (80060e8 <HAL_UART_Transmit_DMA+0xf0>)
|
|
8006050: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set the DMA error callback */
|
|
huart->hdmatx->XferErrorCallback = UART_DMAError;
|
|
8006052: 68fb ldr r3, [r7, #12]
|
|
8006054: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006056: 4a25 ldr r2, [pc, #148] @ (80060ec <HAL_UART_Transmit_DMA+0xf4>)
|
|
8006058: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Set the DMA abort callback */
|
|
huart->hdmatx->XferAbortCallback = NULL;
|
|
800605a: 68fb ldr r3, [r7, #12]
|
|
800605c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800605e: 2200 movs r2, #0
|
|
8006060: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Enable the UART transmit DMA stream */
|
|
tmp = (const uint32_t *)&pData;
|
|
8006062: f107 0308 add.w r3, r7, #8
|
|
8006066: 62fb str r3, [r7, #44] @ 0x2c
|
|
if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK)
|
|
8006068: 68fb ldr r3, [r7, #12]
|
|
800606a: 6b98 ldr r0, [r3, #56] @ 0x38
|
|
800606c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800606e: 6819 ldr r1, [r3, #0]
|
|
8006070: 68fb ldr r3, [r7, #12]
|
|
8006072: 681b ldr r3, [r3, #0]
|
|
8006074: 3304 adds r3, #4
|
|
8006076: 461a mov r2, r3
|
|
8006078: 88fb ldrh r3, [r7, #6]
|
|
800607a: f7fc f89f bl 80021bc <HAL_DMA_Start_IT>
|
|
800607e: 4603 mov r3, r0
|
|
8006080: 2b00 cmp r3, #0
|
|
8006082: d008 beq.n 8006096 <HAL_UART_Transmit_DMA+0x9e>
|
|
{
|
|
/* Set error code to DMA */
|
|
huart->ErrorCode = HAL_UART_ERROR_DMA;
|
|
8006084: 68fb ldr r3, [r7, #12]
|
|
8006086: 2210 movs r2, #16
|
|
8006088: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Restore huart->gState to ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800608a: 68fb ldr r3, [r7, #12]
|
|
800608c: 2220 movs r2, #32
|
|
800608e: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
return HAL_ERROR;
|
|
8006092: 2301 movs r3, #1
|
|
8006094: e021 b.n 80060da <HAL_UART_Transmit_DMA+0xe2>
|
|
}
|
|
/* Clear the TC flag in the SR register by writing 0 to it */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
|
|
8006096: 68fb ldr r3, [r7, #12]
|
|
8006098: 681b ldr r3, [r3, #0]
|
|
800609a: f06f 0240 mvn.w r2, #64 @ 0x40
|
|
800609e: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the DMA transfer for transmit request by setting the DMAT bit
|
|
in the UART CR3 register */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
|
80060a0: 68fb ldr r3, [r7, #12]
|
|
80060a2: 681b ldr r3, [r3, #0]
|
|
80060a4: 3314 adds r3, #20
|
|
80060a6: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80060a8: 69bb ldr r3, [r7, #24]
|
|
80060aa: e853 3f00 ldrex r3, [r3]
|
|
80060ae: 617b str r3, [r7, #20]
|
|
return(result);
|
|
80060b0: 697b ldr r3, [r7, #20]
|
|
80060b2: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80060b6: 62bb str r3, [r7, #40] @ 0x28
|
|
80060b8: 68fb ldr r3, [r7, #12]
|
|
80060ba: 681b ldr r3, [r3, #0]
|
|
80060bc: 3314 adds r3, #20
|
|
80060be: 6aba ldr r2, [r7, #40] @ 0x28
|
|
80060c0: 627a str r2, [r7, #36] @ 0x24
|
|
80060c2: 623b str r3, [r7, #32]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80060c4: 6a39 ldr r1, [r7, #32]
|
|
80060c6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80060c8: e841 2300 strex r3, r2, [r1]
|
|
80060cc: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
80060ce: 69fb ldr r3, [r7, #28]
|
|
80060d0: 2b00 cmp r3, #0
|
|
80060d2: d1e5 bne.n 80060a0 <HAL_UART_Transmit_DMA+0xa8>
|
|
|
|
return HAL_OK;
|
|
80060d4: 2300 movs r3, #0
|
|
80060d6: e000 b.n 80060da <HAL_UART_Transmit_DMA+0xe2>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
80060d8: 2302 movs r3, #2
|
|
}
|
|
}
|
|
80060da: 4618 mov r0, r3
|
|
80060dc: 3730 adds r7, #48 @ 0x30
|
|
80060de: 46bd mov sp, r7
|
|
80060e0: bd80 pop {r7, pc}
|
|
80060e2: bf00 nop
|
|
80060e4: 080066e5 .word 0x080066e5
|
|
80060e8: 0800677f .word 0x0800677f
|
|
80060ec: 08006903 .word 0x08006903
|
|
|
|
080060f0 <HAL_UART_Receive_DMA>:
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
80060f0: b580 push {r7, lr}
|
|
80060f2: b084 sub sp, #16
|
|
80060f4: af00 add r7, sp, #0
|
|
80060f6: 60f8 str r0, [r7, #12]
|
|
80060f8: 60b9 str r1, [r7, #8]
|
|
80060fa: 4613 mov r3, r2
|
|
80060fc: 80fb strh r3, [r7, #6]
|
|
/* Check that a Rx process is not already ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
80060fe: 68fb ldr r3, [r7, #12]
|
|
8006100: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
8006104: b2db uxtb r3, r3
|
|
8006106: 2b20 cmp r3, #32
|
|
8006108: d112 bne.n 8006130 <HAL_UART_Receive_DMA+0x40>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
800610a: 68bb ldr r3, [r7, #8]
|
|
800610c: 2b00 cmp r3, #0
|
|
800610e: d002 beq.n 8006116 <HAL_UART_Receive_DMA+0x26>
|
|
8006110: 88fb ldrh r3, [r7, #6]
|
|
8006112: 2b00 cmp r3, #0
|
|
8006114: d101 bne.n 800611a <HAL_UART_Receive_DMA+0x2a>
|
|
{
|
|
return HAL_ERROR;
|
|
8006116: 2301 movs r3, #1
|
|
8006118: e00b b.n 8006132 <HAL_UART_Receive_DMA+0x42>
|
|
}
|
|
|
|
/* Set Reception type to Standard reception */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
800611a: 68fb ldr r3, [r7, #12]
|
|
800611c: 2200 movs r2, #0
|
|
800611e: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
return (UART_Start_Receive_DMA(huart, pData, Size));
|
|
8006120: 88fb ldrh r3, [r7, #6]
|
|
8006122: 461a mov r2, r3
|
|
8006124: 68b9 ldr r1, [r7, #8]
|
|
8006126: 68f8 ldr r0, [r7, #12]
|
|
8006128: f000 fc36 bl 8006998 <UART_Start_Receive_DMA>
|
|
800612c: 4603 mov r3, r0
|
|
800612e: e000 b.n 8006132 <HAL_UART_Receive_DMA+0x42>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8006130: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8006132: 4618 mov r0, r3
|
|
8006134: 3710 adds r7, #16
|
|
8006136: 46bd mov sp, r7
|
|
8006138: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800613c <HAL_UART_IRQHandler>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|
{
|
|
800613c: b580 push {r7, lr}
|
|
800613e: b0ba sub sp, #232 @ 0xe8
|
|
8006140: af00 add r7, sp, #0
|
|
8006142: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(huart->Instance->SR);
|
|
8006144: 687b ldr r3, [r7, #4]
|
|
8006146: 681b ldr r3, [r3, #0]
|
|
8006148: 681b ldr r3, [r3, #0]
|
|
800614a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
800614e: 687b ldr r3, [r7, #4]
|
|
8006150: 681b ldr r3, [r3, #0]
|
|
8006152: 68db ldr r3, [r3, #12]
|
|
8006154: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
8006158: 687b ldr r3, [r7, #4]
|
|
800615a: 681b ldr r3, [r3, #0]
|
|
800615c: 695b ldr r3, [r3, #20]
|
|
800615e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
uint32_t errorflags = 0x00U;
|
|
8006162: 2300 movs r3, #0
|
|
8006164: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
uint32_t dmarequest = 0x00U;
|
|
8006168: 2300 movs r3, #0
|
|
800616a: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
|
|
/* If no error occurs */
|
|
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
|
|
800616e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006172: f003 030f and.w r3, r3, #15
|
|
8006176: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
if (errorflags == RESET)
|
|
800617a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
800617e: 2b00 cmp r3, #0
|
|
8006180: d10f bne.n 80061a2 <HAL_UART_IRQHandler+0x66>
|
|
{
|
|
/* UART in mode Receiver -------------------------------------------------*/
|
|
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
|
|
8006182: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006186: f003 0320 and.w r3, r3, #32
|
|
800618a: 2b00 cmp r3, #0
|
|
800618c: d009 beq.n 80061a2 <HAL_UART_IRQHandler+0x66>
|
|
800618e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006192: f003 0320 and.w r3, r3, #32
|
|
8006196: 2b00 cmp r3, #0
|
|
8006198: d003 beq.n 80061a2 <HAL_UART_IRQHandler+0x66>
|
|
{
|
|
UART_Receive_IT(huart);
|
|
800619a: 6878 ldr r0, [r7, #4]
|
|
800619c: f000 fda6 bl 8006cec <UART_Receive_IT>
|
|
return;
|
|
80061a0: e273 b.n 800668a <HAL_UART_IRQHandler+0x54e>
|
|
}
|
|
}
|
|
|
|
/* If some errors occur */
|
|
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET)
|
|
80061a2: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
80061a6: 2b00 cmp r3, #0
|
|
80061a8: f000 80de beq.w 8006368 <HAL_UART_IRQHandler+0x22c>
|
|
80061ac: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
80061b0: f003 0301 and.w r3, r3, #1
|
|
80061b4: 2b00 cmp r3, #0
|
|
80061b6: d106 bne.n 80061c6 <HAL_UART_IRQHandler+0x8a>
|
|
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
|
|
80061b8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80061bc: f403 7390 and.w r3, r3, #288 @ 0x120
|
|
80061c0: 2b00 cmp r3, #0
|
|
80061c2: f000 80d1 beq.w 8006368 <HAL_UART_IRQHandler+0x22c>
|
|
{
|
|
/* UART parity error interrupt occurred ----------------------------------*/
|
|
if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
|
|
80061c6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80061ca: f003 0301 and.w r3, r3, #1
|
|
80061ce: 2b00 cmp r3, #0
|
|
80061d0: d00b beq.n 80061ea <HAL_UART_IRQHandler+0xae>
|
|
80061d2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80061d6: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80061da: 2b00 cmp r3, #0
|
|
80061dc: d005 beq.n 80061ea <HAL_UART_IRQHandler+0xae>
|
|
{
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
80061de: 687b ldr r3, [r7, #4]
|
|
80061e0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80061e2: f043 0201 orr.w r2, r3, #1
|
|
80061e6: 687b ldr r3, [r7, #4]
|
|
80061e8: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* UART noise error interrupt occurred -----------------------------------*/
|
|
if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
|
|
80061ea: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80061ee: f003 0304 and.w r3, r3, #4
|
|
80061f2: 2b00 cmp r3, #0
|
|
80061f4: d00b beq.n 800620e <HAL_UART_IRQHandler+0xd2>
|
|
80061f6: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
80061fa: f003 0301 and.w r3, r3, #1
|
|
80061fe: 2b00 cmp r3, #0
|
|
8006200: d005 beq.n 800620e <HAL_UART_IRQHandler+0xd2>
|
|
{
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
8006202: 687b ldr r3, [r7, #4]
|
|
8006204: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8006206: f043 0202 orr.w r2, r3, #2
|
|
800620a: 687b ldr r3, [r7, #4]
|
|
800620c: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* UART frame error interrupt occurred -----------------------------------*/
|
|
if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
|
|
800620e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006212: f003 0302 and.w r3, r3, #2
|
|
8006216: 2b00 cmp r3, #0
|
|
8006218: d00b beq.n 8006232 <HAL_UART_IRQHandler+0xf6>
|
|
800621a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
800621e: f003 0301 and.w r3, r3, #1
|
|
8006222: 2b00 cmp r3, #0
|
|
8006224: d005 beq.n 8006232 <HAL_UART_IRQHandler+0xf6>
|
|
{
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
8006226: 687b ldr r3, [r7, #4]
|
|
8006228: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800622a: f043 0204 orr.w r2, r3, #4
|
|
800622e: 687b ldr r3, [r7, #4]
|
|
8006230: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* UART Over-Run interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET)
|
|
8006232: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006236: f003 0308 and.w r3, r3, #8
|
|
800623a: 2b00 cmp r3, #0
|
|
800623c: d011 beq.n 8006262 <HAL_UART_IRQHandler+0x126>
|
|
800623e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006242: f003 0320 and.w r3, r3, #32
|
|
8006246: 2b00 cmp r3, #0
|
|
8006248: d105 bne.n 8006256 <HAL_UART_IRQHandler+0x11a>
|
|
|| ((cr3its & USART_CR3_EIE) != RESET)))
|
|
800624a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
800624e: f003 0301 and.w r3, r3, #1
|
|
8006252: 2b00 cmp r3, #0
|
|
8006254: d005 beq.n 8006262 <HAL_UART_IRQHandler+0x126>
|
|
{
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
|
8006256: 687b ldr r3, [r7, #4]
|
|
8006258: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800625a: f043 0208 orr.w r2, r3, #8
|
|
800625e: 687b ldr r3, [r7, #4]
|
|
8006260: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be --------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
8006262: 687b ldr r3, [r7, #4]
|
|
8006264: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8006266: 2b00 cmp r3, #0
|
|
8006268: f000 820a beq.w 8006680 <HAL_UART_IRQHandler+0x544>
|
|
{
|
|
/* UART in mode Receiver -----------------------------------------------*/
|
|
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
|
|
800626c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006270: f003 0320 and.w r3, r3, #32
|
|
8006274: 2b00 cmp r3, #0
|
|
8006276: d008 beq.n 800628a <HAL_UART_IRQHandler+0x14e>
|
|
8006278: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
800627c: f003 0320 and.w r3, r3, #32
|
|
8006280: 2b00 cmp r3, #0
|
|
8006282: d002 beq.n 800628a <HAL_UART_IRQHandler+0x14e>
|
|
{
|
|
UART_Receive_IT(huart);
|
|
8006284: 6878 ldr r0, [r7, #4]
|
|
8006286: f000 fd31 bl 8006cec <UART_Receive_IT>
|
|
}
|
|
|
|
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
|
|
consider error as blocking */
|
|
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
|
|
800628a: 687b ldr r3, [r7, #4]
|
|
800628c: 681b ldr r3, [r3, #0]
|
|
800628e: 695b ldr r3, [r3, #20]
|
|
8006290: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006294: 2b40 cmp r3, #64 @ 0x40
|
|
8006296: bf0c ite eq
|
|
8006298: 2301 moveq r3, #1
|
|
800629a: 2300 movne r3, #0
|
|
800629c: b2db uxtb r3, r3
|
|
800629e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
|
|
80062a2: 687b ldr r3, [r7, #4]
|
|
80062a4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80062a6: f003 0308 and.w r3, r3, #8
|
|
80062aa: 2b00 cmp r3, #0
|
|
80062ac: d103 bne.n 80062b6 <HAL_UART_IRQHandler+0x17a>
|
|
80062ae: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
|
|
80062b2: 2b00 cmp r3, #0
|
|
80062b4: d04f beq.n 8006356 <HAL_UART_IRQHandler+0x21a>
|
|
{
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
80062b6: 6878 ldr r0, [r7, #4]
|
|
80062b8: f000 fc3c bl 8006b34 <UART_EndRxTransfer>
|
|
|
|
/* Disable the UART DMA Rx request if enabled */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80062bc: 687b ldr r3, [r7, #4]
|
|
80062be: 681b ldr r3, [r3, #0]
|
|
80062c0: 695b ldr r3, [r3, #20]
|
|
80062c2: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80062c6: 2b40 cmp r3, #64 @ 0x40
|
|
80062c8: d141 bne.n 800634e <HAL_UART_IRQHandler+0x212>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
80062ca: 687b ldr r3, [r7, #4]
|
|
80062cc: 681b ldr r3, [r3, #0]
|
|
80062ce: 3314 adds r3, #20
|
|
80062d0: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80062d4: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
80062d8: e853 3f00 ldrex r3, [r3]
|
|
80062dc: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
return(result);
|
|
80062e0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
80062e4: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80062e8: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
80062ec: 687b ldr r3, [r7, #4]
|
|
80062ee: 681b ldr r3, [r3, #0]
|
|
80062f0: 3314 adds r3, #20
|
|
80062f2: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
|
|
80062f6: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
|
|
80062fa: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80062fe: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
|
|
8006302: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
|
|
8006306: e841 2300 strex r3, r2, [r1]
|
|
800630a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
return(result);
|
|
800630e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8006312: 2b00 cmp r3, #0
|
|
8006314: d1d9 bne.n 80062ca <HAL_UART_IRQHandler+0x18e>
|
|
|
|
/* Abort the UART DMA Rx stream */
|
|
if (huart->hdmarx != NULL)
|
|
8006316: 687b ldr r3, [r7, #4]
|
|
8006318: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800631a: 2b00 cmp r3, #0
|
|
800631c: d013 beq.n 8006346 <HAL_UART_IRQHandler+0x20a>
|
|
{
|
|
/* Set the UART DMA Abort callback :
|
|
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
|
800631e: 687b ldr r3, [r7, #4]
|
|
8006320: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8006322: 4a8a ldr r2, [pc, #552] @ (800654c <HAL_UART_IRQHandler+0x410>)
|
|
8006324: 651a str r2, [r3, #80] @ 0x50
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
|
8006326: 687b ldr r3, [r7, #4]
|
|
8006328: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800632a: 4618 mov r0, r3
|
|
800632c: f7fc f80e bl 800234c <HAL_DMA_Abort_IT>
|
|
8006330: 4603 mov r3, r0
|
|
8006332: 2b00 cmp r3, #0
|
|
8006334: d016 beq.n 8006364 <HAL_UART_IRQHandler+0x228>
|
|
{
|
|
/* Call Directly XferAbortCallback function in case of error */
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
|
8006336: 687b ldr r3, [r7, #4]
|
|
8006338: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800633a: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
800633c: 687a ldr r2, [r7, #4]
|
|
800633e: 6bd2 ldr r2, [r2, #60] @ 0x3c
|
|
8006340: 4610 mov r0, r2
|
|
8006342: 4798 blx r3
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8006344: e00e b.n 8006364 <HAL_UART_IRQHandler+0x228>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8006346: 6878 ldr r0, [r7, #4]
|
|
8006348: f7fa fd28 bl 8000d9c <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
800634c: e00a b.n 8006364 <HAL_UART_IRQHandler+0x228>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
800634e: 6878 ldr r0, [r7, #4]
|
|
8006350: f7fa fd24 bl 8000d9c <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8006354: e006 b.n 8006364 <HAL_UART_IRQHandler+0x228>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8006356: 6878 ldr r0, [r7, #4]
|
|
8006358: f7fa fd20 bl 8000d9c <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800635c: 687b ldr r3, [r7, #4]
|
|
800635e: 2200 movs r2, #0
|
|
8006360: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
}
|
|
return;
|
|
8006362: e18d b.n 8006680 <HAL_UART_IRQHandler+0x544>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8006364: bf00 nop
|
|
return;
|
|
8006366: e18b b.n 8006680 <HAL_UART_IRQHandler+0x544>
|
|
} /* End if some error occurs */
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8006368: 687b ldr r3, [r7, #4]
|
|
800636a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800636c: 2b01 cmp r3, #1
|
|
800636e: f040 8167 bne.w 8006640 <HAL_UART_IRQHandler+0x504>
|
|
&& ((isrflags & USART_SR_IDLE) != 0U)
|
|
8006372: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006376: f003 0310 and.w r3, r3, #16
|
|
800637a: 2b00 cmp r3, #0
|
|
800637c: f000 8160 beq.w 8006640 <HAL_UART_IRQHandler+0x504>
|
|
&& ((cr1its & USART_CR1_IDLEIE) != 0U))
|
|
8006380: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006384: f003 0310 and.w r3, r3, #16
|
|
8006388: 2b00 cmp r3, #0
|
|
800638a: f000 8159 beq.w 8006640 <HAL_UART_IRQHandler+0x504>
|
|
{
|
|
__HAL_UART_CLEAR_IDLEFLAG(huart);
|
|
800638e: 2300 movs r3, #0
|
|
8006390: 60bb str r3, [r7, #8]
|
|
8006392: 687b ldr r3, [r7, #4]
|
|
8006394: 681b ldr r3, [r3, #0]
|
|
8006396: 681b ldr r3, [r3, #0]
|
|
8006398: 60bb str r3, [r7, #8]
|
|
800639a: 687b ldr r3, [r7, #4]
|
|
800639c: 681b ldr r3, [r3, #0]
|
|
800639e: 685b ldr r3, [r3, #4]
|
|
80063a0: 60bb str r3, [r7, #8]
|
|
80063a2: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Check if DMA mode is enabled in UART */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80063a4: 687b ldr r3, [r7, #4]
|
|
80063a6: 681b ldr r3, [r3, #0]
|
|
80063a8: 695b ldr r3, [r3, #20]
|
|
80063aa: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80063ae: 2b40 cmp r3, #64 @ 0x40
|
|
80063b0: f040 80ce bne.w 8006550 <HAL_UART_IRQHandler+0x414>
|
|
{
|
|
/* DMA mode enabled */
|
|
/* Check received length : If all expected data are received, do nothing,
|
|
(DMA cplt callback will be called).
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
|
80063b4: 687b ldr r3, [r7, #4]
|
|
80063b6: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80063b8: 681b ldr r3, [r3, #0]
|
|
80063ba: 685b ldr r3, [r3, #4]
|
|
80063bc: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
|
|
if ((nb_remaining_rx_data > 0U)
|
|
80063c0: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
|
|
80063c4: 2b00 cmp r3, #0
|
|
80063c6: f000 80a9 beq.w 800651c <HAL_UART_IRQHandler+0x3e0>
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
80063ca: 687b ldr r3, [r7, #4]
|
|
80063cc: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
80063ce: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
80063d2: 429a cmp r2, r3
|
|
80063d4: f080 80a2 bcs.w 800651c <HAL_UART_IRQHandler+0x3e0>
|
|
{
|
|
/* Reception is not complete */
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
80063d8: 687b ldr r3, [r7, #4]
|
|
80063da: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
80063de: 85da strh r2, [r3, #46] @ 0x2e
|
|
|
|
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
|
|
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
|
|
80063e0: 687b ldr r3, [r7, #4]
|
|
80063e2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80063e4: 69db ldr r3, [r3, #28]
|
|
80063e6: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80063ea: f000 8088 beq.w 80064fe <HAL_UART_IRQHandler+0x3c2>
|
|
{
|
|
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
80063ee: 687b ldr r3, [r7, #4]
|
|
80063f0: 681b ldr r3, [r3, #0]
|
|
80063f2: 330c adds r3, #12
|
|
80063f4: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80063f8: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
80063fc: e853 3f00 ldrex r3, [r3]
|
|
8006400: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
return(result);
|
|
8006404: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
8006408: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
800640c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
8006410: 687b ldr r3, [r7, #4]
|
|
8006412: 681b ldr r3, [r3, #0]
|
|
8006414: 330c adds r3, #12
|
|
8006416: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8
|
|
800641a: f8c7 2094 str.w r2, [r7, #148] @ 0x94
|
|
800641e: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006422: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
|
|
8006426: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
|
|
800642a: e841 2300 strex r3, r2, [r1]
|
|
800642e: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
return(result);
|
|
8006432: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8006436: 2b00 cmp r3, #0
|
|
8006438: d1d9 bne.n 80063ee <HAL_UART_IRQHandler+0x2b2>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800643a: 687b ldr r3, [r7, #4]
|
|
800643c: 681b ldr r3, [r3, #0]
|
|
800643e: 3314 adds r3, #20
|
|
8006440: 677b str r3, [r7, #116] @ 0x74
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006442: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8006444: e853 3f00 ldrex r3, [r3]
|
|
8006448: 673b str r3, [r7, #112] @ 0x70
|
|
return(result);
|
|
800644a: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
800644c: f023 0301 bic.w r3, r3, #1
|
|
8006450: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8006454: 687b ldr r3, [r7, #4]
|
|
8006456: 681b ldr r3, [r3, #0]
|
|
8006458: 3314 adds r3, #20
|
|
800645a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
800645e: f8c7 2080 str.w r2, [r7, #128] @ 0x80
|
|
8006462: 67fb str r3, [r7, #124] @ 0x7c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006464: 6ff9 ldr r1, [r7, #124] @ 0x7c
|
|
8006466: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
|
|
800646a: e841 2300 strex r3, r2, [r1]
|
|
800646e: 67bb str r3, [r7, #120] @ 0x78
|
|
return(result);
|
|
8006470: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8006472: 2b00 cmp r3, #0
|
|
8006474: d1e1 bne.n 800643a <HAL_UART_IRQHandler+0x2fe>
|
|
|
|
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8006476: 687b ldr r3, [r7, #4]
|
|
8006478: 681b ldr r3, [r3, #0]
|
|
800647a: 3314 adds r3, #20
|
|
800647c: 663b str r3, [r7, #96] @ 0x60
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800647e: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8006480: e853 3f00 ldrex r3, [r3]
|
|
8006484: 65fb str r3, [r7, #92] @ 0x5c
|
|
return(result);
|
|
8006486: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8006488: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800648c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
8006490: 687b ldr r3, [r7, #4]
|
|
8006492: 681b ldr r3, [r3, #0]
|
|
8006494: 3314 adds r3, #20
|
|
8006496: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
|
|
800649a: 66fa str r2, [r7, #108] @ 0x6c
|
|
800649c: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800649e: 6eb9 ldr r1, [r7, #104] @ 0x68
|
|
80064a0: 6efa ldr r2, [r7, #108] @ 0x6c
|
|
80064a2: e841 2300 strex r3, r2, [r1]
|
|
80064a6: 667b str r3, [r7, #100] @ 0x64
|
|
return(result);
|
|
80064a8: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
80064aa: 2b00 cmp r3, #0
|
|
80064ac: d1e3 bne.n 8006476 <HAL_UART_IRQHandler+0x33a>
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80064ae: 687b ldr r3, [r7, #4]
|
|
80064b0: 2220 movs r2, #32
|
|
80064b2: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80064b6: 687b ldr r3, [r7, #4]
|
|
80064b8: 2200 movs r2, #0
|
|
80064ba: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80064bc: 687b ldr r3, [r7, #4]
|
|
80064be: 681b ldr r3, [r3, #0]
|
|
80064c0: 330c adds r3, #12
|
|
80064c2: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80064c4: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80064c6: e853 3f00 ldrex r3, [r3]
|
|
80064ca: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
80064cc: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80064ce: f023 0310 bic.w r3, r3, #16
|
|
80064d2: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
80064d6: 687b ldr r3, [r7, #4]
|
|
80064d8: 681b ldr r3, [r3, #0]
|
|
80064da: 330c adds r3, #12
|
|
80064dc: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac
|
|
80064e0: 65ba str r2, [r7, #88] @ 0x58
|
|
80064e2: 657b str r3, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80064e4: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
80064e6: 6dba ldr r2, [r7, #88] @ 0x58
|
|
80064e8: e841 2300 strex r3, r2, [r1]
|
|
80064ec: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
80064ee: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80064f0: 2b00 cmp r3, #0
|
|
80064f2: d1e3 bne.n 80064bc <HAL_UART_IRQHandler+0x380>
|
|
|
|
/* Last bytes received, so no need as the abort is immediate */
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
|
80064f4: 687b ldr r3, [r7, #4]
|
|
80064f6: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80064f8: 4618 mov r0, r3
|
|
80064fa: f7fb feb7 bl 800226c <HAL_DMA_Abort>
|
|
}
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
80064fe: 687b ldr r3, [r7, #4]
|
|
8006500: 2202 movs r2, #2
|
|
8006502: 635a str r2, [r3, #52] @ 0x34
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
8006504: 687b ldr r3, [r7, #4]
|
|
8006506: 8d9a ldrh r2, [r3, #44] @ 0x2c
|
|
8006508: 687b ldr r3, [r7, #4]
|
|
800650a: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
800650c: b29b uxth r3, r3
|
|
800650e: 1ad3 subs r3, r2, r3
|
|
8006510: b29b uxth r3, r3
|
|
8006512: 4619 mov r1, r3
|
|
8006514: 6878 ldr r0, [r7, #4]
|
|
8006516: f000 f8d9 bl 80066cc <HAL_UARTEx_RxEventCallback>
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
800651a: e0b3 b.n 8006684 <HAL_UART_IRQHandler+0x548>
|
|
if (nb_remaining_rx_data == huart->RxXferSize)
|
|
800651c: 687b ldr r3, [r7, #4]
|
|
800651e: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8006520: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8006524: 429a cmp r2, r3
|
|
8006526: f040 80ad bne.w 8006684 <HAL_UART_IRQHandler+0x548>
|
|
if (huart->hdmarx->Init.Mode == DMA_CIRCULAR)
|
|
800652a: 687b ldr r3, [r7, #4]
|
|
800652c: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800652e: 69db ldr r3, [r3, #28]
|
|
8006530: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8006534: f040 80a6 bne.w 8006684 <HAL_UART_IRQHandler+0x548>
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
8006538: 687b ldr r3, [r7, #4]
|
|
800653a: 2202 movs r2, #2
|
|
800653c: 635a str r2, [r3, #52] @ 0x34
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
800653e: 687b ldr r3, [r7, #4]
|
|
8006540: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8006542: 4619 mov r1, r3
|
|
8006544: 6878 ldr r0, [r7, #4]
|
|
8006546: f000 f8c1 bl 80066cc <HAL_UARTEx_RxEventCallback>
|
|
return;
|
|
800654a: e09b b.n 8006684 <HAL_UART_IRQHandler+0x548>
|
|
800654c: 08006bfb .word 0x08006bfb
|
|
else
|
|
{
|
|
/* DMA mode not enabled */
|
|
/* Check received length : If all expected data are received, do nothing.
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
8006550: 687b ldr r3, [r7, #4]
|
|
8006552: 8d9a ldrh r2, [r3, #44] @ 0x2c
|
|
8006554: 687b ldr r3, [r7, #4]
|
|
8006556: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
8006558: b29b uxth r3, r3
|
|
800655a: 1ad3 subs r3, r2, r3
|
|
800655c: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
|
|
if ((huart->RxXferCount > 0U)
|
|
8006560: 687b ldr r3, [r7, #4]
|
|
8006562: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
8006564: b29b uxth r3, r3
|
|
8006566: 2b00 cmp r3, #0
|
|
8006568: f000 808e beq.w 8006688 <HAL_UART_IRQHandler+0x54c>
|
|
&& (nb_rx_data > 0U))
|
|
800656c: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
8006570: 2b00 cmp r3, #0
|
|
8006572: f000 8089 beq.w 8006688 <HAL_UART_IRQHandler+0x54c>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
8006576: 687b ldr r3, [r7, #4]
|
|
8006578: 681b ldr r3, [r3, #0]
|
|
800657a: 330c adds r3, #12
|
|
800657c: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800657e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006580: e853 3f00 ldrex r3, [r3]
|
|
8006584: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8006586: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006588: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
800658c: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
8006590: 687b ldr r3, [r7, #4]
|
|
8006592: 681b ldr r3, [r3, #0]
|
|
8006594: 330c adds r3, #12
|
|
8006596: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8
|
|
800659a: 647a str r2, [r7, #68] @ 0x44
|
|
800659c: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800659e: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
80065a0: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
80065a2: e841 2300 strex r3, r2, [r1]
|
|
80065a6: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
80065a8: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80065aa: 2b00 cmp r3, #0
|
|
80065ac: d1e3 bne.n 8006576 <HAL_UART_IRQHandler+0x43a>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
80065ae: 687b ldr r3, [r7, #4]
|
|
80065b0: 681b ldr r3, [r3, #0]
|
|
80065b2: 3314 adds r3, #20
|
|
80065b4: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80065b6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80065b8: e853 3f00 ldrex r3, [r3]
|
|
80065bc: 623b str r3, [r7, #32]
|
|
return(result);
|
|
80065be: 6a3b ldr r3, [r7, #32]
|
|
80065c0: f023 0301 bic.w r3, r3, #1
|
|
80065c4: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
|
|
80065c8: 687b ldr r3, [r7, #4]
|
|
80065ca: 681b ldr r3, [r3, #0]
|
|
80065cc: 3314 adds r3, #20
|
|
80065ce: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
|
|
80065d2: 633a str r2, [r7, #48] @ 0x30
|
|
80065d4: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80065d6: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80065d8: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80065da: e841 2300 strex r3, r2, [r1]
|
|
80065de: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
80065e0: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80065e2: 2b00 cmp r3, #0
|
|
80065e4: d1e3 bne.n 80065ae <HAL_UART_IRQHandler+0x472>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80065e6: 687b ldr r3, [r7, #4]
|
|
80065e8: 2220 movs r2, #32
|
|
80065ea: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80065ee: 687b ldr r3, [r7, #4]
|
|
80065f0: 2200 movs r2, #0
|
|
80065f2: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80065f4: 687b ldr r3, [r7, #4]
|
|
80065f6: 681b ldr r3, [r3, #0]
|
|
80065f8: 330c adds r3, #12
|
|
80065fa: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80065fc: 693b ldr r3, [r7, #16]
|
|
80065fe: e853 3f00 ldrex r3, [r3]
|
|
8006602: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8006604: 68fb ldr r3, [r7, #12]
|
|
8006606: f023 0310 bic.w r3, r3, #16
|
|
800660a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
800660e: 687b ldr r3, [r7, #4]
|
|
8006610: 681b ldr r3, [r3, #0]
|
|
8006612: 330c adds r3, #12
|
|
8006614: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0
|
|
8006618: 61fa str r2, [r7, #28]
|
|
800661a: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800661c: 69b9 ldr r1, [r7, #24]
|
|
800661e: 69fa ldr r2, [r7, #28]
|
|
8006620: e841 2300 strex r3, r2, [r1]
|
|
8006624: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8006626: 697b ldr r3, [r7, #20]
|
|
8006628: 2b00 cmp r3, #0
|
|
800662a: d1e3 bne.n 80065f4 <HAL_UART_IRQHandler+0x4b8>
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
800662c: 687b ldr r3, [r7, #4]
|
|
800662e: 2202 movs r2, #2
|
|
8006630: 635a str r2, [r3, #52] @ 0x34
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx complete callback*/
|
|
huart->RxEventCallback(huart, nb_rx_data);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
|
8006632: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
8006636: 4619 mov r1, r3
|
|
8006638: 6878 ldr r0, [r7, #4]
|
|
800663a: f000 f847 bl 80066cc <HAL_UARTEx_RxEventCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
return;
|
|
800663e: e023 b.n 8006688 <HAL_UART_IRQHandler+0x54c>
|
|
}
|
|
}
|
|
|
|
/* UART in mode Transmitter ------------------------------------------------*/
|
|
if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
|
|
8006640: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006644: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006648: 2b00 cmp r3, #0
|
|
800664a: d009 beq.n 8006660 <HAL_UART_IRQHandler+0x524>
|
|
800664c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006650: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006654: 2b00 cmp r3, #0
|
|
8006656: d003 beq.n 8006660 <HAL_UART_IRQHandler+0x524>
|
|
{
|
|
UART_Transmit_IT(huart);
|
|
8006658: 6878 ldr r0, [r7, #4]
|
|
800665a: f000 fadf bl 8006c1c <UART_Transmit_IT>
|
|
return;
|
|
800665e: e014 b.n 800668a <HAL_UART_IRQHandler+0x54e>
|
|
}
|
|
|
|
/* UART in mode Transmitter end --------------------------------------------*/
|
|
if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
|
|
8006660: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006664: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006668: 2b00 cmp r3, #0
|
|
800666a: d00e beq.n 800668a <HAL_UART_IRQHandler+0x54e>
|
|
800666c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006670: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006674: 2b00 cmp r3, #0
|
|
8006676: d008 beq.n 800668a <HAL_UART_IRQHandler+0x54e>
|
|
{
|
|
UART_EndTransmit_IT(huart);
|
|
8006678: 6878 ldr r0, [r7, #4]
|
|
800667a: f000 fb1f bl 8006cbc <UART_EndTransmit_IT>
|
|
return;
|
|
800667e: e004 b.n 800668a <HAL_UART_IRQHandler+0x54e>
|
|
return;
|
|
8006680: bf00 nop
|
|
8006682: e002 b.n 800668a <HAL_UART_IRQHandler+0x54e>
|
|
return;
|
|
8006684: bf00 nop
|
|
8006686: e000 b.n 800668a <HAL_UART_IRQHandler+0x54e>
|
|
return;
|
|
8006688: bf00 nop
|
|
}
|
|
}
|
|
800668a: 37e8 adds r7, #232 @ 0xe8
|
|
800668c: 46bd mov sp, r7
|
|
800668e: bd80 pop {r7, pc}
|
|
|
|
08006690 <HAL_UART_TxCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8006690: b480 push {r7}
|
|
8006692: b083 sub sp, #12
|
|
8006694: af00 add r7, sp, #0
|
|
8006696: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8006698: bf00 nop
|
|
800669a: 370c adds r7, #12
|
|
800669c: 46bd mov sp, r7
|
|
800669e: f85d 7b04 ldr.w r7, [sp], #4
|
|
80066a2: 4770 bx lr
|
|
|
|
080066a4 <HAL_UART_TxHalfCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
80066a4: b480 push {r7}
|
|
80066a6: b083 sub sp, #12
|
|
80066a8: af00 add r7, sp, #0
|
|
80066aa: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxHalfCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80066ac: bf00 nop
|
|
80066ae: 370c adds r7, #12
|
|
80066b0: 46bd mov sp, r7
|
|
80066b2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80066b6: 4770 bx lr
|
|
|
|
080066b8 <HAL_UART_RxHalfCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
80066b8: b480 push {r7}
|
|
80066ba: b083 sub sp, #12
|
|
80066bc: af00 add r7, sp, #0
|
|
80066be: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_RxHalfCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80066c0: bf00 nop
|
|
80066c2: 370c adds r7, #12
|
|
80066c4: 46bd mov sp, r7
|
|
80066c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80066ca: 4770 bx lr
|
|
|
|
080066cc <HAL_UARTEx_RxEventCallback>:
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
|
* reception buffer until which, data are available)
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|
{
|
|
80066cc: b480 push {r7}
|
|
80066ce: b083 sub sp, #12
|
|
80066d0: af00 add r7, sp, #0
|
|
80066d2: 6078 str r0, [r7, #4]
|
|
80066d4: 460b mov r3, r1
|
|
80066d6: 807b strh r3, [r7, #2]
|
|
UNUSED(Size);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
80066d8: bf00 nop
|
|
80066da: 370c adds r7, #12
|
|
80066dc: 46bd mov sp, r7
|
|
80066de: f85d 7b04 ldr.w r7, [sp], #4
|
|
80066e2: 4770 bx lr
|
|
|
|
080066e4 <UART_DMATransmitCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80066e4: b580 push {r7, lr}
|
|
80066e6: b090 sub sp, #64 @ 0x40
|
|
80066e8: af00 add r7, sp, #0
|
|
80066ea: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
80066ec: 687b ldr r3, [r7, #4]
|
|
80066ee: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80066f0: 63fb str r3, [r7, #60] @ 0x3c
|
|
/* DMA Normal mode*/
|
|
if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
|
|
80066f2: 687b ldr r3, [r7, #4]
|
|
80066f4: 681b ldr r3, [r3, #0]
|
|
80066f6: 681b ldr r3, [r3, #0]
|
|
80066f8: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80066fc: 2b00 cmp r3, #0
|
|
80066fe: d137 bne.n 8006770 <UART_DMATransmitCplt+0x8c>
|
|
{
|
|
huart->TxXferCount = 0x00U;
|
|
8006700: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006702: 2200 movs r2, #0
|
|
8006704: 84da strh r2, [r3, #38] @ 0x26
|
|
|
|
/* Disable the DMA transfer for transmit request by setting the DMAT bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
|
8006706: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006708: 681b ldr r3, [r3, #0]
|
|
800670a: 3314 adds r3, #20
|
|
800670c: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800670e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006710: e853 3f00 ldrex r3, [r3]
|
|
8006714: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8006716: 6a3b ldr r3, [r7, #32]
|
|
8006718: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
800671c: 63bb str r3, [r7, #56] @ 0x38
|
|
800671e: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006720: 681b ldr r3, [r3, #0]
|
|
8006722: 3314 adds r3, #20
|
|
8006724: 6bba ldr r2, [r7, #56] @ 0x38
|
|
8006726: 633a str r2, [r7, #48] @ 0x30
|
|
8006728: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800672a: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
800672c: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800672e: e841 2300 strex r3, r2, [r1]
|
|
8006732: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8006734: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006736: 2b00 cmp r3, #0
|
|
8006738: d1e5 bne.n 8006706 <UART_DMATransmitCplt+0x22>
|
|
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
800673a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800673c: 681b ldr r3, [r3, #0]
|
|
800673e: 330c adds r3, #12
|
|
8006740: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006742: 693b ldr r3, [r7, #16]
|
|
8006744: e853 3f00 ldrex r3, [r3]
|
|
8006748: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800674a: 68fb ldr r3, [r7, #12]
|
|
800674c: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8006750: 637b str r3, [r7, #52] @ 0x34
|
|
8006752: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006754: 681b ldr r3, [r3, #0]
|
|
8006756: 330c adds r3, #12
|
|
8006758: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
800675a: 61fa str r2, [r7, #28]
|
|
800675c: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800675e: 69b9 ldr r1, [r7, #24]
|
|
8006760: 69fa ldr r2, [r7, #28]
|
|
8006762: e841 2300 strex r3, r2, [r1]
|
|
8006766: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8006768: 697b ldr r3, [r7, #20]
|
|
800676a: 2b00 cmp r3, #0
|
|
800676c: d1e5 bne.n 800673a <UART_DMATransmitCplt+0x56>
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
800676e: e002 b.n 8006776 <UART_DMATransmitCplt+0x92>
|
|
HAL_UART_TxCpltCallback(huart);
|
|
8006770: 6bf8 ldr r0, [r7, #60] @ 0x3c
|
|
8006772: f7ff ff8d bl 8006690 <HAL_UART_TxCpltCallback>
|
|
}
|
|
8006776: bf00 nop
|
|
8006778: 3740 adds r7, #64 @ 0x40
|
|
800677a: 46bd mov sp, r7
|
|
800677c: bd80 pop {r7, pc}
|
|
|
|
0800677e <UART_DMATxHalfCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800677e: b580 push {r7, lr}
|
|
8006780: b084 sub sp, #16
|
|
8006782: af00 add r7, sp, #0
|
|
8006784: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
8006786: 687b ldr r3, [r7, #4]
|
|
8006788: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800678a: 60fb str r3, [r7, #12]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxHalfCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxHalfCpltCallback(huart);
|
|
800678c: 68f8 ldr r0, [r7, #12]
|
|
800678e: f7ff ff89 bl 80066a4 <HAL_UART_TxHalfCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
8006792: bf00 nop
|
|
8006794: 3710 adds r7, #16
|
|
8006796: 46bd mov sp, r7
|
|
8006798: bd80 pop {r7, pc}
|
|
|
|
0800679a <UART_DMAReceiveCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800679a: b580 push {r7, lr}
|
|
800679c: b09c sub sp, #112 @ 0x70
|
|
800679e: af00 add r7, sp, #0
|
|
80067a0: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
80067a2: 687b ldr r3, [r7, #4]
|
|
80067a4: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80067a6: 66fb str r3, [r7, #108] @ 0x6c
|
|
|
|
/* DMA Normal mode*/
|
|
if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
|
|
80067a8: 687b ldr r3, [r7, #4]
|
|
80067aa: 681b ldr r3, [r3, #0]
|
|
80067ac: 681b ldr r3, [r3, #0]
|
|
80067ae: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80067b2: 2b00 cmp r3, #0
|
|
80067b4: d172 bne.n 800689c <UART_DMAReceiveCplt+0x102>
|
|
{
|
|
huart->RxXferCount = 0U;
|
|
80067b6: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80067b8: 2200 movs r2, #0
|
|
80067ba: 85da strh r2, [r3, #46] @ 0x2e
|
|
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
80067bc: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80067be: 681b ldr r3, [r3, #0]
|
|
80067c0: 330c adds r3, #12
|
|
80067c2: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80067c4: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80067c6: e853 3f00 ldrex r3, [r3]
|
|
80067ca: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
80067cc: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80067ce: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
80067d2: 66bb str r3, [r7, #104] @ 0x68
|
|
80067d4: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80067d6: 681b ldr r3, [r3, #0]
|
|
80067d8: 330c adds r3, #12
|
|
80067da: 6eba ldr r2, [r7, #104] @ 0x68
|
|
80067dc: 65ba str r2, [r7, #88] @ 0x58
|
|
80067de: 657b str r3, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80067e0: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
80067e2: 6dba ldr r2, [r7, #88] @ 0x58
|
|
80067e4: e841 2300 strex r3, r2, [r1]
|
|
80067e8: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
80067ea: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80067ec: 2b00 cmp r3, #0
|
|
80067ee: d1e5 bne.n 80067bc <UART_DMAReceiveCplt+0x22>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
80067f0: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80067f2: 681b ldr r3, [r3, #0]
|
|
80067f4: 3314 adds r3, #20
|
|
80067f6: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80067f8: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80067fa: e853 3f00 ldrex r3, [r3]
|
|
80067fe: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8006800: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006802: f023 0301 bic.w r3, r3, #1
|
|
8006806: 667b str r3, [r7, #100] @ 0x64
|
|
8006808: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800680a: 681b ldr r3, [r3, #0]
|
|
800680c: 3314 adds r3, #20
|
|
800680e: 6e7a ldr r2, [r7, #100] @ 0x64
|
|
8006810: 647a str r2, [r7, #68] @ 0x44
|
|
8006812: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006814: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8006816: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8006818: e841 2300 strex r3, r2, [r1]
|
|
800681c: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
800681e: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006820: 2b00 cmp r3, #0
|
|
8006822: d1e5 bne.n 80067f0 <UART_DMAReceiveCplt+0x56>
|
|
|
|
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8006824: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8006826: 681b ldr r3, [r3, #0]
|
|
8006828: 3314 adds r3, #20
|
|
800682a: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800682c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800682e: e853 3f00 ldrex r3, [r3]
|
|
8006832: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8006834: 6a3b ldr r3, [r7, #32]
|
|
8006836: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800683a: 663b str r3, [r7, #96] @ 0x60
|
|
800683c: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800683e: 681b ldr r3, [r3, #0]
|
|
8006840: 3314 adds r3, #20
|
|
8006842: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
8006844: 633a str r2, [r7, #48] @ 0x30
|
|
8006846: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006848: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
800684a: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800684c: e841 2300 strex r3, r2, [r1]
|
|
8006850: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8006852: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006854: 2b00 cmp r3, #0
|
|
8006856: d1e5 bne.n 8006824 <UART_DMAReceiveCplt+0x8a>
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006858: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800685a: 2220 movs r2, #32
|
|
800685c: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8006860: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8006862: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006864: 2b01 cmp r3, #1
|
|
8006866: d119 bne.n 800689c <UART_DMAReceiveCplt+0x102>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8006868: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800686a: 681b ldr r3, [r3, #0]
|
|
800686c: 330c adds r3, #12
|
|
800686e: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006870: 693b ldr r3, [r7, #16]
|
|
8006872: e853 3f00 ldrex r3, [r3]
|
|
8006876: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8006878: 68fb ldr r3, [r7, #12]
|
|
800687a: f023 0310 bic.w r3, r3, #16
|
|
800687e: 65fb str r3, [r7, #92] @ 0x5c
|
|
8006880: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8006882: 681b ldr r3, [r3, #0]
|
|
8006884: 330c adds r3, #12
|
|
8006886: 6dfa ldr r2, [r7, #92] @ 0x5c
|
|
8006888: 61fa str r2, [r7, #28]
|
|
800688a: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800688c: 69b9 ldr r1, [r7, #24]
|
|
800688e: 69fa ldr r2, [r7, #28]
|
|
8006890: e841 2300 strex r3, r2, [r1]
|
|
8006894: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8006896: 697b ldr r3, [r7, #20]
|
|
8006898: 2b00 cmp r3, #0
|
|
800689a: d1e5 bne.n 8006868 <UART_DMAReceiveCplt+0xce>
|
|
}
|
|
}
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
800689c: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800689e: 2200 movs r2, #0
|
|
80068a0: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : use Rx Event callback */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80068a2: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80068a4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80068a6: 2b01 cmp r3, #1
|
|
80068a8: d106 bne.n 80068b8 <UART_DMAReceiveCplt+0x11e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
80068aa: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80068ac: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
80068ae: 4619 mov r1, r3
|
|
80068b0: 6ef8 ldr r0, [r7, #108] @ 0x6c
|
|
80068b2: f7ff ff0b bl 80066cc <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
80068b6: e002 b.n 80068be <UART_DMAReceiveCplt+0x124>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
80068b8: 6ef8 ldr r0, [r7, #108] @ 0x6c
|
|
80068ba: f7fa fa13 bl 8000ce4 <HAL_UART_RxCpltCallback>
|
|
}
|
|
80068be: bf00 nop
|
|
80068c0: 3770 adds r7, #112 @ 0x70
|
|
80068c2: 46bd mov sp, r7
|
|
80068c4: bd80 pop {r7, pc}
|
|
|
|
080068c6 <UART_DMARxHalfCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80068c6: b580 push {r7, lr}
|
|
80068c8: b084 sub sp, #16
|
|
80068ca: af00 add r7, sp, #0
|
|
80068cc: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
80068ce: 687b ldr r3, [r7, #4]
|
|
80068d0: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80068d2: 60fb str r3, [r7, #12]
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Half Transfer */
|
|
huart->RxEventType = HAL_UART_RXEVENT_HT;
|
|
80068d4: 68fb ldr r3, [r7, #12]
|
|
80068d6: 2201 movs r2, #1
|
|
80068d8: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : use Rx Event callback */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80068da: 68fb ldr r3, [r7, #12]
|
|
80068dc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80068de: 2b01 cmp r3, #1
|
|
80068e0: d108 bne.n 80068f4 <UART_DMARxHalfCplt+0x2e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize / 2U);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
|
|
80068e2: 68fb ldr r3, [r7, #12]
|
|
80068e4: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
80068e6: 085b lsrs r3, r3, #1
|
|
80068e8: b29b uxth r3, r3
|
|
80068ea: 4619 mov r1, r3
|
|
80068ec: 68f8 ldr r0, [r7, #12]
|
|
80068ee: f7ff feed bl 80066cc <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx Half complete callback*/
|
|
HAL_UART_RxHalfCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
80068f2: e002 b.n 80068fa <UART_DMARxHalfCplt+0x34>
|
|
HAL_UART_RxHalfCpltCallback(huart);
|
|
80068f4: 68f8 ldr r0, [r7, #12]
|
|
80068f6: f7ff fedf bl 80066b8 <HAL_UART_RxHalfCpltCallback>
|
|
}
|
|
80068fa: bf00 nop
|
|
80068fc: 3710 adds r7, #16
|
|
80068fe: 46bd mov sp, r7
|
|
8006900: bd80 pop {r7, pc}
|
|
|
|
08006902 <UART_DMAError>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8006902: b580 push {r7, lr}
|
|
8006904: b084 sub sp, #16
|
|
8006906: af00 add r7, sp, #0
|
|
8006908: 6078 str r0, [r7, #4]
|
|
uint32_t dmarequest = 0x00U;
|
|
800690a: 2300 movs r3, #0
|
|
800690c: 60fb str r3, [r7, #12]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
800690e: 687b ldr r3, [r7, #4]
|
|
8006910: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006912: 60bb str r3, [r7, #8]
|
|
|
|
/* Stop UART DMA Tx request if ongoing */
|
|
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
|
|
8006914: 68bb ldr r3, [r7, #8]
|
|
8006916: 681b ldr r3, [r3, #0]
|
|
8006918: 695b ldr r3, [r3, #20]
|
|
800691a: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800691e: 2b80 cmp r3, #128 @ 0x80
|
|
8006920: bf0c ite eq
|
|
8006922: 2301 moveq r3, #1
|
|
8006924: 2300 movne r3, #0
|
|
8006926: b2db uxtb r3, r3
|
|
8006928: 60fb str r3, [r7, #12]
|
|
if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
|
|
800692a: 68bb ldr r3, [r7, #8]
|
|
800692c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8006930: b2db uxtb r3, r3
|
|
8006932: 2b21 cmp r3, #33 @ 0x21
|
|
8006934: d108 bne.n 8006948 <UART_DMAError+0x46>
|
|
8006936: 68fb ldr r3, [r7, #12]
|
|
8006938: 2b00 cmp r3, #0
|
|
800693a: d005 beq.n 8006948 <UART_DMAError+0x46>
|
|
{
|
|
huart->TxXferCount = 0x00U;
|
|
800693c: 68bb ldr r3, [r7, #8]
|
|
800693e: 2200 movs r2, #0
|
|
8006940: 84da strh r2, [r3, #38] @ 0x26
|
|
UART_EndTxTransfer(huart);
|
|
8006942: 68b8 ldr r0, [r7, #8]
|
|
8006944: f000 f8ce bl 8006ae4 <UART_EndTxTransfer>
|
|
}
|
|
|
|
/* Stop UART DMA Rx request if ongoing */
|
|
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8006948: 68bb ldr r3, [r7, #8]
|
|
800694a: 681b ldr r3, [r3, #0]
|
|
800694c: 695b ldr r3, [r3, #20]
|
|
800694e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006952: 2b40 cmp r3, #64 @ 0x40
|
|
8006954: bf0c ite eq
|
|
8006956: 2301 moveq r3, #1
|
|
8006958: 2300 movne r3, #0
|
|
800695a: b2db uxtb r3, r3
|
|
800695c: 60fb str r3, [r7, #12]
|
|
if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
|
|
800695e: 68bb ldr r3, [r7, #8]
|
|
8006960: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
8006964: b2db uxtb r3, r3
|
|
8006966: 2b22 cmp r3, #34 @ 0x22
|
|
8006968: d108 bne.n 800697c <UART_DMAError+0x7a>
|
|
800696a: 68fb ldr r3, [r7, #12]
|
|
800696c: 2b00 cmp r3, #0
|
|
800696e: d005 beq.n 800697c <UART_DMAError+0x7a>
|
|
{
|
|
huart->RxXferCount = 0x00U;
|
|
8006970: 68bb ldr r3, [r7, #8]
|
|
8006972: 2200 movs r2, #0
|
|
8006974: 85da strh r2, [r3, #46] @ 0x2e
|
|
UART_EndRxTransfer(huart);
|
|
8006976: 68b8 ldr r0, [r7, #8]
|
|
8006978: f000 f8dc bl 8006b34 <UART_EndRxTransfer>
|
|
}
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_DMA;
|
|
800697c: 68bb ldr r3, [r7, #8]
|
|
800697e: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8006980: f043 0210 orr.w r2, r3, #16
|
|
8006984: 68bb ldr r3, [r7, #8]
|
|
8006986: 645a str r2, [r3, #68] @ 0x44
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8006988: 68b8 ldr r0, [r7, #8]
|
|
800698a: f7fa fa07 bl 8000d9c <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
800698e: bf00 nop
|
|
8006990: 3710 adds r7, #16
|
|
8006992: 46bd mov sp, r7
|
|
8006994: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08006998 <UART_Start_Receive_DMA>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
8006998: b580 push {r7, lr}
|
|
800699a: b098 sub sp, #96 @ 0x60
|
|
800699c: af00 add r7, sp, #0
|
|
800699e: 60f8 str r0, [r7, #12]
|
|
80069a0: 60b9 str r1, [r7, #8]
|
|
80069a2: 4613 mov r3, r2
|
|
80069a4: 80fb strh r3, [r7, #6]
|
|
uint32_t *tmp;
|
|
|
|
huart->pRxBuffPtr = pData;
|
|
80069a6: 68ba ldr r2, [r7, #8]
|
|
80069a8: 68fb ldr r3, [r7, #12]
|
|
80069aa: 629a str r2, [r3, #40] @ 0x28
|
|
huart->RxXferSize = Size;
|
|
80069ac: 68fb ldr r3, [r7, #12]
|
|
80069ae: 88fa ldrh r2, [r7, #6]
|
|
80069b0: 859a strh r2, [r3, #44] @ 0x2c
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
80069b2: 68fb ldr r3, [r7, #12]
|
|
80069b4: 2200 movs r2, #0
|
|
80069b6: 645a str r2, [r3, #68] @ 0x44
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
80069b8: 68fb ldr r3, [r7, #12]
|
|
80069ba: 2222 movs r2, #34 @ 0x22
|
|
80069bc: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Set the UART DMA transfer complete callback */
|
|
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
|
|
80069c0: 68fb ldr r3, [r7, #12]
|
|
80069c2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80069c4: 4a44 ldr r2, [pc, #272] @ (8006ad8 <UART_Start_Receive_DMA+0x140>)
|
|
80069c6: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Set the UART DMA Half transfer complete callback */
|
|
huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
|
|
80069c8: 68fb ldr r3, [r7, #12]
|
|
80069ca: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80069cc: 4a43 ldr r2, [pc, #268] @ (8006adc <UART_Start_Receive_DMA+0x144>)
|
|
80069ce: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set the DMA error callback */
|
|
huart->hdmarx->XferErrorCallback = UART_DMAError;
|
|
80069d0: 68fb ldr r3, [r7, #12]
|
|
80069d2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80069d4: 4a42 ldr r2, [pc, #264] @ (8006ae0 <UART_Start_Receive_DMA+0x148>)
|
|
80069d6: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Set the DMA abort callback */
|
|
huart->hdmarx->XferAbortCallback = NULL;
|
|
80069d8: 68fb ldr r3, [r7, #12]
|
|
80069da: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80069dc: 2200 movs r2, #0
|
|
80069de: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Enable the DMA stream */
|
|
tmp = (uint32_t *)&pData;
|
|
80069e0: f107 0308 add.w r3, r7, #8
|
|
80069e4: 65fb str r3, [r7, #92] @ 0x5c
|
|
if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK)
|
|
80069e6: 68fb ldr r3, [r7, #12]
|
|
80069e8: 6bd8 ldr r0, [r3, #60] @ 0x3c
|
|
80069ea: 68fb ldr r3, [r7, #12]
|
|
80069ec: 681b ldr r3, [r3, #0]
|
|
80069ee: 3304 adds r3, #4
|
|
80069f0: 4619 mov r1, r3
|
|
80069f2: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80069f4: 681a ldr r2, [r3, #0]
|
|
80069f6: 88fb ldrh r3, [r7, #6]
|
|
80069f8: f7fb fbe0 bl 80021bc <HAL_DMA_Start_IT>
|
|
80069fc: 4603 mov r3, r0
|
|
80069fe: 2b00 cmp r3, #0
|
|
8006a00: d008 beq.n 8006a14 <UART_Start_Receive_DMA+0x7c>
|
|
{
|
|
/* Set error code to DMA */
|
|
huart->ErrorCode = HAL_UART_ERROR_DMA;
|
|
8006a02: 68fb ldr r3, [r7, #12]
|
|
8006a04: 2210 movs r2, #16
|
|
8006a06: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Restore huart->RxState to ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006a08: 68fb ldr r3, [r7, #12]
|
|
8006a0a: 2220 movs r2, #32
|
|
8006a0c: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
return HAL_ERROR;
|
|
8006a10: 2301 movs r3, #1
|
|
8006a12: e05d b.n 8006ad0 <UART_Start_Receive_DMA+0x138>
|
|
}
|
|
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
|
|
__HAL_UART_CLEAR_OREFLAG(huart);
|
|
8006a14: 2300 movs r3, #0
|
|
8006a16: 613b str r3, [r7, #16]
|
|
8006a18: 68fb ldr r3, [r7, #12]
|
|
8006a1a: 681b ldr r3, [r3, #0]
|
|
8006a1c: 681b ldr r3, [r3, #0]
|
|
8006a1e: 613b str r3, [r7, #16]
|
|
8006a20: 68fb ldr r3, [r7, #12]
|
|
8006a22: 681b ldr r3, [r3, #0]
|
|
8006a24: 685b ldr r3, [r3, #4]
|
|
8006a26: 613b str r3, [r7, #16]
|
|
8006a28: 693b ldr r3, [r7, #16]
|
|
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
8006a2a: 68fb ldr r3, [r7, #12]
|
|
8006a2c: 691b ldr r3, [r3, #16]
|
|
8006a2e: 2b00 cmp r3, #0
|
|
8006a30: d019 beq.n 8006a66 <UART_Start_Receive_DMA+0xce>
|
|
{
|
|
/* Enable the UART Parity Error Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8006a32: 68fb ldr r3, [r7, #12]
|
|
8006a34: 681b ldr r3, [r3, #0]
|
|
8006a36: 330c adds r3, #12
|
|
8006a38: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006a3a: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8006a3c: e853 3f00 ldrex r3, [r3]
|
|
8006a40: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8006a42: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006a44: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8006a48: 65bb str r3, [r7, #88] @ 0x58
|
|
8006a4a: 68fb ldr r3, [r7, #12]
|
|
8006a4c: 681b ldr r3, [r3, #0]
|
|
8006a4e: 330c adds r3, #12
|
|
8006a50: 6dba ldr r2, [r7, #88] @ 0x58
|
|
8006a52: 64fa str r2, [r7, #76] @ 0x4c
|
|
8006a54: 64bb str r3, [r7, #72] @ 0x48
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006a56: 6cb9 ldr r1, [r7, #72] @ 0x48
|
|
8006a58: 6cfa ldr r2, [r7, #76] @ 0x4c
|
|
8006a5a: e841 2300 strex r3, r2, [r1]
|
|
8006a5e: 647b str r3, [r7, #68] @ 0x44
|
|
return(result);
|
|
8006a60: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8006a62: 2b00 cmp r3, #0
|
|
8006a64: d1e5 bne.n 8006a32 <UART_Start_Receive_DMA+0x9a>
|
|
}
|
|
|
|
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006a66: 68fb ldr r3, [r7, #12]
|
|
8006a68: 681b ldr r3, [r3, #0]
|
|
8006a6a: 3314 adds r3, #20
|
|
8006a6c: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006a6e: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8006a70: e853 3f00 ldrex r3, [r3]
|
|
8006a74: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8006a76: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006a78: f043 0301 orr.w r3, r3, #1
|
|
8006a7c: 657b str r3, [r7, #84] @ 0x54
|
|
8006a7e: 68fb ldr r3, [r7, #12]
|
|
8006a80: 681b ldr r3, [r3, #0]
|
|
8006a82: 3314 adds r3, #20
|
|
8006a84: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
8006a86: 63ba str r2, [r7, #56] @ 0x38
|
|
8006a88: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006a8a: 6b79 ldr r1, [r7, #52] @ 0x34
|
|
8006a8c: 6bba ldr r2, [r7, #56] @ 0x38
|
|
8006a8e: e841 2300 strex r3, r2, [r1]
|
|
8006a92: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8006a94: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006a96: 2b00 cmp r3, #0
|
|
8006a98: d1e5 bne.n 8006a66 <UART_Start_Receive_DMA+0xce>
|
|
|
|
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8006a9a: 68fb ldr r3, [r7, #12]
|
|
8006a9c: 681b ldr r3, [r3, #0]
|
|
8006a9e: 3314 adds r3, #20
|
|
8006aa0: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006aa2: 69bb ldr r3, [r7, #24]
|
|
8006aa4: e853 3f00 ldrex r3, [r3]
|
|
8006aa8: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8006aaa: 697b ldr r3, [r7, #20]
|
|
8006aac: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8006ab0: 653b str r3, [r7, #80] @ 0x50
|
|
8006ab2: 68fb ldr r3, [r7, #12]
|
|
8006ab4: 681b ldr r3, [r3, #0]
|
|
8006ab6: 3314 adds r3, #20
|
|
8006ab8: 6d3a ldr r2, [r7, #80] @ 0x50
|
|
8006aba: 627a str r2, [r7, #36] @ 0x24
|
|
8006abc: 623b str r3, [r7, #32]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006abe: 6a39 ldr r1, [r7, #32]
|
|
8006ac0: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8006ac2: e841 2300 strex r3, r2, [r1]
|
|
8006ac6: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8006ac8: 69fb ldr r3, [r7, #28]
|
|
8006aca: 2b00 cmp r3, #0
|
|
8006acc: d1e5 bne.n 8006a9a <UART_Start_Receive_DMA+0x102>
|
|
|
|
return HAL_OK;
|
|
8006ace: 2300 movs r3, #0
|
|
}
|
|
8006ad0: 4618 mov r0, r3
|
|
8006ad2: 3760 adds r7, #96 @ 0x60
|
|
8006ad4: 46bd mov sp, r7
|
|
8006ad6: bd80 pop {r7, pc}
|
|
8006ad8: 0800679b .word 0x0800679b
|
|
8006adc: 080068c7 .word 0x080068c7
|
|
8006ae0: 08006903 .word 0x08006903
|
|
|
|
08006ae4 <UART_EndTxTransfer>:
|
|
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
8006ae4: b480 push {r7}
|
|
8006ae6: b089 sub sp, #36 @ 0x24
|
|
8006ae8: af00 add r7, sp, #0
|
|
8006aea: 6078 str r0, [r7, #4]
|
|
/* Disable TXEIE and TCIE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
|
|
8006aec: 687b ldr r3, [r7, #4]
|
|
8006aee: 681b ldr r3, [r3, #0]
|
|
8006af0: 330c adds r3, #12
|
|
8006af2: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006af4: 68fb ldr r3, [r7, #12]
|
|
8006af6: e853 3f00 ldrex r3, [r3]
|
|
8006afa: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8006afc: 68bb ldr r3, [r7, #8]
|
|
8006afe: f023 03c0 bic.w r3, r3, #192 @ 0xc0
|
|
8006b02: 61fb str r3, [r7, #28]
|
|
8006b04: 687b ldr r3, [r7, #4]
|
|
8006b06: 681b ldr r3, [r3, #0]
|
|
8006b08: 330c adds r3, #12
|
|
8006b0a: 69fa ldr r2, [r7, #28]
|
|
8006b0c: 61ba str r2, [r7, #24]
|
|
8006b0e: 617b str r3, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006b10: 6979 ldr r1, [r7, #20]
|
|
8006b12: 69ba ldr r2, [r7, #24]
|
|
8006b14: e841 2300 strex r3, r2, [r1]
|
|
8006b18: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8006b1a: 693b ldr r3, [r7, #16]
|
|
8006b1c: 2b00 cmp r3, #0
|
|
8006b1e: d1e5 bne.n 8006aec <UART_EndTxTransfer+0x8>
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006b20: 687b ldr r3, [r7, #4]
|
|
8006b22: 2220 movs r2, #32
|
|
8006b24: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
}
|
|
8006b28: bf00 nop
|
|
8006b2a: 3724 adds r7, #36 @ 0x24
|
|
8006b2c: 46bd mov sp, r7
|
|
8006b2e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006b32: 4770 bx lr
|
|
|
|
08006b34 <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
8006b34: b480 push {r7}
|
|
8006b36: b095 sub sp, #84 @ 0x54
|
|
8006b38: af00 add r7, sp, #0
|
|
8006b3a: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
8006b3c: 687b ldr r3, [r7, #4]
|
|
8006b3e: 681b ldr r3, [r3, #0]
|
|
8006b40: 330c adds r3, #12
|
|
8006b42: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006b44: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006b46: e853 3f00 ldrex r3, [r3]
|
|
8006b4a: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8006b4c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006b4e: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8006b52: 64fb str r3, [r7, #76] @ 0x4c
|
|
8006b54: 687b ldr r3, [r7, #4]
|
|
8006b56: 681b ldr r3, [r3, #0]
|
|
8006b58: 330c adds r3, #12
|
|
8006b5a: 6cfa ldr r2, [r7, #76] @ 0x4c
|
|
8006b5c: 643a str r2, [r7, #64] @ 0x40
|
|
8006b5e: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006b60: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
8006b62: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8006b64: e841 2300 strex r3, r2, [r1]
|
|
8006b68: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8006b6a: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006b6c: 2b00 cmp r3, #0
|
|
8006b6e: d1e5 bne.n 8006b3c <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006b70: 687b ldr r3, [r7, #4]
|
|
8006b72: 681b ldr r3, [r3, #0]
|
|
8006b74: 3314 adds r3, #20
|
|
8006b76: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006b78: 6a3b ldr r3, [r7, #32]
|
|
8006b7a: e853 3f00 ldrex r3, [r3]
|
|
8006b7e: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8006b80: 69fb ldr r3, [r7, #28]
|
|
8006b82: f023 0301 bic.w r3, r3, #1
|
|
8006b86: 64bb str r3, [r7, #72] @ 0x48
|
|
8006b88: 687b ldr r3, [r7, #4]
|
|
8006b8a: 681b ldr r3, [r3, #0]
|
|
8006b8c: 3314 adds r3, #20
|
|
8006b8e: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8006b90: 62fa str r2, [r7, #44] @ 0x2c
|
|
8006b92: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006b94: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8006b96: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8006b98: e841 2300 strex r3, r2, [r1]
|
|
8006b9c: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8006b9e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006ba0: 2b00 cmp r3, #0
|
|
8006ba2: d1e5 bne.n 8006b70 <UART_EndRxTransfer+0x3c>
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8006ba4: 687b ldr r3, [r7, #4]
|
|
8006ba6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006ba8: 2b01 cmp r3, #1
|
|
8006baa: d119 bne.n 8006be0 <UART_EndRxTransfer+0xac>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8006bac: 687b ldr r3, [r7, #4]
|
|
8006bae: 681b ldr r3, [r3, #0]
|
|
8006bb0: 330c adds r3, #12
|
|
8006bb2: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006bb4: 68fb ldr r3, [r7, #12]
|
|
8006bb6: e853 3f00 ldrex r3, [r3]
|
|
8006bba: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8006bbc: 68bb ldr r3, [r7, #8]
|
|
8006bbe: f023 0310 bic.w r3, r3, #16
|
|
8006bc2: 647b str r3, [r7, #68] @ 0x44
|
|
8006bc4: 687b ldr r3, [r7, #4]
|
|
8006bc6: 681b ldr r3, [r3, #0]
|
|
8006bc8: 330c adds r3, #12
|
|
8006bca: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8006bcc: 61ba str r2, [r7, #24]
|
|
8006bce: 617b str r3, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006bd0: 6979 ldr r1, [r7, #20]
|
|
8006bd2: 69ba ldr r2, [r7, #24]
|
|
8006bd4: e841 2300 strex r3, r2, [r1]
|
|
8006bd8: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8006bda: 693b ldr r3, [r7, #16]
|
|
8006bdc: 2b00 cmp r3, #0
|
|
8006bde: d1e5 bne.n 8006bac <UART_EndRxTransfer+0x78>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006be0: 687b ldr r3, [r7, #4]
|
|
8006be2: 2220 movs r2, #32
|
|
8006be4: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8006be8: 687b ldr r3, [r7, #4]
|
|
8006bea: 2200 movs r2, #0
|
|
8006bec: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
8006bee: bf00 nop
|
|
8006bf0: 3754 adds r7, #84 @ 0x54
|
|
8006bf2: 46bd mov sp, r7
|
|
8006bf4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006bf8: 4770 bx lr
|
|
|
|
08006bfa <UART_DMAAbortOnError>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8006bfa: b580 push {r7, lr}
|
|
8006bfc: b084 sub sp, #16
|
|
8006bfe: af00 add r7, sp, #0
|
|
8006c00: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
8006c02: 687b ldr r3, [r7, #4]
|
|
8006c04: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006c06: 60fb str r3, [r7, #12]
|
|
huart->RxXferCount = 0x00U;
|
|
8006c08: 68fb ldr r3, [r7, #12]
|
|
8006c0a: 2200 movs r2, #0
|
|
8006c0c: 85da strh r2, [r3, #46] @ 0x2e
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8006c0e: 68f8 ldr r0, [r7, #12]
|
|
8006c10: f7fa f8c4 bl 8000d9c <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
8006c14: bf00 nop
|
|
8006c16: 3710 adds r7, #16
|
|
8006c18: 46bd mov sp, r7
|
|
8006c1a: bd80 pop {r7, pc}
|
|
|
|
08006c1c <UART_Transmit_IT>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
8006c1c: b480 push {r7}
|
|
8006c1e: b085 sub sp, #20
|
|
8006c20: af00 add r7, sp, #0
|
|
8006c22: 6078 str r0, [r7, #4]
|
|
const uint16_t *tmp;
|
|
|
|
/* Check that a Tx process is ongoing */
|
|
if (huart->gState == HAL_UART_STATE_BUSY_TX)
|
|
8006c24: 687b ldr r3, [r7, #4]
|
|
8006c26: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8006c2a: b2db uxtb r3, r3
|
|
8006c2c: 2b21 cmp r3, #33 @ 0x21
|
|
8006c2e: d13e bne.n 8006cae <UART_Transmit_IT+0x92>
|
|
{
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8006c30: 687b ldr r3, [r7, #4]
|
|
8006c32: 689b ldr r3, [r3, #8]
|
|
8006c34: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8006c38: d114 bne.n 8006c64 <UART_Transmit_IT+0x48>
|
|
8006c3a: 687b ldr r3, [r7, #4]
|
|
8006c3c: 691b ldr r3, [r3, #16]
|
|
8006c3e: 2b00 cmp r3, #0
|
|
8006c40: d110 bne.n 8006c64 <UART_Transmit_IT+0x48>
|
|
{
|
|
tmp = (const uint16_t *) huart->pTxBuffPtr;
|
|
8006c42: 687b ldr r3, [r7, #4]
|
|
8006c44: 6a1b ldr r3, [r3, #32]
|
|
8006c46: 60fb str r3, [r7, #12]
|
|
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
|
|
8006c48: 68fb ldr r3, [r7, #12]
|
|
8006c4a: 881b ldrh r3, [r3, #0]
|
|
8006c4c: 461a mov r2, r3
|
|
8006c4e: 687b ldr r3, [r7, #4]
|
|
8006c50: 681b ldr r3, [r3, #0]
|
|
8006c52: f3c2 0208 ubfx r2, r2, #0, #9
|
|
8006c56: 605a str r2, [r3, #4]
|
|
huart->pTxBuffPtr += 2U;
|
|
8006c58: 687b ldr r3, [r7, #4]
|
|
8006c5a: 6a1b ldr r3, [r3, #32]
|
|
8006c5c: 1c9a adds r2, r3, #2
|
|
8006c5e: 687b ldr r3, [r7, #4]
|
|
8006c60: 621a str r2, [r3, #32]
|
|
8006c62: e008 b.n 8006c76 <UART_Transmit_IT+0x5a>
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
|
|
8006c64: 687b ldr r3, [r7, #4]
|
|
8006c66: 6a1b ldr r3, [r3, #32]
|
|
8006c68: 1c59 adds r1, r3, #1
|
|
8006c6a: 687a ldr r2, [r7, #4]
|
|
8006c6c: 6211 str r1, [r2, #32]
|
|
8006c6e: 781a ldrb r2, [r3, #0]
|
|
8006c70: 687b ldr r3, [r7, #4]
|
|
8006c72: 681b ldr r3, [r3, #0]
|
|
8006c74: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if (--huart->TxXferCount == 0U)
|
|
8006c76: 687b ldr r3, [r7, #4]
|
|
8006c78: 8cdb ldrh r3, [r3, #38] @ 0x26
|
|
8006c7a: b29b uxth r3, r3
|
|
8006c7c: 3b01 subs r3, #1
|
|
8006c7e: b29b uxth r3, r3
|
|
8006c80: 687a ldr r2, [r7, #4]
|
|
8006c82: 4619 mov r1, r3
|
|
8006c84: 84d1 strh r1, [r2, #38] @ 0x26
|
|
8006c86: 2b00 cmp r3, #0
|
|
8006c88: d10f bne.n 8006caa <UART_Transmit_IT+0x8e>
|
|
{
|
|
/* Disable the UART Transmit Data Register Empty Interrupt */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
|
|
8006c8a: 687b ldr r3, [r7, #4]
|
|
8006c8c: 681b ldr r3, [r3, #0]
|
|
8006c8e: 68da ldr r2, [r3, #12]
|
|
8006c90: 687b ldr r3, [r7, #4]
|
|
8006c92: 681b ldr r3, [r3, #0]
|
|
8006c94: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
8006c98: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|
__HAL_UART_ENABLE_IT(huart, UART_IT_TC);
|
|
8006c9a: 687b ldr r3, [r7, #4]
|
|
8006c9c: 681b ldr r3, [r3, #0]
|
|
8006c9e: 68da ldr r2, [r3, #12]
|
|
8006ca0: 687b ldr r3, [r7, #4]
|
|
8006ca2: 681b ldr r3, [r3, #0]
|
|
8006ca4: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
8006ca8: 60da str r2, [r3, #12]
|
|
}
|
|
return HAL_OK;
|
|
8006caa: 2300 movs r3, #0
|
|
8006cac: e000 b.n 8006cb0 <UART_Transmit_IT+0x94>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8006cae: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8006cb0: 4618 mov r0, r3
|
|
8006cb2: 3714 adds r7, #20
|
|
8006cb4: 46bd mov sp, r7
|
|
8006cb6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006cba: 4770 bx lr
|
|
|
|
08006cbc <UART_EndTransmit_IT>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
8006cbc: b580 push {r7, lr}
|
|
8006cbe: b082 sub sp, #8
|
|
8006cc0: af00 add r7, sp, #0
|
|
8006cc2: 6078 str r0, [r7, #4]
|
|
/* Disable the UART Transmit Complete Interrupt */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
|
|
8006cc4: 687b ldr r3, [r7, #4]
|
|
8006cc6: 681b ldr r3, [r3, #0]
|
|
8006cc8: 68da ldr r2, [r3, #12]
|
|
8006cca: 687b ldr r3, [r7, #4]
|
|
8006ccc: 681b ldr r3, [r3, #0]
|
|
8006cce: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8006cd2: 60da str r2, [r3, #12]
|
|
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006cd4: 687b ldr r3, [r7, #4]
|
|
8006cd6: 2220 movs r2, #32
|
|
8006cd8: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
8006cdc: 6878 ldr r0, [r7, #4]
|
|
8006cde: f7ff fcd7 bl 8006690 <HAL_UART_TxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
|
|
return HAL_OK;
|
|
8006ce2: 2300 movs r3, #0
|
|
}
|
|
8006ce4: 4618 mov r0, r3
|
|
8006ce6: 3708 adds r7, #8
|
|
8006ce8: 46bd mov sp, r7
|
|
8006cea: bd80 pop {r7, pc}
|
|
|
|
08006cec <UART_Receive_IT>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
8006cec: b580 push {r7, lr}
|
|
8006cee: b08c sub sp, #48 @ 0x30
|
|
8006cf0: af00 add r7, sp, #0
|
|
8006cf2: 6078 str r0, [r7, #4]
|
|
uint8_t *pdata8bits = NULL;
|
|
8006cf4: 2300 movs r3, #0
|
|
8006cf6: 62fb str r3, [r7, #44] @ 0x2c
|
|
uint16_t *pdata16bits = NULL;
|
|
8006cf8: 2300 movs r3, #0
|
|
8006cfa: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
8006cfc: 687b ldr r3, [r7, #4]
|
|
8006cfe: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
8006d02: b2db uxtb r3, r3
|
|
8006d04: 2b22 cmp r3, #34 @ 0x22
|
|
8006d06: f040 80aa bne.w 8006e5e <UART_Receive_IT+0x172>
|
|
{
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8006d0a: 687b ldr r3, [r7, #4]
|
|
8006d0c: 689b ldr r3, [r3, #8]
|
|
8006d0e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8006d12: d115 bne.n 8006d40 <UART_Receive_IT+0x54>
|
|
8006d14: 687b ldr r3, [r7, #4]
|
|
8006d16: 691b ldr r3, [r3, #16]
|
|
8006d18: 2b00 cmp r3, #0
|
|
8006d1a: d111 bne.n 8006d40 <UART_Receive_IT+0x54>
|
|
{
|
|
/* Unused pdata8bits */
|
|
UNUSED(pdata8bits);
|
|
pdata16bits = (uint16_t *) huart->pRxBuffPtr;
|
|
8006d1c: 687b ldr r3, [r7, #4]
|
|
8006d1e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006d20: 62bb str r3, [r7, #40] @ 0x28
|
|
*pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
|
|
8006d22: 687b ldr r3, [r7, #4]
|
|
8006d24: 681b ldr r3, [r3, #0]
|
|
8006d26: 685b ldr r3, [r3, #4]
|
|
8006d28: b29b uxth r3, r3
|
|
8006d2a: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8006d2e: b29a uxth r2, r3
|
|
8006d30: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006d32: 801a strh r2, [r3, #0]
|
|
huart->pRxBuffPtr += 2U;
|
|
8006d34: 687b ldr r3, [r7, #4]
|
|
8006d36: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006d38: 1c9a adds r2, r3, #2
|
|
8006d3a: 687b ldr r3, [r7, #4]
|
|
8006d3c: 629a str r2, [r3, #40] @ 0x28
|
|
8006d3e: e024 b.n 8006d8a <UART_Receive_IT+0x9e>
|
|
}
|
|
else
|
|
{
|
|
pdata8bits = (uint8_t *) huart->pRxBuffPtr;
|
|
8006d40: 687b ldr r3, [r7, #4]
|
|
8006d42: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006d44: 62fb str r3, [r7, #44] @ 0x2c
|
|
/* Unused pdata16bits */
|
|
UNUSED(pdata16bits);
|
|
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
|
|
8006d46: 687b ldr r3, [r7, #4]
|
|
8006d48: 689b ldr r3, [r3, #8]
|
|
8006d4a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8006d4e: d007 beq.n 8006d60 <UART_Receive_IT+0x74>
|
|
8006d50: 687b ldr r3, [r7, #4]
|
|
8006d52: 689b ldr r3, [r3, #8]
|
|
8006d54: 2b00 cmp r3, #0
|
|
8006d56: d10a bne.n 8006d6e <UART_Receive_IT+0x82>
|
|
8006d58: 687b ldr r3, [r7, #4]
|
|
8006d5a: 691b ldr r3, [r3, #16]
|
|
8006d5c: 2b00 cmp r3, #0
|
|
8006d5e: d106 bne.n 8006d6e <UART_Receive_IT+0x82>
|
|
{
|
|
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
|
|
8006d60: 687b ldr r3, [r7, #4]
|
|
8006d62: 681b ldr r3, [r3, #0]
|
|
8006d64: 685b ldr r3, [r3, #4]
|
|
8006d66: b2da uxtb r2, r3
|
|
8006d68: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8006d6a: 701a strb r2, [r3, #0]
|
|
8006d6c: e008 b.n 8006d80 <UART_Receive_IT+0x94>
|
|
}
|
|
else
|
|
{
|
|
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
|
|
8006d6e: 687b ldr r3, [r7, #4]
|
|
8006d70: 681b ldr r3, [r3, #0]
|
|
8006d72: 685b ldr r3, [r3, #4]
|
|
8006d74: b2db uxtb r3, r3
|
|
8006d76: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8006d7a: b2da uxtb r2, r3
|
|
8006d7c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8006d7e: 701a strb r2, [r3, #0]
|
|
}
|
|
huart->pRxBuffPtr += 1U;
|
|
8006d80: 687b ldr r3, [r7, #4]
|
|
8006d82: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006d84: 1c5a adds r2, r3, #1
|
|
8006d86: 687b ldr r3, [r7, #4]
|
|
8006d88: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
if (--huart->RxXferCount == 0U)
|
|
8006d8a: 687b ldr r3, [r7, #4]
|
|
8006d8c: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
8006d8e: b29b uxth r3, r3
|
|
8006d90: 3b01 subs r3, #1
|
|
8006d92: b29b uxth r3, r3
|
|
8006d94: 687a ldr r2, [r7, #4]
|
|
8006d96: 4619 mov r1, r3
|
|
8006d98: 85d1 strh r1, [r2, #46] @ 0x2e
|
|
8006d9a: 2b00 cmp r3, #0
|
|
8006d9c: d15d bne.n 8006e5a <UART_Receive_IT+0x16e>
|
|
{
|
|
/* Disable the UART Data Register not empty Interrupt */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
|
|
8006d9e: 687b ldr r3, [r7, #4]
|
|
8006da0: 681b ldr r3, [r3, #0]
|
|
8006da2: 68da ldr r2, [r3, #12]
|
|
8006da4: 687b ldr r3, [r7, #4]
|
|
8006da6: 681b ldr r3, [r3, #0]
|
|
8006da8: f022 0220 bic.w r2, r2, #32
|
|
8006dac: 60da str r2, [r3, #12]
|
|
|
|
/* Disable the UART Parity Error Interrupt */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
|
|
8006dae: 687b ldr r3, [r7, #4]
|
|
8006db0: 681b ldr r3, [r3, #0]
|
|
8006db2: 68da ldr r2, [r3, #12]
|
|
8006db4: 687b ldr r3, [r7, #4]
|
|
8006db6: 681b ldr r3, [r3, #0]
|
|
8006db8: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8006dbc: 60da str r2, [r3, #12]
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
|
|
8006dbe: 687b ldr r3, [r7, #4]
|
|
8006dc0: 681b ldr r3, [r3, #0]
|
|
8006dc2: 695a ldr r2, [r3, #20]
|
|
8006dc4: 687b ldr r3, [r7, #4]
|
|
8006dc6: 681b ldr r3, [r3, #0]
|
|
8006dc8: f022 0201 bic.w r2, r2, #1
|
|
8006dcc: 615a str r2, [r3, #20]
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006dce: 687b ldr r3, [r7, #4]
|
|
8006dd0: 2220 movs r2, #32
|
|
8006dd2: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8006dd6: 687b ldr r3, [r7, #4]
|
|
8006dd8: 2200 movs r2, #0
|
|
8006dda: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8006ddc: 687b ldr r3, [r7, #4]
|
|
8006dde: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006de0: 2b01 cmp r3, #1
|
|
8006de2: d135 bne.n 8006e50 <UART_Receive_IT+0x164>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8006de4: 687b ldr r3, [r7, #4]
|
|
8006de6: 2200 movs r2, #0
|
|
8006de8: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8006dea: 687b ldr r3, [r7, #4]
|
|
8006dec: 681b ldr r3, [r3, #0]
|
|
8006dee: 330c adds r3, #12
|
|
8006df0: 617b str r3, [r7, #20]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006df2: 697b ldr r3, [r7, #20]
|
|
8006df4: e853 3f00 ldrex r3, [r3]
|
|
8006df8: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8006dfa: 693b ldr r3, [r7, #16]
|
|
8006dfc: f023 0310 bic.w r3, r3, #16
|
|
8006e00: 627b str r3, [r7, #36] @ 0x24
|
|
8006e02: 687b ldr r3, [r7, #4]
|
|
8006e04: 681b ldr r3, [r3, #0]
|
|
8006e06: 330c adds r3, #12
|
|
8006e08: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8006e0a: 623a str r2, [r7, #32]
|
|
8006e0c: 61fb str r3, [r7, #28]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006e0e: 69f9 ldr r1, [r7, #28]
|
|
8006e10: 6a3a ldr r2, [r7, #32]
|
|
8006e12: e841 2300 strex r3, r2, [r1]
|
|
8006e16: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
8006e18: 69bb ldr r3, [r7, #24]
|
|
8006e1a: 2b00 cmp r3, #0
|
|
8006e1c: d1e5 bne.n 8006dea <UART_Receive_IT+0xfe>
|
|
|
|
/* Check if IDLE flag is set */
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
|
|
8006e1e: 687b ldr r3, [r7, #4]
|
|
8006e20: 681b ldr r3, [r3, #0]
|
|
8006e22: 681b ldr r3, [r3, #0]
|
|
8006e24: f003 0310 and.w r3, r3, #16
|
|
8006e28: 2b10 cmp r3, #16
|
|
8006e2a: d10a bne.n 8006e42 <UART_Receive_IT+0x156>
|
|
{
|
|
/* Clear IDLE flag in ISR */
|
|
__HAL_UART_CLEAR_IDLEFLAG(huart);
|
|
8006e2c: 2300 movs r3, #0
|
|
8006e2e: 60fb str r3, [r7, #12]
|
|
8006e30: 687b ldr r3, [r7, #4]
|
|
8006e32: 681b ldr r3, [r3, #0]
|
|
8006e34: 681b ldr r3, [r3, #0]
|
|
8006e36: 60fb str r3, [r7, #12]
|
|
8006e38: 687b ldr r3, [r7, #4]
|
|
8006e3a: 681b ldr r3, [r3, #0]
|
|
8006e3c: 685b ldr r3, [r3, #4]
|
|
8006e3e: 60fb str r3, [r7, #12]
|
|
8006e40: 68fb ldr r3, [r7, #12]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8006e42: 687b ldr r3, [r7, #4]
|
|
8006e44: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8006e46: 4619 mov r1, r3
|
|
8006e48: 6878 ldr r0, [r7, #4]
|
|
8006e4a: f7ff fc3f bl 80066cc <HAL_UARTEx_RxEventCallback>
|
|
8006e4e: e002 b.n 8006e56 <UART_Receive_IT+0x16a>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx complete callback*/
|
|
huart->RxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8006e50: 6878 ldr r0, [r7, #4]
|
|
8006e52: f7f9 ff47 bl 8000ce4 <HAL_UART_RxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006e56: 2300 movs r3, #0
|
|
8006e58: e002 b.n 8006e60 <UART_Receive_IT+0x174>
|
|
}
|
|
return HAL_OK;
|
|
8006e5a: 2300 movs r3, #0
|
|
8006e5c: e000 b.n 8006e60 <UART_Receive_IT+0x174>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8006e5e: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8006e60: 4618 mov r0, r3
|
|
8006e62: 3730 adds r7, #48 @ 0x30
|
|
8006e64: 46bd mov sp, r7
|
|
8006e66: bd80 pop {r7, pc}
|
|
|
|
08006e68 <UART_SetConfig>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8006e68: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8006e6c: b0c0 sub sp, #256 @ 0x100
|
|
8006e6e: af00 add r7, sp, #0
|
|
8006e70: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4
|
|
assert_param(IS_UART_MODE(huart->Init.Mode));
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits
|
|
according to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
8006e74: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006e78: 681b ldr r3, [r3, #0]
|
|
8006e7a: 691b ldr r3, [r3, #16]
|
|
8006e7c: f423 5040 bic.w r0, r3, #12288 @ 0x3000
|
|
8006e80: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006e84: 68d9 ldr r1, [r3, #12]
|
|
8006e86: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006e8a: 681a ldr r2, [r3, #0]
|
|
8006e8c: ea40 0301 orr.w r3, r0, r1
|
|
8006e90: 6113 str r3, [r2, #16]
|
|
Set the M bits according to huart->Init.WordLength value
|
|
Set PCE and PS bits according to huart->Init.Parity value
|
|
Set TE and RE bits according to huart->Init.Mode value
|
|
Set OVER8 bit according to huart->Init.OverSampling value */
|
|
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
|
|
8006e92: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006e96: 689a ldr r2, [r3, #8]
|
|
8006e98: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006e9c: 691b ldr r3, [r3, #16]
|
|
8006e9e: 431a orrs r2, r3
|
|
8006ea0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006ea4: 695b ldr r3, [r3, #20]
|
|
8006ea6: 431a orrs r2, r3
|
|
8006ea8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006eac: 69db ldr r3, [r3, #28]
|
|
8006eae: 4313 orrs r3, r2
|
|
8006eb0: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
8006eb4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006eb8: 681b ldr r3, [r3, #0]
|
|
8006eba: 68db ldr r3, [r3, #12]
|
|
8006ebc: f423 4116 bic.w r1, r3, #38400 @ 0x9600
|
|
8006ec0: f021 010c bic.w r1, r1, #12
|
|
8006ec4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006ec8: 681a ldr r2, [r3, #0]
|
|
8006eca: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
|
|
8006ece: 430b orrs r3, r1
|
|
8006ed0: 60d3 str r3, [r2, #12]
|
|
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
|
tmpreg);
|
|
|
|
/*-------------------------- USART CR3 Configuration -----------------------*/
|
|
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
|
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
|
8006ed2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006ed6: 681b ldr r3, [r3, #0]
|
|
8006ed8: 695b ldr r3, [r3, #20]
|
|
8006eda: f423 7040 bic.w r0, r3, #768 @ 0x300
|
|
8006ede: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006ee2: 6999 ldr r1, [r3, #24]
|
|
8006ee4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006ee8: 681a ldr r2, [r3, #0]
|
|
8006eea: ea40 0301 orr.w r3, r0, r1
|
|
8006eee: 6153 str r3, [r2, #20]
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#elif defined(USART6)
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6))
|
|
8006ef0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006ef4: 681a ldr r2, [r3, #0]
|
|
8006ef6: 4b8f ldr r3, [pc, #572] @ (8007134 <UART_SetConfig+0x2cc>)
|
|
8006ef8: 429a cmp r2, r3
|
|
8006efa: d005 beq.n 8006f08 <UART_SetConfig+0xa0>
|
|
8006efc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006f00: 681a ldr r2, [r3, #0]
|
|
8006f02: 4b8d ldr r3, [pc, #564] @ (8007138 <UART_SetConfig+0x2d0>)
|
|
8006f04: 429a cmp r2, r3
|
|
8006f06: d104 bne.n 8006f12 <UART_SetConfig+0xaa>
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8006f08: f7fd fb42 bl 8004590 <HAL_RCC_GetPCLK2Freq>
|
|
8006f0c: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
8006f10: e003 b.n 8006f1a <UART_SetConfig+0xb2>
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#endif /* USART6 */
|
|
else
|
|
{
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8006f12: f7fd fb29 bl 8004568 <HAL_RCC_GetPCLK1Freq>
|
|
8006f16: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
}
|
|
/*-------------------------- USART BRR Configuration ---------------------*/
|
|
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8006f1a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006f1e: 69db ldr r3, [r3, #28]
|
|
8006f20: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8006f24: f040 810c bne.w 8007140 <UART_SetConfig+0x2d8>
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
|
|
8006f28: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006f2c: 2200 movs r2, #0
|
|
8006f2e: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
|
|
8006f32: f8c7 20ec str.w r2, [r7, #236] @ 0xec
|
|
8006f36: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8
|
|
8006f3a: 4622 mov r2, r4
|
|
8006f3c: 462b mov r3, r5
|
|
8006f3e: 1891 adds r1, r2, r2
|
|
8006f40: 65b9 str r1, [r7, #88] @ 0x58
|
|
8006f42: 415b adcs r3, r3
|
|
8006f44: 65fb str r3, [r7, #92] @ 0x5c
|
|
8006f46: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
|
|
8006f4a: 4621 mov r1, r4
|
|
8006f4c: eb12 0801 adds.w r8, r2, r1
|
|
8006f50: 4629 mov r1, r5
|
|
8006f52: eb43 0901 adc.w r9, r3, r1
|
|
8006f56: f04f 0200 mov.w r2, #0
|
|
8006f5a: f04f 0300 mov.w r3, #0
|
|
8006f5e: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8006f62: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8006f66: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
8006f6a: 4690 mov r8, r2
|
|
8006f6c: 4699 mov r9, r3
|
|
8006f6e: 4623 mov r3, r4
|
|
8006f70: eb18 0303 adds.w r3, r8, r3
|
|
8006f74: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
8006f78: 462b mov r3, r5
|
|
8006f7a: eb49 0303 adc.w r3, r9, r3
|
|
8006f7e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
8006f82: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006f86: 685b ldr r3, [r3, #4]
|
|
8006f88: 2200 movs r2, #0
|
|
8006f8a: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
8006f8e: f8c7 20dc str.w r2, [r7, #220] @ 0xdc
|
|
8006f92: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8
|
|
8006f96: 460b mov r3, r1
|
|
8006f98: 18db adds r3, r3, r3
|
|
8006f9a: 653b str r3, [r7, #80] @ 0x50
|
|
8006f9c: 4613 mov r3, r2
|
|
8006f9e: eb42 0303 adc.w r3, r2, r3
|
|
8006fa2: 657b str r3, [r7, #84] @ 0x54
|
|
8006fa4: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50
|
|
8006fa8: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0
|
|
8006fac: f7f9 f92a bl 8000204 <__aeabi_uldivmod>
|
|
8006fb0: 4602 mov r2, r0
|
|
8006fb2: 460b mov r3, r1
|
|
8006fb4: 4b61 ldr r3, [pc, #388] @ (800713c <UART_SetConfig+0x2d4>)
|
|
8006fb6: fba3 2302 umull r2, r3, r3, r2
|
|
8006fba: 095b lsrs r3, r3, #5
|
|
8006fbc: 011c lsls r4, r3, #4
|
|
8006fbe: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006fc2: 2200 movs r2, #0
|
|
8006fc4: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
8006fc8: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4
|
|
8006fcc: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0
|
|
8006fd0: 4642 mov r2, r8
|
|
8006fd2: 464b mov r3, r9
|
|
8006fd4: 1891 adds r1, r2, r2
|
|
8006fd6: 64b9 str r1, [r7, #72] @ 0x48
|
|
8006fd8: 415b adcs r3, r3
|
|
8006fda: 64fb str r3, [r7, #76] @ 0x4c
|
|
8006fdc: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
|
|
8006fe0: 4641 mov r1, r8
|
|
8006fe2: eb12 0a01 adds.w sl, r2, r1
|
|
8006fe6: 4649 mov r1, r9
|
|
8006fe8: eb43 0b01 adc.w fp, r3, r1
|
|
8006fec: f04f 0200 mov.w r2, #0
|
|
8006ff0: f04f 0300 mov.w r3, #0
|
|
8006ff4: ea4f 03cb mov.w r3, fp, lsl #3
|
|
8006ff8: ea43 735a orr.w r3, r3, sl, lsr #29
|
|
8006ffc: ea4f 02ca mov.w r2, sl, lsl #3
|
|
8007000: 4692 mov sl, r2
|
|
8007002: 469b mov fp, r3
|
|
8007004: 4643 mov r3, r8
|
|
8007006: eb1a 0303 adds.w r3, sl, r3
|
|
800700a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
800700e: 464b mov r3, r9
|
|
8007010: eb4b 0303 adc.w r3, fp, r3
|
|
8007014: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
|
|
8007018: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800701c: 685b ldr r3, [r3, #4]
|
|
800701e: 2200 movs r2, #0
|
|
8007020: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
8007024: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4
|
|
8007028: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0
|
|
800702c: 460b mov r3, r1
|
|
800702e: 18db adds r3, r3, r3
|
|
8007030: 643b str r3, [r7, #64] @ 0x40
|
|
8007032: 4613 mov r3, r2
|
|
8007034: eb42 0303 adc.w r3, r2, r3
|
|
8007038: 647b str r3, [r7, #68] @ 0x44
|
|
800703a: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40
|
|
800703e: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8
|
|
8007042: f7f9 f8df bl 8000204 <__aeabi_uldivmod>
|
|
8007046: 4602 mov r2, r0
|
|
8007048: 460b mov r3, r1
|
|
800704a: 4611 mov r1, r2
|
|
800704c: 4b3b ldr r3, [pc, #236] @ (800713c <UART_SetConfig+0x2d4>)
|
|
800704e: fba3 2301 umull r2, r3, r3, r1
|
|
8007052: 095b lsrs r3, r3, #5
|
|
8007054: 2264 movs r2, #100 @ 0x64
|
|
8007056: fb02 f303 mul.w r3, r2, r3
|
|
800705a: 1acb subs r3, r1, r3
|
|
800705c: 00db lsls r3, r3, #3
|
|
800705e: f103 0232 add.w r2, r3, #50 @ 0x32
|
|
8007062: 4b36 ldr r3, [pc, #216] @ (800713c <UART_SetConfig+0x2d4>)
|
|
8007064: fba3 2302 umull r2, r3, r3, r2
|
|
8007068: 095b lsrs r3, r3, #5
|
|
800706a: 005b lsls r3, r3, #1
|
|
800706c: f403 73f8 and.w r3, r3, #496 @ 0x1f0
|
|
8007070: 441c add r4, r3
|
|
8007072: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8007076: 2200 movs r2, #0
|
|
8007078: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
800707c: f8c7 20bc str.w r2, [r7, #188] @ 0xbc
|
|
8007080: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8
|
|
8007084: 4642 mov r2, r8
|
|
8007086: 464b mov r3, r9
|
|
8007088: 1891 adds r1, r2, r2
|
|
800708a: 63b9 str r1, [r7, #56] @ 0x38
|
|
800708c: 415b adcs r3, r3
|
|
800708e: 63fb str r3, [r7, #60] @ 0x3c
|
|
8007090: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38
|
|
8007094: 4641 mov r1, r8
|
|
8007096: 1851 adds r1, r2, r1
|
|
8007098: 6339 str r1, [r7, #48] @ 0x30
|
|
800709a: 4649 mov r1, r9
|
|
800709c: 414b adcs r3, r1
|
|
800709e: 637b str r3, [r7, #52] @ 0x34
|
|
80070a0: f04f 0200 mov.w r2, #0
|
|
80070a4: f04f 0300 mov.w r3, #0
|
|
80070a8: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30
|
|
80070ac: 4659 mov r1, fp
|
|
80070ae: 00cb lsls r3, r1, #3
|
|
80070b0: 4651 mov r1, sl
|
|
80070b2: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
80070b6: 4651 mov r1, sl
|
|
80070b8: 00ca lsls r2, r1, #3
|
|
80070ba: 4610 mov r0, r2
|
|
80070bc: 4619 mov r1, r3
|
|
80070be: 4603 mov r3, r0
|
|
80070c0: 4642 mov r2, r8
|
|
80070c2: 189b adds r3, r3, r2
|
|
80070c4: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
80070c8: 464b mov r3, r9
|
|
80070ca: 460a mov r2, r1
|
|
80070cc: eb42 0303 adc.w r3, r2, r3
|
|
80070d0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
80070d4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80070d8: 685b ldr r3, [r3, #4]
|
|
80070da: 2200 movs r2, #0
|
|
80070dc: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
80070e0: f8c7 20ac str.w r2, [r7, #172] @ 0xac
|
|
80070e4: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8
|
|
80070e8: 460b mov r3, r1
|
|
80070ea: 18db adds r3, r3, r3
|
|
80070ec: 62bb str r3, [r7, #40] @ 0x28
|
|
80070ee: 4613 mov r3, r2
|
|
80070f0: eb42 0303 adc.w r3, r2, r3
|
|
80070f4: 62fb str r3, [r7, #44] @ 0x2c
|
|
80070f6: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
|
|
80070fa: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0
|
|
80070fe: f7f9 f881 bl 8000204 <__aeabi_uldivmod>
|
|
8007102: 4602 mov r2, r0
|
|
8007104: 460b mov r3, r1
|
|
8007106: 4b0d ldr r3, [pc, #52] @ (800713c <UART_SetConfig+0x2d4>)
|
|
8007108: fba3 1302 umull r1, r3, r3, r2
|
|
800710c: 095b lsrs r3, r3, #5
|
|
800710e: 2164 movs r1, #100 @ 0x64
|
|
8007110: fb01 f303 mul.w r3, r1, r3
|
|
8007114: 1ad3 subs r3, r2, r3
|
|
8007116: 00db lsls r3, r3, #3
|
|
8007118: 3332 adds r3, #50 @ 0x32
|
|
800711a: 4a08 ldr r2, [pc, #32] @ (800713c <UART_SetConfig+0x2d4>)
|
|
800711c: fba2 2303 umull r2, r3, r2, r3
|
|
8007120: 095b lsrs r3, r3, #5
|
|
8007122: f003 0207 and.w r2, r3, #7
|
|
8007126: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800712a: 681b ldr r3, [r3, #0]
|
|
800712c: 4422 add r2, r4
|
|
800712e: 609a str r2, [r3, #8]
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
}
|
|
}
|
|
8007130: e106 b.n 8007340 <UART_SetConfig+0x4d8>
|
|
8007132: bf00 nop
|
|
8007134: 40011000 .word 0x40011000
|
|
8007138: 40011400 .word 0x40011400
|
|
800713c: 51eb851f .word 0x51eb851f
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
8007140: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8007144: 2200 movs r2, #0
|
|
8007146: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
800714a: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4
|
|
800714e: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0
|
|
8007152: 4642 mov r2, r8
|
|
8007154: 464b mov r3, r9
|
|
8007156: 1891 adds r1, r2, r2
|
|
8007158: 6239 str r1, [r7, #32]
|
|
800715a: 415b adcs r3, r3
|
|
800715c: 627b str r3, [r7, #36] @ 0x24
|
|
800715e: e9d7 2308 ldrd r2, r3, [r7, #32]
|
|
8007162: 4641 mov r1, r8
|
|
8007164: 1854 adds r4, r2, r1
|
|
8007166: 4649 mov r1, r9
|
|
8007168: eb43 0501 adc.w r5, r3, r1
|
|
800716c: f04f 0200 mov.w r2, #0
|
|
8007170: f04f 0300 mov.w r3, #0
|
|
8007174: 00eb lsls r3, r5, #3
|
|
8007176: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
800717a: 00e2 lsls r2, r4, #3
|
|
800717c: 4614 mov r4, r2
|
|
800717e: 461d mov r5, r3
|
|
8007180: 4643 mov r3, r8
|
|
8007182: 18e3 adds r3, r4, r3
|
|
8007184: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8007188: 464b mov r3, r9
|
|
800718a: eb45 0303 adc.w r3, r5, r3
|
|
800718e: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
8007192: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8007196: 685b ldr r3, [r3, #4]
|
|
8007198: 2200 movs r2, #0
|
|
800719a: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
800719e: f8c7 2094 str.w r2, [r7, #148] @ 0x94
|
|
80071a2: f04f 0200 mov.w r2, #0
|
|
80071a6: f04f 0300 mov.w r3, #0
|
|
80071aa: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
|
|
80071ae: 4629 mov r1, r5
|
|
80071b0: 008b lsls r3, r1, #2
|
|
80071b2: 4621 mov r1, r4
|
|
80071b4: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
80071b8: 4621 mov r1, r4
|
|
80071ba: 008a lsls r2, r1, #2
|
|
80071bc: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98
|
|
80071c0: f7f9 f820 bl 8000204 <__aeabi_uldivmod>
|
|
80071c4: 4602 mov r2, r0
|
|
80071c6: 460b mov r3, r1
|
|
80071c8: 4b60 ldr r3, [pc, #384] @ (800734c <UART_SetConfig+0x4e4>)
|
|
80071ca: fba3 2302 umull r2, r3, r3, r2
|
|
80071ce: 095b lsrs r3, r3, #5
|
|
80071d0: 011c lsls r4, r3, #4
|
|
80071d2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80071d6: 2200 movs r2, #0
|
|
80071d8: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
80071dc: f8c7 208c str.w r2, [r7, #140] @ 0x8c
|
|
80071e0: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88
|
|
80071e4: 4642 mov r2, r8
|
|
80071e6: 464b mov r3, r9
|
|
80071e8: 1891 adds r1, r2, r2
|
|
80071ea: 61b9 str r1, [r7, #24]
|
|
80071ec: 415b adcs r3, r3
|
|
80071ee: 61fb str r3, [r7, #28]
|
|
80071f0: e9d7 2306 ldrd r2, r3, [r7, #24]
|
|
80071f4: 4641 mov r1, r8
|
|
80071f6: 1851 adds r1, r2, r1
|
|
80071f8: 6139 str r1, [r7, #16]
|
|
80071fa: 4649 mov r1, r9
|
|
80071fc: 414b adcs r3, r1
|
|
80071fe: 617b str r3, [r7, #20]
|
|
8007200: f04f 0200 mov.w r2, #0
|
|
8007204: f04f 0300 mov.w r3, #0
|
|
8007208: e9d7 ab04 ldrd sl, fp, [r7, #16]
|
|
800720c: 4659 mov r1, fp
|
|
800720e: 00cb lsls r3, r1, #3
|
|
8007210: 4651 mov r1, sl
|
|
8007212: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8007216: 4651 mov r1, sl
|
|
8007218: 00ca lsls r2, r1, #3
|
|
800721a: 4610 mov r0, r2
|
|
800721c: 4619 mov r1, r3
|
|
800721e: 4603 mov r3, r0
|
|
8007220: 4642 mov r2, r8
|
|
8007222: 189b adds r3, r3, r2
|
|
8007224: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8007228: 464b mov r3, r9
|
|
800722a: 460a mov r2, r1
|
|
800722c: eb42 0303 adc.w r3, r2, r3
|
|
8007230: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8007234: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8007238: 685b ldr r3, [r3, #4]
|
|
800723a: 2200 movs r2, #0
|
|
800723c: 67bb str r3, [r7, #120] @ 0x78
|
|
800723e: 67fa str r2, [r7, #124] @ 0x7c
|
|
8007240: f04f 0200 mov.w r2, #0
|
|
8007244: f04f 0300 mov.w r3, #0
|
|
8007248: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78
|
|
800724c: 4649 mov r1, r9
|
|
800724e: 008b lsls r3, r1, #2
|
|
8007250: 4641 mov r1, r8
|
|
8007252: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8007256: 4641 mov r1, r8
|
|
8007258: 008a lsls r2, r1, #2
|
|
800725a: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80
|
|
800725e: f7f8 ffd1 bl 8000204 <__aeabi_uldivmod>
|
|
8007262: 4602 mov r2, r0
|
|
8007264: 460b mov r3, r1
|
|
8007266: 4611 mov r1, r2
|
|
8007268: 4b38 ldr r3, [pc, #224] @ (800734c <UART_SetConfig+0x4e4>)
|
|
800726a: fba3 2301 umull r2, r3, r3, r1
|
|
800726e: 095b lsrs r3, r3, #5
|
|
8007270: 2264 movs r2, #100 @ 0x64
|
|
8007272: fb02 f303 mul.w r3, r2, r3
|
|
8007276: 1acb subs r3, r1, r3
|
|
8007278: 011b lsls r3, r3, #4
|
|
800727a: 3332 adds r3, #50 @ 0x32
|
|
800727c: 4a33 ldr r2, [pc, #204] @ (800734c <UART_SetConfig+0x4e4>)
|
|
800727e: fba2 2303 umull r2, r3, r2, r3
|
|
8007282: 095b lsrs r3, r3, #5
|
|
8007284: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8007288: 441c add r4, r3
|
|
800728a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
800728e: 2200 movs r2, #0
|
|
8007290: 673b str r3, [r7, #112] @ 0x70
|
|
8007292: 677a str r2, [r7, #116] @ 0x74
|
|
8007294: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70
|
|
8007298: 4642 mov r2, r8
|
|
800729a: 464b mov r3, r9
|
|
800729c: 1891 adds r1, r2, r2
|
|
800729e: 60b9 str r1, [r7, #8]
|
|
80072a0: 415b adcs r3, r3
|
|
80072a2: 60fb str r3, [r7, #12]
|
|
80072a4: e9d7 2302 ldrd r2, r3, [r7, #8]
|
|
80072a8: 4641 mov r1, r8
|
|
80072aa: 1851 adds r1, r2, r1
|
|
80072ac: 6039 str r1, [r7, #0]
|
|
80072ae: 4649 mov r1, r9
|
|
80072b0: 414b adcs r3, r1
|
|
80072b2: 607b str r3, [r7, #4]
|
|
80072b4: f04f 0200 mov.w r2, #0
|
|
80072b8: f04f 0300 mov.w r3, #0
|
|
80072bc: e9d7 ab00 ldrd sl, fp, [r7]
|
|
80072c0: 4659 mov r1, fp
|
|
80072c2: 00cb lsls r3, r1, #3
|
|
80072c4: 4651 mov r1, sl
|
|
80072c6: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
80072ca: 4651 mov r1, sl
|
|
80072cc: 00ca lsls r2, r1, #3
|
|
80072ce: 4610 mov r0, r2
|
|
80072d0: 4619 mov r1, r3
|
|
80072d2: 4603 mov r3, r0
|
|
80072d4: 4642 mov r2, r8
|
|
80072d6: 189b adds r3, r3, r2
|
|
80072d8: 66bb str r3, [r7, #104] @ 0x68
|
|
80072da: 464b mov r3, r9
|
|
80072dc: 460a mov r2, r1
|
|
80072de: eb42 0303 adc.w r3, r2, r3
|
|
80072e2: 66fb str r3, [r7, #108] @ 0x6c
|
|
80072e4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80072e8: 685b ldr r3, [r3, #4]
|
|
80072ea: 2200 movs r2, #0
|
|
80072ec: 663b str r3, [r7, #96] @ 0x60
|
|
80072ee: 667a str r2, [r7, #100] @ 0x64
|
|
80072f0: f04f 0200 mov.w r2, #0
|
|
80072f4: f04f 0300 mov.w r3, #0
|
|
80072f8: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60
|
|
80072fc: 4649 mov r1, r9
|
|
80072fe: 008b lsls r3, r1, #2
|
|
8007300: 4641 mov r1, r8
|
|
8007302: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8007306: 4641 mov r1, r8
|
|
8007308: 008a lsls r2, r1, #2
|
|
800730a: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68
|
|
800730e: f7f8 ff79 bl 8000204 <__aeabi_uldivmod>
|
|
8007312: 4602 mov r2, r0
|
|
8007314: 460b mov r3, r1
|
|
8007316: 4b0d ldr r3, [pc, #52] @ (800734c <UART_SetConfig+0x4e4>)
|
|
8007318: fba3 1302 umull r1, r3, r3, r2
|
|
800731c: 095b lsrs r3, r3, #5
|
|
800731e: 2164 movs r1, #100 @ 0x64
|
|
8007320: fb01 f303 mul.w r3, r1, r3
|
|
8007324: 1ad3 subs r3, r2, r3
|
|
8007326: 011b lsls r3, r3, #4
|
|
8007328: 3332 adds r3, #50 @ 0x32
|
|
800732a: 4a08 ldr r2, [pc, #32] @ (800734c <UART_SetConfig+0x4e4>)
|
|
800732c: fba2 2303 umull r2, r3, r2, r3
|
|
8007330: 095b lsrs r3, r3, #5
|
|
8007332: f003 020f and.w r2, r3, #15
|
|
8007336: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800733a: 681b ldr r3, [r3, #0]
|
|
800733c: 4422 add r2, r4
|
|
800733e: 609a str r2, [r3, #8]
|
|
}
|
|
8007340: bf00 nop
|
|
8007342: f507 7780 add.w r7, r7, #256 @ 0x100
|
|
8007346: 46bd mov sp, r7
|
|
8007348: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
800734c: 51eb851f .word 0x51eb851f
|
|
|
|
08007350 <USB_CoreInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8007350: b084 sub sp, #16
|
|
8007352: b580 push {r7, lr}
|
|
8007354: b084 sub sp, #16
|
|
8007356: af00 add r7, sp, #0
|
|
8007358: 6078 str r0, [r7, #4]
|
|
800735a: f107 001c add.w r0, r7, #28
|
|
800735e: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret;
|
|
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
|
|
8007362: f897 3021 ldrb.w r3, [r7, #33] @ 0x21
|
|
8007366: 2b01 cmp r3, #1
|
|
8007368: d123 bne.n 80073b2 <USB_CoreInit+0x62>
|
|
{
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
800736a: 687b ldr r3, [r7, #4]
|
|
800736c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800736e: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
8007372: 687b ldr r3, [r7, #4]
|
|
8007374: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Init The ULPI Interface */
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
|
|
8007376: 687b ldr r3, [r7, #4]
|
|
8007378: 68db ldr r3, [r3, #12]
|
|
800737a: f423 0384 bic.w r3, r3, #4325376 @ 0x420000
|
|
800737e: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8007382: 687a ldr r2, [r7, #4]
|
|
8007384: 60d3 str r3, [r2, #12]
|
|
|
|
/* Select vbus source */
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
|
|
8007386: 687b ldr r3, [r7, #4]
|
|
8007388: 68db ldr r3, [r3, #12]
|
|
800738a: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
800738e: 687b ldr r3, [r7, #4]
|
|
8007390: 60da str r2, [r3, #12]
|
|
if (cfg.use_external_vbus == 1U)
|
|
8007392: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8007396: 2b01 cmp r3, #1
|
|
8007398: d105 bne.n 80073a6 <USB_CoreInit+0x56>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
|
|
800739a: 687b ldr r3, [r7, #4]
|
|
800739c: 68db ldr r3, [r3, #12]
|
|
800739e: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
|
|
80073a2: 687b ldr r3, [r7, #4]
|
|
80073a4: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
80073a6: 6878 ldr r0, [r7, #4]
|
|
80073a8: f001 fae2 bl 8008970 <USB_CoreReset>
|
|
80073ac: 4603 mov r3, r0
|
|
80073ae: 73fb strb r3, [r7, #15]
|
|
80073b0: e01b b.n 80073ea <USB_CoreInit+0x9a>
|
|
}
|
|
else /* FS interface (embedded Phy) */
|
|
{
|
|
/* Select FS Embedded PHY */
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
|
|
80073b2: 687b ldr r3, [r7, #4]
|
|
80073b4: 68db ldr r3, [r3, #12]
|
|
80073b6: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
80073ba: 687b ldr r3, [r7, #4]
|
|
80073bc: 60da str r2, [r3, #12]
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
80073be: 6878 ldr r0, [r7, #4]
|
|
80073c0: f001 fad6 bl 8008970 <USB_CoreReset>
|
|
80073c4: 4603 mov r3, r0
|
|
80073c6: 73fb strb r3, [r7, #15]
|
|
|
|
if (cfg.battery_charging_enable == 0U)
|
|
80073c8: f897 3025 ldrb.w r3, [r7, #37] @ 0x25
|
|
80073cc: 2b00 cmp r3, #0
|
|
80073ce: d106 bne.n 80073de <USB_CoreInit+0x8e>
|
|
{
|
|
/* Activate the USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
80073d0: 687b ldr r3, [r7, #4]
|
|
80073d2: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80073d4: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
80073d8: 687b ldr r3, [r7, #4]
|
|
80073da: 639a str r2, [r3, #56] @ 0x38
|
|
80073dc: e005 b.n 80073ea <USB_CoreInit+0x9a>
|
|
}
|
|
else
|
|
{
|
|
/* Deactivate the USB Transceiver */
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
80073de: 687b ldr r3, [r7, #4]
|
|
80073e0: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80073e2: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
80073e6: 687b ldr r3, [r7, #4]
|
|
80073e8: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
}
|
|
|
|
if (cfg.dma_enable == 1U)
|
|
80073ea: 7fbb ldrb r3, [r7, #30]
|
|
80073ec: 2b01 cmp r3, #1
|
|
80073ee: d10b bne.n 8007408 <USB_CoreInit+0xb8>
|
|
{
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
|
|
80073f0: 687b ldr r3, [r7, #4]
|
|
80073f2: 689b ldr r3, [r3, #8]
|
|
80073f4: f043 0206 orr.w r2, r3, #6
|
|
80073f8: 687b ldr r3, [r7, #4]
|
|
80073fa: 609a str r2, [r3, #8]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
|
|
80073fc: 687b ldr r3, [r7, #4]
|
|
80073fe: 689b ldr r3, [r3, #8]
|
|
8007400: f043 0220 orr.w r2, r3, #32
|
|
8007404: 687b ldr r3, [r7, #4]
|
|
8007406: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
return ret;
|
|
8007408: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800740a: 4618 mov r0, r3
|
|
800740c: 3710 adds r7, #16
|
|
800740e: 46bd mov sp, r7
|
|
8007410: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
8007414: b004 add sp, #16
|
|
8007416: 4770 bx lr
|
|
|
|
08007418 <USB_SetTurnaroundTime>:
|
|
* @param hclk: AHB clock frequency
|
|
* @retval USB turnaround time In PHY Clocks number
|
|
*/
|
|
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
|
|
uint32_t hclk, uint8_t speed)
|
|
{
|
|
8007418: b480 push {r7}
|
|
800741a: b087 sub sp, #28
|
|
800741c: af00 add r7, sp, #0
|
|
800741e: 60f8 str r0, [r7, #12]
|
|
8007420: 60b9 str r1, [r7, #8]
|
|
8007422: 4613 mov r3, r2
|
|
8007424: 71fb strb r3, [r7, #7]
|
|
|
|
/* The USBTRD is configured according to the tables below, depending on AHB frequency
|
|
used by application. In the low AHB frequency range it is used to stretch enough the USB response
|
|
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
|
|
latency to the Data FIFO */
|
|
if (speed == USBD_FS_SPEED)
|
|
8007426: 79fb ldrb r3, [r7, #7]
|
|
8007428: 2b02 cmp r3, #2
|
|
800742a: d165 bne.n 80074f8 <USB_SetTurnaroundTime+0xe0>
|
|
{
|
|
if ((hclk >= 14200000U) && (hclk < 15000000U))
|
|
800742c: 68bb ldr r3, [r7, #8]
|
|
800742e: 4a41 ldr r2, [pc, #260] @ (8007534 <USB_SetTurnaroundTime+0x11c>)
|
|
8007430: 4293 cmp r3, r2
|
|
8007432: d906 bls.n 8007442 <USB_SetTurnaroundTime+0x2a>
|
|
8007434: 68bb ldr r3, [r7, #8]
|
|
8007436: 4a40 ldr r2, [pc, #256] @ (8007538 <USB_SetTurnaroundTime+0x120>)
|
|
8007438: 4293 cmp r3, r2
|
|
800743a: d202 bcs.n 8007442 <USB_SetTurnaroundTime+0x2a>
|
|
{
|
|
/* hclk Clock Range between 14.2-15 MHz */
|
|
UsbTrd = 0xFU;
|
|
800743c: 230f movs r3, #15
|
|
800743e: 617b str r3, [r7, #20]
|
|
8007440: e062 b.n 8007508 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 15000000U) && (hclk < 16000000U))
|
|
8007442: 68bb ldr r3, [r7, #8]
|
|
8007444: 4a3c ldr r2, [pc, #240] @ (8007538 <USB_SetTurnaroundTime+0x120>)
|
|
8007446: 4293 cmp r3, r2
|
|
8007448: d306 bcc.n 8007458 <USB_SetTurnaroundTime+0x40>
|
|
800744a: 68bb ldr r3, [r7, #8]
|
|
800744c: 4a3b ldr r2, [pc, #236] @ (800753c <USB_SetTurnaroundTime+0x124>)
|
|
800744e: 4293 cmp r3, r2
|
|
8007450: d202 bcs.n 8007458 <USB_SetTurnaroundTime+0x40>
|
|
{
|
|
/* hclk Clock Range between 15-16 MHz */
|
|
UsbTrd = 0xEU;
|
|
8007452: 230e movs r3, #14
|
|
8007454: 617b str r3, [r7, #20]
|
|
8007456: e057 b.n 8007508 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 16000000U) && (hclk < 17200000U))
|
|
8007458: 68bb ldr r3, [r7, #8]
|
|
800745a: 4a38 ldr r2, [pc, #224] @ (800753c <USB_SetTurnaroundTime+0x124>)
|
|
800745c: 4293 cmp r3, r2
|
|
800745e: d306 bcc.n 800746e <USB_SetTurnaroundTime+0x56>
|
|
8007460: 68bb ldr r3, [r7, #8]
|
|
8007462: 4a37 ldr r2, [pc, #220] @ (8007540 <USB_SetTurnaroundTime+0x128>)
|
|
8007464: 4293 cmp r3, r2
|
|
8007466: d202 bcs.n 800746e <USB_SetTurnaroundTime+0x56>
|
|
{
|
|
/* hclk Clock Range between 16-17.2 MHz */
|
|
UsbTrd = 0xDU;
|
|
8007468: 230d movs r3, #13
|
|
800746a: 617b str r3, [r7, #20]
|
|
800746c: e04c b.n 8007508 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 17200000U) && (hclk < 18500000U))
|
|
800746e: 68bb ldr r3, [r7, #8]
|
|
8007470: 4a33 ldr r2, [pc, #204] @ (8007540 <USB_SetTurnaroundTime+0x128>)
|
|
8007472: 4293 cmp r3, r2
|
|
8007474: d306 bcc.n 8007484 <USB_SetTurnaroundTime+0x6c>
|
|
8007476: 68bb ldr r3, [r7, #8]
|
|
8007478: 4a32 ldr r2, [pc, #200] @ (8007544 <USB_SetTurnaroundTime+0x12c>)
|
|
800747a: 4293 cmp r3, r2
|
|
800747c: d802 bhi.n 8007484 <USB_SetTurnaroundTime+0x6c>
|
|
{
|
|
/* hclk Clock Range between 17.2-18.5 MHz */
|
|
UsbTrd = 0xCU;
|
|
800747e: 230c movs r3, #12
|
|
8007480: 617b str r3, [r7, #20]
|
|
8007482: e041 b.n 8007508 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 18500000U) && (hclk < 20000000U))
|
|
8007484: 68bb ldr r3, [r7, #8]
|
|
8007486: 4a2f ldr r2, [pc, #188] @ (8007544 <USB_SetTurnaroundTime+0x12c>)
|
|
8007488: 4293 cmp r3, r2
|
|
800748a: d906 bls.n 800749a <USB_SetTurnaroundTime+0x82>
|
|
800748c: 68bb ldr r3, [r7, #8]
|
|
800748e: 4a2e ldr r2, [pc, #184] @ (8007548 <USB_SetTurnaroundTime+0x130>)
|
|
8007490: 4293 cmp r3, r2
|
|
8007492: d802 bhi.n 800749a <USB_SetTurnaroundTime+0x82>
|
|
{
|
|
/* hclk Clock Range between 18.5-20 MHz */
|
|
UsbTrd = 0xBU;
|
|
8007494: 230b movs r3, #11
|
|
8007496: 617b str r3, [r7, #20]
|
|
8007498: e036 b.n 8007508 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 20000000U) && (hclk < 21800000U))
|
|
800749a: 68bb ldr r3, [r7, #8]
|
|
800749c: 4a2a ldr r2, [pc, #168] @ (8007548 <USB_SetTurnaroundTime+0x130>)
|
|
800749e: 4293 cmp r3, r2
|
|
80074a0: d906 bls.n 80074b0 <USB_SetTurnaroundTime+0x98>
|
|
80074a2: 68bb ldr r3, [r7, #8]
|
|
80074a4: 4a29 ldr r2, [pc, #164] @ (800754c <USB_SetTurnaroundTime+0x134>)
|
|
80074a6: 4293 cmp r3, r2
|
|
80074a8: d802 bhi.n 80074b0 <USB_SetTurnaroundTime+0x98>
|
|
{
|
|
/* hclk Clock Range between 20-21.8 MHz */
|
|
UsbTrd = 0xAU;
|
|
80074aa: 230a movs r3, #10
|
|
80074ac: 617b str r3, [r7, #20]
|
|
80074ae: e02b b.n 8007508 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 21800000U) && (hclk < 24000000U))
|
|
80074b0: 68bb ldr r3, [r7, #8]
|
|
80074b2: 4a26 ldr r2, [pc, #152] @ (800754c <USB_SetTurnaroundTime+0x134>)
|
|
80074b4: 4293 cmp r3, r2
|
|
80074b6: d906 bls.n 80074c6 <USB_SetTurnaroundTime+0xae>
|
|
80074b8: 68bb ldr r3, [r7, #8]
|
|
80074ba: 4a25 ldr r2, [pc, #148] @ (8007550 <USB_SetTurnaroundTime+0x138>)
|
|
80074bc: 4293 cmp r3, r2
|
|
80074be: d202 bcs.n 80074c6 <USB_SetTurnaroundTime+0xae>
|
|
{
|
|
/* hclk Clock Range between 21.8-24 MHz */
|
|
UsbTrd = 0x9U;
|
|
80074c0: 2309 movs r3, #9
|
|
80074c2: 617b str r3, [r7, #20]
|
|
80074c4: e020 b.n 8007508 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 24000000U) && (hclk < 27700000U))
|
|
80074c6: 68bb ldr r3, [r7, #8]
|
|
80074c8: 4a21 ldr r2, [pc, #132] @ (8007550 <USB_SetTurnaroundTime+0x138>)
|
|
80074ca: 4293 cmp r3, r2
|
|
80074cc: d306 bcc.n 80074dc <USB_SetTurnaroundTime+0xc4>
|
|
80074ce: 68bb ldr r3, [r7, #8]
|
|
80074d0: 4a20 ldr r2, [pc, #128] @ (8007554 <USB_SetTurnaroundTime+0x13c>)
|
|
80074d2: 4293 cmp r3, r2
|
|
80074d4: d802 bhi.n 80074dc <USB_SetTurnaroundTime+0xc4>
|
|
{
|
|
/* hclk Clock Range between 24-27.7 MHz */
|
|
UsbTrd = 0x8U;
|
|
80074d6: 2308 movs r3, #8
|
|
80074d8: 617b str r3, [r7, #20]
|
|
80074da: e015 b.n 8007508 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 27700000U) && (hclk < 32000000U))
|
|
80074dc: 68bb ldr r3, [r7, #8]
|
|
80074de: 4a1d ldr r2, [pc, #116] @ (8007554 <USB_SetTurnaroundTime+0x13c>)
|
|
80074e0: 4293 cmp r3, r2
|
|
80074e2: d906 bls.n 80074f2 <USB_SetTurnaroundTime+0xda>
|
|
80074e4: 68bb ldr r3, [r7, #8]
|
|
80074e6: 4a1c ldr r2, [pc, #112] @ (8007558 <USB_SetTurnaroundTime+0x140>)
|
|
80074e8: 4293 cmp r3, r2
|
|
80074ea: d202 bcs.n 80074f2 <USB_SetTurnaroundTime+0xda>
|
|
{
|
|
/* hclk Clock Range between 27.7-32 MHz */
|
|
UsbTrd = 0x7U;
|
|
80074ec: 2307 movs r3, #7
|
|
80074ee: 617b str r3, [r7, #20]
|
|
80074f0: e00a b.n 8007508 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else /* if(hclk >= 32000000) */
|
|
{
|
|
/* hclk Clock Range between 32-200 MHz */
|
|
UsbTrd = 0x6U;
|
|
80074f2: 2306 movs r3, #6
|
|
80074f4: 617b str r3, [r7, #20]
|
|
80074f6: e007 b.n 8007508 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
}
|
|
else if (speed == USBD_HS_SPEED)
|
|
80074f8: 79fb ldrb r3, [r7, #7]
|
|
80074fa: 2b00 cmp r3, #0
|
|
80074fc: d102 bne.n 8007504 <USB_SetTurnaroundTime+0xec>
|
|
{
|
|
UsbTrd = USBD_HS_TRDT_VALUE;
|
|
80074fe: 2309 movs r3, #9
|
|
8007500: 617b str r3, [r7, #20]
|
|
8007502: e001 b.n 8007508 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else
|
|
{
|
|
UsbTrd = USBD_DEFAULT_TRDT_VALUE;
|
|
8007504: 2309 movs r3, #9
|
|
8007506: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
|
|
8007508: 68fb ldr r3, [r7, #12]
|
|
800750a: 68db ldr r3, [r3, #12]
|
|
800750c: f423 5270 bic.w r2, r3, #15360 @ 0x3c00
|
|
8007510: 68fb ldr r3, [r7, #12]
|
|
8007512: 60da str r2, [r3, #12]
|
|
USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
|
|
8007514: 68fb ldr r3, [r7, #12]
|
|
8007516: 68da ldr r2, [r3, #12]
|
|
8007518: 697b ldr r3, [r7, #20]
|
|
800751a: 029b lsls r3, r3, #10
|
|
800751c: f403 5370 and.w r3, r3, #15360 @ 0x3c00
|
|
8007520: 431a orrs r2, r3
|
|
8007522: 68fb ldr r3, [r7, #12]
|
|
8007524: 60da str r2, [r3, #12]
|
|
|
|
return HAL_OK;
|
|
8007526: 2300 movs r3, #0
|
|
}
|
|
8007528: 4618 mov r0, r3
|
|
800752a: 371c adds r7, #28
|
|
800752c: 46bd mov sp, r7
|
|
800752e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007532: 4770 bx lr
|
|
8007534: 00d8acbf .word 0x00d8acbf
|
|
8007538: 00e4e1c0 .word 0x00e4e1c0
|
|
800753c: 00f42400 .word 0x00f42400
|
|
8007540: 01067380 .word 0x01067380
|
|
8007544: 011a499f .word 0x011a499f
|
|
8007548: 01312cff .word 0x01312cff
|
|
800754c: 014ca43f .word 0x014ca43f
|
|
8007550: 016e3600 .word 0x016e3600
|
|
8007554: 01a6ab1f .word 0x01a6ab1f
|
|
8007558: 01e84800 .word 0x01e84800
|
|
|
|
0800755c <USB_EnableGlobalInt>:
|
|
* Enables the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800755c: b480 push {r7}
|
|
800755e: b083 sub sp, #12
|
|
8007560: af00 add r7, sp, #0
|
|
8007562: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
|
|
8007564: 687b ldr r3, [r7, #4]
|
|
8007566: 689b ldr r3, [r3, #8]
|
|
8007568: f043 0201 orr.w r2, r3, #1
|
|
800756c: 687b ldr r3, [r7, #4]
|
|
800756e: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
8007570: 2300 movs r3, #0
|
|
}
|
|
8007572: 4618 mov r0, r3
|
|
8007574: 370c adds r7, #12
|
|
8007576: 46bd mov sp, r7
|
|
8007578: f85d 7b04 ldr.w r7, [sp], #4
|
|
800757c: 4770 bx lr
|
|
|
|
0800757e <USB_DisableGlobalInt>:
|
|
* Disable the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800757e: b480 push {r7}
|
|
8007580: b083 sub sp, #12
|
|
8007582: af00 add r7, sp, #0
|
|
8007584: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
|
|
8007586: 687b ldr r3, [r7, #4]
|
|
8007588: 689b ldr r3, [r3, #8]
|
|
800758a: f023 0201 bic.w r2, r3, #1
|
|
800758e: 687b ldr r3, [r7, #4]
|
|
8007590: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
8007592: 2300 movs r3, #0
|
|
}
|
|
8007594: 4618 mov r0, r3
|
|
8007596: 370c adds r7, #12
|
|
8007598: 46bd mov sp, r7
|
|
800759a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800759e: 4770 bx lr
|
|
|
|
080075a0 <USB_SetCurrentMode>:
|
|
* @arg USB_DEVICE_MODE Peripheral mode
|
|
* @arg USB_HOST_MODE Host mode
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
|
|
{
|
|
80075a0: b580 push {r7, lr}
|
|
80075a2: b084 sub sp, #16
|
|
80075a4: af00 add r7, sp, #0
|
|
80075a6: 6078 str r0, [r7, #4]
|
|
80075a8: 460b mov r3, r1
|
|
80075aa: 70fb strb r3, [r7, #3]
|
|
uint32_t ms = 0U;
|
|
80075ac: 2300 movs r3, #0
|
|
80075ae: 60fb str r3, [r7, #12]
|
|
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
|
|
80075b0: 687b ldr r3, [r7, #4]
|
|
80075b2: 68db ldr r3, [r3, #12]
|
|
80075b4: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000
|
|
80075b8: 687b ldr r3, [r7, #4]
|
|
80075ba: 60da str r2, [r3, #12]
|
|
|
|
if (mode == USB_HOST_MODE)
|
|
80075bc: 78fb ldrb r3, [r7, #3]
|
|
80075be: 2b01 cmp r3, #1
|
|
80075c0: d115 bne.n 80075ee <USB_SetCurrentMode+0x4e>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
|
|
80075c2: 687b ldr r3, [r7, #4]
|
|
80075c4: 68db ldr r3, [r3, #12]
|
|
80075c6: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000
|
|
80075ca: 687b ldr r3, [r7, #4]
|
|
80075cc: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
80075ce: 200a movs r0, #10
|
|
80075d0: f7fa fc10 bl 8001df4 <HAL_Delay>
|
|
ms += 10U;
|
|
80075d4: 68fb ldr r3, [r7, #12]
|
|
80075d6: 330a adds r3, #10
|
|
80075d8: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
80075da: 6878 ldr r0, [r7, #4]
|
|
80075dc: f001 f939 bl 8008852 <USB_GetMode>
|
|
80075e0: 4603 mov r3, r0
|
|
80075e2: 2b01 cmp r3, #1
|
|
80075e4: d01e beq.n 8007624 <USB_SetCurrentMode+0x84>
|
|
80075e6: 68fb ldr r3, [r7, #12]
|
|
80075e8: 2bc7 cmp r3, #199 @ 0xc7
|
|
80075ea: d9f0 bls.n 80075ce <USB_SetCurrentMode+0x2e>
|
|
80075ec: e01a b.n 8007624 <USB_SetCurrentMode+0x84>
|
|
}
|
|
else if (mode == USB_DEVICE_MODE)
|
|
80075ee: 78fb ldrb r3, [r7, #3]
|
|
80075f0: 2b00 cmp r3, #0
|
|
80075f2: d115 bne.n 8007620 <USB_SetCurrentMode+0x80>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
|
|
80075f4: 687b ldr r3, [r7, #4]
|
|
80075f6: 68db ldr r3, [r3, #12]
|
|
80075f8: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000
|
|
80075fc: 687b ldr r3, [r7, #4]
|
|
80075fe: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
8007600: 200a movs r0, #10
|
|
8007602: f7fa fbf7 bl 8001df4 <HAL_Delay>
|
|
ms += 10U;
|
|
8007606: 68fb ldr r3, [r7, #12]
|
|
8007608: 330a adds r3, #10
|
|
800760a: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
800760c: 6878 ldr r0, [r7, #4]
|
|
800760e: f001 f920 bl 8008852 <USB_GetMode>
|
|
8007612: 4603 mov r3, r0
|
|
8007614: 2b00 cmp r3, #0
|
|
8007616: d005 beq.n 8007624 <USB_SetCurrentMode+0x84>
|
|
8007618: 68fb ldr r3, [r7, #12]
|
|
800761a: 2bc7 cmp r3, #199 @ 0xc7
|
|
800761c: d9f0 bls.n 8007600 <USB_SetCurrentMode+0x60>
|
|
800761e: e001 b.n 8007624 <USB_SetCurrentMode+0x84>
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
8007620: 2301 movs r3, #1
|
|
8007622: e005 b.n 8007630 <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
|
|
8007624: 68fb ldr r3, [r7, #12]
|
|
8007626: 2bc8 cmp r3, #200 @ 0xc8
|
|
8007628: d101 bne.n 800762e <USB_SetCurrentMode+0x8e>
|
|
{
|
|
return HAL_ERROR;
|
|
800762a: 2301 movs r3, #1
|
|
800762c: e000 b.n 8007630 <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800762e: 2300 movs r3, #0
|
|
}
|
|
8007630: 4618 mov r0, r3
|
|
8007632: 3710 adds r7, #16
|
|
8007634: 46bd mov sp, r7
|
|
8007636: bd80 pop {r7, pc}
|
|
|
|
08007638 <USB_DevInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8007638: b084 sub sp, #16
|
|
800763a: b580 push {r7, lr}
|
|
800763c: b086 sub sp, #24
|
|
800763e: af00 add r7, sp, #0
|
|
8007640: 6078 str r0, [r7, #4]
|
|
8007642: f107 0024 add.w r0, r7, #36 @ 0x24
|
|
8007646: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
800764a: 2300 movs r3, #0
|
|
800764c: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800764e: 687b ldr r3, [r7, #4]
|
|
8007650: 60fb str r3, [r7, #12]
|
|
uint32_t i;
|
|
|
|
for (i = 0U; i < 15U; i++)
|
|
8007652: 2300 movs r3, #0
|
|
8007654: 613b str r3, [r7, #16]
|
|
8007656: e009 b.n 800766c <USB_DevInit+0x34>
|
|
{
|
|
USBx->DIEPTXF[i] = 0U;
|
|
8007658: 687a ldr r2, [r7, #4]
|
|
800765a: 693b ldr r3, [r7, #16]
|
|
800765c: 3340 adds r3, #64 @ 0x40
|
|
800765e: 009b lsls r3, r3, #2
|
|
8007660: 4413 add r3, r2
|
|
8007662: 2200 movs r2, #0
|
|
8007664: 605a str r2, [r3, #4]
|
|
for (i = 0U; i < 15U; i++)
|
|
8007666: 693b ldr r3, [r7, #16]
|
|
8007668: 3301 adds r3, #1
|
|
800766a: 613b str r3, [r7, #16]
|
|
800766c: 693b ldr r3, [r7, #16]
|
|
800766e: 2b0e cmp r3, #14
|
|
8007670: d9f2 bls.n 8007658 <USB_DevInit+0x20>
|
|
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* VBUS Sensing setup */
|
|
if (cfg.vbus_sensing_enable == 0U)
|
|
8007672: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
8007676: 2b00 cmp r3, #0
|
|
8007678: d11c bne.n 80076b4 <USB_DevInit+0x7c>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
800767a: 68fb ldr r3, [r7, #12]
|
|
800767c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007680: 685b ldr r3, [r3, #4]
|
|
8007682: 68fa ldr r2, [r7, #12]
|
|
8007684: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8007688: f043 0302 orr.w r3, r3, #2
|
|
800768c: 6053 str r3, [r2, #4]
|
|
|
|
/* Deactivate VBUS Sensing B */
|
|
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
|
|
800768e: 687b ldr r3, [r7, #4]
|
|
8007690: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8007692: f423 1200 bic.w r2, r3, #2097152 @ 0x200000
|
|
8007696: 687b ldr r3, [r7, #4]
|
|
8007698: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* B-peripheral session valid override enable */
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
|
|
800769a: 687b ldr r3, [r7, #4]
|
|
800769c: 681b ldr r3, [r3, #0]
|
|
800769e: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
80076a2: 687b ldr r3, [r7, #4]
|
|
80076a4: 601a str r2, [r3, #0]
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
|
|
80076a6: 687b ldr r3, [r7, #4]
|
|
80076a8: 681b ldr r3, [r3, #0]
|
|
80076aa: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
80076ae: 687b ldr r3, [r7, #4]
|
|
80076b0: 601a str r2, [r3, #0]
|
|
80076b2: e005 b.n 80076c0 <USB_DevInit+0x88>
|
|
}
|
|
else
|
|
{
|
|
/* Enable HW VBUS sensing */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
|
|
80076b4: 687b ldr r3, [r7, #4]
|
|
80076b6: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80076b8: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
|
|
80076bc: 687b ldr r3, [r7, #4]
|
|
80076be: 639a str r2, [r3, #56] @ 0x38
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
|
|
/* Restart the Phy Clock */
|
|
USBx_PCGCCTL = 0U;
|
|
80076c0: 68fb ldr r3, [r7, #12]
|
|
80076c2: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80076c6: 461a mov r2, r3
|
|
80076c8: 2300 movs r3, #0
|
|
80076ca: 6013 str r3, [r2, #0]
|
|
|
|
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
|
|
80076cc: f897 3029 ldrb.w r3, [r7, #41] @ 0x29
|
|
80076d0: 2b01 cmp r3, #1
|
|
80076d2: d10d bne.n 80076f0 <USB_DevInit+0xb8>
|
|
{
|
|
if (cfg.speed == USBD_HS_SPEED)
|
|
80076d4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80076d8: 2b00 cmp r3, #0
|
|
80076da: d104 bne.n 80076e6 <USB_DevInit+0xae>
|
|
{
|
|
/* Set Core speed to High speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
|
|
80076dc: 2100 movs r1, #0
|
|
80076de: 6878 ldr r0, [r7, #4]
|
|
80076e0: f000 f968 bl 80079b4 <USB_SetDevSpeed>
|
|
80076e4: e008 b.n 80076f8 <USB_DevInit+0xc0>
|
|
}
|
|
else
|
|
{
|
|
/* Set Core speed to Full speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
|
|
80076e6: 2101 movs r1, #1
|
|
80076e8: 6878 ldr r0, [r7, #4]
|
|
80076ea: f000 f963 bl 80079b4 <USB_SetDevSpeed>
|
|
80076ee: e003 b.n 80076f8 <USB_DevInit+0xc0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set Core speed to Full speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
|
|
80076f0: 2103 movs r1, #3
|
|
80076f2: 6878 ldr r0, [r7, #4]
|
|
80076f4: f000 f95e bl 80079b4 <USB_SetDevSpeed>
|
|
}
|
|
|
|
/* Flush the FIFOs */
|
|
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
|
|
80076f8: 2110 movs r1, #16
|
|
80076fa: 6878 ldr r0, [r7, #4]
|
|
80076fc: f000 f8fa bl 80078f4 <USB_FlushTxFifo>
|
|
8007700: 4603 mov r3, r0
|
|
8007702: 2b00 cmp r3, #0
|
|
8007704: d001 beq.n 800770a <USB_DevInit+0xd2>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8007706: 2301 movs r3, #1
|
|
8007708: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (USB_FlushRxFifo(USBx) != HAL_OK)
|
|
800770a: 6878 ldr r0, [r7, #4]
|
|
800770c: f000 f924 bl 8007958 <USB_FlushRxFifo>
|
|
8007710: 4603 mov r3, r0
|
|
8007712: 2b00 cmp r3, #0
|
|
8007714: d001 beq.n 800771a <USB_DevInit+0xe2>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8007716: 2301 movs r3, #1
|
|
8007718: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Clear all pending Device Interrupts */
|
|
USBx_DEVICE->DIEPMSK = 0U;
|
|
800771a: 68fb ldr r3, [r7, #12]
|
|
800771c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007720: 461a mov r2, r3
|
|
8007722: 2300 movs r3, #0
|
|
8007724: 6113 str r3, [r2, #16]
|
|
USBx_DEVICE->DOEPMSK = 0U;
|
|
8007726: 68fb ldr r3, [r7, #12]
|
|
8007728: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800772c: 461a mov r2, r3
|
|
800772e: 2300 movs r3, #0
|
|
8007730: 6153 str r3, [r2, #20]
|
|
USBx_DEVICE->DAINTMSK = 0U;
|
|
8007732: 68fb ldr r3, [r7, #12]
|
|
8007734: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007738: 461a mov r2, r3
|
|
800773a: 2300 movs r3, #0
|
|
800773c: 61d3 str r3, [r2, #28]
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
800773e: 2300 movs r3, #0
|
|
8007740: 613b str r3, [r7, #16]
|
|
8007742: e043 b.n 80077cc <USB_DevInit+0x194>
|
|
{
|
|
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
8007744: 693b ldr r3, [r7, #16]
|
|
8007746: 015a lsls r2, r3, #5
|
|
8007748: 68fb ldr r3, [r7, #12]
|
|
800774a: 4413 add r3, r2
|
|
800774c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007750: 681b ldr r3, [r3, #0]
|
|
8007752: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007756: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800775a: d118 bne.n 800778e <USB_DevInit+0x156>
|
|
{
|
|
if (i == 0U)
|
|
800775c: 693b ldr r3, [r7, #16]
|
|
800775e: 2b00 cmp r3, #0
|
|
8007760: d10a bne.n 8007778 <USB_DevInit+0x140>
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
|
|
8007762: 693b ldr r3, [r7, #16]
|
|
8007764: 015a lsls r2, r3, #5
|
|
8007766: 68fb ldr r3, [r7, #12]
|
|
8007768: 4413 add r3, r2
|
|
800776a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800776e: 461a mov r2, r3
|
|
8007770: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
8007774: 6013 str r3, [r2, #0]
|
|
8007776: e013 b.n 80077a0 <USB_DevInit+0x168>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
|
|
8007778: 693b ldr r3, [r7, #16]
|
|
800777a: 015a lsls r2, r3, #5
|
|
800777c: 68fb ldr r3, [r7, #12]
|
|
800777e: 4413 add r3, r2
|
|
8007780: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007784: 461a mov r2, r3
|
|
8007786: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
800778a: 6013 str r3, [r2, #0]
|
|
800778c: e008 b.n 80077a0 <USB_DevInit+0x168>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = 0U;
|
|
800778e: 693b ldr r3, [r7, #16]
|
|
8007790: 015a lsls r2, r3, #5
|
|
8007792: 68fb ldr r3, [r7, #12]
|
|
8007794: 4413 add r3, r2
|
|
8007796: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800779a: 461a mov r2, r3
|
|
800779c: 2300 movs r3, #0
|
|
800779e: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_INEP(i)->DIEPTSIZ = 0U;
|
|
80077a0: 693b ldr r3, [r7, #16]
|
|
80077a2: 015a lsls r2, r3, #5
|
|
80077a4: 68fb ldr r3, [r7, #12]
|
|
80077a6: 4413 add r3, r2
|
|
80077a8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80077ac: 461a mov r2, r3
|
|
80077ae: 2300 movs r3, #0
|
|
80077b0: 6113 str r3, [r2, #16]
|
|
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
|
80077b2: 693b ldr r3, [r7, #16]
|
|
80077b4: 015a lsls r2, r3, #5
|
|
80077b6: 68fb ldr r3, [r7, #12]
|
|
80077b8: 4413 add r3, r2
|
|
80077ba: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80077be: 461a mov r2, r3
|
|
80077c0: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
80077c4: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
80077c6: 693b ldr r3, [r7, #16]
|
|
80077c8: 3301 adds r3, #1
|
|
80077ca: 613b str r3, [r7, #16]
|
|
80077cc: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
80077d0: 461a mov r2, r3
|
|
80077d2: 693b ldr r3, [r7, #16]
|
|
80077d4: 4293 cmp r3, r2
|
|
80077d6: d3b5 bcc.n 8007744 <USB_DevInit+0x10c>
|
|
}
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
80077d8: 2300 movs r3, #0
|
|
80077da: 613b str r3, [r7, #16]
|
|
80077dc: e043 b.n 8007866 <USB_DevInit+0x22e>
|
|
{
|
|
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
80077de: 693b ldr r3, [r7, #16]
|
|
80077e0: 015a lsls r2, r3, #5
|
|
80077e2: 68fb ldr r3, [r7, #12]
|
|
80077e4: 4413 add r3, r2
|
|
80077e6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80077ea: 681b ldr r3, [r3, #0]
|
|
80077ec: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80077f0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80077f4: d118 bne.n 8007828 <USB_DevInit+0x1f0>
|
|
{
|
|
if (i == 0U)
|
|
80077f6: 693b ldr r3, [r7, #16]
|
|
80077f8: 2b00 cmp r3, #0
|
|
80077fa: d10a bne.n 8007812 <USB_DevInit+0x1da>
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
|
|
80077fc: 693b ldr r3, [r7, #16]
|
|
80077fe: 015a lsls r2, r3, #5
|
|
8007800: 68fb ldr r3, [r7, #12]
|
|
8007802: 4413 add r3, r2
|
|
8007804: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007808: 461a mov r2, r3
|
|
800780a: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
800780e: 6013 str r3, [r2, #0]
|
|
8007810: e013 b.n 800783a <USB_DevInit+0x202>
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
|
|
8007812: 693b ldr r3, [r7, #16]
|
|
8007814: 015a lsls r2, r3, #5
|
|
8007816: 68fb ldr r3, [r7, #12]
|
|
8007818: 4413 add r3, r2
|
|
800781a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800781e: 461a mov r2, r3
|
|
8007820: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
8007824: 6013 str r3, [r2, #0]
|
|
8007826: e008 b.n 800783a <USB_DevInit+0x202>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = 0U;
|
|
8007828: 693b ldr r3, [r7, #16]
|
|
800782a: 015a lsls r2, r3, #5
|
|
800782c: 68fb ldr r3, [r7, #12]
|
|
800782e: 4413 add r3, r2
|
|
8007830: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007834: 461a mov r2, r3
|
|
8007836: 2300 movs r3, #0
|
|
8007838: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_OUTEP(i)->DOEPTSIZ = 0U;
|
|
800783a: 693b ldr r3, [r7, #16]
|
|
800783c: 015a lsls r2, r3, #5
|
|
800783e: 68fb ldr r3, [r7, #12]
|
|
8007840: 4413 add r3, r2
|
|
8007842: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007846: 461a mov r2, r3
|
|
8007848: 2300 movs r3, #0
|
|
800784a: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
|
800784c: 693b ldr r3, [r7, #16]
|
|
800784e: 015a lsls r2, r3, #5
|
|
8007850: 68fb ldr r3, [r7, #12]
|
|
8007852: 4413 add r3, r2
|
|
8007854: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007858: 461a mov r2, r3
|
|
800785a: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
800785e: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8007860: 693b ldr r3, [r7, #16]
|
|
8007862: 3301 adds r3, #1
|
|
8007864: 613b str r3, [r7, #16]
|
|
8007866: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
800786a: 461a mov r2, r3
|
|
800786c: 693b ldr r3, [r7, #16]
|
|
800786e: 4293 cmp r3, r2
|
|
8007870: d3b5 bcc.n 80077de <USB_DevInit+0x1a6>
|
|
}
|
|
|
|
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
|
|
8007872: 68fb ldr r3, [r7, #12]
|
|
8007874: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007878: 691b ldr r3, [r3, #16]
|
|
800787a: 68fa ldr r2, [r7, #12]
|
|
800787c: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8007880: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8007884: 6113 str r3, [r2, #16]
|
|
|
|
/* Disable all interrupts. */
|
|
USBx->GINTMSK = 0U;
|
|
8007886: 687b ldr r3, [r7, #4]
|
|
8007888: 2200 movs r2, #0
|
|
800788a: 619a str r2, [r3, #24]
|
|
|
|
/* Clear any pending interrupts */
|
|
USBx->GINTSTS = 0xBFFFFFFFU;
|
|
800788c: 687b ldr r3, [r7, #4]
|
|
800788e: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000
|
|
8007892: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the common interrupts */
|
|
if (cfg.dma_enable == 0U)
|
|
8007894: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
|
|
8007898: 2b00 cmp r3, #0
|
|
800789a: d105 bne.n 80078a8 <USB_DevInit+0x270>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
|
|
800789c: 687b ldr r3, [r7, #4]
|
|
800789e: 699b ldr r3, [r3, #24]
|
|
80078a0: f043 0210 orr.w r2, r3, #16
|
|
80078a4: 687b ldr r3, [r7, #4]
|
|
80078a6: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
/* Enable interrupts matching to the Device mode ONLY */
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
|
|
80078a8: 687b ldr r3, [r7, #4]
|
|
80078aa: 699a ldr r2, [r3, #24]
|
|
80078ac: 4b10 ldr r3, [pc, #64] @ (80078f0 <USB_DevInit+0x2b8>)
|
|
80078ae: 4313 orrs r3, r2
|
|
80078b0: 687a ldr r2, [r7, #4]
|
|
80078b2: 6193 str r3, [r2, #24]
|
|
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
|
|
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
|
|
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
|
|
|
|
if (cfg.Sof_enable != 0U)
|
|
80078b4: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
80078b8: 2b00 cmp r3, #0
|
|
80078ba: d005 beq.n 80078c8 <USB_DevInit+0x290>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
|
|
80078bc: 687b ldr r3, [r7, #4]
|
|
80078be: 699b ldr r3, [r3, #24]
|
|
80078c0: f043 0208 orr.w r2, r3, #8
|
|
80078c4: 687b ldr r3, [r7, #4]
|
|
80078c6: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (cfg.vbus_sensing_enable == 1U)
|
|
80078c8: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
80078cc: 2b01 cmp r3, #1
|
|
80078ce: d107 bne.n 80078e0 <USB_DevInit+0x2a8>
|
|
{
|
|
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
|
|
80078d0: 687b ldr r3, [r7, #4]
|
|
80078d2: 699b ldr r3, [r3, #24]
|
|
80078d4: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80078d8: f043 0304 orr.w r3, r3, #4
|
|
80078dc: 687a ldr r2, [r7, #4]
|
|
80078de: 6193 str r3, [r2, #24]
|
|
}
|
|
|
|
return ret;
|
|
80078e0: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80078e2: 4618 mov r0, r3
|
|
80078e4: 3718 adds r7, #24
|
|
80078e6: 46bd mov sp, r7
|
|
80078e8: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
80078ec: b004 add sp, #16
|
|
80078ee: 4770 bx lr
|
|
80078f0: 803c3800 .word 0x803c3800
|
|
|
|
080078f4 <USB_FlushTxFifo>:
|
|
* This parameter can be a value from 1 to 15
|
|
15 means Flush all Tx FIFOs
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
|
|
{
|
|
80078f4: b480 push {r7}
|
|
80078f6: b085 sub sp, #20
|
|
80078f8: af00 add r7, sp, #0
|
|
80078fa: 6078 str r0, [r7, #4]
|
|
80078fc: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
80078fe: 2300 movs r3, #0
|
|
8007900: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
8007902: 68fb ldr r3, [r7, #12]
|
|
8007904: 3301 adds r3, #1
|
|
8007906: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8007908: 68fb ldr r3, [r7, #12]
|
|
800790a: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800790e: d901 bls.n 8007914 <USB_FlushTxFifo+0x20>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007910: 2303 movs r3, #3
|
|
8007912: e01b b.n 800794c <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
8007914: 687b ldr r3, [r7, #4]
|
|
8007916: 691b ldr r3, [r3, #16]
|
|
8007918: 2b00 cmp r3, #0
|
|
800791a: daf2 bge.n 8007902 <USB_FlushTxFifo+0xe>
|
|
|
|
/* Flush TX Fifo */
|
|
count = 0U;
|
|
800791c: 2300 movs r3, #0
|
|
800791e: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
|
|
8007920: 683b ldr r3, [r7, #0]
|
|
8007922: 019b lsls r3, r3, #6
|
|
8007924: f043 0220 orr.w r2, r3, #32
|
|
8007928: 687b ldr r3, [r7, #4]
|
|
800792a: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
800792c: 68fb ldr r3, [r7, #12]
|
|
800792e: 3301 adds r3, #1
|
|
8007930: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8007932: 68fb ldr r3, [r7, #12]
|
|
8007934: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8007938: d901 bls.n 800793e <USB_FlushTxFifo+0x4a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800793a: 2303 movs r3, #3
|
|
800793c: e006 b.n 800794c <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
|
|
800793e: 687b ldr r3, [r7, #4]
|
|
8007940: 691b ldr r3, [r3, #16]
|
|
8007942: f003 0320 and.w r3, r3, #32
|
|
8007946: 2b20 cmp r3, #32
|
|
8007948: d0f0 beq.n 800792c <USB_FlushTxFifo+0x38>
|
|
|
|
return HAL_OK;
|
|
800794a: 2300 movs r3, #0
|
|
}
|
|
800794c: 4618 mov r0, r3
|
|
800794e: 3714 adds r7, #20
|
|
8007950: 46bd mov sp, r7
|
|
8007952: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007956: 4770 bx lr
|
|
|
|
08007958 <USB_FlushRxFifo>:
|
|
* @brief USB_FlushRxFifo Flush Rx FIFO
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8007958: b480 push {r7}
|
|
800795a: b085 sub sp, #20
|
|
800795c: af00 add r7, sp, #0
|
|
800795e: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
8007960: 2300 movs r3, #0
|
|
8007962: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
8007964: 68fb ldr r3, [r7, #12]
|
|
8007966: 3301 adds r3, #1
|
|
8007968: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800796a: 68fb ldr r3, [r7, #12]
|
|
800796c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8007970: d901 bls.n 8007976 <USB_FlushRxFifo+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007972: 2303 movs r3, #3
|
|
8007974: e018 b.n 80079a8 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
8007976: 687b ldr r3, [r7, #4]
|
|
8007978: 691b ldr r3, [r3, #16]
|
|
800797a: 2b00 cmp r3, #0
|
|
800797c: daf2 bge.n 8007964 <USB_FlushRxFifo+0xc>
|
|
|
|
/* Flush RX Fifo */
|
|
count = 0U;
|
|
800797e: 2300 movs r3, #0
|
|
8007980: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
|
|
8007982: 687b ldr r3, [r7, #4]
|
|
8007984: 2210 movs r2, #16
|
|
8007986: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8007988: 68fb ldr r3, [r7, #12]
|
|
800798a: 3301 adds r3, #1
|
|
800798c: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800798e: 68fb ldr r3, [r7, #12]
|
|
8007990: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8007994: d901 bls.n 800799a <USB_FlushRxFifo+0x42>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007996: 2303 movs r3, #3
|
|
8007998: e006 b.n 80079a8 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
|
|
800799a: 687b ldr r3, [r7, #4]
|
|
800799c: 691b ldr r3, [r3, #16]
|
|
800799e: f003 0310 and.w r3, r3, #16
|
|
80079a2: 2b10 cmp r3, #16
|
|
80079a4: d0f0 beq.n 8007988 <USB_FlushRxFifo+0x30>
|
|
|
|
return HAL_OK;
|
|
80079a6: 2300 movs r3, #0
|
|
}
|
|
80079a8: 4618 mov r0, r3
|
|
80079aa: 3714 adds r7, #20
|
|
80079ac: 46bd mov sp, r7
|
|
80079ae: f85d 7b04 ldr.w r7, [sp], #4
|
|
80079b2: 4770 bx lr
|
|
|
|
080079b4 <USB_SetDevSpeed>:
|
|
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
|
|
* @arg USB_OTG_SPEED_FULL: Full speed mode
|
|
* @retval Hal status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
|
|
{
|
|
80079b4: b480 push {r7}
|
|
80079b6: b085 sub sp, #20
|
|
80079b8: af00 add r7, sp, #0
|
|
80079ba: 6078 str r0, [r7, #4]
|
|
80079bc: 460b mov r3, r1
|
|
80079be: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80079c0: 687b ldr r3, [r7, #4]
|
|
80079c2: 60fb str r3, [r7, #12]
|
|
|
|
USBx_DEVICE->DCFG |= speed;
|
|
80079c4: 68fb ldr r3, [r7, #12]
|
|
80079c6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80079ca: 681a ldr r2, [r3, #0]
|
|
80079cc: 78fb ldrb r3, [r7, #3]
|
|
80079ce: 68f9 ldr r1, [r7, #12]
|
|
80079d0: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80079d4: 4313 orrs r3, r2
|
|
80079d6: 600b str r3, [r1, #0]
|
|
return HAL_OK;
|
|
80079d8: 2300 movs r3, #0
|
|
}
|
|
80079da: 4618 mov r0, r3
|
|
80079dc: 3714 adds r7, #20
|
|
80079de: 46bd mov sp, r7
|
|
80079e0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80079e4: 4770 bx lr
|
|
|
|
080079e6 <USB_GetDevSpeed>:
|
|
* This parameter can be one of these values:
|
|
* @arg USBD_HS_SPEED: High speed mode
|
|
* @arg USBD_FS_SPEED: Full speed mode
|
|
*/
|
|
uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80079e6: b480 push {r7}
|
|
80079e8: b087 sub sp, #28
|
|
80079ea: af00 add r7, sp, #0
|
|
80079ec: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80079ee: 687b ldr r3, [r7, #4]
|
|
80079f0: 613b str r3, [r7, #16]
|
|
uint8_t speed;
|
|
uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
|
|
80079f2: 693b ldr r3, [r7, #16]
|
|
80079f4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80079f8: 689b ldr r3, [r3, #8]
|
|
80079fa: f003 0306 and.w r3, r3, #6
|
|
80079fe: 60fb str r3, [r7, #12]
|
|
|
|
if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
|
|
8007a00: 68fb ldr r3, [r7, #12]
|
|
8007a02: 2b00 cmp r3, #0
|
|
8007a04: d102 bne.n 8007a0c <USB_GetDevSpeed+0x26>
|
|
{
|
|
speed = USBD_HS_SPEED;
|
|
8007a06: 2300 movs r3, #0
|
|
8007a08: 75fb strb r3, [r7, #23]
|
|
8007a0a: e00a b.n 8007a22 <USB_GetDevSpeed+0x3c>
|
|
}
|
|
else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
|
|
8007a0c: 68fb ldr r3, [r7, #12]
|
|
8007a0e: 2b02 cmp r3, #2
|
|
8007a10: d002 beq.n 8007a18 <USB_GetDevSpeed+0x32>
|
|
8007a12: 68fb ldr r3, [r7, #12]
|
|
8007a14: 2b06 cmp r3, #6
|
|
8007a16: d102 bne.n 8007a1e <USB_GetDevSpeed+0x38>
|
|
(DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
|
|
{
|
|
speed = USBD_FS_SPEED;
|
|
8007a18: 2302 movs r3, #2
|
|
8007a1a: 75fb strb r3, [r7, #23]
|
|
8007a1c: e001 b.n 8007a22 <USB_GetDevSpeed+0x3c>
|
|
}
|
|
else
|
|
{
|
|
speed = 0xFU;
|
|
8007a1e: 230f movs r3, #15
|
|
8007a20: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return speed;
|
|
8007a22: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8007a24: 4618 mov r0, r3
|
|
8007a26: 371c adds r7, #28
|
|
8007a28: 46bd mov sp, r7
|
|
8007a2a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007a2e: 4770 bx lr
|
|
|
|
08007a30 <USB_ActivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8007a30: b480 push {r7}
|
|
8007a32: b085 sub sp, #20
|
|
8007a34: af00 add r7, sp, #0
|
|
8007a36: 6078 str r0, [r7, #4]
|
|
8007a38: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007a3a: 687b ldr r3, [r7, #4]
|
|
8007a3c: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8007a3e: 683b ldr r3, [r7, #0]
|
|
8007a40: 781b ldrb r3, [r3, #0]
|
|
8007a42: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
8007a44: 683b ldr r3, [r7, #0]
|
|
8007a46: 785b ldrb r3, [r3, #1]
|
|
8007a48: 2b01 cmp r3, #1
|
|
8007a4a: d13a bne.n 8007ac2 <USB_ActivateEndpoint+0x92>
|
|
{
|
|
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
|
|
8007a4c: 68fb ldr r3, [r7, #12]
|
|
8007a4e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007a52: 69da ldr r2, [r3, #28]
|
|
8007a54: 683b ldr r3, [r7, #0]
|
|
8007a56: 781b ldrb r3, [r3, #0]
|
|
8007a58: f003 030f and.w r3, r3, #15
|
|
8007a5c: 2101 movs r1, #1
|
|
8007a5e: fa01 f303 lsl.w r3, r1, r3
|
|
8007a62: b29b uxth r3, r3
|
|
8007a64: 68f9 ldr r1, [r7, #12]
|
|
8007a66: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8007a6a: 4313 orrs r3, r2
|
|
8007a6c: 61cb str r3, [r1, #28]
|
|
|
|
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
|
|
8007a6e: 68bb ldr r3, [r7, #8]
|
|
8007a70: 015a lsls r2, r3, #5
|
|
8007a72: 68fb ldr r3, [r7, #12]
|
|
8007a74: 4413 add r3, r2
|
|
8007a76: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007a7a: 681b ldr r3, [r3, #0]
|
|
8007a7c: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8007a80: 2b00 cmp r3, #0
|
|
8007a82: d155 bne.n 8007b30 <USB_ActivateEndpoint+0x100>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
8007a84: 68bb ldr r3, [r7, #8]
|
|
8007a86: 015a lsls r2, r3, #5
|
|
8007a88: 68fb ldr r3, [r7, #12]
|
|
8007a8a: 4413 add r3, r2
|
|
8007a8c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007a90: 681a ldr r2, [r3, #0]
|
|
8007a92: 683b ldr r3, [r7, #0]
|
|
8007a94: 689b ldr r3, [r3, #8]
|
|
8007a96: f3c3 010a ubfx r1, r3, #0, #11
|
|
((uint32_t)ep->type << 18) | (epnum << 22) |
|
|
8007a9a: 683b ldr r3, [r7, #0]
|
|
8007a9c: 791b ldrb r3, [r3, #4]
|
|
8007a9e: 049b lsls r3, r3, #18
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
8007aa0: 4319 orrs r1, r3
|
|
((uint32_t)ep->type << 18) | (epnum << 22) |
|
|
8007aa2: 68bb ldr r3, [r7, #8]
|
|
8007aa4: 059b lsls r3, r3, #22
|
|
8007aa6: 430b orrs r3, r1
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
8007aa8: 4313 orrs r3, r2
|
|
8007aaa: 68ba ldr r2, [r7, #8]
|
|
8007aac: 0151 lsls r1, r2, #5
|
|
8007aae: 68fa ldr r2, [r7, #12]
|
|
8007ab0: 440a add r2, r1
|
|
8007ab2: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007ab6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8007aba: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8007abe: 6013 str r3, [r2, #0]
|
|
8007ac0: e036 b.n 8007b30 <USB_ActivateEndpoint+0x100>
|
|
USB_OTG_DIEPCTL_USBAEP;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
|
|
8007ac2: 68fb ldr r3, [r7, #12]
|
|
8007ac4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007ac8: 69da ldr r2, [r3, #28]
|
|
8007aca: 683b ldr r3, [r7, #0]
|
|
8007acc: 781b ldrb r3, [r3, #0]
|
|
8007ace: f003 030f and.w r3, r3, #15
|
|
8007ad2: 2101 movs r1, #1
|
|
8007ad4: fa01 f303 lsl.w r3, r1, r3
|
|
8007ad8: 041b lsls r3, r3, #16
|
|
8007ada: 68f9 ldr r1, [r7, #12]
|
|
8007adc: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8007ae0: 4313 orrs r3, r2
|
|
8007ae2: 61cb str r3, [r1, #28]
|
|
|
|
if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
|
|
8007ae4: 68bb ldr r3, [r7, #8]
|
|
8007ae6: 015a lsls r2, r3, #5
|
|
8007ae8: 68fb ldr r3, [r7, #12]
|
|
8007aea: 4413 add r3, r2
|
|
8007aec: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007af0: 681b ldr r3, [r3, #0]
|
|
8007af2: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8007af6: 2b00 cmp r3, #0
|
|
8007af8: d11a bne.n 8007b30 <USB_ActivateEndpoint+0x100>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
|
|
8007afa: 68bb ldr r3, [r7, #8]
|
|
8007afc: 015a lsls r2, r3, #5
|
|
8007afe: 68fb ldr r3, [r7, #12]
|
|
8007b00: 4413 add r3, r2
|
|
8007b02: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007b06: 681a ldr r2, [r3, #0]
|
|
8007b08: 683b ldr r3, [r7, #0]
|
|
8007b0a: 689b ldr r3, [r3, #8]
|
|
8007b0c: f3c3 010a ubfx r1, r3, #0, #11
|
|
((uint32_t)ep->type << 18) |
|
|
8007b10: 683b ldr r3, [r7, #0]
|
|
8007b12: 791b ldrb r3, [r3, #4]
|
|
8007b14: 049b lsls r3, r3, #18
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
|
|
8007b16: 430b orrs r3, r1
|
|
8007b18: 4313 orrs r3, r2
|
|
8007b1a: 68ba ldr r2, [r7, #8]
|
|
8007b1c: 0151 lsls r1, r2, #5
|
|
8007b1e: 68fa ldr r2, [r7, #12]
|
|
8007b20: 440a add r2, r1
|
|
8007b22: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007b26: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8007b2a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8007b2e: 6013 str r3, [r2, #0]
|
|
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DOEPCTL_USBAEP;
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8007b30: 2300 movs r3, #0
|
|
}
|
|
8007b32: 4618 mov r0, r3
|
|
8007b34: 3714 adds r7, #20
|
|
8007b36: 46bd mov sp, r7
|
|
8007b38: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007b3c: 4770 bx lr
|
|
...
|
|
|
|
08007b40 <USB_DeactivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8007b40: b480 push {r7}
|
|
8007b42: b085 sub sp, #20
|
|
8007b44: af00 add r7, sp, #0
|
|
8007b46: 6078 str r0, [r7, #4]
|
|
8007b48: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007b4a: 687b ldr r3, [r7, #4]
|
|
8007b4c: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8007b4e: 683b ldr r3, [r7, #0]
|
|
8007b50: 781b ldrb r3, [r3, #0]
|
|
8007b52: 60bb str r3, [r7, #8]
|
|
|
|
/* Read DEPCTLn register */
|
|
if (ep->is_in == 1U)
|
|
8007b54: 683b ldr r3, [r7, #0]
|
|
8007b56: 785b ldrb r3, [r3, #1]
|
|
8007b58: 2b01 cmp r3, #1
|
|
8007b5a: d161 bne.n 8007c20 <USB_DeactivateEndpoint+0xe0>
|
|
{
|
|
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
8007b5c: 68bb ldr r3, [r7, #8]
|
|
8007b5e: 015a lsls r2, r3, #5
|
|
8007b60: 68fb ldr r3, [r7, #12]
|
|
8007b62: 4413 add r3, r2
|
|
8007b64: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007b68: 681b ldr r3, [r3, #0]
|
|
8007b6a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007b6e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8007b72: d11f bne.n 8007bb4 <USB_DeactivateEndpoint+0x74>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
|
|
8007b74: 68bb ldr r3, [r7, #8]
|
|
8007b76: 015a lsls r2, r3, #5
|
|
8007b78: 68fb ldr r3, [r7, #12]
|
|
8007b7a: 4413 add r3, r2
|
|
8007b7c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007b80: 681b ldr r3, [r3, #0]
|
|
8007b82: 68ba ldr r2, [r7, #8]
|
|
8007b84: 0151 lsls r1, r2, #5
|
|
8007b86: 68fa ldr r2, [r7, #12]
|
|
8007b88: 440a add r2, r1
|
|
8007b8a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007b8e: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8007b92: 6013 str r3, [r2, #0]
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
|
|
8007b94: 68bb ldr r3, [r7, #8]
|
|
8007b96: 015a lsls r2, r3, #5
|
|
8007b98: 68fb ldr r3, [r7, #12]
|
|
8007b9a: 4413 add r3, r2
|
|
8007b9c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007ba0: 681b ldr r3, [r3, #0]
|
|
8007ba2: 68ba ldr r2, [r7, #8]
|
|
8007ba4: 0151 lsls r1, r2, #5
|
|
8007ba6: 68fa ldr r2, [r7, #12]
|
|
8007ba8: 440a add r2, r1
|
|
8007baa: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007bae: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8007bb2: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
|
|
8007bb4: 68fb ldr r3, [r7, #12]
|
|
8007bb6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007bba: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8007bbc: 683b ldr r3, [r7, #0]
|
|
8007bbe: 781b ldrb r3, [r3, #0]
|
|
8007bc0: f003 030f and.w r3, r3, #15
|
|
8007bc4: 2101 movs r1, #1
|
|
8007bc6: fa01 f303 lsl.w r3, r1, r3
|
|
8007bca: b29b uxth r3, r3
|
|
8007bcc: 43db mvns r3, r3
|
|
8007bce: 68f9 ldr r1, [r7, #12]
|
|
8007bd0: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8007bd4: 4013 ands r3, r2
|
|
8007bd6: 63cb str r3, [r1, #60] @ 0x3c
|
|
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
|
|
8007bd8: 68fb ldr r3, [r7, #12]
|
|
8007bda: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007bde: 69da ldr r2, [r3, #28]
|
|
8007be0: 683b ldr r3, [r7, #0]
|
|
8007be2: 781b ldrb r3, [r3, #0]
|
|
8007be4: f003 030f and.w r3, r3, #15
|
|
8007be8: 2101 movs r1, #1
|
|
8007bea: fa01 f303 lsl.w r3, r1, r3
|
|
8007bee: b29b uxth r3, r3
|
|
8007bf0: 43db mvns r3, r3
|
|
8007bf2: 68f9 ldr r1, [r7, #12]
|
|
8007bf4: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8007bf8: 4013 ands r3, r2
|
|
8007bfa: 61cb str r3, [r1, #28]
|
|
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
|
|
8007bfc: 68bb ldr r3, [r7, #8]
|
|
8007bfe: 015a lsls r2, r3, #5
|
|
8007c00: 68fb ldr r3, [r7, #12]
|
|
8007c02: 4413 add r3, r2
|
|
8007c04: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007c08: 681a ldr r2, [r3, #0]
|
|
8007c0a: 68bb ldr r3, [r7, #8]
|
|
8007c0c: 0159 lsls r1, r3, #5
|
|
8007c0e: 68fb ldr r3, [r7, #12]
|
|
8007c10: 440b add r3, r1
|
|
8007c12: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007c16: 4619 mov r1, r3
|
|
8007c18: 4b35 ldr r3, [pc, #212] @ (8007cf0 <USB_DeactivateEndpoint+0x1b0>)
|
|
8007c1a: 4013 ands r3, r2
|
|
8007c1c: 600b str r3, [r1, #0]
|
|
8007c1e: e060 b.n 8007ce2 <USB_DeactivateEndpoint+0x1a2>
|
|
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DIEPCTL_EPTYP);
|
|
}
|
|
else
|
|
{
|
|
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
8007c20: 68bb ldr r3, [r7, #8]
|
|
8007c22: 015a lsls r2, r3, #5
|
|
8007c24: 68fb ldr r3, [r7, #12]
|
|
8007c26: 4413 add r3, r2
|
|
8007c28: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007c2c: 681b ldr r3, [r3, #0]
|
|
8007c2e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007c32: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8007c36: d11f bne.n 8007c78 <USB_DeactivateEndpoint+0x138>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
|
8007c38: 68bb ldr r3, [r7, #8]
|
|
8007c3a: 015a lsls r2, r3, #5
|
|
8007c3c: 68fb ldr r3, [r7, #12]
|
|
8007c3e: 4413 add r3, r2
|
|
8007c40: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007c44: 681b ldr r3, [r3, #0]
|
|
8007c46: 68ba ldr r2, [r7, #8]
|
|
8007c48: 0151 lsls r1, r2, #5
|
|
8007c4a: 68fa ldr r2, [r7, #12]
|
|
8007c4c: 440a add r2, r1
|
|
8007c4e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007c52: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8007c56: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
|
|
8007c58: 68bb ldr r3, [r7, #8]
|
|
8007c5a: 015a lsls r2, r3, #5
|
|
8007c5c: 68fb ldr r3, [r7, #12]
|
|
8007c5e: 4413 add r3, r2
|
|
8007c60: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007c64: 681b ldr r3, [r3, #0]
|
|
8007c66: 68ba ldr r2, [r7, #8]
|
|
8007c68: 0151 lsls r1, r2, #5
|
|
8007c6a: 68fa ldr r2, [r7, #12]
|
|
8007c6c: 440a add r2, r1
|
|
8007c6e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007c72: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8007c76: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
|
|
8007c78: 68fb ldr r3, [r7, #12]
|
|
8007c7a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007c7e: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8007c80: 683b ldr r3, [r7, #0]
|
|
8007c82: 781b ldrb r3, [r3, #0]
|
|
8007c84: f003 030f and.w r3, r3, #15
|
|
8007c88: 2101 movs r1, #1
|
|
8007c8a: fa01 f303 lsl.w r3, r1, r3
|
|
8007c8e: 041b lsls r3, r3, #16
|
|
8007c90: 43db mvns r3, r3
|
|
8007c92: 68f9 ldr r1, [r7, #12]
|
|
8007c94: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8007c98: 4013 ands r3, r2
|
|
8007c9a: 63cb str r3, [r1, #60] @ 0x3c
|
|
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
|
|
8007c9c: 68fb ldr r3, [r7, #12]
|
|
8007c9e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007ca2: 69da ldr r2, [r3, #28]
|
|
8007ca4: 683b ldr r3, [r7, #0]
|
|
8007ca6: 781b ldrb r3, [r3, #0]
|
|
8007ca8: f003 030f and.w r3, r3, #15
|
|
8007cac: 2101 movs r1, #1
|
|
8007cae: fa01 f303 lsl.w r3, r1, r3
|
|
8007cb2: 041b lsls r3, r3, #16
|
|
8007cb4: 43db mvns r3, r3
|
|
8007cb6: 68f9 ldr r1, [r7, #12]
|
|
8007cb8: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8007cbc: 4013 ands r3, r2
|
|
8007cbe: 61cb str r3, [r1, #28]
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
|
|
8007cc0: 68bb ldr r3, [r7, #8]
|
|
8007cc2: 015a lsls r2, r3, #5
|
|
8007cc4: 68fb ldr r3, [r7, #12]
|
|
8007cc6: 4413 add r3, r2
|
|
8007cc8: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007ccc: 681a ldr r2, [r3, #0]
|
|
8007cce: 68bb ldr r3, [r7, #8]
|
|
8007cd0: 0159 lsls r1, r3, #5
|
|
8007cd2: 68fb ldr r3, [r7, #12]
|
|
8007cd4: 440b add r3, r1
|
|
8007cd6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007cda: 4619 mov r1, r3
|
|
8007cdc: 4b05 ldr r3, [pc, #20] @ (8007cf4 <USB_DeactivateEndpoint+0x1b4>)
|
|
8007cde: 4013 ands r3, r2
|
|
8007ce0: 600b str r3, [r1, #0]
|
|
USB_OTG_DOEPCTL_MPSIZ |
|
|
USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DOEPCTL_EPTYP);
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007ce2: 2300 movs r3, #0
|
|
}
|
|
8007ce4: 4618 mov r0, r3
|
|
8007ce6: 3714 adds r7, #20
|
|
8007ce8: 46bd mov sp, r7
|
|
8007cea: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007cee: 4770 bx lr
|
|
8007cf0: ec337800 .word 0xec337800
|
|
8007cf4: eff37800 .word 0xeff37800
|
|
|
|
08007cf8 <USB_EPStartXfer>:
|
|
* 0 : DMA feature not used
|
|
* 1 : DMA feature used
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
|
|
{
|
|
8007cf8: b580 push {r7, lr}
|
|
8007cfa: b08a sub sp, #40 @ 0x28
|
|
8007cfc: af02 add r7, sp, #8
|
|
8007cfe: 60f8 str r0, [r7, #12]
|
|
8007d00: 60b9 str r1, [r7, #8]
|
|
8007d02: 4613 mov r3, r2
|
|
8007d04: 71fb strb r3, [r7, #7]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007d06: 68fb ldr r3, [r7, #12]
|
|
8007d08: 61fb str r3, [r7, #28]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8007d0a: 68bb ldr r3, [r7, #8]
|
|
8007d0c: 781b ldrb r3, [r3, #0]
|
|
8007d0e: 61bb str r3, [r7, #24]
|
|
uint16_t pktcnt;
|
|
|
|
/* IN endpoint */
|
|
if (ep->is_in == 1U)
|
|
8007d10: 68bb ldr r3, [r7, #8]
|
|
8007d12: 785b ldrb r3, [r3, #1]
|
|
8007d14: 2b01 cmp r3, #1
|
|
8007d16: f040 817f bne.w 8008018 <USB_EPStartXfer+0x320>
|
|
{
|
|
/* Zero Length Packet? */
|
|
if (ep->xfer_len == 0U)
|
|
8007d1a: 68bb ldr r3, [r7, #8]
|
|
8007d1c: 691b ldr r3, [r3, #16]
|
|
8007d1e: 2b00 cmp r3, #0
|
|
8007d20: d132 bne.n 8007d88 <USB_EPStartXfer+0x90>
|
|
{
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
|
8007d22: 69bb ldr r3, [r7, #24]
|
|
8007d24: 015a lsls r2, r3, #5
|
|
8007d26: 69fb ldr r3, [r7, #28]
|
|
8007d28: 4413 add r3, r2
|
|
8007d2a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007d2e: 691b ldr r3, [r3, #16]
|
|
8007d30: 69ba ldr r2, [r7, #24]
|
|
8007d32: 0151 lsls r1, r2, #5
|
|
8007d34: 69fa ldr r2, [r7, #28]
|
|
8007d36: 440a add r2, r1
|
|
8007d38: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007d3c: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
8007d40: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
8007d44: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
|
|
8007d46: 69bb ldr r3, [r7, #24]
|
|
8007d48: 015a lsls r2, r3, #5
|
|
8007d4a: 69fb ldr r3, [r7, #28]
|
|
8007d4c: 4413 add r3, r2
|
|
8007d4e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007d52: 691b ldr r3, [r3, #16]
|
|
8007d54: 69ba ldr r2, [r7, #24]
|
|
8007d56: 0151 lsls r1, r2, #5
|
|
8007d58: 69fa ldr r2, [r7, #28]
|
|
8007d5a: 440a add r2, r1
|
|
8007d5c: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007d60: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8007d64: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
|
8007d66: 69bb ldr r3, [r7, #24]
|
|
8007d68: 015a lsls r2, r3, #5
|
|
8007d6a: 69fb ldr r3, [r7, #28]
|
|
8007d6c: 4413 add r3, r2
|
|
8007d6e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007d72: 691b ldr r3, [r3, #16]
|
|
8007d74: 69ba ldr r2, [r7, #24]
|
|
8007d76: 0151 lsls r1, r2, #5
|
|
8007d78: 69fa ldr r2, [r7, #28]
|
|
8007d7a: 440a add r2, r1
|
|
8007d7c: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007d80: 0cdb lsrs r3, r3, #19
|
|
8007d82: 04db lsls r3, r3, #19
|
|
8007d84: 6113 str r3, [r2, #16]
|
|
8007d86: e097 b.n 8007eb8 <USB_EPStartXfer+0x1c0>
|
|
/* Program the transfer size and packet count
|
|
* as follows: xfersize = N * maxpacket +
|
|
* short_packet pktcnt = N + (short_packet
|
|
* exist ? 1 : 0)
|
|
*/
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
|
8007d88: 69bb ldr r3, [r7, #24]
|
|
8007d8a: 015a lsls r2, r3, #5
|
|
8007d8c: 69fb ldr r3, [r7, #28]
|
|
8007d8e: 4413 add r3, r2
|
|
8007d90: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007d94: 691b ldr r3, [r3, #16]
|
|
8007d96: 69ba ldr r2, [r7, #24]
|
|
8007d98: 0151 lsls r1, r2, #5
|
|
8007d9a: 69fa ldr r2, [r7, #28]
|
|
8007d9c: 440a add r2, r1
|
|
8007d9e: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007da2: 0cdb lsrs r3, r3, #19
|
|
8007da4: 04db lsls r3, r3, #19
|
|
8007da6: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
|
8007da8: 69bb ldr r3, [r7, #24]
|
|
8007daa: 015a lsls r2, r3, #5
|
|
8007dac: 69fb ldr r3, [r7, #28]
|
|
8007dae: 4413 add r3, r2
|
|
8007db0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007db4: 691b ldr r3, [r3, #16]
|
|
8007db6: 69ba ldr r2, [r7, #24]
|
|
8007db8: 0151 lsls r1, r2, #5
|
|
8007dba: 69fa ldr r2, [r7, #28]
|
|
8007dbc: 440a add r2, r1
|
|
8007dbe: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007dc2: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
8007dc6: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
8007dca: 6113 str r3, [r2, #16]
|
|
|
|
if (epnum == 0U)
|
|
8007dcc: 69bb ldr r3, [r7, #24]
|
|
8007dce: 2b00 cmp r3, #0
|
|
8007dd0: d11a bne.n 8007e08 <USB_EPStartXfer+0x110>
|
|
{
|
|
if (ep->xfer_len > ep->maxpacket)
|
|
8007dd2: 68bb ldr r3, [r7, #8]
|
|
8007dd4: 691a ldr r2, [r3, #16]
|
|
8007dd6: 68bb ldr r3, [r7, #8]
|
|
8007dd8: 689b ldr r3, [r3, #8]
|
|
8007dda: 429a cmp r2, r3
|
|
8007ddc: d903 bls.n 8007de6 <USB_EPStartXfer+0xee>
|
|
{
|
|
ep->xfer_len = ep->maxpacket;
|
|
8007dde: 68bb ldr r3, [r7, #8]
|
|
8007de0: 689a ldr r2, [r3, #8]
|
|
8007de2: 68bb ldr r3, [r7, #8]
|
|
8007de4: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
|
|
8007de6: 69bb ldr r3, [r7, #24]
|
|
8007de8: 015a lsls r2, r3, #5
|
|
8007dea: 69fb ldr r3, [r7, #28]
|
|
8007dec: 4413 add r3, r2
|
|
8007dee: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007df2: 691b ldr r3, [r3, #16]
|
|
8007df4: 69ba ldr r2, [r7, #24]
|
|
8007df6: 0151 lsls r1, r2, #5
|
|
8007df8: 69fa ldr r2, [r7, #28]
|
|
8007dfa: 440a add r2, r1
|
|
8007dfc: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007e00: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8007e04: 6113 str r3, [r2, #16]
|
|
8007e06: e044 b.n 8007e92 <USB_EPStartXfer+0x19a>
|
|
}
|
|
else
|
|
{
|
|
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
|
|
8007e08: 68bb ldr r3, [r7, #8]
|
|
8007e0a: 691a ldr r2, [r3, #16]
|
|
8007e0c: 68bb ldr r3, [r7, #8]
|
|
8007e0e: 689b ldr r3, [r3, #8]
|
|
8007e10: 4413 add r3, r2
|
|
8007e12: 1e5a subs r2, r3, #1
|
|
8007e14: 68bb ldr r3, [r7, #8]
|
|
8007e16: 689b ldr r3, [r3, #8]
|
|
8007e18: fbb2 f3f3 udiv r3, r2, r3
|
|
8007e1c: 82fb strh r3, [r7, #22]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19));
|
|
8007e1e: 69bb ldr r3, [r7, #24]
|
|
8007e20: 015a lsls r2, r3, #5
|
|
8007e22: 69fb ldr r3, [r7, #28]
|
|
8007e24: 4413 add r3, r2
|
|
8007e26: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007e2a: 691a ldr r2, [r3, #16]
|
|
8007e2c: 8afb ldrh r3, [r7, #22]
|
|
8007e2e: 04d9 lsls r1, r3, #19
|
|
8007e30: 4ba4 ldr r3, [pc, #656] @ (80080c4 <USB_EPStartXfer+0x3cc>)
|
|
8007e32: 400b ands r3, r1
|
|
8007e34: 69b9 ldr r1, [r7, #24]
|
|
8007e36: 0148 lsls r0, r1, #5
|
|
8007e38: 69f9 ldr r1, [r7, #28]
|
|
8007e3a: 4401 add r1, r0
|
|
8007e3c: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
8007e40: 4313 orrs r3, r2
|
|
8007e42: 610b str r3, [r1, #16]
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
8007e44: 68bb ldr r3, [r7, #8]
|
|
8007e46: 791b ldrb r3, [r3, #4]
|
|
8007e48: 2b01 cmp r3, #1
|
|
8007e4a: d122 bne.n 8007e92 <USB_EPStartXfer+0x19a>
|
|
{
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
|
|
8007e4c: 69bb ldr r3, [r7, #24]
|
|
8007e4e: 015a lsls r2, r3, #5
|
|
8007e50: 69fb ldr r3, [r7, #28]
|
|
8007e52: 4413 add r3, r2
|
|
8007e54: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007e58: 691b ldr r3, [r3, #16]
|
|
8007e5a: 69ba ldr r2, [r7, #24]
|
|
8007e5c: 0151 lsls r1, r2, #5
|
|
8007e5e: 69fa ldr r2, [r7, #28]
|
|
8007e60: 440a add r2, r1
|
|
8007e62: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007e66: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000
|
|
8007e6a: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29));
|
|
8007e6c: 69bb ldr r3, [r7, #24]
|
|
8007e6e: 015a lsls r2, r3, #5
|
|
8007e70: 69fb ldr r3, [r7, #28]
|
|
8007e72: 4413 add r3, r2
|
|
8007e74: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007e78: 691a ldr r2, [r3, #16]
|
|
8007e7a: 8afb ldrh r3, [r7, #22]
|
|
8007e7c: 075b lsls r3, r3, #29
|
|
8007e7e: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000
|
|
8007e82: 69b9 ldr r1, [r7, #24]
|
|
8007e84: 0148 lsls r0, r1, #5
|
|
8007e86: 69f9 ldr r1, [r7, #28]
|
|
8007e88: 4401 add r1, r0
|
|
8007e8a: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
8007e8e: 4313 orrs r3, r2
|
|
8007e90: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
|
|
8007e92: 69bb ldr r3, [r7, #24]
|
|
8007e94: 015a lsls r2, r3, #5
|
|
8007e96: 69fb ldr r3, [r7, #28]
|
|
8007e98: 4413 add r3, r2
|
|
8007e9a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007e9e: 691a ldr r2, [r3, #16]
|
|
8007ea0: 68bb ldr r3, [r7, #8]
|
|
8007ea2: 691b ldr r3, [r3, #16]
|
|
8007ea4: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8007ea8: 69b9 ldr r1, [r7, #24]
|
|
8007eaa: 0148 lsls r0, r1, #5
|
|
8007eac: 69f9 ldr r1, [r7, #28]
|
|
8007eae: 4401 add r1, r0
|
|
8007eb0: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
8007eb4: 4313 orrs r3, r2
|
|
8007eb6: 610b str r3, [r1, #16]
|
|
}
|
|
|
|
if (dma == 1U)
|
|
8007eb8: 79fb ldrb r3, [r7, #7]
|
|
8007eba: 2b01 cmp r3, #1
|
|
8007ebc: d14b bne.n 8007f56 <USB_EPStartXfer+0x25e>
|
|
{
|
|
if ((uint32_t)ep->dma_addr != 0U)
|
|
8007ebe: 68bb ldr r3, [r7, #8]
|
|
8007ec0: 69db ldr r3, [r3, #28]
|
|
8007ec2: 2b00 cmp r3, #0
|
|
8007ec4: d009 beq.n 8007eda <USB_EPStartXfer+0x1e2>
|
|
{
|
|
USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
|
|
8007ec6: 69bb ldr r3, [r7, #24]
|
|
8007ec8: 015a lsls r2, r3, #5
|
|
8007eca: 69fb ldr r3, [r7, #28]
|
|
8007ecc: 4413 add r3, r2
|
|
8007ece: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007ed2: 461a mov r2, r3
|
|
8007ed4: 68bb ldr r3, [r7, #8]
|
|
8007ed6: 69db ldr r3, [r3, #28]
|
|
8007ed8: 6153 str r3, [r2, #20]
|
|
}
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
8007eda: 68bb ldr r3, [r7, #8]
|
|
8007edc: 791b ldrb r3, [r3, #4]
|
|
8007ede: 2b01 cmp r3, #1
|
|
8007ee0: d128 bne.n 8007f34 <USB_EPStartXfer+0x23c>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
8007ee2: 69fb ldr r3, [r7, #28]
|
|
8007ee4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007ee8: 689b ldr r3, [r3, #8]
|
|
8007eea: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8007eee: 2b00 cmp r3, #0
|
|
8007ef0: d110 bne.n 8007f14 <USB_EPStartXfer+0x21c>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
|
|
8007ef2: 69bb ldr r3, [r7, #24]
|
|
8007ef4: 015a lsls r2, r3, #5
|
|
8007ef6: 69fb ldr r3, [r7, #28]
|
|
8007ef8: 4413 add r3, r2
|
|
8007efa: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007efe: 681b ldr r3, [r3, #0]
|
|
8007f00: 69ba ldr r2, [r7, #24]
|
|
8007f02: 0151 lsls r1, r2, #5
|
|
8007f04: 69fa ldr r2, [r7, #28]
|
|
8007f06: 440a add r2, r1
|
|
8007f08: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007f0c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8007f10: 6013 str r3, [r2, #0]
|
|
8007f12: e00f b.n 8007f34 <USB_EPStartXfer+0x23c>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
|
8007f14: 69bb ldr r3, [r7, #24]
|
|
8007f16: 015a lsls r2, r3, #5
|
|
8007f18: 69fb ldr r3, [r7, #28]
|
|
8007f1a: 4413 add r3, r2
|
|
8007f1c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007f20: 681b ldr r3, [r3, #0]
|
|
8007f22: 69ba ldr r2, [r7, #24]
|
|
8007f24: 0151 lsls r1, r2, #5
|
|
8007f26: 69fa ldr r2, [r7, #28]
|
|
8007f28: 440a add r2, r1
|
|
8007f2a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007f2e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8007f32: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
/* EP enable, IN data in FIFO */
|
|
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
|
8007f34: 69bb ldr r3, [r7, #24]
|
|
8007f36: 015a lsls r2, r3, #5
|
|
8007f38: 69fb ldr r3, [r7, #28]
|
|
8007f3a: 4413 add r3, r2
|
|
8007f3c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007f40: 681b ldr r3, [r3, #0]
|
|
8007f42: 69ba ldr r2, [r7, #24]
|
|
8007f44: 0151 lsls r1, r2, #5
|
|
8007f46: 69fa ldr r2, [r7, #28]
|
|
8007f48: 440a add r2, r1
|
|
8007f4a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007f4e: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
8007f52: 6013 str r3, [r2, #0]
|
|
8007f54: e166 b.n 8008224 <USB_EPStartXfer+0x52c>
|
|
}
|
|
else
|
|
{
|
|
/* EP enable, IN data in FIFO */
|
|
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
|
8007f56: 69bb ldr r3, [r7, #24]
|
|
8007f58: 015a lsls r2, r3, #5
|
|
8007f5a: 69fb ldr r3, [r7, #28]
|
|
8007f5c: 4413 add r3, r2
|
|
8007f5e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007f62: 681b ldr r3, [r3, #0]
|
|
8007f64: 69ba ldr r2, [r7, #24]
|
|
8007f66: 0151 lsls r1, r2, #5
|
|
8007f68: 69fa ldr r2, [r7, #28]
|
|
8007f6a: 440a add r2, r1
|
|
8007f6c: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007f70: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
8007f74: 6013 str r3, [r2, #0]
|
|
|
|
if (ep->type != EP_TYPE_ISOC)
|
|
8007f76: 68bb ldr r3, [r7, #8]
|
|
8007f78: 791b ldrb r3, [r3, #4]
|
|
8007f7a: 2b01 cmp r3, #1
|
|
8007f7c: d015 beq.n 8007faa <USB_EPStartXfer+0x2b2>
|
|
{
|
|
/* Enable the Tx FIFO Empty Interrupt for this EP */
|
|
if (ep->xfer_len > 0U)
|
|
8007f7e: 68bb ldr r3, [r7, #8]
|
|
8007f80: 691b ldr r3, [r3, #16]
|
|
8007f82: 2b00 cmp r3, #0
|
|
8007f84: f000 814e beq.w 8008224 <USB_EPStartXfer+0x52c>
|
|
{
|
|
USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
|
|
8007f88: 69fb ldr r3, [r7, #28]
|
|
8007f8a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007f8e: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007f90: 68bb ldr r3, [r7, #8]
|
|
8007f92: 781b ldrb r3, [r3, #0]
|
|
8007f94: f003 030f and.w r3, r3, #15
|
|
8007f98: 2101 movs r1, #1
|
|
8007f9a: fa01 f303 lsl.w r3, r1, r3
|
|
8007f9e: 69f9 ldr r1, [r7, #28]
|
|
8007fa0: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8007fa4: 4313 orrs r3, r2
|
|
8007fa6: 634b str r3, [r1, #52] @ 0x34
|
|
8007fa8: e13c b.n 8008224 <USB_EPStartXfer+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
8007faa: 69fb ldr r3, [r7, #28]
|
|
8007fac: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007fb0: 689b ldr r3, [r3, #8]
|
|
8007fb2: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8007fb6: 2b00 cmp r3, #0
|
|
8007fb8: d110 bne.n 8007fdc <USB_EPStartXfer+0x2e4>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
|
|
8007fba: 69bb ldr r3, [r7, #24]
|
|
8007fbc: 015a lsls r2, r3, #5
|
|
8007fbe: 69fb ldr r3, [r7, #28]
|
|
8007fc0: 4413 add r3, r2
|
|
8007fc2: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007fc6: 681b ldr r3, [r3, #0]
|
|
8007fc8: 69ba ldr r2, [r7, #24]
|
|
8007fca: 0151 lsls r1, r2, #5
|
|
8007fcc: 69fa ldr r2, [r7, #28]
|
|
8007fce: 440a add r2, r1
|
|
8007fd0: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007fd4: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8007fd8: 6013 str r3, [r2, #0]
|
|
8007fda: e00f b.n 8007ffc <USB_EPStartXfer+0x304>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
|
8007fdc: 69bb ldr r3, [r7, #24]
|
|
8007fde: 015a lsls r2, r3, #5
|
|
8007fe0: 69fb ldr r3, [r7, #28]
|
|
8007fe2: 4413 add r3, r2
|
|
8007fe4: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007fe8: 681b ldr r3, [r3, #0]
|
|
8007fea: 69ba ldr r2, [r7, #24]
|
|
8007fec: 0151 lsls r1, r2, #5
|
|
8007fee: 69fa ldr r2, [r7, #28]
|
|
8007ff0: 440a add r2, r1
|
|
8007ff2: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007ff6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8007ffa: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
|
|
8007ffc: 68bb ldr r3, [r7, #8]
|
|
8007ffe: 68d9 ldr r1, [r3, #12]
|
|
8008000: 68bb ldr r3, [r7, #8]
|
|
8008002: 781a ldrb r2, [r3, #0]
|
|
8008004: 68bb ldr r3, [r7, #8]
|
|
8008006: 691b ldr r3, [r3, #16]
|
|
8008008: b298 uxth r0, r3
|
|
800800a: 79fb ldrb r3, [r7, #7]
|
|
800800c: 9300 str r3, [sp, #0]
|
|
800800e: 4603 mov r3, r0
|
|
8008010: 68f8 ldr r0, [r7, #12]
|
|
8008012: f000 f9b9 bl 8008388 <USB_WritePacket>
|
|
8008016: e105 b.n 8008224 <USB_EPStartXfer+0x52c>
|
|
{
|
|
/* Program the transfer size and packet count as follows:
|
|
* pktcnt = N
|
|
* xfersize = N * maxpacket
|
|
*/
|
|
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
|
|
8008018: 69bb ldr r3, [r7, #24]
|
|
800801a: 015a lsls r2, r3, #5
|
|
800801c: 69fb ldr r3, [r7, #28]
|
|
800801e: 4413 add r3, r2
|
|
8008020: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008024: 691b ldr r3, [r3, #16]
|
|
8008026: 69ba ldr r2, [r7, #24]
|
|
8008028: 0151 lsls r1, r2, #5
|
|
800802a: 69fa ldr r2, [r7, #28]
|
|
800802c: 440a add r2, r1
|
|
800802e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008032: 0cdb lsrs r3, r3, #19
|
|
8008034: 04db lsls r3, r3, #19
|
|
8008036: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
|
|
8008038: 69bb ldr r3, [r7, #24]
|
|
800803a: 015a lsls r2, r3, #5
|
|
800803c: 69fb ldr r3, [r7, #28]
|
|
800803e: 4413 add r3, r2
|
|
8008040: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008044: 691b ldr r3, [r3, #16]
|
|
8008046: 69ba ldr r2, [r7, #24]
|
|
8008048: 0151 lsls r1, r2, #5
|
|
800804a: 69fa ldr r2, [r7, #28]
|
|
800804c: 440a add r2, r1
|
|
800804e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008052: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
8008056: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
800805a: 6113 str r3, [r2, #16]
|
|
|
|
if (epnum == 0U)
|
|
800805c: 69bb ldr r3, [r7, #24]
|
|
800805e: 2b00 cmp r3, #0
|
|
8008060: d132 bne.n 80080c8 <USB_EPStartXfer+0x3d0>
|
|
{
|
|
if (ep->xfer_len > 0U)
|
|
8008062: 68bb ldr r3, [r7, #8]
|
|
8008064: 691b ldr r3, [r3, #16]
|
|
8008066: 2b00 cmp r3, #0
|
|
8008068: d003 beq.n 8008072 <USB_EPStartXfer+0x37a>
|
|
{
|
|
ep->xfer_len = ep->maxpacket;
|
|
800806a: 68bb ldr r3, [r7, #8]
|
|
800806c: 689a ldr r2, [r3, #8]
|
|
800806e: 68bb ldr r3, [r7, #8]
|
|
8008070: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
/* Store transfer size, for EP0 this is equal to endpoint max packet size */
|
|
ep->xfer_size = ep->maxpacket;
|
|
8008072: 68bb ldr r3, [r7, #8]
|
|
8008074: 689a ldr r2, [r3, #8]
|
|
8008076: 68bb ldr r3, [r7, #8]
|
|
8008078: 621a str r2, [r3, #32]
|
|
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
|
|
800807a: 69bb ldr r3, [r7, #24]
|
|
800807c: 015a lsls r2, r3, #5
|
|
800807e: 69fb ldr r3, [r7, #28]
|
|
8008080: 4413 add r3, r2
|
|
8008082: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008086: 691a ldr r2, [r3, #16]
|
|
8008088: 68bb ldr r3, [r7, #8]
|
|
800808a: 6a1b ldr r3, [r3, #32]
|
|
800808c: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8008090: 69b9 ldr r1, [r7, #24]
|
|
8008092: 0148 lsls r0, r1, #5
|
|
8008094: 69f9 ldr r1, [r7, #28]
|
|
8008096: 4401 add r1, r0
|
|
8008098: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
800809c: 4313 orrs r3, r2
|
|
800809e: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
80080a0: 69bb ldr r3, [r7, #24]
|
|
80080a2: 015a lsls r2, r3, #5
|
|
80080a4: 69fb ldr r3, [r7, #28]
|
|
80080a6: 4413 add r3, r2
|
|
80080a8: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80080ac: 691b ldr r3, [r3, #16]
|
|
80080ae: 69ba ldr r2, [r7, #24]
|
|
80080b0: 0151 lsls r1, r2, #5
|
|
80080b2: 69fa ldr r2, [r7, #28]
|
|
80080b4: 440a add r2, r1
|
|
80080b6: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
80080ba: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
80080be: 6113 str r3, [r2, #16]
|
|
80080c0: e062 b.n 8008188 <USB_EPStartXfer+0x490>
|
|
80080c2: bf00 nop
|
|
80080c4: 1ff80000 .word 0x1ff80000
|
|
}
|
|
else
|
|
{
|
|
if (ep->xfer_len == 0U)
|
|
80080c8: 68bb ldr r3, [r7, #8]
|
|
80080ca: 691b ldr r3, [r3, #16]
|
|
80080cc: 2b00 cmp r3, #0
|
|
80080ce: d123 bne.n 8008118 <USB_EPStartXfer+0x420>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
|
|
80080d0: 69bb ldr r3, [r7, #24]
|
|
80080d2: 015a lsls r2, r3, #5
|
|
80080d4: 69fb ldr r3, [r7, #28]
|
|
80080d6: 4413 add r3, r2
|
|
80080d8: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80080dc: 691a ldr r2, [r3, #16]
|
|
80080de: 68bb ldr r3, [r7, #8]
|
|
80080e0: 689b ldr r3, [r3, #8]
|
|
80080e2: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80080e6: 69b9 ldr r1, [r7, #24]
|
|
80080e8: 0148 lsls r0, r1, #5
|
|
80080ea: 69f9 ldr r1, [r7, #28]
|
|
80080ec: 4401 add r1, r0
|
|
80080ee: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
80080f2: 4313 orrs r3, r2
|
|
80080f4: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
80080f6: 69bb ldr r3, [r7, #24]
|
|
80080f8: 015a lsls r2, r3, #5
|
|
80080fa: 69fb ldr r3, [r7, #28]
|
|
80080fc: 4413 add r3, r2
|
|
80080fe: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008102: 691b ldr r3, [r3, #16]
|
|
8008104: 69ba ldr r2, [r7, #24]
|
|
8008106: 0151 lsls r1, r2, #5
|
|
8008108: 69fa ldr r2, [r7, #28]
|
|
800810a: 440a add r2, r1
|
|
800810c: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008110: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8008114: 6113 str r3, [r2, #16]
|
|
8008116: e037 b.n 8008188 <USB_EPStartXfer+0x490>
|
|
}
|
|
else
|
|
{
|
|
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
|
|
8008118: 68bb ldr r3, [r7, #8]
|
|
800811a: 691a ldr r2, [r3, #16]
|
|
800811c: 68bb ldr r3, [r7, #8]
|
|
800811e: 689b ldr r3, [r3, #8]
|
|
8008120: 4413 add r3, r2
|
|
8008122: 1e5a subs r2, r3, #1
|
|
8008124: 68bb ldr r3, [r7, #8]
|
|
8008126: 689b ldr r3, [r3, #8]
|
|
8008128: fbb2 f3f3 udiv r3, r2, r3
|
|
800812c: 82fb strh r3, [r7, #22]
|
|
ep->xfer_size = ep->maxpacket * pktcnt;
|
|
800812e: 68bb ldr r3, [r7, #8]
|
|
8008130: 689b ldr r3, [r3, #8]
|
|
8008132: 8afa ldrh r2, [r7, #22]
|
|
8008134: fb03 f202 mul.w r2, r3, r2
|
|
8008138: 68bb ldr r3, [r7, #8]
|
|
800813a: 621a str r2, [r3, #32]
|
|
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
|
|
800813c: 69bb ldr r3, [r7, #24]
|
|
800813e: 015a lsls r2, r3, #5
|
|
8008140: 69fb ldr r3, [r7, #28]
|
|
8008142: 4413 add r3, r2
|
|
8008144: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008148: 691a ldr r2, [r3, #16]
|
|
800814a: 8afb ldrh r3, [r7, #22]
|
|
800814c: 04d9 lsls r1, r3, #19
|
|
800814e: 4b38 ldr r3, [pc, #224] @ (8008230 <USB_EPStartXfer+0x538>)
|
|
8008150: 400b ands r3, r1
|
|
8008152: 69b9 ldr r1, [r7, #24]
|
|
8008154: 0148 lsls r0, r1, #5
|
|
8008156: 69f9 ldr r1, [r7, #28]
|
|
8008158: 4401 add r1, r0
|
|
800815a: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
800815e: 4313 orrs r3, r2
|
|
8008160: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size;
|
|
8008162: 69bb ldr r3, [r7, #24]
|
|
8008164: 015a lsls r2, r3, #5
|
|
8008166: 69fb ldr r3, [r7, #28]
|
|
8008168: 4413 add r3, r2
|
|
800816a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800816e: 691a ldr r2, [r3, #16]
|
|
8008170: 68bb ldr r3, [r7, #8]
|
|
8008172: 6a1b ldr r3, [r3, #32]
|
|
8008174: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8008178: 69b9 ldr r1, [r7, #24]
|
|
800817a: 0148 lsls r0, r1, #5
|
|
800817c: 69f9 ldr r1, [r7, #28]
|
|
800817e: 4401 add r1, r0
|
|
8008180: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
8008184: 4313 orrs r3, r2
|
|
8008186: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
if (dma == 1U)
|
|
8008188: 79fb ldrb r3, [r7, #7]
|
|
800818a: 2b01 cmp r3, #1
|
|
800818c: d10d bne.n 80081aa <USB_EPStartXfer+0x4b2>
|
|
{
|
|
if ((uint32_t)ep->xfer_buff != 0U)
|
|
800818e: 68bb ldr r3, [r7, #8]
|
|
8008190: 68db ldr r3, [r3, #12]
|
|
8008192: 2b00 cmp r3, #0
|
|
8008194: d009 beq.n 80081aa <USB_EPStartXfer+0x4b2>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
|
|
8008196: 68bb ldr r3, [r7, #8]
|
|
8008198: 68d9 ldr r1, [r3, #12]
|
|
800819a: 69bb ldr r3, [r7, #24]
|
|
800819c: 015a lsls r2, r3, #5
|
|
800819e: 69fb ldr r3, [r7, #28]
|
|
80081a0: 4413 add r3, r2
|
|
80081a2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80081a6: 460a mov r2, r1
|
|
80081a8: 615a str r2, [r3, #20]
|
|
}
|
|
}
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
80081aa: 68bb ldr r3, [r7, #8]
|
|
80081ac: 791b ldrb r3, [r3, #4]
|
|
80081ae: 2b01 cmp r3, #1
|
|
80081b0: d128 bne.n 8008204 <USB_EPStartXfer+0x50c>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
80081b2: 69fb ldr r3, [r7, #28]
|
|
80081b4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80081b8: 689b ldr r3, [r3, #8]
|
|
80081ba: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80081be: 2b00 cmp r3, #0
|
|
80081c0: d110 bne.n 80081e4 <USB_EPStartXfer+0x4ec>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
|
|
80081c2: 69bb ldr r3, [r7, #24]
|
|
80081c4: 015a lsls r2, r3, #5
|
|
80081c6: 69fb ldr r3, [r7, #28]
|
|
80081c8: 4413 add r3, r2
|
|
80081ca: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80081ce: 681b ldr r3, [r3, #0]
|
|
80081d0: 69ba ldr r2, [r7, #24]
|
|
80081d2: 0151 lsls r1, r2, #5
|
|
80081d4: 69fa ldr r2, [r7, #28]
|
|
80081d6: 440a add r2, r1
|
|
80081d8: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
80081dc: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
80081e0: 6013 str r3, [r2, #0]
|
|
80081e2: e00f b.n 8008204 <USB_EPStartXfer+0x50c>
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
|
|
80081e4: 69bb ldr r3, [r7, #24]
|
|
80081e6: 015a lsls r2, r3, #5
|
|
80081e8: 69fb ldr r3, [r7, #28]
|
|
80081ea: 4413 add r3, r2
|
|
80081ec: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80081f0: 681b ldr r3, [r3, #0]
|
|
80081f2: 69ba ldr r2, [r7, #24]
|
|
80081f4: 0151 lsls r1, r2, #5
|
|
80081f6: 69fa ldr r2, [r7, #28]
|
|
80081f8: 440a add r2, r1
|
|
80081fa: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
80081fe: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8008202: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
/* EP enable */
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
|
|
8008204: 69bb ldr r3, [r7, #24]
|
|
8008206: 015a lsls r2, r3, #5
|
|
8008208: 69fb ldr r3, [r7, #28]
|
|
800820a: 4413 add r3, r2
|
|
800820c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008210: 681b ldr r3, [r3, #0]
|
|
8008212: 69ba ldr r2, [r7, #24]
|
|
8008214: 0151 lsls r1, r2, #5
|
|
8008216: 69fa ldr r2, [r7, #28]
|
|
8008218: 440a add r2, r1
|
|
800821a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800821e: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
8008222: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8008224: 2300 movs r3, #0
|
|
}
|
|
8008226: 4618 mov r0, r3
|
|
8008228: 3720 adds r7, #32
|
|
800822a: 46bd mov sp, r7
|
|
800822c: bd80 pop {r7, pc}
|
|
800822e: bf00 nop
|
|
8008230: 1ff80000 .word 0x1ff80000
|
|
|
|
08008234 <USB_EPStopXfer>:
|
|
* @param USBx usb device instance
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8008234: b480 push {r7}
|
|
8008236: b087 sub sp, #28
|
|
8008238: af00 add r7, sp, #0
|
|
800823a: 6078 str r0, [r7, #4]
|
|
800823c: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
800823e: 2300 movs r3, #0
|
|
8008240: 60fb str r3, [r7, #12]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8008242: 2300 movs r3, #0
|
|
8008244: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8008246: 687b ldr r3, [r7, #4]
|
|
8008248: 613b str r3, [r7, #16]
|
|
|
|
/* IN endpoint */
|
|
if (ep->is_in == 1U)
|
|
800824a: 683b ldr r3, [r7, #0]
|
|
800824c: 785b ldrb r3, [r3, #1]
|
|
800824e: 2b01 cmp r3, #1
|
|
8008250: d14a bne.n 80082e8 <USB_EPStopXfer+0xb4>
|
|
{
|
|
/* EP enable, IN data in FIFO */
|
|
if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
8008252: 683b ldr r3, [r7, #0]
|
|
8008254: 781b ldrb r3, [r3, #0]
|
|
8008256: 015a lsls r2, r3, #5
|
|
8008258: 693b ldr r3, [r7, #16]
|
|
800825a: 4413 add r3, r2
|
|
800825c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8008260: 681b ldr r3, [r3, #0]
|
|
8008262: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8008266: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800826a: f040 8086 bne.w 800837a <USB_EPStopXfer+0x146>
|
|
{
|
|
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
|
|
800826e: 683b ldr r3, [r7, #0]
|
|
8008270: 781b ldrb r3, [r3, #0]
|
|
8008272: 015a lsls r2, r3, #5
|
|
8008274: 693b ldr r3, [r7, #16]
|
|
8008276: 4413 add r3, r2
|
|
8008278: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800827c: 681b ldr r3, [r3, #0]
|
|
800827e: 683a ldr r2, [r7, #0]
|
|
8008280: 7812 ldrb r2, [r2, #0]
|
|
8008282: 0151 lsls r1, r2, #5
|
|
8008284: 693a ldr r2, [r7, #16]
|
|
8008286: 440a add r2, r1
|
|
8008288: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800828c: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8008290: 6013 str r3, [r2, #0]
|
|
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
|
|
8008292: 683b ldr r3, [r7, #0]
|
|
8008294: 781b ldrb r3, [r3, #0]
|
|
8008296: 015a lsls r2, r3, #5
|
|
8008298: 693b ldr r3, [r7, #16]
|
|
800829a: 4413 add r3, r2
|
|
800829c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80082a0: 681b ldr r3, [r3, #0]
|
|
80082a2: 683a ldr r2, [r7, #0]
|
|
80082a4: 7812 ldrb r2, [r2, #0]
|
|
80082a6: 0151 lsls r1, r2, #5
|
|
80082a8: 693a ldr r2, [r7, #16]
|
|
80082aa: 440a add r2, r1
|
|
80082ac: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80082b0: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80082b4: 6013 str r3, [r2, #0]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
80082b6: 68fb ldr r3, [r7, #12]
|
|
80082b8: 3301 adds r3, #1
|
|
80082ba: 60fb str r3, [r7, #12]
|
|
|
|
if (count > 10000U)
|
|
80082bc: 68fb ldr r3, [r7, #12]
|
|
80082be: f242 7210 movw r2, #10000 @ 0x2710
|
|
80082c2: 4293 cmp r3, r2
|
|
80082c4: d902 bls.n 80082cc <USB_EPStopXfer+0x98>
|
|
{
|
|
ret = HAL_ERROR;
|
|
80082c6: 2301 movs r3, #1
|
|
80082c8: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80082ca: e056 b.n 800837a <USB_EPStopXfer+0x146>
|
|
}
|
|
} while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA);
|
|
80082cc: 683b ldr r3, [r7, #0]
|
|
80082ce: 781b ldrb r3, [r3, #0]
|
|
80082d0: 015a lsls r2, r3, #5
|
|
80082d2: 693b ldr r3, [r7, #16]
|
|
80082d4: 4413 add r3, r2
|
|
80082d6: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80082da: 681b ldr r3, [r3, #0]
|
|
80082dc: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80082e0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80082e4: d0e7 beq.n 80082b6 <USB_EPStopXfer+0x82>
|
|
80082e6: e048 b.n 800837a <USB_EPStopXfer+0x146>
|
|
}
|
|
}
|
|
else /* OUT endpoint */
|
|
{
|
|
if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
80082e8: 683b ldr r3, [r7, #0]
|
|
80082ea: 781b ldrb r3, [r3, #0]
|
|
80082ec: 015a lsls r2, r3, #5
|
|
80082ee: 693b ldr r3, [r7, #16]
|
|
80082f0: 4413 add r3, r2
|
|
80082f2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80082f6: 681b ldr r3, [r3, #0]
|
|
80082f8: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80082fc: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8008300: d13b bne.n 800837a <USB_EPStopXfer+0x146>
|
|
{
|
|
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
|
|
8008302: 683b ldr r3, [r7, #0]
|
|
8008304: 781b ldrb r3, [r3, #0]
|
|
8008306: 015a lsls r2, r3, #5
|
|
8008308: 693b ldr r3, [r7, #16]
|
|
800830a: 4413 add r3, r2
|
|
800830c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008310: 681b ldr r3, [r3, #0]
|
|
8008312: 683a ldr r2, [r7, #0]
|
|
8008314: 7812 ldrb r2, [r2, #0]
|
|
8008316: 0151 lsls r1, r2, #5
|
|
8008318: 693a ldr r2, [r7, #16]
|
|
800831a: 440a add r2, r1
|
|
800831c: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008320: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8008324: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
|
|
8008326: 683b ldr r3, [r7, #0]
|
|
8008328: 781b ldrb r3, [r3, #0]
|
|
800832a: 015a lsls r2, r3, #5
|
|
800832c: 693b ldr r3, [r7, #16]
|
|
800832e: 4413 add r3, r2
|
|
8008330: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008334: 681b ldr r3, [r3, #0]
|
|
8008336: 683a ldr r2, [r7, #0]
|
|
8008338: 7812 ldrb r2, [r2, #0]
|
|
800833a: 0151 lsls r1, r2, #5
|
|
800833c: 693a ldr r2, [r7, #16]
|
|
800833e: 440a add r2, r1
|
|
8008340: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008344: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8008348: 6013 str r3, [r2, #0]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
800834a: 68fb ldr r3, [r7, #12]
|
|
800834c: 3301 adds r3, #1
|
|
800834e: 60fb str r3, [r7, #12]
|
|
|
|
if (count > 10000U)
|
|
8008350: 68fb ldr r3, [r7, #12]
|
|
8008352: f242 7210 movw r2, #10000 @ 0x2710
|
|
8008356: 4293 cmp r3, r2
|
|
8008358: d902 bls.n 8008360 <USB_EPStopXfer+0x12c>
|
|
{
|
|
ret = HAL_ERROR;
|
|
800835a: 2301 movs r3, #1
|
|
800835c: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800835e: e00c b.n 800837a <USB_EPStopXfer+0x146>
|
|
}
|
|
} while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA);
|
|
8008360: 683b ldr r3, [r7, #0]
|
|
8008362: 781b ldrb r3, [r3, #0]
|
|
8008364: 015a lsls r2, r3, #5
|
|
8008366: 693b ldr r3, [r7, #16]
|
|
8008368: 4413 add r3, r2
|
|
800836a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800836e: 681b ldr r3, [r3, #0]
|
|
8008370: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8008374: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8008378: d0e7 beq.n 800834a <USB_EPStopXfer+0x116>
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
800837a: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800837c: 4618 mov r0, r3
|
|
800837e: 371c adds r7, #28
|
|
8008380: 46bd mov sp, r7
|
|
8008382: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008386: 4770 bx lr
|
|
|
|
08008388 <USB_WritePacket>:
|
|
* 1 : DMA feature used
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
|
|
uint8_t ch_ep_num, uint16_t len, uint8_t dma)
|
|
{
|
|
8008388: b480 push {r7}
|
|
800838a: b089 sub sp, #36 @ 0x24
|
|
800838c: af00 add r7, sp, #0
|
|
800838e: 60f8 str r0, [r7, #12]
|
|
8008390: 60b9 str r1, [r7, #8]
|
|
8008392: 4611 mov r1, r2
|
|
8008394: 461a mov r2, r3
|
|
8008396: 460b mov r3, r1
|
|
8008398: 71fb strb r3, [r7, #7]
|
|
800839a: 4613 mov r3, r2
|
|
800839c: 80bb strh r3, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800839e: 68fb ldr r3, [r7, #12]
|
|
80083a0: 617b str r3, [r7, #20]
|
|
uint8_t *pSrc = src;
|
|
80083a2: 68bb ldr r3, [r7, #8]
|
|
80083a4: 61fb str r3, [r7, #28]
|
|
uint32_t count32b;
|
|
uint32_t i;
|
|
|
|
if (dma == 0U)
|
|
80083a6: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
80083aa: 2b00 cmp r3, #0
|
|
80083ac: d123 bne.n 80083f6 <USB_WritePacket+0x6e>
|
|
{
|
|
count32b = ((uint32_t)len + 3U) / 4U;
|
|
80083ae: 88bb ldrh r3, [r7, #4]
|
|
80083b0: 3303 adds r3, #3
|
|
80083b2: 089b lsrs r3, r3, #2
|
|
80083b4: 613b str r3, [r7, #16]
|
|
for (i = 0U; i < count32b; i++)
|
|
80083b6: 2300 movs r3, #0
|
|
80083b8: 61bb str r3, [r7, #24]
|
|
80083ba: e018 b.n 80083ee <USB_WritePacket+0x66>
|
|
{
|
|
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
|
|
80083bc: 79fb ldrb r3, [r7, #7]
|
|
80083be: 031a lsls r2, r3, #12
|
|
80083c0: 697b ldr r3, [r7, #20]
|
|
80083c2: 4413 add r3, r2
|
|
80083c4: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
80083c8: 461a mov r2, r3
|
|
80083ca: 69fb ldr r3, [r7, #28]
|
|
80083cc: 681b ldr r3, [r3, #0]
|
|
80083ce: 6013 str r3, [r2, #0]
|
|
pSrc++;
|
|
80083d0: 69fb ldr r3, [r7, #28]
|
|
80083d2: 3301 adds r3, #1
|
|
80083d4: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
80083d6: 69fb ldr r3, [r7, #28]
|
|
80083d8: 3301 adds r3, #1
|
|
80083da: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
80083dc: 69fb ldr r3, [r7, #28]
|
|
80083de: 3301 adds r3, #1
|
|
80083e0: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
80083e2: 69fb ldr r3, [r7, #28]
|
|
80083e4: 3301 adds r3, #1
|
|
80083e6: 61fb str r3, [r7, #28]
|
|
for (i = 0U; i < count32b; i++)
|
|
80083e8: 69bb ldr r3, [r7, #24]
|
|
80083ea: 3301 adds r3, #1
|
|
80083ec: 61bb str r3, [r7, #24]
|
|
80083ee: 69ba ldr r2, [r7, #24]
|
|
80083f0: 693b ldr r3, [r7, #16]
|
|
80083f2: 429a cmp r2, r3
|
|
80083f4: d3e2 bcc.n 80083bc <USB_WritePacket+0x34>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
80083f6: 2300 movs r3, #0
|
|
}
|
|
80083f8: 4618 mov r0, r3
|
|
80083fa: 3724 adds r7, #36 @ 0x24
|
|
80083fc: 46bd mov sp, r7
|
|
80083fe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008402: 4770 bx lr
|
|
|
|
08008404 <USB_ReadPacket>:
|
|
* @param dest source pointer
|
|
* @param len Number of bytes to read
|
|
* @retval pointer to destination buffer
|
|
*/
|
|
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
|
|
{
|
|
8008404: b480 push {r7}
|
|
8008406: b08b sub sp, #44 @ 0x2c
|
|
8008408: af00 add r7, sp, #0
|
|
800840a: 60f8 str r0, [r7, #12]
|
|
800840c: 60b9 str r1, [r7, #8]
|
|
800840e: 4613 mov r3, r2
|
|
8008410: 80fb strh r3, [r7, #6]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8008412: 68fb ldr r3, [r7, #12]
|
|
8008414: 61bb str r3, [r7, #24]
|
|
uint8_t *pDest = dest;
|
|
8008416: 68bb ldr r3, [r7, #8]
|
|
8008418: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t pData;
|
|
uint32_t i;
|
|
uint32_t count32b = (uint32_t)len >> 2U;
|
|
800841a: 88fb ldrh r3, [r7, #6]
|
|
800841c: 089b lsrs r3, r3, #2
|
|
800841e: b29b uxth r3, r3
|
|
8008420: 617b str r3, [r7, #20]
|
|
uint16_t remaining_bytes = len % 4U;
|
|
8008422: 88fb ldrh r3, [r7, #6]
|
|
8008424: f003 0303 and.w r3, r3, #3
|
|
8008428: 83fb strh r3, [r7, #30]
|
|
|
|
for (i = 0U; i < count32b; i++)
|
|
800842a: 2300 movs r3, #0
|
|
800842c: 623b str r3, [r7, #32]
|
|
800842e: e014 b.n 800845a <USB_ReadPacket+0x56>
|
|
{
|
|
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
|
|
8008430: 69bb ldr r3, [r7, #24]
|
|
8008432: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8008436: 681a ldr r2, [r3, #0]
|
|
8008438: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800843a: 601a str r2, [r3, #0]
|
|
pDest++;
|
|
800843c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800843e: 3301 adds r3, #1
|
|
8008440: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8008442: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8008444: 3301 adds r3, #1
|
|
8008446: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8008448: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800844a: 3301 adds r3, #1
|
|
800844c: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
800844e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8008450: 3301 adds r3, #1
|
|
8008452: 627b str r3, [r7, #36] @ 0x24
|
|
for (i = 0U; i < count32b; i++)
|
|
8008454: 6a3b ldr r3, [r7, #32]
|
|
8008456: 3301 adds r3, #1
|
|
8008458: 623b str r3, [r7, #32]
|
|
800845a: 6a3a ldr r2, [r7, #32]
|
|
800845c: 697b ldr r3, [r7, #20]
|
|
800845e: 429a cmp r2, r3
|
|
8008460: d3e6 bcc.n 8008430 <USB_ReadPacket+0x2c>
|
|
}
|
|
|
|
/* When Number of data is not word aligned, read the remaining byte */
|
|
if (remaining_bytes != 0U)
|
|
8008462: 8bfb ldrh r3, [r7, #30]
|
|
8008464: 2b00 cmp r3, #0
|
|
8008466: d01e beq.n 80084a6 <USB_ReadPacket+0xa2>
|
|
{
|
|
i = 0U;
|
|
8008468: 2300 movs r3, #0
|
|
800846a: 623b str r3, [r7, #32]
|
|
__UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
|
|
800846c: 69bb ldr r3, [r7, #24]
|
|
800846e: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8008472: 461a mov r2, r3
|
|
8008474: f107 0310 add.w r3, r7, #16
|
|
8008478: 6812 ldr r2, [r2, #0]
|
|
800847a: 601a str r2, [r3, #0]
|
|
|
|
do
|
|
{
|
|
*(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
|
|
800847c: 693a ldr r2, [r7, #16]
|
|
800847e: 6a3b ldr r3, [r7, #32]
|
|
8008480: b2db uxtb r3, r3
|
|
8008482: 00db lsls r3, r3, #3
|
|
8008484: fa22 f303 lsr.w r3, r2, r3
|
|
8008488: b2da uxtb r2, r3
|
|
800848a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800848c: 701a strb r2, [r3, #0]
|
|
i++;
|
|
800848e: 6a3b ldr r3, [r7, #32]
|
|
8008490: 3301 adds r3, #1
|
|
8008492: 623b str r3, [r7, #32]
|
|
pDest++;
|
|
8008494: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8008496: 3301 adds r3, #1
|
|
8008498: 627b str r3, [r7, #36] @ 0x24
|
|
remaining_bytes--;
|
|
800849a: 8bfb ldrh r3, [r7, #30]
|
|
800849c: 3b01 subs r3, #1
|
|
800849e: 83fb strh r3, [r7, #30]
|
|
} while (remaining_bytes != 0U);
|
|
80084a0: 8bfb ldrh r3, [r7, #30]
|
|
80084a2: 2b00 cmp r3, #0
|
|
80084a4: d1ea bne.n 800847c <USB_ReadPacket+0x78>
|
|
}
|
|
|
|
return ((void *)pDest);
|
|
80084a6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
}
|
|
80084a8: 4618 mov r0, r3
|
|
80084aa: 372c adds r7, #44 @ 0x2c
|
|
80084ac: 46bd mov sp, r7
|
|
80084ae: f85d 7b04 ldr.w r7, [sp], #4
|
|
80084b2: 4770 bx lr
|
|
|
|
080084b4 <USB_EPSetStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
80084b4: b480 push {r7}
|
|
80084b6: b085 sub sp, #20
|
|
80084b8: af00 add r7, sp, #0
|
|
80084ba: 6078 str r0, [r7, #4]
|
|
80084bc: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80084be: 687b ldr r3, [r7, #4]
|
|
80084c0: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
80084c2: 683b ldr r3, [r7, #0]
|
|
80084c4: 781b ldrb r3, [r3, #0]
|
|
80084c6: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
80084c8: 683b ldr r3, [r7, #0]
|
|
80084ca: 785b ldrb r3, [r3, #1]
|
|
80084cc: 2b01 cmp r3, #1
|
|
80084ce: d12c bne.n 800852a <USB_EPSetStall+0x76>
|
|
{
|
|
if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
|
|
80084d0: 68bb ldr r3, [r7, #8]
|
|
80084d2: 015a lsls r2, r3, #5
|
|
80084d4: 68fb ldr r3, [r7, #12]
|
|
80084d6: 4413 add r3, r2
|
|
80084d8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80084dc: 681b ldr r3, [r3, #0]
|
|
80084de: 2b00 cmp r3, #0
|
|
80084e0: db12 blt.n 8008508 <USB_EPSetStall+0x54>
|
|
80084e2: 68bb ldr r3, [r7, #8]
|
|
80084e4: 2b00 cmp r3, #0
|
|
80084e6: d00f beq.n 8008508 <USB_EPSetStall+0x54>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
|
|
80084e8: 68bb ldr r3, [r7, #8]
|
|
80084ea: 015a lsls r2, r3, #5
|
|
80084ec: 68fb ldr r3, [r7, #12]
|
|
80084ee: 4413 add r3, r2
|
|
80084f0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80084f4: 681b ldr r3, [r3, #0]
|
|
80084f6: 68ba ldr r2, [r7, #8]
|
|
80084f8: 0151 lsls r1, r2, #5
|
|
80084fa: 68fa ldr r2, [r7, #12]
|
|
80084fc: 440a add r2, r1
|
|
80084fe: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8008502: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8008506: 6013 str r3, [r2, #0]
|
|
}
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
|
|
8008508: 68bb ldr r3, [r7, #8]
|
|
800850a: 015a lsls r2, r3, #5
|
|
800850c: 68fb ldr r3, [r7, #12]
|
|
800850e: 4413 add r3, r2
|
|
8008510: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8008514: 681b ldr r3, [r3, #0]
|
|
8008516: 68ba ldr r2, [r7, #8]
|
|
8008518: 0151 lsls r1, r2, #5
|
|
800851a: 68fa ldr r2, [r7, #12]
|
|
800851c: 440a add r2, r1
|
|
800851e: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8008522: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8008526: 6013 str r3, [r2, #0]
|
|
8008528: e02b b.n 8008582 <USB_EPSetStall+0xce>
|
|
}
|
|
else
|
|
{
|
|
if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
|
|
800852a: 68bb ldr r3, [r7, #8]
|
|
800852c: 015a lsls r2, r3, #5
|
|
800852e: 68fb ldr r3, [r7, #12]
|
|
8008530: 4413 add r3, r2
|
|
8008532: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008536: 681b ldr r3, [r3, #0]
|
|
8008538: 2b00 cmp r3, #0
|
|
800853a: db12 blt.n 8008562 <USB_EPSetStall+0xae>
|
|
800853c: 68bb ldr r3, [r7, #8]
|
|
800853e: 2b00 cmp r3, #0
|
|
8008540: d00f beq.n 8008562 <USB_EPSetStall+0xae>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
|
|
8008542: 68bb ldr r3, [r7, #8]
|
|
8008544: 015a lsls r2, r3, #5
|
|
8008546: 68fb ldr r3, [r7, #12]
|
|
8008548: 4413 add r3, r2
|
|
800854a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800854e: 681b ldr r3, [r3, #0]
|
|
8008550: 68ba ldr r2, [r7, #8]
|
|
8008552: 0151 lsls r1, r2, #5
|
|
8008554: 68fa ldr r2, [r7, #12]
|
|
8008556: 440a add r2, r1
|
|
8008558: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800855c: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8008560: 6013 str r3, [r2, #0]
|
|
}
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
|
|
8008562: 68bb ldr r3, [r7, #8]
|
|
8008564: 015a lsls r2, r3, #5
|
|
8008566: 68fb ldr r3, [r7, #12]
|
|
8008568: 4413 add r3, r2
|
|
800856a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800856e: 681b ldr r3, [r3, #0]
|
|
8008570: 68ba ldr r2, [r7, #8]
|
|
8008572: 0151 lsls r1, r2, #5
|
|
8008574: 68fa ldr r2, [r7, #12]
|
|
8008576: 440a add r2, r1
|
|
8008578: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800857c: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8008580: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8008582: 2300 movs r3, #0
|
|
}
|
|
8008584: 4618 mov r0, r3
|
|
8008586: 3714 adds r7, #20
|
|
8008588: 46bd mov sp, r7
|
|
800858a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800858e: 4770 bx lr
|
|
|
|
08008590 <USB_EPClearStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8008590: b480 push {r7}
|
|
8008592: b085 sub sp, #20
|
|
8008594: af00 add r7, sp, #0
|
|
8008596: 6078 str r0, [r7, #4]
|
|
8008598: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800859a: 687b ldr r3, [r7, #4]
|
|
800859c: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
800859e: 683b ldr r3, [r7, #0]
|
|
80085a0: 781b ldrb r3, [r3, #0]
|
|
80085a2: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
80085a4: 683b ldr r3, [r7, #0]
|
|
80085a6: 785b ldrb r3, [r3, #1]
|
|
80085a8: 2b01 cmp r3, #1
|
|
80085aa: d128 bne.n 80085fe <USB_EPClearStall+0x6e>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
|
80085ac: 68bb ldr r3, [r7, #8]
|
|
80085ae: 015a lsls r2, r3, #5
|
|
80085b0: 68fb ldr r3, [r7, #12]
|
|
80085b2: 4413 add r3, r2
|
|
80085b4: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80085b8: 681b ldr r3, [r3, #0]
|
|
80085ba: 68ba ldr r2, [r7, #8]
|
|
80085bc: 0151 lsls r1, r2, #5
|
|
80085be: 68fa ldr r2, [r7, #12]
|
|
80085c0: 440a add r2, r1
|
|
80085c2: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80085c6: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
80085ca: 6013 str r3, [r2, #0]
|
|
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
|
|
80085cc: 683b ldr r3, [r7, #0]
|
|
80085ce: 791b ldrb r3, [r3, #4]
|
|
80085d0: 2b03 cmp r3, #3
|
|
80085d2: d003 beq.n 80085dc <USB_EPClearStall+0x4c>
|
|
80085d4: 683b ldr r3, [r7, #0]
|
|
80085d6: 791b ldrb r3, [r3, #4]
|
|
80085d8: 2b02 cmp r3, #2
|
|
80085da: d138 bne.n 800864e <USB_EPClearStall+0xbe>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
|
|
80085dc: 68bb ldr r3, [r7, #8]
|
|
80085de: 015a lsls r2, r3, #5
|
|
80085e0: 68fb ldr r3, [r7, #12]
|
|
80085e2: 4413 add r3, r2
|
|
80085e4: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80085e8: 681b ldr r3, [r3, #0]
|
|
80085ea: 68ba ldr r2, [r7, #8]
|
|
80085ec: 0151 lsls r1, r2, #5
|
|
80085ee: 68fa ldr r2, [r7, #12]
|
|
80085f0: 440a add r2, r1
|
|
80085f2: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80085f6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80085fa: 6013 str r3, [r2, #0]
|
|
80085fc: e027 b.n 800864e <USB_EPClearStall+0xbe>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
|
80085fe: 68bb ldr r3, [r7, #8]
|
|
8008600: 015a lsls r2, r3, #5
|
|
8008602: 68fb ldr r3, [r7, #12]
|
|
8008604: 4413 add r3, r2
|
|
8008606: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800860a: 681b ldr r3, [r3, #0]
|
|
800860c: 68ba ldr r2, [r7, #8]
|
|
800860e: 0151 lsls r1, r2, #5
|
|
8008610: 68fa ldr r2, [r7, #12]
|
|
8008612: 440a add r2, r1
|
|
8008614: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008618: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
800861c: 6013 str r3, [r2, #0]
|
|
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
|
|
800861e: 683b ldr r3, [r7, #0]
|
|
8008620: 791b ldrb r3, [r3, #4]
|
|
8008622: 2b03 cmp r3, #3
|
|
8008624: d003 beq.n 800862e <USB_EPClearStall+0x9e>
|
|
8008626: 683b ldr r3, [r7, #0]
|
|
8008628: 791b ldrb r3, [r3, #4]
|
|
800862a: 2b02 cmp r3, #2
|
|
800862c: d10f bne.n 800864e <USB_EPClearStall+0xbe>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
|
|
800862e: 68bb ldr r3, [r7, #8]
|
|
8008630: 015a lsls r2, r3, #5
|
|
8008632: 68fb ldr r3, [r7, #12]
|
|
8008634: 4413 add r3, r2
|
|
8008636: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800863a: 681b ldr r3, [r3, #0]
|
|
800863c: 68ba ldr r2, [r7, #8]
|
|
800863e: 0151 lsls r1, r2, #5
|
|
8008640: 68fa ldr r2, [r7, #12]
|
|
8008642: 440a add r2, r1
|
|
8008644: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008648: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800864c: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800864e: 2300 movs r3, #0
|
|
}
|
|
8008650: 4618 mov r0, r3
|
|
8008652: 3714 adds r7, #20
|
|
8008654: 46bd mov sp, r7
|
|
8008656: f85d 7b04 ldr.w r7, [sp], #4
|
|
800865a: 4770 bx lr
|
|
|
|
0800865c <USB_SetDevAddress>:
|
|
* @param address new device address to be assigned
|
|
* This parameter can be a value from 0 to 255
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
|
|
{
|
|
800865c: b480 push {r7}
|
|
800865e: b085 sub sp, #20
|
|
8008660: af00 add r7, sp, #0
|
|
8008662: 6078 str r0, [r7, #4]
|
|
8008664: 460b mov r3, r1
|
|
8008666: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8008668: 687b ldr r3, [r7, #4]
|
|
800866a: 60fb str r3, [r7, #12]
|
|
|
|
USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
|
|
800866c: 68fb ldr r3, [r7, #12]
|
|
800866e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8008672: 681b ldr r3, [r3, #0]
|
|
8008674: 68fa ldr r2, [r7, #12]
|
|
8008676: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
800867a: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
|
|
800867e: 6013 str r3, [r2, #0]
|
|
USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
|
|
8008680: 68fb ldr r3, [r7, #12]
|
|
8008682: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8008686: 681a ldr r2, [r3, #0]
|
|
8008688: 78fb ldrb r3, [r7, #3]
|
|
800868a: 011b lsls r3, r3, #4
|
|
800868c: f403 63fe and.w r3, r3, #2032 @ 0x7f0
|
|
8008690: 68f9 ldr r1, [r7, #12]
|
|
8008692: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8008696: 4313 orrs r3, r2
|
|
8008698: 600b str r3, [r1, #0]
|
|
|
|
return HAL_OK;
|
|
800869a: 2300 movs r3, #0
|
|
}
|
|
800869c: 4618 mov r0, r3
|
|
800869e: 3714 adds r7, #20
|
|
80086a0: 46bd mov sp, r7
|
|
80086a2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80086a6: 4770 bx lr
|
|
|
|
080086a8 <USB_DevConnect>:
|
|
* @brief USB_DevConnect : Connect the USB device by enabling Rpu
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80086a8: b480 push {r7}
|
|
80086aa: b085 sub sp, #20
|
|
80086ac: af00 add r7, sp, #0
|
|
80086ae: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80086b0: 687b ldr r3, [r7, #4]
|
|
80086b2: 60fb str r3, [r7, #12]
|
|
|
|
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
|
|
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
|
|
80086b4: 68fb ldr r3, [r7, #12]
|
|
80086b6: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80086ba: 681b ldr r3, [r3, #0]
|
|
80086bc: 68fa ldr r2, [r7, #12]
|
|
80086be: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
80086c2: f023 0303 bic.w r3, r3, #3
|
|
80086c6: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
|
|
80086c8: 68fb ldr r3, [r7, #12]
|
|
80086ca: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80086ce: 685b ldr r3, [r3, #4]
|
|
80086d0: 68fa ldr r2, [r7, #12]
|
|
80086d2: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80086d6: f023 0302 bic.w r3, r3, #2
|
|
80086da: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
80086dc: 2300 movs r3, #0
|
|
}
|
|
80086de: 4618 mov r0, r3
|
|
80086e0: 3714 adds r7, #20
|
|
80086e2: 46bd mov sp, r7
|
|
80086e4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80086e8: 4770 bx lr
|
|
|
|
080086ea <USB_DevDisconnect>:
|
|
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80086ea: b480 push {r7}
|
|
80086ec: b085 sub sp, #20
|
|
80086ee: af00 add r7, sp, #0
|
|
80086f0: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80086f2: 687b ldr r3, [r7, #4]
|
|
80086f4: 60fb str r3, [r7, #12]
|
|
|
|
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
|
|
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
|
|
80086f6: 68fb ldr r3, [r7, #12]
|
|
80086f8: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80086fc: 681b ldr r3, [r3, #0]
|
|
80086fe: 68fa ldr r2, [r7, #12]
|
|
8008700: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
8008704: f023 0303 bic.w r3, r3, #3
|
|
8008708: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
800870a: 68fb ldr r3, [r7, #12]
|
|
800870c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8008710: 685b ldr r3, [r3, #4]
|
|
8008712: 68fa ldr r2, [r7, #12]
|
|
8008714: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8008718: f043 0302 orr.w r3, r3, #2
|
|
800871c: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
800871e: 2300 movs r3, #0
|
|
}
|
|
8008720: 4618 mov r0, r3
|
|
8008722: 3714 adds r7, #20
|
|
8008724: 46bd mov sp, r7
|
|
8008726: f85d 7b04 ldr.w r7, [sp], #4
|
|
800872a: 4770 bx lr
|
|
|
|
0800872c <USB_ReadInterrupts>:
|
|
* @brief USB_ReadInterrupts: return the global USB interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Global Interrupt status
|
|
*/
|
|
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
|
|
{
|
|
800872c: b480 push {r7}
|
|
800872e: b085 sub sp, #20
|
|
8008730: af00 add r7, sp, #0
|
|
8008732: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx->GINTSTS;
|
|
8008734: 687b ldr r3, [r7, #4]
|
|
8008736: 695b ldr r3, [r3, #20]
|
|
8008738: 60fb str r3, [r7, #12]
|
|
tmpreg &= USBx->GINTMSK;
|
|
800873a: 687b ldr r3, [r7, #4]
|
|
800873c: 699b ldr r3, [r3, #24]
|
|
800873e: 68fa ldr r2, [r7, #12]
|
|
8008740: 4013 ands r3, r2
|
|
8008742: 60fb str r3, [r7, #12]
|
|
|
|
return tmpreg;
|
|
8008744: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8008746: 4618 mov r0, r3
|
|
8008748: 3714 adds r7, #20
|
|
800874a: 46bd mov sp, r7
|
|
800874c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008750: 4770 bx lr
|
|
|
|
08008752 <USB_ReadDevAllOutEpInterrupt>:
|
|
* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Device OUT EP interrupt status
|
|
*/
|
|
uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8008752: b480 push {r7}
|
|
8008754: b085 sub sp, #20
|
|
8008756: af00 add r7, sp, #0
|
|
8008758: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800875a: 687b ldr r3, [r7, #4]
|
|
800875c: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_DEVICE->DAINT;
|
|
800875e: 68fb ldr r3, [r7, #12]
|
|
8008760: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8008764: 699b ldr r3, [r3, #24]
|
|
8008766: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DAINTMSK;
|
|
8008768: 68fb ldr r3, [r7, #12]
|
|
800876a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800876e: 69db ldr r3, [r3, #28]
|
|
8008770: 68ba ldr r2, [r7, #8]
|
|
8008772: 4013 ands r3, r2
|
|
8008774: 60bb str r3, [r7, #8]
|
|
|
|
return ((tmpreg & 0xffff0000U) >> 16);
|
|
8008776: 68bb ldr r3, [r7, #8]
|
|
8008778: 0c1b lsrs r3, r3, #16
|
|
}
|
|
800877a: 4618 mov r0, r3
|
|
800877c: 3714 adds r7, #20
|
|
800877e: 46bd mov sp, r7
|
|
8008780: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008784: 4770 bx lr
|
|
|
|
08008786 <USB_ReadDevAllInEpInterrupt>:
|
|
* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Device IN EP interrupt status
|
|
*/
|
|
uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8008786: b480 push {r7}
|
|
8008788: b085 sub sp, #20
|
|
800878a: af00 add r7, sp, #0
|
|
800878c: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800878e: 687b ldr r3, [r7, #4]
|
|
8008790: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_DEVICE->DAINT;
|
|
8008792: 68fb ldr r3, [r7, #12]
|
|
8008794: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8008798: 699b ldr r3, [r3, #24]
|
|
800879a: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DAINTMSK;
|
|
800879c: 68fb ldr r3, [r7, #12]
|
|
800879e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80087a2: 69db ldr r3, [r3, #28]
|
|
80087a4: 68ba ldr r2, [r7, #8]
|
|
80087a6: 4013 ands r3, r2
|
|
80087a8: 60bb str r3, [r7, #8]
|
|
|
|
return ((tmpreg & 0xFFFFU));
|
|
80087aa: 68bb ldr r3, [r7, #8]
|
|
80087ac: b29b uxth r3, r3
|
|
}
|
|
80087ae: 4618 mov r0, r3
|
|
80087b0: 3714 adds r7, #20
|
|
80087b2: 46bd mov sp, r7
|
|
80087b4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80087b8: 4770 bx lr
|
|
|
|
080087ba <USB_ReadDevOutEPInterrupt>:
|
|
* @param epnum endpoint number
|
|
* This parameter can be a value from 0 to 15
|
|
* @retval Device OUT EP Interrupt register
|
|
*/
|
|
uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
|
|
{
|
|
80087ba: b480 push {r7}
|
|
80087bc: b085 sub sp, #20
|
|
80087be: af00 add r7, sp, #0
|
|
80087c0: 6078 str r0, [r7, #4]
|
|
80087c2: 460b mov r3, r1
|
|
80087c4: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80087c6: 687b ldr r3, [r7, #4]
|
|
80087c8: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
|
|
80087ca: 78fb ldrb r3, [r7, #3]
|
|
80087cc: 015a lsls r2, r3, #5
|
|
80087ce: 68fb ldr r3, [r7, #12]
|
|
80087d0: 4413 add r3, r2
|
|
80087d2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80087d6: 689b ldr r3, [r3, #8]
|
|
80087d8: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DOEPMSK;
|
|
80087da: 68fb ldr r3, [r7, #12]
|
|
80087dc: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80087e0: 695b ldr r3, [r3, #20]
|
|
80087e2: 68ba ldr r2, [r7, #8]
|
|
80087e4: 4013 ands r3, r2
|
|
80087e6: 60bb str r3, [r7, #8]
|
|
|
|
return tmpreg;
|
|
80087e8: 68bb ldr r3, [r7, #8]
|
|
}
|
|
80087ea: 4618 mov r0, r3
|
|
80087ec: 3714 adds r7, #20
|
|
80087ee: 46bd mov sp, r7
|
|
80087f0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80087f4: 4770 bx lr
|
|
|
|
080087f6 <USB_ReadDevInEPInterrupt>:
|
|
* @param epnum endpoint number
|
|
* This parameter can be a value from 0 to 15
|
|
* @retval Device IN EP Interrupt register
|
|
*/
|
|
uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
|
|
{
|
|
80087f6: b480 push {r7}
|
|
80087f8: b087 sub sp, #28
|
|
80087fa: af00 add r7, sp, #0
|
|
80087fc: 6078 str r0, [r7, #4]
|
|
80087fe: 460b mov r3, r1
|
|
8008800: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8008802: 687b ldr r3, [r7, #4]
|
|
8008804: 617b str r3, [r7, #20]
|
|
uint32_t tmpreg;
|
|
uint32_t msk;
|
|
uint32_t emp;
|
|
|
|
msk = USBx_DEVICE->DIEPMSK;
|
|
8008806: 697b ldr r3, [r7, #20]
|
|
8008808: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800880c: 691b ldr r3, [r3, #16]
|
|
800880e: 613b str r3, [r7, #16]
|
|
emp = USBx_DEVICE->DIEPEMPMSK;
|
|
8008810: 697b ldr r3, [r7, #20]
|
|
8008812: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8008816: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8008818: 60fb str r3, [r7, #12]
|
|
msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
|
|
800881a: 78fb ldrb r3, [r7, #3]
|
|
800881c: f003 030f and.w r3, r3, #15
|
|
8008820: 68fa ldr r2, [r7, #12]
|
|
8008822: fa22 f303 lsr.w r3, r2, r3
|
|
8008826: 01db lsls r3, r3, #7
|
|
8008828: b2db uxtb r3, r3
|
|
800882a: 693a ldr r2, [r7, #16]
|
|
800882c: 4313 orrs r3, r2
|
|
800882e: 613b str r3, [r7, #16]
|
|
tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
|
|
8008830: 78fb ldrb r3, [r7, #3]
|
|
8008832: 015a lsls r2, r3, #5
|
|
8008834: 697b ldr r3, [r7, #20]
|
|
8008836: 4413 add r3, r2
|
|
8008838: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800883c: 689b ldr r3, [r3, #8]
|
|
800883e: 693a ldr r2, [r7, #16]
|
|
8008840: 4013 ands r3, r2
|
|
8008842: 60bb str r3, [r7, #8]
|
|
|
|
return tmpreg;
|
|
8008844: 68bb ldr r3, [r7, #8]
|
|
}
|
|
8008846: 4618 mov r0, r3
|
|
8008848: 371c adds r7, #28
|
|
800884a: 46bd mov sp, r7
|
|
800884c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008850: 4770 bx lr
|
|
|
|
08008852 <USB_GetMode>:
|
|
* This parameter can be one of these values:
|
|
* 1 : Host
|
|
* 0 : Device
|
|
*/
|
|
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8008852: b480 push {r7}
|
|
8008854: b083 sub sp, #12
|
|
8008856: af00 add r7, sp, #0
|
|
8008858: 6078 str r0, [r7, #4]
|
|
return ((USBx->GINTSTS) & 0x1U);
|
|
800885a: 687b ldr r3, [r7, #4]
|
|
800885c: 695b ldr r3, [r3, #20]
|
|
800885e: f003 0301 and.w r3, r3, #1
|
|
}
|
|
8008862: 4618 mov r0, r3
|
|
8008864: 370c adds r7, #12
|
|
8008866: 46bd mov sp, r7
|
|
8008868: f85d 7b04 ldr.w r7, [sp], #4
|
|
800886c: 4770 bx lr
|
|
|
|
0800886e <USB_ActivateSetup>:
|
|
* @brief Activate EP0 for Setup transactions
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800886e: b480 push {r7}
|
|
8008870: b085 sub sp, #20
|
|
8008872: af00 add r7, sp, #0
|
|
8008874: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8008876: 687b ldr r3, [r7, #4]
|
|
8008878: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the MPS of the IN EP0 to 64 bytes */
|
|
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
|
|
800887a: 68fb ldr r3, [r7, #12]
|
|
800887c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8008880: 681b ldr r3, [r3, #0]
|
|
8008882: 68fa ldr r2, [r7, #12]
|
|
8008884: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8008888: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
|
|
800888c: f023 0307 bic.w r3, r3, #7
|
|
8008890: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
|
|
8008892: 68fb ldr r3, [r7, #12]
|
|
8008894: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8008898: 685b ldr r3, [r3, #4]
|
|
800889a: 68fa ldr r2, [r7, #12]
|
|
800889c: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80088a0: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80088a4: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
80088a6: 2300 movs r3, #0
|
|
}
|
|
80088a8: 4618 mov r0, r3
|
|
80088aa: 3714 adds r7, #20
|
|
80088ac: 46bd mov sp, r7
|
|
80088ae: f85d 7b04 ldr.w r7, [sp], #4
|
|
80088b2: 4770 bx lr
|
|
|
|
080088b4 <USB_EP0_OutStart>:
|
|
* 1 : DMA feature used
|
|
* @param psetup pointer to setup packet
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup)
|
|
{
|
|
80088b4: b480 push {r7}
|
|
80088b6: b087 sub sp, #28
|
|
80088b8: af00 add r7, sp, #0
|
|
80088ba: 60f8 str r0, [r7, #12]
|
|
80088bc: 460b mov r3, r1
|
|
80088be: 607a str r2, [r7, #4]
|
|
80088c0: 72fb strb r3, [r7, #11]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80088c2: 68fb ldr r3, [r7, #12]
|
|
80088c4: 617b str r3, [r7, #20]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
80088c6: 68fb ldr r3, [r7, #12]
|
|
80088c8: 333c adds r3, #60 @ 0x3c
|
|
80088ca: 3304 adds r3, #4
|
|
80088cc: 681b ldr r3, [r3, #0]
|
|
80088ce: 613b str r3, [r7, #16]
|
|
|
|
if (gSNPSiD > USB_OTG_CORE_ID_300A)
|
|
80088d0: 693b ldr r3, [r7, #16]
|
|
80088d2: 4a26 ldr r2, [pc, #152] @ (800896c <USB_EP0_OutStart+0xb8>)
|
|
80088d4: 4293 cmp r3, r2
|
|
80088d6: d90a bls.n 80088ee <USB_EP0_OutStart+0x3a>
|
|
{
|
|
if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
80088d8: 697b ldr r3, [r7, #20]
|
|
80088da: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80088de: 681b ldr r3, [r3, #0]
|
|
80088e0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80088e4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80088e8: d101 bne.n 80088ee <USB_EP0_OutStart+0x3a>
|
|
{
|
|
return HAL_OK;
|
|
80088ea: 2300 movs r3, #0
|
|
80088ec: e037 b.n 800895e <USB_EP0_OutStart+0xaa>
|
|
}
|
|
}
|
|
|
|
USBx_OUTEP(0U)->DOEPTSIZ = 0U;
|
|
80088ee: 697b ldr r3, [r7, #20]
|
|
80088f0: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80088f4: 461a mov r2, r3
|
|
80088f6: 2300 movs r3, #0
|
|
80088f8: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
80088fa: 697b ldr r3, [r7, #20]
|
|
80088fc: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008900: 691b ldr r3, [r3, #16]
|
|
8008902: 697a ldr r2, [r7, #20]
|
|
8008904: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008908: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
800890c: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
|
|
800890e: 697b ldr r3, [r7, #20]
|
|
8008910: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008914: 691b ldr r3, [r3, #16]
|
|
8008916: 697a ldr r2, [r7, #20]
|
|
8008918: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800891c: f043 0318 orr.w r3, r3, #24
|
|
8008920: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
|
|
8008922: 697b ldr r3, [r7, #20]
|
|
8008924: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008928: 691b ldr r3, [r3, #16]
|
|
800892a: 697a ldr r2, [r7, #20]
|
|
800892c: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008930: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000
|
|
8008934: 6113 str r3, [r2, #16]
|
|
|
|
if (dma == 1U)
|
|
8008936: 7afb ldrb r3, [r7, #11]
|
|
8008938: 2b01 cmp r3, #1
|
|
800893a: d10f bne.n 800895c <USB_EP0_OutStart+0xa8>
|
|
{
|
|
USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
|
|
800893c: 697b ldr r3, [r7, #20]
|
|
800893e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008942: 461a mov r2, r3
|
|
8008944: 687b ldr r3, [r7, #4]
|
|
8008946: 6153 str r3, [r2, #20]
|
|
/* EP enable */
|
|
USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
|
|
8008948: 697b ldr r3, [r7, #20]
|
|
800894a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800894e: 681b ldr r3, [r3, #0]
|
|
8008950: 697a ldr r2, [r7, #20]
|
|
8008952: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008956: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000
|
|
800895a: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
800895c: 2300 movs r3, #0
|
|
}
|
|
800895e: 4618 mov r0, r3
|
|
8008960: 371c adds r7, #28
|
|
8008962: 46bd mov sp, r7
|
|
8008964: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008968: 4770 bx lr
|
|
800896a: bf00 nop
|
|
800896c: 4f54300a .word 0x4f54300a
|
|
|
|
08008970 <USB_CoreReset>:
|
|
* @brief Reset the USB Core (needed after USB clock settings change)
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8008970: b480 push {r7}
|
|
8008972: b085 sub sp, #20
|
|
8008974: af00 add r7, sp, #0
|
|
8008976: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
8008978: 2300 movs r3, #0
|
|
800897a: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
800897c: 68fb ldr r3, [r7, #12]
|
|
800897e: 3301 adds r3, #1
|
|
8008980: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8008982: 68fb ldr r3, [r7, #12]
|
|
8008984: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8008988: d901 bls.n 800898e <USB_CoreReset+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800898a: 2303 movs r3, #3
|
|
800898c: e022 b.n 80089d4 <USB_CoreReset+0x64>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
800898e: 687b ldr r3, [r7, #4]
|
|
8008990: 691b ldr r3, [r3, #16]
|
|
8008992: 2b00 cmp r3, #0
|
|
8008994: daf2 bge.n 800897c <USB_CoreReset+0xc>
|
|
|
|
count = 10U;
|
|
8008996: 230a movs r3, #10
|
|
8008998: 60fb str r3, [r7, #12]
|
|
|
|
/* few cycles before setting core reset */
|
|
while (count > 0U)
|
|
800899a: e002 b.n 80089a2 <USB_CoreReset+0x32>
|
|
{
|
|
count--;
|
|
800899c: 68fb ldr r3, [r7, #12]
|
|
800899e: 3b01 subs r3, #1
|
|
80089a0: 60fb str r3, [r7, #12]
|
|
while (count > 0U)
|
|
80089a2: 68fb ldr r3, [r7, #12]
|
|
80089a4: 2b00 cmp r3, #0
|
|
80089a6: d1f9 bne.n 800899c <USB_CoreReset+0x2c>
|
|
}
|
|
|
|
/* Core Soft Reset */
|
|
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
|
|
80089a8: 687b ldr r3, [r7, #4]
|
|
80089aa: 691b ldr r3, [r3, #16]
|
|
80089ac: f043 0201 orr.w r2, r3, #1
|
|
80089b0: 687b ldr r3, [r7, #4]
|
|
80089b2: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
80089b4: 68fb ldr r3, [r7, #12]
|
|
80089b6: 3301 adds r3, #1
|
|
80089b8: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80089ba: 68fb ldr r3, [r7, #12]
|
|
80089bc: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80089c0: d901 bls.n 80089c6 <USB_CoreReset+0x56>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80089c2: 2303 movs r3, #3
|
|
80089c4: e006 b.n 80089d4 <USB_CoreReset+0x64>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
|
|
80089c6: 687b ldr r3, [r7, #4]
|
|
80089c8: 691b ldr r3, [r3, #16]
|
|
80089ca: f003 0301 and.w r3, r3, #1
|
|
80089ce: 2b01 cmp r3, #1
|
|
80089d0: d0f0 beq.n 80089b4 <USB_CoreReset+0x44>
|
|
|
|
return HAL_OK;
|
|
80089d2: 2300 movs r3, #0
|
|
}
|
|
80089d4: 4618 mov r0, r3
|
|
80089d6: 3714 adds r7, #20
|
|
80089d8: 46bd mov sp, r7
|
|
80089da: f85d 7b04 ldr.w r7, [sp], #4
|
|
80089de: 4770 bx lr
|
|
|
|
080089e0 <USBD_HID_Init>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
80089e0: b580 push {r7, lr}
|
|
80089e2: b084 sub sp, #16
|
|
80089e4: af00 add r7, sp, #0
|
|
80089e6: 6078 str r0, [r7, #4]
|
|
80089e8: 460b mov r3, r1
|
|
80089ea: 70fb strb r3, [r7, #3]
|
|
UNUSED(cfgidx);
|
|
|
|
USBD_HID_HandleTypeDef *hhid;
|
|
|
|
hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef));
|
|
80089ec: 2010 movs r0, #16
|
|
80089ee: f002 f9e3 bl 800adb8 <USBD_static_malloc>
|
|
80089f2: 60f8 str r0, [r7, #12]
|
|
|
|
if (hhid == NULL)
|
|
80089f4: 68fb ldr r3, [r7, #12]
|
|
80089f6: 2b00 cmp r3, #0
|
|
80089f8: d109 bne.n 8008a0e <USBD_HID_Init+0x2e>
|
|
{
|
|
pdev->pClassDataCmsit[pdev->classId] = NULL;
|
|
80089fa: 687b ldr r3, [r7, #4]
|
|
80089fc: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008a00: 687b ldr r3, [r7, #4]
|
|
8008a02: 32b0 adds r2, #176 @ 0xb0
|
|
8008a04: 2100 movs r1, #0
|
|
8008a06: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
return (uint8_t)USBD_EMEM;
|
|
8008a0a: 2302 movs r3, #2
|
|
8008a0c: e048 b.n 8008aa0 <USBD_HID_Init+0xc0>
|
|
}
|
|
|
|
pdev->pClassDataCmsit[pdev->classId] = (void *)hhid;
|
|
8008a0e: 687b ldr r3, [r7, #4]
|
|
8008a10: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008a14: 687b ldr r3, [r7, #4]
|
|
8008a16: 32b0 adds r2, #176 @ 0xb0
|
|
8008a18: 68f9 ldr r1, [r7, #12]
|
|
8008a1a: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
|
|
8008a1e: 687b ldr r3, [r7, #4]
|
|
8008a20: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008a24: 687b ldr r3, [r7, #4]
|
|
8008a26: 32b0 adds r2, #176 @ 0xb0
|
|
8008a28: f853 2022 ldr.w r2, [r3, r2, lsl #2]
|
|
8008a2c: 687b ldr r3, [r7, #4]
|
|
8008a2e: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
|
|
#ifdef USE_USBD_COMPOSITE
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8008a32: 687b ldr r3, [r7, #4]
|
|
8008a34: 7c1b ldrb r3, [r3, #16]
|
|
8008a36: 2b00 cmp r3, #0
|
|
8008a38: d10d bne.n 8008a56 <USBD_HID_Init+0x76>
|
|
{
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL;
|
|
8008a3a: 4b1b ldr r3, [pc, #108] @ (8008aa8 <USBD_HID_Init+0xc8>)
|
|
8008a3c: 781b ldrb r3, [r3, #0]
|
|
8008a3e: f003 020f and.w r2, r3, #15
|
|
8008a42: 6879 ldr r1, [r7, #4]
|
|
8008a44: 4613 mov r3, r2
|
|
8008a46: 009b lsls r3, r3, #2
|
|
8008a48: 4413 add r3, r2
|
|
8008a4a: 009b lsls r3, r3, #2
|
|
8008a4c: 440b add r3, r1
|
|
8008a4e: 331c adds r3, #28
|
|
8008a50: 2207 movs r2, #7
|
|
8008a52: 601a str r2, [r3, #0]
|
|
8008a54: e00c b.n 8008a70 <USBD_HID_Init+0x90>
|
|
}
|
|
else /* LOW and FULL-speed endpoints */
|
|
{
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL;
|
|
8008a56: 4b14 ldr r3, [pc, #80] @ (8008aa8 <USBD_HID_Init+0xc8>)
|
|
8008a58: 781b ldrb r3, [r3, #0]
|
|
8008a5a: f003 020f and.w r2, r3, #15
|
|
8008a5e: 6879 ldr r1, [r7, #4]
|
|
8008a60: 4613 mov r3, r2
|
|
8008a62: 009b lsls r3, r3, #2
|
|
8008a64: 4413 add r3, r2
|
|
8008a66: 009b lsls r3, r3, #2
|
|
8008a68: 440b add r3, r1
|
|
8008a6a: 331c adds r3, #28
|
|
8008a6c: 220a movs r2, #10
|
|
8008a6e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Open EP IN */
|
|
(void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE);
|
|
8008a70: 4b0d ldr r3, [pc, #52] @ (8008aa8 <USBD_HID_Init+0xc8>)
|
|
8008a72: 7819 ldrb r1, [r3, #0]
|
|
8008a74: 230e movs r3, #14
|
|
8008a76: 2203 movs r2, #3
|
|
8008a78: 6878 ldr r0, [r7, #4]
|
|
8008a7a: f002 f83e bl 800aafa <USBD_LL_OpenEP>
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U;
|
|
8008a7e: 4b0a ldr r3, [pc, #40] @ (8008aa8 <USBD_HID_Init+0xc8>)
|
|
8008a80: 781b ldrb r3, [r3, #0]
|
|
8008a82: f003 020f and.w r2, r3, #15
|
|
8008a86: 6879 ldr r1, [r7, #4]
|
|
8008a88: 4613 mov r3, r2
|
|
8008a8a: 009b lsls r3, r3, #2
|
|
8008a8c: 4413 add r3, r2
|
|
8008a8e: 009b lsls r3, r3, #2
|
|
8008a90: 440b add r3, r1
|
|
8008a92: 3323 adds r3, #35 @ 0x23
|
|
8008a94: 2201 movs r2, #1
|
|
8008a96: 701a strb r2, [r3, #0]
|
|
|
|
hhid->state = USBD_HID_IDLE;
|
|
8008a98: 68fb ldr r3, [r7, #12]
|
|
8008a9a: 2200 movs r2, #0
|
|
8008a9c: 731a strb r2, [r3, #12]
|
|
|
|
return (uint8_t)USBD_OK;
|
|
8008a9e: 2300 movs r3, #0
|
|
}
|
|
8008aa0: 4618 mov r0, r3
|
|
8008aa2: 3710 adds r7, #16
|
|
8008aa4: 46bd mov sp, r7
|
|
8008aa6: bd80 pop {r7, pc}
|
|
8008aa8: 2000013d .word 0x2000013d
|
|
|
|
08008aac <USBD_HID_DeInit>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8008aac: b580 push {r7, lr}
|
|
8008aae: b082 sub sp, #8
|
|
8008ab0: af00 add r7, sp, #0
|
|
8008ab2: 6078 str r0, [r7, #4]
|
|
8008ab4: 460b mov r3, r1
|
|
8008ab6: 70fb strb r3, [r7, #3]
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Close HID EPs */
|
|
(void)USBD_LL_CloseEP(pdev, HIDInEpAdd);
|
|
8008ab8: 4b1f ldr r3, [pc, #124] @ (8008b38 <USBD_HID_DeInit+0x8c>)
|
|
8008aba: 781b ldrb r3, [r3, #0]
|
|
8008abc: 4619 mov r1, r3
|
|
8008abe: 6878 ldr r0, [r7, #4]
|
|
8008ac0: f002 f841 bl 800ab46 <USBD_LL_CloseEP>
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U;
|
|
8008ac4: 4b1c ldr r3, [pc, #112] @ (8008b38 <USBD_HID_DeInit+0x8c>)
|
|
8008ac6: 781b ldrb r3, [r3, #0]
|
|
8008ac8: f003 020f and.w r2, r3, #15
|
|
8008acc: 6879 ldr r1, [r7, #4]
|
|
8008ace: 4613 mov r3, r2
|
|
8008ad0: 009b lsls r3, r3, #2
|
|
8008ad2: 4413 add r3, r2
|
|
8008ad4: 009b lsls r3, r3, #2
|
|
8008ad6: 440b add r3, r1
|
|
8008ad8: 3323 adds r3, #35 @ 0x23
|
|
8008ada: 2200 movs r2, #0
|
|
8008adc: 701a strb r2, [r3, #0]
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U;
|
|
8008ade: 4b16 ldr r3, [pc, #88] @ (8008b38 <USBD_HID_DeInit+0x8c>)
|
|
8008ae0: 781b ldrb r3, [r3, #0]
|
|
8008ae2: f003 020f and.w r2, r3, #15
|
|
8008ae6: 6879 ldr r1, [r7, #4]
|
|
8008ae8: 4613 mov r3, r2
|
|
8008aea: 009b lsls r3, r3, #2
|
|
8008aec: 4413 add r3, r2
|
|
8008aee: 009b lsls r3, r3, #2
|
|
8008af0: 440b add r3, r1
|
|
8008af2: 331c adds r3, #28
|
|
8008af4: 2200 movs r2, #0
|
|
8008af6: 601a str r2, [r3, #0]
|
|
|
|
/* Free allocated memory */
|
|
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
|
|
8008af8: 687b ldr r3, [r7, #4]
|
|
8008afa: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008afe: 687b ldr r3, [r7, #4]
|
|
8008b00: 32b0 adds r2, #176 @ 0xb0
|
|
8008b02: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008b06: 2b00 cmp r3, #0
|
|
8008b08: d011 beq.n 8008b2e <USBD_HID_DeInit+0x82>
|
|
{
|
|
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
|
|
8008b0a: 687b ldr r3, [r7, #4]
|
|
8008b0c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008b10: 687b ldr r3, [r7, #4]
|
|
8008b12: 32b0 adds r2, #176 @ 0xb0
|
|
8008b14: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008b18: 4618 mov r0, r3
|
|
8008b1a: f002 f95b bl 800add4 <USBD_static_free>
|
|
pdev->pClassDataCmsit[pdev->classId] = NULL;
|
|
8008b1e: 687b ldr r3, [r7, #4]
|
|
8008b20: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008b24: 687b ldr r3, [r7, #4]
|
|
8008b26: 32b0 adds r2, #176 @ 0xb0
|
|
8008b28: 2100 movs r1, #0
|
|
8008b2a: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
8008b2e: 2300 movs r3, #0
|
|
}
|
|
8008b30: 4618 mov r0, r3
|
|
8008b32: 3708 adds r7, #8
|
|
8008b34: 46bd mov sp, r7
|
|
8008b36: bd80 pop {r7, pc}
|
|
8008b38: 2000013d .word 0x2000013d
|
|
|
|
08008b3c <USBD_HID_Setup>:
|
|
* @param pdev: instance
|
|
* @param req: usb requests
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008b3c: b580 push {r7, lr}
|
|
8008b3e: b086 sub sp, #24
|
|
8008b40: af00 add r7, sp, #0
|
|
8008b42: 6078 str r0, [r7, #4]
|
|
8008b44: 6039 str r1, [r7, #0]
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
8008b46: 687b ldr r3, [r7, #4]
|
|
8008b48: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008b4c: 687b ldr r3, [r7, #4]
|
|
8008b4e: 32b0 adds r2, #176 @ 0xb0
|
|
8008b50: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008b54: 60fb str r3, [r7, #12]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8008b56: 2300 movs r3, #0
|
|
8008b58: 75fb strb r3, [r7, #23]
|
|
uint16_t len;
|
|
uint8_t *pbuf;
|
|
uint16_t status_info = 0U;
|
|
8008b5a: 2300 movs r3, #0
|
|
8008b5c: 817b strh r3, [r7, #10]
|
|
|
|
if (hhid == NULL)
|
|
8008b5e: 68fb ldr r3, [r7, #12]
|
|
8008b60: 2b00 cmp r3, #0
|
|
8008b62: d101 bne.n 8008b68 <USBD_HID_Setup+0x2c>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
8008b64: 2303 movs r3, #3
|
|
8008b66: e0e8 b.n 8008d3a <USBD_HID_Setup+0x1fe>
|
|
}
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8008b68: 683b ldr r3, [r7, #0]
|
|
8008b6a: 781b ldrb r3, [r3, #0]
|
|
8008b6c: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8008b70: 2b00 cmp r3, #0
|
|
8008b72: d046 beq.n 8008c02 <USBD_HID_Setup+0xc6>
|
|
8008b74: 2b20 cmp r3, #32
|
|
8008b76: f040 80d8 bne.w 8008d2a <USBD_HID_Setup+0x1ee>
|
|
{
|
|
case USB_REQ_TYPE_CLASS :
|
|
switch (req->bRequest)
|
|
8008b7a: 683b ldr r3, [r7, #0]
|
|
8008b7c: 785b ldrb r3, [r3, #1]
|
|
8008b7e: 3b02 subs r3, #2
|
|
8008b80: 2b09 cmp r3, #9
|
|
8008b82: d836 bhi.n 8008bf2 <USBD_HID_Setup+0xb6>
|
|
8008b84: a201 add r2, pc, #4 @ (adr r2, 8008b8c <USBD_HID_Setup+0x50>)
|
|
8008b86: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8008b8a: bf00 nop
|
|
8008b8c: 08008be3 .word 0x08008be3
|
|
8008b90: 08008bc3 .word 0x08008bc3
|
|
8008b94: 08008bf3 .word 0x08008bf3
|
|
8008b98: 08008bf3 .word 0x08008bf3
|
|
8008b9c: 08008bf3 .word 0x08008bf3
|
|
8008ba0: 08008bf3 .word 0x08008bf3
|
|
8008ba4: 08008bf3 .word 0x08008bf3
|
|
8008ba8: 08008bf3 .word 0x08008bf3
|
|
8008bac: 08008bd1 .word 0x08008bd1
|
|
8008bb0: 08008bb5 .word 0x08008bb5
|
|
{
|
|
case USBD_HID_REQ_SET_PROTOCOL:
|
|
hhid->Protocol = (uint8_t)(req->wValue);
|
|
8008bb4: 683b ldr r3, [r7, #0]
|
|
8008bb6: 885b ldrh r3, [r3, #2]
|
|
8008bb8: b2db uxtb r3, r3
|
|
8008bba: 461a mov r2, r3
|
|
8008bbc: 68fb ldr r3, [r7, #12]
|
|
8008bbe: 601a str r2, [r3, #0]
|
|
break;
|
|
8008bc0: e01e b.n 8008c00 <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_GET_PROTOCOL:
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U);
|
|
8008bc2: 68fb ldr r3, [r7, #12]
|
|
8008bc4: 2201 movs r2, #1
|
|
8008bc6: 4619 mov r1, r3
|
|
8008bc8: 6878 ldr r0, [r7, #4]
|
|
8008bca: f001 fc25 bl 800a418 <USBD_CtlSendData>
|
|
break;
|
|
8008bce: e017 b.n 8008c00 <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_SET_IDLE:
|
|
hhid->IdleState = (uint8_t)(req->wValue >> 8);
|
|
8008bd0: 683b ldr r3, [r7, #0]
|
|
8008bd2: 885b ldrh r3, [r3, #2]
|
|
8008bd4: 0a1b lsrs r3, r3, #8
|
|
8008bd6: b29b uxth r3, r3
|
|
8008bd8: b2db uxtb r3, r3
|
|
8008bda: 461a mov r2, r3
|
|
8008bdc: 68fb ldr r3, [r7, #12]
|
|
8008bde: 605a str r2, [r3, #4]
|
|
break;
|
|
8008be0: e00e b.n 8008c00 <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_GET_IDLE:
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U);
|
|
8008be2: 68fb ldr r3, [r7, #12]
|
|
8008be4: 3304 adds r3, #4
|
|
8008be6: 2201 movs r2, #1
|
|
8008be8: 4619 mov r1, r3
|
|
8008bea: 6878 ldr r0, [r7, #4]
|
|
8008bec: f001 fc14 bl 800a418 <USBD_CtlSendData>
|
|
break;
|
|
8008bf0: e006 b.n 8008c00 <USBD_HID_Setup+0xc4>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008bf2: 6839 ldr r1, [r7, #0]
|
|
8008bf4: 6878 ldr r0, [r7, #4]
|
|
8008bf6: f001 fb92 bl 800a31e <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8008bfa: 2303 movs r3, #3
|
|
8008bfc: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8008bfe: bf00 nop
|
|
}
|
|
break;
|
|
8008c00: e09a b.n 8008d38 <USBD_HID_Setup+0x1fc>
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
8008c02: 683b ldr r3, [r7, #0]
|
|
8008c04: 785b ldrb r3, [r3, #1]
|
|
8008c06: 2b0b cmp r3, #11
|
|
8008c08: f200 8086 bhi.w 8008d18 <USBD_HID_Setup+0x1dc>
|
|
8008c0c: a201 add r2, pc, #4 @ (adr r2, 8008c14 <USBD_HID_Setup+0xd8>)
|
|
8008c0e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8008c12: bf00 nop
|
|
8008c14: 08008c45 .word 0x08008c45
|
|
8008c18: 08008d27 .word 0x08008d27
|
|
8008c1c: 08008d19 .word 0x08008d19
|
|
8008c20: 08008d19 .word 0x08008d19
|
|
8008c24: 08008d19 .word 0x08008d19
|
|
8008c28: 08008d19 .word 0x08008d19
|
|
8008c2c: 08008c6f .word 0x08008c6f
|
|
8008c30: 08008d19 .word 0x08008d19
|
|
8008c34: 08008d19 .word 0x08008d19
|
|
8008c38: 08008d19 .word 0x08008d19
|
|
8008c3c: 08008cc7 .word 0x08008cc7
|
|
8008c40: 08008cf1 .word 0x08008cf1
|
|
{
|
|
case USB_REQ_GET_STATUS:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008c44: 687b ldr r3, [r7, #4]
|
|
8008c46: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008c4a: b2db uxtb r3, r3
|
|
8008c4c: 2b03 cmp r3, #3
|
|
8008c4e: d107 bne.n 8008c60 <USBD_HID_Setup+0x124>
|
|
{
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
|
|
8008c50: f107 030a add.w r3, r7, #10
|
|
8008c54: 2202 movs r2, #2
|
|
8008c56: 4619 mov r1, r3
|
|
8008c58: 6878 ldr r0, [r7, #4]
|
|
8008c5a: f001 fbdd bl 800a418 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
8008c5e: e063 b.n 8008d28 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
8008c60: 6839 ldr r1, [r7, #0]
|
|
8008c62: 6878 ldr r0, [r7, #4]
|
|
8008c64: f001 fb5b bl 800a31e <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8008c68: 2303 movs r3, #3
|
|
8008c6a: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8008c6c: e05c b.n 8008d28 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
if ((req->wValue >> 8) == HID_REPORT_DESC)
|
|
8008c6e: 683b ldr r3, [r7, #0]
|
|
8008c70: 885b ldrh r3, [r3, #2]
|
|
8008c72: 0a1b lsrs r3, r3, #8
|
|
8008c74: b29b uxth r3, r3
|
|
8008c76: 2b22 cmp r3, #34 @ 0x22
|
|
8008c78: d108 bne.n 8008c8c <USBD_HID_Setup+0x150>
|
|
{
|
|
len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength);
|
|
8008c7a: 683b ldr r3, [r7, #0]
|
|
8008c7c: 88db ldrh r3, [r3, #6]
|
|
8008c7e: 2b2d cmp r3, #45 @ 0x2d
|
|
8008c80: bf28 it cs
|
|
8008c82: 232d movcs r3, #45 @ 0x2d
|
|
8008c84: 82bb strh r3, [r7, #20]
|
|
pbuf = HID_MOUSE_ReportDesc;
|
|
8008c86: 4b2f ldr r3, [pc, #188] @ (8008d44 <USBD_HID_Setup+0x208>)
|
|
8008c88: 613b str r3, [r7, #16]
|
|
8008c8a: e015 b.n 8008cb8 <USBD_HID_Setup+0x17c>
|
|
}
|
|
else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE)
|
|
8008c8c: 683b ldr r3, [r7, #0]
|
|
8008c8e: 885b ldrh r3, [r3, #2]
|
|
8008c90: 0a1b lsrs r3, r3, #8
|
|
8008c92: b29b uxth r3, r3
|
|
8008c94: 2b21 cmp r3, #33 @ 0x21
|
|
8008c96: d108 bne.n 8008caa <USBD_HID_Setup+0x16e>
|
|
{
|
|
pbuf = USBD_HID_Desc;
|
|
8008c98: 4b2b ldr r3, [pc, #172] @ (8008d48 <USBD_HID_Setup+0x20c>)
|
|
8008c9a: 613b str r3, [r7, #16]
|
|
len = MIN(USB_HID_DESC_SIZ, req->wLength);
|
|
8008c9c: 683b ldr r3, [r7, #0]
|
|
8008c9e: 88db ldrh r3, [r3, #6]
|
|
8008ca0: 2b09 cmp r3, #9
|
|
8008ca2: bf28 it cs
|
|
8008ca4: 2309 movcs r3, #9
|
|
8008ca6: 82bb strh r3, [r7, #20]
|
|
8008ca8: e006 b.n 8008cb8 <USBD_HID_Setup+0x17c>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008caa: 6839 ldr r1, [r7, #0]
|
|
8008cac: 6878 ldr r0, [r7, #4]
|
|
8008cae: f001 fb36 bl 800a31e <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8008cb2: 2303 movs r3, #3
|
|
8008cb4: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8008cb6: e037 b.n 8008d28 <USBD_HID_Setup+0x1ec>
|
|
}
|
|
(void)USBD_CtlSendData(pdev, pbuf, len);
|
|
8008cb8: 8abb ldrh r3, [r7, #20]
|
|
8008cba: 461a mov r2, r3
|
|
8008cbc: 6939 ldr r1, [r7, #16]
|
|
8008cbe: 6878 ldr r0, [r7, #4]
|
|
8008cc0: f001 fbaa bl 800a418 <USBD_CtlSendData>
|
|
break;
|
|
8008cc4: e030 b.n 8008d28 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_GET_INTERFACE :
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008cc6: 687b ldr r3, [r7, #4]
|
|
8008cc8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008ccc: b2db uxtb r3, r3
|
|
8008cce: 2b03 cmp r3, #3
|
|
8008cd0: d107 bne.n 8008ce2 <USBD_HID_Setup+0x1a6>
|
|
{
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U);
|
|
8008cd2: 68fb ldr r3, [r7, #12]
|
|
8008cd4: 3308 adds r3, #8
|
|
8008cd6: 2201 movs r2, #1
|
|
8008cd8: 4619 mov r1, r3
|
|
8008cda: 6878 ldr r0, [r7, #4]
|
|
8008cdc: f001 fb9c bl 800a418 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
8008ce0: e022 b.n 8008d28 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
8008ce2: 6839 ldr r1, [r7, #0]
|
|
8008ce4: 6878 ldr r0, [r7, #4]
|
|
8008ce6: f001 fb1a bl 800a31e <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8008cea: 2303 movs r3, #3
|
|
8008cec: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8008cee: e01b b.n 8008d28 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_SET_INTERFACE:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008cf0: 687b ldr r3, [r7, #4]
|
|
8008cf2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008cf6: b2db uxtb r3, r3
|
|
8008cf8: 2b03 cmp r3, #3
|
|
8008cfa: d106 bne.n 8008d0a <USBD_HID_Setup+0x1ce>
|
|
{
|
|
hhid->AltSetting = (uint8_t)(req->wValue);
|
|
8008cfc: 683b ldr r3, [r7, #0]
|
|
8008cfe: 885b ldrh r3, [r3, #2]
|
|
8008d00: b2db uxtb r3, r3
|
|
8008d02: 461a mov r2, r3
|
|
8008d04: 68fb ldr r3, [r7, #12]
|
|
8008d06: 609a str r2, [r3, #8]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
8008d08: e00e b.n 8008d28 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
8008d0a: 6839 ldr r1, [r7, #0]
|
|
8008d0c: 6878 ldr r0, [r7, #4]
|
|
8008d0e: f001 fb06 bl 800a31e <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8008d12: 2303 movs r3, #3
|
|
8008d14: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8008d16: e007 b.n 8008d28 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
break;
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008d18: 6839 ldr r1, [r7, #0]
|
|
8008d1a: 6878 ldr r0, [r7, #4]
|
|
8008d1c: f001 faff bl 800a31e <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8008d20: 2303 movs r3, #3
|
|
8008d22: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8008d24: e000 b.n 8008d28 <USBD_HID_Setup+0x1ec>
|
|
break;
|
|
8008d26: bf00 nop
|
|
}
|
|
break;
|
|
8008d28: e006 b.n 8008d38 <USBD_HID_Setup+0x1fc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008d2a: 6839 ldr r1, [r7, #0]
|
|
8008d2c: 6878 ldr r0, [r7, #4]
|
|
8008d2e: f001 faf6 bl 800a31e <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8008d32: 2303 movs r3, #3
|
|
8008d34: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8008d36: bf00 nop
|
|
}
|
|
|
|
return (uint8_t)ret;
|
|
8008d38: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8008d3a: 4618 mov r0, r3
|
|
8008d3c: 3718 adds r7, #24
|
|
8008d3e: 46bd mov sp, r7
|
|
8008d40: bd80 pop {r7, pc}
|
|
8008d42: bf00 nop
|
|
8008d44: 20000110 .word 0x20000110
|
|
8008d48: 200000f8 .word 0x200000f8
|
|
|
|
08008d4c <USBD_HID_SendReport>:
|
|
uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId)
|
|
{
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId];
|
|
#else
|
|
uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
|
|
{
|
|
8008d4c: b580 push {r7, lr}
|
|
8008d4e: b086 sub sp, #24
|
|
8008d50: af00 add r7, sp, #0
|
|
8008d52: 60f8 str r0, [r7, #12]
|
|
8008d54: 60b9 str r1, [r7, #8]
|
|
8008d56: 4613 mov r3, r2
|
|
8008d58: 80fb strh r3, [r7, #6]
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
8008d5a: 68fb ldr r3, [r7, #12]
|
|
8008d5c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008d60: 68fb ldr r3, [r7, #12]
|
|
8008d62: 32b0 adds r2, #176 @ 0xb0
|
|
8008d64: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008d68: 617b str r3, [r7, #20]
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (hhid == NULL)
|
|
8008d6a: 697b ldr r3, [r7, #20]
|
|
8008d6c: 2b00 cmp r3, #0
|
|
8008d6e: d101 bne.n 8008d74 <USBD_HID_SendReport+0x28>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
8008d70: 2303 movs r3, #3
|
|
8008d72: e014 b.n 8008d9e <USBD_HID_SendReport+0x52>
|
|
#ifdef USE_USBD_COMPOSITE
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008d74: 68fb ldr r3, [r7, #12]
|
|
8008d76: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008d7a: b2db uxtb r3, r3
|
|
8008d7c: 2b03 cmp r3, #3
|
|
8008d7e: d10d bne.n 8008d9c <USBD_HID_SendReport+0x50>
|
|
{
|
|
if (hhid->state == USBD_HID_IDLE)
|
|
8008d80: 697b ldr r3, [r7, #20]
|
|
8008d82: 7b1b ldrb r3, [r3, #12]
|
|
8008d84: 2b00 cmp r3, #0
|
|
8008d86: d109 bne.n 8008d9c <USBD_HID_SendReport+0x50>
|
|
{
|
|
hhid->state = USBD_HID_BUSY;
|
|
8008d88: 697b ldr r3, [r7, #20]
|
|
8008d8a: 2201 movs r2, #1
|
|
8008d8c: 731a strb r2, [r3, #12]
|
|
(void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len);
|
|
8008d8e: 4b06 ldr r3, [pc, #24] @ (8008da8 <USBD_HID_SendReport+0x5c>)
|
|
8008d90: 7819 ldrb r1, [r3, #0]
|
|
8008d92: 88fb ldrh r3, [r7, #6]
|
|
8008d94: 68ba ldr r2, [r7, #8]
|
|
8008d96: 68f8 ldr r0, [r7, #12]
|
|
8008d98: f001 ff7d bl 800ac96 <USBD_LL_Transmit>
|
|
}
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
8008d9c: 2300 movs r3, #0
|
|
}
|
|
8008d9e: 4618 mov r0, r3
|
|
8008da0: 3718 adds r7, #24
|
|
8008da2: 46bd mov sp, r7
|
|
8008da4: bd80 pop {r7, pc}
|
|
8008da6: bf00 nop
|
|
8008da8: 2000013d .word 0x2000013d
|
|
|
|
08008dac <USBD_HID_GetFSCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length)
|
|
{
|
|
8008dac: b580 push {r7, lr}
|
|
8008dae: b084 sub sp, #16
|
|
8008db0: af00 add r7, sp, #0
|
|
8008db2: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
8008db4: 2181 movs r1, #129 @ 0x81
|
|
8008db6: 4809 ldr r0, [pc, #36] @ (8008ddc <USBD_HID_GetFSCfgDesc+0x30>)
|
|
8008db8: f000 fc4e bl 8009658 <USBD_GetEpDesc>
|
|
8008dbc: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
8008dbe: 68fb ldr r3, [r7, #12]
|
|
8008dc0: 2b00 cmp r3, #0
|
|
8008dc2: d002 beq.n 8008dca <USBD_HID_GetFSCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_FS_BINTERVAL;
|
|
8008dc4: 68fb ldr r3, [r7, #12]
|
|
8008dc6: 220a movs r2, #10
|
|
8008dc8: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
8008dca: 687b ldr r3, [r7, #4]
|
|
8008dcc: 2222 movs r2, #34 @ 0x22
|
|
8008dce: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
8008dd0: 4b02 ldr r3, [pc, #8] @ (8008ddc <USBD_HID_GetFSCfgDesc+0x30>)
|
|
}
|
|
8008dd2: 4618 mov r0, r3
|
|
8008dd4: 3710 adds r7, #16
|
|
8008dd6: 46bd mov sp, r7
|
|
8008dd8: bd80 pop {r7, pc}
|
|
8008dda: bf00 nop
|
|
8008ddc: 200000d4 .word 0x200000d4
|
|
|
|
08008de0 <USBD_HID_GetHSCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length)
|
|
{
|
|
8008de0: b580 push {r7, lr}
|
|
8008de2: b084 sub sp, #16
|
|
8008de4: af00 add r7, sp, #0
|
|
8008de6: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
8008de8: 2181 movs r1, #129 @ 0x81
|
|
8008dea: 4809 ldr r0, [pc, #36] @ (8008e10 <USBD_HID_GetHSCfgDesc+0x30>)
|
|
8008dec: f000 fc34 bl 8009658 <USBD_GetEpDesc>
|
|
8008df0: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
8008df2: 68fb ldr r3, [r7, #12]
|
|
8008df4: 2b00 cmp r3, #0
|
|
8008df6: d002 beq.n 8008dfe <USBD_HID_GetHSCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_HS_BINTERVAL;
|
|
8008df8: 68fb ldr r3, [r7, #12]
|
|
8008dfa: 2207 movs r2, #7
|
|
8008dfc: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
8008dfe: 687b ldr r3, [r7, #4]
|
|
8008e00: 2222 movs r2, #34 @ 0x22
|
|
8008e02: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
8008e04: 4b02 ldr r3, [pc, #8] @ (8008e10 <USBD_HID_GetHSCfgDesc+0x30>)
|
|
}
|
|
8008e06: 4618 mov r0, r3
|
|
8008e08: 3710 adds r7, #16
|
|
8008e0a: 46bd mov sp, r7
|
|
8008e0c: bd80 pop {r7, pc}
|
|
8008e0e: bf00 nop
|
|
8008e10: 200000d4 .word 0x200000d4
|
|
|
|
08008e14 <USBD_HID_GetOtherSpeedCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length)
|
|
{
|
|
8008e14: b580 push {r7, lr}
|
|
8008e16: b084 sub sp, #16
|
|
8008e18: af00 add r7, sp, #0
|
|
8008e1a: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
8008e1c: 2181 movs r1, #129 @ 0x81
|
|
8008e1e: 4809 ldr r0, [pc, #36] @ (8008e44 <USBD_HID_GetOtherSpeedCfgDesc+0x30>)
|
|
8008e20: f000 fc1a bl 8009658 <USBD_GetEpDesc>
|
|
8008e24: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
8008e26: 68fb ldr r3, [r7, #12]
|
|
8008e28: 2b00 cmp r3, #0
|
|
8008e2a: d002 beq.n 8008e32 <USBD_HID_GetOtherSpeedCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_FS_BINTERVAL;
|
|
8008e2c: 68fb ldr r3, [r7, #12]
|
|
8008e2e: 220a movs r2, #10
|
|
8008e30: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
8008e32: 687b ldr r3, [r7, #4]
|
|
8008e34: 2222 movs r2, #34 @ 0x22
|
|
8008e36: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
8008e38: 4b02 ldr r3, [pc, #8] @ (8008e44 <USBD_HID_GetOtherSpeedCfgDesc+0x30>)
|
|
}
|
|
8008e3a: 4618 mov r0, r3
|
|
8008e3c: 3710 adds r7, #16
|
|
8008e3e: 46bd mov sp, r7
|
|
8008e40: bd80 pop {r7, pc}
|
|
8008e42: bf00 nop
|
|
8008e44: 200000d4 .word 0x200000d4
|
|
|
|
08008e48 <USBD_HID_DataIn>:
|
|
* @param pdev: device instance
|
|
* @param epnum: endpoint index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
|
|
{
|
|
8008e48: b480 push {r7}
|
|
8008e4a: b083 sub sp, #12
|
|
8008e4c: af00 add r7, sp, #0
|
|
8008e4e: 6078 str r0, [r7, #4]
|
|
8008e50: 460b mov r3, r1
|
|
8008e52: 70fb strb r3, [r7, #3]
|
|
UNUSED(epnum);
|
|
/* Ensure that the FIFO is empty before a new transfer, this condition could
|
|
be caused by a new transfer before the end of the previous transfer */
|
|
((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE;
|
|
8008e54: 687b ldr r3, [r7, #4]
|
|
8008e56: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008e5a: 687b ldr r3, [r7, #4]
|
|
8008e5c: 32b0 adds r2, #176 @ 0xb0
|
|
8008e5e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008e62: 2200 movs r2, #0
|
|
8008e64: 731a strb r2, [r3, #12]
|
|
|
|
return (uint8_t)USBD_OK;
|
|
8008e66: 2300 movs r3, #0
|
|
}
|
|
8008e68: 4618 mov r0, r3
|
|
8008e6a: 370c adds r7, #12
|
|
8008e6c: 46bd mov sp, r7
|
|
8008e6e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008e72: 4770 bx lr
|
|
|
|
08008e74 <USBD_HID_GetDeviceQualifierDesc>:
|
|
* return Device Qualifier descriptor
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length)
|
|
{
|
|
8008e74: b480 push {r7}
|
|
8008e76: b083 sub sp, #12
|
|
8008e78: af00 add r7, sp, #0
|
|
8008e7a: 6078 str r0, [r7, #4]
|
|
*length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc);
|
|
8008e7c: 687b ldr r3, [r7, #4]
|
|
8008e7e: 220a movs r2, #10
|
|
8008e80: 801a strh r2, [r3, #0]
|
|
|
|
return USBD_HID_DeviceQualifierDesc;
|
|
8008e82: 4b03 ldr r3, [pc, #12] @ (8008e90 <USBD_HID_GetDeviceQualifierDesc+0x1c>)
|
|
}
|
|
8008e84: 4618 mov r0, r3
|
|
8008e86: 370c adds r7, #12
|
|
8008e88: 46bd mov sp, r7
|
|
8008e8a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008e8e: 4770 bx lr
|
|
8008e90: 20000104 .word 0x20000104
|
|
|
|
08008e94 <USBD_Init>:
|
|
* @param id: Low level core index
|
|
* @retval status: USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
|
|
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
|
|
{
|
|
8008e94: b580 push {r7, lr}
|
|
8008e96: b086 sub sp, #24
|
|
8008e98: af00 add r7, sp, #0
|
|
8008e9a: 60f8 str r0, [r7, #12]
|
|
8008e9c: 60b9 str r1, [r7, #8]
|
|
8008e9e: 4613 mov r3, r2
|
|
8008ea0: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef ret;
|
|
|
|
/* Check whether the USB Host handle is valid */
|
|
if (pdev == NULL)
|
|
8008ea2: 68fb ldr r3, [r7, #12]
|
|
8008ea4: 2b00 cmp r3, #0
|
|
8008ea6: d101 bne.n 8008eac <USBD_Init+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Device handle");
|
|
#endif /* (USBD_DEBUG_LEVEL > 1U) */
|
|
return USBD_FAIL;
|
|
8008ea8: 2303 movs r3, #3
|
|
8008eaa: e01f b.n 8008eec <USBD_Init+0x58>
|
|
pdev->NumClasses = 0;
|
|
pdev->classId = 0;
|
|
}
|
|
#else
|
|
/* Unlink previous class*/
|
|
pdev->pClass[0] = NULL;
|
|
8008eac: 68fb ldr r3, [r7, #12]
|
|
8008eae: 2200 movs r2, #0
|
|
8008eb0: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
pdev->pUserData[0] = NULL;
|
|
8008eb4: 68fb ldr r3, [r7, #12]
|
|
8008eb6: 2200 movs r2, #0
|
|
8008eb8: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
pdev->pConfDesc = NULL;
|
|
8008ebc: 68fb ldr r3, [r7, #12]
|
|
8008ebe: 2200 movs r2, #0
|
|
8008ec0: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
|
|
/* Assign USBD Descriptors */
|
|
if (pdesc != NULL)
|
|
8008ec4: 68bb ldr r3, [r7, #8]
|
|
8008ec6: 2b00 cmp r3, #0
|
|
8008ec8: d003 beq.n 8008ed2 <USBD_Init+0x3e>
|
|
{
|
|
pdev->pDesc = pdesc;
|
|
8008eca: 68fb ldr r3, [r7, #12]
|
|
8008ecc: 68ba ldr r2, [r7, #8]
|
|
8008ece: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
|
|
}
|
|
|
|
/* Set Device initial State */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8008ed2: 68fb ldr r3, [r7, #12]
|
|
8008ed4: 2201 movs r2, #1
|
|
8008ed6: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->id = id;
|
|
8008eda: 68fb ldr r3, [r7, #12]
|
|
8008edc: 79fa ldrb r2, [r7, #7]
|
|
8008ede: 701a strb r2, [r3, #0]
|
|
|
|
/* Initialize low level driver */
|
|
ret = USBD_LL_Init(pdev);
|
|
8008ee0: 68f8 ldr r0, [r7, #12]
|
|
8008ee2: f001 fda3 bl 800aa2c <USBD_LL_Init>
|
|
8008ee6: 4603 mov r3, r0
|
|
8008ee8: 75fb strb r3, [r7, #23]
|
|
|
|
return ret;
|
|
8008eea: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8008eec: 4618 mov r0, r3
|
|
8008eee: 3718 adds r7, #24
|
|
8008ef0: 46bd mov sp, r7
|
|
8008ef2: bd80 pop {r7, pc}
|
|
|
|
08008ef4 <USBD_RegisterClass>:
|
|
* @param pdev: Device Handle
|
|
* @param pclass: Class handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
|
|
{
|
|
8008ef4: b580 push {r7, lr}
|
|
8008ef6: b084 sub sp, #16
|
|
8008ef8: af00 add r7, sp, #0
|
|
8008efa: 6078 str r0, [r7, #4]
|
|
8008efc: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
8008efe: 2300 movs r3, #0
|
|
8008f00: 81fb strh r3, [r7, #14]
|
|
|
|
if (pclass == NULL)
|
|
8008f02: 683b ldr r3, [r7, #0]
|
|
8008f04: 2b00 cmp r3, #0
|
|
8008f06: d101 bne.n 8008f0c <USBD_RegisterClass+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Class handle");
|
|
#endif /* (USBD_DEBUG_LEVEL > 1U) */
|
|
return USBD_FAIL;
|
|
8008f08: 2303 movs r3, #3
|
|
8008f0a: e025 b.n 8008f58 <USBD_RegisterClass+0x64>
|
|
}
|
|
|
|
/* link the class to the USB Device handle */
|
|
pdev->pClass[0] = pclass;
|
|
8008f0c: 687b ldr r3, [r7, #4]
|
|
8008f0e: 683a ldr r2, [r7, #0]
|
|
8008f10: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL)
|
|
{
|
|
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len);
|
|
}
|
|
#else /* Default USE_USB_FS */
|
|
if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL)
|
|
8008f14: 687b ldr r3, [r7, #4]
|
|
8008f16: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008f1a: 687b ldr r3, [r7, #4]
|
|
8008f1c: 32ae adds r2, #174 @ 0xae
|
|
8008f1e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008f22: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8008f24: 2b00 cmp r3, #0
|
|
8008f26: d00f beq.n 8008f48 <USBD_RegisterClass+0x54>
|
|
{
|
|
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len);
|
|
8008f28: 687b ldr r3, [r7, #4]
|
|
8008f2a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008f2e: 687b ldr r3, [r7, #4]
|
|
8008f30: 32ae adds r2, #174 @ 0xae
|
|
8008f32: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008f36: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8008f38: f107 020e add.w r2, r7, #14
|
|
8008f3c: 4610 mov r0, r2
|
|
8008f3e: 4798 blx r3
|
|
8008f40: 4602 mov r2, r0
|
|
8008f42: 687b ldr r3, [r7, #4]
|
|
8008f44: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
}
|
|
#endif /* USE_USB_FS */
|
|
|
|
/* Increment the NumClasses */
|
|
pdev->NumClasses++;
|
|
8008f48: 687b ldr r3, [r7, #4]
|
|
8008f4a: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
8008f4e: 1c5a adds r2, r3, #1
|
|
8008f50: 687b ldr r3, [r7, #4]
|
|
8008f52: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8
|
|
|
|
return USBD_OK;
|
|
8008f56: 2300 movs r3, #0
|
|
}
|
|
8008f58: 4618 mov r0, r3
|
|
8008f5a: 3710 adds r7, #16
|
|
8008f5c: 46bd mov sp, r7
|
|
8008f5e: bd80 pop {r7, pc}
|
|
|
|
08008f60 <USBD_Start>:
|
|
* Start the USB Device Core.
|
|
* @param pdev: Device Handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008f60: b580 push {r7, lr}
|
|
8008f62: b082 sub sp, #8
|
|
8008f64: af00 add r7, sp, #0
|
|
8008f66: 6078 str r0, [r7, #4]
|
|
#ifdef USE_USBD_COMPOSITE
|
|
pdev->classId = 0U;
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Start the low level driver */
|
|
return USBD_LL_Start(pdev);
|
|
8008f68: 6878 ldr r0, [r7, #4]
|
|
8008f6a: f001 fdab bl 800aac4 <USBD_LL_Start>
|
|
8008f6e: 4603 mov r3, r0
|
|
}
|
|
8008f70: 4618 mov r0, r3
|
|
8008f72: 3708 adds r7, #8
|
|
8008f74: 46bd mov sp, r7
|
|
8008f76: bd80 pop {r7, pc}
|
|
|
|
08008f78 <USBD_RunTestMode>:
|
|
* Launch test mode process
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008f78: b480 push {r7}
|
|
8008f7a: b083 sub sp, #12
|
|
8008f7c: af00 add r7, sp, #0
|
|
8008f7e: 6078 str r0, [r7, #4]
|
|
return ret;
|
|
#else
|
|
/* Prevent unused argument compilation warning */
|
|
UNUSED(pdev);
|
|
|
|
return USBD_OK;
|
|
8008f80: 2300 movs r3, #0
|
|
#endif /* USBD_HS_TESTMODE_ENABLE */
|
|
}
|
|
8008f82: 4618 mov r0, r3
|
|
8008f84: 370c adds r7, #12
|
|
8008f86: 46bd mov sp, r7
|
|
8008f88: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008f8c: 4770 bx lr
|
|
|
|
08008f8e <USBD_SetClassConfig>:
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
|
|
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8008f8e: b580 push {r7, lr}
|
|
8008f90: b084 sub sp, #16
|
|
8008f92: af00 add r7, sp, #0
|
|
8008f94: 6078 str r0, [r7, #4]
|
|
8008f96: 460b mov r3, r1
|
|
8008f98: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8008f9a: 2300 movs r3, #0
|
|
8008f9c: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
8008f9e: 687b ldr r3, [r7, #4]
|
|
8008fa0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008fa4: 2b00 cmp r3, #0
|
|
8008fa6: d009 beq.n 8008fbc <USBD_SetClassConfig+0x2e>
|
|
{
|
|
/* Set configuration and Start the Class */
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx);
|
|
8008fa8: 687b ldr r3, [r7, #4]
|
|
8008faa: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008fae: 681b ldr r3, [r3, #0]
|
|
8008fb0: 78fa ldrb r2, [r7, #3]
|
|
8008fb2: 4611 mov r1, r2
|
|
8008fb4: 6878 ldr r0, [r7, #4]
|
|
8008fb6: 4798 blx r3
|
|
8008fb8: 4603 mov r3, r0
|
|
8008fba: 73fb strb r3, [r7, #15]
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8008fbc: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008fbe: 4618 mov r0, r3
|
|
8008fc0: 3710 adds r7, #16
|
|
8008fc2: 46bd mov sp, r7
|
|
8008fc4: bd80 pop {r7, pc}
|
|
|
|
08008fc6 <USBD_ClrClassConfig>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8008fc6: b580 push {r7, lr}
|
|
8008fc8: b084 sub sp, #16
|
|
8008fca: af00 add r7, sp, #0
|
|
8008fcc: 6078 str r0, [r7, #4]
|
|
8008fce: 460b mov r3, r1
|
|
8008fd0: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8008fd2: 2300 movs r3, #0
|
|
8008fd4: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
/* Clear configuration and De-initialize the Class process */
|
|
if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U)
|
|
8008fd6: 687b ldr r3, [r7, #4]
|
|
8008fd8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008fdc: 685b ldr r3, [r3, #4]
|
|
8008fde: 78fa ldrb r2, [r7, #3]
|
|
8008fe0: 4611 mov r1, r2
|
|
8008fe2: 6878 ldr r0, [r7, #4]
|
|
8008fe4: 4798 blx r3
|
|
8008fe6: 4603 mov r3, r0
|
|
8008fe8: 2b00 cmp r3, #0
|
|
8008fea: d001 beq.n 8008ff0 <USBD_ClrClassConfig+0x2a>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8008fec: 2303 movs r3, #3
|
|
8008fee: 73fb strb r3, [r7, #15]
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8008ff0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008ff2: 4618 mov r0, r3
|
|
8008ff4: 3710 adds r7, #16
|
|
8008ff6: 46bd mov sp, r7
|
|
8008ff8: bd80 pop {r7, pc}
|
|
|
|
08008ffa <USBD_LL_SetupStage>:
|
|
* @param pdev: device instance
|
|
* @param psetup: setup packet buffer pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
|
|
{
|
|
8008ffa: b580 push {r7, lr}
|
|
8008ffc: b084 sub sp, #16
|
|
8008ffe: af00 add r7, sp, #0
|
|
8009000: 6078 str r0, [r7, #4]
|
|
8009002: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret;
|
|
|
|
USBD_ParseSetupRequest(&pdev->request, psetup);
|
|
8009004: 687b ldr r3, [r7, #4]
|
|
8009006: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
800900a: 6839 ldr r1, [r7, #0]
|
|
800900c: 4618 mov r0, r3
|
|
800900e: f001 f94c bl 800a2aa <USBD_ParseSetupRequest>
|
|
|
|
pdev->ep0_state = USBD_EP0_SETUP;
|
|
8009012: 687b ldr r3, [r7, #4]
|
|
8009014: 2201 movs r2, #1
|
|
8009016: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
pdev->ep0_data_len = pdev->request.wLength;
|
|
800901a: 687b ldr r3, [r7, #4]
|
|
800901c: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0
|
|
8009020: 461a mov r2, r3
|
|
8009022: 687b ldr r3, [r7, #4]
|
|
8009024: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
8009028: 687b ldr r3, [r7, #4]
|
|
800902a: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
800902e: f003 031f and.w r3, r3, #31
|
|
8009032: 2b02 cmp r3, #2
|
|
8009034: d01a beq.n 800906c <USBD_LL_SetupStage+0x72>
|
|
8009036: 2b02 cmp r3, #2
|
|
8009038: d822 bhi.n 8009080 <USBD_LL_SetupStage+0x86>
|
|
800903a: 2b00 cmp r3, #0
|
|
800903c: d002 beq.n 8009044 <USBD_LL_SetupStage+0x4a>
|
|
800903e: 2b01 cmp r3, #1
|
|
8009040: d00a beq.n 8009058 <USBD_LL_SetupStage+0x5e>
|
|
8009042: e01d b.n 8009080 <USBD_LL_SetupStage+0x86>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
ret = USBD_StdDevReq(pdev, &pdev->request);
|
|
8009044: 687b ldr r3, [r7, #4]
|
|
8009046: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
800904a: 4619 mov r1, r3
|
|
800904c: 6878 ldr r0, [r7, #4]
|
|
800904e: f000 fb77 bl 8009740 <USBD_StdDevReq>
|
|
8009052: 4603 mov r3, r0
|
|
8009054: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009056: e020 b.n 800909a <USBD_LL_SetupStage+0xa0>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
ret = USBD_StdItfReq(pdev, &pdev->request);
|
|
8009058: 687b ldr r3, [r7, #4]
|
|
800905a: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
800905e: 4619 mov r1, r3
|
|
8009060: 6878 ldr r0, [r7, #4]
|
|
8009062: f000 fbdf bl 8009824 <USBD_StdItfReq>
|
|
8009066: 4603 mov r3, r0
|
|
8009068: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800906a: e016 b.n 800909a <USBD_LL_SetupStage+0xa0>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
ret = USBD_StdEPReq(pdev, &pdev->request);
|
|
800906c: 687b ldr r3, [r7, #4]
|
|
800906e: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8009072: 4619 mov r1, r3
|
|
8009074: 6878 ldr r0, [r7, #4]
|
|
8009076: f000 fc41 bl 80098fc <USBD_StdEPReq>
|
|
800907a: 4603 mov r3, r0
|
|
800907c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800907e: e00c b.n 800909a <USBD_LL_SetupStage+0xa0>
|
|
|
|
default:
|
|
ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
|
|
8009080: 687b ldr r3, [r7, #4]
|
|
8009082: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8009086: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
800908a: b2db uxtb r3, r3
|
|
800908c: 4619 mov r1, r3
|
|
800908e: 6878 ldr r0, [r7, #4]
|
|
8009090: f001 fd78 bl 800ab84 <USBD_LL_StallEP>
|
|
8009094: 4603 mov r3, r0
|
|
8009096: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009098: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
800909a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800909c: 4618 mov r0, r3
|
|
800909e: 3710 adds r7, #16
|
|
80090a0: 46bd mov sp, r7
|
|
80090a2: bd80 pop {r7, pc}
|
|
|
|
080090a4 <USBD_LL_DataOutStage>:
|
|
* @param pdata: data pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
80090a4: b580 push {r7, lr}
|
|
80090a6: b086 sub sp, #24
|
|
80090a8: af00 add r7, sp, #0
|
|
80090aa: 60f8 str r0, [r7, #12]
|
|
80090ac: 460b mov r3, r1
|
|
80090ae: 607a str r2, [r7, #4]
|
|
80090b0: 72fb strb r3, [r7, #11]
|
|
USBD_EndpointTypeDef *pep;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80090b2: 2300 movs r3, #0
|
|
80090b4: 75fb strb r3, [r7, #23]
|
|
uint8_t idx;
|
|
|
|
UNUSED(pdata);
|
|
|
|
if (epnum == 0U)
|
|
80090b6: 7afb ldrb r3, [r7, #11]
|
|
80090b8: 2b00 cmp r3, #0
|
|
80090ba: d177 bne.n 80091ac <USBD_LL_DataOutStage+0x108>
|
|
{
|
|
pep = &pdev->ep_out[0];
|
|
80090bc: 68fb ldr r3, [r7, #12]
|
|
80090be: f503 73aa add.w r3, r3, #340 @ 0x154
|
|
80090c2: 613b str r3, [r7, #16]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
|
|
80090c4: 68fb ldr r3, [r7, #12]
|
|
80090c6: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
80090ca: 2b03 cmp r3, #3
|
|
80090cc: f040 80a1 bne.w 8009212 <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
80090d0: 693b ldr r3, [r7, #16]
|
|
80090d2: 685b ldr r3, [r3, #4]
|
|
80090d4: 693a ldr r2, [r7, #16]
|
|
80090d6: 8992 ldrh r2, [r2, #12]
|
|
80090d8: 4293 cmp r3, r2
|
|
80090da: d91c bls.n 8009116 <USBD_LL_DataOutStage+0x72>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
80090dc: 693b ldr r3, [r7, #16]
|
|
80090de: 685b ldr r3, [r3, #4]
|
|
80090e0: 693a ldr r2, [r7, #16]
|
|
80090e2: 8992 ldrh r2, [r2, #12]
|
|
80090e4: 1a9a subs r2, r3, r2
|
|
80090e6: 693b ldr r3, [r7, #16]
|
|
80090e8: 605a str r2, [r3, #4]
|
|
pep->pbuffer += pep->maxpacket;
|
|
80090ea: 693b ldr r3, [r7, #16]
|
|
80090ec: 691b ldr r3, [r3, #16]
|
|
80090ee: 693a ldr r2, [r7, #16]
|
|
80090f0: 8992 ldrh r2, [r2, #12]
|
|
80090f2: 441a add r2, r3
|
|
80090f4: 693b ldr r3, [r7, #16]
|
|
80090f6: 611a str r2, [r3, #16]
|
|
|
|
(void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket));
|
|
80090f8: 693b ldr r3, [r7, #16]
|
|
80090fa: 6919 ldr r1, [r3, #16]
|
|
80090fc: 693b ldr r3, [r7, #16]
|
|
80090fe: 899b ldrh r3, [r3, #12]
|
|
8009100: 461a mov r2, r3
|
|
8009102: 693b ldr r3, [r7, #16]
|
|
8009104: 685b ldr r3, [r3, #4]
|
|
8009106: 4293 cmp r3, r2
|
|
8009108: bf38 it cc
|
|
800910a: 4613 movcc r3, r2
|
|
800910c: 461a mov r2, r3
|
|
800910e: 68f8 ldr r0, [r7, #12]
|
|
8009110: f001 f9b1 bl 800a476 <USBD_CtlContinueRx>
|
|
8009114: e07d b.n 8009212 <USBD_LL_DataOutStage+0x16e>
|
|
}
|
|
else
|
|
{
|
|
/* Find the class ID relative to the current request */
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
8009116: 68fb ldr r3, [r7, #12]
|
|
8009118: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
800911c: f003 031f and.w r3, r3, #31
|
|
8009120: 2b02 cmp r3, #2
|
|
8009122: d014 beq.n 800914e <USBD_LL_DataOutStage+0xaa>
|
|
8009124: 2b02 cmp r3, #2
|
|
8009126: d81d bhi.n 8009164 <USBD_LL_DataOutStage+0xc0>
|
|
8009128: 2b00 cmp r3, #0
|
|
800912a: d002 beq.n 8009132 <USBD_LL_DataOutStage+0x8e>
|
|
800912c: 2b01 cmp r3, #1
|
|
800912e: d003 beq.n 8009138 <USBD_LL_DataOutStage+0x94>
|
|
8009130: e018 b.n 8009164 <USBD_LL_DataOutStage+0xc0>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
/* Device requests must be managed by the first instantiated class
|
|
(or duplicated by all classes for simplicity) */
|
|
idx = 0U;
|
|
8009132: 2300 movs r3, #0
|
|
8009134: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8009136: e018 b.n 800916a <USBD_LL_DataOutStage+0xc6>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex));
|
|
8009138: 68fb ldr r3, [r7, #12]
|
|
800913a: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
800913e: b2db uxtb r3, r3
|
|
8009140: 4619 mov r1, r3
|
|
8009142: 68f8 ldr r0, [r7, #12]
|
|
8009144: f000 fa6e bl 8009624 <USBD_CoreFindIF>
|
|
8009148: 4603 mov r3, r0
|
|
800914a: 75bb strb r3, [r7, #22]
|
|
break;
|
|
800914c: e00d b.n 800916a <USBD_LL_DataOutStage+0xc6>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex));
|
|
800914e: 68fb ldr r3, [r7, #12]
|
|
8009150: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
8009154: b2db uxtb r3, r3
|
|
8009156: 4619 mov r1, r3
|
|
8009158: 68f8 ldr r0, [r7, #12]
|
|
800915a: f000 fa70 bl 800963e <USBD_CoreFindEP>
|
|
800915e: 4603 mov r3, r0
|
|
8009160: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8009162: e002 b.n 800916a <USBD_LL_DataOutStage+0xc6>
|
|
|
|
default:
|
|
/* Back to the first class in case of doubt */
|
|
idx = 0U;
|
|
8009164: 2300 movs r3, #0
|
|
8009166: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8009168: bf00 nop
|
|
}
|
|
|
|
if (idx < USBD_MAX_SUPPORTED_CLASS)
|
|
800916a: 7dbb ldrb r3, [r7, #22]
|
|
800916c: 2b00 cmp r3, #0
|
|
800916e: d119 bne.n 80091a4 <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
/* Setup the class ID and route the request to the relative class function */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8009170: 68fb ldr r3, [r7, #12]
|
|
8009172: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009176: b2db uxtb r3, r3
|
|
8009178: 2b03 cmp r3, #3
|
|
800917a: d113 bne.n 80091a4 <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
if (pdev->pClass[idx]->EP0_RxReady != NULL)
|
|
800917c: 7dba ldrb r2, [r7, #22]
|
|
800917e: 68fb ldr r3, [r7, #12]
|
|
8009180: 32ae adds r2, #174 @ 0xae
|
|
8009182: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009186: 691b ldr r3, [r3, #16]
|
|
8009188: 2b00 cmp r3, #0
|
|
800918a: d00b beq.n 80091a4 <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
pdev->classId = idx;
|
|
800918c: 7dba ldrb r2, [r7, #22]
|
|
800918e: 68fb ldr r3, [r7, #12]
|
|
8009190: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
pdev->pClass[idx]->EP0_RxReady(pdev);
|
|
8009194: 7dba ldrb r2, [r7, #22]
|
|
8009196: 68fb ldr r3, [r7, #12]
|
|
8009198: 32ae adds r2, #174 @ 0xae
|
|
800919a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800919e: 691b ldr r3, [r3, #16]
|
|
80091a0: 68f8 ldr r0, [r7, #12]
|
|
80091a2: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80091a4: 68f8 ldr r0, [r7, #12]
|
|
80091a6: f001 f977 bl 800a498 <USBD_CtlSendStatus>
|
|
80091aa: e032 b.n 8009212 <USBD_LL_DataOutStage+0x16e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU));
|
|
80091ac: 7afb ldrb r3, [r7, #11]
|
|
80091ae: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
80091b2: b2db uxtb r3, r3
|
|
80091b4: 4619 mov r1, r3
|
|
80091b6: 68f8 ldr r0, [r7, #12]
|
|
80091b8: f000 fa41 bl 800963e <USBD_CoreFindEP>
|
|
80091bc: 4603 mov r3, r0
|
|
80091be: 75bb strb r3, [r7, #22]
|
|
|
|
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
80091c0: 7dbb ldrb r3, [r7, #22]
|
|
80091c2: 2bff cmp r3, #255 @ 0xff
|
|
80091c4: d025 beq.n 8009212 <USBD_LL_DataOutStage+0x16e>
|
|
80091c6: 7dbb ldrb r3, [r7, #22]
|
|
80091c8: 2b00 cmp r3, #0
|
|
80091ca: d122 bne.n 8009212 <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80091cc: 68fb ldr r3, [r7, #12]
|
|
80091ce: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80091d2: b2db uxtb r3, r3
|
|
80091d4: 2b03 cmp r3, #3
|
|
80091d6: d117 bne.n 8009208 <USBD_LL_DataOutStage+0x164>
|
|
{
|
|
if (pdev->pClass[idx]->DataOut != NULL)
|
|
80091d8: 7dba ldrb r2, [r7, #22]
|
|
80091da: 68fb ldr r3, [r7, #12]
|
|
80091dc: 32ae adds r2, #174 @ 0xae
|
|
80091de: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80091e2: 699b ldr r3, [r3, #24]
|
|
80091e4: 2b00 cmp r3, #0
|
|
80091e6: d00f beq.n 8009208 <USBD_LL_DataOutStage+0x164>
|
|
{
|
|
pdev->classId = idx;
|
|
80091e8: 7dba ldrb r2, [r7, #22]
|
|
80091ea: 68fb ldr r3, [r7, #12]
|
|
80091ec: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum);
|
|
80091f0: 7dba ldrb r2, [r7, #22]
|
|
80091f2: 68fb ldr r3, [r7, #12]
|
|
80091f4: 32ae adds r2, #174 @ 0xae
|
|
80091f6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80091fa: 699b ldr r3, [r3, #24]
|
|
80091fc: 7afa ldrb r2, [r7, #11]
|
|
80091fe: 4611 mov r1, r2
|
|
8009200: 68f8 ldr r0, [r7, #12]
|
|
8009202: 4798 blx r3
|
|
8009204: 4603 mov r3, r0
|
|
8009206: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
if (ret != USBD_OK)
|
|
8009208: 7dfb ldrb r3, [r7, #23]
|
|
800920a: 2b00 cmp r3, #0
|
|
800920c: d001 beq.n 8009212 <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
return ret;
|
|
800920e: 7dfb ldrb r3, [r7, #23]
|
|
8009210: e000 b.n 8009214 <USBD_LL_DataOutStage+0x170>
|
|
}
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8009212: 2300 movs r3, #0
|
|
}
|
|
8009214: 4618 mov r0, r3
|
|
8009216: 3718 adds r7, #24
|
|
8009218: 46bd mov sp, r7
|
|
800921a: bd80 pop {r7, pc}
|
|
|
|
0800921c <USBD_LL_DataInStage>:
|
|
* @param pdata: data pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
800921c: b580 push {r7, lr}
|
|
800921e: b086 sub sp, #24
|
|
8009220: af00 add r7, sp, #0
|
|
8009222: 60f8 str r0, [r7, #12]
|
|
8009224: 460b mov r3, r1
|
|
8009226: 607a str r2, [r7, #4]
|
|
8009228: 72fb strb r3, [r7, #11]
|
|
USBD_StatusTypeDef ret;
|
|
uint8_t idx;
|
|
|
|
UNUSED(pdata);
|
|
|
|
if (epnum == 0U)
|
|
800922a: 7afb ldrb r3, [r7, #11]
|
|
800922c: 2b00 cmp r3, #0
|
|
800922e: d178 bne.n 8009322 <USBD_LL_DataInStage+0x106>
|
|
{
|
|
pep = &pdev->ep_in[0];
|
|
8009230: 68fb ldr r3, [r7, #12]
|
|
8009232: 3314 adds r3, #20
|
|
8009234: 613b str r3, [r7, #16]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_IN)
|
|
8009236: 68fb ldr r3, [r7, #12]
|
|
8009238: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
800923c: 2b02 cmp r3, #2
|
|
800923e: d163 bne.n 8009308 <USBD_LL_DataInStage+0xec>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
8009240: 693b ldr r3, [r7, #16]
|
|
8009242: 685b ldr r3, [r3, #4]
|
|
8009244: 693a ldr r2, [r7, #16]
|
|
8009246: 8992 ldrh r2, [r2, #12]
|
|
8009248: 4293 cmp r3, r2
|
|
800924a: d91c bls.n 8009286 <USBD_LL_DataInStage+0x6a>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
800924c: 693b ldr r3, [r7, #16]
|
|
800924e: 685b ldr r3, [r3, #4]
|
|
8009250: 693a ldr r2, [r7, #16]
|
|
8009252: 8992 ldrh r2, [r2, #12]
|
|
8009254: 1a9a subs r2, r3, r2
|
|
8009256: 693b ldr r3, [r7, #16]
|
|
8009258: 605a str r2, [r3, #4]
|
|
pep->pbuffer += pep->maxpacket;
|
|
800925a: 693b ldr r3, [r7, #16]
|
|
800925c: 691b ldr r3, [r3, #16]
|
|
800925e: 693a ldr r2, [r7, #16]
|
|
8009260: 8992 ldrh r2, [r2, #12]
|
|
8009262: 441a add r2, r3
|
|
8009264: 693b ldr r3, [r7, #16]
|
|
8009266: 611a str r2, [r3, #16]
|
|
|
|
(void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length);
|
|
8009268: 693b ldr r3, [r7, #16]
|
|
800926a: 6919 ldr r1, [r3, #16]
|
|
800926c: 693b ldr r3, [r7, #16]
|
|
800926e: 685b ldr r3, [r3, #4]
|
|
8009270: 461a mov r2, r3
|
|
8009272: 68f8 ldr r0, [r7, #12]
|
|
8009274: f001 f8ee bl 800a454 <USBD_CtlContinueSendData>
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8009278: 2300 movs r3, #0
|
|
800927a: 2200 movs r2, #0
|
|
800927c: 2100 movs r1, #0
|
|
800927e: 68f8 ldr r0, [r7, #12]
|
|
8009280: f001 fd2a bl 800acd8 <USBD_LL_PrepareReceive>
|
|
8009284: e040 b.n 8009308 <USBD_LL_DataInStage+0xec>
|
|
}
|
|
else
|
|
{
|
|
/* last packet is MPS multiple, so send ZLP packet */
|
|
if ((pep->maxpacket == pep->rem_length) &&
|
|
8009286: 693b ldr r3, [r7, #16]
|
|
8009288: 899b ldrh r3, [r3, #12]
|
|
800928a: 461a mov r2, r3
|
|
800928c: 693b ldr r3, [r7, #16]
|
|
800928e: 685b ldr r3, [r3, #4]
|
|
8009290: 429a cmp r2, r3
|
|
8009292: d11c bne.n 80092ce <USBD_LL_DataInStage+0xb2>
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
8009294: 693b ldr r3, [r7, #16]
|
|
8009296: 681b ldr r3, [r3, #0]
|
|
8009298: 693a ldr r2, [r7, #16]
|
|
800929a: 8992 ldrh r2, [r2, #12]
|
|
if ((pep->maxpacket == pep->rem_length) &&
|
|
800929c: 4293 cmp r3, r2
|
|
800929e: d316 bcc.n 80092ce <USBD_LL_DataInStage+0xb2>
|
|
(pep->total_length < pdev->ep0_data_len))
|
|
80092a0: 693b ldr r3, [r7, #16]
|
|
80092a2: 681a ldr r2, [r3, #0]
|
|
80092a4: 68fb ldr r3, [r7, #12]
|
|
80092a6: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
80092aa: 429a cmp r2, r3
|
|
80092ac: d20f bcs.n 80092ce <USBD_LL_DataInStage+0xb2>
|
|
{
|
|
(void)USBD_CtlContinueSendData(pdev, NULL, 0U);
|
|
80092ae: 2200 movs r2, #0
|
|
80092b0: 2100 movs r1, #0
|
|
80092b2: 68f8 ldr r0, [r7, #12]
|
|
80092b4: f001 f8ce bl 800a454 <USBD_CtlContinueSendData>
|
|
pdev->ep0_data_len = 0U;
|
|
80092b8: 68fb ldr r3, [r7, #12]
|
|
80092ba: 2200 movs r2, #0
|
|
80092bc: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
80092c0: 2300 movs r3, #0
|
|
80092c2: 2200 movs r2, #0
|
|
80092c4: 2100 movs r1, #0
|
|
80092c6: 68f8 ldr r0, [r7, #12]
|
|
80092c8: f001 fd06 bl 800acd8 <USBD_LL_PrepareReceive>
|
|
80092cc: e01c b.n 8009308 <USBD_LL_DataInStage+0xec>
|
|
}
|
|
else
|
|
{
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80092ce: 68fb ldr r3, [r7, #12]
|
|
80092d0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80092d4: b2db uxtb r3, r3
|
|
80092d6: 2b03 cmp r3, #3
|
|
80092d8: d10f bne.n 80092fa <USBD_LL_DataInStage+0xde>
|
|
{
|
|
if (pdev->pClass[0]->EP0_TxSent != NULL)
|
|
80092da: 68fb ldr r3, [r7, #12]
|
|
80092dc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80092e0: 68db ldr r3, [r3, #12]
|
|
80092e2: 2b00 cmp r3, #0
|
|
80092e4: d009 beq.n 80092fa <USBD_LL_DataInStage+0xde>
|
|
{
|
|
pdev->classId = 0U;
|
|
80092e6: 68fb ldr r3, [r7, #12]
|
|
80092e8: 2200 movs r2, #0
|
|
80092ea: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
pdev->pClass[0]->EP0_TxSent(pdev);
|
|
80092ee: 68fb ldr r3, [r7, #12]
|
|
80092f0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80092f4: 68db ldr r3, [r3, #12]
|
|
80092f6: 68f8 ldr r0, [r7, #12]
|
|
80092f8: 4798 blx r3
|
|
}
|
|
}
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
80092fa: 2180 movs r1, #128 @ 0x80
|
|
80092fc: 68f8 ldr r0, [r7, #12]
|
|
80092fe: f001 fc41 bl 800ab84 <USBD_LL_StallEP>
|
|
(void)USBD_CtlReceiveStatus(pdev);
|
|
8009302: 68f8 ldr r0, [r7, #12]
|
|
8009304: f001 f8db bl 800a4be <USBD_CtlReceiveStatus>
|
|
}
|
|
}
|
|
}
|
|
|
|
if (pdev->dev_test_mode != 0U)
|
|
8009308: 68fb ldr r3, [r7, #12]
|
|
800930a: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
|
|
800930e: 2b00 cmp r3, #0
|
|
8009310: d03a beq.n 8009388 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
(void)USBD_RunTestMode(pdev);
|
|
8009312: 68f8 ldr r0, [r7, #12]
|
|
8009314: f7ff fe30 bl 8008f78 <USBD_RunTestMode>
|
|
pdev->dev_test_mode = 0U;
|
|
8009318: 68fb ldr r3, [r7, #12]
|
|
800931a: 2200 movs r2, #0
|
|
800931c: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
8009320: e032 b.n 8009388 <USBD_LL_DataInStage+0x16c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U));
|
|
8009322: 7afb ldrb r3, [r7, #11]
|
|
8009324: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8009328: b2db uxtb r3, r3
|
|
800932a: 4619 mov r1, r3
|
|
800932c: 68f8 ldr r0, [r7, #12]
|
|
800932e: f000 f986 bl 800963e <USBD_CoreFindEP>
|
|
8009332: 4603 mov r3, r0
|
|
8009334: 75fb strb r3, [r7, #23]
|
|
|
|
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8009336: 7dfb ldrb r3, [r7, #23]
|
|
8009338: 2bff cmp r3, #255 @ 0xff
|
|
800933a: d025 beq.n 8009388 <USBD_LL_DataInStage+0x16c>
|
|
800933c: 7dfb ldrb r3, [r7, #23]
|
|
800933e: 2b00 cmp r3, #0
|
|
8009340: d122 bne.n 8009388 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8009342: 68fb ldr r3, [r7, #12]
|
|
8009344: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009348: b2db uxtb r3, r3
|
|
800934a: 2b03 cmp r3, #3
|
|
800934c: d11c bne.n 8009388 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
if (pdev->pClass[idx]->DataIn != NULL)
|
|
800934e: 7dfa ldrb r2, [r7, #23]
|
|
8009350: 68fb ldr r3, [r7, #12]
|
|
8009352: 32ae adds r2, #174 @ 0xae
|
|
8009354: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009358: 695b ldr r3, [r3, #20]
|
|
800935a: 2b00 cmp r3, #0
|
|
800935c: d014 beq.n 8009388 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
pdev->classId = idx;
|
|
800935e: 7dfa ldrb r2, [r7, #23]
|
|
8009360: 68fb ldr r3, [r7, #12]
|
|
8009362: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum);
|
|
8009366: 7dfa ldrb r2, [r7, #23]
|
|
8009368: 68fb ldr r3, [r7, #12]
|
|
800936a: 32ae adds r2, #174 @ 0xae
|
|
800936c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009370: 695b ldr r3, [r3, #20]
|
|
8009372: 7afa ldrb r2, [r7, #11]
|
|
8009374: 4611 mov r1, r2
|
|
8009376: 68f8 ldr r0, [r7, #12]
|
|
8009378: 4798 blx r3
|
|
800937a: 4603 mov r3, r0
|
|
800937c: 75bb strb r3, [r7, #22]
|
|
|
|
if (ret != USBD_OK)
|
|
800937e: 7dbb ldrb r3, [r7, #22]
|
|
8009380: 2b00 cmp r3, #0
|
|
8009382: d001 beq.n 8009388 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
return ret;
|
|
8009384: 7dbb ldrb r3, [r7, #22]
|
|
8009386: e000 b.n 800938a <USBD_LL_DataInStage+0x16e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8009388: 2300 movs r3, #0
|
|
}
|
|
800938a: 4618 mov r0, r3
|
|
800938c: 3718 adds r7, #24
|
|
800938e: 46bd mov sp, r7
|
|
8009390: bd80 pop {r7, pc}
|
|
|
|
08009392 <USBD_LL_Reset>:
|
|
* Handle Reset event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8009392: b580 push {r7, lr}
|
|
8009394: b084 sub sp, #16
|
|
8009396: af00 add r7, sp, #0
|
|
8009398: 6078 str r0, [r7, #4]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
800939a: 2300 movs r3, #0
|
|
800939c: 73fb strb r3, [r7, #15]
|
|
|
|
/* Upon Reset call user call back */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
800939e: 687b ldr r3, [r7, #4]
|
|
80093a0: 2201 movs r2, #1
|
|
80093a2: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->ep0_state = USBD_EP0_IDLE;
|
|
80093a6: 687b ldr r3, [r7, #4]
|
|
80093a8: 2200 movs r2, #0
|
|
80093aa: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->dev_config = 0U;
|
|
80093ae: 687b ldr r3, [r7, #4]
|
|
80093b0: 2200 movs r2, #0
|
|
80093b2: 605a str r2, [r3, #4]
|
|
pdev->dev_remote_wakeup = 0U;
|
|
80093b4: 687b ldr r3, [r7, #4]
|
|
80093b6: 2200 movs r2, #0
|
|
80093b8: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
pdev->dev_test_mode = 0U;
|
|
80093bc: 687b ldr r3, [r7, #4]
|
|
80093be: 2200 movs r2, #0
|
|
80093c0: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
|
|
if (pdev->pClass[0] != NULL)
|
|
80093c4: 687b ldr r3, [r7, #4]
|
|
80093c6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80093ca: 2b00 cmp r3, #0
|
|
80093cc: d014 beq.n 80093f8 <USBD_LL_Reset+0x66>
|
|
{
|
|
if (pdev->pClass[0]->DeInit != NULL)
|
|
80093ce: 687b ldr r3, [r7, #4]
|
|
80093d0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80093d4: 685b ldr r3, [r3, #4]
|
|
80093d6: 2b00 cmp r3, #0
|
|
80093d8: d00e beq.n 80093f8 <USBD_LL_Reset+0x66>
|
|
{
|
|
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK)
|
|
80093da: 687b ldr r3, [r7, #4]
|
|
80093dc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80093e0: 685b ldr r3, [r3, #4]
|
|
80093e2: 687a ldr r2, [r7, #4]
|
|
80093e4: 6852 ldr r2, [r2, #4]
|
|
80093e6: b2d2 uxtb r2, r2
|
|
80093e8: 4611 mov r1, r2
|
|
80093ea: 6878 ldr r0, [r7, #4]
|
|
80093ec: 4798 blx r3
|
|
80093ee: 4603 mov r3, r0
|
|
80093f0: 2b00 cmp r3, #0
|
|
80093f2: d001 beq.n 80093f8 <USBD_LL_Reset+0x66>
|
|
{
|
|
ret = USBD_FAIL;
|
|
80093f4: 2303 movs r3, #3
|
|
80093f6: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Open EP0 OUT */
|
|
(void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
80093f8: 2340 movs r3, #64 @ 0x40
|
|
80093fa: 2200 movs r2, #0
|
|
80093fc: 2100 movs r1, #0
|
|
80093fe: 6878 ldr r0, [r7, #4]
|
|
8009400: f001 fb7b bl 800aafa <USBD_LL_OpenEP>
|
|
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
|
|
8009404: 687b ldr r3, [r7, #4]
|
|
8009406: 2201 movs r2, #1
|
|
8009408: f883 2163 strb.w r2, [r3, #355] @ 0x163
|
|
|
|
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
800940c: 687b ldr r3, [r7, #4]
|
|
800940e: 2240 movs r2, #64 @ 0x40
|
|
8009410: f8a3 2160 strh.w r2, [r3, #352] @ 0x160
|
|
|
|
/* Open EP0 IN */
|
|
(void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
8009414: 2340 movs r3, #64 @ 0x40
|
|
8009416: 2200 movs r2, #0
|
|
8009418: 2180 movs r1, #128 @ 0x80
|
|
800941a: 6878 ldr r0, [r7, #4]
|
|
800941c: f001 fb6d bl 800aafa <USBD_LL_OpenEP>
|
|
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
|
|
8009420: 687b ldr r3, [r7, #4]
|
|
8009422: 2201 movs r2, #1
|
|
8009424: f883 2023 strb.w r2, [r3, #35] @ 0x23
|
|
|
|
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
8009428: 687b ldr r3, [r7, #4]
|
|
800942a: 2240 movs r2, #64 @ 0x40
|
|
800942c: 841a strh r2, [r3, #32]
|
|
|
|
return ret;
|
|
800942e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009430: 4618 mov r0, r3
|
|
8009432: 3710 adds r7, #16
|
|
8009434: 46bd mov sp, r7
|
|
8009436: bd80 pop {r7, pc}
|
|
|
|
08009438 <USBD_LL_SetSpeed>:
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
|
|
USBD_SpeedTypeDef speed)
|
|
{
|
|
8009438: b480 push {r7}
|
|
800943a: b083 sub sp, #12
|
|
800943c: af00 add r7, sp, #0
|
|
800943e: 6078 str r0, [r7, #4]
|
|
8009440: 460b mov r3, r1
|
|
8009442: 70fb strb r3, [r7, #3]
|
|
pdev->dev_speed = speed;
|
|
8009444: 687b ldr r3, [r7, #4]
|
|
8009446: 78fa ldrb r2, [r7, #3]
|
|
8009448: 741a strb r2, [r3, #16]
|
|
|
|
return USBD_OK;
|
|
800944a: 2300 movs r3, #0
|
|
}
|
|
800944c: 4618 mov r0, r3
|
|
800944e: 370c adds r7, #12
|
|
8009450: 46bd mov sp, r7
|
|
8009452: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009456: 4770 bx lr
|
|
|
|
08009458 <USBD_LL_Suspend>:
|
|
* Handle Suspend event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8009458: b480 push {r7}
|
|
800945a: b083 sub sp, #12
|
|
800945c: af00 add r7, sp, #0
|
|
800945e: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state != USBD_STATE_SUSPENDED)
|
|
8009460: 687b ldr r3, [r7, #4]
|
|
8009462: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009466: b2db uxtb r3, r3
|
|
8009468: 2b04 cmp r3, #4
|
|
800946a: d006 beq.n 800947a <USBD_LL_Suspend+0x22>
|
|
{
|
|
pdev->dev_old_state = pdev->dev_state;
|
|
800946c: 687b ldr r3, [r7, #4]
|
|
800946e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009472: b2da uxtb r2, r3
|
|
8009474: 687b ldr r3, [r7, #4]
|
|
8009476: f883 229d strb.w r2, [r3, #669] @ 0x29d
|
|
}
|
|
|
|
pdev->dev_state = USBD_STATE_SUSPENDED;
|
|
800947a: 687b ldr r3, [r7, #4]
|
|
800947c: 2204 movs r2, #4
|
|
800947e: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
|
|
return USBD_OK;
|
|
8009482: 2300 movs r3, #0
|
|
}
|
|
8009484: 4618 mov r0, r3
|
|
8009486: 370c adds r7, #12
|
|
8009488: 46bd mov sp, r7
|
|
800948a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800948e: 4770 bx lr
|
|
|
|
08009490 <USBD_LL_Resume>:
|
|
* Handle Resume event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8009490: b480 push {r7}
|
|
8009492: b083 sub sp, #12
|
|
8009494: af00 add r7, sp, #0
|
|
8009496: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state == USBD_STATE_SUSPENDED)
|
|
8009498: 687b ldr r3, [r7, #4]
|
|
800949a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
800949e: b2db uxtb r3, r3
|
|
80094a0: 2b04 cmp r3, #4
|
|
80094a2: d106 bne.n 80094b2 <USBD_LL_Resume+0x22>
|
|
{
|
|
pdev->dev_state = pdev->dev_old_state;
|
|
80094a4: 687b ldr r3, [r7, #4]
|
|
80094a6: f893 329d ldrb.w r3, [r3, #669] @ 0x29d
|
|
80094aa: b2da uxtb r2, r3
|
|
80094ac: 687b ldr r3, [r7, #4]
|
|
80094ae: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
|
|
return USBD_OK;
|
|
80094b2: 2300 movs r3, #0
|
|
}
|
|
80094b4: 4618 mov r0, r3
|
|
80094b6: 370c adds r7, #12
|
|
80094b8: 46bd mov sp, r7
|
|
80094ba: f85d 7b04 ldr.w r7, [sp], #4
|
|
80094be: 4770 bx lr
|
|
|
|
080094c0 <USBD_LL_SOF>:
|
|
* Handle SOF event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80094c0: b580 push {r7, lr}
|
|
80094c2: b082 sub sp, #8
|
|
80094c4: af00 add r7, sp, #0
|
|
80094c6: 6078 str r0, [r7, #4]
|
|
/* The SOF event can be distributed for all classes that support it */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80094c8: 687b ldr r3, [r7, #4]
|
|
80094ca: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80094ce: b2db uxtb r3, r3
|
|
80094d0: 2b03 cmp r3, #3
|
|
80094d2: d110 bne.n 80094f6 <USBD_LL_SOF+0x36>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
80094d4: 687b ldr r3, [r7, #4]
|
|
80094d6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80094da: 2b00 cmp r3, #0
|
|
80094dc: d00b beq.n 80094f6 <USBD_LL_SOF+0x36>
|
|
{
|
|
if (pdev->pClass[0]->SOF != NULL)
|
|
80094de: 687b ldr r3, [r7, #4]
|
|
80094e0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80094e4: 69db ldr r3, [r3, #28]
|
|
80094e6: 2b00 cmp r3, #0
|
|
80094e8: d005 beq.n 80094f6 <USBD_LL_SOF+0x36>
|
|
{
|
|
(void)pdev->pClass[0]->SOF(pdev);
|
|
80094ea: 687b ldr r3, [r7, #4]
|
|
80094ec: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80094f0: 69db ldr r3, [r3, #28]
|
|
80094f2: 6878 ldr r0, [r7, #4]
|
|
80094f4: 4798 blx r3
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
|
|
return USBD_OK;
|
|
80094f6: 2300 movs r3, #0
|
|
}
|
|
80094f8: 4618 mov r0, r3
|
|
80094fa: 3708 adds r7, #8
|
|
80094fc: 46bd mov sp, r7
|
|
80094fe: bd80 pop {r7, pc}
|
|
|
|
08009500 <USBD_LL_IsoINIncomplete>:
|
|
* @param epnum: Endpoint number
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum)
|
|
{
|
|
8009500: b580 push {r7, lr}
|
|
8009502: b082 sub sp, #8
|
|
8009504: af00 add r7, sp, #0
|
|
8009506: 6078 str r0, [r7, #4]
|
|
8009508: 460b mov r3, r1
|
|
800950a: 70fb strb r3, [r7, #3]
|
|
if (pdev->pClass[pdev->classId] == NULL)
|
|
800950c: 687b ldr r3, [r7, #4]
|
|
800950e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8009512: 687b ldr r3, [r7, #4]
|
|
8009514: 32ae adds r2, #174 @ 0xae
|
|
8009516: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800951a: 2b00 cmp r3, #0
|
|
800951c: d101 bne.n 8009522 <USBD_LL_IsoINIncomplete+0x22>
|
|
{
|
|
return USBD_FAIL;
|
|
800951e: 2303 movs r3, #3
|
|
8009520: e01c b.n 800955c <USBD_LL_IsoINIncomplete+0x5c>
|
|
}
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8009522: 687b ldr r3, [r7, #4]
|
|
8009524: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009528: b2db uxtb r3, r3
|
|
800952a: 2b03 cmp r3, #3
|
|
800952c: d115 bne.n 800955a <USBD_LL_IsoINIncomplete+0x5a>
|
|
{
|
|
if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL)
|
|
800952e: 687b ldr r3, [r7, #4]
|
|
8009530: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8009534: 687b ldr r3, [r7, #4]
|
|
8009536: 32ae adds r2, #174 @ 0xae
|
|
8009538: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800953c: 6a1b ldr r3, [r3, #32]
|
|
800953e: 2b00 cmp r3, #0
|
|
8009540: d00b beq.n 800955a <USBD_LL_IsoINIncomplete+0x5a>
|
|
{
|
|
(void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum);
|
|
8009542: 687b ldr r3, [r7, #4]
|
|
8009544: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8009548: 687b ldr r3, [r7, #4]
|
|
800954a: 32ae adds r2, #174 @ 0xae
|
|
800954c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009550: 6a1b ldr r3, [r3, #32]
|
|
8009552: 78fa ldrb r2, [r7, #3]
|
|
8009554: 4611 mov r1, r2
|
|
8009556: 6878 ldr r0, [r7, #4]
|
|
8009558: 4798 blx r3
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
800955a: 2300 movs r3, #0
|
|
}
|
|
800955c: 4618 mov r0, r3
|
|
800955e: 3708 adds r7, #8
|
|
8009560: 46bd mov sp, r7
|
|
8009562: bd80 pop {r7, pc}
|
|
|
|
08009564 <USBD_LL_IsoOUTIncomplete>:
|
|
* @param epnum: Endpoint number
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum)
|
|
{
|
|
8009564: b580 push {r7, lr}
|
|
8009566: b082 sub sp, #8
|
|
8009568: af00 add r7, sp, #0
|
|
800956a: 6078 str r0, [r7, #4]
|
|
800956c: 460b mov r3, r1
|
|
800956e: 70fb strb r3, [r7, #3]
|
|
if (pdev->pClass[pdev->classId] == NULL)
|
|
8009570: 687b ldr r3, [r7, #4]
|
|
8009572: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8009576: 687b ldr r3, [r7, #4]
|
|
8009578: 32ae adds r2, #174 @ 0xae
|
|
800957a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800957e: 2b00 cmp r3, #0
|
|
8009580: d101 bne.n 8009586 <USBD_LL_IsoOUTIncomplete+0x22>
|
|
{
|
|
return USBD_FAIL;
|
|
8009582: 2303 movs r3, #3
|
|
8009584: e01c b.n 80095c0 <USBD_LL_IsoOUTIncomplete+0x5c>
|
|
}
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8009586: 687b ldr r3, [r7, #4]
|
|
8009588: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
800958c: b2db uxtb r3, r3
|
|
800958e: 2b03 cmp r3, #3
|
|
8009590: d115 bne.n 80095be <USBD_LL_IsoOUTIncomplete+0x5a>
|
|
{
|
|
if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL)
|
|
8009592: 687b ldr r3, [r7, #4]
|
|
8009594: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8009598: 687b ldr r3, [r7, #4]
|
|
800959a: 32ae adds r2, #174 @ 0xae
|
|
800959c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80095a0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80095a2: 2b00 cmp r3, #0
|
|
80095a4: d00b beq.n 80095be <USBD_LL_IsoOUTIncomplete+0x5a>
|
|
{
|
|
(void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum);
|
|
80095a6: 687b ldr r3, [r7, #4]
|
|
80095a8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80095ac: 687b ldr r3, [r7, #4]
|
|
80095ae: 32ae adds r2, #174 @ 0xae
|
|
80095b0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80095b4: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80095b6: 78fa ldrb r2, [r7, #3]
|
|
80095b8: 4611 mov r1, r2
|
|
80095ba: 6878 ldr r0, [r7, #4]
|
|
80095bc: 4798 blx r3
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
80095be: 2300 movs r3, #0
|
|
}
|
|
80095c0: 4618 mov r0, r3
|
|
80095c2: 3708 adds r7, #8
|
|
80095c4: 46bd mov sp, r7
|
|
80095c6: bd80 pop {r7, pc}
|
|
|
|
080095c8 <USBD_LL_DevConnected>:
|
|
* Handle device connection event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80095c8: b480 push {r7}
|
|
80095ca: b083 sub sp, #12
|
|
80095cc: af00 add r7, sp, #0
|
|
80095ce: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument compilation warning */
|
|
UNUSED(pdev);
|
|
|
|
return USBD_OK;
|
|
80095d0: 2300 movs r3, #0
|
|
}
|
|
80095d2: 4618 mov r0, r3
|
|
80095d4: 370c adds r7, #12
|
|
80095d6: 46bd mov sp, r7
|
|
80095d8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80095dc: 4770 bx lr
|
|
|
|
080095de <USBD_LL_DevDisconnected>:
|
|
* Handle device disconnection event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80095de: b580 push {r7, lr}
|
|
80095e0: b084 sub sp, #16
|
|
80095e2: af00 add r7, sp, #0
|
|
80095e4: 6078 str r0, [r7, #4]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80095e6: 2300 movs r3, #0
|
|
80095e8: 73fb strb r3, [r7, #15]
|
|
|
|
/* Free Class Resources */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
80095ea: 687b ldr r3, [r7, #4]
|
|
80095ec: 2201 movs r2, #1
|
|
80095ee: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
80095f2: 687b ldr r3, [r7, #4]
|
|
80095f4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80095f8: 2b00 cmp r3, #0
|
|
80095fa: d00e beq.n 800961a <USBD_LL_DevDisconnected+0x3c>
|
|
{
|
|
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U)
|
|
80095fc: 687b ldr r3, [r7, #4]
|
|
80095fe: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8009602: 685b ldr r3, [r3, #4]
|
|
8009604: 687a ldr r2, [r7, #4]
|
|
8009606: 6852 ldr r2, [r2, #4]
|
|
8009608: b2d2 uxtb r2, r2
|
|
800960a: 4611 mov r1, r2
|
|
800960c: 6878 ldr r0, [r7, #4]
|
|
800960e: 4798 blx r3
|
|
8009610: 4603 mov r3, r0
|
|
8009612: 2b00 cmp r3, #0
|
|
8009614: d001 beq.n 800961a <USBD_LL_DevDisconnected+0x3c>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8009616: 2303 movs r3, #3
|
|
8009618: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
800961a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800961c: 4618 mov r0, r3
|
|
800961e: 3710 adds r7, #16
|
|
8009620: 46bd mov sp, r7
|
|
8009622: bd80 pop {r7, pc}
|
|
|
|
08009624 <USBD_CoreFindIF>:
|
|
* @param pdev: device instance
|
|
* @param index : selected interface number
|
|
* @retval index of the class using the selected interface number. OxFF if no class found.
|
|
*/
|
|
uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index)
|
|
{
|
|
8009624: b480 push {r7}
|
|
8009626: b083 sub sp, #12
|
|
8009628: af00 add r7, sp, #0
|
|
800962a: 6078 str r0, [r7, #4]
|
|
800962c: 460b mov r3, r1
|
|
800962e: 70fb strb r3, [r7, #3]
|
|
return 0xFFU;
|
|
#else
|
|
UNUSED(pdev);
|
|
UNUSED(index);
|
|
|
|
return 0x00U;
|
|
8009630: 2300 movs r3, #0
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
8009632: 4618 mov r0, r3
|
|
8009634: 370c adds r7, #12
|
|
8009636: 46bd mov sp, r7
|
|
8009638: f85d 7b04 ldr.w r7, [sp], #4
|
|
800963c: 4770 bx lr
|
|
|
|
0800963e <USBD_CoreFindEP>:
|
|
* @param pdev: device instance
|
|
* @param index : selected endpoint number
|
|
* @retval index of the class using the selected endpoint number. 0xFF if no class found.
|
|
*/
|
|
uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index)
|
|
{
|
|
800963e: b480 push {r7}
|
|
8009640: b083 sub sp, #12
|
|
8009642: af00 add r7, sp, #0
|
|
8009644: 6078 str r0, [r7, #4]
|
|
8009646: 460b mov r3, r1
|
|
8009648: 70fb strb r3, [r7, #3]
|
|
return 0xFFU;
|
|
#else
|
|
UNUSED(pdev);
|
|
UNUSED(index);
|
|
|
|
return 0x00U;
|
|
800964a: 2300 movs r3, #0
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
800964c: 4618 mov r0, r3
|
|
800964e: 370c adds r7, #12
|
|
8009650: 46bd mov sp, r7
|
|
8009652: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009656: 4770 bx lr
|
|
|
|
08009658 <USBD_GetEpDesc>:
|
|
* @param pConfDesc: pointer to Bos descriptor
|
|
* @param EpAddr: endpoint address
|
|
* @retval pointer to video endpoint descriptor
|
|
*/
|
|
void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr)
|
|
{
|
|
8009658: b580 push {r7, lr}
|
|
800965a: b086 sub sp, #24
|
|
800965c: af00 add r7, sp, #0
|
|
800965e: 6078 str r0, [r7, #4]
|
|
8009660: 460b mov r3, r1
|
|
8009662: 70fb strb r3, [r7, #3]
|
|
USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc;
|
|
8009664: 687b ldr r3, [r7, #4]
|
|
8009666: 617b str r3, [r7, #20]
|
|
USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc;
|
|
8009668: 687b ldr r3, [r7, #4]
|
|
800966a: 60fb str r3, [r7, #12]
|
|
USBD_EpDescTypeDef *pEpDesc = NULL;
|
|
800966c: 2300 movs r3, #0
|
|
800966e: 613b str r3, [r7, #16]
|
|
uint16_t ptr;
|
|
|
|
if (desc->wTotalLength > desc->bLength)
|
|
8009670: 68fb ldr r3, [r7, #12]
|
|
8009672: 885b ldrh r3, [r3, #2]
|
|
8009674: b29b uxth r3, r3
|
|
8009676: 68fa ldr r2, [r7, #12]
|
|
8009678: 7812 ldrb r2, [r2, #0]
|
|
800967a: 4293 cmp r3, r2
|
|
800967c: d91f bls.n 80096be <USBD_GetEpDesc+0x66>
|
|
{
|
|
ptr = desc->bLength;
|
|
800967e: 68fb ldr r3, [r7, #12]
|
|
8009680: 781b ldrb r3, [r3, #0]
|
|
8009682: 817b strh r3, [r7, #10]
|
|
|
|
while (ptr < desc->wTotalLength)
|
|
8009684: e013 b.n 80096ae <USBD_GetEpDesc+0x56>
|
|
{
|
|
pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr);
|
|
8009686: f107 030a add.w r3, r7, #10
|
|
800968a: 4619 mov r1, r3
|
|
800968c: 6978 ldr r0, [r7, #20]
|
|
800968e: f000 f81b bl 80096c8 <USBD_GetNextDesc>
|
|
8009692: 6178 str r0, [r7, #20]
|
|
|
|
if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT)
|
|
8009694: 697b ldr r3, [r7, #20]
|
|
8009696: 785b ldrb r3, [r3, #1]
|
|
8009698: 2b05 cmp r3, #5
|
|
800969a: d108 bne.n 80096ae <USBD_GetEpDesc+0x56>
|
|
{
|
|
pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc;
|
|
800969c: 697b ldr r3, [r7, #20]
|
|
800969e: 613b str r3, [r7, #16]
|
|
|
|
if (pEpDesc->bEndpointAddress == EpAddr)
|
|
80096a0: 693b ldr r3, [r7, #16]
|
|
80096a2: 789b ldrb r3, [r3, #2]
|
|
80096a4: 78fa ldrb r2, [r7, #3]
|
|
80096a6: 429a cmp r2, r3
|
|
80096a8: d008 beq.n 80096bc <USBD_GetEpDesc+0x64>
|
|
{
|
|
break;
|
|
}
|
|
else
|
|
{
|
|
pEpDesc = NULL;
|
|
80096aa: 2300 movs r3, #0
|
|
80096ac: 613b str r3, [r7, #16]
|
|
while (ptr < desc->wTotalLength)
|
|
80096ae: 68fb ldr r3, [r7, #12]
|
|
80096b0: 885b ldrh r3, [r3, #2]
|
|
80096b2: b29a uxth r2, r3
|
|
80096b4: 897b ldrh r3, [r7, #10]
|
|
80096b6: 429a cmp r2, r3
|
|
80096b8: d8e5 bhi.n 8009686 <USBD_GetEpDesc+0x2e>
|
|
80096ba: e000 b.n 80096be <USBD_GetEpDesc+0x66>
|
|
break;
|
|
80096bc: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return (void *)pEpDesc;
|
|
80096be: 693b ldr r3, [r7, #16]
|
|
}
|
|
80096c0: 4618 mov r0, r3
|
|
80096c2: 3718 adds r7, #24
|
|
80096c4: 46bd mov sp, r7
|
|
80096c6: bd80 pop {r7, pc}
|
|
|
|
080096c8 <USBD_GetNextDesc>:
|
|
* @param buf: Buffer where the descriptor is available
|
|
* @param ptr: data pointer inside the descriptor
|
|
* @retval next header
|
|
*/
|
|
USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr)
|
|
{
|
|
80096c8: b480 push {r7}
|
|
80096ca: b085 sub sp, #20
|
|
80096cc: af00 add r7, sp, #0
|
|
80096ce: 6078 str r0, [r7, #4]
|
|
80096d0: 6039 str r1, [r7, #0]
|
|
USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf;
|
|
80096d2: 687b ldr r3, [r7, #4]
|
|
80096d4: 60fb str r3, [r7, #12]
|
|
|
|
*ptr += pnext->bLength;
|
|
80096d6: 683b ldr r3, [r7, #0]
|
|
80096d8: 881b ldrh r3, [r3, #0]
|
|
80096da: 68fa ldr r2, [r7, #12]
|
|
80096dc: 7812 ldrb r2, [r2, #0]
|
|
80096de: 4413 add r3, r2
|
|
80096e0: b29a uxth r2, r3
|
|
80096e2: 683b ldr r3, [r7, #0]
|
|
80096e4: 801a strh r2, [r3, #0]
|
|
pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength);
|
|
80096e6: 68fb ldr r3, [r7, #12]
|
|
80096e8: 781b ldrb r3, [r3, #0]
|
|
80096ea: 461a mov r2, r3
|
|
80096ec: 687b ldr r3, [r7, #4]
|
|
80096ee: 4413 add r3, r2
|
|
80096f0: 60fb str r3, [r7, #12]
|
|
|
|
return (pnext);
|
|
80096f2: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80096f4: 4618 mov r0, r3
|
|
80096f6: 3714 adds r7, #20
|
|
80096f8: 46bd mov sp, r7
|
|
80096fa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80096fe: 4770 bx lr
|
|
|
|
08009700 <SWAPBYTE>:
|
|
|
|
/** @defgroup USBD_DEF_Exported_Macros
|
|
* @{
|
|
*/
|
|
__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
|
|
{
|
|
8009700: b480 push {r7}
|
|
8009702: b087 sub sp, #28
|
|
8009704: af00 add r7, sp, #0
|
|
8009706: 6078 str r0, [r7, #4]
|
|
uint16_t _SwapVal;
|
|
uint16_t _Byte1;
|
|
uint16_t _Byte2;
|
|
uint8_t *_pbuff = addr;
|
|
8009708: 687b ldr r3, [r7, #4]
|
|
800970a: 617b str r3, [r7, #20]
|
|
|
|
_Byte1 = *(uint8_t *)_pbuff;
|
|
800970c: 697b ldr r3, [r7, #20]
|
|
800970e: 781b ldrb r3, [r3, #0]
|
|
8009710: 827b strh r3, [r7, #18]
|
|
_pbuff++;
|
|
8009712: 697b ldr r3, [r7, #20]
|
|
8009714: 3301 adds r3, #1
|
|
8009716: 617b str r3, [r7, #20]
|
|
_Byte2 = *(uint8_t *)_pbuff;
|
|
8009718: 697b ldr r3, [r7, #20]
|
|
800971a: 781b ldrb r3, [r3, #0]
|
|
800971c: 823b strh r3, [r7, #16]
|
|
|
|
_SwapVal = (_Byte2 << 8) | _Byte1;
|
|
800971e: f9b7 3010 ldrsh.w r3, [r7, #16]
|
|
8009722: 021b lsls r3, r3, #8
|
|
8009724: b21a sxth r2, r3
|
|
8009726: f9b7 3012 ldrsh.w r3, [r7, #18]
|
|
800972a: 4313 orrs r3, r2
|
|
800972c: b21b sxth r3, r3
|
|
800972e: 81fb strh r3, [r7, #14]
|
|
|
|
return _SwapVal;
|
|
8009730: 89fb ldrh r3, [r7, #14]
|
|
}
|
|
8009732: 4618 mov r0, r3
|
|
8009734: 371c adds r7, #28
|
|
8009736: 46bd mov sp, r7
|
|
8009738: f85d 7b04 ldr.w r7, [sp], #4
|
|
800973c: 4770 bx lr
|
|
...
|
|
|
|
08009740 <USBD_StdDevReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009740: b580 push {r7, lr}
|
|
8009742: b084 sub sp, #16
|
|
8009744: af00 add r7, sp, #0
|
|
8009746: 6078 str r0, [r7, #4]
|
|
8009748: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
800974a: 2300 movs r3, #0
|
|
800974c: 73fb strb r3, [r7, #15]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
800974e: 683b ldr r3, [r7, #0]
|
|
8009750: 781b ldrb r3, [r3, #0]
|
|
8009752: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8009756: 2b40 cmp r3, #64 @ 0x40
|
|
8009758: d005 beq.n 8009766 <USBD_StdDevReq+0x26>
|
|
800975a: 2b40 cmp r3, #64 @ 0x40
|
|
800975c: d857 bhi.n 800980e <USBD_StdDevReq+0xce>
|
|
800975e: 2b00 cmp r3, #0
|
|
8009760: d00f beq.n 8009782 <USBD_StdDevReq+0x42>
|
|
8009762: 2b20 cmp r3, #32
|
|
8009764: d153 bne.n 800980e <USBD_StdDevReq+0xce>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req);
|
|
8009766: 687b ldr r3, [r7, #4]
|
|
8009768: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800976c: 687b ldr r3, [r7, #4]
|
|
800976e: 32ae adds r2, #174 @ 0xae
|
|
8009770: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009774: 689b ldr r3, [r3, #8]
|
|
8009776: 6839 ldr r1, [r7, #0]
|
|
8009778: 6878 ldr r0, [r7, #4]
|
|
800977a: 4798 blx r3
|
|
800977c: 4603 mov r3, r0
|
|
800977e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009780: e04a b.n 8009818 <USBD_StdDevReq+0xd8>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
8009782: 683b ldr r3, [r7, #0]
|
|
8009784: 785b ldrb r3, [r3, #1]
|
|
8009786: 2b09 cmp r3, #9
|
|
8009788: d83b bhi.n 8009802 <USBD_StdDevReq+0xc2>
|
|
800978a: a201 add r2, pc, #4 @ (adr r2, 8009790 <USBD_StdDevReq+0x50>)
|
|
800978c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8009790: 080097e5 .word 0x080097e5
|
|
8009794: 080097f9 .word 0x080097f9
|
|
8009798: 08009803 .word 0x08009803
|
|
800979c: 080097ef .word 0x080097ef
|
|
80097a0: 08009803 .word 0x08009803
|
|
80097a4: 080097c3 .word 0x080097c3
|
|
80097a8: 080097b9 .word 0x080097b9
|
|
80097ac: 08009803 .word 0x08009803
|
|
80097b0: 080097db .word 0x080097db
|
|
80097b4: 080097cd .word 0x080097cd
|
|
{
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
USBD_GetDescriptor(pdev, req);
|
|
80097b8: 6839 ldr r1, [r7, #0]
|
|
80097ba: 6878 ldr r0, [r7, #4]
|
|
80097bc: f000 fa3e bl 8009c3c <USBD_GetDescriptor>
|
|
break;
|
|
80097c0: e024 b.n 800980c <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_ADDRESS:
|
|
USBD_SetAddress(pdev, req);
|
|
80097c2: 6839 ldr r1, [r7, #0]
|
|
80097c4: 6878 ldr r0, [r7, #4]
|
|
80097c6: f000 fbcd bl 8009f64 <USBD_SetAddress>
|
|
break;
|
|
80097ca: e01f b.n 800980c <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_CONFIGURATION:
|
|
ret = USBD_SetConfig(pdev, req);
|
|
80097cc: 6839 ldr r1, [r7, #0]
|
|
80097ce: 6878 ldr r0, [r7, #4]
|
|
80097d0: f000 fc0c bl 8009fec <USBD_SetConfig>
|
|
80097d4: 4603 mov r3, r0
|
|
80097d6: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80097d8: e018 b.n 800980c <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_GET_CONFIGURATION:
|
|
USBD_GetConfig(pdev, req);
|
|
80097da: 6839 ldr r1, [r7, #0]
|
|
80097dc: 6878 ldr r0, [r7, #4]
|
|
80097de: f000 fcaf bl 800a140 <USBD_GetConfig>
|
|
break;
|
|
80097e2: e013 b.n 800980c <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
USBD_GetStatus(pdev, req);
|
|
80097e4: 6839 ldr r1, [r7, #0]
|
|
80097e6: 6878 ldr r0, [r7, #4]
|
|
80097e8: f000 fce0 bl 800a1ac <USBD_GetStatus>
|
|
break;
|
|
80097ec: e00e b.n 800980c <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_FEATURE:
|
|
USBD_SetFeature(pdev, req);
|
|
80097ee: 6839 ldr r1, [r7, #0]
|
|
80097f0: 6878 ldr r0, [r7, #4]
|
|
80097f2: f000 fd0f bl 800a214 <USBD_SetFeature>
|
|
break;
|
|
80097f6: e009 b.n 800980c <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
USBD_ClrFeature(pdev, req);
|
|
80097f8: 6839 ldr r1, [r7, #0]
|
|
80097fa: 6878 ldr r0, [r7, #4]
|
|
80097fc: f000 fd33 bl 800a266 <USBD_ClrFeature>
|
|
break;
|
|
8009800: e004 b.n 800980c <USBD_StdDevReq+0xcc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8009802: 6839 ldr r1, [r7, #0]
|
|
8009804: 6878 ldr r0, [r7, #4]
|
|
8009806: f000 fd8a bl 800a31e <USBD_CtlError>
|
|
break;
|
|
800980a: bf00 nop
|
|
}
|
|
break;
|
|
800980c: e004 b.n 8009818 <USBD_StdDevReq+0xd8>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800980e: 6839 ldr r1, [r7, #0]
|
|
8009810: 6878 ldr r0, [r7, #4]
|
|
8009812: f000 fd84 bl 800a31e <USBD_CtlError>
|
|
break;
|
|
8009816: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8009818: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800981a: 4618 mov r0, r3
|
|
800981c: 3710 adds r7, #16
|
|
800981e: 46bd mov sp, r7
|
|
8009820: bd80 pop {r7, pc}
|
|
8009822: bf00 nop
|
|
|
|
08009824 <USBD_StdItfReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009824: b580 push {r7, lr}
|
|
8009826: b084 sub sp, #16
|
|
8009828: af00 add r7, sp, #0
|
|
800982a: 6078 str r0, [r7, #4]
|
|
800982c: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
800982e: 2300 movs r3, #0
|
|
8009830: 73fb strb r3, [r7, #15]
|
|
uint8_t idx;
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8009832: 683b ldr r3, [r7, #0]
|
|
8009834: 781b ldrb r3, [r3, #0]
|
|
8009836: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
800983a: 2b40 cmp r3, #64 @ 0x40
|
|
800983c: d005 beq.n 800984a <USBD_StdItfReq+0x26>
|
|
800983e: 2b40 cmp r3, #64 @ 0x40
|
|
8009840: d852 bhi.n 80098e8 <USBD_StdItfReq+0xc4>
|
|
8009842: 2b00 cmp r3, #0
|
|
8009844: d001 beq.n 800984a <USBD_StdItfReq+0x26>
|
|
8009846: 2b20 cmp r3, #32
|
|
8009848: d14e bne.n 80098e8 <USBD_StdItfReq+0xc4>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (pdev->dev_state)
|
|
800984a: 687b ldr r3, [r7, #4]
|
|
800984c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009850: b2db uxtb r3, r3
|
|
8009852: 3b01 subs r3, #1
|
|
8009854: 2b02 cmp r3, #2
|
|
8009856: d840 bhi.n 80098da <USBD_StdItfReq+0xb6>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
|
|
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
|
|
8009858: 683b ldr r3, [r7, #0]
|
|
800985a: 889b ldrh r3, [r3, #4]
|
|
800985c: b2db uxtb r3, r3
|
|
800985e: 2b01 cmp r3, #1
|
|
8009860: d836 bhi.n 80098d0 <USBD_StdItfReq+0xac>
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex));
|
|
8009862: 683b ldr r3, [r7, #0]
|
|
8009864: 889b ldrh r3, [r3, #4]
|
|
8009866: b2db uxtb r3, r3
|
|
8009868: 4619 mov r1, r3
|
|
800986a: 6878 ldr r0, [r7, #4]
|
|
800986c: f7ff feda bl 8009624 <USBD_CoreFindIF>
|
|
8009870: 4603 mov r3, r0
|
|
8009872: 73bb strb r3, [r7, #14]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8009874: 7bbb ldrb r3, [r7, #14]
|
|
8009876: 2bff cmp r3, #255 @ 0xff
|
|
8009878: d01d beq.n 80098b6 <USBD_StdItfReq+0x92>
|
|
800987a: 7bbb ldrb r3, [r7, #14]
|
|
800987c: 2b00 cmp r3, #0
|
|
800987e: d11a bne.n 80098b6 <USBD_StdItfReq+0x92>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8009880: 7bba ldrb r2, [r7, #14]
|
|
8009882: 687b ldr r3, [r7, #4]
|
|
8009884: 32ae adds r2, #174 @ 0xae
|
|
8009886: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800988a: 689b ldr r3, [r3, #8]
|
|
800988c: 2b00 cmp r3, #0
|
|
800988e: d00f beq.n 80098b0 <USBD_StdItfReq+0x8c>
|
|
{
|
|
pdev->classId = idx;
|
|
8009890: 7bba ldrb r2, [r7, #14]
|
|
8009892: 687b ldr r3, [r7, #4]
|
|
8009894: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
|
|
8009898: 7bba ldrb r2, [r7, #14]
|
|
800989a: 687b ldr r3, [r7, #4]
|
|
800989c: 32ae adds r2, #174 @ 0xae
|
|
800989e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80098a2: 689b ldr r3, [r3, #8]
|
|
80098a4: 6839 ldr r1, [r7, #0]
|
|
80098a6: 6878 ldr r0, [r7, #4]
|
|
80098a8: 4798 blx r3
|
|
80098aa: 4603 mov r3, r0
|
|
80098ac: 73fb strb r3, [r7, #15]
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
80098ae: e004 b.n 80098ba <USBD_StdItfReq+0x96>
|
|
}
|
|
else
|
|
{
|
|
/* should never reach this condition */
|
|
ret = USBD_FAIL;
|
|
80098b0: 2303 movs r3, #3
|
|
80098b2: 73fb strb r3, [r7, #15]
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
80098b4: e001 b.n 80098ba <USBD_StdItfReq+0x96>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* No relative interface found */
|
|
ret = USBD_FAIL;
|
|
80098b6: 2303 movs r3, #3
|
|
80098b8: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
if ((req->wLength == 0U) && (ret == USBD_OK))
|
|
80098ba: 683b ldr r3, [r7, #0]
|
|
80098bc: 88db ldrh r3, [r3, #6]
|
|
80098be: 2b00 cmp r3, #0
|
|
80098c0: d110 bne.n 80098e4 <USBD_StdItfReq+0xc0>
|
|
80098c2: 7bfb ldrb r3, [r7, #15]
|
|
80098c4: 2b00 cmp r3, #0
|
|
80098c6: d10d bne.n 80098e4 <USBD_StdItfReq+0xc0>
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80098c8: 6878 ldr r0, [r7, #4]
|
|
80098ca: f000 fde5 bl 800a498 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
80098ce: e009 b.n 80098e4 <USBD_StdItfReq+0xc0>
|
|
USBD_CtlError(pdev, req);
|
|
80098d0: 6839 ldr r1, [r7, #0]
|
|
80098d2: 6878 ldr r0, [r7, #4]
|
|
80098d4: f000 fd23 bl 800a31e <USBD_CtlError>
|
|
break;
|
|
80098d8: e004 b.n 80098e4 <USBD_StdItfReq+0xc0>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80098da: 6839 ldr r1, [r7, #0]
|
|
80098dc: 6878 ldr r0, [r7, #4]
|
|
80098de: f000 fd1e bl 800a31e <USBD_CtlError>
|
|
break;
|
|
80098e2: e000 b.n 80098e6 <USBD_StdItfReq+0xc2>
|
|
break;
|
|
80098e4: bf00 nop
|
|
}
|
|
break;
|
|
80098e6: e004 b.n 80098f2 <USBD_StdItfReq+0xce>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80098e8: 6839 ldr r1, [r7, #0]
|
|
80098ea: 6878 ldr r0, [r7, #4]
|
|
80098ec: f000 fd17 bl 800a31e <USBD_CtlError>
|
|
break;
|
|
80098f0: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
80098f2: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80098f4: 4618 mov r0, r3
|
|
80098f6: 3710 adds r7, #16
|
|
80098f8: 46bd mov sp, r7
|
|
80098fa: bd80 pop {r7, pc}
|
|
|
|
080098fc <USBD_StdEPReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
80098fc: b580 push {r7, lr}
|
|
80098fe: b084 sub sp, #16
|
|
8009900: af00 add r7, sp, #0
|
|
8009902: 6078 str r0, [r7, #4]
|
|
8009904: 6039 str r1, [r7, #0]
|
|
USBD_EndpointTypeDef *pep;
|
|
uint8_t ep_addr;
|
|
uint8_t idx;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8009906: 2300 movs r3, #0
|
|
8009908: 73fb strb r3, [r7, #15]
|
|
|
|
ep_addr = LOBYTE(req->wIndex);
|
|
800990a: 683b ldr r3, [r7, #0]
|
|
800990c: 889b ldrh r3, [r3, #4]
|
|
800990e: 73bb strb r3, [r7, #14]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8009910: 683b ldr r3, [r7, #0]
|
|
8009912: 781b ldrb r3, [r3, #0]
|
|
8009914: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8009918: 2b40 cmp r3, #64 @ 0x40
|
|
800991a: d007 beq.n 800992c <USBD_StdEPReq+0x30>
|
|
800991c: 2b40 cmp r3, #64 @ 0x40
|
|
800991e: f200 8181 bhi.w 8009c24 <USBD_StdEPReq+0x328>
|
|
8009922: 2b00 cmp r3, #0
|
|
8009924: d02a beq.n 800997c <USBD_StdEPReq+0x80>
|
|
8009926: 2b20 cmp r3, #32
|
|
8009928: f040 817c bne.w 8009c24 <USBD_StdEPReq+0x328>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
/* Get the class index relative to this endpoint */
|
|
idx = USBD_CoreFindEP(pdev, ep_addr);
|
|
800992c: 7bbb ldrb r3, [r7, #14]
|
|
800992e: 4619 mov r1, r3
|
|
8009930: 6878 ldr r0, [r7, #4]
|
|
8009932: f7ff fe84 bl 800963e <USBD_CoreFindEP>
|
|
8009936: 4603 mov r3, r0
|
|
8009938: 737b strb r3, [r7, #13]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
800993a: 7b7b ldrb r3, [r7, #13]
|
|
800993c: 2bff cmp r3, #255 @ 0xff
|
|
800993e: f000 8176 beq.w 8009c2e <USBD_StdEPReq+0x332>
|
|
8009942: 7b7b ldrb r3, [r7, #13]
|
|
8009944: 2b00 cmp r3, #0
|
|
8009946: f040 8172 bne.w 8009c2e <USBD_StdEPReq+0x332>
|
|
{
|
|
pdev->classId = idx;
|
|
800994a: 7b7a ldrb r2, [r7, #13]
|
|
800994c: 687b ldr r3, [r7, #4]
|
|
800994e: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8009952: 7b7a ldrb r2, [r7, #13]
|
|
8009954: 687b ldr r3, [r7, #4]
|
|
8009956: 32ae adds r2, #174 @ 0xae
|
|
8009958: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800995c: 689b ldr r3, [r3, #8]
|
|
800995e: 2b00 cmp r3, #0
|
|
8009960: f000 8165 beq.w 8009c2e <USBD_StdEPReq+0x332>
|
|
{
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req);
|
|
8009964: 7b7a ldrb r2, [r7, #13]
|
|
8009966: 687b ldr r3, [r7, #4]
|
|
8009968: 32ae adds r2, #174 @ 0xae
|
|
800996a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800996e: 689b ldr r3, [r3, #8]
|
|
8009970: 6839 ldr r1, [r7, #0]
|
|
8009972: 6878 ldr r0, [r7, #4]
|
|
8009974: 4798 blx r3
|
|
8009976: 4603 mov r3, r0
|
|
8009978: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
800997a: e158 b.n 8009c2e <USBD_StdEPReq+0x332>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
800997c: 683b ldr r3, [r7, #0]
|
|
800997e: 785b ldrb r3, [r3, #1]
|
|
8009980: 2b03 cmp r3, #3
|
|
8009982: d008 beq.n 8009996 <USBD_StdEPReq+0x9a>
|
|
8009984: 2b03 cmp r3, #3
|
|
8009986: f300 8147 bgt.w 8009c18 <USBD_StdEPReq+0x31c>
|
|
800998a: 2b00 cmp r3, #0
|
|
800998c: f000 809b beq.w 8009ac6 <USBD_StdEPReq+0x1ca>
|
|
8009990: 2b01 cmp r3, #1
|
|
8009992: d03c beq.n 8009a0e <USBD_StdEPReq+0x112>
|
|
8009994: e140 b.n 8009c18 <USBD_StdEPReq+0x31c>
|
|
{
|
|
case USB_REQ_SET_FEATURE:
|
|
switch (pdev->dev_state)
|
|
8009996: 687b ldr r3, [r7, #4]
|
|
8009998: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
800999c: b2db uxtb r3, r3
|
|
800999e: 2b02 cmp r3, #2
|
|
80099a0: d002 beq.n 80099a8 <USBD_StdEPReq+0xac>
|
|
80099a2: 2b03 cmp r3, #3
|
|
80099a4: d016 beq.n 80099d4 <USBD_StdEPReq+0xd8>
|
|
80099a6: e02c b.n 8009a02 <USBD_StdEPReq+0x106>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
80099a8: 7bbb ldrb r3, [r7, #14]
|
|
80099aa: 2b00 cmp r3, #0
|
|
80099ac: d00d beq.n 80099ca <USBD_StdEPReq+0xce>
|
|
80099ae: 7bbb ldrb r3, [r7, #14]
|
|
80099b0: 2b80 cmp r3, #128 @ 0x80
|
|
80099b2: d00a beq.n 80099ca <USBD_StdEPReq+0xce>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
80099b4: 7bbb ldrb r3, [r7, #14]
|
|
80099b6: 4619 mov r1, r3
|
|
80099b8: 6878 ldr r0, [r7, #4]
|
|
80099ba: f001 f8e3 bl 800ab84 <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
80099be: 2180 movs r1, #128 @ 0x80
|
|
80099c0: 6878 ldr r0, [r7, #4]
|
|
80099c2: f001 f8df bl 800ab84 <USBD_LL_StallEP>
|
|
80099c6: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
80099c8: e020 b.n 8009a0c <USBD_StdEPReq+0x110>
|
|
USBD_CtlError(pdev, req);
|
|
80099ca: 6839 ldr r1, [r7, #0]
|
|
80099cc: 6878 ldr r0, [r7, #4]
|
|
80099ce: f000 fca6 bl 800a31e <USBD_CtlError>
|
|
break;
|
|
80099d2: e01b b.n 8009a0c <USBD_StdEPReq+0x110>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
80099d4: 683b ldr r3, [r7, #0]
|
|
80099d6: 885b ldrh r3, [r3, #2]
|
|
80099d8: 2b00 cmp r3, #0
|
|
80099da: d10e bne.n 80099fa <USBD_StdEPReq+0xfe>
|
|
{
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U))
|
|
80099dc: 7bbb ldrb r3, [r7, #14]
|
|
80099de: 2b00 cmp r3, #0
|
|
80099e0: d00b beq.n 80099fa <USBD_StdEPReq+0xfe>
|
|
80099e2: 7bbb ldrb r3, [r7, #14]
|
|
80099e4: 2b80 cmp r3, #128 @ 0x80
|
|
80099e6: d008 beq.n 80099fa <USBD_StdEPReq+0xfe>
|
|
80099e8: 683b ldr r3, [r7, #0]
|
|
80099ea: 88db ldrh r3, [r3, #6]
|
|
80099ec: 2b00 cmp r3, #0
|
|
80099ee: d104 bne.n 80099fa <USBD_StdEPReq+0xfe>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
80099f0: 7bbb ldrb r3, [r7, #14]
|
|
80099f2: 4619 mov r1, r3
|
|
80099f4: 6878 ldr r0, [r7, #4]
|
|
80099f6: f001 f8c5 bl 800ab84 <USBD_LL_StallEP>
|
|
}
|
|
}
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80099fa: 6878 ldr r0, [r7, #4]
|
|
80099fc: f000 fd4c bl 800a498 <USBD_CtlSendStatus>
|
|
|
|
break;
|
|
8009a00: e004 b.n 8009a0c <USBD_StdEPReq+0x110>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8009a02: 6839 ldr r1, [r7, #0]
|
|
8009a04: 6878 ldr r0, [r7, #4]
|
|
8009a06: f000 fc8a bl 800a31e <USBD_CtlError>
|
|
break;
|
|
8009a0a: bf00 nop
|
|
}
|
|
break;
|
|
8009a0c: e109 b.n 8009c22 <USBD_StdEPReq+0x326>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
|
|
switch (pdev->dev_state)
|
|
8009a0e: 687b ldr r3, [r7, #4]
|
|
8009a10: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009a14: b2db uxtb r3, r3
|
|
8009a16: 2b02 cmp r3, #2
|
|
8009a18: d002 beq.n 8009a20 <USBD_StdEPReq+0x124>
|
|
8009a1a: 2b03 cmp r3, #3
|
|
8009a1c: d016 beq.n 8009a4c <USBD_StdEPReq+0x150>
|
|
8009a1e: e04b b.n 8009ab8 <USBD_StdEPReq+0x1bc>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
8009a20: 7bbb ldrb r3, [r7, #14]
|
|
8009a22: 2b00 cmp r3, #0
|
|
8009a24: d00d beq.n 8009a42 <USBD_StdEPReq+0x146>
|
|
8009a26: 7bbb ldrb r3, [r7, #14]
|
|
8009a28: 2b80 cmp r3, #128 @ 0x80
|
|
8009a2a: d00a beq.n 8009a42 <USBD_StdEPReq+0x146>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
8009a2c: 7bbb ldrb r3, [r7, #14]
|
|
8009a2e: 4619 mov r1, r3
|
|
8009a30: 6878 ldr r0, [r7, #4]
|
|
8009a32: f001 f8a7 bl 800ab84 <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8009a36: 2180 movs r1, #128 @ 0x80
|
|
8009a38: 6878 ldr r0, [r7, #4]
|
|
8009a3a: f001 f8a3 bl 800ab84 <USBD_LL_StallEP>
|
|
8009a3e: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
8009a40: e040 b.n 8009ac4 <USBD_StdEPReq+0x1c8>
|
|
USBD_CtlError(pdev, req);
|
|
8009a42: 6839 ldr r1, [r7, #0]
|
|
8009a44: 6878 ldr r0, [r7, #4]
|
|
8009a46: f000 fc6a bl 800a31e <USBD_CtlError>
|
|
break;
|
|
8009a4a: e03b b.n 8009ac4 <USBD_StdEPReq+0x1c8>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
8009a4c: 683b ldr r3, [r7, #0]
|
|
8009a4e: 885b ldrh r3, [r3, #2]
|
|
8009a50: 2b00 cmp r3, #0
|
|
8009a52: d136 bne.n 8009ac2 <USBD_StdEPReq+0x1c6>
|
|
{
|
|
if ((ep_addr & 0x7FU) != 0x00U)
|
|
8009a54: 7bbb ldrb r3, [r7, #14]
|
|
8009a56: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8009a5a: 2b00 cmp r3, #0
|
|
8009a5c: d004 beq.n 8009a68 <USBD_StdEPReq+0x16c>
|
|
{
|
|
(void)USBD_LL_ClearStallEP(pdev, ep_addr);
|
|
8009a5e: 7bbb ldrb r3, [r7, #14]
|
|
8009a60: 4619 mov r1, r3
|
|
8009a62: 6878 ldr r0, [r7, #4]
|
|
8009a64: f001 f8ad bl 800abc2 <USBD_LL_ClearStallEP>
|
|
}
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009a68: 6878 ldr r0, [r7, #4]
|
|
8009a6a: f000 fd15 bl 800a498 <USBD_CtlSendStatus>
|
|
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, ep_addr);
|
|
8009a6e: 7bbb ldrb r3, [r7, #14]
|
|
8009a70: 4619 mov r1, r3
|
|
8009a72: 6878 ldr r0, [r7, #4]
|
|
8009a74: f7ff fde3 bl 800963e <USBD_CoreFindEP>
|
|
8009a78: 4603 mov r3, r0
|
|
8009a7a: 737b strb r3, [r7, #13]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8009a7c: 7b7b ldrb r3, [r7, #13]
|
|
8009a7e: 2bff cmp r3, #255 @ 0xff
|
|
8009a80: d01f beq.n 8009ac2 <USBD_StdEPReq+0x1c6>
|
|
8009a82: 7b7b ldrb r3, [r7, #13]
|
|
8009a84: 2b00 cmp r3, #0
|
|
8009a86: d11c bne.n 8009ac2 <USBD_StdEPReq+0x1c6>
|
|
{
|
|
pdev->classId = idx;
|
|
8009a88: 7b7a ldrb r2, [r7, #13]
|
|
8009a8a: 687b ldr r3, [r7, #4]
|
|
8009a8c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8009a90: 7b7a ldrb r2, [r7, #13]
|
|
8009a92: 687b ldr r3, [r7, #4]
|
|
8009a94: 32ae adds r2, #174 @ 0xae
|
|
8009a96: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009a9a: 689b ldr r3, [r3, #8]
|
|
8009a9c: 2b00 cmp r3, #0
|
|
8009a9e: d010 beq.n 8009ac2 <USBD_StdEPReq+0x1c6>
|
|
{
|
|
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
|
|
8009aa0: 7b7a ldrb r2, [r7, #13]
|
|
8009aa2: 687b ldr r3, [r7, #4]
|
|
8009aa4: 32ae adds r2, #174 @ 0xae
|
|
8009aa6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009aaa: 689b ldr r3, [r3, #8]
|
|
8009aac: 6839 ldr r1, [r7, #0]
|
|
8009aae: 6878 ldr r0, [r7, #4]
|
|
8009ab0: 4798 blx r3
|
|
8009ab2: 4603 mov r3, r0
|
|
8009ab4: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
8009ab6: e004 b.n 8009ac2 <USBD_StdEPReq+0x1c6>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8009ab8: 6839 ldr r1, [r7, #0]
|
|
8009aba: 6878 ldr r0, [r7, #4]
|
|
8009abc: f000 fc2f bl 800a31e <USBD_CtlError>
|
|
break;
|
|
8009ac0: e000 b.n 8009ac4 <USBD_StdEPReq+0x1c8>
|
|
break;
|
|
8009ac2: bf00 nop
|
|
}
|
|
break;
|
|
8009ac4: e0ad b.n 8009c22 <USBD_StdEPReq+0x326>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
switch (pdev->dev_state)
|
|
8009ac6: 687b ldr r3, [r7, #4]
|
|
8009ac8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009acc: b2db uxtb r3, r3
|
|
8009ace: 2b02 cmp r3, #2
|
|
8009ad0: d002 beq.n 8009ad8 <USBD_StdEPReq+0x1dc>
|
|
8009ad2: 2b03 cmp r3, #3
|
|
8009ad4: d033 beq.n 8009b3e <USBD_StdEPReq+0x242>
|
|
8009ad6: e099 b.n 8009c0c <USBD_StdEPReq+0x310>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
8009ad8: 7bbb ldrb r3, [r7, #14]
|
|
8009ada: 2b00 cmp r3, #0
|
|
8009adc: d007 beq.n 8009aee <USBD_StdEPReq+0x1f2>
|
|
8009ade: 7bbb ldrb r3, [r7, #14]
|
|
8009ae0: 2b80 cmp r3, #128 @ 0x80
|
|
8009ae2: d004 beq.n 8009aee <USBD_StdEPReq+0x1f2>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009ae4: 6839 ldr r1, [r7, #0]
|
|
8009ae6: 6878 ldr r0, [r7, #4]
|
|
8009ae8: f000 fc19 bl 800a31e <USBD_CtlError>
|
|
break;
|
|
8009aec: e093 b.n 8009c16 <USBD_StdEPReq+0x31a>
|
|
}
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
8009aee: f997 300e ldrsb.w r3, [r7, #14]
|
|
8009af2: 2b00 cmp r3, #0
|
|
8009af4: da0b bge.n 8009b0e <USBD_StdEPReq+0x212>
|
|
8009af6: 7bbb ldrb r3, [r7, #14]
|
|
8009af8: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
8009afc: 4613 mov r3, r2
|
|
8009afe: 009b lsls r3, r3, #2
|
|
8009b00: 4413 add r3, r2
|
|
8009b02: 009b lsls r3, r3, #2
|
|
8009b04: 3310 adds r3, #16
|
|
8009b06: 687a ldr r2, [r7, #4]
|
|
8009b08: 4413 add r3, r2
|
|
8009b0a: 3304 adds r3, #4
|
|
8009b0c: e00b b.n 8009b26 <USBD_StdEPReq+0x22a>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
8009b0e: 7bbb ldrb r3, [r7, #14]
|
|
8009b10: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
8009b14: 4613 mov r3, r2
|
|
8009b16: 009b lsls r3, r3, #2
|
|
8009b18: 4413 add r3, r2
|
|
8009b1a: 009b lsls r3, r3, #2
|
|
8009b1c: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8009b20: 687a ldr r2, [r7, #4]
|
|
8009b22: 4413 add r3, r2
|
|
8009b24: 3304 adds r3, #4
|
|
8009b26: 60bb str r3, [r7, #8]
|
|
|
|
pep->status = 0x0000U;
|
|
8009b28: 68bb ldr r3, [r7, #8]
|
|
8009b2a: 2200 movs r2, #0
|
|
8009b2c: 739a strb r2, [r3, #14]
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
|
|
8009b2e: 68bb ldr r3, [r7, #8]
|
|
8009b30: 330e adds r3, #14
|
|
8009b32: 2202 movs r2, #2
|
|
8009b34: 4619 mov r1, r3
|
|
8009b36: 6878 ldr r0, [r7, #4]
|
|
8009b38: f000 fc6e bl 800a418 <USBD_CtlSendData>
|
|
break;
|
|
8009b3c: e06b b.n 8009c16 <USBD_StdEPReq+0x31a>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8009b3e: f997 300e ldrsb.w r3, [r7, #14]
|
|
8009b42: 2b00 cmp r3, #0
|
|
8009b44: da11 bge.n 8009b6a <USBD_StdEPReq+0x26e>
|
|
{
|
|
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
|
|
8009b46: 7bbb ldrb r3, [r7, #14]
|
|
8009b48: f003 020f and.w r2, r3, #15
|
|
8009b4c: 6879 ldr r1, [r7, #4]
|
|
8009b4e: 4613 mov r3, r2
|
|
8009b50: 009b lsls r3, r3, #2
|
|
8009b52: 4413 add r3, r2
|
|
8009b54: 009b lsls r3, r3, #2
|
|
8009b56: 440b add r3, r1
|
|
8009b58: 3323 adds r3, #35 @ 0x23
|
|
8009b5a: 781b ldrb r3, [r3, #0]
|
|
8009b5c: 2b00 cmp r3, #0
|
|
8009b5e: d117 bne.n 8009b90 <USBD_StdEPReq+0x294>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009b60: 6839 ldr r1, [r7, #0]
|
|
8009b62: 6878 ldr r0, [r7, #4]
|
|
8009b64: f000 fbdb bl 800a31e <USBD_CtlError>
|
|
break;
|
|
8009b68: e055 b.n 8009c16 <USBD_StdEPReq+0x31a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
|
|
8009b6a: 7bbb ldrb r3, [r7, #14]
|
|
8009b6c: f003 020f and.w r2, r3, #15
|
|
8009b70: 6879 ldr r1, [r7, #4]
|
|
8009b72: 4613 mov r3, r2
|
|
8009b74: 009b lsls r3, r3, #2
|
|
8009b76: 4413 add r3, r2
|
|
8009b78: 009b lsls r3, r3, #2
|
|
8009b7a: 440b add r3, r1
|
|
8009b7c: f203 1363 addw r3, r3, #355 @ 0x163
|
|
8009b80: 781b ldrb r3, [r3, #0]
|
|
8009b82: 2b00 cmp r3, #0
|
|
8009b84: d104 bne.n 8009b90 <USBD_StdEPReq+0x294>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009b86: 6839 ldr r1, [r7, #0]
|
|
8009b88: 6878 ldr r0, [r7, #4]
|
|
8009b8a: f000 fbc8 bl 800a31e <USBD_CtlError>
|
|
break;
|
|
8009b8e: e042 b.n 8009c16 <USBD_StdEPReq+0x31a>
|
|
}
|
|
}
|
|
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
8009b90: f997 300e ldrsb.w r3, [r7, #14]
|
|
8009b94: 2b00 cmp r3, #0
|
|
8009b96: da0b bge.n 8009bb0 <USBD_StdEPReq+0x2b4>
|
|
8009b98: 7bbb ldrb r3, [r7, #14]
|
|
8009b9a: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
8009b9e: 4613 mov r3, r2
|
|
8009ba0: 009b lsls r3, r3, #2
|
|
8009ba2: 4413 add r3, r2
|
|
8009ba4: 009b lsls r3, r3, #2
|
|
8009ba6: 3310 adds r3, #16
|
|
8009ba8: 687a ldr r2, [r7, #4]
|
|
8009baa: 4413 add r3, r2
|
|
8009bac: 3304 adds r3, #4
|
|
8009bae: e00b b.n 8009bc8 <USBD_StdEPReq+0x2cc>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
8009bb0: 7bbb ldrb r3, [r7, #14]
|
|
8009bb2: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
8009bb6: 4613 mov r3, r2
|
|
8009bb8: 009b lsls r3, r3, #2
|
|
8009bba: 4413 add r3, r2
|
|
8009bbc: 009b lsls r3, r3, #2
|
|
8009bbe: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8009bc2: 687a ldr r2, [r7, #4]
|
|
8009bc4: 4413 add r3, r2
|
|
8009bc6: 3304 adds r3, #4
|
|
8009bc8: 60bb str r3, [r7, #8]
|
|
|
|
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
|
|
8009bca: 7bbb ldrb r3, [r7, #14]
|
|
8009bcc: 2b00 cmp r3, #0
|
|
8009bce: d002 beq.n 8009bd6 <USBD_StdEPReq+0x2da>
|
|
8009bd0: 7bbb ldrb r3, [r7, #14]
|
|
8009bd2: 2b80 cmp r3, #128 @ 0x80
|
|
8009bd4: d103 bne.n 8009bde <USBD_StdEPReq+0x2e2>
|
|
{
|
|
pep->status = 0x0000U;
|
|
8009bd6: 68bb ldr r3, [r7, #8]
|
|
8009bd8: 2200 movs r2, #0
|
|
8009bda: 739a strb r2, [r3, #14]
|
|
8009bdc: e00e b.n 8009bfc <USBD_StdEPReq+0x300>
|
|
}
|
|
else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U)
|
|
8009bde: 7bbb ldrb r3, [r7, #14]
|
|
8009be0: 4619 mov r1, r3
|
|
8009be2: 6878 ldr r0, [r7, #4]
|
|
8009be4: f001 f80c bl 800ac00 <USBD_LL_IsStallEP>
|
|
8009be8: 4603 mov r3, r0
|
|
8009bea: 2b00 cmp r3, #0
|
|
8009bec: d003 beq.n 8009bf6 <USBD_StdEPReq+0x2fa>
|
|
{
|
|
pep->status = 0x0001U;
|
|
8009bee: 68bb ldr r3, [r7, #8]
|
|
8009bf0: 2201 movs r2, #1
|
|
8009bf2: 739a strb r2, [r3, #14]
|
|
8009bf4: e002 b.n 8009bfc <USBD_StdEPReq+0x300>
|
|
}
|
|
else
|
|
{
|
|
pep->status = 0x0000U;
|
|
8009bf6: 68bb ldr r3, [r7, #8]
|
|
8009bf8: 2200 movs r2, #0
|
|
8009bfa: 739a strb r2, [r3, #14]
|
|
}
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
|
|
8009bfc: 68bb ldr r3, [r7, #8]
|
|
8009bfe: 330e adds r3, #14
|
|
8009c00: 2202 movs r2, #2
|
|
8009c02: 4619 mov r1, r3
|
|
8009c04: 6878 ldr r0, [r7, #4]
|
|
8009c06: f000 fc07 bl 800a418 <USBD_CtlSendData>
|
|
break;
|
|
8009c0a: e004 b.n 8009c16 <USBD_StdEPReq+0x31a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8009c0c: 6839 ldr r1, [r7, #0]
|
|
8009c0e: 6878 ldr r0, [r7, #4]
|
|
8009c10: f000 fb85 bl 800a31e <USBD_CtlError>
|
|
break;
|
|
8009c14: bf00 nop
|
|
}
|
|
break;
|
|
8009c16: e004 b.n 8009c22 <USBD_StdEPReq+0x326>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8009c18: 6839 ldr r1, [r7, #0]
|
|
8009c1a: 6878 ldr r0, [r7, #4]
|
|
8009c1c: f000 fb7f bl 800a31e <USBD_CtlError>
|
|
break;
|
|
8009c20: bf00 nop
|
|
}
|
|
break;
|
|
8009c22: e005 b.n 8009c30 <USBD_StdEPReq+0x334>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8009c24: 6839 ldr r1, [r7, #0]
|
|
8009c26: 6878 ldr r0, [r7, #4]
|
|
8009c28: f000 fb79 bl 800a31e <USBD_CtlError>
|
|
break;
|
|
8009c2c: e000 b.n 8009c30 <USBD_StdEPReq+0x334>
|
|
break;
|
|
8009c2e: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8009c30: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009c32: 4618 mov r0, r3
|
|
8009c34: 3710 adds r7, #16
|
|
8009c36: 46bd mov sp, r7
|
|
8009c38: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08009c3c <USBD_GetDescriptor>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009c3c: b580 push {r7, lr}
|
|
8009c3e: b084 sub sp, #16
|
|
8009c40: af00 add r7, sp, #0
|
|
8009c42: 6078 str r0, [r7, #4]
|
|
8009c44: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
8009c46: 2300 movs r3, #0
|
|
8009c48: 813b strh r3, [r7, #8]
|
|
uint8_t *pbuf = NULL;
|
|
8009c4a: 2300 movs r3, #0
|
|
8009c4c: 60fb str r3, [r7, #12]
|
|
uint8_t err = 0U;
|
|
8009c4e: 2300 movs r3, #0
|
|
8009c50: 72fb strb r3, [r7, #11]
|
|
|
|
switch (req->wValue >> 8)
|
|
8009c52: 683b ldr r3, [r7, #0]
|
|
8009c54: 885b ldrh r3, [r3, #2]
|
|
8009c56: 0a1b lsrs r3, r3, #8
|
|
8009c58: b29b uxth r3, r3
|
|
8009c5a: 3b01 subs r3, #1
|
|
8009c5c: 2b0e cmp r3, #14
|
|
8009c5e: f200 8152 bhi.w 8009f06 <USBD_GetDescriptor+0x2ca>
|
|
8009c62: a201 add r2, pc, #4 @ (adr r2, 8009c68 <USBD_GetDescriptor+0x2c>)
|
|
8009c64: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8009c68: 08009cd9 .word 0x08009cd9
|
|
8009c6c: 08009cf1 .word 0x08009cf1
|
|
8009c70: 08009d31 .word 0x08009d31
|
|
8009c74: 08009f07 .word 0x08009f07
|
|
8009c78: 08009f07 .word 0x08009f07
|
|
8009c7c: 08009ea7 .word 0x08009ea7
|
|
8009c80: 08009ed3 .word 0x08009ed3
|
|
8009c84: 08009f07 .word 0x08009f07
|
|
8009c88: 08009f07 .word 0x08009f07
|
|
8009c8c: 08009f07 .word 0x08009f07
|
|
8009c90: 08009f07 .word 0x08009f07
|
|
8009c94: 08009f07 .word 0x08009f07
|
|
8009c98: 08009f07 .word 0x08009f07
|
|
8009c9c: 08009f07 .word 0x08009f07
|
|
8009ca0: 08009ca5 .word 0x08009ca5
|
|
{
|
|
#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U))
|
|
case USB_DESC_TYPE_BOS:
|
|
if (pdev->pDesc->GetBOSDescriptor != NULL)
|
|
8009ca4: 687b ldr r3, [r7, #4]
|
|
8009ca6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009caa: 69db ldr r3, [r3, #28]
|
|
8009cac: 2b00 cmp r3, #0
|
|
8009cae: d00b beq.n 8009cc8 <USBD_GetDescriptor+0x8c>
|
|
{
|
|
pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
|
|
8009cb0: 687b ldr r3, [r7, #4]
|
|
8009cb2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009cb6: 69db ldr r3, [r3, #28]
|
|
8009cb8: 687a ldr r2, [r7, #4]
|
|
8009cba: 7c12 ldrb r2, [r2, #16]
|
|
8009cbc: f107 0108 add.w r1, r7, #8
|
|
8009cc0: 4610 mov r0, r2
|
|
8009cc2: 4798 blx r3
|
|
8009cc4: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8009cc6: e126 b.n 8009f16 <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
8009cc8: 6839 ldr r1, [r7, #0]
|
|
8009cca: 6878 ldr r0, [r7, #4]
|
|
8009ccc: f000 fb27 bl 800a31e <USBD_CtlError>
|
|
err++;
|
|
8009cd0: 7afb ldrb r3, [r7, #11]
|
|
8009cd2: 3301 adds r3, #1
|
|
8009cd4: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009cd6: e11e b.n 8009f16 <USBD_GetDescriptor+0x2da>
|
|
#endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */
|
|
case USB_DESC_TYPE_DEVICE:
|
|
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
|
|
8009cd8: 687b ldr r3, [r7, #4]
|
|
8009cda: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009cde: 681b ldr r3, [r3, #0]
|
|
8009ce0: 687a ldr r2, [r7, #4]
|
|
8009ce2: 7c12 ldrb r2, [r2, #16]
|
|
8009ce4: f107 0108 add.w r1, r7, #8
|
|
8009ce8: 4610 mov r0, r2
|
|
8009cea: 4798 blx r3
|
|
8009cec: 60f8 str r0, [r7, #12]
|
|
break;
|
|
8009cee: e112 b.n 8009f16 <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8009cf0: 687b ldr r3, [r7, #4]
|
|
8009cf2: 7c1b ldrb r3, [r3, #16]
|
|
8009cf4: 2b00 cmp r3, #0
|
|
8009cf6: d10d bne.n 8009d14 <USBD_GetDescriptor+0xd8>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len);
|
|
8009cf8: 687b ldr r3, [r7, #4]
|
|
8009cfa: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8009cfe: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8009d00: f107 0208 add.w r2, r7, #8
|
|
8009d04: 4610 mov r0, r2
|
|
8009d06: 4798 blx r3
|
|
8009d08: 60f8 str r0, [r7, #12]
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
8009d0a: 68fb ldr r3, [r7, #12]
|
|
8009d0c: 3301 adds r3, #1
|
|
8009d0e: 2202 movs r2, #2
|
|
8009d10: 701a strb r2, [r3, #0]
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
}
|
|
break;
|
|
8009d12: e100 b.n 8009f16 <USBD_GetDescriptor+0x2da>
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
|
|
8009d14: 687b ldr r3, [r7, #4]
|
|
8009d16: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8009d1a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8009d1c: f107 0208 add.w r2, r7, #8
|
|
8009d20: 4610 mov r0, r2
|
|
8009d22: 4798 blx r3
|
|
8009d24: 60f8 str r0, [r7, #12]
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
8009d26: 68fb ldr r3, [r7, #12]
|
|
8009d28: 3301 adds r3, #1
|
|
8009d2a: 2202 movs r2, #2
|
|
8009d2c: 701a strb r2, [r3, #0]
|
|
break;
|
|
8009d2e: e0f2 b.n 8009f16 <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_STRING:
|
|
switch ((uint8_t)(req->wValue))
|
|
8009d30: 683b ldr r3, [r7, #0]
|
|
8009d32: 885b ldrh r3, [r3, #2]
|
|
8009d34: b2db uxtb r3, r3
|
|
8009d36: 2b05 cmp r3, #5
|
|
8009d38: f200 80ac bhi.w 8009e94 <USBD_GetDescriptor+0x258>
|
|
8009d3c: a201 add r2, pc, #4 @ (adr r2, 8009d44 <USBD_GetDescriptor+0x108>)
|
|
8009d3e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8009d42: bf00 nop
|
|
8009d44: 08009d5d .word 0x08009d5d
|
|
8009d48: 08009d91 .word 0x08009d91
|
|
8009d4c: 08009dc5 .word 0x08009dc5
|
|
8009d50: 08009df9 .word 0x08009df9
|
|
8009d54: 08009e2d .word 0x08009e2d
|
|
8009d58: 08009e61 .word 0x08009e61
|
|
{
|
|
case USBD_IDX_LANGID_STR:
|
|
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
|
|
8009d5c: 687b ldr r3, [r7, #4]
|
|
8009d5e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009d62: 685b ldr r3, [r3, #4]
|
|
8009d64: 2b00 cmp r3, #0
|
|
8009d66: d00b beq.n 8009d80 <USBD_GetDescriptor+0x144>
|
|
{
|
|
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
|
|
8009d68: 687b ldr r3, [r7, #4]
|
|
8009d6a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009d6e: 685b ldr r3, [r3, #4]
|
|
8009d70: 687a ldr r2, [r7, #4]
|
|
8009d72: 7c12 ldrb r2, [r2, #16]
|
|
8009d74: f107 0108 add.w r1, r7, #8
|
|
8009d78: 4610 mov r0, r2
|
|
8009d7a: 4798 blx r3
|
|
8009d7c: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8009d7e: e091 b.n 8009ea4 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8009d80: 6839 ldr r1, [r7, #0]
|
|
8009d82: 6878 ldr r0, [r7, #4]
|
|
8009d84: f000 facb bl 800a31e <USBD_CtlError>
|
|
err++;
|
|
8009d88: 7afb ldrb r3, [r7, #11]
|
|
8009d8a: 3301 adds r3, #1
|
|
8009d8c: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009d8e: e089 b.n 8009ea4 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_MFC_STR:
|
|
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
|
|
8009d90: 687b ldr r3, [r7, #4]
|
|
8009d92: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009d96: 689b ldr r3, [r3, #8]
|
|
8009d98: 2b00 cmp r3, #0
|
|
8009d9a: d00b beq.n 8009db4 <USBD_GetDescriptor+0x178>
|
|
{
|
|
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
|
|
8009d9c: 687b ldr r3, [r7, #4]
|
|
8009d9e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009da2: 689b ldr r3, [r3, #8]
|
|
8009da4: 687a ldr r2, [r7, #4]
|
|
8009da6: 7c12 ldrb r2, [r2, #16]
|
|
8009da8: f107 0108 add.w r1, r7, #8
|
|
8009dac: 4610 mov r0, r2
|
|
8009dae: 4798 blx r3
|
|
8009db0: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8009db2: e077 b.n 8009ea4 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8009db4: 6839 ldr r1, [r7, #0]
|
|
8009db6: 6878 ldr r0, [r7, #4]
|
|
8009db8: f000 fab1 bl 800a31e <USBD_CtlError>
|
|
err++;
|
|
8009dbc: 7afb ldrb r3, [r7, #11]
|
|
8009dbe: 3301 adds r3, #1
|
|
8009dc0: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009dc2: e06f b.n 8009ea4 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_PRODUCT_STR:
|
|
if (pdev->pDesc->GetProductStrDescriptor != NULL)
|
|
8009dc4: 687b ldr r3, [r7, #4]
|
|
8009dc6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009dca: 68db ldr r3, [r3, #12]
|
|
8009dcc: 2b00 cmp r3, #0
|
|
8009dce: d00b beq.n 8009de8 <USBD_GetDescriptor+0x1ac>
|
|
{
|
|
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
|
|
8009dd0: 687b ldr r3, [r7, #4]
|
|
8009dd2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009dd6: 68db ldr r3, [r3, #12]
|
|
8009dd8: 687a ldr r2, [r7, #4]
|
|
8009dda: 7c12 ldrb r2, [r2, #16]
|
|
8009ddc: f107 0108 add.w r1, r7, #8
|
|
8009de0: 4610 mov r0, r2
|
|
8009de2: 4798 blx r3
|
|
8009de4: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8009de6: e05d b.n 8009ea4 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8009de8: 6839 ldr r1, [r7, #0]
|
|
8009dea: 6878 ldr r0, [r7, #4]
|
|
8009dec: f000 fa97 bl 800a31e <USBD_CtlError>
|
|
err++;
|
|
8009df0: 7afb ldrb r3, [r7, #11]
|
|
8009df2: 3301 adds r3, #1
|
|
8009df4: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009df6: e055 b.n 8009ea4 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_SERIAL_STR:
|
|
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
|
|
8009df8: 687b ldr r3, [r7, #4]
|
|
8009dfa: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009dfe: 691b ldr r3, [r3, #16]
|
|
8009e00: 2b00 cmp r3, #0
|
|
8009e02: d00b beq.n 8009e1c <USBD_GetDescriptor+0x1e0>
|
|
{
|
|
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
|
|
8009e04: 687b ldr r3, [r7, #4]
|
|
8009e06: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009e0a: 691b ldr r3, [r3, #16]
|
|
8009e0c: 687a ldr r2, [r7, #4]
|
|
8009e0e: 7c12 ldrb r2, [r2, #16]
|
|
8009e10: f107 0108 add.w r1, r7, #8
|
|
8009e14: 4610 mov r0, r2
|
|
8009e16: 4798 blx r3
|
|
8009e18: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8009e1a: e043 b.n 8009ea4 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8009e1c: 6839 ldr r1, [r7, #0]
|
|
8009e1e: 6878 ldr r0, [r7, #4]
|
|
8009e20: f000 fa7d bl 800a31e <USBD_CtlError>
|
|
err++;
|
|
8009e24: 7afb ldrb r3, [r7, #11]
|
|
8009e26: 3301 adds r3, #1
|
|
8009e28: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009e2a: e03b b.n 8009ea4 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_CONFIG_STR:
|
|
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
|
|
8009e2c: 687b ldr r3, [r7, #4]
|
|
8009e2e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009e32: 695b ldr r3, [r3, #20]
|
|
8009e34: 2b00 cmp r3, #0
|
|
8009e36: d00b beq.n 8009e50 <USBD_GetDescriptor+0x214>
|
|
{
|
|
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
|
|
8009e38: 687b ldr r3, [r7, #4]
|
|
8009e3a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009e3e: 695b ldr r3, [r3, #20]
|
|
8009e40: 687a ldr r2, [r7, #4]
|
|
8009e42: 7c12 ldrb r2, [r2, #16]
|
|
8009e44: f107 0108 add.w r1, r7, #8
|
|
8009e48: 4610 mov r0, r2
|
|
8009e4a: 4798 blx r3
|
|
8009e4c: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8009e4e: e029 b.n 8009ea4 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8009e50: 6839 ldr r1, [r7, #0]
|
|
8009e52: 6878 ldr r0, [r7, #4]
|
|
8009e54: f000 fa63 bl 800a31e <USBD_CtlError>
|
|
err++;
|
|
8009e58: 7afb ldrb r3, [r7, #11]
|
|
8009e5a: 3301 adds r3, #1
|
|
8009e5c: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009e5e: e021 b.n 8009ea4 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_INTERFACE_STR:
|
|
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
|
|
8009e60: 687b ldr r3, [r7, #4]
|
|
8009e62: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009e66: 699b ldr r3, [r3, #24]
|
|
8009e68: 2b00 cmp r3, #0
|
|
8009e6a: d00b beq.n 8009e84 <USBD_GetDescriptor+0x248>
|
|
{
|
|
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
|
|
8009e6c: 687b ldr r3, [r7, #4]
|
|
8009e6e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009e72: 699b ldr r3, [r3, #24]
|
|
8009e74: 687a ldr r2, [r7, #4]
|
|
8009e76: 7c12 ldrb r2, [r2, #16]
|
|
8009e78: f107 0108 add.w r1, r7, #8
|
|
8009e7c: 4610 mov r0, r2
|
|
8009e7e: 4798 blx r3
|
|
8009e80: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8009e82: e00f b.n 8009ea4 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8009e84: 6839 ldr r1, [r7, #0]
|
|
8009e86: 6878 ldr r0, [r7, #4]
|
|
8009e88: f000 fa49 bl 800a31e <USBD_CtlError>
|
|
err++;
|
|
8009e8c: 7afb ldrb r3, [r7, #11]
|
|
8009e8e: 3301 adds r3, #1
|
|
8009e90: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009e92: e007 b.n 8009ea4 <USBD_GetDescriptor+0x268>
|
|
err++;
|
|
}
|
|
#endif /* USBD_SUPPORT_USER_STRING_DESC */
|
|
|
|
#if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U))
|
|
USBD_CtlError(pdev, req);
|
|
8009e94: 6839 ldr r1, [r7, #0]
|
|
8009e96: 6878 ldr r0, [r7, #4]
|
|
8009e98: f000 fa41 bl 800a31e <USBD_CtlError>
|
|
err++;
|
|
8009e9c: 7afb ldrb r3, [r7, #11]
|
|
8009e9e: 3301 adds r3, #1
|
|
8009ea0: 72fb strb r3, [r7, #11]
|
|
#endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */
|
|
break;
|
|
8009ea2: bf00 nop
|
|
}
|
|
break;
|
|
8009ea4: e037 b.n 8009f16 <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_DEVICE_QUALIFIER:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8009ea6: 687b ldr r3, [r7, #4]
|
|
8009ea8: 7c1b ldrb r3, [r3, #16]
|
|
8009eaa: 2b00 cmp r3, #0
|
|
8009eac: d109 bne.n 8009ec2 <USBD_GetDescriptor+0x286>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len);
|
|
8009eae: 687b ldr r3, [r7, #4]
|
|
8009eb0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8009eb4: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8009eb6: f107 0208 add.w r2, r7, #8
|
|
8009eba: 4610 mov r0, r2
|
|
8009ebc: 4798 blx r3
|
|
8009ebe: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8009ec0: e029 b.n 8009f16 <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
8009ec2: 6839 ldr r1, [r7, #0]
|
|
8009ec4: 6878 ldr r0, [r7, #4]
|
|
8009ec6: f000 fa2a bl 800a31e <USBD_CtlError>
|
|
err++;
|
|
8009eca: 7afb ldrb r3, [r7, #11]
|
|
8009ecc: 3301 adds r3, #1
|
|
8009ece: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009ed0: e021 b.n 8009f16 <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8009ed2: 687b ldr r3, [r7, #4]
|
|
8009ed4: 7c1b ldrb r3, [r3, #16]
|
|
8009ed6: 2b00 cmp r3, #0
|
|
8009ed8: d10d bne.n 8009ef6 <USBD_GetDescriptor+0x2ba>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len);
|
|
8009eda: 687b ldr r3, [r7, #4]
|
|
8009edc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8009ee0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8009ee2: f107 0208 add.w r2, r7, #8
|
|
8009ee6: 4610 mov r0, r2
|
|
8009ee8: 4798 blx r3
|
|
8009eea: 60f8 str r0, [r7, #12]
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
|
|
8009eec: 68fb ldr r3, [r7, #12]
|
|
8009eee: 3301 adds r3, #1
|
|
8009ef0: 2207 movs r2, #7
|
|
8009ef2: 701a strb r2, [r3, #0]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8009ef4: e00f b.n 8009f16 <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
8009ef6: 6839 ldr r1, [r7, #0]
|
|
8009ef8: 6878 ldr r0, [r7, #4]
|
|
8009efa: f000 fa10 bl 800a31e <USBD_CtlError>
|
|
err++;
|
|
8009efe: 7afb ldrb r3, [r7, #11]
|
|
8009f00: 3301 adds r3, #1
|
|
8009f02: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009f04: e007 b.n 8009f16 <USBD_GetDescriptor+0x2da>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8009f06: 6839 ldr r1, [r7, #0]
|
|
8009f08: 6878 ldr r0, [r7, #4]
|
|
8009f0a: f000 fa08 bl 800a31e <USBD_CtlError>
|
|
err++;
|
|
8009f0e: 7afb ldrb r3, [r7, #11]
|
|
8009f10: 3301 adds r3, #1
|
|
8009f12: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009f14: bf00 nop
|
|
}
|
|
|
|
if (err != 0U)
|
|
8009f16: 7afb ldrb r3, [r7, #11]
|
|
8009f18: 2b00 cmp r3, #0
|
|
8009f1a: d11e bne.n 8009f5a <USBD_GetDescriptor+0x31e>
|
|
{
|
|
return;
|
|
}
|
|
|
|
if (req->wLength != 0U)
|
|
8009f1c: 683b ldr r3, [r7, #0]
|
|
8009f1e: 88db ldrh r3, [r3, #6]
|
|
8009f20: 2b00 cmp r3, #0
|
|
8009f22: d016 beq.n 8009f52 <USBD_GetDescriptor+0x316>
|
|
{
|
|
if (len != 0U)
|
|
8009f24: 893b ldrh r3, [r7, #8]
|
|
8009f26: 2b00 cmp r3, #0
|
|
8009f28: d00e beq.n 8009f48 <USBD_GetDescriptor+0x30c>
|
|
{
|
|
len = MIN(len, req->wLength);
|
|
8009f2a: 683b ldr r3, [r7, #0]
|
|
8009f2c: 88da ldrh r2, [r3, #6]
|
|
8009f2e: 893b ldrh r3, [r7, #8]
|
|
8009f30: 4293 cmp r3, r2
|
|
8009f32: bf28 it cs
|
|
8009f34: 4613 movcs r3, r2
|
|
8009f36: b29b uxth r3, r3
|
|
8009f38: 813b strh r3, [r7, #8]
|
|
(void)USBD_CtlSendData(pdev, pbuf, len);
|
|
8009f3a: 893b ldrh r3, [r7, #8]
|
|
8009f3c: 461a mov r2, r3
|
|
8009f3e: 68f9 ldr r1, [r7, #12]
|
|
8009f40: 6878 ldr r0, [r7, #4]
|
|
8009f42: f000 fa69 bl 800a418 <USBD_CtlSendData>
|
|
8009f46: e009 b.n 8009f5c <USBD_GetDescriptor+0x320>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009f48: 6839 ldr r1, [r7, #0]
|
|
8009f4a: 6878 ldr r0, [r7, #4]
|
|
8009f4c: f000 f9e7 bl 800a31e <USBD_CtlError>
|
|
8009f50: e004 b.n 8009f5c <USBD_GetDescriptor+0x320>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009f52: 6878 ldr r0, [r7, #4]
|
|
8009f54: f000 faa0 bl 800a498 <USBD_CtlSendStatus>
|
|
8009f58: e000 b.n 8009f5c <USBD_GetDescriptor+0x320>
|
|
return;
|
|
8009f5a: bf00 nop
|
|
}
|
|
}
|
|
8009f5c: 3710 adds r7, #16
|
|
8009f5e: 46bd mov sp, r7
|
|
8009f60: bd80 pop {r7, pc}
|
|
8009f62: bf00 nop
|
|
|
|
08009f64 <USBD_SetAddress>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009f64: b580 push {r7, lr}
|
|
8009f66: b084 sub sp, #16
|
|
8009f68: af00 add r7, sp, #0
|
|
8009f6a: 6078 str r0, [r7, #4]
|
|
8009f6c: 6039 str r1, [r7, #0]
|
|
uint8_t dev_addr;
|
|
|
|
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
|
|
8009f6e: 683b ldr r3, [r7, #0]
|
|
8009f70: 889b ldrh r3, [r3, #4]
|
|
8009f72: 2b00 cmp r3, #0
|
|
8009f74: d131 bne.n 8009fda <USBD_SetAddress+0x76>
|
|
8009f76: 683b ldr r3, [r7, #0]
|
|
8009f78: 88db ldrh r3, [r3, #6]
|
|
8009f7a: 2b00 cmp r3, #0
|
|
8009f7c: d12d bne.n 8009fda <USBD_SetAddress+0x76>
|
|
8009f7e: 683b ldr r3, [r7, #0]
|
|
8009f80: 885b ldrh r3, [r3, #2]
|
|
8009f82: 2b7f cmp r3, #127 @ 0x7f
|
|
8009f84: d829 bhi.n 8009fda <USBD_SetAddress+0x76>
|
|
{
|
|
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
|
|
8009f86: 683b ldr r3, [r7, #0]
|
|
8009f88: 885b ldrh r3, [r3, #2]
|
|
8009f8a: b2db uxtb r3, r3
|
|
8009f8c: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8009f90: 73fb strb r3, [r7, #15]
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8009f92: 687b ldr r3, [r7, #4]
|
|
8009f94: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009f98: b2db uxtb r3, r3
|
|
8009f9a: 2b03 cmp r3, #3
|
|
8009f9c: d104 bne.n 8009fa8 <USBD_SetAddress+0x44>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009f9e: 6839 ldr r1, [r7, #0]
|
|
8009fa0: 6878 ldr r0, [r7, #4]
|
|
8009fa2: f000 f9bc bl 800a31e <USBD_CtlError>
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8009fa6: e01d b.n 8009fe4 <USBD_SetAddress+0x80>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_address = dev_addr;
|
|
8009fa8: 687b ldr r3, [r7, #4]
|
|
8009faa: 7bfa ldrb r2, [r7, #15]
|
|
8009fac: f883 229e strb.w r2, [r3, #670] @ 0x29e
|
|
(void)USBD_LL_SetUSBAddress(pdev, dev_addr);
|
|
8009fb0: 7bfb ldrb r3, [r7, #15]
|
|
8009fb2: 4619 mov r1, r3
|
|
8009fb4: 6878 ldr r0, [r7, #4]
|
|
8009fb6: f000 fe4f bl 800ac58 <USBD_LL_SetUSBAddress>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009fba: 6878 ldr r0, [r7, #4]
|
|
8009fbc: f000 fa6c bl 800a498 <USBD_CtlSendStatus>
|
|
|
|
if (dev_addr != 0U)
|
|
8009fc0: 7bfb ldrb r3, [r7, #15]
|
|
8009fc2: 2b00 cmp r3, #0
|
|
8009fc4: d004 beq.n 8009fd0 <USBD_SetAddress+0x6c>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8009fc6: 687b ldr r3, [r7, #4]
|
|
8009fc8: 2202 movs r2, #2
|
|
8009fca: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8009fce: e009 b.n 8009fe4 <USBD_SetAddress+0x80>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8009fd0: 687b ldr r3, [r7, #4]
|
|
8009fd2: 2201 movs r2, #1
|
|
8009fd4: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8009fd8: e004 b.n 8009fe4 <USBD_SetAddress+0x80>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009fda: 6839 ldr r1, [r7, #0]
|
|
8009fdc: 6878 ldr r0, [r7, #4]
|
|
8009fde: f000 f99e bl 800a31e <USBD_CtlError>
|
|
}
|
|
}
|
|
8009fe2: bf00 nop
|
|
8009fe4: bf00 nop
|
|
8009fe6: 3710 adds r7, #16
|
|
8009fe8: 46bd mov sp, r7
|
|
8009fea: bd80 pop {r7, pc}
|
|
|
|
08009fec <USBD_SetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009fec: b580 push {r7, lr}
|
|
8009fee: b084 sub sp, #16
|
|
8009ff0: af00 add r7, sp, #0
|
|
8009ff2: 6078 str r0, [r7, #4]
|
|
8009ff4: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8009ff6: 2300 movs r3, #0
|
|
8009ff8: 73fb strb r3, [r7, #15]
|
|
static uint8_t cfgidx;
|
|
|
|
cfgidx = (uint8_t)(req->wValue);
|
|
8009ffa: 683b ldr r3, [r7, #0]
|
|
8009ffc: 885b ldrh r3, [r3, #2]
|
|
8009ffe: b2da uxtb r2, r3
|
|
800a000: 4b4e ldr r3, [pc, #312] @ (800a13c <USBD_SetConfig+0x150>)
|
|
800a002: 701a strb r2, [r3, #0]
|
|
|
|
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
|
|
800a004: 4b4d ldr r3, [pc, #308] @ (800a13c <USBD_SetConfig+0x150>)
|
|
800a006: 781b ldrb r3, [r3, #0]
|
|
800a008: 2b01 cmp r3, #1
|
|
800a00a: d905 bls.n 800a018 <USBD_SetConfig+0x2c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
800a00c: 6839 ldr r1, [r7, #0]
|
|
800a00e: 6878 ldr r0, [r7, #4]
|
|
800a010: f000 f985 bl 800a31e <USBD_CtlError>
|
|
return USBD_FAIL;
|
|
800a014: 2303 movs r3, #3
|
|
800a016: e08c b.n 800a132 <USBD_SetConfig+0x146>
|
|
}
|
|
|
|
switch (pdev->dev_state)
|
|
800a018: 687b ldr r3, [r7, #4]
|
|
800a01a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
800a01e: b2db uxtb r3, r3
|
|
800a020: 2b02 cmp r3, #2
|
|
800a022: d002 beq.n 800a02a <USBD_SetConfig+0x3e>
|
|
800a024: 2b03 cmp r3, #3
|
|
800a026: d029 beq.n 800a07c <USBD_SetConfig+0x90>
|
|
800a028: e075 b.n 800a116 <USBD_SetConfig+0x12a>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if (cfgidx != 0U)
|
|
800a02a: 4b44 ldr r3, [pc, #272] @ (800a13c <USBD_SetConfig+0x150>)
|
|
800a02c: 781b ldrb r3, [r3, #0]
|
|
800a02e: 2b00 cmp r3, #0
|
|
800a030: d020 beq.n 800a074 <USBD_SetConfig+0x88>
|
|
{
|
|
pdev->dev_config = cfgidx;
|
|
800a032: 4b42 ldr r3, [pc, #264] @ (800a13c <USBD_SetConfig+0x150>)
|
|
800a034: 781b ldrb r3, [r3, #0]
|
|
800a036: 461a mov r2, r3
|
|
800a038: 687b ldr r3, [r7, #4]
|
|
800a03a: 605a str r2, [r3, #4]
|
|
|
|
ret = USBD_SetClassConfig(pdev, cfgidx);
|
|
800a03c: 4b3f ldr r3, [pc, #252] @ (800a13c <USBD_SetConfig+0x150>)
|
|
800a03e: 781b ldrb r3, [r3, #0]
|
|
800a040: 4619 mov r1, r3
|
|
800a042: 6878 ldr r0, [r7, #4]
|
|
800a044: f7fe ffa3 bl 8008f8e <USBD_SetClassConfig>
|
|
800a048: 4603 mov r3, r0
|
|
800a04a: 73fb strb r3, [r7, #15]
|
|
|
|
if (ret != USBD_OK)
|
|
800a04c: 7bfb ldrb r3, [r7, #15]
|
|
800a04e: 2b00 cmp r3, #0
|
|
800a050: d008 beq.n 800a064 <USBD_SetConfig+0x78>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
800a052: 6839 ldr r1, [r7, #0]
|
|
800a054: 6878 ldr r0, [r7, #4]
|
|
800a056: f000 f962 bl 800a31e <USBD_CtlError>
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
800a05a: 687b ldr r3, [r7, #4]
|
|
800a05c: 2202 movs r2, #2
|
|
800a05e: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
800a062: e065 b.n 800a130 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800a064: 6878 ldr r0, [r7, #4]
|
|
800a066: f000 fa17 bl 800a498 <USBD_CtlSendStatus>
|
|
pdev->dev_state = USBD_STATE_CONFIGURED;
|
|
800a06a: 687b ldr r3, [r7, #4]
|
|
800a06c: 2203 movs r2, #3
|
|
800a06e: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
break;
|
|
800a072: e05d b.n 800a130 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800a074: 6878 ldr r0, [r7, #4]
|
|
800a076: f000 fa0f bl 800a498 <USBD_CtlSendStatus>
|
|
break;
|
|
800a07a: e059 b.n 800a130 <USBD_SetConfig+0x144>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (cfgidx == 0U)
|
|
800a07c: 4b2f ldr r3, [pc, #188] @ (800a13c <USBD_SetConfig+0x150>)
|
|
800a07e: 781b ldrb r3, [r3, #0]
|
|
800a080: 2b00 cmp r3, #0
|
|
800a082: d112 bne.n 800a0aa <USBD_SetConfig+0xbe>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
800a084: 687b ldr r3, [r7, #4]
|
|
800a086: 2202 movs r2, #2
|
|
800a088: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->dev_config = cfgidx;
|
|
800a08c: 4b2b ldr r3, [pc, #172] @ (800a13c <USBD_SetConfig+0x150>)
|
|
800a08e: 781b ldrb r3, [r3, #0]
|
|
800a090: 461a mov r2, r3
|
|
800a092: 687b ldr r3, [r7, #4]
|
|
800a094: 605a str r2, [r3, #4]
|
|
(void)USBD_ClrClassConfig(pdev, cfgidx);
|
|
800a096: 4b29 ldr r3, [pc, #164] @ (800a13c <USBD_SetConfig+0x150>)
|
|
800a098: 781b ldrb r3, [r3, #0]
|
|
800a09a: 4619 mov r1, r3
|
|
800a09c: 6878 ldr r0, [r7, #4]
|
|
800a09e: f7fe ff92 bl 8008fc6 <USBD_ClrClassConfig>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800a0a2: 6878 ldr r0, [r7, #4]
|
|
800a0a4: f000 f9f8 bl 800a498 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
800a0a8: e042 b.n 800a130 <USBD_SetConfig+0x144>
|
|
else if (cfgidx != pdev->dev_config)
|
|
800a0aa: 4b24 ldr r3, [pc, #144] @ (800a13c <USBD_SetConfig+0x150>)
|
|
800a0ac: 781b ldrb r3, [r3, #0]
|
|
800a0ae: 461a mov r2, r3
|
|
800a0b0: 687b ldr r3, [r7, #4]
|
|
800a0b2: 685b ldr r3, [r3, #4]
|
|
800a0b4: 429a cmp r2, r3
|
|
800a0b6: d02a beq.n 800a10e <USBD_SetConfig+0x122>
|
|
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
800a0b8: 687b ldr r3, [r7, #4]
|
|
800a0ba: 685b ldr r3, [r3, #4]
|
|
800a0bc: b2db uxtb r3, r3
|
|
800a0be: 4619 mov r1, r3
|
|
800a0c0: 6878 ldr r0, [r7, #4]
|
|
800a0c2: f7fe ff80 bl 8008fc6 <USBD_ClrClassConfig>
|
|
pdev->dev_config = cfgidx;
|
|
800a0c6: 4b1d ldr r3, [pc, #116] @ (800a13c <USBD_SetConfig+0x150>)
|
|
800a0c8: 781b ldrb r3, [r3, #0]
|
|
800a0ca: 461a mov r2, r3
|
|
800a0cc: 687b ldr r3, [r7, #4]
|
|
800a0ce: 605a str r2, [r3, #4]
|
|
ret = USBD_SetClassConfig(pdev, cfgidx);
|
|
800a0d0: 4b1a ldr r3, [pc, #104] @ (800a13c <USBD_SetConfig+0x150>)
|
|
800a0d2: 781b ldrb r3, [r3, #0]
|
|
800a0d4: 4619 mov r1, r3
|
|
800a0d6: 6878 ldr r0, [r7, #4]
|
|
800a0d8: f7fe ff59 bl 8008f8e <USBD_SetClassConfig>
|
|
800a0dc: 4603 mov r3, r0
|
|
800a0de: 73fb strb r3, [r7, #15]
|
|
if (ret != USBD_OK)
|
|
800a0e0: 7bfb ldrb r3, [r7, #15]
|
|
800a0e2: 2b00 cmp r3, #0
|
|
800a0e4: d00f beq.n 800a106 <USBD_SetConfig+0x11a>
|
|
USBD_CtlError(pdev, req);
|
|
800a0e6: 6839 ldr r1, [r7, #0]
|
|
800a0e8: 6878 ldr r0, [r7, #4]
|
|
800a0ea: f000 f918 bl 800a31e <USBD_CtlError>
|
|
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
800a0ee: 687b ldr r3, [r7, #4]
|
|
800a0f0: 685b ldr r3, [r3, #4]
|
|
800a0f2: b2db uxtb r3, r3
|
|
800a0f4: 4619 mov r1, r3
|
|
800a0f6: 6878 ldr r0, [r7, #4]
|
|
800a0f8: f7fe ff65 bl 8008fc6 <USBD_ClrClassConfig>
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
800a0fc: 687b ldr r3, [r7, #4]
|
|
800a0fe: 2202 movs r2, #2
|
|
800a100: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
break;
|
|
800a104: e014 b.n 800a130 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800a106: 6878 ldr r0, [r7, #4]
|
|
800a108: f000 f9c6 bl 800a498 <USBD_CtlSendStatus>
|
|
break;
|
|
800a10c: e010 b.n 800a130 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800a10e: 6878 ldr r0, [r7, #4]
|
|
800a110: f000 f9c2 bl 800a498 <USBD_CtlSendStatus>
|
|
break;
|
|
800a114: e00c b.n 800a130 <USBD_SetConfig+0x144>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800a116: 6839 ldr r1, [r7, #0]
|
|
800a118: 6878 ldr r0, [r7, #4]
|
|
800a11a: f000 f900 bl 800a31e <USBD_CtlError>
|
|
(void)USBD_ClrClassConfig(pdev, cfgidx);
|
|
800a11e: 4b07 ldr r3, [pc, #28] @ (800a13c <USBD_SetConfig+0x150>)
|
|
800a120: 781b ldrb r3, [r3, #0]
|
|
800a122: 4619 mov r1, r3
|
|
800a124: 6878 ldr r0, [r7, #4]
|
|
800a126: f7fe ff4e bl 8008fc6 <USBD_ClrClassConfig>
|
|
ret = USBD_FAIL;
|
|
800a12a: 2303 movs r3, #3
|
|
800a12c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800a12e: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
800a130: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800a132: 4618 mov r0, r3
|
|
800a134: 3710 adds r7, #16
|
|
800a136: 46bd mov sp, r7
|
|
800a138: bd80 pop {r7, pc}
|
|
800a13a: bf00 nop
|
|
800a13c: 20000d84 .word 0x20000d84
|
|
|
|
0800a140 <USBD_GetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
800a140: b580 push {r7, lr}
|
|
800a142: b082 sub sp, #8
|
|
800a144: af00 add r7, sp, #0
|
|
800a146: 6078 str r0, [r7, #4]
|
|
800a148: 6039 str r1, [r7, #0]
|
|
if (req->wLength != 1U)
|
|
800a14a: 683b ldr r3, [r7, #0]
|
|
800a14c: 88db ldrh r3, [r3, #6]
|
|
800a14e: 2b01 cmp r3, #1
|
|
800a150: d004 beq.n 800a15c <USBD_GetConfig+0x1c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
800a152: 6839 ldr r1, [r7, #0]
|
|
800a154: 6878 ldr r0, [r7, #4]
|
|
800a156: f000 f8e2 bl 800a31e <USBD_CtlError>
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
800a15a: e023 b.n 800a1a4 <USBD_GetConfig+0x64>
|
|
switch (pdev->dev_state)
|
|
800a15c: 687b ldr r3, [r7, #4]
|
|
800a15e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
800a162: b2db uxtb r3, r3
|
|
800a164: 2b02 cmp r3, #2
|
|
800a166: dc02 bgt.n 800a16e <USBD_GetConfig+0x2e>
|
|
800a168: 2b00 cmp r3, #0
|
|
800a16a: dc03 bgt.n 800a174 <USBD_GetConfig+0x34>
|
|
800a16c: e015 b.n 800a19a <USBD_GetConfig+0x5a>
|
|
800a16e: 2b03 cmp r3, #3
|
|
800a170: d00b beq.n 800a18a <USBD_GetConfig+0x4a>
|
|
800a172: e012 b.n 800a19a <USBD_GetConfig+0x5a>
|
|
pdev->dev_default_config = 0U;
|
|
800a174: 687b ldr r3, [r7, #4]
|
|
800a176: 2200 movs r2, #0
|
|
800a178: 609a str r2, [r3, #8]
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
|
|
800a17a: 687b ldr r3, [r7, #4]
|
|
800a17c: 3308 adds r3, #8
|
|
800a17e: 2201 movs r2, #1
|
|
800a180: 4619 mov r1, r3
|
|
800a182: 6878 ldr r0, [r7, #4]
|
|
800a184: f000 f948 bl 800a418 <USBD_CtlSendData>
|
|
break;
|
|
800a188: e00c b.n 800a1a4 <USBD_GetConfig+0x64>
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U);
|
|
800a18a: 687b ldr r3, [r7, #4]
|
|
800a18c: 3304 adds r3, #4
|
|
800a18e: 2201 movs r2, #1
|
|
800a190: 4619 mov r1, r3
|
|
800a192: 6878 ldr r0, [r7, #4]
|
|
800a194: f000 f940 bl 800a418 <USBD_CtlSendData>
|
|
break;
|
|
800a198: e004 b.n 800a1a4 <USBD_GetConfig+0x64>
|
|
USBD_CtlError(pdev, req);
|
|
800a19a: 6839 ldr r1, [r7, #0]
|
|
800a19c: 6878 ldr r0, [r7, #4]
|
|
800a19e: f000 f8be bl 800a31e <USBD_CtlError>
|
|
break;
|
|
800a1a2: bf00 nop
|
|
}
|
|
800a1a4: bf00 nop
|
|
800a1a6: 3708 adds r7, #8
|
|
800a1a8: 46bd mov sp, r7
|
|
800a1aa: bd80 pop {r7, pc}
|
|
|
|
0800a1ac <USBD_GetStatus>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
800a1ac: b580 push {r7, lr}
|
|
800a1ae: b082 sub sp, #8
|
|
800a1b0: af00 add r7, sp, #0
|
|
800a1b2: 6078 str r0, [r7, #4]
|
|
800a1b4: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
800a1b6: 687b ldr r3, [r7, #4]
|
|
800a1b8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
800a1bc: b2db uxtb r3, r3
|
|
800a1be: 3b01 subs r3, #1
|
|
800a1c0: 2b02 cmp r3, #2
|
|
800a1c2: d81e bhi.n 800a202 <USBD_GetStatus+0x56>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wLength != 0x2U)
|
|
800a1c4: 683b ldr r3, [r7, #0]
|
|
800a1c6: 88db ldrh r3, [r3, #6]
|
|
800a1c8: 2b02 cmp r3, #2
|
|
800a1ca: d004 beq.n 800a1d6 <USBD_GetStatus+0x2a>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
800a1cc: 6839 ldr r1, [r7, #0]
|
|
800a1ce: 6878 ldr r0, [r7, #4]
|
|
800a1d0: f000 f8a5 bl 800a31e <USBD_CtlError>
|
|
break;
|
|
800a1d4: e01a b.n 800a20c <USBD_GetStatus+0x60>
|
|
}
|
|
|
|
#if (USBD_SELF_POWERED == 1U)
|
|
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
|
|
800a1d6: 687b ldr r3, [r7, #4]
|
|
800a1d8: 2201 movs r2, #1
|
|
800a1da: 60da str r2, [r3, #12]
|
|
#else
|
|
pdev->dev_config_status = 0U;
|
|
#endif /* USBD_SELF_POWERED */
|
|
|
|
if (pdev->dev_remote_wakeup != 0U)
|
|
800a1dc: 687b ldr r3, [r7, #4]
|
|
800a1de: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
|
|
800a1e2: 2b00 cmp r3, #0
|
|
800a1e4: d005 beq.n 800a1f2 <USBD_GetStatus+0x46>
|
|
{
|
|
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
|
|
800a1e6: 687b ldr r3, [r7, #4]
|
|
800a1e8: 68db ldr r3, [r3, #12]
|
|
800a1ea: f043 0202 orr.w r2, r3, #2
|
|
800a1ee: 687b ldr r3, [r7, #4]
|
|
800a1f0: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U);
|
|
800a1f2: 687b ldr r3, [r7, #4]
|
|
800a1f4: 330c adds r3, #12
|
|
800a1f6: 2202 movs r2, #2
|
|
800a1f8: 4619 mov r1, r3
|
|
800a1fa: 6878 ldr r0, [r7, #4]
|
|
800a1fc: f000 f90c bl 800a418 <USBD_CtlSendData>
|
|
break;
|
|
800a200: e004 b.n 800a20c <USBD_GetStatus+0x60>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800a202: 6839 ldr r1, [r7, #0]
|
|
800a204: 6878 ldr r0, [r7, #4]
|
|
800a206: f000 f88a bl 800a31e <USBD_CtlError>
|
|
break;
|
|
800a20a: bf00 nop
|
|
}
|
|
}
|
|
800a20c: bf00 nop
|
|
800a20e: 3708 adds r7, #8
|
|
800a210: 46bd mov sp, r7
|
|
800a212: bd80 pop {r7, pc}
|
|
|
|
0800a214 <USBD_SetFeature>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
800a214: b580 push {r7, lr}
|
|
800a216: b082 sub sp, #8
|
|
800a218: af00 add r7, sp, #0
|
|
800a21a: 6078 str r0, [r7, #4]
|
|
800a21c: 6039 str r1, [r7, #0]
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
800a21e: 683b ldr r3, [r7, #0]
|
|
800a220: 885b ldrh r3, [r3, #2]
|
|
800a222: 2b01 cmp r3, #1
|
|
800a224: d107 bne.n 800a236 <USBD_SetFeature+0x22>
|
|
{
|
|
pdev->dev_remote_wakeup = 1U;
|
|
800a226: 687b ldr r3, [r7, #4]
|
|
800a228: 2201 movs r2, #1
|
|
800a22a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800a22e: 6878 ldr r0, [r7, #4]
|
|
800a230: f000 f932 bl 800a498 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
}
|
|
800a234: e013 b.n 800a25e <USBD_SetFeature+0x4a>
|
|
else if (req->wValue == USB_FEATURE_TEST_MODE)
|
|
800a236: 683b ldr r3, [r7, #0]
|
|
800a238: 885b ldrh r3, [r3, #2]
|
|
800a23a: 2b02 cmp r3, #2
|
|
800a23c: d10b bne.n 800a256 <USBD_SetFeature+0x42>
|
|
pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8);
|
|
800a23e: 683b ldr r3, [r7, #0]
|
|
800a240: 889b ldrh r3, [r3, #4]
|
|
800a242: 0a1b lsrs r3, r3, #8
|
|
800a244: b29b uxth r3, r3
|
|
800a246: b2da uxtb r2, r3
|
|
800a248: 687b ldr r3, [r7, #4]
|
|
800a24a: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800a24e: 6878 ldr r0, [r7, #4]
|
|
800a250: f000 f922 bl 800a498 <USBD_CtlSendStatus>
|
|
}
|
|
800a254: e003 b.n 800a25e <USBD_SetFeature+0x4a>
|
|
USBD_CtlError(pdev, req);
|
|
800a256: 6839 ldr r1, [r7, #0]
|
|
800a258: 6878 ldr r0, [r7, #4]
|
|
800a25a: f000 f860 bl 800a31e <USBD_CtlError>
|
|
}
|
|
800a25e: bf00 nop
|
|
800a260: 3708 adds r7, #8
|
|
800a262: 46bd mov sp, r7
|
|
800a264: bd80 pop {r7, pc}
|
|
|
|
0800a266 <USBD_ClrFeature>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
800a266: b580 push {r7, lr}
|
|
800a268: b082 sub sp, #8
|
|
800a26a: af00 add r7, sp, #0
|
|
800a26c: 6078 str r0, [r7, #4]
|
|
800a26e: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
800a270: 687b ldr r3, [r7, #4]
|
|
800a272: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
800a276: b2db uxtb r3, r3
|
|
800a278: 3b01 subs r3, #1
|
|
800a27a: 2b02 cmp r3, #2
|
|
800a27c: d80b bhi.n 800a296 <USBD_ClrFeature+0x30>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
800a27e: 683b ldr r3, [r7, #0]
|
|
800a280: 885b ldrh r3, [r3, #2]
|
|
800a282: 2b01 cmp r3, #1
|
|
800a284: d10c bne.n 800a2a0 <USBD_ClrFeature+0x3a>
|
|
{
|
|
pdev->dev_remote_wakeup = 0U;
|
|
800a286: 687b ldr r3, [r7, #4]
|
|
800a288: 2200 movs r2, #0
|
|
800a28a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
800a28e: 6878 ldr r0, [r7, #4]
|
|
800a290: f000 f902 bl 800a498 <USBD_CtlSendStatus>
|
|
}
|
|
break;
|
|
800a294: e004 b.n 800a2a0 <USBD_ClrFeature+0x3a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800a296: 6839 ldr r1, [r7, #0]
|
|
800a298: 6878 ldr r0, [r7, #4]
|
|
800a29a: f000 f840 bl 800a31e <USBD_CtlError>
|
|
break;
|
|
800a29e: e000 b.n 800a2a2 <USBD_ClrFeature+0x3c>
|
|
break;
|
|
800a2a0: bf00 nop
|
|
}
|
|
}
|
|
800a2a2: bf00 nop
|
|
800a2a4: 3708 adds r7, #8
|
|
800a2a6: 46bd mov sp, r7
|
|
800a2a8: bd80 pop {r7, pc}
|
|
|
|
0800a2aa <USBD_ParseSetupRequest>:
|
|
* @param req: usb request
|
|
* @param pdata: setup data pointer
|
|
* @retval None
|
|
*/
|
|
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
|
|
{
|
|
800a2aa: b580 push {r7, lr}
|
|
800a2ac: b084 sub sp, #16
|
|
800a2ae: af00 add r7, sp, #0
|
|
800a2b0: 6078 str r0, [r7, #4]
|
|
800a2b2: 6039 str r1, [r7, #0]
|
|
uint8_t *pbuff = pdata;
|
|
800a2b4: 683b ldr r3, [r7, #0]
|
|
800a2b6: 60fb str r3, [r7, #12]
|
|
|
|
req->bmRequest = *(uint8_t *)(pbuff);
|
|
800a2b8: 68fb ldr r3, [r7, #12]
|
|
800a2ba: 781a ldrb r2, [r3, #0]
|
|
800a2bc: 687b ldr r3, [r7, #4]
|
|
800a2be: 701a strb r2, [r3, #0]
|
|
|
|
pbuff++;
|
|
800a2c0: 68fb ldr r3, [r7, #12]
|
|
800a2c2: 3301 adds r3, #1
|
|
800a2c4: 60fb str r3, [r7, #12]
|
|
req->bRequest = *(uint8_t *)(pbuff);
|
|
800a2c6: 68fb ldr r3, [r7, #12]
|
|
800a2c8: 781a ldrb r2, [r3, #0]
|
|
800a2ca: 687b ldr r3, [r7, #4]
|
|
800a2cc: 705a strb r2, [r3, #1]
|
|
|
|
pbuff++;
|
|
800a2ce: 68fb ldr r3, [r7, #12]
|
|
800a2d0: 3301 adds r3, #1
|
|
800a2d2: 60fb str r3, [r7, #12]
|
|
req->wValue = SWAPBYTE(pbuff);
|
|
800a2d4: 68f8 ldr r0, [r7, #12]
|
|
800a2d6: f7ff fa13 bl 8009700 <SWAPBYTE>
|
|
800a2da: 4603 mov r3, r0
|
|
800a2dc: 461a mov r2, r3
|
|
800a2de: 687b ldr r3, [r7, #4]
|
|
800a2e0: 805a strh r2, [r3, #2]
|
|
|
|
pbuff++;
|
|
800a2e2: 68fb ldr r3, [r7, #12]
|
|
800a2e4: 3301 adds r3, #1
|
|
800a2e6: 60fb str r3, [r7, #12]
|
|
pbuff++;
|
|
800a2e8: 68fb ldr r3, [r7, #12]
|
|
800a2ea: 3301 adds r3, #1
|
|
800a2ec: 60fb str r3, [r7, #12]
|
|
req->wIndex = SWAPBYTE(pbuff);
|
|
800a2ee: 68f8 ldr r0, [r7, #12]
|
|
800a2f0: f7ff fa06 bl 8009700 <SWAPBYTE>
|
|
800a2f4: 4603 mov r3, r0
|
|
800a2f6: 461a mov r2, r3
|
|
800a2f8: 687b ldr r3, [r7, #4]
|
|
800a2fa: 809a strh r2, [r3, #4]
|
|
|
|
pbuff++;
|
|
800a2fc: 68fb ldr r3, [r7, #12]
|
|
800a2fe: 3301 adds r3, #1
|
|
800a300: 60fb str r3, [r7, #12]
|
|
pbuff++;
|
|
800a302: 68fb ldr r3, [r7, #12]
|
|
800a304: 3301 adds r3, #1
|
|
800a306: 60fb str r3, [r7, #12]
|
|
req->wLength = SWAPBYTE(pbuff);
|
|
800a308: 68f8 ldr r0, [r7, #12]
|
|
800a30a: f7ff f9f9 bl 8009700 <SWAPBYTE>
|
|
800a30e: 4603 mov r3, r0
|
|
800a310: 461a mov r2, r3
|
|
800a312: 687b ldr r3, [r7, #4]
|
|
800a314: 80da strh r2, [r3, #6]
|
|
}
|
|
800a316: bf00 nop
|
|
800a318: 3710 adds r7, #16
|
|
800a31a: 46bd mov sp, r7
|
|
800a31c: bd80 pop {r7, pc}
|
|
|
|
0800a31e <USBD_CtlError>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
800a31e: b580 push {r7, lr}
|
|
800a320: b082 sub sp, #8
|
|
800a322: af00 add r7, sp, #0
|
|
800a324: 6078 str r0, [r7, #4]
|
|
800a326: 6039 str r1, [r7, #0]
|
|
UNUSED(req);
|
|
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
800a328: 2180 movs r1, #128 @ 0x80
|
|
800a32a: 6878 ldr r0, [r7, #4]
|
|
800a32c: f000 fc2a bl 800ab84 <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0U);
|
|
800a330: 2100 movs r1, #0
|
|
800a332: 6878 ldr r0, [r7, #4]
|
|
800a334: f000 fc26 bl 800ab84 <USBD_LL_StallEP>
|
|
}
|
|
800a338: bf00 nop
|
|
800a33a: 3708 adds r7, #8
|
|
800a33c: 46bd mov sp, r7
|
|
800a33e: bd80 pop {r7, pc}
|
|
|
|
0800a340 <USBD_GetString>:
|
|
* @param unicode : Formatted string buffer (unicode)
|
|
* @param len : descriptor length
|
|
* @retval None
|
|
*/
|
|
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
|
|
{
|
|
800a340: b580 push {r7, lr}
|
|
800a342: b086 sub sp, #24
|
|
800a344: af00 add r7, sp, #0
|
|
800a346: 60f8 str r0, [r7, #12]
|
|
800a348: 60b9 str r1, [r7, #8]
|
|
800a34a: 607a str r2, [r7, #4]
|
|
uint8_t idx = 0U;
|
|
800a34c: 2300 movs r3, #0
|
|
800a34e: 75fb strb r3, [r7, #23]
|
|
uint8_t *pdesc;
|
|
|
|
if (desc == NULL)
|
|
800a350: 68fb ldr r3, [r7, #12]
|
|
800a352: 2b00 cmp r3, #0
|
|
800a354: d042 beq.n 800a3dc <USBD_GetString+0x9c>
|
|
{
|
|
return;
|
|
}
|
|
|
|
pdesc = desc;
|
|
800a356: 68fb ldr r3, [r7, #12]
|
|
800a358: 613b str r3, [r7, #16]
|
|
*len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U);
|
|
800a35a: 6938 ldr r0, [r7, #16]
|
|
800a35c: f000 f842 bl 800a3e4 <USBD_GetLen>
|
|
800a360: 4603 mov r3, r0
|
|
800a362: 3301 adds r3, #1
|
|
800a364: 005b lsls r3, r3, #1
|
|
800a366: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
800a36a: d808 bhi.n 800a37e <USBD_GetString+0x3e>
|
|
800a36c: 6938 ldr r0, [r7, #16]
|
|
800a36e: f000 f839 bl 800a3e4 <USBD_GetLen>
|
|
800a372: 4603 mov r3, r0
|
|
800a374: 3301 adds r3, #1
|
|
800a376: b29b uxth r3, r3
|
|
800a378: 005b lsls r3, r3, #1
|
|
800a37a: b29a uxth r2, r3
|
|
800a37c: e001 b.n 800a382 <USBD_GetString+0x42>
|
|
800a37e: f44f 7200 mov.w r2, #512 @ 0x200
|
|
800a382: 687b ldr r3, [r7, #4]
|
|
800a384: 801a strh r2, [r3, #0]
|
|
|
|
unicode[idx] = *(uint8_t *)len;
|
|
800a386: 7dfb ldrb r3, [r7, #23]
|
|
800a388: 68ba ldr r2, [r7, #8]
|
|
800a38a: 4413 add r3, r2
|
|
800a38c: 687a ldr r2, [r7, #4]
|
|
800a38e: 7812 ldrb r2, [r2, #0]
|
|
800a390: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
800a392: 7dfb ldrb r3, [r7, #23]
|
|
800a394: 3301 adds r3, #1
|
|
800a396: 75fb strb r3, [r7, #23]
|
|
unicode[idx] = USB_DESC_TYPE_STRING;
|
|
800a398: 7dfb ldrb r3, [r7, #23]
|
|
800a39a: 68ba ldr r2, [r7, #8]
|
|
800a39c: 4413 add r3, r2
|
|
800a39e: 2203 movs r2, #3
|
|
800a3a0: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
800a3a2: 7dfb ldrb r3, [r7, #23]
|
|
800a3a4: 3301 adds r3, #1
|
|
800a3a6: 75fb strb r3, [r7, #23]
|
|
|
|
while (*pdesc != (uint8_t)'\0')
|
|
800a3a8: e013 b.n 800a3d2 <USBD_GetString+0x92>
|
|
{
|
|
unicode[idx] = *pdesc;
|
|
800a3aa: 7dfb ldrb r3, [r7, #23]
|
|
800a3ac: 68ba ldr r2, [r7, #8]
|
|
800a3ae: 4413 add r3, r2
|
|
800a3b0: 693a ldr r2, [r7, #16]
|
|
800a3b2: 7812 ldrb r2, [r2, #0]
|
|
800a3b4: 701a strb r2, [r3, #0]
|
|
pdesc++;
|
|
800a3b6: 693b ldr r3, [r7, #16]
|
|
800a3b8: 3301 adds r3, #1
|
|
800a3ba: 613b str r3, [r7, #16]
|
|
idx++;
|
|
800a3bc: 7dfb ldrb r3, [r7, #23]
|
|
800a3be: 3301 adds r3, #1
|
|
800a3c0: 75fb strb r3, [r7, #23]
|
|
|
|
unicode[idx] = 0U;
|
|
800a3c2: 7dfb ldrb r3, [r7, #23]
|
|
800a3c4: 68ba ldr r2, [r7, #8]
|
|
800a3c6: 4413 add r3, r2
|
|
800a3c8: 2200 movs r2, #0
|
|
800a3ca: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
800a3cc: 7dfb ldrb r3, [r7, #23]
|
|
800a3ce: 3301 adds r3, #1
|
|
800a3d0: 75fb strb r3, [r7, #23]
|
|
while (*pdesc != (uint8_t)'\0')
|
|
800a3d2: 693b ldr r3, [r7, #16]
|
|
800a3d4: 781b ldrb r3, [r3, #0]
|
|
800a3d6: 2b00 cmp r3, #0
|
|
800a3d8: d1e7 bne.n 800a3aa <USBD_GetString+0x6a>
|
|
800a3da: e000 b.n 800a3de <USBD_GetString+0x9e>
|
|
return;
|
|
800a3dc: bf00 nop
|
|
}
|
|
}
|
|
800a3de: 3718 adds r7, #24
|
|
800a3e0: 46bd mov sp, r7
|
|
800a3e2: bd80 pop {r7, pc}
|
|
|
|
0800a3e4 <USBD_GetLen>:
|
|
* return the string length
|
|
* @param buf : pointer to the ascii string buffer
|
|
* @retval string length
|
|
*/
|
|
static uint8_t USBD_GetLen(uint8_t *buf)
|
|
{
|
|
800a3e4: b480 push {r7}
|
|
800a3e6: b085 sub sp, #20
|
|
800a3e8: af00 add r7, sp, #0
|
|
800a3ea: 6078 str r0, [r7, #4]
|
|
uint8_t len = 0U;
|
|
800a3ec: 2300 movs r3, #0
|
|
800a3ee: 73fb strb r3, [r7, #15]
|
|
uint8_t *pbuff = buf;
|
|
800a3f0: 687b ldr r3, [r7, #4]
|
|
800a3f2: 60bb str r3, [r7, #8]
|
|
|
|
while (*pbuff != (uint8_t)'\0')
|
|
800a3f4: e005 b.n 800a402 <USBD_GetLen+0x1e>
|
|
{
|
|
len++;
|
|
800a3f6: 7bfb ldrb r3, [r7, #15]
|
|
800a3f8: 3301 adds r3, #1
|
|
800a3fa: 73fb strb r3, [r7, #15]
|
|
pbuff++;
|
|
800a3fc: 68bb ldr r3, [r7, #8]
|
|
800a3fe: 3301 adds r3, #1
|
|
800a400: 60bb str r3, [r7, #8]
|
|
while (*pbuff != (uint8_t)'\0')
|
|
800a402: 68bb ldr r3, [r7, #8]
|
|
800a404: 781b ldrb r3, [r3, #0]
|
|
800a406: 2b00 cmp r3, #0
|
|
800a408: d1f5 bne.n 800a3f6 <USBD_GetLen+0x12>
|
|
}
|
|
|
|
return len;
|
|
800a40a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800a40c: 4618 mov r0, r3
|
|
800a40e: 3714 adds r7, #20
|
|
800a410: 46bd mov sp, r7
|
|
800a412: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a416: 4770 bx lr
|
|
|
|
0800a418 <USBD_CtlSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
800a418: b580 push {r7, lr}
|
|
800a41a: b084 sub sp, #16
|
|
800a41c: af00 add r7, sp, #0
|
|
800a41e: 60f8 str r0, [r7, #12]
|
|
800a420: 60b9 str r1, [r7, #8]
|
|
800a422: 607a str r2, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_DATA_IN;
|
|
800a424: 68fb ldr r3, [r7, #12]
|
|
800a426: 2202 movs r2, #2
|
|
800a428: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->ep_in[0].total_length = len;
|
|
800a42c: 68fb ldr r3, [r7, #12]
|
|
800a42e: 687a ldr r2, [r7, #4]
|
|
800a430: 615a str r2, [r3, #20]
|
|
pdev->ep_in[0].pbuffer = pbuf;
|
|
800a432: 68fb ldr r3, [r7, #12]
|
|
800a434: 68ba ldr r2, [r7, #8]
|
|
800a436: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
|
|
pdev->ep_in[0].rem_length = 0U;
|
|
#else
|
|
pdev->ep_in[0].rem_length = len;
|
|
800a438: 68fb ldr r3, [r7, #12]
|
|
800a43a: 687a ldr r2, [r7, #4]
|
|
800a43c: 619a str r2, [r3, #24]
|
|
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
800a43e: 687b ldr r3, [r7, #4]
|
|
800a440: 68ba ldr r2, [r7, #8]
|
|
800a442: 2100 movs r1, #0
|
|
800a444: 68f8 ldr r0, [r7, #12]
|
|
800a446: f000 fc26 bl 800ac96 <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
800a44a: 2300 movs r3, #0
|
|
}
|
|
800a44c: 4618 mov r0, r3
|
|
800a44e: 3710 adds r7, #16
|
|
800a450: 46bd mov sp, r7
|
|
800a452: bd80 pop {r7, pc}
|
|
|
|
0800a454 <USBD_CtlContinueSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
800a454: b580 push {r7, lr}
|
|
800a456: b084 sub sp, #16
|
|
800a458: af00 add r7, sp, #0
|
|
800a45a: 60f8 str r0, [r7, #12]
|
|
800a45c: 60b9 str r1, [r7, #8]
|
|
800a45e: 607a str r2, [r7, #4]
|
|
/* Start the next transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
800a460: 687b ldr r3, [r7, #4]
|
|
800a462: 68ba ldr r2, [r7, #8]
|
|
800a464: 2100 movs r1, #0
|
|
800a466: 68f8 ldr r0, [r7, #12]
|
|
800a468: f000 fc15 bl 800ac96 <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
800a46c: 2300 movs r3, #0
|
|
}
|
|
800a46e: 4618 mov r0, r3
|
|
800a470: 3710 adds r7, #16
|
|
800a472: 46bd mov sp, r7
|
|
800a474: bd80 pop {r7, pc}
|
|
|
|
0800a476 <USBD_CtlContinueRx>:
|
|
* @param len: length of data to be received
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
800a476: b580 push {r7, lr}
|
|
800a478: b084 sub sp, #16
|
|
800a47a: af00 add r7, sp, #0
|
|
800a47c: 60f8 str r0, [r7, #12]
|
|
800a47e: 60b9 str r1, [r7, #8]
|
|
800a480: 607a str r2, [r7, #4]
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
|
|
800a482: 687b ldr r3, [r7, #4]
|
|
800a484: 68ba ldr r2, [r7, #8]
|
|
800a486: 2100 movs r1, #0
|
|
800a488: 68f8 ldr r0, [r7, #12]
|
|
800a48a: f000 fc25 bl 800acd8 <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
800a48e: 2300 movs r3, #0
|
|
}
|
|
800a490: 4618 mov r0, r3
|
|
800a492: 3710 adds r7, #16
|
|
800a494: 46bd mov sp, r7
|
|
800a496: bd80 pop {r7, pc}
|
|
|
|
0800a498 <USBD_CtlSendStatus>:
|
|
* send zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
800a498: b580 push {r7, lr}
|
|
800a49a: b082 sub sp, #8
|
|
800a49c: af00 add r7, sp, #0
|
|
800a49e: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_IN;
|
|
800a4a0: 687b ldr r3, [r7, #4]
|
|
800a4a2: 2204 movs r2, #4
|
|
800a4a4: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
|
|
800a4a8: 2300 movs r3, #0
|
|
800a4aa: 2200 movs r2, #0
|
|
800a4ac: 2100 movs r1, #0
|
|
800a4ae: 6878 ldr r0, [r7, #4]
|
|
800a4b0: f000 fbf1 bl 800ac96 <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
800a4b4: 2300 movs r3, #0
|
|
}
|
|
800a4b6: 4618 mov r0, r3
|
|
800a4b8: 3708 adds r7, #8
|
|
800a4ba: 46bd mov sp, r7
|
|
800a4bc: bd80 pop {r7, pc}
|
|
|
|
0800a4be <USBD_CtlReceiveStatus>:
|
|
* receive zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
800a4be: b580 push {r7, lr}
|
|
800a4c0: b082 sub sp, #8
|
|
800a4c2: af00 add r7, sp, #0
|
|
800a4c4: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_OUT;
|
|
800a4c6: 687b ldr r3, [r7, #4]
|
|
800a4c8: 2205 movs r2, #5
|
|
800a4ca: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
800a4ce: 2300 movs r3, #0
|
|
800a4d0: 2200 movs r2, #0
|
|
800a4d2: 2100 movs r1, #0
|
|
800a4d4: 6878 ldr r0, [r7, #4]
|
|
800a4d6: f000 fbff bl 800acd8 <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
800a4da: 2300 movs r3, #0
|
|
}
|
|
800a4dc: 4618 mov r0, r3
|
|
800a4de: 3708 adds r7, #8
|
|
800a4e0: 46bd mov sp, r7
|
|
800a4e2: bd80 pop {r7, pc}
|
|
|
|
0800a4e4 <MX_USB_DEVICE_Init>:
|
|
/**
|
|
* Init USB device Library, add supported class and start the library
|
|
* @retval None
|
|
*/
|
|
void MX_USB_DEVICE_Init(void)
|
|
{
|
|
800a4e4: b580 push {r7, lr}
|
|
800a4e6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
|
|
|
|
/* USER CODE END USB_DEVICE_Init_PreTreatment */
|
|
|
|
/* Init Device Library, add supported class and start the library. */
|
|
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
|
|
800a4e8: 2200 movs r2, #0
|
|
800a4ea: 490e ldr r1, [pc, #56] @ (800a524 <MX_USB_DEVICE_Init+0x40>)
|
|
800a4ec: 480e ldr r0, [pc, #56] @ (800a528 <MX_USB_DEVICE_Init+0x44>)
|
|
800a4ee: f7fe fcd1 bl 8008e94 <USBD_Init>
|
|
800a4f2: 4603 mov r3, r0
|
|
800a4f4: 2b00 cmp r3, #0
|
|
800a4f6: d001 beq.n 800a4fc <MX_USB_DEVICE_Init+0x18>
|
|
{
|
|
Error_Handler();
|
|
800a4f8: f7f6 fe38 bl 800116c <Error_Handler>
|
|
}
|
|
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK)
|
|
800a4fc: 490b ldr r1, [pc, #44] @ (800a52c <MX_USB_DEVICE_Init+0x48>)
|
|
800a4fe: 480a ldr r0, [pc, #40] @ (800a528 <MX_USB_DEVICE_Init+0x44>)
|
|
800a500: f7fe fcf8 bl 8008ef4 <USBD_RegisterClass>
|
|
800a504: 4603 mov r3, r0
|
|
800a506: 2b00 cmp r3, #0
|
|
800a508: d001 beq.n 800a50e <MX_USB_DEVICE_Init+0x2a>
|
|
{
|
|
Error_Handler();
|
|
800a50a: f7f6 fe2f bl 800116c <Error_Handler>
|
|
}
|
|
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
|
|
800a50e: 4806 ldr r0, [pc, #24] @ (800a528 <MX_USB_DEVICE_Init+0x44>)
|
|
800a510: f7fe fd26 bl 8008f60 <USBD_Start>
|
|
800a514: 4603 mov r3, r0
|
|
800a516: 2b00 cmp r3, #0
|
|
800a518: d001 beq.n 800a51e <MX_USB_DEVICE_Init+0x3a>
|
|
{
|
|
Error_Handler();
|
|
800a51a: f7f6 fe27 bl 800116c <Error_Handler>
|
|
}
|
|
|
|
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
|
|
|
|
/* USER CODE END USB_DEVICE_Init_PostTreatment */
|
|
}
|
|
800a51e: bf00 nop
|
|
800a520: bd80 pop {r7, pc}
|
|
800a522: bf00 nop
|
|
800a524: 20000140 .word 0x20000140
|
|
800a528: 20000d88 .word 0x20000d88
|
|
800a52c: 2000009c .word 0x2000009c
|
|
|
|
0800a530 <USBD_FS_DeviceDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a530: b480 push {r7}
|
|
800a532: b083 sub sp, #12
|
|
800a534: af00 add r7, sp, #0
|
|
800a536: 4603 mov r3, r0
|
|
800a538: 6039 str r1, [r7, #0]
|
|
800a53a: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_FS_DeviceDesc);
|
|
800a53c: 683b ldr r3, [r7, #0]
|
|
800a53e: 2212 movs r2, #18
|
|
800a540: 801a strh r2, [r3, #0]
|
|
return USBD_FS_DeviceDesc;
|
|
800a542: 4b03 ldr r3, [pc, #12] @ (800a550 <USBD_FS_DeviceDescriptor+0x20>)
|
|
}
|
|
800a544: 4618 mov r0, r3
|
|
800a546: 370c adds r7, #12
|
|
800a548: 46bd mov sp, r7
|
|
800a54a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a54e: 4770 bx lr
|
|
800a550: 20000160 .word 0x20000160
|
|
|
|
0800a554 <USBD_FS_LangIDStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a554: b480 push {r7}
|
|
800a556: b083 sub sp, #12
|
|
800a558: af00 add r7, sp, #0
|
|
800a55a: 4603 mov r3, r0
|
|
800a55c: 6039 str r1, [r7, #0]
|
|
800a55e: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_LangIDDesc);
|
|
800a560: 683b ldr r3, [r7, #0]
|
|
800a562: 2204 movs r2, #4
|
|
800a564: 801a strh r2, [r3, #0]
|
|
return USBD_LangIDDesc;
|
|
800a566: 4b03 ldr r3, [pc, #12] @ (800a574 <USBD_FS_LangIDStrDescriptor+0x20>)
|
|
}
|
|
800a568: 4618 mov r0, r3
|
|
800a56a: 370c adds r7, #12
|
|
800a56c: 46bd mov sp, r7
|
|
800a56e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a572: 4770 bx lr
|
|
800a574: 20000180 .word 0x20000180
|
|
|
|
0800a578 <USBD_FS_ProductStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a578: b580 push {r7, lr}
|
|
800a57a: b082 sub sp, #8
|
|
800a57c: af00 add r7, sp, #0
|
|
800a57e: 4603 mov r3, r0
|
|
800a580: 6039 str r1, [r7, #0]
|
|
800a582: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
800a584: 79fb ldrb r3, [r7, #7]
|
|
800a586: 2b00 cmp r3, #0
|
|
800a588: d105 bne.n 800a596 <USBD_FS_ProductStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
|
|
800a58a: 683a ldr r2, [r7, #0]
|
|
800a58c: 4907 ldr r1, [pc, #28] @ (800a5ac <USBD_FS_ProductStrDescriptor+0x34>)
|
|
800a58e: 4808 ldr r0, [pc, #32] @ (800a5b0 <USBD_FS_ProductStrDescriptor+0x38>)
|
|
800a590: f7ff fed6 bl 800a340 <USBD_GetString>
|
|
800a594: e004 b.n 800a5a0 <USBD_FS_ProductStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
|
|
800a596: 683a ldr r2, [r7, #0]
|
|
800a598: 4904 ldr r1, [pc, #16] @ (800a5ac <USBD_FS_ProductStrDescriptor+0x34>)
|
|
800a59a: 4805 ldr r0, [pc, #20] @ (800a5b0 <USBD_FS_ProductStrDescriptor+0x38>)
|
|
800a59c: f7ff fed0 bl 800a340 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
800a5a0: 4b02 ldr r3, [pc, #8] @ (800a5ac <USBD_FS_ProductStrDescriptor+0x34>)
|
|
}
|
|
800a5a2: 4618 mov r0, r3
|
|
800a5a4: 3708 adds r7, #8
|
|
800a5a6: 46bd mov sp, r7
|
|
800a5a8: bd80 pop {r7, pc}
|
|
800a5aa: bf00 nop
|
|
800a5ac: 20001064 .word 0x20001064
|
|
800a5b0: 0800aecc .word 0x0800aecc
|
|
|
|
0800a5b4 <USBD_FS_ManufacturerStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a5b4: b580 push {r7, lr}
|
|
800a5b6: b082 sub sp, #8
|
|
800a5b8: af00 add r7, sp, #0
|
|
800a5ba: 4603 mov r3, r0
|
|
800a5bc: 6039 str r1, [r7, #0]
|
|
800a5be: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
|
|
800a5c0: 683a ldr r2, [r7, #0]
|
|
800a5c2: 4904 ldr r1, [pc, #16] @ (800a5d4 <USBD_FS_ManufacturerStrDescriptor+0x20>)
|
|
800a5c4: 4804 ldr r0, [pc, #16] @ (800a5d8 <USBD_FS_ManufacturerStrDescriptor+0x24>)
|
|
800a5c6: f7ff febb bl 800a340 <USBD_GetString>
|
|
return USBD_StrDesc;
|
|
800a5ca: 4b02 ldr r3, [pc, #8] @ (800a5d4 <USBD_FS_ManufacturerStrDescriptor+0x20>)
|
|
}
|
|
800a5cc: 4618 mov r0, r3
|
|
800a5ce: 3708 adds r7, #8
|
|
800a5d0: 46bd mov sp, r7
|
|
800a5d2: bd80 pop {r7, pc}
|
|
800a5d4: 20001064 .word 0x20001064
|
|
800a5d8: 0800aee0 .word 0x0800aee0
|
|
|
|
0800a5dc <USBD_FS_SerialStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a5dc: b580 push {r7, lr}
|
|
800a5de: b082 sub sp, #8
|
|
800a5e0: af00 add r7, sp, #0
|
|
800a5e2: 4603 mov r3, r0
|
|
800a5e4: 6039 str r1, [r7, #0]
|
|
800a5e6: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = USB_SIZ_STRING_SERIAL;
|
|
800a5e8: 683b ldr r3, [r7, #0]
|
|
800a5ea: 221a movs r2, #26
|
|
800a5ec: 801a strh r2, [r3, #0]
|
|
|
|
/* Update the serial number string descriptor with the data from the unique
|
|
* ID */
|
|
Get_SerialNum();
|
|
800a5ee: f000 f855 bl 800a69c <Get_SerialNum>
|
|
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
|
|
|
|
/* USER CODE END USBD_FS_SerialStrDescriptor */
|
|
return (uint8_t *) USBD_StringSerial;
|
|
800a5f2: 4b02 ldr r3, [pc, #8] @ (800a5fc <USBD_FS_SerialStrDescriptor+0x20>)
|
|
}
|
|
800a5f4: 4618 mov r0, r3
|
|
800a5f6: 3708 adds r7, #8
|
|
800a5f8: 46bd mov sp, r7
|
|
800a5fa: bd80 pop {r7, pc}
|
|
800a5fc: 20000184 .word 0x20000184
|
|
|
|
0800a600 <USBD_FS_ConfigStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a600: b580 push {r7, lr}
|
|
800a602: b082 sub sp, #8
|
|
800a604: af00 add r7, sp, #0
|
|
800a606: 4603 mov r3, r0
|
|
800a608: 6039 str r1, [r7, #0]
|
|
800a60a: 71fb strb r3, [r7, #7]
|
|
if(speed == USBD_SPEED_HIGH)
|
|
800a60c: 79fb ldrb r3, [r7, #7]
|
|
800a60e: 2b00 cmp r3, #0
|
|
800a610: d105 bne.n 800a61e <USBD_FS_ConfigStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
|
|
800a612: 683a ldr r2, [r7, #0]
|
|
800a614: 4907 ldr r1, [pc, #28] @ (800a634 <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
800a616: 4808 ldr r0, [pc, #32] @ (800a638 <USBD_FS_ConfigStrDescriptor+0x38>)
|
|
800a618: f7ff fe92 bl 800a340 <USBD_GetString>
|
|
800a61c: e004 b.n 800a628 <USBD_FS_ConfigStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
|
|
800a61e: 683a ldr r2, [r7, #0]
|
|
800a620: 4904 ldr r1, [pc, #16] @ (800a634 <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
800a622: 4805 ldr r0, [pc, #20] @ (800a638 <USBD_FS_ConfigStrDescriptor+0x38>)
|
|
800a624: f7ff fe8c bl 800a340 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
800a628: 4b02 ldr r3, [pc, #8] @ (800a634 <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
}
|
|
800a62a: 4618 mov r0, r3
|
|
800a62c: 3708 adds r7, #8
|
|
800a62e: 46bd mov sp, r7
|
|
800a630: bd80 pop {r7, pc}
|
|
800a632: bf00 nop
|
|
800a634: 20001064 .word 0x20001064
|
|
800a638: 0800aeec .word 0x0800aeec
|
|
|
|
0800a63c <USBD_FS_InterfaceStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a63c: b580 push {r7, lr}
|
|
800a63e: b082 sub sp, #8
|
|
800a640: af00 add r7, sp, #0
|
|
800a642: 4603 mov r3, r0
|
|
800a644: 6039 str r1, [r7, #0]
|
|
800a646: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
800a648: 79fb ldrb r3, [r7, #7]
|
|
800a64a: 2b00 cmp r3, #0
|
|
800a64c: d105 bne.n 800a65a <USBD_FS_InterfaceStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
|
|
800a64e: 683a ldr r2, [r7, #0]
|
|
800a650: 4907 ldr r1, [pc, #28] @ (800a670 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
800a652: 4808 ldr r0, [pc, #32] @ (800a674 <USBD_FS_InterfaceStrDescriptor+0x38>)
|
|
800a654: f7ff fe74 bl 800a340 <USBD_GetString>
|
|
800a658: e004 b.n 800a664 <USBD_FS_InterfaceStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
|
|
800a65a: 683a ldr r2, [r7, #0]
|
|
800a65c: 4904 ldr r1, [pc, #16] @ (800a670 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
800a65e: 4805 ldr r0, [pc, #20] @ (800a674 <USBD_FS_InterfaceStrDescriptor+0x38>)
|
|
800a660: f7ff fe6e bl 800a340 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
800a664: 4b02 ldr r3, [pc, #8] @ (800a670 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
}
|
|
800a666: 4618 mov r0, r3
|
|
800a668: 3708 adds r7, #8
|
|
800a66a: 46bd mov sp, r7
|
|
800a66c: bd80 pop {r7, pc}
|
|
800a66e: bf00 nop
|
|
800a670: 20001064 .word 0x20001064
|
|
800a674: 0800aef8 .word 0x0800aef8
|
|
|
|
0800a678 <USBD_FS_USR_BOSDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a678: b480 push {r7}
|
|
800a67a: b083 sub sp, #12
|
|
800a67c: af00 add r7, sp, #0
|
|
800a67e: 4603 mov r3, r0
|
|
800a680: 6039 str r1, [r7, #0]
|
|
800a682: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_FS_BOSDesc);
|
|
800a684: 683b ldr r3, [r7, #0]
|
|
800a686: 220c movs r2, #12
|
|
800a688: 801a strh r2, [r3, #0]
|
|
return (uint8_t*)USBD_FS_BOSDesc;
|
|
800a68a: 4b03 ldr r3, [pc, #12] @ (800a698 <USBD_FS_USR_BOSDescriptor+0x20>)
|
|
}
|
|
800a68c: 4618 mov r0, r3
|
|
800a68e: 370c adds r7, #12
|
|
800a690: 46bd mov sp, r7
|
|
800a692: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a696: 4770 bx lr
|
|
800a698: 20000174 .word 0x20000174
|
|
|
|
0800a69c <Get_SerialNum>:
|
|
* @brief Create the serial number string descriptor
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void Get_SerialNum(void)
|
|
{
|
|
800a69c: b580 push {r7, lr}
|
|
800a69e: b084 sub sp, #16
|
|
800a6a0: af00 add r7, sp, #0
|
|
uint32_t deviceserial0;
|
|
uint32_t deviceserial1;
|
|
uint32_t deviceserial2;
|
|
|
|
deviceserial0 = *(uint32_t *) DEVICE_ID1;
|
|
800a6a2: 4b0f ldr r3, [pc, #60] @ (800a6e0 <Get_SerialNum+0x44>)
|
|
800a6a4: 681b ldr r3, [r3, #0]
|
|
800a6a6: 60fb str r3, [r7, #12]
|
|
deviceserial1 = *(uint32_t *) DEVICE_ID2;
|
|
800a6a8: 4b0e ldr r3, [pc, #56] @ (800a6e4 <Get_SerialNum+0x48>)
|
|
800a6aa: 681b ldr r3, [r3, #0]
|
|
800a6ac: 60bb str r3, [r7, #8]
|
|
deviceserial2 = *(uint32_t *) DEVICE_ID3;
|
|
800a6ae: 4b0e ldr r3, [pc, #56] @ (800a6e8 <Get_SerialNum+0x4c>)
|
|
800a6b0: 681b ldr r3, [r3, #0]
|
|
800a6b2: 607b str r3, [r7, #4]
|
|
|
|
deviceserial0 += deviceserial2;
|
|
800a6b4: 68fa ldr r2, [r7, #12]
|
|
800a6b6: 687b ldr r3, [r7, #4]
|
|
800a6b8: 4413 add r3, r2
|
|
800a6ba: 60fb str r3, [r7, #12]
|
|
|
|
if (deviceserial0 != 0)
|
|
800a6bc: 68fb ldr r3, [r7, #12]
|
|
800a6be: 2b00 cmp r3, #0
|
|
800a6c0: d009 beq.n 800a6d6 <Get_SerialNum+0x3a>
|
|
{
|
|
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
|
|
800a6c2: 2208 movs r2, #8
|
|
800a6c4: 4909 ldr r1, [pc, #36] @ (800a6ec <Get_SerialNum+0x50>)
|
|
800a6c6: 68f8 ldr r0, [r7, #12]
|
|
800a6c8: f000 f814 bl 800a6f4 <IntToUnicode>
|
|
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
|
|
800a6cc: 2204 movs r2, #4
|
|
800a6ce: 4908 ldr r1, [pc, #32] @ (800a6f0 <Get_SerialNum+0x54>)
|
|
800a6d0: 68b8 ldr r0, [r7, #8]
|
|
800a6d2: f000 f80f bl 800a6f4 <IntToUnicode>
|
|
}
|
|
}
|
|
800a6d6: bf00 nop
|
|
800a6d8: 3710 adds r7, #16
|
|
800a6da: 46bd mov sp, r7
|
|
800a6dc: bd80 pop {r7, pc}
|
|
800a6de: bf00 nop
|
|
800a6e0: 1fff7a10 .word 0x1fff7a10
|
|
800a6e4: 1fff7a14 .word 0x1fff7a14
|
|
800a6e8: 1fff7a18 .word 0x1fff7a18
|
|
800a6ec: 20000186 .word 0x20000186
|
|
800a6f0: 20000196 .word 0x20000196
|
|
|
|
0800a6f4 <IntToUnicode>:
|
|
* @param pbuf: pointer to the buffer
|
|
* @param len: buffer length
|
|
* @retval None
|
|
*/
|
|
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
|
|
{
|
|
800a6f4: b480 push {r7}
|
|
800a6f6: b087 sub sp, #28
|
|
800a6f8: af00 add r7, sp, #0
|
|
800a6fa: 60f8 str r0, [r7, #12]
|
|
800a6fc: 60b9 str r1, [r7, #8]
|
|
800a6fe: 4613 mov r3, r2
|
|
800a700: 71fb strb r3, [r7, #7]
|
|
uint8_t idx = 0;
|
|
800a702: 2300 movs r3, #0
|
|
800a704: 75fb strb r3, [r7, #23]
|
|
|
|
for (idx = 0; idx < len; idx++)
|
|
800a706: 2300 movs r3, #0
|
|
800a708: 75fb strb r3, [r7, #23]
|
|
800a70a: e027 b.n 800a75c <IntToUnicode+0x68>
|
|
{
|
|
if (((value >> 28)) < 0xA)
|
|
800a70c: 68fb ldr r3, [r7, #12]
|
|
800a70e: 0f1b lsrs r3, r3, #28
|
|
800a710: 2b09 cmp r3, #9
|
|
800a712: d80b bhi.n 800a72c <IntToUnicode+0x38>
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + '0';
|
|
800a714: 68fb ldr r3, [r7, #12]
|
|
800a716: 0f1b lsrs r3, r3, #28
|
|
800a718: b2da uxtb r2, r3
|
|
800a71a: 7dfb ldrb r3, [r7, #23]
|
|
800a71c: 005b lsls r3, r3, #1
|
|
800a71e: 4619 mov r1, r3
|
|
800a720: 68bb ldr r3, [r7, #8]
|
|
800a722: 440b add r3, r1
|
|
800a724: 3230 adds r2, #48 @ 0x30
|
|
800a726: b2d2 uxtb r2, r2
|
|
800a728: 701a strb r2, [r3, #0]
|
|
800a72a: e00a b.n 800a742 <IntToUnicode+0x4e>
|
|
}
|
|
else
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
|
|
800a72c: 68fb ldr r3, [r7, #12]
|
|
800a72e: 0f1b lsrs r3, r3, #28
|
|
800a730: b2da uxtb r2, r3
|
|
800a732: 7dfb ldrb r3, [r7, #23]
|
|
800a734: 005b lsls r3, r3, #1
|
|
800a736: 4619 mov r1, r3
|
|
800a738: 68bb ldr r3, [r7, #8]
|
|
800a73a: 440b add r3, r1
|
|
800a73c: 3237 adds r2, #55 @ 0x37
|
|
800a73e: b2d2 uxtb r2, r2
|
|
800a740: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
value = value << 4;
|
|
800a742: 68fb ldr r3, [r7, #12]
|
|
800a744: 011b lsls r3, r3, #4
|
|
800a746: 60fb str r3, [r7, #12]
|
|
|
|
pbuf[2 * idx + 1] = 0;
|
|
800a748: 7dfb ldrb r3, [r7, #23]
|
|
800a74a: 005b lsls r3, r3, #1
|
|
800a74c: 3301 adds r3, #1
|
|
800a74e: 68ba ldr r2, [r7, #8]
|
|
800a750: 4413 add r3, r2
|
|
800a752: 2200 movs r2, #0
|
|
800a754: 701a strb r2, [r3, #0]
|
|
for (idx = 0; idx < len; idx++)
|
|
800a756: 7dfb ldrb r3, [r7, #23]
|
|
800a758: 3301 adds r3, #1
|
|
800a75a: 75fb strb r3, [r7, #23]
|
|
800a75c: 7dfa ldrb r2, [r7, #23]
|
|
800a75e: 79fb ldrb r3, [r7, #7]
|
|
800a760: 429a cmp r2, r3
|
|
800a762: d3d3 bcc.n 800a70c <IntToUnicode+0x18>
|
|
}
|
|
}
|
|
800a764: bf00 nop
|
|
800a766: bf00 nop
|
|
800a768: 371c adds r7, #28
|
|
800a76a: 46bd mov sp, r7
|
|
800a76c: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a770: 4770 bx lr
|
|
...
|
|
|
|
0800a774 <HAL_PCD_MspInit>:
|
|
LL Driver Callbacks (PCD -> USB Device Library)
|
|
*******************************************************************************/
|
|
/* MSP Init */
|
|
|
|
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
|
|
{
|
|
800a774: b580 push {r7, lr}
|
|
800a776: b0a0 sub sp, #128 @ 0x80
|
|
800a778: af00 add r7, sp, #0
|
|
800a77a: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800a77c: f107 036c add.w r3, r7, #108 @ 0x6c
|
|
800a780: 2200 movs r2, #0
|
|
800a782: 601a str r2, [r3, #0]
|
|
800a784: 605a str r2, [r3, #4]
|
|
800a786: 609a str r2, [r3, #8]
|
|
800a788: 60da str r2, [r3, #12]
|
|
800a78a: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
800a78c: f107 0310 add.w r3, r7, #16
|
|
800a790: 225c movs r2, #92 @ 0x5c
|
|
800a792: 2100 movs r1, #0
|
|
800a794: 4618 mov r0, r3
|
|
800a796: f000 fb53 bl 800ae40 <memset>
|
|
if(pcdHandle->Instance==USB_OTG_FS)
|
|
800a79a: 687b ldr r3, [r7, #4]
|
|
800a79c: 681b ldr r3, [r3, #0]
|
|
800a79e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
800a7a2: d149 bne.n 800a838 <HAL_PCD_MspInit+0xc4>
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
|
|
800a7a4: f44f 7380 mov.w r3, #256 @ 0x100
|
|
800a7a8: 613b str r3, [r7, #16]
|
|
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ;
|
|
800a7aa: 2300 movs r3, #0
|
|
800a7ac: 667b str r3, [r7, #100] @ 0x64
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
800a7ae: f107 0310 add.w r3, r7, #16
|
|
800a7b2: 4618 mov r0, r3
|
|
800a7b4: f7f9 ff00 bl 80045b8 <HAL_RCCEx_PeriphCLKConfig>
|
|
800a7b8: 4603 mov r3, r0
|
|
800a7ba: 2b00 cmp r3, #0
|
|
800a7bc: d001 beq.n 800a7c2 <HAL_PCD_MspInit+0x4e>
|
|
{
|
|
Error_Handler();
|
|
800a7be: f7f6 fcd5 bl 800116c <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800a7c2: 2300 movs r3, #0
|
|
800a7c4: 60fb str r3, [r7, #12]
|
|
800a7c6: 4b1e ldr r3, [pc, #120] @ (800a840 <HAL_PCD_MspInit+0xcc>)
|
|
800a7c8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800a7ca: 4a1d ldr r2, [pc, #116] @ (800a840 <HAL_PCD_MspInit+0xcc>)
|
|
800a7cc: f043 0301 orr.w r3, r3, #1
|
|
800a7d0: 6313 str r3, [r2, #48] @ 0x30
|
|
800a7d2: 4b1b ldr r3, [pc, #108] @ (800a840 <HAL_PCD_MspInit+0xcc>)
|
|
800a7d4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800a7d6: f003 0301 and.w r3, r3, #1
|
|
800a7da: 60fb str r3, [r7, #12]
|
|
800a7dc: 68fb ldr r3, [r7, #12]
|
|
/**USB_OTG_FS GPIO Configuration
|
|
PA11 ------> USB_OTG_FS_DM
|
|
PA12 ------> USB_OTG_FS_DP
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
|
|
800a7de: f44f 53c0 mov.w r3, #6144 @ 0x1800
|
|
800a7e2: 66fb str r3, [r7, #108] @ 0x6c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800a7e4: 2302 movs r3, #2
|
|
800a7e6: 673b str r3, [r7, #112] @ 0x70
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800a7e8: 2300 movs r3, #0
|
|
800a7ea: 677b str r3, [r7, #116] @ 0x74
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800a7ec: 2303 movs r3, #3
|
|
800a7ee: 67bb str r3, [r7, #120] @ 0x78
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
|
|
800a7f0: 230a movs r3, #10
|
|
800a7f2: 67fb str r3, [r7, #124] @ 0x7c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800a7f4: f107 036c add.w r3, r7, #108 @ 0x6c
|
|
800a7f8: 4619 mov r1, r3
|
|
800a7fa: 4812 ldr r0, [pc, #72] @ (800a844 <HAL_PCD_MspInit+0xd0>)
|
|
800a7fc: f7f8 f832 bl 8002864 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
|
|
800a800: 4b0f ldr r3, [pc, #60] @ (800a840 <HAL_PCD_MspInit+0xcc>)
|
|
800a802: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800a804: 4a0e ldr r2, [pc, #56] @ (800a840 <HAL_PCD_MspInit+0xcc>)
|
|
800a806: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800a80a: 6353 str r3, [r2, #52] @ 0x34
|
|
800a80c: 2300 movs r3, #0
|
|
800a80e: 60bb str r3, [r7, #8]
|
|
800a810: 4b0b ldr r3, [pc, #44] @ (800a840 <HAL_PCD_MspInit+0xcc>)
|
|
800a812: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800a814: 4a0a ldr r2, [pc, #40] @ (800a840 <HAL_PCD_MspInit+0xcc>)
|
|
800a816: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
800a81a: 6453 str r3, [r2, #68] @ 0x44
|
|
800a81c: 4b08 ldr r3, [pc, #32] @ (800a840 <HAL_PCD_MspInit+0xcc>)
|
|
800a81e: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800a820: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800a824: 60bb str r3, [r7, #8]
|
|
800a826: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Peripheral interrupt init */
|
|
HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
|
|
800a828: 2200 movs r2, #0
|
|
800a82a: 2100 movs r1, #0
|
|
800a82c: 2043 movs r0, #67 @ 0x43
|
|
800a82e: f7f7 fbe0 bl 8001ff2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
|
|
800a832: 2043 movs r0, #67 @ 0x43
|
|
800a834: f7f7 fbf9 bl 800202a <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 1 */
|
|
}
|
|
}
|
|
800a838: bf00 nop
|
|
800a83a: 3780 adds r7, #128 @ 0x80
|
|
800a83c: 46bd mov sp, r7
|
|
800a83e: bd80 pop {r7, pc}
|
|
800a840: 40023800 .word 0x40023800
|
|
800a844: 40020000 .word 0x40020000
|
|
|
|
0800a848 <HAL_PCD_SetupStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a848: b580 push {r7, lr}
|
|
800a84a: b082 sub sp, #8
|
|
800a84c: af00 add r7, sp, #0
|
|
800a84e: 6078 str r0, [r7, #4]
|
|
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
|
|
800a850: 687b ldr r3, [r7, #4]
|
|
800a852: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0
|
|
800a856: 687b ldr r3, [r7, #4]
|
|
800a858: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
800a85c: 4619 mov r1, r3
|
|
800a85e: 4610 mov r0, r2
|
|
800a860: f7fe fbcb bl 8008ffa <USBD_LL_SetupStage>
|
|
}
|
|
800a864: bf00 nop
|
|
800a866: 3708 adds r7, #8
|
|
800a868: 46bd mov sp, r7
|
|
800a86a: bd80 pop {r7, pc}
|
|
|
|
0800a86c <HAL_PCD_DataOutStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a86c: b580 push {r7, lr}
|
|
800a86e: b082 sub sp, #8
|
|
800a870: af00 add r7, sp, #0
|
|
800a872: 6078 str r0, [r7, #4]
|
|
800a874: 460b mov r3, r1
|
|
800a876: 70fb strb r3, [r7, #3]
|
|
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
|
|
800a878: 687b ldr r3, [r7, #4]
|
|
800a87a: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
|
|
800a87e: 78fa ldrb r2, [r7, #3]
|
|
800a880: 6879 ldr r1, [r7, #4]
|
|
800a882: 4613 mov r3, r2
|
|
800a884: 00db lsls r3, r3, #3
|
|
800a886: 4413 add r3, r2
|
|
800a888: 009b lsls r3, r3, #2
|
|
800a88a: 440b add r3, r1
|
|
800a88c: f503 7318 add.w r3, r3, #608 @ 0x260
|
|
800a890: 681a ldr r2, [r3, #0]
|
|
800a892: 78fb ldrb r3, [r7, #3]
|
|
800a894: 4619 mov r1, r3
|
|
800a896: f7fe fc05 bl 80090a4 <USBD_LL_DataOutStage>
|
|
}
|
|
800a89a: bf00 nop
|
|
800a89c: 3708 adds r7, #8
|
|
800a89e: 46bd mov sp, r7
|
|
800a8a0: bd80 pop {r7, pc}
|
|
|
|
0800a8a2 <HAL_PCD_DataInStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a8a2: b580 push {r7, lr}
|
|
800a8a4: b082 sub sp, #8
|
|
800a8a6: af00 add r7, sp, #0
|
|
800a8a8: 6078 str r0, [r7, #4]
|
|
800a8aa: 460b mov r3, r1
|
|
800a8ac: 70fb strb r3, [r7, #3]
|
|
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
|
|
800a8ae: 687b ldr r3, [r7, #4]
|
|
800a8b0: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
|
|
800a8b4: 78fa ldrb r2, [r7, #3]
|
|
800a8b6: 6879 ldr r1, [r7, #4]
|
|
800a8b8: 4613 mov r3, r2
|
|
800a8ba: 00db lsls r3, r3, #3
|
|
800a8bc: 4413 add r3, r2
|
|
800a8be: 009b lsls r3, r3, #2
|
|
800a8c0: 440b add r3, r1
|
|
800a8c2: 3320 adds r3, #32
|
|
800a8c4: 681a ldr r2, [r3, #0]
|
|
800a8c6: 78fb ldrb r3, [r7, #3]
|
|
800a8c8: 4619 mov r1, r3
|
|
800a8ca: f7fe fca7 bl 800921c <USBD_LL_DataInStage>
|
|
}
|
|
800a8ce: bf00 nop
|
|
800a8d0: 3708 adds r7, #8
|
|
800a8d2: 46bd mov sp, r7
|
|
800a8d4: bd80 pop {r7, pc}
|
|
|
|
0800a8d6 <HAL_PCD_SOFCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a8d6: b580 push {r7, lr}
|
|
800a8d8: b082 sub sp, #8
|
|
800a8da: af00 add r7, sp, #0
|
|
800a8dc: 6078 str r0, [r7, #4]
|
|
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
|
|
800a8de: 687b ldr r3, [r7, #4]
|
|
800a8e0: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a8e4: 4618 mov r0, r3
|
|
800a8e6: f7fe fdeb bl 80094c0 <USBD_LL_SOF>
|
|
}
|
|
800a8ea: bf00 nop
|
|
800a8ec: 3708 adds r7, #8
|
|
800a8ee: 46bd mov sp, r7
|
|
800a8f0: bd80 pop {r7, pc}
|
|
|
|
0800a8f2 <HAL_PCD_ResetCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a8f2: b580 push {r7, lr}
|
|
800a8f4: b084 sub sp, #16
|
|
800a8f6: af00 add r7, sp, #0
|
|
800a8f8: 6078 str r0, [r7, #4]
|
|
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
|
|
800a8fa: 2301 movs r3, #1
|
|
800a8fc: 73fb strb r3, [r7, #15]
|
|
|
|
if ( hpcd->Init.speed == PCD_SPEED_HIGH)
|
|
800a8fe: 687b ldr r3, [r7, #4]
|
|
800a900: 79db ldrb r3, [r3, #7]
|
|
800a902: 2b00 cmp r3, #0
|
|
800a904: d102 bne.n 800a90c <HAL_PCD_ResetCallback+0x1a>
|
|
{
|
|
speed = USBD_SPEED_HIGH;
|
|
800a906: 2300 movs r3, #0
|
|
800a908: 73fb strb r3, [r7, #15]
|
|
800a90a: e008 b.n 800a91e <HAL_PCD_ResetCallback+0x2c>
|
|
}
|
|
else if ( hpcd->Init.speed == PCD_SPEED_FULL)
|
|
800a90c: 687b ldr r3, [r7, #4]
|
|
800a90e: 79db ldrb r3, [r3, #7]
|
|
800a910: 2b02 cmp r3, #2
|
|
800a912: d102 bne.n 800a91a <HAL_PCD_ResetCallback+0x28>
|
|
{
|
|
speed = USBD_SPEED_FULL;
|
|
800a914: 2301 movs r3, #1
|
|
800a916: 73fb strb r3, [r7, #15]
|
|
800a918: e001 b.n 800a91e <HAL_PCD_ResetCallback+0x2c>
|
|
}
|
|
else
|
|
{
|
|
Error_Handler();
|
|
800a91a: f7f6 fc27 bl 800116c <Error_Handler>
|
|
}
|
|
/* Set Speed. */
|
|
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
|
|
800a91e: 687b ldr r3, [r7, #4]
|
|
800a920: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a924: 7bfa ldrb r2, [r7, #15]
|
|
800a926: 4611 mov r1, r2
|
|
800a928: 4618 mov r0, r3
|
|
800a92a: f7fe fd85 bl 8009438 <USBD_LL_SetSpeed>
|
|
|
|
/* Reset Device. */
|
|
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
|
|
800a92e: 687b ldr r3, [r7, #4]
|
|
800a930: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a934: 4618 mov r0, r3
|
|
800a936: f7fe fd2c bl 8009392 <USBD_LL_Reset>
|
|
}
|
|
800a93a: bf00 nop
|
|
800a93c: 3710 adds r7, #16
|
|
800a93e: 46bd mov sp, r7
|
|
800a940: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800a944 <HAL_PCD_SuspendCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a944: b580 push {r7, lr}
|
|
800a946: b082 sub sp, #8
|
|
800a948: af00 add r7, sp, #0
|
|
800a94a: 6078 str r0, [r7, #4]
|
|
/* Inform USB library that core enters in suspend Mode. */
|
|
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
|
|
800a94c: 687b ldr r3, [r7, #4]
|
|
800a94e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a952: 4618 mov r0, r3
|
|
800a954: f7fe fd80 bl 8009458 <USBD_LL_Suspend>
|
|
__HAL_PCD_GATE_PHYCLOCK(hpcd);
|
|
800a958: 687b ldr r3, [r7, #4]
|
|
800a95a: 681b ldr r3, [r3, #0]
|
|
800a95c: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
800a960: 681b ldr r3, [r3, #0]
|
|
800a962: 687a ldr r2, [r7, #4]
|
|
800a964: 6812 ldr r2, [r2, #0]
|
|
800a966: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
800a96a: f043 0301 orr.w r3, r3, #1
|
|
800a96e: 6013 str r3, [r2, #0]
|
|
/* Enter in STOP mode. */
|
|
/* USER CODE BEGIN 2 */
|
|
if (hpcd->Init.low_power_enable)
|
|
800a970: 687b ldr r3, [r7, #4]
|
|
800a972: 7adb ldrb r3, [r3, #11]
|
|
800a974: 2b00 cmp r3, #0
|
|
800a976: d005 beq.n 800a984 <HAL_PCD_SuspendCallback+0x40>
|
|
{
|
|
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
800a978: 4b04 ldr r3, [pc, #16] @ (800a98c <HAL_PCD_SuspendCallback+0x48>)
|
|
800a97a: 691b ldr r3, [r3, #16]
|
|
800a97c: 4a03 ldr r2, [pc, #12] @ (800a98c <HAL_PCD_SuspendCallback+0x48>)
|
|
800a97e: f043 0306 orr.w r3, r3, #6
|
|
800a982: 6113 str r3, [r2, #16]
|
|
}
|
|
/* USER CODE END 2 */
|
|
}
|
|
800a984: bf00 nop
|
|
800a986: 3708 adds r7, #8
|
|
800a988: 46bd mov sp, r7
|
|
800a98a: bd80 pop {r7, pc}
|
|
800a98c: e000ed00 .word 0xe000ed00
|
|
|
|
0800a990 <HAL_PCD_ResumeCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a990: b580 push {r7, lr}
|
|
800a992: b082 sub sp, #8
|
|
800a994: af00 add r7, sp, #0
|
|
800a996: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN 3 */
|
|
|
|
/* USER CODE END 3 */
|
|
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
|
|
800a998: 687b ldr r3, [r7, #4]
|
|
800a99a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a99e: 4618 mov r0, r3
|
|
800a9a0: f7fe fd76 bl 8009490 <USBD_LL_Resume>
|
|
}
|
|
800a9a4: bf00 nop
|
|
800a9a6: 3708 adds r7, #8
|
|
800a9a8: 46bd mov sp, r7
|
|
800a9aa: bd80 pop {r7, pc}
|
|
|
|
0800a9ac <HAL_PCD_ISOOUTIncompleteCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a9ac: b580 push {r7, lr}
|
|
800a9ae: b082 sub sp, #8
|
|
800a9b0: af00 add r7, sp, #0
|
|
800a9b2: 6078 str r0, [r7, #4]
|
|
800a9b4: 460b mov r3, r1
|
|
800a9b6: 70fb strb r3, [r7, #3]
|
|
USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
|
|
800a9b8: 687b ldr r3, [r7, #4]
|
|
800a9ba: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a9be: 78fa ldrb r2, [r7, #3]
|
|
800a9c0: 4611 mov r1, r2
|
|
800a9c2: 4618 mov r0, r3
|
|
800a9c4: f7fe fdce bl 8009564 <USBD_LL_IsoOUTIncomplete>
|
|
}
|
|
800a9c8: bf00 nop
|
|
800a9ca: 3708 adds r7, #8
|
|
800a9cc: 46bd mov sp, r7
|
|
800a9ce: bd80 pop {r7, pc}
|
|
|
|
0800a9d0 <HAL_PCD_ISOINIncompleteCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a9d0: b580 push {r7, lr}
|
|
800a9d2: b082 sub sp, #8
|
|
800a9d4: af00 add r7, sp, #0
|
|
800a9d6: 6078 str r0, [r7, #4]
|
|
800a9d8: 460b mov r3, r1
|
|
800a9da: 70fb strb r3, [r7, #3]
|
|
USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
|
|
800a9dc: 687b ldr r3, [r7, #4]
|
|
800a9de: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a9e2: 78fa ldrb r2, [r7, #3]
|
|
800a9e4: 4611 mov r1, r2
|
|
800a9e6: 4618 mov r0, r3
|
|
800a9e8: f7fe fd8a bl 8009500 <USBD_LL_IsoINIncomplete>
|
|
}
|
|
800a9ec: bf00 nop
|
|
800a9ee: 3708 adds r7, #8
|
|
800a9f0: 46bd mov sp, r7
|
|
800a9f2: bd80 pop {r7, pc}
|
|
|
|
0800a9f4 <HAL_PCD_ConnectCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a9f4: b580 push {r7, lr}
|
|
800a9f6: b082 sub sp, #8
|
|
800a9f8: af00 add r7, sp, #0
|
|
800a9fa: 6078 str r0, [r7, #4]
|
|
USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
|
|
800a9fc: 687b ldr r3, [r7, #4]
|
|
800a9fe: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800aa02: 4618 mov r0, r3
|
|
800aa04: f7fe fde0 bl 80095c8 <USBD_LL_DevConnected>
|
|
}
|
|
800aa08: bf00 nop
|
|
800aa0a: 3708 adds r7, #8
|
|
800aa0c: 46bd mov sp, r7
|
|
800aa0e: bd80 pop {r7, pc}
|
|
|
|
0800aa10 <HAL_PCD_DisconnectCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800aa10: b580 push {r7, lr}
|
|
800aa12: b082 sub sp, #8
|
|
800aa14: af00 add r7, sp, #0
|
|
800aa16: 6078 str r0, [r7, #4]
|
|
USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
|
|
800aa18: 687b ldr r3, [r7, #4]
|
|
800aa1a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800aa1e: 4618 mov r0, r3
|
|
800aa20: f7fe fddd bl 80095de <USBD_LL_DevDisconnected>
|
|
}
|
|
800aa24: bf00 nop
|
|
800aa26: 3708 adds r7, #8
|
|
800aa28: 46bd mov sp, r7
|
|
800aa2a: bd80 pop {r7, pc}
|
|
|
|
0800aa2c <USBD_LL_Init>:
|
|
* @brief Initializes the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
|
|
{
|
|
800aa2c: b580 push {r7, lr}
|
|
800aa2e: b082 sub sp, #8
|
|
800aa30: af00 add r7, sp, #0
|
|
800aa32: 6078 str r0, [r7, #4]
|
|
/* Init USB Ip. */
|
|
if (pdev->id == DEVICE_FS) {
|
|
800aa34: 687b ldr r3, [r7, #4]
|
|
800aa36: 781b ldrb r3, [r3, #0]
|
|
800aa38: 2b00 cmp r3, #0
|
|
800aa3a: d13c bne.n 800aab6 <USBD_LL_Init+0x8a>
|
|
/* Link the driver to the stack. */
|
|
hpcd_USB_OTG_FS.pData = pdev;
|
|
800aa3c: 4a20 ldr r2, [pc, #128] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa3e: 687b ldr r3, [r7, #4]
|
|
800aa40: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0
|
|
pdev->pData = &hpcd_USB_OTG_FS;
|
|
800aa44: 687b ldr r3, [r7, #4]
|
|
800aa46: 4a1e ldr r2, [pc, #120] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa48: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8
|
|
|
|
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
|
|
800aa4c: 4b1c ldr r3, [pc, #112] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa4e: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
|
|
800aa52: 601a str r2, [r3, #0]
|
|
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
|
|
800aa54: 4b1a ldr r3, [pc, #104] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa56: 2206 movs r2, #6
|
|
800aa58: 711a strb r2, [r3, #4]
|
|
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
|
|
800aa5a: 4b19 ldr r3, [pc, #100] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa5c: 2202 movs r2, #2
|
|
800aa5e: 71da strb r2, [r3, #7]
|
|
hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
|
|
800aa60: 4b17 ldr r3, [pc, #92] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa62: 2200 movs r2, #0
|
|
800aa64: 719a strb r2, [r3, #6]
|
|
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
|
|
800aa66: 4b16 ldr r3, [pc, #88] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa68: 2202 movs r2, #2
|
|
800aa6a: 725a strb r2, [r3, #9]
|
|
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
|
|
800aa6c: 4b14 ldr r3, [pc, #80] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa6e: 2200 movs r2, #0
|
|
800aa70: 729a strb r2, [r3, #10]
|
|
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
|
|
800aa72: 4b13 ldr r3, [pc, #76] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa74: 2200 movs r2, #0
|
|
800aa76: 72da strb r2, [r3, #11]
|
|
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
|
|
800aa78: 4b11 ldr r3, [pc, #68] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa7a: 2200 movs r2, #0
|
|
800aa7c: 731a strb r2, [r3, #12]
|
|
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
|
|
800aa7e: 4b10 ldr r3, [pc, #64] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa80: 2200 movs r2, #0
|
|
800aa82: 739a strb r2, [r3, #14]
|
|
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
|
|
800aa84: 4b0e ldr r3, [pc, #56] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa86: 2200 movs r2, #0
|
|
800aa88: 73da strb r2, [r3, #15]
|
|
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
|
|
800aa8a: 480d ldr r0, [pc, #52] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa8c: f7f8 f9f4 bl 8002e78 <HAL_PCD_Init>
|
|
800aa90: 4603 mov r3, r0
|
|
800aa92: 2b00 cmp r3, #0
|
|
800aa94: d001 beq.n 800aa9a <USBD_LL_Init+0x6e>
|
|
{
|
|
Error_Handler( );
|
|
800aa96: f7f6 fb69 bl 800116c <Error_Handler>
|
|
HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback);
|
|
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback);
|
|
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
|
|
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
|
|
800aa9a: 2180 movs r1, #128 @ 0x80
|
|
800aa9c: 4808 ldr r0, [pc, #32] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aa9e: f7f9 fc3c bl 800431a <HAL_PCDEx_SetRxFiFo>
|
|
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
|
|
800aaa2: 2240 movs r2, #64 @ 0x40
|
|
800aaa4: 2100 movs r1, #0
|
|
800aaa6: 4806 ldr r0, [pc, #24] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aaa8: f7f9 fbf0 bl 800428c <HAL_PCDEx_SetTxFiFo>
|
|
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
|
|
800aaac: 2280 movs r2, #128 @ 0x80
|
|
800aaae: 2101 movs r1, #1
|
|
800aab0: 4803 ldr r0, [pc, #12] @ (800aac0 <USBD_LL_Init+0x94>)
|
|
800aab2: f7f9 fbeb bl 800428c <HAL_PCDEx_SetTxFiFo>
|
|
}
|
|
return USBD_OK;
|
|
800aab6: 2300 movs r3, #0
|
|
}
|
|
800aab8: 4618 mov r0, r3
|
|
800aaba: 3708 adds r7, #8
|
|
800aabc: 46bd mov sp, r7
|
|
800aabe: bd80 pop {r7, pc}
|
|
800aac0: 20001264 .word 0x20001264
|
|
|
|
0800aac4 <USBD_LL_Start>:
|
|
* @brief Starts the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
800aac4: b580 push {r7, lr}
|
|
800aac6: b084 sub sp, #16
|
|
800aac8: af00 add r7, sp, #0
|
|
800aaca: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800aacc: 2300 movs r3, #0
|
|
800aace: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800aad0: 2300 movs r3, #0
|
|
800aad2: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_Start(pdev->pData);
|
|
800aad4: 687b ldr r3, [r7, #4]
|
|
800aad6: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800aada: 4618 mov r0, r3
|
|
800aadc: f7f8 fae2 bl 80030a4 <HAL_PCD_Start>
|
|
800aae0: 4603 mov r3, r0
|
|
800aae2: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800aae4: 7bfb ldrb r3, [r7, #15]
|
|
800aae6: 4618 mov r0, r3
|
|
800aae8: f000 f97e bl 800ade8 <USBD_Get_USB_Status>
|
|
800aaec: 4603 mov r3, r0
|
|
800aaee: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800aaf0: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800aaf2: 4618 mov r0, r3
|
|
800aaf4: 3710 adds r7, #16
|
|
800aaf6: 46bd mov sp, r7
|
|
800aaf8: bd80 pop {r7, pc}
|
|
|
|
0800aafa <USBD_LL_OpenEP>:
|
|
* @param ep_type: Endpoint type
|
|
* @param ep_mps: Endpoint max packet size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
|
|
{
|
|
800aafa: b580 push {r7, lr}
|
|
800aafc: b084 sub sp, #16
|
|
800aafe: af00 add r7, sp, #0
|
|
800ab00: 6078 str r0, [r7, #4]
|
|
800ab02: 4608 mov r0, r1
|
|
800ab04: 4611 mov r1, r2
|
|
800ab06: 461a mov r2, r3
|
|
800ab08: 4603 mov r3, r0
|
|
800ab0a: 70fb strb r3, [r7, #3]
|
|
800ab0c: 460b mov r3, r1
|
|
800ab0e: 70bb strb r3, [r7, #2]
|
|
800ab10: 4613 mov r3, r2
|
|
800ab12: 803b strh r3, [r7, #0]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800ab14: 2300 movs r3, #0
|
|
800ab16: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800ab18: 2300 movs r3, #0
|
|
800ab1a: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
|
|
800ab1c: 687b ldr r3, [r7, #4]
|
|
800ab1e: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
800ab22: 78bb ldrb r3, [r7, #2]
|
|
800ab24: 883a ldrh r2, [r7, #0]
|
|
800ab26: 78f9 ldrb r1, [r7, #3]
|
|
800ab28: f7f8 ffe3 bl 8003af2 <HAL_PCD_EP_Open>
|
|
800ab2c: 4603 mov r3, r0
|
|
800ab2e: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800ab30: 7bfb ldrb r3, [r7, #15]
|
|
800ab32: 4618 mov r0, r3
|
|
800ab34: f000 f958 bl 800ade8 <USBD_Get_USB_Status>
|
|
800ab38: 4603 mov r3, r0
|
|
800ab3a: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800ab3c: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800ab3e: 4618 mov r0, r3
|
|
800ab40: 3710 adds r7, #16
|
|
800ab42: 46bd mov sp, r7
|
|
800ab44: bd80 pop {r7, pc}
|
|
|
|
0800ab46 <USBD_LL_CloseEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
800ab46: b580 push {r7, lr}
|
|
800ab48: b084 sub sp, #16
|
|
800ab4a: af00 add r7, sp, #0
|
|
800ab4c: 6078 str r0, [r7, #4]
|
|
800ab4e: 460b mov r3, r1
|
|
800ab50: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800ab52: 2300 movs r3, #0
|
|
800ab54: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800ab56: 2300 movs r3, #0
|
|
800ab58: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
|
|
800ab5a: 687b ldr r3, [r7, #4]
|
|
800ab5c: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800ab60: 78fa ldrb r2, [r7, #3]
|
|
800ab62: 4611 mov r1, r2
|
|
800ab64: 4618 mov r0, r3
|
|
800ab66: f7f9 f82e bl 8003bc6 <HAL_PCD_EP_Close>
|
|
800ab6a: 4603 mov r3, r0
|
|
800ab6c: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800ab6e: 7bfb ldrb r3, [r7, #15]
|
|
800ab70: 4618 mov r0, r3
|
|
800ab72: f000 f939 bl 800ade8 <USBD_Get_USB_Status>
|
|
800ab76: 4603 mov r3, r0
|
|
800ab78: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800ab7a: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800ab7c: 4618 mov r0, r3
|
|
800ab7e: 3710 adds r7, #16
|
|
800ab80: 46bd mov sp, r7
|
|
800ab82: bd80 pop {r7, pc}
|
|
|
|
0800ab84 <USBD_LL_StallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
800ab84: b580 push {r7, lr}
|
|
800ab86: b084 sub sp, #16
|
|
800ab88: af00 add r7, sp, #0
|
|
800ab8a: 6078 str r0, [r7, #4]
|
|
800ab8c: 460b mov r3, r1
|
|
800ab8e: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800ab90: 2300 movs r3, #0
|
|
800ab92: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800ab94: 2300 movs r3, #0
|
|
800ab96: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
|
|
800ab98: 687b ldr r3, [r7, #4]
|
|
800ab9a: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800ab9e: 78fa ldrb r2, [r7, #3]
|
|
800aba0: 4611 mov r1, r2
|
|
800aba2: 4618 mov r0, r3
|
|
800aba4: f7f9 f8ce bl 8003d44 <HAL_PCD_EP_SetStall>
|
|
800aba8: 4603 mov r3, r0
|
|
800abaa: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800abac: 7bfb ldrb r3, [r7, #15]
|
|
800abae: 4618 mov r0, r3
|
|
800abb0: f000 f91a bl 800ade8 <USBD_Get_USB_Status>
|
|
800abb4: 4603 mov r3, r0
|
|
800abb6: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800abb8: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800abba: 4618 mov r0, r3
|
|
800abbc: 3710 adds r7, #16
|
|
800abbe: 46bd mov sp, r7
|
|
800abc0: bd80 pop {r7, pc}
|
|
|
|
0800abc2 <USBD_LL_ClearStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
800abc2: b580 push {r7, lr}
|
|
800abc4: b084 sub sp, #16
|
|
800abc6: af00 add r7, sp, #0
|
|
800abc8: 6078 str r0, [r7, #4]
|
|
800abca: 460b mov r3, r1
|
|
800abcc: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800abce: 2300 movs r3, #0
|
|
800abd0: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800abd2: 2300 movs r3, #0
|
|
800abd4: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
|
|
800abd6: 687b ldr r3, [r7, #4]
|
|
800abd8: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800abdc: 78fa ldrb r2, [r7, #3]
|
|
800abde: 4611 mov r1, r2
|
|
800abe0: 4618 mov r0, r3
|
|
800abe2: f7f9 f912 bl 8003e0a <HAL_PCD_EP_ClrStall>
|
|
800abe6: 4603 mov r3, r0
|
|
800abe8: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800abea: 7bfb ldrb r3, [r7, #15]
|
|
800abec: 4618 mov r0, r3
|
|
800abee: f000 f8fb bl 800ade8 <USBD_Get_USB_Status>
|
|
800abf2: 4603 mov r3, r0
|
|
800abf4: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800abf6: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800abf8: 4618 mov r0, r3
|
|
800abfa: 3710 adds r7, #16
|
|
800abfc: 46bd mov sp, r7
|
|
800abfe: bd80 pop {r7, pc}
|
|
|
|
0800ac00 <USBD_LL_IsStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval Stall (1: Yes, 0: No)
|
|
*/
|
|
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
800ac00: b480 push {r7}
|
|
800ac02: b085 sub sp, #20
|
|
800ac04: af00 add r7, sp, #0
|
|
800ac06: 6078 str r0, [r7, #4]
|
|
800ac08: 460b mov r3, r1
|
|
800ac0a: 70fb strb r3, [r7, #3]
|
|
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
|
|
800ac0c: 687b ldr r3, [r7, #4]
|
|
800ac0e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800ac12: 60fb str r3, [r7, #12]
|
|
|
|
if((ep_addr & 0x80) == 0x80)
|
|
800ac14: f997 3003 ldrsb.w r3, [r7, #3]
|
|
800ac18: 2b00 cmp r3, #0
|
|
800ac1a: da0b bge.n 800ac34 <USBD_LL_IsStallEP+0x34>
|
|
{
|
|
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
|
|
800ac1c: 78fb ldrb r3, [r7, #3]
|
|
800ac1e: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
800ac22: 68f9 ldr r1, [r7, #12]
|
|
800ac24: 4613 mov r3, r2
|
|
800ac26: 00db lsls r3, r3, #3
|
|
800ac28: 4413 add r3, r2
|
|
800ac2a: 009b lsls r3, r3, #2
|
|
800ac2c: 440b add r3, r1
|
|
800ac2e: 3316 adds r3, #22
|
|
800ac30: 781b ldrb r3, [r3, #0]
|
|
800ac32: e00b b.n 800ac4c <USBD_LL_IsStallEP+0x4c>
|
|
}
|
|
else
|
|
{
|
|
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
|
|
800ac34: 78fb ldrb r3, [r7, #3]
|
|
800ac36: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
800ac3a: 68f9 ldr r1, [r7, #12]
|
|
800ac3c: 4613 mov r3, r2
|
|
800ac3e: 00db lsls r3, r3, #3
|
|
800ac40: 4413 add r3, r2
|
|
800ac42: 009b lsls r3, r3, #2
|
|
800ac44: 440b add r3, r1
|
|
800ac46: f203 2356 addw r3, r3, #598 @ 0x256
|
|
800ac4a: 781b ldrb r3, [r3, #0]
|
|
}
|
|
}
|
|
800ac4c: 4618 mov r0, r3
|
|
800ac4e: 3714 adds r7, #20
|
|
800ac50: 46bd mov sp, r7
|
|
800ac52: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ac56: 4770 bx lr
|
|
|
|
0800ac58 <USBD_LL_SetUSBAddress>:
|
|
* @param pdev: Device handle
|
|
* @param dev_addr: Device address
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
|
|
{
|
|
800ac58: b580 push {r7, lr}
|
|
800ac5a: b084 sub sp, #16
|
|
800ac5c: af00 add r7, sp, #0
|
|
800ac5e: 6078 str r0, [r7, #4]
|
|
800ac60: 460b mov r3, r1
|
|
800ac62: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800ac64: 2300 movs r3, #0
|
|
800ac66: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800ac68: 2300 movs r3, #0
|
|
800ac6a: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
|
|
800ac6c: 687b ldr r3, [r7, #4]
|
|
800ac6e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800ac72: 78fa ldrb r2, [r7, #3]
|
|
800ac74: 4611 mov r1, r2
|
|
800ac76: 4618 mov r0, r3
|
|
800ac78: f7f8 ff17 bl 8003aaa <HAL_PCD_SetAddress>
|
|
800ac7c: 4603 mov r3, r0
|
|
800ac7e: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800ac80: 7bfb ldrb r3, [r7, #15]
|
|
800ac82: 4618 mov r0, r3
|
|
800ac84: f000 f8b0 bl 800ade8 <USBD_Get_USB_Status>
|
|
800ac88: 4603 mov r3, r0
|
|
800ac8a: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800ac8c: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800ac8e: 4618 mov r0, r3
|
|
800ac90: 3710 adds r7, #16
|
|
800ac92: 46bd mov sp, r7
|
|
800ac94: bd80 pop {r7, pc}
|
|
|
|
0800ac96 <USBD_LL_Transmit>:
|
|
* @param pbuf: Pointer to data to be sent
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
|
|
{
|
|
800ac96: b580 push {r7, lr}
|
|
800ac98: b086 sub sp, #24
|
|
800ac9a: af00 add r7, sp, #0
|
|
800ac9c: 60f8 str r0, [r7, #12]
|
|
800ac9e: 607a str r2, [r7, #4]
|
|
800aca0: 603b str r3, [r7, #0]
|
|
800aca2: 460b mov r3, r1
|
|
800aca4: 72fb strb r3, [r7, #11]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800aca6: 2300 movs r3, #0
|
|
800aca8: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800acaa: 2300 movs r3, #0
|
|
800acac: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
|
|
800acae: 68fb ldr r3, [r7, #12]
|
|
800acb0: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
800acb4: 7af9 ldrb r1, [r7, #11]
|
|
800acb6: 683b ldr r3, [r7, #0]
|
|
800acb8: 687a ldr r2, [r7, #4]
|
|
800acba: f7f9 f809 bl 8003cd0 <HAL_PCD_EP_Transmit>
|
|
800acbe: 4603 mov r3, r0
|
|
800acc0: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800acc2: 7dfb ldrb r3, [r7, #23]
|
|
800acc4: 4618 mov r0, r3
|
|
800acc6: f000 f88f bl 800ade8 <USBD_Get_USB_Status>
|
|
800acca: 4603 mov r3, r0
|
|
800accc: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
800acce: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
800acd0: 4618 mov r0, r3
|
|
800acd2: 3718 adds r7, #24
|
|
800acd4: 46bd mov sp, r7
|
|
800acd6: bd80 pop {r7, pc}
|
|
|
|
0800acd8 <USBD_LL_PrepareReceive>:
|
|
* @param pbuf: Pointer to data to be received
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
|
|
{
|
|
800acd8: b580 push {r7, lr}
|
|
800acda: b086 sub sp, #24
|
|
800acdc: af00 add r7, sp, #0
|
|
800acde: 60f8 str r0, [r7, #12]
|
|
800ace0: 607a str r2, [r7, #4]
|
|
800ace2: 603b str r3, [r7, #0]
|
|
800ace4: 460b mov r3, r1
|
|
800ace6: 72fb strb r3, [r7, #11]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800ace8: 2300 movs r3, #0
|
|
800acea: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800acec: 2300 movs r3, #0
|
|
800acee: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
|
|
800acf0: 68fb ldr r3, [r7, #12]
|
|
800acf2: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
800acf6: 7af9 ldrb r1, [r7, #11]
|
|
800acf8: 683b ldr r3, [r7, #0]
|
|
800acfa: 687a ldr r2, [r7, #4]
|
|
800acfc: f7f8 ffad bl 8003c5a <HAL_PCD_EP_Receive>
|
|
800ad00: 4603 mov r3, r0
|
|
800ad02: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800ad04: 7dfb ldrb r3, [r7, #23]
|
|
800ad06: 4618 mov r0, r3
|
|
800ad08: f000 f86e bl 800ade8 <USBD_Get_USB_Status>
|
|
800ad0c: 4603 mov r3, r0
|
|
800ad0e: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
800ad10: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
800ad12: 4618 mov r0, r3
|
|
800ad14: 3718 adds r7, #24
|
|
800ad16: 46bd mov sp, r7
|
|
800ad18: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800ad1c <HAL_PCDEx_LPM_Callback>:
|
|
* @param hpcd: PCD handle
|
|
* @param msg: LPM message
|
|
* @retval None
|
|
*/
|
|
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
|
|
{
|
|
800ad1c: b580 push {r7, lr}
|
|
800ad1e: b082 sub sp, #8
|
|
800ad20: af00 add r7, sp, #0
|
|
800ad22: 6078 str r0, [r7, #4]
|
|
800ad24: 460b mov r3, r1
|
|
800ad26: 70fb strb r3, [r7, #3]
|
|
switch (msg)
|
|
800ad28: 78fb ldrb r3, [r7, #3]
|
|
800ad2a: 2b00 cmp r3, #0
|
|
800ad2c: d002 beq.n 800ad34 <HAL_PCDEx_LPM_Callback+0x18>
|
|
800ad2e: 2b01 cmp r3, #1
|
|
800ad30: d01f beq.n 800ad72 <HAL_PCDEx_LPM_Callback+0x56>
|
|
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
800ad32: e03b b.n 800adac <HAL_PCDEx_LPM_Callback+0x90>
|
|
if (hpcd->Init.low_power_enable)
|
|
800ad34: 687b ldr r3, [r7, #4]
|
|
800ad36: 7adb ldrb r3, [r3, #11]
|
|
800ad38: 2b00 cmp r3, #0
|
|
800ad3a: d007 beq.n 800ad4c <HAL_PCDEx_LPM_Callback+0x30>
|
|
SystemClock_Config();
|
|
800ad3c: f7f5 ff66 bl 8000c0c <SystemClock_Config>
|
|
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
800ad40: 4b1c ldr r3, [pc, #112] @ (800adb4 <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800ad42: 691b ldr r3, [r3, #16]
|
|
800ad44: 4a1b ldr r2, [pc, #108] @ (800adb4 <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800ad46: f023 0306 bic.w r3, r3, #6
|
|
800ad4a: 6113 str r3, [r2, #16]
|
|
__HAL_PCD_UNGATE_PHYCLOCK(hpcd);
|
|
800ad4c: 687b ldr r3, [r7, #4]
|
|
800ad4e: 681b ldr r3, [r3, #0]
|
|
800ad50: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
800ad54: 681b ldr r3, [r3, #0]
|
|
800ad56: 687a ldr r2, [r7, #4]
|
|
800ad58: 6812 ldr r2, [r2, #0]
|
|
800ad5a: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
800ad5e: f023 0301 bic.w r3, r3, #1
|
|
800ad62: 6013 str r3, [r2, #0]
|
|
USBD_LL_Resume(hpcd->pData);
|
|
800ad64: 687b ldr r3, [r7, #4]
|
|
800ad66: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800ad6a: 4618 mov r0, r3
|
|
800ad6c: f7fe fb90 bl 8009490 <USBD_LL_Resume>
|
|
break;
|
|
800ad70: e01c b.n 800adac <HAL_PCDEx_LPM_Callback+0x90>
|
|
__HAL_PCD_GATE_PHYCLOCK(hpcd);
|
|
800ad72: 687b ldr r3, [r7, #4]
|
|
800ad74: 681b ldr r3, [r3, #0]
|
|
800ad76: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
800ad7a: 681b ldr r3, [r3, #0]
|
|
800ad7c: 687a ldr r2, [r7, #4]
|
|
800ad7e: 6812 ldr r2, [r2, #0]
|
|
800ad80: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
800ad84: f043 0301 orr.w r3, r3, #1
|
|
800ad88: 6013 str r3, [r2, #0]
|
|
USBD_LL_Suspend(hpcd->pData);
|
|
800ad8a: 687b ldr r3, [r7, #4]
|
|
800ad8c: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800ad90: 4618 mov r0, r3
|
|
800ad92: f7fe fb61 bl 8009458 <USBD_LL_Suspend>
|
|
if (hpcd->Init.low_power_enable)
|
|
800ad96: 687b ldr r3, [r7, #4]
|
|
800ad98: 7adb ldrb r3, [r3, #11]
|
|
800ad9a: 2b00 cmp r3, #0
|
|
800ad9c: d005 beq.n 800adaa <HAL_PCDEx_LPM_Callback+0x8e>
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
800ad9e: 4b05 ldr r3, [pc, #20] @ (800adb4 <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800ada0: 691b ldr r3, [r3, #16]
|
|
800ada2: 4a04 ldr r2, [pc, #16] @ (800adb4 <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800ada4: f043 0306 orr.w r3, r3, #6
|
|
800ada8: 6113 str r3, [r2, #16]
|
|
break;
|
|
800adaa: bf00 nop
|
|
}
|
|
800adac: bf00 nop
|
|
800adae: 3708 adds r7, #8
|
|
800adb0: 46bd mov sp, r7
|
|
800adb2: bd80 pop {r7, pc}
|
|
800adb4: e000ed00 .word 0xe000ed00
|
|
|
|
0800adb8 <USBD_static_malloc>:
|
|
* @brief Static single allocation.
|
|
* @param size: Size of allocated memory
|
|
* @retval None
|
|
*/
|
|
void *USBD_static_malloc(uint32_t size)
|
|
{
|
|
800adb8: b480 push {r7}
|
|
800adba: b083 sub sp, #12
|
|
800adbc: af00 add r7, sp, #0
|
|
800adbe: 6078 str r0, [r7, #4]
|
|
static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */
|
|
return mem;
|
|
800adc0: 4b03 ldr r3, [pc, #12] @ (800add0 <USBD_static_malloc+0x18>)
|
|
}
|
|
800adc2: 4618 mov r0, r3
|
|
800adc4: 370c adds r7, #12
|
|
800adc6: 46bd mov sp, r7
|
|
800adc8: f85d 7b04 ldr.w r7, [sp], #4
|
|
800adcc: 4770 bx lr
|
|
800adce: bf00 nop
|
|
800add0: 20001748 .word 0x20001748
|
|
|
|
0800add4 <USBD_static_free>:
|
|
* @brief Dummy memory free
|
|
* @param p: Pointer to allocated memory address
|
|
* @retval None
|
|
*/
|
|
void USBD_static_free(void *p)
|
|
{
|
|
800add4: b480 push {r7}
|
|
800add6: b083 sub sp, #12
|
|
800add8: af00 add r7, sp, #0
|
|
800adda: 6078 str r0, [r7, #4]
|
|
|
|
}
|
|
800addc: bf00 nop
|
|
800adde: 370c adds r7, #12
|
|
800ade0: 46bd mov sp, r7
|
|
800ade2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ade6: 4770 bx lr
|
|
|
|
0800ade8 <USBD_Get_USB_Status>:
|
|
* @brief Returns the USB status depending on the HAL status:
|
|
* @param hal_status: HAL status
|
|
* @retval USB status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
|
|
{
|
|
800ade8: b480 push {r7}
|
|
800adea: b085 sub sp, #20
|
|
800adec: af00 add r7, sp, #0
|
|
800adee: 4603 mov r3, r0
|
|
800adf0: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800adf2: 2300 movs r3, #0
|
|
800adf4: 73fb strb r3, [r7, #15]
|
|
|
|
switch (hal_status)
|
|
800adf6: 79fb ldrb r3, [r7, #7]
|
|
800adf8: 2b03 cmp r3, #3
|
|
800adfa: d817 bhi.n 800ae2c <USBD_Get_USB_Status+0x44>
|
|
800adfc: a201 add r2, pc, #4 @ (adr r2, 800ae04 <USBD_Get_USB_Status+0x1c>)
|
|
800adfe: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800ae02: bf00 nop
|
|
800ae04: 0800ae15 .word 0x0800ae15
|
|
800ae08: 0800ae1b .word 0x0800ae1b
|
|
800ae0c: 0800ae21 .word 0x0800ae21
|
|
800ae10: 0800ae27 .word 0x0800ae27
|
|
{
|
|
case HAL_OK :
|
|
usb_status = USBD_OK;
|
|
800ae14: 2300 movs r3, #0
|
|
800ae16: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800ae18: e00b b.n 800ae32 <USBD_Get_USB_Status+0x4a>
|
|
case HAL_ERROR :
|
|
usb_status = USBD_FAIL;
|
|
800ae1a: 2303 movs r3, #3
|
|
800ae1c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800ae1e: e008 b.n 800ae32 <USBD_Get_USB_Status+0x4a>
|
|
case HAL_BUSY :
|
|
usb_status = USBD_BUSY;
|
|
800ae20: 2301 movs r3, #1
|
|
800ae22: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800ae24: e005 b.n 800ae32 <USBD_Get_USB_Status+0x4a>
|
|
case HAL_TIMEOUT :
|
|
usb_status = USBD_FAIL;
|
|
800ae26: 2303 movs r3, #3
|
|
800ae28: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800ae2a: e002 b.n 800ae32 <USBD_Get_USB_Status+0x4a>
|
|
default :
|
|
usb_status = USBD_FAIL;
|
|
800ae2c: 2303 movs r3, #3
|
|
800ae2e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800ae30: bf00 nop
|
|
}
|
|
return usb_status;
|
|
800ae32: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800ae34: 4618 mov r0, r3
|
|
800ae36: 3714 adds r7, #20
|
|
800ae38: 46bd mov sp, r7
|
|
800ae3a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ae3e: 4770 bx lr
|
|
|
|
0800ae40 <memset>:
|
|
800ae40: 4402 add r2, r0
|
|
800ae42: 4603 mov r3, r0
|
|
800ae44: 4293 cmp r3, r2
|
|
800ae46: d100 bne.n 800ae4a <memset+0xa>
|
|
800ae48: 4770 bx lr
|
|
800ae4a: f803 1b01 strb.w r1, [r3], #1
|
|
800ae4e: e7f9 b.n 800ae44 <memset+0x4>
|
|
|
|
0800ae50 <__libc_init_array>:
|
|
800ae50: b570 push {r4, r5, r6, lr}
|
|
800ae52: 4d0d ldr r5, [pc, #52] @ (800ae88 <__libc_init_array+0x38>)
|
|
800ae54: 4c0d ldr r4, [pc, #52] @ (800ae8c <__libc_init_array+0x3c>)
|
|
800ae56: 1b64 subs r4, r4, r5
|
|
800ae58: 10a4 asrs r4, r4, #2
|
|
800ae5a: 2600 movs r6, #0
|
|
800ae5c: 42a6 cmp r6, r4
|
|
800ae5e: d109 bne.n 800ae74 <__libc_init_array+0x24>
|
|
800ae60: 4d0b ldr r5, [pc, #44] @ (800ae90 <__libc_init_array+0x40>)
|
|
800ae62: 4c0c ldr r4, [pc, #48] @ (800ae94 <__libc_init_array+0x44>)
|
|
800ae64: f000 f826 bl 800aeb4 <_init>
|
|
800ae68: 1b64 subs r4, r4, r5
|
|
800ae6a: 10a4 asrs r4, r4, #2
|
|
800ae6c: 2600 movs r6, #0
|
|
800ae6e: 42a6 cmp r6, r4
|
|
800ae70: d105 bne.n 800ae7e <__libc_init_array+0x2e>
|
|
800ae72: bd70 pop {r4, r5, r6, pc}
|
|
800ae74: f855 3b04 ldr.w r3, [r5], #4
|
|
800ae78: 4798 blx r3
|
|
800ae7a: 3601 adds r6, #1
|
|
800ae7c: e7ee b.n 800ae5c <__libc_init_array+0xc>
|
|
800ae7e: f855 3b04 ldr.w r3, [r5], #4
|
|
800ae82: 4798 blx r3
|
|
800ae84: 3601 adds r6, #1
|
|
800ae86: e7f2 b.n 800ae6e <__libc_init_array+0x1e>
|
|
800ae88: 0800af30 .word 0x0800af30
|
|
800ae8c: 0800af30 .word 0x0800af30
|
|
800ae90: 0800af30 .word 0x0800af30
|
|
800ae94: 0800af34 .word 0x0800af34
|
|
|
|
0800ae98 <memcpy>:
|
|
800ae98: 440a add r2, r1
|
|
800ae9a: 4291 cmp r1, r2
|
|
800ae9c: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
|
|
800aea0: d100 bne.n 800aea4 <memcpy+0xc>
|
|
800aea2: 4770 bx lr
|
|
800aea4: b510 push {r4, lr}
|
|
800aea6: f811 4b01 ldrb.w r4, [r1], #1
|
|
800aeaa: f803 4f01 strb.w r4, [r3, #1]!
|
|
800aeae: 4291 cmp r1, r2
|
|
800aeb0: d1f9 bne.n 800aea6 <memcpy+0xe>
|
|
800aeb2: bd10 pop {r4, pc}
|
|
|
|
0800aeb4 <_init>:
|
|
800aeb4: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800aeb6: bf00 nop
|
|
800aeb8: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800aeba: bc08 pop {r3}
|
|
800aebc: 469e mov lr, r3
|
|
800aebe: 4770 bx lr
|
|
|
|
0800aec0 <_fini>:
|
|
800aec0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800aec2: bf00 nop
|
|
800aec4: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800aec6: bc08 pop {r3}
|
|
800aec8: 469e mov lr, r3
|
|
800aeca: 4770 bx lr
|