22775 lines
824 KiB
Plaintext
22775 lines
824 KiB
Plaintext
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modularkbd.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000001c4 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 000087d8 080001c4 080001c4 000011c4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000054 0800899c 0800899c 0000999c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 080089f0 080089f0 0000a12c 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 080089f0 080089f0 000099f0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 080089f8 080089f8 0000a12c 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 080089f8 080089f8 000099f8 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 080089fc 080089fc 000099fc 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 0000012c 20000000 08008a00 0000a000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000c44 2000012c 08008b2c 0000a12c 2**2
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ALLOC
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10 ._user_heap_stack 00000600 20000d70 08008b2c 0000ad70 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0000a12c 2**0
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CONTENTS, READONLY
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12 .debug_info 00018276 00000000 00000000 0000a15c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 0000356f 00000000 00000000 000223d2 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 000015e8 00000000 00000000 00025948 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 0000111c 00000000 00000000 00026f30 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00024cc6 00000000 00000000 0002804c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 0001aef9 00000000 00000000 0004cd12 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000d71a0 00000000 00000000 00067c0b 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 0013edab 2**0
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CONTENTS, READONLY
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20 .debug_frame 00005dc8 00000000 00000000 0013edf0 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000079 00000000 00000000 00144bb8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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080001c4 <__do_global_dtors_aux>:
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80001c4: b510 push {r4, lr}
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80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>)
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80001c8: 7823 ldrb r3, [r4, #0]
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80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16>
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80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>)
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80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12>
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80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>)
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80001d2: f3af 8000 nop.w
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80001d6: 2301 movs r3, #1
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80001d8: 7023 strb r3, [r4, #0]
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80001da: bd10 pop {r4, pc}
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80001dc: 2000012c .word 0x2000012c
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80001e0: 00000000 .word 0x00000000
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80001e4: 08008984 .word 0x08008984
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080001e8 <frame_dummy>:
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80001e8: b508 push {r3, lr}
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80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 <frame_dummy+0x10>)
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80001ec: b11b cbz r3, 80001f6 <frame_dummy+0xe>
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80001ee: 4903 ldr r1, [pc, #12] @ (80001fc <frame_dummy+0x14>)
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80001f0: 4803 ldr r0, [pc, #12] @ (8000200 <frame_dummy+0x18>)
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80001f2: f3af 8000 nop.w
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80001f6: bd08 pop {r3, pc}
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80001f8: 00000000 .word 0x00000000
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80001fc: 20000130 .word 0x20000130
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8000200: 08008984 .word 0x08008984
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08000204 <__aeabi_uldivmod>:
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8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18>
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8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18>
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8000208: 2900 cmp r1, #0
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800020a: bf08 it eq
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800020c: 2800 cmpeq r0, #0
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800020e: bf1c itt ne
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8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
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8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
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8000218: f000 b988 b.w 800052c <__aeabi_idiv0>
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800021c: f1ad 0c08 sub.w ip, sp, #8
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8000220: e96d ce04 strd ip, lr, [sp, #-16]!
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8000224: f000 f806 bl 8000234 <__udivmoddi4>
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8000228: f8dd e004 ldr.w lr, [sp, #4]
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800022c: e9dd 2302 ldrd r2, r3, [sp, #8]
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8000230: b004 add sp, #16
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8000232: 4770 bx lr
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08000234 <__udivmoddi4>:
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8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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8000238: 9d08 ldr r5, [sp, #32]
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800023a: 468e mov lr, r1
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800023c: 4604 mov r4, r0
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800023e: 4688 mov r8, r1
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8000240: 2b00 cmp r3, #0
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8000242: d14a bne.n 80002da <__udivmoddi4+0xa6>
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8000244: 428a cmp r2, r1
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8000246: 4617 mov r7, r2
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8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc>
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800024a: fab2 f682 clz r6, r2
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800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30>
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8000250: f1c6 0320 rsb r3, r6, #32
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8000254: fa01 f806 lsl.w r8, r1, r6
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8000258: fa20 f303 lsr.w r3, r0, r3
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800025c: 40b7 lsls r7, r6
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800025e: ea43 0808 orr.w r8, r3, r8
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8000262: 40b4 lsls r4, r6
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8000264: ea4f 4e17 mov.w lr, r7, lsr #16
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8000268: fa1f fc87 uxth.w ip, r7
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800026c: fbb8 f1fe udiv r1, r8, lr
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8000270: 0c23 lsrs r3, r4, #16
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8000272: fb0e 8811 mls r8, lr, r1, r8
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8000276: ea43 4308 orr.w r3, r3, r8, lsl #16
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800027a: fb01 f20c mul.w r2, r1, ip
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800027e: 429a cmp r2, r3
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8000280: d909 bls.n 8000296 <__udivmoddi4+0x62>
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8000282: 18fb adds r3, r7, r3
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8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
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8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c>
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800028c: 429a cmp r2, r3
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800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c>
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8000292: 3902 subs r1, #2
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8000294: 443b add r3, r7
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8000296: 1a9a subs r2, r3, r2
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8000298: b2a3 uxth r3, r4
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800029a: fbb2 f0fe udiv r0, r2, lr
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800029e: fb0e 2210 mls r2, lr, r0, r2
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80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16
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80002a6: fb00 fc0c mul.w ip, r0, ip
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80002aa: 459c cmp ip, r3
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80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e>
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80002ae: 18fb adds r3, r7, r3
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80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
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80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230>
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80002b8: 459c cmp ip, r3
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80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230>
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80002be: 443b add r3, r7
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80002c0: 3802 subs r0, #2
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80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16
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80002c6: eba3 030c sub.w r3, r3, ip
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80002ca: 2100 movs r1, #0
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80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2>
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80002ce: 40f3 lsrs r3, r6
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80002d0: 2200 movs r2, #0
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80002d2: e9c5 3200 strd r3, r2, [r5]
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80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002da: 428b cmp r3, r1
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80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6>
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80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0>
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80002e0: e9c5 0100 strd r0, r1, [r5]
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80002e4: 2100 movs r1, #0
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80002e6: 4608 mov r0, r1
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80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2>
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80002ea: fab3 f183 clz r1, r3
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80002ee: 2900 cmp r1, #0
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80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c>
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80002f2: 4573 cmp r3, lr
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80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8>
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80002f6: 4282 cmp r2, r0
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80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2>
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80002fc: 1a84 subs r4, r0, r2
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80002fe: eb6e 0203 sbc.w r2, lr, r3
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8000302: 2001 movs r0, #1
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8000304: 4690 mov r8, r2
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8000306: 2d00 cmp r5, #0
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8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2>
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800030a: e9c5 4800 strd r4, r8, [r5]
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800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2>
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8000310: 2a00 cmp r2, #0
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8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202>
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8000316: fab2 f682 clz r6, r2
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800031a: 2e00 cmp r6, #0
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800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234>
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8000320: 1a8a subs r2, r1, r2
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8000322: 0c03 lsrs r3, r0, #16
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8000324: ea4f 4e17 mov.w lr, r7, lsr #16
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8000328: b280 uxth r0, r0
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800032a: b2bc uxth r4, r7
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800032c: 2101 movs r1, #1
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800032e: fbb2 fcfe udiv ip, r2, lr
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8000332: fb0e 221c mls r2, lr, ip, r2
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8000336: ea43 4302 orr.w r3, r3, r2, lsl #16
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800033a: fb04 f20c mul.w r2, r4, ip
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800033e: 429a cmp r2, r3
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8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e>
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8000342: 18fb adds r3, r7, r3
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8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
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8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c>
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800034a: 429a cmp r2, r3
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800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc>
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8000350: 46c4 mov ip, r8
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8000352: 1a9b subs r3, r3, r2
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8000354: fbb3 f2fe udiv r2, r3, lr
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8000358: fb0e 3312 mls r3, lr, r2, r3
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800035c: ea40 4303 orr.w r3, r0, r3, lsl #16
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8000360: fb02 f404 mul.w r4, r2, r4
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8000364: 429c cmp r4, r3
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8000366: d907 bls.n 8000378 <__udivmoddi4+0x144>
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8000368: 18fb adds r3, r7, r3
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800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
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800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142>
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8000370: 429c cmp r4, r3
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8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6>
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8000376: 4602 mov r2, r0
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8000378: 1b1b subs r3, r3, r4
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800037a: ea42 400c orr.w r0, r2, ip, lsl #16
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800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98>
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8000380: f1c1 0620 rsb r6, r1, #32
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8000384: 408b lsls r3, r1
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8000386: fa22 f706 lsr.w r7, r2, r6
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800038a: 431f orrs r7, r3
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800038c: fa0e f401 lsl.w r4, lr, r1
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8000390: fa20 f306 lsr.w r3, r0, r6
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8000394: fa2e fe06 lsr.w lr, lr, r6
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8000398: ea4f 4917 mov.w r9, r7, lsr #16
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800039c: 4323 orrs r3, r4
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800039e: fa00 f801 lsl.w r8, r0, r1
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80003a2: fa1f fc87 uxth.w ip, r7
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80003a6: fbbe f0f9 udiv r0, lr, r9
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80003aa: 0c1c lsrs r4, r3, #16
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80003ac: fb09 ee10 mls lr, r9, r0, lr
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80003b0: ea44 440e orr.w r4, r4, lr, lsl #16
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80003b4: fb00 fe0c mul.w lr, r0, ip
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80003b8: 45a6 cmp lr, r4
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80003ba: fa02 f201 lsl.w r2, r2, r1
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80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0>
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80003c0: 193c adds r4, r7, r4
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80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
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80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce>
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80003ca: 45a6 cmp lr, r4
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80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce>
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80003d0: 3802 subs r0, #2
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80003d2: 443c add r4, r7
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80003d4: eba4 040e sub.w r4, r4, lr
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80003d8: fa1f fe83 uxth.w lr, r3
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80003dc: fbb4 f3f9 udiv r3, r4, r9
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80003e0: fb09 4413 mls r4, r9, r3, r4
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80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16
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80003e8: fb03 fc0c mul.w ip, r3, ip
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80003ec: 45a4 cmp ip, r4
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80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce>
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80003f0: 193c adds r4, r7, r4
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80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
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80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca>
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80003fa: 45a4 cmp ip, r4
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80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca>
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80003fe: 3b02 subs r3, #2
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8000400: 443c add r4, r7
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8000402: ea43 4000 orr.w r0, r3, r0, lsl #16
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8000406: eba4 040c sub.w r4, r4, ip
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800040a: fba0 ec02 umull lr, ip, r0, r2
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800040e: 4564 cmp r4, ip
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8000410: 4673 mov r3, lr
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8000412: 46e1 mov r9, ip
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8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8>
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8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4>
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8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe>
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800041a: ebb8 0203 subs.w r2, r8, r3
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800041e: eb64 0409 sbc.w r4, r4, r9
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8000422: fa04 f606 lsl.w r6, r4, r6
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8000426: fa22 f301 lsr.w r3, r2, r1
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800042a: 431e orrs r6, r3
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800042c: 40cc lsrs r4, r1
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800042e: e9c5 6400 strd r6, r4, [r5]
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8000432: 2100 movs r1, #0
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8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2>
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8000436: fbb1 fcf2 udiv ip, r1, r2
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800043a: 0c01 lsrs r1, r0, #16
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800043c: ea41 410e orr.w r1, r1, lr, lsl #16
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8000440: b280 uxth r0, r0
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8000442: ea40 4201 orr.w r2, r0, r1, lsl #16
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8000446: 463b mov r3, r7
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8000448: 4638 mov r0, r7
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800044a: 463c mov r4, r7
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800044c: 46b8 mov r8, r7
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800044e: 46be mov lr, r7
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8000450: 2620 movs r6, #32
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8000452: fbb1 f1f7 udiv r1, r1, r7
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8000456: eba2 0208 sub.w r2, r2, r8
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800045a: ea41 410c orr.w r1, r1, ip, lsl #16
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800045e: e766 b.n 800032e <__udivmoddi4+0xfa>
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8000460: 4601 mov r1, r0
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8000462: e718 b.n 8000296 <__udivmoddi4+0x62>
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8000464: 4610 mov r0, r2
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8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e>
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8000468: f1c6 0220 rsb r2, r6, #32
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800046c: fa2e f302 lsr.w r3, lr, r2
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8000470: 40b7 lsls r7, r6
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8000472: 40b1 lsls r1, r6
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8000474: fa20 f202 lsr.w r2, r0, r2
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8000478: ea4f 4e17 mov.w lr, r7, lsr #16
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800047c: 430a orrs r2, r1
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800047e: fbb3 f8fe udiv r8, r3, lr
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8000482: b2bc uxth r4, r7
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8000484: fb0e 3318 mls r3, lr, r8, r3
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8000488: 0c11 lsrs r1, r2, #16
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800048a: ea41 4103 orr.w r1, r1, r3, lsl #16
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800048e: fb08 f904 mul.w r9, r8, r4
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8000492: 40b0 lsls r0, r6
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8000494: 4589 cmp r9, r1
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8000496: ea4f 4310 mov.w r3, r0, lsr #16
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800049a: b280 uxth r0, r0
|
|
800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8>
|
|
800049e: 1879 adds r1, r7, r1
|
|
80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276>
|
|
80004a6: 4589 cmp r9, r1
|
|
80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6>
|
|
80004aa: eba1 0109 sub.w r1, r1, r9
|
|
80004ae: fbb1 f9fe udiv r9, r1, lr
|
|
80004b2: fb09 f804 mul.w r8, r9, r4
|
|
80004b6: fb0e 1119 mls r1, lr, r9, r1
|
|
80004ba: b292 uxth r2, r2
|
|
80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
80004c0: 4542 cmp r2, r8
|
|
80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4>
|
|
80004c4: 18ba adds r2, r7, r2
|
|
80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222>
|
|
80004cc: 4542 cmp r2, r8
|
|
80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222>
|
|
80004d0: f1a9 0102 sub.w r1, r9, #2
|
|
80004d4: 443a add r2, r7
|
|
80004d6: e7be b.n 8000456 <__udivmoddi4+0x222>
|
|
80004d8: 45f0 cmp r8, lr
|
|
80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4>
|
|
80004dc: ebbe 0302 subs.w r3, lr, r2
|
|
80004e0: eb6c 0c07 sbc.w ip, ip, r7
|
|
80004e4: 3801 subs r0, #1
|
|
80004e6: 46e1 mov r9, ip
|
|
80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4>
|
|
80004ea: eba7 0909 sub.w r9, r7, r9
|
|
80004ee: 4449 add r1, r9
|
|
80004f0: f1a8 0c02 sub.w ip, r8, #2
|
|
80004f4: fbb1 f9fe udiv r9, r1, lr
|
|
80004f8: fb09 f804 mul.w r8, r9, r4
|
|
80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282>
|
|
80004fe: 4673 mov r3, lr
|
|
8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce>
|
|
8000502: 4650 mov r0, sl
|
|
8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0>
|
|
8000506: 4608 mov r0, r1
|
|
8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2>
|
|
800050a: 443b add r3, r7
|
|
800050c: 3a02 subs r2, #2
|
|
800050e: e733 b.n 8000378 <__udivmoddi4+0x144>
|
|
8000510: f1ac 0c02 sub.w ip, ip, #2
|
|
8000514: 443b add r3, r7
|
|
8000516: e71c b.n 8000352 <__udivmoddi4+0x11e>
|
|
8000518: 4649 mov r1, r9
|
|
800051a: e79c b.n 8000456 <__udivmoddi4+0x222>
|
|
800051c: eba1 0109 sub.w r1, r1, r9
|
|
8000520: 46c4 mov ip, r8
|
|
8000522: fbb1 f9fe udiv r9, r1, lr
|
|
8000526: fb09 f804 mul.w r8, r9, r4
|
|
800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282>
|
|
|
|
0800052c <__aeabi_idiv0>:
|
|
800052c: 4770 bx lr
|
|
800052e: bf00 nop
|
|
|
|
08000530 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8000530: b580 push {r7, lr}
|
|
8000532: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8000534: f000 fd98 bl 8001068 <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8000538: f000 f816 bl 8000568 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
800053c: f000 fa2c bl 8000998 <MX_GPIO_Init>
|
|
MX_TIM2_Init();
|
|
8000540: f000 f8ac bl 800069c <MX_TIM2_Init>
|
|
MX_TIM3_Init();
|
|
8000544: f000 f902 bl 800074c <MX_TIM3_Init>
|
|
MX_UART4_Init();
|
|
8000548: f000 f954 bl 80007f4 <MX_UART4_Init>
|
|
MX_UART5_Init();
|
|
800054c: f000 f97c bl 8000848 <MX_UART5_Init>
|
|
MX_USART1_UART_Init();
|
|
8000550: f000 f9a4 bl 800089c <MX_USART1_UART_Init>
|
|
MX_USART2_UART_Init();
|
|
8000554: f000 f9cc bl 80008f0 <MX_USART2_UART_Init>
|
|
MX_I2C1_Init();
|
|
8000558: f000 f872 bl 8000640 <MX_I2C1_Init>
|
|
MX_USART3_UART_Init();
|
|
800055c: f000 f9f2 bl 8000944 <MX_USART3_UART_Init>
|
|
MX_USB_DEVICE_Init();
|
|
8000560: f007 fd36 bl 8007fd0 <MX_USB_DEVICE_Init>
|
|
|
|
/* USER CODE END 2 */
|
|
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
8000564: bf00 nop
|
|
8000566: e7fd b.n 8000564 <main+0x34>
|
|
|
|
08000568 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8000568: b580 push {r7, lr}
|
|
800056a: b094 sub sp, #80 @ 0x50
|
|
800056c: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
800056e: f107 031c add.w r3, r7, #28
|
|
8000572: 2234 movs r2, #52 @ 0x34
|
|
8000574: 2100 movs r1, #0
|
|
8000576: 4618 mov r0, r3
|
|
8000578: f008 f9d8 bl 800892c <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
800057c: f107 0308 add.w r3, r7, #8
|
|
8000580: 2200 movs r2, #0
|
|
8000582: 601a str r2, [r3, #0]
|
|
8000584: 605a str r2, [r3, #4]
|
|
8000586: 609a str r2, [r3, #8]
|
|
8000588: 60da str r2, [r3, #12]
|
|
800058a: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800058c: 2300 movs r3, #0
|
|
800058e: 607b str r3, [r7, #4]
|
|
8000590: 4b29 ldr r3, [pc, #164] @ (8000638 <SystemClock_Config+0xd0>)
|
|
8000592: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000594: 4a28 ldr r2, [pc, #160] @ (8000638 <SystemClock_Config+0xd0>)
|
|
8000596: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800059a: 6413 str r3, [r2, #64] @ 0x40
|
|
800059c: 4b26 ldr r3, [pc, #152] @ (8000638 <SystemClock_Config+0xd0>)
|
|
800059e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80005a0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80005a4: 607b str r3, [r7, #4]
|
|
80005a6: 687b ldr r3, [r7, #4]
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
|
|
80005a8: 2300 movs r3, #0
|
|
80005aa: 603b str r3, [r7, #0]
|
|
80005ac: 4b23 ldr r3, [pc, #140] @ (800063c <SystemClock_Config+0xd4>)
|
|
80005ae: 681b ldr r3, [r3, #0]
|
|
80005b0: f423 4340 bic.w r3, r3, #49152 @ 0xc000
|
|
80005b4: 4a21 ldr r2, [pc, #132] @ (800063c <SystemClock_Config+0xd4>)
|
|
80005b6: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
80005ba: 6013 str r3, [r2, #0]
|
|
80005bc: 4b1f ldr r3, [pc, #124] @ (800063c <SystemClock_Config+0xd4>)
|
|
80005be: 681b ldr r3, [r3, #0]
|
|
80005c0: f403 4340 and.w r3, r3, #49152 @ 0xc000
|
|
80005c4: 603b str r3, [r7, #0]
|
|
80005c6: 683b ldr r3, [r7, #0]
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
|
80005c8: 2302 movs r3, #2
|
|
80005ca: 61fb str r3, [r7, #28]
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
80005cc: 2301 movs r3, #1
|
|
80005ce: 62bb str r3, [r7, #40] @ 0x28
|
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
|
80005d0: 2310 movs r3, #16
|
|
80005d2: 62fb str r3, [r7, #44] @ 0x2c
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
80005d4: 2302 movs r3, #2
|
|
80005d6: 637b str r3, [r7, #52] @ 0x34
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
80005d8: f44f 0380 mov.w r3, #4194304 @ 0x400000
|
|
80005dc: 63bb str r3, [r7, #56] @ 0x38
|
|
RCC_OscInitStruct.PLL.PLLM = 4;
|
|
80005de: 2304 movs r3, #4
|
|
80005e0: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.PLL.PLLN = 72;
|
|
80005e2: 2348 movs r3, #72 @ 0x48
|
|
80005e4: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
80005e6: 2302 movs r3, #2
|
|
80005e8: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLQ = 3;
|
|
80005ea: 2303 movs r3, #3
|
|
80005ec: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLR = 2;
|
|
80005ee: 2302 movs r3, #2
|
|
80005f0: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
80005f2: f107 031c add.w r3, r7, #28
|
|
80005f6: 4618 mov r0, r3
|
|
80005f8: f003 faca bl 8003b90 <HAL_RCC_OscConfig>
|
|
80005fc: 4603 mov r3, r0
|
|
80005fe: 2b00 cmp r3, #0
|
|
8000600: d001 beq.n 8000606 <SystemClock_Config+0x9e>
|
|
{
|
|
Error_Handler();
|
|
8000602: f000 fa69 bl 8000ad8 <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
8000606: 230f movs r3, #15
|
|
8000608: 60bb str r3, [r7, #8]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
|
|
800060a: 2300 movs r3, #0
|
|
800060c: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
800060e: 2300 movs r3, #0
|
|
8000610: 613b str r3, [r7, #16]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
8000612: 2300 movs r3, #0
|
|
8000614: 617b str r3, [r7, #20]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
8000616: 2300 movs r3, #0
|
|
8000618: 61bb str r3, [r7, #24]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
|
|
800061a: f107 0308 add.w r3, r7, #8
|
|
800061e: 2100 movs r1, #0
|
|
8000620: 4618 mov r0, r3
|
|
8000622: f002 fc41 bl 8002ea8 <HAL_RCC_ClockConfig>
|
|
8000626: 4603 mov r3, r0
|
|
8000628: 2b00 cmp r3, #0
|
|
800062a: d001 beq.n 8000630 <SystemClock_Config+0xc8>
|
|
{
|
|
Error_Handler();
|
|
800062c: f000 fa54 bl 8000ad8 <Error_Handler>
|
|
}
|
|
}
|
|
8000630: bf00 nop
|
|
8000632: 3750 adds r7, #80 @ 0x50
|
|
8000634: 46bd mov sp, r7
|
|
8000636: bd80 pop {r7, pc}
|
|
8000638: 40023800 .word 0x40023800
|
|
800063c: 40007000 .word 0x40007000
|
|
|
|
08000640 <MX_I2C1_Init>:
|
|
* @brief I2C1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C1_Init(void)
|
|
{
|
|
8000640: b580 push {r7, lr}
|
|
8000642: af00 add r7, sp, #0
|
|
/* USER CODE END I2C1_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C1_Init 1 */
|
|
|
|
/* USER CODE END I2C1_Init 1 */
|
|
hi2c1.Instance = I2C1;
|
|
8000644: 4b12 ldr r3, [pc, #72] @ (8000690 <MX_I2C1_Init+0x50>)
|
|
8000646: 4a13 ldr r2, [pc, #76] @ (8000694 <MX_I2C1_Init+0x54>)
|
|
8000648: 601a str r2, [r3, #0]
|
|
hi2c1.Init.ClockSpeed = 100000;
|
|
800064a: 4b11 ldr r3, [pc, #68] @ (8000690 <MX_I2C1_Init+0x50>)
|
|
800064c: 4a12 ldr r2, [pc, #72] @ (8000698 <MX_I2C1_Init+0x58>)
|
|
800064e: 605a str r2, [r3, #4]
|
|
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
|
|
8000650: 4b0f ldr r3, [pc, #60] @ (8000690 <MX_I2C1_Init+0x50>)
|
|
8000652: 2200 movs r2, #0
|
|
8000654: 609a str r2, [r3, #8]
|
|
hi2c1.Init.OwnAddress1 = 0;
|
|
8000656: 4b0e ldr r3, [pc, #56] @ (8000690 <MX_I2C1_Init+0x50>)
|
|
8000658: 2200 movs r2, #0
|
|
800065a: 60da str r2, [r3, #12]
|
|
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
800065c: 4b0c ldr r3, [pc, #48] @ (8000690 <MX_I2C1_Init+0x50>)
|
|
800065e: f44f 4280 mov.w r2, #16384 @ 0x4000
|
|
8000662: 611a str r2, [r3, #16]
|
|
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8000664: 4b0a ldr r3, [pc, #40] @ (8000690 <MX_I2C1_Init+0x50>)
|
|
8000666: 2200 movs r2, #0
|
|
8000668: 615a str r2, [r3, #20]
|
|
hi2c1.Init.OwnAddress2 = 0;
|
|
800066a: 4b09 ldr r3, [pc, #36] @ (8000690 <MX_I2C1_Init+0x50>)
|
|
800066c: 2200 movs r2, #0
|
|
800066e: 619a str r2, [r3, #24]
|
|
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8000670: 4b07 ldr r3, [pc, #28] @ (8000690 <MX_I2C1_Init+0x50>)
|
|
8000672: 2200 movs r2, #0
|
|
8000674: 61da str r2, [r3, #28]
|
|
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8000676: 4b06 ldr r3, [pc, #24] @ (8000690 <MX_I2C1_Init+0x50>)
|
|
8000678: 2200 movs r2, #0
|
|
800067a: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
|
|
800067c: 4804 ldr r0, [pc, #16] @ (8000690 <MX_I2C1_Init+0x50>)
|
|
800067e: f001 f849 bl 8001714 <HAL_I2C_Init>
|
|
8000682: 4603 mov r3, r0
|
|
8000684: 2b00 cmp r3, #0
|
|
8000686: d001 beq.n 800068c <MX_I2C1_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8000688: f000 fa26 bl 8000ad8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C1_Init 2 */
|
|
|
|
/* USER CODE END I2C1_Init 2 */
|
|
|
|
}
|
|
800068c: bf00 nop
|
|
800068e: bd80 pop {r7, pc}
|
|
8000690: 20000148 .word 0x20000148
|
|
8000694: 40005400 .word 0x40005400
|
|
8000698: 000186a0 .word 0x000186a0
|
|
|
|
0800069c <MX_TIM2_Init>:
|
|
* @brief TIM2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM2_Init(void)
|
|
{
|
|
800069c: b580 push {r7, lr}
|
|
800069e: b08a sub sp, #40 @ 0x28
|
|
80006a0: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM2_Init 0 */
|
|
|
|
/* USER CODE END TIM2_Init 0 */
|
|
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
80006a2: f107 0320 add.w r3, r7, #32
|
|
80006a6: 2200 movs r2, #0
|
|
80006a8: 601a str r2, [r3, #0]
|
|
80006aa: 605a str r2, [r3, #4]
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
80006ac: 1d3b adds r3, r7, #4
|
|
80006ae: 2200 movs r2, #0
|
|
80006b0: 601a str r2, [r3, #0]
|
|
80006b2: 605a str r2, [r3, #4]
|
|
80006b4: 609a str r2, [r3, #8]
|
|
80006b6: 60da str r2, [r3, #12]
|
|
80006b8: 611a str r2, [r3, #16]
|
|
80006ba: 615a str r2, [r3, #20]
|
|
80006bc: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE BEGIN TIM2_Init 1 */
|
|
|
|
/* USER CODE END TIM2_Init 1 */
|
|
htim2.Instance = TIM2;
|
|
80006be: 4b22 ldr r3, [pc, #136] @ (8000748 <MX_TIM2_Init+0xac>)
|
|
80006c0: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
|
|
80006c4: 601a str r2, [r3, #0]
|
|
htim2.Init.Prescaler = 0;
|
|
80006c6: 4b20 ldr r3, [pc, #128] @ (8000748 <MX_TIM2_Init+0xac>)
|
|
80006c8: 2200 movs r2, #0
|
|
80006ca: 605a str r2, [r3, #4]
|
|
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
80006cc: 4b1e ldr r3, [pc, #120] @ (8000748 <MX_TIM2_Init+0xac>)
|
|
80006ce: 2200 movs r2, #0
|
|
80006d0: 609a str r2, [r3, #8]
|
|
htim2.Init.Period = 4294967295;
|
|
80006d2: 4b1d ldr r3, [pc, #116] @ (8000748 <MX_TIM2_Init+0xac>)
|
|
80006d4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80006d8: 60da str r2, [r3, #12]
|
|
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
80006da: 4b1b ldr r3, [pc, #108] @ (8000748 <MX_TIM2_Init+0xac>)
|
|
80006dc: 2200 movs r2, #0
|
|
80006de: 611a str r2, [r3, #16]
|
|
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
80006e0: 4b19 ldr r3, [pc, #100] @ (8000748 <MX_TIM2_Init+0xac>)
|
|
80006e2: 2200 movs r2, #0
|
|
80006e4: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_OC_Init(&htim2) != HAL_OK)
|
|
80006e6: 4818 ldr r0, [pc, #96] @ (8000748 <MX_TIM2_Init+0xac>)
|
|
80006e8: f003 fcf0 bl 80040cc <HAL_TIM_OC_Init>
|
|
80006ec: 4603 mov r3, r0
|
|
80006ee: 2b00 cmp r3, #0
|
|
80006f0: d001 beq.n 80006f6 <MX_TIM2_Init+0x5a>
|
|
{
|
|
Error_Handler();
|
|
80006f2: f000 f9f1 bl 8000ad8 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
80006f6: 2300 movs r3, #0
|
|
80006f8: 623b str r3, [r7, #32]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
80006fa: 2300 movs r3, #0
|
|
80006fc: 627b str r3, [r7, #36] @ 0x24
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
|
|
80006fe: f107 0320 add.w r3, r7, #32
|
|
8000702: 4619 mov r1, r3
|
|
8000704: 4810 ldr r0, [pc, #64] @ (8000748 <MX_TIM2_Init+0xac>)
|
|
8000706: f004 f889 bl 800481c <HAL_TIMEx_MasterConfigSynchronization>
|
|
800070a: 4603 mov r3, r0
|
|
800070c: 2b00 cmp r3, #0
|
|
800070e: d001 beq.n 8000714 <MX_TIM2_Init+0x78>
|
|
{
|
|
Error_Handler();
|
|
8000710: f000 f9e2 bl 8000ad8 <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE;
|
|
8000714: 2350 movs r3, #80 @ 0x50
|
|
8000716: 607b str r3, [r7, #4]
|
|
sConfigOC.Pulse = 0;
|
|
8000718: 2300 movs r3, #0
|
|
800071a: 60bb str r3, [r7, #8]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
800071c: 2300 movs r3, #0
|
|
800071e: 60fb str r3, [r7, #12]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
8000720: 2300 movs r3, #0
|
|
8000722: 617b str r3, [r7, #20]
|
|
if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
8000724: 1d3b adds r3, r7, #4
|
|
8000726: 2200 movs r2, #0
|
|
8000728: 4619 mov r1, r3
|
|
800072a: 4807 ldr r0, [pc, #28] @ (8000748 <MX_TIM2_Init+0xac>)
|
|
800072c: f003 fdc4 bl 80042b8 <HAL_TIM_OC_ConfigChannel>
|
|
8000730: 4603 mov r3, r0
|
|
8000732: 2b00 cmp r3, #0
|
|
8000734: d001 beq.n 800073a <MX_TIM2_Init+0x9e>
|
|
{
|
|
Error_Handler();
|
|
8000736: f000 f9cf bl 8000ad8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM2_Init 2 */
|
|
|
|
/* USER CODE END TIM2_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim2);
|
|
800073a: 4803 ldr r0, [pc, #12] @ (8000748 <MX_TIM2_Init+0xac>)
|
|
800073c: f000 faaa bl 8000c94 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
8000740: bf00 nop
|
|
8000742: 3728 adds r7, #40 @ 0x28
|
|
8000744: 46bd mov sp, r7
|
|
8000746: bd80 pop {r7, pc}
|
|
8000748: 2000019c .word 0x2000019c
|
|
|
|
0800074c <MX_TIM3_Init>:
|
|
* @brief TIM3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM3_Init(void)
|
|
{
|
|
800074c: b580 push {r7, lr}
|
|
800074e: b08c sub sp, #48 @ 0x30
|
|
8000750: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM3_Init 0 */
|
|
|
|
/* USER CODE END TIM3_Init 0 */
|
|
|
|
TIM_Encoder_InitTypeDef sConfig = {0};
|
|
8000752: f107 030c add.w r3, r7, #12
|
|
8000756: 2224 movs r2, #36 @ 0x24
|
|
8000758: 2100 movs r1, #0
|
|
800075a: 4618 mov r0, r3
|
|
800075c: f008 f8e6 bl 800892c <memset>
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8000760: 1d3b adds r3, r7, #4
|
|
8000762: 2200 movs r2, #0
|
|
8000764: 601a str r2, [r3, #0]
|
|
8000766: 605a str r2, [r3, #4]
|
|
|
|
/* USER CODE BEGIN TIM3_Init 1 */
|
|
|
|
/* USER CODE END TIM3_Init 1 */
|
|
htim3.Instance = TIM3;
|
|
8000768: 4b20 ldr r3, [pc, #128] @ (80007ec <MX_TIM3_Init+0xa0>)
|
|
800076a: 4a21 ldr r2, [pc, #132] @ (80007f0 <MX_TIM3_Init+0xa4>)
|
|
800076c: 601a str r2, [r3, #0]
|
|
htim3.Init.Prescaler = 0;
|
|
800076e: 4b1f ldr r3, [pc, #124] @ (80007ec <MX_TIM3_Init+0xa0>)
|
|
8000770: 2200 movs r2, #0
|
|
8000772: 605a str r2, [r3, #4]
|
|
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8000774: 4b1d ldr r3, [pc, #116] @ (80007ec <MX_TIM3_Init+0xa0>)
|
|
8000776: 2200 movs r2, #0
|
|
8000778: 609a str r2, [r3, #8]
|
|
htim3.Init.Period = 65535;
|
|
800077a: 4b1c ldr r3, [pc, #112] @ (80007ec <MX_TIM3_Init+0xa0>)
|
|
800077c: f64f 72ff movw r2, #65535 @ 0xffff
|
|
8000780: 60da str r2, [r3, #12]
|
|
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8000782: 4b1a ldr r3, [pc, #104] @ (80007ec <MX_TIM3_Init+0xa0>)
|
|
8000784: 2200 movs r2, #0
|
|
8000786: 611a str r2, [r3, #16]
|
|
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8000788: 4b18 ldr r3, [pc, #96] @ (80007ec <MX_TIM3_Init+0xa0>)
|
|
800078a: 2200 movs r2, #0
|
|
800078c: 619a str r2, [r3, #24]
|
|
sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
|
|
800078e: 2301 movs r3, #1
|
|
8000790: 60fb str r3, [r7, #12]
|
|
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
|
|
8000792: 2300 movs r3, #0
|
|
8000794: 613b str r3, [r7, #16]
|
|
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
|
|
8000796: 2301 movs r3, #1
|
|
8000798: 617b str r3, [r7, #20]
|
|
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
|
|
800079a: 2300 movs r3, #0
|
|
800079c: 61bb str r3, [r7, #24]
|
|
sConfig.IC1Filter = 0;
|
|
800079e: 2300 movs r3, #0
|
|
80007a0: 61fb str r3, [r7, #28]
|
|
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
|
|
80007a2: 2300 movs r3, #0
|
|
80007a4: 623b str r3, [r7, #32]
|
|
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
|
|
80007a6: 2301 movs r3, #1
|
|
80007a8: 627b str r3, [r7, #36] @ 0x24
|
|
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
|
|
80007aa: 2300 movs r3, #0
|
|
80007ac: 62bb str r3, [r7, #40] @ 0x28
|
|
sConfig.IC2Filter = 0;
|
|
80007ae: 2300 movs r3, #0
|
|
80007b0: 62fb str r3, [r7, #44] @ 0x2c
|
|
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
|
|
80007b2: f107 030c add.w r3, r7, #12
|
|
80007b6: 4619 mov r1, r3
|
|
80007b8: 480c ldr r0, [pc, #48] @ (80007ec <MX_TIM3_Init+0xa0>)
|
|
80007ba: f003 fcd6 bl 800416a <HAL_TIM_Encoder_Init>
|
|
80007be: 4603 mov r3, r0
|
|
80007c0: 2b00 cmp r3, #0
|
|
80007c2: d001 beq.n 80007c8 <MX_TIM3_Init+0x7c>
|
|
{
|
|
Error_Handler();
|
|
80007c4: f000 f988 bl 8000ad8 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
80007c8: 2300 movs r3, #0
|
|
80007ca: 607b str r3, [r7, #4]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
80007cc: 2300 movs r3, #0
|
|
80007ce: 60bb str r3, [r7, #8]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
|
80007d0: 1d3b adds r3, r7, #4
|
|
80007d2: 4619 mov r1, r3
|
|
80007d4: 4805 ldr r0, [pc, #20] @ (80007ec <MX_TIM3_Init+0xa0>)
|
|
80007d6: f004 f821 bl 800481c <HAL_TIMEx_MasterConfigSynchronization>
|
|
80007da: 4603 mov r3, r0
|
|
80007dc: 2b00 cmp r3, #0
|
|
80007de: d001 beq.n 80007e4 <MX_TIM3_Init+0x98>
|
|
{
|
|
Error_Handler();
|
|
80007e0: f000 f97a bl 8000ad8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM3_Init 2 */
|
|
|
|
/* USER CODE END TIM3_Init 2 */
|
|
|
|
}
|
|
80007e4: bf00 nop
|
|
80007e6: 3730 adds r7, #48 @ 0x30
|
|
80007e8: 46bd mov sp, r7
|
|
80007ea: bd80 pop {r7, pc}
|
|
80007ec: 200001e4 .word 0x200001e4
|
|
80007f0: 40000400 .word 0x40000400
|
|
|
|
080007f4 <MX_UART4_Init>:
|
|
* @brief UART4 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_UART4_Init(void)
|
|
{
|
|
80007f4: b580 push {r7, lr}
|
|
80007f6: af00 add r7, sp, #0
|
|
/* USER CODE END UART4_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART4_Init 1 */
|
|
|
|
/* USER CODE END UART4_Init 1 */
|
|
huart4.Instance = UART4;
|
|
80007f8: 4b11 ldr r3, [pc, #68] @ (8000840 <MX_UART4_Init+0x4c>)
|
|
80007fa: 4a12 ldr r2, [pc, #72] @ (8000844 <MX_UART4_Init+0x50>)
|
|
80007fc: 601a str r2, [r3, #0]
|
|
huart4.Init.BaudRate = 115200;
|
|
80007fe: 4b10 ldr r3, [pc, #64] @ (8000840 <MX_UART4_Init+0x4c>)
|
|
8000800: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8000804: 605a str r2, [r3, #4]
|
|
huart4.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8000806: 4b0e ldr r3, [pc, #56] @ (8000840 <MX_UART4_Init+0x4c>)
|
|
8000808: 2200 movs r2, #0
|
|
800080a: 609a str r2, [r3, #8]
|
|
huart4.Init.StopBits = UART_STOPBITS_1;
|
|
800080c: 4b0c ldr r3, [pc, #48] @ (8000840 <MX_UART4_Init+0x4c>)
|
|
800080e: 2200 movs r2, #0
|
|
8000810: 60da str r2, [r3, #12]
|
|
huart4.Init.Parity = UART_PARITY_NONE;
|
|
8000812: 4b0b ldr r3, [pc, #44] @ (8000840 <MX_UART4_Init+0x4c>)
|
|
8000814: 2200 movs r2, #0
|
|
8000816: 611a str r2, [r3, #16]
|
|
huart4.Init.Mode = UART_MODE_TX_RX;
|
|
8000818: 4b09 ldr r3, [pc, #36] @ (8000840 <MX_UART4_Init+0x4c>)
|
|
800081a: 220c movs r2, #12
|
|
800081c: 615a str r2, [r3, #20]
|
|
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
800081e: 4b08 ldr r3, [pc, #32] @ (8000840 <MX_UART4_Init+0x4c>)
|
|
8000820: 2200 movs r2, #0
|
|
8000822: 619a str r2, [r3, #24]
|
|
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8000824: 4b06 ldr r3, [pc, #24] @ (8000840 <MX_UART4_Init+0x4c>)
|
|
8000826: 2200 movs r2, #0
|
|
8000828: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart4) != HAL_OK)
|
|
800082a: 4805 ldr r0, [pc, #20] @ (8000840 <MX_UART4_Init+0x4c>)
|
|
800082c: f004 f872 bl 8004914 <HAL_UART_Init>
|
|
8000830: 4603 mov r3, r0
|
|
8000832: 2b00 cmp r3, #0
|
|
8000834: d001 beq.n 800083a <MX_UART4_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8000836: f000 f94f bl 8000ad8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART4_Init 2 */
|
|
|
|
/* USER CODE END UART4_Init 2 */
|
|
|
|
}
|
|
800083a: bf00 nop
|
|
800083c: bd80 pop {r7, pc}
|
|
800083e: bf00 nop
|
|
8000840: 2000022c .word 0x2000022c
|
|
8000844: 40004c00 .word 0x40004c00
|
|
|
|
08000848 <MX_UART5_Init>:
|
|
* @brief UART5 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_UART5_Init(void)
|
|
{
|
|
8000848: b580 push {r7, lr}
|
|
800084a: af00 add r7, sp, #0
|
|
/* USER CODE END UART5_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART5_Init 1 */
|
|
|
|
/* USER CODE END UART5_Init 1 */
|
|
huart5.Instance = UART5;
|
|
800084c: 4b11 ldr r3, [pc, #68] @ (8000894 <MX_UART5_Init+0x4c>)
|
|
800084e: 4a12 ldr r2, [pc, #72] @ (8000898 <MX_UART5_Init+0x50>)
|
|
8000850: 601a str r2, [r3, #0]
|
|
huart5.Init.BaudRate = 115200;
|
|
8000852: 4b10 ldr r3, [pc, #64] @ (8000894 <MX_UART5_Init+0x4c>)
|
|
8000854: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8000858: 605a str r2, [r3, #4]
|
|
huart5.Init.WordLength = UART_WORDLENGTH_8B;
|
|
800085a: 4b0e ldr r3, [pc, #56] @ (8000894 <MX_UART5_Init+0x4c>)
|
|
800085c: 2200 movs r2, #0
|
|
800085e: 609a str r2, [r3, #8]
|
|
huart5.Init.StopBits = UART_STOPBITS_1;
|
|
8000860: 4b0c ldr r3, [pc, #48] @ (8000894 <MX_UART5_Init+0x4c>)
|
|
8000862: 2200 movs r2, #0
|
|
8000864: 60da str r2, [r3, #12]
|
|
huart5.Init.Parity = UART_PARITY_NONE;
|
|
8000866: 4b0b ldr r3, [pc, #44] @ (8000894 <MX_UART5_Init+0x4c>)
|
|
8000868: 2200 movs r2, #0
|
|
800086a: 611a str r2, [r3, #16]
|
|
huart5.Init.Mode = UART_MODE_TX_RX;
|
|
800086c: 4b09 ldr r3, [pc, #36] @ (8000894 <MX_UART5_Init+0x4c>)
|
|
800086e: 220c movs r2, #12
|
|
8000870: 615a str r2, [r3, #20]
|
|
huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8000872: 4b08 ldr r3, [pc, #32] @ (8000894 <MX_UART5_Init+0x4c>)
|
|
8000874: 2200 movs r2, #0
|
|
8000876: 619a str r2, [r3, #24]
|
|
huart5.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8000878: 4b06 ldr r3, [pc, #24] @ (8000894 <MX_UART5_Init+0x4c>)
|
|
800087a: 2200 movs r2, #0
|
|
800087c: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart5) != HAL_OK)
|
|
800087e: 4805 ldr r0, [pc, #20] @ (8000894 <MX_UART5_Init+0x4c>)
|
|
8000880: f004 f848 bl 8004914 <HAL_UART_Init>
|
|
8000884: 4603 mov r3, r0
|
|
8000886: 2b00 cmp r3, #0
|
|
8000888: d001 beq.n 800088e <MX_UART5_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
800088a: f000 f925 bl 8000ad8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART5_Init 2 */
|
|
|
|
/* USER CODE END UART5_Init 2 */
|
|
|
|
}
|
|
800088e: bf00 nop
|
|
8000890: bd80 pop {r7, pc}
|
|
8000892: bf00 nop
|
|
8000894: 20000274 .word 0x20000274
|
|
8000898: 40005000 .word 0x40005000
|
|
|
|
0800089c <MX_USART1_UART_Init>:
|
|
* @brief USART1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART1_UART_Init(void)
|
|
{
|
|
800089c: b580 push {r7, lr}
|
|
800089e: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
80008a0: 4b11 ldr r3, [pc, #68] @ (80008e8 <MX_USART1_UART_Init+0x4c>)
|
|
80008a2: 4a12 ldr r2, [pc, #72] @ (80008ec <MX_USART1_UART_Init+0x50>)
|
|
80008a4: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
80008a6: 4b10 ldr r3, [pc, #64] @ (80008e8 <MX_USART1_UART_Init+0x4c>)
|
|
80008a8: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
80008ac: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
80008ae: 4b0e ldr r3, [pc, #56] @ (80008e8 <MX_USART1_UART_Init+0x4c>)
|
|
80008b0: 2200 movs r2, #0
|
|
80008b2: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
80008b4: 4b0c ldr r3, [pc, #48] @ (80008e8 <MX_USART1_UART_Init+0x4c>)
|
|
80008b6: 2200 movs r2, #0
|
|
80008b8: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
80008ba: 4b0b ldr r3, [pc, #44] @ (80008e8 <MX_USART1_UART_Init+0x4c>)
|
|
80008bc: 2200 movs r2, #0
|
|
80008be: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
80008c0: 4b09 ldr r3, [pc, #36] @ (80008e8 <MX_USART1_UART_Init+0x4c>)
|
|
80008c2: 220c movs r2, #12
|
|
80008c4: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80008c6: 4b08 ldr r3, [pc, #32] @ (80008e8 <MX_USART1_UART_Init+0x4c>)
|
|
80008c8: 2200 movs r2, #0
|
|
80008ca: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80008cc: 4b06 ldr r3, [pc, #24] @ (80008e8 <MX_USART1_UART_Init+0x4c>)
|
|
80008ce: 2200 movs r2, #0
|
|
80008d0: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
80008d2: 4805 ldr r0, [pc, #20] @ (80008e8 <MX_USART1_UART_Init+0x4c>)
|
|
80008d4: f004 f81e bl 8004914 <HAL_UART_Init>
|
|
80008d8: 4603 mov r3, r0
|
|
80008da: 2b00 cmp r3, #0
|
|
80008dc: d001 beq.n 80008e2 <MX_USART1_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
80008de: f000 f8fb bl 8000ad8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
80008e2: bf00 nop
|
|
80008e4: bd80 pop {r7, pc}
|
|
80008e6: bf00 nop
|
|
80008e8: 200002bc .word 0x200002bc
|
|
80008ec: 40011000 .word 0x40011000
|
|
|
|
080008f0 <MX_USART2_UART_Init>:
|
|
* @brief USART2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART2_UART_Init(void)
|
|
{
|
|
80008f0: b580 push {r7, lr}
|
|
80008f2: af00 add r7, sp, #0
|
|
/* USER CODE END USART2_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
|
|
|
/* USER CODE END USART2_Init 1 */
|
|
huart2.Instance = USART2;
|
|
80008f4: 4b11 ldr r3, [pc, #68] @ (800093c <MX_USART2_UART_Init+0x4c>)
|
|
80008f6: 4a12 ldr r2, [pc, #72] @ (8000940 <MX_USART2_UART_Init+0x50>)
|
|
80008f8: 601a str r2, [r3, #0]
|
|
huart2.Init.BaudRate = 115200;
|
|
80008fa: 4b10 ldr r3, [pc, #64] @ (800093c <MX_USART2_UART_Init+0x4c>)
|
|
80008fc: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8000900: 605a str r2, [r3, #4]
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8000902: 4b0e ldr r3, [pc, #56] @ (800093c <MX_USART2_UART_Init+0x4c>)
|
|
8000904: 2200 movs r2, #0
|
|
8000906: 609a str r2, [r3, #8]
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
8000908: 4b0c ldr r3, [pc, #48] @ (800093c <MX_USART2_UART_Init+0x4c>)
|
|
800090a: 2200 movs r2, #0
|
|
800090c: 60da str r2, [r3, #12]
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
800090e: 4b0b ldr r3, [pc, #44] @ (800093c <MX_USART2_UART_Init+0x4c>)
|
|
8000910: 2200 movs r2, #0
|
|
8000912: 611a str r2, [r3, #16]
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
8000914: 4b09 ldr r3, [pc, #36] @ (800093c <MX_USART2_UART_Init+0x4c>)
|
|
8000916: 220c movs r2, #12
|
|
8000918: 615a str r2, [r3, #20]
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
800091a: 4b08 ldr r3, [pc, #32] @ (800093c <MX_USART2_UART_Init+0x4c>)
|
|
800091c: 2200 movs r2, #0
|
|
800091e: 619a str r2, [r3, #24]
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8000920: 4b06 ldr r3, [pc, #24] @ (800093c <MX_USART2_UART_Init+0x4c>)
|
|
8000922: 2200 movs r2, #0
|
|
8000924: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
|
8000926: 4805 ldr r0, [pc, #20] @ (800093c <MX_USART2_UART_Init+0x4c>)
|
|
8000928: f003 fff4 bl 8004914 <HAL_UART_Init>
|
|
800092c: 4603 mov r3, r0
|
|
800092e: 2b00 cmp r3, #0
|
|
8000930: d001 beq.n 8000936 <MX_USART2_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8000932: f000 f8d1 bl 8000ad8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
|
|
|
/* USER CODE END USART2_Init 2 */
|
|
|
|
}
|
|
8000936: bf00 nop
|
|
8000938: bd80 pop {r7, pc}
|
|
800093a: bf00 nop
|
|
800093c: 20000304 .word 0x20000304
|
|
8000940: 40004400 .word 0x40004400
|
|
|
|
08000944 <MX_USART3_UART_Init>:
|
|
* @brief USART3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART3_UART_Init(void)
|
|
{
|
|
8000944: b580 push {r7, lr}
|
|
8000946: af00 add r7, sp, #0
|
|
/* USER CODE END USART3_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART3_Init 1 */
|
|
|
|
/* USER CODE END USART3_Init 1 */
|
|
huart3.Instance = USART3;
|
|
8000948: 4b11 ldr r3, [pc, #68] @ (8000990 <MX_USART3_UART_Init+0x4c>)
|
|
800094a: 4a12 ldr r2, [pc, #72] @ (8000994 <MX_USART3_UART_Init+0x50>)
|
|
800094c: 601a str r2, [r3, #0]
|
|
huart3.Init.BaudRate = 115200;
|
|
800094e: 4b10 ldr r3, [pc, #64] @ (8000990 <MX_USART3_UART_Init+0x4c>)
|
|
8000950: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8000954: 605a str r2, [r3, #4]
|
|
huart3.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8000956: 4b0e ldr r3, [pc, #56] @ (8000990 <MX_USART3_UART_Init+0x4c>)
|
|
8000958: 2200 movs r2, #0
|
|
800095a: 609a str r2, [r3, #8]
|
|
huart3.Init.StopBits = UART_STOPBITS_1;
|
|
800095c: 4b0c ldr r3, [pc, #48] @ (8000990 <MX_USART3_UART_Init+0x4c>)
|
|
800095e: 2200 movs r2, #0
|
|
8000960: 60da str r2, [r3, #12]
|
|
huart3.Init.Parity = UART_PARITY_NONE;
|
|
8000962: 4b0b ldr r3, [pc, #44] @ (8000990 <MX_USART3_UART_Init+0x4c>)
|
|
8000964: 2200 movs r2, #0
|
|
8000966: 611a str r2, [r3, #16]
|
|
huart3.Init.Mode = UART_MODE_TX_RX;
|
|
8000968: 4b09 ldr r3, [pc, #36] @ (8000990 <MX_USART3_UART_Init+0x4c>)
|
|
800096a: 220c movs r2, #12
|
|
800096c: 615a str r2, [r3, #20]
|
|
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
800096e: 4b08 ldr r3, [pc, #32] @ (8000990 <MX_USART3_UART_Init+0x4c>)
|
|
8000970: 2200 movs r2, #0
|
|
8000972: 619a str r2, [r3, #24]
|
|
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8000974: 4b06 ldr r3, [pc, #24] @ (8000990 <MX_USART3_UART_Init+0x4c>)
|
|
8000976: 2200 movs r2, #0
|
|
8000978: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart3) != HAL_OK)
|
|
800097a: 4805 ldr r0, [pc, #20] @ (8000990 <MX_USART3_UART_Init+0x4c>)
|
|
800097c: f003 ffca bl 8004914 <HAL_UART_Init>
|
|
8000980: 4603 mov r3, r0
|
|
8000982: 2b00 cmp r3, #0
|
|
8000984: d001 beq.n 800098a <MX_USART3_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8000986: f000 f8a7 bl 8000ad8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART3_Init 2 */
|
|
|
|
/* USER CODE END USART3_Init 2 */
|
|
|
|
}
|
|
800098a: bf00 nop
|
|
800098c: bd80 pop {r7, pc}
|
|
800098e: bf00 nop
|
|
8000990: 2000034c .word 0x2000034c
|
|
8000994: 40004800 .word 0x40004800
|
|
|
|
08000998 <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8000998: b580 push {r7, lr}
|
|
800099a: b08a sub sp, #40 @ 0x28
|
|
800099c: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800099e: f107 0314 add.w r3, r7, #20
|
|
80009a2: 2200 movs r2, #0
|
|
80009a4: 601a str r2, [r3, #0]
|
|
80009a6: 605a str r2, [r3, #4]
|
|
80009a8: 609a str r2, [r3, #8]
|
|
80009aa: 60da str r2, [r3, #12]
|
|
80009ac: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
80009ae: 2300 movs r3, #0
|
|
80009b0: 613b str r3, [r7, #16]
|
|
80009b2: 4b45 ldr r3, [pc, #276] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
80009b4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80009b6: 4a44 ldr r2, [pc, #272] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
80009b8: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80009bc: 6313 str r3, [r2, #48] @ 0x30
|
|
80009be: 4b42 ldr r3, [pc, #264] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
80009c0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80009c2: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80009c6: 613b str r3, [r7, #16]
|
|
80009c8: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80009ca: 2300 movs r3, #0
|
|
80009cc: 60fb str r3, [r7, #12]
|
|
80009ce: 4b3e ldr r3, [pc, #248] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
80009d0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80009d2: 4a3d ldr r2, [pc, #244] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
80009d4: f043 0301 orr.w r3, r3, #1
|
|
80009d8: 6313 str r3, [r2, #48] @ 0x30
|
|
80009da: 4b3b ldr r3, [pc, #236] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
80009dc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80009de: f003 0301 and.w r3, r3, #1
|
|
80009e2: 60fb str r3, [r7, #12]
|
|
80009e4: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
80009e6: 2300 movs r3, #0
|
|
80009e8: 60bb str r3, [r7, #8]
|
|
80009ea: 4b37 ldr r3, [pc, #220] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
80009ec: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80009ee: 4a36 ldr r2, [pc, #216] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
80009f0: f043 0304 orr.w r3, r3, #4
|
|
80009f4: 6313 str r3, [r2, #48] @ 0x30
|
|
80009f6: 4b34 ldr r3, [pc, #208] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
80009f8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80009fa: f003 0304 and.w r3, r3, #4
|
|
80009fe: 60bb str r3, [r7, #8]
|
|
8000a00: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000a02: 2300 movs r3, #0
|
|
8000a04: 607b str r3, [r7, #4]
|
|
8000a06: 4b30 ldr r3, [pc, #192] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
8000a08: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a0a: 4a2f ldr r2, [pc, #188] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
8000a0c: f043 0302 orr.w r3, r3, #2
|
|
8000a10: 6313 str r3, [r2, #48] @ 0x30
|
|
8000a12: 4b2d ldr r3, [pc, #180] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
8000a14: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a16: f003 0302 and.w r3, r3, #2
|
|
8000a1a: 607b str r3, [r7, #4]
|
|
8000a1c: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8000a1e: 2300 movs r3, #0
|
|
8000a20: 603b str r3, [r7, #0]
|
|
8000a22: 4b29 ldr r3, [pc, #164] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
8000a24: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a26: 4a28 ldr r2, [pc, #160] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
8000a28: f043 0308 orr.w r3, r3, #8
|
|
8000a2c: 6313 str r3, [r2, #48] @ 0x30
|
|
8000a2e: 4b26 ldr r3, [pc, #152] @ (8000ac8 <MX_GPIO_Init+0x130>)
|
|
8000a30: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a32: f003 0308 and.w r3, r3, #8
|
|
8000a36: 603b str r3, [r7, #0]
|
|
8000a38: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET);
|
|
8000a3a: 2200 movs r2, #0
|
|
8000a3c: f44f 7170 mov.w r1, #960 @ 0x3c0
|
|
8000a40: 4822 ldr r0, [pc, #136] @ (8000acc <MX_GPIO_Init+0x134>)
|
|
8000a42: f000 fe4d bl 80016e0 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET);
|
|
8000a46: 2200 movs r2, #0
|
|
8000a48: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8000a4c: 4820 ldr r0, [pc, #128] @ (8000ad0 <MX_GPIO_Init+0x138>)
|
|
8000a4e: f000 fe47 bl 80016e0 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : PC4 PC5 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
|
|
8000a52: 2330 movs r3, #48 @ 0x30
|
|
8000a54: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8000a56: 2300 movs r3, #0
|
|
8000a58: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000a5a: 2300 movs r3, #0
|
|
8000a5c: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8000a5e: f107 0314 add.w r3, r7, #20
|
|
8000a62: 4619 mov r1, r3
|
|
8000a64: 4819 ldr r0, [pc, #100] @ (8000acc <MX_GPIO_Init+0x134>)
|
|
8000a66: f000 fca7 bl 80013b8 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PB0 PB1 PB2 PB10 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10;
|
|
8000a6a: f240 4307 movw r3, #1031 @ 0x407
|
|
8000a6e: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8000a70: 2300 movs r3, #0
|
|
8000a72: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000a74: 2300 movs r3, #0
|
|
8000a76: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8000a78: f107 0314 add.w r3, r7, #20
|
|
8000a7c: 4619 mov r1, r3
|
|
8000a7e: 4815 ldr r0, [pc, #84] @ (8000ad4 <MX_GPIO_Init+0x13c>)
|
|
8000a80: f000 fc9a bl 80013b8 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PC6 PC7 PC8 PC9 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9;
|
|
8000a84: f44f 7370 mov.w r3, #960 @ 0x3c0
|
|
8000a88: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000a8a: 2301 movs r3, #1
|
|
8000a8c: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000a8e: 2300 movs r3, #0
|
|
8000a90: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000a92: 2300 movs r3, #0
|
|
8000a94: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8000a96: f107 0314 add.w r3, r7, #20
|
|
8000a9a: 4619 mov r1, r3
|
|
8000a9c: 480b ldr r0, [pc, #44] @ (8000acc <MX_GPIO_Init+0x134>)
|
|
8000a9e: f000 fc8b bl 80013b8 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : PA8 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_8;
|
|
8000aa2: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8000aa6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000aa8: 2301 movs r3, #1
|
|
8000aaa: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000aac: 2300 movs r3, #0
|
|
8000aae: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000ab0: 2300 movs r3, #0
|
|
8000ab2: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000ab4: f107 0314 add.w r3, r7, #20
|
|
8000ab8: 4619 mov r1, r3
|
|
8000aba: 4805 ldr r0, [pc, #20] @ (8000ad0 <MX_GPIO_Init+0x138>)
|
|
8000abc: f000 fc7c bl 80013b8 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
8000ac0: bf00 nop
|
|
8000ac2: 3728 adds r7, #40 @ 0x28
|
|
8000ac4: 46bd mov sp, r7
|
|
8000ac6: bd80 pop {r7, pc}
|
|
8000ac8: 40023800 .word 0x40023800
|
|
8000acc: 40020800 .word 0x40020800
|
|
8000ad0: 40020000 .word 0x40020000
|
|
8000ad4: 40020400 .word 0x40020400
|
|
|
|
08000ad8 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8000ad8: b480 push {r7}
|
|
8000ada: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8000adc: b672 cpsid i
|
|
}
|
|
8000ade: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8000ae0: bf00 nop
|
|
8000ae2: e7fd b.n 8000ae0 <Error_Handler+0x8>
|
|
|
|
08000ae4 <HAL_MspInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8000ae4: b480 push {r7}
|
|
8000ae6: b083 sub sp, #12
|
|
8000ae8: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8000aea: 2300 movs r3, #0
|
|
8000aec: 607b str r3, [r7, #4]
|
|
8000aee: 4b10 ldr r3, [pc, #64] @ (8000b30 <HAL_MspInit+0x4c>)
|
|
8000af0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000af2: 4a0f ldr r2, [pc, #60] @ (8000b30 <HAL_MspInit+0x4c>)
|
|
8000af4: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8000af8: 6453 str r3, [r2, #68] @ 0x44
|
|
8000afa: 4b0d ldr r3, [pc, #52] @ (8000b30 <HAL_MspInit+0x4c>)
|
|
8000afc: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000afe: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8000b02: 607b str r3, [r7, #4]
|
|
8000b04: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000b06: 2300 movs r3, #0
|
|
8000b08: 603b str r3, [r7, #0]
|
|
8000b0a: 4b09 ldr r3, [pc, #36] @ (8000b30 <HAL_MspInit+0x4c>)
|
|
8000b0c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000b0e: 4a08 ldr r2, [pc, #32] @ (8000b30 <HAL_MspInit+0x4c>)
|
|
8000b10: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8000b14: 6413 str r3, [r2, #64] @ 0x40
|
|
8000b16: 4b06 ldr r3, [pc, #24] @ (8000b30 <HAL_MspInit+0x4c>)
|
|
8000b18: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000b1a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8000b1e: 603b str r3, [r7, #0]
|
|
8000b20: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8000b22: bf00 nop
|
|
8000b24: 370c adds r7, #12
|
|
8000b26: 46bd mov sp, r7
|
|
8000b28: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000b2c: 4770 bx lr
|
|
8000b2e: bf00 nop
|
|
8000b30: 40023800 .word 0x40023800
|
|
|
|
08000b34 <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
8000b34: b580 push {r7, lr}
|
|
8000b36: b08a sub sp, #40 @ 0x28
|
|
8000b38: af00 add r7, sp, #0
|
|
8000b3a: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000b3c: f107 0314 add.w r3, r7, #20
|
|
8000b40: 2200 movs r2, #0
|
|
8000b42: 601a str r2, [r3, #0]
|
|
8000b44: 605a str r2, [r3, #4]
|
|
8000b46: 609a str r2, [r3, #8]
|
|
8000b48: 60da str r2, [r3, #12]
|
|
8000b4a: 611a str r2, [r3, #16]
|
|
if(hi2c->Instance==I2C1)
|
|
8000b4c: 687b ldr r3, [r7, #4]
|
|
8000b4e: 681b ldr r3, [r3, #0]
|
|
8000b50: 4a19 ldr r2, [pc, #100] @ (8000bb8 <HAL_I2C_MspInit+0x84>)
|
|
8000b52: 4293 cmp r3, r2
|
|
8000b54: d12b bne.n 8000bae <HAL_I2C_MspInit+0x7a>
|
|
{
|
|
/* USER CODE BEGIN I2C1_MspInit 0 */
|
|
|
|
/* USER CODE END I2C1_MspInit 0 */
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000b56: 2300 movs r3, #0
|
|
8000b58: 613b str r3, [r7, #16]
|
|
8000b5a: 4b18 ldr r3, [pc, #96] @ (8000bbc <HAL_I2C_MspInit+0x88>)
|
|
8000b5c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b5e: 4a17 ldr r2, [pc, #92] @ (8000bbc <HAL_I2C_MspInit+0x88>)
|
|
8000b60: f043 0302 orr.w r3, r3, #2
|
|
8000b64: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b66: 4b15 ldr r3, [pc, #84] @ (8000bbc <HAL_I2C_MspInit+0x88>)
|
|
8000b68: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b6a: f003 0302 and.w r3, r3, #2
|
|
8000b6e: 613b str r3, [r7, #16]
|
|
8000b70: 693b ldr r3, [r7, #16]
|
|
/**I2C1 GPIO Configuration
|
|
PB6 ------> I2C1_SCL
|
|
PB7 ------> I2C1_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
8000b72: 23c0 movs r3, #192 @ 0xc0
|
|
8000b74: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
8000b76: 2312 movs r3, #18
|
|
8000b78: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000b7a: 2300 movs r3, #0
|
|
8000b7c: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8000b7e: 2303 movs r3, #3
|
|
8000b80: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
|
|
8000b82: 2304 movs r3, #4
|
|
8000b84: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8000b86: f107 0314 add.w r3, r7, #20
|
|
8000b8a: 4619 mov r1, r3
|
|
8000b8c: 480c ldr r0, [pc, #48] @ (8000bc0 <HAL_I2C_MspInit+0x8c>)
|
|
8000b8e: f000 fc13 bl 80013b8 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C1_CLK_ENABLE();
|
|
8000b92: 2300 movs r3, #0
|
|
8000b94: 60fb str r3, [r7, #12]
|
|
8000b96: 4b09 ldr r3, [pc, #36] @ (8000bbc <HAL_I2C_MspInit+0x88>)
|
|
8000b98: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000b9a: 4a08 ldr r2, [pc, #32] @ (8000bbc <HAL_I2C_MspInit+0x88>)
|
|
8000b9c: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8000ba0: 6413 str r3, [r2, #64] @ 0x40
|
|
8000ba2: 4b06 ldr r3, [pc, #24] @ (8000bbc <HAL_I2C_MspInit+0x88>)
|
|
8000ba4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000ba6: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8000baa: 60fb str r3, [r7, #12]
|
|
8000bac: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END I2C1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000bae: bf00 nop
|
|
8000bb0: 3728 adds r7, #40 @ 0x28
|
|
8000bb2: 46bd mov sp, r7
|
|
8000bb4: bd80 pop {r7, pc}
|
|
8000bb6: bf00 nop
|
|
8000bb8: 40005400 .word 0x40005400
|
|
8000bbc: 40023800 .word 0x40023800
|
|
8000bc0: 40020400 .word 0x40020400
|
|
|
|
08000bc4 <HAL_TIM_OC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_oc: TIM_OC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* htim_oc)
|
|
{
|
|
8000bc4: b480 push {r7}
|
|
8000bc6: b085 sub sp, #20
|
|
8000bc8: af00 add r7, sp, #0
|
|
8000bca: 6078 str r0, [r7, #4]
|
|
if(htim_oc->Instance==TIM2)
|
|
8000bcc: 687b ldr r3, [r7, #4]
|
|
8000bce: 681b ldr r3, [r3, #0]
|
|
8000bd0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8000bd4: d10d bne.n 8000bf2 <HAL_TIM_OC_MspInit+0x2e>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
|
8000bd6: 2300 movs r3, #0
|
|
8000bd8: 60fb str r3, [r7, #12]
|
|
8000bda: 4b09 ldr r3, [pc, #36] @ (8000c00 <HAL_TIM_OC_MspInit+0x3c>)
|
|
8000bdc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000bde: 4a08 ldr r2, [pc, #32] @ (8000c00 <HAL_TIM_OC_MspInit+0x3c>)
|
|
8000be0: f043 0301 orr.w r3, r3, #1
|
|
8000be4: 6413 str r3, [r2, #64] @ 0x40
|
|
8000be6: 4b06 ldr r3, [pc, #24] @ (8000c00 <HAL_TIM_OC_MspInit+0x3c>)
|
|
8000be8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000bea: f003 0301 and.w r3, r3, #1
|
|
8000bee: 60fb str r3, [r7, #12]
|
|
8000bf0: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END TIM2_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000bf2: bf00 nop
|
|
8000bf4: 3714 adds r7, #20
|
|
8000bf6: 46bd mov sp, r7
|
|
8000bf8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000bfc: 4770 bx lr
|
|
8000bfe: bf00 nop
|
|
8000c00: 40023800 .word 0x40023800
|
|
|
|
08000c04 <HAL_TIM_Encoder_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_encoder: TIM_Encoder handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
|
|
{
|
|
8000c04: b580 push {r7, lr}
|
|
8000c06: b08a sub sp, #40 @ 0x28
|
|
8000c08: af00 add r7, sp, #0
|
|
8000c0a: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000c0c: f107 0314 add.w r3, r7, #20
|
|
8000c10: 2200 movs r2, #0
|
|
8000c12: 601a str r2, [r3, #0]
|
|
8000c14: 605a str r2, [r3, #4]
|
|
8000c16: 609a str r2, [r3, #8]
|
|
8000c18: 60da str r2, [r3, #12]
|
|
8000c1a: 611a str r2, [r3, #16]
|
|
if(htim_encoder->Instance==TIM3)
|
|
8000c1c: 687b ldr r3, [r7, #4]
|
|
8000c1e: 681b ldr r3, [r3, #0]
|
|
8000c20: 4a19 ldr r2, [pc, #100] @ (8000c88 <HAL_TIM_Encoder_MspInit+0x84>)
|
|
8000c22: 4293 cmp r3, r2
|
|
8000c24: d12b bne.n 8000c7e <HAL_TIM_Encoder_MspInit+0x7a>
|
|
{
|
|
/* USER CODE BEGIN TIM3_MspInit 0 */
|
|
|
|
/* USER CODE END TIM3_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
8000c26: 2300 movs r3, #0
|
|
8000c28: 613b str r3, [r7, #16]
|
|
8000c2a: 4b18 ldr r3, [pc, #96] @ (8000c8c <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8000c2c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000c2e: 4a17 ldr r2, [pc, #92] @ (8000c8c <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8000c30: f043 0302 orr.w r3, r3, #2
|
|
8000c34: 6413 str r3, [r2, #64] @ 0x40
|
|
8000c36: 4b15 ldr r3, [pc, #84] @ (8000c8c <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8000c38: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000c3a: f003 0302 and.w r3, r3, #2
|
|
8000c3e: 613b str r3, [r7, #16]
|
|
8000c40: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000c42: 2300 movs r3, #0
|
|
8000c44: 60fb str r3, [r7, #12]
|
|
8000c46: 4b11 ldr r3, [pc, #68] @ (8000c8c <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8000c48: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000c4a: 4a10 ldr r2, [pc, #64] @ (8000c8c <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8000c4c: f043 0301 orr.w r3, r3, #1
|
|
8000c50: 6313 str r3, [r2, #48] @ 0x30
|
|
8000c52: 4b0e ldr r3, [pc, #56] @ (8000c8c <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8000c54: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000c56: f003 0301 and.w r3, r3, #1
|
|
8000c5a: 60fb str r3, [r7, #12]
|
|
8000c5c: 68fb ldr r3, [r7, #12]
|
|
/**TIM3 GPIO Configuration
|
|
PA6 ------> TIM3_CH1
|
|
PA7 ------> TIM3_CH2
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
8000c5e: 23c0 movs r3, #192 @ 0xc0
|
|
8000c60: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8000c62: 2302 movs r3, #2
|
|
8000c64: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c66: 2300 movs r3, #0
|
|
8000c68: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000c6a: 2300 movs r3, #0
|
|
8000c6c: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
|
|
8000c6e: 2302 movs r3, #2
|
|
8000c70: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000c72: f107 0314 add.w r3, r7, #20
|
|
8000c76: 4619 mov r1, r3
|
|
8000c78: 4805 ldr r0, [pc, #20] @ (8000c90 <HAL_TIM_Encoder_MspInit+0x8c>)
|
|
8000c7a: f000 fb9d bl 80013b8 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END TIM3_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000c7e: bf00 nop
|
|
8000c80: 3728 adds r7, #40 @ 0x28
|
|
8000c82: 46bd mov sp, r7
|
|
8000c84: bd80 pop {r7, pc}
|
|
8000c86: bf00 nop
|
|
8000c88: 40000400 .word 0x40000400
|
|
8000c8c: 40023800 .word 0x40023800
|
|
8000c90: 40020000 .word 0x40020000
|
|
|
|
08000c94 <HAL_TIM_MspPostInit>:
|
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
|
{
|
|
8000c94: b580 push {r7, lr}
|
|
8000c96: b088 sub sp, #32
|
|
8000c98: af00 add r7, sp, #0
|
|
8000c9a: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000c9c: f107 030c add.w r3, r7, #12
|
|
8000ca0: 2200 movs r2, #0
|
|
8000ca2: 601a str r2, [r3, #0]
|
|
8000ca4: 605a str r2, [r3, #4]
|
|
8000ca6: 609a str r2, [r3, #8]
|
|
8000ca8: 60da str r2, [r3, #12]
|
|
8000caa: 611a str r2, [r3, #16]
|
|
if(htim->Instance==TIM2)
|
|
8000cac: 687b ldr r3, [r7, #4]
|
|
8000cae: 681b ldr r3, [r3, #0]
|
|
8000cb0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8000cb4: d11d bne.n 8000cf2 <HAL_TIM_MspPostInit+0x5e>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 0 */
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000cb6: 2300 movs r3, #0
|
|
8000cb8: 60bb str r3, [r7, #8]
|
|
8000cba: 4b10 ldr r3, [pc, #64] @ (8000cfc <HAL_TIM_MspPostInit+0x68>)
|
|
8000cbc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000cbe: 4a0f ldr r2, [pc, #60] @ (8000cfc <HAL_TIM_MspPostInit+0x68>)
|
|
8000cc0: f043 0301 orr.w r3, r3, #1
|
|
8000cc4: 6313 str r3, [r2, #48] @ 0x30
|
|
8000cc6: 4b0d ldr r3, [pc, #52] @ (8000cfc <HAL_TIM_MspPostInit+0x68>)
|
|
8000cc8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000cca: f003 0301 and.w r3, r3, #1
|
|
8000cce: 60bb str r3, [r7, #8]
|
|
8000cd0: 68bb ldr r3, [r7, #8]
|
|
/**TIM2 GPIO Configuration
|
|
PA5 ------> TIM2_CH1
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_5;
|
|
8000cd2: 2320 movs r3, #32
|
|
8000cd4: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8000cd6: 2302 movs r3, #2
|
|
8000cd8: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000cda: 2300 movs r3, #0
|
|
8000cdc: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000cde: 2300 movs r3, #0
|
|
8000ce0: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
|
|
8000ce2: 2301 movs r3, #1
|
|
8000ce4: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000ce6: f107 030c add.w r3, r7, #12
|
|
8000cea: 4619 mov r1, r3
|
|
8000cec: 4804 ldr r0, [pc, #16] @ (8000d00 <HAL_TIM_MspPostInit+0x6c>)
|
|
8000cee: f000 fb63 bl 80013b8 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM2_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
8000cf2: bf00 nop
|
|
8000cf4: 3720 adds r7, #32
|
|
8000cf6: 46bd mov sp, r7
|
|
8000cf8: bd80 pop {r7, pc}
|
|
8000cfa: bf00 nop
|
|
8000cfc: 40023800 .word 0x40023800
|
|
8000d00: 40020000 .word 0x40020000
|
|
|
|
08000d04 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
8000d04: b580 push {r7, lr}
|
|
8000d06: b092 sub sp, #72 @ 0x48
|
|
8000d08: af00 add r7, sp, #0
|
|
8000d0a: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000d0c: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8000d10: 2200 movs r2, #0
|
|
8000d12: 601a str r2, [r3, #0]
|
|
8000d14: 605a str r2, [r3, #4]
|
|
8000d16: 609a str r2, [r3, #8]
|
|
8000d18: 60da str r2, [r3, #12]
|
|
8000d1a: 611a str r2, [r3, #16]
|
|
if(huart->Instance==UART4)
|
|
8000d1c: 687b ldr r3, [r7, #4]
|
|
8000d1e: 681b ldr r3, [r3, #0]
|
|
8000d20: 4a8d ldr r2, [pc, #564] @ (8000f58 <HAL_UART_MspInit+0x254>)
|
|
8000d22: 4293 cmp r3, r2
|
|
8000d24: d12c bne.n 8000d80 <HAL_UART_MspInit+0x7c>
|
|
{
|
|
/* USER CODE BEGIN UART4_MspInit 0 */
|
|
|
|
/* USER CODE END UART4_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_UART4_CLK_ENABLE();
|
|
8000d26: 2300 movs r3, #0
|
|
8000d28: 633b str r3, [r7, #48] @ 0x30
|
|
8000d2a: 4b8c ldr r3, [pc, #560] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000d2c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000d2e: 4a8b ldr r2, [pc, #556] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000d30: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8000d34: 6413 str r3, [r2, #64] @ 0x40
|
|
8000d36: 4b89 ldr r3, [pc, #548] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000d38: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000d3a: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8000d3e: 633b str r3, [r7, #48] @ 0x30
|
|
8000d40: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000d42: 2300 movs r3, #0
|
|
8000d44: 62fb str r3, [r7, #44] @ 0x2c
|
|
8000d46: 4b85 ldr r3, [pc, #532] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000d48: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000d4a: 4a84 ldr r2, [pc, #528] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000d4c: f043 0301 orr.w r3, r3, #1
|
|
8000d50: 6313 str r3, [r2, #48] @ 0x30
|
|
8000d52: 4b82 ldr r3, [pc, #520] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000d54: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000d56: f003 0301 and.w r3, r3, #1
|
|
8000d5a: 62fb str r3, [r7, #44] @ 0x2c
|
|
8000d5c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
/**UART4 GPIO Configuration
|
|
PA0-WKUP ------> UART4_TX
|
|
PA1 ------> UART4_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
|
|
8000d5e: 2303 movs r3, #3
|
|
8000d60: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8000d62: 2302 movs r3, #2
|
|
8000d64: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000d66: 2300 movs r3, #0
|
|
8000d68: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8000d6a: 2303 movs r3, #3
|
|
8000d6c: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
|
|
8000d6e: 2308 movs r3, #8
|
|
8000d70: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000d72: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8000d76: 4619 mov r1, r3
|
|
8000d78: 4879 ldr r0, [pc, #484] @ (8000f60 <HAL_UART_MspInit+0x25c>)
|
|
8000d7a: f000 fb1d bl 80013b8 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN USART3_MspInit 1 */
|
|
|
|
/* USER CODE END USART3_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8000d7e: e0e7 b.n 8000f50 <HAL_UART_MspInit+0x24c>
|
|
else if(huart->Instance==UART5)
|
|
8000d80: 687b ldr r3, [r7, #4]
|
|
8000d82: 681b ldr r3, [r3, #0]
|
|
8000d84: 4a77 ldr r2, [pc, #476] @ (8000f64 <HAL_UART_MspInit+0x260>)
|
|
8000d86: 4293 cmp r3, r2
|
|
8000d88: d14b bne.n 8000e22 <HAL_UART_MspInit+0x11e>
|
|
__HAL_RCC_UART5_CLK_ENABLE();
|
|
8000d8a: 2300 movs r3, #0
|
|
8000d8c: 62bb str r3, [r7, #40] @ 0x28
|
|
8000d8e: 4b73 ldr r3, [pc, #460] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000d90: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000d92: 4a72 ldr r2, [pc, #456] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000d94: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8000d98: 6413 str r3, [r2, #64] @ 0x40
|
|
8000d9a: 4b70 ldr r3, [pc, #448] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000d9c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000d9e: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8000da2: 62bb str r3, [r7, #40] @ 0x28
|
|
8000da4: 6abb ldr r3, [r7, #40] @ 0x28
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8000da6: 2300 movs r3, #0
|
|
8000da8: 627b str r3, [r7, #36] @ 0x24
|
|
8000daa: 4b6c ldr r3, [pc, #432] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000dac: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000dae: 4a6b ldr r2, [pc, #428] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000db0: f043 0304 orr.w r3, r3, #4
|
|
8000db4: 6313 str r3, [r2, #48] @ 0x30
|
|
8000db6: 4b69 ldr r3, [pc, #420] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000db8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000dba: f003 0304 and.w r3, r3, #4
|
|
8000dbe: 627b str r3, [r7, #36] @ 0x24
|
|
8000dc0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8000dc2: 2300 movs r3, #0
|
|
8000dc4: 623b str r3, [r7, #32]
|
|
8000dc6: 4b65 ldr r3, [pc, #404] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000dc8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000dca: 4a64 ldr r2, [pc, #400] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000dcc: f043 0308 orr.w r3, r3, #8
|
|
8000dd0: 6313 str r3, [r2, #48] @ 0x30
|
|
8000dd2: 4b62 ldr r3, [pc, #392] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000dd4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000dd6: f003 0308 and.w r3, r3, #8
|
|
8000dda: 623b str r3, [r7, #32]
|
|
8000ddc: 6a3b ldr r3, [r7, #32]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_12;
|
|
8000dde: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8000de2: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8000de4: 2302 movs r3, #2
|
|
8000de6: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000de8: 2300 movs r3, #0
|
|
8000dea: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8000dec: 2303 movs r3, #3
|
|
8000dee: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
|
|
8000df0: 2308 movs r3, #8
|
|
8000df2: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8000df4: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8000df8: 4619 mov r1, r3
|
|
8000dfa: 485b ldr r0, [pc, #364] @ (8000f68 <HAL_UART_MspInit+0x264>)
|
|
8000dfc: f000 fadc bl 80013b8 <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
8000e00: 2304 movs r3, #4
|
|
8000e02: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8000e04: 2302 movs r3, #2
|
|
8000e06: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000e08: 2300 movs r3, #0
|
|
8000e0a: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8000e0c: 2303 movs r3, #3
|
|
8000e0e: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
|
|
8000e10: 2308 movs r3, #8
|
|
8000e12: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8000e14: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8000e18: 4619 mov r1, r3
|
|
8000e1a: 4854 ldr r0, [pc, #336] @ (8000f6c <HAL_UART_MspInit+0x268>)
|
|
8000e1c: f000 facc bl 80013b8 <HAL_GPIO_Init>
|
|
}
|
|
8000e20: e096 b.n 8000f50 <HAL_UART_MspInit+0x24c>
|
|
else if(huart->Instance==USART1)
|
|
8000e22: 687b ldr r3, [r7, #4]
|
|
8000e24: 681b ldr r3, [r3, #0]
|
|
8000e26: 4a52 ldr r2, [pc, #328] @ (8000f70 <HAL_UART_MspInit+0x26c>)
|
|
8000e28: 4293 cmp r3, r2
|
|
8000e2a: d12d bne.n 8000e88 <HAL_UART_MspInit+0x184>
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8000e2c: 2300 movs r3, #0
|
|
8000e2e: 61fb str r3, [r7, #28]
|
|
8000e30: 4b4a ldr r3, [pc, #296] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000e32: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000e34: 4a49 ldr r2, [pc, #292] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000e36: f043 0310 orr.w r3, r3, #16
|
|
8000e3a: 6453 str r3, [r2, #68] @ 0x44
|
|
8000e3c: 4b47 ldr r3, [pc, #284] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000e3e: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000e40: f003 0310 and.w r3, r3, #16
|
|
8000e44: 61fb str r3, [r7, #28]
|
|
8000e46: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000e48: 2300 movs r3, #0
|
|
8000e4a: 61bb str r3, [r7, #24]
|
|
8000e4c: 4b43 ldr r3, [pc, #268] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000e4e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000e50: 4a42 ldr r2, [pc, #264] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000e52: f043 0301 orr.w r3, r3, #1
|
|
8000e56: 6313 str r3, [r2, #48] @ 0x30
|
|
8000e58: 4b40 ldr r3, [pc, #256] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000e5a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000e5c: f003 0301 and.w r3, r3, #1
|
|
8000e60: 61bb str r3, [r7, #24]
|
|
8000e62: 69bb ldr r3, [r7, #24]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
|
|
8000e64: f44f 63c0 mov.w r3, #1536 @ 0x600
|
|
8000e68: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8000e6a: 2302 movs r3, #2
|
|
8000e6c: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000e6e: 2300 movs r3, #0
|
|
8000e70: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8000e72: 2303 movs r3, #3
|
|
8000e74: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
8000e76: 2307 movs r3, #7
|
|
8000e78: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000e7a: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8000e7e: 4619 mov r1, r3
|
|
8000e80: 4837 ldr r0, [pc, #220] @ (8000f60 <HAL_UART_MspInit+0x25c>)
|
|
8000e82: f000 fa99 bl 80013b8 <HAL_GPIO_Init>
|
|
}
|
|
8000e86: e063 b.n 8000f50 <HAL_UART_MspInit+0x24c>
|
|
else if(huart->Instance==USART2)
|
|
8000e88: 687b ldr r3, [r7, #4]
|
|
8000e8a: 681b ldr r3, [r3, #0]
|
|
8000e8c: 4a39 ldr r2, [pc, #228] @ (8000f74 <HAL_UART_MspInit+0x270>)
|
|
8000e8e: 4293 cmp r3, r2
|
|
8000e90: d12c bne.n 8000eec <HAL_UART_MspInit+0x1e8>
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
8000e92: 2300 movs r3, #0
|
|
8000e94: 617b str r3, [r7, #20]
|
|
8000e96: 4b31 ldr r3, [pc, #196] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000e98: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000e9a: 4a30 ldr r2, [pc, #192] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000e9c: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8000ea0: 6413 str r3, [r2, #64] @ 0x40
|
|
8000ea2: 4b2e ldr r3, [pc, #184] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000ea4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000ea6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8000eaa: 617b str r3, [r7, #20]
|
|
8000eac: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000eae: 2300 movs r3, #0
|
|
8000eb0: 613b str r3, [r7, #16]
|
|
8000eb2: 4b2a ldr r3, [pc, #168] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000eb4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000eb6: 4a29 ldr r2, [pc, #164] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000eb8: f043 0301 orr.w r3, r3, #1
|
|
8000ebc: 6313 str r3, [r2, #48] @ 0x30
|
|
8000ebe: 4b27 ldr r3, [pc, #156] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000ec0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000ec2: f003 0301 and.w r3, r3, #1
|
|
8000ec6: 613b str r3, [r7, #16]
|
|
8000ec8: 693b ldr r3, [r7, #16]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
|
|
8000eca: 230c movs r3, #12
|
|
8000ecc: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8000ece: 2302 movs r3, #2
|
|
8000ed0: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000ed2: 2300 movs r3, #0
|
|
8000ed4: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8000ed6: 2303 movs r3, #3
|
|
8000ed8: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
|
8000eda: 2307 movs r3, #7
|
|
8000edc: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000ede: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8000ee2: 4619 mov r1, r3
|
|
8000ee4: 481e ldr r0, [pc, #120] @ (8000f60 <HAL_UART_MspInit+0x25c>)
|
|
8000ee6: f000 fa67 bl 80013b8 <HAL_GPIO_Init>
|
|
}
|
|
8000eea: e031 b.n 8000f50 <HAL_UART_MspInit+0x24c>
|
|
else if(huart->Instance==USART3)
|
|
8000eec: 687b ldr r3, [r7, #4]
|
|
8000eee: 681b ldr r3, [r3, #0]
|
|
8000ef0: 4a21 ldr r2, [pc, #132] @ (8000f78 <HAL_UART_MspInit+0x274>)
|
|
8000ef2: 4293 cmp r3, r2
|
|
8000ef4: d12c bne.n 8000f50 <HAL_UART_MspInit+0x24c>
|
|
__HAL_RCC_USART3_CLK_ENABLE();
|
|
8000ef6: 2300 movs r3, #0
|
|
8000ef8: 60fb str r3, [r7, #12]
|
|
8000efa: 4b18 ldr r3, [pc, #96] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000efc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000efe: 4a17 ldr r2, [pc, #92] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000f00: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8000f04: 6413 str r3, [r2, #64] @ 0x40
|
|
8000f06: 4b15 ldr r3, [pc, #84] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000f08: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000f0a: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8000f0e: 60fb str r3, [r7, #12]
|
|
8000f10: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8000f12: 2300 movs r3, #0
|
|
8000f14: 60bb str r3, [r7, #8]
|
|
8000f16: 4b11 ldr r3, [pc, #68] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000f18: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f1a: 4a10 ldr r2, [pc, #64] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000f1c: f043 0304 orr.w r3, r3, #4
|
|
8000f20: 6313 str r3, [r2, #48] @ 0x30
|
|
8000f22: 4b0e ldr r3, [pc, #56] @ (8000f5c <HAL_UART_MspInit+0x258>)
|
|
8000f24: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f26: f003 0304 and.w r3, r3, #4
|
|
8000f2a: 60bb str r3, [r7, #8]
|
|
8000f2c: 68bb ldr r3, [r7, #8]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
|
|
8000f2e: f44f 6340 mov.w r3, #3072 @ 0xc00
|
|
8000f32: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8000f34: 2302 movs r3, #2
|
|
8000f36: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000f38: 2300 movs r3, #0
|
|
8000f3a: 63fb str r3, [r7, #60] @ 0x3c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8000f3c: 2303 movs r3, #3
|
|
8000f3e: 643b str r3, [r7, #64] @ 0x40
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
|
|
8000f40: 2307 movs r3, #7
|
|
8000f42: 647b str r3, [r7, #68] @ 0x44
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8000f44: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8000f48: 4619 mov r1, r3
|
|
8000f4a: 4807 ldr r0, [pc, #28] @ (8000f68 <HAL_UART_MspInit+0x264>)
|
|
8000f4c: f000 fa34 bl 80013b8 <HAL_GPIO_Init>
|
|
}
|
|
8000f50: bf00 nop
|
|
8000f52: 3748 adds r7, #72 @ 0x48
|
|
8000f54: 46bd mov sp, r7
|
|
8000f56: bd80 pop {r7, pc}
|
|
8000f58: 40004c00 .word 0x40004c00
|
|
8000f5c: 40023800 .word 0x40023800
|
|
8000f60: 40020000 .word 0x40020000
|
|
8000f64: 40005000 .word 0x40005000
|
|
8000f68: 40020800 .word 0x40020800
|
|
8000f6c: 40020c00 .word 0x40020c00
|
|
8000f70: 40011000 .word 0x40011000
|
|
8000f74: 40004400 .word 0x40004400
|
|
8000f78: 40004800 .word 0x40004800
|
|
|
|
08000f7c <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8000f7c: b480 push {r7}
|
|
8000f7e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8000f80: bf00 nop
|
|
8000f82: e7fd b.n 8000f80 <NMI_Handler+0x4>
|
|
|
|
08000f84 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8000f84: b480 push {r7}
|
|
8000f86: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8000f88: bf00 nop
|
|
8000f8a: e7fd b.n 8000f88 <HardFault_Handler+0x4>
|
|
|
|
08000f8c <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8000f8c: b480 push {r7}
|
|
8000f8e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8000f90: bf00 nop
|
|
8000f92: e7fd b.n 8000f90 <MemManage_Handler+0x4>
|
|
|
|
08000f94 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pre-fetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8000f94: b480 push {r7}
|
|
8000f96: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8000f98: bf00 nop
|
|
8000f9a: e7fd b.n 8000f98 <BusFault_Handler+0x4>
|
|
|
|
08000f9c <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8000f9c: b480 push {r7}
|
|
8000f9e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8000fa0: bf00 nop
|
|
8000fa2: e7fd b.n 8000fa0 <UsageFault_Handler+0x4>
|
|
|
|
08000fa4 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8000fa4: b480 push {r7}
|
|
8000fa6: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8000fa8: bf00 nop
|
|
8000faa: 46bd mov sp, r7
|
|
8000fac: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000fb0: 4770 bx lr
|
|
|
|
08000fb2 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8000fb2: b480 push {r7}
|
|
8000fb4: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8000fb6: bf00 nop
|
|
8000fb8: 46bd mov sp, r7
|
|
8000fba: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000fbe: 4770 bx lr
|
|
|
|
08000fc0 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8000fc0: b480 push {r7}
|
|
8000fc2: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8000fc4: bf00 nop
|
|
8000fc6: 46bd mov sp, r7
|
|
8000fc8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000fcc: 4770 bx lr
|
|
|
|
08000fce <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8000fce: b580 push {r7, lr}
|
|
8000fd0: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
8000fd2: f000 f89b bl 800110c <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8000fd6: bf00 nop
|
|
8000fd8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08000fdc <OTG_FS_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USB On The Go FS global interrupt.
|
|
*/
|
|
void OTG_FS_IRQHandler(void)
|
|
{
|
|
8000fdc: b580 push {r7, lr}
|
|
8000fde: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN OTG_FS_IRQn 0 */
|
|
|
|
/* USER CODE END OTG_FS_IRQn 0 */
|
|
HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
|
|
8000fe0: 4802 ldr r0, [pc, #8] @ (8000fec <OTG_FS_IRQHandler+0x10>)
|
|
8000fe2: f000 fe26 bl 8001c32 <HAL_PCD_IRQHandler>
|
|
/* USER CODE BEGIN OTG_FS_IRQn 1 */
|
|
|
|
/* USER CODE END OTG_FS_IRQn 1 */
|
|
}
|
|
8000fe6: bf00 nop
|
|
8000fe8: bd80 pop {r7, pc}
|
|
8000fea: bf00 nop
|
|
8000fec: 20000878 .word 0x20000878
|
|
|
|
08000ff0 <SystemInit>:
|
|
* configuration.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
8000ff0: b480 push {r7}
|
|
8000ff2: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
8000ff4: 4b06 ldr r3, [pc, #24] @ (8001010 <SystemInit+0x20>)
|
|
8000ff6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8000ffa: 4a05 ldr r2, [pc, #20] @ (8001010 <SystemInit+0x20>)
|
|
8000ffc: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
8001000: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
8001004: bf00 nop
|
|
8001006: 46bd mov sp, r7
|
|
8001008: f85d 7b04 ldr.w r7, [sp], #4
|
|
800100c: 4770 bx lr
|
|
800100e: bf00 nop
|
|
8001010: e000ed00 .word 0xe000ed00
|
|
|
|
08001014 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* set stack pointer */
|
|
8001014: f8df d034 ldr.w sp, [pc, #52] @ 800104c <LoopFillZerobss+0xe>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8001018: f7ff ffea bl 8000ff0 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
800101c: 480c ldr r0, [pc, #48] @ (8001050 <LoopFillZerobss+0x12>)
|
|
ldr r1, =_edata
|
|
800101e: 490d ldr r1, [pc, #52] @ (8001054 <LoopFillZerobss+0x16>)
|
|
ldr r2, =_sidata
|
|
8001020: 4a0d ldr r2, [pc, #52] @ (8001058 <LoopFillZerobss+0x1a>)
|
|
movs r3, #0
|
|
8001022: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
8001024: e002 b.n 800102c <LoopCopyDataInit>
|
|
|
|
08001026 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
8001026: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8001028: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
800102a: 3304 adds r3, #4
|
|
|
|
0800102c <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
800102c: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
800102e: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8001030: d3f9 bcc.n 8001026 <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
8001032: 4a0a ldr r2, [pc, #40] @ (800105c <LoopFillZerobss+0x1e>)
|
|
ldr r4, =_ebss
|
|
8001034: 4c0a ldr r4, [pc, #40] @ (8001060 <LoopFillZerobss+0x22>)
|
|
movs r3, #0
|
|
8001036: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8001038: e001 b.n 800103e <LoopFillZerobss>
|
|
|
|
0800103a <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
800103a: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
800103c: 3204 adds r2, #4
|
|
|
|
0800103e <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
800103e: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8001040: d3fb bcc.n 800103a <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8001042: f007 fc7b bl 800893c <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
8001046: f7ff fa73 bl 8000530 <main>
|
|
bx lr
|
|
800104a: 4770 bx lr
|
|
ldr sp, =_estack /* set stack pointer */
|
|
800104c: 20020000 .word 0x20020000
|
|
ldr r0, =_sdata
|
|
8001050: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
8001054: 2000012c .word 0x2000012c
|
|
ldr r2, =_sidata
|
|
8001058: 08008a00 .word 0x08008a00
|
|
ldr r2, =_sbss
|
|
800105c: 2000012c .word 0x2000012c
|
|
ldr r4, =_ebss
|
|
8001060: 20000d70 .word 0x20000d70
|
|
|
|
08001064 <ADC_IRQHandler>:
|
|
* @retval None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8001064: e7fe b.n 8001064 <ADC_IRQHandler>
|
|
...
|
|
|
|
08001068 <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8001068: b580 push {r7, lr}
|
|
800106a: af00 add r7, sp, #0
|
|
/* Configure Flash prefetch, Instruction cache, Data cache */
|
|
#if (INSTRUCTION_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
|
|
800106c: 4b0e ldr r3, [pc, #56] @ (80010a8 <HAL_Init+0x40>)
|
|
800106e: 681b ldr r3, [r3, #0]
|
|
8001070: 4a0d ldr r2, [pc, #52] @ (80010a8 <HAL_Init+0x40>)
|
|
8001072: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8001076: 6013 str r3, [r2, #0]
|
|
#endif /* INSTRUCTION_CACHE_ENABLE */
|
|
|
|
#if (DATA_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_DATA_CACHE_ENABLE();
|
|
8001078: 4b0b ldr r3, [pc, #44] @ (80010a8 <HAL_Init+0x40>)
|
|
800107a: 681b ldr r3, [r3, #0]
|
|
800107c: 4a0a ldr r2, [pc, #40] @ (80010a8 <HAL_Init+0x40>)
|
|
800107e: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8001082: 6013 str r3, [r2, #0]
|
|
#endif /* DATA_CACHE_ENABLE */
|
|
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
8001084: 4b08 ldr r3, [pc, #32] @ (80010a8 <HAL_Init+0x40>)
|
|
8001086: 681b ldr r3, [r3, #0]
|
|
8001088: 4a07 ldr r2, [pc, #28] @ (80010a8 <HAL_Init+0x40>)
|
|
800108a: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
800108e: 6013 str r3, [r2, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8001090: 2003 movs r0, #3
|
|
8001092: f000 f94f bl 8001334 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
8001096: 200f movs r0, #15
|
|
8001098: f000 f808 bl 80010ac <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
800109c: f7ff fd22 bl 8000ae4 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80010a0: 2300 movs r3, #0
|
|
}
|
|
80010a2: 4618 mov r0, r3
|
|
80010a4: bd80 pop {r7, pc}
|
|
80010a6: bf00 nop
|
|
80010a8: 40023c00 .word 0x40023c00
|
|
|
|
080010ac <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
80010ac: b580 push {r7, lr}
|
|
80010ae: b082 sub sp, #8
|
|
80010b0: af00 add r7, sp, #0
|
|
80010b2: 6078 str r0, [r7, #4]
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
80010b4: 4b12 ldr r3, [pc, #72] @ (8001100 <HAL_InitTick+0x54>)
|
|
80010b6: 681a ldr r2, [r3, #0]
|
|
80010b8: 4b12 ldr r3, [pc, #72] @ (8001104 <HAL_InitTick+0x58>)
|
|
80010ba: 781b ldrb r3, [r3, #0]
|
|
80010bc: 4619 mov r1, r3
|
|
80010be: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
80010c2: fbb3 f3f1 udiv r3, r3, r1
|
|
80010c6: fbb2 f3f3 udiv r3, r2, r3
|
|
80010ca: 4618 mov r0, r3
|
|
80010cc: f000 f967 bl 800139e <HAL_SYSTICK_Config>
|
|
80010d0: 4603 mov r3, r0
|
|
80010d2: 2b00 cmp r3, #0
|
|
80010d4: d001 beq.n 80010da <HAL_InitTick+0x2e>
|
|
{
|
|
return HAL_ERROR;
|
|
80010d6: 2301 movs r3, #1
|
|
80010d8: e00e b.n 80010f8 <HAL_InitTick+0x4c>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
80010da: 687b ldr r3, [r7, #4]
|
|
80010dc: 2b0f cmp r3, #15
|
|
80010de: d80a bhi.n 80010f6 <HAL_InitTick+0x4a>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
80010e0: 2200 movs r2, #0
|
|
80010e2: 6879 ldr r1, [r7, #4]
|
|
80010e4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80010e8: f000 f92f bl 800134a <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
80010ec: 4a06 ldr r2, [pc, #24] @ (8001108 <HAL_InitTick+0x5c>)
|
|
80010ee: 687b ldr r3, [r7, #4]
|
|
80010f0: 6013 str r3, [r2, #0]
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80010f2: 2300 movs r3, #0
|
|
80010f4: e000 b.n 80010f8 <HAL_InitTick+0x4c>
|
|
return HAL_ERROR;
|
|
80010f6: 2301 movs r3, #1
|
|
}
|
|
80010f8: 4618 mov r0, r3
|
|
80010fa: 3708 adds r7, #8
|
|
80010fc: 46bd mov sp, r7
|
|
80010fe: bd80 pop {r7, pc}
|
|
8001100: 20000000 .word 0x20000000
|
|
8001104: 20000008 .word 0x20000008
|
|
8001108: 20000004 .word 0x20000004
|
|
|
|
0800110c <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
800110c: b480 push {r7}
|
|
800110e: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
8001110: 4b06 ldr r3, [pc, #24] @ (800112c <HAL_IncTick+0x20>)
|
|
8001112: 781b ldrb r3, [r3, #0]
|
|
8001114: 461a mov r2, r3
|
|
8001116: 4b06 ldr r3, [pc, #24] @ (8001130 <HAL_IncTick+0x24>)
|
|
8001118: 681b ldr r3, [r3, #0]
|
|
800111a: 4413 add r3, r2
|
|
800111c: 4a04 ldr r2, [pc, #16] @ (8001130 <HAL_IncTick+0x24>)
|
|
800111e: 6013 str r3, [r2, #0]
|
|
}
|
|
8001120: bf00 nop
|
|
8001122: 46bd mov sp, r7
|
|
8001124: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001128: 4770 bx lr
|
|
800112a: bf00 nop
|
|
800112c: 20000008 .word 0x20000008
|
|
8001130: 20000394 .word 0x20000394
|
|
|
|
08001134 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8001134: b480 push {r7}
|
|
8001136: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8001138: 4b03 ldr r3, [pc, #12] @ (8001148 <HAL_GetTick+0x14>)
|
|
800113a: 681b ldr r3, [r3, #0]
|
|
}
|
|
800113c: 4618 mov r0, r3
|
|
800113e: 46bd mov sp, r7
|
|
8001140: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001144: 4770 bx lr
|
|
8001146: bf00 nop
|
|
8001148: 20000394 .word 0x20000394
|
|
|
|
0800114c <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
800114c: b580 push {r7, lr}
|
|
800114e: b084 sub sp, #16
|
|
8001150: af00 add r7, sp, #0
|
|
8001152: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8001154: f7ff ffee bl 8001134 <HAL_GetTick>
|
|
8001158: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
800115a: 687b ldr r3, [r7, #4]
|
|
800115c: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
800115e: 68fb ldr r3, [r7, #12]
|
|
8001160: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8001164: d005 beq.n 8001172 <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
8001166: 4b0a ldr r3, [pc, #40] @ (8001190 <HAL_Delay+0x44>)
|
|
8001168: 781b ldrb r3, [r3, #0]
|
|
800116a: 461a mov r2, r3
|
|
800116c: 68fb ldr r3, [r7, #12]
|
|
800116e: 4413 add r3, r2
|
|
8001170: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while((HAL_GetTick() - tickstart) < wait)
|
|
8001172: bf00 nop
|
|
8001174: f7ff ffde bl 8001134 <HAL_GetTick>
|
|
8001178: 4602 mov r2, r0
|
|
800117a: 68bb ldr r3, [r7, #8]
|
|
800117c: 1ad3 subs r3, r2, r3
|
|
800117e: 68fa ldr r2, [r7, #12]
|
|
8001180: 429a cmp r2, r3
|
|
8001182: d8f7 bhi.n 8001174 <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
8001184: bf00 nop
|
|
8001186: bf00 nop
|
|
8001188: 3710 adds r7, #16
|
|
800118a: 46bd mov sp, r7
|
|
800118c: bd80 pop {r7, pc}
|
|
800118e: bf00 nop
|
|
8001190: 20000008 .word 0x20000008
|
|
|
|
08001194 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001194: b480 push {r7}
|
|
8001196: b085 sub sp, #20
|
|
8001198: af00 add r7, sp, #0
|
|
800119a: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
800119c: 687b ldr r3, [r7, #4]
|
|
800119e: f003 0307 and.w r3, r3, #7
|
|
80011a2: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
80011a4: 4b0c ldr r3, [pc, #48] @ (80011d8 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80011a6: 68db ldr r3, [r3, #12]
|
|
80011a8: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
80011aa: 68ba ldr r2, [r7, #8]
|
|
80011ac: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
80011b0: 4013 ands r3, r2
|
|
80011b2: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80011b4: 68fb ldr r3, [r7, #12]
|
|
80011b6: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80011b8: 68bb ldr r3, [r7, #8]
|
|
80011ba: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80011bc: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80011c0: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80011c4: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80011c6: 4a04 ldr r2, [pc, #16] @ (80011d8 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80011c8: 68bb ldr r3, [r7, #8]
|
|
80011ca: 60d3 str r3, [r2, #12]
|
|
}
|
|
80011cc: bf00 nop
|
|
80011ce: 3714 adds r7, #20
|
|
80011d0: 46bd mov sp, r7
|
|
80011d2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80011d6: 4770 bx lr
|
|
80011d8: e000ed00 .word 0xe000ed00
|
|
|
|
080011dc <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
80011dc: b480 push {r7}
|
|
80011de: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
80011e0: 4b04 ldr r3, [pc, #16] @ (80011f4 <__NVIC_GetPriorityGrouping+0x18>)
|
|
80011e2: 68db ldr r3, [r3, #12]
|
|
80011e4: 0a1b lsrs r3, r3, #8
|
|
80011e6: f003 0307 and.w r3, r3, #7
|
|
}
|
|
80011ea: 4618 mov r0, r3
|
|
80011ec: 46bd mov sp, r7
|
|
80011ee: f85d 7b04 ldr.w r7, [sp], #4
|
|
80011f2: 4770 bx lr
|
|
80011f4: e000ed00 .word 0xe000ed00
|
|
|
|
080011f8 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
80011f8: b480 push {r7}
|
|
80011fa: b083 sub sp, #12
|
|
80011fc: af00 add r7, sp, #0
|
|
80011fe: 4603 mov r3, r0
|
|
8001200: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001202: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001206: 2b00 cmp r3, #0
|
|
8001208: db0b blt.n 8001222 <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
800120a: 79fb ldrb r3, [r7, #7]
|
|
800120c: f003 021f and.w r2, r3, #31
|
|
8001210: 4907 ldr r1, [pc, #28] @ (8001230 <__NVIC_EnableIRQ+0x38>)
|
|
8001212: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001216: 095b lsrs r3, r3, #5
|
|
8001218: 2001 movs r0, #1
|
|
800121a: fa00 f202 lsl.w r2, r0, r2
|
|
800121e: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
8001222: bf00 nop
|
|
8001224: 370c adds r7, #12
|
|
8001226: 46bd mov sp, r7
|
|
8001228: f85d 7b04 ldr.w r7, [sp], #4
|
|
800122c: 4770 bx lr
|
|
800122e: bf00 nop
|
|
8001230: e000e100 .word 0xe000e100
|
|
|
|
08001234 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8001234: b480 push {r7}
|
|
8001236: b083 sub sp, #12
|
|
8001238: af00 add r7, sp, #0
|
|
800123a: 4603 mov r3, r0
|
|
800123c: 6039 str r1, [r7, #0]
|
|
800123e: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001240: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001244: 2b00 cmp r3, #0
|
|
8001246: db0a blt.n 800125e <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001248: 683b ldr r3, [r7, #0]
|
|
800124a: b2da uxtb r2, r3
|
|
800124c: 490c ldr r1, [pc, #48] @ (8001280 <__NVIC_SetPriority+0x4c>)
|
|
800124e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001252: 0112 lsls r2, r2, #4
|
|
8001254: b2d2 uxtb r2, r2
|
|
8001256: 440b add r3, r1
|
|
8001258: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
800125c: e00a b.n 8001274 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
800125e: 683b ldr r3, [r7, #0]
|
|
8001260: b2da uxtb r2, r3
|
|
8001262: 4908 ldr r1, [pc, #32] @ (8001284 <__NVIC_SetPriority+0x50>)
|
|
8001264: 79fb ldrb r3, [r7, #7]
|
|
8001266: f003 030f and.w r3, r3, #15
|
|
800126a: 3b04 subs r3, #4
|
|
800126c: 0112 lsls r2, r2, #4
|
|
800126e: b2d2 uxtb r2, r2
|
|
8001270: 440b add r3, r1
|
|
8001272: 761a strb r2, [r3, #24]
|
|
}
|
|
8001274: bf00 nop
|
|
8001276: 370c adds r7, #12
|
|
8001278: 46bd mov sp, r7
|
|
800127a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800127e: 4770 bx lr
|
|
8001280: e000e100 .word 0xe000e100
|
|
8001284: e000ed00 .word 0xe000ed00
|
|
|
|
08001288 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001288: b480 push {r7}
|
|
800128a: b089 sub sp, #36 @ 0x24
|
|
800128c: af00 add r7, sp, #0
|
|
800128e: 60f8 str r0, [r7, #12]
|
|
8001290: 60b9 str r1, [r7, #8]
|
|
8001292: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8001294: 68fb ldr r3, [r7, #12]
|
|
8001296: f003 0307 and.w r3, r3, #7
|
|
800129a: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
800129c: 69fb ldr r3, [r7, #28]
|
|
800129e: f1c3 0307 rsb r3, r3, #7
|
|
80012a2: 2b04 cmp r3, #4
|
|
80012a4: bf28 it cs
|
|
80012a6: 2304 movcs r3, #4
|
|
80012a8: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
80012aa: 69fb ldr r3, [r7, #28]
|
|
80012ac: 3304 adds r3, #4
|
|
80012ae: 2b06 cmp r3, #6
|
|
80012b0: d902 bls.n 80012b8 <NVIC_EncodePriority+0x30>
|
|
80012b2: 69fb ldr r3, [r7, #28]
|
|
80012b4: 3b03 subs r3, #3
|
|
80012b6: e000 b.n 80012ba <NVIC_EncodePriority+0x32>
|
|
80012b8: 2300 movs r3, #0
|
|
80012ba: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80012bc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80012c0: 69bb ldr r3, [r7, #24]
|
|
80012c2: fa02 f303 lsl.w r3, r2, r3
|
|
80012c6: 43da mvns r2, r3
|
|
80012c8: 68bb ldr r3, [r7, #8]
|
|
80012ca: 401a ands r2, r3
|
|
80012cc: 697b ldr r3, [r7, #20]
|
|
80012ce: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80012d0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
80012d4: 697b ldr r3, [r7, #20]
|
|
80012d6: fa01 f303 lsl.w r3, r1, r3
|
|
80012da: 43d9 mvns r1, r3
|
|
80012dc: 687b ldr r3, [r7, #4]
|
|
80012de: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80012e0: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
80012e2: 4618 mov r0, r3
|
|
80012e4: 3724 adds r7, #36 @ 0x24
|
|
80012e6: 46bd mov sp, r7
|
|
80012e8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80012ec: 4770 bx lr
|
|
...
|
|
|
|
080012f0 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
80012f0: b580 push {r7, lr}
|
|
80012f2: b082 sub sp, #8
|
|
80012f4: af00 add r7, sp, #0
|
|
80012f6: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
80012f8: 687b ldr r3, [r7, #4]
|
|
80012fa: 3b01 subs r3, #1
|
|
80012fc: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8001300: d301 bcc.n 8001306 <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
8001302: 2301 movs r3, #1
|
|
8001304: e00f b.n 8001326 <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8001306: 4a0a ldr r2, [pc, #40] @ (8001330 <SysTick_Config+0x40>)
|
|
8001308: 687b ldr r3, [r7, #4]
|
|
800130a: 3b01 subs r3, #1
|
|
800130c: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
800130e: 210f movs r1, #15
|
|
8001310: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8001314: f7ff ff8e bl 8001234 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8001318: 4b05 ldr r3, [pc, #20] @ (8001330 <SysTick_Config+0x40>)
|
|
800131a: 2200 movs r2, #0
|
|
800131c: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
800131e: 4b04 ldr r3, [pc, #16] @ (8001330 <SysTick_Config+0x40>)
|
|
8001320: 2207 movs r2, #7
|
|
8001322: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8001324: 2300 movs r3, #0
|
|
}
|
|
8001326: 4618 mov r0, r3
|
|
8001328: 3708 adds r7, #8
|
|
800132a: 46bd mov sp, r7
|
|
800132c: bd80 pop {r7, pc}
|
|
800132e: bf00 nop
|
|
8001330: e000e010 .word 0xe000e010
|
|
|
|
08001334 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001334: b580 push {r7, lr}
|
|
8001336: b082 sub sp, #8
|
|
8001338: af00 add r7, sp, #0
|
|
800133a: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
800133c: 6878 ldr r0, [r7, #4]
|
|
800133e: f7ff ff29 bl 8001194 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8001342: bf00 nop
|
|
8001344: 3708 adds r7, #8
|
|
8001346: 46bd mov sp, r7
|
|
8001348: bd80 pop {r7, pc}
|
|
|
|
0800134a <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
800134a: b580 push {r7, lr}
|
|
800134c: b086 sub sp, #24
|
|
800134e: af00 add r7, sp, #0
|
|
8001350: 4603 mov r3, r0
|
|
8001352: 60b9 str r1, [r7, #8]
|
|
8001354: 607a str r2, [r7, #4]
|
|
8001356: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
8001358: 2300 movs r3, #0
|
|
800135a: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
800135c: f7ff ff3e bl 80011dc <__NVIC_GetPriorityGrouping>
|
|
8001360: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8001362: 687a ldr r2, [r7, #4]
|
|
8001364: 68b9 ldr r1, [r7, #8]
|
|
8001366: 6978 ldr r0, [r7, #20]
|
|
8001368: f7ff ff8e bl 8001288 <NVIC_EncodePriority>
|
|
800136c: 4602 mov r2, r0
|
|
800136e: f997 300f ldrsb.w r3, [r7, #15]
|
|
8001372: 4611 mov r1, r2
|
|
8001374: 4618 mov r0, r3
|
|
8001376: f7ff ff5d bl 8001234 <__NVIC_SetPriority>
|
|
}
|
|
800137a: bf00 nop
|
|
800137c: 3718 adds r7, #24
|
|
800137e: 46bd mov sp, r7
|
|
8001380: bd80 pop {r7, pc}
|
|
|
|
08001382 <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001382: b580 push {r7, lr}
|
|
8001384: b082 sub sp, #8
|
|
8001386: af00 add r7, sp, #0
|
|
8001388: 4603 mov r3, r0
|
|
800138a: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
800138c: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001390: 4618 mov r0, r3
|
|
8001392: f7ff ff31 bl 80011f8 <__NVIC_EnableIRQ>
|
|
}
|
|
8001396: bf00 nop
|
|
8001398: 3708 adds r7, #8
|
|
800139a: 46bd mov sp, r7
|
|
800139c: bd80 pop {r7, pc}
|
|
|
|
0800139e <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
800139e: b580 push {r7, lr}
|
|
80013a0: b082 sub sp, #8
|
|
80013a2: af00 add r7, sp, #0
|
|
80013a4: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
80013a6: 6878 ldr r0, [r7, #4]
|
|
80013a8: f7ff ffa2 bl 80012f0 <SysTick_Config>
|
|
80013ac: 4603 mov r3, r0
|
|
}
|
|
80013ae: 4618 mov r0, r3
|
|
80013b0: 3708 adds r7, #8
|
|
80013b2: 46bd mov sp, r7
|
|
80013b4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080013b8 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
80013b8: b480 push {r7}
|
|
80013ba: b089 sub sp, #36 @ 0x24
|
|
80013bc: af00 add r7, sp, #0
|
|
80013be: 6078 str r0, [r7, #4]
|
|
80013c0: 6039 str r1, [r7, #0]
|
|
uint32_t position;
|
|
uint32_t ioposition = 0x00U;
|
|
80013c2: 2300 movs r3, #0
|
|
80013c4: 617b str r3, [r7, #20]
|
|
uint32_t iocurrent = 0x00U;
|
|
80013c6: 2300 movs r3, #0
|
|
80013c8: 613b str r3, [r7, #16]
|
|
uint32_t temp = 0x00U;
|
|
80013ca: 2300 movs r3, #0
|
|
80013cc: 61bb str r3, [r7, #24]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
80013ce: 2300 movs r3, #0
|
|
80013d0: 61fb str r3, [r7, #28]
|
|
80013d2: e165 b.n 80016a0 <HAL_GPIO_Init+0x2e8>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = 0x01U << position;
|
|
80013d4: 2201 movs r2, #1
|
|
80013d6: 69fb ldr r3, [r7, #28]
|
|
80013d8: fa02 f303 lsl.w r3, r2, r3
|
|
80013dc: 617b str r3, [r7, #20]
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
80013de: 683b ldr r3, [r7, #0]
|
|
80013e0: 681b ldr r3, [r3, #0]
|
|
80013e2: 697a ldr r2, [r7, #20]
|
|
80013e4: 4013 ands r3, r2
|
|
80013e6: 613b str r3, [r7, #16]
|
|
|
|
if(iocurrent == ioposition)
|
|
80013e8: 693a ldr r2, [r7, #16]
|
|
80013ea: 697b ldr r3, [r7, #20]
|
|
80013ec: 429a cmp r2, r3
|
|
80013ee: f040 8154 bne.w 800169a <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
80013f2: 683b ldr r3, [r7, #0]
|
|
80013f4: 685b ldr r3, [r3, #4]
|
|
80013f6: f003 0303 and.w r3, r3, #3
|
|
80013fa: 2b01 cmp r3, #1
|
|
80013fc: d005 beq.n 800140a <HAL_GPIO_Init+0x52>
|
|
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
80013fe: 683b ldr r3, [r7, #0]
|
|
8001400: 685b ldr r3, [r3, #4]
|
|
8001402: f003 0303 and.w r3, r3, #3
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
8001406: 2b02 cmp r3, #2
|
|
8001408: d130 bne.n 800146c <HAL_GPIO_Init+0xb4>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
800140a: 687b ldr r3, [r7, #4]
|
|
800140c: 689b ldr r3, [r3, #8]
|
|
800140e: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
|
8001410: 69fb ldr r3, [r7, #28]
|
|
8001412: 005b lsls r3, r3, #1
|
|
8001414: 2203 movs r2, #3
|
|
8001416: fa02 f303 lsl.w r3, r2, r3
|
|
800141a: 43db mvns r3, r3
|
|
800141c: 69ba ldr r2, [r7, #24]
|
|
800141e: 4013 ands r3, r2
|
|
8001420: 61bb str r3, [r7, #24]
|
|
temp |= (GPIO_Init->Speed << (position * 2U));
|
|
8001422: 683b ldr r3, [r7, #0]
|
|
8001424: 68da ldr r2, [r3, #12]
|
|
8001426: 69fb ldr r3, [r7, #28]
|
|
8001428: 005b lsls r3, r3, #1
|
|
800142a: fa02 f303 lsl.w r3, r2, r3
|
|
800142e: 69ba ldr r2, [r7, #24]
|
|
8001430: 4313 orrs r3, r2
|
|
8001432: 61bb str r3, [r7, #24]
|
|
GPIOx->OSPEEDR = temp;
|
|
8001434: 687b ldr r3, [r7, #4]
|
|
8001436: 69ba ldr r2, [r7, #24]
|
|
8001438: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
800143a: 687b ldr r3, [r7, #4]
|
|
800143c: 685b ldr r3, [r3, #4]
|
|
800143e: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
8001440: 2201 movs r2, #1
|
|
8001442: 69fb ldr r3, [r7, #28]
|
|
8001444: fa02 f303 lsl.w r3, r2, r3
|
|
8001448: 43db mvns r3, r3
|
|
800144a: 69ba ldr r2, [r7, #24]
|
|
800144c: 4013 ands r3, r2
|
|
800144e: 61bb str r3, [r7, #24]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8001450: 683b ldr r3, [r7, #0]
|
|
8001452: 685b ldr r3, [r3, #4]
|
|
8001454: 091b lsrs r3, r3, #4
|
|
8001456: f003 0201 and.w r2, r3, #1
|
|
800145a: 69fb ldr r3, [r7, #28]
|
|
800145c: fa02 f303 lsl.w r3, r2, r3
|
|
8001460: 69ba ldr r2, [r7, #24]
|
|
8001462: 4313 orrs r3, r2
|
|
8001464: 61bb str r3, [r7, #24]
|
|
GPIOx->OTYPER = temp;
|
|
8001466: 687b ldr r3, [r7, #4]
|
|
8001468: 69ba ldr r2, [r7, #24]
|
|
800146a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
800146c: 683b ldr r3, [r7, #0]
|
|
800146e: 685b ldr r3, [r3, #4]
|
|
8001470: f003 0303 and.w r3, r3, #3
|
|
8001474: 2b03 cmp r3, #3
|
|
8001476: d017 beq.n 80014a8 <HAL_GPIO_Init+0xf0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
8001478: 687b ldr r3, [r7, #4]
|
|
800147a: 68db ldr r3, [r3, #12]
|
|
800147c: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
|
800147e: 69fb ldr r3, [r7, #28]
|
|
8001480: 005b lsls r3, r3, #1
|
|
8001482: 2203 movs r2, #3
|
|
8001484: fa02 f303 lsl.w r3, r2, r3
|
|
8001488: 43db mvns r3, r3
|
|
800148a: 69ba ldr r2, [r7, #24]
|
|
800148c: 4013 ands r3, r2
|
|
800148e: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
8001490: 683b ldr r3, [r7, #0]
|
|
8001492: 689a ldr r2, [r3, #8]
|
|
8001494: 69fb ldr r3, [r7, #28]
|
|
8001496: 005b lsls r3, r3, #1
|
|
8001498: fa02 f303 lsl.w r3, r2, r3
|
|
800149c: 69ba ldr r2, [r7, #24]
|
|
800149e: 4313 orrs r3, r2
|
|
80014a0: 61bb str r3, [r7, #24]
|
|
GPIOx->PUPDR = temp;
|
|
80014a2: 687b ldr r3, [r7, #4]
|
|
80014a4: 69ba ldr r2, [r7, #24]
|
|
80014a6: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
80014a8: 683b ldr r3, [r7, #0]
|
|
80014aa: 685b ldr r3, [r3, #4]
|
|
80014ac: f003 0303 and.w r3, r3, #3
|
|
80014b0: 2b02 cmp r3, #2
|
|
80014b2: d123 bne.n 80014fc <HAL_GPIO_Init+0x144>
|
|
{
|
|
/* Check the Alternate function parameter */
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3U];
|
|
80014b4: 69fb ldr r3, [r7, #28]
|
|
80014b6: 08da lsrs r2, r3, #3
|
|
80014b8: 687b ldr r3, [r7, #4]
|
|
80014ba: 3208 adds r2, #8
|
|
80014bc: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80014c0: 61bb str r3, [r7, #24]
|
|
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
|
|
80014c2: 69fb ldr r3, [r7, #28]
|
|
80014c4: f003 0307 and.w r3, r3, #7
|
|
80014c8: 009b lsls r3, r3, #2
|
|
80014ca: 220f movs r2, #15
|
|
80014cc: fa02 f303 lsl.w r3, r2, r3
|
|
80014d0: 43db mvns r3, r3
|
|
80014d2: 69ba ldr r2, [r7, #24]
|
|
80014d4: 4013 ands r3, r2
|
|
80014d6: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
|
|
80014d8: 683b ldr r3, [r7, #0]
|
|
80014da: 691a ldr r2, [r3, #16]
|
|
80014dc: 69fb ldr r3, [r7, #28]
|
|
80014de: f003 0307 and.w r3, r3, #7
|
|
80014e2: 009b lsls r3, r3, #2
|
|
80014e4: fa02 f303 lsl.w r3, r2, r3
|
|
80014e8: 69ba ldr r2, [r7, #24]
|
|
80014ea: 4313 orrs r3, r2
|
|
80014ec: 61bb str r3, [r7, #24]
|
|
GPIOx->AFR[position >> 3U] = temp;
|
|
80014ee: 69fb ldr r3, [r7, #28]
|
|
80014f0: 08da lsrs r2, r3, #3
|
|
80014f2: 687b ldr r3, [r7, #4]
|
|
80014f4: 3208 adds r2, #8
|
|
80014f6: 69b9 ldr r1, [r7, #24]
|
|
80014f8: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
80014fc: 687b ldr r3, [r7, #4]
|
|
80014fe: 681b ldr r3, [r3, #0]
|
|
8001500: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
|
8001502: 69fb ldr r3, [r7, #28]
|
|
8001504: 005b lsls r3, r3, #1
|
|
8001506: 2203 movs r2, #3
|
|
8001508: fa02 f303 lsl.w r3, r2, r3
|
|
800150c: 43db mvns r3, r3
|
|
800150e: 69ba ldr r2, [r7, #24]
|
|
8001510: 4013 ands r3, r2
|
|
8001512: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
|
8001514: 683b ldr r3, [r7, #0]
|
|
8001516: 685b ldr r3, [r3, #4]
|
|
8001518: f003 0203 and.w r2, r3, #3
|
|
800151c: 69fb ldr r3, [r7, #28]
|
|
800151e: 005b lsls r3, r3, #1
|
|
8001520: fa02 f303 lsl.w r3, r2, r3
|
|
8001524: 69ba ldr r2, [r7, #24]
|
|
8001526: 4313 orrs r3, r2
|
|
8001528: 61bb str r3, [r7, #24]
|
|
GPIOx->MODER = temp;
|
|
800152a: 687b ldr r3, [r7, #4]
|
|
800152c: 69ba ldr r2, [r7, #24]
|
|
800152e: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
|
|
8001530: 683b ldr r3, [r7, #0]
|
|
8001532: 685b ldr r3, [r3, #4]
|
|
8001534: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8001538: 2b00 cmp r3, #0
|
|
800153a: f000 80ae beq.w 800169a <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
800153e: 2300 movs r3, #0
|
|
8001540: 60fb str r3, [r7, #12]
|
|
8001542: 4b5d ldr r3, [pc, #372] @ (80016b8 <HAL_GPIO_Init+0x300>)
|
|
8001544: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001546: 4a5c ldr r2, [pc, #368] @ (80016b8 <HAL_GPIO_Init+0x300>)
|
|
8001548: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
800154c: 6453 str r3, [r2, #68] @ 0x44
|
|
800154e: 4b5a ldr r3, [pc, #360] @ (80016b8 <HAL_GPIO_Init+0x300>)
|
|
8001550: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001552: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8001556: 60fb str r3, [r7, #12]
|
|
8001558: 68fb ldr r3, [r7, #12]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2U];
|
|
800155a: 4a58 ldr r2, [pc, #352] @ (80016bc <HAL_GPIO_Init+0x304>)
|
|
800155c: 69fb ldr r3, [r7, #28]
|
|
800155e: 089b lsrs r3, r3, #2
|
|
8001560: 3302 adds r3, #2
|
|
8001562: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8001566: 61bb str r3, [r7, #24]
|
|
temp &= ~(0x0FU << (4U * (position & 0x03U)));
|
|
8001568: 69fb ldr r3, [r7, #28]
|
|
800156a: f003 0303 and.w r3, r3, #3
|
|
800156e: 009b lsls r3, r3, #2
|
|
8001570: 220f movs r2, #15
|
|
8001572: fa02 f303 lsl.w r3, r2, r3
|
|
8001576: 43db mvns r3, r3
|
|
8001578: 69ba ldr r2, [r7, #24]
|
|
800157a: 4013 ands r3, r2
|
|
800157c: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
|
|
800157e: 687b ldr r3, [r7, #4]
|
|
8001580: 4a4f ldr r2, [pc, #316] @ (80016c0 <HAL_GPIO_Init+0x308>)
|
|
8001582: 4293 cmp r3, r2
|
|
8001584: d025 beq.n 80015d2 <HAL_GPIO_Init+0x21a>
|
|
8001586: 687b ldr r3, [r7, #4]
|
|
8001588: 4a4e ldr r2, [pc, #312] @ (80016c4 <HAL_GPIO_Init+0x30c>)
|
|
800158a: 4293 cmp r3, r2
|
|
800158c: d01f beq.n 80015ce <HAL_GPIO_Init+0x216>
|
|
800158e: 687b ldr r3, [r7, #4]
|
|
8001590: 4a4d ldr r2, [pc, #308] @ (80016c8 <HAL_GPIO_Init+0x310>)
|
|
8001592: 4293 cmp r3, r2
|
|
8001594: d019 beq.n 80015ca <HAL_GPIO_Init+0x212>
|
|
8001596: 687b ldr r3, [r7, #4]
|
|
8001598: 4a4c ldr r2, [pc, #304] @ (80016cc <HAL_GPIO_Init+0x314>)
|
|
800159a: 4293 cmp r3, r2
|
|
800159c: d013 beq.n 80015c6 <HAL_GPIO_Init+0x20e>
|
|
800159e: 687b ldr r3, [r7, #4]
|
|
80015a0: 4a4b ldr r2, [pc, #300] @ (80016d0 <HAL_GPIO_Init+0x318>)
|
|
80015a2: 4293 cmp r3, r2
|
|
80015a4: d00d beq.n 80015c2 <HAL_GPIO_Init+0x20a>
|
|
80015a6: 687b ldr r3, [r7, #4]
|
|
80015a8: 4a4a ldr r2, [pc, #296] @ (80016d4 <HAL_GPIO_Init+0x31c>)
|
|
80015aa: 4293 cmp r3, r2
|
|
80015ac: d007 beq.n 80015be <HAL_GPIO_Init+0x206>
|
|
80015ae: 687b ldr r3, [r7, #4]
|
|
80015b0: 4a49 ldr r2, [pc, #292] @ (80016d8 <HAL_GPIO_Init+0x320>)
|
|
80015b2: 4293 cmp r3, r2
|
|
80015b4: d101 bne.n 80015ba <HAL_GPIO_Init+0x202>
|
|
80015b6: 2306 movs r3, #6
|
|
80015b8: e00c b.n 80015d4 <HAL_GPIO_Init+0x21c>
|
|
80015ba: 2307 movs r3, #7
|
|
80015bc: e00a b.n 80015d4 <HAL_GPIO_Init+0x21c>
|
|
80015be: 2305 movs r3, #5
|
|
80015c0: e008 b.n 80015d4 <HAL_GPIO_Init+0x21c>
|
|
80015c2: 2304 movs r3, #4
|
|
80015c4: e006 b.n 80015d4 <HAL_GPIO_Init+0x21c>
|
|
80015c6: 2303 movs r3, #3
|
|
80015c8: e004 b.n 80015d4 <HAL_GPIO_Init+0x21c>
|
|
80015ca: 2302 movs r3, #2
|
|
80015cc: e002 b.n 80015d4 <HAL_GPIO_Init+0x21c>
|
|
80015ce: 2301 movs r3, #1
|
|
80015d0: e000 b.n 80015d4 <HAL_GPIO_Init+0x21c>
|
|
80015d2: 2300 movs r3, #0
|
|
80015d4: 69fa ldr r2, [r7, #28]
|
|
80015d6: f002 0203 and.w r2, r2, #3
|
|
80015da: 0092 lsls r2, r2, #2
|
|
80015dc: 4093 lsls r3, r2
|
|
80015de: 69ba ldr r2, [r7, #24]
|
|
80015e0: 4313 orrs r3, r2
|
|
80015e2: 61bb str r3, [r7, #24]
|
|
SYSCFG->EXTICR[position >> 2U] = temp;
|
|
80015e4: 4935 ldr r1, [pc, #212] @ (80016bc <HAL_GPIO_Init+0x304>)
|
|
80015e6: 69fb ldr r3, [r7, #28]
|
|
80015e8: 089b lsrs r3, r3, #2
|
|
80015ea: 3302 adds r3, #2
|
|
80015ec: 69ba ldr r2, [r7, #24]
|
|
80015ee: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR;
|
|
80015f2: 4b3a ldr r3, [pc, #232] @ (80016dc <HAL_GPIO_Init+0x324>)
|
|
80015f4: 689b ldr r3, [r3, #8]
|
|
80015f6: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
80015f8: 693b ldr r3, [r7, #16]
|
|
80015fa: 43db mvns r3, r3
|
|
80015fc: 69ba ldr r2, [r7, #24]
|
|
80015fe: 4013 ands r3, r2
|
|
8001600: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
|
|
8001602: 683b ldr r3, [r7, #0]
|
|
8001604: 685b ldr r3, [r3, #4]
|
|
8001606: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
800160a: 2b00 cmp r3, #0
|
|
800160c: d003 beq.n 8001616 <HAL_GPIO_Init+0x25e>
|
|
{
|
|
temp |= iocurrent;
|
|
800160e: 69ba ldr r2, [r7, #24]
|
|
8001610: 693b ldr r3, [r7, #16]
|
|
8001612: 4313 orrs r3, r2
|
|
8001614: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->RTSR = temp;
|
|
8001616: 4a31 ldr r2, [pc, #196] @ (80016dc <HAL_GPIO_Init+0x324>)
|
|
8001618: 69bb ldr r3, [r7, #24]
|
|
800161a: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR;
|
|
800161c: 4b2f ldr r3, [pc, #188] @ (80016dc <HAL_GPIO_Init+0x324>)
|
|
800161e: 68db ldr r3, [r3, #12]
|
|
8001620: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001622: 693b ldr r3, [r7, #16]
|
|
8001624: 43db mvns r3, r3
|
|
8001626: 69ba ldr r2, [r7, #24]
|
|
8001628: 4013 ands r3, r2
|
|
800162a: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
|
|
800162c: 683b ldr r3, [r7, #0]
|
|
800162e: 685b ldr r3, [r3, #4]
|
|
8001630: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8001634: 2b00 cmp r3, #0
|
|
8001636: d003 beq.n 8001640 <HAL_GPIO_Init+0x288>
|
|
{
|
|
temp |= iocurrent;
|
|
8001638: 69ba ldr r2, [r7, #24]
|
|
800163a: 693b ldr r3, [r7, #16]
|
|
800163c: 4313 orrs r3, r2
|
|
800163e: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->FTSR = temp;
|
|
8001640: 4a26 ldr r2, [pc, #152] @ (80016dc <HAL_GPIO_Init+0x324>)
|
|
8001642: 69bb ldr r3, [r7, #24]
|
|
8001644: 60d3 str r3, [r2, #12]
|
|
|
|
temp = EXTI->EMR;
|
|
8001646: 4b25 ldr r3, [pc, #148] @ (80016dc <HAL_GPIO_Init+0x324>)
|
|
8001648: 685b ldr r3, [r3, #4]
|
|
800164a: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
800164c: 693b ldr r3, [r7, #16]
|
|
800164e: 43db mvns r3, r3
|
|
8001650: 69ba ldr r2, [r7, #24]
|
|
8001652: 4013 ands r3, r2
|
|
8001654: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
|
|
8001656: 683b ldr r3, [r7, #0]
|
|
8001658: 685b ldr r3, [r3, #4]
|
|
800165a: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800165e: 2b00 cmp r3, #0
|
|
8001660: d003 beq.n 800166a <HAL_GPIO_Init+0x2b2>
|
|
{
|
|
temp |= iocurrent;
|
|
8001662: 69ba ldr r2, [r7, #24]
|
|
8001664: 693b ldr r3, [r7, #16]
|
|
8001666: 4313 orrs r3, r2
|
|
8001668: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->EMR = temp;
|
|
800166a: 4a1c ldr r2, [pc, #112] @ (80016dc <HAL_GPIO_Init+0x324>)
|
|
800166c: 69bb ldr r3, [r7, #24]
|
|
800166e: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR;
|
|
8001670: 4b1a ldr r3, [pc, #104] @ (80016dc <HAL_GPIO_Init+0x324>)
|
|
8001672: 681b ldr r3, [r3, #0]
|
|
8001674: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001676: 693b ldr r3, [r7, #16]
|
|
8001678: 43db mvns r3, r3
|
|
800167a: 69ba ldr r2, [r7, #24]
|
|
800167c: 4013 ands r3, r2
|
|
800167e: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
|
|
8001680: 683b ldr r3, [r7, #0]
|
|
8001682: 685b ldr r3, [r3, #4]
|
|
8001684: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8001688: 2b00 cmp r3, #0
|
|
800168a: d003 beq.n 8001694 <HAL_GPIO_Init+0x2dc>
|
|
{
|
|
temp |= iocurrent;
|
|
800168c: 69ba ldr r2, [r7, #24]
|
|
800168e: 693b ldr r3, [r7, #16]
|
|
8001690: 4313 orrs r3, r2
|
|
8001692: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->IMR = temp;
|
|
8001694: 4a11 ldr r2, [pc, #68] @ (80016dc <HAL_GPIO_Init+0x324>)
|
|
8001696: 69bb ldr r3, [r7, #24]
|
|
8001698: 6013 str r3, [r2, #0]
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
800169a: 69fb ldr r3, [r7, #28]
|
|
800169c: 3301 adds r3, #1
|
|
800169e: 61fb str r3, [r7, #28]
|
|
80016a0: 69fb ldr r3, [r7, #28]
|
|
80016a2: 2b0f cmp r3, #15
|
|
80016a4: f67f ae96 bls.w 80013d4 <HAL_GPIO_Init+0x1c>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
80016a8: bf00 nop
|
|
80016aa: bf00 nop
|
|
80016ac: 3724 adds r7, #36 @ 0x24
|
|
80016ae: 46bd mov sp, r7
|
|
80016b0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80016b4: 4770 bx lr
|
|
80016b6: bf00 nop
|
|
80016b8: 40023800 .word 0x40023800
|
|
80016bc: 40013800 .word 0x40013800
|
|
80016c0: 40020000 .word 0x40020000
|
|
80016c4: 40020400 .word 0x40020400
|
|
80016c8: 40020800 .word 0x40020800
|
|
80016cc: 40020c00 .word 0x40020c00
|
|
80016d0: 40021000 .word 0x40021000
|
|
80016d4: 40021400 .word 0x40021400
|
|
80016d8: 40021800 .word 0x40021800
|
|
80016dc: 40013c00 .word 0x40013c00
|
|
|
|
080016e0 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
80016e0: b480 push {r7}
|
|
80016e2: b083 sub sp, #12
|
|
80016e4: af00 add r7, sp, #0
|
|
80016e6: 6078 str r0, [r7, #4]
|
|
80016e8: 460b mov r3, r1
|
|
80016ea: 807b strh r3, [r7, #2]
|
|
80016ec: 4613 mov r3, r2
|
|
80016ee: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
80016f0: 787b ldrb r3, [r7, #1]
|
|
80016f2: 2b00 cmp r3, #0
|
|
80016f4: d003 beq.n 80016fe <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = GPIO_Pin;
|
|
80016f6: 887a ldrh r2, [r7, #2]
|
|
80016f8: 687b ldr r3, [r7, #4]
|
|
80016fa: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
}
|
|
}
|
|
80016fc: e003 b.n 8001706 <HAL_GPIO_WritePin+0x26>
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
80016fe: 887b ldrh r3, [r7, #2]
|
|
8001700: 041a lsls r2, r3, #16
|
|
8001702: 687b ldr r3, [r7, #4]
|
|
8001704: 619a str r2, [r3, #24]
|
|
}
|
|
8001706: bf00 nop
|
|
8001708: 370c adds r7, #12
|
|
800170a: 46bd mov sp, r7
|
|
800170c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001710: 4770 bx lr
|
|
...
|
|
|
|
08001714 <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8001714: b580 push {r7, lr}
|
|
8001716: b084 sub sp, #16
|
|
8001718: af00 add r7, sp, #0
|
|
800171a: 6078 str r0, [r7, #4]
|
|
uint32_t freqrange;
|
|
uint32_t pclk1;
|
|
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
800171c: 687b ldr r3, [r7, #4]
|
|
800171e: 2b00 cmp r3, #0
|
|
8001720: d101 bne.n 8001726 <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001722: 2301 movs r3, #1
|
|
8001724: e12b b.n 800197e <HAL_I2C_Init+0x26a>
|
|
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
8001726: 687b ldr r3, [r7, #4]
|
|
8001728: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
800172c: b2db uxtb r3, r3
|
|
800172e: 2b00 cmp r3, #0
|
|
8001730: d106 bne.n 8001740 <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
8001732: 687b ldr r3, [r7, #4]
|
|
8001734: 2200 movs r2, #0
|
|
8001736: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_I2C_MspInit(hi2c);
|
|
800173a: 6878 ldr r0, [r7, #4]
|
|
800173c: f7ff f9fa bl 8000b34 <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8001740: 687b ldr r3, [r7, #4]
|
|
8001742: 2224 movs r2, #36 @ 0x24
|
|
8001744: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8001748: 687b ldr r3, [r7, #4]
|
|
800174a: 681b ldr r3, [r3, #0]
|
|
800174c: 681a ldr r2, [r3, #0]
|
|
800174e: 687b ldr r3, [r7, #4]
|
|
8001750: 681b ldr r3, [r3, #0]
|
|
8001752: f022 0201 bic.w r2, r2, #1
|
|
8001756: 601a str r2, [r3, #0]
|
|
|
|
/*Reset I2C*/
|
|
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
|
|
8001758: 687b ldr r3, [r7, #4]
|
|
800175a: 681b ldr r3, [r3, #0]
|
|
800175c: 681a ldr r2, [r3, #0]
|
|
800175e: 687b ldr r3, [r7, #4]
|
|
8001760: 681b ldr r3, [r3, #0]
|
|
8001762: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
8001766: 601a str r2, [r3, #0]
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
|
|
8001768: 687b ldr r3, [r7, #4]
|
|
800176a: 681b ldr r3, [r3, #0]
|
|
800176c: 681a ldr r2, [r3, #0]
|
|
800176e: 687b ldr r3, [r7, #4]
|
|
8001770: 681b ldr r3, [r3, #0]
|
|
8001772: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8001776: 601a str r2, [r3, #0]
|
|
|
|
/* Get PCLK1 frequency */
|
|
pclk1 = HAL_RCC_GetPCLK1Freq();
|
|
8001778: f001 fc88 bl 800308c <HAL_RCC_GetPCLK1Freq>
|
|
800177c: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check the minimum allowed PCLK1 frequency */
|
|
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
|
|
800177e: 687b ldr r3, [r7, #4]
|
|
8001780: 685b ldr r3, [r3, #4]
|
|
8001782: 4a81 ldr r2, [pc, #516] @ (8001988 <HAL_I2C_Init+0x274>)
|
|
8001784: 4293 cmp r3, r2
|
|
8001786: d807 bhi.n 8001798 <HAL_I2C_Init+0x84>
|
|
8001788: 68fb ldr r3, [r7, #12]
|
|
800178a: 4a80 ldr r2, [pc, #512] @ (800198c <HAL_I2C_Init+0x278>)
|
|
800178c: 4293 cmp r3, r2
|
|
800178e: bf94 ite ls
|
|
8001790: 2301 movls r3, #1
|
|
8001792: 2300 movhi r3, #0
|
|
8001794: b2db uxtb r3, r3
|
|
8001796: e006 b.n 80017a6 <HAL_I2C_Init+0x92>
|
|
8001798: 68fb ldr r3, [r7, #12]
|
|
800179a: 4a7d ldr r2, [pc, #500] @ (8001990 <HAL_I2C_Init+0x27c>)
|
|
800179c: 4293 cmp r3, r2
|
|
800179e: bf94 ite ls
|
|
80017a0: 2301 movls r3, #1
|
|
80017a2: 2300 movhi r3, #0
|
|
80017a4: b2db uxtb r3, r3
|
|
80017a6: 2b00 cmp r3, #0
|
|
80017a8: d001 beq.n 80017ae <HAL_I2C_Init+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
80017aa: 2301 movs r3, #1
|
|
80017ac: e0e7 b.n 800197e <HAL_I2C_Init+0x26a>
|
|
}
|
|
|
|
/* Calculate frequency range */
|
|
freqrange = I2C_FREQRANGE(pclk1);
|
|
80017ae: 68fb ldr r3, [r7, #12]
|
|
80017b0: 4a78 ldr r2, [pc, #480] @ (8001994 <HAL_I2C_Init+0x280>)
|
|
80017b2: fba2 2303 umull r2, r3, r2, r3
|
|
80017b6: 0c9b lsrs r3, r3, #18
|
|
80017b8: 60bb str r3, [r7, #8]
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
|
|
80017ba: 687b ldr r3, [r7, #4]
|
|
80017bc: 681b ldr r3, [r3, #0]
|
|
80017be: 685b ldr r3, [r3, #4]
|
|
80017c0: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
80017c4: 687b ldr r3, [r7, #4]
|
|
80017c6: 681b ldr r3, [r3, #0]
|
|
80017c8: 68ba ldr r2, [r7, #8]
|
|
80017ca: 430a orrs r2, r1
|
|
80017cc: 605a str r2, [r3, #4]
|
|
|
|
/*---------------------------- I2Cx TRISE Configuration --------------------*/
|
|
/* Configure I2Cx: Rise Time */
|
|
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
|
|
80017ce: 687b ldr r3, [r7, #4]
|
|
80017d0: 681b ldr r3, [r3, #0]
|
|
80017d2: 6a1b ldr r3, [r3, #32]
|
|
80017d4: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
80017d8: 687b ldr r3, [r7, #4]
|
|
80017da: 685b ldr r3, [r3, #4]
|
|
80017dc: 4a6a ldr r2, [pc, #424] @ (8001988 <HAL_I2C_Init+0x274>)
|
|
80017de: 4293 cmp r3, r2
|
|
80017e0: d802 bhi.n 80017e8 <HAL_I2C_Init+0xd4>
|
|
80017e2: 68bb ldr r3, [r7, #8]
|
|
80017e4: 3301 adds r3, #1
|
|
80017e6: e009 b.n 80017fc <HAL_I2C_Init+0xe8>
|
|
80017e8: 68bb ldr r3, [r7, #8]
|
|
80017ea: f44f 7296 mov.w r2, #300 @ 0x12c
|
|
80017ee: fb02 f303 mul.w r3, r2, r3
|
|
80017f2: 4a69 ldr r2, [pc, #420] @ (8001998 <HAL_I2C_Init+0x284>)
|
|
80017f4: fba2 2303 umull r2, r3, r2, r3
|
|
80017f8: 099b lsrs r3, r3, #6
|
|
80017fa: 3301 adds r3, #1
|
|
80017fc: 687a ldr r2, [r7, #4]
|
|
80017fe: 6812 ldr r2, [r2, #0]
|
|
8001800: 430b orrs r3, r1
|
|
8001802: 6213 str r3, [r2, #32]
|
|
|
|
/*---------------------------- I2Cx CCR Configuration ----------------------*/
|
|
/* Configure I2Cx: Speed */
|
|
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
|
|
8001804: 687b ldr r3, [r7, #4]
|
|
8001806: 681b ldr r3, [r3, #0]
|
|
8001808: 69db ldr r3, [r3, #28]
|
|
800180a: f423 424f bic.w r2, r3, #52992 @ 0xcf00
|
|
800180e: f022 02ff bic.w r2, r2, #255 @ 0xff
|
|
8001812: 687b ldr r3, [r7, #4]
|
|
8001814: 685b ldr r3, [r3, #4]
|
|
8001816: 495c ldr r1, [pc, #368] @ (8001988 <HAL_I2C_Init+0x274>)
|
|
8001818: 428b cmp r3, r1
|
|
800181a: d819 bhi.n 8001850 <HAL_I2C_Init+0x13c>
|
|
800181c: 68fb ldr r3, [r7, #12]
|
|
800181e: 1e59 subs r1, r3, #1
|
|
8001820: 687b ldr r3, [r7, #4]
|
|
8001822: 685b ldr r3, [r3, #4]
|
|
8001824: 005b lsls r3, r3, #1
|
|
8001826: fbb1 f3f3 udiv r3, r1, r3
|
|
800182a: 1c59 adds r1, r3, #1
|
|
800182c: f640 73fc movw r3, #4092 @ 0xffc
|
|
8001830: 400b ands r3, r1
|
|
8001832: 2b00 cmp r3, #0
|
|
8001834: d00a beq.n 800184c <HAL_I2C_Init+0x138>
|
|
8001836: 68fb ldr r3, [r7, #12]
|
|
8001838: 1e59 subs r1, r3, #1
|
|
800183a: 687b ldr r3, [r7, #4]
|
|
800183c: 685b ldr r3, [r3, #4]
|
|
800183e: 005b lsls r3, r3, #1
|
|
8001840: fbb1 f3f3 udiv r3, r1, r3
|
|
8001844: 3301 adds r3, #1
|
|
8001846: f3c3 030b ubfx r3, r3, #0, #12
|
|
800184a: e051 b.n 80018f0 <HAL_I2C_Init+0x1dc>
|
|
800184c: 2304 movs r3, #4
|
|
800184e: e04f b.n 80018f0 <HAL_I2C_Init+0x1dc>
|
|
8001850: 687b ldr r3, [r7, #4]
|
|
8001852: 689b ldr r3, [r3, #8]
|
|
8001854: 2b00 cmp r3, #0
|
|
8001856: d111 bne.n 800187c <HAL_I2C_Init+0x168>
|
|
8001858: 68fb ldr r3, [r7, #12]
|
|
800185a: 1e58 subs r0, r3, #1
|
|
800185c: 687b ldr r3, [r7, #4]
|
|
800185e: 6859 ldr r1, [r3, #4]
|
|
8001860: 460b mov r3, r1
|
|
8001862: 005b lsls r3, r3, #1
|
|
8001864: 440b add r3, r1
|
|
8001866: fbb0 f3f3 udiv r3, r0, r3
|
|
800186a: 3301 adds r3, #1
|
|
800186c: f3c3 030b ubfx r3, r3, #0, #12
|
|
8001870: 2b00 cmp r3, #0
|
|
8001872: bf0c ite eq
|
|
8001874: 2301 moveq r3, #1
|
|
8001876: 2300 movne r3, #0
|
|
8001878: b2db uxtb r3, r3
|
|
800187a: e012 b.n 80018a2 <HAL_I2C_Init+0x18e>
|
|
800187c: 68fb ldr r3, [r7, #12]
|
|
800187e: 1e58 subs r0, r3, #1
|
|
8001880: 687b ldr r3, [r7, #4]
|
|
8001882: 6859 ldr r1, [r3, #4]
|
|
8001884: 460b mov r3, r1
|
|
8001886: 009b lsls r3, r3, #2
|
|
8001888: 440b add r3, r1
|
|
800188a: 0099 lsls r1, r3, #2
|
|
800188c: 440b add r3, r1
|
|
800188e: fbb0 f3f3 udiv r3, r0, r3
|
|
8001892: 3301 adds r3, #1
|
|
8001894: f3c3 030b ubfx r3, r3, #0, #12
|
|
8001898: 2b00 cmp r3, #0
|
|
800189a: bf0c ite eq
|
|
800189c: 2301 moveq r3, #1
|
|
800189e: 2300 movne r3, #0
|
|
80018a0: b2db uxtb r3, r3
|
|
80018a2: 2b00 cmp r3, #0
|
|
80018a4: d001 beq.n 80018aa <HAL_I2C_Init+0x196>
|
|
80018a6: 2301 movs r3, #1
|
|
80018a8: e022 b.n 80018f0 <HAL_I2C_Init+0x1dc>
|
|
80018aa: 687b ldr r3, [r7, #4]
|
|
80018ac: 689b ldr r3, [r3, #8]
|
|
80018ae: 2b00 cmp r3, #0
|
|
80018b0: d10e bne.n 80018d0 <HAL_I2C_Init+0x1bc>
|
|
80018b2: 68fb ldr r3, [r7, #12]
|
|
80018b4: 1e58 subs r0, r3, #1
|
|
80018b6: 687b ldr r3, [r7, #4]
|
|
80018b8: 6859 ldr r1, [r3, #4]
|
|
80018ba: 460b mov r3, r1
|
|
80018bc: 005b lsls r3, r3, #1
|
|
80018be: 440b add r3, r1
|
|
80018c0: fbb0 f3f3 udiv r3, r0, r3
|
|
80018c4: 3301 adds r3, #1
|
|
80018c6: f3c3 030b ubfx r3, r3, #0, #12
|
|
80018ca: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80018ce: e00f b.n 80018f0 <HAL_I2C_Init+0x1dc>
|
|
80018d0: 68fb ldr r3, [r7, #12]
|
|
80018d2: 1e58 subs r0, r3, #1
|
|
80018d4: 687b ldr r3, [r7, #4]
|
|
80018d6: 6859 ldr r1, [r3, #4]
|
|
80018d8: 460b mov r3, r1
|
|
80018da: 009b lsls r3, r3, #2
|
|
80018dc: 440b add r3, r1
|
|
80018de: 0099 lsls r1, r3, #2
|
|
80018e0: 440b add r3, r1
|
|
80018e2: fbb0 f3f3 udiv r3, r0, r3
|
|
80018e6: 3301 adds r3, #1
|
|
80018e8: f3c3 030b ubfx r3, r3, #0, #12
|
|
80018ec: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
80018f0: 6879 ldr r1, [r7, #4]
|
|
80018f2: 6809 ldr r1, [r1, #0]
|
|
80018f4: 4313 orrs r3, r2
|
|
80018f6: 61cb str r3, [r1, #28]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
|
|
80018f8: 687b ldr r3, [r7, #4]
|
|
80018fa: 681b ldr r3, [r3, #0]
|
|
80018fc: 681b ldr r3, [r3, #0]
|
|
80018fe: f023 01c0 bic.w r1, r3, #192 @ 0xc0
|
|
8001902: 687b ldr r3, [r7, #4]
|
|
8001904: 69da ldr r2, [r3, #28]
|
|
8001906: 687b ldr r3, [r7, #4]
|
|
8001908: 6a1b ldr r3, [r3, #32]
|
|
800190a: 431a orrs r2, r3
|
|
800190c: 687b ldr r3, [r7, #4]
|
|
800190e: 681b ldr r3, [r3, #0]
|
|
8001910: 430a orrs r2, r1
|
|
8001912: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Configure I2Cx: Own Address1 and addressing mode */
|
|
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
|
|
8001914: 687b ldr r3, [r7, #4]
|
|
8001916: 681b ldr r3, [r3, #0]
|
|
8001918: 689b ldr r3, [r3, #8]
|
|
800191a: f423 4303 bic.w r3, r3, #33536 @ 0x8300
|
|
800191e: f023 03ff bic.w r3, r3, #255 @ 0xff
|
|
8001922: 687a ldr r2, [r7, #4]
|
|
8001924: 6911 ldr r1, [r2, #16]
|
|
8001926: 687a ldr r2, [r7, #4]
|
|
8001928: 68d2 ldr r2, [r2, #12]
|
|
800192a: 4311 orrs r1, r2
|
|
800192c: 687a ldr r2, [r7, #4]
|
|
800192e: 6812 ldr r2, [r2, #0]
|
|
8001930: 430b orrs r3, r1
|
|
8001932: 6093 str r3, [r2, #8]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
|
|
8001934: 687b ldr r3, [r7, #4]
|
|
8001936: 681b ldr r3, [r3, #0]
|
|
8001938: 68db ldr r3, [r3, #12]
|
|
800193a: f023 01ff bic.w r1, r3, #255 @ 0xff
|
|
800193e: 687b ldr r3, [r7, #4]
|
|
8001940: 695a ldr r2, [r3, #20]
|
|
8001942: 687b ldr r3, [r7, #4]
|
|
8001944: 699b ldr r3, [r3, #24]
|
|
8001946: 431a orrs r2, r3
|
|
8001948: 687b ldr r3, [r7, #4]
|
|
800194a: 681b ldr r3, [r3, #0]
|
|
800194c: 430a orrs r2, r1
|
|
800194e: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8001950: 687b ldr r3, [r7, #4]
|
|
8001952: 681b ldr r3, [r3, #0]
|
|
8001954: 681a ldr r2, [r3, #0]
|
|
8001956: 687b ldr r3, [r7, #4]
|
|
8001958: 681b ldr r3, [r3, #0]
|
|
800195a: f042 0201 orr.w r2, r2, #1
|
|
800195e: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8001960: 687b ldr r3, [r7, #4]
|
|
8001962: 2200 movs r2, #0
|
|
8001964: 641a str r2, [r3, #64] @ 0x40
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8001966: 687b ldr r3, [r7, #4]
|
|
8001968: 2220 movs r2, #32
|
|
800196a: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
800196e: 687b ldr r3, [r7, #4]
|
|
8001970: 2200 movs r2, #0
|
|
8001972: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8001974: 687b ldr r3, [r7, #4]
|
|
8001976: 2200 movs r2, #0
|
|
8001978: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
|
|
return HAL_OK;
|
|
800197c: 2300 movs r3, #0
|
|
}
|
|
800197e: 4618 mov r0, r3
|
|
8001980: 3710 adds r7, #16
|
|
8001982: 46bd mov sp, r7
|
|
8001984: bd80 pop {r7, pc}
|
|
8001986: bf00 nop
|
|
8001988: 000186a0 .word 0x000186a0
|
|
800198c: 001e847f .word 0x001e847f
|
|
8001990: 003d08ff .word 0x003d08ff
|
|
8001994: 431bde83 .word 0x431bde83
|
|
8001998: 10624dd3 .word 0x10624dd3
|
|
|
|
0800199c <HAL_PCD_Init>:
|
|
* parameters in the PCD_InitTypeDef and initialize the associated handle.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
800199c: b580 push {r7, lr}
|
|
800199e: b086 sub sp, #24
|
|
80019a0: af02 add r7, sp, #8
|
|
80019a2: 6078 str r0, [r7, #4]
|
|
const USB_OTG_GlobalTypeDef *USBx;
|
|
#endif /* defined (USB_OTG_FS) */
|
|
uint8_t i;
|
|
|
|
/* Check the PCD handle allocation */
|
|
if (hpcd == NULL)
|
|
80019a4: 687b ldr r3, [r7, #4]
|
|
80019a6: 2b00 cmp r3, #0
|
|
80019a8: d101 bne.n 80019ae <HAL_PCD_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80019aa: 2301 movs r3, #1
|
|
80019ac: e108 b.n 8001bc0 <HAL_PCD_Init+0x224>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
|
|
|
|
#if defined (USB_OTG_FS)
|
|
USBx = hpcd->Instance;
|
|
80019ae: 687b ldr r3, [r7, #4]
|
|
80019b0: 681b ldr r3, [r3, #0]
|
|
80019b2: 60bb str r3, [r7, #8]
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
if (hpcd->State == HAL_PCD_STATE_RESET)
|
|
80019b4: 687b ldr r3, [r7, #4]
|
|
80019b6: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495
|
|
80019ba: b2db uxtb r3, r3
|
|
80019bc: 2b00 cmp r3, #0
|
|
80019be: d106 bne.n 80019ce <HAL_PCD_Init+0x32>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hpcd->Lock = HAL_UNLOCKED;
|
|
80019c0: 687b ldr r3, [r7, #4]
|
|
80019c2: 2200 movs r2, #0
|
|
80019c4: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
/* Init the low level hardware */
|
|
hpcd->MspInitCallback(hpcd);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_PCD_MspInit(hpcd);
|
|
80019c8: 6878 ldr r0, [r7, #4]
|
|
80019ca: f006 fc49 bl 8008260 <HAL_PCD_MspInit>
|
|
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
hpcd->State = HAL_PCD_STATE_BUSY;
|
|
80019ce: 687b ldr r3, [r7, #4]
|
|
80019d0: 2203 movs r2, #3
|
|
80019d2: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
|
|
#if defined (USB_OTG_FS)
|
|
/* Disable DMA mode for FS instance */
|
|
if (USBx == USB_OTG_FS)
|
|
80019d6: 68bb ldr r3, [r7, #8]
|
|
80019d8: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
80019dc: d102 bne.n 80019e4 <HAL_PCD_Init+0x48>
|
|
{
|
|
hpcd->Init.dma_enable = 0U;
|
|
80019de: 687b ldr r3, [r7, #4]
|
|
80019e0: 2200 movs r2, #0
|
|
80019e2: 719a strb r2, [r3, #6]
|
|
}
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
/* Disable the Interrupts */
|
|
__HAL_PCD_DISABLE(hpcd);
|
|
80019e4: 687b ldr r3, [r7, #4]
|
|
80019e6: 681b ldr r3, [r3, #0]
|
|
80019e8: 4618 mov r0, r3
|
|
80019ea: f003 fb6e bl 80050ca <USB_DisableGlobalInt>
|
|
|
|
/*Init the Core (common init.) */
|
|
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
80019ee: 687b ldr r3, [r7, #4]
|
|
80019f0: 6818 ldr r0, [r3, #0]
|
|
80019f2: 687b ldr r3, [r7, #4]
|
|
80019f4: 7c1a ldrb r2, [r3, #16]
|
|
80019f6: f88d 2000 strb.w r2, [sp]
|
|
80019fa: 3304 adds r3, #4
|
|
80019fc: cb0e ldmia r3, {r1, r2, r3}
|
|
80019fe: f003 fa4d bl 8004e9c <USB_CoreInit>
|
|
8001a02: 4603 mov r3, r0
|
|
8001a04: 2b00 cmp r3, #0
|
|
8001a06: d005 beq.n 8001a14 <HAL_PCD_Init+0x78>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8001a08: 687b ldr r3, [r7, #4]
|
|
8001a0a: 2202 movs r2, #2
|
|
8001a0c: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8001a10: 2301 movs r3, #1
|
|
8001a12: e0d5 b.n 8001bc0 <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
/* Force Device Mode */
|
|
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
|
|
8001a14: 687b ldr r3, [r7, #4]
|
|
8001a16: 681b ldr r3, [r3, #0]
|
|
8001a18: 2100 movs r1, #0
|
|
8001a1a: 4618 mov r0, r3
|
|
8001a1c: f003 fb66 bl 80050ec <USB_SetCurrentMode>
|
|
8001a20: 4603 mov r3, r0
|
|
8001a22: 2b00 cmp r3, #0
|
|
8001a24: d005 beq.n 8001a32 <HAL_PCD_Init+0x96>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8001a26: 687b ldr r3, [r7, #4]
|
|
8001a28: 2202 movs r2, #2
|
|
8001a2a: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8001a2e: 2301 movs r3, #1
|
|
8001a30: e0c6 b.n 8001bc0 <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
/* Init endpoints structures */
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001a32: 2300 movs r3, #0
|
|
8001a34: 73fb strb r3, [r7, #15]
|
|
8001a36: e04a b.n 8001ace <HAL_PCD_Init+0x132>
|
|
{
|
|
/* Init ep structure */
|
|
hpcd->IN_ep[i].is_in = 1U;
|
|
8001a38: 7bfa ldrb r2, [r7, #15]
|
|
8001a3a: 6879 ldr r1, [r7, #4]
|
|
8001a3c: 4613 mov r3, r2
|
|
8001a3e: 00db lsls r3, r3, #3
|
|
8001a40: 4413 add r3, r2
|
|
8001a42: 009b lsls r3, r3, #2
|
|
8001a44: 440b add r3, r1
|
|
8001a46: 3315 adds r3, #21
|
|
8001a48: 2201 movs r2, #1
|
|
8001a4a: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].num = i;
|
|
8001a4c: 7bfa ldrb r2, [r7, #15]
|
|
8001a4e: 6879 ldr r1, [r7, #4]
|
|
8001a50: 4613 mov r3, r2
|
|
8001a52: 00db lsls r3, r3, #3
|
|
8001a54: 4413 add r3, r2
|
|
8001a56: 009b lsls r3, r3, #2
|
|
8001a58: 440b add r3, r1
|
|
8001a5a: 3314 adds r3, #20
|
|
8001a5c: 7bfa ldrb r2, [r7, #15]
|
|
8001a5e: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].tx_fifo_num = i;
|
|
8001a60: 7bfa ldrb r2, [r7, #15]
|
|
8001a62: 7bfb ldrb r3, [r7, #15]
|
|
8001a64: b298 uxth r0, r3
|
|
8001a66: 6879 ldr r1, [r7, #4]
|
|
8001a68: 4613 mov r3, r2
|
|
8001a6a: 00db lsls r3, r3, #3
|
|
8001a6c: 4413 add r3, r2
|
|
8001a6e: 009b lsls r3, r3, #2
|
|
8001a70: 440b add r3, r1
|
|
8001a72: 332e adds r3, #46 @ 0x2e
|
|
8001a74: 4602 mov r2, r0
|
|
8001a76: 801a strh r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
|
|
8001a78: 7bfa ldrb r2, [r7, #15]
|
|
8001a7a: 6879 ldr r1, [r7, #4]
|
|
8001a7c: 4613 mov r3, r2
|
|
8001a7e: 00db lsls r3, r3, #3
|
|
8001a80: 4413 add r3, r2
|
|
8001a82: 009b lsls r3, r3, #2
|
|
8001a84: 440b add r3, r1
|
|
8001a86: 3318 adds r3, #24
|
|
8001a88: 2200 movs r2, #0
|
|
8001a8a: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].maxpacket = 0U;
|
|
8001a8c: 7bfa ldrb r2, [r7, #15]
|
|
8001a8e: 6879 ldr r1, [r7, #4]
|
|
8001a90: 4613 mov r3, r2
|
|
8001a92: 00db lsls r3, r3, #3
|
|
8001a94: 4413 add r3, r2
|
|
8001a96: 009b lsls r3, r3, #2
|
|
8001a98: 440b add r3, r1
|
|
8001a9a: 331c adds r3, #28
|
|
8001a9c: 2200 movs r2, #0
|
|
8001a9e: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_buff = 0U;
|
|
8001aa0: 7bfa ldrb r2, [r7, #15]
|
|
8001aa2: 6879 ldr r1, [r7, #4]
|
|
8001aa4: 4613 mov r3, r2
|
|
8001aa6: 00db lsls r3, r3, #3
|
|
8001aa8: 4413 add r3, r2
|
|
8001aaa: 009b lsls r3, r3, #2
|
|
8001aac: 440b add r3, r1
|
|
8001aae: 3320 adds r3, #32
|
|
8001ab0: 2200 movs r2, #0
|
|
8001ab2: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_len = 0U;
|
|
8001ab4: 7bfa ldrb r2, [r7, #15]
|
|
8001ab6: 6879 ldr r1, [r7, #4]
|
|
8001ab8: 4613 mov r3, r2
|
|
8001aba: 00db lsls r3, r3, #3
|
|
8001abc: 4413 add r3, r2
|
|
8001abe: 009b lsls r3, r3, #2
|
|
8001ac0: 440b add r3, r1
|
|
8001ac2: 3324 adds r3, #36 @ 0x24
|
|
8001ac4: 2200 movs r2, #0
|
|
8001ac6: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001ac8: 7bfb ldrb r3, [r7, #15]
|
|
8001aca: 3301 adds r3, #1
|
|
8001acc: 73fb strb r3, [r7, #15]
|
|
8001ace: 687b ldr r3, [r7, #4]
|
|
8001ad0: 791b ldrb r3, [r3, #4]
|
|
8001ad2: 7bfa ldrb r2, [r7, #15]
|
|
8001ad4: 429a cmp r2, r3
|
|
8001ad6: d3af bcc.n 8001a38 <HAL_PCD_Init+0x9c>
|
|
}
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001ad8: 2300 movs r3, #0
|
|
8001ada: 73fb strb r3, [r7, #15]
|
|
8001adc: e044 b.n 8001b68 <HAL_PCD_Init+0x1cc>
|
|
{
|
|
hpcd->OUT_ep[i].is_in = 0U;
|
|
8001ade: 7bfa ldrb r2, [r7, #15]
|
|
8001ae0: 6879 ldr r1, [r7, #4]
|
|
8001ae2: 4613 mov r3, r2
|
|
8001ae4: 00db lsls r3, r3, #3
|
|
8001ae6: 4413 add r3, r2
|
|
8001ae8: 009b lsls r3, r3, #2
|
|
8001aea: 440b add r3, r1
|
|
8001aec: f203 2355 addw r3, r3, #597 @ 0x255
|
|
8001af0: 2200 movs r2, #0
|
|
8001af2: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].num = i;
|
|
8001af4: 7bfa ldrb r2, [r7, #15]
|
|
8001af6: 6879 ldr r1, [r7, #4]
|
|
8001af8: 4613 mov r3, r2
|
|
8001afa: 00db lsls r3, r3, #3
|
|
8001afc: 4413 add r3, r2
|
|
8001afe: 009b lsls r3, r3, #2
|
|
8001b00: 440b add r3, r1
|
|
8001b02: f503 7315 add.w r3, r3, #596 @ 0x254
|
|
8001b06: 7bfa ldrb r2, [r7, #15]
|
|
8001b08: 701a strb r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
|
|
8001b0a: 7bfa ldrb r2, [r7, #15]
|
|
8001b0c: 6879 ldr r1, [r7, #4]
|
|
8001b0e: 4613 mov r3, r2
|
|
8001b10: 00db lsls r3, r3, #3
|
|
8001b12: 4413 add r3, r2
|
|
8001b14: 009b lsls r3, r3, #2
|
|
8001b16: 440b add r3, r1
|
|
8001b18: f503 7316 add.w r3, r3, #600 @ 0x258
|
|
8001b1c: 2200 movs r2, #0
|
|
8001b1e: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].maxpacket = 0U;
|
|
8001b20: 7bfa ldrb r2, [r7, #15]
|
|
8001b22: 6879 ldr r1, [r7, #4]
|
|
8001b24: 4613 mov r3, r2
|
|
8001b26: 00db lsls r3, r3, #3
|
|
8001b28: 4413 add r3, r2
|
|
8001b2a: 009b lsls r3, r3, #2
|
|
8001b2c: 440b add r3, r1
|
|
8001b2e: f503 7317 add.w r3, r3, #604 @ 0x25c
|
|
8001b32: 2200 movs r2, #0
|
|
8001b34: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_buff = 0U;
|
|
8001b36: 7bfa ldrb r2, [r7, #15]
|
|
8001b38: 6879 ldr r1, [r7, #4]
|
|
8001b3a: 4613 mov r3, r2
|
|
8001b3c: 00db lsls r3, r3, #3
|
|
8001b3e: 4413 add r3, r2
|
|
8001b40: 009b lsls r3, r3, #2
|
|
8001b42: 440b add r3, r1
|
|
8001b44: f503 7318 add.w r3, r3, #608 @ 0x260
|
|
8001b48: 2200 movs r2, #0
|
|
8001b4a: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_len = 0U;
|
|
8001b4c: 7bfa ldrb r2, [r7, #15]
|
|
8001b4e: 6879 ldr r1, [r7, #4]
|
|
8001b50: 4613 mov r3, r2
|
|
8001b52: 00db lsls r3, r3, #3
|
|
8001b54: 4413 add r3, r2
|
|
8001b56: 009b lsls r3, r3, #2
|
|
8001b58: 440b add r3, r1
|
|
8001b5a: f503 7319 add.w r3, r3, #612 @ 0x264
|
|
8001b5e: 2200 movs r2, #0
|
|
8001b60: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8001b62: 7bfb ldrb r3, [r7, #15]
|
|
8001b64: 3301 adds r3, #1
|
|
8001b66: 73fb strb r3, [r7, #15]
|
|
8001b68: 687b ldr r3, [r7, #4]
|
|
8001b6a: 791b ldrb r3, [r3, #4]
|
|
8001b6c: 7bfa ldrb r2, [r7, #15]
|
|
8001b6e: 429a cmp r2, r3
|
|
8001b70: d3b5 bcc.n 8001ade <HAL_PCD_Init+0x142>
|
|
}
|
|
|
|
/* Init Device */
|
|
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8001b72: 687b ldr r3, [r7, #4]
|
|
8001b74: 6818 ldr r0, [r3, #0]
|
|
8001b76: 687b ldr r3, [r7, #4]
|
|
8001b78: 7c1a ldrb r2, [r3, #16]
|
|
8001b7a: f88d 2000 strb.w r2, [sp]
|
|
8001b7e: 3304 adds r3, #4
|
|
8001b80: cb0e ldmia r3, {r1, r2, r3}
|
|
8001b82: f003 faff bl 8005184 <USB_DevInit>
|
|
8001b86: 4603 mov r3, r0
|
|
8001b88: 2b00 cmp r3, #0
|
|
8001b8a: d005 beq.n 8001b98 <HAL_PCD_Init+0x1fc>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8001b8c: 687b ldr r3, [r7, #4]
|
|
8001b8e: 2202 movs r2, #2
|
|
8001b90: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8001b94: 2301 movs r3, #1
|
|
8001b96: e013 b.n 8001bc0 <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
hpcd->USB_Address = 0U;
|
|
8001b98: 687b ldr r3, [r7, #4]
|
|
8001b9a: 2200 movs r2, #0
|
|
8001b9c: 745a strb r2, [r3, #17]
|
|
hpcd->State = HAL_PCD_STATE_READY;
|
|
8001b9e: 687b ldr r3, [r7, #4]
|
|
8001ba0: 2201 movs r2, #1
|
|
8001ba2: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* Activate LPM */
|
|
if (hpcd->Init.lpm_enable == 1U)
|
|
8001ba6: 687b ldr r3, [r7, #4]
|
|
8001ba8: 7b1b ldrb r3, [r3, #12]
|
|
8001baa: 2b01 cmp r3, #1
|
|
8001bac: d102 bne.n 8001bb4 <HAL_PCD_Init+0x218>
|
|
{
|
|
(void)HAL_PCDEx_ActivateLPM(hpcd);
|
|
8001bae: 6878 ldr r0, [r7, #4]
|
|
8001bb0: f001 f956 bl 8002e60 <HAL_PCDEx_ActivateLPM>
|
|
}
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
(void)USB_DevDisconnect(hpcd->Instance);
|
|
8001bb4: 687b ldr r3, [r7, #4]
|
|
8001bb6: 681b ldr r3, [r3, #0]
|
|
8001bb8: 4618 mov r0, r3
|
|
8001bba: f004 fb3c bl 8006236 <USB_DevDisconnect>
|
|
|
|
return HAL_OK;
|
|
8001bbe: 2300 movs r3, #0
|
|
}
|
|
8001bc0: 4618 mov r0, r3
|
|
8001bc2: 3710 adds r7, #16
|
|
8001bc4: 46bd mov sp, r7
|
|
8001bc6: bd80 pop {r7, pc}
|
|
|
|
08001bc8 <HAL_PCD_Start>:
|
|
* @brief Start the USB device
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8001bc8: b580 push {r7, lr}
|
|
8001bca: b084 sub sp, #16
|
|
8001bcc: af00 add r7, sp, #0
|
|
8001bce: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8001bd0: 687b ldr r3, [r7, #4]
|
|
8001bd2: 681b ldr r3, [r3, #0]
|
|
8001bd4: 60fb str r3, [r7, #12]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8001bd6: 687b ldr r3, [r7, #4]
|
|
8001bd8: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8001bdc: 2b01 cmp r3, #1
|
|
8001bde: d101 bne.n 8001be4 <HAL_PCD_Start+0x1c>
|
|
8001be0: 2302 movs r3, #2
|
|
8001be2: e022 b.n 8001c2a <HAL_PCD_Start+0x62>
|
|
8001be4: 687b ldr r3, [r7, #4]
|
|
8001be6: 2201 movs r2, #1
|
|
8001be8: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
|
|
8001bec: 68fb ldr r3, [r7, #12]
|
|
8001bee: 68db ldr r3, [r3, #12]
|
|
8001bf0: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8001bf4: 2b00 cmp r3, #0
|
|
8001bf6: d009 beq.n 8001c0c <HAL_PCD_Start+0x44>
|
|
(hpcd->Init.battery_charging_enable == 1U))
|
|
8001bf8: 687b ldr r3, [r7, #4]
|
|
8001bfa: 7b5b ldrb r3, [r3, #13]
|
|
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
|
|
8001bfc: 2b01 cmp r3, #1
|
|
8001bfe: d105 bne.n 8001c0c <HAL_PCD_Start+0x44>
|
|
{
|
|
/* Enable USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
8001c00: 68fb ldr r3, [r7, #12]
|
|
8001c02: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8001c04: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
8001c08: 68fb ldr r3, [r7, #12]
|
|
8001c0a: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
|
|
__HAL_PCD_ENABLE(hpcd);
|
|
8001c0c: 687b ldr r3, [r7, #4]
|
|
8001c0e: 681b ldr r3, [r3, #0]
|
|
8001c10: 4618 mov r0, r3
|
|
8001c12: f003 fa49 bl 80050a8 <USB_EnableGlobalInt>
|
|
(void)USB_DevConnect(hpcd->Instance);
|
|
8001c16: 687b ldr r3, [r7, #4]
|
|
8001c18: 681b ldr r3, [r3, #0]
|
|
8001c1a: 4618 mov r0, r3
|
|
8001c1c: f004 faea bl 80061f4 <USB_DevConnect>
|
|
__HAL_UNLOCK(hpcd);
|
|
8001c20: 687b ldr r3, [r7, #4]
|
|
8001c22: 2200 movs r2, #0
|
|
8001c24: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8001c28: 2300 movs r3, #0
|
|
}
|
|
8001c2a: 4618 mov r0, r3
|
|
8001c2c: 3710 adds r7, #16
|
|
8001c2e: 46bd mov sp, r7
|
|
8001c30: bd80 pop {r7, pc}
|
|
|
|
08001c32 <HAL_PCD_IRQHandler>:
|
|
* @brief Handles PCD interrupt request.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8001c32: b590 push {r4, r7, lr}
|
|
8001c34: b08d sub sp, #52 @ 0x34
|
|
8001c36: af00 add r7, sp, #0
|
|
8001c38: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8001c3a: 687b ldr r3, [r7, #4]
|
|
8001c3c: 681b ldr r3, [r3, #0]
|
|
8001c3e: 623b str r3, [r7, #32]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8001c40: 6a3b ldr r3, [r7, #32]
|
|
8001c42: 61fb str r3, [r7, #28]
|
|
uint32_t epnum;
|
|
uint32_t fifoemptymsk;
|
|
uint32_t RegVal;
|
|
|
|
/* ensure that we are in device mode */
|
|
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
|
|
8001c44: 687b ldr r3, [r7, #4]
|
|
8001c46: 681b ldr r3, [r3, #0]
|
|
8001c48: 4618 mov r0, r3
|
|
8001c4a: f004 fba8 bl 800639e <USB_GetMode>
|
|
8001c4e: 4603 mov r3, r0
|
|
8001c50: 2b00 cmp r3, #0
|
|
8001c52: f040 84b9 bne.w 80025c8 <HAL_PCD_IRQHandler+0x996>
|
|
{
|
|
/* avoid spurious interrupt */
|
|
if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
|
|
8001c56: 687b ldr r3, [r7, #4]
|
|
8001c58: 681b ldr r3, [r3, #0]
|
|
8001c5a: 4618 mov r0, r3
|
|
8001c5c: f004 fb0c bl 8006278 <USB_ReadInterrupts>
|
|
8001c60: 4603 mov r3, r0
|
|
8001c62: 2b00 cmp r3, #0
|
|
8001c64: f000 84af beq.w 80025c6 <HAL_PCD_IRQHandler+0x994>
|
|
{
|
|
return;
|
|
}
|
|
|
|
/* store current frame number */
|
|
hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos;
|
|
8001c68: 69fb ldr r3, [r7, #28]
|
|
8001c6a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8001c6e: 689b ldr r3, [r3, #8]
|
|
8001c70: 0a1b lsrs r3, r3, #8
|
|
8001c72: f3c3 020d ubfx r2, r3, #0, #14
|
|
8001c76: 687b ldr r3, [r7, #4]
|
|
8001c78: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
|
|
8001c7c: 687b ldr r3, [r7, #4]
|
|
8001c7e: 681b ldr r3, [r3, #0]
|
|
8001c80: 4618 mov r0, r3
|
|
8001c82: f004 faf9 bl 8006278 <USB_ReadInterrupts>
|
|
8001c86: 4603 mov r3, r0
|
|
8001c88: f003 0302 and.w r3, r3, #2
|
|
8001c8c: 2b02 cmp r3, #2
|
|
8001c8e: d107 bne.n 8001ca0 <HAL_PCD_IRQHandler+0x6e>
|
|
{
|
|
/* incorrect mode, acknowledge the interrupt */
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
|
|
8001c90: 687b ldr r3, [r7, #4]
|
|
8001c92: 681b ldr r3, [r3, #0]
|
|
8001c94: 695a ldr r2, [r3, #20]
|
|
8001c96: 687b ldr r3, [r7, #4]
|
|
8001c98: 681b ldr r3, [r3, #0]
|
|
8001c9a: f002 0202 and.w r2, r2, #2
|
|
8001c9e: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle RxQLevel Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
|
|
8001ca0: 687b ldr r3, [r7, #4]
|
|
8001ca2: 681b ldr r3, [r3, #0]
|
|
8001ca4: 4618 mov r0, r3
|
|
8001ca6: f004 fae7 bl 8006278 <USB_ReadInterrupts>
|
|
8001caa: 4603 mov r3, r0
|
|
8001cac: f003 0310 and.w r3, r3, #16
|
|
8001cb0: 2b10 cmp r3, #16
|
|
8001cb2: d161 bne.n 8001d78 <HAL_PCD_IRQHandler+0x146>
|
|
{
|
|
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
8001cb4: 687b ldr r3, [r7, #4]
|
|
8001cb6: 681b ldr r3, [r3, #0]
|
|
8001cb8: 699a ldr r2, [r3, #24]
|
|
8001cba: 687b ldr r3, [r7, #4]
|
|
8001cbc: 681b ldr r3, [r3, #0]
|
|
8001cbe: f022 0210 bic.w r2, r2, #16
|
|
8001cc2: 619a str r2, [r3, #24]
|
|
|
|
RegVal = USBx->GRXSTSP;
|
|
8001cc4: 6a3b ldr r3, [r7, #32]
|
|
8001cc6: 6a1b ldr r3, [r3, #32]
|
|
8001cc8: 61bb str r3, [r7, #24]
|
|
|
|
ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM];
|
|
8001cca: 69bb ldr r3, [r7, #24]
|
|
8001ccc: f003 020f and.w r2, r3, #15
|
|
8001cd0: 4613 mov r3, r2
|
|
8001cd2: 00db lsls r3, r3, #3
|
|
8001cd4: 4413 add r3, r2
|
|
8001cd6: 009b lsls r3, r3, #2
|
|
8001cd8: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8001cdc: 687a ldr r2, [r7, #4]
|
|
8001cde: 4413 add r3, r2
|
|
8001ce0: 3304 adds r3, #4
|
|
8001ce2: 617b str r3, [r7, #20]
|
|
|
|
if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
|
|
8001ce4: 69bb ldr r3, [r7, #24]
|
|
8001ce6: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
|
|
8001cea: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
8001cee: d124 bne.n 8001d3a <HAL_PCD_IRQHandler+0x108>
|
|
{
|
|
if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U)
|
|
8001cf0: 69ba ldr r2, [r7, #24]
|
|
8001cf2: f647 73f0 movw r3, #32752 @ 0x7ff0
|
|
8001cf6: 4013 ands r3, r2
|
|
8001cf8: 2b00 cmp r3, #0
|
|
8001cfa: d035 beq.n 8001d68 <HAL_PCD_IRQHandler+0x136>
|
|
{
|
|
(void)USB_ReadPacket(USBx, ep->xfer_buff,
|
|
8001cfc: 697b ldr r3, [r7, #20]
|
|
8001cfe: 68d9 ldr r1, [r3, #12]
|
|
(uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4));
|
|
8001d00: 69bb ldr r3, [r7, #24]
|
|
8001d02: 091b lsrs r3, r3, #4
|
|
8001d04: b29b uxth r3, r3
|
|
(void)USB_ReadPacket(USBx, ep->xfer_buff,
|
|
8001d06: f3c3 030a ubfx r3, r3, #0, #11
|
|
8001d0a: b29b uxth r3, r3
|
|
8001d0c: 461a mov r2, r3
|
|
8001d0e: 6a38 ldr r0, [r7, #32]
|
|
8001d10: f004 f91e bl 8005f50 <USB_ReadPacket>
|
|
|
|
ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8001d14: 697b ldr r3, [r7, #20]
|
|
8001d16: 68da ldr r2, [r3, #12]
|
|
8001d18: 69bb ldr r3, [r7, #24]
|
|
8001d1a: 091b lsrs r3, r3, #4
|
|
8001d1c: f3c3 030a ubfx r3, r3, #0, #11
|
|
8001d20: 441a add r2, r3
|
|
8001d22: 697b ldr r3, [r7, #20]
|
|
8001d24: 60da str r2, [r3, #12]
|
|
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8001d26: 697b ldr r3, [r7, #20]
|
|
8001d28: 695a ldr r2, [r3, #20]
|
|
8001d2a: 69bb ldr r3, [r7, #24]
|
|
8001d2c: 091b lsrs r3, r3, #4
|
|
8001d2e: f3c3 030a ubfx r3, r3, #0, #11
|
|
8001d32: 441a add r2, r3
|
|
8001d34: 697b ldr r3, [r7, #20]
|
|
8001d36: 615a str r2, [r3, #20]
|
|
8001d38: e016 b.n 8001d68 <HAL_PCD_IRQHandler+0x136>
|
|
}
|
|
}
|
|
else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
|
|
8001d3a: 69bb ldr r3, [r7, #24]
|
|
8001d3c: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
|
|
8001d40: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000
|
|
8001d44: d110 bne.n 8001d68 <HAL_PCD_IRQHandler+0x136>
|
|
{
|
|
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
|
|
8001d46: 687b ldr r3, [r7, #4]
|
|
8001d48: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8001d4c: 2208 movs r2, #8
|
|
8001d4e: 4619 mov r1, r3
|
|
8001d50: 6a38 ldr r0, [r7, #32]
|
|
8001d52: f004 f8fd bl 8005f50 <USB_ReadPacket>
|
|
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8001d56: 697b ldr r3, [r7, #20]
|
|
8001d58: 695a ldr r2, [r3, #20]
|
|
8001d5a: 69bb ldr r3, [r7, #24]
|
|
8001d5c: 091b lsrs r3, r3, #4
|
|
8001d5e: f3c3 030a ubfx r3, r3, #0, #11
|
|
8001d62: 441a add r2, r3
|
|
8001d64: 697b ldr r3, [r7, #20]
|
|
8001d66: 615a str r2, [r3, #20]
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
|
|
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
8001d68: 687b ldr r3, [r7, #4]
|
|
8001d6a: 681b ldr r3, [r3, #0]
|
|
8001d6c: 699a ldr r2, [r3, #24]
|
|
8001d6e: 687b ldr r3, [r7, #4]
|
|
8001d70: 681b ldr r3, [r3, #0]
|
|
8001d72: f042 0210 orr.w r2, r2, #16
|
|
8001d76: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
|
|
8001d78: 687b ldr r3, [r7, #4]
|
|
8001d7a: 681b ldr r3, [r3, #0]
|
|
8001d7c: 4618 mov r0, r3
|
|
8001d7e: f004 fa7b bl 8006278 <USB_ReadInterrupts>
|
|
8001d82: 4603 mov r3, r0
|
|
8001d84: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8001d88: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
|
|
8001d8c: f040 80a7 bne.w 8001ede <HAL_PCD_IRQHandler+0x2ac>
|
|
{
|
|
epnum = 0U;
|
|
8001d90: 2300 movs r3, #0
|
|
8001d92: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Read in the device interrupt bits */
|
|
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
|
|
8001d94: 687b ldr r3, [r7, #4]
|
|
8001d96: 681b ldr r3, [r3, #0]
|
|
8001d98: 4618 mov r0, r3
|
|
8001d9a: f004 fa80 bl 800629e <USB_ReadDevAllOutEpInterrupt>
|
|
8001d9e: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
while (ep_intr != 0U)
|
|
8001da0: e099 b.n 8001ed6 <HAL_PCD_IRQHandler+0x2a4>
|
|
{
|
|
if ((ep_intr & 0x1U) != 0U)
|
|
8001da2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8001da4: f003 0301 and.w r3, r3, #1
|
|
8001da8: 2b00 cmp r3, #0
|
|
8001daa: f000 808e beq.w 8001eca <HAL_PCD_IRQHandler+0x298>
|
|
{
|
|
epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
|
|
8001dae: 687b ldr r3, [r7, #4]
|
|
8001db0: 681b ldr r3, [r3, #0]
|
|
8001db2: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8001db4: b2d2 uxtb r2, r2
|
|
8001db6: 4611 mov r1, r2
|
|
8001db8: 4618 mov r0, r3
|
|
8001dba: f004 faa4 bl 8006306 <USB_ReadDevOutEPInterrupt>
|
|
8001dbe: 6138 str r0, [r7, #16]
|
|
|
|
if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
|
|
8001dc0: 693b ldr r3, [r7, #16]
|
|
8001dc2: f003 0301 and.w r3, r3, #1
|
|
8001dc6: 2b00 cmp r3, #0
|
|
8001dc8: d00c beq.n 8001de4 <HAL_PCD_IRQHandler+0x1b2>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
|
|
8001dca: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001dcc: 015a lsls r2, r3, #5
|
|
8001dce: 69fb ldr r3, [r7, #28]
|
|
8001dd0: 4413 add r3, r2
|
|
8001dd2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8001dd6: 461a mov r2, r3
|
|
8001dd8: 2301 movs r3, #1
|
|
8001dda: 6093 str r3, [r2, #8]
|
|
(void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
|
|
8001ddc: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8001dde: 6878 ldr r0, [r7, #4]
|
|
8001de0: f000 feb8 bl 8002b54 <PCD_EP_OutXfrComplete_int>
|
|
}
|
|
|
|
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
|
|
8001de4: 693b ldr r3, [r7, #16]
|
|
8001de6: f003 0308 and.w r3, r3, #8
|
|
8001dea: 2b00 cmp r3, #0
|
|
8001dec: d00c beq.n 8001e08 <HAL_PCD_IRQHandler+0x1d6>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
|
|
8001dee: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001df0: 015a lsls r2, r3, #5
|
|
8001df2: 69fb ldr r3, [r7, #28]
|
|
8001df4: 4413 add r3, r2
|
|
8001df6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8001dfa: 461a mov r2, r3
|
|
8001dfc: 2308 movs r3, #8
|
|
8001dfe: 6093 str r3, [r2, #8]
|
|
/* Class B setup phase done for previous decoded setup */
|
|
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
|
|
8001e00: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8001e02: 6878 ldr r0, [r7, #4]
|
|
8001e04: f000 ff8e bl 8002d24 <PCD_EP_OutSetupPacket_int>
|
|
}
|
|
|
|
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
|
|
8001e08: 693b ldr r3, [r7, #16]
|
|
8001e0a: f003 0310 and.w r3, r3, #16
|
|
8001e0e: 2b00 cmp r3, #0
|
|
8001e10: d008 beq.n 8001e24 <HAL_PCD_IRQHandler+0x1f2>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
|
|
8001e12: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001e14: 015a lsls r2, r3, #5
|
|
8001e16: 69fb ldr r3, [r7, #28]
|
|
8001e18: 4413 add r3, r2
|
|
8001e1a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8001e1e: 461a mov r2, r3
|
|
8001e20: 2310 movs r3, #16
|
|
8001e22: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear OUT Endpoint disable interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
|
|
8001e24: 693b ldr r3, [r7, #16]
|
|
8001e26: f003 0302 and.w r3, r3, #2
|
|
8001e2a: 2b00 cmp r3, #0
|
|
8001e2c: d030 beq.n 8001e90 <HAL_PCD_IRQHandler+0x25e>
|
|
{
|
|
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF)
|
|
8001e2e: 6a3b ldr r3, [r7, #32]
|
|
8001e30: 695b ldr r3, [r3, #20]
|
|
8001e32: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8001e36: 2b80 cmp r3, #128 @ 0x80
|
|
8001e38: d109 bne.n 8001e4e <HAL_PCD_IRQHandler+0x21c>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
|
|
8001e3a: 69fb ldr r3, [r7, #28]
|
|
8001e3c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8001e40: 685b ldr r3, [r3, #4]
|
|
8001e42: 69fa ldr r2, [r7, #28]
|
|
8001e44: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8001e48: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8001e4c: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
ep = &hpcd->OUT_ep[epnum];
|
|
8001e4e: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8001e50: 4613 mov r3, r2
|
|
8001e52: 00db lsls r3, r3, #3
|
|
8001e54: 4413 add r3, r2
|
|
8001e56: 009b lsls r3, r3, #2
|
|
8001e58: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8001e5c: 687a ldr r2, [r7, #4]
|
|
8001e5e: 4413 add r3, r2
|
|
8001e60: 3304 adds r3, #4
|
|
8001e62: 617b str r3, [r7, #20]
|
|
|
|
if (ep->is_iso_incomplete == 1U)
|
|
8001e64: 697b ldr r3, [r7, #20]
|
|
8001e66: 78db ldrb r3, [r3, #3]
|
|
8001e68: 2b01 cmp r3, #1
|
|
8001e6a: d108 bne.n 8001e7e <HAL_PCD_IRQHandler+0x24c>
|
|
{
|
|
ep->is_iso_incomplete = 0U;
|
|
8001e6c: 697b ldr r3, [r7, #20]
|
|
8001e6e: 2200 movs r2, #0
|
|
8001e70: 70da strb r2, [r3, #3]
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
8001e72: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001e74: b2db uxtb r3, r3
|
|
8001e76: 4619 mov r1, r3
|
|
8001e78: 6878 ldr r0, [r7, #4]
|
|
8001e7a: f006 fb0d bl 8008498 <HAL_PCD_ISOOUTIncompleteCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
|
|
8001e7e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001e80: 015a lsls r2, r3, #5
|
|
8001e82: 69fb ldr r3, [r7, #28]
|
|
8001e84: 4413 add r3, r2
|
|
8001e86: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8001e8a: 461a mov r2, r3
|
|
8001e8c: 2302 movs r3, #2
|
|
8001e8e: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear Status Phase Received interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
|
|
8001e90: 693b ldr r3, [r7, #16]
|
|
8001e92: f003 0320 and.w r3, r3, #32
|
|
8001e96: 2b00 cmp r3, #0
|
|
8001e98: d008 beq.n 8001eac <HAL_PCD_IRQHandler+0x27a>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
8001e9a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001e9c: 015a lsls r2, r3, #5
|
|
8001e9e: 69fb ldr r3, [r7, #28]
|
|
8001ea0: 4413 add r3, r2
|
|
8001ea2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8001ea6: 461a mov r2, r3
|
|
8001ea8: 2320 movs r3, #32
|
|
8001eaa: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear OUT NAK interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
|
|
8001eac: 693b ldr r3, [r7, #16]
|
|
8001eae: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
8001eb2: 2b00 cmp r3, #0
|
|
8001eb4: d009 beq.n 8001eca <HAL_PCD_IRQHandler+0x298>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
|
|
8001eb6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001eb8: 015a lsls r2, r3, #5
|
|
8001eba: 69fb ldr r3, [r7, #28]
|
|
8001ebc: 4413 add r3, r2
|
|
8001ebe: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8001ec2: 461a mov r2, r3
|
|
8001ec4: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
8001ec8: 6093 str r3, [r2, #8]
|
|
}
|
|
}
|
|
epnum++;
|
|
8001eca: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001ecc: 3301 adds r3, #1
|
|
8001ece: 627b str r3, [r7, #36] @ 0x24
|
|
ep_intr >>= 1U;
|
|
8001ed0: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8001ed2: 085b lsrs r3, r3, #1
|
|
8001ed4: 62bb str r3, [r7, #40] @ 0x28
|
|
while (ep_intr != 0U)
|
|
8001ed6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8001ed8: 2b00 cmp r3, #0
|
|
8001eda: f47f af62 bne.w 8001da2 <HAL_PCD_IRQHandler+0x170>
|
|
}
|
|
}
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
|
|
8001ede: 687b ldr r3, [r7, #4]
|
|
8001ee0: 681b ldr r3, [r3, #0]
|
|
8001ee2: 4618 mov r0, r3
|
|
8001ee4: f004 f9c8 bl 8006278 <USB_ReadInterrupts>
|
|
8001ee8: 4603 mov r3, r0
|
|
8001eea: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8001eee: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
8001ef2: f040 80db bne.w 80020ac <HAL_PCD_IRQHandler+0x47a>
|
|
{
|
|
/* Read in the device interrupt bits */
|
|
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
|
|
8001ef6: 687b ldr r3, [r7, #4]
|
|
8001ef8: 681b ldr r3, [r3, #0]
|
|
8001efa: 4618 mov r0, r3
|
|
8001efc: f004 f9e9 bl 80062d2 <USB_ReadDevAllInEpInterrupt>
|
|
8001f00: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
epnum = 0U;
|
|
8001f02: 2300 movs r3, #0
|
|
8001f04: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
while (ep_intr != 0U)
|
|
8001f06: e0cd b.n 80020a4 <HAL_PCD_IRQHandler+0x472>
|
|
{
|
|
if ((ep_intr & 0x1U) != 0U) /* In ITR */
|
|
8001f08: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8001f0a: f003 0301 and.w r3, r3, #1
|
|
8001f0e: 2b00 cmp r3, #0
|
|
8001f10: f000 80c2 beq.w 8002098 <HAL_PCD_IRQHandler+0x466>
|
|
{
|
|
epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
|
|
8001f14: 687b ldr r3, [r7, #4]
|
|
8001f16: 681b ldr r3, [r3, #0]
|
|
8001f18: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8001f1a: b2d2 uxtb r2, r2
|
|
8001f1c: 4611 mov r1, r2
|
|
8001f1e: 4618 mov r0, r3
|
|
8001f20: f004 fa0f bl 8006342 <USB_ReadDevInEPInterrupt>
|
|
8001f24: 6138 str r0, [r7, #16]
|
|
|
|
if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
|
|
8001f26: 693b ldr r3, [r7, #16]
|
|
8001f28: f003 0301 and.w r3, r3, #1
|
|
8001f2c: 2b00 cmp r3, #0
|
|
8001f2e: d057 beq.n 8001fe0 <HAL_PCD_IRQHandler+0x3ae>
|
|
{
|
|
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
|
|
8001f30: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001f32: f003 030f and.w r3, r3, #15
|
|
8001f36: 2201 movs r2, #1
|
|
8001f38: fa02 f303 lsl.w r3, r2, r3
|
|
8001f3c: 60fb str r3, [r7, #12]
|
|
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
|
|
8001f3e: 69fb ldr r3, [r7, #28]
|
|
8001f40: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8001f44: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8001f46: 68fb ldr r3, [r7, #12]
|
|
8001f48: 43db mvns r3, r3
|
|
8001f4a: 69f9 ldr r1, [r7, #28]
|
|
8001f4c: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8001f50: 4013 ands r3, r2
|
|
8001f52: 634b str r3, [r1, #52] @ 0x34
|
|
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
|
|
8001f54: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001f56: 015a lsls r2, r3, #5
|
|
8001f58: 69fb ldr r3, [r7, #28]
|
|
8001f5a: 4413 add r3, r2
|
|
8001f5c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8001f60: 461a mov r2, r3
|
|
8001f62: 2301 movs r3, #1
|
|
8001f64: 6093 str r3, [r2, #8]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8001f66: 687b ldr r3, [r7, #4]
|
|
8001f68: 799b ldrb r3, [r3, #6]
|
|
8001f6a: 2b01 cmp r3, #1
|
|
8001f6c: d132 bne.n 8001fd4 <HAL_PCD_IRQHandler+0x3a2>
|
|
{
|
|
hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
|
|
8001f6e: 6879 ldr r1, [r7, #4]
|
|
8001f70: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8001f72: 4613 mov r3, r2
|
|
8001f74: 00db lsls r3, r3, #3
|
|
8001f76: 4413 add r3, r2
|
|
8001f78: 009b lsls r3, r3, #2
|
|
8001f7a: 440b add r3, r1
|
|
8001f7c: 3320 adds r3, #32
|
|
8001f7e: 6819 ldr r1, [r3, #0]
|
|
8001f80: 6878 ldr r0, [r7, #4]
|
|
8001f82: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8001f84: 4613 mov r3, r2
|
|
8001f86: 00db lsls r3, r3, #3
|
|
8001f88: 4413 add r3, r2
|
|
8001f8a: 009b lsls r3, r3, #2
|
|
8001f8c: 4403 add r3, r0
|
|
8001f8e: 331c adds r3, #28
|
|
8001f90: 681b ldr r3, [r3, #0]
|
|
8001f92: 4419 add r1, r3
|
|
8001f94: 6878 ldr r0, [r7, #4]
|
|
8001f96: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8001f98: 4613 mov r3, r2
|
|
8001f9a: 00db lsls r3, r3, #3
|
|
8001f9c: 4413 add r3, r2
|
|
8001f9e: 009b lsls r3, r3, #2
|
|
8001fa0: 4403 add r3, r0
|
|
8001fa2: 3320 adds r3, #32
|
|
8001fa4: 6019 str r1, [r3, #0]
|
|
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
|
|
8001fa6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001fa8: 2b00 cmp r3, #0
|
|
8001faa: d113 bne.n 8001fd4 <HAL_PCD_IRQHandler+0x3a2>
|
|
8001fac: 6879 ldr r1, [r7, #4]
|
|
8001fae: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8001fb0: 4613 mov r3, r2
|
|
8001fb2: 00db lsls r3, r3, #3
|
|
8001fb4: 4413 add r3, r2
|
|
8001fb6: 009b lsls r3, r3, #2
|
|
8001fb8: 440b add r3, r1
|
|
8001fba: 3324 adds r3, #36 @ 0x24
|
|
8001fbc: 681b ldr r3, [r3, #0]
|
|
8001fbe: 2b00 cmp r3, #0
|
|
8001fc0: d108 bne.n 8001fd4 <HAL_PCD_IRQHandler+0x3a2>
|
|
{
|
|
/* prepare to rx more setup packets */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
8001fc2: 687b ldr r3, [r7, #4]
|
|
8001fc4: 6818 ldr r0, [r3, #0]
|
|
8001fc6: 687b ldr r3, [r7, #4]
|
|
8001fc8: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8001fcc: 461a mov r2, r3
|
|
8001fce: 2101 movs r1, #1
|
|
8001fd0: f004 fa16 bl 8006400 <USB_EP0_OutStart>
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
|
|
8001fd4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001fd6: b2db uxtb r3, r3
|
|
8001fd8: 4619 mov r1, r3
|
|
8001fda: 6878 ldr r0, [r7, #4]
|
|
8001fdc: f006 f9d7 bl 800838e <HAL_PCD_DataInStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
|
|
8001fe0: 693b ldr r3, [r7, #16]
|
|
8001fe2: f003 0308 and.w r3, r3, #8
|
|
8001fe6: 2b00 cmp r3, #0
|
|
8001fe8: d008 beq.n 8001ffc <HAL_PCD_IRQHandler+0x3ca>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
|
|
8001fea: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001fec: 015a lsls r2, r3, #5
|
|
8001fee: 69fb ldr r3, [r7, #28]
|
|
8001ff0: 4413 add r3, r2
|
|
8001ff2: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8001ff6: 461a mov r2, r3
|
|
8001ff8: 2308 movs r3, #8
|
|
8001ffa: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
|
|
8001ffc: 693b ldr r3, [r7, #16]
|
|
8001ffe: f003 0310 and.w r3, r3, #16
|
|
8002002: 2b00 cmp r3, #0
|
|
8002004: d008 beq.n 8002018 <HAL_PCD_IRQHandler+0x3e6>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
|
|
8002006: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002008: 015a lsls r2, r3, #5
|
|
800200a: 69fb ldr r3, [r7, #28]
|
|
800200c: 4413 add r3, r2
|
|
800200e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002012: 461a mov r2, r3
|
|
8002014: 2310 movs r3, #16
|
|
8002016: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
|
|
8002018: 693b ldr r3, [r7, #16]
|
|
800201a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800201e: 2b00 cmp r3, #0
|
|
8002020: d008 beq.n 8002034 <HAL_PCD_IRQHandler+0x402>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
|
|
8002022: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002024: 015a lsls r2, r3, #5
|
|
8002026: 69fb ldr r3, [r7, #28]
|
|
8002028: 4413 add r3, r2
|
|
800202a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800202e: 461a mov r2, r3
|
|
8002030: 2340 movs r3, #64 @ 0x40
|
|
8002032: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
|
|
8002034: 693b ldr r3, [r7, #16]
|
|
8002036: f003 0302 and.w r3, r3, #2
|
|
800203a: 2b00 cmp r3, #0
|
|
800203c: d023 beq.n 8002086 <HAL_PCD_IRQHandler+0x454>
|
|
{
|
|
(void)USB_FlushTxFifo(USBx, epnum);
|
|
800203e: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8002040: 6a38 ldr r0, [r7, #32]
|
|
8002042: f003 f9fd bl 8005440 <USB_FlushTxFifo>
|
|
|
|
ep = &hpcd->IN_ep[epnum];
|
|
8002046: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002048: 4613 mov r3, r2
|
|
800204a: 00db lsls r3, r3, #3
|
|
800204c: 4413 add r3, r2
|
|
800204e: 009b lsls r3, r3, #2
|
|
8002050: 3310 adds r3, #16
|
|
8002052: 687a ldr r2, [r7, #4]
|
|
8002054: 4413 add r3, r2
|
|
8002056: 3304 adds r3, #4
|
|
8002058: 617b str r3, [r7, #20]
|
|
|
|
if (ep->is_iso_incomplete == 1U)
|
|
800205a: 697b ldr r3, [r7, #20]
|
|
800205c: 78db ldrb r3, [r3, #3]
|
|
800205e: 2b01 cmp r3, #1
|
|
8002060: d108 bne.n 8002074 <HAL_PCD_IRQHandler+0x442>
|
|
{
|
|
ep->is_iso_incomplete = 0U;
|
|
8002062: 697b ldr r3, [r7, #20]
|
|
8002064: 2200 movs r2, #0
|
|
8002066: 70da strb r2, [r3, #3]
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
8002068: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800206a: b2db uxtb r3, r3
|
|
800206c: 4619 mov r1, r3
|
|
800206e: 6878 ldr r0, [r7, #4]
|
|
8002070: f006 fa24 bl 80084bc <HAL_PCD_ISOINIncompleteCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
|
|
8002074: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002076: 015a lsls r2, r3, #5
|
|
8002078: 69fb ldr r3, [r7, #28]
|
|
800207a: 4413 add r3, r2
|
|
800207c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002080: 461a mov r2, r3
|
|
8002082: 2302 movs r3, #2
|
|
8002084: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
|
|
8002086: 693b ldr r3, [r7, #16]
|
|
8002088: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800208c: 2b00 cmp r3, #0
|
|
800208e: d003 beq.n 8002098 <HAL_PCD_IRQHandler+0x466>
|
|
{
|
|
(void)PCD_WriteEmptyTxFifo(hpcd, epnum);
|
|
8002090: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8002092: 6878 ldr r0, [r7, #4]
|
|
8002094: f000 fcd2 bl 8002a3c <PCD_WriteEmptyTxFifo>
|
|
}
|
|
}
|
|
epnum++;
|
|
8002098: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800209a: 3301 adds r3, #1
|
|
800209c: 627b str r3, [r7, #36] @ 0x24
|
|
ep_intr >>= 1U;
|
|
800209e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80020a0: 085b lsrs r3, r3, #1
|
|
80020a2: 62bb str r3, [r7, #40] @ 0x28
|
|
while (ep_intr != 0U)
|
|
80020a4: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80020a6: 2b00 cmp r3, #0
|
|
80020a8: f47f af2e bne.w 8001f08 <HAL_PCD_IRQHandler+0x2d6>
|
|
}
|
|
}
|
|
|
|
/* Handle Resume Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
|
|
80020ac: 687b ldr r3, [r7, #4]
|
|
80020ae: 681b ldr r3, [r3, #0]
|
|
80020b0: 4618 mov r0, r3
|
|
80020b2: f004 f8e1 bl 8006278 <USB_ReadInterrupts>
|
|
80020b6: 4603 mov r3, r0
|
|
80020b8: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80020bc: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80020c0: d122 bne.n 8002108 <HAL_PCD_IRQHandler+0x4d6>
|
|
{
|
|
/* Clear the Remote Wake-up Signaling */
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
|
|
80020c2: 69fb ldr r3, [r7, #28]
|
|
80020c4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80020c8: 685b ldr r3, [r3, #4]
|
|
80020ca: 69fa ldr r2, [r7, #28]
|
|
80020cc: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80020d0: f023 0301 bic.w r3, r3, #1
|
|
80020d4: 6053 str r3, [r2, #4]
|
|
|
|
if (hpcd->LPM_State == LPM_L1)
|
|
80020d6: 687b ldr r3, [r7, #4]
|
|
80020d8: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
|
|
80020dc: 2b01 cmp r3, #1
|
|
80020de: d108 bne.n 80020f2 <HAL_PCD_IRQHandler+0x4c0>
|
|
{
|
|
hpcd->LPM_State = LPM_L0;
|
|
80020e0: 687b ldr r3, [r7, #4]
|
|
80020e2: 2200 movs r2, #0
|
|
80020e4: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
|
|
#else
|
|
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
|
|
80020e8: 2100 movs r1, #0
|
|
80020ea: 6878 ldr r0, [r7, #4]
|
|
80020ec: f006 fb8c bl 8008808 <HAL_PCDEx_LPM_Callback>
|
|
80020f0: e002 b.n 80020f8 <HAL_PCD_IRQHandler+0x4c6>
|
|
else
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResumeCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResumeCallback(hpcd);
|
|
80020f2: 6878 ldr r0, [r7, #4]
|
|
80020f4: f006 f9c2 bl 800847c <HAL_PCD_ResumeCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
|
|
80020f8: 687b ldr r3, [r7, #4]
|
|
80020fa: 681b ldr r3, [r3, #0]
|
|
80020fc: 695a ldr r2, [r3, #20]
|
|
80020fe: 687b ldr r3, [r7, #4]
|
|
8002100: 681b ldr r3, [r3, #0]
|
|
8002102: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000
|
|
8002106: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Suspend Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
|
|
8002108: 687b ldr r3, [r7, #4]
|
|
800210a: 681b ldr r3, [r3, #0]
|
|
800210c: 4618 mov r0, r3
|
|
800210e: f004 f8b3 bl 8006278 <USB_ReadInterrupts>
|
|
8002112: 4603 mov r3, r0
|
|
8002114: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8002118: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
800211c: d112 bne.n 8002144 <HAL_PCD_IRQHandler+0x512>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
|
|
800211e: 69fb ldr r3, [r7, #28]
|
|
8002120: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002124: 689b ldr r3, [r3, #8]
|
|
8002126: f003 0301 and.w r3, r3, #1
|
|
800212a: 2b01 cmp r3, #1
|
|
800212c: d102 bne.n 8002134 <HAL_PCD_IRQHandler+0x502>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SuspendCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
800212e: 6878 ldr r0, [r7, #4]
|
|
8002130: f006 f97e bl 8008430 <HAL_PCD_SuspendCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
|
|
8002134: 687b ldr r3, [r7, #4]
|
|
8002136: 681b ldr r3, [r3, #0]
|
|
8002138: 695a ldr r2, [r3, #20]
|
|
800213a: 687b ldr r3, [r7, #4]
|
|
800213c: 681b ldr r3, [r3, #0]
|
|
800213e: f402 6200 and.w r2, r2, #2048 @ 0x800
|
|
8002142: 615a str r2, [r3, #20]
|
|
}
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* Handle LPM Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
|
|
8002144: 687b ldr r3, [r7, #4]
|
|
8002146: 681b ldr r3, [r3, #0]
|
|
8002148: 4618 mov r0, r3
|
|
800214a: f004 f895 bl 8006278 <USB_ReadInterrupts>
|
|
800214e: 4603 mov r3, r0
|
|
8002150: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8002154: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8002158: d121 bne.n 800219e <HAL_PCD_IRQHandler+0x56c>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
|
|
800215a: 687b ldr r3, [r7, #4]
|
|
800215c: 681b ldr r3, [r3, #0]
|
|
800215e: 695a ldr r2, [r3, #20]
|
|
8002160: 687b ldr r3, [r7, #4]
|
|
8002162: 681b ldr r3, [r3, #0]
|
|
8002164: f002 6200 and.w r2, r2, #134217728 @ 0x8000000
|
|
8002168: 615a str r2, [r3, #20]
|
|
|
|
if (hpcd->LPM_State == LPM_L0)
|
|
800216a: 687b ldr r3, [r7, #4]
|
|
800216c: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
|
|
8002170: 2b00 cmp r3, #0
|
|
8002172: d111 bne.n 8002198 <HAL_PCD_IRQHandler+0x566>
|
|
{
|
|
hpcd->LPM_State = LPM_L1;
|
|
8002174: 687b ldr r3, [r7, #4]
|
|
8002176: 2201 movs r2, #1
|
|
8002178: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
|
|
800217c: 687b ldr r3, [r7, #4]
|
|
800217e: 681b ldr r3, [r3, #0]
|
|
8002180: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8002182: 089b lsrs r3, r3, #2
|
|
8002184: f003 020f and.w r2, r3, #15
|
|
8002188: 687b ldr r3, [r7, #4]
|
|
800218a: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
|
|
#else
|
|
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
|
|
800218e: 2101 movs r1, #1
|
|
8002190: 6878 ldr r0, [r7, #4]
|
|
8002192: f006 fb39 bl 8008808 <HAL_PCDEx_LPM_Callback>
|
|
8002196: e002 b.n 800219e <HAL_PCD_IRQHandler+0x56c>
|
|
else
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SuspendCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
8002198: 6878 ldr r0, [r7, #4]
|
|
800219a: f006 f949 bl 8008430 <HAL_PCD_SuspendCallback>
|
|
}
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
/* Handle Reset Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
|
|
800219e: 687b ldr r3, [r7, #4]
|
|
80021a0: 681b ldr r3, [r3, #0]
|
|
80021a2: 4618 mov r0, r3
|
|
80021a4: f004 f868 bl 8006278 <USB_ReadInterrupts>
|
|
80021a8: 4603 mov r3, r0
|
|
80021aa: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
80021ae: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
80021b2: f040 80b7 bne.w 8002324 <HAL_PCD_IRQHandler+0x6f2>
|
|
{
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
|
|
80021b6: 69fb ldr r3, [r7, #28]
|
|
80021b8: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80021bc: 685b ldr r3, [r3, #4]
|
|
80021be: 69fa ldr r2, [r7, #28]
|
|
80021c0: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80021c4: f023 0301 bic.w r3, r3, #1
|
|
80021c8: 6053 str r3, [r2, #4]
|
|
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
|
|
80021ca: 687b ldr r3, [r7, #4]
|
|
80021cc: 681b ldr r3, [r3, #0]
|
|
80021ce: 2110 movs r1, #16
|
|
80021d0: 4618 mov r0, r3
|
|
80021d2: f003 f935 bl 8005440 <USB_FlushTxFifo>
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
80021d6: 2300 movs r3, #0
|
|
80021d8: 62fb str r3, [r7, #44] @ 0x2c
|
|
80021da: e046 b.n 800226a <HAL_PCD_IRQHandler+0x638>
|
|
{
|
|
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
|
80021dc: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80021de: 015a lsls r2, r3, #5
|
|
80021e0: 69fb ldr r3, [r7, #28]
|
|
80021e2: 4413 add r3, r2
|
|
80021e4: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80021e8: 461a mov r2, r3
|
|
80021ea: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
80021ee: 6093 str r3, [r2, #8]
|
|
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
|
80021f0: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80021f2: 015a lsls r2, r3, #5
|
|
80021f4: 69fb ldr r3, [r7, #28]
|
|
80021f6: 4413 add r3, r2
|
|
80021f8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80021fc: 681b ldr r3, [r3, #0]
|
|
80021fe: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8002200: 0151 lsls r1, r2, #5
|
|
8002202: 69fa ldr r2, [r7, #28]
|
|
8002204: 440a add r2, r1
|
|
8002206: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800220a: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
800220e: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
|
8002210: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002212: 015a lsls r2, r3, #5
|
|
8002214: 69fb ldr r3, [r7, #28]
|
|
8002216: 4413 add r3, r2
|
|
8002218: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800221c: 461a mov r2, r3
|
|
800221e: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
8002222: 6093 str r3, [r2, #8]
|
|
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
|
8002224: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002226: 015a lsls r2, r3, #5
|
|
8002228: 69fb ldr r3, [r7, #28]
|
|
800222a: 4413 add r3, r2
|
|
800222c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002230: 681b ldr r3, [r3, #0]
|
|
8002232: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8002234: 0151 lsls r1, r2, #5
|
|
8002236: 69fa ldr r2, [r7, #28]
|
|
8002238: 440a add r2, r1
|
|
800223a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800223e: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
8002242: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
|
8002244: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002246: 015a lsls r2, r3, #5
|
|
8002248: 69fb ldr r3, [r7, #28]
|
|
800224a: 4413 add r3, r2
|
|
800224c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002250: 681b ldr r3, [r3, #0]
|
|
8002252: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8002254: 0151 lsls r1, r2, #5
|
|
8002256: 69fa ldr r2, [r7, #28]
|
|
8002258: 440a add r2, r1
|
|
800225a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800225e: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8002262: 6013 str r3, [r2, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8002264: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002266: 3301 adds r3, #1
|
|
8002268: 62fb str r3, [r7, #44] @ 0x2c
|
|
800226a: 687b ldr r3, [r7, #4]
|
|
800226c: 791b ldrb r3, [r3, #4]
|
|
800226e: 461a mov r2, r3
|
|
8002270: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002272: 4293 cmp r3, r2
|
|
8002274: d3b2 bcc.n 80021dc <HAL_PCD_IRQHandler+0x5aa>
|
|
}
|
|
USBx_DEVICE->DAINTMSK |= 0x10001U;
|
|
8002276: 69fb ldr r3, [r7, #28]
|
|
8002278: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800227c: 69db ldr r3, [r3, #28]
|
|
800227e: 69fa ldr r2, [r7, #28]
|
|
8002280: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8002284: f043 1301 orr.w r3, r3, #65537 @ 0x10001
|
|
8002288: 61d3 str r3, [r2, #28]
|
|
|
|
if (hpcd->Init.use_dedicated_ep1 != 0U)
|
|
800228a: 687b ldr r3, [r7, #4]
|
|
800228c: 7bdb ldrb r3, [r3, #15]
|
|
800228e: 2b00 cmp r3, #0
|
|
8002290: d016 beq.n 80022c0 <HAL_PCD_IRQHandler+0x68e>
|
|
{
|
|
USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
|
|
8002292: 69fb ldr r3, [r7, #28]
|
|
8002294: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002298: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
800229c: 69fa ldr r2, [r7, #28]
|
|
800229e: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80022a2: f043 030b orr.w r3, r3, #11
|
|
80022a6: f8c2 3084 str.w r3, [r2, #132] @ 0x84
|
|
USB_OTG_DOEPMSK_XFRCM |
|
|
USB_OTG_DOEPMSK_EPDM;
|
|
|
|
USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
|
|
80022aa: 69fb ldr r3, [r7, #28]
|
|
80022ac: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80022b0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80022b2: 69fa ldr r2, [r7, #28]
|
|
80022b4: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80022b8: f043 030b orr.w r3, r3, #11
|
|
80022bc: 6453 str r3, [r2, #68] @ 0x44
|
|
80022be: e015 b.n 80022ec <HAL_PCD_IRQHandler+0x6ba>
|
|
USB_OTG_DIEPMSK_XFRCM |
|
|
USB_OTG_DIEPMSK_EPDM;
|
|
}
|
|
else
|
|
{
|
|
USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
|
|
80022c0: 69fb ldr r3, [r7, #28]
|
|
80022c2: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80022c6: 695b ldr r3, [r3, #20]
|
|
80022c8: 69fa ldr r2, [r7, #28]
|
|
80022ca: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80022ce: f443 5300 orr.w r3, r3, #8192 @ 0x2000
|
|
80022d2: f043 032b orr.w r3, r3, #43 @ 0x2b
|
|
80022d6: 6153 str r3, [r2, #20]
|
|
USB_OTG_DOEPMSK_XFRCM |
|
|
USB_OTG_DOEPMSK_EPDM |
|
|
USB_OTG_DOEPMSK_OTEPSPRM |
|
|
USB_OTG_DOEPMSK_NAKM;
|
|
|
|
USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
|
|
80022d8: 69fb ldr r3, [r7, #28]
|
|
80022da: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80022de: 691b ldr r3, [r3, #16]
|
|
80022e0: 69fa ldr r2, [r7, #28]
|
|
80022e2: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80022e6: f043 030b orr.w r3, r3, #11
|
|
80022ea: 6113 str r3, [r2, #16]
|
|
USB_OTG_DIEPMSK_XFRCM |
|
|
USB_OTG_DIEPMSK_EPDM;
|
|
}
|
|
|
|
/* Set Default Address to 0 */
|
|
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
|
|
80022ec: 69fb ldr r3, [r7, #28]
|
|
80022ee: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80022f2: 681b ldr r3, [r3, #0]
|
|
80022f4: 69fa ldr r2, [r7, #28]
|
|
80022f6: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80022fa: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
|
|
80022fe: 6013 str r3, [r2, #0]
|
|
|
|
/* setup EP0 to receive SETUP packets */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
|
|
8002300: 687b ldr r3, [r7, #4]
|
|
8002302: 6818 ldr r0, [r3, #0]
|
|
8002304: 687b ldr r3, [r7, #4]
|
|
8002306: 7999 ldrb r1, [r3, #6]
|
|
(uint8_t *)hpcd->Setup);
|
|
8002308: 687b ldr r3, [r7, #4]
|
|
800230a: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
|
|
800230e: 461a mov r2, r3
|
|
8002310: f004 f876 bl 8006400 <USB_EP0_OutStart>
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
|
|
8002314: 687b ldr r3, [r7, #4]
|
|
8002316: 681b ldr r3, [r3, #0]
|
|
8002318: 695a ldr r2, [r3, #20]
|
|
800231a: 687b ldr r3, [r7, #4]
|
|
800231c: 681b ldr r3, [r3, #0]
|
|
800231e: f402 5280 and.w r2, r2, #4096 @ 0x1000
|
|
8002322: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Enumeration done Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
|
|
8002324: 687b ldr r3, [r7, #4]
|
|
8002326: 681b ldr r3, [r3, #0]
|
|
8002328: 4618 mov r0, r3
|
|
800232a: f003 ffa5 bl 8006278 <USB_ReadInterrupts>
|
|
800232e: 4603 mov r3, r0
|
|
8002330: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
8002334: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
8002338: d123 bne.n 8002382 <HAL_PCD_IRQHandler+0x750>
|
|
{
|
|
(void)USB_ActivateSetup(hpcd->Instance);
|
|
800233a: 687b ldr r3, [r7, #4]
|
|
800233c: 681b ldr r3, [r3, #0]
|
|
800233e: 4618 mov r0, r3
|
|
8002340: f004 f83b bl 80063ba <USB_ActivateSetup>
|
|
hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
|
|
8002344: 687b ldr r3, [r7, #4]
|
|
8002346: 681b ldr r3, [r3, #0]
|
|
8002348: 4618 mov r0, r3
|
|
800234a: f003 f8f2 bl 8005532 <USB_GetDevSpeed>
|
|
800234e: 4603 mov r3, r0
|
|
8002350: 461a mov r2, r3
|
|
8002352: 687b ldr r3, [r7, #4]
|
|
8002354: 71da strb r2, [r3, #7]
|
|
|
|
/* Set USB Turnaround time */
|
|
(void)USB_SetTurnaroundTime(hpcd->Instance,
|
|
8002356: 687b ldr r3, [r7, #4]
|
|
8002358: 681c ldr r4, [r3, #0]
|
|
800235a: f000 fe8b bl 8003074 <HAL_RCC_GetHCLKFreq>
|
|
800235e: 4601 mov r1, r0
|
|
HAL_RCC_GetHCLKFreq(),
|
|
(uint8_t)hpcd->Init.speed);
|
|
8002360: 687b ldr r3, [r7, #4]
|
|
8002362: 79db ldrb r3, [r3, #7]
|
|
(void)USB_SetTurnaroundTime(hpcd->Instance,
|
|
8002364: 461a mov r2, r3
|
|
8002366: 4620 mov r0, r4
|
|
8002368: f002 fdfc bl 8004f64 <USB_SetTurnaroundTime>
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResetCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResetCallback(hpcd);
|
|
800236c: 6878 ldr r0, [r7, #4]
|
|
800236e: f006 f836 bl 80083de <HAL_PCD_ResetCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
|
|
8002372: 687b ldr r3, [r7, #4]
|
|
8002374: 681b ldr r3, [r3, #0]
|
|
8002376: 695a ldr r2, [r3, #20]
|
|
8002378: 687b ldr r3, [r7, #4]
|
|
800237a: 681b ldr r3, [r3, #0]
|
|
800237c: f402 5200 and.w r2, r2, #8192 @ 0x2000
|
|
8002380: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle SOF Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
|
|
8002382: 687b ldr r3, [r7, #4]
|
|
8002384: 681b ldr r3, [r3, #0]
|
|
8002386: 4618 mov r0, r3
|
|
8002388: f003 ff76 bl 8006278 <USB_ReadInterrupts>
|
|
800238c: 4603 mov r3, r0
|
|
800238e: f003 0308 and.w r3, r3, #8
|
|
8002392: 2b08 cmp r3, #8
|
|
8002394: d10a bne.n 80023ac <HAL_PCD_IRQHandler+0x77a>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SOFCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SOFCallback(hpcd);
|
|
8002396: 6878 ldr r0, [r7, #4]
|
|
8002398: f006 f813 bl 80083c2 <HAL_PCD_SOFCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
|
|
800239c: 687b ldr r3, [r7, #4]
|
|
800239e: 681b ldr r3, [r3, #0]
|
|
80023a0: 695a ldr r2, [r3, #20]
|
|
80023a2: 687b ldr r3, [r7, #4]
|
|
80023a4: 681b ldr r3, [r3, #0]
|
|
80023a6: f002 0208 and.w r2, r2, #8
|
|
80023aa: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Global OUT NAK effective Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF))
|
|
80023ac: 687b ldr r3, [r7, #4]
|
|
80023ae: 681b ldr r3, [r3, #0]
|
|
80023b0: 4618 mov r0, r3
|
|
80023b2: f003 ff61 bl 8006278 <USB_ReadInterrupts>
|
|
80023b6: 4603 mov r3, r0
|
|
80023b8: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80023bc: 2b80 cmp r3, #128 @ 0x80
|
|
80023be: d123 bne.n 8002408 <HAL_PCD_IRQHandler+0x7d6>
|
|
{
|
|
USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM;
|
|
80023c0: 6a3b ldr r3, [r7, #32]
|
|
80023c2: 699b ldr r3, [r3, #24]
|
|
80023c4: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
80023c8: 6a3b ldr r3, [r7, #32]
|
|
80023ca: 619a str r2, [r3, #24]
|
|
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
80023cc: 2301 movs r3, #1
|
|
80023ce: 627b str r3, [r7, #36] @ 0x24
|
|
80023d0: e014 b.n 80023fc <HAL_PCD_IRQHandler+0x7ca>
|
|
{
|
|
if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U)
|
|
80023d2: 6879 ldr r1, [r7, #4]
|
|
80023d4: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80023d6: 4613 mov r3, r2
|
|
80023d8: 00db lsls r3, r3, #3
|
|
80023da: 4413 add r3, r2
|
|
80023dc: 009b lsls r3, r3, #2
|
|
80023de: 440b add r3, r1
|
|
80023e0: f203 2357 addw r3, r3, #599 @ 0x257
|
|
80023e4: 781b ldrb r3, [r3, #0]
|
|
80023e6: 2b01 cmp r3, #1
|
|
80023e8: d105 bne.n 80023f6 <HAL_PCD_IRQHandler+0x7c4>
|
|
{
|
|
/* Abort current transaction and disable the EP */
|
|
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum);
|
|
80023ea: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80023ec: b2db uxtb r3, r3
|
|
80023ee: 4619 mov r1, r3
|
|
80023f0: 6878 ldr r0, [r7, #4]
|
|
80023f2: f000 faf2 bl 80029da <HAL_PCD_EP_Abort>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
80023f6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80023f8: 3301 adds r3, #1
|
|
80023fa: 627b str r3, [r7, #36] @ 0x24
|
|
80023fc: 687b ldr r3, [r7, #4]
|
|
80023fe: 791b ldrb r3, [r3, #4]
|
|
8002400: 461a mov r2, r3
|
|
8002402: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002404: 4293 cmp r3, r2
|
|
8002406: d3e4 bcc.n 80023d2 <HAL_PCD_IRQHandler+0x7a0>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Handle Incomplete ISO IN Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
|
|
8002408: 687b ldr r3, [r7, #4]
|
|
800240a: 681b ldr r3, [r3, #0]
|
|
800240c: 4618 mov r0, r3
|
|
800240e: f003 ff33 bl 8006278 <USB_ReadInterrupts>
|
|
8002412: 4603 mov r3, r0
|
|
8002414: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8002418: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
800241c: d13c bne.n 8002498 <HAL_PCD_IRQHandler+0x866>
|
|
{
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
800241e: 2301 movs r3, #1
|
|
8002420: 627b str r3, [r7, #36] @ 0x24
|
|
8002422: e02b b.n 800247c <HAL_PCD_IRQHandler+0x84a>
|
|
{
|
|
RegVal = USBx_INEP(epnum)->DIEPCTL;
|
|
8002424: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002426: 015a lsls r2, r3, #5
|
|
8002428: 69fb ldr r3, [r7, #28]
|
|
800242a: 4413 add r3, r2
|
|
800242c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002430: 681b ldr r3, [r3, #0]
|
|
8002432: 61bb str r3, [r7, #24]
|
|
|
|
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
8002434: 6879 ldr r1, [r7, #4]
|
|
8002436: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002438: 4613 mov r3, r2
|
|
800243a: 00db lsls r3, r3, #3
|
|
800243c: 4413 add r3, r2
|
|
800243e: 009b lsls r3, r3, #2
|
|
8002440: 440b add r3, r1
|
|
8002442: 3318 adds r3, #24
|
|
8002444: 781b ldrb r3, [r3, #0]
|
|
8002446: 2b01 cmp r3, #1
|
|
8002448: d115 bne.n 8002476 <HAL_PCD_IRQHandler+0x844>
|
|
((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA))
|
|
800244a: 69bb ldr r3, [r7, #24]
|
|
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
800244c: 2b00 cmp r3, #0
|
|
800244e: da12 bge.n 8002476 <HAL_PCD_IRQHandler+0x844>
|
|
{
|
|
hpcd->IN_ep[epnum].is_iso_incomplete = 1U;
|
|
8002450: 6879 ldr r1, [r7, #4]
|
|
8002452: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002454: 4613 mov r3, r2
|
|
8002456: 00db lsls r3, r3, #3
|
|
8002458: 4413 add r3, r2
|
|
800245a: 009b lsls r3, r3, #2
|
|
800245c: 440b add r3, r1
|
|
800245e: 3317 adds r3, #23
|
|
8002460: 2201 movs r2, #1
|
|
8002462: 701a strb r2, [r3, #0]
|
|
|
|
/* Abort current transaction and disable the EP */
|
|
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U));
|
|
8002464: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002466: b2db uxtb r3, r3
|
|
8002468: f063 037f orn r3, r3, #127 @ 0x7f
|
|
800246c: b2db uxtb r3, r3
|
|
800246e: 4619 mov r1, r3
|
|
8002470: 6878 ldr r0, [r7, #4]
|
|
8002472: f000 fab2 bl 80029da <HAL_PCD_EP_Abort>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
8002476: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002478: 3301 adds r3, #1
|
|
800247a: 627b str r3, [r7, #36] @ 0x24
|
|
800247c: 687b ldr r3, [r7, #4]
|
|
800247e: 791b ldrb r3, [r3, #4]
|
|
8002480: 461a mov r2, r3
|
|
8002482: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002484: 4293 cmp r3, r2
|
|
8002486: d3cd bcc.n 8002424 <HAL_PCD_IRQHandler+0x7f2>
|
|
}
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
|
|
8002488: 687b ldr r3, [r7, #4]
|
|
800248a: 681b ldr r3, [r3, #0]
|
|
800248c: 695a ldr r2, [r3, #20]
|
|
800248e: 687b ldr r3, [r7, #4]
|
|
8002490: 681b ldr r3, [r3, #0]
|
|
8002492: f402 1280 and.w r2, r2, #1048576 @ 0x100000
|
|
8002496: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Incomplete ISO OUT Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
|
|
8002498: 687b ldr r3, [r7, #4]
|
|
800249a: 681b ldr r3, [r3, #0]
|
|
800249c: 4618 mov r0, r3
|
|
800249e: f003 feeb bl 8006278 <USB_ReadInterrupts>
|
|
80024a2: 4603 mov r3, r0
|
|
80024a4: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
80024a8: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
|
|
80024ac: d156 bne.n 800255c <HAL_PCD_IRQHandler+0x92a>
|
|
{
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
80024ae: 2301 movs r3, #1
|
|
80024b0: 627b str r3, [r7, #36] @ 0x24
|
|
80024b2: e045 b.n 8002540 <HAL_PCD_IRQHandler+0x90e>
|
|
{
|
|
RegVal = USBx_OUTEP(epnum)->DOEPCTL;
|
|
80024b4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80024b6: 015a lsls r2, r3, #5
|
|
80024b8: 69fb ldr r3, [r7, #28]
|
|
80024ba: 4413 add r3, r2
|
|
80024bc: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80024c0: 681b ldr r3, [r3, #0]
|
|
80024c2: 61bb str r3, [r7, #24]
|
|
|
|
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
80024c4: 6879 ldr r1, [r7, #4]
|
|
80024c6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80024c8: 4613 mov r3, r2
|
|
80024ca: 00db lsls r3, r3, #3
|
|
80024cc: 4413 add r3, r2
|
|
80024ce: 009b lsls r3, r3, #2
|
|
80024d0: 440b add r3, r1
|
|
80024d2: f503 7316 add.w r3, r3, #600 @ 0x258
|
|
80024d6: 781b ldrb r3, [r3, #0]
|
|
80024d8: 2b01 cmp r3, #1
|
|
80024da: d12e bne.n 800253a <HAL_PCD_IRQHandler+0x908>
|
|
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
|
|
80024dc: 69bb ldr r3, [r7, #24]
|
|
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
80024de: 2b00 cmp r3, #0
|
|
80024e0: da2b bge.n 800253a <HAL_PCD_IRQHandler+0x908>
|
|
(((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U)))
|
|
80024e2: 69bb ldr r3, [r7, #24]
|
|
80024e4: 0c1a lsrs r2, r3, #16
|
|
80024e6: 687b ldr r3, [r7, #4]
|
|
80024e8: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4
|
|
80024ec: 4053 eors r3, r2
|
|
80024ee: f003 0301 and.w r3, r3, #1
|
|
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
|
|
80024f2: 2b00 cmp r3, #0
|
|
80024f4: d121 bne.n 800253a <HAL_PCD_IRQHandler+0x908>
|
|
{
|
|
hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
|
|
80024f6: 6879 ldr r1, [r7, #4]
|
|
80024f8: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80024fa: 4613 mov r3, r2
|
|
80024fc: 00db lsls r3, r3, #3
|
|
80024fe: 4413 add r3, r2
|
|
8002500: 009b lsls r3, r3, #2
|
|
8002502: 440b add r3, r1
|
|
8002504: f203 2357 addw r3, r3, #599 @ 0x257
|
|
8002508: 2201 movs r2, #1
|
|
800250a: 701a strb r2, [r3, #0]
|
|
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM;
|
|
800250c: 6a3b ldr r3, [r7, #32]
|
|
800250e: 699b ldr r3, [r3, #24]
|
|
8002510: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
8002514: 6a3b ldr r3, [r7, #32]
|
|
8002516: 619a str r2, [r3, #24]
|
|
|
|
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U)
|
|
8002518: 6a3b ldr r3, [r7, #32]
|
|
800251a: 695b ldr r3, [r3, #20]
|
|
800251c: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002520: 2b00 cmp r3, #0
|
|
8002522: d10a bne.n 800253a <HAL_PCD_IRQHandler+0x908>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
|
|
8002524: 69fb ldr r3, [r7, #28]
|
|
8002526: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800252a: 685b ldr r3, [r3, #4]
|
|
800252c: 69fa ldr r2, [r7, #28]
|
|
800252e: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8002532: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8002536: 6053 str r3, [r2, #4]
|
|
break;
|
|
8002538: e008 b.n 800254c <HAL_PCD_IRQHandler+0x91a>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
800253a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800253c: 3301 adds r3, #1
|
|
800253e: 627b str r3, [r7, #36] @ 0x24
|
|
8002540: 687b ldr r3, [r7, #4]
|
|
8002542: 791b ldrb r3, [r3, #4]
|
|
8002544: 461a mov r2, r3
|
|
8002546: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002548: 4293 cmp r3, r2
|
|
800254a: d3b3 bcc.n 80024b4 <HAL_PCD_IRQHandler+0x882>
|
|
}
|
|
}
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
|
|
800254c: 687b ldr r3, [r7, #4]
|
|
800254e: 681b ldr r3, [r3, #0]
|
|
8002550: 695a ldr r2, [r3, #20]
|
|
8002552: 687b ldr r3, [r7, #4]
|
|
8002554: 681b ldr r3, [r3, #0]
|
|
8002556: f402 1200 and.w r2, r2, #2097152 @ 0x200000
|
|
800255a: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Connection event Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
|
|
800255c: 687b ldr r3, [r7, #4]
|
|
800255e: 681b ldr r3, [r3, #0]
|
|
8002560: 4618 mov r0, r3
|
|
8002562: f003 fe89 bl 8006278 <USB_ReadInterrupts>
|
|
8002566: 4603 mov r3, r0
|
|
8002568: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
|
|
800256c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8002570: d10a bne.n 8002588 <HAL_PCD_IRQHandler+0x956>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ConnectCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ConnectCallback(hpcd);
|
|
8002572: 6878 ldr r0, [r7, #4]
|
|
8002574: f005 ffb4 bl 80084e0 <HAL_PCD_ConnectCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
|
|
8002578: 687b ldr r3, [r7, #4]
|
|
800257a: 681b ldr r3, [r3, #0]
|
|
800257c: 695a ldr r2, [r3, #20]
|
|
800257e: 687b ldr r3, [r7, #4]
|
|
8002580: 681b ldr r3, [r3, #0]
|
|
8002582: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000
|
|
8002586: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Disconnection event Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
|
|
8002588: 687b ldr r3, [r7, #4]
|
|
800258a: 681b ldr r3, [r3, #0]
|
|
800258c: 4618 mov r0, r3
|
|
800258e: f003 fe73 bl 8006278 <USB_ReadInterrupts>
|
|
8002592: 4603 mov r3, r0
|
|
8002594: f003 0304 and.w r3, r3, #4
|
|
8002598: 2b04 cmp r3, #4
|
|
800259a: d115 bne.n 80025c8 <HAL_PCD_IRQHandler+0x996>
|
|
{
|
|
RegVal = hpcd->Instance->GOTGINT;
|
|
800259c: 687b ldr r3, [r7, #4]
|
|
800259e: 681b ldr r3, [r3, #0]
|
|
80025a0: 685b ldr r3, [r3, #4]
|
|
80025a2: 61bb str r3, [r7, #24]
|
|
|
|
if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
|
|
80025a4: 69bb ldr r3, [r7, #24]
|
|
80025a6: f003 0304 and.w r3, r3, #4
|
|
80025aa: 2b00 cmp r3, #0
|
|
80025ac: d002 beq.n 80025b4 <HAL_PCD_IRQHandler+0x982>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DisconnectCallback(hpcd);
|
|
#else
|
|
HAL_PCD_DisconnectCallback(hpcd);
|
|
80025ae: 6878 ldr r0, [r7, #4]
|
|
80025b0: f005 ffa4 bl 80084fc <HAL_PCD_DisconnectCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
hpcd->Instance->GOTGINT |= RegVal;
|
|
80025b4: 687b ldr r3, [r7, #4]
|
|
80025b6: 681b ldr r3, [r3, #0]
|
|
80025b8: 6859 ldr r1, [r3, #4]
|
|
80025ba: 687b ldr r3, [r7, #4]
|
|
80025bc: 681b ldr r3, [r3, #0]
|
|
80025be: 69ba ldr r2, [r7, #24]
|
|
80025c0: 430a orrs r2, r1
|
|
80025c2: 605a str r2, [r3, #4]
|
|
80025c4: e000 b.n 80025c8 <HAL_PCD_IRQHandler+0x996>
|
|
return;
|
|
80025c6: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
80025c8: 3734 adds r7, #52 @ 0x34
|
|
80025ca: 46bd mov sp, r7
|
|
80025cc: bd90 pop {r4, r7, pc}
|
|
|
|
080025ce <HAL_PCD_SetAddress>:
|
|
* @param hpcd PCD handle
|
|
* @param address new device address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
|
|
{
|
|
80025ce: b580 push {r7, lr}
|
|
80025d0: b082 sub sp, #8
|
|
80025d2: af00 add r7, sp, #0
|
|
80025d4: 6078 str r0, [r7, #4]
|
|
80025d6: 460b mov r3, r1
|
|
80025d8: 70fb strb r3, [r7, #3]
|
|
__HAL_LOCK(hpcd);
|
|
80025da: 687b ldr r3, [r7, #4]
|
|
80025dc: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
80025e0: 2b01 cmp r3, #1
|
|
80025e2: d101 bne.n 80025e8 <HAL_PCD_SetAddress+0x1a>
|
|
80025e4: 2302 movs r3, #2
|
|
80025e6: e012 b.n 800260e <HAL_PCD_SetAddress+0x40>
|
|
80025e8: 687b ldr r3, [r7, #4]
|
|
80025ea: 2201 movs r2, #1
|
|
80025ec: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
hpcd->USB_Address = address;
|
|
80025f0: 687b ldr r3, [r7, #4]
|
|
80025f2: 78fa ldrb r2, [r7, #3]
|
|
80025f4: 745a strb r2, [r3, #17]
|
|
(void)USB_SetDevAddress(hpcd->Instance, address);
|
|
80025f6: 687b ldr r3, [r7, #4]
|
|
80025f8: 681b ldr r3, [r3, #0]
|
|
80025fa: 78fa ldrb r2, [r7, #3]
|
|
80025fc: 4611 mov r1, r2
|
|
80025fe: 4618 mov r0, r3
|
|
8002600: f003 fdd2 bl 80061a8 <USB_SetDevAddress>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002604: 687b ldr r3, [r7, #4]
|
|
8002606: 2200 movs r2, #0
|
|
8002608: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
800260c: 2300 movs r3, #0
|
|
}
|
|
800260e: 4618 mov r0, r3
|
|
8002610: 3708 adds r7, #8
|
|
8002612: 46bd mov sp, r7
|
|
8002614: bd80 pop {r7, pc}
|
|
|
|
08002616 <HAL_PCD_EP_Open>:
|
|
* @param ep_type endpoint type
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
|
uint16_t ep_mps, uint8_t ep_type)
|
|
{
|
|
8002616: b580 push {r7, lr}
|
|
8002618: b084 sub sp, #16
|
|
800261a: af00 add r7, sp, #0
|
|
800261c: 6078 str r0, [r7, #4]
|
|
800261e: 4608 mov r0, r1
|
|
8002620: 4611 mov r1, r2
|
|
8002622: 461a mov r2, r3
|
|
8002624: 4603 mov r3, r0
|
|
8002626: 70fb strb r3, [r7, #3]
|
|
8002628: 460b mov r3, r1
|
|
800262a: 803b strh r3, [r7, #0]
|
|
800262c: 4613 mov r3, r2
|
|
800262e: 70bb strb r3, [r7, #2]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8002630: 2300 movs r3, #0
|
|
8002632: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8002634: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002638: 2b00 cmp r3, #0
|
|
800263a: da0f bge.n 800265c <HAL_PCD_EP_Open+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
800263c: 78fb ldrb r3, [r7, #3]
|
|
800263e: f003 020f and.w r2, r3, #15
|
|
8002642: 4613 mov r3, r2
|
|
8002644: 00db lsls r3, r3, #3
|
|
8002646: 4413 add r3, r2
|
|
8002648: 009b lsls r3, r3, #2
|
|
800264a: 3310 adds r3, #16
|
|
800264c: 687a ldr r2, [r7, #4]
|
|
800264e: 4413 add r3, r2
|
|
8002650: 3304 adds r3, #4
|
|
8002652: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8002654: 68fb ldr r3, [r7, #12]
|
|
8002656: 2201 movs r2, #1
|
|
8002658: 705a strb r2, [r3, #1]
|
|
800265a: e00f b.n 800267c <HAL_PCD_EP_Open+0x66>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
800265c: 78fb ldrb r3, [r7, #3]
|
|
800265e: f003 020f and.w r2, r3, #15
|
|
8002662: 4613 mov r3, r2
|
|
8002664: 00db lsls r3, r3, #3
|
|
8002666: 4413 add r3, r2
|
|
8002668: 009b lsls r3, r3, #2
|
|
800266a: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
800266e: 687a ldr r2, [r7, #4]
|
|
8002670: 4413 add r3, r2
|
|
8002672: 3304 adds r3, #4
|
|
8002674: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8002676: 68fb ldr r3, [r7, #12]
|
|
8002678: 2200 movs r2, #0
|
|
800267a: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
800267c: 78fb ldrb r3, [r7, #3]
|
|
800267e: f003 030f and.w r3, r3, #15
|
|
8002682: b2da uxtb r2, r3
|
|
8002684: 68fb ldr r3, [r7, #12]
|
|
8002686: 701a strb r2, [r3, #0]
|
|
ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
|
|
8002688: 883b ldrh r3, [r7, #0]
|
|
800268a: f3c3 020a ubfx r2, r3, #0, #11
|
|
800268e: 68fb ldr r3, [r7, #12]
|
|
8002690: 609a str r2, [r3, #8]
|
|
ep->type = ep_type;
|
|
8002692: 68fb ldr r3, [r7, #12]
|
|
8002694: 78ba ldrb r2, [r7, #2]
|
|
8002696: 711a strb r2, [r3, #4]
|
|
|
|
if (ep->is_in != 0U)
|
|
8002698: 68fb ldr r3, [r7, #12]
|
|
800269a: 785b ldrb r3, [r3, #1]
|
|
800269c: 2b00 cmp r3, #0
|
|
800269e: d004 beq.n 80026aa <HAL_PCD_EP_Open+0x94>
|
|
{
|
|
/* Assign a Tx FIFO */
|
|
ep->tx_fifo_num = ep->num;
|
|
80026a0: 68fb ldr r3, [r7, #12]
|
|
80026a2: 781b ldrb r3, [r3, #0]
|
|
80026a4: 461a mov r2, r3
|
|
80026a6: 68fb ldr r3, [r7, #12]
|
|
80026a8: 835a strh r2, [r3, #26]
|
|
}
|
|
|
|
/* Set initial data PID. */
|
|
if (ep_type == EP_TYPE_BULK)
|
|
80026aa: 78bb ldrb r3, [r7, #2]
|
|
80026ac: 2b02 cmp r3, #2
|
|
80026ae: d102 bne.n 80026b6 <HAL_PCD_EP_Open+0xa0>
|
|
{
|
|
ep->data_pid_start = 0U;
|
|
80026b0: 68fb ldr r3, [r7, #12]
|
|
80026b2: 2200 movs r2, #0
|
|
80026b4: 715a strb r2, [r3, #5]
|
|
}
|
|
|
|
__HAL_LOCK(hpcd);
|
|
80026b6: 687b ldr r3, [r7, #4]
|
|
80026b8: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
80026bc: 2b01 cmp r3, #1
|
|
80026be: d101 bne.n 80026c4 <HAL_PCD_EP_Open+0xae>
|
|
80026c0: 2302 movs r3, #2
|
|
80026c2: e00e b.n 80026e2 <HAL_PCD_EP_Open+0xcc>
|
|
80026c4: 687b ldr r3, [r7, #4]
|
|
80026c6: 2201 movs r2, #1
|
|
80026c8: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
|
|
80026cc: 687b ldr r3, [r7, #4]
|
|
80026ce: 681b ldr r3, [r3, #0]
|
|
80026d0: 68f9 ldr r1, [r7, #12]
|
|
80026d2: 4618 mov r0, r3
|
|
80026d4: f002 ff52 bl 800557c <USB_ActivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
80026d8: 687b ldr r3, [r7, #4]
|
|
80026da: 2200 movs r2, #0
|
|
80026dc: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return ret;
|
|
80026e0: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
80026e2: 4618 mov r0, r3
|
|
80026e4: 3710 adds r7, #16
|
|
80026e6: 46bd mov sp, r7
|
|
80026e8: bd80 pop {r7, pc}
|
|
|
|
080026ea <HAL_PCD_EP_Close>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
80026ea: b580 push {r7, lr}
|
|
80026ec: b084 sub sp, #16
|
|
80026ee: af00 add r7, sp, #0
|
|
80026f0: 6078 str r0, [r7, #4]
|
|
80026f2: 460b mov r3, r1
|
|
80026f4: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
80026f6: f997 3003 ldrsb.w r3, [r7, #3]
|
|
80026fa: 2b00 cmp r3, #0
|
|
80026fc: da0f bge.n 800271e <HAL_PCD_EP_Close+0x34>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
80026fe: 78fb ldrb r3, [r7, #3]
|
|
8002700: f003 020f and.w r2, r3, #15
|
|
8002704: 4613 mov r3, r2
|
|
8002706: 00db lsls r3, r3, #3
|
|
8002708: 4413 add r3, r2
|
|
800270a: 009b lsls r3, r3, #2
|
|
800270c: 3310 adds r3, #16
|
|
800270e: 687a ldr r2, [r7, #4]
|
|
8002710: 4413 add r3, r2
|
|
8002712: 3304 adds r3, #4
|
|
8002714: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8002716: 68fb ldr r3, [r7, #12]
|
|
8002718: 2201 movs r2, #1
|
|
800271a: 705a strb r2, [r3, #1]
|
|
800271c: e00f b.n 800273e <HAL_PCD_EP_Close+0x54>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
800271e: 78fb ldrb r3, [r7, #3]
|
|
8002720: f003 020f and.w r2, r3, #15
|
|
8002724: 4613 mov r3, r2
|
|
8002726: 00db lsls r3, r3, #3
|
|
8002728: 4413 add r3, r2
|
|
800272a: 009b lsls r3, r3, #2
|
|
800272c: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002730: 687a ldr r2, [r7, #4]
|
|
8002732: 4413 add r3, r2
|
|
8002734: 3304 adds r3, #4
|
|
8002736: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8002738: 68fb ldr r3, [r7, #12]
|
|
800273a: 2200 movs r2, #0
|
|
800273c: 705a strb r2, [r3, #1]
|
|
}
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
800273e: 78fb ldrb r3, [r7, #3]
|
|
8002740: f003 030f and.w r3, r3, #15
|
|
8002744: b2da uxtb r2, r3
|
|
8002746: 68fb ldr r3, [r7, #12]
|
|
8002748: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
800274a: 687b ldr r3, [r7, #4]
|
|
800274c: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002750: 2b01 cmp r3, #1
|
|
8002752: d101 bne.n 8002758 <HAL_PCD_EP_Close+0x6e>
|
|
8002754: 2302 movs r3, #2
|
|
8002756: e00e b.n 8002776 <HAL_PCD_EP_Close+0x8c>
|
|
8002758: 687b ldr r3, [r7, #4]
|
|
800275a: 2201 movs r2, #1
|
|
800275c: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
|
|
8002760: 687b ldr r3, [r7, #4]
|
|
8002762: 681b ldr r3, [r3, #0]
|
|
8002764: 68f9 ldr r1, [r7, #12]
|
|
8002766: 4618 mov r0, r3
|
|
8002768: f002 ff90 bl 800568c <USB_DeactivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
800276c: 687b ldr r3, [r7, #4]
|
|
800276e: 2200 movs r2, #0
|
|
8002770: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
return HAL_OK;
|
|
8002774: 2300 movs r3, #0
|
|
}
|
|
8002776: 4618 mov r0, r3
|
|
8002778: 3710 adds r7, #16
|
|
800277a: 46bd mov sp, r7
|
|
800277c: bd80 pop {r7, pc}
|
|
|
|
0800277e <HAL_PCD_EP_Receive>:
|
|
* @param pBuf pointer to the reception buffer
|
|
* @param len amount of data to be received
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
800277e: b580 push {r7, lr}
|
|
8002780: b086 sub sp, #24
|
|
8002782: af00 add r7, sp, #0
|
|
8002784: 60f8 str r0, [r7, #12]
|
|
8002786: 607a str r2, [r7, #4]
|
|
8002788: 603b str r3, [r7, #0]
|
|
800278a: 460b mov r3, r1
|
|
800278c: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
800278e: 7afb ldrb r3, [r7, #11]
|
|
8002790: f003 020f and.w r2, r3, #15
|
|
8002794: 4613 mov r3, r2
|
|
8002796: 00db lsls r3, r3, #3
|
|
8002798: 4413 add r3, r2
|
|
800279a: 009b lsls r3, r3, #2
|
|
800279c: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
80027a0: 68fa ldr r2, [r7, #12]
|
|
80027a2: 4413 add r3, r2
|
|
80027a4: 3304 adds r3, #4
|
|
80027a6: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
80027a8: 697b ldr r3, [r7, #20]
|
|
80027aa: 687a ldr r2, [r7, #4]
|
|
80027ac: 60da str r2, [r3, #12]
|
|
ep->xfer_len = len;
|
|
80027ae: 697b ldr r3, [r7, #20]
|
|
80027b0: 683a ldr r2, [r7, #0]
|
|
80027b2: 611a str r2, [r3, #16]
|
|
ep->xfer_count = 0U;
|
|
80027b4: 697b ldr r3, [r7, #20]
|
|
80027b6: 2200 movs r2, #0
|
|
80027b8: 615a str r2, [r3, #20]
|
|
ep->is_in = 0U;
|
|
80027ba: 697b ldr r3, [r7, #20]
|
|
80027bc: 2200 movs r2, #0
|
|
80027be: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
80027c0: 7afb ldrb r3, [r7, #11]
|
|
80027c2: f003 030f and.w r3, r3, #15
|
|
80027c6: b2da uxtb r2, r3
|
|
80027c8: 697b ldr r3, [r7, #20]
|
|
80027ca: 701a strb r2, [r3, #0]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
80027cc: 68fb ldr r3, [r7, #12]
|
|
80027ce: 799b ldrb r3, [r3, #6]
|
|
80027d0: 2b01 cmp r3, #1
|
|
80027d2: d102 bne.n 80027da <HAL_PCD_EP_Receive+0x5c>
|
|
{
|
|
ep->dma_addr = (uint32_t)pBuf;
|
|
80027d4: 687a ldr r2, [r7, #4]
|
|
80027d6: 697b ldr r3, [r7, #20]
|
|
80027d8: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
|
|
80027da: 68fb ldr r3, [r7, #12]
|
|
80027dc: 6818 ldr r0, [r3, #0]
|
|
80027de: 68fb ldr r3, [r7, #12]
|
|
80027e0: 799b ldrb r3, [r3, #6]
|
|
80027e2: 461a mov r2, r3
|
|
80027e4: 6979 ldr r1, [r7, #20]
|
|
80027e6: f003 f82d bl 8005844 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
80027ea: 2300 movs r3, #0
|
|
}
|
|
80027ec: 4618 mov r0, r3
|
|
80027ee: 3718 adds r7, #24
|
|
80027f0: 46bd mov sp, r7
|
|
80027f2: bd80 pop {r7, pc}
|
|
|
|
080027f4 <HAL_PCD_EP_Transmit>:
|
|
* @param pBuf pointer to the transmission buffer
|
|
* @param len amount of data to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
80027f4: b580 push {r7, lr}
|
|
80027f6: b086 sub sp, #24
|
|
80027f8: af00 add r7, sp, #0
|
|
80027fa: 60f8 str r0, [r7, #12]
|
|
80027fc: 607a str r2, [r7, #4]
|
|
80027fe: 603b str r3, [r7, #0]
|
|
8002800: 460b mov r3, r1
|
|
8002802: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002804: 7afb ldrb r3, [r7, #11]
|
|
8002806: f003 020f and.w r2, r3, #15
|
|
800280a: 4613 mov r3, r2
|
|
800280c: 00db lsls r3, r3, #3
|
|
800280e: 4413 add r3, r2
|
|
8002810: 009b lsls r3, r3, #2
|
|
8002812: 3310 adds r3, #16
|
|
8002814: 68fa ldr r2, [r7, #12]
|
|
8002816: 4413 add r3, r2
|
|
8002818: 3304 adds r3, #4
|
|
800281a: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
800281c: 697b ldr r3, [r7, #20]
|
|
800281e: 687a ldr r2, [r7, #4]
|
|
8002820: 60da str r2, [r3, #12]
|
|
ep->xfer_len = len;
|
|
8002822: 697b ldr r3, [r7, #20]
|
|
8002824: 683a ldr r2, [r7, #0]
|
|
8002826: 611a str r2, [r3, #16]
|
|
ep->xfer_count = 0U;
|
|
8002828: 697b ldr r3, [r7, #20]
|
|
800282a: 2200 movs r2, #0
|
|
800282c: 615a str r2, [r3, #20]
|
|
ep->is_in = 1U;
|
|
800282e: 697b ldr r3, [r7, #20]
|
|
8002830: 2201 movs r2, #1
|
|
8002832: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8002834: 7afb ldrb r3, [r7, #11]
|
|
8002836: f003 030f and.w r3, r3, #15
|
|
800283a: b2da uxtb r2, r3
|
|
800283c: 697b ldr r3, [r7, #20]
|
|
800283e: 701a strb r2, [r3, #0]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8002840: 68fb ldr r3, [r7, #12]
|
|
8002842: 799b ldrb r3, [r3, #6]
|
|
8002844: 2b01 cmp r3, #1
|
|
8002846: d102 bne.n 800284e <HAL_PCD_EP_Transmit+0x5a>
|
|
{
|
|
ep->dma_addr = (uint32_t)pBuf;
|
|
8002848: 687a ldr r2, [r7, #4]
|
|
800284a: 697b ldr r3, [r7, #20]
|
|
800284c: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
|
|
800284e: 68fb ldr r3, [r7, #12]
|
|
8002850: 6818 ldr r0, [r3, #0]
|
|
8002852: 68fb ldr r3, [r7, #12]
|
|
8002854: 799b ldrb r3, [r3, #6]
|
|
8002856: 461a mov r2, r3
|
|
8002858: 6979 ldr r1, [r7, #20]
|
|
800285a: f002 fff3 bl 8005844 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
800285e: 2300 movs r3, #0
|
|
}
|
|
8002860: 4618 mov r0, r3
|
|
8002862: 3718 adds r7, #24
|
|
8002864: 46bd mov sp, r7
|
|
8002866: bd80 pop {r7, pc}
|
|
|
|
08002868 <HAL_PCD_EP_SetStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8002868: b580 push {r7, lr}
|
|
800286a: b084 sub sp, #16
|
|
800286c: af00 add r7, sp, #0
|
|
800286e: 6078 str r0, [r7, #4]
|
|
8002870: 460b mov r3, r1
|
|
8002872: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
|
|
8002874: 78fb ldrb r3, [r7, #3]
|
|
8002876: f003 030f and.w r3, r3, #15
|
|
800287a: 687a ldr r2, [r7, #4]
|
|
800287c: 7912 ldrb r2, [r2, #4]
|
|
800287e: 4293 cmp r3, r2
|
|
8002880: d901 bls.n 8002886 <HAL_PCD_EP_SetStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8002882: 2301 movs r3, #1
|
|
8002884: e04f b.n 8002926 <HAL_PCD_EP_SetStall+0xbe>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8002886: f997 3003 ldrsb.w r3, [r7, #3]
|
|
800288a: 2b00 cmp r3, #0
|
|
800288c: da0f bge.n 80028ae <HAL_PCD_EP_SetStall+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
800288e: 78fb ldrb r3, [r7, #3]
|
|
8002890: f003 020f and.w r2, r3, #15
|
|
8002894: 4613 mov r3, r2
|
|
8002896: 00db lsls r3, r3, #3
|
|
8002898: 4413 add r3, r2
|
|
800289a: 009b lsls r3, r3, #2
|
|
800289c: 3310 adds r3, #16
|
|
800289e: 687a ldr r2, [r7, #4]
|
|
80028a0: 4413 add r3, r2
|
|
80028a2: 3304 adds r3, #4
|
|
80028a4: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
80028a6: 68fb ldr r3, [r7, #12]
|
|
80028a8: 2201 movs r2, #1
|
|
80028aa: 705a strb r2, [r3, #1]
|
|
80028ac: e00d b.n 80028ca <HAL_PCD_EP_SetStall+0x62>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr];
|
|
80028ae: 78fa ldrb r2, [r7, #3]
|
|
80028b0: 4613 mov r3, r2
|
|
80028b2: 00db lsls r3, r3, #3
|
|
80028b4: 4413 add r3, r2
|
|
80028b6: 009b lsls r3, r3, #2
|
|
80028b8: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
80028bc: 687a ldr r2, [r7, #4]
|
|
80028be: 4413 add r3, r2
|
|
80028c0: 3304 adds r3, #4
|
|
80028c2: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
80028c4: 68fb ldr r3, [r7, #12]
|
|
80028c6: 2200 movs r2, #0
|
|
80028c8: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 1U;
|
|
80028ca: 68fb ldr r3, [r7, #12]
|
|
80028cc: 2201 movs r2, #1
|
|
80028ce: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
80028d0: 78fb ldrb r3, [r7, #3]
|
|
80028d2: f003 030f and.w r3, r3, #15
|
|
80028d6: b2da uxtb r2, r3
|
|
80028d8: 68fb ldr r3, [r7, #12]
|
|
80028da: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
80028dc: 687b ldr r3, [r7, #4]
|
|
80028de: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
80028e2: 2b01 cmp r3, #1
|
|
80028e4: d101 bne.n 80028ea <HAL_PCD_EP_SetStall+0x82>
|
|
80028e6: 2302 movs r3, #2
|
|
80028e8: e01d b.n 8002926 <HAL_PCD_EP_SetStall+0xbe>
|
|
80028ea: 687b ldr r3, [r7, #4]
|
|
80028ec: 2201 movs r2, #1
|
|
80028ee: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
(void)USB_EPSetStall(hpcd->Instance, ep);
|
|
80028f2: 687b ldr r3, [r7, #4]
|
|
80028f4: 681b ldr r3, [r3, #0]
|
|
80028f6: 68f9 ldr r1, [r7, #12]
|
|
80028f8: 4618 mov r0, r3
|
|
80028fa: f003 fb81 bl 8006000 <USB_EPSetStall>
|
|
|
|
if ((ep_addr & EP_ADDR_MSK) == 0U)
|
|
80028fe: 78fb ldrb r3, [r7, #3]
|
|
8002900: f003 030f and.w r3, r3, #15
|
|
8002904: 2b00 cmp r3, #0
|
|
8002906: d109 bne.n 800291c <HAL_PCD_EP_SetStall+0xb4>
|
|
{
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
|
|
8002908: 687b ldr r3, [r7, #4]
|
|
800290a: 6818 ldr r0, [r3, #0]
|
|
800290c: 687b ldr r3, [r7, #4]
|
|
800290e: 7999 ldrb r1, [r3, #6]
|
|
8002910: 687b ldr r3, [r7, #4]
|
|
8002912: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8002916: 461a mov r2, r3
|
|
8002918: f003 fd72 bl 8006400 <USB_EP0_OutStart>
|
|
}
|
|
|
|
__HAL_UNLOCK(hpcd);
|
|
800291c: 687b ldr r3, [r7, #4]
|
|
800291e: 2200 movs r2, #0
|
|
8002920: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8002924: 2300 movs r3, #0
|
|
}
|
|
8002926: 4618 mov r0, r3
|
|
8002928: 3710 adds r7, #16
|
|
800292a: 46bd mov sp, r7
|
|
800292c: bd80 pop {r7, pc}
|
|
|
|
0800292e <HAL_PCD_EP_ClrStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
800292e: b580 push {r7, lr}
|
|
8002930: b084 sub sp, #16
|
|
8002932: af00 add r7, sp, #0
|
|
8002934: 6078 str r0, [r7, #4]
|
|
8002936: 460b mov r3, r1
|
|
8002938: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
|
|
800293a: 78fb ldrb r3, [r7, #3]
|
|
800293c: f003 030f and.w r3, r3, #15
|
|
8002940: 687a ldr r2, [r7, #4]
|
|
8002942: 7912 ldrb r2, [r2, #4]
|
|
8002944: 4293 cmp r3, r2
|
|
8002946: d901 bls.n 800294c <HAL_PCD_EP_ClrStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8002948: 2301 movs r3, #1
|
|
800294a: e042 b.n 80029d2 <HAL_PCD_EP_ClrStall+0xa4>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
800294c: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8002950: 2b00 cmp r3, #0
|
|
8002952: da0f bge.n 8002974 <HAL_PCD_EP_ClrStall+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8002954: 78fb ldrb r3, [r7, #3]
|
|
8002956: f003 020f and.w r2, r3, #15
|
|
800295a: 4613 mov r3, r2
|
|
800295c: 00db lsls r3, r3, #3
|
|
800295e: 4413 add r3, r2
|
|
8002960: 009b lsls r3, r3, #2
|
|
8002962: 3310 adds r3, #16
|
|
8002964: 687a ldr r2, [r7, #4]
|
|
8002966: 4413 add r3, r2
|
|
8002968: 3304 adds r3, #4
|
|
800296a: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
800296c: 68fb ldr r3, [r7, #12]
|
|
800296e: 2201 movs r2, #1
|
|
8002970: 705a strb r2, [r3, #1]
|
|
8002972: e00f b.n 8002994 <HAL_PCD_EP_ClrStall+0x66>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002974: 78fb ldrb r3, [r7, #3]
|
|
8002976: f003 020f and.w r2, r3, #15
|
|
800297a: 4613 mov r3, r2
|
|
800297c: 00db lsls r3, r3, #3
|
|
800297e: 4413 add r3, r2
|
|
8002980: 009b lsls r3, r3, #2
|
|
8002982: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002986: 687a ldr r2, [r7, #4]
|
|
8002988: 4413 add r3, r2
|
|
800298a: 3304 adds r3, #4
|
|
800298c: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
800298e: 68fb ldr r3, [r7, #12]
|
|
8002990: 2200 movs r2, #0
|
|
8002992: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 0U;
|
|
8002994: 68fb ldr r3, [r7, #12]
|
|
8002996: 2200 movs r2, #0
|
|
8002998: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
800299a: 78fb ldrb r3, [r7, #3]
|
|
800299c: f003 030f and.w r3, r3, #15
|
|
80029a0: b2da uxtb r2, r3
|
|
80029a2: 68fb ldr r3, [r7, #12]
|
|
80029a4: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
80029a6: 687b ldr r3, [r7, #4]
|
|
80029a8: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
80029ac: 2b01 cmp r3, #1
|
|
80029ae: d101 bne.n 80029b4 <HAL_PCD_EP_ClrStall+0x86>
|
|
80029b0: 2302 movs r3, #2
|
|
80029b2: e00e b.n 80029d2 <HAL_PCD_EP_ClrStall+0xa4>
|
|
80029b4: 687b ldr r3, [r7, #4]
|
|
80029b6: 2201 movs r2, #1
|
|
80029b8: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_EPClearStall(hpcd->Instance, ep);
|
|
80029bc: 687b ldr r3, [r7, #4]
|
|
80029be: 681b ldr r3, [r3, #0]
|
|
80029c0: 68f9 ldr r1, [r7, #12]
|
|
80029c2: 4618 mov r0, r3
|
|
80029c4: f003 fb8a bl 80060dc <USB_EPClearStall>
|
|
__HAL_UNLOCK(hpcd);
|
|
80029c8: 687b ldr r3, [r7, #4]
|
|
80029ca: 2200 movs r2, #0
|
|
80029cc: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
80029d0: 2300 movs r3, #0
|
|
}
|
|
80029d2: 4618 mov r0, r3
|
|
80029d4: 3710 adds r7, #16
|
|
80029d6: 46bd mov sp, r7
|
|
80029d8: bd80 pop {r7, pc}
|
|
|
|
080029da <HAL_PCD_EP_Abort>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
80029da: b580 push {r7, lr}
|
|
80029dc: b084 sub sp, #16
|
|
80029de: af00 add r7, sp, #0
|
|
80029e0: 6078 str r0, [r7, #4]
|
|
80029e2: 460b mov r3, r1
|
|
80029e4: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef ret;
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
80029e6: f997 3003 ldrsb.w r3, [r7, #3]
|
|
80029ea: 2b00 cmp r3, #0
|
|
80029ec: da0c bge.n 8002a08 <HAL_PCD_EP_Abort+0x2e>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
80029ee: 78fb ldrb r3, [r7, #3]
|
|
80029f0: f003 020f and.w r2, r3, #15
|
|
80029f4: 4613 mov r3, r2
|
|
80029f6: 00db lsls r3, r3, #3
|
|
80029f8: 4413 add r3, r2
|
|
80029fa: 009b lsls r3, r3, #2
|
|
80029fc: 3310 adds r3, #16
|
|
80029fe: 687a ldr r2, [r7, #4]
|
|
8002a00: 4413 add r3, r2
|
|
8002a02: 3304 adds r3, #4
|
|
8002a04: 60fb str r3, [r7, #12]
|
|
8002a06: e00c b.n 8002a22 <HAL_PCD_EP_Abort+0x48>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8002a08: 78fb ldrb r3, [r7, #3]
|
|
8002a0a: f003 020f and.w r2, r3, #15
|
|
8002a0e: 4613 mov r3, r2
|
|
8002a10: 00db lsls r3, r3, #3
|
|
8002a12: 4413 add r3, r2
|
|
8002a14: 009b lsls r3, r3, #2
|
|
8002a16: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002a1a: 687a ldr r2, [r7, #4]
|
|
8002a1c: 4413 add r3, r2
|
|
8002a1e: 3304 adds r3, #4
|
|
8002a20: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Stop Xfer */
|
|
ret = USB_EPStopXfer(hpcd->Instance, ep);
|
|
8002a22: 687b ldr r3, [r7, #4]
|
|
8002a24: 681b ldr r3, [r3, #0]
|
|
8002a26: 68f9 ldr r1, [r7, #12]
|
|
8002a28: 4618 mov r0, r3
|
|
8002a2a: f003 f9a9 bl 8005d80 <USB_EPStopXfer>
|
|
8002a2e: 4603 mov r3, r0
|
|
8002a30: 72fb strb r3, [r7, #11]
|
|
|
|
return ret;
|
|
8002a32: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
8002a34: 4618 mov r0, r3
|
|
8002a36: 3710 adds r7, #16
|
|
8002a38: 46bd mov sp, r7
|
|
8002a3a: bd80 pop {r7, pc}
|
|
|
|
08002a3c <PCD_WriteEmptyTxFifo>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8002a3c: b580 push {r7, lr}
|
|
8002a3e: b08a sub sp, #40 @ 0x28
|
|
8002a40: af02 add r7, sp, #8
|
|
8002a42: 6078 str r0, [r7, #4]
|
|
8002a44: 6039 str r1, [r7, #0]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8002a46: 687b ldr r3, [r7, #4]
|
|
8002a48: 681b ldr r3, [r3, #0]
|
|
8002a4a: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8002a4c: 697b ldr r3, [r7, #20]
|
|
8002a4e: 613b str r3, [r7, #16]
|
|
USB_OTG_EPTypeDef *ep;
|
|
uint32_t len;
|
|
uint32_t len32b;
|
|
uint32_t fifoemptymsk;
|
|
|
|
ep = &hpcd->IN_ep[epnum];
|
|
8002a50: 683a ldr r2, [r7, #0]
|
|
8002a52: 4613 mov r3, r2
|
|
8002a54: 00db lsls r3, r3, #3
|
|
8002a56: 4413 add r3, r2
|
|
8002a58: 009b lsls r3, r3, #2
|
|
8002a5a: 3310 adds r3, #16
|
|
8002a5c: 687a ldr r2, [r7, #4]
|
|
8002a5e: 4413 add r3, r2
|
|
8002a60: 3304 adds r3, #4
|
|
8002a62: 60fb str r3, [r7, #12]
|
|
|
|
if (ep->xfer_count > ep->xfer_len)
|
|
8002a64: 68fb ldr r3, [r7, #12]
|
|
8002a66: 695a ldr r2, [r3, #20]
|
|
8002a68: 68fb ldr r3, [r7, #12]
|
|
8002a6a: 691b ldr r3, [r3, #16]
|
|
8002a6c: 429a cmp r2, r3
|
|
8002a6e: d901 bls.n 8002a74 <PCD_WriteEmptyTxFifo+0x38>
|
|
{
|
|
return HAL_ERROR;
|
|
8002a70: 2301 movs r3, #1
|
|
8002a72: e06b b.n 8002b4c <PCD_WriteEmptyTxFifo+0x110>
|
|
}
|
|
|
|
len = ep->xfer_len - ep->xfer_count;
|
|
8002a74: 68fb ldr r3, [r7, #12]
|
|
8002a76: 691a ldr r2, [r3, #16]
|
|
8002a78: 68fb ldr r3, [r7, #12]
|
|
8002a7a: 695b ldr r3, [r3, #20]
|
|
8002a7c: 1ad3 subs r3, r2, r3
|
|
8002a7e: 61fb str r3, [r7, #28]
|
|
|
|
if (len > ep->maxpacket)
|
|
8002a80: 68fb ldr r3, [r7, #12]
|
|
8002a82: 689b ldr r3, [r3, #8]
|
|
8002a84: 69fa ldr r2, [r7, #28]
|
|
8002a86: 429a cmp r2, r3
|
|
8002a88: d902 bls.n 8002a90 <PCD_WriteEmptyTxFifo+0x54>
|
|
{
|
|
len = ep->maxpacket;
|
|
8002a8a: 68fb ldr r3, [r7, #12]
|
|
8002a8c: 689b ldr r3, [r3, #8]
|
|
8002a8e: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
len32b = (len + 3U) / 4U;
|
|
8002a90: 69fb ldr r3, [r7, #28]
|
|
8002a92: 3303 adds r3, #3
|
|
8002a94: 089b lsrs r3, r3, #2
|
|
8002a96: 61bb str r3, [r7, #24]
|
|
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8002a98: e02a b.n 8002af0 <PCD_WriteEmptyTxFifo+0xb4>
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
{
|
|
/* Write the FIFO */
|
|
len = ep->xfer_len - ep->xfer_count;
|
|
8002a9a: 68fb ldr r3, [r7, #12]
|
|
8002a9c: 691a ldr r2, [r3, #16]
|
|
8002a9e: 68fb ldr r3, [r7, #12]
|
|
8002aa0: 695b ldr r3, [r3, #20]
|
|
8002aa2: 1ad3 subs r3, r2, r3
|
|
8002aa4: 61fb str r3, [r7, #28]
|
|
|
|
if (len > ep->maxpacket)
|
|
8002aa6: 68fb ldr r3, [r7, #12]
|
|
8002aa8: 689b ldr r3, [r3, #8]
|
|
8002aaa: 69fa ldr r2, [r7, #28]
|
|
8002aac: 429a cmp r2, r3
|
|
8002aae: d902 bls.n 8002ab6 <PCD_WriteEmptyTxFifo+0x7a>
|
|
{
|
|
len = ep->maxpacket;
|
|
8002ab0: 68fb ldr r3, [r7, #12]
|
|
8002ab2: 689b ldr r3, [r3, #8]
|
|
8002ab4: 61fb str r3, [r7, #28]
|
|
}
|
|
len32b = (len + 3U) / 4U;
|
|
8002ab6: 69fb ldr r3, [r7, #28]
|
|
8002ab8: 3303 adds r3, #3
|
|
8002aba: 089b lsrs r3, r3, #2
|
|
8002abc: 61bb str r3, [r7, #24]
|
|
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
|
|
8002abe: 68fb ldr r3, [r7, #12]
|
|
8002ac0: 68d9 ldr r1, [r3, #12]
|
|
8002ac2: 683b ldr r3, [r7, #0]
|
|
8002ac4: b2da uxtb r2, r3
|
|
8002ac6: 69fb ldr r3, [r7, #28]
|
|
8002ac8: b298 uxth r0, r3
|
|
(uint8_t)hpcd->Init.dma_enable);
|
|
8002aca: 687b ldr r3, [r7, #4]
|
|
8002acc: 799b ldrb r3, [r3, #6]
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
|
|
8002ace: 9300 str r3, [sp, #0]
|
|
8002ad0: 4603 mov r3, r0
|
|
8002ad2: 6978 ldr r0, [r7, #20]
|
|
8002ad4: f003 f9fe bl 8005ed4 <USB_WritePacket>
|
|
|
|
ep->xfer_buff += len;
|
|
8002ad8: 68fb ldr r3, [r7, #12]
|
|
8002ada: 68da ldr r2, [r3, #12]
|
|
8002adc: 69fb ldr r3, [r7, #28]
|
|
8002ade: 441a add r2, r3
|
|
8002ae0: 68fb ldr r3, [r7, #12]
|
|
8002ae2: 60da str r2, [r3, #12]
|
|
ep->xfer_count += len;
|
|
8002ae4: 68fb ldr r3, [r7, #12]
|
|
8002ae6: 695a ldr r2, [r3, #20]
|
|
8002ae8: 69fb ldr r3, [r7, #28]
|
|
8002aea: 441a add r2, r3
|
|
8002aec: 68fb ldr r3, [r7, #12]
|
|
8002aee: 615a str r2, [r3, #20]
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8002af0: 683b ldr r3, [r7, #0]
|
|
8002af2: 015a lsls r2, r3, #5
|
|
8002af4: 693b ldr r3, [r7, #16]
|
|
8002af6: 4413 add r3, r2
|
|
8002af8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8002afc: 699b ldr r3, [r3, #24]
|
|
8002afe: b29b uxth r3, r3
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
8002b00: 69ba ldr r2, [r7, #24]
|
|
8002b02: 429a cmp r2, r3
|
|
8002b04: d809 bhi.n 8002b1a <PCD_WriteEmptyTxFifo+0xde>
|
|
8002b06: 68fb ldr r3, [r7, #12]
|
|
8002b08: 695a ldr r2, [r3, #20]
|
|
8002b0a: 68fb ldr r3, [r7, #12]
|
|
8002b0c: 691b ldr r3, [r3, #16]
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8002b0e: 429a cmp r2, r3
|
|
8002b10: d203 bcs.n 8002b1a <PCD_WriteEmptyTxFifo+0xde>
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
8002b12: 68fb ldr r3, [r7, #12]
|
|
8002b14: 691b ldr r3, [r3, #16]
|
|
8002b16: 2b00 cmp r3, #0
|
|
8002b18: d1bf bne.n 8002a9a <PCD_WriteEmptyTxFifo+0x5e>
|
|
}
|
|
|
|
if (ep->xfer_len <= ep->xfer_count)
|
|
8002b1a: 68fb ldr r3, [r7, #12]
|
|
8002b1c: 691a ldr r2, [r3, #16]
|
|
8002b1e: 68fb ldr r3, [r7, #12]
|
|
8002b20: 695b ldr r3, [r3, #20]
|
|
8002b22: 429a cmp r2, r3
|
|
8002b24: d811 bhi.n 8002b4a <PCD_WriteEmptyTxFifo+0x10e>
|
|
{
|
|
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
|
|
8002b26: 683b ldr r3, [r7, #0]
|
|
8002b28: f003 030f and.w r3, r3, #15
|
|
8002b2c: 2201 movs r2, #1
|
|
8002b2e: fa02 f303 lsl.w r3, r2, r3
|
|
8002b32: 60bb str r3, [r7, #8]
|
|
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
|
|
8002b34: 693b ldr r3, [r7, #16]
|
|
8002b36: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002b3a: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8002b3c: 68bb ldr r3, [r7, #8]
|
|
8002b3e: 43db mvns r3, r3
|
|
8002b40: 6939 ldr r1, [r7, #16]
|
|
8002b42: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8002b46: 4013 ands r3, r2
|
|
8002b48: 634b str r3, [r1, #52] @ 0x34
|
|
}
|
|
|
|
return HAL_OK;
|
|
8002b4a: 2300 movs r3, #0
|
|
}
|
|
8002b4c: 4618 mov r0, r3
|
|
8002b4e: 3720 adds r7, #32
|
|
8002b50: 46bd mov sp, r7
|
|
8002b52: bd80 pop {r7, pc}
|
|
|
|
08002b54 <PCD_EP_OutXfrComplete_int>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8002b54: b580 push {r7, lr}
|
|
8002b56: b088 sub sp, #32
|
|
8002b58: af00 add r7, sp, #0
|
|
8002b5a: 6078 str r0, [r7, #4]
|
|
8002b5c: 6039 str r1, [r7, #0]
|
|
USB_OTG_EPTypeDef *ep;
|
|
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8002b5e: 687b ldr r3, [r7, #4]
|
|
8002b60: 681b ldr r3, [r3, #0]
|
|
8002b62: 61fb str r3, [r7, #28]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8002b64: 69fb ldr r3, [r7, #28]
|
|
8002b66: 61bb str r3, [r7, #24]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
8002b68: 69fb ldr r3, [r7, #28]
|
|
8002b6a: 333c adds r3, #60 @ 0x3c
|
|
8002b6c: 3304 adds r3, #4
|
|
8002b6e: 681b ldr r3, [r3, #0]
|
|
8002b70: 617b str r3, [r7, #20]
|
|
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
|
|
8002b72: 683b ldr r3, [r7, #0]
|
|
8002b74: 015a lsls r2, r3, #5
|
|
8002b76: 69bb ldr r3, [r7, #24]
|
|
8002b78: 4413 add r3, r2
|
|
8002b7a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002b7e: 689b ldr r3, [r3, #8]
|
|
8002b80: 613b str r3, [r7, #16]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8002b82: 687b ldr r3, [r7, #4]
|
|
8002b84: 799b ldrb r3, [r3, #6]
|
|
8002b86: 2b01 cmp r3, #1
|
|
8002b88: d17b bne.n 8002c82 <PCD_EP_OutXfrComplete_int+0x12e>
|
|
{
|
|
if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
|
|
8002b8a: 693b ldr r3, [r7, #16]
|
|
8002b8c: f003 0308 and.w r3, r3, #8
|
|
8002b90: 2b00 cmp r3, #0
|
|
8002b92: d015 beq.n 8002bc0 <PCD_EP_OutXfrComplete_int+0x6c>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8002b94: 697b ldr r3, [r7, #20]
|
|
8002b96: 4a61 ldr r2, [pc, #388] @ (8002d1c <PCD_EP_OutXfrComplete_int+0x1c8>)
|
|
8002b98: 4293 cmp r3, r2
|
|
8002b9a: f240 80b9 bls.w 8002d10 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
8002b9e: 693b ldr r3, [r7, #16]
|
|
8002ba0: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8002ba4: 2b00 cmp r3, #0
|
|
8002ba6: f000 80b3 beq.w 8002d10 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8002baa: 683b ldr r3, [r7, #0]
|
|
8002bac: 015a lsls r2, r3, #5
|
|
8002bae: 69bb ldr r3, [r7, #24]
|
|
8002bb0: 4413 add r3, r2
|
|
8002bb2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002bb6: 461a mov r2, r3
|
|
8002bb8: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8002bbc: 6093 str r3, [r2, #8]
|
|
8002bbe: e0a7 b.n 8002d10 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
}
|
|
else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
|
|
8002bc0: 693b ldr r3, [r7, #16]
|
|
8002bc2: f003 0320 and.w r3, r3, #32
|
|
8002bc6: 2b00 cmp r3, #0
|
|
8002bc8: d009 beq.n 8002bde <PCD_EP_OutXfrComplete_int+0x8a>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
8002bca: 683b ldr r3, [r7, #0]
|
|
8002bcc: 015a lsls r2, r3, #5
|
|
8002bce: 69bb ldr r3, [r7, #24]
|
|
8002bd0: 4413 add r3, r2
|
|
8002bd2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002bd6: 461a mov r2, r3
|
|
8002bd8: 2320 movs r3, #32
|
|
8002bda: 6093 str r3, [r2, #8]
|
|
8002bdc: e098 b.n 8002d10 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
|
|
8002bde: 693b ldr r3, [r7, #16]
|
|
8002be0: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
8002be4: 2b00 cmp r3, #0
|
|
8002be6: f040 8093 bne.w 8002d10 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8002bea: 697b ldr r3, [r7, #20]
|
|
8002bec: 4a4b ldr r2, [pc, #300] @ (8002d1c <PCD_EP_OutXfrComplete_int+0x1c8>)
|
|
8002bee: 4293 cmp r3, r2
|
|
8002bf0: d90f bls.n 8002c12 <PCD_EP_OutXfrComplete_int+0xbe>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
8002bf2: 693b ldr r3, [r7, #16]
|
|
8002bf4: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8002bf8: 2b00 cmp r3, #0
|
|
8002bfa: d00a beq.n 8002c12 <PCD_EP_OutXfrComplete_int+0xbe>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8002bfc: 683b ldr r3, [r7, #0]
|
|
8002bfe: 015a lsls r2, r3, #5
|
|
8002c00: 69bb ldr r3, [r7, #24]
|
|
8002c02: 4413 add r3, r2
|
|
8002c04: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002c08: 461a mov r2, r3
|
|
8002c0a: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8002c0e: 6093 str r3, [r2, #8]
|
|
8002c10: e07e b.n 8002d10 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[epnum];
|
|
8002c12: 683a ldr r2, [r7, #0]
|
|
8002c14: 4613 mov r3, r2
|
|
8002c16: 00db lsls r3, r3, #3
|
|
8002c18: 4413 add r3, r2
|
|
8002c1a: 009b lsls r3, r3, #2
|
|
8002c1c: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002c20: 687a ldr r2, [r7, #4]
|
|
8002c22: 4413 add r3, r2
|
|
8002c24: 3304 adds r3, #4
|
|
8002c26: 60fb str r3, [r7, #12]
|
|
|
|
/* out data packet received over EP */
|
|
ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
|
|
8002c28: 68fb ldr r3, [r7, #12]
|
|
8002c2a: 6a1a ldr r2, [r3, #32]
|
|
8002c2c: 683b ldr r3, [r7, #0]
|
|
8002c2e: 0159 lsls r1, r3, #5
|
|
8002c30: 69bb ldr r3, [r7, #24]
|
|
8002c32: 440b add r3, r1
|
|
8002c34: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002c38: 691b ldr r3, [r3, #16]
|
|
8002c3a: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8002c3e: 1ad2 subs r2, r2, r3
|
|
8002c40: 68fb ldr r3, [r7, #12]
|
|
8002c42: 615a str r2, [r3, #20]
|
|
|
|
if (epnum == 0U)
|
|
8002c44: 683b ldr r3, [r7, #0]
|
|
8002c46: 2b00 cmp r3, #0
|
|
8002c48: d114 bne.n 8002c74 <PCD_EP_OutXfrComplete_int+0x120>
|
|
{
|
|
if (ep->xfer_len == 0U)
|
|
8002c4a: 68fb ldr r3, [r7, #12]
|
|
8002c4c: 691b ldr r3, [r3, #16]
|
|
8002c4e: 2b00 cmp r3, #0
|
|
8002c50: d109 bne.n 8002c66 <PCD_EP_OutXfrComplete_int+0x112>
|
|
{
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
8002c52: 687b ldr r3, [r7, #4]
|
|
8002c54: 6818 ldr r0, [r3, #0]
|
|
8002c56: 687b ldr r3, [r7, #4]
|
|
8002c58: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8002c5c: 461a mov r2, r3
|
|
8002c5e: 2101 movs r1, #1
|
|
8002c60: f003 fbce bl 8006400 <USB_EP0_OutStart>
|
|
8002c64: e006 b.n 8002c74 <PCD_EP_OutXfrComplete_int+0x120>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_buff += ep->xfer_count;
|
|
8002c66: 68fb ldr r3, [r7, #12]
|
|
8002c68: 68da ldr r2, [r3, #12]
|
|
8002c6a: 68fb ldr r3, [r7, #12]
|
|
8002c6c: 695b ldr r3, [r3, #20]
|
|
8002c6e: 441a add r2, r3
|
|
8002c70: 68fb ldr r3, [r7, #12]
|
|
8002c72: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
8002c74: 683b ldr r3, [r7, #0]
|
|
8002c76: b2db uxtb r3, r3
|
|
8002c78: 4619 mov r1, r3
|
|
8002c7a: 6878 ldr r0, [r7, #4]
|
|
8002c7c: f005 fb6c bl 8008358 <HAL_PCD_DataOutStageCallback>
|
|
8002c80: e046 b.n 8002d10 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
/* ... */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (gSNPSiD == USB_OTG_CORE_ID_310A)
|
|
8002c82: 697b ldr r3, [r7, #20]
|
|
8002c84: 4a26 ldr r2, [pc, #152] @ (8002d20 <PCD_EP_OutXfrComplete_int+0x1cc>)
|
|
8002c86: 4293 cmp r3, r2
|
|
8002c88: d124 bne.n 8002cd4 <PCD_EP_OutXfrComplete_int+0x180>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
|
|
8002c8a: 693b ldr r3, [r7, #16]
|
|
8002c8c: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8002c90: 2b00 cmp r3, #0
|
|
8002c92: d00a beq.n 8002caa <PCD_EP_OutXfrComplete_int+0x156>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8002c94: 683b ldr r3, [r7, #0]
|
|
8002c96: 015a lsls r2, r3, #5
|
|
8002c98: 69bb ldr r3, [r7, #24]
|
|
8002c9a: 4413 add r3, r2
|
|
8002c9c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002ca0: 461a mov r2, r3
|
|
8002ca2: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8002ca6: 6093 str r3, [r2, #8]
|
|
8002ca8: e032 b.n 8002d10 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else
|
|
{
|
|
if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
|
|
8002caa: 693b ldr r3, [r7, #16]
|
|
8002cac: f003 0320 and.w r3, r3, #32
|
|
8002cb0: 2b00 cmp r3, #0
|
|
8002cb2: d008 beq.n 8002cc6 <PCD_EP_OutXfrComplete_int+0x172>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
8002cb4: 683b ldr r3, [r7, #0]
|
|
8002cb6: 015a lsls r2, r3, #5
|
|
8002cb8: 69bb ldr r3, [r7, #24]
|
|
8002cba: 4413 add r3, r2
|
|
8002cbc: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002cc0: 461a mov r2, r3
|
|
8002cc2: 2320 movs r3, #32
|
|
8002cc4: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
8002cc6: 683b ldr r3, [r7, #0]
|
|
8002cc8: b2db uxtb r3, r3
|
|
8002cca: 4619 mov r1, r3
|
|
8002ccc: 6878 ldr r0, [r7, #4]
|
|
8002cce: f005 fb43 bl 8008358 <HAL_PCD_DataOutStageCallback>
|
|
8002cd2: e01d b.n 8002d10 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
|
|
8002cd4: 683b ldr r3, [r7, #0]
|
|
8002cd6: 2b00 cmp r3, #0
|
|
8002cd8: d114 bne.n 8002d04 <PCD_EP_OutXfrComplete_int+0x1b0>
|
|
8002cda: 6879 ldr r1, [r7, #4]
|
|
8002cdc: 683a ldr r2, [r7, #0]
|
|
8002cde: 4613 mov r3, r2
|
|
8002ce0: 00db lsls r3, r3, #3
|
|
8002ce2: 4413 add r3, r2
|
|
8002ce4: 009b lsls r3, r3, #2
|
|
8002ce6: 440b add r3, r1
|
|
8002ce8: f503 7319 add.w r3, r3, #612 @ 0x264
|
|
8002cec: 681b ldr r3, [r3, #0]
|
|
8002cee: 2b00 cmp r3, #0
|
|
8002cf0: d108 bne.n 8002d04 <PCD_EP_OutXfrComplete_int+0x1b0>
|
|
{
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
|
|
8002cf2: 687b ldr r3, [r7, #4]
|
|
8002cf4: 6818 ldr r0, [r3, #0]
|
|
8002cf6: 687b ldr r3, [r7, #4]
|
|
8002cf8: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8002cfc: 461a mov r2, r3
|
|
8002cfe: 2100 movs r1, #0
|
|
8002d00: f003 fb7e bl 8006400 <USB_EP0_OutStart>
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
8002d04: 683b ldr r3, [r7, #0]
|
|
8002d06: b2db uxtb r3, r3
|
|
8002d08: 4619 mov r1, r3
|
|
8002d0a: 6878 ldr r0, [r7, #4]
|
|
8002d0c: f005 fb24 bl 8008358 <HAL_PCD_DataOutStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8002d10: 2300 movs r3, #0
|
|
}
|
|
8002d12: 4618 mov r0, r3
|
|
8002d14: 3720 adds r7, #32
|
|
8002d16: 46bd mov sp, r7
|
|
8002d18: bd80 pop {r7, pc}
|
|
8002d1a: bf00 nop
|
|
8002d1c: 4f54300a .word 0x4f54300a
|
|
8002d20: 4f54310a .word 0x4f54310a
|
|
|
|
08002d24 <PCD_EP_OutSetupPacket_int>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8002d24: b580 push {r7, lr}
|
|
8002d26: b086 sub sp, #24
|
|
8002d28: af00 add r7, sp, #0
|
|
8002d2a: 6078 str r0, [r7, #4]
|
|
8002d2c: 6039 str r1, [r7, #0]
|
|
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8002d2e: 687b ldr r3, [r7, #4]
|
|
8002d30: 681b ldr r3, [r3, #0]
|
|
8002d32: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8002d34: 697b ldr r3, [r7, #20]
|
|
8002d36: 613b str r3, [r7, #16]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
8002d38: 697b ldr r3, [r7, #20]
|
|
8002d3a: 333c adds r3, #60 @ 0x3c
|
|
8002d3c: 3304 adds r3, #4
|
|
8002d3e: 681b ldr r3, [r3, #0]
|
|
8002d40: 60fb str r3, [r7, #12]
|
|
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
|
|
8002d42: 683b ldr r3, [r7, #0]
|
|
8002d44: 015a lsls r2, r3, #5
|
|
8002d46: 693b ldr r3, [r7, #16]
|
|
8002d48: 4413 add r3, r2
|
|
8002d4a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002d4e: 689b ldr r3, [r3, #8]
|
|
8002d50: 60bb str r3, [r7, #8]
|
|
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8002d52: 68fb ldr r3, [r7, #12]
|
|
8002d54: 4a15 ldr r2, [pc, #84] @ (8002dac <PCD_EP_OutSetupPacket_int+0x88>)
|
|
8002d56: 4293 cmp r3, r2
|
|
8002d58: d90e bls.n 8002d78 <PCD_EP_OutSetupPacket_int+0x54>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
8002d5a: 68bb ldr r3, [r7, #8]
|
|
8002d5c: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8002d60: 2b00 cmp r3, #0
|
|
8002d62: d009 beq.n 8002d78 <PCD_EP_OutSetupPacket_int+0x54>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8002d64: 683b ldr r3, [r7, #0]
|
|
8002d66: 015a lsls r2, r3, #5
|
|
8002d68: 693b ldr r3, [r7, #16]
|
|
8002d6a: 4413 add r3, r2
|
|
8002d6c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002d70: 461a mov r2, r3
|
|
8002d72: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8002d76: 6093 str r3, [r2, #8]
|
|
|
|
/* Inform the upper layer that a setup packet is available */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SetupStageCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SetupStageCallback(hpcd);
|
|
8002d78: 6878 ldr r0, [r7, #4]
|
|
8002d7a: f005 fadb bl 8008334 <HAL_PCD_SetupStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
|
|
8002d7e: 68fb ldr r3, [r7, #12]
|
|
8002d80: 4a0a ldr r2, [pc, #40] @ (8002dac <PCD_EP_OutSetupPacket_int+0x88>)
|
|
8002d82: 4293 cmp r3, r2
|
|
8002d84: d90c bls.n 8002da0 <PCD_EP_OutSetupPacket_int+0x7c>
|
|
8002d86: 687b ldr r3, [r7, #4]
|
|
8002d88: 799b ldrb r3, [r3, #6]
|
|
8002d8a: 2b01 cmp r3, #1
|
|
8002d8c: d108 bne.n 8002da0 <PCD_EP_OutSetupPacket_int+0x7c>
|
|
{
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
8002d8e: 687b ldr r3, [r7, #4]
|
|
8002d90: 6818 ldr r0, [r3, #0]
|
|
8002d92: 687b ldr r3, [r7, #4]
|
|
8002d94: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8002d98: 461a mov r2, r3
|
|
8002d9a: 2101 movs r1, #1
|
|
8002d9c: f003 fb30 bl 8006400 <USB_EP0_OutStart>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8002da0: 2300 movs r3, #0
|
|
}
|
|
8002da2: 4618 mov r0, r3
|
|
8002da4: 3718 adds r7, #24
|
|
8002da6: 46bd mov sp, r7
|
|
8002da8: bd80 pop {r7, pc}
|
|
8002daa: bf00 nop
|
|
8002dac: 4f54300a .word 0x4f54300a
|
|
|
|
08002db0 <HAL_PCDEx_SetTxFiFo>:
|
|
* @param fifo The number of Tx fifo
|
|
* @param size Fifo size
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
|
|
{
|
|
8002db0: b480 push {r7}
|
|
8002db2: b085 sub sp, #20
|
|
8002db4: af00 add r7, sp, #0
|
|
8002db6: 6078 str r0, [r7, #4]
|
|
8002db8: 460b mov r3, r1
|
|
8002dba: 70fb strb r3, [r7, #3]
|
|
8002dbc: 4613 mov r3, r2
|
|
8002dbe: 803b strh r3, [r7, #0]
|
|
--> Txn should be configured with the minimum space of 16 words
|
|
The FIFO is used optimally when used TxFIFOs are allocated in the top
|
|
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
|
|
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
|
|
|
|
Tx_Offset = hpcd->Instance->GRXFSIZ;
|
|
8002dc0: 687b ldr r3, [r7, #4]
|
|
8002dc2: 681b ldr r3, [r3, #0]
|
|
8002dc4: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8002dc6: 60bb str r3, [r7, #8]
|
|
|
|
if (fifo == 0U)
|
|
8002dc8: 78fb ldrb r3, [r7, #3]
|
|
8002dca: 2b00 cmp r3, #0
|
|
8002dcc: d107 bne.n 8002dde <HAL_PCDEx_SetTxFiFo+0x2e>
|
|
{
|
|
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
|
|
8002dce: 883b ldrh r3, [r7, #0]
|
|
8002dd0: 0419 lsls r1, r3, #16
|
|
8002dd2: 687b ldr r3, [r7, #4]
|
|
8002dd4: 681b ldr r3, [r3, #0]
|
|
8002dd6: 68ba ldr r2, [r7, #8]
|
|
8002dd8: 430a orrs r2, r1
|
|
8002dda: 629a str r2, [r3, #40] @ 0x28
|
|
8002ddc: e028 b.n 8002e30 <HAL_PCDEx_SetTxFiFo+0x80>
|
|
}
|
|
else
|
|
{
|
|
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
|
|
8002dde: 687b ldr r3, [r7, #4]
|
|
8002de0: 681b ldr r3, [r3, #0]
|
|
8002de2: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002de4: 0c1b lsrs r3, r3, #16
|
|
8002de6: 68ba ldr r2, [r7, #8]
|
|
8002de8: 4413 add r3, r2
|
|
8002dea: 60bb str r3, [r7, #8]
|
|
for (i = 0U; i < (fifo - 1U); i++)
|
|
8002dec: 2300 movs r3, #0
|
|
8002dee: 73fb strb r3, [r7, #15]
|
|
8002df0: e00d b.n 8002e0e <HAL_PCDEx_SetTxFiFo+0x5e>
|
|
{
|
|
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
|
|
8002df2: 687b ldr r3, [r7, #4]
|
|
8002df4: 681a ldr r2, [r3, #0]
|
|
8002df6: 7bfb ldrb r3, [r7, #15]
|
|
8002df8: 3340 adds r3, #64 @ 0x40
|
|
8002dfa: 009b lsls r3, r3, #2
|
|
8002dfc: 4413 add r3, r2
|
|
8002dfe: 685b ldr r3, [r3, #4]
|
|
8002e00: 0c1b lsrs r3, r3, #16
|
|
8002e02: 68ba ldr r2, [r7, #8]
|
|
8002e04: 4413 add r3, r2
|
|
8002e06: 60bb str r3, [r7, #8]
|
|
for (i = 0U; i < (fifo - 1U); i++)
|
|
8002e08: 7bfb ldrb r3, [r7, #15]
|
|
8002e0a: 3301 adds r3, #1
|
|
8002e0c: 73fb strb r3, [r7, #15]
|
|
8002e0e: 7bfa ldrb r2, [r7, #15]
|
|
8002e10: 78fb ldrb r3, [r7, #3]
|
|
8002e12: 3b01 subs r3, #1
|
|
8002e14: 429a cmp r2, r3
|
|
8002e16: d3ec bcc.n 8002df2 <HAL_PCDEx_SetTxFiFo+0x42>
|
|
}
|
|
|
|
/* Multiply Tx_Size by 2 to get higher performance */
|
|
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
|
|
8002e18: 883b ldrh r3, [r7, #0]
|
|
8002e1a: 0418 lsls r0, r3, #16
|
|
8002e1c: 687b ldr r3, [r7, #4]
|
|
8002e1e: 6819 ldr r1, [r3, #0]
|
|
8002e20: 78fb ldrb r3, [r7, #3]
|
|
8002e22: 3b01 subs r3, #1
|
|
8002e24: 68ba ldr r2, [r7, #8]
|
|
8002e26: 4302 orrs r2, r0
|
|
8002e28: 3340 adds r3, #64 @ 0x40
|
|
8002e2a: 009b lsls r3, r3, #2
|
|
8002e2c: 440b add r3, r1
|
|
8002e2e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8002e30: 2300 movs r3, #0
|
|
}
|
|
8002e32: 4618 mov r0, r3
|
|
8002e34: 3714 adds r7, #20
|
|
8002e36: 46bd mov sp, r7
|
|
8002e38: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002e3c: 4770 bx lr
|
|
|
|
08002e3e <HAL_PCDEx_SetRxFiFo>:
|
|
* @param hpcd PCD handle
|
|
* @param size Size of Rx fifo
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
|
|
{
|
|
8002e3e: b480 push {r7}
|
|
8002e40: b083 sub sp, #12
|
|
8002e42: af00 add r7, sp, #0
|
|
8002e44: 6078 str r0, [r7, #4]
|
|
8002e46: 460b mov r3, r1
|
|
8002e48: 807b strh r3, [r7, #2]
|
|
hpcd->Instance->GRXFSIZ = size;
|
|
8002e4a: 687b ldr r3, [r7, #4]
|
|
8002e4c: 681b ldr r3, [r3, #0]
|
|
8002e4e: 887a ldrh r2, [r7, #2]
|
|
8002e50: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_OK;
|
|
8002e52: 2300 movs r3, #0
|
|
}
|
|
8002e54: 4618 mov r0, r3
|
|
8002e56: 370c adds r7, #12
|
|
8002e58: 46bd mov sp, r7
|
|
8002e5a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002e5e: 4770 bx lr
|
|
|
|
08002e60 <HAL_PCDEx_ActivateLPM>:
|
|
* @brief Activate LPM feature.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8002e60: b480 push {r7}
|
|
8002e62: b085 sub sp, #20
|
|
8002e64: af00 add r7, sp, #0
|
|
8002e66: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8002e68: 687b ldr r3, [r7, #4]
|
|
8002e6a: 681b ldr r3, [r3, #0]
|
|
8002e6c: 60fb str r3, [r7, #12]
|
|
|
|
hpcd->lpm_active = 1U;
|
|
8002e6e: 687b ldr r3, [r7, #4]
|
|
8002e70: 2201 movs r2, #1
|
|
8002e72: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8
|
|
hpcd->LPM_State = LPM_L0;
|
|
8002e76: 687b ldr r3, [r7, #4]
|
|
8002e78: 2200 movs r2, #0
|
|
8002e7a: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
|
|
8002e7e: 68fb ldr r3, [r7, #12]
|
|
8002e80: 699b ldr r3, [r3, #24]
|
|
8002e82: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000
|
|
8002e86: 68fb ldr r3, [r7, #12]
|
|
8002e88: 619a str r2, [r3, #24]
|
|
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
|
|
8002e8a: 68fb ldr r3, [r7, #12]
|
|
8002e8c: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8002e8e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8002e92: f043 0303 orr.w r3, r3, #3
|
|
8002e96: 68fa ldr r2, [r7, #12]
|
|
8002e98: 6553 str r3, [r2, #84] @ 0x54
|
|
|
|
return HAL_OK;
|
|
8002e9a: 2300 movs r3, #0
|
|
}
|
|
8002e9c: 4618 mov r0, r3
|
|
8002e9e: 3714 adds r7, #20
|
|
8002ea0: 46bd mov sp, r7
|
|
8002ea2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002ea6: 4770 bx lr
|
|
|
|
08002ea8 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8002ea8: b580 push {r7, lr}
|
|
8002eaa: b084 sub sp, #16
|
|
8002eac: af00 add r7, sp, #0
|
|
8002eae: 6078 str r0, [r7, #4]
|
|
8002eb0: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
8002eb2: 687b ldr r3, [r7, #4]
|
|
8002eb4: 2b00 cmp r3, #0
|
|
8002eb6: d101 bne.n 8002ebc <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8002eb8: 2301 movs r3, #1
|
|
8002eba: e0cc b.n 8003056 <HAL_RCC_ClockConfig+0x1ae>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8002ebc: 4b68 ldr r3, [pc, #416] @ (8003060 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8002ebe: 681b ldr r3, [r3, #0]
|
|
8002ec0: f003 030f and.w r3, r3, #15
|
|
8002ec4: 683a ldr r2, [r7, #0]
|
|
8002ec6: 429a cmp r2, r3
|
|
8002ec8: d90c bls.n 8002ee4 <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8002eca: 4b65 ldr r3, [pc, #404] @ (8003060 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8002ecc: 683a ldr r2, [r7, #0]
|
|
8002ece: b2d2 uxtb r2, r2
|
|
8002ed0: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8002ed2: 4b63 ldr r3, [pc, #396] @ (8003060 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8002ed4: 681b ldr r3, [r3, #0]
|
|
8002ed6: f003 030f and.w r3, r3, #15
|
|
8002eda: 683a ldr r2, [r7, #0]
|
|
8002edc: 429a cmp r2, r3
|
|
8002ede: d001 beq.n 8002ee4 <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
return HAL_ERROR;
|
|
8002ee0: 2301 movs r3, #1
|
|
8002ee2: e0b8 b.n 8003056 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8002ee4: 687b ldr r3, [r7, #4]
|
|
8002ee6: 681b ldr r3, [r3, #0]
|
|
8002ee8: f003 0302 and.w r3, r3, #2
|
|
8002eec: 2b00 cmp r3, #0
|
|
8002eee: d020 beq.n 8002f32 <HAL_RCC_ClockConfig+0x8a>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8002ef0: 687b ldr r3, [r7, #4]
|
|
8002ef2: 681b ldr r3, [r3, #0]
|
|
8002ef4: f003 0304 and.w r3, r3, #4
|
|
8002ef8: 2b00 cmp r3, #0
|
|
8002efa: d005 beq.n 8002f08 <HAL_RCC_ClockConfig+0x60>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
8002efc: 4b59 ldr r3, [pc, #356] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002efe: 689b ldr r3, [r3, #8]
|
|
8002f00: 4a58 ldr r2, [pc, #352] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002f02: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
|
|
8002f06: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8002f08: 687b ldr r3, [r7, #4]
|
|
8002f0a: 681b ldr r3, [r3, #0]
|
|
8002f0c: f003 0308 and.w r3, r3, #8
|
|
8002f10: 2b00 cmp r3, #0
|
|
8002f12: d005 beq.n 8002f20 <HAL_RCC_ClockConfig+0x78>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
8002f14: 4b53 ldr r3, [pc, #332] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002f16: 689b ldr r3, [r3, #8]
|
|
8002f18: 4a52 ldr r2, [pc, #328] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002f1a: f443 4360 orr.w r3, r3, #57344 @ 0xe000
|
|
8002f1e: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8002f20: 4b50 ldr r3, [pc, #320] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002f22: 689b ldr r3, [r3, #8]
|
|
8002f24: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8002f28: 687b ldr r3, [r7, #4]
|
|
8002f2a: 689b ldr r3, [r3, #8]
|
|
8002f2c: 494d ldr r1, [pc, #308] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002f2e: 4313 orrs r3, r2
|
|
8002f30: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8002f32: 687b ldr r3, [r7, #4]
|
|
8002f34: 681b ldr r3, [r3, #0]
|
|
8002f36: f003 0301 and.w r3, r3, #1
|
|
8002f3a: 2b00 cmp r3, #0
|
|
8002f3c: d044 beq.n 8002fc8 <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8002f3e: 687b ldr r3, [r7, #4]
|
|
8002f40: 685b ldr r3, [r3, #4]
|
|
8002f42: 2b01 cmp r3, #1
|
|
8002f44: d107 bne.n 8002f56 <HAL_RCC_ClockConfig+0xae>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8002f46: 4b47 ldr r3, [pc, #284] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002f48: 681b ldr r3, [r3, #0]
|
|
8002f4a: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8002f4e: 2b00 cmp r3, #0
|
|
8002f50: d119 bne.n 8002f86 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8002f52: 2301 movs r3, #1
|
|
8002f54: e07f b.n 8003056 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
8002f56: 687b ldr r3, [r7, #4]
|
|
8002f58: 685b ldr r3, [r3, #4]
|
|
8002f5a: 2b02 cmp r3, #2
|
|
8002f5c: d003 beq.n 8002f66 <HAL_RCC_ClockConfig+0xbe>
|
|
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
|
|
8002f5e: 687b ldr r3, [r7, #4]
|
|
8002f60: 685b ldr r3, [r3, #4]
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
8002f62: 2b03 cmp r3, #3
|
|
8002f64: d107 bne.n 8002f76 <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8002f66: 4b3f ldr r3, [pc, #252] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002f68: 681b ldr r3, [r3, #0]
|
|
8002f6a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8002f6e: 2b00 cmp r3, #0
|
|
8002f70: d109 bne.n 8002f86 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8002f72: 2301 movs r3, #1
|
|
8002f74: e06f b.n 8003056 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8002f76: 4b3b ldr r3, [pc, #236] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002f78: 681b ldr r3, [r3, #0]
|
|
8002f7a: f003 0302 and.w r3, r3, #2
|
|
8002f7e: 2b00 cmp r3, #0
|
|
8002f80: d101 bne.n 8002f86 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8002f82: 2301 movs r3, #1
|
|
8002f84: e067 b.n 8003056 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
8002f86: 4b37 ldr r3, [pc, #220] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002f88: 689b ldr r3, [r3, #8]
|
|
8002f8a: f023 0203 bic.w r2, r3, #3
|
|
8002f8e: 687b ldr r3, [r7, #4]
|
|
8002f90: 685b ldr r3, [r3, #4]
|
|
8002f92: 4934 ldr r1, [pc, #208] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002f94: 4313 orrs r3, r2
|
|
8002f96: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8002f98: f7fe f8cc bl 8001134 <HAL_GetTick>
|
|
8002f9c: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8002f9e: e00a b.n 8002fb6 <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8002fa0: f7fe f8c8 bl 8001134 <HAL_GetTick>
|
|
8002fa4: 4602 mov r2, r0
|
|
8002fa6: 68fb ldr r3, [r7, #12]
|
|
8002fa8: 1ad3 subs r3, r2, r3
|
|
8002faa: f241 3288 movw r2, #5000 @ 0x1388
|
|
8002fae: 4293 cmp r3, r2
|
|
8002fb0: d901 bls.n 8002fb6 <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002fb2: 2303 movs r3, #3
|
|
8002fb4: e04f b.n 8003056 <HAL_RCC_ClockConfig+0x1ae>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8002fb6: 4b2b ldr r3, [pc, #172] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002fb8: 689b ldr r3, [r3, #8]
|
|
8002fba: f003 020c and.w r2, r3, #12
|
|
8002fbe: 687b ldr r3, [r7, #4]
|
|
8002fc0: 685b ldr r3, [r3, #4]
|
|
8002fc2: 009b lsls r3, r3, #2
|
|
8002fc4: 429a cmp r2, r3
|
|
8002fc6: d1eb bne.n 8002fa0 <HAL_RCC_ClockConfig+0xf8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8002fc8: 4b25 ldr r3, [pc, #148] @ (8003060 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8002fca: 681b ldr r3, [r3, #0]
|
|
8002fcc: f003 030f and.w r3, r3, #15
|
|
8002fd0: 683a ldr r2, [r7, #0]
|
|
8002fd2: 429a cmp r2, r3
|
|
8002fd4: d20c bcs.n 8002ff0 <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8002fd6: 4b22 ldr r3, [pc, #136] @ (8003060 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8002fd8: 683a ldr r2, [r7, #0]
|
|
8002fda: b2d2 uxtb r2, r2
|
|
8002fdc: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8002fde: 4b20 ldr r3, [pc, #128] @ (8003060 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8002fe0: 681b ldr r3, [r3, #0]
|
|
8002fe2: f003 030f and.w r3, r3, #15
|
|
8002fe6: 683a ldr r2, [r7, #0]
|
|
8002fe8: 429a cmp r2, r3
|
|
8002fea: d001 beq.n 8002ff0 <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
return HAL_ERROR;
|
|
8002fec: 2301 movs r3, #1
|
|
8002fee: e032 b.n 8003056 <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8002ff0: 687b ldr r3, [r7, #4]
|
|
8002ff2: 681b ldr r3, [r3, #0]
|
|
8002ff4: f003 0304 and.w r3, r3, #4
|
|
8002ff8: 2b00 cmp r3, #0
|
|
8002ffa: d008 beq.n 800300e <HAL_RCC_ClockConfig+0x166>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8002ffc: 4b19 ldr r3, [pc, #100] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8002ffe: 689b ldr r3, [r3, #8]
|
|
8003000: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
|
|
8003004: 687b ldr r3, [r7, #4]
|
|
8003006: 68db ldr r3, [r3, #12]
|
|
8003008: 4916 ldr r1, [pc, #88] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800300a: 4313 orrs r3, r2
|
|
800300c: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
800300e: 687b ldr r3, [r7, #4]
|
|
8003010: 681b ldr r3, [r3, #0]
|
|
8003012: f003 0308 and.w r3, r3, #8
|
|
8003016: 2b00 cmp r3, #0
|
|
8003018: d009 beq.n 800302e <HAL_RCC_ClockConfig+0x186>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
800301a: 4b12 ldr r3, [pc, #72] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800301c: 689b ldr r3, [r3, #8]
|
|
800301e: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
8003022: 687b ldr r3, [r7, #4]
|
|
8003024: 691b ldr r3, [r3, #16]
|
|
8003026: 00db lsls r3, r3, #3
|
|
8003028: 490e ldr r1, [pc, #56] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
800302a: 4313 orrs r3, r2
|
|
800302c: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
800302e: f000 fb7f bl 8003730 <HAL_RCC_GetSysClockFreq>
|
|
8003032: 4602 mov r2, r0
|
|
8003034: 4b0b ldr r3, [pc, #44] @ (8003064 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8003036: 689b ldr r3, [r3, #8]
|
|
8003038: 091b lsrs r3, r3, #4
|
|
800303a: f003 030f and.w r3, r3, #15
|
|
800303e: 490a ldr r1, [pc, #40] @ (8003068 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8003040: 5ccb ldrb r3, [r1, r3]
|
|
8003042: fa22 f303 lsr.w r3, r2, r3
|
|
8003046: 4a09 ldr r2, [pc, #36] @ (800306c <HAL_RCC_ClockConfig+0x1c4>)
|
|
8003048: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings */
|
|
HAL_InitTick(uwTickPrio);
|
|
800304a: 4b09 ldr r3, [pc, #36] @ (8003070 <HAL_RCC_ClockConfig+0x1c8>)
|
|
800304c: 681b ldr r3, [r3, #0]
|
|
800304e: 4618 mov r0, r3
|
|
8003050: f7fe f82c bl 80010ac <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
8003054: 2300 movs r3, #0
|
|
}
|
|
8003056: 4618 mov r0, r3
|
|
8003058: 3710 adds r7, #16
|
|
800305a: 46bd mov sp, r7
|
|
800305c: bd80 pop {r7, pc}
|
|
800305e: bf00 nop
|
|
8003060: 40023c00 .word 0x40023c00
|
|
8003064: 40023800 .word 0x40023800
|
|
8003068: 080089d8 .word 0x080089d8
|
|
800306c: 20000000 .word 0x20000000
|
|
8003070: 20000004 .word 0x20000004
|
|
|
|
08003074 <HAL_RCC_GetHCLKFreq>:
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8003074: b480 push {r7}
|
|
8003076: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
8003078: 4b03 ldr r3, [pc, #12] @ (8003088 <HAL_RCC_GetHCLKFreq+0x14>)
|
|
800307a: 681b ldr r3, [r3, #0]
|
|
}
|
|
800307c: 4618 mov r0, r3
|
|
800307e: 46bd mov sp, r7
|
|
8003080: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003084: 4770 bx lr
|
|
8003086: bf00 nop
|
|
8003088: 20000000 .word 0x20000000
|
|
|
|
0800308c <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
800308c: b580 push {r7, lr}
|
|
800308e: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
8003090: f7ff fff0 bl 8003074 <HAL_RCC_GetHCLKFreq>
|
|
8003094: 4602 mov r2, r0
|
|
8003096: 4b05 ldr r3, [pc, #20] @ (80030ac <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
8003098: 689b ldr r3, [r3, #8]
|
|
800309a: 0a9b lsrs r3, r3, #10
|
|
800309c: f003 0307 and.w r3, r3, #7
|
|
80030a0: 4903 ldr r1, [pc, #12] @ (80030b0 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
80030a2: 5ccb ldrb r3, [r1, r3]
|
|
80030a4: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80030a8: 4618 mov r0, r3
|
|
80030aa: bd80 pop {r7, pc}
|
|
80030ac: 40023800 .word 0x40023800
|
|
80030b0: 080089e8 .word 0x080089e8
|
|
|
|
080030b4 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
80030b4: b580 push {r7, lr}
|
|
80030b6: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
80030b8: f7ff ffdc bl 8003074 <HAL_RCC_GetHCLKFreq>
|
|
80030bc: 4602 mov r2, r0
|
|
80030be: 4b05 ldr r3, [pc, #20] @ (80030d4 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
80030c0: 689b ldr r3, [r3, #8]
|
|
80030c2: 0b5b lsrs r3, r3, #13
|
|
80030c4: f003 0307 and.w r3, r3, #7
|
|
80030c8: 4903 ldr r1, [pc, #12] @ (80030d8 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
80030ca: 5ccb ldrb r3, [r1, r3]
|
|
80030cc: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80030d0: 4618 mov r0, r3
|
|
80030d2: bd80 pop {r7, pc}
|
|
80030d4: 40023800 .word 0x40023800
|
|
80030d8: 080089e8 .word 0x080089e8
|
|
|
|
080030dc <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the backup registers) and RCC_BDCR register are set to their reset values.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
80030dc: b580 push {r7, lr}
|
|
80030de: b08c sub sp, #48 @ 0x30
|
|
80030e0: af00 add r7, sp, #0
|
|
80030e2: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
80030e4: 2300 movs r3, #0
|
|
80030e6: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t tmpreg1 = 0U;
|
|
80030e8: 2300 movs r3, #0
|
|
80030ea: 623b str r3, [r7, #32]
|
|
uint32_t plli2sp = 0U;
|
|
80030ec: 2300 movs r3, #0
|
|
80030ee: 61fb str r3, [r7, #28]
|
|
uint32_t plli2sq = 0U;
|
|
80030f0: 2300 movs r3, #0
|
|
80030f2: 61bb str r3, [r7, #24]
|
|
uint32_t plli2sr = 0U;
|
|
80030f4: 2300 movs r3, #0
|
|
80030f6: 617b str r3, [r7, #20]
|
|
uint32_t pllsaip = 0U;
|
|
80030f8: 2300 movs r3, #0
|
|
80030fa: 613b str r3, [r7, #16]
|
|
uint32_t pllsaiq = 0U;
|
|
80030fc: 2300 movs r3, #0
|
|
80030fe: 60fb str r3, [r7, #12]
|
|
uint32_t plli2sused = 0U;
|
|
8003100: 2300 movs r3, #0
|
|
8003102: 62fb str r3, [r7, #44] @ 0x2c
|
|
uint32_t pllsaiused = 0U;
|
|
8003104: 2300 movs r3, #0
|
|
8003106: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Check the peripheral clock selection parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*------------------------ I2S APB1 configuration --------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
|
|
8003108: 687b ldr r3, [r7, #4]
|
|
800310a: 681b ldr r3, [r3, #0]
|
|
800310c: f003 0301 and.w r3, r3, #1
|
|
8003110: 2b00 cmp r3, #0
|
|
8003112: d010 beq.n 8003136 <HAL_RCCEx_PeriphCLKConfig+0x5a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
|
|
|
|
/* Configure I2S Clock source */
|
|
__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
|
|
8003114: 4b6f ldr r3, [pc, #444] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003116: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
800311a: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000
|
|
800311e: 687b ldr r3, [r7, #4]
|
|
8003120: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003122: 496c ldr r1, [pc, #432] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003124: 4313 orrs r3, r2
|
|
8003126: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for I2S */
|
|
if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
|
|
800312a: 687b ldr r3, [r7, #4]
|
|
800312c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800312e: 2b00 cmp r3, #0
|
|
8003130: d101 bne.n 8003136 <HAL_RCCEx_PeriphCLKConfig+0x5a>
|
|
{
|
|
plli2sused = 1U;
|
|
8003132: 2301 movs r3, #1
|
|
8003134: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- I2S APB2 configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
|
|
8003136: 687b ldr r3, [r7, #4]
|
|
8003138: 681b ldr r3, [r3, #0]
|
|
800313a: f003 0302 and.w r3, r3, #2
|
|
800313e: 2b00 cmp r3, #0
|
|
8003140: d010 beq.n 8003164 <HAL_RCCEx_PeriphCLKConfig+0x88>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
|
|
|
|
/* Configure I2S Clock source */
|
|
__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
|
|
8003142: 4b64 ldr r3, [pc, #400] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003144: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8003148: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000
|
|
800314c: 687b ldr r3, [r7, #4]
|
|
800314e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8003150: 4960 ldr r1, [pc, #384] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003152: 4313 orrs r3, r2
|
|
8003154: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for I2S */
|
|
if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
|
|
8003158: 687b ldr r3, [r7, #4]
|
|
800315a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800315c: 2b00 cmp r3, #0
|
|
800315e: d101 bne.n 8003164 <HAL_RCCEx_PeriphCLKConfig+0x88>
|
|
{
|
|
plli2sused = 1U;
|
|
8003160: 2301 movs r3, #1
|
|
8003162: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*--------------------------- SAI1 configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
|
|
8003164: 687b ldr r3, [r7, #4]
|
|
8003166: 681b ldr r3, [r3, #0]
|
|
8003168: f003 0304 and.w r3, r3, #4
|
|
800316c: 2b00 cmp r3, #0
|
|
800316e: d017 beq.n 80031a0 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
/* Configure SAI1 Clock source */
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
8003170: 4b58 ldr r3, [pc, #352] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003172: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8003176: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
800317a: 687b ldr r3, [r7, #4]
|
|
800317c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800317e: 4955 ldr r1, [pc, #340] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003180: 4313 orrs r3, r2
|
|
8003182: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
|
|
8003186: 687b ldr r3, [r7, #4]
|
|
8003188: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800318a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
800318e: d101 bne.n 8003194 <HAL_RCCEx_PeriphCLKConfig+0xb8>
|
|
{
|
|
plli2sused = 1U;
|
|
8003190: 2301 movs r3, #1
|
|
8003192: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
/* Enable the PLLSAI when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
|
|
8003194: 687b ldr r3, [r7, #4]
|
|
8003196: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8003198: 2b00 cmp r3, #0
|
|
800319a: d101 bne.n 80031a0 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|
{
|
|
pllsaiused = 1U;
|
|
800319c: 2301 movs r3, #1
|
|
800319e: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*-------------------------- SAI2 configuration ----------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
|
|
80031a0: 687b ldr r3, [r7, #4]
|
|
80031a2: 681b ldr r3, [r3, #0]
|
|
80031a4: f003 0308 and.w r3, r3, #8
|
|
80031a8: 2b00 cmp r3, #0
|
|
80031aa: d017 beq.n 80031dc <HAL_RCCEx_PeriphCLKConfig+0x100>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
|
|
|
|
/* Configure SAI2 Clock source */
|
|
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
|
|
80031ac: 4b49 ldr r3, [pc, #292] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80031ae: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80031b2: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
80031b6: 687b ldr r3, [r7, #4]
|
|
80031b8: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80031ba: 4946 ldr r1, [pc, #280] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80031bc: 4313 orrs r3, r2
|
|
80031be: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
|
|
/* Enable the PLLI2S when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
|
|
80031c2: 687b ldr r3, [r7, #4]
|
|
80031c4: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80031c6: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80031ca: d101 bne.n 80031d0 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
{
|
|
plli2sused = 1U;
|
|
80031cc: 2301 movs r3, #1
|
|
80031ce: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
/* Enable the PLLSAI when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
|
|
80031d0: 687b ldr r3, [r7, #4]
|
|
80031d2: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80031d4: 2b00 cmp r3, #0
|
|
80031d6: d101 bne.n 80031dc <HAL_RCCEx_PeriphCLKConfig+0x100>
|
|
{
|
|
pllsaiused = 1U;
|
|
80031d8: 2301 movs r3, #1
|
|
80031da: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- RTC configuration --------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
|
80031dc: 687b ldr r3, [r7, #4]
|
|
80031de: 681b ldr r3, [r3, #0]
|
|
80031e0: f003 0320 and.w r3, r3, #32
|
|
80031e4: 2b00 cmp r3, #0
|
|
80031e6: f000 808a beq.w 80032fe <HAL_RCCEx_PeriphCLKConfig+0x222>
|
|
{
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80031ea: 2300 movs r3, #0
|
|
80031ec: 60bb str r3, [r7, #8]
|
|
80031ee: 4b39 ldr r3, [pc, #228] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80031f0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80031f2: 4a38 ldr r2, [pc, #224] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80031f4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80031f8: 6413 str r3, [r2, #64] @ 0x40
|
|
80031fa: 4b36 ldr r3, [pc, #216] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80031fc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80031fe: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003202: 60bb str r3, [r7, #8]
|
|
8003204: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Enable write access to Backup domain */
|
|
PWR->CR |= PWR_CR_DBP;
|
|
8003206: 4b34 ldr r3, [pc, #208] @ (80032d8 <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
8003208: 681b ldr r3, [r3, #0]
|
|
800320a: 4a33 ldr r2, [pc, #204] @ (80032d8 <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
800320c: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8003210: 6013 str r3, [r2, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003212: f7fd ff8f bl 8001134 <HAL_GetTick>
|
|
8003216: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
8003218: e008 b.n 800322c <HAL_RCCEx_PeriphCLKConfig+0x150>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
800321a: f7fd ff8b bl 8001134 <HAL_GetTick>
|
|
800321e: 4602 mov r2, r0
|
|
8003220: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003222: 1ad3 subs r3, r2, r3
|
|
8003224: 2b02 cmp r3, #2
|
|
8003226: d901 bls.n 800322c <HAL_RCCEx_PeriphCLKConfig+0x150>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003228: 2303 movs r3, #3
|
|
800322a: e278 b.n 800371e <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
800322c: 4b2a ldr r3, [pc, #168] @ (80032d8 <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
800322e: 681b ldr r3, [r3, #0]
|
|
8003230: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003234: 2b00 cmp r3, #0
|
|
8003236: d0f0 beq.n 800321a <HAL_RCCEx_PeriphCLKConfig+0x13e>
|
|
}
|
|
}
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
8003238: 4b26 ldr r3, [pc, #152] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800323a: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800323c: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8003240: 623b str r3, [r7, #32]
|
|
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
8003242: 6a3b ldr r3, [r7, #32]
|
|
8003244: 2b00 cmp r3, #0
|
|
8003246: d02f beq.n 80032a8 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
8003248: 687b ldr r3, [r7, #4]
|
|
800324a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800324c: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8003250: 6a3a ldr r2, [r7, #32]
|
|
8003252: 429a cmp r2, r3
|
|
8003254: d028 beq.n 80032a8 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
8003256: 4b1f ldr r3, [pc, #124] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003258: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800325a: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800325e: 623b str r3, [r7, #32]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8003260: 4b1e ldr r3, [pc, #120] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x200>)
|
|
8003262: 2201 movs r2, #1
|
|
8003264: 601a str r2, [r3, #0]
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8003266: 4b1d ldr r3, [pc, #116] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x200>)
|
|
8003268: 2200 movs r2, #0
|
|
800326a: 601a str r2, [r3, #0]
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpreg1;
|
|
800326c: 4a19 ldr r2, [pc, #100] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800326e: 6a3b ldr r3, [r7, #32]
|
|
8003270: 6713 str r3, [r2, #112] @ 0x70
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
|
|
8003272: 4b18 ldr r3, [pc, #96] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8003274: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003276: f003 0301 and.w r3, r3, #1
|
|
800327a: 2b01 cmp r3, #1
|
|
800327c: d114 bne.n 80032a8 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800327e: f7fd ff59 bl 8001134 <HAL_GetTick>
|
|
8003282: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8003284: e00a b.n 800329c <HAL_RCCEx_PeriphCLKConfig+0x1c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003286: f7fd ff55 bl 8001134 <HAL_GetTick>
|
|
800328a: 4602 mov r2, r0
|
|
800328c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800328e: 1ad3 subs r3, r2, r3
|
|
8003290: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003294: 4293 cmp r3, r2
|
|
8003296: d901 bls.n 800329c <HAL_RCCEx_PeriphCLKConfig+0x1c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003298: 2303 movs r3, #3
|
|
800329a: e240 b.n 800371e <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
800329c: 4b0d ldr r3, [pc, #52] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800329e: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80032a0: f003 0302 and.w r3, r3, #2
|
|
80032a4: 2b00 cmp r3, #0
|
|
80032a6: d0ee beq.n 8003286 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
80032a8: 687b ldr r3, [r7, #4]
|
|
80032aa: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80032ac: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80032b0: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
80032b4: d114 bne.n 80032e0 <HAL_RCCEx_PeriphCLKConfig+0x204>
|
|
80032b6: 4b07 ldr r3, [pc, #28] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80032b8: 689b ldr r3, [r3, #8]
|
|
80032ba: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
|
|
80032be: 687b ldr r3, [r7, #4]
|
|
80032c0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80032c2: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000
|
|
80032c6: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80032ca: 4902 ldr r1, [pc, #8] @ (80032d4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80032cc: 4313 orrs r3, r2
|
|
80032ce: 608b str r3, [r1, #8]
|
|
80032d0: e00c b.n 80032ec <HAL_RCCEx_PeriphCLKConfig+0x210>
|
|
80032d2: bf00 nop
|
|
80032d4: 40023800 .word 0x40023800
|
|
80032d8: 40007000 .word 0x40007000
|
|
80032dc: 42470e40 .word 0x42470e40
|
|
80032e0: 4b4a ldr r3, [pc, #296] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80032e2: 689b ldr r3, [r3, #8]
|
|
80032e4: 4a49 ldr r2, [pc, #292] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80032e6: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
|
|
80032ea: 6093 str r3, [r2, #8]
|
|
80032ec: 4b47 ldr r3, [pc, #284] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80032ee: 6f1a ldr r2, [r3, #112] @ 0x70
|
|
80032f0: 687b ldr r3, [r7, #4]
|
|
80032f2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80032f4: f3c3 030b ubfx r3, r3, #0, #12
|
|
80032f8: 4944 ldr r1, [pc, #272] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80032fa: 4313 orrs r3, r2
|
|
80032fc: 670b str r3, [r1, #112] @ 0x70
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- TIM configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
|
|
80032fe: 687b ldr r3, [r7, #4]
|
|
8003300: 681b ldr r3, [r3, #0]
|
|
8003302: f003 0310 and.w r3, r3, #16
|
|
8003306: 2b00 cmp r3, #0
|
|
8003308: d004 beq.n 8003314 <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
{
|
|
/* Configure Timer Prescaler */
|
|
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
|
|
800330a: 687b ldr r3, [r7, #4]
|
|
800330c: f893 2058 ldrb.w r2, [r3, #88] @ 0x58
|
|
8003310: 4b3f ldr r3, [pc, #252] @ (8003410 <HAL_RCCEx_PeriphCLKConfig+0x334>)
|
|
8003312: 601a str r2, [r3, #0]
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- FMPI2C1 Configuration -----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
|
|
8003314: 687b ldr r3, [r7, #4]
|
|
8003316: 681b ldr r3, [r3, #0]
|
|
8003318: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800331c: 2b00 cmp r3, #0
|
|
800331e: d00a beq.n 8003336 <HAL_RCCEx_PeriphCLKConfig+0x25a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
|
|
|
|
/* Configure the FMPI2C1 clock source */
|
|
__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
|
|
8003320: 4b3a ldr r3, [pc, #232] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003322: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003326: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
800332a: 687b ldr r3, [r7, #4]
|
|
800332c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800332e: 4937 ldr r1, [pc, #220] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003330: 4313 orrs r3, r2
|
|
8003332: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*------------------------------ CEC Configuration -------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
|
|
8003336: 687b ldr r3, [r7, #4]
|
|
8003338: 681b ldr r3, [r3, #0]
|
|
800333a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800333e: 2b00 cmp r3, #0
|
|
8003340: d00a beq.n 8003358 <HAL_RCCEx_PeriphCLKConfig+0x27c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
|
|
|
|
/* Configure the CEC clock source */
|
|
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
|
|
8003342: 4b32 ldr r3, [pc, #200] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003344: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003348: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000
|
|
800334c: 687b ldr r3, [r7, #4]
|
|
800334e: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8003350: 492e ldr r1, [pc, #184] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003352: 4313 orrs r3, r2
|
|
8003354: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- CLK48 Configuration ------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
|
|
8003358: 687b ldr r3, [r7, #4]
|
|
800335a: 681b ldr r3, [r3, #0]
|
|
800335c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003360: 2b00 cmp r3, #0
|
|
8003362: d011 beq.n 8003388 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
|
|
|
|
/* Configure the CLK48 clock source */
|
|
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
|
|
8003364: 4b29 ldr r3, [pc, #164] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003366: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800336a: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000
|
|
800336e: 687b ldr r3, [r7, #4]
|
|
8003370: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8003372: 4926 ldr r1, [pc, #152] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003374: 4313 orrs r3, r2
|
|
8003376: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
|
|
/* Enable the PLLSAI when it's used as clock source for CLK48 */
|
|
if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
|
|
800337a: 687b ldr r3, [r7, #4]
|
|
800337c: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800337e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8003382: d101 bne.n 8003388 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
pllsaiused = 1U;
|
|
8003384: 2301 movs r3, #1
|
|
8003386: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- SDIO Configuration -------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
|
|
8003388: 687b ldr r3, [r7, #4]
|
|
800338a: 681b ldr r3, [r3, #0]
|
|
800338c: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8003390: 2b00 cmp r3, #0
|
|
8003392: d00a beq.n 80033aa <HAL_RCCEx_PeriphCLKConfig+0x2ce>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
|
|
|
|
/* Configure the SDIO clock source */
|
|
__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
|
|
8003394: 4b1d ldr r3, [pc, #116] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8003396: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800339a: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
|
|
800339e: 687b ldr r3, [r7, #4]
|
|
80033a0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80033a2: 491a ldr r1, [pc, #104] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80033a4: 4313 orrs r3, r2
|
|
80033a6: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*------------------------------ SPDIFRX Configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
|
80033aa: 687b ldr r3, [r7, #4]
|
|
80033ac: 681b ldr r3, [r3, #0]
|
|
80033ae: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80033b2: 2b00 cmp r3, #0
|
|
80033b4: d011 beq.n 80033da <HAL_RCCEx_PeriphCLKConfig+0x2fe>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
|
|
|
|
/* Configure the SPDIFRX clock source */
|
|
__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
|
|
80033b6: 4b15 ldr r3, [pc, #84] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80033b8: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
80033bc: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
|
|
80033c0: 687b ldr r3, [r7, #4]
|
|
80033c2: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80033c4: 4911 ldr r1, [pc, #68] @ (800340c <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80033c6: 4313 orrs r3, r2
|
|
80033c8: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
|
|
if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
|
|
80033cc: 687b ldr r3, [r7, #4]
|
|
80033ce: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80033d0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
80033d4: d101 bne.n 80033da <HAL_RCCEx_PeriphCLKConfig+0x2fe>
|
|
{
|
|
plli2sused = 1U;
|
|
80033d6: 2301 movs r3, #1
|
|
80033d8: 62fb str r3, [r7, #44] @ 0x2c
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- PLLI2S Configuration ------------------------*/
|
|
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
|
|
I2S on APB2 or SPDIFRX */
|
|
if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
|
|
80033da: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80033dc: 2b01 cmp r3, #1
|
|
80033de: d005 beq.n 80033ec <HAL_RCCEx_PeriphCLKConfig+0x310>
|
|
80033e0: 687b ldr r3, [r7, #4]
|
|
80033e2: 681b ldr r3, [r3, #0]
|
|
80033e4: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
80033e8: f040 80ff bne.w 80035ea <HAL_RCCEx_PeriphCLKConfig+0x50e>
|
|
{
|
|
/* Disable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_DISABLE();
|
|
80033ec: 4b09 ldr r3, [pc, #36] @ (8003414 <HAL_RCCEx_PeriphCLKConfig+0x338>)
|
|
80033ee: 2200 movs r2, #0
|
|
80033f0: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80033f2: f7fd fe9f bl 8001134 <HAL_GetTick>
|
|
80033f6: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLI2S is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
80033f8: e00e b.n 8003418 <HAL_RCCEx_PeriphCLKConfig+0x33c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
80033fa: f7fd fe9b bl 8001134 <HAL_GetTick>
|
|
80033fe: 4602 mov r2, r0
|
|
8003400: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003402: 1ad3 subs r3, r2, r3
|
|
8003404: 2b02 cmp r3, #2
|
|
8003406: d907 bls.n 8003418 <HAL_RCCEx_PeriphCLKConfig+0x33c>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8003408: 2303 movs r3, #3
|
|
800340a: e188 b.n 800371e <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
800340c: 40023800 .word 0x40023800
|
|
8003410: 424711e0 .word 0x424711e0
|
|
8003414: 42470068 .word 0x42470068
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
8003418: 4b7e ldr r3, [pc, #504] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800341a: 681b ldr r3, [r3, #0]
|
|
800341c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8003420: 2b00 cmp r3, #0
|
|
8003422: d1ea bne.n 80033fa <HAL_RCCEx_PeriphCLKConfig+0x31e>
|
|
/* check for common PLLI2S Parameters */
|
|
assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
|
|
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
|
|
|
/*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1)
|
|
8003424: 687b ldr r3, [r7, #4]
|
|
8003426: 681b ldr r3, [r3, #0]
|
|
8003428: f003 0301 and.w r3, r3, #1
|
|
800342c: 2b00 cmp r3, #0
|
|
800342e: d003 beq.n 8003438 <HAL_RCCEx_PeriphCLKConfig+0x35c>
|
|
&& (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
|
|
8003430: 687b ldr r3, [r7, #4]
|
|
8003432: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003434: 2b00 cmp r3, #0
|
|
8003436: d009 beq.n 800344c <HAL_RCCEx_PeriphCLKConfig+0x370>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
|
|
8003438: 687b ldr r3, [r7, #4]
|
|
800343a: 681b ldr r3, [r3, #0]
|
|
800343c: f003 0302 and.w r3, r3, #2
|
|
&& (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
|
|
8003440: 2b00 cmp r3, #0
|
|
8003442: d028 beq.n 8003496 <HAL_RCCEx_PeriphCLKConfig+0x3ba>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
|
|
8003444: 687b ldr r3, [r7, #4]
|
|
8003446: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8003448: 2b00 cmp r3, #0
|
|
800344a: d124 bne.n 8003496 <HAL_RCCEx_PeriphCLKConfig+0x3ba>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
|
|
/* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
|
|
plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
800344c: 4b71 ldr r3, [pc, #452] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800344e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003452: 0c1b lsrs r3, r3, #16
|
|
8003454: f003 0303 and.w r3, r3, #3
|
|
8003458: 3301 adds r3, #1
|
|
800345a: 005b lsls r3, r3, #1
|
|
800345c: 61fb str r3, [r7, #28]
|
|
plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
|
|
800345e: 4b6d ldr r3, [pc, #436] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003460: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003464: 0e1b lsrs r3, r3, #24
|
|
8003466: f003 030f and.w r3, r3, #15
|
|
800346a: 61bb str r3, [r7, #24]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq,
|
|
800346c: 687b ldr r3, [r7, #4]
|
|
800346e: 685a ldr r2, [r3, #4]
|
|
8003470: 687b ldr r3, [r7, #4]
|
|
8003472: 689b ldr r3, [r3, #8]
|
|
8003474: 019b lsls r3, r3, #6
|
|
8003476: 431a orrs r2, r3
|
|
8003478: 69fb ldr r3, [r7, #28]
|
|
800347a: 085b lsrs r3, r3, #1
|
|
800347c: 3b01 subs r3, #1
|
|
800347e: 041b lsls r3, r3, #16
|
|
8003480: 431a orrs r2, r3
|
|
8003482: 69bb ldr r3, [r7, #24]
|
|
8003484: 061b lsls r3, r3, #24
|
|
8003486: 431a orrs r2, r3
|
|
8003488: 687b ldr r3, [r7, #4]
|
|
800348a: 695b ldr r3, [r3, #20]
|
|
800348c: 071b lsls r3, r3, #28
|
|
800348e: 4961 ldr r1, [pc, #388] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003490: 4313 orrs r3, r2
|
|
8003492: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SR);
|
|
}
|
|
|
|
/*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
|
|
8003496: 687b ldr r3, [r7, #4]
|
|
8003498: 681b ldr r3, [r3, #0]
|
|
800349a: f003 0304 and.w r3, r3, #4
|
|
800349e: 2b00 cmp r3, #0
|
|
80034a0: d004 beq.n 80034ac <HAL_RCCEx_PeriphCLKConfig+0x3d0>
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
|
80034a2: 687b ldr r3, [r7, #4]
|
|
80034a4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80034a6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
80034aa: d00a beq.n 80034c2 <HAL_RCCEx_PeriphCLKConfig+0x3e6>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
|
80034ac: 687b ldr r3, [r7, #4]
|
|
80034ae: 681b ldr r3, [r3, #0]
|
|
80034b0: f003 0308 and.w r3, r3, #8
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
|
80034b4: 2b00 cmp r3, #0
|
|
80034b6: d035 beq.n 8003524 <HAL_RCCEx_PeriphCLKConfig+0x448>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
|
80034b8: 687b ldr r3, [r7, #4]
|
|
80034ba: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80034bc: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80034c0: d130 bne.n 8003524 <HAL_RCCEx_PeriphCLKConfig+0x448>
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
/* Check for PLLI2S/DIVQ parameters */
|
|
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
|
|
|
|
/* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
|
|
plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
80034c2: 4b54 ldr r3, [pc, #336] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80034c4: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80034c8: 0c1b lsrs r3, r3, #16
|
|
80034ca: f003 0303 and.w r3, r3, #3
|
|
80034ce: 3301 adds r3, #1
|
|
80034d0: 005b lsls r3, r3, #1
|
|
80034d2: 61fb str r3, [r7, #28]
|
|
plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
80034d4: 4b4f ldr r3, [pc, #316] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80034d6: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80034da: 0f1b lsrs r3, r3, #28
|
|
80034dc: f003 0307 and.w r3, r3, #7
|
|
80034e0: 617b str r3, [r7, #20]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
|
|
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
|
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp,
|
|
80034e2: 687b ldr r3, [r7, #4]
|
|
80034e4: 685a ldr r2, [r3, #4]
|
|
80034e6: 687b ldr r3, [r7, #4]
|
|
80034e8: 689b ldr r3, [r3, #8]
|
|
80034ea: 019b lsls r3, r3, #6
|
|
80034ec: 431a orrs r2, r3
|
|
80034ee: 69fb ldr r3, [r7, #28]
|
|
80034f0: 085b lsrs r3, r3, #1
|
|
80034f2: 3b01 subs r3, #1
|
|
80034f4: 041b lsls r3, r3, #16
|
|
80034f6: 431a orrs r2, r3
|
|
80034f8: 687b ldr r3, [r7, #4]
|
|
80034fa: 691b ldr r3, [r3, #16]
|
|
80034fc: 061b lsls r3, r3, #24
|
|
80034fe: 431a orrs r2, r3
|
|
8003500: 697b ldr r3, [r7, #20]
|
|
8003502: 071b lsls r3, r3, #28
|
|
8003504: 4943 ldr r1, [pc, #268] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8003506: 4313 orrs r3, r2
|
|
8003508: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
|
|
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
|
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
|
|
800350c: 4b41 ldr r3, [pc, #260] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800350e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8003512: f023 021f bic.w r2, r3, #31
|
|
8003516: 687b ldr r3, [r7, #4]
|
|
8003518: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800351a: 3b01 subs r3, #1
|
|
800351c: 493d ldr r1, [pc, #244] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800351e: 4313 orrs r3, r2
|
|
8003520: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
|
8003524: 687b ldr r3, [r7, #4]
|
|
8003526: 681b ldr r3, [r3, #0]
|
|
8003528: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800352c: 2b00 cmp r3, #0
|
|
800352e: d029 beq.n 8003584 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
|
|
&& (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
|
|
8003530: 687b ldr r3, [r7, #4]
|
|
8003532: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8003534: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8003538: d124 bne.n 8003584 <HAL_RCCEx_PeriphCLKConfig+0x4a8>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
|
|
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
|
plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
800353a: 4b36 ldr r3, [pc, #216] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800353c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003540: 0c1b lsrs r3, r3, #16
|
|
8003542: f003 0303 and.w r3, r3, #3
|
|
8003546: 3301 adds r3, #1
|
|
8003548: 005b lsls r3, r3, #1
|
|
800354a: 61bb str r3, [r7, #24]
|
|
plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
800354c: 4b31 ldr r3, [pc, #196] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800354e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8003552: 0f1b lsrs r3, r3, #28
|
|
8003554: f003 0307 and.w r3, r3, #7
|
|
8003558: 617b str r3, [r7, #20]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP,
|
|
800355a: 687b ldr r3, [r7, #4]
|
|
800355c: 685a ldr r2, [r3, #4]
|
|
800355e: 687b ldr r3, [r7, #4]
|
|
8003560: 689b ldr r3, [r3, #8]
|
|
8003562: 019b lsls r3, r3, #6
|
|
8003564: 431a orrs r2, r3
|
|
8003566: 687b ldr r3, [r7, #4]
|
|
8003568: 68db ldr r3, [r3, #12]
|
|
800356a: 085b lsrs r3, r3, #1
|
|
800356c: 3b01 subs r3, #1
|
|
800356e: 041b lsls r3, r3, #16
|
|
8003570: 431a orrs r2, r3
|
|
8003572: 69bb ldr r3, [r7, #24]
|
|
8003574: 061b lsls r3, r3, #24
|
|
8003576: 431a orrs r2, r3
|
|
8003578: 697b ldr r3, [r7, #20]
|
|
800357a: 071b lsls r3, r3, #28
|
|
800357c: 4925 ldr r1, [pc, #148] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800357e: 4313 orrs r3, r2
|
|
8003580: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
plli2sq, plli2sr);
|
|
}
|
|
|
|
/*----------------- In Case of PLLI2S is just selected -----------------*/
|
|
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
|
|
8003584: 687b ldr r3, [r7, #4]
|
|
8003586: 681b ldr r3, [r3, #0]
|
|
8003588: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
800358c: 2b00 cmp r3, #0
|
|
800358e: d016 beq.n 80035be <HAL_RCCEx_PeriphCLKConfig+0x4e2>
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP,
|
|
8003590: 687b ldr r3, [r7, #4]
|
|
8003592: 685a ldr r2, [r3, #4]
|
|
8003594: 687b ldr r3, [r7, #4]
|
|
8003596: 689b ldr r3, [r3, #8]
|
|
8003598: 019b lsls r3, r3, #6
|
|
800359a: 431a orrs r2, r3
|
|
800359c: 687b ldr r3, [r7, #4]
|
|
800359e: 68db ldr r3, [r3, #12]
|
|
80035a0: 085b lsrs r3, r3, #1
|
|
80035a2: 3b01 subs r3, #1
|
|
80035a4: 041b lsls r3, r3, #16
|
|
80035a6: 431a orrs r2, r3
|
|
80035a8: 687b ldr r3, [r7, #4]
|
|
80035aa: 691b ldr r3, [r3, #16]
|
|
80035ac: 061b lsls r3, r3, #24
|
|
80035ae: 431a orrs r2, r3
|
|
80035b0: 687b ldr r3, [r7, #4]
|
|
80035b2: 695b ldr r3, [r3, #20]
|
|
80035b4: 071b lsls r3, r3, #28
|
|
80035b6: 4917 ldr r1, [pc, #92] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80035b8: 4313 orrs r3, r2
|
|
80035ba: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
|
|
}
|
|
|
|
/* Enable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_ENABLE();
|
|
80035be: 4b16 ldr r3, [pc, #88] @ (8003618 <HAL_RCCEx_PeriphCLKConfig+0x53c>)
|
|
80035c0: 2201 movs r2, #1
|
|
80035c2: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80035c4: f7fd fdb6 bl 8001134 <HAL_GetTick>
|
|
80035c8: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLI2S is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
80035ca: e008 b.n 80035de <HAL_RCCEx_PeriphCLKConfig+0x502>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
80035cc: f7fd fdb2 bl 8001134 <HAL_GetTick>
|
|
80035d0: 4602 mov r2, r0
|
|
80035d2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80035d4: 1ad3 subs r3, r2, r3
|
|
80035d6: 2b02 cmp r3, #2
|
|
80035d8: d901 bls.n 80035de <HAL_RCCEx_PeriphCLKConfig+0x502>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
80035da: 2303 movs r3, #3
|
|
80035dc: e09f b.n 800371e <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
80035de: 4b0d ldr r3, [pc, #52] @ (8003614 <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80035e0: 681b ldr r3, [r3, #0]
|
|
80035e2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
80035e6: 2b00 cmp r3, #0
|
|
80035e8: d0f0 beq.n 80035cc <HAL_RCCEx_PeriphCLKConfig+0x4f0>
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- PLLSAI Configuration -----------------------*/
|
|
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
|
|
if (pllsaiused == 1U)
|
|
80035ea: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80035ec: 2b01 cmp r3, #1
|
|
80035ee: f040 8095 bne.w 800371c <HAL_RCCEx_PeriphCLKConfig+0x640>
|
|
{
|
|
/* Disable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_DISABLE();
|
|
80035f2: 4b0a ldr r3, [pc, #40] @ (800361c <HAL_RCCEx_PeriphCLKConfig+0x540>)
|
|
80035f4: 2200 movs r2, #0
|
|
80035f6: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80035f8: f7fd fd9c bl 8001134 <HAL_GetTick>
|
|
80035fc: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLSAI is disabled */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
80035fe: e00f b.n 8003620 <HAL_RCCEx_PeriphCLKConfig+0x544>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
8003600: f7fd fd98 bl 8001134 <HAL_GetTick>
|
|
8003604: 4602 mov r2, r0
|
|
8003606: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003608: 1ad3 subs r3, r2, r3
|
|
800360a: 2b02 cmp r3, #2
|
|
800360c: d908 bls.n 8003620 <HAL_RCCEx_PeriphCLKConfig+0x544>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
800360e: 2303 movs r3, #3
|
|
8003610: e085 b.n 800371e <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
8003612: bf00 nop
|
|
8003614: 40023800 .word 0x40023800
|
|
8003618: 42470068 .word 0x42470068
|
|
800361c: 42470070 .word 0x42470070
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
8003620: 4b41 ldr r3, [pc, #260] @ (8003728 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003622: 681b ldr r3, [r3, #0]
|
|
8003624: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8003628: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
800362c: d0e8 beq.n 8003600 <HAL_RCCEx_PeriphCLKConfig+0x524>
|
|
/* Check the PLLSAI division factors */
|
|
assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
|
|
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
|
|
|
|
/*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
|
|
800362e: 687b ldr r3, [r7, #4]
|
|
8003630: 681b ldr r3, [r3, #0]
|
|
8003632: f003 0304 and.w r3, r3, #4
|
|
8003636: 2b00 cmp r3, #0
|
|
8003638: d003 beq.n 8003642 <HAL_RCCEx_PeriphCLKConfig+0x566>
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
|
|
800363a: 687b ldr r3, [r7, #4]
|
|
800363c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800363e: 2b00 cmp r3, #0
|
|
8003640: d009 beq.n 8003656 <HAL_RCCEx_PeriphCLKConfig+0x57a>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
|
8003642: 687b ldr r3, [r7, #4]
|
|
8003644: 681b ldr r3, [r3, #0]
|
|
8003646: f003 0308 and.w r3, r3, #8
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
|
|
800364a: 2b00 cmp r3, #0
|
|
800364c: d02b beq.n 80036a6 <HAL_RCCEx_PeriphCLKConfig+0x5ca>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
|
800364e: 687b ldr r3, [r7, #4]
|
|
8003650: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8003652: 2b00 cmp r3, #0
|
|
8003654: d127 bne.n 80036a6 <HAL_RCCEx_PeriphCLKConfig+0x5ca>
|
|
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
|
|
/* check for PLLSAI/DIVQ Parameter */
|
|
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
|
|
|
|
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
|
|
pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
|
|
8003656: 4b34 ldr r3, [pc, #208] @ (8003728 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003658: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800365c: 0c1b lsrs r3, r3, #16
|
|
800365e: f003 0303 and.w r3, r3, #3
|
|
8003662: 3301 adds r3, #1
|
|
8003664: 005b lsls r3, r3, #1
|
|
8003666: 613b str r3, [r7, #16]
|
|
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
|
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip,
|
|
8003668: 687b ldr r3, [r7, #4]
|
|
800366a: 699a ldr r2, [r3, #24]
|
|
800366c: 687b ldr r3, [r7, #4]
|
|
800366e: 69db ldr r3, [r3, #28]
|
|
8003670: 019b lsls r3, r3, #6
|
|
8003672: 431a orrs r2, r3
|
|
8003674: 693b ldr r3, [r7, #16]
|
|
8003676: 085b lsrs r3, r3, #1
|
|
8003678: 3b01 subs r3, #1
|
|
800367a: 041b lsls r3, r3, #16
|
|
800367c: 431a orrs r2, r3
|
|
800367e: 687b ldr r3, [r7, #4]
|
|
8003680: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003682: 061b lsls r3, r3, #24
|
|
8003684: 4928 ldr r1, [pc, #160] @ (8003728 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003686: 4313 orrs r3, r2
|
|
8003688: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
|
|
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
|
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
|
|
800368c: 4b26 ldr r3, [pc, #152] @ (8003728 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
800368e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8003692: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
|
|
8003696: 687b ldr r3, [r7, #4]
|
|
8003698: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800369a: 3b01 subs r3, #1
|
|
800369c: 021b lsls r3, r3, #8
|
|
800369e: 4922 ldr r1, [pc, #136] @ (8003728 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
80036a0: 4313 orrs r3, r2
|
|
80036a2: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/
|
|
/* In Case of PLLI2S is selected as source clock for CLK48 */
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
|
|
80036a6: 687b ldr r3, [r7, #4]
|
|
80036a8: 681b ldr r3, [r3, #0]
|
|
80036aa: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80036ae: 2b00 cmp r3, #0
|
|
80036b0: d01d beq.n 80036ee <HAL_RCCEx_PeriphCLKConfig+0x612>
|
|
&& (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
|
|
80036b2: 687b ldr r3, [r7, #4]
|
|
80036b4: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80036b6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
80036ba: d118 bne.n 80036ee <HAL_RCCEx_PeriphCLKConfig+0x612>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
|
|
/* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
|
pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
|
|
80036bc: 4b1a ldr r3, [pc, #104] @ (8003728 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
80036be: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80036c2: 0e1b lsrs r3, r3, #24
|
|
80036c4: f003 030f and.w r3, r3, #15
|
|
80036c8: 60fb str r3, [r7, #12]
|
|
/* Configure the PLLSAI division factors */
|
|
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
|
|
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP,
|
|
80036ca: 687b ldr r3, [r7, #4]
|
|
80036cc: 699a ldr r2, [r3, #24]
|
|
80036ce: 687b ldr r3, [r7, #4]
|
|
80036d0: 69db ldr r3, [r3, #28]
|
|
80036d2: 019b lsls r3, r3, #6
|
|
80036d4: 431a orrs r2, r3
|
|
80036d6: 687b ldr r3, [r7, #4]
|
|
80036d8: 6a1b ldr r3, [r3, #32]
|
|
80036da: 085b lsrs r3, r3, #1
|
|
80036dc: 3b01 subs r3, #1
|
|
80036de: 041b lsls r3, r3, #16
|
|
80036e0: 431a orrs r2, r3
|
|
80036e2: 68fb ldr r3, [r7, #12]
|
|
80036e4: 061b lsls r3, r3, #24
|
|
80036e6: 4910 ldr r1, [pc, #64] @ (8003728 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
80036e8: 4313 orrs r3, r2
|
|
80036ea: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
pllsaiq, 0U);
|
|
}
|
|
|
|
/* Enable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_ENABLE();
|
|
80036ee: 4b0f ldr r3, [pc, #60] @ (800372c <HAL_RCCEx_PeriphCLKConfig+0x650>)
|
|
80036f0: 2201 movs r2, #1
|
|
80036f2: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80036f4: f7fd fd1e bl 8001134 <HAL_GetTick>
|
|
80036f8: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLSAI is ready */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
80036fa: e008 b.n 800370e <HAL_RCCEx_PeriphCLKConfig+0x632>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
80036fc: f7fd fd1a bl 8001134 <HAL_GetTick>
|
|
8003700: 4602 mov r2, r0
|
|
8003702: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003704: 1ad3 subs r3, r2, r3
|
|
8003706: 2b02 cmp r3, #2
|
|
8003708: d901 bls.n 800370e <HAL_RCCEx_PeriphCLKConfig+0x632>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
800370a: 2303 movs r3, #3
|
|
800370c: e007 b.n 800371e <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
800370e: 4b06 ldr r3, [pc, #24] @ (8003728 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8003710: 681b ldr r3, [r3, #0]
|
|
8003712: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8003716: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
800371a: d1ef bne.n 80036fc <HAL_RCCEx_PeriphCLKConfig+0x620>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800371c: 2300 movs r3, #0
|
|
}
|
|
800371e: 4618 mov r0, r3
|
|
8003720: 3730 adds r7, #48 @ 0x30
|
|
8003722: 46bd mov sp, r7
|
|
8003724: bd80 pop {r7, pc}
|
|
8003726: bf00 nop
|
|
8003728: 40023800 .word 0x40023800
|
|
800372c: 42470070 .word 0x42470070
|
|
|
|
08003730 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8003730: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8003734: b0ae sub sp, #184 @ 0xb8
|
|
8003736: af00 add r7, sp, #0
|
|
uint32_t pllm = 0U;
|
|
8003738: 2300 movs r3, #0
|
|
800373a: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
uint32_t pllvco = 0U;
|
|
800373e: 2300 movs r3, #0
|
|
8003740: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
uint32_t pllp = 0U;
|
|
8003744: 2300 movs r3, #0
|
|
8003746: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
uint32_t pllr = 0U;
|
|
800374a: 2300 movs r3, #0
|
|
800374c: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
uint32_t sysclockfreq = 0U;
|
|
8003750: 2300 movs r3, #0
|
|
8003752: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
8003756: 4bcb ldr r3, [pc, #812] @ (8003a84 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8003758: 689b ldr r3, [r3, #8]
|
|
800375a: f003 030c and.w r3, r3, #12
|
|
800375e: 2b0c cmp r3, #12
|
|
8003760: f200 8206 bhi.w 8003b70 <HAL_RCC_GetSysClockFreq+0x440>
|
|
8003764: a201 add r2, pc, #4 @ (adr r2, 800376c <HAL_RCC_GetSysClockFreq+0x3c>)
|
|
8003766: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800376a: bf00 nop
|
|
800376c: 080037a1 .word 0x080037a1
|
|
8003770: 08003b71 .word 0x08003b71
|
|
8003774: 08003b71 .word 0x08003b71
|
|
8003778: 08003b71 .word 0x08003b71
|
|
800377c: 080037a9 .word 0x080037a9
|
|
8003780: 08003b71 .word 0x08003b71
|
|
8003784: 08003b71 .word 0x08003b71
|
|
8003788: 08003b71 .word 0x08003b71
|
|
800378c: 080037b1 .word 0x080037b1
|
|
8003790: 08003b71 .word 0x08003b71
|
|
8003794: 08003b71 .word 0x08003b71
|
|
8003798: 08003b71 .word 0x08003b71
|
|
800379c: 080039a1 .word 0x080039a1
|
|
{
|
|
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
80037a0: 4bb9 ldr r3, [pc, #740] @ (8003a88 <HAL_RCC_GetSysClockFreq+0x358>)
|
|
80037a2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
80037a6: e1e7 b.n 8003b78 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
80037a8: 4bb8 ldr r3, [pc, #736] @ (8003a8c <HAL_RCC_GetSysClockFreq+0x35c>)
|
|
80037aa: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
80037ae: e1e3 b.n 8003b78 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLP */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
80037b0: 4bb4 ldr r3, [pc, #720] @ (8003a84 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
80037b2: 685b ldr r3, [r3, #4]
|
|
80037b4: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
80037b8: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
80037bc: 4bb1 ldr r3, [pc, #708] @ (8003a84 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
80037be: 685b ldr r3, [r3, #4]
|
|
80037c0: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80037c4: 2b00 cmp r3, #0
|
|
80037c6: d071 beq.n 80038ac <HAL_RCC_GetSysClockFreq+0x17c>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
80037c8: 4bae ldr r3, [pc, #696] @ (8003a84 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
80037ca: 685b ldr r3, [r3, #4]
|
|
80037cc: 099b lsrs r3, r3, #6
|
|
80037ce: 2200 movs r2, #0
|
|
80037d0: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
80037d4: f8c7 209c str.w r2, [r7, #156] @ 0x9c
|
|
80037d8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
80037dc: f3c3 0308 ubfx r3, r3, #0, #9
|
|
80037e0: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
80037e4: 2300 movs r3, #0
|
|
80037e6: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
80037ea: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
|
|
80037ee: 4622 mov r2, r4
|
|
80037f0: 462b mov r3, r5
|
|
80037f2: f04f 0000 mov.w r0, #0
|
|
80037f6: f04f 0100 mov.w r1, #0
|
|
80037fa: 0159 lsls r1, r3, #5
|
|
80037fc: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8003800: 0150 lsls r0, r2, #5
|
|
8003802: 4602 mov r2, r0
|
|
8003804: 460b mov r3, r1
|
|
8003806: 4621 mov r1, r4
|
|
8003808: 1a51 subs r1, r2, r1
|
|
800380a: 6439 str r1, [r7, #64] @ 0x40
|
|
800380c: 4629 mov r1, r5
|
|
800380e: eb63 0301 sbc.w r3, r3, r1
|
|
8003812: 647b str r3, [r7, #68] @ 0x44
|
|
8003814: f04f 0200 mov.w r2, #0
|
|
8003818: f04f 0300 mov.w r3, #0
|
|
800381c: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40
|
|
8003820: 4649 mov r1, r9
|
|
8003822: 018b lsls r3, r1, #6
|
|
8003824: 4641 mov r1, r8
|
|
8003826: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
800382a: 4641 mov r1, r8
|
|
800382c: 018a lsls r2, r1, #6
|
|
800382e: 4641 mov r1, r8
|
|
8003830: 1a51 subs r1, r2, r1
|
|
8003832: 63b9 str r1, [r7, #56] @ 0x38
|
|
8003834: 4649 mov r1, r9
|
|
8003836: eb63 0301 sbc.w r3, r3, r1
|
|
800383a: 63fb str r3, [r7, #60] @ 0x3c
|
|
800383c: f04f 0200 mov.w r2, #0
|
|
8003840: f04f 0300 mov.w r3, #0
|
|
8003844: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38
|
|
8003848: 4649 mov r1, r9
|
|
800384a: 00cb lsls r3, r1, #3
|
|
800384c: 4641 mov r1, r8
|
|
800384e: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8003852: 4641 mov r1, r8
|
|
8003854: 00ca lsls r2, r1, #3
|
|
8003856: 4610 mov r0, r2
|
|
8003858: 4619 mov r1, r3
|
|
800385a: 4603 mov r3, r0
|
|
800385c: 4622 mov r2, r4
|
|
800385e: 189b adds r3, r3, r2
|
|
8003860: 633b str r3, [r7, #48] @ 0x30
|
|
8003862: 462b mov r3, r5
|
|
8003864: 460a mov r2, r1
|
|
8003866: eb42 0303 adc.w r3, r2, r3
|
|
800386a: 637b str r3, [r7, #52] @ 0x34
|
|
800386c: f04f 0200 mov.w r2, #0
|
|
8003870: f04f 0300 mov.w r3, #0
|
|
8003874: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30
|
|
8003878: 4629 mov r1, r5
|
|
800387a: 024b lsls r3, r1, #9
|
|
800387c: 4621 mov r1, r4
|
|
800387e: ea43 53d1 orr.w r3, r3, r1, lsr #23
|
|
8003882: 4621 mov r1, r4
|
|
8003884: 024a lsls r2, r1, #9
|
|
8003886: 4610 mov r0, r2
|
|
8003888: 4619 mov r1, r3
|
|
800388a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
800388e: 2200 movs r2, #0
|
|
8003890: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
8003894: f8c7 208c str.w r2, [r7, #140] @ 0x8c
|
|
8003898: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88
|
|
800389c: f7fc fcb2 bl 8000204 <__aeabi_uldivmod>
|
|
80038a0: 4602 mov r2, r0
|
|
80038a2: 460b mov r3, r1
|
|
80038a4: 4613 mov r3, r2
|
|
80038a6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
80038aa: e067 b.n 800397c <HAL_RCC_GetSysClockFreq+0x24c>
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
80038ac: 4b75 ldr r3, [pc, #468] @ (8003a84 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
80038ae: 685b ldr r3, [r3, #4]
|
|
80038b0: 099b lsrs r3, r3, #6
|
|
80038b2: 2200 movs r2, #0
|
|
80038b4: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
80038b8: f8c7 2084 str.w r2, [r7, #132] @ 0x84
|
|
80038bc: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
80038c0: f3c3 0308 ubfx r3, r3, #0, #9
|
|
80038c4: 67bb str r3, [r7, #120] @ 0x78
|
|
80038c6: 2300 movs r3, #0
|
|
80038c8: 67fb str r3, [r7, #124] @ 0x7c
|
|
80038ca: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78
|
|
80038ce: 4622 mov r2, r4
|
|
80038d0: 462b mov r3, r5
|
|
80038d2: f04f 0000 mov.w r0, #0
|
|
80038d6: f04f 0100 mov.w r1, #0
|
|
80038da: 0159 lsls r1, r3, #5
|
|
80038dc: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
80038e0: 0150 lsls r0, r2, #5
|
|
80038e2: 4602 mov r2, r0
|
|
80038e4: 460b mov r3, r1
|
|
80038e6: 4621 mov r1, r4
|
|
80038e8: 1a51 subs r1, r2, r1
|
|
80038ea: 62b9 str r1, [r7, #40] @ 0x28
|
|
80038ec: 4629 mov r1, r5
|
|
80038ee: eb63 0301 sbc.w r3, r3, r1
|
|
80038f2: 62fb str r3, [r7, #44] @ 0x2c
|
|
80038f4: f04f 0200 mov.w r2, #0
|
|
80038f8: f04f 0300 mov.w r3, #0
|
|
80038fc: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28
|
|
8003900: 4649 mov r1, r9
|
|
8003902: 018b lsls r3, r1, #6
|
|
8003904: 4641 mov r1, r8
|
|
8003906: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
800390a: 4641 mov r1, r8
|
|
800390c: 018a lsls r2, r1, #6
|
|
800390e: 4641 mov r1, r8
|
|
8003910: ebb2 0a01 subs.w sl, r2, r1
|
|
8003914: 4649 mov r1, r9
|
|
8003916: eb63 0b01 sbc.w fp, r3, r1
|
|
800391a: f04f 0200 mov.w r2, #0
|
|
800391e: f04f 0300 mov.w r3, #0
|
|
8003922: ea4f 03cb mov.w r3, fp, lsl #3
|
|
8003926: ea43 735a orr.w r3, r3, sl, lsr #29
|
|
800392a: ea4f 02ca mov.w r2, sl, lsl #3
|
|
800392e: 4692 mov sl, r2
|
|
8003930: 469b mov fp, r3
|
|
8003932: 4623 mov r3, r4
|
|
8003934: eb1a 0303 adds.w r3, sl, r3
|
|
8003938: 623b str r3, [r7, #32]
|
|
800393a: 462b mov r3, r5
|
|
800393c: eb4b 0303 adc.w r3, fp, r3
|
|
8003940: 627b str r3, [r7, #36] @ 0x24
|
|
8003942: f04f 0200 mov.w r2, #0
|
|
8003946: f04f 0300 mov.w r3, #0
|
|
800394a: e9d7 4508 ldrd r4, r5, [r7, #32]
|
|
800394e: 4629 mov r1, r5
|
|
8003950: 028b lsls r3, r1, #10
|
|
8003952: 4621 mov r1, r4
|
|
8003954: ea43 5391 orr.w r3, r3, r1, lsr #22
|
|
8003958: 4621 mov r1, r4
|
|
800395a: 028a lsls r2, r1, #10
|
|
800395c: 4610 mov r0, r2
|
|
800395e: 4619 mov r1, r3
|
|
8003960: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8003964: 2200 movs r2, #0
|
|
8003966: 673b str r3, [r7, #112] @ 0x70
|
|
8003968: 677a str r2, [r7, #116] @ 0x74
|
|
800396a: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70
|
|
800396e: f7fc fc49 bl 8000204 <__aeabi_uldivmod>
|
|
8003972: 4602 mov r2, r0
|
|
8003974: 460b mov r3, r1
|
|
8003976: 4613 mov r3, r2
|
|
8003978: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
}
|
|
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
|
|
800397c: 4b41 ldr r3, [pc, #260] @ (8003a84 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
800397e: 685b ldr r3, [r3, #4]
|
|
8003980: 0c1b lsrs r3, r3, #16
|
|
8003982: f003 0303 and.w r3, r3, #3
|
|
8003986: 3301 adds r3, #1
|
|
8003988: 005b lsls r3, r3, #1
|
|
800398a: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
|
|
sysclockfreq = pllvco / pllp;
|
|
800398e: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
8003992: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8003996: fbb2 f3f3 udiv r3, r2, r3
|
|
800399a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
800399e: e0eb b.n 8003b78 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLR */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
80039a0: 4b38 ldr r3, [pc, #224] @ (8003a84 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
80039a2: 685b ldr r3, [r3, #4]
|
|
80039a4: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
80039a8: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
80039ac: 4b35 ldr r3, [pc, #212] @ (8003a84 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
80039ae: 685b ldr r3, [r3, #4]
|
|
80039b0: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80039b4: 2b00 cmp r3, #0
|
|
80039b6: d06b beq.n 8003a90 <HAL_RCC_GetSysClockFreq+0x360>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
80039b8: 4b32 ldr r3, [pc, #200] @ (8003a84 <HAL_RCC_GetSysClockFreq+0x354>)
|
|
80039ba: 685b ldr r3, [r3, #4]
|
|
80039bc: 099b lsrs r3, r3, #6
|
|
80039be: 2200 movs r2, #0
|
|
80039c0: 66bb str r3, [r7, #104] @ 0x68
|
|
80039c2: 66fa str r2, [r7, #108] @ 0x6c
|
|
80039c4: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
80039c6: f3c3 0308 ubfx r3, r3, #0, #9
|
|
80039ca: 663b str r3, [r7, #96] @ 0x60
|
|
80039cc: 2300 movs r3, #0
|
|
80039ce: 667b str r3, [r7, #100] @ 0x64
|
|
80039d0: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60
|
|
80039d4: 4622 mov r2, r4
|
|
80039d6: 462b mov r3, r5
|
|
80039d8: f04f 0000 mov.w r0, #0
|
|
80039dc: f04f 0100 mov.w r1, #0
|
|
80039e0: 0159 lsls r1, r3, #5
|
|
80039e2: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
80039e6: 0150 lsls r0, r2, #5
|
|
80039e8: 4602 mov r2, r0
|
|
80039ea: 460b mov r3, r1
|
|
80039ec: 4621 mov r1, r4
|
|
80039ee: 1a51 subs r1, r2, r1
|
|
80039f0: 61b9 str r1, [r7, #24]
|
|
80039f2: 4629 mov r1, r5
|
|
80039f4: eb63 0301 sbc.w r3, r3, r1
|
|
80039f8: 61fb str r3, [r7, #28]
|
|
80039fa: f04f 0200 mov.w r2, #0
|
|
80039fe: f04f 0300 mov.w r3, #0
|
|
8003a02: e9d7 ab06 ldrd sl, fp, [r7, #24]
|
|
8003a06: 4659 mov r1, fp
|
|
8003a08: 018b lsls r3, r1, #6
|
|
8003a0a: 4651 mov r1, sl
|
|
8003a0c: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8003a10: 4651 mov r1, sl
|
|
8003a12: 018a lsls r2, r1, #6
|
|
8003a14: 4651 mov r1, sl
|
|
8003a16: ebb2 0801 subs.w r8, r2, r1
|
|
8003a1a: 4659 mov r1, fp
|
|
8003a1c: eb63 0901 sbc.w r9, r3, r1
|
|
8003a20: f04f 0200 mov.w r2, #0
|
|
8003a24: f04f 0300 mov.w r3, #0
|
|
8003a28: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8003a2c: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8003a30: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
8003a34: 4690 mov r8, r2
|
|
8003a36: 4699 mov r9, r3
|
|
8003a38: 4623 mov r3, r4
|
|
8003a3a: eb18 0303 adds.w r3, r8, r3
|
|
8003a3e: 613b str r3, [r7, #16]
|
|
8003a40: 462b mov r3, r5
|
|
8003a42: eb49 0303 adc.w r3, r9, r3
|
|
8003a46: 617b str r3, [r7, #20]
|
|
8003a48: f04f 0200 mov.w r2, #0
|
|
8003a4c: f04f 0300 mov.w r3, #0
|
|
8003a50: e9d7 4504 ldrd r4, r5, [r7, #16]
|
|
8003a54: 4629 mov r1, r5
|
|
8003a56: 024b lsls r3, r1, #9
|
|
8003a58: 4621 mov r1, r4
|
|
8003a5a: ea43 53d1 orr.w r3, r3, r1, lsr #23
|
|
8003a5e: 4621 mov r1, r4
|
|
8003a60: 024a lsls r2, r1, #9
|
|
8003a62: 4610 mov r0, r2
|
|
8003a64: 4619 mov r1, r3
|
|
8003a66: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8003a6a: 2200 movs r2, #0
|
|
8003a6c: 65bb str r3, [r7, #88] @ 0x58
|
|
8003a6e: 65fa str r2, [r7, #92] @ 0x5c
|
|
8003a70: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
|
|
8003a74: f7fc fbc6 bl 8000204 <__aeabi_uldivmod>
|
|
8003a78: 4602 mov r2, r0
|
|
8003a7a: 460b mov r3, r1
|
|
8003a7c: 4613 mov r3, r2
|
|
8003a7e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8003a82: e065 b.n 8003b50 <HAL_RCC_GetSysClockFreq+0x420>
|
|
8003a84: 40023800 .word 0x40023800
|
|
8003a88: 00f42400 .word 0x00f42400
|
|
8003a8c: 007a1200 .word 0x007a1200
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8003a90: 4b3d ldr r3, [pc, #244] @ (8003b88 <HAL_RCC_GetSysClockFreq+0x458>)
|
|
8003a92: 685b ldr r3, [r3, #4]
|
|
8003a94: 099b lsrs r3, r3, #6
|
|
8003a96: 2200 movs r2, #0
|
|
8003a98: 4618 mov r0, r3
|
|
8003a9a: 4611 mov r1, r2
|
|
8003a9c: f3c0 0308 ubfx r3, r0, #0, #9
|
|
8003aa0: 653b str r3, [r7, #80] @ 0x50
|
|
8003aa2: 2300 movs r3, #0
|
|
8003aa4: 657b str r3, [r7, #84] @ 0x54
|
|
8003aa6: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50
|
|
8003aaa: 4642 mov r2, r8
|
|
8003aac: 464b mov r3, r9
|
|
8003aae: f04f 0000 mov.w r0, #0
|
|
8003ab2: f04f 0100 mov.w r1, #0
|
|
8003ab6: 0159 lsls r1, r3, #5
|
|
8003ab8: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8003abc: 0150 lsls r0, r2, #5
|
|
8003abe: 4602 mov r2, r0
|
|
8003ac0: 460b mov r3, r1
|
|
8003ac2: 4641 mov r1, r8
|
|
8003ac4: 1a51 subs r1, r2, r1
|
|
8003ac6: 60b9 str r1, [r7, #8]
|
|
8003ac8: 4649 mov r1, r9
|
|
8003aca: eb63 0301 sbc.w r3, r3, r1
|
|
8003ace: 60fb str r3, [r7, #12]
|
|
8003ad0: f04f 0200 mov.w r2, #0
|
|
8003ad4: f04f 0300 mov.w r3, #0
|
|
8003ad8: e9d7 ab02 ldrd sl, fp, [r7, #8]
|
|
8003adc: 4659 mov r1, fp
|
|
8003ade: 018b lsls r3, r1, #6
|
|
8003ae0: 4651 mov r1, sl
|
|
8003ae2: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8003ae6: 4651 mov r1, sl
|
|
8003ae8: 018a lsls r2, r1, #6
|
|
8003aea: 4651 mov r1, sl
|
|
8003aec: 1a54 subs r4, r2, r1
|
|
8003aee: 4659 mov r1, fp
|
|
8003af0: eb63 0501 sbc.w r5, r3, r1
|
|
8003af4: f04f 0200 mov.w r2, #0
|
|
8003af8: f04f 0300 mov.w r3, #0
|
|
8003afc: 00eb lsls r3, r5, #3
|
|
8003afe: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
8003b02: 00e2 lsls r2, r4, #3
|
|
8003b04: 4614 mov r4, r2
|
|
8003b06: 461d mov r5, r3
|
|
8003b08: 4643 mov r3, r8
|
|
8003b0a: 18e3 adds r3, r4, r3
|
|
8003b0c: 603b str r3, [r7, #0]
|
|
8003b0e: 464b mov r3, r9
|
|
8003b10: eb45 0303 adc.w r3, r5, r3
|
|
8003b14: 607b str r3, [r7, #4]
|
|
8003b16: f04f 0200 mov.w r2, #0
|
|
8003b1a: f04f 0300 mov.w r3, #0
|
|
8003b1e: e9d7 4500 ldrd r4, r5, [r7]
|
|
8003b22: 4629 mov r1, r5
|
|
8003b24: 028b lsls r3, r1, #10
|
|
8003b26: 4621 mov r1, r4
|
|
8003b28: ea43 5391 orr.w r3, r3, r1, lsr #22
|
|
8003b2c: 4621 mov r1, r4
|
|
8003b2e: 028a lsls r2, r1, #10
|
|
8003b30: 4610 mov r0, r2
|
|
8003b32: 4619 mov r1, r3
|
|
8003b34: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8003b38: 2200 movs r2, #0
|
|
8003b3a: 64bb str r3, [r7, #72] @ 0x48
|
|
8003b3c: 64fa str r2, [r7, #76] @ 0x4c
|
|
8003b3e: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
|
|
8003b42: f7fc fb5f bl 8000204 <__aeabi_uldivmod>
|
|
8003b46: 4602 mov r2, r0
|
|
8003b48: 460b mov r3, r1
|
|
8003b4a: 4613 mov r3, r2
|
|
8003b4c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
}
|
|
pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
|
|
8003b50: 4b0d ldr r3, [pc, #52] @ (8003b88 <HAL_RCC_GetSysClockFreq+0x458>)
|
|
8003b52: 685b ldr r3, [r3, #4]
|
|
8003b54: 0f1b lsrs r3, r3, #28
|
|
8003b56: f003 0307 and.w r3, r3, #7
|
|
8003b5a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
|
|
sysclockfreq = pllvco / pllr;
|
|
8003b5e: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
8003b62: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
8003b66: fbb2 f3f3 udiv r3, r2, r3
|
|
8003b6a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8003b6e: e003 b.n 8003b78 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
default:
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8003b70: 4b06 ldr r3, [pc, #24] @ (8003b8c <HAL_RCC_GetSysClockFreq+0x45c>)
|
|
8003b72: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8003b76: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8003b78: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
|
|
}
|
|
8003b7c: 4618 mov r0, r3
|
|
8003b7e: 37b8 adds r7, #184 @ 0xb8
|
|
8003b80: 46bd mov sp, r7
|
|
8003b82: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8003b86: bf00 nop
|
|
8003b88: 40023800 .word 0x40023800
|
|
8003b8c: 00f42400 .word 0x00f42400
|
|
|
|
08003b90 <HAL_RCC_OscConfig>:
|
|
* @note This function add the PLL/PLLR factor management during PLL configuration this feature
|
|
* is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8003b90: b580 push {r7, lr}
|
|
8003b92: b086 sub sp, #24
|
|
8003b94: af00 add r7, sp, #0
|
|
8003b96: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8003b98: 687b ldr r3, [r7, #4]
|
|
8003b9a: 2b00 cmp r3, #0
|
|
8003b9c: d101 bne.n 8003ba2 <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8003b9e: 2301 movs r3, #1
|
|
8003ba0: e28d b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8003ba2: 687b ldr r3, [r7, #4]
|
|
8003ba4: 681b ldr r3, [r3, #0]
|
|
8003ba6: f003 0301 and.w r3, r3, #1
|
|
8003baa: 2b00 cmp r3, #0
|
|
8003bac: f000 8083 beq.w 8003cb6 <HAL_RCC_OscConfig+0x126>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
|
|
#if defined(STM32F446xx)
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
8003bb0: 4b94 ldr r3, [pc, #592] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003bb2: 689b ldr r3, [r3, #8]
|
|
8003bb4: f003 030c and.w r3, r3, #12
|
|
8003bb8: 2b04 cmp r3, #4
|
|
8003bba: d019 beq.n 8003bf0 <HAL_RCC_OscConfig+0x60>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
8003bbc: 4b91 ldr r3, [pc, #580] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003bbe: 689b ldr r3, [r3, #8]
|
|
8003bc0: f003 030c and.w r3, r3, #12
|
|
|| \
|
|
8003bc4: 2b08 cmp r3, #8
|
|
8003bc6: d106 bne.n 8003bd6 <HAL_RCC_OscConfig+0x46>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
8003bc8: 4b8e ldr r3, [pc, #568] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003bca: 685b ldr r3, [r3, #4]
|
|
8003bcc: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8003bd0: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
8003bd4: d00c beq.n 8003bf0 <HAL_RCC_OscConfig+0x60>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
8003bd6: 4b8b ldr r3, [pc, #556] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003bd8: 689b ldr r3, [r3, #8]
|
|
8003bda: f003 030c and.w r3, r3, #12
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
8003bde: 2b0c cmp r3, #12
|
|
8003be0: d112 bne.n 8003c08 <HAL_RCC_OscConfig+0x78>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
8003be2: 4b88 ldr r3, [pc, #544] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003be4: 685b ldr r3, [r3, #4]
|
|
8003be6: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8003bea: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
8003bee: d10b bne.n 8003c08 <HAL_RCC_OscConfig+0x78>
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
#endif /* STM32F446xx */
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8003bf0: 4b84 ldr r3, [pc, #528] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003bf2: 681b ldr r3, [r3, #0]
|
|
8003bf4: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003bf8: 2b00 cmp r3, #0
|
|
8003bfa: d05b beq.n 8003cb4 <HAL_RCC_OscConfig+0x124>
|
|
8003bfc: 687b ldr r3, [r7, #4]
|
|
8003bfe: 685b ldr r3, [r3, #4]
|
|
8003c00: 2b00 cmp r3, #0
|
|
8003c02: d157 bne.n 8003cb4 <HAL_RCC_OscConfig+0x124>
|
|
{
|
|
return HAL_ERROR;
|
|
8003c04: 2301 movs r3, #1
|
|
8003c06: e25a b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8003c08: 687b ldr r3, [r7, #4]
|
|
8003c0a: 685b ldr r3, [r3, #4]
|
|
8003c0c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8003c10: d106 bne.n 8003c20 <HAL_RCC_OscConfig+0x90>
|
|
8003c12: 4b7c ldr r3, [pc, #496] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003c14: 681b ldr r3, [r3, #0]
|
|
8003c16: 4a7b ldr r2, [pc, #492] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003c18: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8003c1c: 6013 str r3, [r2, #0]
|
|
8003c1e: e01d b.n 8003c5c <HAL_RCC_OscConfig+0xcc>
|
|
8003c20: 687b ldr r3, [r7, #4]
|
|
8003c22: 685b ldr r3, [r3, #4]
|
|
8003c24: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8003c28: d10c bne.n 8003c44 <HAL_RCC_OscConfig+0xb4>
|
|
8003c2a: 4b76 ldr r3, [pc, #472] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003c2c: 681b ldr r3, [r3, #0]
|
|
8003c2e: 4a75 ldr r2, [pc, #468] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003c30: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8003c34: 6013 str r3, [r2, #0]
|
|
8003c36: 4b73 ldr r3, [pc, #460] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003c38: 681b ldr r3, [r3, #0]
|
|
8003c3a: 4a72 ldr r2, [pc, #456] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003c3c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8003c40: 6013 str r3, [r2, #0]
|
|
8003c42: e00b b.n 8003c5c <HAL_RCC_OscConfig+0xcc>
|
|
8003c44: 4b6f ldr r3, [pc, #444] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003c46: 681b ldr r3, [r3, #0]
|
|
8003c48: 4a6e ldr r2, [pc, #440] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003c4a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8003c4e: 6013 str r3, [r2, #0]
|
|
8003c50: 4b6c ldr r3, [pc, #432] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003c52: 681b ldr r3, [r3, #0]
|
|
8003c54: 4a6b ldr r2, [pc, #428] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003c56: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8003c5a: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
|
|
8003c5c: 687b ldr r3, [r7, #4]
|
|
8003c5e: 685b ldr r3, [r3, #4]
|
|
8003c60: 2b00 cmp r3, #0
|
|
8003c62: d013 beq.n 8003c8c <HAL_RCC_OscConfig+0xfc>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003c64: f7fd fa66 bl 8001134 <HAL_GetTick>
|
|
8003c68: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8003c6a: e008 b.n 8003c7e <HAL_RCC_OscConfig+0xee>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8003c6c: f7fd fa62 bl 8001134 <HAL_GetTick>
|
|
8003c70: 4602 mov r2, r0
|
|
8003c72: 693b ldr r3, [r7, #16]
|
|
8003c74: 1ad3 subs r3, r2, r3
|
|
8003c76: 2b64 cmp r3, #100 @ 0x64
|
|
8003c78: d901 bls.n 8003c7e <HAL_RCC_OscConfig+0xee>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003c7a: 2303 movs r3, #3
|
|
8003c7c: e21f b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8003c7e: 4b61 ldr r3, [pc, #388] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003c80: 681b ldr r3, [r3, #0]
|
|
8003c82: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003c86: 2b00 cmp r3, #0
|
|
8003c88: d0f0 beq.n 8003c6c <HAL_RCC_OscConfig+0xdc>
|
|
8003c8a: e014 b.n 8003cb6 <HAL_RCC_OscConfig+0x126>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003c8c: f7fd fa52 bl 8001134 <HAL_GetTick>
|
|
8003c90: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is bypassed or disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8003c92: e008 b.n 8003ca6 <HAL_RCC_OscConfig+0x116>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8003c94: f7fd fa4e bl 8001134 <HAL_GetTick>
|
|
8003c98: 4602 mov r2, r0
|
|
8003c9a: 693b ldr r3, [r7, #16]
|
|
8003c9c: 1ad3 subs r3, r2, r3
|
|
8003c9e: 2b64 cmp r3, #100 @ 0x64
|
|
8003ca0: d901 bls.n 8003ca6 <HAL_RCC_OscConfig+0x116>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003ca2: 2303 movs r3, #3
|
|
8003ca4: e20b b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8003ca6: 4b57 ldr r3, [pc, #348] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003ca8: 681b ldr r3, [r3, #0]
|
|
8003caa: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003cae: 2b00 cmp r3, #0
|
|
8003cb0: d1f0 bne.n 8003c94 <HAL_RCC_OscConfig+0x104>
|
|
8003cb2: e000 b.n 8003cb6 <HAL_RCC_OscConfig+0x126>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8003cb4: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8003cb6: 687b ldr r3, [r7, #4]
|
|
8003cb8: 681b ldr r3, [r3, #0]
|
|
8003cba: f003 0302 and.w r3, r3, #2
|
|
8003cbe: 2b00 cmp r3, #0
|
|
8003cc0: d06f beq.n 8003da2 <HAL_RCC_OscConfig+0x212>
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
#if defined(STM32F446xx)
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
|
|
8003cc2: 4b50 ldr r3, [pc, #320] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003cc4: 689b ldr r3, [r3, #8]
|
|
8003cc6: f003 030c and.w r3, r3, #12
|
|
8003cca: 2b00 cmp r3, #0
|
|
8003ccc: d017 beq.n 8003cfe <HAL_RCC_OscConfig+0x16e>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
8003cce: 4b4d ldr r3, [pc, #308] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003cd0: 689b ldr r3, [r3, #8]
|
|
8003cd2: f003 030c and.w r3, r3, #12
|
|
|| \
|
|
8003cd6: 2b08 cmp r3, #8
|
|
8003cd8: d105 bne.n 8003ce6 <HAL_RCC_OscConfig+0x156>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
8003cda: 4b4a ldr r3, [pc, #296] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003cdc: 685b ldr r3, [r3, #4]
|
|
8003cde: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8003ce2: 2b00 cmp r3, #0
|
|
8003ce4: d00b beq.n 8003cfe <HAL_RCC_OscConfig+0x16e>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
8003ce6: 4b47 ldr r3, [pc, #284] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003ce8: 689b ldr r3, [r3, #8]
|
|
8003cea: f003 030c and.w r3, r3, #12
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
8003cee: 2b0c cmp r3, #12
|
|
8003cf0: d11c bne.n 8003d2c <HAL_RCC_OscConfig+0x19c>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
8003cf2: 4b44 ldr r3, [pc, #272] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003cf4: 685b ldr r3, [r3, #4]
|
|
8003cf6: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8003cfa: 2b00 cmp r3, #0
|
|
8003cfc: d116 bne.n 8003d2c <HAL_RCC_OscConfig+0x19c>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
#endif /* STM32F446xx */
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8003cfe: 4b41 ldr r3, [pc, #260] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003d00: 681b ldr r3, [r3, #0]
|
|
8003d02: f003 0302 and.w r3, r3, #2
|
|
8003d06: 2b00 cmp r3, #0
|
|
8003d08: d005 beq.n 8003d16 <HAL_RCC_OscConfig+0x186>
|
|
8003d0a: 687b ldr r3, [r7, #4]
|
|
8003d0c: 68db ldr r3, [r3, #12]
|
|
8003d0e: 2b01 cmp r3, #1
|
|
8003d10: d001 beq.n 8003d16 <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
return HAL_ERROR;
|
|
8003d12: 2301 movs r3, #1
|
|
8003d14: e1d3 b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8003d16: 4b3b ldr r3, [pc, #236] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003d18: 681b ldr r3, [r3, #0]
|
|
8003d1a: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8003d1e: 687b ldr r3, [r7, #4]
|
|
8003d20: 691b ldr r3, [r3, #16]
|
|
8003d22: 00db lsls r3, r3, #3
|
|
8003d24: 4937 ldr r1, [pc, #220] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003d26: 4313 orrs r3, r2
|
|
8003d28: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8003d2a: e03a b.n 8003da2 <HAL_RCC_OscConfig+0x212>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
|
|
8003d2c: 687b ldr r3, [r7, #4]
|
|
8003d2e: 68db ldr r3, [r3, #12]
|
|
8003d30: 2b00 cmp r3, #0
|
|
8003d32: d020 beq.n 8003d76 <HAL_RCC_OscConfig+0x1e6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8003d34: 4b34 ldr r3, [pc, #208] @ (8003e08 <HAL_RCC_OscConfig+0x278>)
|
|
8003d36: 2201 movs r2, #1
|
|
8003d38: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003d3a: f7fd f9fb bl 8001134 <HAL_GetTick>
|
|
8003d3e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8003d40: e008 b.n 8003d54 <HAL_RCC_OscConfig+0x1c4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8003d42: f7fd f9f7 bl 8001134 <HAL_GetTick>
|
|
8003d46: 4602 mov r2, r0
|
|
8003d48: 693b ldr r3, [r7, #16]
|
|
8003d4a: 1ad3 subs r3, r2, r3
|
|
8003d4c: 2b02 cmp r3, #2
|
|
8003d4e: d901 bls.n 8003d54 <HAL_RCC_OscConfig+0x1c4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003d50: 2303 movs r3, #3
|
|
8003d52: e1b4 b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8003d54: 4b2b ldr r3, [pc, #172] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003d56: 681b ldr r3, [r3, #0]
|
|
8003d58: f003 0302 and.w r3, r3, #2
|
|
8003d5c: 2b00 cmp r3, #0
|
|
8003d5e: d0f0 beq.n 8003d42 <HAL_RCC_OscConfig+0x1b2>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8003d60: 4b28 ldr r3, [pc, #160] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003d62: 681b ldr r3, [r3, #0]
|
|
8003d64: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8003d68: 687b ldr r3, [r7, #4]
|
|
8003d6a: 691b ldr r3, [r3, #16]
|
|
8003d6c: 00db lsls r3, r3, #3
|
|
8003d6e: 4925 ldr r1, [pc, #148] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003d70: 4313 orrs r3, r2
|
|
8003d72: 600b str r3, [r1, #0]
|
|
8003d74: e015 b.n 8003da2 <HAL_RCC_OscConfig+0x212>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8003d76: 4b24 ldr r3, [pc, #144] @ (8003e08 <HAL_RCC_OscConfig+0x278>)
|
|
8003d78: 2200 movs r2, #0
|
|
8003d7a: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003d7c: f7fd f9da bl 8001134 <HAL_GetTick>
|
|
8003d80: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8003d82: e008 b.n 8003d96 <HAL_RCC_OscConfig+0x206>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8003d84: f7fd f9d6 bl 8001134 <HAL_GetTick>
|
|
8003d88: 4602 mov r2, r0
|
|
8003d8a: 693b ldr r3, [r7, #16]
|
|
8003d8c: 1ad3 subs r3, r2, r3
|
|
8003d8e: 2b02 cmp r3, #2
|
|
8003d90: d901 bls.n 8003d96 <HAL_RCC_OscConfig+0x206>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003d92: 2303 movs r3, #3
|
|
8003d94: e193 b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8003d96: 4b1b ldr r3, [pc, #108] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003d98: 681b ldr r3, [r3, #0]
|
|
8003d9a: f003 0302 and.w r3, r3, #2
|
|
8003d9e: 2b00 cmp r3, #0
|
|
8003da0: d1f0 bne.n 8003d84 <HAL_RCC_OscConfig+0x1f4>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8003da2: 687b ldr r3, [r7, #4]
|
|
8003da4: 681b ldr r3, [r3, #0]
|
|
8003da6: f003 0308 and.w r3, r3, #8
|
|
8003daa: 2b00 cmp r3, #0
|
|
8003dac: d036 beq.n 8003e1c <HAL_RCC_OscConfig+0x28c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
|
|
8003dae: 687b ldr r3, [r7, #4]
|
|
8003db0: 695b ldr r3, [r3, #20]
|
|
8003db2: 2b00 cmp r3, #0
|
|
8003db4: d016 beq.n 8003de4 <HAL_RCC_OscConfig+0x254>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8003db6: 4b15 ldr r3, [pc, #84] @ (8003e0c <HAL_RCC_OscConfig+0x27c>)
|
|
8003db8: 2201 movs r2, #1
|
|
8003dba: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003dbc: f7fd f9ba bl 8001134 <HAL_GetTick>
|
|
8003dc0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8003dc2: e008 b.n 8003dd6 <HAL_RCC_OscConfig+0x246>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8003dc4: f7fd f9b6 bl 8001134 <HAL_GetTick>
|
|
8003dc8: 4602 mov r2, r0
|
|
8003dca: 693b ldr r3, [r7, #16]
|
|
8003dcc: 1ad3 subs r3, r2, r3
|
|
8003dce: 2b02 cmp r3, #2
|
|
8003dd0: d901 bls.n 8003dd6 <HAL_RCC_OscConfig+0x246>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003dd2: 2303 movs r3, #3
|
|
8003dd4: e173 b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8003dd6: 4b0b ldr r3, [pc, #44] @ (8003e04 <HAL_RCC_OscConfig+0x274>)
|
|
8003dd8: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8003dda: f003 0302 and.w r3, r3, #2
|
|
8003dde: 2b00 cmp r3, #0
|
|
8003de0: d0f0 beq.n 8003dc4 <HAL_RCC_OscConfig+0x234>
|
|
8003de2: e01b b.n 8003e1c <HAL_RCC_OscConfig+0x28c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8003de4: 4b09 ldr r3, [pc, #36] @ (8003e0c <HAL_RCC_OscConfig+0x27c>)
|
|
8003de6: 2200 movs r2, #0
|
|
8003de8: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003dea: f7fd f9a3 bl 8001134 <HAL_GetTick>
|
|
8003dee: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8003df0: e00e b.n 8003e10 <HAL_RCC_OscConfig+0x280>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8003df2: f7fd f99f bl 8001134 <HAL_GetTick>
|
|
8003df6: 4602 mov r2, r0
|
|
8003df8: 693b ldr r3, [r7, #16]
|
|
8003dfa: 1ad3 subs r3, r2, r3
|
|
8003dfc: 2b02 cmp r3, #2
|
|
8003dfe: d907 bls.n 8003e10 <HAL_RCC_OscConfig+0x280>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003e00: 2303 movs r3, #3
|
|
8003e02: e15c b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
8003e04: 40023800 .word 0x40023800
|
|
8003e08: 42470000 .word 0x42470000
|
|
8003e0c: 42470e80 .word 0x42470e80
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8003e10: 4b8a ldr r3, [pc, #552] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003e12: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8003e14: f003 0302 and.w r3, r3, #2
|
|
8003e18: 2b00 cmp r3, #0
|
|
8003e1a: d1ea bne.n 8003df2 <HAL_RCC_OscConfig+0x262>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8003e1c: 687b ldr r3, [r7, #4]
|
|
8003e1e: 681b ldr r3, [r3, #0]
|
|
8003e20: f003 0304 and.w r3, r3, #4
|
|
8003e24: 2b00 cmp r3, #0
|
|
8003e26: f000 8097 beq.w 8003f58 <HAL_RCC_OscConfig+0x3c8>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8003e2a: 2300 movs r3, #0
|
|
8003e2c: 75fb strb r3, [r7, #23]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8003e2e: 4b83 ldr r3, [pc, #524] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003e30: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003e32: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003e36: 2b00 cmp r3, #0
|
|
8003e38: d10f bne.n 8003e5a <HAL_RCC_OscConfig+0x2ca>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8003e3a: 2300 movs r3, #0
|
|
8003e3c: 60bb str r3, [r7, #8]
|
|
8003e3e: 4b7f ldr r3, [pc, #508] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003e40: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003e42: 4a7e ldr r2, [pc, #504] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003e44: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8003e48: 6413 str r3, [r2, #64] @ 0x40
|
|
8003e4a: 4b7c ldr r3, [pc, #496] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003e4c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003e4e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003e52: 60bb str r3, [r7, #8]
|
|
8003e54: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8003e56: 2301 movs r3, #1
|
|
8003e58: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8003e5a: 4b79 ldr r3, [pc, #484] @ (8004040 <HAL_RCC_OscConfig+0x4b0>)
|
|
8003e5c: 681b ldr r3, [r3, #0]
|
|
8003e5e: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003e62: 2b00 cmp r3, #0
|
|
8003e64: d118 bne.n 8003e98 <HAL_RCC_OscConfig+0x308>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
8003e66: 4b76 ldr r3, [pc, #472] @ (8004040 <HAL_RCC_OscConfig+0x4b0>)
|
|
8003e68: 681b ldr r3, [r3, #0]
|
|
8003e6a: 4a75 ldr r2, [pc, #468] @ (8004040 <HAL_RCC_OscConfig+0x4b0>)
|
|
8003e6c: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8003e70: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8003e72: f7fd f95f bl 8001134 <HAL_GetTick>
|
|
8003e76: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8003e78: e008 b.n 8003e8c <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8003e7a: f7fd f95b bl 8001134 <HAL_GetTick>
|
|
8003e7e: 4602 mov r2, r0
|
|
8003e80: 693b ldr r3, [r7, #16]
|
|
8003e82: 1ad3 subs r3, r2, r3
|
|
8003e84: 2b02 cmp r3, #2
|
|
8003e86: d901 bls.n 8003e8c <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003e88: 2303 movs r3, #3
|
|
8003e8a: e118 b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8003e8c: 4b6c ldr r3, [pc, #432] @ (8004040 <HAL_RCC_OscConfig+0x4b0>)
|
|
8003e8e: 681b ldr r3, [r3, #0]
|
|
8003e90: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003e94: 2b00 cmp r3, #0
|
|
8003e96: d0f0 beq.n 8003e7a <HAL_RCC_OscConfig+0x2ea>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8003e98: 687b ldr r3, [r7, #4]
|
|
8003e9a: 689b ldr r3, [r3, #8]
|
|
8003e9c: 2b01 cmp r3, #1
|
|
8003e9e: d106 bne.n 8003eae <HAL_RCC_OscConfig+0x31e>
|
|
8003ea0: 4b66 ldr r3, [pc, #408] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003ea2: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003ea4: 4a65 ldr r2, [pc, #404] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003ea6: f043 0301 orr.w r3, r3, #1
|
|
8003eaa: 6713 str r3, [r2, #112] @ 0x70
|
|
8003eac: e01c b.n 8003ee8 <HAL_RCC_OscConfig+0x358>
|
|
8003eae: 687b ldr r3, [r7, #4]
|
|
8003eb0: 689b ldr r3, [r3, #8]
|
|
8003eb2: 2b05 cmp r3, #5
|
|
8003eb4: d10c bne.n 8003ed0 <HAL_RCC_OscConfig+0x340>
|
|
8003eb6: 4b61 ldr r3, [pc, #388] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003eb8: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003eba: 4a60 ldr r2, [pc, #384] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003ebc: f043 0304 orr.w r3, r3, #4
|
|
8003ec0: 6713 str r3, [r2, #112] @ 0x70
|
|
8003ec2: 4b5e ldr r3, [pc, #376] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003ec4: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003ec6: 4a5d ldr r2, [pc, #372] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003ec8: f043 0301 orr.w r3, r3, #1
|
|
8003ecc: 6713 str r3, [r2, #112] @ 0x70
|
|
8003ece: e00b b.n 8003ee8 <HAL_RCC_OscConfig+0x358>
|
|
8003ed0: 4b5a ldr r3, [pc, #360] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003ed2: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003ed4: 4a59 ldr r2, [pc, #356] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003ed6: f023 0301 bic.w r3, r3, #1
|
|
8003eda: 6713 str r3, [r2, #112] @ 0x70
|
|
8003edc: 4b57 ldr r3, [pc, #348] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003ede: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003ee0: 4a56 ldr r2, [pc, #344] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003ee2: f023 0304 bic.w r3, r3, #4
|
|
8003ee6: 6713 str r3, [r2, #112] @ 0x70
|
|
/* Check the LSE State */
|
|
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
|
|
8003ee8: 687b ldr r3, [r7, #4]
|
|
8003eea: 689b ldr r3, [r3, #8]
|
|
8003eec: 2b00 cmp r3, #0
|
|
8003eee: d015 beq.n 8003f1c <HAL_RCC_OscConfig+0x38c>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003ef0: f7fd f920 bl 8001134 <HAL_GetTick>
|
|
8003ef4: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8003ef6: e00a b.n 8003f0e <HAL_RCC_OscConfig+0x37e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003ef8: f7fd f91c bl 8001134 <HAL_GetTick>
|
|
8003efc: 4602 mov r2, r0
|
|
8003efe: 693b ldr r3, [r7, #16]
|
|
8003f00: 1ad3 subs r3, r2, r3
|
|
8003f02: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003f06: 4293 cmp r3, r2
|
|
8003f08: d901 bls.n 8003f0e <HAL_RCC_OscConfig+0x37e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003f0a: 2303 movs r3, #3
|
|
8003f0c: e0d7 b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8003f0e: 4b4b ldr r3, [pc, #300] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003f10: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003f12: f003 0302 and.w r3, r3, #2
|
|
8003f16: 2b00 cmp r3, #0
|
|
8003f18: d0ee beq.n 8003ef8 <HAL_RCC_OscConfig+0x368>
|
|
8003f1a: e014 b.n 8003f46 <HAL_RCC_OscConfig+0x3b6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003f1c: f7fd f90a bl 8001134 <HAL_GetTick>
|
|
8003f20: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8003f22: e00a b.n 8003f3a <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003f24: f7fd f906 bl 8001134 <HAL_GetTick>
|
|
8003f28: 4602 mov r2, r0
|
|
8003f2a: 693b ldr r3, [r7, #16]
|
|
8003f2c: 1ad3 subs r3, r2, r3
|
|
8003f2e: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003f32: 4293 cmp r3, r2
|
|
8003f34: d901 bls.n 8003f3a <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003f36: 2303 movs r3, #3
|
|
8003f38: e0c1 b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8003f3a: 4b40 ldr r3, [pc, #256] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003f3c: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8003f3e: f003 0302 and.w r3, r3, #2
|
|
8003f42: 2b00 cmp r3, #0
|
|
8003f44: d1ee bne.n 8003f24 <HAL_RCC_OscConfig+0x394>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
8003f46: 7dfb ldrb r3, [r7, #23]
|
|
8003f48: 2b01 cmp r3, #1
|
|
8003f4a: d105 bne.n 8003f58 <HAL_RCC_OscConfig+0x3c8>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8003f4c: 4b3b ldr r3, [pc, #236] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003f4e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003f50: 4a3a ldr r2, [pc, #232] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003f52: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8003f56: 6413 str r3, [r2, #64] @ 0x40
|
|
}
|
|
}
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8003f58: 687b ldr r3, [r7, #4]
|
|
8003f5a: 699b ldr r3, [r3, #24]
|
|
8003f5c: 2b00 cmp r3, #0
|
|
8003f5e: f000 80ad beq.w 80040bc <HAL_RCC_OscConfig+0x52c>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
|
8003f62: 4b36 ldr r3, [pc, #216] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003f64: 689b ldr r3, [r3, #8]
|
|
8003f66: f003 030c and.w r3, r3, #12
|
|
8003f6a: 2b08 cmp r3, #8
|
|
8003f6c: d060 beq.n 8004030 <HAL_RCC_OscConfig+0x4a0>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
8003f6e: 687b ldr r3, [r7, #4]
|
|
8003f70: 699b ldr r3, [r3, #24]
|
|
8003f72: 2b02 cmp r3, #2
|
|
8003f74: d145 bne.n 8004002 <HAL_RCC_OscConfig+0x472>
|
|
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8003f76: 4b33 ldr r3, [pc, #204] @ (8004044 <HAL_RCC_OscConfig+0x4b4>)
|
|
8003f78: 2200 movs r2, #0
|
|
8003f7a: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003f7c: f7fd f8da bl 8001134 <HAL_GetTick>
|
|
8003f80: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8003f82: e008 b.n 8003f96 <HAL_RCC_OscConfig+0x406>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003f84: f7fd f8d6 bl 8001134 <HAL_GetTick>
|
|
8003f88: 4602 mov r2, r0
|
|
8003f8a: 693b ldr r3, [r7, #16]
|
|
8003f8c: 1ad3 subs r3, r2, r3
|
|
8003f8e: 2b02 cmp r3, #2
|
|
8003f90: d901 bls.n 8003f96 <HAL_RCC_OscConfig+0x406>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003f92: 2303 movs r3, #3
|
|
8003f94: e093 b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8003f96: 4b29 ldr r3, [pc, #164] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003f98: 681b ldr r3, [r3, #0]
|
|
8003f9a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003f9e: 2b00 cmp r3, #0
|
|
8003fa0: d1f0 bne.n 8003f84 <HAL_RCC_OscConfig+0x3f4>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
|
|
8003fa2: 687b ldr r3, [r7, #4]
|
|
8003fa4: 69da ldr r2, [r3, #28]
|
|
8003fa6: 687b ldr r3, [r7, #4]
|
|
8003fa8: 6a1b ldr r3, [r3, #32]
|
|
8003faa: 431a orrs r2, r3
|
|
8003fac: 687b ldr r3, [r7, #4]
|
|
8003fae: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003fb0: 019b lsls r3, r3, #6
|
|
8003fb2: 431a orrs r2, r3
|
|
8003fb4: 687b ldr r3, [r7, #4]
|
|
8003fb6: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003fb8: 085b lsrs r3, r3, #1
|
|
8003fba: 3b01 subs r3, #1
|
|
8003fbc: 041b lsls r3, r3, #16
|
|
8003fbe: 431a orrs r2, r3
|
|
8003fc0: 687b ldr r3, [r7, #4]
|
|
8003fc2: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8003fc4: 061b lsls r3, r3, #24
|
|
8003fc6: 431a orrs r2, r3
|
|
8003fc8: 687b ldr r3, [r7, #4]
|
|
8003fca: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8003fcc: 071b lsls r3, r3, #28
|
|
8003fce: 491b ldr r1, [pc, #108] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003fd0: 4313 orrs r3, r2
|
|
8003fd2: 604b str r3, [r1, #4]
|
|
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
|
|
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8003fd4: 4b1b ldr r3, [pc, #108] @ (8004044 <HAL_RCC_OscConfig+0x4b4>)
|
|
8003fd6: 2201 movs r2, #1
|
|
8003fd8: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003fda: f7fd f8ab bl 8001134 <HAL_GetTick>
|
|
8003fde: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8003fe0: e008 b.n 8003ff4 <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003fe2: f7fd f8a7 bl 8001134 <HAL_GetTick>
|
|
8003fe6: 4602 mov r2, r0
|
|
8003fe8: 693b ldr r3, [r7, #16]
|
|
8003fea: 1ad3 subs r3, r2, r3
|
|
8003fec: 2b02 cmp r3, #2
|
|
8003fee: d901 bls.n 8003ff4 <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003ff0: 2303 movs r3, #3
|
|
8003ff2: e064 b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8003ff4: 4b11 ldr r3, [pc, #68] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8003ff6: 681b ldr r3, [r3, #0]
|
|
8003ff8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003ffc: 2b00 cmp r3, #0
|
|
8003ffe: d0f0 beq.n 8003fe2 <HAL_RCC_OscConfig+0x452>
|
|
8004000: e05c b.n 80040bc <HAL_RCC_OscConfig+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8004002: 4b10 ldr r3, [pc, #64] @ (8004044 <HAL_RCC_OscConfig+0x4b4>)
|
|
8004004: 2200 movs r2, #0
|
|
8004006: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004008: f7fd f894 bl 8001134 <HAL_GetTick>
|
|
800400c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
800400e: e008 b.n 8004022 <HAL_RCC_OscConfig+0x492>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8004010: f7fd f890 bl 8001134 <HAL_GetTick>
|
|
8004014: 4602 mov r2, r0
|
|
8004016: 693b ldr r3, [r7, #16]
|
|
8004018: 1ad3 subs r3, r2, r3
|
|
800401a: 2b02 cmp r3, #2
|
|
800401c: d901 bls.n 8004022 <HAL_RCC_OscConfig+0x492>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800401e: 2303 movs r3, #3
|
|
8004020: e04d b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8004022: 4b06 ldr r3, [pc, #24] @ (800403c <HAL_RCC_OscConfig+0x4ac>)
|
|
8004024: 681b ldr r3, [r3, #0]
|
|
8004026: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800402a: 2b00 cmp r3, #0
|
|
800402c: d1f0 bne.n 8004010 <HAL_RCC_OscConfig+0x480>
|
|
800402e: e045 b.n 80040bc <HAL_RCC_OscConfig+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8004030: 687b ldr r3, [r7, #4]
|
|
8004032: 699b ldr r3, [r3, #24]
|
|
8004034: 2b01 cmp r3, #1
|
|
8004036: d107 bne.n 8004048 <HAL_RCC_OscConfig+0x4b8>
|
|
{
|
|
return HAL_ERROR;
|
|
8004038: 2301 movs r3, #1
|
|
800403a: e040 b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
800403c: 40023800 .word 0x40023800
|
|
8004040: 40007000 .word 0x40007000
|
|
8004044: 42470060 .word 0x42470060
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->PLLCFGR;
|
|
8004048: 4b1f ldr r3, [pc, #124] @ (80040c8 <HAL_RCC_OscConfig+0x538>)
|
|
800404a: 685b ldr r3, [r3, #4]
|
|
800404c: 60fb str r3, [r7, #12]
|
|
#if defined (RCC_PLLCFGR_PLLR)
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
800404e: 687b ldr r3, [r7, #4]
|
|
8004050: 699b ldr r3, [r3, #24]
|
|
8004052: 2b01 cmp r3, #1
|
|
8004054: d030 beq.n 80040b8 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8004056: 68fb ldr r3, [r7, #12]
|
|
8004058: f403 0280 and.w r2, r3, #4194304 @ 0x400000
|
|
800405c: 687b ldr r3, [r7, #4]
|
|
800405e: 69db ldr r3, [r3, #28]
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
8004060: 429a cmp r2, r3
|
|
8004062: d129 bne.n 80040b8 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
8004064: 68fb ldr r3, [r7, #12]
|
|
8004066: f003 023f and.w r2, r3, #63 @ 0x3f
|
|
800406a: 687b ldr r3, [r7, #4]
|
|
800406c: 6a1b ldr r3, [r3, #32]
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800406e: 429a cmp r2, r3
|
|
8004070: d122 bne.n 80040b8 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
8004072: 68fa ldr r2, [r7, #12]
|
|
8004074: f647 73c0 movw r3, #32704 @ 0x7fc0
|
|
8004078: 4013 ands r3, r2
|
|
800407a: 687a ldr r2, [r7, #4]
|
|
800407c: 6a52 ldr r2, [r2, #36] @ 0x24
|
|
800407e: 0192 lsls r2, r2, #6
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
8004080: 4293 cmp r3, r2
|
|
8004082: d119 bne.n 80040b8 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
8004084: 68fb ldr r3, [r7, #12]
|
|
8004086: f403 3240 and.w r2, r3, #196608 @ 0x30000
|
|
800408a: 687b ldr r3, [r7, #4]
|
|
800408c: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800408e: 085b lsrs r3, r3, #1
|
|
8004090: 3b01 subs r3, #1
|
|
8004092: 041b lsls r3, r3, #16
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
8004094: 429a cmp r2, r3
|
|
8004096: d10f bne.n 80040b8 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
8004098: 68fb ldr r3, [r7, #12]
|
|
800409a: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
|
|
800409e: 687b ldr r3, [r7, #4]
|
|
80040a0: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80040a2: 061b lsls r3, r3, #24
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
80040a4: 429a cmp r2, r3
|
|
80040a6: d107 bne.n 80040b8 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
|
|
80040a8: 68fb ldr r3, [r7, #12]
|
|
80040aa: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000
|
|
80040ae: 687b ldr r3, [r7, #4]
|
|
80040b0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80040b2: 071b lsls r3, r3, #28
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
80040b4: 429a cmp r2, r3
|
|
80040b6: d001 beq.n 80040bc <HAL_RCC_OscConfig+0x52c>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
|
|
#endif /* RCC_PLLCFGR_PLLR */
|
|
{
|
|
return HAL_ERROR;
|
|
80040b8: 2301 movs r3, #1
|
|
80040ba: e000 b.n 80040be <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80040bc: 2300 movs r3, #0
|
|
}
|
|
80040be: 4618 mov r0, r3
|
|
80040c0: 3718 adds r7, #24
|
|
80040c2: 46bd mov sp, r7
|
|
80040c4: bd80 pop {r7, pc}
|
|
80040c6: bf00 nop
|
|
80040c8: 40023800 .word 0x40023800
|
|
|
|
080040cc <HAL_TIM_OC_Init>:
|
|
* Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
|
|
* @param htim TIM Output Compare handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
80040cc: b580 push {r7, lr}
|
|
80040ce: b082 sub sp, #8
|
|
80040d0: af00 add r7, sp, #0
|
|
80040d2: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
80040d4: 687b ldr r3, [r7, #4]
|
|
80040d6: 2b00 cmp r3, #0
|
|
80040d8: d101 bne.n 80040de <HAL_TIM_OC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80040da: 2301 movs r3, #1
|
|
80040dc: e041 b.n 8004162 <HAL_TIM_OC_Init+0x96>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
80040de: 687b ldr r3, [r7, #4]
|
|
80040e0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
80040e4: b2db uxtb r3, r3
|
|
80040e6: 2b00 cmp r3, #0
|
|
80040e8: d106 bne.n 80040f8 <HAL_TIM_OC_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
80040ea: 687b ldr r3, [r7, #4]
|
|
80040ec: 2200 movs r2, #0
|
|
80040ee: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->OC_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_OC_MspInit(htim);
|
|
80040f2: 6878 ldr r0, [r7, #4]
|
|
80040f4: f7fc fd66 bl 8000bc4 <HAL_TIM_OC_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80040f8: 687b ldr r3, [r7, #4]
|
|
80040fa: 2202 movs r2, #2
|
|
80040fc: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Init the base time for the Output Compare */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8004100: 687b ldr r3, [r7, #4]
|
|
8004102: 681a ldr r2, [r3, #0]
|
|
8004104: 687b ldr r3, [r7, #4]
|
|
8004106: 3304 adds r3, #4
|
|
8004108: 4619 mov r1, r3
|
|
800410a: 4610 mov r0, r2
|
|
800410c: f000 f930 bl 8004370 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8004110: 687b ldr r3, [r7, #4]
|
|
8004112: 2201 movs r2, #1
|
|
8004114: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8004118: 687b ldr r3, [r7, #4]
|
|
800411a: 2201 movs r2, #1
|
|
800411c: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
8004120: 687b ldr r3, [r7, #4]
|
|
8004122: 2201 movs r2, #1
|
|
8004124: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
8004128: 687b ldr r3, [r7, #4]
|
|
800412a: 2201 movs r2, #1
|
|
800412c: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
8004130: 687b ldr r3, [r7, #4]
|
|
8004132: 2201 movs r2, #1
|
|
8004134: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8004138: 687b ldr r3, [r7, #4]
|
|
800413a: 2201 movs r2, #1
|
|
800413c: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
8004140: 687b ldr r3, [r7, #4]
|
|
8004142: 2201 movs r2, #1
|
|
8004144: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
8004148: 687b ldr r3, [r7, #4]
|
|
800414a: 2201 movs r2, #1
|
|
800414c: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
8004150: 687b ldr r3, [r7, #4]
|
|
8004152: 2201 movs r2, #1
|
|
8004154: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8004158: 687b ldr r3, [r7, #4]
|
|
800415a: 2201 movs r2, #1
|
|
800415c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
8004160: 2300 movs r3, #0
|
|
}
|
|
8004162: 4618 mov r0, r3
|
|
8004164: 3708 adds r7, #8
|
|
8004166: 46bd mov sp, r7
|
|
8004168: bd80 pop {r7, pc}
|
|
|
|
0800416a <HAL_TIM_Encoder_Init>:
|
|
* @param htim TIM Encoder Interface handle
|
|
* @param sConfig TIM Encoder Interface configuration structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
|
|
{
|
|
800416a: b580 push {r7, lr}
|
|
800416c: b086 sub sp, #24
|
|
800416e: af00 add r7, sp, #0
|
|
8004170: 6078 str r0, [r7, #4]
|
|
8004172: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
8004174: 687b ldr r3, [r7, #4]
|
|
8004176: 2b00 cmp r3, #0
|
|
8004178: d101 bne.n 800417e <HAL_TIM_Encoder_Init+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
800417a: 2301 movs r3, #1
|
|
800417c: e097 b.n 80042ae <HAL_TIM_Encoder_Init+0x144>
|
|
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
|
|
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
|
|
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
800417e: 687b ldr r3, [r7, #4]
|
|
8004180: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8004184: b2db uxtb r3, r3
|
|
8004186: 2b00 cmp r3, #0
|
|
8004188: d106 bne.n 8004198 <HAL_TIM_Encoder_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
800418a: 687b ldr r3, [r7, #4]
|
|
800418c: 2200 movs r2, #0
|
|
800418e: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Encoder_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_Encoder_MspInit(htim);
|
|
8004192: 6878 ldr r0, [r7, #4]
|
|
8004194: f7fc fd36 bl 8000c04 <HAL_TIM_Encoder_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8004198: 687b ldr r3, [r7, #4]
|
|
800419a: 2202 movs r2, #2
|
|
800419c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Reset the SMS and ECE bits */
|
|
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
|
|
80041a0: 687b ldr r3, [r7, #4]
|
|
80041a2: 681b ldr r3, [r3, #0]
|
|
80041a4: 689b ldr r3, [r3, #8]
|
|
80041a6: 687a ldr r2, [r7, #4]
|
|
80041a8: 6812 ldr r2, [r2, #0]
|
|
80041aa: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
80041ae: f023 0307 bic.w r3, r3, #7
|
|
80041b2: 6093 str r3, [r2, #8]
|
|
|
|
/* Configure the Time base in the Encoder Mode */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
80041b4: 687b ldr r3, [r7, #4]
|
|
80041b6: 681a ldr r2, [r3, #0]
|
|
80041b8: 687b ldr r3, [r7, #4]
|
|
80041ba: 3304 adds r3, #4
|
|
80041bc: 4619 mov r1, r3
|
|
80041be: 4610 mov r0, r2
|
|
80041c0: f000 f8d6 bl 8004370 <TIM_Base_SetConfig>
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80041c4: 687b ldr r3, [r7, #4]
|
|
80041c6: 681b ldr r3, [r3, #0]
|
|
80041c8: 689b ldr r3, [r3, #8]
|
|
80041ca: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmr1 = htim->Instance->CCMR1;
|
|
80041cc: 687b ldr r3, [r7, #4]
|
|
80041ce: 681b ldr r3, [r3, #0]
|
|
80041d0: 699b ldr r3, [r3, #24]
|
|
80041d2: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = htim->Instance->CCER;
|
|
80041d4: 687b ldr r3, [r7, #4]
|
|
80041d6: 681b ldr r3, [r3, #0]
|
|
80041d8: 6a1b ldr r3, [r3, #32]
|
|
80041da: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the encoder Mode */
|
|
tmpsmcr |= sConfig->EncoderMode;
|
|
80041dc: 683b ldr r3, [r7, #0]
|
|
80041de: 681b ldr r3, [r3, #0]
|
|
80041e0: 697a ldr r2, [r7, #20]
|
|
80041e2: 4313 orrs r3, r2
|
|
80041e4: 617b str r3, [r7, #20]
|
|
|
|
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
|
|
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
|
|
80041e6: 693b ldr r3, [r7, #16]
|
|
80041e8: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80041ec: f023 0303 bic.w r3, r3, #3
|
|
80041f0: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
|
|
80041f2: 683b ldr r3, [r7, #0]
|
|
80041f4: 689a ldr r2, [r3, #8]
|
|
80041f6: 683b ldr r3, [r7, #0]
|
|
80041f8: 699b ldr r3, [r3, #24]
|
|
80041fa: 021b lsls r3, r3, #8
|
|
80041fc: 4313 orrs r3, r2
|
|
80041fe: 693a ldr r2, [r7, #16]
|
|
8004200: 4313 orrs r3, r2
|
|
8004202: 613b str r3, [r7, #16]
|
|
|
|
/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
|
|
8004204: 693b ldr r3, [r7, #16]
|
|
8004206: f423 6340 bic.w r3, r3, #3072 @ 0xc00
|
|
800420a: f023 030c bic.w r3, r3, #12
|
|
800420e: 613b str r3, [r7, #16]
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
|
|
8004210: 693b ldr r3, [r7, #16]
|
|
8004212: f423 4370 bic.w r3, r3, #61440 @ 0xf000
|
|
8004216: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
800421a: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
|
|
800421c: 683b ldr r3, [r7, #0]
|
|
800421e: 68da ldr r2, [r3, #12]
|
|
8004220: 683b ldr r3, [r7, #0]
|
|
8004222: 69db ldr r3, [r3, #28]
|
|
8004224: 021b lsls r3, r3, #8
|
|
8004226: 4313 orrs r3, r2
|
|
8004228: 693a ldr r2, [r7, #16]
|
|
800422a: 4313 orrs r3, r2
|
|
800422c: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
|
|
800422e: 683b ldr r3, [r7, #0]
|
|
8004230: 691b ldr r3, [r3, #16]
|
|
8004232: 011a lsls r2, r3, #4
|
|
8004234: 683b ldr r3, [r7, #0]
|
|
8004236: 6a1b ldr r3, [r3, #32]
|
|
8004238: 031b lsls r3, r3, #12
|
|
800423a: 4313 orrs r3, r2
|
|
800423c: 693a ldr r2, [r7, #16]
|
|
800423e: 4313 orrs r3, r2
|
|
8004240: 613b str r3, [r7, #16]
|
|
|
|
/* Set the TI1 and the TI2 Polarities */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
|
|
8004242: 68fb ldr r3, [r7, #12]
|
|
8004244: f023 0322 bic.w r3, r3, #34 @ 0x22
|
|
8004248: 60fb str r3, [r7, #12]
|
|
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
|
|
800424a: 68fb ldr r3, [r7, #12]
|
|
800424c: f023 0388 bic.w r3, r3, #136 @ 0x88
|
|
8004250: 60fb str r3, [r7, #12]
|
|
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
|
|
8004252: 683b ldr r3, [r7, #0]
|
|
8004254: 685a ldr r2, [r3, #4]
|
|
8004256: 683b ldr r3, [r7, #0]
|
|
8004258: 695b ldr r3, [r3, #20]
|
|
800425a: 011b lsls r3, r3, #4
|
|
800425c: 4313 orrs r3, r2
|
|
800425e: 68fa ldr r2, [r7, #12]
|
|
8004260: 4313 orrs r3, r2
|
|
8004262: 60fb str r3, [r7, #12]
|
|
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8004264: 687b ldr r3, [r7, #4]
|
|
8004266: 681b ldr r3, [r3, #0]
|
|
8004268: 697a ldr r2, [r7, #20]
|
|
800426a: 609a str r2, [r3, #8]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
htim->Instance->CCMR1 = tmpccmr1;
|
|
800426c: 687b ldr r3, [r7, #4]
|
|
800426e: 681b ldr r3, [r3, #0]
|
|
8004270: 693a ldr r2, [r7, #16]
|
|
8004272: 619a str r2, [r3, #24]
|
|
|
|
/* Write to TIMx CCER */
|
|
htim->Instance->CCER = tmpccer;
|
|
8004274: 687b ldr r3, [r7, #4]
|
|
8004276: 681b ldr r3, [r3, #0]
|
|
8004278: 68fa ldr r2, [r7, #12]
|
|
800427a: 621a str r2, [r3, #32]
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
800427c: 687b ldr r3, [r7, #4]
|
|
800427e: 2201 movs r2, #1
|
|
8004280: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Set the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
8004284: 687b ldr r3, [r7, #4]
|
|
8004286: 2201 movs r2, #1
|
|
8004288: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
800428c: 687b ldr r3, [r7, #4]
|
|
800428e: 2201 movs r2, #1
|
|
8004290: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
8004294: 687b ldr r3, [r7, #4]
|
|
8004296: 2201 movs r2, #1
|
|
8004298: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
800429c: 687b ldr r3, [r7, #4]
|
|
800429e: 2201 movs r2, #1
|
|
80042a0: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80042a4: 687b ldr r3, [r7, #4]
|
|
80042a6: 2201 movs r2, #1
|
|
80042a8: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
80042ac: 2300 movs r3, #0
|
|
}
|
|
80042ae: 4618 mov r0, r3
|
|
80042b0: 3718 adds r7, #24
|
|
80042b2: 46bd mov sp, r7
|
|
80042b4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080042b8 <HAL_TIM_OC_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
const TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
80042b8: b580 push {r7, lr}
|
|
80042ba: b086 sub sp, #24
|
|
80042bc: af00 add r7, sp, #0
|
|
80042be: 60f8 str r0, [r7, #12]
|
|
80042c0: 60b9 str r1, [r7, #8]
|
|
80042c2: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80042c4: 2300 movs r3, #0
|
|
80042c6: 75fb strb r3, [r7, #23]
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
80042c8: 68fb ldr r3, [r7, #12]
|
|
80042ca: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
80042ce: 2b01 cmp r3, #1
|
|
80042d0: d101 bne.n 80042d6 <HAL_TIM_OC_ConfigChannel+0x1e>
|
|
80042d2: 2302 movs r3, #2
|
|
80042d4: e048 b.n 8004368 <HAL_TIM_OC_ConfigChannel+0xb0>
|
|
80042d6: 68fb ldr r3, [r7, #12]
|
|
80042d8: 2201 movs r2, #1
|
|
80042da: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
switch (Channel)
|
|
80042de: 687b ldr r3, [r7, #4]
|
|
80042e0: 2b0c cmp r3, #12
|
|
80042e2: d839 bhi.n 8004358 <HAL_TIM_OC_ConfigChannel+0xa0>
|
|
80042e4: a201 add r2, pc, #4 @ (adr r2, 80042ec <HAL_TIM_OC_ConfigChannel+0x34>)
|
|
80042e6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80042ea: bf00 nop
|
|
80042ec: 08004321 .word 0x08004321
|
|
80042f0: 08004359 .word 0x08004359
|
|
80042f4: 08004359 .word 0x08004359
|
|
80042f8: 08004359 .word 0x08004359
|
|
80042fc: 0800432f .word 0x0800432f
|
|
8004300: 08004359 .word 0x08004359
|
|
8004304: 08004359 .word 0x08004359
|
|
8004308: 08004359 .word 0x08004359
|
|
800430c: 0800433d .word 0x0800433d
|
|
8004310: 08004359 .word 0x08004359
|
|
8004314: 08004359 .word 0x08004359
|
|
8004318: 08004359 .word 0x08004359
|
|
800431c: 0800434b .word 0x0800434b
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 1 in Output Compare */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
8004320: 68fb ldr r3, [r7, #12]
|
|
8004322: 681b ldr r3, [r3, #0]
|
|
8004324: 68b9 ldr r1, [r7, #8]
|
|
8004326: 4618 mov r0, r3
|
|
8004328: f000 f8c8 bl 80044bc <TIM_OC1_SetConfig>
|
|
break;
|
|
800432c: e017 b.n 800435e <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 2 in Output Compare */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
800432e: 68fb ldr r3, [r7, #12]
|
|
8004330: 681b ldr r3, [r3, #0]
|
|
8004332: 68b9 ldr r1, [r7, #8]
|
|
8004334: 4618 mov r0, r3
|
|
8004336: f000 f931 bl 800459c <TIM_OC2_SetConfig>
|
|
break;
|
|
800433a: e010 b.n 800435e <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 3 in Output Compare */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
800433c: 68fb ldr r3, [r7, #12]
|
|
800433e: 681b ldr r3, [r3, #0]
|
|
8004340: 68b9 ldr r1, [r7, #8]
|
|
8004342: 4618 mov r0, r3
|
|
8004344: f000 f9a0 bl 8004688 <TIM_OC3_SetConfig>
|
|
break;
|
|
8004348: e009 b.n 800435e <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 4 in Output Compare */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
800434a: 68fb ldr r3, [r7, #12]
|
|
800434c: 681b ldr r3, [r3, #0]
|
|
800434e: 68b9 ldr r1, [r7, #8]
|
|
8004350: 4618 mov r0, r3
|
|
8004352: f000 fa0d bl 8004770 <TIM_OC4_SetConfig>
|
|
break;
|
|
8004356: e002 b.n 800435e <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
8004358: 2301 movs r3, #1
|
|
800435a: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800435c: bf00 nop
|
|
}
|
|
|
|
__HAL_UNLOCK(htim);
|
|
800435e: 68fb ldr r3, [r7, #12]
|
|
8004360: 2200 movs r2, #0
|
|
8004362: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
8004366: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8004368: 4618 mov r0, r3
|
|
800436a: 3718 adds r7, #24
|
|
800436c: 46bd mov sp, r7
|
|
800436e: bd80 pop {r7, pc}
|
|
|
|
08004370 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8004370: b480 push {r7}
|
|
8004372: b085 sub sp, #20
|
|
8004374: af00 add r7, sp, #0
|
|
8004376: 6078 str r0, [r7, #4]
|
|
8004378: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
800437a: 687b ldr r3, [r7, #4]
|
|
800437c: 681b ldr r3, [r3, #0]
|
|
800437e: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8004380: 687b ldr r3, [r7, #4]
|
|
8004382: 4a43 ldr r2, [pc, #268] @ (8004490 <TIM_Base_SetConfig+0x120>)
|
|
8004384: 4293 cmp r3, r2
|
|
8004386: d013 beq.n 80043b0 <TIM_Base_SetConfig+0x40>
|
|
8004388: 687b ldr r3, [r7, #4]
|
|
800438a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
800438e: d00f beq.n 80043b0 <TIM_Base_SetConfig+0x40>
|
|
8004390: 687b ldr r3, [r7, #4]
|
|
8004392: 4a40 ldr r2, [pc, #256] @ (8004494 <TIM_Base_SetConfig+0x124>)
|
|
8004394: 4293 cmp r3, r2
|
|
8004396: d00b beq.n 80043b0 <TIM_Base_SetConfig+0x40>
|
|
8004398: 687b ldr r3, [r7, #4]
|
|
800439a: 4a3f ldr r2, [pc, #252] @ (8004498 <TIM_Base_SetConfig+0x128>)
|
|
800439c: 4293 cmp r3, r2
|
|
800439e: d007 beq.n 80043b0 <TIM_Base_SetConfig+0x40>
|
|
80043a0: 687b ldr r3, [r7, #4]
|
|
80043a2: 4a3e ldr r2, [pc, #248] @ (800449c <TIM_Base_SetConfig+0x12c>)
|
|
80043a4: 4293 cmp r3, r2
|
|
80043a6: d003 beq.n 80043b0 <TIM_Base_SetConfig+0x40>
|
|
80043a8: 687b ldr r3, [r7, #4]
|
|
80043aa: 4a3d ldr r2, [pc, #244] @ (80044a0 <TIM_Base_SetConfig+0x130>)
|
|
80043ac: 4293 cmp r3, r2
|
|
80043ae: d108 bne.n 80043c2 <TIM_Base_SetConfig+0x52>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
80043b0: 68fb ldr r3, [r7, #12]
|
|
80043b2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80043b6: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
80043b8: 683b ldr r3, [r7, #0]
|
|
80043ba: 685b ldr r3, [r3, #4]
|
|
80043bc: 68fa ldr r2, [r7, #12]
|
|
80043be: 4313 orrs r3, r2
|
|
80043c0: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80043c2: 687b ldr r3, [r7, #4]
|
|
80043c4: 4a32 ldr r2, [pc, #200] @ (8004490 <TIM_Base_SetConfig+0x120>)
|
|
80043c6: 4293 cmp r3, r2
|
|
80043c8: d02b beq.n 8004422 <TIM_Base_SetConfig+0xb2>
|
|
80043ca: 687b ldr r3, [r7, #4]
|
|
80043cc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80043d0: d027 beq.n 8004422 <TIM_Base_SetConfig+0xb2>
|
|
80043d2: 687b ldr r3, [r7, #4]
|
|
80043d4: 4a2f ldr r2, [pc, #188] @ (8004494 <TIM_Base_SetConfig+0x124>)
|
|
80043d6: 4293 cmp r3, r2
|
|
80043d8: d023 beq.n 8004422 <TIM_Base_SetConfig+0xb2>
|
|
80043da: 687b ldr r3, [r7, #4]
|
|
80043dc: 4a2e ldr r2, [pc, #184] @ (8004498 <TIM_Base_SetConfig+0x128>)
|
|
80043de: 4293 cmp r3, r2
|
|
80043e0: d01f beq.n 8004422 <TIM_Base_SetConfig+0xb2>
|
|
80043e2: 687b ldr r3, [r7, #4]
|
|
80043e4: 4a2d ldr r2, [pc, #180] @ (800449c <TIM_Base_SetConfig+0x12c>)
|
|
80043e6: 4293 cmp r3, r2
|
|
80043e8: d01b beq.n 8004422 <TIM_Base_SetConfig+0xb2>
|
|
80043ea: 687b ldr r3, [r7, #4]
|
|
80043ec: 4a2c ldr r2, [pc, #176] @ (80044a0 <TIM_Base_SetConfig+0x130>)
|
|
80043ee: 4293 cmp r3, r2
|
|
80043f0: d017 beq.n 8004422 <TIM_Base_SetConfig+0xb2>
|
|
80043f2: 687b ldr r3, [r7, #4]
|
|
80043f4: 4a2b ldr r2, [pc, #172] @ (80044a4 <TIM_Base_SetConfig+0x134>)
|
|
80043f6: 4293 cmp r3, r2
|
|
80043f8: d013 beq.n 8004422 <TIM_Base_SetConfig+0xb2>
|
|
80043fa: 687b ldr r3, [r7, #4]
|
|
80043fc: 4a2a ldr r2, [pc, #168] @ (80044a8 <TIM_Base_SetConfig+0x138>)
|
|
80043fe: 4293 cmp r3, r2
|
|
8004400: d00f beq.n 8004422 <TIM_Base_SetConfig+0xb2>
|
|
8004402: 687b ldr r3, [r7, #4]
|
|
8004404: 4a29 ldr r2, [pc, #164] @ (80044ac <TIM_Base_SetConfig+0x13c>)
|
|
8004406: 4293 cmp r3, r2
|
|
8004408: d00b beq.n 8004422 <TIM_Base_SetConfig+0xb2>
|
|
800440a: 687b ldr r3, [r7, #4]
|
|
800440c: 4a28 ldr r2, [pc, #160] @ (80044b0 <TIM_Base_SetConfig+0x140>)
|
|
800440e: 4293 cmp r3, r2
|
|
8004410: d007 beq.n 8004422 <TIM_Base_SetConfig+0xb2>
|
|
8004412: 687b ldr r3, [r7, #4]
|
|
8004414: 4a27 ldr r2, [pc, #156] @ (80044b4 <TIM_Base_SetConfig+0x144>)
|
|
8004416: 4293 cmp r3, r2
|
|
8004418: d003 beq.n 8004422 <TIM_Base_SetConfig+0xb2>
|
|
800441a: 687b ldr r3, [r7, #4]
|
|
800441c: 4a26 ldr r2, [pc, #152] @ (80044b8 <TIM_Base_SetConfig+0x148>)
|
|
800441e: 4293 cmp r3, r2
|
|
8004420: d108 bne.n 8004434 <TIM_Base_SetConfig+0xc4>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
8004422: 68fb ldr r3, [r7, #12]
|
|
8004424: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004428: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
800442a: 683b ldr r3, [r7, #0]
|
|
800442c: 68db ldr r3, [r3, #12]
|
|
800442e: 68fa ldr r2, [r7, #12]
|
|
8004430: 4313 orrs r3, r2
|
|
8004432: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
8004434: 68fb ldr r3, [r7, #12]
|
|
8004436: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
800443a: 683b ldr r3, [r7, #0]
|
|
800443c: 695b ldr r3, [r3, #20]
|
|
800443e: 4313 orrs r3, r2
|
|
8004440: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
8004442: 683b ldr r3, [r7, #0]
|
|
8004444: 689a ldr r2, [r3, #8]
|
|
8004446: 687b ldr r3, [r7, #4]
|
|
8004448: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
800444a: 683b ldr r3, [r7, #0]
|
|
800444c: 681a ldr r2, [r3, #0]
|
|
800444e: 687b ldr r3, [r7, #4]
|
|
8004450: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
8004452: 687b ldr r3, [r7, #4]
|
|
8004454: 4a0e ldr r2, [pc, #56] @ (8004490 <TIM_Base_SetConfig+0x120>)
|
|
8004456: 4293 cmp r3, r2
|
|
8004458: d003 beq.n 8004462 <TIM_Base_SetConfig+0xf2>
|
|
800445a: 687b ldr r3, [r7, #4]
|
|
800445c: 4a10 ldr r2, [pc, #64] @ (80044a0 <TIM_Base_SetConfig+0x130>)
|
|
800445e: 4293 cmp r3, r2
|
|
8004460: d103 bne.n 800446a <TIM_Base_SetConfig+0xfa>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
8004462: 683b ldr r3, [r7, #0]
|
|
8004464: 691a ldr r2, [r3, #16]
|
|
8004466: 687b ldr r3, [r7, #4]
|
|
8004468: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Disable Update Event (UEV) with Update Generation (UG)
|
|
by changing Update Request Source (URS) to avoid Update flag (UIF) */
|
|
SET_BIT(TIMx->CR1, TIM_CR1_URS);
|
|
800446a: 687b ldr r3, [r7, #4]
|
|
800446c: 681b ldr r3, [r3, #0]
|
|
800446e: f043 0204 orr.w r2, r3, #4
|
|
8004472: 687b ldr r3, [r7, #4]
|
|
8004474: 601a str r2, [r3, #0]
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
8004476: 687b ldr r3, [r7, #4]
|
|
8004478: 2201 movs r2, #1
|
|
800447a: 615a str r2, [r3, #20]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
800447c: 687b ldr r3, [r7, #4]
|
|
800447e: 68fa ldr r2, [r7, #12]
|
|
8004480: 601a str r2, [r3, #0]
|
|
}
|
|
8004482: bf00 nop
|
|
8004484: 3714 adds r7, #20
|
|
8004486: 46bd mov sp, r7
|
|
8004488: f85d 7b04 ldr.w r7, [sp], #4
|
|
800448c: 4770 bx lr
|
|
800448e: bf00 nop
|
|
8004490: 40010000 .word 0x40010000
|
|
8004494: 40000400 .word 0x40000400
|
|
8004498: 40000800 .word 0x40000800
|
|
800449c: 40000c00 .word 0x40000c00
|
|
80044a0: 40010400 .word 0x40010400
|
|
80044a4: 40014000 .word 0x40014000
|
|
80044a8: 40014400 .word 0x40014400
|
|
80044ac: 40014800 .word 0x40014800
|
|
80044b0: 40001800 .word 0x40001800
|
|
80044b4: 40001c00 .word 0x40001c00
|
|
80044b8: 40002000 .word 0x40002000
|
|
|
|
080044bc <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
80044bc: b480 push {r7}
|
|
80044be: b087 sub sp, #28
|
|
80044c0: af00 add r7, sp, #0
|
|
80044c2: 6078 str r0, [r7, #4]
|
|
80044c4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
80044c6: 687b ldr r3, [r7, #4]
|
|
80044c8: 6a1b ldr r3, [r3, #32]
|
|
80044ca: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
80044cc: 687b ldr r3, [r7, #4]
|
|
80044ce: 6a1b ldr r3, [r3, #32]
|
|
80044d0: f023 0201 bic.w r2, r3, #1
|
|
80044d4: 687b ldr r3, [r7, #4]
|
|
80044d6: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80044d8: 687b ldr r3, [r7, #4]
|
|
80044da: 685b ldr r3, [r3, #4]
|
|
80044dc: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
80044de: 687b ldr r3, [r7, #4]
|
|
80044e0: 699b ldr r3, [r3, #24]
|
|
80044e2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
80044e4: 68fb ldr r3, [r7, #12]
|
|
80044e6: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80044ea: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
80044ec: 68fb ldr r3, [r7, #12]
|
|
80044ee: f023 0303 bic.w r3, r3, #3
|
|
80044f2: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
80044f4: 683b ldr r3, [r7, #0]
|
|
80044f6: 681b ldr r3, [r3, #0]
|
|
80044f8: 68fa ldr r2, [r7, #12]
|
|
80044fa: 4313 orrs r3, r2
|
|
80044fc: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
80044fe: 697b ldr r3, [r7, #20]
|
|
8004500: f023 0302 bic.w r3, r3, #2
|
|
8004504: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
8004506: 683b ldr r3, [r7, #0]
|
|
8004508: 689b ldr r3, [r3, #8]
|
|
800450a: 697a ldr r2, [r7, #20]
|
|
800450c: 4313 orrs r3, r2
|
|
800450e: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
8004510: 687b ldr r3, [r7, #4]
|
|
8004512: 4a20 ldr r2, [pc, #128] @ (8004594 <TIM_OC1_SetConfig+0xd8>)
|
|
8004514: 4293 cmp r3, r2
|
|
8004516: d003 beq.n 8004520 <TIM_OC1_SetConfig+0x64>
|
|
8004518: 687b ldr r3, [r7, #4]
|
|
800451a: 4a1f ldr r2, [pc, #124] @ (8004598 <TIM_OC1_SetConfig+0xdc>)
|
|
800451c: 4293 cmp r3, r2
|
|
800451e: d10c bne.n 800453a <TIM_OC1_SetConfig+0x7e>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
8004520: 697b ldr r3, [r7, #20]
|
|
8004522: f023 0308 bic.w r3, r3, #8
|
|
8004526: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
8004528: 683b ldr r3, [r7, #0]
|
|
800452a: 68db ldr r3, [r3, #12]
|
|
800452c: 697a ldr r2, [r7, #20]
|
|
800452e: 4313 orrs r3, r2
|
|
8004530: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
8004532: 697b ldr r3, [r7, #20]
|
|
8004534: f023 0304 bic.w r3, r3, #4
|
|
8004538: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800453a: 687b ldr r3, [r7, #4]
|
|
800453c: 4a15 ldr r2, [pc, #84] @ (8004594 <TIM_OC1_SetConfig+0xd8>)
|
|
800453e: 4293 cmp r3, r2
|
|
8004540: d003 beq.n 800454a <TIM_OC1_SetConfig+0x8e>
|
|
8004542: 687b ldr r3, [r7, #4]
|
|
8004544: 4a14 ldr r2, [pc, #80] @ (8004598 <TIM_OC1_SetConfig+0xdc>)
|
|
8004546: 4293 cmp r3, r2
|
|
8004548: d111 bne.n 800456e <TIM_OC1_SetConfig+0xb2>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
800454a: 693b ldr r3, [r7, #16]
|
|
800454c: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8004550: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
8004552: 693b ldr r3, [r7, #16]
|
|
8004554: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
8004558: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
800455a: 683b ldr r3, [r7, #0]
|
|
800455c: 695b ldr r3, [r3, #20]
|
|
800455e: 693a ldr r2, [r7, #16]
|
|
8004560: 4313 orrs r3, r2
|
|
8004562: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
8004564: 683b ldr r3, [r7, #0]
|
|
8004566: 699b ldr r3, [r3, #24]
|
|
8004568: 693a ldr r2, [r7, #16]
|
|
800456a: 4313 orrs r3, r2
|
|
800456c: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800456e: 687b ldr r3, [r7, #4]
|
|
8004570: 693a ldr r2, [r7, #16]
|
|
8004572: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8004574: 687b ldr r3, [r7, #4]
|
|
8004576: 68fa ldr r2, [r7, #12]
|
|
8004578: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
800457a: 683b ldr r3, [r7, #0]
|
|
800457c: 685a ldr r2, [r3, #4]
|
|
800457e: 687b ldr r3, [r7, #4]
|
|
8004580: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004582: 687b ldr r3, [r7, #4]
|
|
8004584: 697a ldr r2, [r7, #20]
|
|
8004586: 621a str r2, [r3, #32]
|
|
}
|
|
8004588: bf00 nop
|
|
800458a: 371c adds r7, #28
|
|
800458c: 46bd mov sp, r7
|
|
800458e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004592: 4770 bx lr
|
|
8004594: 40010000 .word 0x40010000
|
|
8004598: 40010400 .word 0x40010400
|
|
|
|
0800459c <TIM_OC2_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800459c: b480 push {r7}
|
|
800459e: b087 sub sp, #28
|
|
80045a0: af00 add r7, sp, #0
|
|
80045a2: 6078 str r0, [r7, #4]
|
|
80045a4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
80045a6: 687b ldr r3, [r7, #4]
|
|
80045a8: 6a1b ldr r3, [r3, #32]
|
|
80045aa: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
80045ac: 687b ldr r3, [r7, #4]
|
|
80045ae: 6a1b ldr r3, [r3, #32]
|
|
80045b0: f023 0210 bic.w r2, r3, #16
|
|
80045b4: 687b ldr r3, [r7, #4]
|
|
80045b6: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80045b8: 687b ldr r3, [r7, #4]
|
|
80045ba: 685b ldr r3, [r3, #4]
|
|
80045bc: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
80045be: 687b ldr r3, [r7, #4]
|
|
80045c0: 699b ldr r3, [r3, #24]
|
|
80045c2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
80045c4: 68fb ldr r3, [r7, #12]
|
|
80045c6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80045ca: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
80045cc: 68fb ldr r3, [r7, #12]
|
|
80045ce: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80045d2: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
80045d4: 683b ldr r3, [r7, #0]
|
|
80045d6: 681b ldr r3, [r3, #0]
|
|
80045d8: 021b lsls r3, r3, #8
|
|
80045da: 68fa ldr r2, [r7, #12]
|
|
80045dc: 4313 orrs r3, r2
|
|
80045de: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
80045e0: 697b ldr r3, [r7, #20]
|
|
80045e2: f023 0320 bic.w r3, r3, #32
|
|
80045e6: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
80045e8: 683b ldr r3, [r7, #0]
|
|
80045ea: 689b ldr r3, [r3, #8]
|
|
80045ec: 011b lsls r3, r3, #4
|
|
80045ee: 697a ldr r2, [r7, #20]
|
|
80045f0: 4313 orrs r3, r2
|
|
80045f2: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
80045f4: 687b ldr r3, [r7, #4]
|
|
80045f6: 4a22 ldr r2, [pc, #136] @ (8004680 <TIM_OC2_SetConfig+0xe4>)
|
|
80045f8: 4293 cmp r3, r2
|
|
80045fa: d003 beq.n 8004604 <TIM_OC2_SetConfig+0x68>
|
|
80045fc: 687b ldr r3, [r7, #4]
|
|
80045fe: 4a21 ldr r2, [pc, #132] @ (8004684 <TIM_OC2_SetConfig+0xe8>)
|
|
8004600: 4293 cmp r3, r2
|
|
8004602: d10d bne.n 8004620 <TIM_OC2_SetConfig+0x84>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
8004604: 697b ldr r3, [r7, #20]
|
|
8004606: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
800460a: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
800460c: 683b ldr r3, [r7, #0]
|
|
800460e: 68db ldr r3, [r3, #12]
|
|
8004610: 011b lsls r3, r3, #4
|
|
8004612: 697a ldr r2, [r7, #20]
|
|
8004614: 4313 orrs r3, r2
|
|
8004616: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
8004618: 697b ldr r3, [r7, #20]
|
|
800461a: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800461e: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8004620: 687b ldr r3, [r7, #4]
|
|
8004622: 4a17 ldr r2, [pc, #92] @ (8004680 <TIM_OC2_SetConfig+0xe4>)
|
|
8004624: 4293 cmp r3, r2
|
|
8004626: d003 beq.n 8004630 <TIM_OC2_SetConfig+0x94>
|
|
8004628: 687b ldr r3, [r7, #4]
|
|
800462a: 4a16 ldr r2, [pc, #88] @ (8004684 <TIM_OC2_SetConfig+0xe8>)
|
|
800462c: 4293 cmp r3, r2
|
|
800462e: d113 bne.n 8004658 <TIM_OC2_SetConfig+0xbc>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
8004630: 693b ldr r3, [r7, #16]
|
|
8004632: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8004636: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
8004638: 693b ldr r3, [r7, #16]
|
|
800463a: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
800463e: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
8004640: 683b ldr r3, [r7, #0]
|
|
8004642: 695b ldr r3, [r3, #20]
|
|
8004644: 009b lsls r3, r3, #2
|
|
8004646: 693a ldr r2, [r7, #16]
|
|
8004648: 4313 orrs r3, r2
|
|
800464a: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
800464c: 683b ldr r3, [r7, #0]
|
|
800464e: 699b ldr r3, [r3, #24]
|
|
8004650: 009b lsls r3, r3, #2
|
|
8004652: 693a ldr r2, [r7, #16]
|
|
8004654: 4313 orrs r3, r2
|
|
8004656: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004658: 687b ldr r3, [r7, #4]
|
|
800465a: 693a ldr r2, [r7, #16]
|
|
800465c: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
800465e: 687b ldr r3, [r7, #4]
|
|
8004660: 68fa ldr r2, [r7, #12]
|
|
8004662: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
8004664: 683b ldr r3, [r7, #0]
|
|
8004666: 685a ldr r2, [r3, #4]
|
|
8004668: 687b ldr r3, [r7, #4]
|
|
800466a: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800466c: 687b ldr r3, [r7, #4]
|
|
800466e: 697a ldr r2, [r7, #20]
|
|
8004670: 621a str r2, [r3, #32]
|
|
}
|
|
8004672: bf00 nop
|
|
8004674: 371c adds r7, #28
|
|
8004676: 46bd mov sp, r7
|
|
8004678: f85d 7b04 ldr.w r7, [sp], #4
|
|
800467c: 4770 bx lr
|
|
800467e: bf00 nop
|
|
8004680: 40010000 .word 0x40010000
|
|
8004684: 40010400 .word 0x40010400
|
|
|
|
08004688 <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004688: b480 push {r7}
|
|
800468a: b087 sub sp, #28
|
|
800468c: af00 add r7, sp, #0
|
|
800468e: 6078 str r0, [r7, #4]
|
|
8004690: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8004692: 687b ldr r3, [r7, #4]
|
|
8004694: 6a1b ldr r3, [r3, #32]
|
|
8004696: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
8004698: 687b ldr r3, [r7, #4]
|
|
800469a: 6a1b ldr r3, [r3, #32]
|
|
800469c: f423 7280 bic.w r2, r3, #256 @ 0x100
|
|
80046a0: 687b ldr r3, [r7, #4]
|
|
80046a2: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80046a4: 687b ldr r3, [r7, #4]
|
|
80046a6: 685b ldr r3, [r3, #4]
|
|
80046a8: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
80046aa: 687b ldr r3, [r7, #4]
|
|
80046ac: 69db ldr r3, [r3, #28]
|
|
80046ae: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
80046b0: 68fb ldr r3, [r7, #12]
|
|
80046b2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80046b6: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
80046b8: 68fb ldr r3, [r7, #12]
|
|
80046ba: f023 0303 bic.w r3, r3, #3
|
|
80046be: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
80046c0: 683b ldr r3, [r7, #0]
|
|
80046c2: 681b ldr r3, [r3, #0]
|
|
80046c4: 68fa ldr r2, [r7, #12]
|
|
80046c6: 4313 orrs r3, r2
|
|
80046c8: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
80046ca: 697b ldr r3, [r7, #20]
|
|
80046cc: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
80046d0: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
80046d2: 683b ldr r3, [r7, #0]
|
|
80046d4: 689b ldr r3, [r3, #8]
|
|
80046d6: 021b lsls r3, r3, #8
|
|
80046d8: 697a ldr r2, [r7, #20]
|
|
80046da: 4313 orrs r3, r2
|
|
80046dc: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
80046de: 687b ldr r3, [r7, #4]
|
|
80046e0: 4a21 ldr r2, [pc, #132] @ (8004768 <TIM_OC3_SetConfig+0xe0>)
|
|
80046e2: 4293 cmp r3, r2
|
|
80046e4: d003 beq.n 80046ee <TIM_OC3_SetConfig+0x66>
|
|
80046e6: 687b ldr r3, [r7, #4]
|
|
80046e8: 4a20 ldr r2, [pc, #128] @ (800476c <TIM_OC3_SetConfig+0xe4>)
|
|
80046ea: 4293 cmp r3, r2
|
|
80046ec: d10d bne.n 800470a <TIM_OC3_SetConfig+0x82>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
80046ee: 697b ldr r3, [r7, #20]
|
|
80046f0: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
80046f4: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
80046f6: 683b ldr r3, [r7, #0]
|
|
80046f8: 68db ldr r3, [r3, #12]
|
|
80046fa: 021b lsls r3, r3, #8
|
|
80046fc: 697a ldr r2, [r7, #20]
|
|
80046fe: 4313 orrs r3, r2
|
|
8004700: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
8004702: 697b ldr r3, [r7, #20]
|
|
8004704: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8004708: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800470a: 687b ldr r3, [r7, #4]
|
|
800470c: 4a16 ldr r2, [pc, #88] @ (8004768 <TIM_OC3_SetConfig+0xe0>)
|
|
800470e: 4293 cmp r3, r2
|
|
8004710: d003 beq.n 800471a <TIM_OC3_SetConfig+0x92>
|
|
8004712: 687b ldr r3, [r7, #4]
|
|
8004714: 4a15 ldr r2, [pc, #84] @ (800476c <TIM_OC3_SetConfig+0xe4>)
|
|
8004716: 4293 cmp r3, r2
|
|
8004718: d113 bne.n 8004742 <TIM_OC3_SetConfig+0xba>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
800471a: 693b ldr r3, [r7, #16]
|
|
800471c: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
8004720: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
8004722: 693b ldr r3, [r7, #16]
|
|
8004724: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
8004728: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
800472a: 683b ldr r3, [r7, #0]
|
|
800472c: 695b ldr r3, [r3, #20]
|
|
800472e: 011b lsls r3, r3, #4
|
|
8004730: 693a ldr r2, [r7, #16]
|
|
8004732: 4313 orrs r3, r2
|
|
8004734: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
8004736: 683b ldr r3, [r7, #0]
|
|
8004738: 699b ldr r3, [r3, #24]
|
|
800473a: 011b lsls r3, r3, #4
|
|
800473c: 693a ldr r2, [r7, #16]
|
|
800473e: 4313 orrs r3, r2
|
|
8004740: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8004742: 687b ldr r3, [r7, #4]
|
|
8004744: 693a ldr r2, [r7, #16]
|
|
8004746: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8004748: 687b ldr r3, [r7, #4]
|
|
800474a: 68fa ldr r2, [r7, #12]
|
|
800474c: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
800474e: 683b ldr r3, [r7, #0]
|
|
8004750: 685a ldr r2, [r3, #4]
|
|
8004752: 687b ldr r3, [r7, #4]
|
|
8004754: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004756: 687b ldr r3, [r7, #4]
|
|
8004758: 697a ldr r2, [r7, #20]
|
|
800475a: 621a str r2, [r3, #32]
|
|
}
|
|
800475c: bf00 nop
|
|
800475e: 371c adds r7, #28
|
|
8004760: 46bd mov sp, r7
|
|
8004762: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004766: 4770 bx lr
|
|
8004768: 40010000 .word 0x40010000
|
|
800476c: 40010400 .word 0x40010400
|
|
|
|
08004770 <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8004770: b480 push {r7}
|
|
8004772: b087 sub sp, #28
|
|
8004774: af00 add r7, sp, #0
|
|
8004776: 6078 str r0, [r7, #4]
|
|
8004778: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800477a: 687b ldr r3, [r7, #4]
|
|
800477c: 6a1b ldr r3, [r3, #32]
|
|
800477e: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
8004780: 687b ldr r3, [r7, #4]
|
|
8004782: 6a1b ldr r3, [r3, #32]
|
|
8004784: f423 5280 bic.w r2, r3, #4096 @ 0x1000
|
|
8004788: 687b ldr r3, [r7, #4]
|
|
800478a: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800478c: 687b ldr r3, [r7, #4]
|
|
800478e: 685b ldr r3, [r3, #4]
|
|
8004790: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8004792: 687b ldr r3, [r7, #4]
|
|
8004794: 69db ldr r3, [r3, #28]
|
|
8004796: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
8004798: 68fb ldr r3, [r7, #12]
|
|
800479a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800479e: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
80047a0: 68fb ldr r3, [r7, #12]
|
|
80047a2: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80047a6: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
80047a8: 683b ldr r3, [r7, #0]
|
|
80047aa: 681b ldr r3, [r3, #0]
|
|
80047ac: 021b lsls r3, r3, #8
|
|
80047ae: 68fa ldr r2, [r7, #12]
|
|
80047b0: 4313 orrs r3, r2
|
|
80047b2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
80047b4: 693b ldr r3, [r7, #16]
|
|
80047b6: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
80047ba: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
80047bc: 683b ldr r3, [r7, #0]
|
|
80047be: 689b ldr r3, [r3, #8]
|
|
80047c0: 031b lsls r3, r3, #12
|
|
80047c2: 693a ldr r2, [r7, #16]
|
|
80047c4: 4313 orrs r3, r2
|
|
80047c6: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
80047c8: 687b ldr r3, [r7, #4]
|
|
80047ca: 4a12 ldr r2, [pc, #72] @ (8004814 <TIM_OC4_SetConfig+0xa4>)
|
|
80047cc: 4293 cmp r3, r2
|
|
80047ce: d003 beq.n 80047d8 <TIM_OC4_SetConfig+0x68>
|
|
80047d0: 687b ldr r3, [r7, #4]
|
|
80047d2: 4a11 ldr r2, [pc, #68] @ (8004818 <TIM_OC4_SetConfig+0xa8>)
|
|
80047d4: 4293 cmp r3, r2
|
|
80047d6: d109 bne.n 80047ec <TIM_OC4_SetConfig+0x7c>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
80047d8: 697b ldr r3, [r7, #20]
|
|
80047da: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
80047de: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
80047e0: 683b ldr r3, [r7, #0]
|
|
80047e2: 695b ldr r3, [r3, #20]
|
|
80047e4: 019b lsls r3, r3, #6
|
|
80047e6: 697a ldr r2, [r7, #20]
|
|
80047e8: 4313 orrs r3, r2
|
|
80047ea: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
80047ec: 687b ldr r3, [r7, #4]
|
|
80047ee: 697a ldr r2, [r7, #20]
|
|
80047f0: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
80047f2: 687b ldr r3, [r7, #4]
|
|
80047f4: 68fa ldr r2, [r7, #12]
|
|
80047f6: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
80047f8: 683b ldr r3, [r7, #0]
|
|
80047fa: 685a ldr r2, [r3, #4]
|
|
80047fc: 687b ldr r3, [r7, #4]
|
|
80047fe: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8004800: 687b ldr r3, [r7, #4]
|
|
8004802: 693a ldr r2, [r7, #16]
|
|
8004804: 621a str r2, [r3, #32]
|
|
}
|
|
8004806: bf00 nop
|
|
8004808: 371c adds r7, #28
|
|
800480a: 46bd mov sp, r7
|
|
800480c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004810: 4770 bx lr
|
|
8004812: bf00 nop
|
|
8004814: 40010000 .word 0x40010000
|
|
8004818: 40010400 .word 0x40010400
|
|
|
|
0800481c <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
800481c: b480 push {r7}
|
|
800481e: b085 sub sp, #20
|
|
8004820: af00 add r7, sp, #0
|
|
8004822: 6078 str r0, [r7, #4]
|
|
8004824: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8004826: 687b ldr r3, [r7, #4]
|
|
8004828: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
800482c: 2b01 cmp r3, #1
|
|
800482e: d101 bne.n 8004834 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8004830: 2302 movs r3, #2
|
|
8004832: e05a b.n 80048ea <HAL_TIMEx_MasterConfigSynchronization+0xce>
|
|
8004834: 687b ldr r3, [r7, #4]
|
|
8004836: 2201 movs r2, #1
|
|
8004838: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800483c: 687b ldr r3, [r7, #4]
|
|
800483e: 2202 movs r2, #2
|
|
8004840: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8004844: 687b ldr r3, [r7, #4]
|
|
8004846: 681b ldr r3, [r3, #0]
|
|
8004848: 685b ldr r3, [r3, #4]
|
|
800484a: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
800484c: 687b ldr r3, [r7, #4]
|
|
800484e: 681b ldr r3, [r3, #0]
|
|
8004850: 689b ldr r3, [r3, #8]
|
|
8004852: 60bb str r3, [r7, #8]
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8004854: 68fb ldr r3, [r7, #12]
|
|
8004856: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800485a: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
800485c: 683b ldr r3, [r7, #0]
|
|
800485e: 681b ldr r3, [r3, #0]
|
|
8004860: 68fa ldr r2, [r7, #12]
|
|
8004862: 4313 orrs r3, r2
|
|
8004864: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8004866: 687b ldr r3, [r7, #4]
|
|
8004868: 681b ldr r3, [r3, #0]
|
|
800486a: 68fa ldr r2, [r7, #12]
|
|
800486c: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
800486e: 687b ldr r3, [r7, #4]
|
|
8004870: 681b ldr r3, [r3, #0]
|
|
8004872: 4a21 ldr r2, [pc, #132] @ (80048f8 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
|
|
8004874: 4293 cmp r3, r2
|
|
8004876: d022 beq.n 80048be <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004878: 687b ldr r3, [r7, #4]
|
|
800487a: 681b ldr r3, [r3, #0]
|
|
800487c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8004880: d01d beq.n 80048be <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004882: 687b ldr r3, [r7, #4]
|
|
8004884: 681b ldr r3, [r3, #0]
|
|
8004886: 4a1d ldr r2, [pc, #116] @ (80048fc <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
|
|
8004888: 4293 cmp r3, r2
|
|
800488a: d018 beq.n 80048be <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
800488c: 687b ldr r3, [r7, #4]
|
|
800488e: 681b ldr r3, [r3, #0]
|
|
8004890: 4a1b ldr r2, [pc, #108] @ (8004900 <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
|
|
8004892: 4293 cmp r3, r2
|
|
8004894: d013 beq.n 80048be <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8004896: 687b ldr r3, [r7, #4]
|
|
8004898: 681b ldr r3, [r3, #0]
|
|
800489a: 4a1a ldr r2, [pc, #104] @ (8004904 <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
|
|
800489c: 4293 cmp r3, r2
|
|
800489e: d00e beq.n 80048be <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
80048a0: 687b ldr r3, [r7, #4]
|
|
80048a2: 681b ldr r3, [r3, #0]
|
|
80048a4: 4a18 ldr r2, [pc, #96] @ (8004908 <HAL_TIMEx_MasterConfigSynchronization+0xec>)
|
|
80048a6: 4293 cmp r3, r2
|
|
80048a8: d009 beq.n 80048be <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
80048aa: 687b ldr r3, [r7, #4]
|
|
80048ac: 681b ldr r3, [r3, #0]
|
|
80048ae: 4a17 ldr r2, [pc, #92] @ (800490c <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
|
|
80048b0: 4293 cmp r3, r2
|
|
80048b2: d004 beq.n 80048be <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
80048b4: 687b ldr r3, [r7, #4]
|
|
80048b6: 681b ldr r3, [r3, #0]
|
|
80048b8: 4a15 ldr r2, [pc, #84] @ (8004910 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
|
|
80048ba: 4293 cmp r3, r2
|
|
80048bc: d10c bne.n 80048d8 <HAL_TIMEx_MasterConfigSynchronization+0xbc>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
80048be: 68bb ldr r3, [r7, #8]
|
|
80048c0: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
80048c4: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
80048c6: 683b ldr r3, [r7, #0]
|
|
80048c8: 685b ldr r3, [r3, #4]
|
|
80048ca: 68ba ldr r2, [r7, #8]
|
|
80048cc: 4313 orrs r3, r2
|
|
80048ce: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
80048d0: 687b ldr r3, [r7, #4]
|
|
80048d2: 681b ldr r3, [r3, #0]
|
|
80048d4: 68ba ldr r2, [r7, #8]
|
|
80048d6: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80048d8: 687b ldr r3, [r7, #4]
|
|
80048da: 2201 movs r2, #1
|
|
80048dc: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
80048e0: 687b ldr r3, [r7, #4]
|
|
80048e2: 2200 movs r2, #0
|
|
80048e4: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
80048e8: 2300 movs r3, #0
|
|
}
|
|
80048ea: 4618 mov r0, r3
|
|
80048ec: 3714 adds r7, #20
|
|
80048ee: 46bd mov sp, r7
|
|
80048f0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80048f4: 4770 bx lr
|
|
80048f6: bf00 nop
|
|
80048f8: 40010000 .word 0x40010000
|
|
80048fc: 40000400 .word 0x40000400
|
|
8004900: 40000800 .word 0x40000800
|
|
8004904: 40000c00 .word 0x40000c00
|
|
8004908: 40010400 .word 0x40010400
|
|
800490c: 40014000 .word 0x40014000
|
|
8004910: 40001800 .word 0x40001800
|
|
|
|
08004914 <HAL_UART_Init>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8004914: b580 push {r7, lr}
|
|
8004916: b082 sub sp, #8
|
|
8004918: af00 add r7, sp, #0
|
|
800491a: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
800491c: 687b ldr r3, [r7, #4]
|
|
800491e: 2b00 cmp r3, #0
|
|
8004920: d101 bne.n 8004926 <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004922: 2301 movs r3, #1
|
|
8004924: e042 b.n 80049ac <HAL_UART_Init+0x98>
|
|
assert_param(IS_UART_INSTANCE(huart->Instance));
|
|
}
|
|
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
|
|
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8004926: 687b ldr r3, [r7, #4]
|
|
8004928: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
800492c: b2db uxtb r3, r3
|
|
800492e: 2b00 cmp r3, #0
|
|
8004930: d106 bne.n 8004940 <HAL_UART_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8004932: 687b ldr r3, [r7, #4]
|
|
8004934: 2200 movs r2, #0
|
|
8004936: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
800493a: 6878 ldr r0, [r7, #4]
|
|
800493c: f7fc f9e2 bl 8000d04 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8004940: 687b ldr r3, [r7, #4]
|
|
8004942: 2224 movs r2, #36 @ 0x24
|
|
8004944: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_UART_DISABLE(huart);
|
|
8004948: 687b ldr r3, [r7, #4]
|
|
800494a: 681b ldr r3, [r3, #0]
|
|
800494c: 68da ldr r2, [r3, #12]
|
|
800494e: 687b ldr r3, [r7, #4]
|
|
8004950: 681b ldr r3, [r3, #0]
|
|
8004952: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
8004956: 60da str r2, [r3, #12]
|
|
|
|
/* Set the UART Communication parameters */
|
|
UART_SetConfig(huart);
|
|
8004958: 6878 ldr r0, [r7, #4]
|
|
800495a: f000 f82b bl 80049b4 <UART_SetConfig>
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
800495e: 687b ldr r3, [r7, #4]
|
|
8004960: 681b ldr r3, [r3, #0]
|
|
8004962: 691a ldr r2, [r3, #16]
|
|
8004964: 687b ldr r3, [r7, #4]
|
|
8004966: 681b ldr r3, [r3, #0]
|
|
8004968: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
800496c: 611a str r2, [r3, #16]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
800496e: 687b ldr r3, [r7, #4]
|
|
8004970: 681b ldr r3, [r3, #0]
|
|
8004972: 695a ldr r2, [r3, #20]
|
|
8004974: 687b ldr r3, [r7, #4]
|
|
8004976: 681b ldr r3, [r3, #0]
|
|
8004978: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
800497c: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the peripheral */
|
|
__HAL_UART_ENABLE(huart);
|
|
800497e: 687b ldr r3, [r7, #4]
|
|
8004980: 681b ldr r3, [r3, #0]
|
|
8004982: 68da ldr r2, [r3, #12]
|
|
8004984: 687b ldr r3, [r7, #4]
|
|
8004986: 681b ldr r3, [r3, #0]
|
|
8004988: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
800498c: 60da str r2, [r3, #12]
|
|
|
|
/* Initialize the UART state */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800498e: 687b ldr r3, [r7, #4]
|
|
8004990: 2200 movs r2, #0
|
|
8004992: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004994: 687b ldr r3, [r7, #4]
|
|
8004996: 2220 movs r2, #32
|
|
8004998: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800499c: 687b ldr r3, [r7, #4]
|
|
800499e: 2220 movs r2, #32
|
|
80049a0: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
80049a4: 687b ldr r3, [r7, #4]
|
|
80049a6: 2200 movs r2, #0
|
|
80049a8: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_OK;
|
|
80049aa: 2300 movs r3, #0
|
|
}
|
|
80049ac: 4618 mov r0, r3
|
|
80049ae: 3708 adds r7, #8
|
|
80049b0: 46bd mov sp, r7
|
|
80049b2: bd80 pop {r7, pc}
|
|
|
|
080049b4 <UART_SetConfig>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
80049b4: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
80049b8: b0c0 sub sp, #256 @ 0x100
|
|
80049ba: af00 add r7, sp, #0
|
|
80049bc: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4
|
|
assert_param(IS_UART_MODE(huart->Init.Mode));
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits
|
|
according to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
80049c0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80049c4: 681b ldr r3, [r3, #0]
|
|
80049c6: 691b ldr r3, [r3, #16]
|
|
80049c8: f423 5040 bic.w r0, r3, #12288 @ 0x3000
|
|
80049cc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80049d0: 68d9 ldr r1, [r3, #12]
|
|
80049d2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80049d6: 681a ldr r2, [r3, #0]
|
|
80049d8: ea40 0301 orr.w r3, r0, r1
|
|
80049dc: 6113 str r3, [r2, #16]
|
|
Set the M bits according to huart->Init.WordLength value
|
|
Set PCE and PS bits according to huart->Init.Parity value
|
|
Set TE and RE bits according to huart->Init.Mode value
|
|
Set OVER8 bit according to huart->Init.OverSampling value */
|
|
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
|
|
80049de: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80049e2: 689a ldr r2, [r3, #8]
|
|
80049e4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80049e8: 691b ldr r3, [r3, #16]
|
|
80049ea: 431a orrs r2, r3
|
|
80049ec: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80049f0: 695b ldr r3, [r3, #20]
|
|
80049f2: 431a orrs r2, r3
|
|
80049f4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80049f8: 69db ldr r3, [r3, #28]
|
|
80049fa: 4313 orrs r3, r2
|
|
80049fc: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
8004a00: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004a04: 681b ldr r3, [r3, #0]
|
|
8004a06: 68db ldr r3, [r3, #12]
|
|
8004a08: f423 4116 bic.w r1, r3, #38400 @ 0x9600
|
|
8004a0c: f021 010c bic.w r1, r1, #12
|
|
8004a10: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004a14: 681a ldr r2, [r3, #0]
|
|
8004a16: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
|
|
8004a1a: 430b orrs r3, r1
|
|
8004a1c: 60d3 str r3, [r2, #12]
|
|
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
|
tmpreg);
|
|
|
|
/*-------------------------- USART CR3 Configuration -----------------------*/
|
|
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
|
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
|
8004a1e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004a22: 681b ldr r3, [r3, #0]
|
|
8004a24: 695b ldr r3, [r3, #20]
|
|
8004a26: f423 7040 bic.w r0, r3, #768 @ 0x300
|
|
8004a2a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004a2e: 6999 ldr r1, [r3, #24]
|
|
8004a30: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004a34: 681a ldr r2, [r3, #0]
|
|
8004a36: ea40 0301 orr.w r3, r0, r1
|
|
8004a3a: 6153 str r3, [r2, #20]
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#elif defined(USART6)
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6))
|
|
8004a3c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004a40: 681a ldr r2, [r3, #0]
|
|
8004a42: 4b8f ldr r3, [pc, #572] @ (8004c80 <UART_SetConfig+0x2cc>)
|
|
8004a44: 429a cmp r2, r3
|
|
8004a46: d005 beq.n 8004a54 <UART_SetConfig+0xa0>
|
|
8004a48: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004a4c: 681a ldr r2, [r3, #0]
|
|
8004a4e: 4b8d ldr r3, [pc, #564] @ (8004c84 <UART_SetConfig+0x2d0>)
|
|
8004a50: 429a cmp r2, r3
|
|
8004a52: d104 bne.n 8004a5e <UART_SetConfig+0xaa>
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8004a54: f7fe fb2e bl 80030b4 <HAL_RCC_GetPCLK2Freq>
|
|
8004a58: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
8004a5c: e003 b.n 8004a66 <UART_SetConfig+0xb2>
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#endif /* USART6 */
|
|
else
|
|
{
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8004a5e: f7fe fb15 bl 800308c <HAL_RCC_GetPCLK1Freq>
|
|
8004a62: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
}
|
|
/*-------------------------- USART BRR Configuration ---------------------*/
|
|
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8004a66: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004a6a: 69db ldr r3, [r3, #28]
|
|
8004a6c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8004a70: f040 810c bne.w 8004c8c <UART_SetConfig+0x2d8>
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
|
|
8004a74: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8004a78: 2200 movs r2, #0
|
|
8004a7a: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
|
|
8004a7e: f8c7 20ec str.w r2, [r7, #236] @ 0xec
|
|
8004a82: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8
|
|
8004a86: 4622 mov r2, r4
|
|
8004a88: 462b mov r3, r5
|
|
8004a8a: 1891 adds r1, r2, r2
|
|
8004a8c: 65b9 str r1, [r7, #88] @ 0x58
|
|
8004a8e: 415b adcs r3, r3
|
|
8004a90: 65fb str r3, [r7, #92] @ 0x5c
|
|
8004a92: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
|
|
8004a96: 4621 mov r1, r4
|
|
8004a98: eb12 0801 adds.w r8, r2, r1
|
|
8004a9c: 4629 mov r1, r5
|
|
8004a9e: eb43 0901 adc.w r9, r3, r1
|
|
8004aa2: f04f 0200 mov.w r2, #0
|
|
8004aa6: f04f 0300 mov.w r3, #0
|
|
8004aaa: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8004aae: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8004ab2: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
8004ab6: 4690 mov r8, r2
|
|
8004ab8: 4699 mov r9, r3
|
|
8004aba: 4623 mov r3, r4
|
|
8004abc: eb18 0303 adds.w r3, r8, r3
|
|
8004ac0: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
8004ac4: 462b mov r3, r5
|
|
8004ac6: eb49 0303 adc.w r3, r9, r3
|
|
8004aca: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
8004ace: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004ad2: 685b ldr r3, [r3, #4]
|
|
8004ad4: 2200 movs r2, #0
|
|
8004ad6: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
8004ada: f8c7 20dc str.w r2, [r7, #220] @ 0xdc
|
|
8004ade: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8
|
|
8004ae2: 460b mov r3, r1
|
|
8004ae4: 18db adds r3, r3, r3
|
|
8004ae6: 653b str r3, [r7, #80] @ 0x50
|
|
8004ae8: 4613 mov r3, r2
|
|
8004aea: eb42 0303 adc.w r3, r2, r3
|
|
8004aee: 657b str r3, [r7, #84] @ 0x54
|
|
8004af0: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50
|
|
8004af4: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0
|
|
8004af8: f7fb fb84 bl 8000204 <__aeabi_uldivmod>
|
|
8004afc: 4602 mov r2, r0
|
|
8004afe: 460b mov r3, r1
|
|
8004b00: 4b61 ldr r3, [pc, #388] @ (8004c88 <UART_SetConfig+0x2d4>)
|
|
8004b02: fba3 2302 umull r2, r3, r3, r2
|
|
8004b06: 095b lsrs r3, r3, #5
|
|
8004b08: 011c lsls r4, r3, #4
|
|
8004b0a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8004b0e: 2200 movs r2, #0
|
|
8004b10: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
8004b14: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4
|
|
8004b18: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0
|
|
8004b1c: 4642 mov r2, r8
|
|
8004b1e: 464b mov r3, r9
|
|
8004b20: 1891 adds r1, r2, r2
|
|
8004b22: 64b9 str r1, [r7, #72] @ 0x48
|
|
8004b24: 415b adcs r3, r3
|
|
8004b26: 64fb str r3, [r7, #76] @ 0x4c
|
|
8004b28: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
|
|
8004b2c: 4641 mov r1, r8
|
|
8004b2e: eb12 0a01 adds.w sl, r2, r1
|
|
8004b32: 4649 mov r1, r9
|
|
8004b34: eb43 0b01 adc.w fp, r3, r1
|
|
8004b38: f04f 0200 mov.w r2, #0
|
|
8004b3c: f04f 0300 mov.w r3, #0
|
|
8004b40: ea4f 03cb mov.w r3, fp, lsl #3
|
|
8004b44: ea43 735a orr.w r3, r3, sl, lsr #29
|
|
8004b48: ea4f 02ca mov.w r2, sl, lsl #3
|
|
8004b4c: 4692 mov sl, r2
|
|
8004b4e: 469b mov fp, r3
|
|
8004b50: 4643 mov r3, r8
|
|
8004b52: eb1a 0303 adds.w r3, sl, r3
|
|
8004b56: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
8004b5a: 464b mov r3, r9
|
|
8004b5c: eb4b 0303 adc.w r3, fp, r3
|
|
8004b60: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
|
|
8004b64: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004b68: 685b ldr r3, [r3, #4]
|
|
8004b6a: 2200 movs r2, #0
|
|
8004b6c: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
8004b70: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4
|
|
8004b74: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0
|
|
8004b78: 460b mov r3, r1
|
|
8004b7a: 18db adds r3, r3, r3
|
|
8004b7c: 643b str r3, [r7, #64] @ 0x40
|
|
8004b7e: 4613 mov r3, r2
|
|
8004b80: eb42 0303 adc.w r3, r2, r3
|
|
8004b84: 647b str r3, [r7, #68] @ 0x44
|
|
8004b86: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40
|
|
8004b8a: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8
|
|
8004b8e: f7fb fb39 bl 8000204 <__aeabi_uldivmod>
|
|
8004b92: 4602 mov r2, r0
|
|
8004b94: 460b mov r3, r1
|
|
8004b96: 4611 mov r1, r2
|
|
8004b98: 4b3b ldr r3, [pc, #236] @ (8004c88 <UART_SetConfig+0x2d4>)
|
|
8004b9a: fba3 2301 umull r2, r3, r3, r1
|
|
8004b9e: 095b lsrs r3, r3, #5
|
|
8004ba0: 2264 movs r2, #100 @ 0x64
|
|
8004ba2: fb02 f303 mul.w r3, r2, r3
|
|
8004ba6: 1acb subs r3, r1, r3
|
|
8004ba8: 00db lsls r3, r3, #3
|
|
8004baa: f103 0232 add.w r2, r3, #50 @ 0x32
|
|
8004bae: 4b36 ldr r3, [pc, #216] @ (8004c88 <UART_SetConfig+0x2d4>)
|
|
8004bb0: fba3 2302 umull r2, r3, r3, r2
|
|
8004bb4: 095b lsrs r3, r3, #5
|
|
8004bb6: 005b lsls r3, r3, #1
|
|
8004bb8: f403 73f8 and.w r3, r3, #496 @ 0x1f0
|
|
8004bbc: 441c add r4, r3
|
|
8004bbe: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8004bc2: 2200 movs r2, #0
|
|
8004bc4: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
8004bc8: f8c7 20bc str.w r2, [r7, #188] @ 0xbc
|
|
8004bcc: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8
|
|
8004bd0: 4642 mov r2, r8
|
|
8004bd2: 464b mov r3, r9
|
|
8004bd4: 1891 adds r1, r2, r2
|
|
8004bd6: 63b9 str r1, [r7, #56] @ 0x38
|
|
8004bd8: 415b adcs r3, r3
|
|
8004bda: 63fb str r3, [r7, #60] @ 0x3c
|
|
8004bdc: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38
|
|
8004be0: 4641 mov r1, r8
|
|
8004be2: 1851 adds r1, r2, r1
|
|
8004be4: 6339 str r1, [r7, #48] @ 0x30
|
|
8004be6: 4649 mov r1, r9
|
|
8004be8: 414b adcs r3, r1
|
|
8004bea: 637b str r3, [r7, #52] @ 0x34
|
|
8004bec: f04f 0200 mov.w r2, #0
|
|
8004bf0: f04f 0300 mov.w r3, #0
|
|
8004bf4: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30
|
|
8004bf8: 4659 mov r1, fp
|
|
8004bfa: 00cb lsls r3, r1, #3
|
|
8004bfc: 4651 mov r1, sl
|
|
8004bfe: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8004c02: 4651 mov r1, sl
|
|
8004c04: 00ca lsls r2, r1, #3
|
|
8004c06: 4610 mov r0, r2
|
|
8004c08: 4619 mov r1, r3
|
|
8004c0a: 4603 mov r3, r0
|
|
8004c0c: 4642 mov r2, r8
|
|
8004c0e: 189b adds r3, r3, r2
|
|
8004c10: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
8004c14: 464b mov r3, r9
|
|
8004c16: 460a mov r2, r1
|
|
8004c18: eb42 0303 adc.w r3, r2, r3
|
|
8004c1c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8004c20: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004c24: 685b ldr r3, [r3, #4]
|
|
8004c26: 2200 movs r2, #0
|
|
8004c28: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
8004c2c: f8c7 20ac str.w r2, [r7, #172] @ 0xac
|
|
8004c30: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8
|
|
8004c34: 460b mov r3, r1
|
|
8004c36: 18db adds r3, r3, r3
|
|
8004c38: 62bb str r3, [r7, #40] @ 0x28
|
|
8004c3a: 4613 mov r3, r2
|
|
8004c3c: eb42 0303 adc.w r3, r2, r3
|
|
8004c40: 62fb str r3, [r7, #44] @ 0x2c
|
|
8004c42: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
|
|
8004c46: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0
|
|
8004c4a: f7fb fadb bl 8000204 <__aeabi_uldivmod>
|
|
8004c4e: 4602 mov r2, r0
|
|
8004c50: 460b mov r3, r1
|
|
8004c52: 4b0d ldr r3, [pc, #52] @ (8004c88 <UART_SetConfig+0x2d4>)
|
|
8004c54: fba3 1302 umull r1, r3, r3, r2
|
|
8004c58: 095b lsrs r3, r3, #5
|
|
8004c5a: 2164 movs r1, #100 @ 0x64
|
|
8004c5c: fb01 f303 mul.w r3, r1, r3
|
|
8004c60: 1ad3 subs r3, r2, r3
|
|
8004c62: 00db lsls r3, r3, #3
|
|
8004c64: 3332 adds r3, #50 @ 0x32
|
|
8004c66: 4a08 ldr r2, [pc, #32] @ (8004c88 <UART_SetConfig+0x2d4>)
|
|
8004c68: fba2 2303 umull r2, r3, r2, r3
|
|
8004c6c: 095b lsrs r3, r3, #5
|
|
8004c6e: f003 0207 and.w r2, r3, #7
|
|
8004c72: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004c76: 681b ldr r3, [r3, #0]
|
|
8004c78: 4422 add r2, r4
|
|
8004c7a: 609a str r2, [r3, #8]
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
}
|
|
}
|
|
8004c7c: e106 b.n 8004e8c <UART_SetConfig+0x4d8>
|
|
8004c7e: bf00 nop
|
|
8004c80: 40011000 .word 0x40011000
|
|
8004c84: 40011400 .word 0x40011400
|
|
8004c88: 51eb851f .word 0x51eb851f
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
8004c8c: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8004c90: 2200 movs r2, #0
|
|
8004c92: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
8004c96: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4
|
|
8004c9a: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0
|
|
8004c9e: 4642 mov r2, r8
|
|
8004ca0: 464b mov r3, r9
|
|
8004ca2: 1891 adds r1, r2, r2
|
|
8004ca4: 6239 str r1, [r7, #32]
|
|
8004ca6: 415b adcs r3, r3
|
|
8004ca8: 627b str r3, [r7, #36] @ 0x24
|
|
8004caa: e9d7 2308 ldrd r2, r3, [r7, #32]
|
|
8004cae: 4641 mov r1, r8
|
|
8004cb0: 1854 adds r4, r2, r1
|
|
8004cb2: 4649 mov r1, r9
|
|
8004cb4: eb43 0501 adc.w r5, r3, r1
|
|
8004cb8: f04f 0200 mov.w r2, #0
|
|
8004cbc: f04f 0300 mov.w r3, #0
|
|
8004cc0: 00eb lsls r3, r5, #3
|
|
8004cc2: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
8004cc6: 00e2 lsls r2, r4, #3
|
|
8004cc8: 4614 mov r4, r2
|
|
8004cca: 461d mov r5, r3
|
|
8004ccc: 4643 mov r3, r8
|
|
8004cce: 18e3 adds r3, r4, r3
|
|
8004cd0: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8004cd4: 464b mov r3, r9
|
|
8004cd6: eb45 0303 adc.w r3, r5, r3
|
|
8004cda: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
8004cde: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004ce2: 685b ldr r3, [r3, #4]
|
|
8004ce4: 2200 movs r2, #0
|
|
8004ce6: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8004cea: f8c7 2094 str.w r2, [r7, #148] @ 0x94
|
|
8004cee: f04f 0200 mov.w r2, #0
|
|
8004cf2: f04f 0300 mov.w r3, #0
|
|
8004cf6: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
|
|
8004cfa: 4629 mov r1, r5
|
|
8004cfc: 008b lsls r3, r1, #2
|
|
8004cfe: 4621 mov r1, r4
|
|
8004d00: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8004d04: 4621 mov r1, r4
|
|
8004d06: 008a lsls r2, r1, #2
|
|
8004d08: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98
|
|
8004d0c: f7fb fa7a bl 8000204 <__aeabi_uldivmod>
|
|
8004d10: 4602 mov r2, r0
|
|
8004d12: 460b mov r3, r1
|
|
8004d14: 4b60 ldr r3, [pc, #384] @ (8004e98 <UART_SetConfig+0x4e4>)
|
|
8004d16: fba3 2302 umull r2, r3, r3, r2
|
|
8004d1a: 095b lsrs r3, r3, #5
|
|
8004d1c: 011c lsls r4, r3, #4
|
|
8004d1e: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8004d22: 2200 movs r2, #0
|
|
8004d24: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
8004d28: f8c7 208c str.w r2, [r7, #140] @ 0x8c
|
|
8004d2c: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88
|
|
8004d30: 4642 mov r2, r8
|
|
8004d32: 464b mov r3, r9
|
|
8004d34: 1891 adds r1, r2, r2
|
|
8004d36: 61b9 str r1, [r7, #24]
|
|
8004d38: 415b adcs r3, r3
|
|
8004d3a: 61fb str r3, [r7, #28]
|
|
8004d3c: e9d7 2306 ldrd r2, r3, [r7, #24]
|
|
8004d40: 4641 mov r1, r8
|
|
8004d42: 1851 adds r1, r2, r1
|
|
8004d44: 6139 str r1, [r7, #16]
|
|
8004d46: 4649 mov r1, r9
|
|
8004d48: 414b adcs r3, r1
|
|
8004d4a: 617b str r3, [r7, #20]
|
|
8004d4c: f04f 0200 mov.w r2, #0
|
|
8004d50: f04f 0300 mov.w r3, #0
|
|
8004d54: e9d7 ab04 ldrd sl, fp, [r7, #16]
|
|
8004d58: 4659 mov r1, fp
|
|
8004d5a: 00cb lsls r3, r1, #3
|
|
8004d5c: 4651 mov r1, sl
|
|
8004d5e: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8004d62: 4651 mov r1, sl
|
|
8004d64: 00ca lsls r2, r1, #3
|
|
8004d66: 4610 mov r0, r2
|
|
8004d68: 4619 mov r1, r3
|
|
8004d6a: 4603 mov r3, r0
|
|
8004d6c: 4642 mov r2, r8
|
|
8004d6e: 189b adds r3, r3, r2
|
|
8004d70: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8004d74: 464b mov r3, r9
|
|
8004d76: 460a mov r2, r1
|
|
8004d78: eb42 0303 adc.w r3, r2, r3
|
|
8004d7c: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8004d80: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004d84: 685b ldr r3, [r3, #4]
|
|
8004d86: 2200 movs r2, #0
|
|
8004d88: 67bb str r3, [r7, #120] @ 0x78
|
|
8004d8a: 67fa str r2, [r7, #124] @ 0x7c
|
|
8004d8c: f04f 0200 mov.w r2, #0
|
|
8004d90: f04f 0300 mov.w r3, #0
|
|
8004d94: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78
|
|
8004d98: 4649 mov r1, r9
|
|
8004d9a: 008b lsls r3, r1, #2
|
|
8004d9c: 4641 mov r1, r8
|
|
8004d9e: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8004da2: 4641 mov r1, r8
|
|
8004da4: 008a lsls r2, r1, #2
|
|
8004da6: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80
|
|
8004daa: f7fb fa2b bl 8000204 <__aeabi_uldivmod>
|
|
8004dae: 4602 mov r2, r0
|
|
8004db0: 460b mov r3, r1
|
|
8004db2: 4611 mov r1, r2
|
|
8004db4: 4b38 ldr r3, [pc, #224] @ (8004e98 <UART_SetConfig+0x4e4>)
|
|
8004db6: fba3 2301 umull r2, r3, r3, r1
|
|
8004dba: 095b lsrs r3, r3, #5
|
|
8004dbc: 2264 movs r2, #100 @ 0x64
|
|
8004dbe: fb02 f303 mul.w r3, r2, r3
|
|
8004dc2: 1acb subs r3, r1, r3
|
|
8004dc4: 011b lsls r3, r3, #4
|
|
8004dc6: 3332 adds r3, #50 @ 0x32
|
|
8004dc8: 4a33 ldr r2, [pc, #204] @ (8004e98 <UART_SetConfig+0x4e4>)
|
|
8004dca: fba2 2303 umull r2, r3, r2, r3
|
|
8004dce: 095b lsrs r3, r3, #5
|
|
8004dd0: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8004dd4: 441c add r4, r3
|
|
8004dd6: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8004dda: 2200 movs r2, #0
|
|
8004ddc: 673b str r3, [r7, #112] @ 0x70
|
|
8004dde: 677a str r2, [r7, #116] @ 0x74
|
|
8004de0: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70
|
|
8004de4: 4642 mov r2, r8
|
|
8004de6: 464b mov r3, r9
|
|
8004de8: 1891 adds r1, r2, r2
|
|
8004dea: 60b9 str r1, [r7, #8]
|
|
8004dec: 415b adcs r3, r3
|
|
8004dee: 60fb str r3, [r7, #12]
|
|
8004df0: e9d7 2302 ldrd r2, r3, [r7, #8]
|
|
8004df4: 4641 mov r1, r8
|
|
8004df6: 1851 adds r1, r2, r1
|
|
8004df8: 6039 str r1, [r7, #0]
|
|
8004dfa: 4649 mov r1, r9
|
|
8004dfc: 414b adcs r3, r1
|
|
8004dfe: 607b str r3, [r7, #4]
|
|
8004e00: f04f 0200 mov.w r2, #0
|
|
8004e04: f04f 0300 mov.w r3, #0
|
|
8004e08: e9d7 ab00 ldrd sl, fp, [r7]
|
|
8004e0c: 4659 mov r1, fp
|
|
8004e0e: 00cb lsls r3, r1, #3
|
|
8004e10: 4651 mov r1, sl
|
|
8004e12: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8004e16: 4651 mov r1, sl
|
|
8004e18: 00ca lsls r2, r1, #3
|
|
8004e1a: 4610 mov r0, r2
|
|
8004e1c: 4619 mov r1, r3
|
|
8004e1e: 4603 mov r3, r0
|
|
8004e20: 4642 mov r2, r8
|
|
8004e22: 189b adds r3, r3, r2
|
|
8004e24: 66bb str r3, [r7, #104] @ 0x68
|
|
8004e26: 464b mov r3, r9
|
|
8004e28: 460a mov r2, r1
|
|
8004e2a: eb42 0303 adc.w r3, r2, r3
|
|
8004e2e: 66fb str r3, [r7, #108] @ 0x6c
|
|
8004e30: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004e34: 685b ldr r3, [r3, #4]
|
|
8004e36: 2200 movs r2, #0
|
|
8004e38: 663b str r3, [r7, #96] @ 0x60
|
|
8004e3a: 667a str r2, [r7, #100] @ 0x64
|
|
8004e3c: f04f 0200 mov.w r2, #0
|
|
8004e40: f04f 0300 mov.w r3, #0
|
|
8004e44: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60
|
|
8004e48: 4649 mov r1, r9
|
|
8004e4a: 008b lsls r3, r1, #2
|
|
8004e4c: 4641 mov r1, r8
|
|
8004e4e: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8004e52: 4641 mov r1, r8
|
|
8004e54: 008a lsls r2, r1, #2
|
|
8004e56: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68
|
|
8004e5a: f7fb f9d3 bl 8000204 <__aeabi_uldivmod>
|
|
8004e5e: 4602 mov r2, r0
|
|
8004e60: 460b mov r3, r1
|
|
8004e62: 4b0d ldr r3, [pc, #52] @ (8004e98 <UART_SetConfig+0x4e4>)
|
|
8004e64: fba3 1302 umull r1, r3, r3, r2
|
|
8004e68: 095b lsrs r3, r3, #5
|
|
8004e6a: 2164 movs r1, #100 @ 0x64
|
|
8004e6c: fb01 f303 mul.w r3, r1, r3
|
|
8004e70: 1ad3 subs r3, r2, r3
|
|
8004e72: 011b lsls r3, r3, #4
|
|
8004e74: 3332 adds r3, #50 @ 0x32
|
|
8004e76: 4a08 ldr r2, [pc, #32] @ (8004e98 <UART_SetConfig+0x4e4>)
|
|
8004e78: fba2 2303 umull r2, r3, r2, r3
|
|
8004e7c: 095b lsrs r3, r3, #5
|
|
8004e7e: f003 020f and.w r2, r3, #15
|
|
8004e82: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8004e86: 681b ldr r3, [r3, #0]
|
|
8004e88: 4422 add r2, r4
|
|
8004e8a: 609a str r2, [r3, #8]
|
|
}
|
|
8004e8c: bf00 nop
|
|
8004e8e: f507 7780 add.w r7, r7, #256 @ 0x100
|
|
8004e92: 46bd mov sp, r7
|
|
8004e94: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8004e98: 51eb851f .word 0x51eb851f
|
|
|
|
08004e9c <USB_CoreInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8004e9c: b084 sub sp, #16
|
|
8004e9e: b580 push {r7, lr}
|
|
8004ea0: b084 sub sp, #16
|
|
8004ea2: af00 add r7, sp, #0
|
|
8004ea4: 6078 str r0, [r7, #4]
|
|
8004ea6: f107 001c add.w r0, r7, #28
|
|
8004eaa: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret;
|
|
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
|
|
8004eae: f897 3021 ldrb.w r3, [r7, #33] @ 0x21
|
|
8004eb2: 2b01 cmp r3, #1
|
|
8004eb4: d123 bne.n 8004efe <USB_CoreInit+0x62>
|
|
{
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
8004eb6: 687b ldr r3, [r7, #4]
|
|
8004eb8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004eba: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
8004ebe: 687b ldr r3, [r7, #4]
|
|
8004ec0: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Init The ULPI Interface */
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
|
|
8004ec2: 687b ldr r3, [r7, #4]
|
|
8004ec4: 68db ldr r3, [r3, #12]
|
|
8004ec6: f423 0384 bic.w r3, r3, #4325376 @ 0x420000
|
|
8004eca: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8004ece: 687a ldr r2, [r7, #4]
|
|
8004ed0: 60d3 str r3, [r2, #12]
|
|
|
|
/* Select vbus source */
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
|
|
8004ed2: 687b ldr r3, [r7, #4]
|
|
8004ed4: 68db ldr r3, [r3, #12]
|
|
8004ed6: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
8004eda: 687b ldr r3, [r7, #4]
|
|
8004edc: 60da str r2, [r3, #12]
|
|
if (cfg.use_external_vbus == 1U)
|
|
8004ede: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8004ee2: 2b01 cmp r3, #1
|
|
8004ee4: d105 bne.n 8004ef2 <USB_CoreInit+0x56>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
|
|
8004ee6: 687b ldr r3, [r7, #4]
|
|
8004ee8: 68db ldr r3, [r3, #12]
|
|
8004eea: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
|
|
8004eee: 687b ldr r3, [r7, #4]
|
|
8004ef0: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
8004ef2: 6878 ldr r0, [r7, #4]
|
|
8004ef4: f001 fae2 bl 80064bc <USB_CoreReset>
|
|
8004ef8: 4603 mov r3, r0
|
|
8004efa: 73fb strb r3, [r7, #15]
|
|
8004efc: e01b b.n 8004f36 <USB_CoreInit+0x9a>
|
|
}
|
|
else /* FS interface (embedded Phy) */
|
|
{
|
|
/* Select FS Embedded PHY */
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
|
|
8004efe: 687b ldr r3, [r7, #4]
|
|
8004f00: 68db ldr r3, [r3, #12]
|
|
8004f02: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
8004f06: 687b ldr r3, [r7, #4]
|
|
8004f08: 60da str r2, [r3, #12]
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
8004f0a: 6878 ldr r0, [r7, #4]
|
|
8004f0c: f001 fad6 bl 80064bc <USB_CoreReset>
|
|
8004f10: 4603 mov r3, r0
|
|
8004f12: 73fb strb r3, [r7, #15]
|
|
|
|
if (cfg.battery_charging_enable == 0U)
|
|
8004f14: f897 3025 ldrb.w r3, [r7, #37] @ 0x25
|
|
8004f18: 2b00 cmp r3, #0
|
|
8004f1a: d106 bne.n 8004f2a <USB_CoreInit+0x8e>
|
|
{
|
|
/* Activate the USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
8004f1c: 687b ldr r3, [r7, #4]
|
|
8004f1e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004f20: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
8004f24: 687b ldr r3, [r7, #4]
|
|
8004f26: 639a str r2, [r3, #56] @ 0x38
|
|
8004f28: e005 b.n 8004f36 <USB_CoreInit+0x9a>
|
|
}
|
|
else
|
|
{
|
|
/* Deactivate the USB Transceiver */
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
8004f2a: 687b ldr r3, [r7, #4]
|
|
8004f2c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004f2e: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
8004f32: 687b ldr r3, [r7, #4]
|
|
8004f34: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
}
|
|
|
|
if (cfg.dma_enable == 1U)
|
|
8004f36: 7fbb ldrb r3, [r7, #30]
|
|
8004f38: 2b01 cmp r3, #1
|
|
8004f3a: d10b bne.n 8004f54 <USB_CoreInit+0xb8>
|
|
{
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
|
|
8004f3c: 687b ldr r3, [r7, #4]
|
|
8004f3e: 689b ldr r3, [r3, #8]
|
|
8004f40: f043 0206 orr.w r2, r3, #6
|
|
8004f44: 687b ldr r3, [r7, #4]
|
|
8004f46: 609a str r2, [r3, #8]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
|
|
8004f48: 687b ldr r3, [r7, #4]
|
|
8004f4a: 689b ldr r3, [r3, #8]
|
|
8004f4c: f043 0220 orr.w r2, r3, #32
|
|
8004f50: 687b ldr r3, [r7, #4]
|
|
8004f52: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
return ret;
|
|
8004f54: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8004f56: 4618 mov r0, r3
|
|
8004f58: 3710 adds r7, #16
|
|
8004f5a: 46bd mov sp, r7
|
|
8004f5c: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
8004f60: b004 add sp, #16
|
|
8004f62: 4770 bx lr
|
|
|
|
08004f64 <USB_SetTurnaroundTime>:
|
|
* @param hclk: AHB clock frequency
|
|
* @retval USB turnaround time In PHY Clocks number
|
|
*/
|
|
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
|
|
uint32_t hclk, uint8_t speed)
|
|
{
|
|
8004f64: b480 push {r7}
|
|
8004f66: b087 sub sp, #28
|
|
8004f68: af00 add r7, sp, #0
|
|
8004f6a: 60f8 str r0, [r7, #12]
|
|
8004f6c: 60b9 str r1, [r7, #8]
|
|
8004f6e: 4613 mov r3, r2
|
|
8004f70: 71fb strb r3, [r7, #7]
|
|
|
|
/* The USBTRD is configured according to the tables below, depending on AHB frequency
|
|
used by application. In the low AHB frequency range it is used to stretch enough the USB response
|
|
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
|
|
latency to the Data FIFO */
|
|
if (speed == USBD_FS_SPEED)
|
|
8004f72: 79fb ldrb r3, [r7, #7]
|
|
8004f74: 2b02 cmp r3, #2
|
|
8004f76: d165 bne.n 8005044 <USB_SetTurnaroundTime+0xe0>
|
|
{
|
|
if ((hclk >= 14200000U) && (hclk < 15000000U))
|
|
8004f78: 68bb ldr r3, [r7, #8]
|
|
8004f7a: 4a41 ldr r2, [pc, #260] @ (8005080 <USB_SetTurnaroundTime+0x11c>)
|
|
8004f7c: 4293 cmp r3, r2
|
|
8004f7e: d906 bls.n 8004f8e <USB_SetTurnaroundTime+0x2a>
|
|
8004f80: 68bb ldr r3, [r7, #8]
|
|
8004f82: 4a40 ldr r2, [pc, #256] @ (8005084 <USB_SetTurnaroundTime+0x120>)
|
|
8004f84: 4293 cmp r3, r2
|
|
8004f86: d202 bcs.n 8004f8e <USB_SetTurnaroundTime+0x2a>
|
|
{
|
|
/* hclk Clock Range between 14.2-15 MHz */
|
|
UsbTrd = 0xFU;
|
|
8004f88: 230f movs r3, #15
|
|
8004f8a: 617b str r3, [r7, #20]
|
|
8004f8c: e062 b.n 8005054 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 15000000U) && (hclk < 16000000U))
|
|
8004f8e: 68bb ldr r3, [r7, #8]
|
|
8004f90: 4a3c ldr r2, [pc, #240] @ (8005084 <USB_SetTurnaroundTime+0x120>)
|
|
8004f92: 4293 cmp r3, r2
|
|
8004f94: d306 bcc.n 8004fa4 <USB_SetTurnaroundTime+0x40>
|
|
8004f96: 68bb ldr r3, [r7, #8]
|
|
8004f98: 4a3b ldr r2, [pc, #236] @ (8005088 <USB_SetTurnaroundTime+0x124>)
|
|
8004f9a: 4293 cmp r3, r2
|
|
8004f9c: d202 bcs.n 8004fa4 <USB_SetTurnaroundTime+0x40>
|
|
{
|
|
/* hclk Clock Range between 15-16 MHz */
|
|
UsbTrd = 0xEU;
|
|
8004f9e: 230e movs r3, #14
|
|
8004fa0: 617b str r3, [r7, #20]
|
|
8004fa2: e057 b.n 8005054 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 16000000U) && (hclk < 17200000U))
|
|
8004fa4: 68bb ldr r3, [r7, #8]
|
|
8004fa6: 4a38 ldr r2, [pc, #224] @ (8005088 <USB_SetTurnaroundTime+0x124>)
|
|
8004fa8: 4293 cmp r3, r2
|
|
8004faa: d306 bcc.n 8004fba <USB_SetTurnaroundTime+0x56>
|
|
8004fac: 68bb ldr r3, [r7, #8]
|
|
8004fae: 4a37 ldr r2, [pc, #220] @ (800508c <USB_SetTurnaroundTime+0x128>)
|
|
8004fb0: 4293 cmp r3, r2
|
|
8004fb2: d202 bcs.n 8004fba <USB_SetTurnaroundTime+0x56>
|
|
{
|
|
/* hclk Clock Range between 16-17.2 MHz */
|
|
UsbTrd = 0xDU;
|
|
8004fb4: 230d movs r3, #13
|
|
8004fb6: 617b str r3, [r7, #20]
|
|
8004fb8: e04c b.n 8005054 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 17200000U) && (hclk < 18500000U))
|
|
8004fba: 68bb ldr r3, [r7, #8]
|
|
8004fbc: 4a33 ldr r2, [pc, #204] @ (800508c <USB_SetTurnaroundTime+0x128>)
|
|
8004fbe: 4293 cmp r3, r2
|
|
8004fc0: d306 bcc.n 8004fd0 <USB_SetTurnaroundTime+0x6c>
|
|
8004fc2: 68bb ldr r3, [r7, #8]
|
|
8004fc4: 4a32 ldr r2, [pc, #200] @ (8005090 <USB_SetTurnaroundTime+0x12c>)
|
|
8004fc6: 4293 cmp r3, r2
|
|
8004fc8: d802 bhi.n 8004fd0 <USB_SetTurnaroundTime+0x6c>
|
|
{
|
|
/* hclk Clock Range between 17.2-18.5 MHz */
|
|
UsbTrd = 0xCU;
|
|
8004fca: 230c movs r3, #12
|
|
8004fcc: 617b str r3, [r7, #20]
|
|
8004fce: e041 b.n 8005054 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 18500000U) && (hclk < 20000000U))
|
|
8004fd0: 68bb ldr r3, [r7, #8]
|
|
8004fd2: 4a2f ldr r2, [pc, #188] @ (8005090 <USB_SetTurnaroundTime+0x12c>)
|
|
8004fd4: 4293 cmp r3, r2
|
|
8004fd6: d906 bls.n 8004fe6 <USB_SetTurnaroundTime+0x82>
|
|
8004fd8: 68bb ldr r3, [r7, #8]
|
|
8004fda: 4a2e ldr r2, [pc, #184] @ (8005094 <USB_SetTurnaroundTime+0x130>)
|
|
8004fdc: 4293 cmp r3, r2
|
|
8004fde: d802 bhi.n 8004fe6 <USB_SetTurnaroundTime+0x82>
|
|
{
|
|
/* hclk Clock Range between 18.5-20 MHz */
|
|
UsbTrd = 0xBU;
|
|
8004fe0: 230b movs r3, #11
|
|
8004fe2: 617b str r3, [r7, #20]
|
|
8004fe4: e036 b.n 8005054 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 20000000U) && (hclk < 21800000U))
|
|
8004fe6: 68bb ldr r3, [r7, #8]
|
|
8004fe8: 4a2a ldr r2, [pc, #168] @ (8005094 <USB_SetTurnaroundTime+0x130>)
|
|
8004fea: 4293 cmp r3, r2
|
|
8004fec: d906 bls.n 8004ffc <USB_SetTurnaroundTime+0x98>
|
|
8004fee: 68bb ldr r3, [r7, #8]
|
|
8004ff0: 4a29 ldr r2, [pc, #164] @ (8005098 <USB_SetTurnaroundTime+0x134>)
|
|
8004ff2: 4293 cmp r3, r2
|
|
8004ff4: d802 bhi.n 8004ffc <USB_SetTurnaroundTime+0x98>
|
|
{
|
|
/* hclk Clock Range between 20-21.8 MHz */
|
|
UsbTrd = 0xAU;
|
|
8004ff6: 230a movs r3, #10
|
|
8004ff8: 617b str r3, [r7, #20]
|
|
8004ffa: e02b b.n 8005054 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 21800000U) && (hclk < 24000000U))
|
|
8004ffc: 68bb ldr r3, [r7, #8]
|
|
8004ffe: 4a26 ldr r2, [pc, #152] @ (8005098 <USB_SetTurnaroundTime+0x134>)
|
|
8005000: 4293 cmp r3, r2
|
|
8005002: d906 bls.n 8005012 <USB_SetTurnaroundTime+0xae>
|
|
8005004: 68bb ldr r3, [r7, #8]
|
|
8005006: 4a25 ldr r2, [pc, #148] @ (800509c <USB_SetTurnaroundTime+0x138>)
|
|
8005008: 4293 cmp r3, r2
|
|
800500a: d202 bcs.n 8005012 <USB_SetTurnaroundTime+0xae>
|
|
{
|
|
/* hclk Clock Range between 21.8-24 MHz */
|
|
UsbTrd = 0x9U;
|
|
800500c: 2309 movs r3, #9
|
|
800500e: 617b str r3, [r7, #20]
|
|
8005010: e020 b.n 8005054 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 24000000U) && (hclk < 27700000U))
|
|
8005012: 68bb ldr r3, [r7, #8]
|
|
8005014: 4a21 ldr r2, [pc, #132] @ (800509c <USB_SetTurnaroundTime+0x138>)
|
|
8005016: 4293 cmp r3, r2
|
|
8005018: d306 bcc.n 8005028 <USB_SetTurnaroundTime+0xc4>
|
|
800501a: 68bb ldr r3, [r7, #8]
|
|
800501c: 4a20 ldr r2, [pc, #128] @ (80050a0 <USB_SetTurnaroundTime+0x13c>)
|
|
800501e: 4293 cmp r3, r2
|
|
8005020: d802 bhi.n 8005028 <USB_SetTurnaroundTime+0xc4>
|
|
{
|
|
/* hclk Clock Range between 24-27.7 MHz */
|
|
UsbTrd = 0x8U;
|
|
8005022: 2308 movs r3, #8
|
|
8005024: 617b str r3, [r7, #20]
|
|
8005026: e015 b.n 8005054 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 27700000U) && (hclk < 32000000U))
|
|
8005028: 68bb ldr r3, [r7, #8]
|
|
800502a: 4a1d ldr r2, [pc, #116] @ (80050a0 <USB_SetTurnaroundTime+0x13c>)
|
|
800502c: 4293 cmp r3, r2
|
|
800502e: d906 bls.n 800503e <USB_SetTurnaroundTime+0xda>
|
|
8005030: 68bb ldr r3, [r7, #8]
|
|
8005032: 4a1c ldr r2, [pc, #112] @ (80050a4 <USB_SetTurnaroundTime+0x140>)
|
|
8005034: 4293 cmp r3, r2
|
|
8005036: d202 bcs.n 800503e <USB_SetTurnaroundTime+0xda>
|
|
{
|
|
/* hclk Clock Range between 27.7-32 MHz */
|
|
UsbTrd = 0x7U;
|
|
8005038: 2307 movs r3, #7
|
|
800503a: 617b str r3, [r7, #20]
|
|
800503c: e00a b.n 8005054 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else /* if(hclk >= 32000000) */
|
|
{
|
|
/* hclk Clock Range between 32-200 MHz */
|
|
UsbTrd = 0x6U;
|
|
800503e: 2306 movs r3, #6
|
|
8005040: 617b str r3, [r7, #20]
|
|
8005042: e007 b.n 8005054 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
}
|
|
else if (speed == USBD_HS_SPEED)
|
|
8005044: 79fb ldrb r3, [r7, #7]
|
|
8005046: 2b00 cmp r3, #0
|
|
8005048: d102 bne.n 8005050 <USB_SetTurnaroundTime+0xec>
|
|
{
|
|
UsbTrd = USBD_HS_TRDT_VALUE;
|
|
800504a: 2309 movs r3, #9
|
|
800504c: 617b str r3, [r7, #20]
|
|
800504e: e001 b.n 8005054 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else
|
|
{
|
|
UsbTrd = USBD_DEFAULT_TRDT_VALUE;
|
|
8005050: 2309 movs r3, #9
|
|
8005052: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
|
|
8005054: 68fb ldr r3, [r7, #12]
|
|
8005056: 68db ldr r3, [r3, #12]
|
|
8005058: f423 5270 bic.w r2, r3, #15360 @ 0x3c00
|
|
800505c: 68fb ldr r3, [r7, #12]
|
|
800505e: 60da str r2, [r3, #12]
|
|
USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
|
|
8005060: 68fb ldr r3, [r7, #12]
|
|
8005062: 68da ldr r2, [r3, #12]
|
|
8005064: 697b ldr r3, [r7, #20]
|
|
8005066: 029b lsls r3, r3, #10
|
|
8005068: f403 5370 and.w r3, r3, #15360 @ 0x3c00
|
|
800506c: 431a orrs r2, r3
|
|
800506e: 68fb ldr r3, [r7, #12]
|
|
8005070: 60da str r2, [r3, #12]
|
|
|
|
return HAL_OK;
|
|
8005072: 2300 movs r3, #0
|
|
}
|
|
8005074: 4618 mov r0, r3
|
|
8005076: 371c adds r7, #28
|
|
8005078: 46bd mov sp, r7
|
|
800507a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800507e: 4770 bx lr
|
|
8005080: 00d8acbf .word 0x00d8acbf
|
|
8005084: 00e4e1c0 .word 0x00e4e1c0
|
|
8005088: 00f42400 .word 0x00f42400
|
|
800508c: 01067380 .word 0x01067380
|
|
8005090: 011a499f .word 0x011a499f
|
|
8005094: 01312cff .word 0x01312cff
|
|
8005098: 014ca43f .word 0x014ca43f
|
|
800509c: 016e3600 .word 0x016e3600
|
|
80050a0: 01a6ab1f .word 0x01a6ab1f
|
|
80050a4: 01e84800 .word 0x01e84800
|
|
|
|
080050a8 <USB_EnableGlobalInt>:
|
|
* Enables the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80050a8: b480 push {r7}
|
|
80050aa: b083 sub sp, #12
|
|
80050ac: af00 add r7, sp, #0
|
|
80050ae: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
|
|
80050b0: 687b ldr r3, [r7, #4]
|
|
80050b2: 689b ldr r3, [r3, #8]
|
|
80050b4: f043 0201 orr.w r2, r3, #1
|
|
80050b8: 687b ldr r3, [r7, #4]
|
|
80050ba: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
80050bc: 2300 movs r3, #0
|
|
}
|
|
80050be: 4618 mov r0, r3
|
|
80050c0: 370c adds r7, #12
|
|
80050c2: 46bd mov sp, r7
|
|
80050c4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80050c8: 4770 bx lr
|
|
|
|
080050ca <USB_DisableGlobalInt>:
|
|
* Disable the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80050ca: b480 push {r7}
|
|
80050cc: b083 sub sp, #12
|
|
80050ce: af00 add r7, sp, #0
|
|
80050d0: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
|
|
80050d2: 687b ldr r3, [r7, #4]
|
|
80050d4: 689b ldr r3, [r3, #8]
|
|
80050d6: f023 0201 bic.w r2, r3, #1
|
|
80050da: 687b ldr r3, [r7, #4]
|
|
80050dc: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
80050de: 2300 movs r3, #0
|
|
}
|
|
80050e0: 4618 mov r0, r3
|
|
80050e2: 370c adds r7, #12
|
|
80050e4: 46bd mov sp, r7
|
|
80050e6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80050ea: 4770 bx lr
|
|
|
|
080050ec <USB_SetCurrentMode>:
|
|
* @arg USB_DEVICE_MODE Peripheral mode
|
|
* @arg USB_HOST_MODE Host mode
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
|
|
{
|
|
80050ec: b580 push {r7, lr}
|
|
80050ee: b084 sub sp, #16
|
|
80050f0: af00 add r7, sp, #0
|
|
80050f2: 6078 str r0, [r7, #4]
|
|
80050f4: 460b mov r3, r1
|
|
80050f6: 70fb strb r3, [r7, #3]
|
|
uint32_t ms = 0U;
|
|
80050f8: 2300 movs r3, #0
|
|
80050fa: 60fb str r3, [r7, #12]
|
|
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
|
|
80050fc: 687b ldr r3, [r7, #4]
|
|
80050fe: 68db ldr r3, [r3, #12]
|
|
8005100: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000
|
|
8005104: 687b ldr r3, [r7, #4]
|
|
8005106: 60da str r2, [r3, #12]
|
|
|
|
if (mode == USB_HOST_MODE)
|
|
8005108: 78fb ldrb r3, [r7, #3]
|
|
800510a: 2b01 cmp r3, #1
|
|
800510c: d115 bne.n 800513a <USB_SetCurrentMode+0x4e>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
|
|
800510e: 687b ldr r3, [r7, #4]
|
|
8005110: 68db ldr r3, [r3, #12]
|
|
8005112: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000
|
|
8005116: 687b ldr r3, [r7, #4]
|
|
8005118: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
800511a: 200a movs r0, #10
|
|
800511c: f7fc f816 bl 800114c <HAL_Delay>
|
|
ms += 10U;
|
|
8005120: 68fb ldr r3, [r7, #12]
|
|
8005122: 330a adds r3, #10
|
|
8005124: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
8005126: 6878 ldr r0, [r7, #4]
|
|
8005128: f001 f939 bl 800639e <USB_GetMode>
|
|
800512c: 4603 mov r3, r0
|
|
800512e: 2b01 cmp r3, #1
|
|
8005130: d01e beq.n 8005170 <USB_SetCurrentMode+0x84>
|
|
8005132: 68fb ldr r3, [r7, #12]
|
|
8005134: 2bc7 cmp r3, #199 @ 0xc7
|
|
8005136: d9f0 bls.n 800511a <USB_SetCurrentMode+0x2e>
|
|
8005138: e01a b.n 8005170 <USB_SetCurrentMode+0x84>
|
|
}
|
|
else if (mode == USB_DEVICE_MODE)
|
|
800513a: 78fb ldrb r3, [r7, #3]
|
|
800513c: 2b00 cmp r3, #0
|
|
800513e: d115 bne.n 800516c <USB_SetCurrentMode+0x80>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
|
|
8005140: 687b ldr r3, [r7, #4]
|
|
8005142: 68db ldr r3, [r3, #12]
|
|
8005144: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000
|
|
8005148: 687b ldr r3, [r7, #4]
|
|
800514a: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
800514c: 200a movs r0, #10
|
|
800514e: f7fb fffd bl 800114c <HAL_Delay>
|
|
ms += 10U;
|
|
8005152: 68fb ldr r3, [r7, #12]
|
|
8005154: 330a adds r3, #10
|
|
8005156: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
8005158: 6878 ldr r0, [r7, #4]
|
|
800515a: f001 f920 bl 800639e <USB_GetMode>
|
|
800515e: 4603 mov r3, r0
|
|
8005160: 2b00 cmp r3, #0
|
|
8005162: d005 beq.n 8005170 <USB_SetCurrentMode+0x84>
|
|
8005164: 68fb ldr r3, [r7, #12]
|
|
8005166: 2bc7 cmp r3, #199 @ 0xc7
|
|
8005168: d9f0 bls.n 800514c <USB_SetCurrentMode+0x60>
|
|
800516a: e001 b.n 8005170 <USB_SetCurrentMode+0x84>
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
800516c: 2301 movs r3, #1
|
|
800516e: e005 b.n 800517c <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
|
|
8005170: 68fb ldr r3, [r7, #12]
|
|
8005172: 2bc8 cmp r3, #200 @ 0xc8
|
|
8005174: d101 bne.n 800517a <USB_SetCurrentMode+0x8e>
|
|
{
|
|
return HAL_ERROR;
|
|
8005176: 2301 movs r3, #1
|
|
8005178: e000 b.n 800517c <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800517a: 2300 movs r3, #0
|
|
}
|
|
800517c: 4618 mov r0, r3
|
|
800517e: 3710 adds r7, #16
|
|
8005180: 46bd mov sp, r7
|
|
8005182: bd80 pop {r7, pc}
|
|
|
|
08005184 <USB_DevInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8005184: b084 sub sp, #16
|
|
8005186: b580 push {r7, lr}
|
|
8005188: b086 sub sp, #24
|
|
800518a: af00 add r7, sp, #0
|
|
800518c: 6078 str r0, [r7, #4]
|
|
800518e: f107 0024 add.w r0, r7, #36 @ 0x24
|
|
8005192: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8005196: 2300 movs r3, #0
|
|
8005198: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800519a: 687b ldr r3, [r7, #4]
|
|
800519c: 60fb str r3, [r7, #12]
|
|
uint32_t i;
|
|
|
|
for (i = 0U; i < 15U; i++)
|
|
800519e: 2300 movs r3, #0
|
|
80051a0: 613b str r3, [r7, #16]
|
|
80051a2: e009 b.n 80051b8 <USB_DevInit+0x34>
|
|
{
|
|
USBx->DIEPTXF[i] = 0U;
|
|
80051a4: 687a ldr r2, [r7, #4]
|
|
80051a6: 693b ldr r3, [r7, #16]
|
|
80051a8: 3340 adds r3, #64 @ 0x40
|
|
80051aa: 009b lsls r3, r3, #2
|
|
80051ac: 4413 add r3, r2
|
|
80051ae: 2200 movs r2, #0
|
|
80051b0: 605a str r2, [r3, #4]
|
|
for (i = 0U; i < 15U; i++)
|
|
80051b2: 693b ldr r3, [r7, #16]
|
|
80051b4: 3301 adds r3, #1
|
|
80051b6: 613b str r3, [r7, #16]
|
|
80051b8: 693b ldr r3, [r7, #16]
|
|
80051ba: 2b0e cmp r3, #14
|
|
80051bc: d9f2 bls.n 80051a4 <USB_DevInit+0x20>
|
|
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* VBUS Sensing setup */
|
|
if (cfg.vbus_sensing_enable == 0U)
|
|
80051be: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
80051c2: 2b00 cmp r3, #0
|
|
80051c4: d11c bne.n 8005200 <USB_DevInit+0x7c>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
80051c6: 68fb ldr r3, [r7, #12]
|
|
80051c8: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80051cc: 685b ldr r3, [r3, #4]
|
|
80051ce: 68fa ldr r2, [r7, #12]
|
|
80051d0: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80051d4: f043 0302 orr.w r3, r3, #2
|
|
80051d8: 6053 str r3, [r2, #4]
|
|
|
|
/* Deactivate VBUS Sensing B */
|
|
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
|
|
80051da: 687b ldr r3, [r7, #4]
|
|
80051dc: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80051de: f423 1200 bic.w r2, r3, #2097152 @ 0x200000
|
|
80051e2: 687b ldr r3, [r7, #4]
|
|
80051e4: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* B-peripheral session valid override enable */
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
|
|
80051e6: 687b ldr r3, [r7, #4]
|
|
80051e8: 681b ldr r3, [r3, #0]
|
|
80051ea: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
80051ee: 687b ldr r3, [r7, #4]
|
|
80051f0: 601a str r2, [r3, #0]
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
|
|
80051f2: 687b ldr r3, [r7, #4]
|
|
80051f4: 681b ldr r3, [r3, #0]
|
|
80051f6: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
80051fa: 687b ldr r3, [r7, #4]
|
|
80051fc: 601a str r2, [r3, #0]
|
|
80051fe: e005 b.n 800520c <USB_DevInit+0x88>
|
|
}
|
|
else
|
|
{
|
|
/* Enable HW VBUS sensing */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
|
|
8005200: 687b ldr r3, [r7, #4]
|
|
8005202: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005204: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
|
|
8005208: 687b ldr r3, [r7, #4]
|
|
800520a: 639a str r2, [r3, #56] @ 0x38
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
|
|
/* Restart the Phy Clock */
|
|
USBx_PCGCCTL = 0U;
|
|
800520c: 68fb ldr r3, [r7, #12]
|
|
800520e: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
8005212: 461a mov r2, r3
|
|
8005214: 2300 movs r3, #0
|
|
8005216: 6013 str r3, [r2, #0]
|
|
|
|
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
|
|
8005218: f897 3029 ldrb.w r3, [r7, #41] @ 0x29
|
|
800521c: 2b01 cmp r3, #1
|
|
800521e: d10d bne.n 800523c <USB_DevInit+0xb8>
|
|
{
|
|
if (cfg.speed == USBD_HS_SPEED)
|
|
8005220: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8005224: 2b00 cmp r3, #0
|
|
8005226: d104 bne.n 8005232 <USB_DevInit+0xae>
|
|
{
|
|
/* Set Core speed to High speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
|
|
8005228: 2100 movs r1, #0
|
|
800522a: 6878 ldr r0, [r7, #4]
|
|
800522c: f000 f968 bl 8005500 <USB_SetDevSpeed>
|
|
8005230: e008 b.n 8005244 <USB_DevInit+0xc0>
|
|
}
|
|
else
|
|
{
|
|
/* Set Core speed to Full speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
|
|
8005232: 2101 movs r1, #1
|
|
8005234: 6878 ldr r0, [r7, #4]
|
|
8005236: f000 f963 bl 8005500 <USB_SetDevSpeed>
|
|
800523a: e003 b.n 8005244 <USB_DevInit+0xc0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set Core speed to Full speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
|
|
800523c: 2103 movs r1, #3
|
|
800523e: 6878 ldr r0, [r7, #4]
|
|
8005240: f000 f95e bl 8005500 <USB_SetDevSpeed>
|
|
}
|
|
|
|
/* Flush the FIFOs */
|
|
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
|
|
8005244: 2110 movs r1, #16
|
|
8005246: 6878 ldr r0, [r7, #4]
|
|
8005248: f000 f8fa bl 8005440 <USB_FlushTxFifo>
|
|
800524c: 4603 mov r3, r0
|
|
800524e: 2b00 cmp r3, #0
|
|
8005250: d001 beq.n 8005256 <USB_DevInit+0xd2>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005252: 2301 movs r3, #1
|
|
8005254: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (USB_FlushRxFifo(USBx) != HAL_OK)
|
|
8005256: 6878 ldr r0, [r7, #4]
|
|
8005258: f000 f924 bl 80054a4 <USB_FlushRxFifo>
|
|
800525c: 4603 mov r3, r0
|
|
800525e: 2b00 cmp r3, #0
|
|
8005260: d001 beq.n 8005266 <USB_DevInit+0xe2>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005262: 2301 movs r3, #1
|
|
8005264: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Clear all pending Device Interrupts */
|
|
USBx_DEVICE->DIEPMSK = 0U;
|
|
8005266: 68fb ldr r3, [r7, #12]
|
|
8005268: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800526c: 461a mov r2, r3
|
|
800526e: 2300 movs r3, #0
|
|
8005270: 6113 str r3, [r2, #16]
|
|
USBx_DEVICE->DOEPMSK = 0U;
|
|
8005272: 68fb ldr r3, [r7, #12]
|
|
8005274: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005278: 461a mov r2, r3
|
|
800527a: 2300 movs r3, #0
|
|
800527c: 6153 str r3, [r2, #20]
|
|
USBx_DEVICE->DAINTMSK = 0U;
|
|
800527e: 68fb ldr r3, [r7, #12]
|
|
8005280: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005284: 461a mov r2, r3
|
|
8005286: 2300 movs r3, #0
|
|
8005288: 61d3 str r3, [r2, #28]
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
800528a: 2300 movs r3, #0
|
|
800528c: 613b str r3, [r7, #16]
|
|
800528e: e043 b.n 8005318 <USB_DevInit+0x194>
|
|
{
|
|
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
8005290: 693b ldr r3, [r7, #16]
|
|
8005292: 015a lsls r2, r3, #5
|
|
8005294: 68fb ldr r3, [r7, #12]
|
|
8005296: 4413 add r3, r2
|
|
8005298: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800529c: 681b ldr r3, [r3, #0]
|
|
800529e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80052a2: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80052a6: d118 bne.n 80052da <USB_DevInit+0x156>
|
|
{
|
|
if (i == 0U)
|
|
80052a8: 693b ldr r3, [r7, #16]
|
|
80052aa: 2b00 cmp r3, #0
|
|
80052ac: d10a bne.n 80052c4 <USB_DevInit+0x140>
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
|
|
80052ae: 693b ldr r3, [r7, #16]
|
|
80052b0: 015a lsls r2, r3, #5
|
|
80052b2: 68fb ldr r3, [r7, #12]
|
|
80052b4: 4413 add r3, r2
|
|
80052b6: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80052ba: 461a mov r2, r3
|
|
80052bc: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
80052c0: 6013 str r3, [r2, #0]
|
|
80052c2: e013 b.n 80052ec <USB_DevInit+0x168>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
|
|
80052c4: 693b ldr r3, [r7, #16]
|
|
80052c6: 015a lsls r2, r3, #5
|
|
80052c8: 68fb ldr r3, [r7, #12]
|
|
80052ca: 4413 add r3, r2
|
|
80052cc: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80052d0: 461a mov r2, r3
|
|
80052d2: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
80052d6: 6013 str r3, [r2, #0]
|
|
80052d8: e008 b.n 80052ec <USB_DevInit+0x168>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = 0U;
|
|
80052da: 693b ldr r3, [r7, #16]
|
|
80052dc: 015a lsls r2, r3, #5
|
|
80052de: 68fb ldr r3, [r7, #12]
|
|
80052e0: 4413 add r3, r2
|
|
80052e2: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80052e6: 461a mov r2, r3
|
|
80052e8: 2300 movs r3, #0
|
|
80052ea: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_INEP(i)->DIEPTSIZ = 0U;
|
|
80052ec: 693b ldr r3, [r7, #16]
|
|
80052ee: 015a lsls r2, r3, #5
|
|
80052f0: 68fb ldr r3, [r7, #12]
|
|
80052f2: 4413 add r3, r2
|
|
80052f4: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80052f8: 461a mov r2, r3
|
|
80052fa: 2300 movs r3, #0
|
|
80052fc: 6113 str r3, [r2, #16]
|
|
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
|
80052fe: 693b ldr r3, [r7, #16]
|
|
8005300: 015a lsls r2, r3, #5
|
|
8005302: 68fb ldr r3, [r7, #12]
|
|
8005304: 4413 add r3, r2
|
|
8005306: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800530a: 461a mov r2, r3
|
|
800530c: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
8005310: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8005312: 693b ldr r3, [r7, #16]
|
|
8005314: 3301 adds r3, #1
|
|
8005316: 613b str r3, [r7, #16]
|
|
8005318: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
800531c: 461a mov r2, r3
|
|
800531e: 693b ldr r3, [r7, #16]
|
|
8005320: 4293 cmp r3, r2
|
|
8005322: d3b5 bcc.n 8005290 <USB_DevInit+0x10c>
|
|
}
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8005324: 2300 movs r3, #0
|
|
8005326: 613b str r3, [r7, #16]
|
|
8005328: e043 b.n 80053b2 <USB_DevInit+0x22e>
|
|
{
|
|
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
800532a: 693b ldr r3, [r7, #16]
|
|
800532c: 015a lsls r2, r3, #5
|
|
800532e: 68fb ldr r3, [r7, #12]
|
|
8005330: 4413 add r3, r2
|
|
8005332: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005336: 681b ldr r3, [r3, #0]
|
|
8005338: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
800533c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8005340: d118 bne.n 8005374 <USB_DevInit+0x1f0>
|
|
{
|
|
if (i == 0U)
|
|
8005342: 693b ldr r3, [r7, #16]
|
|
8005344: 2b00 cmp r3, #0
|
|
8005346: d10a bne.n 800535e <USB_DevInit+0x1da>
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
|
|
8005348: 693b ldr r3, [r7, #16]
|
|
800534a: 015a lsls r2, r3, #5
|
|
800534c: 68fb ldr r3, [r7, #12]
|
|
800534e: 4413 add r3, r2
|
|
8005350: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005354: 461a mov r2, r3
|
|
8005356: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
800535a: 6013 str r3, [r2, #0]
|
|
800535c: e013 b.n 8005386 <USB_DevInit+0x202>
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
|
|
800535e: 693b ldr r3, [r7, #16]
|
|
8005360: 015a lsls r2, r3, #5
|
|
8005362: 68fb ldr r3, [r7, #12]
|
|
8005364: 4413 add r3, r2
|
|
8005366: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800536a: 461a mov r2, r3
|
|
800536c: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
8005370: 6013 str r3, [r2, #0]
|
|
8005372: e008 b.n 8005386 <USB_DevInit+0x202>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = 0U;
|
|
8005374: 693b ldr r3, [r7, #16]
|
|
8005376: 015a lsls r2, r3, #5
|
|
8005378: 68fb ldr r3, [r7, #12]
|
|
800537a: 4413 add r3, r2
|
|
800537c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005380: 461a mov r2, r3
|
|
8005382: 2300 movs r3, #0
|
|
8005384: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_OUTEP(i)->DOEPTSIZ = 0U;
|
|
8005386: 693b ldr r3, [r7, #16]
|
|
8005388: 015a lsls r2, r3, #5
|
|
800538a: 68fb ldr r3, [r7, #12]
|
|
800538c: 4413 add r3, r2
|
|
800538e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005392: 461a mov r2, r3
|
|
8005394: 2300 movs r3, #0
|
|
8005396: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
|
8005398: 693b ldr r3, [r7, #16]
|
|
800539a: 015a lsls r2, r3, #5
|
|
800539c: 68fb ldr r3, [r7, #12]
|
|
800539e: 4413 add r3, r2
|
|
80053a0: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80053a4: 461a mov r2, r3
|
|
80053a6: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
80053aa: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
80053ac: 693b ldr r3, [r7, #16]
|
|
80053ae: 3301 adds r3, #1
|
|
80053b0: 613b str r3, [r7, #16]
|
|
80053b2: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
80053b6: 461a mov r2, r3
|
|
80053b8: 693b ldr r3, [r7, #16]
|
|
80053ba: 4293 cmp r3, r2
|
|
80053bc: d3b5 bcc.n 800532a <USB_DevInit+0x1a6>
|
|
}
|
|
|
|
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
|
|
80053be: 68fb ldr r3, [r7, #12]
|
|
80053c0: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80053c4: 691b ldr r3, [r3, #16]
|
|
80053c6: 68fa ldr r2, [r7, #12]
|
|
80053c8: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80053cc: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
80053d0: 6113 str r3, [r2, #16]
|
|
|
|
/* Disable all interrupts. */
|
|
USBx->GINTMSK = 0U;
|
|
80053d2: 687b ldr r3, [r7, #4]
|
|
80053d4: 2200 movs r2, #0
|
|
80053d6: 619a str r2, [r3, #24]
|
|
|
|
/* Clear any pending interrupts */
|
|
USBx->GINTSTS = 0xBFFFFFFFU;
|
|
80053d8: 687b ldr r3, [r7, #4]
|
|
80053da: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000
|
|
80053de: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the common interrupts */
|
|
if (cfg.dma_enable == 0U)
|
|
80053e0: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
|
|
80053e4: 2b00 cmp r3, #0
|
|
80053e6: d105 bne.n 80053f4 <USB_DevInit+0x270>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
|
|
80053e8: 687b ldr r3, [r7, #4]
|
|
80053ea: 699b ldr r3, [r3, #24]
|
|
80053ec: f043 0210 orr.w r2, r3, #16
|
|
80053f0: 687b ldr r3, [r7, #4]
|
|
80053f2: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
/* Enable interrupts matching to the Device mode ONLY */
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
|
|
80053f4: 687b ldr r3, [r7, #4]
|
|
80053f6: 699a ldr r2, [r3, #24]
|
|
80053f8: 4b10 ldr r3, [pc, #64] @ (800543c <USB_DevInit+0x2b8>)
|
|
80053fa: 4313 orrs r3, r2
|
|
80053fc: 687a ldr r2, [r7, #4]
|
|
80053fe: 6193 str r3, [r2, #24]
|
|
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
|
|
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
|
|
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
|
|
|
|
if (cfg.Sof_enable != 0U)
|
|
8005400: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
8005404: 2b00 cmp r3, #0
|
|
8005406: d005 beq.n 8005414 <USB_DevInit+0x290>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
|
|
8005408: 687b ldr r3, [r7, #4]
|
|
800540a: 699b ldr r3, [r3, #24]
|
|
800540c: f043 0208 orr.w r2, r3, #8
|
|
8005410: 687b ldr r3, [r7, #4]
|
|
8005412: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (cfg.vbus_sensing_enable == 1U)
|
|
8005414: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
8005418: 2b01 cmp r3, #1
|
|
800541a: d107 bne.n 800542c <USB_DevInit+0x2a8>
|
|
{
|
|
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
|
|
800541c: 687b ldr r3, [r7, #4]
|
|
800541e: 699b ldr r3, [r3, #24]
|
|
8005420: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8005424: f043 0304 orr.w r3, r3, #4
|
|
8005428: 687a ldr r2, [r7, #4]
|
|
800542a: 6193 str r3, [r2, #24]
|
|
}
|
|
|
|
return ret;
|
|
800542c: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800542e: 4618 mov r0, r3
|
|
8005430: 3718 adds r7, #24
|
|
8005432: 46bd mov sp, r7
|
|
8005434: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
8005438: b004 add sp, #16
|
|
800543a: 4770 bx lr
|
|
800543c: 803c3800 .word 0x803c3800
|
|
|
|
08005440 <USB_FlushTxFifo>:
|
|
* This parameter can be a value from 1 to 15
|
|
15 means Flush all Tx FIFOs
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
|
|
{
|
|
8005440: b480 push {r7}
|
|
8005442: b085 sub sp, #20
|
|
8005444: af00 add r7, sp, #0
|
|
8005446: 6078 str r0, [r7, #4]
|
|
8005448: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
800544a: 2300 movs r3, #0
|
|
800544c: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
800544e: 68fb ldr r3, [r7, #12]
|
|
8005450: 3301 adds r3, #1
|
|
8005452: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8005454: 68fb ldr r3, [r7, #12]
|
|
8005456: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800545a: d901 bls.n 8005460 <USB_FlushTxFifo+0x20>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800545c: 2303 movs r3, #3
|
|
800545e: e01b b.n 8005498 <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
8005460: 687b ldr r3, [r7, #4]
|
|
8005462: 691b ldr r3, [r3, #16]
|
|
8005464: 2b00 cmp r3, #0
|
|
8005466: daf2 bge.n 800544e <USB_FlushTxFifo+0xe>
|
|
|
|
/* Flush TX Fifo */
|
|
count = 0U;
|
|
8005468: 2300 movs r3, #0
|
|
800546a: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
|
|
800546c: 683b ldr r3, [r7, #0]
|
|
800546e: 019b lsls r3, r3, #6
|
|
8005470: f043 0220 orr.w r2, r3, #32
|
|
8005474: 687b ldr r3, [r7, #4]
|
|
8005476: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8005478: 68fb ldr r3, [r7, #12]
|
|
800547a: 3301 adds r3, #1
|
|
800547c: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800547e: 68fb ldr r3, [r7, #12]
|
|
8005480: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8005484: d901 bls.n 800548a <USB_FlushTxFifo+0x4a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005486: 2303 movs r3, #3
|
|
8005488: e006 b.n 8005498 <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
|
|
800548a: 687b ldr r3, [r7, #4]
|
|
800548c: 691b ldr r3, [r3, #16]
|
|
800548e: f003 0320 and.w r3, r3, #32
|
|
8005492: 2b20 cmp r3, #32
|
|
8005494: d0f0 beq.n 8005478 <USB_FlushTxFifo+0x38>
|
|
|
|
return HAL_OK;
|
|
8005496: 2300 movs r3, #0
|
|
}
|
|
8005498: 4618 mov r0, r3
|
|
800549a: 3714 adds r7, #20
|
|
800549c: 46bd mov sp, r7
|
|
800549e: f85d 7b04 ldr.w r7, [sp], #4
|
|
80054a2: 4770 bx lr
|
|
|
|
080054a4 <USB_FlushRxFifo>:
|
|
* @brief USB_FlushRxFifo Flush Rx FIFO
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80054a4: b480 push {r7}
|
|
80054a6: b085 sub sp, #20
|
|
80054a8: af00 add r7, sp, #0
|
|
80054aa: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
80054ac: 2300 movs r3, #0
|
|
80054ae: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
80054b0: 68fb ldr r3, [r7, #12]
|
|
80054b2: 3301 adds r3, #1
|
|
80054b4: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80054b6: 68fb ldr r3, [r7, #12]
|
|
80054b8: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80054bc: d901 bls.n 80054c2 <USB_FlushRxFifo+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80054be: 2303 movs r3, #3
|
|
80054c0: e018 b.n 80054f4 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
80054c2: 687b ldr r3, [r7, #4]
|
|
80054c4: 691b ldr r3, [r3, #16]
|
|
80054c6: 2b00 cmp r3, #0
|
|
80054c8: daf2 bge.n 80054b0 <USB_FlushRxFifo+0xc>
|
|
|
|
/* Flush RX Fifo */
|
|
count = 0U;
|
|
80054ca: 2300 movs r3, #0
|
|
80054cc: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
|
|
80054ce: 687b ldr r3, [r7, #4]
|
|
80054d0: 2210 movs r2, #16
|
|
80054d2: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
80054d4: 68fb ldr r3, [r7, #12]
|
|
80054d6: 3301 adds r3, #1
|
|
80054d8: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80054da: 68fb ldr r3, [r7, #12]
|
|
80054dc: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80054e0: d901 bls.n 80054e6 <USB_FlushRxFifo+0x42>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80054e2: 2303 movs r3, #3
|
|
80054e4: e006 b.n 80054f4 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
|
|
80054e6: 687b ldr r3, [r7, #4]
|
|
80054e8: 691b ldr r3, [r3, #16]
|
|
80054ea: f003 0310 and.w r3, r3, #16
|
|
80054ee: 2b10 cmp r3, #16
|
|
80054f0: d0f0 beq.n 80054d4 <USB_FlushRxFifo+0x30>
|
|
|
|
return HAL_OK;
|
|
80054f2: 2300 movs r3, #0
|
|
}
|
|
80054f4: 4618 mov r0, r3
|
|
80054f6: 3714 adds r7, #20
|
|
80054f8: 46bd mov sp, r7
|
|
80054fa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80054fe: 4770 bx lr
|
|
|
|
08005500 <USB_SetDevSpeed>:
|
|
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
|
|
* @arg USB_OTG_SPEED_FULL: Full speed mode
|
|
* @retval Hal status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
|
|
{
|
|
8005500: b480 push {r7}
|
|
8005502: b085 sub sp, #20
|
|
8005504: af00 add r7, sp, #0
|
|
8005506: 6078 str r0, [r7, #4]
|
|
8005508: 460b mov r3, r1
|
|
800550a: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800550c: 687b ldr r3, [r7, #4]
|
|
800550e: 60fb str r3, [r7, #12]
|
|
|
|
USBx_DEVICE->DCFG |= speed;
|
|
8005510: 68fb ldr r3, [r7, #12]
|
|
8005512: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005516: 681a ldr r2, [r3, #0]
|
|
8005518: 78fb ldrb r3, [r7, #3]
|
|
800551a: 68f9 ldr r1, [r7, #12]
|
|
800551c: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8005520: 4313 orrs r3, r2
|
|
8005522: 600b str r3, [r1, #0]
|
|
return HAL_OK;
|
|
8005524: 2300 movs r3, #0
|
|
}
|
|
8005526: 4618 mov r0, r3
|
|
8005528: 3714 adds r7, #20
|
|
800552a: 46bd mov sp, r7
|
|
800552c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005530: 4770 bx lr
|
|
|
|
08005532 <USB_GetDevSpeed>:
|
|
* This parameter can be one of these values:
|
|
* @arg USBD_HS_SPEED: High speed mode
|
|
* @arg USBD_FS_SPEED: Full speed mode
|
|
*/
|
|
uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8005532: b480 push {r7}
|
|
8005534: b087 sub sp, #28
|
|
8005536: af00 add r7, sp, #0
|
|
8005538: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800553a: 687b ldr r3, [r7, #4]
|
|
800553c: 613b str r3, [r7, #16]
|
|
uint8_t speed;
|
|
uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
|
|
800553e: 693b ldr r3, [r7, #16]
|
|
8005540: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005544: 689b ldr r3, [r3, #8]
|
|
8005546: f003 0306 and.w r3, r3, #6
|
|
800554a: 60fb str r3, [r7, #12]
|
|
|
|
if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
|
|
800554c: 68fb ldr r3, [r7, #12]
|
|
800554e: 2b00 cmp r3, #0
|
|
8005550: d102 bne.n 8005558 <USB_GetDevSpeed+0x26>
|
|
{
|
|
speed = USBD_HS_SPEED;
|
|
8005552: 2300 movs r3, #0
|
|
8005554: 75fb strb r3, [r7, #23]
|
|
8005556: e00a b.n 800556e <USB_GetDevSpeed+0x3c>
|
|
}
|
|
else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
|
|
8005558: 68fb ldr r3, [r7, #12]
|
|
800555a: 2b02 cmp r3, #2
|
|
800555c: d002 beq.n 8005564 <USB_GetDevSpeed+0x32>
|
|
800555e: 68fb ldr r3, [r7, #12]
|
|
8005560: 2b06 cmp r3, #6
|
|
8005562: d102 bne.n 800556a <USB_GetDevSpeed+0x38>
|
|
(DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
|
|
{
|
|
speed = USBD_FS_SPEED;
|
|
8005564: 2302 movs r3, #2
|
|
8005566: 75fb strb r3, [r7, #23]
|
|
8005568: e001 b.n 800556e <USB_GetDevSpeed+0x3c>
|
|
}
|
|
else
|
|
{
|
|
speed = 0xFU;
|
|
800556a: 230f movs r3, #15
|
|
800556c: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return speed;
|
|
800556e: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8005570: 4618 mov r0, r3
|
|
8005572: 371c adds r7, #28
|
|
8005574: 46bd mov sp, r7
|
|
8005576: f85d 7b04 ldr.w r7, [sp], #4
|
|
800557a: 4770 bx lr
|
|
|
|
0800557c <USB_ActivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
800557c: b480 push {r7}
|
|
800557e: b085 sub sp, #20
|
|
8005580: af00 add r7, sp, #0
|
|
8005582: 6078 str r0, [r7, #4]
|
|
8005584: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8005586: 687b ldr r3, [r7, #4]
|
|
8005588: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
800558a: 683b ldr r3, [r7, #0]
|
|
800558c: 781b ldrb r3, [r3, #0]
|
|
800558e: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
8005590: 683b ldr r3, [r7, #0]
|
|
8005592: 785b ldrb r3, [r3, #1]
|
|
8005594: 2b01 cmp r3, #1
|
|
8005596: d13a bne.n 800560e <USB_ActivateEndpoint+0x92>
|
|
{
|
|
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
|
|
8005598: 68fb ldr r3, [r7, #12]
|
|
800559a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800559e: 69da ldr r2, [r3, #28]
|
|
80055a0: 683b ldr r3, [r7, #0]
|
|
80055a2: 781b ldrb r3, [r3, #0]
|
|
80055a4: f003 030f and.w r3, r3, #15
|
|
80055a8: 2101 movs r1, #1
|
|
80055aa: fa01 f303 lsl.w r3, r1, r3
|
|
80055ae: b29b uxth r3, r3
|
|
80055b0: 68f9 ldr r1, [r7, #12]
|
|
80055b2: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80055b6: 4313 orrs r3, r2
|
|
80055b8: 61cb str r3, [r1, #28]
|
|
|
|
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
|
|
80055ba: 68bb ldr r3, [r7, #8]
|
|
80055bc: 015a lsls r2, r3, #5
|
|
80055be: 68fb ldr r3, [r7, #12]
|
|
80055c0: 4413 add r3, r2
|
|
80055c2: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80055c6: 681b ldr r3, [r3, #0]
|
|
80055c8: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80055cc: 2b00 cmp r3, #0
|
|
80055ce: d155 bne.n 800567c <USB_ActivateEndpoint+0x100>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
80055d0: 68bb ldr r3, [r7, #8]
|
|
80055d2: 015a lsls r2, r3, #5
|
|
80055d4: 68fb ldr r3, [r7, #12]
|
|
80055d6: 4413 add r3, r2
|
|
80055d8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80055dc: 681a ldr r2, [r3, #0]
|
|
80055de: 683b ldr r3, [r7, #0]
|
|
80055e0: 689b ldr r3, [r3, #8]
|
|
80055e2: f3c3 010a ubfx r1, r3, #0, #11
|
|
((uint32_t)ep->type << 18) | (epnum << 22) |
|
|
80055e6: 683b ldr r3, [r7, #0]
|
|
80055e8: 791b ldrb r3, [r3, #4]
|
|
80055ea: 049b lsls r3, r3, #18
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
80055ec: 4319 orrs r1, r3
|
|
((uint32_t)ep->type << 18) | (epnum << 22) |
|
|
80055ee: 68bb ldr r3, [r7, #8]
|
|
80055f0: 059b lsls r3, r3, #22
|
|
80055f2: 430b orrs r3, r1
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
80055f4: 4313 orrs r3, r2
|
|
80055f6: 68ba ldr r2, [r7, #8]
|
|
80055f8: 0151 lsls r1, r2, #5
|
|
80055fa: 68fa ldr r2, [r7, #12]
|
|
80055fc: 440a add r2, r1
|
|
80055fe: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8005602: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8005606: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800560a: 6013 str r3, [r2, #0]
|
|
800560c: e036 b.n 800567c <USB_ActivateEndpoint+0x100>
|
|
USB_OTG_DIEPCTL_USBAEP;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
|
|
800560e: 68fb ldr r3, [r7, #12]
|
|
8005610: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005614: 69da ldr r2, [r3, #28]
|
|
8005616: 683b ldr r3, [r7, #0]
|
|
8005618: 781b ldrb r3, [r3, #0]
|
|
800561a: f003 030f and.w r3, r3, #15
|
|
800561e: 2101 movs r1, #1
|
|
8005620: fa01 f303 lsl.w r3, r1, r3
|
|
8005624: 041b lsls r3, r3, #16
|
|
8005626: 68f9 ldr r1, [r7, #12]
|
|
8005628: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
800562c: 4313 orrs r3, r2
|
|
800562e: 61cb str r3, [r1, #28]
|
|
|
|
if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
|
|
8005630: 68bb ldr r3, [r7, #8]
|
|
8005632: 015a lsls r2, r3, #5
|
|
8005634: 68fb ldr r3, [r7, #12]
|
|
8005636: 4413 add r3, r2
|
|
8005638: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800563c: 681b ldr r3, [r3, #0]
|
|
800563e: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8005642: 2b00 cmp r3, #0
|
|
8005644: d11a bne.n 800567c <USB_ActivateEndpoint+0x100>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
|
|
8005646: 68bb ldr r3, [r7, #8]
|
|
8005648: 015a lsls r2, r3, #5
|
|
800564a: 68fb ldr r3, [r7, #12]
|
|
800564c: 4413 add r3, r2
|
|
800564e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005652: 681a ldr r2, [r3, #0]
|
|
8005654: 683b ldr r3, [r7, #0]
|
|
8005656: 689b ldr r3, [r3, #8]
|
|
8005658: f3c3 010a ubfx r1, r3, #0, #11
|
|
((uint32_t)ep->type << 18) |
|
|
800565c: 683b ldr r3, [r7, #0]
|
|
800565e: 791b ldrb r3, [r3, #4]
|
|
8005660: 049b lsls r3, r3, #18
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
|
|
8005662: 430b orrs r3, r1
|
|
8005664: 4313 orrs r3, r2
|
|
8005666: 68ba ldr r2, [r7, #8]
|
|
8005668: 0151 lsls r1, r2, #5
|
|
800566a: 68fa ldr r2, [r7, #12]
|
|
800566c: 440a add r2, r1
|
|
800566e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8005672: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8005676: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800567a: 6013 str r3, [r2, #0]
|
|
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DOEPCTL_USBAEP;
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800567c: 2300 movs r3, #0
|
|
}
|
|
800567e: 4618 mov r0, r3
|
|
8005680: 3714 adds r7, #20
|
|
8005682: 46bd mov sp, r7
|
|
8005684: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005688: 4770 bx lr
|
|
...
|
|
|
|
0800568c <USB_DeactivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
800568c: b480 push {r7}
|
|
800568e: b085 sub sp, #20
|
|
8005690: af00 add r7, sp, #0
|
|
8005692: 6078 str r0, [r7, #4]
|
|
8005694: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8005696: 687b ldr r3, [r7, #4]
|
|
8005698: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
800569a: 683b ldr r3, [r7, #0]
|
|
800569c: 781b ldrb r3, [r3, #0]
|
|
800569e: 60bb str r3, [r7, #8]
|
|
|
|
/* Read DEPCTLn register */
|
|
if (ep->is_in == 1U)
|
|
80056a0: 683b ldr r3, [r7, #0]
|
|
80056a2: 785b ldrb r3, [r3, #1]
|
|
80056a4: 2b01 cmp r3, #1
|
|
80056a6: d161 bne.n 800576c <USB_DeactivateEndpoint+0xe0>
|
|
{
|
|
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
80056a8: 68bb ldr r3, [r7, #8]
|
|
80056aa: 015a lsls r2, r3, #5
|
|
80056ac: 68fb ldr r3, [r7, #12]
|
|
80056ae: 4413 add r3, r2
|
|
80056b0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80056b4: 681b ldr r3, [r3, #0]
|
|
80056b6: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80056ba: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80056be: d11f bne.n 8005700 <USB_DeactivateEndpoint+0x74>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
|
|
80056c0: 68bb ldr r3, [r7, #8]
|
|
80056c2: 015a lsls r2, r3, #5
|
|
80056c4: 68fb ldr r3, [r7, #12]
|
|
80056c6: 4413 add r3, r2
|
|
80056c8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80056cc: 681b ldr r3, [r3, #0]
|
|
80056ce: 68ba ldr r2, [r7, #8]
|
|
80056d0: 0151 lsls r1, r2, #5
|
|
80056d2: 68fa ldr r2, [r7, #12]
|
|
80056d4: 440a add r2, r1
|
|
80056d6: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80056da: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
80056de: 6013 str r3, [r2, #0]
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
|
|
80056e0: 68bb ldr r3, [r7, #8]
|
|
80056e2: 015a lsls r2, r3, #5
|
|
80056e4: 68fb ldr r3, [r7, #12]
|
|
80056e6: 4413 add r3, r2
|
|
80056e8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80056ec: 681b ldr r3, [r3, #0]
|
|
80056ee: 68ba ldr r2, [r7, #8]
|
|
80056f0: 0151 lsls r1, r2, #5
|
|
80056f2: 68fa ldr r2, [r7, #12]
|
|
80056f4: 440a add r2, r1
|
|
80056f6: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80056fa: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80056fe: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
|
|
8005700: 68fb ldr r3, [r7, #12]
|
|
8005702: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005706: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8005708: 683b ldr r3, [r7, #0]
|
|
800570a: 781b ldrb r3, [r3, #0]
|
|
800570c: f003 030f and.w r3, r3, #15
|
|
8005710: 2101 movs r1, #1
|
|
8005712: fa01 f303 lsl.w r3, r1, r3
|
|
8005716: b29b uxth r3, r3
|
|
8005718: 43db mvns r3, r3
|
|
800571a: 68f9 ldr r1, [r7, #12]
|
|
800571c: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8005720: 4013 ands r3, r2
|
|
8005722: 63cb str r3, [r1, #60] @ 0x3c
|
|
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
|
|
8005724: 68fb ldr r3, [r7, #12]
|
|
8005726: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800572a: 69da ldr r2, [r3, #28]
|
|
800572c: 683b ldr r3, [r7, #0]
|
|
800572e: 781b ldrb r3, [r3, #0]
|
|
8005730: f003 030f and.w r3, r3, #15
|
|
8005734: 2101 movs r1, #1
|
|
8005736: fa01 f303 lsl.w r3, r1, r3
|
|
800573a: b29b uxth r3, r3
|
|
800573c: 43db mvns r3, r3
|
|
800573e: 68f9 ldr r1, [r7, #12]
|
|
8005740: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8005744: 4013 ands r3, r2
|
|
8005746: 61cb str r3, [r1, #28]
|
|
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
|
|
8005748: 68bb ldr r3, [r7, #8]
|
|
800574a: 015a lsls r2, r3, #5
|
|
800574c: 68fb ldr r3, [r7, #12]
|
|
800574e: 4413 add r3, r2
|
|
8005750: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005754: 681a ldr r2, [r3, #0]
|
|
8005756: 68bb ldr r3, [r7, #8]
|
|
8005758: 0159 lsls r1, r3, #5
|
|
800575a: 68fb ldr r3, [r7, #12]
|
|
800575c: 440b add r3, r1
|
|
800575e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005762: 4619 mov r1, r3
|
|
8005764: 4b35 ldr r3, [pc, #212] @ (800583c <USB_DeactivateEndpoint+0x1b0>)
|
|
8005766: 4013 ands r3, r2
|
|
8005768: 600b str r3, [r1, #0]
|
|
800576a: e060 b.n 800582e <USB_DeactivateEndpoint+0x1a2>
|
|
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DIEPCTL_EPTYP);
|
|
}
|
|
else
|
|
{
|
|
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
800576c: 68bb ldr r3, [r7, #8]
|
|
800576e: 015a lsls r2, r3, #5
|
|
8005770: 68fb ldr r3, [r7, #12]
|
|
8005772: 4413 add r3, r2
|
|
8005774: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005778: 681b ldr r3, [r3, #0]
|
|
800577a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
800577e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8005782: d11f bne.n 80057c4 <USB_DeactivateEndpoint+0x138>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
|
8005784: 68bb ldr r3, [r7, #8]
|
|
8005786: 015a lsls r2, r3, #5
|
|
8005788: 68fb ldr r3, [r7, #12]
|
|
800578a: 4413 add r3, r2
|
|
800578c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005790: 681b ldr r3, [r3, #0]
|
|
8005792: 68ba ldr r2, [r7, #8]
|
|
8005794: 0151 lsls r1, r2, #5
|
|
8005796: 68fa ldr r2, [r7, #12]
|
|
8005798: 440a add r2, r1
|
|
800579a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800579e: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
80057a2: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
|
|
80057a4: 68bb ldr r3, [r7, #8]
|
|
80057a6: 015a lsls r2, r3, #5
|
|
80057a8: 68fb ldr r3, [r7, #12]
|
|
80057aa: 4413 add r3, r2
|
|
80057ac: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80057b0: 681b ldr r3, [r3, #0]
|
|
80057b2: 68ba ldr r2, [r7, #8]
|
|
80057b4: 0151 lsls r1, r2, #5
|
|
80057b6: 68fa ldr r2, [r7, #12]
|
|
80057b8: 440a add r2, r1
|
|
80057ba: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
80057be: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80057c2: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
|
|
80057c4: 68fb ldr r3, [r7, #12]
|
|
80057c6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80057ca: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
80057cc: 683b ldr r3, [r7, #0]
|
|
80057ce: 781b ldrb r3, [r3, #0]
|
|
80057d0: f003 030f and.w r3, r3, #15
|
|
80057d4: 2101 movs r1, #1
|
|
80057d6: fa01 f303 lsl.w r3, r1, r3
|
|
80057da: 041b lsls r3, r3, #16
|
|
80057dc: 43db mvns r3, r3
|
|
80057de: 68f9 ldr r1, [r7, #12]
|
|
80057e0: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80057e4: 4013 ands r3, r2
|
|
80057e6: 63cb str r3, [r1, #60] @ 0x3c
|
|
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
|
|
80057e8: 68fb ldr r3, [r7, #12]
|
|
80057ea: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80057ee: 69da ldr r2, [r3, #28]
|
|
80057f0: 683b ldr r3, [r7, #0]
|
|
80057f2: 781b ldrb r3, [r3, #0]
|
|
80057f4: f003 030f and.w r3, r3, #15
|
|
80057f8: 2101 movs r1, #1
|
|
80057fa: fa01 f303 lsl.w r3, r1, r3
|
|
80057fe: 041b lsls r3, r3, #16
|
|
8005800: 43db mvns r3, r3
|
|
8005802: 68f9 ldr r1, [r7, #12]
|
|
8005804: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8005808: 4013 ands r3, r2
|
|
800580a: 61cb str r3, [r1, #28]
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
|
|
800580c: 68bb ldr r3, [r7, #8]
|
|
800580e: 015a lsls r2, r3, #5
|
|
8005810: 68fb ldr r3, [r7, #12]
|
|
8005812: 4413 add r3, r2
|
|
8005814: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005818: 681a ldr r2, [r3, #0]
|
|
800581a: 68bb ldr r3, [r7, #8]
|
|
800581c: 0159 lsls r1, r3, #5
|
|
800581e: 68fb ldr r3, [r7, #12]
|
|
8005820: 440b add r3, r1
|
|
8005822: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005826: 4619 mov r1, r3
|
|
8005828: 4b05 ldr r3, [pc, #20] @ (8005840 <USB_DeactivateEndpoint+0x1b4>)
|
|
800582a: 4013 ands r3, r2
|
|
800582c: 600b str r3, [r1, #0]
|
|
USB_OTG_DOEPCTL_MPSIZ |
|
|
USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DOEPCTL_EPTYP);
|
|
}
|
|
|
|
return HAL_OK;
|
|
800582e: 2300 movs r3, #0
|
|
}
|
|
8005830: 4618 mov r0, r3
|
|
8005832: 3714 adds r7, #20
|
|
8005834: 46bd mov sp, r7
|
|
8005836: f85d 7b04 ldr.w r7, [sp], #4
|
|
800583a: 4770 bx lr
|
|
800583c: ec337800 .word 0xec337800
|
|
8005840: eff37800 .word 0xeff37800
|
|
|
|
08005844 <USB_EPStartXfer>:
|
|
* 0 : DMA feature not used
|
|
* 1 : DMA feature used
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
|
|
{
|
|
8005844: b580 push {r7, lr}
|
|
8005846: b08a sub sp, #40 @ 0x28
|
|
8005848: af02 add r7, sp, #8
|
|
800584a: 60f8 str r0, [r7, #12]
|
|
800584c: 60b9 str r1, [r7, #8]
|
|
800584e: 4613 mov r3, r2
|
|
8005850: 71fb strb r3, [r7, #7]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8005852: 68fb ldr r3, [r7, #12]
|
|
8005854: 61fb str r3, [r7, #28]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8005856: 68bb ldr r3, [r7, #8]
|
|
8005858: 781b ldrb r3, [r3, #0]
|
|
800585a: 61bb str r3, [r7, #24]
|
|
uint16_t pktcnt;
|
|
|
|
/* IN endpoint */
|
|
if (ep->is_in == 1U)
|
|
800585c: 68bb ldr r3, [r7, #8]
|
|
800585e: 785b ldrb r3, [r3, #1]
|
|
8005860: 2b01 cmp r3, #1
|
|
8005862: f040 817f bne.w 8005b64 <USB_EPStartXfer+0x320>
|
|
{
|
|
/* Zero Length Packet? */
|
|
if (ep->xfer_len == 0U)
|
|
8005866: 68bb ldr r3, [r7, #8]
|
|
8005868: 691b ldr r3, [r3, #16]
|
|
800586a: 2b00 cmp r3, #0
|
|
800586c: d132 bne.n 80058d4 <USB_EPStartXfer+0x90>
|
|
{
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
|
800586e: 69bb ldr r3, [r7, #24]
|
|
8005870: 015a lsls r2, r3, #5
|
|
8005872: 69fb ldr r3, [r7, #28]
|
|
8005874: 4413 add r3, r2
|
|
8005876: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800587a: 691b ldr r3, [r3, #16]
|
|
800587c: 69ba ldr r2, [r7, #24]
|
|
800587e: 0151 lsls r1, r2, #5
|
|
8005880: 69fa ldr r2, [r7, #28]
|
|
8005882: 440a add r2, r1
|
|
8005884: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8005888: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
800588c: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
8005890: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
|
|
8005892: 69bb ldr r3, [r7, #24]
|
|
8005894: 015a lsls r2, r3, #5
|
|
8005896: 69fb ldr r3, [r7, #28]
|
|
8005898: 4413 add r3, r2
|
|
800589a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800589e: 691b ldr r3, [r3, #16]
|
|
80058a0: 69ba ldr r2, [r7, #24]
|
|
80058a2: 0151 lsls r1, r2, #5
|
|
80058a4: 69fa ldr r2, [r7, #28]
|
|
80058a6: 440a add r2, r1
|
|
80058a8: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80058ac: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
80058b0: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
|
80058b2: 69bb ldr r3, [r7, #24]
|
|
80058b4: 015a lsls r2, r3, #5
|
|
80058b6: 69fb ldr r3, [r7, #28]
|
|
80058b8: 4413 add r3, r2
|
|
80058ba: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80058be: 691b ldr r3, [r3, #16]
|
|
80058c0: 69ba ldr r2, [r7, #24]
|
|
80058c2: 0151 lsls r1, r2, #5
|
|
80058c4: 69fa ldr r2, [r7, #28]
|
|
80058c6: 440a add r2, r1
|
|
80058c8: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80058cc: 0cdb lsrs r3, r3, #19
|
|
80058ce: 04db lsls r3, r3, #19
|
|
80058d0: 6113 str r3, [r2, #16]
|
|
80058d2: e097 b.n 8005a04 <USB_EPStartXfer+0x1c0>
|
|
/* Program the transfer size and packet count
|
|
* as follows: xfersize = N * maxpacket +
|
|
* short_packet pktcnt = N + (short_packet
|
|
* exist ? 1 : 0)
|
|
*/
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
|
80058d4: 69bb ldr r3, [r7, #24]
|
|
80058d6: 015a lsls r2, r3, #5
|
|
80058d8: 69fb ldr r3, [r7, #28]
|
|
80058da: 4413 add r3, r2
|
|
80058dc: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80058e0: 691b ldr r3, [r3, #16]
|
|
80058e2: 69ba ldr r2, [r7, #24]
|
|
80058e4: 0151 lsls r1, r2, #5
|
|
80058e6: 69fa ldr r2, [r7, #28]
|
|
80058e8: 440a add r2, r1
|
|
80058ea: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80058ee: 0cdb lsrs r3, r3, #19
|
|
80058f0: 04db lsls r3, r3, #19
|
|
80058f2: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
|
80058f4: 69bb ldr r3, [r7, #24]
|
|
80058f6: 015a lsls r2, r3, #5
|
|
80058f8: 69fb ldr r3, [r7, #28]
|
|
80058fa: 4413 add r3, r2
|
|
80058fc: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005900: 691b ldr r3, [r3, #16]
|
|
8005902: 69ba ldr r2, [r7, #24]
|
|
8005904: 0151 lsls r1, r2, #5
|
|
8005906: 69fa ldr r2, [r7, #28]
|
|
8005908: 440a add r2, r1
|
|
800590a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800590e: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
8005912: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
8005916: 6113 str r3, [r2, #16]
|
|
|
|
if (epnum == 0U)
|
|
8005918: 69bb ldr r3, [r7, #24]
|
|
800591a: 2b00 cmp r3, #0
|
|
800591c: d11a bne.n 8005954 <USB_EPStartXfer+0x110>
|
|
{
|
|
if (ep->xfer_len > ep->maxpacket)
|
|
800591e: 68bb ldr r3, [r7, #8]
|
|
8005920: 691a ldr r2, [r3, #16]
|
|
8005922: 68bb ldr r3, [r7, #8]
|
|
8005924: 689b ldr r3, [r3, #8]
|
|
8005926: 429a cmp r2, r3
|
|
8005928: d903 bls.n 8005932 <USB_EPStartXfer+0xee>
|
|
{
|
|
ep->xfer_len = ep->maxpacket;
|
|
800592a: 68bb ldr r3, [r7, #8]
|
|
800592c: 689a ldr r2, [r3, #8]
|
|
800592e: 68bb ldr r3, [r7, #8]
|
|
8005930: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
|
|
8005932: 69bb ldr r3, [r7, #24]
|
|
8005934: 015a lsls r2, r3, #5
|
|
8005936: 69fb ldr r3, [r7, #28]
|
|
8005938: 4413 add r3, r2
|
|
800593a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800593e: 691b ldr r3, [r3, #16]
|
|
8005940: 69ba ldr r2, [r7, #24]
|
|
8005942: 0151 lsls r1, r2, #5
|
|
8005944: 69fa ldr r2, [r7, #28]
|
|
8005946: 440a add r2, r1
|
|
8005948: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800594c: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8005950: 6113 str r3, [r2, #16]
|
|
8005952: e044 b.n 80059de <USB_EPStartXfer+0x19a>
|
|
}
|
|
else
|
|
{
|
|
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
|
|
8005954: 68bb ldr r3, [r7, #8]
|
|
8005956: 691a ldr r2, [r3, #16]
|
|
8005958: 68bb ldr r3, [r7, #8]
|
|
800595a: 689b ldr r3, [r3, #8]
|
|
800595c: 4413 add r3, r2
|
|
800595e: 1e5a subs r2, r3, #1
|
|
8005960: 68bb ldr r3, [r7, #8]
|
|
8005962: 689b ldr r3, [r3, #8]
|
|
8005964: fbb2 f3f3 udiv r3, r2, r3
|
|
8005968: 82fb strh r3, [r7, #22]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19));
|
|
800596a: 69bb ldr r3, [r7, #24]
|
|
800596c: 015a lsls r2, r3, #5
|
|
800596e: 69fb ldr r3, [r7, #28]
|
|
8005970: 4413 add r3, r2
|
|
8005972: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005976: 691a ldr r2, [r3, #16]
|
|
8005978: 8afb ldrh r3, [r7, #22]
|
|
800597a: 04d9 lsls r1, r3, #19
|
|
800597c: 4ba4 ldr r3, [pc, #656] @ (8005c10 <USB_EPStartXfer+0x3cc>)
|
|
800597e: 400b ands r3, r1
|
|
8005980: 69b9 ldr r1, [r7, #24]
|
|
8005982: 0148 lsls r0, r1, #5
|
|
8005984: 69f9 ldr r1, [r7, #28]
|
|
8005986: 4401 add r1, r0
|
|
8005988: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
800598c: 4313 orrs r3, r2
|
|
800598e: 610b str r3, [r1, #16]
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
8005990: 68bb ldr r3, [r7, #8]
|
|
8005992: 791b ldrb r3, [r3, #4]
|
|
8005994: 2b01 cmp r3, #1
|
|
8005996: d122 bne.n 80059de <USB_EPStartXfer+0x19a>
|
|
{
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
|
|
8005998: 69bb ldr r3, [r7, #24]
|
|
800599a: 015a lsls r2, r3, #5
|
|
800599c: 69fb ldr r3, [r7, #28]
|
|
800599e: 4413 add r3, r2
|
|
80059a0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80059a4: 691b ldr r3, [r3, #16]
|
|
80059a6: 69ba ldr r2, [r7, #24]
|
|
80059a8: 0151 lsls r1, r2, #5
|
|
80059aa: 69fa ldr r2, [r7, #28]
|
|
80059ac: 440a add r2, r1
|
|
80059ae: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80059b2: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000
|
|
80059b6: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29));
|
|
80059b8: 69bb ldr r3, [r7, #24]
|
|
80059ba: 015a lsls r2, r3, #5
|
|
80059bc: 69fb ldr r3, [r7, #28]
|
|
80059be: 4413 add r3, r2
|
|
80059c0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80059c4: 691a ldr r2, [r3, #16]
|
|
80059c6: 8afb ldrh r3, [r7, #22]
|
|
80059c8: 075b lsls r3, r3, #29
|
|
80059ca: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000
|
|
80059ce: 69b9 ldr r1, [r7, #24]
|
|
80059d0: 0148 lsls r0, r1, #5
|
|
80059d2: 69f9 ldr r1, [r7, #28]
|
|
80059d4: 4401 add r1, r0
|
|
80059d6: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
80059da: 4313 orrs r3, r2
|
|
80059dc: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
|
|
80059de: 69bb ldr r3, [r7, #24]
|
|
80059e0: 015a lsls r2, r3, #5
|
|
80059e2: 69fb ldr r3, [r7, #28]
|
|
80059e4: 4413 add r3, r2
|
|
80059e6: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80059ea: 691a ldr r2, [r3, #16]
|
|
80059ec: 68bb ldr r3, [r7, #8]
|
|
80059ee: 691b ldr r3, [r3, #16]
|
|
80059f0: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80059f4: 69b9 ldr r1, [r7, #24]
|
|
80059f6: 0148 lsls r0, r1, #5
|
|
80059f8: 69f9 ldr r1, [r7, #28]
|
|
80059fa: 4401 add r1, r0
|
|
80059fc: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
8005a00: 4313 orrs r3, r2
|
|
8005a02: 610b str r3, [r1, #16]
|
|
}
|
|
|
|
if (dma == 1U)
|
|
8005a04: 79fb ldrb r3, [r7, #7]
|
|
8005a06: 2b01 cmp r3, #1
|
|
8005a08: d14b bne.n 8005aa2 <USB_EPStartXfer+0x25e>
|
|
{
|
|
if ((uint32_t)ep->dma_addr != 0U)
|
|
8005a0a: 68bb ldr r3, [r7, #8]
|
|
8005a0c: 69db ldr r3, [r3, #28]
|
|
8005a0e: 2b00 cmp r3, #0
|
|
8005a10: d009 beq.n 8005a26 <USB_EPStartXfer+0x1e2>
|
|
{
|
|
USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
|
|
8005a12: 69bb ldr r3, [r7, #24]
|
|
8005a14: 015a lsls r2, r3, #5
|
|
8005a16: 69fb ldr r3, [r7, #28]
|
|
8005a18: 4413 add r3, r2
|
|
8005a1a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005a1e: 461a mov r2, r3
|
|
8005a20: 68bb ldr r3, [r7, #8]
|
|
8005a22: 69db ldr r3, [r3, #28]
|
|
8005a24: 6153 str r3, [r2, #20]
|
|
}
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
8005a26: 68bb ldr r3, [r7, #8]
|
|
8005a28: 791b ldrb r3, [r3, #4]
|
|
8005a2a: 2b01 cmp r3, #1
|
|
8005a2c: d128 bne.n 8005a80 <USB_EPStartXfer+0x23c>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
8005a2e: 69fb ldr r3, [r7, #28]
|
|
8005a30: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005a34: 689b ldr r3, [r3, #8]
|
|
8005a36: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005a3a: 2b00 cmp r3, #0
|
|
8005a3c: d110 bne.n 8005a60 <USB_EPStartXfer+0x21c>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
|
|
8005a3e: 69bb ldr r3, [r7, #24]
|
|
8005a40: 015a lsls r2, r3, #5
|
|
8005a42: 69fb ldr r3, [r7, #28]
|
|
8005a44: 4413 add r3, r2
|
|
8005a46: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005a4a: 681b ldr r3, [r3, #0]
|
|
8005a4c: 69ba ldr r2, [r7, #24]
|
|
8005a4e: 0151 lsls r1, r2, #5
|
|
8005a50: 69fa ldr r2, [r7, #28]
|
|
8005a52: 440a add r2, r1
|
|
8005a54: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8005a58: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8005a5c: 6013 str r3, [r2, #0]
|
|
8005a5e: e00f b.n 8005a80 <USB_EPStartXfer+0x23c>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
|
8005a60: 69bb ldr r3, [r7, #24]
|
|
8005a62: 015a lsls r2, r3, #5
|
|
8005a64: 69fb ldr r3, [r7, #28]
|
|
8005a66: 4413 add r3, r2
|
|
8005a68: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005a6c: 681b ldr r3, [r3, #0]
|
|
8005a6e: 69ba ldr r2, [r7, #24]
|
|
8005a70: 0151 lsls r1, r2, #5
|
|
8005a72: 69fa ldr r2, [r7, #28]
|
|
8005a74: 440a add r2, r1
|
|
8005a76: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8005a7a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8005a7e: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
/* EP enable, IN data in FIFO */
|
|
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
|
8005a80: 69bb ldr r3, [r7, #24]
|
|
8005a82: 015a lsls r2, r3, #5
|
|
8005a84: 69fb ldr r3, [r7, #28]
|
|
8005a86: 4413 add r3, r2
|
|
8005a88: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005a8c: 681b ldr r3, [r3, #0]
|
|
8005a8e: 69ba ldr r2, [r7, #24]
|
|
8005a90: 0151 lsls r1, r2, #5
|
|
8005a92: 69fa ldr r2, [r7, #28]
|
|
8005a94: 440a add r2, r1
|
|
8005a96: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8005a9a: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
8005a9e: 6013 str r3, [r2, #0]
|
|
8005aa0: e166 b.n 8005d70 <USB_EPStartXfer+0x52c>
|
|
}
|
|
else
|
|
{
|
|
/* EP enable, IN data in FIFO */
|
|
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
|
8005aa2: 69bb ldr r3, [r7, #24]
|
|
8005aa4: 015a lsls r2, r3, #5
|
|
8005aa6: 69fb ldr r3, [r7, #28]
|
|
8005aa8: 4413 add r3, r2
|
|
8005aaa: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005aae: 681b ldr r3, [r3, #0]
|
|
8005ab0: 69ba ldr r2, [r7, #24]
|
|
8005ab2: 0151 lsls r1, r2, #5
|
|
8005ab4: 69fa ldr r2, [r7, #28]
|
|
8005ab6: 440a add r2, r1
|
|
8005ab8: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8005abc: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
8005ac0: 6013 str r3, [r2, #0]
|
|
|
|
if (ep->type != EP_TYPE_ISOC)
|
|
8005ac2: 68bb ldr r3, [r7, #8]
|
|
8005ac4: 791b ldrb r3, [r3, #4]
|
|
8005ac6: 2b01 cmp r3, #1
|
|
8005ac8: d015 beq.n 8005af6 <USB_EPStartXfer+0x2b2>
|
|
{
|
|
/* Enable the Tx FIFO Empty Interrupt for this EP */
|
|
if (ep->xfer_len > 0U)
|
|
8005aca: 68bb ldr r3, [r7, #8]
|
|
8005acc: 691b ldr r3, [r3, #16]
|
|
8005ace: 2b00 cmp r3, #0
|
|
8005ad0: f000 814e beq.w 8005d70 <USB_EPStartXfer+0x52c>
|
|
{
|
|
USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
|
|
8005ad4: 69fb ldr r3, [r7, #28]
|
|
8005ad6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005ada: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8005adc: 68bb ldr r3, [r7, #8]
|
|
8005ade: 781b ldrb r3, [r3, #0]
|
|
8005ae0: f003 030f and.w r3, r3, #15
|
|
8005ae4: 2101 movs r1, #1
|
|
8005ae6: fa01 f303 lsl.w r3, r1, r3
|
|
8005aea: 69f9 ldr r1, [r7, #28]
|
|
8005aec: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8005af0: 4313 orrs r3, r2
|
|
8005af2: 634b str r3, [r1, #52] @ 0x34
|
|
8005af4: e13c b.n 8005d70 <USB_EPStartXfer+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
8005af6: 69fb ldr r3, [r7, #28]
|
|
8005af8: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005afc: 689b ldr r3, [r3, #8]
|
|
8005afe: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005b02: 2b00 cmp r3, #0
|
|
8005b04: d110 bne.n 8005b28 <USB_EPStartXfer+0x2e4>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
|
|
8005b06: 69bb ldr r3, [r7, #24]
|
|
8005b08: 015a lsls r2, r3, #5
|
|
8005b0a: 69fb ldr r3, [r7, #28]
|
|
8005b0c: 4413 add r3, r2
|
|
8005b0e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005b12: 681b ldr r3, [r3, #0]
|
|
8005b14: 69ba ldr r2, [r7, #24]
|
|
8005b16: 0151 lsls r1, r2, #5
|
|
8005b18: 69fa ldr r2, [r7, #28]
|
|
8005b1a: 440a add r2, r1
|
|
8005b1c: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8005b20: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8005b24: 6013 str r3, [r2, #0]
|
|
8005b26: e00f b.n 8005b48 <USB_EPStartXfer+0x304>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
|
8005b28: 69bb ldr r3, [r7, #24]
|
|
8005b2a: 015a lsls r2, r3, #5
|
|
8005b2c: 69fb ldr r3, [r7, #28]
|
|
8005b2e: 4413 add r3, r2
|
|
8005b30: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005b34: 681b ldr r3, [r3, #0]
|
|
8005b36: 69ba ldr r2, [r7, #24]
|
|
8005b38: 0151 lsls r1, r2, #5
|
|
8005b3a: 69fa ldr r2, [r7, #28]
|
|
8005b3c: 440a add r2, r1
|
|
8005b3e: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8005b42: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8005b46: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
|
|
8005b48: 68bb ldr r3, [r7, #8]
|
|
8005b4a: 68d9 ldr r1, [r3, #12]
|
|
8005b4c: 68bb ldr r3, [r7, #8]
|
|
8005b4e: 781a ldrb r2, [r3, #0]
|
|
8005b50: 68bb ldr r3, [r7, #8]
|
|
8005b52: 691b ldr r3, [r3, #16]
|
|
8005b54: b298 uxth r0, r3
|
|
8005b56: 79fb ldrb r3, [r7, #7]
|
|
8005b58: 9300 str r3, [sp, #0]
|
|
8005b5a: 4603 mov r3, r0
|
|
8005b5c: 68f8 ldr r0, [r7, #12]
|
|
8005b5e: f000 f9b9 bl 8005ed4 <USB_WritePacket>
|
|
8005b62: e105 b.n 8005d70 <USB_EPStartXfer+0x52c>
|
|
{
|
|
/* Program the transfer size and packet count as follows:
|
|
* pktcnt = N
|
|
* xfersize = N * maxpacket
|
|
*/
|
|
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
|
|
8005b64: 69bb ldr r3, [r7, #24]
|
|
8005b66: 015a lsls r2, r3, #5
|
|
8005b68: 69fb ldr r3, [r7, #28]
|
|
8005b6a: 4413 add r3, r2
|
|
8005b6c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005b70: 691b ldr r3, [r3, #16]
|
|
8005b72: 69ba ldr r2, [r7, #24]
|
|
8005b74: 0151 lsls r1, r2, #5
|
|
8005b76: 69fa ldr r2, [r7, #28]
|
|
8005b78: 440a add r2, r1
|
|
8005b7a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8005b7e: 0cdb lsrs r3, r3, #19
|
|
8005b80: 04db lsls r3, r3, #19
|
|
8005b82: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
|
|
8005b84: 69bb ldr r3, [r7, #24]
|
|
8005b86: 015a lsls r2, r3, #5
|
|
8005b88: 69fb ldr r3, [r7, #28]
|
|
8005b8a: 4413 add r3, r2
|
|
8005b8c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005b90: 691b ldr r3, [r3, #16]
|
|
8005b92: 69ba ldr r2, [r7, #24]
|
|
8005b94: 0151 lsls r1, r2, #5
|
|
8005b96: 69fa ldr r2, [r7, #28]
|
|
8005b98: 440a add r2, r1
|
|
8005b9a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8005b9e: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
8005ba2: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
8005ba6: 6113 str r3, [r2, #16]
|
|
|
|
if (epnum == 0U)
|
|
8005ba8: 69bb ldr r3, [r7, #24]
|
|
8005baa: 2b00 cmp r3, #0
|
|
8005bac: d132 bne.n 8005c14 <USB_EPStartXfer+0x3d0>
|
|
{
|
|
if (ep->xfer_len > 0U)
|
|
8005bae: 68bb ldr r3, [r7, #8]
|
|
8005bb0: 691b ldr r3, [r3, #16]
|
|
8005bb2: 2b00 cmp r3, #0
|
|
8005bb4: d003 beq.n 8005bbe <USB_EPStartXfer+0x37a>
|
|
{
|
|
ep->xfer_len = ep->maxpacket;
|
|
8005bb6: 68bb ldr r3, [r7, #8]
|
|
8005bb8: 689a ldr r2, [r3, #8]
|
|
8005bba: 68bb ldr r3, [r7, #8]
|
|
8005bbc: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
/* Store transfer size, for EP0 this is equal to endpoint max packet size */
|
|
ep->xfer_size = ep->maxpacket;
|
|
8005bbe: 68bb ldr r3, [r7, #8]
|
|
8005bc0: 689a ldr r2, [r3, #8]
|
|
8005bc2: 68bb ldr r3, [r7, #8]
|
|
8005bc4: 621a str r2, [r3, #32]
|
|
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
|
|
8005bc6: 69bb ldr r3, [r7, #24]
|
|
8005bc8: 015a lsls r2, r3, #5
|
|
8005bca: 69fb ldr r3, [r7, #28]
|
|
8005bcc: 4413 add r3, r2
|
|
8005bce: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005bd2: 691a ldr r2, [r3, #16]
|
|
8005bd4: 68bb ldr r3, [r7, #8]
|
|
8005bd6: 6a1b ldr r3, [r3, #32]
|
|
8005bd8: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005bdc: 69b9 ldr r1, [r7, #24]
|
|
8005bde: 0148 lsls r0, r1, #5
|
|
8005be0: 69f9 ldr r1, [r7, #28]
|
|
8005be2: 4401 add r1, r0
|
|
8005be4: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
8005be8: 4313 orrs r3, r2
|
|
8005bea: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
8005bec: 69bb ldr r3, [r7, #24]
|
|
8005bee: 015a lsls r2, r3, #5
|
|
8005bf0: 69fb ldr r3, [r7, #28]
|
|
8005bf2: 4413 add r3, r2
|
|
8005bf4: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005bf8: 691b ldr r3, [r3, #16]
|
|
8005bfa: 69ba ldr r2, [r7, #24]
|
|
8005bfc: 0151 lsls r1, r2, #5
|
|
8005bfe: 69fa ldr r2, [r7, #28]
|
|
8005c00: 440a add r2, r1
|
|
8005c02: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8005c06: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8005c0a: 6113 str r3, [r2, #16]
|
|
8005c0c: e062 b.n 8005cd4 <USB_EPStartXfer+0x490>
|
|
8005c0e: bf00 nop
|
|
8005c10: 1ff80000 .word 0x1ff80000
|
|
}
|
|
else
|
|
{
|
|
if (ep->xfer_len == 0U)
|
|
8005c14: 68bb ldr r3, [r7, #8]
|
|
8005c16: 691b ldr r3, [r3, #16]
|
|
8005c18: 2b00 cmp r3, #0
|
|
8005c1a: d123 bne.n 8005c64 <USB_EPStartXfer+0x420>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
|
|
8005c1c: 69bb ldr r3, [r7, #24]
|
|
8005c1e: 015a lsls r2, r3, #5
|
|
8005c20: 69fb ldr r3, [r7, #28]
|
|
8005c22: 4413 add r3, r2
|
|
8005c24: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005c28: 691a ldr r2, [r3, #16]
|
|
8005c2a: 68bb ldr r3, [r7, #8]
|
|
8005c2c: 689b ldr r3, [r3, #8]
|
|
8005c2e: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005c32: 69b9 ldr r1, [r7, #24]
|
|
8005c34: 0148 lsls r0, r1, #5
|
|
8005c36: 69f9 ldr r1, [r7, #28]
|
|
8005c38: 4401 add r1, r0
|
|
8005c3a: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
8005c3e: 4313 orrs r3, r2
|
|
8005c40: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
8005c42: 69bb ldr r3, [r7, #24]
|
|
8005c44: 015a lsls r2, r3, #5
|
|
8005c46: 69fb ldr r3, [r7, #28]
|
|
8005c48: 4413 add r3, r2
|
|
8005c4a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005c4e: 691b ldr r3, [r3, #16]
|
|
8005c50: 69ba ldr r2, [r7, #24]
|
|
8005c52: 0151 lsls r1, r2, #5
|
|
8005c54: 69fa ldr r2, [r7, #28]
|
|
8005c56: 440a add r2, r1
|
|
8005c58: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8005c5c: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8005c60: 6113 str r3, [r2, #16]
|
|
8005c62: e037 b.n 8005cd4 <USB_EPStartXfer+0x490>
|
|
}
|
|
else
|
|
{
|
|
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
|
|
8005c64: 68bb ldr r3, [r7, #8]
|
|
8005c66: 691a ldr r2, [r3, #16]
|
|
8005c68: 68bb ldr r3, [r7, #8]
|
|
8005c6a: 689b ldr r3, [r3, #8]
|
|
8005c6c: 4413 add r3, r2
|
|
8005c6e: 1e5a subs r2, r3, #1
|
|
8005c70: 68bb ldr r3, [r7, #8]
|
|
8005c72: 689b ldr r3, [r3, #8]
|
|
8005c74: fbb2 f3f3 udiv r3, r2, r3
|
|
8005c78: 82fb strh r3, [r7, #22]
|
|
ep->xfer_size = ep->maxpacket * pktcnt;
|
|
8005c7a: 68bb ldr r3, [r7, #8]
|
|
8005c7c: 689b ldr r3, [r3, #8]
|
|
8005c7e: 8afa ldrh r2, [r7, #22]
|
|
8005c80: fb03 f202 mul.w r2, r3, r2
|
|
8005c84: 68bb ldr r3, [r7, #8]
|
|
8005c86: 621a str r2, [r3, #32]
|
|
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
|
|
8005c88: 69bb ldr r3, [r7, #24]
|
|
8005c8a: 015a lsls r2, r3, #5
|
|
8005c8c: 69fb ldr r3, [r7, #28]
|
|
8005c8e: 4413 add r3, r2
|
|
8005c90: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005c94: 691a ldr r2, [r3, #16]
|
|
8005c96: 8afb ldrh r3, [r7, #22]
|
|
8005c98: 04d9 lsls r1, r3, #19
|
|
8005c9a: 4b38 ldr r3, [pc, #224] @ (8005d7c <USB_EPStartXfer+0x538>)
|
|
8005c9c: 400b ands r3, r1
|
|
8005c9e: 69b9 ldr r1, [r7, #24]
|
|
8005ca0: 0148 lsls r0, r1, #5
|
|
8005ca2: 69f9 ldr r1, [r7, #28]
|
|
8005ca4: 4401 add r1, r0
|
|
8005ca6: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
8005caa: 4313 orrs r3, r2
|
|
8005cac: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size;
|
|
8005cae: 69bb ldr r3, [r7, #24]
|
|
8005cb0: 015a lsls r2, r3, #5
|
|
8005cb2: 69fb ldr r3, [r7, #28]
|
|
8005cb4: 4413 add r3, r2
|
|
8005cb6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005cba: 691a ldr r2, [r3, #16]
|
|
8005cbc: 68bb ldr r3, [r7, #8]
|
|
8005cbe: 6a1b ldr r3, [r3, #32]
|
|
8005cc0: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005cc4: 69b9 ldr r1, [r7, #24]
|
|
8005cc6: 0148 lsls r0, r1, #5
|
|
8005cc8: 69f9 ldr r1, [r7, #28]
|
|
8005cca: 4401 add r1, r0
|
|
8005ccc: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
8005cd0: 4313 orrs r3, r2
|
|
8005cd2: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
if (dma == 1U)
|
|
8005cd4: 79fb ldrb r3, [r7, #7]
|
|
8005cd6: 2b01 cmp r3, #1
|
|
8005cd8: d10d bne.n 8005cf6 <USB_EPStartXfer+0x4b2>
|
|
{
|
|
if ((uint32_t)ep->xfer_buff != 0U)
|
|
8005cda: 68bb ldr r3, [r7, #8]
|
|
8005cdc: 68db ldr r3, [r3, #12]
|
|
8005cde: 2b00 cmp r3, #0
|
|
8005ce0: d009 beq.n 8005cf6 <USB_EPStartXfer+0x4b2>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
|
|
8005ce2: 68bb ldr r3, [r7, #8]
|
|
8005ce4: 68d9 ldr r1, [r3, #12]
|
|
8005ce6: 69bb ldr r3, [r7, #24]
|
|
8005ce8: 015a lsls r2, r3, #5
|
|
8005cea: 69fb ldr r3, [r7, #28]
|
|
8005cec: 4413 add r3, r2
|
|
8005cee: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005cf2: 460a mov r2, r1
|
|
8005cf4: 615a str r2, [r3, #20]
|
|
}
|
|
}
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
8005cf6: 68bb ldr r3, [r7, #8]
|
|
8005cf8: 791b ldrb r3, [r3, #4]
|
|
8005cfa: 2b01 cmp r3, #1
|
|
8005cfc: d128 bne.n 8005d50 <USB_EPStartXfer+0x50c>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
8005cfe: 69fb ldr r3, [r7, #28]
|
|
8005d00: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8005d04: 689b ldr r3, [r3, #8]
|
|
8005d06: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005d0a: 2b00 cmp r3, #0
|
|
8005d0c: d110 bne.n 8005d30 <USB_EPStartXfer+0x4ec>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
|
|
8005d0e: 69bb ldr r3, [r7, #24]
|
|
8005d10: 015a lsls r2, r3, #5
|
|
8005d12: 69fb ldr r3, [r7, #28]
|
|
8005d14: 4413 add r3, r2
|
|
8005d16: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005d1a: 681b ldr r3, [r3, #0]
|
|
8005d1c: 69ba ldr r2, [r7, #24]
|
|
8005d1e: 0151 lsls r1, r2, #5
|
|
8005d20: 69fa ldr r2, [r7, #28]
|
|
8005d22: 440a add r2, r1
|
|
8005d24: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8005d28: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8005d2c: 6013 str r3, [r2, #0]
|
|
8005d2e: e00f b.n 8005d50 <USB_EPStartXfer+0x50c>
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
|
|
8005d30: 69bb ldr r3, [r7, #24]
|
|
8005d32: 015a lsls r2, r3, #5
|
|
8005d34: 69fb ldr r3, [r7, #28]
|
|
8005d36: 4413 add r3, r2
|
|
8005d38: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005d3c: 681b ldr r3, [r3, #0]
|
|
8005d3e: 69ba ldr r2, [r7, #24]
|
|
8005d40: 0151 lsls r1, r2, #5
|
|
8005d42: 69fa ldr r2, [r7, #28]
|
|
8005d44: 440a add r2, r1
|
|
8005d46: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8005d4a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8005d4e: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
/* EP enable */
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
|
|
8005d50: 69bb ldr r3, [r7, #24]
|
|
8005d52: 015a lsls r2, r3, #5
|
|
8005d54: 69fb ldr r3, [r7, #28]
|
|
8005d56: 4413 add r3, r2
|
|
8005d58: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005d5c: 681b ldr r3, [r3, #0]
|
|
8005d5e: 69ba ldr r2, [r7, #24]
|
|
8005d60: 0151 lsls r1, r2, #5
|
|
8005d62: 69fa ldr r2, [r7, #28]
|
|
8005d64: 440a add r2, r1
|
|
8005d66: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8005d6a: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
8005d6e: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8005d70: 2300 movs r3, #0
|
|
}
|
|
8005d72: 4618 mov r0, r3
|
|
8005d74: 3720 adds r7, #32
|
|
8005d76: 46bd mov sp, r7
|
|
8005d78: bd80 pop {r7, pc}
|
|
8005d7a: bf00 nop
|
|
8005d7c: 1ff80000 .word 0x1ff80000
|
|
|
|
08005d80 <USB_EPStopXfer>:
|
|
* @param USBx usb device instance
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8005d80: b480 push {r7}
|
|
8005d82: b087 sub sp, #28
|
|
8005d84: af00 add r7, sp, #0
|
|
8005d86: 6078 str r0, [r7, #4]
|
|
8005d88: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
8005d8a: 2300 movs r3, #0
|
|
8005d8c: 60fb str r3, [r7, #12]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8005d8e: 2300 movs r3, #0
|
|
8005d90: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8005d92: 687b ldr r3, [r7, #4]
|
|
8005d94: 613b str r3, [r7, #16]
|
|
|
|
/* IN endpoint */
|
|
if (ep->is_in == 1U)
|
|
8005d96: 683b ldr r3, [r7, #0]
|
|
8005d98: 785b ldrb r3, [r3, #1]
|
|
8005d9a: 2b01 cmp r3, #1
|
|
8005d9c: d14a bne.n 8005e34 <USB_EPStopXfer+0xb4>
|
|
{
|
|
/* EP enable, IN data in FIFO */
|
|
if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
8005d9e: 683b ldr r3, [r7, #0]
|
|
8005da0: 781b ldrb r3, [r3, #0]
|
|
8005da2: 015a lsls r2, r3, #5
|
|
8005da4: 693b ldr r3, [r7, #16]
|
|
8005da6: 4413 add r3, r2
|
|
8005da8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005dac: 681b ldr r3, [r3, #0]
|
|
8005dae: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8005db2: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8005db6: f040 8086 bne.w 8005ec6 <USB_EPStopXfer+0x146>
|
|
{
|
|
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
|
|
8005dba: 683b ldr r3, [r7, #0]
|
|
8005dbc: 781b ldrb r3, [r3, #0]
|
|
8005dbe: 015a lsls r2, r3, #5
|
|
8005dc0: 693b ldr r3, [r7, #16]
|
|
8005dc2: 4413 add r3, r2
|
|
8005dc4: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005dc8: 681b ldr r3, [r3, #0]
|
|
8005dca: 683a ldr r2, [r7, #0]
|
|
8005dcc: 7812 ldrb r2, [r2, #0]
|
|
8005dce: 0151 lsls r1, r2, #5
|
|
8005dd0: 693a ldr r2, [r7, #16]
|
|
8005dd2: 440a add r2, r1
|
|
8005dd4: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8005dd8: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8005ddc: 6013 str r3, [r2, #0]
|
|
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
|
|
8005dde: 683b ldr r3, [r7, #0]
|
|
8005de0: 781b ldrb r3, [r3, #0]
|
|
8005de2: 015a lsls r2, r3, #5
|
|
8005de4: 693b ldr r3, [r7, #16]
|
|
8005de6: 4413 add r3, r2
|
|
8005de8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005dec: 681b ldr r3, [r3, #0]
|
|
8005dee: 683a ldr r2, [r7, #0]
|
|
8005df0: 7812 ldrb r2, [r2, #0]
|
|
8005df2: 0151 lsls r1, r2, #5
|
|
8005df4: 693a ldr r2, [r7, #16]
|
|
8005df6: 440a add r2, r1
|
|
8005df8: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8005dfc: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8005e00: 6013 str r3, [r2, #0]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8005e02: 68fb ldr r3, [r7, #12]
|
|
8005e04: 3301 adds r3, #1
|
|
8005e06: 60fb str r3, [r7, #12]
|
|
|
|
if (count > 10000U)
|
|
8005e08: 68fb ldr r3, [r7, #12]
|
|
8005e0a: f242 7210 movw r2, #10000 @ 0x2710
|
|
8005e0e: 4293 cmp r3, r2
|
|
8005e10: d902 bls.n 8005e18 <USB_EPStopXfer+0x98>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005e12: 2301 movs r3, #1
|
|
8005e14: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8005e16: e056 b.n 8005ec6 <USB_EPStopXfer+0x146>
|
|
}
|
|
} while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA);
|
|
8005e18: 683b ldr r3, [r7, #0]
|
|
8005e1a: 781b ldrb r3, [r3, #0]
|
|
8005e1c: 015a lsls r2, r3, #5
|
|
8005e1e: 693b ldr r3, [r7, #16]
|
|
8005e20: 4413 add r3, r2
|
|
8005e22: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8005e26: 681b ldr r3, [r3, #0]
|
|
8005e28: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8005e2c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8005e30: d0e7 beq.n 8005e02 <USB_EPStopXfer+0x82>
|
|
8005e32: e048 b.n 8005ec6 <USB_EPStopXfer+0x146>
|
|
}
|
|
}
|
|
else /* OUT endpoint */
|
|
{
|
|
if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
8005e34: 683b ldr r3, [r7, #0]
|
|
8005e36: 781b ldrb r3, [r3, #0]
|
|
8005e38: 015a lsls r2, r3, #5
|
|
8005e3a: 693b ldr r3, [r7, #16]
|
|
8005e3c: 4413 add r3, r2
|
|
8005e3e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005e42: 681b ldr r3, [r3, #0]
|
|
8005e44: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8005e48: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8005e4c: d13b bne.n 8005ec6 <USB_EPStopXfer+0x146>
|
|
{
|
|
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
|
|
8005e4e: 683b ldr r3, [r7, #0]
|
|
8005e50: 781b ldrb r3, [r3, #0]
|
|
8005e52: 015a lsls r2, r3, #5
|
|
8005e54: 693b ldr r3, [r7, #16]
|
|
8005e56: 4413 add r3, r2
|
|
8005e58: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005e5c: 681b ldr r3, [r3, #0]
|
|
8005e5e: 683a ldr r2, [r7, #0]
|
|
8005e60: 7812 ldrb r2, [r2, #0]
|
|
8005e62: 0151 lsls r1, r2, #5
|
|
8005e64: 693a ldr r2, [r7, #16]
|
|
8005e66: 440a add r2, r1
|
|
8005e68: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8005e6c: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8005e70: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
|
|
8005e72: 683b ldr r3, [r7, #0]
|
|
8005e74: 781b ldrb r3, [r3, #0]
|
|
8005e76: 015a lsls r2, r3, #5
|
|
8005e78: 693b ldr r3, [r7, #16]
|
|
8005e7a: 4413 add r3, r2
|
|
8005e7c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005e80: 681b ldr r3, [r3, #0]
|
|
8005e82: 683a ldr r2, [r7, #0]
|
|
8005e84: 7812 ldrb r2, [r2, #0]
|
|
8005e86: 0151 lsls r1, r2, #5
|
|
8005e88: 693a ldr r2, [r7, #16]
|
|
8005e8a: 440a add r2, r1
|
|
8005e8c: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8005e90: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8005e94: 6013 str r3, [r2, #0]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8005e96: 68fb ldr r3, [r7, #12]
|
|
8005e98: 3301 adds r3, #1
|
|
8005e9a: 60fb str r3, [r7, #12]
|
|
|
|
if (count > 10000U)
|
|
8005e9c: 68fb ldr r3, [r7, #12]
|
|
8005e9e: f242 7210 movw r2, #10000 @ 0x2710
|
|
8005ea2: 4293 cmp r3, r2
|
|
8005ea4: d902 bls.n 8005eac <USB_EPStopXfer+0x12c>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005ea6: 2301 movs r3, #1
|
|
8005ea8: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8005eaa: e00c b.n 8005ec6 <USB_EPStopXfer+0x146>
|
|
}
|
|
} while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA);
|
|
8005eac: 683b ldr r3, [r7, #0]
|
|
8005eae: 781b ldrb r3, [r3, #0]
|
|
8005eb0: 015a lsls r2, r3, #5
|
|
8005eb2: 693b ldr r3, [r7, #16]
|
|
8005eb4: 4413 add r3, r2
|
|
8005eb6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8005eba: 681b ldr r3, [r3, #0]
|
|
8005ebc: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8005ec0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8005ec4: d0e7 beq.n 8005e96 <USB_EPStopXfer+0x116>
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
8005ec6: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8005ec8: 4618 mov r0, r3
|
|
8005eca: 371c adds r7, #28
|
|
8005ecc: 46bd mov sp, r7
|
|
8005ece: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005ed2: 4770 bx lr
|
|
|
|
08005ed4 <USB_WritePacket>:
|
|
* 1 : DMA feature used
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
|
|
uint8_t ch_ep_num, uint16_t len, uint8_t dma)
|
|
{
|
|
8005ed4: b480 push {r7}
|
|
8005ed6: b089 sub sp, #36 @ 0x24
|
|
8005ed8: af00 add r7, sp, #0
|
|
8005eda: 60f8 str r0, [r7, #12]
|
|
8005edc: 60b9 str r1, [r7, #8]
|
|
8005ede: 4611 mov r1, r2
|
|
8005ee0: 461a mov r2, r3
|
|
8005ee2: 460b mov r3, r1
|
|
8005ee4: 71fb strb r3, [r7, #7]
|
|
8005ee6: 4613 mov r3, r2
|
|
8005ee8: 80bb strh r3, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8005eea: 68fb ldr r3, [r7, #12]
|
|
8005eec: 617b str r3, [r7, #20]
|
|
uint8_t *pSrc = src;
|
|
8005eee: 68bb ldr r3, [r7, #8]
|
|
8005ef0: 61fb str r3, [r7, #28]
|
|
uint32_t count32b;
|
|
uint32_t i;
|
|
|
|
if (dma == 0U)
|
|
8005ef2: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8005ef6: 2b00 cmp r3, #0
|
|
8005ef8: d123 bne.n 8005f42 <USB_WritePacket+0x6e>
|
|
{
|
|
count32b = ((uint32_t)len + 3U) / 4U;
|
|
8005efa: 88bb ldrh r3, [r7, #4]
|
|
8005efc: 3303 adds r3, #3
|
|
8005efe: 089b lsrs r3, r3, #2
|
|
8005f00: 613b str r3, [r7, #16]
|
|
for (i = 0U; i < count32b; i++)
|
|
8005f02: 2300 movs r3, #0
|
|
8005f04: 61bb str r3, [r7, #24]
|
|
8005f06: e018 b.n 8005f3a <USB_WritePacket+0x66>
|
|
{
|
|
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
|
|
8005f08: 79fb ldrb r3, [r7, #7]
|
|
8005f0a: 031a lsls r2, r3, #12
|
|
8005f0c: 697b ldr r3, [r7, #20]
|
|
8005f0e: 4413 add r3, r2
|
|
8005f10: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8005f14: 461a mov r2, r3
|
|
8005f16: 69fb ldr r3, [r7, #28]
|
|
8005f18: 681b ldr r3, [r3, #0]
|
|
8005f1a: 6013 str r3, [r2, #0]
|
|
pSrc++;
|
|
8005f1c: 69fb ldr r3, [r7, #28]
|
|
8005f1e: 3301 adds r3, #1
|
|
8005f20: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8005f22: 69fb ldr r3, [r7, #28]
|
|
8005f24: 3301 adds r3, #1
|
|
8005f26: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8005f28: 69fb ldr r3, [r7, #28]
|
|
8005f2a: 3301 adds r3, #1
|
|
8005f2c: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8005f2e: 69fb ldr r3, [r7, #28]
|
|
8005f30: 3301 adds r3, #1
|
|
8005f32: 61fb str r3, [r7, #28]
|
|
for (i = 0U; i < count32b; i++)
|
|
8005f34: 69bb ldr r3, [r7, #24]
|
|
8005f36: 3301 adds r3, #1
|
|
8005f38: 61bb str r3, [r7, #24]
|
|
8005f3a: 69ba ldr r2, [r7, #24]
|
|
8005f3c: 693b ldr r3, [r7, #16]
|
|
8005f3e: 429a cmp r2, r3
|
|
8005f40: d3e2 bcc.n 8005f08 <USB_WritePacket+0x34>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8005f42: 2300 movs r3, #0
|
|
}
|
|
8005f44: 4618 mov r0, r3
|
|
8005f46: 3724 adds r7, #36 @ 0x24
|
|
8005f48: 46bd mov sp, r7
|
|
8005f4a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005f4e: 4770 bx lr
|
|
|
|
08005f50 <USB_ReadPacket>:
|
|
* @param dest source pointer
|
|
* @param len Number of bytes to read
|
|
* @retval pointer to destination buffer
|
|
*/
|
|
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
|
|
{
|
|
8005f50: b480 push {r7}
|
|
8005f52: b08b sub sp, #44 @ 0x2c
|
|
8005f54: af00 add r7, sp, #0
|
|
8005f56: 60f8 str r0, [r7, #12]
|
|
8005f58: 60b9 str r1, [r7, #8]
|
|
8005f5a: 4613 mov r3, r2
|
|
8005f5c: 80fb strh r3, [r7, #6]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8005f5e: 68fb ldr r3, [r7, #12]
|
|
8005f60: 61bb str r3, [r7, #24]
|
|
uint8_t *pDest = dest;
|
|
8005f62: 68bb ldr r3, [r7, #8]
|
|
8005f64: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t pData;
|
|
uint32_t i;
|
|
uint32_t count32b = (uint32_t)len >> 2U;
|
|
8005f66: 88fb ldrh r3, [r7, #6]
|
|
8005f68: 089b lsrs r3, r3, #2
|
|
8005f6a: b29b uxth r3, r3
|
|
8005f6c: 617b str r3, [r7, #20]
|
|
uint16_t remaining_bytes = len % 4U;
|
|
8005f6e: 88fb ldrh r3, [r7, #6]
|
|
8005f70: f003 0303 and.w r3, r3, #3
|
|
8005f74: 83fb strh r3, [r7, #30]
|
|
|
|
for (i = 0U; i < count32b; i++)
|
|
8005f76: 2300 movs r3, #0
|
|
8005f78: 623b str r3, [r7, #32]
|
|
8005f7a: e014 b.n 8005fa6 <USB_ReadPacket+0x56>
|
|
{
|
|
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
|
|
8005f7c: 69bb ldr r3, [r7, #24]
|
|
8005f7e: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8005f82: 681a ldr r2, [r3, #0]
|
|
8005f84: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005f86: 601a str r2, [r3, #0]
|
|
pDest++;
|
|
8005f88: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005f8a: 3301 adds r3, #1
|
|
8005f8c: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8005f8e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005f90: 3301 adds r3, #1
|
|
8005f92: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8005f94: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005f96: 3301 adds r3, #1
|
|
8005f98: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8005f9a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005f9c: 3301 adds r3, #1
|
|
8005f9e: 627b str r3, [r7, #36] @ 0x24
|
|
for (i = 0U; i < count32b; i++)
|
|
8005fa0: 6a3b ldr r3, [r7, #32]
|
|
8005fa2: 3301 adds r3, #1
|
|
8005fa4: 623b str r3, [r7, #32]
|
|
8005fa6: 6a3a ldr r2, [r7, #32]
|
|
8005fa8: 697b ldr r3, [r7, #20]
|
|
8005faa: 429a cmp r2, r3
|
|
8005fac: d3e6 bcc.n 8005f7c <USB_ReadPacket+0x2c>
|
|
}
|
|
|
|
/* When Number of data is not word aligned, read the remaining byte */
|
|
if (remaining_bytes != 0U)
|
|
8005fae: 8bfb ldrh r3, [r7, #30]
|
|
8005fb0: 2b00 cmp r3, #0
|
|
8005fb2: d01e beq.n 8005ff2 <USB_ReadPacket+0xa2>
|
|
{
|
|
i = 0U;
|
|
8005fb4: 2300 movs r3, #0
|
|
8005fb6: 623b str r3, [r7, #32]
|
|
__UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
|
|
8005fb8: 69bb ldr r3, [r7, #24]
|
|
8005fba: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8005fbe: 461a mov r2, r3
|
|
8005fc0: f107 0310 add.w r3, r7, #16
|
|
8005fc4: 6812 ldr r2, [r2, #0]
|
|
8005fc6: 601a str r2, [r3, #0]
|
|
|
|
do
|
|
{
|
|
*(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
|
|
8005fc8: 693a ldr r2, [r7, #16]
|
|
8005fca: 6a3b ldr r3, [r7, #32]
|
|
8005fcc: b2db uxtb r3, r3
|
|
8005fce: 00db lsls r3, r3, #3
|
|
8005fd0: fa22 f303 lsr.w r3, r2, r3
|
|
8005fd4: b2da uxtb r2, r3
|
|
8005fd6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005fd8: 701a strb r2, [r3, #0]
|
|
i++;
|
|
8005fda: 6a3b ldr r3, [r7, #32]
|
|
8005fdc: 3301 adds r3, #1
|
|
8005fde: 623b str r3, [r7, #32]
|
|
pDest++;
|
|
8005fe0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005fe2: 3301 adds r3, #1
|
|
8005fe4: 627b str r3, [r7, #36] @ 0x24
|
|
remaining_bytes--;
|
|
8005fe6: 8bfb ldrh r3, [r7, #30]
|
|
8005fe8: 3b01 subs r3, #1
|
|
8005fea: 83fb strh r3, [r7, #30]
|
|
} while (remaining_bytes != 0U);
|
|
8005fec: 8bfb ldrh r3, [r7, #30]
|
|
8005fee: 2b00 cmp r3, #0
|
|
8005ff0: d1ea bne.n 8005fc8 <USB_ReadPacket+0x78>
|
|
}
|
|
|
|
return ((void *)pDest);
|
|
8005ff2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
}
|
|
8005ff4: 4618 mov r0, r3
|
|
8005ff6: 372c adds r7, #44 @ 0x2c
|
|
8005ff8: 46bd mov sp, r7
|
|
8005ffa: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005ffe: 4770 bx lr
|
|
|
|
08006000 <USB_EPSetStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8006000: b480 push {r7}
|
|
8006002: b085 sub sp, #20
|
|
8006004: af00 add r7, sp, #0
|
|
8006006: 6078 str r0, [r7, #4]
|
|
8006008: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800600a: 687b ldr r3, [r7, #4]
|
|
800600c: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
800600e: 683b ldr r3, [r7, #0]
|
|
8006010: 781b ldrb r3, [r3, #0]
|
|
8006012: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
8006014: 683b ldr r3, [r7, #0]
|
|
8006016: 785b ldrb r3, [r3, #1]
|
|
8006018: 2b01 cmp r3, #1
|
|
800601a: d12c bne.n 8006076 <USB_EPSetStall+0x76>
|
|
{
|
|
if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
|
|
800601c: 68bb ldr r3, [r7, #8]
|
|
800601e: 015a lsls r2, r3, #5
|
|
8006020: 68fb ldr r3, [r7, #12]
|
|
8006022: 4413 add r3, r2
|
|
8006024: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006028: 681b ldr r3, [r3, #0]
|
|
800602a: 2b00 cmp r3, #0
|
|
800602c: db12 blt.n 8006054 <USB_EPSetStall+0x54>
|
|
800602e: 68bb ldr r3, [r7, #8]
|
|
8006030: 2b00 cmp r3, #0
|
|
8006032: d00f beq.n 8006054 <USB_EPSetStall+0x54>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
|
|
8006034: 68bb ldr r3, [r7, #8]
|
|
8006036: 015a lsls r2, r3, #5
|
|
8006038: 68fb ldr r3, [r7, #12]
|
|
800603a: 4413 add r3, r2
|
|
800603c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006040: 681b ldr r3, [r3, #0]
|
|
8006042: 68ba ldr r2, [r7, #8]
|
|
8006044: 0151 lsls r1, r2, #5
|
|
8006046: 68fa ldr r2, [r7, #12]
|
|
8006048: 440a add r2, r1
|
|
800604a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800604e: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8006052: 6013 str r3, [r2, #0]
|
|
}
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
|
|
8006054: 68bb ldr r3, [r7, #8]
|
|
8006056: 015a lsls r2, r3, #5
|
|
8006058: 68fb ldr r3, [r7, #12]
|
|
800605a: 4413 add r3, r2
|
|
800605c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006060: 681b ldr r3, [r3, #0]
|
|
8006062: 68ba ldr r2, [r7, #8]
|
|
8006064: 0151 lsls r1, r2, #5
|
|
8006066: 68fa ldr r2, [r7, #12]
|
|
8006068: 440a add r2, r1
|
|
800606a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800606e: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8006072: 6013 str r3, [r2, #0]
|
|
8006074: e02b b.n 80060ce <USB_EPSetStall+0xce>
|
|
}
|
|
else
|
|
{
|
|
if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
|
|
8006076: 68bb ldr r3, [r7, #8]
|
|
8006078: 015a lsls r2, r3, #5
|
|
800607a: 68fb ldr r3, [r7, #12]
|
|
800607c: 4413 add r3, r2
|
|
800607e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006082: 681b ldr r3, [r3, #0]
|
|
8006084: 2b00 cmp r3, #0
|
|
8006086: db12 blt.n 80060ae <USB_EPSetStall+0xae>
|
|
8006088: 68bb ldr r3, [r7, #8]
|
|
800608a: 2b00 cmp r3, #0
|
|
800608c: d00f beq.n 80060ae <USB_EPSetStall+0xae>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
|
|
800608e: 68bb ldr r3, [r7, #8]
|
|
8006090: 015a lsls r2, r3, #5
|
|
8006092: 68fb ldr r3, [r7, #12]
|
|
8006094: 4413 add r3, r2
|
|
8006096: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800609a: 681b ldr r3, [r3, #0]
|
|
800609c: 68ba ldr r2, [r7, #8]
|
|
800609e: 0151 lsls r1, r2, #5
|
|
80060a0: 68fa ldr r2, [r7, #12]
|
|
80060a2: 440a add r2, r1
|
|
80060a4: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
80060a8: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
80060ac: 6013 str r3, [r2, #0]
|
|
}
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
|
|
80060ae: 68bb ldr r3, [r7, #8]
|
|
80060b0: 015a lsls r2, r3, #5
|
|
80060b2: 68fb ldr r3, [r7, #12]
|
|
80060b4: 4413 add r3, r2
|
|
80060b6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80060ba: 681b ldr r3, [r3, #0]
|
|
80060bc: 68ba ldr r2, [r7, #8]
|
|
80060be: 0151 lsls r1, r2, #5
|
|
80060c0: 68fa ldr r2, [r7, #12]
|
|
80060c2: 440a add r2, r1
|
|
80060c4: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
80060c8: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
80060cc: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
80060ce: 2300 movs r3, #0
|
|
}
|
|
80060d0: 4618 mov r0, r3
|
|
80060d2: 3714 adds r7, #20
|
|
80060d4: 46bd mov sp, r7
|
|
80060d6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80060da: 4770 bx lr
|
|
|
|
080060dc <USB_EPClearStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
80060dc: b480 push {r7}
|
|
80060de: b085 sub sp, #20
|
|
80060e0: af00 add r7, sp, #0
|
|
80060e2: 6078 str r0, [r7, #4]
|
|
80060e4: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80060e6: 687b ldr r3, [r7, #4]
|
|
80060e8: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
80060ea: 683b ldr r3, [r7, #0]
|
|
80060ec: 781b ldrb r3, [r3, #0]
|
|
80060ee: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
80060f0: 683b ldr r3, [r7, #0]
|
|
80060f2: 785b ldrb r3, [r3, #1]
|
|
80060f4: 2b01 cmp r3, #1
|
|
80060f6: d128 bne.n 800614a <USB_EPClearStall+0x6e>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
|
80060f8: 68bb ldr r3, [r7, #8]
|
|
80060fa: 015a lsls r2, r3, #5
|
|
80060fc: 68fb ldr r3, [r7, #12]
|
|
80060fe: 4413 add r3, r2
|
|
8006100: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006104: 681b ldr r3, [r3, #0]
|
|
8006106: 68ba ldr r2, [r7, #8]
|
|
8006108: 0151 lsls r1, r2, #5
|
|
800610a: 68fa ldr r2, [r7, #12]
|
|
800610c: 440a add r2, r1
|
|
800610e: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006112: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
8006116: 6013 str r3, [r2, #0]
|
|
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
|
|
8006118: 683b ldr r3, [r7, #0]
|
|
800611a: 791b ldrb r3, [r3, #4]
|
|
800611c: 2b03 cmp r3, #3
|
|
800611e: d003 beq.n 8006128 <USB_EPClearStall+0x4c>
|
|
8006120: 683b ldr r3, [r7, #0]
|
|
8006122: 791b ldrb r3, [r3, #4]
|
|
8006124: 2b02 cmp r3, #2
|
|
8006126: d138 bne.n 800619a <USB_EPClearStall+0xbe>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
|
|
8006128: 68bb ldr r3, [r7, #8]
|
|
800612a: 015a lsls r2, r3, #5
|
|
800612c: 68fb ldr r3, [r7, #12]
|
|
800612e: 4413 add r3, r2
|
|
8006130: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006134: 681b ldr r3, [r3, #0]
|
|
8006136: 68ba ldr r2, [r7, #8]
|
|
8006138: 0151 lsls r1, r2, #5
|
|
800613a: 68fa ldr r2, [r7, #12]
|
|
800613c: 440a add r2, r1
|
|
800613e: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8006142: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006146: 6013 str r3, [r2, #0]
|
|
8006148: e027 b.n 800619a <USB_EPClearStall+0xbe>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
|
800614a: 68bb ldr r3, [r7, #8]
|
|
800614c: 015a lsls r2, r3, #5
|
|
800614e: 68fb ldr r3, [r7, #12]
|
|
8006150: 4413 add r3, r2
|
|
8006152: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006156: 681b ldr r3, [r3, #0]
|
|
8006158: 68ba ldr r2, [r7, #8]
|
|
800615a: 0151 lsls r1, r2, #5
|
|
800615c: 68fa ldr r2, [r7, #12]
|
|
800615e: 440a add r2, r1
|
|
8006160: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006164: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
8006168: 6013 str r3, [r2, #0]
|
|
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
|
|
800616a: 683b ldr r3, [r7, #0]
|
|
800616c: 791b ldrb r3, [r3, #4]
|
|
800616e: 2b03 cmp r3, #3
|
|
8006170: d003 beq.n 800617a <USB_EPClearStall+0x9e>
|
|
8006172: 683b ldr r3, [r7, #0]
|
|
8006174: 791b ldrb r3, [r3, #4]
|
|
8006176: 2b02 cmp r3, #2
|
|
8006178: d10f bne.n 800619a <USB_EPClearStall+0xbe>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
|
|
800617a: 68bb ldr r3, [r7, #8]
|
|
800617c: 015a lsls r2, r3, #5
|
|
800617e: 68fb ldr r3, [r7, #12]
|
|
8006180: 4413 add r3, r2
|
|
8006182: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006186: 681b ldr r3, [r3, #0]
|
|
8006188: 68ba ldr r2, [r7, #8]
|
|
800618a: 0151 lsls r1, r2, #5
|
|
800618c: 68fa ldr r2, [r7, #12]
|
|
800618e: 440a add r2, r1
|
|
8006190: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006194: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8006198: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800619a: 2300 movs r3, #0
|
|
}
|
|
800619c: 4618 mov r0, r3
|
|
800619e: 3714 adds r7, #20
|
|
80061a0: 46bd mov sp, r7
|
|
80061a2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80061a6: 4770 bx lr
|
|
|
|
080061a8 <USB_SetDevAddress>:
|
|
* @param address new device address to be assigned
|
|
* This parameter can be a value from 0 to 255
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
|
|
{
|
|
80061a8: b480 push {r7}
|
|
80061aa: b085 sub sp, #20
|
|
80061ac: af00 add r7, sp, #0
|
|
80061ae: 6078 str r0, [r7, #4]
|
|
80061b0: 460b mov r3, r1
|
|
80061b2: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80061b4: 687b ldr r3, [r7, #4]
|
|
80061b6: 60fb str r3, [r7, #12]
|
|
|
|
USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
|
|
80061b8: 68fb ldr r3, [r7, #12]
|
|
80061ba: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80061be: 681b ldr r3, [r3, #0]
|
|
80061c0: 68fa ldr r2, [r7, #12]
|
|
80061c2: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80061c6: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
|
|
80061ca: 6013 str r3, [r2, #0]
|
|
USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
|
|
80061cc: 68fb ldr r3, [r7, #12]
|
|
80061ce: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80061d2: 681a ldr r2, [r3, #0]
|
|
80061d4: 78fb ldrb r3, [r7, #3]
|
|
80061d6: 011b lsls r3, r3, #4
|
|
80061d8: f403 63fe and.w r3, r3, #2032 @ 0x7f0
|
|
80061dc: 68f9 ldr r1, [r7, #12]
|
|
80061de: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80061e2: 4313 orrs r3, r2
|
|
80061e4: 600b str r3, [r1, #0]
|
|
|
|
return HAL_OK;
|
|
80061e6: 2300 movs r3, #0
|
|
}
|
|
80061e8: 4618 mov r0, r3
|
|
80061ea: 3714 adds r7, #20
|
|
80061ec: 46bd mov sp, r7
|
|
80061ee: f85d 7b04 ldr.w r7, [sp], #4
|
|
80061f2: 4770 bx lr
|
|
|
|
080061f4 <USB_DevConnect>:
|
|
* @brief USB_DevConnect : Connect the USB device by enabling Rpu
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80061f4: b480 push {r7}
|
|
80061f6: b085 sub sp, #20
|
|
80061f8: af00 add r7, sp, #0
|
|
80061fa: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80061fc: 687b ldr r3, [r7, #4]
|
|
80061fe: 60fb str r3, [r7, #12]
|
|
|
|
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
|
|
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
|
|
8006200: 68fb ldr r3, [r7, #12]
|
|
8006202: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
8006206: 681b ldr r3, [r3, #0]
|
|
8006208: 68fa ldr r2, [r7, #12]
|
|
800620a: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
800620e: f023 0303 bic.w r3, r3, #3
|
|
8006212: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
|
|
8006214: 68fb ldr r3, [r7, #12]
|
|
8006216: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800621a: 685b ldr r3, [r3, #4]
|
|
800621c: 68fa ldr r2, [r7, #12]
|
|
800621e: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8006222: f023 0302 bic.w r3, r3, #2
|
|
8006226: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
8006228: 2300 movs r3, #0
|
|
}
|
|
800622a: 4618 mov r0, r3
|
|
800622c: 3714 adds r7, #20
|
|
800622e: 46bd mov sp, r7
|
|
8006230: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006234: 4770 bx lr
|
|
|
|
08006236 <USB_DevDisconnect>:
|
|
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006236: b480 push {r7}
|
|
8006238: b085 sub sp, #20
|
|
800623a: af00 add r7, sp, #0
|
|
800623c: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800623e: 687b ldr r3, [r7, #4]
|
|
8006240: 60fb str r3, [r7, #12]
|
|
|
|
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
|
|
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
|
|
8006242: 68fb ldr r3, [r7, #12]
|
|
8006244: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
8006248: 681b ldr r3, [r3, #0]
|
|
800624a: 68fa ldr r2, [r7, #12]
|
|
800624c: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
8006250: f023 0303 bic.w r3, r3, #3
|
|
8006254: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
8006256: 68fb ldr r3, [r7, #12]
|
|
8006258: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800625c: 685b ldr r3, [r3, #4]
|
|
800625e: 68fa ldr r2, [r7, #12]
|
|
8006260: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8006264: f043 0302 orr.w r3, r3, #2
|
|
8006268: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
800626a: 2300 movs r3, #0
|
|
}
|
|
800626c: 4618 mov r0, r3
|
|
800626e: 3714 adds r7, #20
|
|
8006270: 46bd mov sp, r7
|
|
8006272: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006276: 4770 bx lr
|
|
|
|
08006278 <USB_ReadInterrupts>:
|
|
* @brief USB_ReadInterrupts: return the global USB interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Global Interrupt status
|
|
*/
|
|
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
|
|
{
|
|
8006278: b480 push {r7}
|
|
800627a: b085 sub sp, #20
|
|
800627c: af00 add r7, sp, #0
|
|
800627e: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx->GINTSTS;
|
|
8006280: 687b ldr r3, [r7, #4]
|
|
8006282: 695b ldr r3, [r3, #20]
|
|
8006284: 60fb str r3, [r7, #12]
|
|
tmpreg &= USBx->GINTMSK;
|
|
8006286: 687b ldr r3, [r7, #4]
|
|
8006288: 699b ldr r3, [r3, #24]
|
|
800628a: 68fa ldr r2, [r7, #12]
|
|
800628c: 4013 ands r3, r2
|
|
800628e: 60fb str r3, [r7, #12]
|
|
|
|
return tmpreg;
|
|
8006290: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8006292: 4618 mov r0, r3
|
|
8006294: 3714 adds r7, #20
|
|
8006296: 46bd mov sp, r7
|
|
8006298: f85d 7b04 ldr.w r7, [sp], #4
|
|
800629c: 4770 bx lr
|
|
|
|
0800629e <USB_ReadDevAllOutEpInterrupt>:
|
|
* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Device OUT EP interrupt status
|
|
*/
|
|
uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800629e: b480 push {r7}
|
|
80062a0: b085 sub sp, #20
|
|
80062a2: af00 add r7, sp, #0
|
|
80062a4: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80062a6: 687b ldr r3, [r7, #4]
|
|
80062a8: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_DEVICE->DAINT;
|
|
80062aa: 68fb ldr r3, [r7, #12]
|
|
80062ac: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80062b0: 699b ldr r3, [r3, #24]
|
|
80062b2: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DAINTMSK;
|
|
80062b4: 68fb ldr r3, [r7, #12]
|
|
80062b6: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80062ba: 69db ldr r3, [r3, #28]
|
|
80062bc: 68ba ldr r2, [r7, #8]
|
|
80062be: 4013 ands r3, r2
|
|
80062c0: 60bb str r3, [r7, #8]
|
|
|
|
return ((tmpreg & 0xffff0000U) >> 16);
|
|
80062c2: 68bb ldr r3, [r7, #8]
|
|
80062c4: 0c1b lsrs r3, r3, #16
|
|
}
|
|
80062c6: 4618 mov r0, r3
|
|
80062c8: 3714 adds r7, #20
|
|
80062ca: 46bd mov sp, r7
|
|
80062cc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80062d0: 4770 bx lr
|
|
|
|
080062d2 <USB_ReadDevAllInEpInterrupt>:
|
|
* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Device IN EP interrupt status
|
|
*/
|
|
uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80062d2: b480 push {r7}
|
|
80062d4: b085 sub sp, #20
|
|
80062d6: af00 add r7, sp, #0
|
|
80062d8: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80062da: 687b ldr r3, [r7, #4]
|
|
80062dc: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_DEVICE->DAINT;
|
|
80062de: 68fb ldr r3, [r7, #12]
|
|
80062e0: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80062e4: 699b ldr r3, [r3, #24]
|
|
80062e6: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DAINTMSK;
|
|
80062e8: 68fb ldr r3, [r7, #12]
|
|
80062ea: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80062ee: 69db ldr r3, [r3, #28]
|
|
80062f0: 68ba ldr r2, [r7, #8]
|
|
80062f2: 4013 ands r3, r2
|
|
80062f4: 60bb str r3, [r7, #8]
|
|
|
|
return ((tmpreg & 0xFFFFU));
|
|
80062f6: 68bb ldr r3, [r7, #8]
|
|
80062f8: b29b uxth r3, r3
|
|
}
|
|
80062fa: 4618 mov r0, r3
|
|
80062fc: 3714 adds r7, #20
|
|
80062fe: 46bd mov sp, r7
|
|
8006300: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006304: 4770 bx lr
|
|
|
|
08006306 <USB_ReadDevOutEPInterrupt>:
|
|
* @param epnum endpoint number
|
|
* This parameter can be a value from 0 to 15
|
|
* @retval Device OUT EP Interrupt register
|
|
*/
|
|
uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
|
|
{
|
|
8006306: b480 push {r7}
|
|
8006308: b085 sub sp, #20
|
|
800630a: af00 add r7, sp, #0
|
|
800630c: 6078 str r0, [r7, #4]
|
|
800630e: 460b mov r3, r1
|
|
8006310: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006312: 687b ldr r3, [r7, #4]
|
|
8006314: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
|
|
8006316: 78fb ldrb r3, [r7, #3]
|
|
8006318: 015a lsls r2, r3, #5
|
|
800631a: 68fb ldr r3, [r7, #12]
|
|
800631c: 4413 add r3, r2
|
|
800631e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006322: 689b ldr r3, [r3, #8]
|
|
8006324: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DOEPMSK;
|
|
8006326: 68fb ldr r3, [r7, #12]
|
|
8006328: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800632c: 695b ldr r3, [r3, #20]
|
|
800632e: 68ba ldr r2, [r7, #8]
|
|
8006330: 4013 ands r3, r2
|
|
8006332: 60bb str r3, [r7, #8]
|
|
|
|
return tmpreg;
|
|
8006334: 68bb ldr r3, [r7, #8]
|
|
}
|
|
8006336: 4618 mov r0, r3
|
|
8006338: 3714 adds r7, #20
|
|
800633a: 46bd mov sp, r7
|
|
800633c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006340: 4770 bx lr
|
|
|
|
08006342 <USB_ReadDevInEPInterrupt>:
|
|
* @param epnum endpoint number
|
|
* This parameter can be a value from 0 to 15
|
|
* @retval Device IN EP Interrupt register
|
|
*/
|
|
uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
|
|
{
|
|
8006342: b480 push {r7}
|
|
8006344: b087 sub sp, #28
|
|
8006346: af00 add r7, sp, #0
|
|
8006348: 6078 str r0, [r7, #4]
|
|
800634a: 460b mov r3, r1
|
|
800634c: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800634e: 687b ldr r3, [r7, #4]
|
|
8006350: 617b str r3, [r7, #20]
|
|
uint32_t tmpreg;
|
|
uint32_t msk;
|
|
uint32_t emp;
|
|
|
|
msk = USBx_DEVICE->DIEPMSK;
|
|
8006352: 697b ldr r3, [r7, #20]
|
|
8006354: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006358: 691b ldr r3, [r3, #16]
|
|
800635a: 613b str r3, [r7, #16]
|
|
emp = USBx_DEVICE->DIEPEMPMSK;
|
|
800635c: 697b ldr r3, [r7, #20]
|
|
800635e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8006362: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8006364: 60fb str r3, [r7, #12]
|
|
msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
|
|
8006366: 78fb ldrb r3, [r7, #3]
|
|
8006368: f003 030f and.w r3, r3, #15
|
|
800636c: 68fa ldr r2, [r7, #12]
|
|
800636e: fa22 f303 lsr.w r3, r2, r3
|
|
8006372: 01db lsls r3, r3, #7
|
|
8006374: b2db uxtb r3, r3
|
|
8006376: 693a ldr r2, [r7, #16]
|
|
8006378: 4313 orrs r3, r2
|
|
800637a: 613b str r3, [r7, #16]
|
|
tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
|
|
800637c: 78fb ldrb r3, [r7, #3]
|
|
800637e: 015a lsls r2, r3, #5
|
|
8006380: 697b ldr r3, [r7, #20]
|
|
8006382: 4413 add r3, r2
|
|
8006384: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8006388: 689b ldr r3, [r3, #8]
|
|
800638a: 693a ldr r2, [r7, #16]
|
|
800638c: 4013 ands r3, r2
|
|
800638e: 60bb str r3, [r7, #8]
|
|
|
|
return tmpreg;
|
|
8006390: 68bb ldr r3, [r7, #8]
|
|
}
|
|
8006392: 4618 mov r0, r3
|
|
8006394: 371c adds r7, #28
|
|
8006396: 46bd mov sp, r7
|
|
8006398: f85d 7b04 ldr.w r7, [sp], #4
|
|
800639c: 4770 bx lr
|
|
|
|
0800639e <USB_GetMode>:
|
|
* This parameter can be one of these values:
|
|
* 1 : Host
|
|
* 0 : Device
|
|
*/
|
|
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800639e: b480 push {r7}
|
|
80063a0: b083 sub sp, #12
|
|
80063a2: af00 add r7, sp, #0
|
|
80063a4: 6078 str r0, [r7, #4]
|
|
return ((USBx->GINTSTS) & 0x1U);
|
|
80063a6: 687b ldr r3, [r7, #4]
|
|
80063a8: 695b ldr r3, [r3, #20]
|
|
80063aa: f003 0301 and.w r3, r3, #1
|
|
}
|
|
80063ae: 4618 mov r0, r3
|
|
80063b0: 370c adds r7, #12
|
|
80063b2: 46bd mov sp, r7
|
|
80063b4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80063b8: 4770 bx lr
|
|
|
|
080063ba <USB_ActivateSetup>:
|
|
* @brief Activate EP0 for Setup transactions
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80063ba: b480 push {r7}
|
|
80063bc: b085 sub sp, #20
|
|
80063be: af00 add r7, sp, #0
|
|
80063c0: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80063c2: 687b ldr r3, [r7, #4]
|
|
80063c4: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the MPS of the IN EP0 to 64 bytes */
|
|
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
|
|
80063c6: 68fb ldr r3, [r7, #12]
|
|
80063c8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80063cc: 681b ldr r3, [r3, #0]
|
|
80063ce: 68fa ldr r2, [r7, #12]
|
|
80063d0: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80063d4: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
|
|
80063d8: f023 0307 bic.w r3, r3, #7
|
|
80063dc: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
|
|
80063de: 68fb ldr r3, [r7, #12]
|
|
80063e0: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80063e4: 685b ldr r3, [r3, #4]
|
|
80063e6: 68fa ldr r2, [r7, #12]
|
|
80063e8: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80063ec: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80063f0: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
80063f2: 2300 movs r3, #0
|
|
}
|
|
80063f4: 4618 mov r0, r3
|
|
80063f6: 3714 adds r7, #20
|
|
80063f8: 46bd mov sp, r7
|
|
80063fa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80063fe: 4770 bx lr
|
|
|
|
08006400 <USB_EP0_OutStart>:
|
|
* 1 : DMA feature used
|
|
* @param psetup pointer to setup packet
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup)
|
|
{
|
|
8006400: b480 push {r7}
|
|
8006402: b087 sub sp, #28
|
|
8006404: af00 add r7, sp, #0
|
|
8006406: 60f8 str r0, [r7, #12]
|
|
8006408: 460b mov r3, r1
|
|
800640a: 607a str r2, [r7, #4]
|
|
800640c: 72fb strb r3, [r7, #11]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800640e: 68fb ldr r3, [r7, #12]
|
|
8006410: 617b str r3, [r7, #20]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
8006412: 68fb ldr r3, [r7, #12]
|
|
8006414: 333c adds r3, #60 @ 0x3c
|
|
8006416: 3304 adds r3, #4
|
|
8006418: 681b ldr r3, [r3, #0]
|
|
800641a: 613b str r3, [r7, #16]
|
|
|
|
if (gSNPSiD > USB_OTG_CORE_ID_300A)
|
|
800641c: 693b ldr r3, [r7, #16]
|
|
800641e: 4a26 ldr r2, [pc, #152] @ (80064b8 <USB_EP0_OutStart+0xb8>)
|
|
8006420: 4293 cmp r3, r2
|
|
8006422: d90a bls.n 800643a <USB_EP0_OutStart+0x3a>
|
|
{
|
|
if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
8006424: 697b ldr r3, [r7, #20]
|
|
8006426: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800642a: 681b ldr r3, [r3, #0]
|
|
800642c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006430: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8006434: d101 bne.n 800643a <USB_EP0_OutStart+0x3a>
|
|
{
|
|
return HAL_OK;
|
|
8006436: 2300 movs r3, #0
|
|
8006438: e037 b.n 80064aa <USB_EP0_OutStart+0xaa>
|
|
}
|
|
}
|
|
|
|
USBx_OUTEP(0U)->DOEPTSIZ = 0U;
|
|
800643a: 697b ldr r3, [r7, #20]
|
|
800643c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006440: 461a mov r2, r3
|
|
8006442: 2300 movs r3, #0
|
|
8006444: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
8006446: 697b ldr r3, [r7, #20]
|
|
8006448: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800644c: 691b ldr r3, [r3, #16]
|
|
800644e: 697a ldr r2, [r7, #20]
|
|
8006450: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006454: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8006458: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
|
|
800645a: 697b ldr r3, [r7, #20]
|
|
800645c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006460: 691b ldr r3, [r3, #16]
|
|
8006462: 697a ldr r2, [r7, #20]
|
|
8006464: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8006468: f043 0318 orr.w r3, r3, #24
|
|
800646c: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
|
|
800646e: 697b ldr r3, [r7, #20]
|
|
8006470: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8006474: 691b ldr r3, [r3, #16]
|
|
8006476: 697a ldr r2, [r7, #20]
|
|
8006478: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800647c: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000
|
|
8006480: 6113 str r3, [r2, #16]
|
|
|
|
if (dma == 1U)
|
|
8006482: 7afb ldrb r3, [r7, #11]
|
|
8006484: 2b01 cmp r3, #1
|
|
8006486: d10f bne.n 80064a8 <USB_EP0_OutStart+0xa8>
|
|
{
|
|
USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
|
|
8006488: 697b ldr r3, [r7, #20]
|
|
800648a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800648e: 461a mov r2, r3
|
|
8006490: 687b ldr r3, [r7, #4]
|
|
8006492: 6153 str r3, [r2, #20]
|
|
/* EP enable */
|
|
USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
|
|
8006494: 697b ldr r3, [r7, #20]
|
|
8006496: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800649a: 681b ldr r3, [r3, #0]
|
|
800649c: 697a ldr r2, [r7, #20]
|
|
800649e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
80064a2: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000
|
|
80064a6: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
80064a8: 2300 movs r3, #0
|
|
}
|
|
80064aa: 4618 mov r0, r3
|
|
80064ac: 371c adds r7, #28
|
|
80064ae: 46bd mov sp, r7
|
|
80064b0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80064b4: 4770 bx lr
|
|
80064b6: bf00 nop
|
|
80064b8: 4f54300a .word 0x4f54300a
|
|
|
|
080064bc <USB_CoreReset>:
|
|
* @brief Reset the USB Core (needed after USB clock settings change)
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80064bc: b480 push {r7}
|
|
80064be: b085 sub sp, #20
|
|
80064c0: af00 add r7, sp, #0
|
|
80064c2: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
80064c4: 2300 movs r3, #0
|
|
80064c6: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
80064c8: 68fb ldr r3, [r7, #12]
|
|
80064ca: 3301 adds r3, #1
|
|
80064cc: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80064ce: 68fb ldr r3, [r7, #12]
|
|
80064d0: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80064d4: d901 bls.n 80064da <USB_CoreReset+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80064d6: 2303 movs r3, #3
|
|
80064d8: e022 b.n 8006520 <USB_CoreReset+0x64>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
80064da: 687b ldr r3, [r7, #4]
|
|
80064dc: 691b ldr r3, [r3, #16]
|
|
80064de: 2b00 cmp r3, #0
|
|
80064e0: daf2 bge.n 80064c8 <USB_CoreReset+0xc>
|
|
|
|
count = 10U;
|
|
80064e2: 230a movs r3, #10
|
|
80064e4: 60fb str r3, [r7, #12]
|
|
|
|
/* few cycles before setting core reset */
|
|
while (count > 0U)
|
|
80064e6: e002 b.n 80064ee <USB_CoreReset+0x32>
|
|
{
|
|
count--;
|
|
80064e8: 68fb ldr r3, [r7, #12]
|
|
80064ea: 3b01 subs r3, #1
|
|
80064ec: 60fb str r3, [r7, #12]
|
|
while (count > 0U)
|
|
80064ee: 68fb ldr r3, [r7, #12]
|
|
80064f0: 2b00 cmp r3, #0
|
|
80064f2: d1f9 bne.n 80064e8 <USB_CoreReset+0x2c>
|
|
}
|
|
|
|
/* Core Soft Reset */
|
|
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
|
|
80064f4: 687b ldr r3, [r7, #4]
|
|
80064f6: 691b ldr r3, [r3, #16]
|
|
80064f8: f043 0201 orr.w r2, r3, #1
|
|
80064fc: 687b ldr r3, [r7, #4]
|
|
80064fe: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8006500: 68fb ldr r3, [r7, #12]
|
|
8006502: 3301 adds r3, #1
|
|
8006504: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8006506: 68fb ldr r3, [r7, #12]
|
|
8006508: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800650c: d901 bls.n 8006512 <USB_CoreReset+0x56>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800650e: 2303 movs r3, #3
|
|
8006510: e006 b.n 8006520 <USB_CoreReset+0x64>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
|
|
8006512: 687b ldr r3, [r7, #4]
|
|
8006514: 691b ldr r3, [r3, #16]
|
|
8006516: f003 0301 and.w r3, r3, #1
|
|
800651a: 2b01 cmp r3, #1
|
|
800651c: d0f0 beq.n 8006500 <USB_CoreReset+0x44>
|
|
|
|
return HAL_OK;
|
|
800651e: 2300 movs r3, #0
|
|
}
|
|
8006520: 4618 mov r0, r3
|
|
8006522: 3714 adds r7, #20
|
|
8006524: 46bd mov sp, r7
|
|
8006526: f85d 7b04 ldr.w r7, [sp], #4
|
|
800652a: 4770 bx lr
|
|
|
|
0800652c <USBD_HID_Init>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
800652c: b580 push {r7, lr}
|
|
800652e: b084 sub sp, #16
|
|
8006530: af00 add r7, sp, #0
|
|
8006532: 6078 str r0, [r7, #4]
|
|
8006534: 460b mov r3, r1
|
|
8006536: 70fb strb r3, [r7, #3]
|
|
UNUSED(cfgidx);
|
|
|
|
USBD_HID_HandleTypeDef *hhid;
|
|
|
|
hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef));
|
|
8006538: 2010 movs r0, #16
|
|
800653a: f002 f9b3 bl 80088a4 <USBD_static_malloc>
|
|
800653e: 60f8 str r0, [r7, #12]
|
|
|
|
if (hhid == NULL)
|
|
8006540: 68fb ldr r3, [r7, #12]
|
|
8006542: 2b00 cmp r3, #0
|
|
8006544: d109 bne.n 800655a <USBD_HID_Init+0x2e>
|
|
{
|
|
pdev->pClassDataCmsit[pdev->classId] = NULL;
|
|
8006546: 687b ldr r3, [r7, #4]
|
|
8006548: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800654c: 687b ldr r3, [r7, #4]
|
|
800654e: 32b0 adds r2, #176 @ 0xb0
|
|
8006550: 2100 movs r1, #0
|
|
8006552: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
return (uint8_t)USBD_EMEM;
|
|
8006556: 2302 movs r3, #2
|
|
8006558: e048 b.n 80065ec <USBD_HID_Init+0xc0>
|
|
}
|
|
|
|
pdev->pClassDataCmsit[pdev->classId] = (void *)hhid;
|
|
800655a: 687b ldr r3, [r7, #4]
|
|
800655c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8006560: 687b ldr r3, [r7, #4]
|
|
8006562: 32b0 adds r2, #176 @ 0xb0
|
|
8006564: 68f9 ldr r1, [r7, #12]
|
|
8006566: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
|
|
800656a: 687b ldr r3, [r7, #4]
|
|
800656c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8006570: 687b ldr r3, [r7, #4]
|
|
8006572: 32b0 adds r2, #176 @ 0xb0
|
|
8006574: f853 2022 ldr.w r2, [r3, r2, lsl #2]
|
|
8006578: 687b ldr r3, [r7, #4]
|
|
800657a: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
|
|
#ifdef USE_USBD_COMPOSITE
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
800657e: 687b ldr r3, [r7, #4]
|
|
8006580: 7c1b ldrb r3, [r3, #16]
|
|
8006582: 2b00 cmp r3, #0
|
|
8006584: d10d bne.n 80065a2 <USBD_HID_Init+0x76>
|
|
{
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL;
|
|
8006586: 4b1b ldr r3, [pc, #108] @ (80065f4 <USBD_HID_Init+0xc8>)
|
|
8006588: 781b ldrb r3, [r3, #0]
|
|
800658a: f003 020f and.w r2, r3, #15
|
|
800658e: 6879 ldr r1, [r7, #4]
|
|
8006590: 4613 mov r3, r2
|
|
8006592: 009b lsls r3, r3, #2
|
|
8006594: 4413 add r3, r2
|
|
8006596: 009b lsls r3, r3, #2
|
|
8006598: 440b add r3, r1
|
|
800659a: 331c adds r3, #28
|
|
800659c: 2207 movs r2, #7
|
|
800659e: 601a str r2, [r3, #0]
|
|
80065a0: e00c b.n 80065bc <USBD_HID_Init+0x90>
|
|
}
|
|
else /* LOW and FULL-speed endpoints */
|
|
{
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL;
|
|
80065a2: 4b14 ldr r3, [pc, #80] @ (80065f4 <USBD_HID_Init+0xc8>)
|
|
80065a4: 781b ldrb r3, [r3, #0]
|
|
80065a6: f003 020f and.w r2, r3, #15
|
|
80065aa: 6879 ldr r1, [r7, #4]
|
|
80065ac: 4613 mov r3, r2
|
|
80065ae: 009b lsls r3, r3, #2
|
|
80065b0: 4413 add r3, r2
|
|
80065b2: 009b lsls r3, r3, #2
|
|
80065b4: 440b add r3, r1
|
|
80065b6: 331c adds r3, #28
|
|
80065b8: 220a movs r2, #10
|
|
80065ba: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Open EP IN */
|
|
(void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE);
|
|
80065bc: 4b0d ldr r3, [pc, #52] @ (80065f4 <USBD_HID_Init+0xc8>)
|
|
80065be: 7819 ldrb r1, [r3, #0]
|
|
80065c0: 2304 movs r3, #4
|
|
80065c2: 2203 movs r2, #3
|
|
80065c4: 6878 ldr r0, [r7, #4]
|
|
80065c6: f002 f80e bl 80085e6 <USBD_LL_OpenEP>
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U;
|
|
80065ca: 4b0a ldr r3, [pc, #40] @ (80065f4 <USBD_HID_Init+0xc8>)
|
|
80065cc: 781b ldrb r3, [r3, #0]
|
|
80065ce: f003 020f and.w r2, r3, #15
|
|
80065d2: 6879 ldr r1, [r7, #4]
|
|
80065d4: 4613 mov r3, r2
|
|
80065d6: 009b lsls r3, r3, #2
|
|
80065d8: 4413 add r3, r2
|
|
80065da: 009b lsls r3, r3, #2
|
|
80065dc: 440b add r3, r1
|
|
80065de: 3323 adds r3, #35 @ 0x23
|
|
80065e0: 2201 movs r2, #1
|
|
80065e2: 701a strb r2, [r3, #0]
|
|
|
|
hhid->state = USBD_HID_IDLE;
|
|
80065e4: 68fb ldr r3, [r7, #12]
|
|
80065e6: 2200 movs r2, #0
|
|
80065e8: 731a strb r2, [r3, #12]
|
|
|
|
return (uint8_t)USBD_OK;
|
|
80065ea: 2300 movs r3, #0
|
|
}
|
|
80065ec: 4618 mov r0, r3
|
|
80065ee: 3710 adds r7, #16
|
|
80065f0: 46bd mov sp, r7
|
|
80065f2: bd80 pop {r7, pc}
|
|
80065f4: 200000ca .word 0x200000ca
|
|
|
|
080065f8 <USBD_HID_DeInit>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
80065f8: b580 push {r7, lr}
|
|
80065fa: b082 sub sp, #8
|
|
80065fc: af00 add r7, sp, #0
|
|
80065fe: 6078 str r0, [r7, #4]
|
|
8006600: 460b mov r3, r1
|
|
8006602: 70fb strb r3, [r7, #3]
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Close HID EPs */
|
|
(void)USBD_LL_CloseEP(pdev, HIDInEpAdd);
|
|
8006604: 4b1f ldr r3, [pc, #124] @ (8006684 <USBD_HID_DeInit+0x8c>)
|
|
8006606: 781b ldrb r3, [r3, #0]
|
|
8006608: 4619 mov r1, r3
|
|
800660a: 6878 ldr r0, [r7, #4]
|
|
800660c: f002 f811 bl 8008632 <USBD_LL_CloseEP>
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U;
|
|
8006610: 4b1c ldr r3, [pc, #112] @ (8006684 <USBD_HID_DeInit+0x8c>)
|
|
8006612: 781b ldrb r3, [r3, #0]
|
|
8006614: f003 020f and.w r2, r3, #15
|
|
8006618: 6879 ldr r1, [r7, #4]
|
|
800661a: 4613 mov r3, r2
|
|
800661c: 009b lsls r3, r3, #2
|
|
800661e: 4413 add r3, r2
|
|
8006620: 009b lsls r3, r3, #2
|
|
8006622: 440b add r3, r1
|
|
8006624: 3323 adds r3, #35 @ 0x23
|
|
8006626: 2200 movs r2, #0
|
|
8006628: 701a strb r2, [r3, #0]
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U;
|
|
800662a: 4b16 ldr r3, [pc, #88] @ (8006684 <USBD_HID_DeInit+0x8c>)
|
|
800662c: 781b ldrb r3, [r3, #0]
|
|
800662e: f003 020f and.w r2, r3, #15
|
|
8006632: 6879 ldr r1, [r7, #4]
|
|
8006634: 4613 mov r3, r2
|
|
8006636: 009b lsls r3, r3, #2
|
|
8006638: 4413 add r3, r2
|
|
800663a: 009b lsls r3, r3, #2
|
|
800663c: 440b add r3, r1
|
|
800663e: 331c adds r3, #28
|
|
8006640: 2200 movs r2, #0
|
|
8006642: 601a str r2, [r3, #0]
|
|
|
|
/* Free allocated memory */
|
|
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
|
|
8006644: 687b ldr r3, [r7, #4]
|
|
8006646: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800664a: 687b ldr r3, [r7, #4]
|
|
800664c: 32b0 adds r2, #176 @ 0xb0
|
|
800664e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8006652: 2b00 cmp r3, #0
|
|
8006654: d011 beq.n 800667a <USBD_HID_DeInit+0x82>
|
|
{
|
|
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
|
|
8006656: 687b ldr r3, [r7, #4]
|
|
8006658: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800665c: 687b ldr r3, [r7, #4]
|
|
800665e: 32b0 adds r2, #176 @ 0xb0
|
|
8006660: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8006664: 4618 mov r0, r3
|
|
8006666: f002 f92b bl 80088c0 <USBD_static_free>
|
|
pdev->pClassDataCmsit[pdev->classId] = NULL;
|
|
800666a: 687b ldr r3, [r7, #4]
|
|
800666c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8006670: 687b ldr r3, [r7, #4]
|
|
8006672: 32b0 adds r2, #176 @ 0xb0
|
|
8006674: 2100 movs r1, #0
|
|
8006676: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
800667a: 2300 movs r3, #0
|
|
}
|
|
800667c: 4618 mov r0, r3
|
|
800667e: 3708 adds r7, #8
|
|
8006680: 46bd mov sp, r7
|
|
8006682: bd80 pop {r7, pc}
|
|
8006684: 200000ca .word 0x200000ca
|
|
|
|
08006688 <USBD_HID_Setup>:
|
|
* @param pdev: instance
|
|
* @param req: usb requests
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8006688: b580 push {r7, lr}
|
|
800668a: b086 sub sp, #24
|
|
800668c: af00 add r7, sp, #0
|
|
800668e: 6078 str r0, [r7, #4]
|
|
8006690: 6039 str r1, [r7, #0]
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
8006692: 687b ldr r3, [r7, #4]
|
|
8006694: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8006698: 687b ldr r3, [r7, #4]
|
|
800669a: 32b0 adds r2, #176 @ 0xb0
|
|
800669c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80066a0: 60fb str r3, [r7, #12]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80066a2: 2300 movs r3, #0
|
|
80066a4: 75fb strb r3, [r7, #23]
|
|
uint16_t len;
|
|
uint8_t *pbuf;
|
|
uint16_t status_info = 0U;
|
|
80066a6: 2300 movs r3, #0
|
|
80066a8: 817b strh r3, [r7, #10]
|
|
|
|
if (hhid == NULL)
|
|
80066aa: 68fb ldr r3, [r7, #12]
|
|
80066ac: 2b00 cmp r3, #0
|
|
80066ae: d101 bne.n 80066b4 <USBD_HID_Setup+0x2c>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
80066b0: 2303 movs r3, #3
|
|
80066b2: e0e8 b.n 8006886 <USBD_HID_Setup+0x1fe>
|
|
}
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
80066b4: 683b ldr r3, [r7, #0]
|
|
80066b6: 781b ldrb r3, [r3, #0]
|
|
80066b8: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
80066bc: 2b00 cmp r3, #0
|
|
80066be: d046 beq.n 800674e <USBD_HID_Setup+0xc6>
|
|
80066c0: 2b20 cmp r3, #32
|
|
80066c2: f040 80d8 bne.w 8006876 <USBD_HID_Setup+0x1ee>
|
|
{
|
|
case USB_REQ_TYPE_CLASS :
|
|
switch (req->bRequest)
|
|
80066c6: 683b ldr r3, [r7, #0]
|
|
80066c8: 785b ldrb r3, [r3, #1]
|
|
80066ca: 3b02 subs r3, #2
|
|
80066cc: 2b09 cmp r3, #9
|
|
80066ce: d836 bhi.n 800673e <USBD_HID_Setup+0xb6>
|
|
80066d0: a201 add r2, pc, #4 @ (adr r2, 80066d8 <USBD_HID_Setup+0x50>)
|
|
80066d2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80066d6: bf00 nop
|
|
80066d8: 0800672f .word 0x0800672f
|
|
80066dc: 0800670f .word 0x0800670f
|
|
80066e0: 0800673f .word 0x0800673f
|
|
80066e4: 0800673f .word 0x0800673f
|
|
80066e8: 0800673f .word 0x0800673f
|
|
80066ec: 0800673f .word 0x0800673f
|
|
80066f0: 0800673f .word 0x0800673f
|
|
80066f4: 0800673f .word 0x0800673f
|
|
80066f8: 0800671d .word 0x0800671d
|
|
80066fc: 08006701 .word 0x08006701
|
|
{
|
|
case USBD_HID_REQ_SET_PROTOCOL:
|
|
hhid->Protocol = (uint8_t)(req->wValue);
|
|
8006700: 683b ldr r3, [r7, #0]
|
|
8006702: 885b ldrh r3, [r3, #2]
|
|
8006704: b2db uxtb r3, r3
|
|
8006706: 461a mov r2, r3
|
|
8006708: 68fb ldr r3, [r7, #12]
|
|
800670a: 601a str r2, [r3, #0]
|
|
break;
|
|
800670c: e01e b.n 800674c <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_GET_PROTOCOL:
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U);
|
|
800670e: 68fb ldr r3, [r7, #12]
|
|
8006710: 2201 movs r2, #1
|
|
8006712: 4619 mov r1, r3
|
|
8006714: 6878 ldr r0, [r7, #4]
|
|
8006716: f001 fbf5 bl 8007f04 <USBD_CtlSendData>
|
|
break;
|
|
800671a: e017 b.n 800674c <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_SET_IDLE:
|
|
hhid->IdleState = (uint8_t)(req->wValue >> 8);
|
|
800671c: 683b ldr r3, [r7, #0]
|
|
800671e: 885b ldrh r3, [r3, #2]
|
|
8006720: 0a1b lsrs r3, r3, #8
|
|
8006722: b29b uxth r3, r3
|
|
8006724: b2db uxtb r3, r3
|
|
8006726: 461a mov r2, r3
|
|
8006728: 68fb ldr r3, [r7, #12]
|
|
800672a: 605a str r2, [r3, #4]
|
|
break;
|
|
800672c: e00e b.n 800674c <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_GET_IDLE:
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U);
|
|
800672e: 68fb ldr r3, [r7, #12]
|
|
8006730: 3304 adds r3, #4
|
|
8006732: 2201 movs r2, #1
|
|
8006734: 4619 mov r1, r3
|
|
8006736: 6878 ldr r0, [r7, #4]
|
|
8006738: f001 fbe4 bl 8007f04 <USBD_CtlSendData>
|
|
break;
|
|
800673c: e006 b.n 800674c <USBD_HID_Setup+0xc4>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800673e: 6839 ldr r1, [r7, #0]
|
|
8006740: 6878 ldr r0, [r7, #4]
|
|
8006742: f001 fb62 bl 8007e0a <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8006746: 2303 movs r3, #3
|
|
8006748: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800674a: bf00 nop
|
|
}
|
|
break;
|
|
800674c: e09a b.n 8006884 <USBD_HID_Setup+0x1fc>
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
800674e: 683b ldr r3, [r7, #0]
|
|
8006750: 785b ldrb r3, [r3, #1]
|
|
8006752: 2b0b cmp r3, #11
|
|
8006754: f200 8086 bhi.w 8006864 <USBD_HID_Setup+0x1dc>
|
|
8006758: a201 add r2, pc, #4 @ (adr r2, 8006760 <USBD_HID_Setup+0xd8>)
|
|
800675a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800675e: bf00 nop
|
|
8006760: 08006791 .word 0x08006791
|
|
8006764: 08006873 .word 0x08006873
|
|
8006768: 08006865 .word 0x08006865
|
|
800676c: 08006865 .word 0x08006865
|
|
8006770: 08006865 .word 0x08006865
|
|
8006774: 08006865 .word 0x08006865
|
|
8006778: 080067bb .word 0x080067bb
|
|
800677c: 08006865 .word 0x08006865
|
|
8006780: 08006865 .word 0x08006865
|
|
8006784: 08006865 .word 0x08006865
|
|
8006788: 08006813 .word 0x08006813
|
|
800678c: 0800683d .word 0x0800683d
|
|
{
|
|
case USB_REQ_GET_STATUS:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8006790: 687b ldr r3, [r7, #4]
|
|
8006792: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8006796: b2db uxtb r3, r3
|
|
8006798: 2b03 cmp r3, #3
|
|
800679a: d107 bne.n 80067ac <USBD_HID_Setup+0x124>
|
|
{
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
|
|
800679c: f107 030a add.w r3, r7, #10
|
|
80067a0: 2202 movs r2, #2
|
|
80067a2: 4619 mov r1, r3
|
|
80067a4: 6878 ldr r0, [r7, #4]
|
|
80067a6: f001 fbad bl 8007f04 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
80067aa: e063 b.n 8006874 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
80067ac: 6839 ldr r1, [r7, #0]
|
|
80067ae: 6878 ldr r0, [r7, #4]
|
|
80067b0: f001 fb2b bl 8007e0a <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
80067b4: 2303 movs r3, #3
|
|
80067b6: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80067b8: e05c b.n 8006874 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
if ((req->wValue >> 8) == HID_REPORT_DESC)
|
|
80067ba: 683b ldr r3, [r7, #0]
|
|
80067bc: 885b ldrh r3, [r3, #2]
|
|
80067be: 0a1b lsrs r3, r3, #8
|
|
80067c0: b29b uxth r3, r3
|
|
80067c2: 2b22 cmp r3, #34 @ 0x22
|
|
80067c4: d108 bne.n 80067d8 <USBD_HID_Setup+0x150>
|
|
{
|
|
len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength);
|
|
80067c6: 683b ldr r3, [r7, #0]
|
|
80067c8: 88db ldrh r3, [r3, #6]
|
|
80067ca: 2b4a cmp r3, #74 @ 0x4a
|
|
80067cc: bf28 it cs
|
|
80067ce: 234a movcs r3, #74 @ 0x4a
|
|
80067d0: 82bb strh r3, [r7, #20]
|
|
pbuf = HID_MOUSE_ReportDesc;
|
|
80067d2: 4b2f ldr r3, [pc, #188] @ (8006890 <USBD_HID_Setup+0x208>)
|
|
80067d4: 613b str r3, [r7, #16]
|
|
80067d6: e015 b.n 8006804 <USBD_HID_Setup+0x17c>
|
|
}
|
|
else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE)
|
|
80067d8: 683b ldr r3, [r7, #0]
|
|
80067da: 885b ldrh r3, [r3, #2]
|
|
80067dc: 0a1b lsrs r3, r3, #8
|
|
80067de: b29b uxth r3, r3
|
|
80067e0: 2b21 cmp r3, #33 @ 0x21
|
|
80067e2: d108 bne.n 80067f6 <USBD_HID_Setup+0x16e>
|
|
{
|
|
pbuf = USBD_HID_Desc;
|
|
80067e4: 4b2b ldr r3, [pc, #172] @ (8006894 <USBD_HID_Setup+0x20c>)
|
|
80067e6: 613b str r3, [r7, #16]
|
|
len = MIN(USB_HID_DESC_SIZ, req->wLength);
|
|
80067e8: 683b ldr r3, [r7, #0]
|
|
80067ea: 88db ldrh r3, [r3, #6]
|
|
80067ec: 2b09 cmp r3, #9
|
|
80067ee: bf28 it cs
|
|
80067f0: 2309 movcs r3, #9
|
|
80067f2: 82bb strh r3, [r7, #20]
|
|
80067f4: e006 b.n 8006804 <USBD_HID_Setup+0x17c>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80067f6: 6839 ldr r1, [r7, #0]
|
|
80067f8: 6878 ldr r0, [r7, #4]
|
|
80067fa: f001 fb06 bl 8007e0a <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
80067fe: 2303 movs r3, #3
|
|
8006800: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8006802: e037 b.n 8006874 <USBD_HID_Setup+0x1ec>
|
|
}
|
|
(void)USBD_CtlSendData(pdev, pbuf, len);
|
|
8006804: 8abb ldrh r3, [r7, #20]
|
|
8006806: 461a mov r2, r3
|
|
8006808: 6939 ldr r1, [r7, #16]
|
|
800680a: 6878 ldr r0, [r7, #4]
|
|
800680c: f001 fb7a bl 8007f04 <USBD_CtlSendData>
|
|
break;
|
|
8006810: e030 b.n 8006874 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_GET_INTERFACE :
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8006812: 687b ldr r3, [r7, #4]
|
|
8006814: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8006818: b2db uxtb r3, r3
|
|
800681a: 2b03 cmp r3, #3
|
|
800681c: d107 bne.n 800682e <USBD_HID_Setup+0x1a6>
|
|
{
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U);
|
|
800681e: 68fb ldr r3, [r7, #12]
|
|
8006820: 3308 adds r3, #8
|
|
8006822: 2201 movs r2, #1
|
|
8006824: 4619 mov r1, r3
|
|
8006826: 6878 ldr r0, [r7, #4]
|
|
8006828: f001 fb6c bl 8007f04 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
800682c: e022 b.n 8006874 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
800682e: 6839 ldr r1, [r7, #0]
|
|
8006830: 6878 ldr r0, [r7, #4]
|
|
8006832: f001 faea bl 8007e0a <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8006836: 2303 movs r3, #3
|
|
8006838: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800683a: e01b b.n 8006874 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_SET_INTERFACE:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
800683c: 687b ldr r3, [r7, #4]
|
|
800683e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8006842: b2db uxtb r3, r3
|
|
8006844: 2b03 cmp r3, #3
|
|
8006846: d106 bne.n 8006856 <USBD_HID_Setup+0x1ce>
|
|
{
|
|
hhid->AltSetting = (uint8_t)(req->wValue);
|
|
8006848: 683b ldr r3, [r7, #0]
|
|
800684a: 885b ldrh r3, [r3, #2]
|
|
800684c: b2db uxtb r3, r3
|
|
800684e: 461a mov r2, r3
|
|
8006850: 68fb ldr r3, [r7, #12]
|
|
8006852: 609a str r2, [r3, #8]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
8006854: e00e b.n 8006874 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
8006856: 6839 ldr r1, [r7, #0]
|
|
8006858: 6878 ldr r0, [r7, #4]
|
|
800685a: f001 fad6 bl 8007e0a <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
800685e: 2303 movs r3, #3
|
|
8006860: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8006862: e007 b.n 8006874 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
break;
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8006864: 6839 ldr r1, [r7, #0]
|
|
8006866: 6878 ldr r0, [r7, #4]
|
|
8006868: f001 facf bl 8007e0a <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
800686c: 2303 movs r3, #3
|
|
800686e: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8006870: e000 b.n 8006874 <USBD_HID_Setup+0x1ec>
|
|
break;
|
|
8006872: bf00 nop
|
|
}
|
|
break;
|
|
8006874: e006 b.n 8006884 <USBD_HID_Setup+0x1fc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8006876: 6839 ldr r1, [r7, #0]
|
|
8006878: 6878 ldr r0, [r7, #4]
|
|
800687a: f001 fac6 bl 8007e0a <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
800687e: 2303 movs r3, #3
|
|
8006880: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8006882: bf00 nop
|
|
}
|
|
|
|
return (uint8_t)ret;
|
|
8006884: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8006886: 4618 mov r0, r3
|
|
8006888: 3718 adds r7, #24
|
|
800688a: 46bd mov sp, r7
|
|
800688c: bd80 pop {r7, pc}
|
|
800688e: bf00 nop
|
|
8006890: 20000080 .word 0x20000080
|
|
8006894: 20000068 .word 0x20000068
|
|
|
|
08006898 <USBD_HID_GetFSCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length)
|
|
{
|
|
8006898: b580 push {r7, lr}
|
|
800689a: b084 sub sp, #16
|
|
800689c: af00 add r7, sp, #0
|
|
800689e: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
80068a0: 2181 movs r1, #129 @ 0x81
|
|
80068a2: 4809 ldr r0, [pc, #36] @ (80068c8 <USBD_HID_GetFSCfgDesc+0x30>)
|
|
80068a4: f000 fc4e bl 8007144 <USBD_GetEpDesc>
|
|
80068a8: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
80068aa: 68fb ldr r3, [r7, #12]
|
|
80068ac: 2b00 cmp r3, #0
|
|
80068ae: d002 beq.n 80068b6 <USBD_HID_GetFSCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_FS_BINTERVAL;
|
|
80068b0: 68fb ldr r3, [r7, #12]
|
|
80068b2: 220a movs r2, #10
|
|
80068b4: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
80068b6: 687b ldr r3, [r7, #4]
|
|
80068b8: 2222 movs r2, #34 @ 0x22
|
|
80068ba: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
80068bc: 4b02 ldr r3, [pc, #8] @ (80068c8 <USBD_HID_GetFSCfgDesc+0x30>)
|
|
}
|
|
80068be: 4618 mov r0, r3
|
|
80068c0: 3710 adds r7, #16
|
|
80068c2: 46bd mov sp, r7
|
|
80068c4: bd80 pop {r7, pc}
|
|
80068c6: bf00 nop
|
|
80068c8: 20000044 .word 0x20000044
|
|
|
|
080068cc <USBD_HID_GetHSCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length)
|
|
{
|
|
80068cc: b580 push {r7, lr}
|
|
80068ce: b084 sub sp, #16
|
|
80068d0: af00 add r7, sp, #0
|
|
80068d2: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
80068d4: 2181 movs r1, #129 @ 0x81
|
|
80068d6: 4809 ldr r0, [pc, #36] @ (80068fc <USBD_HID_GetHSCfgDesc+0x30>)
|
|
80068d8: f000 fc34 bl 8007144 <USBD_GetEpDesc>
|
|
80068dc: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
80068de: 68fb ldr r3, [r7, #12]
|
|
80068e0: 2b00 cmp r3, #0
|
|
80068e2: d002 beq.n 80068ea <USBD_HID_GetHSCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_HS_BINTERVAL;
|
|
80068e4: 68fb ldr r3, [r7, #12]
|
|
80068e6: 2207 movs r2, #7
|
|
80068e8: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
80068ea: 687b ldr r3, [r7, #4]
|
|
80068ec: 2222 movs r2, #34 @ 0x22
|
|
80068ee: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
80068f0: 4b02 ldr r3, [pc, #8] @ (80068fc <USBD_HID_GetHSCfgDesc+0x30>)
|
|
}
|
|
80068f2: 4618 mov r0, r3
|
|
80068f4: 3710 adds r7, #16
|
|
80068f6: 46bd mov sp, r7
|
|
80068f8: bd80 pop {r7, pc}
|
|
80068fa: bf00 nop
|
|
80068fc: 20000044 .word 0x20000044
|
|
|
|
08006900 <USBD_HID_GetOtherSpeedCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length)
|
|
{
|
|
8006900: b580 push {r7, lr}
|
|
8006902: b084 sub sp, #16
|
|
8006904: af00 add r7, sp, #0
|
|
8006906: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
8006908: 2181 movs r1, #129 @ 0x81
|
|
800690a: 4809 ldr r0, [pc, #36] @ (8006930 <USBD_HID_GetOtherSpeedCfgDesc+0x30>)
|
|
800690c: f000 fc1a bl 8007144 <USBD_GetEpDesc>
|
|
8006910: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
8006912: 68fb ldr r3, [r7, #12]
|
|
8006914: 2b00 cmp r3, #0
|
|
8006916: d002 beq.n 800691e <USBD_HID_GetOtherSpeedCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_FS_BINTERVAL;
|
|
8006918: 68fb ldr r3, [r7, #12]
|
|
800691a: 220a movs r2, #10
|
|
800691c: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
800691e: 687b ldr r3, [r7, #4]
|
|
8006920: 2222 movs r2, #34 @ 0x22
|
|
8006922: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
8006924: 4b02 ldr r3, [pc, #8] @ (8006930 <USBD_HID_GetOtherSpeedCfgDesc+0x30>)
|
|
}
|
|
8006926: 4618 mov r0, r3
|
|
8006928: 3710 adds r7, #16
|
|
800692a: 46bd mov sp, r7
|
|
800692c: bd80 pop {r7, pc}
|
|
800692e: bf00 nop
|
|
8006930: 20000044 .word 0x20000044
|
|
|
|
08006934 <USBD_HID_DataIn>:
|
|
* @param pdev: device instance
|
|
* @param epnum: endpoint index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
|
|
{
|
|
8006934: b480 push {r7}
|
|
8006936: b083 sub sp, #12
|
|
8006938: af00 add r7, sp, #0
|
|
800693a: 6078 str r0, [r7, #4]
|
|
800693c: 460b mov r3, r1
|
|
800693e: 70fb strb r3, [r7, #3]
|
|
UNUSED(epnum);
|
|
/* Ensure that the FIFO is empty before a new transfer, this condition could
|
|
be caused by a new transfer before the end of the previous transfer */
|
|
((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE;
|
|
8006940: 687b ldr r3, [r7, #4]
|
|
8006942: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8006946: 687b ldr r3, [r7, #4]
|
|
8006948: 32b0 adds r2, #176 @ 0xb0
|
|
800694a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800694e: 2200 movs r2, #0
|
|
8006950: 731a strb r2, [r3, #12]
|
|
|
|
return (uint8_t)USBD_OK;
|
|
8006952: 2300 movs r3, #0
|
|
}
|
|
8006954: 4618 mov r0, r3
|
|
8006956: 370c adds r7, #12
|
|
8006958: 46bd mov sp, r7
|
|
800695a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800695e: 4770 bx lr
|
|
|
|
08006960 <USBD_HID_GetDeviceQualifierDesc>:
|
|
* return Device Qualifier descriptor
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length)
|
|
{
|
|
8006960: b480 push {r7}
|
|
8006962: b083 sub sp, #12
|
|
8006964: af00 add r7, sp, #0
|
|
8006966: 6078 str r0, [r7, #4]
|
|
*length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc);
|
|
8006968: 687b ldr r3, [r7, #4]
|
|
800696a: 220a movs r2, #10
|
|
800696c: 801a strh r2, [r3, #0]
|
|
|
|
return USBD_HID_DeviceQualifierDesc;
|
|
800696e: 4b03 ldr r3, [pc, #12] @ (800697c <USBD_HID_GetDeviceQualifierDesc+0x1c>)
|
|
}
|
|
8006970: 4618 mov r0, r3
|
|
8006972: 370c adds r7, #12
|
|
8006974: 46bd mov sp, r7
|
|
8006976: f85d 7b04 ldr.w r7, [sp], #4
|
|
800697a: 4770 bx lr
|
|
800697c: 20000074 .word 0x20000074
|
|
|
|
08006980 <USBD_Init>:
|
|
* @param id: Low level core index
|
|
* @retval status: USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
|
|
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
|
|
{
|
|
8006980: b580 push {r7, lr}
|
|
8006982: b086 sub sp, #24
|
|
8006984: af00 add r7, sp, #0
|
|
8006986: 60f8 str r0, [r7, #12]
|
|
8006988: 60b9 str r1, [r7, #8]
|
|
800698a: 4613 mov r3, r2
|
|
800698c: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef ret;
|
|
|
|
/* Check whether the USB Host handle is valid */
|
|
if (pdev == NULL)
|
|
800698e: 68fb ldr r3, [r7, #12]
|
|
8006990: 2b00 cmp r3, #0
|
|
8006992: d101 bne.n 8006998 <USBD_Init+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Device handle");
|
|
#endif /* (USBD_DEBUG_LEVEL > 1U) */
|
|
return USBD_FAIL;
|
|
8006994: 2303 movs r3, #3
|
|
8006996: e01f b.n 80069d8 <USBD_Init+0x58>
|
|
pdev->NumClasses = 0;
|
|
pdev->classId = 0;
|
|
}
|
|
#else
|
|
/* Unlink previous class*/
|
|
pdev->pClass[0] = NULL;
|
|
8006998: 68fb ldr r3, [r7, #12]
|
|
800699a: 2200 movs r2, #0
|
|
800699c: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
pdev->pUserData[0] = NULL;
|
|
80069a0: 68fb ldr r3, [r7, #12]
|
|
80069a2: 2200 movs r2, #0
|
|
80069a4: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
pdev->pConfDesc = NULL;
|
|
80069a8: 68fb ldr r3, [r7, #12]
|
|
80069aa: 2200 movs r2, #0
|
|
80069ac: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
|
|
/* Assign USBD Descriptors */
|
|
if (pdesc != NULL)
|
|
80069b0: 68bb ldr r3, [r7, #8]
|
|
80069b2: 2b00 cmp r3, #0
|
|
80069b4: d003 beq.n 80069be <USBD_Init+0x3e>
|
|
{
|
|
pdev->pDesc = pdesc;
|
|
80069b6: 68fb ldr r3, [r7, #12]
|
|
80069b8: 68ba ldr r2, [r7, #8]
|
|
80069ba: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
|
|
}
|
|
|
|
/* Set Device initial State */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
80069be: 68fb ldr r3, [r7, #12]
|
|
80069c0: 2201 movs r2, #1
|
|
80069c2: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->id = id;
|
|
80069c6: 68fb ldr r3, [r7, #12]
|
|
80069c8: 79fa ldrb r2, [r7, #7]
|
|
80069ca: 701a strb r2, [r3, #0]
|
|
|
|
/* Initialize low level driver */
|
|
ret = USBD_LL_Init(pdev);
|
|
80069cc: 68f8 ldr r0, [r7, #12]
|
|
80069ce: f001 fda3 bl 8008518 <USBD_LL_Init>
|
|
80069d2: 4603 mov r3, r0
|
|
80069d4: 75fb strb r3, [r7, #23]
|
|
|
|
return ret;
|
|
80069d6: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80069d8: 4618 mov r0, r3
|
|
80069da: 3718 adds r7, #24
|
|
80069dc: 46bd mov sp, r7
|
|
80069de: bd80 pop {r7, pc}
|
|
|
|
080069e0 <USBD_RegisterClass>:
|
|
* @param pdev: Device Handle
|
|
* @param pclass: Class handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
|
|
{
|
|
80069e0: b580 push {r7, lr}
|
|
80069e2: b084 sub sp, #16
|
|
80069e4: af00 add r7, sp, #0
|
|
80069e6: 6078 str r0, [r7, #4]
|
|
80069e8: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
80069ea: 2300 movs r3, #0
|
|
80069ec: 81fb strh r3, [r7, #14]
|
|
|
|
if (pclass == NULL)
|
|
80069ee: 683b ldr r3, [r7, #0]
|
|
80069f0: 2b00 cmp r3, #0
|
|
80069f2: d101 bne.n 80069f8 <USBD_RegisterClass+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Class handle");
|
|
#endif /* (USBD_DEBUG_LEVEL > 1U) */
|
|
return USBD_FAIL;
|
|
80069f4: 2303 movs r3, #3
|
|
80069f6: e025 b.n 8006a44 <USBD_RegisterClass+0x64>
|
|
}
|
|
|
|
/* link the class to the USB Device handle */
|
|
pdev->pClass[0] = pclass;
|
|
80069f8: 687b ldr r3, [r7, #4]
|
|
80069fa: 683a ldr r2, [r7, #0]
|
|
80069fc: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL)
|
|
{
|
|
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len);
|
|
}
|
|
#else /* Default USE_USB_FS */
|
|
if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL)
|
|
8006a00: 687b ldr r3, [r7, #4]
|
|
8006a02: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8006a06: 687b ldr r3, [r7, #4]
|
|
8006a08: 32ae adds r2, #174 @ 0xae
|
|
8006a0a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8006a0e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006a10: 2b00 cmp r3, #0
|
|
8006a12: d00f beq.n 8006a34 <USBD_RegisterClass+0x54>
|
|
{
|
|
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len);
|
|
8006a14: 687b ldr r3, [r7, #4]
|
|
8006a16: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8006a1a: 687b ldr r3, [r7, #4]
|
|
8006a1c: 32ae adds r2, #174 @ 0xae
|
|
8006a1e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8006a22: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006a24: f107 020e add.w r2, r7, #14
|
|
8006a28: 4610 mov r0, r2
|
|
8006a2a: 4798 blx r3
|
|
8006a2c: 4602 mov r2, r0
|
|
8006a2e: 687b ldr r3, [r7, #4]
|
|
8006a30: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
}
|
|
#endif /* USE_USB_FS */
|
|
|
|
/* Increment the NumClasses */
|
|
pdev->NumClasses++;
|
|
8006a34: 687b ldr r3, [r7, #4]
|
|
8006a36: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
8006a3a: 1c5a adds r2, r3, #1
|
|
8006a3c: 687b ldr r3, [r7, #4]
|
|
8006a3e: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8
|
|
|
|
return USBD_OK;
|
|
8006a42: 2300 movs r3, #0
|
|
}
|
|
8006a44: 4618 mov r0, r3
|
|
8006a46: 3710 adds r7, #16
|
|
8006a48: 46bd mov sp, r7
|
|
8006a4a: bd80 pop {r7, pc}
|
|
|
|
08006a4c <USBD_Start>:
|
|
* Start the USB Device Core.
|
|
* @param pdev: Device Handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8006a4c: b580 push {r7, lr}
|
|
8006a4e: b082 sub sp, #8
|
|
8006a50: af00 add r7, sp, #0
|
|
8006a52: 6078 str r0, [r7, #4]
|
|
#ifdef USE_USBD_COMPOSITE
|
|
pdev->classId = 0U;
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Start the low level driver */
|
|
return USBD_LL_Start(pdev);
|
|
8006a54: 6878 ldr r0, [r7, #4]
|
|
8006a56: f001 fdab bl 80085b0 <USBD_LL_Start>
|
|
8006a5a: 4603 mov r3, r0
|
|
}
|
|
8006a5c: 4618 mov r0, r3
|
|
8006a5e: 3708 adds r7, #8
|
|
8006a60: 46bd mov sp, r7
|
|
8006a62: bd80 pop {r7, pc}
|
|
|
|
08006a64 <USBD_RunTestMode>:
|
|
* Launch test mode process
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8006a64: b480 push {r7}
|
|
8006a66: b083 sub sp, #12
|
|
8006a68: af00 add r7, sp, #0
|
|
8006a6a: 6078 str r0, [r7, #4]
|
|
return ret;
|
|
#else
|
|
/* Prevent unused argument compilation warning */
|
|
UNUSED(pdev);
|
|
|
|
return USBD_OK;
|
|
8006a6c: 2300 movs r3, #0
|
|
#endif /* USBD_HS_TESTMODE_ENABLE */
|
|
}
|
|
8006a6e: 4618 mov r0, r3
|
|
8006a70: 370c adds r7, #12
|
|
8006a72: 46bd mov sp, r7
|
|
8006a74: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006a78: 4770 bx lr
|
|
|
|
08006a7a <USBD_SetClassConfig>:
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
|
|
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8006a7a: b580 push {r7, lr}
|
|
8006a7c: b084 sub sp, #16
|
|
8006a7e: af00 add r7, sp, #0
|
|
8006a80: 6078 str r0, [r7, #4]
|
|
8006a82: 460b mov r3, r1
|
|
8006a84: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8006a86: 2300 movs r3, #0
|
|
8006a88: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
8006a8a: 687b ldr r3, [r7, #4]
|
|
8006a8c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8006a90: 2b00 cmp r3, #0
|
|
8006a92: d009 beq.n 8006aa8 <USBD_SetClassConfig+0x2e>
|
|
{
|
|
/* Set configuration and Start the Class */
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx);
|
|
8006a94: 687b ldr r3, [r7, #4]
|
|
8006a96: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8006a9a: 681b ldr r3, [r3, #0]
|
|
8006a9c: 78fa ldrb r2, [r7, #3]
|
|
8006a9e: 4611 mov r1, r2
|
|
8006aa0: 6878 ldr r0, [r7, #4]
|
|
8006aa2: 4798 blx r3
|
|
8006aa4: 4603 mov r3, r0
|
|
8006aa6: 73fb strb r3, [r7, #15]
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8006aa8: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8006aaa: 4618 mov r0, r3
|
|
8006aac: 3710 adds r7, #16
|
|
8006aae: 46bd mov sp, r7
|
|
8006ab0: bd80 pop {r7, pc}
|
|
|
|
08006ab2 <USBD_ClrClassConfig>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8006ab2: b580 push {r7, lr}
|
|
8006ab4: b084 sub sp, #16
|
|
8006ab6: af00 add r7, sp, #0
|
|
8006ab8: 6078 str r0, [r7, #4]
|
|
8006aba: 460b mov r3, r1
|
|
8006abc: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8006abe: 2300 movs r3, #0
|
|
8006ac0: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
/* Clear configuration and De-initialize the Class process */
|
|
if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U)
|
|
8006ac2: 687b ldr r3, [r7, #4]
|
|
8006ac4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8006ac8: 685b ldr r3, [r3, #4]
|
|
8006aca: 78fa ldrb r2, [r7, #3]
|
|
8006acc: 4611 mov r1, r2
|
|
8006ace: 6878 ldr r0, [r7, #4]
|
|
8006ad0: 4798 blx r3
|
|
8006ad2: 4603 mov r3, r0
|
|
8006ad4: 2b00 cmp r3, #0
|
|
8006ad6: d001 beq.n 8006adc <USBD_ClrClassConfig+0x2a>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8006ad8: 2303 movs r3, #3
|
|
8006ada: 73fb strb r3, [r7, #15]
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8006adc: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8006ade: 4618 mov r0, r3
|
|
8006ae0: 3710 adds r7, #16
|
|
8006ae2: 46bd mov sp, r7
|
|
8006ae4: bd80 pop {r7, pc}
|
|
|
|
08006ae6 <USBD_LL_SetupStage>:
|
|
* @param pdev: device instance
|
|
* @param psetup: setup packet buffer pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
|
|
{
|
|
8006ae6: b580 push {r7, lr}
|
|
8006ae8: b084 sub sp, #16
|
|
8006aea: af00 add r7, sp, #0
|
|
8006aec: 6078 str r0, [r7, #4]
|
|
8006aee: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret;
|
|
|
|
USBD_ParseSetupRequest(&pdev->request, psetup);
|
|
8006af0: 687b ldr r3, [r7, #4]
|
|
8006af2: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8006af6: 6839 ldr r1, [r7, #0]
|
|
8006af8: 4618 mov r0, r3
|
|
8006afa: f001 f94c bl 8007d96 <USBD_ParseSetupRequest>
|
|
|
|
pdev->ep0_state = USBD_EP0_SETUP;
|
|
8006afe: 687b ldr r3, [r7, #4]
|
|
8006b00: 2201 movs r2, #1
|
|
8006b02: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
pdev->ep0_data_len = pdev->request.wLength;
|
|
8006b06: 687b ldr r3, [r7, #4]
|
|
8006b08: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0
|
|
8006b0c: 461a mov r2, r3
|
|
8006b0e: 687b ldr r3, [r7, #4]
|
|
8006b10: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
8006b14: 687b ldr r3, [r7, #4]
|
|
8006b16: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8006b1a: f003 031f and.w r3, r3, #31
|
|
8006b1e: 2b02 cmp r3, #2
|
|
8006b20: d01a beq.n 8006b58 <USBD_LL_SetupStage+0x72>
|
|
8006b22: 2b02 cmp r3, #2
|
|
8006b24: d822 bhi.n 8006b6c <USBD_LL_SetupStage+0x86>
|
|
8006b26: 2b00 cmp r3, #0
|
|
8006b28: d002 beq.n 8006b30 <USBD_LL_SetupStage+0x4a>
|
|
8006b2a: 2b01 cmp r3, #1
|
|
8006b2c: d00a beq.n 8006b44 <USBD_LL_SetupStage+0x5e>
|
|
8006b2e: e01d b.n 8006b6c <USBD_LL_SetupStage+0x86>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
ret = USBD_StdDevReq(pdev, &pdev->request);
|
|
8006b30: 687b ldr r3, [r7, #4]
|
|
8006b32: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8006b36: 4619 mov r1, r3
|
|
8006b38: 6878 ldr r0, [r7, #4]
|
|
8006b3a: f000 fb77 bl 800722c <USBD_StdDevReq>
|
|
8006b3e: 4603 mov r3, r0
|
|
8006b40: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8006b42: e020 b.n 8006b86 <USBD_LL_SetupStage+0xa0>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
ret = USBD_StdItfReq(pdev, &pdev->request);
|
|
8006b44: 687b ldr r3, [r7, #4]
|
|
8006b46: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8006b4a: 4619 mov r1, r3
|
|
8006b4c: 6878 ldr r0, [r7, #4]
|
|
8006b4e: f000 fbdf bl 8007310 <USBD_StdItfReq>
|
|
8006b52: 4603 mov r3, r0
|
|
8006b54: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8006b56: e016 b.n 8006b86 <USBD_LL_SetupStage+0xa0>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
ret = USBD_StdEPReq(pdev, &pdev->request);
|
|
8006b58: 687b ldr r3, [r7, #4]
|
|
8006b5a: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8006b5e: 4619 mov r1, r3
|
|
8006b60: 6878 ldr r0, [r7, #4]
|
|
8006b62: f000 fc41 bl 80073e8 <USBD_StdEPReq>
|
|
8006b66: 4603 mov r3, r0
|
|
8006b68: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8006b6a: e00c b.n 8006b86 <USBD_LL_SetupStage+0xa0>
|
|
|
|
default:
|
|
ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
|
|
8006b6c: 687b ldr r3, [r7, #4]
|
|
8006b6e: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8006b72: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
8006b76: b2db uxtb r3, r3
|
|
8006b78: 4619 mov r1, r3
|
|
8006b7a: 6878 ldr r0, [r7, #4]
|
|
8006b7c: f001 fd78 bl 8008670 <USBD_LL_StallEP>
|
|
8006b80: 4603 mov r3, r0
|
|
8006b82: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8006b84: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8006b86: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8006b88: 4618 mov r0, r3
|
|
8006b8a: 3710 adds r7, #16
|
|
8006b8c: 46bd mov sp, r7
|
|
8006b8e: bd80 pop {r7, pc}
|
|
|
|
08006b90 <USBD_LL_DataOutStage>:
|
|
* @param pdata: data pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
8006b90: b580 push {r7, lr}
|
|
8006b92: b086 sub sp, #24
|
|
8006b94: af00 add r7, sp, #0
|
|
8006b96: 60f8 str r0, [r7, #12]
|
|
8006b98: 460b mov r3, r1
|
|
8006b9a: 607a str r2, [r7, #4]
|
|
8006b9c: 72fb strb r3, [r7, #11]
|
|
USBD_EndpointTypeDef *pep;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8006b9e: 2300 movs r3, #0
|
|
8006ba0: 75fb strb r3, [r7, #23]
|
|
uint8_t idx;
|
|
|
|
UNUSED(pdata);
|
|
|
|
if (epnum == 0U)
|
|
8006ba2: 7afb ldrb r3, [r7, #11]
|
|
8006ba4: 2b00 cmp r3, #0
|
|
8006ba6: d177 bne.n 8006c98 <USBD_LL_DataOutStage+0x108>
|
|
{
|
|
pep = &pdev->ep_out[0];
|
|
8006ba8: 68fb ldr r3, [r7, #12]
|
|
8006baa: f503 73aa add.w r3, r3, #340 @ 0x154
|
|
8006bae: 613b str r3, [r7, #16]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
|
|
8006bb0: 68fb ldr r3, [r7, #12]
|
|
8006bb2: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
8006bb6: 2b03 cmp r3, #3
|
|
8006bb8: f040 80a1 bne.w 8006cfe <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
8006bbc: 693b ldr r3, [r7, #16]
|
|
8006bbe: 685b ldr r3, [r3, #4]
|
|
8006bc0: 693a ldr r2, [r7, #16]
|
|
8006bc2: 8992 ldrh r2, [r2, #12]
|
|
8006bc4: 4293 cmp r3, r2
|
|
8006bc6: d91c bls.n 8006c02 <USBD_LL_DataOutStage+0x72>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
8006bc8: 693b ldr r3, [r7, #16]
|
|
8006bca: 685b ldr r3, [r3, #4]
|
|
8006bcc: 693a ldr r2, [r7, #16]
|
|
8006bce: 8992 ldrh r2, [r2, #12]
|
|
8006bd0: 1a9a subs r2, r3, r2
|
|
8006bd2: 693b ldr r3, [r7, #16]
|
|
8006bd4: 605a str r2, [r3, #4]
|
|
pep->pbuffer += pep->maxpacket;
|
|
8006bd6: 693b ldr r3, [r7, #16]
|
|
8006bd8: 691b ldr r3, [r3, #16]
|
|
8006bda: 693a ldr r2, [r7, #16]
|
|
8006bdc: 8992 ldrh r2, [r2, #12]
|
|
8006bde: 441a add r2, r3
|
|
8006be0: 693b ldr r3, [r7, #16]
|
|
8006be2: 611a str r2, [r3, #16]
|
|
|
|
(void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket));
|
|
8006be4: 693b ldr r3, [r7, #16]
|
|
8006be6: 6919 ldr r1, [r3, #16]
|
|
8006be8: 693b ldr r3, [r7, #16]
|
|
8006bea: 899b ldrh r3, [r3, #12]
|
|
8006bec: 461a mov r2, r3
|
|
8006bee: 693b ldr r3, [r7, #16]
|
|
8006bf0: 685b ldr r3, [r3, #4]
|
|
8006bf2: 4293 cmp r3, r2
|
|
8006bf4: bf38 it cc
|
|
8006bf6: 4613 movcc r3, r2
|
|
8006bf8: 461a mov r2, r3
|
|
8006bfa: 68f8 ldr r0, [r7, #12]
|
|
8006bfc: f001 f9b1 bl 8007f62 <USBD_CtlContinueRx>
|
|
8006c00: e07d b.n 8006cfe <USBD_LL_DataOutStage+0x16e>
|
|
}
|
|
else
|
|
{
|
|
/* Find the class ID relative to the current request */
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
8006c02: 68fb ldr r3, [r7, #12]
|
|
8006c04: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8006c08: f003 031f and.w r3, r3, #31
|
|
8006c0c: 2b02 cmp r3, #2
|
|
8006c0e: d014 beq.n 8006c3a <USBD_LL_DataOutStage+0xaa>
|
|
8006c10: 2b02 cmp r3, #2
|
|
8006c12: d81d bhi.n 8006c50 <USBD_LL_DataOutStage+0xc0>
|
|
8006c14: 2b00 cmp r3, #0
|
|
8006c16: d002 beq.n 8006c1e <USBD_LL_DataOutStage+0x8e>
|
|
8006c18: 2b01 cmp r3, #1
|
|
8006c1a: d003 beq.n 8006c24 <USBD_LL_DataOutStage+0x94>
|
|
8006c1c: e018 b.n 8006c50 <USBD_LL_DataOutStage+0xc0>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
/* Device requests must be managed by the first instantiated class
|
|
(or duplicated by all classes for simplicity) */
|
|
idx = 0U;
|
|
8006c1e: 2300 movs r3, #0
|
|
8006c20: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8006c22: e018 b.n 8006c56 <USBD_LL_DataOutStage+0xc6>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex));
|
|
8006c24: 68fb ldr r3, [r7, #12]
|
|
8006c26: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
8006c2a: b2db uxtb r3, r3
|
|
8006c2c: 4619 mov r1, r3
|
|
8006c2e: 68f8 ldr r0, [r7, #12]
|
|
8006c30: f000 fa6e bl 8007110 <USBD_CoreFindIF>
|
|
8006c34: 4603 mov r3, r0
|
|
8006c36: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8006c38: e00d b.n 8006c56 <USBD_LL_DataOutStage+0xc6>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex));
|
|
8006c3a: 68fb ldr r3, [r7, #12]
|
|
8006c3c: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
8006c40: b2db uxtb r3, r3
|
|
8006c42: 4619 mov r1, r3
|
|
8006c44: 68f8 ldr r0, [r7, #12]
|
|
8006c46: f000 fa70 bl 800712a <USBD_CoreFindEP>
|
|
8006c4a: 4603 mov r3, r0
|
|
8006c4c: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8006c4e: e002 b.n 8006c56 <USBD_LL_DataOutStage+0xc6>
|
|
|
|
default:
|
|
/* Back to the first class in case of doubt */
|
|
idx = 0U;
|
|
8006c50: 2300 movs r3, #0
|
|
8006c52: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8006c54: bf00 nop
|
|
}
|
|
|
|
if (idx < USBD_MAX_SUPPORTED_CLASS)
|
|
8006c56: 7dbb ldrb r3, [r7, #22]
|
|
8006c58: 2b00 cmp r3, #0
|
|
8006c5a: d119 bne.n 8006c90 <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
/* Setup the class ID and route the request to the relative class function */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8006c5c: 68fb ldr r3, [r7, #12]
|
|
8006c5e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8006c62: b2db uxtb r3, r3
|
|
8006c64: 2b03 cmp r3, #3
|
|
8006c66: d113 bne.n 8006c90 <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
if (pdev->pClass[idx]->EP0_RxReady != NULL)
|
|
8006c68: 7dba ldrb r2, [r7, #22]
|
|
8006c6a: 68fb ldr r3, [r7, #12]
|
|
8006c6c: 32ae adds r2, #174 @ 0xae
|
|
8006c6e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8006c72: 691b ldr r3, [r3, #16]
|
|
8006c74: 2b00 cmp r3, #0
|
|
8006c76: d00b beq.n 8006c90 <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
pdev->classId = idx;
|
|
8006c78: 7dba ldrb r2, [r7, #22]
|
|
8006c7a: 68fb ldr r3, [r7, #12]
|
|
8006c7c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
pdev->pClass[idx]->EP0_RxReady(pdev);
|
|
8006c80: 7dba ldrb r2, [r7, #22]
|
|
8006c82: 68fb ldr r3, [r7, #12]
|
|
8006c84: 32ae adds r2, #174 @ 0xae
|
|
8006c86: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8006c8a: 691b ldr r3, [r3, #16]
|
|
8006c8c: 68f8 ldr r0, [r7, #12]
|
|
8006c8e: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8006c90: 68f8 ldr r0, [r7, #12]
|
|
8006c92: f001 f977 bl 8007f84 <USBD_CtlSendStatus>
|
|
8006c96: e032 b.n 8006cfe <USBD_LL_DataOutStage+0x16e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU));
|
|
8006c98: 7afb ldrb r3, [r7, #11]
|
|
8006c9a: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8006c9e: b2db uxtb r3, r3
|
|
8006ca0: 4619 mov r1, r3
|
|
8006ca2: 68f8 ldr r0, [r7, #12]
|
|
8006ca4: f000 fa41 bl 800712a <USBD_CoreFindEP>
|
|
8006ca8: 4603 mov r3, r0
|
|
8006caa: 75bb strb r3, [r7, #22]
|
|
|
|
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8006cac: 7dbb ldrb r3, [r7, #22]
|
|
8006cae: 2bff cmp r3, #255 @ 0xff
|
|
8006cb0: d025 beq.n 8006cfe <USBD_LL_DataOutStage+0x16e>
|
|
8006cb2: 7dbb ldrb r3, [r7, #22]
|
|
8006cb4: 2b00 cmp r3, #0
|
|
8006cb6: d122 bne.n 8006cfe <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8006cb8: 68fb ldr r3, [r7, #12]
|
|
8006cba: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8006cbe: b2db uxtb r3, r3
|
|
8006cc0: 2b03 cmp r3, #3
|
|
8006cc2: d117 bne.n 8006cf4 <USBD_LL_DataOutStage+0x164>
|
|
{
|
|
if (pdev->pClass[idx]->DataOut != NULL)
|
|
8006cc4: 7dba ldrb r2, [r7, #22]
|
|
8006cc6: 68fb ldr r3, [r7, #12]
|
|
8006cc8: 32ae adds r2, #174 @ 0xae
|
|
8006cca: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8006cce: 699b ldr r3, [r3, #24]
|
|
8006cd0: 2b00 cmp r3, #0
|
|
8006cd2: d00f beq.n 8006cf4 <USBD_LL_DataOutStage+0x164>
|
|
{
|
|
pdev->classId = idx;
|
|
8006cd4: 7dba ldrb r2, [r7, #22]
|
|
8006cd6: 68fb ldr r3, [r7, #12]
|
|
8006cd8: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum);
|
|
8006cdc: 7dba ldrb r2, [r7, #22]
|
|
8006cde: 68fb ldr r3, [r7, #12]
|
|
8006ce0: 32ae adds r2, #174 @ 0xae
|
|
8006ce2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8006ce6: 699b ldr r3, [r3, #24]
|
|
8006ce8: 7afa ldrb r2, [r7, #11]
|
|
8006cea: 4611 mov r1, r2
|
|
8006cec: 68f8 ldr r0, [r7, #12]
|
|
8006cee: 4798 blx r3
|
|
8006cf0: 4603 mov r3, r0
|
|
8006cf2: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
if (ret != USBD_OK)
|
|
8006cf4: 7dfb ldrb r3, [r7, #23]
|
|
8006cf6: 2b00 cmp r3, #0
|
|
8006cf8: d001 beq.n 8006cfe <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
return ret;
|
|
8006cfa: 7dfb ldrb r3, [r7, #23]
|
|
8006cfc: e000 b.n 8006d00 <USBD_LL_DataOutStage+0x170>
|
|
}
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8006cfe: 2300 movs r3, #0
|
|
}
|
|
8006d00: 4618 mov r0, r3
|
|
8006d02: 3718 adds r7, #24
|
|
8006d04: 46bd mov sp, r7
|
|
8006d06: bd80 pop {r7, pc}
|
|
|
|
08006d08 <USBD_LL_DataInStage>:
|
|
* @param pdata: data pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
8006d08: b580 push {r7, lr}
|
|
8006d0a: b086 sub sp, #24
|
|
8006d0c: af00 add r7, sp, #0
|
|
8006d0e: 60f8 str r0, [r7, #12]
|
|
8006d10: 460b mov r3, r1
|
|
8006d12: 607a str r2, [r7, #4]
|
|
8006d14: 72fb strb r3, [r7, #11]
|
|
USBD_StatusTypeDef ret;
|
|
uint8_t idx;
|
|
|
|
UNUSED(pdata);
|
|
|
|
if (epnum == 0U)
|
|
8006d16: 7afb ldrb r3, [r7, #11]
|
|
8006d18: 2b00 cmp r3, #0
|
|
8006d1a: d178 bne.n 8006e0e <USBD_LL_DataInStage+0x106>
|
|
{
|
|
pep = &pdev->ep_in[0];
|
|
8006d1c: 68fb ldr r3, [r7, #12]
|
|
8006d1e: 3314 adds r3, #20
|
|
8006d20: 613b str r3, [r7, #16]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_IN)
|
|
8006d22: 68fb ldr r3, [r7, #12]
|
|
8006d24: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
8006d28: 2b02 cmp r3, #2
|
|
8006d2a: d163 bne.n 8006df4 <USBD_LL_DataInStage+0xec>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
8006d2c: 693b ldr r3, [r7, #16]
|
|
8006d2e: 685b ldr r3, [r3, #4]
|
|
8006d30: 693a ldr r2, [r7, #16]
|
|
8006d32: 8992 ldrh r2, [r2, #12]
|
|
8006d34: 4293 cmp r3, r2
|
|
8006d36: d91c bls.n 8006d72 <USBD_LL_DataInStage+0x6a>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
8006d38: 693b ldr r3, [r7, #16]
|
|
8006d3a: 685b ldr r3, [r3, #4]
|
|
8006d3c: 693a ldr r2, [r7, #16]
|
|
8006d3e: 8992 ldrh r2, [r2, #12]
|
|
8006d40: 1a9a subs r2, r3, r2
|
|
8006d42: 693b ldr r3, [r7, #16]
|
|
8006d44: 605a str r2, [r3, #4]
|
|
pep->pbuffer += pep->maxpacket;
|
|
8006d46: 693b ldr r3, [r7, #16]
|
|
8006d48: 691b ldr r3, [r3, #16]
|
|
8006d4a: 693a ldr r2, [r7, #16]
|
|
8006d4c: 8992 ldrh r2, [r2, #12]
|
|
8006d4e: 441a add r2, r3
|
|
8006d50: 693b ldr r3, [r7, #16]
|
|
8006d52: 611a str r2, [r3, #16]
|
|
|
|
(void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length);
|
|
8006d54: 693b ldr r3, [r7, #16]
|
|
8006d56: 6919 ldr r1, [r3, #16]
|
|
8006d58: 693b ldr r3, [r7, #16]
|
|
8006d5a: 685b ldr r3, [r3, #4]
|
|
8006d5c: 461a mov r2, r3
|
|
8006d5e: 68f8 ldr r0, [r7, #12]
|
|
8006d60: f001 f8ee bl 8007f40 <USBD_CtlContinueSendData>
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8006d64: 2300 movs r3, #0
|
|
8006d66: 2200 movs r2, #0
|
|
8006d68: 2100 movs r1, #0
|
|
8006d6a: 68f8 ldr r0, [r7, #12]
|
|
8006d6c: f001 fd2a bl 80087c4 <USBD_LL_PrepareReceive>
|
|
8006d70: e040 b.n 8006df4 <USBD_LL_DataInStage+0xec>
|
|
}
|
|
else
|
|
{
|
|
/* last packet is MPS multiple, so send ZLP packet */
|
|
if ((pep->maxpacket == pep->rem_length) &&
|
|
8006d72: 693b ldr r3, [r7, #16]
|
|
8006d74: 899b ldrh r3, [r3, #12]
|
|
8006d76: 461a mov r2, r3
|
|
8006d78: 693b ldr r3, [r7, #16]
|
|
8006d7a: 685b ldr r3, [r3, #4]
|
|
8006d7c: 429a cmp r2, r3
|
|
8006d7e: d11c bne.n 8006dba <USBD_LL_DataInStage+0xb2>
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
8006d80: 693b ldr r3, [r7, #16]
|
|
8006d82: 681b ldr r3, [r3, #0]
|
|
8006d84: 693a ldr r2, [r7, #16]
|
|
8006d86: 8992 ldrh r2, [r2, #12]
|
|
if ((pep->maxpacket == pep->rem_length) &&
|
|
8006d88: 4293 cmp r3, r2
|
|
8006d8a: d316 bcc.n 8006dba <USBD_LL_DataInStage+0xb2>
|
|
(pep->total_length < pdev->ep0_data_len))
|
|
8006d8c: 693b ldr r3, [r7, #16]
|
|
8006d8e: 681a ldr r2, [r3, #0]
|
|
8006d90: 68fb ldr r3, [r7, #12]
|
|
8006d92: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
8006d96: 429a cmp r2, r3
|
|
8006d98: d20f bcs.n 8006dba <USBD_LL_DataInStage+0xb2>
|
|
{
|
|
(void)USBD_CtlContinueSendData(pdev, NULL, 0U);
|
|
8006d9a: 2200 movs r2, #0
|
|
8006d9c: 2100 movs r1, #0
|
|
8006d9e: 68f8 ldr r0, [r7, #12]
|
|
8006da0: f001 f8ce bl 8007f40 <USBD_CtlContinueSendData>
|
|
pdev->ep0_data_len = 0U;
|
|
8006da4: 68fb ldr r3, [r7, #12]
|
|
8006da6: 2200 movs r2, #0
|
|
8006da8: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8006dac: 2300 movs r3, #0
|
|
8006dae: 2200 movs r2, #0
|
|
8006db0: 2100 movs r1, #0
|
|
8006db2: 68f8 ldr r0, [r7, #12]
|
|
8006db4: f001 fd06 bl 80087c4 <USBD_LL_PrepareReceive>
|
|
8006db8: e01c b.n 8006df4 <USBD_LL_DataInStage+0xec>
|
|
}
|
|
else
|
|
{
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8006dba: 68fb ldr r3, [r7, #12]
|
|
8006dbc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8006dc0: b2db uxtb r3, r3
|
|
8006dc2: 2b03 cmp r3, #3
|
|
8006dc4: d10f bne.n 8006de6 <USBD_LL_DataInStage+0xde>
|
|
{
|
|
if (pdev->pClass[0]->EP0_TxSent != NULL)
|
|
8006dc6: 68fb ldr r3, [r7, #12]
|
|
8006dc8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8006dcc: 68db ldr r3, [r3, #12]
|
|
8006dce: 2b00 cmp r3, #0
|
|
8006dd0: d009 beq.n 8006de6 <USBD_LL_DataInStage+0xde>
|
|
{
|
|
pdev->classId = 0U;
|
|
8006dd2: 68fb ldr r3, [r7, #12]
|
|
8006dd4: 2200 movs r2, #0
|
|
8006dd6: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
pdev->pClass[0]->EP0_TxSent(pdev);
|
|
8006dda: 68fb ldr r3, [r7, #12]
|
|
8006ddc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8006de0: 68db ldr r3, [r3, #12]
|
|
8006de2: 68f8 ldr r0, [r7, #12]
|
|
8006de4: 4798 blx r3
|
|
}
|
|
}
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8006de6: 2180 movs r1, #128 @ 0x80
|
|
8006de8: 68f8 ldr r0, [r7, #12]
|
|
8006dea: f001 fc41 bl 8008670 <USBD_LL_StallEP>
|
|
(void)USBD_CtlReceiveStatus(pdev);
|
|
8006dee: 68f8 ldr r0, [r7, #12]
|
|
8006df0: f001 f8db bl 8007faa <USBD_CtlReceiveStatus>
|
|
}
|
|
}
|
|
}
|
|
|
|
if (pdev->dev_test_mode != 0U)
|
|
8006df4: 68fb ldr r3, [r7, #12]
|
|
8006df6: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
|
|
8006dfa: 2b00 cmp r3, #0
|
|
8006dfc: d03a beq.n 8006e74 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
(void)USBD_RunTestMode(pdev);
|
|
8006dfe: 68f8 ldr r0, [r7, #12]
|
|
8006e00: f7ff fe30 bl 8006a64 <USBD_RunTestMode>
|
|
pdev->dev_test_mode = 0U;
|
|
8006e04: 68fb ldr r3, [r7, #12]
|
|
8006e06: 2200 movs r2, #0
|
|
8006e08: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
8006e0c: e032 b.n 8006e74 <USBD_LL_DataInStage+0x16c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U));
|
|
8006e0e: 7afb ldrb r3, [r7, #11]
|
|
8006e10: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8006e14: b2db uxtb r3, r3
|
|
8006e16: 4619 mov r1, r3
|
|
8006e18: 68f8 ldr r0, [r7, #12]
|
|
8006e1a: f000 f986 bl 800712a <USBD_CoreFindEP>
|
|
8006e1e: 4603 mov r3, r0
|
|
8006e20: 75fb strb r3, [r7, #23]
|
|
|
|
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8006e22: 7dfb ldrb r3, [r7, #23]
|
|
8006e24: 2bff cmp r3, #255 @ 0xff
|
|
8006e26: d025 beq.n 8006e74 <USBD_LL_DataInStage+0x16c>
|
|
8006e28: 7dfb ldrb r3, [r7, #23]
|
|
8006e2a: 2b00 cmp r3, #0
|
|
8006e2c: d122 bne.n 8006e74 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8006e2e: 68fb ldr r3, [r7, #12]
|
|
8006e30: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8006e34: b2db uxtb r3, r3
|
|
8006e36: 2b03 cmp r3, #3
|
|
8006e38: d11c bne.n 8006e74 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
if (pdev->pClass[idx]->DataIn != NULL)
|
|
8006e3a: 7dfa ldrb r2, [r7, #23]
|
|
8006e3c: 68fb ldr r3, [r7, #12]
|
|
8006e3e: 32ae adds r2, #174 @ 0xae
|
|
8006e40: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8006e44: 695b ldr r3, [r3, #20]
|
|
8006e46: 2b00 cmp r3, #0
|
|
8006e48: d014 beq.n 8006e74 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
pdev->classId = idx;
|
|
8006e4a: 7dfa ldrb r2, [r7, #23]
|
|
8006e4c: 68fb ldr r3, [r7, #12]
|
|
8006e4e: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum);
|
|
8006e52: 7dfa ldrb r2, [r7, #23]
|
|
8006e54: 68fb ldr r3, [r7, #12]
|
|
8006e56: 32ae adds r2, #174 @ 0xae
|
|
8006e58: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8006e5c: 695b ldr r3, [r3, #20]
|
|
8006e5e: 7afa ldrb r2, [r7, #11]
|
|
8006e60: 4611 mov r1, r2
|
|
8006e62: 68f8 ldr r0, [r7, #12]
|
|
8006e64: 4798 blx r3
|
|
8006e66: 4603 mov r3, r0
|
|
8006e68: 75bb strb r3, [r7, #22]
|
|
|
|
if (ret != USBD_OK)
|
|
8006e6a: 7dbb ldrb r3, [r7, #22]
|
|
8006e6c: 2b00 cmp r3, #0
|
|
8006e6e: d001 beq.n 8006e74 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
return ret;
|
|
8006e70: 7dbb ldrb r3, [r7, #22]
|
|
8006e72: e000 b.n 8006e76 <USBD_LL_DataInStage+0x16e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8006e74: 2300 movs r3, #0
|
|
}
|
|
8006e76: 4618 mov r0, r3
|
|
8006e78: 3718 adds r7, #24
|
|
8006e7a: 46bd mov sp, r7
|
|
8006e7c: bd80 pop {r7, pc}
|
|
|
|
08006e7e <USBD_LL_Reset>:
|
|
* Handle Reset event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8006e7e: b580 push {r7, lr}
|
|
8006e80: b084 sub sp, #16
|
|
8006e82: af00 add r7, sp, #0
|
|
8006e84: 6078 str r0, [r7, #4]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8006e86: 2300 movs r3, #0
|
|
8006e88: 73fb strb r3, [r7, #15]
|
|
|
|
/* Upon Reset call user call back */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8006e8a: 687b ldr r3, [r7, #4]
|
|
8006e8c: 2201 movs r2, #1
|
|
8006e8e: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->ep0_state = USBD_EP0_IDLE;
|
|
8006e92: 687b ldr r3, [r7, #4]
|
|
8006e94: 2200 movs r2, #0
|
|
8006e96: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->dev_config = 0U;
|
|
8006e9a: 687b ldr r3, [r7, #4]
|
|
8006e9c: 2200 movs r2, #0
|
|
8006e9e: 605a str r2, [r3, #4]
|
|
pdev->dev_remote_wakeup = 0U;
|
|
8006ea0: 687b ldr r3, [r7, #4]
|
|
8006ea2: 2200 movs r2, #0
|
|
8006ea4: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
pdev->dev_test_mode = 0U;
|
|
8006ea8: 687b ldr r3, [r7, #4]
|
|
8006eaa: 2200 movs r2, #0
|
|
8006eac: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
|
|
if (pdev->pClass[0] != NULL)
|
|
8006eb0: 687b ldr r3, [r7, #4]
|
|
8006eb2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8006eb6: 2b00 cmp r3, #0
|
|
8006eb8: d014 beq.n 8006ee4 <USBD_LL_Reset+0x66>
|
|
{
|
|
if (pdev->pClass[0]->DeInit != NULL)
|
|
8006eba: 687b ldr r3, [r7, #4]
|
|
8006ebc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8006ec0: 685b ldr r3, [r3, #4]
|
|
8006ec2: 2b00 cmp r3, #0
|
|
8006ec4: d00e beq.n 8006ee4 <USBD_LL_Reset+0x66>
|
|
{
|
|
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK)
|
|
8006ec6: 687b ldr r3, [r7, #4]
|
|
8006ec8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8006ecc: 685b ldr r3, [r3, #4]
|
|
8006ece: 687a ldr r2, [r7, #4]
|
|
8006ed0: 6852 ldr r2, [r2, #4]
|
|
8006ed2: b2d2 uxtb r2, r2
|
|
8006ed4: 4611 mov r1, r2
|
|
8006ed6: 6878 ldr r0, [r7, #4]
|
|
8006ed8: 4798 blx r3
|
|
8006eda: 4603 mov r3, r0
|
|
8006edc: 2b00 cmp r3, #0
|
|
8006ede: d001 beq.n 8006ee4 <USBD_LL_Reset+0x66>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8006ee0: 2303 movs r3, #3
|
|
8006ee2: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Open EP0 OUT */
|
|
(void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
8006ee4: 2340 movs r3, #64 @ 0x40
|
|
8006ee6: 2200 movs r2, #0
|
|
8006ee8: 2100 movs r1, #0
|
|
8006eea: 6878 ldr r0, [r7, #4]
|
|
8006eec: f001 fb7b bl 80085e6 <USBD_LL_OpenEP>
|
|
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
|
|
8006ef0: 687b ldr r3, [r7, #4]
|
|
8006ef2: 2201 movs r2, #1
|
|
8006ef4: f883 2163 strb.w r2, [r3, #355] @ 0x163
|
|
|
|
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
8006ef8: 687b ldr r3, [r7, #4]
|
|
8006efa: 2240 movs r2, #64 @ 0x40
|
|
8006efc: f8a3 2160 strh.w r2, [r3, #352] @ 0x160
|
|
|
|
/* Open EP0 IN */
|
|
(void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
8006f00: 2340 movs r3, #64 @ 0x40
|
|
8006f02: 2200 movs r2, #0
|
|
8006f04: 2180 movs r1, #128 @ 0x80
|
|
8006f06: 6878 ldr r0, [r7, #4]
|
|
8006f08: f001 fb6d bl 80085e6 <USBD_LL_OpenEP>
|
|
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
|
|
8006f0c: 687b ldr r3, [r7, #4]
|
|
8006f0e: 2201 movs r2, #1
|
|
8006f10: f883 2023 strb.w r2, [r3, #35] @ 0x23
|
|
|
|
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
8006f14: 687b ldr r3, [r7, #4]
|
|
8006f16: 2240 movs r2, #64 @ 0x40
|
|
8006f18: 841a strh r2, [r3, #32]
|
|
|
|
return ret;
|
|
8006f1a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8006f1c: 4618 mov r0, r3
|
|
8006f1e: 3710 adds r7, #16
|
|
8006f20: 46bd mov sp, r7
|
|
8006f22: bd80 pop {r7, pc}
|
|
|
|
08006f24 <USBD_LL_SetSpeed>:
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
|
|
USBD_SpeedTypeDef speed)
|
|
{
|
|
8006f24: b480 push {r7}
|
|
8006f26: b083 sub sp, #12
|
|
8006f28: af00 add r7, sp, #0
|
|
8006f2a: 6078 str r0, [r7, #4]
|
|
8006f2c: 460b mov r3, r1
|
|
8006f2e: 70fb strb r3, [r7, #3]
|
|
pdev->dev_speed = speed;
|
|
8006f30: 687b ldr r3, [r7, #4]
|
|
8006f32: 78fa ldrb r2, [r7, #3]
|
|
8006f34: 741a strb r2, [r3, #16]
|
|
|
|
return USBD_OK;
|
|
8006f36: 2300 movs r3, #0
|
|
}
|
|
8006f38: 4618 mov r0, r3
|
|
8006f3a: 370c adds r7, #12
|
|
8006f3c: 46bd mov sp, r7
|
|
8006f3e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f42: 4770 bx lr
|
|
|
|
08006f44 <USBD_LL_Suspend>:
|
|
* Handle Suspend event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8006f44: b480 push {r7}
|
|
8006f46: b083 sub sp, #12
|
|
8006f48: af00 add r7, sp, #0
|
|
8006f4a: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state != USBD_STATE_SUSPENDED)
|
|
8006f4c: 687b ldr r3, [r7, #4]
|
|
8006f4e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8006f52: b2db uxtb r3, r3
|
|
8006f54: 2b04 cmp r3, #4
|
|
8006f56: d006 beq.n 8006f66 <USBD_LL_Suspend+0x22>
|
|
{
|
|
pdev->dev_old_state = pdev->dev_state;
|
|
8006f58: 687b ldr r3, [r7, #4]
|
|
8006f5a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8006f5e: b2da uxtb r2, r3
|
|
8006f60: 687b ldr r3, [r7, #4]
|
|
8006f62: f883 229d strb.w r2, [r3, #669] @ 0x29d
|
|
}
|
|
|
|
pdev->dev_state = USBD_STATE_SUSPENDED;
|
|
8006f66: 687b ldr r3, [r7, #4]
|
|
8006f68: 2204 movs r2, #4
|
|
8006f6a: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
|
|
return USBD_OK;
|
|
8006f6e: 2300 movs r3, #0
|
|
}
|
|
8006f70: 4618 mov r0, r3
|
|
8006f72: 370c adds r7, #12
|
|
8006f74: 46bd mov sp, r7
|
|
8006f76: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f7a: 4770 bx lr
|
|
|
|
08006f7c <USBD_LL_Resume>:
|
|
* Handle Resume event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8006f7c: b480 push {r7}
|
|
8006f7e: b083 sub sp, #12
|
|
8006f80: af00 add r7, sp, #0
|
|
8006f82: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state == USBD_STATE_SUSPENDED)
|
|
8006f84: 687b ldr r3, [r7, #4]
|
|
8006f86: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8006f8a: b2db uxtb r3, r3
|
|
8006f8c: 2b04 cmp r3, #4
|
|
8006f8e: d106 bne.n 8006f9e <USBD_LL_Resume+0x22>
|
|
{
|
|
pdev->dev_state = pdev->dev_old_state;
|
|
8006f90: 687b ldr r3, [r7, #4]
|
|
8006f92: f893 329d ldrb.w r3, [r3, #669] @ 0x29d
|
|
8006f96: b2da uxtb r2, r3
|
|
8006f98: 687b ldr r3, [r7, #4]
|
|
8006f9a: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
|
|
return USBD_OK;
|
|
8006f9e: 2300 movs r3, #0
|
|
}
|
|
8006fa0: 4618 mov r0, r3
|
|
8006fa2: 370c adds r7, #12
|
|
8006fa4: 46bd mov sp, r7
|
|
8006fa6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006faa: 4770 bx lr
|
|
|
|
08006fac <USBD_LL_SOF>:
|
|
* Handle SOF event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8006fac: b580 push {r7, lr}
|
|
8006fae: b082 sub sp, #8
|
|
8006fb0: af00 add r7, sp, #0
|
|
8006fb2: 6078 str r0, [r7, #4]
|
|
/* The SOF event can be distributed for all classes that support it */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8006fb4: 687b ldr r3, [r7, #4]
|
|
8006fb6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8006fba: b2db uxtb r3, r3
|
|
8006fbc: 2b03 cmp r3, #3
|
|
8006fbe: d110 bne.n 8006fe2 <USBD_LL_SOF+0x36>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
8006fc0: 687b ldr r3, [r7, #4]
|
|
8006fc2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8006fc6: 2b00 cmp r3, #0
|
|
8006fc8: d00b beq.n 8006fe2 <USBD_LL_SOF+0x36>
|
|
{
|
|
if (pdev->pClass[0]->SOF != NULL)
|
|
8006fca: 687b ldr r3, [r7, #4]
|
|
8006fcc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8006fd0: 69db ldr r3, [r3, #28]
|
|
8006fd2: 2b00 cmp r3, #0
|
|
8006fd4: d005 beq.n 8006fe2 <USBD_LL_SOF+0x36>
|
|
{
|
|
(void)pdev->pClass[0]->SOF(pdev);
|
|
8006fd6: 687b ldr r3, [r7, #4]
|
|
8006fd8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8006fdc: 69db ldr r3, [r3, #28]
|
|
8006fde: 6878 ldr r0, [r7, #4]
|
|
8006fe0: 4798 blx r3
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
|
|
return USBD_OK;
|
|
8006fe2: 2300 movs r3, #0
|
|
}
|
|
8006fe4: 4618 mov r0, r3
|
|
8006fe6: 3708 adds r7, #8
|
|
8006fe8: 46bd mov sp, r7
|
|
8006fea: bd80 pop {r7, pc}
|
|
|
|
08006fec <USBD_LL_IsoINIncomplete>:
|
|
* @param epnum: Endpoint number
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum)
|
|
{
|
|
8006fec: b580 push {r7, lr}
|
|
8006fee: b082 sub sp, #8
|
|
8006ff0: af00 add r7, sp, #0
|
|
8006ff2: 6078 str r0, [r7, #4]
|
|
8006ff4: 460b mov r3, r1
|
|
8006ff6: 70fb strb r3, [r7, #3]
|
|
if (pdev->pClass[pdev->classId] == NULL)
|
|
8006ff8: 687b ldr r3, [r7, #4]
|
|
8006ffa: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8006ffe: 687b ldr r3, [r7, #4]
|
|
8007000: 32ae adds r2, #174 @ 0xae
|
|
8007002: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007006: 2b00 cmp r3, #0
|
|
8007008: d101 bne.n 800700e <USBD_LL_IsoINIncomplete+0x22>
|
|
{
|
|
return USBD_FAIL;
|
|
800700a: 2303 movs r3, #3
|
|
800700c: e01c b.n 8007048 <USBD_LL_IsoINIncomplete+0x5c>
|
|
}
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
800700e: 687b ldr r3, [r7, #4]
|
|
8007010: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007014: b2db uxtb r3, r3
|
|
8007016: 2b03 cmp r3, #3
|
|
8007018: d115 bne.n 8007046 <USBD_LL_IsoINIncomplete+0x5a>
|
|
{
|
|
if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL)
|
|
800701a: 687b ldr r3, [r7, #4]
|
|
800701c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007020: 687b ldr r3, [r7, #4]
|
|
8007022: 32ae adds r2, #174 @ 0xae
|
|
8007024: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007028: 6a1b ldr r3, [r3, #32]
|
|
800702a: 2b00 cmp r3, #0
|
|
800702c: d00b beq.n 8007046 <USBD_LL_IsoINIncomplete+0x5a>
|
|
{
|
|
(void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum);
|
|
800702e: 687b ldr r3, [r7, #4]
|
|
8007030: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007034: 687b ldr r3, [r7, #4]
|
|
8007036: 32ae adds r2, #174 @ 0xae
|
|
8007038: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800703c: 6a1b ldr r3, [r3, #32]
|
|
800703e: 78fa ldrb r2, [r7, #3]
|
|
8007040: 4611 mov r1, r2
|
|
8007042: 6878 ldr r0, [r7, #4]
|
|
8007044: 4798 blx r3
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8007046: 2300 movs r3, #0
|
|
}
|
|
8007048: 4618 mov r0, r3
|
|
800704a: 3708 adds r7, #8
|
|
800704c: 46bd mov sp, r7
|
|
800704e: bd80 pop {r7, pc}
|
|
|
|
08007050 <USBD_LL_IsoOUTIncomplete>:
|
|
* @param epnum: Endpoint number
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum)
|
|
{
|
|
8007050: b580 push {r7, lr}
|
|
8007052: b082 sub sp, #8
|
|
8007054: af00 add r7, sp, #0
|
|
8007056: 6078 str r0, [r7, #4]
|
|
8007058: 460b mov r3, r1
|
|
800705a: 70fb strb r3, [r7, #3]
|
|
if (pdev->pClass[pdev->classId] == NULL)
|
|
800705c: 687b ldr r3, [r7, #4]
|
|
800705e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007062: 687b ldr r3, [r7, #4]
|
|
8007064: 32ae adds r2, #174 @ 0xae
|
|
8007066: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800706a: 2b00 cmp r3, #0
|
|
800706c: d101 bne.n 8007072 <USBD_LL_IsoOUTIncomplete+0x22>
|
|
{
|
|
return USBD_FAIL;
|
|
800706e: 2303 movs r3, #3
|
|
8007070: e01c b.n 80070ac <USBD_LL_IsoOUTIncomplete+0x5c>
|
|
}
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007072: 687b ldr r3, [r7, #4]
|
|
8007074: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007078: b2db uxtb r3, r3
|
|
800707a: 2b03 cmp r3, #3
|
|
800707c: d115 bne.n 80070aa <USBD_LL_IsoOUTIncomplete+0x5a>
|
|
{
|
|
if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL)
|
|
800707e: 687b ldr r3, [r7, #4]
|
|
8007080: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007084: 687b ldr r3, [r7, #4]
|
|
8007086: 32ae adds r2, #174 @ 0xae
|
|
8007088: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800708c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800708e: 2b00 cmp r3, #0
|
|
8007090: d00b beq.n 80070aa <USBD_LL_IsoOUTIncomplete+0x5a>
|
|
{
|
|
(void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum);
|
|
8007092: 687b ldr r3, [r7, #4]
|
|
8007094: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007098: 687b ldr r3, [r7, #4]
|
|
800709a: 32ae adds r2, #174 @ 0xae
|
|
800709c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80070a0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80070a2: 78fa ldrb r2, [r7, #3]
|
|
80070a4: 4611 mov r1, r2
|
|
80070a6: 6878 ldr r0, [r7, #4]
|
|
80070a8: 4798 blx r3
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
80070aa: 2300 movs r3, #0
|
|
}
|
|
80070ac: 4618 mov r0, r3
|
|
80070ae: 3708 adds r7, #8
|
|
80070b0: 46bd mov sp, r7
|
|
80070b2: bd80 pop {r7, pc}
|
|
|
|
080070b4 <USBD_LL_DevConnected>:
|
|
* Handle device connection event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80070b4: b480 push {r7}
|
|
80070b6: b083 sub sp, #12
|
|
80070b8: af00 add r7, sp, #0
|
|
80070ba: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument compilation warning */
|
|
UNUSED(pdev);
|
|
|
|
return USBD_OK;
|
|
80070bc: 2300 movs r3, #0
|
|
}
|
|
80070be: 4618 mov r0, r3
|
|
80070c0: 370c adds r7, #12
|
|
80070c2: 46bd mov sp, r7
|
|
80070c4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80070c8: 4770 bx lr
|
|
|
|
080070ca <USBD_LL_DevDisconnected>:
|
|
* Handle device disconnection event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80070ca: b580 push {r7, lr}
|
|
80070cc: b084 sub sp, #16
|
|
80070ce: af00 add r7, sp, #0
|
|
80070d0: 6078 str r0, [r7, #4]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80070d2: 2300 movs r3, #0
|
|
80070d4: 73fb strb r3, [r7, #15]
|
|
|
|
/* Free Class Resources */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
80070d6: 687b ldr r3, [r7, #4]
|
|
80070d8: 2201 movs r2, #1
|
|
80070da: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
80070de: 687b ldr r3, [r7, #4]
|
|
80070e0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80070e4: 2b00 cmp r3, #0
|
|
80070e6: d00e beq.n 8007106 <USBD_LL_DevDisconnected+0x3c>
|
|
{
|
|
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U)
|
|
80070e8: 687b ldr r3, [r7, #4]
|
|
80070ea: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80070ee: 685b ldr r3, [r3, #4]
|
|
80070f0: 687a ldr r2, [r7, #4]
|
|
80070f2: 6852 ldr r2, [r2, #4]
|
|
80070f4: b2d2 uxtb r2, r2
|
|
80070f6: 4611 mov r1, r2
|
|
80070f8: 6878 ldr r0, [r7, #4]
|
|
80070fa: 4798 blx r3
|
|
80070fc: 4603 mov r3, r0
|
|
80070fe: 2b00 cmp r3, #0
|
|
8007100: d001 beq.n 8007106 <USBD_LL_DevDisconnected+0x3c>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8007102: 2303 movs r3, #3
|
|
8007104: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8007106: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007108: 4618 mov r0, r3
|
|
800710a: 3710 adds r7, #16
|
|
800710c: 46bd mov sp, r7
|
|
800710e: bd80 pop {r7, pc}
|
|
|
|
08007110 <USBD_CoreFindIF>:
|
|
* @param pdev: device instance
|
|
* @param index : selected interface number
|
|
* @retval index of the class using the selected interface number. OxFF if no class found.
|
|
*/
|
|
uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index)
|
|
{
|
|
8007110: b480 push {r7}
|
|
8007112: b083 sub sp, #12
|
|
8007114: af00 add r7, sp, #0
|
|
8007116: 6078 str r0, [r7, #4]
|
|
8007118: 460b mov r3, r1
|
|
800711a: 70fb strb r3, [r7, #3]
|
|
return 0xFFU;
|
|
#else
|
|
UNUSED(pdev);
|
|
UNUSED(index);
|
|
|
|
return 0x00U;
|
|
800711c: 2300 movs r3, #0
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
800711e: 4618 mov r0, r3
|
|
8007120: 370c adds r7, #12
|
|
8007122: 46bd mov sp, r7
|
|
8007124: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007128: 4770 bx lr
|
|
|
|
0800712a <USBD_CoreFindEP>:
|
|
* @param pdev: device instance
|
|
* @param index : selected endpoint number
|
|
* @retval index of the class using the selected endpoint number. 0xFF if no class found.
|
|
*/
|
|
uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index)
|
|
{
|
|
800712a: b480 push {r7}
|
|
800712c: b083 sub sp, #12
|
|
800712e: af00 add r7, sp, #0
|
|
8007130: 6078 str r0, [r7, #4]
|
|
8007132: 460b mov r3, r1
|
|
8007134: 70fb strb r3, [r7, #3]
|
|
return 0xFFU;
|
|
#else
|
|
UNUSED(pdev);
|
|
UNUSED(index);
|
|
|
|
return 0x00U;
|
|
8007136: 2300 movs r3, #0
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
8007138: 4618 mov r0, r3
|
|
800713a: 370c adds r7, #12
|
|
800713c: 46bd mov sp, r7
|
|
800713e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007142: 4770 bx lr
|
|
|
|
08007144 <USBD_GetEpDesc>:
|
|
* @param pConfDesc: pointer to Bos descriptor
|
|
* @param EpAddr: endpoint address
|
|
* @retval pointer to video endpoint descriptor
|
|
*/
|
|
void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr)
|
|
{
|
|
8007144: b580 push {r7, lr}
|
|
8007146: b086 sub sp, #24
|
|
8007148: af00 add r7, sp, #0
|
|
800714a: 6078 str r0, [r7, #4]
|
|
800714c: 460b mov r3, r1
|
|
800714e: 70fb strb r3, [r7, #3]
|
|
USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc;
|
|
8007150: 687b ldr r3, [r7, #4]
|
|
8007152: 617b str r3, [r7, #20]
|
|
USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc;
|
|
8007154: 687b ldr r3, [r7, #4]
|
|
8007156: 60fb str r3, [r7, #12]
|
|
USBD_EpDescTypeDef *pEpDesc = NULL;
|
|
8007158: 2300 movs r3, #0
|
|
800715a: 613b str r3, [r7, #16]
|
|
uint16_t ptr;
|
|
|
|
if (desc->wTotalLength > desc->bLength)
|
|
800715c: 68fb ldr r3, [r7, #12]
|
|
800715e: 885b ldrh r3, [r3, #2]
|
|
8007160: b29b uxth r3, r3
|
|
8007162: 68fa ldr r2, [r7, #12]
|
|
8007164: 7812 ldrb r2, [r2, #0]
|
|
8007166: 4293 cmp r3, r2
|
|
8007168: d91f bls.n 80071aa <USBD_GetEpDesc+0x66>
|
|
{
|
|
ptr = desc->bLength;
|
|
800716a: 68fb ldr r3, [r7, #12]
|
|
800716c: 781b ldrb r3, [r3, #0]
|
|
800716e: 817b strh r3, [r7, #10]
|
|
|
|
while (ptr < desc->wTotalLength)
|
|
8007170: e013 b.n 800719a <USBD_GetEpDesc+0x56>
|
|
{
|
|
pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr);
|
|
8007172: f107 030a add.w r3, r7, #10
|
|
8007176: 4619 mov r1, r3
|
|
8007178: 6978 ldr r0, [r7, #20]
|
|
800717a: f000 f81b bl 80071b4 <USBD_GetNextDesc>
|
|
800717e: 6178 str r0, [r7, #20]
|
|
|
|
if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT)
|
|
8007180: 697b ldr r3, [r7, #20]
|
|
8007182: 785b ldrb r3, [r3, #1]
|
|
8007184: 2b05 cmp r3, #5
|
|
8007186: d108 bne.n 800719a <USBD_GetEpDesc+0x56>
|
|
{
|
|
pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc;
|
|
8007188: 697b ldr r3, [r7, #20]
|
|
800718a: 613b str r3, [r7, #16]
|
|
|
|
if (pEpDesc->bEndpointAddress == EpAddr)
|
|
800718c: 693b ldr r3, [r7, #16]
|
|
800718e: 789b ldrb r3, [r3, #2]
|
|
8007190: 78fa ldrb r2, [r7, #3]
|
|
8007192: 429a cmp r2, r3
|
|
8007194: d008 beq.n 80071a8 <USBD_GetEpDesc+0x64>
|
|
{
|
|
break;
|
|
}
|
|
else
|
|
{
|
|
pEpDesc = NULL;
|
|
8007196: 2300 movs r3, #0
|
|
8007198: 613b str r3, [r7, #16]
|
|
while (ptr < desc->wTotalLength)
|
|
800719a: 68fb ldr r3, [r7, #12]
|
|
800719c: 885b ldrh r3, [r3, #2]
|
|
800719e: b29a uxth r2, r3
|
|
80071a0: 897b ldrh r3, [r7, #10]
|
|
80071a2: 429a cmp r2, r3
|
|
80071a4: d8e5 bhi.n 8007172 <USBD_GetEpDesc+0x2e>
|
|
80071a6: e000 b.n 80071aa <USBD_GetEpDesc+0x66>
|
|
break;
|
|
80071a8: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return (void *)pEpDesc;
|
|
80071aa: 693b ldr r3, [r7, #16]
|
|
}
|
|
80071ac: 4618 mov r0, r3
|
|
80071ae: 3718 adds r7, #24
|
|
80071b0: 46bd mov sp, r7
|
|
80071b2: bd80 pop {r7, pc}
|
|
|
|
080071b4 <USBD_GetNextDesc>:
|
|
* @param buf: Buffer where the descriptor is available
|
|
* @param ptr: data pointer inside the descriptor
|
|
* @retval next header
|
|
*/
|
|
USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr)
|
|
{
|
|
80071b4: b480 push {r7}
|
|
80071b6: b085 sub sp, #20
|
|
80071b8: af00 add r7, sp, #0
|
|
80071ba: 6078 str r0, [r7, #4]
|
|
80071bc: 6039 str r1, [r7, #0]
|
|
USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf;
|
|
80071be: 687b ldr r3, [r7, #4]
|
|
80071c0: 60fb str r3, [r7, #12]
|
|
|
|
*ptr += pnext->bLength;
|
|
80071c2: 683b ldr r3, [r7, #0]
|
|
80071c4: 881b ldrh r3, [r3, #0]
|
|
80071c6: 68fa ldr r2, [r7, #12]
|
|
80071c8: 7812 ldrb r2, [r2, #0]
|
|
80071ca: 4413 add r3, r2
|
|
80071cc: b29a uxth r2, r3
|
|
80071ce: 683b ldr r3, [r7, #0]
|
|
80071d0: 801a strh r2, [r3, #0]
|
|
pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength);
|
|
80071d2: 68fb ldr r3, [r7, #12]
|
|
80071d4: 781b ldrb r3, [r3, #0]
|
|
80071d6: 461a mov r2, r3
|
|
80071d8: 687b ldr r3, [r7, #4]
|
|
80071da: 4413 add r3, r2
|
|
80071dc: 60fb str r3, [r7, #12]
|
|
|
|
return (pnext);
|
|
80071de: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80071e0: 4618 mov r0, r3
|
|
80071e2: 3714 adds r7, #20
|
|
80071e4: 46bd mov sp, r7
|
|
80071e6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80071ea: 4770 bx lr
|
|
|
|
080071ec <SWAPBYTE>:
|
|
|
|
/** @defgroup USBD_DEF_Exported_Macros
|
|
* @{
|
|
*/
|
|
__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
|
|
{
|
|
80071ec: b480 push {r7}
|
|
80071ee: b087 sub sp, #28
|
|
80071f0: af00 add r7, sp, #0
|
|
80071f2: 6078 str r0, [r7, #4]
|
|
uint16_t _SwapVal;
|
|
uint16_t _Byte1;
|
|
uint16_t _Byte2;
|
|
uint8_t *_pbuff = addr;
|
|
80071f4: 687b ldr r3, [r7, #4]
|
|
80071f6: 617b str r3, [r7, #20]
|
|
|
|
_Byte1 = *(uint8_t *)_pbuff;
|
|
80071f8: 697b ldr r3, [r7, #20]
|
|
80071fa: 781b ldrb r3, [r3, #0]
|
|
80071fc: 827b strh r3, [r7, #18]
|
|
_pbuff++;
|
|
80071fe: 697b ldr r3, [r7, #20]
|
|
8007200: 3301 adds r3, #1
|
|
8007202: 617b str r3, [r7, #20]
|
|
_Byte2 = *(uint8_t *)_pbuff;
|
|
8007204: 697b ldr r3, [r7, #20]
|
|
8007206: 781b ldrb r3, [r3, #0]
|
|
8007208: 823b strh r3, [r7, #16]
|
|
|
|
_SwapVal = (_Byte2 << 8) | _Byte1;
|
|
800720a: f9b7 3010 ldrsh.w r3, [r7, #16]
|
|
800720e: 021b lsls r3, r3, #8
|
|
8007210: b21a sxth r2, r3
|
|
8007212: f9b7 3012 ldrsh.w r3, [r7, #18]
|
|
8007216: 4313 orrs r3, r2
|
|
8007218: b21b sxth r3, r3
|
|
800721a: 81fb strh r3, [r7, #14]
|
|
|
|
return _SwapVal;
|
|
800721c: 89fb ldrh r3, [r7, #14]
|
|
}
|
|
800721e: 4618 mov r0, r3
|
|
8007220: 371c adds r7, #28
|
|
8007222: 46bd mov sp, r7
|
|
8007224: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007228: 4770 bx lr
|
|
...
|
|
|
|
0800722c <USBD_StdDevReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
800722c: b580 push {r7, lr}
|
|
800722e: b084 sub sp, #16
|
|
8007230: af00 add r7, sp, #0
|
|
8007232: 6078 str r0, [r7, #4]
|
|
8007234: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007236: 2300 movs r3, #0
|
|
8007238: 73fb strb r3, [r7, #15]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
800723a: 683b ldr r3, [r7, #0]
|
|
800723c: 781b ldrb r3, [r3, #0]
|
|
800723e: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8007242: 2b40 cmp r3, #64 @ 0x40
|
|
8007244: d005 beq.n 8007252 <USBD_StdDevReq+0x26>
|
|
8007246: 2b40 cmp r3, #64 @ 0x40
|
|
8007248: d857 bhi.n 80072fa <USBD_StdDevReq+0xce>
|
|
800724a: 2b00 cmp r3, #0
|
|
800724c: d00f beq.n 800726e <USBD_StdDevReq+0x42>
|
|
800724e: 2b20 cmp r3, #32
|
|
8007250: d153 bne.n 80072fa <USBD_StdDevReq+0xce>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req);
|
|
8007252: 687b ldr r3, [r7, #4]
|
|
8007254: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8007258: 687b ldr r3, [r7, #4]
|
|
800725a: 32ae adds r2, #174 @ 0xae
|
|
800725c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007260: 689b ldr r3, [r3, #8]
|
|
8007262: 6839 ldr r1, [r7, #0]
|
|
8007264: 6878 ldr r0, [r7, #4]
|
|
8007266: 4798 blx r3
|
|
8007268: 4603 mov r3, r0
|
|
800726a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800726c: e04a b.n 8007304 <USBD_StdDevReq+0xd8>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
800726e: 683b ldr r3, [r7, #0]
|
|
8007270: 785b ldrb r3, [r3, #1]
|
|
8007272: 2b09 cmp r3, #9
|
|
8007274: d83b bhi.n 80072ee <USBD_StdDevReq+0xc2>
|
|
8007276: a201 add r2, pc, #4 @ (adr r2, 800727c <USBD_StdDevReq+0x50>)
|
|
8007278: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800727c: 080072d1 .word 0x080072d1
|
|
8007280: 080072e5 .word 0x080072e5
|
|
8007284: 080072ef .word 0x080072ef
|
|
8007288: 080072db .word 0x080072db
|
|
800728c: 080072ef .word 0x080072ef
|
|
8007290: 080072af .word 0x080072af
|
|
8007294: 080072a5 .word 0x080072a5
|
|
8007298: 080072ef .word 0x080072ef
|
|
800729c: 080072c7 .word 0x080072c7
|
|
80072a0: 080072b9 .word 0x080072b9
|
|
{
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
USBD_GetDescriptor(pdev, req);
|
|
80072a4: 6839 ldr r1, [r7, #0]
|
|
80072a6: 6878 ldr r0, [r7, #4]
|
|
80072a8: f000 fa3e bl 8007728 <USBD_GetDescriptor>
|
|
break;
|
|
80072ac: e024 b.n 80072f8 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_ADDRESS:
|
|
USBD_SetAddress(pdev, req);
|
|
80072ae: 6839 ldr r1, [r7, #0]
|
|
80072b0: 6878 ldr r0, [r7, #4]
|
|
80072b2: f000 fbcd bl 8007a50 <USBD_SetAddress>
|
|
break;
|
|
80072b6: e01f b.n 80072f8 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_CONFIGURATION:
|
|
ret = USBD_SetConfig(pdev, req);
|
|
80072b8: 6839 ldr r1, [r7, #0]
|
|
80072ba: 6878 ldr r0, [r7, #4]
|
|
80072bc: f000 fc0c bl 8007ad8 <USBD_SetConfig>
|
|
80072c0: 4603 mov r3, r0
|
|
80072c2: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80072c4: e018 b.n 80072f8 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_GET_CONFIGURATION:
|
|
USBD_GetConfig(pdev, req);
|
|
80072c6: 6839 ldr r1, [r7, #0]
|
|
80072c8: 6878 ldr r0, [r7, #4]
|
|
80072ca: f000 fcaf bl 8007c2c <USBD_GetConfig>
|
|
break;
|
|
80072ce: e013 b.n 80072f8 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
USBD_GetStatus(pdev, req);
|
|
80072d0: 6839 ldr r1, [r7, #0]
|
|
80072d2: 6878 ldr r0, [r7, #4]
|
|
80072d4: f000 fce0 bl 8007c98 <USBD_GetStatus>
|
|
break;
|
|
80072d8: e00e b.n 80072f8 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_FEATURE:
|
|
USBD_SetFeature(pdev, req);
|
|
80072da: 6839 ldr r1, [r7, #0]
|
|
80072dc: 6878 ldr r0, [r7, #4]
|
|
80072de: f000 fd0f bl 8007d00 <USBD_SetFeature>
|
|
break;
|
|
80072e2: e009 b.n 80072f8 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
USBD_ClrFeature(pdev, req);
|
|
80072e4: 6839 ldr r1, [r7, #0]
|
|
80072e6: 6878 ldr r0, [r7, #4]
|
|
80072e8: f000 fd33 bl 8007d52 <USBD_ClrFeature>
|
|
break;
|
|
80072ec: e004 b.n 80072f8 <USBD_StdDevReq+0xcc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80072ee: 6839 ldr r1, [r7, #0]
|
|
80072f0: 6878 ldr r0, [r7, #4]
|
|
80072f2: f000 fd8a bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
80072f6: bf00 nop
|
|
}
|
|
break;
|
|
80072f8: e004 b.n 8007304 <USBD_StdDevReq+0xd8>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80072fa: 6839 ldr r1, [r7, #0]
|
|
80072fc: 6878 ldr r0, [r7, #4]
|
|
80072fe: f000 fd84 bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
8007302: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8007304: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007306: 4618 mov r0, r3
|
|
8007308: 3710 adds r7, #16
|
|
800730a: 46bd mov sp, r7
|
|
800730c: bd80 pop {r7, pc}
|
|
800730e: bf00 nop
|
|
|
|
08007310 <USBD_StdItfReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007310: b580 push {r7, lr}
|
|
8007312: b084 sub sp, #16
|
|
8007314: af00 add r7, sp, #0
|
|
8007316: 6078 str r0, [r7, #4]
|
|
8007318: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
800731a: 2300 movs r3, #0
|
|
800731c: 73fb strb r3, [r7, #15]
|
|
uint8_t idx;
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
800731e: 683b ldr r3, [r7, #0]
|
|
8007320: 781b ldrb r3, [r3, #0]
|
|
8007322: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8007326: 2b40 cmp r3, #64 @ 0x40
|
|
8007328: d005 beq.n 8007336 <USBD_StdItfReq+0x26>
|
|
800732a: 2b40 cmp r3, #64 @ 0x40
|
|
800732c: d852 bhi.n 80073d4 <USBD_StdItfReq+0xc4>
|
|
800732e: 2b00 cmp r3, #0
|
|
8007330: d001 beq.n 8007336 <USBD_StdItfReq+0x26>
|
|
8007332: 2b20 cmp r3, #32
|
|
8007334: d14e bne.n 80073d4 <USBD_StdItfReq+0xc4>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (pdev->dev_state)
|
|
8007336: 687b ldr r3, [r7, #4]
|
|
8007338: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
800733c: b2db uxtb r3, r3
|
|
800733e: 3b01 subs r3, #1
|
|
8007340: 2b02 cmp r3, #2
|
|
8007342: d840 bhi.n 80073c6 <USBD_StdItfReq+0xb6>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
|
|
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
|
|
8007344: 683b ldr r3, [r7, #0]
|
|
8007346: 889b ldrh r3, [r3, #4]
|
|
8007348: b2db uxtb r3, r3
|
|
800734a: 2b01 cmp r3, #1
|
|
800734c: d836 bhi.n 80073bc <USBD_StdItfReq+0xac>
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex));
|
|
800734e: 683b ldr r3, [r7, #0]
|
|
8007350: 889b ldrh r3, [r3, #4]
|
|
8007352: b2db uxtb r3, r3
|
|
8007354: 4619 mov r1, r3
|
|
8007356: 6878 ldr r0, [r7, #4]
|
|
8007358: f7ff feda bl 8007110 <USBD_CoreFindIF>
|
|
800735c: 4603 mov r3, r0
|
|
800735e: 73bb strb r3, [r7, #14]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8007360: 7bbb ldrb r3, [r7, #14]
|
|
8007362: 2bff cmp r3, #255 @ 0xff
|
|
8007364: d01d beq.n 80073a2 <USBD_StdItfReq+0x92>
|
|
8007366: 7bbb ldrb r3, [r7, #14]
|
|
8007368: 2b00 cmp r3, #0
|
|
800736a: d11a bne.n 80073a2 <USBD_StdItfReq+0x92>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
800736c: 7bba ldrb r2, [r7, #14]
|
|
800736e: 687b ldr r3, [r7, #4]
|
|
8007370: 32ae adds r2, #174 @ 0xae
|
|
8007372: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007376: 689b ldr r3, [r3, #8]
|
|
8007378: 2b00 cmp r3, #0
|
|
800737a: d00f beq.n 800739c <USBD_StdItfReq+0x8c>
|
|
{
|
|
pdev->classId = idx;
|
|
800737c: 7bba ldrb r2, [r7, #14]
|
|
800737e: 687b ldr r3, [r7, #4]
|
|
8007380: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
|
|
8007384: 7bba ldrb r2, [r7, #14]
|
|
8007386: 687b ldr r3, [r7, #4]
|
|
8007388: 32ae adds r2, #174 @ 0xae
|
|
800738a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800738e: 689b ldr r3, [r3, #8]
|
|
8007390: 6839 ldr r1, [r7, #0]
|
|
8007392: 6878 ldr r0, [r7, #4]
|
|
8007394: 4798 blx r3
|
|
8007396: 4603 mov r3, r0
|
|
8007398: 73fb strb r3, [r7, #15]
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
800739a: e004 b.n 80073a6 <USBD_StdItfReq+0x96>
|
|
}
|
|
else
|
|
{
|
|
/* should never reach this condition */
|
|
ret = USBD_FAIL;
|
|
800739c: 2303 movs r3, #3
|
|
800739e: 73fb strb r3, [r7, #15]
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
80073a0: e001 b.n 80073a6 <USBD_StdItfReq+0x96>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* No relative interface found */
|
|
ret = USBD_FAIL;
|
|
80073a2: 2303 movs r3, #3
|
|
80073a4: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
if ((req->wLength == 0U) && (ret == USBD_OK))
|
|
80073a6: 683b ldr r3, [r7, #0]
|
|
80073a8: 88db ldrh r3, [r3, #6]
|
|
80073aa: 2b00 cmp r3, #0
|
|
80073ac: d110 bne.n 80073d0 <USBD_StdItfReq+0xc0>
|
|
80073ae: 7bfb ldrb r3, [r7, #15]
|
|
80073b0: 2b00 cmp r3, #0
|
|
80073b2: d10d bne.n 80073d0 <USBD_StdItfReq+0xc0>
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80073b4: 6878 ldr r0, [r7, #4]
|
|
80073b6: f000 fde5 bl 8007f84 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
80073ba: e009 b.n 80073d0 <USBD_StdItfReq+0xc0>
|
|
USBD_CtlError(pdev, req);
|
|
80073bc: 6839 ldr r1, [r7, #0]
|
|
80073be: 6878 ldr r0, [r7, #4]
|
|
80073c0: f000 fd23 bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
80073c4: e004 b.n 80073d0 <USBD_StdItfReq+0xc0>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80073c6: 6839 ldr r1, [r7, #0]
|
|
80073c8: 6878 ldr r0, [r7, #4]
|
|
80073ca: f000 fd1e bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
80073ce: e000 b.n 80073d2 <USBD_StdItfReq+0xc2>
|
|
break;
|
|
80073d0: bf00 nop
|
|
}
|
|
break;
|
|
80073d2: e004 b.n 80073de <USBD_StdItfReq+0xce>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80073d4: 6839 ldr r1, [r7, #0]
|
|
80073d6: 6878 ldr r0, [r7, #4]
|
|
80073d8: f000 fd17 bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
80073dc: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
80073de: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80073e0: 4618 mov r0, r3
|
|
80073e2: 3710 adds r7, #16
|
|
80073e4: 46bd mov sp, r7
|
|
80073e6: bd80 pop {r7, pc}
|
|
|
|
080073e8 <USBD_StdEPReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
80073e8: b580 push {r7, lr}
|
|
80073ea: b084 sub sp, #16
|
|
80073ec: af00 add r7, sp, #0
|
|
80073ee: 6078 str r0, [r7, #4]
|
|
80073f0: 6039 str r1, [r7, #0]
|
|
USBD_EndpointTypeDef *pep;
|
|
uint8_t ep_addr;
|
|
uint8_t idx;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80073f2: 2300 movs r3, #0
|
|
80073f4: 73fb strb r3, [r7, #15]
|
|
|
|
ep_addr = LOBYTE(req->wIndex);
|
|
80073f6: 683b ldr r3, [r7, #0]
|
|
80073f8: 889b ldrh r3, [r3, #4]
|
|
80073fa: 73bb strb r3, [r7, #14]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
80073fc: 683b ldr r3, [r7, #0]
|
|
80073fe: 781b ldrb r3, [r3, #0]
|
|
8007400: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8007404: 2b40 cmp r3, #64 @ 0x40
|
|
8007406: d007 beq.n 8007418 <USBD_StdEPReq+0x30>
|
|
8007408: 2b40 cmp r3, #64 @ 0x40
|
|
800740a: f200 8181 bhi.w 8007710 <USBD_StdEPReq+0x328>
|
|
800740e: 2b00 cmp r3, #0
|
|
8007410: d02a beq.n 8007468 <USBD_StdEPReq+0x80>
|
|
8007412: 2b20 cmp r3, #32
|
|
8007414: f040 817c bne.w 8007710 <USBD_StdEPReq+0x328>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
/* Get the class index relative to this endpoint */
|
|
idx = USBD_CoreFindEP(pdev, ep_addr);
|
|
8007418: 7bbb ldrb r3, [r7, #14]
|
|
800741a: 4619 mov r1, r3
|
|
800741c: 6878 ldr r0, [r7, #4]
|
|
800741e: f7ff fe84 bl 800712a <USBD_CoreFindEP>
|
|
8007422: 4603 mov r3, r0
|
|
8007424: 737b strb r3, [r7, #13]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8007426: 7b7b ldrb r3, [r7, #13]
|
|
8007428: 2bff cmp r3, #255 @ 0xff
|
|
800742a: f000 8176 beq.w 800771a <USBD_StdEPReq+0x332>
|
|
800742e: 7b7b ldrb r3, [r7, #13]
|
|
8007430: 2b00 cmp r3, #0
|
|
8007432: f040 8172 bne.w 800771a <USBD_StdEPReq+0x332>
|
|
{
|
|
pdev->classId = idx;
|
|
8007436: 7b7a ldrb r2, [r7, #13]
|
|
8007438: 687b ldr r3, [r7, #4]
|
|
800743a: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
800743e: 7b7a ldrb r2, [r7, #13]
|
|
8007440: 687b ldr r3, [r7, #4]
|
|
8007442: 32ae adds r2, #174 @ 0xae
|
|
8007444: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007448: 689b ldr r3, [r3, #8]
|
|
800744a: 2b00 cmp r3, #0
|
|
800744c: f000 8165 beq.w 800771a <USBD_StdEPReq+0x332>
|
|
{
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req);
|
|
8007450: 7b7a ldrb r2, [r7, #13]
|
|
8007452: 687b ldr r3, [r7, #4]
|
|
8007454: 32ae adds r2, #174 @ 0xae
|
|
8007456: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800745a: 689b ldr r3, [r3, #8]
|
|
800745c: 6839 ldr r1, [r7, #0]
|
|
800745e: 6878 ldr r0, [r7, #4]
|
|
8007460: 4798 blx r3
|
|
8007462: 4603 mov r3, r0
|
|
8007464: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
8007466: e158 b.n 800771a <USBD_StdEPReq+0x332>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
8007468: 683b ldr r3, [r7, #0]
|
|
800746a: 785b ldrb r3, [r3, #1]
|
|
800746c: 2b03 cmp r3, #3
|
|
800746e: d008 beq.n 8007482 <USBD_StdEPReq+0x9a>
|
|
8007470: 2b03 cmp r3, #3
|
|
8007472: f300 8147 bgt.w 8007704 <USBD_StdEPReq+0x31c>
|
|
8007476: 2b00 cmp r3, #0
|
|
8007478: f000 809b beq.w 80075b2 <USBD_StdEPReq+0x1ca>
|
|
800747c: 2b01 cmp r3, #1
|
|
800747e: d03c beq.n 80074fa <USBD_StdEPReq+0x112>
|
|
8007480: e140 b.n 8007704 <USBD_StdEPReq+0x31c>
|
|
{
|
|
case USB_REQ_SET_FEATURE:
|
|
switch (pdev->dev_state)
|
|
8007482: 687b ldr r3, [r7, #4]
|
|
8007484: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007488: b2db uxtb r3, r3
|
|
800748a: 2b02 cmp r3, #2
|
|
800748c: d002 beq.n 8007494 <USBD_StdEPReq+0xac>
|
|
800748e: 2b03 cmp r3, #3
|
|
8007490: d016 beq.n 80074c0 <USBD_StdEPReq+0xd8>
|
|
8007492: e02c b.n 80074ee <USBD_StdEPReq+0x106>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
8007494: 7bbb ldrb r3, [r7, #14]
|
|
8007496: 2b00 cmp r3, #0
|
|
8007498: d00d beq.n 80074b6 <USBD_StdEPReq+0xce>
|
|
800749a: 7bbb ldrb r3, [r7, #14]
|
|
800749c: 2b80 cmp r3, #128 @ 0x80
|
|
800749e: d00a beq.n 80074b6 <USBD_StdEPReq+0xce>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
80074a0: 7bbb ldrb r3, [r7, #14]
|
|
80074a2: 4619 mov r1, r3
|
|
80074a4: 6878 ldr r0, [r7, #4]
|
|
80074a6: f001 f8e3 bl 8008670 <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
80074aa: 2180 movs r1, #128 @ 0x80
|
|
80074ac: 6878 ldr r0, [r7, #4]
|
|
80074ae: f001 f8df bl 8008670 <USBD_LL_StallEP>
|
|
80074b2: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
80074b4: e020 b.n 80074f8 <USBD_StdEPReq+0x110>
|
|
USBD_CtlError(pdev, req);
|
|
80074b6: 6839 ldr r1, [r7, #0]
|
|
80074b8: 6878 ldr r0, [r7, #4]
|
|
80074ba: f000 fca6 bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
80074be: e01b b.n 80074f8 <USBD_StdEPReq+0x110>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
80074c0: 683b ldr r3, [r7, #0]
|
|
80074c2: 885b ldrh r3, [r3, #2]
|
|
80074c4: 2b00 cmp r3, #0
|
|
80074c6: d10e bne.n 80074e6 <USBD_StdEPReq+0xfe>
|
|
{
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U))
|
|
80074c8: 7bbb ldrb r3, [r7, #14]
|
|
80074ca: 2b00 cmp r3, #0
|
|
80074cc: d00b beq.n 80074e6 <USBD_StdEPReq+0xfe>
|
|
80074ce: 7bbb ldrb r3, [r7, #14]
|
|
80074d0: 2b80 cmp r3, #128 @ 0x80
|
|
80074d2: d008 beq.n 80074e6 <USBD_StdEPReq+0xfe>
|
|
80074d4: 683b ldr r3, [r7, #0]
|
|
80074d6: 88db ldrh r3, [r3, #6]
|
|
80074d8: 2b00 cmp r3, #0
|
|
80074da: d104 bne.n 80074e6 <USBD_StdEPReq+0xfe>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
80074dc: 7bbb ldrb r3, [r7, #14]
|
|
80074de: 4619 mov r1, r3
|
|
80074e0: 6878 ldr r0, [r7, #4]
|
|
80074e2: f001 f8c5 bl 8008670 <USBD_LL_StallEP>
|
|
}
|
|
}
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80074e6: 6878 ldr r0, [r7, #4]
|
|
80074e8: f000 fd4c bl 8007f84 <USBD_CtlSendStatus>
|
|
|
|
break;
|
|
80074ec: e004 b.n 80074f8 <USBD_StdEPReq+0x110>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80074ee: 6839 ldr r1, [r7, #0]
|
|
80074f0: 6878 ldr r0, [r7, #4]
|
|
80074f2: f000 fc8a bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
80074f6: bf00 nop
|
|
}
|
|
break;
|
|
80074f8: e109 b.n 800770e <USBD_StdEPReq+0x326>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
|
|
switch (pdev->dev_state)
|
|
80074fa: 687b ldr r3, [r7, #4]
|
|
80074fc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007500: b2db uxtb r3, r3
|
|
8007502: 2b02 cmp r3, #2
|
|
8007504: d002 beq.n 800750c <USBD_StdEPReq+0x124>
|
|
8007506: 2b03 cmp r3, #3
|
|
8007508: d016 beq.n 8007538 <USBD_StdEPReq+0x150>
|
|
800750a: e04b b.n 80075a4 <USBD_StdEPReq+0x1bc>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
800750c: 7bbb ldrb r3, [r7, #14]
|
|
800750e: 2b00 cmp r3, #0
|
|
8007510: d00d beq.n 800752e <USBD_StdEPReq+0x146>
|
|
8007512: 7bbb ldrb r3, [r7, #14]
|
|
8007514: 2b80 cmp r3, #128 @ 0x80
|
|
8007516: d00a beq.n 800752e <USBD_StdEPReq+0x146>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
8007518: 7bbb ldrb r3, [r7, #14]
|
|
800751a: 4619 mov r1, r3
|
|
800751c: 6878 ldr r0, [r7, #4]
|
|
800751e: f001 f8a7 bl 8008670 <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8007522: 2180 movs r1, #128 @ 0x80
|
|
8007524: 6878 ldr r0, [r7, #4]
|
|
8007526: f001 f8a3 bl 8008670 <USBD_LL_StallEP>
|
|
800752a: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
800752c: e040 b.n 80075b0 <USBD_StdEPReq+0x1c8>
|
|
USBD_CtlError(pdev, req);
|
|
800752e: 6839 ldr r1, [r7, #0]
|
|
8007530: 6878 ldr r0, [r7, #4]
|
|
8007532: f000 fc6a bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
8007536: e03b b.n 80075b0 <USBD_StdEPReq+0x1c8>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
8007538: 683b ldr r3, [r7, #0]
|
|
800753a: 885b ldrh r3, [r3, #2]
|
|
800753c: 2b00 cmp r3, #0
|
|
800753e: d136 bne.n 80075ae <USBD_StdEPReq+0x1c6>
|
|
{
|
|
if ((ep_addr & 0x7FU) != 0x00U)
|
|
8007540: 7bbb ldrb r3, [r7, #14]
|
|
8007542: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8007546: 2b00 cmp r3, #0
|
|
8007548: d004 beq.n 8007554 <USBD_StdEPReq+0x16c>
|
|
{
|
|
(void)USBD_LL_ClearStallEP(pdev, ep_addr);
|
|
800754a: 7bbb ldrb r3, [r7, #14]
|
|
800754c: 4619 mov r1, r3
|
|
800754e: 6878 ldr r0, [r7, #4]
|
|
8007550: f001 f8ad bl 80086ae <USBD_LL_ClearStallEP>
|
|
}
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8007554: 6878 ldr r0, [r7, #4]
|
|
8007556: f000 fd15 bl 8007f84 <USBD_CtlSendStatus>
|
|
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, ep_addr);
|
|
800755a: 7bbb ldrb r3, [r7, #14]
|
|
800755c: 4619 mov r1, r3
|
|
800755e: 6878 ldr r0, [r7, #4]
|
|
8007560: f7ff fde3 bl 800712a <USBD_CoreFindEP>
|
|
8007564: 4603 mov r3, r0
|
|
8007566: 737b strb r3, [r7, #13]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8007568: 7b7b ldrb r3, [r7, #13]
|
|
800756a: 2bff cmp r3, #255 @ 0xff
|
|
800756c: d01f beq.n 80075ae <USBD_StdEPReq+0x1c6>
|
|
800756e: 7b7b ldrb r3, [r7, #13]
|
|
8007570: 2b00 cmp r3, #0
|
|
8007572: d11c bne.n 80075ae <USBD_StdEPReq+0x1c6>
|
|
{
|
|
pdev->classId = idx;
|
|
8007574: 7b7a ldrb r2, [r7, #13]
|
|
8007576: 687b ldr r3, [r7, #4]
|
|
8007578: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
800757c: 7b7a ldrb r2, [r7, #13]
|
|
800757e: 687b ldr r3, [r7, #4]
|
|
8007580: 32ae adds r2, #174 @ 0xae
|
|
8007582: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007586: 689b ldr r3, [r3, #8]
|
|
8007588: 2b00 cmp r3, #0
|
|
800758a: d010 beq.n 80075ae <USBD_StdEPReq+0x1c6>
|
|
{
|
|
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
|
|
800758c: 7b7a ldrb r2, [r7, #13]
|
|
800758e: 687b ldr r3, [r7, #4]
|
|
8007590: 32ae adds r2, #174 @ 0xae
|
|
8007592: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007596: 689b ldr r3, [r3, #8]
|
|
8007598: 6839 ldr r1, [r7, #0]
|
|
800759a: 6878 ldr r0, [r7, #4]
|
|
800759c: 4798 blx r3
|
|
800759e: 4603 mov r3, r0
|
|
80075a0: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
80075a2: e004 b.n 80075ae <USBD_StdEPReq+0x1c6>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80075a4: 6839 ldr r1, [r7, #0]
|
|
80075a6: 6878 ldr r0, [r7, #4]
|
|
80075a8: f000 fc2f bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
80075ac: e000 b.n 80075b0 <USBD_StdEPReq+0x1c8>
|
|
break;
|
|
80075ae: bf00 nop
|
|
}
|
|
break;
|
|
80075b0: e0ad b.n 800770e <USBD_StdEPReq+0x326>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
switch (pdev->dev_state)
|
|
80075b2: 687b ldr r3, [r7, #4]
|
|
80075b4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80075b8: b2db uxtb r3, r3
|
|
80075ba: 2b02 cmp r3, #2
|
|
80075bc: d002 beq.n 80075c4 <USBD_StdEPReq+0x1dc>
|
|
80075be: 2b03 cmp r3, #3
|
|
80075c0: d033 beq.n 800762a <USBD_StdEPReq+0x242>
|
|
80075c2: e099 b.n 80076f8 <USBD_StdEPReq+0x310>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
80075c4: 7bbb ldrb r3, [r7, #14]
|
|
80075c6: 2b00 cmp r3, #0
|
|
80075c8: d007 beq.n 80075da <USBD_StdEPReq+0x1f2>
|
|
80075ca: 7bbb ldrb r3, [r7, #14]
|
|
80075cc: 2b80 cmp r3, #128 @ 0x80
|
|
80075ce: d004 beq.n 80075da <USBD_StdEPReq+0x1f2>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80075d0: 6839 ldr r1, [r7, #0]
|
|
80075d2: 6878 ldr r0, [r7, #4]
|
|
80075d4: f000 fc19 bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
80075d8: e093 b.n 8007702 <USBD_StdEPReq+0x31a>
|
|
}
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
80075da: f997 300e ldrsb.w r3, [r7, #14]
|
|
80075de: 2b00 cmp r3, #0
|
|
80075e0: da0b bge.n 80075fa <USBD_StdEPReq+0x212>
|
|
80075e2: 7bbb ldrb r3, [r7, #14]
|
|
80075e4: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
80075e8: 4613 mov r3, r2
|
|
80075ea: 009b lsls r3, r3, #2
|
|
80075ec: 4413 add r3, r2
|
|
80075ee: 009b lsls r3, r3, #2
|
|
80075f0: 3310 adds r3, #16
|
|
80075f2: 687a ldr r2, [r7, #4]
|
|
80075f4: 4413 add r3, r2
|
|
80075f6: 3304 adds r3, #4
|
|
80075f8: e00b b.n 8007612 <USBD_StdEPReq+0x22a>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
80075fa: 7bbb ldrb r3, [r7, #14]
|
|
80075fc: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
8007600: 4613 mov r3, r2
|
|
8007602: 009b lsls r3, r3, #2
|
|
8007604: 4413 add r3, r2
|
|
8007606: 009b lsls r3, r3, #2
|
|
8007608: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
800760c: 687a ldr r2, [r7, #4]
|
|
800760e: 4413 add r3, r2
|
|
8007610: 3304 adds r3, #4
|
|
8007612: 60bb str r3, [r7, #8]
|
|
|
|
pep->status = 0x0000U;
|
|
8007614: 68bb ldr r3, [r7, #8]
|
|
8007616: 2200 movs r2, #0
|
|
8007618: 739a strb r2, [r3, #14]
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
|
|
800761a: 68bb ldr r3, [r7, #8]
|
|
800761c: 330e adds r3, #14
|
|
800761e: 2202 movs r2, #2
|
|
8007620: 4619 mov r1, r3
|
|
8007622: 6878 ldr r0, [r7, #4]
|
|
8007624: f000 fc6e bl 8007f04 <USBD_CtlSendData>
|
|
break;
|
|
8007628: e06b b.n 8007702 <USBD_StdEPReq+0x31a>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
800762a: f997 300e ldrsb.w r3, [r7, #14]
|
|
800762e: 2b00 cmp r3, #0
|
|
8007630: da11 bge.n 8007656 <USBD_StdEPReq+0x26e>
|
|
{
|
|
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
|
|
8007632: 7bbb ldrb r3, [r7, #14]
|
|
8007634: f003 020f and.w r2, r3, #15
|
|
8007638: 6879 ldr r1, [r7, #4]
|
|
800763a: 4613 mov r3, r2
|
|
800763c: 009b lsls r3, r3, #2
|
|
800763e: 4413 add r3, r2
|
|
8007640: 009b lsls r3, r3, #2
|
|
8007642: 440b add r3, r1
|
|
8007644: 3323 adds r3, #35 @ 0x23
|
|
8007646: 781b ldrb r3, [r3, #0]
|
|
8007648: 2b00 cmp r3, #0
|
|
800764a: d117 bne.n 800767c <USBD_StdEPReq+0x294>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
800764c: 6839 ldr r1, [r7, #0]
|
|
800764e: 6878 ldr r0, [r7, #4]
|
|
8007650: f000 fbdb bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
8007654: e055 b.n 8007702 <USBD_StdEPReq+0x31a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
|
|
8007656: 7bbb ldrb r3, [r7, #14]
|
|
8007658: f003 020f and.w r2, r3, #15
|
|
800765c: 6879 ldr r1, [r7, #4]
|
|
800765e: 4613 mov r3, r2
|
|
8007660: 009b lsls r3, r3, #2
|
|
8007662: 4413 add r3, r2
|
|
8007664: 009b lsls r3, r3, #2
|
|
8007666: 440b add r3, r1
|
|
8007668: f203 1363 addw r3, r3, #355 @ 0x163
|
|
800766c: 781b ldrb r3, [r3, #0]
|
|
800766e: 2b00 cmp r3, #0
|
|
8007670: d104 bne.n 800767c <USBD_StdEPReq+0x294>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8007672: 6839 ldr r1, [r7, #0]
|
|
8007674: 6878 ldr r0, [r7, #4]
|
|
8007676: f000 fbc8 bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
800767a: e042 b.n 8007702 <USBD_StdEPReq+0x31a>
|
|
}
|
|
}
|
|
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
800767c: f997 300e ldrsb.w r3, [r7, #14]
|
|
8007680: 2b00 cmp r3, #0
|
|
8007682: da0b bge.n 800769c <USBD_StdEPReq+0x2b4>
|
|
8007684: 7bbb ldrb r3, [r7, #14]
|
|
8007686: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
800768a: 4613 mov r3, r2
|
|
800768c: 009b lsls r3, r3, #2
|
|
800768e: 4413 add r3, r2
|
|
8007690: 009b lsls r3, r3, #2
|
|
8007692: 3310 adds r3, #16
|
|
8007694: 687a ldr r2, [r7, #4]
|
|
8007696: 4413 add r3, r2
|
|
8007698: 3304 adds r3, #4
|
|
800769a: e00b b.n 80076b4 <USBD_StdEPReq+0x2cc>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
800769c: 7bbb ldrb r3, [r7, #14]
|
|
800769e: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
80076a2: 4613 mov r3, r2
|
|
80076a4: 009b lsls r3, r3, #2
|
|
80076a6: 4413 add r3, r2
|
|
80076a8: 009b lsls r3, r3, #2
|
|
80076aa: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
80076ae: 687a ldr r2, [r7, #4]
|
|
80076b0: 4413 add r3, r2
|
|
80076b2: 3304 adds r3, #4
|
|
80076b4: 60bb str r3, [r7, #8]
|
|
|
|
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
|
|
80076b6: 7bbb ldrb r3, [r7, #14]
|
|
80076b8: 2b00 cmp r3, #0
|
|
80076ba: d002 beq.n 80076c2 <USBD_StdEPReq+0x2da>
|
|
80076bc: 7bbb ldrb r3, [r7, #14]
|
|
80076be: 2b80 cmp r3, #128 @ 0x80
|
|
80076c0: d103 bne.n 80076ca <USBD_StdEPReq+0x2e2>
|
|
{
|
|
pep->status = 0x0000U;
|
|
80076c2: 68bb ldr r3, [r7, #8]
|
|
80076c4: 2200 movs r2, #0
|
|
80076c6: 739a strb r2, [r3, #14]
|
|
80076c8: e00e b.n 80076e8 <USBD_StdEPReq+0x300>
|
|
}
|
|
else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U)
|
|
80076ca: 7bbb ldrb r3, [r7, #14]
|
|
80076cc: 4619 mov r1, r3
|
|
80076ce: 6878 ldr r0, [r7, #4]
|
|
80076d0: f001 f80c bl 80086ec <USBD_LL_IsStallEP>
|
|
80076d4: 4603 mov r3, r0
|
|
80076d6: 2b00 cmp r3, #0
|
|
80076d8: d003 beq.n 80076e2 <USBD_StdEPReq+0x2fa>
|
|
{
|
|
pep->status = 0x0001U;
|
|
80076da: 68bb ldr r3, [r7, #8]
|
|
80076dc: 2201 movs r2, #1
|
|
80076de: 739a strb r2, [r3, #14]
|
|
80076e0: e002 b.n 80076e8 <USBD_StdEPReq+0x300>
|
|
}
|
|
else
|
|
{
|
|
pep->status = 0x0000U;
|
|
80076e2: 68bb ldr r3, [r7, #8]
|
|
80076e4: 2200 movs r2, #0
|
|
80076e6: 739a strb r2, [r3, #14]
|
|
}
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
|
|
80076e8: 68bb ldr r3, [r7, #8]
|
|
80076ea: 330e adds r3, #14
|
|
80076ec: 2202 movs r2, #2
|
|
80076ee: 4619 mov r1, r3
|
|
80076f0: 6878 ldr r0, [r7, #4]
|
|
80076f2: f000 fc07 bl 8007f04 <USBD_CtlSendData>
|
|
break;
|
|
80076f6: e004 b.n 8007702 <USBD_StdEPReq+0x31a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80076f8: 6839 ldr r1, [r7, #0]
|
|
80076fa: 6878 ldr r0, [r7, #4]
|
|
80076fc: f000 fb85 bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
8007700: bf00 nop
|
|
}
|
|
break;
|
|
8007702: e004 b.n 800770e <USBD_StdEPReq+0x326>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007704: 6839 ldr r1, [r7, #0]
|
|
8007706: 6878 ldr r0, [r7, #4]
|
|
8007708: f000 fb7f bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
800770c: bf00 nop
|
|
}
|
|
break;
|
|
800770e: e005 b.n 800771c <USBD_StdEPReq+0x334>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007710: 6839 ldr r1, [r7, #0]
|
|
8007712: 6878 ldr r0, [r7, #4]
|
|
8007714: f000 fb79 bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
8007718: e000 b.n 800771c <USBD_StdEPReq+0x334>
|
|
break;
|
|
800771a: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
800771c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800771e: 4618 mov r0, r3
|
|
8007720: 3710 adds r7, #16
|
|
8007722: 46bd mov sp, r7
|
|
8007724: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08007728 <USBD_GetDescriptor>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007728: b580 push {r7, lr}
|
|
800772a: b084 sub sp, #16
|
|
800772c: af00 add r7, sp, #0
|
|
800772e: 6078 str r0, [r7, #4]
|
|
8007730: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
8007732: 2300 movs r3, #0
|
|
8007734: 813b strh r3, [r7, #8]
|
|
uint8_t *pbuf = NULL;
|
|
8007736: 2300 movs r3, #0
|
|
8007738: 60fb str r3, [r7, #12]
|
|
uint8_t err = 0U;
|
|
800773a: 2300 movs r3, #0
|
|
800773c: 72fb strb r3, [r7, #11]
|
|
|
|
switch (req->wValue >> 8)
|
|
800773e: 683b ldr r3, [r7, #0]
|
|
8007740: 885b ldrh r3, [r3, #2]
|
|
8007742: 0a1b lsrs r3, r3, #8
|
|
8007744: b29b uxth r3, r3
|
|
8007746: 3b01 subs r3, #1
|
|
8007748: 2b0e cmp r3, #14
|
|
800774a: f200 8152 bhi.w 80079f2 <USBD_GetDescriptor+0x2ca>
|
|
800774e: a201 add r2, pc, #4 @ (adr r2, 8007754 <USBD_GetDescriptor+0x2c>)
|
|
8007750: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8007754: 080077c5 .word 0x080077c5
|
|
8007758: 080077dd .word 0x080077dd
|
|
800775c: 0800781d .word 0x0800781d
|
|
8007760: 080079f3 .word 0x080079f3
|
|
8007764: 080079f3 .word 0x080079f3
|
|
8007768: 08007993 .word 0x08007993
|
|
800776c: 080079bf .word 0x080079bf
|
|
8007770: 080079f3 .word 0x080079f3
|
|
8007774: 080079f3 .word 0x080079f3
|
|
8007778: 080079f3 .word 0x080079f3
|
|
800777c: 080079f3 .word 0x080079f3
|
|
8007780: 080079f3 .word 0x080079f3
|
|
8007784: 080079f3 .word 0x080079f3
|
|
8007788: 080079f3 .word 0x080079f3
|
|
800778c: 08007791 .word 0x08007791
|
|
{
|
|
#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U))
|
|
case USB_DESC_TYPE_BOS:
|
|
if (pdev->pDesc->GetBOSDescriptor != NULL)
|
|
8007790: 687b ldr r3, [r7, #4]
|
|
8007792: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8007796: 69db ldr r3, [r3, #28]
|
|
8007798: 2b00 cmp r3, #0
|
|
800779a: d00b beq.n 80077b4 <USBD_GetDescriptor+0x8c>
|
|
{
|
|
pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
|
|
800779c: 687b ldr r3, [r7, #4]
|
|
800779e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80077a2: 69db ldr r3, [r3, #28]
|
|
80077a4: 687a ldr r2, [r7, #4]
|
|
80077a6: 7c12 ldrb r2, [r2, #16]
|
|
80077a8: f107 0108 add.w r1, r7, #8
|
|
80077ac: 4610 mov r0, r2
|
|
80077ae: 4798 blx r3
|
|
80077b0: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80077b2: e126 b.n 8007a02 <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
80077b4: 6839 ldr r1, [r7, #0]
|
|
80077b6: 6878 ldr r0, [r7, #4]
|
|
80077b8: f000 fb27 bl 8007e0a <USBD_CtlError>
|
|
err++;
|
|
80077bc: 7afb ldrb r3, [r7, #11]
|
|
80077be: 3301 adds r3, #1
|
|
80077c0: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80077c2: e11e b.n 8007a02 <USBD_GetDescriptor+0x2da>
|
|
#endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */
|
|
case USB_DESC_TYPE_DEVICE:
|
|
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
|
|
80077c4: 687b ldr r3, [r7, #4]
|
|
80077c6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80077ca: 681b ldr r3, [r3, #0]
|
|
80077cc: 687a ldr r2, [r7, #4]
|
|
80077ce: 7c12 ldrb r2, [r2, #16]
|
|
80077d0: f107 0108 add.w r1, r7, #8
|
|
80077d4: 4610 mov r0, r2
|
|
80077d6: 4798 blx r3
|
|
80077d8: 60f8 str r0, [r7, #12]
|
|
break;
|
|
80077da: e112 b.n 8007a02 <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
80077dc: 687b ldr r3, [r7, #4]
|
|
80077de: 7c1b ldrb r3, [r3, #16]
|
|
80077e0: 2b00 cmp r3, #0
|
|
80077e2: d10d bne.n 8007800 <USBD_GetDescriptor+0xd8>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len);
|
|
80077e4: 687b ldr r3, [r7, #4]
|
|
80077e6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80077ea: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80077ec: f107 0208 add.w r2, r7, #8
|
|
80077f0: 4610 mov r0, r2
|
|
80077f2: 4798 blx r3
|
|
80077f4: 60f8 str r0, [r7, #12]
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
80077f6: 68fb ldr r3, [r7, #12]
|
|
80077f8: 3301 adds r3, #1
|
|
80077fa: 2202 movs r2, #2
|
|
80077fc: 701a strb r2, [r3, #0]
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
}
|
|
break;
|
|
80077fe: e100 b.n 8007a02 <USBD_GetDescriptor+0x2da>
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
|
|
8007800: 687b ldr r3, [r7, #4]
|
|
8007802: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8007806: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007808: f107 0208 add.w r2, r7, #8
|
|
800780c: 4610 mov r0, r2
|
|
800780e: 4798 blx r3
|
|
8007810: 60f8 str r0, [r7, #12]
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
8007812: 68fb ldr r3, [r7, #12]
|
|
8007814: 3301 adds r3, #1
|
|
8007816: 2202 movs r2, #2
|
|
8007818: 701a strb r2, [r3, #0]
|
|
break;
|
|
800781a: e0f2 b.n 8007a02 <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_STRING:
|
|
switch ((uint8_t)(req->wValue))
|
|
800781c: 683b ldr r3, [r7, #0]
|
|
800781e: 885b ldrh r3, [r3, #2]
|
|
8007820: b2db uxtb r3, r3
|
|
8007822: 2b05 cmp r3, #5
|
|
8007824: f200 80ac bhi.w 8007980 <USBD_GetDescriptor+0x258>
|
|
8007828: a201 add r2, pc, #4 @ (adr r2, 8007830 <USBD_GetDescriptor+0x108>)
|
|
800782a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800782e: bf00 nop
|
|
8007830: 08007849 .word 0x08007849
|
|
8007834: 0800787d .word 0x0800787d
|
|
8007838: 080078b1 .word 0x080078b1
|
|
800783c: 080078e5 .word 0x080078e5
|
|
8007840: 08007919 .word 0x08007919
|
|
8007844: 0800794d .word 0x0800794d
|
|
{
|
|
case USBD_IDX_LANGID_STR:
|
|
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
|
|
8007848: 687b ldr r3, [r7, #4]
|
|
800784a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800784e: 685b ldr r3, [r3, #4]
|
|
8007850: 2b00 cmp r3, #0
|
|
8007852: d00b beq.n 800786c <USBD_GetDescriptor+0x144>
|
|
{
|
|
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
|
|
8007854: 687b ldr r3, [r7, #4]
|
|
8007856: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800785a: 685b ldr r3, [r3, #4]
|
|
800785c: 687a ldr r2, [r7, #4]
|
|
800785e: 7c12 ldrb r2, [r2, #16]
|
|
8007860: f107 0108 add.w r1, r7, #8
|
|
8007864: 4610 mov r0, r2
|
|
8007866: 4798 blx r3
|
|
8007868: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800786a: e091 b.n 8007990 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
800786c: 6839 ldr r1, [r7, #0]
|
|
800786e: 6878 ldr r0, [r7, #4]
|
|
8007870: f000 facb bl 8007e0a <USBD_CtlError>
|
|
err++;
|
|
8007874: 7afb ldrb r3, [r7, #11]
|
|
8007876: 3301 adds r3, #1
|
|
8007878: 72fb strb r3, [r7, #11]
|
|
break;
|
|
800787a: e089 b.n 8007990 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_MFC_STR:
|
|
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
|
|
800787c: 687b ldr r3, [r7, #4]
|
|
800787e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8007882: 689b ldr r3, [r3, #8]
|
|
8007884: 2b00 cmp r3, #0
|
|
8007886: d00b beq.n 80078a0 <USBD_GetDescriptor+0x178>
|
|
{
|
|
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
|
|
8007888: 687b ldr r3, [r7, #4]
|
|
800788a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800788e: 689b ldr r3, [r3, #8]
|
|
8007890: 687a ldr r2, [r7, #4]
|
|
8007892: 7c12 ldrb r2, [r2, #16]
|
|
8007894: f107 0108 add.w r1, r7, #8
|
|
8007898: 4610 mov r0, r2
|
|
800789a: 4798 blx r3
|
|
800789c: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800789e: e077 b.n 8007990 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
80078a0: 6839 ldr r1, [r7, #0]
|
|
80078a2: 6878 ldr r0, [r7, #4]
|
|
80078a4: f000 fab1 bl 8007e0a <USBD_CtlError>
|
|
err++;
|
|
80078a8: 7afb ldrb r3, [r7, #11]
|
|
80078aa: 3301 adds r3, #1
|
|
80078ac: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80078ae: e06f b.n 8007990 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_PRODUCT_STR:
|
|
if (pdev->pDesc->GetProductStrDescriptor != NULL)
|
|
80078b0: 687b ldr r3, [r7, #4]
|
|
80078b2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80078b6: 68db ldr r3, [r3, #12]
|
|
80078b8: 2b00 cmp r3, #0
|
|
80078ba: d00b beq.n 80078d4 <USBD_GetDescriptor+0x1ac>
|
|
{
|
|
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
|
|
80078bc: 687b ldr r3, [r7, #4]
|
|
80078be: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80078c2: 68db ldr r3, [r3, #12]
|
|
80078c4: 687a ldr r2, [r7, #4]
|
|
80078c6: 7c12 ldrb r2, [r2, #16]
|
|
80078c8: f107 0108 add.w r1, r7, #8
|
|
80078cc: 4610 mov r0, r2
|
|
80078ce: 4798 blx r3
|
|
80078d0: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80078d2: e05d b.n 8007990 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
80078d4: 6839 ldr r1, [r7, #0]
|
|
80078d6: 6878 ldr r0, [r7, #4]
|
|
80078d8: f000 fa97 bl 8007e0a <USBD_CtlError>
|
|
err++;
|
|
80078dc: 7afb ldrb r3, [r7, #11]
|
|
80078de: 3301 adds r3, #1
|
|
80078e0: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80078e2: e055 b.n 8007990 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_SERIAL_STR:
|
|
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
|
|
80078e4: 687b ldr r3, [r7, #4]
|
|
80078e6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80078ea: 691b ldr r3, [r3, #16]
|
|
80078ec: 2b00 cmp r3, #0
|
|
80078ee: d00b beq.n 8007908 <USBD_GetDescriptor+0x1e0>
|
|
{
|
|
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
|
|
80078f0: 687b ldr r3, [r7, #4]
|
|
80078f2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80078f6: 691b ldr r3, [r3, #16]
|
|
80078f8: 687a ldr r2, [r7, #4]
|
|
80078fa: 7c12 ldrb r2, [r2, #16]
|
|
80078fc: f107 0108 add.w r1, r7, #8
|
|
8007900: 4610 mov r0, r2
|
|
8007902: 4798 blx r3
|
|
8007904: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8007906: e043 b.n 8007990 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8007908: 6839 ldr r1, [r7, #0]
|
|
800790a: 6878 ldr r0, [r7, #4]
|
|
800790c: f000 fa7d bl 8007e0a <USBD_CtlError>
|
|
err++;
|
|
8007910: 7afb ldrb r3, [r7, #11]
|
|
8007912: 3301 adds r3, #1
|
|
8007914: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8007916: e03b b.n 8007990 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_CONFIG_STR:
|
|
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
|
|
8007918: 687b ldr r3, [r7, #4]
|
|
800791a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800791e: 695b ldr r3, [r3, #20]
|
|
8007920: 2b00 cmp r3, #0
|
|
8007922: d00b beq.n 800793c <USBD_GetDescriptor+0x214>
|
|
{
|
|
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
|
|
8007924: 687b ldr r3, [r7, #4]
|
|
8007926: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800792a: 695b ldr r3, [r3, #20]
|
|
800792c: 687a ldr r2, [r7, #4]
|
|
800792e: 7c12 ldrb r2, [r2, #16]
|
|
8007930: f107 0108 add.w r1, r7, #8
|
|
8007934: 4610 mov r0, r2
|
|
8007936: 4798 blx r3
|
|
8007938: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800793a: e029 b.n 8007990 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
800793c: 6839 ldr r1, [r7, #0]
|
|
800793e: 6878 ldr r0, [r7, #4]
|
|
8007940: f000 fa63 bl 8007e0a <USBD_CtlError>
|
|
err++;
|
|
8007944: 7afb ldrb r3, [r7, #11]
|
|
8007946: 3301 adds r3, #1
|
|
8007948: 72fb strb r3, [r7, #11]
|
|
break;
|
|
800794a: e021 b.n 8007990 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_INTERFACE_STR:
|
|
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
|
|
800794c: 687b ldr r3, [r7, #4]
|
|
800794e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8007952: 699b ldr r3, [r3, #24]
|
|
8007954: 2b00 cmp r3, #0
|
|
8007956: d00b beq.n 8007970 <USBD_GetDescriptor+0x248>
|
|
{
|
|
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
|
|
8007958: 687b ldr r3, [r7, #4]
|
|
800795a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800795e: 699b ldr r3, [r3, #24]
|
|
8007960: 687a ldr r2, [r7, #4]
|
|
8007962: 7c12 ldrb r2, [r2, #16]
|
|
8007964: f107 0108 add.w r1, r7, #8
|
|
8007968: 4610 mov r0, r2
|
|
800796a: 4798 blx r3
|
|
800796c: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800796e: e00f b.n 8007990 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8007970: 6839 ldr r1, [r7, #0]
|
|
8007972: 6878 ldr r0, [r7, #4]
|
|
8007974: f000 fa49 bl 8007e0a <USBD_CtlError>
|
|
err++;
|
|
8007978: 7afb ldrb r3, [r7, #11]
|
|
800797a: 3301 adds r3, #1
|
|
800797c: 72fb strb r3, [r7, #11]
|
|
break;
|
|
800797e: e007 b.n 8007990 <USBD_GetDescriptor+0x268>
|
|
err++;
|
|
}
|
|
#endif /* USBD_SUPPORT_USER_STRING_DESC */
|
|
|
|
#if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U))
|
|
USBD_CtlError(pdev, req);
|
|
8007980: 6839 ldr r1, [r7, #0]
|
|
8007982: 6878 ldr r0, [r7, #4]
|
|
8007984: f000 fa41 bl 8007e0a <USBD_CtlError>
|
|
err++;
|
|
8007988: 7afb ldrb r3, [r7, #11]
|
|
800798a: 3301 adds r3, #1
|
|
800798c: 72fb strb r3, [r7, #11]
|
|
#endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */
|
|
break;
|
|
800798e: bf00 nop
|
|
}
|
|
break;
|
|
8007990: e037 b.n 8007a02 <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_DEVICE_QUALIFIER:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8007992: 687b ldr r3, [r7, #4]
|
|
8007994: 7c1b ldrb r3, [r3, #16]
|
|
8007996: 2b00 cmp r3, #0
|
|
8007998: d109 bne.n 80079ae <USBD_GetDescriptor+0x286>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len);
|
|
800799a: 687b ldr r3, [r7, #4]
|
|
800799c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80079a0: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80079a2: f107 0208 add.w r2, r7, #8
|
|
80079a6: 4610 mov r0, r2
|
|
80079a8: 4798 blx r3
|
|
80079aa: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80079ac: e029 b.n 8007a02 <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
80079ae: 6839 ldr r1, [r7, #0]
|
|
80079b0: 6878 ldr r0, [r7, #4]
|
|
80079b2: f000 fa2a bl 8007e0a <USBD_CtlError>
|
|
err++;
|
|
80079b6: 7afb ldrb r3, [r7, #11]
|
|
80079b8: 3301 adds r3, #1
|
|
80079ba: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80079bc: e021 b.n 8007a02 <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
80079be: 687b ldr r3, [r7, #4]
|
|
80079c0: 7c1b ldrb r3, [r3, #16]
|
|
80079c2: 2b00 cmp r3, #0
|
|
80079c4: d10d bne.n 80079e2 <USBD_GetDescriptor+0x2ba>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len);
|
|
80079c6: 687b ldr r3, [r7, #4]
|
|
80079c8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80079cc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80079ce: f107 0208 add.w r2, r7, #8
|
|
80079d2: 4610 mov r0, r2
|
|
80079d4: 4798 blx r3
|
|
80079d6: 60f8 str r0, [r7, #12]
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
|
|
80079d8: 68fb ldr r3, [r7, #12]
|
|
80079da: 3301 adds r3, #1
|
|
80079dc: 2207 movs r2, #7
|
|
80079de: 701a strb r2, [r3, #0]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80079e0: e00f b.n 8007a02 <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
80079e2: 6839 ldr r1, [r7, #0]
|
|
80079e4: 6878 ldr r0, [r7, #4]
|
|
80079e6: f000 fa10 bl 8007e0a <USBD_CtlError>
|
|
err++;
|
|
80079ea: 7afb ldrb r3, [r7, #11]
|
|
80079ec: 3301 adds r3, #1
|
|
80079ee: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80079f0: e007 b.n 8007a02 <USBD_GetDescriptor+0x2da>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80079f2: 6839 ldr r1, [r7, #0]
|
|
80079f4: 6878 ldr r0, [r7, #4]
|
|
80079f6: f000 fa08 bl 8007e0a <USBD_CtlError>
|
|
err++;
|
|
80079fa: 7afb ldrb r3, [r7, #11]
|
|
80079fc: 3301 adds r3, #1
|
|
80079fe: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8007a00: bf00 nop
|
|
}
|
|
|
|
if (err != 0U)
|
|
8007a02: 7afb ldrb r3, [r7, #11]
|
|
8007a04: 2b00 cmp r3, #0
|
|
8007a06: d11e bne.n 8007a46 <USBD_GetDescriptor+0x31e>
|
|
{
|
|
return;
|
|
}
|
|
|
|
if (req->wLength != 0U)
|
|
8007a08: 683b ldr r3, [r7, #0]
|
|
8007a0a: 88db ldrh r3, [r3, #6]
|
|
8007a0c: 2b00 cmp r3, #0
|
|
8007a0e: d016 beq.n 8007a3e <USBD_GetDescriptor+0x316>
|
|
{
|
|
if (len != 0U)
|
|
8007a10: 893b ldrh r3, [r7, #8]
|
|
8007a12: 2b00 cmp r3, #0
|
|
8007a14: d00e beq.n 8007a34 <USBD_GetDescriptor+0x30c>
|
|
{
|
|
len = MIN(len, req->wLength);
|
|
8007a16: 683b ldr r3, [r7, #0]
|
|
8007a18: 88da ldrh r2, [r3, #6]
|
|
8007a1a: 893b ldrh r3, [r7, #8]
|
|
8007a1c: 4293 cmp r3, r2
|
|
8007a1e: bf28 it cs
|
|
8007a20: 4613 movcs r3, r2
|
|
8007a22: b29b uxth r3, r3
|
|
8007a24: 813b strh r3, [r7, #8]
|
|
(void)USBD_CtlSendData(pdev, pbuf, len);
|
|
8007a26: 893b ldrh r3, [r7, #8]
|
|
8007a28: 461a mov r2, r3
|
|
8007a2a: 68f9 ldr r1, [r7, #12]
|
|
8007a2c: 6878 ldr r0, [r7, #4]
|
|
8007a2e: f000 fa69 bl 8007f04 <USBD_CtlSendData>
|
|
8007a32: e009 b.n 8007a48 <USBD_GetDescriptor+0x320>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8007a34: 6839 ldr r1, [r7, #0]
|
|
8007a36: 6878 ldr r0, [r7, #4]
|
|
8007a38: f000 f9e7 bl 8007e0a <USBD_CtlError>
|
|
8007a3c: e004 b.n 8007a48 <USBD_GetDescriptor+0x320>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8007a3e: 6878 ldr r0, [r7, #4]
|
|
8007a40: f000 faa0 bl 8007f84 <USBD_CtlSendStatus>
|
|
8007a44: e000 b.n 8007a48 <USBD_GetDescriptor+0x320>
|
|
return;
|
|
8007a46: bf00 nop
|
|
}
|
|
}
|
|
8007a48: 3710 adds r7, #16
|
|
8007a4a: 46bd mov sp, r7
|
|
8007a4c: bd80 pop {r7, pc}
|
|
8007a4e: bf00 nop
|
|
|
|
08007a50 <USBD_SetAddress>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007a50: b580 push {r7, lr}
|
|
8007a52: b084 sub sp, #16
|
|
8007a54: af00 add r7, sp, #0
|
|
8007a56: 6078 str r0, [r7, #4]
|
|
8007a58: 6039 str r1, [r7, #0]
|
|
uint8_t dev_addr;
|
|
|
|
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
|
|
8007a5a: 683b ldr r3, [r7, #0]
|
|
8007a5c: 889b ldrh r3, [r3, #4]
|
|
8007a5e: 2b00 cmp r3, #0
|
|
8007a60: d131 bne.n 8007ac6 <USBD_SetAddress+0x76>
|
|
8007a62: 683b ldr r3, [r7, #0]
|
|
8007a64: 88db ldrh r3, [r3, #6]
|
|
8007a66: 2b00 cmp r3, #0
|
|
8007a68: d12d bne.n 8007ac6 <USBD_SetAddress+0x76>
|
|
8007a6a: 683b ldr r3, [r7, #0]
|
|
8007a6c: 885b ldrh r3, [r3, #2]
|
|
8007a6e: 2b7f cmp r3, #127 @ 0x7f
|
|
8007a70: d829 bhi.n 8007ac6 <USBD_SetAddress+0x76>
|
|
{
|
|
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
|
|
8007a72: 683b ldr r3, [r7, #0]
|
|
8007a74: 885b ldrh r3, [r3, #2]
|
|
8007a76: b2db uxtb r3, r3
|
|
8007a78: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8007a7c: 73fb strb r3, [r7, #15]
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007a7e: 687b ldr r3, [r7, #4]
|
|
8007a80: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007a84: b2db uxtb r3, r3
|
|
8007a86: 2b03 cmp r3, #3
|
|
8007a88: d104 bne.n 8007a94 <USBD_SetAddress+0x44>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8007a8a: 6839 ldr r1, [r7, #0]
|
|
8007a8c: 6878 ldr r0, [r7, #4]
|
|
8007a8e: f000 f9bc bl 8007e0a <USBD_CtlError>
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007a92: e01d b.n 8007ad0 <USBD_SetAddress+0x80>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_address = dev_addr;
|
|
8007a94: 687b ldr r3, [r7, #4]
|
|
8007a96: 7bfa ldrb r2, [r7, #15]
|
|
8007a98: f883 229e strb.w r2, [r3, #670] @ 0x29e
|
|
(void)USBD_LL_SetUSBAddress(pdev, dev_addr);
|
|
8007a9c: 7bfb ldrb r3, [r7, #15]
|
|
8007a9e: 4619 mov r1, r3
|
|
8007aa0: 6878 ldr r0, [r7, #4]
|
|
8007aa2: f000 fe4f bl 8008744 <USBD_LL_SetUSBAddress>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8007aa6: 6878 ldr r0, [r7, #4]
|
|
8007aa8: f000 fa6c bl 8007f84 <USBD_CtlSendStatus>
|
|
|
|
if (dev_addr != 0U)
|
|
8007aac: 7bfb ldrb r3, [r7, #15]
|
|
8007aae: 2b00 cmp r3, #0
|
|
8007ab0: d004 beq.n 8007abc <USBD_SetAddress+0x6c>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8007ab2: 687b ldr r3, [r7, #4]
|
|
8007ab4: 2202 movs r2, #2
|
|
8007ab6: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007aba: e009 b.n 8007ad0 <USBD_SetAddress+0x80>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8007abc: 687b ldr r3, [r7, #4]
|
|
8007abe: 2201 movs r2, #1
|
|
8007ac0: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8007ac4: e004 b.n 8007ad0 <USBD_SetAddress+0x80>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8007ac6: 6839 ldr r1, [r7, #0]
|
|
8007ac8: 6878 ldr r0, [r7, #4]
|
|
8007aca: f000 f99e bl 8007e0a <USBD_CtlError>
|
|
}
|
|
}
|
|
8007ace: bf00 nop
|
|
8007ad0: bf00 nop
|
|
8007ad2: 3710 adds r7, #16
|
|
8007ad4: 46bd mov sp, r7
|
|
8007ad6: bd80 pop {r7, pc}
|
|
|
|
08007ad8 <USBD_SetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007ad8: b580 push {r7, lr}
|
|
8007ada: b084 sub sp, #16
|
|
8007adc: af00 add r7, sp, #0
|
|
8007ade: 6078 str r0, [r7, #4]
|
|
8007ae0: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8007ae2: 2300 movs r3, #0
|
|
8007ae4: 73fb strb r3, [r7, #15]
|
|
static uint8_t cfgidx;
|
|
|
|
cfgidx = (uint8_t)(req->wValue);
|
|
8007ae6: 683b ldr r3, [r7, #0]
|
|
8007ae8: 885b ldrh r3, [r3, #2]
|
|
8007aea: b2da uxtb r2, r3
|
|
8007aec: 4b4e ldr r3, [pc, #312] @ (8007c28 <USBD_SetConfig+0x150>)
|
|
8007aee: 701a strb r2, [r3, #0]
|
|
|
|
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
|
|
8007af0: 4b4d ldr r3, [pc, #308] @ (8007c28 <USBD_SetConfig+0x150>)
|
|
8007af2: 781b ldrb r3, [r3, #0]
|
|
8007af4: 2b01 cmp r3, #1
|
|
8007af6: d905 bls.n 8007b04 <USBD_SetConfig+0x2c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8007af8: 6839 ldr r1, [r7, #0]
|
|
8007afa: 6878 ldr r0, [r7, #4]
|
|
8007afc: f000 f985 bl 8007e0a <USBD_CtlError>
|
|
return USBD_FAIL;
|
|
8007b00: 2303 movs r3, #3
|
|
8007b02: e08c b.n 8007c1e <USBD_SetConfig+0x146>
|
|
}
|
|
|
|
switch (pdev->dev_state)
|
|
8007b04: 687b ldr r3, [r7, #4]
|
|
8007b06: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007b0a: b2db uxtb r3, r3
|
|
8007b0c: 2b02 cmp r3, #2
|
|
8007b0e: d002 beq.n 8007b16 <USBD_SetConfig+0x3e>
|
|
8007b10: 2b03 cmp r3, #3
|
|
8007b12: d029 beq.n 8007b68 <USBD_SetConfig+0x90>
|
|
8007b14: e075 b.n 8007c02 <USBD_SetConfig+0x12a>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if (cfgidx != 0U)
|
|
8007b16: 4b44 ldr r3, [pc, #272] @ (8007c28 <USBD_SetConfig+0x150>)
|
|
8007b18: 781b ldrb r3, [r3, #0]
|
|
8007b1a: 2b00 cmp r3, #0
|
|
8007b1c: d020 beq.n 8007b60 <USBD_SetConfig+0x88>
|
|
{
|
|
pdev->dev_config = cfgidx;
|
|
8007b1e: 4b42 ldr r3, [pc, #264] @ (8007c28 <USBD_SetConfig+0x150>)
|
|
8007b20: 781b ldrb r3, [r3, #0]
|
|
8007b22: 461a mov r2, r3
|
|
8007b24: 687b ldr r3, [r7, #4]
|
|
8007b26: 605a str r2, [r3, #4]
|
|
|
|
ret = USBD_SetClassConfig(pdev, cfgidx);
|
|
8007b28: 4b3f ldr r3, [pc, #252] @ (8007c28 <USBD_SetConfig+0x150>)
|
|
8007b2a: 781b ldrb r3, [r3, #0]
|
|
8007b2c: 4619 mov r1, r3
|
|
8007b2e: 6878 ldr r0, [r7, #4]
|
|
8007b30: f7fe ffa3 bl 8006a7a <USBD_SetClassConfig>
|
|
8007b34: 4603 mov r3, r0
|
|
8007b36: 73fb strb r3, [r7, #15]
|
|
|
|
if (ret != USBD_OK)
|
|
8007b38: 7bfb ldrb r3, [r7, #15]
|
|
8007b3a: 2b00 cmp r3, #0
|
|
8007b3c: d008 beq.n 8007b50 <USBD_SetConfig+0x78>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8007b3e: 6839 ldr r1, [r7, #0]
|
|
8007b40: 6878 ldr r0, [r7, #4]
|
|
8007b42: f000 f962 bl 8007e0a <USBD_CtlError>
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8007b46: 687b ldr r3, [r7, #4]
|
|
8007b48: 2202 movs r2, #2
|
|
8007b4a: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
8007b4e: e065 b.n 8007c1c <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8007b50: 6878 ldr r0, [r7, #4]
|
|
8007b52: f000 fa17 bl 8007f84 <USBD_CtlSendStatus>
|
|
pdev->dev_state = USBD_STATE_CONFIGURED;
|
|
8007b56: 687b ldr r3, [r7, #4]
|
|
8007b58: 2203 movs r2, #3
|
|
8007b5a: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
break;
|
|
8007b5e: e05d b.n 8007c1c <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8007b60: 6878 ldr r0, [r7, #4]
|
|
8007b62: f000 fa0f bl 8007f84 <USBD_CtlSendStatus>
|
|
break;
|
|
8007b66: e059 b.n 8007c1c <USBD_SetConfig+0x144>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (cfgidx == 0U)
|
|
8007b68: 4b2f ldr r3, [pc, #188] @ (8007c28 <USBD_SetConfig+0x150>)
|
|
8007b6a: 781b ldrb r3, [r3, #0]
|
|
8007b6c: 2b00 cmp r3, #0
|
|
8007b6e: d112 bne.n 8007b96 <USBD_SetConfig+0xbe>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8007b70: 687b ldr r3, [r7, #4]
|
|
8007b72: 2202 movs r2, #2
|
|
8007b74: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->dev_config = cfgidx;
|
|
8007b78: 4b2b ldr r3, [pc, #172] @ (8007c28 <USBD_SetConfig+0x150>)
|
|
8007b7a: 781b ldrb r3, [r3, #0]
|
|
8007b7c: 461a mov r2, r3
|
|
8007b7e: 687b ldr r3, [r7, #4]
|
|
8007b80: 605a str r2, [r3, #4]
|
|
(void)USBD_ClrClassConfig(pdev, cfgidx);
|
|
8007b82: 4b29 ldr r3, [pc, #164] @ (8007c28 <USBD_SetConfig+0x150>)
|
|
8007b84: 781b ldrb r3, [r3, #0]
|
|
8007b86: 4619 mov r1, r3
|
|
8007b88: 6878 ldr r0, [r7, #4]
|
|
8007b8a: f7fe ff92 bl 8006ab2 <USBD_ClrClassConfig>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8007b8e: 6878 ldr r0, [r7, #4]
|
|
8007b90: f000 f9f8 bl 8007f84 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
8007b94: e042 b.n 8007c1c <USBD_SetConfig+0x144>
|
|
else if (cfgidx != pdev->dev_config)
|
|
8007b96: 4b24 ldr r3, [pc, #144] @ (8007c28 <USBD_SetConfig+0x150>)
|
|
8007b98: 781b ldrb r3, [r3, #0]
|
|
8007b9a: 461a mov r2, r3
|
|
8007b9c: 687b ldr r3, [r7, #4]
|
|
8007b9e: 685b ldr r3, [r3, #4]
|
|
8007ba0: 429a cmp r2, r3
|
|
8007ba2: d02a beq.n 8007bfa <USBD_SetConfig+0x122>
|
|
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
8007ba4: 687b ldr r3, [r7, #4]
|
|
8007ba6: 685b ldr r3, [r3, #4]
|
|
8007ba8: b2db uxtb r3, r3
|
|
8007baa: 4619 mov r1, r3
|
|
8007bac: 6878 ldr r0, [r7, #4]
|
|
8007bae: f7fe ff80 bl 8006ab2 <USBD_ClrClassConfig>
|
|
pdev->dev_config = cfgidx;
|
|
8007bb2: 4b1d ldr r3, [pc, #116] @ (8007c28 <USBD_SetConfig+0x150>)
|
|
8007bb4: 781b ldrb r3, [r3, #0]
|
|
8007bb6: 461a mov r2, r3
|
|
8007bb8: 687b ldr r3, [r7, #4]
|
|
8007bba: 605a str r2, [r3, #4]
|
|
ret = USBD_SetClassConfig(pdev, cfgidx);
|
|
8007bbc: 4b1a ldr r3, [pc, #104] @ (8007c28 <USBD_SetConfig+0x150>)
|
|
8007bbe: 781b ldrb r3, [r3, #0]
|
|
8007bc0: 4619 mov r1, r3
|
|
8007bc2: 6878 ldr r0, [r7, #4]
|
|
8007bc4: f7fe ff59 bl 8006a7a <USBD_SetClassConfig>
|
|
8007bc8: 4603 mov r3, r0
|
|
8007bca: 73fb strb r3, [r7, #15]
|
|
if (ret != USBD_OK)
|
|
8007bcc: 7bfb ldrb r3, [r7, #15]
|
|
8007bce: 2b00 cmp r3, #0
|
|
8007bd0: d00f beq.n 8007bf2 <USBD_SetConfig+0x11a>
|
|
USBD_CtlError(pdev, req);
|
|
8007bd2: 6839 ldr r1, [r7, #0]
|
|
8007bd4: 6878 ldr r0, [r7, #4]
|
|
8007bd6: f000 f918 bl 8007e0a <USBD_CtlError>
|
|
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
8007bda: 687b ldr r3, [r7, #4]
|
|
8007bdc: 685b ldr r3, [r3, #4]
|
|
8007bde: b2db uxtb r3, r3
|
|
8007be0: 4619 mov r1, r3
|
|
8007be2: 6878 ldr r0, [r7, #4]
|
|
8007be4: f7fe ff65 bl 8006ab2 <USBD_ClrClassConfig>
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8007be8: 687b ldr r3, [r7, #4]
|
|
8007bea: 2202 movs r2, #2
|
|
8007bec: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
break;
|
|
8007bf0: e014 b.n 8007c1c <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8007bf2: 6878 ldr r0, [r7, #4]
|
|
8007bf4: f000 f9c6 bl 8007f84 <USBD_CtlSendStatus>
|
|
break;
|
|
8007bf8: e010 b.n 8007c1c <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8007bfa: 6878 ldr r0, [r7, #4]
|
|
8007bfc: f000 f9c2 bl 8007f84 <USBD_CtlSendStatus>
|
|
break;
|
|
8007c00: e00c b.n 8007c1c <USBD_SetConfig+0x144>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007c02: 6839 ldr r1, [r7, #0]
|
|
8007c04: 6878 ldr r0, [r7, #4]
|
|
8007c06: f000 f900 bl 8007e0a <USBD_CtlError>
|
|
(void)USBD_ClrClassConfig(pdev, cfgidx);
|
|
8007c0a: 4b07 ldr r3, [pc, #28] @ (8007c28 <USBD_SetConfig+0x150>)
|
|
8007c0c: 781b ldrb r3, [r3, #0]
|
|
8007c0e: 4619 mov r1, r3
|
|
8007c10: 6878 ldr r0, [r7, #4]
|
|
8007c12: f7fe ff4e bl 8006ab2 <USBD_ClrClassConfig>
|
|
ret = USBD_FAIL;
|
|
8007c16: 2303 movs r3, #3
|
|
8007c18: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8007c1a: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8007c1c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007c1e: 4618 mov r0, r3
|
|
8007c20: 3710 adds r7, #16
|
|
8007c22: 46bd mov sp, r7
|
|
8007c24: bd80 pop {r7, pc}
|
|
8007c26: bf00 nop
|
|
8007c28: 20000398 .word 0x20000398
|
|
|
|
08007c2c <USBD_GetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007c2c: b580 push {r7, lr}
|
|
8007c2e: b082 sub sp, #8
|
|
8007c30: af00 add r7, sp, #0
|
|
8007c32: 6078 str r0, [r7, #4]
|
|
8007c34: 6039 str r1, [r7, #0]
|
|
if (req->wLength != 1U)
|
|
8007c36: 683b ldr r3, [r7, #0]
|
|
8007c38: 88db ldrh r3, [r3, #6]
|
|
8007c3a: 2b01 cmp r3, #1
|
|
8007c3c: d004 beq.n 8007c48 <USBD_GetConfig+0x1c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8007c3e: 6839 ldr r1, [r7, #0]
|
|
8007c40: 6878 ldr r0, [r7, #4]
|
|
8007c42: f000 f8e2 bl 8007e0a <USBD_CtlError>
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
8007c46: e023 b.n 8007c90 <USBD_GetConfig+0x64>
|
|
switch (pdev->dev_state)
|
|
8007c48: 687b ldr r3, [r7, #4]
|
|
8007c4a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007c4e: b2db uxtb r3, r3
|
|
8007c50: 2b02 cmp r3, #2
|
|
8007c52: dc02 bgt.n 8007c5a <USBD_GetConfig+0x2e>
|
|
8007c54: 2b00 cmp r3, #0
|
|
8007c56: dc03 bgt.n 8007c60 <USBD_GetConfig+0x34>
|
|
8007c58: e015 b.n 8007c86 <USBD_GetConfig+0x5a>
|
|
8007c5a: 2b03 cmp r3, #3
|
|
8007c5c: d00b beq.n 8007c76 <USBD_GetConfig+0x4a>
|
|
8007c5e: e012 b.n 8007c86 <USBD_GetConfig+0x5a>
|
|
pdev->dev_default_config = 0U;
|
|
8007c60: 687b ldr r3, [r7, #4]
|
|
8007c62: 2200 movs r2, #0
|
|
8007c64: 609a str r2, [r3, #8]
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
|
|
8007c66: 687b ldr r3, [r7, #4]
|
|
8007c68: 3308 adds r3, #8
|
|
8007c6a: 2201 movs r2, #1
|
|
8007c6c: 4619 mov r1, r3
|
|
8007c6e: 6878 ldr r0, [r7, #4]
|
|
8007c70: f000 f948 bl 8007f04 <USBD_CtlSendData>
|
|
break;
|
|
8007c74: e00c b.n 8007c90 <USBD_GetConfig+0x64>
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U);
|
|
8007c76: 687b ldr r3, [r7, #4]
|
|
8007c78: 3304 adds r3, #4
|
|
8007c7a: 2201 movs r2, #1
|
|
8007c7c: 4619 mov r1, r3
|
|
8007c7e: 6878 ldr r0, [r7, #4]
|
|
8007c80: f000 f940 bl 8007f04 <USBD_CtlSendData>
|
|
break;
|
|
8007c84: e004 b.n 8007c90 <USBD_GetConfig+0x64>
|
|
USBD_CtlError(pdev, req);
|
|
8007c86: 6839 ldr r1, [r7, #0]
|
|
8007c88: 6878 ldr r0, [r7, #4]
|
|
8007c8a: f000 f8be bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
8007c8e: bf00 nop
|
|
}
|
|
8007c90: bf00 nop
|
|
8007c92: 3708 adds r7, #8
|
|
8007c94: 46bd mov sp, r7
|
|
8007c96: bd80 pop {r7, pc}
|
|
|
|
08007c98 <USBD_GetStatus>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007c98: b580 push {r7, lr}
|
|
8007c9a: b082 sub sp, #8
|
|
8007c9c: af00 add r7, sp, #0
|
|
8007c9e: 6078 str r0, [r7, #4]
|
|
8007ca0: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
8007ca2: 687b ldr r3, [r7, #4]
|
|
8007ca4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007ca8: b2db uxtb r3, r3
|
|
8007caa: 3b01 subs r3, #1
|
|
8007cac: 2b02 cmp r3, #2
|
|
8007cae: d81e bhi.n 8007cee <USBD_GetStatus+0x56>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wLength != 0x2U)
|
|
8007cb0: 683b ldr r3, [r7, #0]
|
|
8007cb2: 88db ldrh r3, [r3, #6]
|
|
8007cb4: 2b02 cmp r3, #2
|
|
8007cb6: d004 beq.n 8007cc2 <USBD_GetStatus+0x2a>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8007cb8: 6839 ldr r1, [r7, #0]
|
|
8007cba: 6878 ldr r0, [r7, #4]
|
|
8007cbc: f000 f8a5 bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
8007cc0: e01a b.n 8007cf8 <USBD_GetStatus+0x60>
|
|
}
|
|
|
|
#if (USBD_SELF_POWERED == 1U)
|
|
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
|
|
8007cc2: 687b ldr r3, [r7, #4]
|
|
8007cc4: 2201 movs r2, #1
|
|
8007cc6: 60da str r2, [r3, #12]
|
|
#else
|
|
pdev->dev_config_status = 0U;
|
|
#endif /* USBD_SELF_POWERED */
|
|
|
|
if (pdev->dev_remote_wakeup != 0U)
|
|
8007cc8: 687b ldr r3, [r7, #4]
|
|
8007cca: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
|
|
8007cce: 2b00 cmp r3, #0
|
|
8007cd0: d005 beq.n 8007cde <USBD_GetStatus+0x46>
|
|
{
|
|
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
|
|
8007cd2: 687b ldr r3, [r7, #4]
|
|
8007cd4: 68db ldr r3, [r3, #12]
|
|
8007cd6: f043 0202 orr.w r2, r3, #2
|
|
8007cda: 687b ldr r3, [r7, #4]
|
|
8007cdc: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U);
|
|
8007cde: 687b ldr r3, [r7, #4]
|
|
8007ce0: 330c adds r3, #12
|
|
8007ce2: 2202 movs r2, #2
|
|
8007ce4: 4619 mov r1, r3
|
|
8007ce6: 6878 ldr r0, [r7, #4]
|
|
8007ce8: f000 f90c bl 8007f04 <USBD_CtlSendData>
|
|
break;
|
|
8007cec: e004 b.n 8007cf8 <USBD_GetStatus+0x60>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007cee: 6839 ldr r1, [r7, #0]
|
|
8007cf0: 6878 ldr r0, [r7, #4]
|
|
8007cf2: f000 f88a bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
8007cf6: bf00 nop
|
|
}
|
|
}
|
|
8007cf8: bf00 nop
|
|
8007cfa: 3708 adds r7, #8
|
|
8007cfc: 46bd mov sp, r7
|
|
8007cfe: bd80 pop {r7, pc}
|
|
|
|
08007d00 <USBD_SetFeature>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007d00: b580 push {r7, lr}
|
|
8007d02: b082 sub sp, #8
|
|
8007d04: af00 add r7, sp, #0
|
|
8007d06: 6078 str r0, [r7, #4]
|
|
8007d08: 6039 str r1, [r7, #0]
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
8007d0a: 683b ldr r3, [r7, #0]
|
|
8007d0c: 885b ldrh r3, [r3, #2]
|
|
8007d0e: 2b01 cmp r3, #1
|
|
8007d10: d107 bne.n 8007d22 <USBD_SetFeature+0x22>
|
|
{
|
|
pdev->dev_remote_wakeup = 1U;
|
|
8007d12: 687b ldr r3, [r7, #4]
|
|
8007d14: 2201 movs r2, #1
|
|
8007d16: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8007d1a: 6878 ldr r0, [r7, #4]
|
|
8007d1c: f000 f932 bl 8007f84 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
}
|
|
8007d20: e013 b.n 8007d4a <USBD_SetFeature+0x4a>
|
|
else if (req->wValue == USB_FEATURE_TEST_MODE)
|
|
8007d22: 683b ldr r3, [r7, #0]
|
|
8007d24: 885b ldrh r3, [r3, #2]
|
|
8007d26: 2b02 cmp r3, #2
|
|
8007d28: d10b bne.n 8007d42 <USBD_SetFeature+0x42>
|
|
pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8);
|
|
8007d2a: 683b ldr r3, [r7, #0]
|
|
8007d2c: 889b ldrh r3, [r3, #4]
|
|
8007d2e: 0a1b lsrs r3, r3, #8
|
|
8007d30: b29b uxth r3, r3
|
|
8007d32: b2da uxtb r2, r3
|
|
8007d34: 687b ldr r3, [r7, #4]
|
|
8007d36: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8007d3a: 6878 ldr r0, [r7, #4]
|
|
8007d3c: f000 f922 bl 8007f84 <USBD_CtlSendStatus>
|
|
}
|
|
8007d40: e003 b.n 8007d4a <USBD_SetFeature+0x4a>
|
|
USBD_CtlError(pdev, req);
|
|
8007d42: 6839 ldr r1, [r7, #0]
|
|
8007d44: 6878 ldr r0, [r7, #4]
|
|
8007d46: f000 f860 bl 8007e0a <USBD_CtlError>
|
|
}
|
|
8007d4a: bf00 nop
|
|
8007d4c: 3708 adds r7, #8
|
|
8007d4e: 46bd mov sp, r7
|
|
8007d50: bd80 pop {r7, pc}
|
|
|
|
08007d52 <USBD_ClrFeature>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007d52: b580 push {r7, lr}
|
|
8007d54: b082 sub sp, #8
|
|
8007d56: af00 add r7, sp, #0
|
|
8007d58: 6078 str r0, [r7, #4]
|
|
8007d5a: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
8007d5c: 687b ldr r3, [r7, #4]
|
|
8007d5e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8007d62: b2db uxtb r3, r3
|
|
8007d64: 3b01 subs r3, #1
|
|
8007d66: 2b02 cmp r3, #2
|
|
8007d68: d80b bhi.n 8007d82 <USBD_ClrFeature+0x30>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
8007d6a: 683b ldr r3, [r7, #0]
|
|
8007d6c: 885b ldrh r3, [r3, #2]
|
|
8007d6e: 2b01 cmp r3, #1
|
|
8007d70: d10c bne.n 8007d8c <USBD_ClrFeature+0x3a>
|
|
{
|
|
pdev->dev_remote_wakeup = 0U;
|
|
8007d72: 687b ldr r3, [r7, #4]
|
|
8007d74: 2200 movs r2, #0
|
|
8007d76: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8007d7a: 6878 ldr r0, [r7, #4]
|
|
8007d7c: f000 f902 bl 8007f84 <USBD_CtlSendStatus>
|
|
}
|
|
break;
|
|
8007d80: e004 b.n 8007d8c <USBD_ClrFeature+0x3a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8007d82: 6839 ldr r1, [r7, #0]
|
|
8007d84: 6878 ldr r0, [r7, #4]
|
|
8007d86: f000 f840 bl 8007e0a <USBD_CtlError>
|
|
break;
|
|
8007d8a: e000 b.n 8007d8e <USBD_ClrFeature+0x3c>
|
|
break;
|
|
8007d8c: bf00 nop
|
|
}
|
|
}
|
|
8007d8e: bf00 nop
|
|
8007d90: 3708 adds r7, #8
|
|
8007d92: 46bd mov sp, r7
|
|
8007d94: bd80 pop {r7, pc}
|
|
|
|
08007d96 <USBD_ParseSetupRequest>:
|
|
* @param req: usb request
|
|
* @param pdata: setup data pointer
|
|
* @retval None
|
|
*/
|
|
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
|
|
{
|
|
8007d96: b580 push {r7, lr}
|
|
8007d98: b084 sub sp, #16
|
|
8007d9a: af00 add r7, sp, #0
|
|
8007d9c: 6078 str r0, [r7, #4]
|
|
8007d9e: 6039 str r1, [r7, #0]
|
|
uint8_t *pbuff = pdata;
|
|
8007da0: 683b ldr r3, [r7, #0]
|
|
8007da2: 60fb str r3, [r7, #12]
|
|
|
|
req->bmRequest = *(uint8_t *)(pbuff);
|
|
8007da4: 68fb ldr r3, [r7, #12]
|
|
8007da6: 781a ldrb r2, [r3, #0]
|
|
8007da8: 687b ldr r3, [r7, #4]
|
|
8007daa: 701a strb r2, [r3, #0]
|
|
|
|
pbuff++;
|
|
8007dac: 68fb ldr r3, [r7, #12]
|
|
8007dae: 3301 adds r3, #1
|
|
8007db0: 60fb str r3, [r7, #12]
|
|
req->bRequest = *(uint8_t *)(pbuff);
|
|
8007db2: 68fb ldr r3, [r7, #12]
|
|
8007db4: 781a ldrb r2, [r3, #0]
|
|
8007db6: 687b ldr r3, [r7, #4]
|
|
8007db8: 705a strb r2, [r3, #1]
|
|
|
|
pbuff++;
|
|
8007dba: 68fb ldr r3, [r7, #12]
|
|
8007dbc: 3301 adds r3, #1
|
|
8007dbe: 60fb str r3, [r7, #12]
|
|
req->wValue = SWAPBYTE(pbuff);
|
|
8007dc0: 68f8 ldr r0, [r7, #12]
|
|
8007dc2: f7ff fa13 bl 80071ec <SWAPBYTE>
|
|
8007dc6: 4603 mov r3, r0
|
|
8007dc8: 461a mov r2, r3
|
|
8007dca: 687b ldr r3, [r7, #4]
|
|
8007dcc: 805a strh r2, [r3, #2]
|
|
|
|
pbuff++;
|
|
8007dce: 68fb ldr r3, [r7, #12]
|
|
8007dd0: 3301 adds r3, #1
|
|
8007dd2: 60fb str r3, [r7, #12]
|
|
pbuff++;
|
|
8007dd4: 68fb ldr r3, [r7, #12]
|
|
8007dd6: 3301 adds r3, #1
|
|
8007dd8: 60fb str r3, [r7, #12]
|
|
req->wIndex = SWAPBYTE(pbuff);
|
|
8007dda: 68f8 ldr r0, [r7, #12]
|
|
8007ddc: f7ff fa06 bl 80071ec <SWAPBYTE>
|
|
8007de0: 4603 mov r3, r0
|
|
8007de2: 461a mov r2, r3
|
|
8007de4: 687b ldr r3, [r7, #4]
|
|
8007de6: 809a strh r2, [r3, #4]
|
|
|
|
pbuff++;
|
|
8007de8: 68fb ldr r3, [r7, #12]
|
|
8007dea: 3301 adds r3, #1
|
|
8007dec: 60fb str r3, [r7, #12]
|
|
pbuff++;
|
|
8007dee: 68fb ldr r3, [r7, #12]
|
|
8007df0: 3301 adds r3, #1
|
|
8007df2: 60fb str r3, [r7, #12]
|
|
req->wLength = SWAPBYTE(pbuff);
|
|
8007df4: 68f8 ldr r0, [r7, #12]
|
|
8007df6: f7ff f9f9 bl 80071ec <SWAPBYTE>
|
|
8007dfa: 4603 mov r3, r0
|
|
8007dfc: 461a mov r2, r3
|
|
8007dfe: 687b ldr r3, [r7, #4]
|
|
8007e00: 80da strh r2, [r3, #6]
|
|
}
|
|
8007e02: bf00 nop
|
|
8007e04: 3710 adds r7, #16
|
|
8007e06: 46bd mov sp, r7
|
|
8007e08: bd80 pop {r7, pc}
|
|
|
|
08007e0a <USBD_CtlError>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8007e0a: b580 push {r7, lr}
|
|
8007e0c: b082 sub sp, #8
|
|
8007e0e: af00 add r7, sp, #0
|
|
8007e10: 6078 str r0, [r7, #4]
|
|
8007e12: 6039 str r1, [r7, #0]
|
|
UNUSED(req);
|
|
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8007e14: 2180 movs r1, #128 @ 0x80
|
|
8007e16: 6878 ldr r0, [r7, #4]
|
|
8007e18: f000 fc2a bl 8008670 <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0U);
|
|
8007e1c: 2100 movs r1, #0
|
|
8007e1e: 6878 ldr r0, [r7, #4]
|
|
8007e20: f000 fc26 bl 8008670 <USBD_LL_StallEP>
|
|
}
|
|
8007e24: bf00 nop
|
|
8007e26: 3708 adds r7, #8
|
|
8007e28: 46bd mov sp, r7
|
|
8007e2a: bd80 pop {r7, pc}
|
|
|
|
08007e2c <USBD_GetString>:
|
|
* @param unicode : Formatted string buffer (unicode)
|
|
* @param len : descriptor length
|
|
* @retval None
|
|
*/
|
|
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
|
|
{
|
|
8007e2c: b580 push {r7, lr}
|
|
8007e2e: b086 sub sp, #24
|
|
8007e30: af00 add r7, sp, #0
|
|
8007e32: 60f8 str r0, [r7, #12]
|
|
8007e34: 60b9 str r1, [r7, #8]
|
|
8007e36: 607a str r2, [r7, #4]
|
|
uint8_t idx = 0U;
|
|
8007e38: 2300 movs r3, #0
|
|
8007e3a: 75fb strb r3, [r7, #23]
|
|
uint8_t *pdesc;
|
|
|
|
if (desc == NULL)
|
|
8007e3c: 68fb ldr r3, [r7, #12]
|
|
8007e3e: 2b00 cmp r3, #0
|
|
8007e40: d042 beq.n 8007ec8 <USBD_GetString+0x9c>
|
|
{
|
|
return;
|
|
}
|
|
|
|
pdesc = desc;
|
|
8007e42: 68fb ldr r3, [r7, #12]
|
|
8007e44: 613b str r3, [r7, #16]
|
|
*len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U);
|
|
8007e46: 6938 ldr r0, [r7, #16]
|
|
8007e48: f000 f842 bl 8007ed0 <USBD_GetLen>
|
|
8007e4c: 4603 mov r3, r0
|
|
8007e4e: 3301 adds r3, #1
|
|
8007e50: 005b lsls r3, r3, #1
|
|
8007e52: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8007e56: d808 bhi.n 8007e6a <USBD_GetString+0x3e>
|
|
8007e58: 6938 ldr r0, [r7, #16]
|
|
8007e5a: f000 f839 bl 8007ed0 <USBD_GetLen>
|
|
8007e5e: 4603 mov r3, r0
|
|
8007e60: 3301 adds r3, #1
|
|
8007e62: b29b uxth r3, r3
|
|
8007e64: 005b lsls r3, r3, #1
|
|
8007e66: b29a uxth r2, r3
|
|
8007e68: e001 b.n 8007e6e <USBD_GetString+0x42>
|
|
8007e6a: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8007e6e: 687b ldr r3, [r7, #4]
|
|
8007e70: 801a strh r2, [r3, #0]
|
|
|
|
unicode[idx] = *(uint8_t *)len;
|
|
8007e72: 7dfb ldrb r3, [r7, #23]
|
|
8007e74: 68ba ldr r2, [r7, #8]
|
|
8007e76: 4413 add r3, r2
|
|
8007e78: 687a ldr r2, [r7, #4]
|
|
8007e7a: 7812 ldrb r2, [r2, #0]
|
|
8007e7c: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8007e7e: 7dfb ldrb r3, [r7, #23]
|
|
8007e80: 3301 adds r3, #1
|
|
8007e82: 75fb strb r3, [r7, #23]
|
|
unicode[idx] = USB_DESC_TYPE_STRING;
|
|
8007e84: 7dfb ldrb r3, [r7, #23]
|
|
8007e86: 68ba ldr r2, [r7, #8]
|
|
8007e88: 4413 add r3, r2
|
|
8007e8a: 2203 movs r2, #3
|
|
8007e8c: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8007e8e: 7dfb ldrb r3, [r7, #23]
|
|
8007e90: 3301 adds r3, #1
|
|
8007e92: 75fb strb r3, [r7, #23]
|
|
|
|
while (*pdesc != (uint8_t)'\0')
|
|
8007e94: e013 b.n 8007ebe <USBD_GetString+0x92>
|
|
{
|
|
unicode[idx] = *pdesc;
|
|
8007e96: 7dfb ldrb r3, [r7, #23]
|
|
8007e98: 68ba ldr r2, [r7, #8]
|
|
8007e9a: 4413 add r3, r2
|
|
8007e9c: 693a ldr r2, [r7, #16]
|
|
8007e9e: 7812 ldrb r2, [r2, #0]
|
|
8007ea0: 701a strb r2, [r3, #0]
|
|
pdesc++;
|
|
8007ea2: 693b ldr r3, [r7, #16]
|
|
8007ea4: 3301 adds r3, #1
|
|
8007ea6: 613b str r3, [r7, #16]
|
|
idx++;
|
|
8007ea8: 7dfb ldrb r3, [r7, #23]
|
|
8007eaa: 3301 adds r3, #1
|
|
8007eac: 75fb strb r3, [r7, #23]
|
|
|
|
unicode[idx] = 0U;
|
|
8007eae: 7dfb ldrb r3, [r7, #23]
|
|
8007eb0: 68ba ldr r2, [r7, #8]
|
|
8007eb2: 4413 add r3, r2
|
|
8007eb4: 2200 movs r2, #0
|
|
8007eb6: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8007eb8: 7dfb ldrb r3, [r7, #23]
|
|
8007eba: 3301 adds r3, #1
|
|
8007ebc: 75fb strb r3, [r7, #23]
|
|
while (*pdesc != (uint8_t)'\0')
|
|
8007ebe: 693b ldr r3, [r7, #16]
|
|
8007ec0: 781b ldrb r3, [r3, #0]
|
|
8007ec2: 2b00 cmp r3, #0
|
|
8007ec4: d1e7 bne.n 8007e96 <USBD_GetString+0x6a>
|
|
8007ec6: e000 b.n 8007eca <USBD_GetString+0x9e>
|
|
return;
|
|
8007ec8: bf00 nop
|
|
}
|
|
}
|
|
8007eca: 3718 adds r7, #24
|
|
8007ecc: 46bd mov sp, r7
|
|
8007ece: bd80 pop {r7, pc}
|
|
|
|
08007ed0 <USBD_GetLen>:
|
|
* return the string length
|
|
* @param buf : pointer to the ascii string buffer
|
|
* @retval string length
|
|
*/
|
|
static uint8_t USBD_GetLen(uint8_t *buf)
|
|
{
|
|
8007ed0: b480 push {r7}
|
|
8007ed2: b085 sub sp, #20
|
|
8007ed4: af00 add r7, sp, #0
|
|
8007ed6: 6078 str r0, [r7, #4]
|
|
uint8_t len = 0U;
|
|
8007ed8: 2300 movs r3, #0
|
|
8007eda: 73fb strb r3, [r7, #15]
|
|
uint8_t *pbuff = buf;
|
|
8007edc: 687b ldr r3, [r7, #4]
|
|
8007ede: 60bb str r3, [r7, #8]
|
|
|
|
while (*pbuff != (uint8_t)'\0')
|
|
8007ee0: e005 b.n 8007eee <USBD_GetLen+0x1e>
|
|
{
|
|
len++;
|
|
8007ee2: 7bfb ldrb r3, [r7, #15]
|
|
8007ee4: 3301 adds r3, #1
|
|
8007ee6: 73fb strb r3, [r7, #15]
|
|
pbuff++;
|
|
8007ee8: 68bb ldr r3, [r7, #8]
|
|
8007eea: 3301 adds r3, #1
|
|
8007eec: 60bb str r3, [r7, #8]
|
|
while (*pbuff != (uint8_t)'\0')
|
|
8007eee: 68bb ldr r3, [r7, #8]
|
|
8007ef0: 781b ldrb r3, [r3, #0]
|
|
8007ef2: 2b00 cmp r3, #0
|
|
8007ef4: d1f5 bne.n 8007ee2 <USBD_GetLen+0x12>
|
|
}
|
|
|
|
return len;
|
|
8007ef6: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007ef8: 4618 mov r0, r3
|
|
8007efa: 3714 adds r7, #20
|
|
8007efc: 46bd mov sp, r7
|
|
8007efe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007f02: 4770 bx lr
|
|
|
|
08007f04 <USBD_CtlSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8007f04: b580 push {r7, lr}
|
|
8007f06: b084 sub sp, #16
|
|
8007f08: af00 add r7, sp, #0
|
|
8007f0a: 60f8 str r0, [r7, #12]
|
|
8007f0c: 60b9 str r1, [r7, #8]
|
|
8007f0e: 607a str r2, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_DATA_IN;
|
|
8007f10: 68fb ldr r3, [r7, #12]
|
|
8007f12: 2202 movs r2, #2
|
|
8007f14: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->ep_in[0].total_length = len;
|
|
8007f18: 68fb ldr r3, [r7, #12]
|
|
8007f1a: 687a ldr r2, [r7, #4]
|
|
8007f1c: 615a str r2, [r3, #20]
|
|
pdev->ep_in[0].pbuffer = pbuf;
|
|
8007f1e: 68fb ldr r3, [r7, #12]
|
|
8007f20: 68ba ldr r2, [r7, #8]
|
|
8007f22: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
|
|
pdev->ep_in[0].rem_length = 0U;
|
|
#else
|
|
pdev->ep_in[0].rem_length = len;
|
|
8007f24: 68fb ldr r3, [r7, #12]
|
|
8007f26: 687a ldr r2, [r7, #4]
|
|
8007f28: 619a str r2, [r3, #24]
|
|
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
8007f2a: 687b ldr r3, [r7, #4]
|
|
8007f2c: 68ba ldr r2, [r7, #8]
|
|
8007f2e: 2100 movs r1, #0
|
|
8007f30: 68f8 ldr r0, [r7, #12]
|
|
8007f32: f000 fc26 bl 8008782 <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8007f36: 2300 movs r3, #0
|
|
}
|
|
8007f38: 4618 mov r0, r3
|
|
8007f3a: 3710 adds r7, #16
|
|
8007f3c: 46bd mov sp, r7
|
|
8007f3e: bd80 pop {r7, pc}
|
|
|
|
08007f40 <USBD_CtlContinueSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8007f40: b580 push {r7, lr}
|
|
8007f42: b084 sub sp, #16
|
|
8007f44: af00 add r7, sp, #0
|
|
8007f46: 60f8 str r0, [r7, #12]
|
|
8007f48: 60b9 str r1, [r7, #8]
|
|
8007f4a: 607a str r2, [r7, #4]
|
|
/* Start the next transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
8007f4c: 687b ldr r3, [r7, #4]
|
|
8007f4e: 68ba ldr r2, [r7, #8]
|
|
8007f50: 2100 movs r1, #0
|
|
8007f52: 68f8 ldr r0, [r7, #12]
|
|
8007f54: f000 fc15 bl 8008782 <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8007f58: 2300 movs r3, #0
|
|
}
|
|
8007f5a: 4618 mov r0, r3
|
|
8007f5c: 3710 adds r7, #16
|
|
8007f5e: 46bd mov sp, r7
|
|
8007f60: bd80 pop {r7, pc}
|
|
|
|
08007f62 <USBD_CtlContinueRx>:
|
|
* @param len: length of data to be received
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8007f62: b580 push {r7, lr}
|
|
8007f64: b084 sub sp, #16
|
|
8007f66: af00 add r7, sp, #0
|
|
8007f68: 60f8 str r0, [r7, #12]
|
|
8007f6a: 60b9 str r1, [r7, #8]
|
|
8007f6c: 607a str r2, [r7, #4]
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
|
|
8007f6e: 687b ldr r3, [r7, #4]
|
|
8007f70: 68ba ldr r2, [r7, #8]
|
|
8007f72: 2100 movs r1, #0
|
|
8007f74: 68f8 ldr r0, [r7, #12]
|
|
8007f76: f000 fc25 bl 80087c4 <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8007f7a: 2300 movs r3, #0
|
|
}
|
|
8007f7c: 4618 mov r0, r3
|
|
8007f7e: 3710 adds r7, #16
|
|
8007f80: 46bd mov sp, r7
|
|
8007f82: bd80 pop {r7, pc}
|
|
|
|
08007f84 <USBD_CtlSendStatus>:
|
|
* send zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007f84: b580 push {r7, lr}
|
|
8007f86: b082 sub sp, #8
|
|
8007f88: af00 add r7, sp, #0
|
|
8007f8a: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_IN;
|
|
8007f8c: 687b ldr r3, [r7, #4]
|
|
8007f8e: 2204 movs r2, #4
|
|
8007f90: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
|
|
8007f94: 2300 movs r3, #0
|
|
8007f96: 2200 movs r2, #0
|
|
8007f98: 2100 movs r1, #0
|
|
8007f9a: 6878 ldr r0, [r7, #4]
|
|
8007f9c: f000 fbf1 bl 8008782 <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8007fa0: 2300 movs r3, #0
|
|
}
|
|
8007fa2: 4618 mov r0, r3
|
|
8007fa4: 3708 adds r7, #8
|
|
8007fa6: 46bd mov sp, r7
|
|
8007fa8: bd80 pop {r7, pc}
|
|
|
|
08007faa <USBD_CtlReceiveStatus>:
|
|
* receive zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8007faa: b580 push {r7, lr}
|
|
8007fac: b082 sub sp, #8
|
|
8007fae: af00 add r7, sp, #0
|
|
8007fb0: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_OUT;
|
|
8007fb2: 687b ldr r3, [r7, #4]
|
|
8007fb4: 2205 movs r2, #5
|
|
8007fb6: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8007fba: 2300 movs r3, #0
|
|
8007fbc: 2200 movs r2, #0
|
|
8007fbe: 2100 movs r1, #0
|
|
8007fc0: 6878 ldr r0, [r7, #4]
|
|
8007fc2: f000 fbff bl 80087c4 <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8007fc6: 2300 movs r3, #0
|
|
}
|
|
8007fc8: 4618 mov r0, r3
|
|
8007fca: 3708 adds r7, #8
|
|
8007fcc: 46bd mov sp, r7
|
|
8007fce: bd80 pop {r7, pc}
|
|
|
|
08007fd0 <MX_USB_DEVICE_Init>:
|
|
/**
|
|
* Init USB device Library, add supported class and start the library
|
|
* @retval None
|
|
*/
|
|
void MX_USB_DEVICE_Init(void)
|
|
{
|
|
8007fd0: b580 push {r7, lr}
|
|
8007fd2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
|
|
|
|
/* USER CODE END USB_DEVICE_Init_PreTreatment */
|
|
|
|
/* Init Device Library, add supported class and start the library. */
|
|
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
|
|
8007fd4: 2200 movs r2, #0
|
|
8007fd6: 490e ldr r1, [pc, #56] @ (8008010 <MX_USB_DEVICE_Init+0x40>)
|
|
8007fd8: 480e ldr r0, [pc, #56] @ (8008014 <MX_USB_DEVICE_Init+0x44>)
|
|
8007fda: f7fe fcd1 bl 8006980 <USBD_Init>
|
|
8007fde: 4603 mov r3, r0
|
|
8007fe0: 2b00 cmp r3, #0
|
|
8007fe2: d001 beq.n 8007fe8 <MX_USB_DEVICE_Init+0x18>
|
|
{
|
|
Error_Handler();
|
|
8007fe4: f7f8 fd78 bl 8000ad8 <Error_Handler>
|
|
}
|
|
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK)
|
|
8007fe8: 490b ldr r1, [pc, #44] @ (8008018 <MX_USB_DEVICE_Init+0x48>)
|
|
8007fea: 480a ldr r0, [pc, #40] @ (8008014 <MX_USB_DEVICE_Init+0x44>)
|
|
8007fec: f7fe fcf8 bl 80069e0 <USBD_RegisterClass>
|
|
8007ff0: 4603 mov r3, r0
|
|
8007ff2: 2b00 cmp r3, #0
|
|
8007ff4: d001 beq.n 8007ffa <MX_USB_DEVICE_Init+0x2a>
|
|
{
|
|
Error_Handler();
|
|
8007ff6: f7f8 fd6f bl 8000ad8 <Error_Handler>
|
|
}
|
|
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
|
|
8007ffa: 4806 ldr r0, [pc, #24] @ (8008014 <MX_USB_DEVICE_Init+0x44>)
|
|
8007ffc: f7fe fd26 bl 8006a4c <USBD_Start>
|
|
8008000: 4603 mov r3, r0
|
|
8008002: 2b00 cmp r3, #0
|
|
8008004: d001 beq.n 800800a <MX_USB_DEVICE_Init+0x3a>
|
|
{
|
|
Error_Handler();
|
|
8008006: f7f8 fd67 bl 8000ad8 <Error_Handler>
|
|
}
|
|
|
|
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
|
|
|
|
/* USER CODE END USB_DEVICE_Init_PostTreatment */
|
|
}
|
|
800800a: bf00 nop
|
|
800800c: bd80 pop {r7, pc}
|
|
800800e: bf00 nop
|
|
8008010: 200000cc .word 0x200000cc
|
|
8008014: 2000039c .word 0x2000039c
|
|
8008018: 2000000c .word 0x2000000c
|
|
|
|
0800801c <USBD_FS_DeviceDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800801c: b480 push {r7}
|
|
800801e: b083 sub sp, #12
|
|
8008020: af00 add r7, sp, #0
|
|
8008022: 4603 mov r3, r0
|
|
8008024: 6039 str r1, [r7, #0]
|
|
8008026: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_FS_DeviceDesc);
|
|
8008028: 683b ldr r3, [r7, #0]
|
|
800802a: 2212 movs r2, #18
|
|
800802c: 801a strh r2, [r3, #0]
|
|
return USBD_FS_DeviceDesc;
|
|
800802e: 4b03 ldr r3, [pc, #12] @ (800803c <USBD_FS_DeviceDescriptor+0x20>)
|
|
}
|
|
8008030: 4618 mov r0, r3
|
|
8008032: 370c adds r7, #12
|
|
8008034: 46bd mov sp, r7
|
|
8008036: f85d 7b04 ldr.w r7, [sp], #4
|
|
800803a: 4770 bx lr
|
|
800803c: 200000ec .word 0x200000ec
|
|
|
|
08008040 <USBD_FS_LangIDStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008040: b480 push {r7}
|
|
8008042: b083 sub sp, #12
|
|
8008044: af00 add r7, sp, #0
|
|
8008046: 4603 mov r3, r0
|
|
8008048: 6039 str r1, [r7, #0]
|
|
800804a: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_LangIDDesc);
|
|
800804c: 683b ldr r3, [r7, #0]
|
|
800804e: 2204 movs r2, #4
|
|
8008050: 801a strh r2, [r3, #0]
|
|
return USBD_LangIDDesc;
|
|
8008052: 4b03 ldr r3, [pc, #12] @ (8008060 <USBD_FS_LangIDStrDescriptor+0x20>)
|
|
}
|
|
8008054: 4618 mov r0, r3
|
|
8008056: 370c adds r7, #12
|
|
8008058: 46bd mov sp, r7
|
|
800805a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800805e: 4770 bx lr
|
|
8008060: 2000010c .word 0x2000010c
|
|
|
|
08008064 <USBD_FS_ProductStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008064: b580 push {r7, lr}
|
|
8008066: b082 sub sp, #8
|
|
8008068: af00 add r7, sp, #0
|
|
800806a: 4603 mov r3, r0
|
|
800806c: 6039 str r1, [r7, #0]
|
|
800806e: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
8008070: 79fb ldrb r3, [r7, #7]
|
|
8008072: 2b00 cmp r3, #0
|
|
8008074: d105 bne.n 8008082 <USBD_FS_ProductStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
|
|
8008076: 683a ldr r2, [r7, #0]
|
|
8008078: 4907 ldr r1, [pc, #28] @ (8008098 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
800807a: 4808 ldr r0, [pc, #32] @ (800809c <USBD_FS_ProductStrDescriptor+0x38>)
|
|
800807c: f7ff fed6 bl 8007e2c <USBD_GetString>
|
|
8008080: e004 b.n 800808c <USBD_FS_ProductStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
|
|
8008082: 683a ldr r2, [r7, #0]
|
|
8008084: 4904 ldr r1, [pc, #16] @ (8008098 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
8008086: 4805 ldr r0, [pc, #20] @ (800809c <USBD_FS_ProductStrDescriptor+0x38>)
|
|
8008088: f7ff fed0 bl 8007e2c <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
800808c: 4b02 ldr r3, [pc, #8] @ (8008098 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
}
|
|
800808e: 4618 mov r0, r3
|
|
8008090: 3708 adds r7, #8
|
|
8008092: 46bd mov sp, r7
|
|
8008094: bd80 pop {r7, pc}
|
|
8008096: bf00 nop
|
|
8008098: 20000678 .word 0x20000678
|
|
800809c: 0800899c .word 0x0800899c
|
|
|
|
080080a0 <USBD_FS_ManufacturerStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
80080a0: b580 push {r7, lr}
|
|
80080a2: b082 sub sp, #8
|
|
80080a4: af00 add r7, sp, #0
|
|
80080a6: 4603 mov r3, r0
|
|
80080a8: 6039 str r1, [r7, #0]
|
|
80080aa: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
|
|
80080ac: 683a ldr r2, [r7, #0]
|
|
80080ae: 4904 ldr r1, [pc, #16] @ (80080c0 <USBD_FS_ManufacturerStrDescriptor+0x20>)
|
|
80080b0: 4804 ldr r0, [pc, #16] @ (80080c4 <USBD_FS_ManufacturerStrDescriptor+0x24>)
|
|
80080b2: f7ff febb bl 8007e2c <USBD_GetString>
|
|
return USBD_StrDesc;
|
|
80080b6: 4b02 ldr r3, [pc, #8] @ (80080c0 <USBD_FS_ManufacturerStrDescriptor+0x20>)
|
|
}
|
|
80080b8: 4618 mov r0, r3
|
|
80080ba: 3708 adds r7, #8
|
|
80080bc: 46bd mov sp, r7
|
|
80080be: bd80 pop {r7, pc}
|
|
80080c0: 20000678 .word 0x20000678
|
|
80080c4: 080089b0 .word 0x080089b0
|
|
|
|
080080c8 <USBD_FS_SerialStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
80080c8: b580 push {r7, lr}
|
|
80080ca: b082 sub sp, #8
|
|
80080cc: af00 add r7, sp, #0
|
|
80080ce: 4603 mov r3, r0
|
|
80080d0: 6039 str r1, [r7, #0]
|
|
80080d2: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = USB_SIZ_STRING_SERIAL;
|
|
80080d4: 683b ldr r3, [r7, #0]
|
|
80080d6: 221a movs r2, #26
|
|
80080d8: 801a strh r2, [r3, #0]
|
|
|
|
/* Update the serial number string descriptor with the data from the unique
|
|
* ID */
|
|
Get_SerialNum();
|
|
80080da: f000 f855 bl 8008188 <Get_SerialNum>
|
|
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
|
|
|
|
/* USER CODE END USBD_FS_SerialStrDescriptor */
|
|
return (uint8_t *) USBD_StringSerial;
|
|
80080de: 4b02 ldr r3, [pc, #8] @ (80080e8 <USBD_FS_SerialStrDescriptor+0x20>)
|
|
}
|
|
80080e0: 4618 mov r0, r3
|
|
80080e2: 3708 adds r7, #8
|
|
80080e4: 46bd mov sp, r7
|
|
80080e6: bd80 pop {r7, pc}
|
|
80080e8: 20000110 .word 0x20000110
|
|
|
|
080080ec <USBD_FS_ConfigStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
80080ec: b580 push {r7, lr}
|
|
80080ee: b082 sub sp, #8
|
|
80080f0: af00 add r7, sp, #0
|
|
80080f2: 4603 mov r3, r0
|
|
80080f4: 6039 str r1, [r7, #0]
|
|
80080f6: 71fb strb r3, [r7, #7]
|
|
if(speed == USBD_SPEED_HIGH)
|
|
80080f8: 79fb ldrb r3, [r7, #7]
|
|
80080fa: 2b00 cmp r3, #0
|
|
80080fc: d105 bne.n 800810a <USBD_FS_ConfigStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
|
|
80080fe: 683a ldr r2, [r7, #0]
|
|
8008100: 4907 ldr r1, [pc, #28] @ (8008120 <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
8008102: 4808 ldr r0, [pc, #32] @ (8008124 <USBD_FS_ConfigStrDescriptor+0x38>)
|
|
8008104: f7ff fe92 bl 8007e2c <USBD_GetString>
|
|
8008108: e004 b.n 8008114 <USBD_FS_ConfigStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
|
|
800810a: 683a ldr r2, [r7, #0]
|
|
800810c: 4904 ldr r1, [pc, #16] @ (8008120 <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
800810e: 4805 ldr r0, [pc, #20] @ (8008124 <USBD_FS_ConfigStrDescriptor+0x38>)
|
|
8008110: f7ff fe8c bl 8007e2c <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8008114: 4b02 ldr r3, [pc, #8] @ (8008120 <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
}
|
|
8008116: 4618 mov r0, r3
|
|
8008118: 3708 adds r7, #8
|
|
800811a: 46bd mov sp, r7
|
|
800811c: bd80 pop {r7, pc}
|
|
800811e: bf00 nop
|
|
8008120: 20000678 .word 0x20000678
|
|
8008124: 080089bc .word 0x080089bc
|
|
|
|
08008128 <USBD_FS_InterfaceStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008128: b580 push {r7, lr}
|
|
800812a: b082 sub sp, #8
|
|
800812c: af00 add r7, sp, #0
|
|
800812e: 4603 mov r3, r0
|
|
8008130: 6039 str r1, [r7, #0]
|
|
8008132: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
8008134: 79fb ldrb r3, [r7, #7]
|
|
8008136: 2b00 cmp r3, #0
|
|
8008138: d105 bne.n 8008146 <USBD_FS_InterfaceStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
|
|
800813a: 683a ldr r2, [r7, #0]
|
|
800813c: 4907 ldr r1, [pc, #28] @ (800815c <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
800813e: 4808 ldr r0, [pc, #32] @ (8008160 <USBD_FS_InterfaceStrDescriptor+0x38>)
|
|
8008140: f7ff fe74 bl 8007e2c <USBD_GetString>
|
|
8008144: e004 b.n 8008150 <USBD_FS_InterfaceStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
|
|
8008146: 683a ldr r2, [r7, #0]
|
|
8008148: 4904 ldr r1, [pc, #16] @ (800815c <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
800814a: 4805 ldr r0, [pc, #20] @ (8008160 <USBD_FS_InterfaceStrDescriptor+0x38>)
|
|
800814c: f7ff fe6e bl 8007e2c <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8008150: 4b02 ldr r3, [pc, #8] @ (800815c <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
}
|
|
8008152: 4618 mov r0, r3
|
|
8008154: 3708 adds r7, #8
|
|
8008156: 46bd mov sp, r7
|
|
8008158: bd80 pop {r7, pc}
|
|
800815a: bf00 nop
|
|
800815c: 20000678 .word 0x20000678
|
|
8008160: 080089c8 .word 0x080089c8
|
|
|
|
08008164 <USBD_FS_USR_BOSDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8008164: b480 push {r7}
|
|
8008166: b083 sub sp, #12
|
|
8008168: af00 add r7, sp, #0
|
|
800816a: 4603 mov r3, r0
|
|
800816c: 6039 str r1, [r7, #0]
|
|
800816e: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_FS_BOSDesc);
|
|
8008170: 683b ldr r3, [r7, #0]
|
|
8008172: 220c movs r2, #12
|
|
8008174: 801a strh r2, [r3, #0]
|
|
return (uint8_t*)USBD_FS_BOSDesc;
|
|
8008176: 4b03 ldr r3, [pc, #12] @ (8008184 <USBD_FS_USR_BOSDescriptor+0x20>)
|
|
}
|
|
8008178: 4618 mov r0, r3
|
|
800817a: 370c adds r7, #12
|
|
800817c: 46bd mov sp, r7
|
|
800817e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008182: 4770 bx lr
|
|
8008184: 20000100 .word 0x20000100
|
|
|
|
08008188 <Get_SerialNum>:
|
|
* @brief Create the serial number string descriptor
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void Get_SerialNum(void)
|
|
{
|
|
8008188: b580 push {r7, lr}
|
|
800818a: b084 sub sp, #16
|
|
800818c: af00 add r7, sp, #0
|
|
uint32_t deviceserial0;
|
|
uint32_t deviceserial1;
|
|
uint32_t deviceserial2;
|
|
|
|
deviceserial0 = *(uint32_t *) DEVICE_ID1;
|
|
800818e: 4b0f ldr r3, [pc, #60] @ (80081cc <Get_SerialNum+0x44>)
|
|
8008190: 681b ldr r3, [r3, #0]
|
|
8008192: 60fb str r3, [r7, #12]
|
|
deviceserial1 = *(uint32_t *) DEVICE_ID2;
|
|
8008194: 4b0e ldr r3, [pc, #56] @ (80081d0 <Get_SerialNum+0x48>)
|
|
8008196: 681b ldr r3, [r3, #0]
|
|
8008198: 60bb str r3, [r7, #8]
|
|
deviceserial2 = *(uint32_t *) DEVICE_ID3;
|
|
800819a: 4b0e ldr r3, [pc, #56] @ (80081d4 <Get_SerialNum+0x4c>)
|
|
800819c: 681b ldr r3, [r3, #0]
|
|
800819e: 607b str r3, [r7, #4]
|
|
|
|
deviceserial0 += deviceserial2;
|
|
80081a0: 68fa ldr r2, [r7, #12]
|
|
80081a2: 687b ldr r3, [r7, #4]
|
|
80081a4: 4413 add r3, r2
|
|
80081a6: 60fb str r3, [r7, #12]
|
|
|
|
if (deviceserial0 != 0)
|
|
80081a8: 68fb ldr r3, [r7, #12]
|
|
80081aa: 2b00 cmp r3, #0
|
|
80081ac: d009 beq.n 80081c2 <Get_SerialNum+0x3a>
|
|
{
|
|
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
|
|
80081ae: 2208 movs r2, #8
|
|
80081b0: 4909 ldr r1, [pc, #36] @ (80081d8 <Get_SerialNum+0x50>)
|
|
80081b2: 68f8 ldr r0, [r7, #12]
|
|
80081b4: f000 f814 bl 80081e0 <IntToUnicode>
|
|
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
|
|
80081b8: 2204 movs r2, #4
|
|
80081ba: 4908 ldr r1, [pc, #32] @ (80081dc <Get_SerialNum+0x54>)
|
|
80081bc: 68b8 ldr r0, [r7, #8]
|
|
80081be: f000 f80f bl 80081e0 <IntToUnicode>
|
|
}
|
|
}
|
|
80081c2: bf00 nop
|
|
80081c4: 3710 adds r7, #16
|
|
80081c6: 46bd mov sp, r7
|
|
80081c8: bd80 pop {r7, pc}
|
|
80081ca: bf00 nop
|
|
80081cc: 1fff7a10 .word 0x1fff7a10
|
|
80081d0: 1fff7a14 .word 0x1fff7a14
|
|
80081d4: 1fff7a18 .word 0x1fff7a18
|
|
80081d8: 20000112 .word 0x20000112
|
|
80081dc: 20000122 .word 0x20000122
|
|
|
|
080081e0 <IntToUnicode>:
|
|
* @param pbuf: pointer to the buffer
|
|
* @param len: buffer length
|
|
* @retval None
|
|
*/
|
|
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
|
|
{
|
|
80081e0: b480 push {r7}
|
|
80081e2: b087 sub sp, #28
|
|
80081e4: af00 add r7, sp, #0
|
|
80081e6: 60f8 str r0, [r7, #12]
|
|
80081e8: 60b9 str r1, [r7, #8]
|
|
80081ea: 4613 mov r3, r2
|
|
80081ec: 71fb strb r3, [r7, #7]
|
|
uint8_t idx = 0;
|
|
80081ee: 2300 movs r3, #0
|
|
80081f0: 75fb strb r3, [r7, #23]
|
|
|
|
for (idx = 0; idx < len; idx++)
|
|
80081f2: 2300 movs r3, #0
|
|
80081f4: 75fb strb r3, [r7, #23]
|
|
80081f6: e027 b.n 8008248 <IntToUnicode+0x68>
|
|
{
|
|
if (((value >> 28)) < 0xA)
|
|
80081f8: 68fb ldr r3, [r7, #12]
|
|
80081fa: 0f1b lsrs r3, r3, #28
|
|
80081fc: 2b09 cmp r3, #9
|
|
80081fe: d80b bhi.n 8008218 <IntToUnicode+0x38>
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + '0';
|
|
8008200: 68fb ldr r3, [r7, #12]
|
|
8008202: 0f1b lsrs r3, r3, #28
|
|
8008204: b2da uxtb r2, r3
|
|
8008206: 7dfb ldrb r3, [r7, #23]
|
|
8008208: 005b lsls r3, r3, #1
|
|
800820a: 4619 mov r1, r3
|
|
800820c: 68bb ldr r3, [r7, #8]
|
|
800820e: 440b add r3, r1
|
|
8008210: 3230 adds r2, #48 @ 0x30
|
|
8008212: b2d2 uxtb r2, r2
|
|
8008214: 701a strb r2, [r3, #0]
|
|
8008216: e00a b.n 800822e <IntToUnicode+0x4e>
|
|
}
|
|
else
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
|
|
8008218: 68fb ldr r3, [r7, #12]
|
|
800821a: 0f1b lsrs r3, r3, #28
|
|
800821c: b2da uxtb r2, r3
|
|
800821e: 7dfb ldrb r3, [r7, #23]
|
|
8008220: 005b lsls r3, r3, #1
|
|
8008222: 4619 mov r1, r3
|
|
8008224: 68bb ldr r3, [r7, #8]
|
|
8008226: 440b add r3, r1
|
|
8008228: 3237 adds r2, #55 @ 0x37
|
|
800822a: b2d2 uxtb r2, r2
|
|
800822c: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
value = value << 4;
|
|
800822e: 68fb ldr r3, [r7, #12]
|
|
8008230: 011b lsls r3, r3, #4
|
|
8008232: 60fb str r3, [r7, #12]
|
|
|
|
pbuf[2 * idx + 1] = 0;
|
|
8008234: 7dfb ldrb r3, [r7, #23]
|
|
8008236: 005b lsls r3, r3, #1
|
|
8008238: 3301 adds r3, #1
|
|
800823a: 68ba ldr r2, [r7, #8]
|
|
800823c: 4413 add r3, r2
|
|
800823e: 2200 movs r2, #0
|
|
8008240: 701a strb r2, [r3, #0]
|
|
for (idx = 0; idx < len; idx++)
|
|
8008242: 7dfb ldrb r3, [r7, #23]
|
|
8008244: 3301 adds r3, #1
|
|
8008246: 75fb strb r3, [r7, #23]
|
|
8008248: 7dfa ldrb r2, [r7, #23]
|
|
800824a: 79fb ldrb r3, [r7, #7]
|
|
800824c: 429a cmp r2, r3
|
|
800824e: d3d3 bcc.n 80081f8 <IntToUnicode+0x18>
|
|
}
|
|
}
|
|
8008250: bf00 nop
|
|
8008252: bf00 nop
|
|
8008254: 371c adds r7, #28
|
|
8008256: 46bd mov sp, r7
|
|
8008258: f85d 7b04 ldr.w r7, [sp], #4
|
|
800825c: 4770 bx lr
|
|
...
|
|
|
|
08008260 <HAL_PCD_MspInit>:
|
|
LL Driver Callbacks (PCD -> USB Device Library)
|
|
*******************************************************************************/
|
|
/* MSP Init */
|
|
|
|
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
|
|
{
|
|
8008260: b580 push {r7, lr}
|
|
8008262: b0a0 sub sp, #128 @ 0x80
|
|
8008264: af00 add r7, sp, #0
|
|
8008266: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8008268: f107 036c add.w r3, r7, #108 @ 0x6c
|
|
800826c: 2200 movs r2, #0
|
|
800826e: 601a str r2, [r3, #0]
|
|
8008270: 605a str r2, [r3, #4]
|
|
8008272: 609a str r2, [r3, #8]
|
|
8008274: 60da str r2, [r3, #12]
|
|
8008276: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
8008278: f107 0310 add.w r3, r7, #16
|
|
800827c: 225c movs r2, #92 @ 0x5c
|
|
800827e: 2100 movs r1, #0
|
|
8008280: 4618 mov r0, r3
|
|
8008282: f000 fb53 bl 800892c <memset>
|
|
if(pcdHandle->Instance==USB_OTG_FS)
|
|
8008286: 687b ldr r3, [r7, #4]
|
|
8008288: 681b ldr r3, [r3, #0]
|
|
800828a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
800828e: d149 bne.n 8008324 <HAL_PCD_MspInit+0xc4>
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
|
|
8008290: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8008294: 613b str r3, [r7, #16]
|
|
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ;
|
|
8008296: 2300 movs r3, #0
|
|
8008298: 667b str r3, [r7, #100] @ 0x64
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
800829a: f107 0310 add.w r3, r7, #16
|
|
800829e: 4618 mov r0, r3
|
|
80082a0: f7fa ff1c bl 80030dc <HAL_RCCEx_PeriphCLKConfig>
|
|
80082a4: 4603 mov r3, r0
|
|
80082a6: 2b00 cmp r3, #0
|
|
80082a8: d001 beq.n 80082ae <HAL_PCD_MspInit+0x4e>
|
|
{
|
|
Error_Handler();
|
|
80082aa: f7f8 fc15 bl 8000ad8 <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80082ae: 2300 movs r3, #0
|
|
80082b0: 60fb str r3, [r7, #12]
|
|
80082b2: 4b1e ldr r3, [pc, #120] @ (800832c <HAL_PCD_MspInit+0xcc>)
|
|
80082b4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80082b6: 4a1d ldr r2, [pc, #116] @ (800832c <HAL_PCD_MspInit+0xcc>)
|
|
80082b8: f043 0301 orr.w r3, r3, #1
|
|
80082bc: 6313 str r3, [r2, #48] @ 0x30
|
|
80082be: 4b1b ldr r3, [pc, #108] @ (800832c <HAL_PCD_MspInit+0xcc>)
|
|
80082c0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80082c2: f003 0301 and.w r3, r3, #1
|
|
80082c6: 60fb str r3, [r7, #12]
|
|
80082c8: 68fb ldr r3, [r7, #12]
|
|
/**USB_OTG_FS GPIO Configuration
|
|
PA11 ------> USB_OTG_FS_DM
|
|
PA12 ------> USB_OTG_FS_DP
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
|
|
80082ca: f44f 53c0 mov.w r3, #6144 @ 0x1800
|
|
80082ce: 66fb str r3, [r7, #108] @ 0x6c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80082d0: 2302 movs r3, #2
|
|
80082d2: 673b str r3, [r7, #112] @ 0x70
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80082d4: 2300 movs r3, #0
|
|
80082d6: 677b str r3, [r7, #116] @ 0x74
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80082d8: 2303 movs r3, #3
|
|
80082da: 67bb str r3, [r7, #120] @ 0x78
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
|
|
80082dc: 230a movs r3, #10
|
|
80082de: 67fb str r3, [r7, #124] @ 0x7c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80082e0: f107 036c add.w r3, r7, #108 @ 0x6c
|
|
80082e4: 4619 mov r1, r3
|
|
80082e6: 4812 ldr r0, [pc, #72] @ (8008330 <HAL_PCD_MspInit+0xd0>)
|
|
80082e8: f7f9 f866 bl 80013b8 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
|
|
80082ec: 4b0f ldr r3, [pc, #60] @ (800832c <HAL_PCD_MspInit+0xcc>)
|
|
80082ee: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80082f0: 4a0e ldr r2, [pc, #56] @ (800832c <HAL_PCD_MspInit+0xcc>)
|
|
80082f2: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80082f6: 6353 str r3, [r2, #52] @ 0x34
|
|
80082f8: 2300 movs r3, #0
|
|
80082fa: 60bb str r3, [r7, #8]
|
|
80082fc: 4b0b ldr r3, [pc, #44] @ (800832c <HAL_PCD_MspInit+0xcc>)
|
|
80082fe: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008300: 4a0a ldr r2, [pc, #40] @ (800832c <HAL_PCD_MspInit+0xcc>)
|
|
8008302: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8008306: 6453 str r3, [r2, #68] @ 0x44
|
|
8008308: 4b08 ldr r3, [pc, #32] @ (800832c <HAL_PCD_MspInit+0xcc>)
|
|
800830a: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800830c: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8008310: 60bb str r3, [r7, #8]
|
|
8008312: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Peripheral interrupt init */
|
|
HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
|
|
8008314: 2200 movs r2, #0
|
|
8008316: 2100 movs r1, #0
|
|
8008318: 2043 movs r0, #67 @ 0x43
|
|
800831a: f7f9 f816 bl 800134a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
|
|
800831e: 2043 movs r0, #67 @ 0x43
|
|
8008320: f7f9 f82f bl 8001382 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 1 */
|
|
}
|
|
}
|
|
8008324: bf00 nop
|
|
8008326: 3780 adds r7, #128 @ 0x80
|
|
8008328: 46bd mov sp, r7
|
|
800832a: bd80 pop {r7, pc}
|
|
800832c: 40023800 .word 0x40023800
|
|
8008330: 40020000 .word 0x40020000
|
|
|
|
08008334 <HAL_PCD_SetupStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8008334: b580 push {r7, lr}
|
|
8008336: b082 sub sp, #8
|
|
8008338: af00 add r7, sp, #0
|
|
800833a: 6078 str r0, [r7, #4]
|
|
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
|
|
800833c: 687b ldr r3, [r7, #4]
|
|
800833e: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0
|
|
8008342: 687b ldr r3, [r7, #4]
|
|
8008344: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8008348: 4619 mov r1, r3
|
|
800834a: 4610 mov r0, r2
|
|
800834c: f7fe fbcb bl 8006ae6 <USBD_LL_SetupStage>
|
|
}
|
|
8008350: bf00 nop
|
|
8008352: 3708 adds r7, #8
|
|
8008354: 46bd mov sp, r7
|
|
8008356: bd80 pop {r7, pc}
|
|
|
|
08008358 <HAL_PCD_DataOutStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8008358: b580 push {r7, lr}
|
|
800835a: b082 sub sp, #8
|
|
800835c: af00 add r7, sp, #0
|
|
800835e: 6078 str r0, [r7, #4]
|
|
8008360: 460b mov r3, r1
|
|
8008362: 70fb strb r3, [r7, #3]
|
|
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
|
|
8008364: 687b ldr r3, [r7, #4]
|
|
8008366: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
|
|
800836a: 78fa ldrb r2, [r7, #3]
|
|
800836c: 6879 ldr r1, [r7, #4]
|
|
800836e: 4613 mov r3, r2
|
|
8008370: 00db lsls r3, r3, #3
|
|
8008372: 4413 add r3, r2
|
|
8008374: 009b lsls r3, r3, #2
|
|
8008376: 440b add r3, r1
|
|
8008378: f503 7318 add.w r3, r3, #608 @ 0x260
|
|
800837c: 681a ldr r2, [r3, #0]
|
|
800837e: 78fb ldrb r3, [r7, #3]
|
|
8008380: 4619 mov r1, r3
|
|
8008382: f7fe fc05 bl 8006b90 <USBD_LL_DataOutStage>
|
|
}
|
|
8008386: bf00 nop
|
|
8008388: 3708 adds r7, #8
|
|
800838a: 46bd mov sp, r7
|
|
800838c: bd80 pop {r7, pc}
|
|
|
|
0800838e <HAL_PCD_DataInStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800838e: b580 push {r7, lr}
|
|
8008390: b082 sub sp, #8
|
|
8008392: af00 add r7, sp, #0
|
|
8008394: 6078 str r0, [r7, #4]
|
|
8008396: 460b mov r3, r1
|
|
8008398: 70fb strb r3, [r7, #3]
|
|
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
|
|
800839a: 687b ldr r3, [r7, #4]
|
|
800839c: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
|
|
80083a0: 78fa ldrb r2, [r7, #3]
|
|
80083a2: 6879 ldr r1, [r7, #4]
|
|
80083a4: 4613 mov r3, r2
|
|
80083a6: 00db lsls r3, r3, #3
|
|
80083a8: 4413 add r3, r2
|
|
80083aa: 009b lsls r3, r3, #2
|
|
80083ac: 440b add r3, r1
|
|
80083ae: 3320 adds r3, #32
|
|
80083b0: 681a ldr r2, [r3, #0]
|
|
80083b2: 78fb ldrb r3, [r7, #3]
|
|
80083b4: 4619 mov r1, r3
|
|
80083b6: f7fe fca7 bl 8006d08 <USBD_LL_DataInStage>
|
|
}
|
|
80083ba: bf00 nop
|
|
80083bc: 3708 adds r7, #8
|
|
80083be: 46bd mov sp, r7
|
|
80083c0: bd80 pop {r7, pc}
|
|
|
|
080083c2 <HAL_PCD_SOFCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
80083c2: b580 push {r7, lr}
|
|
80083c4: b082 sub sp, #8
|
|
80083c6: af00 add r7, sp, #0
|
|
80083c8: 6078 str r0, [r7, #4]
|
|
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
|
|
80083ca: 687b ldr r3, [r7, #4]
|
|
80083cc: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
80083d0: 4618 mov r0, r3
|
|
80083d2: f7fe fdeb bl 8006fac <USBD_LL_SOF>
|
|
}
|
|
80083d6: bf00 nop
|
|
80083d8: 3708 adds r7, #8
|
|
80083da: 46bd mov sp, r7
|
|
80083dc: bd80 pop {r7, pc}
|
|
|
|
080083de <HAL_PCD_ResetCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
80083de: b580 push {r7, lr}
|
|
80083e0: b084 sub sp, #16
|
|
80083e2: af00 add r7, sp, #0
|
|
80083e4: 6078 str r0, [r7, #4]
|
|
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
|
|
80083e6: 2301 movs r3, #1
|
|
80083e8: 73fb strb r3, [r7, #15]
|
|
|
|
if ( hpcd->Init.speed == PCD_SPEED_HIGH)
|
|
80083ea: 687b ldr r3, [r7, #4]
|
|
80083ec: 79db ldrb r3, [r3, #7]
|
|
80083ee: 2b00 cmp r3, #0
|
|
80083f0: d102 bne.n 80083f8 <HAL_PCD_ResetCallback+0x1a>
|
|
{
|
|
speed = USBD_SPEED_HIGH;
|
|
80083f2: 2300 movs r3, #0
|
|
80083f4: 73fb strb r3, [r7, #15]
|
|
80083f6: e008 b.n 800840a <HAL_PCD_ResetCallback+0x2c>
|
|
}
|
|
else if ( hpcd->Init.speed == PCD_SPEED_FULL)
|
|
80083f8: 687b ldr r3, [r7, #4]
|
|
80083fa: 79db ldrb r3, [r3, #7]
|
|
80083fc: 2b02 cmp r3, #2
|
|
80083fe: d102 bne.n 8008406 <HAL_PCD_ResetCallback+0x28>
|
|
{
|
|
speed = USBD_SPEED_FULL;
|
|
8008400: 2301 movs r3, #1
|
|
8008402: 73fb strb r3, [r7, #15]
|
|
8008404: e001 b.n 800840a <HAL_PCD_ResetCallback+0x2c>
|
|
}
|
|
else
|
|
{
|
|
Error_Handler();
|
|
8008406: f7f8 fb67 bl 8000ad8 <Error_Handler>
|
|
}
|
|
/* Set Speed. */
|
|
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
|
|
800840a: 687b ldr r3, [r7, #4]
|
|
800840c: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
8008410: 7bfa ldrb r2, [r7, #15]
|
|
8008412: 4611 mov r1, r2
|
|
8008414: 4618 mov r0, r3
|
|
8008416: f7fe fd85 bl 8006f24 <USBD_LL_SetSpeed>
|
|
|
|
/* Reset Device. */
|
|
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
|
|
800841a: 687b ldr r3, [r7, #4]
|
|
800841c: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
8008420: 4618 mov r0, r3
|
|
8008422: f7fe fd2c bl 8006e7e <USBD_LL_Reset>
|
|
}
|
|
8008426: bf00 nop
|
|
8008428: 3710 adds r7, #16
|
|
800842a: 46bd mov sp, r7
|
|
800842c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08008430 <HAL_PCD_SuspendCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8008430: b580 push {r7, lr}
|
|
8008432: b082 sub sp, #8
|
|
8008434: af00 add r7, sp, #0
|
|
8008436: 6078 str r0, [r7, #4]
|
|
/* Inform USB library that core enters in suspend Mode. */
|
|
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
|
|
8008438: 687b ldr r3, [r7, #4]
|
|
800843a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800843e: 4618 mov r0, r3
|
|
8008440: f7fe fd80 bl 8006f44 <USBD_LL_Suspend>
|
|
__HAL_PCD_GATE_PHYCLOCK(hpcd);
|
|
8008444: 687b ldr r3, [r7, #4]
|
|
8008446: 681b ldr r3, [r3, #0]
|
|
8008448: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
800844c: 681b ldr r3, [r3, #0]
|
|
800844e: 687a ldr r2, [r7, #4]
|
|
8008450: 6812 ldr r2, [r2, #0]
|
|
8008452: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
8008456: f043 0301 orr.w r3, r3, #1
|
|
800845a: 6013 str r3, [r2, #0]
|
|
/* Enter in STOP mode. */
|
|
/* USER CODE BEGIN 2 */
|
|
if (hpcd->Init.low_power_enable)
|
|
800845c: 687b ldr r3, [r7, #4]
|
|
800845e: 7adb ldrb r3, [r3, #11]
|
|
8008460: 2b00 cmp r3, #0
|
|
8008462: d005 beq.n 8008470 <HAL_PCD_SuspendCallback+0x40>
|
|
{
|
|
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
8008464: 4b04 ldr r3, [pc, #16] @ (8008478 <HAL_PCD_SuspendCallback+0x48>)
|
|
8008466: 691b ldr r3, [r3, #16]
|
|
8008468: 4a03 ldr r2, [pc, #12] @ (8008478 <HAL_PCD_SuspendCallback+0x48>)
|
|
800846a: f043 0306 orr.w r3, r3, #6
|
|
800846e: 6113 str r3, [r2, #16]
|
|
}
|
|
/* USER CODE END 2 */
|
|
}
|
|
8008470: bf00 nop
|
|
8008472: 3708 adds r7, #8
|
|
8008474: 46bd mov sp, r7
|
|
8008476: bd80 pop {r7, pc}
|
|
8008478: e000ed00 .word 0xe000ed00
|
|
|
|
0800847c <HAL_PCD_ResumeCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800847c: b580 push {r7, lr}
|
|
800847e: b082 sub sp, #8
|
|
8008480: af00 add r7, sp, #0
|
|
8008482: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN 3 */
|
|
|
|
/* USER CODE END 3 */
|
|
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
|
|
8008484: 687b ldr r3, [r7, #4]
|
|
8008486: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800848a: 4618 mov r0, r3
|
|
800848c: f7fe fd76 bl 8006f7c <USBD_LL_Resume>
|
|
}
|
|
8008490: bf00 nop
|
|
8008492: 3708 adds r7, #8
|
|
8008494: 46bd mov sp, r7
|
|
8008496: bd80 pop {r7, pc}
|
|
|
|
08008498 <HAL_PCD_ISOOUTIncompleteCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8008498: b580 push {r7, lr}
|
|
800849a: b082 sub sp, #8
|
|
800849c: af00 add r7, sp, #0
|
|
800849e: 6078 str r0, [r7, #4]
|
|
80084a0: 460b mov r3, r1
|
|
80084a2: 70fb strb r3, [r7, #3]
|
|
USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
|
|
80084a4: 687b ldr r3, [r7, #4]
|
|
80084a6: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
80084aa: 78fa ldrb r2, [r7, #3]
|
|
80084ac: 4611 mov r1, r2
|
|
80084ae: 4618 mov r0, r3
|
|
80084b0: f7fe fdce bl 8007050 <USBD_LL_IsoOUTIncomplete>
|
|
}
|
|
80084b4: bf00 nop
|
|
80084b6: 3708 adds r7, #8
|
|
80084b8: 46bd mov sp, r7
|
|
80084ba: bd80 pop {r7, pc}
|
|
|
|
080084bc <HAL_PCD_ISOINIncompleteCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
80084bc: b580 push {r7, lr}
|
|
80084be: b082 sub sp, #8
|
|
80084c0: af00 add r7, sp, #0
|
|
80084c2: 6078 str r0, [r7, #4]
|
|
80084c4: 460b mov r3, r1
|
|
80084c6: 70fb strb r3, [r7, #3]
|
|
USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
|
|
80084c8: 687b ldr r3, [r7, #4]
|
|
80084ca: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
80084ce: 78fa ldrb r2, [r7, #3]
|
|
80084d0: 4611 mov r1, r2
|
|
80084d2: 4618 mov r0, r3
|
|
80084d4: f7fe fd8a bl 8006fec <USBD_LL_IsoINIncomplete>
|
|
}
|
|
80084d8: bf00 nop
|
|
80084da: 3708 adds r7, #8
|
|
80084dc: 46bd mov sp, r7
|
|
80084de: bd80 pop {r7, pc}
|
|
|
|
080084e0 <HAL_PCD_ConnectCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
80084e0: b580 push {r7, lr}
|
|
80084e2: b082 sub sp, #8
|
|
80084e4: af00 add r7, sp, #0
|
|
80084e6: 6078 str r0, [r7, #4]
|
|
USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
|
|
80084e8: 687b ldr r3, [r7, #4]
|
|
80084ea: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
80084ee: 4618 mov r0, r3
|
|
80084f0: f7fe fde0 bl 80070b4 <USBD_LL_DevConnected>
|
|
}
|
|
80084f4: bf00 nop
|
|
80084f6: 3708 adds r7, #8
|
|
80084f8: 46bd mov sp, r7
|
|
80084fa: bd80 pop {r7, pc}
|
|
|
|
080084fc <HAL_PCD_DisconnectCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
80084fc: b580 push {r7, lr}
|
|
80084fe: b082 sub sp, #8
|
|
8008500: af00 add r7, sp, #0
|
|
8008502: 6078 str r0, [r7, #4]
|
|
USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
|
|
8008504: 687b ldr r3, [r7, #4]
|
|
8008506: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800850a: 4618 mov r0, r3
|
|
800850c: f7fe fddd bl 80070ca <USBD_LL_DevDisconnected>
|
|
}
|
|
8008510: bf00 nop
|
|
8008512: 3708 adds r7, #8
|
|
8008514: 46bd mov sp, r7
|
|
8008516: bd80 pop {r7, pc}
|
|
|
|
08008518 <USBD_LL_Init>:
|
|
* @brief Initializes the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008518: b580 push {r7, lr}
|
|
800851a: b082 sub sp, #8
|
|
800851c: af00 add r7, sp, #0
|
|
800851e: 6078 str r0, [r7, #4]
|
|
/* Init USB Ip. */
|
|
if (pdev->id == DEVICE_FS) {
|
|
8008520: 687b ldr r3, [r7, #4]
|
|
8008522: 781b ldrb r3, [r3, #0]
|
|
8008524: 2b00 cmp r3, #0
|
|
8008526: d13c bne.n 80085a2 <USBD_LL_Init+0x8a>
|
|
/* Link the driver to the stack. */
|
|
hpcd_USB_OTG_FS.pData = pdev;
|
|
8008528: 4a20 ldr r2, [pc, #128] @ (80085ac <USBD_LL_Init+0x94>)
|
|
800852a: 687b ldr r3, [r7, #4]
|
|
800852c: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0
|
|
pdev->pData = &hpcd_USB_OTG_FS;
|
|
8008530: 687b ldr r3, [r7, #4]
|
|
8008532: 4a1e ldr r2, [pc, #120] @ (80085ac <USBD_LL_Init+0x94>)
|
|
8008534: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8
|
|
|
|
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
|
|
8008538: 4b1c ldr r3, [pc, #112] @ (80085ac <USBD_LL_Init+0x94>)
|
|
800853a: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
|
|
800853e: 601a str r2, [r3, #0]
|
|
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
|
|
8008540: 4b1a ldr r3, [pc, #104] @ (80085ac <USBD_LL_Init+0x94>)
|
|
8008542: 2206 movs r2, #6
|
|
8008544: 711a strb r2, [r3, #4]
|
|
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
|
|
8008546: 4b19 ldr r3, [pc, #100] @ (80085ac <USBD_LL_Init+0x94>)
|
|
8008548: 2202 movs r2, #2
|
|
800854a: 71da strb r2, [r3, #7]
|
|
hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
|
|
800854c: 4b17 ldr r3, [pc, #92] @ (80085ac <USBD_LL_Init+0x94>)
|
|
800854e: 2200 movs r2, #0
|
|
8008550: 719a strb r2, [r3, #6]
|
|
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
|
|
8008552: 4b16 ldr r3, [pc, #88] @ (80085ac <USBD_LL_Init+0x94>)
|
|
8008554: 2202 movs r2, #2
|
|
8008556: 725a strb r2, [r3, #9]
|
|
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
|
|
8008558: 4b14 ldr r3, [pc, #80] @ (80085ac <USBD_LL_Init+0x94>)
|
|
800855a: 2200 movs r2, #0
|
|
800855c: 729a strb r2, [r3, #10]
|
|
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
|
|
800855e: 4b13 ldr r3, [pc, #76] @ (80085ac <USBD_LL_Init+0x94>)
|
|
8008560: 2200 movs r2, #0
|
|
8008562: 72da strb r2, [r3, #11]
|
|
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
|
|
8008564: 4b11 ldr r3, [pc, #68] @ (80085ac <USBD_LL_Init+0x94>)
|
|
8008566: 2200 movs r2, #0
|
|
8008568: 731a strb r2, [r3, #12]
|
|
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
|
|
800856a: 4b10 ldr r3, [pc, #64] @ (80085ac <USBD_LL_Init+0x94>)
|
|
800856c: 2200 movs r2, #0
|
|
800856e: 739a strb r2, [r3, #14]
|
|
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
|
|
8008570: 4b0e ldr r3, [pc, #56] @ (80085ac <USBD_LL_Init+0x94>)
|
|
8008572: 2200 movs r2, #0
|
|
8008574: 73da strb r2, [r3, #15]
|
|
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
|
|
8008576: 480d ldr r0, [pc, #52] @ (80085ac <USBD_LL_Init+0x94>)
|
|
8008578: f7f9 fa10 bl 800199c <HAL_PCD_Init>
|
|
800857c: 4603 mov r3, r0
|
|
800857e: 2b00 cmp r3, #0
|
|
8008580: d001 beq.n 8008586 <USBD_LL_Init+0x6e>
|
|
{
|
|
Error_Handler( );
|
|
8008582: f7f8 faa9 bl 8000ad8 <Error_Handler>
|
|
HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback);
|
|
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback);
|
|
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
|
|
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
|
|
8008586: 2180 movs r1, #128 @ 0x80
|
|
8008588: 4808 ldr r0, [pc, #32] @ (80085ac <USBD_LL_Init+0x94>)
|
|
800858a: f7fa fc58 bl 8002e3e <HAL_PCDEx_SetRxFiFo>
|
|
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
|
|
800858e: 2240 movs r2, #64 @ 0x40
|
|
8008590: 2100 movs r1, #0
|
|
8008592: 4806 ldr r0, [pc, #24] @ (80085ac <USBD_LL_Init+0x94>)
|
|
8008594: f7fa fc0c bl 8002db0 <HAL_PCDEx_SetTxFiFo>
|
|
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
|
|
8008598: 2280 movs r2, #128 @ 0x80
|
|
800859a: 2101 movs r1, #1
|
|
800859c: 4803 ldr r0, [pc, #12] @ (80085ac <USBD_LL_Init+0x94>)
|
|
800859e: f7fa fc07 bl 8002db0 <HAL_PCDEx_SetTxFiFo>
|
|
}
|
|
return USBD_OK;
|
|
80085a2: 2300 movs r3, #0
|
|
}
|
|
80085a4: 4618 mov r0, r3
|
|
80085a6: 3708 adds r7, #8
|
|
80085a8: 46bd mov sp, r7
|
|
80085aa: bd80 pop {r7, pc}
|
|
80085ac: 20000878 .word 0x20000878
|
|
|
|
080085b0 <USBD_LL_Start>:
|
|
* @brief Starts the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80085b0: b580 push {r7, lr}
|
|
80085b2: b084 sub sp, #16
|
|
80085b4: af00 add r7, sp, #0
|
|
80085b6: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80085b8: 2300 movs r3, #0
|
|
80085ba: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80085bc: 2300 movs r3, #0
|
|
80085be: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_Start(pdev->pData);
|
|
80085c0: 687b ldr r3, [r7, #4]
|
|
80085c2: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
80085c6: 4618 mov r0, r3
|
|
80085c8: f7f9 fafe bl 8001bc8 <HAL_PCD_Start>
|
|
80085cc: 4603 mov r3, r0
|
|
80085ce: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80085d0: 7bfb ldrb r3, [r7, #15]
|
|
80085d2: 4618 mov r0, r3
|
|
80085d4: f000 f97e bl 80088d4 <USBD_Get_USB_Status>
|
|
80085d8: 4603 mov r3, r0
|
|
80085da: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
80085dc: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
80085de: 4618 mov r0, r3
|
|
80085e0: 3710 adds r7, #16
|
|
80085e2: 46bd mov sp, r7
|
|
80085e4: bd80 pop {r7, pc}
|
|
|
|
080085e6 <USBD_LL_OpenEP>:
|
|
* @param ep_type: Endpoint type
|
|
* @param ep_mps: Endpoint max packet size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
|
|
{
|
|
80085e6: b580 push {r7, lr}
|
|
80085e8: b084 sub sp, #16
|
|
80085ea: af00 add r7, sp, #0
|
|
80085ec: 6078 str r0, [r7, #4]
|
|
80085ee: 4608 mov r0, r1
|
|
80085f0: 4611 mov r1, r2
|
|
80085f2: 461a mov r2, r3
|
|
80085f4: 4603 mov r3, r0
|
|
80085f6: 70fb strb r3, [r7, #3]
|
|
80085f8: 460b mov r3, r1
|
|
80085fa: 70bb strb r3, [r7, #2]
|
|
80085fc: 4613 mov r3, r2
|
|
80085fe: 803b strh r3, [r7, #0]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8008600: 2300 movs r3, #0
|
|
8008602: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8008604: 2300 movs r3, #0
|
|
8008606: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
|
|
8008608: 687b ldr r3, [r7, #4]
|
|
800860a: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
800860e: 78bb ldrb r3, [r7, #2]
|
|
8008610: 883a ldrh r2, [r7, #0]
|
|
8008612: 78f9 ldrb r1, [r7, #3]
|
|
8008614: f7f9 ffff bl 8002616 <HAL_PCD_EP_Open>
|
|
8008618: 4603 mov r3, r0
|
|
800861a: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800861c: 7bfb ldrb r3, [r7, #15]
|
|
800861e: 4618 mov r0, r3
|
|
8008620: f000 f958 bl 80088d4 <USBD_Get_USB_Status>
|
|
8008624: 4603 mov r3, r0
|
|
8008626: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8008628: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800862a: 4618 mov r0, r3
|
|
800862c: 3710 adds r7, #16
|
|
800862e: 46bd mov sp, r7
|
|
8008630: bd80 pop {r7, pc}
|
|
|
|
08008632 <USBD_LL_CloseEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
8008632: b580 push {r7, lr}
|
|
8008634: b084 sub sp, #16
|
|
8008636: af00 add r7, sp, #0
|
|
8008638: 6078 str r0, [r7, #4]
|
|
800863a: 460b mov r3, r1
|
|
800863c: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800863e: 2300 movs r3, #0
|
|
8008640: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8008642: 2300 movs r3, #0
|
|
8008644: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
|
|
8008646: 687b ldr r3, [r7, #4]
|
|
8008648: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800864c: 78fa ldrb r2, [r7, #3]
|
|
800864e: 4611 mov r1, r2
|
|
8008650: 4618 mov r0, r3
|
|
8008652: f7fa f84a bl 80026ea <HAL_PCD_EP_Close>
|
|
8008656: 4603 mov r3, r0
|
|
8008658: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800865a: 7bfb ldrb r3, [r7, #15]
|
|
800865c: 4618 mov r0, r3
|
|
800865e: f000 f939 bl 80088d4 <USBD_Get_USB_Status>
|
|
8008662: 4603 mov r3, r0
|
|
8008664: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8008666: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8008668: 4618 mov r0, r3
|
|
800866a: 3710 adds r7, #16
|
|
800866c: 46bd mov sp, r7
|
|
800866e: bd80 pop {r7, pc}
|
|
|
|
08008670 <USBD_LL_StallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
8008670: b580 push {r7, lr}
|
|
8008672: b084 sub sp, #16
|
|
8008674: af00 add r7, sp, #0
|
|
8008676: 6078 str r0, [r7, #4]
|
|
8008678: 460b mov r3, r1
|
|
800867a: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800867c: 2300 movs r3, #0
|
|
800867e: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8008680: 2300 movs r3, #0
|
|
8008682: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
|
|
8008684: 687b ldr r3, [r7, #4]
|
|
8008686: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800868a: 78fa ldrb r2, [r7, #3]
|
|
800868c: 4611 mov r1, r2
|
|
800868e: 4618 mov r0, r3
|
|
8008690: f7fa f8ea bl 8002868 <HAL_PCD_EP_SetStall>
|
|
8008694: 4603 mov r3, r0
|
|
8008696: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8008698: 7bfb ldrb r3, [r7, #15]
|
|
800869a: 4618 mov r0, r3
|
|
800869c: f000 f91a bl 80088d4 <USBD_Get_USB_Status>
|
|
80086a0: 4603 mov r3, r0
|
|
80086a2: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
80086a4: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
80086a6: 4618 mov r0, r3
|
|
80086a8: 3710 adds r7, #16
|
|
80086aa: 46bd mov sp, r7
|
|
80086ac: bd80 pop {r7, pc}
|
|
|
|
080086ae <USBD_LL_ClearStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
80086ae: b580 push {r7, lr}
|
|
80086b0: b084 sub sp, #16
|
|
80086b2: af00 add r7, sp, #0
|
|
80086b4: 6078 str r0, [r7, #4]
|
|
80086b6: 460b mov r3, r1
|
|
80086b8: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80086ba: 2300 movs r3, #0
|
|
80086bc: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80086be: 2300 movs r3, #0
|
|
80086c0: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
|
|
80086c2: 687b ldr r3, [r7, #4]
|
|
80086c4: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
80086c8: 78fa ldrb r2, [r7, #3]
|
|
80086ca: 4611 mov r1, r2
|
|
80086cc: 4618 mov r0, r3
|
|
80086ce: f7fa f92e bl 800292e <HAL_PCD_EP_ClrStall>
|
|
80086d2: 4603 mov r3, r0
|
|
80086d4: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80086d6: 7bfb ldrb r3, [r7, #15]
|
|
80086d8: 4618 mov r0, r3
|
|
80086da: f000 f8fb bl 80088d4 <USBD_Get_USB_Status>
|
|
80086de: 4603 mov r3, r0
|
|
80086e0: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
80086e2: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
80086e4: 4618 mov r0, r3
|
|
80086e6: 3710 adds r7, #16
|
|
80086e8: 46bd mov sp, r7
|
|
80086ea: bd80 pop {r7, pc}
|
|
|
|
080086ec <USBD_LL_IsStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval Stall (1: Yes, 0: No)
|
|
*/
|
|
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
80086ec: b480 push {r7}
|
|
80086ee: b085 sub sp, #20
|
|
80086f0: af00 add r7, sp, #0
|
|
80086f2: 6078 str r0, [r7, #4]
|
|
80086f4: 460b mov r3, r1
|
|
80086f6: 70fb strb r3, [r7, #3]
|
|
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
|
|
80086f8: 687b ldr r3, [r7, #4]
|
|
80086fa: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
80086fe: 60fb str r3, [r7, #12]
|
|
|
|
if((ep_addr & 0x80) == 0x80)
|
|
8008700: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8008704: 2b00 cmp r3, #0
|
|
8008706: da0b bge.n 8008720 <USBD_LL_IsStallEP+0x34>
|
|
{
|
|
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
|
|
8008708: 78fb ldrb r3, [r7, #3]
|
|
800870a: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
800870e: 68f9 ldr r1, [r7, #12]
|
|
8008710: 4613 mov r3, r2
|
|
8008712: 00db lsls r3, r3, #3
|
|
8008714: 4413 add r3, r2
|
|
8008716: 009b lsls r3, r3, #2
|
|
8008718: 440b add r3, r1
|
|
800871a: 3316 adds r3, #22
|
|
800871c: 781b ldrb r3, [r3, #0]
|
|
800871e: e00b b.n 8008738 <USBD_LL_IsStallEP+0x4c>
|
|
}
|
|
else
|
|
{
|
|
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
|
|
8008720: 78fb ldrb r3, [r7, #3]
|
|
8008722: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
8008726: 68f9 ldr r1, [r7, #12]
|
|
8008728: 4613 mov r3, r2
|
|
800872a: 00db lsls r3, r3, #3
|
|
800872c: 4413 add r3, r2
|
|
800872e: 009b lsls r3, r3, #2
|
|
8008730: 440b add r3, r1
|
|
8008732: f203 2356 addw r3, r3, #598 @ 0x256
|
|
8008736: 781b ldrb r3, [r3, #0]
|
|
}
|
|
}
|
|
8008738: 4618 mov r0, r3
|
|
800873a: 3714 adds r7, #20
|
|
800873c: 46bd mov sp, r7
|
|
800873e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008742: 4770 bx lr
|
|
|
|
08008744 <USBD_LL_SetUSBAddress>:
|
|
* @param pdev: Device handle
|
|
* @param dev_addr: Device address
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
|
|
{
|
|
8008744: b580 push {r7, lr}
|
|
8008746: b084 sub sp, #16
|
|
8008748: af00 add r7, sp, #0
|
|
800874a: 6078 str r0, [r7, #4]
|
|
800874c: 460b mov r3, r1
|
|
800874e: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8008750: 2300 movs r3, #0
|
|
8008752: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8008754: 2300 movs r3, #0
|
|
8008756: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
|
|
8008758: 687b ldr r3, [r7, #4]
|
|
800875a: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800875e: 78fa ldrb r2, [r7, #3]
|
|
8008760: 4611 mov r1, r2
|
|
8008762: 4618 mov r0, r3
|
|
8008764: f7f9 ff33 bl 80025ce <HAL_PCD_SetAddress>
|
|
8008768: 4603 mov r3, r0
|
|
800876a: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800876c: 7bfb ldrb r3, [r7, #15]
|
|
800876e: 4618 mov r0, r3
|
|
8008770: f000 f8b0 bl 80088d4 <USBD_Get_USB_Status>
|
|
8008774: 4603 mov r3, r0
|
|
8008776: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8008778: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800877a: 4618 mov r0, r3
|
|
800877c: 3710 adds r7, #16
|
|
800877e: 46bd mov sp, r7
|
|
8008780: bd80 pop {r7, pc}
|
|
|
|
08008782 <USBD_LL_Transmit>:
|
|
* @param pbuf: Pointer to data to be sent
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
|
|
{
|
|
8008782: b580 push {r7, lr}
|
|
8008784: b086 sub sp, #24
|
|
8008786: af00 add r7, sp, #0
|
|
8008788: 60f8 str r0, [r7, #12]
|
|
800878a: 607a str r2, [r7, #4]
|
|
800878c: 603b str r3, [r7, #0]
|
|
800878e: 460b mov r3, r1
|
|
8008790: 72fb strb r3, [r7, #11]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8008792: 2300 movs r3, #0
|
|
8008794: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8008796: 2300 movs r3, #0
|
|
8008798: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
|
|
800879a: 68fb ldr r3, [r7, #12]
|
|
800879c: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
80087a0: 7af9 ldrb r1, [r7, #11]
|
|
80087a2: 683b ldr r3, [r7, #0]
|
|
80087a4: 687a ldr r2, [r7, #4]
|
|
80087a6: f7fa f825 bl 80027f4 <HAL_PCD_EP_Transmit>
|
|
80087aa: 4603 mov r3, r0
|
|
80087ac: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80087ae: 7dfb ldrb r3, [r7, #23]
|
|
80087b0: 4618 mov r0, r3
|
|
80087b2: f000 f88f bl 80088d4 <USBD_Get_USB_Status>
|
|
80087b6: 4603 mov r3, r0
|
|
80087b8: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
80087ba: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
80087bc: 4618 mov r0, r3
|
|
80087be: 3718 adds r7, #24
|
|
80087c0: 46bd mov sp, r7
|
|
80087c2: bd80 pop {r7, pc}
|
|
|
|
080087c4 <USBD_LL_PrepareReceive>:
|
|
* @param pbuf: Pointer to data to be received
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
|
|
{
|
|
80087c4: b580 push {r7, lr}
|
|
80087c6: b086 sub sp, #24
|
|
80087c8: af00 add r7, sp, #0
|
|
80087ca: 60f8 str r0, [r7, #12]
|
|
80087cc: 607a str r2, [r7, #4]
|
|
80087ce: 603b str r3, [r7, #0]
|
|
80087d0: 460b mov r3, r1
|
|
80087d2: 72fb strb r3, [r7, #11]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80087d4: 2300 movs r3, #0
|
|
80087d6: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80087d8: 2300 movs r3, #0
|
|
80087da: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
|
|
80087dc: 68fb ldr r3, [r7, #12]
|
|
80087de: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
80087e2: 7af9 ldrb r1, [r7, #11]
|
|
80087e4: 683b ldr r3, [r7, #0]
|
|
80087e6: 687a ldr r2, [r7, #4]
|
|
80087e8: f7f9 ffc9 bl 800277e <HAL_PCD_EP_Receive>
|
|
80087ec: 4603 mov r3, r0
|
|
80087ee: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80087f0: 7dfb ldrb r3, [r7, #23]
|
|
80087f2: 4618 mov r0, r3
|
|
80087f4: f000 f86e bl 80088d4 <USBD_Get_USB_Status>
|
|
80087f8: 4603 mov r3, r0
|
|
80087fa: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
80087fc: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
80087fe: 4618 mov r0, r3
|
|
8008800: 3718 adds r7, #24
|
|
8008802: 46bd mov sp, r7
|
|
8008804: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08008808 <HAL_PCDEx_LPM_Callback>:
|
|
* @param hpcd: PCD handle
|
|
* @param msg: LPM message
|
|
* @retval None
|
|
*/
|
|
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
|
|
{
|
|
8008808: b580 push {r7, lr}
|
|
800880a: b082 sub sp, #8
|
|
800880c: af00 add r7, sp, #0
|
|
800880e: 6078 str r0, [r7, #4]
|
|
8008810: 460b mov r3, r1
|
|
8008812: 70fb strb r3, [r7, #3]
|
|
switch (msg)
|
|
8008814: 78fb ldrb r3, [r7, #3]
|
|
8008816: 2b00 cmp r3, #0
|
|
8008818: d002 beq.n 8008820 <HAL_PCDEx_LPM_Callback+0x18>
|
|
800881a: 2b01 cmp r3, #1
|
|
800881c: d01f beq.n 800885e <HAL_PCDEx_LPM_Callback+0x56>
|
|
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
800881e: e03b b.n 8008898 <HAL_PCDEx_LPM_Callback+0x90>
|
|
if (hpcd->Init.low_power_enable)
|
|
8008820: 687b ldr r3, [r7, #4]
|
|
8008822: 7adb ldrb r3, [r3, #11]
|
|
8008824: 2b00 cmp r3, #0
|
|
8008826: d007 beq.n 8008838 <HAL_PCDEx_LPM_Callback+0x30>
|
|
SystemClock_Config();
|
|
8008828: f7f7 fe9e bl 8000568 <SystemClock_Config>
|
|
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
800882c: 4b1c ldr r3, [pc, #112] @ (80088a0 <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800882e: 691b ldr r3, [r3, #16]
|
|
8008830: 4a1b ldr r2, [pc, #108] @ (80088a0 <HAL_PCDEx_LPM_Callback+0x98>)
|
|
8008832: f023 0306 bic.w r3, r3, #6
|
|
8008836: 6113 str r3, [r2, #16]
|
|
__HAL_PCD_UNGATE_PHYCLOCK(hpcd);
|
|
8008838: 687b ldr r3, [r7, #4]
|
|
800883a: 681b ldr r3, [r3, #0]
|
|
800883c: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
8008840: 681b ldr r3, [r3, #0]
|
|
8008842: 687a ldr r2, [r7, #4]
|
|
8008844: 6812 ldr r2, [r2, #0]
|
|
8008846: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
800884a: f023 0301 bic.w r3, r3, #1
|
|
800884e: 6013 str r3, [r2, #0]
|
|
USBD_LL_Resume(hpcd->pData);
|
|
8008850: 687b ldr r3, [r7, #4]
|
|
8008852: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
8008856: 4618 mov r0, r3
|
|
8008858: f7fe fb90 bl 8006f7c <USBD_LL_Resume>
|
|
break;
|
|
800885c: e01c b.n 8008898 <HAL_PCDEx_LPM_Callback+0x90>
|
|
__HAL_PCD_GATE_PHYCLOCK(hpcd);
|
|
800885e: 687b ldr r3, [r7, #4]
|
|
8008860: 681b ldr r3, [r3, #0]
|
|
8008862: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
8008866: 681b ldr r3, [r3, #0]
|
|
8008868: 687a ldr r2, [r7, #4]
|
|
800886a: 6812 ldr r2, [r2, #0]
|
|
800886c: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
8008870: f043 0301 orr.w r3, r3, #1
|
|
8008874: 6013 str r3, [r2, #0]
|
|
USBD_LL_Suspend(hpcd->pData);
|
|
8008876: 687b ldr r3, [r7, #4]
|
|
8008878: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800887c: 4618 mov r0, r3
|
|
800887e: f7fe fb61 bl 8006f44 <USBD_LL_Suspend>
|
|
if (hpcd->Init.low_power_enable)
|
|
8008882: 687b ldr r3, [r7, #4]
|
|
8008884: 7adb ldrb r3, [r3, #11]
|
|
8008886: 2b00 cmp r3, #0
|
|
8008888: d005 beq.n 8008896 <HAL_PCDEx_LPM_Callback+0x8e>
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
800888a: 4b05 ldr r3, [pc, #20] @ (80088a0 <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800888c: 691b ldr r3, [r3, #16]
|
|
800888e: 4a04 ldr r2, [pc, #16] @ (80088a0 <HAL_PCDEx_LPM_Callback+0x98>)
|
|
8008890: f043 0306 orr.w r3, r3, #6
|
|
8008894: 6113 str r3, [r2, #16]
|
|
break;
|
|
8008896: bf00 nop
|
|
}
|
|
8008898: bf00 nop
|
|
800889a: 3708 adds r7, #8
|
|
800889c: 46bd mov sp, r7
|
|
800889e: bd80 pop {r7, pc}
|
|
80088a0: e000ed00 .word 0xe000ed00
|
|
|
|
080088a4 <USBD_static_malloc>:
|
|
* @brief Static single allocation.
|
|
* @param size: Size of allocated memory
|
|
* @retval None
|
|
*/
|
|
void *USBD_static_malloc(uint32_t size)
|
|
{
|
|
80088a4: b480 push {r7}
|
|
80088a6: b083 sub sp, #12
|
|
80088a8: af00 add r7, sp, #0
|
|
80088aa: 6078 str r0, [r7, #4]
|
|
static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */
|
|
return mem;
|
|
80088ac: 4b03 ldr r3, [pc, #12] @ (80088bc <USBD_static_malloc+0x18>)
|
|
}
|
|
80088ae: 4618 mov r0, r3
|
|
80088b0: 370c adds r7, #12
|
|
80088b2: 46bd mov sp, r7
|
|
80088b4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80088b8: 4770 bx lr
|
|
80088ba: bf00 nop
|
|
80088bc: 20000d5c .word 0x20000d5c
|
|
|
|
080088c0 <USBD_static_free>:
|
|
* @brief Dummy memory free
|
|
* @param p: Pointer to allocated memory address
|
|
* @retval None
|
|
*/
|
|
void USBD_static_free(void *p)
|
|
{
|
|
80088c0: b480 push {r7}
|
|
80088c2: b083 sub sp, #12
|
|
80088c4: af00 add r7, sp, #0
|
|
80088c6: 6078 str r0, [r7, #4]
|
|
|
|
}
|
|
80088c8: bf00 nop
|
|
80088ca: 370c adds r7, #12
|
|
80088cc: 46bd mov sp, r7
|
|
80088ce: f85d 7b04 ldr.w r7, [sp], #4
|
|
80088d2: 4770 bx lr
|
|
|
|
080088d4 <USBD_Get_USB_Status>:
|
|
* @brief Returns the USB status depending on the HAL status:
|
|
* @param hal_status: HAL status
|
|
* @retval USB status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
|
|
{
|
|
80088d4: b480 push {r7}
|
|
80088d6: b085 sub sp, #20
|
|
80088d8: af00 add r7, sp, #0
|
|
80088da: 4603 mov r3, r0
|
|
80088dc: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80088de: 2300 movs r3, #0
|
|
80088e0: 73fb strb r3, [r7, #15]
|
|
|
|
switch (hal_status)
|
|
80088e2: 79fb ldrb r3, [r7, #7]
|
|
80088e4: 2b03 cmp r3, #3
|
|
80088e6: d817 bhi.n 8008918 <USBD_Get_USB_Status+0x44>
|
|
80088e8: a201 add r2, pc, #4 @ (adr r2, 80088f0 <USBD_Get_USB_Status+0x1c>)
|
|
80088ea: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80088ee: bf00 nop
|
|
80088f0: 08008901 .word 0x08008901
|
|
80088f4: 08008907 .word 0x08008907
|
|
80088f8: 0800890d .word 0x0800890d
|
|
80088fc: 08008913 .word 0x08008913
|
|
{
|
|
case HAL_OK :
|
|
usb_status = USBD_OK;
|
|
8008900: 2300 movs r3, #0
|
|
8008902: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8008904: e00b b.n 800891e <USBD_Get_USB_Status+0x4a>
|
|
case HAL_ERROR :
|
|
usb_status = USBD_FAIL;
|
|
8008906: 2303 movs r3, #3
|
|
8008908: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800890a: e008 b.n 800891e <USBD_Get_USB_Status+0x4a>
|
|
case HAL_BUSY :
|
|
usb_status = USBD_BUSY;
|
|
800890c: 2301 movs r3, #1
|
|
800890e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8008910: e005 b.n 800891e <USBD_Get_USB_Status+0x4a>
|
|
case HAL_TIMEOUT :
|
|
usb_status = USBD_FAIL;
|
|
8008912: 2303 movs r3, #3
|
|
8008914: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8008916: e002 b.n 800891e <USBD_Get_USB_Status+0x4a>
|
|
default :
|
|
usb_status = USBD_FAIL;
|
|
8008918: 2303 movs r3, #3
|
|
800891a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800891c: bf00 nop
|
|
}
|
|
return usb_status;
|
|
800891e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008920: 4618 mov r0, r3
|
|
8008922: 3714 adds r7, #20
|
|
8008924: 46bd mov sp, r7
|
|
8008926: f85d 7b04 ldr.w r7, [sp], #4
|
|
800892a: 4770 bx lr
|
|
|
|
0800892c <memset>:
|
|
800892c: 4402 add r2, r0
|
|
800892e: 4603 mov r3, r0
|
|
8008930: 4293 cmp r3, r2
|
|
8008932: d100 bne.n 8008936 <memset+0xa>
|
|
8008934: 4770 bx lr
|
|
8008936: f803 1b01 strb.w r1, [r3], #1
|
|
800893a: e7f9 b.n 8008930 <memset+0x4>
|
|
|
|
0800893c <__libc_init_array>:
|
|
800893c: b570 push {r4, r5, r6, lr}
|
|
800893e: 4d0d ldr r5, [pc, #52] @ (8008974 <__libc_init_array+0x38>)
|
|
8008940: 4c0d ldr r4, [pc, #52] @ (8008978 <__libc_init_array+0x3c>)
|
|
8008942: 1b64 subs r4, r4, r5
|
|
8008944: 10a4 asrs r4, r4, #2
|
|
8008946: 2600 movs r6, #0
|
|
8008948: 42a6 cmp r6, r4
|
|
800894a: d109 bne.n 8008960 <__libc_init_array+0x24>
|
|
800894c: 4d0b ldr r5, [pc, #44] @ (800897c <__libc_init_array+0x40>)
|
|
800894e: 4c0c ldr r4, [pc, #48] @ (8008980 <__libc_init_array+0x44>)
|
|
8008950: f000 f818 bl 8008984 <_init>
|
|
8008954: 1b64 subs r4, r4, r5
|
|
8008956: 10a4 asrs r4, r4, #2
|
|
8008958: 2600 movs r6, #0
|
|
800895a: 42a6 cmp r6, r4
|
|
800895c: d105 bne.n 800896a <__libc_init_array+0x2e>
|
|
800895e: bd70 pop {r4, r5, r6, pc}
|
|
8008960: f855 3b04 ldr.w r3, [r5], #4
|
|
8008964: 4798 blx r3
|
|
8008966: 3601 adds r6, #1
|
|
8008968: e7ee b.n 8008948 <__libc_init_array+0xc>
|
|
800896a: f855 3b04 ldr.w r3, [r5], #4
|
|
800896e: 4798 blx r3
|
|
8008970: 3601 adds r6, #1
|
|
8008972: e7f2 b.n 800895a <__libc_init_array+0x1e>
|
|
8008974: 080089f8 .word 0x080089f8
|
|
8008978: 080089f8 .word 0x080089f8
|
|
800897c: 080089f8 .word 0x080089f8
|
|
8008980: 080089fc .word 0x080089fc
|
|
|
|
08008984 <_init>:
|
|
8008984: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8008986: bf00 nop
|
|
8008988: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800898a: bc08 pop {r3}
|
|
800898c: 469e mov lr, r3
|
|
800898e: 4770 bx lr
|
|
|
|
08008990 <_fini>:
|
|
8008990: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8008992: bf00 nop
|
|
8008994: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8008996: bc08 pop {r3}
|
|
8008998: 469e mov lr, r3
|
|
800899a: 4770 bx lr
|