28371 lines
1.0 MiB
28371 lines
1.0 MiB
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modularkbd.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000001c4 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 0000a7f0 080001c4 080001c4 000011c4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 0000005c 0800a9b4 0800a9b4 0000b9b4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 0800aa10 0800aa10 0000c1a0 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 0800aa10 0800aa10 0000ba10 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 0800aa18 0800aa18 0000c1a0 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 0800aa18 0800aa18 0000ba18 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 0800aa1c 0800aa1c 0000ba1c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 000001a0 20000000 0800aa20 0000c000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000f58 200001a0 0800abc0 0000c1a0 2**2
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ALLOC
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10 ._user_heap_stack 00000600 200010f8 0800abc0 0000d0f8 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0000c1a0 2**0
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CONTENTS, READONLY
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12 .debug_info 0001af6f 00000000 00000000 0000c1d0 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00004057 00000000 00000000 0002713f 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00001780 00000000 00000000 0002b198 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 0000123f 00000000 00000000 0002c918 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00026060 00000000 00000000 0002db57 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 0001e655 00000000 00000000 00053bb7 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000d7ebb 00000000 00000000 0007220c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 0014a0c7 2**0
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CONTENTS, READONLY
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20 .debug_frame 000062c0 00000000 00000000 0014a10c 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000062 00000000 00000000 001503cc 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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080001c4 <__do_global_dtors_aux>:
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80001c4: b510 push {r4, lr}
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80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>)
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80001c8: 7823 ldrb r3, [r4, #0]
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80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16>
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80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>)
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80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12>
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80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>)
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80001d2: f3af 8000 nop.w
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80001d6: 2301 movs r3, #1
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80001d8: 7023 strb r3, [r4, #0]
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80001da: bd10 pop {r4, pc}
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80001dc: 200001a0 .word 0x200001a0
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80001e0: 00000000 .word 0x00000000
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80001e4: 0800a99c .word 0x0800a99c
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080001e8 <frame_dummy>:
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80001e8: b508 push {r3, lr}
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80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 <frame_dummy+0x10>)
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80001ec: b11b cbz r3, 80001f6 <frame_dummy+0xe>
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80001ee: 4903 ldr r1, [pc, #12] @ (80001fc <frame_dummy+0x14>)
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80001f0: 4803 ldr r0, [pc, #12] @ (8000200 <frame_dummy+0x18>)
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80001f2: f3af 8000 nop.w
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80001f6: bd08 pop {r3, pc}
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80001f8: 00000000 .word 0x00000000
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80001fc: 200001a4 .word 0x200001a4
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8000200: 0800a99c .word 0x0800a99c
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08000204 <__aeabi_uldivmod>:
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8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18>
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8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18>
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8000208: 2900 cmp r1, #0
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800020a: bf08 it eq
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800020c: 2800 cmpeq r0, #0
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800020e: bf1c itt ne
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8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
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8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
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8000218: f000 b988 b.w 800052c <__aeabi_idiv0>
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800021c: f1ad 0c08 sub.w ip, sp, #8
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8000220: e96d ce04 strd ip, lr, [sp, #-16]!
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8000224: f000 f806 bl 8000234 <__udivmoddi4>
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8000228: f8dd e004 ldr.w lr, [sp, #4]
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800022c: e9dd 2302 ldrd r2, r3, [sp, #8]
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8000230: b004 add sp, #16
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8000232: 4770 bx lr
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08000234 <__udivmoddi4>:
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8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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8000238: 9d08 ldr r5, [sp, #32]
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800023a: 468e mov lr, r1
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800023c: 4604 mov r4, r0
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800023e: 4688 mov r8, r1
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8000240: 2b00 cmp r3, #0
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8000242: d14a bne.n 80002da <__udivmoddi4+0xa6>
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8000244: 428a cmp r2, r1
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8000246: 4617 mov r7, r2
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8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc>
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800024a: fab2 f682 clz r6, r2
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800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30>
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8000250: f1c6 0320 rsb r3, r6, #32
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8000254: fa01 f806 lsl.w r8, r1, r6
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8000258: fa20 f303 lsr.w r3, r0, r3
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800025c: 40b7 lsls r7, r6
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800025e: ea43 0808 orr.w r8, r3, r8
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8000262: 40b4 lsls r4, r6
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8000264: ea4f 4e17 mov.w lr, r7, lsr #16
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8000268: fa1f fc87 uxth.w ip, r7
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800026c: fbb8 f1fe udiv r1, r8, lr
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8000270: 0c23 lsrs r3, r4, #16
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8000272: fb0e 8811 mls r8, lr, r1, r8
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8000276: ea43 4308 orr.w r3, r3, r8, lsl #16
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800027a: fb01 f20c mul.w r2, r1, ip
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800027e: 429a cmp r2, r3
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8000280: d909 bls.n 8000296 <__udivmoddi4+0x62>
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8000282: 18fb adds r3, r7, r3
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8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
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8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c>
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800028c: 429a cmp r2, r3
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800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c>
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8000292: 3902 subs r1, #2
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8000294: 443b add r3, r7
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8000296: 1a9a subs r2, r3, r2
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8000298: b2a3 uxth r3, r4
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800029a: fbb2 f0fe udiv r0, r2, lr
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800029e: fb0e 2210 mls r2, lr, r0, r2
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80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16
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80002a6: fb00 fc0c mul.w ip, r0, ip
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80002aa: 459c cmp ip, r3
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80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e>
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80002ae: 18fb adds r3, r7, r3
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80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
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80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230>
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80002b8: 459c cmp ip, r3
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80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230>
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80002be: 443b add r3, r7
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80002c0: 3802 subs r0, #2
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80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16
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80002c6: eba3 030c sub.w r3, r3, ip
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80002ca: 2100 movs r1, #0
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80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2>
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80002ce: 40f3 lsrs r3, r6
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80002d0: 2200 movs r2, #0
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80002d2: e9c5 3200 strd r3, r2, [r5]
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80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002da: 428b cmp r3, r1
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80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6>
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80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0>
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80002e0: e9c5 0100 strd r0, r1, [r5]
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80002e4: 2100 movs r1, #0
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80002e6: 4608 mov r0, r1
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80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2>
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80002ea: fab3 f183 clz r1, r3
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80002ee: 2900 cmp r1, #0
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80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c>
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80002f2: 4573 cmp r3, lr
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80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8>
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80002f6: 4282 cmp r2, r0
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80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2>
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80002fc: 1a84 subs r4, r0, r2
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80002fe: eb6e 0203 sbc.w r2, lr, r3
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8000302: 2001 movs r0, #1
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8000304: 4690 mov r8, r2
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8000306: 2d00 cmp r5, #0
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8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2>
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800030a: e9c5 4800 strd r4, r8, [r5]
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800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2>
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8000310: 2a00 cmp r2, #0
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8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202>
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8000316: fab2 f682 clz r6, r2
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800031a: 2e00 cmp r6, #0
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800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234>
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8000320: 1a8a subs r2, r1, r2
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8000322: 0c03 lsrs r3, r0, #16
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8000324: ea4f 4e17 mov.w lr, r7, lsr #16
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8000328: b280 uxth r0, r0
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800032a: b2bc uxth r4, r7
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800032c: 2101 movs r1, #1
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800032e: fbb2 fcfe udiv ip, r2, lr
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8000332: fb0e 221c mls r2, lr, ip, r2
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8000336: ea43 4302 orr.w r3, r3, r2, lsl #16
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800033a: fb04 f20c mul.w r2, r4, ip
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800033e: 429a cmp r2, r3
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8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e>
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8000342: 18fb adds r3, r7, r3
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8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
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8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c>
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800034a: 429a cmp r2, r3
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800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc>
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8000350: 46c4 mov ip, r8
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8000352: 1a9b subs r3, r3, r2
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8000354: fbb3 f2fe udiv r2, r3, lr
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8000358: fb0e 3312 mls r3, lr, r2, r3
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800035c: ea40 4303 orr.w r3, r0, r3, lsl #16
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8000360: fb02 f404 mul.w r4, r2, r4
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8000364: 429c cmp r4, r3
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8000366: d907 bls.n 8000378 <__udivmoddi4+0x144>
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8000368: 18fb adds r3, r7, r3
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800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
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800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142>
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8000370: 429c cmp r4, r3
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8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6>
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8000376: 4602 mov r2, r0
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8000378: 1b1b subs r3, r3, r4
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800037a: ea42 400c orr.w r0, r2, ip, lsl #16
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800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98>
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8000380: f1c1 0620 rsb r6, r1, #32
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8000384: 408b lsls r3, r1
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8000386: fa22 f706 lsr.w r7, r2, r6
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800038a: 431f orrs r7, r3
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800038c: fa0e f401 lsl.w r4, lr, r1
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8000390: fa20 f306 lsr.w r3, r0, r6
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8000394: fa2e fe06 lsr.w lr, lr, r6
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8000398: ea4f 4917 mov.w r9, r7, lsr #16
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800039c: 4323 orrs r3, r4
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800039e: fa00 f801 lsl.w r8, r0, r1
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80003a2: fa1f fc87 uxth.w ip, r7
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80003a6: fbbe f0f9 udiv r0, lr, r9
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80003aa: 0c1c lsrs r4, r3, #16
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80003ac: fb09 ee10 mls lr, r9, r0, lr
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80003b0: ea44 440e orr.w r4, r4, lr, lsl #16
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80003b4: fb00 fe0c mul.w lr, r0, ip
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80003b8: 45a6 cmp lr, r4
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80003ba: fa02 f201 lsl.w r2, r2, r1
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80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0>
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80003c0: 193c adds r4, r7, r4
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80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
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80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce>
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80003ca: 45a6 cmp lr, r4
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80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce>
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80003d0: 3802 subs r0, #2
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80003d2: 443c add r4, r7
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80003d4: eba4 040e sub.w r4, r4, lr
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80003d8: fa1f fe83 uxth.w lr, r3
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80003dc: fbb4 f3f9 udiv r3, r4, r9
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80003e0: fb09 4413 mls r4, r9, r3, r4
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80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16
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80003e8: fb03 fc0c mul.w ip, r3, ip
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80003ec: 45a4 cmp ip, r4
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80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce>
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80003f0: 193c adds r4, r7, r4
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80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
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80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca>
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80003fa: 45a4 cmp ip, r4
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80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca>
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80003fe: 3b02 subs r3, #2
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8000400: 443c add r4, r7
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8000402: ea43 4000 orr.w r0, r3, r0, lsl #16
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8000406: eba4 040c sub.w r4, r4, ip
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800040a: fba0 ec02 umull lr, ip, r0, r2
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800040e: 4564 cmp r4, ip
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8000410: 4673 mov r3, lr
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8000412: 46e1 mov r9, ip
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8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8>
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8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4>
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8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe>
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800041a: ebb8 0203 subs.w r2, r8, r3
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800041e: eb64 0409 sbc.w r4, r4, r9
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8000422: fa04 f606 lsl.w r6, r4, r6
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8000426: fa22 f301 lsr.w r3, r2, r1
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800042a: 431e orrs r6, r3
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800042c: 40cc lsrs r4, r1
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800042e: e9c5 6400 strd r6, r4, [r5]
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8000432: 2100 movs r1, #0
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8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2>
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8000436: fbb1 fcf2 udiv ip, r1, r2
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800043a: 0c01 lsrs r1, r0, #16
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800043c: ea41 410e orr.w r1, r1, lr, lsl #16
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8000440: b280 uxth r0, r0
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8000442: ea40 4201 orr.w r2, r0, r1, lsl #16
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8000446: 463b mov r3, r7
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8000448: 4638 mov r0, r7
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800044a: 463c mov r4, r7
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800044c: 46b8 mov r8, r7
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800044e: 46be mov lr, r7
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8000450: 2620 movs r6, #32
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8000452: fbb1 f1f7 udiv r1, r1, r7
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8000456: eba2 0208 sub.w r2, r2, r8
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800045a: ea41 410c orr.w r1, r1, ip, lsl #16
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800045e: e766 b.n 800032e <__udivmoddi4+0xfa>
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8000460: 4601 mov r1, r0
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8000462: e718 b.n 8000296 <__udivmoddi4+0x62>
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8000464: 4610 mov r0, r2
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8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e>
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8000468: f1c6 0220 rsb r2, r6, #32
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800046c: fa2e f302 lsr.w r3, lr, r2
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8000470: 40b7 lsls r7, r6
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8000472: 40b1 lsls r1, r6
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8000474: fa20 f202 lsr.w r2, r0, r2
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8000478: ea4f 4e17 mov.w lr, r7, lsr #16
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800047c: 430a orrs r2, r1
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800047e: fbb3 f8fe udiv r8, r3, lr
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8000482: b2bc uxth r4, r7
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8000484: fb0e 3318 mls r3, lr, r8, r3
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8000488: 0c11 lsrs r1, r2, #16
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800048a: ea41 4103 orr.w r1, r1, r3, lsl #16
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800048e: fb08 f904 mul.w r9, r8, r4
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8000492: 40b0 lsls r0, r6
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8000494: 4589 cmp r9, r1
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8000496: ea4f 4310 mov.w r3, r0, lsr #16
|
|
800049a: b280 uxth r0, r0
|
|
800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8>
|
|
800049e: 1879 adds r1, r7, r1
|
|
80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276>
|
|
80004a6: 4589 cmp r9, r1
|
|
80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6>
|
|
80004aa: eba1 0109 sub.w r1, r1, r9
|
|
80004ae: fbb1 f9fe udiv r9, r1, lr
|
|
80004b2: fb09 f804 mul.w r8, r9, r4
|
|
80004b6: fb0e 1119 mls r1, lr, r9, r1
|
|
80004ba: b292 uxth r2, r2
|
|
80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
80004c0: 4542 cmp r2, r8
|
|
80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4>
|
|
80004c4: 18ba adds r2, r7, r2
|
|
80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222>
|
|
80004cc: 4542 cmp r2, r8
|
|
80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222>
|
|
80004d0: f1a9 0102 sub.w r1, r9, #2
|
|
80004d4: 443a add r2, r7
|
|
80004d6: e7be b.n 8000456 <__udivmoddi4+0x222>
|
|
80004d8: 45f0 cmp r8, lr
|
|
80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4>
|
|
80004dc: ebbe 0302 subs.w r3, lr, r2
|
|
80004e0: eb6c 0c07 sbc.w ip, ip, r7
|
|
80004e4: 3801 subs r0, #1
|
|
80004e6: 46e1 mov r9, ip
|
|
80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4>
|
|
80004ea: eba7 0909 sub.w r9, r7, r9
|
|
80004ee: 4449 add r1, r9
|
|
80004f0: f1a8 0c02 sub.w ip, r8, #2
|
|
80004f4: fbb1 f9fe udiv r9, r1, lr
|
|
80004f8: fb09 f804 mul.w r8, r9, r4
|
|
80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282>
|
|
80004fe: 4673 mov r3, lr
|
|
8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce>
|
|
8000502: 4650 mov r0, sl
|
|
8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0>
|
|
8000506: 4608 mov r0, r1
|
|
8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2>
|
|
800050a: 443b add r3, r7
|
|
800050c: 3a02 subs r2, #2
|
|
800050e: e733 b.n 8000378 <__udivmoddi4+0x144>
|
|
8000510: f1ac 0c02 sub.w ip, ip, #2
|
|
8000514: 443b add r3, r7
|
|
8000516: e71c b.n 8000352 <__udivmoddi4+0x11e>
|
|
8000518: 4649 mov r1, r9
|
|
800051a: e79c b.n 8000456 <__udivmoddi4+0x222>
|
|
800051c: eba1 0109 sub.w r1, r1, r9
|
|
8000520: 46c4 mov ip, r8
|
|
8000522: fbb1 f9fe udiv r9, r1, lr
|
|
8000526: fb09 f804 mul.w r8, r9, r4
|
|
800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282>
|
|
|
|
0800052c <__aeabi_idiv0>:
|
|
800052c: 4770 bx lr
|
|
800052e: bf00 nop
|
|
|
|
08000530 <MX_DMA_Init>:
|
|
|
|
/**
|
|
* Enable DMA controller clock
|
|
*/
|
|
void MX_DMA_Init(void)
|
|
{
|
|
8000530: b580 push {r7, lr}
|
|
8000532: b082 sub sp, #8
|
|
8000534: af00 add r7, sp, #0
|
|
|
|
/* DMA controller clock enable */
|
|
__HAL_RCC_DMA1_CLK_ENABLE();
|
|
8000536: 2300 movs r3, #0
|
|
8000538: 607b str r3, [r7, #4]
|
|
800053a: 4b2f ldr r3, [pc, #188] @ (80005f8 <MX_DMA_Init+0xc8>)
|
|
800053c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800053e: 4a2e ldr r2, [pc, #184] @ (80005f8 <MX_DMA_Init+0xc8>)
|
|
8000540: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8000544: 6313 str r3, [r2, #48] @ 0x30
|
|
8000546: 4b2c ldr r3, [pc, #176] @ (80005f8 <MX_DMA_Init+0xc8>)
|
|
8000548: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800054a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
800054e: 607b str r3, [r7, #4]
|
|
8000550: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_DMA2_CLK_ENABLE();
|
|
8000552: 2300 movs r3, #0
|
|
8000554: 603b str r3, [r7, #0]
|
|
8000556: 4b28 ldr r3, [pc, #160] @ (80005f8 <MX_DMA_Init+0xc8>)
|
|
8000558: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800055a: 4a27 ldr r2, [pc, #156] @ (80005f8 <MX_DMA_Init+0xc8>)
|
|
800055c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8000560: 6313 str r3, [r2, #48] @ 0x30
|
|
8000562: 4b25 ldr r3, [pc, #148] @ (80005f8 <MX_DMA_Init+0xc8>)
|
|
8000564: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000566: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
800056a: 603b str r3, [r7, #0]
|
|
800056c: 683b ldr r3, [r7, #0]
|
|
|
|
/* DMA interrupt init */
|
|
/* DMA1_Stream0_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);
|
|
800056e: 2200 movs r2, #0
|
|
8000570: 2100 movs r1, #0
|
|
8000572: 200b movs r0, #11
|
|
8000574: f001 fb5b bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
|
|
8000578: 200b movs r0, #11
|
|
800057a: f001 fb74 bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream2_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0);
|
|
800057e: 2200 movs r2, #0
|
|
8000580: 2100 movs r1, #0
|
|
8000582: 200d movs r0, #13
|
|
8000584: f001 fb53 bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
|
|
8000588: 200d movs r0, #13
|
|
800058a: f001 fb6c bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream4_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0);
|
|
800058e: 2200 movs r2, #0
|
|
8000590: 2100 movs r1, #0
|
|
8000592: 200f movs r0, #15
|
|
8000594: f001 fb4b bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);
|
|
8000598: 200f movs r0, #15
|
|
800059a: f001 fb64 bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream5_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0);
|
|
800059e: 2200 movs r2, #0
|
|
80005a0: 2100 movs r1, #0
|
|
80005a2: 2010 movs r0, #16
|
|
80005a4: f001 fb43 bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
|
|
80005a8: 2010 movs r0, #16
|
|
80005aa: f001 fb5c bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream6_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0);
|
|
80005ae: 2200 movs r2, #0
|
|
80005b0: 2100 movs r1, #0
|
|
80005b2: 2011 movs r0, #17
|
|
80005b4: f001 fb3b bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn);
|
|
80005b8: 2011 movs r0, #17
|
|
80005ba: f001 fb54 bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Stream7_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0);
|
|
80005be: 2200 movs r2, #0
|
|
80005c0: 2100 movs r1, #0
|
|
80005c2: 202f movs r0, #47 @ 0x2f
|
|
80005c4: f001 fb33 bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);
|
|
80005c8: 202f movs r0, #47 @ 0x2f
|
|
80005ca: f001 fb4c bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
/* DMA2_Stream2_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0);
|
|
80005ce: 2200 movs r2, #0
|
|
80005d0: 2100 movs r1, #0
|
|
80005d2: 203a movs r0, #58 @ 0x3a
|
|
80005d4: f001 fb2b bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
|
|
80005d8: 203a movs r0, #58 @ 0x3a
|
|
80005da: f001 fb44 bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
/* DMA2_Stream7_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0);
|
|
80005de: 2200 movs r2, #0
|
|
80005e0: 2100 movs r1, #0
|
|
80005e2: 2046 movs r0, #70 @ 0x46
|
|
80005e4: f001 fb23 bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
|
|
80005e8: 2046 movs r0, #70 @ 0x46
|
|
80005ea: f001 fb3c bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
|
|
}
|
|
80005ee: bf00 nop
|
|
80005f0: 3708 adds r7, #8
|
|
80005f2: 46bd mov sp, r7
|
|
80005f4: bd80 pop {r7, pc}
|
|
80005f6: bf00 nop
|
|
80005f8: 40023800 .word 0x40023800
|
|
|
|
080005fc <MX_GPIO_Init>:
|
|
* Output
|
|
* EVENT_OUT
|
|
* EXTI
|
|
*/
|
|
void MX_GPIO_Init(void)
|
|
{
|
|
80005fc: b580 push {r7, lr}
|
|
80005fe: b08a sub sp, #40 @ 0x28
|
|
8000600: af00 add r7, sp, #0
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000602: f107 0314 add.w r3, r7, #20
|
|
8000606: 2200 movs r2, #0
|
|
8000608: 601a str r2, [r3, #0]
|
|
800060a: 605a str r2, [r3, #4]
|
|
800060c: 609a str r2, [r3, #8]
|
|
800060e: 60da str r2, [r3, #12]
|
|
8000610: 611a str r2, [r3, #16]
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
8000612: 2300 movs r3, #0
|
|
8000614: 613b str r3, [r7, #16]
|
|
8000616: 4b45 ldr r3, [pc, #276] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000618: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800061a: 4a44 ldr r2, [pc, #272] @ (800072c <MX_GPIO_Init+0x130>)
|
|
800061c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8000620: 6313 str r3, [r2, #48] @ 0x30
|
|
8000622: 4b42 ldr r3, [pc, #264] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000624: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000626: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800062a: 613b str r3, [r7, #16]
|
|
800062c: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800062e: 2300 movs r3, #0
|
|
8000630: 60fb str r3, [r7, #12]
|
|
8000632: 4b3e ldr r3, [pc, #248] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000634: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000636: 4a3d ldr r2, [pc, #244] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000638: f043 0301 orr.w r3, r3, #1
|
|
800063c: 6313 str r3, [r2, #48] @ 0x30
|
|
800063e: 4b3b ldr r3, [pc, #236] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000640: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000642: f003 0301 and.w r3, r3, #1
|
|
8000646: 60fb str r3, [r7, #12]
|
|
8000648: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
800064a: 2300 movs r3, #0
|
|
800064c: 60bb str r3, [r7, #8]
|
|
800064e: 4b37 ldr r3, [pc, #220] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000650: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000652: 4a36 ldr r2, [pc, #216] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000654: f043 0304 orr.w r3, r3, #4
|
|
8000658: 6313 str r3, [r2, #48] @ 0x30
|
|
800065a: 4b34 ldr r3, [pc, #208] @ (800072c <MX_GPIO_Init+0x130>)
|
|
800065c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800065e: f003 0304 and.w r3, r3, #4
|
|
8000662: 60bb str r3, [r7, #8]
|
|
8000664: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000666: 2300 movs r3, #0
|
|
8000668: 607b str r3, [r7, #4]
|
|
800066a: 4b30 ldr r3, [pc, #192] @ (800072c <MX_GPIO_Init+0x130>)
|
|
800066c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800066e: 4a2f ldr r2, [pc, #188] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000670: f043 0302 orr.w r3, r3, #2
|
|
8000674: 6313 str r3, [r2, #48] @ 0x30
|
|
8000676: 4b2d ldr r3, [pc, #180] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000678: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800067a: f003 0302 and.w r3, r3, #2
|
|
800067e: 607b str r3, [r7, #4]
|
|
8000680: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8000682: 2300 movs r3, #0
|
|
8000684: 603b str r3, [r7, #0]
|
|
8000686: 4b29 ldr r3, [pc, #164] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000688: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800068a: 4a28 ldr r2, [pc, #160] @ (800072c <MX_GPIO_Init+0x130>)
|
|
800068c: f043 0308 orr.w r3, r3, #8
|
|
8000690: 6313 str r3, [r2, #48] @ 0x30
|
|
8000692: 4b26 ldr r3, [pc, #152] @ (800072c <MX_GPIO_Init+0x130>)
|
|
8000694: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000696: f003 0308 and.w r3, r3, #8
|
|
800069a: 603b str r3, [r7, #0]
|
|
800069c: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET);
|
|
800069e: 2200 movs r2, #0
|
|
80006a0: f44f 7170 mov.w r1, #960 @ 0x3c0
|
|
80006a4: 4822 ldr r0, [pc, #136] @ (8000730 <MX_GPIO_Init+0x134>)
|
|
80006a6: f002 f8a7 bl 80027f8 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET);
|
|
80006aa: 2200 movs r2, #0
|
|
80006ac: f44f 7180 mov.w r1, #256 @ 0x100
|
|
80006b0: 4820 ldr r0, [pc, #128] @ (8000734 <MX_GPIO_Init+0x138>)
|
|
80006b2: f002 f8a1 bl 80027f8 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : PC4 PC5 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
|
|
80006b6: 2330 movs r3, #48 @ 0x30
|
|
80006b8: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
80006ba: 2300 movs r3, #0
|
|
80006bc: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
80006be: 2302 movs r3, #2
|
|
80006c0: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80006c2: f107 0314 add.w r3, r7, #20
|
|
80006c6: 4619 mov r1, r3
|
|
80006c8: 4819 ldr r0, [pc, #100] @ (8000730 <MX_GPIO_Init+0x134>)
|
|
80006ca: f001 fee9 bl 80024a0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PB0 PB1 PB2 PB10 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10;
|
|
80006ce: f240 4307 movw r3, #1031 @ 0x407
|
|
80006d2: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
80006d4: 2300 movs r3, #0
|
|
80006d6: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
|
80006d8: 2302 movs r3, #2
|
|
80006da: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80006dc: f107 0314 add.w r3, r7, #20
|
|
80006e0: 4619 mov r1, r3
|
|
80006e2: 4815 ldr r0, [pc, #84] @ (8000738 <MX_GPIO_Init+0x13c>)
|
|
80006e4: f001 fedc bl 80024a0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : PC6 PC7 PC8 PC9 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9;
|
|
80006e8: f44f 7370 mov.w r3, #960 @ 0x3c0
|
|
80006ec: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80006ee: 2301 movs r3, #1
|
|
80006f0: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80006f2: 2300 movs r3, #0
|
|
80006f4: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80006f6: 2300 movs r3, #0
|
|
80006f8: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80006fa: f107 0314 add.w r3, r7, #20
|
|
80006fe: 4619 mov r1, r3
|
|
8000700: 480b ldr r0, [pc, #44] @ (8000730 <MX_GPIO_Init+0x134>)
|
|
8000702: f001 fecd bl 80024a0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : PA8 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_8;
|
|
8000706: f44f 7380 mov.w r3, #256 @ 0x100
|
|
800070a: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
800070c: 2301 movs r3, #1
|
|
800070e: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000710: 2300 movs r3, #0
|
|
8000712: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000714: 2300 movs r3, #0
|
|
8000716: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000718: f107 0314 add.w r3, r7, #20
|
|
800071c: 4619 mov r1, r3
|
|
800071e: 4805 ldr r0, [pc, #20] @ (8000734 <MX_GPIO_Init+0x138>)
|
|
8000720: f001 febe bl 80024a0 <HAL_GPIO_Init>
|
|
|
|
}
|
|
8000724: bf00 nop
|
|
8000726: 3728 adds r7, #40 @ 0x28
|
|
8000728: 46bd mov sp, r7
|
|
800072a: bd80 pop {r7, pc}
|
|
800072c: 40023800 .word 0x40023800
|
|
8000730: 40020800 .word 0x40020800
|
|
8000734: 40020000 .word 0x40020000
|
|
8000738: 40020400 .word 0x40020400
|
|
|
|
0800073c <MX_I2C1_Init>:
|
|
|
|
I2C_HandleTypeDef hi2c1;
|
|
|
|
/* I2C1 init function */
|
|
void MX_I2C1_Init(void)
|
|
{
|
|
800073c: b580 push {r7, lr}
|
|
800073e: af00 add r7, sp, #0
|
|
/* USER CODE END I2C1_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C1_Init 1 */
|
|
|
|
/* USER CODE END I2C1_Init 1 */
|
|
hi2c1.Instance = I2C1;
|
|
8000740: 4b12 ldr r3, [pc, #72] @ (800078c <MX_I2C1_Init+0x50>)
|
|
8000742: 4a13 ldr r2, [pc, #76] @ (8000790 <MX_I2C1_Init+0x54>)
|
|
8000744: 601a str r2, [r3, #0]
|
|
hi2c1.Init.ClockSpeed = 100000;
|
|
8000746: 4b11 ldr r3, [pc, #68] @ (800078c <MX_I2C1_Init+0x50>)
|
|
8000748: 4a12 ldr r2, [pc, #72] @ (8000794 <MX_I2C1_Init+0x58>)
|
|
800074a: 605a str r2, [r3, #4]
|
|
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
|
|
800074c: 4b0f ldr r3, [pc, #60] @ (800078c <MX_I2C1_Init+0x50>)
|
|
800074e: 2200 movs r2, #0
|
|
8000750: 609a str r2, [r3, #8]
|
|
hi2c1.Init.OwnAddress1 = 0;
|
|
8000752: 4b0e ldr r3, [pc, #56] @ (800078c <MX_I2C1_Init+0x50>)
|
|
8000754: 2200 movs r2, #0
|
|
8000756: 60da str r2, [r3, #12]
|
|
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
8000758: 4b0c ldr r3, [pc, #48] @ (800078c <MX_I2C1_Init+0x50>)
|
|
800075a: f44f 4280 mov.w r2, #16384 @ 0x4000
|
|
800075e: 611a str r2, [r3, #16]
|
|
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8000760: 4b0a ldr r3, [pc, #40] @ (800078c <MX_I2C1_Init+0x50>)
|
|
8000762: 2200 movs r2, #0
|
|
8000764: 615a str r2, [r3, #20]
|
|
hi2c1.Init.OwnAddress2 = 0;
|
|
8000766: 4b09 ldr r3, [pc, #36] @ (800078c <MX_I2C1_Init+0x50>)
|
|
8000768: 2200 movs r2, #0
|
|
800076a: 619a str r2, [r3, #24]
|
|
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
800076c: 4b07 ldr r3, [pc, #28] @ (800078c <MX_I2C1_Init+0x50>)
|
|
800076e: 2200 movs r2, #0
|
|
8000770: 61da str r2, [r3, #28]
|
|
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8000772: 4b06 ldr r3, [pc, #24] @ (800078c <MX_I2C1_Init+0x50>)
|
|
8000774: 2200 movs r2, #0
|
|
8000776: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
|
|
8000778: 4804 ldr r0, [pc, #16] @ (800078c <MX_I2C1_Init+0x50>)
|
|
800077a: f002 f857 bl 800282c <HAL_I2C_Init>
|
|
800077e: 4603 mov r3, r0
|
|
8000780: 2b00 cmp r3, #0
|
|
8000782: d001 beq.n 8000788 <MX_I2C1_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8000784: f000 fb10 bl 8000da8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C1_Init 2 */
|
|
|
|
/* USER CODE END I2C1_Init 2 */
|
|
|
|
}
|
|
8000788: bf00 nop
|
|
800078a: bd80 pop {r7, pc}
|
|
800078c: 200001bc .word 0x200001bc
|
|
8000790: 40005400 .word 0x40005400
|
|
8000794: 000186a0 .word 0x000186a0
|
|
|
|
08000798 <HAL_I2C_MspInit>:
|
|
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
|
|
{
|
|
8000798: b580 push {r7, lr}
|
|
800079a: b08a sub sp, #40 @ 0x28
|
|
800079c: af00 add r7, sp, #0
|
|
800079e: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80007a0: f107 0314 add.w r3, r7, #20
|
|
80007a4: 2200 movs r2, #0
|
|
80007a6: 601a str r2, [r3, #0]
|
|
80007a8: 605a str r2, [r3, #4]
|
|
80007aa: 609a str r2, [r3, #8]
|
|
80007ac: 60da str r2, [r3, #12]
|
|
80007ae: 611a str r2, [r3, #16]
|
|
if(i2cHandle->Instance==I2C1)
|
|
80007b0: 687b ldr r3, [r7, #4]
|
|
80007b2: 681b ldr r3, [r3, #0]
|
|
80007b4: 4a19 ldr r2, [pc, #100] @ (800081c <HAL_I2C_MspInit+0x84>)
|
|
80007b6: 4293 cmp r3, r2
|
|
80007b8: d12b bne.n 8000812 <HAL_I2C_MspInit+0x7a>
|
|
{
|
|
/* USER CODE BEGIN I2C1_MspInit 0 */
|
|
|
|
/* USER CODE END I2C1_MspInit 0 */
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80007ba: 2300 movs r3, #0
|
|
80007bc: 613b str r3, [r7, #16]
|
|
80007be: 4b18 ldr r3, [pc, #96] @ (8000820 <HAL_I2C_MspInit+0x88>)
|
|
80007c0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80007c2: 4a17 ldr r2, [pc, #92] @ (8000820 <HAL_I2C_MspInit+0x88>)
|
|
80007c4: f043 0302 orr.w r3, r3, #2
|
|
80007c8: 6313 str r3, [r2, #48] @ 0x30
|
|
80007ca: 4b15 ldr r3, [pc, #84] @ (8000820 <HAL_I2C_MspInit+0x88>)
|
|
80007cc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80007ce: f003 0302 and.w r3, r3, #2
|
|
80007d2: 613b str r3, [r7, #16]
|
|
80007d4: 693b ldr r3, [r7, #16]
|
|
/**I2C1 GPIO Configuration
|
|
PB6 ------> I2C1_SCL
|
|
PB7 ------> I2C1_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
80007d6: 23c0 movs r3, #192 @ 0xc0
|
|
80007d8: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
80007da: 2312 movs r3, #18
|
|
80007dc: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80007de: 2300 movs r3, #0
|
|
80007e0: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80007e2: 2303 movs r3, #3
|
|
80007e4: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
|
|
80007e6: 2304 movs r3, #4
|
|
80007e8: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80007ea: f107 0314 add.w r3, r7, #20
|
|
80007ee: 4619 mov r1, r3
|
|
80007f0: 480c ldr r0, [pc, #48] @ (8000824 <HAL_I2C_MspInit+0x8c>)
|
|
80007f2: f001 fe55 bl 80024a0 <HAL_GPIO_Init>
|
|
|
|
/* I2C1 clock enable */
|
|
__HAL_RCC_I2C1_CLK_ENABLE();
|
|
80007f6: 2300 movs r3, #0
|
|
80007f8: 60fb str r3, [r7, #12]
|
|
80007fa: 4b09 ldr r3, [pc, #36] @ (8000820 <HAL_I2C_MspInit+0x88>)
|
|
80007fc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80007fe: 4a08 ldr r2, [pc, #32] @ (8000820 <HAL_I2C_MspInit+0x88>)
|
|
8000800: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8000804: 6413 str r3, [r2, #64] @ 0x40
|
|
8000806: 4b06 ldr r3, [pc, #24] @ (8000820 <HAL_I2C_MspInit+0x88>)
|
|
8000808: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800080a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
800080e: 60fb str r3, [r7, #12]
|
|
8000810: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN I2C1_MspInit 1 */
|
|
|
|
/* USER CODE END I2C1_MspInit 1 */
|
|
}
|
|
}
|
|
8000812: bf00 nop
|
|
8000814: 3728 adds r7, #40 @ 0x28
|
|
8000816: 46bd mov sp, r7
|
|
8000818: bd80 pop {r7, pc}
|
|
800081a: bf00 nop
|
|
800081c: 40005400 .word 0x40005400
|
|
8000820: 40023800 .word 0x40023800
|
|
8000824: 40020400 .word 0x40020400
|
|
|
|
08000828 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8000828: b580 push {r7, lr}
|
|
800082a: b088 sub sp, #32
|
|
800082c: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
800082e: f001 f88d bl 800194c <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8000832: f000 f8af bl 8000994 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8000836: f7ff fee1 bl 80005fc <MX_GPIO_Init>
|
|
MX_DMA_Init();
|
|
800083a: f7ff fe79 bl 8000530 <MX_DMA_Init>
|
|
MX_TIM2_Init();
|
|
800083e: f000 fba5 bl 8000f8c <MX_TIM2_Init>
|
|
MX_TIM3_Init();
|
|
8000842: f000 fbfb bl 800103c <MX_TIM3_Init>
|
|
MX_UART4_Init();
|
|
8000846: f000 fced bl 8001224 <MX_UART4_Init>
|
|
MX_UART5_Init();
|
|
800084a: f000 fd15 bl 8001278 <MX_UART5_Init>
|
|
MX_USART1_UART_Init();
|
|
800084e: f000 fd3d bl 80012cc <MX_USART1_UART_Init>
|
|
MX_USART2_UART_Init();
|
|
8000852: f000 fd65 bl 8001320 <MX_USART2_UART_Init>
|
|
MX_I2C1_Init();
|
|
8000856: f7ff ff71 bl 800073c <MX_I2C1_Init>
|
|
MX_USB_DEVICE_Init();
|
|
800085a: f009 fbb7 bl 8009fcc <MX_USB_DEVICE_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
|
|
//Enable UART RX DMA for all ports
|
|
HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage));
|
|
800085e: 2210 movs r2, #16
|
|
8000860: 493f ldr r1, [pc, #252] @ (8000960 <main+0x138>)
|
|
8000862: 4840 ldr r0, [pc, #256] @ (8000964 <main+0x13c>)
|
|
8000864: f005 f9ae bl 8005bc4 <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage));
|
|
8000868: 2210 movs r2, #16
|
|
800086a: 493f ldr r1, [pc, #252] @ (8000968 <main+0x140>)
|
|
800086c: 483f ldr r0, [pc, #252] @ (800096c <main+0x144>)
|
|
800086e: f005 f9a9 bl 8005bc4 <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage));
|
|
8000872: 2210 movs r2, #16
|
|
8000874: 493e ldr r1, [pc, #248] @ (8000970 <main+0x148>)
|
|
8000876: 483f ldr r0, [pc, #252] @ (8000974 <main+0x14c>)
|
|
8000878: f005 f9a4 bl 8005bc4 <HAL_UART_Receive_DMA>
|
|
HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage));
|
|
800087c: 2210 movs r2, #16
|
|
800087e: 493e ldr r1, [pc, #248] @ (8000978 <main+0x150>)
|
|
8000880: 483e ldr r0, [pc, #248] @ (800097c <main+0x154>)
|
|
8000882: f005 f99f bl 8005bc4 <HAL_UART_Receive_DMA>
|
|
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
switch (MODE){
|
|
8000886: 4b3e ldr r3, [pc, #248] @ (8000980 <main+0x158>)
|
|
8000888: 781b ldrb r3, [r3, #0]
|
|
800088a: b2db uxtb r3, r3
|
|
800088c: 2b02 cmp r3, #2
|
|
800088e: d006 beq.n 800089e <main+0x76>
|
|
8000890: 2b02 cmp r3, #2
|
|
8000892: dc5f bgt.n 8000954 <main+0x12c>
|
|
8000894: 2b00 cmp r3, #0
|
|
8000896: d01c beq.n 80008d2 <main+0xaa>
|
|
8000898: 2b01 cmp r3, #1
|
|
800089a: d051 beq.n 8000940 <main+0x118>
|
|
matrixScan();
|
|
USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT));
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
800089c: e05a b.n 8000954 <main+0x12c>
|
|
resetReport();
|
|
800089e: f000 fa73 bl 8000d88 <resetReport>
|
|
matrixScan();
|
|
80008a2: f000 fa17 bl 8000cd4 <matrixScan>
|
|
UARTREPORT.DEPTH = DEPTH;
|
|
80008a6: 4b37 ldr r3, [pc, #220] @ (8000984 <main+0x15c>)
|
|
80008a8: 881b ldrh r3, [r3, #0]
|
|
80008aa: 823b strh r3, [r7, #16]
|
|
UARTREPORT.TYPE = 0xEE;
|
|
80008ac: 23ee movs r3, #238 @ 0xee
|
|
80008ae: 827b strh r3, [r7, #18]
|
|
memset(UARTREPORT.KEYPRESS, 1, sizeof(UARTREPORT.KEYPRESS));
|
|
80008b0: f107 0310 add.w r3, r7, #16
|
|
80008b4: 3304 adds r3, #4
|
|
80008b6: 220c movs r2, #12
|
|
80008b8: 2101 movs r1, #1
|
|
80008ba: 4618 mov r0, r3
|
|
80008bc: f00a f834 bl 800a928 <memset>
|
|
HAL_UART_Transmit_DMA(PARENT, (uint8_t*)&UARTREPORT, sizeof(UARTREPORT));
|
|
80008c0: 4b31 ldr r3, [pc, #196] @ (8000988 <main+0x160>)
|
|
80008c2: 681b ldr r3, [r3, #0]
|
|
80008c4: f107 0110 add.w r1, r7, #16
|
|
80008c8: 2210 movs r2, #16
|
|
80008ca: 4618 mov r0, r3
|
|
80008cc: f005 f8fe bl 8005acc <HAL_UART_Transmit_DMA>
|
|
break;
|
|
80008d0: e041 b.n 8000956 <main+0x12e>
|
|
if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){
|
|
80008d2: 4b2e ldr r3, [pc, #184] @ (800098c <main+0x164>)
|
|
80008d4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80008d8: b2db uxtb r3, r3
|
|
80008da: 2b03 cmp r3, #3
|
|
80008dc: d106 bne.n 80008ec <main+0xc4>
|
|
MODE = MODE_MAINBOARD;
|
|
80008de: 4b28 ldr r3, [pc, #160] @ (8000980 <main+0x158>)
|
|
80008e0: 2201 movs r2, #1
|
|
80008e2: 701a strb r2, [r3, #0]
|
|
DEPTH = 0;
|
|
80008e4: 4b27 ldr r3, [pc, #156] @ (8000984 <main+0x15c>)
|
|
80008e6: 2200 movs r2, #0
|
|
80008e8: 801a strh r2, [r3, #0]
|
|
break;
|
|
80008ea: e034 b.n 8000956 <main+0x12e>
|
|
REQ.DEPTH = 0;
|
|
80008ec: 2300 movs r3, #0
|
|
80008ee: 803b strh r3, [r7, #0]
|
|
REQ.TYPE = 0xFF; //Message code for request is 0xFF
|
|
80008f0: 23ff movs r3, #255 @ 0xff
|
|
80008f2: 807b strh r3, [r7, #2]
|
|
memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS));
|
|
80008f4: 463b mov r3, r7
|
|
80008f6: 3304 adds r3, #4
|
|
80008f8: 220c movs r2, #12
|
|
80008fa: 2100 movs r1, #0
|
|
80008fc: 4618 mov r0, r3
|
|
80008fe: f00a f813 bl 800a928 <memset>
|
|
HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ));
|
|
8000902: 463b mov r3, r7
|
|
8000904: 2210 movs r2, #16
|
|
8000906: 4619 mov r1, r3
|
|
8000908: 4816 ldr r0, [pc, #88] @ (8000964 <main+0x13c>)
|
|
800090a: f005 f8df bl 8005acc <HAL_UART_Transmit_DMA>
|
|
HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ));
|
|
800090e: 463b mov r3, r7
|
|
8000910: 2210 movs r2, #16
|
|
8000912: 4619 mov r1, r3
|
|
8000914: 4815 ldr r0, [pc, #84] @ (800096c <main+0x144>)
|
|
8000916: f005 f8d9 bl 8005acc <HAL_UART_Transmit_DMA>
|
|
HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ));
|
|
800091a: 463b mov r3, r7
|
|
800091c: 2210 movs r2, #16
|
|
800091e: 4619 mov r1, r3
|
|
8000920: 4814 ldr r0, [pc, #80] @ (8000974 <main+0x14c>)
|
|
8000922: f005 f8d3 bl 8005acc <HAL_UART_Transmit_DMA>
|
|
HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ));
|
|
8000926: 463b mov r3, r7
|
|
8000928: 2210 movs r2, #16
|
|
800092a: 4619 mov r1, r3
|
|
800092c: 4813 ldr r0, [pc, #76] @ (800097c <main+0x154>)
|
|
800092e: f005 f8cd bl 8005acc <HAL_UART_Transmit_DMA>
|
|
HAL_Delay(500);
|
|
8000932: f44f 70fa mov.w r0, #500 @ 0x1f4
|
|
8000936: f001 f87b bl 8001a30 <HAL_Delay>
|
|
findBestParent(); //So true...
|
|
800093a: f000 f8f3 bl 8000b24 <findBestParent>
|
|
break;
|
|
800093e: e00a b.n 8000956 <main+0x12e>
|
|
resetReport();
|
|
8000940: f000 fa22 bl 8000d88 <resetReport>
|
|
matrixScan();
|
|
8000944: f000 f9c6 bl 8000cd4 <matrixScan>
|
|
USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT));
|
|
8000948: 220e movs r2, #14
|
|
800094a: 4911 ldr r1, [pc, #68] @ (8000990 <main+0x168>)
|
|
800094c: 480f ldr r0, [pc, #60] @ (800098c <main+0x164>)
|
|
800094e: f007 ff71 bl 8008834 <USBD_HID_SendReport>
|
|
break;
|
|
8000952: e000 b.n 8000956 <main+0x12e>
|
|
break;
|
|
8000954: bf00 nop
|
|
}
|
|
|
|
HAL_Delay(50);
|
|
8000956: 2032 movs r0, #50 @ 0x32
|
|
8000958: f001 f86a bl 8001a30 <HAL_Delay>
|
|
switch (MODE){
|
|
800095c: e793 b.n 8000886 <main+0x5e>
|
|
800095e: bf00 nop
|
|
8000960: 20000230 .word 0x20000230
|
|
8000964: 2000038c .word 0x2000038c
|
|
8000968: 20000240 .word 0x20000240
|
|
800096c: 200003d4 .word 0x200003d4
|
|
8000970: 20000250 .word 0x20000250
|
|
8000974: 200002fc .word 0x200002fc
|
|
8000978: 20000220 .word 0x20000220
|
|
800097c: 20000344 .word 0x20000344
|
|
8000980: 20000268 .word 0x20000268
|
|
8000984: 20000260 .word 0x20000260
|
|
8000988: 20000264 .word 0x20000264
|
|
800098c: 20000724 .word 0x20000724
|
|
8000990: 20000210 .word 0x20000210
|
|
|
|
08000994 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8000994: b580 push {r7, lr}
|
|
8000996: b094 sub sp, #80 @ 0x50
|
|
8000998: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
800099a: f107 031c add.w r3, r7, #28
|
|
800099e: 2234 movs r2, #52 @ 0x34
|
|
80009a0: 2100 movs r1, #0
|
|
80009a2: 4618 mov r0, r3
|
|
80009a4: f009 ffc0 bl 800a928 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
80009a8: f107 0308 add.w r3, r7, #8
|
|
80009ac: 2200 movs r2, #0
|
|
80009ae: 601a str r2, [r3, #0]
|
|
80009b0: 605a str r2, [r3, #4]
|
|
80009b2: 609a str r2, [r3, #8]
|
|
80009b4: 60da str r2, [r3, #12]
|
|
80009b6: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80009b8: 2300 movs r3, #0
|
|
80009ba: 607b str r3, [r7, #4]
|
|
80009bc: 4b29 ldr r3, [pc, #164] @ (8000a64 <SystemClock_Config+0xd0>)
|
|
80009be: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80009c0: 4a28 ldr r2, [pc, #160] @ (8000a64 <SystemClock_Config+0xd0>)
|
|
80009c2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80009c6: 6413 str r3, [r2, #64] @ 0x40
|
|
80009c8: 4b26 ldr r3, [pc, #152] @ (8000a64 <SystemClock_Config+0xd0>)
|
|
80009ca: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80009cc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80009d0: 607b str r3, [r7, #4]
|
|
80009d2: 687b ldr r3, [r7, #4]
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
|
|
80009d4: 2300 movs r3, #0
|
|
80009d6: 603b str r3, [r7, #0]
|
|
80009d8: 4b23 ldr r3, [pc, #140] @ (8000a68 <SystemClock_Config+0xd4>)
|
|
80009da: 681b ldr r3, [r3, #0]
|
|
80009dc: f423 4340 bic.w r3, r3, #49152 @ 0xc000
|
|
80009e0: 4a21 ldr r2, [pc, #132] @ (8000a68 <SystemClock_Config+0xd4>)
|
|
80009e2: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
80009e6: 6013 str r3, [r2, #0]
|
|
80009e8: 4b1f ldr r3, [pc, #124] @ (8000a68 <SystemClock_Config+0xd4>)
|
|
80009ea: 681b ldr r3, [r3, #0]
|
|
80009ec: f403 4340 and.w r3, r3, #49152 @ 0xc000
|
|
80009f0: 603b str r3, [r7, #0]
|
|
80009f2: 683b ldr r3, [r7, #0]
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
80009f4: 2301 movs r3, #1
|
|
80009f6: 61fb str r3, [r7, #28]
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
80009f8: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
80009fc: 623b str r3, [r7, #32]
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
80009fe: 2302 movs r3, #2
|
|
8000a00: 637b str r3, [r7, #52] @ 0x34
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
8000a02: f44f 0380 mov.w r3, #4194304 @ 0x400000
|
|
8000a06: 63bb str r3, [r7, #56] @ 0x38
|
|
RCC_OscInitStruct.PLL.PLLM = 4;
|
|
8000a08: 2304 movs r3, #4
|
|
8000a0a: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.PLL.PLLN = 96;
|
|
8000a0c: 2360 movs r3, #96 @ 0x60
|
|
8000a0e: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
8000a10: 2302 movs r3, #2
|
|
8000a12: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLQ = 4;
|
|
8000a14: 2304 movs r3, #4
|
|
8000a16: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLR = 2;
|
|
8000a18: 2302 movs r3, #2
|
|
8000a1a: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8000a1c: f107 031c add.w r3, r7, #28
|
|
8000a20: 4618 mov r0, r3
|
|
8000a22: f004 f941 bl 8004ca8 <HAL_RCC_OscConfig>
|
|
8000a26: 4603 mov r3, r0
|
|
8000a28: 2b00 cmp r3, #0
|
|
8000a2a: d001 beq.n 8000a30 <SystemClock_Config+0x9c>
|
|
{
|
|
Error_Handler();
|
|
8000a2c: f000 f9bc bl 8000da8 <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
8000a30: 230f movs r3, #15
|
|
8000a32: 60bb str r3, [r7, #8]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
8000a34: 2302 movs r3, #2
|
|
8000a36: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
|
|
8000a38: 2380 movs r3, #128 @ 0x80
|
|
8000a3a: 613b str r3, [r7, #16]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
|
|
8000a3c: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8000a40: 617b str r3, [r7, #20]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
8000a42: 2300 movs r3, #0
|
|
8000a44: 61bb str r3, [r7, #24]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
|
|
8000a46: f107 0308 add.w r3, r7, #8
|
|
8000a4a: 2101 movs r1, #1
|
|
8000a4c: 4618 mov r0, r3
|
|
8000a4e: f003 fab7 bl 8003fc0 <HAL_RCC_ClockConfig>
|
|
8000a52: 4603 mov r3, r0
|
|
8000a54: 2b00 cmp r3, #0
|
|
8000a56: d001 beq.n 8000a5c <SystemClock_Config+0xc8>
|
|
{
|
|
Error_Handler();
|
|
8000a58: f000 f9a6 bl 8000da8 <Error_Handler>
|
|
}
|
|
}
|
|
8000a5c: bf00 nop
|
|
8000a5e: 3750 adds r7, #80 @ 0x50
|
|
8000a60: 46bd mov sp, r7
|
|
8000a62: bd80 pop {r7, pc}
|
|
8000a64: 40023800 .word 0x40023800
|
|
8000a68: 40007000 .word 0x40007000
|
|
|
|
08000a6c <HAL_UART_RxCpltCallback>:
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
// UART Message Requests Goes Here
|
|
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) {
|
|
8000a6c: b580 push {r7, lr}
|
|
8000a6e: b082 sub sp, #8
|
|
8000a70: af00 add r7, sp, #0
|
|
8000a72: 6078 str r0, [r7, #4]
|
|
if (huart->Instance == USART1) {
|
|
8000a74: 687b ldr r3, [r7, #4]
|
|
8000a76: 681b ldr r3, [r3, #0]
|
|
8000a78: 4a1e ldr r2, [pc, #120] @ (8000af4 <HAL_UART_RxCpltCallback+0x88>)
|
|
8000a7a: 4293 cmp r3, r2
|
|
8000a7c: d109 bne.n 8000a92 <HAL_UART_RxCpltCallback+0x26>
|
|
handleUARTMessages((uint8_t*)&RX1Msg, &huart1);
|
|
8000a7e: 491e ldr r1, [pc, #120] @ (8000af8 <HAL_UART_RxCpltCallback+0x8c>)
|
|
8000a80: 481e ldr r0, [pc, #120] @ (8000afc <HAL_UART_RxCpltCallback+0x90>)
|
|
8000a82: f000 f891 bl 8000ba8 <handleUARTMessages>
|
|
HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage));
|
|
8000a86: 2210 movs r2, #16
|
|
8000a88: 491c ldr r1, [pc, #112] @ (8000afc <HAL_UART_RxCpltCallback+0x90>)
|
|
8000a8a: 481b ldr r0, [pc, #108] @ (8000af8 <HAL_UART_RxCpltCallback+0x8c>)
|
|
8000a8c: f005 f89a bl 8005bc4 <HAL_UART_Receive_DMA>
|
|
}
|
|
else if (huart->Instance == UART5) {
|
|
handleUARTMessages((uint8_t*)&RX5Msg, &huart5);
|
|
HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage));
|
|
}
|
|
}
|
|
8000a90: e02b b.n 8000aea <HAL_UART_RxCpltCallback+0x7e>
|
|
else if (huart->Instance == USART2) {
|
|
8000a92: 687b ldr r3, [r7, #4]
|
|
8000a94: 681b ldr r3, [r3, #0]
|
|
8000a96: 4a1a ldr r2, [pc, #104] @ (8000b00 <HAL_UART_RxCpltCallback+0x94>)
|
|
8000a98: 4293 cmp r3, r2
|
|
8000a9a: d109 bne.n 8000ab0 <HAL_UART_RxCpltCallback+0x44>
|
|
handleUARTMessages((uint8_t*)&RX2Msg, &huart2);
|
|
8000a9c: 4919 ldr r1, [pc, #100] @ (8000b04 <HAL_UART_RxCpltCallback+0x98>)
|
|
8000a9e: 481a ldr r0, [pc, #104] @ (8000b08 <HAL_UART_RxCpltCallback+0x9c>)
|
|
8000aa0: f000 f882 bl 8000ba8 <handleUARTMessages>
|
|
HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage));
|
|
8000aa4: 2210 movs r2, #16
|
|
8000aa6: 4918 ldr r1, [pc, #96] @ (8000b08 <HAL_UART_RxCpltCallback+0x9c>)
|
|
8000aa8: 4816 ldr r0, [pc, #88] @ (8000b04 <HAL_UART_RxCpltCallback+0x98>)
|
|
8000aaa: f005 f88b bl 8005bc4 <HAL_UART_Receive_DMA>
|
|
}
|
|
8000aae: e01c b.n 8000aea <HAL_UART_RxCpltCallback+0x7e>
|
|
else if (huart->Instance == UART4) {
|
|
8000ab0: 687b ldr r3, [r7, #4]
|
|
8000ab2: 681b ldr r3, [r3, #0]
|
|
8000ab4: 4a15 ldr r2, [pc, #84] @ (8000b0c <HAL_UART_RxCpltCallback+0xa0>)
|
|
8000ab6: 4293 cmp r3, r2
|
|
8000ab8: d109 bne.n 8000ace <HAL_UART_RxCpltCallback+0x62>
|
|
handleUARTMessages((uint8_t*)&RX4Msg, &huart4);
|
|
8000aba: 4915 ldr r1, [pc, #84] @ (8000b10 <HAL_UART_RxCpltCallback+0xa4>)
|
|
8000abc: 4815 ldr r0, [pc, #84] @ (8000b14 <HAL_UART_RxCpltCallback+0xa8>)
|
|
8000abe: f000 f873 bl 8000ba8 <handleUARTMessages>
|
|
HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage));
|
|
8000ac2: 2210 movs r2, #16
|
|
8000ac4: 4913 ldr r1, [pc, #76] @ (8000b14 <HAL_UART_RxCpltCallback+0xa8>)
|
|
8000ac6: 4812 ldr r0, [pc, #72] @ (8000b10 <HAL_UART_RxCpltCallback+0xa4>)
|
|
8000ac8: f005 f87c bl 8005bc4 <HAL_UART_Receive_DMA>
|
|
}
|
|
8000acc: e00d b.n 8000aea <HAL_UART_RxCpltCallback+0x7e>
|
|
else if (huart->Instance == UART5) {
|
|
8000ace: 687b ldr r3, [r7, #4]
|
|
8000ad0: 681b ldr r3, [r3, #0]
|
|
8000ad2: 4a11 ldr r2, [pc, #68] @ (8000b18 <HAL_UART_RxCpltCallback+0xac>)
|
|
8000ad4: 4293 cmp r3, r2
|
|
8000ad6: d108 bne.n 8000aea <HAL_UART_RxCpltCallback+0x7e>
|
|
handleUARTMessages((uint8_t*)&RX5Msg, &huart5);
|
|
8000ad8: 4910 ldr r1, [pc, #64] @ (8000b1c <HAL_UART_RxCpltCallback+0xb0>)
|
|
8000ada: 4811 ldr r0, [pc, #68] @ (8000b20 <HAL_UART_RxCpltCallback+0xb4>)
|
|
8000adc: f000 f864 bl 8000ba8 <handleUARTMessages>
|
|
HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage));
|
|
8000ae0: 2210 movs r2, #16
|
|
8000ae2: 490f ldr r1, [pc, #60] @ (8000b20 <HAL_UART_RxCpltCallback+0xb4>)
|
|
8000ae4: 480d ldr r0, [pc, #52] @ (8000b1c <HAL_UART_RxCpltCallback+0xb0>)
|
|
8000ae6: f005 f86d bl 8005bc4 <HAL_UART_Receive_DMA>
|
|
}
|
|
8000aea: bf00 nop
|
|
8000aec: 3708 adds r7, #8
|
|
8000aee: 46bd mov sp, r7
|
|
8000af0: bd80 pop {r7, pc}
|
|
8000af2: bf00 nop
|
|
8000af4: 40011000 .word 0x40011000
|
|
8000af8: 2000038c .word 0x2000038c
|
|
8000afc: 20000230 .word 0x20000230
|
|
8000b00: 40004400 .word 0x40004400
|
|
8000b04: 200003d4 .word 0x200003d4
|
|
8000b08: 20000240 .word 0x20000240
|
|
8000b0c: 40004c00 .word 0x40004c00
|
|
8000b10: 200002fc .word 0x200002fc
|
|
8000b14: 20000250 .word 0x20000250
|
|
8000b18: 40005000 .word 0x40005000
|
|
8000b1c: 20000344 .word 0x20000344
|
|
8000b20: 20000220 .word 0x20000220
|
|
|
|
08000b24 <findBestParent>:
|
|
|
|
|
|
void findBestParent(){
|
|
8000b24: b580 push {r7, lr}
|
|
8000b26: b084 sub sp, #16
|
|
8000b28: af00 add r7, sp, #0
|
|
//Find least depth parent
|
|
uint16_t least_val = 0xFF;
|
|
8000b2a: 23ff movs r3, #255 @ 0xff
|
|
8000b2c: 81fb strh r3, [r7, #14]
|
|
UART_HandleTypeDef* least_port = NULL;
|
|
8000b2e: 2300 movs r3, #0
|
|
8000b30: 60bb str r3, [r7, #8]
|
|
for(uint8_t i = 0; i < 4; i++){
|
|
8000b32: 2300 movs r3, #0
|
|
8000b34: 71fb strb r3, [r7, #7]
|
|
8000b36: e013 b.n 8000b60 <findBestParent+0x3c>
|
|
if(PORT_DEPTH[i]<least_val){
|
|
8000b38: 79fb ldrb r3, [r7, #7]
|
|
8000b3a: 4a16 ldr r2, [pc, #88] @ (8000b94 <findBestParent+0x70>)
|
|
8000b3c: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8000b40: 89fa ldrh r2, [r7, #14]
|
|
8000b42: 429a cmp r2, r3
|
|
8000b44: d909 bls.n 8000b5a <findBestParent+0x36>
|
|
least_port = PORTS[i];
|
|
8000b46: 79fb ldrb r3, [r7, #7]
|
|
8000b48: 4a13 ldr r2, [pc, #76] @ (8000b98 <findBestParent+0x74>)
|
|
8000b4a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8000b4e: 60bb str r3, [r7, #8]
|
|
least_val = PORT_DEPTH[i];
|
|
8000b50: 79fb ldrb r3, [r7, #7]
|
|
8000b52: 4a10 ldr r2, [pc, #64] @ (8000b94 <findBestParent+0x70>)
|
|
8000b54: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8000b58: 81fb strh r3, [r7, #14]
|
|
for(uint8_t i = 0; i < 4; i++){
|
|
8000b5a: 79fb ldrb r3, [r7, #7]
|
|
8000b5c: 3301 adds r3, #1
|
|
8000b5e: 71fb strb r3, [r7, #7]
|
|
8000b60: 79fb ldrb r3, [r7, #7]
|
|
8000b62: 2b03 cmp r3, #3
|
|
8000b64: d9e8 bls.n 8000b38 <findBestParent+0x14>
|
|
}
|
|
}
|
|
|
|
//Assign if valid
|
|
if(least_val < 0xFF){
|
|
8000b66: 89fb ldrh r3, [r7, #14]
|
|
8000b68: 2bfe cmp r3, #254 @ 0xfe
|
|
8000b6a: d80e bhi.n 8000b8a <findBestParent+0x66>
|
|
PARENT = least_port;
|
|
8000b6c: 4a0b ldr r2, [pc, #44] @ (8000b9c <findBestParent+0x78>)
|
|
8000b6e: 68bb ldr r3, [r7, #8]
|
|
8000b70: 6013 str r3, [r2, #0]
|
|
DEPTH = least_val + 1;
|
|
8000b72: 89fb ldrh r3, [r7, #14]
|
|
8000b74: 3301 adds r3, #1
|
|
8000b76: b29a uxth r2, r3
|
|
8000b78: 4b09 ldr r3, [pc, #36] @ (8000ba0 <findBestParent+0x7c>)
|
|
8000b7a: 801a strh r2, [r3, #0]
|
|
MODE = MODE_ACTIVE;
|
|
8000b7c: 4b09 ldr r3, [pc, #36] @ (8000ba4 <findBestParent+0x80>)
|
|
8000b7e: 2202 movs r2, #2
|
|
8000b80: 701a strb r2, [r3, #0]
|
|
HAL_Delay(500);
|
|
8000b82: f44f 70fa mov.w r0, #500 @ 0x1f4
|
|
8000b86: f000 ff53 bl 8001a30 <HAL_Delay>
|
|
}
|
|
}
|
|
8000b8a: bf00 nop
|
|
8000b8c: 3710 adds r7, #16
|
|
8000b8e: 46bd mov sp, r7
|
|
8000b90: bd80 pop {r7, pc}
|
|
8000b92: bf00 nop
|
|
8000b94: 20000078 .word 0x20000078
|
|
8000b98: 20000080 .word 0x20000080
|
|
8000b9c: 20000264 .word 0x20000264
|
|
8000ba0: 20000260 .word 0x20000260
|
|
8000ba4: 20000268 .word 0x20000268
|
|
|
|
08000ba8 <handleUARTMessages>:
|
|
|
|
// Called when UART RX interrupt completes
|
|
void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender) {
|
|
8000ba8: b580 push {r7, lr}
|
|
8000baa: b08a sub sp, #40 @ 0x28
|
|
8000bac: af00 add r7, sp, #0
|
|
8000bae: 6078 str r0, [r7, #4]
|
|
8000bb0: 6039 str r1, [r7, #0]
|
|
UARTMessage msg;
|
|
UARTMessage reply;
|
|
|
|
// Parse incoming message into struct
|
|
memcpy(&msg, data, sizeof(UARTMessage));
|
|
8000bb2: f107 0318 add.w r3, r7, #24
|
|
8000bb6: 2210 movs r2, #16
|
|
8000bb8: 6879 ldr r1, [r7, #4]
|
|
8000bba: 4618 mov r0, r3
|
|
8000bbc: f009 fee0 bl 800a980 <memcpy>
|
|
|
|
switch(msg.TYPE) {
|
|
8000bc0: 8b7b ldrh r3, [r7, #26]
|
|
8000bc2: 2baa cmp r3, #170 @ 0xaa
|
|
8000bc4: d002 beq.n 8000bcc <handleUARTMessages+0x24>
|
|
8000bc6: 2bff cmp r3, #255 @ 0xff
|
|
8000bc8: d020 beq.n 8000c0c <handleUARTMessages+0x64>
|
|
HAL_UART_Transmit_DMA(sender, (uint8_t*)&reply, sizeof(reply));
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
8000bca: e03c b.n 8000c46 <handleUARTMessages+0x9e>
|
|
if(sender == &huart5) {
|
|
8000bcc: 683b ldr r3, [r7, #0]
|
|
8000bce: 4a20 ldr r2, [pc, #128] @ (8000c50 <handleUARTMessages+0xa8>)
|
|
8000bd0: 4293 cmp r3, r2
|
|
8000bd2: d103 bne.n 8000bdc <handleUARTMessages+0x34>
|
|
PORT_DEPTH[0] = msg.DEPTH;
|
|
8000bd4: 8b3a ldrh r2, [r7, #24]
|
|
8000bd6: 4b1f ldr r3, [pc, #124] @ (8000c54 <handleUARTMessages+0xac>)
|
|
8000bd8: 801a strh r2, [r3, #0]
|
|
break;
|
|
8000bda: e031 b.n 8000c40 <handleUARTMessages+0x98>
|
|
} else if(sender == &huart1) {
|
|
8000bdc: 683b ldr r3, [r7, #0]
|
|
8000bde: 4a1e ldr r2, [pc, #120] @ (8000c58 <handleUARTMessages+0xb0>)
|
|
8000be0: 4293 cmp r3, r2
|
|
8000be2: d103 bne.n 8000bec <handleUARTMessages+0x44>
|
|
PORT_DEPTH[1] = msg.DEPTH;
|
|
8000be4: 8b3a ldrh r2, [r7, #24]
|
|
8000be6: 4b1b ldr r3, [pc, #108] @ (8000c54 <handleUARTMessages+0xac>)
|
|
8000be8: 805a strh r2, [r3, #2]
|
|
break;
|
|
8000bea: e029 b.n 8000c40 <handleUARTMessages+0x98>
|
|
} else if(sender == &huart2) {
|
|
8000bec: 683b ldr r3, [r7, #0]
|
|
8000bee: 4a1b ldr r2, [pc, #108] @ (8000c5c <handleUARTMessages+0xb4>)
|
|
8000bf0: 4293 cmp r3, r2
|
|
8000bf2: d103 bne.n 8000bfc <handleUARTMessages+0x54>
|
|
PORT_DEPTH[2] = msg.DEPTH;
|
|
8000bf4: 8b3a ldrh r2, [r7, #24]
|
|
8000bf6: 4b17 ldr r3, [pc, #92] @ (8000c54 <handleUARTMessages+0xac>)
|
|
8000bf8: 809a strh r2, [r3, #4]
|
|
break;
|
|
8000bfa: e021 b.n 8000c40 <handleUARTMessages+0x98>
|
|
} else if(sender == &huart4) {
|
|
8000bfc: 683b ldr r3, [r7, #0]
|
|
8000bfe: 4a18 ldr r2, [pc, #96] @ (8000c60 <handleUARTMessages+0xb8>)
|
|
8000c00: 4293 cmp r3, r2
|
|
8000c02: d11d bne.n 8000c40 <handleUARTMessages+0x98>
|
|
PORT_DEPTH[3] = msg.DEPTH;
|
|
8000c04: 8b3a ldrh r2, [r7, #24]
|
|
8000c06: 4b13 ldr r3, [pc, #76] @ (8000c54 <handleUARTMessages+0xac>)
|
|
8000c08: 80da strh r2, [r3, #6]
|
|
break;
|
|
8000c0a: e019 b.n 8000c40 <handleUARTMessages+0x98>
|
|
if(MODE!=MODE_INACTIVE){
|
|
8000c0c: 4b15 ldr r3, [pc, #84] @ (8000c64 <handleUARTMessages+0xbc>)
|
|
8000c0e: 781b ldrb r3, [r3, #0]
|
|
8000c10: b2db uxtb r3, r3
|
|
8000c12: 2b00 cmp r3, #0
|
|
8000c14: d016 beq.n 8000c44 <handleUARTMessages+0x9c>
|
|
reply.TYPE = 0xAA;
|
|
8000c16: 23aa movs r3, #170 @ 0xaa
|
|
8000c18: 817b strh r3, [r7, #10]
|
|
reply.DEPTH = DEPTH; // use your local DEPTH
|
|
8000c1a: 4b13 ldr r3, [pc, #76] @ (8000c68 <handleUARTMessages+0xc0>)
|
|
8000c1c: 881b ldrh r3, [r3, #0]
|
|
8000c1e: 813b strh r3, [r7, #8]
|
|
memset(reply.KEYPRESS, 0, sizeof(reply.KEYPRESS));
|
|
8000c20: f107 0308 add.w r3, r7, #8
|
|
8000c24: 3304 adds r3, #4
|
|
8000c26: 220c movs r2, #12
|
|
8000c28: 2100 movs r1, #0
|
|
8000c2a: 4618 mov r0, r3
|
|
8000c2c: f009 fe7c bl 800a928 <memset>
|
|
HAL_UART_Transmit_DMA(sender, (uint8_t*)&reply, sizeof(reply));
|
|
8000c30: f107 0308 add.w r3, r7, #8
|
|
8000c34: 2210 movs r2, #16
|
|
8000c36: 4619 mov r1, r3
|
|
8000c38: 6838 ldr r0, [r7, #0]
|
|
8000c3a: f004 ff47 bl 8005acc <HAL_UART_Transmit_DMA>
|
|
break;
|
|
8000c3e: e001 b.n 8000c44 <handleUARTMessages+0x9c>
|
|
break;
|
|
8000c40: bf00 nop
|
|
8000c42: e000 b.n 8000c46 <handleUARTMessages+0x9e>
|
|
break;
|
|
8000c44: bf00 nop
|
|
|
|
}
|
|
}
|
|
8000c46: bf00 nop
|
|
8000c48: 3728 adds r7, #40 @ 0x28
|
|
8000c4a: 46bd mov sp, r7
|
|
8000c4c: bd80 pop {r7, pc}
|
|
8000c4e: bf00 nop
|
|
8000c50: 20000344 .word 0x20000344
|
|
8000c54: 20000078 .word 0x20000078
|
|
8000c58: 2000038c .word 0x2000038c
|
|
8000c5c: 200003d4 .word 0x200003d4
|
|
8000c60: 200002fc .word 0x200002fc
|
|
8000c64: 20000268 .word 0x20000268
|
|
8000c68: 20000260 .word 0x20000260
|
|
|
|
08000c6c <addUSBReport>:
|
|
|
|
|
|
void addUSBReport(uint8_t usageID){
|
|
8000c6c: b480 push {r7}
|
|
8000c6e: b085 sub sp, #20
|
|
8000c70: af00 add r7, sp, #0
|
|
8000c72: 4603 mov r3, r0
|
|
8000c74: 71fb strb r3, [r7, #7]
|
|
if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds
|
|
8000c76: 79fb ldrb r3, [r7, #7]
|
|
8000c78: 2b03 cmp r3, #3
|
|
8000c7a: d922 bls.n 8000cc2 <addUSBReport+0x56>
|
|
8000c7c: 79fb ldrb r3, [r7, #7]
|
|
8000c7e: 2b73 cmp r3, #115 @ 0x73
|
|
8000c80: d81f bhi.n 8000cc2 <addUSBReport+0x56>
|
|
uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit
|
|
8000c82: 79fb ldrb r3, [r7, #7]
|
|
8000c84: b29b uxth r3, r3
|
|
8000c86: 3b04 subs r3, #4
|
|
8000c88: 81fb strh r3, [r7, #14]
|
|
uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array
|
|
8000c8a: 89fb ldrh r3, [r7, #14]
|
|
8000c8c: 08db lsrs r3, r3, #3
|
|
8000c8e: b29b uxth r3, r3
|
|
8000c90: 737b strb r3, [r7, #13]
|
|
uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset
|
|
8000c92: 89fb ldrh r3, [r7, #14]
|
|
8000c94: b2db uxtb r3, r3
|
|
8000c96: f003 0307 and.w r3, r3, #7
|
|
8000c9a: 733b strb r3, [r7, #12]
|
|
REPORT.KEYPRESS[byte_index] |= (1 << bit_offset);
|
|
8000c9c: 7b7b ldrb r3, [r7, #13]
|
|
8000c9e: 4a0c ldr r2, [pc, #48] @ (8000cd0 <addUSBReport+0x64>)
|
|
8000ca0: 4413 add r3, r2
|
|
8000ca2: 789b ldrb r3, [r3, #2]
|
|
8000ca4: b25a sxtb r2, r3
|
|
8000ca6: 7b3b ldrb r3, [r7, #12]
|
|
8000ca8: 2101 movs r1, #1
|
|
8000caa: fa01 f303 lsl.w r3, r1, r3
|
|
8000cae: b25b sxtb r3, r3
|
|
8000cb0: 4313 orrs r3, r2
|
|
8000cb2: b25a sxtb r2, r3
|
|
8000cb4: 7b7b ldrb r3, [r7, #13]
|
|
8000cb6: b2d1 uxtb r1, r2
|
|
8000cb8: 4a05 ldr r2, [pc, #20] @ (8000cd0 <addUSBReport+0x64>)
|
|
8000cba: 4413 add r3, r2
|
|
8000cbc: 460a mov r2, r1
|
|
8000cbe: 709a strb r2, [r3, #2]
|
|
8000cc0: e000 b.n 8000cc4 <addUSBReport+0x58>
|
|
if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds
|
|
8000cc2: bf00 nop
|
|
}
|
|
8000cc4: 3714 adds r7, #20
|
|
8000cc6: 46bd mov sp, r7
|
|
8000cc8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000ccc: 4770 bx lr
|
|
8000cce: bf00 nop
|
|
8000cd0: 20000210 .word 0x20000210
|
|
|
|
08000cd4 <matrixScan>:
|
|
|
|
void matrixScan(void){
|
|
8000cd4: b580 push {r7, lr}
|
|
8000cd6: b082 sub sp, #8
|
|
8000cd8: af00 add r7, sp, #0
|
|
for (uint8_t col = 0; col < COL; col++){
|
|
8000cda: 2300 movs r3, #0
|
|
8000cdc: 71fb strb r3, [r7, #7]
|
|
8000cde: e044 b.n 8000d6a <matrixScan+0x96>
|
|
HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET);
|
|
8000ce0: 79fb ldrb r3, [r7, #7]
|
|
8000ce2: 4a26 ldr r2, [pc, #152] @ (8000d7c <matrixScan+0xa8>)
|
|
8000ce4: f852 0033 ldr.w r0, [r2, r3, lsl #3]
|
|
8000ce8: 79fb ldrb r3, [r7, #7]
|
|
8000cea: 4a24 ldr r2, [pc, #144] @ (8000d7c <matrixScan+0xa8>)
|
|
8000cec: 00db lsls r3, r3, #3
|
|
8000cee: 4413 add r3, r2
|
|
8000cf0: 889b ldrh r3, [r3, #4]
|
|
8000cf2: 2201 movs r2, #1
|
|
8000cf4: 4619 mov r1, r3
|
|
8000cf6: f001 fd7f bl 80027f8 <HAL_GPIO_WritePin>
|
|
HAL_Delay(1);
|
|
8000cfa: 2001 movs r0, #1
|
|
8000cfc: f000 fe98 bl 8001a30 <HAL_Delay>
|
|
for(uint8_t row = 0; row < ROW; row++){
|
|
8000d00: 2300 movs r3, #0
|
|
8000d02: 71bb strb r3, [r7, #6]
|
|
8000d04: e01e b.n 8000d44 <matrixScan+0x70>
|
|
if(HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN)){
|
|
8000d06: 79bb ldrb r3, [r7, #6]
|
|
8000d08: 4a1d ldr r2, [pc, #116] @ (8000d80 <matrixScan+0xac>)
|
|
8000d0a: f852 2033 ldr.w r2, [r2, r3, lsl #3]
|
|
8000d0e: 79bb ldrb r3, [r7, #6]
|
|
8000d10: 491b ldr r1, [pc, #108] @ (8000d80 <matrixScan+0xac>)
|
|
8000d12: 00db lsls r3, r3, #3
|
|
8000d14: 440b add r3, r1
|
|
8000d16: 889b ldrh r3, [r3, #4]
|
|
8000d18: 4619 mov r1, r3
|
|
8000d1a: 4610 mov r0, r2
|
|
8000d1c: f001 fd54 bl 80027c8 <HAL_GPIO_ReadPin>
|
|
8000d20: 4603 mov r3, r0
|
|
8000d22: 2b00 cmp r3, #0
|
|
8000d24: d00b beq.n 8000d3e <matrixScan+0x6a>
|
|
addUSBReport(KEYCODES[row][col]);
|
|
8000d26: 79ba ldrb r2, [r7, #6]
|
|
8000d28: 79f9 ldrb r1, [r7, #7]
|
|
8000d2a: 4816 ldr r0, [pc, #88] @ (8000d84 <matrixScan+0xb0>)
|
|
8000d2c: 4613 mov r3, r2
|
|
8000d2e: 009b lsls r3, r3, #2
|
|
8000d30: 4413 add r3, r2
|
|
8000d32: 4403 add r3, r0
|
|
8000d34: 440b add r3, r1
|
|
8000d36: 781b ldrb r3, [r3, #0]
|
|
8000d38: 4618 mov r0, r3
|
|
8000d3a: f7ff ff97 bl 8000c6c <addUSBReport>
|
|
for(uint8_t row = 0; row < ROW; row++){
|
|
8000d3e: 79bb ldrb r3, [r7, #6]
|
|
8000d40: 3301 adds r3, #1
|
|
8000d42: 71bb strb r3, [r7, #6]
|
|
8000d44: 79bb ldrb r3, [r7, #6]
|
|
8000d46: 2b05 cmp r3, #5
|
|
8000d48: d9dd bls.n 8000d06 <matrixScan+0x32>
|
|
}
|
|
}
|
|
HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET);
|
|
8000d4a: 79fb ldrb r3, [r7, #7]
|
|
8000d4c: 4a0b ldr r2, [pc, #44] @ (8000d7c <matrixScan+0xa8>)
|
|
8000d4e: f852 0033 ldr.w r0, [r2, r3, lsl #3]
|
|
8000d52: 79fb ldrb r3, [r7, #7]
|
|
8000d54: 4a09 ldr r2, [pc, #36] @ (8000d7c <matrixScan+0xa8>)
|
|
8000d56: 00db lsls r3, r3, #3
|
|
8000d58: 4413 add r3, r2
|
|
8000d5a: 889b ldrh r3, [r3, #4]
|
|
8000d5c: 2200 movs r2, #0
|
|
8000d5e: 4619 mov r1, r3
|
|
8000d60: f001 fd4a bl 80027f8 <HAL_GPIO_WritePin>
|
|
for (uint8_t col = 0; col < COL; col++){
|
|
8000d64: 79fb ldrb r3, [r7, #7]
|
|
8000d66: 3301 adds r3, #1
|
|
8000d68: 71fb strb r3, [r7, #7]
|
|
8000d6a: 79fb ldrb r3, [r7, #7]
|
|
8000d6c: 2b04 cmp r3, #4
|
|
8000d6e: d9b7 bls.n 8000ce0 <matrixScan+0xc>
|
|
}
|
|
}
|
|
8000d70: bf00 nop
|
|
8000d72: bf00 nop
|
|
8000d74: 3708 adds r7, #8
|
|
8000d76: 46bd mov sp, r7
|
|
8000d78: bd80 pop {r7, pc}
|
|
8000d7a: bf00 nop
|
|
8000d7c: 20000030 .word 0x20000030
|
|
8000d80: 20000000 .word 0x20000000
|
|
8000d84: 20000058 .word 0x20000058
|
|
|
|
08000d88 <resetReport>:
|
|
|
|
void resetReport(void){
|
|
8000d88: b580 push {r7, lr}
|
|
8000d8a: af00 add r7, sp, #0
|
|
REPORT.MODIFIER = 0;
|
|
8000d8c: 4b04 ldr r3, [pc, #16] @ (8000da0 <resetReport+0x18>)
|
|
8000d8e: 2200 movs r2, #0
|
|
8000d90: 701a strb r2, [r3, #0]
|
|
memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS));
|
|
8000d92: 220c movs r2, #12
|
|
8000d94: 2100 movs r1, #0
|
|
8000d96: 4803 ldr r0, [pc, #12] @ (8000da4 <resetReport+0x1c>)
|
|
8000d98: f009 fdc6 bl 800a928 <memset>
|
|
}
|
|
8000d9c: bf00 nop
|
|
8000d9e: bd80 pop {r7, pc}
|
|
8000da0: 20000210 .word 0x20000210
|
|
8000da4: 20000212 .word 0x20000212
|
|
|
|
08000da8 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8000da8: b480 push {r7}
|
|
8000daa: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8000dac: b672 cpsid i
|
|
}
|
|
8000dae: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8000db0: bf00 nop
|
|
8000db2: e7fd b.n 8000db0 <Error_Handler+0x8>
|
|
|
|
08000db4 <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8000db4: b480 push {r7}
|
|
8000db6: b083 sub sp, #12
|
|
8000db8: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8000dba: 2300 movs r3, #0
|
|
8000dbc: 607b str r3, [r7, #4]
|
|
8000dbe: 4b10 ldr r3, [pc, #64] @ (8000e00 <HAL_MspInit+0x4c>)
|
|
8000dc0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000dc2: 4a0f ldr r2, [pc, #60] @ (8000e00 <HAL_MspInit+0x4c>)
|
|
8000dc4: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8000dc8: 6453 str r3, [r2, #68] @ 0x44
|
|
8000dca: 4b0d ldr r3, [pc, #52] @ (8000e00 <HAL_MspInit+0x4c>)
|
|
8000dcc: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000dce: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8000dd2: 607b str r3, [r7, #4]
|
|
8000dd4: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000dd6: 2300 movs r3, #0
|
|
8000dd8: 603b str r3, [r7, #0]
|
|
8000dda: 4b09 ldr r3, [pc, #36] @ (8000e00 <HAL_MspInit+0x4c>)
|
|
8000ddc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000dde: 4a08 ldr r2, [pc, #32] @ (8000e00 <HAL_MspInit+0x4c>)
|
|
8000de0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8000de4: 6413 str r3, [r2, #64] @ 0x40
|
|
8000de6: 4b06 ldr r3, [pc, #24] @ (8000e00 <HAL_MspInit+0x4c>)
|
|
8000de8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000dea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8000dee: 603b str r3, [r7, #0]
|
|
8000df0: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8000df2: bf00 nop
|
|
8000df4: 370c adds r7, #12
|
|
8000df6: 46bd mov sp, r7
|
|
8000df8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000dfc: 4770 bx lr
|
|
8000dfe: bf00 nop
|
|
8000e00: 40023800 .word 0x40023800
|
|
|
|
08000e04 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8000e04: b480 push {r7}
|
|
8000e06: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8000e08: bf00 nop
|
|
8000e0a: e7fd b.n 8000e08 <NMI_Handler+0x4>
|
|
|
|
08000e0c <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8000e0c: b480 push {r7}
|
|
8000e0e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8000e10: bf00 nop
|
|
8000e12: e7fd b.n 8000e10 <HardFault_Handler+0x4>
|
|
|
|
08000e14 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8000e14: b480 push {r7}
|
|
8000e16: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8000e18: bf00 nop
|
|
8000e1a: e7fd b.n 8000e18 <MemManage_Handler+0x4>
|
|
|
|
08000e1c <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pre-fetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8000e1c: b480 push {r7}
|
|
8000e1e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8000e20: bf00 nop
|
|
8000e22: e7fd b.n 8000e20 <BusFault_Handler+0x4>
|
|
|
|
08000e24 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8000e24: b480 push {r7}
|
|
8000e26: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8000e28: bf00 nop
|
|
8000e2a: e7fd b.n 8000e28 <UsageFault_Handler+0x4>
|
|
|
|
08000e2c <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8000e2c: b480 push {r7}
|
|
8000e2e: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8000e30: bf00 nop
|
|
8000e32: 46bd mov sp, r7
|
|
8000e34: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000e38: 4770 bx lr
|
|
|
|
08000e3a <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8000e3a: b480 push {r7}
|
|
8000e3c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8000e3e: bf00 nop
|
|
8000e40: 46bd mov sp, r7
|
|
8000e42: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000e46: 4770 bx lr
|
|
|
|
08000e48 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8000e48: b480 push {r7}
|
|
8000e4a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8000e4c: bf00 nop
|
|
8000e4e: 46bd mov sp, r7
|
|
8000e50: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000e54: 4770 bx lr
|
|
|
|
08000e56 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8000e56: b580 push {r7, lr}
|
|
8000e58: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
8000e5a: f000 fdc9 bl 80019f0 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8000e5e: bf00 nop
|
|
8000e60: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08000e64 <DMA1_Stream0_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 stream0 global interrupt.
|
|
*/
|
|
void DMA1_Stream0_IRQHandler(void)
|
|
{
|
|
8000e64: b580 push {r7, lr}
|
|
8000e66: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Stream0_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_uart5_rx);
|
|
8000e68: 4802 ldr r0, [pc, #8] @ (8000e74 <DMA1_Stream0_IRQHandler+0x10>)
|
|
8000e6a: f001 f8af bl 8001fcc <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Stream0_IRQn 1 */
|
|
}
|
|
8000e6e: bf00 nop
|
|
8000e70: bd80 pop {r7, pc}
|
|
8000e72: bf00 nop
|
|
8000e74: 200004dc .word 0x200004dc
|
|
|
|
08000e78 <DMA1_Stream2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 stream2 global interrupt.
|
|
*/
|
|
void DMA1_Stream2_IRQHandler(void)
|
|
{
|
|
8000e78: b580 push {r7, lr}
|
|
8000e7a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Stream2_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Stream2_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_uart4_rx);
|
|
8000e7c: 4802 ldr r0, [pc, #8] @ (8000e88 <DMA1_Stream2_IRQHandler+0x10>)
|
|
8000e7e: f001 f8a5 bl 8001fcc <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Stream2_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Stream2_IRQn 1 */
|
|
}
|
|
8000e82: bf00 nop
|
|
8000e84: bd80 pop {r7, pc}
|
|
8000e86: bf00 nop
|
|
8000e88: 2000041c .word 0x2000041c
|
|
|
|
08000e8c <DMA1_Stream4_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 stream4 global interrupt.
|
|
*/
|
|
void DMA1_Stream4_IRQHandler(void)
|
|
{
|
|
8000e8c: b580 push {r7, lr}
|
|
8000e8e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Stream4_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Stream4_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_uart4_tx);
|
|
8000e90: 4802 ldr r0, [pc, #8] @ (8000e9c <DMA1_Stream4_IRQHandler+0x10>)
|
|
8000e92: f001 f89b bl 8001fcc <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Stream4_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Stream4_IRQn 1 */
|
|
}
|
|
8000e96: bf00 nop
|
|
8000e98: bd80 pop {r7, pc}
|
|
8000e9a: bf00 nop
|
|
8000e9c: 2000047c .word 0x2000047c
|
|
|
|
08000ea0 <DMA1_Stream5_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 stream5 global interrupt.
|
|
*/
|
|
void DMA1_Stream5_IRQHandler(void)
|
|
{
|
|
8000ea0: b580 push {r7, lr}
|
|
8000ea2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Stream5_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_usart2_rx);
|
|
8000ea4: 4802 ldr r0, [pc, #8] @ (8000eb0 <DMA1_Stream5_IRQHandler+0x10>)
|
|
8000ea6: f001 f891 bl 8001fcc <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Stream5_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Stream5_IRQn 1 */
|
|
}
|
|
8000eaa: bf00 nop
|
|
8000eac: bd80 pop {r7, pc}
|
|
8000eae: bf00 nop
|
|
8000eb0: 2000065c .word 0x2000065c
|
|
|
|
08000eb4 <DMA1_Stream6_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 stream6 global interrupt.
|
|
*/
|
|
void DMA1_Stream6_IRQHandler(void)
|
|
{
|
|
8000eb4: b580 push {r7, lr}
|
|
8000eb6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Stream6_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Stream6_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_usart2_tx);
|
|
8000eb8: 4802 ldr r0, [pc, #8] @ (8000ec4 <DMA1_Stream6_IRQHandler+0x10>)
|
|
8000eba: f001 f887 bl 8001fcc <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Stream6_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Stream6_IRQn 1 */
|
|
}
|
|
8000ebe: bf00 nop
|
|
8000ec0: bd80 pop {r7, pc}
|
|
8000ec2: bf00 nop
|
|
8000ec4: 200006bc .word 0x200006bc
|
|
|
|
08000ec8 <USART1_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USART1 global interrupt.
|
|
*/
|
|
void USART1_IRQHandler(void)
|
|
{
|
|
8000ec8: b580 push {r7, lr}
|
|
8000eca: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USART1_IRQn 0 */
|
|
|
|
/* USER CODE END USART1_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart1);
|
|
8000ecc: 4802 ldr r0, [pc, #8] @ (8000ed8 <USART1_IRQHandler+0x10>)
|
|
8000ece: f004 fe9f bl 8005c10 <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN USART1_IRQn 1 */
|
|
|
|
/* USER CODE END USART1_IRQn 1 */
|
|
}
|
|
8000ed2: bf00 nop
|
|
8000ed4: bd80 pop {r7, pc}
|
|
8000ed6: bf00 nop
|
|
8000ed8: 2000038c .word 0x2000038c
|
|
|
|
08000edc <USART2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USART2 global interrupt.
|
|
*/
|
|
void USART2_IRQHandler(void)
|
|
{
|
|
8000edc: b580 push {r7, lr}
|
|
8000ede: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USART2_IRQn 0 */
|
|
|
|
/* USER CODE END USART2_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart2);
|
|
8000ee0: 4802 ldr r0, [pc, #8] @ (8000eec <USART2_IRQHandler+0x10>)
|
|
8000ee2: f004 fe95 bl 8005c10 <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN USART2_IRQn 1 */
|
|
|
|
/* USER CODE END USART2_IRQn 1 */
|
|
}
|
|
8000ee6: bf00 nop
|
|
8000ee8: bd80 pop {r7, pc}
|
|
8000eea: bf00 nop
|
|
8000eec: 200003d4 .word 0x200003d4
|
|
|
|
08000ef0 <DMA1_Stream7_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 stream7 global interrupt.
|
|
*/
|
|
void DMA1_Stream7_IRQHandler(void)
|
|
{
|
|
8000ef0: b580 push {r7, lr}
|
|
8000ef2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Stream7_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Stream7_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_uart5_tx);
|
|
8000ef4: 4802 ldr r0, [pc, #8] @ (8000f00 <DMA1_Stream7_IRQHandler+0x10>)
|
|
8000ef6: f001 f869 bl 8001fcc <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Stream7_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Stream7_IRQn 1 */
|
|
}
|
|
8000efa: bf00 nop
|
|
8000efc: bd80 pop {r7, pc}
|
|
8000efe: bf00 nop
|
|
8000f00: 2000053c .word 0x2000053c
|
|
|
|
08000f04 <UART4_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles UART4 global interrupt.
|
|
*/
|
|
void UART4_IRQHandler(void)
|
|
{
|
|
8000f04: b580 push {r7, lr}
|
|
8000f06: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UART4_IRQn 0 */
|
|
|
|
/* USER CODE END UART4_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart4);
|
|
8000f08: 4802 ldr r0, [pc, #8] @ (8000f14 <UART4_IRQHandler+0x10>)
|
|
8000f0a: f004 fe81 bl 8005c10 <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN UART4_IRQn 1 */
|
|
|
|
/* USER CODE END UART4_IRQn 1 */
|
|
}
|
|
8000f0e: bf00 nop
|
|
8000f10: bd80 pop {r7, pc}
|
|
8000f12: bf00 nop
|
|
8000f14: 200002fc .word 0x200002fc
|
|
|
|
08000f18 <UART5_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles UART5 global interrupt.
|
|
*/
|
|
void UART5_IRQHandler(void)
|
|
{
|
|
8000f18: b580 push {r7, lr}
|
|
8000f1a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UART5_IRQn 0 */
|
|
|
|
/* USER CODE END UART5_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart5);
|
|
8000f1c: 4802 ldr r0, [pc, #8] @ (8000f28 <UART5_IRQHandler+0x10>)
|
|
8000f1e: f004 fe77 bl 8005c10 <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN UART5_IRQn 1 */
|
|
|
|
/* USER CODE END UART5_IRQn 1 */
|
|
}
|
|
8000f22: bf00 nop
|
|
8000f24: bd80 pop {r7, pc}
|
|
8000f26: bf00 nop
|
|
8000f28: 20000344 .word 0x20000344
|
|
|
|
08000f2c <DMA2_Stream2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA2 stream2 global interrupt.
|
|
*/
|
|
void DMA2_Stream2_IRQHandler(void)
|
|
{
|
|
8000f2c: b580 push {r7, lr}
|
|
8000f2e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA2_Stream2_IRQn 0 */
|
|
|
|
/* USER CODE END DMA2_Stream2_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_usart1_rx);
|
|
8000f30: 4802 ldr r0, [pc, #8] @ (8000f3c <DMA2_Stream2_IRQHandler+0x10>)
|
|
8000f32: f001 f84b bl 8001fcc <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA2_Stream2_IRQn 1 */
|
|
|
|
/* USER CODE END DMA2_Stream2_IRQn 1 */
|
|
}
|
|
8000f36: bf00 nop
|
|
8000f38: bd80 pop {r7, pc}
|
|
8000f3a: bf00 nop
|
|
8000f3c: 2000059c .word 0x2000059c
|
|
|
|
08000f40 <OTG_FS_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USB On The Go FS global interrupt.
|
|
*/
|
|
void OTG_FS_IRQHandler(void)
|
|
{
|
|
8000f40: b580 push {r7, lr}
|
|
8000f42: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN OTG_FS_IRQn 0 */
|
|
|
|
/* USER CODE END OTG_FS_IRQn 0 */
|
|
HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
|
|
8000f44: 4802 ldr r0, [pc, #8] @ (8000f50 <OTG_FS_IRQHandler+0x10>)
|
|
8000f46: f001 ff00 bl 8002d4a <HAL_PCD_IRQHandler>
|
|
/* USER CODE BEGIN OTG_FS_IRQn 1 */
|
|
|
|
/* USER CODE END OTG_FS_IRQn 1 */
|
|
}
|
|
8000f4a: bf00 nop
|
|
8000f4c: bd80 pop {r7, pc}
|
|
8000f4e: bf00 nop
|
|
8000f50: 20000c00 .word 0x20000c00
|
|
|
|
08000f54 <DMA2_Stream7_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA2 stream7 global interrupt.
|
|
*/
|
|
void DMA2_Stream7_IRQHandler(void)
|
|
{
|
|
8000f54: b580 push {r7, lr}
|
|
8000f56: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
|
|
|
|
/* USER CODE END DMA2_Stream7_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_usart1_tx);
|
|
8000f58: 4802 ldr r0, [pc, #8] @ (8000f64 <DMA2_Stream7_IRQHandler+0x10>)
|
|
8000f5a: f001 f837 bl 8001fcc <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA2_Stream7_IRQn 1 */
|
|
|
|
/* USER CODE END DMA2_Stream7_IRQn 1 */
|
|
}
|
|
8000f5e: bf00 nop
|
|
8000f60: bd80 pop {r7, pc}
|
|
8000f62: bf00 nop
|
|
8000f64: 200005fc .word 0x200005fc
|
|
|
|
08000f68 <SystemInit>:
|
|
* configuration.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
8000f68: b480 push {r7}
|
|
8000f6a: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
8000f6c: 4b06 ldr r3, [pc, #24] @ (8000f88 <SystemInit+0x20>)
|
|
8000f6e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8000f72: 4a05 ldr r2, [pc, #20] @ (8000f88 <SystemInit+0x20>)
|
|
8000f74: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
8000f78: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
8000f7c: bf00 nop
|
|
8000f7e: 46bd mov sp, r7
|
|
8000f80: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000f84: 4770 bx lr
|
|
8000f86: bf00 nop
|
|
8000f88: e000ed00 .word 0xe000ed00
|
|
|
|
08000f8c <MX_TIM2_Init>:
|
|
TIM_HandleTypeDef htim2;
|
|
TIM_HandleTypeDef htim3;
|
|
|
|
/* TIM2 init function */
|
|
void MX_TIM2_Init(void)
|
|
{
|
|
8000f8c: b580 push {r7, lr}
|
|
8000f8e: b08a sub sp, #40 @ 0x28
|
|
8000f90: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM2_Init 0 */
|
|
|
|
/* USER CODE END TIM2_Init 0 */
|
|
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8000f92: f107 0320 add.w r3, r7, #32
|
|
8000f96: 2200 movs r2, #0
|
|
8000f98: 601a str r2, [r3, #0]
|
|
8000f9a: 605a str r2, [r3, #4]
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
8000f9c: 1d3b adds r3, r7, #4
|
|
8000f9e: 2200 movs r2, #0
|
|
8000fa0: 601a str r2, [r3, #0]
|
|
8000fa2: 605a str r2, [r3, #4]
|
|
8000fa4: 609a str r2, [r3, #8]
|
|
8000fa6: 60da str r2, [r3, #12]
|
|
8000fa8: 611a str r2, [r3, #16]
|
|
8000faa: 615a str r2, [r3, #20]
|
|
8000fac: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE BEGIN TIM2_Init 1 */
|
|
|
|
/* USER CODE END TIM2_Init 1 */
|
|
htim2.Instance = TIM2;
|
|
8000fae: 4b22 ldr r3, [pc, #136] @ (8001038 <MX_TIM2_Init+0xac>)
|
|
8000fb0: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
|
|
8000fb4: 601a str r2, [r3, #0]
|
|
htim2.Init.Prescaler = 0;
|
|
8000fb6: 4b20 ldr r3, [pc, #128] @ (8001038 <MX_TIM2_Init+0xac>)
|
|
8000fb8: 2200 movs r2, #0
|
|
8000fba: 605a str r2, [r3, #4]
|
|
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8000fbc: 4b1e ldr r3, [pc, #120] @ (8001038 <MX_TIM2_Init+0xac>)
|
|
8000fbe: 2200 movs r2, #0
|
|
8000fc0: 609a str r2, [r3, #8]
|
|
htim2.Init.Period = 4294967295;
|
|
8000fc2: 4b1d ldr r3, [pc, #116] @ (8001038 <MX_TIM2_Init+0xac>)
|
|
8000fc4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8000fc8: 60da str r2, [r3, #12]
|
|
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8000fca: 4b1b ldr r3, [pc, #108] @ (8001038 <MX_TIM2_Init+0xac>)
|
|
8000fcc: 2200 movs r2, #0
|
|
8000fce: 611a str r2, [r3, #16]
|
|
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8000fd0: 4b19 ldr r3, [pc, #100] @ (8001038 <MX_TIM2_Init+0xac>)
|
|
8000fd2: 2200 movs r2, #0
|
|
8000fd4: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_OC_Init(&htim2) != HAL_OK)
|
|
8000fd6: 4818 ldr r0, [pc, #96] @ (8001038 <MX_TIM2_Init+0xac>)
|
|
8000fd8: f004 f904 bl 80051e4 <HAL_TIM_OC_Init>
|
|
8000fdc: 4603 mov r3, r0
|
|
8000fde: 2b00 cmp r3, #0
|
|
8000fe0: d001 beq.n 8000fe6 <MX_TIM2_Init+0x5a>
|
|
{
|
|
Error_Handler();
|
|
8000fe2: f7ff fee1 bl 8000da8 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8000fe6: 2300 movs r3, #0
|
|
8000fe8: 623b str r3, [r7, #32]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8000fea: 2300 movs r3, #0
|
|
8000fec: 627b str r3, [r7, #36] @ 0x24
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
|
|
8000fee: f107 0320 add.w r3, r7, #32
|
|
8000ff2: 4619 mov r1, r3
|
|
8000ff4: 4810 ldr r0, [pc, #64] @ (8001038 <MX_TIM2_Init+0xac>)
|
|
8000ff6: f004 fc9d bl 8005934 <HAL_TIMEx_MasterConfigSynchronization>
|
|
8000ffa: 4603 mov r3, r0
|
|
8000ffc: 2b00 cmp r3, #0
|
|
8000ffe: d001 beq.n 8001004 <MX_TIM2_Init+0x78>
|
|
{
|
|
Error_Handler();
|
|
8001000: f7ff fed2 bl 8000da8 <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE;
|
|
8001004: 2350 movs r3, #80 @ 0x50
|
|
8001006: 607b str r3, [r7, #4]
|
|
sConfigOC.Pulse = 0;
|
|
8001008: 2300 movs r3, #0
|
|
800100a: 60bb str r3, [r7, #8]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
800100c: 2300 movs r3, #0
|
|
800100e: 60fb str r3, [r7, #12]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
8001010: 2300 movs r3, #0
|
|
8001012: 617b str r3, [r7, #20]
|
|
if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
8001014: 1d3b adds r3, r7, #4
|
|
8001016: 2200 movs r2, #0
|
|
8001018: 4619 mov r1, r3
|
|
800101a: 4807 ldr r0, [pc, #28] @ (8001038 <MX_TIM2_Init+0xac>)
|
|
800101c: f004 f9d8 bl 80053d0 <HAL_TIM_OC_ConfigChannel>
|
|
8001020: 4603 mov r3, r0
|
|
8001022: 2b00 cmp r3, #0
|
|
8001024: d001 beq.n 800102a <MX_TIM2_Init+0x9e>
|
|
{
|
|
Error_Handler();
|
|
8001026: f7ff febf bl 8000da8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM2_Init 2 */
|
|
|
|
/* USER CODE END TIM2_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim2);
|
|
800102a: 4803 ldr r0, [pc, #12] @ (8001038 <MX_TIM2_Init+0xac>)
|
|
800102c: f000 f8c2 bl 80011b4 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
8001030: bf00 nop
|
|
8001032: 3728 adds r7, #40 @ 0x28
|
|
8001034: 46bd mov sp, r7
|
|
8001036: bd80 pop {r7, pc}
|
|
8001038: 2000026c .word 0x2000026c
|
|
|
|
0800103c <MX_TIM3_Init>:
|
|
/* TIM3 init function */
|
|
void MX_TIM3_Init(void)
|
|
{
|
|
800103c: b580 push {r7, lr}
|
|
800103e: b08c sub sp, #48 @ 0x30
|
|
8001040: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM3_Init 0 */
|
|
|
|
/* USER CODE END TIM3_Init 0 */
|
|
|
|
TIM_Encoder_InitTypeDef sConfig = {0};
|
|
8001042: f107 030c add.w r3, r7, #12
|
|
8001046: 2224 movs r2, #36 @ 0x24
|
|
8001048: 2100 movs r1, #0
|
|
800104a: 4618 mov r0, r3
|
|
800104c: f009 fc6c bl 800a928 <memset>
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8001050: 1d3b adds r3, r7, #4
|
|
8001052: 2200 movs r2, #0
|
|
8001054: 601a str r2, [r3, #0]
|
|
8001056: 605a str r2, [r3, #4]
|
|
|
|
/* USER CODE BEGIN TIM3_Init 1 */
|
|
|
|
/* USER CODE END TIM3_Init 1 */
|
|
htim3.Instance = TIM3;
|
|
8001058: 4b20 ldr r3, [pc, #128] @ (80010dc <MX_TIM3_Init+0xa0>)
|
|
800105a: 4a21 ldr r2, [pc, #132] @ (80010e0 <MX_TIM3_Init+0xa4>)
|
|
800105c: 601a str r2, [r3, #0]
|
|
htim3.Init.Prescaler = 0;
|
|
800105e: 4b1f ldr r3, [pc, #124] @ (80010dc <MX_TIM3_Init+0xa0>)
|
|
8001060: 2200 movs r2, #0
|
|
8001062: 605a str r2, [r3, #4]
|
|
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8001064: 4b1d ldr r3, [pc, #116] @ (80010dc <MX_TIM3_Init+0xa0>)
|
|
8001066: 2200 movs r2, #0
|
|
8001068: 609a str r2, [r3, #8]
|
|
htim3.Init.Period = 65535;
|
|
800106a: 4b1c ldr r3, [pc, #112] @ (80010dc <MX_TIM3_Init+0xa0>)
|
|
800106c: f64f 72ff movw r2, #65535 @ 0xffff
|
|
8001070: 60da str r2, [r3, #12]
|
|
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8001072: 4b1a ldr r3, [pc, #104] @ (80010dc <MX_TIM3_Init+0xa0>)
|
|
8001074: 2200 movs r2, #0
|
|
8001076: 611a str r2, [r3, #16]
|
|
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8001078: 4b18 ldr r3, [pc, #96] @ (80010dc <MX_TIM3_Init+0xa0>)
|
|
800107a: 2200 movs r2, #0
|
|
800107c: 619a str r2, [r3, #24]
|
|
sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
|
|
800107e: 2301 movs r3, #1
|
|
8001080: 60fb str r3, [r7, #12]
|
|
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
|
|
8001082: 2300 movs r3, #0
|
|
8001084: 613b str r3, [r7, #16]
|
|
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
|
|
8001086: 2301 movs r3, #1
|
|
8001088: 617b str r3, [r7, #20]
|
|
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
|
|
800108a: 2300 movs r3, #0
|
|
800108c: 61bb str r3, [r7, #24]
|
|
sConfig.IC1Filter = 0;
|
|
800108e: 2300 movs r3, #0
|
|
8001090: 61fb str r3, [r7, #28]
|
|
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
|
|
8001092: 2300 movs r3, #0
|
|
8001094: 623b str r3, [r7, #32]
|
|
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
|
|
8001096: 2301 movs r3, #1
|
|
8001098: 627b str r3, [r7, #36] @ 0x24
|
|
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
|
|
800109a: 2300 movs r3, #0
|
|
800109c: 62bb str r3, [r7, #40] @ 0x28
|
|
sConfig.IC2Filter = 0;
|
|
800109e: 2300 movs r3, #0
|
|
80010a0: 62fb str r3, [r7, #44] @ 0x2c
|
|
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
|
|
80010a2: f107 030c add.w r3, r7, #12
|
|
80010a6: 4619 mov r1, r3
|
|
80010a8: 480c ldr r0, [pc, #48] @ (80010dc <MX_TIM3_Init+0xa0>)
|
|
80010aa: f004 f8ea bl 8005282 <HAL_TIM_Encoder_Init>
|
|
80010ae: 4603 mov r3, r0
|
|
80010b0: 2b00 cmp r3, #0
|
|
80010b2: d001 beq.n 80010b8 <MX_TIM3_Init+0x7c>
|
|
{
|
|
Error_Handler();
|
|
80010b4: f7ff fe78 bl 8000da8 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
80010b8: 2300 movs r3, #0
|
|
80010ba: 607b str r3, [r7, #4]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
80010bc: 2300 movs r3, #0
|
|
80010be: 60bb str r3, [r7, #8]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
|
80010c0: 1d3b adds r3, r7, #4
|
|
80010c2: 4619 mov r1, r3
|
|
80010c4: 4805 ldr r0, [pc, #20] @ (80010dc <MX_TIM3_Init+0xa0>)
|
|
80010c6: f004 fc35 bl 8005934 <HAL_TIMEx_MasterConfigSynchronization>
|
|
80010ca: 4603 mov r3, r0
|
|
80010cc: 2b00 cmp r3, #0
|
|
80010ce: d001 beq.n 80010d4 <MX_TIM3_Init+0x98>
|
|
{
|
|
Error_Handler();
|
|
80010d0: f7ff fe6a bl 8000da8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM3_Init 2 */
|
|
|
|
/* USER CODE END TIM3_Init 2 */
|
|
|
|
}
|
|
80010d4: bf00 nop
|
|
80010d6: 3730 adds r7, #48 @ 0x30
|
|
80010d8: 46bd mov sp, r7
|
|
80010da: bd80 pop {r7, pc}
|
|
80010dc: 200002b4 .word 0x200002b4
|
|
80010e0: 40000400 .word 0x40000400
|
|
|
|
080010e4 <HAL_TIM_OC_MspInit>:
|
|
|
|
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle)
|
|
{
|
|
80010e4: b480 push {r7}
|
|
80010e6: b085 sub sp, #20
|
|
80010e8: af00 add r7, sp, #0
|
|
80010ea: 6078 str r0, [r7, #4]
|
|
|
|
if(tim_ocHandle->Instance==TIM2)
|
|
80010ec: 687b ldr r3, [r7, #4]
|
|
80010ee: 681b ldr r3, [r3, #0]
|
|
80010f0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80010f4: d10d bne.n 8001112 <HAL_TIM_OC_MspInit+0x2e>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspInit 0 */
|
|
/* TIM2 clock enable */
|
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
|
80010f6: 2300 movs r3, #0
|
|
80010f8: 60fb str r3, [r7, #12]
|
|
80010fa: 4b09 ldr r3, [pc, #36] @ (8001120 <HAL_TIM_OC_MspInit+0x3c>)
|
|
80010fc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80010fe: 4a08 ldr r2, [pc, #32] @ (8001120 <HAL_TIM_OC_MspInit+0x3c>)
|
|
8001100: f043 0301 orr.w r3, r3, #1
|
|
8001104: 6413 str r3, [r2, #64] @ 0x40
|
|
8001106: 4b06 ldr r3, [pc, #24] @ (8001120 <HAL_TIM_OC_MspInit+0x3c>)
|
|
8001108: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800110a: f003 0301 and.w r3, r3, #1
|
|
800110e: 60fb str r3, [r7, #12]
|
|
8001110: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN TIM2_MspInit 1 */
|
|
|
|
/* USER CODE END TIM2_MspInit 1 */
|
|
}
|
|
}
|
|
8001112: bf00 nop
|
|
8001114: 3714 adds r7, #20
|
|
8001116: 46bd mov sp, r7
|
|
8001118: f85d 7b04 ldr.w r7, [sp], #4
|
|
800111c: 4770 bx lr
|
|
800111e: bf00 nop
|
|
8001120: 40023800 .word 0x40023800
|
|
|
|
08001124 <HAL_TIM_Encoder_MspInit>:
|
|
|
|
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle)
|
|
{
|
|
8001124: b580 push {r7, lr}
|
|
8001126: b08a sub sp, #40 @ 0x28
|
|
8001128: af00 add r7, sp, #0
|
|
800112a: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800112c: f107 0314 add.w r3, r7, #20
|
|
8001130: 2200 movs r2, #0
|
|
8001132: 601a str r2, [r3, #0]
|
|
8001134: 605a str r2, [r3, #4]
|
|
8001136: 609a str r2, [r3, #8]
|
|
8001138: 60da str r2, [r3, #12]
|
|
800113a: 611a str r2, [r3, #16]
|
|
if(tim_encoderHandle->Instance==TIM3)
|
|
800113c: 687b ldr r3, [r7, #4]
|
|
800113e: 681b ldr r3, [r3, #0]
|
|
8001140: 4a19 ldr r2, [pc, #100] @ (80011a8 <HAL_TIM_Encoder_MspInit+0x84>)
|
|
8001142: 4293 cmp r3, r2
|
|
8001144: d12b bne.n 800119e <HAL_TIM_Encoder_MspInit+0x7a>
|
|
{
|
|
/* USER CODE BEGIN TIM3_MspInit 0 */
|
|
|
|
/* USER CODE END TIM3_MspInit 0 */
|
|
/* TIM3 clock enable */
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
8001146: 2300 movs r3, #0
|
|
8001148: 613b str r3, [r7, #16]
|
|
800114a: 4b18 ldr r3, [pc, #96] @ (80011ac <HAL_TIM_Encoder_MspInit+0x88>)
|
|
800114c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800114e: 4a17 ldr r2, [pc, #92] @ (80011ac <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001150: f043 0302 orr.w r3, r3, #2
|
|
8001154: 6413 str r3, [r2, #64] @ 0x40
|
|
8001156: 4b15 ldr r3, [pc, #84] @ (80011ac <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001158: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800115a: f003 0302 and.w r3, r3, #2
|
|
800115e: 613b str r3, [r7, #16]
|
|
8001160: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001162: 2300 movs r3, #0
|
|
8001164: 60fb str r3, [r7, #12]
|
|
8001166: 4b11 ldr r3, [pc, #68] @ (80011ac <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001168: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800116a: 4a10 ldr r2, [pc, #64] @ (80011ac <HAL_TIM_Encoder_MspInit+0x88>)
|
|
800116c: f043 0301 orr.w r3, r3, #1
|
|
8001170: 6313 str r3, [r2, #48] @ 0x30
|
|
8001172: 4b0e ldr r3, [pc, #56] @ (80011ac <HAL_TIM_Encoder_MspInit+0x88>)
|
|
8001174: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001176: f003 0301 and.w r3, r3, #1
|
|
800117a: 60fb str r3, [r7, #12]
|
|
800117c: 68fb ldr r3, [r7, #12]
|
|
/**TIM3 GPIO Configuration
|
|
PA6 ------> TIM3_CH1
|
|
PA7 ------> TIM3_CH2
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
800117e: 23c0 movs r3, #192 @ 0xc0
|
|
8001180: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001182: 2302 movs r3, #2
|
|
8001184: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001186: 2300 movs r3, #0
|
|
8001188: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800118a: 2300 movs r3, #0
|
|
800118c: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
|
|
800118e: 2302 movs r3, #2
|
|
8001190: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001192: f107 0314 add.w r3, r7, #20
|
|
8001196: 4619 mov r1, r3
|
|
8001198: 4805 ldr r0, [pc, #20] @ (80011b0 <HAL_TIM_Encoder_MspInit+0x8c>)
|
|
800119a: f001 f981 bl 80024a0 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN TIM3_MspInit 1 */
|
|
|
|
/* USER CODE END TIM3_MspInit 1 */
|
|
}
|
|
}
|
|
800119e: bf00 nop
|
|
80011a0: 3728 adds r7, #40 @ 0x28
|
|
80011a2: 46bd mov sp, r7
|
|
80011a4: bd80 pop {r7, pc}
|
|
80011a6: bf00 nop
|
|
80011a8: 40000400 .word 0x40000400
|
|
80011ac: 40023800 .word 0x40023800
|
|
80011b0: 40020000 .word 0x40020000
|
|
|
|
080011b4 <HAL_TIM_MspPostInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
|
|
{
|
|
80011b4: b580 push {r7, lr}
|
|
80011b6: b088 sub sp, #32
|
|
80011b8: af00 add r7, sp, #0
|
|
80011ba: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80011bc: f107 030c add.w r3, r7, #12
|
|
80011c0: 2200 movs r2, #0
|
|
80011c2: 601a str r2, [r3, #0]
|
|
80011c4: 605a str r2, [r3, #4]
|
|
80011c6: 609a str r2, [r3, #8]
|
|
80011c8: 60da str r2, [r3, #12]
|
|
80011ca: 611a str r2, [r3, #16]
|
|
if(timHandle->Instance==TIM2)
|
|
80011cc: 687b ldr r3, [r7, #4]
|
|
80011ce: 681b ldr r3, [r3, #0]
|
|
80011d0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80011d4: d11d bne.n 8001212 <HAL_TIM_MspPostInit+0x5e>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 0 */
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80011d6: 2300 movs r3, #0
|
|
80011d8: 60bb str r3, [r7, #8]
|
|
80011da: 4b10 ldr r3, [pc, #64] @ (800121c <HAL_TIM_MspPostInit+0x68>)
|
|
80011dc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80011de: 4a0f ldr r2, [pc, #60] @ (800121c <HAL_TIM_MspPostInit+0x68>)
|
|
80011e0: f043 0301 orr.w r3, r3, #1
|
|
80011e4: 6313 str r3, [r2, #48] @ 0x30
|
|
80011e6: 4b0d ldr r3, [pc, #52] @ (800121c <HAL_TIM_MspPostInit+0x68>)
|
|
80011e8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80011ea: f003 0301 and.w r3, r3, #1
|
|
80011ee: 60bb str r3, [r7, #8]
|
|
80011f0: 68bb ldr r3, [r7, #8]
|
|
/**TIM2 GPIO Configuration
|
|
PA5 ------> TIM2_CH1
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_5;
|
|
80011f2: 2320 movs r3, #32
|
|
80011f4: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80011f6: 2302 movs r3, #2
|
|
80011f8: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80011fa: 2300 movs r3, #0
|
|
80011fc: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80011fe: 2300 movs r3, #0
|
|
8001200: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
|
|
8001202: 2301 movs r3, #1
|
|
8001204: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001206: f107 030c add.w r3, r7, #12
|
|
800120a: 4619 mov r1, r3
|
|
800120c: 4804 ldr r0, [pc, #16] @ (8001220 <HAL_TIM_MspPostInit+0x6c>)
|
|
800120e: f001 f947 bl 80024a0 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM2_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
8001212: bf00 nop
|
|
8001214: 3720 adds r7, #32
|
|
8001216: 46bd mov sp, r7
|
|
8001218: bd80 pop {r7, pc}
|
|
800121a: bf00 nop
|
|
800121c: 40023800 .word 0x40023800
|
|
8001220: 40020000 .word 0x40020000
|
|
|
|
08001224 <MX_UART4_Init>:
|
|
DMA_HandleTypeDef hdma_usart2_rx;
|
|
DMA_HandleTypeDef hdma_usart2_tx;
|
|
|
|
/* UART4 init function */
|
|
void MX_UART4_Init(void)
|
|
{
|
|
8001224: b580 push {r7, lr}
|
|
8001226: af00 add r7, sp, #0
|
|
/* USER CODE END UART4_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART4_Init 1 */
|
|
|
|
/* USER CODE END UART4_Init 1 */
|
|
huart4.Instance = UART4;
|
|
8001228: 4b11 ldr r3, [pc, #68] @ (8001270 <MX_UART4_Init+0x4c>)
|
|
800122a: 4a12 ldr r2, [pc, #72] @ (8001274 <MX_UART4_Init+0x50>)
|
|
800122c: 601a str r2, [r3, #0]
|
|
huart4.Init.BaudRate = 115200;
|
|
800122e: 4b10 ldr r3, [pc, #64] @ (8001270 <MX_UART4_Init+0x4c>)
|
|
8001230: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8001234: 605a str r2, [r3, #4]
|
|
huart4.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8001236: 4b0e ldr r3, [pc, #56] @ (8001270 <MX_UART4_Init+0x4c>)
|
|
8001238: 2200 movs r2, #0
|
|
800123a: 609a str r2, [r3, #8]
|
|
huart4.Init.StopBits = UART_STOPBITS_1;
|
|
800123c: 4b0c ldr r3, [pc, #48] @ (8001270 <MX_UART4_Init+0x4c>)
|
|
800123e: 2200 movs r2, #0
|
|
8001240: 60da str r2, [r3, #12]
|
|
huart4.Init.Parity = UART_PARITY_NONE;
|
|
8001242: 4b0b ldr r3, [pc, #44] @ (8001270 <MX_UART4_Init+0x4c>)
|
|
8001244: 2200 movs r2, #0
|
|
8001246: 611a str r2, [r3, #16]
|
|
huart4.Init.Mode = UART_MODE_TX_RX;
|
|
8001248: 4b09 ldr r3, [pc, #36] @ (8001270 <MX_UART4_Init+0x4c>)
|
|
800124a: 220c movs r2, #12
|
|
800124c: 615a str r2, [r3, #20]
|
|
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
800124e: 4b08 ldr r3, [pc, #32] @ (8001270 <MX_UART4_Init+0x4c>)
|
|
8001250: 2200 movs r2, #0
|
|
8001252: 619a str r2, [r3, #24]
|
|
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8001254: 4b06 ldr r3, [pc, #24] @ (8001270 <MX_UART4_Init+0x4c>)
|
|
8001256: 2200 movs r2, #0
|
|
8001258: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart4) != HAL_OK)
|
|
800125a: 4805 ldr r0, [pc, #20] @ (8001270 <MX_UART4_Init+0x4c>)
|
|
800125c: f004 fbe6 bl 8005a2c <HAL_UART_Init>
|
|
8001260: 4603 mov r3, r0
|
|
8001262: 2b00 cmp r3, #0
|
|
8001264: d001 beq.n 800126a <MX_UART4_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8001266: f7ff fd9f bl 8000da8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART4_Init 2 */
|
|
|
|
/* USER CODE END UART4_Init 2 */
|
|
|
|
}
|
|
800126a: bf00 nop
|
|
800126c: bd80 pop {r7, pc}
|
|
800126e: bf00 nop
|
|
8001270: 200002fc .word 0x200002fc
|
|
8001274: 40004c00 .word 0x40004c00
|
|
|
|
08001278 <MX_UART5_Init>:
|
|
/* UART5 init function */
|
|
void MX_UART5_Init(void)
|
|
{
|
|
8001278: b580 push {r7, lr}
|
|
800127a: af00 add r7, sp, #0
|
|
/* USER CODE END UART5_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART5_Init 1 */
|
|
|
|
/* USER CODE END UART5_Init 1 */
|
|
huart5.Instance = UART5;
|
|
800127c: 4b11 ldr r3, [pc, #68] @ (80012c4 <MX_UART5_Init+0x4c>)
|
|
800127e: 4a12 ldr r2, [pc, #72] @ (80012c8 <MX_UART5_Init+0x50>)
|
|
8001280: 601a str r2, [r3, #0]
|
|
huart5.Init.BaudRate = 115200;
|
|
8001282: 4b10 ldr r3, [pc, #64] @ (80012c4 <MX_UART5_Init+0x4c>)
|
|
8001284: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8001288: 605a str r2, [r3, #4]
|
|
huart5.Init.WordLength = UART_WORDLENGTH_8B;
|
|
800128a: 4b0e ldr r3, [pc, #56] @ (80012c4 <MX_UART5_Init+0x4c>)
|
|
800128c: 2200 movs r2, #0
|
|
800128e: 609a str r2, [r3, #8]
|
|
huart5.Init.StopBits = UART_STOPBITS_1;
|
|
8001290: 4b0c ldr r3, [pc, #48] @ (80012c4 <MX_UART5_Init+0x4c>)
|
|
8001292: 2200 movs r2, #0
|
|
8001294: 60da str r2, [r3, #12]
|
|
huart5.Init.Parity = UART_PARITY_NONE;
|
|
8001296: 4b0b ldr r3, [pc, #44] @ (80012c4 <MX_UART5_Init+0x4c>)
|
|
8001298: 2200 movs r2, #0
|
|
800129a: 611a str r2, [r3, #16]
|
|
huart5.Init.Mode = UART_MODE_TX_RX;
|
|
800129c: 4b09 ldr r3, [pc, #36] @ (80012c4 <MX_UART5_Init+0x4c>)
|
|
800129e: 220c movs r2, #12
|
|
80012a0: 615a str r2, [r3, #20]
|
|
huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80012a2: 4b08 ldr r3, [pc, #32] @ (80012c4 <MX_UART5_Init+0x4c>)
|
|
80012a4: 2200 movs r2, #0
|
|
80012a6: 619a str r2, [r3, #24]
|
|
huart5.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80012a8: 4b06 ldr r3, [pc, #24] @ (80012c4 <MX_UART5_Init+0x4c>)
|
|
80012aa: 2200 movs r2, #0
|
|
80012ac: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart5) != HAL_OK)
|
|
80012ae: 4805 ldr r0, [pc, #20] @ (80012c4 <MX_UART5_Init+0x4c>)
|
|
80012b0: f004 fbbc bl 8005a2c <HAL_UART_Init>
|
|
80012b4: 4603 mov r3, r0
|
|
80012b6: 2b00 cmp r3, #0
|
|
80012b8: d001 beq.n 80012be <MX_UART5_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
80012ba: f7ff fd75 bl 8000da8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART5_Init 2 */
|
|
|
|
/* USER CODE END UART5_Init 2 */
|
|
|
|
}
|
|
80012be: bf00 nop
|
|
80012c0: bd80 pop {r7, pc}
|
|
80012c2: bf00 nop
|
|
80012c4: 20000344 .word 0x20000344
|
|
80012c8: 40005000 .word 0x40005000
|
|
|
|
080012cc <MX_USART1_UART_Init>:
|
|
/* USART1 init function */
|
|
|
|
void MX_USART1_UART_Init(void)
|
|
{
|
|
80012cc: b580 push {r7, lr}
|
|
80012ce: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
80012d0: 4b11 ldr r3, [pc, #68] @ (8001318 <MX_USART1_UART_Init+0x4c>)
|
|
80012d2: 4a12 ldr r2, [pc, #72] @ (800131c <MX_USART1_UART_Init+0x50>)
|
|
80012d4: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
80012d6: 4b10 ldr r3, [pc, #64] @ (8001318 <MX_USART1_UART_Init+0x4c>)
|
|
80012d8: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
80012dc: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
80012de: 4b0e ldr r3, [pc, #56] @ (8001318 <MX_USART1_UART_Init+0x4c>)
|
|
80012e0: 2200 movs r2, #0
|
|
80012e2: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
80012e4: 4b0c ldr r3, [pc, #48] @ (8001318 <MX_USART1_UART_Init+0x4c>)
|
|
80012e6: 2200 movs r2, #0
|
|
80012e8: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
80012ea: 4b0b ldr r3, [pc, #44] @ (8001318 <MX_USART1_UART_Init+0x4c>)
|
|
80012ec: 2200 movs r2, #0
|
|
80012ee: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
80012f0: 4b09 ldr r3, [pc, #36] @ (8001318 <MX_USART1_UART_Init+0x4c>)
|
|
80012f2: 220c movs r2, #12
|
|
80012f4: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80012f6: 4b08 ldr r3, [pc, #32] @ (8001318 <MX_USART1_UART_Init+0x4c>)
|
|
80012f8: 2200 movs r2, #0
|
|
80012fa: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80012fc: 4b06 ldr r3, [pc, #24] @ (8001318 <MX_USART1_UART_Init+0x4c>)
|
|
80012fe: 2200 movs r2, #0
|
|
8001300: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
8001302: 4805 ldr r0, [pc, #20] @ (8001318 <MX_USART1_UART_Init+0x4c>)
|
|
8001304: f004 fb92 bl 8005a2c <HAL_UART_Init>
|
|
8001308: 4603 mov r3, r0
|
|
800130a: 2b00 cmp r3, #0
|
|
800130c: d001 beq.n 8001312 <MX_USART1_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
800130e: f7ff fd4b bl 8000da8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
8001312: bf00 nop
|
|
8001314: bd80 pop {r7, pc}
|
|
8001316: bf00 nop
|
|
8001318: 2000038c .word 0x2000038c
|
|
800131c: 40011000 .word 0x40011000
|
|
|
|
08001320 <MX_USART2_UART_Init>:
|
|
/* USART2 init function */
|
|
|
|
void MX_USART2_UART_Init(void)
|
|
{
|
|
8001320: b580 push {r7, lr}
|
|
8001322: af00 add r7, sp, #0
|
|
/* USER CODE END USART2_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
|
|
|
/* USER CODE END USART2_Init 1 */
|
|
huart2.Instance = USART2;
|
|
8001324: 4b11 ldr r3, [pc, #68] @ (800136c <MX_USART2_UART_Init+0x4c>)
|
|
8001326: 4a12 ldr r2, [pc, #72] @ (8001370 <MX_USART2_UART_Init+0x50>)
|
|
8001328: 601a str r2, [r3, #0]
|
|
huart2.Init.BaudRate = 115200;
|
|
800132a: 4b10 ldr r3, [pc, #64] @ (800136c <MX_USART2_UART_Init+0x4c>)
|
|
800132c: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8001330: 605a str r2, [r3, #4]
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8001332: 4b0e ldr r3, [pc, #56] @ (800136c <MX_USART2_UART_Init+0x4c>)
|
|
8001334: 2200 movs r2, #0
|
|
8001336: 609a str r2, [r3, #8]
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
8001338: 4b0c ldr r3, [pc, #48] @ (800136c <MX_USART2_UART_Init+0x4c>)
|
|
800133a: 2200 movs r2, #0
|
|
800133c: 60da str r2, [r3, #12]
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
800133e: 4b0b ldr r3, [pc, #44] @ (800136c <MX_USART2_UART_Init+0x4c>)
|
|
8001340: 2200 movs r2, #0
|
|
8001342: 611a str r2, [r3, #16]
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
8001344: 4b09 ldr r3, [pc, #36] @ (800136c <MX_USART2_UART_Init+0x4c>)
|
|
8001346: 220c movs r2, #12
|
|
8001348: 615a str r2, [r3, #20]
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
800134a: 4b08 ldr r3, [pc, #32] @ (800136c <MX_USART2_UART_Init+0x4c>)
|
|
800134c: 2200 movs r2, #0
|
|
800134e: 619a str r2, [r3, #24]
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8001350: 4b06 ldr r3, [pc, #24] @ (800136c <MX_USART2_UART_Init+0x4c>)
|
|
8001352: 2200 movs r2, #0
|
|
8001354: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
|
8001356: 4805 ldr r0, [pc, #20] @ (800136c <MX_USART2_UART_Init+0x4c>)
|
|
8001358: f004 fb68 bl 8005a2c <HAL_UART_Init>
|
|
800135c: 4603 mov r3, r0
|
|
800135e: 2b00 cmp r3, #0
|
|
8001360: d001 beq.n 8001366 <MX_USART2_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8001362: f7ff fd21 bl 8000da8 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
|
|
|
/* USER CODE END USART2_Init 2 */
|
|
|
|
}
|
|
8001366: bf00 nop
|
|
8001368: bd80 pop {r7, pc}
|
|
800136a: bf00 nop
|
|
800136c: 200003d4 .word 0x200003d4
|
|
8001370: 40004400 .word 0x40004400
|
|
|
|
08001374 <HAL_UART_MspInit>:
|
|
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
|
|
{
|
|
8001374: b580 push {r7, lr}
|
|
8001376: b090 sub sp, #64 @ 0x40
|
|
8001378: af00 add r7, sp, #0
|
|
800137a: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800137c: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
8001380: 2200 movs r2, #0
|
|
8001382: 601a str r2, [r3, #0]
|
|
8001384: 605a str r2, [r3, #4]
|
|
8001386: 609a str r2, [r3, #8]
|
|
8001388: 60da str r2, [r3, #12]
|
|
800138a: 611a str r2, [r3, #16]
|
|
if(uartHandle->Instance==UART4)
|
|
800138c: 687b ldr r3, [r7, #4]
|
|
800138e: 681b ldr r3, [r3, #0]
|
|
8001390: 4a4a ldr r2, [pc, #296] @ (80014bc <HAL_UART_MspInit+0x148>)
|
|
8001392: 4293 cmp r3, r2
|
|
8001394: f040 80a0 bne.w 80014d8 <HAL_UART_MspInit+0x164>
|
|
{
|
|
/* USER CODE BEGIN UART4_MspInit 0 */
|
|
|
|
/* USER CODE END UART4_MspInit 0 */
|
|
/* UART4 clock enable */
|
|
__HAL_RCC_UART4_CLK_ENABLE();
|
|
8001398: 2300 movs r3, #0
|
|
800139a: 62bb str r3, [r7, #40] @ 0x28
|
|
800139c: 4b48 ldr r3, [pc, #288] @ (80014c0 <HAL_UART_MspInit+0x14c>)
|
|
800139e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80013a0: 4a47 ldr r2, [pc, #284] @ (80014c0 <HAL_UART_MspInit+0x14c>)
|
|
80013a2: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
80013a6: 6413 str r3, [r2, #64] @ 0x40
|
|
80013a8: 4b45 ldr r3, [pc, #276] @ (80014c0 <HAL_UART_MspInit+0x14c>)
|
|
80013aa: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80013ac: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
80013b0: 62bb str r3, [r7, #40] @ 0x28
|
|
80013b2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80013b4: 2300 movs r3, #0
|
|
80013b6: 627b str r3, [r7, #36] @ 0x24
|
|
80013b8: 4b41 ldr r3, [pc, #260] @ (80014c0 <HAL_UART_MspInit+0x14c>)
|
|
80013ba: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80013bc: 4a40 ldr r2, [pc, #256] @ (80014c0 <HAL_UART_MspInit+0x14c>)
|
|
80013be: f043 0301 orr.w r3, r3, #1
|
|
80013c2: 6313 str r3, [r2, #48] @ 0x30
|
|
80013c4: 4b3e ldr r3, [pc, #248] @ (80014c0 <HAL_UART_MspInit+0x14c>)
|
|
80013c6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80013c8: f003 0301 and.w r3, r3, #1
|
|
80013cc: 627b str r3, [r7, #36] @ 0x24
|
|
80013ce: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
/**UART4 GPIO Configuration
|
|
PA0-WKUP ------> UART4_TX
|
|
PA1 ------> UART4_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
|
|
80013d0: 2303 movs r3, #3
|
|
80013d2: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80013d4: 2302 movs r3, #2
|
|
80013d6: 633b str r3, [r7, #48] @ 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80013d8: 2300 movs r3, #0
|
|
80013da: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80013dc: 2303 movs r3, #3
|
|
80013de: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
|
|
80013e0: 2308 movs r3, #8
|
|
80013e2: 63fb str r3, [r7, #60] @ 0x3c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80013e4: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
80013e8: 4619 mov r1, r3
|
|
80013ea: 4836 ldr r0, [pc, #216] @ (80014c4 <HAL_UART_MspInit+0x150>)
|
|
80013ec: f001 f858 bl 80024a0 <HAL_GPIO_Init>
|
|
|
|
/* UART4 DMA Init */
|
|
/* UART4_RX Init */
|
|
hdma_uart4_rx.Instance = DMA1_Stream2;
|
|
80013f0: 4b35 ldr r3, [pc, #212] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
80013f2: 4a36 ldr r2, [pc, #216] @ (80014cc <HAL_UART_MspInit+0x158>)
|
|
80013f4: 601a str r2, [r3, #0]
|
|
hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4;
|
|
80013f6: 4b34 ldr r3, [pc, #208] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
80013f8: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
80013fc: 605a str r2, [r3, #4]
|
|
hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
80013fe: 4b32 ldr r3, [pc, #200] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
8001400: 2200 movs r2, #0
|
|
8001402: 609a str r2, [r3, #8]
|
|
hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
8001404: 4b30 ldr r3, [pc, #192] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
8001406: 2200 movs r2, #0
|
|
8001408: 60da str r2, [r3, #12]
|
|
hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE;
|
|
800140a: 4b2f ldr r3, [pc, #188] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
800140c: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001410: 611a str r2, [r3, #16]
|
|
hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
8001412: 4b2d ldr r3, [pc, #180] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
8001414: 2200 movs r2, #0
|
|
8001416: 615a str r2, [r3, #20]
|
|
hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
8001418: 4b2b ldr r3, [pc, #172] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
800141a: 2200 movs r2, #0
|
|
800141c: 619a str r2, [r3, #24]
|
|
hdma_uart4_rx.Init.Mode = DMA_NORMAL;
|
|
800141e: 4b2a ldr r3, [pc, #168] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
8001420: 2200 movs r2, #0
|
|
8001422: 61da str r2, [r3, #28]
|
|
hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW;
|
|
8001424: 4b28 ldr r3, [pc, #160] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
8001426: 2200 movs r2, #0
|
|
8001428: 621a str r2, [r3, #32]
|
|
hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
800142a: 4b27 ldr r3, [pc, #156] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
800142c: 2200 movs r2, #0
|
|
800142e: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK)
|
|
8001430: 4825 ldr r0, [pc, #148] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
8001432: f000 fc33 bl 8001c9c <HAL_DMA_Init>
|
|
8001436: 4603 mov r3, r0
|
|
8001438: 2b00 cmp r3, #0
|
|
800143a: d001 beq.n 8001440 <HAL_UART_MspInit+0xcc>
|
|
{
|
|
Error_Handler();
|
|
800143c: f7ff fcb4 bl 8000da8 <Error_Handler>
|
|
}
|
|
|
|
__HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx);
|
|
8001440: 687b ldr r3, [r7, #4]
|
|
8001442: 4a21 ldr r2, [pc, #132] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
8001444: 63da str r2, [r3, #60] @ 0x3c
|
|
8001446: 4a20 ldr r2, [pc, #128] @ (80014c8 <HAL_UART_MspInit+0x154>)
|
|
8001448: 687b ldr r3, [r7, #4]
|
|
800144a: 6393 str r3, [r2, #56] @ 0x38
|
|
|
|
/* UART4_TX Init */
|
|
hdma_uart4_tx.Instance = DMA1_Stream4;
|
|
800144c: 4b20 ldr r3, [pc, #128] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
800144e: 4a21 ldr r2, [pc, #132] @ (80014d4 <HAL_UART_MspInit+0x160>)
|
|
8001450: 601a str r2, [r3, #0]
|
|
hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4;
|
|
8001452: 4b1f ldr r3, [pc, #124] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
8001454: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
8001458: 605a str r2, [r3, #4]
|
|
hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
800145a: 4b1d ldr r3, [pc, #116] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
800145c: 2240 movs r2, #64 @ 0x40
|
|
800145e: 609a str r2, [r3, #8]
|
|
hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
8001460: 4b1b ldr r3, [pc, #108] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
8001462: 2200 movs r2, #0
|
|
8001464: 60da str r2, [r3, #12]
|
|
hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8001466: 4b1a ldr r3, [pc, #104] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
8001468: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
800146c: 611a str r2, [r3, #16]
|
|
hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
800146e: 4b18 ldr r3, [pc, #96] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
8001470: 2200 movs r2, #0
|
|
8001472: 615a str r2, [r3, #20]
|
|
hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
8001474: 4b16 ldr r3, [pc, #88] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
8001476: 2200 movs r2, #0
|
|
8001478: 619a str r2, [r3, #24]
|
|
hdma_uart4_tx.Init.Mode = DMA_NORMAL;
|
|
800147a: 4b15 ldr r3, [pc, #84] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
800147c: 2200 movs r2, #0
|
|
800147e: 61da str r2, [r3, #28]
|
|
hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW;
|
|
8001480: 4b13 ldr r3, [pc, #76] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
8001482: 2200 movs r2, #0
|
|
8001484: 621a str r2, [r3, #32]
|
|
hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
8001486: 4b12 ldr r3, [pc, #72] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
8001488: 2200 movs r2, #0
|
|
800148a: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK)
|
|
800148c: 4810 ldr r0, [pc, #64] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
800148e: f000 fc05 bl 8001c9c <HAL_DMA_Init>
|
|
8001492: 4603 mov r3, r0
|
|
8001494: 2b00 cmp r3, #0
|
|
8001496: d001 beq.n 800149c <HAL_UART_MspInit+0x128>
|
|
{
|
|
Error_Handler();
|
|
8001498: f7ff fc86 bl 8000da8 <Error_Handler>
|
|
}
|
|
|
|
__HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx);
|
|
800149c: 687b ldr r3, [r7, #4]
|
|
800149e: 4a0c ldr r2, [pc, #48] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
80014a0: 639a str r2, [r3, #56] @ 0x38
|
|
80014a2: 4a0b ldr r2, [pc, #44] @ (80014d0 <HAL_UART_MspInit+0x15c>)
|
|
80014a4: 687b ldr r3, [r7, #4]
|
|
80014a6: 6393 str r3, [r2, #56] @ 0x38
|
|
|
|
/* UART4 interrupt Init */
|
|
HAL_NVIC_SetPriority(UART4_IRQn, 0, 0);
|
|
80014a8: 2200 movs r2, #0
|
|
80014aa: 2100 movs r1, #0
|
|
80014ac: 2034 movs r0, #52 @ 0x34
|
|
80014ae: f000 fbbe bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(UART4_IRQn);
|
|
80014b2: 2034 movs r0, #52 @ 0x34
|
|
80014b4: f000 fbd7 bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
HAL_NVIC_EnableIRQ(USART2_IRQn);
|
|
/* USER CODE BEGIN USART2_MspInit 1 */
|
|
|
|
/* USER CODE END USART2_MspInit 1 */
|
|
}
|
|
}
|
|
80014b8: e202 b.n 80018c0 <HAL_UART_MspInit+0x54c>
|
|
80014ba: bf00 nop
|
|
80014bc: 40004c00 .word 0x40004c00
|
|
80014c0: 40023800 .word 0x40023800
|
|
80014c4: 40020000 .word 0x40020000
|
|
80014c8: 2000041c .word 0x2000041c
|
|
80014cc: 40026040 .word 0x40026040
|
|
80014d0: 2000047c .word 0x2000047c
|
|
80014d4: 40026070 .word 0x40026070
|
|
else if(uartHandle->Instance==UART5)
|
|
80014d8: 687b ldr r3, [r7, #4]
|
|
80014da: 681b ldr r3, [r3, #0]
|
|
80014dc: 4a59 ldr r2, [pc, #356] @ (8001644 <HAL_UART_MspInit+0x2d0>)
|
|
80014de: 4293 cmp r3, r2
|
|
80014e0: f040 80c0 bne.w 8001664 <HAL_UART_MspInit+0x2f0>
|
|
__HAL_RCC_UART5_CLK_ENABLE();
|
|
80014e4: 2300 movs r3, #0
|
|
80014e6: 623b str r3, [r7, #32]
|
|
80014e8: 4b57 ldr r3, [pc, #348] @ (8001648 <HAL_UART_MspInit+0x2d4>)
|
|
80014ea: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80014ec: 4a56 ldr r2, [pc, #344] @ (8001648 <HAL_UART_MspInit+0x2d4>)
|
|
80014ee: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
80014f2: 6413 str r3, [r2, #64] @ 0x40
|
|
80014f4: 4b54 ldr r3, [pc, #336] @ (8001648 <HAL_UART_MspInit+0x2d4>)
|
|
80014f6: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80014f8: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
80014fc: 623b str r3, [r7, #32]
|
|
80014fe: 6a3b ldr r3, [r7, #32]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8001500: 2300 movs r3, #0
|
|
8001502: 61fb str r3, [r7, #28]
|
|
8001504: 4b50 ldr r3, [pc, #320] @ (8001648 <HAL_UART_MspInit+0x2d4>)
|
|
8001506: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001508: 4a4f ldr r2, [pc, #316] @ (8001648 <HAL_UART_MspInit+0x2d4>)
|
|
800150a: f043 0304 orr.w r3, r3, #4
|
|
800150e: 6313 str r3, [r2, #48] @ 0x30
|
|
8001510: 4b4d ldr r3, [pc, #308] @ (8001648 <HAL_UART_MspInit+0x2d4>)
|
|
8001512: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001514: f003 0304 and.w r3, r3, #4
|
|
8001518: 61fb str r3, [r7, #28]
|
|
800151a: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
800151c: 2300 movs r3, #0
|
|
800151e: 61bb str r3, [r7, #24]
|
|
8001520: 4b49 ldr r3, [pc, #292] @ (8001648 <HAL_UART_MspInit+0x2d4>)
|
|
8001522: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001524: 4a48 ldr r2, [pc, #288] @ (8001648 <HAL_UART_MspInit+0x2d4>)
|
|
8001526: f043 0308 orr.w r3, r3, #8
|
|
800152a: 6313 str r3, [r2, #48] @ 0x30
|
|
800152c: 4b46 ldr r3, [pc, #280] @ (8001648 <HAL_UART_MspInit+0x2d4>)
|
|
800152e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001530: f003 0308 and.w r3, r3, #8
|
|
8001534: 61bb str r3, [r7, #24]
|
|
8001536: 69bb ldr r3, [r7, #24]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_12;
|
|
8001538: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
800153c: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800153e: 2302 movs r3, #2
|
|
8001540: 633b str r3, [r7, #48] @ 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001542: 2300 movs r3, #0
|
|
8001544: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001546: 2303 movs r3, #3
|
|
8001548: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
|
|
800154a: 2308 movs r3, #8
|
|
800154c: 63fb str r3, [r7, #60] @ 0x3c
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
800154e: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
8001552: 4619 mov r1, r3
|
|
8001554: 483d ldr r0, [pc, #244] @ (800164c <HAL_UART_MspInit+0x2d8>)
|
|
8001556: f000 ffa3 bl 80024a0 <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
800155a: 2304 movs r3, #4
|
|
800155c: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800155e: 2302 movs r3, #2
|
|
8001560: 633b str r3, [r7, #48] @ 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001562: 2300 movs r3, #0
|
|
8001564: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001566: 2303 movs r3, #3
|
|
8001568: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
|
|
800156a: 2308 movs r3, #8
|
|
800156c: 63fb str r3, [r7, #60] @ 0x3c
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
800156e: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
8001572: 4619 mov r1, r3
|
|
8001574: 4836 ldr r0, [pc, #216] @ (8001650 <HAL_UART_MspInit+0x2dc>)
|
|
8001576: f000 ff93 bl 80024a0 <HAL_GPIO_Init>
|
|
hdma_uart5_rx.Instance = DMA1_Stream0;
|
|
800157a: 4b36 ldr r3, [pc, #216] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
800157c: 4a36 ldr r2, [pc, #216] @ (8001658 <HAL_UART_MspInit+0x2e4>)
|
|
800157e: 601a str r2, [r3, #0]
|
|
hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4;
|
|
8001580: 4b34 ldr r3, [pc, #208] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
8001582: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
8001586: 605a str r2, [r3, #4]
|
|
hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
8001588: 4b32 ldr r3, [pc, #200] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
800158a: 2200 movs r2, #0
|
|
800158c: 609a str r2, [r3, #8]
|
|
hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
800158e: 4b31 ldr r3, [pc, #196] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
8001590: 2200 movs r2, #0
|
|
8001592: 60da str r2, [r3, #12]
|
|
hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8001594: 4b2f ldr r3, [pc, #188] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
8001596: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
800159a: 611a str r2, [r3, #16]
|
|
hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
800159c: 4b2d ldr r3, [pc, #180] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
800159e: 2200 movs r2, #0
|
|
80015a0: 615a str r2, [r3, #20]
|
|
hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
80015a2: 4b2c ldr r3, [pc, #176] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
80015a4: 2200 movs r2, #0
|
|
80015a6: 619a str r2, [r3, #24]
|
|
hdma_uart5_rx.Init.Mode = DMA_NORMAL;
|
|
80015a8: 4b2a ldr r3, [pc, #168] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
80015aa: 2200 movs r2, #0
|
|
80015ac: 61da str r2, [r3, #28]
|
|
hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW;
|
|
80015ae: 4b29 ldr r3, [pc, #164] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
80015b0: 2200 movs r2, #0
|
|
80015b2: 621a str r2, [r3, #32]
|
|
hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
80015b4: 4b27 ldr r3, [pc, #156] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
80015b6: 2200 movs r2, #0
|
|
80015b8: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK)
|
|
80015ba: 4826 ldr r0, [pc, #152] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
80015bc: f000 fb6e bl 8001c9c <HAL_DMA_Init>
|
|
80015c0: 4603 mov r3, r0
|
|
80015c2: 2b00 cmp r3, #0
|
|
80015c4: d001 beq.n 80015ca <HAL_UART_MspInit+0x256>
|
|
Error_Handler();
|
|
80015c6: f7ff fbef bl 8000da8 <Error_Handler>
|
|
__HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx);
|
|
80015ca: 687b ldr r3, [r7, #4]
|
|
80015cc: 4a21 ldr r2, [pc, #132] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
80015ce: 63da str r2, [r3, #60] @ 0x3c
|
|
80015d0: 4a20 ldr r2, [pc, #128] @ (8001654 <HAL_UART_MspInit+0x2e0>)
|
|
80015d2: 687b ldr r3, [r7, #4]
|
|
80015d4: 6393 str r3, [r2, #56] @ 0x38
|
|
hdma_uart5_tx.Instance = DMA1_Stream7;
|
|
80015d6: 4b21 ldr r3, [pc, #132] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
80015d8: 4a21 ldr r2, [pc, #132] @ (8001660 <HAL_UART_MspInit+0x2ec>)
|
|
80015da: 601a str r2, [r3, #0]
|
|
hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4;
|
|
80015dc: 4b1f ldr r3, [pc, #124] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
80015de: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
80015e2: 605a str r2, [r3, #4]
|
|
hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
80015e4: 4b1d ldr r3, [pc, #116] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
80015e6: 2240 movs r2, #64 @ 0x40
|
|
80015e8: 609a str r2, [r3, #8]
|
|
hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
80015ea: 4b1c ldr r3, [pc, #112] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
80015ec: 2200 movs r2, #0
|
|
80015ee: 60da str r2, [r3, #12]
|
|
hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
80015f0: 4b1a ldr r3, [pc, #104] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
80015f2: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
80015f6: 611a str r2, [r3, #16]
|
|
hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
80015f8: 4b18 ldr r3, [pc, #96] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
80015fa: 2200 movs r2, #0
|
|
80015fc: 615a str r2, [r3, #20]
|
|
hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
80015fe: 4b17 ldr r3, [pc, #92] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
8001600: 2200 movs r2, #0
|
|
8001602: 619a str r2, [r3, #24]
|
|
hdma_uart5_tx.Init.Mode = DMA_NORMAL;
|
|
8001604: 4b15 ldr r3, [pc, #84] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
8001606: 2200 movs r2, #0
|
|
8001608: 61da str r2, [r3, #28]
|
|
hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW;
|
|
800160a: 4b14 ldr r3, [pc, #80] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
800160c: 2200 movs r2, #0
|
|
800160e: 621a str r2, [r3, #32]
|
|
hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
8001610: 4b12 ldr r3, [pc, #72] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
8001612: 2200 movs r2, #0
|
|
8001614: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK)
|
|
8001616: 4811 ldr r0, [pc, #68] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
8001618: f000 fb40 bl 8001c9c <HAL_DMA_Init>
|
|
800161c: 4603 mov r3, r0
|
|
800161e: 2b00 cmp r3, #0
|
|
8001620: d001 beq.n 8001626 <HAL_UART_MspInit+0x2b2>
|
|
Error_Handler();
|
|
8001622: f7ff fbc1 bl 8000da8 <Error_Handler>
|
|
__HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx);
|
|
8001626: 687b ldr r3, [r7, #4]
|
|
8001628: 4a0c ldr r2, [pc, #48] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
800162a: 639a str r2, [r3, #56] @ 0x38
|
|
800162c: 4a0b ldr r2, [pc, #44] @ (800165c <HAL_UART_MspInit+0x2e8>)
|
|
800162e: 687b ldr r3, [r7, #4]
|
|
8001630: 6393 str r3, [r2, #56] @ 0x38
|
|
HAL_NVIC_SetPriority(UART5_IRQn, 0, 0);
|
|
8001632: 2200 movs r2, #0
|
|
8001634: 2100 movs r1, #0
|
|
8001636: 2035 movs r0, #53 @ 0x35
|
|
8001638: f000 faf9 bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(UART5_IRQn);
|
|
800163c: 2035 movs r0, #53 @ 0x35
|
|
800163e: f000 fb12 bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
}
|
|
8001642: e13d b.n 80018c0 <HAL_UART_MspInit+0x54c>
|
|
8001644: 40005000 .word 0x40005000
|
|
8001648: 40023800 .word 0x40023800
|
|
800164c: 40020800 .word 0x40020800
|
|
8001650: 40020c00 .word 0x40020c00
|
|
8001654: 200004dc .word 0x200004dc
|
|
8001658: 40026010 .word 0x40026010
|
|
800165c: 2000053c .word 0x2000053c
|
|
8001660: 400260b8 .word 0x400260b8
|
|
else if(uartHandle->Instance==USART1)
|
|
8001664: 687b ldr r3, [r7, #4]
|
|
8001666: 681b ldr r3, [r3, #0]
|
|
8001668: 4a97 ldr r2, [pc, #604] @ (80018c8 <HAL_UART_MspInit+0x554>)
|
|
800166a: 4293 cmp r3, r2
|
|
800166c: f040 8092 bne.w 8001794 <HAL_UART_MspInit+0x420>
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8001670: 2300 movs r3, #0
|
|
8001672: 617b str r3, [r7, #20]
|
|
8001674: 4b95 ldr r3, [pc, #596] @ (80018cc <HAL_UART_MspInit+0x558>)
|
|
8001676: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001678: 4a94 ldr r2, [pc, #592] @ (80018cc <HAL_UART_MspInit+0x558>)
|
|
800167a: f043 0310 orr.w r3, r3, #16
|
|
800167e: 6453 str r3, [r2, #68] @ 0x44
|
|
8001680: 4b92 ldr r3, [pc, #584] @ (80018cc <HAL_UART_MspInit+0x558>)
|
|
8001682: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001684: f003 0310 and.w r3, r3, #16
|
|
8001688: 617b str r3, [r7, #20]
|
|
800168a: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800168c: 2300 movs r3, #0
|
|
800168e: 613b str r3, [r7, #16]
|
|
8001690: 4b8e ldr r3, [pc, #568] @ (80018cc <HAL_UART_MspInit+0x558>)
|
|
8001692: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001694: 4a8d ldr r2, [pc, #564] @ (80018cc <HAL_UART_MspInit+0x558>)
|
|
8001696: f043 0301 orr.w r3, r3, #1
|
|
800169a: 6313 str r3, [r2, #48] @ 0x30
|
|
800169c: 4b8b ldr r3, [pc, #556] @ (80018cc <HAL_UART_MspInit+0x558>)
|
|
800169e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80016a0: f003 0301 and.w r3, r3, #1
|
|
80016a4: 613b str r3, [r7, #16]
|
|
80016a6: 693b ldr r3, [r7, #16]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
|
|
80016a8: f44f 63c0 mov.w r3, #1536 @ 0x600
|
|
80016ac: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80016ae: 2302 movs r3, #2
|
|
80016b0: 633b str r3, [r7, #48] @ 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80016b2: 2300 movs r3, #0
|
|
80016b4: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80016b6: 2303 movs r3, #3
|
|
80016b8: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
80016ba: 2307 movs r3, #7
|
|
80016bc: 63fb str r3, [r7, #60] @ 0x3c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80016be: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
80016c2: 4619 mov r1, r3
|
|
80016c4: 4882 ldr r0, [pc, #520] @ (80018d0 <HAL_UART_MspInit+0x55c>)
|
|
80016c6: f000 feeb bl 80024a0 <HAL_GPIO_Init>
|
|
hdma_usart1_rx.Instance = DMA2_Stream2;
|
|
80016ca: 4b82 ldr r3, [pc, #520] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
80016cc: 4a82 ldr r2, [pc, #520] @ (80018d8 <HAL_UART_MspInit+0x564>)
|
|
80016ce: 601a str r2, [r3, #0]
|
|
hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4;
|
|
80016d0: 4b80 ldr r3, [pc, #512] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
80016d2: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
80016d6: 605a str r2, [r3, #4]
|
|
hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
80016d8: 4b7e ldr r3, [pc, #504] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
80016da: 2200 movs r2, #0
|
|
80016dc: 609a str r2, [r3, #8]
|
|
hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
80016de: 4b7d ldr r3, [pc, #500] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
80016e0: 2200 movs r2, #0
|
|
80016e2: 60da str r2, [r3, #12]
|
|
hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
|
|
80016e4: 4b7b ldr r3, [pc, #492] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
80016e6: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
80016ea: 611a str r2, [r3, #16]
|
|
hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
80016ec: 4b79 ldr r3, [pc, #484] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
80016ee: 2200 movs r2, #0
|
|
80016f0: 615a str r2, [r3, #20]
|
|
hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
80016f2: 4b78 ldr r3, [pc, #480] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
80016f4: 2200 movs r2, #0
|
|
80016f6: 619a str r2, [r3, #24]
|
|
hdma_usart1_rx.Init.Mode = DMA_NORMAL;
|
|
80016f8: 4b76 ldr r3, [pc, #472] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
80016fa: 2200 movs r2, #0
|
|
80016fc: 61da str r2, [r3, #28]
|
|
hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
|
|
80016fe: 4b75 ldr r3, [pc, #468] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
8001700: 2200 movs r2, #0
|
|
8001702: 621a str r2, [r3, #32]
|
|
hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
8001704: 4b73 ldr r3, [pc, #460] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
8001706: 2200 movs r2, #0
|
|
8001708: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
|
|
800170a: 4872 ldr r0, [pc, #456] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
800170c: f000 fac6 bl 8001c9c <HAL_DMA_Init>
|
|
8001710: 4603 mov r3, r0
|
|
8001712: 2b00 cmp r3, #0
|
|
8001714: d001 beq.n 800171a <HAL_UART_MspInit+0x3a6>
|
|
Error_Handler();
|
|
8001716: f7ff fb47 bl 8000da8 <Error_Handler>
|
|
__HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx);
|
|
800171a: 687b ldr r3, [r7, #4]
|
|
800171c: 4a6d ldr r2, [pc, #436] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
800171e: 63da str r2, [r3, #60] @ 0x3c
|
|
8001720: 4a6c ldr r2, [pc, #432] @ (80018d4 <HAL_UART_MspInit+0x560>)
|
|
8001722: 687b ldr r3, [r7, #4]
|
|
8001724: 6393 str r3, [r2, #56] @ 0x38
|
|
hdma_usart1_tx.Instance = DMA2_Stream7;
|
|
8001726: 4b6d ldr r3, [pc, #436] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
8001728: 4a6d ldr r2, [pc, #436] @ (80018e0 <HAL_UART_MspInit+0x56c>)
|
|
800172a: 601a str r2, [r3, #0]
|
|
hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4;
|
|
800172c: 4b6b ldr r3, [pc, #428] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
800172e: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
8001732: 605a str r2, [r3, #4]
|
|
hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
8001734: 4b69 ldr r3, [pc, #420] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
8001736: 2240 movs r2, #64 @ 0x40
|
|
8001738: 609a str r2, [r3, #8]
|
|
hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
800173a: 4b68 ldr r3, [pc, #416] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
800173c: 2200 movs r2, #0
|
|
800173e: 60da str r2, [r3, #12]
|
|
hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8001740: 4b66 ldr r3, [pc, #408] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
8001742: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001746: 611a str r2, [r3, #16]
|
|
hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
8001748: 4b64 ldr r3, [pc, #400] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
800174a: 2200 movs r2, #0
|
|
800174c: 615a str r2, [r3, #20]
|
|
hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
800174e: 4b63 ldr r3, [pc, #396] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
8001750: 2200 movs r2, #0
|
|
8001752: 619a str r2, [r3, #24]
|
|
hdma_usart1_tx.Init.Mode = DMA_NORMAL;
|
|
8001754: 4b61 ldr r3, [pc, #388] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
8001756: 2200 movs r2, #0
|
|
8001758: 61da str r2, [r3, #28]
|
|
hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
|
|
800175a: 4b60 ldr r3, [pc, #384] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
800175c: 2200 movs r2, #0
|
|
800175e: 621a str r2, [r3, #32]
|
|
hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
8001760: 4b5e ldr r3, [pc, #376] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
8001762: 2200 movs r2, #0
|
|
8001764: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
|
|
8001766: 485d ldr r0, [pc, #372] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
8001768: f000 fa98 bl 8001c9c <HAL_DMA_Init>
|
|
800176c: 4603 mov r3, r0
|
|
800176e: 2b00 cmp r3, #0
|
|
8001770: d001 beq.n 8001776 <HAL_UART_MspInit+0x402>
|
|
Error_Handler();
|
|
8001772: f7ff fb19 bl 8000da8 <Error_Handler>
|
|
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx);
|
|
8001776: 687b ldr r3, [r7, #4]
|
|
8001778: 4a58 ldr r2, [pc, #352] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
800177a: 639a str r2, [r3, #56] @ 0x38
|
|
800177c: 4a57 ldr r2, [pc, #348] @ (80018dc <HAL_UART_MspInit+0x568>)
|
|
800177e: 687b ldr r3, [r7, #4]
|
|
8001780: 6393 str r3, [r2, #56] @ 0x38
|
|
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
|
|
8001782: 2200 movs r2, #0
|
|
8001784: 2100 movs r1, #0
|
|
8001786: 2025 movs r0, #37 @ 0x25
|
|
8001788: f000 fa51 bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USART1_IRQn);
|
|
800178c: 2025 movs r0, #37 @ 0x25
|
|
800178e: f000 fa6a bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
}
|
|
8001792: e095 b.n 80018c0 <HAL_UART_MspInit+0x54c>
|
|
else if(uartHandle->Instance==USART2)
|
|
8001794: 687b ldr r3, [r7, #4]
|
|
8001796: 681b ldr r3, [r3, #0]
|
|
8001798: 4a52 ldr r2, [pc, #328] @ (80018e4 <HAL_UART_MspInit+0x570>)
|
|
800179a: 4293 cmp r3, r2
|
|
800179c: f040 8090 bne.w 80018c0 <HAL_UART_MspInit+0x54c>
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
80017a0: 2300 movs r3, #0
|
|
80017a2: 60fb str r3, [r7, #12]
|
|
80017a4: 4b49 ldr r3, [pc, #292] @ (80018cc <HAL_UART_MspInit+0x558>)
|
|
80017a6: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80017a8: 4a48 ldr r2, [pc, #288] @ (80018cc <HAL_UART_MspInit+0x558>)
|
|
80017aa: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80017ae: 6413 str r3, [r2, #64] @ 0x40
|
|
80017b0: 4b46 ldr r3, [pc, #280] @ (80018cc <HAL_UART_MspInit+0x558>)
|
|
80017b2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80017b4: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80017b8: 60fb str r3, [r7, #12]
|
|
80017ba: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80017bc: 2300 movs r3, #0
|
|
80017be: 60bb str r3, [r7, #8]
|
|
80017c0: 4b42 ldr r3, [pc, #264] @ (80018cc <HAL_UART_MspInit+0x558>)
|
|
80017c2: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80017c4: 4a41 ldr r2, [pc, #260] @ (80018cc <HAL_UART_MspInit+0x558>)
|
|
80017c6: f043 0301 orr.w r3, r3, #1
|
|
80017ca: 6313 str r3, [r2, #48] @ 0x30
|
|
80017cc: 4b3f ldr r3, [pc, #252] @ (80018cc <HAL_UART_MspInit+0x558>)
|
|
80017ce: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80017d0: f003 0301 and.w r3, r3, #1
|
|
80017d4: 60bb str r3, [r7, #8]
|
|
80017d6: 68bb ldr r3, [r7, #8]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
|
|
80017d8: 230c movs r3, #12
|
|
80017da: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80017dc: 2302 movs r3, #2
|
|
80017de: 633b str r3, [r7, #48] @ 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80017e0: 2300 movs r3, #0
|
|
80017e2: 637b str r3, [r7, #52] @ 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80017e4: 2303 movs r3, #3
|
|
80017e6: 63bb str r3, [r7, #56] @ 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
|
80017e8: 2307 movs r3, #7
|
|
80017ea: 63fb str r3, [r7, #60] @ 0x3c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80017ec: f107 032c add.w r3, r7, #44 @ 0x2c
|
|
80017f0: 4619 mov r1, r3
|
|
80017f2: 4837 ldr r0, [pc, #220] @ (80018d0 <HAL_UART_MspInit+0x55c>)
|
|
80017f4: f000 fe54 bl 80024a0 <HAL_GPIO_Init>
|
|
hdma_usart2_rx.Instance = DMA1_Stream5;
|
|
80017f8: 4b3b ldr r3, [pc, #236] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
80017fa: 4a3c ldr r2, [pc, #240] @ (80018ec <HAL_UART_MspInit+0x578>)
|
|
80017fc: 601a str r2, [r3, #0]
|
|
hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4;
|
|
80017fe: 4b3a ldr r3, [pc, #232] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
8001800: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
8001804: 605a str r2, [r3, #4]
|
|
hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
8001806: 4b38 ldr r3, [pc, #224] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
8001808: 2200 movs r2, #0
|
|
800180a: 609a str r2, [r3, #8]
|
|
hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
800180c: 4b36 ldr r3, [pc, #216] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
800180e: 2200 movs r2, #0
|
|
8001810: 60da str r2, [r3, #12]
|
|
hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8001812: 4b35 ldr r3, [pc, #212] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
8001814: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001818: 611a str r2, [r3, #16]
|
|
hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
800181a: 4b33 ldr r3, [pc, #204] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
800181c: 2200 movs r2, #0
|
|
800181e: 615a str r2, [r3, #20]
|
|
hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
8001820: 4b31 ldr r3, [pc, #196] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
8001822: 2200 movs r2, #0
|
|
8001824: 619a str r2, [r3, #24]
|
|
hdma_usart2_rx.Init.Mode = DMA_NORMAL;
|
|
8001826: 4b30 ldr r3, [pc, #192] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
8001828: 2200 movs r2, #0
|
|
800182a: 61da str r2, [r3, #28]
|
|
hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW;
|
|
800182c: 4b2e ldr r3, [pc, #184] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
800182e: 2200 movs r2, #0
|
|
8001830: 621a str r2, [r3, #32]
|
|
hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
8001832: 4b2d ldr r3, [pc, #180] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
8001834: 2200 movs r2, #0
|
|
8001836: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
|
|
8001838: 482b ldr r0, [pc, #172] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
800183a: f000 fa2f bl 8001c9c <HAL_DMA_Init>
|
|
800183e: 4603 mov r3, r0
|
|
8001840: 2b00 cmp r3, #0
|
|
8001842: d001 beq.n 8001848 <HAL_UART_MspInit+0x4d4>
|
|
Error_Handler();
|
|
8001844: f7ff fab0 bl 8000da8 <Error_Handler>
|
|
__HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx);
|
|
8001848: 687b ldr r3, [r7, #4]
|
|
800184a: 4a27 ldr r2, [pc, #156] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
800184c: 63da str r2, [r3, #60] @ 0x3c
|
|
800184e: 4a26 ldr r2, [pc, #152] @ (80018e8 <HAL_UART_MspInit+0x574>)
|
|
8001850: 687b ldr r3, [r7, #4]
|
|
8001852: 6393 str r3, [r2, #56] @ 0x38
|
|
hdma_usart2_tx.Instance = DMA1_Stream6;
|
|
8001854: 4b26 ldr r3, [pc, #152] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
8001856: 4a27 ldr r2, [pc, #156] @ (80018f4 <HAL_UART_MspInit+0x580>)
|
|
8001858: 601a str r2, [r3, #0]
|
|
hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4;
|
|
800185a: 4b25 ldr r3, [pc, #148] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
800185c: f04f 6200 mov.w r2, #134217728 @ 0x8000000
|
|
8001860: 605a str r2, [r3, #4]
|
|
hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
8001862: 4b23 ldr r3, [pc, #140] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
8001864: 2240 movs r2, #64 @ 0x40
|
|
8001866: 609a str r2, [r3, #8]
|
|
hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
8001868: 4b21 ldr r3, [pc, #132] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
800186a: 2200 movs r2, #0
|
|
800186c: 60da str r2, [r3, #12]
|
|
hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
800186e: 4b20 ldr r3, [pc, #128] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
8001870: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001874: 611a str r2, [r3, #16]
|
|
hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
8001876: 4b1e ldr r3, [pc, #120] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
8001878: 2200 movs r2, #0
|
|
800187a: 615a str r2, [r3, #20]
|
|
hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
800187c: 4b1c ldr r3, [pc, #112] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
800187e: 2200 movs r2, #0
|
|
8001880: 619a str r2, [r3, #24]
|
|
hdma_usart2_tx.Init.Mode = DMA_NORMAL;
|
|
8001882: 4b1b ldr r3, [pc, #108] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
8001884: 2200 movs r2, #0
|
|
8001886: 61da str r2, [r3, #28]
|
|
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW;
|
|
8001888: 4b19 ldr r3, [pc, #100] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
800188a: 2200 movs r2, #0
|
|
800188c: 621a str r2, [r3, #32]
|
|
hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
800188e: 4b18 ldr r3, [pc, #96] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
8001890: 2200 movs r2, #0
|
|
8001892: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
|
|
8001894: 4816 ldr r0, [pc, #88] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
8001896: f000 fa01 bl 8001c9c <HAL_DMA_Init>
|
|
800189a: 4603 mov r3, r0
|
|
800189c: 2b00 cmp r3, #0
|
|
800189e: d001 beq.n 80018a4 <HAL_UART_MspInit+0x530>
|
|
Error_Handler();
|
|
80018a0: f7ff fa82 bl 8000da8 <Error_Handler>
|
|
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx);
|
|
80018a4: 687b ldr r3, [r7, #4]
|
|
80018a6: 4a12 ldr r2, [pc, #72] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
80018a8: 639a str r2, [r3, #56] @ 0x38
|
|
80018aa: 4a11 ldr r2, [pc, #68] @ (80018f0 <HAL_UART_MspInit+0x57c>)
|
|
80018ac: 687b ldr r3, [r7, #4]
|
|
80018ae: 6393 str r3, [r2, #56] @ 0x38
|
|
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
|
|
80018b0: 2200 movs r2, #0
|
|
80018b2: 2100 movs r1, #0
|
|
80018b4: 2026 movs r0, #38 @ 0x26
|
|
80018b6: f000 f9ba bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USART2_IRQn);
|
|
80018ba: 2026 movs r0, #38 @ 0x26
|
|
80018bc: f000 f9d3 bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
}
|
|
80018c0: bf00 nop
|
|
80018c2: 3740 adds r7, #64 @ 0x40
|
|
80018c4: 46bd mov sp, r7
|
|
80018c6: bd80 pop {r7, pc}
|
|
80018c8: 40011000 .word 0x40011000
|
|
80018cc: 40023800 .word 0x40023800
|
|
80018d0: 40020000 .word 0x40020000
|
|
80018d4: 2000059c .word 0x2000059c
|
|
80018d8: 40026440 .word 0x40026440
|
|
80018dc: 200005fc .word 0x200005fc
|
|
80018e0: 400264b8 .word 0x400264b8
|
|
80018e4: 40004400 .word 0x40004400
|
|
80018e8: 2000065c .word 0x2000065c
|
|
80018ec: 40026088 .word 0x40026088
|
|
80018f0: 200006bc .word 0x200006bc
|
|
80018f4: 400260a0 .word 0x400260a0
|
|
|
|
080018f8 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* set stack pointer */
|
|
80018f8: f8df d034 ldr.w sp, [pc, #52] @ 8001930 <LoopFillZerobss+0xe>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
80018fc: f7ff fb34 bl 8000f68 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8001900: 480c ldr r0, [pc, #48] @ (8001934 <LoopFillZerobss+0x12>)
|
|
ldr r1, =_edata
|
|
8001902: 490d ldr r1, [pc, #52] @ (8001938 <LoopFillZerobss+0x16>)
|
|
ldr r2, =_sidata
|
|
8001904: 4a0d ldr r2, [pc, #52] @ (800193c <LoopFillZerobss+0x1a>)
|
|
movs r3, #0
|
|
8001906: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
8001908: e002 b.n 8001910 <LoopCopyDataInit>
|
|
|
|
0800190a <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
800190a: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
800190c: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
800190e: 3304 adds r3, #4
|
|
|
|
08001910 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8001910: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8001912: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8001914: d3f9 bcc.n 800190a <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
8001916: 4a0a ldr r2, [pc, #40] @ (8001940 <LoopFillZerobss+0x1e>)
|
|
ldr r4, =_ebss
|
|
8001918: 4c0a ldr r4, [pc, #40] @ (8001944 <LoopFillZerobss+0x22>)
|
|
movs r3, #0
|
|
800191a: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
800191c: e001 b.n 8001922 <LoopFillZerobss>
|
|
|
|
0800191e <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
800191e: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8001920: 3204 adds r2, #4
|
|
|
|
08001922 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8001922: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8001924: d3fb bcc.n 800191e <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8001926: f009 f807 bl 800a938 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
800192a: f7fe ff7d bl 8000828 <main>
|
|
bx lr
|
|
800192e: 4770 bx lr
|
|
ldr sp, =_estack /* set stack pointer */
|
|
8001930: 20020000 .word 0x20020000
|
|
ldr r0, =_sdata
|
|
8001934: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
8001938: 200001a0 .word 0x200001a0
|
|
ldr r2, =_sidata
|
|
800193c: 0800aa20 .word 0x0800aa20
|
|
ldr r2, =_sbss
|
|
8001940: 200001a0 .word 0x200001a0
|
|
ldr r4, =_ebss
|
|
8001944: 200010f8 .word 0x200010f8
|
|
|
|
08001948 <ADC_IRQHandler>:
|
|
* @retval None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8001948: e7fe b.n 8001948 <ADC_IRQHandler>
|
|
...
|
|
|
|
0800194c <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
800194c: b580 push {r7, lr}
|
|
800194e: af00 add r7, sp, #0
|
|
/* Configure Flash prefetch, Instruction cache, Data cache */
|
|
#if (INSTRUCTION_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
|
|
8001950: 4b0e ldr r3, [pc, #56] @ (800198c <HAL_Init+0x40>)
|
|
8001952: 681b ldr r3, [r3, #0]
|
|
8001954: 4a0d ldr r2, [pc, #52] @ (800198c <HAL_Init+0x40>)
|
|
8001956: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
800195a: 6013 str r3, [r2, #0]
|
|
#endif /* INSTRUCTION_CACHE_ENABLE */
|
|
|
|
#if (DATA_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_DATA_CACHE_ENABLE();
|
|
800195c: 4b0b ldr r3, [pc, #44] @ (800198c <HAL_Init+0x40>)
|
|
800195e: 681b ldr r3, [r3, #0]
|
|
8001960: 4a0a ldr r2, [pc, #40] @ (800198c <HAL_Init+0x40>)
|
|
8001962: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8001966: 6013 str r3, [r2, #0]
|
|
#endif /* DATA_CACHE_ENABLE */
|
|
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
8001968: 4b08 ldr r3, [pc, #32] @ (800198c <HAL_Init+0x40>)
|
|
800196a: 681b ldr r3, [r3, #0]
|
|
800196c: 4a07 ldr r2, [pc, #28] @ (800198c <HAL_Init+0x40>)
|
|
800196e: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8001972: 6013 str r3, [r2, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8001974: 2003 movs r0, #3
|
|
8001976: f000 f94f bl 8001c18 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
800197a: 200f movs r0, #15
|
|
800197c: f000 f808 bl 8001990 <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8001980: f7ff fa18 bl 8000db4 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8001984: 2300 movs r3, #0
|
|
}
|
|
8001986: 4618 mov r0, r3
|
|
8001988: bd80 pop {r7, pc}
|
|
800198a: bf00 nop
|
|
800198c: 40023c00 .word 0x40023c00
|
|
|
|
08001990 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8001990: b580 push {r7, lr}
|
|
8001992: b082 sub sp, #8
|
|
8001994: af00 add r7, sp, #0
|
|
8001996: 6078 str r0, [r7, #4]
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
8001998: 4b12 ldr r3, [pc, #72] @ (80019e4 <HAL_InitTick+0x54>)
|
|
800199a: 681a ldr r2, [r3, #0]
|
|
800199c: 4b12 ldr r3, [pc, #72] @ (80019e8 <HAL_InitTick+0x58>)
|
|
800199e: 781b ldrb r3, [r3, #0]
|
|
80019a0: 4619 mov r1, r3
|
|
80019a2: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
80019a6: fbb3 f3f1 udiv r3, r3, r1
|
|
80019aa: fbb2 f3f3 udiv r3, r2, r3
|
|
80019ae: 4618 mov r0, r3
|
|
80019b0: f000 f967 bl 8001c82 <HAL_SYSTICK_Config>
|
|
80019b4: 4603 mov r3, r0
|
|
80019b6: 2b00 cmp r3, #0
|
|
80019b8: d001 beq.n 80019be <HAL_InitTick+0x2e>
|
|
{
|
|
return HAL_ERROR;
|
|
80019ba: 2301 movs r3, #1
|
|
80019bc: e00e b.n 80019dc <HAL_InitTick+0x4c>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
80019be: 687b ldr r3, [r7, #4]
|
|
80019c0: 2b0f cmp r3, #15
|
|
80019c2: d80a bhi.n 80019da <HAL_InitTick+0x4a>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
80019c4: 2200 movs r2, #0
|
|
80019c6: 6879 ldr r1, [r7, #4]
|
|
80019c8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80019cc: f000 f92f bl 8001c2e <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
80019d0: 4a06 ldr r2, [pc, #24] @ (80019ec <HAL_InitTick+0x5c>)
|
|
80019d2: 687b ldr r3, [r7, #4]
|
|
80019d4: 6013 str r3, [r2, #0]
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80019d6: 2300 movs r3, #0
|
|
80019d8: e000 b.n 80019dc <HAL_InitTick+0x4c>
|
|
return HAL_ERROR;
|
|
80019da: 2301 movs r3, #1
|
|
}
|
|
80019dc: 4618 mov r0, r3
|
|
80019de: 3708 adds r7, #8
|
|
80019e0: 46bd mov sp, r7
|
|
80019e2: bd80 pop {r7, pc}
|
|
80019e4: 20000090 .word 0x20000090
|
|
80019e8: 20000098 .word 0x20000098
|
|
80019ec: 20000094 .word 0x20000094
|
|
|
|
080019f0 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
80019f0: b480 push {r7}
|
|
80019f2: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
80019f4: 4b06 ldr r3, [pc, #24] @ (8001a10 <HAL_IncTick+0x20>)
|
|
80019f6: 781b ldrb r3, [r3, #0]
|
|
80019f8: 461a mov r2, r3
|
|
80019fa: 4b06 ldr r3, [pc, #24] @ (8001a14 <HAL_IncTick+0x24>)
|
|
80019fc: 681b ldr r3, [r3, #0]
|
|
80019fe: 4413 add r3, r2
|
|
8001a00: 4a04 ldr r2, [pc, #16] @ (8001a14 <HAL_IncTick+0x24>)
|
|
8001a02: 6013 str r3, [r2, #0]
|
|
}
|
|
8001a04: bf00 nop
|
|
8001a06: 46bd mov sp, r7
|
|
8001a08: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001a0c: 4770 bx lr
|
|
8001a0e: bf00 nop
|
|
8001a10: 20000098 .word 0x20000098
|
|
8001a14: 2000071c .word 0x2000071c
|
|
|
|
08001a18 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8001a18: b480 push {r7}
|
|
8001a1a: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8001a1c: 4b03 ldr r3, [pc, #12] @ (8001a2c <HAL_GetTick+0x14>)
|
|
8001a1e: 681b ldr r3, [r3, #0]
|
|
}
|
|
8001a20: 4618 mov r0, r3
|
|
8001a22: 46bd mov sp, r7
|
|
8001a24: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001a28: 4770 bx lr
|
|
8001a2a: bf00 nop
|
|
8001a2c: 2000071c .word 0x2000071c
|
|
|
|
08001a30 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8001a30: b580 push {r7, lr}
|
|
8001a32: b084 sub sp, #16
|
|
8001a34: af00 add r7, sp, #0
|
|
8001a36: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8001a38: f7ff ffee bl 8001a18 <HAL_GetTick>
|
|
8001a3c: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8001a3e: 687b ldr r3, [r7, #4]
|
|
8001a40: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8001a42: 68fb ldr r3, [r7, #12]
|
|
8001a44: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8001a48: d005 beq.n 8001a56 <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
8001a4a: 4b0a ldr r3, [pc, #40] @ (8001a74 <HAL_Delay+0x44>)
|
|
8001a4c: 781b ldrb r3, [r3, #0]
|
|
8001a4e: 461a mov r2, r3
|
|
8001a50: 68fb ldr r3, [r7, #12]
|
|
8001a52: 4413 add r3, r2
|
|
8001a54: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while((HAL_GetTick() - tickstart) < wait)
|
|
8001a56: bf00 nop
|
|
8001a58: f7ff ffde bl 8001a18 <HAL_GetTick>
|
|
8001a5c: 4602 mov r2, r0
|
|
8001a5e: 68bb ldr r3, [r7, #8]
|
|
8001a60: 1ad3 subs r3, r2, r3
|
|
8001a62: 68fa ldr r2, [r7, #12]
|
|
8001a64: 429a cmp r2, r3
|
|
8001a66: d8f7 bhi.n 8001a58 <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
8001a68: bf00 nop
|
|
8001a6a: bf00 nop
|
|
8001a6c: 3710 adds r7, #16
|
|
8001a6e: 46bd mov sp, r7
|
|
8001a70: bd80 pop {r7, pc}
|
|
8001a72: bf00 nop
|
|
8001a74: 20000098 .word 0x20000098
|
|
|
|
08001a78 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001a78: b480 push {r7}
|
|
8001a7a: b085 sub sp, #20
|
|
8001a7c: af00 add r7, sp, #0
|
|
8001a7e: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8001a80: 687b ldr r3, [r7, #4]
|
|
8001a82: f003 0307 and.w r3, r3, #7
|
|
8001a86: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
8001a88: 4b0c ldr r3, [pc, #48] @ (8001abc <__NVIC_SetPriorityGrouping+0x44>)
|
|
8001a8a: 68db ldr r3, [r3, #12]
|
|
8001a8c: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
8001a8e: 68ba ldr r2, [r7, #8]
|
|
8001a90: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
8001a94: 4013 ands r3, r2
|
|
8001a96: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
8001a98: 68fb ldr r3, [r7, #12]
|
|
8001a9a: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
8001a9c: 68bb ldr r3, [r7, #8]
|
|
8001a9e: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
8001aa0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
8001aa4: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8001aa8: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
8001aaa: 4a04 ldr r2, [pc, #16] @ (8001abc <__NVIC_SetPriorityGrouping+0x44>)
|
|
8001aac: 68bb ldr r3, [r7, #8]
|
|
8001aae: 60d3 str r3, [r2, #12]
|
|
}
|
|
8001ab0: bf00 nop
|
|
8001ab2: 3714 adds r7, #20
|
|
8001ab4: 46bd mov sp, r7
|
|
8001ab6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001aba: 4770 bx lr
|
|
8001abc: e000ed00 .word 0xe000ed00
|
|
|
|
08001ac0 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8001ac0: b480 push {r7}
|
|
8001ac2: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8001ac4: 4b04 ldr r3, [pc, #16] @ (8001ad8 <__NVIC_GetPriorityGrouping+0x18>)
|
|
8001ac6: 68db ldr r3, [r3, #12]
|
|
8001ac8: 0a1b lsrs r3, r3, #8
|
|
8001aca: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8001ace: 4618 mov r0, r3
|
|
8001ad0: 46bd mov sp, r7
|
|
8001ad2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001ad6: 4770 bx lr
|
|
8001ad8: e000ed00 .word 0xe000ed00
|
|
|
|
08001adc <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001adc: b480 push {r7}
|
|
8001ade: b083 sub sp, #12
|
|
8001ae0: af00 add r7, sp, #0
|
|
8001ae2: 4603 mov r3, r0
|
|
8001ae4: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001ae6: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001aea: 2b00 cmp r3, #0
|
|
8001aec: db0b blt.n 8001b06 <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8001aee: 79fb ldrb r3, [r7, #7]
|
|
8001af0: f003 021f and.w r2, r3, #31
|
|
8001af4: 4907 ldr r1, [pc, #28] @ (8001b14 <__NVIC_EnableIRQ+0x38>)
|
|
8001af6: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001afa: 095b lsrs r3, r3, #5
|
|
8001afc: 2001 movs r0, #1
|
|
8001afe: fa00 f202 lsl.w r2, r0, r2
|
|
8001b02: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
8001b06: bf00 nop
|
|
8001b08: 370c adds r7, #12
|
|
8001b0a: 46bd mov sp, r7
|
|
8001b0c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001b10: 4770 bx lr
|
|
8001b12: bf00 nop
|
|
8001b14: e000e100 .word 0xe000e100
|
|
|
|
08001b18 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8001b18: b480 push {r7}
|
|
8001b1a: b083 sub sp, #12
|
|
8001b1c: af00 add r7, sp, #0
|
|
8001b1e: 4603 mov r3, r0
|
|
8001b20: 6039 str r1, [r7, #0]
|
|
8001b22: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8001b24: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001b28: 2b00 cmp r3, #0
|
|
8001b2a: db0a blt.n 8001b42 <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001b2c: 683b ldr r3, [r7, #0]
|
|
8001b2e: b2da uxtb r2, r3
|
|
8001b30: 490c ldr r1, [pc, #48] @ (8001b64 <__NVIC_SetPriority+0x4c>)
|
|
8001b32: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001b36: 0112 lsls r2, r2, #4
|
|
8001b38: b2d2 uxtb r2, r2
|
|
8001b3a: 440b add r3, r1
|
|
8001b3c: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8001b40: e00a b.n 8001b58 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001b42: 683b ldr r3, [r7, #0]
|
|
8001b44: b2da uxtb r2, r3
|
|
8001b46: 4908 ldr r1, [pc, #32] @ (8001b68 <__NVIC_SetPriority+0x50>)
|
|
8001b48: 79fb ldrb r3, [r7, #7]
|
|
8001b4a: f003 030f and.w r3, r3, #15
|
|
8001b4e: 3b04 subs r3, #4
|
|
8001b50: 0112 lsls r2, r2, #4
|
|
8001b52: b2d2 uxtb r2, r2
|
|
8001b54: 440b add r3, r1
|
|
8001b56: 761a strb r2, [r3, #24]
|
|
}
|
|
8001b58: bf00 nop
|
|
8001b5a: 370c adds r7, #12
|
|
8001b5c: 46bd mov sp, r7
|
|
8001b5e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001b62: 4770 bx lr
|
|
8001b64: e000e100 .word 0xe000e100
|
|
8001b68: e000ed00 .word 0xe000ed00
|
|
|
|
08001b6c <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001b6c: b480 push {r7}
|
|
8001b6e: b089 sub sp, #36 @ 0x24
|
|
8001b70: af00 add r7, sp, #0
|
|
8001b72: 60f8 str r0, [r7, #12]
|
|
8001b74: 60b9 str r1, [r7, #8]
|
|
8001b76: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8001b78: 68fb ldr r3, [r7, #12]
|
|
8001b7a: f003 0307 and.w r3, r3, #7
|
|
8001b7e: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8001b80: 69fb ldr r3, [r7, #28]
|
|
8001b82: f1c3 0307 rsb r3, r3, #7
|
|
8001b86: 2b04 cmp r3, #4
|
|
8001b88: bf28 it cs
|
|
8001b8a: 2304 movcs r3, #4
|
|
8001b8c: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8001b8e: 69fb ldr r3, [r7, #28]
|
|
8001b90: 3304 adds r3, #4
|
|
8001b92: 2b06 cmp r3, #6
|
|
8001b94: d902 bls.n 8001b9c <NVIC_EncodePriority+0x30>
|
|
8001b96: 69fb ldr r3, [r7, #28]
|
|
8001b98: 3b03 subs r3, #3
|
|
8001b9a: e000 b.n 8001b9e <NVIC_EncodePriority+0x32>
|
|
8001b9c: 2300 movs r3, #0
|
|
8001b9e: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8001ba0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8001ba4: 69bb ldr r3, [r7, #24]
|
|
8001ba6: fa02 f303 lsl.w r3, r2, r3
|
|
8001baa: 43da mvns r2, r3
|
|
8001bac: 68bb ldr r3, [r7, #8]
|
|
8001bae: 401a ands r2, r3
|
|
8001bb0: 697b ldr r3, [r7, #20]
|
|
8001bb2: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8001bb4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8001bb8: 697b ldr r3, [r7, #20]
|
|
8001bba: fa01 f303 lsl.w r3, r1, r3
|
|
8001bbe: 43d9 mvns r1, r3
|
|
8001bc0: 687b ldr r3, [r7, #4]
|
|
8001bc2: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8001bc4: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
8001bc6: 4618 mov r0, r3
|
|
8001bc8: 3724 adds r7, #36 @ 0x24
|
|
8001bca: 46bd mov sp, r7
|
|
8001bcc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001bd0: 4770 bx lr
|
|
...
|
|
|
|
08001bd4 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
8001bd4: b580 push {r7, lr}
|
|
8001bd6: b082 sub sp, #8
|
|
8001bd8: af00 add r7, sp, #0
|
|
8001bda: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8001bdc: 687b ldr r3, [r7, #4]
|
|
8001bde: 3b01 subs r3, #1
|
|
8001be0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8001be4: d301 bcc.n 8001bea <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
8001be6: 2301 movs r3, #1
|
|
8001be8: e00f b.n 8001c0a <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8001bea: 4a0a ldr r2, [pc, #40] @ (8001c14 <SysTick_Config+0x40>)
|
|
8001bec: 687b ldr r3, [r7, #4]
|
|
8001bee: 3b01 subs r3, #1
|
|
8001bf0: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8001bf2: 210f movs r1, #15
|
|
8001bf4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8001bf8: f7ff ff8e bl 8001b18 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8001bfc: 4b05 ldr r3, [pc, #20] @ (8001c14 <SysTick_Config+0x40>)
|
|
8001bfe: 2200 movs r2, #0
|
|
8001c00: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8001c02: 4b04 ldr r3, [pc, #16] @ (8001c14 <SysTick_Config+0x40>)
|
|
8001c04: 2207 movs r2, #7
|
|
8001c06: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8001c08: 2300 movs r3, #0
|
|
}
|
|
8001c0a: 4618 mov r0, r3
|
|
8001c0c: 3708 adds r7, #8
|
|
8001c0e: 46bd mov sp, r7
|
|
8001c10: bd80 pop {r7, pc}
|
|
8001c12: bf00 nop
|
|
8001c14: e000e010 .word 0xe000e010
|
|
|
|
08001c18 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001c18: b580 push {r7, lr}
|
|
8001c1a: b082 sub sp, #8
|
|
8001c1c: af00 add r7, sp, #0
|
|
8001c1e: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8001c20: 6878 ldr r0, [r7, #4]
|
|
8001c22: f7ff ff29 bl 8001a78 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8001c26: bf00 nop
|
|
8001c28: 3708 adds r7, #8
|
|
8001c2a: 46bd mov sp, r7
|
|
8001c2c: bd80 pop {r7, pc}
|
|
|
|
08001c2e <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001c2e: b580 push {r7, lr}
|
|
8001c30: b086 sub sp, #24
|
|
8001c32: af00 add r7, sp, #0
|
|
8001c34: 4603 mov r3, r0
|
|
8001c36: 60b9 str r1, [r7, #8]
|
|
8001c38: 607a str r2, [r7, #4]
|
|
8001c3a: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
8001c3c: 2300 movs r3, #0
|
|
8001c3e: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8001c40: f7ff ff3e bl 8001ac0 <__NVIC_GetPriorityGrouping>
|
|
8001c44: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8001c46: 687a ldr r2, [r7, #4]
|
|
8001c48: 68b9 ldr r1, [r7, #8]
|
|
8001c4a: 6978 ldr r0, [r7, #20]
|
|
8001c4c: f7ff ff8e bl 8001b6c <NVIC_EncodePriority>
|
|
8001c50: 4602 mov r2, r0
|
|
8001c52: f997 300f ldrsb.w r3, [r7, #15]
|
|
8001c56: 4611 mov r1, r2
|
|
8001c58: 4618 mov r0, r3
|
|
8001c5a: f7ff ff5d bl 8001b18 <__NVIC_SetPriority>
|
|
}
|
|
8001c5e: bf00 nop
|
|
8001c60: 3718 adds r7, #24
|
|
8001c62: 46bd mov sp, r7
|
|
8001c64: bd80 pop {r7, pc}
|
|
|
|
08001c66 <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001c66: b580 push {r7, lr}
|
|
8001c68: b082 sub sp, #8
|
|
8001c6a: af00 add r7, sp, #0
|
|
8001c6c: 4603 mov r3, r0
|
|
8001c6e: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8001c70: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001c74: 4618 mov r0, r3
|
|
8001c76: f7ff ff31 bl 8001adc <__NVIC_EnableIRQ>
|
|
}
|
|
8001c7a: bf00 nop
|
|
8001c7c: 3708 adds r7, #8
|
|
8001c7e: 46bd mov sp, r7
|
|
8001c80: bd80 pop {r7, pc}
|
|
|
|
08001c82 <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
8001c82: b580 push {r7, lr}
|
|
8001c84: b082 sub sp, #8
|
|
8001c86: af00 add r7, sp, #0
|
|
8001c88: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8001c8a: 6878 ldr r0, [r7, #4]
|
|
8001c8c: f7ff ffa2 bl 8001bd4 <SysTick_Config>
|
|
8001c90: 4603 mov r3, r0
|
|
}
|
|
8001c92: 4618 mov r0, r3
|
|
8001c94: 3708 adds r7, #8
|
|
8001c96: 46bd mov sp, r7
|
|
8001c98: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001c9c <HAL_DMA_Init>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8001c9c: b580 push {r7, lr}
|
|
8001c9e: b086 sub sp, #24
|
|
8001ca0: af00 add r7, sp, #0
|
|
8001ca2: 6078 str r0, [r7, #4]
|
|
uint32_t tmp = 0U;
|
|
8001ca4: 2300 movs r3, #0
|
|
8001ca6: 617b str r3, [r7, #20]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8001ca8: f7ff feb6 bl 8001a18 <HAL_GetTick>
|
|
8001cac: 6138 str r0, [r7, #16]
|
|
DMA_Base_Registers *regs;
|
|
|
|
/* Check the DMA peripheral state */
|
|
if(hdma == NULL)
|
|
8001cae: 687b ldr r3, [r7, #4]
|
|
8001cb0: 2b00 cmp r3, #0
|
|
8001cb2: d101 bne.n 8001cb8 <HAL_DMA_Init+0x1c>
|
|
{
|
|
return HAL_ERROR;
|
|
8001cb4: 2301 movs r3, #1
|
|
8001cb6: e099 b.n 8001dec <HAL_DMA_Init+0x150>
|
|
assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
|
|
assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
|
|
}
|
|
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
8001cb8: 687b ldr r3, [r7, #4]
|
|
8001cba: 2202 movs r2, #2
|
|
8001cbc: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Allocate lock resource */
|
|
__HAL_UNLOCK(hdma);
|
|
8001cc0: 687b ldr r3, [r7, #4]
|
|
8001cc2: 2200 movs r2, #0
|
|
8001cc4: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8001cc8: 687b ldr r3, [r7, #4]
|
|
8001cca: 681b ldr r3, [r3, #0]
|
|
8001ccc: 681a ldr r2, [r3, #0]
|
|
8001cce: 687b ldr r3, [r7, #4]
|
|
8001cd0: 681b ldr r3, [r3, #0]
|
|
8001cd2: f022 0201 bic.w r2, r2, #1
|
|
8001cd6: 601a str r2, [r3, #0]
|
|
|
|
/* Check if the DMA Stream is effectively disabled */
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
|
|
8001cd8: e00f b.n 8001cfa <HAL_DMA_Init+0x5e>
|
|
{
|
|
/* Check for the Timeout */
|
|
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
|
|
8001cda: f7ff fe9d bl 8001a18 <HAL_GetTick>
|
|
8001cde: 4602 mov r2, r0
|
|
8001ce0: 693b ldr r3, [r7, #16]
|
|
8001ce2: 1ad3 subs r3, r2, r3
|
|
8001ce4: 2b05 cmp r3, #5
|
|
8001ce6: d908 bls.n 8001cfa <HAL_DMA_Init+0x5e>
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
|
8001ce8: 687b ldr r3, [r7, #4]
|
|
8001cea: 2220 movs r2, #32
|
|
8001cec: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_TIMEOUT;
|
|
8001cee: 687b ldr r3, [r7, #4]
|
|
8001cf0: 2203 movs r2, #3
|
|
8001cf2: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
return HAL_TIMEOUT;
|
|
8001cf6: 2303 movs r3, #3
|
|
8001cf8: e078 b.n 8001dec <HAL_DMA_Init+0x150>
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
|
|
8001cfa: 687b ldr r3, [r7, #4]
|
|
8001cfc: 681b ldr r3, [r3, #0]
|
|
8001cfe: 681b ldr r3, [r3, #0]
|
|
8001d00: f003 0301 and.w r3, r3, #1
|
|
8001d04: 2b00 cmp r3, #0
|
|
8001d06: d1e8 bne.n 8001cda <HAL_DMA_Init+0x3e>
|
|
}
|
|
}
|
|
|
|
/* Get the CR register value */
|
|
tmp = hdma->Instance->CR;
|
|
8001d08: 687b ldr r3, [r7, #4]
|
|
8001d0a: 681b ldr r3, [r3, #0]
|
|
8001d0c: 681b ldr r3, [r3, #0]
|
|
8001d0e: 617b str r3, [r7, #20]
|
|
|
|
/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
|
|
tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
|
|
8001d10: 697a ldr r2, [r7, #20]
|
|
8001d12: 4b38 ldr r3, [pc, #224] @ (8001df4 <HAL_DMA_Init+0x158>)
|
|
8001d14: 4013 ands r3, r2
|
|
8001d16: 617b str r3, [r7, #20]
|
|
DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
|
|
DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
|
|
DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
|
|
|
|
/* Prepare the DMA Stream configuration */
|
|
tmp |= hdma->Init.Channel | hdma->Init.Direction |
|
|
8001d18: 687b ldr r3, [r7, #4]
|
|
8001d1a: 685a ldr r2, [r3, #4]
|
|
8001d1c: 687b ldr r3, [r7, #4]
|
|
8001d1e: 689b ldr r3, [r3, #8]
|
|
8001d20: 431a orrs r2, r3
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
8001d22: 687b ldr r3, [r7, #4]
|
|
8001d24: 68db ldr r3, [r3, #12]
|
|
tmp |= hdma->Init.Channel | hdma->Init.Direction |
|
|
8001d26: 431a orrs r2, r3
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
8001d28: 687b ldr r3, [r7, #4]
|
|
8001d2a: 691b ldr r3, [r3, #16]
|
|
8001d2c: 431a orrs r2, r3
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
8001d2e: 687b ldr r3, [r7, #4]
|
|
8001d30: 695b ldr r3, [r3, #20]
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
8001d32: 431a orrs r2, r3
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
8001d34: 687b ldr r3, [r7, #4]
|
|
8001d36: 699b ldr r3, [r3, #24]
|
|
8001d38: 431a orrs r2, r3
|
|
hdma->Init.Mode | hdma->Init.Priority;
|
|
8001d3a: 687b ldr r3, [r7, #4]
|
|
8001d3c: 69db ldr r3, [r3, #28]
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
8001d3e: 431a orrs r2, r3
|
|
hdma->Init.Mode | hdma->Init.Priority;
|
|
8001d40: 687b ldr r3, [r7, #4]
|
|
8001d42: 6a1b ldr r3, [r3, #32]
|
|
8001d44: 4313 orrs r3, r2
|
|
tmp |= hdma->Init.Channel | hdma->Init.Direction |
|
|
8001d46: 697a ldr r2, [r7, #20]
|
|
8001d48: 4313 orrs r3, r2
|
|
8001d4a: 617b str r3, [r7, #20]
|
|
|
|
/* the Memory burst and peripheral burst are not used when the FIFO is disabled */
|
|
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
|
|
8001d4c: 687b ldr r3, [r7, #4]
|
|
8001d4e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001d50: 2b04 cmp r3, #4
|
|
8001d52: d107 bne.n 8001d64 <HAL_DMA_Init+0xc8>
|
|
{
|
|
/* Get memory burst and peripheral burst */
|
|
tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
|
|
8001d54: 687b ldr r3, [r7, #4]
|
|
8001d56: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8001d58: 687b ldr r3, [r7, #4]
|
|
8001d5a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001d5c: 4313 orrs r3, r2
|
|
8001d5e: 697a ldr r2, [r7, #20]
|
|
8001d60: 4313 orrs r3, r2
|
|
8001d62: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to DMA Stream CR register */
|
|
hdma->Instance->CR = tmp;
|
|
8001d64: 687b ldr r3, [r7, #4]
|
|
8001d66: 681b ldr r3, [r3, #0]
|
|
8001d68: 697a ldr r2, [r7, #20]
|
|
8001d6a: 601a str r2, [r3, #0]
|
|
|
|
/* Get the FCR register value */
|
|
tmp = hdma->Instance->FCR;
|
|
8001d6c: 687b ldr r3, [r7, #4]
|
|
8001d6e: 681b ldr r3, [r3, #0]
|
|
8001d70: 695b ldr r3, [r3, #20]
|
|
8001d72: 617b str r3, [r7, #20]
|
|
|
|
/* Clear Direct mode and FIFO threshold bits */
|
|
tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
|
|
8001d74: 697b ldr r3, [r7, #20]
|
|
8001d76: f023 0307 bic.w r3, r3, #7
|
|
8001d7a: 617b str r3, [r7, #20]
|
|
|
|
/* Prepare the DMA Stream FIFO configuration */
|
|
tmp |= hdma->Init.FIFOMode;
|
|
8001d7c: 687b ldr r3, [r7, #4]
|
|
8001d7e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001d80: 697a ldr r2, [r7, #20]
|
|
8001d82: 4313 orrs r3, r2
|
|
8001d84: 617b str r3, [r7, #20]
|
|
|
|
/* The FIFO threshold is not used when the FIFO mode is disabled */
|
|
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
|
|
8001d86: 687b ldr r3, [r7, #4]
|
|
8001d88: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001d8a: 2b04 cmp r3, #4
|
|
8001d8c: d117 bne.n 8001dbe <HAL_DMA_Init+0x122>
|
|
{
|
|
/* Get the FIFO threshold */
|
|
tmp |= hdma->Init.FIFOThreshold;
|
|
8001d8e: 687b ldr r3, [r7, #4]
|
|
8001d90: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8001d92: 697a ldr r2, [r7, #20]
|
|
8001d94: 4313 orrs r3, r2
|
|
8001d96: 617b str r3, [r7, #20]
|
|
|
|
/* Check compatibility between FIFO threshold level and size of the memory burst */
|
|
/* for INCR4, INCR8, INCR16 bursts */
|
|
if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
|
|
8001d98: 687b ldr r3, [r7, #4]
|
|
8001d9a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8001d9c: 2b00 cmp r3, #0
|
|
8001d9e: d00e beq.n 8001dbe <HAL_DMA_Init+0x122>
|
|
{
|
|
if (DMA_CheckFifoParam(hdma) != HAL_OK)
|
|
8001da0: 6878 ldr r0, [r7, #4]
|
|
8001da2: f000 fb01 bl 80023a8 <DMA_CheckFifoParam>
|
|
8001da6: 4603 mov r3, r0
|
|
8001da8: 2b00 cmp r3, #0
|
|
8001daa: d008 beq.n 8001dbe <HAL_DMA_Init+0x122>
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
|
|
8001dac: 687b ldr r3, [r7, #4]
|
|
8001dae: 2240 movs r2, #64 @ 0x40
|
|
8001db0: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8001db2: 687b ldr r3, [r7, #4]
|
|
8001db4: 2201 movs r2, #1
|
|
8001db6: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
return HAL_ERROR;
|
|
8001dba: 2301 movs r3, #1
|
|
8001dbc: e016 b.n 8001dec <HAL_DMA_Init+0x150>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Write to DMA Stream FCR */
|
|
hdma->Instance->FCR = tmp;
|
|
8001dbe: 687b ldr r3, [r7, #4]
|
|
8001dc0: 681b ldr r3, [r3, #0]
|
|
8001dc2: 697a ldr r2, [r7, #20]
|
|
8001dc4: 615a str r2, [r3, #20]
|
|
|
|
/* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
|
|
DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
|
|
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
|
|
8001dc6: 6878 ldr r0, [r7, #4]
|
|
8001dc8: f000 fab8 bl 800233c <DMA_CalcBaseAndBitshift>
|
|
8001dcc: 4603 mov r3, r0
|
|
8001dce: 60fb str r3, [r7, #12]
|
|
|
|
/* Clear all interrupt flags */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
8001dd0: 687b ldr r3, [r7, #4]
|
|
8001dd2: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8001dd4: 223f movs r2, #63 @ 0x3f
|
|
8001dd6: 409a lsls r2, r3
|
|
8001dd8: 68fb ldr r3, [r7, #12]
|
|
8001dda: 609a str r2, [r3, #8]
|
|
|
|
/* Initialize the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8001ddc: 687b ldr r3, [r7, #4]
|
|
8001dde: 2200 movs r2, #0
|
|
8001de0: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Initialize the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8001de2: 687b ldr r3, [r7, #4]
|
|
8001de4: 2201 movs r2, #1
|
|
8001de6: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
return HAL_OK;
|
|
8001dea: 2300 movs r3, #0
|
|
}
|
|
8001dec: 4618 mov r0, r3
|
|
8001dee: 3718 adds r7, #24
|
|
8001df0: 46bd mov sp, r7
|
|
8001df2: bd80 pop {r7, pc}
|
|
8001df4: f010803f .word 0xf010803f
|
|
|
|
08001df8 <HAL_DMA_Start_IT>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
8001df8: b580 push {r7, lr}
|
|
8001dfa: b086 sub sp, #24
|
|
8001dfc: af00 add r7, sp, #0
|
|
8001dfe: 60f8 str r0, [r7, #12]
|
|
8001e00: 60b9 str r1, [r7, #8]
|
|
8001e02: 607a str r2, [r7, #4]
|
|
8001e04: 603b str r3, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8001e06: 2300 movs r3, #0
|
|
8001e08: 75fb strb r3, [r7, #23]
|
|
|
|
/* calculate DMA base and stream number */
|
|
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
|
|
8001e0a: 68fb ldr r3, [r7, #12]
|
|
8001e0c: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001e0e: 613b str r3, [r7, #16]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma);
|
|
8001e10: 68fb ldr r3, [r7, #12]
|
|
8001e12: f893 3034 ldrb.w r3, [r3, #52] @ 0x34
|
|
8001e16: 2b01 cmp r3, #1
|
|
8001e18: d101 bne.n 8001e1e <HAL_DMA_Start_IT+0x26>
|
|
8001e1a: 2302 movs r3, #2
|
|
8001e1c: e040 b.n 8001ea0 <HAL_DMA_Start_IT+0xa8>
|
|
8001e1e: 68fb ldr r3, [r7, #12]
|
|
8001e20: 2201 movs r2, #1
|
|
8001e22: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
if(HAL_DMA_STATE_READY == hdma->State)
|
|
8001e26: 68fb ldr r3, [r7, #12]
|
|
8001e28: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
|
|
8001e2c: b2db uxtb r3, r3
|
|
8001e2e: 2b01 cmp r3, #1
|
|
8001e30: d12f bne.n 8001e92 <HAL_DMA_Start_IT+0x9a>
|
|
{
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
8001e32: 68fb ldr r3, [r7, #12]
|
|
8001e34: 2202 movs r2, #2
|
|
8001e36: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Initialize the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8001e3a: 68fb ldr r3, [r7, #12]
|
|
8001e3c: 2200 movs r2, #0
|
|
8001e3e: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Configure the source, destination address and the data length */
|
|
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
|
8001e40: 683b ldr r3, [r7, #0]
|
|
8001e42: 687a ldr r2, [r7, #4]
|
|
8001e44: 68b9 ldr r1, [r7, #8]
|
|
8001e46: 68f8 ldr r0, [r7, #12]
|
|
8001e48: f000 fa4a bl 80022e0 <DMA_SetConfig>
|
|
|
|
/* Clear all interrupt flags at correct offset within the register */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
8001e4c: 68fb ldr r3, [r7, #12]
|
|
8001e4e: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8001e50: 223f movs r2, #63 @ 0x3f
|
|
8001e52: 409a lsls r2, r3
|
|
8001e54: 693b ldr r3, [r7, #16]
|
|
8001e56: 609a str r2, [r3, #8]
|
|
|
|
/* Enable Common interrupts*/
|
|
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
|
|
8001e58: 68fb ldr r3, [r7, #12]
|
|
8001e5a: 681b ldr r3, [r3, #0]
|
|
8001e5c: 681a ldr r2, [r3, #0]
|
|
8001e5e: 68fb ldr r3, [r7, #12]
|
|
8001e60: 681b ldr r3, [r3, #0]
|
|
8001e62: f042 0216 orr.w r2, r2, #22
|
|
8001e66: 601a str r2, [r3, #0]
|
|
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
8001e68: 68fb ldr r3, [r7, #12]
|
|
8001e6a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001e6c: 2b00 cmp r3, #0
|
|
8001e6e: d007 beq.n 8001e80 <HAL_DMA_Start_IT+0x88>
|
|
{
|
|
hdma->Instance->CR |= DMA_IT_HT;
|
|
8001e70: 68fb ldr r3, [r7, #12]
|
|
8001e72: 681b ldr r3, [r3, #0]
|
|
8001e74: 681a ldr r2, [r3, #0]
|
|
8001e76: 68fb ldr r3, [r7, #12]
|
|
8001e78: 681b ldr r3, [r3, #0]
|
|
8001e7a: f042 0208 orr.w r2, r2, #8
|
|
8001e7e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_DMA_ENABLE(hdma);
|
|
8001e80: 68fb ldr r3, [r7, #12]
|
|
8001e82: 681b ldr r3, [r3, #0]
|
|
8001e84: 681a ldr r2, [r3, #0]
|
|
8001e86: 68fb ldr r3, [r7, #12]
|
|
8001e88: 681b ldr r3, [r3, #0]
|
|
8001e8a: f042 0201 orr.w r2, r2, #1
|
|
8001e8e: 601a str r2, [r3, #0]
|
|
8001e90: e005 b.n 8001e9e <HAL_DMA_Start_IT+0xa6>
|
|
}
|
|
else
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001e92: 68fb ldr r3, [r7, #12]
|
|
8001e94: 2200 movs r2, #0
|
|
8001e96: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
/* Return error status */
|
|
status = HAL_BUSY;
|
|
8001e9a: 2302 movs r3, #2
|
|
8001e9c: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return status;
|
|
8001e9e: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8001ea0: 4618 mov r0, r3
|
|
8001ea2: 3718 adds r7, #24
|
|
8001ea4: 46bd mov sp, r7
|
|
8001ea6: bd80 pop {r7, pc}
|
|
|
|
08001ea8 <HAL_DMA_Abort>:
|
|
* and the Stream will be effectively disabled only after the transfer of
|
|
* this single data is finished.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8001ea8: b580 push {r7, lr}
|
|
8001eaa: b084 sub sp, #16
|
|
8001eac: af00 add r7, sp, #0
|
|
8001eae: 6078 str r0, [r7, #4]
|
|
/* calculate DMA base and stream number */
|
|
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
|
|
8001eb0: 687b ldr r3, [r7, #4]
|
|
8001eb2: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001eb4: 60fb str r3, [r7, #12]
|
|
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8001eb6: f7ff fdaf bl 8001a18 <HAL_GetTick>
|
|
8001eba: 60b8 str r0, [r7, #8]
|
|
|
|
if(hdma->State != HAL_DMA_STATE_BUSY)
|
|
8001ebc: 687b ldr r3, [r7, #4]
|
|
8001ebe: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
|
|
8001ec2: b2db uxtb r3, r3
|
|
8001ec4: 2b02 cmp r3, #2
|
|
8001ec6: d008 beq.n 8001eda <HAL_DMA_Abort+0x32>
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8001ec8: 687b ldr r3, [r7, #4]
|
|
8001eca: 2280 movs r2, #128 @ 0x80
|
|
8001ecc: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001ece: 687b ldr r3, [r7, #4]
|
|
8001ed0: 2200 movs r2, #0
|
|
8001ed2: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_ERROR;
|
|
8001ed6: 2301 movs r3, #1
|
|
8001ed8: e052 b.n 8001f80 <HAL_DMA_Abort+0xd8>
|
|
}
|
|
else
|
|
{
|
|
/* Disable all the transfer interrupts */
|
|
hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
|
|
8001eda: 687b ldr r3, [r7, #4]
|
|
8001edc: 681b ldr r3, [r3, #0]
|
|
8001ede: 681a ldr r2, [r3, #0]
|
|
8001ee0: 687b ldr r3, [r7, #4]
|
|
8001ee2: 681b ldr r3, [r3, #0]
|
|
8001ee4: f022 0216 bic.w r2, r2, #22
|
|
8001ee8: 601a str r2, [r3, #0]
|
|
hdma->Instance->FCR &= ~(DMA_IT_FE);
|
|
8001eea: 687b ldr r3, [r7, #4]
|
|
8001eec: 681b ldr r3, [r3, #0]
|
|
8001eee: 695a ldr r2, [r3, #20]
|
|
8001ef0: 687b ldr r3, [r7, #4]
|
|
8001ef2: 681b ldr r3, [r3, #0]
|
|
8001ef4: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
8001ef8: 615a str r2, [r3, #20]
|
|
|
|
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
|
|
8001efa: 687b ldr r3, [r7, #4]
|
|
8001efc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001efe: 2b00 cmp r3, #0
|
|
8001f00: d103 bne.n 8001f0a <HAL_DMA_Abort+0x62>
|
|
8001f02: 687b ldr r3, [r7, #4]
|
|
8001f04: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001f06: 2b00 cmp r3, #0
|
|
8001f08: d007 beq.n 8001f1a <HAL_DMA_Abort+0x72>
|
|
{
|
|
hdma->Instance->CR &= ~(DMA_IT_HT);
|
|
8001f0a: 687b ldr r3, [r7, #4]
|
|
8001f0c: 681b ldr r3, [r3, #0]
|
|
8001f0e: 681a ldr r2, [r3, #0]
|
|
8001f10: 687b ldr r3, [r7, #4]
|
|
8001f12: 681b ldr r3, [r3, #0]
|
|
8001f14: f022 0208 bic.w r2, r2, #8
|
|
8001f18: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Disable the stream */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8001f1a: 687b ldr r3, [r7, #4]
|
|
8001f1c: 681b ldr r3, [r3, #0]
|
|
8001f1e: 681a ldr r2, [r3, #0]
|
|
8001f20: 687b ldr r3, [r7, #4]
|
|
8001f22: 681b ldr r3, [r3, #0]
|
|
8001f24: f022 0201 bic.w r2, r2, #1
|
|
8001f28: 601a str r2, [r3, #0]
|
|
|
|
/* Check if the DMA Stream is effectively disabled */
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
|
|
8001f2a: e013 b.n 8001f54 <HAL_DMA_Abort+0xac>
|
|
{
|
|
/* Check for the Timeout */
|
|
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
|
|
8001f2c: f7ff fd74 bl 8001a18 <HAL_GetTick>
|
|
8001f30: 4602 mov r2, r0
|
|
8001f32: 68bb ldr r3, [r7, #8]
|
|
8001f34: 1ad3 subs r3, r2, r3
|
|
8001f36: 2b05 cmp r3, #5
|
|
8001f38: d90c bls.n 8001f54 <HAL_DMA_Abort+0xac>
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
|
8001f3a: 687b ldr r3, [r7, #4]
|
|
8001f3c: 2220 movs r2, #32
|
|
8001f3e: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_TIMEOUT;
|
|
8001f40: 687b ldr r3, [r7, #4]
|
|
8001f42: 2203 movs r2, #3
|
|
8001f44: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001f48: 687b ldr r3, [r7, #4]
|
|
8001f4a: 2200 movs r2, #0
|
|
8001f4c: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_TIMEOUT;
|
|
8001f50: 2303 movs r3, #3
|
|
8001f52: e015 b.n 8001f80 <HAL_DMA_Abort+0xd8>
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
|
|
8001f54: 687b ldr r3, [r7, #4]
|
|
8001f56: 681b ldr r3, [r3, #0]
|
|
8001f58: 681b ldr r3, [r3, #0]
|
|
8001f5a: f003 0301 and.w r3, r3, #1
|
|
8001f5e: 2b00 cmp r3, #0
|
|
8001f60: d1e4 bne.n 8001f2c <HAL_DMA_Abort+0x84>
|
|
}
|
|
}
|
|
|
|
/* Clear all interrupt flags at correct offset within the register */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
8001f62: 687b ldr r3, [r7, #4]
|
|
8001f64: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8001f66: 223f movs r2, #63 @ 0x3f
|
|
8001f68: 409a lsls r2, r3
|
|
8001f6a: 68fb ldr r3, [r7, #12]
|
|
8001f6c: 609a str r2, [r3, #8]
|
|
|
|
/* Change the DMA state*/
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8001f6e: 687b ldr r3, [r7, #4]
|
|
8001f70: 2201 movs r2, #1
|
|
8001f72: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001f76: 687b ldr r3, [r7, #4]
|
|
8001f78: 2200 movs r2, #0
|
|
8001f7a: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
}
|
|
return HAL_OK;
|
|
8001f7e: 2300 movs r3, #0
|
|
}
|
|
8001f80: 4618 mov r0, r3
|
|
8001f82: 3710 adds r7, #16
|
|
8001f84: 46bd mov sp, r7
|
|
8001f86: bd80 pop {r7, pc}
|
|
|
|
08001f88 <HAL_DMA_Abort_IT>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8001f88: b480 push {r7}
|
|
8001f8a: b083 sub sp, #12
|
|
8001f8c: af00 add r7, sp, #0
|
|
8001f8e: 6078 str r0, [r7, #4]
|
|
if(hdma->State != HAL_DMA_STATE_BUSY)
|
|
8001f90: 687b ldr r3, [r7, #4]
|
|
8001f92: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
|
|
8001f96: b2db uxtb r3, r3
|
|
8001f98: 2b02 cmp r3, #2
|
|
8001f9a: d004 beq.n 8001fa6 <HAL_DMA_Abort_IT+0x1e>
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8001f9c: 687b ldr r3, [r7, #4]
|
|
8001f9e: 2280 movs r2, #128 @ 0x80
|
|
8001fa0: 655a str r2, [r3, #84] @ 0x54
|
|
return HAL_ERROR;
|
|
8001fa2: 2301 movs r3, #1
|
|
8001fa4: e00c b.n 8001fc0 <HAL_DMA_Abort_IT+0x38>
|
|
}
|
|
else
|
|
{
|
|
/* Set Abort State */
|
|
hdma->State = HAL_DMA_STATE_ABORT;
|
|
8001fa6: 687b ldr r3, [r7, #4]
|
|
8001fa8: 2205 movs r2, #5
|
|
8001faa: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Disable the stream */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8001fae: 687b ldr r3, [r7, #4]
|
|
8001fb0: 681b ldr r3, [r3, #0]
|
|
8001fb2: 681a ldr r2, [r3, #0]
|
|
8001fb4: 687b ldr r3, [r7, #4]
|
|
8001fb6: 681b ldr r3, [r3, #0]
|
|
8001fb8: f022 0201 bic.w r2, r2, #1
|
|
8001fbc: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8001fbe: 2300 movs r3, #0
|
|
}
|
|
8001fc0: 4618 mov r0, r3
|
|
8001fc2: 370c adds r7, #12
|
|
8001fc4: 46bd mov sp, r7
|
|
8001fc6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001fca: 4770 bx lr
|
|
|
|
08001fcc <HAL_DMA_IRQHandler>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval None
|
|
*/
|
|
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8001fcc: b580 push {r7, lr}
|
|
8001fce: b086 sub sp, #24
|
|
8001fd0: af00 add r7, sp, #0
|
|
8001fd2: 6078 str r0, [r7, #4]
|
|
uint32_t tmpisr;
|
|
__IO uint32_t count = 0U;
|
|
8001fd4: 2300 movs r3, #0
|
|
8001fd6: 60bb str r3, [r7, #8]
|
|
uint32_t timeout = SystemCoreClock / 9600U;
|
|
8001fd8: 4b8e ldr r3, [pc, #568] @ (8002214 <HAL_DMA_IRQHandler+0x248>)
|
|
8001fda: 681b ldr r3, [r3, #0]
|
|
8001fdc: 4a8e ldr r2, [pc, #568] @ (8002218 <HAL_DMA_IRQHandler+0x24c>)
|
|
8001fde: fba2 2303 umull r2, r3, r2, r3
|
|
8001fe2: 0a9b lsrs r3, r3, #10
|
|
8001fe4: 617b str r3, [r7, #20]
|
|
|
|
/* calculate DMA base and stream number */
|
|
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
|
|
8001fe6: 687b ldr r3, [r7, #4]
|
|
8001fe8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001fea: 613b str r3, [r7, #16]
|
|
|
|
tmpisr = regs->ISR;
|
|
8001fec: 693b ldr r3, [r7, #16]
|
|
8001fee: 681b ldr r3, [r3, #0]
|
|
8001ff0: 60fb str r3, [r7, #12]
|
|
|
|
/* Transfer Error Interrupt management ***************************************/
|
|
if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
|
|
8001ff2: 687b ldr r3, [r7, #4]
|
|
8001ff4: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8001ff6: 2208 movs r2, #8
|
|
8001ff8: 409a lsls r2, r3
|
|
8001ffa: 68fb ldr r3, [r7, #12]
|
|
8001ffc: 4013 ands r3, r2
|
|
8001ffe: 2b00 cmp r3, #0
|
|
8002000: d01a beq.n 8002038 <HAL_DMA_IRQHandler+0x6c>
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
|
|
8002002: 687b ldr r3, [r7, #4]
|
|
8002004: 681b ldr r3, [r3, #0]
|
|
8002006: 681b ldr r3, [r3, #0]
|
|
8002008: f003 0304 and.w r3, r3, #4
|
|
800200c: 2b00 cmp r3, #0
|
|
800200e: d013 beq.n 8002038 <HAL_DMA_IRQHandler+0x6c>
|
|
{
|
|
/* Disable the transfer error interrupt */
|
|
hdma->Instance->CR &= ~(DMA_IT_TE);
|
|
8002010: 687b ldr r3, [r7, #4]
|
|
8002012: 681b ldr r3, [r3, #0]
|
|
8002014: 681a ldr r2, [r3, #0]
|
|
8002016: 687b ldr r3, [r7, #4]
|
|
8002018: 681b ldr r3, [r3, #0]
|
|
800201a: f022 0204 bic.w r2, r2, #4
|
|
800201e: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the transfer error flag */
|
|
regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
|
|
8002020: 687b ldr r3, [r7, #4]
|
|
8002022: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002024: 2208 movs r2, #8
|
|
8002026: 409a lsls r2, r3
|
|
8002028: 693b ldr r3, [r7, #16]
|
|
800202a: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
|
|
800202c: 687b ldr r3, [r7, #4]
|
|
800202e: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8002030: f043 0201 orr.w r2, r3, #1
|
|
8002034: 687b ldr r3, [r7, #4]
|
|
8002036: 655a str r2, [r3, #84] @ 0x54
|
|
}
|
|
}
|
|
/* FIFO Error Interrupt management ******************************************/
|
|
if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
|
|
8002038: 687b ldr r3, [r7, #4]
|
|
800203a: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800203c: 2201 movs r2, #1
|
|
800203e: 409a lsls r2, r3
|
|
8002040: 68fb ldr r3, [r7, #12]
|
|
8002042: 4013 ands r3, r2
|
|
8002044: 2b00 cmp r3, #0
|
|
8002046: d012 beq.n 800206e <HAL_DMA_IRQHandler+0xa2>
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
|
|
8002048: 687b ldr r3, [r7, #4]
|
|
800204a: 681b ldr r3, [r3, #0]
|
|
800204c: 695b ldr r3, [r3, #20]
|
|
800204e: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002052: 2b00 cmp r3, #0
|
|
8002054: d00b beq.n 800206e <HAL_DMA_IRQHandler+0xa2>
|
|
{
|
|
/* Clear the FIFO error flag */
|
|
regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
|
|
8002056: 687b ldr r3, [r7, #4]
|
|
8002058: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800205a: 2201 movs r2, #1
|
|
800205c: 409a lsls r2, r3
|
|
800205e: 693b ldr r3, [r7, #16]
|
|
8002060: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
|
|
8002062: 687b ldr r3, [r7, #4]
|
|
8002064: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8002066: f043 0202 orr.w r2, r3, #2
|
|
800206a: 687b ldr r3, [r7, #4]
|
|
800206c: 655a str r2, [r3, #84] @ 0x54
|
|
}
|
|
}
|
|
/* Direct Mode Error Interrupt management ***********************************/
|
|
if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
|
|
800206e: 687b ldr r3, [r7, #4]
|
|
8002070: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002072: 2204 movs r2, #4
|
|
8002074: 409a lsls r2, r3
|
|
8002076: 68fb ldr r3, [r7, #12]
|
|
8002078: 4013 ands r3, r2
|
|
800207a: 2b00 cmp r3, #0
|
|
800207c: d012 beq.n 80020a4 <HAL_DMA_IRQHandler+0xd8>
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
|
|
800207e: 687b ldr r3, [r7, #4]
|
|
8002080: 681b ldr r3, [r3, #0]
|
|
8002082: 681b ldr r3, [r3, #0]
|
|
8002084: f003 0302 and.w r3, r3, #2
|
|
8002088: 2b00 cmp r3, #0
|
|
800208a: d00b beq.n 80020a4 <HAL_DMA_IRQHandler+0xd8>
|
|
{
|
|
/* Clear the direct mode error flag */
|
|
regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
|
|
800208c: 687b ldr r3, [r7, #4]
|
|
800208e: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002090: 2204 movs r2, #4
|
|
8002092: 409a lsls r2, r3
|
|
8002094: 693b ldr r3, [r7, #16]
|
|
8002096: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
|
|
8002098: 687b ldr r3, [r7, #4]
|
|
800209a: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800209c: f043 0204 orr.w r2, r3, #4
|
|
80020a0: 687b ldr r3, [r7, #4]
|
|
80020a2: 655a str r2, [r3, #84] @ 0x54
|
|
}
|
|
}
|
|
/* Half Transfer Complete Interrupt management ******************************/
|
|
if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
|
|
80020a4: 687b ldr r3, [r7, #4]
|
|
80020a6: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80020a8: 2210 movs r2, #16
|
|
80020aa: 409a lsls r2, r3
|
|
80020ac: 68fb ldr r3, [r7, #12]
|
|
80020ae: 4013 ands r3, r2
|
|
80020b0: 2b00 cmp r3, #0
|
|
80020b2: d043 beq.n 800213c <HAL_DMA_IRQHandler+0x170>
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
|
|
80020b4: 687b ldr r3, [r7, #4]
|
|
80020b6: 681b ldr r3, [r3, #0]
|
|
80020b8: 681b ldr r3, [r3, #0]
|
|
80020ba: f003 0308 and.w r3, r3, #8
|
|
80020be: 2b00 cmp r3, #0
|
|
80020c0: d03c beq.n 800213c <HAL_DMA_IRQHandler+0x170>
|
|
{
|
|
/* Clear the half transfer complete flag */
|
|
regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
|
|
80020c2: 687b ldr r3, [r7, #4]
|
|
80020c4: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80020c6: 2210 movs r2, #16
|
|
80020c8: 409a lsls r2, r3
|
|
80020ca: 693b ldr r3, [r7, #16]
|
|
80020cc: 609a str r2, [r3, #8]
|
|
|
|
/* Multi_Buffering mode enabled */
|
|
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
|
|
80020ce: 687b ldr r3, [r7, #4]
|
|
80020d0: 681b ldr r3, [r3, #0]
|
|
80020d2: 681b ldr r3, [r3, #0]
|
|
80020d4: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
80020d8: 2b00 cmp r3, #0
|
|
80020da: d018 beq.n 800210e <HAL_DMA_IRQHandler+0x142>
|
|
{
|
|
/* Current memory buffer used is Memory 0 */
|
|
if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
|
|
80020dc: 687b ldr r3, [r7, #4]
|
|
80020de: 681b ldr r3, [r3, #0]
|
|
80020e0: 681b ldr r3, [r3, #0]
|
|
80020e2: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
80020e6: 2b00 cmp r3, #0
|
|
80020e8: d108 bne.n 80020fc <HAL_DMA_IRQHandler+0x130>
|
|
{
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
80020ea: 687b ldr r3, [r7, #4]
|
|
80020ec: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80020ee: 2b00 cmp r3, #0
|
|
80020f0: d024 beq.n 800213c <HAL_DMA_IRQHandler+0x170>
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferHalfCpltCallback(hdma);
|
|
80020f2: 687b ldr r3, [r7, #4]
|
|
80020f4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80020f6: 6878 ldr r0, [r7, #4]
|
|
80020f8: 4798 blx r3
|
|
80020fa: e01f b.n 800213c <HAL_DMA_IRQHandler+0x170>
|
|
}
|
|
}
|
|
/* Current memory buffer used is Memory 1 */
|
|
else
|
|
{
|
|
if(hdma->XferM1HalfCpltCallback != NULL)
|
|
80020fc: 687b ldr r3, [r7, #4]
|
|
80020fe: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8002100: 2b00 cmp r3, #0
|
|
8002102: d01b beq.n 800213c <HAL_DMA_IRQHandler+0x170>
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferM1HalfCpltCallback(hdma);
|
|
8002104: 687b ldr r3, [r7, #4]
|
|
8002106: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8002108: 6878 ldr r0, [r7, #4]
|
|
800210a: 4798 blx r3
|
|
800210c: e016 b.n 800213c <HAL_DMA_IRQHandler+0x170>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
|
if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
|
|
800210e: 687b ldr r3, [r7, #4]
|
|
8002110: 681b ldr r3, [r3, #0]
|
|
8002112: 681b ldr r3, [r3, #0]
|
|
8002114: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002118: 2b00 cmp r3, #0
|
|
800211a: d107 bne.n 800212c <HAL_DMA_IRQHandler+0x160>
|
|
{
|
|
/* Disable the half transfer interrupt */
|
|
hdma->Instance->CR &= ~(DMA_IT_HT);
|
|
800211c: 687b ldr r3, [r7, #4]
|
|
800211e: 681b ldr r3, [r3, #0]
|
|
8002120: 681a ldr r2, [r3, #0]
|
|
8002122: 687b ldr r3, [r7, #4]
|
|
8002124: 681b ldr r3, [r3, #0]
|
|
8002126: f022 0208 bic.w r2, r2, #8
|
|
800212a: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
800212c: 687b ldr r3, [r7, #4]
|
|
800212e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002130: 2b00 cmp r3, #0
|
|
8002132: d003 beq.n 800213c <HAL_DMA_IRQHandler+0x170>
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferHalfCpltCallback(hdma);
|
|
8002134: 687b ldr r3, [r7, #4]
|
|
8002136: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002138: 6878 ldr r0, [r7, #4]
|
|
800213a: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/* Transfer Complete Interrupt management ***********************************/
|
|
if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
|
|
800213c: 687b ldr r3, [r7, #4]
|
|
800213e: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002140: 2220 movs r2, #32
|
|
8002142: 409a lsls r2, r3
|
|
8002144: 68fb ldr r3, [r7, #12]
|
|
8002146: 4013 ands r3, r2
|
|
8002148: 2b00 cmp r3, #0
|
|
800214a: f000 808f beq.w 800226c <HAL_DMA_IRQHandler+0x2a0>
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
|
|
800214e: 687b ldr r3, [r7, #4]
|
|
8002150: 681b ldr r3, [r3, #0]
|
|
8002152: 681b ldr r3, [r3, #0]
|
|
8002154: f003 0310 and.w r3, r3, #16
|
|
8002158: 2b00 cmp r3, #0
|
|
800215a: f000 8087 beq.w 800226c <HAL_DMA_IRQHandler+0x2a0>
|
|
{
|
|
/* Clear the transfer complete flag */
|
|
regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
|
|
800215e: 687b ldr r3, [r7, #4]
|
|
8002160: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002162: 2220 movs r2, #32
|
|
8002164: 409a lsls r2, r3
|
|
8002166: 693b ldr r3, [r7, #16]
|
|
8002168: 609a str r2, [r3, #8]
|
|
|
|
if(HAL_DMA_STATE_ABORT == hdma->State)
|
|
800216a: 687b ldr r3, [r7, #4]
|
|
800216c: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
|
|
8002170: b2db uxtb r3, r3
|
|
8002172: 2b05 cmp r3, #5
|
|
8002174: d136 bne.n 80021e4 <HAL_DMA_IRQHandler+0x218>
|
|
{
|
|
/* Disable all the transfer interrupts */
|
|
hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
|
|
8002176: 687b ldr r3, [r7, #4]
|
|
8002178: 681b ldr r3, [r3, #0]
|
|
800217a: 681a ldr r2, [r3, #0]
|
|
800217c: 687b ldr r3, [r7, #4]
|
|
800217e: 681b ldr r3, [r3, #0]
|
|
8002180: f022 0216 bic.w r2, r2, #22
|
|
8002184: 601a str r2, [r3, #0]
|
|
hdma->Instance->FCR &= ~(DMA_IT_FE);
|
|
8002186: 687b ldr r3, [r7, #4]
|
|
8002188: 681b ldr r3, [r3, #0]
|
|
800218a: 695a ldr r2, [r3, #20]
|
|
800218c: 687b ldr r3, [r7, #4]
|
|
800218e: 681b ldr r3, [r3, #0]
|
|
8002190: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
8002194: 615a str r2, [r3, #20]
|
|
|
|
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
|
|
8002196: 687b ldr r3, [r7, #4]
|
|
8002198: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800219a: 2b00 cmp r3, #0
|
|
800219c: d103 bne.n 80021a6 <HAL_DMA_IRQHandler+0x1da>
|
|
800219e: 687b ldr r3, [r7, #4]
|
|
80021a0: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
80021a2: 2b00 cmp r3, #0
|
|
80021a4: d007 beq.n 80021b6 <HAL_DMA_IRQHandler+0x1ea>
|
|
{
|
|
hdma->Instance->CR &= ~(DMA_IT_HT);
|
|
80021a6: 687b ldr r3, [r7, #4]
|
|
80021a8: 681b ldr r3, [r3, #0]
|
|
80021aa: 681a ldr r2, [r3, #0]
|
|
80021ac: 687b ldr r3, [r7, #4]
|
|
80021ae: 681b ldr r3, [r3, #0]
|
|
80021b0: f022 0208 bic.w r2, r2, #8
|
|
80021b4: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Clear all interrupt flags at correct offset within the register */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
80021b6: 687b ldr r3, [r7, #4]
|
|
80021b8: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80021ba: 223f movs r2, #63 @ 0x3f
|
|
80021bc: 409a lsls r2, r3
|
|
80021be: 693b ldr r3, [r7, #16]
|
|
80021c0: 609a str r2, [r3, #8]
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80021c2: 687b ldr r3, [r7, #4]
|
|
80021c4: 2201 movs r2, #1
|
|
80021c6: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
80021ca: 687b ldr r3, [r7, #4]
|
|
80021cc: 2200 movs r2, #0
|
|
80021ce: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
|
|
if(hdma->XferAbortCallback != NULL)
|
|
80021d2: 687b ldr r3, [r7, #4]
|
|
80021d4: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80021d6: 2b00 cmp r3, #0
|
|
80021d8: d07e beq.n 80022d8 <HAL_DMA_IRQHandler+0x30c>
|
|
{
|
|
hdma->XferAbortCallback(hdma);
|
|
80021da: 687b ldr r3, [r7, #4]
|
|
80021dc: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80021de: 6878 ldr r0, [r7, #4]
|
|
80021e0: 4798 blx r3
|
|
}
|
|
return;
|
|
80021e2: e079 b.n 80022d8 <HAL_DMA_IRQHandler+0x30c>
|
|
}
|
|
|
|
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
|
|
80021e4: 687b ldr r3, [r7, #4]
|
|
80021e6: 681b ldr r3, [r3, #0]
|
|
80021e8: 681b ldr r3, [r3, #0]
|
|
80021ea: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
80021ee: 2b00 cmp r3, #0
|
|
80021f0: d01d beq.n 800222e <HAL_DMA_IRQHandler+0x262>
|
|
{
|
|
/* Current memory buffer used is Memory 0 */
|
|
if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
|
|
80021f2: 687b ldr r3, [r7, #4]
|
|
80021f4: 681b ldr r3, [r3, #0]
|
|
80021f6: 681b ldr r3, [r3, #0]
|
|
80021f8: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
80021fc: 2b00 cmp r3, #0
|
|
80021fe: d10d bne.n 800221c <HAL_DMA_IRQHandler+0x250>
|
|
{
|
|
if(hdma->XferM1CpltCallback != NULL)
|
|
8002200: 687b ldr r3, [r7, #4]
|
|
8002202: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8002204: 2b00 cmp r3, #0
|
|
8002206: d031 beq.n 800226c <HAL_DMA_IRQHandler+0x2a0>
|
|
{
|
|
/* Transfer complete Callback for memory1 */
|
|
hdma->XferM1CpltCallback(hdma);
|
|
8002208: 687b ldr r3, [r7, #4]
|
|
800220a: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800220c: 6878 ldr r0, [r7, #4]
|
|
800220e: 4798 blx r3
|
|
8002210: e02c b.n 800226c <HAL_DMA_IRQHandler+0x2a0>
|
|
8002212: bf00 nop
|
|
8002214: 20000090 .word 0x20000090
|
|
8002218: 1b4e81b5 .word 0x1b4e81b5
|
|
}
|
|
}
|
|
/* Current memory buffer used is Memory 1 */
|
|
else
|
|
{
|
|
if(hdma->XferCpltCallback != NULL)
|
|
800221c: 687b ldr r3, [r7, #4]
|
|
800221e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8002220: 2b00 cmp r3, #0
|
|
8002222: d023 beq.n 800226c <HAL_DMA_IRQHandler+0x2a0>
|
|
{
|
|
/* Transfer complete Callback for memory0 */
|
|
hdma->XferCpltCallback(hdma);
|
|
8002224: 687b ldr r3, [r7, #4]
|
|
8002226: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8002228: 6878 ldr r0, [r7, #4]
|
|
800222a: 4798 blx r3
|
|
800222c: e01e b.n 800226c <HAL_DMA_IRQHandler+0x2a0>
|
|
}
|
|
}
|
|
/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
|
|
else
|
|
{
|
|
if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
|
|
800222e: 687b ldr r3, [r7, #4]
|
|
8002230: 681b ldr r3, [r3, #0]
|
|
8002232: 681b ldr r3, [r3, #0]
|
|
8002234: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002238: 2b00 cmp r3, #0
|
|
800223a: d10f bne.n 800225c <HAL_DMA_IRQHandler+0x290>
|
|
{
|
|
/* Disable the transfer complete interrupt */
|
|
hdma->Instance->CR &= ~(DMA_IT_TC);
|
|
800223c: 687b ldr r3, [r7, #4]
|
|
800223e: 681b ldr r3, [r3, #0]
|
|
8002240: 681a ldr r2, [r3, #0]
|
|
8002242: 687b ldr r3, [r7, #4]
|
|
8002244: 681b ldr r3, [r3, #0]
|
|
8002246: f022 0210 bic.w r2, r2, #16
|
|
800224a: 601a str r2, [r3, #0]
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
800224c: 687b ldr r3, [r7, #4]
|
|
800224e: 2201 movs r2, #1
|
|
8002250: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8002254: 687b ldr r3, [r7, #4]
|
|
8002256: 2200 movs r2, #0
|
|
8002258: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
}
|
|
|
|
if(hdma->XferCpltCallback != NULL)
|
|
800225c: 687b ldr r3, [r7, #4]
|
|
800225e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8002260: 2b00 cmp r3, #0
|
|
8002262: d003 beq.n 800226c <HAL_DMA_IRQHandler+0x2a0>
|
|
{
|
|
/* Transfer complete callback */
|
|
hdma->XferCpltCallback(hdma);
|
|
8002264: 687b ldr r3, [r7, #4]
|
|
8002266: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8002268: 6878 ldr r0, [r7, #4]
|
|
800226a: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
|
|
/* manage error case */
|
|
if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
|
|
800226c: 687b ldr r3, [r7, #4]
|
|
800226e: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8002270: 2b00 cmp r3, #0
|
|
8002272: d032 beq.n 80022da <HAL_DMA_IRQHandler+0x30e>
|
|
{
|
|
if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
|
|
8002274: 687b ldr r3, [r7, #4]
|
|
8002276: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8002278: f003 0301 and.w r3, r3, #1
|
|
800227c: 2b00 cmp r3, #0
|
|
800227e: d022 beq.n 80022c6 <HAL_DMA_IRQHandler+0x2fa>
|
|
{
|
|
hdma->State = HAL_DMA_STATE_ABORT;
|
|
8002280: 687b ldr r3, [r7, #4]
|
|
8002282: 2205 movs r2, #5
|
|
8002284: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Disable the stream */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8002288: 687b ldr r3, [r7, #4]
|
|
800228a: 681b ldr r3, [r3, #0]
|
|
800228c: 681a ldr r2, [r3, #0]
|
|
800228e: 687b ldr r3, [r7, #4]
|
|
8002290: 681b ldr r3, [r3, #0]
|
|
8002292: f022 0201 bic.w r2, r2, #1
|
|
8002296: 601a str r2, [r3, #0]
|
|
|
|
do
|
|
{
|
|
if (++count > timeout)
|
|
8002298: 68bb ldr r3, [r7, #8]
|
|
800229a: 3301 adds r3, #1
|
|
800229c: 60bb str r3, [r7, #8]
|
|
800229e: 697a ldr r2, [r7, #20]
|
|
80022a0: 429a cmp r2, r3
|
|
80022a2: d307 bcc.n 80022b4 <HAL_DMA_IRQHandler+0x2e8>
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
|
|
80022a4: 687b ldr r3, [r7, #4]
|
|
80022a6: 681b ldr r3, [r3, #0]
|
|
80022a8: 681b ldr r3, [r3, #0]
|
|
80022aa: f003 0301 and.w r3, r3, #1
|
|
80022ae: 2b00 cmp r3, #0
|
|
80022b0: d1f2 bne.n 8002298 <HAL_DMA_IRQHandler+0x2cc>
|
|
80022b2: e000 b.n 80022b6 <HAL_DMA_IRQHandler+0x2ea>
|
|
break;
|
|
80022b4: bf00 nop
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80022b6: 687b ldr r3, [r7, #4]
|
|
80022b8: 2201 movs r2, #1
|
|
80022ba: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
80022be: 687b ldr r3, [r7, #4]
|
|
80022c0: 2200 movs r2, #0
|
|
80022c2: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
}
|
|
|
|
if(hdma->XferErrorCallback != NULL)
|
|
80022c6: 687b ldr r3, [r7, #4]
|
|
80022c8: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80022ca: 2b00 cmp r3, #0
|
|
80022cc: d005 beq.n 80022da <HAL_DMA_IRQHandler+0x30e>
|
|
{
|
|
/* Transfer error callback */
|
|
hdma->XferErrorCallback(hdma);
|
|
80022ce: 687b ldr r3, [r7, #4]
|
|
80022d0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80022d2: 6878 ldr r0, [r7, #4]
|
|
80022d4: 4798 blx r3
|
|
80022d6: e000 b.n 80022da <HAL_DMA_IRQHandler+0x30e>
|
|
return;
|
|
80022d8: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
80022da: 3718 adds r7, #24
|
|
80022dc: 46bd mov sp, r7
|
|
80022de: bd80 pop {r7, pc}
|
|
|
|
080022e0 <DMA_SetConfig>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
80022e0: b480 push {r7}
|
|
80022e2: b085 sub sp, #20
|
|
80022e4: af00 add r7, sp, #0
|
|
80022e6: 60f8 str r0, [r7, #12]
|
|
80022e8: 60b9 str r1, [r7, #8]
|
|
80022ea: 607a str r2, [r7, #4]
|
|
80022ec: 603b str r3, [r7, #0]
|
|
/* Clear DBM bit */
|
|
hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
|
|
80022ee: 68fb ldr r3, [r7, #12]
|
|
80022f0: 681b ldr r3, [r3, #0]
|
|
80022f2: 681a ldr r2, [r3, #0]
|
|
80022f4: 68fb ldr r3, [r7, #12]
|
|
80022f6: 681b ldr r3, [r3, #0]
|
|
80022f8: f422 2280 bic.w r2, r2, #262144 @ 0x40000
|
|
80022fc: 601a str r2, [r3, #0]
|
|
|
|
/* Configure DMA Stream data length */
|
|
hdma->Instance->NDTR = DataLength;
|
|
80022fe: 68fb ldr r3, [r7, #12]
|
|
8002300: 681b ldr r3, [r3, #0]
|
|
8002302: 683a ldr r2, [r7, #0]
|
|
8002304: 605a str r2, [r3, #4]
|
|
|
|
/* Memory to Peripheral */
|
|
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
|
8002306: 68fb ldr r3, [r7, #12]
|
|
8002308: 689b ldr r3, [r3, #8]
|
|
800230a: 2b40 cmp r3, #64 @ 0x40
|
|
800230c: d108 bne.n 8002320 <DMA_SetConfig+0x40>
|
|
{
|
|
/* Configure DMA Stream destination address */
|
|
hdma->Instance->PAR = DstAddress;
|
|
800230e: 68fb ldr r3, [r7, #12]
|
|
8002310: 681b ldr r3, [r3, #0]
|
|
8002312: 687a ldr r2, [r7, #4]
|
|
8002314: 609a str r2, [r3, #8]
|
|
|
|
/* Configure DMA Stream source address */
|
|
hdma->Instance->M0AR = SrcAddress;
|
|
8002316: 68fb ldr r3, [r7, #12]
|
|
8002318: 681b ldr r3, [r3, #0]
|
|
800231a: 68ba ldr r2, [r7, #8]
|
|
800231c: 60da str r2, [r3, #12]
|
|
hdma->Instance->PAR = SrcAddress;
|
|
|
|
/* Configure DMA Stream destination address */
|
|
hdma->Instance->M0AR = DstAddress;
|
|
}
|
|
}
|
|
800231e: e007 b.n 8002330 <DMA_SetConfig+0x50>
|
|
hdma->Instance->PAR = SrcAddress;
|
|
8002320: 68fb ldr r3, [r7, #12]
|
|
8002322: 681b ldr r3, [r3, #0]
|
|
8002324: 68ba ldr r2, [r7, #8]
|
|
8002326: 609a str r2, [r3, #8]
|
|
hdma->Instance->M0AR = DstAddress;
|
|
8002328: 68fb ldr r3, [r7, #12]
|
|
800232a: 681b ldr r3, [r3, #0]
|
|
800232c: 687a ldr r2, [r7, #4]
|
|
800232e: 60da str r2, [r3, #12]
|
|
}
|
|
8002330: bf00 nop
|
|
8002332: 3714 adds r7, #20
|
|
8002334: 46bd mov sp, r7
|
|
8002336: f85d 7b04 ldr.w r7, [sp], #4
|
|
800233a: 4770 bx lr
|
|
|
|
0800233c <DMA_CalcBaseAndBitshift>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval Stream base address
|
|
*/
|
|
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800233c: b480 push {r7}
|
|
800233e: b085 sub sp, #20
|
|
8002340: af00 add r7, sp, #0
|
|
8002342: 6078 str r0, [r7, #4]
|
|
uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
|
|
8002344: 687b ldr r3, [r7, #4]
|
|
8002346: 681b ldr r3, [r3, #0]
|
|
8002348: b2db uxtb r3, r3
|
|
800234a: 3b10 subs r3, #16
|
|
800234c: 4a14 ldr r2, [pc, #80] @ (80023a0 <DMA_CalcBaseAndBitshift+0x64>)
|
|
800234e: fba2 2303 umull r2, r3, r2, r3
|
|
8002352: 091b lsrs r3, r3, #4
|
|
8002354: 60fb str r3, [r7, #12]
|
|
|
|
/* lookup table for necessary bitshift of flags within status registers */
|
|
static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
|
|
hdma->StreamIndex = flagBitshiftOffset[stream_number];
|
|
8002356: 4a13 ldr r2, [pc, #76] @ (80023a4 <DMA_CalcBaseAndBitshift+0x68>)
|
|
8002358: 68fb ldr r3, [r7, #12]
|
|
800235a: 4413 add r3, r2
|
|
800235c: 781b ldrb r3, [r3, #0]
|
|
800235e: 461a mov r2, r3
|
|
8002360: 687b ldr r3, [r7, #4]
|
|
8002362: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
if (stream_number > 3U)
|
|
8002364: 68fb ldr r3, [r7, #12]
|
|
8002366: 2b03 cmp r3, #3
|
|
8002368: d909 bls.n 800237e <DMA_CalcBaseAndBitshift+0x42>
|
|
{
|
|
/* return pointer to HISR and HIFCR */
|
|
hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
|
|
800236a: 687b ldr r3, [r7, #4]
|
|
800236c: 681b ldr r3, [r3, #0]
|
|
800236e: f423 737f bic.w r3, r3, #1020 @ 0x3fc
|
|
8002372: f023 0303 bic.w r3, r3, #3
|
|
8002376: 1d1a adds r2, r3, #4
|
|
8002378: 687b ldr r3, [r7, #4]
|
|
800237a: 659a str r2, [r3, #88] @ 0x58
|
|
800237c: e007 b.n 800238e <DMA_CalcBaseAndBitshift+0x52>
|
|
}
|
|
else
|
|
{
|
|
/* return pointer to LISR and LIFCR */
|
|
hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
|
|
800237e: 687b ldr r3, [r7, #4]
|
|
8002380: 681b ldr r3, [r3, #0]
|
|
8002382: f423 737f bic.w r3, r3, #1020 @ 0x3fc
|
|
8002386: f023 0303 bic.w r3, r3, #3
|
|
800238a: 687a ldr r2, [r7, #4]
|
|
800238c: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
|
|
return hdma->StreamBaseAddress;
|
|
800238e: 687b ldr r3, [r7, #4]
|
|
8002390: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
}
|
|
8002392: 4618 mov r0, r3
|
|
8002394: 3714 adds r7, #20
|
|
8002396: 46bd mov sp, r7
|
|
8002398: f85d 7b04 ldr.w r7, [sp], #4
|
|
800239c: 4770 bx lr
|
|
800239e: bf00 nop
|
|
80023a0: aaaaaaab .word 0xaaaaaaab
|
|
80023a4: 0800aa08 .word 0x0800aa08
|
|
|
|
080023a8 <DMA_CheckFifoParam>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80023a8: b480 push {r7}
|
|
80023aa: b085 sub sp, #20
|
|
80023ac: af00 add r7, sp, #0
|
|
80023ae: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80023b0: 2300 movs r3, #0
|
|
80023b2: 73fb strb r3, [r7, #15]
|
|
uint32_t tmp = hdma->Init.FIFOThreshold;
|
|
80023b4: 687b ldr r3, [r7, #4]
|
|
80023b6: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80023b8: 60bb str r3, [r7, #8]
|
|
|
|
/* Memory Data size equal to Byte */
|
|
if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
|
|
80023ba: 687b ldr r3, [r7, #4]
|
|
80023bc: 699b ldr r3, [r3, #24]
|
|
80023be: 2b00 cmp r3, #0
|
|
80023c0: d11f bne.n 8002402 <DMA_CheckFifoParam+0x5a>
|
|
{
|
|
switch (tmp)
|
|
80023c2: 68bb ldr r3, [r7, #8]
|
|
80023c4: 2b03 cmp r3, #3
|
|
80023c6: d856 bhi.n 8002476 <DMA_CheckFifoParam+0xce>
|
|
80023c8: a201 add r2, pc, #4 @ (adr r2, 80023d0 <DMA_CheckFifoParam+0x28>)
|
|
80023ca: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80023ce: bf00 nop
|
|
80023d0: 080023e1 .word 0x080023e1
|
|
80023d4: 080023f3 .word 0x080023f3
|
|
80023d8: 080023e1 .word 0x080023e1
|
|
80023dc: 08002477 .word 0x08002477
|
|
{
|
|
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
|
|
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
|
|
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
|
|
80023e0: 687b ldr r3, [r7, #4]
|
|
80023e2: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80023e4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
80023e8: 2b00 cmp r3, #0
|
|
80023ea: d046 beq.n 800247a <DMA_CheckFifoParam+0xd2>
|
|
{
|
|
status = HAL_ERROR;
|
|
80023ec: 2301 movs r3, #1
|
|
80023ee: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
80023f0: e043 b.n 800247a <DMA_CheckFifoParam+0xd2>
|
|
case DMA_FIFO_THRESHOLD_HALFFULL:
|
|
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
|
|
80023f2: 687b ldr r3, [r7, #4]
|
|
80023f4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80023f6: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000
|
|
80023fa: d140 bne.n 800247e <DMA_CheckFifoParam+0xd6>
|
|
{
|
|
status = HAL_ERROR;
|
|
80023fc: 2301 movs r3, #1
|
|
80023fe: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8002400: e03d b.n 800247e <DMA_CheckFifoParam+0xd6>
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Memory Data size equal to Half-Word */
|
|
else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
|
|
8002402: 687b ldr r3, [r7, #4]
|
|
8002404: 699b ldr r3, [r3, #24]
|
|
8002406: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
800240a: d121 bne.n 8002450 <DMA_CheckFifoParam+0xa8>
|
|
{
|
|
switch (tmp)
|
|
800240c: 68bb ldr r3, [r7, #8]
|
|
800240e: 2b03 cmp r3, #3
|
|
8002410: d837 bhi.n 8002482 <DMA_CheckFifoParam+0xda>
|
|
8002412: a201 add r2, pc, #4 @ (adr r2, 8002418 <DMA_CheckFifoParam+0x70>)
|
|
8002414: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8002418: 08002429 .word 0x08002429
|
|
800241c: 0800242f .word 0x0800242f
|
|
8002420: 08002429 .word 0x08002429
|
|
8002424: 08002441 .word 0x08002441
|
|
{
|
|
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
|
|
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
|
|
status = HAL_ERROR;
|
|
8002428: 2301 movs r3, #1
|
|
800242a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800242c: e030 b.n 8002490 <DMA_CheckFifoParam+0xe8>
|
|
case DMA_FIFO_THRESHOLD_HALFFULL:
|
|
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
|
|
800242e: 687b ldr r3, [r7, #4]
|
|
8002430: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8002432: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
8002436: 2b00 cmp r3, #0
|
|
8002438: d025 beq.n 8002486 <DMA_CheckFifoParam+0xde>
|
|
{
|
|
status = HAL_ERROR;
|
|
800243a: 2301 movs r3, #1
|
|
800243c: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
800243e: e022 b.n 8002486 <DMA_CheckFifoParam+0xde>
|
|
case DMA_FIFO_THRESHOLD_FULL:
|
|
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
|
|
8002440: 687b ldr r3, [r7, #4]
|
|
8002442: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8002444: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000
|
|
8002448: d11f bne.n 800248a <DMA_CheckFifoParam+0xe2>
|
|
{
|
|
status = HAL_ERROR;
|
|
800244a: 2301 movs r3, #1
|
|
800244c: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
800244e: e01c b.n 800248a <DMA_CheckFifoParam+0xe2>
|
|
}
|
|
|
|
/* Memory Data size equal to Word */
|
|
else
|
|
{
|
|
switch (tmp)
|
|
8002450: 68bb ldr r3, [r7, #8]
|
|
8002452: 2b02 cmp r3, #2
|
|
8002454: d903 bls.n 800245e <DMA_CheckFifoParam+0xb6>
|
|
8002456: 68bb ldr r3, [r7, #8]
|
|
8002458: 2b03 cmp r3, #3
|
|
800245a: d003 beq.n 8002464 <DMA_CheckFifoParam+0xbc>
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
800245c: e018 b.n 8002490 <DMA_CheckFifoParam+0xe8>
|
|
status = HAL_ERROR;
|
|
800245e: 2301 movs r3, #1
|
|
8002460: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8002462: e015 b.n 8002490 <DMA_CheckFifoParam+0xe8>
|
|
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
|
|
8002464: 687b ldr r3, [r7, #4]
|
|
8002466: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8002468: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
800246c: 2b00 cmp r3, #0
|
|
800246e: d00e beq.n 800248e <DMA_CheckFifoParam+0xe6>
|
|
status = HAL_ERROR;
|
|
8002470: 2301 movs r3, #1
|
|
8002472: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8002474: e00b b.n 800248e <DMA_CheckFifoParam+0xe6>
|
|
break;
|
|
8002476: bf00 nop
|
|
8002478: e00a b.n 8002490 <DMA_CheckFifoParam+0xe8>
|
|
break;
|
|
800247a: bf00 nop
|
|
800247c: e008 b.n 8002490 <DMA_CheckFifoParam+0xe8>
|
|
break;
|
|
800247e: bf00 nop
|
|
8002480: e006 b.n 8002490 <DMA_CheckFifoParam+0xe8>
|
|
break;
|
|
8002482: bf00 nop
|
|
8002484: e004 b.n 8002490 <DMA_CheckFifoParam+0xe8>
|
|
break;
|
|
8002486: bf00 nop
|
|
8002488: e002 b.n 8002490 <DMA_CheckFifoParam+0xe8>
|
|
break;
|
|
800248a: bf00 nop
|
|
800248c: e000 b.n 8002490 <DMA_CheckFifoParam+0xe8>
|
|
break;
|
|
800248e: bf00 nop
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8002490: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8002492: 4618 mov r0, r3
|
|
8002494: 3714 adds r7, #20
|
|
8002496: 46bd mov sp, r7
|
|
8002498: f85d 7b04 ldr.w r7, [sp], #4
|
|
800249c: 4770 bx lr
|
|
800249e: bf00 nop
|
|
|
|
080024a0 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
80024a0: b480 push {r7}
|
|
80024a2: b089 sub sp, #36 @ 0x24
|
|
80024a4: af00 add r7, sp, #0
|
|
80024a6: 6078 str r0, [r7, #4]
|
|
80024a8: 6039 str r1, [r7, #0]
|
|
uint32_t position;
|
|
uint32_t ioposition = 0x00U;
|
|
80024aa: 2300 movs r3, #0
|
|
80024ac: 617b str r3, [r7, #20]
|
|
uint32_t iocurrent = 0x00U;
|
|
80024ae: 2300 movs r3, #0
|
|
80024b0: 613b str r3, [r7, #16]
|
|
uint32_t temp = 0x00U;
|
|
80024b2: 2300 movs r3, #0
|
|
80024b4: 61bb str r3, [r7, #24]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
80024b6: 2300 movs r3, #0
|
|
80024b8: 61fb str r3, [r7, #28]
|
|
80024ba: e165 b.n 8002788 <HAL_GPIO_Init+0x2e8>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = 0x01U << position;
|
|
80024bc: 2201 movs r2, #1
|
|
80024be: 69fb ldr r3, [r7, #28]
|
|
80024c0: fa02 f303 lsl.w r3, r2, r3
|
|
80024c4: 617b str r3, [r7, #20]
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
80024c6: 683b ldr r3, [r7, #0]
|
|
80024c8: 681b ldr r3, [r3, #0]
|
|
80024ca: 697a ldr r2, [r7, #20]
|
|
80024cc: 4013 ands r3, r2
|
|
80024ce: 613b str r3, [r7, #16]
|
|
|
|
if(iocurrent == ioposition)
|
|
80024d0: 693a ldr r2, [r7, #16]
|
|
80024d2: 697b ldr r3, [r7, #20]
|
|
80024d4: 429a cmp r2, r3
|
|
80024d6: f040 8154 bne.w 8002782 <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
80024da: 683b ldr r3, [r7, #0]
|
|
80024dc: 685b ldr r3, [r3, #4]
|
|
80024de: f003 0303 and.w r3, r3, #3
|
|
80024e2: 2b01 cmp r3, #1
|
|
80024e4: d005 beq.n 80024f2 <HAL_GPIO_Init+0x52>
|
|
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
80024e6: 683b ldr r3, [r7, #0]
|
|
80024e8: 685b ldr r3, [r3, #4]
|
|
80024ea: f003 0303 and.w r3, r3, #3
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
80024ee: 2b02 cmp r3, #2
|
|
80024f0: d130 bne.n 8002554 <HAL_GPIO_Init+0xb4>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
80024f2: 687b ldr r3, [r7, #4]
|
|
80024f4: 689b ldr r3, [r3, #8]
|
|
80024f6: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
|
80024f8: 69fb ldr r3, [r7, #28]
|
|
80024fa: 005b lsls r3, r3, #1
|
|
80024fc: 2203 movs r2, #3
|
|
80024fe: fa02 f303 lsl.w r3, r2, r3
|
|
8002502: 43db mvns r3, r3
|
|
8002504: 69ba ldr r2, [r7, #24]
|
|
8002506: 4013 ands r3, r2
|
|
8002508: 61bb str r3, [r7, #24]
|
|
temp |= (GPIO_Init->Speed << (position * 2U));
|
|
800250a: 683b ldr r3, [r7, #0]
|
|
800250c: 68da ldr r2, [r3, #12]
|
|
800250e: 69fb ldr r3, [r7, #28]
|
|
8002510: 005b lsls r3, r3, #1
|
|
8002512: fa02 f303 lsl.w r3, r2, r3
|
|
8002516: 69ba ldr r2, [r7, #24]
|
|
8002518: 4313 orrs r3, r2
|
|
800251a: 61bb str r3, [r7, #24]
|
|
GPIOx->OSPEEDR = temp;
|
|
800251c: 687b ldr r3, [r7, #4]
|
|
800251e: 69ba ldr r2, [r7, #24]
|
|
8002520: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8002522: 687b ldr r3, [r7, #4]
|
|
8002524: 685b ldr r3, [r3, #4]
|
|
8002526: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
8002528: 2201 movs r2, #1
|
|
800252a: 69fb ldr r3, [r7, #28]
|
|
800252c: fa02 f303 lsl.w r3, r2, r3
|
|
8002530: 43db mvns r3, r3
|
|
8002532: 69ba ldr r2, [r7, #24]
|
|
8002534: 4013 ands r3, r2
|
|
8002536: 61bb str r3, [r7, #24]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8002538: 683b ldr r3, [r7, #0]
|
|
800253a: 685b ldr r3, [r3, #4]
|
|
800253c: 091b lsrs r3, r3, #4
|
|
800253e: f003 0201 and.w r2, r3, #1
|
|
8002542: 69fb ldr r3, [r7, #28]
|
|
8002544: fa02 f303 lsl.w r3, r2, r3
|
|
8002548: 69ba ldr r2, [r7, #24]
|
|
800254a: 4313 orrs r3, r2
|
|
800254c: 61bb str r3, [r7, #24]
|
|
GPIOx->OTYPER = temp;
|
|
800254e: 687b ldr r3, [r7, #4]
|
|
8002550: 69ba ldr r2, [r7, #24]
|
|
8002552: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
8002554: 683b ldr r3, [r7, #0]
|
|
8002556: 685b ldr r3, [r3, #4]
|
|
8002558: f003 0303 and.w r3, r3, #3
|
|
800255c: 2b03 cmp r3, #3
|
|
800255e: d017 beq.n 8002590 <HAL_GPIO_Init+0xf0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
8002560: 687b ldr r3, [r7, #4]
|
|
8002562: 68db ldr r3, [r3, #12]
|
|
8002564: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
|
8002566: 69fb ldr r3, [r7, #28]
|
|
8002568: 005b lsls r3, r3, #1
|
|
800256a: 2203 movs r2, #3
|
|
800256c: fa02 f303 lsl.w r3, r2, r3
|
|
8002570: 43db mvns r3, r3
|
|
8002572: 69ba ldr r2, [r7, #24]
|
|
8002574: 4013 ands r3, r2
|
|
8002576: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
8002578: 683b ldr r3, [r7, #0]
|
|
800257a: 689a ldr r2, [r3, #8]
|
|
800257c: 69fb ldr r3, [r7, #28]
|
|
800257e: 005b lsls r3, r3, #1
|
|
8002580: fa02 f303 lsl.w r3, r2, r3
|
|
8002584: 69ba ldr r2, [r7, #24]
|
|
8002586: 4313 orrs r3, r2
|
|
8002588: 61bb str r3, [r7, #24]
|
|
GPIOx->PUPDR = temp;
|
|
800258a: 687b ldr r3, [r7, #4]
|
|
800258c: 69ba ldr r2, [r7, #24]
|
|
800258e: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8002590: 683b ldr r3, [r7, #0]
|
|
8002592: 685b ldr r3, [r3, #4]
|
|
8002594: f003 0303 and.w r3, r3, #3
|
|
8002598: 2b02 cmp r3, #2
|
|
800259a: d123 bne.n 80025e4 <HAL_GPIO_Init+0x144>
|
|
{
|
|
/* Check the Alternate function parameter */
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3U];
|
|
800259c: 69fb ldr r3, [r7, #28]
|
|
800259e: 08da lsrs r2, r3, #3
|
|
80025a0: 687b ldr r3, [r7, #4]
|
|
80025a2: 3208 adds r2, #8
|
|
80025a4: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80025a8: 61bb str r3, [r7, #24]
|
|
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
|
|
80025aa: 69fb ldr r3, [r7, #28]
|
|
80025ac: f003 0307 and.w r3, r3, #7
|
|
80025b0: 009b lsls r3, r3, #2
|
|
80025b2: 220f movs r2, #15
|
|
80025b4: fa02 f303 lsl.w r3, r2, r3
|
|
80025b8: 43db mvns r3, r3
|
|
80025ba: 69ba ldr r2, [r7, #24]
|
|
80025bc: 4013 ands r3, r2
|
|
80025be: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
|
|
80025c0: 683b ldr r3, [r7, #0]
|
|
80025c2: 691a ldr r2, [r3, #16]
|
|
80025c4: 69fb ldr r3, [r7, #28]
|
|
80025c6: f003 0307 and.w r3, r3, #7
|
|
80025ca: 009b lsls r3, r3, #2
|
|
80025cc: fa02 f303 lsl.w r3, r2, r3
|
|
80025d0: 69ba ldr r2, [r7, #24]
|
|
80025d2: 4313 orrs r3, r2
|
|
80025d4: 61bb str r3, [r7, #24]
|
|
GPIOx->AFR[position >> 3U] = temp;
|
|
80025d6: 69fb ldr r3, [r7, #28]
|
|
80025d8: 08da lsrs r2, r3, #3
|
|
80025da: 687b ldr r3, [r7, #4]
|
|
80025dc: 3208 adds r2, #8
|
|
80025de: 69b9 ldr r1, [r7, #24]
|
|
80025e0: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
80025e4: 687b ldr r3, [r7, #4]
|
|
80025e6: 681b ldr r3, [r3, #0]
|
|
80025e8: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
|
80025ea: 69fb ldr r3, [r7, #28]
|
|
80025ec: 005b lsls r3, r3, #1
|
|
80025ee: 2203 movs r2, #3
|
|
80025f0: fa02 f303 lsl.w r3, r2, r3
|
|
80025f4: 43db mvns r3, r3
|
|
80025f6: 69ba ldr r2, [r7, #24]
|
|
80025f8: 4013 ands r3, r2
|
|
80025fa: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
|
80025fc: 683b ldr r3, [r7, #0]
|
|
80025fe: 685b ldr r3, [r3, #4]
|
|
8002600: f003 0203 and.w r2, r3, #3
|
|
8002604: 69fb ldr r3, [r7, #28]
|
|
8002606: 005b lsls r3, r3, #1
|
|
8002608: fa02 f303 lsl.w r3, r2, r3
|
|
800260c: 69ba ldr r2, [r7, #24]
|
|
800260e: 4313 orrs r3, r2
|
|
8002610: 61bb str r3, [r7, #24]
|
|
GPIOx->MODER = temp;
|
|
8002612: 687b ldr r3, [r7, #4]
|
|
8002614: 69ba ldr r2, [r7, #24]
|
|
8002616: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
|
|
8002618: 683b ldr r3, [r7, #0]
|
|
800261a: 685b ldr r3, [r3, #4]
|
|
800261c: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8002620: 2b00 cmp r3, #0
|
|
8002622: f000 80ae beq.w 8002782 <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8002626: 2300 movs r3, #0
|
|
8002628: 60fb str r3, [r7, #12]
|
|
800262a: 4b5d ldr r3, [pc, #372] @ (80027a0 <HAL_GPIO_Init+0x300>)
|
|
800262c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800262e: 4a5c ldr r2, [pc, #368] @ (80027a0 <HAL_GPIO_Init+0x300>)
|
|
8002630: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8002634: 6453 str r3, [r2, #68] @ 0x44
|
|
8002636: 4b5a ldr r3, [pc, #360] @ (80027a0 <HAL_GPIO_Init+0x300>)
|
|
8002638: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800263a: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800263e: 60fb str r3, [r7, #12]
|
|
8002640: 68fb ldr r3, [r7, #12]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2U];
|
|
8002642: 4a58 ldr r2, [pc, #352] @ (80027a4 <HAL_GPIO_Init+0x304>)
|
|
8002644: 69fb ldr r3, [r7, #28]
|
|
8002646: 089b lsrs r3, r3, #2
|
|
8002648: 3302 adds r3, #2
|
|
800264a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
800264e: 61bb str r3, [r7, #24]
|
|
temp &= ~(0x0FU << (4U * (position & 0x03U)));
|
|
8002650: 69fb ldr r3, [r7, #28]
|
|
8002652: f003 0303 and.w r3, r3, #3
|
|
8002656: 009b lsls r3, r3, #2
|
|
8002658: 220f movs r2, #15
|
|
800265a: fa02 f303 lsl.w r3, r2, r3
|
|
800265e: 43db mvns r3, r3
|
|
8002660: 69ba ldr r2, [r7, #24]
|
|
8002662: 4013 ands r3, r2
|
|
8002664: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
|
|
8002666: 687b ldr r3, [r7, #4]
|
|
8002668: 4a4f ldr r2, [pc, #316] @ (80027a8 <HAL_GPIO_Init+0x308>)
|
|
800266a: 4293 cmp r3, r2
|
|
800266c: d025 beq.n 80026ba <HAL_GPIO_Init+0x21a>
|
|
800266e: 687b ldr r3, [r7, #4]
|
|
8002670: 4a4e ldr r2, [pc, #312] @ (80027ac <HAL_GPIO_Init+0x30c>)
|
|
8002672: 4293 cmp r3, r2
|
|
8002674: d01f beq.n 80026b6 <HAL_GPIO_Init+0x216>
|
|
8002676: 687b ldr r3, [r7, #4]
|
|
8002678: 4a4d ldr r2, [pc, #308] @ (80027b0 <HAL_GPIO_Init+0x310>)
|
|
800267a: 4293 cmp r3, r2
|
|
800267c: d019 beq.n 80026b2 <HAL_GPIO_Init+0x212>
|
|
800267e: 687b ldr r3, [r7, #4]
|
|
8002680: 4a4c ldr r2, [pc, #304] @ (80027b4 <HAL_GPIO_Init+0x314>)
|
|
8002682: 4293 cmp r3, r2
|
|
8002684: d013 beq.n 80026ae <HAL_GPIO_Init+0x20e>
|
|
8002686: 687b ldr r3, [r7, #4]
|
|
8002688: 4a4b ldr r2, [pc, #300] @ (80027b8 <HAL_GPIO_Init+0x318>)
|
|
800268a: 4293 cmp r3, r2
|
|
800268c: d00d beq.n 80026aa <HAL_GPIO_Init+0x20a>
|
|
800268e: 687b ldr r3, [r7, #4]
|
|
8002690: 4a4a ldr r2, [pc, #296] @ (80027bc <HAL_GPIO_Init+0x31c>)
|
|
8002692: 4293 cmp r3, r2
|
|
8002694: d007 beq.n 80026a6 <HAL_GPIO_Init+0x206>
|
|
8002696: 687b ldr r3, [r7, #4]
|
|
8002698: 4a49 ldr r2, [pc, #292] @ (80027c0 <HAL_GPIO_Init+0x320>)
|
|
800269a: 4293 cmp r3, r2
|
|
800269c: d101 bne.n 80026a2 <HAL_GPIO_Init+0x202>
|
|
800269e: 2306 movs r3, #6
|
|
80026a0: e00c b.n 80026bc <HAL_GPIO_Init+0x21c>
|
|
80026a2: 2307 movs r3, #7
|
|
80026a4: e00a b.n 80026bc <HAL_GPIO_Init+0x21c>
|
|
80026a6: 2305 movs r3, #5
|
|
80026a8: e008 b.n 80026bc <HAL_GPIO_Init+0x21c>
|
|
80026aa: 2304 movs r3, #4
|
|
80026ac: e006 b.n 80026bc <HAL_GPIO_Init+0x21c>
|
|
80026ae: 2303 movs r3, #3
|
|
80026b0: e004 b.n 80026bc <HAL_GPIO_Init+0x21c>
|
|
80026b2: 2302 movs r3, #2
|
|
80026b4: e002 b.n 80026bc <HAL_GPIO_Init+0x21c>
|
|
80026b6: 2301 movs r3, #1
|
|
80026b8: e000 b.n 80026bc <HAL_GPIO_Init+0x21c>
|
|
80026ba: 2300 movs r3, #0
|
|
80026bc: 69fa ldr r2, [r7, #28]
|
|
80026be: f002 0203 and.w r2, r2, #3
|
|
80026c2: 0092 lsls r2, r2, #2
|
|
80026c4: 4093 lsls r3, r2
|
|
80026c6: 69ba ldr r2, [r7, #24]
|
|
80026c8: 4313 orrs r3, r2
|
|
80026ca: 61bb str r3, [r7, #24]
|
|
SYSCFG->EXTICR[position >> 2U] = temp;
|
|
80026cc: 4935 ldr r1, [pc, #212] @ (80027a4 <HAL_GPIO_Init+0x304>)
|
|
80026ce: 69fb ldr r3, [r7, #28]
|
|
80026d0: 089b lsrs r3, r3, #2
|
|
80026d2: 3302 adds r3, #2
|
|
80026d4: 69ba ldr r2, [r7, #24]
|
|
80026d6: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR;
|
|
80026da: 4b3a ldr r3, [pc, #232] @ (80027c4 <HAL_GPIO_Init+0x324>)
|
|
80026dc: 689b ldr r3, [r3, #8]
|
|
80026de: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
80026e0: 693b ldr r3, [r7, #16]
|
|
80026e2: 43db mvns r3, r3
|
|
80026e4: 69ba ldr r2, [r7, #24]
|
|
80026e6: 4013 ands r3, r2
|
|
80026e8: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
|
|
80026ea: 683b ldr r3, [r7, #0]
|
|
80026ec: 685b ldr r3, [r3, #4]
|
|
80026ee: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
80026f2: 2b00 cmp r3, #0
|
|
80026f4: d003 beq.n 80026fe <HAL_GPIO_Init+0x25e>
|
|
{
|
|
temp |= iocurrent;
|
|
80026f6: 69ba ldr r2, [r7, #24]
|
|
80026f8: 693b ldr r3, [r7, #16]
|
|
80026fa: 4313 orrs r3, r2
|
|
80026fc: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->RTSR = temp;
|
|
80026fe: 4a31 ldr r2, [pc, #196] @ (80027c4 <HAL_GPIO_Init+0x324>)
|
|
8002700: 69bb ldr r3, [r7, #24]
|
|
8002702: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR;
|
|
8002704: 4b2f ldr r3, [pc, #188] @ (80027c4 <HAL_GPIO_Init+0x324>)
|
|
8002706: 68db ldr r3, [r3, #12]
|
|
8002708: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
800270a: 693b ldr r3, [r7, #16]
|
|
800270c: 43db mvns r3, r3
|
|
800270e: 69ba ldr r2, [r7, #24]
|
|
8002710: 4013 ands r3, r2
|
|
8002712: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
|
|
8002714: 683b ldr r3, [r7, #0]
|
|
8002716: 685b ldr r3, [r3, #4]
|
|
8002718: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
800271c: 2b00 cmp r3, #0
|
|
800271e: d003 beq.n 8002728 <HAL_GPIO_Init+0x288>
|
|
{
|
|
temp |= iocurrent;
|
|
8002720: 69ba ldr r2, [r7, #24]
|
|
8002722: 693b ldr r3, [r7, #16]
|
|
8002724: 4313 orrs r3, r2
|
|
8002726: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->FTSR = temp;
|
|
8002728: 4a26 ldr r2, [pc, #152] @ (80027c4 <HAL_GPIO_Init+0x324>)
|
|
800272a: 69bb ldr r3, [r7, #24]
|
|
800272c: 60d3 str r3, [r2, #12]
|
|
|
|
temp = EXTI->EMR;
|
|
800272e: 4b25 ldr r3, [pc, #148] @ (80027c4 <HAL_GPIO_Init+0x324>)
|
|
8002730: 685b ldr r3, [r3, #4]
|
|
8002732: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8002734: 693b ldr r3, [r7, #16]
|
|
8002736: 43db mvns r3, r3
|
|
8002738: 69ba ldr r2, [r7, #24]
|
|
800273a: 4013 ands r3, r2
|
|
800273c: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
|
|
800273e: 683b ldr r3, [r7, #0]
|
|
8002740: 685b ldr r3, [r3, #4]
|
|
8002742: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8002746: 2b00 cmp r3, #0
|
|
8002748: d003 beq.n 8002752 <HAL_GPIO_Init+0x2b2>
|
|
{
|
|
temp |= iocurrent;
|
|
800274a: 69ba ldr r2, [r7, #24]
|
|
800274c: 693b ldr r3, [r7, #16]
|
|
800274e: 4313 orrs r3, r2
|
|
8002750: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->EMR = temp;
|
|
8002752: 4a1c ldr r2, [pc, #112] @ (80027c4 <HAL_GPIO_Init+0x324>)
|
|
8002754: 69bb ldr r3, [r7, #24]
|
|
8002756: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR;
|
|
8002758: 4b1a ldr r3, [pc, #104] @ (80027c4 <HAL_GPIO_Init+0x324>)
|
|
800275a: 681b ldr r3, [r3, #0]
|
|
800275c: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
800275e: 693b ldr r3, [r7, #16]
|
|
8002760: 43db mvns r3, r3
|
|
8002762: 69ba ldr r2, [r7, #24]
|
|
8002764: 4013 ands r3, r2
|
|
8002766: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
|
|
8002768: 683b ldr r3, [r7, #0]
|
|
800276a: 685b ldr r3, [r3, #4]
|
|
800276c: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8002770: 2b00 cmp r3, #0
|
|
8002772: d003 beq.n 800277c <HAL_GPIO_Init+0x2dc>
|
|
{
|
|
temp |= iocurrent;
|
|
8002774: 69ba ldr r2, [r7, #24]
|
|
8002776: 693b ldr r3, [r7, #16]
|
|
8002778: 4313 orrs r3, r2
|
|
800277a: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->IMR = temp;
|
|
800277c: 4a11 ldr r2, [pc, #68] @ (80027c4 <HAL_GPIO_Init+0x324>)
|
|
800277e: 69bb ldr r3, [r7, #24]
|
|
8002780: 6013 str r3, [r2, #0]
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
8002782: 69fb ldr r3, [r7, #28]
|
|
8002784: 3301 adds r3, #1
|
|
8002786: 61fb str r3, [r7, #28]
|
|
8002788: 69fb ldr r3, [r7, #28]
|
|
800278a: 2b0f cmp r3, #15
|
|
800278c: f67f ae96 bls.w 80024bc <HAL_GPIO_Init+0x1c>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8002790: bf00 nop
|
|
8002792: bf00 nop
|
|
8002794: 3724 adds r7, #36 @ 0x24
|
|
8002796: 46bd mov sp, r7
|
|
8002798: f85d 7b04 ldr.w r7, [sp], #4
|
|
800279c: 4770 bx lr
|
|
800279e: bf00 nop
|
|
80027a0: 40023800 .word 0x40023800
|
|
80027a4: 40013800 .word 0x40013800
|
|
80027a8: 40020000 .word 0x40020000
|
|
80027ac: 40020400 .word 0x40020400
|
|
80027b0: 40020800 .word 0x40020800
|
|
80027b4: 40020c00 .word 0x40020c00
|
|
80027b8: 40021000 .word 0x40021000
|
|
80027bc: 40021400 .word 0x40021400
|
|
80027c0: 40021800 .word 0x40021800
|
|
80027c4: 40013c00 .word 0x40013c00
|
|
|
|
080027c8 <HAL_GPIO_ReadPin>:
|
|
* @param GPIO_Pin specifies the port bit to read.
|
|
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
|
* @retval The input port pin value.
|
|
*/
|
|
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
80027c8: b480 push {r7}
|
|
80027ca: b085 sub sp, #20
|
|
80027cc: af00 add r7, sp, #0
|
|
80027ce: 6078 str r0, [r7, #4]
|
|
80027d0: 460b mov r3, r1
|
|
80027d2: 807b strh r3, [r7, #2]
|
|
GPIO_PinState bitstatus;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
|
80027d4: 687b ldr r3, [r7, #4]
|
|
80027d6: 691a ldr r2, [r3, #16]
|
|
80027d8: 887b ldrh r3, [r7, #2]
|
|
80027da: 4013 ands r3, r2
|
|
80027dc: 2b00 cmp r3, #0
|
|
80027de: d002 beq.n 80027e6 <HAL_GPIO_ReadPin+0x1e>
|
|
{
|
|
bitstatus = GPIO_PIN_SET;
|
|
80027e0: 2301 movs r3, #1
|
|
80027e2: 73fb strb r3, [r7, #15]
|
|
80027e4: e001 b.n 80027ea <HAL_GPIO_ReadPin+0x22>
|
|
}
|
|
else
|
|
{
|
|
bitstatus = GPIO_PIN_RESET;
|
|
80027e6: 2300 movs r3, #0
|
|
80027e8: 73fb strb r3, [r7, #15]
|
|
}
|
|
return bitstatus;
|
|
80027ea: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80027ec: 4618 mov r0, r3
|
|
80027ee: 3714 adds r7, #20
|
|
80027f0: 46bd mov sp, r7
|
|
80027f2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80027f6: 4770 bx lr
|
|
|
|
080027f8 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
80027f8: b480 push {r7}
|
|
80027fa: b083 sub sp, #12
|
|
80027fc: af00 add r7, sp, #0
|
|
80027fe: 6078 str r0, [r7, #4]
|
|
8002800: 460b mov r3, r1
|
|
8002802: 807b strh r3, [r7, #2]
|
|
8002804: 4613 mov r3, r2
|
|
8002806: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8002808: 787b ldrb r3, [r7, #1]
|
|
800280a: 2b00 cmp r3, #0
|
|
800280c: d003 beq.n 8002816 <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = GPIO_Pin;
|
|
800280e: 887a ldrh r2, [r7, #2]
|
|
8002810: 687b ldr r3, [r7, #4]
|
|
8002812: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
}
|
|
}
|
|
8002814: e003 b.n 800281e <HAL_GPIO_WritePin+0x26>
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
8002816: 887b ldrh r3, [r7, #2]
|
|
8002818: 041a lsls r2, r3, #16
|
|
800281a: 687b ldr r3, [r7, #4]
|
|
800281c: 619a str r2, [r3, #24]
|
|
}
|
|
800281e: bf00 nop
|
|
8002820: 370c adds r7, #12
|
|
8002822: 46bd mov sp, r7
|
|
8002824: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002828: 4770 bx lr
|
|
...
|
|
|
|
0800282c <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
800282c: b580 push {r7, lr}
|
|
800282e: b084 sub sp, #16
|
|
8002830: af00 add r7, sp, #0
|
|
8002832: 6078 str r0, [r7, #4]
|
|
uint32_t freqrange;
|
|
uint32_t pclk1;
|
|
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8002834: 687b ldr r3, [r7, #4]
|
|
8002836: 2b00 cmp r3, #0
|
|
8002838: d101 bne.n 800283e <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800283a: 2301 movs r3, #1
|
|
800283c: e12b b.n 8002a96 <HAL_I2C_Init+0x26a>
|
|
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
800283e: 687b ldr r3, [r7, #4]
|
|
8002840: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8002844: b2db uxtb r3, r3
|
|
8002846: 2b00 cmp r3, #0
|
|
8002848: d106 bne.n 8002858 <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
800284a: 687b ldr r3, [r7, #4]
|
|
800284c: 2200 movs r2, #0
|
|
800284e: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_I2C_MspInit(hi2c);
|
|
8002852: 6878 ldr r0, [r7, #4]
|
|
8002854: f7fd ffa0 bl 8000798 <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8002858: 687b ldr r3, [r7, #4]
|
|
800285a: 2224 movs r2, #36 @ 0x24
|
|
800285c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8002860: 687b ldr r3, [r7, #4]
|
|
8002862: 681b ldr r3, [r3, #0]
|
|
8002864: 681a ldr r2, [r3, #0]
|
|
8002866: 687b ldr r3, [r7, #4]
|
|
8002868: 681b ldr r3, [r3, #0]
|
|
800286a: f022 0201 bic.w r2, r2, #1
|
|
800286e: 601a str r2, [r3, #0]
|
|
|
|
/*Reset I2C*/
|
|
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
|
|
8002870: 687b ldr r3, [r7, #4]
|
|
8002872: 681b ldr r3, [r3, #0]
|
|
8002874: 681a ldr r2, [r3, #0]
|
|
8002876: 687b ldr r3, [r7, #4]
|
|
8002878: 681b ldr r3, [r3, #0]
|
|
800287a: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
800287e: 601a str r2, [r3, #0]
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
|
|
8002880: 687b ldr r3, [r7, #4]
|
|
8002882: 681b ldr r3, [r3, #0]
|
|
8002884: 681a ldr r2, [r3, #0]
|
|
8002886: 687b ldr r3, [r7, #4]
|
|
8002888: 681b ldr r3, [r3, #0]
|
|
800288a: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
800288e: 601a str r2, [r3, #0]
|
|
|
|
/* Get PCLK1 frequency */
|
|
pclk1 = HAL_RCC_GetPCLK1Freq();
|
|
8002890: f001 fc88 bl 80041a4 <HAL_RCC_GetPCLK1Freq>
|
|
8002894: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check the minimum allowed PCLK1 frequency */
|
|
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
|
|
8002896: 687b ldr r3, [r7, #4]
|
|
8002898: 685b ldr r3, [r3, #4]
|
|
800289a: 4a81 ldr r2, [pc, #516] @ (8002aa0 <HAL_I2C_Init+0x274>)
|
|
800289c: 4293 cmp r3, r2
|
|
800289e: d807 bhi.n 80028b0 <HAL_I2C_Init+0x84>
|
|
80028a0: 68fb ldr r3, [r7, #12]
|
|
80028a2: 4a80 ldr r2, [pc, #512] @ (8002aa4 <HAL_I2C_Init+0x278>)
|
|
80028a4: 4293 cmp r3, r2
|
|
80028a6: bf94 ite ls
|
|
80028a8: 2301 movls r3, #1
|
|
80028aa: 2300 movhi r3, #0
|
|
80028ac: b2db uxtb r3, r3
|
|
80028ae: e006 b.n 80028be <HAL_I2C_Init+0x92>
|
|
80028b0: 68fb ldr r3, [r7, #12]
|
|
80028b2: 4a7d ldr r2, [pc, #500] @ (8002aa8 <HAL_I2C_Init+0x27c>)
|
|
80028b4: 4293 cmp r3, r2
|
|
80028b6: bf94 ite ls
|
|
80028b8: 2301 movls r3, #1
|
|
80028ba: 2300 movhi r3, #0
|
|
80028bc: b2db uxtb r3, r3
|
|
80028be: 2b00 cmp r3, #0
|
|
80028c0: d001 beq.n 80028c6 <HAL_I2C_Init+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
80028c2: 2301 movs r3, #1
|
|
80028c4: e0e7 b.n 8002a96 <HAL_I2C_Init+0x26a>
|
|
}
|
|
|
|
/* Calculate frequency range */
|
|
freqrange = I2C_FREQRANGE(pclk1);
|
|
80028c6: 68fb ldr r3, [r7, #12]
|
|
80028c8: 4a78 ldr r2, [pc, #480] @ (8002aac <HAL_I2C_Init+0x280>)
|
|
80028ca: fba2 2303 umull r2, r3, r2, r3
|
|
80028ce: 0c9b lsrs r3, r3, #18
|
|
80028d0: 60bb str r3, [r7, #8]
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
|
|
80028d2: 687b ldr r3, [r7, #4]
|
|
80028d4: 681b ldr r3, [r3, #0]
|
|
80028d6: 685b ldr r3, [r3, #4]
|
|
80028d8: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
80028dc: 687b ldr r3, [r7, #4]
|
|
80028de: 681b ldr r3, [r3, #0]
|
|
80028e0: 68ba ldr r2, [r7, #8]
|
|
80028e2: 430a orrs r2, r1
|
|
80028e4: 605a str r2, [r3, #4]
|
|
|
|
/*---------------------------- I2Cx TRISE Configuration --------------------*/
|
|
/* Configure I2Cx: Rise Time */
|
|
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
|
|
80028e6: 687b ldr r3, [r7, #4]
|
|
80028e8: 681b ldr r3, [r3, #0]
|
|
80028ea: 6a1b ldr r3, [r3, #32]
|
|
80028ec: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
80028f0: 687b ldr r3, [r7, #4]
|
|
80028f2: 685b ldr r3, [r3, #4]
|
|
80028f4: 4a6a ldr r2, [pc, #424] @ (8002aa0 <HAL_I2C_Init+0x274>)
|
|
80028f6: 4293 cmp r3, r2
|
|
80028f8: d802 bhi.n 8002900 <HAL_I2C_Init+0xd4>
|
|
80028fa: 68bb ldr r3, [r7, #8]
|
|
80028fc: 3301 adds r3, #1
|
|
80028fe: e009 b.n 8002914 <HAL_I2C_Init+0xe8>
|
|
8002900: 68bb ldr r3, [r7, #8]
|
|
8002902: f44f 7296 mov.w r2, #300 @ 0x12c
|
|
8002906: fb02 f303 mul.w r3, r2, r3
|
|
800290a: 4a69 ldr r2, [pc, #420] @ (8002ab0 <HAL_I2C_Init+0x284>)
|
|
800290c: fba2 2303 umull r2, r3, r2, r3
|
|
8002910: 099b lsrs r3, r3, #6
|
|
8002912: 3301 adds r3, #1
|
|
8002914: 687a ldr r2, [r7, #4]
|
|
8002916: 6812 ldr r2, [r2, #0]
|
|
8002918: 430b orrs r3, r1
|
|
800291a: 6213 str r3, [r2, #32]
|
|
|
|
/*---------------------------- I2Cx CCR Configuration ----------------------*/
|
|
/* Configure I2Cx: Speed */
|
|
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
|
|
800291c: 687b ldr r3, [r7, #4]
|
|
800291e: 681b ldr r3, [r3, #0]
|
|
8002920: 69db ldr r3, [r3, #28]
|
|
8002922: f423 424f bic.w r2, r3, #52992 @ 0xcf00
|
|
8002926: f022 02ff bic.w r2, r2, #255 @ 0xff
|
|
800292a: 687b ldr r3, [r7, #4]
|
|
800292c: 685b ldr r3, [r3, #4]
|
|
800292e: 495c ldr r1, [pc, #368] @ (8002aa0 <HAL_I2C_Init+0x274>)
|
|
8002930: 428b cmp r3, r1
|
|
8002932: d819 bhi.n 8002968 <HAL_I2C_Init+0x13c>
|
|
8002934: 68fb ldr r3, [r7, #12]
|
|
8002936: 1e59 subs r1, r3, #1
|
|
8002938: 687b ldr r3, [r7, #4]
|
|
800293a: 685b ldr r3, [r3, #4]
|
|
800293c: 005b lsls r3, r3, #1
|
|
800293e: fbb1 f3f3 udiv r3, r1, r3
|
|
8002942: 1c59 adds r1, r3, #1
|
|
8002944: f640 73fc movw r3, #4092 @ 0xffc
|
|
8002948: 400b ands r3, r1
|
|
800294a: 2b00 cmp r3, #0
|
|
800294c: d00a beq.n 8002964 <HAL_I2C_Init+0x138>
|
|
800294e: 68fb ldr r3, [r7, #12]
|
|
8002950: 1e59 subs r1, r3, #1
|
|
8002952: 687b ldr r3, [r7, #4]
|
|
8002954: 685b ldr r3, [r3, #4]
|
|
8002956: 005b lsls r3, r3, #1
|
|
8002958: fbb1 f3f3 udiv r3, r1, r3
|
|
800295c: 3301 adds r3, #1
|
|
800295e: f3c3 030b ubfx r3, r3, #0, #12
|
|
8002962: e051 b.n 8002a08 <HAL_I2C_Init+0x1dc>
|
|
8002964: 2304 movs r3, #4
|
|
8002966: e04f b.n 8002a08 <HAL_I2C_Init+0x1dc>
|
|
8002968: 687b ldr r3, [r7, #4]
|
|
800296a: 689b ldr r3, [r3, #8]
|
|
800296c: 2b00 cmp r3, #0
|
|
800296e: d111 bne.n 8002994 <HAL_I2C_Init+0x168>
|
|
8002970: 68fb ldr r3, [r7, #12]
|
|
8002972: 1e58 subs r0, r3, #1
|
|
8002974: 687b ldr r3, [r7, #4]
|
|
8002976: 6859 ldr r1, [r3, #4]
|
|
8002978: 460b mov r3, r1
|
|
800297a: 005b lsls r3, r3, #1
|
|
800297c: 440b add r3, r1
|
|
800297e: fbb0 f3f3 udiv r3, r0, r3
|
|
8002982: 3301 adds r3, #1
|
|
8002984: f3c3 030b ubfx r3, r3, #0, #12
|
|
8002988: 2b00 cmp r3, #0
|
|
800298a: bf0c ite eq
|
|
800298c: 2301 moveq r3, #1
|
|
800298e: 2300 movne r3, #0
|
|
8002990: b2db uxtb r3, r3
|
|
8002992: e012 b.n 80029ba <HAL_I2C_Init+0x18e>
|
|
8002994: 68fb ldr r3, [r7, #12]
|
|
8002996: 1e58 subs r0, r3, #1
|
|
8002998: 687b ldr r3, [r7, #4]
|
|
800299a: 6859 ldr r1, [r3, #4]
|
|
800299c: 460b mov r3, r1
|
|
800299e: 009b lsls r3, r3, #2
|
|
80029a0: 440b add r3, r1
|
|
80029a2: 0099 lsls r1, r3, #2
|
|
80029a4: 440b add r3, r1
|
|
80029a6: fbb0 f3f3 udiv r3, r0, r3
|
|
80029aa: 3301 adds r3, #1
|
|
80029ac: f3c3 030b ubfx r3, r3, #0, #12
|
|
80029b0: 2b00 cmp r3, #0
|
|
80029b2: bf0c ite eq
|
|
80029b4: 2301 moveq r3, #1
|
|
80029b6: 2300 movne r3, #0
|
|
80029b8: b2db uxtb r3, r3
|
|
80029ba: 2b00 cmp r3, #0
|
|
80029bc: d001 beq.n 80029c2 <HAL_I2C_Init+0x196>
|
|
80029be: 2301 movs r3, #1
|
|
80029c0: e022 b.n 8002a08 <HAL_I2C_Init+0x1dc>
|
|
80029c2: 687b ldr r3, [r7, #4]
|
|
80029c4: 689b ldr r3, [r3, #8]
|
|
80029c6: 2b00 cmp r3, #0
|
|
80029c8: d10e bne.n 80029e8 <HAL_I2C_Init+0x1bc>
|
|
80029ca: 68fb ldr r3, [r7, #12]
|
|
80029cc: 1e58 subs r0, r3, #1
|
|
80029ce: 687b ldr r3, [r7, #4]
|
|
80029d0: 6859 ldr r1, [r3, #4]
|
|
80029d2: 460b mov r3, r1
|
|
80029d4: 005b lsls r3, r3, #1
|
|
80029d6: 440b add r3, r1
|
|
80029d8: fbb0 f3f3 udiv r3, r0, r3
|
|
80029dc: 3301 adds r3, #1
|
|
80029de: f3c3 030b ubfx r3, r3, #0, #12
|
|
80029e2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80029e6: e00f b.n 8002a08 <HAL_I2C_Init+0x1dc>
|
|
80029e8: 68fb ldr r3, [r7, #12]
|
|
80029ea: 1e58 subs r0, r3, #1
|
|
80029ec: 687b ldr r3, [r7, #4]
|
|
80029ee: 6859 ldr r1, [r3, #4]
|
|
80029f0: 460b mov r3, r1
|
|
80029f2: 009b lsls r3, r3, #2
|
|
80029f4: 440b add r3, r1
|
|
80029f6: 0099 lsls r1, r3, #2
|
|
80029f8: 440b add r3, r1
|
|
80029fa: fbb0 f3f3 udiv r3, r0, r3
|
|
80029fe: 3301 adds r3, #1
|
|
8002a00: f3c3 030b ubfx r3, r3, #0, #12
|
|
8002a04: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8002a08: 6879 ldr r1, [r7, #4]
|
|
8002a0a: 6809 ldr r1, [r1, #0]
|
|
8002a0c: 4313 orrs r3, r2
|
|
8002a0e: 61cb str r3, [r1, #28]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
|
|
8002a10: 687b ldr r3, [r7, #4]
|
|
8002a12: 681b ldr r3, [r3, #0]
|
|
8002a14: 681b ldr r3, [r3, #0]
|
|
8002a16: f023 01c0 bic.w r1, r3, #192 @ 0xc0
|
|
8002a1a: 687b ldr r3, [r7, #4]
|
|
8002a1c: 69da ldr r2, [r3, #28]
|
|
8002a1e: 687b ldr r3, [r7, #4]
|
|
8002a20: 6a1b ldr r3, [r3, #32]
|
|
8002a22: 431a orrs r2, r3
|
|
8002a24: 687b ldr r3, [r7, #4]
|
|
8002a26: 681b ldr r3, [r3, #0]
|
|
8002a28: 430a orrs r2, r1
|
|
8002a2a: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Configure I2Cx: Own Address1 and addressing mode */
|
|
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
|
|
8002a2c: 687b ldr r3, [r7, #4]
|
|
8002a2e: 681b ldr r3, [r3, #0]
|
|
8002a30: 689b ldr r3, [r3, #8]
|
|
8002a32: f423 4303 bic.w r3, r3, #33536 @ 0x8300
|
|
8002a36: f023 03ff bic.w r3, r3, #255 @ 0xff
|
|
8002a3a: 687a ldr r2, [r7, #4]
|
|
8002a3c: 6911 ldr r1, [r2, #16]
|
|
8002a3e: 687a ldr r2, [r7, #4]
|
|
8002a40: 68d2 ldr r2, [r2, #12]
|
|
8002a42: 4311 orrs r1, r2
|
|
8002a44: 687a ldr r2, [r7, #4]
|
|
8002a46: 6812 ldr r2, [r2, #0]
|
|
8002a48: 430b orrs r3, r1
|
|
8002a4a: 6093 str r3, [r2, #8]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
|
|
8002a4c: 687b ldr r3, [r7, #4]
|
|
8002a4e: 681b ldr r3, [r3, #0]
|
|
8002a50: 68db ldr r3, [r3, #12]
|
|
8002a52: f023 01ff bic.w r1, r3, #255 @ 0xff
|
|
8002a56: 687b ldr r3, [r7, #4]
|
|
8002a58: 695a ldr r2, [r3, #20]
|
|
8002a5a: 687b ldr r3, [r7, #4]
|
|
8002a5c: 699b ldr r3, [r3, #24]
|
|
8002a5e: 431a orrs r2, r3
|
|
8002a60: 687b ldr r3, [r7, #4]
|
|
8002a62: 681b ldr r3, [r3, #0]
|
|
8002a64: 430a orrs r2, r1
|
|
8002a66: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8002a68: 687b ldr r3, [r7, #4]
|
|
8002a6a: 681b ldr r3, [r3, #0]
|
|
8002a6c: 681a ldr r2, [r3, #0]
|
|
8002a6e: 687b ldr r3, [r7, #4]
|
|
8002a70: 681b ldr r3, [r3, #0]
|
|
8002a72: f042 0201 orr.w r2, r2, #1
|
|
8002a76: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8002a78: 687b ldr r3, [r7, #4]
|
|
8002a7a: 2200 movs r2, #0
|
|
8002a7c: 641a str r2, [r3, #64] @ 0x40
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8002a7e: 687b ldr r3, [r7, #4]
|
|
8002a80: 2220 movs r2, #32
|
|
8002a82: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8002a86: 687b ldr r3, [r7, #4]
|
|
8002a88: 2200 movs r2, #0
|
|
8002a8a: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8002a8c: 687b ldr r3, [r7, #4]
|
|
8002a8e: 2200 movs r2, #0
|
|
8002a90: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
|
|
return HAL_OK;
|
|
8002a94: 2300 movs r3, #0
|
|
}
|
|
8002a96: 4618 mov r0, r3
|
|
8002a98: 3710 adds r7, #16
|
|
8002a9a: 46bd mov sp, r7
|
|
8002a9c: bd80 pop {r7, pc}
|
|
8002a9e: bf00 nop
|
|
8002aa0: 000186a0 .word 0x000186a0
|
|
8002aa4: 001e847f .word 0x001e847f
|
|
8002aa8: 003d08ff .word 0x003d08ff
|
|
8002aac: 431bde83 .word 0x431bde83
|
|
8002ab0: 10624dd3 .word 0x10624dd3
|
|
|
|
08002ab4 <HAL_PCD_Init>:
|
|
* parameters in the PCD_InitTypeDef and initialize the associated handle.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8002ab4: b580 push {r7, lr}
|
|
8002ab6: b086 sub sp, #24
|
|
8002ab8: af02 add r7, sp, #8
|
|
8002aba: 6078 str r0, [r7, #4]
|
|
const USB_OTG_GlobalTypeDef *USBx;
|
|
#endif /* defined (USB_OTG_FS) */
|
|
uint8_t i;
|
|
|
|
/* Check the PCD handle allocation */
|
|
if (hpcd == NULL)
|
|
8002abc: 687b ldr r3, [r7, #4]
|
|
8002abe: 2b00 cmp r3, #0
|
|
8002ac0: d101 bne.n 8002ac6 <HAL_PCD_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8002ac2: 2301 movs r3, #1
|
|
8002ac4: e108 b.n 8002cd8 <HAL_PCD_Init+0x224>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
|
|
|
|
#if defined (USB_OTG_FS)
|
|
USBx = hpcd->Instance;
|
|
8002ac6: 687b ldr r3, [r7, #4]
|
|
8002ac8: 681b ldr r3, [r3, #0]
|
|
8002aca: 60bb str r3, [r7, #8]
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
if (hpcd->State == HAL_PCD_STATE_RESET)
|
|
8002acc: 687b ldr r3, [r7, #4]
|
|
8002ace: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495
|
|
8002ad2: b2db uxtb r3, r3
|
|
8002ad4: 2b00 cmp r3, #0
|
|
8002ad6: d106 bne.n 8002ae6 <HAL_PCD_Init+0x32>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hpcd->Lock = HAL_UNLOCKED;
|
|
8002ad8: 687b ldr r3, [r7, #4]
|
|
8002ada: 2200 movs r2, #0
|
|
8002adc: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
/* Init the low level hardware */
|
|
hpcd->MspInitCallback(hpcd);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_PCD_MspInit(hpcd);
|
|
8002ae0: 6878 ldr r0, [r7, #4]
|
|
8002ae2: f007 fbbb bl 800a25c <HAL_PCD_MspInit>
|
|
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
hpcd->State = HAL_PCD_STATE_BUSY;
|
|
8002ae6: 687b ldr r3, [r7, #4]
|
|
8002ae8: 2203 movs r2, #3
|
|
8002aea: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
|
|
#if defined (USB_OTG_FS)
|
|
/* Disable DMA mode for FS instance */
|
|
if (USBx == USB_OTG_FS)
|
|
8002aee: 68bb ldr r3, [r7, #8]
|
|
8002af0: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8002af4: d102 bne.n 8002afc <HAL_PCD_Init+0x48>
|
|
{
|
|
hpcd->Init.dma_enable = 0U;
|
|
8002af6: 687b ldr r3, [r7, #4]
|
|
8002af8: 2200 movs r2, #0
|
|
8002afa: 719a strb r2, [r3, #6]
|
|
}
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
/* Disable the Interrupts */
|
|
__HAL_PCD_DISABLE(hpcd);
|
|
8002afc: 687b ldr r3, [r7, #4]
|
|
8002afe: 681b ldr r3, [r3, #0]
|
|
8002b00: 4618 mov r0, r3
|
|
8002b02: f004 fab0 bl 8007066 <USB_DisableGlobalInt>
|
|
|
|
/*Init the Core (common init.) */
|
|
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8002b06: 687b ldr r3, [r7, #4]
|
|
8002b08: 6818 ldr r0, [r3, #0]
|
|
8002b0a: 687b ldr r3, [r7, #4]
|
|
8002b0c: 7c1a ldrb r2, [r3, #16]
|
|
8002b0e: f88d 2000 strb.w r2, [sp]
|
|
8002b12: 3304 adds r3, #4
|
|
8002b14: cb0e ldmia r3, {r1, r2, r3}
|
|
8002b16: f004 f98f bl 8006e38 <USB_CoreInit>
|
|
8002b1a: 4603 mov r3, r0
|
|
8002b1c: 2b00 cmp r3, #0
|
|
8002b1e: d005 beq.n 8002b2c <HAL_PCD_Init+0x78>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8002b20: 687b ldr r3, [r7, #4]
|
|
8002b22: 2202 movs r2, #2
|
|
8002b24: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8002b28: 2301 movs r3, #1
|
|
8002b2a: e0d5 b.n 8002cd8 <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
/* Force Device Mode */
|
|
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
|
|
8002b2c: 687b ldr r3, [r7, #4]
|
|
8002b2e: 681b ldr r3, [r3, #0]
|
|
8002b30: 2100 movs r1, #0
|
|
8002b32: 4618 mov r0, r3
|
|
8002b34: f004 faa8 bl 8007088 <USB_SetCurrentMode>
|
|
8002b38: 4603 mov r3, r0
|
|
8002b3a: 2b00 cmp r3, #0
|
|
8002b3c: d005 beq.n 8002b4a <HAL_PCD_Init+0x96>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8002b3e: 687b ldr r3, [r7, #4]
|
|
8002b40: 2202 movs r2, #2
|
|
8002b42: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8002b46: 2301 movs r3, #1
|
|
8002b48: e0c6 b.n 8002cd8 <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
/* Init endpoints structures */
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8002b4a: 2300 movs r3, #0
|
|
8002b4c: 73fb strb r3, [r7, #15]
|
|
8002b4e: e04a b.n 8002be6 <HAL_PCD_Init+0x132>
|
|
{
|
|
/* Init ep structure */
|
|
hpcd->IN_ep[i].is_in = 1U;
|
|
8002b50: 7bfa ldrb r2, [r7, #15]
|
|
8002b52: 6879 ldr r1, [r7, #4]
|
|
8002b54: 4613 mov r3, r2
|
|
8002b56: 00db lsls r3, r3, #3
|
|
8002b58: 4413 add r3, r2
|
|
8002b5a: 009b lsls r3, r3, #2
|
|
8002b5c: 440b add r3, r1
|
|
8002b5e: 3315 adds r3, #21
|
|
8002b60: 2201 movs r2, #1
|
|
8002b62: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].num = i;
|
|
8002b64: 7bfa ldrb r2, [r7, #15]
|
|
8002b66: 6879 ldr r1, [r7, #4]
|
|
8002b68: 4613 mov r3, r2
|
|
8002b6a: 00db lsls r3, r3, #3
|
|
8002b6c: 4413 add r3, r2
|
|
8002b6e: 009b lsls r3, r3, #2
|
|
8002b70: 440b add r3, r1
|
|
8002b72: 3314 adds r3, #20
|
|
8002b74: 7bfa ldrb r2, [r7, #15]
|
|
8002b76: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].tx_fifo_num = i;
|
|
8002b78: 7bfa ldrb r2, [r7, #15]
|
|
8002b7a: 7bfb ldrb r3, [r7, #15]
|
|
8002b7c: b298 uxth r0, r3
|
|
8002b7e: 6879 ldr r1, [r7, #4]
|
|
8002b80: 4613 mov r3, r2
|
|
8002b82: 00db lsls r3, r3, #3
|
|
8002b84: 4413 add r3, r2
|
|
8002b86: 009b lsls r3, r3, #2
|
|
8002b88: 440b add r3, r1
|
|
8002b8a: 332e adds r3, #46 @ 0x2e
|
|
8002b8c: 4602 mov r2, r0
|
|
8002b8e: 801a strh r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
|
|
8002b90: 7bfa ldrb r2, [r7, #15]
|
|
8002b92: 6879 ldr r1, [r7, #4]
|
|
8002b94: 4613 mov r3, r2
|
|
8002b96: 00db lsls r3, r3, #3
|
|
8002b98: 4413 add r3, r2
|
|
8002b9a: 009b lsls r3, r3, #2
|
|
8002b9c: 440b add r3, r1
|
|
8002b9e: 3318 adds r3, #24
|
|
8002ba0: 2200 movs r2, #0
|
|
8002ba2: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].maxpacket = 0U;
|
|
8002ba4: 7bfa ldrb r2, [r7, #15]
|
|
8002ba6: 6879 ldr r1, [r7, #4]
|
|
8002ba8: 4613 mov r3, r2
|
|
8002baa: 00db lsls r3, r3, #3
|
|
8002bac: 4413 add r3, r2
|
|
8002bae: 009b lsls r3, r3, #2
|
|
8002bb0: 440b add r3, r1
|
|
8002bb2: 331c adds r3, #28
|
|
8002bb4: 2200 movs r2, #0
|
|
8002bb6: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_buff = 0U;
|
|
8002bb8: 7bfa ldrb r2, [r7, #15]
|
|
8002bba: 6879 ldr r1, [r7, #4]
|
|
8002bbc: 4613 mov r3, r2
|
|
8002bbe: 00db lsls r3, r3, #3
|
|
8002bc0: 4413 add r3, r2
|
|
8002bc2: 009b lsls r3, r3, #2
|
|
8002bc4: 440b add r3, r1
|
|
8002bc6: 3320 adds r3, #32
|
|
8002bc8: 2200 movs r2, #0
|
|
8002bca: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_len = 0U;
|
|
8002bcc: 7bfa ldrb r2, [r7, #15]
|
|
8002bce: 6879 ldr r1, [r7, #4]
|
|
8002bd0: 4613 mov r3, r2
|
|
8002bd2: 00db lsls r3, r3, #3
|
|
8002bd4: 4413 add r3, r2
|
|
8002bd6: 009b lsls r3, r3, #2
|
|
8002bd8: 440b add r3, r1
|
|
8002bda: 3324 adds r3, #36 @ 0x24
|
|
8002bdc: 2200 movs r2, #0
|
|
8002bde: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8002be0: 7bfb ldrb r3, [r7, #15]
|
|
8002be2: 3301 adds r3, #1
|
|
8002be4: 73fb strb r3, [r7, #15]
|
|
8002be6: 687b ldr r3, [r7, #4]
|
|
8002be8: 791b ldrb r3, [r3, #4]
|
|
8002bea: 7bfa ldrb r2, [r7, #15]
|
|
8002bec: 429a cmp r2, r3
|
|
8002bee: d3af bcc.n 8002b50 <HAL_PCD_Init+0x9c>
|
|
}
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8002bf0: 2300 movs r3, #0
|
|
8002bf2: 73fb strb r3, [r7, #15]
|
|
8002bf4: e044 b.n 8002c80 <HAL_PCD_Init+0x1cc>
|
|
{
|
|
hpcd->OUT_ep[i].is_in = 0U;
|
|
8002bf6: 7bfa ldrb r2, [r7, #15]
|
|
8002bf8: 6879 ldr r1, [r7, #4]
|
|
8002bfa: 4613 mov r3, r2
|
|
8002bfc: 00db lsls r3, r3, #3
|
|
8002bfe: 4413 add r3, r2
|
|
8002c00: 009b lsls r3, r3, #2
|
|
8002c02: 440b add r3, r1
|
|
8002c04: f203 2355 addw r3, r3, #597 @ 0x255
|
|
8002c08: 2200 movs r2, #0
|
|
8002c0a: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].num = i;
|
|
8002c0c: 7bfa ldrb r2, [r7, #15]
|
|
8002c0e: 6879 ldr r1, [r7, #4]
|
|
8002c10: 4613 mov r3, r2
|
|
8002c12: 00db lsls r3, r3, #3
|
|
8002c14: 4413 add r3, r2
|
|
8002c16: 009b lsls r3, r3, #2
|
|
8002c18: 440b add r3, r1
|
|
8002c1a: f503 7315 add.w r3, r3, #596 @ 0x254
|
|
8002c1e: 7bfa ldrb r2, [r7, #15]
|
|
8002c20: 701a strb r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
|
|
8002c22: 7bfa ldrb r2, [r7, #15]
|
|
8002c24: 6879 ldr r1, [r7, #4]
|
|
8002c26: 4613 mov r3, r2
|
|
8002c28: 00db lsls r3, r3, #3
|
|
8002c2a: 4413 add r3, r2
|
|
8002c2c: 009b lsls r3, r3, #2
|
|
8002c2e: 440b add r3, r1
|
|
8002c30: f503 7316 add.w r3, r3, #600 @ 0x258
|
|
8002c34: 2200 movs r2, #0
|
|
8002c36: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].maxpacket = 0U;
|
|
8002c38: 7bfa ldrb r2, [r7, #15]
|
|
8002c3a: 6879 ldr r1, [r7, #4]
|
|
8002c3c: 4613 mov r3, r2
|
|
8002c3e: 00db lsls r3, r3, #3
|
|
8002c40: 4413 add r3, r2
|
|
8002c42: 009b lsls r3, r3, #2
|
|
8002c44: 440b add r3, r1
|
|
8002c46: f503 7317 add.w r3, r3, #604 @ 0x25c
|
|
8002c4a: 2200 movs r2, #0
|
|
8002c4c: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_buff = 0U;
|
|
8002c4e: 7bfa ldrb r2, [r7, #15]
|
|
8002c50: 6879 ldr r1, [r7, #4]
|
|
8002c52: 4613 mov r3, r2
|
|
8002c54: 00db lsls r3, r3, #3
|
|
8002c56: 4413 add r3, r2
|
|
8002c58: 009b lsls r3, r3, #2
|
|
8002c5a: 440b add r3, r1
|
|
8002c5c: f503 7318 add.w r3, r3, #608 @ 0x260
|
|
8002c60: 2200 movs r2, #0
|
|
8002c62: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_len = 0U;
|
|
8002c64: 7bfa ldrb r2, [r7, #15]
|
|
8002c66: 6879 ldr r1, [r7, #4]
|
|
8002c68: 4613 mov r3, r2
|
|
8002c6a: 00db lsls r3, r3, #3
|
|
8002c6c: 4413 add r3, r2
|
|
8002c6e: 009b lsls r3, r3, #2
|
|
8002c70: 440b add r3, r1
|
|
8002c72: f503 7319 add.w r3, r3, #612 @ 0x264
|
|
8002c76: 2200 movs r2, #0
|
|
8002c78: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8002c7a: 7bfb ldrb r3, [r7, #15]
|
|
8002c7c: 3301 adds r3, #1
|
|
8002c7e: 73fb strb r3, [r7, #15]
|
|
8002c80: 687b ldr r3, [r7, #4]
|
|
8002c82: 791b ldrb r3, [r3, #4]
|
|
8002c84: 7bfa ldrb r2, [r7, #15]
|
|
8002c86: 429a cmp r2, r3
|
|
8002c88: d3b5 bcc.n 8002bf6 <HAL_PCD_Init+0x142>
|
|
}
|
|
|
|
/* Init Device */
|
|
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
|
|
8002c8a: 687b ldr r3, [r7, #4]
|
|
8002c8c: 6818 ldr r0, [r3, #0]
|
|
8002c8e: 687b ldr r3, [r7, #4]
|
|
8002c90: 7c1a ldrb r2, [r3, #16]
|
|
8002c92: f88d 2000 strb.w r2, [sp]
|
|
8002c96: 3304 adds r3, #4
|
|
8002c98: cb0e ldmia r3, {r1, r2, r3}
|
|
8002c9a: f004 fa41 bl 8007120 <USB_DevInit>
|
|
8002c9e: 4603 mov r3, r0
|
|
8002ca0: 2b00 cmp r3, #0
|
|
8002ca2: d005 beq.n 8002cb0 <HAL_PCD_Init+0x1fc>
|
|
{
|
|
hpcd->State = HAL_PCD_STATE_ERROR;
|
|
8002ca4: 687b ldr r3, [r7, #4]
|
|
8002ca6: 2202 movs r2, #2
|
|
8002ca8: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
return HAL_ERROR;
|
|
8002cac: 2301 movs r3, #1
|
|
8002cae: e013 b.n 8002cd8 <HAL_PCD_Init+0x224>
|
|
}
|
|
|
|
hpcd->USB_Address = 0U;
|
|
8002cb0: 687b ldr r3, [r7, #4]
|
|
8002cb2: 2200 movs r2, #0
|
|
8002cb4: 745a strb r2, [r3, #17]
|
|
hpcd->State = HAL_PCD_STATE_READY;
|
|
8002cb6: 687b ldr r3, [r7, #4]
|
|
8002cb8: 2201 movs r2, #1
|
|
8002cba: f883 2495 strb.w r2, [r3, #1173] @ 0x495
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* Activate LPM */
|
|
if (hpcd->Init.lpm_enable == 1U)
|
|
8002cbe: 687b ldr r3, [r7, #4]
|
|
8002cc0: 7b1b ldrb r3, [r3, #12]
|
|
8002cc2: 2b01 cmp r3, #1
|
|
8002cc4: d102 bne.n 8002ccc <HAL_PCD_Init+0x218>
|
|
{
|
|
(void)HAL_PCDEx_ActivateLPM(hpcd);
|
|
8002cc6: 6878 ldr r0, [r7, #4]
|
|
8002cc8: f001 f956 bl 8003f78 <HAL_PCDEx_ActivateLPM>
|
|
}
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
(void)USB_DevDisconnect(hpcd->Instance);
|
|
8002ccc: 687b ldr r3, [r7, #4]
|
|
8002cce: 681b ldr r3, [r3, #0]
|
|
8002cd0: 4618 mov r0, r3
|
|
8002cd2: f005 fa7e bl 80081d2 <USB_DevDisconnect>
|
|
|
|
return HAL_OK;
|
|
8002cd6: 2300 movs r3, #0
|
|
}
|
|
8002cd8: 4618 mov r0, r3
|
|
8002cda: 3710 adds r7, #16
|
|
8002cdc: 46bd mov sp, r7
|
|
8002cde: bd80 pop {r7, pc}
|
|
|
|
08002ce0 <HAL_PCD_Start>:
|
|
* @brief Start the USB device
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8002ce0: b580 push {r7, lr}
|
|
8002ce2: b084 sub sp, #16
|
|
8002ce4: af00 add r7, sp, #0
|
|
8002ce6: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8002ce8: 687b ldr r3, [r7, #4]
|
|
8002cea: 681b ldr r3, [r3, #0]
|
|
8002cec: 60fb str r3, [r7, #12]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8002cee: 687b ldr r3, [r7, #4]
|
|
8002cf0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8002cf4: 2b01 cmp r3, #1
|
|
8002cf6: d101 bne.n 8002cfc <HAL_PCD_Start+0x1c>
|
|
8002cf8: 2302 movs r3, #2
|
|
8002cfa: e022 b.n 8002d42 <HAL_PCD_Start+0x62>
|
|
8002cfc: 687b ldr r3, [r7, #4]
|
|
8002cfe: 2201 movs r2, #1
|
|
8002d00: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
|
|
8002d04: 68fb ldr r3, [r7, #12]
|
|
8002d06: 68db ldr r3, [r3, #12]
|
|
8002d08: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8002d0c: 2b00 cmp r3, #0
|
|
8002d0e: d009 beq.n 8002d24 <HAL_PCD_Start+0x44>
|
|
(hpcd->Init.battery_charging_enable == 1U))
|
|
8002d10: 687b ldr r3, [r7, #4]
|
|
8002d12: 7b5b ldrb r3, [r3, #13]
|
|
if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
|
|
8002d14: 2b01 cmp r3, #1
|
|
8002d16: d105 bne.n 8002d24 <HAL_PCD_Start+0x44>
|
|
{
|
|
/* Enable USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
8002d18: 68fb ldr r3, [r7, #12]
|
|
8002d1a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8002d1c: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
8002d20: 68fb ldr r3, [r7, #12]
|
|
8002d22: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
|
|
__HAL_PCD_ENABLE(hpcd);
|
|
8002d24: 687b ldr r3, [r7, #4]
|
|
8002d26: 681b ldr r3, [r3, #0]
|
|
8002d28: 4618 mov r0, r3
|
|
8002d2a: f004 f98b bl 8007044 <USB_EnableGlobalInt>
|
|
(void)USB_DevConnect(hpcd->Instance);
|
|
8002d2e: 687b ldr r3, [r7, #4]
|
|
8002d30: 681b ldr r3, [r3, #0]
|
|
8002d32: 4618 mov r0, r3
|
|
8002d34: f005 fa2c bl 8008190 <USB_DevConnect>
|
|
__HAL_UNLOCK(hpcd);
|
|
8002d38: 687b ldr r3, [r7, #4]
|
|
8002d3a: 2200 movs r2, #0
|
|
8002d3c: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8002d40: 2300 movs r3, #0
|
|
}
|
|
8002d42: 4618 mov r0, r3
|
|
8002d44: 3710 adds r7, #16
|
|
8002d46: 46bd mov sp, r7
|
|
8002d48: bd80 pop {r7, pc}
|
|
|
|
08002d4a <HAL_PCD_IRQHandler>:
|
|
* @brief Handles PCD interrupt request.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8002d4a: b590 push {r4, r7, lr}
|
|
8002d4c: b08d sub sp, #52 @ 0x34
|
|
8002d4e: af00 add r7, sp, #0
|
|
8002d50: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8002d52: 687b ldr r3, [r7, #4]
|
|
8002d54: 681b ldr r3, [r3, #0]
|
|
8002d56: 623b str r3, [r7, #32]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8002d58: 6a3b ldr r3, [r7, #32]
|
|
8002d5a: 61fb str r3, [r7, #28]
|
|
uint32_t epnum;
|
|
uint32_t fifoemptymsk;
|
|
uint32_t RegVal;
|
|
|
|
/* ensure that we are in device mode */
|
|
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
|
|
8002d5c: 687b ldr r3, [r7, #4]
|
|
8002d5e: 681b ldr r3, [r3, #0]
|
|
8002d60: 4618 mov r0, r3
|
|
8002d62: f005 faea bl 800833a <USB_GetMode>
|
|
8002d66: 4603 mov r3, r0
|
|
8002d68: 2b00 cmp r3, #0
|
|
8002d6a: f040 84b9 bne.w 80036e0 <HAL_PCD_IRQHandler+0x996>
|
|
{
|
|
/* avoid spurious interrupt */
|
|
if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
|
|
8002d6e: 687b ldr r3, [r7, #4]
|
|
8002d70: 681b ldr r3, [r3, #0]
|
|
8002d72: 4618 mov r0, r3
|
|
8002d74: f005 fa4e bl 8008214 <USB_ReadInterrupts>
|
|
8002d78: 4603 mov r3, r0
|
|
8002d7a: 2b00 cmp r3, #0
|
|
8002d7c: f000 84af beq.w 80036de <HAL_PCD_IRQHandler+0x994>
|
|
{
|
|
return;
|
|
}
|
|
|
|
/* store current frame number */
|
|
hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos;
|
|
8002d80: 69fb ldr r3, [r7, #28]
|
|
8002d82: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002d86: 689b ldr r3, [r3, #8]
|
|
8002d88: 0a1b lsrs r3, r3, #8
|
|
8002d8a: f3c3 020d ubfx r2, r3, #0, #14
|
|
8002d8e: 687b ldr r3, [r7, #4]
|
|
8002d90: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
|
|
8002d94: 687b ldr r3, [r7, #4]
|
|
8002d96: 681b ldr r3, [r3, #0]
|
|
8002d98: 4618 mov r0, r3
|
|
8002d9a: f005 fa3b bl 8008214 <USB_ReadInterrupts>
|
|
8002d9e: 4603 mov r3, r0
|
|
8002da0: f003 0302 and.w r3, r3, #2
|
|
8002da4: 2b02 cmp r3, #2
|
|
8002da6: d107 bne.n 8002db8 <HAL_PCD_IRQHandler+0x6e>
|
|
{
|
|
/* incorrect mode, acknowledge the interrupt */
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
|
|
8002da8: 687b ldr r3, [r7, #4]
|
|
8002daa: 681b ldr r3, [r3, #0]
|
|
8002dac: 695a ldr r2, [r3, #20]
|
|
8002dae: 687b ldr r3, [r7, #4]
|
|
8002db0: 681b ldr r3, [r3, #0]
|
|
8002db2: f002 0202 and.w r2, r2, #2
|
|
8002db6: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle RxQLevel Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
|
|
8002db8: 687b ldr r3, [r7, #4]
|
|
8002dba: 681b ldr r3, [r3, #0]
|
|
8002dbc: 4618 mov r0, r3
|
|
8002dbe: f005 fa29 bl 8008214 <USB_ReadInterrupts>
|
|
8002dc2: 4603 mov r3, r0
|
|
8002dc4: f003 0310 and.w r3, r3, #16
|
|
8002dc8: 2b10 cmp r3, #16
|
|
8002dca: d161 bne.n 8002e90 <HAL_PCD_IRQHandler+0x146>
|
|
{
|
|
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
8002dcc: 687b ldr r3, [r7, #4]
|
|
8002dce: 681b ldr r3, [r3, #0]
|
|
8002dd0: 699a ldr r2, [r3, #24]
|
|
8002dd2: 687b ldr r3, [r7, #4]
|
|
8002dd4: 681b ldr r3, [r3, #0]
|
|
8002dd6: f022 0210 bic.w r2, r2, #16
|
|
8002dda: 619a str r2, [r3, #24]
|
|
|
|
RegVal = USBx->GRXSTSP;
|
|
8002ddc: 6a3b ldr r3, [r7, #32]
|
|
8002dde: 6a1b ldr r3, [r3, #32]
|
|
8002de0: 61bb str r3, [r7, #24]
|
|
|
|
ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM];
|
|
8002de2: 69bb ldr r3, [r7, #24]
|
|
8002de4: f003 020f and.w r2, r3, #15
|
|
8002de8: 4613 mov r3, r2
|
|
8002dea: 00db lsls r3, r3, #3
|
|
8002dec: 4413 add r3, r2
|
|
8002dee: 009b lsls r3, r3, #2
|
|
8002df0: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002df4: 687a ldr r2, [r7, #4]
|
|
8002df6: 4413 add r3, r2
|
|
8002df8: 3304 adds r3, #4
|
|
8002dfa: 617b str r3, [r7, #20]
|
|
|
|
if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
|
|
8002dfc: 69bb ldr r3, [r7, #24]
|
|
8002dfe: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
|
|
8002e02: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
8002e06: d124 bne.n 8002e52 <HAL_PCD_IRQHandler+0x108>
|
|
{
|
|
if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U)
|
|
8002e08: 69ba ldr r2, [r7, #24]
|
|
8002e0a: f647 73f0 movw r3, #32752 @ 0x7ff0
|
|
8002e0e: 4013 ands r3, r2
|
|
8002e10: 2b00 cmp r3, #0
|
|
8002e12: d035 beq.n 8002e80 <HAL_PCD_IRQHandler+0x136>
|
|
{
|
|
(void)USB_ReadPacket(USBx, ep->xfer_buff,
|
|
8002e14: 697b ldr r3, [r7, #20]
|
|
8002e16: 68d9 ldr r1, [r3, #12]
|
|
(uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4));
|
|
8002e18: 69bb ldr r3, [r7, #24]
|
|
8002e1a: 091b lsrs r3, r3, #4
|
|
8002e1c: b29b uxth r3, r3
|
|
(void)USB_ReadPacket(USBx, ep->xfer_buff,
|
|
8002e1e: f3c3 030a ubfx r3, r3, #0, #11
|
|
8002e22: b29b uxth r3, r3
|
|
8002e24: 461a mov r2, r3
|
|
8002e26: 6a38 ldr r0, [r7, #32]
|
|
8002e28: f005 f860 bl 8007eec <USB_ReadPacket>
|
|
|
|
ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8002e2c: 697b ldr r3, [r7, #20]
|
|
8002e2e: 68da ldr r2, [r3, #12]
|
|
8002e30: 69bb ldr r3, [r7, #24]
|
|
8002e32: 091b lsrs r3, r3, #4
|
|
8002e34: f3c3 030a ubfx r3, r3, #0, #11
|
|
8002e38: 441a add r2, r3
|
|
8002e3a: 697b ldr r3, [r7, #20]
|
|
8002e3c: 60da str r2, [r3, #12]
|
|
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8002e3e: 697b ldr r3, [r7, #20]
|
|
8002e40: 695a ldr r2, [r3, #20]
|
|
8002e42: 69bb ldr r3, [r7, #24]
|
|
8002e44: 091b lsrs r3, r3, #4
|
|
8002e46: f3c3 030a ubfx r3, r3, #0, #11
|
|
8002e4a: 441a add r2, r3
|
|
8002e4c: 697b ldr r3, [r7, #20]
|
|
8002e4e: 615a str r2, [r3, #20]
|
|
8002e50: e016 b.n 8002e80 <HAL_PCD_IRQHandler+0x136>
|
|
}
|
|
}
|
|
else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
|
|
8002e52: 69bb ldr r3, [r7, #24]
|
|
8002e54: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000
|
|
8002e58: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000
|
|
8002e5c: d110 bne.n 8002e80 <HAL_PCD_IRQHandler+0x136>
|
|
{
|
|
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
|
|
8002e5e: 687b ldr r3, [r7, #4]
|
|
8002e60: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8002e64: 2208 movs r2, #8
|
|
8002e66: 4619 mov r1, r3
|
|
8002e68: 6a38 ldr r0, [r7, #32]
|
|
8002e6a: f005 f83f bl 8007eec <USB_ReadPacket>
|
|
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8002e6e: 697b ldr r3, [r7, #20]
|
|
8002e70: 695a ldr r2, [r3, #20]
|
|
8002e72: 69bb ldr r3, [r7, #24]
|
|
8002e74: 091b lsrs r3, r3, #4
|
|
8002e76: f3c3 030a ubfx r3, r3, #0, #11
|
|
8002e7a: 441a add r2, r3
|
|
8002e7c: 697b ldr r3, [r7, #20]
|
|
8002e7e: 615a str r2, [r3, #20]
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
|
|
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
8002e80: 687b ldr r3, [r7, #4]
|
|
8002e82: 681b ldr r3, [r3, #0]
|
|
8002e84: 699a ldr r2, [r3, #24]
|
|
8002e86: 687b ldr r3, [r7, #4]
|
|
8002e88: 681b ldr r3, [r3, #0]
|
|
8002e8a: f042 0210 orr.w r2, r2, #16
|
|
8002e8e: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
|
|
8002e90: 687b ldr r3, [r7, #4]
|
|
8002e92: 681b ldr r3, [r3, #0]
|
|
8002e94: 4618 mov r0, r3
|
|
8002e96: f005 f9bd bl 8008214 <USB_ReadInterrupts>
|
|
8002e9a: 4603 mov r3, r0
|
|
8002e9c: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8002ea0: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
|
|
8002ea4: f040 80a7 bne.w 8002ff6 <HAL_PCD_IRQHandler+0x2ac>
|
|
{
|
|
epnum = 0U;
|
|
8002ea8: 2300 movs r3, #0
|
|
8002eaa: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Read in the device interrupt bits */
|
|
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
|
|
8002eac: 687b ldr r3, [r7, #4]
|
|
8002eae: 681b ldr r3, [r3, #0]
|
|
8002eb0: 4618 mov r0, r3
|
|
8002eb2: f005 f9c2 bl 800823a <USB_ReadDevAllOutEpInterrupt>
|
|
8002eb6: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
while (ep_intr != 0U)
|
|
8002eb8: e099 b.n 8002fee <HAL_PCD_IRQHandler+0x2a4>
|
|
{
|
|
if ((ep_intr & 0x1U) != 0U)
|
|
8002eba: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8002ebc: f003 0301 and.w r3, r3, #1
|
|
8002ec0: 2b00 cmp r3, #0
|
|
8002ec2: f000 808e beq.w 8002fe2 <HAL_PCD_IRQHandler+0x298>
|
|
{
|
|
epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
|
|
8002ec6: 687b ldr r3, [r7, #4]
|
|
8002ec8: 681b ldr r3, [r3, #0]
|
|
8002eca: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002ecc: b2d2 uxtb r2, r2
|
|
8002ece: 4611 mov r1, r2
|
|
8002ed0: 4618 mov r0, r3
|
|
8002ed2: f005 f9e6 bl 80082a2 <USB_ReadDevOutEPInterrupt>
|
|
8002ed6: 6138 str r0, [r7, #16]
|
|
|
|
if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
|
|
8002ed8: 693b ldr r3, [r7, #16]
|
|
8002eda: f003 0301 and.w r3, r3, #1
|
|
8002ede: 2b00 cmp r3, #0
|
|
8002ee0: d00c beq.n 8002efc <HAL_PCD_IRQHandler+0x1b2>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
|
|
8002ee2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002ee4: 015a lsls r2, r3, #5
|
|
8002ee6: 69fb ldr r3, [r7, #28]
|
|
8002ee8: 4413 add r3, r2
|
|
8002eea: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002eee: 461a mov r2, r3
|
|
8002ef0: 2301 movs r3, #1
|
|
8002ef2: 6093 str r3, [r2, #8]
|
|
(void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
|
|
8002ef4: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8002ef6: 6878 ldr r0, [r7, #4]
|
|
8002ef8: f000 feb8 bl 8003c6c <PCD_EP_OutXfrComplete_int>
|
|
}
|
|
|
|
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
|
|
8002efc: 693b ldr r3, [r7, #16]
|
|
8002efe: f003 0308 and.w r3, r3, #8
|
|
8002f02: 2b00 cmp r3, #0
|
|
8002f04: d00c beq.n 8002f20 <HAL_PCD_IRQHandler+0x1d6>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
|
|
8002f06: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002f08: 015a lsls r2, r3, #5
|
|
8002f0a: 69fb ldr r3, [r7, #28]
|
|
8002f0c: 4413 add r3, r2
|
|
8002f0e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002f12: 461a mov r2, r3
|
|
8002f14: 2308 movs r3, #8
|
|
8002f16: 6093 str r3, [r2, #8]
|
|
/* Class B setup phase done for previous decoded setup */
|
|
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
|
|
8002f18: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8002f1a: 6878 ldr r0, [r7, #4]
|
|
8002f1c: f000 ff8e bl 8003e3c <PCD_EP_OutSetupPacket_int>
|
|
}
|
|
|
|
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
|
|
8002f20: 693b ldr r3, [r7, #16]
|
|
8002f22: f003 0310 and.w r3, r3, #16
|
|
8002f26: 2b00 cmp r3, #0
|
|
8002f28: d008 beq.n 8002f3c <HAL_PCD_IRQHandler+0x1f2>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
|
|
8002f2a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002f2c: 015a lsls r2, r3, #5
|
|
8002f2e: 69fb ldr r3, [r7, #28]
|
|
8002f30: 4413 add r3, r2
|
|
8002f32: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002f36: 461a mov r2, r3
|
|
8002f38: 2310 movs r3, #16
|
|
8002f3a: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear OUT Endpoint disable interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
|
|
8002f3c: 693b ldr r3, [r7, #16]
|
|
8002f3e: f003 0302 and.w r3, r3, #2
|
|
8002f42: 2b00 cmp r3, #0
|
|
8002f44: d030 beq.n 8002fa8 <HAL_PCD_IRQHandler+0x25e>
|
|
{
|
|
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF)
|
|
8002f46: 6a3b ldr r3, [r7, #32]
|
|
8002f48: 695b ldr r3, [r3, #20]
|
|
8002f4a: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002f4e: 2b80 cmp r3, #128 @ 0x80
|
|
8002f50: d109 bne.n 8002f66 <HAL_PCD_IRQHandler+0x21c>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
|
|
8002f52: 69fb ldr r3, [r7, #28]
|
|
8002f54: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8002f58: 685b ldr r3, [r3, #4]
|
|
8002f5a: 69fa ldr r2, [r7, #28]
|
|
8002f5c: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8002f60: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8002f64: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
ep = &hpcd->OUT_ep[epnum];
|
|
8002f66: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8002f68: 4613 mov r3, r2
|
|
8002f6a: 00db lsls r3, r3, #3
|
|
8002f6c: 4413 add r3, r2
|
|
8002f6e: 009b lsls r3, r3, #2
|
|
8002f70: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8002f74: 687a ldr r2, [r7, #4]
|
|
8002f76: 4413 add r3, r2
|
|
8002f78: 3304 adds r3, #4
|
|
8002f7a: 617b str r3, [r7, #20]
|
|
|
|
if (ep->is_iso_incomplete == 1U)
|
|
8002f7c: 697b ldr r3, [r7, #20]
|
|
8002f7e: 78db ldrb r3, [r3, #3]
|
|
8002f80: 2b01 cmp r3, #1
|
|
8002f82: d108 bne.n 8002f96 <HAL_PCD_IRQHandler+0x24c>
|
|
{
|
|
ep->is_iso_incomplete = 0U;
|
|
8002f84: 697b ldr r3, [r7, #20]
|
|
8002f86: 2200 movs r2, #0
|
|
8002f88: 70da strb r2, [r3, #3]
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
8002f8a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002f8c: b2db uxtb r3, r3
|
|
8002f8e: 4619 mov r1, r3
|
|
8002f90: 6878 ldr r0, [r7, #4]
|
|
8002f92: f007 fa7f bl 800a494 <HAL_PCD_ISOOUTIncompleteCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
|
|
8002f96: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002f98: 015a lsls r2, r3, #5
|
|
8002f9a: 69fb ldr r3, [r7, #28]
|
|
8002f9c: 4413 add r3, r2
|
|
8002f9e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002fa2: 461a mov r2, r3
|
|
8002fa4: 2302 movs r3, #2
|
|
8002fa6: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear Status Phase Received interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
|
|
8002fa8: 693b ldr r3, [r7, #16]
|
|
8002faa: f003 0320 and.w r3, r3, #32
|
|
8002fae: 2b00 cmp r3, #0
|
|
8002fb0: d008 beq.n 8002fc4 <HAL_PCD_IRQHandler+0x27a>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
8002fb2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002fb4: 015a lsls r2, r3, #5
|
|
8002fb6: 69fb ldr r3, [r7, #28]
|
|
8002fb8: 4413 add r3, r2
|
|
8002fba: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002fbe: 461a mov r2, r3
|
|
8002fc0: 2320 movs r3, #32
|
|
8002fc2: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Clear OUT NAK interrupt */
|
|
if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
|
|
8002fc4: 693b ldr r3, [r7, #16]
|
|
8002fc6: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
8002fca: 2b00 cmp r3, #0
|
|
8002fcc: d009 beq.n 8002fe2 <HAL_PCD_IRQHandler+0x298>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
|
|
8002fce: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002fd0: 015a lsls r2, r3, #5
|
|
8002fd2: 69fb ldr r3, [r7, #28]
|
|
8002fd4: 4413 add r3, r2
|
|
8002fd6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8002fda: 461a mov r2, r3
|
|
8002fdc: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
8002fe0: 6093 str r3, [r2, #8]
|
|
}
|
|
}
|
|
epnum++;
|
|
8002fe2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002fe4: 3301 adds r3, #1
|
|
8002fe6: 627b str r3, [r7, #36] @ 0x24
|
|
ep_intr >>= 1U;
|
|
8002fe8: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8002fea: 085b lsrs r3, r3, #1
|
|
8002fec: 62bb str r3, [r7, #40] @ 0x28
|
|
while (ep_intr != 0U)
|
|
8002fee: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8002ff0: 2b00 cmp r3, #0
|
|
8002ff2: f47f af62 bne.w 8002eba <HAL_PCD_IRQHandler+0x170>
|
|
}
|
|
}
|
|
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
|
|
8002ff6: 687b ldr r3, [r7, #4]
|
|
8002ff8: 681b ldr r3, [r3, #0]
|
|
8002ffa: 4618 mov r0, r3
|
|
8002ffc: f005 f90a bl 8008214 <USB_ReadInterrupts>
|
|
8003000: 4603 mov r3, r0
|
|
8003002: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8003006: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
800300a: f040 80db bne.w 80031c4 <HAL_PCD_IRQHandler+0x47a>
|
|
{
|
|
/* Read in the device interrupt bits */
|
|
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
|
|
800300e: 687b ldr r3, [r7, #4]
|
|
8003010: 681b ldr r3, [r3, #0]
|
|
8003012: 4618 mov r0, r3
|
|
8003014: f005 f92b bl 800826e <USB_ReadDevAllInEpInterrupt>
|
|
8003018: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
epnum = 0U;
|
|
800301a: 2300 movs r3, #0
|
|
800301c: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
while (ep_intr != 0U)
|
|
800301e: e0cd b.n 80031bc <HAL_PCD_IRQHandler+0x472>
|
|
{
|
|
if ((ep_intr & 0x1U) != 0U) /* In ITR */
|
|
8003020: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003022: f003 0301 and.w r3, r3, #1
|
|
8003026: 2b00 cmp r3, #0
|
|
8003028: f000 80c2 beq.w 80031b0 <HAL_PCD_IRQHandler+0x466>
|
|
{
|
|
epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
|
|
800302c: 687b ldr r3, [r7, #4]
|
|
800302e: 681b ldr r3, [r3, #0]
|
|
8003030: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8003032: b2d2 uxtb r2, r2
|
|
8003034: 4611 mov r1, r2
|
|
8003036: 4618 mov r0, r3
|
|
8003038: f005 f951 bl 80082de <USB_ReadDevInEPInterrupt>
|
|
800303c: 6138 str r0, [r7, #16]
|
|
|
|
if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
|
|
800303e: 693b ldr r3, [r7, #16]
|
|
8003040: f003 0301 and.w r3, r3, #1
|
|
8003044: 2b00 cmp r3, #0
|
|
8003046: d057 beq.n 80030f8 <HAL_PCD_IRQHandler+0x3ae>
|
|
{
|
|
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
|
|
8003048: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800304a: f003 030f and.w r3, r3, #15
|
|
800304e: 2201 movs r2, #1
|
|
8003050: fa02 f303 lsl.w r3, r2, r3
|
|
8003054: 60fb str r3, [r7, #12]
|
|
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
|
|
8003056: 69fb ldr r3, [r7, #28]
|
|
8003058: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800305c: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
800305e: 68fb ldr r3, [r7, #12]
|
|
8003060: 43db mvns r3, r3
|
|
8003062: 69f9 ldr r1, [r7, #28]
|
|
8003064: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8003068: 4013 ands r3, r2
|
|
800306a: 634b str r3, [r1, #52] @ 0x34
|
|
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
|
|
800306c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800306e: 015a lsls r2, r3, #5
|
|
8003070: 69fb ldr r3, [r7, #28]
|
|
8003072: 4413 add r3, r2
|
|
8003074: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8003078: 461a mov r2, r3
|
|
800307a: 2301 movs r3, #1
|
|
800307c: 6093 str r3, [r2, #8]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
800307e: 687b ldr r3, [r7, #4]
|
|
8003080: 799b ldrb r3, [r3, #6]
|
|
8003082: 2b01 cmp r3, #1
|
|
8003084: d132 bne.n 80030ec <HAL_PCD_IRQHandler+0x3a2>
|
|
{
|
|
hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
|
|
8003086: 6879 ldr r1, [r7, #4]
|
|
8003088: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800308a: 4613 mov r3, r2
|
|
800308c: 00db lsls r3, r3, #3
|
|
800308e: 4413 add r3, r2
|
|
8003090: 009b lsls r3, r3, #2
|
|
8003092: 440b add r3, r1
|
|
8003094: 3320 adds r3, #32
|
|
8003096: 6819 ldr r1, [r3, #0]
|
|
8003098: 6878 ldr r0, [r7, #4]
|
|
800309a: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800309c: 4613 mov r3, r2
|
|
800309e: 00db lsls r3, r3, #3
|
|
80030a0: 4413 add r3, r2
|
|
80030a2: 009b lsls r3, r3, #2
|
|
80030a4: 4403 add r3, r0
|
|
80030a6: 331c adds r3, #28
|
|
80030a8: 681b ldr r3, [r3, #0]
|
|
80030aa: 4419 add r1, r3
|
|
80030ac: 6878 ldr r0, [r7, #4]
|
|
80030ae: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80030b0: 4613 mov r3, r2
|
|
80030b2: 00db lsls r3, r3, #3
|
|
80030b4: 4413 add r3, r2
|
|
80030b6: 009b lsls r3, r3, #2
|
|
80030b8: 4403 add r3, r0
|
|
80030ba: 3320 adds r3, #32
|
|
80030bc: 6019 str r1, [r3, #0]
|
|
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
|
|
80030be: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80030c0: 2b00 cmp r3, #0
|
|
80030c2: d113 bne.n 80030ec <HAL_PCD_IRQHandler+0x3a2>
|
|
80030c4: 6879 ldr r1, [r7, #4]
|
|
80030c6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80030c8: 4613 mov r3, r2
|
|
80030ca: 00db lsls r3, r3, #3
|
|
80030cc: 4413 add r3, r2
|
|
80030ce: 009b lsls r3, r3, #2
|
|
80030d0: 440b add r3, r1
|
|
80030d2: 3324 adds r3, #36 @ 0x24
|
|
80030d4: 681b ldr r3, [r3, #0]
|
|
80030d6: 2b00 cmp r3, #0
|
|
80030d8: d108 bne.n 80030ec <HAL_PCD_IRQHandler+0x3a2>
|
|
{
|
|
/* prepare to rx more setup packets */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
80030da: 687b ldr r3, [r7, #4]
|
|
80030dc: 6818 ldr r0, [r3, #0]
|
|
80030de: 687b ldr r3, [r7, #4]
|
|
80030e0: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
80030e4: 461a mov r2, r3
|
|
80030e6: 2101 movs r1, #1
|
|
80030e8: f005 f958 bl 800839c <USB_EP0_OutStart>
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
|
|
80030ec: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80030ee: b2db uxtb r3, r3
|
|
80030f0: 4619 mov r1, r3
|
|
80030f2: 6878 ldr r0, [r7, #4]
|
|
80030f4: f007 f949 bl 800a38a <HAL_PCD_DataInStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
|
|
80030f8: 693b ldr r3, [r7, #16]
|
|
80030fa: f003 0308 and.w r3, r3, #8
|
|
80030fe: 2b00 cmp r3, #0
|
|
8003100: d008 beq.n 8003114 <HAL_PCD_IRQHandler+0x3ca>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
|
|
8003102: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003104: 015a lsls r2, r3, #5
|
|
8003106: 69fb ldr r3, [r7, #28]
|
|
8003108: 4413 add r3, r2
|
|
800310a: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800310e: 461a mov r2, r3
|
|
8003110: 2308 movs r3, #8
|
|
8003112: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
|
|
8003114: 693b ldr r3, [r7, #16]
|
|
8003116: f003 0310 and.w r3, r3, #16
|
|
800311a: 2b00 cmp r3, #0
|
|
800311c: d008 beq.n 8003130 <HAL_PCD_IRQHandler+0x3e6>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
|
|
800311e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003120: 015a lsls r2, r3, #5
|
|
8003122: 69fb ldr r3, [r7, #28]
|
|
8003124: 4413 add r3, r2
|
|
8003126: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800312a: 461a mov r2, r3
|
|
800312c: 2310 movs r3, #16
|
|
800312e: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
|
|
8003130: 693b ldr r3, [r7, #16]
|
|
8003132: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8003136: 2b00 cmp r3, #0
|
|
8003138: d008 beq.n 800314c <HAL_PCD_IRQHandler+0x402>
|
|
{
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
|
|
800313a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800313c: 015a lsls r2, r3, #5
|
|
800313e: 69fb ldr r3, [r7, #28]
|
|
8003140: 4413 add r3, r2
|
|
8003142: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8003146: 461a mov r2, r3
|
|
8003148: 2340 movs r3, #64 @ 0x40
|
|
800314a: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
|
|
800314c: 693b ldr r3, [r7, #16]
|
|
800314e: f003 0302 and.w r3, r3, #2
|
|
8003152: 2b00 cmp r3, #0
|
|
8003154: d023 beq.n 800319e <HAL_PCD_IRQHandler+0x454>
|
|
{
|
|
(void)USB_FlushTxFifo(USBx, epnum);
|
|
8003156: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8003158: 6a38 ldr r0, [r7, #32]
|
|
800315a: f004 f93f bl 80073dc <USB_FlushTxFifo>
|
|
|
|
ep = &hpcd->IN_ep[epnum];
|
|
800315e: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8003160: 4613 mov r3, r2
|
|
8003162: 00db lsls r3, r3, #3
|
|
8003164: 4413 add r3, r2
|
|
8003166: 009b lsls r3, r3, #2
|
|
8003168: 3310 adds r3, #16
|
|
800316a: 687a ldr r2, [r7, #4]
|
|
800316c: 4413 add r3, r2
|
|
800316e: 3304 adds r3, #4
|
|
8003170: 617b str r3, [r7, #20]
|
|
|
|
if (ep->is_iso_incomplete == 1U)
|
|
8003172: 697b ldr r3, [r7, #20]
|
|
8003174: 78db ldrb r3, [r3, #3]
|
|
8003176: 2b01 cmp r3, #1
|
|
8003178: d108 bne.n 800318c <HAL_PCD_IRQHandler+0x442>
|
|
{
|
|
ep->is_iso_incomplete = 0U;
|
|
800317a: 697b ldr r3, [r7, #20]
|
|
800317c: 2200 movs r2, #0
|
|
800317e: 70da strb r2, [r3, #3]
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
|
|
8003180: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003182: b2db uxtb r3, r3
|
|
8003184: 4619 mov r1, r3
|
|
8003186: 6878 ldr r0, [r7, #4]
|
|
8003188: f007 f996 bl 800a4b8 <HAL_PCD_ISOINIncompleteCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
|
|
800318c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800318e: 015a lsls r2, r3, #5
|
|
8003190: 69fb ldr r3, [r7, #28]
|
|
8003192: 4413 add r3, r2
|
|
8003194: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8003198: 461a mov r2, r3
|
|
800319a: 2302 movs r3, #2
|
|
800319c: 6093 str r3, [r2, #8]
|
|
}
|
|
if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
|
|
800319e: 693b ldr r3, [r7, #16]
|
|
80031a0: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80031a4: 2b00 cmp r3, #0
|
|
80031a6: d003 beq.n 80031b0 <HAL_PCD_IRQHandler+0x466>
|
|
{
|
|
(void)PCD_WriteEmptyTxFifo(hpcd, epnum);
|
|
80031a8: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
80031aa: 6878 ldr r0, [r7, #4]
|
|
80031ac: f000 fcd2 bl 8003b54 <PCD_WriteEmptyTxFifo>
|
|
}
|
|
}
|
|
epnum++;
|
|
80031b0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80031b2: 3301 adds r3, #1
|
|
80031b4: 627b str r3, [r7, #36] @ 0x24
|
|
ep_intr >>= 1U;
|
|
80031b6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80031b8: 085b lsrs r3, r3, #1
|
|
80031ba: 62bb str r3, [r7, #40] @ 0x28
|
|
while (ep_intr != 0U)
|
|
80031bc: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80031be: 2b00 cmp r3, #0
|
|
80031c0: f47f af2e bne.w 8003020 <HAL_PCD_IRQHandler+0x2d6>
|
|
}
|
|
}
|
|
|
|
/* Handle Resume Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
|
|
80031c4: 687b ldr r3, [r7, #4]
|
|
80031c6: 681b ldr r3, [r3, #0]
|
|
80031c8: 4618 mov r0, r3
|
|
80031ca: f005 f823 bl 8008214 <USB_ReadInterrupts>
|
|
80031ce: 4603 mov r3, r0
|
|
80031d0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80031d4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80031d8: d122 bne.n 8003220 <HAL_PCD_IRQHandler+0x4d6>
|
|
{
|
|
/* Clear the Remote Wake-up Signaling */
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
|
|
80031da: 69fb ldr r3, [r7, #28]
|
|
80031dc: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80031e0: 685b ldr r3, [r3, #4]
|
|
80031e2: 69fa ldr r2, [r7, #28]
|
|
80031e4: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80031e8: f023 0301 bic.w r3, r3, #1
|
|
80031ec: 6053 str r3, [r2, #4]
|
|
|
|
if (hpcd->LPM_State == LPM_L1)
|
|
80031ee: 687b ldr r3, [r7, #4]
|
|
80031f0: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
|
|
80031f4: 2b01 cmp r3, #1
|
|
80031f6: d108 bne.n 800320a <HAL_PCD_IRQHandler+0x4c0>
|
|
{
|
|
hpcd->LPM_State = LPM_L0;
|
|
80031f8: 687b ldr r3, [r7, #4]
|
|
80031fa: 2200 movs r2, #0
|
|
80031fc: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
|
|
#else
|
|
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
|
|
8003200: 2100 movs r1, #0
|
|
8003202: 6878 ldr r0, [r7, #4]
|
|
8003204: f007 fafe bl 800a804 <HAL_PCDEx_LPM_Callback>
|
|
8003208: e002 b.n 8003210 <HAL_PCD_IRQHandler+0x4c6>
|
|
else
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResumeCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResumeCallback(hpcd);
|
|
800320a: 6878 ldr r0, [r7, #4]
|
|
800320c: f007 f934 bl 800a478 <HAL_PCD_ResumeCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
|
|
8003210: 687b ldr r3, [r7, #4]
|
|
8003212: 681b ldr r3, [r3, #0]
|
|
8003214: 695a ldr r2, [r3, #20]
|
|
8003216: 687b ldr r3, [r7, #4]
|
|
8003218: 681b ldr r3, [r3, #0]
|
|
800321a: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000
|
|
800321e: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Suspend Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
|
|
8003220: 687b ldr r3, [r7, #4]
|
|
8003222: 681b ldr r3, [r3, #0]
|
|
8003224: 4618 mov r0, r3
|
|
8003226: f004 fff5 bl 8008214 <USB_ReadInterrupts>
|
|
800322a: 4603 mov r3, r0
|
|
800322c: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8003230: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8003234: d112 bne.n 800325c <HAL_PCD_IRQHandler+0x512>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
|
|
8003236: 69fb ldr r3, [r7, #28]
|
|
8003238: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800323c: 689b ldr r3, [r3, #8]
|
|
800323e: f003 0301 and.w r3, r3, #1
|
|
8003242: 2b01 cmp r3, #1
|
|
8003244: d102 bne.n 800324c <HAL_PCD_IRQHandler+0x502>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SuspendCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
8003246: 6878 ldr r0, [r7, #4]
|
|
8003248: f007 f8f0 bl 800a42c <HAL_PCD_SuspendCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
|
|
800324c: 687b ldr r3, [r7, #4]
|
|
800324e: 681b ldr r3, [r3, #0]
|
|
8003250: 695a ldr r2, [r3, #20]
|
|
8003252: 687b ldr r3, [r7, #4]
|
|
8003254: 681b ldr r3, [r3, #0]
|
|
8003256: f402 6200 and.w r2, r2, #2048 @ 0x800
|
|
800325a: 615a str r2, [r3, #20]
|
|
}
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* Handle LPM Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
|
|
800325c: 687b ldr r3, [r7, #4]
|
|
800325e: 681b ldr r3, [r3, #0]
|
|
8003260: 4618 mov r0, r3
|
|
8003262: f004 ffd7 bl 8008214 <USB_ReadInterrupts>
|
|
8003266: 4603 mov r3, r0
|
|
8003268: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
800326c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8003270: d121 bne.n 80032b6 <HAL_PCD_IRQHandler+0x56c>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
|
|
8003272: 687b ldr r3, [r7, #4]
|
|
8003274: 681b ldr r3, [r3, #0]
|
|
8003276: 695a ldr r2, [r3, #20]
|
|
8003278: 687b ldr r3, [r7, #4]
|
|
800327a: 681b ldr r3, [r3, #0]
|
|
800327c: f002 6200 and.w r2, r2, #134217728 @ 0x8000000
|
|
8003280: 615a str r2, [r3, #20]
|
|
|
|
if (hpcd->LPM_State == LPM_L0)
|
|
8003282: 687b ldr r3, [r7, #4]
|
|
8003284: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc
|
|
8003288: 2b00 cmp r3, #0
|
|
800328a: d111 bne.n 80032b0 <HAL_PCD_IRQHandler+0x566>
|
|
{
|
|
hpcd->LPM_State = LPM_L1;
|
|
800328c: 687b ldr r3, [r7, #4]
|
|
800328e: 2201 movs r2, #1
|
|
8003290: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
|
|
8003294: 687b ldr r3, [r7, #4]
|
|
8003296: 681b ldr r3, [r3, #0]
|
|
8003298: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800329a: 089b lsrs r3, r3, #2
|
|
800329c: f003 020f and.w r2, r3, #15
|
|
80032a0: 687b ldr r3, [r7, #4]
|
|
80032a2: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
|
|
#else
|
|
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
|
|
80032a6: 2101 movs r1, #1
|
|
80032a8: 6878 ldr r0, [r7, #4]
|
|
80032aa: f007 faab bl 800a804 <HAL_PCDEx_LPM_Callback>
|
|
80032ae: e002 b.n 80032b6 <HAL_PCD_IRQHandler+0x56c>
|
|
else
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SuspendCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
80032b0: 6878 ldr r0, [r7, #4]
|
|
80032b2: f007 f8bb bl 800a42c <HAL_PCD_SuspendCallback>
|
|
}
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
/* Handle Reset Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
|
|
80032b6: 687b ldr r3, [r7, #4]
|
|
80032b8: 681b ldr r3, [r3, #0]
|
|
80032ba: 4618 mov r0, r3
|
|
80032bc: f004 ffaa bl 8008214 <USB_ReadInterrupts>
|
|
80032c0: 4603 mov r3, r0
|
|
80032c2: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
80032c6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
80032ca: f040 80b7 bne.w 800343c <HAL_PCD_IRQHandler+0x6f2>
|
|
{
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
|
|
80032ce: 69fb ldr r3, [r7, #28]
|
|
80032d0: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80032d4: 685b ldr r3, [r3, #4]
|
|
80032d6: 69fa ldr r2, [r7, #28]
|
|
80032d8: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80032dc: f023 0301 bic.w r3, r3, #1
|
|
80032e0: 6053 str r3, [r2, #4]
|
|
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
|
|
80032e2: 687b ldr r3, [r7, #4]
|
|
80032e4: 681b ldr r3, [r3, #0]
|
|
80032e6: 2110 movs r1, #16
|
|
80032e8: 4618 mov r0, r3
|
|
80032ea: f004 f877 bl 80073dc <USB_FlushTxFifo>
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
80032ee: 2300 movs r3, #0
|
|
80032f0: 62fb str r3, [r7, #44] @ 0x2c
|
|
80032f2: e046 b.n 8003382 <HAL_PCD_IRQHandler+0x638>
|
|
{
|
|
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
|
80032f4: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80032f6: 015a lsls r2, r3, #5
|
|
80032f8: 69fb ldr r3, [r7, #28]
|
|
80032fa: 4413 add r3, r2
|
|
80032fc: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8003300: 461a mov r2, r3
|
|
8003302: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
8003306: 6093 str r3, [r2, #8]
|
|
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
|
8003308: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800330a: 015a lsls r2, r3, #5
|
|
800330c: 69fb ldr r3, [r7, #28]
|
|
800330e: 4413 add r3, r2
|
|
8003310: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8003314: 681b ldr r3, [r3, #0]
|
|
8003316: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8003318: 0151 lsls r1, r2, #5
|
|
800331a: 69fa ldr r2, [r7, #28]
|
|
800331c: 440a add r2, r1
|
|
800331e: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8003322: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
8003326: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
|
8003328: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800332a: 015a lsls r2, r3, #5
|
|
800332c: 69fb ldr r3, [r7, #28]
|
|
800332e: 4413 add r3, r2
|
|
8003330: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003334: 461a mov r2, r3
|
|
8003336: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
800333a: 6093 str r3, [r2, #8]
|
|
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
|
800333c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800333e: 015a lsls r2, r3, #5
|
|
8003340: 69fb ldr r3, [r7, #28]
|
|
8003342: 4413 add r3, r2
|
|
8003344: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003348: 681b ldr r3, [r3, #0]
|
|
800334a: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800334c: 0151 lsls r1, r2, #5
|
|
800334e: 69fa ldr r2, [r7, #28]
|
|
8003350: 440a add r2, r1
|
|
8003352: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8003356: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
800335a: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
|
800335c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800335e: 015a lsls r2, r3, #5
|
|
8003360: 69fb ldr r3, [r7, #28]
|
|
8003362: 4413 add r3, r2
|
|
8003364: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003368: 681b ldr r3, [r3, #0]
|
|
800336a: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800336c: 0151 lsls r1, r2, #5
|
|
800336e: 69fa ldr r2, [r7, #28]
|
|
8003370: 440a add r2, r1
|
|
8003372: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8003376: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
800337a: 6013 str r3, [r2, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
800337c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800337e: 3301 adds r3, #1
|
|
8003380: 62fb str r3, [r7, #44] @ 0x2c
|
|
8003382: 687b ldr r3, [r7, #4]
|
|
8003384: 791b ldrb r3, [r3, #4]
|
|
8003386: 461a mov r2, r3
|
|
8003388: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800338a: 4293 cmp r3, r2
|
|
800338c: d3b2 bcc.n 80032f4 <HAL_PCD_IRQHandler+0x5aa>
|
|
}
|
|
USBx_DEVICE->DAINTMSK |= 0x10001U;
|
|
800338e: 69fb ldr r3, [r7, #28]
|
|
8003390: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8003394: 69db ldr r3, [r3, #28]
|
|
8003396: 69fa ldr r2, [r7, #28]
|
|
8003398: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
800339c: f043 1301 orr.w r3, r3, #65537 @ 0x10001
|
|
80033a0: 61d3 str r3, [r2, #28]
|
|
|
|
if (hpcd->Init.use_dedicated_ep1 != 0U)
|
|
80033a2: 687b ldr r3, [r7, #4]
|
|
80033a4: 7bdb ldrb r3, [r3, #15]
|
|
80033a6: 2b00 cmp r3, #0
|
|
80033a8: d016 beq.n 80033d8 <HAL_PCD_IRQHandler+0x68e>
|
|
{
|
|
USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
|
|
80033aa: 69fb ldr r3, [r7, #28]
|
|
80033ac: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80033b0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80033b4: 69fa ldr r2, [r7, #28]
|
|
80033b6: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80033ba: f043 030b orr.w r3, r3, #11
|
|
80033be: f8c2 3084 str.w r3, [r2, #132] @ 0x84
|
|
USB_OTG_DOEPMSK_XFRCM |
|
|
USB_OTG_DOEPMSK_EPDM;
|
|
|
|
USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
|
|
80033c2: 69fb ldr r3, [r7, #28]
|
|
80033c4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80033c8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80033ca: 69fa ldr r2, [r7, #28]
|
|
80033cc: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80033d0: f043 030b orr.w r3, r3, #11
|
|
80033d4: 6453 str r3, [r2, #68] @ 0x44
|
|
80033d6: e015 b.n 8003404 <HAL_PCD_IRQHandler+0x6ba>
|
|
USB_OTG_DIEPMSK_XFRCM |
|
|
USB_OTG_DIEPMSK_EPDM;
|
|
}
|
|
else
|
|
{
|
|
USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
|
|
80033d8: 69fb ldr r3, [r7, #28]
|
|
80033da: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80033de: 695b ldr r3, [r3, #20]
|
|
80033e0: 69fa ldr r2, [r7, #28]
|
|
80033e2: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80033e6: f443 5300 orr.w r3, r3, #8192 @ 0x2000
|
|
80033ea: f043 032b orr.w r3, r3, #43 @ 0x2b
|
|
80033ee: 6153 str r3, [r2, #20]
|
|
USB_OTG_DOEPMSK_XFRCM |
|
|
USB_OTG_DOEPMSK_EPDM |
|
|
USB_OTG_DOEPMSK_OTEPSPRM |
|
|
USB_OTG_DOEPMSK_NAKM;
|
|
|
|
USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
|
|
80033f0: 69fb ldr r3, [r7, #28]
|
|
80033f2: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80033f6: 691b ldr r3, [r3, #16]
|
|
80033f8: 69fa ldr r2, [r7, #28]
|
|
80033fa: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80033fe: f043 030b orr.w r3, r3, #11
|
|
8003402: 6113 str r3, [r2, #16]
|
|
USB_OTG_DIEPMSK_XFRCM |
|
|
USB_OTG_DIEPMSK_EPDM;
|
|
}
|
|
|
|
/* Set Default Address to 0 */
|
|
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
|
|
8003404: 69fb ldr r3, [r7, #28]
|
|
8003406: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800340a: 681b ldr r3, [r3, #0]
|
|
800340c: 69fa ldr r2, [r7, #28]
|
|
800340e: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8003412: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
|
|
8003416: 6013 str r3, [r2, #0]
|
|
|
|
/* setup EP0 to receive SETUP packets */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
|
|
8003418: 687b ldr r3, [r7, #4]
|
|
800341a: 6818 ldr r0, [r3, #0]
|
|
800341c: 687b ldr r3, [r7, #4]
|
|
800341e: 7999 ldrb r1, [r3, #6]
|
|
(uint8_t *)hpcd->Setup);
|
|
8003420: 687b ldr r3, [r7, #4]
|
|
8003422: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
|
|
8003426: 461a mov r2, r3
|
|
8003428: f004 ffb8 bl 800839c <USB_EP0_OutStart>
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
|
|
800342c: 687b ldr r3, [r7, #4]
|
|
800342e: 681b ldr r3, [r3, #0]
|
|
8003430: 695a ldr r2, [r3, #20]
|
|
8003432: 687b ldr r3, [r7, #4]
|
|
8003434: 681b ldr r3, [r3, #0]
|
|
8003436: f402 5280 and.w r2, r2, #4096 @ 0x1000
|
|
800343a: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Enumeration done Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
|
|
800343c: 687b ldr r3, [r7, #4]
|
|
800343e: 681b ldr r3, [r3, #0]
|
|
8003440: 4618 mov r0, r3
|
|
8003442: f004 fee7 bl 8008214 <USB_ReadInterrupts>
|
|
8003446: 4603 mov r3, r0
|
|
8003448: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
800344c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
8003450: d123 bne.n 800349a <HAL_PCD_IRQHandler+0x750>
|
|
{
|
|
(void)USB_ActivateSetup(hpcd->Instance);
|
|
8003452: 687b ldr r3, [r7, #4]
|
|
8003454: 681b ldr r3, [r3, #0]
|
|
8003456: 4618 mov r0, r3
|
|
8003458: f004 ff7d bl 8008356 <USB_ActivateSetup>
|
|
hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
|
|
800345c: 687b ldr r3, [r7, #4]
|
|
800345e: 681b ldr r3, [r3, #0]
|
|
8003460: 4618 mov r0, r3
|
|
8003462: f004 f834 bl 80074ce <USB_GetDevSpeed>
|
|
8003466: 4603 mov r3, r0
|
|
8003468: 461a mov r2, r3
|
|
800346a: 687b ldr r3, [r7, #4]
|
|
800346c: 71da strb r2, [r3, #7]
|
|
|
|
/* Set USB Turnaround time */
|
|
(void)USB_SetTurnaroundTime(hpcd->Instance,
|
|
800346e: 687b ldr r3, [r7, #4]
|
|
8003470: 681c ldr r4, [r3, #0]
|
|
8003472: f000 fe8b bl 800418c <HAL_RCC_GetHCLKFreq>
|
|
8003476: 4601 mov r1, r0
|
|
HAL_RCC_GetHCLKFreq(),
|
|
(uint8_t)hpcd->Init.speed);
|
|
8003478: 687b ldr r3, [r7, #4]
|
|
800347a: 79db ldrb r3, [r3, #7]
|
|
(void)USB_SetTurnaroundTime(hpcd->Instance,
|
|
800347c: 461a mov r2, r3
|
|
800347e: 4620 mov r0, r4
|
|
8003480: f003 fd3e bl 8006f00 <USB_SetTurnaroundTime>
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResetCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResetCallback(hpcd);
|
|
8003484: 6878 ldr r0, [r7, #4]
|
|
8003486: f006 ffa8 bl 800a3da <HAL_PCD_ResetCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
|
|
800348a: 687b ldr r3, [r7, #4]
|
|
800348c: 681b ldr r3, [r3, #0]
|
|
800348e: 695a ldr r2, [r3, #20]
|
|
8003490: 687b ldr r3, [r7, #4]
|
|
8003492: 681b ldr r3, [r3, #0]
|
|
8003494: f402 5200 and.w r2, r2, #8192 @ 0x2000
|
|
8003498: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle SOF Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
|
|
800349a: 687b ldr r3, [r7, #4]
|
|
800349c: 681b ldr r3, [r3, #0]
|
|
800349e: 4618 mov r0, r3
|
|
80034a0: f004 feb8 bl 8008214 <USB_ReadInterrupts>
|
|
80034a4: 4603 mov r3, r0
|
|
80034a6: f003 0308 and.w r3, r3, #8
|
|
80034aa: 2b08 cmp r3, #8
|
|
80034ac: d10a bne.n 80034c4 <HAL_PCD_IRQHandler+0x77a>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SOFCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SOFCallback(hpcd);
|
|
80034ae: 6878 ldr r0, [r7, #4]
|
|
80034b0: f006 ff85 bl 800a3be <HAL_PCD_SOFCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
|
|
80034b4: 687b ldr r3, [r7, #4]
|
|
80034b6: 681b ldr r3, [r3, #0]
|
|
80034b8: 695a ldr r2, [r3, #20]
|
|
80034ba: 687b ldr r3, [r7, #4]
|
|
80034bc: 681b ldr r3, [r3, #0]
|
|
80034be: f002 0208 and.w r2, r2, #8
|
|
80034c2: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Global OUT NAK effective Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF))
|
|
80034c4: 687b ldr r3, [r7, #4]
|
|
80034c6: 681b ldr r3, [r3, #0]
|
|
80034c8: 4618 mov r0, r3
|
|
80034ca: f004 fea3 bl 8008214 <USB_ReadInterrupts>
|
|
80034ce: 4603 mov r3, r0
|
|
80034d0: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80034d4: 2b80 cmp r3, #128 @ 0x80
|
|
80034d6: d123 bne.n 8003520 <HAL_PCD_IRQHandler+0x7d6>
|
|
{
|
|
USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM;
|
|
80034d8: 6a3b ldr r3, [r7, #32]
|
|
80034da: 699b ldr r3, [r3, #24]
|
|
80034dc: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
80034e0: 6a3b ldr r3, [r7, #32]
|
|
80034e2: 619a str r2, [r3, #24]
|
|
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
80034e4: 2301 movs r3, #1
|
|
80034e6: 627b str r3, [r7, #36] @ 0x24
|
|
80034e8: e014 b.n 8003514 <HAL_PCD_IRQHandler+0x7ca>
|
|
{
|
|
if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U)
|
|
80034ea: 6879 ldr r1, [r7, #4]
|
|
80034ec: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80034ee: 4613 mov r3, r2
|
|
80034f0: 00db lsls r3, r3, #3
|
|
80034f2: 4413 add r3, r2
|
|
80034f4: 009b lsls r3, r3, #2
|
|
80034f6: 440b add r3, r1
|
|
80034f8: f203 2357 addw r3, r3, #599 @ 0x257
|
|
80034fc: 781b ldrb r3, [r3, #0]
|
|
80034fe: 2b01 cmp r3, #1
|
|
8003500: d105 bne.n 800350e <HAL_PCD_IRQHandler+0x7c4>
|
|
{
|
|
/* Abort current transaction and disable the EP */
|
|
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum);
|
|
8003502: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003504: b2db uxtb r3, r3
|
|
8003506: 4619 mov r1, r3
|
|
8003508: 6878 ldr r0, [r7, #4]
|
|
800350a: f000 faf2 bl 8003af2 <HAL_PCD_EP_Abort>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
800350e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003510: 3301 adds r3, #1
|
|
8003512: 627b str r3, [r7, #36] @ 0x24
|
|
8003514: 687b ldr r3, [r7, #4]
|
|
8003516: 791b ldrb r3, [r3, #4]
|
|
8003518: 461a mov r2, r3
|
|
800351a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800351c: 4293 cmp r3, r2
|
|
800351e: d3e4 bcc.n 80034ea <HAL_PCD_IRQHandler+0x7a0>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Handle Incomplete ISO IN Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
|
|
8003520: 687b ldr r3, [r7, #4]
|
|
8003522: 681b ldr r3, [r3, #0]
|
|
8003524: 4618 mov r0, r3
|
|
8003526: f004 fe75 bl 8008214 <USB_ReadInterrupts>
|
|
800352a: 4603 mov r3, r0
|
|
800352c: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8003530: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8003534: d13c bne.n 80035b0 <HAL_PCD_IRQHandler+0x866>
|
|
{
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
8003536: 2301 movs r3, #1
|
|
8003538: 627b str r3, [r7, #36] @ 0x24
|
|
800353a: e02b b.n 8003594 <HAL_PCD_IRQHandler+0x84a>
|
|
{
|
|
RegVal = USBx_INEP(epnum)->DIEPCTL;
|
|
800353c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800353e: 015a lsls r2, r3, #5
|
|
8003540: 69fb ldr r3, [r7, #28]
|
|
8003542: 4413 add r3, r2
|
|
8003544: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8003548: 681b ldr r3, [r3, #0]
|
|
800354a: 61bb str r3, [r7, #24]
|
|
|
|
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
800354c: 6879 ldr r1, [r7, #4]
|
|
800354e: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8003550: 4613 mov r3, r2
|
|
8003552: 00db lsls r3, r3, #3
|
|
8003554: 4413 add r3, r2
|
|
8003556: 009b lsls r3, r3, #2
|
|
8003558: 440b add r3, r1
|
|
800355a: 3318 adds r3, #24
|
|
800355c: 781b ldrb r3, [r3, #0]
|
|
800355e: 2b01 cmp r3, #1
|
|
8003560: d115 bne.n 800358e <HAL_PCD_IRQHandler+0x844>
|
|
((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA))
|
|
8003562: 69bb ldr r3, [r7, #24]
|
|
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
8003564: 2b00 cmp r3, #0
|
|
8003566: da12 bge.n 800358e <HAL_PCD_IRQHandler+0x844>
|
|
{
|
|
hpcd->IN_ep[epnum].is_iso_incomplete = 1U;
|
|
8003568: 6879 ldr r1, [r7, #4]
|
|
800356a: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800356c: 4613 mov r3, r2
|
|
800356e: 00db lsls r3, r3, #3
|
|
8003570: 4413 add r3, r2
|
|
8003572: 009b lsls r3, r3, #2
|
|
8003574: 440b add r3, r1
|
|
8003576: 3317 adds r3, #23
|
|
8003578: 2201 movs r2, #1
|
|
800357a: 701a strb r2, [r3, #0]
|
|
|
|
/* Abort current transaction and disable the EP */
|
|
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U));
|
|
800357c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800357e: b2db uxtb r3, r3
|
|
8003580: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8003584: b2db uxtb r3, r3
|
|
8003586: 4619 mov r1, r3
|
|
8003588: 6878 ldr r0, [r7, #4]
|
|
800358a: f000 fab2 bl 8003af2 <HAL_PCD_EP_Abort>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
800358e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003590: 3301 adds r3, #1
|
|
8003592: 627b str r3, [r7, #36] @ 0x24
|
|
8003594: 687b ldr r3, [r7, #4]
|
|
8003596: 791b ldrb r3, [r3, #4]
|
|
8003598: 461a mov r2, r3
|
|
800359a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800359c: 4293 cmp r3, r2
|
|
800359e: d3cd bcc.n 800353c <HAL_PCD_IRQHandler+0x7f2>
|
|
}
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
|
|
80035a0: 687b ldr r3, [r7, #4]
|
|
80035a2: 681b ldr r3, [r3, #0]
|
|
80035a4: 695a ldr r2, [r3, #20]
|
|
80035a6: 687b ldr r3, [r7, #4]
|
|
80035a8: 681b ldr r3, [r3, #0]
|
|
80035aa: f402 1280 and.w r2, r2, #1048576 @ 0x100000
|
|
80035ae: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Incomplete ISO OUT Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
|
|
80035b0: 687b ldr r3, [r7, #4]
|
|
80035b2: 681b ldr r3, [r3, #0]
|
|
80035b4: 4618 mov r0, r3
|
|
80035b6: f004 fe2d bl 8008214 <USB_ReadInterrupts>
|
|
80035ba: 4603 mov r3, r0
|
|
80035bc: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
80035c0: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
|
|
80035c4: d156 bne.n 8003674 <HAL_PCD_IRQHandler+0x92a>
|
|
{
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
80035c6: 2301 movs r3, #1
|
|
80035c8: 627b str r3, [r7, #36] @ 0x24
|
|
80035ca: e045 b.n 8003658 <HAL_PCD_IRQHandler+0x90e>
|
|
{
|
|
RegVal = USBx_OUTEP(epnum)->DOEPCTL;
|
|
80035cc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80035ce: 015a lsls r2, r3, #5
|
|
80035d0: 69fb ldr r3, [r7, #28]
|
|
80035d2: 4413 add r3, r2
|
|
80035d4: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80035d8: 681b ldr r3, [r3, #0]
|
|
80035da: 61bb str r3, [r7, #24]
|
|
|
|
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
80035dc: 6879 ldr r1, [r7, #4]
|
|
80035de: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80035e0: 4613 mov r3, r2
|
|
80035e2: 00db lsls r3, r3, #3
|
|
80035e4: 4413 add r3, r2
|
|
80035e6: 009b lsls r3, r3, #2
|
|
80035e8: 440b add r3, r1
|
|
80035ea: f503 7316 add.w r3, r3, #600 @ 0x258
|
|
80035ee: 781b ldrb r3, [r3, #0]
|
|
80035f0: 2b01 cmp r3, #1
|
|
80035f2: d12e bne.n 8003652 <HAL_PCD_IRQHandler+0x908>
|
|
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
|
|
80035f4: 69bb ldr r3, [r7, #24]
|
|
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
|
|
80035f6: 2b00 cmp r3, #0
|
|
80035f8: da2b bge.n 8003652 <HAL_PCD_IRQHandler+0x908>
|
|
(((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U)))
|
|
80035fa: 69bb ldr r3, [r7, #24]
|
|
80035fc: 0c1a lsrs r2, r3, #16
|
|
80035fe: 687b ldr r3, [r7, #4]
|
|
8003600: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4
|
|
8003604: 4053 eors r3, r2
|
|
8003606: f003 0301 and.w r3, r3, #1
|
|
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
|
|
800360a: 2b00 cmp r3, #0
|
|
800360c: d121 bne.n 8003652 <HAL_PCD_IRQHandler+0x908>
|
|
{
|
|
hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
|
|
800360e: 6879 ldr r1, [r7, #4]
|
|
8003610: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8003612: 4613 mov r3, r2
|
|
8003614: 00db lsls r3, r3, #3
|
|
8003616: 4413 add r3, r2
|
|
8003618: 009b lsls r3, r3, #2
|
|
800361a: 440b add r3, r1
|
|
800361c: f203 2357 addw r3, r3, #599 @ 0x257
|
|
8003620: 2201 movs r2, #1
|
|
8003622: 701a strb r2, [r3, #0]
|
|
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM;
|
|
8003624: 6a3b ldr r3, [r7, #32]
|
|
8003626: 699b ldr r3, [r3, #24]
|
|
8003628: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
800362c: 6a3b ldr r3, [r7, #32]
|
|
800362e: 619a str r2, [r3, #24]
|
|
|
|
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U)
|
|
8003630: 6a3b ldr r3, [r7, #32]
|
|
8003632: 695b ldr r3, [r3, #20]
|
|
8003634: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8003638: 2b00 cmp r3, #0
|
|
800363a: d10a bne.n 8003652 <HAL_PCD_IRQHandler+0x908>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
|
|
800363c: 69fb ldr r3, [r7, #28]
|
|
800363e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8003642: 685b ldr r3, [r3, #4]
|
|
8003644: 69fa ldr r2, [r7, #28]
|
|
8003646: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
800364a: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
800364e: 6053 str r3, [r2, #4]
|
|
break;
|
|
8003650: e008 b.n 8003664 <HAL_PCD_IRQHandler+0x91a>
|
|
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
|
|
8003652: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003654: 3301 adds r3, #1
|
|
8003656: 627b str r3, [r7, #36] @ 0x24
|
|
8003658: 687b ldr r3, [r7, #4]
|
|
800365a: 791b ldrb r3, [r3, #4]
|
|
800365c: 461a mov r2, r3
|
|
800365e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003660: 4293 cmp r3, r2
|
|
8003662: d3b3 bcc.n 80035cc <HAL_PCD_IRQHandler+0x882>
|
|
}
|
|
}
|
|
}
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
|
|
8003664: 687b ldr r3, [r7, #4]
|
|
8003666: 681b ldr r3, [r3, #0]
|
|
8003668: 695a ldr r2, [r3, #20]
|
|
800366a: 687b ldr r3, [r7, #4]
|
|
800366c: 681b ldr r3, [r3, #0]
|
|
800366e: f402 1200 and.w r2, r2, #2097152 @ 0x200000
|
|
8003672: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Connection event Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
|
|
8003674: 687b ldr r3, [r7, #4]
|
|
8003676: 681b ldr r3, [r3, #0]
|
|
8003678: 4618 mov r0, r3
|
|
800367a: f004 fdcb bl 8008214 <USB_ReadInterrupts>
|
|
800367e: 4603 mov r3, r0
|
|
8003680: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
|
|
8003684: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8003688: d10a bne.n 80036a0 <HAL_PCD_IRQHandler+0x956>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ConnectCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ConnectCallback(hpcd);
|
|
800368a: 6878 ldr r0, [r7, #4]
|
|
800368c: f006 ff26 bl 800a4dc <HAL_PCD_ConnectCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
|
|
8003690: 687b ldr r3, [r7, #4]
|
|
8003692: 681b ldr r3, [r3, #0]
|
|
8003694: 695a ldr r2, [r3, #20]
|
|
8003696: 687b ldr r3, [r7, #4]
|
|
8003698: 681b ldr r3, [r3, #0]
|
|
800369a: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000
|
|
800369e: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Disconnection event Interrupt */
|
|
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
|
|
80036a0: 687b ldr r3, [r7, #4]
|
|
80036a2: 681b ldr r3, [r3, #0]
|
|
80036a4: 4618 mov r0, r3
|
|
80036a6: f004 fdb5 bl 8008214 <USB_ReadInterrupts>
|
|
80036aa: 4603 mov r3, r0
|
|
80036ac: f003 0304 and.w r3, r3, #4
|
|
80036b0: 2b04 cmp r3, #4
|
|
80036b2: d115 bne.n 80036e0 <HAL_PCD_IRQHandler+0x996>
|
|
{
|
|
RegVal = hpcd->Instance->GOTGINT;
|
|
80036b4: 687b ldr r3, [r7, #4]
|
|
80036b6: 681b ldr r3, [r3, #0]
|
|
80036b8: 685b ldr r3, [r3, #4]
|
|
80036ba: 61bb str r3, [r7, #24]
|
|
|
|
if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
|
|
80036bc: 69bb ldr r3, [r7, #24]
|
|
80036be: f003 0304 and.w r3, r3, #4
|
|
80036c2: 2b00 cmp r3, #0
|
|
80036c4: d002 beq.n 80036cc <HAL_PCD_IRQHandler+0x982>
|
|
{
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DisconnectCallback(hpcd);
|
|
#else
|
|
HAL_PCD_DisconnectCallback(hpcd);
|
|
80036c6: 6878 ldr r0, [r7, #4]
|
|
80036c8: f006 ff16 bl 800a4f8 <HAL_PCD_DisconnectCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
hpcd->Instance->GOTGINT |= RegVal;
|
|
80036cc: 687b ldr r3, [r7, #4]
|
|
80036ce: 681b ldr r3, [r3, #0]
|
|
80036d0: 6859 ldr r1, [r3, #4]
|
|
80036d2: 687b ldr r3, [r7, #4]
|
|
80036d4: 681b ldr r3, [r3, #0]
|
|
80036d6: 69ba ldr r2, [r7, #24]
|
|
80036d8: 430a orrs r2, r1
|
|
80036da: 605a str r2, [r3, #4]
|
|
80036dc: e000 b.n 80036e0 <HAL_PCD_IRQHandler+0x996>
|
|
return;
|
|
80036de: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
80036e0: 3734 adds r7, #52 @ 0x34
|
|
80036e2: 46bd mov sp, r7
|
|
80036e4: bd90 pop {r4, r7, pc}
|
|
|
|
080036e6 <HAL_PCD_SetAddress>:
|
|
* @param hpcd PCD handle
|
|
* @param address new device address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
|
|
{
|
|
80036e6: b580 push {r7, lr}
|
|
80036e8: b082 sub sp, #8
|
|
80036ea: af00 add r7, sp, #0
|
|
80036ec: 6078 str r0, [r7, #4]
|
|
80036ee: 460b mov r3, r1
|
|
80036f0: 70fb strb r3, [r7, #3]
|
|
__HAL_LOCK(hpcd);
|
|
80036f2: 687b ldr r3, [r7, #4]
|
|
80036f4: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
80036f8: 2b01 cmp r3, #1
|
|
80036fa: d101 bne.n 8003700 <HAL_PCD_SetAddress+0x1a>
|
|
80036fc: 2302 movs r3, #2
|
|
80036fe: e012 b.n 8003726 <HAL_PCD_SetAddress+0x40>
|
|
8003700: 687b ldr r3, [r7, #4]
|
|
8003702: 2201 movs r2, #1
|
|
8003704: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
hpcd->USB_Address = address;
|
|
8003708: 687b ldr r3, [r7, #4]
|
|
800370a: 78fa ldrb r2, [r7, #3]
|
|
800370c: 745a strb r2, [r3, #17]
|
|
(void)USB_SetDevAddress(hpcd->Instance, address);
|
|
800370e: 687b ldr r3, [r7, #4]
|
|
8003710: 681b ldr r3, [r3, #0]
|
|
8003712: 78fa ldrb r2, [r7, #3]
|
|
8003714: 4611 mov r1, r2
|
|
8003716: 4618 mov r0, r3
|
|
8003718: f004 fd14 bl 8008144 <USB_SetDevAddress>
|
|
__HAL_UNLOCK(hpcd);
|
|
800371c: 687b ldr r3, [r7, #4]
|
|
800371e: 2200 movs r2, #0
|
|
8003720: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8003724: 2300 movs r3, #0
|
|
}
|
|
8003726: 4618 mov r0, r3
|
|
8003728: 3708 adds r7, #8
|
|
800372a: 46bd mov sp, r7
|
|
800372c: bd80 pop {r7, pc}
|
|
|
|
0800372e <HAL_PCD_EP_Open>:
|
|
* @param ep_type endpoint type
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
|
uint16_t ep_mps, uint8_t ep_type)
|
|
{
|
|
800372e: b580 push {r7, lr}
|
|
8003730: b084 sub sp, #16
|
|
8003732: af00 add r7, sp, #0
|
|
8003734: 6078 str r0, [r7, #4]
|
|
8003736: 4608 mov r0, r1
|
|
8003738: 4611 mov r1, r2
|
|
800373a: 461a mov r2, r3
|
|
800373c: 4603 mov r3, r0
|
|
800373e: 70fb strb r3, [r7, #3]
|
|
8003740: 460b mov r3, r1
|
|
8003742: 803b strh r3, [r7, #0]
|
|
8003744: 4613 mov r3, r2
|
|
8003746: 70bb strb r3, [r7, #2]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8003748: 2300 movs r3, #0
|
|
800374a: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
800374c: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8003750: 2b00 cmp r3, #0
|
|
8003752: da0f bge.n 8003774 <HAL_PCD_EP_Open+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8003754: 78fb ldrb r3, [r7, #3]
|
|
8003756: f003 020f and.w r2, r3, #15
|
|
800375a: 4613 mov r3, r2
|
|
800375c: 00db lsls r3, r3, #3
|
|
800375e: 4413 add r3, r2
|
|
8003760: 009b lsls r3, r3, #2
|
|
8003762: 3310 adds r3, #16
|
|
8003764: 687a ldr r2, [r7, #4]
|
|
8003766: 4413 add r3, r2
|
|
8003768: 3304 adds r3, #4
|
|
800376a: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
800376c: 68fb ldr r3, [r7, #12]
|
|
800376e: 2201 movs r2, #1
|
|
8003770: 705a strb r2, [r3, #1]
|
|
8003772: e00f b.n 8003794 <HAL_PCD_EP_Open+0x66>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8003774: 78fb ldrb r3, [r7, #3]
|
|
8003776: f003 020f and.w r2, r3, #15
|
|
800377a: 4613 mov r3, r2
|
|
800377c: 00db lsls r3, r3, #3
|
|
800377e: 4413 add r3, r2
|
|
8003780: 009b lsls r3, r3, #2
|
|
8003782: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003786: 687a ldr r2, [r7, #4]
|
|
8003788: 4413 add r3, r2
|
|
800378a: 3304 adds r3, #4
|
|
800378c: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
800378e: 68fb ldr r3, [r7, #12]
|
|
8003790: 2200 movs r2, #0
|
|
8003792: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8003794: 78fb ldrb r3, [r7, #3]
|
|
8003796: f003 030f and.w r3, r3, #15
|
|
800379a: b2da uxtb r2, r3
|
|
800379c: 68fb ldr r3, [r7, #12]
|
|
800379e: 701a strb r2, [r3, #0]
|
|
ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
|
|
80037a0: 883b ldrh r3, [r7, #0]
|
|
80037a2: f3c3 020a ubfx r2, r3, #0, #11
|
|
80037a6: 68fb ldr r3, [r7, #12]
|
|
80037a8: 609a str r2, [r3, #8]
|
|
ep->type = ep_type;
|
|
80037aa: 68fb ldr r3, [r7, #12]
|
|
80037ac: 78ba ldrb r2, [r7, #2]
|
|
80037ae: 711a strb r2, [r3, #4]
|
|
|
|
if (ep->is_in != 0U)
|
|
80037b0: 68fb ldr r3, [r7, #12]
|
|
80037b2: 785b ldrb r3, [r3, #1]
|
|
80037b4: 2b00 cmp r3, #0
|
|
80037b6: d004 beq.n 80037c2 <HAL_PCD_EP_Open+0x94>
|
|
{
|
|
/* Assign a Tx FIFO */
|
|
ep->tx_fifo_num = ep->num;
|
|
80037b8: 68fb ldr r3, [r7, #12]
|
|
80037ba: 781b ldrb r3, [r3, #0]
|
|
80037bc: 461a mov r2, r3
|
|
80037be: 68fb ldr r3, [r7, #12]
|
|
80037c0: 835a strh r2, [r3, #26]
|
|
}
|
|
|
|
/* Set initial data PID. */
|
|
if (ep_type == EP_TYPE_BULK)
|
|
80037c2: 78bb ldrb r3, [r7, #2]
|
|
80037c4: 2b02 cmp r3, #2
|
|
80037c6: d102 bne.n 80037ce <HAL_PCD_EP_Open+0xa0>
|
|
{
|
|
ep->data_pid_start = 0U;
|
|
80037c8: 68fb ldr r3, [r7, #12]
|
|
80037ca: 2200 movs r2, #0
|
|
80037cc: 715a strb r2, [r3, #5]
|
|
}
|
|
|
|
__HAL_LOCK(hpcd);
|
|
80037ce: 687b ldr r3, [r7, #4]
|
|
80037d0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
80037d4: 2b01 cmp r3, #1
|
|
80037d6: d101 bne.n 80037dc <HAL_PCD_EP_Open+0xae>
|
|
80037d8: 2302 movs r3, #2
|
|
80037da: e00e b.n 80037fa <HAL_PCD_EP_Open+0xcc>
|
|
80037dc: 687b ldr r3, [r7, #4]
|
|
80037de: 2201 movs r2, #1
|
|
80037e0: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
|
|
80037e4: 687b ldr r3, [r7, #4]
|
|
80037e6: 681b ldr r3, [r3, #0]
|
|
80037e8: 68f9 ldr r1, [r7, #12]
|
|
80037ea: 4618 mov r0, r3
|
|
80037ec: f003 fe94 bl 8007518 <USB_ActivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
80037f0: 687b ldr r3, [r7, #4]
|
|
80037f2: 2200 movs r2, #0
|
|
80037f4: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return ret;
|
|
80037f8: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
80037fa: 4618 mov r0, r3
|
|
80037fc: 3710 adds r7, #16
|
|
80037fe: 46bd mov sp, r7
|
|
8003800: bd80 pop {r7, pc}
|
|
|
|
08003802 <HAL_PCD_EP_Close>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8003802: b580 push {r7, lr}
|
|
8003804: b084 sub sp, #16
|
|
8003806: af00 add r7, sp, #0
|
|
8003808: 6078 str r0, [r7, #4]
|
|
800380a: 460b mov r3, r1
|
|
800380c: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
800380e: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8003812: 2b00 cmp r3, #0
|
|
8003814: da0f bge.n 8003836 <HAL_PCD_EP_Close+0x34>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8003816: 78fb ldrb r3, [r7, #3]
|
|
8003818: f003 020f and.w r2, r3, #15
|
|
800381c: 4613 mov r3, r2
|
|
800381e: 00db lsls r3, r3, #3
|
|
8003820: 4413 add r3, r2
|
|
8003822: 009b lsls r3, r3, #2
|
|
8003824: 3310 adds r3, #16
|
|
8003826: 687a ldr r2, [r7, #4]
|
|
8003828: 4413 add r3, r2
|
|
800382a: 3304 adds r3, #4
|
|
800382c: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
800382e: 68fb ldr r3, [r7, #12]
|
|
8003830: 2201 movs r2, #1
|
|
8003832: 705a strb r2, [r3, #1]
|
|
8003834: e00f b.n 8003856 <HAL_PCD_EP_Close+0x54>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8003836: 78fb ldrb r3, [r7, #3]
|
|
8003838: f003 020f and.w r2, r3, #15
|
|
800383c: 4613 mov r3, r2
|
|
800383e: 00db lsls r3, r3, #3
|
|
8003840: 4413 add r3, r2
|
|
8003842: 009b lsls r3, r3, #2
|
|
8003844: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003848: 687a ldr r2, [r7, #4]
|
|
800384a: 4413 add r3, r2
|
|
800384c: 3304 adds r3, #4
|
|
800384e: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8003850: 68fb ldr r3, [r7, #12]
|
|
8003852: 2200 movs r2, #0
|
|
8003854: 705a strb r2, [r3, #1]
|
|
}
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8003856: 78fb ldrb r3, [r7, #3]
|
|
8003858: f003 030f and.w r3, r3, #15
|
|
800385c: b2da uxtb r2, r3
|
|
800385e: 68fb ldr r3, [r7, #12]
|
|
8003860: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8003862: 687b ldr r3, [r7, #4]
|
|
8003864: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8003868: 2b01 cmp r3, #1
|
|
800386a: d101 bne.n 8003870 <HAL_PCD_EP_Close+0x6e>
|
|
800386c: 2302 movs r3, #2
|
|
800386e: e00e b.n 800388e <HAL_PCD_EP_Close+0x8c>
|
|
8003870: 687b ldr r3, [r7, #4]
|
|
8003872: 2201 movs r2, #1
|
|
8003874: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
|
|
8003878: 687b ldr r3, [r7, #4]
|
|
800387a: 681b ldr r3, [r3, #0]
|
|
800387c: 68f9 ldr r1, [r7, #12]
|
|
800387e: 4618 mov r0, r3
|
|
8003880: f003 fed2 bl 8007628 <USB_DeactivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
8003884: 687b ldr r3, [r7, #4]
|
|
8003886: 2200 movs r2, #0
|
|
8003888: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
return HAL_OK;
|
|
800388c: 2300 movs r3, #0
|
|
}
|
|
800388e: 4618 mov r0, r3
|
|
8003890: 3710 adds r7, #16
|
|
8003892: 46bd mov sp, r7
|
|
8003894: bd80 pop {r7, pc}
|
|
|
|
08003896 <HAL_PCD_EP_Receive>:
|
|
* @param pBuf pointer to the reception buffer
|
|
* @param len amount of data to be received
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
8003896: b580 push {r7, lr}
|
|
8003898: b086 sub sp, #24
|
|
800389a: af00 add r7, sp, #0
|
|
800389c: 60f8 str r0, [r7, #12]
|
|
800389e: 607a str r2, [r7, #4]
|
|
80038a0: 603b str r3, [r7, #0]
|
|
80038a2: 460b mov r3, r1
|
|
80038a4: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
80038a6: 7afb ldrb r3, [r7, #11]
|
|
80038a8: f003 020f and.w r2, r3, #15
|
|
80038ac: 4613 mov r3, r2
|
|
80038ae: 00db lsls r3, r3, #3
|
|
80038b0: 4413 add r3, r2
|
|
80038b2: 009b lsls r3, r3, #2
|
|
80038b4: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
80038b8: 68fa ldr r2, [r7, #12]
|
|
80038ba: 4413 add r3, r2
|
|
80038bc: 3304 adds r3, #4
|
|
80038be: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
80038c0: 697b ldr r3, [r7, #20]
|
|
80038c2: 687a ldr r2, [r7, #4]
|
|
80038c4: 60da str r2, [r3, #12]
|
|
ep->xfer_len = len;
|
|
80038c6: 697b ldr r3, [r7, #20]
|
|
80038c8: 683a ldr r2, [r7, #0]
|
|
80038ca: 611a str r2, [r3, #16]
|
|
ep->xfer_count = 0U;
|
|
80038cc: 697b ldr r3, [r7, #20]
|
|
80038ce: 2200 movs r2, #0
|
|
80038d0: 615a str r2, [r3, #20]
|
|
ep->is_in = 0U;
|
|
80038d2: 697b ldr r3, [r7, #20]
|
|
80038d4: 2200 movs r2, #0
|
|
80038d6: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
80038d8: 7afb ldrb r3, [r7, #11]
|
|
80038da: f003 030f and.w r3, r3, #15
|
|
80038de: b2da uxtb r2, r3
|
|
80038e0: 697b ldr r3, [r7, #20]
|
|
80038e2: 701a strb r2, [r3, #0]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
80038e4: 68fb ldr r3, [r7, #12]
|
|
80038e6: 799b ldrb r3, [r3, #6]
|
|
80038e8: 2b01 cmp r3, #1
|
|
80038ea: d102 bne.n 80038f2 <HAL_PCD_EP_Receive+0x5c>
|
|
{
|
|
ep->dma_addr = (uint32_t)pBuf;
|
|
80038ec: 687a ldr r2, [r7, #4]
|
|
80038ee: 697b ldr r3, [r7, #20]
|
|
80038f0: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
|
|
80038f2: 68fb ldr r3, [r7, #12]
|
|
80038f4: 6818 ldr r0, [r3, #0]
|
|
80038f6: 68fb ldr r3, [r7, #12]
|
|
80038f8: 799b ldrb r3, [r3, #6]
|
|
80038fa: 461a mov r2, r3
|
|
80038fc: 6979 ldr r1, [r7, #20]
|
|
80038fe: f003 ff6f bl 80077e0 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
8003902: 2300 movs r3, #0
|
|
}
|
|
8003904: 4618 mov r0, r3
|
|
8003906: 3718 adds r7, #24
|
|
8003908: 46bd mov sp, r7
|
|
800390a: bd80 pop {r7, pc}
|
|
|
|
0800390c <HAL_PCD_EP_Transmit>:
|
|
* @param pBuf pointer to the transmission buffer
|
|
* @param len amount of data to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
800390c: b580 push {r7, lr}
|
|
800390e: b086 sub sp, #24
|
|
8003910: af00 add r7, sp, #0
|
|
8003912: 60f8 str r0, [r7, #12]
|
|
8003914: 607a str r2, [r7, #4]
|
|
8003916: 603b str r3, [r7, #0]
|
|
8003918: 460b mov r3, r1
|
|
800391a: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
800391c: 7afb ldrb r3, [r7, #11]
|
|
800391e: f003 020f and.w r2, r3, #15
|
|
8003922: 4613 mov r3, r2
|
|
8003924: 00db lsls r3, r3, #3
|
|
8003926: 4413 add r3, r2
|
|
8003928: 009b lsls r3, r3, #2
|
|
800392a: 3310 adds r3, #16
|
|
800392c: 68fa ldr r2, [r7, #12]
|
|
800392e: 4413 add r3, r2
|
|
8003930: 3304 adds r3, #4
|
|
8003932: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
8003934: 697b ldr r3, [r7, #20]
|
|
8003936: 687a ldr r2, [r7, #4]
|
|
8003938: 60da str r2, [r3, #12]
|
|
ep->xfer_len = len;
|
|
800393a: 697b ldr r3, [r7, #20]
|
|
800393c: 683a ldr r2, [r7, #0]
|
|
800393e: 611a str r2, [r3, #16]
|
|
ep->xfer_count = 0U;
|
|
8003940: 697b ldr r3, [r7, #20]
|
|
8003942: 2200 movs r2, #0
|
|
8003944: 615a str r2, [r3, #20]
|
|
ep->is_in = 1U;
|
|
8003946: 697b ldr r3, [r7, #20]
|
|
8003948: 2201 movs r2, #1
|
|
800394a: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
800394c: 7afb ldrb r3, [r7, #11]
|
|
800394e: f003 030f and.w r3, r3, #15
|
|
8003952: b2da uxtb r2, r3
|
|
8003954: 697b ldr r3, [r7, #20]
|
|
8003956: 701a strb r2, [r3, #0]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8003958: 68fb ldr r3, [r7, #12]
|
|
800395a: 799b ldrb r3, [r3, #6]
|
|
800395c: 2b01 cmp r3, #1
|
|
800395e: d102 bne.n 8003966 <HAL_PCD_EP_Transmit+0x5a>
|
|
{
|
|
ep->dma_addr = (uint32_t)pBuf;
|
|
8003960: 687a ldr r2, [r7, #4]
|
|
8003962: 697b ldr r3, [r7, #20]
|
|
8003964: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
|
|
8003966: 68fb ldr r3, [r7, #12]
|
|
8003968: 6818 ldr r0, [r3, #0]
|
|
800396a: 68fb ldr r3, [r7, #12]
|
|
800396c: 799b ldrb r3, [r3, #6]
|
|
800396e: 461a mov r2, r3
|
|
8003970: 6979 ldr r1, [r7, #20]
|
|
8003972: f003 ff35 bl 80077e0 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
8003976: 2300 movs r3, #0
|
|
}
|
|
8003978: 4618 mov r0, r3
|
|
800397a: 3718 adds r7, #24
|
|
800397c: 46bd mov sp, r7
|
|
800397e: bd80 pop {r7, pc}
|
|
|
|
08003980 <HAL_PCD_EP_SetStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8003980: b580 push {r7, lr}
|
|
8003982: b084 sub sp, #16
|
|
8003984: af00 add r7, sp, #0
|
|
8003986: 6078 str r0, [r7, #4]
|
|
8003988: 460b mov r3, r1
|
|
800398a: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
|
|
800398c: 78fb ldrb r3, [r7, #3]
|
|
800398e: f003 030f and.w r3, r3, #15
|
|
8003992: 687a ldr r2, [r7, #4]
|
|
8003994: 7912 ldrb r2, [r2, #4]
|
|
8003996: 4293 cmp r3, r2
|
|
8003998: d901 bls.n 800399e <HAL_PCD_EP_SetStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
800399a: 2301 movs r3, #1
|
|
800399c: e04f b.n 8003a3e <HAL_PCD_EP_SetStall+0xbe>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
800399e: f997 3003 ldrsb.w r3, [r7, #3]
|
|
80039a2: 2b00 cmp r3, #0
|
|
80039a4: da0f bge.n 80039c6 <HAL_PCD_EP_SetStall+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
80039a6: 78fb ldrb r3, [r7, #3]
|
|
80039a8: f003 020f and.w r2, r3, #15
|
|
80039ac: 4613 mov r3, r2
|
|
80039ae: 00db lsls r3, r3, #3
|
|
80039b0: 4413 add r3, r2
|
|
80039b2: 009b lsls r3, r3, #2
|
|
80039b4: 3310 adds r3, #16
|
|
80039b6: 687a ldr r2, [r7, #4]
|
|
80039b8: 4413 add r3, r2
|
|
80039ba: 3304 adds r3, #4
|
|
80039bc: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
80039be: 68fb ldr r3, [r7, #12]
|
|
80039c0: 2201 movs r2, #1
|
|
80039c2: 705a strb r2, [r3, #1]
|
|
80039c4: e00d b.n 80039e2 <HAL_PCD_EP_SetStall+0x62>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr];
|
|
80039c6: 78fa ldrb r2, [r7, #3]
|
|
80039c8: 4613 mov r3, r2
|
|
80039ca: 00db lsls r3, r3, #3
|
|
80039cc: 4413 add r3, r2
|
|
80039ce: 009b lsls r3, r3, #2
|
|
80039d0: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
80039d4: 687a ldr r2, [r7, #4]
|
|
80039d6: 4413 add r3, r2
|
|
80039d8: 3304 adds r3, #4
|
|
80039da: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
80039dc: 68fb ldr r3, [r7, #12]
|
|
80039de: 2200 movs r2, #0
|
|
80039e0: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 1U;
|
|
80039e2: 68fb ldr r3, [r7, #12]
|
|
80039e4: 2201 movs r2, #1
|
|
80039e6: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
80039e8: 78fb ldrb r3, [r7, #3]
|
|
80039ea: f003 030f and.w r3, r3, #15
|
|
80039ee: b2da uxtb r2, r3
|
|
80039f0: 68fb ldr r3, [r7, #12]
|
|
80039f2: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
80039f4: 687b ldr r3, [r7, #4]
|
|
80039f6: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
80039fa: 2b01 cmp r3, #1
|
|
80039fc: d101 bne.n 8003a02 <HAL_PCD_EP_SetStall+0x82>
|
|
80039fe: 2302 movs r3, #2
|
|
8003a00: e01d b.n 8003a3e <HAL_PCD_EP_SetStall+0xbe>
|
|
8003a02: 687b ldr r3, [r7, #4]
|
|
8003a04: 2201 movs r2, #1
|
|
8003a06: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
(void)USB_EPSetStall(hpcd->Instance, ep);
|
|
8003a0a: 687b ldr r3, [r7, #4]
|
|
8003a0c: 681b ldr r3, [r3, #0]
|
|
8003a0e: 68f9 ldr r1, [r7, #12]
|
|
8003a10: 4618 mov r0, r3
|
|
8003a12: f004 fac3 bl 8007f9c <USB_EPSetStall>
|
|
|
|
if ((ep_addr & EP_ADDR_MSK) == 0U)
|
|
8003a16: 78fb ldrb r3, [r7, #3]
|
|
8003a18: f003 030f and.w r3, r3, #15
|
|
8003a1c: 2b00 cmp r3, #0
|
|
8003a1e: d109 bne.n 8003a34 <HAL_PCD_EP_SetStall+0xb4>
|
|
{
|
|
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
|
|
8003a20: 687b ldr r3, [r7, #4]
|
|
8003a22: 6818 ldr r0, [r3, #0]
|
|
8003a24: 687b ldr r3, [r7, #4]
|
|
8003a26: 7999 ldrb r1, [r3, #6]
|
|
8003a28: 687b ldr r3, [r7, #4]
|
|
8003a2a: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8003a2e: 461a mov r2, r3
|
|
8003a30: f004 fcb4 bl 800839c <USB_EP0_OutStart>
|
|
}
|
|
|
|
__HAL_UNLOCK(hpcd);
|
|
8003a34: 687b ldr r3, [r7, #4]
|
|
8003a36: 2200 movs r2, #0
|
|
8003a38: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8003a3c: 2300 movs r3, #0
|
|
}
|
|
8003a3e: 4618 mov r0, r3
|
|
8003a40: 3710 adds r7, #16
|
|
8003a42: 46bd mov sp, r7
|
|
8003a44: bd80 pop {r7, pc}
|
|
|
|
08003a46 <HAL_PCD_EP_ClrStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8003a46: b580 push {r7, lr}
|
|
8003a48: b084 sub sp, #16
|
|
8003a4a: af00 add r7, sp, #0
|
|
8003a4c: 6078 str r0, [r7, #4]
|
|
8003a4e: 460b mov r3, r1
|
|
8003a50: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
|
|
8003a52: 78fb ldrb r3, [r7, #3]
|
|
8003a54: f003 030f and.w r3, r3, #15
|
|
8003a58: 687a ldr r2, [r7, #4]
|
|
8003a5a: 7912 ldrb r2, [r2, #4]
|
|
8003a5c: 4293 cmp r3, r2
|
|
8003a5e: d901 bls.n 8003a64 <HAL_PCD_EP_ClrStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8003a60: 2301 movs r3, #1
|
|
8003a62: e042 b.n 8003aea <HAL_PCD_EP_ClrStall+0xa4>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8003a64: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8003a68: 2b00 cmp r3, #0
|
|
8003a6a: da0f bge.n 8003a8c <HAL_PCD_EP_ClrStall+0x46>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8003a6c: 78fb ldrb r3, [r7, #3]
|
|
8003a6e: f003 020f and.w r2, r3, #15
|
|
8003a72: 4613 mov r3, r2
|
|
8003a74: 00db lsls r3, r3, #3
|
|
8003a76: 4413 add r3, r2
|
|
8003a78: 009b lsls r3, r3, #2
|
|
8003a7a: 3310 adds r3, #16
|
|
8003a7c: 687a ldr r2, [r7, #4]
|
|
8003a7e: 4413 add r3, r2
|
|
8003a80: 3304 adds r3, #4
|
|
8003a82: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8003a84: 68fb ldr r3, [r7, #12]
|
|
8003a86: 2201 movs r2, #1
|
|
8003a88: 705a strb r2, [r3, #1]
|
|
8003a8a: e00f b.n 8003aac <HAL_PCD_EP_ClrStall+0x66>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8003a8c: 78fb ldrb r3, [r7, #3]
|
|
8003a8e: f003 020f and.w r2, r3, #15
|
|
8003a92: 4613 mov r3, r2
|
|
8003a94: 00db lsls r3, r3, #3
|
|
8003a96: 4413 add r3, r2
|
|
8003a98: 009b lsls r3, r3, #2
|
|
8003a9a: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003a9e: 687a ldr r2, [r7, #4]
|
|
8003aa0: 4413 add r3, r2
|
|
8003aa2: 3304 adds r3, #4
|
|
8003aa4: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8003aa6: 68fb ldr r3, [r7, #12]
|
|
8003aa8: 2200 movs r2, #0
|
|
8003aaa: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 0U;
|
|
8003aac: 68fb ldr r3, [r7, #12]
|
|
8003aae: 2200 movs r2, #0
|
|
8003ab0: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8003ab2: 78fb ldrb r3, [r7, #3]
|
|
8003ab4: f003 030f and.w r3, r3, #15
|
|
8003ab8: b2da uxtb r2, r3
|
|
8003aba: 68fb ldr r3, [r7, #12]
|
|
8003abc: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8003abe: 687b ldr r3, [r7, #4]
|
|
8003ac0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494
|
|
8003ac4: 2b01 cmp r3, #1
|
|
8003ac6: d101 bne.n 8003acc <HAL_PCD_EP_ClrStall+0x86>
|
|
8003ac8: 2302 movs r3, #2
|
|
8003aca: e00e b.n 8003aea <HAL_PCD_EP_ClrStall+0xa4>
|
|
8003acc: 687b ldr r3, [r7, #4]
|
|
8003ace: 2201 movs r2, #1
|
|
8003ad0: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
(void)USB_EPClearStall(hpcd->Instance, ep);
|
|
8003ad4: 687b ldr r3, [r7, #4]
|
|
8003ad6: 681b ldr r3, [r3, #0]
|
|
8003ad8: 68f9 ldr r1, [r7, #12]
|
|
8003ada: 4618 mov r0, r3
|
|
8003adc: f004 facc bl 8008078 <USB_EPClearStall>
|
|
__HAL_UNLOCK(hpcd);
|
|
8003ae0: 687b ldr r3, [r7, #4]
|
|
8003ae2: 2200 movs r2, #0
|
|
8003ae4: f883 2494 strb.w r2, [r3, #1172] @ 0x494
|
|
|
|
return HAL_OK;
|
|
8003ae8: 2300 movs r3, #0
|
|
}
|
|
8003aea: 4618 mov r0, r3
|
|
8003aec: 3710 adds r7, #16
|
|
8003aee: 46bd mov sp, r7
|
|
8003af0: bd80 pop {r7, pc}
|
|
|
|
08003af2 <HAL_PCD_EP_Abort>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8003af2: b580 push {r7, lr}
|
|
8003af4: b084 sub sp, #16
|
|
8003af6: af00 add r7, sp, #0
|
|
8003af8: 6078 str r0, [r7, #4]
|
|
8003afa: 460b mov r3, r1
|
|
8003afc: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef ret;
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8003afe: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8003b02: 2b00 cmp r3, #0
|
|
8003b04: da0c bge.n 8003b20 <HAL_PCD_EP_Abort+0x2e>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8003b06: 78fb ldrb r3, [r7, #3]
|
|
8003b08: f003 020f and.w r2, r3, #15
|
|
8003b0c: 4613 mov r3, r2
|
|
8003b0e: 00db lsls r3, r3, #3
|
|
8003b10: 4413 add r3, r2
|
|
8003b12: 009b lsls r3, r3, #2
|
|
8003b14: 3310 adds r3, #16
|
|
8003b16: 687a ldr r2, [r7, #4]
|
|
8003b18: 4413 add r3, r2
|
|
8003b1a: 3304 adds r3, #4
|
|
8003b1c: 60fb str r3, [r7, #12]
|
|
8003b1e: e00c b.n 8003b3a <HAL_PCD_EP_Abort+0x48>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8003b20: 78fb ldrb r3, [r7, #3]
|
|
8003b22: f003 020f and.w r2, r3, #15
|
|
8003b26: 4613 mov r3, r2
|
|
8003b28: 00db lsls r3, r3, #3
|
|
8003b2a: 4413 add r3, r2
|
|
8003b2c: 009b lsls r3, r3, #2
|
|
8003b2e: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003b32: 687a ldr r2, [r7, #4]
|
|
8003b34: 4413 add r3, r2
|
|
8003b36: 3304 adds r3, #4
|
|
8003b38: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Stop Xfer */
|
|
ret = USB_EPStopXfer(hpcd->Instance, ep);
|
|
8003b3a: 687b ldr r3, [r7, #4]
|
|
8003b3c: 681b ldr r3, [r3, #0]
|
|
8003b3e: 68f9 ldr r1, [r7, #12]
|
|
8003b40: 4618 mov r0, r3
|
|
8003b42: f004 f8eb bl 8007d1c <USB_EPStopXfer>
|
|
8003b46: 4603 mov r3, r0
|
|
8003b48: 72fb strb r3, [r7, #11]
|
|
|
|
return ret;
|
|
8003b4a: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
8003b4c: 4618 mov r0, r3
|
|
8003b4e: 3710 adds r7, #16
|
|
8003b50: 46bd mov sp, r7
|
|
8003b52: bd80 pop {r7, pc}
|
|
|
|
08003b54 <PCD_WriteEmptyTxFifo>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8003b54: b580 push {r7, lr}
|
|
8003b56: b08a sub sp, #40 @ 0x28
|
|
8003b58: af02 add r7, sp, #8
|
|
8003b5a: 6078 str r0, [r7, #4]
|
|
8003b5c: 6039 str r1, [r7, #0]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8003b5e: 687b ldr r3, [r7, #4]
|
|
8003b60: 681b ldr r3, [r3, #0]
|
|
8003b62: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8003b64: 697b ldr r3, [r7, #20]
|
|
8003b66: 613b str r3, [r7, #16]
|
|
USB_OTG_EPTypeDef *ep;
|
|
uint32_t len;
|
|
uint32_t len32b;
|
|
uint32_t fifoemptymsk;
|
|
|
|
ep = &hpcd->IN_ep[epnum];
|
|
8003b68: 683a ldr r2, [r7, #0]
|
|
8003b6a: 4613 mov r3, r2
|
|
8003b6c: 00db lsls r3, r3, #3
|
|
8003b6e: 4413 add r3, r2
|
|
8003b70: 009b lsls r3, r3, #2
|
|
8003b72: 3310 adds r3, #16
|
|
8003b74: 687a ldr r2, [r7, #4]
|
|
8003b76: 4413 add r3, r2
|
|
8003b78: 3304 adds r3, #4
|
|
8003b7a: 60fb str r3, [r7, #12]
|
|
|
|
if (ep->xfer_count > ep->xfer_len)
|
|
8003b7c: 68fb ldr r3, [r7, #12]
|
|
8003b7e: 695a ldr r2, [r3, #20]
|
|
8003b80: 68fb ldr r3, [r7, #12]
|
|
8003b82: 691b ldr r3, [r3, #16]
|
|
8003b84: 429a cmp r2, r3
|
|
8003b86: d901 bls.n 8003b8c <PCD_WriteEmptyTxFifo+0x38>
|
|
{
|
|
return HAL_ERROR;
|
|
8003b88: 2301 movs r3, #1
|
|
8003b8a: e06b b.n 8003c64 <PCD_WriteEmptyTxFifo+0x110>
|
|
}
|
|
|
|
len = ep->xfer_len - ep->xfer_count;
|
|
8003b8c: 68fb ldr r3, [r7, #12]
|
|
8003b8e: 691a ldr r2, [r3, #16]
|
|
8003b90: 68fb ldr r3, [r7, #12]
|
|
8003b92: 695b ldr r3, [r3, #20]
|
|
8003b94: 1ad3 subs r3, r2, r3
|
|
8003b96: 61fb str r3, [r7, #28]
|
|
|
|
if (len > ep->maxpacket)
|
|
8003b98: 68fb ldr r3, [r7, #12]
|
|
8003b9a: 689b ldr r3, [r3, #8]
|
|
8003b9c: 69fa ldr r2, [r7, #28]
|
|
8003b9e: 429a cmp r2, r3
|
|
8003ba0: d902 bls.n 8003ba8 <PCD_WriteEmptyTxFifo+0x54>
|
|
{
|
|
len = ep->maxpacket;
|
|
8003ba2: 68fb ldr r3, [r7, #12]
|
|
8003ba4: 689b ldr r3, [r3, #8]
|
|
8003ba6: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
len32b = (len + 3U) / 4U;
|
|
8003ba8: 69fb ldr r3, [r7, #28]
|
|
8003baa: 3303 adds r3, #3
|
|
8003bac: 089b lsrs r3, r3, #2
|
|
8003bae: 61bb str r3, [r7, #24]
|
|
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8003bb0: e02a b.n 8003c08 <PCD_WriteEmptyTxFifo+0xb4>
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
{
|
|
/* Write the FIFO */
|
|
len = ep->xfer_len - ep->xfer_count;
|
|
8003bb2: 68fb ldr r3, [r7, #12]
|
|
8003bb4: 691a ldr r2, [r3, #16]
|
|
8003bb6: 68fb ldr r3, [r7, #12]
|
|
8003bb8: 695b ldr r3, [r3, #20]
|
|
8003bba: 1ad3 subs r3, r2, r3
|
|
8003bbc: 61fb str r3, [r7, #28]
|
|
|
|
if (len > ep->maxpacket)
|
|
8003bbe: 68fb ldr r3, [r7, #12]
|
|
8003bc0: 689b ldr r3, [r3, #8]
|
|
8003bc2: 69fa ldr r2, [r7, #28]
|
|
8003bc4: 429a cmp r2, r3
|
|
8003bc6: d902 bls.n 8003bce <PCD_WriteEmptyTxFifo+0x7a>
|
|
{
|
|
len = ep->maxpacket;
|
|
8003bc8: 68fb ldr r3, [r7, #12]
|
|
8003bca: 689b ldr r3, [r3, #8]
|
|
8003bcc: 61fb str r3, [r7, #28]
|
|
}
|
|
len32b = (len + 3U) / 4U;
|
|
8003bce: 69fb ldr r3, [r7, #28]
|
|
8003bd0: 3303 adds r3, #3
|
|
8003bd2: 089b lsrs r3, r3, #2
|
|
8003bd4: 61bb str r3, [r7, #24]
|
|
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
|
|
8003bd6: 68fb ldr r3, [r7, #12]
|
|
8003bd8: 68d9 ldr r1, [r3, #12]
|
|
8003bda: 683b ldr r3, [r7, #0]
|
|
8003bdc: b2da uxtb r2, r3
|
|
8003bde: 69fb ldr r3, [r7, #28]
|
|
8003be0: b298 uxth r0, r3
|
|
(uint8_t)hpcd->Init.dma_enable);
|
|
8003be2: 687b ldr r3, [r7, #4]
|
|
8003be4: 799b ldrb r3, [r3, #6]
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
|
|
8003be6: 9300 str r3, [sp, #0]
|
|
8003be8: 4603 mov r3, r0
|
|
8003bea: 6978 ldr r0, [r7, #20]
|
|
8003bec: f004 f940 bl 8007e70 <USB_WritePacket>
|
|
|
|
ep->xfer_buff += len;
|
|
8003bf0: 68fb ldr r3, [r7, #12]
|
|
8003bf2: 68da ldr r2, [r3, #12]
|
|
8003bf4: 69fb ldr r3, [r7, #28]
|
|
8003bf6: 441a add r2, r3
|
|
8003bf8: 68fb ldr r3, [r7, #12]
|
|
8003bfa: 60da str r2, [r3, #12]
|
|
ep->xfer_count += len;
|
|
8003bfc: 68fb ldr r3, [r7, #12]
|
|
8003bfe: 695a ldr r2, [r3, #20]
|
|
8003c00: 69fb ldr r3, [r7, #28]
|
|
8003c02: 441a add r2, r3
|
|
8003c04: 68fb ldr r3, [r7, #12]
|
|
8003c06: 615a str r2, [r3, #20]
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8003c08: 683b ldr r3, [r7, #0]
|
|
8003c0a: 015a lsls r2, r3, #5
|
|
8003c0c: 693b ldr r3, [r7, #16]
|
|
8003c0e: 4413 add r3, r2
|
|
8003c10: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8003c14: 699b ldr r3, [r3, #24]
|
|
8003c16: b29b uxth r3, r3
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
8003c18: 69ba ldr r2, [r7, #24]
|
|
8003c1a: 429a cmp r2, r3
|
|
8003c1c: d809 bhi.n 8003c32 <PCD_WriteEmptyTxFifo+0xde>
|
|
8003c1e: 68fb ldr r3, [r7, #12]
|
|
8003c20: 695a ldr r2, [r3, #20]
|
|
8003c22: 68fb ldr r3, [r7, #12]
|
|
8003c24: 691b ldr r3, [r3, #16]
|
|
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
|
|
8003c26: 429a cmp r2, r3
|
|
8003c28: d203 bcs.n 8003c32 <PCD_WriteEmptyTxFifo+0xde>
|
|
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
|
|
8003c2a: 68fb ldr r3, [r7, #12]
|
|
8003c2c: 691b ldr r3, [r3, #16]
|
|
8003c2e: 2b00 cmp r3, #0
|
|
8003c30: d1bf bne.n 8003bb2 <PCD_WriteEmptyTxFifo+0x5e>
|
|
}
|
|
|
|
if (ep->xfer_len <= ep->xfer_count)
|
|
8003c32: 68fb ldr r3, [r7, #12]
|
|
8003c34: 691a ldr r2, [r3, #16]
|
|
8003c36: 68fb ldr r3, [r7, #12]
|
|
8003c38: 695b ldr r3, [r3, #20]
|
|
8003c3a: 429a cmp r2, r3
|
|
8003c3c: d811 bhi.n 8003c62 <PCD_WriteEmptyTxFifo+0x10e>
|
|
{
|
|
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
|
|
8003c3e: 683b ldr r3, [r7, #0]
|
|
8003c40: f003 030f and.w r3, r3, #15
|
|
8003c44: 2201 movs r2, #1
|
|
8003c46: fa02 f303 lsl.w r3, r2, r3
|
|
8003c4a: 60bb str r3, [r7, #8]
|
|
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
|
|
8003c4c: 693b ldr r3, [r7, #16]
|
|
8003c4e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8003c52: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8003c54: 68bb ldr r3, [r7, #8]
|
|
8003c56: 43db mvns r3, r3
|
|
8003c58: 6939 ldr r1, [r7, #16]
|
|
8003c5a: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8003c5e: 4013 ands r3, r2
|
|
8003c60: 634b str r3, [r1, #52] @ 0x34
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003c62: 2300 movs r3, #0
|
|
}
|
|
8003c64: 4618 mov r0, r3
|
|
8003c66: 3720 adds r7, #32
|
|
8003c68: 46bd mov sp, r7
|
|
8003c6a: bd80 pop {r7, pc}
|
|
|
|
08003c6c <PCD_EP_OutXfrComplete_int>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8003c6c: b580 push {r7, lr}
|
|
8003c6e: b088 sub sp, #32
|
|
8003c70: af00 add r7, sp, #0
|
|
8003c72: 6078 str r0, [r7, #4]
|
|
8003c74: 6039 str r1, [r7, #0]
|
|
USB_OTG_EPTypeDef *ep;
|
|
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8003c76: 687b ldr r3, [r7, #4]
|
|
8003c78: 681b ldr r3, [r3, #0]
|
|
8003c7a: 61fb str r3, [r7, #28]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8003c7c: 69fb ldr r3, [r7, #28]
|
|
8003c7e: 61bb str r3, [r7, #24]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
8003c80: 69fb ldr r3, [r7, #28]
|
|
8003c82: 333c adds r3, #60 @ 0x3c
|
|
8003c84: 3304 adds r3, #4
|
|
8003c86: 681b ldr r3, [r3, #0]
|
|
8003c88: 617b str r3, [r7, #20]
|
|
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
|
|
8003c8a: 683b ldr r3, [r7, #0]
|
|
8003c8c: 015a lsls r2, r3, #5
|
|
8003c8e: 69bb ldr r3, [r7, #24]
|
|
8003c90: 4413 add r3, r2
|
|
8003c92: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003c96: 689b ldr r3, [r3, #8]
|
|
8003c98: 613b str r3, [r7, #16]
|
|
|
|
if (hpcd->Init.dma_enable == 1U)
|
|
8003c9a: 687b ldr r3, [r7, #4]
|
|
8003c9c: 799b ldrb r3, [r3, #6]
|
|
8003c9e: 2b01 cmp r3, #1
|
|
8003ca0: d17b bne.n 8003d9a <PCD_EP_OutXfrComplete_int+0x12e>
|
|
{
|
|
if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
|
|
8003ca2: 693b ldr r3, [r7, #16]
|
|
8003ca4: f003 0308 and.w r3, r3, #8
|
|
8003ca8: 2b00 cmp r3, #0
|
|
8003caa: d015 beq.n 8003cd8 <PCD_EP_OutXfrComplete_int+0x6c>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8003cac: 697b ldr r3, [r7, #20]
|
|
8003cae: 4a61 ldr r2, [pc, #388] @ (8003e34 <PCD_EP_OutXfrComplete_int+0x1c8>)
|
|
8003cb0: 4293 cmp r3, r2
|
|
8003cb2: f240 80b9 bls.w 8003e28 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
8003cb6: 693b ldr r3, [r7, #16]
|
|
8003cb8: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8003cbc: 2b00 cmp r3, #0
|
|
8003cbe: f000 80b3 beq.w 8003e28 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8003cc2: 683b ldr r3, [r7, #0]
|
|
8003cc4: 015a lsls r2, r3, #5
|
|
8003cc6: 69bb ldr r3, [r7, #24]
|
|
8003cc8: 4413 add r3, r2
|
|
8003cca: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003cce: 461a mov r2, r3
|
|
8003cd0: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8003cd4: 6093 str r3, [r2, #8]
|
|
8003cd6: e0a7 b.n 8003e28 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
}
|
|
else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
|
|
8003cd8: 693b ldr r3, [r7, #16]
|
|
8003cda: f003 0320 and.w r3, r3, #32
|
|
8003cde: 2b00 cmp r3, #0
|
|
8003ce0: d009 beq.n 8003cf6 <PCD_EP_OutXfrComplete_int+0x8a>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
8003ce2: 683b ldr r3, [r7, #0]
|
|
8003ce4: 015a lsls r2, r3, #5
|
|
8003ce6: 69bb ldr r3, [r7, #24]
|
|
8003ce8: 4413 add r3, r2
|
|
8003cea: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003cee: 461a mov r2, r3
|
|
8003cf0: 2320 movs r3, #32
|
|
8003cf2: 6093 str r3, [r2, #8]
|
|
8003cf4: e098 b.n 8003e28 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
|
|
8003cf6: 693b ldr r3, [r7, #16]
|
|
8003cf8: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
8003cfc: 2b00 cmp r3, #0
|
|
8003cfe: f040 8093 bne.w 8003e28 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8003d02: 697b ldr r3, [r7, #20]
|
|
8003d04: 4a4b ldr r2, [pc, #300] @ (8003e34 <PCD_EP_OutXfrComplete_int+0x1c8>)
|
|
8003d06: 4293 cmp r3, r2
|
|
8003d08: d90f bls.n 8003d2a <PCD_EP_OutXfrComplete_int+0xbe>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
8003d0a: 693b ldr r3, [r7, #16]
|
|
8003d0c: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8003d10: 2b00 cmp r3, #0
|
|
8003d12: d00a beq.n 8003d2a <PCD_EP_OutXfrComplete_int+0xbe>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8003d14: 683b ldr r3, [r7, #0]
|
|
8003d16: 015a lsls r2, r3, #5
|
|
8003d18: 69bb ldr r3, [r7, #24]
|
|
8003d1a: 4413 add r3, r2
|
|
8003d1c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003d20: 461a mov r2, r3
|
|
8003d22: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8003d26: 6093 str r3, [r2, #8]
|
|
8003d28: e07e b.n 8003e28 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[epnum];
|
|
8003d2a: 683a ldr r2, [r7, #0]
|
|
8003d2c: 4613 mov r3, r2
|
|
8003d2e: 00db lsls r3, r3, #3
|
|
8003d30: 4413 add r3, r2
|
|
8003d32: 009b lsls r3, r3, #2
|
|
8003d34: f503 7314 add.w r3, r3, #592 @ 0x250
|
|
8003d38: 687a ldr r2, [r7, #4]
|
|
8003d3a: 4413 add r3, r2
|
|
8003d3c: 3304 adds r3, #4
|
|
8003d3e: 60fb str r3, [r7, #12]
|
|
|
|
/* out data packet received over EP */
|
|
ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
|
|
8003d40: 68fb ldr r3, [r7, #12]
|
|
8003d42: 6a1a ldr r2, [r3, #32]
|
|
8003d44: 683b ldr r3, [r7, #0]
|
|
8003d46: 0159 lsls r1, r3, #5
|
|
8003d48: 69bb ldr r3, [r7, #24]
|
|
8003d4a: 440b add r3, r1
|
|
8003d4c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003d50: 691b ldr r3, [r3, #16]
|
|
8003d52: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8003d56: 1ad2 subs r2, r2, r3
|
|
8003d58: 68fb ldr r3, [r7, #12]
|
|
8003d5a: 615a str r2, [r3, #20]
|
|
|
|
if (epnum == 0U)
|
|
8003d5c: 683b ldr r3, [r7, #0]
|
|
8003d5e: 2b00 cmp r3, #0
|
|
8003d60: d114 bne.n 8003d8c <PCD_EP_OutXfrComplete_int+0x120>
|
|
{
|
|
if (ep->xfer_len == 0U)
|
|
8003d62: 68fb ldr r3, [r7, #12]
|
|
8003d64: 691b ldr r3, [r3, #16]
|
|
8003d66: 2b00 cmp r3, #0
|
|
8003d68: d109 bne.n 8003d7e <PCD_EP_OutXfrComplete_int+0x112>
|
|
{
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
8003d6a: 687b ldr r3, [r7, #4]
|
|
8003d6c: 6818 ldr r0, [r3, #0]
|
|
8003d6e: 687b ldr r3, [r7, #4]
|
|
8003d70: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8003d74: 461a mov r2, r3
|
|
8003d76: 2101 movs r1, #1
|
|
8003d78: f004 fb10 bl 800839c <USB_EP0_OutStart>
|
|
8003d7c: e006 b.n 8003d8c <PCD_EP_OutXfrComplete_int+0x120>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_buff += ep->xfer_count;
|
|
8003d7e: 68fb ldr r3, [r7, #12]
|
|
8003d80: 68da ldr r2, [r3, #12]
|
|
8003d82: 68fb ldr r3, [r7, #12]
|
|
8003d84: 695b ldr r3, [r3, #20]
|
|
8003d86: 441a add r2, r3
|
|
8003d88: 68fb ldr r3, [r7, #12]
|
|
8003d8a: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
8003d8c: 683b ldr r3, [r7, #0]
|
|
8003d8e: b2db uxtb r3, r3
|
|
8003d90: 4619 mov r1, r3
|
|
8003d92: 6878 ldr r0, [r7, #4]
|
|
8003d94: f006 fade bl 800a354 <HAL_PCD_DataOutStageCallback>
|
|
8003d98: e046 b.n 8003e28 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
/* ... */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (gSNPSiD == USB_OTG_CORE_ID_310A)
|
|
8003d9a: 697b ldr r3, [r7, #20]
|
|
8003d9c: 4a26 ldr r2, [pc, #152] @ (8003e38 <PCD_EP_OutXfrComplete_int+0x1cc>)
|
|
8003d9e: 4293 cmp r3, r2
|
|
8003da0: d124 bne.n 8003dec <PCD_EP_OutXfrComplete_int+0x180>
|
|
{
|
|
/* StupPktRcvd = 1 this is a setup packet */
|
|
if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
|
|
8003da2: 693b ldr r3, [r7, #16]
|
|
8003da4: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8003da8: 2b00 cmp r3, #0
|
|
8003daa: d00a beq.n 8003dc2 <PCD_EP_OutXfrComplete_int+0x156>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8003dac: 683b ldr r3, [r7, #0]
|
|
8003dae: 015a lsls r2, r3, #5
|
|
8003db0: 69bb ldr r3, [r7, #24]
|
|
8003db2: 4413 add r3, r2
|
|
8003db4: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003db8: 461a mov r2, r3
|
|
8003dba: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8003dbe: 6093 str r3, [r2, #8]
|
|
8003dc0: e032 b.n 8003e28 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
}
|
|
else
|
|
{
|
|
if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
|
|
8003dc2: 693b ldr r3, [r7, #16]
|
|
8003dc4: f003 0320 and.w r3, r3, #32
|
|
8003dc8: 2b00 cmp r3, #0
|
|
8003dca: d008 beq.n 8003dde <PCD_EP_OutXfrComplete_int+0x172>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
|
|
8003dcc: 683b ldr r3, [r7, #0]
|
|
8003dce: 015a lsls r2, r3, #5
|
|
8003dd0: 69bb ldr r3, [r7, #24]
|
|
8003dd2: 4413 add r3, r2
|
|
8003dd4: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003dd8: 461a mov r2, r3
|
|
8003dda: 2320 movs r3, #32
|
|
8003ddc: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
8003dde: 683b ldr r3, [r7, #0]
|
|
8003de0: b2db uxtb r3, r3
|
|
8003de2: 4619 mov r1, r3
|
|
8003de4: 6878 ldr r0, [r7, #4]
|
|
8003de6: f006 fab5 bl 800a354 <HAL_PCD_DataOutStageCallback>
|
|
8003dea: e01d b.n 8003e28 <PCD_EP_OutXfrComplete_int+0x1bc>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
|
|
8003dec: 683b ldr r3, [r7, #0]
|
|
8003dee: 2b00 cmp r3, #0
|
|
8003df0: d114 bne.n 8003e1c <PCD_EP_OutXfrComplete_int+0x1b0>
|
|
8003df2: 6879 ldr r1, [r7, #4]
|
|
8003df4: 683a ldr r2, [r7, #0]
|
|
8003df6: 4613 mov r3, r2
|
|
8003df8: 00db lsls r3, r3, #3
|
|
8003dfa: 4413 add r3, r2
|
|
8003dfc: 009b lsls r3, r3, #2
|
|
8003dfe: 440b add r3, r1
|
|
8003e00: f503 7319 add.w r3, r3, #612 @ 0x264
|
|
8003e04: 681b ldr r3, [r3, #0]
|
|
8003e06: 2b00 cmp r3, #0
|
|
8003e08: d108 bne.n 8003e1c <PCD_EP_OutXfrComplete_int+0x1b0>
|
|
{
|
|
/* this is ZLP, so prepare EP0 for next setup */
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
|
|
8003e0a: 687b ldr r3, [r7, #4]
|
|
8003e0c: 6818 ldr r0, [r3, #0]
|
|
8003e0e: 687b ldr r3, [r7, #4]
|
|
8003e10: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8003e14: 461a mov r2, r3
|
|
8003e16: 2100 movs r1, #0
|
|
8003e18: f004 fac0 bl 800839c <USB_EP0_OutStart>
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
|
|
8003e1c: 683b ldr r3, [r7, #0]
|
|
8003e1e: b2db uxtb r3, r3
|
|
8003e20: 4619 mov r1, r3
|
|
8003e22: 6878 ldr r0, [r7, #4]
|
|
8003e24: f006 fa96 bl 800a354 <HAL_PCD_DataOutStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003e28: 2300 movs r3, #0
|
|
}
|
|
8003e2a: 4618 mov r0, r3
|
|
8003e2c: 3720 adds r7, #32
|
|
8003e2e: 46bd mov sp, r7
|
|
8003e30: bd80 pop {r7, pc}
|
|
8003e32: bf00 nop
|
|
8003e34: 4f54300a .word 0x4f54300a
|
|
8003e38: 4f54310a .word 0x4f54310a
|
|
|
|
08003e3c <PCD_EP_OutSetupPacket_int>:
|
|
* @param hpcd PCD handle
|
|
* @param epnum endpoint number
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
|
|
{
|
|
8003e3c: b580 push {r7, lr}
|
|
8003e3e: b086 sub sp, #24
|
|
8003e40: af00 add r7, sp, #0
|
|
8003e42: 6078 str r0, [r7, #4]
|
|
8003e44: 6039 str r1, [r7, #0]
|
|
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8003e46: 687b ldr r3, [r7, #4]
|
|
8003e48: 681b ldr r3, [r3, #0]
|
|
8003e4a: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8003e4c: 697b ldr r3, [r7, #20]
|
|
8003e4e: 613b str r3, [r7, #16]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
8003e50: 697b ldr r3, [r7, #20]
|
|
8003e52: 333c adds r3, #60 @ 0x3c
|
|
8003e54: 3304 adds r3, #4
|
|
8003e56: 681b ldr r3, [r3, #0]
|
|
8003e58: 60fb str r3, [r7, #12]
|
|
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
|
|
8003e5a: 683b ldr r3, [r7, #0]
|
|
8003e5c: 015a lsls r2, r3, #5
|
|
8003e5e: 693b ldr r3, [r7, #16]
|
|
8003e60: 4413 add r3, r2
|
|
8003e62: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003e66: 689b ldr r3, [r3, #8]
|
|
8003e68: 60bb str r3, [r7, #8]
|
|
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8003e6a: 68fb ldr r3, [r7, #12]
|
|
8003e6c: 4a15 ldr r2, [pc, #84] @ (8003ec4 <PCD_EP_OutSetupPacket_int+0x88>)
|
|
8003e6e: 4293 cmp r3, r2
|
|
8003e70: d90e bls.n 8003e90 <PCD_EP_OutSetupPacket_int+0x54>
|
|
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
|
|
8003e72: 68bb ldr r3, [r7, #8]
|
|
8003e74: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
|
|
8003e78: 2b00 cmp r3, #0
|
|
8003e7a: d009 beq.n 8003e90 <PCD_EP_OutSetupPacket_int+0x54>
|
|
{
|
|
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
|
|
8003e7c: 683b ldr r3, [r7, #0]
|
|
8003e7e: 015a lsls r2, r3, #5
|
|
8003e80: 693b ldr r3, [r7, #16]
|
|
8003e82: 4413 add r3, r2
|
|
8003e84: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8003e88: 461a mov r2, r3
|
|
8003e8a: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8003e8e: 6093 str r3, [r2, #8]
|
|
|
|
/* Inform the upper layer that a setup packet is available */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SetupStageCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SetupStageCallback(hpcd);
|
|
8003e90: 6878 ldr r0, [r7, #4]
|
|
8003e92: f006 fa4d bl 800a330 <HAL_PCD_SetupStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
|
|
8003e96: 68fb ldr r3, [r7, #12]
|
|
8003e98: 4a0a ldr r2, [pc, #40] @ (8003ec4 <PCD_EP_OutSetupPacket_int+0x88>)
|
|
8003e9a: 4293 cmp r3, r2
|
|
8003e9c: d90c bls.n 8003eb8 <PCD_EP_OutSetupPacket_int+0x7c>
|
|
8003e9e: 687b ldr r3, [r7, #4]
|
|
8003ea0: 799b ldrb r3, [r3, #6]
|
|
8003ea2: 2b01 cmp r3, #1
|
|
8003ea4: d108 bne.n 8003eb8 <PCD_EP_OutSetupPacket_int+0x7c>
|
|
{
|
|
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
|
|
8003ea6: 687b ldr r3, [r7, #4]
|
|
8003ea8: 6818 ldr r0, [r3, #0]
|
|
8003eaa: 687b ldr r3, [r7, #4]
|
|
8003eac: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
8003eb0: 461a mov r2, r3
|
|
8003eb2: 2101 movs r1, #1
|
|
8003eb4: f004 fa72 bl 800839c <USB_EP0_OutStart>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003eb8: 2300 movs r3, #0
|
|
}
|
|
8003eba: 4618 mov r0, r3
|
|
8003ebc: 3718 adds r7, #24
|
|
8003ebe: 46bd mov sp, r7
|
|
8003ec0: bd80 pop {r7, pc}
|
|
8003ec2: bf00 nop
|
|
8003ec4: 4f54300a .word 0x4f54300a
|
|
|
|
08003ec8 <HAL_PCDEx_SetTxFiFo>:
|
|
* @param fifo The number of Tx fifo
|
|
* @param size Fifo size
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
|
|
{
|
|
8003ec8: b480 push {r7}
|
|
8003eca: b085 sub sp, #20
|
|
8003ecc: af00 add r7, sp, #0
|
|
8003ece: 6078 str r0, [r7, #4]
|
|
8003ed0: 460b mov r3, r1
|
|
8003ed2: 70fb strb r3, [r7, #3]
|
|
8003ed4: 4613 mov r3, r2
|
|
8003ed6: 803b strh r3, [r7, #0]
|
|
--> Txn should be configured with the minimum space of 16 words
|
|
The FIFO is used optimally when used TxFIFOs are allocated in the top
|
|
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
|
|
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
|
|
|
|
Tx_Offset = hpcd->Instance->GRXFSIZ;
|
|
8003ed8: 687b ldr r3, [r7, #4]
|
|
8003eda: 681b ldr r3, [r3, #0]
|
|
8003edc: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003ede: 60bb str r3, [r7, #8]
|
|
|
|
if (fifo == 0U)
|
|
8003ee0: 78fb ldrb r3, [r7, #3]
|
|
8003ee2: 2b00 cmp r3, #0
|
|
8003ee4: d107 bne.n 8003ef6 <HAL_PCDEx_SetTxFiFo+0x2e>
|
|
{
|
|
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
|
|
8003ee6: 883b ldrh r3, [r7, #0]
|
|
8003ee8: 0419 lsls r1, r3, #16
|
|
8003eea: 687b ldr r3, [r7, #4]
|
|
8003eec: 681b ldr r3, [r3, #0]
|
|
8003eee: 68ba ldr r2, [r7, #8]
|
|
8003ef0: 430a orrs r2, r1
|
|
8003ef2: 629a str r2, [r3, #40] @ 0x28
|
|
8003ef4: e028 b.n 8003f48 <HAL_PCDEx_SetTxFiFo+0x80>
|
|
}
|
|
else
|
|
{
|
|
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
|
|
8003ef6: 687b ldr r3, [r7, #4]
|
|
8003ef8: 681b ldr r3, [r3, #0]
|
|
8003efa: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003efc: 0c1b lsrs r3, r3, #16
|
|
8003efe: 68ba ldr r2, [r7, #8]
|
|
8003f00: 4413 add r3, r2
|
|
8003f02: 60bb str r3, [r7, #8]
|
|
for (i = 0U; i < (fifo - 1U); i++)
|
|
8003f04: 2300 movs r3, #0
|
|
8003f06: 73fb strb r3, [r7, #15]
|
|
8003f08: e00d b.n 8003f26 <HAL_PCDEx_SetTxFiFo+0x5e>
|
|
{
|
|
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
|
|
8003f0a: 687b ldr r3, [r7, #4]
|
|
8003f0c: 681a ldr r2, [r3, #0]
|
|
8003f0e: 7bfb ldrb r3, [r7, #15]
|
|
8003f10: 3340 adds r3, #64 @ 0x40
|
|
8003f12: 009b lsls r3, r3, #2
|
|
8003f14: 4413 add r3, r2
|
|
8003f16: 685b ldr r3, [r3, #4]
|
|
8003f18: 0c1b lsrs r3, r3, #16
|
|
8003f1a: 68ba ldr r2, [r7, #8]
|
|
8003f1c: 4413 add r3, r2
|
|
8003f1e: 60bb str r3, [r7, #8]
|
|
for (i = 0U; i < (fifo - 1U); i++)
|
|
8003f20: 7bfb ldrb r3, [r7, #15]
|
|
8003f22: 3301 adds r3, #1
|
|
8003f24: 73fb strb r3, [r7, #15]
|
|
8003f26: 7bfa ldrb r2, [r7, #15]
|
|
8003f28: 78fb ldrb r3, [r7, #3]
|
|
8003f2a: 3b01 subs r3, #1
|
|
8003f2c: 429a cmp r2, r3
|
|
8003f2e: d3ec bcc.n 8003f0a <HAL_PCDEx_SetTxFiFo+0x42>
|
|
}
|
|
|
|
/* Multiply Tx_Size by 2 to get higher performance */
|
|
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
|
|
8003f30: 883b ldrh r3, [r7, #0]
|
|
8003f32: 0418 lsls r0, r3, #16
|
|
8003f34: 687b ldr r3, [r7, #4]
|
|
8003f36: 6819 ldr r1, [r3, #0]
|
|
8003f38: 78fb ldrb r3, [r7, #3]
|
|
8003f3a: 3b01 subs r3, #1
|
|
8003f3c: 68ba ldr r2, [r7, #8]
|
|
8003f3e: 4302 orrs r2, r0
|
|
8003f40: 3340 adds r3, #64 @ 0x40
|
|
8003f42: 009b lsls r3, r3, #2
|
|
8003f44: 440b add r3, r1
|
|
8003f46: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003f48: 2300 movs r3, #0
|
|
}
|
|
8003f4a: 4618 mov r0, r3
|
|
8003f4c: 3714 adds r7, #20
|
|
8003f4e: 46bd mov sp, r7
|
|
8003f50: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003f54: 4770 bx lr
|
|
|
|
08003f56 <HAL_PCDEx_SetRxFiFo>:
|
|
* @param hpcd PCD handle
|
|
* @param size Size of Rx fifo
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
|
|
{
|
|
8003f56: b480 push {r7}
|
|
8003f58: b083 sub sp, #12
|
|
8003f5a: af00 add r7, sp, #0
|
|
8003f5c: 6078 str r0, [r7, #4]
|
|
8003f5e: 460b mov r3, r1
|
|
8003f60: 807b strh r3, [r7, #2]
|
|
hpcd->Instance->GRXFSIZ = size;
|
|
8003f62: 687b ldr r3, [r7, #4]
|
|
8003f64: 681b ldr r3, [r3, #0]
|
|
8003f66: 887a ldrh r2, [r7, #2]
|
|
8003f68: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_OK;
|
|
8003f6a: 2300 movs r3, #0
|
|
}
|
|
8003f6c: 4618 mov r0, r3
|
|
8003f6e: 370c adds r7, #12
|
|
8003f70: 46bd mov sp, r7
|
|
8003f72: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003f76: 4770 bx lr
|
|
|
|
08003f78 <HAL_PCDEx_ActivateLPM>:
|
|
* @brief Activate LPM feature.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8003f78: b480 push {r7}
|
|
8003f7a: b085 sub sp, #20
|
|
8003f7c: af00 add r7, sp, #0
|
|
8003f7e: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
|
8003f80: 687b ldr r3, [r7, #4]
|
|
8003f82: 681b ldr r3, [r3, #0]
|
|
8003f84: 60fb str r3, [r7, #12]
|
|
|
|
hpcd->lpm_active = 1U;
|
|
8003f86: 687b ldr r3, [r7, #4]
|
|
8003f88: 2201 movs r2, #1
|
|
8003f8a: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8
|
|
hpcd->LPM_State = LPM_L0;
|
|
8003f8e: 687b ldr r3, [r7, #4]
|
|
8003f90: 2200 movs r2, #0
|
|
8003f92: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
|
|
8003f96: 68fb ldr r3, [r7, #12]
|
|
8003f98: 699b ldr r3, [r3, #24]
|
|
8003f9a: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000
|
|
8003f9e: 68fb ldr r3, [r7, #12]
|
|
8003fa0: 619a str r2, [r3, #24]
|
|
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
|
|
8003fa2: 68fb ldr r3, [r7, #12]
|
|
8003fa4: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8003fa6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8003faa: f043 0303 orr.w r3, r3, #3
|
|
8003fae: 68fa ldr r2, [r7, #12]
|
|
8003fb0: 6553 str r3, [r2, #84] @ 0x54
|
|
|
|
return HAL_OK;
|
|
8003fb2: 2300 movs r3, #0
|
|
}
|
|
8003fb4: 4618 mov r0, r3
|
|
8003fb6: 3714 adds r7, #20
|
|
8003fb8: 46bd mov sp, r7
|
|
8003fba: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003fbe: 4770 bx lr
|
|
|
|
08003fc0 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8003fc0: b580 push {r7, lr}
|
|
8003fc2: b084 sub sp, #16
|
|
8003fc4: af00 add r7, sp, #0
|
|
8003fc6: 6078 str r0, [r7, #4]
|
|
8003fc8: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
8003fca: 687b ldr r3, [r7, #4]
|
|
8003fcc: 2b00 cmp r3, #0
|
|
8003fce: d101 bne.n 8003fd4 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8003fd0: 2301 movs r3, #1
|
|
8003fd2: e0cc b.n 800416e <HAL_RCC_ClockConfig+0x1ae>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8003fd4: 4b68 ldr r3, [pc, #416] @ (8004178 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8003fd6: 681b ldr r3, [r3, #0]
|
|
8003fd8: f003 030f and.w r3, r3, #15
|
|
8003fdc: 683a ldr r2, [r7, #0]
|
|
8003fde: 429a cmp r2, r3
|
|
8003fe0: d90c bls.n 8003ffc <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8003fe2: 4b65 ldr r3, [pc, #404] @ (8004178 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8003fe4: 683a ldr r2, [r7, #0]
|
|
8003fe6: b2d2 uxtb r2, r2
|
|
8003fe8: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8003fea: 4b63 ldr r3, [pc, #396] @ (8004178 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8003fec: 681b ldr r3, [r3, #0]
|
|
8003fee: f003 030f and.w r3, r3, #15
|
|
8003ff2: 683a ldr r2, [r7, #0]
|
|
8003ff4: 429a cmp r2, r3
|
|
8003ff6: d001 beq.n 8003ffc <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003ff8: 2301 movs r3, #1
|
|
8003ffa: e0b8 b.n 800416e <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8003ffc: 687b ldr r3, [r7, #4]
|
|
8003ffe: 681b ldr r3, [r3, #0]
|
|
8004000: f003 0302 and.w r3, r3, #2
|
|
8004004: 2b00 cmp r3, #0
|
|
8004006: d020 beq.n 800404a <HAL_RCC_ClockConfig+0x8a>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8004008: 687b ldr r3, [r7, #4]
|
|
800400a: 681b ldr r3, [r3, #0]
|
|
800400c: f003 0304 and.w r3, r3, #4
|
|
8004010: 2b00 cmp r3, #0
|
|
8004012: d005 beq.n 8004020 <HAL_RCC_ClockConfig+0x60>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
8004014: 4b59 ldr r3, [pc, #356] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004016: 689b ldr r3, [r3, #8]
|
|
8004018: 4a58 ldr r2, [pc, #352] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
800401a: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
|
|
800401e: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8004020: 687b ldr r3, [r7, #4]
|
|
8004022: 681b ldr r3, [r3, #0]
|
|
8004024: f003 0308 and.w r3, r3, #8
|
|
8004028: 2b00 cmp r3, #0
|
|
800402a: d005 beq.n 8004038 <HAL_RCC_ClockConfig+0x78>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
800402c: 4b53 ldr r3, [pc, #332] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
800402e: 689b ldr r3, [r3, #8]
|
|
8004030: 4a52 ldr r2, [pc, #328] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004032: f443 4360 orr.w r3, r3, #57344 @ 0xe000
|
|
8004036: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8004038: 4b50 ldr r3, [pc, #320] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
800403a: 689b ldr r3, [r3, #8]
|
|
800403c: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8004040: 687b ldr r3, [r7, #4]
|
|
8004042: 689b ldr r3, [r3, #8]
|
|
8004044: 494d ldr r1, [pc, #308] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004046: 4313 orrs r3, r2
|
|
8004048: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
800404a: 687b ldr r3, [r7, #4]
|
|
800404c: 681b ldr r3, [r3, #0]
|
|
800404e: f003 0301 and.w r3, r3, #1
|
|
8004052: 2b00 cmp r3, #0
|
|
8004054: d044 beq.n 80040e0 <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8004056: 687b ldr r3, [r7, #4]
|
|
8004058: 685b ldr r3, [r3, #4]
|
|
800405a: 2b01 cmp r3, #1
|
|
800405c: d107 bne.n 800406e <HAL_RCC_ClockConfig+0xae>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
800405e: 4b47 ldr r3, [pc, #284] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004060: 681b ldr r3, [r3, #0]
|
|
8004062: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004066: 2b00 cmp r3, #0
|
|
8004068: d119 bne.n 800409e <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
800406a: 2301 movs r3, #1
|
|
800406c: e07f b.n 800416e <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
800406e: 687b ldr r3, [r7, #4]
|
|
8004070: 685b ldr r3, [r3, #4]
|
|
8004072: 2b02 cmp r3, #2
|
|
8004074: d003 beq.n 800407e <HAL_RCC_ClockConfig+0xbe>
|
|
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
|
|
8004076: 687b ldr r3, [r7, #4]
|
|
8004078: 685b ldr r3, [r3, #4]
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
800407a: 2b03 cmp r3, #3
|
|
800407c: d107 bne.n 800408e <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
800407e: 4b3f ldr r3, [pc, #252] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004080: 681b ldr r3, [r3, #0]
|
|
8004082: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8004086: 2b00 cmp r3, #0
|
|
8004088: d109 bne.n 800409e <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
800408a: 2301 movs r3, #1
|
|
800408c: e06f b.n 800416e <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
800408e: 4b3b ldr r3, [pc, #236] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004090: 681b ldr r3, [r3, #0]
|
|
8004092: f003 0302 and.w r3, r3, #2
|
|
8004096: 2b00 cmp r3, #0
|
|
8004098: d101 bne.n 800409e <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
800409a: 2301 movs r3, #1
|
|
800409c: e067 b.n 800416e <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
800409e: 4b37 ldr r3, [pc, #220] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
80040a0: 689b ldr r3, [r3, #8]
|
|
80040a2: f023 0203 bic.w r2, r3, #3
|
|
80040a6: 687b ldr r3, [r7, #4]
|
|
80040a8: 685b ldr r3, [r3, #4]
|
|
80040aa: 4934 ldr r1, [pc, #208] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
80040ac: 4313 orrs r3, r2
|
|
80040ae: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80040b0: f7fd fcb2 bl 8001a18 <HAL_GetTick>
|
|
80040b4: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80040b6: e00a b.n 80040ce <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80040b8: f7fd fcae bl 8001a18 <HAL_GetTick>
|
|
80040bc: 4602 mov r2, r0
|
|
80040be: 68fb ldr r3, [r7, #12]
|
|
80040c0: 1ad3 subs r3, r2, r3
|
|
80040c2: f241 3288 movw r2, #5000 @ 0x1388
|
|
80040c6: 4293 cmp r3, r2
|
|
80040c8: d901 bls.n 80040ce <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80040ca: 2303 movs r3, #3
|
|
80040cc: e04f b.n 800416e <HAL_RCC_ClockConfig+0x1ae>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80040ce: 4b2b ldr r3, [pc, #172] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
80040d0: 689b ldr r3, [r3, #8]
|
|
80040d2: f003 020c and.w r2, r3, #12
|
|
80040d6: 687b ldr r3, [r7, #4]
|
|
80040d8: 685b ldr r3, [r3, #4]
|
|
80040da: 009b lsls r3, r3, #2
|
|
80040dc: 429a cmp r2, r3
|
|
80040de: d1eb bne.n 80040b8 <HAL_RCC_ClockConfig+0xf8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
80040e0: 4b25 ldr r3, [pc, #148] @ (8004178 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80040e2: 681b ldr r3, [r3, #0]
|
|
80040e4: f003 030f and.w r3, r3, #15
|
|
80040e8: 683a ldr r2, [r7, #0]
|
|
80040ea: 429a cmp r2, r3
|
|
80040ec: d20c bcs.n 8004108 <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80040ee: 4b22 ldr r3, [pc, #136] @ (8004178 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80040f0: 683a ldr r2, [r7, #0]
|
|
80040f2: b2d2 uxtb r2, r2
|
|
80040f4: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80040f6: 4b20 ldr r3, [pc, #128] @ (8004178 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80040f8: 681b ldr r3, [r3, #0]
|
|
80040fa: f003 030f and.w r3, r3, #15
|
|
80040fe: 683a ldr r2, [r7, #0]
|
|
8004100: 429a cmp r2, r3
|
|
8004102: d001 beq.n 8004108 <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
return HAL_ERROR;
|
|
8004104: 2301 movs r3, #1
|
|
8004106: e032 b.n 800416e <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8004108: 687b ldr r3, [r7, #4]
|
|
800410a: 681b ldr r3, [r3, #0]
|
|
800410c: f003 0304 and.w r3, r3, #4
|
|
8004110: 2b00 cmp r3, #0
|
|
8004112: d008 beq.n 8004126 <HAL_RCC_ClockConfig+0x166>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8004114: 4b19 ldr r3, [pc, #100] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004116: 689b ldr r3, [r3, #8]
|
|
8004118: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
|
|
800411c: 687b ldr r3, [r7, #4]
|
|
800411e: 68db ldr r3, [r3, #12]
|
|
8004120: 4916 ldr r1, [pc, #88] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004122: 4313 orrs r3, r2
|
|
8004124: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8004126: 687b ldr r3, [r7, #4]
|
|
8004128: 681b ldr r3, [r3, #0]
|
|
800412a: f003 0308 and.w r3, r3, #8
|
|
800412e: 2b00 cmp r3, #0
|
|
8004130: d009 beq.n 8004146 <HAL_RCC_ClockConfig+0x186>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
8004132: 4b12 ldr r3, [pc, #72] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004134: 689b ldr r3, [r3, #8]
|
|
8004136: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
800413a: 687b ldr r3, [r7, #4]
|
|
800413c: 691b ldr r3, [r3, #16]
|
|
800413e: 00db lsls r3, r3, #3
|
|
8004140: 490e ldr r1, [pc, #56] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004142: 4313 orrs r3, r2
|
|
8004144: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
8004146: f000 fb7f bl 8004848 <HAL_RCC_GetSysClockFreq>
|
|
800414a: 4602 mov r2, r0
|
|
800414c: 4b0b ldr r3, [pc, #44] @ (800417c <HAL_RCC_ClockConfig+0x1bc>)
|
|
800414e: 689b ldr r3, [r3, #8]
|
|
8004150: 091b lsrs r3, r3, #4
|
|
8004152: f003 030f and.w r3, r3, #15
|
|
8004156: 490a ldr r1, [pc, #40] @ (8004180 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8004158: 5ccb ldrb r3, [r1, r3]
|
|
800415a: fa22 f303 lsr.w r3, r2, r3
|
|
800415e: 4a09 ldr r2, [pc, #36] @ (8004184 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004160: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings */
|
|
HAL_InitTick(uwTickPrio);
|
|
8004162: 4b09 ldr r3, [pc, #36] @ (8004188 <HAL_RCC_ClockConfig+0x1c8>)
|
|
8004164: 681b ldr r3, [r3, #0]
|
|
8004166: 4618 mov r0, r3
|
|
8004168: f7fd fc12 bl 8001990 <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
800416c: 2300 movs r3, #0
|
|
}
|
|
800416e: 4618 mov r0, r3
|
|
8004170: 3710 adds r7, #16
|
|
8004172: 46bd mov sp, r7
|
|
8004174: bd80 pop {r7, pc}
|
|
8004176: bf00 nop
|
|
8004178: 40023c00 .word 0x40023c00
|
|
800417c: 40023800 .word 0x40023800
|
|
8004180: 0800a9f0 .word 0x0800a9f0
|
|
8004184: 20000090 .word 0x20000090
|
|
8004188: 20000094 .word 0x20000094
|
|
|
|
0800418c <HAL_RCC_GetHCLKFreq>:
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
800418c: b480 push {r7}
|
|
800418e: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
8004190: 4b03 ldr r3, [pc, #12] @ (80041a0 <HAL_RCC_GetHCLKFreq+0x14>)
|
|
8004192: 681b ldr r3, [r3, #0]
|
|
}
|
|
8004194: 4618 mov r0, r3
|
|
8004196: 46bd mov sp, r7
|
|
8004198: f85d 7b04 ldr.w r7, [sp], #4
|
|
800419c: 4770 bx lr
|
|
800419e: bf00 nop
|
|
80041a0: 20000090 .word 0x20000090
|
|
|
|
080041a4 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
80041a4: b580 push {r7, lr}
|
|
80041a6: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
80041a8: f7ff fff0 bl 800418c <HAL_RCC_GetHCLKFreq>
|
|
80041ac: 4602 mov r2, r0
|
|
80041ae: 4b05 ldr r3, [pc, #20] @ (80041c4 <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
80041b0: 689b ldr r3, [r3, #8]
|
|
80041b2: 0a9b lsrs r3, r3, #10
|
|
80041b4: f003 0307 and.w r3, r3, #7
|
|
80041b8: 4903 ldr r1, [pc, #12] @ (80041c8 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
80041ba: 5ccb ldrb r3, [r1, r3]
|
|
80041bc: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80041c0: 4618 mov r0, r3
|
|
80041c2: bd80 pop {r7, pc}
|
|
80041c4: 40023800 .word 0x40023800
|
|
80041c8: 0800aa00 .word 0x0800aa00
|
|
|
|
080041cc <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
80041cc: b580 push {r7, lr}
|
|
80041ce: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
80041d0: f7ff ffdc bl 800418c <HAL_RCC_GetHCLKFreq>
|
|
80041d4: 4602 mov r2, r0
|
|
80041d6: 4b05 ldr r3, [pc, #20] @ (80041ec <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
80041d8: 689b ldr r3, [r3, #8]
|
|
80041da: 0b5b lsrs r3, r3, #13
|
|
80041dc: f003 0307 and.w r3, r3, #7
|
|
80041e0: 4903 ldr r1, [pc, #12] @ (80041f0 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
80041e2: 5ccb ldrb r3, [r1, r3]
|
|
80041e4: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80041e8: 4618 mov r0, r3
|
|
80041ea: bd80 pop {r7, pc}
|
|
80041ec: 40023800 .word 0x40023800
|
|
80041f0: 0800aa00 .word 0x0800aa00
|
|
|
|
080041f4 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the backup registers) and RCC_BDCR register are set to their reset values.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
80041f4: b580 push {r7, lr}
|
|
80041f6: b08c sub sp, #48 @ 0x30
|
|
80041f8: af00 add r7, sp, #0
|
|
80041fa: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
80041fc: 2300 movs r3, #0
|
|
80041fe: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t tmpreg1 = 0U;
|
|
8004200: 2300 movs r3, #0
|
|
8004202: 623b str r3, [r7, #32]
|
|
uint32_t plli2sp = 0U;
|
|
8004204: 2300 movs r3, #0
|
|
8004206: 61fb str r3, [r7, #28]
|
|
uint32_t plli2sq = 0U;
|
|
8004208: 2300 movs r3, #0
|
|
800420a: 61bb str r3, [r7, #24]
|
|
uint32_t plli2sr = 0U;
|
|
800420c: 2300 movs r3, #0
|
|
800420e: 617b str r3, [r7, #20]
|
|
uint32_t pllsaip = 0U;
|
|
8004210: 2300 movs r3, #0
|
|
8004212: 613b str r3, [r7, #16]
|
|
uint32_t pllsaiq = 0U;
|
|
8004214: 2300 movs r3, #0
|
|
8004216: 60fb str r3, [r7, #12]
|
|
uint32_t plli2sused = 0U;
|
|
8004218: 2300 movs r3, #0
|
|
800421a: 62fb str r3, [r7, #44] @ 0x2c
|
|
uint32_t pllsaiused = 0U;
|
|
800421c: 2300 movs r3, #0
|
|
800421e: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Check the peripheral clock selection parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*------------------------ I2S APB1 configuration --------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
|
|
8004220: 687b ldr r3, [r7, #4]
|
|
8004222: 681b ldr r3, [r3, #0]
|
|
8004224: f003 0301 and.w r3, r3, #1
|
|
8004228: 2b00 cmp r3, #0
|
|
800422a: d010 beq.n 800424e <HAL_RCCEx_PeriphCLKConfig+0x5a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
|
|
|
|
/* Configure I2S Clock source */
|
|
__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
|
|
800422c: 4b6f ldr r3, [pc, #444] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800422e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8004232: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000
|
|
8004236: 687b ldr r3, [r7, #4]
|
|
8004238: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800423a: 496c ldr r1, [pc, #432] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800423c: 4313 orrs r3, r2
|
|
800423e: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for I2S */
|
|
if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
|
|
8004242: 687b ldr r3, [r7, #4]
|
|
8004244: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004246: 2b00 cmp r3, #0
|
|
8004248: d101 bne.n 800424e <HAL_RCCEx_PeriphCLKConfig+0x5a>
|
|
{
|
|
plli2sused = 1U;
|
|
800424a: 2301 movs r3, #1
|
|
800424c: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- I2S APB2 configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
|
|
800424e: 687b ldr r3, [r7, #4]
|
|
8004250: 681b ldr r3, [r3, #0]
|
|
8004252: f003 0302 and.w r3, r3, #2
|
|
8004256: 2b00 cmp r3, #0
|
|
8004258: d010 beq.n 800427c <HAL_RCCEx_PeriphCLKConfig+0x88>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
|
|
|
|
/* Configure I2S Clock source */
|
|
__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
|
|
800425a: 4b64 ldr r3, [pc, #400] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800425c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8004260: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000
|
|
8004264: 687b ldr r3, [r7, #4]
|
|
8004266: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8004268: 4960 ldr r1, [pc, #384] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800426a: 4313 orrs r3, r2
|
|
800426c: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for I2S */
|
|
if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
|
|
8004270: 687b ldr r3, [r7, #4]
|
|
8004272: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8004274: 2b00 cmp r3, #0
|
|
8004276: d101 bne.n 800427c <HAL_RCCEx_PeriphCLKConfig+0x88>
|
|
{
|
|
plli2sused = 1U;
|
|
8004278: 2301 movs r3, #1
|
|
800427a: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*--------------------------- SAI1 configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
|
|
800427c: 687b ldr r3, [r7, #4]
|
|
800427e: 681b ldr r3, [r3, #0]
|
|
8004280: f003 0304 and.w r3, r3, #4
|
|
8004284: 2b00 cmp r3, #0
|
|
8004286: d017 beq.n 80042b8 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
/* Configure SAI1 Clock source */
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
8004288: 4b58 ldr r3, [pc, #352] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800428a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
800428e: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
8004292: 687b ldr r3, [r7, #4]
|
|
8004294: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8004296: 4955 ldr r1, [pc, #340] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004298: 4313 orrs r3, r2
|
|
800429a: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
|
|
800429e: 687b ldr r3, [r7, #4]
|
|
80042a0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80042a2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
80042a6: d101 bne.n 80042ac <HAL_RCCEx_PeriphCLKConfig+0xb8>
|
|
{
|
|
plli2sused = 1U;
|
|
80042a8: 2301 movs r3, #1
|
|
80042aa: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
/* Enable the PLLSAI when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
|
|
80042ac: 687b ldr r3, [r7, #4]
|
|
80042ae: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80042b0: 2b00 cmp r3, #0
|
|
80042b2: d101 bne.n 80042b8 <HAL_RCCEx_PeriphCLKConfig+0xc4>
|
|
{
|
|
pllsaiused = 1U;
|
|
80042b4: 2301 movs r3, #1
|
|
80042b6: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*-------------------------- SAI2 configuration ----------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
|
|
80042b8: 687b ldr r3, [r7, #4]
|
|
80042ba: 681b ldr r3, [r3, #0]
|
|
80042bc: f003 0308 and.w r3, r3, #8
|
|
80042c0: 2b00 cmp r3, #0
|
|
80042c2: d017 beq.n 80042f4 <HAL_RCCEx_PeriphCLKConfig+0x100>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
|
|
|
|
/* Configure SAI2 Clock source */
|
|
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
|
|
80042c4: 4b49 ldr r3, [pc, #292] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80042c6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80042ca: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
80042ce: 687b ldr r3, [r7, #4]
|
|
80042d0: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80042d2: 4946 ldr r1, [pc, #280] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80042d4: 4313 orrs r3, r2
|
|
80042d6: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
|
|
/* Enable the PLLI2S when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
|
|
80042da: 687b ldr r3, [r7, #4]
|
|
80042dc: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80042de: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80042e2: d101 bne.n 80042e8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
{
|
|
plli2sused = 1U;
|
|
80042e4: 2301 movs r3, #1
|
|
80042e6: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
/* Enable the PLLSAI when it's used as clock source for SAI */
|
|
if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
|
|
80042e8: 687b ldr r3, [r7, #4]
|
|
80042ea: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80042ec: 2b00 cmp r3, #0
|
|
80042ee: d101 bne.n 80042f4 <HAL_RCCEx_PeriphCLKConfig+0x100>
|
|
{
|
|
pllsaiused = 1U;
|
|
80042f0: 2301 movs r3, #1
|
|
80042f2: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- RTC configuration --------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
|
80042f4: 687b ldr r3, [r7, #4]
|
|
80042f6: 681b ldr r3, [r3, #0]
|
|
80042f8: f003 0320 and.w r3, r3, #32
|
|
80042fc: 2b00 cmp r3, #0
|
|
80042fe: f000 808a beq.w 8004416 <HAL_RCCEx_PeriphCLKConfig+0x222>
|
|
{
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8004302: 2300 movs r3, #0
|
|
8004304: 60bb str r3, [r7, #8]
|
|
8004306: 4b39 ldr r3, [pc, #228] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004308: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800430a: 4a38 ldr r2, [pc, #224] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800430c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8004310: 6413 str r3, [r2, #64] @ 0x40
|
|
8004312: 4b36 ldr r3, [pc, #216] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004314: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004316: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800431a: 60bb str r3, [r7, #8]
|
|
800431c: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Enable write access to Backup domain */
|
|
PWR->CR |= PWR_CR_DBP;
|
|
800431e: 4b34 ldr r3, [pc, #208] @ (80043f0 <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
8004320: 681b ldr r3, [r3, #0]
|
|
8004322: 4a33 ldr r2, [pc, #204] @ (80043f0 <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
8004324: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8004328: 6013 str r3, [r2, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800432a: f7fd fb75 bl 8001a18 <HAL_GetTick>
|
|
800432e: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
8004330: e008 b.n 8004344 <HAL_RCCEx_PeriphCLKConfig+0x150>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8004332: f7fd fb71 bl 8001a18 <HAL_GetTick>
|
|
8004336: 4602 mov r2, r0
|
|
8004338: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800433a: 1ad3 subs r3, r2, r3
|
|
800433c: 2b02 cmp r3, #2
|
|
800433e: d901 bls.n 8004344 <HAL_RCCEx_PeriphCLKConfig+0x150>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004340: 2303 movs r3, #3
|
|
8004342: e278 b.n 8004836 <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
8004344: 4b2a ldr r3, [pc, #168] @ (80043f0 <HAL_RCCEx_PeriphCLKConfig+0x1fc>)
|
|
8004346: 681b ldr r3, [r3, #0]
|
|
8004348: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800434c: 2b00 cmp r3, #0
|
|
800434e: d0f0 beq.n 8004332 <HAL_RCCEx_PeriphCLKConfig+0x13e>
|
|
}
|
|
}
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
8004350: 4b26 ldr r3, [pc, #152] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004352: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004354: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8004358: 623b str r3, [r7, #32]
|
|
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
800435a: 6a3b ldr r3, [r7, #32]
|
|
800435c: 2b00 cmp r3, #0
|
|
800435e: d02f beq.n 80043c0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
8004360: 687b ldr r3, [r7, #4]
|
|
8004362: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004364: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8004368: 6a3a ldr r2, [r7, #32]
|
|
800436a: 429a cmp r2, r3
|
|
800436c: d028 beq.n 80043c0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
800436e: 4b1f ldr r3, [pc, #124] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004370: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004372: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004376: 623b str r3, [r7, #32]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8004378: 4b1e ldr r3, [pc, #120] @ (80043f4 <HAL_RCCEx_PeriphCLKConfig+0x200>)
|
|
800437a: 2201 movs r2, #1
|
|
800437c: 601a str r2, [r3, #0]
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
800437e: 4b1d ldr r3, [pc, #116] @ (80043f4 <HAL_RCCEx_PeriphCLKConfig+0x200>)
|
|
8004380: 2200 movs r2, #0
|
|
8004382: 601a str r2, [r3, #0]
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpreg1;
|
|
8004384: 4a19 ldr r2, [pc, #100] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
8004386: 6a3b ldr r3, [r7, #32]
|
|
8004388: 6713 str r3, [r2, #112] @ 0x70
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
|
|
800438a: 4b18 ldr r3, [pc, #96] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
800438c: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800438e: f003 0301 and.w r3, r3, #1
|
|
8004392: 2b01 cmp r3, #1
|
|
8004394: d114 bne.n 80043c0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8004396: f7fd fb3f bl 8001a18 <HAL_GetTick>
|
|
800439a: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
800439c: e00a b.n 80043b4 <HAL_RCCEx_PeriphCLKConfig+0x1c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800439e: f7fd fb3b bl 8001a18 <HAL_GetTick>
|
|
80043a2: 4602 mov r2, r0
|
|
80043a4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80043a6: 1ad3 subs r3, r2, r3
|
|
80043a8: f241 3288 movw r2, #5000 @ 0x1388
|
|
80043ac: 4293 cmp r3, r2
|
|
80043ae: d901 bls.n 80043b4 <HAL_RCCEx_PeriphCLKConfig+0x1c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80043b0: 2303 movs r3, #3
|
|
80043b2: e240 b.n 8004836 <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
80043b4: 4b0d ldr r3, [pc, #52] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80043b6: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80043b8: f003 0302 and.w r3, r3, #2
|
|
80043bc: 2b00 cmp r3, #0
|
|
80043be: d0ee beq.n 800439e <HAL_RCCEx_PeriphCLKConfig+0x1aa>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
80043c0: 687b ldr r3, [r7, #4]
|
|
80043c2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80043c4: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80043c8: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
80043cc: d114 bne.n 80043f8 <HAL_RCCEx_PeriphCLKConfig+0x204>
|
|
80043ce: 4b07 ldr r3, [pc, #28] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80043d0: 689b ldr r3, [r3, #8]
|
|
80043d2: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
|
|
80043d6: 687b ldr r3, [r7, #4]
|
|
80043d8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80043da: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000
|
|
80043de: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80043e2: 4902 ldr r1, [pc, #8] @ (80043ec <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80043e4: 4313 orrs r3, r2
|
|
80043e6: 608b str r3, [r1, #8]
|
|
80043e8: e00c b.n 8004404 <HAL_RCCEx_PeriphCLKConfig+0x210>
|
|
80043ea: bf00 nop
|
|
80043ec: 40023800 .word 0x40023800
|
|
80043f0: 40007000 .word 0x40007000
|
|
80043f4: 42470e40 .word 0x42470e40
|
|
80043f8: 4b4a ldr r3, [pc, #296] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80043fa: 689b ldr r3, [r3, #8]
|
|
80043fc: 4a49 ldr r2, [pc, #292] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80043fe: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
|
|
8004402: 6093 str r3, [r2, #8]
|
|
8004404: 4b47 ldr r3, [pc, #284] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8004406: 6f1a ldr r2, [r3, #112] @ 0x70
|
|
8004408: 687b ldr r3, [r7, #4]
|
|
800440a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800440c: f3c3 030b ubfx r3, r3, #0, #12
|
|
8004410: 4944 ldr r1, [pc, #272] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8004412: 4313 orrs r3, r2
|
|
8004414: 670b str r3, [r1, #112] @ 0x70
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- TIM configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
|
|
8004416: 687b ldr r3, [r7, #4]
|
|
8004418: 681b ldr r3, [r3, #0]
|
|
800441a: f003 0310 and.w r3, r3, #16
|
|
800441e: 2b00 cmp r3, #0
|
|
8004420: d004 beq.n 800442c <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
{
|
|
/* Configure Timer Prescaler */
|
|
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
|
|
8004422: 687b ldr r3, [r7, #4]
|
|
8004424: f893 2058 ldrb.w r2, [r3, #88] @ 0x58
|
|
8004428: 4b3f ldr r3, [pc, #252] @ (8004528 <HAL_RCCEx_PeriphCLKConfig+0x334>)
|
|
800442a: 601a str r2, [r3, #0]
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- FMPI2C1 Configuration -----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
|
|
800442c: 687b ldr r3, [r7, #4]
|
|
800442e: 681b ldr r3, [r3, #0]
|
|
8004430: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8004434: 2b00 cmp r3, #0
|
|
8004436: d00a beq.n 800444e <HAL_RCCEx_PeriphCLKConfig+0x25a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
|
|
|
|
/* Configure the FMPI2C1 clock source */
|
|
__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
|
|
8004438: 4b3a ldr r3, [pc, #232] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
800443a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800443e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
8004442: 687b ldr r3, [r7, #4]
|
|
8004444: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8004446: 4937 ldr r1, [pc, #220] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
8004448: 4313 orrs r3, r2
|
|
800444a: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*------------------------------ CEC Configuration -------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
|
|
800444e: 687b ldr r3, [r7, #4]
|
|
8004450: 681b ldr r3, [r3, #0]
|
|
8004452: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8004456: 2b00 cmp r3, #0
|
|
8004458: d00a beq.n 8004470 <HAL_RCCEx_PeriphCLKConfig+0x27c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
|
|
|
|
/* Configure the CEC clock source */
|
|
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
|
|
800445a: 4b32 ldr r3, [pc, #200] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
800445c: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8004460: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000
|
|
8004464: 687b ldr r3, [r7, #4]
|
|
8004466: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8004468: 492e ldr r1, [pc, #184] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
800446a: 4313 orrs r3, r2
|
|
800446c: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- CLK48 Configuration ------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
|
|
8004470: 687b ldr r3, [r7, #4]
|
|
8004472: 681b ldr r3, [r3, #0]
|
|
8004474: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004478: 2b00 cmp r3, #0
|
|
800447a: d011 beq.n 80044a0 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
|
|
|
|
/* Configure the CLK48 clock source */
|
|
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
|
|
800447c: 4b29 ldr r3, [pc, #164] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
800447e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8004482: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000
|
|
8004486: 687b ldr r3, [r7, #4]
|
|
8004488: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800448a: 4926 ldr r1, [pc, #152] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
800448c: 4313 orrs r3, r2
|
|
800448e: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
|
|
/* Enable the PLLSAI when it's used as clock source for CLK48 */
|
|
if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
|
|
8004492: 687b ldr r3, [r7, #4]
|
|
8004494: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8004496: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
800449a: d101 bne.n 80044a0 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
pllsaiused = 1U;
|
|
800449c: 2301 movs r3, #1
|
|
800449e: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- SDIO Configuration -------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
|
|
80044a0: 687b ldr r3, [r7, #4]
|
|
80044a2: 681b ldr r3, [r3, #0]
|
|
80044a4: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80044a8: 2b00 cmp r3, #0
|
|
80044aa: d00a beq.n 80044c2 <HAL_RCCEx_PeriphCLKConfig+0x2ce>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
|
|
|
|
/* Configure the SDIO clock source */
|
|
__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
|
|
80044ac: 4b1d ldr r3, [pc, #116] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80044ae: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
80044b2: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
|
|
80044b6: 687b ldr r3, [r7, #4]
|
|
80044b8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80044ba: 491a ldr r1, [pc, #104] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80044bc: 4313 orrs r3, r2
|
|
80044be: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*------------------------------ SPDIFRX Configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
|
80044c2: 687b ldr r3, [r7, #4]
|
|
80044c4: 681b ldr r3, [r3, #0]
|
|
80044c6: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80044ca: 2b00 cmp r3, #0
|
|
80044cc: d011 beq.n 80044f2 <HAL_RCCEx_PeriphCLKConfig+0x2fe>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
|
|
|
|
/* Configure the SPDIFRX clock source */
|
|
__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
|
|
80044ce: 4b15 ldr r3, [pc, #84] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80044d0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
80044d4: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
|
|
80044d8: 687b ldr r3, [r7, #4]
|
|
80044da: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80044dc: 4911 ldr r1, [pc, #68] @ (8004524 <HAL_RCCEx_PeriphCLKConfig+0x330>)
|
|
80044de: 4313 orrs r3, r2
|
|
80044e0: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
|
|
if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
|
|
80044e4: 687b ldr r3, [r7, #4]
|
|
80044e6: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80044e8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
80044ec: d101 bne.n 80044f2 <HAL_RCCEx_PeriphCLKConfig+0x2fe>
|
|
{
|
|
plli2sused = 1U;
|
|
80044ee: 2301 movs r3, #1
|
|
80044f0: 62fb str r3, [r7, #44] @ 0x2c
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- PLLI2S Configuration ------------------------*/
|
|
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
|
|
I2S on APB2 or SPDIFRX */
|
|
if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
|
|
80044f2: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80044f4: 2b01 cmp r3, #1
|
|
80044f6: d005 beq.n 8004504 <HAL_RCCEx_PeriphCLKConfig+0x310>
|
|
80044f8: 687b ldr r3, [r7, #4]
|
|
80044fa: 681b ldr r3, [r3, #0]
|
|
80044fc: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8004500: f040 80ff bne.w 8004702 <HAL_RCCEx_PeriphCLKConfig+0x50e>
|
|
{
|
|
/* Disable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_DISABLE();
|
|
8004504: 4b09 ldr r3, [pc, #36] @ (800452c <HAL_RCCEx_PeriphCLKConfig+0x338>)
|
|
8004506: 2200 movs r2, #0
|
|
8004508: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800450a: f7fd fa85 bl 8001a18 <HAL_GetTick>
|
|
800450e: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLI2S is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
8004510: e00e b.n 8004530 <HAL_RCCEx_PeriphCLKConfig+0x33c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
8004512: f7fd fa81 bl 8001a18 <HAL_GetTick>
|
|
8004516: 4602 mov r2, r0
|
|
8004518: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800451a: 1ad3 subs r3, r2, r3
|
|
800451c: 2b02 cmp r3, #2
|
|
800451e: d907 bls.n 8004530 <HAL_RCCEx_PeriphCLKConfig+0x33c>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8004520: 2303 movs r3, #3
|
|
8004522: e188 b.n 8004836 <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
8004524: 40023800 .word 0x40023800
|
|
8004528: 424711e0 .word 0x424711e0
|
|
800452c: 42470068 .word 0x42470068
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
8004530: 4b7e ldr r3, [pc, #504] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004532: 681b ldr r3, [r3, #0]
|
|
8004534: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8004538: 2b00 cmp r3, #0
|
|
800453a: d1ea bne.n 8004512 <HAL_RCCEx_PeriphCLKConfig+0x31e>
|
|
/* check for common PLLI2S Parameters */
|
|
assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
|
|
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
|
|
|
/*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1)
|
|
800453c: 687b ldr r3, [r7, #4]
|
|
800453e: 681b ldr r3, [r3, #0]
|
|
8004540: f003 0301 and.w r3, r3, #1
|
|
8004544: 2b00 cmp r3, #0
|
|
8004546: d003 beq.n 8004550 <HAL_RCCEx_PeriphCLKConfig+0x35c>
|
|
&& (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
|
|
8004548: 687b ldr r3, [r7, #4]
|
|
800454a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800454c: 2b00 cmp r3, #0
|
|
800454e: d009 beq.n 8004564 <HAL_RCCEx_PeriphCLKConfig+0x370>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
|
|
8004550: 687b ldr r3, [r7, #4]
|
|
8004552: 681b ldr r3, [r3, #0]
|
|
8004554: f003 0302 and.w r3, r3, #2
|
|
&& (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
|
|
8004558: 2b00 cmp r3, #0
|
|
800455a: d028 beq.n 80045ae <HAL_RCCEx_PeriphCLKConfig+0x3ba>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
|
|
800455c: 687b ldr r3, [r7, #4]
|
|
800455e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8004560: 2b00 cmp r3, #0
|
|
8004562: d124 bne.n 80045ae <HAL_RCCEx_PeriphCLKConfig+0x3ba>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
|
|
/* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
|
|
plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
8004564: 4b71 ldr r3, [pc, #452] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004566: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
800456a: 0c1b lsrs r3, r3, #16
|
|
800456c: f003 0303 and.w r3, r3, #3
|
|
8004570: 3301 adds r3, #1
|
|
8004572: 005b lsls r3, r3, #1
|
|
8004574: 61fb str r3, [r7, #28]
|
|
plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
|
|
8004576: 4b6d ldr r3, [pc, #436] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004578: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
800457c: 0e1b lsrs r3, r3, #24
|
|
800457e: f003 030f and.w r3, r3, #15
|
|
8004582: 61bb str r3, [r7, #24]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq,
|
|
8004584: 687b ldr r3, [r7, #4]
|
|
8004586: 685a ldr r2, [r3, #4]
|
|
8004588: 687b ldr r3, [r7, #4]
|
|
800458a: 689b ldr r3, [r3, #8]
|
|
800458c: 019b lsls r3, r3, #6
|
|
800458e: 431a orrs r2, r3
|
|
8004590: 69fb ldr r3, [r7, #28]
|
|
8004592: 085b lsrs r3, r3, #1
|
|
8004594: 3b01 subs r3, #1
|
|
8004596: 041b lsls r3, r3, #16
|
|
8004598: 431a orrs r2, r3
|
|
800459a: 69bb ldr r3, [r7, #24]
|
|
800459c: 061b lsls r3, r3, #24
|
|
800459e: 431a orrs r2, r3
|
|
80045a0: 687b ldr r3, [r7, #4]
|
|
80045a2: 695b ldr r3, [r3, #20]
|
|
80045a4: 071b lsls r3, r3, #28
|
|
80045a6: 4961 ldr r1, [pc, #388] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80045a8: 4313 orrs r3, r2
|
|
80045aa: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SR);
|
|
}
|
|
|
|
/*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
|
|
80045ae: 687b ldr r3, [r7, #4]
|
|
80045b0: 681b ldr r3, [r3, #0]
|
|
80045b2: f003 0304 and.w r3, r3, #4
|
|
80045b6: 2b00 cmp r3, #0
|
|
80045b8: d004 beq.n 80045c4 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
|
80045ba: 687b ldr r3, [r7, #4]
|
|
80045bc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80045be: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
80045c2: d00a beq.n 80045da <HAL_RCCEx_PeriphCLKConfig+0x3e6>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
|
80045c4: 687b ldr r3, [r7, #4]
|
|
80045c6: 681b ldr r3, [r3, #0]
|
|
80045c8: f003 0308 and.w r3, r3, #8
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
|
80045cc: 2b00 cmp r3, #0
|
|
80045ce: d035 beq.n 800463c <HAL_RCCEx_PeriphCLKConfig+0x448>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
|
80045d0: 687b ldr r3, [r7, #4]
|
|
80045d2: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80045d4: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80045d8: d130 bne.n 800463c <HAL_RCCEx_PeriphCLKConfig+0x448>
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
/* Check for PLLI2S/DIVQ parameters */
|
|
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
|
|
|
|
/* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
|
|
plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
80045da: 4b54 ldr r3, [pc, #336] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80045dc: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80045e0: 0c1b lsrs r3, r3, #16
|
|
80045e2: f003 0303 and.w r3, r3, #3
|
|
80045e6: 3301 adds r3, #1
|
|
80045e8: 005b lsls r3, r3, #1
|
|
80045ea: 61fb str r3, [r7, #28]
|
|
plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
80045ec: 4b4f ldr r3, [pc, #316] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80045ee: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80045f2: 0f1b lsrs r3, r3, #28
|
|
80045f4: f003 0307 and.w r3, r3, #7
|
|
80045f8: 617b str r3, [r7, #20]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
|
|
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
|
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp,
|
|
80045fa: 687b ldr r3, [r7, #4]
|
|
80045fc: 685a ldr r2, [r3, #4]
|
|
80045fe: 687b ldr r3, [r7, #4]
|
|
8004600: 689b ldr r3, [r3, #8]
|
|
8004602: 019b lsls r3, r3, #6
|
|
8004604: 431a orrs r2, r3
|
|
8004606: 69fb ldr r3, [r7, #28]
|
|
8004608: 085b lsrs r3, r3, #1
|
|
800460a: 3b01 subs r3, #1
|
|
800460c: 041b lsls r3, r3, #16
|
|
800460e: 431a orrs r2, r3
|
|
8004610: 687b ldr r3, [r7, #4]
|
|
8004612: 691b ldr r3, [r3, #16]
|
|
8004614: 061b lsls r3, r3, #24
|
|
8004616: 431a orrs r2, r3
|
|
8004618: 697b ldr r3, [r7, #20]
|
|
800461a: 071b lsls r3, r3, #28
|
|
800461c: 4943 ldr r1, [pc, #268] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
800461e: 4313 orrs r3, r2
|
|
8004620: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
|
|
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
|
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
|
|
8004624: 4b41 ldr r3, [pc, #260] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004626: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
800462a: f023 021f bic.w r2, r3, #31
|
|
800462e: 687b ldr r3, [r7, #4]
|
|
8004630: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8004632: 3b01 subs r3, #1
|
|
8004634: 493d ldr r1, [pc, #244] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004636: 4313 orrs r3, r2
|
|
8004638: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
|
800463c: 687b ldr r3, [r7, #4]
|
|
800463e: 681b ldr r3, [r3, #0]
|
|
8004640: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8004644: 2b00 cmp r3, #0
|
|
8004646: d029 beq.n 800469c <HAL_RCCEx_PeriphCLKConfig+0x4a8>
|
|
&& (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
|
|
8004648: 687b ldr r3, [r7, #4]
|
|
800464a: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
800464c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8004650: d124 bne.n 800469c <HAL_RCCEx_PeriphCLKConfig+0x4a8>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
|
|
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
|
plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
|
|
8004652: 4b36 ldr r3, [pc, #216] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004654: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8004658: 0c1b lsrs r3, r3, #16
|
|
800465a: f003 0303 and.w r3, r3, #3
|
|
800465e: 3301 adds r3, #1
|
|
8004660: 005b lsls r3, r3, #1
|
|
8004662: 61bb str r3, [r7, #24]
|
|
plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
8004664: 4b31 ldr r3, [pc, #196] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004666: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
800466a: 0f1b lsrs r3, r3, #28
|
|
800466c: f003 0307 and.w r3, r3, #7
|
|
8004670: 617b str r3, [r7, #20]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP,
|
|
8004672: 687b ldr r3, [r7, #4]
|
|
8004674: 685a ldr r2, [r3, #4]
|
|
8004676: 687b ldr r3, [r7, #4]
|
|
8004678: 689b ldr r3, [r3, #8]
|
|
800467a: 019b lsls r3, r3, #6
|
|
800467c: 431a orrs r2, r3
|
|
800467e: 687b ldr r3, [r7, #4]
|
|
8004680: 68db ldr r3, [r3, #12]
|
|
8004682: 085b lsrs r3, r3, #1
|
|
8004684: 3b01 subs r3, #1
|
|
8004686: 041b lsls r3, r3, #16
|
|
8004688: 431a orrs r2, r3
|
|
800468a: 69bb ldr r3, [r7, #24]
|
|
800468c: 061b lsls r3, r3, #24
|
|
800468e: 431a orrs r2, r3
|
|
8004690: 697b ldr r3, [r7, #20]
|
|
8004692: 071b lsls r3, r3, #28
|
|
8004694: 4925 ldr r1, [pc, #148] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
8004696: 4313 orrs r3, r2
|
|
8004698: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
plli2sq, plli2sr);
|
|
}
|
|
|
|
/*----------------- In Case of PLLI2S is just selected -----------------*/
|
|
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
|
|
800469c: 687b ldr r3, [r7, #4]
|
|
800469e: 681b ldr r3, [r3, #0]
|
|
80046a0: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80046a4: 2b00 cmp r3, #0
|
|
80046a6: d016 beq.n 80046d6 <HAL_RCCEx_PeriphCLKConfig+0x4e2>
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP,
|
|
80046a8: 687b ldr r3, [r7, #4]
|
|
80046aa: 685a ldr r2, [r3, #4]
|
|
80046ac: 687b ldr r3, [r7, #4]
|
|
80046ae: 689b ldr r3, [r3, #8]
|
|
80046b0: 019b lsls r3, r3, #6
|
|
80046b2: 431a orrs r2, r3
|
|
80046b4: 687b ldr r3, [r7, #4]
|
|
80046b6: 68db ldr r3, [r3, #12]
|
|
80046b8: 085b lsrs r3, r3, #1
|
|
80046ba: 3b01 subs r3, #1
|
|
80046bc: 041b lsls r3, r3, #16
|
|
80046be: 431a orrs r2, r3
|
|
80046c0: 687b ldr r3, [r7, #4]
|
|
80046c2: 691b ldr r3, [r3, #16]
|
|
80046c4: 061b lsls r3, r3, #24
|
|
80046c6: 431a orrs r2, r3
|
|
80046c8: 687b ldr r3, [r7, #4]
|
|
80046ca: 695b ldr r3, [r3, #20]
|
|
80046cc: 071b lsls r3, r3, #28
|
|
80046ce: 4917 ldr r1, [pc, #92] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80046d0: 4313 orrs r3, r2
|
|
80046d2: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
|
|
}
|
|
|
|
/* Enable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_ENABLE();
|
|
80046d6: 4b16 ldr r3, [pc, #88] @ (8004730 <HAL_RCCEx_PeriphCLKConfig+0x53c>)
|
|
80046d8: 2201 movs r2, #1
|
|
80046da: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80046dc: f7fd f99c bl 8001a18 <HAL_GetTick>
|
|
80046e0: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLI2S is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
80046e2: e008 b.n 80046f6 <HAL_RCCEx_PeriphCLKConfig+0x502>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
80046e4: f7fd f998 bl 8001a18 <HAL_GetTick>
|
|
80046e8: 4602 mov r2, r0
|
|
80046ea: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80046ec: 1ad3 subs r3, r2, r3
|
|
80046ee: 2b02 cmp r3, #2
|
|
80046f0: d901 bls.n 80046f6 <HAL_RCCEx_PeriphCLKConfig+0x502>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
80046f2: 2303 movs r3, #3
|
|
80046f4: e09f b.n 8004836 <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
80046f6: 4b0d ldr r3, [pc, #52] @ (800472c <HAL_RCCEx_PeriphCLKConfig+0x538>)
|
|
80046f8: 681b ldr r3, [r3, #0]
|
|
80046fa: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
80046fe: 2b00 cmp r3, #0
|
|
8004700: d0f0 beq.n 80046e4 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*----------------------------- PLLSAI Configuration -----------------------*/
|
|
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
|
|
if (pllsaiused == 1U)
|
|
8004702: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8004704: 2b01 cmp r3, #1
|
|
8004706: f040 8095 bne.w 8004834 <HAL_RCCEx_PeriphCLKConfig+0x640>
|
|
{
|
|
/* Disable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_DISABLE();
|
|
800470a: 4b0a ldr r3, [pc, #40] @ (8004734 <HAL_RCCEx_PeriphCLKConfig+0x540>)
|
|
800470c: 2200 movs r2, #0
|
|
800470e: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8004710: f7fd f982 bl 8001a18 <HAL_GetTick>
|
|
8004714: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLSAI is disabled */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
8004716: e00f b.n 8004738 <HAL_RCCEx_PeriphCLKConfig+0x544>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
8004718: f7fd f97e bl 8001a18 <HAL_GetTick>
|
|
800471c: 4602 mov r2, r0
|
|
800471e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004720: 1ad3 subs r3, r2, r3
|
|
8004722: 2b02 cmp r3, #2
|
|
8004724: d908 bls.n 8004738 <HAL_RCCEx_PeriphCLKConfig+0x544>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8004726: 2303 movs r3, #3
|
|
8004728: e085 b.n 8004836 <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
800472a: bf00 nop
|
|
800472c: 40023800 .word 0x40023800
|
|
8004730: 42470068 .word 0x42470068
|
|
8004734: 42470070 .word 0x42470070
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
8004738: 4b41 ldr r3, [pc, #260] @ (8004840 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
800473a: 681b ldr r3, [r3, #0]
|
|
800473c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8004740: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8004744: d0e8 beq.n 8004718 <HAL_RCCEx_PeriphCLKConfig+0x524>
|
|
/* Check the PLLSAI division factors */
|
|
assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
|
|
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
|
|
|
|
/*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
|
|
if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
|
|
8004746: 687b ldr r3, [r7, #4]
|
|
8004748: 681b ldr r3, [r3, #0]
|
|
800474a: f003 0304 and.w r3, r3, #4
|
|
800474e: 2b00 cmp r3, #0
|
|
8004750: d003 beq.n 800475a <HAL_RCCEx_PeriphCLKConfig+0x566>
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
|
|
8004752: 687b ldr r3, [r7, #4]
|
|
8004754: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8004756: 2b00 cmp r3, #0
|
|
8004758: d009 beq.n 800476e <HAL_RCCEx_PeriphCLKConfig+0x57a>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
|
800475a: 687b ldr r3, [r7, #4]
|
|
800475c: 681b ldr r3, [r3, #0]
|
|
800475e: f003 0308 and.w r3, r3, #8
|
|
&& (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
|
|
8004762: 2b00 cmp r3, #0
|
|
8004764: d02b beq.n 80047be <HAL_RCCEx_PeriphCLKConfig+0x5ca>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
|
8004766: 687b ldr r3, [r7, #4]
|
|
8004768: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800476a: 2b00 cmp r3, #0
|
|
800476c: d127 bne.n 80047be <HAL_RCCEx_PeriphCLKConfig+0x5ca>
|
|
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
|
|
/* check for PLLSAI/DIVQ Parameter */
|
|
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
|
|
|
|
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
|
|
pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
|
|
800476e: 4b34 ldr r3, [pc, #208] @ (8004840 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8004770: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004774: 0c1b lsrs r3, r3, #16
|
|
8004776: f003 0303 and.w r3, r3, #3
|
|
800477a: 3301 adds r3, #1
|
|
800477c: 005b lsls r3, r3, #1
|
|
800477e: 613b str r3, [r7, #16]
|
|
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
|
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip,
|
|
8004780: 687b ldr r3, [r7, #4]
|
|
8004782: 699a ldr r2, [r3, #24]
|
|
8004784: 687b ldr r3, [r7, #4]
|
|
8004786: 69db ldr r3, [r3, #28]
|
|
8004788: 019b lsls r3, r3, #6
|
|
800478a: 431a orrs r2, r3
|
|
800478c: 693b ldr r3, [r7, #16]
|
|
800478e: 085b lsrs r3, r3, #1
|
|
8004790: 3b01 subs r3, #1
|
|
8004792: 041b lsls r3, r3, #16
|
|
8004794: 431a orrs r2, r3
|
|
8004796: 687b ldr r3, [r7, #4]
|
|
8004798: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800479a: 061b lsls r3, r3, #24
|
|
800479c: 4928 ldr r1, [pc, #160] @ (8004840 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
800479e: 4313 orrs r3, r2
|
|
80047a0: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
|
|
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
|
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
|
|
80047a4: 4b26 ldr r3, [pc, #152] @ (8004840 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
80047a6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80047aa: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
|
|
80047ae: 687b ldr r3, [r7, #4]
|
|
80047b0: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80047b2: 3b01 subs r3, #1
|
|
80047b4: 021b lsls r3, r3, #8
|
|
80047b6: 4922 ldr r1, [pc, #136] @ (8004840 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
80047b8: 4313 orrs r3, r2
|
|
80047ba: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/
|
|
/* In Case of PLLI2S is selected as source clock for CLK48 */
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
|
|
80047be: 687b ldr r3, [r7, #4]
|
|
80047c0: 681b ldr r3, [r3, #0]
|
|
80047c2: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80047c6: 2b00 cmp r3, #0
|
|
80047c8: d01d beq.n 8004806 <HAL_RCCEx_PeriphCLKConfig+0x612>
|
|
&& (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
|
|
80047ca: 687b ldr r3, [r7, #4]
|
|
80047cc: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80047ce: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
80047d2: d118 bne.n 8004806 <HAL_RCCEx_PeriphCLKConfig+0x612>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
|
|
/* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
|
pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
|
|
80047d4: 4b1a ldr r3, [pc, #104] @ (8004840 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
80047d6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80047da: 0e1b lsrs r3, r3, #24
|
|
80047dc: f003 030f and.w r3, r3, #15
|
|
80047e0: 60fb str r3, [r7, #12]
|
|
/* Configure the PLLSAI division factors */
|
|
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
|
|
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP,
|
|
80047e2: 687b ldr r3, [r7, #4]
|
|
80047e4: 699a ldr r2, [r3, #24]
|
|
80047e6: 687b ldr r3, [r7, #4]
|
|
80047e8: 69db ldr r3, [r3, #28]
|
|
80047ea: 019b lsls r3, r3, #6
|
|
80047ec: 431a orrs r2, r3
|
|
80047ee: 687b ldr r3, [r7, #4]
|
|
80047f0: 6a1b ldr r3, [r3, #32]
|
|
80047f2: 085b lsrs r3, r3, #1
|
|
80047f4: 3b01 subs r3, #1
|
|
80047f6: 041b lsls r3, r3, #16
|
|
80047f8: 431a orrs r2, r3
|
|
80047fa: 68fb ldr r3, [r7, #12]
|
|
80047fc: 061b lsls r3, r3, #24
|
|
80047fe: 4910 ldr r1, [pc, #64] @ (8004840 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8004800: 4313 orrs r3, r2
|
|
8004802: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
pllsaiq, 0U);
|
|
}
|
|
|
|
/* Enable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_ENABLE();
|
|
8004806: 4b0f ldr r3, [pc, #60] @ (8004844 <HAL_RCCEx_PeriphCLKConfig+0x650>)
|
|
8004808: 2201 movs r2, #1
|
|
800480a: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800480c: f7fd f904 bl 8001a18 <HAL_GetTick>
|
|
8004810: 6278 str r0, [r7, #36] @ 0x24
|
|
/* Wait till PLLSAI is ready */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
8004812: e008 b.n 8004826 <HAL_RCCEx_PeriphCLKConfig+0x632>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
8004814: f7fd f900 bl 8001a18 <HAL_GetTick>
|
|
8004818: 4602 mov r2, r0
|
|
800481a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800481c: 1ad3 subs r3, r2, r3
|
|
800481e: 2b02 cmp r3, #2
|
|
8004820: d901 bls.n 8004826 <HAL_RCCEx_PeriphCLKConfig+0x632>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8004822: 2303 movs r3, #3
|
|
8004824: e007 b.n 8004836 <HAL_RCCEx_PeriphCLKConfig+0x642>
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
8004826: 4b06 ldr r3, [pc, #24] @ (8004840 <HAL_RCCEx_PeriphCLKConfig+0x64c>)
|
|
8004828: 681b ldr r3, [r3, #0]
|
|
800482a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
800482e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8004832: d1ef bne.n 8004814 <HAL_RCCEx_PeriphCLKConfig+0x620>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8004834: 2300 movs r3, #0
|
|
}
|
|
8004836: 4618 mov r0, r3
|
|
8004838: 3730 adds r7, #48 @ 0x30
|
|
800483a: 46bd mov sp, r7
|
|
800483c: bd80 pop {r7, pc}
|
|
800483e: bf00 nop
|
|
8004840: 40023800 .word 0x40023800
|
|
8004844: 42470070 .word 0x42470070
|
|
|
|
08004848 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8004848: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
800484c: b0ae sub sp, #184 @ 0xb8
|
|
800484e: af00 add r7, sp, #0
|
|
uint32_t pllm = 0U;
|
|
8004850: 2300 movs r3, #0
|
|
8004852: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
uint32_t pllvco = 0U;
|
|
8004856: 2300 movs r3, #0
|
|
8004858: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
uint32_t pllp = 0U;
|
|
800485c: 2300 movs r3, #0
|
|
800485e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
uint32_t pllr = 0U;
|
|
8004862: 2300 movs r3, #0
|
|
8004864: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
uint32_t sysclockfreq = 0U;
|
|
8004868: 2300 movs r3, #0
|
|
800486a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
800486e: 4bcb ldr r3, [pc, #812] @ (8004b9c <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004870: 689b ldr r3, [r3, #8]
|
|
8004872: f003 030c and.w r3, r3, #12
|
|
8004876: 2b0c cmp r3, #12
|
|
8004878: f200 8206 bhi.w 8004c88 <HAL_RCC_GetSysClockFreq+0x440>
|
|
800487c: a201 add r2, pc, #4 @ (adr r2, 8004884 <HAL_RCC_GetSysClockFreq+0x3c>)
|
|
800487e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8004882: bf00 nop
|
|
8004884: 080048b9 .word 0x080048b9
|
|
8004888: 08004c89 .word 0x08004c89
|
|
800488c: 08004c89 .word 0x08004c89
|
|
8004890: 08004c89 .word 0x08004c89
|
|
8004894: 080048c1 .word 0x080048c1
|
|
8004898: 08004c89 .word 0x08004c89
|
|
800489c: 08004c89 .word 0x08004c89
|
|
80048a0: 08004c89 .word 0x08004c89
|
|
80048a4: 080048c9 .word 0x080048c9
|
|
80048a8: 08004c89 .word 0x08004c89
|
|
80048ac: 08004c89 .word 0x08004c89
|
|
80048b0: 08004c89 .word 0x08004c89
|
|
80048b4: 08004ab9 .word 0x08004ab9
|
|
{
|
|
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
80048b8: 4bb9 ldr r3, [pc, #740] @ (8004ba0 <HAL_RCC_GetSysClockFreq+0x358>)
|
|
80048ba: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
80048be: e1e7 b.n 8004c90 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
80048c0: 4bb8 ldr r3, [pc, #736] @ (8004ba4 <HAL_RCC_GetSysClockFreq+0x35c>)
|
|
80048c2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
80048c6: e1e3 b.n 8004c90 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLP */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
80048c8: 4bb4 ldr r3, [pc, #720] @ (8004b9c <HAL_RCC_GetSysClockFreq+0x354>)
|
|
80048ca: 685b ldr r3, [r3, #4]
|
|
80048cc: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
80048d0: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
80048d4: 4bb1 ldr r3, [pc, #708] @ (8004b9c <HAL_RCC_GetSysClockFreq+0x354>)
|
|
80048d6: 685b ldr r3, [r3, #4]
|
|
80048d8: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80048dc: 2b00 cmp r3, #0
|
|
80048de: d071 beq.n 80049c4 <HAL_RCC_GetSysClockFreq+0x17c>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
80048e0: 4bae ldr r3, [pc, #696] @ (8004b9c <HAL_RCC_GetSysClockFreq+0x354>)
|
|
80048e2: 685b ldr r3, [r3, #4]
|
|
80048e4: 099b lsrs r3, r3, #6
|
|
80048e6: 2200 movs r2, #0
|
|
80048e8: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
80048ec: f8c7 209c str.w r2, [r7, #156] @ 0x9c
|
|
80048f0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
80048f4: f3c3 0308 ubfx r3, r3, #0, #9
|
|
80048f8: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
80048fc: 2300 movs r3, #0
|
|
80048fe: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
8004902: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
|
|
8004906: 4622 mov r2, r4
|
|
8004908: 462b mov r3, r5
|
|
800490a: f04f 0000 mov.w r0, #0
|
|
800490e: f04f 0100 mov.w r1, #0
|
|
8004912: 0159 lsls r1, r3, #5
|
|
8004914: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8004918: 0150 lsls r0, r2, #5
|
|
800491a: 4602 mov r2, r0
|
|
800491c: 460b mov r3, r1
|
|
800491e: 4621 mov r1, r4
|
|
8004920: 1a51 subs r1, r2, r1
|
|
8004922: 6439 str r1, [r7, #64] @ 0x40
|
|
8004924: 4629 mov r1, r5
|
|
8004926: eb63 0301 sbc.w r3, r3, r1
|
|
800492a: 647b str r3, [r7, #68] @ 0x44
|
|
800492c: f04f 0200 mov.w r2, #0
|
|
8004930: f04f 0300 mov.w r3, #0
|
|
8004934: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40
|
|
8004938: 4649 mov r1, r9
|
|
800493a: 018b lsls r3, r1, #6
|
|
800493c: 4641 mov r1, r8
|
|
800493e: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8004942: 4641 mov r1, r8
|
|
8004944: 018a lsls r2, r1, #6
|
|
8004946: 4641 mov r1, r8
|
|
8004948: 1a51 subs r1, r2, r1
|
|
800494a: 63b9 str r1, [r7, #56] @ 0x38
|
|
800494c: 4649 mov r1, r9
|
|
800494e: eb63 0301 sbc.w r3, r3, r1
|
|
8004952: 63fb str r3, [r7, #60] @ 0x3c
|
|
8004954: f04f 0200 mov.w r2, #0
|
|
8004958: f04f 0300 mov.w r3, #0
|
|
800495c: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38
|
|
8004960: 4649 mov r1, r9
|
|
8004962: 00cb lsls r3, r1, #3
|
|
8004964: 4641 mov r1, r8
|
|
8004966: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
800496a: 4641 mov r1, r8
|
|
800496c: 00ca lsls r2, r1, #3
|
|
800496e: 4610 mov r0, r2
|
|
8004970: 4619 mov r1, r3
|
|
8004972: 4603 mov r3, r0
|
|
8004974: 4622 mov r2, r4
|
|
8004976: 189b adds r3, r3, r2
|
|
8004978: 633b str r3, [r7, #48] @ 0x30
|
|
800497a: 462b mov r3, r5
|
|
800497c: 460a mov r2, r1
|
|
800497e: eb42 0303 adc.w r3, r2, r3
|
|
8004982: 637b str r3, [r7, #52] @ 0x34
|
|
8004984: f04f 0200 mov.w r2, #0
|
|
8004988: f04f 0300 mov.w r3, #0
|
|
800498c: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30
|
|
8004990: 4629 mov r1, r5
|
|
8004992: 024b lsls r3, r1, #9
|
|
8004994: 4621 mov r1, r4
|
|
8004996: ea43 53d1 orr.w r3, r3, r1, lsr #23
|
|
800499a: 4621 mov r1, r4
|
|
800499c: 024a lsls r2, r1, #9
|
|
800499e: 4610 mov r0, r2
|
|
80049a0: 4619 mov r1, r3
|
|
80049a2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80049a6: 2200 movs r2, #0
|
|
80049a8: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
80049ac: f8c7 208c str.w r2, [r7, #140] @ 0x8c
|
|
80049b0: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88
|
|
80049b4: f7fb fc26 bl 8000204 <__aeabi_uldivmod>
|
|
80049b8: 4602 mov r2, r0
|
|
80049ba: 460b mov r3, r1
|
|
80049bc: 4613 mov r3, r2
|
|
80049be: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
80049c2: e067 b.n 8004a94 <HAL_RCC_GetSysClockFreq+0x24c>
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
80049c4: 4b75 ldr r3, [pc, #468] @ (8004b9c <HAL_RCC_GetSysClockFreq+0x354>)
|
|
80049c6: 685b ldr r3, [r3, #4]
|
|
80049c8: 099b lsrs r3, r3, #6
|
|
80049ca: 2200 movs r2, #0
|
|
80049cc: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
80049d0: f8c7 2084 str.w r2, [r7, #132] @ 0x84
|
|
80049d4: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
80049d8: f3c3 0308 ubfx r3, r3, #0, #9
|
|
80049dc: 67bb str r3, [r7, #120] @ 0x78
|
|
80049de: 2300 movs r3, #0
|
|
80049e0: 67fb str r3, [r7, #124] @ 0x7c
|
|
80049e2: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78
|
|
80049e6: 4622 mov r2, r4
|
|
80049e8: 462b mov r3, r5
|
|
80049ea: f04f 0000 mov.w r0, #0
|
|
80049ee: f04f 0100 mov.w r1, #0
|
|
80049f2: 0159 lsls r1, r3, #5
|
|
80049f4: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
80049f8: 0150 lsls r0, r2, #5
|
|
80049fa: 4602 mov r2, r0
|
|
80049fc: 460b mov r3, r1
|
|
80049fe: 4621 mov r1, r4
|
|
8004a00: 1a51 subs r1, r2, r1
|
|
8004a02: 62b9 str r1, [r7, #40] @ 0x28
|
|
8004a04: 4629 mov r1, r5
|
|
8004a06: eb63 0301 sbc.w r3, r3, r1
|
|
8004a0a: 62fb str r3, [r7, #44] @ 0x2c
|
|
8004a0c: f04f 0200 mov.w r2, #0
|
|
8004a10: f04f 0300 mov.w r3, #0
|
|
8004a14: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28
|
|
8004a18: 4649 mov r1, r9
|
|
8004a1a: 018b lsls r3, r1, #6
|
|
8004a1c: 4641 mov r1, r8
|
|
8004a1e: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8004a22: 4641 mov r1, r8
|
|
8004a24: 018a lsls r2, r1, #6
|
|
8004a26: 4641 mov r1, r8
|
|
8004a28: ebb2 0a01 subs.w sl, r2, r1
|
|
8004a2c: 4649 mov r1, r9
|
|
8004a2e: eb63 0b01 sbc.w fp, r3, r1
|
|
8004a32: f04f 0200 mov.w r2, #0
|
|
8004a36: f04f 0300 mov.w r3, #0
|
|
8004a3a: ea4f 03cb mov.w r3, fp, lsl #3
|
|
8004a3e: ea43 735a orr.w r3, r3, sl, lsr #29
|
|
8004a42: ea4f 02ca mov.w r2, sl, lsl #3
|
|
8004a46: 4692 mov sl, r2
|
|
8004a48: 469b mov fp, r3
|
|
8004a4a: 4623 mov r3, r4
|
|
8004a4c: eb1a 0303 adds.w r3, sl, r3
|
|
8004a50: 623b str r3, [r7, #32]
|
|
8004a52: 462b mov r3, r5
|
|
8004a54: eb4b 0303 adc.w r3, fp, r3
|
|
8004a58: 627b str r3, [r7, #36] @ 0x24
|
|
8004a5a: f04f 0200 mov.w r2, #0
|
|
8004a5e: f04f 0300 mov.w r3, #0
|
|
8004a62: e9d7 4508 ldrd r4, r5, [r7, #32]
|
|
8004a66: 4629 mov r1, r5
|
|
8004a68: 028b lsls r3, r1, #10
|
|
8004a6a: 4621 mov r1, r4
|
|
8004a6c: ea43 5391 orr.w r3, r3, r1, lsr #22
|
|
8004a70: 4621 mov r1, r4
|
|
8004a72: 028a lsls r2, r1, #10
|
|
8004a74: 4610 mov r0, r2
|
|
8004a76: 4619 mov r1, r3
|
|
8004a78: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8004a7c: 2200 movs r2, #0
|
|
8004a7e: 673b str r3, [r7, #112] @ 0x70
|
|
8004a80: 677a str r2, [r7, #116] @ 0x74
|
|
8004a82: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70
|
|
8004a86: f7fb fbbd bl 8000204 <__aeabi_uldivmod>
|
|
8004a8a: 4602 mov r2, r0
|
|
8004a8c: 460b mov r3, r1
|
|
8004a8e: 4613 mov r3, r2
|
|
8004a90: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
}
|
|
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
|
|
8004a94: 4b41 ldr r3, [pc, #260] @ (8004b9c <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004a96: 685b ldr r3, [r3, #4]
|
|
8004a98: 0c1b lsrs r3, r3, #16
|
|
8004a9a: f003 0303 and.w r3, r3, #3
|
|
8004a9e: 3301 adds r3, #1
|
|
8004aa0: 005b lsls r3, r3, #1
|
|
8004aa2: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
|
|
sysclockfreq = pllvco / pllp;
|
|
8004aa6: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
8004aaa: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8004aae: fbb2 f3f3 udiv r3, r2, r3
|
|
8004ab2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8004ab6: e0eb b.n 8004c90 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLR */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
8004ab8: 4b38 ldr r3, [pc, #224] @ (8004b9c <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004aba: 685b ldr r3, [r3, #4]
|
|
8004abc: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
8004ac0: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
8004ac4: 4b35 ldr r3, [pc, #212] @ (8004b9c <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004ac6: 685b ldr r3, [r3, #4]
|
|
8004ac8: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004acc: 2b00 cmp r3, #0
|
|
8004ace: d06b beq.n 8004ba8 <HAL_RCC_GetSysClockFreq+0x360>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8004ad0: 4b32 ldr r3, [pc, #200] @ (8004b9c <HAL_RCC_GetSysClockFreq+0x354>)
|
|
8004ad2: 685b ldr r3, [r3, #4]
|
|
8004ad4: 099b lsrs r3, r3, #6
|
|
8004ad6: 2200 movs r2, #0
|
|
8004ad8: 66bb str r3, [r7, #104] @ 0x68
|
|
8004ada: 66fa str r2, [r7, #108] @ 0x6c
|
|
8004adc: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8004ade: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8004ae2: 663b str r3, [r7, #96] @ 0x60
|
|
8004ae4: 2300 movs r3, #0
|
|
8004ae6: 667b str r3, [r7, #100] @ 0x64
|
|
8004ae8: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60
|
|
8004aec: 4622 mov r2, r4
|
|
8004aee: 462b mov r3, r5
|
|
8004af0: f04f 0000 mov.w r0, #0
|
|
8004af4: f04f 0100 mov.w r1, #0
|
|
8004af8: 0159 lsls r1, r3, #5
|
|
8004afa: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8004afe: 0150 lsls r0, r2, #5
|
|
8004b00: 4602 mov r2, r0
|
|
8004b02: 460b mov r3, r1
|
|
8004b04: 4621 mov r1, r4
|
|
8004b06: 1a51 subs r1, r2, r1
|
|
8004b08: 61b9 str r1, [r7, #24]
|
|
8004b0a: 4629 mov r1, r5
|
|
8004b0c: eb63 0301 sbc.w r3, r3, r1
|
|
8004b10: 61fb str r3, [r7, #28]
|
|
8004b12: f04f 0200 mov.w r2, #0
|
|
8004b16: f04f 0300 mov.w r3, #0
|
|
8004b1a: e9d7 ab06 ldrd sl, fp, [r7, #24]
|
|
8004b1e: 4659 mov r1, fp
|
|
8004b20: 018b lsls r3, r1, #6
|
|
8004b22: 4651 mov r1, sl
|
|
8004b24: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8004b28: 4651 mov r1, sl
|
|
8004b2a: 018a lsls r2, r1, #6
|
|
8004b2c: 4651 mov r1, sl
|
|
8004b2e: ebb2 0801 subs.w r8, r2, r1
|
|
8004b32: 4659 mov r1, fp
|
|
8004b34: eb63 0901 sbc.w r9, r3, r1
|
|
8004b38: f04f 0200 mov.w r2, #0
|
|
8004b3c: f04f 0300 mov.w r3, #0
|
|
8004b40: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8004b44: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8004b48: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
8004b4c: 4690 mov r8, r2
|
|
8004b4e: 4699 mov r9, r3
|
|
8004b50: 4623 mov r3, r4
|
|
8004b52: eb18 0303 adds.w r3, r8, r3
|
|
8004b56: 613b str r3, [r7, #16]
|
|
8004b58: 462b mov r3, r5
|
|
8004b5a: eb49 0303 adc.w r3, r9, r3
|
|
8004b5e: 617b str r3, [r7, #20]
|
|
8004b60: f04f 0200 mov.w r2, #0
|
|
8004b64: f04f 0300 mov.w r3, #0
|
|
8004b68: e9d7 4504 ldrd r4, r5, [r7, #16]
|
|
8004b6c: 4629 mov r1, r5
|
|
8004b6e: 024b lsls r3, r1, #9
|
|
8004b70: 4621 mov r1, r4
|
|
8004b72: ea43 53d1 orr.w r3, r3, r1, lsr #23
|
|
8004b76: 4621 mov r1, r4
|
|
8004b78: 024a lsls r2, r1, #9
|
|
8004b7a: 4610 mov r0, r2
|
|
8004b7c: 4619 mov r1, r3
|
|
8004b7e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8004b82: 2200 movs r2, #0
|
|
8004b84: 65bb str r3, [r7, #88] @ 0x58
|
|
8004b86: 65fa str r2, [r7, #92] @ 0x5c
|
|
8004b88: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
|
|
8004b8c: f7fb fb3a bl 8000204 <__aeabi_uldivmod>
|
|
8004b90: 4602 mov r2, r0
|
|
8004b92: 460b mov r3, r1
|
|
8004b94: 4613 mov r3, r2
|
|
8004b96: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8004b9a: e065 b.n 8004c68 <HAL_RCC_GetSysClockFreq+0x420>
|
|
8004b9c: 40023800 .word 0x40023800
|
|
8004ba0: 00f42400 .word 0x00f42400
|
|
8004ba4: 007a1200 .word 0x007a1200
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8004ba8: 4b3d ldr r3, [pc, #244] @ (8004ca0 <HAL_RCC_GetSysClockFreq+0x458>)
|
|
8004baa: 685b ldr r3, [r3, #4]
|
|
8004bac: 099b lsrs r3, r3, #6
|
|
8004bae: 2200 movs r2, #0
|
|
8004bb0: 4618 mov r0, r3
|
|
8004bb2: 4611 mov r1, r2
|
|
8004bb4: f3c0 0308 ubfx r3, r0, #0, #9
|
|
8004bb8: 653b str r3, [r7, #80] @ 0x50
|
|
8004bba: 2300 movs r3, #0
|
|
8004bbc: 657b str r3, [r7, #84] @ 0x54
|
|
8004bbe: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50
|
|
8004bc2: 4642 mov r2, r8
|
|
8004bc4: 464b mov r3, r9
|
|
8004bc6: f04f 0000 mov.w r0, #0
|
|
8004bca: f04f 0100 mov.w r1, #0
|
|
8004bce: 0159 lsls r1, r3, #5
|
|
8004bd0: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8004bd4: 0150 lsls r0, r2, #5
|
|
8004bd6: 4602 mov r2, r0
|
|
8004bd8: 460b mov r3, r1
|
|
8004bda: 4641 mov r1, r8
|
|
8004bdc: 1a51 subs r1, r2, r1
|
|
8004bde: 60b9 str r1, [r7, #8]
|
|
8004be0: 4649 mov r1, r9
|
|
8004be2: eb63 0301 sbc.w r3, r3, r1
|
|
8004be6: 60fb str r3, [r7, #12]
|
|
8004be8: f04f 0200 mov.w r2, #0
|
|
8004bec: f04f 0300 mov.w r3, #0
|
|
8004bf0: e9d7 ab02 ldrd sl, fp, [r7, #8]
|
|
8004bf4: 4659 mov r1, fp
|
|
8004bf6: 018b lsls r3, r1, #6
|
|
8004bf8: 4651 mov r1, sl
|
|
8004bfa: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8004bfe: 4651 mov r1, sl
|
|
8004c00: 018a lsls r2, r1, #6
|
|
8004c02: 4651 mov r1, sl
|
|
8004c04: 1a54 subs r4, r2, r1
|
|
8004c06: 4659 mov r1, fp
|
|
8004c08: eb63 0501 sbc.w r5, r3, r1
|
|
8004c0c: f04f 0200 mov.w r2, #0
|
|
8004c10: f04f 0300 mov.w r3, #0
|
|
8004c14: 00eb lsls r3, r5, #3
|
|
8004c16: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
8004c1a: 00e2 lsls r2, r4, #3
|
|
8004c1c: 4614 mov r4, r2
|
|
8004c1e: 461d mov r5, r3
|
|
8004c20: 4643 mov r3, r8
|
|
8004c22: 18e3 adds r3, r4, r3
|
|
8004c24: 603b str r3, [r7, #0]
|
|
8004c26: 464b mov r3, r9
|
|
8004c28: eb45 0303 adc.w r3, r5, r3
|
|
8004c2c: 607b str r3, [r7, #4]
|
|
8004c2e: f04f 0200 mov.w r2, #0
|
|
8004c32: f04f 0300 mov.w r3, #0
|
|
8004c36: e9d7 4500 ldrd r4, r5, [r7]
|
|
8004c3a: 4629 mov r1, r5
|
|
8004c3c: 028b lsls r3, r1, #10
|
|
8004c3e: 4621 mov r1, r4
|
|
8004c40: ea43 5391 orr.w r3, r3, r1, lsr #22
|
|
8004c44: 4621 mov r1, r4
|
|
8004c46: 028a lsls r2, r1, #10
|
|
8004c48: 4610 mov r0, r2
|
|
8004c4a: 4619 mov r1, r3
|
|
8004c4c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8004c50: 2200 movs r2, #0
|
|
8004c52: 64bb str r3, [r7, #72] @ 0x48
|
|
8004c54: 64fa str r2, [r7, #76] @ 0x4c
|
|
8004c56: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
|
|
8004c5a: f7fb fad3 bl 8000204 <__aeabi_uldivmod>
|
|
8004c5e: 4602 mov r2, r0
|
|
8004c60: 460b mov r3, r1
|
|
8004c62: 4613 mov r3, r2
|
|
8004c64: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
}
|
|
pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
|
|
8004c68: 4b0d ldr r3, [pc, #52] @ (8004ca0 <HAL_RCC_GetSysClockFreq+0x458>)
|
|
8004c6a: 685b ldr r3, [r3, #4]
|
|
8004c6c: 0f1b lsrs r3, r3, #28
|
|
8004c6e: f003 0307 and.w r3, r3, #7
|
|
8004c72: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
|
|
sysclockfreq = pllvco / pllr;
|
|
8004c76: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
8004c7a: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
8004c7e: fbb2 f3f3 udiv r3, r2, r3
|
|
8004c82: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8004c86: e003 b.n 8004c90 <HAL_RCC_GetSysClockFreq+0x448>
|
|
}
|
|
default:
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8004c88: 4b06 ldr r3, [pc, #24] @ (8004ca4 <HAL_RCC_GetSysClockFreq+0x45c>)
|
|
8004c8a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
break;
|
|
8004c8e: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8004c90: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
|
|
}
|
|
8004c94: 4618 mov r0, r3
|
|
8004c96: 37b8 adds r7, #184 @ 0xb8
|
|
8004c98: 46bd mov sp, r7
|
|
8004c9a: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8004c9e: bf00 nop
|
|
8004ca0: 40023800 .word 0x40023800
|
|
8004ca4: 00f42400 .word 0x00f42400
|
|
|
|
08004ca8 <HAL_RCC_OscConfig>:
|
|
* @note This function add the PLL/PLLR factor management during PLL configuration this feature
|
|
* is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8004ca8: b580 push {r7, lr}
|
|
8004caa: b086 sub sp, #24
|
|
8004cac: af00 add r7, sp, #0
|
|
8004cae: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8004cb0: 687b ldr r3, [r7, #4]
|
|
8004cb2: 2b00 cmp r3, #0
|
|
8004cb4: d101 bne.n 8004cba <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004cb6: 2301 movs r3, #1
|
|
8004cb8: e28d b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8004cba: 687b ldr r3, [r7, #4]
|
|
8004cbc: 681b ldr r3, [r3, #0]
|
|
8004cbe: f003 0301 and.w r3, r3, #1
|
|
8004cc2: 2b00 cmp r3, #0
|
|
8004cc4: f000 8083 beq.w 8004dce <HAL_RCC_OscConfig+0x126>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
|
|
#if defined(STM32F446xx)
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
8004cc8: 4b94 ldr r3, [pc, #592] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004cca: 689b ldr r3, [r3, #8]
|
|
8004ccc: f003 030c and.w r3, r3, #12
|
|
8004cd0: 2b04 cmp r3, #4
|
|
8004cd2: d019 beq.n 8004d08 <HAL_RCC_OscConfig+0x60>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
8004cd4: 4b91 ldr r3, [pc, #580] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004cd6: 689b ldr r3, [r3, #8]
|
|
8004cd8: f003 030c and.w r3, r3, #12
|
|
|| \
|
|
8004cdc: 2b08 cmp r3, #8
|
|
8004cde: d106 bne.n 8004cee <HAL_RCC_OscConfig+0x46>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
8004ce0: 4b8e ldr r3, [pc, #568] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004ce2: 685b ldr r3, [r3, #4]
|
|
8004ce4: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004ce8: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
8004cec: d00c beq.n 8004d08 <HAL_RCC_OscConfig+0x60>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
8004cee: 4b8b ldr r3, [pc, #556] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004cf0: 689b ldr r3, [r3, #8]
|
|
8004cf2: f003 030c and.w r3, r3, #12
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \
|
|
8004cf6: 2b0c cmp r3, #12
|
|
8004cf8: d112 bne.n 8004d20 <HAL_RCC_OscConfig+0x78>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
8004cfa: 4b88 ldr r3, [pc, #544] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004cfc: 685b ldr r3, [r3, #4]
|
|
8004cfe: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004d02: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
8004d06: d10b bne.n 8004d20 <HAL_RCC_OscConfig+0x78>
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
#endif /* STM32F446xx */
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8004d08: 4b84 ldr r3, [pc, #528] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004d0a: 681b ldr r3, [r3, #0]
|
|
8004d0c: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004d10: 2b00 cmp r3, #0
|
|
8004d12: d05b beq.n 8004dcc <HAL_RCC_OscConfig+0x124>
|
|
8004d14: 687b ldr r3, [r7, #4]
|
|
8004d16: 685b ldr r3, [r3, #4]
|
|
8004d18: 2b00 cmp r3, #0
|
|
8004d1a: d157 bne.n 8004dcc <HAL_RCC_OscConfig+0x124>
|
|
{
|
|
return HAL_ERROR;
|
|
8004d1c: 2301 movs r3, #1
|
|
8004d1e: e25a b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8004d20: 687b ldr r3, [r7, #4]
|
|
8004d22: 685b ldr r3, [r3, #4]
|
|
8004d24: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8004d28: d106 bne.n 8004d38 <HAL_RCC_OscConfig+0x90>
|
|
8004d2a: 4b7c ldr r3, [pc, #496] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004d2c: 681b ldr r3, [r3, #0]
|
|
8004d2e: 4a7b ldr r2, [pc, #492] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004d30: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004d34: 6013 str r3, [r2, #0]
|
|
8004d36: e01d b.n 8004d74 <HAL_RCC_OscConfig+0xcc>
|
|
8004d38: 687b ldr r3, [r7, #4]
|
|
8004d3a: 685b ldr r3, [r3, #4]
|
|
8004d3c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8004d40: d10c bne.n 8004d5c <HAL_RCC_OscConfig+0xb4>
|
|
8004d42: 4b76 ldr r3, [pc, #472] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004d44: 681b ldr r3, [r3, #0]
|
|
8004d46: 4a75 ldr r2, [pc, #468] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004d48: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8004d4c: 6013 str r3, [r2, #0]
|
|
8004d4e: 4b73 ldr r3, [pc, #460] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004d50: 681b ldr r3, [r3, #0]
|
|
8004d52: 4a72 ldr r2, [pc, #456] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004d54: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004d58: 6013 str r3, [r2, #0]
|
|
8004d5a: e00b b.n 8004d74 <HAL_RCC_OscConfig+0xcc>
|
|
8004d5c: 4b6f ldr r3, [pc, #444] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004d5e: 681b ldr r3, [r3, #0]
|
|
8004d60: 4a6e ldr r2, [pc, #440] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004d62: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8004d66: 6013 str r3, [r2, #0]
|
|
8004d68: 4b6c ldr r3, [pc, #432] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004d6a: 681b ldr r3, [r3, #0]
|
|
8004d6c: 4a6b ldr r2, [pc, #428] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004d6e: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8004d72: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
|
|
8004d74: 687b ldr r3, [r7, #4]
|
|
8004d76: 685b ldr r3, [r3, #4]
|
|
8004d78: 2b00 cmp r3, #0
|
|
8004d7a: d013 beq.n 8004da4 <HAL_RCC_OscConfig+0xfc>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004d7c: f7fc fe4c bl 8001a18 <HAL_GetTick>
|
|
8004d80: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8004d82: e008 b.n 8004d96 <HAL_RCC_OscConfig+0xee>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8004d84: f7fc fe48 bl 8001a18 <HAL_GetTick>
|
|
8004d88: 4602 mov r2, r0
|
|
8004d8a: 693b ldr r3, [r7, #16]
|
|
8004d8c: 1ad3 subs r3, r2, r3
|
|
8004d8e: 2b64 cmp r3, #100 @ 0x64
|
|
8004d90: d901 bls.n 8004d96 <HAL_RCC_OscConfig+0xee>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004d92: 2303 movs r3, #3
|
|
8004d94: e21f b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8004d96: 4b61 ldr r3, [pc, #388] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004d98: 681b ldr r3, [r3, #0]
|
|
8004d9a: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004d9e: 2b00 cmp r3, #0
|
|
8004da0: d0f0 beq.n 8004d84 <HAL_RCC_OscConfig+0xdc>
|
|
8004da2: e014 b.n 8004dce <HAL_RCC_OscConfig+0x126>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004da4: f7fc fe38 bl 8001a18 <HAL_GetTick>
|
|
8004da8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is bypassed or disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8004daa: e008 b.n 8004dbe <HAL_RCC_OscConfig+0x116>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8004dac: f7fc fe34 bl 8001a18 <HAL_GetTick>
|
|
8004db0: 4602 mov r2, r0
|
|
8004db2: 693b ldr r3, [r7, #16]
|
|
8004db4: 1ad3 subs r3, r2, r3
|
|
8004db6: 2b64 cmp r3, #100 @ 0x64
|
|
8004db8: d901 bls.n 8004dbe <HAL_RCC_OscConfig+0x116>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004dba: 2303 movs r3, #3
|
|
8004dbc: e20b b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8004dbe: 4b57 ldr r3, [pc, #348] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004dc0: 681b ldr r3, [r3, #0]
|
|
8004dc2: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004dc6: 2b00 cmp r3, #0
|
|
8004dc8: d1f0 bne.n 8004dac <HAL_RCC_OscConfig+0x104>
|
|
8004dca: e000 b.n 8004dce <HAL_RCC_OscConfig+0x126>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8004dcc: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8004dce: 687b ldr r3, [r7, #4]
|
|
8004dd0: 681b ldr r3, [r3, #0]
|
|
8004dd2: f003 0302 and.w r3, r3, #2
|
|
8004dd6: 2b00 cmp r3, #0
|
|
8004dd8: d06f beq.n 8004eba <HAL_RCC_OscConfig+0x212>
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
#if defined(STM32F446xx)
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
|
|
8004dda: 4b50 ldr r3, [pc, #320] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004ddc: 689b ldr r3, [r3, #8]
|
|
8004dde: f003 030c and.w r3, r3, #12
|
|
8004de2: 2b00 cmp r3, #0
|
|
8004de4: d017 beq.n 8004e16 <HAL_RCC_OscConfig+0x16e>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
8004de6: 4b4d ldr r3, [pc, #308] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004de8: 689b ldr r3, [r3, #8]
|
|
8004dea: f003 030c and.w r3, r3, #12
|
|
|| \
|
|
8004dee: 2b08 cmp r3, #8
|
|
8004df0: d105 bne.n 8004dfe <HAL_RCC_OscConfig+0x156>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
8004df2: 4b4a ldr r3, [pc, #296] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004df4: 685b ldr r3, [r3, #4]
|
|
8004df6: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004dfa: 2b00 cmp r3, #0
|
|
8004dfc: d00b beq.n 8004e16 <HAL_RCC_OscConfig+0x16e>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
8004dfe: 4b47 ldr r3, [pc, #284] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004e00: 689b ldr r3, [r3, #8]
|
|
8004e02: f003 030c and.w r3, r3, #12
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \
|
|
8004e06: 2b0c cmp r3, #12
|
|
8004e08: d11c bne.n 8004e44 <HAL_RCC_OscConfig+0x19c>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
8004e0a: 4b44 ldr r3, [pc, #272] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004e0c: 685b ldr r3, [r3, #4]
|
|
8004e0e: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004e12: 2b00 cmp r3, #0
|
|
8004e14: d116 bne.n 8004e44 <HAL_RCC_OscConfig+0x19c>
|
|
|| \
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
#endif /* STM32F446xx */
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8004e16: 4b41 ldr r3, [pc, #260] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004e18: 681b ldr r3, [r3, #0]
|
|
8004e1a: f003 0302 and.w r3, r3, #2
|
|
8004e1e: 2b00 cmp r3, #0
|
|
8004e20: d005 beq.n 8004e2e <HAL_RCC_OscConfig+0x186>
|
|
8004e22: 687b ldr r3, [r7, #4]
|
|
8004e24: 68db ldr r3, [r3, #12]
|
|
8004e26: 2b01 cmp r3, #1
|
|
8004e28: d001 beq.n 8004e2e <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
return HAL_ERROR;
|
|
8004e2a: 2301 movs r3, #1
|
|
8004e2c: e1d3 b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8004e2e: 4b3b ldr r3, [pc, #236] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004e30: 681b ldr r3, [r3, #0]
|
|
8004e32: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8004e36: 687b ldr r3, [r7, #4]
|
|
8004e38: 691b ldr r3, [r3, #16]
|
|
8004e3a: 00db lsls r3, r3, #3
|
|
8004e3c: 4937 ldr r1, [pc, #220] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004e3e: 4313 orrs r3, r2
|
|
8004e40: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8004e42: e03a b.n 8004eba <HAL_RCC_OscConfig+0x212>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
|
|
8004e44: 687b ldr r3, [r7, #4]
|
|
8004e46: 68db ldr r3, [r3, #12]
|
|
8004e48: 2b00 cmp r3, #0
|
|
8004e4a: d020 beq.n 8004e8e <HAL_RCC_OscConfig+0x1e6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8004e4c: 4b34 ldr r3, [pc, #208] @ (8004f20 <HAL_RCC_OscConfig+0x278>)
|
|
8004e4e: 2201 movs r2, #1
|
|
8004e50: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004e52: f7fc fde1 bl 8001a18 <HAL_GetTick>
|
|
8004e56: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004e58: e008 b.n 8004e6c <HAL_RCC_OscConfig+0x1c4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8004e5a: f7fc fddd bl 8001a18 <HAL_GetTick>
|
|
8004e5e: 4602 mov r2, r0
|
|
8004e60: 693b ldr r3, [r7, #16]
|
|
8004e62: 1ad3 subs r3, r2, r3
|
|
8004e64: 2b02 cmp r3, #2
|
|
8004e66: d901 bls.n 8004e6c <HAL_RCC_OscConfig+0x1c4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004e68: 2303 movs r3, #3
|
|
8004e6a: e1b4 b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004e6c: 4b2b ldr r3, [pc, #172] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004e6e: 681b ldr r3, [r3, #0]
|
|
8004e70: f003 0302 and.w r3, r3, #2
|
|
8004e74: 2b00 cmp r3, #0
|
|
8004e76: d0f0 beq.n 8004e5a <HAL_RCC_OscConfig+0x1b2>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8004e78: 4b28 ldr r3, [pc, #160] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004e7a: 681b ldr r3, [r3, #0]
|
|
8004e7c: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8004e80: 687b ldr r3, [r7, #4]
|
|
8004e82: 691b ldr r3, [r3, #16]
|
|
8004e84: 00db lsls r3, r3, #3
|
|
8004e86: 4925 ldr r1, [pc, #148] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004e88: 4313 orrs r3, r2
|
|
8004e8a: 600b str r3, [r1, #0]
|
|
8004e8c: e015 b.n 8004eba <HAL_RCC_OscConfig+0x212>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8004e8e: 4b24 ldr r3, [pc, #144] @ (8004f20 <HAL_RCC_OscConfig+0x278>)
|
|
8004e90: 2200 movs r2, #0
|
|
8004e92: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004e94: f7fc fdc0 bl 8001a18 <HAL_GetTick>
|
|
8004e98: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8004e9a: e008 b.n 8004eae <HAL_RCC_OscConfig+0x206>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8004e9c: f7fc fdbc bl 8001a18 <HAL_GetTick>
|
|
8004ea0: 4602 mov r2, r0
|
|
8004ea2: 693b ldr r3, [r7, #16]
|
|
8004ea4: 1ad3 subs r3, r2, r3
|
|
8004ea6: 2b02 cmp r3, #2
|
|
8004ea8: d901 bls.n 8004eae <HAL_RCC_OscConfig+0x206>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004eaa: 2303 movs r3, #3
|
|
8004eac: e193 b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8004eae: 4b1b ldr r3, [pc, #108] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004eb0: 681b ldr r3, [r3, #0]
|
|
8004eb2: f003 0302 and.w r3, r3, #2
|
|
8004eb6: 2b00 cmp r3, #0
|
|
8004eb8: d1f0 bne.n 8004e9c <HAL_RCC_OscConfig+0x1f4>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8004eba: 687b ldr r3, [r7, #4]
|
|
8004ebc: 681b ldr r3, [r3, #0]
|
|
8004ebe: f003 0308 and.w r3, r3, #8
|
|
8004ec2: 2b00 cmp r3, #0
|
|
8004ec4: d036 beq.n 8004f34 <HAL_RCC_OscConfig+0x28c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
|
|
8004ec6: 687b ldr r3, [r7, #4]
|
|
8004ec8: 695b ldr r3, [r3, #20]
|
|
8004eca: 2b00 cmp r3, #0
|
|
8004ecc: d016 beq.n 8004efc <HAL_RCC_OscConfig+0x254>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8004ece: 4b15 ldr r3, [pc, #84] @ (8004f24 <HAL_RCC_OscConfig+0x27c>)
|
|
8004ed0: 2201 movs r2, #1
|
|
8004ed2: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004ed4: f7fc fda0 bl 8001a18 <HAL_GetTick>
|
|
8004ed8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8004eda: e008 b.n 8004eee <HAL_RCC_OscConfig+0x246>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8004edc: f7fc fd9c bl 8001a18 <HAL_GetTick>
|
|
8004ee0: 4602 mov r2, r0
|
|
8004ee2: 693b ldr r3, [r7, #16]
|
|
8004ee4: 1ad3 subs r3, r2, r3
|
|
8004ee6: 2b02 cmp r3, #2
|
|
8004ee8: d901 bls.n 8004eee <HAL_RCC_OscConfig+0x246>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004eea: 2303 movs r3, #3
|
|
8004eec: e173 b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8004eee: 4b0b ldr r3, [pc, #44] @ (8004f1c <HAL_RCC_OscConfig+0x274>)
|
|
8004ef0: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8004ef2: f003 0302 and.w r3, r3, #2
|
|
8004ef6: 2b00 cmp r3, #0
|
|
8004ef8: d0f0 beq.n 8004edc <HAL_RCC_OscConfig+0x234>
|
|
8004efa: e01b b.n 8004f34 <HAL_RCC_OscConfig+0x28c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8004efc: 4b09 ldr r3, [pc, #36] @ (8004f24 <HAL_RCC_OscConfig+0x27c>)
|
|
8004efe: 2200 movs r2, #0
|
|
8004f00: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004f02: f7fc fd89 bl 8001a18 <HAL_GetTick>
|
|
8004f06: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8004f08: e00e b.n 8004f28 <HAL_RCC_OscConfig+0x280>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8004f0a: f7fc fd85 bl 8001a18 <HAL_GetTick>
|
|
8004f0e: 4602 mov r2, r0
|
|
8004f10: 693b ldr r3, [r7, #16]
|
|
8004f12: 1ad3 subs r3, r2, r3
|
|
8004f14: 2b02 cmp r3, #2
|
|
8004f16: d907 bls.n 8004f28 <HAL_RCC_OscConfig+0x280>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004f18: 2303 movs r3, #3
|
|
8004f1a: e15c b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
8004f1c: 40023800 .word 0x40023800
|
|
8004f20: 42470000 .word 0x42470000
|
|
8004f24: 42470e80 .word 0x42470e80
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8004f28: 4b8a ldr r3, [pc, #552] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004f2a: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8004f2c: f003 0302 and.w r3, r3, #2
|
|
8004f30: 2b00 cmp r3, #0
|
|
8004f32: d1ea bne.n 8004f0a <HAL_RCC_OscConfig+0x262>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8004f34: 687b ldr r3, [r7, #4]
|
|
8004f36: 681b ldr r3, [r3, #0]
|
|
8004f38: f003 0304 and.w r3, r3, #4
|
|
8004f3c: 2b00 cmp r3, #0
|
|
8004f3e: f000 8097 beq.w 8005070 <HAL_RCC_OscConfig+0x3c8>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8004f42: 2300 movs r3, #0
|
|
8004f44: 75fb strb r3, [r7, #23]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8004f46: 4b83 ldr r3, [pc, #524] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004f48: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004f4a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8004f4e: 2b00 cmp r3, #0
|
|
8004f50: d10f bne.n 8004f72 <HAL_RCC_OscConfig+0x2ca>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8004f52: 2300 movs r3, #0
|
|
8004f54: 60bb str r3, [r7, #8]
|
|
8004f56: 4b7f ldr r3, [pc, #508] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004f58: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004f5a: 4a7e ldr r2, [pc, #504] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004f5c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8004f60: 6413 str r3, [r2, #64] @ 0x40
|
|
8004f62: 4b7c ldr r3, [pc, #496] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004f64: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004f66: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8004f6a: 60bb str r3, [r7, #8]
|
|
8004f6c: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8004f6e: 2301 movs r3, #1
|
|
8004f70: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004f72: 4b79 ldr r3, [pc, #484] @ (8005158 <HAL_RCC_OscConfig+0x4b0>)
|
|
8004f74: 681b ldr r3, [r3, #0]
|
|
8004f76: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004f7a: 2b00 cmp r3, #0
|
|
8004f7c: d118 bne.n 8004fb0 <HAL_RCC_OscConfig+0x308>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
8004f7e: 4b76 ldr r3, [pc, #472] @ (8005158 <HAL_RCC_OscConfig+0x4b0>)
|
|
8004f80: 681b ldr r3, [r3, #0]
|
|
8004f82: 4a75 ldr r2, [pc, #468] @ (8005158 <HAL_RCC_OscConfig+0x4b0>)
|
|
8004f84: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8004f88: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8004f8a: f7fc fd45 bl 8001a18 <HAL_GetTick>
|
|
8004f8e: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004f90: e008 b.n 8004fa4 <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8004f92: f7fc fd41 bl 8001a18 <HAL_GetTick>
|
|
8004f96: 4602 mov r2, r0
|
|
8004f98: 693b ldr r3, [r7, #16]
|
|
8004f9a: 1ad3 subs r3, r2, r3
|
|
8004f9c: 2b02 cmp r3, #2
|
|
8004f9e: d901 bls.n 8004fa4 <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004fa0: 2303 movs r3, #3
|
|
8004fa2: e118 b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004fa4: 4b6c ldr r3, [pc, #432] @ (8005158 <HAL_RCC_OscConfig+0x4b0>)
|
|
8004fa6: 681b ldr r3, [r3, #0]
|
|
8004fa8: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004fac: 2b00 cmp r3, #0
|
|
8004fae: d0f0 beq.n 8004f92 <HAL_RCC_OscConfig+0x2ea>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8004fb0: 687b ldr r3, [r7, #4]
|
|
8004fb2: 689b ldr r3, [r3, #8]
|
|
8004fb4: 2b01 cmp r3, #1
|
|
8004fb6: d106 bne.n 8004fc6 <HAL_RCC_OscConfig+0x31e>
|
|
8004fb8: 4b66 ldr r3, [pc, #408] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004fba: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004fbc: 4a65 ldr r2, [pc, #404] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004fbe: f043 0301 orr.w r3, r3, #1
|
|
8004fc2: 6713 str r3, [r2, #112] @ 0x70
|
|
8004fc4: e01c b.n 8005000 <HAL_RCC_OscConfig+0x358>
|
|
8004fc6: 687b ldr r3, [r7, #4]
|
|
8004fc8: 689b ldr r3, [r3, #8]
|
|
8004fca: 2b05 cmp r3, #5
|
|
8004fcc: d10c bne.n 8004fe8 <HAL_RCC_OscConfig+0x340>
|
|
8004fce: 4b61 ldr r3, [pc, #388] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004fd0: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004fd2: 4a60 ldr r2, [pc, #384] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004fd4: f043 0304 orr.w r3, r3, #4
|
|
8004fd8: 6713 str r3, [r2, #112] @ 0x70
|
|
8004fda: 4b5e ldr r3, [pc, #376] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004fdc: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004fde: 4a5d ldr r2, [pc, #372] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004fe0: f043 0301 orr.w r3, r3, #1
|
|
8004fe4: 6713 str r3, [r2, #112] @ 0x70
|
|
8004fe6: e00b b.n 8005000 <HAL_RCC_OscConfig+0x358>
|
|
8004fe8: 4b5a ldr r3, [pc, #360] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004fea: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004fec: 4a59 ldr r2, [pc, #356] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004fee: f023 0301 bic.w r3, r3, #1
|
|
8004ff2: 6713 str r3, [r2, #112] @ 0x70
|
|
8004ff4: 4b57 ldr r3, [pc, #348] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004ff6: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004ff8: 4a56 ldr r2, [pc, #344] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8004ffa: f023 0304 bic.w r3, r3, #4
|
|
8004ffe: 6713 str r3, [r2, #112] @ 0x70
|
|
/* Check the LSE State */
|
|
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
|
|
8005000: 687b ldr r3, [r7, #4]
|
|
8005002: 689b ldr r3, [r3, #8]
|
|
8005004: 2b00 cmp r3, #0
|
|
8005006: d015 beq.n 8005034 <HAL_RCC_OscConfig+0x38c>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005008: f7fc fd06 bl 8001a18 <HAL_GetTick>
|
|
800500c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
800500e: e00a b.n 8005026 <HAL_RCC_OscConfig+0x37e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8005010: f7fc fd02 bl 8001a18 <HAL_GetTick>
|
|
8005014: 4602 mov r2, r0
|
|
8005016: 693b ldr r3, [r7, #16]
|
|
8005018: 1ad3 subs r3, r2, r3
|
|
800501a: f241 3288 movw r2, #5000 @ 0x1388
|
|
800501e: 4293 cmp r3, r2
|
|
8005020: d901 bls.n 8005026 <HAL_RCC_OscConfig+0x37e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005022: 2303 movs r3, #3
|
|
8005024: e0d7 b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8005026: 4b4b ldr r3, [pc, #300] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8005028: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800502a: f003 0302 and.w r3, r3, #2
|
|
800502e: 2b00 cmp r3, #0
|
|
8005030: d0ee beq.n 8005010 <HAL_RCC_OscConfig+0x368>
|
|
8005032: e014 b.n 800505e <HAL_RCC_OscConfig+0x3b6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005034: f7fc fcf0 bl 8001a18 <HAL_GetTick>
|
|
8005038: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
800503a: e00a b.n 8005052 <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800503c: f7fc fcec bl 8001a18 <HAL_GetTick>
|
|
8005040: 4602 mov r2, r0
|
|
8005042: 693b ldr r3, [r7, #16]
|
|
8005044: 1ad3 subs r3, r2, r3
|
|
8005046: f241 3288 movw r2, #5000 @ 0x1388
|
|
800504a: 4293 cmp r3, r2
|
|
800504c: d901 bls.n 8005052 <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800504e: 2303 movs r3, #3
|
|
8005050: e0c1 b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8005052: 4b40 ldr r3, [pc, #256] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8005054: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8005056: f003 0302 and.w r3, r3, #2
|
|
800505a: 2b00 cmp r3, #0
|
|
800505c: d1ee bne.n 800503c <HAL_RCC_OscConfig+0x394>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
800505e: 7dfb ldrb r3, [r7, #23]
|
|
8005060: 2b01 cmp r3, #1
|
|
8005062: d105 bne.n 8005070 <HAL_RCC_OscConfig+0x3c8>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8005064: 4b3b ldr r3, [pc, #236] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
8005066: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8005068: 4a3a ldr r2, [pc, #232] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
800506a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
800506e: 6413 str r3, [r2, #64] @ 0x40
|
|
}
|
|
}
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8005070: 687b ldr r3, [r7, #4]
|
|
8005072: 699b ldr r3, [r3, #24]
|
|
8005074: 2b00 cmp r3, #0
|
|
8005076: f000 80ad beq.w 80051d4 <HAL_RCC_OscConfig+0x52c>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
|
800507a: 4b36 ldr r3, [pc, #216] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
800507c: 689b ldr r3, [r3, #8]
|
|
800507e: f003 030c and.w r3, r3, #12
|
|
8005082: 2b08 cmp r3, #8
|
|
8005084: d060 beq.n 8005148 <HAL_RCC_OscConfig+0x4a0>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
8005086: 687b ldr r3, [r7, #4]
|
|
8005088: 699b ldr r3, [r3, #24]
|
|
800508a: 2b02 cmp r3, #2
|
|
800508c: d145 bne.n 800511a <HAL_RCC_OscConfig+0x472>
|
|
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
800508e: 4b33 ldr r3, [pc, #204] @ (800515c <HAL_RCC_OscConfig+0x4b4>)
|
|
8005090: 2200 movs r2, #0
|
|
8005092: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005094: f7fc fcc0 bl 8001a18 <HAL_GetTick>
|
|
8005098: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
800509a: e008 b.n 80050ae <HAL_RCC_OscConfig+0x406>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800509c: f7fc fcbc bl 8001a18 <HAL_GetTick>
|
|
80050a0: 4602 mov r2, r0
|
|
80050a2: 693b ldr r3, [r7, #16]
|
|
80050a4: 1ad3 subs r3, r2, r3
|
|
80050a6: 2b02 cmp r3, #2
|
|
80050a8: d901 bls.n 80050ae <HAL_RCC_OscConfig+0x406>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80050aa: 2303 movs r3, #3
|
|
80050ac: e093 b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80050ae: 4b29 ldr r3, [pc, #164] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
80050b0: 681b ldr r3, [r3, #0]
|
|
80050b2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80050b6: 2b00 cmp r3, #0
|
|
80050b8: d1f0 bne.n 800509c <HAL_RCC_OscConfig+0x3f4>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
|
|
80050ba: 687b ldr r3, [r7, #4]
|
|
80050bc: 69da ldr r2, [r3, #28]
|
|
80050be: 687b ldr r3, [r7, #4]
|
|
80050c0: 6a1b ldr r3, [r3, #32]
|
|
80050c2: 431a orrs r2, r3
|
|
80050c4: 687b ldr r3, [r7, #4]
|
|
80050c6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80050c8: 019b lsls r3, r3, #6
|
|
80050ca: 431a orrs r2, r3
|
|
80050cc: 687b ldr r3, [r7, #4]
|
|
80050ce: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80050d0: 085b lsrs r3, r3, #1
|
|
80050d2: 3b01 subs r3, #1
|
|
80050d4: 041b lsls r3, r3, #16
|
|
80050d6: 431a orrs r2, r3
|
|
80050d8: 687b ldr r3, [r7, #4]
|
|
80050da: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80050dc: 061b lsls r3, r3, #24
|
|
80050de: 431a orrs r2, r3
|
|
80050e0: 687b ldr r3, [r7, #4]
|
|
80050e2: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80050e4: 071b lsls r3, r3, #28
|
|
80050e6: 491b ldr r1, [pc, #108] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
80050e8: 4313 orrs r3, r2
|
|
80050ea: 604b str r3, [r1, #4]
|
|
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
|
|
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
80050ec: 4b1b ldr r3, [pc, #108] @ (800515c <HAL_RCC_OscConfig+0x4b4>)
|
|
80050ee: 2201 movs r2, #1
|
|
80050f0: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80050f2: f7fc fc91 bl 8001a18 <HAL_GetTick>
|
|
80050f6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
80050f8: e008 b.n 800510c <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80050fa: f7fc fc8d bl 8001a18 <HAL_GetTick>
|
|
80050fe: 4602 mov r2, r0
|
|
8005100: 693b ldr r3, [r7, #16]
|
|
8005102: 1ad3 subs r3, r2, r3
|
|
8005104: 2b02 cmp r3, #2
|
|
8005106: d901 bls.n 800510c <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005108: 2303 movs r3, #3
|
|
800510a: e064 b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
800510c: 4b11 ldr r3, [pc, #68] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
800510e: 681b ldr r3, [r3, #0]
|
|
8005110: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8005114: 2b00 cmp r3, #0
|
|
8005116: d0f0 beq.n 80050fa <HAL_RCC_OscConfig+0x452>
|
|
8005118: e05c b.n 80051d4 <HAL_RCC_OscConfig+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
800511a: 4b10 ldr r3, [pc, #64] @ (800515c <HAL_RCC_OscConfig+0x4b4>)
|
|
800511c: 2200 movs r2, #0
|
|
800511e: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8005120: f7fc fc7a bl 8001a18 <HAL_GetTick>
|
|
8005124: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8005126: e008 b.n 800513a <HAL_RCC_OscConfig+0x492>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8005128: f7fc fc76 bl 8001a18 <HAL_GetTick>
|
|
800512c: 4602 mov r2, r0
|
|
800512e: 693b ldr r3, [r7, #16]
|
|
8005130: 1ad3 subs r3, r2, r3
|
|
8005132: 2b02 cmp r3, #2
|
|
8005134: d901 bls.n 800513a <HAL_RCC_OscConfig+0x492>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005136: 2303 movs r3, #3
|
|
8005138: e04d b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
800513a: 4b06 ldr r3, [pc, #24] @ (8005154 <HAL_RCC_OscConfig+0x4ac>)
|
|
800513c: 681b ldr r3, [r3, #0]
|
|
800513e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8005142: 2b00 cmp r3, #0
|
|
8005144: d1f0 bne.n 8005128 <HAL_RCC_OscConfig+0x480>
|
|
8005146: e045 b.n 80051d4 <HAL_RCC_OscConfig+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8005148: 687b ldr r3, [r7, #4]
|
|
800514a: 699b ldr r3, [r3, #24]
|
|
800514c: 2b01 cmp r3, #1
|
|
800514e: d107 bne.n 8005160 <HAL_RCC_OscConfig+0x4b8>
|
|
{
|
|
return HAL_ERROR;
|
|
8005150: 2301 movs r3, #1
|
|
8005152: e040 b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
8005154: 40023800 .word 0x40023800
|
|
8005158: 40007000 .word 0x40007000
|
|
800515c: 42470060 .word 0x42470060
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->PLLCFGR;
|
|
8005160: 4b1f ldr r3, [pc, #124] @ (80051e0 <HAL_RCC_OscConfig+0x538>)
|
|
8005162: 685b ldr r3, [r3, #4]
|
|
8005164: 60fb str r3, [r7, #12]
|
|
#if defined (RCC_PLLCFGR_PLLR)
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
8005166: 687b ldr r3, [r7, #4]
|
|
8005168: 699b ldr r3, [r3, #24]
|
|
800516a: 2b01 cmp r3, #1
|
|
800516c: d030 beq.n 80051d0 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800516e: 68fb ldr r3, [r7, #12]
|
|
8005170: f403 0280 and.w r2, r3, #4194304 @ 0x400000
|
|
8005174: 687b ldr r3, [r7, #4]
|
|
8005176: 69db ldr r3, [r3, #28]
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
8005178: 429a cmp r2, r3
|
|
800517a: d129 bne.n 80051d0 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
800517c: 68fb ldr r3, [r7, #12]
|
|
800517e: f003 023f and.w r2, r3, #63 @ 0x3f
|
|
8005182: 687b ldr r3, [r7, #4]
|
|
8005184: 6a1b ldr r3, [r3, #32]
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8005186: 429a cmp r2, r3
|
|
8005188: d122 bne.n 80051d0 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
800518a: 68fa ldr r2, [r7, #12]
|
|
800518c: f647 73c0 movw r3, #32704 @ 0x7fc0
|
|
8005190: 4013 ands r3, r2
|
|
8005192: 687a ldr r2, [r7, #4]
|
|
8005194: 6a52 ldr r2, [r2, #36] @ 0x24
|
|
8005196: 0192 lsls r2, r2, #6
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
8005198: 4293 cmp r3, r2
|
|
800519a: d119 bne.n 80051d0 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
800519c: 68fb ldr r3, [r7, #12]
|
|
800519e: f403 3240 and.w r2, r3, #196608 @ 0x30000
|
|
80051a2: 687b ldr r3, [r7, #4]
|
|
80051a4: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80051a6: 085b lsrs r3, r3, #1
|
|
80051a8: 3b01 subs r3, #1
|
|
80051aa: 041b lsls r3, r3, #16
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
80051ac: 429a cmp r2, r3
|
|
80051ae: d10f bne.n 80051d0 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
80051b0: 68fb ldr r3, [r7, #12]
|
|
80051b2: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
|
|
80051b6: 687b ldr r3, [r7, #4]
|
|
80051b8: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80051ba: 061b lsls r3, r3, #24
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
80051bc: 429a cmp r2, r3
|
|
80051be: d107 bne.n 80051d0 <HAL_RCC_OscConfig+0x528>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
|
|
80051c0: 68fb ldr r3, [r7, #12]
|
|
80051c2: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000
|
|
80051c6: 687b ldr r3, [r7, #4]
|
|
80051c8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80051ca: 071b lsls r3, r3, #28
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
80051cc: 429a cmp r2, r3
|
|
80051ce: d001 beq.n 80051d4 <HAL_RCC_OscConfig+0x52c>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
|
|
#endif /* RCC_PLLCFGR_PLLR */
|
|
{
|
|
return HAL_ERROR;
|
|
80051d0: 2301 movs r3, #1
|
|
80051d2: e000 b.n 80051d6 <HAL_RCC_OscConfig+0x52e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80051d4: 2300 movs r3, #0
|
|
}
|
|
80051d6: 4618 mov r0, r3
|
|
80051d8: 3718 adds r7, #24
|
|
80051da: 46bd mov sp, r7
|
|
80051dc: bd80 pop {r7, pc}
|
|
80051de: bf00 nop
|
|
80051e0: 40023800 .word 0x40023800
|
|
|
|
080051e4 <HAL_TIM_OC_Init>:
|
|
* Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
|
|
* @param htim TIM Output Compare handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
80051e4: b580 push {r7, lr}
|
|
80051e6: b082 sub sp, #8
|
|
80051e8: af00 add r7, sp, #0
|
|
80051ea: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
80051ec: 687b ldr r3, [r7, #4]
|
|
80051ee: 2b00 cmp r3, #0
|
|
80051f0: d101 bne.n 80051f6 <HAL_TIM_OC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80051f2: 2301 movs r3, #1
|
|
80051f4: e041 b.n 800527a <HAL_TIM_OC_Init+0x96>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
80051f6: 687b ldr r3, [r7, #4]
|
|
80051f8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
80051fc: b2db uxtb r3, r3
|
|
80051fe: 2b00 cmp r3, #0
|
|
8005200: d106 bne.n 8005210 <HAL_TIM_OC_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8005202: 687b ldr r3, [r7, #4]
|
|
8005204: 2200 movs r2, #0
|
|
8005206: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->OC_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_OC_MspInit(htim);
|
|
800520a: 6878 ldr r0, [r7, #4]
|
|
800520c: f7fb ff6a bl 80010e4 <HAL_TIM_OC_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005210: 687b ldr r3, [r7, #4]
|
|
8005212: 2202 movs r2, #2
|
|
8005214: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Init the base time for the Output Compare */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8005218: 687b ldr r3, [r7, #4]
|
|
800521a: 681a ldr r2, [r3, #0]
|
|
800521c: 687b ldr r3, [r7, #4]
|
|
800521e: 3304 adds r3, #4
|
|
8005220: 4619 mov r1, r3
|
|
8005222: 4610 mov r0, r2
|
|
8005224: f000 f930 bl 8005488 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8005228: 687b ldr r3, [r7, #4]
|
|
800522a: 2201 movs r2, #1
|
|
800522c: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8005230: 687b ldr r3, [r7, #4]
|
|
8005232: 2201 movs r2, #1
|
|
8005234: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
8005238: 687b ldr r3, [r7, #4]
|
|
800523a: 2201 movs r2, #1
|
|
800523c: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
8005240: 687b ldr r3, [r7, #4]
|
|
8005242: 2201 movs r2, #1
|
|
8005244: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
8005248: 687b ldr r3, [r7, #4]
|
|
800524a: 2201 movs r2, #1
|
|
800524c: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8005250: 687b ldr r3, [r7, #4]
|
|
8005252: 2201 movs r2, #1
|
|
8005254: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
8005258: 687b ldr r3, [r7, #4]
|
|
800525a: 2201 movs r2, #1
|
|
800525c: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
8005260: 687b ldr r3, [r7, #4]
|
|
8005262: 2201 movs r2, #1
|
|
8005264: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
8005268: 687b ldr r3, [r7, #4]
|
|
800526a: 2201 movs r2, #1
|
|
800526c: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005270: 687b ldr r3, [r7, #4]
|
|
8005272: 2201 movs r2, #1
|
|
8005274: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
8005278: 2300 movs r3, #0
|
|
}
|
|
800527a: 4618 mov r0, r3
|
|
800527c: 3708 adds r7, #8
|
|
800527e: 46bd mov sp, r7
|
|
8005280: bd80 pop {r7, pc}
|
|
|
|
08005282 <HAL_TIM_Encoder_Init>:
|
|
* @param htim TIM Encoder Interface handle
|
|
* @param sConfig TIM Encoder Interface configuration structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
|
|
{
|
|
8005282: b580 push {r7, lr}
|
|
8005284: b086 sub sp, #24
|
|
8005286: af00 add r7, sp, #0
|
|
8005288: 6078 str r0, [r7, #4]
|
|
800528a: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
800528c: 687b ldr r3, [r7, #4]
|
|
800528e: 2b00 cmp r3, #0
|
|
8005290: d101 bne.n 8005296 <HAL_TIM_Encoder_Init+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8005292: 2301 movs r3, #1
|
|
8005294: e097 b.n 80053c6 <HAL_TIM_Encoder_Init+0x144>
|
|
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
|
|
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
|
|
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8005296: 687b ldr r3, [r7, #4]
|
|
8005298: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
800529c: b2db uxtb r3, r3
|
|
800529e: 2b00 cmp r3, #0
|
|
80052a0: d106 bne.n 80052b0 <HAL_TIM_Encoder_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
80052a2: 687b ldr r3, [r7, #4]
|
|
80052a4: 2200 movs r2, #0
|
|
80052a6: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Encoder_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_Encoder_MspInit(htim);
|
|
80052aa: 6878 ldr r0, [r7, #4]
|
|
80052ac: f7fb ff3a bl 8001124 <HAL_TIM_Encoder_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80052b0: 687b ldr r3, [r7, #4]
|
|
80052b2: 2202 movs r2, #2
|
|
80052b4: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Reset the SMS and ECE bits */
|
|
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
|
|
80052b8: 687b ldr r3, [r7, #4]
|
|
80052ba: 681b ldr r3, [r3, #0]
|
|
80052bc: 689b ldr r3, [r3, #8]
|
|
80052be: 687a ldr r2, [r7, #4]
|
|
80052c0: 6812 ldr r2, [r2, #0]
|
|
80052c2: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
80052c6: f023 0307 bic.w r3, r3, #7
|
|
80052ca: 6093 str r3, [r2, #8]
|
|
|
|
/* Configure the Time base in the Encoder Mode */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
80052cc: 687b ldr r3, [r7, #4]
|
|
80052ce: 681a ldr r2, [r3, #0]
|
|
80052d0: 687b ldr r3, [r7, #4]
|
|
80052d2: 3304 adds r3, #4
|
|
80052d4: 4619 mov r1, r3
|
|
80052d6: 4610 mov r0, r2
|
|
80052d8: f000 f8d6 bl 8005488 <TIM_Base_SetConfig>
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80052dc: 687b ldr r3, [r7, #4]
|
|
80052de: 681b ldr r3, [r3, #0]
|
|
80052e0: 689b ldr r3, [r3, #8]
|
|
80052e2: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmr1 = htim->Instance->CCMR1;
|
|
80052e4: 687b ldr r3, [r7, #4]
|
|
80052e6: 681b ldr r3, [r3, #0]
|
|
80052e8: 699b ldr r3, [r3, #24]
|
|
80052ea: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = htim->Instance->CCER;
|
|
80052ec: 687b ldr r3, [r7, #4]
|
|
80052ee: 681b ldr r3, [r3, #0]
|
|
80052f0: 6a1b ldr r3, [r3, #32]
|
|
80052f2: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the encoder Mode */
|
|
tmpsmcr |= sConfig->EncoderMode;
|
|
80052f4: 683b ldr r3, [r7, #0]
|
|
80052f6: 681b ldr r3, [r3, #0]
|
|
80052f8: 697a ldr r2, [r7, #20]
|
|
80052fa: 4313 orrs r3, r2
|
|
80052fc: 617b str r3, [r7, #20]
|
|
|
|
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
|
|
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
|
|
80052fe: 693b ldr r3, [r7, #16]
|
|
8005300: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8005304: f023 0303 bic.w r3, r3, #3
|
|
8005308: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
|
|
800530a: 683b ldr r3, [r7, #0]
|
|
800530c: 689a ldr r2, [r3, #8]
|
|
800530e: 683b ldr r3, [r7, #0]
|
|
8005310: 699b ldr r3, [r3, #24]
|
|
8005312: 021b lsls r3, r3, #8
|
|
8005314: 4313 orrs r3, r2
|
|
8005316: 693a ldr r2, [r7, #16]
|
|
8005318: 4313 orrs r3, r2
|
|
800531a: 613b str r3, [r7, #16]
|
|
|
|
/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
|
|
800531c: 693b ldr r3, [r7, #16]
|
|
800531e: f423 6340 bic.w r3, r3, #3072 @ 0xc00
|
|
8005322: f023 030c bic.w r3, r3, #12
|
|
8005326: 613b str r3, [r7, #16]
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
|
|
8005328: 693b ldr r3, [r7, #16]
|
|
800532a: f423 4370 bic.w r3, r3, #61440 @ 0xf000
|
|
800532e: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
8005332: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
|
|
8005334: 683b ldr r3, [r7, #0]
|
|
8005336: 68da ldr r2, [r3, #12]
|
|
8005338: 683b ldr r3, [r7, #0]
|
|
800533a: 69db ldr r3, [r3, #28]
|
|
800533c: 021b lsls r3, r3, #8
|
|
800533e: 4313 orrs r3, r2
|
|
8005340: 693a ldr r2, [r7, #16]
|
|
8005342: 4313 orrs r3, r2
|
|
8005344: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
|
|
8005346: 683b ldr r3, [r7, #0]
|
|
8005348: 691b ldr r3, [r3, #16]
|
|
800534a: 011a lsls r2, r3, #4
|
|
800534c: 683b ldr r3, [r7, #0]
|
|
800534e: 6a1b ldr r3, [r3, #32]
|
|
8005350: 031b lsls r3, r3, #12
|
|
8005352: 4313 orrs r3, r2
|
|
8005354: 693a ldr r2, [r7, #16]
|
|
8005356: 4313 orrs r3, r2
|
|
8005358: 613b str r3, [r7, #16]
|
|
|
|
/* Set the TI1 and the TI2 Polarities */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
|
|
800535a: 68fb ldr r3, [r7, #12]
|
|
800535c: f023 0322 bic.w r3, r3, #34 @ 0x22
|
|
8005360: 60fb str r3, [r7, #12]
|
|
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
|
|
8005362: 68fb ldr r3, [r7, #12]
|
|
8005364: f023 0388 bic.w r3, r3, #136 @ 0x88
|
|
8005368: 60fb str r3, [r7, #12]
|
|
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
|
|
800536a: 683b ldr r3, [r7, #0]
|
|
800536c: 685a ldr r2, [r3, #4]
|
|
800536e: 683b ldr r3, [r7, #0]
|
|
8005370: 695b ldr r3, [r3, #20]
|
|
8005372: 011b lsls r3, r3, #4
|
|
8005374: 4313 orrs r3, r2
|
|
8005376: 68fa ldr r2, [r7, #12]
|
|
8005378: 4313 orrs r3, r2
|
|
800537a: 60fb str r3, [r7, #12]
|
|
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
800537c: 687b ldr r3, [r7, #4]
|
|
800537e: 681b ldr r3, [r3, #0]
|
|
8005380: 697a ldr r2, [r7, #20]
|
|
8005382: 609a str r2, [r3, #8]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
htim->Instance->CCMR1 = tmpccmr1;
|
|
8005384: 687b ldr r3, [r7, #4]
|
|
8005386: 681b ldr r3, [r3, #0]
|
|
8005388: 693a ldr r2, [r7, #16]
|
|
800538a: 619a str r2, [r3, #24]
|
|
|
|
/* Write to TIMx CCER */
|
|
htim->Instance->CCER = tmpccer;
|
|
800538c: 687b ldr r3, [r7, #4]
|
|
800538e: 681b ldr r3, [r3, #0]
|
|
8005390: 68fa ldr r2, [r7, #12]
|
|
8005392: 621a str r2, [r3, #32]
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8005394: 687b ldr r3, [r7, #4]
|
|
8005396: 2201 movs r2, #1
|
|
8005398: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Set the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
800539c: 687b ldr r3, [r7, #4]
|
|
800539e: 2201 movs r2, #1
|
|
80053a0: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
80053a4: 687b ldr r3, [r7, #4]
|
|
80053a6: 2201 movs r2, #1
|
|
80053a8: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
80053ac: 687b ldr r3, [r7, #4]
|
|
80053ae: 2201 movs r2, #1
|
|
80053b0: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
80053b4: 687b ldr r3, [r7, #4]
|
|
80053b6: 2201 movs r2, #1
|
|
80053b8: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80053bc: 687b ldr r3, [r7, #4]
|
|
80053be: 2201 movs r2, #1
|
|
80053c0: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
80053c4: 2300 movs r3, #0
|
|
}
|
|
80053c6: 4618 mov r0, r3
|
|
80053c8: 3718 adds r7, #24
|
|
80053ca: 46bd mov sp, r7
|
|
80053cc: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080053d0 <HAL_TIM_OC_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
const TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
80053d0: b580 push {r7, lr}
|
|
80053d2: b086 sub sp, #24
|
|
80053d4: af00 add r7, sp, #0
|
|
80053d6: 60f8 str r0, [r7, #12]
|
|
80053d8: 60b9 str r1, [r7, #8]
|
|
80053da: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80053dc: 2300 movs r3, #0
|
|
80053de: 75fb strb r3, [r7, #23]
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
80053e0: 68fb ldr r3, [r7, #12]
|
|
80053e2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
80053e6: 2b01 cmp r3, #1
|
|
80053e8: d101 bne.n 80053ee <HAL_TIM_OC_ConfigChannel+0x1e>
|
|
80053ea: 2302 movs r3, #2
|
|
80053ec: e048 b.n 8005480 <HAL_TIM_OC_ConfigChannel+0xb0>
|
|
80053ee: 68fb ldr r3, [r7, #12]
|
|
80053f0: 2201 movs r2, #1
|
|
80053f2: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
switch (Channel)
|
|
80053f6: 687b ldr r3, [r7, #4]
|
|
80053f8: 2b0c cmp r3, #12
|
|
80053fa: d839 bhi.n 8005470 <HAL_TIM_OC_ConfigChannel+0xa0>
|
|
80053fc: a201 add r2, pc, #4 @ (adr r2, 8005404 <HAL_TIM_OC_ConfigChannel+0x34>)
|
|
80053fe: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8005402: bf00 nop
|
|
8005404: 08005439 .word 0x08005439
|
|
8005408: 08005471 .word 0x08005471
|
|
800540c: 08005471 .word 0x08005471
|
|
8005410: 08005471 .word 0x08005471
|
|
8005414: 08005447 .word 0x08005447
|
|
8005418: 08005471 .word 0x08005471
|
|
800541c: 08005471 .word 0x08005471
|
|
8005420: 08005471 .word 0x08005471
|
|
8005424: 08005455 .word 0x08005455
|
|
8005428: 08005471 .word 0x08005471
|
|
800542c: 08005471 .word 0x08005471
|
|
8005430: 08005471 .word 0x08005471
|
|
8005434: 08005463 .word 0x08005463
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 1 in Output Compare */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
8005438: 68fb ldr r3, [r7, #12]
|
|
800543a: 681b ldr r3, [r3, #0]
|
|
800543c: 68b9 ldr r1, [r7, #8]
|
|
800543e: 4618 mov r0, r3
|
|
8005440: f000 f8c8 bl 80055d4 <TIM_OC1_SetConfig>
|
|
break;
|
|
8005444: e017 b.n 8005476 <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 2 in Output Compare */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
8005446: 68fb ldr r3, [r7, #12]
|
|
8005448: 681b ldr r3, [r3, #0]
|
|
800544a: 68b9 ldr r1, [r7, #8]
|
|
800544c: 4618 mov r0, r3
|
|
800544e: f000 f931 bl 80056b4 <TIM_OC2_SetConfig>
|
|
break;
|
|
8005452: e010 b.n 8005476 <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 3 in Output Compare */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
8005454: 68fb ldr r3, [r7, #12]
|
|
8005456: 681b ldr r3, [r3, #0]
|
|
8005458: 68b9 ldr r1, [r7, #8]
|
|
800545a: 4618 mov r0, r3
|
|
800545c: f000 f9a0 bl 80057a0 <TIM_OC3_SetConfig>
|
|
break;
|
|
8005460: e009 b.n 8005476 <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 4 in Output Compare */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
8005462: 68fb ldr r3, [r7, #12]
|
|
8005464: 681b ldr r3, [r3, #0]
|
|
8005466: 68b9 ldr r1, [r7, #8]
|
|
8005468: 4618 mov r0, r3
|
|
800546a: f000 fa0d bl 8005888 <TIM_OC4_SetConfig>
|
|
break;
|
|
800546e: e002 b.n 8005476 <HAL_TIM_OC_ConfigChannel+0xa6>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
8005470: 2301 movs r3, #1
|
|
8005472: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8005474: bf00 nop
|
|
}
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8005476: 68fb ldr r3, [r7, #12]
|
|
8005478: 2200 movs r2, #0
|
|
800547a: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
800547e: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8005480: 4618 mov r0, r3
|
|
8005482: 3718 adds r7, #24
|
|
8005484: 46bd mov sp, r7
|
|
8005486: bd80 pop {r7, pc}
|
|
|
|
08005488 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8005488: b480 push {r7}
|
|
800548a: b085 sub sp, #20
|
|
800548c: af00 add r7, sp, #0
|
|
800548e: 6078 str r0, [r7, #4]
|
|
8005490: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
8005492: 687b ldr r3, [r7, #4]
|
|
8005494: 681b ldr r3, [r3, #0]
|
|
8005496: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8005498: 687b ldr r3, [r7, #4]
|
|
800549a: 4a43 ldr r2, [pc, #268] @ (80055a8 <TIM_Base_SetConfig+0x120>)
|
|
800549c: 4293 cmp r3, r2
|
|
800549e: d013 beq.n 80054c8 <TIM_Base_SetConfig+0x40>
|
|
80054a0: 687b ldr r3, [r7, #4]
|
|
80054a2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80054a6: d00f beq.n 80054c8 <TIM_Base_SetConfig+0x40>
|
|
80054a8: 687b ldr r3, [r7, #4]
|
|
80054aa: 4a40 ldr r2, [pc, #256] @ (80055ac <TIM_Base_SetConfig+0x124>)
|
|
80054ac: 4293 cmp r3, r2
|
|
80054ae: d00b beq.n 80054c8 <TIM_Base_SetConfig+0x40>
|
|
80054b0: 687b ldr r3, [r7, #4]
|
|
80054b2: 4a3f ldr r2, [pc, #252] @ (80055b0 <TIM_Base_SetConfig+0x128>)
|
|
80054b4: 4293 cmp r3, r2
|
|
80054b6: d007 beq.n 80054c8 <TIM_Base_SetConfig+0x40>
|
|
80054b8: 687b ldr r3, [r7, #4]
|
|
80054ba: 4a3e ldr r2, [pc, #248] @ (80055b4 <TIM_Base_SetConfig+0x12c>)
|
|
80054bc: 4293 cmp r3, r2
|
|
80054be: d003 beq.n 80054c8 <TIM_Base_SetConfig+0x40>
|
|
80054c0: 687b ldr r3, [r7, #4]
|
|
80054c2: 4a3d ldr r2, [pc, #244] @ (80055b8 <TIM_Base_SetConfig+0x130>)
|
|
80054c4: 4293 cmp r3, r2
|
|
80054c6: d108 bne.n 80054da <TIM_Base_SetConfig+0x52>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
80054c8: 68fb ldr r3, [r7, #12]
|
|
80054ca: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80054ce: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
80054d0: 683b ldr r3, [r7, #0]
|
|
80054d2: 685b ldr r3, [r3, #4]
|
|
80054d4: 68fa ldr r2, [r7, #12]
|
|
80054d6: 4313 orrs r3, r2
|
|
80054d8: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80054da: 687b ldr r3, [r7, #4]
|
|
80054dc: 4a32 ldr r2, [pc, #200] @ (80055a8 <TIM_Base_SetConfig+0x120>)
|
|
80054de: 4293 cmp r3, r2
|
|
80054e0: d02b beq.n 800553a <TIM_Base_SetConfig+0xb2>
|
|
80054e2: 687b ldr r3, [r7, #4]
|
|
80054e4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80054e8: d027 beq.n 800553a <TIM_Base_SetConfig+0xb2>
|
|
80054ea: 687b ldr r3, [r7, #4]
|
|
80054ec: 4a2f ldr r2, [pc, #188] @ (80055ac <TIM_Base_SetConfig+0x124>)
|
|
80054ee: 4293 cmp r3, r2
|
|
80054f0: d023 beq.n 800553a <TIM_Base_SetConfig+0xb2>
|
|
80054f2: 687b ldr r3, [r7, #4]
|
|
80054f4: 4a2e ldr r2, [pc, #184] @ (80055b0 <TIM_Base_SetConfig+0x128>)
|
|
80054f6: 4293 cmp r3, r2
|
|
80054f8: d01f beq.n 800553a <TIM_Base_SetConfig+0xb2>
|
|
80054fa: 687b ldr r3, [r7, #4]
|
|
80054fc: 4a2d ldr r2, [pc, #180] @ (80055b4 <TIM_Base_SetConfig+0x12c>)
|
|
80054fe: 4293 cmp r3, r2
|
|
8005500: d01b beq.n 800553a <TIM_Base_SetConfig+0xb2>
|
|
8005502: 687b ldr r3, [r7, #4]
|
|
8005504: 4a2c ldr r2, [pc, #176] @ (80055b8 <TIM_Base_SetConfig+0x130>)
|
|
8005506: 4293 cmp r3, r2
|
|
8005508: d017 beq.n 800553a <TIM_Base_SetConfig+0xb2>
|
|
800550a: 687b ldr r3, [r7, #4]
|
|
800550c: 4a2b ldr r2, [pc, #172] @ (80055bc <TIM_Base_SetConfig+0x134>)
|
|
800550e: 4293 cmp r3, r2
|
|
8005510: d013 beq.n 800553a <TIM_Base_SetConfig+0xb2>
|
|
8005512: 687b ldr r3, [r7, #4]
|
|
8005514: 4a2a ldr r2, [pc, #168] @ (80055c0 <TIM_Base_SetConfig+0x138>)
|
|
8005516: 4293 cmp r3, r2
|
|
8005518: d00f beq.n 800553a <TIM_Base_SetConfig+0xb2>
|
|
800551a: 687b ldr r3, [r7, #4]
|
|
800551c: 4a29 ldr r2, [pc, #164] @ (80055c4 <TIM_Base_SetConfig+0x13c>)
|
|
800551e: 4293 cmp r3, r2
|
|
8005520: d00b beq.n 800553a <TIM_Base_SetConfig+0xb2>
|
|
8005522: 687b ldr r3, [r7, #4]
|
|
8005524: 4a28 ldr r2, [pc, #160] @ (80055c8 <TIM_Base_SetConfig+0x140>)
|
|
8005526: 4293 cmp r3, r2
|
|
8005528: d007 beq.n 800553a <TIM_Base_SetConfig+0xb2>
|
|
800552a: 687b ldr r3, [r7, #4]
|
|
800552c: 4a27 ldr r2, [pc, #156] @ (80055cc <TIM_Base_SetConfig+0x144>)
|
|
800552e: 4293 cmp r3, r2
|
|
8005530: d003 beq.n 800553a <TIM_Base_SetConfig+0xb2>
|
|
8005532: 687b ldr r3, [r7, #4]
|
|
8005534: 4a26 ldr r2, [pc, #152] @ (80055d0 <TIM_Base_SetConfig+0x148>)
|
|
8005536: 4293 cmp r3, r2
|
|
8005538: d108 bne.n 800554c <TIM_Base_SetConfig+0xc4>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
800553a: 68fb ldr r3, [r7, #12]
|
|
800553c: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8005540: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
8005542: 683b ldr r3, [r7, #0]
|
|
8005544: 68db ldr r3, [r3, #12]
|
|
8005546: 68fa ldr r2, [r7, #12]
|
|
8005548: 4313 orrs r3, r2
|
|
800554a: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
800554c: 68fb ldr r3, [r7, #12]
|
|
800554e: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
8005552: 683b ldr r3, [r7, #0]
|
|
8005554: 695b ldr r3, [r3, #20]
|
|
8005556: 4313 orrs r3, r2
|
|
8005558: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
800555a: 683b ldr r3, [r7, #0]
|
|
800555c: 689a ldr r2, [r3, #8]
|
|
800555e: 687b ldr r3, [r7, #4]
|
|
8005560: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
8005562: 683b ldr r3, [r7, #0]
|
|
8005564: 681a ldr r2, [r3, #0]
|
|
8005566: 687b ldr r3, [r7, #4]
|
|
8005568: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
800556a: 687b ldr r3, [r7, #4]
|
|
800556c: 4a0e ldr r2, [pc, #56] @ (80055a8 <TIM_Base_SetConfig+0x120>)
|
|
800556e: 4293 cmp r3, r2
|
|
8005570: d003 beq.n 800557a <TIM_Base_SetConfig+0xf2>
|
|
8005572: 687b ldr r3, [r7, #4]
|
|
8005574: 4a10 ldr r2, [pc, #64] @ (80055b8 <TIM_Base_SetConfig+0x130>)
|
|
8005576: 4293 cmp r3, r2
|
|
8005578: d103 bne.n 8005582 <TIM_Base_SetConfig+0xfa>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
800557a: 683b ldr r3, [r7, #0]
|
|
800557c: 691a ldr r2, [r3, #16]
|
|
800557e: 687b ldr r3, [r7, #4]
|
|
8005580: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Disable Update Event (UEV) with Update Generation (UG)
|
|
by changing Update Request Source (URS) to avoid Update flag (UIF) */
|
|
SET_BIT(TIMx->CR1, TIM_CR1_URS);
|
|
8005582: 687b ldr r3, [r7, #4]
|
|
8005584: 681b ldr r3, [r3, #0]
|
|
8005586: f043 0204 orr.w r2, r3, #4
|
|
800558a: 687b ldr r3, [r7, #4]
|
|
800558c: 601a str r2, [r3, #0]
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
800558e: 687b ldr r3, [r7, #4]
|
|
8005590: 2201 movs r2, #1
|
|
8005592: 615a str r2, [r3, #20]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
8005594: 687b ldr r3, [r7, #4]
|
|
8005596: 68fa ldr r2, [r7, #12]
|
|
8005598: 601a str r2, [r3, #0]
|
|
}
|
|
800559a: bf00 nop
|
|
800559c: 3714 adds r7, #20
|
|
800559e: 46bd mov sp, r7
|
|
80055a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80055a4: 4770 bx lr
|
|
80055a6: bf00 nop
|
|
80055a8: 40010000 .word 0x40010000
|
|
80055ac: 40000400 .word 0x40000400
|
|
80055b0: 40000800 .word 0x40000800
|
|
80055b4: 40000c00 .word 0x40000c00
|
|
80055b8: 40010400 .word 0x40010400
|
|
80055bc: 40014000 .word 0x40014000
|
|
80055c0: 40014400 .word 0x40014400
|
|
80055c4: 40014800 .word 0x40014800
|
|
80055c8: 40001800 .word 0x40001800
|
|
80055cc: 40001c00 .word 0x40001c00
|
|
80055d0: 40002000 .word 0x40002000
|
|
|
|
080055d4 <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
80055d4: b480 push {r7}
|
|
80055d6: b087 sub sp, #28
|
|
80055d8: af00 add r7, sp, #0
|
|
80055da: 6078 str r0, [r7, #4]
|
|
80055dc: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
80055de: 687b ldr r3, [r7, #4]
|
|
80055e0: 6a1b ldr r3, [r3, #32]
|
|
80055e2: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
80055e4: 687b ldr r3, [r7, #4]
|
|
80055e6: 6a1b ldr r3, [r3, #32]
|
|
80055e8: f023 0201 bic.w r2, r3, #1
|
|
80055ec: 687b ldr r3, [r7, #4]
|
|
80055ee: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80055f0: 687b ldr r3, [r7, #4]
|
|
80055f2: 685b ldr r3, [r3, #4]
|
|
80055f4: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
80055f6: 687b ldr r3, [r7, #4]
|
|
80055f8: 699b ldr r3, [r3, #24]
|
|
80055fa: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
80055fc: 68fb ldr r3, [r7, #12]
|
|
80055fe: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005602: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
8005604: 68fb ldr r3, [r7, #12]
|
|
8005606: f023 0303 bic.w r3, r3, #3
|
|
800560a: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
800560c: 683b ldr r3, [r7, #0]
|
|
800560e: 681b ldr r3, [r3, #0]
|
|
8005610: 68fa ldr r2, [r7, #12]
|
|
8005612: 4313 orrs r3, r2
|
|
8005614: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
8005616: 697b ldr r3, [r7, #20]
|
|
8005618: f023 0302 bic.w r3, r3, #2
|
|
800561c: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
800561e: 683b ldr r3, [r7, #0]
|
|
8005620: 689b ldr r3, [r3, #8]
|
|
8005622: 697a ldr r2, [r7, #20]
|
|
8005624: 4313 orrs r3, r2
|
|
8005626: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
8005628: 687b ldr r3, [r7, #4]
|
|
800562a: 4a20 ldr r2, [pc, #128] @ (80056ac <TIM_OC1_SetConfig+0xd8>)
|
|
800562c: 4293 cmp r3, r2
|
|
800562e: d003 beq.n 8005638 <TIM_OC1_SetConfig+0x64>
|
|
8005630: 687b ldr r3, [r7, #4]
|
|
8005632: 4a1f ldr r2, [pc, #124] @ (80056b0 <TIM_OC1_SetConfig+0xdc>)
|
|
8005634: 4293 cmp r3, r2
|
|
8005636: d10c bne.n 8005652 <TIM_OC1_SetConfig+0x7e>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
8005638: 697b ldr r3, [r7, #20]
|
|
800563a: f023 0308 bic.w r3, r3, #8
|
|
800563e: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
8005640: 683b ldr r3, [r7, #0]
|
|
8005642: 68db ldr r3, [r3, #12]
|
|
8005644: 697a ldr r2, [r7, #20]
|
|
8005646: 4313 orrs r3, r2
|
|
8005648: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
800564a: 697b ldr r3, [r7, #20]
|
|
800564c: f023 0304 bic.w r3, r3, #4
|
|
8005650: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8005652: 687b ldr r3, [r7, #4]
|
|
8005654: 4a15 ldr r2, [pc, #84] @ (80056ac <TIM_OC1_SetConfig+0xd8>)
|
|
8005656: 4293 cmp r3, r2
|
|
8005658: d003 beq.n 8005662 <TIM_OC1_SetConfig+0x8e>
|
|
800565a: 687b ldr r3, [r7, #4]
|
|
800565c: 4a14 ldr r2, [pc, #80] @ (80056b0 <TIM_OC1_SetConfig+0xdc>)
|
|
800565e: 4293 cmp r3, r2
|
|
8005660: d111 bne.n 8005686 <TIM_OC1_SetConfig+0xb2>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
8005662: 693b ldr r3, [r7, #16]
|
|
8005664: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8005668: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
800566a: 693b ldr r3, [r7, #16]
|
|
800566c: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
8005670: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
8005672: 683b ldr r3, [r7, #0]
|
|
8005674: 695b ldr r3, [r3, #20]
|
|
8005676: 693a ldr r2, [r7, #16]
|
|
8005678: 4313 orrs r3, r2
|
|
800567a: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
800567c: 683b ldr r3, [r7, #0]
|
|
800567e: 699b ldr r3, [r3, #24]
|
|
8005680: 693a ldr r2, [r7, #16]
|
|
8005682: 4313 orrs r3, r2
|
|
8005684: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005686: 687b ldr r3, [r7, #4]
|
|
8005688: 693a ldr r2, [r7, #16]
|
|
800568a: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
800568c: 687b ldr r3, [r7, #4]
|
|
800568e: 68fa ldr r2, [r7, #12]
|
|
8005690: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
8005692: 683b ldr r3, [r7, #0]
|
|
8005694: 685a ldr r2, [r3, #4]
|
|
8005696: 687b ldr r3, [r7, #4]
|
|
8005698: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800569a: 687b ldr r3, [r7, #4]
|
|
800569c: 697a ldr r2, [r7, #20]
|
|
800569e: 621a str r2, [r3, #32]
|
|
}
|
|
80056a0: bf00 nop
|
|
80056a2: 371c adds r7, #28
|
|
80056a4: 46bd mov sp, r7
|
|
80056a6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80056aa: 4770 bx lr
|
|
80056ac: 40010000 .word 0x40010000
|
|
80056b0: 40010400 .word 0x40010400
|
|
|
|
080056b4 <TIM_OC2_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
80056b4: b480 push {r7}
|
|
80056b6: b087 sub sp, #28
|
|
80056b8: af00 add r7, sp, #0
|
|
80056ba: 6078 str r0, [r7, #4]
|
|
80056bc: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
80056be: 687b ldr r3, [r7, #4]
|
|
80056c0: 6a1b ldr r3, [r3, #32]
|
|
80056c2: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
80056c4: 687b ldr r3, [r7, #4]
|
|
80056c6: 6a1b ldr r3, [r3, #32]
|
|
80056c8: f023 0210 bic.w r2, r3, #16
|
|
80056cc: 687b ldr r3, [r7, #4]
|
|
80056ce: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80056d0: 687b ldr r3, [r7, #4]
|
|
80056d2: 685b ldr r3, [r3, #4]
|
|
80056d4: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
80056d6: 687b ldr r3, [r7, #4]
|
|
80056d8: 699b ldr r3, [r3, #24]
|
|
80056da: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
80056dc: 68fb ldr r3, [r7, #12]
|
|
80056de: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80056e2: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
80056e4: 68fb ldr r3, [r7, #12]
|
|
80056e6: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80056ea: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
80056ec: 683b ldr r3, [r7, #0]
|
|
80056ee: 681b ldr r3, [r3, #0]
|
|
80056f0: 021b lsls r3, r3, #8
|
|
80056f2: 68fa ldr r2, [r7, #12]
|
|
80056f4: 4313 orrs r3, r2
|
|
80056f6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
80056f8: 697b ldr r3, [r7, #20]
|
|
80056fa: f023 0320 bic.w r3, r3, #32
|
|
80056fe: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
8005700: 683b ldr r3, [r7, #0]
|
|
8005702: 689b ldr r3, [r3, #8]
|
|
8005704: 011b lsls r3, r3, #4
|
|
8005706: 697a ldr r2, [r7, #20]
|
|
8005708: 4313 orrs r3, r2
|
|
800570a: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
800570c: 687b ldr r3, [r7, #4]
|
|
800570e: 4a22 ldr r2, [pc, #136] @ (8005798 <TIM_OC2_SetConfig+0xe4>)
|
|
8005710: 4293 cmp r3, r2
|
|
8005712: d003 beq.n 800571c <TIM_OC2_SetConfig+0x68>
|
|
8005714: 687b ldr r3, [r7, #4]
|
|
8005716: 4a21 ldr r2, [pc, #132] @ (800579c <TIM_OC2_SetConfig+0xe8>)
|
|
8005718: 4293 cmp r3, r2
|
|
800571a: d10d bne.n 8005738 <TIM_OC2_SetConfig+0x84>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
800571c: 697b ldr r3, [r7, #20]
|
|
800571e: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8005722: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
8005724: 683b ldr r3, [r7, #0]
|
|
8005726: 68db ldr r3, [r3, #12]
|
|
8005728: 011b lsls r3, r3, #4
|
|
800572a: 697a ldr r2, [r7, #20]
|
|
800572c: 4313 orrs r3, r2
|
|
800572e: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
8005730: 697b ldr r3, [r7, #20]
|
|
8005732: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005736: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8005738: 687b ldr r3, [r7, #4]
|
|
800573a: 4a17 ldr r2, [pc, #92] @ (8005798 <TIM_OC2_SetConfig+0xe4>)
|
|
800573c: 4293 cmp r3, r2
|
|
800573e: d003 beq.n 8005748 <TIM_OC2_SetConfig+0x94>
|
|
8005740: 687b ldr r3, [r7, #4]
|
|
8005742: 4a16 ldr r2, [pc, #88] @ (800579c <TIM_OC2_SetConfig+0xe8>)
|
|
8005744: 4293 cmp r3, r2
|
|
8005746: d113 bne.n 8005770 <TIM_OC2_SetConfig+0xbc>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
8005748: 693b ldr r3, [r7, #16]
|
|
800574a: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
800574e: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
8005750: 693b ldr r3, [r7, #16]
|
|
8005752: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
8005756: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
8005758: 683b ldr r3, [r7, #0]
|
|
800575a: 695b ldr r3, [r3, #20]
|
|
800575c: 009b lsls r3, r3, #2
|
|
800575e: 693a ldr r2, [r7, #16]
|
|
8005760: 4313 orrs r3, r2
|
|
8005762: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
8005764: 683b ldr r3, [r7, #0]
|
|
8005766: 699b ldr r3, [r3, #24]
|
|
8005768: 009b lsls r3, r3, #2
|
|
800576a: 693a ldr r2, [r7, #16]
|
|
800576c: 4313 orrs r3, r2
|
|
800576e: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005770: 687b ldr r3, [r7, #4]
|
|
8005772: 693a ldr r2, [r7, #16]
|
|
8005774: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8005776: 687b ldr r3, [r7, #4]
|
|
8005778: 68fa ldr r2, [r7, #12]
|
|
800577a: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
800577c: 683b ldr r3, [r7, #0]
|
|
800577e: 685a ldr r2, [r3, #4]
|
|
8005780: 687b ldr r3, [r7, #4]
|
|
8005782: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8005784: 687b ldr r3, [r7, #4]
|
|
8005786: 697a ldr r2, [r7, #20]
|
|
8005788: 621a str r2, [r3, #32]
|
|
}
|
|
800578a: bf00 nop
|
|
800578c: 371c adds r7, #28
|
|
800578e: 46bd mov sp, r7
|
|
8005790: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005794: 4770 bx lr
|
|
8005796: bf00 nop
|
|
8005798: 40010000 .word 0x40010000
|
|
800579c: 40010400 .word 0x40010400
|
|
|
|
080057a0 <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
80057a0: b480 push {r7}
|
|
80057a2: b087 sub sp, #28
|
|
80057a4: af00 add r7, sp, #0
|
|
80057a6: 6078 str r0, [r7, #4]
|
|
80057a8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
80057aa: 687b ldr r3, [r7, #4]
|
|
80057ac: 6a1b ldr r3, [r3, #32]
|
|
80057ae: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
80057b0: 687b ldr r3, [r7, #4]
|
|
80057b2: 6a1b ldr r3, [r3, #32]
|
|
80057b4: f423 7280 bic.w r2, r3, #256 @ 0x100
|
|
80057b8: 687b ldr r3, [r7, #4]
|
|
80057ba: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80057bc: 687b ldr r3, [r7, #4]
|
|
80057be: 685b ldr r3, [r3, #4]
|
|
80057c0: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
80057c2: 687b ldr r3, [r7, #4]
|
|
80057c4: 69db ldr r3, [r3, #28]
|
|
80057c6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
80057c8: 68fb ldr r3, [r7, #12]
|
|
80057ca: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80057ce: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
80057d0: 68fb ldr r3, [r7, #12]
|
|
80057d2: f023 0303 bic.w r3, r3, #3
|
|
80057d6: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
80057d8: 683b ldr r3, [r7, #0]
|
|
80057da: 681b ldr r3, [r3, #0]
|
|
80057dc: 68fa ldr r2, [r7, #12]
|
|
80057de: 4313 orrs r3, r2
|
|
80057e0: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
80057e2: 697b ldr r3, [r7, #20]
|
|
80057e4: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
80057e8: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
80057ea: 683b ldr r3, [r7, #0]
|
|
80057ec: 689b ldr r3, [r3, #8]
|
|
80057ee: 021b lsls r3, r3, #8
|
|
80057f0: 697a ldr r2, [r7, #20]
|
|
80057f2: 4313 orrs r3, r2
|
|
80057f4: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
80057f6: 687b ldr r3, [r7, #4]
|
|
80057f8: 4a21 ldr r2, [pc, #132] @ (8005880 <TIM_OC3_SetConfig+0xe0>)
|
|
80057fa: 4293 cmp r3, r2
|
|
80057fc: d003 beq.n 8005806 <TIM_OC3_SetConfig+0x66>
|
|
80057fe: 687b ldr r3, [r7, #4]
|
|
8005800: 4a20 ldr r2, [pc, #128] @ (8005884 <TIM_OC3_SetConfig+0xe4>)
|
|
8005802: 4293 cmp r3, r2
|
|
8005804: d10d bne.n 8005822 <TIM_OC3_SetConfig+0x82>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
8005806: 697b ldr r3, [r7, #20]
|
|
8005808: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
800580c: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
800580e: 683b ldr r3, [r7, #0]
|
|
8005810: 68db ldr r3, [r3, #12]
|
|
8005812: 021b lsls r3, r3, #8
|
|
8005814: 697a ldr r2, [r7, #20]
|
|
8005816: 4313 orrs r3, r2
|
|
8005818: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
800581a: 697b ldr r3, [r7, #20]
|
|
800581c: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8005820: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8005822: 687b ldr r3, [r7, #4]
|
|
8005824: 4a16 ldr r2, [pc, #88] @ (8005880 <TIM_OC3_SetConfig+0xe0>)
|
|
8005826: 4293 cmp r3, r2
|
|
8005828: d003 beq.n 8005832 <TIM_OC3_SetConfig+0x92>
|
|
800582a: 687b ldr r3, [r7, #4]
|
|
800582c: 4a15 ldr r2, [pc, #84] @ (8005884 <TIM_OC3_SetConfig+0xe4>)
|
|
800582e: 4293 cmp r3, r2
|
|
8005830: d113 bne.n 800585a <TIM_OC3_SetConfig+0xba>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
8005832: 693b ldr r3, [r7, #16]
|
|
8005834: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
8005838: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
800583a: 693b ldr r3, [r7, #16]
|
|
800583c: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
8005840: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
8005842: 683b ldr r3, [r7, #0]
|
|
8005844: 695b ldr r3, [r3, #20]
|
|
8005846: 011b lsls r3, r3, #4
|
|
8005848: 693a ldr r2, [r7, #16]
|
|
800584a: 4313 orrs r3, r2
|
|
800584c: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
800584e: 683b ldr r3, [r7, #0]
|
|
8005850: 699b ldr r3, [r3, #24]
|
|
8005852: 011b lsls r3, r3, #4
|
|
8005854: 693a ldr r2, [r7, #16]
|
|
8005856: 4313 orrs r3, r2
|
|
8005858: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800585a: 687b ldr r3, [r7, #4]
|
|
800585c: 693a ldr r2, [r7, #16]
|
|
800585e: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8005860: 687b ldr r3, [r7, #4]
|
|
8005862: 68fa ldr r2, [r7, #12]
|
|
8005864: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
8005866: 683b ldr r3, [r7, #0]
|
|
8005868: 685a ldr r2, [r3, #4]
|
|
800586a: 687b ldr r3, [r7, #4]
|
|
800586c: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800586e: 687b ldr r3, [r7, #4]
|
|
8005870: 697a ldr r2, [r7, #20]
|
|
8005872: 621a str r2, [r3, #32]
|
|
}
|
|
8005874: bf00 nop
|
|
8005876: 371c adds r7, #28
|
|
8005878: 46bd mov sp, r7
|
|
800587a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800587e: 4770 bx lr
|
|
8005880: 40010000 .word 0x40010000
|
|
8005884: 40010400 .word 0x40010400
|
|
|
|
08005888 <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8005888: b480 push {r7}
|
|
800588a: b087 sub sp, #28
|
|
800588c: af00 add r7, sp, #0
|
|
800588e: 6078 str r0, [r7, #4]
|
|
8005890: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8005892: 687b ldr r3, [r7, #4]
|
|
8005894: 6a1b ldr r3, [r3, #32]
|
|
8005896: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
8005898: 687b ldr r3, [r7, #4]
|
|
800589a: 6a1b ldr r3, [r3, #32]
|
|
800589c: f423 5280 bic.w r2, r3, #4096 @ 0x1000
|
|
80058a0: 687b ldr r3, [r7, #4]
|
|
80058a2: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80058a4: 687b ldr r3, [r7, #4]
|
|
80058a6: 685b ldr r3, [r3, #4]
|
|
80058a8: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
80058aa: 687b ldr r3, [r7, #4]
|
|
80058ac: 69db ldr r3, [r3, #28]
|
|
80058ae: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
80058b0: 68fb ldr r3, [r7, #12]
|
|
80058b2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80058b6: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
80058b8: 68fb ldr r3, [r7, #12]
|
|
80058ba: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80058be: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
80058c0: 683b ldr r3, [r7, #0]
|
|
80058c2: 681b ldr r3, [r3, #0]
|
|
80058c4: 021b lsls r3, r3, #8
|
|
80058c6: 68fa ldr r2, [r7, #12]
|
|
80058c8: 4313 orrs r3, r2
|
|
80058ca: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
80058cc: 693b ldr r3, [r7, #16]
|
|
80058ce: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
80058d2: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
80058d4: 683b ldr r3, [r7, #0]
|
|
80058d6: 689b ldr r3, [r3, #8]
|
|
80058d8: 031b lsls r3, r3, #12
|
|
80058da: 693a ldr r2, [r7, #16]
|
|
80058dc: 4313 orrs r3, r2
|
|
80058de: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
80058e0: 687b ldr r3, [r7, #4]
|
|
80058e2: 4a12 ldr r2, [pc, #72] @ (800592c <TIM_OC4_SetConfig+0xa4>)
|
|
80058e4: 4293 cmp r3, r2
|
|
80058e6: d003 beq.n 80058f0 <TIM_OC4_SetConfig+0x68>
|
|
80058e8: 687b ldr r3, [r7, #4]
|
|
80058ea: 4a11 ldr r2, [pc, #68] @ (8005930 <TIM_OC4_SetConfig+0xa8>)
|
|
80058ec: 4293 cmp r3, r2
|
|
80058ee: d109 bne.n 8005904 <TIM_OC4_SetConfig+0x7c>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
80058f0: 697b ldr r3, [r7, #20]
|
|
80058f2: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
80058f6: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
80058f8: 683b ldr r3, [r7, #0]
|
|
80058fa: 695b ldr r3, [r3, #20]
|
|
80058fc: 019b lsls r3, r3, #6
|
|
80058fe: 697a ldr r2, [r7, #20]
|
|
8005900: 4313 orrs r3, r2
|
|
8005902: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005904: 687b ldr r3, [r7, #4]
|
|
8005906: 697a ldr r2, [r7, #20]
|
|
8005908: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
800590a: 687b ldr r3, [r7, #4]
|
|
800590c: 68fa ldr r2, [r7, #12]
|
|
800590e: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
8005910: 683b ldr r3, [r7, #0]
|
|
8005912: 685a ldr r2, [r3, #4]
|
|
8005914: 687b ldr r3, [r7, #4]
|
|
8005916: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8005918: 687b ldr r3, [r7, #4]
|
|
800591a: 693a ldr r2, [r7, #16]
|
|
800591c: 621a str r2, [r3, #32]
|
|
}
|
|
800591e: bf00 nop
|
|
8005920: 371c adds r7, #28
|
|
8005922: 46bd mov sp, r7
|
|
8005924: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005928: 4770 bx lr
|
|
800592a: bf00 nop
|
|
800592c: 40010000 .word 0x40010000
|
|
8005930: 40010400 .word 0x40010400
|
|
|
|
08005934 <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
8005934: b480 push {r7}
|
|
8005936: b085 sub sp, #20
|
|
8005938: af00 add r7, sp, #0
|
|
800593a: 6078 str r0, [r7, #4]
|
|
800593c: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
800593e: 687b ldr r3, [r7, #4]
|
|
8005940: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8005944: 2b01 cmp r3, #1
|
|
8005946: d101 bne.n 800594c <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8005948: 2302 movs r3, #2
|
|
800594a: e05a b.n 8005a02 <HAL_TIMEx_MasterConfigSynchronization+0xce>
|
|
800594c: 687b ldr r3, [r7, #4]
|
|
800594e: 2201 movs r2, #1
|
|
8005950: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005954: 687b ldr r3, [r7, #4]
|
|
8005956: 2202 movs r2, #2
|
|
8005958: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
800595c: 687b ldr r3, [r7, #4]
|
|
800595e: 681b ldr r3, [r3, #0]
|
|
8005960: 685b ldr r3, [r3, #4]
|
|
8005962: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8005964: 687b ldr r3, [r7, #4]
|
|
8005966: 681b ldr r3, [r3, #0]
|
|
8005968: 689b ldr r3, [r3, #8]
|
|
800596a: 60bb str r3, [r7, #8]
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
800596c: 68fb ldr r3, [r7, #12]
|
|
800596e: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005972: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8005974: 683b ldr r3, [r7, #0]
|
|
8005976: 681b ldr r3, [r3, #0]
|
|
8005978: 68fa ldr r2, [r7, #12]
|
|
800597a: 4313 orrs r3, r2
|
|
800597c: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
800597e: 687b ldr r3, [r7, #4]
|
|
8005980: 681b ldr r3, [r3, #0]
|
|
8005982: 68fa ldr r2, [r7, #12]
|
|
8005984: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8005986: 687b ldr r3, [r7, #4]
|
|
8005988: 681b ldr r3, [r3, #0]
|
|
800598a: 4a21 ldr r2, [pc, #132] @ (8005a10 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
|
|
800598c: 4293 cmp r3, r2
|
|
800598e: d022 beq.n 80059d6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005990: 687b ldr r3, [r7, #4]
|
|
8005992: 681b ldr r3, [r3, #0]
|
|
8005994: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8005998: d01d beq.n 80059d6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
800599a: 687b ldr r3, [r7, #4]
|
|
800599c: 681b ldr r3, [r3, #0]
|
|
800599e: 4a1d ldr r2, [pc, #116] @ (8005a14 <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
|
|
80059a0: 4293 cmp r3, r2
|
|
80059a2: d018 beq.n 80059d6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
80059a4: 687b ldr r3, [r7, #4]
|
|
80059a6: 681b ldr r3, [r3, #0]
|
|
80059a8: 4a1b ldr r2, [pc, #108] @ (8005a18 <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
|
|
80059aa: 4293 cmp r3, r2
|
|
80059ac: d013 beq.n 80059d6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
80059ae: 687b ldr r3, [r7, #4]
|
|
80059b0: 681b ldr r3, [r3, #0]
|
|
80059b2: 4a1a ldr r2, [pc, #104] @ (8005a1c <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
|
|
80059b4: 4293 cmp r3, r2
|
|
80059b6: d00e beq.n 80059d6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
80059b8: 687b ldr r3, [r7, #4]
|
|
80059ba: 681b ldr r3, [r3, #0]
|
|
80059bc: 4a18 ldr r2, [pc, #96] @ (8005a20 <HAL_TIMEx_MasterConfigSynchronization+0xec>)
|
|
80059be: 4293 cmp r3, r2
|
|
80059c0: d009 beq.n 80059d6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
80059c2: 687b ldr r3, [r7, #4]
|
|
80059c4: 681b ldr r3, [r3, #0]
|
|
80059c6: 4a17 ldr r2, [pc, #92] @ (8005a24 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
|
|
80059c8: 4293 cmp r3, r2
|
|
80059ca: d004 beq.n 80059d6 <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
80059cc: 687b ldr r3, [r7, #4]
|
|
80059ce: 681b ldr r3, [r3, #0]
|
|
80059d0: 4a15 ldr r2, [pc, #84] @ (8005a28 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
|
|
80059d2: 4293 cmp r3, r2
|
|
80059d4: d10c bne.n 80059f0 <HAL_TIMEx_MasterConfigSynchronization+0xbc>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
80059d6: 68bb ldr r3, [r7, #8]
|
|
80059d8: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
80059dc: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
80059de: 683b ldr r3, [r7, #0]
|
|
80059e0: 685b ldr r3, [r3, #4]
|
|
80059e2: 68ba ldr r2, [r7, #8]
|
|
80059e4: 4313 orrs r3, r2
|
|
80059e6: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
80059e8: 687b ldr r3, [r7, #4]
|
|
80059ea: 681b ldr r3, [r3, #0]
|
|
80059ec: 68ba ldr r2, [r7, #8]
|
|
80059ee: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80059f0: 687b ldr r3, [r7, #4]
|
|
80059f2: 2201 movs r2, #1
|
|
80059f4: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
80059f8: 687b ldr r3, [r7, #4]
|
|
80059fa: 2200 movs r2, #0
|
|
80059fc: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
8005a00: 2300 movs r3, #0
|
|
}
|
|
8005a02: 4618 mov r0, r3
|
|
8005a04: 3714 adds r7, #20
|
|
8005a06: 46bd mov sp, r7
|
|
8005a08: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005a0c: 4770 bx lr
|
|
8005a0e: bf00 nop
|
|
8005a10: 40010000 .word 0x40010000
|
|
8005a14: 40000400 .word 0x40000400
|
|
8005a18: 40000800 .word 0x40000800
|
|
8005a1c: 40000c00 .word 0x40000c00
|
|
8005a20: 40010400 .word 0x40010400
|
|
8005a24: 40014000 .word 0x40014000
|
|
8005a28: 40001800 .word 0x40001800
|
|
|
|
08005a2c <HAL_UART_Init>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8005a2c: b580 push {r7, lr}
|
|
8005a2e: b082 sub sp, #8
|
|
8005a30: af00 add r7, sp, #0
|
|
8005a32: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8005a34: 687b ldr r3, [r7, #4]
|
|
8005a36: 2b00 cmp r3, #0
|
|
8005a38: d101 bne.n 8005a3e <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8005a3a: 2301 movs r3, #1
|
|
8005a3c: e042 b.n 8005ac4 <HAL_UART_Init+0x98>
|
|
assert_param(IS_UART_INSTANCE(huart->Instance));
|
|
}
|
|
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
|
|
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8005a3e: 687b ldr r3, [r7, #4]
|
|
8005a40: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8005a44: b2db uxtb r3, r3
|
|
8005a46: 2b00 cmp r3, #0
|
|
8005a48: d106 bne.n 8005a58 <HAL_UART_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8005a4a: 687b ldr r3, [r7, #4]
|
|
8005a4c: 2200 movs r2, #0
|
|
8005a4e: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8005a52: 6878 ldr r0, [r7, #4]
|
|
8005a54: f7fb fc8e bl 8001374 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8005a58: 687b ldr r3, [r7, #4]
|
|
8005a5a: 2224 movs r2, #36 @ 0x24
|
|
8005a5c: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_UART_DISABLE(huart);
|
|
8005a60: 687b ldr r3, [r7, #4]
|
|
8005a62: 681b ldr r3, [r3, #0]
|
|
8005a64: 68da ldr r2, [r3, #12]
|
|
8005a66: 687b ldr r3, [r7, #4]
|
|
8005a68: 681b ldr r3, [r3, #0]
|
|
8005a6a: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
8005a6e: 60da str r2, [r3, #12]
|
|
|
|
/* Set the UART Communication parameters */
|
|
UART_SetConfig(huart);
|
|
8005a70: 6878 ldr r0, [r7, #4]
|
|
8005a72: f000 ff6d bl 8006950 <UART_SetConfig>
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8005a76: 687b ldr r3, [r7, #4]
|
|
8005a78: 681b ldr r3, [r3, #0]
|
|
8005a7a: 691a ldr r2, [r3, #16]
|
|
8005a7c: 687b ldr r3, [r7, #4]
|
|
8005a7e: 681b ldr r3, [r3, #0]
|
|
8005a80: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
8005a84: 611a str r2, [r3, #16]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8005a86: 687b ldr r3, [r7, #4]
|
|
8005a88: 681b ldr r3, [r3, #0]
|
|
8005a8a: 695a ldr r2, [r3, #20]
|
|
8005a8c: 687b ldr r3, [r7, #4]
|
|
8005a8e: 681b ldr r3, [r3, #0]
|
|
8005a90: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
8005a94: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the peripheral */
|
|
__HAL_UART_ENABLE(huart);
|
|
8005a96: 687b ldr r3, [r7, #4]
|
|
8005a98: 681b ldr r3, [r3, #0]
|
|
8005a9a: 68da ldr r2, [r3, #12]
|
|
8005a9c: 687b ldr r3, [r7, #4]
|
|
8005a9e: 681b ldr r3, [r3, #0]
|
|
8005aa0: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
8005aa4: 60da str r2, [r3, #12]
|
|
|
|
/* Initialize the UART state */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8005aa6: 687b ldr r3, [r7, #4]
|
|
8005aa8: 2200 movs r2, #0
|
|
8005aaa: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005aac: 687b ldr r3, [r7, #4]
|
|
8005aae: 2220 movs r2, #32
|
|
8005ab0: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8005ab4: 687b ldr r3, [r7, #4]
|
|
8005ab6: 2220 movs r2, #32
|
|
8005ab8: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8005abc: 687b ldr r3, [r7, #4]
|
|
8005abe: 2200 movs r2, #0
|
|
8005ac0: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_OK;
|
|
8005ac2: 2300 movs r3, #0
|
|
}
|
|
8005ac4: 4618 mov r0, r3
|
|
8005ac6: 3708 adds r7, #8
|
|
8005ac8: 46bd mov sp, r7
|
|
8005aca: bd80 pop {r7, pc}
|
|
|
|
08005acc <HAL_UART_Transmit_DMA>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
|
|
{
|
|
8005acc: b580 push {r7, lr}
|
|
8005ace: b08c sub sp, #48 @ 0x30
|
|
8005ad0: af00 add r7, sp, #0
|
|
8005ad2: 60f8 str r0, [r7, #12]
|
|
8005ad4: 60b9 str r1, [r7, #8]
|
|
8005ad6: 4613 mov r3, r2
|
|
8005ad8: 80fb strh r3, [r7, #6]
|
|
const uint32_t *tmp;
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8005ada: 68fb ldr r3, [r7, #12]
|
|
8005adc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8005ae0: b2db uxtb r3, r3
|
|
8005ae2: 2b20 cmp r3, #32
|
|
8005ae4: d162 bne.n 8005bac <HAL_UART_Transmit_DMA+0xe0>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8005ae6: 68bb ldr r3, [r7, #8]
|
|
8005ae8: 2b00 cmp r3, #0
|
|
8005aea: d002 beq.n 8005af2 <HAL_UART_Transmit_DMA+0x26>
|
|
8005aec: 88fb ldrh r3, [r7, #6]
|
|
8005aee: 2b00 cmp r3, #0
|
|
8005af0: d101 bne.n 8005af6 <HAL_UART_Transmit_DMA+0x2a>
|
|
{
|
|
return HAL_ERROR;
|
|
8005af2: 2301 movs r3, #1
|
|
8005af4: e05b b.n 8005bae <HAL_UART_Transmit_DMA+0xe2>
|
|
}
|
|
|
|
huart->pTxBuffPtr = pData;
|
|
8005af6: 68ba ldr r2, [r7, #8]
|
|
8005af8: 68fb ldr r3, [r7, #12]
|
|
8005afa: 621a str r2, [r3, #32]
|
|
huart->TxXferSize = Size;
|
|
8005afc: 68fb ldr r3, [r7, #12]
|
|
8005afe: 88fa ldrh r2, [r7, #6]
|
|
8005b00: 849a strh r2, [r3, #36] @ 0x24
|
|
huart->TxXferCount = Size;
|
|
8005b02: 68fb ldr r3, [r7, #12]
|
|
8005b04: 88fa ldrh r2, [r7, #6]
|
|
8005b06: 84da strh r2, [r3, #38] @ 0x26
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8005b08: 68fb ldr r3, [r7, #12]
|
|
8005b0a: 2200 movs r2, #0
|
|
8005b0c: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
8005b0e: 68fb ldr r3, [r7, #12]
|
|
8005b10: 2221 movs r2, #33 @ 0x21
|
|
8005b12: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Set the UART DMA transfer complete callback */
|
|
huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
|
|
8005b16: 68fb ldr r3, [r7, #12]
|
|
8005b18: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005b1a: 4a27 ldr r2, [pc, #156] @ (8005bb8 <HAL_UART_Transmit_DMA+0xec>)
|
|
8005b1c: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Set the UART DMA Half transfer complete callback */
|
|
huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
|
|
8005b1e: 68fb ldr r3, [r7, #12]
|
|
8005b20: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005b22: 4a26 ldr r2, [pc, #152] @ (8005bbc <HAL_UART_Transmit_DMA+0xf0>)
|
|
8005b24: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set the DMA error callback */
|
|
huart->hdmatx->XferErrorCallback = UART_DMAError;
|
|
8005b26: 68fb ldr r3, [r7, #12]
|
|
8005b28: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005b2a: 4a25 ldr r2, [pc, #148] @ (8005bc0 <HAL_UART_Transmit_DMA+0xf4>)
|
|
8005b2c: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Set the DMA abort callback */
|
|
huart->hdmatx->XferAbortCallback = NULL;
|
|
8005b2e: 68fb ldr r3, [r7, #12]
|
|
8005b30: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005b32: 2200 movs r2, #0
|
|
8005b34: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Enable the UART transmit DMA stream */
|
|
tmp = (const uint32_t *)&pData;
|
|
8005b36: f107 0308 add.w r3, r7, #8
|
|
8005b3a: 62fb str r3, [r7, #44] @ 0x2c
|
|
if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK)
|
|
8005b3c: 68fb ldr r3, [r7, #12]
|
|
8005b3e: 6b98 ldr r0, [r3, #56] @ 0x38
|
|
8005b40: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8005b42: 6819 ldr r1, [r3, #0]
|
|
8005b44: 68fb ldr r3, [r7, #12]
|
|
8005b46: 681b ldr r3, [r3, #0]
|
|
8005b48: 3304 adds r3, #4
|
|
8005b4a: 461a mov r2, r3
|
|
8005b4c: 88fb ldrh r3, [r7, #6]
|
|
8005b4e: f7fc f953 bl 8001df8 <HAL_DMA_Start_IT>
|
|
8005b52: 4603 mov r3, r0
|
|
8005b54: 2b00 cmp r3, #0
|
|
8005b56: d008 beq.n 8005b6a <HAL_UART_Transmit_DMA+0x9e>
|
|
{
|
|
/* Set error code to DMA */
|
|
huart->ErrorCode = HAL_UART_ERROR_DMA;
|
|
8005b58: 68fb ldr r3, [r7, #12]
|
|
8005b5a: 2210 movs r2, #16
|
|
8005b5c: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Restore huart->gState to ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005b5e: 68fb ldr r3, [r7, #12]
|
|
8005b60: 2220 movs r2, #32
|
|
8005b62: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
return HAL_ERROR;
|
|
8005b66: 2301 movs r3, #1
|
|
8005b68: e021 b.n 8005bae <HAL_UART_Transmit_DMA+0xe2>
|
|
}
|
|
/* Clear the TC flag in the SR register by writing 0 to it */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
|
|
8005b6a: 68fb ldr r3, [r7, #12]
|
|
8005b6c: 681b ldr r3, [r3, #0]
|
|
8005b6e: f06f 0240 mvn.w r2, #64 @ 0x40
|
|
8005b72: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the DMA transfer for transmit request by setting the DMAT bit
|
|
in the UART CR3 register */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
|
8005b74: 68fb ldr r3, [r7, #12]
|
|
8005b76: 681b ldr r3, [r3, #0]
|
|
8005b78: 3314 adds r3, #20
|
|
8005b7a: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005b7c: 69bb ldr r3, [r7, #24]
|
|
8005b7e: e853 3f00 ldrex r3, [r3]
|
|
8005b82: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8005b84: 697b ldr r3, [r7, #20]
|
|
8005b86: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8005b8a: 62bb str r3, [r7, #40] @ 0x28
|
|
8005b8c: 68fb ldr r3, [r7, #12]
|
|
8005b8e: 681b ldr r3, [r3, #0]
|
|
8005b90: 3314 adds r3, #20
|
|
8005b92: 6aba ldr r2, [r7, #40] @ 0x28
|
|
8005b94: 627a str r2, [r7, #36] @ 0x24
|
|
8005b96: 623b str r3, [r7, #32]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005b98: 6a39 ldr r1, [r7, #32]
|
|
8005b9a: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8005b9c: e841 2300 strex r3, r2, [r1]
|
|
8005ba0: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8005ba2: 69fb ldr r3, [r7, #28]
|
|
8005ba4: 2b00 cmp r3, #0
|
|
8005ba6: d1e5 bne.n 8005b74 <HAL_UART_Transmit_DMA+0xa8>
|
|
|
|
return HAL_OK;
|
|
8005ba8: 2300 movs r3, #0
|
|
8005baa: e000 b.n 8005bae <HAL_UART_Transmit_DMA+0xe2>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8005bac: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8005bae: 4618 mov r0, r3
|
|
8005bb0: 3730 adds r7, #48 @ 0x30
|
|
8005bb2: 46bd mov sp, r7
|
|
8005bb4: bd80 pop {r7, pc}
|
|
8005bb6: bf00 nop
|
|
8005bb8: 080061cd .word 0x080061cd
|
|
8005bbc: 08006267 .word 0x08006267
|
|
8005bc0: 080063eb .word 0x080063eb
|
|
|
|
08005bc4 <HAL_UART_Receive_DMA>:
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
8005bc4: b580 push {r7, lr}
|
|
8005bc6: b084 sub sp, #16
|
|
8005bc8: af00 add r7, sp, #0
|
|
8005bca: 60f8 str r0, [r7, #12]
|
|
8005bcc: 60b9 str r1, [r7, #8]
|
|
8005bce: 4613 mov r3, r2
|
|
8005bd0: 80fb strh r3, [r7, #6]
|
|
/* Check that a Rx process is not already ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
8005bd2: 68fb ldr r3, [r7, #12]
|
|
8005bd4: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
8005bd8: b2db uxtb r3, r3
|
|
8005bda: 2b20 cmp r3, #32
|
|
8005bdc: d112 bne.n 8005c04 <HAL_UART_Receive_DMA+0x40>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8005bde: 68bb ldr r3, [r7, #8]
|
|
8005be0: 2b00 cmp r3, #0
|
|
8005be2: d002 beq.n 8005bea <HAL_UART_Receive_DMA+0x26>
|
|
8005be4: 88fb ldrh r3, [r7, #6]
|
|
8005be6: 2b00 cmp r3, #0
|
|
8005be8: d101 bne.n 8005bee <HAL_UART_Receive_DMA+0x2a>
|
|
{
|
|
return HAL_ERROR;
|
|
8005bea: 2301 movs r3, #1
|
|
8005bec: e00b b.n 8005c06 <HAL_UART_Receive_DMA+0x42>
|
|
}
|
|
|
|
/* Set Reception type to Standard reception */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8005bee: 68fb ldr r3, [r7, #12]
|
|
8005bf0: 2200 movs r2, #0
|
|
8005bf2: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
return (UART_Start_Receive_DMA(huart, pData, Size));
|
|
8005bf4: 88fb ldrh r3, [r7, #6]
|
|
8005bf6: 461a mov r2, r3
|
|
8005bf8: 68b9 ldr r1, [r7, #8]
|
|
8005bfa: 68f8 ldr r0, [r7, #12]
|
|
8005bfc: f000 fc40 bl 8006480 <UART_Start_Receive_DMA>
|
|
8005c00: 4603 mov r3, r0
|
|
8005c02: e000 b.n 8005c06 <HAL_UART_Receive_DMA+0x42>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8005c04: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8005c06: 4618 mov r0, r3
|
|
8005c08: 3710 adds r7, #16
|
|
8005c0a: 46bd mov sp, r7
|
|
8005c0c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08005c10 <HAL_UART_IRQHandler>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|
{
|
|
8005c10: b580 push {r7, lr}
|
|
8005c12: b0ba sub sp, #232 @ 0xe8
|
|
8005c14: af00 add r7, sp, #0
|
|
8005c16: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(huart->Instance->SR);
|
|
8005c18: 687b ldr r3, [r7, #4]
|
|
8005c1a: 681b ldr r3, [r3, #0]
|
|
8005c1c: 681b ldr r3, [r3, #0]
|
|
8005c1e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
8005c22: 687b ldr r3, [r7, #4]
|
|
8005c24: 681b ldr r3, [r3, #0]
|
|
8005c26: 68db ldr r3, [r3, #12]
|
|
8005c28: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
8005c2c: 687b ldr r3, [r7, #4]
|
|
8005c2e: 681b ldr r3, [r3, #0]
|
|
8005c30: 695b ldr r3, [r3, #20]
|
|
8005c32: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
uint32_t errorflags = 0x00U;
|
|
8005c36: 2300 movs r3, #0
|
|
8005c38: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
uint32_t dmarequest = 0x00U;
|
|
8005c3c: 2300 movs r3, #0
|
|
8005c3e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
|
|
/* If no error occurs */
|
|
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
|
|
8005c42: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005c46: f003 030f and.w r3, r3, #15
|
|
8005c4a: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
if (errorflags == RESET)
|
|
8005c4e: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
8005c52: 2b00 cmp r3, #0
|
|
8005c54: d10f bne.n 8005c76 <HAL_UART_IRQHandler+0x66>
|
|
{
|
|
/* UART in mode Receiver -------------------------------------------------*/
|
|
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
|
|
8005c56: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005c5a: f003 0320 and.w r3, r3, #32
|
|
8005c5e: 2b00 cmp r3, #0
|
|
8005c60: d009 beq.n 8005c76 <HAL_UART_IRQHandler+0x66>
|
|
8005c62: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005c66: f003 0320 and.w r3, r3, #32
|
|
8005c6a: 2b00 cmp r3, #0
|
|
8005c6c: d003 beq.n 8005c76 <HAL_UART_IRQHandler+0x66>
|
|
{
|
|
UART_Receive_IT(huart);
|
|
8005c6e: 6878 ldr r0, [r7, #4]
|
|
8005c70: f000 fdb0 bl 80067d4 <UART_Receive_IT>
|
|
return;
|
|
8005c74: e273 b.n 800615e <HAL_UART_IRQHandler+0x54e>
|
|
}
|
|
}
|
|
|
|
/* If some errors occur */
|
|
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET)
|
|
8005c76: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
8005c7a: 2b00 cmp r3, #0
|
|
8005c7c: f000 80de beq.w 8005e3c <HAL_UART_IRQHandler+0x22c>
|
|
8005c80: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8005c84: f003 0301 and.w r3, r3, #1
|
|
8005c88: 2b00 cmp r3, #0
|
|
8005c8a: d106 bne.n 8005c9a <HAL_UART_IRQHandler+0x8a>
|
|
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
|
|
8005c8c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005c90: f403 7390 and.w r3, r3, #288 @ 0x120
|
|
8005c94: 2b00 cmp r3, #0
|
|
8005c96: f000 80d1 beq.w 8005e3c <HAL_UART_IRQHandler+0x22c>
|
|
{
|
|
/* UART parity error interrupt occurred ----------------------------------*/
|
|
if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
|
|
8005c9a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005c9e: f003 0301 and.w r3, r3, #1
|
|
8005ca2: 2b00 cmp r3, #0
|
|
8005ca4: d00b beq.n 8005cbe <HAL_UART_IRQHandler+0xae>
|
|
8005ca6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005caa: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005cae: 2b00 cmp r3, #0
|
|
8005cb0: d005 beq.n 8005cbe <HAL_UART_IRQHandler+0xae>
|
|
{
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
8005cb2: 687b ldr r3, [r7, #4]
|
|
8005cb4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005cb6: f043 0201 orr.w r2, r3, #1
|
|
8005cba: 687b ldr r3, [r7, #4]
|
|
8005cbc: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* UART noise error interrupt occurred -----------------------------------*/
|
|
if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
|
|
8005cbe: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005cc2: f003 0304 and.w r3, r3, #4
|
|
8005cc6: 2b00 cmp r3, #0
|
|
8005cc8: d00b beq.n 8005ce2 <HAL_UART_IRQHandler+0xd2>
|
|
8005cca: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8005cce: f003 0301 and.w r3, r3, #1
|
|
8005cd2: 2b00 cmp r3, #0
|
|
8005cd4: d005 beq.n 8005ce2 <HAL_UART_IRQHandler+0xd2>
|
|
{
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
8005cd6: 687b ldr r3, [r7, #4]
|
|
8005cd8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005cda: f043 0202 orr.w r2, r3, #2
|
|
8005cde: 687b ldr r3, [r7, #4]
|
|
8005ce0: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* UART frame error interrupt occurred -----------------------------------*/
|
|
if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
|
|
8005ce2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005ce6: f003 0302 and.w r3, r3, #2
|
|
8005cea: 2b00 cmp r3, #0
|
|
8005cec: d00b beq.n 8005d06 <HAL_UART_IRQHandler+0xf6>
|
|
8005cee: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8005cf2: f003 0301 and.w r3, r3, #1
|
|
8005cf6: 2b00 cmp r3, #0
|
|
8005cf8: d005 beq.n 8005d06 <HAL_UART_IRQHandler+0xf6>
|
|
{
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
8005cfa: 687b ldr r3, [r7, #4]
|
|
8005cfc: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005cfe: f043 0204 orr.w r2, r3, #4
|
|
8005d02: 687b ldr r3, [r7, #4]
|
|
8005d04: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* UART Over-Run interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET)
|
|
8005d06: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005d0a: f003 0308 and.w r3, r3, #8
|
|
8005d0e: 2b00 cmp r3, #0
|
|
8005d10: d011 beq.n 8005d36 <HAL_UART_IRQHandler+0x126>
|
|
8005d12: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005d16: f003 0320 and.w r3, r3, #32
|
|
8005d1a: 2b00 cmp r3, #0
|
|
8005d1c: d105 bne.n 8005d2a <HAL_UART_IRQHandler+0x11a>
|
|
|| ((cr3its & USART_CR3_EIE) != RESET)))
|
|
8005d1e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8005d22: f003 0301 and.w r3, r3, #1
|
|
8005d26: 2b00 cmp r3, #0
|
|
8005d28: d005 beq.n 8005d36 <HAL_UART_IRQHandler+0x126>
|
|
{
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
|
8005d2a: 687b ldr r3, [r7, #4]
|
|
8005d2c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005d2e: f043 0208 orr.w r2, r3, #8
|
|
8005d32: 687b ldr r3, [r7, #4]
|
|
8005d34: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be --------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
8005d36: 687b ldr r3, [r7, #4]
|
|
8005d38: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005d3a: 2b00 cmp r3, #0
|
|
8005d3c: f000 820a beq.w 8006154 <HAL_UART_IRQHandler+0x544>
|
|
{
|
|
/* UART in mode Receiver -----------------------------------------------*/
|
|
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
|
|
8005d40: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005d44: f003 0320 and.w r3, r3, #32
|
|
8005d48: 2b00 cmp r3, #0
|
|
8005d4a: d008 beq.n 8005d5e <HAL_UART_IRQHandler+0x14e>
|
|
8005d4c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005d50: f003 0320 and.w r3, r3, #32
|
|
8005d54: 2b00 cmp r3, #0
|
|
8005d56: d002 beq.n 8005d5e <HAL_UART_IRQHandler+0x14e>
|
|
{
|
|
UART_Receive_IT(huart);
|
|
8005d58: 6878 ldr r0, [r7, #4]
|
|
8005d5a: f000 fd3b bl 80067d4 <UART_Receive_IT>
|
|
}
|
|
|
|
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
|
|
consider error as blocking */
|
|
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8005d5e: 687b ldr r3, [r7, #4]
|
|
8005d60: 681b ldr r3, [r3, #0]
|
|
8005d62: 695b ldr r3, [r3, #20]
|
|
8005d64: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005d68: 2b40 cmp r3, #64 @ 0x40
|
|
8005d6a: bf0c ite eq
|
|
8005d6c: 2301 moveq r3, #1
|
|
8005d6e: 2300 movne r3, #0
|
|
8005d70: b2db uxtb r3, r3
|
|
8005d72: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
|
|
8005d76: 687b ldr r3, [r7, #4]
|
|
8005d78: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8005d7a: f003 0308 and.w r3, r3, #8
|
|
8005d7e: 2b00 cmp r3, #0
|
|
8005d80: d103 bne.n 8005d8a <HAL_UART_IRQHandler+0x17a>
|
|
8005d82: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
|
|
8005d86: 2b00 cmp r3, #0
|
|
8005d88: d04f beq.n 8005e2a <HAL_UART_IRQHandler+0x21a>
|
|
{
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8005d8a: 6878 ldr r0, [r7, #4]
|
|
8005d8c: f000 fc46 bl 800661c <UART_EndRxTransfer>
|
|
|
|
/* Disable the UART DMA Rx request if enabled */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005d90: 687b ldr r3, [r7, #4]
|
|
8005d92: 681b ldr r3, [r3, #0]
|
|
8005d94: 695b ldr r3, [r3, #20]
|
|
8005d96: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005d9a: 2b40 cmp r3, #64 @ 0x40
|
|
8005d9c: d141 bne.n 8005e22 <HAL_UART_IRQHandler+0x212>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8005d9e: 687b ldr r3, [r7, #4]
|
|
8005da0: 681b ldr r3, [r3, #0]
|
|
8005da2: 3314 adds r3, #20
|
|
8005da4: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005da8: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
8005dac: e853 3f00 ldrex r3, [r3]
|
|
8005db0: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
return(result);
|
|
8005db4: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8005db8: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005dbc: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
8005dc0: 687b ldr r3, [r7, #4]
|
|
8005dc2: 681b ldr r3, [r3, #0]
|
|
8005dc4: 3314 adds r3, #20
|
|
8005dc6: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
|
|
8005dca: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
|
|
8005dce: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005dd2: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
|
|
8005dd6: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
|
|
8005dda: e841 2300 strex r3, r2, [r1]
|
|
8005dde: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
return(result);
|
|
8005de2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8005de6: 2b00 cmp r3, #0
|
|
8005de8: d1d9 bne.n 8005d9e <HAL_UART_IRQHandler+0x18e>
|
|
|
|
/* Abort the UART DMA Rx stream */
|
|
if (huart->hdmarx != NULL)
|
|
8005dea: 687b ldr r3, [r7, #4]
|
|
8005dec: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005dee: 2b00 cmp r3, #0
|
|
8005df0: d013 beq.n 8005e1a <HAL_UART_IRQHandler+0x20a>
|
|
{
|
|
/* Set the UART DMA Abort callback :
|
|
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
|
8005df2: 687b ldr r3, [r7, #4]
|
|
8005df4: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005df6: 4a8a ldr r2, [pc, #552] @ (8006020 <HAL_UART_IRQHandler+0x410>)
|
|
8005df8: 651a str r2, [r3, #80] @ 0x50
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
|
8005dfa: 687b ldr r3, [r7, #4]
|
|
8005dfc: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005dfe: 4618 mov r0, r3
|
|
8005e00: f7fc f8c2 bl 8001f88 <HAL_DMA_Abort_IT>
|
|
8005e04: 4603 mov r3, r0
|
|
8005e06: 2b00 cmp r3, #0
|
|
8005e08: d016 beq.n 8005e38 <HAL_UART_IRQHandler+0x228>
|
|
{
|
|
/* Call Directly XferAbortCallback function in case of error */
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
|
8005e0a: 687b ldr r3, [r7, #4]
|
|
8005e0c: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005e0e: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8005e10: 687a ldr r2, [r7, #4]
|
|
8005e12: 6bd2 ldr r2, [r2, #60] @ 0x3c
|
|
8005e14: 4610 mov r0, r2
|
|
8005e16: 4798 blx r3
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005e18: e00e b.n 8005e38 <HAL_UART_IRQHandler+0x228>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8005e1a: 6878 ldr r0, [r7, #4]
|
|
8005e1c: f000 f9c0 bl 80061a0 <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005e20: e00a b.n 8005e38 <HAL_UART_IRQHandler+0x228>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8005e22: 6878 ldr r0, [r7, #4]
|
|
8005e24: f000 f9bc bl 80061a0 <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005e28: e006 b.n 8005e38 <HAL_UART_IRQHandler+0x228>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8005e2a: 6878 ldr r0, [r7, #4]
|
|
8005e2c: f000 f9b8 bl 80061a0 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8005e30: 687b ldr r3, [r7, #4]
|
|
8005e32: 2200 movs r2, #0
|
|
8005e34: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
}
|
|
return;
|
|
8005e36: e18d b.n 8006154 <HAL_UART_IRQHandler+0x544>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005e38: bf00 nop
|
|
return;
|
|
8005e3a: e18b b.n 8006154 <HAL_UART_IRQHandler+0x544>
|
|
} /* End if some error occurs */
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8005e3c: 687b ldr r3, [r7, #4]
|
|
8005e3e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8005e40: 2b01 cmp r3, #1
|
|
8005e42: f040 8167 bne.w 8006114 <HAL_UART_IRQHandler+0x504>
|
|
&& ((isrflags & USART_SR_IDLE) != 0U)
|
|
8005e46: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005e4a: f003 0310 and.w r3, r3, #16
|
|
8005e4e: 2b00 cmp r3, #0
|
|
8005e50: f000 8160 beq.w 8006114 <HAL_UART_IRQHandler+0x504>
|
|
&& ((cr1its & USART_CR1_IDLEIE) != 0U))
|
|
8005e54: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005e58: f003 0310 and.w r3, r3, #16
|
|
8005e5c: 2b00 cmp r3, #0
|
|
8005e5e: f000 8159 beq.w 8006114 <HAL_UART_IRQHandler+0x504>
|
|
{
|
|
__HAL_UART_CLEAR_IDLEFLAG(huart);
|
|
8005e62: 2300 movs r3, #0
|
|
8005e64: 60bb str r3, [r7, #8]
|
|
8005e66: 687b ldr r3, [r7, #4]
|
|
8005e68: 681b ldr r3, [r3, #0]
|
|
8005e6a: 681b ldr r3, [r3, #0]
|
|
8005e6c: 60bb str r3, [r7, #8]
|
|
8005e6e: 687b ldr r3, [r7, #4]
|
|
8005e70: 681b ldr r3, [r3, #0]
|
|
8005e72: 685b ldr r3, [r3, #4]
|
|
8005e74: 60bb str r3, [r7, #8]
|
|
8005e76: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Check if DMA mode is enabled in UART */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005e78: 687b ldr r3, [r7, #4]
|
|
8005e7a: 681b ldr r3, [r3, #0]
|
|
8005e7c: 695b ldr r3, [r3, #20]
|
|
8005e7e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005e82: 2b40 cmp r3, #64 @ 0x40
|
|
8005e84: f040 80ce bne.w 8006024 <HAL_UART_IRQHandler+0x414>
|
|
{
|
|
/* DMA mode enabled */
|
|
/* Check received length : If all expected data are received, do nothing,
|
|
(DMA cplt callback will be called).
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
|
8005e88: 687b ldr r3, [r7, #4]
|
|
8005e8a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005e8c: 681b ldr r3, [r3, #0]
|
|
8005e8e: 685b ldr r3, [r3, #4]
|
|
8005e90: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
|
|
if ((nb_remaining_rx_data > 0U)
|
|
8005e94: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
|
|
8005e98: 2b00 cmp r3, #0
|
|
8005e9a: f000 80a9 beq.w 8005ff0 <HAL_UART_IRQHandler+0x3e0>
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
8005e9e: 687b ldr r3, [r7, #4]
|
|
8005ea0: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8005ea2: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8005ea6: 429a cmp r2, r3
|
|
8005ea8: f080 80a2 bcs.w 8005ff0 <HAL_UART_IRQHandler+0x3e0>
|
|
{
|
|
/* Reception is not complete */
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
8005eac: 687b ldr r3, [r7, #4]
|
|
8005eae: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8005eb2: 85da strh r2, [r3, #46] @ 0x2e
|
|
|
|
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
|
|
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
|
|
8005eb4: 687b ldr r3, [r7, #4]
|
|
8005eb6: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005eb8: 69db ldr r3, [r3, #28]
|
|
8005eba: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8005ebe: f000 8088 beq.w 8005fd2 <HAL_UART_IRQHandler+0x3c2>
|
|
{
|
|
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8005ec2: 687b ldr r3, [r7, #4]
|
|
8005ec4: 681b ldr r3, [r3, #0]
|
|
8005ec6: 330c adds r3, #12
|
|
8005ec8: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005ecc: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
8005ed0: e853 3f00 ldrex r3, [r3]
|
|
8005ed4: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
return(result);
|
|
8005ed8: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
8005edc: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8005ee0: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
8005ee4: 687b ldr r3, [r7, #4]
|
|
8005ee6: 681b ldr r3, [r3, #0]
|
|
8005ee8: 330c adds r3, #12
|
|
8005eea: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8
|
|
8005eee: f8c7 2094 str.w r2, [r7, #148] @ 0x94
|
|
8005ef2: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005ef6: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
|
|
8005efa: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
|
|
8005efe: e841 2300 strex r3, r2, [r1]
|
|
8005f02: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
return(result);
|
|
8005f06: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8005f0a: 2b00 cmp r3, #0
|
|
8005f0c: d1d9 bne.n 8005ec2 <HAL_UART_IRQHandler+0x2b2>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8005f0e: 687b ldr r3, [r7, #4]
|
|
8005f10: 681b ldr r3, [r3, #0]
|
|
8005f12: 3314 adds r3, #20
|
|
8005f14: 677b str r3, [r7, #116] @ 0x74
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005f16: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8005f18: e853 3f00 ldrex r3, [r3]
|
|
8005f1c: 673b str r3, [r7, #112] @ 0x70
|
|
return(result);
|
|
8005f1e: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8005f20: f023 0301 bic.w r3, r3, #1
|
|
8005f24: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8005f28: 687b ldr r3, [r7, #4]
|
|
8005f2a: 681b ldr r3, [r3, #0]
|
|
8005f2c: 3314 adds r3, #20
|
|
8005f2e: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
8005f32: f8c7 2080 str.w r2, [r7, #128] @ 0x80
|
|
8005f36: 67fb str r3, [r7, #124] @ 0x7c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005f38: 6ff9 ldr r1, [r7, #124] @ 0x7c
|
|
8005f3a: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
|
|
8005f3e: e841 2300 strex r3, r2, [r1]
|
|
8005f42: 67bb str r3, [r7, #120] @ 0x78
|
|
return(result);
|
|
8005f44: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8005f46: 2b00 cmp r3, #0
|
|
8005f48: d1e1 bne.n 8005f0e <HAL_UART_IRQHandler+0x2fe>
|
|
|
|
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8005f4a: 687b ldr r3, [r7, #4]
|
|
8005f4c: 681b ldr r3, [r3, #0]
|
|
8005f4e: 3314 adds r3, #20
|
|
8005f50: 663b str r3, [r7, #96] @ 0x60
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005f52: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8005f54: e853 3f00 ldrex r3, [r3]
|
|
8005f58: 65fb str r3, [r7, #92] @ 0x5c
|
|
return(result);
|
|
8005f5a: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8005f5c: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005f60: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
8005f64: 687b ldr r3, [r7, #4]
|
|
8005f66: 681b ldr r3, [r3, #0]
|
|
8005f68: 3314 adds r3, #20
|
|
8005f6a: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
|
|
8005f6e: 66fa str r2, [r7, #108] @ 0x6c
|
|
8005f70: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005f72: 6eb9 ldr r1, [r7, #104] @ 0x68
|
|
8005f74: 6efa ldr r2, [r7, #108] @ 0x6c
|
|
8005f76: e841 2300 strex r3, r2, [r1]
|
|
8005f7a: 667b str r3, [r7, #100] @ 0x64
|
|
return(result);
|
|
8005f7c: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8005f7e: 2b00 cmp r3, #0
|
|
8005f80: d1e3 bne.n 8005f4a <HAL_UART_IRQHandler+0x33a>
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8005f82: 687b ldr r3, [r7, #4]
|
|
8005f84: 2220 movs r2, #32
|
|
8005f86: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8005f8a: 687b ldr r3, [r7, #4]
|
|
8005f8c: 2200 movs r2, #0
|
|
8005f8e: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8005f90: 687b ldr r3, [r7, #4]
|
|
8005f92: 681b ldr r3, [r3, #0]
|
|
8005f94: 330c adds r3, #12
|
|
8005f96: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005f98: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8005f9a: e853 3f00 ldrex r3, [r3]
|
|
8005f9e: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
8005fa0: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8005fa2: f023 0310 bic.w r3, r3, #16
|
|
8005fa6: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
8005faa: 687b ldr r3, [r7, #4]
|
|
8005fac: 681b ldr r3, [r3, #0]
|
|
8005fae: 330c adds r3, #12
|
|
8005fb0: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac
|
|
8005fb4: 65ba str r2, [r7, #88] @ 0x58
|
|
8005fb6: 657b str r3, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005fb8: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
8005fba: 6dba ldr r2, [r7, #88] @ 0x58
|
|
8005fbc: e841 2300 strex r3, r2, [r1]
|
|
8005fc0: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
8005fc2: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8005fc4: 2b00 cmp r3, #0
|
|
8005fc6: d1e3 bne.n 8005f90 <HAL_UART_IRQHandler+0x380>
|
|
|
|
/* Last bytes received, so no need as the abort is immediate */
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
|
8005fc8: 687b ldr r3, [r7, #4]
|
|
8005fca: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8005fcc: 4618 mov r0, r3
|
|
8005fce: f7fb ff6b bl 8001ea8 <HAL_DMA_Abort>
|
|
}
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
8005fd2: 687b ldr r3, [r7, #4]
|
|
8005fd4: 2202 movs r2, #2
|
|
8005fd6: 635a str r2, [r3, #52] @ 0x34
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
8005fd8: 687b ldr r3, [r7, #4]
|
|
8005fda: 8d9a ldrh r2, [r3, #44] @ 0x2c
|
|
8005fdc: 687b ldr r3, [r7, #4]
|
|
8005fde: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
8005fe0: b29b uxth r3, r3
|
|
8005fe2: 1ad3 subs r3, r2, r3
|
|
8005fe4: b29b uxth r3, r3
|
|
8005fe6: 4619 mov r1, r3
|
|
8005fe8: 6878 ldr r0, [r7, #4]
|
|
8005fea: f000 f8e3 bl 80061b4 <HAL_UARTEx_RxEventCallback>
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
8005fee: e0b3 b.n 8006158 <HAL_UART_IRQHandler+0x548>
|
|
if (nb_remaining_rx_data == huart->RxXferSize)
|
|
8005ff0: 687b ldr r3, [r7, #4]
|
|
8005ff2: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8005ff4: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8005ff8: 429a cmp r2, r3
|
|
8005ffa: f040 80ad bne.w 8006158 <HAL_UART_IRQHandler+0x548>
|
|
if (huart->hdmarx->Init.Mode == DMA_CIRCULAR)
|
|
8005ffe: 687b ldr r3, [r7, #4]
|
|
8006000: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8006002: 69db ldr r3, [r3, #28]
|
|
8006004: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8006008: f040 80a6 bne.w 8006158 <HAL_UART_IRQHandler+0x548>
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
800600c: 687b ldr r3, [r7, #4]
|
|
800600e: 2202 movs r2, #2
|
|
8006010: 635a str r2, [r3, #52] @ 0x34
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8006012: 687b ldr r3, [r7, #4]
|
|
8006014: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8006016: 4619 mov r1, r3
|
|
8006018: 6878 ldr r0, [r7, #4]
|
|
800601a: f000 f8cb bl 80061b4 <HAL_UARTEx_RxEventCallback>
|
|
return;
|
|
800601e: e09b b.n 8006158 <HAL_UART_IRQHandler+0x548>
|
|
8006020: 080066e3 .word 0x080066e3
|
|
else
|
|
{
|
|
/* DMA mode not enabled */
|
|
/* Check received length : If all expected data are received, do nothing.
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
8006024: 687b ldr r3, [r7, #4]
|
|
8006026: 8d9a ldrh r2, [r3, #44] @ 0x2c
|
|
8006028: 687b ldr r3, [r7, #4]
|
|
800602a: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
800602c: b29b uxth r3, r3
|
|
800602e: 1ad3 subs r3, r2, r3
|
|
8006030: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
|
|
if ((huart->RxXferCount > 0U)
|
|
8006034: 687b ldr r3, [r7, #4]
|
|
8006036: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
8006038: b29b uxth r3, r3
|
|
800603a: 2b00 cmp r3, #0
|
|
800603c: f000 808e beq.w 800615c <HAL_UART_IRQHandler+0x54c>
|
|
&& (nb_rx_data > 0U))
|
|
8006040: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
8006044: 2b00 cmp r3, #0
|
|
8006046: f000 8089 beq.w 800615c <HAL_UART_IRQHandler+0x54c>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
800604a: 687b ldr r3, [r7, #4]
|
|
800604c: 681b ldr r3, [r3, #0]
|
|
800604e: 330c adds r3, #12
|
|
8006050: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006052: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006054: e853 3f00 ldrex r3, [r3]
|
|
8006058: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
800605a: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800605c: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8006060: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
8006064: 687b ldr r3, [r7, #4]
|
|
8006066: 681b ldr r3, [r3, #0]
|
|
8006068: 330c adds r3, #12
|
|
800606a: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8
|
|
800606e: 647a str r2, [r7, #68] @ 0x44
|
|
8006070: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006072: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8006074: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8006076: e841 2300 strex r3, r2, [r1]
|
|
800607a: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
800607c: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800607e: 2b00 cmp r3, #0
|
|
8006080: d1e3 bne.n 800604a <HAL_UART_IRQHandler+0x43a>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006082: 687b ldr r3, [r7, #4]
|
|
8006084: 681b ldr r3, [r3, #0]
|
|
8006086: 3314 adds r3, #20
|
|
8006088: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800608a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800608c: e853 3f00 ldrex r3, [r3]
|
|
8006090: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8006092: 6a3b ldr r3, [r7, #32]
|
|
8006094: f023 0301 bic.w r3, r3, #1
|
|
8006098: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
|
|
800609c: 687b ldr r3, [r7, #4]
|
|
800609e: 681b ldr r3, [r3, #0]
|
|
80060a0: 3314 adds r3, #20
|
|
80060a2: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
|
|
80060a6: 633a str r2, [r7, #48] @ 0x30
|
|
80060a8: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80060aa: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80060ac: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80060ae: e841 2300 strex r3, r2, [r1]
|
|
80060b2: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
80060b4: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80060b6: 2b00 cmp r3, #0
|
|
80060b8: d1e3 bne.n 8006082 <HAL_UART_IRQHandler+0x472>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80060ba: 687b ldr r3, [r7, #4]
|
|
80060bc: 2220 movs r2, #32
|
|
80060be: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80060c2: 687b ldr r3, [r7, #4]
|
|
80060c4: 2200 movs r2, #0
|
|
80060c6: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80060c8: 687b ldr r3, [r7, #4]
|
|
80060ca: 681b ldr r3, [r3, #0]
|
|
80060cc: 330c adds r3, #12
|
|
80060ce: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80060d0: 693b ldr r3, [r7, #16]
|
|
80060d2: e853 3f00 ldrex r3, [r3]
|
|
80060d6: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80060d8: 68fb ldr r3, [r7, #12]
|
|
80060da: f023 0310 bic.w r3, r3, #16
|
|
80060de: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
80060e2: 687b ldr r3, [r7, #4]
|
|
80060e4: 681b ldr r3, [r3, #0]
|
|
80060e6: 330c adds r3, #12
|
|
80060e8: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0
|
|
80060ec: 61fa str r2, [r7, #28]
|
|
80060ee: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80060f0: 69b9 ldr r1, [r7, #24]
|
|
80060f2: 69fa ldr r2, [r7, #28]
|
|
80060f4: e841 2300 strex r3, r2, [r1]
|
|
80060f8: 617b str r3, [r7, #20]
|
|
return(result);
|
|
80060fa: 697b ldr r3, [r7, #20]
|
|
80060fc: 2b00 cmp r3, #0
|
|
80060fe: d1e3 bne.n 80060c8 <HAL_UART_IRQHandler+0x4b8>
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
8006100: 687b ldr r3, [r7, #4]
|
|
8006102: 2202 movs r2, #2
|
|
8006104: 635a str r2, [r3, #52] @ 0x34
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx complete callback*/
|
|
huart->RxEventCallback(huart, nb_rx_data);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
|
8006106: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
800610a: 4619 mov r1, r3
|
|
800610c: 6878 ldr r0, [r7, #4]
|
|
800610e: f000 f851 bl 80061b4 <HAL_UARTEx_RxEventCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
return;
|
|
8006112: e023 b.n 800615c <HAL_UART_IRQHandler+0x54c>
|
|
}
|
|
}
|
|
|
|
/* UART in mode Transmitter ------------------------------------------------*/
|
|
if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
|
|
8006114: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006118: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800611c: 2b00 cmp r3, #0
|
|
800611e: d009 beq.n 8006134 <HAL_UART_IRQHandler+0x524>
|
|
8006120: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006124: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006128: 2b00 cmp r3, #0
|
|
800612a: d003 beq.n 8006134 <HAL_UART_IRQHandler+0x524>
|
|
{
|
|
UART_Transmit_IT(huart);
|
|
800612c: 6878 ldr r0, [r7, #4]
|
|
800612e: f000 fae9 bl 8006704 <UART_Transmit_IT>
|
|
return;
|
|
8006132: e014 b.n 800615e <HAL_UART_IRQHandler+0x54e>
|
|
}
|
|
|
|
/* UART in mode Transmitter end --------------------------------------------*/
|
|
if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
|
|
8006134: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006138: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800613c: 2b00 cmp r3, #0
|
|
800613e: d00e beq.n 800615e <HAL_UART_IRQHandler+0x54e>
|
|
8006140: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006144: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006148: 2b00 cmp r3, #0
|
|
800614a: d008 beq.n 800615e <HAL_UART_IRQHandler+0x54e>
|
|
{
|
|
UART_EndTransmit_IT(huart);
|
|
800614c: 6878 ldr r0, [r7, #4]
|
|
800614e: f000 fb29 bl 80067a4 <UART_EndTransmit_IT>
|
|
return;
|
|
8006152: e004 b.n 800615e <HAL_UART_IRQHandler+0x54e>
|
|
return;
|
|
8006154: bf00 nop
|
|
8006156: e002 b.n 800615e <HAL_UART_IRQHandler+0x54e>
|
|
return;
|
|
8006158: bf00 nop
|
|
800615a: e000 b.n 800615e <HAL_UART_IRQHandler+0x54e>
|
|
return;
|
|
800615c: bf00 nop
|
|
}
|
|
}
|
|
800615e: 37e8 adds r7, #232 @ 0xe8
|
|
8006160: 46bd mov sp, r7
|
|
8006162: bd80 pop {r7, pc}
|
|
|
|
08006164 <HAL_UART_TxCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8006164: b480 push {r7}
|
|
8006166: b083 sub sp, #12
|
|
8006168: af00 add r7, sp, #0
|
|
800616a: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800616c: bf00 nop
|
|
800616e: 370c adds r7, #12
|
|
8006170: 46bd mov sp, r7
|
|
8006172: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006176: 4770 bx lr
|
|
|
|
08006178 <HAL_UART_TxHalfCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8006178: b480 push {r7}
|
|
800617a: b083 sub sp, #12
|
|
800617c: af00 add r7, sp, #0
|
|
800617e: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxHalfCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8006180: bf00 nop
|
|
8006182: 370c adds r7, #12
|
|
8006184: 46bd mov sp, r7
|
|
8006186: f85d 7b04 ldr.w r7, [sp], #4
|
|
800618a: 4770 bx lr
|
|
|
|
0800618c <HAL_UART_RxHalfCpltCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800618c: b480 push {r7}
|
|
800618e: b083 sub sp, #12
|
|
8006190: af00 add r7, sp, #0
|
|
8006192: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_RxHalfCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8006194: bf00 nop
|
|
8006196: 370c adds r7, #12
|
|
8006198: 46bd mov sp, r7
|
|
800619a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800619e: 4770 bx lr
|
|
|
|
080061a0 <HAL_UART_ErrorCallback>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
80061a0: b480 push {r7}
|
|
80061a2: b083 sub sp, #12
|
|
80061a4: af00 add r7, sp, #0
|
|
80061a6: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(huart);
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_UART_ErrorCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80061a8: bf00 nop
|
|
80061aa: 370c adds r7, #12
|
|
80061ac: 46bd mov sp, r7
|
|
80061ae: f85d 7b04 ldr.w r7, [sp], #4
|
|
80061b2: 4770 bx lr
|
|
|
|
080061b4 <HAL_UARTEx_RxEventCallback>:
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
|
* reception buffer until which, data are available)
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|
{
|
|
80061b4: b480 push {r7}
|
|
80061b6: b083 sub sp, #12
|
|
80061b8: af00 add r7, sp, #0
|
|
80061ba: 6078 str r0, [r7, #4]
|
|
80061bc: 460b mov r3, r1
|
|
80061be: 807b strh r3, [r7, #2]
|
|
UNUSED(Size);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
80061c0: bf00 nop
|
|
80061c2: 370c adds r7, #12
|
|
80061c4: 46bd mov sp, r7
|
|
80061c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80061ca: 4770 bx lr
|
|
|
|
080061cc <UART_DMATransmitCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80061cc: b580 push {r7, lr}
|
|
80061ce: b090 sub sp, #64 @ 0x40
|
|
80061d0: af00 add r7, sp, #0
|
|
80061d2: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
80061d4: 687b ldr r3, [r7, #4]
|
|
80061d6: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80061d8: 63fb str r3, [r7, #60] @ 0x3c
|
|
/* DMA Normal mode*/
|
|
if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
|
|
80061da: 687b ldr r3, [r7, #4]
|
|
80061dc: 681b ldr r3, [r3, #0]
|
|
80061de: 681b ldr r3, [r3, #0]
|
|
80061e0: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80061e4: 2b00 cmp r3, #0
|
|
80061e6: d137 bne.n 8006258 <UART_DMATransmitCplt+0x8c>
|
|
{
|
|
huart->TxXferCount = 0x00U;
|
|
80061e8: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80061ea: 2200 movs r2, #0
|
|
80061ec: 84da strh r2, [r3, #38] @ 0x26
|
|
|
|
/* Disable the DMA transfer for transmit request by setting the DMAT bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
|
80061ee: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80061f0: 681b ldr r3, [r3, #0]
|
|
80061f2: 3314 adds r3, #20
|
|
80061f4: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80061f6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80061f8: e853 3f00 ldrex r3, [r3]
|
|
80061fc: 623b str r3, [r7, #32]
|
|
return(result);
|
|
80061fe: 6a3b ldr r3, [r7, #32]
|
|
8006200: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8006204: 63bb str r3, [r7, #56] @ 0x38
|
|
8006206: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006208: 681b ldr r3, [r3, #0]
|
|
800620a: 3314 adds r3, #20
|
|
800620c: 6bba ldr r2, [r7, #56] @ 0x38
|
|
800620e: 633a str r2, [r7, #48] @ 0x30
|
|
8006210: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006212: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8006214: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8006216: e841 2300 strex r3, r2, [r1]
|
|
800621a: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
800621c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800621e: 2b00 cmp r3, #0
|
|
8006220: d1e5 bne.n 80061ee <UART_DMATransmitCplt+0x22>
|
|
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
8006222: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006224: 681b ldr r3, [r3, #0]
|
|
8006226: 330c adds r3, #12
|
|
8006228: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800622a: 693b ldr r3, [r7, #16]
|
|
800622c: e853 3f00 ldrex r3, [r3]
|
|
8006230: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8006232: 68fb ldr r3, [r7, #12]
|
|
8006234: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8006238: 637b str r3, [r7, #52] @ 0x34
|
|
800623a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800623c: 681b ldr r3, [r3, #0]
|
|
800623e: 330c adds r3, #12
|
|
8006240: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
8006242: 61fa str r2, [r7, #28]
|
|
8006244: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006246: 69b9 ldr r1, [r7, #24]
|
|
8006248: 69fa ldr r2, [r7, #28]
|
|
800624a: e841 2300 strex r3, r2, [r1]
|
|
800624e: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8006250: 697b ldr r3, [r7, #20]
|
|
8006252: 2b00 cmp r3, #0
|
|
8006254: d1e5 bne.n 8006222 <UART_DMATransmitCplt+0x56>
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
8006256: e002 b.n 800625e <UART_DMATransmitCplt+0x92>
|
|
HAL_UART_TxCpltCallback(huart);
|
|
8006258: 6bf8 ldr r0, [r7, #60] @ 0x3c
|
|
800625a: f7ff ff83 bl 8006164 <HAL_UART_TxCpltCallback>
|
|
}
|
|
800625e: bf00 nop
|
|
8006260: 3740 adds r7, #64 @ 0x40
|
|
8006262: 46bd mov sp, r7
|
|
8006264: bd80 pop {r7, pc}
|
|
|
|
08006266 <UART_DMATxHalfCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8006266: b580 push {r7, lr}
|
|
8006268: b084 sub sp, #16
|
|
800626a: af00 add r7, sp, #0
|
|
800626c: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
800626e: 687b ldr r3, [r7, #4]
|
|
8006270: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006272: 60fb str r3, [r7, #12]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxHalfCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxHalfCpltCallback(huart);
|
|
8006274: 68f8 ldr r0, [r7, #12]
|
|
8006276: f7ff ff7f bl 8006178 <HAL_UART_TxHalfCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
800627a: bf00 nop
|
|
800627c: 3710 adds r7, #16
|
|
800627e: 46bd mov sp, r7
|
|
8006280: bd80 pop {r7, pc}
|
|
|
|
08006282 <UART_DMAReceiveCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8006282: b580 push {r7, lr}
|
|
8006284: b09c sub sp, #112 @ 0x70
|
|
8006286: af00 add r7, sp, #0
|
|
8006288: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
800628a: 687b ldr r3, [r7, #4]
|
|
800628c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800628e: 66fb str r3, [r7, #108] @ 0x6c
|
|
|
|
/* DMA Normal mode*/
|
|
if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
|
|
8006290: 687b ldr r3, [r7, #4]
|
|
8006292: 681b ldr r3, [r3, #0]
|
|
8006294: 681b ldr r3, [r3, #0]
|
|
8006296: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800629a: 2b00 cmp r3, #0
|
|
800629c: d172 bne.n 8006384 <UART_DMAReceiveCplt+0x102>
|
|
{
|
|
huart->RxXferCount = 0U;
|
|
800629e: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80062a0: 2200 movs r2, #0
|
|
80062a2: 85da strh r2, [r3, #46] @ 0x2e
|
|
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
80062a4: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80062a6: 681b ldr r3, [r3, #0]
|
|
80062a8: 330c adds r3, #12
|
|
80062aa: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80062ac: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80062ae: e853 3f00 ldrex r3, [r3]
|
|
80062b2: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
80062b4: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80062b6: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
80062ba: 66bb str r3, [r7, #104] @ 0x68
|
|
80062bc: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80062be: 681b ldr r3, [r3, #0]
|
|
80062c0: 330c adds r3, #12
|
|
80062c2: 6eba ldr r2, [r7, #104] @ 0x68
|
|
80062c4: 65ba str r2, [r7, #88] @ 0x58
|
|
80062c6: 657b str r3, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80062c8: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
80062ca: 6dba ldr r2, [r7, #88] @ 0x58
|
|
80062cc: e841 2300 strex r3, r2, [r1]
|
|
80062d0: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
80062d2: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80062d4: 2b00 cmp r3, #0
|
|
80062d6: d1e5 bne.n 80062a4 <UART_DMAReceiveCplt+0x22>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
80062d8: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80062da: 681b ldr r3, [r3, #0]
|
|
80062dc: 3314 adds r3, #20
|
|
80062de: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80062e0: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80062e2: e853 3f00 ldrex r3, [r3]
|
|
80062e6: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
80062e8: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80062ea: f023 0301 bic.w r3, r3, #1
|
|
80062ee: 667b str r3, [r7, #100] @ 0x64
|
|
80062f0: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80062f2: 681b ldr r3, [r3, #0]
|
|
80062f4: 3314 adds r3, #20
|
|
80062f6: 6e7a ldr r2, [r7, #100] @ 0x64
|
|
80062f8: 647a str r2, [r7, #68] @ 0x44
|
|
80062fa: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80062fc: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
80062fe: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8006300: e841 2300 strex r3, r2, [r1]
|
|
8006304: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8006306: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006308: 2b00 cmp r3, #0
|
|
800630a: d1e5 bne.n 80062d8 <UART_DMAReceiveCplt+0x56>
|
|
|
|
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
800630c: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800630e: 681b ldr r3, [r3, #0]
|
|
8006310: 3314 adds r3, #20
|
|
8006312: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006314: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006316: e853 3f00 ldrex r3, [r3]
|
|
800631a: 623b str r3, [r7, #32]
|
|
return(result);
|
|
800631c: 6a3b ldr r3, [r7, #32]
|
|
800631e: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8006322: 663b str r3, [r7, #96] @ 0x60
|
|
8006324: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8006326: 681b ldr r3, [r3, #0]
|
|
8006328: 3314 adds r3, #20
|
|
800632a: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
800632c: 633a str r2, [r7, #48] @ 0x30
|
|
800632e: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006330: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8006332: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8006334: e841 2300 strex r3, r2, [r1]
|
|
8006338: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
800633a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800633c: 2b00 cmp r3, #0
|
|
800633e: d1e5 bne.n 800630c <UART_DMAReceiveCplt+0x8a>
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006340: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8006342: 2220 movs r2, #32
|
|
8006344: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8006348: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800634a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800634c: 2b01 cmp r3, #1
|
|
800634e: d119 bne.n 8006384 <UART_DMAReceiveCplt+0x102>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8006350: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8006352: 681b ldr r3, [r3, #0]
|
|
8006354: 330c adds r3, #12
|
|
8006356: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006358: 693b ldr r3, [r7, #16]
|
|
800635a: e853 3f00 ldrex r3, [r3]
|
|
800635e: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8006360: 68fb ldr r3, [r7, #12]
|
|
8006362: f023 0310 bic.w r3, r3, #16
|
|
8006366: 65fb str r3, [r7, #92] @ 0x5c
|
|
8006368: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800636a: 681b ldr r3, [r3, #0]
|
|
800636c: 330c adds r3, #12
|
|
800636e: 6dfa ldr r2, [r7, #92] @ 0x5c
|
|
8006370: 61fa str r2, [r7, #28]
|
|
8006372: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006374: 69b9 ldr r1, [r7, #24]
|
|
8006376: 69fa ldr r2, [r7, #28]
|
|
8006378: e841 2300 strex r3, r2, [r1]
|
|
800637c: 617b str r3, [r7, #20]
|
|
return(result);
|
|
800637e: 697b ldr r3, [r7, #20]
|
|
8006380: 2b00 cmp r3, #0
|
|
8006382: d1e5 bne.n 8006350 <UART_DMAReceiveCplt+0xce>
|
|
}
|
|
}
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8006384: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8006386: 2200 movs r2, #0
|
|
8006388: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : use Rx Event callback */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
800638a: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800638c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800638e: 2b01 cmp r3, #1
|
|
8006390: d106 bne.n 80063a0 <UART_DMAReceiveCplt+0x11e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8006392: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8006394: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8006396: 4619 mov r1, r3
|
|
8006398: 6ef8 ldr r0, [r7, #108] @ 0x6c
|
|
800639a: f7ff ff0b bl 80061b4 <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
800639e: e002 b.n 80063a6 <UART_DMAReceiveCplt+0x124>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
80063a0: 6ef8 ldr r0, [r7, #108] @ 0x6c
|
|
80063a2: f7fa fb63 bl 8000a6c <HAL_UART_RxCpltCallback>
|
|
}
|
|
80063a6: bf00 nop
|
|
80063a8: 3770 adds r7, #112 @ 0x70
|
|
80063aa: 46bd mov sp, r7
|
|
80063ac: bd80 pop {r7, pc}
|
|
|
|
080063ae <UART_DMARxHalfCplt>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80063ae: b580 push {r7, lr}
|
|
80063b0: b084 sub sp, #16
|
|
80063b2: af00 add r7, sp, #0
|
|
80063b4: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
80063b6: 687b ldr r3, [r7, #4]
|
|
80063b8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80063ba: 60fb str r3, [r7, #12]
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Half Transfer */
|
|
huart->RxEventType = HAL_UART_RXEVENT_HT;
|
|
80063bc: 68fb ldr r3, [r7, #12]
|
|
80063be: 2201 movs r2, #1
|
|
80063c0: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : use Rx Event callback */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80063c2: 68fb ldr r3, [r7, #12]
|
|
80063c4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80063c6: 2b01 cmp r3, #1
|
|
80063c8: d108 bne.n 80063dc <UART_DMARxHalfCplt+0x2e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize / 2U);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
|
|
80063ca: 68fb ldr r3, [r7, #12]
|
|
80063cc: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
80063ce: 085b lsrs r3, r3, #1
|
|
80063d0: b29b uxth r3, r3
|
|
80063d2: 4619 mov r1, r3
|
|
80063d4: 68f8 ldr r0, [r7, #12]
|
|
80063d6: f7ff feed bl 80061b4 <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx Half complete callback*/
|
|
HAL_UART_RxHalfCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
80063da: e002 b.n 80063e2 <UART_DMARxHalfCplt+0x34>
|
|
HAL_UART_RxHalfCpltCallback(huart);
|
|
80063dc: 68f8 ldr r0, [r7, #12]
|
|
80063de: f7ff fed5 bl 800618c <HAL_UART_RxHalfCpltCallback>
|
|
}
|
|
80063e2: bf00 nop
|
|
80063e4: 3710 adds r7, #16
|
|
80063e6: 46bd mov sp, r7
|
|
80063e8: bd80 pop {r7, pc}
|
|
|
|
080063ea <UART_DMAError>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80063ea: b580 push {r7, lr}
|
|
80063ec: b084 sub sp, #16
|
|
80063ee: af00 add r7, sp, #0
|
|
80063f0: 6078 str r0, [r7, #4]
|
|
uint32_t dmarequest = 0x00U;
|
|
80063f2: 2300 movs r3, #0
|
|
80063f4: 60fb str r3, [r7, #12]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
80063f6: 687b ldr r3, [r7, #4]
|
|
80063f8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80063fa: 60bb str r3, [r7, #8]
|
|
|
|
/* Stop UART DMA Tx request if ongoing */
|
|
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
|
|
80063fc: 68bb ldr r3, [r7, #8]
|
|
80063fe: 681b ldr r3, [r3, #0]
|
|
8006400: 695b ldr r3, [r3, #20]
|
|
8006402: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006406: 2b80 cmp r3, #128 @ 0x80
|
|
8006408: bf0c ite eq
|
|
800640a: 2301 moveq r3, #1
|
|
800640c: 2300 movne r3, #0
|
|
800640e: b2db uxtb r3, r3
|
|
8006410: 60fb str r3, [r7, #12]
|
|
if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
|
|
8006412: 68bb ldr r3, [r7, #8]
|
|
8006414: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8006418: b2db uxtb r3, r3
|
|
800641a: 2b21 cmp r3, #33 @ 0x21
|
|
800641c: d108 bne.n 8006430 <UART_DMAError+0x46>
|
|
800641e: 68fb ldr r3, [r7, #12]
|
|
8006420: 2b00 cmp r3, #0
|
|
8006422: d005 beq.n 8006430 <UART_DMAError+0x46>
|
|
{
|
|
huart->TxXferCount = 0x00U;
|
|
8006424: 68bb ldr r3, [r7, #8]
|
|
8006426: 2200 movs r2, #0
|
|
8006428: 84da strh r2, [r3, #38] @ 0x26
|
|
UART_EndTxTransfer(huart);
|
|
800642a: 68b8 ldr r0, [r7, #8]
|
|
800642c: f000 f8ce bl 80065cc <UART_EndTxTransfer>
|
|
}
|
|
|
|
/* Stop UART DMA Rx request if ongoing */
|
|
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8006430: 68bb ldr r3, [r7, #8]
|
|
8006432: 681b ldr r3, [r3, #0]
|
|
8006434: 695b ldr r3, [r3, #20]
|
|
8006436: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800643a: 2b40 cmp r3, #64 @ 0x40
|
|
800643c: bf0c ite eq
|
|
800643e: 2301 moveq r3, #1
|
|
8006440: 2300 movne r3, #0
|
|
8006442: b2db uxtb r3, r3
|
|
8006444: 60fb str r3, [r7, #12]
|
|
if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
|
|
8006446: 68bb ldr r3, [r7, #8]
|
|
8006448: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
800644c: b2db uxtb r3, r3
|
|
800644e: 2b22 cmp r3, #34 @ 0x22
|
|
8006450: d108 bne.n 8006464 <UART_DMAError+0x7a>
|
|
8006452: 68fb ldr r3, [r7, #12]
|
|
8006454: 2b00 cmp r3, #0
|
|
8006456: d005 beq.n 8006464 <UART_DMAError+0x7a>
|
|
{
|
|
huart->RxXferCount = 0x00U;
|
|
8006458: 68bb ldr r3, [r7, #8]
|
|
800645a: 2200 movs r2, #0
|
|
800645c: 85da strh r2, [r3, #46] @ 0x2e
|
|
UART_EndRxTransfer(huart);
|
|
800645e: 68b8 ldr r0, [r7, #8]
|
|
8006460: f000 f8dc bl 800661c <UART_EndRxTransfer>
|
|
}
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_DMA;
|
|
8006464: 68bb ldr r3, [r7, #8]
|
|
8006466: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8006468: f043 0210 orr.w r2, r3, #16
|
|
800646c: 68bb ldr r3, [r7, #8]
|
|
800646e: 645a str r2, [r3, #68] @ 0x44
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8006470: 68b8 ldr r0, [r7, #8]
|
|
8006472: f7ff fe95 bl 80061a0 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
8006476: bf00 nop
|
|
8006478: 3710 adds r7, #16
|
|
800647a: 46bd mov sp, r7
|
|
800647c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08006480 <UART_Start_Receive_DMA>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
8006480: b580 push {r7, lr}
|
|
8006482: b098 sub sp, #96 @ 0x60
|
|
8006484: af00 add r7, sp, #0
|
|
8006486: 60f8 str r0, [r7, #12]
|
|
8006488: 60b9 str r1, [r7, #8]
|
|
800648a: 4613 mov r3, r2
|
|
800648c: 80fb strh r3, [r7, #6]
|
|
uint32_t *tmp;
|
|
|
|
huart->pRxBuffPtr = pData;
|
|
800648e: 68ba ldr r2, [r7, #8]
|
|
8006490: 68fb ldr r3, [r7, #12]
|
|
8006492: 629a str r2, [r3, #40] @ 0x28
|
|
huart->RxXferSize = Size;
|
|
8006494: 68fb ldr r3, [r7, #12]
|
|
8006496: 88fa ldrh r2, [r7, #6]
|
|
8006498: 859a strh r2, [r3, #44] @ 0x2c
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800649a: 68fb ldr r3, [r7, #12]
|
|
800649c: 2200 movs r2, #0
|
|
800649e: 645a str r2, [r3, #68] @ 0x44
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
80064a0: 68fb ldr r3, [r7, #12]
|
|
80064a2: 2222 movs r2, #34 @ 0x22
|
|
80064a4: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Set the UART DMA transfer complete callback */
|
|
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
|
|
80064a8: 68fb ldr r3, [r7, #12]
|
|
80064aa: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80064ac: 4a44 ldr r2, [pc, #272] @ (80065c0 <UART_Start_Receive_DMA+0x140>)
|
|
80064ae: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Set the UART DMA Half transfer complete callback */
|
|
huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
|
|
80064b0: 68fb ldr r3, [r7, #12]
|
|
80064b2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80064b4: 4a43 ldr r2, [pc, #268] @ (80065c4 <UART_Start_Receive_DMA+0x144>)
|
|
80064b6: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set the DMA error callback */
|
|
huart->hdmarx->XferErrorCallback = UART_DMAError;
|
|
80064b8: 68fb ldr r3, [r7, #12]
|
|
80064ba: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80064bc: 4a42 ldr r2, [pc, #264] @ (80065c8 <UART_Start_Receive_DMA+0x148>)
|
|
80064be: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Set the DMA abort callback */
|
|
huart->hdmarx->XferAbortCallback = NULL;
|
|
80064c0: 68fb ldr r3, [r7, #12]
|
|
80064c2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80064c4: 2200 movs r2, #0
|
|
80064c6: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Enable the DMA stream */
|
|
tmp = (uint32_t *)&pData;
|
|
80064c8: f107 0308 add.w r3, r7, #8
|
|
80064cc: 65fb str r3, [r7, #92] @ 0x5c
|
|
if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK)
|
|
80064ce: 68fb ldr r3, [r7, #12]
|
|
80064d0: 6bd8 ldr r0, [r3, #60] @ 0x3c
|
|
80064d2: 68fb ldr r3, [r7, #12]
|
|
80064d4: 681b ldr r3, [r3, #0]
|
|
80064d6: 3304 adds r3, #4
|
|
80064d8: 4619 mov r1, r3
|
|
80064da: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80064dc: 681a ldr r2, [r3, #0]
|
|
80064de: 88fb ldrh r3, [r7, #6]
|
|
80064e0: f7fb fc8a bl 8001df8 <HAL_DMA_Start_IT>
|
|
80064e4: 4603 mov r3, r0
|
|
80064e6: 2b00 cmp r3, #0
|
|
80064e8: d008 beq.n 80064fc <UART_Start_Receive_DMA+0x7c>
|
|
{
|
|
/* Set error code to DMA */
|
|
huart->ErrorCode = HAL_UART_ERROR_DMA;
|
|
80064ea: 68fb ldr r3, [r7, #12]
|
|
80064ec: 2210 movs r2, #16
|
|
80064ee: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Restore huart->RxState to ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80064f0: 68fb ldr r3, [r7, #12]
|
|
80064f2: 2220 movs r2, #32
|
|
80064f4: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
return HAL_ERROR;
|
|
80064f8: 2301 movs r3, #1
|
|
80064fa: e05d b.n 80065b8 <UART_Start_Receive_DMA+0x138>
|
|
}
|
|
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
|
|
__HAL_UART_CLEAR_OREFLAG(huart);
|
|
80064fc: 2300 movs r3, #0
|
|
80064fe: 613b str r3, [r7, #16]
|
|
8006500: 68fb ldr r3, [r7, #12]
|
|
8006502: 681b ldr r3, [r3, #0]
|
|
8006504: 681b ldr r3, [r3, #0]
|
|
8006506: 613b str r3, [r7, #16]
|
|
8006508: 68fb ldr r3, [r7, #12]
|
|
800650a: 681b ldr r3, [r3, #0]
|
|
800650c: 685b ldr r3, [r3, #4]
|
|
800650e: 613b str r3, [r7, #16]
|
|
8006510: 693b ldr r3, [r7, #16]
|
|
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
8006512: 68fb ldr r3, [r7, #12]
|
|
8006514: 691b ldr r3, [r3, #16]
|
|
8006516: 2b00 cmp r3, #0
|
|
8006518: d019 beq.n 800654e <UART_Start_Receive_DMA+0xce>
|
|
{
|
|
/* Enable the UART Parity Error Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
800651a: 68fb ldr r3, [r7, #12]
|
|
800651c: 681b ldr r3, [r3, #0]
|
|
800651e: 330c adds r3, #12
|
|
8006520: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006522: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8006524: e853 3f00 ldrex r3, [r3]
|
|
8006528: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
800652a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800652c: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8006530: 65bb str r3, [r7, #88] @ 0x58
|
|
8006532: 68fb ldr r3, [r7, #12]
|
|
8006534: 681b ldr r3, [r3, #0]
|
|
8006536: 330c adds r3, #12
|
|
8006538: 6dba ldr r2, [r7, #88] @ 0x58
|
|
800653a: 64fa str r2, [r7, #76] @ 0x4c
|
|
800653c: 64bb str r3, [r7, #72] @ 0x48
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800653e: 6cb9 ldr r1, [r7, #72] @ 0x48
|
|
8006540: 6cfa ldr r2, [r7, #76] @ 0x4c
|
|
8006542: e841 2300 strex r3, r2, [r1]
|
|
8006546: 647b str r3, [r7, #68] @ 0x44
|
|
return(result);
|
|
8006548: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800654a: 2b00 cmp r3, #0
|
|
800654c: d1e5 bne.n 800651a <UART_Start_Receive_DMA+0x9a>
|
|
}
|
|
|
|
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800654e: 68fb ldr r3, [r7, #12]
|
|
8006550: 681b ldr r3, [r3, #0]
|
|
8006552: 3314 adds r3, #20
|
|
8006554: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006556: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8006558: e853 3f00 ldrex r3, [r3]
|
|
800655c: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
800655e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006560: f043 0301 orr.w r3, r3, #1
|
|
8006564: 657b str r3, [r7, #84] @ 0x54
|
|
8006566: 68fb ldr r3, [r7, #12]
|
|
8006568: 681b ldr r3, [r3, #0]
|
|
800656a: 3314 adds r3, #20
|
|
800656c: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
800656e: 63ba str r2, [r7, #56] @ 0x38
|
|
8006570: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006572: 6b79 ldr r1, [r7, #52] @ 0x34
|
|
8006574: 6bba ldr r2, [r7, #56] @ 0x38
|
|
8006576: e841 2300 strex r3, r2, [r1]
|
|
800657a: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
800657c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800657e: 2b00 cmp r3, #0
|
|
8006580: d1e5 bne.n 800654e <UART_Start_Receive_DMA+0xce>
|
|
|
|
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8006582: 68fb ldr r3, [r7, #12]
|
|
8006584: 681b ldr r3, [r3, #0]
|
|
8006586: 3314 adds r3, #20
|
|
8006588: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800658a: 69bb ldr r3, [r7, #24]
|
|
800658c: e853 3f00 ldrex r3, [r3]
|
|
8006590: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8006592: 697b ldr r3, [r7, #20]
|
|
8006594: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8006598: 653b str r3, [r7, #80] @ 0x50
|
|
800659a: 68fb ldr r3, [r7, #12]
|
|
800659c: 681b ldr r3, [r3, #0]
|
|
800659e: 3314 adds r3, #20
|
|
80065a0: 6d3a ldr r2, [r7, #80] @ 0x50
|
|
80065a2: 627a str r2, [r7, #36] @ 0x24
|
|
80065a4: 623b str r3, [r7, #32]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80065a6: 6a39 ldr r1, [r7, #32]
|
|
80065a8: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80065aa: e841 2300 strex r3, r2, [r1]
|
|
80065ae: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
80065b0: 69fb ldr r3, [r7, #28]
|
|
80065b2: 2b00 cmp r3, #0
|
|
80065b4: d1e5 bne.n 8006582 <UART_Start_Receive_DMA+0x102>
|
|
|
|
return HAL_OK;
|
|
80065b6: 2300 movs r3, #0
|
|
}
|
|
80065b8: 4618 mov r0, r3
|
|
80065ba: 3760 adds r7, #96 @ 0x60
|
|
80065bc: 46bd mov sp, r7
|
|
80065be: bd80 pop {r7, pc}
|
|
80065c0: 08006283 .word 0x08006283
|
|
80065c4: 080063af .word 0x080063af
|
|
80065c8: 080063eb .word 0x080063eb
|
|
|
|
080065cc <UART_EndTxTransfer>:
|
|
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
80065cc: b480 push {r7}
|
|
80065ce: b089 sub sp, #36 @ 0x24
|
|
80065d0: af00 add r7, sp, #0
|
|
80065d2: 6078 str r0, [r7, #4]
|
|
/* Disable TXEIE and TCIE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
|
|
80065d4: 687b ldr r3, [r7, #4]
|
|
80065d6: 681b ldr r3, [r3, #0]
|
|
80065d8: 330c adds r3, #12
|
|
80065da: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80065dc: 68fb ldr r3, [r7, #12]
|
|
80065de: e853 3f00 ldrex r3, [r3]
|
|
80065e2: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
80065e4: 68bb ldr r3, [r7, #8]
|
|
80065e6: f023 03c0 bic.w r3, r3, #192 @ 0xc0
|
|
80065ea: 61fb str r3, [r7, #28]
|
|
80065ec: 687b ldr r3, [r7, #4]
|
|
80065ee: 681b ldr r3, [r3, #0]
|
|
80065f0: 330c adds r3, #12
|
|
80065f2: 69fa ldr r2, [r7, #28]
|
|
80065f4: 61ba str r2, [r7, #24]
|
|
80065f6: 617b str r3, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80065f8: 6979 ldr r1, [r7, #20]
|
|
80065fa: 69ba ldr r2, [r7, #24]
|
|
80065fc: e841 2300 strex r3, r2, [r1]
|
|
8006600: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8006602: 693b ldr r3, [r7, #16]
|
|
8006604: 2b00 cmp r3, #0
|
|
8006606: d1e5 bne.n 80065d4 <UART_EndTxTransfer+0x8>
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006608: 687b ldr r3, [r7, #4]
|
|
800660a: 2220 movs r2, #32
|
|
800660c: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
}
|
|
8006610: bf00 nop
|
|
8006612: 3724 adds r7, #36 @ 0x24
|
|
8006614: 46bd mov sp, r7
|
|
8006616: f85d 7b04 ldr.w r7, [sp], #4
|
|
800661a: 4770 bx lr
|
|
|
|
0800661c <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
800661c: b480 push {r7}
|
|
800661e: b095 sub sp, #84 @ 0x54
|
|
8006620: af00 add r7, sp, #0
|
|
8006622: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
8006624: 687b ldr r3, [r7, #4]
|
|
8006626: 681b ldr r3, [r3, #0]
|
|
8006628: 330c adds r3, #12
|
|
800662a: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800662c: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800662e: e853 3f00 ldrex r3, [r3]
|
|
8006632: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8006634: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006636: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
800663a: 64fb str r3, [r7, #76] @ 0x4c
|
|
800663c: 687b ldr r3, [r7, #4]
|
|
800663e: 681b ldr r3, [r3, #0]
|
|
8006640: 330c adds r3, #12
|
|
8006642: 6cfa ldr r2, [r7, #76] @ 0x4c
|
|
8006644: 643a str r2, [r7, #64] @ 0x40
|
|
8006646: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006648: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
800664a: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
800664c: e841 2300 strex r3, r2, [r1]
|
|
8006650: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8006652: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006654: 2b00 cmp r3, #0
|
|
8006656: d1e5 bne.n 8006624 <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006658: 687b ldr r3, [r7, #4]
|
|
800665a: 681b ldr r3, [r3, #0]
|
|
800665c: 3314 adds r3, #20
|
|
800665e: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006660: 6a3b ldr r3, [r7, #32]
|
|
8006662: e853 3f00 ldrex r3, [r3]
|
|
8006666: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8006668: 69fb ldr r3, [r7, #28]
|
|
800666a: f023 0301 bic.w r3, r3, #1
|
|
800666e: 64bb str r3, [r7, #72] @ 0x48
|
|
8006670: 687b ldr r3, [r7, #4]
|
|
8006672: 681b ldr r3, [r3, #0]
|
|
8006674: 3314 adds r3, #20
|
|
8006676: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8006678: 62fa str r2, [r7, #44] @ 0x2c
|
|
800667a: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800667c: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
800667e: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8006680: e841 2300 strex r3, r2, [r1]
|
|
8006684: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8006686: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006688: 2b00 cmp r3, #0
|
|
800668a: d1e5 bne.n 8006658 <UART_EndRxTransfer+0x3c>
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
800668c: 687b ldr r3, [r7, #4]
|
|
800668e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006690: 2b01 cmp r3, #1
|
|
8006692: d119 bne.n 80066c8 <UART_EndRxTransfer+0xac>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8006694: 687b ldr r3, [r7, #4]
|
|
8006696: 681b ldr r3, [r3, #0]
|
|
8006698: 330c adds r3, #12
|
|
800669a: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800669c: 68fb ldr r3, [r7, #12]
|
|
800669e: e853 3f00 ldrex r3, [r3]
|
|
80066a2: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
80066a4: 68bb ldr r3, [r7, #8]
|
|
80066a6: f023 0310 bic.w r3, r3, #16
|
|
80066aa: 647b str r3, [r7, #68] @ 0x44
|
|
80066ac: 687b ldr r3, [r7, #4]
|
|
80066ae: 681b ldr r3, [r3, #0]
|
|
80066b0: 330c adds r3, #12
|
|
80066b2: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
80066b4: 61ba str r2, [r7, #24]
|
|
80066b6: 617b str r3, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80066b8: 6979 ldr r1, [r7, #20]
|
|
80066ba: 69ba ldr r2, [r7, #24]
|
|
80066bc: e841 2300 strex r3, r2, [r1]
|
|
80066c0: 613b str r3, [r7, #16]
|
|
return(result);
|
|
80066c2: 693b ldr r3, [r7, #16]
|
|
80066c4: 2b00 cmp r3, #0
|
|
80066c6: d1e5 bne.n 8006694 <UART_EndRxTransfer+0x78>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80066c8: 687b ldr r3, [r7, #4]
|
|
80066ca: 2220 movs r2, #32
|
|
80066cc: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80066d0: 687b ldr r3, [r7, #4]
|
|
80066d2: 2200 movs r2, #0
|
|
80066d4: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
80066d6: bf00 nop
|
|
80066d8: 3754 adds r7, #84 @ 0x54
|
|
80066da: 46bd mov sp, r7
|
|
80066dc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80066e0: 4770 bx lr
|
|
|
|
080066e2 <UART_DMAAbortOnError>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80066e2: b580 push {r7, lr}
|
|
80066e4: b084 sub sp, #16
|
|
80066e6: af00 add r7, sp, #0
|
|
80066e8: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
|
80066ea: 687b ldr r3, [r7, #4]
|
|
80066ec: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80066ee: 60fb str r3, [r7, #12]
|
|
huart->RxXferCount = 0x00U;
|
|
80066f0: 68fb ldr r3, [r7, #12]
|
|
80066f2: 2200 movs r2, #0
|
|
80066f4: 85da strh r2, [r3, #46] @ 0x2e
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
80066f6: 68f8 ldr r0, [r7, #12]
|
|
80066f8: f7ff fd52 bl 80061a0 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
80066fc: bf00 nop
|
|
80066fe: 3710 adds r7, #16
|
|
8006700: 46bd mov sp, r7
|
|
8006702: bd80 pop {r7, pc}
|
|
|
|
08006704 <UART_Transmit_IT>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
8006704: b480 push {r7}
|
|
8006706: b085 sub sp, #20
|
|
8006708: af00 add r7, sp, #0
|
|
800670a: 6078 str r0, [r7, #4]
|
|
const uint16_t *tmp;
|
|
|
|
/* Check that a Tx process is ongoing */
|
|
if (huart->gState == HAL_UART_STATE_BUSY_TX)
|
|
800670c: 687b ldr r3, [r7, #4]
|
|
800670e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8006712: b2db uxtb r3, r3
|
|
8006714: 2b21 cmp r3, #33 @ 0x21
|
|
8006716: d13e bne.n 8006796 <UART_Transmit_IT+0x92>
|
|
{
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8006718: 687b ldr r3, [r7, #4]
|
|
800671a: 689b ldr r3, [r3, #8]
|
|
800671c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8006720: d114 bne.n 800674c <UART_Transmit_IT+0x48>
|
|
8006722: 687b ldr r3, [r7, #4]
|
|
8006724: 691b ldr r3, [r3, #16]
|
|
8006726: 2b00 cmp r3, #0
|
|
8006728: d110 bne.n 800674c <UART_Transmit_IT+0x48>
|
|
{
|
|
tmp = (const uint16_t *) huart->pTxBuffPtr;
|
|
800672a: 687b ldr r3, [r7, #4]
|
|
800672c: 6a1b ldr r3, [r3, #32]
|
|
800672e: 60fb str r3, [r7, #12]
|
|
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
|
|
8006730: 68fb ldr r3, [r7, #12]
|
|
8006732: 881b ldrh r3, [r3, #0]
|
|
8006734: 461a mov r2, r3
|
|
8006736: 687b ldr r3, [r7, #4]
|
|
8006738: 681b ldr r3, [r3, #0]
|
|
800673a: f3c2 0208 ubfx r2, r2, #0, #9
|
|
800673e: 605a str r2, [r3, #4]
|
|
huart->pTxBuffPtr += 2U;
|
|
8006740: 687b ldr r3, [r7, #4]
|
|
8006742: 6a1b ldr r3, [r3, #32]
|
|
8006744: 1c9a adds r2, r3, #2
|
|
8006746: 687b ldr r3, [r7, #4]
|
|
8006748: 621a str r2, [r3, #32]
|
|
800674a: e008 b.n 800675e <UART_Transmit_IT+0x5a>
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
|
|
800674c: 687b ldr r3, [r7, #4]
|
|
800674e: 6a1b ldr r3, [r3, #32]
|
|
8006750: 1c59 adds r1, r3, #1
|
|
8006752: 687a ldr r2, [r7, #4]
|
|
8006754: 6211 str r1, [r2, #32]
|
|
8006756: 781a ldrb r2, [r3, #0]
|
|
8006758: 687b ldr r3, [r7, #4]
|
|
800675a: 681b ldr r3, [r3, #0]
|
|
800675c: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if (--huart->TxXferCount == 0U)
|
|
800675e: 687b ldr r3, [r7, #4]
|
|
8006760: 8cdb ldrh r3, [r3, #38] @ 0x26
|
|
8006762: b29b uxth r3, r3
|
|
8006764: 3b01 subs r3, #1
|
|
8006766: b29b uxth r3, r3
|
|
8006768: 687a ldr r2, [r7, #4]
|
|
800676a: 4619 mov r1, r3
|
|
800676c: 84d1 strh r1, [r2, #38] @ 0x26
|
|
800676e: 2b00 cmp r3, #0
|
|
8006770: d10f bne.n 8006792 <UART_Transmit_IT+0x8e>
|
|
{
|
|
/* Disable the UART Transmit Data Register Empty Interrupt */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
|
|
8006772: 687b ldr r3, [r7, #4]
|
|
8006774: 681b ldr r3, [r3, #0]
|
|
8006776: 68da ldr r2, [r3, #12]
|
|
8006778: 687b ldr r3, [r7, #4]
|
|
800677a: 681b ldr r3, [r3, #0]
|
|
800677c: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
8006780: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the UART Transmit Complete Interrupt */
|
|
__HAL_UART_ENABLE_IT(huart, UART_IT_TC);
|
|
8006782: 687b ldr r3, [r7, #4]
|
|
8006784: 681b ldr r3, [r3, #0]
|
|
8006786: 68da ldr r2, [r3, #12]
|
|
8006788: 687b ldr r3, [r7, #4]
|
|
800678a: 681b ldr r3, [r3, #0]
|
|
800678c: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
8006790: 60da str r2, [r3, #12]
|
|
}
|
|
return HAL_OK;
|
|
8006792: 2300 movs r3, #0
|
|
8006794: e000 b.n 8006798 <UART_Transmit_IT+0x94>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8006796: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8006798: 4618 mov r0, r3
|
|
800679a: 3714 adds r7, #20
|
|
800679c: 46bd mov sp, r7
|
|
800679e: f85d 7b04 ldr.w r7, [sp], #4
|
|
80067a2: 4770 bx lr
|
|
|
|
080067a4 <UART_EndTransmit_IT>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
80067a4: b580 push {r7, lr}
|
|
80067a6: b082 sub sp, #8
|
|
80067a8: af00 add r7, sp, #0
|
|
80067aa: 6078 str r0, [r7, #4]
|
|
/* Disable the UART Transmit Complete Interrupt */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
|
|
80067ac: 687b ldr r3, [r7, #4]
|
|
80067ae: 681b ldr r3, [r3, #0]
|
|
80067b0: 68da ldr r2, [r3, #12]
|
|
80067b2: 687b ldr r3, [r7, #4]
|
|
80067b4: 681b ldr r3, [r3, #0]
|
|
80067b6: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
80067ba: 60da str r2, [r3, #12]
|
|
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80067bc: 687b ldr r3, [r7, #4]
|
|
80067be: 2220 movs r2, #32
|
|
80067c0: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
80067c4: 6878 ldr r0, [r7, #4]
|
|
80067c6: f7ff fccd bl 8006164 <HAL_UART_TxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
|
|
return HAL_OK;
|
|
80067ca: 2300 movs r3, #0
|
|
}
|
|
80067cc: 4618 mov r0, r3
|
|
80067ce: 3708 adds r7, #8
|
|
80067d0: 46bd mov sp, r7
|
|
80067d2: bd80 pop {r7, pc}
|
|
|
|
080067d4 <UART_Receive_IT>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
80067d4: b580 push {r7, lr}
|
|
80067d6: b08c sub sp, #48 @ 0x30
|
|
80067d8: af00 add r7, sp, #0
|
|
80067da: 6078 str r0, [r7, #4]
|
|
uint8_t *pdata8bits = NULL;
|
|
80067dc: 2300 movs r3, #0
|
|
80067de: 62fb str r3, [r7, #44] @ 0x2c
|
|
uint16_t *pdata16bits = NULL;
|
|
80067e0: 2300 movs r3, #0
|
|
80067e2: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
80067e4: 687b ldr r3, [r7, #4]
|
|
80067e6: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
80067ea: b2db uxtb r3, r3
|
|
80067ec: 2b22 cmp r3, #34 @ 0x22
|
|
80067ee: f040 80aa bne.w 8006946 <UART_Receive_IT+0x172>
|
|
{
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
80067f2: 687b ldr r3, [r7, #4]
|
|
80067f4: 689b ldr r3, [r3, #8]
|
|
80067f6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
80067fa: d115 bne.n 8006828 <UART_Receive_IT+0x54>
|
|
80067fc: 687b ldr r3, [r7, #4]
|
|
80067fe: 691b ldr r3, [r3, #16]
|
|
8006800: 2b00 cmp r3, #0
|
|
8006802: d111 bne.n 8006828 <UART_Receive_IT+0x54>
|
|
{
|
|
/* Unused pdata8bits */
|
|
UNUSED(pdata8bits);
|
|
pdata16bits = (uint16_t *) huart->pRxBuffPtr;
|
|
8006804: 687b ldr r3, [r7, #4]
|
|
8006806: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006808: 62bb str r3, [r7, #40] @ 0x28
|
|
*pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
|
|
800680a: 687b ldr r3, [r7, #4]
|
|
800680c: 681b ldr r3, [r3, #0]
|
|
800680e: 685b ldr r3, [r3, #4]
|
|
8006810: b29b uxth r3, r3
|
|
8006812: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8006816: b29a uxth r2, r3
|
|
8006818: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800681a: 801a strh r2, [r3, #0]
|
|
huart->pRxBuffPtr += 2U;
|
|
800681c: 687b ldr r3, [r7, #4]
|
|
800681e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006820: 1c9a adds r2, r3, #2
|
|
8006822: 687b ldr r3, [r7, #4]
|
|
8006824: 629a str r2, [r3, #40] @ 0x28
|
|
8006826: e024 b.n 8006872 <UART_Receive_IT+0x9e>
|
|
}
|
|
else
|
|
{
|
|
pdata8bits = (uint8_t *) huart->pRxBuffPtr;
|
|
8006828: 687b ldr r3, [r7, #4]
|
|
800682a: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800682c: 62fb str r3, [r7, #44] @ 0x2c
|
|
/* Unused pdata16bits */
|
|
UNUSED(pdata16bits);
|
|
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
|
|
800682e: 687b ldr r3, [r7, #4]
|
|
8006830: 689b ldr r3, [r3, #8]
|
|
8006832: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8006836: d007 beq.n 8006848 <UART_Receive_IT+0x74>
|
|
8006838: 687b ldr r3, [r7, #4]
|
|
800683a: 689b ldr r3, [r3, #8]
|
|
800683c: 2b00 cmp r3, #0
|
|
800683e: d10a bne.n 8006856 <UART_Receive_IT+0x82>
|
|
8006840: 687b ldr r3, [r7, #4]
|
|
8006842: 691b ldr r3, [r3, #16]
|
|
8006844: 2b00 cmp r3, #0
|
|
8006846: d106 bne.n 8006856 <UART_Receive_IT+0x82>
|
|
{
|
|
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
|
|
8006848: 687b ldr r3, [r7, #4]
|
|
800684a: 681b ldr r3, [r3, #0]
|
|
800684c: 685b ldr r3, [r3, #4]
|
|
800684e: b2da uxtb r2, r3
|
|
8006850: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8006852: 701a strb r2, [r3, #0]
|
|
8006854: e008 b.n 8006868 <UART_Receive_IT+0x94>
|
|
}
|
|
else
|
|
{
|
|
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
|
|
8006856: 687b ldr r3, [r7, #4]
|
|
8006858: 681b ldr r3, [r3, #0]
|
|
800685a: 685b ldr r3, [r3, #4]
|
|
800685c: b2db uxtb r3, r3
|
|
800685e: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8006862: b2da uxtb r2, r3
|
|
8006864: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8006866: 701a strb r2, [r3, #0]
|
|
}
|
|
huart->pRxBuffPtr += 1U;
|
|
8006868: 687b ldr r3, [r7, #4]
|
|
800686a: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800686c: 1c5a adds r2, r3, #1
|
|
800686e: 687b ldr r3, [r7, #4]
|
|
8006870: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
if (--huart->RxXferCount == 0U)
|
|
8006872: 687b ldr r3, [r7, #4]
|
|
8006874: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
8006876: b29b uxth r3, r3
|
|
8006878: 3b01 subs r3, #1
|
|
800687a: b29b uxth r3, r3
|
|
800687c: 687a ldr r2, [r7, #4]
|
|
800687e: 4619 mov r1, r3
|
|
8006880: 85d1 strh r1, [r2, #46] @ 0x2e
|
|
8006882: 2b00 cmp r3, #0
|
|
8006884: d15d bne.n 8006942 <UART_Receive_IT+0x16e>
|
|
{
|
|
/* Disable the UART Data Register not empty Interrupt */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
|
|
8006886: 687b ldr r3, [r7, #4]
|
|
8006888: 681b ldr r3, [r3, #0]
|
|
800688a: 68da ldr r2, [r3, #12]
|
|
800688c: 687b ldr r3, [r7, #4]
|
|
800688e: 681b ldr r3, [r3, #0]
|
|
8006890: f022 0220 bic.w r2, r2, #32
|
|
8006894: 60da str r2, [r3, #12]
|
|
|
|
/* Disable the UART Parity Error Interrupt */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
|
|
8006896: 687b ldr r3, [r7, #4]
|
|
8006898: 681b ldr r3, [r3, #0]
|
|
800689a: 68da ldr r2, [r3, #12]
|
|
800689c: 687b ldr r3, [r7, #4]
|
|
800689e: 681b ldr r3, [r3, #0]
|
|
80068a0: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
80068a4: 60da str r2, [r3, #12]
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
|
|
80068a6: 687b ldr r3, [r7, #4]
|
|
80068a8: 681b ldr r3, [r3, #0]
|
|
80068aa: 695a ldr r2, [r3, #20]
|
|
80068ac: 687b ldr r3, [r7, #4]
|
|
80068ae: 681b ldr r3, [r3, #0]
|
|
80068b0: f022 0201 bic.w r2, r2, #1
|
|
80068b4: 615a str r2, [r3, #20]
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80068b6: 687b ldr r3, [r7, #4]
|
|
80068b8: 2220 movs r2, #32
|
|
80068ba: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
80068be: 687b ldr r3, [r7, #4]
|
|
80068c0: 2200 movs r2, #0
|
|
80068c2: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80068c4: 687b ldr r3, [r7, #4]
|
|
80068c6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80068c8: 2b01 cmp r3, #1
|
|
80068ca: d135 bne.n 8006938 <UART_Receive_IT+0x164>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80068cc: 687b ldr r3, [r7, #4]
|
|
80068ce: 2200 movs r2, #0
|
|
80068d0: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80068d2: 687b ldr r3, [r7, #4]
|
|
80068d4: 681b ldr r3, [r3, #0]
|
|
80068d6: 330c adds r3, #12
|
|
80068d8: 617b str r3, [r7, #20]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80068da: 697b ldr r3, [r7, #20]
|
|
80068dc: e853 3f00 ldrex r3, [r3]
|
|
80068e0: 613b str r3, [r7, #16]
|
|
return(result);
|
|
80068e2: 693b ldr r3, [r7, #16]
|
|
80068e4: f023 0310 bic.w r3, r3, #16
|
|
80068e8: 627b str r3, [r7, #36] @ 0x24
|
|
80068ea: 687b ldr r3, [r7, #4]
|
|
80068ec: 681b ldr r3, [r3, #0]
|
|
80068ee: 330c adds r3, #12
|
|
80068f0: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80068f2: 623a str r2, [r7, #32]
|
|
80068f4: 61fb str r3, [r7, #28]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80068f6: 69f9 ldr r1, [r7, #28]
|
|
80068f8: 6a3a ldr r2, [r7, #32]
|
|
80068fa: e841 2300 strex r3, r2, [r1]
|
|
80068fe: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
8006900: 69bb ldr r3, [r7, #24]
|
|
8006902: 2b00 cmp r3, #0
|
|
8006904: d1e5 bne.n 80068d2 <UART_Receive_IT+0xfe>
|
|
|
|
/* Check if IDLE flag is set */
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
|
|
8006906: 687b ldr r3, [r7, #4]
|
|
8006908: 681b ldr r3, [r3, #0]
|
|
800690a: 681b ldr r3, [r3, #0]
|
|
800690c: f003 0310 and.w r3, r3, #16
|
|
8006910: 2b10 cmp r3, #16
|
|
8006912: d10a bne.n 800692a <UART_Receive_IT+0x156>
|
|
{
|
|
/* Clear IDLE flag in ISR */
|
|
__HAL_UART_CLEAR_IDLEFLAG(huart);
|
|
8006914: 2300 movs r3, #0
|
|
8006916: 60fb str r3, [r7, #12]
|
|
8006918: 687b ldr r3, [r7, #4]
|
|
800691a: 681b ldr r3, [r3, #0]
|
|
800691c: 681b ldr r3, [r3, #0]
|
|
800691e: 60fb str r3, [r7, #12]
|
|
8006920: 687b ldr r3, [r7, #4]
|
|
8006922: 681b ldr r3, [r3, #0]
|
|
8006924: 685b ldr r3, [r3, #4]
|
|
8006926: 60fb str r3, [r7, #12]
|
|
8006928: 68fb ldr r3, [r7, #12]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
800692a: 687b ldr r3, [r7, #4]
|
|
800692c: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
800692e: 4619 mov r1, r3
|
|
8006930: 6878 ldr r0, [r7, #4]
|
|
8006932: f7ff fc3f bl 80061b4 <HAL_UARTEx_RxEventCallback>
|
|
8006936: e002 b.n 800693e <UART_Receive_IT+0x16a>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx complete callback*/
|
|
huart->RxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8006938: 6878 ldr r0, [r7, #4]
|
|
800693a: f7fa f897 bl 8000a6c <HAL_UART_RxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
return HAL_OK;
|
|
800693e: 2300 movs r3, #0
|
|
8006940: e002 b.n 8006948 <UART_Receive_IT+0x174>
|
|
}
|
|
return HAL_OK;
|
|
8006942: 2300 movs r3, #0
|
|
8006944: e000 b.n 8006948 <UART_Receive_IT+0x174>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8006946: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8006948: 4618 mov r0, r3
|
|
800694a: 3730 adds r7, #48 @ 0x30
|
|
800694c: 46bd mov sp, r7
|
|
800694e: bd80 pop {r7, pc}
|
|
|
|
08006950 <UART_SetConfig>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8006950: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8006954: b0c0 sub sp, #256 @ 0x100
|
|
8006956: af00 add r7, sp, #0
|
|
8006958: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4
|
|
assert_param(IS_UART_MODE(huart->Init.Mode));
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits
|
|
according to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
800695c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006960: 681b ldr r3, [r3, #0]
|
|
8006962: 691b ldr r3, [r3, #16]
|
|
8006964: f423 5040 bic.w r0, r3, #12288 @ 0x3000
|
|
8006968: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800696c: 68d9 ldr r1, [r3, #12]
|
|
800696e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006972: 681a ldr r2, [r3, #0]
|
|
8006974: ea40 0301 orr.w r3, r0, r1
|
|
8006978: 6113 str r3, [r2, #16]
|
|
Set the M bits according to huart->Init.WordLength value
|
|
Set PCE and PS bits according to huart->Init.Parity value
|
|
Set TE and RE bits according to huart->Init.Mode value
|
|
Set OVER8 bit according to huart->Init.OverSampling value */
|
|
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
|
|
800697a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800697e: 689a ldr r2, [r3, #8]
|
|
8006980: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006984: 691b ldr r3, [r3, #16]
|
|
8006986: 431a orrs r2, r3
|
|
8006988: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800698c: 695b ldr r3, [r3, #20]
|
|
800698e: 431a orrs r2, r3
|
|
8006990: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006994: 69db ldr r3, [r3, #28]
|
|
8006996: 4313 orrs r3, r2
|
|
8006998: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
800699c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80069a0: 681b ldr r3, [r3, #0]
|
|
80069a2: 68db ldr r3, [r3, #12]
|
|
80069a4: f423 4116 bic.w r1, r3, #38400 @ 0x9600
|
|
80069a8: f021 010c bic.w r1, r1, #12
|
|
80069ac: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80069b0: 681a ldr r2, [r3, #0]
|
|
80069b2: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
|
|
80069b6: 430b orrs r3, r1
|
|
80069b8: 60d3 str r3, [r2, #12]
|
|
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
|
tmpreg);
|
|
|
|
/*-------------------------- USART CR3 Configuration -----------------------*/
|
|
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
|
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
|
80069ba: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80069be: 681b ldr r3, [r3, #0]
|
|
80069c0: 695b ldr r3, [r3, #20]
|
|
80069c2: f423 7040 bic.w r0, r3, #768 @ 0x300
|
|
80069c6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80069ca: 6999 ldr r1, [r3, #24]
|
|
80069cc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80069d0: 681a ldr r2, [r3, #0]
|
|
80069d2: ea40 0301 orr.w r3, r0, r1
|
|
80069d6: 6153 str r3, [r2, #20]
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#elif defined(USART6)
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6))
|
|
80069d8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80069dc: 681a ldr r2, [r3, #0]
|
|
80069de: 4b8f ldr r3, [pc, #572] @ (8006c1c <UART_SetConfig+0x2cc>)
|
|
80069e0: 429a cmp r2, r3
|
|
80069e2: d005 beq.n 80069f0 <UART_SetConfig+0xa0>
|
|
80069e4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80069e8: 681a ldr r2, [r3, #0]
|
|
80069ea: 4b8d ldr r3, [pc, #564] @ (8006c20 <UART_SetConfig+0x2d0>)
|
|
80069ec: 429a cmp r2, r3
|
|
80069ee: d104 bne.n 80069fa <UART_SetConfig+0xaa>
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
80069f0: f7fd fbec bl 80041cc <HAL_RCC_GetPCLK2Freq>
|
|
80069f4: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
80069f8: e003 b.n 8006a02 <UART_SetConfig+0xb2>
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#endif /* USART6 */
|
|
else
|
|
{
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
80069fa: f7fd fbd3 bl 80041a4 <HAL_RCC_GetPCLK1Freq>
|
|
80069fe: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
}
|
|
/*-------------------------- USART BRR Configuration ---------------------*/
|
|
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8006a02: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006a06: 69db ldr r3, [r3, #28]
|
|
8006a08: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8006a0c: f040 810c bne.w 8006c28 <UART_SetConfig+0x2d8>
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
|
|
8006a10: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006a14: 2200 movs r2, #0
|
|
8006a16: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
|
|
8006a1a: f8c7 20ec str.w r2, [r7, #236] @ 0xec
|
|
8006a1e: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8
|
|
8006a22: 4622 mov r2, r4
|
|
8006a24: 462b mov r3, r5
|
|
8006a26: 1891 adds r1, r2, r2
|
|
8006a28: 65b9 str r1, [r7, #88] @ 0x58
|
|
8006a2a: 415b adcs r3, r3
|
|
8006a2c: 65fb str r3, [r7, #92] @ 0x5c
|
|
8006a2e: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
|
|
8006a32: 4621 mov r1, r4
|
|
8006a34: eb12 0801 adds.w r8, r2, r1
|
|
8006a38: 4629 mov r1, r5
|
|
8006a3a: eb43 0901 adc.w r9, r3, r1
|
|
8006a3e: f04f 0200 mov.w r2, #0
|
|
8006a42: f04f 0300 mov.w r3, #0
|
|
8006a46: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8006a4a: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8006a4e: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
8006a52: 4690 mov r8, r2
|
|
8006a54: 4699 mov r9, r3
|
|
8006a56: 4623 mov r3, r4
|
|
8006a58: eb18 0303 adds.w r3, r8, r3
|
|
8006a5c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
8006a60: 462b mov r3, r5
|
|
8006a62: eb49 0303 adc.w r3, r9, r3
|
|
8006a66: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
8006a6a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006a6e: 685b ldr r3, [r3, #4]
|
|
8006a70: 2200 movs r2, #0
|
|
8006a72: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
8006a76: f8c7 20dc str.w r2, [r7, #220] @ 0xdc
|
|
8006a7a: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8
|
|
8006a7e: 460b mov r3, r1
|
|
8006a80: 18db adds r3, r3, r3
|
|
8006a82: 653b str r3, [r7, #80] @ 0x50
|
|
8006a84: 4613 mov r3, r2
|
|
8006a86: eb42 0303 adc.w r3, r2, r3
|
|
8006a8a: 657b str r3, [r7, #84] @ 0x54
|
|
8006a8c: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50
|
|
8006a90: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0
|
|
8006a94: f7f9 fbb6 bl 8000204 <__aeabi_uldivmod>
|
|
8006a98: 4602 mov r2, r0
|
|
8006a9a: 460b mov r3, r1
|
|
8006a9c: 4b61 ldr r3, [pc, #388] @ (8006c24 <UART_SetConfig+0x2d4>)
|
|
8006a9e: fba3 2302 umull r2, r3, r3, r2
|
|
8006aa2: 095b lsrs r3, r3, #5
|
|
8006aa4: 011c lsls r4, r3, #4
|
|
8006aa6: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006aaa: 2200 movs r2, #0
|
|
8006aac: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
8006ab0: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4
|
|
8006ab4: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0
|
|
8006ab8: 4642 mov r2, r8
|
|
8006aba: 464b mov r3, r9
|
|
8006abc: 1891 adds r1, r2, r2
|
|
8006abe: 64b9 str r1, [r7, #72] @ 0x48
|
|
8006ac0: 415b adcs r3, r3
|
|
8006ac2: 64fb str r3, [r7, #76] @ 0x4c
|
|
8006ac4: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
|
|
8006ac8: 4641 mov r1, r8
|
|
8006aca: eb12 0a01 adds.w sl, r2, r1
|
|
8006ace: 4649 mov r1, r9
|
|
8006ad0: eb43 0b01 adc.w fp, r3, r1
|
|
8006ad4: f04f 0200 mov.w r2, #0
|
|
8006ad8: f04f 0300 mov.w r3, #0
|
|
8006adc: ea4f 03cb mov.w r3, fp, lsl #3
|
|
8006ae0: ea43 735a orr.w r3, r3, sl, lsr #29
|
|
8006ae4: ea4f 02ca mov.w r2, sl, lsl #3
|
|
8006ae8: 4692 mov sl, r2
|
|
8006aea: 469b mov fp, r3
|
|
8006aec: 4643 mov r3, r8
|
|
8006aee: eb1a 0303 adds.w r3, sl, r3
|
|
8006af2: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
8006af6: 464b mov r3, r9
|
|
8006af8: eb4b 0303 adc.w r3, fp, r3
|
|
8006afc: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
|
|
8006b00: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006b04: 685b ldr r3, [r3, #4]
|
|
8006b06: 2200 movs r2, #0
|
|
8006b08: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
8006b0c: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4
|
|
8006b10: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0
|
|
8006b14: 460b mov r3, r1
|
|
8006b16: 18db adds r3, r3, r3
|
|
8006b18: 643b str r3, [r7, #64] @ 0x40
|
|
8006b1a: 4613 mov r3, r2
|
|
8006b1c: eb42 0303 adc.w r3, r2, r3
|
|
8006b20: 647b str r3, [r7, #68] @ 0x44
|
|
8006b22: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40
|
|
8006b26: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8
|
|
8006b2a: f7f9 fb6b bl 8000204 <__aeabi_uldivmod>
|
|
8006b2e: 4602 mov r2, r0
|
|
8006b30: 460b mov r3, r1
|
|
8006b32: 4611 mov r1, r2
|
|
8006b34: 4b3b ldr r3, [pc, #236] @ (8006c24 <UART_SetConfig+0x2d4>)
|
|
8006b36: fba3 2301 umull r2, r3, r3, r1
|
|
8006b3a: 095b lsrs r3, r3, #5
|
|
8006b3c: 2264 movs r2, #100 @ 0x64
|
|
8006b3e: fb02 f303 mul.w r3, r2, r3
|
|
8006b42: 1acb subs r3, r1, r3
|
|
8006b44: 00db lsls r3, r3, #3
|
|
8006b46: f103 0232 add.w r2, r3, #50 @ 0x32
|
|
8006b4a: 4b36 ldr r3, [pc, #216] @ (8006c24 <UART_SetConfig+0x2d4>)
|
|
8006b4c: fba3 2302 umull r2, r3, r3, r2
|
|
8006b50: 095b lsrs r3, r3, #5
|
|
8006b52: 005b lsls r3, r3, #1
|
|
8006b54: f403 73f8 and.w r3, r3, #496 @ 0x1f0
|
|
8006b58: 441c add r4, r3
|
|
8006b5a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006b5e: 2200 movs r2, #0
|
|
8006b60: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
8006b64: f8c7 20bc str.w r2, [r7, #188] @ 0xbc
|
|
8006b68: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8
|
|
8006b6c: 4642 mov r2, r8
|
|
8006b6e: 464b mov r3, r9
|
|
8006b70: 1891 adds r1, r2, r2
|
|
8006b72: 63b9 str r1, [r7, #56] @ 0x38
|
|
8006b74: 415b adcs r3, r3
|
|
8006b76: 63fb str r3, [r7, #60] @ 0x3c
|
|
8006b78: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38
|
|
8006b7c: 4641 mov r1, r8
|
|
8006b7e: 1851 adds r1, r2, r1
|
|
8006b80: 6339 str r1, [r7, #48] @ 0x30
|
|
8006b82: 4649 mov r1, r9
|
|
8006b84: 414b adcs r3, r1
|
|
8006b86: 637b str r3, [r7, #52] @ 0x34
|
|
8006b88: f04f 0200 mov.w r2, #0
|
|
8006b8c: f04f 0300 mov.w r3, #0
|
|
8006b90: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30
|
|
8006b94: 4659 mov r1, fp
|
|
8006b96: 00cb lsls r3, r1, #3
|
|
8006b98: 4651 mov r1, sl
|
|
8006b9a: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8006b9e: 4651 mov r1, sl
|
|
8006ba0: 00ca lsls r2, r1, #3
|
|
8006ba2: 4610 mov r0, r2
|
|
8006ba4: 4619 mov r1, r3
|
|
8006ba6: 4603 mov r3, r0
|
|
8006ba8: 4642 mov r2, r8
|
|
8006baa: 189b adds r3, r3, r2
|
|
8006bac: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
8006bb0: 464b mov r3, r9
|
|
8006bb2: 460a mov r2, r1
|
|
8006bb4: eb42 0303 adc.w r3, r2, r3
|
|
8006bb8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8006bbc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006bc0: 685b ldr r3, [r3, #4]
|
|
8006bc2: 2200 movs r2, #0
|
|
8006bc4: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
8006bc8: f8c7 20ac str.w r2, [r7, #172] @ 0xac
|
|
8006bcc: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8
|
|
8006bd0: 460b mov r3, r1
|
|
8006bd2: 18db adds r3, r3, r3
|
|
8006bd4: 62bb str r3, [r7, #40] @ 0x28
|
|
8006bd6: 4613 mov r3, r2
|
|
8006bd8: eb42 0303 adc.w r3, r2, r3
|
|
8006bdc: 62fb str r3, [r7, #44] @ 0x2c
|
|
8006bde: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
|
|
8006be2: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0
|
|
8006be6: f7f9 fb0d bl 8000204 <__aeabi_uldivmod>
|
|
8006bea: 4602 mov r2, r0
|
|
8006bec: 460b mov r3, r1
|
|
8006bee: 4b0d ldr r3, [pc, #52] @ (8006c24 <UART_SetConfig+0x2d4>)
|
|
8006bf0: fba3 1302 umull r1, r3, r3, r2
|
|
8006bf4: 095b lsrs r3, r3, #5
|
|
8006bf6: 2164 movs r1, #100 @ 0x64
|
|
8006bf8: fb01 f303 mul.w r3, r1, r3
|
|
8006bfc: 1ad3 subs r3, r2, r3
|
|
8006bfe: 00db lsls r3, r3, #3
|
|
8006c00: 3332 adds r3, #50 @ 0x32
|
|
8006c02: 4a08 ldr r2, [pc, #32] @ (8006c24 <UART_SetConfig+0x2d4>)
|
|
8006c04: fba2 2303 umull r2, r3, r2, r3
|
|
8006c08: 095b lsrs r3, r3, #5
|
|
8006c0a: f003 0207 and.w r2, r3, #7
|
|
8006c0e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006c12: 681b ldr r3, [r3, #0]
|
|
8006c14: 4422 add r2, r4
|
|
8006c16: 609a str r2, [r3, #8]
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
}
|
|
}
|
|
8006c18: e106 b.n 8006e28 <UART_SetConfig+0x4d8>
|
|
8006c1a: bf00 nop
|
|
8006c1c: 40011000 .word 0x40011000
|
|
8006c20: 40011400 .word 0x40011400
|
|
8006c24: 51eb851f .word 0x51eb851f
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
8006c28: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006c2c: 2200 movs r2, #0
|
|
8006c2e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
8006c32: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4
|
|
8006c36: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0
|
|
8006c3a: 4642 mov r2, r8
|
|
8006c3c: 464b mov r3, r9
|
|
8006c3e: 1891 adds r1, r2, r2
|
|
8006c40: 6239 str r1, [r7, #32]
|
|
8006c42: 415b adcs r3, r3
|
|
8006c44: 627b str r3, [r7, #36] @ 0x24
|
|
8006c46: e9d7 2308 ldrd r2, r3, [r7, #32]
|
|
8006c4a: 4641 mov r1, r8
|
|
8006c4c: 1854 adds r4, r2, r1
|
|
8006c4e: 4649 mov r1, r9
|
|
8006c50: eb43 0501 adc.w r5, r3, r1
|
|
8006c54: f04f 0200 mov.w r2, #0
|
|
8006c58: f04f 0300 mov.w r3, #0
|
|
8006c5c: 00eb lsls r3, r5, #3
|
|
8006c5e: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
8006c62: 00e2 lsls r2, r4, #3
|
|
8006c64: 4614 mov r4, r2
|
|
8006c66: 461d mov r5, r3
|
|
8006c68: 4643 mov r3, r8
|
|
8006c6a: 18e3 adds r3, r4, r3
|
|
8006c6c: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8006c70: 464b mov r3, r9
|
|
8006c72: eb45 0303 adc.w r3, r5, r3
|
|
8006c76: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
8006c7a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006c7e: 685b ldr r3, [r3, #4]
|
|
8006c80: 2200 movs r2, #0
|
|
8006c82: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8006c86: f8c7 2094 str.w r2, [r7, #148] @ 0x94
|
|
8006c8a: f04f 0200 mov.w r2, #0
|
|
8006c8e: f04f 0300 mov.w r3, #0
|
|
8006c92: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
|
|
8006c96: 4629 mov r1, r5
|
|
8006c98: 008b lsls r3, r1, #2
|
|
8006c9a: 4621 mov r1, r4
|
|
8006c9c: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8006ca0: 4621 mov r1, r4
|
|
8006ca2: 008a lsls r2, r1, #2
|
|
8006ca4: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98
|
|
8006ca8: f7f9 faac bl 8000204 <__aeabi_uldivmod>
|
|
8006cac: 4602 mov r2, r0
|
|
8006cae: 460b mov r3, r1
|
|
8006cb0: 4b60 ldr r3, [pc, #384] @ (8006e34 <UART_SetConfig+0x4e4>)
|
|
8006cb2: fba3 2302 umull r2, r3, r3, r2
|
|
8006cb6: 095b lsrs r3, r3, #5
|
|
8006cb8: 011c lsls r4, r3, #4
|
|
8006cba: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006cbe: 2200 movs r2, #0
|
|
8006cc0: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
8006cc4: f8c7 208c str.w r2, [r7, #140] @ 0x8c
|
|
8006cc8: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88
|
|
8006ccc: 4642 mov r2, r8
|
|
8006cce: 464b mov r3, r9
|
|
8006cd0: 1891 adds r1, r2, r2
|
|
8006cd2: 61b9 str r1, [r7, #24]
|
|
8006cd4: 415b adcs r3, r3
|
|
8006cd6: 61fb str r3, [r7, #28]
|
|
8006cd8: e9d7 2306 ldrd r2, r3, [r7, #24]
|
|
8006cdc: 4641 mov r1, r8
|
|
8006cde: 1851 adds r1, r2, r1
|
|
8006ce0: 6139 str r1, [r7, #16]
|
|
8006ce2: 4649 mov r1, r9
|
|
8006ce4: 414b adcs r3, r1
|
|
8006ce6: 617b str r3, [r7, #20]
|
|
8006ce8: f04f 0200 mov.w r2, #0
|
|
8006cec: f04f 0300 mov.w r3, #0
|
|
8006cf0: e9d7 ab04 ldrd sl, fp, [r7, #16]
|
|
8006cf4: 4659 mov r1, fp
|
|
8006cf6: 00cb lsls r3, r1, #3
|
|
8006cf8: 4651 mov r1, sl
|
|
8006cfa: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8006cfe: 4651 mov r1, sl
|
|
8006d00: 00ca lsls r2, r1, #3
|
|
8006d02: 4610 mov r0, r2
|
|
8006d04: 4619 mov r1, r3
|
|
8006d06: 4603 mov r3, r0
|
|
8006d08: 4642 mov r2, r8
|
|
8006d0a: 189b adds r3, r3, r2
|
|
8006d0c: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8006d10: 464b mov r3, r9
|
|
8006d12: 460a mov r2, r1
|
|
8006d14: eb42 0303 adc.w r3, r2, r3
|
|
8006d18: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8006d1c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006d20: 685b ldr r3, [r3, #4]
|
|
8006d22: 2200 movs r2, #0
|
|
8006d24: 67bb str r3, [r7, #120] @ 0x78
|
|
8006d26: 67fa str r2, [r7, #124] @ 0x7c
|
|
8006d28: f04f 0200 mov.w r2, #0
|
|
8006d2c: f04f 0300 mov.w r3, #0
|
|
8006d30: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78
|
|
8006d34: 4649 mov r1, r9
|
|
8006d36: 008b lsls r3, r1, #2
|
|
8006d38: 4641 mov r1, r8
|
|
8006d3a: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8006d3e: 4641 mov r1, r8
|
|
8006d40: 008a lsls r2, r1, #2
|
|
8006d42: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80
|
|
8006d46: f7f9 fa5d bl 8000204 <__aeabi_uldivmod>
|
|
8006d4a: 4602 mov r2, r0
|
|
8006d4c: 460b mov r3, r1
|
|
8006d4e: 4611 mov r1, r2
|
|
8006d50: 4b38 ldr r3, [pc, #224] @ (8006e34 <UART_SetConfig+0x4e4>)
|
|
8006d52: fba3 2301 umull r2, r3, r3, r1
|
|
8006d56: 095b lsrs r3, r3, #5
|
|
8006d58: 2264 movs r2, #100 @ 0x64
|
|
8006d5a: fb02 f303 mul.w r3, r2, r3
|
|
8006d5e: 1acb subs r3, r1, r3
|
|
8006d60: 011b lsls r3, r3, #4
|
|
8006d62: 3332 adds r3, #50 @ 0x32
|
|
8006d64: 4a33 ldr r2, [pc, #204] @ (8006e34 <UART_SetConfig+0x4e4>)
|
|
8006d66: fba2 2303 umull r2, r3, r2, r3
|
|
8006d6a: 095b lsrs r3, r3, #5
|
|
8006d6c: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8006d70: 441c add r4, r3
|
|
8006d72: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006d76: 2200 movs r2, #0
|
|
8006d78: 673b str r3, [r7, #112] @ 0x70
|
|
8006d7a: 677a str r2, [r7, #116] @ 0x74
|
|
8006d7c: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70
|
|
8006d80: 4642 mov r2, r8
|
|
8006d82: 464b mov r3, r9
|
|
8006d84: 1891 adds r1, r2, r2
|
|
8006d86: 60b9 str r1, [r7, #8]
|
|
8006d88: 415b adcs r3, r3
|
|
8006d8a: 60fb str r3, [r7, #12]
|
|
8006d8c: e9d7 2302 ldrd r2, r3, [r7, #8]
|
|
8006d90: 4641 mov r1, r8
|
|
8006d92: 1851 adds r1, r2, r1
|
|
8006d94: 6039 str r1, [r7, #0]
|
|
8006d96: 4649 mov r1, r9
|
|
8006d98: 414b adcs r3, r1
|
|
8006d9a: 607b str r3, [r7, #4]
|
|
8006d9c: f04f 0200 mov.w r2, #0
|
|
8006da0: f04f 0300 mov.w r3, #0
|
|
8006da4: e9d7 ab00 ldrd sl, fp, [r7]
|
|
8006da8: 4659 mov r1, fp
|
|
8006daa: 00cb lsls r3, r1, #3
|
|
8006dac: 4651 mov r1, sl
|
|
8006dae: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8006db2: 4651 mov r1, sl
|
|
8006db4: 00ca lsls r2, r1, #3
|
|
8006db6: 4610 mov r0, r2
|
|
8006db8: 4619 mov r1, r3
|
|
8006dba: 4603 mov r3, r0
|
|
8006dbc: 4642 mov r2, r8
|
|
8006dbe: 189b adds r3, r3, r2
|
|
8006dc0: 66bb str r3, [r7, #104] @ 0x68
|
|
8006dc2: 464b mov r3, r9
|
|
8006dc4: 460a mov r2, r1
|
|
8006dc6: eb42 0303 adc.w r3, r2, r3
|
|
8006dca: 66fb str r3, [r7, #108] @ 0x6c
|
|
8006dcc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006dd0: 685b ldr r3, [r3, #4]
|
|
8006dd2: 2200 movs r2, #0
|
|
8006dd4: 663b str r3, [r7, #96] @ 0x60
|
|
8006dd6: 667a str r2, [r7, #100] @ 0x64
|
|
8006dd8: f04f 0200 mov.w r2, #0
|
|
8006ddc: f04f 0300 mov.w r3, #0
|
|
8006de0: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60
|
|
8006de4: 4649 mov r1, r9
|
|
8006de6: 008b lsls r3, r1, #2
|
|
8006de8: 4641 mov r1, r8
|
|
8006dea: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8006dee: 4641 mov r1, r8
|
|
8006df0: 008a lsls r2, r1, #2
|
|
8006df2: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68
|
|
8006df6: f7f9 fa05 bl 8000204 <__aeabi_uldivmod>
|
|
8006dfa: 4602 mov r2, r0
|
|
8006dfc: 460b mov r3, r1
|
|
8006dfe: 4b0d ldr r3, [pc, #52] @ (8006e34 <UART_SetConfig+0x4e4>)
|
|
8006e00: fba3 1302 umull r1, r3, r3, r2
|
|
8006e04: 095b lsrs r3, r3, #5
|
|
8006e06: 2164 movs r1, #100 @ 0x64
|
|
8006e08: fb01 f303 mul.w r3, r1, r3
|
|
8006e0c: 1ad3 subs r3, r2, r3
|
|
8006e0e: 011b lsls r3, r3, #4
|
|
8006e10: 3332 adds r3, #50 @ 0x32
|
|
8006e12: 4a08 ldr r2, [pc, #32] @ (8006e34 <UART_SetConfig+0x4e4>)
|
|
8006e14: fba2 2303 umull r2, r3, r2, r3
|
|
8006e18: 095b lsrs r3, r3, #5
|
|
8006e1a: f003 020f and.w r2, r3, #15
|
|
8006e1e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006e22: 681b ldr r3, [r3, #0]
|
|
8006e24: 4422 add r2, r4
|
|
8006e26: 609a str r2, [r3, #8]
|
|
}
|
|
8006e28: bf00 nop
|
|
8006e2a: f507 7780 add.w r7, r7, #256 @ 0x100
|
|
8006e2e: 46bd mov sp, r7
|
|
8006e30: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8006e34: 51eb851f .word 0x51eb851f
|
|
|
|
08006e38 <USB_CoreInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8006e38: b084 sub sp, #16
|
|
8006e3a: b580 push {r7, lr}
|
|
8006e3c: b084 sub sp, #16
|
|
8006e3e: af00 add r7, sp, #0
|
|
8006e40: 6078 str r0, [r7, #4]
|
|
8006e42: f107 001c add.w r0, r7, #28
|
|
8006e46: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret;
|
|
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
|
|
8006e4a: f897 3021 ldrb.w r3, [r7, #33] @ 0x21
|
|
8006e4e: 2b01 cmp r3, #1
|
|
8006e50: d123 bne.n 8006e9a <USB_CoreInit+0x62>
|
|
{
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
8006e52: 687b ldr r3, [r7, #4]
|
|
8006e54: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006e56: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
8006e5a: 687b ldr r3, [r7, #4]
|
|
8006e5c: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Init The ULPI Interface */
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
|
|
8006e5e: 687b ldr r3, [r7, #4]
|
|
8006e60: 68db ldr r3, [r3, #12]
|
|
8006e62: f423 0384 bic.w r3, r3, #4325376 @ 0x420000
|
|
8006e66: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8006e6a: 687a ldr r2, [r7, #4]
|
|
8006e6c: 60d3 str r3, [r2, #12]
|
|
|
|
/* Select vbus source */
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
|
|
8006e6e: 687b ldr r3, [r7, #4]
|
|
8006e70: 68db ldr r3, [r3, #12]
|
|
8006e72: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
8006e76: 687b ldr r3, [r7, #4]
|
|
8006e78: 60da str r2, [r3, #12]
|
|
if (cfg.use_external_vbus == 1U)
|
|
8006e7a: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8006e7e: 2b01 cmp r3, #1
|
|
8006e80: d105 bne.n 8006e8e <USB_CoreInit+0x56>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
|
|
8006e82: 687b ldr r3, [r7, #4]
|
|
8006e84: 68db ldr r3, [r3, #12]
|
|
8006e86: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
|
|
8006e8a: 687b ldr r3, [r7, #4]
|
|
8006e8c: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
8006e8e: 6878 ldr r0, [r7, #4]
|
|
8006e90: f001 fae2 bl 8008458 <USB_CoreReset>
|
|
8006e94: 4603 mov r3, r0
|
|
8006e96: 73fb strb r3, [r7, #15]
|
|
8006e98: e01b b.n 8006ed2 <USB_CoreInit+0x9a>
|
|
}
|
|
else /* FS interface (embedded Phy) */
|
|
{
|
|
/* Select FS Embedded PHY */
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
|
|
8006e9a: 687b ldr r3, [r7, #4]
|
|
8006e9c: 68db ldr r3, [r3, #12]
|
|
8006e9e: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
8006ea2: 687b ldr r3, [r7, #4]
|
|
8006ea4: 60da str r2, [r3, #12]
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
8006ea6: 6878 ldr r0, [r7, #4]
|
|
8006ea8: f001 fad6 bl 8008458 <USB_CoreReset>
|
|
8006eac: 4603 mov r3, r0
|
|
8006eae: 73fb strb r3, [r7, #15]
|
|
|
|
if (cfg.battery_charging_enable == 0U)
|
|
8006eb0: f897 3025 ldrb.w r3, [r7, #37] @ 0x25
|
|
8006eb4: 2b00 cmp r3, #0
|
|
8006eb6: d106 bne.n 8006ec6 <USB_CoreInit+0x8e>
|
|
{
|
|
/* Activate the USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
8006eb8: 687b ldr r3, [r7, #4]
|
|
8006eba: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006ebc: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
8006ec0: 687b ldr r3, [r7, #4]
|
|
8006ec2: 639a str r2, [r3, #56] @ 0x38
|
|
8006ec4: e005 b.n 8006ed2 <USB_CoreInit+0x9a>
|
|
}
|
|
else
|
|
{
|
|
/* Deactivate the USB Transceiver */
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
8006ec6: 687b ldr r3, [r7, #4]
|
|
8006ec8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006eca: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
8006ece: 687b ldr r3, [r7, #4]
|
|
8006ed0: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
}
|
|
|
|
if (cfg.dma_enable == 1U)
|
|
8006ed2: 7fbb ldrb r3, [r7, #30]
|
|
8006ed4: 2b01 cmp r3, #1
|
|
8006ed6: d10b bne.n 8006ef0 <USB_CoreInit+0xb8>
|
|
{
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
|
|
8006ed8: 687b ldr r3, [r7, #4]
|
|
8006eda: 689b ldr r3, [r3, #8]
|
|
8006edc: f043 0206 orr.w r2, r3, #6
|
|
8006ee0: 687b ldr r3, [r7, #4]
|
|
8006ee2: 609a str r2, [r3, #8]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
|
|
8006ee4: 687b ldr r3, [r7, #4]
|
|
8006ee6: 689b ldr r3, [r3, #8]
|
|
8006ee8: f043 0220 orr.w r2, r3, #32
|
|
8006eec: 687b ldr r3, [r7, #4]
|
|
8006eee: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
return ret;
|
|
8006ef0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8006ef2: 4618 mov r0, r3
|
|
8006ef4: 3710 adds r7, #16
|
|
8006ef6: 46bd mov sp, r7
|
|
8006ef8: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
8006efc: b004 add sp, #16
|
|
8006efe: 4770 bx lr
|
|
|
|
08006f00 <USB_SetTurnaroundTime>:
|
|
* @param hclk: AHB clock frequency
|
|
* @retval USB turnaround time In PHY Clocks number
|
|
*/
|
|
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
|
|
uint32_t hclk, uint8_t speed)
|
|
{
|
|
8006f00: b480 push {r7}
|
|
8006f02: b087 sub sp, #28
|
|
8006f04: af00 add r7, sp, #0
|
|
8006f06: 60f8 str r0, [r7, #12]
|
|
8006f08: 60b9 str r1, [r7, #8]
|
|
8006f0a: 4613 mov r3, r2
|
|
8006f0c: 71fb strb r3, [r7, #7]
|
|
|
|
/* The USBTRD is configured according to the tables below, depending on AHB frequency
|
|
used by application. In the low AHB frequency range it is used to stretch enough the USB response
|
|
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
|
|
latency to the Data FIFO */
|
|
if (speed == USBD_FS_SPEED)
|
|
8006f0e: 79fb ldrb r3, [r7, #7]
|
|
8006f10: 2b02 cmp r3, #2
|
|
8006f12: d165 bne.n 8006fe0 <USB_SetTurnaroundTime+0xe0>
|
|
{
|
|
if ((hclk >= 14200000U) && (hclk < 15000000U))
|
|
8006f14: 68bb ldr r3, [r7, #8]
|
|
8006f16: 4a41 ldr r2, [pc, #260] @ (800701c <USB_SetTurnaroundTime+0x11c>)
|
|
8006f18: 4293 cmp r3, r2
|
|
8006f1a: d906 bls.n 8006f2a <USB_SetTurnaroundTime+0x2a>
|
|
8006f1c: 68bb ldr r3, [r7, #8]
|
|
8006f1e: 4a40 ldr r2, [pc, #256] @ (8007020 <USB_SetTurnaroundTime+0x120>)
|
|
8006f20: 4293 cmp r3, r2
|
|
8006f22: d202 bcs.n 8006f2a <USB_SetTurnaroundTime+0x2a>
|
|
{
|
|
/* hclk Clock Range between 14.2-15 MHz */
|
|
UsbTrd = 0xFU;
|
|
8006f24: 230f movs r3, #15
|
|
8006f26: 617b str r3, [r7, #20]
|
|
8006f28: e062 b.n 8006ff0 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 15000000U) && (hclk < 16000000U))
|
|
8006f2a: 68bb ldr r3, [r7, #8]
|
|
8006f2c: 4a3c ldr r2, [pc, #240] @ (8007020 <USB_SetTurnaroundTime+0x120>)
|
|
8006f2e: 4293 cmp r3, r2
|
|
8006f30: d306 bcc.n 8006f40 <USB_SetTurnaroundTime+0x40>
|
|
8006f32: 68bb ldr r3, [r7, #8]
|
|
8006f34: 4a3b ldr r2, [pc, #236] @ (8007024 <USB_SetTurnaroundTime+0x124>)
|
|
8006f36: 4293 cmp r3, r2
|
|
8006f38: d202 bcs.n 8006f40 <USB_SetTurnaroundTime+0x40>
|
|
{
|
|
/* hclk Clock Range between 15-16 MHz */
|
|
UsbTrd = 0xEU;
|
|
8006f3a: 230e movs r3, #14
|
|
8006f3c: 617b str r3, [r7, #20]
|
|
8006f3e: e057 b.n 8006ff0 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 16000000U) && (hclk < 17200000U))
|
|
8006f40: 68bb ldr r3, [r7, #8]
|
|
8006f42: 4a38 ldr r2, [pc, #224] @ (8007024 <USB_SetTurnaroundTime+0x124>)
|
|
8006f44: 4293 cmp r3, r2
|
|
8006f46: d306 bcc.n 8006f56 <USB_SetTurnaroundTime+0x56>
|
|
8006f48: 68bb ldr r3, [r7, #8]
|
|
8006f4a: 4a37 ldr r2, [pc, #220] @ (8007028 <USB_SetTurnaroundTime+0x128>)
|
|
8006f4c: 4293 cmp r3, r2
|
|
8006f4e: d202 bcs.n 8006f56 <USB_SetTurnaroundTime+0x56>
|
|
{
|
|
/* hclk Clock Range between 16-17.2 MHz */
|
|
UsbTrd = 0xDU;
|
|
8006f50: 230d movs r3, #13
|
|
8006f52: 617b str r3, [r7, #20]
|
|
8006f54: e04c b.n 8006ff0 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 17200000U) && (hclk < 18500000U))
|
|
8006f56: 68bb ldr r3, [r7, #8]
|
|
8006f58: 4a33 ldr r2, [pc, #204] @ (8007028 <USB_SetTurnaroundTime+0x128>)
|
|
8006f5a: 4293 cmp r3, r2
|
|
8006f5c: d306 bcc.n 8006f6c <USB_SetTurnaroundTime+0x6c>
|
|
8006f5e: 68bb ldr r3, [r7, #8]
|
|
8006f60: 4a32 ldr r2, [pc, #200] @ (800702c <USB_SetTurnaroundTime+0x12c>)
|
|
8006f62: 4293 cmp r3, r2
|
|
8006f64: d802 bhi.n 8006f6c <USB_SetTurnaroundTime+0x6c>
|
|
{
|
|
/* hclk Clock Range between 17.2-18.5 MHz */
|
|
UsbTrd = 0xCU;
|
|
8006f66: 230c movs r3, #12
|
|
8006f68: 617b str r3, [r7, #20]
|
|
8006f6a: e041 b.n 8006ff0 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 18500000U) && (hclk < 20000000U))
|
|
8006f6c: 68bb ldr r3, [r7, #8]
|
|
8006f6e: 4a2f ldr r2, [pc, #188] @ (800702c <USB_SetTurnaroundTime+0x12c>)
|
|
8006f70: 4293 cmp r3, r2
|
|
8006f72: d906 bls.n 8006f82 <USB_SetTurnaroundTime+0x82>
|
|
8006f74: 68bb ldr r3, [r7, #8]
|
|
8006f76: 4a2e ldr r2, [pc, #184] @ (8007030 <USB_SetTurnaroundTime+0x130>)
|
|
8006f78: 4293 cmp r3, r2
|
|
8006f7a: d802 bhi.n 8006f82 <USB_SetTurnaroundTime+0x82>
|
|
{
|
|
/* hclk Clock Range between 18.5-20 MHz */
|
|
UsbTrd = 0xBU;
|
|
8006f7c: 230b movs r3, #11
|
|
8006f7e: 617b str r3, [r7, #20]
|
|
8006f80: e036 b.n 8006ff0 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 20000000U) && (hclk < 21800000U))
|
|
8006f82: 68bb ldr r3, [r7, #8]
|
|
8006f84: 4a2a ldr r2, [pc, #168] @ (8007030 <USB_SetTurnaroundTime+0x130>)
|
|
8006f86: 4293 cmp r3, r2
|
|
8006f88: d906 bls.n 8006f98 <USB_SetTurnaroundTime+0x98>
|
|
8006f8a: 68bb ldr r3, [r7, #8]
|
|
8006f8c: 4a29 ldr r2, [pc, #164] @ (8007034 <USB_SetTurnaroundTime+0x134>)
|
|
8006f8e: 4293 cmp r3, r2
|
|
8006f90: d802 bhi.n 8006f98 <USB_SetTurnaroundTime+0x98>
|
|
{
|
|
/* hclk Clock Range between 20-21.8 MHz */
|
|
UsbTrd = 0xAU;
|
|
8006f92: 230a movs r3, #10
|
|
8006f94: 617b str r3, [r7, #20]
|
|
8006f96: e02b b.n 8006ff0 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 21800000U) && (hclk < 24000000U))
|
|
8006f98: 68bb ldr r3, [r7, #8]
|
|
8006f9a: 4a26 ldr r2, [pc, #152] @ (8007034 <USB_SetTurnaroundTime+0x134>)
|
|
8006f9c: 4293 cmp r3, r2
|
|
8006f9e: d906 bls.n 8006fae <USB_SetTurnaroundTime+0xae>
|
|
8006fa0: 68bb ldr r3, [r7, #8]
|
|
8006fa2: 4a25 ldr r2, [pc, #148] @ (8007038 <USB_SetTurnaroundTime+0x138>)
|
|
8006fa4: 4293 cmp r3, r2
|
|
8006fa6: d202 bcs.n 8006fae <USB_SetTurnaroundTime+0xae>
|
|
{
|
|
/* hclk Clock Range between 21.8-24 MHz */
|
|
UsbTrd = 0x9U;
|
|
8006fa8: 2309 movs r3, #9
|
|
8006faa: 617b str r3, [r7, #20]
|
|
8006fac: e020 b.n 8006ff0 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 24000000U) && (hclk < 27700000U))
|
|
8006fae: 68bb ldr r3, [r7, #8]
|
|
8006fb0: 4a21 ldr r2, [pc, #132] @ (8007038 <USB_SetTurnaroundTime+0x138>)
|
|
8006fb2: 4293 cmp r3, r2
|
|
8006fb4: d306 bcc.n 8006fc4 <USB_SetTurnaroundTime+0xc4>
|
|
8006fb6: 68bb ldr r3, [r7, #8]
|
|
8006fb8: 4a20 ldr r2, [pc, #128] @ (800703c <USB_SetTurnaroundTime+0x13c>)
|
|
8006fba: 4293 cmp r3, r2
|
|
8006fbc: d802 bhi.n 8006fc4 <USB_SetTurnaroundTime+0xc4>
|
|
{
|
|
/* hclk Clock Range between 24-27.7 MHz */
|
|
UsbTrd = 0x8U;
|
|
8006fbe: 2308 movs r3, #8
|
|
8006fc0: 617b str r3, [r7, #20]
|
|
8006fc2: e015 b.n 8006ff0 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else if ((hclk >= 27700000U) && (hclk < 32000000U))
|
|
8006fc4: 68bb ldr r3, [r7, #8]
|
|
8006fc6: 4a1d ldr r2, [pc, #116] @ (800703c <USB_SetTurnaroundTime+0x13c>)
|
|
8006fc8: 4293 cmp r3, r2
|
|
8006fca: d906 bls.n 8006fda <USB_SetTurnaroundTime+0xda>
|
|
8006fcc: 68bb ldr r3, [r7, #8]
|
|
8006fce: 4a1c ldr r2, [pc, #112] @ (8007040 <USB_SetTurnaroundTime+0x140>)
|
|
8006fd0: 4293 cmp r3, r2
|
|
8006fd2: d202 bcs.n 8006fda <USB_SetTurnaroundTime+0xda>
|
|
{
|
|
/* hclk Clock Range between 27.7-32 MHz */
|
|
UsbTrd = 0x7U;
|
|
8006fd4: 2307 movs r3, #7
|
|
8006fd6: 617b str r3, [r7, #20]
|
|
8006fd8: e00a b.n 8006ff0 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else /* if(hclk >= 32000000) */
|
|
{
|
|
/* hclk Clock Range between 32-200 MHz */
|
|
UsbTrd = 0x6U;
|
|
8006fda: 2306 movs r3, #6
|
|
8006fdc: 617b str r3, [r7, #20]
|
|
8006fde: e007 b.n 8006ff0 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
}
|
|
else if (speed == USBD_HS_SPEED)
|
|
8006fe0: 79fb ldrb r3, [r7, #7]
|
|
8006fe2: 2b00 cmp r3, #0
|
|
8006fe4: d102 bne.n 8006fec <USB_SetTurnaroundTime+0xec>
|
|
{
|
|
UsbTrd = USBD_HS_TRDT_VALUE;
|
|
8006fe6: 2309 movs r3, #9
|
|
8006fe8: 617b str r3, [r7, #20]
|
|
8006fea: e001 b.n 8006ff0 <USB_SetTurnaroundTime+0xf0>
|
|
}
|
|
else
|
|
{
|
|
UsbTrd = USBD_DEFAULT_TRDT_VALUE;
|
|
8006fec: 2309 movs r3, #9
|
|
8006fee: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
|
|
8006ff0: 68fb ldr r3, [r7, #12]
|
|
8006ff2: 68db ldr r3, [r3, #12]
|
|
8006ff4: f423 5270 bic.w r2, r3, #15360 @ 0x3c00
|
|
8006ff8: 68fb ldr r3, [r7, #12]
|
|
8006ffa: 60da str r2, [r3, #12]
|
|
USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
|
|
8006ffc: 68fb ldr r3, [r7, #12]
|
|
8006ffe: 68da ldr r2, [r3, #12]
|
|
8007000: 697b ldr r3, [r7, #20]
|
|
8007002: 029b lsls r3, r3, #10
|
|
8007004: f403 5370 and.w r3, r3, #15360 @ 0x3c00
|
|
8007008: 431a orrs r2, r3
|
|
800700a: 68fb ldr r3, [r7, #12]
|
|
800700c: 60da str r2, [r3, #12]
|
|
|
|
return HAL_OK;
|
|
800700e: 2300 movs r3, #0
|
|
}
|
|
8007010: 4618 mov r0, r3
|
|
8007012: 371c adds r7, #28
|
|
8007014: 46bd mov sp, r7
|
|
8007016: f85d 7b04 ldr.w r7, [sp], #4
|
|
800701a: 4770 bx lr
|
|
800701c: 00d8acbf .word 0x00d8acbf
|
|
8007020: 00e4e1c0 .word 0x00e4e1c0
|
|
8007024: 00f42400 .word 0x00f42400
|
|
8007028: 01067380 .word 0x01067380
|
|
800702c: 011a499f .word 0x011a499f
|
|
8007030: 01312cff .word 0x01312cff
|
|
8007034: 014ca43f .word 0x014ca43f
|
|
8007038: 016e3600 .word 0x016e3600
|
|
800703c: 01a6ab1f .word 0x01a6ab1f
|
|
8007040: 01e84800 .word 0x01e84800
|
|
|
|
08007044 <USB_EnableGlobalInt>:
|
|
* Enables the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8007044: b480 push {r7}
|
|
8007046: b083 sub sp, #12
|
|
8007048: af00 add r7, sp, #0
|
|
800704a: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
|
|
800704c: 687b ldr r3, [r7, #4]
|
|
800704e: 689b ldr r3, [r3, #8]
|
|
8007050: f043 0201 orr.w r2, r3, #1
|
|
8007054: 687b ldr r3, [r7, #4]
|
|
8007056: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
8007058: 2300 movs r3, #0
|
|
}
|
|
800705a: 4618 mov r0, r3
|
|
800705c: 370c adds r7, #12
|
|
800705e: 46bd mov sp, r7
|
|
8007060: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007064: 4770 bx lr
|
|
|
|
08007066 <USB_DisableGlobalInt>:
|
|
* Disable the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8007066: b480 push {r7}
|
|
8007068: b083 sub sp, #12
|
|
800706a: af00 add r7, sp, #0
|
|
800706c: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
|
|
800706e: 687b ldr r3, [r7, #4]
|
|
8007070: 689b ldr r3, [r3, #8]
|
|
8007072: f023 0201 bic.w r2, r3, #1
|
|
8007076: 687b ldr r3, [r7, #4]
|
|
8007078: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
800707a: 2300 movs r3, #0
|
|
}
|
|
800707c: 4618 mov r0, r3
|
|
800707e: 370c adds r7, #12
|
|
8007080: 46bd mov sp, r7
|
|
8007082: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007086: 4770 bx lr
|
|
|
|
08007088 <USB_SetCurrentMode>:
|
|
* @arg USB_DEVICE_MODE Peripheral mode
|
|
* @arg USB_HOST_MODE Host mode
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
|
|
{
|
|
8007088: b580 push {r7, lr}
|
|
800708a: b084 sub sp, #16
|
|
800708c: af00 add r7, sp, #0
|
|
800708e: 6078 str r0, [r7, #4]
|
|
8007090: 460b mov r3, r1
|
|
8007092: 70fb strb r3, [r7, #3]
|
|
uint32_t ms = 0U;
|
|
8007094: 2300 movs r3, #0
|
|
8007096: 60fb str r3, [r7, #12]
|
|
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
|
|
8007098: 687b ldr r3, [r7, #4]
|
|
800709a: 68db ldr r3, [r3, #12]
|
|
800709c: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000
|
|
80070a0: 687b ldr r3, [r7, #4]
|
|
80070a2: 60da str r2, [r3, #12]
|
|
|
|
if (mode == USB_HOST_MODE)
|
|
80070a4: 78fb ldrb r3, [r7, #3]
|
|
80070a6: 2b01 cmp r3, #1
|
|
80070a8: d115 bne.n 80070d6 <USB_SetCurrentMode+0x4e>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
|
|
80070aa: 687b ldr r3, [r7, #4]
|
|
80070ac: 68db ldr r3, [r3, #12]
|
|
80070ae: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000
|
|
80070b2: 687b ldr r3, [r7, #4]
|
|
80070b4: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
80070b6: 200a movs r0, #10
|
|
80070b8: f7fa fcba bl 8001a30 <HAL_Delay>
|
|
ms += 10U;
|
|
80070bc: 68fb ldr r3, [r7, #12]
|
|
80070be: 330a adds r3, #10
|
|
80070c0: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
80070c2: 6878 ldr r0, [r7, #4]
|
|
80070c4: f001 f939 bl 800833a <USB_GetMode>
|
|
80070c8: 4603 mov r3, r0
|
|
80070ca: 2b01 cmp r3, #1
|
|
80070cc: d01e beq.n 800710c <USB_SetCurrentMode+0x84>
|
|
80070ce: 68fb ldr r3, [r7, #12]
|
|
80070d0: 2bc7 cmp r3, #199 @ 0xc7
|
|
80070d2: d9f0 bls.n 80070b6 <USB_SetCurrentMode+0x2e>
|
|
80070d4: e01a b.n 800710c <USB_SetCurrentMode+0x84>
|
|
}
|
|
else if (mode == USB_DEVICE_MODE)
|
|
80070d6: 78fb ldrb r3, [r7, #3]
|
|
80070d8: 2b00 cmp r3, #0
|
|
80070da: d115 bne.n 8007108 <USB_SetCurrentMode+0x80>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
|
|
80070dc: 687b ldr r3, [r7, #4]
|
|
80070de: 68db ldr r3, [r3, #12]
|
|
80070e0: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000
|
|
80070e4: 687b ldr r3, [r7, #4]
|
|
80070e6: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
80070e8: 200a movs r0, #10
|
|
80070ea: f7fa fca1 bl 8001a30 <HAL_Delay>
|
|
ms += 10U;
|
|
80070ee: 68fb ldr r3, [r7, #12]
|
|
80070f0: 330a adds r3, #10
|
|
80070f2: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
80070f4: 6878 ldr r0, [r7, #4]
|
|
80070f6: f001 f920 bl 800833a <USB_GetMode>
|
|
80070fa: 4603 mov r3, r0
|
|
80070fc: 2b00 cmp r3, #0
|
|
80070fe: d005 beq.n 800710c <USB_SetCurrentMode+0x84>
|
|
8007100: 68fb ldr r3, [r7, #12]
|
|
8007102: 2bc7 cmp r3, #199 @ 0xc7
|
|
8007104: d9f0 bls.n 80070e8 <USB_SetCurrentMode+0x60>
|
|
8007106: e001 b.n 800710c <USB_SetCurrentMode+0x84>
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
8007108: 2301 movs r3, #1
|
|
800710a: e005 b.n 8007118 <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
|
|
800710c: 68fb ldr r3, [r7, #12]
|
|
800710e: 2bc8 cmp r3, #200 @ 0xc8
|
|
8007110: d101 bne.n 8007116 <USB_SetCurrentMode+0x8e>
|
|
{
|
|
return HAL_ERROR;
|
|
8007112: 2301 movs r3, #1
|
|
8007114: e000 b.n 8007118 <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007116: 2300 movs r3, #0
|
|
}
|
|
8007118: 4618 mov r0, r3
|
|
800711a: 3710 adds r7, #16
|
|
800711c: 46bd mov sp, r7
|
|
800711e: bd80 pop {r7, pc}
|
|
|
|
08007120 <USB_DevInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8007120: b084 sub sp, #16
|
|
8007122: b580 push {r7, lr}
|
|
8007124: b086 sub sp, #24
|
|
8007126: af00 add r7, sp, #0
|
|
8007128: 6078 str r0, [r7, #4]
|
|
800712a: f107 0024 add.w r0, r7, #36 @ 0x24
|
|
800712e: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8007132: 2300 movs r3, #0
|
|
8007134: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007136: 687b ldr r3, [r7, #4]
|
|
8007138: 60fb str r3, [r7, #12]
|
|
uint32_t i;
|
|
|
|
for (i = 0U; i < 15U; i++)
|
|
800713a: 2300 movs r3, #0
|
|
800713c: 613b str r3, [r7, #16]
|
|
800713e: e009 b.n 8007154 <USB_DevInit+0x34>
|
|
{
|
|
USBx->DIEPTXF[i] = 0U;
|
|
8007140: 687a ldr r2, [r7, #4]
|
|
8007142: 693b ldr r3, [r7, #16]
|
|
8007144: 3340 adds r3, #64 @ 0x40
|
|
8007146: 009b lsls r3, r3, #2
|
|
8007148: 4413 add r3, r2
|
|
800714a: 2200 movs r2, #0
|
|
800714c: 605a str r2, [r3, #4]
|
|
for (i = 0U; i < 15U; i++)
|
|
800714e: 693b ldr r3, [r7, #16]
|
|
8007150: 3301 adds r3, #1
|
|
8007152: 613b str r3, [r7, #16]
|
|
8007154: 693b ldr r3, [r7, #16]
|
|
8007156: 2b0e cmp r3, #14
|
|
8007158: d9f2 bls.n 8007140 <USB_DevInit+0x20>
|
|
|
|
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \
|
|
|| defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \
|
|
|| defined(STM32F423xx)
|
|
/* VBUS Sensing setup */
|
|
if (cfg.vbus_sensing_enable == 0U)
|
|
800715a: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
800715e: 2b00 cmp r3, #0
|
|
8007160: d11c bne.n 800719c <USB_DevInit+0x7c>
|
|
{
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
8007162: 68fb ldr r3, [r7, #12]
|
|
8007164: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007168: 685b ldr r3, [r3, #4]
|
|
800716a: 68fa ldr r2, [r7, #12]
|
|
800716c: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8007170: f043 0302 orr.w r3, r3, #2
|
|
8007174: 6053 str r3, [r2, #4]
|
|
|
|
/* Deactivate VBUS Sensing B */
|
|
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
|
|
8007176: 687b ldr r3, [r7, #4]
|
|
8007178: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800717a: f423 1200 bic.w r2, r3, #2097152 @ 0x200000
|
|
800717e: 687b ldr r3, [r7, #4]
|
|
8007180: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* B-peripheral session valid override enable */
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
|
|
8007182: 687b ldr r3, [r7, #4]
|
|
8007184: 681b ldr r3, [r3, #0]
|
|
8007186: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
800718a: 687b ldr r3, [r7, #4]
|
|
800718c: 601a str r2, [r3, #0]
|
|
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
|
|
800718e: 687b ldr r3, [r7, #4]
|
|
8007190: 681b ldr r3, [r3, #0]
|
|
8007192: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
8007196: 687b ldr r3, [r7, #4]
|
|
8007198: 601a str r2, [r3, #0]
|
|
800719a: e005 b.n 80071a8 <USB_DevInit+0x88>
|
|
}
|
|
else
|
|
{
|
|
/* Enable HW VBUS sensing */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
|
|
800719c: 687b ldr r3, [r7, #4]
|
|
800719e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80071a0: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
|
|
80071a4: 687b ldr r3, [r7, #4]
|
|
80071a6: 639a str r2, [r3, #56] @ 0x38
|
|
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
|
|
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
|
|
defined(STM32F423xx) */
|
|
|
|
/* Restart the Phy Clock */
|
|
USBx_PCGCCTL = 0U;
|
|
80071a8: 68fb ldr r3, [r7, #12]
|
|
80071aa: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80071ae: 461a mov r2, r3
|
|
80071b0: 2300 movs r3, #0
|
|
80071b2: 6013 str r3, [r2, #0]
|
|
|
|
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
|
|
80071b4: f897 3029 ldrb.w r3, [r7, #41] @ 0x29
|
|
80071b8: 2b01 cmp r3, #1
|
|
80071ba: d10d bne.n 80071d8 <USB_DevInit+0xb8>
|
|
{
|
|
if (cfg.speed == USBD_HS_SPEED)
|
|
80071bc: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80071c0: 2b00 cmp r3, #0
|
|
80071c2: d104 bne.n 80071ce <USB_DevInit+0xae>
|
|
{
|
|
/* Set Core speed to High speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
|
|
80071c4: 2100 movs r1, #0
|
|
80071c6: 6878 ldr r0, [r7, #4]
|
|
80071c8: f000 f968 bl 800749c <USB_SetDevSpeed>
|
|
80071cc: e008 b.n 80071e0 <USB_DevInit+0xc0>
|
|
}
|
|
else
|
|
{
|
|
/* Set Core speed to Full speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
|
|
80071ce: 2101 movs r1, #1
|
|
80071d0: 6878 ldr r0, [r7, #4]
|
|
80071d2: f000 f963 bl 800749c <USB_SetDevSpeed>
|
|
80071d6: e003 b.n 80071e0 <USB_DevInit+0xc0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set Core speed to Full speed mode */
|
|
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
|
|
80071d8: 2103 movs r1, #3
|
|
80071da: 6878 ldr r0, [r7, #4]
|
|
80071dc: f000 f95e bl 800749c <USB_SetDevSpeed>
|
|
}
|
|
|
|
/* Flush the FIFOs */
|
|
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
|
|
80071e0: 2110 movs r1, #16
|
|
80071e2: 6878 ldr r0, [r7, #4]
|
|
80071e4: f000 f8fa bl 80073dc <USB_FlushTxFifo>
|
|
80071e8: 4603 mov r3, r0
|
|
80071ea: 2b00 cmp r3, #0
|
|
80071ec: d001 beq.n 80071f2 <USB_DevInit+0xd2>
|
|
{
|
|
ret = HAL_ERROR;
|
|
80071ee: 2301 movs r3, #1
|
|
80071f0: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (USB_FlushRxFifo(USBx) != HAL_OK)
|
|
80071f2: 6878 ldr r0, [r7, #4]
|
|
80071f4: f000 f924 bl 8007440 <USB_FlushRxFifo>
|
|
80071f8: 4603 mov r3, r0
|
|
80071fa: 2b00 cmp r3, #0
|
|
80071fc: d001 beq.n 8007202 <USB_DevInit+0xe2>
|
|
{
|
|
ret = HAL_ERROR;
|
|
80071fe: 2301 movs r3, #1
|
|
8007200: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Clear all pending Device Interrupts */
|
|
USBx_DEVICE->DIEPMSK = 0U;
|
|
8007202: 68fb ldr r3, [r7, #12]
|
|
8007204: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007208: 461a mov r2, r3
|
|
800720a: 2300 movs r3, #0
|
|
800720c: 6113 str r3, [r2, #16]
|
|
USBx_DEVICE->DOEPMSK = 0U;
|
|
800720e: 68fb ldr r3, [r7, #12]
|
|
8007210: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007214: 461a mov r2, r3
|
|
8007216: 2300 movs r3, #0
|
|
8007218: 6153 str r3, [r2, #20]
|
|
USBx_DEVICE->DAINTMSK = 0U;
|
|
800721a: 68fb ldr r3, [r7, #12]
|
|
800721c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007220: 461a mov r2, r3
|
|
8007222: 2300 movs r3, #0
|
|
8007224: 61d3 str r3, [r2, #28]
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8007226: 2300 movs r3, #0
|
|
8007228: 613b str r3, [r7, #16]
|
|
800722a: e043 b.n 80072b4 <USB_DevInit+0x194>
|
|
{
|
|
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
800722c: 693b ldr r3, [r7, #16]
|
|
800722e: 015a lsls r2, r3, #5
|
|
8007230: 68fb ldr r3, [r7, #12]
|
|
8007232: 4413 add r3, r2
|
|
8007234: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007238: 681b ldr r3, [r3, #0]
|
|
800723a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
800723e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8007242: d118 bne.n 8007276 <USB_DevInit+0x156>
|
|
{
|
|
if (i == 0U)
|
|
8007244: 693b ldr r3, [r7, #16]
|
|
8007246: 2b00 cmp r3, #0
|
|
8007248: d10a bne.n 8007260 <USB_DevInit+0x140>
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
|
|
800724a: 693b ldr r3, [r7, #16]
|
|
800724c: 015a lsls r2, r3, #5
|
|
800724e: 68fb ldr r3, [r7, #12]
|
|
8007250: 4413 add r3, r2
|
|
8007252: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007256: 461a mov r2, r3
|
|
8007258: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
800725c: 6013 str r3, [r2, #0]
|
|
800725e: e013 b.n 8007288 <USB_DevInit+0x168>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
|
|
8007260: 693b ldr r3, [r7, #16]
|
|
8007262: 015a lsls r2, r3, #5
|
|
8007264: 68fb ldr r3, [r7, #12]
|
|
8007266: 4413 add r3, r2
|
|
8007268: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800726c: 461a mov r2, r3
|
|
800726e: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
8007272: 6013 str r3, [r2, #0]
|
|
8007274: e008 b.n 8007288 <USB_DevInit+0x168>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(i)->DIEPCTL = 0U;
|
|
8007276: 693b ldr r3, [r7, #16]
|
|
8007278: 015a lsls r2, r3, #5
|
|
800727a: 68fb ldr r3, [r7, #12]
|
|
800727c: 4413 add r3, r2
|
|
800727e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007282: 461a mov r2, r3
|
|
8007284: 2300 movs r3, #0
|
|
8007286: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_INEP(i)->DIEPTSIZ = 0U;
|
|
8007288: 693b ldr r3, [r7, #16]
|
|
800728a: 015a lsls r2, r3, #5
|
|
800728c: 68fb ldr r3, [r7, #12]
|
|
800728e: 4413 add r3, r2
|
|
8007290: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007294: 461a mov r2, r3
|
|
8007296: 2300 movs r3, #0
|
|
8007298: 6113 str r3, [r2, #16]
|
|
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
|
800729a: 693b ldr r3, [r7, #16]
|
|
800729c: 015a lsls r2, r3, #5
|
|
800729e: 68fb ldr r3, [r7, #12]
|
|
80072a0: 4413 add r3, r2
|
|
80072a2: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80072a6: 461a mov r2, r3
|
|
80072a8: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
80072ac: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
80072ae: 693b ldr r3, [r7, #16]
|
|
80072b0: 3301 adds r3, #1
|
|
80072b2: 613b str r3, [r7, #16]
|
|
80072b4: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
80072b8: 461a mov r2, r3
|
|
80072ba: 693b ldr r3, [r7, #16]
|
|
80072bc: 4293 cmp r3, r2
|
|
80072be: d3b5 bcc.n 800722c <USB_DevInit+0x10c>
|
|
}
|
|
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
80072c0: 2300 movs r3, #0
|
|
80072c2: 613b str r3, [r7, #16]
|
|
80072c4: e043 b.n 800734e <USB_DevInit+0x22e>
|
|
{
|
|
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
80072c6: 693b ldr r3, [r7, #16]
|
|
80072c8: 015a lsls r2, r3, #5
|
|
80072ca: 68fb ldr r3, [r7, #12]
|
|
80072cc: 4413 add r3, r2
|
|
80072ce: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80072d2: 681b ldr r3, [r3, #0]
|
|
80072d4: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80072d8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80072dc: d118 bne.n 8007310 <USB_DevInit+0x1f0>
|
|
{
|
|
if (i == 0U)
|
|
80072de: 693b ldr r3, [r7, #16]
|
|
80072e0: 2b00 cmp r3, #0
|
|
80072e2: d10a bne.n 80072fa <USB_DevInit+0x1da>
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
|
|
80072e4: 693b ldr r3, [r7, #16]
|
|
80072e6: 015a lsls r2, r3, #5
|
|
80072e8: 68fb ldr r3, [r7, #12]
|
|
80072ea: 4413 add r3, r2
|
|
80072ec: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80072f0: 461a mov r2, r3
|
|
80072f2: f04f 6300 mov.w r3, #134217728 @ 0x8000000
|
|
80072f6: 6013 str r3, [r2, #0]
|
|
80072f8: e013 b.n 8007322 <USB_DevInit+0x202>
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
|
|
80072fa: 693b ldr r3, [r7, #16]
|
|
80072fc: 015a lsls r2, r3, #5
|
|
80072fe: 68fb ldr r3, [r7, #12]
|
|
8007300: 4413 add r3, r2
|
|
8007302: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007306: 461a mov r2, r3
|
|
8007308: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
800730c: 6013 str r3, [r2, #0]
|
|
800730e: e008 b.n 8007322 <USB_DevInit+0x202>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(i)->DOEPCTL = 0U;
|
|
8007310: 693b ldr r3, [r7, #16]
|
|
8007312: 015a lsls r2, r3, #5
|
|
8007314: 68fb ldr r3, [r7, #12]
|
|
8007316: 4413 add r3, r2
|
|
8007318: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800731c: 461a mov r2, r3
|
|
800731e: 2300 movs r3, #0
|
|
8007320: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_OUTEP(i)->DOEPTSIZ = 0U;
|
|
8007322: 693b ldr r3, [r7, #16]
|
|
8007324: 015a lsls r2, r3, #5
|
|
8007326: 68fb ldr r3, [r7, #12]
|
|
8007328: 4413 add r3, r2
|
|
800732a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800732e: 461a mov r2, r3
|
|
8007330: 2300 movs r3, #0
|
|
8007332: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
|
8007334: 693b ldr r3, [r7, #16]
|
|
8007336: 015a lsls r2, r3, #5
|
|
8007338: 68fb ldr r3, [r7, #12]
|
|
800733a: 4413 add r3, r2
|
|
800733c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007340: 461a mov r2, r3
|
|
8007342: f64f 337f movw r3, #64383 @ 0xfb7f
|
|
8007346: 6093 str r3, [r2, #8]
|
|
for (i = 0U; i < cfg.dev_endpoints; i++)
|
|
8007348: 693b ldr r3, [r7, #16]
|
|
800734a: 3301 adds r3, #1
|
|
800734c: 613b str r3, [r7, #16]
|
|
800734e: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
8007352: 461a mov r2, r3
|
|
8007354: 693b ldr r3, [r7, #16]
|
|
8007356: 4293 cmp r3, r2
|
|
8007358: d3b5 bcc.n 80072c6 <USB_DevInit+0x1a6>
|
|
}
|
|
|
|
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
|
|
800735a: 68fb ldr r3, [r7, #12]
|
|
800735c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007360: 691b ldr r3, [r3, #16]
|
|
8007362: 68fa ldr r2, [r7, #12]
|
|
8007364: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8007368: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
800736c: 6113 str r3, [r2, #16]
|
|
|
|
/* Disable all interrupts. */
|
|
USBx->GINTMSK = 0U;
|
|
800736e: 687b ldr r3, [r7, #4]
|
|
8007370: 2200 movs r2, #0
|
|
8007372: 619a str r2, [r3, #24]
|
|
|
|
/* Clear any pending interrupts */
|
|
USBx->GINTSTS = 0xBFFFFFFFU;
|
|
8007374: 687b ldr r3, [r7, #4]
|
|
8007376: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000
|
|
800737a: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the common interrupts */
|
|
if (cfg.dma_enable == 0U)
|
|
800737c: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
|
|
8007380: 2b00 cmp r3, #0
|
|
8007382: d105 bne.n 8007390 <USB_DevInit+0x270>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
|
|
8007384: 687b ldr r3, [r7, #4]
|
|
8007386: 699b ldr r3, [r3, #24]
|
|
8007388: f043 0210 orr.w r2, r3, #16
|
|
800738c: 687b ldr r3, [r7, #4]
|
|
800738e: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
/* Enable interrupts matching to the Device mode ONLY */
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
|
|
8007390: 687b ldr r3, [r7, #4]
|
|
8007392: 699a ldr r2, [r3, #24]
|
|
8007394: 4b10 ldr r3, [pc, #64] @ (80073d8 <USB_DevInit+0x2b8>)
|
|
8007396: 4313 orrs r3, r2
|
|
8007398: 687a ldr r2, [r7, #4]
|
|
800739a: 6193 str r3, [r2, #24]
|
|
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
|
|
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
|
|
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
|
|
|
|
if (cfg.Sof_enable != 0U)
|
|
800739c: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
80073a0: 2b00 cmp r3, #0
|
|
80073a2: d005 beq.n 80073b0 <USB_DevInit+0x290>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
|
|
80073a4: 687b ldr r3, [r7, #4]
|
|
80073a6: 699b ldr r3, [r3, #24]
|
|
80073a8: f043 0208 orr.w r2, r3, #8
|
|
80073ac: 687b ldr r3, [r7, #4]
|
|
80073ae: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (cfg.vbus_sensing_enable == 1U)
|
|
80073b0: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
80073b4: 2b01 cmp r3, #1
|
|
80073b6: d107 bne.n 80073c8 <USB_DevInit+0x2a8>
|
|
{
|
|
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
|
|
80073b8: 687b ldr r3, [r7, #4]
|
|
80073ba: 699b ldr r3, [r3, #24]
|
|
80073bc: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80073c0: f043 0304 orr.w r3, r3, #4
|
|
80073c4: 687a ldr r2, [r7, #4]
|
|
80073c6: 6193 str r3, [r2, #24]
|
|
}
|
|
|
|
return ret;
|
|
80073c8: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80073ca: 4618 mov r0, r3
|
|
80073cc: 3718 adds r7, #24
|
|
80073ce: 46bd mov sp, r7
|
|
80073d0: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
80073d4: b004 add sp, #16
|
|
80073d6: 4770 bx lr
|
|
80073d8: 803c3800 .word 0x803c3800
|
|
|
|
080073dc <USB_FlushTxFifo>:
|
|
* This parameter can be a value from 1 to 15
|
|
15 means Flush all Tx FIFOs
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
|
|
{
|
|
80073dc: b480 push {r7}
|
|
80073de: b085 sub sp, #20
|
|
80073e0: af00 add r7, sp, #0
|
|
80073e2: 6078 str r0, [r7, #4]
|
|
80073e4: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
80073e6: 2300 movs r3, #0
|
|
80073e8: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
80073ea: 68fb ldr r3, [r7, #12]
|
|
80073ec: 3301 adds r3, #1
|
|
80073ee: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80073f0: 68fb ldr r3, [r7, #12]
|
|
80073f2: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80073f6: d901 bls.n 80073fc <USB_FlushTxFifo+0x20>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80073f8: 2303 movs r3, #3
|
|
80073fa: e01b b.n 8007434 <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
80073fc: 687b ldr r3, [r7, #4]
|
|
80073fe: 691b ldr r3, [r3, #16]
|
|
8007400: 2b00 cmp r3, #0
|
|
8007402: daf2 bge.n 80073ea <USB_FlushTxFifo+0xe>
|
|
|
|
/* Flush TX Fifo */
|
|
count = 0U;
|
|
8007404: 2300 movs r3, #0
|
|
8007406: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
|
|
8007408: 683b ldr r3, [r7, #0]
|
|
800740a: 019b lsls r3, r3, #6
|
|
800740c: f043 0220 orr.w r2, r3, #32
|
|
8007410: 687b ldr r3, [r7, #4]
|
|
8007412: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8007414: 68fb ldr r3, [r7, #12]
|
|
8007416: 3301 adds r3, #1
|
|
8007418: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800741a: 68fb ldr r3, [r7, #12]
|
|
800741c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8007420: d901 bls.n 8007426 <USB_FlushTxFifo+0x4a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007422: 2303 movs r3, #3
|
|
8007424: e006 b.n 8007434 <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
|
|
8007426: 687b ldr r3, [r7, #4]
|
|
8007428: 691b ldr r3, [r3, #16]
|
|
800742a: f003 0320 and.w r3, r3, #32
|
|
800742e: 2b20 cmp r3, #32
|
|
8007430: d0f0 beq.n 8007414 <USB_FlushTxFifo+0x38>
|
|
|
|
return HAL_OK;
|
|
8007432: 2300 movs r3, #0
|
|
}
|
|
8007434: 4618 mov r0, r3
|
|
8007436: 3714 adds r7, #20
|
|
8007438: 46bd mov sp, r7
|
|
800743a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800743e: 4770 bx lr
|
|
|
|
08007440 <USB_FlushRxFifo>:
|
|
* @brief USB_FlushRxFifo Flush Rx FIFO
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8007440: b480 push {r7}
|
|
8007442: b085 sub sp, #20
|
|
8007444: af00 add r7, sp, #0
|
|
8007446: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
8007448: 2300 movs r3, #0
|
|
800744a: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
800744c: 68fb ldr r3, [r7, #12]
|
|
800744e: 3301 adds r3, #1
|
|
8007450: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8007452: 68fb ldr r3, [r7, #12]
|
|
8007454: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8007458: d901 bls.n 800745e <USB_FlushRxFifo+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800745a: 2303 movs r3, #3
|
|
800745c: e018 b.n 8007490 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
800745e: 687b ldr r3, [r7, #4]
|
|
8007460: 691b ldr r3, [r3, #16]
|
|
8007462: 2b00 cmp r3, #0
|
|
8007464: daf2 bge.n 800744c <USB_FlushRxFifo+0xc>
|
|
|
|
/* Flush RX Fifo */
|
|
count = 0U;
|
|
8007466: 2300 movs r3, #0
|
|
8007468: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
|
|
800746a: 687b ldr r3, [r7, #4]
|
|
800746c: 2210 movs r2, #16
|
|
800746e: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8007470: 68fb ldr r3, [r7, #12]
|
|
8007472: 3301 adds r3, #1
|
|
8007474: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8007476: 68fb ldr r3, [r7, #12]
|
|
8007478: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800747c: d901 bls.n 8007482 <USB_FlushRxFifo+0x42>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800747e: 2303 movs r3, #3
|
|
8007480: e006 b.n 8007490 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
|
|
8007482: 687b ldr r3, [r7, #4]
|
|
8007484: 691b ldr r3, [r3, #16]
|
|
8007486: f003 0310 and.w r3, r3, #16
|
|
800748a: 2b10 cmp r3, #16
|
|
800748c: d0f0 beq.n 8007470 <USB_FlushRxFifo+0x30>
|
|
|
|
return HAL_OK;
|
|
800748e: 2300 movs r3, #0
|
|
}
|
|
8007490: 4618 mov r0, r3
|
|
8007492: 3714 adds r7, #20
|
|
8007494: 46bd mov sp, r7
|
|
8007496: f85d 7b04 ldr.w r7, [sp], #4
|
|
800749a: 4770 bx lr
|
|
|
|
0800749c <USB_SetDevSpeed>:
|
|
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
|
|
* @arg USB_OTG_SPEED_FULL: Full speed mode
|
|
* @retval Hal status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
|
|
{
|
|
800749c: b480 push {r7}
|
|
800749e: b085 sub sp, #20
|
|
80074a0: af00 add r7, sp, #0
|
|
80074a2: 6078 str r0, [r7, #4]
|
|
80074a4: 460b mov r3, r1
|
|
80074a6: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80074a8: 687b ldr r3, [r7, #4]
|
|
80074aa: 60fb str r3, [r7, #12]
|
|
|
|
USBx_DEVICE->DCFG |= speed;
|
|
80074ac: 68fb ldr r3, [r7, #12]
|
|
80074ae: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80074b2: 681a ldr r2, [r3, #0]
|
|
80074b4: 78fb ldrb r3, [r7, #3]
|
|
80074b6: 68f9 ldr r1, [r7, #12]
|
|
80074b8: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80074bc: 4313 orrs r3, r2
|
|
80074be: 600b str r3, [r1, #0]
|
|
return HAL_OK;
|
|
80074c0: 2300 movs r3, #0
|
|
}
|
|
80074c2: 4618 mov r0, r3
|
|
80074c4: 3714 adds r7, #20
|
|
80074c6: 46bd mov sp, r7
|
|
80074c8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80074cc: 4770 bx lr
|
|
|
|
080074ce <USB_GetDevSpeed>:
|
|
* This parameter can be one of these values:
|
|
* @arg USBD_HS_SPEED: High speed mode
|
|
* @arg USBD_FS_SPEED: Full speed mode
|
|
*/
|
|
uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80074ce: b480 push {r7}
|
|
80074d0: b087 sub sp, #28
|
|
80074d2: af00 add r7, sp, #0
|
|
80074d4: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80074d6: 687b ldr r3, [r7, #4]
|
|
80074d8: 613b str r3, [r7, #16]
|
|
uint8_t speed;
|
|
uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
|
|
80074da: 693b ldr r3, [r7, #16]
|
|
80074dc: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80074e0: 689b ldr r3, [r3, #8]
|
|
80074e2: f003 0306 and.w r3, r3, #6
|
|
80074e6: 60fb str r3, [r7, #12]
|
|
|
|
if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
|
|
80074e8: 68fb ldr r3, [r7, #12]
|
|
80074ea: 2b00 cmp r3, #0
|
|
80074ec: d102 bne.n 80074f4 <USB_GetDevSpeed+0x26>
|
|
{
|
|
speed = USBD_HS_SPEED;
|
|
80074ee: 2300 movs r3, #0
|
|
80074f0: 75fb strb r3, [r7, #23]
|
|
80074f2: e00a b.n 800750a <USB_GetDevSpeed+0x3c>
|
|
}
|
|
else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
|
|
80074f4: 68fb ldr r3, [r7, #12]
|
|
80074f6: 2b02 cmp r3, #2
|
|
80074f8: d002 beq.n 8007500 <USB_GetDevSpeed+0x32>
|
|
80074fa: 68fb ldr r3, [r7, #12]
|
|
80074fc: 2b06 cmp r3, #6
|
|
80074fe: d102 bne.n 8007506 <USB_GetDevSpeed+0x38>
|
|
(DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
|
|
{
|
|
speed = USBD_FS_SPEED;
|
|
8007500: 2302 movs r3, #2
|
|
8007502: 75fb strb r3, [r7, #23]
|
|
8007504: e001 b.n 800750a <USB_GetDevSpeed+0x3c>
|
|
}
|
|
else
|
|
{
|
|
speed = 0xFU;
|
|
8007506: 230f movs r3, #15
|
|
8007508: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return speed;
|
|
800750a: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800750c: 4618 mov r0, r3
|
|
800750e: 371c adds r7, #28
|
|
8007510: 46bd mov sp, r7
|
|
8007512: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007516: 4770 bx lr
|
|
|
|
08007518 <USB_ActivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8007518: b480 push {r7}
|
|
800751a: b085 sub sp, #20
|
|
800751c: af00 add r7, sp, #0
|
|
800751e: 6078 str r0, [r7, #4]
|
|
8007520: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007522: 687b ldr r3, [r7, #4]
|
|
8007524: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8007526: 683b ldr r3, [r7, #0]
|
|
8007528: 781b ldrb r3, [r3, #0]
|
|
800752a: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
800752c: 683b ldr r3, [r7, #0]
|
|
800752e: 785b ldrb r3, [r3, #1]
|
|
8007530: 2b01 cmp r3, #1
|
|
8007532: d13a bne.n 80075aa <USB_ActivateEndpoint+0x92>
|
|
{
|
|
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
|
|
8007534: 68fb ldr r3, [r7, #12]
|
|
8007536: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800753a: 69da ldr r2, [r3, #28]
|
|
800753c: 683b ldr r3, [r7, #0]
|
|
800753e: 781b ldrb r3, [r3, #0]
|
|
8007540: f003 030f and.w r3, r3, #15
|
|
8007544: 2101 movs r1, #1
|
|
8007546: fa01 f303 lsl.w r3, r1, r3
|
|
800754a: b29b uxth r3, r3
|
|
800754c: 68f9 ldr r1, [r7, #12]
|
|
800754e: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8007552: 4313 orrs r3, r2
|
|
8007554: 61cb str r3, [r1, #28]
|
|
|
|
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
|
|
8007556: 68bb ldr r3, [r7, #8]
|
|
8007558: 015a lsls r2, r3, #5
|
|
800755a: 68fb ldr r3, [r7, #12]
|
|
800755c: 4413 add r3, r2
|
|
800755e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007562: 681b ldr r3, [r3, #0]
|
|
8007564: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8007568: 2b00 cmp r3, #0
|
|
800756a: d155 bne.n 8007618 <USB_ActivateEndpoint+0x100>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
800756c: 68bb ldr r3, [r7, #8]
|
|
800756e: 015a lsls r2, r3, #5
|
|
8007570: 68fb ldr r3, [r7, #12]
|
|
8007572: 4413 add r3, r2
|
|
8007574: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007578: 681a ldr r2, [r3, #0]
|
|
800757a: 683b ldr r3, [r7, #0]
|
|
800757c: 689b ldr r3, [r3, #8]
|
|
800757e: f3c3 010a ubfx r1, r3, #0, #11
|
|
((uint32_t)ep->type << 18) | (epnum << 22) |
|
|
8007582: 683b ldr r3, [r7, #0]
|
|
8007584: 791b ldrb r3, [r3, #4]
|
|
8007586: 049b lsls r3, r3, #18
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
8007588: 4319 orrs r1, r3
|
|
((uint32_t)ep->type << 18) | (epnum << 22) |
|
|
800758a: 68bb ldr r3, [r7, #8]
|
|
800758c: 059b lsls r3, r3, #22
|
|
800758e: 430b orrs r3, r1
|
|
USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
|
|
8007590: 4313 orrs r3, r2
|
|
8007592: 68ba ldr r2, [r7, #8]
|
|
8007594: 0151 lsls r1, r2, #5
|
|
8007596: 68fa ldr r2, [r7, #12]
|
|
8007598: 440a add r2, r1
|
|
800759a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800759e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80075a2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80075a6: 6013 str r3, [r2, #0]
|
|
80075a8: e036 b.n 8007618 <USB_ActivateEndpoint+0x100>
|
|
USB_OTG_DIEPCTL_USBAEP;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
|
|
80075aa: 68fb ldr r3, [r7, #12]
|
|
80075ac: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80075b0: 69da ldr r2, [r3, #28]
|
|
80075b2: 683b ldr r3, [r7, #0]
|
|
80075b4: 781b ldrb r3, [r3, #0]
|
|
80075b6: f003 030f and.w r3, r3, #15
|
|
80075ba: 2101 movs r1, #1
|
|
80075bc: fa01 f303 lsl.w r3, r1, r3
|
|
80075c0: 041b lsls r3, r3, #16
|
|
80075c2: 68f9 ldr r1, [r7, #12]
|
|
80075c4: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80075c8: 4313 orrs r3, r2
|
|
80075ca: 61cb str r3, [r1, #28]
|
|
|
|
if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
|
|
80075cc: 68bb ldr r3, [r7, #8]
|
|
80075ce: 015a lsls r2, r3, #5
|
|
80075d0: 68fb ldr r3, [r7, #12]
|
|
80075d2: 4413 add r3, r2
|
|
80075d4: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80075d8: 681b ldr r3, [r3, #0]
|
|
80075da: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80075de: 2b00 cmp r3, #0
|
|
80075e0: d11a bne.n 8007618 <USB_ActivateEndpoint+0x100>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
|
|
80075e2: 68bb ldr r3, [r7, #8]
|
|
80075e4: 015a lsls r2, r3, #5
|
|
80075e6: 68fb ldr r3, [r7, #12]
|
|
80075e8: 4413 add r3, r2
|
|
80075ea: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80075ee: 681a ldr r2, [r3, #0]
|
|
80075f0: 683b ldr r3, [r7, #0]
|
|
80075f2: 689b ldr r3, [r3, #8]
|
|
80075f4: f3c3 010a ubfx r1, r3, #0, #11
|
|
((uint32_t)ep->type << 18) |
|
|
80075f8: 683b ldr r3, [r7, #0]
|
|
80075fa: 791b ldrb r3, [r3, #4]
|
|
80075fc: 049b lsls r3, r3, #18
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
|
|
80075fe: 430b orrs r3, r1
|
|
8007600: 4313 orrs r3, r2
|
|
8007602: 68ba ldr r2, [r7, #8]
|
|
8007604: 0151 lsls r1, r2, #5
|
|
8007606: 68fa ldr r2, [r7, #12]
|
|
8007608: 440a add r2, r1
|
|
800760a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800760e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8007612: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8007616: 6013 str r3, [r2, #0]
|
|
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DOEPCTL_USBAEP;
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8007618: 2300 movs r3, #0
|
|
}
|
|
800761a: 4618 mov r0, r3
|
|
800761c: 3714 adds r7, #20
|
|
800761e: 46bd mov sp, r7
|
|
8007620: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007624: 4770 bx lr
|
|
...
|
|
|
|
08007628 <USB_DeactivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8007628: b480 push {r7}
|
|
800762a: b085 sub sp, #20
|
|
800762c: af00 add r7, sp, #0
|
|
800762e: 6078 str r0, [r7, #4]
|
|
8007630: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007632: 687b ldr r3, [r7, #4]
|
|
8007634: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8007636: 683b ldr r3, [r7, #0]
|
|
8007638: 781b ldrb r3, [r3, #0]
|
|
800763a: 60bb str r3, [r7, #8]
|
|
|
|
/* Read DEPCTLn register */
|
|
if (ep->is_in == 1U)
|
|
800763c: 683b ldr r3, [r7, #0]
|
|
800763e: 785b ldrb r3, [r3, #1]
|
|
8007640: 2b01 cmp r3, #1
|
|
8007642: d161 bne.n 8007708 <USB_DeactivateEndpoint+0xe0>
|
|
{
|
|
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
8007644: 68bb ldr r3, [r7, #8]
|
|
8007646: 015a lsls r2, r3, #5
|
|
8007648: 68fb ldr r3, [r7, #12]
|
|
800764a: 4413 add r3, r2
|
|
800764c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007650: 681b ldr r3, [r3, #0]
|
|
8007652: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007656: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800765a: d11f bne.n 800769c <USB_DeactivateEndpoint+0x74>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
|
|
800765c: 68bb ldr r3, [r7, #8]
|
|
800765e: 015a lsls r2, r3, #5
|
|
8007660: 68fb ldr r3, [r7, #12]
|
|
8007662: 4413 add r3, r2
|
|
8007664: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007668: 681b ldr r3, [r3, #0]
|
|
800766a: 68ba ldr r2, [r7, #8]
|
|
800766c: 0151 lsls r1, r2, #5
|
|
800766e: 68fa ldr r2, [r7, #12]
|
|
8007670: 440a add r2, r1
|
|
8007672: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007676: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
800767a: 6013 str r3, [r2, #0]
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
|
|
800767c: 68bb ldr r3, [r7, #8]
|
|
800767e: 015a lsls r2, r3, #5
|
|
8007680: 68fb ldr r3, [r7, #12]
|
|
8007682: 4413 add r3, r2
|
|
8007684: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007688: 681b ldr r3, [r3, #0]
|
|
800768a: 68ba ldr r2, [r7, #8]
|
|
800768c: 0151 lsls r1, r2, #5
|
|
800768e: 68fa ldr r2, [r7, #12]
|
|
8007690: 440a add r2, r1
|
|
8007692: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007696: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
800769a: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
|
|
800769c: 68fb ldr r3, [r7, #12]
|
|
800769e: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80076a2: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
80076a4: 683b ldr r3, [r7, #0]
|
|
80076a6: 781b ldrb r3, [r3, #0]
|
|
80076a8: f003 030f and.w r3, r3, #15
|
|
80076ac: 2101 movs r1, #1
|
|
80076ae: fa01 f303 lsl.w r3, r1, r3
|
|
80076b2: b29b uxth r3, r3
|
|
80076b4: 43db mvns r3, r3
|
|
80076b6: 68f9 ldr r1, [r7, #12]
|
|
80076b8: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80076bc: 4013 ands r3, r2
|
|
80076be: 63cb str r3, [r1, #60] @ 0x3c
|
|
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
|
|
80076c0: 68fb ldr r3, [r7, #12]
|
|
80076c2: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80076c6: 69da ldr r2, [r3, #28]
|
|
80076c8: 683b ldr r3, [r7, #0]
|
|
80076ca: 781b ldrb r3, [r3, #0]
|
|
80076cc: f003 030f and.w r3, r3, #15
|
|
80076d0: 2101 movs r1, #1
|
|
80076d2: fa01 f303 lsl.w r3, r1, r3
|
|
80076d6: b29b uxth r3, r3
|
|
80076d8: 43db mvns r3, r3
|
|
80076da: 68f9 ldr r1, [r7, #12]
|
|
80076dc: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80076e0: 4013 ands r3, r2
|
|
80076e2: 61cb str r3, [r1, #28]
|
|
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
|
|
80076e4: 68bb ldr r3, [r7, #8]
|
|
80076e6: 015a lsls r2, r3, #5
|
|
80076e8: 68fb ldr r3, [r7, #12]
|
|
80076ea: 4413 add r3, r2
|
|
80076ec: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80076f0: 681a ldr r2, [r3, #0]
|
|
80076f2: 68bb ldr r3, [r7, #8]
|
|
80076f4: 0159 lsls r1, r3, #5
|
|
80076f6: 68fb ldr r3, [r7, #12]
|
|
80076f8: 440b add r3, r1
|
|
80076fa: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80076fe: 4619 mov r1, r3
|
|
8007700: 4b35 ldr r3, [pc, #212] @ (80077d8 <USB_DeactivateEndpoint+0x1b0>)
|
|
8007702: 4013 ands r3, r2
|
|
8007704: 600b str r3, [r1, #0]
|
|
8007706: e060 b.n 80077ca <USB_DeactivateEndpoint+0x1a2>
|
|
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DIEPCTL_EPTYP);
|
|
}
|
|
else
|
|
{
|
|
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
8007708: 68bb ldr r3, [r7, #8]
|
|
800770a: 015a lsls r2, r3, #5
|
|
800770c: 68fb ldr r3, [r7, #12]
|
|
800770e: 4413 add r3, r2
|
|
8007710: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007714: 681b ldr r3, [r3, #0]
|
|
8007716: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
800771a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800771e: d11f bne.n 8007760 <USB_DeactivateEndpoint+0x138>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
|
8007720: 68bb ldr r3, [r7, #8]
|
|
8007722: 015a lsls r2, r3, #5
|
|
8007724: 68fb ldr r3, [r7, #12]
|
|
8007726: 4413 add r3, r2
|
|
8007728: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800772c: 681b ldr r3, [r3, #0]
|
|
800772e: 68ba ldr r2, [r7, #8]
|
|
8007730: 0151 lsls r1, r2, #5
|
|
8007732: 68fa ldr r2, [r7, #12]
|
|
8007734: 440a add r2, r1
|
|
8007736: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800773a: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
800773e: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
|
|
8007740: 68bb ldr r3, [r7, #8]
|
|
8007742: 015a lsls r2, r3, #5
|
|
8007744: 68fb ldr r3, [r7, #12]
|
|
8007746: 4413 add r3, r2
|
|
8007748: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800774c: 681b ldr r3, [r3, #0]
|
|
800774e: 68ba ldr r2, [r7, #8]
|
|
8007750: 0151 lsls r1, r2, #5
|
|
8007752: 68fa ldr r2, [r7, #12]
|
|
8007754: 440a add r2, r1
|
|
8007756: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800775a: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
800775e: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
|
|
8007760: 68fb ldr r3, [r7, #12]
|
|
8007762: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007766: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8007768: 683b ldr r3, [r7, #0]
|
|
800776a: 781b ldrb r3, [r3, #0]
|
|
800776c: f003 030f and.w r3, r3, #15
|
|
8007770: 2101 movs r1, #1
|
|
8007772: fa01 f303 lsl.w r3, r1, r3
|
|
8007776: 041b lsls r3, r3, #16
|
|
8007778: 43db mvns r3, r3
|
|
800777a: 68f9 ldr r1, [r7, #12]
|
|
800777c: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8007780: 4013 ands r3, r2
|
|
8007782: 63cb str r3, [r1, #60] @ 0x3c
|
|
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
|
|
8007784: 68fb ldr r3, [r7, #12]
|
|
8007786: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800778a: 69da ldr r2, [r3, #28]
|
|
800778c: 683b ldr r3, [r7, #0]
|
|
800778e: 781b ldrb r3, [r3, #0]
|
|
8007790: f003 030f and.w r3, r3, #15
|
|
8007794: 2101 movs r1, #1
|
|
8007796: fa01 f303 lsl.w r3, r1, r3
|
|
800779a: 041b lsls r3, r3, #16
|
|
800779c: 43db mvns r3, r3
|
|
800779e: 68f9 ldr r1, [r7, #12]
|
|
80077a0: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
80077a4: 4013 ands r3, r2
|
|
80077a6: 61cb str r3, [r1, #28]
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
|
|
80077a8: 68bb ldr r3, [r7, #8]
|
|
80077aa: 015a lsls r2, r3, #5
|
|
80077ac: 68fb ldr r3, [r7, #12]
|
|
80077ae: 4413 add r3, r2
|
|
80077b0: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80077b4: 681a ldr r2, [r3, #0]
|
|
80077b6: 68bb ldr r3, [r7, #8]
|
|
80077b8: 0159 lsls r1, r3, #5
|
|
80077ba: 68fb ldr r3, [r7, #12]
|
|
80077bc: 440b add r3, r1
|
|
80077be: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80077c2: 4619 mov r1, r3
|
|
80077c4: 4b05 ldr r3, [pc, #20] @ (80077dc <USB_DeactivateEndpoint+0x1b4>)
|
|
80077c6: 4013 ands r3, r2
|
|
80077c8: 600b str r3, [r1, #0]
|
|
USB_OTG_DOEPCTL_MPSIZ |
|
|
USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
|
|
USB_OTG_DOEPCTL_EPTYP);
|
|
}
|
|
|
|
return HAL_OK;
|
|
80077ca: 2300 movs r3, #0
|
|
}
|
|
80077cc: 4618 mov r0, r3
|
|
80077ce: 3714 adds r7, #20
|
|
80077d0: 46bd mov sp, r7
|
|
80077d2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80077d6: 4770 bx lr
|
|
80077d8: ec337800 .word 0xec337800
|
|
80077dc: eff37800 .word 0xeff37800
|
|
|
|
080077e0 <USB_EPStartXfer>:
|
|
* 0 : DMA feature not used
|
|
* 1 : DMA feature used
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
|
|
{
|
|
80077e0: b580 push {r7, lr}
|
|
80077e2: b08a sub sp, #40 @ 0x28
|
|
80077e4: af02 add r7, sp, #8
|
|
80077e6: 60f8 str r0, [r7, #12]
|
|
80077e8: 60b9 str r1, [r7, #8]
|
|
80077ea: 4613 mov r3, r2
|
|
80077ec: 71fb strb r3, [r7, #7]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80077ee: 68fb ldr r3, [r7, #12]
|
|
80077f0: 61fb str r3, [r7, #28]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
80077f2: 68bb ldr r3, [r7, #8]
|
|
80077f4: 781b ldrb r3, [r3, #0]
|
|
80077f6: 61bb str r3, [r7, #24]
|
|
uint16_t pktcnt;
|
|
|
|
/* IN endpoint */
|
|
if (ep->is_in == 1U)
|
|
80077f8: 68bb ldr r3, [r7, #8]
|
|
80077fa: 785b ldrb r3, [r3, #1]
|
|
80077fc: 2b01 cmp r3, #1
|
|
80077fe: f040 817f bne.w 8007b00 <USB_EPStartXfer+0x320>
|
|
{
|
|
/* Zero Length Packet? */
|
|
if (ep->xfer_len == 0U)
|
|
8007802: 68bb ldr r3, [r7, #8]
|
|
8007804: 691b ldr r3, [r3, #16]
|
|
8007806: 2b00 cmp r3, #0
|
|
8007808: d132 bne.n 8007870 <USB_EPStartXfer+0x90>
|
|
{
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
|
800780a: 69bb ldr r3, [r7, #24]
|
|
800780c: 015a lsls r2, r3, #5
|
|
800780e: 69fb ldr r3, [r7, #28]
|
|
8007810: 4413 add r3, r2
|
|
8007812: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007816: 691b ldr r3, [r3, #16]
|
|
8007818: 69ba ldr r2, [r7, #24]
|
|
800781a: 0151 lsls r1, r2, #5
|
|
800781c: 69fa ldr r2, [r7, #28]
|
|
800781e: 440a add r2, r1
|
|
8007820: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007824: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
8007828: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
800782c: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
|
|
800782e: 69bb ldr r3, [r7, #24]
|
|
8007830: 015a lsls r2, r3, #5
|
|
8007832: 69fb ldr r3, [r7, #28]
|
|
8007834: 4413 add r3, r2
|
|
8007836: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800783a: 691b ldr r3, [r3, #16]
|
|
800783c: 69ba ldr r2, [r7, #24]
|
|
800783e: 0151 lsls r1, r2, #5
|
|
8007840: 69fa ldr r2, [r7, #28]
|
|
8007842: 440a add r2, r1
|
|
8007844: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007848: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
800784c: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
|
800784e: 69bb ldr r3, [r7, #24]
|
|
8007850: 015a lsls r2, r3, #5
|
|
8007852: 69fb ldr r3, [r7, #28]
|
|
8007854: 4413 add r3, r2
|
|
8007856: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800785a: 691b ldr r3, [r3, #16]
|
|
800785c: 69ba ldr r2, [r7, #24]
|
|
800785e: 0151 lsls r1, r2, #5
|
|
8007860: 69fa ldr r2, [r7, #28]
|
|
8007862: 440a add r2, r1
|
|
8007864: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007868: 0cdb lsrs r3, r3, #19
|
|
800786a: 04db lsls r3, r3, #19
|
|
800786c: 6113 str r3, [r2, #16]
|
|
800786e: e097 b.n 80079a0 <USB_EPStartXfer+0x1c0>
|
|
/* Program the transfer size and packet count
|
|
* as follows: xfersize = N * maxpacket +
|
|
* short_packet pktcnt = N + (short_packet
|
|
* exist ? 1 : 0)
|
|
*/
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
|
8007870: 69bb ldr r3, [r7, #24]
|
|
8007872: 015a lsls r2, r3, #5
|
|
8007874: 69fb ldr r3, [r7, #28]
|
|
8007876: 4413 add r3, r2
|
|
8007878: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800787c: 691b ldr r3, [r3, #16]
|
|
800787e: 69ba ldr r2, [r7, #24]
|
|
8007880: 0151 lsls r1, r2, #5
|
|
8007882: 69fa ldr r2, [r7, #28]
|
|
8007884: 440a add r2, r1
|
|
8007886: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800788a: 0cdb lsrs r3, r3, #19
|
|
800788c: 04db lsls r3, r3, #19
|
|
800788e: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
|
8007890: 69bb ldr r3, [r7, #24]
|
|
8007892: 015a lsls r2, r3, #5
|
|
8007894: 69fb ldr r3, [r7, #28]
|
|
8007896: 4413 add r3, r2
|
|
8007898: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
800789c: 691b ldr r3, [r3, #16]
|
|
800789e: 69ba ldr r2, [r7, #24]
|
|
80078a0: 0151 lsls r1, r2, #5
|
|
80078a2: 69fa ldr r2, [r7, #28]
|
|
80078a4: 440a add r2, r1
|
|
80078a6: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80078aa: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
80078ae: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
80078b2: 6113 str r3, [r2, #16]
|
|
|
|
if (epnum == 0U)
|
|
80078b4: 69bb ldr r3, [r7, #24]
|
|
80078b6: 2b00 cmp r3, #0
|
|
80078b8: d11a bne.n 80078f0 <USB_EPStartXfer+0x110>
|
|
{
|
|
if (ep->xfer_len > ep->maxpacket)
|
|
80078ba: 68bb ldr r3, [r7, #8]
|
|
80078bc: 691a ldr r2, [r3, #16]
|
|
80078be: 68bb ldr r3, [r7, #8]
|
|
80078c0: 689b ldr r3, [r3, #8]
|
|
80078c2: 429a cmp r2, r3
|
|
80078c4: d903 bls.n 80078ce <USB_EPStartXfer+0xee>
|
|
{
|
|
ep->xfer_len = ep->maxpacket;
|
|
80078c6: 68bb ldr r3, [r7, #8]
|
|
80078c8: 689a ldr r2, [r3, #8]
|
|
80078ca: 68bb ldr r3, [r7, #8]
|
|
80078cc: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
|
|
80078ce: 69bb ldr r3, [r7, #24]
|
|
80078d0: 015a lsls r2, r3, #5
|
|
80078d2: 69fb ldr r3, [r7, #28]
|
|
80078d4: 4413 add r3, r2
|
|
80078d6: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80078da: 691b ldr r3, [r3, #16]
|
|
80078dc: 69ba ldr r2, [r7, #24]
|
|
80078de: 0151 lsls r1, r2, #5
|
|
80078e0: 69fa ldr r2, [r7, #28]
|
|
80078e2: 440a add r2, r1
|
|
80078e4: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80078e8: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
80078ec: 6113 str r3, [r2, #16]
|
|
80078ee: e044 b.n 800797a <USB_EPStartXfer+0x19a>
|
|
}
|
|
else
|
|
{
|
|
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
|
|
80078f0: 68bb ldr r3, [r7, #8]
|
|
80078f2: 691a ldr r2, [r3, #16]
|
|
80078f4: 68bb ldr r3, [r7, #8]
|
|
80078f6: 689b ldr r3, [r3, #8]
|
|
80078f8: 4413 add r3, r2
|
|
80078fa: 1e5a subs r2, r3, #1
|
|
80078fc: 68bb ldr r3, [r7, #8]
|
|
80078fe: 689b ldr r3, [r3, #8]
|
|
8007900: fbb2 f3f3 udiv r3, r2, r3
|
|
8007904: 82fb strh r3, [r7, #22]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19));
|
|
8007906: 69bb ldr r3, [r7, #24]
|
|
8007908: 015a lsls r2, r3, #5
|
|
800790a: 69fb ldr r3, [r7, #28]
|
|
800790c: 4413 add r3, r2
|
|
800790e: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007912: 691a ldr r2, [r3, #16]
|
|
8007914: 8afb ldrh r3, [r7, #22]
|
|
8007916: 04d9 lsls r1, r3, #19
|
|
8007918: 4ba4 ldr r3, [pc, #656] @ (8007bac <USB_EPStartXfer+0x3cc>)
|
|
800791a: 400b ands r3, r1
|
|
800791c: 69b9 ldr r1, [r7, #24]
|
|
800791e: 0148 lsls r0, r1, #5
|
|
8007920: 69f9 ldr r1, [r7, #28]
|
|
8007922: 4401 add r1, r0
|
|
8007924: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
8007928: 4313 orrs r3, r2
|
|
800792a: 610b str r3, [r1, #16]
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
800792c: 68bb ldr r3, [r7, #8]
|
|
800792e: 791b ldrb r3, [r3, #4]
|
|
8007930: 2b01 cmp r3, #1
|
|
8007932: d122 bne.n 800797a <USB_EPStartXfer+0x19a>
|
|
{
|
|
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
|
|
8007934: 69bb ldr r3, [r7, #24]
|
|
8007936: 015a lsls r2, r3, #5
|
|
8007938: 69fb ldr r3, [r7, #28]
|
|
800793a: 4413 add r3, r2
|
|
800793c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007940: 691b ldr r3, [r3, #16]
|
|
8007942: 69ba ldr r2, [r7, #24]
|
|
8007944: 0151 lsls r1, r2, #5
|
|
8007946: 69fa ldr r2, [r7, #28]
|
|
8007948: 440a add r2, r1
|
|
800794a: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800794e: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000
|
|
8007952: 6113 str r3, [r2, #16]
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29));
|
|
8007954: 69bb ldr r3, [r7, #24]
|
|
8007956: 015a lsls r2, r3, #5
|
|
8007958: 69fb ldr r3, [r7, #28]
|
|
800795a: 4413 add r3, r2
|
|
800795c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007960: 691a ldr r2, [r3, #16]
|
|
8007962: 8afb ldrh r3, [r7, #22]
|
|
8007964: 075b lsls r3, r3, #29
|
|
8007966: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000
|
|
800796a: 69b9 ldr r1, [r7, #24]
|
|
800796c: 0148 lsls r0, r1, #5
|
|
800796e: 69f9 ldr r1, [r7, #28]
|
|
8007970: 4401 add r1, r0
|
|
8007972: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
8007976: 4313 orrs r3, r2
|
|
8007978: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
|
|
800797a: 69bb ldr r3, [r7, #24]
|
|
800797c: 015a lsls r2, r3, #5
|
|
800797e: 69fb ldr r3, [r7, #28]
|
|
8007980: 4413 add r3, r2
|
|
8007982: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007986: 691a ldr r2, [r3, #16]
|
|
8007988: 68bb ldr r3, [r7, #8]
|
|
800798a: 691b ldr r3, [r3, #16]
|
|
800798c: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8007990: 69b9 ldr r1, [r7, #24]
|
|
8007992: 0148 lsls r0, r1, #5
|
|
8007994: 69f9 ldr r1, [r7, #28]
|
|
8007996: 4401 add r1, r0
|
|
8007998: f501 6110 add.w r1, r1, #2304 @ 0x900
|
|
800799c: 4313 orrs r3, r2
|
|
800799e: 610b str r3, [r1, #16]
|
|
}
|
|
|
|
if (dma == 1U)
|
|
80079a0: 79fb ldrb r3, [r7, #7]
|
|
80079a2: 2b01 cmp r3, #1
|
|
80079a4: d14b bne.n 8007a3e <USB_EPStartXfer+0x25e>
|
|
{
|
|
if ((uint32_t)ep->dma_addr != 0U)
|
|
80079a6: 68bb ldr r3, [r7, #8]
|
|
80079a8: 69db ldr r3, [r3, #28]
|
|
80079aa: 2b00 cmp r3, #0
|
|
80079ac: d009 beq.n 80079c2 <USB_EPStartXfer+0x1e2>
|
|
{
|
|
USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
|
|
80079ae: 69bb ldr r3, [r7, #24]
|
|
80079b0: 015a lsls r2, r3, #5
|
|
80079b2: 69fb ldr r3, [r7, #28]
|
|
80079b4: 4413 add r3, r2
|
|
80079b6: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80079ba: 461a mov r2, r3
|
|
80079bc: 68bb ldr r3, [r7, #8]
|
|
80079be: 69db ldr r3, [r3, #28]
|
|
80079c0: 6153 str r3, [r2, #20]
|
|
}
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
80079c2: 68bb ldr r3, [r7, #8]
|
|
80079c4: 791b ldrb r3, [r3, #4]
|
|
80079c6: 2b01 cmp r3, #1
|
|
80079c8: d128 bne.n 8007a1c <USB_EPStartXfer+0x23c>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
80079ca: 69fb ldr r3, [r7, #28]
|
|
80079cc: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80079d0: 689b ldr r3, [r3, #8]
|
|
80079d2: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80079d6: 2b00 cmp r3, #0
|
|
80079d8: d110 bne.n 80079fc <USB_EPStartXfer+0x21c>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
|
|
80079da: 69bb ldr r3, [r7, #24]
|
|
80079dc: 015a lsls r2, r3, #5
|
|
80079de: 69fb ldr r3, [r7, #28]
|
|
80079e0: 4413 add r3, r2
|
|
80079e2: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80079e6: 681b ldr r3, [r3, #0]
|
|
80079e8: 69ba ldr r2, [r7, #24]
|
|
80079ea: 0151 lsls r1, r2, #5
|
|
80079ec: 69fa ldr r2, [r7, #28]
|
|
80079ee: 440a add r2, r1
|
|
80079f0: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80079f4: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
80079f8: 6013 str r3, [r2, #0]
|
|
80079fa: e00f b.n 8007a1c <USB_EPStartXfer+0x23c>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
|
80079fc: 69bb ldr r3, [r7, #24]
|
|
80079fe: 015a lsls r2, r3, #5
|
|
8007a00: 69fb ldr r3, [r7, #28]
|
|
8007a02: 4413 add r3, r2
|
|
8007a04: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007a08: 681b ldr r3, [r3, #0]
|
|
8007a0a: 69ba ldr r2, [r7, #24]
|
|
8007a0c: 0151 lsls r1, r2, #5
|
|
8007a0e: 69fa ldr r2, [r7, #28]
|
|
8007a10: 440a add r2, r1
|
|
8007a12: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007a16: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8007a1a: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
/* EP enable, IN data in FIFO */
|
|
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
|
8007a1c: 69bb ldr r3, [r7, #24]
|
|
8007a1e: 015a lsls r2, r3, #5
|
|
8007a20: 69fb ldr r3, [r7, #28]
|
|
8007a22: 4413 add r3, r2
|
|
8007a24: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007a28: 681b ldr r3, [r3, #0]
|
|
8007a2a: 69ba ldr r2, [r7, #24]
|
|
8007a2c: 0151 lsls r1, r2, #5
|
|
8007a2e: 69fa ldr r2, [r7, #28]
|
|
8007a30: 440a add r2, r1
|
|
8007a32: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007a36: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
8007a3a: 6013 str r3, [r2, #0]
|
|
8007a3c: e166 b.n 8007d0c <USB_EPStartXfer+0x52c>
|
|
}
|
|
else
|
|
{
|
|
/* EP enable, IN data in FIFO */
|
|
USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
|
8007a3e: 69bb ldr r3, [r7, #24]
|
|
8007a40: 015a lsls r2, r3, #5
|
|
8007a42: 69fb ldr r3, [r7, #28]
|
|
8007a44: 4413 add r3, r2
|
|
8007a46: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007a4a: 681b ldr r3, [r3, #0]
|
|
8007a4c: 69ba ldr r2, [r7, #24]
|
|
8007a4e: 0151 lsls r1, r2, #5
|
|
8007a50: 69fa ldr r2, [r7, #28]
|
|
8007a52: 440a add r2, r1
|
|
8007a54: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007a58: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
8007a5c: 6013 str r3, [r2, #0]
|
|
|
|
if (ep->type != EP_TYPE_ISOC)
|
|
8007a5e: 68bb ldr r3, [r7, #8]
|
|
8007a60: 791b ldrb r3, [r3, #4]
|
|
8007a62: 2b01 cmp r3, #1
|
|
8007a64: d015 beq.n 8007a92 <USB_EPStartXfer+0x2b2>
|
|
{
|
|
/* Enable the Tx FIFO Empty Interrupt for this EP */
|
|
if (ep->xfer_len > 0U)
|
|
8007a66: 68bb ldr r3, [r7, #8]
|
|
8007a68: 691b ldr r3, [r3, #16]
|
|
8007a6a: 2b00 cmp r3, #0
|
|
8007a6c: f000 814e beq.w 8007d0c <USB_EPStartXfer+0x52c>
|
|
{
|
|
USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
|
|
8007a70: 69fb ldr r3, [r7, #28]
|
|
8007a72: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007a76: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007a78: 68bb ldr r3, [r7, #8]
|
|
8007a7a: 781b ldrb r3, [r3, #0]
|
|
8007a7c: f003 030f and.w r3, r3, #15
|
|
8007a80: 2101 movs r1, #1
|
|
8007a82: fa01 f303 lsl.w r3, r1, r3
|
|
8007a86: 69f9 ldr r1, [r7, #28]
|
|
8007a88: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
8007a8c: 4313 orrs r3, r2
|
|
8007a8e: 634b str r3, [r1, #52] @ 0x34
|
|
8007a90: e13c b.n 8007d0c <USB_EPStartXfer+0x52c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
8007a92: 69fb ldr r3, [r7, #28]
|
|
8007a94: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007a98: 689b ldr r3, [r3, #8]
|
|
8007a9a: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8007a9e: 2b00 cmp r3, #0
|
|
8007aa0: d110 bne.n 8007ac4 <USB_EPStartXfer+0x2e4>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
|
|
8007aa2: 69bb ldr r3, [r7, #24]
|
|
8007aa4: 015a lsls r2, r3, #5
|
|
8007aa6: 69fb ldr r3, [r7, #28]
|
|
8007aa8: 4413 add r3, r2
|
|
8007aaa: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007aae: 681b ldr r3, [r3, #0]
|
|
8007ab0: 69ba ldr r2, [r7, #24]
|
|
8007ab2: 0151 lsls r1, r2, #5
|
|
8007ab4: 69fa ldr r2, [r7, #28]
|
|
8007ab6: 440a add r2, r1
|
|
8007ab8: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007abc: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8007ac0: 6013 str r3, [r2, #0]
|
|
8007ac2: e00f b.n 8007ae4 <USB_EPStartXfer+0x304>
|
|
}
|
|
else
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
|
8007ac4: 69bb ldr r3, [r7, #24]
|
|
8007ac6: 015a lsls r2, r3, #5
|
|
8007ac8: 69fb ldr r3, [r7, #28]
|
|
8007aca: 4413 add r3, r2
|
|
8007acc: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007ad0: 681b ldr r3, [r3, #0]
|
|
8007ad2: 69ba ldr r2, [r7, #24]
|
|
8007ad4: 0151 lsls r1, r2, #5
|
|
8007ad6: 69fa ldr r2, [r7, #28]
|
|
8007ad8: 440a add r2, r1
|
|
8007ada: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007ade: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8007ae2: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
(void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
|
|
8007ae4: 68bb ldr r3, [r7, #8]
|
|
8007ae6: 68d9 ldr r1, [r3, #12]
|
|
8007ae8: 68bb ldr r3, [r7, #8]
|
|
8007aea: 781a ldrb r2, [r3, #0]
|
|
8007aec: 68bb ldr r3, [r7, #8]
|
|
8007aee: 691b ldr r3, [r3, #16]
|
|
8007af0: b298 uxth r0, r3
|
|
8007af2: 79fb ldrb r3, [r7, #7]
|
|
8007af4: 9300 str r3, [sp, #0]
|
|
8007af6: 4603 mov r3, r0
|
|
8007af8: 68f8 ldr r0, [r7, #12]
|
|
8007afa: f000 f9b9 bl 8007e70 <USB_WritePacket>
|
|
8007afe: e105 b.n 8007d0c <USB_EPStartXfer+0x52c>
|
|
{
|
|
/* Program the transfer size and packet count as follows:
|
|
* pktcnt = N
|
|
* xfersize = N * maxpacket
|
|
*/
|
|
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
|
|
8007b00: 69bb ldr r3, [r7, #24]
|
|
8007b02: 015a lsls r2, r3, #5
|
|
8007b04: 69fb ldr r3, [r7, #28]
|
|
8007b06: 4413 add r3, r2
|
|
8007b08: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007b0c: 691b ldr r3, [r3, #16]
|
|
8007b0e: 69ba ldr r2, [r7, #24]
|
|
8007b10: 0151 lsls r1, r2, #5
|
|
8007b12: 69fa ldr r2, [r7, #28]
|
|
8007b14: 440a add r2, r1
|
|
8007b16: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007b1a: 0cdb lsrs r3, r3, #19
|
|
8007b1c: 04db lsls r3, r3, #19
|
|
8007b1e: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
|
|
8007b20: 69bb ldr r3, [r7, #24]
|
|
8007b22: 015a lsls r2, r3, #5
|
|
8007b24: 69fb ldr r3, [r7, #28]
|
|
8007b26: 4413 add r3, r2
|
|
8007b28: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007b2c: 691b ldr r3, [r3, #16]
|
|
8007b2e: 69ba ldr r2, [r7, #24]
|
|
8007b30: 0151 lsls r1, r2, #5
|
|
8007b32: 69fa ldr r2, [r7, #28]
|
|
8007b34: 440a add r2, r1
|
|
8007b36: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007b3a: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000
|
|
8007b3e: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000
|
|
8007b42: 6113 str r3, [r2, #16]
|
|
|
|
if (epnum == 0U)
|
|
8007b44: 69bb ldr r3, [r7, #24]
|
|
8007b46: 2b00 cmp r3, #0
|
|
8007b48: d132 bne.n 8007bb0 <USB_EPStartXfer+0x3d0>
|
|
{
|
|
if (ep->xfer_len > 0U)
|
|
8007b4a: 68bb ldr r3, [r7, #8]
|
|
8007b4c: 691b ldr r3, [r3, #16]
|
|
8007b4e: 2b00 cmp r3, #0
|
|
8007b50: d003 beq.n 8007b5a <USB_EPStartXfer+0x37a>
|
|
{
|
|
ep->xfer_len = ep->maxpacket;
|
|
8007b52: 68bb ldr r3, [r7, #8]
|
|
8007b54: 689a ldr r2, [r3, #8]
|
|
8007b56: 68bb ldr r3, [r7, #8]
|
|
8007b58: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
/* Store transfer size, for EP0 this is equal to endpoint max packet size */
|
|
ep->xfer_size = ep->maxpacket;
|
|
8007b5a: 68bb ldr r3, [r7, #8]
|
|
8007b5c: 689a ldr r2, [r3, #8]
|
|
8007b5e: 68bb ldr r3, [r7, #8]
|
|
8007b60: 621a str r2, [r3, #32]
|
|
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
|
|
8007b62: 69bb ldr r3, [r7, #24]
|
|
8007b64: 015a lsls r2, r3, #5
|
|
8007b66: 69fb ldr r3, [r7, #28]
|
|
8007b68: 4413 add r3, r2
|
|
8007b6a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007b6e: 691a ldr r2, [r3, #16]
|
|
8007b70: 68bb ldr r3, [r7, #8]
|
|
8007b72: 6a1b ldr r3, [r3, #32]
|
|
8007b74: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8007b78: 69b9 ldr r1, [r7, #24]
|
|
8007b7a: 0148 lsls r0, r1, #5
|
|
8007b7c: 69f9 ldr r1, [r7, #28]
|
|
8007b7e: 4401 add r1, r0
|
|
8007b80: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
8007b84: 4313 orrs r3, r2
|
|
8007b86: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
8007b88: 69bb ldr r3, [r7, #24]
|
|
8007b8a: 015a lsls r2, r3, #5
|
|
8007b8c: 69fb ldr r3, [r7, #28]
|
|
8007b8e: 4413 add r3, r2
|
|
8007b90: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007b94: 691b ldr r3, [r3, #16]
|
|
8007b96: 69ba ldr r2, [r7, #24]
|
|
8007b98: 0151 lsls r1, r2, #5
|
|
8007b9a: 69fa ldr r2, [r7, #28]
|
|
8007b9c: 440a add r2, r1
|
|
8007b9e: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007ba2: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8007ba6: 6113 str r3, [r2, #16]
|
|
8007ba8: e062 b.n 8007c70 <USB_EPStartXfer+0x490>
|
|
8007baa: bf00 nop
|
|
8007bac: 1ff80000 .word 0x1ff80000
|
|
}
|
|
else
|
|
{
|
|
if (ep->xfer_len == 0U)
|
|
8007bb0: 68bb ldr r3, [r7, #8]
|
|
8007bb2: 691b ldr r3, [r3, #16]
|
|
8007bb4: 2b00 cmp r3, #0
|
|
8007bb6: d123 bne.n 8007c00 <USB_EPStartXfer+0x420>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
|
|
8007bb8: 69bb ldr r3, [r7, #24]
|
|
8007bba: 015a lsls r2, r3, #5
|
|
8007bbc: 69fb ldr r3, [r7, #28]
|
|
8007bbe: 4413 add r3, r2
|
|
8007bc0: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007bc4: 691a ldr r2, [r3, #16]
|
|
8007bc6: 68bb ldr r3, [r7, #8]
|
|
8007bc8: 689b ldr r3, [r3, #8]
|
|
8007bca: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8007bce: 69b9 ldr r1, [r7, #24]
|
|
8007bd0: 0148 lsls r0, r1, #5
|
|
8007bd2: 69f9 ldr r1, [r7, #28]
|
|
8007bd4: 4401 add r1, r0
|
|
8007bd6: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
8007bda: 4313 orrs r3, r2
|
|
8007bdc: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
8007bde: 69bb ldr r3, [r7, #24]
|
|
8007be0: 015a lsls r2, r3, #5
|
|
8007be2: 69fb ldr r3, [r7, #28]
|
|
8007be4: 4413 add r3, r2
|
|
8007be6: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007bea: 691b ldr r3, [r3, #16]
|
|
8007bec: 69ba ldr r2, [r7, #24]
|
|
8007bee: 0151 lsls r1, r2, #5
|
|
8007bf0: 69fa ldr r2, [r7, #28]
|
|
8007bf2: 440a add r2, r1
|
|
8007bf4: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007bf8: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8007bfc: 6113 str r3, [r2, #16]
|
|
8007bfe: e037 b.n 8007c70 <USB_EPStartXfer+0x490>
|
|
}
|
|
else
|
|
{
|
|
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
|
|
8007c00: 68bb ldr r3, [r7, #8]
|
|
8007c02: 691a ldr r2, [r3, #16]
|
|
8007c04: 68bb ldr r3, [r7, #8]
|
|
8007c06: 689b ldr r3, [r3, #8]
|
|
8007c08: 4413 add r3, r2
|
|
8007c0a: 1e5a subs r2, r3, #1
|
|
8007c0c: 68bb ldr r3, [r7, #8]
|
|
8007c0e: 689b ldr r3, [r3, #8]
|
|
8007c10: fbb2 f3f3 udiv r3, r2, r3
|
|
8007c14: 82fb strh r3, [r7, #22]
|
|
ep->xfer_size = ep->maxpacket * pktcnt;
|
|
8007c16: 68bb ldr r3, [r7, #8]
|
|
8007c18: 689b ldr r3, [r3, #8]
|
|
8007c1a: 8afa ldrh r2, [r7, #22]
|
|
8007c1c: fb03 f202 mul.w r2, r3, r2
|
|
8007c20: 68bb ldr r3, [r7, #8]
|
|
8007c22: 621a str r2, [r3, #32]
|
|
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
|
|
8007c24: 69bb ldr r3, [r7, #24]
|
|
8007c26: 015a lsls r2, r3, #5
|
|
8007c28: 69fb ldr r3, [r7, #28]
|
|
8007c2a: 4413 add r3, r2
|
|
8007c2c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007c30: 691a ldr r2, [r3, #16]
|
|
8007c32: 8afb ldrh r3, [r7, #22]
|
|
8007c34: 04d9 lsls r1, r3, #19
|
|
8007c36: 4b38 ldr r3, [pc, #224] @ (8007d18 <USB_EPStartXfer+0x538>)
|
|
8007c38: 400b ands r3, r1
|
|
8007c3a: 69b9 ldr r1, [r7, #24]
|
|
8007c3c: 0148 lsls r0, r1, #5
|
|
8007c3e: 69f9 ldr r1, [r7, #28]
|
|
8007c40: 4401 add r1, r0
|
|
8007c42: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
8007c46: 4313 orrs r3, r2
|
|
8007c48: 610b str r3, [r1, #16]
|
|
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size;
|
|
8007c4a: 69bb ldr r3, [r7, #24]
|
|
8007c4c: 015a lsls r2, r3, #5
|
|
8007c4e: 69fb ldr r3, [r7, #28]
|
|
8007c50: 4413 add r3, r2
|
|
8007c52: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007c56: 691a ldr r2, [r3, #16]
|
|
8007c58: 68bb ldr r3, [r7, #8]
|
|
8007c5a: 6a1b ldr r3, [r3, #32]
|
|
8007c5c: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8007c60: 69b9 ldr r1, [r7, #24]
|
|
8007c62: 0148 lsls r0, r1, #5
|
|
8007c64: 69f9 ldr r1, [r7, #28]
|
|
8007c66: 4401 add r1, r0
|
|
8007c68: f501 6130 add.w r1, r1, #2816 @ 0xb00
|
|
8007c6c: 4313 orrs r3, r2
|
|
8007c6e: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
if (dma == 1U)
|
|
8007c70: 79fb ldrb r3, [r7, #7]
|
|
8007c72: 2b01 cmp r3, #1
|
|
8007c74: d10d bne.n 8007c92 <USB_EPStartXfer+0x4b2>
|
|
{
|
|
if ((uint32_t)ep->xfer_buff != 0U)
|
|
8007c76: 68bb ldr r3, [r7, #8]
|
|
8007c78: 68db ldr r3, [r3, #12]
|
|
8007c7a: 2b00 cmp r3, #0
|
|
8007c7c: d009 beq.n 8007c92 <USB_EPStartXfer+0x4b2>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
|
|
8007c7e: 68bb ldr r3, [r7, #8]
|
|
8007c80: 68d9 ldr r1, [r3, #12]
|
|
8007c82: 69bb ldr r3, [r7, #24]
|
|
8007c84: 015a lsls r2, r3, #5
|
|
8007c86: 69fb ldr r3, [r7, #28]
|
|
8007c88: 4413 add r3, r2
|
|
8007c8a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007c8e: 460a mov r2, r1
|
|
8007c90: 615a str r2, [r3, #20]
|
|
}
|
|
}
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
8007c92: 68bb ldr r3, [r7, #8]
|
|
8007c94: 791b ldrb r3, [r3, #4]
|
|
8007c96: 2b01 cmp r3, #1
|
|
8007c98: d128 bne.n 8007cec <USB_EPStartXfer+0x50c>
|
|
{
|
|
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
|
|
8007c9a: 69fb ldr r3, [r7, #28]
|
|
8007c9c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8007ca0: 689b ldr r3, [r3, #8]
|
|
8007ca2: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8007ca6: 2b00 cmp r3, #0
|
|
8007ca8: d110 bne.n 8007ccc <USB_EPStartXfer+0x4ec>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
|
|
8007caa: 69bb ldr r3, [r7, #24]
|
|
8007cac: 015a lsls r2, r3, #5
|
|
8007cae: 69fb ldr r3, [r7, #28]
|
|
8007cb0: 4413 add r3, r2
|
|
8007cb2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007cb6: 681b ldr r3, [r3, #0]
|
|
8007cb8: 69ba ldr r2, [r7, #24]
|
|
8007cba: 0151 lsls r1, r2, #5
|
|
8007cbc: 69fa ldr r2, [r7, #28]
|
|
8007cbe: 440a add r2, r1
|
|
8007cc0: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007cc4: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8007cc8: 6013 str r3, [r2, #0]
|
|
8007cca: e00f b.n 8007cec <USB_EPStartXfer+0x50c>
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
|
|
8007ccc: 69bb ldr r3, [r7, #24]
|
|
8007cce: 015a lsls r2, r3, #5
|
|
8007cd0: 69fb ldr r3, [r7, #28]
|
|
8007cd2: 4413 add r3, r2
|
|
8007cd4: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007cd8: 681b ldr r3, [r3, #0]
|
|
8007cda: 69ba ldr r2, [r7, #24]
|
|
8007cdc: 0151 lsls r1, r2, #5
|
|
8007cde: 69fa ldr r2, [r7, #28]
|
|
8007ce0: 440a add r2, r1
|
|
8007ce2: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007ce6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8007cea: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
/* EP enable */
|
|
USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
|
|
8007cec: 69bb ldr r3, [r7, #24]
|
|
8007cee: 015a lsls r2, r3, #5
|
|
8007cf0: 69fb ldr r3, [r7, #28]
|
|
8007cf2: 4413 add r3, r2
|
|
8007cf4: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007cf8: 681b ldr r3, [r3, #0]
|
|
8007cfa: 69ba ldr r2, [r7, #24]
|
|
8007cfc: 0151 lsls r1, r2, #5
|
|
8007cfe: 69fa ldr r2, [r7, #28]
|
|
8007d00: 440a add r2, r1
|
|
8007d02: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007d06: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000
|
|
8007d0a: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007d0c: 2300 movs r3, #0
|
|
}
|
|
8007d0e: 4618 mov r0, r3
|
|
8007d10: 3720 adds r7, #32
|
|
8007d12: 46bd mov sp, r7
|
|
8007d14: bd80 pop {r7, pc}
|
|
8007d16: bf00 nop
|
|
8007d18: 1ff80000 .word 0x1ff80000
|
|
|
|
08007d1c <USB_EPStopXfer>:
|
|
* @param USBx usb device instance
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8007d1c: b480 push {r7}
|
|
8007d1e: b087 sub sp, #28
|
|
8007d20: af00 add r7, sp, #0
|
|
8007d22: 6078 str r0, [r7, #4]
|
|
8007d24: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
8007d26: 2300 movs r3, #0
|
|
8007d28: 60fb str r3, [r7, #12]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8007d2a: 2300 movs r3, #0
|
|
8007d2c: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007d2e: 687b ldr r3, [r7, #4]
|
|
8007d30: 613b str r3, [r7, #16]
|
|
|
|
/* IN endpoint */
|
|
if (ep->is_in == 1U)
|
|
8007d32: 683b ldr r3, [r7, #0]
|
|
8007d34: 785b ldrb r3, [r3, #1]
|
|
8007d36: 2b01 cmp r3, #1
|
|
8007d38: d14a bne.n 8007dd0 <USB_EPStopXfer+0xb4>
|
|
{
|
|
/* EP enable, IN data in FIFO */
|
|
if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
|
|
8007d3a: 683b ldr r3, [r7, #0]
|
|
8007d3c: 781b ldrb r3, [r3, #0]
|
|
8007d3e: 015a lsls r2, r3, #5
|
|
8007d40: 693b ldr r3, [r7, #16]
|
|
8007d42: 4413 add r3, r2
|
|
8007d44: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007d48: 681b ldr r3, [r3, #0]
|
|
8007d4a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007d4e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8007d52: f040 8086 bne.w 8007e62 <USB_EPStopXfer+0x146>
|
|
{
|
|
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
|
|
8007d56: 683b ldr r3, [r7, #0]
|
|
8007d58: 781b ldrb r3, [r3, #0]
|
|
8007d5a: 015a lsls r2, r3, #5
|
|
8007d5c: 693b ldr r3, [r7, #16]
|
|
8007d5e: 4413 add r3, r2
|
|
8007d60: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007d64: 681b ldr r3, [r3, #0]
|
|
8007d66: 683a ldr r2, [r7, #0]
|
|
8007d68: 7812 ldrb r2, [r2, #0]
|
|
8007d6a: 0151 lsls r1, r2, #5
|
|
8007d6c: 693a ldr r2, [r7, #16]
|
|
8007d6e: 440a add r2, r1
|
|
8007d70: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007d74: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8007d78: 6013 str r3, [r2, #0]
|
|
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
|
|
8007d7a: 683b ldr r3, [r7, #0]
|
|
8007d7c: 781b ldrb r3, [r3, #0]
|
|
8007d7e: 015a lsls r2, r3, #5
|
|
8007d80: 693b ldr r3, [r7, #16]
|
|
8007d82: 4413 add r3, r2
|
|
8007d84: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007d88: 681b ldr r3, [r3, #0]
|
|
8007d8a: 683a ldr r2, [r7, #0]
|
|
8007d8c: 7812 ldrb r2, [r2, #0]
|
|
8007d8e: 0151 lsls r1, r2, #5
|
|
8007d90: 693a ldr r2, [r7, #16]
|
|
8007d92: 440a add r2, r1
|
|
8007d94: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007d98: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8007d9c: 6013 str r3, [r2, #0]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8007d9e: 68fb ldr r3, [r7, #12]
|
|
8007da0: 3301 adds r3, #1
|
|
8007da2: 60fb str r3, [r7, #12]
|
|
|
|
if (count > 10000U)
|
|
8007da4: 68fb ldr r3, [r7, #12]
|
|
8007da6: f242 7210 movw r2, #10000 @ 0x2710
|
|
8007daa: 4293 cmp r3, r2
|
|
8007dac: d902 bls.n 8007db4 <USB_EPStopXfer+0x98>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8007dae: 2301 movs r3, #1
|
|
8007db0: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007db2: e056 b.n 8007e62 <USB_EPStopXfer+0x146>
|
|
}
|
|
} while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA);
|
|
8007db4: 683b ldr r3, [r7, #0]
|
|
8007db6: 781b ldrb r3, [r3, #0]
|
|
8007db8: 015a lsls r2, r3, #5
|
|
8007dba: 693b ldr r3, [r7, #16]
|
|
8007dbc: 4413 add r3, r2
|
|
8007dbe: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007dc2: 681b ldr r3, [r3, #0]
|
|
8007dc4: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007dc8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8007dcc: d0e7 beq.n 8007d9e <USB_EPStopXfer+0x82>
|
|
8007dce: e048 b.n 8007e62 <USB_EPStopXfer+0x146>
|
|
}
|
|
}
|
|
else /* OUT endpoint */
|
|
{
|
|
if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
8007dd0: 683b ldr r3, [r7, #0]
|
|
8007dd2: 781b ldrb r3, [r3, #0]
|
|
8007dd4: 015a lsls r2, r3, #5
|
|
8007dd6: 693b ldr r3, [r7, #16]
|
|
8007dd8: 4413 add r3, r2
|
|
8007dda: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007dde: 681b ldr r3, [r3, #0]
|
|
8007de0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007de4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8007de8: d13b bne.n 8007e62 <USB_EPStopXfer+0x146>
|
|
{
|
|
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
|
|
8007dea: 683b ldr r3, [r7, #0]
|
|
8007dec: 781b ldrb r3, [r3, #0]
|
|
8007dee: 015a lsls r2, r3, #5
|
|
8007df0: 693b ldr r3, [r7, #16]
|
|
8007df2: 4413 add r3, r2
|
|
8007df4: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007df8: 681b ldr r3, [r3, #0]
|
|
8007dfa: 683a ldr r2, [r7, #0]
|
|
8007dfc: 7812 ldrb r2, [r2, #0]
|
|
8007dfe: 0151 lsls r1, r2, #5
|
|
8007e00: 693a ldr r2, [r7, #16]
|
|
8007e02: 440a add r2, r1
|
|
8007e04: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007e08: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
|
|
8007e0c: 6013 str r3, [r2, #0]
|
|
USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
|
|
8007e0e: 683b ldr r3, [r7, #0]
|
|
8007e10: 781b ldrb r3, [r3, #0]
|
|
8007e12: 015a lsls r2, r3, #5
|
|
8007e14: 693b ldr r3, [r7, #16]
|
|
8007e16: 4413 add r3, r2
|
|
8007e18: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007e1c: 681b ldr r3, [r3, #0]
|
|
8007e1e: 683a ldr r2, [r7, #0]
|
|
8007e20: 7812 ldrb r2, [r2, #0]
|
|
8007e22: 0151 lsls r1, r2, #5
|
|
8007e24: 693a ldr r2, [r7, #16]
|
|
8007e26: 440a add r2, r1
|
|
8007e28: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8007e2c: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8007e30: 6013 str r3, [r2, #0]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8007e32: 68fb ldr r3, [r7, #12]
|
|
8007e34: 3301 adds r3, #1
|
|
8007e36: 60fb str r3, [r7, #12]
|
|
|
|
if (count > 10000U)
|
|
8007e38: 68fb ldr r3, [r7, #12]
|
|
8007e3a: f242 7210 movw r2, #10000 @ 0x2710
|
|
8007e3e: 4293 cmp r3, r2
|
|
8007e40: d902 bls.n 8007e48 <USB_EPStopXfer+0x12c>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8007e42: 2301 movs r3, #1
|
|
8007e44: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8007e46: e00c b.n 8007e62 <USB_EPStopXfer+0x146>
|
|
}
|
|
} while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA);
|
|
8007e48: 683b ldr r3, [r7, #0]
|
|
8007e4a: 781b ldrb r3, [r3, #0]
|
|
8007e4c: 015a lsls r2, r3, #5
|
|
8007e4e: 693b ldr r3, [r7, #16]
|
|
8007e50: 4413 add r3, r2
|
|
8007e52: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8007e56: 681b ldr r3, [r3, #0]
|
|
8007e58: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007e5c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8007e60: d0e7 beq.n 8007e32 <USB_EPStopXfer+0x116>
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
8007e62: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8007e64: 4618 mov r0, r3
|
|
8007e66: 371c adds r7, #28
|
|
8007e68: 46bd mov sp, r7
|
|
8007e6a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007e6e: 4770 bx lr
|
|
|
|
08007e70 <USB_WritePacket>:
|
|
* 1 : DMA feature used
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
|
|
uint8_t ch_ep_num, uint16_t len, uint8_t dma)
|
|
{
|
|
8007e70: b480 push {r7}
|
|
8007e72: b089 sub sp, #36 @ 0x24
|
|
8007e74: af00 add r7, sp, #0
|
|
8007e76: 60f8 str r0, [r7, #12]
|
|
8007e78: 60b9 str r1, [r7, #8]
|
|
8007e7a: 4611 mov r1, r2
|
|
8007e7c: 461a mov r2, r3
|
|
8007e7e: 460b mov r3, r1
|
|
8007e80: 71fb strb r3, [r7, #7]
|
|
8007e82: 4613 mov r3, r2
|
|
8007e84: 80bb strh r3, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007e86: 68fb ldr r3, [r7, #12]
|
|
8007e88: 617b str r3, [r7, #20]
|
|
uint8_t *pSrc = src;
|
|
8007e8a: 68bb ldr r3, [r7, #8]
|
|
8007e8c: 61fb str r3, [r7, #28]
|
|
uint32_t count32b;
|
|
uint32_t i;
|
|
|
|
if (dma == 0U)
|
|
8007e8e: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8007e92: 2b00 cmp r3, #0
|
|
8007e94: d123 bne.n 8007ede <USB_WritePacket+0x6e>
|
|
{
|
|
count32b = ((uint32_t)len + 3U) / 4U;
|
|
8007e96: 88bb ldrh r3, [r7, #4]
|
|
8007e98: 3303 adds r3, #3
|
|
8007e9a: 089b lsrs r3, r3, #2
|
|
8007e9c: 613b str r3, [r7, #16]
|
|
for (i = 0U; i < count32b; i++)
|
|
8007e9e: 2300 movs r3, #0
|
|
8007ea0: 61bb str r3, [r7, #24]
|
|
8007ea2: e018 b.n 8007ed6 <USB_WritePacket+0x66>
|
|
{
|
|
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
|
|
8007ea4: 79fb ldrb r3, [r7, #7]
|
|
8007ea6: 031a lsls r2, r3, #12
|
|
8007ea8: 697b ldr r3, [r7, #20]
|
|
8007eaa: 4413 add r3, r2
|
|
8007eac: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8007eb0: 461a mov r2, r3
|
|
8007eb2: 69fb ldr r3, [r7, #28]
|
|
8007eb4: 681b ldr r3, [r3, #0]
|
|
8007eb6: 6013 str r3, [r2, #0]
|
|
pSrc++;
|
|
8007eb8: 69fb ldr r3, [r7, #28]
|
|
8007eba: 3301 adds r3, #1
|
|
8007ebc: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8007ebe: 69fb ldr r3, [r7, #28]
|
|
8007ec0: 3301 adds r3, #1
|
|
8007ec2: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8007ec4: 69fb ldr r3, [r7, #28]
|
|
8007ec6: 3301 adds r3, #1
|
|
8007ec8: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8007eca: 69fb ldr r3, [r7, #28]
|
|
8007ecc: 3301 adds r3, #1
|
|
8007ece: 61fb str r3, [r7, #28]
|
|
for (i = 0U; i < count32b; i++)
|
|
8007ed0: 69bb ldr r3, [r7, #24]
|
|
8007ed2: 3301 adds r3, #1
|
|
8007ed4: 61bb str r3, [r7, #24]
|
|
8007ed6: 69ba ldr r2, [r7, #24]
|
|
8007ed8: 693b ldr r3, [r7, #16]
|
|
8007eda: 429a cmp r2, r3
|
|
8007edc: d3e2 bcc.n 8007ea4 <USB_WritePacket+0x34>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007ede: 2300 movs r3, #0
|
|
}
|
|
8007ee0: 4618 mov r0, r3
|
|
8007ee2: 3724 adds r7, #36 @ 0x24
|
|
8007ee4: 46bd mov sp, r7
|
|
8007ee6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007eea: 4770 bx lr
|
|
|
|
08007eec <USB_ReadPacket>:
|
|
* @param dest source pointer
|
|
* @param len Number of bytes to read
|
|
* @retval pointer to destination buffer
|
|
*/
|
|
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
|
|
{
|
|
8007eec: b480 push {r7}
|
|
8007eee: b08b sub sp, #44 @ 0x2c
|
|
8007ef0: af00 add r7, sp, #0
|
|
8007ef2: 60f8 str r0, [r7, #12]
|
|
8007ef4: 60b9 str r1, [r7, #8]
|
|
8007ef6: 4613 mov r3, r2
|
|
8007ef8: 80fb strh r3, [r7, #6]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007efa: 68fb ldr r3, [r7, #12]
|
|
8007efc: 61bb str r3, [r7, #24]
|
|
uint8_t *pDest = dest;
|
|
8007efe: 68bb ldr r3, [r7, #8]
|
|
8007f00: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t pData;
|
|
uint32_t i;
|
|
uint32_t count32b = (uint32_t)len >> 2U;
|
|
8007f02: 88fb ldrh r3, [r7, #6]
|
|
8007f04: 089b lsrs r3, r3, #2
|
|
8007f06: b29b uxth r3, r3
|
|
8007f08: 617b str r3, [r7, #20]
|
|
uint16_t remaining_bytes = len % 4U;
|
|
8007f0a: 88fb ldrh r3, [r7, #6]
|
|
8007f0c: f003 0303 and.w r3, r3, #3
|
|
8007f10: 83fb strh r3, [r7, #30]
|
|
|
|
for (i = 0U; i < count32b; i++)
|
|
8007f12: 2300 movs r3, #0
|
|
8007f14: 623b str r3, [r7, #32]
|
|
8007f16: e014 b.n 8007f42 <USB_ReadPacket+0x56>
|
|
{
|
|
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
|
|
8007f18: 69bb ldr r3, [r7, #24]
|
|
8007f1a: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8007f1e: 681a ldr r2, [r3, #0]
|
|
8007f20: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007f22: 601a str r2, [r3, #0]
|
|
pDest++;
|
|
8007f24: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007f26: 3301 adds r3, #1
|
|
8007f28: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8007f2a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007f2c: 3301 adds r3, #1
|
|
8007f2e: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8007f30: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007f32: 3301 adds r3, #1
|
|
8007f34: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8007f36: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007f38: 3301 adds r3, #1
|
|
8007f3a: 627b str r3, [r7, #36] @ 0x24
|
|
for (i = 0U; i < count32b; i++)
|
|
8007f3c: 6a3b ldr r3, [r7, #32]
|
|
8007f3e: 3301 adds r3, #1
|
|
8007f40: 623b str r3, [r7, #32]
|
|
8007f42: 6a3a ldr r2, [r7, #32]
|
|
8007f44: 697b ldr r3, [r7, #20]
|
|
8007f46: 429a cmp r2, r3
|
|
8007f48: d3e6 bcc.n 8007f18 <USB_ReadPacket+0x2c>
|
|
}
|
|
|
|
/* When Number of data is not word aligned, read the remaining byte */
|
|
if (remaining_bytes != 0U)
|
|
8007f4a: 8bfb ldrh r3, [r7, #30]
|
|
8007f4c: 2b00 cmp r3, #0
|
|
8007f4e: d01e beq.n 8007f8e <USB_ReadPacket+0xa2>
|
|
{
|
|
i = 0U;
|
|
8007f50: 2300 movs r3, #0
|
|
8007f52: 623b str r3, [r7, #32]
|
|
__UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
|
|
8007f54: 69bb ldr r3, [r7, #24]
|
|
8007f56: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8007f5a: 461a mov r2, r3
|
|
8007f5c: f107 0310 add.w r3, r7, #16
|
|
8007f60: 6812 ldr r2, [r2, #0]
|
|
8007f62: 601a str r2, [r3, #0]
|
|
|
|
do
|
|
{
|
|
*(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
|
|
8007f64: 693a ldr r2, [r7, #16]
|
|
8007f66: 6a3b ldr r3, [r7, #32]
|
|
8007f68: b2db uxtb r3, r3
|
|
8007f6a: 00db lsls r3, r3, #3
|
|
8007f6c: fa22 f303 lsr.w r3, r2, r3
|
|
8007f70: b2da uxtb r2, r3
|
|
8007f72: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007f74: 701a strb r2, [r3, #0]
|
|
i++;
|
|
8007f76: 6a3b ldr r3, [r7, #32]
|
|
8007f78: 3301 adds r3, #1
|
|
8007f7a: 623b str r3, [r7, #32]
|
|
pDest++;
|
|
8007f7c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007f7e: 3301 adds r3, #1
|
|
8007f80: 627b str r3, [r7, #36] @ 0x24
|
|
remaining_bytes--;
|
|
8007f82: 8bfb ldrh r3, [r7, #30]
|
|
8007f84: 3b01 subs r3, #1
|
|
8007f86: 83fb strh r3, [r7, #30]
|
|
} while (remaining_bytes != 0U);
|
|
8007f88: 8bfb ldrh r3, [r7, #30]
|
|
8007f8a: 2b00 cmp r3, #0
|
|
8007f8c: d1ea bne.n 8007f64 <USB_ReadPacket+0x78>
|
|
}
|
|
|
|
return ((void *)pDest);
|
|
8007f8e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
}
|
|
8007f90: 4618 mov r0, r3
|
|
8007f92: 372c adds r7, #44 @ 0x2c
|
|
8007f94: 46bd mov sp, r7
|
|
8007f96: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007f9a: 4770 bx lr
|
|
|
|
08007f9c <USB_EPSetStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8007f9c: b480 push {r7}
|
|
8007f9e: b085 sub sp, #20
|
|
8007fa0: af00 add r7, sp, #0
|
|
8007fa2: 6078 str r0, [r7, #4]
|
|
8007fa4: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007fa6: 687b ldr r3, [r7, #4]
|
|
8007fa8: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8007faa: 683b ldr r3, [r7, #0]
|
|
8007fac: 781b ldrb r3, [r3, #0]
|
|
8007fae: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
8007fb0: 683b ldr r3, [r7, #0]
|
|
8007fb2: 785b ldrb r3, [r3, #1]
|
|
8007fb4: 2b01 cmp r3, #1
|
|
8007fb6: d12c bne.n 8008012 <USB_EPSetStall+0x76>
|
|
{
|
|
if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
|
|
8007fb8: 68bb ldr r3, [r7, #8]
|
|
8007fba: 015a lsls r2, r3, #5
|
|
8007fbc: 68fb ldr r3, [r7, #12]
|
|
8007fbe: 4413 add r3, r2
|
|
8007fc0: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007fc4: 681b ldr r3, [r3, #0]
|
|
8007fc6: 2b00 cmp r3, #0
|
|
8007fc8: db12 blt.n 8007ff0 <USB_EPSetStall+0x54>
|
|
8007fca: 68bb ldr r3, [r7, #8]
|
|
8007fcc: 2b00 cmp r3, #0
|
|
8007fce: d00f beq.n 8007ff0 <USB_EPSetStall+0x54>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
|
|
8007fd0: 68bb ldr r3, [r7, #8]
|
|
8007fd2: 015a lsls r2, r3, #5
|
|
8007fd4: 68fb ldr r3, [r7, #12]
|
|
8007fd6: 4413 add r3, r2
|
|
8007fd8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007fdc: 681b ldr r3, [r3, #0]
|
|
8007fde: 68ba ldr r2, [r7, #8]
|
|
8007fe0: 0151 lsls r1, r2, #5
|
|
8007fe2: 68fa ldr r2, [r7, #12]
|
|
8007fe4: 440a add r2, r1
|
|
8007fe6: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8007fea: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8007fee: 6013 str r3, [r2, #0]
|
|
}
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
|
|
8007ff0: 68bb ldr r3, [r7, #8]
|
|
8007ff2: 015a lsls r2, r3, #5
|
|
8007ff4: 68fb ldr r3, [r7, #12]
|
|
8007ff6: 4413 add r3, r2
|
|
8007ff8: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8007ffc: 681b ldr r3, [r3, #0]
|
|
8007ffe: 68ba ldr r2, [r7, #8]
|
|
8008000: 0151 lsls r1, r2, #5
|
|
8008002: 68fa ldr r2, [r7, #12]
|
|
8008004: 440a add r2, r1
|
|
8008006: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
800800a: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
800800e: 6013 str r3, [r2, #0]
|
|
8008010: e02b b.n 800806a <USB_EPSetStall+0xce>
|
|
}
|
|
else
|
|
{
|
|
if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
|
|
8008012: 68bb ldr r3, [r7, #8]
|
|
8008014: 015a lsls r2, r3, #5
|
|
8008016: 68fb ldr r3, [r7, #12]
|
|
8008018: 4413 add r3, r2
|
|
800801a: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800801e: 681b ldr r3, [r3, #0]
|
|
8008020: 2b00 cmp r3, #0
|
|
8008022: db12 blt.n 800804a <USB_EPSetStall+0xae>
|
|
8008024: 68bb ldr r3, [r7, #8]
|
|
8008026: 2b00 cmp r3, #0
|
|
8008028: d00f beq.n 800804a <USB_EPSetStall+0xae>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
|
|
800802a: 68bb ldr r3, [r7, #8]
|
|
800802c: 015a lsls r2, r3, #5
|
|
800802e: 68fb ldr r3, [r7, #12]
|
|
8008030: 4413 add r3, r2
|
|
8008032: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008036: 681b ldr r3, [r3, #0]
|
|
8008038: 68ba ldr r2, [r7, #8]
|
|
800803a: 0151 lsls r1, r2, #5
|
|
800803c: 68fa ldr r2, [r7, #12]
|
|
800803e: 440a add r2, r1
|
|
8008040: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008044: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8008048: 6013 str r3, [r2, #0]
|
|
}
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
|
|
800804a: 68bb ldr r3, [r7, #8]
|
|
800804c: 015a lsls r2, r3, #5
|
|
800804e: 68fb ldr r3, [r7, #12]
|
|
8008050: 4413 add r3, r2
|
|
8008052: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008056: 681b ldr r3, [r3, #0]
|
|
8008058: 68ba ldr r2, [r7, #8]
|
|
800805a: 0151 lsls r1, r2, #5
|
|
800805c: 68fa ldr r2, [r7, #12]
|
|
800805e: 440a add r2, r1
|
|
8008060: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008064: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
|
|
8008068: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
800806a: 2300 movs r3, #0
|
|
}
|
|
800806c: 4618 mov r0, r3
|
|
800806e: 3714 adds r7, #20
|
|
8008070: 46bd mov sp, r7
|
|
8008072: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008076: 4770 bx lr
|
|
|
|
08008078 <USB_EPClearStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
|
|
{
|
|
8008078: b480 push {r7}
|
|
800807a: b085 sub sp, #20
|
|
800807c: af00 add r7, sp, #0
|
|
800807e: 6078 str r0, [r7, #4]
|
|
8008080: 6039 str r1, [r7, #0]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8008082: 687b ldr r3, [r7, #4]
|
|
8008084: 60fb str r3, [r7, #12]
|
|
uint32_t epnum = (uint32_t)ep->num;
|
|
8008086: 683b ldr r3, [r7, #0]
|
|
8008088: 781b ldrb r3, [r3, #0]
|
|
800808a: 60bb str r3, [r7, #8]
|
|
|
|
if (ep->is_in == 1U)
|
|
800808c: 683b ldr r3, [r7, #0]
|
|
800808e: 785b ldrb r3, [r3, #1]
|
|
8008090: 2b01 cmp r3, #1
|
|
8008092: d128 bne.n 80080e6 <USB_EPClearStall+0x6e>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
|
8008094: 68bb ldr r3, [r7, #8]
|
|
8008096: 015a lsls r2, r3, #5
|
|
8008098: 68fb ldr r3, [r7, #12]
|
|
800809a: 4413 add r3, r2
|
|
800809c: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80080a0: 681b ldr r3, [r3, #0]
|
|
80080a2: 68ba ldr r2, [r7, #8]
|
|
80080a4: 0151 lsls r1, r2, #5
|
|
80080a6: 68fa ldr r2, [r7, #12]
|
|
80080a8: 440a add r2, r1
|
|
80080aa: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80080ae: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
80080b2: 6013 str r3, [r2, #0]
|
|
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
|
|
80080b4: 683b ldr r3, [r7, #0]
|
|
80080b6: 791b ldrb r3, [r3, #4]
|
|
80080b8: 2b03 cmp r3, #3
|
|
80080ba: d003 beq.n 80080c4 <USB_EPClearStall+0x4c>
|
|
80080bc: 683b ldr r3, [r7, #0]
|
|
80080be: 791b ldrb r3, [r3, #4]
|
|
80080c0: 2b02 cmp r3, #2
|
|
80080c2: d138 bne.n 8008136 <USB_EPClearStall+0xbe>
|
|
{
|
|
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
|
|
80080c4: 68bb ldr r3, [r7, #8]
|
|
80080c6: 015a lsls r2, r3, #5
|
|
80080c8: 68fb ldr r3, [r7, #12]
|
|
80080ca: 4413 add r3, r2
|
|
80080cc: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
80080d0: 681b ldr r3, [r3, #0]
|
|
80080d2: 68ba ldr r2, [r7, #8]
|
|
80080d4: 0151 lsls r1, r2, #5
|
|
80080d6: 68fa ldr r2, [r7, #12]
|
|
80080d8: 440a add r2, r1
|
|
80080da: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
80080de: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80080e2: 6013 str r3, [r2, #0]
|
|
80080e4: e027 b.n 8008136 <USB_EPClearStall+0xbe>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
|
80080e6: 68bb ldr r3, [r7, #8]
|
|
80080e8: 015a lsls r2, r3, #5
|
|
80080ea: 68fb ldr r3, [r7, #12]
|
|
80080ec: 4413 add r3, r2
|
|
80080ee: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80080f2: 681b ldr r3, [r3, #0]
|
|
80080f4: 68ba ldr r2, [r7, #8]
|
|
80080f6: 0151 lsls r1, r2, #5
|
|
80080f8: 68fa ldr r2, [r7, #12]
|
|
80080fa: 440a add r2, r1
|
|
80080fc: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008100: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
8008104: 6013 str r3, [r2, #0]
|
|
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
|
|
8008106: 683b ldr r3, [r7, #0]
|
|
8008108: 791b ldrb r3, [r3, #4]
|
|
800810a: 2b03 cmp r3, #3
|
|
800810c: d003 beq.n 8008116 <USB_EPClearStall+0x9e>
|
|
800810e: 683b ldr r3, [r7, #0]
|
|
8008110: 791b ldrb r3, [r3, #4]
|
|
8008112: 2b02 cmp r3, #2
|
|
8008114: d10f bne.n 8008136 <USB_EPClearStall+0xbe>
|
|
{
|
|
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
|
|
8008116: 68bb ldr r3, [r7, #8]
|
|
8008118: 015a lsls r2, r3, #5
|
|
800811a: 68fb ldr r3, [r7, #12]
|
|
800811c: 4413 add r3, r2
|
|
800811e: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008122: 681b ldr r3, [r3, #0]
|
|
8008124: 68ba ldr r2, [r7, #8]
|
|
8008126: 0151 lsls r1, r2, #5
|
|
8008128: 68fa ldr r2, [r7, #12]
|
|
800812a: 440a add r2, r1
|
|
800812c: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008130: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8008134: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8008136: 2300 movs r3, #0
|
|
}
|
|
8008138: 4618 mov r0, r3
|
|
800813a: 3714 adds r7, #20
|
|
800813c: 46bd mov sp, r7
|
|
800813e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008142: 4770 bx lr
|
|
|
|
08008144 <USB_SetDevAddress>:
|
|
* @param address new device address to be assigned
|
|
* This parameter can be a value from 0 to 255
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
|
|
{
|
|
8008144: b480 push {r7}
|
|
8008146: b085 sub sp, #20
|
|
8008148: af00 add r7, sp, #0
|
|
800814a: 6078 str r0, [r7, #4]
|
|
800814c: 460b mov r3, r1
|
|
800814e: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8008150: 687b ldr r3, [r7, #4]
|
|
8008152: 60fb str r3, [r7, #12]
|
|
|
|
USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
|
|
8008154: 68fb ldr r3, [r7, #12]
|
|
8008156: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800815a: 681b ldr r3, [r3, #0]
|
|
800815c: 68fa ldr r2, [r7, #12]
|
|
800815e: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8008162: f423 63fe bic.w r3, r3, #2032 @ 0x7f0
|
|
8008166: 6013 str r3, [r2, #0]
|
|
USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
|
|
8008168: 68fb ldr r3, [r7, #12]
|
|
800816a: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800816e: 681a ldr r2, [r3, #0]
|
|
8008170: 78fb ldrb r3, [r7, #3]
|
|
8008172: 011b lsls r3, r3, #4
|
|
8008174: f403 63fe and.w r3, r3, #2032 @ 0x7f0
|
|
8008178: 68f9 ldr r1, [r7, #12]
|
|
800817a: f501 6100 add.w r1, r1, #2048 @ 0x800
|
|
800817e: 4313 orrs r3, r2
|
|
8008180: 600b str r3, [r1, #0]
|
|
|
|
return HAL_OK;
|
|
8008182: 2300 movs r3, #0
|
|
}
|
|
8008184: 4618 mov r0, r3
|
|
8008186: 3714 adds r7, #20
|
|
8008188: 46bd mov sp, r7
|
|
800818a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800818e: 4770 bx lr
|
|
|
|
08008190 <USB_DevConnect>:
|
|
* @brief USB_DevConnect : Connect the USB device by enabling Rpu
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8008190: b480 push {r7}
|
|
8008192: b085 sub sp, #20
|
|
8008194: af00 add r7, sp, #0
|
|
8008196: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8008198: 687b ldr r3, [r7, #4]
|
|
800819a: 60fb str r3, [r7, #12]
|
|
|
|
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
|
|
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
|
|
800819c: 68fb ldr r3, [r7, #12]
|
|
800819e: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80081a2: 681b ldr r3, [r3, #0]
|
|
80081a4: 68fa ldr r2, [r7, #12]
|
|
80081a6: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
80081aa: f023 0303 bic.w r3, r3, #3
|
|
80081ae: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
|
|
80081b0: 68fb ldr r3, [r7, #12]
|
|
80081b2: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80081b6: 685b ldr r3, [r3, #4]
|
|
80081b8: 68fa ldr r2, [r7, #12]
|
|
80081ba: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
80081be: f023 0302 bic.w r3, r3, #2
|
|
80081c2: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
80081c4: 2300 movs r3, #0
|
|
}
|
|
80081c6: 4618 mov r0, r3
|
|
80081c8: 3714 adds r7, #20
|
|
80081ca: 46bd mov sp, r7
|
|
80081cc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80081d0: 4770 bx lr
|
|
|
|
080081d2 <USB_DevDisconnect>:
|
|
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80081d2: b480 push {r7}
|
|
80081d4: b085 sub sp, #20
|
|
80081d6: af00 add r7, sp, #0
|
|
80081d8: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80081da: 687b ldr r3, [r7, #4]
|
|
80081dc: 60fb str r3, [r7, #12]
|
|
|
|
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
|
|
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
|
|
80081de: 68fb ldr r3, [r7, #12]
|
|
80081e0: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
80081e4: 681b ldr r3, [r3, #0]
|
|
80081e6: 68fa ldr r2, [r7, #12]
|
|
80081e8: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
80081ec: f023 0303 bic.w r3, r3, #3
|
|
80081f0: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
|
80081f2: 68fb ldr r3, [r7, #12]
|
|
80081f4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80081f8: 685b ldr r3, [r3, #4]
|
|
80081fa: 68fa ldr r2, [r7, #12]
|
|
80081fc: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8008200: f043 0302 orr.w r3, r3, #2
|
|
8008204: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
8008206: 2300 movs r3, #0
|
|
}
|
|
8008208: 4618 mov r0, r3
|
|
800820a: 3714 adds r7, #20
|
|
800820c: 46bd mov sp, r7
|
|
800820e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008212: 4770 bx lr
|
|
|
|
08008214 <USB_ReadInterrupts>:
|
|
* @brief USB_ReadInterrupts: return the global USB interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Global Interrupt status
|
|
*/
|
|
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
|
|
{
|
|
8008214: b480 push {r7}
|
|
8008216: b085 sub sp, #20
|
|
8008218: af00 add r7, sp, #0
|
|
800821a: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx->GINTSTS;
|
|
800821c: 687b ldr r3, [r7, #4]
|
|
800821e: 695b ldr r3, [r3, #20]
|
|
8008220: 60fb str r3, [r7, #12]
|
|
tmpreg &= USBx->GINTMSK;
|
|
8008222: 687b ldr r3, [r7, #4]
|
|
8008224: 699b ldr r3, [r3, #24]
|
|
8008226: 68fa ldr r2, [r7, #12]
|
|
8008228: 4013 ands r3, r2
|
|
800822a: 60fb str r3, [r7, #12]
|
|
|
|
return tmpreg;
|
|
800822c: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800822e: 4618 mov r0, r3
|
|
8008230: 3714 adds r7, #20
|
|
8008232: 46bd mov sp, r7
|
|
8008234: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008238: 4770 bx lr
|
|
|
|
0800823a <USB_ReadDevAllOutEpInterrupt>:
|
|
* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Device OUT EP interrupt status
|
|
*/
|
|
uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800823a: b480 push {r7}
|
|
800823c: b085 sub sp, #20
|
|
800823e: af00 add r7, sp, #0
|
|
8008240: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8008242: 687b ldr r3, [r7, #4]
|
|
8008244: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_DEVICE->DAINT;
|
|
8008246: 68fb ldr r3, [r7, #12]
|
|
8008248: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800824c: 699b ldr r3, [r3, #24]
|
|
800824e: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DAINTMSK;
|
|
8008250: 68fb ldr r3, [r7, #12]
|
|
8008252: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8008256: 69db ldr r3, [r3, #28]
|
|
8008258: 68ba ldr r2, [r7, #8]
|
|
800825a: 4013 ands r3, r2
|
|
800825c: 60bb str r3, [r7, #8]
|
|
|
|
return ((tmpreg & 0xffff0000U) >> 16);
|
|
800825e: 68bb ldr r3, [r7, #8]
|
|
8008260: 0c1b lsrs r3, r3, #16
|
|
}
|
|
8008262: 4618 mov r0, r3
|
|
8008264: 3714 adds r7, #20
|
|
8008266: 46bd mov sp, r7
|
|
8008268: f85d 7b04 ldr.w r7, [sp], #4
|
|
800826c: 4770 bx lr
|
|
|
|
0800826e <USB_ReadDevAllInEpInterrupt>:
|
|
* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Device IN EP interrupt status
|
|
*/
|
|
uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800826e: b480 push {r7}
|
|
8008270: b085 sub sp, #20
|
|
8008272: af00 add r7, sp, #0
|
|
8008274: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8008276: 687b ldr r3, [r7, #4]
|
|
8008278: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_DEVICE->DAINT;
|
|
800827a: 68fb ldr r3, [r7, #12]
|
|
800827c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8008280: 699b ldr r3, [r3, #24]
|
|
8008282: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DAINTMSK;
|
|
8008284: 68fb ldr r3, [r7, #12]
|
|
8008286: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
800828a: 69db ldr r3, [r3, #28]
|
|
800828c: 68ba ldr r2, [r7, #8]
|
|
800828e: 4013 ands r3, r2
|
|
8008290: 60bb str r3, [r7, #8]
|
|
|
|
return ((tmpreg & 0xFFFFU));
|
|
8008292: 68bb ldr r3, [r7, #8]
|
|
8008294: b29b uxth r3, r3
|
|
}
|
|
8008296: 4618 mov r0, r3
|
|
8008298: 3714 adds r7, #20
|
|
800829a: 46bd mov sp, r7
|
|
800829c: f85d 7b04 ldr.w r7, [sp], #4
|
|
80082a0: 4770 bx lr
|
|
|
|
080082a2 <USB_ReadDevOutEPInterrupt>:
|
|
* @param epnum endpoint number
|
|
* This parameter can be a value from 0 to 15
|
|
* @retval Device OUT EP Interrupt register
|
|
*/
|
|
uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
|
|
{
|
|
80082a2: b480 push {r7}
|
|
80082a4: b085 sub sp, #20
|
|
80082a6: af00 add r7, sp, #0
|
|
80082a8: 6078 str r0, [r7, #4]
|
|
80082aa: 460b mov r3, r1
|
|
80082ac: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80082ae: 687b ldr r3, [r7, #4]
|
|
80082b0: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
|
|
80082b2: 78fb ldrb r3, [r7, #3]
|
|
80082b4: 015a lsls r2, r3, #5
|
|
80082b6: 68fb ldr r3, [r7, #12]
|
|
80082b8: 4413 add r3, r2
|
|
80082ba: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80082be: 689b ldr r3, [r3, #8]
|
|
80082c0: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_DEVICE->DOEPMSK;
|
|
80082c2: 68fb ldr r3, [r7, #12]
|
|
80082c4: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80082c8: 695b ldr r3, [r3, #20]
|
|
80082ca: 68ba ldr r2, [r7, #8]
|
|
80082cc: 4013 ands r3, r2
|
|
80082ce: 60bb str r3, [r7, #8]
|
|
|
|
return tmpreg;
|
|
80082d0: 68bb ldr r3, [r7, #8]
|
|
}
|
|
80082d2: 4618 mov r0, r3
|
|
80082d4: 3714 adds r7, #20
|
|
80082d6: 46bd mov sp, r7
|
|
80082d8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80082dc: 4770 bx lr
|
|
|
|
080082de <USB_ReadDevInEPInterrupt>:
|
|
* @param epnum endpoint number
|
|
* This parameter can be a value from 0 to 15
|
|
* @retval Device IN EP Interrupt register
|
|
*/
|
|
uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
|
|
{
|
|
80082de: b480 push {r7}
|
|
80082e0: b087 sub sp, #28
|
|
80082e2: af00 add r7, sp, #0
|
|
80082e4: 6078 str r0, [r7, #4]
|
|
80082e6: 460b mov r3, r1
|
|
80082e8: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80082ea: 687b ldr r3, [r7, #4]
|
|
80082ec: 617b str r3, [r7, #20]
|
|
uint32_t tmpreg;
|
|
uint32_t msk;
|
|
uint32_t emp;
|
|
|
|
msk = USBx_DEVICE->DIEPMSK;
|
|
80082ee: 697b ldr r3, [r7, #20]
|
|
80082f0: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80082f4: 691b ldr r3, [r3, #16]
|
|
80082f6: 613b str r3, [r7, #16]
|
|
emp = USBx_DEVICE->DIEPEMPMSK;
|
|
80082f8: 697b ldr r3, [r7, #20]
|
|
80082fa: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
80082fe: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8008300: 60fb str r3, [r7, #12]
|
|
msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
|
|
8008302: 78fb ldrb r3, [r7, #3]
|
|
8008304: f003 030f and.w r3, r3, #15
|
|
8008308: 68fa ldr r2, [r7, #12]
|
|
800830a: fa22 f303 lsr.w r3, r2, r3
|
|
800830e: 01db lsls r3, r3, #7
|
|
8008310: b2db uxtb r3, r3
|
|
8008312: 693a ldr r2, [r7, #16]
|
|
8008314: 4313 orrs r3, r2
|
|
8008316: 613b str r3, [r7, #16]
|
|
tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
|
|
8008318: 78fb ldrb r3, [r7, #3]
|
|
800831a: 015a lsls r2, r3, #5
|
|
800831c: 697b ldr r3, [r7, #20]
|
|
800831e: 4413 add r3, r2
|
|
8008320: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8008324: 689b ldr r3, [r3, #8]
|
|
8008326: 693a ldr r2, [r7, #16]
|
|
8008328: 4013 ands r3, r2
|
|
800832a: 60bb str r3, [r7, #8]
|
|
|
|
return tmpreg;
|
|
800832c: 68bb ldr r3, [r7, #8]
|
|
}
|
|
800832e: 4618 mov r0, r3
|
|
8008330: 371c adds r7, #28
|
|
8008332: 46bd mov sp, r7
|
|
8008334: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008338: 4770 bx lr
|
|
|
|
0800833a <USB_GetMode>:
|
|
* This parameter can be one of these values:
|
|
* 1 : Host
|
|
* 0 : Device
|
|
*/
|
|
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800833a: b480 push {r7}
|
|
800833c: b083 sub sp, #12
|
|
800833e: af00 add r7, sp, #0
|
|
8008340: 6078 str r0, [r7, #4]
|
|
return ((USBx->GINTSTS) & 0x1U);
|
|
8008342: 687b ldr r3, [r7, #4]
|
|
8008344: 695b ldr r3, [r3, #20]
|
|
8008346: f003 0301 and.w r3, r3, #1
|
|
}
|
|
800834a: 4618 mov r0, r3
|
|
800834c: 370c adds r7, #12
|
|
800834e: 46bd mov sp, r7
|
|
8008350: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008354: 4770 bx lr
|
|
|
|
08008356 <USB_ActivateSetup>:
|
|
* @brief Activate EP0 for Setup transactions
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8008356: b480 push {r7}
|
|
8008358: b085 sub sp, #20
|
|
800835a: af00 add r7, sp, #0
|
|
800835c: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800835e: 687b ldr r3, [r7, #4]
|
|
8008360: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the MPS of the IN EP0 to 64 bytes */
|
|
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
|
|
8008362: 68fb ldr r3, [r7, #12]
|
|
8008364: f503 6310 add.w r3, r3, #2304 @ 0x900
|
|
8008368: 681b ldr r3, [r3, #0]
|
|
800836a: 68fa ldr r2, [r7, #12]
|
|
800836c: f502 6210 add.w r2, r2, #2304 @ 0x900
|
|
8008370: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
|
|
8008374: f023 0307 bic.w r3, r3, #7
|
|
8008378: 6013 str r3, [r2, #0]
|
|
|
|
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
|
|
800837a: 68fb ldr r3, [r7, #12]
|
|
800837c: f503 6300 add.w r3, r3, #2048 @ 0x800
|
|
8008380: 685b ldr r3, [r3, #4]
|
|
8008382: 68fa ldr r2, [r7, #12]
|
|
8008384: f502 6200 add.w r2, r2, #2048 @ 0x800
|
|
8008388: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
800838c: 6053 str r3, [r2, #4]
|
|
|
|
return HAL_OK;
|
|
800838e: 2300 movs r3, #0
|
|
}
|
|
8008390: 4618 mov r0, r3
|
|
8008392: 3714 adds r7, #20
|
|
8008394: 46bd mov sp, r7
|
|
8008396: f85d 7b04 ldr.w r7, [sp], #4
|
|
800839a: 4770 bx lr
|
|
|
|
0800839c <USB_EP0_OutStart>:
|
|
* 1 : DMA feature used
|
|
* @param psetup pointer to setup packet
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup)
|
|
{
|
|
800839c: b480 push {r7}
|
|
800839e: b087 sub sp, #28
|
|
80083a0: af00 add r7, sp, #0
|
|
80083a2: 60f8 str r0, [r7, #12]
|
|
80083a4: 460b mov r3, r1
|
|
80083a6: 607a str r2, [r7, #4]
|
|
80083a8: 72fb strb r3, [r7, #11]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80083aa: 68fb ldr r3, [r7, #12]
|
|
80083ac: 617b str r3, [r7, #20]
|
|
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
|
|
80083ae: 68fb ldr r3, [r7, #12]
|
|
80083b0: 333c adds r3, #60 @ 0x3c
|
|
80083b2: 3304 adds r3, #4
|
|
80083b4: 681b ldr r3, [r3, #0]
|
|
80083b6: 613b str r3, [r7, #16]
|
|
|
|
if (gSNPSiD > USB_OTG_CORE_ID_300A)
|
|
80083b8: 693b ldr r3, [r7, #16]
|
|
80083ba: 4a26 ldr r2, [pc, #152] @ (8008454 <USB_EP0_OutStart+0xb8>)
|
|
80083bc: 4293 cmp r3, r2
|
|
80083be: d90a bls.n 80083d6 <USB_EP0_OutStart+0x3a>
|
|
{
|
|
if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
|
|
80083c0: 697b ldr r3, [r7, #20]
|
|
80083c2: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80083c6: 681b ldr r3, [r3, #0]
|
|
80083c8: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
80083cc: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80083d0: d101 bne.n 80083d6 <USB_EP0_OutStart+0x3a>
|
|
{
|
|
return HAL_OK;
|
|
80083d2: 2300 movs r3, #0
|
|
80083d4: e037 b.n 8008446 <USB_EP0_OutStart+0xaa>
|
|
}
|
|
}
|
|
|
|
USBx_OUTEP(0U)->DOEPTSIZ = 0U;
|
|
80083d6: 697b ldr r3, [r7, #20]
|
|
80083d8: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80083dc: 461a mov r2, r3
|
|
80083de: 2300 movs r3, #0
|
|
80083e0: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
|
80083e2: 697b ldr r3, [r7, #20]
|
|
80083e4: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80083e8: 691b ldr r3, [r3, #16]
|
|
80083ea: 697a ldr r2, [r7, #20]
|
|
80083ec: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
80083f0: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
80083f4: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
|
|
80083f6: 697b ldr r3, [r7, #20]
|
|
80083f8: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
80083fc: 691b ldr r3, [r3, #16]
|
|
80083fe: 697a ldr r2, [r7, #20]
|
|
8008400: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008404: f043 0318 orr.w r3, r3, #24
|
|
8008408: 6113 str r3, [r2, #16]
|
|
USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
|
|
800840a: 697b ldr r3, [r7, #20]
|
|
800840c: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008410: 691b ldr r3, [r3, #16]
|
|
8008412: 697a ldr r2, [r7, #20]
|
|
8008414: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
8008418: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000
|
|
800841c: 6113 str r3, [r2, #16]
|
|
|
|
if (dma == 1U)
|
|
800841e: 7afb ldrb r3, [r7, #11]
|
|
8008420: 2b01 cmp r3, #1
|
|
8008422: d10f bne.n 8008444 <USB_EP0_OutStart+0xa8>
|
|
{
|
|
USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
|
|
8008424: 697b ldr r3, [r7, #20]
|
|
8008426: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
800842a: 461a mov r2, r3
|
|
800842c: 687b ldr r3, [r7, #4]
|
|
800842e: 6153 str r3, [r2, #20]
|
|
/* EP enable */
|
|
USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
|
|
8008430: 697b ldr r3, [r7, #20]
|
|
8008432: f503 6330 add.w r3, r3, #2816 @ 0xb00
|
|
8008436: 681b ldr r3, [r3, #0]
|
|
8008438: 697a ldr r2, [r7, #20]
|
|
800843a: f502 6230 add.w r2, r2, #2816 @ 0xb00
|
|
800843e: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000
|
|
8008442: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8008444: 2300 movs r3, #0
|
|
}
|
|
8008446: 4618 mov r0, r3
|
|
8008448: 371c adds r7, #28
|
|
800844a: 46bd mov sp, r7
|
|
800844c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008450: 4770 bx lr
|
|
8008452: bf00 nop
|
|
8008454: 4f54300a .word 0x4f54300a
|
|
|
|
08008458 <USB_CoreReset>:
|
|
* @brief Reset the USB Core (needed after USB clock settings change)
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8008458: b480 push {r7}
|
|
800845a: b085 sub sp, #20
|
|
800845c: af00 add r7, sp, #0
|
|
800845e: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
8008460: 2300 movs r3, #0
|
|
8008462: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
8008464: 68fb ldr r3, [r7, #12]
|
|
8008466: 3301 adds r3, #1
|
|
8008468: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800846a: 68fb ldr r3, [r7, #12]
|
|
800846c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8008470: d901 bls.n 8008476 <USB_CoreReset+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8008472: 2303 movs r3, #3
|
|
8008474: e022 b.n 80084bc <USB_CoreReset+0x64>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
8008476: 687b ldr r3, [r7, #4]
|
|
8008478: 691b ldr r3, [r3, #16]
|
|
800847a: 2b00 cmp r3, #0
|
|
800847c: daf2 bge.n 8008464 <USB_CoreReset+0xc>
|
|
|
|
count = 10U;
|
|
800847e: 230a movs r3, #10
|
|
8008480: 60fb str r3, [r7, #12]
|
|
|
|
/* few cycles before setting core reset */
|
|
while (count > 0U)
|
|
8008482: e002 b.n 800848a <USB_CoreReset+0x32>
|
|
{
|
|
count--;
|
|
8008484: 68fb ldr r3, [r7, #12]
|
|
8008486: 3b01 subs r3, #1
|
|
8008488: 60fb str r3, [r7, #12]
|
|
while (count > 0U)
|
|
800848a: 68fb ldr r3, [r7, #12]
|
|
800848c: 2b00 cmp r3, #0
|
|
800848e: d1f9 bne.n 8008484 <USB_CoreReset+0x2c>
|
|
}
|
|
|
|
/* Core Soft Reset */
|
|
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
|
|
8008490: 687b ldr r3, [r7, #4]
|
|
8008492: 691b ldr r3, [r3, #16]
|
|
8008494: f043 0201 orr.w r2, r3, #1
|
|
8008498: 687b ldr r3, [r7, #4]
|
|
800849a: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
800849c: 68fb ldr r3, [r7, #12]
|
|
800849e: 3301 adds r3, #1
|
|
80084a0: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80084a2: 68fb ldr r3, [r7, #12]
|
|
80084a4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80084a8: d901 bls.n 80084ae <USB_CoreReset+0x56>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80084aa: 2303 movs r3, #3
|
|
80084ac: e006 b.n 80084bc <USB_CoreReset+0x64>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
|
|
80084ae: 687b ldr r3, [r7, #4]
|
|
80084b0: 691b ldr r3, [r3, #16]
|
|
80084b2: f003 0301 and.w r3, r3, #1
|
|
80084b6: 2b01 cmp r3, #1
|
|
80084b8: d0f0 beq.n 800849c <USB_CoreReset+0x44>
|
|
|
|
return HAL_OK;
|
|
80084ba: 2300 movs r3, #0
|
|
}
|
|
80084bc: 4618 mov r0, r3
|
|
80084be: 3714 adds r7, #20
|
|
80084c0: 46bd mov sp, r7
|
|
80084c2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80084c6: 4770 bx lr
|
|
|
|
080084c8 <USBD_HID_Init>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
80084c8: b580 push {r7, lr}
|
|
80084ca: b084 sub sp, #16
|
|
80084cc: af00 add r7, sp, #0
|
|
80084ce: 6078 str r0, [r7, #4]
|
|
80084d0: 460b mov r3, r1
|
|
80084d2: 70fb strb r3, [r7, #3]
|
|
UNUSED(cfgidx);
|
|
|
|
USBD_HID_HandleTypeDef *hhid;
|
|
|
|
hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef));
|
|
80084d4: 2010 movs r0, #16
|
|
80084d6: f002 f9e3 bl 800a8a0 <USBD_static_malloc>
|
|
80084da: 60f8 str r0, [r7, #12]
|
|
|
|
if (hhid == NULL)
|
|
80084dc: 68fb ldr r3, [r7, #12]
|
|
80084de: 2b00 cmp r3, #0
|
|
80084e0: d109 bne.n 80084f6 <USBD_HID_Init+0x2e>
|
|
{
|
|
pdev->pClassDataCmsit[pdev->classId] = NULL;
|
|
80084e2: 687b ldr r3, [r7, #4]
|
|
80084e4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80084e8: 687b ldr r3, [r7, #4]
|
|
80084ea: 32b0 adds r2, #176 @ 0xb0
|
|
80084ec: 2100 movs r1, #0
|
|
80084ee: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
return (uint8_t)USBD_EMEM;
|
|
80084f2: 2302 movs r3, #2
|
|
80084f4: e048 b.n 8008588 <USBD_HID_Init+0xc0>
|
|
}
|
|
|
|
pdev->pClassDataCmsit[pdev->classId] = (void *)hhid;
|
|
80084f6: 687b ldr r3, [r7, #4]
|
|
80084f8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80084fc: 687b ldr r3, [r7, #4]
|
|
80084fe: 32b0 adds r2, #176 @ 0xb0
|
|
8008500: 68f9 ldr r1, [r7, #12]
|
|
8008502: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
|
|
8008506: 687b ldr r3, [r7, #4]
|
|
8008508: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800850c: 687b ldr r3, [r7, #4]
|
|
800850e: 32b0 adds r2, #176 @ 0xb0
|
|
8008510: f853 2022 ldr.w r2, [r3, r2, lsl #2]
|
|
8008514: 687b ldr r3, [r7, #4]
|
|
8008516: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
|
|
#ifdef USE_USBD_COMPOSITE
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
800851a: 687b ldr r3, [r7, #4]
|
|
800851c: 7c1b ldrb r3, [r3, #16]
|
|
800851e: 2b00 cmp r3, #0
|
|
8008520: d10d bne.n 800853e <USBD_HID_Init+0x76>
|
|
{
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL;
|
|
8008522: 4b1b ldr r3, [pc, #108] @ (8008590 <USBD_HID_Init+0xc8>)
|
|
8008524: 781b ldrb r3, [r3, #0]
|
|
8008526: f003 020f and.w r2, r3, #15
|
|
800852a: 6879 ldr r1, [r7, #4]
|
|
800852c: 4613 mov r3, r2
|
|
800852e: 009b lsls r3, r3, #2
|
|
8008530: 4413 add r3, r2
|
|
8008532: 009b lsls r3, r3, #2
|
|
8008534: 440b add r3, r1
|
|
8008536: 331c adds r3, #28
|
|
8008538: 2207 movs r2, #7
|
|
800853a: 601a str r2, [r3, #0]
|
|
800853c: e00c b.n 8008558 <USBD_HID_Init+0x90>
|
|
}
|
|
else /* LOW and FULL-speed endpoints */
|
|
{
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL;
|
|
800853e: 4b14 ldr r3, [pc, #80] @ (8008590 <USBD_HID_Init+0xc8>)
|
|
8008540: 781b ldrb r3, [r3, #0]
|
|
8008542: f003 020f and.w r2, r3, #15
|
|
8008546: 6879 ldr r1, [r7, #4]
|
|
8008548: 4613 mov r3, r2
|
|
800854a: 009b lsls r3, r3, #2
|
|
800854c: 4413 add r3, r2
|
|
800854e: 009b lsls r3, r3, #2
|
|
8008550: 440b add r3, r1
|
|
8008552: 331c adds r3, #28
|
|
8008554: 220a movs r2, #10
|
|
8008556: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Open EP IN */
|
|
(void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE);
|
|
8008558: 4b0d ldr r3, [pc, #52] @ (8008590 <USBD_HID_Init+0xc8>)
|
|
800855a: 7819 ldrb r1, [r3, #0]
|
|
800855c: 230e movs r3, #14
|
|
800855e: 2203 movs r2, #3
|
|
8008560: 6878 ldr r0, [r7, #4]
|
|
8008562: f002 f83e bl 800a5e2 <USBD_LL_OpenEP>
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U;
|
|
8008566: 4b0a ldr r3, [pc, #40] @ (8008590 <USBD_HID_Init+0xc8>)
|
|
8008568: 781b ldrb r3, [r3, #0]
|
|
800856a: f003 020f and.w r2, r3, #15
|
|
800856e: 6879 ldr r1, [r7, #4]
|
|
8008570: 4613 mov r3, r2
|
|
8008572: 009b lsls r3, r3, #2
|
|
8008574: 4413 add r3, r2
|
|
8008576: 009b lsls r3, r3, #2
|
|
8008578: 440b add r3, r1
|
|
800857a: 3323 adds r3, #35 @ 0x23
|
|
800857c: 2201 movs r2, #1
|
|
800857e: 701a strb r2, [r3, #0]
|
|
|
|
hhid->state = USBD_HID_IDLE;
|
|
8008580: 68fb ldr r3, [r7, #12]
|
|
8008582: 2200 movs r2, #0
|
|
8008584: 731a strb r2, [r3, #12]
|
|
|
|
return (uint8_t)USBD_OK;
|
|
8008586: 2300 movs r3, #0
|
|
}
|
|
8008588: 4618 mov r0, r3
|
|
800858a: 3710 adds r7, #16
|
|
800858c: 46bd mov sp, r7
|
|
800858e: bd80 pop {r7, pc}
|
|
8008590: 2000013d .word 0x2000013d
|
|
|
|
08008594 <USBD_HID_DeInit>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8008594: b580 push {r7, lr}
|
|
8008596: b082 sub sp, #8
|
|
8008598: af00 add r7, sp, #0
|
|
800859a: 6078 str r0, [r7, #4]
|
|
800859c: 460b mov r3, r1
|
|
800859e: 70fb strb r3, [r7, #3]
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Close HID EPs */
|
|
(void)USBD_LL_CloseEP(pdev, HIDInEpAdd);
|
|
80085a0: 4b1f ldr r3, [pc, #124] @ (8008620 <USBD_HID_DeInit+0x8c>)
|
|
80085a2: 781b ldrb r3, [r3, #0]
|
|
80085a4: 4619 mov r1, r3
|
|
80085a6: 6878 ldr r0, [r7, #4]
|
|
80085a8: f002 f841 bl 800a62e <USBD_LL_CloseEP>
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U;
|
|
80085ac: 4b1c ldr r3, [pc, #112] @ (8008620 <USBD_HID_DeInit+0x8c>)
|
|
80085ae: 781b ldrb r3, [r3, #0]
|
|
80085b0: f003 020f and.w r2, r3, #15
|
|
80085b4: 6879 ldr r1, [r7, #4]
|
|
80085b6: 4613 mov r3, r2
|
|
80085b8: 009b lsls r3, r3, #2
|
|
80085ba: 4413 add r3, r2
|
|
80085bc: 009b lsls r3, r3, #2
|
|
80085be: 440b add r3, r1
|
|
80085c0: 3323 adds r3, #35 @ 0x23
|
|
80085c2: 2200 movs r2, #0
|
|
80085c4: 701a strb r2, [r3, #0]
|
|
pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U;
|
|
80085c6: 4b16 ldr r3, [pc, #88] @ (8008620 <USBD_HID_DeInit+0x8c>)
|
|
80085c8: 781b ldrb r3, [r3, #0]
|
|
80085ca: f003 020f and.w r2, r3, #15
|
|
80085ce: 6879 ldr r1, [r7, #4]
|
|
80085d0: 4613 mov r3, r2
|
|
80085d2: 009b lsls r3, r3, #2
|
|
80085d4: 4413 add r3, r2
|
|
80085d6: 009b lsls r3, r3, #2
|
|
80085d8: 440b add r3, r1
|
|
80085da: 331c adds r3, #28
|
|
80085dc: 2200 movs r2, #0
|
|
80085de: 601a str r2, [r3, #0]
|
|
|
|
/* Free allocated memory */
|
|
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
|
|
80085e0: 687b ldr r3, [r7, #4]
|
|
80085e2: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80085e6: 687b ldr r3, [r7, #4]
|
|
80085e8: 32b0 adds r2, #176 @ 0xb0
|
|
80085ea: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80085ee: 2b00 cmp r3, #0
|
|
80085f0: d011 beq.n 8008616 <USBD_HID_DeInit+0x82>
|
|
{
|
|
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
|
|
80085f2: 687b ldr r3, [r7, #4]
|
|
80085f4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80085f8: 687b ldr r3, [r7, #4]
|
|
80085fa: 32b0 adds r2, #176 @ 0xb0
|
|
80085fc: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008600: 4618 mov r0, r3
|
|
8008602: f002 f95b bl 800a8bc <USBD_static_free>
|
|
pdev->pClassDataCmsit[pdev->classId] = NULL;
|
|
8008606: 687b ldr r3, [r7, #4]
|
|
8008608: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800860c: 687b ldr r3, [r7, #4]
|
|
800860e: 32b0 adds r2, #176 @ 0xb0
|
|
8008610: 2100 movs r1, #0
|
|
8008612: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
8008616: 2300 movs r3, #0
|
|
}
|
|
8008618: 4618 mov r0, r3
|
|
800861a: 3708 adds r7, #8
|
|
800861c: 46bd mov sp, r7
|
|
800861e: bd80 pop {r7, pc}
|
|
8008620: 2000013d .word 0x2000013d
|
|
|
|
08008624 <USBD_HID_Setup>:
|
|
* @param pdev: instance
|
|
* @param req: usb requests
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8008624: b580 push {r7, lr}
|
|
8008626: b086 sub sp, #24
|
|
8008628: af00 add r7, sp, #0
|
|
800862a: 6078 str r0, [r7, #4]
|
|
800862c: 6039 str r1, [r7, #0]
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
800862e: 687b ldr r3, [r7, #4]
|
|
8008630: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008634: 687b ldr r3, [r7, #4]
|
|
8008636: 32b0 adds r2, #176 @ 0xb0
|
|
8008638: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800863c: 60fb str r3, [r7, #12]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
800863e: 2300 movs r3, #0
|
|
8008640: 75fb strb r3, [r7, #23]
|
|
uint16_t len;
|
|
uint8_t *pbuf;
|
|
uint16_t status_info = 0U;
|
|
8008642: 2300 movs r3, #0
|
|
8008644: 817b strh r3, [r7, #10]
|
|
|
|
if (hhid == NULL)
|
|
8008646: 68fb ldr r3, [r7, #12]
|
|
8008648: 2b00 cmp r3, #0
|
|
800864a: d101 bne.n 8008650 <USBD_HID_Setup+0x2c>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
800864c: 2303 movs r3, #3
|
|
800864e: e0e8 b.n 8008822 <USBD_HID_Setup+0x1fe>
|
|
}
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8008650: 683b ldr r3, [r7, #0]
|
|
8008652: 781b ldrb r3, [r3, #0]
|
|
8008654: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8008658: 2b00 cmp r3, #0
|
|
800865a: d046 beq.n 80086ea <USBD_HID_Setup+0xc6>
|
|
800865c: 2b20 cmp r3, #32
|
|
800865e: f040 80d8 bne.w 8008812 <USBD_HID_Setup+0x1ee>
|
|
{
|
|
case USB_REQ_TYPE_CLASS :
|
|
switch (req->bRequest)
|
|
8008662: 683b ldr r3, [r7, #0]
|
|
8008664: 785b ldrb r3, [r3, #1]
|
|
8008666: 3b02 subs r3, #2
|
|
8008668: 2b09 cmp r3, #9
|
|
800866a: d836 bhi.n 80086da <USBD_HID_Setup+0xb6>
|
|
800866c: a201 add r2, pc, #4 @ (adr r2, 8008674 <USBD_HID_Setup+0x50>)
|
|
800866e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8008672: bf00 nop
|
|
8008674: 080086cb .word 0x080086cb
|
|
8008678: 080086ab .word 0x080086ab
|
|
800867c: 080086db .word 0x080086db
|
|
8008680: 080086db .word 0x080086db
|
|
8008684: 080086db .word 0x080086db
|
|
8008688: 080086db .word 0x080086db
|
|
800868c: 080086db .word 0x080086db
|
|
8008690: 080086db .word 0x080086db
|
|
8008694: 080086b9 .word 0x080086b9
|
|
8008698: 0800869d .word 0x0800869d
|
|
{
|
|
case USBD_HID_REQ_SET_PROTOCOL:
|
|
hhid->Protocol = (uint8_t)(req->wValue);
|
|
800869c: 683b ldr r3, [r7, #0]
|
|
800869e: 885b ldrh r3, [r3, #2]
|
|
80086a0: b2db uxtb r3, r3
|
|
80086a2: 461a mov r2, r3
|
|
80086a4: 68fb ldr r3, [r7, #12]
|
|
80086a6: 601a str r2, [r3, #0]
|
|
break;
|
|
80086a8: e01e b.n 80086e8 <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_GET_PROTOCOL:
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U);
|
|
80086aa: 68fb ldr r3, [r7, #12]
|
|
80086ac: 2201 movs r2, #1
|
|
80086ae: 4619 mov r1, r3
|
|
80086b0: 6878 ldr r0, [r7, #4]
|
|
80086b2: f001 fc25 bl 8009f00 <USBD_CtlSendData>
|
|
break;
|
|
80086b6: e017 b.n 80086e8 <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_SET_IDLE:
|
|
hhid->IdleState = (uint8_t)(req->wValue >> 8);
|
|
80086b8: 683b ldr r3, [r7, #0]
|
|
80086ba: 885b ldrh r3, [r3, #2]
|
|
80086bc: 0a1b lsrs r3, r3, #8
|
|
80086be: b29b uxth r3, r3
|
|
80086c0: b2db uxtb r3, r3
|
|
80086c2: 461a mov r2, r3
|
|
80086c4: 68fb ldr r3, [r7, #12]
|
|
80086c6: 605a str r2, [r3, #4]
|
|
break;
|
|
80086c8: e00e b.n 80086e8 <USBD_HID_Setup+0xc4>
|
|
|
|
case USBD_HID_REQ_GET_IDLE:
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U);
|
|
80086ca: 68fb ldr r3, [r7, #12]
|
|
80086cc: 3304 adds r3, #4
|
|
80086ce: 2201 movs r2, #1
|
|
80086d0: 4619 mov r1, r3
|
|
80086d2: 6878 ldr r0, [r7, #4]
|
|
80086d4: f001 fc14 bl 8009f00 <USBD_CtlSendData>
|
|
break;
|
|
80086d8: e006 b.n 80086e8 <USBD_HID_Setup+0xc4>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80086da: 6839 ldr r1, [r7, #0]
|
|
80086dc: 6878 ldr r0, [r7, #4]
|
|
80086de: f001 fb92 bl 8009e06 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
80086e2: 2303 movs r3, #3
|
|
80086e4: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80086e6: bf00 nop
|
|
}
|
|
break;
|
|
80086e8: e09a b.n 8008820 <USBD_HID_Setup+0x1fc>
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
80086ea: 683b ldr r3, [r7, #0]
|
|
80086ec: 785b ldrb r3, [r3, #1]
|
|
80086ee: 2b0b cmp r3, #11
|
|
80086f0: f200 8086 bhi.w 8008800 <USBD_HID_Setup+0x1dc>
|
|
80086f4: a201 add r2, pc, #4 @ (adr r2, 80086fc <USBD_HID_Setup+0xd8>)
|
|
80086f6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80086fa: bf00 nop
|
|
80086fc: 0800872d .word 0x0800872d
|
|
8008700: 0800880f .word 0x0800880f
|
|
8008704: 08008801 .word 0x08008801
|
|
8008708: 08008801 .word 0x08008801
|
|
800870c: 08008801 .word 0x08008801
|
|
8008710: 08008801 .word 0x08008801
|
|
8008714: 08008757 .word 0x08008757
|
|
8008718: 08008801 .word 0x08008801
|
|
800871c: 08008801 .word 0x08008801
|
|
8008720: 08008801 .word 0x08008801
|
|
8008724: 080087af .word 0x080087af
|
|
8008728: 080087d9 .word 0x080087d9
|
|
{
|
|
case USB_REQ_GET_STATUS:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
800872c: 687b ldr r3, [r7, #4]
|
|
800872e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008732: b2db uxtb r3, r3
|
|
8008734: 2b03 cmp r3, #3
|
|
8008736: d107 bne.n 8008748 <USBD_HID_Setup+0x124>
|
|
{
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
|
|
8008738: f107 030a add.w r3, r7, #10
|
|
800873c: 2202 movs r2, #2
|
|
800873e: 4619 mov r1, r3
|
|
8008740: 6878 ldr r0, [r7, #4]
|
|
8008742: f001 fbdd bl 8009f00 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
8008746: e063 b.n 8008810 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
8008748: 6839 ldr r1, [r7, #0]
|
|
800874a: 6878 ldr r0, [r7, #4]
|
|
800874c: f001 fb5b bl 8009e06 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8008750: 2303 movs r3, #3
|
|
8008752: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8008754: e05c b.n 8008810 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
if ((req->wValue >> 8) == HID_REPORT_DESC)
|
|
8008756: 683b ldr r3, [r7, #0]
|
|
8008758: 885b ldrh r3, [r3, #2]
|
|
800875a: 0a1b lsrs r3, r3, #8
|
|
800875c: b29b uxth r3, r3
|
|
800875e: 2b22 cmp r3, #34 @ 0x22
|
|
8008760: d108 bne.n 8008774 <USBD_HID_Setup+0x150>
|
|
{
|
|
len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength);
|
|
8008762: 683b ldr r3, [r7, #0]
|
|
8008764: 88db ldrh r3, [r3, #6]
|
|
8008766: 2b2d cmp r3, #45 @ 0x2d
|
|
8008768: bf28 it cs
|
|
800876a: 232d movcs r3, #45 @ 0x2d
|
|
800876c: 82bb strh r3, [r7, #20]
|
|
pbuf = HID_MOUSE_ReportDesc;
|
|
800876e: 4b2f ldr r3, [pc, #188] @ (800882c <USBD_HID_Setup+0x208>)
|
|
8008770: 613b str r3, [r7, #16]
|
|
8008772: e015 b.n 80087a0 <USBD_HID_Setup+0x17c>
|
|
}
|
|
else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE)
|
|
8008774: 683b ldr r3, [r7, #0]
|
|
8008776: 885b ldrh r3, [r3, #2]
|
|
8008778: 0a1b lsrs r3, r3, #8
|
|
800877a: b29b uxth r3, r3
|
|
800877c: 2b21 cmp r3, #33 @ 0x21
|
|
800877e: d108 bne.n 8008792 <USBD_HID_Setup+0x16e>
|
|
{
|
|
pbuf = USBD_HID_Desc;
|
|
8008780: 4b2b ldr r3, [pc, #172] @ (8008830 <USBD_HID_Setup+0x20c>)
|
|
8008782: 613b str r3, [r7, #16]
|
|
len = MIN(USB_HID_DESC_SIZ, req->wLength);
|
|
8008784: 683b ldr r3, [r7, #0]
|
|
8008786: 88db ldrh r3, [r3, #6]
|
|
8008788: 2b09 cmp r3, #9
|
|
800878a: bf28 it cs
|
|
800878c: 2309 movcs r3, #9
|
|
800878e: 82bb strh r3, [r7, #20]
|
|
8008790: e006 b.n 80087a0 <USBD_HID_Setup+0x17c>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8008792: 6839 ldr r1, [r7, #0]
|
|
8008794: 6878 ldr r0, [r7, #4]
|
|
8008796: f001 fb36 bl 8009e06 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
800879a: 2303 movs r3, #3
|
|
800879c: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800879e: e037 b.n 8008810 <USBD_HID_Setup+0x1ec>
|
|
}
|
|
(void)USBD_CtlSendData(pdev, pbuf, len);
|
|
80087a0: 8abb ldrh r3, [r7, #20]
|
|
80087a2: 461a mov r2, r3
|
|
80087a4: 6939 ldr r1, [r7, #16]
|
|
80087a6: 6878 ldr r0, [r7, #4]
|
|
80087a8: f001 fbaa bl 8009f00 <USBD_CtlSendData>
|
|
break;
|
|
80087ac: e030 b.n 8008810 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_GET_INTERFACE :
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80087ae: 687b ldr r3, [r7, #4]
|
|
80087b0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80087b4: b2db uxtb r3, r3
|
|
80087b6: 2b03 cmp r3, #3
|
|
80087b8: d107 bne.n 80087ca <USBD_HID_Setup+0x1a6>
|
|
{
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U);
|
|
80087ba: 68fb ldr r3, [r7, #12]
|
|
80087bc: 3308 adds r3, #8
|
|
80087be: 2201 movs r2, #1
|
|
80087c0: 4619 mov r1, r3
|
|
80087c2: 6878 ldr r0, [r7, #4]
|
|
80087c4: f001 fb9c bl 8009f00 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
80087c8: e022 b.n 8008810 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
80087ca: 6839 ldr r1, [r7, #0]
|
|
80087cc: 6878 ldr r0, [r7, #4]
|
|
80087ce: f001 fb1a bl 8009e06 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
80087d2: 2303 movs r3, #3
|
|
80087d4: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80087d6: e01b b.n 8008810 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_SET_INTERFACE:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80087d8: 687b ldr r3, [r7, #4]
|
|
80087da: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80087de: b2db uxtb r3, r3
|
|
80087e0: 2b03 cmp r3, #3
|
|
80087e2: d106 bne.n 80087f2 <USBD_HID_Setup+0x1ce>
|
|
{
|
|
hhid->AltSetting = (uint8_t)(req->wValue);
|
|
80087e4: 683b ldr r3, [r7, #0]
|
|
80087e6: 885b ldrh r3, [r3, #2]
|
|
80087e8: b2db uxtb r3, r3
|
|
80087ea: 461a mov r2, r3
|
|
80087ec: 68fb ldr r3, [r7, #12]
|
|
80087ee: 609a str r2, [r3, #8]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
80087f0: e00e b.n 8008810 <USBD_HID_Setup+0x1ec>
|
|
USBD_CtlError(pdev, req);
|
|
80087f2: 6839 ldr r1, [r7, #0]
|
|
80087f4: 6878 ldr r0, [r7, #4]
|
|
80087f6: f001 fb06 bl 8009e06 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
80087fa: 2303 movs r3, #3
|
|
80087fc: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80087fe: e007 b.n 8008810 <USBD_HID_Setup+0x1ec>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
break;
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008800: 6839 ldr r1, [r7, #0]
|
|
8008802: 6878 ldr r0, [r7, #4]
|
|
8008804: f001 faff bl 8009e06 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8008808: 2303 movs r3, #3
|
|
800880a: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800880c: e000 b.n 8008810 <USBD_HID_Setup+0x1ec>
|
|
break;
|
|
800880e: bf00 nop
|
|
}
|
|
break;
|
|
8008810: e006 b.n 8008820 <USBD_HID_Setup+0x1fc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8008812: 6839 ldr r1, [r7, #0]
|
|
8008814: 6878 ldr r0, [r7, #4]
|
|
8008816: f001 faf6 bl 8009e06 <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
800881a: 2303 movs r3, #3
|
|
800881c: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800881e: bf00 nop
|
|
}
|
|
|
|
return (uint8_t)ret;
|
|
8008820: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8008822: 4618 mov r0, r3
|
|
8008824: 3718 adds r7, #24
|
|
8008826: 46bd mov sp, r7
|
|
8008828: bd80 pop {r7, pc}
|
|
800882a: bf00 nop
|
|
800882c: 20000110 .word 0x20000110
|
|
8008830: 200000f8 .word 0x200000f8
|
|
|
|
08008834 <USBD_HID_SendReport>:
|
|
uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId)
|
|
{
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId];
|
|
#else
|
|
uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len)
|
|
{
|
|
8008834: b580 push {r7, lr}
|
|
8008836: b086 sub sp, #24
|
|
8008838: af00 add r7, sp, #0
|
|
800883a: 60f8 str r0, [r7, #12]
|
|
800883c: 60b9 str r1, [r7, #8]
|
|
800883e: 4613 mov r3, r2
|
|
8008840: 80fb strh r3, [r7, #6]
|
|
USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
8008842: 68fb ldr r3, [r7, #12]
|
|
8008844: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008848: 68fb ldr r3, [r7, #12]
|
|
800884a: 32b0 adds r2, #176 @ 0xb0
|
|
800884c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008850: 617b str r3, [r7, #20]
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (hhid == NULL)
|
|
8008852: 697b ldr r3, [r7, #20]
|
|
8008854: 2b00 cmp r3, #0
|
|
8008856: d101 bne.n 800885c <USBD_HID_SendReport+0x28>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
8008858: 2303 movs r3, #3
|
|
800885a: e014 b.n 8008886 <USBD_HID_SendReport+0x52>
|
|
#ifdef USE_USBD_COMPOSITE
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
800885c: 68fb ldr r3, [r7, #12]
|
|
800885e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008862: b2db uxtb r3, r3
|
|
8008864: 2b03 cmp r3, #3
|
|
8008866: d10d bne.n 8008884 <USBD_HID_SendReport+0x50>
|
|
{
|
|
if (hhid->state == USBD_HID_IDLE)
|
|
8008868: 697b ldr r3, [r7, #20]
|
|
800886a: 7b1b ldrb r3, [r3, #12]
|
|
800886c: 2b00 cmp r3, #0
|
|
800886e: d109 bne.n 8008884 <USBD_HID_SendReport+0x50>
|
|
{
|
|
hhid->state = USBD_HID_BUSY;
|
|
8008870: 697b ldr r3, [r7, #20]
|
|
8008872: 2201 movs r2, #1
|
|
8008874: 731a strb r2, [r3, #12]
|
|
(void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len);
|
|
8008876: 4b06 ldr r3, [pc, #24] @ (8008890 <USBD_HID_SendReport+0x5c>)
|
|
8008878: 7819 ldrb r1, [r3, #0]
|
|
800887a: 88fb ldrh r3, [r7, #6]
|
|
800887c: 68ba ldr r2, [r7, #8]
|
|
800887e: 68f8 ldr r0, [r7, #12]
|
|
8008880: f001 ff7d bl 800a77e <USBD_LL_Transmit>
|
|
}
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
8008884: 2300 movs r3, #0
|
|
}
|
|
8008886: 4618 mov r0, r3
|
|
8008888: 3718 adds r7, #24
|
|
800888a: 46bd mov sp, r7
|
|
800888c: bd80 pop {r7, pc}
|
|
800888e: bf00 nop
|
|
8008890: 2000013d .word 0x2000013d
|
|
|
|
08008894 <USBD_HID_GetFSCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length)
|
|
{
|
|
8008894: b580 push {r7, lr}
|
|
8008896: b084 sub sp, #16
|
|
8008898: af00 add r7, sp, #0
|
|
800889a: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
800889c: 2181 movs r1, #129 @ 0x81
|
|
800889e: 4809 ldr r0, [pc, #36] @ (80088c4 <USBD_HID_GetFSCfgDesc+0x30>)
|
|
80088a0: f000 fc4e bl 8009140 <USBD_GetEpDesc>
|
|
80088a4: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
80088a6: 68fb ldr r3, [r7, #12]
|
|
80088a8: 2b00 cmp r3, #0
|
|
80088aa: d002 beq.n 80088b2 <USBD_HID_GetFSCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_FS_BINTERVAL;
|
|
80088ac: 68fb ldr r3, [r7, #12]
|
|
80088ae: 220a movs r2, #10
|
|
80088b0: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
80088b2: 687b ldr r3, [r7, #4]
|
|
80088b4: 2222 movs r2, #34 @ 0x22
|
|
80088b6: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
80088b8: 4b02 ldr r3, [pc, #8] @ (80088c4 <USBD_HID_GetFSCfgDesc+0x30>)
|
|
}
|
|
80088ba: 4618 mov r0, r3
|
|
80088bc: 3710 adds r7, #16
|
|
80088be: 46bd mov sp, r7
|
|
80088c0: bd80 pop {r7, pc}
|
|
80088c2: bf00 nop
|
|
80088c4: 200000d4 .word 0x200000d4
|
|
|
|
080088c8 <USBD_HID_GetHSCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length)
|
|
{
|
|
80088c8: b580 push {r7, lr}
|
|
80088ca: b084 sub sp, #16
|
|
80088cc: af00 add r7, sp, #0
|
|
80088ce: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
80088d0: 2181 movs r1, #129 @ 0x81
|
|
80088d2: 4809 ldr r0, [pc, #36] @ (80088f8 <USBD_HID_GetHSCfgDesc+0x30>)
|
|
80088d4: f000 fc34 bl 8009140 <USBD_GetEpDesc>
|
|
80088d8: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
80088da: 68fb ldr r3, [r7, #12]
|
|
80088dc: 2b00 cmp r3, #0
|
|
80088de: d002 beq.n 80088e6 <USBD_HID_GetHSCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_HS_BINTERVAL;
|
|
80088e0: 68fb ldr r3, [r7, #12]
|
|
80088e2: 2207 movs r2, #7
|
|
80088e4: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
80088e6: 687b ldr r3, [r7, #4]
|
|
80088e8: 2222 movs r2, #34 @ 0x22
|
|
80088ea: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
80088ec: 4b02 ldr r3, [pc, #8] @ (80088f8 <USBD_HID_GetHSCfgDesc+0x30>)
|
|
}
|
|
80088ee: 4618 mov r0, r3
|
|
80088f0: 3710 adds r7, #16
|
|
80088f2: 46bd mov sp, r7
|
|
80088f4: bd80 pop {r7, pc}
|
|
80088f6: bf00 nop
|
|
80088f8: 200000d4 .word 0x200000d4
|
|
|
|
080088fc <USBD_HID_GetOtherSpeedCfgDesc>:
|
|
* @param speed : current device speed
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length)
|
|
{
|
|
80088fc: b580 push {r7, lr}
|
|
80088fe: b084 sub sp, #16
|
|
8008900: af00 add r7, sp, #0
|
|
8008902: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR);
|
|
8008904: 2181 movs r1, #129 @ 0x81
|
|
8008906: 4809 ldr r0, [pc, #36] @ (800892c <USBD_HID_GetOtherSpeedCfgDesc+0x30>)
|
|
8008908: f000 fc1a bl 8009140 <USBD_GetEpDesc>
|
|
800890c: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpDesc != NULL)
|
|
800890e: 68fb ldr r3, [r7, #12]
|
|
8008910: 2b00 cmp r3, #0
|
|
8008912: d002 beq.n 800891a <USBD_HID_GetOtherSpeedCfgDesc+0x1e>
|
|
{
|
|
pEpDesc->bInterval = HID_FS_BINTERVAL;
|
|
8008914: 68fb ldr r3, [r7, #12]
|
|
8008916: 220a movs r2, #10
|
|
8008918: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_HID_CfgDesc);
|
|
800891a: 687b ldr r3, [r7, #4]
|
|
800891c: 2222 movs r2, #34 @ 0x22
|
|
800891e: 801a strh r2, [r3, #0]
|
|
return USBD_HID_CfgDesc;
|
|
8008920: 4b02 ldr r3, [pc, #8] @ (800892c <USBD_HID_GetOtherSpeedCfgDesc+0x30>)
|
|
}
|
|
8008922: 4618 mov r0, r3
|
|
8008924: 3710 adds r7, #16
|
|
8008926: 46bd mov sp, r7
|
|
8008928: bd80 pop {r7, pc}
|
|
800892a: bf00 nop
|
|
800892c: 200000d4 .word 0x200000d4
|
|
|
|
08008930 <USBD_HID_DataIn>:
|
|
* @param pdev: device instance
|
|
* @param epnum: endpoint index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
|
|
{
|
|
8008930: b480 push {r7}
|
|
8008932: b083 sub sp, #12
|
|
8008934: af00 add r7, sp, #0
|
|
8008936: 6078 str r0, [r7, #4]
|
|
8008938: 460b mov r3, r1
|
|
800893a: 70fb strb r3, [r7, #3]
|
|
UNUSED(epnum);
|
|
/* Ensure that the FIFO is empty before a new transfer, this condition could
|
|
be caused by a new transfer before the end of the previous transfer */
|
|
((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE;
|
|
800893c: 687b ldr r3, [r7, #4]
|
|
800893e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008942: 687b ldr r3, [r7, #4]
|
|
8008944: 32b0 adds r2, #176 @ 0xb0
|
|
8008946: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800894a: 2200 movs r2, #0
|
|
800894c: 731a strb r2, [r3, #12]
|
|
|
|
return (uint8_t)USBD_OK;
|
|
800894e: 2300 movs r3, #0
|
|
}
|
|
8008950: 4618 mov r0, r3
|
|
8008952: 370c adds r7, #12
|
|
8008954: 46bd mov sp, r7
|
|
8008956: f85d 7b04 ldr.w r7, [sp], #4
|
|
800895a: 4770 bx lr
|
|
|
|
0800895c <USBD_HID_GetDeviceQualifierDesc>:
|
|
* return Device Qualifier descriptor
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length)
|
|
{
|
|
800895c: b480 push {r7}
|
|
800895e: b083 sub sp, #12
|
|
8008960: af00 add r7, sp, #0
|
|
8008962: 6078 str r0, [r7, #4]
|
|
*length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc);
|
|
8008964: 687b ldr r3, [r7, #4]
|
|
8008966: 220a movs r2, #10
|
|
8008968: 801a strh r2, [r3, #0]
|
|
|
|
return USBD_HID_DeviceQualifierDesc;
|
|
800896a: 4b03 ldr r3, [pc, #12] @ (8008978 <USBD_HID_GetDeviceQualifierDesc+0x1c>)
|
|
}
|
|
800896c: 4618 mov r0, r3
|
|
800896e: 370c adds r7, #12
|
|
8008970: 46bd mov sp, r7
|
|
8008972: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008976: 4770 bx lr
|
|
8008978: 20000104 .word 0x20000104
|
|
|
|
0800897c <USBD_Init>:
|
|
* @param id: Low level core index
|
|
* @retval status: USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
|
|
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
|
|
{
|
|
800897c: b580 push {r7, lr}
|
|
800897e: b086 sub sp, #24
|
|
8008980: af00 add r7, sp, #0
|
|
8008982: 60f8 str r0, [r7, #12]
|
|
8008984: 60b9 str r1, [r7, #8]
|
|
8008986: 4613 mov r3, r2
|
|
8008988: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef ret;
|
|
|
|
/* Check whether the USB Host handle is valid */
|
|
if (pdev == NULL)
|
|
800898a: 68fb ldr r3, [r7, #12]
|
|
800898c: 2b00 cmp r3, #0
|
|
800898e: d101 bne.n 8008994 <USBD_Init+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Device handle");
|
|
#endif /* (USBD_DEBUG_LEVEL > 1U) */
|
|
return USBD_FAIL;
|
|
8008990: 2303 movs r3, #3
|
|
8008992: e01f b.n 80089d4 <USBD_Init+0x58>
|
|
pdev->NumClasses = 0;
|
|
pdev->classId = 0;
|
|
}
|
|
#else
|
|
/* Unlink previous class*/
|
|
pdev->pClass[0] = NULL;
|
|
8008994: 68fb ldr r3, [r7, #12]
|
|
8008996: 2200 movs r2, #0
|
|
8008998: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
pdev->pUserData[0] = NULL;
|
|
800899c: 68fb ldr r3, [r7, #12]
|
|
800899e: 2200 movs r2, #0
|
|
80089a0: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
pdev->pConfDesc = NULL;
|
|
80089a4: 68fb ldr r3, [r7, #12]
|
|
80089a6: 2200 movs r2, #0
|
|
80089a8: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
|
|
/* Assign USBD Descriptors */
|
|
if (pdesc != NULL)
|
|
80089ac: 68bb ldr r3, [r7, #8]
|
|
80089ae: 2b00 cmp r3, #0
|
|
80089b0: d003 beq.n 80089ba <USBD_Init+0x3e>
|
|
{
|
|
pdev->pDesc = pdesc;
|
|
80089b2: 68fb ldr r3, [r7, #12]
|
|
80089b4: 68ba ldr r2, [r7, #8]
|
|
80089b6: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
|
|
}
|
|
|
|
/* Set Device initial State */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
80089ba: 68fb ldr r3, [r7, #12]
|
|
80089bc: 2201 movs r2, #1
|
|
80089be: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->id = id;
|
|
80089c2: 68fb ldr r3, [r7, #12]
|
|
80089c4: 79fa ldrb r2, [r7, #7]
|
|
80089c6: 701a strb r2, [r3, #0]
|
|
|
|
/* Initialize low level driver */
|
|
ret = USBD_LL_Init(pdev);
|
|
80089c8: 68f8 ldr r0, [r7, #12]
|
|
80089ca: f001 fda3 bl 800a514 <USBD_LL_Init>
|
|
80089ce: 4603 mov r3, r0
|
|
80089d0: 75fb strb r3, [r7, #23]
|
|
|
|
return ret;
|
|
80089d2: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80089d4: 4618 mov r0, r3
|
|
80089d6: 3718 adds r7, #24
|
|
80089d8: 46bd mov sp, r7
|
|
80089da: bd80 pop {r7, pc}
|
|
|
|
080089dc <USBD_RegisterClass>:
|
|
* @param pdev: Device Handle
|
|
* @param pclass: Class handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
|
|
{
|
|
80089dc: b580 push {r7, lr}
|
|
80089de: b084 sub sp, #16
|
|
80089e0: af00 add r7, sp, #0
|
|
80089e2: 6078 str r0, [r7, #4]
|
|
80089e4: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
80089e6: 2300 movs r3, #0
|
|
80089e8: 81fb strh r3, [r7, #14]
|
|
|
|
if (pclass == NULL)
|
|
80089ea: 683b ldr r3, [r7, #0]
|
|
80089ec: 2b00 cmp r3, #0
|
|
80089ee: d101 bne.n 80089f4 <USBD_RegisterClass+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Class handle");
|
|
#endif /* (USBD_DEBUG_LEVEL > 1U) */
|
|
return USBD_FAIL;
|
|
80089f0: 2303 movs r3, #3
|
|
80089f2: e025 b.n 8008a40 <USBD_RegisterClass+0x64>
|
|
}
|
|
|
|
/* link the class to the USB Device handle */
|
|
pdev->pClass[0] = pclass;
|
|
80089f4: 687b ldr r3, [r7, #4]
|
|
80089f6: 683a ldr r2, [r7, #0]
|
|
80089f8: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL)
|
|
{
|
|
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len);
|
|
}
|
|
#else /* Default USE_USB_FS */
|
|
if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL)
|
|
80089fc: 687b ldr r3, [r7, #4]
|
|
80089fe: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008a02: 687b ldr r3, [r7, #4]
|
|
8008a04: 32ae adds r2, #174 @ 0xae
|
|
8008a06: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008a0a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8008a0c: 2b00 cmp r3, #0
|
|
8008a0e: d00f beq.n 8008a30 <USBD_RegisterClass+0x54>
|
|
{
|
|
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len);
|
|
8008a10: 687b ldr r3, [r7, #4]
|
|
8008a12: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008a16: 687b ldr r3, [r7, #4]
|
|
8008a18: 32ae adds r2, #174 @ 0xae
|
|
8008a1a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008a1e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8008a20: f107 020e add.w r2, r7, #14
|
|
8008a24: 4610 mov r0, r2
|
|
8008a26: 4798 blx r3
|
|
8008a28: 4602 mov r2, r0
|
|
8008a2a: 687b ldr r3, [r7, #4]
|
|
8008a2c: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
}
|
|
#endif /* USE_USB_FS */
|
|
|
|
/* Increment the NumClasses */
|
|
pdev->NumClasses++;
|
|
8008a30: 687b ldr r3, [r7, #4]
|
|
8008a32: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
8008a36: 1c5a adds r2, r3, #1
|
|
8008a38: 687b ldr r3, [r7, #4]
|
|
8008a3a: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8
|
|
|
|
return USBD_OK;
|
|
8008a3e: 2300 movs r3, #0
|
|
}
|
|
8008a40: 4618 mov r0, r3
|
|
8008a42: 3710 adds r7, #16
|
|
8008a44: 46bd mov sp, r7
|
|
8008a46: bd80 pop {r7, pc}
|
|
|
|
08008a48 <USBD_Start>:
|
|
* Start the USB Device Core.
|
|
* @param pdev: Device Handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008a48: b580 push {r7, lr}
|
|
8008a4a: b082 sub sp, #8
|
|
8008a4c: af00 add r7, sp, #0
|
|
8008a4e: 6078 str r0, [r7, #4]
|
|
#ifdef USE_USBD_COMPOSITE
|
|
pdev->classId = 0U;
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Start the low level driver */
|
|
return USBD_LL_Start(pdev);
|
|
8008a50: 6878 ldr r0, [r7, #4]
|
|
8008a52: f001 fdab bl 800a5ac <USBD_LL_Start>
|
|
8008a56: 4603 mov r3, r0
|
|
}
|
|
8008a58: 4618 mov r0, r3
|
|
8008a5a: 3708 adds r7, #8
|
|
8008a5c: 46bd mov sp, r7
|
|
8008a5e: bd80 pop {r7, pc}
|
|
|
|
08008a60 <USBD_RunTestMode>:
|
|
* Launch test mode process
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008a60: b480 push {r7}
|
|
8008a62: b083 sub sp, #12
|
|
8008a64: af00 add r7, sp, #0
|
|
8008a66: 6078 str r0, [r7, #4]
|
|
return ret;
|
|
#else
|
|
/* Prevent unused argument compilation warning */
|
|
UNUSED(pdev);
|
|
|
|
return USBD_OK;
|
|
8008a68: 2300 movs r3, #0
|
|
#endif /* USBD_HS_TESTMODE_ENABLE */
|
|
}
|
|
8008a6a: 4618 mov r0, r3
|
|
8008a6c: 370c adds r7, #12
|
|
8008a6e: 46bd mov sp, r7
|
|
8008a70: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008a74: 4770 bx lr
|
|
|
|
08008a76 <USBD_SetClassConfig>:
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
|
|
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8008a76: b580 push {r7, lr}
|
|
8008a78: b084 sub sp, #16
|
|
8008a7a: af00 add r7, sp, #0
|
|
8008a7c: 6078 str r0, [r7, #4]
|
|
8008a7e: 460b mov r3, r1
|
|
8008a80: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8008a82: 2300 movs r3, #0
|
|
8008a84: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
8008a86: 687b ldr r3, [r7, #4]
|
|
8008a88: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008a8c: 2b00 cmp r3, #0
|
|
8008a8e: d009 beq.n 8008aa4 <USBD_SetClassConfig+0x2e>
|
|
{
|
|
/* Set configuration and Start the Class */
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx);
|
|
8008a90: 687b ldr r3, [r7, #4]
|
|
8008a92: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008a96: 681b ldr r3, [r3, #0]
|
|
8008a98: 78fa ldrb r2, [r7, #3]
|
|
8008a9a: 4611 mov r1, r2
|
|
8008a9c: 6878 ldr r0, [r7, #4]
|
|
8008a9e: 4798 blx r3
|
|
8008aa0: 4603 mov r3, r0
|
|
8008aa2: 73fb strb r3, [r7, #15]
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8008aa4: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008aa6: 4618 mov r0, r3
|
|
8008aa8: 3710 adds r7, #16
|
|
8008aaa: 46bd mov sp, r7
|
|
8008aac: bd80 pop {r7, pc}
|
|
|
|
08008aae <USBD_ClrClassConfig>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8008aae: b580 push {r7, lr}
|
|
8008ab0: b084 sub sp, #16
|
|
8008ab2: af00 add r7, sp, #0
|
|
8008ab4: 6078 str r0, [r7, #4]
|
|
8008ab6: 460b mov r3, r1
|
|
8008ab8: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8008aba: 2300 movs r3, #0
|
|
8008abc: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
/* Clear configuration and De-initialize the Class process */
|
|
if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U)
|
|
8008abe: 687b ldr r3, [r7, #4]
|
|
8008ac0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008ac4: 685b ldr r3, [r3, #4]
|
|
8008ac6: 78fa ldrb r2, [r7, #3]
|
|
8008ac8: 4611 mov r1, r2
|
|
8008aca: 6878 ldr r0, [r7, #4]
|
|
8008acc: 4798 blx r3
|
|
8008ace: 4603 mov r3, r0
|
|
8008ad0: 2b00 cmp r3, #0
|
|
8008ad2: d001 beq.n 8008ad8 <USBD_ClrClassConfig+0x2a>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8008ad4: 2303 movs r3, #3
|
|
8008ad6: 73fb strb r3, [r7, #15]
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8008ad8: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008ada: 4618 mov r0, r3
|
|
8008adc: 3710 adds r7, #16
|
|
8008ade: 46bd mov sp, r7
|
|
8008ae0: bd80 pop {r7, pc}
|
|
|
|
08008ae2 <USBD_LL_SetupStage>:
|
|
* @param pdev: device instance
|
|
* @param psetup: setup packet buffer pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
|
|
{
|
|
8008ae2: b580 push {r7, lr}
|
|
8008ae4: b084 sub sp, #16
|
|
8008ae6: af00 add r7, sp, #0
|
|
8008ae8: 6078 str r0, [r7, #4]
|
|
8008aea: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret;
|
|
|
|
USBD_ParseSetupRequest(&pdev->request, psetup);
|
|
8008aec: 687b ldr r3, [r7, #4]
|
|
8008aee: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8008af2: 6839 ldr r1, [r7, #0]
|
|
8008af4: 4618 mov r0, r3
|
|
8008af6: f001 f94c bl 8009d92 <USBD_ParseSetupRequest>
|
|
|
|
pdev->ep0_state = USBD_EP0_SETUP;
|
|
8008afa: 687b ldr r3, [r7, #4]
|
|
8008afc: 2201 movs r2, #1
|
|
8008afe: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
pdev->ep0_data_len = pdev->request.wLength;
|
|
8008b02: 687b ldr r3, [r7, #4]
|
|
8008b04: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0
|
|
8008b08: 461a mov r2, r3
|
|
8008b0a: 687b ldr r3, [r7, #4]
|
|
8008b0c: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
8008b10: 687b ldr r3, [r7, #4]
|
|
8008b12: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8008b16: f003 031f and.w r3, r3, #31
|
|
8008b1a: 2b02 cmp r3, #2
|
|
8008b1c: d01a beq.n 8008b54 <USBD_LL_SetupStage+0x72>
|
|
8008b1e: 2b02 cmp r3, #2
|
|
8008b20: d822 bhi.n 8008b68 <USBD_LL_SetupStage+0x86>
|
|
8008b22: 2b00 cmp r3, #0
|
|
8008b24: d002 beq.n 8008b2c <USBD_LL_SetupStage+0x4a>
|
|
8008b26: 2b01 cmp r3, #1
|
|
8008b28: d00a beq.n 8008b40 <USBD_LL_SetupStage+0x5e>
|
|
8008b2a: e01d b.n 8008b68 <USBD_LL_SetupStage+0x86>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
ret = USBD_StdDevReq(pdev, &pdev->request);
|
|
8008b2c: 687b ldr r3, [r7, #4]
|
|
8008b2e: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8008b32: 4619 mov r1, r3
|
|
8008b34: 6878 ldr r0, [r7, #4]
|
|
8008b36: f000 fb77 bl 8009228 <USBD_StdDevReq>
|
|
8008b3a: 4603 mov r3, r0
|
|
8008b3c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8008b3e: e020 b.n 8008b82 <USBD_LL_SetupStage+0xa0>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
ret = USBD_StdItfReq(pdev, &pdev->request);
|
|
8008b40: 687b ldr r3, [r7, #4]
|
|
8008b42: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8008b46: 4619 mov r1, r3
|
|
8008b48: 6878 ldr r0, [r7, #4]
|
|
8008b4a: f000 fbdf bl 800930c <USBD_StdItfReq>
|
|
8008b4e: 4603 mov r3, r0
|
|
8008b50: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8008b52: e016 b.n 8008b82 <USBD_LL_SetupStage+0xa0>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
ret = USBD_StdEPReq(pdev, &pdev->request);
|
|
8008b54: 687b ldr r3, [r7, #4]
|
|
8008b56: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8008b5a: 4619 mov r1, r3
|
|
8008b5c: 6878 ldr r0, [r7, #4]
|
|
8008b5e: f000 fc41 bl 80093e4 <USBD_StdEPReq>
|
|
8008b62: 4603 mov r3, r0
|
|
8008b64: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8008b66: e00c b.n 8008b82 <USBD_LL_SetupStage+0xa0>
|
|
|
|
default:
|
|
ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
|
|
8008b68: 687b ldr r3, [r7, #4]
|
|
8008b6a: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8008b6e: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
8008b72: b2db uxtb r3, r3
|
|
8008b74: 4619 mov r1, r3
|
|
8008b76: 6878 ldr r0, [r7, #4]
|
|
8008b78: f001 fd78 bl 800a66c <USBD_LL_StallEP>
|
|
8008b7c: 4603 mov r3, r0
|
|
8008b7e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8008b80: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8008b82: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008b84: 4618 mov r0, r3
|
|
8008b86: 3710 adds r7, #16
|
|
8008b88: 46bd mov sp, r7
|
|
8008b8a: bd80 pop {r7, pc}
|
|
|
|
08008b8c <USBD_LL_DataOutStage>:
|
|
* @param pdata: data pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
8008b8c: b580 push {r7, lr}
|
|
8008b8e: b086 sub sp, #24
|
|
8008b90: af00 add r7, sp, #0
|
|
8008b92: 60f8 str r0, [r7, #12]
|
|
8008b94: 460b mov r3, r1
|
|
8008b96: 607a str r2, [r7, #4]
|
|
8008b98: 72fb strb r3, [r7, #11]
|
|
USBD_EndpointTypeDef *pep;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8008b9a: 2300 movs r3, #0
|
|
8008b9c: 75fb strb r3, [r7, #23]
|
|
uint8_t idx;
|
|
|
|
UNUSED(pdata);
|
|
|
|
if (epnum == 0U)
|
|
8008b9e: 7afb ldrb r3, [r7, #11]
|
|
8008ba0: 2b00 cmp r3, #0
|
|
8008ba2: d177 bne.n 8008c94 <USBD_LL_DataOutStage+0x108>
|
|
{
|
|
pep = &pdev->ep_out[0];
|
|
8008ba4: 68fb ldr r3, [r7, #12]
|
|
8008ba6: f503 73aa add.w r3, r3, #340 @ 0x154
|
|
8008baa: 613b str r3, [r7, #16]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
|
|
8008bac: 68fb ldr r3, [r7, #12]
|
|
8008bae: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
8008bb2: 2b03 cmp r3, #3
|
|
8008bb4: f040 80a1 bne.w 8008cfa <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
8008bb8: 693b ldr r3, [r7, #16]
|
|
8008bba: 685b ldr r3, [r3, #4]
|
|
8008bbc: 693a ldr r2, [r7, #16]
|
|
8008bbe: 8992 ldrh r2, [r2, #12]
|
|
8008bc0: 4293 cmp r3, r2
|
|
8008bc2: d91c bls.n 8008bfe <USBD_LL_DataOutStage+0x72>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
8008bc4: 693b ldr r3, [r7, #16]
|
|
8008bc6: 685b ldr r3, [r3, #4]
|
|
8008bc8: 693a ldr r2, [r7, #16]
|
|
8008bca: 8992 ldrh r2, [r2, #12]
|
|
8008bcc: 1a9a subs r2, r3, r2
|
|
8008bce: 693b ldr r3, [r7, #16]
|
|
8008bd0: 605a str r2, [r3, #4]
|
|
pep->pbuffer += pep->maxpacket;
|
|
8008bd2: 693b ldr r3, [r7, #16]
|
|
8008bd4: 691b ldr r3, [r3, #16]
|
|
8008bd6: 693a ldr r2, [r7, #16]
|
|
8008bd8: 8992 ldrh r2, [r2, #12]
|
|
8008bda: 441a add r2, r3
|
|
8008bdc: 693b ldr r3, [r7, #16]
|
|
8008bde: 611a str r2, [r3, #16]
|
|
|
|
(void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket));
|
|
8008be0: 693b ldr r3, [r7, #16]
|
|
8008be2: 6919 ldr r1, [r3, #16]
|
|
8008be4: 693b ldr r3, [r7, #16]
|
|
8008be6: 899b ldrh r3, [r3, #12]
|
|
8008be8: 461a mov r2, r3
|
|
8008bea: 693b ldr r3, [r7, #16]
|
|
8008bec: 685b ldr r3, [r3, #4]
|
|
8008bee: 4293 cmp r3, r2
|
|
8008bf0: bf38 it cc
|
|
8008bf2: 4613 movcc r3, r2
|
|
8008bf4: 461a mov r2, r3
|
|
8008bf6: 68f8 ldr r0, [r7, #12]
|
|
8008bf8: f001 f9b1 bl 8009f5e <USBD_CtlContinueRx>
|
|
8008bfc: e07d b.n 8008cfa <USBD_LL_DataOutStage+0x16e>
|
|
}
|
|
else
|
|
{
|
|
/* Find the class ID relative to the current request */
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
8008bfe: 68fb ldr r3, [r7, #12]
|
|
8008c00: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8008c04: f003 031f and.w r3, r3, #31
|
|
8008c08: 2b02 cmp r3, #2
|
|
8008c0a: d014 beq.n 8008c36 <USBD_LL_DataOutStage+0xaa>
|
|
8008c0c: 2b02 cmp r3, #2
|
|
8008c0e: d81d bhi.n 8008c4c <USBD_LL_DataOutStage+0xc0>
|
|
8008c10: 2b00 cmp r3, #0
|
|
8008c12: d002 beq.n 8008c1a <USBD_LL_DataOutStage+0x8e>
|
|
8008c14: 2b01 cmp r3, #1
|
|
8008c16: d003 beq.n 8008c20 <USBD_LL_DataOutStage+0x94>
|
|
8008c18: e018 b.n 8008c4c <USBD_LL_DataOutStage+0xc0>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
/* Device requests must be managed by the first instantiated class
|
|
(or duplicated by all classes for simplicity) */
|
|
idx = 0U;
|
|
8008c1a: 2300 movs r3, #0
|
|
8008c1c: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8008c1e: e018 b.n 8008c52 <USBD_LL_DataOutStage+0xc6>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex));
|
|
8008c20: 68fb ldr r3, [r7, #12]
|
|
8008c22: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
8008c26: b2db uxtb r3, r3
|
|
8008c28: 4619 mov r1, r3
|
|
8008c2a: 68f8 ldr r0, [r7, #12]
|
|
8008c2c: f000 fa6e bl 800910c <USBD_CoreFindIF>
|
|
8008c30: 4603 mov r3, r0
|
|
8008c32: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8008c34: e00d b.n 8008c52 <USBD_LL_DataOutStage+0xc6>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex));
|
|
8008c36: 68fb ldr r3, [r7, #12]
|
|
8008c38: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
8008c3c: b2db uxtb r3, r3
|
|
8008c3e: 4619 mov r1, r3
|
|
8008c40: 68f8 ldr r0, [r7, #12]
|
|
8008c42: f000 fa70 bl 8009126 <USBD_CoreFindEP>
|
|
8008c46: 4603 mov r3, r0
|
|
8008c48: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8008c4a: e002 b.n 8008c52 <USBD_LL_DataOutStage+0xc6>
|
|
|
|
default:
|
|
/* Back to the first class in case of doubt */
|
|
idx = 0U;
|
|
8008c4c: 2300 movs r3, #0
|
|
8008c4e: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8008c50: bf00 nop
|
|
}
|
|
|
|
if (idx < USBD_MAX_SUPPORTED_CLASS)
|
|
8008c52: 7dbb ldrb r3, [r7, #22]
|
|
8008c54: 2b00 cmp r3, #0
|
|
8008c56: d119 bne.n 8008c8c <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
/* Setup the class ID and route the request to the relative class function */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008c58: 68fb ldr r3, [r7, #12]
|
|
8008c5a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008c5e: b2db uxtb r3, r3
|
|
8008c60: 2b03 cmp r3, #3
|
|
8008c62: d113 bne.n 8008c8c <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
if (pdev->pClass[idx]->EP0_RxReady != NULL)
|
|
8008c64: 7dba ldrb r2, [r7, #22]
|
|
8008c66: 68fb ldr r3, [r7, #12]
|
|
8008c68: 32ae adds r2, #174 @ 0xae
|
|
8008c6a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008c6e: 691b ldr r3, [r3, #16]
|
|
8008c70: 2b00 cmp r3, #0
|
|
8008c72: d00b beq.n 8008c8c <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
pdev->classId = idx;
|
|
8008c74: 7dba ldrb r2, [r7, #22]
|
|
8008c76: 68fb ldr r3, [r7, #12]
|
|
8008c78: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
pdev->pClass[idx]->EP0_RxReady(pdev);
|
|
8008c7c: 7dba ldrb r2, [r7, #22]
|
|
8008c7e: 68fb ldr r3, [r7, #12]
|
|
8008c80: 32ae adds r2, #174 @ 0xae
|
|
8008c82: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008c86: 691b ldr r3, [r3, #16]
|
|
8008c88: 68f8 ldr r0, [r7, #12]
|
|
8008c8a: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8008c8c: 68f8 ldr r0, [r7, #12]
|
|
8008c8e: f001 f977 bl 8009f80 <USBD_CtlSendStatus>
|
|
8008c92: e032 b.n 8008cfa <USBD_LL_DataOutStage+0x16e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU));
|
|
8008c94: 7afb ldrb r3, [r7, #11]
|
|
8008c96: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8008c9a: b2db uxtb r3, r3
|
|
8008c9c: 4619 mov r1, r3
|
|
8008c9e: 68f8 ldr r0, [r7, #12]
|
|
8008ca0: f000 fa41 bl 8009126 <USBD_CoreFindEP>
|
|
8008ca4: 4603 mov r3, r0
|
|
8008ca6: 75bb strb r3, [r7, #22]
|
|
|
|
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8008ca8: 7dbb ldrb r3, [r7, #22]
|
|
8008caa: 2bff cmp r3, #255 @ 0xff
|
|
8008cac: d025 beq.n 8008cfa <USBD_LL_DataOutStage+0x16e>
|
|
8008cae: 7dbb ldrb r3, [r7, #22]
|
|
8008cb0: 2b00 cmp r3, #0
|
|
8008cb2: d122 bne.n 8008cfa <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008cb4: 68fb ldr r3, [r7, #12]
|
|
8008cb6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008cba: b2db uxtb r3, r3
|
|
8008cbc: 2b03 cmp r3, #3
|
|
8008cbe: d117 bne.n 8008cf0 <USBD_LL_DataOutStage+0x164>
|
|
{
|
|
if (pdev->pClass[idx]->DataOut != NULL)
|
|
8008cc0: 7dba ldrb r2, [r7, #22]
|
|
8008cc2: 68fb ldr r3, [r7, #12]
|
|
8008cc4: 32ae adds r2, #174 @ 0xae
|
|
8008cc6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008cca: 699b ldr r3, [r3, #24]
|
|
8008ccc: 2b00 cmp r3, #0
|
|
8008cce: d00f beq.n 8008cf0 <USBD_LL_DataOutStage+0x164>
|
|
{
|
|
pdev->classId = idx;
|
|
8008cd0: 7dba ldrb r2, [r7, #22]
|
|
8008cd2: 68fb ldr r3, [r7, #12]
|
|
8008cd4: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum);
|
|
8008cd8: 7dba ldrb r2, [r7, #22]
|
|
8008cda: 68fb ldr r3, [r7, #12]
|
|
8008cdc: 32ae adds r2, #174 @ 0xae
|
|
8008cde: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008ce2: 699b ldr r3, [r3, #24]
|
|
8008ce4: 7afa ldrb r2, [r7, #11]
|
|
8008ce6: 4611 mov r1, r2
|
|
8008ce8: 68f8 ldr r0, [r7, #12]
|
|
8008cea: 4798 blx r3
|
|
8008cec: 4603 mov r3, r0
|
|
8008cee: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
if (ret != USBD_OK)
|
|
8008cf0: 7dfb ldrb r3, [r7, #23]
|
|
8008cf2: 2b00 cmp r3, #0
|
|
8008cf4: d001 beq.n 8008cfa <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
return ret;
|
|
8008cf6: 7dfb ldrb r3, [r7, #23]
|
|
8008cf8: e000 b.n 8008cfc <USBD_LL_DataOutStage+0x170>
|
|
}
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8008cfa: 2300 movs r3, #0
|
|
}
|
|
8008cfc: 4618 mov r0, r3
|
|
8008cfe: 3718 adds r7, #24
|
|
8008d00: 46bd mov sp, r7
|
|
8008d02: bd80 pop {r7, pc}
|
|
|
|
08008d04 <USBD_LL_DataInStage>:
|
|
* @param pdata: data pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
8008d04: b580 push {r7, lr}
|
|
8008d06: b086 sub sp, #24
|
|
8008d08: af00 add r7, sp, #0
|
|
8008d0a: 60f8 str r0, [r7, #12]
|
|
8008d0c: 460b mov r3, r1
|
|
8008d0e: 607a str r2, [r7, #4]
|
|
8008d10: 72fb strb r3, [r7, #11]
|
|
USBD_StatusTypeDef ret;
|
|
uint8_t idx;
|
|
|
|
UNUSED(pdata);
|
|
|
|
if (epnum == 0U)
|
|
8008d12: 7afb ldrb r3, [r7, #11]
|
|
8008d14: 2b00 cmp r3, #0
|
|
8008d16: d178 bne.n 8008e0a <USBD_LL_DataInStage+0x106>
|
|
{
|
|
pep = &pdev->ep_in[0];
|
|
8008d18: 68fb ldr r3, [r7, #12]
|
|
8008d1a: 3314 adds r3, #20
|
|
8008d1c: 613b str r3, [r7, #16]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_IN)
|
|
8008d1e: 68fb ldr r3, [r7, #12]
|
|
8008d20: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
8008d24: 2b02 cmp r3, #2
|
|
8008d26: d163 bne.n 8008df0 <USBD_LL_DataInStage+0xec>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
8008d28: 693b ldr r3, [r7, #16]
|
|
8008d2a: 685b ldr r3, [r3, #4]
|
|
8008d2c: 693a ldr r2, [r7, #16]
|
|
8008d2e: 8992 ldrh r2, [r2, #12]
|
|
8008d30: 4293 cmp r3, r2
|
|
8008d32: d91c bls.n 8008d6e <USBD_LL_DataInStage+0x6a>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
8008d34: 693b ldr r3, [r7, #16]
|
|
8008d36: 685b ldr r3, [r3, #4]
|
|
8008d38: 693a ldr r2, [r7, #16]
|
|
8008d3a: 8992 ldrh r2, [r2, #12]
|
|
8008d3c: 1a9a subs r2, r3, r2
|
|
8008d3e: 693b ldr r3, [r7, #16]
|
|
8008d40: 605a str r2, [r3, #4]
|
|
pep->pbuffer += pep->maxpacket;
|
|
8008d42: 693b ldr r3, [r7, #16]
|
|
8008d44: 691b ldr r3, [r3, #16]
|
|
8008d46: 693a ldr r2, [r7, #16]
|
|
8008d48: 8992 ldrh r2, [r2, #12]
|
|
8008d4a: 441a add r2, r3
|
|
8008d4c: 693b ldr r3, [r7, #16]
|
|
8008d4e: 611a str r2, [r3, #16]
|
|
|
|
(void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length);
|
|
8008d50: 693b ldr r3, [r7, #16]
|
|
8008d52: 6919 ldr r1, [r3, #16]
|
|
8008d54: 693b ldr r3, [r7, #16]
|
|
8008d56: 685b ldr r3, [r3, #4]
|
|
8008d58: 461a mov r2, r3
|
|
8008d5a: 68f8 ldr r0, [r7, #12]
|
|
8008d5c: f001 f8ee bl 8009f3c <USBD_CtlContinueSendData>
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8008d60: 2300 movs r3, #0
|
|
8008d62: 2200 movs r2, #0
|
|
8008d64: 2100 movs r1, #0
|
|
8008d66: 68f8 ldr r0, [r7, #12]
|
|
8008d68: f001 fd2a bl 800a7c0 <USBD_LL_PrepareReceive>
|
|
8008d6c: e040 b.n 8008df0 <USBD_LL_DataInStage+0xec>
|
|
}
|
|
else
|
|
{
|
|
/* last packet is MPS multiple, so send ZLP packet */
|
|
if ((pep->maxpacket == pep->rem_length) &&
|
|
8008d6e: 693b ldr r3, [r7, #16]
|
|
8008d70: 899b ldrh r3, [r3, #12]
|
|
8008d72: 461a mov r2, r3
|
|
8008d74: 693b ldr r3, [r7, #16]
|
|
8008d76: 685b ldr r3, [r3, #4]
|
|
8008d78: 429a cmp r2, r3
|
|
8008d7a: d11c bne.n 8008db6 <USBD_LL_DataInStage+0xb2>
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
8008d7c: 693b ldr r3, [r7, #16]
|
|
8008d7e: 681b ldr r3, [r3, #0]
|
|
8008d80: 693a ldr r2, [r7, #16]
|
|
8008d82: 8992 ldrh r2, [r2, #12]
|
|
if ((pep->maxpacket == pep->rem_length) &&
|
|
8008d84: 4293 cmp r3, r2
|
|
8008d86: d316 bcc.n 8008db6 <USBD_LL_DataInStage+0xb2>
|
|
(pep->total_length < pdev->ep0_data_len))
|
|
8008d88: 693b ldr r3, [r7, #16]
|
|
8008d8a: 681a ldr r2, [r3, #0]
|
|
8008d8c: 68fb ldr r3, [r7, #12]
|
|
8008d8e: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
8008d92: 429a cmp r2, r3
|
|
8008d94: d20f bcs.n 8008db6 <USBD_LL_DataInStage+0xb2>
|
|
{
|
|
(void)USBD_CtlContinueSendData(pdev, NULL, 0U);
|
|
8008d96: 2200 movs r2, #0
|
|
8008d98: 2100 movs r1, #0
|
|
8008d9a: 68f8 ldr r0, [r7, #12]
|
|
8008d9c: f001 f8ce bl 8009f3c <USBD_CtlContinueSendData>
|
|
pdev->ep0_data_len = 0U;
|
|
8008da0: 68fb ldr r3, [r7, #12]
|
|
8008da2: 2200 movs r2, #0
|
|
8008da4: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8008da8: 2300 movs r3, #0
|
|
8008daa: 2200 movs r2, #0
|
|
8008dac: 2100 movs r1, #0
|
|
8008dae: 68f8 ldr r0, [r7, #12]
|
|
8008db0: f001 fd06 bl 800a7c0 <USBD_LL_PrepareReceive>
|
|
8008db4: e01c b.n 8008df0 <USBD_LL_DataInStage+0xec>
|
|
}
|
|
else
|
|
{
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008db6: 68fb ldr r3, [r7, #12]
|
|
8008db8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008dbc: b2db uxtb r3, r3
|
|
8008dbe: 2b03 cmp r3, #3
|
|
8008dc0: d10f bne.n 8008de2 <USBD_LL_DataInStage+0xde>
|
|
{
|
|
if (pdev->pClass[0]->EP0_TxSent != NULL)
|
|
8008dc2: 68fb ldr r3, [r7, #12]
|
|
8008dc4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008dc8: 68db ldr r3, [r3, #12]
|
|
8008dca: 2b00 cmp r3, #0
|
|
8008dcc: d009 beq.n 8008de2 <USBD_LL_DataInStage+0xde>
|
|
{
|
|
pdev->classId = 0U;
|
|
8008dce: 68fb ldr r3, [r7, #12]
|
|
8008dd0: 2200 movs r2, #0
|
|
8008dd2: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
pdev->pClass[0]->EP0_TxSent(pdev);
|
|
8008dd6: 68fb ldr r3, [r7, #12]
|
|
8008dd8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008ddc: 68db ldr r3, [r3, #12]
|
|
8008dde: 68f8 ldr r0, [r7, #12]
|
|
8008de0: 4798 blx r3
|
|
}
|
|
}
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8008de2: 2180 movs r1, #128 @ 0x80
|
|
8008de4: 68f8 ldr r0, [r7, #12]
|
|
8008de6: f001 fc41 bl 800a66c <USBD_LL_StallEP>
|
|
(void)USBD_CtlReceiveStatus(pdev);
|
|
8008dea: 68f8 ldr r0, [r7, #12]
|
|
8008dec: f001 f8db bl 8009fa6 <USBD_CtlReceiveStatus>
|
|
}
|
|
}
|
|
}
|
|
|
|
if (pdev->dev_test_mode != 0U)
|
|
8008df0: 68fb ldr r3, [r7, #12]
|
|
8008df2: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
|
|
8008df6: 2b00 cmp r3, #0
|
|
8008df8: d03a beq.n 8008e70 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
(void)USBD_RunTestMode(pdev);
|
|
8008dfa: 68f8 ldr r0, [r7, #12]
|
|
8008dfc: f7ff fe30 bl 8008a60 <USBD_RunTestMode>
|
|
pdev->dev_test_mode = 0U;
|
|
8008e00: 68fb ldr r3, [r7, #12]
|
|
8008e02: 2200 movs r2, #0
|
|
8008e04: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
8008e08: e032 b.n 8008e70 <USBD_LL_DataInStage+0x16c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U));
|
|
8008e0a: 7afb ldrb r3, [r7, #11]
|
|
8008e0c: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8008e10: b2db uxtb r3, r3
|
|
8008e12: 4619 mov r1, r3
|
|
8008e14: 68f8 ldr r0, [r7, #12]
|
|
8008e16: f000 f986 bl 8009126 <USBD_CoreFindEP>
|
|
8008e1a: 4603 mov r3, r0
|
|
8008e1c: 75fb strb r3, [r7, #23]
|
|
|
|
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8008e1e: 7dfb ldrb r3, [r7, #23]
|
|
8008e20: 2bff cmp r3, #255 @ 0xff
|
|
8008e22: d025 beq.n 8008e70 <USBD_LL_DataInStage+0x16c>
|
|
8008e24: 7dfb ldrb r3, [r7, #23]
|
|
8008e26: 2b00 cmp r3, #0
|
|
8008e28: d122 bne.n 8008e70 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008e2a: 68fb ldr r3, [r7, #12]
|
|
8008e2c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008e30: b2db uxtb r3, r3
|
|
8008e32: 2b03 cmp r3, #3
|
|
8008e34: d11c bne.n 8008e70 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
if (pdev->pClass[idx]->DataIn != NULL)
|
|
8008e36: 7dfa ldrb r2, [r7, #23]
|
|
8008e38: 68fb ldr r3, [r7, #12]
|
|
8008e3a: 32ae adds r2, #174 @ 0xae
|
|
8008e3c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008e40: 695b ldr r3, [r3, #20]
|
|
8008e42: 2b00 cmp r3, #0
|
|
8008e44: d014 beq.n 8008e70 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
pdev->classId = idx;
|
|
8008e46: 7dfa ldrb r2, [r7, #23]
|
|
8008e48: 68fb ldr r3, [r7, #12]
|
|
8008e4a: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum);
|
|
8008e4e: 7dfa ldrb r2, [r7, #23]
|
|
8008e50: 68fb ldr r3, [r7, #12]
|
|
8008e52: 32ae adds r2, #174 @ 0xae
|
|
8008e54: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008e58: 695b ldr r3, [r3, #20]
|
|
8008e5a: 7afa ldrb r2, [r7, #11]
|
|
8008e5c: 4611 mov r1, r2
|
|
8008e5e: 68f8 ldr r0, [r7, #12]
|
|
8008e60: 4798 blx r3
|
|
8008e62: 4603 mov r3, r0
|
|
8008e64: 75bb strb r3, [r7, #22]
|
|
|
|
if (ret != USBD_OK)
|
|
8008e66: 7dbb ldrb r3, [r7, #22]
|
|
8008e68: 2b00 cmp r3, #0
|
|
8008e6a: d001 beq.n 8008e70 <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
return ret;
|
|
8008e6c: 7dbb ldrb r3, [r7, #22]
|
|
8008e6e: e000 b.n 8008e72 <USBD_LL_DataInStage+0x16e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8008e70: 2300 movs r3, #0
|
|
}
|
|
8008e72: 4618 mov r0, r3
|
|
8008e74: 3718 adds r7, #24
|
|
8008e76: 46bd mov sp, r7
|
|
8008e78: bd80 pop {r7, pc}
|
|
|
|
08008e7a <USBD_LL_Reset>:
|
|
* Handle Reset event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008e7a: b580 push {r7, lr}
|
|
8008e7c: b084 sub sp, #16
|
|
8008e7e: af00 add r7, sp, #0
|
|
8008e80: 6078 str r0, [r7, #4]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8008e82: 2300 movs r3, #0
|
|
8008e84: 73fb strb r3, [r7, #15]
|
|
|
|
/* Upon Reset call user call back */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8008e86: 687b ldr r3, [r7, #4]
|
|
8008e88: 2201 movs r2, #1
|
|
8008e8a: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->ep0_state = USBD_EP0_IDLE;
|
|
8008e8e: 687b ldr r3, [r7, #4]
|
|
8008e90: 2200 movs r2, #0
|
|
8008e92: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->dev_config = 0U;
|
|
8008e96: 687b ldr r3, [r7, #4]
|
|
8008e98: 2200 movs r2, #0
|
|
8008e9a: 605a str r2, [r3, #4]
|
|
pdev->dev_remote_wakeup = 0U;
|
|
8008e9c: 687b ldr r3, [r7, #4]
|
|
8008e9e: 2200 movs r2, #0
|
|
8008ea0: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
pdev->dev_test_mode = 0U;
|
|
8008ea4: 687b ldr r3, [r7, #4]
|
|
8008ea6: 2200 movs r2, #0
|
|
8008ea8: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
|
|
if (pdev->pClass[0] != NULL)
|
|
8008eac: 687b ldr r3, [r7, #4]
|
|
8008eae: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008eb2: 2b00 cmp r3, #0
|
|
8008eb4: d014 beq.n 8008ee0 <USBD_LL_Reset+0x66>
|
|
{
|
|
if (pdev->pClass[0]->DeInit != NULL)
|
|
8008eb6: 687b ldr r3, [r7, #4]
|
|
8008eb8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008ebc: 685b ldr r3, [r3, #4]
|
|
8008ebe: 2b00 cmp r3, #0
|
|
8008ec0: d00e beq.n 8008ee0 <USBD_LL_Reset+0x66>
|
|
{
|
|
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK)
|
|
8008ec2: 687b ldr r3, [r7, #4]
|
|
8008ec4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008ec8: 685b ldr r3, [r3, #4]
|
|
8008eca: 687a ldr r2, [r7, #4]
|
|
8008ecc: 6852 ldr r2, [r2, #4]
|
|
8008ece: b2d2 uxtb r2, r2
|
|
8008ed0: 4611 mov r1, r2
|
|
8008ed2: 6878 ldr r0, [r7, #4]
|
|
8008ed4: 4798 blx r3
|
|
8008ed6: 4603 mov r3, r0
|
|
8008ed8: 2b00 cmp r3, #0
|
|
8008eda: d001 beq.n 8008ee0 <USBD_LL_Reset+0x66>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8008edc: 2303 movs r3, #3
|
|
8008ede: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Open EP0 OUT */
|
|
(void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
8008ee0: 2340 movs r3, #64 @ 0x40
|
|
8008ee2: 2200 movs r2, #0
|
|
8008ee4: 2100 movs r1, #0
|
|
8008ee6: 6878 ldr r0, [r7, #4]
|
|
8008ee8: f001 fb7b bl 800a5e2 <USBD_LL_OpenEP>
|
|
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
|
|
8008eec: 687b ldr r3, [r7, #4]
|
|
8008eee: 2201 movs r2, #1
|
|
8008ef0: f883 2163 strb.w r2, [r3, #355] @ 0x163
|
|
|
|
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
8008ef4: 687b ldr r3, [r7, #4]
|
|
8008ef6: 2240 movs r2, #64 @ 0x40
|
|
8008ef8: f8a3 2160 strh.w r2, [r3, #352] @ 0x160
|
|
|
|
/* Open EP0 IN */
|
|
(void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
8008efc: 2340 movs r3, #64 @ 0x40
|
|
8008efe: 2200 movs r2, #0
|
|
8008f00: 2180 movs r1, #128 @ 0x80
|
|
8008f02: 6878 ldr r0, [r7, #4]
|
|
8008f04: f001 fb6d bl 800a5e2 <USBD_LL_OpenEP>
|
|
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
|
|
8008f08: 687b ldr r3, [r7, #4]
|
|
8008f0a: 2201 movs r2, #1
|
|
8008f0c: f883 2023 strb.w r2, [r3, #35] @ 0x23
|
|
|
|
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
8008f10: 687b ldr r3, [r7, #4]
|
|
8008f12: 2240 movs r2, #64 @ 0x40
|
|
8008f14: 841a strh r2, [r3, #32]
|
|
|
|
return ret;
|
|
8008f16: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008f18: 4618 mov r0, r3
|
|
8008f1a: 3710 adds r7, #16
|
|
8008f1c: 46bd mov sp, r7
|
|
8008f1e: bd80 pop {r7, pc}
|
|
|
|
08008f20 <USBD_LL_SetSpeed>:
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
|
|
USBD_SpeedTypeDef speed)
|
|
{
|
|
8008f20: b480 push {r7}
|
|
8008f22: b083 sub sp, #12
|
|
8008f24: af00 add r7, sp, #0
|
|
8008f26: 6078 str r0, [r7, #4]
|
|
8008f28: 460b mov r3, r1
|
|
8008f2a: 70fb strb r3, [r7, #3]
|
|
pdev->dev_speed = speed;
|
|
8008f2c: 687b ldr r3, [r7, #4]
|
|
8008f2e: 78fa ldrb r2, [r7, #3]
|
|
8008f30: 741a strb r2, [r3, #16]
|
|
|
|
return USBD_OK;
|
|
8008f32: 2300 movs r3, #0
|
|
}
|
|
8008f34: 4618 mov r0, r3
|
|
8008f36: 370c adds r7, #12
|
|
8008f38: 46bd mov sp, r7
|
|
8008f3a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008f3e: 4770 bx lr
|
|
|
|
08008f40 <USBD_LL_Suspend>:
|
|
* Handle Suspend event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008f40: b480 push {r7}
|
|
8008f42: b083 sub sp, #12
|
|
8008f44: af00 add r7, sp, #0
|
|
8008f46: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state != USBD_STATE_SUSPENDED)
|
|
8008f48: 687b ldr r3, [r7, #4]
|
|
8008f4a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008f4e: b2db uxtb r3, r3
|
|
8008f50: 2b04 cmp r3, #4
|
|
8008f52: d006 beq.n 8008f62 <USBD_LL_Suspend+0x22>
|
|
{
|
|
pdev->dev_old_state = pdev->dev_state;
|
|
8008f54: 687b ldr r3, [r7, #4]
|
|
8008f56: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008f5a: b2da uxtb r2, r3
|
|
8008f5c: 687b ldr r3, [r7, #4]
|
|
8008f5e: f883 229d strb.w r2, [r3, #669] @ 0x29d
|
|
}
|
|
|
|
pdev->dev_state = USBD_STATE_SUSPENDED;
|
|
8008f62: 687b ldr r3, [r7, #4]
|
|
8008f64: 2204 movs r2, #4
|
|
8008f66: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
|
|
return USBD_OK;
|
|
8008f6a: 2300 movs r3, #0
|
|
}
|
|
8008f6c: 4618 mov r0, r3
|
|
8008f6e: 370c adds r7, #12
|
|
8008f70: 46bd mov sp, r7
|
|
8008f72: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008f76: 4770 bx lr
|
|
|
|
08008f78 <USBD_LL_Resume>:
|
|
* Handle Resume event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008f78: b480 push {r7}
|
|
8008f7a: b083 sub sp, #12
|
|
8008f7c: af00 add r7, sp, #0
|
|
8008f7e: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state == USBD_STATE_SUSPENDED)
|
|
8008f80: 687b ldr r3, [r7, #4]
|
|
8008f82: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008f86: b2db uxtb r3, r3
|
|
8008f88: 2b04 cmp r3, #4
|
|
8008f8a: d106 bne.n 8008f9a <USBD_LL_Resume+0x22>
|
|
{
|
|
pdev->dev_state = pdev->dev_old_state;
|
|
8008f8c: 687b ldr r3, [r7, #4]
|
|
8008f8e: f893 329d ldrb.w r3, [r3, #669] @ 0x29d
|
|
8008f92: b2da uxtb r2, r3
|
|
8008f94: 687b ldr r3, [r7, #4]
|
|
8008f96: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
|
|
return USBD_OK;
|
|
8008f9a: 2300 movs r3, #0
|
|
}
|
|
8008f9c: 4618 mov r0, r3
|
|
8008f9e: 370c adds r7, #12
|
|
8008fa0: 46bd mov sp, r7
|
|
8008fa2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008fa6: 4770 bx lr
|
|
|
|
08008fa8 <USBD_LL_SOF>:
|
|
* Handle SOF event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8008fa8: b580 push {r7, lr}
|
|
8008faa: b082 sub sp, #8
|
|
8008fac: af00 add r7, sp, #0
|
|
8008fae: 6078 str r0, [r7, #4]
|
|
/* The SOF event can be distributed for all classes that support it */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8008fb0: 687b ldr r3, [r7, #4]
|
|
8008fb2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8008fb6: b2db uxtb r3, r3
|
|
8008fb8: 2b03 cmp r3, #3
|
|
8008fba: d110 bne.n 8008fde <USBD_LL_SOF+0x36>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
8008fbc: 687b ldr r3, [r7, #4]
|
|
8008fbe: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008fc2: 2b00 cmp r3, #0
|
|
8008fc4: d00b beq.n 8008fde <USBD_LL_SOF+0x36>
|
|
{
|
|
if (pdev->pClass[0]->SOF != NULL)
|
|
8008fc6: 687b ldr r3, [r7, #4]
|
|
8008fc8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008fcc: 69db ldr r3, [r3, #28]
|
|
8008fce: 2b00 cmp r3, #0
|
|
8008fd0: d005 beq.n 8008fde <USBD_LL_SOF+0x36>
|
|
{
|
|
(void)pdev->pClass[0]->SOF(pdev);
|
|
8008fd2: 687b ldr r3, [r7, #4]
|
|
8008fd4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8008fd8: 69db ldr r3, [r3, #28]
|
|
8008fda: 6878 ldr r0, [r7, #4]
|
|
8008fdc: 4798 blx r3
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
|
|
return USBD_OK;
|
|
8008fde: 2300 movs r3, #0
|
|
}
|
|
8008fe0: 4618 mov r0, r3
|
|
8008fe2: 3708 adds r7, #8
|
|
8008fe4: 46bd mov sp, r7
|
|
8008fe6: bd80 pop {r7, pc}
|
|
|
|
08008fe8 <USBD_LL_IsoINIncomplete>:
|
|
* @param epnum: Endpoint number
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum)
|
|
{
|
|
8008fe8: b580 push {r7, lr}
|
|
8008fea: b082 sub sp, #8
|
|
8008fec: af00 add r7, sp, #0
|
|
8008fee: 6078 str r0, [r7, #4]
|
|
8008ff0: 460b mov r3, r1
|
|
8008ff2: 70fb strb r3, [r7, #3]
|
|
if (pdev->pClass[pdev->classId] == NULL)
|
|
8008ff4: 687b ldr r3, [r7, #4]
|
|
8008ff6: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8008ffa: 687b ldr r3, [r7, #4]
|
|
8008ffc: 32ae adds r2, #174 @ 0xae
|
|
8008ffe: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009002: 2b00 cmp r3, #0
|
|
8009004: d101 bne.n 800900a <USBD_LL_IsoINIncomplete+0x22>
|
|
{
|
|
return USBD_FAIL;
|
|
8009006: 2303 movs r3, #3
|
|
8009008: e01c b.n 8009044 <USBD_LL_IsoINIncomplete+0x5c>
|
|
}
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
800900a: 687b ldr r3, [r7, #4]
|
|
800900c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009010: b2db uxtb r3, r3
|
|
8009012: 2b03 cmp r3, #3
|
|
8009014: d115 bne.n 8009042 <USBD_LL_IsoINIncomplete+0x5a>
|
|
{
|
|
if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL)
|
|
8009016: 687b ldr r3, [r7, #4]
|
|
8009018: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800901c: 687b ldr r3, [r7, #4]
|
|
800901e: 32ae adds r2, #174 @ 0xae
|
|
8009020: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009024: 6a1b ldr r3, [r3, #32]
|
|
8009026: 2b00 cmp r3, #0
|
|
8009028: d00b beq.n 8009042 <USBD_LL_IsoINIncomplete+0x5a>
|
|
{
|
|
(void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum);
|
|
800902a: 687b ldr r3, [r7, #4]
|
|
800902c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8009030: 687b ldr r3, [r7, #4]
|
|
8009032: 32ae adds r2, #174 @ 0xae
|
|
8009034: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009038: 6a1b ldr r3, [r3, #32]
|
|
800903a: 78fa ldrb r2, [r7, #3]
|
|
800903c: 4611 mov r1, r2
|
|
800903e: 6878 ldr r0, [r7, #4]
|
|
8009040: 4798 blx r3
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8009042: 2300 movs r3, #0
|
|
}
|
|
8009044: 4618 mov r0, r3
|
|
8009046: 3708 adds r7, #8
|
|
8009048: 46bd mov sp, r7
|
|
800904a: bd80 pop {r7, pc}
|
|
|
|
0800904c <USBD_LL_IsoOUTIncomplete>:
|
|
* @param epnum: Endpoint number
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum)
|
|
{
|
|
800904c: b580 push {r7, lr}
|
|
800904e: b082 sub sp, #8
|
|
8009050: af00 add r7, sp, #0
|
|
8009052: 6078 str r0, [r7, #4]
|
|
8009054: 460b mov r3, r1
|
|
8009056: 70fb strb r3, [r7, #3]
|
|
if (pdev->pClass[pdev->classId] == NULL)
|
|
8009058: 687b ldr r3, [r7, #4]
|
|
800905a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
800905e: 687b ldr r3, [r7, #4]
|
|
8009060: 32ae adds r2, #174 @ 0xae
|
|
8009062: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009066: 2b00 cmp r3, #0
|
|
8009068: d101 bne.n 800906e <USBD_LL_IsoOUTIncomplete+0x22>
|
|
{
|
|
return USBD_FAIL;
|
|
800906a: 2303 movs r3, #3
|
|
800906c: e01c b.n 80090a8 <USBD_LL_IsoOUTIncomplete+0x5c>
|
|
}
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
800906e: 687b ldr r3, [r7, #4]
|
|
8009070: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009074: b2db uxtb r3, r3
|
|
8009076: 2b03 cmp r3, #3
|
|
8009078: d115 bne.n 80090a6 <USBD_LL_IsoOUTIncomplete+0x5a>
|
|
{
|
|
if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL)
|
|
800907a: 687b ldr r3, [r7, #4]
|
|
800907c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8009080: 687b ldr r3, [r7, #4]
|
|
8009082: 32ae adds r2, #174 @ 0xae
|
|
8009084: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009088: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800908a: 2b00 cmp r3, #0
|
|
800908c: d00b beq.n 80090a6 <USBD_LL_IsoOUTIncomplete+0x5a>
|
|
{
|
|
(void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum);
|
|
800908e: 687b ldr r3, [r7, #4]
|
|
8009090: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8009094: 687b ldr r3, [r7, #4]
|
|
8009096: 32ae adds r2, #174 @ 0xae
|
|
8009098: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800909c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800909e: 78fa ldrb r2, [r7, #3]
|
|
80090a0: 4611 mov r1, r2
|
|
80090a2: 6878 ldr r0, [r7, #4]
|
|
80090a4: 4798 blx r3
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
80090a6: 2300 movs r3, #0
|
|
}
|
|
80090a8: 4618 mov r0, r3
|
|
80090aa: 3708 adds r7, #8
|
|
80090ac: 46bd mov sp, r7
|
|
80090ae: bd80 pop {r7, pc}
|
|
|
|
080090b0 <USBD_LL_DevConnected>:
|
|
* Handle device connection event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80090b0: b480 push {r7}
|
|
80090b2: b083 sub sp, #12
|
|
80090b4: af00 add r7, sp, #0
|
|
80090b6: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument compilation warning */
|
|
UNUSED(pdev);
|
|
|
|
return USBD_OK;
|
|
80090b8: 2300 movs r3, #0
|
|
}
|
|
80090ba: 4618 mov r0, r3
|
|
80090bc: 370c adds r7, #12
|
|
80090be: 46bd mov sp, r7
|
|
80090c0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80090c4: 4770 bx lr
|
|
|
|
080090c6 <USBD_LL_DevDisconnected>:
|
|
* Handle device disconnection event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80090c6: b580 push {r7, lr}
|
|
80090c8: b084 sub sp, #16
|
|
80090ca: af00 add r7, sp, #0
|
|
80090cc: 6078 str r0, [r7, #4]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80090ce: 2300 movs r3, #0
|
|
80090d0: 73fb strb r3, [r7, #15]
|
|
|
|
/* Free Class Resources */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
80090d2: 687b ldr r3, [r7, #4]
|
|
80090d4: 2201 movs r2, #1
|
|
80090d6: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
80090da: 687b ldr r3, [r7, #4]
|
|
80090dc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80090e0: 2b00 cmp r3, #0
|
|
80090e2: d00e beq.n 8009102 <USBD_LL_DevDisconnected+0x3c>
|
|
{
|
|
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U)
|
|
80090e4: 687b ldr r3, [r7, #4]
|
|
80090e6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80090ea: 685b ldr r3, [r3, #4]
|
|
80090ec: 687a ldr r2, [r7, #4]
|
|
80090ee: 6852 ldr r2, [r2, #4]
|
|
80090f0: b2d2 uxtb r2, r2
|
|
80090f2: 4611 mov r1, r2
|
|
80090f4: 6878 ldr r0, [r7, #4]
|
|
80090f6: 4798 blx r3
|
|
80090f8: 4603 mov r3, r0
|
|
80090fa: 2b00 cmp r3, #0
|
|
80090fc: d001 beq.n 8009102 <USBD_LL_DevDisconnected+0x3c>
|
|
{
|
|
ret = USBD_FAIL;
|
|
80090fe: 2303 movs r3, #3
|
|
8009100: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
8009102: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009104: 4618 mov r0, r3
|
|
8009106: 3710 adds r7, #16
|
|
8009108: 46bd mov sp, r7
|
|
800910a: bd80 pop {r7, pc}
|
|
|
|
0800910c <USBD_CoreFindIF>:
|
|
* @param pdev: device instance
|
|
* @param index : selected interface number
|
|
* @retval index of the class using the selected interface number. OxFF if no class found.
|
|
*/
|
|
uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index)
|
|
{
|
|
800910c: b480 push {r7}
|
|
800910e: b083 sub sp, #12
|
|
8009110: af00 add r7, sp, #0
|
|
8009112: 6078 str r0, [r7, #4]
|
|
8009114: 460b mov r3, r1
|
|
8009116: 70fb strb r3, [r7, #3]
|
|
return 0xFFU;
|
|
#else
|
|
UNUSED(pdev);
|
|
UNUSED(index);
|
|
|
|
return 0x00U;
|
|
8009118: 2300 movs r3, #0
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
800911a: 4618 mov r0, r3
|
|
800911c: 370c adds r7, #12
|
|
800911e: 46bd mov sp, r7
|
|
8009120: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009124: 4770 bx lr
|
|
|
|
08009126 <USBD_CoreFindEP>:
|
|
* @param pdev: device instance
|
|
* @param index : selected endpoint number
|
|
* @retval index of the class using the selected endpoint number. 0xFF if no class found.
|
|
*/
|
|
uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index)
|
|
{
|
|
8009126: b480 push {r7}
|
|
8009128: b083 sub sp, #12
|
|
800912a: af00 add r7, sp, #0
|
|
800912c: 6078 str r0, [r7, #4]
|
|
800912e: 460b mov r3, r1
|
|
8009130: 70fb strb r3, [r7, #3]
|
|
return 0xFFU;
|
|
#else
|
|
UNUSED(pdev);
|
|
UNUSED(index);
|
|
|
|
return 0x00U;
|
|
8009132: 2300 movs r3, #0
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
8009134: 4618 mov r0, r3
|
|
8009136: 370c adds r7, #12
|
|
8009138: 46bd mov sp, r7
|
|
800913a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800913e: 4770 bx lr
|
|
|
|
08009140 <USBD_GetEpDesc>:
|
|
* @param pConfDesc: pointer to Bos descriptor
|
|
* @param EpAddr: endpoint address
|
|
* @retval pointer to video endpoint descriptor
|
|
*/
|
|
void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr)
|
|
{
|
|
8009140: b580 push {r7, lr}
|
|
8009142: b086 sub sp, #24
|
|
8009144: af00 add r7, sp, #0
|
|
8009146: 6078 str r0, [r7, #4]
|
|
8009148: 460b mov r3, r1
|
|
800914a: 70fb strb r3, [r7, #3]
|
|
USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc;
|
|
800914c: 687b ldr r3, [r7, #4]
|
|
800914e: 617b str r3, [r7, #20]
|
|
USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc;
|
|
8009150: 687b ldr r3, [r7, #4]
|
|
8009152: 60fb str r3, [r7, #12]
|
|
USBD_EpDescTypeDef *pEpDesc = NULL;
|
|
8009154: 2300 movs r3, #0
|
|
8009156: 613b str r3, [r7, #16]
|
|
uint16_t ptr;
|
|
|
|
if (desc->wTotalLength > desc->bLength)
|
|
8009158: 68fb ldr r3, [r7, #12]
|
|
800915a: 885b ldrh r3, [r3, #2]
|
|
800915c: b29b uxth r3, r3
|
|
800915e: 68fa ldr r2, [r7, #12]
|
|
8009160: 7812 ldrb r2, [r2, #0]
|
|
8009162: 4293 cmp r3, r2
|
|
8009164: d91f bls.n 80091a6 <USBD_GetEpDesc+0x66>
|
|
{
|
|
ptr = desc->bLength;
|
|
8009166: 68fb ldr r3, [r7, #12]
|
|
8009168: 781b ldrb r3, [r3, #0]
|
|
800916a: 817b strh r3, [r7, #10]
|
|
|
|
while (ptr < desc->wTotalLength)
|
|
800916c: e013 b.n 8009196 <USBD_GetEpDesc+0x56>
|
|
{
|
|
pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr);
|
|
800916e: f107 030a add.w r3, r7, #10
|
|
8009172: 4619 mov r1, r3
|
|
8009174: 6978 ldr r0, [r7, #20]
|
|
8009176: f000 f81b bl 80091b0 <USBD_GetNextDesc>
|
|
800917a: 6178 str r0, [r7, #20]
|
|
|
|
if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT)
|
|
800917c: 697b ldr r3, [r7, #20]
|
|
800917e: 785b ldrb r3, [r3, #1]
|
|
8009180: 2b05 cmp r3, #5
|
|
8009182: d108 bne.n 8009196 <USBD_GetEpDesc+0x56>
|
|
{
|
|
pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc;
|
|
8009184: 697b ldr r3, [r7, #20]
|
|
8009186: 613b str r3, [r7, #16]
|
|
|
|
if (pEpDesc->bEndpointAddress == EpAddr)
|
|
8009188: 693b ldr r3, [r7, #16]
|
|
800918a: 789b ldrb r3, [r3, #2]
|
|
800918c: 78fa ldrb r2, [r7, #3]
|
|
800918e: 429a cmp r2, r3
|
|
8009190: d008 beq.n 80091a4 <USBD_GetEpDesc+0x64>
|
|
{
|
|
break;
|
|
}
|
|
else
|
|
{
|
|
pEpDesc = NULL;
|
|
8009192: 2300 movs r3, #0
|
|
8009194: 613b str r3, [r7, #16]
|
|
while (ptr < desc->wTotalLength)
|
|
8009196: 68fb ldr r3, [r7, #12]
|
|
8009198: 885b ldrh r3, [r3, #2]
|
|
800919a: b29a uxth r2, r3
|
|
800919c: 897b ldrh r3, [r7, #10]
|
|
800919e: 429a cmp r2, r3
|
|
80091a0: d8e5 bhi.n 800916e <USBD_GetEpDesc+0x2e>
|
|
80091a2: e000 b.n 80091a6 <USBD_GetEpDesc+0x66>
|
|
break;
|
|
80091a4: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return (void *)pEpDesc;
|
|
80091a6: 693b ldr r3, [r7, #16]
|
|
}
|
|
80091a8: 4618 mov r0, r3
|
|
80091aa: 3718 adds r7, #24
|
|
80091ac: 46bd mov sp, r7
|
|
80091ae: bd80 pop {r7, pc}
|
|
|
|
080091b0 <USBD_GetNextDesc>:
|
|
* @param buf: Buffer where the descriptor is available
|
|
* @param ptr: data pointer inside the descriptor
|
|
* @retval next header
|
|
*/
|
|
USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr)
|
|
{
|
|
80091b0: b480 push {r7}
|
|
80091b2: b085 sub sp, #20
|
|
80091b4: af00 add r7, sp, #0
|
|
80091b6: 6078 str r0, [r7, #4]
|
|
80091b8: 6039 str r1, [r7, #0]
|
|
USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf;
|
|
80091ba: 687b ldr r3, [r7, #4]
|
|
80091bc: 60fb str r3, [r7, #12]
|
|
|
|
*ptr += pnext->bLength;
|
|
80091be: 683b ldr r3, [r7, #0]
|
|
80091c0: 881b ldrh r3, [r3, #0]
|
|
80091c2: 68fa ldr r2, [r7, #12]
|
|
80091c4: 7812 ldrb r2, [r2, #0]
|
|
80091c6: 4413 add r3, r2
|
|
80091c8: b29a uxth r2, r3
|
|
80091ca: 683b ldr r3, [r7, #0]
|
|
80091cc: 801a strh r2, [r3, #0]
|
|
pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength);
|
|
80091ce: 68fb ldr r3, [r7, #12]
|
|
80091d0: 781b ldrb r3, [r3, #0]
|
|
80091d2: 461a mov r2, r3
|
|
80091d4: 687b ldr r3, [r7, #4]
|
|
80091d6: 4413 add r3, r2
|
|
80091d8: 60fb str r3, [r7, #12]
|
|
|
|
return (pnext);
|
|
80091da: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80091dc: 4618 mov r0, r3
|
|
80091de: 3714 adds r7, #20
|
|
80091e0: 46bd mov sp, r7
|
|
80091e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80091e6: 4770 bx lr
|
|
|
|
080091e8 <SWAPBYTE>:
|
|
|
|
/** @defgroup USBD_DEF_Exported_Macros
|
|
* @{
|
|
*/
|
|
__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
|
|
{
|
|
80091e8: b480 push {r7}
|
|
80091ea: b087 sub sp, #28
|
|
80091ec: af00 add r7, sp, #0
|
|
80091ee: 6078 str r0, [r7, #4]
|
|
uint16_t _SwapVal;
|
|
uint16_t _Byte1;
|
|
uint16_t _Byte2;
|
|
uint8_t *_pbuff = addr;
|
|
80091f0: 687b ldr r3, [r7, #4]
|
|
80091f2: 617b str r3, [r7, #20]
|
|
|
|
_Byte1 = *(uint8_t *)_pbuff;
|
|
80091f4: 697b ldr r3, [r7, #20]
|
|
80091f6: 781b ldrb r3, [r3, #0]
|
|
80091f8: 827b strh r3, [r7, #18]
|
|
_pbuff++;
|
|
80091fa: 697b ldr r3, [r7, #20]
|
|
80091fc: 3301 adds r3, #1
|
|
80091fe: 617b str r3, [r7, #20]
|
|
_Byte2 = *(uint8_t *)_pbuff;
|
|
8009200: 697b ldr r3, [r7, #20]
|
|
8009202: 781b ldrb r3, [r3, #0]
|
|
8009204: 823b strh r3, [r7, #16]
|
|
|
|
_SwapVal = (_Byte2 << 8) | _Byte1;
|
|
8009206: f9b7 3010 ldrsh.w r3, [r7, #16]
|
|
800920a: 021b lsls r3, r3, #8
|
|
800920c: b21a sxth r2, r3
|
|
800920e: f9b7 3012 ldrsh.w r3, [r7, #18]
|
|
8009212: 4313 orrs r3, r2
|
|
8009214: b21b sxth r3, r3
|
|
8009216: 81fb strh r3, [r7, #14]
|
|
|
|
return _SwapVal;
|
|
8009218: 89fb ldrh r3, [r7, #14]
|
|
}
|
|
800921a: 4618 mov r0, r3
|
|
800921c: 371c adds r7, #28
|
|
800921e: 46bd mov sp, r7
|
|
8009220: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009224: 4770 bx lr
|
|
...
|
|
|
|
08009228 <USBD_StdDevReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009228: b580 push {r7, lr}
|
|
800922a: b084 sub sp, #16
|
|
800922c: af00 add r7, sp, #0
|
|
800922e: 6078 str r0, [r7, #4]
|
|
8009230: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8009232: 2300 movs r3, #0
|
|
8009234: 73fb strb r3, [r7, #15]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8009236: 683b ldr r3, [r7, #0]
|
|
8009238: 781b ldrb r3, [r3, #0]
|
|
800923a: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
800923e: 2b40 cmp r3, #64 @ 0x40
|
|
8009240: d005 beq.n 800924e <USBD_StdDevReq+0x26>
|
|
8009242: 2b40 cmp r3, #64 @ 0x40
|
|
8009244: d857 bhi.n 80092f6 <USBD_StdDevReq+0xce>
|
|
8009246: 2b00 cmp r3, #0
|
|
8009248: d00f beq.n 800926a <USBD_StdDevReq+0x42>
|
|
800924a: 2b20 cmp r3, #32
|
|
800924c: d153 bne.n 80092f6 <USBD_StdDevReq+0xce>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req);
|
|
800924e: 687b ldr r3, [r7, #4]
|
|
8009250: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8009254: 687b ldr r3, [r7, #4]
|
|
8009256: 32ae adds r2, #174 @ 0xae
|
|
8009258: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800925c: 689b ldr r3, [r3, #8]
|
|
800925e: 6839 ldr r1, [r7, #0]
|
|
8009260: 6878 ldr r0, [r7, #4]
|
|
8009262: 4798 blx r3
|
|
8009264: 4603 mov r3, r0
|
|
8009266: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009268: e04a b.n 8009300 <USBD_StdDevReq+0xd8>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
800926a: 683b ldr r3, [r7, #0]
|
|
800926c: 785b ldrb r3, [r3, #1]
|
|
800926e: 2b09 cmp r3, #9
|
|
8009270: d83b bhi.n 80092ea <USBD_StdDevReq+0xc2>
|
|
8009272: a201 add r2, pc, #4 @ (adr r2, 8009278 <USBD_StdDevReq+0x50>)
|
|
8009274: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8009278: 080092cd .word 0x080092cd
|
|
800927c: 080092e1 .word 0x080092e1
|
|
8009280: 080092eb .word 0x080092eb
|
|
8009284: 080092d7 .word 0x080092d7
|
|
8009288: 080092eb .word 0x080092eb
|
|
800928c: 080092ab .word 0x080092ab
|
|
8009290: 080092a1 .word 0x080092a1
|
|
8009294: 080092eb .word 0x080092eb
|
|
8009298: 080092c3 .word 0x080092c3
|
|
800929c: 080092b5 .word 0x080092b5
|
|
{
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
USBD_GetDescriptor(pdev, req);
|
|
80092a0: 6839 ldr r1, [r7, #0]
|
|
80092a2: 6878 ldr r0, [r7, #4]
|
|
80092a4: f000 fa3e bl 8009724 <USBD_GetDescriptor>
|
|
break;
|
|
80092a8: e024 b.n 80092f4 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_ADDRESS:
|
|
USBD_SetAddress(pdev, req);
|
|
80092aa: 6839 ldr r1, [r7, #0]
|
|
80092ac: 6878 ldr r0, [r7, #4]
|
|
80092ae: f000 fbcd bl 8009a4c <USBD_SetAddress>
|
|
break;
|
|
80092b2: e01f b.n 80092f4 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_CONFIGURATION:
|
|
ret = USBD_SetConfig(pdev, req);
|
|
80092b4: 6839 ldr r1, [r7, #0]
|
|
80092b6: 6878 ldr r0, [r7, #4]
|
|
80092b8: f000 fc0c bl 8009ad4 <USBD_SetConfig>
|
|
80092bc: 4603 mov r3, r0
|
|
80092be: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80092c0: e018 b.n 80092f4 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_GET_CONFIGURATION:
|
|
USBD_GetConfig(pdev, req);
|
|
80092c2: 6839 ldr r1, [r7, #0]
|
|
80092c4: 6878 ldr r0, [r7, #4]
|
|
80092c6: f000 fcaf bl 8009c28 <USBD_GetConfig>
|
|
break;
|
|
80092ca: e013 b.n 80092f4 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
USBD_GetStatus(pdev, req);
|
|
80092cc: 6839 ldr r1, [r7, #0]
|
|
80092ce: 6878 ldr r0, [r7, #4]
|
|
80092d0: f000 fce0 bl 8009c94 <USBD_GetStatus>
|
|
break;
|
|
80092d4: e00e b.n 80092f4 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_FEATURE:
|
|
USBD_SetFeature(pdev, req);
|
|
80092d6: 6839 ldr r1, [r7, #0]
|
|
80092d8: 6878 ldr r0, [r7, #4]
|
|
80092da: f000 fd0f bl 8009cfc <USBD_SetFeature>
|
|
break;
|
|
80092de: e009 b.n 80092f4 <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
USBD_ClrFeature(pdev, req);
|
|
80092e0: 6839 ldr r1, [r7, #0]
|
|
80092e2: 6878 ldr r0, [r7, #4]
|
|
80092e4: f000 fd33 bl 8009d4e <USBD_ClrFeature>
|
|
break;
|
|
80092e8: e004 b.n 80092f4 <USBD_StdDevReq+0xcc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80092ea: 6839 ldr r1, [r7, #0]
|
|
80092ec: 6878 ldr r0, [r7, #4]
|
|
80092ee: f000 fd8a bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
80092f2: bf00 nop
|
|
}
|
|
break;
|
|
80092f4: e004 b.n 8009300 <USBD_StdDevReq+0xd8>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80092f6: 6839 ldr r1, [r7, #0]
|
|
80092f8: 6878 ldr r0, [r7, #4]
|
|
80092fa: f000 fd84 bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
80092fe: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8009300: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009302: 4618 mov r0, r3
|
|
8009304: 3710 adds r7, #16
|
|
8009306: 46bd mov sp, r7
|
|
8009308: bd80 pop {r7, pc}
|
|
800930a: bf00 nop
|
|
|
|
0800930c <USBD_StdItfReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
800930c: b580 push {r7, lr}
|
|
800930e: b084 sub sp, #16
|
|
8009310: af00 add r7, sp, #0
|
|
8009312: 6078 str r0, [r7, #4]
|
|
8009314: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8009316: 2300 movs r3, #0
|
|
8009318: 73fb strb r3, [r7, #15]
|
|
uint8_t idx;
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
800931a: 683b ldr r3, [r7, #0]
|
|
800931c: 781b ldrb r3, [r3, #0]
|
|
800931e: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8009322: 2b40 cmp r3, #64 @ 0x40
|
|
8009324: d005 beq.n 8009332 <USBD_StdItfReq+0x26>
|
|
8009326: 2b40 cmp r3, #64 @ 0x40
|
|
8009328: d852 bhi.n 80093d0 <USBD_StdItfReq+0xc4>
|
|
800932a: 2b00 cmp r3, #0
|
|
800932c: d001 beq.n 8009332 <USBD_StdItfReq+0x26>
|
|
800932e: 2b20 cmp r3, #32
|
|
8009330: d14e bne.n 80093d0 <USBD_StdItfReq+0xc4>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (pdev->dev_state)
|
|
8009332: 687b ldr r3, [r7, #4]
|
|
8009334: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009338: b2db uxtb r3, r3
|
|
800933a: 3b01 subs r3, #1
|
|
800933c: 2b02 cmp r3, #2
|
|
800933e: d840 bhi.n 80093c2 <USBD_StdItfReq+0xb6>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
|
|
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
|
|
8009340: 683b ldr r3, [r7, #0]
|
|
8009342: 889b ldrh r3, [r3, #4]
|
|
8009344: b2db uxtb r3, r3
|
|
8009346: 2b01 cmp r3, #1
|
|
8009348: d836 bhi.n 80093b8 <USBD_StdItfReq+0xac>
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex));
|
|
800934a: 683b ldr r3, [r7, #0]
|
|
800934c: 889b ldrh r3, [r3, #4]
|
|
800934e: b2db uxtb r3, r3
|
|
8009350: 4619 mov r1, r3
|
|
8009352: 6878 ldr r0, [r7, #4]
|
|
8009354: f7ff feda bl 800910c <USBD_CoreFindIF>
|
|
8009358: 4603 mov r3, r0
|
|
800935a: 73bb strb r3, [r7, #14]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
800935c: 7bbb ldrb r3, [r7, #14]
|
|
800935e: 2bff cmp r3, #255 @ 0xff
|
|
8009360: d01d beq.n 800939e <USBD_StdItfReq+0x92>
|
|
8009362: 7bbb ldrb r3, [r7, #14]
|
|
8009364: 2b00 cmp r3, #0
|
|
8009366: d11a bne.n 800939e <USBD_StdItfReq+0x92>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8009368: 7bba ldrb r2, [r7, #14]
|
|
800936a: 687b ldr r3, [r7, #4]
|
|
800936c: 32ae adds r2, #174 @ 0xae
|
|
800936e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009372: 689b ldr r3, [r3, #8]
|
|
8009374: 2b00 cmp r3, #0
|
|
8009376: d00f beq.n 8009398 <USBD_StdItfReq+0x8c>
|
|
{
|
|
pdev->classId = idx;
|
|
8009378: 7bba ldrb r2, [r7, #14]
|
|
800937a: 687b ldr r3, [r7, #4]
|
|
800937c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
|
|
8009380: 7bba ldrb r2, [r7, #14]
|
|
8009382: 687b ldr r3, [r7, #4]
|
|
8009384: 32ae adds r2, #174 @ 0xae
|
|
8009386: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
800938a: 689b ldr r3, [r3, #8]
|
|
800938c: 6839 ldr r1, [r7, #0]
|
|
800938e: 6878 ldr r0, [r7, #4]
|
|
8009390: 4798 blx r3
|
|
8009392: 4603 mov r3, r0
|
|
8009394: 73fb strb r3, [r7, #15]
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8009396: e004 b.n 80093a2 <USBD_StdItfReq+0x96>
|
|
}
|
|
else
|
|
{
|
|
/* should never reach this condition */
|
|
ret = USBD_FAIL;
|
|
8009398: 2303 movs r3, #3
|
|
800939a: 73fb strb r3, [r7, #15]
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
800939c: e001 b.n 80093a2 <USBD_StdItfReq+0x96>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* No relative interface found */
|
|
ret = USBD_FAIL;
|
|
800939e: 2303 movs r3, #3
|
|
80093a0: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
if ((req->wLength == 0U) && (ret == USBD_OK))
|
|
80093a2: 683b ldr r3, [r7, #0]
|
|
80093a4: 88db ldrh r3, [r3, #6]
|
|
80093a6: 2b00 cmp r3, #0
|
|
80093a8: d110 bne.n 80093cc <USBD_StdItfReq+0xc0>
|
|
80093aa: 7bfb ldrb r3, [r7, #15]
|
|
80093ac: 2b00 cmp r3, #0
|
|
80093ae: d10d bne.n 80093cc <USBD_StdItfReq+0xc0>
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80093b0: 6878 ldr r0, [r7, #4]
|
|
80093b2: f000 fde5 bl 8009f80 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
80093b6: e009 b.n 80093cc <USBD_StdItfReq+0xc0>
|
|
USBD_CtlError(pdev, req);
|
|
80093b8: 6839 ldr r1, [r7, #0]
|
|
80093ba: 6878 ldr r0, [r7, #4]
|
|
80093bc: f000 fd23 bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
80093c0: e004 b.n 80093cc <USBD_StdItfReq+0xc0>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80093c2: 6839 ldr r1, [r7, #0]
|
|
80093c4: 6878 ldr r0, [r7, #4]
|
|
80093c6: f000 fd1e bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
80093ca: e000 b.n 80093ce <USBD_StdItfReq+0xc2>
|
|
break;
|
|
80093cc: bf00 nop
|
|
}
|
|
break;
|
|
80093ce: e004 b.n 80093da <USBD_StdItfReq+0xce>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80093d0: 6839 ldr r1, [r7, #0]
|
|
80093d2: 6878 ldr r0, [r7, #4]
|
|
80093d4: f000 fd17 bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
80093d8: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
80093da: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80093dc: 4618 mov r0, r3
|
|
80093de: 3710 adds r7, #16
|
|
80093e0: 46bd mov sp, r7
|
|
80093e2: bd80 pop {r7, pc}
|
|
|
|
080093e4 <USBD_StdEPReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
80093e4: b580 push {r7, lr}
|
|
80093e6: b084 sub sp, #16
|
|
80093e8: af00 add r7, sp, #0
|
|
80093ea: 6078 str r0, [r7, #4]
|
|
80093ec: 6039 str r1, [r7, #0]
|
|
USBD_EndpointTypeDef *pep;
|
|
uint8_t ep_addr;
|
|
uint8_t idx;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80093ee: 2300 movs r3, #0
|
|
80093f0: 73fb strb r3, [r7, #15]
|
|
|
|
ep_addr = LOBYTE(req->wIndex);
|
|
80093f2: 683b ldr r3, [r7, #0]
|
|
80093f4: 889b ldrh r3, [r3, #4]
|
|
80093f6: 73bb strb r3, [r7, #14]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
80093f8: 683b ldr r3, [r7, #0]
|
|
80093fa: 781b ldrb r3, [r3, #0]
|
|
80093fc: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8009400: 2b40 cmp r3, #64 @ 0x40
|
|
8009402: d007 beq.n 8009414 <USBD_StdEPReq+0x30>
|
|
8009404: 2b40 cmp r3, #64 @ 0x40
|
|
8009406: f200 8181 bhi.w 800970c <USBD_StdEPReq+0x328>
|
|
800940a: 2b00 cmp r3, #0
|
|
800940c: d02a beq.n 8009464 <USBD_StdEPReq+0x80>
|
|
800940e: 2b20 cmp r3, #32
|
|
8009410: f040 817c bne.w 800970c <USBD_StdEPReq+0x328>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
/* Get the class index relative to this endpoint */
|
|
idx = USBD_CoreFindEP(pdev, ep_addr);
|
|
8009414: 7bbb ldrb r3, [r7, #14]
|
|
8009416: 4619 mov r1, r3
|
|
8009418: 6878 ldr r0, [r7, #4]
|
|
800941a: f7ff fe84 bl 8009126 <USBD_CoreFindEP>
|
|
800941e: 4603 mov r3, r0
|
|
8009420: 737b strb r3, [r7, #13]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8009422: 7b7b ldrb r3, [r7, #13]
|
|
8009424: 2bff cmp r3, #255 @ 0xff
|
|
8009426: f000 8176 beq.w 8009716 <USBD_StdEPReq+0x332>
|
|
800942a: 7b7b ldrb r3, [r7, #13]
|
|
800942c: 2b00 cmp r3, #0
|
|
800942e: f040 8172 bne.w 8009716 <USBD_StdEPReq+0x332>
|
|
{
|
|
pdev->classId = idx;
|
|
8009432: 7b7a ldrb r2, [r7, #13]
|
|
8009434: 687b ldr r3, [r7, #4]
|
|
8009436: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
800943a: 7b7a ldrb r2, [r7, #13]
|
|
800943c: 687b ldr r3, [r7, #4]
|
|
800943e: 32ae adds r2, #174 @ 0xae
|
|
8009440: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009444: 689b ldr r3, [r3, #8]
|
|
8009446: 2b00 cmp r3, #0
|
|
8009448: f000 8165 beq.w 8009716 <USBD_StdEPReq+0x332>
|
|
{
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req);
|
|
800944c: 7b7a ldrb r2, [r7, #13]
|
|
800944e: 687b ldr r3, [r7, #4]
|
|
8009450: 32ae adds r2, #174 @ 0xae
|
|
8009452: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009456: 689b ldr r3, [r3, #8]
|
|
8009458: 6839 ldr r1, [r7, #0]
|
|
800945a: 6878 ldr r0, [r7, #4]
|
|
800945c: 4798 blx r3
|
|
800945e: 4603 mov r3, r0
|
|
8009460: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
8009462: e158 b.n 8009716 <USBD_StdEPReq+0x332>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
8009464: 683b ldr r3, [r7, #0]
|
|
8009466: 785b ldrb r3, [r3, #1]
|
|
8009468: 2b03 cmp r3, #3
|
|
800946a: d008 beq.n 800947e <USBD_StdEPReq+0x9a>
|
|
800946c: 2b03 cmp r3, #3
|
|
800946e: f300 8147 bgt.w 8009700 <USBD_StdEPReq+0x31c>
|
|
8009472: 2b00 cmp r3, #0
|
|
8009474: f000 809b beq.w 80095ae <USBD_StdEPReq+0x1ca>
|
|
8009478: 2b01 cmp r3, #1
|
|
800947a: d03c beq.n 80094f6 <USBD_StdEPReq+0x112>
|
|
800947c: e140 b.n 8009700 <USBD_StdEPReq+0x31c>
|
|
{
|
|
case USB_REQ_SET_FEATURE:
|
|
switch (pdev->dev_state)
|
|
800947e: 687b ldr r3, [r7, #4]
|
|
8009480: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009484: b2db uxtb r3, r3
|
|
8009486: 2b02 cmp r3, #2
|
|
8009488: d002 beq.n 8009490 <USBD_StdEPReq+0xac>
|
|
800948a: 2b03 cmp r3, #3
|
|
800948c: d016 beq.n 80094bc <USBD_StdEPReq+0xd8>
|
|
800948e: e02c b.n 80094ea <USBD_StdEPReq+0x106>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
8009490: 7bbb ldrb r3, [r7, #14]
|
|
8009492: 2b00 cmp r3, #0
|
|
8009494: d00d beq.n 80094b2 <USBD_StdEPReq+0xce>
|
|
8009496: 7bbb ldrb r3, [r7, #14]
|
|
8009498: 2b80 cmp r3, #128 @ 0x80
|
|
800949a: d00a beq.n 80094b2 <USBD_StdEPReq+0xce>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
800949c: 7bbb ldrb r3, [r7, #14]
|
|
800949e: 4619 mov r1, r3
|
|
80094a0: 6878 ldr r0, [r7, #4]
|
|
80094a2: f001 f8e3 bl 800a66c <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
80094a6: 2180 movs r1, #128 @ 0x80
|
|
80094a8: 6878 ldr r0, [r7, #4]
|
|
80094aa: f001 f8df bl 800a66c <USBD_LL_StallEP>
|
|
80094ae: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
80094b0: e020 b.n 80094f4 <USBD_StdEPReq+0x110>
|
|
USBD_CtlError(pdev, req);
|
|
80094b2: 6839 ldr r1, [r7, #0]
|
|
80094b4: 6878 ldr r0, [r7, #4]
|
|
80094b6: f000 fca6 bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
80094ba: e01b b.n 80094f4 <USBD_StdEPReq+0x110>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
80094bc: 683b ldr r3, [r7, #0]
|
|
80094be: 885b ldrh r3, [r3, #2]
|
|
80094c0: 2b00 cmp r3, #0
|
|
80094c2: d10e bne.n 80094e2 <USBD_StdEPReq+0xfe>
|
|
{
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U))
|
|
80094c4: 7bbb ldrb r3, [r7, #14]
|
|
80094c6: 2b00 cmp r3, #0
|
|
80094c8: d00b beq.n 80094e2 <USBD_StdEPReq+0xfe>
|
|
80094ca: 7bbb ldrb r3, [r7, #14]
|
|
80094cc: 2b80 cmp r3, #128 @ 0x80
|
|
80094ce: d008 beq.n 80094e2 <USBD_StdEPReq+0xfe>
|
|
80094d0: 683b ldr r3, [r7, #0]
|
|
80094d2: 88db ldrh r3, [r3, #6]
|
|
80094d4: 2b00 cmp r3, #0
|
|
80094d6: d104 bne.n 80094e2 <USBD_StdEPReq+0xfe>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
80094d8: 7bbb ldrb r3, [r7, #14]
|
|
80094da: 4619 mov r1, r3
|
|
80094dc: 6878 ldr r0, [r7, #4]
|
|
80094de: f001 f8c5 bl 800a66c <USBD_LL_StallEP>
|
|
}
|
|
}
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80094e2: 6878 ldr r0, [r7, #4]
|
|
80094e4: f000 fd4c bl 8009f80 <USBD_CtlSendStatus>
|
|
|
|
break;
|
|
80094e8: e004 b.n 80094f4 <USBD_StdEPReq+0x110>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80094ea: 6839 ldr r1, [r7, #0]
|
|
80094ec: 6878 ldr r0, [r7, #4]
|
|
80094ee: f000 fc8a bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
80094f2: bf00 nop
|
|
}
|
|
break;
|
|
80094f4: e109 b.n 800970a <USBD_StdEPReq+0x326>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
|
|
switch (pdev->dev_state)
|
|
80094f6: 687b ldr r3, [r7, #4]
|
|
80094f8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80094fc: b2db uxtb r3, r3
|
|
80094fe: 2b02 cmp r3, #2
|
|
8009500: d002 beq.n 8009508 <USBD_StdEPReq+0x124>
|
|
8009502: 2b03 cmp r3, #3
|
|
8009504: d016 beq.n 8009534 <USBD_StdEPReq+0x150>
|
|
8009506: e04b b.n 80095a0 <USBD_StdEPReq+0x1bc>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
8009508: 7bbb ldrb r3, [r7, #14]
|
|
800950a: 2b00 cmp r3, #0
|
|
800950c: d00d beq.n 800952a <USBD_StdEPReq+0x146>
|
|
800950e: 7bbb ldrb r3, [r7, #14]
|
|
8009510: 2b80 cmp r3, #128 @ 0x80
|
|
8009512: d00a beq.n 800952a <USBD_StdEPReq+0x146>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
8009514: 7bbb ldrb r3, [r7, #14]
|
|
8009516: 4619 mov r1, r3
|
|
8009518: 6878 ldr r0, [r7, #4]
|
|
800951a: f001 f8a7 bl 800a66c <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
800951e: 2180 movs r1, #128 @ 0x80
|
|
8009520: 6878 ldr r0, [r7, #4]
|
|
8009522: f001 f8a3 bl 800a66c <USBD_LL_StallEP>
|
|
8009526: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
8009528: e040 b.n 80095ac <USBD_StdEPReq+0x1c8>
|
|
USBD_CtlError(pdev, req);
|
|
800952a: 6839 ldr r1, [r7, #0]
|
|
800952c: 6878 ldr r0, [r7, #4]
|
|
800952e: f000 fc6a bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
8009532: e03b b.n 80095ac <USBD_StdEPReq+0x1c8>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
8009534: 683b ldr r3, [r7, #0]
|
|
8009536: 885b ldrh r3, [r3, #2]
|
|
8009538: 2b00 cmp r3, #0
|
|
800953a: d136 bne.n 80095aa <USBD_StdEPReq+0x1c6>
|
|
{
|
|
if ((ep_addr & 0x7FU) != 0x00U)
|
|
800953c: 7bbb ldrb r3, [r7, #14]
|
|
800953e: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8009542: 2b00 cmp r3, #0
|
|
8009544: d004 beq.n 8009550 <USBD_StdEPReq+0x16c>
|
|
{
|
|
(void)USBD_LL_ClearStallEP(pdev, ep_addr);
|
|
8009546: 7bbb ldrb r3, [r7, #14]
|
|
8009548: 4619 mov r1, r3
|
|
800954a: 6878 ldr r0, [r7, #4]
|
|
800954c: f001 f8ad bl 800a6aa <USBD_LL_ClearStallEP>
|
|
}
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009550: 6878 ldr r0, [r7, #4]
|
|
8009552: f000 fd15 bl 8009f80 <USBD_CtlSendStatus>
|
|
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, ep_addr);
|
|
8009556: 7bbb ldrb r3, [r7, #14]
|
|
8009558: 4619 mov r1, r3
|
|
800955a: 6878 ldr r0, [r7, #4]
|
|
800955c: f7ff fde3 bl 8009126 <USBD_CoreFindEP>
|
|
8009560: 4603 mov r3, r0
|
|
8009562: 737b strb r3, [r7, #13]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8009564: 7b7b ldrb r3, [r7, #13]
|
|
8009566: 2bff cmp r3, #255 @ 0xff
|
|
8009568: d01f beq.n 80095aa <USBD_StdEPReq+0x1c6>
|
|
800956a: 7b7b ldrb r3, [r7, #13]
|
|
800956c: 2b00 cmp r3, #0
|
|
800956e: d11c bne.n 80095aa <USBD_StdEPReq+0x1c6>
|
|
{
|
|
pdev->classId = idx;
|
|
8009570: 7b7a ldrb r2, [r7, #13]
|
|
8009572: 687b ldr r3, [r7, #4]
|
|
8009574: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8009578: 7b7a ldrb r2, [r7, #13]
|
|
800957a: 687b ldr r3, [r7, #4]
|
|
800957c: 32ae adds r2, #174 @ 0xae
|
|
800957e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009582: 689b ldr r3, [r3, #8]
|
|
8009584: 2b00 cmp r3, #0
|
|
8009586: d010 beq.n 80095aa <USBD_StdEPReq+0x1c6>
|
|
{
|
|
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
|
|
8009588: 7b7a ldrb r2, [r7, #13]
|
|
800958a: 687b ldr r3, [r7, #4]
|
|
800958c: 32ae adds r2, #174 @ 0xae
|
|
800958e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8009592: 689b ldr r3, [r3, #8]
|
|
8009594: 6839 ldr r1, [r7, #0]
|
|
8009596: 6878 ldr r0, [r7, #4]
|
|
8009598: 4798 blx r3
|
|
800959a: 4603 mov r3, r0
|
|
800959c: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
800959e: e004 b.n 80095aa <USBD_StdEPReq+0x1c6>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80095a0: 6839 ldr r1, [r7, #0]
|
|
80095a2: 6878 ldr r0, [r7, #4]
|
|
80095a4: f000 fc2f bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
80095a8: e000 b.n 80095ac <USBD_StdEPReq+0x1c8>
|
|
break;
|
|
80095aa: bf00 nop
|
|
}
|
|
break;
|
|
80095ac: e0ad b.n 800970a <USBD_StdEPReq+0x326>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
switch (pdev->dev_state)
|
|
80095ae: 687b ldr r3, [r7, #4]
|
|
80095b0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80095b4: b2db uxtb r3, r3
|
|
80095b6: 2b02 cmp r3, #2
|
|
80095b8: d002 beq.n 80095c0 <USBD_StdEPReq+0x1dc>
|
|
80095ba: 2b03 cmp r3, #3
|
|
80095bc: d033 beq.n 8009626 <USBD_StdEPReq+0x242>
|
|
80095be: e099 b.n 80096f4 <USBD_StdEPReq+0x310>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
80095c0: 7bbb ldrb r3, [r7, #14]
|
|
80095c2: 2b00 cmp r3, #0
|
|
80095c4: d007 beq.n 80095d6 <USBD_StdEPReq+0x1f2>
|
|
80095c6: 7bbb ldrb r3, [r7, #14]
|
|
80095c8: 2b80 cmp r3, #128 @ 0x80
|
|
80095ca: d004 beq.n 80095d6 <USBD_StdEPReq+0x1f2>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80095cc: 6839 ldr r1, [r7, #0]
|
|
80095ce: 6878 ldr r0, [r7, #4]
|
|
80095d0: f000 fc19 bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
80095d4: e093 b.n 80096fe <USBD_StdEPReq+0x31a>
|
|
}
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
80095d6: f997 300e ldrsb.w r3, [r7, #14]
|
|
80095da: 2b00 cmp r3, #0
|
|
80095dc: da0b bge.n 80095f6 <USBD_StdEPReq+0x212>
|
|
80095de: 7bbb ldrb r3, [r7, #14]
|
|
80095e0: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
80095e4: 4613 mov r3, r2
|
|
80095e6: 009b lsls r3, r3, #2
|
|
80095e8: 4413 add r3, r2
|
|
80095ea: 009b lsls r3, r3, #2
|
|
80095ec: 3310 adds r3, #16
|
|
80095ee: 687a ldr r2, [r7, #4]
|
|
80095f0: 4413 add r3, r2
|
|
80095f2: 3304 adds r3, #4
|
|
80095f4: e00b b.n 800960e <USBD_StdEPReq+0x22a>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
80095f6: 7bbb ldrb r3, [r7, #14]
|
|
80095f8: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
80095fc: 4613 mov r3, r2
|
|
80095fe: 009b lsls r3, r3, #2
|
|
8009600: 4413 add r3, r2
|
|
8009602: 009b lsls r3, r3, #2
|
|
8009604: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8009608: 687a ldr r2, [r7, #4]
|
|
800960a: 4413 add r3, r2
|
|
800960c: 3304 adds r3, #4
|
|
800960e: 60bb str r3, [r7, #8]
|
|
|
|
pep->status = 0x0000U;
|
|
8009610: 68bb ldr r3, [r7, #8]
|
|
8009612: 2200 movs r2, #0
|
|
8009614: 739a strb r2, [r3, #14]
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
|
|
8009616: 68bb ldr r3, [r7, #8]
|
|
8009618: 330e adds r3, #14
|
|
800961a: 2202 movs r2, #2
|
|
800961c: 4619 mov r1, r3
|
|
800961e: 6878 ldr r0, [r7, #4]
|
|
8009620: f000 fc6e bl 8009f00 <USBD_CtlSendData>
|
|
break;
|
|
8009624: e06b b.n 80096fe <USBD_StdEPReq+0x31a>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8009626: f997 300e ldrsb.w r3, [r7, #14]
|
|
800962a: 2b00 cmp r3, #0
|
|
800962c: da11 bge.n 8009652 <USBD_StdEPReq+0x26e>
|
|
{
|
|
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
|
|
800962e: 7bbb ldrb r3, [r7, #14]
|
|
8009630: f003 020f and.w r2, r3, #15
|
|
8009634: 6879 ldr r1, [r7, #4]
|
|
8009636: 4613 mov r3, r2
|
|
8009638: 009b lsls r3, r3, #2
|
|
800963a: 4413 add r3, r2
|
|
800963c: 009b lsls r3, r3, #2
|
|
800963e: 440b add r3, r1
|
|
8009640: 3323 adds r3, #35 @ 0x23
|
|
8009642: 781b ldrb r3, [r3, #0]
|
|
8009644: 2b00 cmp r3, #0
|
|
8009646: d117 bne.n 8009678 <USBD_StdEPReq+0x294>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009648: 6839 ldr r1, [r7, #0]
|
|
800964a: 6878 ldr r0, [r7, #4]
|
|
800964c: f000 fbdb bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
8009650: e055 b.n 80096fe <USBD_StdEPReq+0x31a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
|
|
8009652: 7bbb ldrb r3, [r7, #14]
|
|
8009654: f003 020f and.w r2, r3, #15
|
|
8009658: 6879 ldr r1, [r7, #4]
|
|
800965a: 4613 mov r3, r2
|
|
800965c: 009b lsls r3, r3, #2
|
|
800965e: 4413 add r3, r2
|
|
8009660: 009b lsls r3, r3, #2
|
|
8009662: 440b add r3, r1
|
|
8009664: f203 1363 addw r3, r3, #355 @ 0x163
|
|
8009668: 781b ldrb r3, [r3, #0]
|
|
800966a: 2b00 cmp r3, #0
|
|
800966c: d104 bne.n 8009678 <USBD_StdEPReq+0x294>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
800966e: 6839 ldr r1, [r7, #0]
|
|
8009670: 6878 ldr r0, [r7, #4]
|
|
8009672: f000 fbc8 bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
8009676: e042 b.n 80096fe <USBD_StdEPReq+0x31a>
|
|
}
|
|
}
|
|
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
8009678: f997 300e ldrsb.w r3, [r7, #14]
|
|
800967c: 2b00 cmp r3, #0
|
|
800967e: da0b bge.n 8009698 <USBD_StdEPReq+0x2b4>
|
|
8009680: 7bbb ldrb r3, [r7, #14]
|
|
8009682: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
8009686: 4613 mov r3, r2
|
|
8009688: 009b lsls r3, r3, #2
|
|
800968a: 4413 add r3, r2
|
|
800968c: 009b lsls r3, r3, #2
|
|
800968e: 3310 adds r3, #16
|
|
8009690: 687a ldr r2, [r7, #4]
|
|
8009692: 4413 add r3, r2
|
|
8009694: 3304 adds r3, #4
|
|
8009696: e00b b.n 80096b0 <USBD_StdEPReq+0x2cc>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
8009698: 7bbb ldrb r3, [r7, #14]
|
|
800969a: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
800969e: 4613 mov r3, r2
|
|
80096a0: 009b lsls r3, r3, #2
|
|
80096a2: 4413 add r3, r2
|
|
80096a4: 009b lsls r3, r3, #2
|
|
80096a6: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
80096aa: 687a ldr r2, [r7, #4]
|
|
80096ac: 4413 add r3, r2
|
|
80096ae: 3304 adds r3, #4
|
|
80096b0: 60bb str r3, [r7, #8]
|
|
|
|
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
|
|
80096b2: 7bbb ldrb r3, [r7, #14]
|
|
80096b4: 2b00 cmp r3, #0
|
|
80096b6: d002 beq.n 80096be <USBD_StdEPReq+0x2da>
|
|
80096b8: 7bbb ldrb r3, [r7, #14]
|
|
80096ba: 2b80 cmp r3, #128 @ 0x80
|
|
80096bc: d103 bne.n 80096c6 <USBD_StdEPReq+0x2e2>
|
|
{
|
|
pep->status = 0x0000U;
|
|
80096be: 68bb ldr r3, [r7, #8]
|
|
80096c0: 2200 movs r2, #0
|
|
80096c2: 739a strb r2, [r3, #14]
|
|
80096c4: e00e b.n 80096e4 <USBD_StdEPReq+0x300>
|
|
}
|
|
else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U)
|
|
80096c6: 7bbb ldrb r3, [r7, #14]
|
|
80096c8: 4619 mov r1, r3
|
|
80096ca: 6878 ldr r0, [r7, #4]
|
|
80096cc: f001 f80c bl 800a6e8 <USBD_LL_IsStallEP>
|
|
80096d0: 4603 mov r3, r0
|
|
80096d2: 2b00 cmp r3, #0
|
|
80096d4: d003 beq.n 80096de <USBD_StdEPReq+0x2fa>
|
|
{
|
|
pep->status = 0x0001U;
|
|
80096d6: 68bb ldr r3, [r7, #8]
|
|
80096d8: 2201 movs r2, #1
|
|
80096da: 739a strb r2, [r3, #14]
|
|
80096dc: e002 b.n 80096e4 <USBD_StdEPReq+0x300>
|
|
}
|
|
else
|
|
{
|
|
pep->status = 0x0000U;
|
|
80096de: 68bb ldr r3, [r7, #8]
|
|
80096e0: 2200 movs r2, #0
|
|
80096e2: 739a strb r2, [r3, #14]
|
|
}
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
|
|
80096e4: 68bb ldr r3, [r7, #8]
|
|
80096e6: 330e adds r3, #14
|
|
80096e8: 2202 movs r2, #2
|
|
80096ea: 4619 mov r1, r3
|
|
80096ec: 6878 ldr r0, [r7, #4]
|
|
80096ee: f000 fc07 bl 8009f00 <USBD_CtlSendData>
|
|
break;
|
|
80096f2: e004 b.n 80096fe <USBD_StdEPReq+0x31a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80096f4: 6839 ldr r1, [r7, #0]
|
|
80096f6: 6878 ldr r0, [r7, #4]
|
|
80096f8: f000 fb85 bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
80096fc: bf00 nop
|
|
}
|
|
break;
|
|
80096fe: e004 b.n 800970a <USBD_StdEPReq+0x326>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8009700: 6839 ldr r1, [r7, #0]
|
|
8009702: 6878 ldr r0, [r7, #4]
|
|
8009704: f000 fb7f bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
8009708: bf00 nop
|
|
}
|
|
break;
|
|
800970a: e005 b.n 8009718 <USBD_StdEPReq+0x334>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
800970c: 6839 ldr r1, [r7, #0]
|
|
800970e: 6878 ldr r0, [r7, #4]
|
|
8009710: f000 fb79 bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
8009714: e000 b.n 8009718 <USBD_StdEPReq+0x334>
|
|
break;
|
|
8009716: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8009718: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800971a: 4618 mov r0, r3
|
|
800971c: 3710 adds r7, #16
|
|
800971e: 46bd mov sp, r7
|
|
8009720: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08009724 <USBD_GetDescriptor>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009724: b580 push {r7, lr}
|
|
8009726: b084 sub sp, #16
|
|
8009728: af00 add r7, sp, #0
|
|
800972a: 6078 str r0, [r7, #4]
|
|
800972c: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
800972e: 2300 movs r3, #0
|
|
8009730: 813b strh r3, [r7, #8]
|
|
uint8_t *pbuf = NULL;
|
|
8009732: 2300 movs r3, #0
|
|
8009734: 60fb str r3, [r7, #12]
|
|
uint8_t err = 0U;
|
|
8009736: 2300 movs r3, #0
|
|
8009738: 72fb strb r3, [r7, #11]
|
|
|
|
switch (req->wValue >> 8)
|
|
800973a: 683b ldr r3, [r7, #0]
|
|
800973c: 885b ldrh r3, [r3, #2]
|
|
800973e: 0a1b lsrs r3, r3, #8
|
|
8009740: b29b uxth r3, r3
|
|
8009742: 3b01 subs r3, #1
|
|
8009744: 2b0e cmp r3, #14
|
|
8009746: f200 8152 bhi.w 80099ee <USBD_GetDescriptor+0x2ca>
|
|
800974a: a201 add r2, pc, #4 @ (adr r2, 8009750 <USBD_GetDescriptor+0x2c>)
|
|
800974c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8009750: 080097c1 .word 0x080097c1
|
|
8009754: 080097d9 .word 0x080097d9
|
|
8009758: 08009819 .word 0x08009819
|
|
800975c: 080099ef .word 0x080099ef
|
|
8009760: 080099ef .word 0x080099ef
|
|
8009764: 0800998f .word 0x0800998f
|
|
8009768: 080099bb .word 0x080099bb
|
|
800976c: 080099ef .word 0x080099ef
|
|
8009770: 080099ef .word 0x080099ef
|
|
8009774: 080099ef .word 0x080099ef
|
|
8009778: 080099ef .word 0x080099ef
|
|
800977c: 080099ef .word 0x080099ef
|
|
8009780: 080099ef .word 0x080099ef
|
|
8009784: 080099ef .word 0x080099ef
|
|
8009788: 0800978d .word 0x0800978d
|
|
{
|
|
#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U))
|
|
case USB_DESC_TYPE_BOS:
|
|
if (pdev->pDesc->GetBOSDescriptor != NULL)
|
|
800978c: 687b ldr r3, [r7, #4]
|
|
800978e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009792: 69db ldr r3, [r3, #28]
|
|
8009794: 2b00 cmp r3, #0
|
|
8009796: d00b beq.n 80097b0 <USBD_GetDescriptor+0x8c>
|
|
{
|
|
pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
|
|
8009798: 687b ldr r3, [r7, #4]
|
|
800979a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800979e: 69db ldr r3, [r3, #28]
|
|
80097a0: 687a ldr r2, [r7, #4]
|
|
80097a2: 7c12 ldrb r2, [r2, #16]
|
|
80097a4: f107 0108 add.w r1, r7, #8
|
|
80097a8: 4610 mov r0, r2
|
|
80097aa: 4798 blx r3
|
|
80097ac: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80097ae: e126 b.n 80099fe <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
80097b0: 6839 ldr r1, [r7, #0]
|
|
80097b2: 6878 ldr r0, [r7, #4]
|
|
80097b4: f000 fb27 bl 8009e06 <USBD_CtlError>
|
|
err++;
|
|
80097b8: 7afb ldrb r3, [r7, #11]
|
|
80097ba: 3301 adds r3, #1
|
|
80097bc: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80097be: e11e b.n 80099fe <USBD_GetDescriptor+0x2da>
|
|
#endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */
|
|
case USB_DESC_TYPE_DEVICE:
|
|
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
|
|
80097c0: 687b ldr r3, [r7, #4]
|
|
80097c2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80097c6: 681b ldr r3, [r3, #0]
|
|
80097c8: 687a ldr r2, [r7, #4]
|
|
80097ca: 7c12 ldrb r2, [r2, #16]
|
|
80097cc: f107 0108 add.w r1, r7, #8
|
|
80097d0: 4610 mov r0, r2
|
|
80097d2: 4798 blx r3
|
|
80097d4: 60f8 str r0, [r7, #12]
|
|
break;
|
|
80097d6: e112 b.n 80099fe <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
80097d8: 687b ldr r3, [r7, #4]
|
|
80097da: 7c1b ldrb r3, [r3, #16]
|
|
80097dc: 2b00 cmp r3, #0
|
|
80097de: d10d bne.n 80097fc <USBD_GetDescriptor+0xd8>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len);
|
|
80097e0: 687b ldr r3, [r7, #4]
|
|
80097e2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80097e6: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80097e8: f107 0208 add.w r2, r7, #8
|
|
80097ec: 4610 mov r0, r2
|
|
80097ee: 4798 blx r3
|
|
80097f0: 60f8 str r0, [r7, #12]
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
80097f2: 68fb ldr r3, [r7, #12]
|
|
80097f4: 3301 adds r3, #1
|
|
80097f6: 2202 movs r2, #2
|
|
80097f8: 701a strb r2, [r3, #0]
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
}
|
|
break;
|
|
80097fa: e100 b.n 80099fe <USBD_GetDescriptor+0x2da>
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
|
|
80097fc: 687b ldr r3, [r7, #4]
|
|
80097fe: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8009802: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8009804: f107 0208 add.w r2, r7, #8
|
|
8009808: 4610 mov r0, r2
|
|
800980a: 4798 blx r3
|
|
800980c: 60f8 str r0, [r7, #12]
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
800980e: 68fb ldr r3, [r7, #12]
|
|
8009810: 3301 adds r3, #1
|
|
8009812: 2202 movs r2, #2
|
|
8009814: 701a strb r2, [r3, #0]
|
|
break;
|
|
8009816: e0f2 b.n 80099fe <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_STRING:
|
|
switch ((uint8_t)(req->wValue))
|
|
8009818: 683b ldr r3, [r7, #0]
|
|
800981a: 885b ldrh r3, [r3, #2]
|
|
800981c: b2db uxtb r3, r3
|
|
800981e: 2b05 cmp r3, #5
|
|
8009820: f200 80ac bhi.w 800997c <USBD_GetDescriptor+0x258>
|
|
8009824: a201 add r2, pc, #4 @ (adr r2, 800982c <USBD_GetDescriptor+0x108>)
|
|
8009826: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800982a: bf00 nop
|
|
800982c: 08009845 .word 0x08009845
|
|
8009830: 08009879 .word 0x08009879
|
|
8009834: 080098ad .word 0x080098ad
|
|
8009838: 080098e1 .word 0x080098e1
|
|
800983c: 08009915 .word 0x08009915
|
|
8009840: 08009949 .word 0x08009949
|
|
{
|
|
case USBD_IDX_LANGID_STR:
|
|
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
|
|
8009844: 687b ldr r3, [r7, #4]
|
|
8009846: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800984a: 685b ldr r3, [r3, #4]
|
|
800984c: 2b00 cmp r3, #0
|
|
800984e: d00b beq.n 8009868 <USBD_GetDescriptor+0x144>
|
|
{
|
|
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
|
|
8009850: 687b ldr r3, [r7, #4]
|
|
8009852: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009856: 685b ldr r3, [r3, #4]
|
|
8009858: 687a ldr r2, [r7, #4]
|
|
800985a: 7c12 ldrb r2, [r2, #16]
|
|
800985c: f107 0108 add.w r1, r7, #8
|
|
8009860: 4610 mov r0, r2
|
|
8009862: 4798 blx r3
|
|
8009864: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8009866: e091 b.n 800998c <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8009868: 6839 ldr r1, [r7, #0]
|
|
800986a: 6878 ldr r0, [r7, #4]
|
|
800986c: f000 facb bl 8009e06 <USBD_CtlError>
|
|
err++;
|
|
8009870: 7afb ldrb r3, [r7, #11]
|
|
8009872: 3301 adds r3, #1
|
|
8009874: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009876: e089 b.n 800998c <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_MFC_STR:
|
|
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
|
|
8009878: 687b ldr r3, [r7, #4]
|
|
800987a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800987e: 689b ldr r3, [r3, #8]
|
|
8009880: 2b00 cmp r3, #0
|
|
8009882: d00b beq.n 800989c <USBD_GetDescriptor+0x178>
|
|
{
|
|
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
|
|
8009884: 687b ldr r3, [r7, #4]
|
|
8009886: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800988a: 689b ldr r3, [r3, #8]
|
|
800988c: 687a ldr r2, [r7, #4]
|
|
800988e: 7c12 ldrb r2, [r2, #16]
|
|
8009890: f107 0108 add.w r1, r7, #8
|
|
8009894: 4610 mov r0, r2
|
|
8009896: 4798 blx r3
|
|
8009898: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800989a: e077 b.n 800998c <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
800989c: 6839 ldr r1, [r7, #0]
|
|
800989e: 6878 ldr r0, [r7, #4]
|
|
80098a0: f000 fab1 bl 8009e06 <USBD_CtlError>
|
|
err++;
|
|
80098a4: 7afb ldrb r3, [r7, #11]
|
|
80098a6: 3301 adds r3, #1
|
|
80098a8: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80098aa: e06f b.n 800998c <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_PRODUCT_STR:
|
|
if (pdev->pDesc->GetProductStrDescriptor != NULL)
|
|
80098ac: 687b ldr r3, [r7, #4]
|
|
80098ae: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80098b2: 68db ldr r3, [r3, #12]
|
|
80098b4: 2b00 cmp r3, #0
|
|
80098b6: d00b beq.n 80098d0 <USBD_GetDescriptor+0x1ac>
|
|
{
|
|
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
|
|
80098b8: 687b ldr r3, [r7, #4]
|
|
80098ba: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80098be: 68db ldr r3, [r3, #12]
|
|
80098c0: 687a ldr r2, [r7, #4]
|
|
80098c2: 7c12 ldrb r2, [r2, #16]
|
|
80098c4: f107 0108 add.w r1, r7, #8
|
|
80098c8: 4610 mov r0, r2
|
|
80098ca: 4798 blx r3
|
|
80098cc: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80098ce: e05d b.n 800998c <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
80098d0: 6839 ldr r1, [r7, #0]
|
|
80098d2: 6878 ldr r0, [r7, #4]
|
|
80098d4: f000 fa97 bl 8009e06 <USBD_CtlError>
|
|
err++;
|
|
80098d8: 7afb ldrb r3, [r7, #11]
|
|
80098da: 3301 adds r3, #1
|
|
80098dc: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80098de: e055 b.n 800998c <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_SERIAL_STR:
|
|
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
|
|
80098e0: 687b ldr r3, [r7, #4]
|
|
80098e2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80098e6: 691b ldr r3, [r3, #16]
|
|
80098e8: 2b00 cmp r3, #0
|
|
80098ea: d00b beq.n 8009904 <USBD_GetDescriptor+0x1e0>
|
|
{
|
|
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
|
|
80098ec: 687b ldr r3, [r7, #4]
|
|
80098ee: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80098f2: 691b ldr r3, [r3, #16]
|
|
80098f4: 687a ldr r2, [r7, #4]
|
|
80098f6: 7c12 ldrb r2, [r2, #16]
|
|
80098f8: f107 0108 add.w r1, r7, #8
|
|
80098fc: 4610 mov r0, r2
|
|
80098fe: 4798 blx r3
|
|
8009900: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8009902: e043 b.n 800998c <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8009904: 6839 ldr r1, [r7, #0]
|
|
8009906: 6878 ldr r0, [r7, #4]
|
|
8009908: f000 fa7d bl 8009e06 <USBD_CtlError>
|
|
err++;
|
|
800990c: 7afb ldrb r3, [r7, #11]
|
|
800990e: 3301 adds r3, #1
|
|
8009910: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009912: e03b b.n 800998c <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_CONFIG_STR:
|
|
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
|
|
8009914: 687b ldr r3, [r7, #4]
|
|
8009916: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800991a: 695b ldr r3, [r3, #20]
|
|
800991c: 2b00 cmp r3, #0
|
|
800991e: d00b beq.n 8009938 <USBD_GetDescriptor+0x214>
|
|
{
|
|
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
|
|
8009920: 687b ldr r3, [r7, #4]
|
|
8009922: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8009926: 695b ldr r3, [r3, #20]
|
|
8009928: 687a ldr r2, [r7, #4]
|
|
800992a: 7c12 ldrb r2, [r2, #16]
|
|
800992c: f107 0108 add.w r1, r7, #8
|
|
8009930: 4610 mov r0, r2
|
|
8009932: 4798 blx r3
|
|
8009934: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8009936: e029 b.n 800998c <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8009938: 6839 ldr r1, [r7, #0]
|
|
800993a: 6878 ldr r0, [r7, #4]
|
|
800993c: f000 fa63 bl 8009e06 <USBD_CtlError>
|
|
err++;
|
|
8009940: 7afb ldrb r3, [r7, #11]
|
|
8009942: 3301 adds r3, #1
|
|
8009944: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8009946: e021 b.n 800998c <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_INTERFACE_STR:
|
|
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
|
|
8009948: 687b ldr r3, [r7, #4]
|
|
800994a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800994e: 699b ldr r3, [r3, #24]
|
|
8009950: 2b00 cmp r3, #0
|
|
8009952: d00b beq.n 800996c <USBD_GetDescriptor+0x248>
|
|
{
|
|
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
|
|
8009954: 687b ldr r3, [r7, #4]
|
|
8009956: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
800995a: 699b ldr r3, [r3, #24]
|
|
800995c: 687a ldr r2, [r7, #4]
|
|
800995e: 7c12 ldrb r2, [r2, #16]
|
|
8009960: f107 0108 add.w r1, r7, #8
|
|
8009964: 4610 mov r0, r2
|
|
8009966: 4798 blx r3
|
|
8009968: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
800996a: e00f b.n 800998c <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
800996c: 6839 ldr r1, [r7, #0]
|
|
800996e: 6878 ldr r0, [r7, #4]
|
|
8009970: f000 fa49 bl 8009e06 <USBD_CtlError>
|
|
err++;
|
|
8009974: 7afb ldrb r3, [r7, #11]
|
|
8009976: 3301 adds r3, #1
|
|
8009978: 72fb strb r3, [r7, #11]
|
|
break;
|
|
800997a: e007 b.n 800998c <USBD_GetDescriptor+0x268>
|
|
err++;
|
|
}
|
|
#endif /* USBD_SUPPORT_USER_STRING_DESC */
|
|
|
|
#if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U))
|
|
USBD_CtlError(pdev, req);
|
|
800997c: 6839 ldr r1, [r7, #0]
|
|
800997e: 6878 ldr r0, [r7, #4]
|
|
8009980: f000 fa41 bl 8009e06 <USBD_CtlError>
|
|
err++;
|
|
8009984: 7afb ldrb r3, [r7, #11]
|
|
8009986: 3301 adds r3, #1
|
|
8009988: 72fb strb r3, [r7, #11]
|
|
#endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */
|
|
break;
|
|
800998a: bf00 nop
|
|
}
|
|
break;
|
|
800998c: e037 b.n 80099fe <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_DEVICE_QUALIFIER:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
800998e: 687b ldr r3, [r7, #4]
|
|
8009990: 7c1b ldrb r3, [r3, #16]
|
|
8009992: 2b00 cmp r3, #0
|
|
8009994: d109 bne.n 80099aa <USBD_GetDescriptor+0x286>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len);
|
|
8009996: 687b ldr r3, [r7, #4]
|
|
8009998: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
800999c: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800999e: f107 0208 add.w r2, r7, #8
|
|
80099a2: 4610 mov r0, r2
|
|
80099a4: 4798 blx r3
|
|
80099a6: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80099a8: e029 b.n 80099fe <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
80099aa: 6839 ldr r1, [r7, #0]
|
|
80099ac: 6878 ldr r0, [r7, #4]
|
|
80099ae: f000 fa2a bl 8009e06 <USBD_CtlError>
|
|
err++;
|
|
80099b2: 7afb ldrb r3, [r7, #11]
|
|
80099b4: 3301 adds r3, #1
|
|
80099b6: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80099b8: e021 b.n 80099fe <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
80099ba: 687b ldr r3, [r7, #4]
|
|
80099bc: 7c1b ldrb r3, [r3, #16]
|
|
80099be: 2b00 cmp r3, #0
|
|
80099c0: d10d bne.n 80099de <USBD_GetDescriptor+0x2ba>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len);
|
|
80099c2: 687b ldr r3, [r7, #4]
|
|
80099c4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80099c8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80099ca: f107 0208 add.w r2, r7, #8
|
|
80099ce: 4610 mov r0, r2
|
|
80099d0: 4798 blx r3
|
|
80099d2: 60f8 str r0, [r7, #12]
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
|
|
80099d4: 68fb ldr r3, [r7, #12]
|
|
80099d6: 3301 adds r3, #1
|
|
80099d8: 2207 movs r2, #7
|
|
80099da: 701a strb r2, [r3, #0]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80099dc: e00f b.n 80099fe <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
80099de: 6839 ldr r1, [r7, #0]
|
|
80099e0: 6878 ldr r0, [r7, #4]
|
|
80099e2: f000 fa10 bl 8009e06 <USBD_CtlError>
|
|
err++;
|
|
80099e6: 7afb ldrb r3, [r7, #11]
|
|
80099e8: 3301 adds r3, #1
|
|
80099ea: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80099ec: e007 b.n 80099fe <USBD_GetDescriptor+0x2da>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80099ee: 6839 ldr r1, [r7, #0]
|
|
80099f0: 6878 ldr r0, [r7, #4]
|
|
80099f2: f000 fa08 bl 8009e06 <USBD_CtlError>
|
|
err++;
|
|
80099f6: 7afb ldrb r3, [r7, #11]
|
|
80099f8: 3301 adds r3, #1
|
|
80099fa: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80099fc: bf00 nop
|
|
}
|
|
|
|
if (err != 0U)
|
|
80099fe: 7afb ldrb r3, [r7, #11]
|
|
8009a00: 2b00 cmp r3, #0
|
|
8009a02: d11e bne.n 8009a42 <USBD_GetDescriptor+0x31e>
|
|
{
|
|
return;
|
|
}
|
|
|
|
if (req->wLength != 0U)
|
|
8009a04: 683b ldr r3, [r7, #0]
|
|
8009a06: 88db ldrh r3, [r3, #6]
|
|
8009a08: 2b00 cmp r3, #0
|
|
8009a0a: d016 beq.n 8009a3a <USBD_GetDescriptor+0x316>
|
|
{
|
|
if (len != 0U)
|
|
8009a0c: 893b ldrh r3, [r7, #8]
|
|
8009a0e: 2b00 cmp r3, #0
|
|
8009a10: d00e beq.n 8009a30 <USBD_GetDescriptor+0x30c>
|
|
{
|
|
len = MIN(len, req->wLength);
|
|
8009a12: 683b ldr r3, [r7, #0]
|
|
8009a14: 88da ldrh r2, [r3, #6]
|
|
8009a16: 893b ldrh r3, [r7, #8]
|
|
8009a18: 4293 cmp r3, r2
|
|
8009a1a: bf28 it cs
|
|
8009a1c: 4613 movcs r3, r2
|
|
8009a1e: b29b uxth r3, r3
|
|
8009a20: 813b strh r3, [r7, #8]
|
|
(void)USBD_CtlSendData(pdev, pbuf, len);
|
|
8009a22: 893b ldrh r3, [r7, #8]
|
|
8009a24: 461a mov r2, r3
|
|
8009a26: 68f9 ldr r1, [r7, #12]
|
|
8009a28: 6878 ldr r0, [r7, #4]
|
|
8009a2a: f000 fa69 bl 8009f00 <USBD_CtlSendData>
|
|
8009a2e: e009 b.n 8009a44 <USBD_GetDescriptor+0x320>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009a30: 6839 ldr r1, [r7, #0]
|
|
8009a32: 6878 ldr r0, [r7, #4]
|
|
8009a34: f000 f9e7 bl 8009e06 <USBD_CtlError>
|
|
8009a38: e004 b.n 8009a44 <USBD_GetDescriptor+0x320>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009a3a: 6878 ldr r0, [r7, #4]
|
|
8009a3c: f000 faa0 bl 8009f80 <USBD_CtlSendStatus>
|
|
8009a40: e000 b.n 8009a44 <USBD_GetDescriptor+0x320>
|
|
return;
|
|
8009a42: bf00 nop
|
|
}
|
|
}
|
|
8009a44: 3710 adds r7, #16
|
|
8009a46: 46bd mov sp, r7
|
|
8009a48: bd80 pop {r7, pc}
|
|
8009a4a: bf00 nop
|
|
|
|
08009a4c <USBD_SetAddress>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009a4c: b580 push {r7, lr}
|
|
8009a4e: b084 sub sp, #16
|
|
8009a50: af00 add r7, sp, #0
|
|
8009a52: 6078 str r0, [r7, #4]
|
|
8009a54: 6039 str r1, [r7, #0]
|
|
uint8_t dev_addr;
|
|
|
|
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
|
|
8009a56: 683b ldr r3, [r7, #0]
|
|
8009a58: 889b ldrh r3, [r3, #4]
|
|
8009a5a: 2b00 cmp r3, #0
|
|
8009a5c: d131 bne.n 8009ac2 <USBD_SetAddress+0x76>
|
|
8009a5e: 683b ldr r3, [r7, #0]
|
|
8009a60: 88db ldrh r3, [r3, #6]
|
|
8009a62: 2b00 cmp r3, #0
|
|
8009a64: d12d bne.n 8009ac2 <USBD_SetAddress+0x76>
|
|
8009a66: 683b ldr r3, [r7, #0]
|
|
8009a68: 885b ldrh r3, [r3, #2]
|
|
8009a6a: 2b7f cmp r3, #127 @ 0x7f
|
|
8009a6c: d829 bhi.n 8009ac2 <USBD_SetAddress+0x76>
|
|
{
|
|
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
|
|
8009a6e: 683b ldr r3, [r7, #0]
|
|
8009a70: 885b ldrh r3, [r3, #2]
|
|
8009a72: b2db uxtb r3, r3
|
|
8009a74: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8009a78: 73fb strb r3, [r7, #15]
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8009a7a: 687b ldr r3, [r7, #4]
|
|
8009a7c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009a80: b2db uxtb r3, r3
|
|
8009a82: 2b03 cmp r3, #3
|
|
8009a84: d104 bne.n 8009a90 <USBD_SetAddress+0x44>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009a86: 6839 ldr r1, [r7, #0]
|
|
8009a88: 6878 ldr r0, [r7, #4]
|
|
8009a8a: f000 f9bc bl 8009e06 <USBD_CtlError>
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8009a8e: e01d b.n 8009acc <USBD_SetAddress+0x80>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_address = dev_addr;
|
|
8009a90: 687b ldr r3, [r7, #4]
|
|
8009a92: 7bfa ldrb r2, [r7, #15]
|
|
8009a94: f883 229e strb.w r2, [r3, #670] @ 0x29e
|
|
(void)USBD_LL_SetUSBAddress(pdev, dev_addr);
|
|
8009a98: 7bfb ldrb r3, [r7, #15]
|
|
8009a9a: 4619 mov r1, r3
|
|
8009a9c: 6878 ldr r0, [r7, #4]
|
|
8009a9e: f000 fe4f bl 800a740 <USBD_LL_SetUSBAddress>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009aa2: 6878 ldr r0, [r7, #4]
|
|
8009aa4: f000 fa6c bl 8009f80 <USBD_CtlSendStatus>
|
|
|
|
if (dev_addr != 0U)
|
|
8009aa8: 7bfb ldrb r3, [r7, #15]
|
|
8009aaa: 2b00 cmp r3, #0
|
|
8009aac: d004 beq.n 8009ab8 <USBD_SetAddress+0x6c>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8009aae: 687b ldr r3, [r7, #4]
|
|
8009ab0: 2202 movs r2, #2
|
|
8009ab2: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8009ab6: e009 b.n 8009acc <USBD_SetAddress+0x80>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8009ab8: 687b ldr r3, [r7, #4]
|
|
8009aba: 2201 movs r2, #1
|
|
8009abc: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8009ac0: e004 b.n 8009acc <USBD_SetAddress+0x80>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009ac2: 6839 ldr r1, [r7, #0]
|
|
8009ac4: 6878 ldr r0, [r7, #4]
|
|
8009ac6: f000 f99e bl 8009e06 <USBD_CtlError>
|
|
}
|
|
}
|
|
8009aca: bf00 nop
|
|
8009acc: bf00 nop
|
|
8009ace: 3710 adds r7, #16
|
|
8009ad0: 46bd mov sp, r7
|
|
8009ad2: bd80 pop {r7, pc}
|
|
|
|
08009ad4 <USBD_SetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009ad4: b580 push {r7, lr}
|
|
8009ad6: b084 sub sp, #16
|
|
8009ad8: af00 add r7, sp, #0
|
|
8009ada: 6078 str r0, [r7, #4]
|
|
8009adc: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8009ade: 2300 movs r3, #0
|
|
8009ae0: 73fb strb r3, [r7, #15]
|
|
static uint8_t cfgidx;
|
|
|
|
cfgidx = (uint8_t)(req->wValue);
|
|
8009ae2: 683b ldr r3, [r7, #0]
|
|
8009ae4: 885b ldrh r3, [r3, #2]
|
|
8009ae6: b2da uxtb r2, r3
|
|
8009ae8: 4b4e ldr r3, [pc, #312] @ (8009c24 <USBD_SetConfig+0x150>)
|
|
8009aea: 701a strb r2, [r3, #0]
|
|
|
|
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
|
|
8009aec: 4b4d ldr r3, [pc, #308] @ (8009c24 <USBD_SetConfig+0x150>)
|
|
8009aee: 781b ldrb r3, [r3, #0]
|
|
8009af0: 2b01 cmp r3, #1
|
|
8009af2: d905 bls.n 8009b00 <USBD_SetConfig+0x2c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009af4: 6839 ldr r1, [r7, #0]
|
|
8009af6: 6878 ldr r0, [r7, #4]
|
|
8009af8: f000 f985 bl 8009e06 <USBD_CtlError>
|
|
return USBD_FAIL;
|
|
8009afc: 2303 movs r3, #3
|
|
8009afe: e08c b.n 8009c1a <USBD_SetConfig+0x146>
|
|
}
|
|
|
|
switch (pdev->dev_state)
|
|
8009b00: 687b ldr r3, [r7, #4]
|
|
8009b02: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009b06: b2db uxtb r3, r3
|
|
8009b08: 2b02 cmp r3, #2
|
|
8009b0a: d002 beq.n 8009b12 <USBD_SetConfig+0x3e>
|
|
8009b0c: 2b03 cmp r3, #3
|
|
8009b0e: d029 beq.n 8009b64 <USBD_SetConfig+0x90>
|
|
8009b10: e075 b.n 8009bfe <USBD_SetConfig+0x12a>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if (cfgidx != 0U)
|
|
8009b12: 4b44 ldr r3, [pc, #272] @ (8009c24 <USBD_SetConfig+0x150>)
|
|
8009b14: 781b ldrb r3, [r3, #0]
|
|
8009b16: 2b00 cmp r3, #0
|
|
8009b18: d020 beq.n 8009b5c <USBD_SetConfig+0x88>
|
|
{
|
|
pdev->dev_config = cfgidx;
|
|
8009b1a: 4b42 ldr r3, [pc, #264] @ (8009c24 <USBD_SetConfig+0x150>)
|
|
8009b1c: 781b ldrb r3, [r3, #0]
|
|
8009b1e: 461a mov r2, r3
|
|
8009b20: 687b ldr r3, [r7, #4]
|
|
8009b22: 605a str r2, [r3, #4]
|
|
|
|
ret = USBD_SetClassConfig(pdev, cfgidx);
|
|
8009b24: 4b3f ldr r3, [pc, #252] @ (8009c24 <USBD_SetConfig+0x150>)
|
|
8009b26: 781b ldrb r3, [r3, #0]
|
|
8009b28: 4619 mov r1, r3
|
|
8009b2a: 6878 ldr r0, [r7, #4]
|
|
8009b2c: f7fe ffa3 bl 8008a76 <USBD_SetClassConfig>
|
|
8009b30: 4603 mov r3, r0
|
|
8009b32: 73fb strb r3, [r7, #15]
|
|
|
|
if (ret != USBD_OK)
|
|
8009b34: 7bfb ldrb r3, [r7, #15]
|
|
8009b36: 2b00 cmp r3, #0
|
|
8009b38: d008 beq.n 8009b4c <USBD_SetConfig+0x78>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009b3a: 6839 ldr r1, [r7, #0]
|
|
8009b3c: 6878 ldr r0, [r7, #4]
|
|
8009b3e: f000 f962 bl 8009e06 <USBD_CtlError>
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8009b42: 687b ldr r3, [r7, #4]
|
|
8009b44: 2202 movs r2, #2
|
|
8009b46: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
8009b4a: e065 b.n 8009c18 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009b4c: 6878 ldr r0, [r7, #4]
|
|
8009b4e: f000 fa17 bl 8009f80 <USBD_CtlSendStatus>
|
|
pdev->dev_state = USBD_STATE_CONFIGURED;
|
|
8009b52: 687b ldr r3, [r7, #4]
|
|
8009b54: 2203 movs r2, #3
|
|
8009b56: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
break;
|
|
8009b5a: e05d b.n 8009c18 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009b5c: 6878 ldr r0, [r7, #4]
|
|
8009b5e: f000 fa0f bl 8009f80 <USBD_CtlSendStatus>
|
|
break;
|
|
8009b62: e059 b.n 8009c18 <USBD_SetConfig+0x144>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (cfgidx == 0U)
|
|
8009b64: 4b2f ldr r3, [pc, #188] @ (8009c24 <USBD_SetConfig+0x150>)
|
|
8009b66: 781b ldrb r3, [r3, #0]
|
|
8009b68: 2b00 cmp r3, #0
|
|
8009b6a: d112 bne.n 8009b92 <USBD_SetConfig+0xbe>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8009b6c: 687b ldr r3, [r7, #4]
|
|
8009b6e: 2202 movs r2, #2
|
|
8009b70: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->dev_config = cfgidx;
|
|
8009b74: 4b2b ldr r3, [pc, #172] @ (8009c24 <USBD_SetConfig+0x150>)
|
|
8009b76: 781b ldrb r3, [r3, #0]
|
|
8009b78: 461a mov r2, r3
|
|
8009b7a: 687b ldr r3, [r7, #4]
|
|
8009b7c: 605a str r2, [r3, #4]
|
|
(void)USBD_ClrClassConfig(pdev, cfgidx);
|
|
8009b7e: 4b29 ldr r3, [pc, #164] @ (8009c24 <USBD_SetConfig+0x150>)
|
|
8009b80: 781b ldrb r3, [r3, #0]
|
|
8009b82: 4619 mov r1, r3
|
|
8009b84: 6878 ldr r0, [r7, #4]
|
|
8009b86: f7fe ff92 bl 8008aae <USBD_ClrClassConfig>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009b8a: 6878 ldr r0, [r7, #4]
|
|
8009b8c: f000 f9f8 bl 8009f80 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
8009b90: e042 b.n 8009c18 <USBD_SetConfig+0x144>
|
|
else if (cfgidx != pdev->dev_config)
|
|
8009b92: 4b24 ldr r3, [pc, #144] @ (8009c24 <USBD_SetConfig+0x150>)
|
|
8009b94: 781b ldrb r3, [r3, #0]
|
|
8009b96: 461a mov r2, r3
|
|
8009b98: 687b ldr r3, [r7, #4]
|
|
8009b9a: 685b ldr r3, [r3, #4]
|
|
8009b9c: 429a cmp r2, r3
|
|
8009b9e: d02a beq.n 8009bf6 <USBD_SetConfig+0x122>
|
|
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
8009ba0: 687b ldr r3, [r7, #4]
|
|
8009ba2: 685b ldr r3, [r3, #4]
|
|
8009ba4: b2db uxtb r3, r3
|
|
8009ba6: 4619 mov r1, r3
|
|
8009ba8: 6878 ldr r0, [r7, #4]
|
|
8009baa: f7fe ff80 bl 8008aae <USBD_ClrClassConfig>
|
|
pdev->dev_config = cfgidx;
|
|
8009bae: 4b1d ldr r3, [pc, #116] @ (8009c24 <USBD_SetConfig+0x150>)
|
|
8009bb0: 781b ldrb r3, [r3, #0]
|
|
8009bb2: 461a mov r2, r3
|
|
8009bb4: 687b ldr r3, [r7, #4]
|
|
8009bb6: 605a str r2, [r3, #4]
|
|
ret = USBD_SetClassConfig(pdev, cfgidx);
|
|
8009bb8: 4b1a ldr r3, [pc, #104] @ (8009c24 <USBD_SetConfig+0x150>)
|
|
8009bba: 781b ldrb r3, [r3, #0]
|
|
8009bbc: 4619 mov r1, r3
|
|
8009bbe: 6878 ldr r0, [r7, #4]
|
|
8009bc0: f7fe ff59 bl 8008a76 <USBD_SetClassConfig>
|
|
8009bc4: 4603 mov r3, r0
|
|
8009bc6: 73fb strb r3, [r7, #15]
|
|
if (ret != USBD_OK)
|
|
8009bc8: 7bfb ldrb r3, [r7, #15]
|
|
8009bca: 2b00 cmp r3, #0
|
|
8009bcc: d00f beq.n 8009bee <USBD_SetConfig+0x11a>
|
|
USBD_CtlError(pdev, req);
|
|
8009bce: 6839 ldr r1, [r7, #0]
|
|
8009bd0: 6878 ldr r0, [r7, #4]
|
|
8009bd2: f000 f918 bl 8009e06 <USBD_CtlError>
|
|
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
8009bd6: 687b ldr r3, [r7, #4]
|
|
8009bd8: 685b ldr r3, [r3, #4]
|
|
8009bda: b2db uxtb r3, r3
|
|
8009bdc: 4619 mov r1, r3
|
|
8009bde: 6878 ldr r0, [r7, #4]
|
|
8009be0: f7fe ff65 bl 8008aae <USBD_ClrClassConfig>
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8009be4: 687b ldr r3, [r7, #4]
|
|
8009be6: 2202 movs r2, #2
|
|
8009be8: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
break;
|
|
8009bec: e014 b.n 8009c18 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009bee: 6878 ldr r0, [r7, #4]
|
|
8009bf0: f000 f9c6 bl 8009f80 <USBD_CtlSendStatus>
|
|
break;
|
|
8009bf4: e010 b.n 8009c18 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009bf6: 6878 ldr r0, [r7, #4]
|
|
8009bf8: f000 f9c2 bl 8009f80 <USBD_CtlSendStatus>
|
|
break;
|
|
8009bfc: e00c b.n 8009c18 <USBD_SetConfig+0x144>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8009bfe: 6839 ldr r1, [r7, #0]
|
|
8009c00: 6878 ldr r0, [r7, #4]
|
|
8009c02: f000 f900 bl 8009e06 <USBD_CtlError>
|
|
(void)USBD_ClrClassConfig(pdev, cfgidx);
|
|
8009c06: 4b07 ldr r3, [pc, #28] @ (8009c24 <USBD_SetConfig+0x150>)
|
|
8009c08: 781b ldrb r3, [r3, #0]
|
|
8009c0a: 4619 mov r1, r3
|
|
8009c0c: 6878 ldr r0, [r7, #4]
|
|
8009c0e: f7fe ff4e bl 8008aae <USBD_ClrClassConfig>
|
|
ret = USBD_FAIL;
|
|
8009c12: 2303 movs r3, #3
|
|
8009c14: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009c16: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8009c18: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009c1a: 4618 mov r0, r3
|
|
8009c1c: 3710 adds r7, #16
|
|
8009c1e: 46bd mov sp, r7
|
|
8009c20: bd80 pop {r7, pc}
|
|
8009c22: bf00 nop
|
|
8009c24: 20000720 .word 0x20000720
|
|
|
|
08009c28 <USBD_GetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009c28: b580 push {r7, lr}
|
|
8009c2a: b082 sub sp, #8
|
|
8009c2c: af00 add r7, sp, #0
|
|
8009c2e: 6078 str r0, [r7, #4]
|
|
8009c30: 6039 str r1, [r7, #0]
|
|
if (req->wLength != 1U)
|
|
8009c32: 683b ldr r3, [r7, #0]
|
|
8009c34: 88db ldrh r3, [r3, #6]
|
|
8009c36: 2b01 cmp r3, #1
|
|
8009c38: d004 beq.n 8009c44 <USBD_GetConfig+0x1c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009c3a: 6839 ldr r1, [r7, #0]
|
|
8009c3c: 6878 ldr r0, [r7, #4]
|
|
8009c3e: f000 f8e2 bl 8009e06 <USBD_CtlError>
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
8009c42: e023 b.n 8009c8c <USBD_GetConfig+0x64>
|
|
switch (pdev->dev_state)
|
|
8009c44: 687b ldr r3, [r7, #4]
|
|
8009c46: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009c4a: b2db uxtb r3, r3
|
|
8009c4c: 2b02 cmp r3, #2
|
|
8009c4e: dc02 bgt.n 8009c56 <USBD_GetConfig+0x2e>
|
|
8009c50: 2b00 cmp r3, #0
|
|
8009c52: dc03 bgt.n 8009c5c <USBD_GetConfig+0x34>
|
|
8009c54: e015 b.n 8009c82 <USBD_GetConfig+0x5a>
|
|
8009c56: 2b03 cmp r3, #3
|
|
8009c58: d00b beq.n 8009c72 <USBD_GetConfig+0x4a>
|
|
8009c5a: e012 b.n 8009c82 <USBD_GetConfig+0x5a>
|
|
pdev->dev_default_config = 0U;
|
|
8009c5c: 687b ldr r3, [r7, #4]
|
|
8009c5e: 2200 movs r2, #0
|
|
8009c60: 609a str r2, [r3, #8]
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
|
|
8009c62: 687b ldr r3, [r7, #4]
|
|
8009c64: 3308 adds r3, #8
|
|
8009c66: 2201 movs r2, #1
|
|
8009c68: 4619 mov r1, r3
|
|
8009c6a: 6878 ldr r0, [r7, #4]
|
|
8009c6c: f000 f948 bl 8009f00 <USBD_CtlSendData>
|
|
break;
|
|
8009c70: e00c b.n 8009c8c <USBD_GetConfig+0x64>
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U);
|
|
8009c72: 687b ldr r3, [r7, #4]
|
|
8009c74: 3304 adds r3, #4
|
|
8009c76: 2201 movs r2, #1
|
|
8009c78: 4619 mov r1, r3
|
|
8009c7a: 6878 ldr r0, [r7, #4]
|
|
8009c7c: f000 f940 bl 8009f00 <USBD_CtlSendData>
|
|
break;
|
|
8009c80: e004 b.n 8009c8c <USBD_GetConfig+0x64>
|
|
USBD_CtlError(pdev, req);
|
|
8009c82: 6839 ldr r1, [r7, #0]
|
|
8009c84: 6878 ldr r0, [r7, #4]
|
|
8009c86: f000 f8be bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
8009c8a: bf00 nop
|
|
}
|
|
8009c8c: bf00 nop
|
|
8009c8e: 3708 adds r7, #8
|
|
8009c90: 46bd mov sp, r7
|
|
8009c92: bd80 pop {r7, pc}
|
|
|
|
08009c94 <USBD_GetStatus>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009c94: b580 push {r7, lr}
|
|
8009c96: b082 sub sp, #8
|
|
8009c98: af00 add r7, sp, #0
|
|
8009c9a: 6078 str r0, [r7, #4]
|
|
8009c9c: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
8009c9e: 687b ldr r3, [r7, #4]
|
|
8009ca0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009ca4: b2db uxtb r3, r3
|
|
8009ca6: 3b01 subs r3, #1
|
|
8009ca8: 2b02 cmp r3, #2
|
|
8009caa: d81e bhi.n 8009cea <USBD_GetStatus+0x56>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wLength != 0x2U)
|
|
8009cac: 683b ldr r3, [r7, #0]
|
|
8009cae: 88db ldrh r3, [r3, #6]
|
|
8009cb0: 2b02 cmp r3, #2
|
|
8009cb2: d004 beq.n 8009cbe <USBD_GetStatus+0x2a>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8009cb4: 6839 ldr r1, [r7, #0]
|
|
8009cb6: 6878 ldr r0, [r7, #4]
|
|
8009cb8: f000 f8a5 bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
8009cbc: e01a b.n 8009cf4 <USBD_GetStatus+0x60>
|
|
}
|
|
|
|
#if (USBD_SELF_POWERED == 1U)
|
|
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
|
|
8009cbe: 687b ldr r3, [r7, #4]
|
|
8009cc0: 2201 movs r2, #1
|
|
8009cc2: 60da str r2, [r3, #12]
|
|
#else
|
|
pdev->dev_config_status = 0U;
|
|
#endif /* USBD_SELF_POWERED */
|
|
|
|
if (pdev->dev_remote_wakeup != 0U)
|
|
8009cc4: 687b ldr r3, [r7, #4]
|
|
8009cc6: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
|
|
8009cca: 2b00 cmp r3, #0
|
|
8009ccc: d005 beq.n 8009cda <USBD_GetStatus+0x46>
|
|
{
|
|
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
|
|
8009cce: 687b ldr r3, [r7, #4]
|
|
8009cd0: 68db ldr r3, [r3, #12]
|
|
8009cd2: f043 0202 orr.w r2, r3, #2
|
|
8009cd6: 687b ldr r3, [r7, #4]
|
|
8009cd8: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U);
|
|
8009cda: 687b ldr r3, [r7, #4]
|
|
8009cdc: 330c adds r3, #12
|
|
8009cde: 2202 movs r2, #2
|
|
8009ce0: 4619 mov r1, r3
|
|
8009ce2: 6878 ldr r0, [r7, #4]
|
|
8009ce4: f000 f90c bl 8009f00 <USBD_CtlSendData>
|
|
break;
|
|
8009ce8: e004 b.n 8009cf4 <USBD_GetStatus+0x60>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8009cea: 6839 ldr r1, [r7, #0]
|
|
8009cec: 6878 ldr r0, [r7, #4]
|
|
8009cee: f000 f88a bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
8009cf2: bf00 nop
|
|
}
|
|
}
|
|
8009cf4: bf00 nop
|
|
8009cf6: 3708 adds r7, #8
|
|
8009cf8: 46bd mov sp, r7
|
|
8009cfa: bd80 pop {r7, pc}
|
|
|
|
08009cfc <USBD_SetFeature>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009cfc: b580 push {r7, lr}
|
|
8009cfe: b082 sub sp, #8
|
|
8009d00: af00 add r7, sp, #0
|
|
8009d02: 6078 str r0, [r7, #4]
|
|
8009d04: 6039 str r1, [r7, #0]
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
8009d06: 683b ldr r3, [r7, #0]
|
|
8009d08: 885b ldrh r3, [r3, #2]
|
|
8009d0a: 2b01 cmp r3, #1
|
|
8009d0c: d107 bne.n 8009d1e <USBD_SetFeature+0x22>
|
|
{
|
|
pdev->dev_remote_wakeup = 1U;
|
|
8009d0e: 687b ldr r3, [r7, #4]
|
|
8009d10: 2201 movs r2, #1
|
|
8009d12: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009d16: 6878 ldr r0, [r7, #4]
|
|
8009d18: f000 f932 bl 8009f80 <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
}
|
|
8009d1c: e013 b.n 8009d46 <USBD_SetFeature+0x4a>
|
|
else if (req->wValue == USB_FEATURE_TEST_MODE)
|
|
8009d1e: 683b ldr r3, [r7, #0]
|
|
8009d20: 885b ldrh r3, [r3, #2]
|
|
8009d22: 2b02 cmp r3, #2
|
|
8009d24: d10b bne.n 8009d3e <USBD_SetFeature+0x42>
|
|
pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8);
|
|
8009d26: 683b ldr r3, [r7, #0]
|
|
8009d28: 889b ldrh r3, [r3, #4]
|
|
8009d2a: 0a1b lsrs r3, r3, #8
|
|
8009d2c: b29b uxth r3, r3
|
|
8009d2e: b2da uxtb r2, r3
|
|
8009d30: 687b ldr r3, [r7, #4]
|
|
8009d32: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009d36: 6878 ldr r0, [r7, #4]
|
|
8009d38: f000 f922 bl 8009f80 <USBD_CtlSendStatus>
|
|
}
|
|
8009d3c: e003 b.n 8009d46 <USBD_SetFeature+0x4a>
|
|
USBD_CtlError(pdev, req);
|
|
8009d3e: 6839 ldr r1, [r7, #0]
|
|
8009d40: 6878 ldr r0, [r7, #4]
|
|
8009d42: f000 f860 bl 8009e06 <USBD_CtlError>
|
|
}
|
|
8009d46: bf00 nop
|
|
8009d48: 3708 adds r7, #8
|
|
8009d4a: 46bd mov sp, r7
|
|
8009d4c: bd80 pop {r7, pc}
|
|
|
|
08009d4e <USBD_ClrFeature>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009d4e: b580 push {r7, lr}
|
|
8009d50: b082 sub sp, #8
|
|
8009d52: af00 add r7, sp, #0
|
|
8009d54: 6078 str r0, [r7, #4]
|
|
8009d56: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
8009d58: 687b ldr r3, [r7, #4]
|
|
8009d5a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8009d5e: b2db uxtb r3, r3
|
|
8009d60: 3b01 subs r3, #1
|
|
8009d62: 2b02 cmp r3, #2
|
|
8009d64: d80b bhi.n 8009d7e <USBD_ClrFeature+0x30>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
8009d66: 683b ldr r3, [r7, #0]
|
|
8009d68: 885b ldrh r3, [r3, #2]
|
|
8009d6a: 2b01 cmp r3, #1
|
|
8009d6c: d10c bne.n 8009d88 <USBD_ClrFeature+0x3a>
|
|
{
|
|
pdev->dev_remote_wakeup = 0U;
|
|
8009d6e: 687b ldr r3, [r7, #4]
|
|
8009d70: 2200 movs r2, #0
|
|
8009d72: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8009d76: 6878 ldr r0, [r7, #4]
|
|
8009d78: f000 f902 bl 8009f80 <USBD_CtlSendStatus>
|
|
}
|
|
break;
|
|
8009d7c: e004 b.n 8009d88 <USBD_ClrFeature+0x3a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8009d7e: 6839 ldr r1, [r7, #0]
|
|
8009d80: 6878 ldr r0, [r7, #4]
|
|
8009d82: f000 f840 bl 8009e06 <USBD_CtlError>
|
|
break;
|
|
8009d86: e000 b.n 8009d8a <USBD_ClrFeature+0x3c>
|
|
break;
|
|
8009d88: bf00 nop
|
|
}
|
|
}
|
|
8009d8a: bf00 nop
|
|
8009d8c: 3708 adds r7, #8
|
|
8009d8e: 46bd mov sp, r7
|
|
8009d90: bd80 pop {r7, pc}
|
|
|
|
08009d92 <USBD_ParseSetupRequest>:
|
|
* @param req: usb request
|
|
* @param pdata: setup data pointer
|
|
* @retval None
|
|
*/
|
|
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
|
|
{
|
|
8009d92: b580 push {r7, lr}
|
|
8009d94: b084 sub sp, #16
|
|
8009d96: af00 add r7, sp, #0
|
|
8009d98: 6078 str r0, [r7, #4]
|
|
8009d9a: 6039 str r1, [r7, #0]
|
|
uint8_t *pbuff = pdata;
|
|
8009d9c: 683b ldr r3, [r7, #0]
|
|
8009d9e: 60fb str r3, [r7, #12]
|
|
|
|
req->bmRequest = *(uint8_t *)(pbuff);
|
|
8009da0: 68fb ldr r3, [r7, #12]
|
|
8009da2: 781a ldrb r2, [r3, #0]
|
|
8009da4: 687b ldr r3, [r7, #4]
|
|
8009da6: 701a strb r2, [r3, #0]
|
|
|
|
pbuff++;
|
|
8009da8: 68fb ldr r3, [r7, #12]
|
|
8009daa: 3301 adds r3, #1
|
|
8009dac: 60fb str r3, [r7, #12]
|
|
req->bRequest = *(uint8_t *)(pbuff);
|
|
8009dae: 68fb ldr r3, [r7, #12]
|
|
8009db0: 781a ldrb r2, [r3, #0]
|
|
8009db2: 687b ldr r3, [r7, #4]
|
|
8009db4: 705a strb r2, [r3, #1]
|
|
|
|
pbuff++;
|
|
8009db6: 68fb ldr r3, [r7, #12]
|
|
8009db8: 3301 adds r3, #1
|
|
8009dba: 60fb str r3, [r7, #12]
|
|
req->wValue = SWAPBYTE(pbuff);
|
|
8009dbc: 68f8 ldr r0, [r7, #12]
|
|
8009dbe: f7ff fa13 bl 80091e8 <SWAPBYTE>
|
|
8009dc2: 4603 mov r3, r0
|
|
8009dc4: 461a mov r2, r3
|
|
8009dc6: 687b ldr r3, [r7, #4]
|
|
8009dc8: 805a strh r2, [r3, #2]
|
|
|
|
pbuff++;
|
|
8009dca: 68fb ldr r3, [r7, #12]
|
|
8009dcc: 3301 adds r3, #1
|
|
8009dce: 60fb str r3, [r7, #12]
|
|
pbuff++;
|
|
8009dd0: 68fb ldr r3, [r7, #12]
|
|
8009dd2: 3301 adds r3, #1
|
|
8009dd4: 60fb str r3, [r7, #12]
|
|
req->wIndex = SWAPBYTE(pbuff);
|
|
8009dd6: 68f8 ldr r0, [r7, #12]
|
|
8009dd8: f7ff fa06 bl 80091e8 <SWAPBYTE>
|
|
8009ddc: 4603 mov r3, r0
|
|
8009dde: 461a mov r2, r3
|
|
8009de0: 687b ldr r3, [r7, #4]
|
|
8009de2: 809a strh r2, [r3, #4]
|
|
|
|
pbuff++;
|
|
8009de4: 68fb ldr r3, [r7, #12]
|
|
8009de6: 3301 adds r3, #1
|
|
8009de8: 60fb str r3, [r7, #12]
|
|
pbuff++;
|
|
8009dea: 68fb ldr r3, [r7, #12]
|
|
8009dec: 3301 adds r3, #1
|
|
8009dee: 60fb str r3, [r7, #12]
|
|
req->wLength = SWAPBYTE(pbuff);
|
|
8009df0: 68f8 ldr r0, [r7, #12]
|
|
8009df2: f7ff f9f9 bl 80091e8 <SWAPBYTE>
|
|
8009df6: 4603 mov r3, r0
|
|
8009df8: 461a mov r2, r3
|
|
8009dfa: 687b ldr r3, [r7, #4]
|
|
8009dfc: 80da strh r2, [r3, #6]
|
|
}
|
|
8009dfe: bf00 nop
|
|
8009e00: 3710 adds r7, #16
|
|
8009e02: 46bd mov sp, r7
|
|
8009e04: bd80 pop {r7, pc}
|
|
|
|
08009e06 <USBD_CtlError>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8009e06: b580 push {r7, lr}
|
|
8009e08: b082 sub sp, #8
|
|
8009e0a: af00 add r7, sp, #0
|
|
8009e0c: 6078 str r0, [r7, #4]
|
|
8009e0e: 6039 str r1, [r7, #0]
|
|
UNUSED(req);
|
|
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8009e10: 2180 movs r1, #128 @ 0x80
|
|
8009e12: 6878 ldr r0, [r7, #4]
|
|
8009e14: f000 fc2a bl 800a66c <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0U);
|
|
8009e18: 2100 movs r1, #0
|
|
8009e1a: 6878 ldr r0, [r7, #4]
|
|
8009e1c: f000 fc26 bl 800a66c <USBD_LL_StallEP>
|
|
}
|
|
8009e20: bf00 nop
|
|
8009e22: 3708 adds r7, #8
|
|
8009e24: 46bd mov sp, r7
|
|
8009e26: bd80 pop {r7, pc}
|
|
|
|
08009e28 <USBD_GetString>:
|
|
* @param unicode : Formatted string buffer (unicode)
|
|
* @param len : descriptor length
|
|
* @retval None
|
|
*/
|
|
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
|
|
{
|
|
8009e28: b580 push {r7, lr}
|
|
8009e2a: b086 sub sp, #24
|
|
8009e2c: af00 add r7, sp, #0
|
|
8009e2e: 60f8 str r0, [r7, #12]
|
|
8009e30: 60b9 str r1, [r7, #8]
|
|
8009e32: 607a str r2, [r7, #4]
|
|
uint8_t idx = 0U;
|
|
8009e34: 2300 movs r3, #0
|
|
8009e36: 75fb strb r3, [r7, #23]
|
|
uint8_t *pdesc;
|
|
|
|
if (desc == NULL)
|
|
8009e38: 68fb ldr r3, [r7, #12]
|
|
8009e3a: 2b00 cmp r3, #0
|
|
8009e3c: d042 beq.n 8009ec4 <USBD_GetString+0x9c>
|
|
{
|
|
return;
|
|
}
|
|
|
|
pdesc = desc;
|
|
8009e3e: 68fb ldr r3, [r7, #12]
|
|
8009e40: 613b str r3, [r7, #16]
|
|
*len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U);
|
|
8009e42: 6938 ldr r0, [r7, #16]
|
|
8009e44: f000 f842 bl 8009ecc <USBD_GetLen>
|
|
8009e48: 4603 mov r3, r0
|
|
8009e4a: 3301 adds r3, #1
|
|
8009e4c: 005b lsls r3, r3, #1
|
|
8009e4e: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8009e52: d808 bhi.n 8009e66 <USBD_GetString+0x3e>
|
|
8009e54: 6938 ldr r0, [r7, #16]
|
|
8009e56: f000 f839 bl 8009ecc <USBD_GetLen>
|
|
8009e5a: 4603 mov r3, r0
|
|
8009e5c: 3301 adds r3, #1
|
|
8009e5e: b29b uxth r3, r3
|
|
8009e60: 005b lsls r3, r3, #1
|
|
8009e62: b29a uxth r2, r3
|
|
8009e64: e001 b.n 8009e6a <USBD_GetString+0x42>
|
|
8009e66: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8009e6a: 687b ldr r3, [r7, #4]
|
|
8009e6c: 801a strh r2, [r3, #0]
|
|
|
|
unicode[idx] = *(uint8_t *)len;
|
|
8009e6e: 7dfb ldrb r3, [r7, #23]
|
|
8009e70: 68ba ldr r2, [r7, #8]
|
|
8009e72: 4413 add r3, r2
|
|
8009e74: 687a ldr r2, [r7, #4]
|
|
8009e76: 7812 ldrb r2, [r2, #0]
|
|
8009e78: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8009e7a: 7dfb ldrb r3, [r7, #23]
|
|
8009e7c: 3301 adds r3, #1
|
|
8009e7e: 75fb strb r3, [r7, #23]
|
|
unicode[idx] = USB_DESC_TYPE_STRING;
|
|
8009e80: 7dfb ldrb r3, [r7, #23]
|
|
8009e82: 68ba ldr r2, [r7, #8]
|
|
8009e84: 4413 add r3, r2
|
|
8009e86: 2203 movs r2, #3
|
|
8009e88: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8009e8a: 7dfb ldrb r3, [r7, #23]
|
|
8009e8c: 3301 adds r3, #1
|
|
8009e8e: 75fb strb r3, [r7, #23]
|
|
|
|
while (*pdesc != (uint8_t)'\0')
|
|
8009e90: e013 b.n 8009eba <USBD_GetString+0x92>
|
|
{
|
|
unicode[idx] = *pdesc;
|
|
8009e92: 7dfb ldrb r3, [r7, #23]
|
|
8009e94: 68ba ldr r2, [r7, #8]
|
|
8009e96: 4413 add r3, r2
|
|
8009e98: 693a ldr r2, [r7, #16]
|
|
8009e9a: 7812 ldrb r2, [r2, #0]
|
|
8009e9c: 701a strb r2, [r3, #0]
|
|
pdesc++;
|
|
8009e9e: 693b ldr r3, [r7, #16]
|
|
8009ea0: 3301 adds r3, #1
|
|
8009ea2: 613b str r3, [r7, #16]
|
|
idx++;
|
|
8009ea4: 7dfb ldrb r3, [r7, #23]
|
|
8009ea6: 3301 adds r3, #1
|
|
8009ea8: 75fb strb r3, [r7, #23]
|
|
|
|
unicode[idx] = 0U;
|
|
8009eaa: 7dfb ldrb r3, [r7, #23]
|
|
8009eac: 68ba ldr r2, [r7, #8]
|
|
8009eae: 4413 add r3, r2
|
|
8009eb0: 2200 movs r2, #0
|
|
8009eb2: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8009eb4: 7dfb ldrb r3, [r7, #23]
|
|
8009eb6: 3301 adds r3, #1
|
|
8009eb8: 75fb strb r3, [r7, #23]
|
|
while (*pdesc != (uint8_t)'\0')
|
|
8009eba: 693b ldr r3, [r7, #16]
|
|
8009ebc: 781b ldrb r3, [r3, #0]
|
|
8009ebe: 2b00 cmp r3, #0
|
|
8009ec0: d1e7 bne.n 8009e92 <USBD_GetString+0x6a>
|
|
8009ec2: e000 b.n 8009ec6 <USBD_GetString+0x9e>
|
|
return;
|
|
8009ec4: bf00 nop
|
|
}
|
|
}
|
|
8009ec6: 3718 adds r7, #24
|
|
8009ec8: 46bd mov sp, r7
|
|
8009eca: bd80 pop {r7, pc}
|
|
|
|
08009ecc <USBD_GetLen>:
|
|
* return the string length
|
|
* @param buf : pointer to the ascii string buffer
|
|
* @retval string length
|
|
*/
|
|
static uint8_t USBD_GetLen(uint8_t *buf)
|
|
{
|
|
8009ecc: b480 push {r7}
|
|
8009ece: b085 sub sp, #20
|
|
8009ed0: af00 add r7, sp, #0
|
|
8009ed2: 6078 str r0, [r7, #4]
|
|
uint8_t len = 0U;
|
|
8009ed4: 2300 movs r3, #0
|
|
8009ed6: 73fb strb r3, [r7, #15]
|
|
uint8_t *pbuff = buf;
|
|
8009ed8: 687b ldr r3, [r7, #4]
|
|
8009eda: 60bb str r3, [r7, #8]
|
|
|
|
while (*pbuff != (uint8_t)'\0')
|
|
8009edc: e005 b.n 8009eea <USBD_GetLen+0x1e>
|
|
{
|
|
len++;
|
|
8009ede: 7bfb ldrb r3, [r7, #15]
|
|
8009ee0: 3301 adds r3, #1
|
|
8009ee2: 73fb strb r3, [r7, #15]
|
|
pbuff++;
|
|
8009ee4: 68bb ldr r3, [r7, #8]
|
|
8009ee6: 3301 adds r3, #1
|
|
8009ee8: 60bb str r3, [r7, #8]
|
|
while (*pbuff != (uint8_t)'\0')
|
|
8009eea: 68bb ldr r3, [r7, #8]
|
|
8009eec: 781b ldrb r3, [r3, #0]
|
|
8009eee: 2b00 cmp r3, #0
|
|
8009ef0: d1f5 bne.n 8009ede <USBD_GetLen+0x12>
|
|
}
|
|
|
|
return len;
|
|
8009ef2: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009ef4: 4618 mov r0, r3
|
|
8009ef6: 3714 adds r7, #20
|
|
8009ef8: 46bd mov sp, r7
|
|
8009efa: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009efe: 4770 bx lr
|
|
|
|
08009f00 <USBD_CtlSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8009f00: b580 push {r7, lr}
|
|
8009f02: b084 sub sp, #16
|
|
8009f04: af00 add r7, sp, #0
|
|
8009f06: 60f8 str r0, [r7, #12]
|
|
8009f08: 60b9 str r1, [r7, #8]
|
|
8009f0a: 607a str r2, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_DATA_IN;
|
|
8009f0c: 68fb ldr r3, [r7, #12]
|
|
8009f0e: 2202 movs r2, #2
|
|
8009f10: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->ep_in[0].total_length = len;
|
|
8009f14: 68fb ldr r3, [r7, #12]
|
|
8009f16: 687a ldr r2, [r7, #4]
|
|
8009f18: 615a str r2, [r3, #20]
|
|
pdev->ep_in[0].pbuffer = pbuf;
|
|
8009f1a: 68fb ldr r3, [r7, #12]
|
|
8009f1c: 68ba ldr r2, [r7, #8]
|
|
8009f1e: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
|
|
pdev->ep_in[0].rem_length = 0U;
|
|
#else
|
|
pdev->ep_in[0].rem_length = len;
|
|
8009f20: 68fb ldr r3, [r7, #12]
|
|
8009f22: 687a ldr r2, [r7, #4]
|
|
8009f24: 619a str r2, [r3, #24]
|
|
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
8009f26: 687b ldr r3, [r7, #4]
|
|
8009f28: 68ba ldr r2, [r7, #8]
|
|
8009f2a: 2100 movs r1, #0
|
|
8009f2c: 68f8 ldr r0, [r7, #12]
|
|
8009f2e: f000 fc26 bl 800a77e <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8009f32: 2300 movs r3, #0
|
|
}
|
|
8009f34: 4618 mov r0, r3
|
|
8009f36: 3710 adds r7, #16
|
|
8009f38: 46bd mov sp, r7
|
|
8009f3a: bd80 pop {r7, pc}
|
|
|
|
08009f3c <USBD_CtlContinueSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8009f3c: b580 push {r7, lr}
|
|
8009f3e: b084 sub sp, #16
|
|
8009f40: af00 add r7, sp, #0
|
|
8009f42: 60f8 str r0, [r7, #12]
|
|
8009f44: 60b9 str r1, [r7, #8]
|
|
8009f46: 607a str r2, [r7, #4]
|
|
/* Start the next transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
8009f48: 687b ldr r3, [r7, #4]
|
|
8009f4a: 68ba ldr r2, [r7, #8]
|
|
8009f4c: 2100 movs r1, #0
|
|
8009f4e: 68f8 ldr r0, [r7, #12]
|
|
8009f50: f000 fc15 bl 800a77e <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8009f54: 2300 movs r3, #0
|
|
}
|
|
8009f56: 4618 mov r0, r3
|
|
8009f58: 3710 adds r7, #16
|
|
8009f5a: 46bd mov sp, r7
|
|
8009f5c: bd80 pop {r7, pc}
|
|
|
|
08009f5e <USBD_CtlContinueRx>:
|
|
* @param len: length of data to be received
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8009f5e: b580 push {r7, lr}
|
|
8009f60: b084 sub sp, #16
|
|
8009f62: af00 add r7, sp, #0
|
|
8009f64: 60f8 str r0, [r7, #12]
|
|
8009f66: 60b9 str r1, [r7, #8]
|
|
8009f68: 607a str r2, [r7, #4]
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
|
|
8009f6a: 687b ldr r3, [r7, #4]
|
|
8009f6c: 68ba ldr r2, [r7, #8]
|
|
8009f6e: 2100 movs r1, #0
|
|
8009f70: 68f8 ldr r0, [r7, #12]
|
|
8009f72: f000 fc25 bl 800a7c0 <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8009f76: 2300 movs r3, #0
|
|
}
|
|
8009f78: 4618 mov r0, r3
|
|
8009f7a: 3710 adds r7, #16
|
|
8009f7c: 46bd mov sp, r7
|
|
8009f7e: bd80 pop {r7, pc}
|
|
|
|
08009f80 <USBD_CtlSendStatus>:
|
|
* send zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8009f80: b580 push {r7, lr}
|
|
8009f82: b082 sub sp, #8
|
|
8009f84: af00 add r7, sp, #0
|
|
8009f86: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_IN;
|
|
8009f88: 687b ldr r3, [r7, #4]
|
|
8009f8a: 2204 movs r2, #4
|
|
8009f8c: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
|
|
8009f90: 2300 movs r3, #0
|
|
8009f92: 2200 movs r2, #0
|
|
8009f94: 2100 movs r1, #0
|
|
8009f96: 6878 ldr r0, [r7, #4]
|
|
8009f98: f000 fbf1 bl 800a77e <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8009f9c: 2300 movs r3, #0
|
|
}
|
|
8009f9e: 4618 mov r0, r3
|
|
8009fa0: 3708 adds r7, #8
|
|
8009fa2: 46bd mov sp, r7
|
|
8009fa4: bd80 pop {r7, pc}
|
|
|
|
08009fa6 <USBD_CtlReceiveStatus>:
|
|
* receive zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8009fa6: b580 push {r7, lr}
|
|
8009fa8: b082 sub sp, #8
|
|
8009faa: af00 add r7, sp, #0
|
|
8009fac: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_OUT;
|
|
8009fae: 687b ldr r3, [r7, #4]
|
|
8009fb0: 2205 movs r2, #5
|
|
8009fb2: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8009fb6: 2300 movs r3, #0
|
|
8009fb8: 2200 movs r2, #0
|
|
8009fba: 2100 movs r1, #0
|
|
8009fbc: 6878 ldr r0, [r7, #4]
|
|
8009fbe: f000 fbff bl 800a7c0 <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8009fc2: 2300 movs r3, #0
|
|
}
|
|
8009fc4: 4618 mov r0, r3
|
|
8009fc6: 3708 adds r7, #8
|
|
8009fc8: 46bd mov sp, r7
|
|
8009fca: bd80 pop {r7, pc}
|
|
|
|
08009fcc <MX_USB_DEVICE_Init>:
|
|
/**
|
|
* Init USB device Library, add supported class and start the library
|
|
* @retval None
|
|
*/
|
|
void MX_USB_DEVICE_Init(void)
|
|
{
|
|
8009fcc: b580 push {r7, lr}
|
|
8009fce: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
|
|
|
|
/* USER CODE END USB_DEVICE_Init_PreTreatment */
|
|
|
|
/* Init Device Library, add supported class and start the library. */
|
|
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
|
|
8009fd0: 2200 movs r2, #0
|
|
8009fd2: 490e ldr r1, [pc, #56] @ (800a00c <MX_USB_DEVICE_Init+0x40>)
|
|
8009fd4: 480e ldr r0, [pc, #56] @ (800a010 <MX_USB_DEVICE_Init+0x44>)
|
|
8009fd6: f7fe fcd1 bl 800897c <USBD_Init>
|
|
8009fda: 4603 mov r3, r0
|
|
8009fdc: 2b00 cmp r3, #0
|
|
8009fde: d001 beq.n 8009fe4 <MX_USB_DEVICE_Init+0x18>
|
|
{
|
|
Error_Handler();
|
|
8009fe0: f7f6 fee2 bl 8000da8 <Error_Handler>
|
|
}
|
|
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK)
|
|
8009fe4: 490b ldr r1, [pc, #44] @ (800a014 <MX_USB_DEVICE_Init+0x48>)
|
|
8009fe6: 480a ldr r0, [pc, #40] @ (800a010 <MX_USB_DEVICE_Init+0x44>)
|
|
8009fe8: f7fe fcf8 bl 80089dc <USBD_RegisterClass>
|
|
8009fec: 4603 mov r3, r0
|
|
8009fee: 2b00 cmp r3, #0
|
|
8009ff0: d001 beq.n 8009ff6 <MX_USB_DEVICE_Init+0x2a>
|
|
{
|
|
Error_Handler();
|
|
8009ff2: f7f6 fed9 bl 8000da8 <Error_Handler>
|
|
}
|
|
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
|
|
8009ff6: 4806 ldr r0, [pc, #24] @ (800a010 <MX_USB_DEVICE_Init+0x44>)
|
|
8009ff8: f7fe fd26 bl 8008a48 <USBD_Start>
|
|
8009ffc: 4603 mov r3, r0
|
|
8009ffe: 2b00 cmp r3, #0
|
|
800a000: d001 beq.n 800a006 <MX_USB_DEVICE_Init+0x3a>
|
|
{
|
|
Error_Handler();
|
|
800a002: f7f6 fed1 bl 8000da8 <Error_Handler>
|
|
}
|
|
|
|
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
|
|
|
|
/* USER CODE END USB_DEVICE_Init_PostTreatment */
|
|
}
|
|
800a006: bf00 nop
|
|
800a008: bd80 pop {r7, pc}
|
|
800a00a: bf00 nop
|
|
800a00c: 20000140 .word 0x20000140
|
|
800a010: 20000724 .word 0x20000724
|
|
800a014: 2000009c .word 0x2000009c
|
|
|
|
0800a018 <USBD_FS_DeviceDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a018: b480 push {r7}
|
|
800a01a: b083 sub sp, #12
|
|
800a01c: af00 add r7, sp, #0
|
|
800a01e: 4603 mov r3, r0
|
|
800a020: 6039 str r1, [r7, #0]
|
|
800a022: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_FS_DeviceDesc);
|
|
800a024: 683b ldr r3, [r7, #0]
|
|
800a026: 2212 movs r2, #18
|
|
800a028: 801a strh r2, [r3, #0]
|
|
return USBD_FS_DeviceDesc;
|
|
800a02a: 4b03 ldr r3, [pc, #12] @ (800a038 <USBD_FS_DeviceDescriptor+0x20>)
|
|
}
|
|
800a02c: 4618 mov r0, r3
|
|
800a02e: 370c adds r7, #12
|
|
800a030: 46bd mov sp, r7
|
|
800a032: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a036: 4770 bx lr
|
|
800a038: 20000160 .word 0x20000160
|
|
|
|
0800a03c <USBD_FS_LangIDStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a03c: b480 push {r7}
|
|
800a03e: b083 sub sp, #12
|
|
800a040: af00 add r7, sp, #0
|
|
800a042: 4603 mov r3, r0
|
|
800a044: 6039 str r1, [r7, #0]
|
|
800a046: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_LangIDDesc);
|
|
800a048: 683b ldr r3, [r7, #0]
|
|
800a04a: 2204 movs r2, #4
|
|
800a04c: 801a strh r2, [r3, #0]
|
|
return USBD_LangIDDesc;
|
|
800a04e: 4b03 ldr r3, [pc, #12] @ (800a05c <USBD_FS_LangIDStrDescriptor+0x20>)
|
|
}
|
|
800a050: 4618 mov r0, r3
|
|
800a052: 370c adds r7, #12
|
|
800a054: 46bd mov sp, r7
|
|
800a056: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a05a: 4770 bx lr
|
|
800a05c: 20000180 .word 0x20000180
|
|
|
|
0800a060 <USBD_FS_ProductStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a060: b580 push {r7, lr}
|
|
800a062: b082 sub sp, #8
|
|
800a064: af00 add r7, sp, #0
|
|
800a066: 4603 mov r3, r0
|
|
800a068: 6039 str r1, [r7, #0]
|
|
800a06a: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
800a06c: 79fb ldrb r3, [r7, #7]
|
|
800a06e: 2b00 cmp r3, #0
|
|
800a070: d105 bne.n 800a07e <USBD_FS_ProductStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
|
|
800a072: 683a ldr r2, [r7, #0]
|
|
800a074: 4907 ldr r1, [pc, #28] @ (800a094 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
800a076: 4808 ldr r0, [pc, #32] @ (800a098 <USBD_FS_ProductStrDescriptor+0x38>)
|
|
800a078: f7ff fed6 bl 8009e28 <USBD_GetString>
|
|
800a07c: e004 b.n 800a088 <USBD_FS_ProductStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
|
|
800a07e: 683a ldr r2, [r7, #0]
|
|
800a080: 4904 ldr r1, [pc, #16] @ (800a094 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
800a082: 4805 ldr r0, [pc, #20] @ (800a098 <USBD_FS_ProductStrDescriptor+0x38>)
|
|
800a084: f7ff fed0 bl 8009e28 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
800a088: 4b02 ldr r3, [pc, #8] @ (800a094 <USBD_FS_ProductStrDescriptor+0x34>)
|
|
}
|
|
800a08a: 4618 mov r0, r3
|
|
800a08c: 3708 adds r7, #8
|
|
800a08e: 46bd mov sp, r7
|
|
800a090: bd80 pop {r7, pc}
|
|
800a092: bf00 nop
|
|
800a094: 20000a00 .word 0x20000a00
|
|
800a098: 0800a9b4 .word 0x0800a9b4
|
|
|
|
0800a09c <USBD_FS_ManufacturerStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a09c: b580 push {r7, lr}
|
|
800a09e: b082 sub sp, #8
|
|
800a0a0: af00 add r7, sp, #0
|
|
800a0a2: 4603 mov r3, r0
|
|
800a0a4: 6039 str r1, [r7, #0]
|
|
800a0a6: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
|
|
800a0a8: 683a ldr r2, [r7, #0]
|
|
800a0aa: 4904 ldr r1, [pc, #16] @ (800a0bc <USBD_FS_ManufacturerStrDescriptor+0x20>)
|
|
800a0ac: 4804 ldr r0, [pc, #16] @ (800a0c0 <USBD_FS_ManufacturerStrDescriptor+0x24>)
|
|
800a0ae: f7ff febb bl 8009e28 <USBD_GetString>
|
|
return USBD_StrDesc;
|
|
800a0b2: 4b02 ldr r3, [pc, #8] @ (800a0bc <USBD_FS_ManufacturerStrDescriptor+0x20>)
|
|
}
|
|
800a0b4: 4618 mov r0, r3
|
|
800a0b6: 3708 adds r7, #8
|
|
800a0b8: 46bd mov sp, r7
|
|
800a0ba: bd80 pop {r7, pc}
|
|
800a0bc: 20000a00 .word 0x20000a00
|
|
800a0c0: 0800a9c8 .word 0x0800a9c8
|
|
|
|
0800a0c4 <USBD_FS_SerialStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a0c4: b580 push {r7, lr}
|
|
800a0c6: b082 sub sp, #8
|
|
800a0c8: af00 add r7, sp, #0
|
|
800a0ca: 4603 mov r3, r0
|
|
800a0cc: 6039 str r1, [r7, #0]
|
|
800a0ce: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = USB_SIZ_STRING_SERIAL;
|
|
800a0d0: 683b ldr r3, [r7, #0]
|
|
800a0d2: 221a movs r2, #26
|
|
800a0d4: 801a strh r2, [r3, #0]
|
|
|
|
/* Update the serial number string descriptor with the data from the unique
|
|
* ID */
|
|
Get_SerialNum();
|
|
800a0d6: f000 f855 bl 800a184 <Get_SerialNum>
|
|
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
|
|
|
|
/* USER CODE END USBD_FS_SerialStrDescriptor */
|
|
return (uint8_t *) USBD_StringSerial;
|
|
800a0da: 4b02 ldr r3, [pc, #8] @ (800a0e4 <USBD_FS_SerialStrDescriptor+0x20>)
|
|
}
|
|
800a0dc: 4618 mov r0, r3
|
|
800a0de: 3708 adds r7, #8
|
|
800a0e0: 46bd mov sp, r7
|
|
800a0e2: bd80 pop {r7, pc}
|
|
800a0e4: 20000184 .word 0x20000184
|
|
|
|
0800a0e8 <USBD_FS_ConfigStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a0e8: b580 push {r7, lr}
|
|
800a0ea: b082 sub sp, #8
|
|
800a0ec: af00 add r7, sp, #0
|
|
800a0ee: 4603 mov r3, r0
|
|
800a0f0: 6039 str r1, [r7, #0]
|
|
800a0f2: 71fb strb r3, [r7, #7]
|
|
if(speed == USBD_SPEED_HIGH)
|
|
800a0f4: 79fb ldrb r3, [r7, #7]
|
|
800a0f6: 2b00 cmp r3, #0
|
|
800a0f8: d105 bne.n 800a106 <USBD_FS_ConfigStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
|
|
800a0fa: 683a ldr r2, [r7, #0]
|
|
800a0fc: 4907 ldr r1, [pc, #28] @ (800a11c <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
800a0fe: 4808 ldr r0, [pc, #32] @ (800a120 <USBD_FS_ConfigStrDescriptor+0x38>)
|
|
800a100: f7ff fe92 bl 8009e28 <USBD_GetString>
|
|
800a104: e004 b.n 800a110 <USBD_FS_ConfigStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
|
|
800a106: 683a ldr r2, [r7, #0]
|
|
800a108: 4904 ldr r1, [pc, #16] @ (800a11c <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
800a10a: 4805 ldr r0, [pc, #20] @ (800a120 <USBD_FS_ConfigStrDescriptor+0x38>)
|
|
800a10c: f7ff fe8c bl 8009e28 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
800a110: 4b02 ldr r3, [pc, #8] @ (800a11c <USBD_FS_ConfigStrDescriptor+0x34>)
|
|
}
|
|
800a112: 4618 mov r0, r3
|
|
800a114: 3708 adds r7, #8
|
|
800a116: 46bd mov sp, r7
|
|
800a118: bd80 pop {r7, pc}
|
|
800a11a: bf00 nop
|
|
800a11c: 20000a00 .word 0x20000a00
|
|
800a120: 0800a9d4 .word 0x0800a9d4
|
|
|
|
0800a124 <USBD_FS_InterfaceStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a124: b580 push {r7, lr}
|
|
800a126: b082 sub sp, #8
|
|
800a128: af00 add r7, sp, #0
|
|
800a12a: 4603 mov r3, r0
|
|
800a12c: 6039 str r1, [r7, #0]
|
|
800a12e: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
800a130: 79fb ldrb r3, [r7, #7]
|
|
800a132: 2b00 cmp r3, #0
|
|
800a134: d105 bne.n 800a142 <USBD_FS_InterfaceStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
|
|
800a136: 683a ldr r2, [r7, #0]
|
|
800a138: 4907 ldr r1, [pc, #28] @ (800a158 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
800a13a: 4808 ldr r0, [pc, #32] @ (800a15c <USBD_FS_InterfaceStrDescriptor+0x38>)
|
|
800a13c: f7ff fe74 bl 8009e28 <USBD_GetString>
|
|
800a140: e004 b.n 800a14c <USBD_FS_InterfaceStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
|
|
800a142: 683a ldr r2, [r7, #0]
|
|
800a144: 4904 ldr r1, [pc, #16] @ (800a158 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
800a146: 4805 ldr r0, [pc, #20] @ (800a15c <USBD_FS_InterfaceStrDescriptor+0x38>)
|
|
800a148: f7ff fe6e bl 8009e28 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
800a14c: 4b02 ldr r3, [pc, #8] @ (800a158 <USBD_FS_InterfaceStrDescriptor+0x34>)
|
|
}
|
|
800a14e: 4618 mov r0, r3
|
|
800a150: 3708 adds r7, #8
|
|
800a152: 46bd mov sp, r7
|
|
800a154: bd80 pop {r7, pc}
|
|
800a156: bf00 nop
|
|
800a158: 20000a00 .word 0x20000a00
|
|
800a15c: 0800a9e0 .word 0x0800a9e0
|
|
|
|
0800a160 <USBD_FS_USR_BOSDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
800a160: b480 push {r7}
|
|
800a162: b083 sub sp, #12
|
|
800a164: af00 add r7, sp, #0
|
|
800a166: 4603 mov r3, r0
|
|
800a168: 6039 str r1, [r7, #0]
|
|
800a16a: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_FS_BOSDesc);
|
|
800a16c: 683b ldr r3, [r7, #0]
|
|
800a16e: 220c movs r2, #12
|
|
800a170: 801a strh r2, [r3, #0]
|
|
return (uint8_t*)USBD_FS_BOSDesc;
|
|
800a172: 4b03 ldr r3, [pc, #12] @ (800a180 <USBD_FS_USR_BOSDescriptor+0x20>)
|
|
}
|
|
800a174: 4618 mov r0, r3
|
|
800a176: 370c adds r7, #12
|
|
800a178: 46bd mov sp, r7
|
|
800a17a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a17e: 4770 bx lr
|
|
800a180: 20000174 .word 0x20000174
|
|
|
|
0800a184 <Get_SerialNum>:
|
|
* @brief Create the serial number string descriptor
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void Get_SerialNum(void)
|
|
{
|
|
800a184: b580 push {r7, lr}
|
|
800a186: b084 sub sp, #16
|
|
800a188: af00 add r7, sp, #0
|
|
uint32_t deviceserial0;
|
|
uint32_t deviceserial1;
|
|
uint32_t deviceserial2;
|
|
|
|
deviceserial0 = *(uint32_t *) DEVICE_ID1;
|
|
800a18a: 4b0f ldr r3, [pc, #60] @ (800a1c8 <Get_SerialNum+0x44>)
|
|
800a18c: 681b ldr r3, [r3, #0]
|
|
800a18e: 60fb str r3, [r7, #12]
|
|
deviceserial1 = *(uint32_t *) DEVICE_ID2;
|
|
800a190: 4b0e ldr r3, [pc, #56] @ (800a1cc <Get_SerialNum+0x48>)
|
|
800a192: 681b ldr r3, [r3, #0]
|
|
800a194: 60bb str r3, [r7, #8]
|
|
deviceserial2 = *(uint32_t *) DEVICE_ID3;
|
|
800a196: 4b0e ldr r3, [pc, #56] @ (800a1d0 <Get_SerialNum+0x4c>)
|
|
800a198: 681b ldr r3, [r3, #0]
|
|
800a19a: 607b str r3, [r7, #4]
|
|
|
|
deviceserial0 += deviceserial2;
|
|
800a19c: 68fa ldr r2, [r7, #12]
|
|
800a19e: 687b ldr r3, [r7, #4]
|
|
800a1a0: 4413 add r3, r2
|
|
800a1a2: 60fb str r3, [r7, #12]
|
|
|
|
if (deviceserial0 != 0)
|
|
800a1a4: 68fb ldr r3, [r7, #12]
|
|
800a1a6: 2b00 cmp r3, #0
|
|
800a1a8: d009 beq.n 800a1be <Get_SerialNum+0x3a>
|
|
{
|
|
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
|
|
800a1aa: 2208 movs r2, #8
|
|
800a1ac: 4909 ldr r1, [pc, #36] @ (800a1d4 <Get_SerialNum+0x50>)
|
|
800a1ae: 68f8 ldr r0, [r7, #12]
|
|
800a1b0: f000 f814 bl 800a1dc <IntToUnicode>
|
|
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
|
|
800a1b4: 2204 movs r2, #4
|
|
800a1b6: 4908 ldr r1, [pc, #32] @ (800a1d8 <Get_SerialNum+0x54>)
|
|
800a1b8: 68b8 ldr r0, [r7, #8]
|
|
800a1ba: f000 f80f bl 800a1dc <IntToUnicode>
|
|
}
|
|
}
|
|
800a1be: bf00 nop
|
|
800a1c0: 3710 adds r7, #16
|
|
800a1c2: 46bd mov sp, r7
|
|
800a1c4: bd80 pop {r7, pc}
|
|
800a1c6: bf00 nop
|
|
800a1c8: 1fff7a10 .word 0x1fff7a10
|
|
800a1cc: 1fff7a14 .word 0x1fff7a14
|
|
800a1d0: 1fff7a18 .word 0x1fff7a18
|
|
800a1d4: 20000186 .word 0x20000186
|
|
800a1d8: 20000196 .word 0x20000196
|
|
|
|
0800a1dc <IntToUnicode>:
|
|
* @param pbuf: pointer to the buffer
|
|
* @param len: buffer length
|
|
* @retval None
|
|
*/
|
|
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
|
|
{
|
|
800a1dc: b480 push {r7}
|
|
800a1de: b087 sub sp, #28
|
|
800a1e0: af00 add r7, sp, #0
|
|
800a1e2: 60f8 str r0, [r7, #12]
|
|
800a1e4: 60b9 str r1, [r7, #8]
|
|
800a1e6: 4613 mov r3, r2
|
|
800a1e8: 71fb strb r3, [r7, #7]
|
|
uint8_t idx = 0;
|
|
800a1ea: 2300 movs r3, #0
|
|
800a1ec: 75fb strb r3, [r7, #23]
|
|
|
|
for (idx = 0; idx < len; idx++)
|
|
800a1ee: 2300 movs r3, #0
|
|
800a1f0: 75fb strb r3, [r7, #23]
|
|
800a1f2: e027 b.n 800a244 <IntToUnicode+0x68>
|
|
{
|
|
if (((value >> 28)) < 0xA)
|
|
800a1f4: 68fb ldr r3, [r7, #12]
|
|
800a1f6: 0f1b lsrs r3, r3, #28
|
|
800a1f8: 2b09 cmp r3, #9
|
|
800a1fa: d80b bhi.n 800a214 <IntToUnicode+0x38>
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + '0';
|
|
800a1fc: 68fb ldr r3, [r7, #12]
|
|
800a1fe: 0f1b lsrs r3, r3, #28
|
|
800a200: b2da uxtb r2, r3
|
|
800a202: 7dfb ldrb r3, [r7, #23]
|
|
800a204: 005b lsls r3, r3, #1
|
|
800a206: 4619 mov r1, r3
|
|
800a208: 68bb ldr r3, [r7, #8]
|
|
800a20a: 440b add r3, r1
|
|
800a20c: 3230 adds r2, #48 @ 0x30
|
|
800a20e: b2d2 uxtb r2, r2
|
|
800a210: 701a strb r2, [r3, #0]
|
|
800a212: e00a b.n 800a22a <IntToUnicode+0x4e>
|
|
}
|
|
else
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
|
|
800a214: 68fb ldr r3, [r7, #12]
|
|
800a216: 0f1b lsrs r3, r3, #28
|
|
800a218: b2da uxtb r2, r3
|
|
800a21a: 7dfb ldrb r3, [r7, #23]
|
|
800a21c: 005b lsls r3, r3, #1
|
|
800a21e: 4619 mov r1, r3
|
|
800a220: 68bb ldr r3, [r7, #8]
|
|
800a222: 440b add r3, r1
|
|
800a224: 3237 adds r2, #55 @ 0x37
|
|
800a226: b2d2 uxtb r2, r2
|
|
800a228: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
value = value << 4;
|
|
800a22a: 68fb ldr r3, [r7, #12]
|
|
800a22c: 011b lsls r3, r3, #4
|
|
800a22e: 60fb str r3, [r7, #12]
|
|
|
|
pbuf[2 * idx + 1] = 0;
|
|
800a230: 7dfb ldrb r3, [r7, #23]
|
|
800a232: 005b lsls r3, r3, #1
|
|
800a234: 3301 adds r3, #1
|
|
800a236: 68ba ldr r2, [r7, #8]
|
|
800a238: 4413 add r3, r2
|
|
800a23a: 2200 movs r2, #0
|
|
800a23c: 701a strb r2, [r3, #0]
|
|
for (idx = 0; idx < len; idx++)
|
|
800a23e: 7dfb ldrb r3, [r7, #23]
|
|
800a240: 3301 adds r3, #1
|
|
800a242: 75fb strb r3, [r7, #23]
|
|
800a244: 7dfa ldrb r2, [r7, #23]
|
|
800a246: 79fb ldrb r3, [r7, #7]
|
|
800a248: 429a cmp r2, r3
|
|
800a24a: d3d3 bcc.n 800a1f4 <IntToUnicode+0x18>
|
|
}
|
|
}
|
|
800a24c: bf00 nop
|
|
800a24e: bf00 nop
|
|
800a250: 371c adds r7, #28
|
|
800a252: 46bd mov sp, r7
|
|
800a254: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a258: 4770 bx lr
|
|
...
|
|
|
|
0800a25c <HAL_PCD_MspInit>:
|
|
LL Driver Callbacks (PCD -> USB Device Library)
|
|
*******************************************************************************/
|
|
/* MSP Init */
|
|
|
|
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
|
|
{
|
|
800a25c: b580 push {r7, lr}
|
|
800a25e: b0a0 sub sp, #128 @ 0x80
|
|
800a260: af00 add r7, sp, #0
|
|
800a262: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800a264: f107 036c add.w r3, r7, #108 @ 0x6c
|
|
800a268: 2200 movs r2, #0
|
|
800a26a: 601a str r2, [r3, #0]
|
|
800a26c: 605a str r2, [r3, #4]
|
|
800a26e: 609a str r2, [r3, #8]
|
|
800a270: 60da str r2, [r3, #12]
|
|
800a272: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
800a274: f107 0310 add.w r3, r7, #16
|
|
800a278: 225c movs r2, #92 @ 0x5c
|
|
800a27a: 2100 movs r1, #0
|
|
800a27c: 4618 mov r0, r3
|
|
800a27e: f000 fb53 bl 800a928 <memset>
|
|
if(pcdHandle->Instance==USB_OTG_FS)
|
|
800a282: 687b ldr r3, [r7, #4]
|
|
800a284: 681b ldr r3, [r3, #0]
|
|
800a286: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
800a28a: d149 bne.n 800a320 <HAL_PCD_MspInit+0xc4>
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
|
|
800a28c: f44f 7380 mov.w r3, #256 @ 0x100
|
|
800a290: 613b str r3, [r7, #16]
|
|
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ;
|
|
800a292: 2300 movs r3, #0
|
|
800a294: 667b str r3, [r7, #100] @ 0x64
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
800a296: f107 0310 add.w r3, r7, #16
|
|
800a29a: 4618 mov r0, r3
|
|
800a29c: f7f9 ffaa bl 80041f4 <HAL_RCCEx_PeriphCLKConfig>
|
|
800a2a0: 4603 mov r3, r0
|
|
800a2a2: 2b00 cmp r3, #0
|
|
800a2a4: d001 beq.n 800a2aa <HAL_PCD_MspInit+0x4e>
|
|
{
|
|
Error_Handler();
|
|
800a2a6: f7f6 fd7f bl 8000da8 <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800a2aa: 2300 movs r3, #0
|
|
800a2ac: 60fb str r3, [r7, #12]
|
|
800a2ae: 4b1e ldr r3, [pc, #120] @ (800a328 <HAL_PCD_MspInit+0xcc>)
|
|
800a2b0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800a2b2: 4a1d ldr r2, [pc, #116] @ (800a328 <HAL_PCD_MspInit+0xcc>)
|
|
800a2b4: f043 0301 orr.w r3, r3, #1
|
|
800a2b8: 6313 str r3, [r2, #48] @ 0x30
|
|
800a2ba: 4b1b ldr r3, [pc, #108] @ (800a328 <HAL_PCD_MspInit+0xcc>)
|
|
800a2bc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800a2be: f003 0301 and.w r3, r3, #1
|
|
800a2c2: 60fb str r3, [r7, #12]
|
|
800a2c4: 68fb ldr r3, [r7, #12]
|
|
/**USB_OTG_FS GPIO Configuration
|
|
PA11 ------> USB_OTG_FS_DM
|
|
PA12 ------> USB_OTG_FS_DP
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
|
|
800a2c6: f44f 53c0 mov.w r3, #6144 @ 0x1800
|
|
800a2ca: 66fb str r3, [r7, #108] @ 0x6c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800a2cc: 2302 movs r3, #2
|
|
800a2ce: 673b str r3, [r7, #112] @ 0x70
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800a2d0: 2300 movs r3, #0
|
|
800a2d2: 677b str r3, [r7, #116] @ 0x74
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800a2d4: 2303 movs r3, #3
|
|
800a2d6: 67bb str r3, [r7, #120] @ 0x78
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
|
|
800a2d8: 230a movs r3, #10
|
|
800a2da: 67fb str r3, [r7, #124] @ 0x7c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800a2dc: f107 036c add.w r3, r7, #108 @ 0x6c
|
|
800a2e0: 4619 mov r1, r3
|
|
800a2e2: 4812 ldr r0, [pc, #72] @ (800a32c <HAL_PCD_MspInit+0xd0>)
|
|
800a2e4: f7f8 f8dc bl 80024a0 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
|
|
800a2e8: 4b0f ldr r3, [pc, #60] @ (800a328 <HAL_PCD_MspInit+0xcc>)
|
|
800a2ea: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800a2ec: 4a0e ldr r2, [pc, #56] @ (800a328 <HAL_PCD_MspInit+0xcc>)
|
|
800a2ee: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800a2f2: 6353 str r3, [r2, #52] @ 0x34
|
|
800a2f4: 2300 movs r3, #0
|
|
800a2f6: 60bb str r3, [r7, #8]
|
|
800a2f8: 4b0b ldr r3, [pc, #44] @ (800a328 <HAL_PCD_MspInit+0xcc>)
|
|
800a2fa: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800a2fc: 4a0a ldr r2, [pc, #40] @ (800a328 <HAL_PCD_MspInit+0xcc>)
|
|
800a2fe: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
800a302: 6453 str r3, [r2, #68] @ 0x44
|
|
800a304: 4b08 ldr r3, [pc, #32] @ (800a328 <HAL_PCD_MspInit+0xcc>)
|
|
800a306: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800a308: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800a30c: 60bb str r3, [r7, #8]
|
|
800a30e: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Peripheral interrupt init */
|
|
HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
|
|
800a310: 2200 movs r2, #0
|
|
800a312: 2100 movs r1, #0
|
|
800a314: 2043 movs r0, #67 @ 0x43
|
|
800a316: f7f7 fc8a bl 8001c2e <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
|
|
800a31a: 2043 movs r0, #67 @ 0x43
|
|
800a31c: f7f7 fca3 bl 8001c66 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
|
|
|
|
/* USER CODE END USB_OTG_FS_MspInit 1 */
|
|
}
|
|
}
|
|
800a320: bf00 nop
|
|
800a322: 3780 adds r7, #128 @ 0x80
|
|
800a324: 46bd mov sp, r7
|
|
800a326: bd80 pop {r7, pc}
|
|
800a328: 40023800 .word 0x40023800
|
|
800a32c: 40020000 .word 0x40020000
|
|
|
|
0800a330 <HAL_PCD_SetupStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a330: b580 push {r7, lr}
|
|
800a332: b082 sub sp, #8
|
|
800a334: af00 add r7, sp, #0
|
|
800a336: 6078 str r0, [r7, #4]
|
|
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
|
|
800a338: 687b ldr r3, [r7, #4]
|
|
800a33a: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0
|
|
800a33e: 687b ldr r3, [r7, #4]
|
|
800a340: f203 439c addw r3, r3, #1180 @ 0x49c
|
|
800a344: 4619 mov r1, r3
|
|
800a346: 4610 mov r0, r2
|
|
800a348: f7fe fbcb bl 8008ae2 <USBD_LL_SetupStage>
|
|
}
|
|
800a34c: bf00 nop
|
|
800a34e: 3708 adds r7, #8
|
|
800a350: 46bd mov sp, r7
|
|
800a352: bd80 pop {r7, pc}
|
|
|
|
0800a354 <HAL_PCD_DataOutStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a354: b580 push {r7, lr}
|
|
800a356: b082 sub sp, #8
|
|
800a358: af00 add r7, sp, #0
|
|
800a35a: 6078 str r0, [r7, #4]
|
|
800a35c: 460b mov r3, r1
|
|
800a35e: 70fb strb r3, [r7, #3]
|
|
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
|
|
800a360: 687b ldr r3, [r7, #4]
|
|
800a362: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
|
|
800a366: 78fa ldrb r2, [r7, #3]
|
|
800a368: 6879 ldr r1, [r7, #4]
|
|
800a36a: 4613 mov r3, r2
|
|
800a36c: 00db lsls r3, r3, #3
|
|
800a36e: 4413 add r3, r2
|
|
800a370: 009b lsls r3, r3, #2
|
|
800a372: 440b add r3, r1
|
|
800a374: f503 7318 add.w r3, r3, #608 @ 0x260
|
|
800a378: 681a ldr r2, [r3, #0]
|
|
800a37a: 78fb ldrb r3, [r7, #3]
|
|
800a37c: 4619 mov r1, r3
|
|
800a37e: f7fe fc05 bl 8008b8c <USBD_LL_DataOutStage>
|
|
}
|
|
800a382: bf00 nop
|
|
800a384: 3708 adds r7, #8
|
|
800a386: 46bd mov sp, r7
|
|
800a388: bd80 pop {r7, pc}
|
|
|
|
0800a38a <HAL_PCD_DataInStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a38a: b580 push {r7, lr}
|
|
800a38c: b082 sub sp, #8
|
|
800a38e: af00 add r7, sp, #0
|
|
800a390: 6078 str r0, [r7, #4]
|
|
800a392: 460b mov r3, r1
|
|
800a394: 70fb strb r3, [r7, #3]
|
|
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
|
|
800a396: 687b ldr r3, [r7, #4]
|
|
800a398: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0
|
|
800a39c: 78fa ldrb r2, [r7, #3]
|
|
800a39e: 6879 ldr r1, [r7, #4]
|
|
800a3a0: 4613 mov r3, r2
|
|
800a3a2: 00db lsls r3, r3, #3
|
|
800a3a4: 4413 add r3, r2
|
|
800a3a6: 009b lsls r3, r3, #2
|
|
800a3a8: 440b add r3, r1
|
|
800a3aa: 3320 adds r3, #32
|
|
800a3ac: 681a ldr r2, [r3, #0]
|
|
800a3ae: 78fb ldrb r3, [r7, #3]
|
|
800a3b0: 4619 mov r1, r3
|
|
800a3b2: f7fe fca7 bl 8008d04 <USBD_LL_DataInStage>
|
|
}
|
|
800a3b6: bf00 nop
|
|
800a3b8: 3708 adds r7, #8
|
|
800a3ba: 46bd mov sp, r7
|
|
800a3bc: bd80 pop {r7, pc}
|
|
|
|
0800a3be <HAL_PCD_SOFCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a3be: b580 push {r7, lr}
|
|
800a3c0: b082 sub sp, #8
|
|
800a3c2: af00 add r7, sp, #0
|
|
800a3c4: 6078 str r0, [r7, #4]
|
|
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
|
|
800a3c6: 687b ldr r3, [r7, #4]
|
|
800a3c8: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a3cc: 4618 mov r0, r3
|
|
800a3ce: f7fe fdeb bl 8008fa8 <USBD_LL_SOF>
|
|
}
|
|
800a3d2: bf00 nop
|
|
800a3d4: 3708 adds r7, #8
|
|
800a3d6: 46bd mov sp, r7
|
|
800a3d8: bd80 pop {r7, pc}
|
|
|
|
0800a3da <HAL_PCD_ResetCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a3da: b580 push {r7, lr}
|
|
800a3dc: b084 sub sp, #16
|
|
800a3de: af00 add r7, sp, #0
|
|
800a3e0: 6078 str r0, [r7, #4]
|
|
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
|
|
800a3e2: 2301 movs r3, #1
|
|
800a3e4: 73fb strb r3, [r7, #15]
|
|
|
|
if ( hpcd->Init.speed == PCD_SPEED_HIGH)
|
|
800a3e6: 687b ldr r3, [r7, #4]
|
|
800a3e8: 79db ldrb r3, [r3, #7]
|
|
800a3ea: 2b00 cmp r3, #0
|
|
800a3ec: d102 bne.n 800a3f4 <HAL_PCD_ResetCallback+0x1a>
|
|
{
|
|
speed = USBD_SPEED_HIGH;
|
|
800a3ee: 2300 movs r3, #0
|
|
800a3f0: 73fb strb r3, [r7, #15]
|
|
800a3f2: e008 b.n 800a406 <HAL_PCD_ResetCallback+0x2c>
|
|
}
|
|
else if ( hpcd->Init.speed == PCD_SPEED_FULL)
|
|
800a3f4: 687b ldr r3, [r7, #4]
|
|
800a3f6: 79db ldrb r3, [r3, #7]
|
|
800a3f8: 2b02 cmp r3, #2
|
|
800a3fa: d102 bne.n 800a402 <HAL_PCD_ResetCallback+0x28>
|
|
{
|
|
speed = USBD_SPEED_FULL;
|
|
800a3fc: 2301 movs r3, #1
|
|
800a3fe: 73fb strb r3, [r7, #15]
|
|
800a400: e001 b.n 800a406 <HAL_PCD_ResetCallback+0x2c>
|
|
}
|
|
else
|
|
{
|
|
Error_Handler();
|
|
800a402: f7f6 fcd1 bl 8000da8 <Error_Handler>
|
|
}
|
|
/* Set Speed. */
|
|
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
|
|
800a406: 687b ldr r3, [r7, #4]
|
|
800a408: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a40c: 7bfa ldrb r2, [r7, #15]
|
|
800a40e: 4611 mov r1, r2
|
|
800a410: 4618 mov r0, r3
|
|
800a412: f7fe fd85 bl 8008f20 <USBD_LL_SetSpeed>
|
|
|
|
/* Reset Device. */
|
|
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
|
|
800a416: 687b ldr r3, [r7, #4]
|
|
800a418: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a41c: 4618 mov r0, r3
|
|
800a41e: f7fe fd2c bl 8008e7a <USBD_LL_Reset>
|
|
}
|
|
800a422: bf00 nop
|
|
800a424: 3710 adds r7, #16
|
|
800a426: 46bd mov sp, r7
|
|
800a428: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800a42c <HAL_PCD_SuspendCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a42c: b580 push {r7, lr}
|
|
800a42e: b082 sub sp, #8
|
|
800a430: af00 add r7, sp, #0
|
|
800a432: 6078 str r0, [r7, #4]
|
|
/* Inform USB library that core enters in suspend Mode. */
|
|
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
|
|
800a434: 687b ldr r3, [r7, #4]
|
|
800a436: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a43a: 4618 mov r0, r3
|
|
800a43c: f7fe fd80 bl 8008f40 <USBD_LL_Suspend>
|
|
__HAL_PCD_GATE_PHYCLOCK(hpcd);
|
|
800a440: 687b ldr r3, [r7, #4]
|
|
800a442: 681b ldr r3, [r3, #0]
|
|
800a444: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
800a448: 681b ldr r3, [r3, #0]
|
|
800a44a: 687a ldr r2, [r7, #4]
|
|
800a44c: 6812 ldr r2, [r2, #0]
|
|
800a44e: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
800a452: f043 0301 orr.w r3, r3, #1
|
|
800a456: 6013 str r3, [r2, #0]
|
|
/* Enter in STOP mode. */
|
|
/* USER CODE BEGIN 2 */
|
|
if (hpcd->Init.low_power_enable)
|
|
800a458: 687b ldr r3, [r7, #4]
|
|
800a45a: 7adb ldrb r3, [r3, #11]
|
|
800a45c: 2b00 cmp r3, #0
|
|
800a45e: d005 beq.n 800a46c <HAL_PCD_SuspendCallback+0x40>
|
|
{
|
|
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
800a460: 4b04 ldr r3, [pc, #16] @ (800a474 <HAL_PCD_SuspendCallback+0x48>)
|
|
800a462: 691b ldr r3, [r3, #16]
|
|
800a464: 4a03 ldr r2, [pc, #12] @ (800a474 <HAL_PCD_SuspendCallback+0x48>)
|
|
800a466: f043 0306 orr.w r3, r3, #6
|
|
800a46a: 6113 str r3, [r2, #16]
|
|
}
|
|
/* USER CODE END 2 */
|
|
}
|
|
800a46c: bf00 nop
|
|
800a46e: 3708 adds r7, #8
|
|
800a470: 46bd mov sp, r7
|
|
800a472: bd80 pop {r7, pc}
|
|
800a474: e000ed00 .word 0xe000ed00
|
|
|
|
0800a478 <HAL_PCD_ResumeCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a478: b580 push {r7, lr}
|
|
800a47a: b082 sub sp, #8
|
|
800a47c: af00 add r7, sp, #0
|
|
800a47e: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN 3 */
|
|
|
|
/* USER CODE END 3 */
|
|
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
|
|
800a480: 687b ldr r3, [r7, #4]
|
|
800a482: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a486: 4618 mov r0, r3
|
|
800a488: f7fe fd76 bl 8008f78 <USBD_LL_Resume>
|
|
}
|
|
800a48c: bf00 nop
|
|
800a48e: 3708 adds r7, #8
|
|
800a490: 46bd mov sp, r7
|
|
800a492: bd80 pop {r7, pc}
|
|
|
|
0800a494 <HAL_PCD_ISOOUTIncompleteCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a494: b580 push {r7, lr}
|
|
800a496: b082 sub sp, #8
|
|
800a498: af00 add r7, sp, #0
|
|
800a49a: 6078 str r0, [r7, #4]
|
|
800a49c: 460b mov r3, r1
|
|
800a49e: 70fb strb r3, [r7, #3]
|
|
USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
|
|
800a4a0: 687b ldr r3, [r7, #4]
|
|
800a4a2: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a4a6: 78fa ldrb r2, [r7, #3]
|
|
800a4a8: 4611 mov r1, r2
|
|
800a4aa: 4618 mov r0, r3
|
|
800a4ac: f7fe fdce bl 800904c <USBD_LL_IsoOUTIncomplete>
|
|
}
|
|
800a4b0: bf00 nop
|
|
800a4b2: 3708 adds r7, #8
|
|
800a4b4: 46bd mov sp, r7
|
|
800a4b6: bd80 pop {r7, pc}
|
|
|
|
0800a4b8 <HAL_PCD_ISOINIncompleteCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a4b8: b580 push {r7, lr}
|
|
800a4ba: b082 sub sp, #8
|
|
800a4bc: af00 add r7, sp, #0
|
|
800a4be: 6078 str r0, [r7, #4]
|
|
800a4c0: 460b mov r3, r1
|
|
800a4c2: 70fb strb r3, [r7, #3]
|
|
USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
|
|
800a4c4: 687b ldr r3, [r7, #4]
|
|
800a4c6: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a4ca: 78fa ldrb r2, [r7, #3]
|
|
800a4cc: 4611 mov r1, r2
|
|
800a4ce: 4618 mov r0, r3
|
|
800a4d0: f7fe fd8a bl 8008fe8 <USBD_LL_IsoINIncomplete>
|
|
}
|
|
800a4d4: bf00 nop
|
|
800a4d6: 3708 adds r7, #8
|
|
800a4d8: 46bd mov sp, r7
|
|
800a4da: bd80 pop {r7, pc}
|
|
|
|
0800a4dc <HAL_PCD_ConnectCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a4dc: b580 push {r7, lr}
|
|
800a4de: b082 sub sp, #8
|
|
800a4e0: af00 add r7, sp, #0
|
|
800a4e2: 6078 str r0, [r7, #4]
|
|
USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
|
|
800a4e4: 687b ldr r3, [r7, #4]
|
|
800a4e6: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a4ea: 4618 mov r0, r3
|
|
800a4ec: f7fe fde0 bl 80090b0 <USBD_LL_DevConnected>
|
|
}
|
|
800a4f0: bf00 nop
|
|
800a4f2: 3708 adds r7, #8
|
|
800a4f4: 46bd mov sp, r7
|
|
800a4f6: bd80 pop {r7, pc}
|
|
|
|
0800a4f8 <HAL_PCD_DisconnectCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
800a4f8: b580 push {r7, lr}
|
|
800a4fa: b082 sub sp, #8
|
|
800a4fc: af00 add r7, sp, #0
|
|
800a4fe: 6078 str r0, [r7, #4]
|
|
USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
|
|
800a500: 687b ldr r3, [r7, #4]
|
|
800a502: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a506: 4618 mov r0, r3
|
|
800a508: f7fe fddd bl 80090c6 <USBD_LL_DevDisconnected>
|
|
}
|
|
800a50c: bf00 nop
|
|
800a50e: 3708 adds r7, #8
|
|
800a510: 46bd mov sp, r7
|
|
800a512: bd80 pop {r7, pc}
|
|
|
|
0800a514 <USBD_LL_Init>:
|
|
* @brief Initializes the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
|
|
{
|
|
800a514: b580 push {r7, lr}
|
|
800a516: b082 sub sp, #8
|
|
800a518: af00 add r7, sp, #0
|
|
800a51a: 6078 str r0, [r7, #4]
|
|
/* Init USB Ip. */
|
|
if (pdev->id == DEVICE_FS) {
|
|
800a51c: 687b ldr r3, [r7, #4]
|
|
800a51e: 781b ldrb r3, [r3, #0]
|
|
800a520: 2b00 cmp r3, #0
|
|
800a522: d13c bne.n 800a59e <USBD_LL_Init+0x8a>
|
|
/* Link the driver to the stack. */
|
|
hpcd_USB_OTG_FS.pData = pdev;
|
|
800a524: 4a20 ldr r2, [pc, #128] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a526: 687b ldr r3, [r7, #4]
|
|
800a528: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0
|
|
pdev->pData = &hpcd_USB_OTG_FS;
|
|
800a52c: 687b ldr r3, [r7, #4]
|
|
800a52e: 4a1e ldr r2, [pc, #120] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a530: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8
|
|
|
|
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
|
|
800a534: 4b1c ldr r3, [pc, #112] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a536: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
|
|
800a53a: 601a str r2, [r3, #0]
|
|
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
|
|
800a53c: 4b1a ldr r3, [pc, #104] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a53e: 2206 movs r2, #6
|
|
800a540: 711a strb r2, [r3, #4]
|
|
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
|
|
800a542: 4b19 ldr r3, [pc, #100] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a544: 2202 movs r2, #2
|
|
800a546: 71da strb r2, [r3, #7]
|
|
hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
|
|
800a548: 4b17 ldr r3, [pc, #92] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a54a: 2200 movs r2, #0
|
|
800a54c: 719a strb r2, [r3, #6]
|
|
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
|
|
800a54e: 4b16 ldr r3, [pc, #88] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a550: 2202 movs r2, #2
|
|
800a552: 725a strb r2, [r3, #9]
|
|
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
|
|
800a554: 4b14 ldr r3, [pc, #80] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a556: 2200 movs r2, #0
|
|
800a558: 729a strb r2, [r3, #10]
|
|
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
|
|
800a55a: 4b13 ldr r3, [pc, #76] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a55c: 2200 movs r2, #0
|
|
800a55e: 72da strb r2, [r3, #11]
|
|
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
|
|
800a560: 4b11 ldr r3, [pc, #68] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a562: 2200 movs r2, #0
|
|
800a564: 731a strb r2, [r3, #12]
|
|
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
|
|
800a566: 4b10 ldr r3, [pc, #64] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a568: 2200 movs r2, #0
|
|
800a56a: 739a strb r2, [r3, #14]
|
|
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
|
|
800a56c: 4b0e ldr r3, [pc, #56] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a56e: 2200 movs r2, #0
|
|
800a570: 73da strb r2, [r3, #15]
|
|
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
|
|
800a572: 480d ldr r0, [pc, #52] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a574: f7f8 fa9e bl 8002ab4 <HAL_PCD_Init>
|
|
800a578: 4603 mov r3, r0
|
|
800a57a: 2b00 cmp r3, #0
|
|
800a57c: d001 beq.n 800a582 <USBD_LL_Init+0x6e>
|
|
{
|
|
Error_Handler( );
|
|
800a57e: f7f6 fc13 bl 8000da8 <Error_Handler>
|
|
HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback);
|
|
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback);
|
|
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
|
|
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
|
|
800a582: 2180 movs r1, #128 @ 0x80
|
|
800a584: 4808 ldr r0, [pc, #32] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a586: f7f9 fce6 bl 8003f56 <HAL_PCDEx_SetRxFiFo>
|
|
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
|
|
800a58a: 2240 movs r2, #64 @ 0x40
|
|
800a58c: 2100 movs r1, #0
|
|
800a58e: 4806 ldr r0, [pc, #24] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a590: f7f9 fc9a bl 8003ec8 <HAL_PCDEx_SetTxFiFo>
|
|
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
|
|
800a594: 2280 movs r2, #128 @ 0x80
|
|
800a596: 2101 movs r1, #1
|
|
800a598: 4803 ldr r0, [pc, #12] @ (800a5a8 <USBD_LL_Init+0x94>)
|
|
800a59a: f7f9 fc95 bl 8003ec8 <HAL_PCDEx_SetTxFiFo>
|
|
}
|
|
return USBD_OK;
|
|
800a59e: 2300 movs r3, #0
|
|
}
|
|
800a5a0: 4618 mov r0, r3
|
|
800a5a2: 3708 adds r7, #8
|
|
800a5a4: 46bd mov sp, r7
|
|
800a5a6: bd80 pop {r7, pc}
|
|
800a5a8: 20000c00 .word 0x20000c00
|
|
|
|
0800a5ac <USBD_LL_Start>:
|
|
* @brief Starts the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
800a5ac: b580 push {r7, lr}
|
|
800a5ae: b084 sub sp, #16
|
|
800a5b0: af00 add r7, sp, #0
|
|
800a5b2: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800a5b4: 2300 movs r3, #0
|
|
800a5b6: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800a5b8: 2300 movs r3, #0
|
|
800a5ba: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_Start(pdev->pData);
|
|
800a5bc: 687b ldr r3, [r7, #4]
|
|
800a5be: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800a5c2: 4618 mov r0, r3
|
|
800a5c4: f7f8 fb8c bl 8002ce0 <HAL_PCD_Start>
|
|
800a5c8: 4603 mov r3, r0
|
|
800a5ca: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800a5cc: 7bfb ldrb r3, [r7, #15]
|
|
800a5ce: 4618 mov r0, r3
|
|
800a5d0: f000 f97e bl 800a8d0 <USBD_Get_USB_Status>
|
|
800a5d4: 4603 mov r3, r0
|
|
800a5d6: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800a5d8: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800a5da: 4618 mov r0, r3
|
|
800a5dc: 3710 adds r7, #16
|
|
800a5de: 46bd mov sp, r7
|
|
800a5e0: bd80 pop {r7, pc}
|
|
|
|
0800a5e2 <USBD_LL_OpenEP>:
|
|
* @param ep_type: Endpoint type
|
|
* @param ep_mps: Endpoint max packet size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
|
|
{
|
|
800a5e2: b580 push {r7, lr}
|
|
800a5e4: b084 sub sp, #16
|
|
800a5e6: af00 add r7, sp, #0
|
|
800a5e8: 6078 str r0, [r7, #4]
|
|
800a5ea: 4608 mov r0, r1
|
|
800a5ec: 4611 mov r1, r2
|
|
800a5ee: 461a mov r2, r3
|
|
800a5f0: 4603 mov r3, r0
|
|
800a5f2: 70fb strb r3, [r7, #3]
|
|
800a5f4: 460b mov r3, r1
|
|
800a5f6: 70bb strb r3, [r7, #2]
|
|
800a5f8: 4613 mov r3, r2
|
|
800a5fa: 803b strh r3, [r7, #0]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800a5fc: 2300 movs r3, #0
|
|
800a5fe: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800a600: 2300 movs r3, #0
|
|
800a602: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
|
|
800a604: 687b ldr r3, [r7, #4]
|
|
800a606: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
800a60a: 78bb ldrb r3, [r7, #2]
|
|
800a60c: 883a ldrh r2, [r7, #0]
|
|
800a60e: 78f9 ldrb r1, [r7, #3]
|
|
800a610: f7f9 f88d bl 800372e <HAL_PCD_EP_Open>
|
|
800a614: 4603 mov r3, r0
|
|
800a616: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800a618: 7bfb ldrb r3, [r7, #15]
|
|
800a61a: 4618 mov r0, r3
|
|
800a61c: f000 f958 bl 800a8d0 <USBD_Get_USB_Status>
|
|
800a620: 4603 mov r3, r0
|
|
800a622: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800a624: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800a626: 4618 mov r0, r3
|
|
800a628: 3710 adds r7, #16
|
|
800a62a: 46bd mov sp, r7
|
|
800a62c: bd80 pop {r7, pc}
|
|
|
|
0800a62e <USBD_LL_CloseEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
800a62e: b580 push {r7, lr}
|
|
800a630: b084 sub sp, #16
|
|
800a632: af00 add r7, sp, #0
|
|
800a634: 6078 str r0, [r7, #4]
|
|
800a636: 460b mov r3, r1
|
|
800a638: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800a63a: 2300 movs r3, #0
|
|
800a63c: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800a63e: 2300 movs r3, #0
|
|
800a640: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
|
|
800a642: 687b ldr r3, [r7, #4]
|
|
800a644: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800a648: 78fa ldrb r2, [r7, #3]
|
|
800a64a: 4611 mov r1, r2
|
|
800a64c: 4618 mov r0, r3
|
|
800a64e: f7f9 f8d8 bl 8003802 <HAL_PCD_EP_Close>
|
|
800a652: 4603 mov r3, r0
|
|
800a654: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800a656: 7bfb ldrb r3, [r7, #15]
|
|
800a658: 4618 mov r0, r3
|
|
800a65a: f000 f939 bl 800a8d0 <USBD_Get_USB_Status>
|
|
800a65e: 4603 mov r3, r0
|
|
800a660: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800a662: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800a664: 4618 mov r0, r3
|
|
800a666: 3710 adds r7, #16
|
|
800a668: 46bd mov sp, r7
|
|
800a66a: bd80 pop {r7, pc}
|
|
|
|
0800a66c <USBD_LL_StallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
800a66c: b580 push {r7, lr}
|
|
800a66e: b084 sub sp, #16
|
|
800a670: af00 add r7, sp, #0
|
|
800a672: 6078 str r0, [r7, #4]
|
|
800a674: 460b mov r3, r1
|
|
800a676: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800a678: 2300 movs r3, #0
|
|
800a67a: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800a67c: 2300 movs r3, #0
|
|
800a67e: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
|
|
800a680: 687b ldr r3, [r7, #4]
|
|
800a682: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800a686: 78fa ldrb r2, [r7, #3]
|
|
800a688: 4611 mov r1, r2
|
|
800a68a: 4618 mov r0, r3
|
|
800a68c: f7f9 f978 bl 8003980 <HAL_PCD_EP_SetStall>
|
|
800a690: 4603 mov r3, r0
|
|
800a692: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800a694: 7bfb ldrb r3, [r7, #15]
|
|
800a696: 4618 mov r0, r3
|
|
800a698: f000 f91a bl 800a8d0 <USBD_Get_USB_Status>
|
|
800a69c: 4603 mov r3, r0
|
|
800a69e: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800a6a0: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800a6a2: 4618 mov r0, r3
|
|
800a6a4: 3710 adds r7, #16
|
|
800a6a6: 46bd mov sp, r7
|
|
800a6a8: bd80 pop {r7, pc}
|
|
|
|
0800a6aa <USBD_LL_ClearStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
800a6aa: b580 push {r7, lr}
|
|
800a6ac: b084 sub sp, #16
|
|
800a6ae: af00 add r7, sp, #0
|
|
800a6b0: 6078 str r0, [r7, #4]
|
|
800a6b2: 460b mov r3, r1
|
|
800a6b4: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800a6b6: 2300 movs r3, #0
|
|
800a6b8: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800a6ba: 2300 movs r3, #0
|
|
800a6bc: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
|
|
800a6be: 687b ldr r3, [r7, #4]
|
|
800a6c0: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800a6c4: 78fa ldrb r2, [r7, #3]
|
|
800a6c6: 4611 mov r1, r2
|
|
800a6c8: 4618 mov r0, r3
|
|
800a6ca: f7f9 f9bc bl 8003a46 <HAL_PCD_EP_ClrStall>
|
|
800a6ce: 4603 mov r3, r0
|
|
800a6d0: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800a6d2: 7bfb ldrb r3, [r7, #15]
|
|
800a6d4: 4618 mov r0, r3
|
|
800a6d6: f000 f8fb bl 800a8d0 <USBD_Get_USB_Status>
|
|
800a6da: 4603 mov r3, r0
|
|
800a6dc: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800a6de: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800a6e0: 4618 mov r0, r3
|
|
800a6e2: 3710 adds r7, #16
|
|
800a6e4: 46bd mov sp, r7
|
|
800a6e6: bd80 pop {r7, pc}
|
|
|
|
0800a6e8 <USBD_LL_IsStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval Stall (1: Yes, 0: No)
|
|
*/
|
|
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
800a6e8: b480 push {r7}
|
|
800a6ea: b085 sub sp, #20
|
|
800a6ec: af00 add r7, sp, #0
|
|
800a6ee: 6078 str r0, [r7, #4]
|
|
800a6f0: 460b mov r3, r1
|
|
800a6f2: 70fb strb r3, [r7, #3]
|
|
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
|
|
800a6f4: 687b ldr r3, [r7, #4]
|
|
800a6f6: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800a6fa: 60fb str r3, [r7, #12]
|
|
|
|
if((ep_addr & 0x80) == 0x80)
|
|
800a6fc: f997 3003 ldrsb.w r3, [r7, #3]
|
|
800a700: 2b00 cmp r3, #0
|
|
800a702: da0b bge.n 800a71c <USBD_LL_IsStallEP+0x34>
|
|
{
|
|
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
|
|
800a704: 78fb ldrb r3, [r7, #3]
|
|
800a706: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
800a70a: 68f9 ldr r1, [r7, #12]
|
|
800a70c: 4613 mov r3, r2
|
|
800a70e: 00db lsls r3, r3, #3
|
|
800a710: 4413 add r3, r2
|
|
800a712: 009b lsls r3, r3, #2
|
|
800a714: 440b add r3, r1
|
|
800a716: 3316 adds r3, #22
|
|
800a718: 781b ldrb r3, [r3, #0]
|
|
800a71a: e00b b.n 800a734 <USBD_LL_IsStallEP+0x4c>
|
|
}
|
|
else
|
|
{
|
|
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
|
|
800a71c: 78fb ldrb r3, [r7, #3]
|
|
800a71e: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
800a722: 68f9 ldr r1, [r7, #12]
|
|
800a724: 4613 mov r3, r2
|
|
800a726: 00db lsls r3, r3, #3
|
|
800a728: 4413 add r3, r2
|
|
800a72a: 009b lsls r3, r3, #2
|
|
800a72c: 440b add r3, r1
|
|
800a72e: f203 2356 addw r3, r3, #598 @ 0x256
|
|
800a732: 781b ldrb r3, [r3, #0]
|
|
}
|
|
}
|
|
800a734: 4618 mov r0, r3
|
|
800a736: 3714 adds r7, #20
|
|
800a738: 46bd mov sp, r7
|
|
800a73a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a73e: 4770 bx lr
|
|
|
|
0800a740 <USBD_LL_SetUSBAddress>:
|
|
* @param pdev: Device handle
|
|
* @param dev_addr: Device address
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
|
|
{
|
|
800a740: b580 push {r7, lr}
|
|
800a742: b084 sub sp, #16
|
|
800a744: af00 add r7, sp, #0
|
|
800a746: 6078 str r0, [r7, #4]
|
|
800a748: 460b mov r3, r1
|
|
800a74a: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800a74c: 2300 movs r3, #0
|
|
800a74e: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800a750: 2300 movs r3, #0
|
|
800a752: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
|
|
800a754: 687b ldr r3, [r7, #4]
|
|
800a756: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
800a75a: 78fa ldrb r2, [r7, #3]
|
|
800a75c: 4611 mov r1, r2
|
|
800a75e: 4618 mov r0, r3
|
|
800a760: f7f8 ffc1 bl 80036e6 <HAL_PCD_SetAddress>
|
|
800a764: 4603 mov r3, r0
|
|
800a766: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800a768: 7bfb ldrb r3, [r7, #15]
|
|
800a76a: 4618 mov r0, r3
|
|
800a76c: f000 f8b0 bl 800a8d0 <USBD_Get_USB_Status>
|
|
800a770: 4603 mov r3, r0
|
|
800a772: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800a774: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800a776: 4618 mov r0, r3
|
|
800a778: 3710 adds r7, #16
|
|
800a77a: 46bd mov sp, r7
|
|
800a77c: bd80 pop {r7, pc}
|
|
|
|
0800a77e <USBD_LL_Transmit>:
|
|
* @param pbuf: Pointer to data to be sent
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
|
|
{
|
|
800a77e: b580 push {r7, lr}
|
|
800a780: b086 sub sp, #24
|
|
800a782: af00 add r7, sp, #0
|
|
800a784: 60f8 str r0, [r7, #12]
|
|
800a786: 607a str r2, [r7, #4]
|
|
800a788: 603b str r3, [r7, #0]
|
|
800a78a: 460b mov r3, r1
|
|
800a78c: 72fb strb r3, [r7, #11]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800a78e: 2300 movs r3, #0
|
|
800a790: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800a792: 2300 movs r3, #0
|
|
800a794: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
|
|
800a796: 68fb ldr r3, [r7, #12]
|
|
800a798: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
800a79c: 7af9 ldrb r1, [r7, #11]
|
|
800a79e: 683b ldr r3, [r7, #0]
|
|
800a7a0: 687a ldr r2, [r7, #4]
|
|
800a7a2: f7f9 f8b3 bl 800390c <HAL_PCD_EP_Transmit>
|
|
800a7a6: 4603 mov r3, r0
|
|
800a7a8: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800a7aa: 7dfb ldrb r3, [r7, #23]
|
|
800a7ac: 4618 mov r0, r3
|
|
800a7ae: f000 f88f bl 800a8d0 <USBD_Get_USB_Status>
|
|
800a7b2: 4603 mov r3, r0
|
|
800a7b4: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
800a7b6: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
800a7b8: 4618 mov r0, r3
|
|
800a7ba: 3718 adds r7, #24
|
|
800a7bc: 46bd mov sp, r7
|
|
800a7be: bd80 pop {r7, pc}
|
|
|
|
0800a7c0 <USBD_LL_PrepareReceive>:
|
|
* @param pbuf: Pointer to data to be received
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
|
|
{
|
|
800a7c0: b580 push {r7, lr}
|
|
800a7c2: b086 sub sp, #24
|
|
800a7c4: af00 add r7, sp, #0
|
|
800a7c6: 60f8 str r0, [r7, #12]
|
|
800a7c8: 607a str r2, [r7, #4]
|
|
800a7ca: 603b str r3, [r7, #0]
|
|
800a7cc: 460b mov r3, r1
|
|
800a7ce: 72fb strb r3, [r7, #11]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800a7d0: 2300 movs r3, #0
|
|
800a7d2: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800a7d4: 2300 movs r3, #0
|
|
800a7d6: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
|
|
800a7d8: 68fb ldr r3, [r7, #12]
|
|
800a7da: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
800a7de: 7af9 ldrb r1, [r7, #11]
|
|
800a7e0: 683b ldr r3, [r7, #0]
|
|
800a7e2: 687a ldr r2, [r7, #4]
|
|
800a7e4: f7f9 f857 bl 8003896 <HAL_PCD_EP_Receive>
|
|
800a7e8: 4603 mov r3, r0
|
|
800a7ea: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
800a7ec: 7dfb ldrb r3, [r7, #23]
|
|
800a7ee: 4618 mov r0, r3
|
|
800a7f0: f000 f86e bl 800a8d0 <USBD_Get_USB_Status>
|
|
800a7f4: 4603 mov r3, r0
|
|
800a7f6: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
800a7f8: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
800a7fa: 4618 mov r0, r3
|
|
800a7fc: 3718 adds r7, #24
|
|
800a7fe: 46bd mov sp, r7
|
|
800a800: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800a804 <HAL_PCDEx_LPM_Callback>:
|
|
* @param hpcd: PCD handle
|
|
* @param msg: LPM message
|
|
* @retval None
|
|
*/
|
|
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
|
|
{
|
|
800a804: b580 push {r7, lr}
|
|
800a806: b082 sub sp, #8
|
|
800a808: af00 add r7, sp, #0
|
|
800a80a: 6078 str r0, [r7, #4]
|
|
800a80c: 460b mov r3, r1
|
|
800a80e: 70fb strb r3, [r7, #3]
|
|
switch (msg)
|
|
800a810: 78fb ldrb r3, [r7, #3]
|
|
800a812: 2b00 cmp r3, #0
|
|
800a814: d002 beq.n 800a81c <HAL_PCDEx_LPM_Callback+0x18>
|
|
800a816: 2b01 cmp r3, #1
|
|
800a818: d01f beq.n 800a85a <HAL_PCDEx_LPM_Callback+0x56>
|
|
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
800a81a: e03b b.n 800a894 <HAL_PCDEx_LPM_Callback+0x90>
|
|
if (hpcd->Init.low_power_enable)
|
|
800a81c: 687b ldr r3, [r7, #4]
|
|
800a81e: 7adb ldrb r3, [r3, #11]
|
|
800a820: 2b00 cmp r3, #0
|
|
800a822: d007 beq.n 800a834 <HAL_PCDEx_LPM_Callback+0x30>
|
|
SystemClock_Config();
|
|
800a824: f7f6 f8b6 bl 8000994 <SystemClock_Config>
|
|
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
800a828: 4b1c ldr r3, [pc, #112] @ (800a89c <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800a82a: 691b ldr r3, [r3, #16]
|
|
800a82c: 4a1b ldr r2, [pc, #108] @ (800a89c <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800a82e: f023 0306 bic.w r3, r3, #6
|
|
800a832: 6113 str r3, [r2, #16]
|
|
__HAL_PCD_UNGATE_PHYCLOCK(hpcd);
|
|
800a834: 687b ldr r3, [r7, #4]
|
|
800a836: 681b ldr r3, [r3, #0]
|
|
800a838: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
800a83c: 681b ldr r3, [r3, #0]
|
|
800a83e: 687a ldr r2, [r7, #4]
|
|
800a840: 6812 ldr r2, [r2, #0]
|
|
800a842: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
800a846: f023 0301 bic.w r3, r3, #1
|
|
800a84a: 6013 str r3, [r2, #0]
|
|
USBD_LL_Resume(hpcd->pData);
|
|
800a84c: 687b ldr r3, [r7, #4]
|
|
800a84e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a852: 4618 mov r0, r3
|
|
800a854: f7fe fb90 bl 8008f78 <USBD_LL_Resume>
|
|
break;
|
|
800a858: e01c b.n 800a894 <HAL_PCDEx_LPM_Callback+0x90>
|
|
__HAL_PCD_GATE_PHYCLOCK(hpcd);
|
|
800a85a: 687b ldr r3, [r7, #4]
|
|
800a85c: 681b ldr r3, [r3, #0]
|
|
800a85e: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
800a862: 681b ldr r3, [r3, #0]
|
|
800a864: 687a ldr r2, [r7, #4]
|
|
800a866: 6812 ldr r2, [r2, #0]
|
|
800a868: f502 6260 add.w r2, r2, #3584 @ 0xe00
|
|
800a86c: f043 0301 orr.w r3, r3, #1
|
|
800a870: 6013 str r3, [r2, #0]
|
|
USBD_LL_Suspend(hpcd->pData);
|
|
800a872: 687b ldr r3, [r7, #4]
|
|
800a874: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0
|
|
800a878: 4618 mov r0, r3
|
|
800a87a: f7fe fb61 bl 8008f40 <USBD_LL_Suspend>
|
|
if (hpcd->Init.low_power_enable)
|
|
800a87e: 687b ldr r3, [r7, #4]
|
|
800a880: 7adb ldrb r3, [r3, #11]
|
|
800a882: 2b00 cmp r3, #0
|
|
800a884: d005 beq.n 800a892 <HAL_PCDEx_LPM_Callback+0x8e>
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
800a886: 4b05 ldr r3, [pc, #20] @ (800a89c <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800a888: 691b ldr r3, [r3, #16]
|
|
800a88a: 4a04 ldr r2, [pc, #16] @ (800a89c <HAL_PCDEx_LPM_Callback+0x98>)
|
|
800a88c: f043 0306 orr.w r3, r3, #6
|
|
800a890: 6113 str r3, [r2, #16]
|
|
break;
|
|
800a892: bf00 nop
|
|
}
|
|
800a894: bf00 nop
|
|
800a896: 3708 adds r7, #8
|
|
800a898: 46bd mov sp, r7
|
|
800a89a: bd80 pop {r7, pc}
|
|
800a89c: e000ed00 .word 0xe000ed00
|
|
|
|
0800a8a0 <USBD_static_malloc>:
|
|
* @brief Static single allocation.
|
|
* @param size: Size of allocated memory
|
|
* @retval None
|
|
*/
|
|
void *USBD_static_malloc(uint32_t size)
|
|
{
|
|
800a8a0: b480 push {r7}
|
|
800a8a2: b083 sub sp, #12
|
|
800a8a4: af00 add r7, sp, #0
|
|
800a8a6: 6078 str r0, [r7, #4]
|
|
static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */
|
|
return mem;
|
|
800a8a8: 4b03 ldr r3, [pc, #12] @ (800a8b8 <USBD_static_malloc+0x18>)
|
|
}
|
|
800a8aa: 4618 mov r0, r3
|
|
800a8ac: 370c adds r7, #12
|
|
800a8ae: 46bd mov sp, r7
|
|
800a8b0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a8b4: 4770 bx lr
|
|
800a8b6: bf00 nop
|
|
800a8b8: 200010e4 .word 0x200010e4
|
|
|
|
0800a8bc <USBD_static_free>:
|
|
* @brief Dummy memory free
|
|
* @param p: Pointer to allocated memory address
|
|
* @retval None
|
|
*/
|
|
void USBD_static_free(void *p)
|
|
{
|
|
800a8bc: b480 push {r7}
|
|
800a8be: b083 sub sp, #12
|
|
800a8c0: af00 add r7, sp, #0
|
|
800a8c2: 6078 str r0, [r7, #4]
|
|
|
|
}
|
|
800a8c4: bf00 nop
|
|
800a8c6: 370c adds r7, #12
|
|
800a8c8: 46bd mov sp, r7
|
|
800a8ca: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a8ce: 4770 bx lr
|
|
|
|
0800a8d0 <USBD_Get_USB_Status>:
|
|
* @brief Returns the USB status depending on the HAL status:
|
|
* @param hal_status: HAL status
|
|
* @retval USB status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
|
|
{
|
|
800a8d0: b480 push {r7}
|
|
800a8d2: b085 sub sp, #20
|
|
800a8d4: af00 add r7, sp, #0
|
|
800a8d6: 4603 mov r3, r0
|
|
800a8d8: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
800a8da: 2300 movs r3, #0
|
|
800a8dc: 73fb strb r3, [r7, #15]
|
|
|
|
switch (hal_status)
|
|
800a8de: 79fb ldrb r3, [r7, #7]
|
|
800a8e0: 2b03 cmp r3, #3
|
|
800a8e2: d817 bhi.n 800a914 <USBD_Get_USB_Status+0x44>
|
|
800a8e4: a201 add r2, pc, #4 @ (adr r2, 800a8ec <USBD_Get_USB_Status+0x1c>)
|
|
800a8e6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800a8ea: bf00 nop
|
|
800a8ec: 0800a8fd .word 0x0800a8fd
|
|
800a8f0: 0800a903 .word 0x0800a903
|
|
800a8f4: 0800a909 .word 0x0800a909
|
|
800a8f8: 0800a90f .word 0x0800a90f
|
|
{
|
|
case HAL_OK :
|
|
usb_status = USBD_OK;
|
|
800a8fc: 2300 movs r3, #0
|
|
800a8fe: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800a900: e00b b.n 800a91a <USBD_Get_USB_Status+0x4a>
|
|
case HAL_ERROR :
|
|
usb_status = USBD_FAIL;
|
|
800a902: 2303 movs r3, #3
|
|
800a904: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800a906: e008 b.n 800a91a <USBD_Get_USB_Status+0x4a>
|
|
case HAL_BUSY :
|
|
usb_status = USBD_BUSY;
|
|
800a908: 2301 movs r3, #1
|
|
800a90a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800a90c: e005 b.n 800a91a <USBD_Get_USB_Status+0x4a>
|
|
case HAL_TIMEOUT :
|
|
usb_status = USBD_FAIL;
|
|
800a90e: 2303 movs r3, #3
|
|
800a910: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800a912: e002 b.n 800a91a <USBD_Get_USB_Status+0x4a>
|
|
default :
|
|
usb_status = USBD_FAIL;
|
|
800a914: 2303 movs r3, #3
|
|
800a916: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800a918: bf00 nop
|
|
}
|
|
return usb_status;
|
|
800a91a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800a91c: 4618 mov r0, r3
|
|
800a91e: 3714 adds r7, #20
|
|
800a920: 46bd mov sp, r7
|
|
800a922: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a926: 4770 bx lr
|
|
|
|
0800a928 <memset>:
|
|
800a928: 4402 add r2, r0
|
|
800a92a: 4603 mov r3, r0
|
|
800a92c: 4293 cmp r3, r2
|
|
800a92e: d100 bne.n 800a932 <memset+0xa>
|
|
800a930: 4770 bx lr
|
|
800a932: f803 1b01 strb.w r1, [r3], #1
|
|
800a936: e7f9 b.n 800a92c <memset+0x4>
|
|
|
|
0800a938 <__libc_init_array>:
|
|
800a938: b570 push {r4, r5, r6, lr}
|
|
800a93a: 4d0d ldr r5, [pc, #52] @ (800a970 <__libc_init_array+0x38>)
|
|
800a93c: 4c0d ldr r4, [pc, #52] @ (800a974 <__libc_init_array+0x3c>)
|
|
800a93e: 1b64 subs r4, r4, r5
|
|
800a940: 10a4 asrs r4, r4, #2
|
|
800a942: 2600 movs r6, #0
|
|
800a944: 42a6 cmp r6, r4
|
|
800a946: d109 bne.n 800a95c <__libc_init_array+0x24>
|
|
800a948: 4d0b ldr r5, [pc, #44] @ (800a978 <__libc_init_array+0x40>)
|
|
800a94a: 4c0c ldr r4, [pc, #48] @ (800a97c <__libc_init_array+0x44>)
|
|
800a94c: f000 f826 bl 800a99c <_init>
|
|
800a950: 1b64 subs r4, r4, r5
|
|
800a952: 10a4 asrs r4, r4, #2
|
|
800a954: 2600 movs r6, #0
|
|
800a956: 42a6 cmp r6, r4
|
|
800a958: d105 bne.n 800a966 <__libc_init_array+0x2e>
|
|
800a95a: bd70 pop {r4, r5, r6, pc}
|
|
800a95c: f855 3b04 ldr.w r3, [r5], #4
|
|
800a960: 4798 blx r3
|
|
800a962: 3601 adds r6, #1
|
|
800a964: e7ee b.n 800a944 <__libc_init_array+0xc>
|
|
800a966: f855 3b04 ldr.w r3, [r5], #4
|
|
800a96a: 4798 blx r3
|
|
800a96c: 3601 adds r6, #1
|
|
800a96e: e7f2 b.n 800a956 <__libc_init_array+0x1e>
|
|
800a970: 0800aa18 .word 0x0800aa18
|
|
800a974: 0800aa18 .word 0x0800aa18
|
|
800a978: 0800aa18 .word 0x0800aa18
|
|
800a97c: 0800aa1c .word 0x0800aa1c
|
|
|
|
0800a980 <memcpy>:
|
|
800a980: 440a add r2, r1
|
|
800a982: 4291 cmp r1, r2
|
|
800a984: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
|
|
800a988: d100 bne.n 800a98c <memcpy+0xc>
|
|
800a98a: 4770 bx lr
|
|
800a98c: b510 push {r4, lr}
|
|
800a98e: f811 4b01 ldrb.w r4, [r1], #1
|
|
800a992: f803 4f01 strb.w r4, [r3, #1]!
|
|
800a996: 4291 cmp r1, r2
|
|
800a998: d1f9 bne.n 800a98e <memcpy+0xe>
|
|
800a99a: bd10 pop {r4, pc}
|
|
|
|
0800a99c <_init>:
|
|
800a99c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800a99e: bf00 nop
|
|
800a9a0: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800a9a2: bc08 pop {r3}
|
|
800a9a4: 469e mov lr, r3
|
|
800a9a6: 4770 bx lr
|
|
|
|
0800a9a8 <_fini>:
|
|
800a9a8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800a9aa: bf00 nop
|
|
800a9ac: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800a9ae: bc08 pop {r3}
|
|
800a9b0: 469e mov lr, r3
|
|
800a9b2: 4770 bx lr
|