modularkbd.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001c4 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000a2e0 080001c4 080001c4 000011c4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000005c 0800a4a4 0800a4a4 0000b4a4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800a500 0800a500 0000c1bc 2**0 CONTENTS, READONLY 4 .ARM 00000008 0800a500 0800a500 0000b500 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800a508 0800a508 0000c1bc 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800a508 0800a508 0000b508 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 0800a50c 0800a50c 0000b50c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 000001bc 20000000 0800a510 0000c000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000f14 200001bc 0800a6cc 0000c1bc 2**2 ALLOC 10 ._user_heap_stack 00000600 200010d0 0800a6cc 0000d0d0 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000c1bc 2**0 CONTENTS, READONLY 12 .debug_info 0001aeaf 00000000 00000000 0000c1ec 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00004050 00000000 00000000 0002709b 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001780 00000000 00000000 0002b0f0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 0000123c 00000000 00000000 0002c870 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00026060 00000000 00000000 0002daac 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001e5a9 00000000 00000000 00053b0c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000d7e93 00000000 00000000 000720b5 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 00149f48 2**0 CONTENTS, READONLY 20 .debug_frame 000062a4 00000000 00000000 00149f8c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000062 00000000 00000000 00150230 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001c4 <__do_global_dtors_aux>: 80001c4: b510 push {r4, lr} 80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>) 80001c8: 7823 ldrb r3, [r4, #0] 80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16> 80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>) 80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12> 80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>) 80001d2: f3af 8000 nop.w 80001d6: 2301 movs r3, #1 80001d8: 7023 strb r3, [r4, #0] 80001da: bd10 pop {r4, pc} 80001dc: 200001bc .word 0x200001bc 80001e0: 00000000 .word 0x00000000 80001e4: 0800a48c .word 0x0800a48c 080001e8 : 80001e8: b508 push {r3, lr} 80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 ) 80001ec: b11b cbz r3, 80001f6 80001ee: 4903 ldr r1, [pc, #12] @ (80001fc ) 80001f0: 4803 ldr r0, [pc, #12] @ (8000200 ) 80001f2: f3af 8000 nop.w 80001f6: bd08 pop {r3, pc} 80001f8: 00000000 .word 0x00000000 80001fc: 200001c0 .word 0x200001c0 8000200: 0800a48c .word 0x0800a48c 08000204 <__aeabi_uldivmod>: 8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18> 8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18> 8000208: 2900 cmp r1, #0 800020a: bf08 it eq 800020c: 2800 cmpeq r0, #0 800020e: bf1c itt ne 8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000218: f000 b988 b.w 800052c <__aeabi_idiv0> 800021c: f1ad 0c08 sub.w ip, sp, #8 8000220: e96d ce04 strd ip, lr, [sp, #-16]! 8000224: f000 f806 bl 8000234 <__udivmoddi4> 8000228: f8dd e004 ldr.w lr, [sp, #4] 800022c: e9dd 2302 ldrd r2, r3, [sp, #8] 8000230: b004 add sp, #16 8000232: 4770 bx lr 08000234 <__udivmoddi4>: 8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000238: 9d08 ldr r5, [sp, #32] 800023a: 468e mov lr, r1 800023c: 4604 mov r4, r0 800023e: 4688 mov r8, r1 8000240: 2b00 cmp r3, #0 8000242: d14a bne.n 80002da <__udivmoddi4+0xa6> 8000244: 428a cmp r2, r1 8000246: 4617 mov r7, r2 8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc> 800024a: fab2 f682 clz r6, r2 800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30> 8000250: f1c6 0320 rsb r3, r6, #32 8000254: fa01 f806 lsl.w r8, r1, r6 8000258: fa20 f303 lsr.w r3, r0, r3 800025c: 40b7 lsls r7, r6 800025e: ea43 0808 orr.w r8, r3, r8 8000262: 40b4 lsls r4, r6 8000264: ea4f 4e17 mov.w lr, r7, lsr #16 8000268: fa1f fc87 uxth.w ip, r7 800026c: fbb8 f1fe udiv r1, r8, lr 8000270: 0c23 lsrs r3, r4, #16 8000272: fb0e 8811 mls r8, lr, r1, r8 8000276: ea43 4308 orr.w r3, r3, r8, lsl #16 800027a: fb01 f20c mul.w r2, r1, ip 800027e: 429a cmp r2, r3 8000280: d909 bls.n 8000296 <__udivmoddi4+0x62> 8000282: 18fb adds r3, r7, r3 8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c> 800028c: 429a cmp r2, r3 800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c> 8000292: 3902 subs r1, #2 8000294: 443b add r3, r7 8000296: 1a9a subs r2, r3, r2 8000298: b2a3 uxth r3, r4 800029a: fbb2 f0fe udiv r0, r2, lr 800029e: fb0e 2210 mls r2, lr, r0, r2 80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16 80002a6: fb00 fc0c mul.w ip, r0, ip 80002aa: 459c cmp ip, r3 80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e> 80002ae: 18fb adds r3, r7, r3 80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230> 80002b8: 459c cmp ip, r3 80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230> 80002be: 443b add r3, r7 80002c0: 3802 subs r0, #2 80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16 80002c6: eba3 030c sub.w r3, r3, ip 80002ca: 2100 movs r1, #0 80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2> 80002ce: 40f3 lsrs r3, r6 80002d0: 2200 movs r2, #0 80002d2: e9c5 3200 strd r3, r2, [r5] 80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002da: 428b cmp r3, r1 80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6> 80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0> 80002e0: e9c5 0100 strd r0, r1, [r5] 80002e4: 2100 movs r1, #0 80002e6: 4608 mov r0, r1 80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2> 80002ea: fab3 f183 clz r1, r3 80002ee: 2900 cmp r1, #0 80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c> 80002f2: 4573 cmp r3, lr 80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8> 80002f6: 4282 cmp r2, r0 80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2> 80002fc: 1a84 subs r4, r0, r2 80002fe: eb6e 0203 sbc.w r2, lr, r3 8000302: 2001 movs r0, #1 8000304: 4690 mov r8, r2 8000306: 2d00 cmp r5, #0 8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2> 800030a: e9c5 4800 strd r4, r8, [r5] 800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2> 8000310: 2a00 cmp r2, #0 8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202> 8000316: fab2 f682 clz r6, r2 800031a: 2e00 cmp r6, #0 800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234> 8000320: 1a8a subs r2, r1, r2 8000322: 0c03 lsrs r3, r0, #16 8000324: ea4f 4e17 mov.w lr, r7, lsr #16 8000328: b280 uxth r0, r0 800032a: b2bc uxth r4, r7 800032c: 2101 movs r1, #1 800032e: fbb2 fcfe udiv ip, r2, lr 8000332: fb0e 221c mls r2, lr, ip, r2 8000336: ea43 4302 orr.w r3, r3, r2, lsl #16 800033a: fb04 f20c mul.w r2, r4, ip 800033e: 429a cmp r2, r3 8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e> 8000342: 18fb adds r3, r7, r3 8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c> 800034a: 429a cmp r2, r3 800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc> 8000350: 46c4 mov ip, r8 8000352: 1a9b subs r3, r3, r2 8000354: fbb3 f2fe udiv r2, r3, lr 8000358: fb0e 3312 mls r3, lr, r2, r3 800035c: ea40 4303 orr.w r3, r0, r3, lsl #16 8000360: fb02 f404 mul.w r4, r2, r4 8000364: 429c cmp r4, r3 8000366: d907 bls.n 8000378 <__udivmoddi4+0x144> 8000368: 18fb adds r3, r7, r3 800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142> 8000370: 429c cmp r4, r3 8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6> 8000376: 4602 mov r2, r0 8000378: 1b1b subs r3, r3, r4 800037a: ea42 400c orr.w r0, r2, ip, lsl #16 800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98> 8000380: f1c1 0620 rsb r6, r1, #32 8000384: 408b lsls r3, r1 8000386: fa22 f706 lsr.w r7, r2, r6 800038a: 431f orrs r7, r3 800038c: fa0e f401 lsl.w r4, lr, r1 8000390: fa20 f306 lsr.w r3, r0, r6 8000394: fa2e fe06 lsr.w lr, lr, r6 8000398: ea4f 4917 mov.w r9, r7, lsr #16 800039c: 4323 orrs r3, r4 800039e: fa00 f801 lsl.w r8, r0, r1 80003a2: fa1f fc87 uxth.w ip, r7 80003a6: fbbe f0f9 udiv r0, lr, r9 80003aa: 0c1c lsrs r4, r3, #16 80003ac: fb09 ee10 mls lr, r9, r0, lr 80003b0: ea44 440e orr.w r4, r4, lr, lsl #16 80003b4: fb00 fe0c mul.w lr, r0, ip 80003b8: 45a6 cmp lr, r4 80003ba: fa02 f201 lsl.w r2, r2, r1 80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0> 80003c0: 193c adds r4, r7, r4 80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce> 80003ca: 45a6 cmp lr, r4 80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce> 80003d0: 3802 subs r0, #2 80003d2: 443c add r4, r7 80003d4: eba4 040e sub.w r4, r4, lr 80003d8: fa1f fe83 uxth.w lr, r3 80003dc: fbb4 f3f9 udiv r3, r4, r9 80003e0: fb09 4413 mls r4, r9, r3, r4 80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003e8: fb03 fc0c mul.w ip, r3, ip 80003ec: 45a4 cmp ip, r4 80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce> 80003f0: 193c adds r4, r7, r4 80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca> 80003fa: 45a4 cmp ip, r4 80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca> 80003fe: 3b02 subs r3, #2 8000400: 443c add r4, r7 8000402: ea43 4000 orr.w r0, r3, r0, lsl #16 8000406: eba4 040c sub.w r4, r4, ip 800040a: fba0 ec02 umull lr, ip, r0, r2 800040e: 4564 cmp r4, ip 8000410: 4673 mov r3, lr 8000412: 46e1 mov r9, ip 8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8> 8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4> 8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe> 800041a: ebb8 0203 subs.w r2, r8, r3 800041e: eb64 0409 sbc.w r4, r4, r9 8000422: fa04 f606 lsl.w r6, r4, r6 8000426: fa22 f301 lsr.w r3, r2, r1 800042a: 431e orrs r6, r3 800042c: 40cc lsrs r4, r1 800042e: e9c5 6400 strd r6, r4, [r5] 8000432: 2100 movs r1, #0 8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2> 8000436: fbb1 fcf2 udiv ip, r1, r2 800043a: 0c01 lsrs r1, r0, #16 800043c: ea41 410e orr.w r1, r1, lr, lsl #16 8000440: b280 uxth r0, r0 8000442: ea40 4201 orr.w r2, r0, r1, lsl #16 8000446: 463b mov r3, r7 8000448: 4638 mov r0, r7 800044a: 463c mov r4, r7 800044c: 46b8 mov r8, r7 800044e: 46be mov lr, r7 8000450: 2620 movs r6, #32 8000452: fbb1 f1f7 udiv r1, r1, r7 8000456: eba2 0208 sub.w r2, r2, r8 800045a: ea41 410c orr.w r1, r1, ip, lsl #16 800045e: e766 b.n 800032e <__udivmoddi4+0xfa> 8000460: 4601 mov r1, r0 8000462: e718 b.n 8000296 <__udivmoddi4+0x62> 8000464: 4610 mov r0, r2 8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e> 8000468: f1c6 0220 rsb r2, r6, #32 800046c: fa2e f302 lsr.w r3, lr, r2 8000470: 40b7 lsls r7, r6 8000472: 40b1 lsls r1, r6 8000474: fa20 f202 lsr.w r2, r0, r2 8000478: ea4f 4e17 mov.w lr, r7, lsr #16 800047c: 430a orrs r2, r1 800047e: fbb3 f8fe udiv r8, r3, lr 8000482: b2bc uxth r4, r7 8000484: fb0e 3318 mls r3, lr, r8, r3 8000488: 0c11 lsrs r1, r2, #16 800048a: ea41 4103 orr.w r1, r1, r3, lsl #16 800048e: fb08 f904 mul.w r9, r8, r4 8000492: 40b0 lsls r0, r6 8000494: 4589 cmp r9, r1 8000496: ea4f 4310 mov.w r3, r0, lsr #16 800049a: b280 uxth r0, r0 800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8> 800049e: 1879 adds r1, r7, r1 80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276> 80004a6: 4589 cmp r9, r1 80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6> 80004aa: eba1 0109 sub.w r1, r1, r9 80004ae: fbb1 f9fe udiv r9, r1, lr 80004b2: fb09 f804 mul.w r8, r9, r4 80004b6: fb0e 1119 mls r1, lr, r9, r1 80004ba: b292 uxth r2, r2 80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16 80004c0: 4542 cmp r2, r8 80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4> 80004c4: 18ba adds r2, r7, r2 80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222> 80004cc: 4542 cmp r2, r8 80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222> 80004d0: f1a9 0102 sub.w r1, r9, #2 80004d4: 443a add r2, r7 80004d6: e7be b.n 8000456 <__udivmoddi4+0x222> 80004d8: 45f0 cmp r8, lr 80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4> 80004dc: ebbe 0302 subs.w r3, lr, r2 80004e0: eb6c 0c07 sbc.w ip, ip, r7 80004e4: 3801 subs r0, #1 80004e6: 46e1 mov r9, ip 80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4> 80004ea: eba7 0909 sub.w r9, r7, r9 80004ee: 4449 add r1, r9 80004f0: f1a8 0c02 sub.w ip, r8, #2 80004f4: fbb1 f9fe udiv r9, r1, lr 80004f8: fb09 f804 mul.w r8, r9, r4 80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282> 80004fe: 4673 mov r3, lr 8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce> 8000502: 4650 mov r0, sl 8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0> 8000506: 4608 mov r0, r1 8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2> 800050a: 443b add r3, r7 800050c: 3a02 subs r2, #2 800050e: e733 b.n 8000378 <__udivmoddi4+0x144> 8000510: f1ac 0c02 sub.w ip, ip, #2 8000514: 443b add r3, r7 8000516: e71c b.n 8000352 <__udivmoddi4+0x11e> 8000518: 4649 mov r1, r9 800051a: e79c b.n 8000456 <__udivmoddi4+0x222> 800051c: eba1 0109 sub.w r1, r1, r9 8000520: 46c4 mov ip, r8 8000522: fbb1 f9fe udiv r9, r1, lr 8000526: fb09 f804 mul.w r8, r9, r4 800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282> 0800052c <__aeabi_idiv0>: 800052c: 4770 bx lr 800052e: bf00 nop 08000530 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 8000530: b580 push {r7, lr} 8000532: b082 sub sp, #8 8000534: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8000536: 2300 movs r3, #0 8000538: 607b str r3, [r7, #4] 800053a: 4b2f ldr r3, [pc, #188] @ (80005f8 ) 800053c: 6b1b ldr r3, [r3, #48] @ 0x30 800053e: 4a2e ldr r2, [pc, #184] @ (80005f8 ) 8000540: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000544: 6313 str r3, [r2, #48] @ 0x30 8000546: 4b2c ldr r3, [pc, #176] @ (80005f8 ) 8000548: 6b1b ldr r3, [r3, #48] @ 0x30 800054a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800054e: 607b str r3, [r7, #4] 8000550: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); 8000552: 2300 movs r3, #0 8000554: 603b str r3, [r7, #0] 8000556: 4b28 ldr r3, [pc, #160] @ (80005f8 ) 8000558: 6b1b ldr r3, [r3, #48] @ 0x30 800055a: 4a27 ldr r2, [pc, #156] @ (80005f8 ) 800055c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8000560: 6313 str r3, [r2, #48] @ 0x30 8000562: 4b25 ldr r3, [pc, #148] @ (80005f8 ) 8000564: 6b1b ldr r3, [r3, #48] @ 0x30 8000566: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800056a: 603b str r3, [r7, #0] 800056c: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); 800056e: 2200 movs r2, #0 8000570: 2100 movs r1, #0 8000572: 200b movs r0, #11 8000574: f001 fa6b bl 8001a4e HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8000578: 200b movs r0, #11 800057a: f001 fa84 bl 8001a86 /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); 800057e: 2200 movs r2, #0 8000580: 2100 movs r1, #0 8000582: 200d movs r0, #13 8000584: f001 fa63 bl 8001a4e HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8000588: 200d movs r0, #13 800058a: f001 fa7c bl 8001a86 /* DMA1_Stream4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0); 800058e: 2200 movs r2, #0 8000590: 2100 movs r1, #0 8000592: 200f movs r0, #15 8000594: f001 fa5b bl 8001a4e HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); 8000598: 200f movs r0, #15 800059a: f001 fa74 bl 8001a86 /* DMA1_Stream5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); 800059e: 2200 movs r2, #0 80005a0: 2100 movs r1, #0 80005a2: 2010 movs r0, #16 80005a4: f001 fa53 bl 8001a4e HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); 80005a8: 2010 movs r0, #16 80005aa: f001 fa6c bl 8001a86 /* DMA1_Stream6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0); 80005ae: 2200 movs r2, #0 80005b0: 2100 movs r1, #0 80005b2: 2011 movs r0, #17 80005b4: f001 fa4b bl 8001a4e HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); 80005b8: 2011 movs r0, #17 80005ba: f001 fa64 bl 8001a86 /* DMA1_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0); 80005be: 2200 movs r2, #0 80005c0: 2100 movs r1, #0 80005c2: 202f movs r0, #47 @ 0x2f 80005c4: f001 fa43 bl 8001a4e HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); 80005c8: 202f movs r0, #47 @ 0x2f 80005ca: f001 fa5c bl 8001a86 /* DMA2_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); 80005ce: 2200 movs r2, #0 80005d0: 2100 movs r1, #0 80005d2: 203a movs r0, #58 @ 0x3a 80005d4: f001 fa3b bl 8001a4e HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); 80005d8: 203a movs r0, #58 @ 0x3a 80005da: f001 fa54 bl 8001a86 /* DMA2_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 80005de: 2200 movs r2, #0 80005e0: 2100 movs r1, #0 80005e2: 2046 movs r0, #70 @ 0x46 80005e4: f001 fa33 bl 8001a4e HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 80005e8: 2046 movs r0, #70 @ 0x46 80005ea: f001 fa4c bl 8001a86 } 80005ee: bf00 nop 80005f0: 3708 adds r7, #8 80005f2: 46bd mov sp, r7 80005f4: bd80 pop {r7, pc} 80005f6: bf00 nop 80005f8: 40023800 .word 0x40023800 080005fc : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 80005fc: b580 push {r7, lr} 80005fe: b08a sub sp, #40 @ 0x28 8000600: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000602: f107 0314 add.w r3, r7, #20 8000606: 2200 movs r2, #0 8000608: 601a str r2, [r3, #0] 800060a: 605a str r2, [r3, #4] 800060c: 609a str r2, [r3, #8] 800060e: 60da str r2, [r3, #12] 8000610: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8000612: 2300 movs r3, #0 8000614: 613b str r3, [r7, #16] 8000616: 4b45 ldr r3, [pc, #276] @ (800072c ) 8000618: 6b1b ldr r3, [r3, #48] @ 0x30 800061a: 4a44 ldr r2, [pc, #272] @ (800072c ) 800061c: f043 0380 orr.w r3, r3, #128 @ 0x80 8000620: 6313 str r3, [r2, #48] @ 0x30 8000622: 4b42 ldr r3, [pc, #264] @ (800072c ) 8000624: 6b1b ldr r3, [r3, #48] @ 0x30 8000626: f003 0380 and.w r3, r3, #128 @ 0x80 800062a: 613b str r3, [r7, #16] 800062c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800062e: 2300 movs r3, #0 8000630: 60fb str r3, [r7, #12] 8000632: 4b3e ldr r3, [pc, #248] @ (800072c ) 8000634: 6b1b ldr r3, [r3, #48] @ 0x30 8000636: 4a3d ldr r2, [pc, #244] @ (800072c ) 8000638: f043 0301 orr.w r3, r3, #1 800063c: 6313 str r3, [r2, #48] @ 0x30 800063e: 4b3b ldr r3, [pc, #236] @ (800072c ) 8000640: 6b1b ldr r3, [r3, #48] @ 0x30 8000642: f003 0301 and.w r3, r3, #1 8000646: 60fb str r3, [r7, #12] 8000648: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); 800064a: 2300 movs r3, #0 800064c: 60bb str r3, [r7, #8] 800064e: 4b37 ldr r3, [pc, #220] @ (800072c ) 8000650: 6b1b ldr r3, [r3, #48] @ 0x30 8000652: 4a36 ldr r2, [pc, #216] @ (800072c ) 8000654: f043 0304 orr.w r3, r3, #4 8000658: 6313 str r3, [r2, #48] @ 0x30 800065a: 4b34 ldr r3, [pc, #208] @ (800072c ) 800065c: 6b1b ldr r3, [r3, #48] @ 0x30 800065e: f003 0304 and.w r3, r3, #4 8000662: 60bb str r3, [r7, #8] 8000664: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000666: 2300 movs r3, #0 8000668: 607b str r3, [r7, #4] 800066a: 4b30 ldr r3, [pc, #192] @ (800072c ) 800066c: 6b1b ldr r3, [r3, #48] @ 0x30 800066e: 4a2f ldr r2, [pc, #188] @ (800072c ) 8000670: f043 0302 orr.w r3, r3, #2 8000674: 6313 str r3, [r2, #48] @ 0x30 8000676: 4b2d ldr r3, [pc, #180] @ (800072c ) 8000678: 6b1b ldr r3, [r3, #48] @ 0x30 800067a: f003 0302 and.w r3, r3, #2 800067e: 607b str r3, [r7, #4] 8000680: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000682: 2300 movs r3, #0 8000684: 603b str r3, [r7, #0] 8000686: 4b29 ldr r3, [pc, #164] @ (800072c ) 8000688: 6b1b ldr r3, [r3, #48] @ 0x30 800068a: 4a28 ldr r2, [pc, #160] @ (800072c ) 800068c: f043 0308 orr.w r3, r3, #8 8000690: 6313 str r3, [r2, #48] @ 0x30 8000692: 4b26 ldr r3, [pc, #152] @ (800072c ) 8000694: 6b1b ldr r3, [r3, #48] @ 0x30 8000696: f003 0308 and.w r3, r3, #8 800069a: 603b str r3, [r7, #0] 800069c: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET); 800069e: 2200 movs r2, #0 80006a0: f44f 7170 mov.w r1, #960 @ 0x3c0 80006a4: 4822 ldr r0, [pc, #136] @ (8000730 ) 80006a6: f001 ffb7 bl 8002618 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); 80006aa: 2200 movs r2, #0 80006ac: f44f 7180 mov.w r1, #256 @ 0x100 80006b0: 4820 ldr r0, [pc, #128] @ (8000734 ) 80006b2: f001 ffb1 bl 8002618 /*Configure GPIO pins : PC4 PC5 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80006b6: 2330 movs r3, #48 @ 0x30 80006b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006ba: 2300 movs r3, #0 80006bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006be: 2302 movs r3, #2 80006c0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006c2: f107 0314 add.w r3, r7, #20 80006c6: 4619 mov r1, r3 80006c8: 4819 ldr r0, [pc, #100] @ (8000730 ) 80006ca: f001 fdf9 bl 80022c0 /*Configure GPIO pins : PB0 PB1 PB2 PB10 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10; 80006ce: f240 4307 movw r3, #1031 @ 0x407 80006d2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006d4: 2300 movs r3, #0 80006d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006d8: 2302 movs r3, #2 80006da: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80006dc: f107 0314 add.w r3, r7, #20 80006e0: 4619 mov r1, r3 80006e2: 4815 ldr r0, [pc, #84] @ (8000738 ) 80006e4: f001 fdec bl 80022c0 /*Configure GPIO pins : PC6 PC7 PC8 PC9 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 80006e8: f44f 7370 mov.w r3, #960 @ 0x3c0 80006ec: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006ee: 2301 movs r3, #1 80006f0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80006f2: 2300 movs r3, #0 80006f4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80006f6: 2300 movs r3, #0 80006f8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006fa: f107 0314 add.w r3, r7, #20 80006fe: 4619 mov r1, r3 8000700: 480b ldr r0, [pc, #44] @ (8000730 ) 8000702: f001 fddd bl 80022c0 /*Configure GPIO pin : PA8 */ GPIO_InitStruct.Pin = GPIO_PIN_8; 8000706: f44f 7380 mov.w r3, #256 @ 0x100 800070a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800070c: 2301 movs r3, #1 800070e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000710: 2300 movs r3, #0 8000712: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000714: 2300 movs r3, #0 8000716: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000718: f107 0314 add.w r3, r7, #20 800071c: 4619 mov r1, r3 800071e: 4805 ldr r0, [pc, #20] @ (8000734 ) 8000720: f001 fdce bl 80022c0 } 8000724: bf00 nop 8000726: 3728 adds r7, #40 @ 0x28 8000728: 46bd mov sp, r7 800072a: bd80 pop {r7, pc} 800072c: 40023800 .word 0x40023800 8000730: 40020800 .word 0x40020800 8000734: 40020000 .word 0x40020000 8000738: 40020400 .word 0x40020400 0800073c : I2C_HandleTypeDef hi2c1; /* I2C1 init function */ void MX_I2C1_Init(void) { 800073c: b580 push {r7, lr} 800073e: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8000740: 4b12 ldr r3, [pc, #72] @ (800078c ) 8000742: 4a13 ldr r2, [pc, #76] @ (8000790 ) 8000744: 601a str r2, [r3, #0] hi2c1.Init.ClockSpeed = 100000; 8000746: 4b11 ldr r3, [pc, #68] @ (800078c ) 8000748: 4a12 ldr r2, [pc, #72] @ (8000794 ) 800074a: 605a str r2, [r3, #4] hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; 800074c: 4b0f ldr r3, [pc, #60] @ (800078c ) 800074e: 2200 movs r2, #0 8000750: 609a str r2, [r3, #8] hi2c1.Init.OwnAddress1 = 0; 8000752: 4b0e ldr r3, [pc, #56] @ (800078c ) 8000754: 2200 movs r2, #0 8000756: 60da str r2, [r3, #12] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8000758: 4b0c ldr r3, [pc, #48] @ (800078c ) 800075a: f44f 4280 mov.w r2, #16384 @ 0x4000 800075e: 611a str r2, [r3, #16] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000760: 4b0a ldr r3, [pc, #40] @ (800078c ) 8000762: 2200 movs r2, #0 8000764: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2 = 0; 8000766: 4b09 ldr r3, [pc, #36] @ (800078c ) 8000768: 2200 movs r2, #0 800076a: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 800076c: 4b07 ldr r3, [pc, #28] @ (800078c ) 800076e: 2200 movs r2, #0 8000770: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8000772: 4b06 ldr r3, [pc, #24] @ (800078c ) 8000774: 2200 movs r2, #0 8000776: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8000778: 4804 ldr r0, [pc, #16] @ (800078c ) 800077a: f001 ff67 bl 800264c 800077e: 4603 mov r3, r0 8000780: 2b00 cmp r3, #0 8000782: d001 beq.n 8000788 { Error_Handler(); 8000784: f000 fa20 bl 8000bc8 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8000788: bf00 nop 800078a: bd80 pop {r7, pc} 800078c: 200001d8 .word 0x200001d8 8000790: 40005400 .word 0x40005400 8000794: 000186a0 .word 0x000186a0 08000798 : void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) { 8000798: b580 push {r7, lr} 800079a: b08a sub sp, #40 @ 0x28 800079c: af00 add r7, sp, #0 800079e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007a0: f107 0314 add.w r3, r7, #20 80007a4: 2200 movs r2, #0 80007a6: 601a str r2, [r3, #0] 80007a8: 605a str r2, [r3, #4] 80007aa: 609a str r2, [r3, #8] 80007ac: 60da str r2, [r3, #12] 80007ae: 611a str r2, [r3, #16] if(i2cHandle->Instance==I2C1) 80007b0: 687b ldr r3, [r7, #4] 80007b2: 681b ldr r3, [r3, #0] 80007b4: 4a19 ldr r2, [pc, #100] @ (800081c ) 80007b6: 4293 cmp r3, r2 80007b8: d12b bne.n 8000812 { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80007ba: 2300 movs r3, #0 80007bc: 613b str r3, [r7, #16] 80007be: 4b18 ldr r3, [pc, #96] @ (8000820 ) 80007c0: 6b1b ldr r3, [r3, #48] @ 0x30 80007c2: 4a17 ldr r2, [pc, #92] @ (8000820 ) 80007c4: f043 0302 orr.w r3, r3, #2 80007c8: 6313 str r3, [r2, #48] @ 0x30 80007ca: 4b15 ldr r3, [pc, #84] @ (8000820 ) 80007cc: 6b1b ldr r3, [r3, #48] @ 0x30 80007ce: f003 0302 and.w r3, r3, #2 80007d2: 613b str r3, [r7, #16] 80007d4: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80007d6: 23c0 movs r3, #192 @ 0xc0 80007d8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80007da: 2312 movs r3, #18 80007dc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80007de: 2300 movs r3, #0 80007e0: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80007e2: 2303 movs r3, #3 80007e4: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 80007e6: 2304 movs r3, #4 80007e8: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80007ea: f107 0314 add.w r3, r7, #20 80007ee: 4619 mov r1, r3 80007f0: 480c ldr r0, [pc, #48] @ (8000824 ) 80007f2: f001 fd65 bl 80022c0 /* I2C1 clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 80007f6: 2300 movs r3, #0 80007f8: 60fb str r3, [r7, #12] 80007fa: 4b09 ldr r3, [pc, #36] @ (8000820 ) 80007fc: 6c1b ldr r3, [r3, #64] @ 0x40 80007fe: 4a08 ldr r2, [pc, #32] @ (8000820 ) 8000800: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000804: 6413 str r3, [r2, #64] @ 0x40 8000806: 4b06 ldr r3, [pc, #24] @ (8000820 ) 8000808: 6c1b ldr r3, [r3, #64] @ 0x40 800080a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800080e: 60fb str r3, [r7, #12] 8000810: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8000812: bf00 nop 8000814: 3728 adds r7, #40 @ 0x28 8000816: 46bd mov sp, r7 8000818: bd80 pop {r7, pc} 800081a: bf00 nop 800081c: 40005400 .word 0x40005400 8000820: 40023800 .word 0x40023800 8000824: 40020400 .word 0x40020400 08000828
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000828: b580 push {r7, lr} 800082a: b084 sub sp, #16 800082c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800082e: f000 ff9d bl 800176c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000832: f000 f87b bl 800092c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000836: f7ff fee1 bl 80005fc MX_DMA_Init(); 800083a: f7ff fe79 bl 8000530 MX_TIM2_Init(); 800083e: f000 fab5 bl 8000dac MX_TIM3_Init(); 8000842: f000 fb0b bl 8000e5c MX_UART4_Init(); 8000846: f000 fbfd bl 8001044 MX_UART5_Init(); 800084a: f000 fc25 bl 8001098 MX_USART1_UART_Init(); 800084e: f000 fc4d bl 80010ec MX_USART2_UART_Init(); 8000852: f000 fc75 bl 8001140 MX_I2C1_Init(); 8000856: f7ff ff71 bl 800073c MX_USB_DEVICE_Init(); 800085a: f009 f93d bl 8009ad8 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { switch (MODE){ 800085e: 4b2b ldr r3, [pc, #172] @ (800090c ) 8000860: 781b ldrb r3, [r3, #0] 8000862: b2db uxtb r3, r3 8000864: 2b02 cmp r3, #2 8000866: d006 beq.n 8000876 8000868: 2b02 cmp r3, #2 800086a: dc4a bgt.n 8000902 800086c: 2b00 cmp r3, #0 800086e: d007 beq.n 8000880 8000870: 2b01 cmp r3, #1 8000872: d03c beq.n 80008ee 8000874: e045 b.n 8000902 case MODE_ACTIVE: resetReport(); 8000876: f000 f997 bl 8000ba8 matrixScan(); 800087a: f000 f93b bl 8000af4 break; 800087e: e040 b.n 8000902 case MODE_INACTIVE: //If the module is connected through the USB then mode is mainboard if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){ 8000880: 4b23 ldr r3, [pc, #140] @ (8000910 ) 8000882: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8000886: b2db uxtb r3, r3 8000888: 2b03 cmp r3, #3 800088a: d106 bne.n 800089a MODE = MODE_MAINBOARD; 800088c: 4b1f ldr r3, [pc, #124] @ (800090c ) 800088e: 2201 movs r2, #1 8000890: 701a strb r2, [r3, #0] DEPTH = 0; 8000892: 4b20 ldr r3, [pc, #128] @ (8000914 ) 8000894: 2200 movs r2, #0 8000896: 801a strh r2, [r3, #0] HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); HAL_Delay(500); findBestParent(); //So true... } break; 8000898: e033 b.n 8000902 REQ.DEPTH = 0; 800089a: 2300 movs r3, #0 800089c: 803b strh r3, [r7, #0] REQ.TYPE = 0xFF; //Message code for request is 0xFF 800089e: 23ff movs r3, #255 @ 0xff 80008a0: 807b strh r3, [r7, #2] memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS)); 80008a2: 463b mov r3, r7 80008a4: 3304 adds r3, #4 80008a6: 220c movs r2, #12 80008a8: 2100 movs r1, #0 80008aa: 4618 mov r0, r3 80008ac: f009 fdc2 bl 800a434 HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ)); 80008b0: 463b mov r3, r7 80008b2: 2210 movs r2, #16 80008b4: 4619 mov r1, r3 80008b6: 4818 ldr r0, [pc, #96] @ (8000918 ) 80008b8: f005 f818 bl 80058ec HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ)); 80008bc: 463b mov r3, r7 80008be: 2210 movs r2, #16 80008c0: 4619 mov r1, r3 80008c2: 4816 ldr r0, [pc, #88] @ (800091c ) 80008c4: f005 f812 bl 80058ec HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); 80008c8: 463b mov r3, r7 80008ca: 2210 movs r2, #16 80008cc: 4619 mov r1, r3 80008ce: 4814 ldr r0, [pc, #80] @ (8000920 ) 80008d0: f005 f80c bl 80058ec HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); 80008d4: 463b mov r3, r7 80008d6: 2210 movs r2, #16 80008d8: 4619 mov r1, r3 80008da: 4812 ldr r0, [pc, #72] @ (8000924 ) 80008dc: f005 f806 bl 80058ec HAL_Delay(500); 80008e0: f44f 70fa mov.w r0, #500 @ 0x1f4 80008e4: f000 ffb4 bl 8001850 findBestParent(); //So true... 80008e8: f000 f896 bl 8000a18 break; 80008ec: e009 b.n 8000902 case MODE_MAINBOARD: resetReport(); 80008ee: f000 f95b bl 8000ba8 matrixScan(); 80008f2: f000 f8ff bl 8000af4 USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); 80008f6: 220e movs r2, #14 80008f8: 490b ldr r1, [pc, #44] @ (8000928 ) 80008fa: 4805 ldr r0, [pc, #20] @ (8000910 ) 80008fc: f007 fd20 bl 8008340 break; 8000900: bf00 nop } HAL_Delay(50); 8000902: 2032 movs r0, #50 @ 0x32 8000904: f000 ffa4 bl 8001850 switch (MODE){ 8000908: e7a9 b.n 800085e 800090a: bf00 nop 800090c: 20000240 .word 0x20000240 8000910: 200006fc .word 0x200006fc 8000914: 2000023a .word 0x2000023a 8000918: 20000364 .word 0x20000364 800091c: 200003ac .word 0x200003ac 8000920: 200002d4 .word 0x200002d4 8000924: 2000031c .word 0x2000031c 8000928: 2000022c .word 0x2000022c 0800092c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800092c: b580 push {r7, lr} 800092e: b094 sub sp, #80 @ 0x50 8000930: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000932: f107 031c add.w r3, r7, #28 8000936: 2234 movs r2, #52 @ 0x34 8000938: 2100 movs r1, #0 800093a: 4618 mov r0, r3 800093c: f009 fd7a bl 800a434 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000940: f107 0308 add.w r3, r7, #8 8000944: 2200 movs r2, #0 8000946: 601a str r2, [r3, #0] 8000948: 605a str r2, [r3, #4] 800094a: 609a str r2, [r3, #8] 800094c: 60da str r2, [r3, #12] 800094e: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 8000950: 2300 movs r3, #0 8000952: 607b str r3, [r7, #4] 8000954: 4b29 ldr r3, [pc, #164] @ (80009fc ) 8000956: 6c1b ldr r3, [r3, #64] @ 0x40 8000958: 4a28 ldr r2, [pc, #160] @ (80009fc ) 800095a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800095e: 6413 str r3, [r2, #64] @ 0x40 8000960: 4b26 ldr r3, [pc, #152] @ (80009fc ) 8000962: 6c1b ldr r3, [r3, #64] @ 0x40 8000964: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000968: 607b str r3, [r7, #4] 800096a: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 800096c: 2300 movs r3, #0 800096e: 603b str r3, [r7, #0] 8000970: 4b23 ldr r3, [pc, #140] @ (8000a00 ) 8000972: 681b ldr r3, [r3, #0] 8000974: f423 4340 bic.w r3, r3, #49152 @ 0xc000 8000978: 4a21 ldr r2, [pc, #132] @ (8000a00 ) 800097a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800097e: 6013 str r3, [r2, #0] 8000980: 4b1f ldr r3, [pc, #124] @ (8000a00 ) 8000982: 681b ldr r3, [r3, #0] 8000984: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000988: 603b str r3, [r7, #0] 800098a: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 800098c: 2301 movs r3, #1 800098e: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000990: f44f 3380 mov.w r3, #65536 @ 0x10000 8000994: 623b str r3, [r7, #32] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000996: 2302 movs r3, #2 8000998: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800099a: f44f 0380 mov.w r3, #4194304 @ 0x400000 800099e: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLM = 4; 80009a0: 2304 movs r3, #4 80009a2: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLN = 96; 80009a4: 2360 movs r3, #96 @ 0x60 80009a6: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 80009a8: 2302 movs r3, #2 80009aa: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLQ = 4; 80009ac: 2304 movs r3, #4 80009ae: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLR = 2; 80009b0: 2302 movs r3, #2 80009b2: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80009b4: f107 031c add.w r3, r7, #28 80009b8: 4618 mov r0, r3 80009ba: f004 f885 bl 8004ac8 80009be: 4603 mov r3, r0 80009c0: 2b00 cmp r3, #0 80009c2: d001 beq.n 80009c8 { Error_Handler(); 80009c4: f000 f900 bl 8000bc8 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80009c8: 230f movs r3, #15 80009ca: 60bb str r3, [r7, #8] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80009cc: 2302 movs r3, #2 80009ce: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; 80009d0: 2380 movs r3, #128 @ 0x80 80009d2: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 80009d4: f44f 5380 mov.w r3, #4096 @ 0x1000 80009d8: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80009da: 2300 movs r3, #0 80009dc: 61bb str r3, [r7, #24] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 80009de: f107 0308 add.w r3, r7, #8 80009e2: 2101 movs r1, #1 80009e4: 4618 mov r0, r3 80009e6: f003 f9fb bl 8003de0 80009ea: 4603 mov r3, r0 80009ec: 2b00 cmp r3, #0 80009ee: d001 beq.n 80009f4 { Error_Handler(); 80009f0: f000 f8ea bl 8000bc8 } } 80009f4: bf00 nop 80009f6: 3750 adds r7, #80 @ 0x50 80009f8: 46bd mov sp, r7 80009fa: bd80 pop {r7, pc} 80009fc: 40023800 .word 0x40023800 8000a00: 40007000 .word 0x40007000 08000a04 : /* USER CODE BEGIN 4 */ //UART Message Requests Goes Here void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart){ 8000a04: b480 push {r7} 8000a06: b083 sub sp, #12 8000a08: af00 add r7, sp, #0 8000a0a: 6078 str r0, [r7, #4] } 8000a0c: bf00 nop 8000a0e: 370c adds r7, #12 8000a10: 46bd mov sp, r7 8000a12: f85d 7b04 ldr.w r7, [sp], #4 8000a16: 4770 bx lr 08000a18 : void findBestParent(){ 8000a18: b480 push {r7} 8000a1a: b085 sub sp, #20 8000a1c: af00 add r7, sp, #0 //Find least depth parent uint16_t least_val = 0xFF; 8000a1e: 23ff movs r3, #255 @ 0xff 8000a20: 81fb strh r3, [r7, #14] UART_HandleTypeDef* least_port = NULL; 8000a22: 2300 movs r3, #0 8000a24: 60bb str r3, [r7, #8] for(uint8_t i = 0; i < 4; i++){ 8000a26: 2300 movs r3, #0 8000a28: 71fb strb r3, [r7, #7] 8000a2a: e013 b.n 8000a54 if(PORT_DEPTH[i]) 8000a30: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000a34: 89fa ldrh r2, [r7, #14] 8000a36: 429a cmp r2, r3 8000a38: d909 bls.n 8000a4e least_port = PORTS[i]; 8000a3a: 79fb ldrb r3, [r7, #7] 8000a3c: 4a10 ldr r2, [pc, #64] @ (8000a80 ) 8000a3e: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000a42: 60bb str r3, [r7, #8] least_val = PORT_DEPTH[i]; 8000a44: 79fb ldrb r3, [r7, #7] 8000a46: 4a0d ldr r2, [pc, #52] @ (8000a7c ) 8000a48: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000a4c: 81fb strh r3, [r7, #14] for(uint8_t i = 0; i < 4; i++){ 8000a4e: 79fb ldrb r3, [r7, #7] 8000a50: 3301 adds r3, #1 8000a52: 71fb strb r3, [r7, #7] 8000a54: 79fb ldrb r3, [r7, #7] 8000a56: 2b03 cmp r3, #3 8000a58: d9e8 bls.n 8000a2c } } //Assign if valid if(least_val < 0xFF){ 8000a5a: 89fb ldrh r3, [r7, #14] 8000a5c: 2bfe cmp r3, #254 @ 0xfe 8000a5e: d807 bhi.n 8000a70 PARENT = least_port; 8000a60: 4a08 ldr r2, [pc, #32] @ (8000a84 ) 8000a62: 68bb ldr r3, [r7, #8] 8000a64: 6013 str r3, [r2, #0] DEPTH = least_val + 1; 8000a66: 89fb ldrh r3, [r7, #14] 8000a68: 3301 adds r3, #1 8000a6a: b29a uxth r2, r3 8000a6c: 4b06 ldr r3, [pc, #24] @ (8000a88 ) 8000a6e: 801a strh r2, [r3, #0] } } 8000a70: bf00 nop 8000a72: 3714 adds r7, #20 8000a74: 46bd mov sp, r7 8000a76: f85d 7b04 ldr.w r7, [sp], #4 8000a7a: 4770 bx lr 8000a7c: 20000078 .word 0x20000078 8000a80: 20000080 .word 0x20000080 8000a84: 2000023c .word 0x2000023c 8000a88: 2000023a .word 0x2000023a 08000a8c : //TODO: A function that gets called by RX Interrupt to handle messages that get sent void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender){ //TODO: Handle messages coming from devices based on the message type... } void addUSBReport(uint8_t usageID){ 8000a8c: b480 push {r7} 8000a8e: b085 sub sp, #20 8000a90: af00 add r7, sp, #0 8000a92: 4603 mov r3, r0 8000a94: 71fb strb r3, [r7, #7] if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8000a96: 79fb ldrb r3, [r7, #7] 8000a98: 2b03 cmp r3, #3 8000a9a: d922 bls.n 8000ae2 8000a9c: 79fb ldrb r3, [r7, #7] 8000a9e: 2b73 cmp r3, #115 @ 0x73 8000aa0: d81f bhi.n 8000ae2 uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit 8000aa2: 79fb ldrb r3, [r7, #7] 8000aa4: b29b uxth r3, r3 8000aa6: 3b04 subs r3, #4 8000aa8: 81fb strh r3, [r7, #14] uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array 8000aaa: 89fb ldrh r3, [r7, #14] 8000aac: 08db lsrs r3, r3, #3 8000aae: b29b uxth r3, r3 8000ab0: 737b strb r3, [r7, #13] uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset 8000ab2: 89fb ldrh r3, [r7, #14] 8000ab4: b2db uxtb r3, r3 8000ab6: f003 0307 and.w r3, r3, #7 8000aba: 733b strb r3, [r7, #12] REPORT.KEYPRESS[byte_index] |= (1 << bit_offset); 8000abc: 7b7b ldrb r3, [r7, #13] 8000abe: 4a0c ldr r2, [pc, #48] @ (8000af0 ) 8000ac0: 4413 add r3, r2 8000ac2: 789b ldrb r3, [r3, #2] 8000ac4: b25a sxtb r2, r3 8000ac6: 7b3b ldrb r3, [r7, #12] 8000ac8: 2101 movs r1, #1 8000aca: fa01 f303 lsl.w r3, r1, r3 8000ace: b25b sxtb r3, r3 8000ad0: 4313 orrs r3, r2 8000ad2: b25a sxtb r2, r3 8000ad4: 7b7b ldrb r3, [r7, #13] 8000ad6: b2d1 uxtb r1, r2 8000ad8: 4a05 ldr r2, [pc, #20] @ (8000af0 ) 8000ada: 4413 add r3, r2 8000adc: 460a mov r2, r1 8000ade: 709a strb r2, [r3, #2] 8000ae0: e000 b.n 8000ae4 if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8000ae2: bf00 nop } 8000ae4: 3714 adds r7, #20 8000ae6: 46bd mov sp, r7 8000ae8: f85d 7b04 ldr.w r7, [sp], #4 8000aec: 4770 bx lr 8000aee: bf00 nop 8000af0: 2000022c .word 0x2000022c 08000af4 : void matrixScan(void){ 8000af4: b580 push {r7, lr} 8000af6: b082 sub sp, #8 8000af8: af00 add r7, sp, #0 for (uint8_t col = 0; col < COL; col++){ 8000afa: 2300 movs r3, #0 8000afc: 71fb strb r3, [r7, #7] 8000afe: e044 b.n 8000b8a HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET); 8000b00: 79fb ldrb r3, [r7, #7] 8000b02: 4a26 ldr r2, [pc, #152] @ (8000b9c ) 8000b04: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000b08: 79fb ldrb r3, [r7, #7] 8000b0a: 4a24 ldr r2, [pc, #144] @ (8000b9c ) 8000b0c: 00db lsls r3, r3, #3 8000b0e: 4413 add r3, r2 8000b10: 889b ldrh r3, [r3, #4] 8000b12: 2201 movs r2, #1 8000b14: 4619 mov r1, r3 8000b16: f001 fd7f bl 8002618 HAL_Delay(1); 8000b1a: 2001 movs r0, #1 8000b1c: f000 fe98 bl 8001850 for(uint8_t row = 0; row < ROW; row++){ 8000b20: 2300 movs r3, #0 8000b22: 71bb strb r3, [r7, #6] 8000b24: e01e b.n 8000b64 if(HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN)){ 8000b26: 79bb ldrb r3, [r7, #6] 8000b28: 4a1d ldr r2, [pc, #116] @ (8000ba0 ) 8000b2a: f852 2033 ldr.w r2, [r2, r3, lsl #3] 8000b2e: 79bb ldrb r3, [r7, #6] 8000b30: 491b ldr r1, [pc, #108] @ (8000ba0 ) 8000b32: 00db lsls r3, r3, #3 8000b34: 440b add r3, r1 8000b36: 889b ldrh r3, [r3, #4] 8000b38: 4619 mov r1, r3 8000b3a: 4610 mov r0, r2 8000b3c: f001 fd54 bl 80025e8 8000b40: 4603 mov r3, r0 8000b42: 2b00 cmp r3, #0 8000b44: d00b beq.n 8000b5e addUSBReport(KEYCODES[row][col]); 8000b46: 79ba ldrb r2, [r7, #6] 8000b48: 79f9 ldrb r1, [r7, #7] 8000b4a: 4816 ldr r0, [pc, #88] @ (8000ba4 ) 8000b4c: 4613 mov r3, r2 8000b4e: 009b lsls r3, r3, #2 8000b50: 4413 add r3, r2 8000b52: 4403 add r3, r0 8000b54: 440b add r3, r1 8000b56: 781b ldrb r3, [r3, #0] 8000b58: 4618 mov r0, r3 8000b5a: f7ff ff97 bl 8000a8c for(uint8_t row = 0; row < ROW; row++){ 8000b5e: 79bb ldrb r3, [r7, #6] 8000b60: 3301 adds r3, #1 8000b62: 71bb strb r3, [r7, #6] 8000b64: 79bb ldrb r3, [r7, #6] 8000b66: 2b05 cmp r3, #5 8000b68: d9dd bls.n 8000b26 } } HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET); 8000b6a: 79fb ldrb r3, [r7, #7] 8000b6c: 4a0b ldr r2, [pc, #44] @ (8000b9c ) 8000b6e: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000b72: 79fb ldrb r3, [r7, #7] 8000b74: 4a09 ldr r2, [pc, #36] @ (8000b9c ) 8000b76: 00db lsls r3, r3, #3 8000b78: 4413 add r3, r2 8000b7a: 889b ldrh r3, [r3, #4] 8000b7c: 2200 movs r2, #0 8000b7e: 4619 mov r1, r3 8000b80: f001 fd4a bl 8002618 for (uint8_t col = 0; col < COL; col++){ 8000b84: 79fb ldrb r3, [r7, #7] 8000b86: 3301 adds r3, #1 8000b88: 71fb strb r3, [r7, #7] 8000b8a: 79fb ldrb r3, [r7, #7] 8000b8c: 2b04 cmp r3, #4 8000b8e: d9b7 bls.n 8000b00 } } 8000b90: bf00 nop 8000b92: bf00 nop 8000b94: 3708 adds r7, #8 8000b96: 46bd mov sp, r7 8000b98: bd80 pop {r7, pc} 8000b9a: bf00 nop 8000b9c: 20000030 .word 0x20000030 8000ba0: 20000000 .word 0x20000000 8000ba4: 20000058 .word 0x20000058 08000ba8 : void resetReport(void){ 8000ba8: b580 push {r7, lr} 8000baa: af00 add r7, sp, #0 REPORT.MODIFIER = 0; 8000bac: 4b04 ldr r3, [pc, #16] @ (8000bc0 ) 8000bae: 2200 movs r2, #0 8000bb0: 701a strb r2, [r3, #0] memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS)); 8000bb2: 220c movs r2, #12 8000bb4: 2100 movs r1, #0 8000bb6: 4803 ldr r0, [pc, #12] @ (8000bc4 ) 8000bb8: f009 fc3c bl 800a434 } 8000bbc: bf00 nop 8000bbe: bd80 pop {r7, pc} 8000bc0: 2000022c .word 0x2000022c 8000bc4: 2000022e .word 0x2000022e 08000bc8 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000bc8: b480 push {r7} 8000bca: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000bcc: b672 cpsid i } 8000bce: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000bd0: bf00 nop 8000bd2: e7fd b.n 8000bd0 08000bd4 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000bd4: b480 push {r7} 8000bd6: b083 sub sp, #12 8000bd8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000bda: 2300 movs r3, #0 8000bdc: 607b str r3, [r7, #4] 8000bde: 4b10 ldr r3, [pc, #64] @ (8000c20 ) 8000be0: 6c5b ldr r3, [r3, #68] @ 0x44 8000be2: 4a0f ldr r2, [pc, #60] @ (8000c20 ) 8000be4: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000be8: 6453 str r3, [r2, #68] @ 0x44 8000bea: 4b0d ldr r3, [pc, #52] @ (8000c20 ) 8000bec: 6c5b ldr r3, [r3, #68] @ 0x44 8000bee: f403 4380 and.w r3, r3, #16384 @ 0x4000 8000bf2: 607b str r3, [r7, #4] 8000bf4: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000bf6: 2300 movs r3, #0 8000bf8: 603b str r3, [r7, #0] 8000bfa: 4b09 ldr r3, [pc, #36] @ (8000c20 ) 8000bfc: 6c1b ldr r3, [r3, #64] @ 0x40 8000bfe: 4a08 ldr r2, [pc, #32] @ (8000c20 ) 8000c00: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000c04: 6413 str r3, [r2, #64] @ 0x40 8000c06: 4b06 ldr r3, [pc, #24] @ (8000c20 ) 8000c08: 6c1b ldr r3, [r3, #64] @ 0x40 8000c0a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000c0e: 603b str r3, [r7, #0] 8000c10: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000c12: bf00 nop 8000c14: 370c adds r7, #12 8000c16: 46bd mov sp, r7 8000c18: f85d 7b04 ldr.w r7, [sp], #4 8000c1c: 4770 bx lr 8000c1e: bf00 nop 8000c20: 40023800 .word 0x40023800 08000c24 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000c24: b480 push {r7} 8000c26: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000c28: bf00 nop 8000c2a: e7fd b.n 8000c28 08000c2c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000c2c: b480 push {r7} 8000c2e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000c30: bf00 nop 8000c32: e7fd b.n 8000c30 08000c34 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000c34: b480 push {r7} 8000c36: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000c38: bf00 nop 8000c3a: e7fd b.n 8000c38 08000c3c : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000c3c: b480 push {r7} 8000c3e: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000c40: bf00 nop 8000c42: e7fd b.n 8000c40 08000c44 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000c44: b480 push {r7} 8000c46: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000c48: bf00 nop 8000c4a: e7fd b.n 8000c48 08000c4c : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000c4c: b480 push {r7} 8000c4e: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000c50: bf00 nop 8000c52: 46bd mov sp, r7 8000c54: f85d 7b04 ldr.w r7, [sp], #4 8000c58: 4770 bx lr 08000c5a : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000c5a: b480 push {r7} 8000c5c: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000c5e: bf00 nop 8000c60: 46bd mov sp, r7 8000c62: f85d 7b04 ldr.w r7, [sp], #4 8000c66: 4770 bx lr 08000c68 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000c68: b480 push {r7} 8000c6a: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000c6c: bf00 nop 8000c6e: 46bd mov sp, r7 8000c70: f85d 7b04 ldr.w r7, [sp], #4 8000c74: 4770 bx lr 08000c76 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000c76: b580 push {r7, lr} 8000c78: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000c7a: f000 fdc9 bl 8001810 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000c7e: bf00 nop 8000c80: bd80 pop {r7, pc} ... 08000c84 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8000c84: b580 push {r7, lr} 8000c86: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_rx); 8000c88: 4802 ldr r0, [pc, #8] @ (8000c94 ) 8000c8a: f001 f8af bl 8001dec /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 8000c8e: bf00 nop 8000c90: bd80 pop {r7, pc} 8000c92: bf00 nop 8000c94: 200004b4 .word 0x200004b4 08000c98 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 8000c98: b580 push {r7, lr} 8000c9a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_rx); 8000c9c: 4802 ldr r0, [pc, #8] @ (8000ca8 ) 8000c9e: f001 f8a5 bl 8001dec /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 8000ca2: bf00 nop 8000ca4: bd80 pop {r7, pc} 8000ca6: bf00 nop 8000ca8: 200003f4 .word 0x200003f4 08000cac : /** * @brief This function handles DMA1 stream4 global interrupt. */ void DMA1_Stream4_IRQHandler(void) { 8000cac: b580 push {r7, lr} 8000cae: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ /* USER CODE END DMA1_Stream4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_tx); 8000cb0: 4802 ldr r0, [pc, #8] @ (8000cbc ) 8000cb2: f001 f89b bl 8001dec /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ /* USER CODE END DMA1_Stream4_IRQn 1 */ } 8000cb6: bf00 nop 8000cb8: bd80 pop {r7, pc} 8000cba: bf00 nop 8000cbc: 20000454 .word 0x20000454 08000cc0 : /** * @brief This function handles DMA1 stream5 global interrupt. */ void DMA1_Stream5_IRQHandler(void) { 8000cc0: b580 push {r7, lr} 8000cc2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ /* USER CODE END DMA1_Stream5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 8000cc4: 4802 ldr r0, [pc, #8] @ (8000cd0 ) 8000cc6: f001 f891 bl 8001dec /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ /* USER CODE END DMA1_Stream5_IRQn 1 */ } 8000cca: bf00 nop 8000ccc: bd80 pop {r7, pc} 8000cce: bf00 nop 8000cd0: 20000634 .word 0x20000634 08000cd4 : /** * @brief This function handles DMA1 stream6 global interrupt. */ void DMA1_Stream6_IRQHandler(void) { 8000cd4: b580 push {r7, lr} 8000cd6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ /* USER CODE END DMA1_Stream6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 8000cd8: 4802 ldr r0, [pc, #8] @ (8000ce4 ) 8000cda: f001 f887 bl 8001dec /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ /* USER CODE END DMA1_Stream6_IRQn 1 */ } 8000cde: bf00 nop 8000ce0: bd80 pop {r7, pc} 8000ce2: bf00 nop 8000ce4: 20000694 .word 0x20000694 08000ce8 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8000ce8: b580 push {r7, lr} 8000cea: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8000cec: 4802 ldr r0, [pc, #8] @ (8000cf8 ) 8000cee: f004 fe79 bl 80059e4 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8000cf2: bf00 nop 8000cf4: bd80 pop {r7, pc} 8000cf6: bf00 nop 8000cf8: 20000364 .word 0x20000364 08000cfc : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 8000cfc: b580 push {r7, lr} 8000cfe: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 8000d00: 4802 ldr r0, [pc, #8] @ (8000d0c ) 8000d02: f004 fe6f bl 80059e4 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 8000d06: bf00 nop 8000d08: bd80 pop {r7, pc} 8000d0a: bf00 nop 8000d0c: 200003ac .word 0x200003ac 08000d10 : /** * @brief This function handles DMA1 stream7 global interrupt. */ void DMA1_Stream7_IRQHandler(void) { 8000d10: b580 push {r7, lr} 8000d12: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ /* USER CODE END DMA1_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_tx); 8000d14: 4802 ldr r0, [pc, #8] @ (8000d20 ) 8000d16: f001 f869 bl 8001dec /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ /* USER CODE END DMA1_Stream7_IRQn 1 */ } 8000d1a: bf00 nop 8000d1c: bd80 pop {r7, pc} 8000d1e: bf00 nop 8000d20: 20000514 .word 0x20000514 08000d24 : /** * @brief This function handles UART4 global interrupt. */ void UART4_IRQHandler(void) { 8000d24: b580 push {r7, lr} 8000d26: af00 add r7, sp, #0 /* USER CODE BEGIN UART4_IRQn 0 */ /* USER CODE END UART4_IRQn 0 */ HAL_UART_IRQHandler(&huart4); 8000d28: 4802 ldr r0, [pc, #8] @ (8000d34 ) 8000d2a: f004 fe5b bl 80059e4 /* USER CODE BEGIN UART4_IRQn 1 */ /* USER CODE END UART4_IRQn 1 */ } 8000d2e: bf00 nop 8000d30: bd80 pop {r7, pc} 8000d32: bf00 nop 8000d34: 200002d4 .word 0x200002d4 08000d38 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 8000d38: b580 push {r7, lr} 8000d3a: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 8000d3c: 4802 ldr r0, [pc, #8] @ (8000d48 ) 8000d3e: f004 fe51 bl 80059e4 /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 8000d42: bf00 nop 8000d44: bd80 pop {r7, pc} 8000d46: bf00 nop 8000d48: 2000031c .word 0x2000031c 08000d4c : /** * @brief This function handles DMA2 stream2 global interrupt. */ void DMA2_Stream2_IRQHandler(void) { 8000d4c: b580 push {r7, lr} 8000d4e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ /* USER CODE END DMA2_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_rx); 8000d50: 4802 ldr r0, [pc, #8] @ (8000d5c ) 8000d52: f001 f84b bl 8001dec /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ /* USER CODE END DMA2_Stream2_IRQn 1 */ } 8000d56: bf00 nop 8000d58: bd80 pop {r7, pc} 8000d5a: bf00 nop 8000d5c: 20000574 .word 0x20000574 08000d60 : /** * @brief This function handles USB On The Go FS global interrupt. */ void OTG_FS_IRQHandler(void) { 8000d60: b580 push {r7, lr} 8000d62: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_FS_IRQn 0 */ /* USER CODE END OTG_FS_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); 8000d64: 4802 ldr r0, [pc, #8] @ (8000d70 ) 8000d66: f001 ff00 bl 8002b6a /* USER CODE BEGIN OTG_FS_IRQn 1 */ /* USER CODE END OTG_FS_IRQn 1 */ } 8000d6a: bf00 nop 8000d6c: bd80 pop {r7, pc} 8000d6e: bf00 nop 8000d70: 20000bd8 .word 0x20000bd8 08000d74 : /** * @brief This function handles DMA2 stream7 global interrupt. */ void DMA2_Stream7_IRQHandler(void) { 8000d74: b580 push {r7, lr} 8000d76: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ /* USER CODE END DMA2_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 8000d78: 4802 ldr r0, [pc, #8] @ (8000d84 ) 8000d7a: f001 f837 bl 8001dec /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ /* USER CODE END DMA2_Stream7_IRQn 1 */ } 8000d7e: bf00 nop 8000d80: bd80 pop {r7, pc} 8000d82: bf00 nop 8000d84: 200005d4 .word 0x200005d4 08000d88 : * configuration. * @param None * @retval None */ void SystemInit(void) { 8000d88: b480 push {r7} 8000d8a: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8000d8c: 4b06 ldr r3, [pc, #24] @ (8000da8 ) 8000d8e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8000d92: 4a05 ldr r2, [pc, #20] @ (8000da8 ) 8000d94: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8000d98: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8000d9c: bf00 nop 8000d9e: 46bd mov sp, r7 8000da0: f85d 7b04 ldr.w r7, [sp], #4 8000da4: 4770 bx lr 8000da6: bf00 nop 8000da8: e000ed00 .word 0xe000ed00 08000dac : TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; /* TIM2 init function */ void MX_TIM2_Init(void) { 8000dac: b580 push {r7, lr} 8000dae: b08a sub sp, #40 @ 0x28 8000db0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000db2: f107 0320 add.w r3, r7, #32 8000db6: 2200 movs r2, #0 8000db8: 601a str r2, [r3, #0] 8000dba: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 8000dbc: 1d3b adds r3, r7, #4 8000dbe: 2200 movs r2, #0 8000dc0: 601a str r2, [r3, #0] 8000dc2: 605a str r2, [r3, #4] 8000dc4: 609a str r2, [r3, #8] 8000dc6: 60da str r2, [r3, #12] 8000dc8: 611a str r2, [r3, #16] 8000dca: 615a str r2, [r3, #20] 8000dcc: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 8000dce: 4b22 ldr r3, [pc, #136] @ (8000e58 ) 8000dd0: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 8000dd4: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 8000dd6: 4b20 ldr r3, [pc, #128] @ (8000e58 ) 8000dd8: 2200 movs r2, #0 8000dda: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8000ddc: 4b1e ldr r3, [pc, #120] @ (8000e58 ) 8000dde: 2200 movs r2, #0 8000de0: 609a str r2, [r3, #8] htim2.Init.Period = 4294967295; 8000de2: 4b1d ldr r3, [pc, #116] @ (8000e58 ) 8000de4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000de8: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000dea: 4b1b ldr r3, [pc, #108] @ (8000e58 ) 8000dec: 2200 movs r2, #0 8000dee: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000df0: 4b19 ldr r3, [pc, #100] @ (8000e58 ) 8000df2: 2200 movs r2, #0 8000df4: 619a str r2, [r3, #24] if (HAL_TIM_OC_Init(&htim2) != HAL_OK) 8000df6: 4818 ldr r0, [pc, #96] @ (8000e58 ) 8000df8: f004 f904 bl 8005004 8000dfc: 4603 mov r3, r0 8000dfe: 2b00 cmp r3, #0 8000e00: d001 beq.n 8000e06 { Error_Handler(); 8000e02: f7ff fee1 bl 8000bc8 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000e06: 2300 movs r3, #0 8000e08: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000e0a: 2300 movs r3, #0 8000e0c: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8000e0e: f107 0320 add.w r3, r7, #32 8000e12: 4619 mov r1, r3 8000e14: 4810 ldr r0, [pc, #64] @ (8000e58 ) 8000e16: f004 fc9d bl 8005754 8000e1a: 4603 mov r3, r0 8000e1c: 2b00 cmp r3, #0 8000e1e: d001 beq.n 8000e24 { Error_Handler(); 8000e20: f7ff fed2 bl 8000bc8 } sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE; 8000e24: 2350 movs r3, #80 @ 0x50 8000e26: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 8000e28: 2300 movs r3, #0 8000e2a: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8000e2c: 2300 movs r3, #0 8000e2e: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8000e30: 2300 movs r3, #0 8000e32: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8000e34: 1d3b adds r3, r7, #4 8000e36: 2200 movs r2, #0 8000e38: 4619 mov r1, r3 8000e3a: 4807 ldr r0, [pc, #28] @ (8000e58 ) 8000e3c: f004 f9d8 bl 80051f0 8000e40: 4603 mov r3, r0 8000e42: 2b00 cmp r3, #0 8000e44: d001 beq.n 8000e4a { Error_Handler(); 8000e46: f7ff febf bl 8000bc8 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 8000e4a: 4803 ldr r0, [pc, #12] @ (8000e58 ) 8000e4c: f000 f8c2 bl 8000fd4 } 8000e50: bf00 nop 8000e52: 3728 adds r7, #40 @ 0x28 8000e54: 46bd mov sp, r7 8000e56: bd80 pop {r7, pc} 8000e58: 20000244 .word 0x20000244 08000e5c : /* TIM3 init function */ void MX_TIM3_Init(void) { 8000e5c: b580 push {r7, lr} 8000e5e: b08c sub sp, #48 @ 0x30 8000e60: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_Encoder_InitTypeDef sConfig = {0}; 8000e62: f107 030c add.w r3, r7, #12 8000e66: 2224 movs r2, #36 @ 0x24 8000e68: 2100 movs r1, #0 8000e6a: 4618 mov r0, r3 8000e6c: f009 fae2 bl 800a434 TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000e70: 1d3b adds r3, r7, #4 8000e72: 2200 movs r2, #0 8000e74: 601a str r2, [r3, #0] 8000e76: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8000e78: 4b20 ldr r3, [pc, #128] @ (8000efc ) 8000e7a: 4a21 ldr r2, [pc, #132] @ (8000f00 ) 8000e7c: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 8000e7e: 4b1f ldr r3, [pc, #124] @ (8000efc ) 8000e80: 2200 movs r2, #0 8000e82: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8000e84: 4b1d ldr r3, [pc, #116] @ (8000efc ) 8000e86: 2200 movs r2, #0 8000e88: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 8000e8a: 4b1c ldr r3, [pc, #112] @ (8000efc ) 8000e8c: f64f 72ff movw r2, #65535 @ 0xffff 8000e90: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000e92: 4b1a ldr r3, [pc, #104] @ (8000efc ) 8000e94: 2200 movs r2, #0 8000e96: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000e98: 4b18 ldr r3, [pc, #96] @ (8000efc ) 8000e9a: 2200 movs r2, #0 8000e9c: 619a str r2, [r3, #24] sConfig.EncoderMode = TIM_ENCODERMODE_TI1; 8000e9e: 2301 movs r3, #1 8000ea0: 60fb str r3, [r7, #12] sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; 8000ea2: 2300 movs r3, #0 8000ea4: 613b str r3, [r7, #16] sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; 8000ea6: 2301 movs r3, #1 8000ea8: 617b str r3, [r7, #20] sConfig.IC1Prescaler = TIM_ICPSC_DIV1; 8000eaa: 2300 movs r3, #0 8000eac: 61bb str r3, [r7, #24] sConfig.IC1Filter = 0; 8000eae: 2300 movs r3, #0 8000eb0: 61fb str r3, [r7, #28] sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; 8000eb2: 2300 movs r3, #0 8000eb4: 623b str r3, [r7, #32] sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; 8000eb6: 2301 movs r3, #1 8000eb8: 627b str r3, [r7, #36] @ 0x24 sConfig.IC2Prescaler = TIM_ICPSC_DIV1; 8000eba: 2300 movs r3, #0 8000ebc: 62bb str r3, [r7, #40] @ 0x28 sConfig.IC2Filter = 0; 8000ebe: 2300 movs r3, #0 8000ec0: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) 8000ec2: f107 030c add.w r3, r7, #12 8000ec6: 4619 mov r1, r3 8000ec8: 480c ldr r0, [pc, #48] @ (8000efc ) 8000eca: f004 f8ea bl 80050a2 8000ece: 4603 mov r3, r0 8000ed0: 2b00 cmp r3, #0 8000ed2: d001 beq.n 8000ed8 { Error_Handler(); 8000ed4: f7ff fe78 bl 8000bc8 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000ed8: 2300 movs r3, #0 8000eda: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000edc: 2300 movs r3, #0 8000ede: 60bb str r3, [r7, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8000ee0: 1d3b adds r3, r7, #4 8000ee2: 4619 mov r1, r3 8000ee4: 4805 ldr r0, [pc, #20] @ (8000efc ) 8000ee6: f004 fc35 bl 8005754 8000eea: 4603 mov r3, r0 8000eec: 2b00 cmp r3, #0 8000eee: d001 beq.n 8000ef4 { Error_Handler(); 8000ef0: f7ff fe6a bl 8000bc8 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8000ef4: bf00 nop 8000ef6: 3730 adds r7, #48 @ 0x30 8000ef8: 46bd mov sp, r7 8000efa: bd80 pop {r7, pc} 8000efc: 2000028c .word 0x2000028c 8000f00: 40000400 .word 0x40000400 08000f04 : void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle) { 8000f04: b480 push {r7} 8000f06: b085 sub sp, #20 8000f08: af00 add r7, sp, #0 8000f0a: 6078 str r0, [r7, #4] if(tim_ocHandle->Instance==TIM2) 8000f0c: 687b ldr r3, [r7, #4] 8000f0e: 681b ldr r3, [r3, #0] 8000f10: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8000f14: d10d bne.n 8000f32 { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* TIM2 clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 8000f16: 2300 movs r3, #0 8000f18: 60fb str r3, [r7, #12] 8000f1a: 4b09 ldr r3, [pc, #36] @ (8000f40 ) 8000f1c: 6c1b ldr r3, [r3, #64] @ 0x40 8000f1e: 4a08 ldr r2, [pc, #32] @ (8000f40 ) 8000f20: f043 0301 orr.w r3, r3, #1 8000f24: 6413 str r3, [r2, #64] @ 0x40 8000f26: 4b06 ldr r3, [pc, #24] @ (8000f40 ) 8000f28: 6c1b ldr r3, [r3, #64] @ 0x40 8000f2a: f003 0301 and.w r3, r3, #1 8000f2e: 60fb str r3, [r7, #12] 8000f30: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } } 8000f32: bf00 nop 8000f34: 3714 adds r7, #20 8000f36: 46bd mov sp, r7 8000f38: f85d 7b04 ldr.w r7, [sp], #4 8000f3c: 4770 bx lr 8000f3e: bf00 nop 8000f40: 40023800 .word 0x40023800 08000f44 : void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) { 8000f44: b580 push {r7, lr} 8000f46: b08a sub sp, #40 @ 0x28 8000f48: af00 add r7, sp, #0 8000f4a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000f4c: f107 0314 add.w r3, r7, #20 8000f50: 2200 movs r2, #0 8000f52: 601a str r2, [r3, #0] 8000f54: 605a str r2, [r3, #4] 8000f56: 609a str r2, [r3, #8] 8000f58: 60da str r2, [r3, #12] 8000f5a: 611a str r2, [r3, #16] if(tim_encoderHandle->Instance==TIM3) 8000f5c: 687b ldr r3, [r7, #4] 8000f5e: 681b ldr r3, [r3, #0] 8000f60: 4a19 ldr r2, [pc, #100] @ (8000fc8 ) 8000f62: 4293 cmp r3, r2 8000f64: d12b bne.n 8000fbe { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 8000f66: 2300 movs r3, #0 8000f68: 613b str r3, [r7, #16] 8000f6a: 4b18 ldr r3, [pc, #96] @ (8000fcc ) 8000f6c: 6c1b ldr r3, [r3, #64] @ 0x40 8000f6e: 4a17 ldr r2, [pc, #92] @ (8000fcc ) 8000f70: f043 0302 orr.w r3, r3, #2 8000f74: 6413 str r3, [r2, #64] @ 0x40 8000f76: 4b15 ldr r3, [pc, #84] @ (8000fcc ) 8000f78: 6c1b ldr r3, [r3, #64] @ 0x40 8000f7a: f003 0302 and.w r3, r3, #2 8000f7e: 613b str r3, [r7, #16] 8000f80: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000f82: 2300 movs r3, #0 8000f84: 60fb str r3, [r7, #12] 8000f86: 4b11 ldr r3, [pc, #68] @ (8000fcc ) 8000f88: 6b1b ldr r3, [r3, #48] @ 0x30 8000f8a: 4a10 ldr r2, [pc, #64] @ (8000fcc ) 8000f8c: f043 0301 orr.w r3, r3, #1 8000f90: 6313 str r3, [r2, #48] @ 0x30 8000f92: 4b0e ldr r3, [pc, #56] @ (8000fcc ) 8000f94: 6b1b ldr r3, [r3, #48] @ 0x30 8000f96: f003 0301 and.w r3, r3, #1 8000f9a: 60fb str r3, [r7, #12] 8000f9c: 68fb ldr r3, [r7, #12] /**TIM3 GPIO Configuration PA6 ------> TIM3_CH1 PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 8000f9e: 23c0 movs r3, #192 @ 0xc0 8000fa0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000fa2: 2302 movs r3, #2 8000fa4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000fa6: 2300 movs r3, #0 8000fa8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000faa: 2300 movs r3, #0 8000fac: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 8000fae: 2302 movs r3, #2 8000fb0: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000fb2: f107 0314 add.w r3, r7, #20 8000fb6: 4619 mov r1, r3 8000fb8: 4805 ldr r0, [pc, #20] @ (8000fd0 ) 8000fba: f001 f981 bl 80022c0 /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8000fbe: bf00 nop 8000fc0: 3728 adds r7, #40 @ 0x28 8000fc2: 46bd mov sp, r7 8000fc4: bd80 pop {r7, pc} 8000fc6: bf00 nop 8000fc8: 40000400 .word 0x40000400 8000fcc: 40023800 .word 0x40023800 8000fd0: 40020000 .word 0x40020000 08000fd4 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 8000fd4: b580 push {r7, lr} 8000fd6: b088 sub sp, #32 8000fd8: af00 add r7, sp, #0 8000fda: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000fdc: f107 030c add.w r3, r7, #12 8000fe0: 2200 movs r2, #0 8000fe2: 601a str r2, [r3, #0] 8000fe4: 605a str r2, [r3, #4] 8000fe6: 609a str r2, [r3, #8] 8000fe8: 60da str r2, [r3, #12] 8000fea: 611a str r2, [r3, #16] if(timHandle->Instance==TIM2) 8000fec: 687b ldr r3, [r7, #4] 8000fee: 681b ldr r3, [r3, #0] 8000ff0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8000ff4: d11d bne.n 8001032 { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8000ff6: 2300 movs r3, #0 8000ff8: 60bb str r3, [r7, #8] 8000ffa: 4b10 ldr r3, [pc, #64] @ (800103c ) 8000ffc: 6b1b ldr r3, [r3, #48] @ 0x30 8000ffe: 4a0f ldr r2, [pc, #60] @ (800103c ) 8001000: f043 0301 orr.w r3, r3, #1 8001004: 6313 str r3, [r2, #48] @ 0x30 8001006: 4b0d ldr r3, [pc, #52] @ (800103c ) 8001008: 6b1b ldr r3, [r3, #48] @ 0x30 800100a: f003 0301 and.w r3, r3, #1 800100e: 60bb str r3, [r7, #8] 8001010: 68bb ldr r3, [r7, #8] /**TIM2 GPIO Configuration PA5 ------> TIM2_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_5; 8001012: 2320 movs r3, #32 8001014: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001016: 2302 movs r3, #2 8001018: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800101a: 2300 movs r3, #0 800101c: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800101e: 2300 movs r3, #0 8001020: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 8001022: 2301 movs r3, #1 8001024: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001026: f107 030c add.w r3, r7, #12 800102a: 4619 mov r1, r3 800102c: 4804 ldr r0, [pc, #16] @ (8001040 ) 800102e: f001 f947 bl 80022c0 /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8001032: bf00 nop 8001034: 3720 adds r7, #32 8001036: 46bd mov sp, r7 8001038: bd80 pop {r7, pc} 800103a: bf00 nop 800103c: 40023800 .word 0x40023800 8001040: 40020000 .word 0x40020000 08001044 : DMA_HandleTypeDef hdma_usart2_rx; DMA_HandleTypeDef hdma_usart2_tx; /* UART4 init function */ void MX_UART4_Init(void) { 8001044: b580 push {r7, lr} 8001046: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; 8001048: 4b11 ldr r3, [pc, #68] @ (8001090 ) 800104a: 4a12 ldr r2, [pc, #72] @ (8001094 ) 800104c: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; 800104e: 4b10 ldr r3, [pc, #64] @ (8001090 ) 8001050: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001054: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; 8001056: 4b0e ldr r3, [pc, #56] @ (8001090 ) 8001058: 2200 movs r2, #0 800105a: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; 800105c: 4b0c ldr r3, [pc, #48] @ (8001090 ) 800105e: 2200 movs r2, #0 8001060: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; 8001062: 4b0b ldr r3, [pc, #44] @ (8001090 ) 8001064: 2200 movs r2, #0 8001066: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; 8001068: 4b09 ldr r3, [pc, #36] @ (8001090 ) 800106a: 220c movs r2, #12 800106c: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800106e: 4b08 ldr r3, [pc, #32] @ (8001090 ) 8001070: 2200 movs r2, #0 8001072: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; 8001074: 4b06 ldr r3, [pc, #24] @ (8001090 ) 8001076: 2200 movs r2, #0 8001078: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart4) != HAL_OK) 800107a: 4805 ldr r0, [pc, #20] @ (8001090 ) 800107c: f004 fbe6 bl 800584c 8001080: 4603 mov r3, r0 8001082: 2b00 cmp r3, #0 8001084: d001 beq.n 800108a { Error_Handler(); 8001086: f7ff fd9f bl 8000bc8 } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } 800108a: bf00 nop 800108c: bd80 pop {r7, pc} 800108e: bf00 nop 8001090: 200002d4 .word 0x200002d4 8001094: 40004c00 .word 0x40004c00 08001098 : /* UART5 init function */ void MX_UART5_Init(void) { 8001098: b580 push {r7, lr} 800109a: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800109c: 4b11 ldr r3, [pc, #68] @ (80010e4 ) 800109e: 4a12 ldr r2, [pc, #72] @ (80010e8 ) 80010a0: 601a str r2, [r3, #0] huart5.Init.BaudRate = 115200; 80010a2: 4b10 ldr r3, [pc, #64] @ (80010e4 ) 80010a4: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80010a8: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 80010aa: 4b0e ldr r3, [pc, #56] @ (80010e4 ) 80010ac: 2200 movs r2, #0 80010ae: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 80010b0: 4b0c ldr r3, [pc, #48] @ (80010e4 ) 80010b2: 2200 movs r2, #0 80010b4: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 80010b6: 4b0b ldr r3, [pc, #44] @ (80010e4 ) 80010b8: 2200 movs r2, #0 80010ba: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 80010bc: 4b09 ldr r3, [pc, #36] @ (80010e4 ) 80010be: 220c movs r2, #12 80010c0: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80010c2: 4b08 ldr r3, [pc, #32] @ (80010e4 ) 80010c4: 2200 movs r2, #0 80010c6: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 80010c8: 4b06 ldr r3, [pc, #24] @ (80010e4 ) 80010ca: 2200 movs r2, #0 80010cc: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 80010ce: 4805 ldr r0, [pc, #20] @ (80010e4 ) 80010d0: f004 fbbc bl 800584c 80010d4: 4603 mov r3, r0 80010d6: 2b00 cmp r3, #0 80010d8: d001 beq.n 80010de { Error_Handler(); 80010da: f7ff fd75 bl 8000bc8 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 80010de: bf00 nop 80010e0: bd80 pop {r7, pc} 80010e2: bf00 nop 80010e4: 2000031c .word 0x2000031c 80010e8: 40005000 .word 0x40005000 080010ec : /* USART1 init function */ void MX_USART1_UART_Init(void) { 80010ec: b580 push {r7, lr} 80010ee: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 80010f0: 4b11 ldr r3, [pc, #68] @ (8001138 ) 80010f2: 4a12 ldr r2, [pc, #72] @ (800113c ) 80010f4: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 80010f6: 4b10 ldr r3, [pc, #64] @ (8001138 ) 80010f8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80010fc: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 80010fe: 4b0e ldr r3, [pc, #56] @ (8001138 ) 8001100: 2200 movs r2, #0 8001102: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8001104: 4b0c ldr r3, [pc, #48] @ (8001138 ) 8001106: 2200 movs r2, #0 8001108: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800110a: 4b0b ldr r3, [pc, #44] @ (8001138 ) 800110c: 2200 movs r2, #0 800110e: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001110: 4b09 ldr r3, [pc, #36] @ (8001138 ) 8001112: 220c movs r2, #12 8001114: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001116: 4b08 ldr r3, [pc, #32] @ (8001138 ) 8001118: 2200 movs r2, #0 800111a: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800111c: 4b06 ldr r3, [pc, #24] @ (8001138 ) 800111e: 2200 movs r2, #0 8001120: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8001122: 4805 ldr r0, [pc, #20] @ (8001138 ) 8001124: f004 fb92 bl 800584c 8001128: 4603 mov r3, r0 800112a: 2b00 cmp r3, #0 800112c: d001 beq.n 8001132 { Error_Handler(); 800112e: f7ff fd4b bl 8000bc8 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8001132: bf00 nop 8001134: bd80 pop {r7, pc} 8001136: bf00 nop 8001138: 20000364 .word 0x20000364 800113c: 40011000 .word 0x40011000 08001140 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 8001140: b580 push {r7, lr} 8001142: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8001144: 4b11 ldr r3, [pc, #68] @ (800118c ) 8001146: 4a12 ldr r2, [pc, #72] @ (8001190 ) 8001148: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800114a: 4b10 ldr r3, [pc, #64] @ (800118c ) 800114c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001150: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8001152: 4b0e ldr r3, [pc, #56] @ (800118c ) 8001154: 2200 movs r2, #0 8001156: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8001158: 4b0c ldr r3, [pc, #48] @ (800118c ) 800115a: 2200 movs r2, #0 800115c: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800115e: 4b0b ldr r3, [pc, #44] @ (800118c ) 8001160: 2200 movs r2, #0 8001162: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8001164: 4b09 ldr r3, [pc, #36] @ (800118c ) 8001166: 220c movs r2, #12 8001168: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800116a: 4b08 ldr r3, [pc, #32] @ (800118c ) 800116c: 2200 movs r2, #0 800116e: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8001170: 4b06 ldr r3, [pc, #24] @ (800118c ) 8001172: 2200 movs r2, #0 8001174: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 8001176: 4805 ldr r0, [pc, #20] @ (800118c ) 8001178: f004 fb68 bl 800584c 800117c: 4603 mov r3, r0 800117e: 2b00 cmp r3, #0 8001180: d001 beq.n 8001186 { Error_Handler(); 8001182: f7ff fd21 bl 8000bc8 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8001186: bf00 nop 8001188: bd80 pop {r7, pc} 800118a: bf00 nop 800118c: 200003ac .word 0x200003ac 8001190: 40004400 .word 0x40004400 08001194 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8001194: b580 push {r7, lr} 8001196: b090 sub sp, #64 @ 0x40 8001198: af00 add r7, sp, #0 800119a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800119c: f107 032c add.w r3, r7, #44 @ 0x2c 80011a0: 2200 movs r2, #0 80011a2: 601a str r2, [r3, #0] 80011a4: 605a str r2, [r3, #4] 80011a6: 609a str r2, [r3, #8] 80011a8: 60da str r2, [r3, #12] 80011aa: 611a str r2, [r3, #16] if(uartHandle->Instance==UART4) 80011ac: 687b ldr r3, [r7, #4] 80011ae: 681b ldr r3, [r3, #0] 80011b0: 4a4a ldr r2, [pc, #296] @ (80012dc ) 80011b2: 4293 cmp r3, r2 80011b4: f040 80a0 bne.w 80012f8 { /* USER CODE BEGIN UART4_MspInit 0 */ /* USER CODE END UART4_MspInit 0 */ /* UART4 clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); 80011b8: 2300 movs r3, #0 80011ba: 62bb str r3, [r7, #40] @ 0x28 80011bc: 4b48 ldr r3, [pc, #288] @ (80012e0 ) 80011be: 6c1b ldr r3, [r3, #64] @ 0x40 80011c0: 4a47 ldr r2, [pc, #284] @ (80012e0 ) 80011c2: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80011c6: 6413 str r3, [r2, #64] @ 0x40 80011c8: 4b45 ldr r3, [pc, #276] @ (80012e0 ) 80011ca: 6c1b ldr r3, [r3, #64] @ 0x40 80011cc: f403 2300 and.w r3, r3, #524288 @ 0x80000 80011d0: 62bb str r3, [r7, #40] @ 0x28 80011d2: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOA_CLK_ENABLE(); 80011d4: 2300 movs r3, #0 80011d6: 627b str r3, [r7, #36] @ 0x24 80011d8: 4b41 ldr r3, [pc, #260] @ (80012e0 ) 80011da: 6b1b ldr r3, [r3, #48] @ 0x30 80011dc: 4a40 ldr r2, [pc, #256] @ (80012e0 ) 80011de: f043 0301 orr.w r3, r3, #1 80011e2: 6313 str r3, [r2, #48] @ 0x30 80011e4: 4b3e ldr r3, [pc, #248] @ (80012e0 ) 80011e6: 6b1b ldr r3, [r3, #48] @ 0x30 80011e8: f003 0301 and.w r3, r3, #1 80011ec: 627b str r3, [r7, #36] @ 0x24 80011ee: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART4 GPIO Configuration PA0-WKUP ------> UART4_TX PA1 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 80011f0: 2303 movs r3, #3 80011f2: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80011f4: 2302 movs r3, #2 80011f6: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80011f8: 2300 movs r3, #0 80011fa: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80011fc: 2303 movs r3, #3 80011fe: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 8001200: 2308 movs r3, #8 8001202: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001204: f107 032c add.w r3, r7, #44 @ 0x2c 8001208: 4619 mov r1, r3 800120a: 4836 ldr r0, [pc, #216] @ (80012e4 ) 800120c: f001 f858 bl 80022c0 /* UART4 DMA Init */ /* UART4_RX Init */ hdma_uart4_rx.Instance = DMA1_Stream2; 8001210: 4b35 ldr r3, [pc, #212] @ (80012e8 ) 8001212: 4a36 ldr r2, [pc, #216] @ (80012ec ) 8001214: 601a str r2, [r3, #0] hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4; 8001216: 4b34 ldr r3, [pc, #208] @ (80012e8 ) 8001218: f04f 6200 mov.w r2, #134217728 @ 0x8000000 800121c: 605a str r2, [r3, #4] hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800121e: 4b32 ldr r3, [pc, #200] @ (80012e8 ) 8001220: 2200 movs r2, #0 8001222: 609a str r2, [r3, #8] hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001224: 4b30 ldr r3, [pc, #192] @ (80012e8 ) 8001226: 2200 movs r2, #0 8001228: 60da str r2, [r3, #12] hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE; 800122a: 4b2f ldr r3, [pc, #188] @ (80012e8 ) 800122c: f44f 6280 mov.w r2, #1024 @ 0x400 8001230: 611a str r2, [r3, #16] hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001232: 4b2d ldr r3, [pc, #180] @ (80012e8 ) 8001234: 2200 movs r2, #0 8001236: 615a str r2, [r3, #20] hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001238: 4b2b ldr r3, [pc, #172] @ (80012e8 ) 800123a: 2200 movs r2, #0 800123c: 619a str r2, [r3, #24] hdma_uart4_rx.Init.Mode = DMA_NORMAL; 800123e: 4b2a ldr r3, [pc, #168] @ (80012e8 ) 8001240: 2200 movs r2, #0 8001242: 61da str r2, [r3, #28] hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW; 8001244: 4b28 ldr r3, [pc, #160] @ (80012e8 ) 8001246: 2200 movs r2, #0 8001248: 621a str r2, [r3, #32] hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800124a: 4b27 ldr r3, [pc, #156] @ (80012e8 ) 800124c: 2200 movs r2, #0 800124e: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK) 8001250: 4825 ldr r0, [pc, #148] @ (80012e8 ) 8001252: f000 fc33 bl 8001abc 8001256: 4603 mov r3, r0 8001258: 2b00 cmp r3, #0 800125a: d001 beq.n 8001260 { Error_Handler(); 800125c: f7ff fcb4 bl 8000bc8 } __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx); 8001260: 687b ldr r3, [r7, #4] 8001262: 4a21 ldr r2, [pc, #132] @ (80012e8 ) 8001264: 63da str r2, [r3, #60] @ 0x3c 8001266: 4a20 ldr r2, [pc, #128] @ (80012e8 ) 8001268: 687b ldr r3, [r7, #4] 800126a: 6393 str r3, [r2, #56] @ 0x38 /* UART4_TX Init */ hdma_uart4_tx.Instance = DMA1_Stream4; 800126c: 4b20 ldr r3, [pc, #128] @ (80012f0 ) 800126e: 4a21 ldr r2, [pc, #132] @ (80012f4 ) 8001270: 601a str r2, [r3, #0] hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4; 8001272: 4b1f ldr r3, [pc, #124] @ (80012f0 ) 8001274: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001278: 605a str r2, [r3, #4] hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800127a: 4b1d ldr r3, [pc, #116] @ (80012f0 ) 800127c: 2240 movs r2, #64 @ 0x40 800127e: 609a str r2, [r3, #8] hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001280: 4b1b ldr r3, [pc, #108] @ (80012f0 ) 8001282: 2200 movs r2, #0 8001284: 60da str r2, [r3, #12] hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE; 8001286: 4b1a ldr r3, [pc, #104] @ (80012f0 ) 8001288: f44f 6280 mov.w r2, #1024 @ 0x400 800128c: 611a str r2, [r3, #16] hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800128e: 4b18 ldr r3, [pc, #96] @ (80012f0 ) 8001290: 2200 movs r2, #0 8001292: 615a str r2, [r3, #20] hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001294: 4b16 ldr r3, [pc, #88] @ (80012f0 ) 8001296: 2200 movs r2, #0 8001298: 619a str r2, [r3, #24] hdma_uart4_tx.Init.Mode = DMA_NORMAL; 800129a: 4b15 ldr r3, [pc, #84] @ (80012f0 ) 800129c: 2200 movs r2, #0 800129e: 61da str r2, [r3, #28] hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW; 80012a0: 4b13 ldr r3, [pc, #76] @ (80012f0 ) 80012a2: 2200 movs r2, #0 80012a4: 621a str r2, [r3, #32] hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80012a6: 4b12 ldr r3, [pc, #72] @ (80012f0 ) 80012a8: 2200 movs r2, #0 80012aa: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK) 80012ac: 4810 ldr r0, [pc, #64] @ (80012f0 ) 80012ae: f000 fc05 bl 8001abc 80012b2: 4603 mov r3, r0 80012b4: 2b00 cmp r3, #0 80012b6: d001 beq.n 80012bc { Error_Handler(); 80012b8: f7ff fc86 bl 8000bc8 } __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); 80012bc: 687b ldr r3, [r7, #4] 80012be: 4a0c ldr r2, [pc, #48] @ (80012f0 ) 80012c0: 639a str r2, [r3, #56] @ 0x38 80012c2: 4a0b ldr r2, [pc, #44] @ (80012f0 ) 80012c4: 687b ldr r3, [r7, #4] 80012c6: 6393 str r3, [r2, #56] @ 0x38 /* UART4 interrupt Init */ HAL_NVIC_SetPriority(UART4_IRQn, 0, 0); 80012c8: 2200 movs r2, #0 80012ca: 2100 movs r1, #0 80012cc: 2034 movs r0, #52 @ 0x34 80012ce: f000 fbbe bl 8001a4e HAL_NVIC_EnableIRQ(UART4_IRQn); 80012d2: 2034 movs r0, #52 @ 0x34 80012d4: f000 fbd7 bl 8001a86 HAL_NVIC_EnableIRQ(USART2_IRQn); /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 80012d8: e202 b.n 80016e0 80012da: bf00 nop 80012dc: 40004c00 .word 0x40004c00 80012e0: 40023800 .word 0x40023800 80012e4: 40020000 .word 0x40020000 80012e8: 200003f4 .word 0x200003f4 80012ec: 40026040 .word 0x40026040 80012f0: 20000454 .word 0x20000454 80012f4: 40026070 .word 0x40026070 else if(uartHandle->Instance==UART5) 80012f8: 687b ldr r3, [r7, #4] 80012fa: 681b ldr r3, [r3, #0] 80012fc: 4a59 ldr r2, [pc, #356] @ (8001464 ) 80012fe: 4293 cmp r3, r2 8001300: f040 80c0 bne.w 8001484 __HAL_RCC_UART5_CLK_ENABLE(); 8001304: 2300 movs r3, #0 8001306: 623b str r3, [r7, #32] 8001308: 4b57 ldr r3, [pc, #348] @ (8001468 ) 800130a: 6c1b ldr r3, [r3, #64] @ 0x40 800130c: 4a56 ldr r2, [pc, #344] @ (8001468 ) 800130e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8001312: 6413 str r3, [r2, #64] @ 0x40 8001314: 4b54 ldr r3, [pc, #336] @ (8001468 ) 8001316: 6c1b ldr r3, [r3, #64] @ 0x40 8001318: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800131c: 623b str r3, [r7, #32] 800131e: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001320: 2300 movs r3, #0 8001322: 61fb str r3, [r7, #28] 8001324: 4b50 ldr r3, [pc, #320] @ (8001468 ) 8001326: 6b1b ldr r3, [r3, #48] @ 0x30 8001328: 4a4f ldr r2, [pc, #316] @ (8001468 ) 800132a: f043 0304 orr.w r3, r3, #4 800132e: 6313 str r3, [r2, #48] @ 0x30 8001330: 4b4d ldr r3, [pc, #308] @ (8001468 ) 8001332: 6b1b ldr r3, [r3, #48] @ 0x30 8001334: f003 0304 and.w r3, r3, #4 8001338: 61fb str r3, [r7, #28] 800133a: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOD_CLK_ENABLE(); 800133c: 2300 movs r3, #0 800133e: 61bb str r3, [r7, #24] 8001340: 4b49 ldr r3, [pc, #292] @ (8001468 ) 8001342: 6b1b ldr r3, [r3, #48] @ 0x30 8001344: 4a48 ldr r2, [pc, #288] @ (8001468 ) 8001346: f043 0308 orr.w r3, r3, #8 800134a: 6313 str r3, [r2, #48] @ 0x30 800134c: 4b46 ldr r3, [pc, #280] @ (8001468 ) 800134e: 6b1b ldr r3, [r3, #48] @ 0x30 8001350: f003 0308 and.w r3, r3, #8 8001354: 61bb str r3, [r7, #24] 8001356: 69bb ldr r3, [r7, #24] GPIO_InitStruct.Pin = GPIO_PIN_12; 8001358: f44f 5380 mov.w r3, #4096 @ 0x1000 800135c: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800135e: 2302 movs r3, #2 8001360: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001362: 2300 movs r3, #0 8001364: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001366: 2303 movs r3, #3 8001368: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 800136a: 2308 movs r3, #8 800136c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800136e: f107 032c add.w r3, r7, #44 @ 0x2c 8001372: 4619 mov r1, r3 8001374: 483d ldr r0, [pc, #244] @ (800146c ) 8001376: f000 ffa3 bl 80022c0 GPIO_InitStruct.Pin = GPIO_PIN_2; 800137a: 2304 movs r3, #4 800137c: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800137e: 2302 movs r3, #2 8001380: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001382: 2300 movs r3, #0 8001384: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001386: 2303 movs r3, #3 8001388: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 800138a: 2308 movs r3, #8 800138c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800138e: f107 032c add.w r3, r7, #44 @ 0x2c 8001392: 4619 mov r1, r3 8001394: 4836 ldr r0, [pc, #216] @ (8001470 ) 8001396: f000 ff93 bl 80022c0 hdma_uart5_rx.Instance = DMA1_Stream0; 800139a: 4b36 ldr r3, [pc, #216] @ (8001474 ) 800139c: 4a36 ldr r2, [pc, #216] @ (8001478 ) 800139e: 601a str r2, [r3, #0] hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4; 80013a0: 4b34 ldr r3, [pc, #208] @ (8001474 ) 80013a2: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80013a6: 605a str r2, [r3, #4] hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80013a8: 4b32 ldr r3, [pc, #200] @ (8001474 ) 80013aa: 2200 movs r2, #0 80013ac: 609a str r2, [r3, #8] hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE; 80013ae: 4b31 ldr r3, [pc, #196] @ (8001474 ) 80013b0: 2200 movs r2, #0 80013b2: 60da str r2, [r3, #12] hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE; 80013b4: 4b2f ldr r3, [pc, #188] @ (8001474 ) 80013b6: f44f 6280 mov.w r2, #1024 @ 0x400 80013ba: 611a str r2, [r3, #16] hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80013bc: 4b2d ldr r3, [pc, #180] @ (8001474 ) 80013be: 2200 movs r2, #0 80013c0: 615a str r2, [r3, #20] hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80013c2: 4b2c ldr r3, [pc, #176] @ (8001474 ) 80013c4: 2200 movs r2, #0 80013c6: 619a str r2, [r3, #24] hdma_uart5_rx.Init.Mode = DMA_NORMAL; 80013c8: 4b2a ldr r3, [pc, #168] @ (8001474 ) 80013ca: 2200 movs r2, #0 80013cc: 61da str r2, [r3, #28] hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; 80013ce: 4b29 ldr r3, [pc, #164] @ (8001474 ) 80013d0: 2200 movs r2, #0 80013d2: 621a str r2, [r3, #32] hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80013d4: 4b27 ldr r3, [pc, #156] @ (8001474 ) 80013d6: 2200 movs r2, #0 80013d8: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) 80013da: 4826 ldr r0, [pc, #152] @ (8001474 ) 80013dc: f000 fb6e bl 8001abc 80013e0: 4603 mov r3, r0 80013e2: 2b00 cmp r3, #0 80013e4: d001 beq.n 80013ea Error_Handler(); 80013e6: f7ff fbef bl 8000bc8 __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx); 80013ea: 687b ldr r3, [r7, #4] 80013ec: 4a21 ldr r2, [pc, #132] @ (8001474 ) 80013ee: 63da str r2, [r3, #60] @ 0x3c 80013f0: 4a20 ldr r2, [pc, #128] @ (8001474 ) 80013f2: 687b ldr r3, [r7, #4] 80013f4: 6393 str r3, [r2, #56] @ 0x38 hdma_uart5_tx.Instance = DMA1_Stream7; 80013f6: 4b21 ldr r3, [pc, #132] @ (800147c ) 80013f8: 4a21 ldr r2, [pc, #132] @ (8001480 ) 80013fa: 601a str r2, [r3, #0] hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4; 80013fc: 4b1f ldr r3, [pc, #124] @ (800147c ) 80013fe: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001402: 605a str r2, [r3, #4] hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001404: 4b1d ldr r3, [pc, #116] @ (800147c ) 8001406: 2240 movs r2, #64 @ 0x40 8001408: 609a str r2, [r3, #8] hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800140a: 4b1c ldr r3, [pc, #112] @ (800147c ) 800140c: 2200 movs r2, #0 800140e: 60da str r2, [r3, #12] hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE; 8001410: 4b1a ldr r3, [pc, #104] @ (800147c ) 8001412: f44f 6280 mov.w r2, #1024 @ 0x400 8001416: 611a str r2, [r3, #16] hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001418: 4b18 ldr r3, [pc, #96] @ (800147c ) 800141a: 2200 movs r2, #0 800141c: 615a str r2, [r3, #20] hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800141e: 4b17 ldr r3, [pc, #92] @ (800147c ) 8001420: 2200 movs r2, #0 8001422: 619a str r2, [r3, #24] hdma_uart5_tx.Init.Mode = DMA_NORMAL; 8001424: 4b15 ldr r3, [pc, #84] @ (800147c ) 8001426: 2200 movs r2, #0 8001428: 61da str r2, [r3, #28] hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; 800142a: 4b14 ldr r3, [pc, #80] @ (800147c ) 800142c: 2200 movs r2, #0 800142e: 621a str r2, [r3, #32] hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001430: 4b12 ldr r3, [pc, #72] @ (800147c ) 8001432: 2200 movs r2, #0 8001434: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) 8001436: 4811 ldr r0, [pc, #68] @ (800147c ) 8001438: f000 fb40 bl 8001abc 800143c: 4603 mov r3, r0 800143e: 2b00 cmp r3, #0 8001440: d001 beq.n 8001446 Error_Handler(); 8001442: f7ff fbc1 bl 8000bc8 __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); 8001446: 687b ldr r3, [r7, #4] 8001448: 4a0c ldr r2, [pc, #48] @ (800147c ) 800144a: 639a str r2, [r3, #56] @ 0x38 800144c: 4a0b ldr r2, [pc, #44] @ (800147c ) 800144e: 687b ldr r3, [r7, #4] 8001450: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(UART5_IRQn, 0, 0); 8001452: 2200 movs r2, #0 8001454: 2100 movs r1, #0 8001456: 2035 movs r0, #53 @ 0x35 8001458: f000 faf9 bl 8001a4e HAL_NVIC_EnableIRQ(UART5_IRQn); 800145c: 2035 movs r0, #53 @ 0x35 800145e: f000 fb12 bl 8001a86 } 8001462: e13d b.n 80016e0 8001464: 40005000 .word 0x40005000 8001468: 40023800 .word 0x40023800 800146c: 40020800 .word 0x40020800 8001470: 40020c00 .word 0x40020c00 8001474: 200004b4 .word 0x200004b4 8001478: 40026010 .word 0x40026010 800147c: 20000514 .word 0x20000514 8001480: 400260b8 .word 0x400260b8 else if(uartHandle->Instance==USART1) 8001484: 687b ldr r3, [r7, #4] 8001486: 681b ldr r3, [r3, #0] 8001488: 4a97 ldr r2, [pc, #604] @ (80016e8 ) 800148a: 4293 cmp r3, r2 800148c: f040 8092 bne.w 80015b4 __HAL_RCC_USART1_CLK_ENABLE(); 8001490: 2300 movs r3, #0 8001492: 617b str r3, [r7, #20] 8001494: 4b95 ldr r3, [pc, #596] @ (80016ec ) 8001496: 6c5b ldr r3, [r3, #68] @ 0x44 8001498: 4a94 ldr r2, [pc, #592] @ (80016ec ) 800149a: f043 0310 orr.w r3, r3, #16 800149e: 6453 str r3, [r2, #68] @ 0x44 80014a0: 4b92 ldr r3, [pc, #584] @ (80016ec ) 80014a2: 6c5b ldr r3, [r3, #68] @ 0x44 80014a4: f003 0310 and.w r3, r3, #16 80014a8: 617b str r3, [r7, #20] 80014aa: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80014ac: 2300 movs r3, #0 80014ae: 613b str r3, [r7, #16] 80014b0: 4b8e ldr r3, [pc, #568] @ (80016ec ) 80014b2: 6b1b ldr r3, [r3, #48] @ 0x30 80014b4: 4a8d ldr r2, [pc, #564] @ (80016ec ) 80014b6: f043 0301 orr.w r3, r3, #1 80014ba: 6313 str r3, [r2, #48] @ 0x30 80014bc: 4b8b ldr r3, [pc, #556] @ (80016ec ) 80014be: 6b1b ldr r3, [r3, #48] @ 0x30 80014c0: f003 0301 and.w r3, r3, #1 80014c4: 613b str r3, [r7, #16] 80014c6: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 80014c8: f44f 63c0 mov.w r3, #1536 @ 0x600 80014cc: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80014ce: 2302 movs r3, #2 80014d0: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80014d2: 2300 movs r3, #0 80014d4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80014d6: 2303 movs r3, #3 80014d8: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 80014da: 2307 movs r3, #7 80014dc: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80014de: f107 032c add.w r3, r7, #44 @ 0x2c 80014e2: 4619 mov r1, r3 80014e4: 4882 ldr r0, [pc, #520] @ (80016f0 ) 80014e6: f000 feeb bl 80022c0 hdma_usart1_rx.Instance = DMA2_Stream2; 80014ea: 4b82 ldr r3, [pc, #520] @ (80016f4 ) 80014ec: 4a82 ldr r2, [pc, #520] @ (80016f8 ) 80014ee: 601a str r2, [r3, #0] hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; 80014f0: 4b80 ldr r3, [pc, #512] @ (80016f4 ) 80014f2: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80014f6: 605a str r2, [r3, #4] hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80014f8: 4b7e ldr r3, [pc, #504] @ (80016f4 ) 80014fa: 2200 movs r2, #0 80014fc: 609a str r2, [r3, #8] hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 80014fe: 4b7d ldr r3, [pc, #500] @ (80016f4 ) 8001500: 2200 movs r2, #0 8001502: 60da str r2, [r3, #12] hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 8001504: 4b7b ldr r3, [pc, #492] @ (80016f4 ) 8001506: f44f 6280 mov.w r2, #1024 @ 0x400 800150a: 611a str r2, [r3, #16] hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800150c: 4b79 ldr r3, [pc, #484] @ (80016f4 ) 800150e: 2200 movs r2, #0 8001510: 615a str r2, [r3, #20] hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001512: 4b78 ldr r3, [pc, #480] @ (80016f4 ) 8001514: 2200 movs r2, #0 8001516: 619a str r2, [r3, #24] hdma_usart1_rx.Init.Mode = DMA_NORMAL; 8001518: 4b76 ldr r3, [pc, #472] @ (80016f4 ) 800151a: 2200 movs r2, #0 800151c: 61da str r2, [r3, #28] hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; 800151e: 4b75 ldr r3, [pc, #468] @ (80016f4 ) 8001520: 2200 movs r2, #0 8001522: 621a str r2, [r3, #32] hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001524: 4b73 ldr r3, [pc, #460] @ (80016f4 ) 8001526: 2200 movs r2, #0 8001528: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 800152a: 4872 ldr r0, [pc, #456] @ (80016f4 ) 800152c: f000 fac6 bl 8001abc 8001530: 4603 mov r3, r0 8001532: 2b00 cmp r3, #0 8001534: d001 beq.n 800153a Error_Handler(); 8001536: f7ff fb47 bl 8000bc8 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); 800153a: 687b ldr r3, [r7, #4] 800153c: 4a6d ldr r2, [pc, #436] @ (80016f4 ) 800153e: 63da str r2, [r3, #60] @ 0x3c 8001540: 4a6c ldr r2, [pc, #432] @ (80016f4 ) 8001542: 687b ldr r3, [r7, #4] 8001544: 6393 str r3, [r2, #56] @ 0x38 hdma_usart1_tx.Instance = DMA2_Stream7; 8001546: 4b6d ldr r3, [pc, #436] @ (80016fc ) 8001548: 4a6d ldr r2, [pc, #436] @ (8001700 ) 800154a: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; 800154c: 4b6b ldr r3, [pc, #428] @ (80016fc ) 800154e: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001552: 605a str r2, [r3, #4] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001554: 4b69 ldr r3, [pc, #420] @ (80016fc ) 8001556: 2240 movs r2, #64 @ 0x40 8001558: 609a str r2, [r3, #8] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800155a: 4b68 ldr r3, [pc, #416] @ (80016fc ) 800155c: 2200 movs r2, #0 800155e: 60da str r2, [r3, #12] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 8001560: 4b66 ldr r3, [pc, #408] @ (80016fc ) 8001562: f44f 6280 mov.w r2, #1024 @ 0x400 8001566: 611a str r2, [r3, #16] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001568: 4b64 ldr r3, [pc, #400] @ (80016fc ) 800156a: 2200 movs r2, #0 800156c: 615a str r2, [r3, #20] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800156e: 4b63 ldr r3, [pc, #396] @ (80016fc ) 8001570: 2200 movs r2, #0 8001572: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 8001574: 4b61 ldr r3, [pc, #388] @ (80016fc ) 8001576: 2200 movs r2, #0 8001578: 61da str r2, [r3, #28] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 800157a: 4b60 ldr r3, [pc, #384] @ (80016fc ) 800157c: 2200 movs r2, #0 800157e: 621a str r2, [r3, #32] hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001580: 4b5e ldr r3, [pc, #376] @ (80016fc ) 8001582: 2200 movs r2, #0 8001584: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 8001586: 485d ldr r0, [pc, #372] @ (80016fc ) 8001588: f000 fa98 bl 8001abc 800158c: 4603 mov r3, r0 800158e: 2b00 cmp r3, #0 8001590: d001 beq.n 8001596 Error_Handler(); 8001592: f7ff fb19 bl 8000bc8 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); 8001596: 687b ldr r3, [r7, #4] 8001598: 4a58 ldr r2, [pc, #352] @ (80016fc ) 800159a: 639a str r2, [r3, #56] @ 0x38 800159c: 4a57 ldr r2, [pc, #348] @ (80016fc ) 800159e: 687b ldr r3, [r7, #4] 80015a0: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 80015a2: 2200 movs r2, #0 80015a4: 2100 movs r1, #0 80015a6: 2025 movs r0, #37 @ 0x25 80015a8: f000 fa51 bl 8001a4e HAL_NVIC_EnableIRQ(USART1_IRQn); 80015ac: 2025 movs r0, #37 @ 0x25 80015ae: f000 fa6a bl 8001a86 } 80015b2: e095 b.n 80016e0 else if(uartHandle->Instance==USART2) 80015b4: 687b ldr r3, [r7, #4] 80015b6: 681b ldr r3, [r3, #0] 80015b8: 4a52 ldr r2, [pc, #328] @ (8001704 ) 80015ba: 4293 cmp r3, r2 80015bc: f040 8090 bne.w 80016e0 __HAL_RCC_USART2_CLK_ENABLE(); 80015c0: 2300 movs r3, #0 80015c2: 60fb str r3, [r7, #12] 80015c4: 4b49 ldr r3, [pc, #292] @ (80016ec ) 80015c6: 6c1b ldr r3, [r3, #64] @ 0x40 80015c8: 4a48 ldr r2, [pc, #288] @ (80016ec ) 80015ca: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80015ce: 6413 str r3, [r2, #64] @ 0x40 80015d0: 4b46 ldr r3, [pc, #280] @ (80016ec ) 80015d2: 6c1b ldr r3, [r3, #64] @ 0x40 80015d4: f403 3300 and.w r3, r3, #131072 @ 0x20000 80015d8: 60fb str r3, [r7, #12] 80015da: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 80015dc: 2300 movs r3, #0 80015de: 60bb str r3, [r7, #8] 80015e0: 4b42 ldr r3, [pc, #264] @ (80016ec ) 80015e2: 6b1b ldr r3, [r3, #48] @ 0x30 80015e4: 4a41 ldr r2, [pc, #260] @ (80016ec ) 80015e6: f043 0301 orr.w r3, r3, #1 80015ea: 6313 str r3, [r2, #48] @ 0x30 80015ec: 4b3f ldr r3, [pc, #252] @ (80016ec ) 80015ee: 6b1b ldr r3, [r3, #48] @ 0x30 80015f0: f003 0301 and.w r3, r3, #1 80015f4: 60bb str r3, [r7, #8] 80015f6: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; 80015f8: 230c movs r3, #12 80015fa: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80015fc: 2302 movs r3, #2 80015fe: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001600: 2300 movs r3, #0 8001602: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001604: 2303 movs r3, #3 8001606: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 8001608: 2307 movs r3, #7 800160a: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800160c: f107 032c add.w r3, r7, #44 @ 0x2c 8001610: 4619 mov r1, r3 8001612: 4837 ldr r0, [pc, #220] @ (80016f0 ) 8001614: f000 fe54 bl 80022c0 hdma_usart2_rx.Instance = DMA1_Stream5; 8001618: 4b3b ldr r3, [pc, #236] @ (8001708 ) 800161a: 4a3c ldr r2, [pc, #240] @ (800170c ) 800161c: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; 800161e: 4b3a ldr r3, [pc, #232] @ (8001708 ) 8001620: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001624: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001626: 4b38 ldr r3, [pc, #224] @ (8001708 ) 8001628: 2200 movs r2, #0 800162a: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800162c: 4b36 ldr r3, [pc, #216] @ (8001708 ) 800162e: 2200 movs r2, #0 8001630: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 8001632: 4b35 ldr r3, [pc, #212] @ (8001708 ) 8001634: f44f 6280 mov.w r2, #1024 @ 0x400 8001638: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800163a: 4b33 ldr r3, [pc, #204] @ (8001708 ) 800163c: 2200 movs r2, #0 800163e: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001640: 4b31 ldr r3, [pc, #196] @ (8001708 ) 8001642: 2200 movs r2, #0 8001644: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 8001646: 4b30 ldr r3, [pc, #192] @ (8001708 ) 8001648: 2200 movs r2, #0 800164a: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; 800164c: 4b2e ldr r3, [pc, #184] @ (8001708 ) 800164e: 2200 movs r2, #0 8001650: 621a str r2, [r3, #32] hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001652: 4b2d ldr r3, [pc, #180] @ (8001708 ) 8001654: 2200 movs r2, #0 8001656: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 8001658: 482b ldr r0, [pc, #172] @ (8001708 ) 800165a: f000 fa2f bl 8001abc 800165e: 4603 mov r3, r0 8001660: 2b00 cmp r3, #0 8001662: d001 beq.n 8001668 Error_Handler(); 8001664: f7ff fab0 bl 8000bc8 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 8001668: 687b ldr r3, [r7, #4] 800166a: 4a27 ldr r2, [pc, #156] @ (8001708 ) 800166c: 63da str r2, [r3, #60] @ 0x3c 800166e: 4a26 ldr r2, [pc, #152] @ (8001708 ) 8001670: 687b ldr r3, [r7, #4] 8001672: 6393 str r3, [r2, #56] @ 0x38 hdma_usart2_tx.Instance = DMA1_Stream6; 8001674: 4b26 ldr r3, [pc, #152] @ (8001710 ) 8001676: 4a27 ldr r2, [pc, #156] @ (8001714 ) 8001678: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; 800167a: 4b25 ldr r3, [pc, #148] @ (8001710 ) 800167c: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001680: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001682: 4b23 ldr r3, [pc, #140] @ (8001710 ) 8001684: 2240 movs r2, #64 @ 0x40 8001686: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001688: 4b21 ldr r3, [pc, #132] @ (8001710 ) 800168a: 2200 movs r2, #0 800168c: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 800168e: 4b20 ldr r3, [pc, #128] @ (8001710 ) 8001690: f44f 6280 mov.w r2, #1024 @ 0x400 8001694: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001696: 4b1e ldr r3, [pc, #120] @ (8001710 ) 8001698: 2200 movs r2, #0 800169a: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800169c: 4b1c ldr r3, [pc, #112] @ (8001710 ) 800169e: 2200 movs r2, #0 80016a0: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 80016a2: 4b1b ldr r3, [pc, #108] @ (8001710 ) 80016a4: 2200 movs r2, #0 80016a6: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; 80016a8: 4b19 ldr r3, [pc, #100] @ (8001710 ) 80016aa: 2200 movs r2, #0 80016ac: 621a str r2, [r3, #32] hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80016ae: 4b18 ldr r3, [pc, #96] @ (8001710 ) 80016b0: 2200 movs r2, #0 80016b2: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 80016b4: 4816 ldr r0, [pc, #88] @ (8001710 ) 80016b6: f000 fa01 bl 8001abc 80016ba: 4603 mov r3, r0 80016bc: 2b00 cmp r3, #0 80016be: d001 beq.n 80016c4 Error_Handler(); 80016c0: f7ff fa82 bl 8000bc8 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 80016c4: 687b ldr r3, [r7, #4] 80016c6: 4a12 ldr r2, [pc, #72] @ (8001710 ) 80016c8: 639a str r2, [r3, #56] @ 0x38 80016ca: 4a11 ldr r2, [pc, #68] @ (8001710 ) 80016cc: 687b ldr r3, [r7, #4] 80016ce: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 80016d0: 2200 movs r2, #0 80016d2: 2100 movs r1, #0 80016d4: 2026 movs r0, #38 @ 0x26 80016d6: f000 f9ba bl 8001a4e HAL_NVIC_EnableIRQ(USART2_IRQn); 80016da: 2026 movs r0, #38 @ 0x26 80016dc: f000 f9d3 bl 8001a86 } 80016e0: bf00 nop 80016e2: 3740 adds r7, #64 @ 0x40 80016e4: 46bd mov sp, r7 80016e6: bd80 pop {r7, pc} 80016e8: 40011000 .word 0x40011000 80016ec: 40023800 .word 0x40023800 80016f0: 40020000 .word 0x40020000 80016f4: 20000574 .word 0x20000574 80016f8: 40026440 .word 0x40026440 80016fc: 200005d4 .word 0x200005d4 8001700: 400264b8 .word 0x400264b8 8001704: 40004400 .word 0x40004400 8001708: 20000634 .word 0x20000634 800170c: 40026088 .word 0x40026088 8001710: 20000694 .word 0x20000694 8001714: 400260a0 .word 0x400260a0 08001718 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001718: f8df d034 ldr.w sp, [pc, #52] @ 8001750 /* Call the clock system initialization function.*/ bl SystemInit 800171c: f7ff fb34 bl 8000d88 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001720: 480c ldr r0, [pc, #48] @ (8001754 ) ldr r1, =_edata 8001722: 490d ldr r1, [pc, #52] @ (8001758 ) ldr r2, =_sidata 8001724: 4a0d ldr r2, [pc, #52] @ (800175c ) movs r3, #0 8001726: 2300 movs r3, #0 b LoopCopyDataInit 8001728: e002 b.n 8001730 0800172a : CopyDataInit: ldr r4, [r2, r3] 800172a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800172c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800172e: 3304 adds r3, #4 08001730 : LoopCopyDataInit: adds r4, r0, r3 8001730: 18c4 adds r4, r0, r3 cmp r4, r1 8001732: 428c cmp r4, r1 bcc CopyDataInit 8001734: d3f9 bcc.n 800172a /* Zero fill the bss segment. */ ldr r2, =_sbss 8001736: 4a0a ldr r2, [pc, #40] @ (8001760 ) ldr r4, =_ebss 8001738: 4c0a ldr r4, [pc, #40] @ (8001764 ) movs r3, #0 800173a: 2300 movs r3, #0 b LoopFillZerobss 800173c: e001 b.n 8001742 0800173e : FillZerobss: str r3, [r2] 800173e: 6013 str r3, [r2, #0] adds r2, r2, #4 8001740: 3204 adds r2, #4 08001742 : LoopFillZerobss: cmp r2, r4 8001742: 42a2 cmp r2, r4 bcc FillZerobss 8001744: d3fb bcc.n 800173e /* Call static constructors */ bl __libc_init_array 8001746: f008 fe7d bl 800a444 <__libc_init_array> /* Call the application's entry point.*/ bl main 800174a: f7ff f86d bl 8000828
bx lr 800174e: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001750: 20020000 .word 0x20020000 ldr r0, =_sdata 8001754: 20000000 .word 0x20000000 ldr r1, =_edata 8001758: 200001bc .word 0x200001bc ldr r2, =_sidata 800175c: 0800a510 .word 0x0800a510 ldr r2, =_sbss 8001760: 200001bc .word 0x200001bc ldr r4, =_ebss 8001764: 200010d0 .word 0x200010d0 08001768 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001768: e7fe b.n 8001768 ... 0800176c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800176c: b580 push {r7, lr} 800176e: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 8001770: 4b0e ldr r3, [pc, #56] @ (80017ac ) 8001772: 681b ldr r3, [r3, #0] 8001774: 4a0d ldr r2, [pc, #52] @ (80017ac ) 8001776: f443 7300 orr.w r3, r3, #512 @ 0x200 800177a: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 800177c: 4b0b ldr r3, [pc, #44] @ (80017ac ) 800177e: 681b ldr r3, [r3, #0] 8001780: 4a0a ldr r2, [pc, #40] @ (80017ac ) 8001782: f443 6380 orr.w r3, r3, #1024 @ 0x400 8001786: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001788: 4b08 ldr r3, [pc, #32] @ (80017ac ) 800178a: 681b ldr r3, [r3, #0] 800178c: 4a07 ldr r2, [pc, #28] @ (80017ac ) 800178e: f443 7380 orr.w r3, r3, #256 @ 0x100 8001792: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001794: 2003 movs r0, #3 8001796: f000 f94f bl 8001a38 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800179a: 200f movs r0, #15 800179c: f000 f808 bl 80017b0 /* Init the low level hardware */ HAL_MspInit(); 80017a0: f7ff fa18 bl 8000bd4 /* Return function status */ return HAL_OK; 80017a4: 2300 movs r3, #0 } 80017a6: 4618 mov r0, r3 80017a8: bd80 pop {r7, pc} 80017aa: bf00 nop 80017ac: 40023c00 .word 0x40023c00 080017b0 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80017b0: b580 push {r7, lr} 80017b2: b082 sub sp, #8 80017b4: af00 add r7, sp, #0 80017b6: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80017b8: 4b12 ldr r3, [pc, #72] @ (8001804 ) 80017ba: 681a ldr r2, [r3, #0] 80017bc: 4b12 ldr r3, [pc, #72] @ (8001808 ) 80017be: 781b ldrb r3, [r3, #0] 80017c0: 4619 mov r1, r3 80017c2: f44f 737a mov.w r3, #1000 @ 0x3e8 80017c6: fbb3 f3f1 udiv r3, r3, r1 80017ca: fbb2 f3f3 udiv r3, r2, r3 80017ce: 4618 mov r0, r3 80017d0: f000 f967 bl 8001aa2 80017d4: 4603 mov r3, r0 80017d6: 2b00 cmp r3, #0 80017d8: d001 beq.n 80017de { return HAL_ERROR; 80017da: 2301 movs r3, #1 80017dc: e00e b.n 80017fc } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80017de: 687b ldr r3, [r7, #4] 80017e0: 2b0f cmp r3, #15 80017e2: d80a bhi.n 80017fa { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80017e4: 2200 movs r2, #0 80017e6: 6879 ldr r1, [r7, #4] 80017e8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80017ec: f000 f92f bl 8001a4e uwTickPrio = TickPriority; 80017f0: 4a06 ldr r2, [pc, #24] @ (800180c ) 80017f2: 687b ldr r3, [r7, #4] 80017f4: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80017f6: 2300 movs r3, #0 80017f8: e000 b.n 80017fc return HAL_ERROR; 80017fa: 2301 movs r3, #1 } 80017fc: 4618 mov r0, r3 80017fe: 3708 adds r7, #8 8001800: 46bd mov sp, r7 8001802: bd80 pop {r7, pc} 8001804: 20000090 .word 0x20000090 8001808: 20000098 .word 0x20000098 800180c: 20000094 .word 0x20000094 08001810 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001810: b480 push {r7} 8001812: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001814: 4b06 ldr r3, [pc, #24] @ (8001830 ) 8001816: 781b ldrb r3, [r3, #0] 8001818: 461a mov r2, r3 800181a: 4b06 ldr r3, [pc, #24] @ (8001834 ) 800181c: 681b ldr r3, [r3, #0] 800181e: 4413 add r3, r2 8001820: 4a04 ldr r2, [pc, #16] @ (8001834 ) 8001822: 6013 str r3, [r2, #0] } 8001824: bf00 nop 8001826: 46bd mov sp, r7 8001828: f85d 7b04 ldr.w r7, [sp], #4 800182c: 4770 bx lr 800182e: bf00 nop 8001830: 20000098 .word 0x20000098 8001834: 200006f4 .word 0x200006f4 08001838 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001838: b480 push {r7} 800183a: af00 add r7, sp, #0 return uwTick; 800183c: 4b03 ldr r3, [pc, #12] @ (800184c ) 800183e: 681b ldr r3, [r3, #0] } 8001840: 4618 mov r0, r3 8001842: 46bd mov sp, r7 8001844: f85d 7b04 ldr.w r7, [sp], #4 8001848: 4770 bx lr 800184a: bf00 nop 800184c: 200006f4 .word 0x200006f4 08001850 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001850: b580 push {r7, lr} 8001852: b084 sub sp, #16 8001854: af00 add r7, sp, #0 8001856: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001858: f7ff ffee bl 8001838 800185c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800185e: 687b ldr r3, [r7, #4] 8001860: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001862: 68fb ldr r3, [r7, #12] 8001864: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8001868: d005 beq.n 8001876 { wait += (uint32_t)(uwTickFreq); 800186a: 4b0a ldr r3, [pc, #40] @ (8001894 ) 800186c: 781b ldrb r3, [r3, #0] 800186e: 461a mov r2, r3 8001870: 68fb ldr r3, [r7, #12] 8001872: 4413 add r3, r2 8001874: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8001876: bf00 nop 8001878: f7ff ffde bl 8001838 800187c: 4602 mov r2, r0 800187e: 68bb ldr r3, [r7, #8] 8001880: 1ad3 subs r3, r2, r3 8001882: 68fa ldr r2, [r7, #12] 8001884: 429a cmp r2, r3 8001886: d8f7 bhi.n 8001878 { } } 8001888: bf00 nop 800188a: bf00 nop 800188c: 3710 adds r7, #16 800188e: 46bd mov sp, r7 8001890: bd80 pop {r7, pc} 8001892: bf00 nop 8001894: 20000098 .word 0x20000098 08001898 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001898: b480 push {r7} 800189a: b085 sub sp, #20 800189c: af00 add r7, sp, #0 800189e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80018a0: 687b ldr r3, [r7, #4] 80018a2: f003 0307 and.w r3, r3, #7 80018a6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80018a8: 4b0c ldr r3, [pc, #48] @ (80018dc <__NVIC_SetPriorityGrouping+0x44>) 80018aa: 68db ldr r3, [r3, #12] 80018ac: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80018ae: 68ba ldr r2, [r7, #8] 80018b0: f64f 03ff movw r3, #63743 @ 0xf8ff 80018b4: 4013 ands r3, r2 80018b6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80018b8: 68fb ldr r3, [r7, #12] 80018ba: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80018bc: 68bb ldr r3, [r7, #8] 80018be: 4313 orrs r3, r2 reg_value = (reg_value | 80018c0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 80018c4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80018c8: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80018ca: 4a04 ldr r2, [pc, #16] @ (80018dc <__NVIC_SetPriorityGrouping+0x44>) 80018cc: 68bb ldr r3, [r7, #8] 80018ce: 60d3 str r3, [r2, #12] } 80018d0: bf00 nop 80018d2: 3714 adds r7, #20 80018d4: 46bd mov sp, r7 80018d6: f85d 7b04 ldr.w r7, [sp], #4 80018da: 4770 bx lr 80018dc: e000ed00 .word 0xe000ed00 080018e0 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 80018e0: b480 push {r7} 80018e2: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80018e4: 4b04 ldr r3, [pc, #16] @ (80018f8 <__NVIC_GetPriorityGrouping+0x18>) 80018e6: 68db ldr r3, [r3, #12] 80018e8: 0a1b lsrs r3, r3, #8 80018ea: f003 0307 and.w r3, r3, #7 } 80018ee: 4618 mov r0, r3 80018f0: 46bd mov sp, r7 80018f2: f85d 7b04 ldr.w r7, [sp], #4 80018f6: 4770 bx lr 80018f8: e000ed00 .word 0xe000ed00 080018fc <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80018fc: b480 push {r7} 80018fe: b083 sub sp, #12 8001900: af00 add r7, sp, #0 8001902: 4603 mov r3, r0 8001904: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001906: f997 3007 ldrsb.w r3, [r7, #7] 800190a: 2b00 cmp r3, #0 800190c: db0b blt.n 8001926 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800190e: 79fb ldrb r3, [r7, #7] 8001910: f003 021f and.w r2, r3, #31 8001914: 4907 ldr r1, [pc, #28] @ (8001934 <__NVIC_EnableIRQ+0x38>) 8001916: f997 3007 ldrsb.w r3, [r7, #7] 800191a: 095b lsrs r3, r3, #5 800191c: 2001 movs r0, #1 800191e: fa00 f202 lsl.w r2, r0, r2 8001922: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8001926: bf00 nop 8001928: 370c adds r7, #12 800192a: 46bd mov sp, r7 800192c: f85d 7b04 ldr.w r7, [sp], #4 8001930: 4770 bx lr 8001932: bf00 nop 8001934: e000e100 .word 0xe000e100 08001938 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001938: b480 push {r7} 800193a: b083 sub sp, #12 800193c: af00 add r7, sp, #0 800193e: 4603 mov r3, r0 8001940: 6039 str r1, [r7, #0] 8001942: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001944: f997 3007 ldrsb.w r3, [r7, #7] 8001948: 2b00 cmp r3, #0 800194a: db0a blt.n 8001962 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800194c: 683b ldr r3, [r7, #0] 800194e: b2da uxtb r2, r3 8001950: 490c ldr r1, [pc, #48] @ (8001984 <__NVIC_SetPriority+0x4c>) 8001952: f997 3007 ldrsb.w r3, [r7, #7] 8001956: 0112 lsls r2, r2, #4 8001958: b2d2 uxtb r2, r2 800195a: 440b add r3, r1 800195c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001960: e00a b.n 8001978 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001962: 683b ldr r3, [r7, #0] 8001964: b2da uxtb r2, r3 8001966: 4908 ldr r1, [pc, #32] @ (8001988 <__NVIC_SetPriority+0x50>) 8001968: 79fb ldrb r3, [r7, #7] 800196a: f003 030f and.w r3, r3, #15 800196e: 3b04 subs r3, #4 8001970: 0112 lsls r2, r2, #4 8001972: b2d2 uxtb r2, r2 8001974: 440b add r3, r1 8001976: 761a strb r2, [r3, #24] } 8001978: bf00 nop 800197a: 370c adds r7, #12 800197c: 46bd mov sp, r7 800197e: f85d 7b04 ldr.w r7, [sp], #4 8001982: 4770 bx lr 8001984: e000e100 .word 0xe000e100 8001988: e000ed00 .word 0xe000ed00 0800198c : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 800198c: b480 push {r7} 800198e: b089 sub sp, #36 @ 0x24 8001990: af00 add r7, sp, #0 8001992: 60f8 str r0, [r7, #12] 8001994: 60b9 str r1, [r7, #8] 8001996: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001998: 68fb ldr r3, [r7, #12] 800199a: f003 0307 and.w r3, r3, #7 800199e: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80019a0: 69fb ldr r3, [r7, #28] 80019a2: f1c3 0307 rsb r3, r3, #7 80019a6: 2b04 cmp r3, #4 80019a8: bf28 it cs 80019aa: 2304 movcs r3, #4 80019ac: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80019ae: 69fb ldr r3, [r7, #28] 80019b0: 3304 adds r3, #4 80019b2: 2b06 cmp r3, #6 80019b4: d902 bls.n 80019bc 80019b6: 69fb ldr r3, [r7, #28] 80019b8: 3b03 subs r3, #3 80019ba: e000 b.n 80019be 80019bc: 2300 movs r3, #0 80019be: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80019c0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80019c4: 69bb ldr r3, [r7, #24] 80019c6: fa02 f303 lsl.w r3, r2, r3 80019ca: 43da mvns r2, r3 80019cc: 68bb ldr r3, [r7, #8] 80019ce: 401a ands r2, r3 80019d0: 697b ldr r3, [r7, #20] 80019d2: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80019d4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80019d8: 697b ldr r3, [r7, #20] 80019da: fa01 f303 lsl.w r3, r1, r3 80019de: 43d9 mvns r1, r3 80019e0: 687b ldr r3, [r7, #4] 80019e2: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80019e4: 4313 orrs r3, r2 ); } 80019e6: 4618 mov r0, r3 80019e8: 3724 adds r7, #36 @ 0x24 80019ea: 46bd mov sp, r7 80019ec: f85d 7b04 ldr.w r7, [sp], #4 80019f0: 4770 bx lr ... 080019f4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80019f4: b580 push {r7, lr} 80019f6: b082 sub sp, #8 80019f8: af00 add r7, sp, #0 80019fa: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80019fc: 687b ldr r3, [r7, #4] 80019fe: 3b01 subs r3, #1 8001a00: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8001a04: d301 bcc.n 8001a0a { return (1UL); /* Reload value impossible */ 8001a06: 2301 movs r3, #1 8001a08: e00f b.n 8001a2a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001a0a: 4a0a ldr r2, [pc, #40] @ (8001a34 ) 8001a0c: 687b ldr r3, [r7, #4] 8001a0e: 3b01 subs r3, #1 8001a10: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001a12: 210f movs r1, #15 8001a14: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8001a18: f7ff ff8e bl 8001938 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001a1c: 4b05 ldr r3, [pc, #20] @ (8001a34 ) 8001a1e: 2200 movs r2, #0 8001a20: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001a22: 4b04 ldr r3, [pc, #16] @ (8001a34 ) 8001a24: 2207 movs r2, #7 8001a26: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001a28: 2300 movs r3, #0 } 8001a2a: 4618 mov r0, r3 8001a2c: 3708 adds r7, #8 8001a2e: 46bd mov sp, r7 8001a30: bd80 pop {r7, pc} 8001a32: bf00 nop 8001a34: e000e010 .word 0xe000e010 08001a38 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001a38: b580 push {r7, lr} 8001a3a: b082 sub sp, #8 8001a3c: af00 add r7, sp, #0 8001a3e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001a40: 6878 ldr r0, [r7, #4] 8001a42: f7ff ff29 bl 8001898 <__NVIC_SetPriorityGrouping> } 8001a46: bf00 nop 8001a48: 3708 adds r7, #8 8001a4a: 46bd mov sp, r7 8001a4c: bd80 pop {r7, pc} 08001a4e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001a4e: b580 push {r7, lr} 8001a50: b086 sub sp, #24 8001a52: af00 add r7, sp, #0 8001a54: 4603 mov r3, r0 8001a56: 60b9 str r1, [r7, #8] 8001a58: 607a str r2, [r7, #4] 8001a5a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001a5c: 2300 movs r3, #0 8001a5e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001a60: f7ff ff3e bl 80018e0 <__NVIC_GetPriorityGrouping> 8001a64: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001a66: 687a ldr r2, [r7, #4] 8001a68: 68b9 ldr r1, [r7, #8] 8001a6a: 6978 ldr r0, [r7, #20] 8001a6c: f7ff ff8e bl 800198c 8001a70: 4602 mov r2, r0 8001a72: f997 300f ldrsb.w r3, [r7, #15] 8001a76: 4611 mov r1, r2 8001a78: 4618 mov r0, r3 8001a7a: f7ff ff5d bl 8001938 <__NVIC_SetPriority> } 8001a7e: bf00 nop 8001a80: 3718 adds r7, #24 8001a82: 46bd mov sp, r7 8001a84: bd80 pop {r7, pc} 08001a86 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8001a86: b580 push {r7, lr} 8001a88: b082 sub sp, #8 8001a8a: af00 add r7, sp, #0 8001a8c: 4603 mov r3, r0 8001a8e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001a90: f997 3007 ldrsb.w r3, [r7, #7] 8001a94: 4618 mov r0, r3 8001a96: f7ff ff31 bl 80018fc <__NVIC_EnableIRQ> } 8001a9a: bf00 nop 8001a9c: 3708 adds r7, #8 8001a9e: 46bd mov sp, r7 8001aa0: bd80 pop {r7, pc} 08001aa2 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001aa2: b580 push {r7, lr} 8001aa4: b082 sub sp, #8 8001aa6: af00 add r7, sp, #0 8001aa8: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001aaa: 6878 ldr r0, [r7, #4] 8001aac: f7ff ffa2 bl 80019f4 8001ab0: 4603 mov r3, r0 } 8001ab2: 4618 mov r0, r3 8001ab4: 3708 adds r7, #8 8001ab6: 46bd mov sp, r7 8001ab8: bd80 pop {r7, pc} ... 08001abc : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8001abc: b580 push {r7, lr} 8001abe: b086 sub sp, #24 8001ac0: af00 add r7, sp, #0 8001ac2: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 8001ac4: 2300 movs r3, #0 8001ac6: 617b str r3, [r7, #20] uint32_t tickstart = HAL_GetTick(); 8001ac8: f7ff feb6 bl 8001838 8001acc: 6138 str r0, [r7, #16] DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) 8001ace: 687b ldr r3, [r7, #4] 8001ad0: 2b00 cmp r3, #0 8001ad2: d101 bne.n 8001ad8 { return HAL_ERROR; 8001ad4: 2301 movs r3, #1 8001ad6: e099 b.n 8001c0c assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001ad8: 687b ldr r3, [r7, #4] 8001ada: 2202 movs r2, #2 8001adc: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8001ae0: 687b ldr r3, [r7, #4] 8001ae2: 2200 movs r2, #0 8001ae4: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8001ae8: 687b ldr r3, [r7, #4] 8001aea: 681b ldr r3, [r3, #0] 8001aec: 681a ldr r2, [r3, #0] 8001aee: 687b ldr r3, [r7, #4] 8001af0: 681b ldr r3, [r3, #0] 8001af2: f022 0201 bic.w r2, r2, #1 8001af6: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001af8: e00f b.n 8001b1a { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8001afa: f7ff fe9d bl 8001838 8001afe: 4602 mov r2, r0 8001b00: 693b ldr r3, [r7, #16] 8001b02: 1ad3 subs r3, r2, r3 8001b04: 2b05 cmp r3, #5 8001b06: d908 bls.n 8001b1a { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8001b08: 687b ldr r3, [r7, #4] 8001b0a: 2220 movs r2, #32 8001b0c: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8001b0e: 687b ldr r3, [r7, #4] 8001b10: 2203 movs r2, #3 8001b12: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_TIMEOUT; 8001b16: 2303 movs r3, #3 8001b18: e078 b.n 8001c0c while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001b1a: 687b ldr r3, [r7, #4] 8001b1c: 681b ldr r3, [r3, #0] 8001b1e: 681b ldr r3, [r3, #0] 8001b20: f003 0301 and.w r3, r3, #1 8001b24: 2b00 cmp r3, #0 8001b26: d1e8 bne.n 8001afa } } /* Get the CR register value */ tmp = hdma->Instance->CR; 8001b28: 687b ldr r3, [r7, #4] 8001b2a: 681b ldr r3, [r3, #0] 8001b2c: 681b ldr r3, [r3, #0] 8001b2e: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8001b30: 697a ldr r2, [r7, #20] 8001b32: 4b38 ldr r3, [pc, #224] @ (8001c14 ) 8001b34: 4013 ands r3, r2 8001b36: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001b38: 687b ldr r3, [r7, #4] 8001b3a: 685a ldr r2, [r3, #4] 8001b3c: 687b ldr r3, [r7, #4] 8001b3e: 689b ldr r3, [r3, #8] 8001b40: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001b42: 687b ldr r3, [r7, #4] 8001b44: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001b46: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001b48: 687b ldr r3, [r7, #4] 8001b4a: 691b ldr r3, [r3, #16] 8001b4c: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001b4e: 687b ldr r3, [r7, #4] 8001b50: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8001b52: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001b54: 687b ldr r3, [r7, #4] 8001b56: 699b ldr r3, [r3, #24] 8001b58: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001b5a: 687b ldr r3, [r7, #4] 8001b5c: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001b5e: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001b60: 687b ldr r3, [r7, #4] 8001b62: 6a1b ldr r3, [r3, #32] 8001b64: 4313 orrs r3, r2 tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001b66: 697a ldr r2, [r7, #20] 8001b68: 4313 orrs r3, r2 8001b6a: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001b6c: 687b ldr r3, [r7, #4] 8001b6e: 6a5b ldr r3, [r3, #36] @ 0x24 8001b70: 2b04 cmp r3, #4 8001b72: d107 bne.n 8001b84 { /* Get memory burst and peripheral burst */ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8001b74: 687b ldr r3, [r7, #4] 8001b76: 6ada ldr r2, [r3, #44] @ 0x2c 8001b78: 687b ldr r3, [r7, #4] 8001b7a: 6b1b ldr r3, [r3, #48] @ 0x30 8001b7c: 4313 orrs r3, r2 8001b7e: 697a ldr r2, [r7, #20] 8001b80: 4313 orrs r3, r2 8001b82: 617b str r3, [r7, #20] } /* Write to DMA Stream CR register */ hdma->Instance->CR = tmp; 8001b84: 687b ldr r3, [r7, #4] 8001b86: 681b ldr r3, [r3, #0] 8001b88: 697a ldr r2, [r7, #20] 8001b8a: 601a str r2, [r3, #0] /* Get the FCR register value */ tmp = hdma->Instance->FCR; 8001b8c: 687b ldr r3, [r7, #4] 8001b8e: 681b ldr r3, [r3, #0] 8001b90: 695b ldr r3, [r3, #20] 8001b92: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8001b94: 697b ldr r3, [r7, #20] 8001b96: f023 0307 bic.w r3, r3, #7 8001b9a: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ tmp |= hdma->Init.FIFOMode; 8001b9c: 687b ldr r3, [r7, #4] 8001b9e: 6a5b ldr r3, [r3, #36] @ 0x24 8001ba0: 697a ldr r2, [r7, #20] 8001ba2: 4313 orrs r3, r2 8001ba4: 617b str r3, [r7, #20] /* The FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001ba6: 687b ldr r3, [r7, #4] 8001ba8: 6a5b ldr r3, [r3, #36] @ 0x24 8001baa: 2b04 cmp r3, #4 8001bac: d117 bne.n 8001bde { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; 8001bae: 687b ldr r3, [r7, #4] 8001bb0: 6a9b ldr r3, [r3, #40] @ 0x28 8001bb2: 697a ldr r2, [r7, #20] 8001bb4: 4313 orrs r3, r2 8001bb6: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 bursts */ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8001bb8: 687b ldr r3, [r7, #4] 8001bba: 6adb ldr r3, [r3, #44] @ 0x2c 8001bbc: 2b00 cmp r3, #0 8001bbe: d00e beq.n 8001bde { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8001bc0: 6878 ldr r0, [r7, #4] 8001bc2: f000 fb01 bl 80021c8 8001bc6: 4603 mov r3, r0 8001bc8: 2b00 cmp r3, #0 8001bca: d008 beq.n 8001bde { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8001bcc: 687b ldr r3, [r7, #4] 8001bce: 2240 movs r2, #64 @ 0x40 8001bd0: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001bd2: 687b ldr r3, [r7, #4] 8001bd4: 2201 movs r2, #1 8001bd6: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8001bda: 2301 movs r3, #1 8001bdc: e016 b.n 8001c0c } } } /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; 8001bde: 687b ldr r3, [r7, #4] 8001be0: 681b ldr r3, [r3, #0] 8001be2: 697a ldr r2, [r7, #20] 8001be4: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8001be6: 6878 ldr r0, [r7, #4] 8001be8: f000 fab8 bl 800215c 8001bec: 4603 mov r3, r0 8001bee: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001bf0: 687b ldr r3, [r7, #4] 8001bf2: 6ddb ldr r3, [r3, #92] @ 0x5c 8001bf4: 223f movs r2, #63 @ 0x3f 8001bf6: 409a lsls r2, r3 8001bf8: 68fb ldr r3, [r7, #12] 8001bfa: 609a str r2, [r3, #8] /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001bfc: 687b ldr r3, [r7, #4] 8001bfe: 2200 movs r2, #0 8001c00: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001c02: 687b ldr r3, [r7, #4] 8001c04: 2201 movs r2, #1 8001c06: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8001c0a: 2300 movs r3, #0 } 8001c0c: 4618 mov r0, r3 8001c0e: 3718 adds r7, #24 8001c10: 46bd mov sp, r7 8001c12: bd80 pop {r7, pc} 8001c14: f010803f .word 0xf010803f 08001c18 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8001c18: b580 push {r7, lr} 8001c1a: b086 sub sp, #24 8001c1c: af00 add r7, sp, #0 8001c1e: 60f8 str r0, [r7, #12] 8001c20: 60b9 str r1, [r7, #8] 8001c22: 607a str r2, [r7, #4] 8001c24: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8001c26: 2300 movs r3, #0 8001c28: 75fb strb r3, [r7, #23] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001c2a: 68fb ldr r3, [r7, #12] 8001c2c: 6d9b ldr r3, [r3, #88] @ 0x58 8001c2e: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8001c30: 68fb ldr r3, [r7, #12] 8001c32: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8001c36: 2b01 cmp r3, #1 8001c38: d101 bne.n 8001c3e 8001c3a: 2302 movs r3, #2 8001c3c: e040 b.n 8001cc0 8001c3e: 68fb ldr r3, [r7, #12] 8001c40: 2201 movs r2, #1 8001c42: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8001c46: 68fb ldr r3, [r7, #12] 8001c48: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001c4c: b2db uxtb r3, r3 8001c4e: 2b01 cmp r3, #1 8001c50: d12f bne.n 8001cb2 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001c52: 68fb ldr r3, [r7, #12] 8001c54: 2202 movs r2, #2 8001c56: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001c5a: 68fb ldr r3, [r7, #12] 8001c5c: 2200 movs r2, #0 8001c5e: 655a str r2, [r3, #84] @ 0x54 /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8001c60: 683b ldr r3, [r7, #0] 8001c62: 687a ldr r2, [r7, #4] 8001c64: 68b9 ldr r1, [r7, #8] 8001c66: 68f8 ldr r0, [r7, #12] 8001c68: f000 fa4a bl 8002100 /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001c6c: 68fb ldr r3, [r7, #12] 8001c6e: 6ddb ldr r3, [r3, #92] @ 0x5c 8001c70: 223f movs r2, #63 @ 0x3f 8001c72: 409a lsls r2, r3 8001c74: 693b ldr r3, [r7, #16] 8001c76: 609a str r2, [r3, #8] /* Enable Common interrupts*/ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; 8001c78: 68fb ldr r3, [r7, #12] 8001c7a: 681b ldr r3, [r3, #0] 8001c7c: 681a ldr r2, [r3, #0] 8001c7e: 68fb ldr r3, [r7, #12] 8001c80: 681b ldr r3, [r3, #0] 8001c82: f042 0216 orr.w r2, r2, #22 8001c86: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8001c88: 68fb ldr r3, [r7, #12] 8001c8a: 6c1b ldr r3, [r3, #64] @ 0x40 8001c8c: 2b00 cmp r3, #0 8001c8e: d007 beq.n 8001ca0 { hdma->Instance->CR |= DMA_IT_HT; 8001c90: 68fb ldr r3, [r7, #12] 8001c92: 681b ldr r3, [r3, #0] 8001c94: 681a ldr r2, [r3, #0] 8001c96: 68fb ldr r3, [r7, #12] 8001c98: 681b ldr r3, [r3, #0] 8001c9a: f042 0208 orr.w r2, r2, #8 8001c9e: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8001ca0: 68fb ldr r3, [r7, #12] 8001ca2: 681b ldr r3, [r3, #0] 8001ca4: 681a ldr r2, [r3, #0] 8001ca6: 68fb ldr r3, [r7, #12] 8001ca8: 681b ldr r3, [r3, #0] 8001caa: f042 0201 orr.w r2, r2, #1 8001cae: 601a str r2, [r3, #0] 8001cb0: e005 b.n 8001cbe } else { /* Process unlocked */ __HAL_UNLOCK(hdma); 8001cb2: 68fb ldr r3, [r7, #12] 8001cb4: 2200 movs r2, #0 8001cb6: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_BUSY; 8001cba: 2302 movs r3, #2 8001cbc: 75fb strb r3, [r7, #23] } return status; 8001cbe: 7dfb ldrb r3, [r7, #23] } 8001cc0: 4618 mov r0, r3 8001cc2: 3718 adds r7, #24 8001cc4: 46bd mov sp, r7 8001cc6: bd80 pop {r7, pc} 08001cc8 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8001cc8: b580 push {r7, lr} 8001cca: b084 sub sp, #16 8001ccc: af00 add r7, sp, #0 8001cce: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001cd0: 687b ldr r3, [r7, #4] 8001cd2: 6d9b ldr r3, [r3, #88] @ 0x58 8001cd4: 60fb str r3, [r7, #12] uint32_t tickstart = HAL_GetTick(); 8001cd6: f7ff fdaf bl 8001838 8001cda: 60b8 str r0, [r7, #8] if(hdma->State != HAL_DMA_STATE_BUSY) 8001cdc: 687b ldr r3, [r7, #4] 8001cde: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001ce2: b2db uxtb r3, r3 8001ce4: 2b02 cmp r3, #2 8001ce6: d008 beq.n 8001cfa { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001ce8: 687b ldr r3, [r7, #4] 8001cea: 2280 movs r2, #128 @ 0x80 8001cec: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001cee: 687b ldr r3, [r7, #4] 8001cf0: 2200 movs r2, #0 8001cf2: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8001cf6: 2301 movs r3, #1 8001cf8: e052 b.n 8001da0 } else { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8001cfa: 687b ldr r3, [r7, #4] 8001cfc: 681b ldr r3, [r3, #0] 8001cfe: 681a ldr r2, [r3, #0] 8001d00: 687b ldr r3, [r7, #4] 8001d02: 681b ldr r3, [r3, #0] 8001d04: f022 0216 bic.w r2, r2, #22 8001d08: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 8001d0a: 687b ldr r3, [r7, #4] 8001d0c: 681b ldr r3, [r3, #0] 8001d0e: 695a ldr r2, [r3, #20] 8001d10: 687b ldr r3, [r7, #4] 8001d12: 681b ldr r3, [r3, #0] 8001d14: f022 0280 bic.w r2, r2, #128 @ 0x80 8001d18: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8001d1a: 687b ldr r3, [r7, #4] 8001d1c: 6c1b ldr r3, [r3, #64] @ 0x40 8001d1e: 2b00 cmp r3, #0 8001d20: d103 bne.n 8001d2a 8001d22: 687b ldr r3, [r7, #4] 8001d24: 6c9b ldr r3, [r3, #72] @ 0x48 8001d26: 2b00 cmp r3, #0 8001d28: d007 beq.n 8001d3a { hdma->Instance->CR &= ~(DMA_IT_HT); 8001d2a: 687b ldr r3, [r7, #4] 8001d2c: 681b ldr r3, [r3, #0] 8001d2e: 681a ldr r2, [r3, #0] 8001d30: 687b ldr r3, [r7, #4] 8001d32: 681b ldr r3, [r3, #0] 8001d34: f022 0208 bic.w r2, r2, #8 8001d38: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8001d3a: 687b ldr r3, [r7, #4] 8001d3c: 681b ldr r3, [r3, #0] 8001d3e: 681a ldr r2, [r3, #0] 8001d40: 687b ldr r3, [r7, #4] 8001d42: 681b ldr r3, [r3, #0] 8001d44: f022 0201 bic.w r2, r2, #1 8001d48: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001d4a: e013 b.n 8001d74 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8001d4c: f7ff fd74 bl 8001838 8001d50: 4602 mov r2, r0 8001d52: 68bb ldr r3, [r7, #8] 8001d54: 1ad3 subs r3, r2, r3 8001d56: 2b05 cmp r3, #5 8001d58: d90c bls.n 8001d74 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8001d5a: 687b ldr r3, [r7, #4] 8001d5c: 2220 movs r2, #32 8001d5e: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8001d60: 687b ldr r3, [r7, #4] 8001d62: 2203 movs r2, #3 8001d64: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001d68: 687b ldr r3, [r7, #4] 8001d6a: 2200 movs r2, #0 8001d6c: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_TIMEOUT; 8001d70: 2303 movs r3, #3 8001d72: e015 b.n 8001da0 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001d74: 687b ldr r3, [r7, #4] 8001d76: 681b ldr r3, [r3, #0] 8001d78: 681b ldr r3, [r3, #0] 8001d7a: f003 0301 and.w r3, r3, #1 8001d7e: 2b00 cmp r3, #0 8001d80: d1e4 bne.n 8001d4c } } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001d82: 687b ldr r3, [r7, #4] 8001d84: 6ddb ldr r3, [r3, #92] @ 0x5c 8001d86: 223f movs r2, #63 @ 0x3f 8001d88: 409a lsls r2, r3 8001d8a: 68fb ldr r3, [r7, #12] 8001d8c: 609a str r2, [r3, #8] /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8001d8e: 687b ldr r3, [r7, #4] 8001d90: 2201 movs r2, #1 8001d92: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001d96: 687b ldr r3, [r7, #4] 8001d98: 2200 movs r2, #0 8001d9a: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 8001d9e: 2300 movs r3, #0 } 8001da0: 4618 mov r0, r3 8001da2: 3710 adds r7, #16 8001da4: 46bd mov sp, r7 8001da6: bd80 pop {r7, pc} 08001da8 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8001da8: b480 push {r7} 8001daa: b083 sub sp, #12 8001dac: af00 add r7, sp, #0 8001dae: 6078 str r0, [r7, #4] if(hdma->State != HAL_DMA_STATE_BUSY) 8001db0: 687b ldr r3, [r7, #4] 8001db2: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001db6: b2db uxtb r3, r3 8001db8: 2b02 cmp r3, #2 8001dba: d004 beq.n 8001dc6 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001dbc: 687b ldr r3, [r7, #4] 8001dbe: 2280 movs r2, #128 @ 0x80 8001dc0: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 8001dc2: 2301 movs r3, #1 8001dc4: e00c b.n 8001de0 } else { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 8001dc6: 687b ldr r3, [r7, #4] 8001dc8: 2205 movs r2, #5 8001dca: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8001dce: 687b ldr r3, [r7, #4] 8001dd0: 681b ldr r3, [r3, #0] 8001dd2: 681a ldr r2, [r3, #0] 8001dd4: 687b ldr r3, [r7, #4] 8001dd6: 681b ldr r3, [r3, #0] 8001dd8: f022 0201 bic.w r2, r2, #1 8001ddc: 601a str r2, [r3, #0] } return HAL_OK; 8001dde: 2300 movs r3, #0 } 8001de0: 4618 mov r0, r3 8001de2: 370c adds r7, #12 8001de4: 46bd mov sp, r7 8001de6: f85d 7b04 ldr.w r7, [sp], #4 8001dea: 4770 bx lr 08001dec : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8001dec: b580 push {r7, lr} 8001dee: b086 sub sp, #24 8001df0: af00 add r7, sp, #0 8001df2: 6078 str r0, [r7, #4] uint32_t tmpisr; __IO uint32_t count = 0U; 8001df4: 2300 movs r3, #0 8001df6: 60bb str r3, [r7, #8] uint32_t timeout = SystemCoreClock / 9600U; 8001df8: 4b8e ldr r3, [pc, #568] @ (8002034 ) 8001dfa: 681b ldr r3, [r3, #0] 8001dfc: 4a8e ldr r2, [pc, #568] @ (8002038 ) 8001dfe: fba2 2303 umull r2, r3, r2, r3 8001e02: 0a9b lsrs r3, r3, #10 8001e04: 617b str r3, [r7, #20] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001e06: 687b ldr r3, [r7, #4] 8001e08: 6d9b ldr r3, [r3, #88] @ 0x58 8001e0a: 613b str r3, [r7, #16] tmpisr = regs->ISR; 8001e0c: 693b ldr r3, [r7, #16] 8001e0e: 681b ldr r3, [r3, #0] 8001e10: 60fb str r3, [r7, #12] /* Transfer Error Interrupt management ***************************************/ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) 8001e12: 687b ldr r3, [r7, #4] 8001e14: 6ddb ldr r3, [r3, #92] @ 0x5c 8001e16: 2208 movs r2, #8 8001e18: 409a lsls r2, r3 8001e1a: 68fb ldr r3, [r7, #12] 8001e1c: 4013 ands r3, r2 8001e1e: 2b00 cmp r3, #0 8001e20: d01a beq.n 8001e58 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) 8001e22: 687b ldr r3, [r7, #4] 8001e24: 681b ldr r3, [r3, #0] 8001e26: 681b ldr r3, [r3, #0] 8001e28: f003 0304 and.w r3, r3, #4 8001e2c: 2b00 cmp r3, #0 8001e2e: d013 beq.n 8001e58 { /* Disable the transfer error interrupt */ hdma->Instance->CR &= ~(DMA_IT_TE); 8001e30: 687b ldr r3, [r7, #4] 8001e32: 681b ldr r3, [r3, #0] 8001e34: 681a ldr r2, [r3, #0] 8001e36: 687b ldr r3, [r7, #4] 8001e38: 681b ldr r3, [r3, #0] 8001e3a: f022 0204 bic.w r2, r2, #4 8001e3e: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; 8001e40: 687b ldr r3, [r7, #4] 8001e42: 6ddb ldr r3, [r3, #92] @ 0x5c 8001e44: 2208 movs r2, #8 8001e46: 409a lsls r2, r3 8001e48: 693b ldr r3, [r7, #16] 8001e4a: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8001e4c: 687b ldr r3, [r7, #4] 8001e4e: 6d5b ldr r3, [r3, #84] @ 0x54 8001e50: f043 0201 orr.w r2, r3, #1 8001e54: 687b ldr r3, [r7, #4] 8001e56: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) 8001e58: 687b ldr r3, [r7, #4] 8001e5a: 6ddb ldr r3, [r3, #92] @ 0x5c 8001e5c: 2201 movs r2, #1 8001e5e: 409a lsls r2, r3 8001e60: 68fb ldr r3, [r7, #12] 8001e62: 4013 ands r3, r2 8001e64: 2b00 cmp r3, #0 8001e66: d012 beq.n 8001e8e { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) 8001e68: 687b ldr r3, [r7, #4] 8001e6a: 681b ldr r3, [r3, #0] 8001e6c: 695b ldr r3, [r3, #20] 8001e6e: f003 0380 and.w r3, r3, #128 @ 0x80 8001e72: 2b00 cmp r3, #0 8001e74: d00b beq.n 8001e8e { /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; 8001e76: 687b ldr r3, [r7, #4] 8001e78: 6ddb ldr r3, [r3, #92] @ 0x5c 8001e7a: 2201 movs r2, #1 8001e7c: 409a lsls r2, r3 8001e7e: 693b ldr r3, [r7, #16] 8001e80: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8001e82: 687b ldr r3, [r7, #4] 8001e84: 6d5b ldr r3, [r3, #84] @ 0x54 8001e86: f043 0202 orr.w r2, r3, #2 8001e8a: 687b ldr r3, [r7, #4] 8001e8c: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) 8001e8e: 687b ldr r3, [r7, #4] 8001e90: 6ddb ldr r3, [r3, #92] @ 0x5c 8001e92: 2204 movs r2, #4 8001e94: 409a lsls r2, r3 8001e96: 68fb ldr r3, [r7, #12] 8001e98: 4013 ands r3, r2 8001e9a: 2b00 cmp r3, #0 8001e9c: d012 beq.n 8001ec4 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) 8001e9e: 687b ldr r3, [r7, #4] 8001ea0: 681b ldr r3, [r3, #0] 8001ea2: 681b ldr r3, [r3, #0] 8001ea4: f003 0302 and.w r3, r3, #2 8001ea8: 2b00 cmp r3, #0 8001eaa: d00b beq.n 8001ec4 { /* Clear the direct mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; 8001eac: 687b ldr r3, [r7, #4] 8001eae: 6ddb ldr r3, [r3, #92] @ 0x5c 8001eb0: 2204 movs r2, #4 8001eb2: 409a lsls r2, r3 8001eb4: 693b ldr r3, [r7, #16] 8001eb6: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8001eb8: 687b ldr r3, [r7, #4] 8001eba: 6d5b ldr r3, [r3, #84] @ 0x54 8001ebc: f043 0204 orr.w r2, r3, #4 8001ec0: 687b ldr r3, [r7, #4] 8001ec2: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) 8001ec4: 687b ldr r3, [r7, #4] 8001ec6: 6ddb ldr r3, [r3, #92] @ 0x5c 8001ec8: 2210 movs r2, #16 8001eca: 409a lsls r2, r3 8001ecc: 68fb ldr r3, [r7, #12] 8001ece: 4013 ands r3, r2 8001ed0: 2b00 cmp r3, #0 8001ed2: d043 beq.n 8001f5c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) 8001ed4: 687b ldr r3, [r7, #4] 8001ed6: 681b ldr r3, [r3, #0] 8001ed8: 681b ldr r3, [r3, #0] 8001eda: f003 0308 and.w r3, r3, #8 8001ede: 2b00 cmp r3, #0 8001ee0: d03c beq.n 8001f5c { /* Clear the half transfer complete flag */ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; 8001ee2: 687b ldr r3, [r7, #4] 8001ee4: 6ddb ldr r3, [r3, #92] @ 0x5c 8001ee6: 2210 movs r2, #16 8001ee8: 409a lsls r2, r3 8001eea: 693b ldr r3, [r7, #16] 8001eec: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 8001eee: 687b ldr r3, [r7, #4] 8001ef0: 681b ldr r3, [r3, #0] 8001ef2: 681b ldr r3, [r3, #0] 8001ef4: f403 2380 and.w r3, r3, #262144 @ 0x40000 8001ef8: 2b00 cmp r3, #0 8001efa: d018 beq.n 8001f2e { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 8001efc: 687b ldr r3, [r7, #4] 8001efe: 681b ldr r3, [r3, #0] 8001f00: 681b ldr r3, [r3, #0] 8001f02: f403 2300 and.w r3, r3, #524288 @ 0x80000 8001f06: 2b00 cmp r3, #0 8001f08: d108 bne.n 8001f1c { if(hdma->XferHalfCpltCallback != NULL) 8001f0a: 687b ldr r3, [r7, #4] 8001f0c: 6c1b ldr r3, [r3, #64] @ 0x40 8001f0e: 2b00 cmp r3, #0 8001f10: d024 beq.n 8001f5c { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8001f12: 687b ldr r3, [r7, #4] 8001f14: 6c1b ldr r3, [r3, #64] @ 0x40 8001f16: 6878 ldr r0, [r7, #4] 8001f18: 4798 blx r3 8001f1a: e01f b.n 8001f5c } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 8001f1c: 687b ldr r3, [r7, #4] 8001f1e: 6c9b ldr r3, [r3, #72] @ 0x48 8001f20: 2b00 cmp r3, #0 8001f22: d01b beq.n 8001f5c { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8001f24: 687b ldr r3, [r7, #4] 8001f26: 6c9b ldr r3, [r3, #72] @ 0x48 8001f28: 6878 ldr r0, [r7, #4] 8001f2a: 4798 blx r3 8001f2c: e016 b.n 8001f5c } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 8001f2e: 687b ldr r3, [r7, #4] 8001f30: 681b ldr r3, [r3, #0] 8001f32: 681b ldr r3, [r3, #0] 8001f34: f403 7380 and.w r3, r3, #256 @ 0x100 8001f38: 2b00 cmp r3, #0 8001f3a: d107 bne.n 8001f4c { /* Disable the half transfer interrupt */ hdma->Instance->CR &= ~(DMA_IT_HT); 8001f3c: 687b ldr r3, [r7, #4] 8001f3e: 681b ldr r3, [r3, #0] 8001f40: 681a ldr r2, [r3, #0] 8001f42: 687b ldr r3, [r7, #4] 8001f44: 681b ldr r3, [r3, #0] 8001f46: f022 0208 bic.w r2, r2, #8 8001f4a: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 8001f4c: 687b ldr r3, [r7, #4] 8001f4e: 6c1b ldr r3, [r3, #64] @ 0x40 8001f50: 2b00 cmp r3, #0 8001f52: d003 beq.n 8001f5c { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8001f54: 687b ldr r3, [r7, #4] 8001f56: 6c1b ldr r3, [r3, #64] @ 0x40 8001f58: 6878 ldr r0, [r7, #4] 8001f5a: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) 8001f5c: 687b ldr r3, [r7, #4] 8001f5e: 6ddb ldr r3, [r3, #92] @ 0x5c 8001f60: 2220 movs r2, #32 8001f62: 409a lsls r2, r3 8001f64: 68fb ldr r3, [r7, #12] 8001f66: 4013 ands r3, r2 8001f68: 2b00 cmp r3, #0 8001f6a: f000 808f beq.w 800208c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) 8001f6e: 687b ldr r3, [r7, #4] 8001f70: 681b ldr r3, [r3, #0] 8001f72: 681b ldr r3, [r3, #0] 8001f74: f003 0310 and.w r3, r3, #16 8001f78: 2b00 cmp r3, #0 8001f7a: f000 8087 beq.w 800208c { /* Clear the transfer complete flag */ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; 8001f7e: 687b ldr r3, [r7, #4] 8001f80: 6ddb ldr r3, [r3, #92] @ 0x5c 8001f82: 2220 movs r2, #32 8001f84: 409a lsls r2, r3 8001f86: 693b ldr r3, [r7, #16] 8001f88: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 8001f8a: 687b ldr r3, [r7, #4] 8001f8c: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001f90: b2db uxtb r3, r3 8001f92: 2b05 cmp r3, #5 8001f94: d136 bne.n 8002004 { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8001f96: 687b ldr r3, [r7, #4] 8001f98: 681b ldr r3, [r3, #0] 8001f9a: 681a ldr r2, [r3, #0] 8001f9c: 687b ldr r3, [r7, #4] 8001f9e: 681b ldr r3, [r3, #0] 8001fa0: f022 0216 bic.w r2, r2, #22 8001fa4: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 8001fa6: 687b ldr r3, [r7, #4] 8001fa8: 681b ldr r3, [r3, #0] 8001faa: 695a ldr r2, [r3, #20] 8001fac: 687b ldr r3, [r7, #4] 8001fae: 681b ldr r3, [r3, #0] 8001fb0: f022 0280 bic.w r2, r2, #128 @ 0x80 8001fb4: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8001fb6: 687b ldr r3, [r7, #4] 8001fb8: 6c1b ldr r3, [r3, #64] @ 0x40 8001fba: 2b00 cmp r3, #0 8001fbc: d103 bne.n 8001fc6 8001fbe: 687b ldr r3, [r7, #4] 8001fc0: 6c9b ldr r3, [r3, #72] @ 0x48 8001fc2: 2b00 cmp r3, #0 8001fc4: d007 beq.n 8001fd6 { hdma->Instance->CR &= ~(DMA_IT_HT); 8001fc6: 687b ldr r3, [r7, #4] 8001fc8: 681b ldr r3, [r3, #0] 8001fca: 681a ldr r2, [r3, #0] 8001fcc: 687b ldr r3, [r7, #4] 8001fce: 681b ldr r3, [r3, #0] 8001fd0: f022 0208 bic.w r2, r2, #8 8001fd4: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001fd6: 687b ldr r3, [r7, #4] 8001fd8: 6ddb ldr r3, [r3, #92] @ 0x5c 8001fda: 223f movs r2, #63 @ 0x3f 8001fdc: 409a lsls r2, r3 8001fde: 693b ldr r3, [r7, #16] 8001fe0: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001fe2: 687b ldr r3, [r7, #4] 8001fe4: 2201 movs r2, #1 8001fe6: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001fea: 687b ldr r3, [r7, #4] 8001fec: 2200 movs r2, #0 8001fee: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 8001ff2: 687b ldr r3, [r7, #4] 8001ff4: 6d1b ldr r3, [r3, #80] @ 0x50 8001ff6: 2b00 cmp r3, #0 8001ff8: d07e beq.n 80020f8 { hdma->XferAbortCallback(hdma); 8001ffa: 687b ldr r3, [r7, #4] 8001ffc: 6d1b ldr r3, [r3, #80] @ 0x50 8001ffe: 6878 ldr r0, [r7, #4] 8002000: 4798 blx r3 } return; 8002002: e079 b.n 80020f8 } if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 8002004: 687b ldr r3, [r7, #4] 8002006: 681b ldr r3, [r3, #0] 8002008: 681b ldr r3, [r3, #0] 800200a: f403 2380 and.w r3, r3, #262144 @ 0x40000 800200e: 2b00 cmp r3, #0 8002010: d01d beq.n 800204e { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 8002012: 687b ldr r3, [r7, #4] 8002014: 681b ldr r3, [r3, #0] 8002016: 681b ldr r3, [r3, #0] 8002018: f403 2300 and.w r3, r3, #524288 @ 0x80000 800201c: 2b00 cmp r3, #0 800201e: d10d bne.n 800203c { if(hdma->XferM1CpltCallback != NULL) 8002020: 687b ldr r3, [r7, #4] 8002022: 6c5b ldr r3, [r3, #68] @ 0x44 8002024: 2b00 cmp r3, #0 8002026: d031 beq.n 800208c { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 8002028: 687b ldr r3, [r7, #4] 800202a: 6c5b ldr r3, [r3, #68] @ 0x44 800202c: 6878 ldr r0, [r7, #4] 800202e: 4798 blx r3 8002030: e02c b.n 800208c 8002032: bf00 nop 8002034: 20000090 .word 0x20000090 8002038: 1b4e81b5 .word 0x1b4e81b5 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800203c: 687b ldr r3, [r7, #4] 800203e: 6bdb ldr r3, [r3, #60] @ 0x3c 8002040: 2b00 cmp r3, #0 8002042: d023 beq.n 800208c { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8002044: 687b ldr r3, [r7, #4] 8002046: 6bdb ldr r3, [r3, #60] @ 0x3c 8002048: 6878 ldr r0, [r7, #4] 800204a: 4798 blx r3 800204c: e01e b.n 800208c } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 800204e: 687b ldr r3, [r7, #4] 8002050: 681b ldr r3, [r3, #0] 8002052: 681b ldr r3, [r3, #0] 8002054: f403 7380 and.w r3, r3, #256 @ 0x100 8002058: 2b00 cmp r3, #0 800205a: d10f bne.n 800207c { /* Disable the transfer complete interrupt */ hdma->Instance->CR &= ~(DMA_IT_TC); 800205c: 687b ldr r3, [r7, #4] 800205e: 681b ldr r3, [r3, #0] 8002060: 681a ldr r2, [r3, #0] 8002062: 687b ldr r3, [r7, #4] 8002064: 681b ldr r3, [r3, #0] 8002066: f022 0210 bic.w r2, r2, #16 800206a: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800206c: 687b ldr r3, [r7, #4] 800206e: 2201 movs r2, #1 8002070: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002074: 687b ldr r3, [r7, #4] 8002076: 2200 movs r2, #0 8002078: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800207c: 687b ldr r3, [r7, #4] 800207e: 6bdb ldr r3, [r3, #60] @ 0x3c 8002080: 2b00 cmp r3, #0 8002082: d003 beq.n 800208c { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8002084: 687b ldr r3, [r7, #4] 8002086: 6bdb ldr r3, [r3, #60] @ 0x3c 8002088: 6878 ldr r0, [r7, #4] 800208a: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 800208c: 687b ldr r3, [r7, #4] 800208e: 6d5b ldr r3, [r3, #84] @ 0x54 8002090: 2b00 cmp r3, #0 8002092: d032 beq.n 80020fa { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) 8002094: 687b ldr r3, [r7, #4] 8002096: 6d5b ldr r3, [r3, #84] @ 0x54 8002098: f003 0301 and.w r3, r3, #1 800209c: 2b00 cmp r3, #0 800209e: d022 beq.n 80020e6 { hdma->State = HAL_DMA_STATE_ABORT; 80020a0: 687b ldr r3, [r7, #4] 80020a2: 2205 movs r2, #5 80020a4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80020a8: 687b ldr r3, [r7, #4] 80020aa: 681b ldr r3, [r3, #0] 80020ac: 681a ldr r2, [r3, #0] 80020ae: 687b ldr r3, [r7, #4] 80020b0: 681b ldr r3, [r3, #0] 80020b2: f022 0201 bic.w r2, r2, #1 80020b6: 601a str r2, [r3, #0] do { if (++count > timeout) 80020b8: 68bb ldr r3, [r7, #8] 80020ba: 3301 adds r3, #1 80020bc: 60bb str r3, [r7, #8] 80020be: 697a ldr r2, [r7, #20] 80020c0: 429a cmp r2, r3 80020c2: d307 bcc.n 80020d4 { break; } } while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); 80020c4: 687b ldr r3, [r7, #4] 80020c6: 681b ldr r3, [r3, #0] 80020c8: 681b ldr r3, [r3, #0] 80020ca: f003 0301 and.w r3, r3, #1 80020ce: 2b00 cmp r3, #0 80020d0: d1f2 bne.n 80020b8 80020d2: e000 b.n 80020d6 break; 80020d4: bf00 nop /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80020d6: 687b ldr r3, [r7, #4] 80020d8: 2201 movs r2, #1 80020da: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80020de: 687b ldr r3, [r7, #4] 80020e0: 2200 movs r2, #0 80020e2: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 80020e6: 687b ldr r3, [r7, #4] 80020e8: 6cdb ldr r3, [r3, #76] @ 0x4c 80020ea: 2b00 cmp r3, #0 80020ec: d005 beq.n 80020fa { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 80020ee: 687b ldr r3, [r7, #4] 80020f0: 6cdb ldr r3, [r3, #76] @ 0x4c 80020f2: 6878 ldr r0, [r7, #4] 80020f4: 4798 blx r3 80020f6: e000 b.n 80020fa return; 80020f8: bf00 nop } } } 80020fa: 3718 adds r7, #24 80020fc: 46bd mov sp, r7 80020fe: bd80 pop {r7, pc} 08002100 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002100: b480 push {r7} 8002102: b085 sub sp, #20 8002104: af00 add r7, sp, #0 8002106: 60f8 str r0, [r7, #12] 8002108: 60b9 str r1, [r7, #8] 800210a: 607a str r2, [r7, #4] 800210c: 603b str r3, [r7, #0] /* Clear DBM bit */ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); 800210e: 68fb ldr r3, [r7, #12] 8002110: 681b ldr r3, [r3, #0] 8002112: 681a ldr r2, [r3, #0] 8002114: 68fb ldr r3, [r7, #12] 8002116: 681b ldr r3, [r3, #0] 8002118: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800211c: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; 800211e: 68fb ldr r3, [r7, #12] 8002120: 681b ldr r3, [r3, #0] 8002122: 683a ldr r2, [r7, #0] 8002124: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8002126: 68fb ldr r3, [r7, #12] 8002128: 689b ldr r3, [r3, #8] 800212a: 2b40 cmp r3, #64 @ 0x40 800212c: d108 bne.n 8002140 { /* Configure DMA Stream destination address */ hdma->Instance->PAR = DstAddress; 800212e: 68fb ldr r3, [r7, #12] 8002130: 681b ldr r3, [r3, #0] 8002132: 687a ldr r2, [r7, #4] 8002134: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; 8002136: 68fb ldr r3, [r7, #12] 8002138: 681b ldr r3, [r3, #0] 800213a: 68ba ldr r2, [r7, #8] 800213c: 60da str r2, [r3, #12] hdma->Instance->PAR = SrcAddress; /* Configure DMA Stream destination address */ hdma->Instance->M0AR = DstAddress; } } 800213e: e007 b.n 8002150 hdma->Instance->PAR = SrcAddress; 8002140: 68fb ldr r3, [r7, #12] 8002142: 681b ldr r3, [r3, #0] 8002144: 68ba ldr r2, [r7, #8] 8002146: 609a str r2, [r3, #8] hdma->Instance->M0AR = DstAddress; 8002148: 68fb ldr r3, [r7, #12] 800214a: 681b ldr r3, [r3, #0] 800214c: 687a ldr r2, [r7, #4] 800214e: 60da str r2, [r3, #12] } 8002150: bf00 nop 8002152: 3714 adds r7, #20 8002154: 46bd mov sp, r7 8002156: f85d 7b04 ldr.w r7, [sp], #4 800215a: 4770 bx lr 0800215c : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 800215c: b480 push {r7} 800215e: b085 sub sp, #20 8002160: af00 add r7, sp, #0 8002162: 6078 str r0, [r7, #4] uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; 8002164: 687b ldr r3, [r7, #4] 8002166: 681b ldr r3, [r3, #0] 8002168: b2db uxtb r3, r3 800216a: 3b10 subs r3, #16 800216c: 4a14 ldr r2, [pc, #80] @ (80021c0 ) 800216e: fba2 2303 umull r2, r3, r2, r3 8002172: 091b lsrs r3, r3, #4 8002174: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number]; 8002176: 4a13 ldr r2, [pc, #76] @ (80021c4 ) 8002178: 68fb ldr r3, [r7, #12] 800217a: 4413 add r3, r2 800217c: 781b ldrb r3, [r3, #0] 800217e: 461a mov r2, r3 8002180: 687b ldr r3, [r7, #4] 8002182: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 8002184: 68fb ldr r3, [r7, #12] 8002186: 2b03 cmp r3, #3 8002188: d909 bls.n 800219e { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); 800218a: 687b ldr r3, [r7, #4] 800218c: 681b ldr r3, [r3, #0] 800218e: f423 737f bic.w r3, r3, #1020 @ 0x3fc 8002192: f023 0303 bic.w r3, r3, #3 8002196: 1d1a adds r2, r3, #4 8002198: 687b ldr r3, [r7, #4] 800219a: 659a str r2, [r3, #88] @ 0x58 800219c: e007 b.n 80021ae } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); 800219e: 687b ldr r3, [r7, #4] 80021a0: 681b ldr r3, [r3, #0] 80021a2: f423 737f bic.w r3, r3, #1020 @ 0x3fc 80021a6: f023 0303 bic.w r3, r3, #3 80021aa: 687a ldr r2, [r7, #4] 80021ac: 6593 str r3, [r2, #88] @ 0x58 } return hdma->StreamBaseAddress; 80021ae: 687b ldr r3, [r7, #4] 80021b0: 6d9b ldr r3, [r3, #88] @ 0x58 } 80021b2: 4618 mov r0, r3 80021b4: 3714 adds r7, #20 80021b6: 46bd mov sp, r7 80021b8: f85d 7b04 ldr.w r7, [sp], #4 80021bc: 4770 bx lr 80021be: bf00 nop 80021c0: aaaaaaab .word 0xaaaaaaab 80021c4: 0800a4f8 .word 0x0800a4f8 080021c8 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 80021c8: b480 push {r7} 80021ca: b085 sub sp, #20 80021cc: af00 add r7, sp, #0 80021ce: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80021d0: 2300 movs r3, #0 80021d2: 73fb strb r3, [r7, #15] uint32_t tmp = hdma->Init.FIFOThreshold; 80021d4: 687b ldr r3, [r7, #4] 80021d6: 6a9b ldr r3, [r3, #40] @ 0x28 80021d8: 60bb str r3, [r7, #8] /* Memory Data size equal to Byte */ if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 80021da: 687b ldr r3, [r7, #4] 80021dc: 699b ldr r3, [r3, #24] 80021de: 2b00 cmp r3, #0 80021e0: d11f bne.n 8002222 { switch (tmp) 80021e2: 68bb ldr r3, [r7, #8] 80021e4: 2b03 cmp r3, #3 80021e6: d856 bhi.n 8002296 80021e8: a201 add r2, pc, #4 @ (adr r2, 80021f0 ) 80021ea: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80021ee: bf00 nop 80021f0: 08002201 .word 0x08002201 80021f4: 08002213 .word 0x08002213 80021f8: 08002201 .word 0x08002201 80021fc: 08002297 .word 0x08002297 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002200: 687b ldr r3, [r7, #4] 8002202: 6adb ldr r3, [r3, #44] @ 0x2c 8002204: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002208: 2b00 cmp r3, #0 800220a: d046 beq.n 800229a { status = HAL_ERROR; 800220c: 2301 movs r3, #1 800220e: 73fb strb r3, [r7, #15] } break; 8002210: e043 b.n 800229a case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8002212: 687b ldr r3, [r7, #4] 8002214: 6adb ldr r3, [r3, #44] @ 0x2c 8002216: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800221a: d140 bne.n 800229e { status = HAL_ERROR; 800221c: 2301 movs r3, #1 800221e: 73fb strb r3, [r7, #15] } break; 8002220: e03d b.n 800229e break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 8002222: 687b ldr r3, [r7, #4] 8002224: 699b ldr r3, [r3, #24] 8002226: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800222a: d121 bne.n 8002270 { switch (tmp) 800222c: 68bb ldr r3, [r7, #8] 800222e: 2b03 cmp r3, #3 8002230: d837 bhi.n 80022a2 8002232: a201 add r2, pc, #4 @ (adr r2, 8002238 ) 8002234: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002238: 08002249 .word 0x08002249 800223c: 0800224f .word 0x0800224f 8002240: 08002249 .word 0x08002249 8002244: 08002261 .word 0x08002261 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 8002248: 2301 movs r3, #1 800224a: 73fb strb r3, [r7, #15] break; 800224c: e030 b.n 80022b0 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800224e: 687b ldr r3, [r7, #4] 8002250: 6adb ldr r3, [r3, #44] @ 0x2c 8002252: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002256: 2b00 cmp r3, #0 8002258: d025 beq.n 80022a6 { status = HAL_ERROR; 800225a: 2301 movs r3, #1 800225c: 73fb strb r3, [r7, #15] } break; 800225e: e022 b.n 80022a6 case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8002260: 687b ldr r3, [r7, #4] 8002262: 6adb ldr r3, [r3, #44] @ 0x2c 8002264: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 8002268: d11f bne.n 80022aa { status = HAL_ERROR; 800226a: 2301 movs r3, #1 800226c: 73fb strb r3, [r7, #15] } break; 800226e: e01c b.n 80022aa } /* Memory Data size equal to Word */ else { switch (tmp) 8002270: 68bb ldr r3, [r7, #8] 8002272: 2b02 cmp r3, #2 8002274: d903 bls.n 800227e 8002276: 68bb ldr r3, [r7, #8] 8002278: 2b03 cmp r3, #3 800227a: d003 beq.n 8002284 { status = HAL_ERROR; } break; default: break; 800227c: e018 b.n 80022b0 status = HAL_ERROR; 800227e: 2301 movs r3, #1 8002280: 73fb strb r3, [r7, #15] break; 8002282: e015 b.n 80022b0 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002284: 687b ldr r3, [r7, #4] 8002286: 6adb ldr r3, [r3, #44] @ 0x2c 8002288: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800228c: 2b00 cmp r3, #0 800228e: d00e beq.n 80022ae status = HAL_ERROR; 8002290: 2301 movs r3, #1 8002292: 73fb strb r3, [r7, #15] break; 8002294: e00b b.n 80022ae break; 8002296: bf00 nop 8002298: e00a b.n 80022b0 break; 800229a: bf00 nop 800229c: e008 b.n 80022b0 break; 800229e: bf00 nop 80022a0: e006 b.n 80022b0 break; 80022a2: bf00 nop 80022a4: e004 b.n 80022b0 break; 80022a6: bf00 nop 80022a8: e002 b.n 80022b0 break; 80022aa: bf00 nop 80022ac: e000 b.n 80022b0 break; 80022ae: bf00 nop } } return status; 80022b0: 7bfb ldrb r3, [r7, #15] } 80022b2: 4618 mov r0, r3 80022b4: 3714 adds r7, #20 80022b6: 46bd mov sp, r7 80022b8: f85d 7b04 ldr.w r7, [sp], #4 80022bc: 4770 bx lr 80022be: bf00 nop 080022c0 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80022c0: b480 push {r7} 80022c2: b089 sub sp, #36 @ 0x24 80022c4: af00 add r7, sp, #0 80022c6: 6078 str r0, [r7, #4] 80022c8: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 80022ca: 2300 movs r3, #0 80022cc: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 80022ce: 2300 movs r3, #0 80022d0: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 80022d2: 2300 movs r3, #0 80022d4: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 80022d6: 2300 movs r3, #0 80022d8: 61fb str r3, [r7, #28] 80022da: e165 b.n 80025a8 { /* Get the IO position */ ioposition = 0x01U << position; 80022dc: 2201 movs r2, #1 80022de: 69fb ldr r3, [r7, #28] 80022e0: fa02 f303 lsl.w r3, r2, r3 80022e4: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80022e6: 683b ldr r3, [r7, #0] 80022e8: 681b ldr r3, [r3, #0] 80022ea: 697a ldr r2, [r7, #20] 80022ec: 4013 ands r3, r2 80022ee: 613b str r3, [r7, #16] if(iocurrent == ioposition) 80022f0: 693a ldr r2, [r7, #16] 80022f2: 697b ldr r3, [r7, #20] 80022f4: 429a cmp r2, r3 80022f6: f040 8154 bne.w 80025a2 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 80022fa: 683b ldr r3, [r7, #0] 80022fc: 685b ldr r3, [r3, #4] 80022fe: f003 0303 and.w r3, r3, #3 8002302: 2b01 cmp r3, #1 8002304: d005 beq.n 8002312 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002306: 683b ldr r3, [r7, #0] 8002308: 685b ldr r3, [r3, #4] 800230a: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 800230e: 2b02 cmp r3, #2 8002310: d130 bne.n 8002374 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8002312: 687b ldr r3, [r7, #4] 8002314: 689b ldr r3, [r3, #8] 8002316: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8002318: 69fb ldr r3, [r7, #28] 800231a: 005b lsls r3, r3, #1 800231c: 2203 movs r2, #3 800231e: fa02 f303 lsl.w r3, r2, r3 8002322: 43db mvns r3, r3 8002324: 69ba ldr r2, [r7, #24] 8002326: 4013 ands r3, r2 8002328: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800232a: 683b ldr r3, [r7, #0] 800232c: 68da ldr r2, [r3, #12] 800232e: 69fb ldr r3, [r7, #28] 8002330: 005b lsls r3, r3, #1 8002332: fa02 f303 lsl.w r3, r2, r3 8002336: 69ba ldr r2, [r7, #24] 8002338: 4313 orrs r3, r2 800233a: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800233c: 687b ldr r3, [r7, #4] 800233e: 69ba ldr r2, [r7, #24] 8002340: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8002342: 687b ldr r3, [r7, #4] 8002344: 685b ldr r3, [r3, #4] 8002346: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8002348: 2201 movs r2, #1 800234a: 69fb ldr r3, [r7, #28] 800234c: fa02 f303 lsl.w r3, r2, r3 8002350: 43db mvns r3, r3 8002352: 69ba ldr r2, [r7, #24] 8002354: 4013 ands r3, r2 8002356: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8002358: 683b ldr r3, [r7, #0] 800235a: 685b ldr r3, [r3, #4] 800235c: 091b lsrs r3, r3, #4 800235e: f003 0201 and.w r2, r3, #1 8002362: 69fb ldr r3, [r7, #28] 8002364: fa02 f303 lsl.w r3, r2, r3 8002368: 69ba ldr r2, [r7, #24] 800236a: 4313 orrs r3, r2 800236c: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 800236e: 687b ldr r3, [r7, #4] 8002370: 69ba ldr r2, [r7, #24] 8002372: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8002374: 683b ldr r3, [r7, #0] 8002376: 685b ldr r3, [r3, #4] 8002378: f003 0303 and.w r3, r3, #3 800237c: 2b03 cmp r3, #3 800237e: d017 beq.n 80023b0 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8002380: 687b ldr r3, [r7, #4] 8002382: 68db ldr r3, [r3, #12] 8002384: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8002386: 69fb ldr r3, [r7, #28] 8002388: 005b lsls r3, r3, #1 800238a: 2203 movs r2, #3 800238c: fa02 f303 lsl.w r3, r2, r3 8002390: 43db mvns r3, r3 8002392: 69ba ldr r2, [r7, #24] 8002394: 4013 ands r3, r2 8002396: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8002398: 683b ldr r3, [r7, #0] 800239a: 689a ldr r2, [r3, #8] 800239c: 69fb ldr r3, [r7, #28] 800239e: 005b lsls r3, r3, #1 80023a0: fa02 f303 lsl.w r3, r2, r3 80023a4: 69ba ldr r2, [r7, #24] 80023a6: 4313 orrs r3, r2 80023a8: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 80023aa: 687b ldr r3, [r7, #4] 80023ac: 69ba ldr r2, [r7, #24] 80023ae: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80023b0: 683b ldr r3, [r7, #0] 80023b2: 685b ldr r3, [r3, #4] 80023b4: f003 0303 and.w r3, r3, #3 80023b8: 2b02 cmp r3, #2 80023ba: d123 bne.n 8002404 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 80023bc: 69fb ldr r3, [r7, #28] 80023be: 08da lsrs r2, r3, #3 80023c0: 687b ldr r3, [r7, #4] 80023c2: 3208 adds r2, #8 80023c4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80023c8: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 80023ca: 69fb ldr r3, [r7, #28] 80023cc: f003 0307 and.w r3, r3, #7 80023d0: 009b lsls r3, r3, #2 80023d2: 220f movs r2, #15 80023d4: fa02 f303 lsl.w r3, r2, r3 80023d8: 43db mvns r3, r3 80023da: 69ba ldr r2, [r7, #24] 80023dc: 4013 ands r3, r2 80023de: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 80023e0: 683b ldr r3, [r7, #0] 80023e2: 691a ldr r2, [r3, #16] 80023e4: 69fb ldr r3, [r7, #28] 80023e6: f003 0307 and.w r3, r3, #7 80023ea: 009b lsls r3, r3, #2 80023ec: fa02 f303 lsl.w r3, r2, r3 80023f0: 69ba ldr r2, [r7, #24] 80023f2: 4313 orrs r3, r2 80023f4: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 80023f6: 69fb ldr r3, [r7, #28] 80023f8: 08da lsrs r2, r3, #3 80023fa: 687b ldr r3, [r7, #4] 80023fc: 3208 adds r2, #8 80023fe: 69b9 ldr r1, [r7, #24] 8002400: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8002404: 687b ldr r3, [r7, #4] 8002406: 681b ldr r3, [r3, #0] 8002408: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 800240a: 69fb ldr r3, [r7, #28] 800240c: 005b lsls r3, r3, #1 800240e: 2203 movs r2, #3 8002410: fa02 f303 lsl.w r3, r2, r3 8002414: 43db mvns r3, r3 8002416: 69ba ldr r2, [r7, #24] 8002418: 4013 ands r3, r2 800241a: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800241c: 683b ldr r3, [r7, #0] 800241e: 685b ldr r3, [r3, #4] 8002420: f003 0203 and.w r2, r3, #3 8002424: 69fb ldr r3, [r7, #28] 8002426: 005b lsls r3, r3, #1 8002428: fa02 f303 lsl.w r3, r2, r3 800242c: 69ba ldr r2, [r7, #24] 800242e: 4313 orrs r3, r2 8002430: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8002432: 687b ldr r3, [r7, #4] 8002434: 69ba ldr r2, [r7, #24] 8002436: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8002438: 683b ldr r3, [r7, #0] 800243a: 685b ldr r3, [r3, #4] 800243c: f403 3340 and.w r3, r3, #196608 @ 0x30000 8002440: 2b00 cmp r3, #0 8002442: f000 80ae beq.w 80025a2 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002446: 2300 movs r3, #0 8002448: 60fb str r3, [r7, #12] 800244a: 4b5d ldr r3, [pc, #372] @ (80025c0 ) 800244c: 6c5b ldr r3, [r3, #68] @ 0x44 800244e: 4a5c ldr r2, [pc, #368] @ (80025c0 ) 8002450: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002454: 6453 str r3, [r2, #68] @ 0x44 8002456: 4b5a ldr r3, [pc, #360] @ (80025c0 ) 8002458: 6c5b ldr r3, [r3, #68] @ 0x44 800245a: f403 4380 and.w r3, r3, #16384 @ 0x4000 800245e: 60fb str r3, [r7, #12] 8002460: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8002462: 4a58 ldr r2, [pc, #352] @ (80025c4 ) 8002464: 69fb ldr r3, [r7, #28] 8002466: 089b lsrs r3, r3, #2 8002468: 3302 adds r3, #2 800246a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800246e: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8002470: 69fb ldr r3, [r7, #28] 8002472: f003 0303 and.w r3, r3, #3 8002476: 009b lsls r3, r3, #2 8002478: 220f movs r2, #15 800247a: fa02 f303 lsl.w r3, r2, r3 800247e: 43db mvns r3, r3 8002480: 69ba ldr r2, [r7, #24] 8002482: 4013 ands r3, r2 8002484: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8002486: 687b ldr r3, [r7, #4] 8002488: 4a4f ldr r2, [pc, #316] @ (80025c8 ) 800248a: 4293 cmp r3, r2 800248c: d025 beq.n 80024da 800248e: 687b ldr r3, [r7, #4] 8002490: 4a4e ldr r2, [pc, #312] @ (80025cc ) 8002492: 4293 cmp r3, r2 8002494: d01f beq.n 80024d6 8002496: 687b ldr r3, [r7, #4] 8002498: 4a4d ldr r2, [pc, #308] @ (80025d0 ) 800249a: 4293 cmp r3, r2 800249c: d019 beq.n 80024d2 800249e: 687b ldr r3, [r7, #4] 80024a0: 4a4c ldr r2, [pc, #304] @ (80025d4 ) 80024a2: 4293 cmp r3, r2 80024a4: d013 beq.n 80024ce 80024a6: 687b ldr r3, [r7, #4] 80024a8: 4a4b ldr r2, [pc, #300] @ (80025d8 ) 80024aa: 4293 cmp r3, r2 80024ac: d00d beq.n 80024ca 80024ae: 687b ldr r3, [r7, #4] 80024b0: 4a4a ldr r2, [pc, #296] @ (80025dc ) 80024b2: 4293 cmp r3, r2 80024b4: d007 beq.n 80024c6 80024b6: 687b ldr r3, [r7, #4] 80024b8: 4a49 ldr r2, [pc, #292] @ (80025e0 ) 80024ba: 4293 cmp r3, r2 80024bc: d101 bne.n 80024c2 80024be: 2306 movs r3, #6 80024c0: e00c b.n 80024dc 80024c2: 2307 movs r3, #7 80024c4: e00a b.n 80024dc 80024c6: 2305 movs r3, #5 80024c8: e008 b.n 80024dc 80024ca: 2304 movs r3, #4 80024cc: e006 b.n 80024dc 80024ce: 2303 movs r3, #3 80024d0: e004 b.n 80024dc 80024d2: 2302 movs r3, #2 80024d4: e002 b.n 80024dc 80024d6: 2301 movs r3, #1 80024d8: e000 b.n 80024dc 80024da: 2300 movs r3, #0 80024dc: 69fa ldr r2, [r7, #28] 80024de: f002 0203 and.w r2, r2, #3 80024e2: 0092 lsls r2, r2, #2 80024e4: 4093 lsls r3, r2 80024e6: 69ba ldr r2, [r7, #24] 80024e8: 4313 orrs r3, r2 80024ea: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 80024ec: 4935 ldr r1, [pc, #212] @ (80025c4 ) 80024ee: 69fb ldr r3, [r7, #28] 80024f0: 089b lsrs r3, r3, #2 80024f2: 3302 adds r3, #2 80024f4: 69ba ldr r2, [r7, #24] 80024f6: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 80024fa: 4b3a ldr r3, [pc, #232] @ (80025e4 ) 80024fc: 689b ldr r3, [r3, #8] 80024fe: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002500: 693b ldr r3, [r7, #16] 8002502: 43db mvns r3, r3 8002504: 69ba ldr r2, [r7, #24] 8002506: 4013 ands r3, r2 8002508: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800250a: 683b ldr r3, [r7, #0] 800250c: 685b ldr r3, [r3, #4] 800250e: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8002512: 2b00 cmp r3, #0 8002514: d003 beq.n 800251e { temp |= iocurrent; 8002516: 69ba ldr r2, [r7, #24] 8002518: 693b ldr r3, [r7, #16] 800251a: 4313 orrs r3, r2 800251c: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 800251e: 4a31 ldr r2, [pc, #196] @ (80025e4 ) 8002520: 69bb ldr r3, [r7, #24] 8002522: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8002524: 4b2f ldr r3, [pc, #188] @ (80025e4 ) 8002526: 68db ldr r3, [r3, #12] 8002528: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 800252a: 693b ldr r3, [r7, #16] 800252c: 43db mvns r3, r3 800252e: 69ba ldr r2, [r7, #24] 8002530: 4013 ands r3, r2 8002532: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8002534: 683b ldr r3, [r7, #0] 8002536: 685b ldr r3, [r3, #4] 8002538: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800253c: 2b00 cmp r3, #0 800253e: d003 beq.n 8002548 { temp |= iocurrent; 8002540: 69ba ldr r2, [r7, #24] 8002542: 693b ldr r3, [r7, #16] 8002544: 4313 orrs r3, r2 8002546: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8002548: 4a26 ldr r2, [pc, #152] @ (80025e4 ) 800254a: 69bb ldr r3, [r7, #24] 800254c: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 800254e: 4b25 ldr r3, [pc, #148] @ (80025e4 ) 8002550: 685b ldr r3, [r3, #4] 8002552: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002554: 693b ldr r3, [r7, #16] 8002556: 43db mvns r3, r3 8002558: 69ba ldr r2, [r7, #24] 800255a: 4013 ands r3, r2 800255c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800255e: 683b ldr r3, [r7, #0] 8002560: 685b ldr r3, [r3, #4] 8002562: f403 3300 and.w r3, r3, #131072 @ 0x20000 8002566: 2b00 cmp r3, #0 8002568: d003 beq.n 8002572 { temp |= iocurrent; 800256a: 69ba ldr r2, [r7, #24] 800256c: 693b ldr r3, [r7, #16] 800256e: 4313 orrs r3, r2 8002570: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 8002572: 4a1c ldr r2, [pc, #112] @ (80025e4 ) 8002574: 69bb ldr r3, [r7, #24] 8002576: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8002578: 4b1a ldr r3, [pc, #104] @ (80025e4 ) 800257a: 681b ldr r3, [r3, #0] 800257c: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 800257e: 693b ldr r3, [r7, #16] 8002580: 43db mvns r3, r3 8002582: 69ba ldr r2, [r7, #24] 8002584: 4013 ands r3, r2 8002586: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8002588: 683b ldr r3, [r7, #0] 800258a: 685b ldr r3, [r3, #4] 800258c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8002590: 2b00 cmp r3, #0 8002592: d003 beq.n 800259c { temp |= iocurrent; 8002594: 69ba ldr r2, [r7, #24] 8002596: 693b ldr r3, [r7, #16] 8002598: 4313 orrs r3, r2 800259a: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 800259c: 4a11 ldr r2, [pc, #68] @ (80025e4 ) 800259e: 69bb ldr r3, [r7, #24] 80025a0: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 80025a2: 69fb ldr r3, [r7, #28] 80025a4: 3301 adds r3, #1 80025a6: 61fb str r3, [r7, #28] 80025a8: 69fb ldr r3, [r7, #28] 80025aa: 2b0f cmp r3, #15 80025ac: f67f ae96 bls.w 80022dc } } } } 80025b0: bf00 nop 80025b2: bf00 nop 80025b4: 3724 adds r7, #36 @ 0x24 80025b6: 46bd mov sp, r7 80025b8: f85d 7b04 ldr.w r7, [sp], #4 80025bc: 4770 bx lr 80025be: bf00 nop 80025c0: 40023800 .word 0x40023800 80025c4: 40013800 .word 0x40013800 80025c8: 40020000 .word 0x40020000 80025cc: 40020400 .word 0x40020400 80025d0: 40020800 .word 0x40020800 80025d4: 40020c00 .word 0x40020c00 80025d8: 40021000 .word 0x40021000 80025dc: 40021400 .word 0x40021400 80025e0: 40021800 .word 0x40021800 80025e4: 40013c00 .word 0x40013c00 080025e8 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 80025e8: b480 push {r7} 80025ea: b085 sub sp, #20 80025ec: af00 add r7, sp, #0 80025ee: 6078 str r0, [r7, #4] 80025f0: 460b mov r3, r1 80025f2: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 80025f4: 687b ldr r3, [r7, #4] 80025f6: 691a ldr r2, [r3, #16] 80025f8: 887b ldrh r3, [r7, #2] 80025fa: 4013 ands r3, r2 80025fc: 2b00 cmp r3, #0 80025fe: d002 beq.n 8002606 { bitstatus = GPIO_PIN_SET; 8002600: 2301 movs r3, #1 8002602: 73fb strb r3, [r7, #15] 8002604: e001 b.n 800260a } else { bitstatus = GPIO_PIN_RESET; 8002606: 2300 movs r3, #0 8002608: 73fb strb r3, [r7, #15] } return bitstatus; 800260a: 7bfb ldrb r3, [r7, #15] } 800260c: 4618 mov r0, r3 800260e: 3714 adds r7, #20 8002610: 46bd mov sp, r7 8002612: f85d 7b04 ldr.w r7, [sp], #4 8002616: 4770 bx lr 08002618 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8002618: b480 push {r7} 800261a: b083 sub sp, #12 800261c: af00 add r7, sp, #0 800261e: 6078 str r0, [r7, #4] 8002620: 460b mov r3, r1 8002622: 807b strh r3, [r7, #2] 8002624: 4613 mov r3, r2 8002626: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8002628: 787b ldrb r3, [r7, #1] 800262a: 2b00 cmp r3, #0 800262c: d003 beq.n 8002636 { GPIOx->BSRR = GPIO_Pin; 800262e: 887a ldrh r2, [r7, #2] 8002630: 687b ldr r3, [r7, #4] 8002632: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8002634: e003 b.n 800263e GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8002636: 887b ldrh r3, [r7, #2] 8002638: 041a lsls r2, r3, #16 800263a: 687b ldr r3, [r7, #4] 800263c: 619a str r2, [r3, #24] } 800263e: bf00 nop 8002640: 370c adds r7, #12 8002642: 46bd mov sp, r7 8002644: f85d 7b04 ldr.w r7, [sp], #4 8002648: 4770 bx lr ... 0800264c : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 800264c: b580 push {r7, lr} 800264e: b084 sub sp, #16 8002650: af00 add r7, sp, #0 8002652: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8002654: 687b ldr r3, [r7, #4] 8002656: 2b00 cmp r3, #0 8002658: d101 bne.n 800265e { return HAL_ERROR; 800265a: 2301 movs r3, #1 800265c: e12b b.n 80028b6 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 800265e: 687b ldr r3, [r7, #4] 8002660: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8002664: b2db uxtb r3, r3 8002666: 2b00 cmp r3, #0 8002668: d106 bne.n 8002678 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 800266a: 687b ldr r3, [r7, #4] 800266c: 2200 movs r2, #0 800266e: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8002672: 6878 ldr r0, [r7, #4] 8002674: f7fe f890 bl 8000798 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8002678: 687b ldr r3, [r7, #4] 800267a: 2224 movs r2, #36 @ 0x24 800267c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8002680: 687b ldr r3, [r7, #4] 8002682: 681b ldr r3, [r3, #0] 8002684: 681a ldr r2, [r3, #0] 8002686: 687b ldr r3, [r7, #4] 8002688: 681b ldr r3, [r3, #0] 800268a: f022 0201 bic.w r2, r2, #1 800268e: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8002690: 687b ldr r3, [r7, #4] 8002692: 681b ldr r3, [r3, #0] 8002694: 681a ldr r2, [r3, #0] 8002696: 687b ldr r3, [r7, #4] 8002698: 681b ldr r3, [r3, #0] 800269a: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800269e: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 80026a0: 687b ldr r3, [r7, #4] 80026a2: 681b ldr r3, [r3, #0] 80026a4: 681a ldr r2, [r3, #0] 80026a6: 687b ldr r3, [r7, #4] 80026a8: 681b ldr r3, [r3, #0] 80026aa: f422 4200 bic.w r2, r2, #32768 @ 0x8000 80026ae: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 80026b0: f001 fc88 bl 8003fc4 80026b4: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 80026b6: 687b ldr r3, [r7, #4] 80026b8: 685b ldr r3, [r3, #4] 80026ba: 4a81 ldr r2, [pc, #516] @ (80028c0 ) 80026bc: 4293 cmp r3, r2 80026be: d807 bhi.n 80026d0 80026c0: 68fb ldr r3, [r7, #12] 80026c2: 4a80 ldr r2, [pc, #512] @ (80028c4 ) 80026c4: 4293 cmp r3, r2 80026c6: bf94 ite ls 80026c8: 2301 movls r3, #1 80026ca: 2300 movhi r3, #0 80026cc: b2db uxtb r3, r3 80026ce: e006 b.n 80026de 80026d0: 68fb ldr r3, [r7, #12] 80026d2: 4a7d ldr r2, [pc, #500] @ (80028c8 ) 80026d4: 4293 cmp r3, r2 80026d6: bf94 ite ls 80026d8: 2301 movls r3, #1 80026da: 2300 movhi r3, #0 80026dc: b2db uxtb r3, r3 80026de: 2b00 cmp r3, #0 80026e0: d001 beq.n 80026e6 { return HAL_ERROR; 80026e2: 2301 movs r3, #1 80026e4: e0e7 b.n 80028b6 } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 80026e6: 68fb ldr r3, [r7, #12] 80026e8: 4a78 ldr r2, [pc, #480] @ (80028cc ) 80026ea: fba2 2303 umull r2, r3, r2, r3 80026ee: 0c9b lsrs r3, r3, #18 80026f0: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 80026f2: 687b ldr r3, [r7, #4] 80026f4: 681b ldr r3, [r3, #0] 80026f6: 685b ldr r3, [r3, #4] 80026f8: f023 013f bic.w r1, r3, #63 @ 0x3f 80026fc: 687b ldr r3, [r7, #4] 80026fe: 681b ldr r3, [r3, #0] 8002700: 68ba ldr r2, [r7, #8] 8002702: 430a orrs r2, r1 8002704: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 8002706: 687b ldr r3, [r7, #4] 8002708: 681b ldr r3, [r3, #0] 800270a: 6a1b ldr r3, [r3, #32] 800270c: f023 013f bic.w r1, r3, #63 @ 0x3f 8002710: 687b ldr r3, [r7, #4] 8002712: 685b ldr r3, [r3, #4] 8002714: 4a6a ldr r2, [pc, #424] @ (80028c0 ) 8002716: 4293 cmp r3, r2 8002718: d802 bhi.n 8002720 800271a: 68bb ldr r3, [r7, #8] 800271c: 3301 adds r3, #1 800271e: e009 b.n 8002734 8002720: 68bb ldr r3, [r7, #8] 8002722: f44f 7296 mov.w r2, #300 @ 0x12c 8002726: fb02 f303 mul.w r3, r2, r3 800272a: 4a69 ldr r2, [pc, #420] @ (80028d0 ) 800272c: fba2 2303 umull r2, r3, r2, r3 8002730: 099b lsrs r3, r3, #6 8002732: 3301 adds r3, #1 8002734: 687a ldr r2, [r7, #4] 8002736: 6812 ldr r2, [r2, #0] 8002738: 430b orrs r3, r1 800273a: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 800273c: 687b ldr r3, [r7, #4] 800273e: 681b ldr r3, [r3, #0] 8002740: 69db ldr r3, [r3, #28] 8002742: f423 424f bic.w r2, r3, #52992 @ 0xcf00 8002746: f022 02ff bic.w r2, r2, #255 @ 0xff 800274a: 687b ldr r3, [r7, #4] 800274c: 685b ldr r3, [r3, #4] 800274e: 495c ldr r1, [pc, #368] @ (80028c0 ) 8002750: 428b cmp r3, r1 8002752: d819 bhi.n 8002788 8002754: 68fb ldr r3, [r7, #12] 8002756: 1e59 subs r1, r3, #1 8002758: 687b ldr r3, [r7, #4] 800275a: 685b ldr r3, [r3, #4] 800275c: 005b lsls r3, r3, #1 800275e: fbb1 f3f3 udiv r3, r1, r3 8002762: 1c59 adds r1, r3, #1 8002764: f640 73fc movw r3, #4092 @ 0xffc 8002768: 400b ands r3, r1 800276a: 2b00 cmp r3, #0 800276c: d00a beq.n 8002784 800276e: 68fb ldr r3, [r7, #12] 8002770: 1e59 subs r1, r3, #1 8002772: 687b ldr r3, [r7, #4] 8002774: 685b ldr r3, [r3, #4] 8002776: 005b lsls r3, r3, #1 8002778: fbb1 f3f3 udiv r3, r1, r3 800277c: 3301 adds r3, #1 800277e: f3c3 030b ubfx r3, r3, #0, #12 8002782: e051 b.n 8002828 8002784: 2304 movs r3, #4 8002786: e04f b.n 8002828 8002788: 687b ldr r3, [r7, #4] 800278a: 689b ldr r3, [r3, #8] 800278c: 2b00 cmp r3, #0 800278e: d111 bne.n 80027b4 8002790: 68fb ldr r3, [r7, #12] 8002792: 1e58 subs r0, r3, #1 8002794: 687b ldr r3, [r7, #4] 8002796: 6859 ldr r1, [r3, #4] 8002798: 460b mov r3, r1 800279a: 005b lsls r3, r3, #1 800279c: 440b add r3, r1 800279e: fbb0 f3f3 udiv r3, r0, r3 80027a2: 3301 adds r3, #1 80027a4: f3c3 030b ubfx r3, r3, #0, #12 80027a8: 2b00 cmp r3, #0 80027aa: bf0c ite eq 80027ac: 2301 moveq r3, #1 80027ae: 2300 movne r3, #0 80027b0: b2db uxtb r3, r3 80027b2: e012 b.n 80027da 80027b4: 68fb ldr r3, [r7, #12] 80027b6: 1e58 subs r0, r3, #1 80027b8: 687b ldr r3, [r7, #4] 80027ba: 6859 ldr r1, [r3, #4] 80027bc: 460b mov r3, r1 80027be: 009b lsls r3, r3, #2 80027c0: 440b add r3, r1 80027c2: 0099 lsls r1, r3, #2 80027c4: 440b add r3, r1 80027c6: fbb0 f3f3 udiv r3, r0, r3 80027ca: 3301 adds r3, #1 80027cc: f3c3 030b ubfx r3, r3, #0, #12 80027d0: 2b00 cmp r3, #0 80027d2: bf0c ite eq 80027d4: 2301 moveq r3, #1 80027d6: 2300 movne r3, #0 80027d8: b2db uxtb r3, r3 80027da: 2b00 cmp r3, #0 80027dc: d001 beq.n 80027e2 80027de: 2301 movs r3, #1 80027e0: e022 b.n 8002828 80027e2: 687b ldr r3, [r7, #4] 80027e4: 689b ldr r3, [r3, #8] 80027e6: 2b00 cmp r3, #0 80027e8: d10e bne.n 8002808 80027ea: 68fb ldr r3, [r7, #12] 80027ec: 1e58 subs r0, r3, #1 80027ee: 687b ldr r3, [r7, #4] 80027f0: 6859 ldr r1, [r3, #4] 80027f2: 460b mov r3, r1 80027f4: 005b lsls r3, r3, #1 80027f6: 440b add r3, r1 80027f8: fbb0 f3f3 udiv r3, r0, r3 80027fc: 3301 adds r3, #1 80027fe: f3c3 030b ubfx r3, r3, #0, #12 8002802: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8002806: e00f b.n 8002828 8002808: 68fb ldr r3, [r7, #12] 800280a: 1e58 subs r0, r3, #1 800280c: 687b ldr r3, [r7, #4] 800280e: 6859 ldr r1, [r3, #4] 8002810: 460b mov r3, r1 8002812: 009b lsls r3, r3, #2 8002814: 440b add r3, r1 8002816: 0099 lsls r1, r3, #2 8002818: 440b add r3, r1 800281a: fbb0 f3f3 udiv r3, r0, r3 800281e: 3301 adds r3, #1 8002820: f3c3 030b ubfx r3, r3, #0, #12 8002824: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8002828: 6879 ldr r1, [r7, #4] 800282a: 6809 ldr r1, [r1, #0] 800282c: 4313 orrs r3, r2 800282e: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8002830: 687b ldr r3, [r7, #4] 8002832: 681b ldr r3, [r3, #0] 8002834: 681b ldr r3, [r3, #0] 8002836: f023 01c0 bic.w r1, r3, #192 @ 0xc0 800283a: 687b ldr r3, [r7, #4] 800283c: 69da ldr r2, [r3, #28] 800283e: 687b ldr r3, [r7, #4] 8002840: 6a1b ldr r3, [r3, #32] 8002842: 431a orrs r2, r3 8002844: 687b ldr r3, [r7, #4] 8002846: 681b ldr r3, [r3, #0] 8002848: 430a orrs r2, r1 800284a: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 800284c: 687b ldr r3, [r7, #4] 800284e: 681b ldr r3, [r3, #0] 8002850: 689b ldr r3, [r3, #8] 8002852: f423 4303 bic.w r3, r3, #33536 @ 0x8300 8002856: f023 03ff bic.w r3, r3, #255 @ 0xff 800285a: 687a ldr r2, [r7, #4] 800285c: 6911 ldr r1, [r2, #16] 800285e: 687a ldr r2, [r7, #4] 8002860: 68d2 ldr r2, [r2, #12] 8002862: 4311 orrs r1, r2 8002864: 687a ldr r2, [r7, #4] 8002866: 6812 ldr r2, [r2, #0] 8002868: 430b orrs r3, r1 800286a: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 800286c: 687b ldr r3, [r7, #4] 800286e: 681b ldr r3, [r3, #0] 8002870: 68db ldr r3, [r3, #12] 8002872: f023 01ff bic.w r1, r3, #255 @ 0xff 8002876: 687b ldr r3, [r7, #4] 8002878: 695a ldr r2, [r3, #20] 800287a: 687b ldr r3, [r7, #4] 800287c: 699b ldr r3, [r3, #24] 800287e: 431a orrs r2, r3 8002880: 687b ldr r3, [r7, #4] 8002882: 681b ldr r3, [r3, #0] 8002884: 430a orrs r2, r1 8002886: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002888: 687b ldr r3, [r7, #4] 800288a: 681b ldr r3, [r3, #0] 800288c: 681a ldr r2, [r3, #0] 800288e: 687b ldr r3, [r7, #4] 8002890: 681b ldr r3, [r3, #0] 8002892: f042 0201 orr.w r2, r2, #1 8002896: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002898: 687b ldr r3, [r7, #4] 800289a: 2200 movs r2, #0 800289c: 641a str r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_READY; 800289e: 687b ldr r3, [r7, #4] 80028a0: 2220 movs r2, #32 80028a2: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->PreviousState = I2C_STATE_NONE; 80028a6: 687b ldr r3, [r7, #4] 80028a8: 2200 movs r2, #0 80028aa: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 80028ac: 687b ldr r3, [r7, #4] 80028ae: 2200 movs r2, #0 80028b0: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 80028b4: 2300 movs r3, #0 } 80028b6: 4618 mov r0, r3 80028b8: 3710 adds r7, #16 80028ba: 46bd mov sp, r7 80028bc: bd80 pop {r7, pc} 80028be: bf00 nop 80028c0: 000186a0 .word 0x000186a0 80028c4: 001e847f .word 0x001e847f 80028c8: 003d08ff .word 0x003d08ff 80028cc: 431bde83 .word 0x431bde83 80028d0: 10624dd3 .word 0x10624dd3 080028d4 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 80028d4: b580 push {r7, lr} 80028d6: b086 sub sp, #24 80028d8: af02 add r7, sp, #8 80028da: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx; #endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 80028dc: 687b ldr r3, [r7, #4] 80028de: 2b00 cmp r3, #0 80028e0: d101 bne.n 80028e6 { return HAL_ERROR; 80028e2: 2301 movs r3, #1 80028e4: e108 b.n 8002af8 /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); #if defined (USB_OTG_FS) USBx = hpcd->Instance; 80028e6: 687b ldr r3, [r7, #4] 80028e8: 681b ldr r3, [r3, #0] 80028ea: 60bb str r3, [r7, #8] #endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) 80028ec: 687b ldr r3, [r7, #4] 80028ee: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495 80028f2: b2db uxtb r3, r3 80028f4: 2b00 cmp r3, #0 80028f6: d106 bne.n 8002906 { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 80028f8: 687b ldr r3, [r7, #4] 80028fa: 2200 movs r2, #0 80028fc: f883 2494 strb.w r2, [r3, #1172] @ 0x494 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8002900: 6878 ldr r0, [r7, #4] 8002902: f007 fa31 bl 8009d68 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8002906: 687b ldr r3, [r7, #4] 8002908: 2203 movs r2, #3 800290a: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ if (USBx == USB_OTG_FS) 800290e: 68bb ldr r3, [r7, #8] 8002910: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002914: d102 bne.n 800291c { hpcd->Init.dma_enable = 0U; 8002916: 687b ldr r3, [r7, #4] 8002918: 2200 movs r2, #0 800291a: 719a strb r2, [r3, #6] } #endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 800291c: 687b ldr r3, [r7, #4] 800291e: 681b ldr r3, [r3, #0] 8002920: 4618 mov r0, r3 8002922: f004 f926 bl 8006b72 /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002926: 687b ldr r3, [r7, #4] 8002928: 6818 ldr r0, [r3, #0] 800292a: 687b ldr r3, [r7, #4] 800292c: 7c1a ldrb r2, [r3, #16] 800292e: f88d 2000 strb.w r2, [sp] 8002932: 3304 adds r3, #4 8002934: cb0e ldmia r3, {r1, r2, r3} 8002936: f004 f805 bl 8006944 800293a: 4603 mov r3, r0 800293c: 2b00 cmp r3, #0 800293e: d005 beq.n 800294c { hpcd->State = HAL_PCD_STATE_ERROR; 8002940: 687b ldr r3, [r7, #4] 8002942: 2202 movs r2, #2 8002944: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002948: 2301 movs r3, #1 800294a: e0d5 b.n 8002af8 } /* Force Device Mode */ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) 800294c: 687b ldr r3, [r7, #4] 800294e: 681b ldr r3, [r3, #0] 8002950: 2100 movs r1, #0 8002952: 4618 mov r0, r3 8002954: f004 f91e bl 8006b94 8002958: 4603 mov r3, r0 800295a: 2b00 cmp r3, #0 800295c: d005 beq.n 800296a { hpcd->State = HAL_PCD_STATE_ERROR; 800295e: 687b ldr r3, [r7, #4] 8002960: 2202 movs r2, #2 8002962: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002966: 2301 movs r3, #1 8002968: e0c6 b.n 8002af8 } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800296a: 2300 movs r3, #0 800296c: 73fb strb r3, [r7, #15] 800296e: e04a b.n 8002a06 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8002970: 7bfa ldrb r2, [r7, #15] 8002972: 6879 ldr r1, [r7, #4] 8002974: 4613 mov r3, r2 8002976: 00db lsls r3, r3, #3 8002978: 4413 add r3, r2 800297a: 009b lsls r3, r3, #2 800297c: 440b add r3, r1 800297e: 3315 adds r3, #21 8002980: 2201 movs r2, #1 8002982: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8002984: 7bfa ldrb r2, [r7, #15] 8002986: 6879 ldr r1, [r7, #4] 8002988: 4613 mov r3, r2 800298a: 00db lsls r3, r3, #3 800298c: 4413 add r3, r2 800298e: 009b lsls r3, r3, #2 8002990: 440b add r3, r1 8002992: 3314 adds r3, #20 8002994: 7bfa ldrb r2, [r7, #15] 8002996: 701a strb r2, [r3, #0] hpcd->IN_ep[i].tx_fifo_num = i; 8002998: 7bfa ldrb r2, [r7, #15] 800299a: 7bfb ldrb r3, [r7, #15] 800299c: b298 uxth r0, r3 800299e: 6879 ldr r1, [r7, #4] 80029a0: 4613 mov r3, r2 80029a2: 00db lsls r3, r3, #3 80029a4: 4413 add r3, r2 80029a6: 009b lsls r3, r3, #2 80029a8: 440b add r3, r1 80029aa: 332e adds r3, #46 @ 0x2e 80029ac: 4602 mov r2, r0 80029ae: 801a strh r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 80029b0: 7bfa ldrb r2, [r7, #15] 80029b2: 6879 ldr r1, [r7, #4] 80029b4: 4613 mov r3, r2 80029b6: 00db lsls r3, r3, #3 80029b8: 4413 add r3, r2 80029ba: 009b lsls r3, r3, #2 80029bc: 440b add r3, r1 80029be: 3318 adds r3, #24 80029c0: 2200 movs r2, #0 80029c2: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 80029c4: 7bfa ldrb r2, [r7, #15] 80029c6: 6879 ldr r1, [r7, #4] 80029c8: 4613 mov r3, r2 80029ca: 00db lsls r3, r3, #3 80029cc: 4413 add r3, r2 80029ce: 009b lsls r3, r3, #2 80029d0: 440b add r3, r1 80029d2: 331c adds r3, #28 80029d4: 2200 movs r2, #0 80029d6: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 80029d8: 7bfa ldrb r2, [r7, #15] 80029da: 6879 ldr r1, [r7, #4] 80029dc: 4613 mov r3, r2 80029de: 00db lsls r3, r3, #3 80029e0: 4413 add r3, r2 80029e2: 009b lsls r3, r3, #2 80029e4: 440b add r3, r1 80029e6: 3320 adds r3, #32 80029e8: 2200 movs r2, #0 80029ea: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 80029ec: 7bfa ldrb r2, [r7, #15] 80029ee: 6879 ldr r1, [r7, #4] 80029f0: 4613 mov r3, r2 80029f2: 00db lsls r3, r3, #3 80029f4: 4413 add r3, r2 80029f6: 009b lsls r3, r3, #2 80029f8: 440b add r3, r1 80029fa: 3324 adds r3, #36 @ 0x24 80029fc: 2200 movs r2, #0 80029fe: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002a00: 7bfb ldrb r3, [r7, #15] 8002a02: 3301 adds r3, #1 8002a04: 73fb strb r3, [r7, #15] 8002a06: 687b ldr r3, [r7, #4] 8002a08: 791b ldrb r3, [r3, #4] 8002a0a: 7bfa ldrb r2, [r7, #15] 8002a0c: 429a cmp r2, r3 8002a0e: d3af bcc.n 8002970 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002a10: 2300 movs r3, #0 8002a12: 73fb strb r3, [r7, #15] 8002a14: e044 b.n 8002aa0 { hpcd->OUT_ep[i].is_in = 0U; 8002a16: 7bfa ldrb r2, [r7, #15] 8002a18: 6879 ldr r1, [r7, #4] 8002a1a: 4613 mov r3, r2 8002a1c: 00db lsls r3, r3, #3 8002a1e: 4413 add r3, r2 8002a20: 009b lsls r3, r3, #2 8002a22: 440b add r3, r1 8002a24: f203 2355 addw r3, r3, #597 @ 0x255 8002a28: 2200 movs r2, #0 8002a2a: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 8002a2c: 7bfa ldrb r2, [r7, #15] 8002a2e: 6879 ldr r1, [r7, #4] 8002a30: 4613 mov r3, r2 8002a32: 00db lsls r3, r3, #3 8002a34: 4413 add r3, r2 8002a36: 009b lsls r3, r3, #2 8002a38: 440b add r3, r1 8002a3a: f503 7315 add.w r3, r3, #596 @ 0x254 8002a3e: 7bfa ldrb r2, [r7, #15] 8002a40: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8002a42: 7bfa ldrb r2, [r7, #15] 8002a44: 6879 ldr r1, [r7, #4] 8002a46: 4613 mov r3, r2 8002a48: 00db lsls r3, r3, #3 8002a4a: 4413 add r3, r2 8002a4c: 009b lsls r3, r3, #2 8002a4e: 440b add r3, r1 8002a50: f503 7316 add.w r3, r3, #600 @ 0x258 8002a54: 2200 movs r2, #0 8002a56: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8002a58: 7bfa ldrb r2, [r7, #15] 8002a5a: 6879 ldr r1, [r7, #4] 8002a5c: 4613 mov r3, r2 8002a5e: 00db lsls r3, r3, #3 8002a60: 4413 add r3, r2 8002a62: 009b lsls r3, r3, #2 8002a64: 440b add r3, r1 8002a66: f503 7317 add.w r3, r3, #604 @ 0x25c 8002a6a: 2200 movs r2, #0 8002a6c: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 8002a6e: 7bfa ldrb r2, [r7, #15] 8002a70: 6879 ldr r1, [r7, #4] 8002a72: 4613 mov r3, r2 8002a74: 00db lsls r3, r3, #3 8002a76: 4413 add r3, r2 8002a78: 009b lsls r3, r3, #2 8002a7a: 440b add r3, r1 8002a7c: f503 7318 add.w r3, r3, #608 @ 0x260 8002a80: 2200 movs r2, #0 8002a82: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8002a84: 7bfa ldrb r2, [r7, #15] 8002a86: 6879 ldr r1, [r7, #4] 8002a88: 4613 mov r3, r2 8002a8a: 00db lsls r3, r3, #3 8002a8c: 4413 add r3, r2 8002a8e: 009b lsls r3, r3, #2 8002a90: 440b add r3, r1 8002a92: f503 7319 add.w r3, r3, #612 @ 0x264 8002a96: 2200 movs r2, #0 8002a98: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002a9a: 7bfb ldrb r3, [r7, #15] 8002a9c: 3301 adds r3, #1 8002a9e: 73fb strb r3, [r7, #15] 8002aa0: 687b ldr r3, [r7, #4] 8002aa2: 791b ldrb r3, [r3, #4] 8002aa4: 7bfa ldrb r2, [r7, #15] 8002aa6: 429a cmp r2, r3 8002aa8: d3b5 bcc.n 8002a16 } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002aaa: 687b ldr r3, [r7, #4] 8002aac: 6818 ldr r0, [r3, #0] 8002aae: 687b ldr r3, [r7, #4] 8002ab0: 7c1a ldrb r2, [r3, #16] 8002ab2: f88d 2000 strb.w r2, [sp] 8002ab6: 3304 adds r3, #4 8002ab8: cb0e ldmia r3, {r1, r2, r3} 8002aba: f004 f8b7 bl 8006c2c 8002abe: 4603 mov r3, r0 8002ac0: 2b00 cmp r3, #0 8002ac2: d005 beq.n 8002ad0 { hpcd->State = HAL_PCD_STATE_ERROR; 8002ac4: 687b ldr r3, [r7, #4] 8002ac6: 2202 movs r2, #2 8002ac8: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002acc: 2301 movs r3, #1 8002ace: e013 b.n 8002af8 } hpcd->USB_Address = 0U; 8002ad0: 687b ldr r3, [r7, #4] 8002ad2: 2200 movs r2, #0 8002ad4: 745a strb r2, [r3, #17] hpcd->State = HAL_PCD_STATE_READY; 8002ad6: 687b ldr r3, [r7, #4] 8002ad8: 2201 movs r2, #1 8002ada: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 8002ade: 687b ldr r3, [r7, #4] 8002ae0: 7b1b ldrb r3, [r3, #12] 8002ae2: 2b01 cmp r3, #1 8002ae4: d102 bne.n 8002aec { (void)HAL_PCDEx_ActivateLPM(hpcd); 8002ae6: 6878 ldr r0, [r7, #4] 8002ae8: f001 f956 bl 8003d98 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); 8002aec: 687b ldr r3, [r7, #4] 8002aee: 681b ldr r3, [r3, #0] 8002af0: 4618 mov r0, r3 8002af2: f005 f8f4 bl 8007cde return HAL_OK; 8002af6: 2300 movs r3, #0 } 8002af8: 4618 mov r0, r3 8002afa: 3710 adds r7, #16 8002afc: 46bd mov sp, r7 8002afe: bd80 pop {r7, pc} 08002b00 : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 8002b00: b580 push {r7, lr} 8002b02: b084 sub sp, #16 8002b04: af00 add r7, sp, #0 8002b06: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002b08: 687b ldr r3, [r7, #4] 8002b0a: 681b ldr r3, [r3, #0] 8002b0c: 60fb str r3, [r7, #12] __HAL_LOCK(hpcd); 8002b0e: 687b ldr r3, [r7, #4] 8002b10: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8002b14: 2b01 cmp r3, #1 8002b16: d101 bne.n 8002b1c 8002b18: 2302 movs r3, #2 8002b1a: e022 b.n 8002b62 8002b1c: 687b ldr r3, [r7, #4] 8002b1e: 2201 movs r2, #1 8002b20: f883 2494 strb.w r2, [r3, #1172] @ 0x494 if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8002b24: 68fb ldr r3, [r7, #12] 8002b26: 68db ldr r3, [r3, #12] 8002b28: f003 0340 and.w r3, r3, #64 @ 0x40 8002b2c: 2b00 cmp r3, #0 8002b2e: d009 beq.n 8002b44 (hpcd->Init.battery_charging_enable == 1U)) 8002b30: 687b ldr r3, [r7, #4] 8002b32: 7b5b ldrb r3, [r3, #13] if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8002b34: 2b01 cmp r3, #1 8002b36: d105 bne.n 8002b44 { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8002b38: 68fb ldr r3, [r7, #12] 8002b3a: 6b9b ldr r3, [r3, #56] @ 0x38 8002b3c: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8002b40: 68fb ldr r3, [r7, #12] 8002b42: 639a str r2, [r3, #56] @ 0x38 } __HAL_PCD_ENABLE(hpcd); 8002b44: 687b ldr r3, [r7, #4] 8002b46: 681b ldr r3, [r3, #0] 8002b48: 4618 mov r0, r3 8002b4a: f004 f801 bl 8006b50 (void)USB_DevConnect(hpcd->Instance); 8002b4e: 687b ldr r3, [r7, #4] 8002b50: 681b ldr r3, [r3, #0] 8002b52: 4618 mov r0, r3 8002b54: f005 f8a2 bl 8007c9c __HAL_UNLOCK(hpcd); 8002b58: 687b ldr r3, [r7, #4] 8002b5a: 2200 movs r2, #0 8002b5c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8002b60: 2300 movs r3, #0 } 8002b62: 4618 mov r0, r3 8002b64: 3710 adds r7, #16 8002b66: 46bd mov sp, r7 8002b68: bd80 pop {r7, pc} 08002b6a : * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 8002b6a: b590 push {r4, r7, lr} 8002b6c: b08d sub sp, #52 @ 0x34 8002b6e: af00 add r7, sp, #0 8002b70: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002b72: 687b ldr r3, [r7, #4] 8002b74: 681b ldr r3, [r3, #0] 8002b76: 623b str r3, [r7, #32] uint32_t USBx_BASE = (uint32_t)USBx; 8002b78: 6a3b ldr r3, [r7, #32] 8002b7a: 61fb str r3, [r7, #28] uint32_t epnum; uint32_t fifoemptymsk; uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) 8002b7c: 687b ldr r3, [r7, #4] 8002b7e: 681b ldr r3, [r3, #0] 8002b80: 4618 mov r0, r3 8002b82: f005 f960 bl 8007e46 8002b86: 4603 mov r3, r0 8002b88: 2b00 cmp r3, #0 8002b8a: f040 84b9 bne.w 8003500 { /* avoid spurious interrupt */ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 8002b8e: 687b ldr r3, [r7, #4] 8002b90: 681b ldr r3, [r3, #0] 8002b92: 4618 mov r0, r3 8002b94: f005 f8c4 bl 8007d20 8002b98: 4603 mov r3, r0 8002b9a: 2b00 cmp r3, #0 8002b9c: f000 84af beq.w 80034fe { return; } /* store current frame number */ hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; 8002ba0: 69fb ldr r3, [r7, #28] 8002ba2: f503 6300 add.w r3, r3, #2048 @ 0x800 8002ba6: 689b ldr r3, [r3, #8] 8002ba8: 0a1b lsrs r3, r3, #8 8002baa: f3c3 020d ubfx r2, r3, #0, #14 8002bae: 687b ldr r3, [r7, #4] 8002bb0: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4 if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) 8002bb4: 687b ldr r3, [r7, #4] 8002bb6: 681b ldr r3, [r3, #0] 8002bb8: 4618 mov r0, r3 8002bba: f005 f8b1 bl 8007d20 8002bbe: 4603 mov r3, r0 8002bc0: f003 0302 and.w r3, r3, #2 8002bc4: 2b02 cmp r3, #2 8002bc6: d107 bne.n 8002bd8 { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); 8002bc8: 687b ldr r3, [r7, #4] 8002bca: 681b ldr r3, [r3, #0] 8002bcc: 695a ldr r2, [r3, #20] 8002bce: 687b ldr r3, [r7, #4] 8002bd0: 681b ldr r3, [r3, #0] 8002bd2: f002 0202 and.w r2, r2, #2 8002bd6: 615a str r2, [r3, #20] } /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) 8002bd8: 687b ldr r3, [r7, #4] 8002bda: 681b ldr r3, [r3, #0] 8002bdc: 4618 mov r0, r3 8002bde: f005 f89f bl 8007d20 8002be2: 4603 mov r3, r0 8002be4: f003 0310 and.w r3, r3, #16 8002be8: 2b10 cmp r3, #16 8002bea: d161 bne.n 8002cb0 { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002bec: 687b ldr r3, [r7, #4] 8002bee: 681b ldr r3, [r3, #0] 8002bf0: 699a ldr r2, [r3, #24] 8002bf2: 687b ldr r3, [r7, #4] 8002bf4: 681b ldr r3, [r3, #0] 8002bf6: f022 0210 bic.w r2, r2, #16 8002bfa: 619a str r2, [r3, #24] RegVal = USBx->GRXSTSP; 8002bfc: 6a3b ldr r3, [r7, #32] 8002bfe: 6a1b ldr r3, [r3, #32] 8002c00: 61bb str r3, [r7, #24] ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; 8002c02: 69bb ldr r3, [r7, #24] 8002c04: f003 020f and.w r2, r3, #15 8002c08: 4613 mov r3, r2 8002c0a: 00db lsls r3, r3, #3 8002c0c: 4413 add r3, r2 8002c0e: 009b lsls r3, r3, #2 8002c10: f503 7314 add.w r3, r3, #592 @ 0x250 8002c14: 687a ldr r2, [r7, #4] 8002c16: 4413 add r3, r2 8002c18: 3304 adds r3, #4 8002c1a: 617b str r3, [r7, #20] if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) 8002c1c: 69bb ldr r3, [r7, #24] 8002c1e: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8002c22: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8002c26: d124 bne.n 8002c72 { if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) 8002c28: 69ba ldr r2, [r7, #24] 8002c2a: f647 73f0 movw r3, #32752 @ 0x7ff0 8002c2e: 4013 ands r3, r2 8002c30: 2b00 cmp r3, #0 8002c32: d035 beq.n 8002ca0 { (void)USB_ReadPacket(USBx, ep->xfer_buff, 8002c34: 697b ldr r3, [r7, #20] 8002c36: 68d9 ldr r1, [r3, #12] (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); 8002c38: 69bb ldr r3, [r7, #24] 8002c3a: 091b lsrs r3, r3, #4 8002c3c: b29b uxth r3, r3 (void)USB_ReadPacket(USBx, ep->xfer_buff, 8002c3e: f3c3 030a ubfx r3, r3, #0, #11 8002c42: b29b uxth r3, r3 8002c44: 461a mov r2, r3 8002c46: 6a38 ldr r0, [r7, #32] 8002c48: f004 fed6 bl 80079f8 ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002c4c: 697b ldr r3, [r7, #20] 8002c4e: 68da ldr r2, [r3, #12] 8002c50: 69bb ldr r3, [r7, #24] 8002c52: 091b lsrs r3, r3, #4 8002c54: f3c3 030a ubfx r3, r3, #0, #11 8002c58: 441a add r2, r3 8002c5a: 697b ldr r3, [r7, #20] 8002c5c: 60da str r2, [r3, #12] ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002c5e: 697b ldr r3, [r7, #20] 8002c60: 695a ldr r2, [r3, #20] 8002c62: 69bb ldr r3, [r7, #24] 8002c64: 091b lsrs r3, r3, #4 8002c66: f3c3 030a ubfx r3, r3, #0, #11 8002c6a: 441a add r2, r3 8002c6c: 697b ldr r3, [r7, #20] 8002c6e: 615a str r2, [r3, #20] 8002c70: e016 b.n 8002ca0 } } else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) 8002c72: 69bb ldr r3, [r7, #24] 8002c74: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8002c78: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8002c7c: d110 bne.n 8002ca0 { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); 8002c7e: 687b ldr r3, [r7, #4] 8002c80: f203 439c addw r3, r3, #1180 @ 0x49c 8002c84: 2208 movs r2, #8 8002c86: 4619 mov r1, r3 8002c88: 6a38 ldr r0, [r7, #32] 8002c8a: f004 feb5 bl 80079f8 ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002c8e: 697b ldr r3, [r7, #20] 8002c90: 695a ldr r2, [r3, #20] 8002c92: 69bb ldr r3, [r7, #24] 8002c94: 091b lsrs r3, r3, #4 8002c96: f3c3 030a ubfx r3, r3, #0, #11 8002c9a: 441a add r2, r3 8002c9c: 697b ldr r3, [r7, #20] 8002c9e: 615a str r2, [r3, #20] else { /* ... */ } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002ca0: 687b ldr r3, [r7, #4] 8002ca2: 681b ldr r3, [r3, #0] 8002ca4: 699a ldr r2, [r3, #24] 8002ca6: 687b ldr r3, [r7, #4] 8002ca8: 681b ldr r3, [r3, #0] 8002caa: f042 0210 orr.w r2, r2, #16 8002cae: 619a str r2, [r3, #24] } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) 8002cb0: 687b ldr r3, [r7, #4] 8002cb2: 681b ldr r3, [r3, #0] 8002cb4: 4618 mov r0, r3 8002cb6: f005 f833 bl 8007d20 8002cba: 4603 mov r3, r0 8002cbc: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002cc0: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8002cc4: f040 80a7 bne.w 8002e16 { epnum = 0U; 8002cc8: 2300 movs r3, #0 8002cca: 627b str r3, [r7, #36] @ 0x24 /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); 8002ccc: 687b ldr r3, [r7, #4] 8002cce: 681b ldr r3, [r3, #0] 8002cd0: 4618 mov r0, r3 8002cd2: f005 f838 bl 8007d46 8002cd6: 62b8 str r0, [r7, #40] @ 0x28 while (ep_intr != 0U) 8002cd8: e099 b.n 8002e0e { if ((ep_intr & 0x1U) != 0U) 8002cda: 6abb ldr r3, [r7, #40] @ 0x28 8002cdc: f003 0301 and.w r3, r3, #1 8002ce0: 2b00 cmp r3, #0 8002ce2: f000 808e beq.w 8002e02 { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8002ce6: 687b ldr r3, [r7, #4] 8002ce8: 681b ldr r3, [r3, #0] 8002cea: 6a7a ldr r2, [r7, #36] @ 0x24 8002cec: b2d2 uxtb r2, r2 8002cee: 4611 mov r1, r2 8002cf0: 4618 mov r0, r3 8002cf2: f005 f85c bl 8007dae 8002cf6: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) 8002cf8: 693b ldr r3, [r7, #16] 8002cfa: f003 0301 and.w r3, r3, #1 8002cfe: 2b00 cmp r3, #0 8002d00: d00c beq.n 8002d1c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); 8002d02: 6a7b ldr r3, [r7, #36] @ 0x24 8002d04: 015a lsls r2, r3, #5 8002d06: 69fb ldr r3, [r7, #28] 8002d08: 4413 add r3, r2 8002d0a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002d0e: 461a mov r2, r3 8002d10: 2301 movs r3, #1 8002d12: 6093 str r3, [r2, #8] (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); 8002d14: 6a79 ldr r1, [r7, #36] @ 0x24 8002d16: 6878 ldr r0, [r7, #4] 8002d18: f000 feb8 bl 8003a8c } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) 8002d1c: 693b ldr r3, [r7, #16] 8002d1e: f003 0308 and.w r3, r3, #8 8002d22: 2b00 cmp r3, #0 8002d24: d00c beq.n 8002d40 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); 8002d26: 6a7b ldr r3, [r7, #36] @ 0x24 8002d28: 015a lsls r2, r3, #5 8002d2a: 69fb ldr r3, [r7, #28] 8002d2c: 4413 add r3, r2 8002d2e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002d32: 461a mov r2, r3 8002d34: 2308 movs r3, #8 8002d36: 6093 str r3, [r2, #8] /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); 8002d38: 6a79 ldr r1, [r7, #36] @ 0x24 8002d3a: 6878 ldr r0, [r7, #4] 8002d3c: f000 ff8e bl 8003c5c } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) 8002d40: 693b ldr r3, [r7, #16] 8002d42: f003 0310 and.w r3, r3, #16 8002d46: 2b00 cmp r3, #0 8002d48: d008 beq.n 8002d5c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); 8002d4a: 6a7b ldr r3, [r7, #36] @ 0x24 8002d4c: 015a lsls r2, r3, #5 8002d4e: 69fb ldr r3, [r7, #28] 8002d50: 4413 add r3, r2 8002d52: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002d56: 461a mov r2, r3 8002d58: 2310 movs r3, #16 8002d5a: 6093 str r3, [r2, #8] } /* Clear OUT Endpoint disable interrupt */ if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) 8002d5c: 693b ldr r3, [r7, #16] 8002d5e: f003 0302 and.w r3, r3, #2 8002d62: 2b00 cmp r3, #0 8002d64: d030 beq.n 8002dc8 { if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) 8002d66: 6a3b ldr r3, [r7, #32] 8002d68: 695b ldr r3, [r3, #20] 8002d6a: f003 0380 and.w r3, r3, #128 @ 0x80 8002d6e: 2b80 cmp r3, #128 @ 0x80 8002d70: d109 bne.n 8002d86 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; 8002d72: 69fb ldr r3, [r7, #28] 8002d74: f503 6300 add.w r3, r3, #2048 @ 0x800 8002d78: 685b ldr r3, [r3, #4] 8002d7a: 69fa ldr r2, [r7, #28] 8002d7c: f502 6200 add.w r2, r2, #2048 @ 0x800 8002d80: f443 6380 orr.w r3, r3, #1024 @ 0x400 8002d84: 6053 str r3, [r2, #4] } ep = &hpcd->OUT_ep[epnum]; 8002d86: 6a7a ldr r2, [r7, #36] @ 0x24 8002d88: 4613 mov r3, r2 8002d8a: 00db lsls r3, r3, #3 8002d8c: 4413 add r3, r2 8002d8e: 009b lsls r3, r3, #2 8002d90: f503 7314 add.w r3, r3, #592 @ 0x250 8002d94: 687a ldr r2, [r7, #4] 8002d96: 4413 add r3, r2 8002d98: 3304 adds r3, #4 8002d9a: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 8002d9c: 697b ldr r3, [r7, #20] 8002d9e: 78db ldrb r3, [r3, #3] 8002da0: 2b01 cmp r3, #1 8002da2: d108 bne.n 8002db6 { ep->is_iso_incomplete = 0U; 8002da4: 697b ldr r3, [r7, #20] 8002da6: 2200 movs r2, #0 8002da8: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); 8002daa: 6a7b ldr r3, [r7, #36] @ 0x24 8002dac: b2db uxtb r3, r3 8002dae: 4619 mov r1, r3 8002db0: 6878 ldr r0, [r7, #4] 8002db2: f007 f8f5 bl 8009fa0 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); 8002db6: 6a7b ldr r3, [r7, #36] @ 0x24 8002db8: 015a lsls r2, r3, #5 8002dba: 69fb ldr r3, [r7, #28] 8002dbc: 4413 add r3, r2 8002dbe: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002dc2: 461a mov r2, r3 8002dc4: 2302 movs r3, #2 8002dc6: 6093 str r3, [r2, #8] } /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8002dc8: 693b ldr r3, [r7, #16] 8002dca: f003 0320 and.w r3, r3, #32 8002dce: 2b00 cmp r3, #0 8002dd0: d008 beq.n 8002de4 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8002dd2: 6a7b ldr r3, [r7, #36] @ 0x24 8002dd4: 015a lsls r2, r3, #5 8002dd6: 69fb ldr r3, [r7, #28] 8002dd8: 4413 add r3, r2 8002dda: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002dde: 461a mov r2, r3 8002de0: 2320 movs r3, #32 8002de2: 6093 str r3, [r2, #8] } /* Clear OUT NAK interrupt */ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) 8002de4: 693b ldr r3, [r7, #16] 8002de6: f403 5300 and.w r3, r3, #8192 @ 0x2000 8002dea: 2b00 cmp r3, #0 8002dec: d009 beq.n 8002e02 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); 8002dee: 6a7b ldr r3, [r7, #36] @ 0x24 8002df0: 015a lsls r2, r3, #5 8002df2: 69fb ldr r3, [r7, #28] 8002df4: 4413 add r3, r2 8002df6: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002dfa: 461a mov r2, r3 8002dfc: f44f 5300 mov.w r3, #8192 @ 0x2000 8002e00: 6093 str r3, [r2, #8] } } epnum++; 8002e02: 6a7b ldr r3, [r7, #36] @ 0x24 8002e04: 3301 adds r3, #1 8002e06: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 8002e08: 6abb ldr r3, [r7, #40] @ 0x28 8002e0a: 085b lsrs r3, r3, #1 8002e0c: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 8002e0e: 6abb ldr r3, [r7, #40] @ 0x28 8002e10: 2b00 cmp r3, #0 8002e12: f47f af62 bne.w 8002cda } } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) 8002e16: 687b ldr r3, [r7, #4] 8002e18: 681b ldr r3, [r3, #0] 8002e1a: 4618 mov r0, r3 8002e1c: f004 ff80 bl 8007d20 8002e20: 4603 mov r3, r0 8002e22: f403 2380 and.w r3, r3, #262144 @ 0x40000 8002e26: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8002e2a: f040 80db bne.w 8002fe4 { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); 8002e2e: 687b ldr r3, [r7, #4] 8002e30: 681b ldr r3, [r3, #0] 8002e32: 4618 mov r0, r3 8002e34: f004 ffa1 bl 8007d7a 8002e38: 62b8 str r0, [r7, #40] @ 0x28 epnum = 0U; 8002e3a: 2300 movs r3, #0 8002e3c: 627b str r3, [r7, #36] @ 0x24 while (ep_intr != 0U) 8002e3e: e0cd b.n 8002fdc { if ((ep_intr & 0x1U) != 0U) /* In ITR */ 8002e40: 6abb ldr r3, [r7, #40] @ 0x28 8002e42: f003 0301 and.w r3, r3, #1 8002e46: 2b00 cmp r3, #0 8002e48: f000 80c2 beq.w 8002fd0 { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8002e4c: 687b ldr r3, [r7, #4] 8002e4e: 681b ldr r3, [r3, #0] 8002e50: 6a7a ldr r2, [r7, #36] @ 0x24 8002e52: b2d2 uxtb r2, r2 8002e54: 4611 mov r1, r2 8002e56: 4618 mov r0, r3 8002e58: f004 ffc7 bl 8007dea 8002e5c: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) 8002e5e: 693b ldr r3, [r7, #16] 8002e60: f003 0301 and.w r3, r3, #1 8002e64: 2b00 cmp r3, #0 8002e66: d057 beq.n 8002f18 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8002e68: 6a7b ldr r3, [r7, #36] @ 0x24 8002e6a: f003 030f and.w r3, r3, #15 8002e6e: 2201 movs r2, #1 8002e70: fa02 f303 lsl.w r3, r2, r3 8002e74: 60fb str r3, [r7, #12] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8002e76: 69fb ldr r3, [r7, #28] 8002e78: f503 6300 add.w r3, r3, #2048 @ 0x800 8002e7c: 6b5a ldr r2, [r3, #52] @ 0x34 8002e7e: 68fb ldr r3, [r7, #12] 8002e80: 43db mvns r3, r3 8002e82: 69f9 ldr r1, [r7, #28] 8002e84: f501 6100 add.w r1, r1, #2048 @ 0x800 8002e88: 4013 ands r3, r2 8002e8a: 634b str r3, [r1, #52] @ 0x34 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); 8002e8c: 6a7b ldr r3, [r7, #36] @ 0x24 8002e8e: 015a lsls r2, r3, #5 8002e90: 69fb ldr r3, [r7, #28] 8002e92: 4413 add r3, r2 8002e94: f503 6310 add.w r3, r3, #2304 @ 0x900 8002e98: 461a mov r2, r3 8002e9a: 2301 movs r3, #1 8002e9c: 6093 str r3, [r2, #8] if (hpcd->Init.dma_enable == 1U) 8002e9e: 687b ldr r3, [r7, #4] 8002ea0: 799b ldrb r3, [r3, #6] 8002ea2: 2b01 cmp r3, #1 8002ea4: d132 bne.n 8002f0c { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 8002ea6: 6879 ldr r1, [r7, #4] 8002ea8: 6a7a ldr r2, [r7, #36] @ 0x24 8002eaa: 4613 mov r3, r2 8002eac: 00db lsls r3, r3, #3 8002eae: 4413 add r3, r2 8002eb0: 009b lsls r3, r3, #2 8002eb2: 440b add r3, r1 8002eb4: 3320 adds r3, #32 8002eb6: 6819 ldr r1, [r3, #0] 8002eb8: 6878 ldr r0, [r7, #4] 8002eba: 6a7a ldr r2, [r7, #36] @ 0x24 8002ebc: 4613 mov r3, r2 8002ebe: 00db lsls r3, r3, #3 8002ec0: 4413 add r3, r2 8002ec2: 009b lsls r3, r3, #2 8002ec4: 4403 add r3, r0 8002ec6: 331c adds r3, #28 8002ec8: 681b ldr r3, [r3, #0] 8002eca: 4419 add r1, r3 8002ecc: 6878 ldr r0, [r7, #4] 8002ece: 6a7a ldr r2, [r7, #36] @ 0x24 8002ed0: 4613 mov r3, r2 8002ed2: 00db lsls r3, r3, #3 8002ed4: 4413 add r3, r2 8002ed6: 009b lsls r3, r3, #2 8002ed8: 4403 add r3, r0 8002eda: 3320 adds r3, #32 8002edc: 6019 str r1, [r3, #0] /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) 8002ede: 6a7b ldr r3, [r7, #36] @ 0x24 8002ee0: 2b00 cmp r3, #0 8002ee2: d113 bne.n 8002f0c 8002ee4: 6879 ldr r1, [r7, #4] 8002ee6: 6a7a ldr r2, [r7, #36] @ 0x24 8002ee8: 4613 mov r3, r2 8002eea: 00db lsls r3, r3, #3 8002eec: 4413 add r3, r2 8002eee: 009b lsls r3, r3, #2 8002ef0: 440b add r3, r1 8002ef2: 3324 adds r3, #36 @ 0x24 8002ef4: 681b ldr r3, [r3, #0] 8002ef6: 2b00 cmp r3, #0 8002ef8: d108 bne.n 8002f0c { /* prepare to rx more setup packets */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8002efa: 687b ldr r3, [r7, #4] 8002efc: 6818 ldr r0, [r3, #0] 8002efe: 687b ldr r3, [r7, #4] 8002f00: f203 439c addw r3, r3, #1180 @ 0x49c 8002f04: 461a mov r2, r3 8002f06: 2101 movs r1, #1 8002f08: f004 ffce bl 8007ea8 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); 8002f0c: 6a7b ldr r3, [r7, #36] @ 0x24 8002f0e: b2db uxtb r3, r3 8002f10: 4619 mov r1, r3 8002f12: 6878 ldr r0, [r7, #4] 8002f14: f006 ffbf bl 8009e96 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) 8002f18: 693b ldr r3, [r7, #16] 8002f1a: f003 0308 and.w r3, r3, #8 8002f1e: 2b00 cmp r3, #0 8002f20: d008 beq.n 8002f34 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); 8002f22: 6a7b ldr r3, [r7, #36] @ 0x24 8002f24: 015a lsls r2, r3, #5 8002f26: 69fb ldr r3, [r7, #28] 8002f28: 4413 add r3, r2 8002f2a: f503 6310 add.w r3, r3, #2304 @ 0x900 8002f2e: 461a mov r2, r3 8002f30: 2308 movs r3, #8 8002f32: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) 8002f34: 693b ldr r3, [r7, #16] 8002f36: f003 0310 and.w r3, r3, #16 8002f3a: 2b00 cmp r3, #0 8002f3c: d008 beq.n 8002f50 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); 8002f3e: 6a7b ldr r3, [r7, #36] @ 0x24 8002f40: 015a lsls r2, r3, #5 8002f42: 69fb ldr r3, [r7, #28] 8002f44: 4413 add r3, r2 8002f46: f503 6310 add.w r3, r3, #2304 @ 0x900 8002f4a: 461a mov r2, r3 8002f4c: 2310 movs r3, #16 8002f4e: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) 8002f50: 693b ldr r3, [r7, #16] 8002f52: f003 0340 and.w r3, r3, #64 @ 0x40 8002f56: 2b00 cmp r3, #0 8002f58: d008 beq.n 8002f6c { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); 8002f5a: 6a7b ldr r3, [r7, #36] @ 0x24 8002f5c: 015a lsls r2, r3, #5 8002f5e: 69fb ldr r3, [r7, #28] 8002f60: 4413 add r3, r2 8002f62: f503 6310 add.w r3, r3, #2304 @ 0x900 8002f66: 461a mov r2, r3 8002f68: 2340 movs r3, #64 @ 0x40 8002f6a: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) 8002f6c: 693b ldr r3, [r7, #16] 8002f6e: f003 0302 and.w r3, r3, #2 8002f72: 2b00 cmp r3, #0 8002f74: d023 beq.n 8002fbe { (void)USB_FlushTxFifo(USBx, epnum); 8002f76: 6a79 ldr r1, [r7, #36] @ 0x24 8002f78: 6a38 ldr r0, [r7, #32] 8002f7a: f003 ffb5 bl 8006ee8 ep = &hpcd->IN_ep[epnum]; 8002f7e: 6a7a ldr r2, [r7, #36] @ 0x24 8002f80: 4613 mov r3, r2 8002f82: 00db lsls r3, r3, #3 8002f84: 4413 add r3, r2 8002f86: 009b lsls r3, r3, #2 8002f88: 3310 adds r3, #16 8002f8a: 687a ldr r2, [r7, #4] 8002f8c: 4413 add r3, r2 8002f8e: 3304 adds r3, #4 8002f90: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 8002f92: 697b ldr r3, [r7, #20] 8002f94: 78db ldrb r3, [r3, #3] 8002f96: 2b01 cmp r3, #1 8002f98: d108 bne.n 8002fac { ep->is_iso_incomplete = 0U; 8002f9a: 697b ldr r3, [r7, #20] 8002f9c: 2200 movs r2, #0 8002f9e: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); 8002fa0: 6a7b ldr r3, [r7, #36] @ 0x24 8002fa2: b2db uxtb r3, r3 8002fa4: 4619 mov r1, r3 8002fa6: 6878 ldr r0, [r7, #4] 8002fa8: f007 f80c bl 8009fc4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); 8002fac: 6a7b ldr r3, [r7, #36] @ 0x24 8002fae: 015a lsls r2, r3, #5 8002fb0: 69fb ldr r3, [r7, #28] 8002fb2: 4413 add r3, r2 8002fb4: f503 6310 add.w r3, r3, #2304 @ 0x900 8002fb8: 461a mov r2, r3 8002fba: 2302 movs r3, #2 8002fbc: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) 8002fbe: 693b ldr r3, [r7, #16] 8002fc0: f003 0380 and.w r3, r3, #128 @ 0x80 8002fc4: 2b00 cmp r3, #0 8002fc6: d003 beq.n 8002fd0 { (void)PCD_WriteEmptyTxFifo(hpcd, epnum); 8002fc8: 6a79 ldr r1, [r7, #36] @ 0x24 8002fca: 6878 ldr r0, [r7, #4] 8002fcc: f000 fcd2 bl 8003974 } } epnum++; 8002fd0: 6a7b ldr r3, [r7, #36] @ 0x24 8002fd2: 3301 adds r3, #1 8002fd4: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 8002fd6: 6abb ldr r3, [r7, #40] @ 0x28 8002fd8: 085b lsrs r3, r3, #1 8002fda: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 8002fdc: 6abb ldr r3, [r7, #40] @ 0x28 8002fde: 2b00 cmp r3, #0 8002fe0: f47f af2e bne.w 8002e40 } } /* Handle Resume Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) 8002fe4: 687b ldr r3, [r7, #4] 8002fe6: 681b ldr r3, [r3, #0] 8002fe8: 4618 mov r0, r3 8002fea: f004 fe99 bl 8007d20 8002fee: 4603 mov r3, r0 8002ff0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8002ff4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8002ff8: d122 bne.n 8003040 { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 8002ffa: 69fb ldr r3, [r7, #28] 8002ffc: f503 6300 add.w r3, r3, #2048 @ 0x800 8003000: 685b ldr r3, [r3, #4] 8003002: 69fa ldr r2, [r7, #28] 8003004: f502 6200 add.w r2, r2, #2048 @ 0x800 8003008: f023 0301 bic.w r3, r3, #1 800300c: 6053 str r3, [r2, #4] if (hpcd->LPM_State == LPM_L1) 800300e: 687b ldr r3, [r7, #4] 8003010: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 8003014: 2b01 cmp r3, #1 8003016: d108 bne.n 800302a { hpcd->LPM_State = LPM_L0; 8003018: 687b ldr r3, [r7, #4] 800301a: 2200 movs r2, #0 800301c: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 8003020: 2100 movs r1, #0 8003022: 6878 ldr r0, [r7, #4] 8003024: f007 f974 bl 800a310 8003028: e002 b.n 8003030 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 800302a: 6878 ldr r0, [r7, #4] 800302c: f006 ffaa bl 8009f84 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); 8003030: 687b ldr r3, [r7, #4] 8003032: 681b ldr r3, [r3, #0] 8003034: 695a ldr r2, [r3, #20] 8003036: 687b ldr r3, [r7, #4] 8003038: 681b ldr r3, [r3, #0] 800303a: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000 800303e: 615a str r2, [r3, #20] } /* Handle Suspend Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) 8003040: 687b ldr r3, [r7, #4] 8003042: 681b ldr r3, [r3, #0] 8003044: 4618 mov r0, r3 8003046: f004 fe6b bl 8007d20 800304a: 4603 mov r3, r0 800304c: f403 6300 and.w r3, r3, #2048 @ 0x800 8003050: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8003054: d112 bne.n 800307c { if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 8003056: 69fb ldr r3, [r7, #28] 8003058: f503 6300 add.w r3, r3, #2048 @ 0x800 800305c: 689b ldr r3, [r3, #8] 800305e: f003 0301 and.w r3, r3, #1 8003062: 2b01 cmp r3, #1 8003064: d102 bne.n 800306c { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 8003066: 6878 ldr r0, [r7, #4] 8003068: f006 ff66 bl 8009f38 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); 800306c: 687b ldr r3, [r7, #4] 800306e: 681b ldr r3, [r3, #0] 8003070: 695a ldr r2, [r3, #20] 8003072: 687b ldr r3, [r7, #4] 8003074: 681b ldr r3, [r3, #0] 8003076: f402 6200 and.w r2, r2, #2048 @ 0x800 800307a: 615a str r2, [r3, #20] } #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) 800307c: 687b ldr r3, [r7, #4] 800307e: 681b ldr r3, [r3, #0] 8003080: 4618 mov r0, r3 8003082: f004 fe4d bl 8007d20 8003086: 4603 mov r3, r0 8003088: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800308c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8003090: d121 bne.n 80030d6 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); 8003092: 687b ldr r3, [r7, #4] 8003094: 681b ldr r3, [r3, #0] 8003096: 695a ldr r2, [r3, #20] 8003098: 687b ldr r3, [r7, #4] 800309a: 681b ldr r3, [r3, #0] 800309c: f002 6200 and.w r2, r2, #134217728 @ 0x8000000 80030a0: 615a str r2, [r3, #20] if (hpcd->LPM_State == LPM_L0) 80030a2: 687b ldr r3, [r7, #4] 80030a4: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 80030a8: 2b00 cmp r3, #0 80030aa: d111 bne.n 80030d0 { hpcd->LPM_State = LPM_L1; 80030ac: 687b ldr r3, [r7, #4] 80030ae: 2201 movs r2, #1 80030b0: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; 80030b4: 687b ldr r3, [r7, #4] 80030b6: 681b ldr r3, [r3, #0] 80030b8: 6d5b ldr r3, [r3, #84] @ 0x54 80030ba: 089b lsrs r3, r3, #2 80030bc: f003 020f and.w r2, r3, #15 80030c0: 687b ldr r3, [r7, #4] 80030c2: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 80030c6: 2101 movs r1, #1 80030c8: 6878 ldr r0, [r7, #4] 80030ca: f007 f921 bl 800a310 80030ce: e002 b.n 80030d6 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 80030d0: 6878 ldr r0, [r7, #4] 80030d2: f006 ff31 bl 8009f38 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) 80030d6: 687b ldr r3, [r7, #4] 80030d8: 681b ldr r3, [r3, #0] 80030da: 4618 mov r0, r3 80030dc: f004 fe20 bl 8007d20 80030e0: 4603 mov r3, r0 80030e2: f403 5380 and.w r3, r3, #4096 @ 0x1000 80030e6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80030ea: f040 80b7 bne.w 800325c { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 80030ee: 69fb ldr r3, [r7, #28] 80030f0: f503 6300 add.w r3, r3, #2048 @ 0x800 80030f4: 685b ldr r3, [r3, #4] 80030f6: 69fa ldr r2, [r7, #28] 80030f8: f502 6200 add.w r2, r2, #2048 @ 0x800 80030fc: f023 0301 bic.w r3, r3, #1 8003100: 6053 str r3, [r2, #4] (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); 8003102: 687b ldr r3, [r7, #4] 8003104: 681b ldr r3, [r3, #0] 8003106: 2110 movs r1, #16 8003108: 4618 mov r0, r3 800310a: f003 feed bl 8006ee8 for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800310e: 2300 movs r3, #0 8003110: 62fb str r3, [r7, #44] @ 0x2c 8003112: e046 b.n 80031a2 { USBx_INEP(i)->DIEPINT = 0xFB7FU; 8003114: 6afb ldr r3, [r7, #44] @ 0x2c 8003116: 015a lsls r2, r3, #5 8003118: 69fb ldr r3, [r7, #28] 800311a: 4413 add r3, r2 800311c: f503 6310 add.w r3, r3, #2304 @ 0x900 8003120: 461a mov r2, r3 8003122: f64f 337f movw r3, #64383 @ 0xfb7f 8003126: 6093 str r3, [r2, #8] USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 8003128: 6afb ldr r3, [r7, #44] @ 0x2c 800312a: 015a lsls r2, r3, #5 800312c: 69fb ldr r3, [r7, #28] 800312e: 4413 add r3, r2 8003130: f503 6310 add.w r3, r3, #2304 @ 0x900 8003134: 681b ldr r3, [r3, #0] 8003136: 6afa ldr r2, [r7, #44] @ 0x2c 8003138: 0151 lsls r1, r2, #5 800313a: 69fa ldr r2, [r7, #28] 800313c: 440a add r2, r1 800313e: f502 6210 add.w r2, r2, #2304 @ 0x900 8003142: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8003146: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8003148: 6afb ldr r3, [r7, #44] @ 0x2c 800314a: 015a lsls r2, r3, #5 800314c: 69fb ldr r3, [r7, #28] 800314e: 4413 add r3, r2 8003150: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003154: 461a mov r2, r3 8003156: f64f 337f movw r3, #64383 @ 0xfb7f 800315a: 6093 str r3, [r2, #8] USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 800315c: 6afb ldr r3, [r7, #44] @ 0x2c 800315e: 015a lsls r2, r3, #5 8003160: 69fb ldr r3, [r7, #28] 8003162: 4413 add r3, r2 8003164: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003168: 681b ldr r3, [r3, #0] 800316a: 6afa ldr r2, [r7, #44] @ 0x2c 800316c: 0151 lsls r1, r2, #5 800316e: 69fa ldr r2, [r7, #28] 8003170: 440a add r2, r1 8003172: f502 6230 add.w r2, r2, #2816 @ 0xb00 8003176: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 800317a: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 800317c: 6afb ldr r3, [r7, #44] @ 0x2c 800317e: 015a lsls r2, r3, #5 8003180: 69fb ldr r3, [r7, #28] 8003182: 4413 add r3, r2 8003184: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003188: 681b ldr r3, [r3, #0] 800318a: 6afa ldr r2, [r7, #44] @ 0x2c 800318c: 0151 lsls r1, r2, #5 800318e: 69fa ldr r2, [r7, #28] 8003190: 440a add r2, r1 8003192: f502 6230 add.w r2, r2, #2816 @ 0xb00 8003196: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800319a: 6013 str r3, [r2, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800319c: 6afb ldr r3, [r7, #44] @ 0x2c 800319e: 3301 adds r3, #1 80031a0: 62fb str r3, [r7, #44] @ 0x2c 80031a2: 687b ldr r3, [r7, #4] 80031a4: 791b ldrb r3, [r3, #4] 80031a6: 461a mov r2, r3 80031a8: 6afb ldr r3, [r7, #44] @ 0x2c 80031aa: 4293 cmp r3, r2 80031ac: d3b2 bcc.n 8003114 } USBx_DEVICE->DAINTMSK |= 0x10001U; 80031ae: 69fb ldr r3, [r7, #28] 80031b0: f503 6300 add.w r3, r3, #2048 @ 0x800 80031b4: 69db ldr r3, [r3, #28] 80031b6: 69fa ldr r2, [r7, #28] 80031b8: f502 6200 add.w r2, r2, #2048 @ 0x800 80031bc: f043 1301 orr.w r3, r3, #65537 @ 0x10001 80031c0: 61d3 str r3, [r2, #28] if (hpcd->Init.use_dedicated_ep1 != 0U) 80031c2: 687b ldr r3, [r7, #4] 80031c4: 7bdb ldrb r3, [r3, #15] 80031c6: 2b00 cmp r3, #0 80031c8: d016 beq.n 80031f8 { USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | 80031ca: 69fb ldr r3, [r7, #28] 80031cc: f503 6300 add.w r3, r3, #2048 @ 0x800 80031d0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80031d4: 69fa ldr r2, [r7, #28] 80031d6: f502 6200 add.w r2, r2, #2048 @ 0x800 80031da: f043 030b orr.w r3, r3, #11 80031de: f8c2 3084 str.w r3, [r2, #132] @ 0x84 USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM; USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | 80031e2: 69fb ldr r3, [r7, #28] 80031e4: f503 6300 add.w r3, r3, #2048 @ 0x800 80031e8: 6c5b ldr r3, [r3, #68] @ 0x44 80031ea: 69fa ldr r2, [r7, #28] 80031ec: f502 6200 add.w r2, r2, #2048 @ 0x800 80031f0: f043 030b orr.w r3, r3, #11 80031f4: 6453 str r3, [r2, #68] @ 0x44 80031f6: e015 b.n 8003224 USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } else { USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | 80031f8: 69fb ldr r3, [r7, #28] 80031fa: f503 6300 add.w r3, r3, #2048 @ 0x800 80031fe: 695b ldr r3, [r3, #20] 8003200: 69fa ldr r2, [r7, #28] 8003202: f502 6200 add.w r2, r2, #2048 @ 0x800 8003206: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800320a: f043 032b orr.w r3, r3, #43 @ 0x2b 800320e: 6153 str r3, [r2, #20] USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM | USB_OTG_DOEPMSK_NAKM; USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | 8003210: 69fb ldr r3, [r7, #28] 8003212: f503 6300 add.w r3, r3, #2048 @ 0x800 8003216: 691b ldr r3, [r3, #16] 8003218: 69fa ldr r2, [r7, #28] 800321a: f502 6200 add.w r2, r2, #2048 @ 0x800 800321e: f043 030b orr.w r3, r3, #11 8003222: 6113 str r3, [r2, #16] USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; 8003224: 69fb ldr r3, [r7, #28] 8003226: f503 6300 add.w r3, r3, #2048 @ 0x800 800322a: 681b ldr r3, [r3, #0] 800322c: 69fa ldr r2, [r7, #28] 800322e: f502 6200 add.w r2, r2, #2048 @ 0x800 8003232: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 8003236: 6013 str r3, [r2, #0] /* setup EP0 to receive SETUP packets */ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 8003238: 687b ldr r3, [r7, #4] 800323a: 6818 ldr r0, [r3, #0] 800323c: 687b ldr r3, [r7, #4] 800323e: 7999 ldrb r1, [r3, #6] (uint8_t *)hpcd->Setup); 8003240: 687b ldr r3, [r7, #4] 8003242: f203 439c addw r3, r3, #1180 @ 0x49c (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 8003246: 461a mov r2, r3 8003248: f004 fe2e bl 8007ea8 __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); 800324c: 687b ldr r3, [r7, #4] 800324e: 681b ldr r3, [r3, #0] 8003250: 695a ldr r2, [r3, #20] 8003252: 687b ldr r3, [r7, #4] 8003254: 681b ldr r3, [r3, #0] 8003256: f402 5280 and.w r2, r2, #4096 @ 0x1000 800325a: 615a str r2, [r3, #20] } /* Handle Enumeration done Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) 800325c: 687b ldr r3, [r7, #4] 800325e: 681b ldr r3, [r3, #0] 8003260: 4618 mov r0, r3 8003262: f004 fd5d bl 8007d20 8003266: 4603 mov r3, r0 8003268: f403 5300 and.w r3, r3, #8192 @ 0x2000 800326c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8003270: d123 bne.n 80032ba { (void)USB_ActivateSetup(hpcd->Instance); 8003272: 687b ldr r3, [r7, #4] 8003274: 681b ldr r3, [r3, #0] 8003276: 4618 mov r0, r3 8003278: f004 fdf3 bl 8007e62 hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); 800327c: 687b ldr r3, [r7, #4] 800327e: 681b ldr r3, [r3, #0] 8003280: 4618 mov r0, r3 8003282: f003 feaa bl 8006fda 8003286: 4603 mov r3, r0 8003288: 461a mov r2, r3 800328a: 687b ldr r3, [r7, #4] 800328c: 71da strb r2, [r3, #7] /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, 800328e: 687b ldr r3, [r7, #4] 8003290: 681c ldr r4, [r3, #0] 8003292: f000 fe8b bl 8003fac 8003296: 4601 mov r1, r0 HAL_RCC_GetHCLKFreq(), (uint8_t)hpcd->Init.speed); 8003298: 687b ldr r3, [r7, #4] 800329a: 79db ldrb r3, [r3, #7] (void)USB_SetTurnaroundTime(hpcd->Instance, 800329c: 461a mov r2, r3 800329e: 4620 mov r0, r4 80032a0: f003 fbb4 bl 8006a0c #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 80032a4: 6878 ldr r0, [r7, #4] 80032a6: f006 fe1e bl 8009ee6 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); 80032aa: 687b ldr r3, [r7, #4] 80032ac: 681b ldr r3, [r3, #0] 80032ae: 695a ldr r2, [r3, #20] 80032b0: 687b ldr r3, [r7, #4] 80032b2: 681b ldr r3, [r3, #0] 80032b4: f402 5200 and.w r2, r2, #8192 @ 0x2000 80032b8: 615a str r2, [r3, #20] } /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) 80032ba: 687b ldr r3, [r7, #4] 80032bc: 681b ldr r3, [r3, #0] 80032be: 4618 mov r0, r3 80032c0: f004 fd2e bl 8007d20 80032c4: 4603 mov r3, r0 80032c6: f003 0308 and.w r3, r3, #8 80032ca: 2b08 cmp r3, #8 80032cc: d10a bne.n 80032e4 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 80032ce: 6878 ldr r0, [r7, #4] 80032d0: f006 fdfb bl 8009eca #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); 80032d4: 687b ldr r3, [r7, #4] 80032d6: 681b ldr r3, [r3, #0] 80032d8: 695a ldr r2, [r3, #20] 80032da: 687b ldr r3, [r7, #4] 80032dc: 681b ldr r3, [r3, #0] 80032de: f002 0208 and.w r2, r2, #8 80032e2: 615a str r2, [r3, #20] } /* Handle Global OUT NAK effective Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) 80032e4: 687b ldr r3, [r7, #4] 80032e6: 681b ldr r3, [r3, #0] 80032e8: 4618 mov r0, r3 80032ea: f004 fd19 bl 8007d20 80032ee: 4603 mov r3, r0 80032f0: f003 0380 and.w r3, r3, #128 @ 0x80 80032f4: 2b80 cmp r3, #128 @ 0x80 80032f6: d123 bne.n 8003340 { USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; 80032f8: 6a3b ldr r3, [r7, #32] 80032fa: 699b ldr r3, [r3, #24] 80032fc: f023 0280 bic.w r2, r3, #128 @ 0x80 8003300: 6a3b ldr r3, [r7, #32] 8003302: 619a str r2, [r3, #24] for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003304: 2301 movs r3, #1 8003306: 627b str r3, [r7, #36] @ 0x24 8003308: e014 b.n 8003334 { if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) 800330a: 6879 ldr r1, [r7, #4] 800330c: 6a7a ldr r2, [r7, #36] @ 0x24 800330e: 4613 mov r3, r2 8003310: 00db lsls r3, r3, #3 8003312: 4413 add r3, r2 8003314: 009b lsls r3, r3, #2 8003316: 440b add r3, r1 8003318: f203 2357 addw r3, r3, #599 @ 0x257 800331c: 781b ldrb r3, [r3, #0] 800331e: 2b01 cmp r3, #1 8003320: d105 bne.n 800332e { /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); 8003322: 6a7b ldr r3, [r7, #36] @ 0x24 8003324: b2db uxtb r3, r3 8003326: 4619 mov r1, r3 8003328: 6878 ldr r0, [r7, #4] 800332a: f000 faf2 bl 8003912 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 800332e: 6a7b ldr r3, [r7, #36] @ 0x24 8003330: 3301 adds r3, #1 8003332: 627b str r3, [r7, #36] @ 0x24 8003334: 687b ldr r3, [r7, #4] 8003336: 791b ldrb r3, [r3, #4] 8003338: 461a mov r2, r3 800333a: 6a7b ldr r3, [r7, #36] @ 0x24 800333c: 4293 cmp r3, r2 800333e: d3e4 bcc.n 800330a } } } /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) 8003340: 687b ldr r3, [r7, #4] 8003342: 681b ldr r3, [r3, #0] 8003344: 4618 mov r0, r3 8003346: f004 fceb bl 8007d20 800334a: 4603 mov r3, r0 800334c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8003350: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8003354: d13c bne.n 80033d0 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003356: 2301 movs r3, #1 8003358: 627b str r3, [r7, #36] @ 0x24 800335a: e02b b.n 80033b4 { RegVal = USBx_INEP(epnum)->DIEPCTL; 800335c: 6a7b ldr r3, [r7, #36] @ 0x24 800335e: 015a lsls r2, r3, #5 8003360: 69fb ldr r3, [r7, #28] 8003362: 4413 add r3, r2 8003364: f503 6310 add.w r3, r3, #2304 @ 0x900 8003368: 681b ldr r3, [r3, #0] 800336a: 61bb str r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 800336c: 6879 ldr r1, [r7, #4] 800336e: 6a7a ldr r2, [r7, #36] @ 0x24 8003370: 4613 mov r3, r2 8003372: 00db lsls r3, r3, #3 8003374: 4413 add r3, r2 8003376: 009b lsls r3, r3, #2 8003378: 440b add r3, r1 800337a: 3318 adds r3, #24 800337c: 781b ldrb r3, [r3, #0] 800337e: 2b01 cmp r3, #1 8003380: d115 bne.n 80033ae ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) 8003382: 69bb ldr r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 8003384: 2b00 cmp r3, #0 8003386: da12 bge.n 80033ae { hpcd->IN_ep[epnum].is_iso_incomplete = 1U; 8003388: 6879 ldr r1, [r7, #4] 800338a: 6a7a ldr r2, [r7, #36] @ 0x24 800338c: 4613 mov r3, r2 800338e: 00db lsls r3, r3, #3 8003390: 4413 add r3, r2 8003392: 009b lsls r3, r3, #2 8003394: 440b add r3, r1 8003396: 3317 adds r3, #23 8003398: 2201 movs r2, #1 800339a: 701a strb r2, [r3, #0] /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); 800339c: 6a7b ldr r3, [r7, #36] @ 0x24 800339e: b2db uxtb r3, r3 80033a0: f063 037f orn r3, r3, #127 @ 0x7f 80033a4: b2db uxtb r3, r3 80033a6: 4619 mov r1, r3 80033a8: 6878 ldr r0, [r7, #4] 80033aa: f000 fab2 bl 8003912 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80033ae: 6a7b ldr r3, [r7, #36] @ 0x24 80033b0: 3301 adds r3, #1 80033b2: 627b str r3, [r7, #36] @ 0x24 80033b4: 687b ldr r3, [r7, #4] 80033b6: 791b ldrb r3, [r3, #4] 80033b8: 461a mov r2, r3 80033ba: 6a7b ldr r3, [r7, #36] @ 0x24 80033bc: 4293 cmp r3, r2 80033be: d3cd bcc.n 800335c } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); 80033c0: 687b ldr r3, [r7, #4] 80033c2: 681b ldr r3, [r3, #0] 80033c4: 695a ldr r2, [r3, #20] 80033c6: 687b ldr r3, [r7, #4] 80033c8: 681b ldr r3, [r3, #0] 80033ca: f402 1280 and.w r2, r2, #1048576 @ 0x100000 80033ce: 615a str r2, [r3, #20] } /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 80033d0: 687b ldr r3, [r7, #4] 80033d2: 681b ldr r3, [r3, #0] 80033d4: 4618 mov r0, r3 80033d6: f004 fca3 bl 8007d20 80033da: 4603 mov r3, r0 80033dc: f403 1300 and.w r3, r3, #2097152 @ 0x200000 80033e0: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80033e4: d156 bne.n 8003494 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80033e6: 2301 movs r3, #1 80033e8: 627b str r3, [r7, #36] @ 0x24 80033ea: e045 b.n 8003478 { RegVal = USBx_OUTEP(epnum)->DOEPCTL; 80033ec: 6a7b ldr r3, [r7, #36] @ 0x24 80033ee: 015a lsls r2, r3, #5 80033f0: 69fb ldr r3, [r7, #28] 80033f2: 4413 add r3, r2 80033f4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80033f8: 681b ldr r3, [r3, #0] 80033fa: 61bb str r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 80033fc: 6879 ldr r1, [r7, #4] 80033fe: 6a7a ldr r2, [r7, #36] @ 0x24 8003400: 4613 mov r3, r2 8003402: 00db lsls r3, r3, #3 8003404: 4413 add r3, r2 8003406: 009b lsls r3, r3, #2 8003408: 440b add r3, r1 800340a: f503 7316 add.w r3, r3, #600 @ 0x258 800340e: 781b ldrb r3, [r3, #0] 8003410: 2b01 cmp r3, #1 8003412: d12e bne.n 8003472 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 8003414: 69bb ldr r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 8003416: 2b00 cmp r3, #0 8003418: da2b bge.n 8003472 (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) 800341a: 69bb ldr r3, [r7, #24] 800341c: 0c1a lsrs r2, r3, #16 800341e: 687b ldr r3, [r7, #4] 8003420: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4 8003424: 4053 eors r3, r2 8003426: f003 0301 and.w r3, r3, #1 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 800342a: 2b00 cmp r3, #0 800342c: d121 bne.n 8003472 { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; 800342e: 6879 ldr r1, [r7, #4] 8003430: 6a7a ldr r2, [r7, #36] @ 0x24 8003432: 4613 mov r3, r2 8003434: 00db lsls r3, r3, #3 8003436: 4413 add r3, r2 8003438: 009b lsls r3, r3, #2 800343a: 440b add r3, r1 800343c: f203 2357 addw r3, r3, #599 @ 0x257 8003440: 2201 movs r2, #1 8003442: 701a strb r2, [r3, #0] USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; 8003444: 6a3b ldr r3, [r7, #32] 8003446: 699b ldr r3, [r3, #24] 8003448: f043 0280 orr.w r2, r3, #128 @ 0x80 800344c: 6a3b ldr r3, [r7, #32] 800344e: 619a str r2, [r3, #24] if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) 8003450: 6a3b ldr r3, [r7, #32] 8003452: 695b ldr r3, [r3, #20] 8003454: f003 0380 and.w r3, r3, #128 @ 0x80 8003458: 2b00 cmp r3, #0 800345a: d10a bne.n 8003472 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; 800345c: 69fb ldr r3, [r7, #28] 800345e: f503 6300 add.w r3, r3, #2048 @ 0x800 8003462: 685b ldr r3, [r3, #4] 8003464: 69fa ldr r2, [r7, #28] 8003466: f502 6200 add.w r2, r2, #2048 @ 0x800 800346a: f443 7300 orr.w r3, r3, #512 @ 0x200 800346e: 6053 str r3, [r2, #4] break; 8003470: e008 b.n 8003484 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003472: 6a7b ldr r3, [r7, #36] @ 0x24 8003474: 3301 adds r3, #1 8003476: 627b str r3, [r7, #36] @ 0x24 8003478: 687b ldr r3, [r7, #4] 800347a: 791b ldrb r3, [r3, #4] 800347c: 461a mov r2, r3 800347e: 6a7b ldr r3, [r7, #36] @ 0x24 8003480: 4293 cmp r3, r2 8003482: d3b3 bcc.n 80033ec } } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 8003484: 687b ldr r3, [r7, #4] 8003486: 681b ldr r3, [r3, #0] 8003488: 695a ldr r2, [r3, #20] 800348a: 687b ldr r3, [r7, #4] 800348c: 681b ldr r3, [r3, #0] 800348e: f402 1200 and.w r2, r2, #2097152 @ 0x200000 8003492: 615a str r2, [r3, #20] } /* Handle Connection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) 8003494: 687b ldr r3, [r7, #4] 8003496: 681b ldr r3, [r3, #0] 8003498: 4618 mov r0, r3 800349a: f004 fc41 bl 8007d20 800349e: 4603 mov r3, r0 80034a0: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 80034a4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80034a8: d10a bne.n 80034c0 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ConnectCallback(hpcd); #else HAL_PCD_ConnectCallback(hpcd); 80034aa: 6878 ldr r0, [r7, #4] 80034ac: f006 fd9c bl 8009fe8 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); 80034b0: 687b ldr r3, [r7, #4] 80034b2: 681b ldr r3, [r3, #0] 80034b4: 695a ldr r2, [r3, #20] 80034b6: 687b ldr r3, [r7, #4] 80034b8: 681b ldr r3, [r3, #0] 80034ba: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 80034be: 615a str r2, [r3, #20] } /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) 80034c0: 687b ldr r3, [r7, #4] 80034c2: 681b ldr r3, [r3, #0] 80034c4: 4618 mov r0, r3 80034c6: f004 fc2b bl 8007d20 80034ca: 4603 mov r3, r0 80034cc: f003 0304 and.w r3, r3, #4 80034d0: 2b04 cmp r3, #4 80034d2: d115 bne.n 8003500 { RegVal = hpcd->Instance->GOTGINT; 80034d4: 687b ldr r3, [r7, #4] 80034d6: 681b ldr r3, [r3, #0] 80034d8: 685b ldr r3, [r3, #4] 80034da: 61bb str r3, [r7, #24] if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) 80034dc: 69bb ldr r3, [r7, #24] 80034de: f003 0304 and.w r3, r3, #4 80034e2: 2b00 cmp r3, #0 80034e4: d002 beq.n 80034ec { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); #else HAL_PCD_DisconnectCallback(hpcd); 80034e6: 6878 ldr r0, [r7, #4] 80034e8: f006 fd8c bl 800a004 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= RegVal; 80034ec: 687b ldr r3, [r7, #4] 80034ee: 681b ldr r3, [r3, #0] 80034f0: 6859 ldr r1, [r3, #4] 80034f2: 687b ldr r3, [r7, #4] 80034f4: 681b ldr r3, [r3, #0] 80034f6: 69ba ldr r2, [r7, #24] 80034f8: 430a orrs r2, r1 80034fa: 605a str r2, [r3, #4] 80034fc: e000 b.n 8003500 return; 80034fe: bf00 nop } } } 8003500: 3734 adds r7, #52 @ 0x34 8003502: 46bd mov sp, r7 8003504: bd90 pop {r4, r7, pc} 08003506 : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 8003506: b580 push {r7, lr} 8003508: b082 sub sp, #8 800350a: af00 add r7, sp, #0 800350c: 6078 str r0, [r7, #4] 800350e: 460b mov r3, r1 8003510: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 8003512: 687b ldr r3, [r7, #4] 8003514: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003518: 2b01 cmp r3, #1 800351a: d101 bne.n 8003520 800351c: 2302 movs r3, #2 800351e: e012 b.n 8003546 8003520: 687b ldr r3, [r7, #4] 8003522: 2201 movs r2, #1 8003524: f883 2494 strb.w r2, [r3, #1172] @ 0x494 hpcd->USB_Address = address; 8003528: 687b ldr r3, [r7, #4] 800352a: 78fa ldrb r2, [r7, #3] 800352c: 745a strb r2, [r3, #17] (void)USB_SetDevAddress(hpcd->Instance, address); 800352e: 687b ldr r3, [r7, #4] 8003530: 681b ldr r3, [r3, #0] 8003532: 78fa ldrb r2, [r7, #3] 8003534: 4611 mov r1, r2 8003536: 4618 mov r0, r3 8003538: f004 fb8a bl 8007c50 __HAL_UNLOCK(hpcd); 800353c: 687b ldr r3, [r7, #4] 800353e: 2200 movs r2, #0 8003540: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003544: 2300 movs r3, #0 } 8003546: 4618 mov r0, r3 8003548: 3708 adds r7, #8 800354a: 46bd mov sp, r7 800354c: bd80 pop {r7, pc} 0800354e : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 800354e: b580 push {r7, lr} 8003550: b084 sub sp, #16 8003552: af00 add r7, sp, #0 8003554: 6078 str r0, [r7, #4] 8003556: 4608 mov r0, r1 8003558: 4611 mov r1, r2 800355a: 461a mov r2, r3 800355c: 4603 mov r3, r0 800355e: 70fb strb r3, [r7, #3] 8003560: 460b mov r3, r1 8003562: 803b strh r3, [r7, #0] 8003564: 4613 mov r3, r2 8003566: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 8003568: 2300 movs r3, #0 800356a: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 800356c: f997 3003 ldrsb.w r3, [r7, #3] 8003570: 2b00 cmp r3, #0 8003572: da0f bge.n 8003594 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003574: 78fb ldrb r3, [r7, #3] 8003576: f003 020f and.w r2, r3, #15 800357a: 4613 mov r3, r2 800357c: 00db lsls r3, r3, #3 800357e: 4413 add r3, r2 8003580: 009b lsls r3, r3, #2 8003582: 3310 adds r3, #16 8003584: 687a ldr r2, [r7, #4] 8003586: 4413 add r3, r2 8003588: 3304 adds r3, #4 800358a: 60fb str r3, [r7, #12] ep->is_in = 1U; 800358c: 68fb ldr r3, [r7, #12] 800358e: 2201 movs r2, #1 8003590: 705a strb r2, [r3, #1] 8003592: e00f b.n 80035b4 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003594: 78fb ldrb r3, [r7, #3] 8003596: f003 020f and.w r2, r3, #15 800359a: 4613 mov r3, r2 800359c: 00db lsls r3, r3, #3 800359e: 4413 add r3, r2 80035a0: 009b lsls r3, r3, #2 80035a2: f503 7314 add.w r3, r3, #592 @ 0x250 80035a6: 687a ldr r2, [r7, #4] 80035a8: 4413 add r3, r2 80035aa: 3304 adds r3, #4 80035ac: 60fb str r3, [r7, #12] ep->is_in = 0U; 80035ae: 68fb ldr r3, [r7, #12] 80035b0: 2200 movs r2, #0 80035b2: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 80035b4: 78fb ldrb r3, [r7, #3] 80035b6: f003 030f and.w r3, r3, #15 80035ba: b2da uxtb r2, r3 80035bc: 68fb ldr r3, [r7, #12] 80035be: 701a strb r2, [r3, #0] ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; 80035c0: 883b ldrh r3, [r7, #0] 80035c2: f3c3 020a ubfx r2, r3, #0, #11 80035c6: 68fb ldr r3, [r7, #12] 80035c8: 609a str r2, [r3, #8] ep->type = ep_type; 80035ca: 68fb ldr r3, [r7, #12] 80035cc: 78ba ldrb r2, [r7, #2] 80035ce: 711a strb r2, [r3, #4] if (ep->is_in != 0U) 80035d0: 68fb ldr r3, [r7, #12] 80035d2: 785b ldrb r3, [r3, #1] 80035d4: 2b00 cmp r3, #0 80035d6: d004 beq.n 80035e2 { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; 80035d8: 68fb ldr r3, [r7, #12] 80035da: 781b ldrb r3, [r3, #0] 80035dc: 461a mov r2, r3 80035de: 68fb ldr r3, [r7, #12] 80035e0: 835a strh r2, [r3, #26] } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 80035e2: 78bb ldrb r3, [r7, #2] 80035e4: 2b02 cmp r3, #2 80035e6: d102 bne.n 80035ee { ep->data_pid_start = 0U; 80035e8: 68fb ldr r3, [r7, #12] 80035ea: 2200 movs r2, #0 80035ec: 715a strb r2, [r3, #5] } __HAL_LOCK(hpcd); 80035ee: 687b ldr r3, [r7, #4] 80035f0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 80035f4: 2b01 cmp r3, #1 80035f6: d101 bne.n 80035fc 80035f8: 2302 movs r3, #2 80035fa: e00e b.n 800361a 80035fc: 687b ldr r3, [r7, #4] 80035fe: 2201 movs r2, #1 8003600: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_ActivateEndpoint(hpcd->Instance, ep); 8003604: 687b ldr r3, [r7, #4] 8003606: 681b ldr r3, [r3, #0] 8003608: 68f9 ldr r1, [r7, #12] 800360a: 4618 mov r0, r3 800360c: f003 fd0a bl 8007024 __HAL_UNLOCK(hpcd); 8003610: 687b ldr r3, [r7, #4] 8003612: 2200 movs r2, #0 8003614: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return ret; 8003618: 7afb ldrb r3, [r7, #11] } 800361a: 4618 mov r0, r3 800361c: 3710 adds r7, #16 800361e: 46bd mov sp, r7 8003620: bd80 pop {r7, pc} 08003622 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003622: b580 push {r7, lr} 8003624: b084 sub sp, #16 8003626: af00 add r7, sp, #0 8003628: 6078 str r0, [r7, #4] 800362a: 460b mov r3, r1 800362c: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 800362e: f997 3003 ldrsb.w r3, [r7, #3] 8003632: 2b00 cmp r3, #0 8003634: da0f bge.n 8003656 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003636: 78fb ldrb r3, [r7, #3] 8003638: f003 020f and.w r2, r3, #15 800363c: 4613 mov r3, r2 800363e: 00db lsls r3, r3, #3 8003640: 4413 add r3, r2 8003642: 009b lsls r3, r3, #2 8003644: 3310 adds r3, #16 8003646: 687a ldr r2, [r7, #4] 8003648: 4413 add r3, r2 800364a: 3304 adds r3, #4 800364c: 60fb str r3, [r7, #12] ep->is_in = 1U; 800364e: 68fb ldr r3, [r7, #12] 8003650: 2201 movs r2, #1 8003652: 705a strb r2, [r3, #1] 8003654: e00f b.n 8003676 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003656: 78fb ldrb r3, [r7, #3] 8003658: f003 020f and.w r2, r3, #15 800365c: 4613 mov r3, r2 800365e: 00db lsls r3, r3, #3 8003660: 4413 add r3, r2 8003662: 009b lsls r3, r3, #2 8003664: f503 7314 add.w r3, r3, #592 @ 0x250 8003668: 687a ldr r2, [r7, #4] 800366a: 4413 add r3, r2 800366c: 3304 adds r3, #4 800366e: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003670: 68fb ldr r3, [r7, #12] 8003672: 2200 movs r2, #0 8003674: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8003676: 78fb ldrb r3, [r7, #3] 8003678: f003 030f and.w r3, r3, #15 800367c: b2da uxtb r2, r3 800367e: 68fb ldr r3, [r7, #12] 8003680: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003682: 687b ldr r3, [r7, #4] 8003684: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003688: 2b01 cmp r3, #1 800368a: d101 bne.n 8003690 800368c: 2302 movs r3, #2 800368e: e00e b.n 80036ae 8003690: 687b ldr r3, [r7, #4] 8003692: 2201 movs r2, #1 8003694: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 8003698: 687b ldr r3, [r7, #4] 800369a: 681b ldr r3, [r3, #0] 800369c: 68f9 ldr r1, [r7, #12] 800369e: 4618 mov r0, r3 80036a0: f003 fd48 bl 8007134 __HAL_UNLOCK(hpcd); 80036a4: 687b ldr r3, [r7, #4] 80036a6: 2200 movs r2, #0 80036a8: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 80036ac: 2300 movs r3, #0 } 80036ae: 4618 mov r0, r3 80036b0: 3710 adds r7, #16 80036b2: 46bd mov sp, r7 80036b4: bd80 pop {r7, pc} 080036b6 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 80036b6: b580 push {r7, lr} 80036b8: b086 sub sp, #24 80036ba: af00 add r7, sp, #0 80036bc: 60f8 str r0, [r7, #12] 80036be: 607a str r2, [r7, #4] 80036c0: 603b str r3, [r7, #0] 80036c2: 460b mov r3, r1 80036c4: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80036c6: 7afb ldrb r3, [r7, #11] 80036c8: f003 020f and.w r2, r3, #15 80036cc: 4613 mov r3, r2 80036ce: 00db lsls r3, r3, #3 80036d0: 4413 add r3, r2 80036d2: 009b lsls r3, r3, #2 80036d4: f503 7314 add.w r3, r3, #592 @ 0x250 80036d8: 68fa ldr r2, [r7, #12] 80036da: 4413 add r3, r2 80036dc: 3304 adds r3, #4 80036de: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 80036e0: 697b ldr r3, [r7, #20] 80036e2: 687a ldr r2, [r7, #4] 80036e4: 60da str r2, [r3, #12] ep->xfer_len = len; 80036e6: 697b ldr r3, [r7, #20] 80036e8: 683a ldr r2, [r7, #0] 80036ea: 611a str r2, [r3, #16] ep->xfer_count = 0U; 80036ec: 697b ldr r3, [r7, #20] 80036ee: 2200 movs r2, #0 80036f0: 615a str r2, [r3, #20] ep->is_in = 0U; 80036f2: 697b ldr r3, [r7, #20] 80036f4: 2200 movs r2, #0 80036f6: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 80036f8: 7afb ldrb r3, [r7, #11] 80036fa: f003 030f and.w r3, r3, #15 80036fe: b2da uxtb r2, r3 8003700: 697b ldr r3, [r7, #20] 8003702: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003704: 68fb ldr r3, [r7, #12] 8003706: 799b ldrb r3, [r3, #6] 8003708: 2b01 cmp r3, #1 800370a: d102 bne.n 8003712 { ep->dma_addr = (uint32_t)pBuf; 800370c: 687a ldr r2, [r7, #4] 800370e: 697b ldr r3, [r7, #20] 8003710: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003712: 68fb ldr r3, [r7, #12] 8003714: 6818 ldr r0, [r3, #0] 8003716: 68fb ldr r3, [r7, #12] 8003718: 799b ldrb r3, [r3, #6] 800371a: 461a mov r2, r3 800371c: 6979 ldr r1, [r7, #20] 800371e: f003 fde5 bl 80072ec return HAL_OK; 8003722: 2300 movs r3, #0 } 8003724: 4618 mov r0, r3 8003726: 3718 adds r7, #24 8003728: 46bd mov sp, r7 800372a: bd80 pop {r7, pc} 0800372c : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 800372c: b580 push {r7, lr} 800372e: b086 sub sp, #24 8003730: af00 add r7, sp, #0 8003732: 60f8 str r0, [r7, #12] 8003734: 607a str r2, [r7, #4] 8003736: 603b str r3, [r7, #0] 8003738: 460b mov r3, r1 800373a: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800373c: 7afb ldrb r3, [r7, #11] 800373e: f003 020f and.w r2, r3, #15 8003742: 4613 mov r3, r2 8003744: 00db lsls r3, r3, #3 8003746: 4413 add r3, r2 8003748: 009b lsls r3, r3, #2 800374a: 3310 adds r3, #16 800374c: 68fa ldr r2, [r7, #12] 800374e: 4413 add r3, r2 8003750: 3304 adds r3, #4 8003752: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003754: 697b ldr r3, [r7, #20] 8003756: 687a ldr r2, [r7, #4] 8003758: 60da str r2, [r3, #12] ep->xfer_len = len; 800375a: 697b ldr r3, [r7, #20] 800375c: 683a ldr r2, [r7, #0] 800375e: 611a str r2, [r3, #16] ep->xfer_count = 0U; 8003760: 697b ldr r3, [r7, #20] 8003762: 2200 movs r2, #0 8003764: 615a str r2, [r3, #20] ep->is_in = 1U; 8003766: 697b ldr r3, [r7, #20] 8003768: 2201 movs r2, #1 800376a: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 800376c: 7afb ldrb r3, [r7, #11] 800376e: f003 030f and.w r3, r3, #15 8003772: b2da uxtb r2, r3 8003774: 697b ldr r3, [r7, #20] 8003776: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003778: 68fb ldr r3, [r7, #12] 800377a: 799b ldrb r3, [r3, #6] 800377c: 2b01 cmp r3, #1 800377e: d102 bne.n 8003786 { ep->dma_addr = (uint32_t)pBuf; 8003780: 687a ldr r2, [r7, #4] 8003782: 697b ldr r3, [r7, #20] 8003784: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003786: 68fb ldr r3, [r7, #12] 8003788: 6818 ldr r0, [r3, #0] 800378a: 68fb ldr r3, [r7, #12] 800378c: 799b ldrb r3, [r3, #6] 800378e: 461a mov r2, r3 8003790: 6979 ldr r1, [r7, #20] 8003792: f003 fdab bl 80072ec return HAL_OK; 8003796: 2300 movs r3, #0 } 8003798: 4618 mov r0, r3 800379a: 3718 adds r7, #24 800379c: 46bd mov sp, r7 800379e: bd80 pop {r7, pc} 080037a0 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 80037a0: b580 push {r7, lr} 80037a2: b084 sub sp, #16 80037a4: af00 add r7, sp, #0 80037a6: 6078 str r0, [r7, #4] 80037a8: 460b mov r3, r1 80037aa: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 80037ac: 78fb ldrb r3, [r7, #3] 80037ae: f003 030f and.w r3, r3, #15 80037b2: 687a ldr r2, [r7, #4] 80037b4: 7912 ldrb r2, [r2, #4] 80037b6: 4293 cmp r3, r2 80037b8: d901 bls.n 80037be { return HAL_ERROR; 80037ba: 2301 movs r3, #1 80037bc: e04f b.n 800385e } if ((0x80U & ep_addr) == 0x80U) 80037be: f997 3003 ldrsb.w r3, [r7, #3] 80037c2: 2b00 cmp r3, #0 80037c4: da0f bge.n 80037e6 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 80037c6: 78fb ldrb r3, [r7, #3] 80037c8: f003 020f and.w r2, r3, #15 80037cc: 4613 mov r3, r2 80037ce: 00db lsls r3, r3, #3 80037d0: 4413 add r3, r2 80037d2: 009b lsls r3, r3, #2 80037d4: 3310 adds r3, #16 80037d6: 687a ldr r2, [r7, #4] 80037d8: 4413 add r3, r2 80037da: 3304 adds r3, #4 80037dc: 60fb str r3, [r7, #12] ep->is_in = 1U; 80037de: 68fb ldr r3, [r7, #12] 80037e0: 2201 movs r2, #1 80037e2: 705a strb r2, [r3, #1] 80037e4: e00d b.n 8003802 } else { ep = &hpcd->OUT_ep[ep_addr]; 80037e6: 78fa ldrb r2, [r7, #3] 80037e8: 4613 mov r3, r2 80037ea: 00db lsls r3, r3, #3 80037ec: 4413 add r3, r2 80037ee: 009b lsls r3, r3, #2 80037f0: f503 7314 add.w r3, r3, #592 @ 0x250 80037f4: 687a ldr r2, [r7, #4] 80037f6: 4413 add r3, r2 80037f8: 3304 adds r3, #4 80037fa: 60fb str r3, [r7, #12] ep->is_in = 0U; 80037fc: 68fb ldr r3, [r7, #12] 80037fe: 2200 movs r2, #0 8003800: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8003802: 68fb ldr r3, [r7, #12] 8003804: 2201 movs r2, #1 8003806: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003808: 78fb ldrb r3, [r7, #3] 800380a: f003 030f and.w r3, r3, #15 800380e: b2da uxtb r2, r3 8003810: 68fb ldr r3, [r7, #12] 8003812: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003814: 687b ldr r3, [r7, #4] 8003816: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 800381a: 2b01 cmp r3, #1 800381c: d101 bne.n 8003822 800381e: 2302 movs r3, #2 8003820: e01d b.n 800385e 8003822: 687b ldr r3, [r7, #4] 8003824: 2201 movs r2, #1 8003826: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPSetStall(hpcd->Instance, ep); 800382a: 687b ldr r3, [r7, #4] 800382c: 681b ldr r3, [r3, #0] 800382e: 68f9 ldr r1, [r7, #12] 8003830: 4618 mov r0, r3 8003832: f004 f939 bl 8007aa8 if ((ep_addr & EP_ADDR_MSK) == 0U) 8003836: 78fb ldrb r3, [r7, #3] 8003838: f003 030f and.w r3, r3, #15 800383c: 2b00 cmp r3, #0 800383e: d109 bne.n 8003854 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); 8003840: 687b ldr r3, [r7, #4] 8003842: 6818 ldr r0, [r3, #0] 8003844: 687b ldr r3, [r7, #4] 8003846: 7999 ldrb r1, [r3, #6] 8003848: 687b ldr r3, [r7, #4] 800384a: f203 439c addw r3, r3, #1180 @ 0x49c 800384e: 461a mov r2, r3 8003850: f004 fb2a bl 8007ea8 } __HAL_UNLOCK(hpcd); 8003854: 687b ldr r3, [r7, #4] 8003856: 2200 movs r2, #0 8003858: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 800385c: 2300 movs r3, #0 } 800385e: 4618 mov r0, r3 8003860: 3710 adds r7, #16 8003862: 46bd mov sp, r7 8003864: bd80 pop {r7, pc} 08003866 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003866: b580 push {r7, lr} 8003868: b084 sub sp, #16 800386a: af00 add r7, sp, #0 800386c: 6078 str r0, [r7, #4] 800386e: 460b mov r3, r1 8003870: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8003872: 78fb ldrb r3, [r7, #3] 8003874: f003 030f and.w r3, r3, #15 8003878: 687a ldr r2, [r7, #4] 800387a: 7912 ldrb r2, [r2, #4] 800387c: 4293 cmp r3, r2 800387e: d901 bls.n 8003884 { return HAL_ERROR; 8003880: 2301 movs r3, #1 8003882: e042 b.n 800390a } if ((0x80U & ep_addr) == 0x80U) 8003884: f997 3003 ldrsb.w r3, [r7, #3] 8003888: 2b00 cmp r3, #0 800388a: da0f bge.n 80038ac { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800388c: 78fb ldrb r3, [r7, #3] 800388e: f003 020f and.w r2, r3, #15 8003892: 4613 mov r3, r2 8003894: 00db lsls r3, r3, #3 8003896: 4413 add r3, r2 8003898: 009b lsls r3, r3, #2 800389a: 3310 adds r3, #16 800389c: 687a ldr r2, [r7, #4] 800389e: 4413 add r3, r2 80038a0: 3304 adds r3, #4 80038a2: 60fb str r3, [r7, #12] ep->is_in = 1U; 80038a4: 68fb ldr r3, [r7, #12] 80038a6: 2201 movs r2, #1 80038a8: 705a strb r2, [r3, #1] 80038aa: e00f b.n 80038cc } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80038ac: 78fb ldrb r3, [r7, #3] 80038ae: f003 020f and.w r2, r3, #15 80038b2: 4613 mov r3, r2 80038b4: 00db lsls r3, r3, #3 80038b6: 4413 add r3, r2 80038b8: 009b lsls r3, r3, #2 80038ba: f503 7314 add.w r3, r3, #592 @ 0x250 80038be: 687a ldr r2, [r7, #4] 80038c0: 4413 add r3, r2 80038c2: 3304 adds r3, #4 80038c4: 60fb str r3, [r7, #12] ep->is_in = 0U; 80038c6: 68fb ldr r3, [r7, #12] 80038c8: 2200 movs r2, #0 80038ca: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 80038cc: 68fb ldr r3, [r7, #12] 80038ce: 2200 movs r2, #0 80038d0: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 80038d2: 78fb ldrb r3, [r7, #3] 80038d4: f003 030f and.w r3, r3, #15 80038d8: b2da uxtb r2, r3 80038da: 68fb ldr r3, [r7, #12] 80038dc: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 80038de: 687b ldr r3, [r7, #4] 80038e0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 80038e4: 2b01 cmp r3, #1 80038e6: d101 bne.n 80038ec 80038e8: 2302 movs r3, #2 80038ea: e00e b.n 800390a 80038ec: 687b ldr r3, [r7, #4] 80038ee: 2201 movs r2, #1 80038f0: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPClearStall(hpcd->Instance, ep); 80038f4: 687b ldr r3, [r7, #4] 80038f6: 681b ldr r3, [r3, #0] 80038f8: 68f9 ldr r1, [r7, #12] 80038fa: 4618 mov r0, r3 80038fc: f004 f942 bl 8007b84 __HAL_UNLOCK(hpcd); 8003900: 687b ldr r3, [r7, #4] 8003902: 2200 movs r2, #0 8003904: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003908: 2300 movs r3, #0 } 800390a: 4618 mov r0, r3 800390c: 3710 adds r7, #16 800390e: 46bd mov sp, r7 8003910: bd80 pop {r7, pc} 08003912 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003912: b580 push {r7, lr} 8003914: b084 sub sp, #16 8003916: af00 add r7, sp, #0 8003918: 6078 str r0, [r7, #4] 800391a: 460b mov r3, r1 800391c: 70fb strb r3, [r7, #3] HAL_StatusTypeDef ret; PCD_EPTypeDef *ep; if ((0x80U & ep_addr) == 0x80U) 800391e: f997 3003 ldrsb.w r3, [r7, #3] 8003922: 2b00 cmp r3, #0 8003924: da0c bge.n 8003940 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003926: 78fb ldrb r3, [r7, #3] 8003928: f003 020f and.w r2, r3, #15 800392c: 4613 mov r3, r2 800392e: 00db lsls r3, r3, #3 8003930: 4413 add r3, r2 8003932: 009b lsls r3, r3, #2 8003934: 3310 adds r3, #16 8003936: 687a ldr r2, [r7, #4] 8003938: 4413 add r3, r2 800393a: 3304 adds r3, #4 800393c: 60fb str r3, [r7, #12] 800393e: e00c b.n 800395a } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003940: 78fb ldrb r3, [r7, #3] 8003942: f003 020f and.w r2, r3, #15 8003946: 4613 mov r3, r2 8003948: 00db lsls r3, r3, #3 800394a: 4413 add r3, r2 800394c: 009b lsls r3, r3, #2 800394e: f503 7314 add.w r3, r3, #592 @ 0x250 8003952: 687a ldr r2, [r7, #4] 8003954: 4413 add r3, r2 8003956: 3304 adds r3, #4 8003958: 60fb str r3, [r7, #12] } /* Stop Xfer */ ret = USB_EPStopXfer(hpcd->Instance, ep); 800395a: 687b ldr r3, [r7, #4] 800395c: 681b ldr r3, [r3, #0] 800395e: 68f9 ldr r1, [r7, #12] 8003960: 4618 mov r0, r3 8003962: f003 ff61 bl 8007828 8003966: 4603 mov r3, r0 8003968: 72fb strb r3, [r7, #11] return ret; 800396a: 7afb ldrb r3, [r7, #11] } 800396c: 4618 mov r0, r3 800396e: 3710 adds r7, #16 8003970: 46bd mov sp, r7 8003972: bd80 pop {r7, pc} 08003974 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003974: b580 push {r7, lr} 8003976: b08a sub sp, #40 @ 0x28 8003978: af02 add r7, sp, #8 800397a: 6078 str r0, [r7, #4] 800397c: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 800397e: 687b ldr r3, [r7, #4] 8003980: 681b ldr r3, [r3, #0] 8003982: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003984: 697b ldr r3, [r7, #20] 8003986: 613b str r3, [r7, #16] USB_OTG_EPTypeDef *ep; uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; 8003988: 683a ldr r2, [r7, #0] 800398a: 4613 mov r3, r2 800398c: 00db lsls r3, r3, #3 800398e: 4413 add r3, r2 8003990: 009b lsls r3, r3, #2 8003992: 3310 adds r3, #16 8003994: 687a ldr r2, [r7, #4] 8003996: 4413 add r3, r2 8003998: 3304 adds r3, #4 800399a: 60fb str r3, [r7, #12] if (ep->xfer_count > ep->xfer_len) 800399c: 68fb ldr r3, [r7, #12] 800399e: 695a ldr r2, [r3, #20] 80039a0: 68fb ldr r3, [r7, #12] 80039a2: 691b ldr r3, [r3, #16] 80039a4: 429a cmp r2, r3 80039a6: d901 bls.n 80039ac { return HAL_ERROR; 80039a8: 2301 movs r3, #1 80039aa: e06b b.n 8003a84 } len = ep->xfer_len - ep->xfer_count; 80039ac: 68fb ldr r3, [r7, #12] 80039ae: 691a ldr r2, [r3, #16] 80039b0: 68fb ldr r3, [r7, #12] 80039b2: 695b ldr r3, [r3, #20] 80039b4: 1ad3 subs r3, r2, r3 80039b6: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 80039b8: 68fb ldr r3, [r7, #12] 80039ba: 689b ldr r3, [r3, #8] 80039bc: 69fa ldr r2, [r7, #28] 80039be: 429a cmp r2, r3 80039c0: d902 bls.n 80039c8 { len = ep->maxpacket; 80039c2: 68fb ldr r3, [r7, #12] 80039c4: 689b ldr r3, [r3, #8] 80039c6: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 80039c8: 69fb ldr r3, [r7, #28] 80039ca: 3303 adds r3, #3 80039cc: 089b lsrs r3, r3, #2 80039ce: 61bb str r3, [r7, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 80039d0: e02a b.n 8003a28 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; 80039d2: 68fb ldr r3, [r7, #12] 80039d4: 691a ldr r2, [r3, #16] 80039d6: 68fb ldr r3, [r7, #12] 80039d8: 695b ldr r3, [r3, #20] 80039da: 1ad3 subs r3, r2, r3 80039dc: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 80039de: 68fb ldr r3, [r7, #12] 80039e0: 689b ldr r3, [r3, #8] 80039e2: 69fa ldr r2, [r7, #28] 80039e4: 429a cmp r2, r3 80039e6: d902 bls.n 80039ee { len = ep->maxpacket; 80039e8: 68fb ldr r3, [r7, #12] 80039ea: 689b ldr r3, [r3, #8] 80039ec: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 80039ee: 69fb ldr r3, [r7, #28] 80039f0: 3303 adds r3, #3 80039f2: 089b lsrs r3, r3, #2 80039f4: 61bb str r3, [r7, #24] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 80039f6: 68fb ldr r3, [r7, #12] 80039f8: 68d9 ldr r1, [r3, #12] 80039fa: 683b ldr r3, [r7, #0] 80039fc: b2da uxtb r2, r3 80039fe: 69fb ldr r3, [r7, #28] 8003a00: b298 uxth r0, r3 (uint8_t)hpcd->Init.dma_enable); 8003a02: 687b ldr r3, [r7, #4] 8003a04: 799b ldrb r3, [r3, #6] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8003a06: 9300 str r3, [sp, #0] 8003a08: 4603 mov r3, r0 8003a0a: 6978 ldr r0, [r7, #20] 8003a0c: f003 ffb6 bl 800797c ep->xfer_buff += len; 8003a10: 68fb ldr r3, [r7, #12] 8003a12: 68da ldr r2, [r3, #12] 8003a14: 69fb ldr r3, [r7, #28] 8003a16: 441a add r2, r3 8003a18: 68fb ldr r3, [r7, #12] 8003a1a: 60da str r2, [r3, #12] ep->xfer_count += len; 8003a1c: 68fb ldr r3, [r7, #12] 8003a1e: 695a ldr r2, [r3, #20] 8003a20: 69fb ldr r3, [r7, #28] 8003a22: 441a add r2, r3 8003a24: 68fb ldr r3, [r7, #12] 8003a26: 615a str r2, [r3, #20] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003a28: 683b ldr r3, [r7, #0] 8003a2a: 015a lsls r2, r3, #5 8003a2c: 693b ldr r3, [r7, #16] 8003a2e: 4413 add r3, r2 8003a30: f503 6310 add.w r3, r3, #2304 @ 0x900 8003a34: 699b ldr r3, [r3, #24] 8003a36: b29b uxth r3, r3 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8003a38: 69ba ldr r2, [r7, #24] 8003a3a: 429a cmp r2, r3 8003a3c: d809 bhi.n 8003a52 8003a3e: 68fb ldr r3, [r7, #12] 8003a40: 695a ldr r2, [r3, #20] 8003a42: 68fb ldr r3, [r7, #12] 8003a44: 691b ldr r3, [r3, #16] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003a46: 429a cmp r2, r3 8003a48: d203 bcs.n 8003a52 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8003a4a: 68fb ldr r3, [r7, #12] 8003a4c: 691b ldr r3, [r3, #16] 8003a4e: 2b00 cmp r3, #0 8003a50: d1bf bne.n 80039d2 } if (ep->xfer_len <= ep->xfer_count) 8003a52: 68fb ldr r3, [r7, #12] 8003a54: 691a ldr r2, [r3, #16] 8003a56: 68fb ldr r3, [r7, #12] 8003a58: 695b ldr r3, [r3, #20] 8003a5a: 429a cmp r2, r3 8003a5c: d811 bhi.n 8003a82 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8003a5e: 683b ldr r3, [r7, #0] 8003a60: f003 030f and.w r3, r3, #15 8003a64: 2201 movs r2, #1 8003a66: fa02 f303 lsl.w r3, r2, r3 8003a6a: 60bb str r3, [r7, #8] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8003a6c: 693b ldr r3, [r7, #16] 8003a6e: f503 6300 add.w r3, r3, #2048 @ 0x800 8003a72: 6b5a ldr r2, [r3, #52] @ 0x34 8003a74: 68bb ldr r3, [r7, #8] 8003a76: 43db mvns r3, r3 8003a78: 6939 ldr r1, [r7, #16] 8003a7a: f501 6100 add.w r1, r1, #2048 @ 0x800 8003a7e: 4013 ands r3, r2 8003a80: 634b str r3, [r1, #52] @ 0x34 } return HAL_OK; 8003a82: 2300 movs r3, #0 } 8003a84: 4618 mov r0, r3 8003a86: 3720 adds r7, #32 8003a88: 46bd mov sp, r7 8003a8a: bd80 pop {r7, pc} 08003a8c : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003a8c: b580 push {r7, lr} 8003a8e: b088 sub sp, #32 8003a90: af00 add r7, sp, #0 8003a92: 6078 str r0, [r7, #4] 8003a94: 6039 str r1, [r7, #0] USB_OTG_EPTypeDef *ep; const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003a96: 687b ldr r3, [r7, #4] 8003a98: 681b ldr r3, [r3, #0] 8003a9a: 61fb str r3, [r7, #28] uint32_t USBx_BASE = (uint32_t)USBx; 8003a9c: 69fb ldr r3, [r7, #28] 8003a9e: 61bb str r3, [r7, #24] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8003aa0: 69fb ldr r3, [r7, #28] 8003aa2: 333c adds r3, #60 @ 0x3c 8003aa4: 3304 adds r3, #4 8003aa6: 681b ldr r3, [r3, #0] 8003aa8: 617b str r3, [r7, #20] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003aaa: 683b ldr r3, [r7, #0] 8003aac: 015a lsls r2, r3, #5 8003aae: 69bb ldr r3, [r7, #24] 8003ab0: 4413 add r3, r2 8003ab2: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003ab6: 689b ldr r3, [r3, #8] 8003ab8: 613b str r3, [r7, #16] if (hpcd->Init.dma_enable == 1U) 8003aba: 687b ldr r3, [r7, #4] 8003abc: 799b ldrb r3, [r3, #6] 8003abe: 2b01 cmp r3, #1 8003ac0: d17b bne.n 8003bba { if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ 8003ac2: 693b ldr r3, [r7, #16] 8003ac4: f003 0308 and.w r3, r3, #8 8003ac8: 2b00 cmp r3, #0 8003aca: d015 beq.n 8003af8 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003acc: 697b ldr r3, [r7, #20] 8003ace: 4a61 ldr r2, [pc, #388] @ (8003c54 ) 8003ad0: 4293 cmp r3, r2 8003ad2: f240 80b9 bls.w 8003c48 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003ad6: 693b ldr r3, [r7, #16] 8003ad8: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003adc: 2b00 cmp r3, #0 8003ade: f000 80b3 beq.w 8003c48 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003ae2: 683b ldr r3, [r7, #0] 8003ae4: 015a lsls r2, r3, #5 8003ae6: 69bb ldr r3, [r7, #24] 8003ae8: 4413 add r3, r2 8003aea: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003aee: 461a mov r2, r3 8003af0: f44f 4300 mov.w r3, #32768 @ 0x8000 8003af4: 6093 str r3, [r2, #8] 8003af6: e0a7 b.n 8003c48 } } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ 8003af8: 693b ldr r3, [r7, #16] 8003afa: f003 0320 and.w r3, r3, #32 8003afe: 2b00 cmp r3, #0 8003b00: d009 beq.n 8003b16 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003b02: 683b ldr r3, [r7, #0] 8003b04: 015a lsls r2, r3, #5 8003b06: 69bb ldr r3, [r7, #24] 8003b08: 4413 add r3, r2 8003b0a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003b0e: 461a mov r2, r3 8003b10: 2320 movs r3, #32 8003b12: 6093 str r3, [r2, #8] 8003b14: e098 b.n 8003c48 } else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) 8003b16: 693b ldr r3, [r7, #16] 8003b18: f003 0328 and.w r3, r3, #40 @ 0x28 8003b1c: 2b00 cmp r3, #0 8003b1e: f040 8093 bne.w 8003c48 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003b22: 697b ldr r3, [r7, #20] 8003b24: 4a4b ldr r2, [pc, #300] @ (8003c54 ) 8003b26: 4293 cmp r3, r2 8003b28: d90f bls.n 8003b4a ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003b2a: 693b ldr r3, [r7, #16] 8003b2c: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003b30: 2b00 cmp r3, #0 8003b32: d00a beq.n 8003b4a { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003b34: 683b ldr r3, [r7, #0] 8003b36: 015a lsls r2, r3, #5 8003b38: 69bb ldr r3, [r7, #24] 8003b3a: 4413 add r3, r2 8003b3c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003b40: 461a mov r2, r3 8003b42: f44f 4300 mov.w r3, #32768 @ 0x8000 8003b46: 6093 str r3, [r2, #8] 8003b48: e07e b.n 8003c48 } else { ep = &hpcd->OUT_ep[epnum]; 8003b4a: 683a ldr r2, [r7, #0] 8003b4c: 4613 mov r3, r2 8003b4e: 00db lsls r3, r3, #3 8003b50: 4413 add r3, r2 8003b52: 009b lsls r3, r3, #2 8003b54: f503 7314 add.w r3, r3, #592 @ 0x250 8003b58: 687a ldr r2, [r7, #4] 8003b5a: 4413 add r3, r2 8003b5c: 3304 adds r3, #4 8003b5e: 60fb str r3, [r7, #12] /* out data packet received over EP */ ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 8003b60: 68fb ldr r3, [r7, #12] 8003b62: 6a1a ldr r2, [r3, #32] 8003b64: 683b ldr r3, [r7, #0] 8003b66: 0159 lsls r1, r3, #5 8003b68: 69bb ldr r3, [r7, #24] 8003b6a: 440b add r3, r1 8003b6c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003b70: 691b ldr r3, [r3, #16] 8003b72: f3c3 0312 ubfx r3, r3, #0, #19 8003b76: 1ad2 subs r2, r2, r3 8003b78: 68fb ldr r3, [r7, #12] 8003b7a: 615a str r2, [r3, #20] if (epnum == 0U) 8003b7c: 683b ldr r3, [r7, #0] 8003b7e: 2b00 cmp r3, #0 8003b80: d114 bne.n 8003bac { if (ep->xfer_len == 0U) 8003b82: 68fb ldr r3, [r7, #12] 8003b84: 691b ldr r3, [r3, #16] 8003b86: 2b00 cmp r3, #0 8003b88: d109 bne.n 8003b9e { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003b8a: 687b ldr r3, [r7, #4] 8003b8c: 6818 ldr r0, [r3, #0] 8003b8e: 687b ldr r3, [r7, #4] 8003b90: f203 439c addw r3, r3, #1180 @ 0x49c 8003b94: 461a mov r2, r3 8003b96: 2101 movs r1, #1 8003b98: f004 f986 bl 8007ea8 8003b9c: e006 b.n 8003bac } else { ep->xfer_buff += ep->xfer_count; 8003b9e: 68fb ldr r3, [r7, #12] 8003ba0: 68da ldr r2, [r3, #12] 8003ba2: 68fb ldr r3, [r7, #12] 8003ba4: 695b ldr r3, [r3, #20] 8003ba6: 441a add r2, r3 8003ba8: 68fb ldr r3, [r7, #12] 8003baa: 60da str r2, [r3, #12] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003bac: 683b ldr r3, [r7, #0] 8003bae: b2db uxtb r3, r3 8003bb0: 4619 mov r1, r3 8003bb2: 6878 ldr r0, [r7, #4] 8003bb4: f006 f954 bl 8009e60 8003bb8: e046 b.n 8003c48 /* ... */ } } else { if (gSNPSiD == USB_OTG_CORE_ID_310A) 8003bba: 697b ldr r3, [r7, #20] 8003bbc: 4a26 ldr r2, [pc, #152] @ (8003c58 ) 8003bbe: 4293 cmp r3, r2 8003bc0: d124 bne.n 8003c0c { /* StupPktRcvd = 1 this is a setup packet */ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) 8003bc2: 693b ldr r3, [r7, #16] 8003bc4: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003bc8: 2b00 cmp r3, #0 8003bca: d00a beq.n 8003be2 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003bcc: 683b ldr r3, [r7, #0] 8003bce: 015a lsls r2, r3, #5 8003bd0: 69bb ldr r3, [r7, #24] 8003bd2: 4413 add r3, r2 8003bd4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003bd8: 461a mov r2, r3 8003bda: f44f 4300 mov.w r3, #32768 @ 0x8000 8003bde: 6093 str r3, [r2, #8] 8003be0: e032 b.n 8003c48 } else { if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8003be2: 693b ldr r3, [r7, #16] 8003be4: f003 0320 and.w r3, r3, #32 8003be8: 2b00 cmp r3, #0 8003bea: d008 beq.n 8003bfe { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003bec: 683b ldr r3, [r7, #0] 8003bee: 015a lsls r2, r3, #5 8003bf0: 69bb ldr r3, [r7, #24] 8003bf2: 4413 add r3, r2 8003bf4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003bf8: 461a mov r2, r3 8003bfa: 2320 movs r3, #32 8003bfc: 6093 str r3, [r2, #8] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003bfe: 683b ldr r3, [r7, #0] 8003c00: b2db uxtb r3, r3 8003c02: 4619 mov r1, r3 8003c04: 6878 ldr r0, [r7, #4] 8003c06: f006 f92b bl 8009e60 8003c0a: e01d b.n 8003c48 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else { if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8003c0c: 683b ldr r3, [r7, #0] 8003c0e: 2b00 cmp r3, #0 8003c10: d114 bne.n 8003c3c 8003c12: 6879 ldr r1, [r7, #4] 8003c14: 683a ldr r2, [r7, #0] 8003c16: 4613 mov r3, r2 8003c18: 00db lsls r3, r3, #3 8003c1a: 4413 add r3, r2 8003c1c: 009b lsls r3, r3, #2 8003c1e: 440b add r3, r1 8003c20: f503 7319 add.w r3, r3, #612 @ 0x264 8003c24: 681b ldr r3, [r3, #0] 8003c26: 2b00 cmp r3, #0 8003c28: d108 bne.n 8003c3c { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); 8003c2a: 687b ldr r3, [r7, #4] 8003c2c: 6818 ldr r0, [r3, #0] 8003c2e: 687b ldr r3, [r7, #4] 8003c30: f203 439c addw r3, r3, #1180 @ 0x49c 8003c34: 461a mov r2, r3 8003c36: 2100 movs r1, #0 8003c38: f004 f936 bl 8007ea8 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003c3c: 683b ldr r3, [r7, #0] 8003c3e: b2db uxtb r3, r3 8003c40: 4619 mov r1, r3 8003c42: 6878 ldr r0, [r7, #4] 8003c44: f006 f90c bl 8009e60 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } return HAL_OK; 8003c48: 2300 movs r3, #0 } 8003c4a: 4618 mov r0, r3 8003c4c: 3720 adds r7, #32 8003c4e: 46bd mov sp, r7 8003c50: bd80 pop {r7, pc} 8003c52: bf00 nop 8003c54: 4f54300a .word 0x4f54300a 8003c58: 4f54310a .word 0x4f54310a 08003c5c : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003c5c: b580 push {r7, lr} 8003c5e: b086 sub sp, #24 8003c60: af00 add r7, sp, #0 8003c62: 6078 str r0, [r7, #4] 8003c64: 6039 str r1, [r7, #0] const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003c66: 687b ldr r3, [r7, #4] 8003c68: 681b ldr r3, [r3, #0] 8003c6a: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003c6c: 697b ldr r3, [r7, #20] 8003c6e: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8003c70: 697b ldr r3, [r7, #20] 8003c72: 333c adds r3, #60 @ 0x3c 8003c74: 3304 adds r3, #4 8003c76: 681b ldr r3, [r3, #0] 8003c78: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003c7a: 683b ldr r3, [r7, #0] 8003c7c: 015a lsls r2, r3, #5 8003c7e: 693b ldr r3, [r7, #16] 8003c80: 4413 add r3, r2 8003c82: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003c86: 689b ldr r3, [r3, #8] 8003c88: 60bb str r3, [r7, #8] if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003c8a: 68fb ldr r3, [r7, #12] 8003c8c: 4a15 ldr r2, [pc, #84] @ (8003ce4 ) 8003c8e: 4293 cmp r3, r2 8003c90: d90e bls.n 8003cb0 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003c92: 68bb ldr r3, [r7, #8] 8003c94: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003c98: 2b00 cmp r3, #0 8003c9a: d009 beq.n 8003cb0 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003c9c: 683b ldr r3, [r7, #0] 8003c9e: 015a lsls r2, r3, #5 8003ca0: 693b ldr r3, [r7, #16] 8003ca2: 4413 add r3, r2 8003ca4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003ca8: 461a mov r2, r3 8003caa: f44f 4300 mov.w r3, #32768 @ 0x8000 8003cae: 6093 str r3, [r2, #8] /* Inform the upper layer that a setup packet is available */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 8003cb0: 6878 ldr r0, [r7, #4] 8003cb2: f006 f8c3 bl 8009e3c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) 8003cb6: 68fb ldr r3, [r7, #12] 8003cb8: 4a0a ldr r2, [pc, #40] @ (8003ce4 ) 8003cba: 4293 cmp r3, r2 8003cbc: d90c bls.n 8003cd8 8003cbe: 687b ldr r3, [r7, #4] 8003cc0: 799b ldrb r3, [r3, #6] 8003cc2: 2b01 cmp r3, #1 8003cc4: d108 bne.n 8003cd8 { (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003cc6: 687b ldr r3, [r7, #4] 8003cc8: 6818 ldr r0, [r3, #0] 8003cca: 687b ldr r3, [r7, #4] 8003ccc: f203 439c addw r3, r3, #1180 @ 0x49c 8003cd0: 461a mov r2, r3 8003cd2: 2101 movs r1, #1 8003cd4: f004 f8e8 bl 8007ea8 } return HAL_OK; 8003cd8: 2300 movs r3, #0 } 8003cda: 4618 mov r0, r3 8003cdc: 3718 adds r7, #24 8003cde: 46bd mov sp, r7 8003ce0: bd80 pop {r7, pc} 8003ce2: bf00 nop 8003ce4: 4f54300a .word 0x4f54300a 08003ce8 : * @param fifo The number of Tx fifo * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { 8003ce8: b480 push {r7} 8003cea: b085 sub sp, #20 8003cec: af00 add r7, sp, #0 8003cee: 6078 str r0, [r7, #4] 8003cf0: 460b mov r3, r1 8003cf2: 70fb strb r3, [r7, #3] 8003cf4: 4613 mov r3, r2 8003cf6: 803b strh r3, [r7, #0] --> Txn should be configured with the minimum space of 16 words The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ Tx_Offset = hpcd->Instance->GRXFSIZ; 8003cf8: 687b ldr r3, [r7, #4] 8003cfa: 681b ldr r3, [r3, #0] 8003cfc: 6a5b ldr r3, [r3, #36] @ 0x24 8003cfe: 60bb str r3, [r7, #8] if (fifo == 0U) 8003d00: 78fb ldrb r3, [r7, #3] 8003d02: 2b00 cmp r3, #0 8003d04: d107 bne.n 8003d16 { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; 8003d06: 883b ldrh r3, [r7, #0] 8003d08: 0419 lsls r1, r3, #16 8003d0a: 687b ldr r3, [r7, #4] 8003d0c: 681b ldr r3, [r3, #0] 8003d0e: 68ba ldr r2, [r7, #8] 8003d10: 430a orrs r2, r1 8003d12: 629a str r2, [r3, #40] @ 0x28 8003d14: e028 b.n 8003d68 } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; 8003d16: 687b ldr r3, [r7, #4] 8003d18: 681b ldr r3, [r3, #0] 8003d1a: 6a9b ldr r3, [r3, #40] @ 0x28 8003d1c: 0c1b lsrs r3, r3, #16 8003d1e: 68ba ldr r2, [r7, #8] 8003d20: 4413 add r3, r2 8003d22: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8003d24: 2300 movs r3, #0 8003d26: 73fb strb r3, [r7, #15] 8003d28: e00d b.n 8003d46 { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); 8003d2a: 687b ldr r3, [r7, #4] 8003d2c: 681a ldr r2, [r3, #0] 8003d2e: 7bfb ldrb r3, [r7, #15] 8003d30: 3340 adds r3, #64 @ 0x40 8003d32: 009b lsls r3, r3, #2 8003d34: 4413 add r3, r2 8003d36: 685b ldr r3, [r3, #4] 8003d38: 0c1b lsrs r3, r3, #16 8003d3a: 68ba ldr r2, [r7, #8] 8003d3c: 4413 add r3, r2 8003d3e: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8003d40: 7bfb ldrb r3, [r7, #15] 8003d42: 3301 adds r3, #1 8003d44: 73fb strb r3, [r7, #15] 8003d46: 7bfa ldrb r2, [r7, #15] 8003d48: 78fb ldrb r3, [r7, #3] 8003d4a: 3b01 subs r3, #1 8003d4c: 429a cmp r2, r3 8003d4e: d3ec bcc.n 8003d2a } /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; 8003d50: 883b ldrh r3, [r7, #0] 8003d52: 0418 lsls r0, r3, #16 8003d54: 687b ldr r3, [r7, #4] 8003d56: 6819 ldr r1, [r3, #0] 8003d58: 78fb ldrb r3, [r7, #3] 8003d5a: 3b01 subs r3, #1 8003d5c: 68ba ldr r2, [r7, #8] 8003d5e: 4302 orrs r2, r0 8003d60: 3340 adds r3, #64 @ 0x40 8003d62: 009b lsls r3, r3, #2 8003d64: 440b add r3, r1 8003d66: 605a str r2, [r3, #4] } return HAL_OK; 8003d68: 2300 movs r3, #0 } 8003d6a: 4618 mov r0, r3 8003d6c: 3714 adds r7, #20 8003d6e: 46bd mov sp, r7 8003d70: f85d 7b04 ldr.w r7, [sp], #4 8003d74: 4770 bx lr 08003d76 : * @param hpcd PCD handle * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { 8003d76: b480 push {r7} 8003d78: b083 sub sp, #12 8003d7a: af00 add r7, sp, #0 8003d7c: 6078 str r0, [r7, #4] 8003d7e: 460b mov r3, r1 8003d80: 807b strh r3, [r7, #2] hpcd->Instance->GRXFSIZ = size; 8003d82: 687b ldr r3, [r7, #4] 8003d84: 681b ldr r3, [r3, #0] 8003d86: 887a ldrh r2, [r7, #2] 8003d88: 625a str r2, [r3, #36] @ 0x24 return HAL_OK; 8003d8a: 2300 movs r3, #0 } 8003d8c: 4618 mov r0, r3 8003d8e: 370c adds r7, #12 8003d90: 46bd mov sp, r7 8003d92: f85d 7b04 ldr.w r7, [sp], #4 8003d96: 4770 bx lr 08003d98 : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 8003d98: b480 push {r7} 8003d9a: b085 sub sp, #20 8003d9c: af00 add r7, sp, #0 8003d9e: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003da0: 687b ldr r3, [r7, #4] 8003da2: 681b ldr r3, [r3, #0] 8003da4: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 8003da6: 687b ldr r3, [r7, #4] 8003da8: 2201 movs r2, #1 8003daa: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8 hpcd->LPM_State = LPM_L0; 8003dae: 687b ldr r3, [r7, #4] 8003db0: 2200 movs r2, #0 8003db2: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 8003db6: 68fb ldr r3, [r7, #12] 8003db8: 699b ldr r3, [r3, #24] 8003dba: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 8003dbe: 68fb ldr r3, [r7, #12] 8003dc0: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 8003dc2: 68fb ldr r3, [r7, #12] 8003dc4: 6d5b ldr r3, [r3, #84] @ 0x54 8003dc6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003dca: f043 0303 orr.w r3, r3, #3 8003dce: 68fa ldr r2, [r7, #12] 8003dd0: 6553 str r3, [r2, #84] @ 0x54 return HAL_OK; 8003dd2: 2300 movs r3, #0 } 8003dd4: 4618 mov r0, r3 8003dd6: 3714 adds r7, #20 8003dd8: 46bd mov sp, r7 8003dda: f85d 7b04 ldr.w r7, [sp], #4 8003dde: 4770 bx lr 08003de0 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003de0: b580 push {r7, lr} 8003de2: b084 sub sp, #16 8003de4: af00 add r7, sp, #0 8003de6: 6078 str r0, [r7, #4] 8003de8: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8003dea: 687b ldr r3, [r7, #4] 8003dec: 2b00 cmp r3, #0 8003dee: d101 bne.n 8003df4 { return HAL_ERROR; 8003df0: 2301 movs r3, #1 8003df2: e0cc b.n 8003f8e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8003df4: 4b68 ldr r3, [pc, #416] @ (8003f98 ) 8003df6: 681b ldr r3, [r3, #0] 8003df8: f003 030f and.w r3, r3, #15 8003dfc: 683a ldr r2, [r7, #0] 8003dfe: 429a cmp r2, r3 8003e00: d90c bls.n 8003e1c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003e02: 4b65 ldr r3, [pc, #404] @ (8003f98 ) 8003e04: 683a ldr r2, [r7, #0] 8003e06: b2d2 uxtb r2, r2 8003e08: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8003e0a: 4b63 ldr r3, [pc, #396] @ (8003f98 ) 8003e0c: 681b ldr r3, [r3, #0] 8003e0e: f003 030f and.w r3, r3, #15 8003e12: 683a ldr r2, [r7, #0] 8003e14: 429a cmp r2, r3 8003e16: d001 beq.n 8003e1c { return HAL_ERROR; 8003e18: 2301 movs r3, #1 8003e1a: e0b8 b.n 8003f8e } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003e1c: 687b ldr r3, [r7, #4] 8003e1e: 681b ldr r3, [r3, #0] 8003e20: f003 0302 and.w r3, r3, #2 8003e24: 2b00 cmp r3, #0 8003e26: d020 beq.n 8003e6a { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003e28: 687b ldr r3, [r7, #4] 8003e2a: 681b ldr r3, [r3, #0] 8003e2c: f003 0304 and.w r3, r3, #4 8003e30: 2b00 cmp r3, #0 8003e32: d005 beq.n 8003e40 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8003e34: 4b59 ldr r3, [pc, #356] @ (8003f9c ) 8003e36: 689b ldr r3, [r3, #8] 8003e38: 4a58 ldr r2, [pc, #352] @ (8003f9c ) 8003e3a: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 8003e3e: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003e40: 687b ldr r3, [r7, #4] 8003e42: 681b ldr r3, [r3, #0] 8003e44: f003 0308 and.w r3, r3, #8 8003e48: 2b00 cmp r3, #0 8003e4a: d005 beq.n 8003e58 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8003e4c: 4b53 ldr r3, [pc, #332] @ (8003f9c ) 8003e4e: 689b ldr r3, [r3, #8] 8003e50: 4a52 ldr r2, [pc, #328] @ (8003f9c ) 8003e52: f443 4360 orr.w r3, r3, #57344 @ 0xe000 8003e56: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003e58: 4b50 ldr r3, [pc, #320] @ (8003f9c ) 8003e5a: 689b ldr r3, [r3, #8] 8003e5c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8003e60: 687b ldr r3, [r7, #4] 8003e62: 689b ldr r3, [r3, #8] 8003e64: 494d ldr r1, [pc, #308] @ (8003f9c ) 8003e66: 4313 orrs r3, r2 8003e68: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003e6a: 687b ldr r3, [r7, #4] 8003e6c: 681b ldr r3, [r3, #0] 8003e6e: f003 0301 and.w r3, r3, #1 8003e72: 2b00 cmp r3, #0 8003e74: d044 beq.n 8003f00 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8003e76: 687b ldr r3, [r7, #4] 8003e78: 685b ldr r3, [r3, #4] 8003e7a: 2b01 cmp r3, #1 8003e7c: d107 bne.n 8003e8e { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003e7e: 4b47 ldr r3, [pc, #284] @ (8003f9c ) 8003e80: 681b ldr r3, [r3, #0] 8003e82: f403 3300 and.w r3, r3, #131072 @ 0x20000 8003e86: 2b00 cmp r3, #0 8003e88: d119 bne.n 8003ebe { return HAL_ERROR; 8003e8a: 2301 movs r3, #1 8003e8c: e07f b.n 8003f8e } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 8003e8e: 687b ldr r3, [r7, #4] 8003e90: 685b ldr r3, [r3, #4] 8003e92: 2b02 cmp r3, #2 8003e94: d003 beq.n 8003e9e (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 8003e96: 687b ldr r3, [r7, #4] 8003e98: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 8003e9a: 2b03 cmp r3, #3 8003e9c: d107 bne.n 8003eae { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8003e9e: 4b3f ldr r3, [pc, #252] @ (8003f9c ) 8003ea0: 681b ldr r3, [r3, #0] 8003ea2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8003ea6: 2b00 cmp r3, #0 8003ea8: d109 bne.n 8003ebe { return HAL_ERROR; 8003eaa: 2301 movs r3, #1 8003eac: e06f b.n 8003f8e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003eae: 4b3b ldr r3, [pc, #236] @ (8003f9c ) 8003eb0: 681b ldr r3, [r3, #0] 8003eb2: f003 0302 and.w r3, r3, #2 8003eb6: 2b00 cmp r3, #0 8003eb8: d101 bne.n 8003ebe { return HAL_ERROR; 8003eba: 2301 movs r3, #1 8003ebc: e067 b.n 8003f8e } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8003ebe: 4b37 ldr r3, [pc, #220] @ (8003f9c ) 8003ec0: 689b ldr r3, [r3, #8] 8003ec2: f023 0203 bic.w r2, r3, #3 8003ec6: 687b ldr r3, [r7, #4] 8003ec8: 685b ldr r3, [r3, #4] 8003eca: 4934 ldr r1, [pc, #208] @ (8003f9c ) 8003ecc: 4313 orrs r3, r2 8003ece: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003ed0: f7fd fcb2 bl 8001838 8003ed4: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003ed6: e00a b.n 8003eee { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003ed8: f7fd fcae bl 8001838 8003edc: 4602 mov r2, r0 8003ede: 68fb ldr r3, [r7, #12] 8003ee0: 1ad3 subs r3, r2, r3 8003ee2: f241 3288 movw r2, #5000 @ 0x1388 8003ee6: 4293 cmp r3, r2 8003ee8: d901 bls.n 8003eee { return HAL_TIMEOUT; 8003eea: 2303 movs r3, #3 8003eec: e04f b.n 8003f8e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003eee: 4b2b ldr r3, [pc, #172] @ (8003f9c ) 8003ef0: 689b ldr r3, [r3, #8] 8003ef2: f003 020c and.w r2, r3, #12 8003ef6: 687b ldr r3, [r7, #4] 8003ef8: 685b ldr r3, [r3, #4] 8003efa: 009b lsls r3, r3, #2 8003efc: 429a cmp r2, r3 8003efe: d1eb bne.n 8003ed8 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8003f00: 4b25 ldr r3, [pc, #148] @ (8003f98 ) 8003f02: 681b ldr r3, [r3, #0] 8003f04: f003 030f and.w r3, r3, #15 8003f08: 683a ldr r2, [r7, #0] 8003f0a: 429a cmp r2, r3 8003f0c: d20c bcs.n 8003f28 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003f0e: 4b22 ldr r3, [pc, #136] @ (8003f98 ) 8003f10: 683a ldr r2, [r7, #0] 8003f12: b2d2 uxtb r2, r2 8003f14: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8003f16: 4b20 ldr r3, [pc, #128] @ (8003f98 ) 8003f18: 681b ldr r3, [r3, #0] 8003f1a: f003 030f and.w r3, r3, #15 8003f1e: 683a ldr r2, [r7, #0] 8003f20: 429a cmp r2, r3 8003f22: d001 beq.n 8003f28 { return HAL_ERROR; 8003f24: 2301 movs r3, #1 8003f26: e032 b.n 8003f8e } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003f28: 687b ldr r3, [r7, #4] 8003f2a: 681b ldr r3, [r3, #0] 8003f2c: f003 0304 and.w r3, r3, #4 8003f30: 2b00 cmp r3, #0 8003f32: d008 beq.n 8003f46 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8003f34: 4b19 ldr r3, [pc, #100] @ (8003f9c ) 8003f36: 689b ldr r3, [r3, #8] 8003f38: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 8003f3c: 687b ldr r3, [r7, #4] 8003f3e: 68db ldr r3, [r3, #12] 8003f40: 4916 ldr r1, [pc, #88] @ (8003f9c ) 8003f42: 4313 orrs r3, r2 8003f44: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003f46: 687b ldr r3, [r7, #4] 8003f48: 681b ldr r3, [r3, #0] 8003f4a: f003 0308 and.w r3, r3, #8 8003f4e: 2b00 cmp r3, #0 8003f50: d009 beq.n 8003f66 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8003f52: 4b12 ldr r3, [pc, #72] @ (8003f9c ) 8003f54: 689b ldr r3, [r3, #8] 8003f56: f423 4260 bic.w r2, r3, #57344 @ 0xe000 8003f5a: 687b ldr r3, [r7, #4] 8003f5c: 691b ldr r3, [r3, #16] 8003f5e: 00db lsls r3, r3, #3 8003f60: 490e ldr r1, [pc, #56] @ (8003f9c ) 8003f62: 4313 orrs r3, r2 8003f64: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8003f66: f000 fb7f bl 8004668 8003f6a: 4602 mov r2, r0 8003f6c: 4b0b ldr r3, [pc, #44] @ (8003f9c ) 8003f6e: 689b ldr r3, [r3, #8] 8003f70: 091b lsrs r3, r3, #4 8003f72: f003 030f and.w r3, r3, #15 8003f76: 490a ldr r1, [pc, #40] @ (8003fa0 ) 8003f78: 5ccb ldrb r3, [r1, r3] 8003f7a: fa22 f303 lsr.w r3, r2, r3 8003f7e: 4a09 ldr r2, [pc, #36] @ (8003fa4 ) 8003f80: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); 8003f82: 4b09 ldr r3, [pc, #36] @ (8003fa8 ) 8003f84: 681b ldr r3, [r3, #0] 8003f86: 4618 mov r0, r3 8003f88: f7fd fc12 bl 80017b0 return HAL_OK; 8003f8c: 2300 movs r3, #0 } 8003f8e: 4618 mov r0, r3 8003f90: 3710 adds r7, #16 8003f92: 46bd mov sp, r7 8003f94: bd80 pop {r7, pc} 8003f96: bf00 nop 8003f98: 40023c00 .word 0x40023c00 8003f9c: 40023800 .word 0x40023800 8003fa0: 0800a4e0 .word 0x0800a4e0 8003fa4: 20000090 .word 0x20000090 8003fa8: 20000094 .word 0x20000094 08003fac : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8003fac: b480 push {r7} 8003fae: af00 add r7, sp, #0 return SystemCoreClock; 8003fb0: 4b03 ldr r3, [pc, #12] @ (8003fc0 ) 8003fb2: 681b ldr r3, [r3, #0] } 8003fb4: 4618 mov r0, r3 8003fb6: 46bd mov sp, r7 8003fb8: f85d 7b04 ldr.w r7, [sp], #4 8003fbc: 4770 bx lr 8003fbe: bf00 nop 8003fc0: 20000090 .word 0x20000090 08003fc4 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8003fc4: b580 push {r7, lr} 8003fc6: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8003fc8: f7ff fff0 bl 8003fac 8003fcc: 4602 mov r2, r0 8003fce: 4b05 ldr r3, [pc, #20] @ (8003fe4 ) 8003fd0: 689b ldr r3, [r3, #8] 8003fd2: 0a9b lsrs r3, r3, #10 8003fd4: f003 0307 and.w r3, r3, #7 8003fd8: 4903 ldr r1, [pc, #12] @ (8003fe8 ) 8003fda: 5ccb ldrb r3, [r1, r3] 8003fdc: fa22 f303 lsr.w r3, r2, r3 } 8003fe0: 4618 mov r0, r3 8003fe2: bd80 pop {r7, pc} 8003fe4: 40023800 .word 0x40023800 8003fe8: 0800a4f0 .word 0x0800a4f0 08003fec : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8003fec: b580 push {r7, lr} 8003fee: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8003ff0: f7ff ffdc bl 8003fac 8003ff4: 4602 mov r2, r0 8003ff6: 4b05 ldr r3, [pc, #20] @ (800400c ) 8003ff8: 689b ldr r3, [r3, #8] 8003ffa: 0b5b lsrs r3, r3, #13 8003ffc: f003 0307 and.w r3, r3, #7 8004000: 4903 ldr r1, [pc, #12] @ (8004010 ) 8004002: 5ccb ldrb r3, [r1, r3] 8004004: fa22 f303 lsr.w r3, r2, r3 } 8004008: 4618 mov r0, r3 800400a: bd80 pop {r7, pc} 800400c: 40023800 .word 0x40023800 8004010: 0800a4f0 .word 0x0800a4f0 08004014 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8004014: b580 push {r7, lr} 8004016: b08c sub sp, #48 @ 0x30 8004018: af00 add r7, sp, #0 800401a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800401c: 2300 movs r3, #0 800401e: 627b str r3, [r7, #36] @ 0x24 uint32_t tmpreg1 = 0U; 8004020: 2300 movs r3, #0 8004022: 623b str r3, [r7, #32] uint32_t plli2sp = 0U; 8004024: 2300 movs r3, #0 8004026: 61fb str r3, [r7, #28] uint32_t plli2sq = 0U; 8004028: 2300 movs r3, #0 800402a: 61bb str r3, [r7, #24] uint32_t plli2sr = 0U; 800402c: 2300 movs r3, #0 800402e: 617b str r3, [r7, #20] uint32_t pllsaip = 0U; 8004030: 2300 movs r3, #0 8004032: 613b str r3, [r7, #16] uint32_t pllsaiq = 0U; 8004034: 2300 movs r3, #0 8004036: 60fb str r3, [r7, #12] uint32_t plli2sused = 0U; 8004038: 2300 movs r3, #0 800403a: 62fb str r3, [r7, #44] @ 0x2c uint32_t pllsaiused = 0U; 800403c: 2300 movs r3, #0 800403e: 62bb str r3, [r7, #40] @ 0x28 /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------ I2S APB1 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) 8004040: 687b ldr r3, [r7, #4] 8004042: 681b ldr r3, [r3, #0] 8004044: f003 0301 and.w r3, r3, #1 8004048: 2b00 cmp r3, #0 800404a: d010 beq.n 800406e { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); 800404c: 4b6f ldr r3, [pc, #444] @ (800420c ) 800404e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004052: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000 8004056: 687b ldr r3, [r7, #4] 8004058: 6b9b ldr r3, [r3, #56] @ 0x38 800405a: 496c ldr r1, [pc, #432] @ (800420c ) 800405c: 4313 orrs r3, r2 800405e: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) 8004062: 687b ldr r3, [r7, #4] 8004064: 6b9b ldr r3, [r3, #56] @ 0x38 8004066: 2b00 cmp r3, #0 8004068: d101 bne.n 800406e { plli2sused = 1U; 800406a: 2301 movs r3, #1 800406c: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*---------------------------- I2S APB2 configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) 800406e: 687b ldr r3, [r7, #4] 8004070: 681b ldr r3, [r3, #0] 8004072: f003 0302 and.w r3, r3, #2 8004076: 2b00 cmp r3, #0 8004078: d010 beq.n 800409c { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); 800407a: 4b64 ldr r3, [pc, #400] @ (800420c ) 800407c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004080: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000 8004084: 687b ldr r3, [r7, #4] 8004086: 6bdb ldr r3, [r3, #60] @ 0x3c 8004088: 4960 ldr r1, [pc, #384] @ (800420c ) 800408a: 4313 orrs r3, r2 800408c: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) 8004090: 687b ldr r3, [r7, #4] 8004092: 6bdb ldr r3, [r3, #60] @ 0x3c 8004094: 2b00 cmp r3, #0 8004096: d101 bne.n 800409c { plli2sused = 1U; 8004098: 2301 movs r3, #1 800409a: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*--------------------------- SAI1 configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) 800409c: 687b ldr r3, [r7, #4] 800409e: 681b ldr r3, [r3, #0] 80040a0: f003 0304 and.w r3, r3, #4 80040a4: 2b00 cmp r3, #0 80040a6: d017 beq.n 80040d8 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 80040a8: 4b58 ldr r3, [pc, #352] @ (800420c ) 80040aa: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80040ae: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 80040b2: 687b ldr r3, [r7, #4] 80040b4: 6b1b ldr r3, [r3, #48] @ 0x30 80040b6: 4955 ldr r1, [pc, #340] @ (800420c ) 80040b8: 4313 orrs r3, r2 80040ba: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) 80040be: 687b ldr r3, [r7, #4] 80040c0: 6b1b ldr r3, [r3, #48] @ 0x30 80040c2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80040c6: d101 bne.n 80040cc { plli2sused = 1U; 80040c8: 2301 movs r3, #1 80040ca: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) 80040cc: 687b ldr r3, [r7, #4] 80040ce: 6b1b ldr r3, [r3, #48] @ 0x30 80040d0: 2b00 cmp r3, #0 80040d2: d101 bne.n 80040d8 { pllsaiused = 1U; 80040d4: 2301 movs r3, #1 80040d6: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*-------------------------- SAI2 configuration ----------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) 80040d8: 687b ldr r3, [r7, #4] 80040da: 681b ldr r3, [r3, #0] 80040dc: f003 0308 and.w r3, r3, #8 80040e0: 2b00 cmp r3, #0 80040e2: d017 beq.n 8004114 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 80040e4: 4b49 ldr r3, [pc, #292] @ (800420c ) 80040e6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80040ea: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 80040ee: 687b ldr r3, [r7, #4] 80040f0: 6b5b ldr r3, [r3, #52] @ 0x34 80040f2: 4946 ldr r1, [pc, #280] @ (800420c ) 80040f4: 4313 orrs r3, r2 80040f6: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) 80040fa: 687b ldr r3, [r7, #4] 80040fc: 6b5b ldr r3, [r3, #52] @ 0x34 80040fe: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004102: d101 bne.n 8004108 { plli2sused = 1U; 8004104: 2301 movs r3, #1 8004106: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) 8004108: 687b ldr r3, [r7, #4] 800410a: 6b5b ldr r3, [r3, #52] @ 0x34 800410c: 2b00 cmp r3, #0 800410e: d101 bne.n 8004114 { pllsaiused = 1U; 8004110: 2301 movs r3, #1 8004112: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- RTC configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 8004114: 687b ldr r3, [r7, #4] 8004116: 681b ldr r3, [r3, #0] 8004118: f003 0320 and.w r3, r3, #32 800411c: 2b00 cmp r3, #0 800411e: f000 808a beq.w 8004236 { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 8004122: 2300 movs r3, #0 8004124: 60bb str r3, [r7, #8] 8004126: 4b39 ldr r3, [pc, #228] @ (800420c ) 8004128: 6c1b ldr r3, [r3, #64] @ 0x40 800412a: 4a38 ldr r2, [pc, #224] @ (800420c ) 800412c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004130: 6413 str r3, [r2, #64] @ 0x40 8004132: 4b36 ldr r3, [pc, #216] @ (800420c ) 8004134: 6c1b ldr r3, [r3, #64] @ 0x40 8004136: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800413a: 60bb str r3, [r7, #8] 800413c: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; 800413e: 4b34 ldr r3, [pc, #208] @ (8004210 ) 8004140: 681b ldr r3, [r3, #0] 8004142: 4a33 ldr r2, [pc, #204] @ (8004210 ) 8004144: f443 7380 orr.w r3, r3, #256 @ 0x100 8004148: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 800414a: f7fd fb75 bl 8001838 800414e: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR & PWR_CR_DBP) == RESET) 8004150: e008 b.n 8004164 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004152: f7fd fb71 bl 8001838 8004156: 4602 mov r2, r0 8004158: 6a7b ldr r3, [r7, #36] @ 0x24 800415a: 1ad3 subs r3, r2, r3 800415c: 2b02 cmp r3, #2 800415e: d901 bls.n 8004164 { return HAL_TIMEOUT; 8004160: 2303 movs r3, #3 8004162: e278 b.n 8004656 while ((PWR->CR & PWR_CR_DBP) == RESET) 8004164: 4b2a ldr r3, [pc, #168] @ (8004210 ) 8004166: 681b ldr r3, [r3, #0] 8004168: f403 7380 and.w r3, r3, #256 @ 0x100 800416c: 2b00 cmp r3, #0 800416e: d0f0 beq.n 8004152 } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); 8004170: 4b26 ldr r3, [pc, #152] @ (800420c ) 8004172: 6f1b ldr r3, [r3, #112] @ 0x70 8004174: f403 7340 and.w r3, r3, #768 @ 0x300 8004178: 623b str r3, [r7, #32] if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 800417a: 6a3b ldr r3, [r7, #32] 800417c: 2b00 cmp r3, #0 800417e: d02f beq.n 80041e0 8004180: 687b ldr r3, [r7, #4] 8004182: 6c1b ldr r3, [r3, #64] @ 0x40 8004184: f403 7340 and.w r3, r3, #768 @ 0x300 8004188: 6a3a ldr r2, [r7, #32] 800418a: 429a cmp r2, r3 800418c: d028 beq.n 80041e0 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800418e: 4b1f ldr r3, [pc, #124] @ (800420c ) 8004190: 6f1b ldr r3, [r3, #112] @ 0x70 8004192: f423 7340 bic.w r3, r3, #768 @ 0x300 8004196: 623b str r3, [r7, #32] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8004198: 4b1e ldr r3, [pc, #120] @ (8004214 ) 800419a: 2201 movs r2, #1 800419c: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 800419e: 4b1d ldr r3, [pc, #116] @ (8004214 ) 80041a0: 2200 movs r2, #0 80041a2: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; 80041a4: 4a19 ldr r2, [pc, #100] @ (800420c ) 80041a6: 6a3b ldr r3, [r7, #32] 80041a8: 6713 str r3, [r2, #112] @ 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 80041aa: 4b18 ldr r3, [pc, #96] @ (800420c ) 80041ac: 6f1b ldr r3, [r3, #112] @ 0x70 80041ae: f003 0301 and.w r3, r3, #1 80041b2: 2b01 cmp r3, #1 80041b4: d114 bne.n 80041e0 { /* Get tick */ tickstart = HAL_GetTick(); 80041b6: f7fd fb3f bl 8001838 80041ba: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80041bc: e00a b.n 80041d4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80041be: f7fd fb3b bl 8001838 80041c2: 4602 mov r2, r0 80041c4: 6a7b ldr r3, [r7, #36] @ 0x24 80041c6: 1ad3 subs r3, r2, r3 80041c8: f241 3288 movw r2, #5000 @ 0x1388 80041cc: 4293 cmp r3, r2 80041ce: d901 bls.n 80041d4 { return HAL_TIMEOUT; 80041d0: 2303 movs r3, #3 80041d2: e240 b.n 8004656 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80041d4: 4b0d ldr r3, [pc, #52] @ (800420c ) 80041d6: 6f1b ldr r3, [r3, #112] @ 0x70 80041d8: f003 0302 and.w r3, r3, #2 80041dc: 2b00 cmp r3, #0 80041de: d0ee beq.n 80041be } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80041e0: 687b ldr r3, [r7, #4] 80041e2: 6c1b ldr r3, [r3, #64] @ 0x40 80041e4: f403 7340 and.w r3, r3, #768 @ 0x300 80041e8: f5b3 7f40 cmp.w r3, #768 @ 0x300 80041ec: d114 bne.n 8004218 80041ee: 4b07 ldr r3, [pc, #28] @ (800420c ) 80041f0: 689b ldr r3, [r3, #8] 80041f2: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000 80041f6: 687b ldr r3, [r7, #4] 80041f8: 6c1b ldr r3, [r3, #64] @ 0x40 80041fa: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 80041fe: f423 7340 bic.w r3, r3, #768 @ 0x300 8004202: 4902 ldr r1, [pc, #8] @ (800420c ) 8004204: 4313 orrs r3, r2 8004206: 608b str r3, [r1, #8] 8004208: e00c b.n 8004224 800420a: bf00 nop 800420c: 40023800 .word 0x40023800 8004210: 40007000 .word 0x40007000 8004214: 42470e40 .word 0x42470e40 8004218: 4b4a ldr r3, [pc, #296] @ (8004344 ) 800421a: 689b ldr r3, [r3, #8] 800421c: 4a49 ldr r2, [pc, #292] @ (8004344 ) 800421e: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000 8004222: 6093 str r3, [r2, #8] 8004224: 4b47 ldr r3, [pc, #284] @ (8004344 ) 8004226: 6f1a ldr r2, [r3, #112] @ 0x70 8004228: 687b ldr r3, [r7, #4] 800422a: 6c1b ldr r3, [r3, #64] @ 0x40 800422c: f3c3 030b ubfx r3, r3, #0, #12 8004230: 4944 ldr r1, [pc, #272] @ (8004344 ) 8004232: 4313 orrs r3, r2 8004234: 670b str r3, [r1, #112] @ 0x70 } /*--------------------------------------------------------------------------*/ /*---------------------------- TIM configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 8004236: 687b ldr r3, [r7, #4] 8004238: 681b ldr r3, [r3, #0] 800423a: f003 0310 and.w r3, r3, #16 800423e: 2b00 cmp r3, #0 8004240: d004 beq.n 800424c { /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8004242: 687b ldr r3, [r7, #4] 8004244: f893 2058 ldrb.w r2, [r3, #88] @ 0x58 8004248: 4b3f ldr r3, [pc, #252] @ (8004348 ) 800424a: 601a str r2, [r3, #0] } /*--------------------------------------------------------------------------*/ /*---------------------------- FMPI2C1 Configuration -----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) 800424c: 687b ldr r3, [r7, #4] 800424e: 681b ldr r3, [r3, #0] 8004250: f003 0380 and.w r3, r3, #128 @ 0x80 8004254: 2b00 cmp r3, #0 8004256: d00a beq.n 800426e { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); 8004258: 4b3a ldr r3, [pc, #232] @ (8004344 ) 800425a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800425e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 8004262: 687b ldr r3, [r7, #4] 8004264: 6cdb ldr r3, [r3, #76] @ 0x4c 8004266: 4937 ldr r1, [pc, #220] @ (8004344 ) 8004268: 4313 orrs r3, r2 800426a: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ CEC Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800426e: 687b ldr r3, [r7, #4] 8004270: 681b ldr r3, [r3, #0] 8004272: f003 0340 and.w r3, r3, #64 @ 0x40 8004276: 2b00 cmp r3, #0 8004278: d00a beq.n 8004290 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800427a: 4b32 ldr r3, [pc, #200] @ (8004344 ) 800427c: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004280: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000 8004284: 687b ldr r3, [r7, #4] 8004286: 6c9b ldr r3, [r3, #72] @ 0x48 8004288: 492e ldr r1, [pc, #184] @ (8004344 ) 800428a: 4313 orrs r3, r2 800428c: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*----------------------------- CLK48 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 8004290: 687b ldr r3, [r7, #4] 8004292: 681b ldr r3, [r3, #0] 8004294: f403 7380 and.w r3, r3, #256 @ 0x100 8004298: 2b00 cmp r3, #0 800429a: d011 beq.n 80042c0 { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); 800429c: 4b29 ldr r3, [pc, #164] @ (8004344 ) 800429e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80042a2: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000 80042a6: 687b ldr r3, [r7, #4] 80042a8: 6d5b ldr r3, [r3, #84] @ 0x54 80042aa: 4926 ldr r1, [pc, #152] @ (8004344 ) 80042ac: 4313 orrs r3, r2 80042ae: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLSAI when it's used as clock source for CLK48 */ if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) 80042b2: 687b ldr r3, [r7, #4] 80042b4: 6d5b ldr r3, [r3, #84] @ 0x54 80042b6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80042ba: d101 bne.n 80042c0 { pllsaiused = 1U; 80042bc: 2301 movs r3, #1 80042be: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- SDIO Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) 80042c0: 687b ldr r3, [r7, #4] 80042c2: 681b ldr r3, [r3, #0] 80042c4: f403 7300 and.w r3, r3, #512 @ 0x200 80042c8: 2b00 cmp r3, #0 80042ca: d00a beq.n 80042e2 { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); 80042cc: 4b1d ldr r3, [pc, #116] @ (8004344 ) 80042ce: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80042d2: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000 80042d6: 687b ldr r3, [r7, #4] 80042d8: 6c5b ldr r3, [r3, #68] @ 0x44 80042da: 491a ldr r1, [pc, #104] @ (8004344 ) 80042dc: 4313 orrs r3, r2 80042de: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ SPDIFRX Configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 80042e2: 687b ldr r3, [r7, #4] 80042e4: 681b ldr r3, [r3, #0] 80042e6: f403 6380 and.w r3, r3, #1024 @ 0x400 80042ea: 2b00 cmp r3, #0 80042ec: d011 beq.n 8004312 { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); /* Configure the SPDIFRX clock source */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); 80042ee: 4b15 ldr r3, [pc, #84] @ (8004344 ) 80042f0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80042f4: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000 80042f8: 687b ldr r3, [r7, #4] 80042fa: 6d1b ldr r3, [r3, #80] @ 0x50 80042fc: 4911 ldr r1, [pc, #68] @ (8004344 ) 80042fe: 4313 orrs r3, r2 8004300: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) 8004304: 687b ldr r3, [r7, #4] 8004306: 6d1b ldr r3, [r3, #80] @ 0x50 8004308: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800430c: d101 bne.n 8004312 { plli2sused = 1U; 800430e: 2301 movs r3, #1 8004310: 62fb str r3, [r7, #44] @ 0x2c /*--------------------------------------------------------------------------*/ /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) 8004312: 6afb ldr r3, [r7, #44] @ 0x2c 8004314: 2b01 cmp r3, #1 8004316: d005 beq.n 8004324 8004318: 687b ldr r3, [r7, #4] 800431a: 681b ldr r3, [r3, #0] 800431c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8004320: f040 80ff bne.w 8004522 { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 8004324: 4b09 ldr r3, [pc, #36] @ (800434c ) 8004326: 2200 movs r2, #0 8004328: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800432a: f7fd fa85 bl 8001838 800432e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004330: e00e b.n 8004350 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004332: f7fd fa81 bl 8001838 8004336: 4602 mov r2, r0 8004338: 6a7b ldr r3, [r7, #36] @ 0x24 800433a: 1ad3 subs r3, r2, r3 800433c: 2b02 cmp r3, #2 800433e: d907 bls.n 8004350 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004340: 2303 movs r3, #3 8004342: e188 b.n 8004656 8004344: 40023800 .word 0x40023800 8004348: 424711e0 .word 0x424711e0 800434c: 42470068 .word 0x42470068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004350: 4b7e ldr r3, [pc, #504] @ (800454c ) 8004352: 681b ldr r3, [r3, #0] 8004354: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004358: 2b00 cmp r3, #0 800435a: d1ea bne.n 8004332 /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) 800435c: 687b ldr r3, [r7, #4] 800435e: 681b ldr r3, [r3, #0] 8004360: f003 0301 and.w r3, r3, #1 8004364: 2b00 cmp r3, #0 8004366: d003 beq.n 8004370 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8004368: 687b ldr r3, [r7, #4] 800436a: 6b9b ldr r3, [r3, #56] @ 0x38 800436c: 2b00 cmp r3, #0 800436e: d009 beq.n 8004384 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 8004370: 687b ldr r3, [r7, #4] 8004372: 681b ldr r3, [r3, #0] 8004374: f003 0302 and.w r3, r3, #2 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8004378: 2b00 cmp r3, #0 800437a: d028 beq.n 80043ce ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 800437c: 687b ldr r3, [r7, #4] 800437e: 6bdb ldr r3, [r3, #60] @ 0x3c 8004380: 2b00 cmp r3, #0 8004382: d124 bne.n 80043ce { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004384: 4b71 ldr r3, [pc, #452] @ (800454c ) 8004386: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800438a: 0c1b lsrs r3, r3, #16 800438c: f003 0303 and.w r3, r3, #3 8004390: 3301 adds r3, #1 8004392: 005b lsls r3, r3, #1 8004394: 61fb str r3, [r7, #28] plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); 8004396: 4b6d ldr r3, [pc, #436] @ (800454c ) 8004398: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800439c: 0e1b lsrs r3, r3, #24 800439e: f003 030f and.w r3, r3, #15 80043a2: 61bb str r3, [r7, #24] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq, 80043a4: 687b ldr r3, [r7, #4] 80043a6: 685a ldr r2, [r3, #4] 80043a8: 687b ldr r3, [r7, #4] 80043aa: 689b ldr r3, [r3, #8] 80043ac: 019b lsls r3, r3, #6 80043ae: 431a orrs r2, r3 80043b0: 69fb ldr r3, [r7, #28] 80043b2: 085b lsrs r3, r3, #1 80043b4: 3b01 subs r3, #1 80043b6: 041b lsls r3, r3, #16 80043b8: 431a orrs r2, r3 80043ba: 69bb ldr r3, [r7, #24] 80043bc: 061b lsls r3, r3, #24 80043be: 431a orrs r2, r3 80043c0: 687b ldr r3, [r7, #4] 80043c2: 695b ldr r3, [r3, #20] 80043c4: 071b lsls r3, r3, #28 80043c6: 4961 ldr r1, [pc, #388] @ (800454c ) 80043c8: 4313 orrs r3, r2 80043ca: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SR); } /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 80043ce: 687b ldr r3, [r7, #4] 80043d0: 681b ldr r3, [r3, #0] 80043d2: f003 0304 and.w r3, r3, #4 80043d6: 2b00 cmp r3, #0 80043d8: d004 beq.n 80043e4 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 80043da: 687b ldr r3, [r7, #4] 80043dc: 6b1b ldr r3, [r3, #48] @ 0x30 80043de: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80043e2: d00a beq.n 80043fa ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 80043e4: 687b ldr r3, [r7, #4] 80043e6: 681b ldr r3, [r3, #0] 80043e8: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 80043ec: 2b00 cmp r3, #0 80043ee: d035 beq.n 800445c ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 80043f0: 687b ldr r3, [r7, #4] 80043f2: 6b5b ldr r3, [r3, #52] @ 0x34 80043f4: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80043f8: d130 bne.n 800445c assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 80043fa: 4b54 ldr r3, [pc, #336] @ (800454c ) 80043fc: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004400: 0c1b lsrs r3, r3, #16 8004402: f003 0303 and.w r3, r3, #3 8004406: 3301 adds r3, #1 8004408: 005b lsls r3, r3, #1 800440a: 61fb str r3, [r7, #28] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 800440c: 4b4f ldr r3, [pc, #316] @ (800454c ) 800440e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004412: 0f1b lsrs r3, r3, #28 8004414: f003 0307 and.w r3, r3, #7 8004418: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, 800441a: 687b ldr r3, [r7, #4] 800441c: 685a ldr r2, [r3, #4] 800441e: 687b ldr r3, [r7, #4] 8004420: 689b ldr r3, [r3, #8] 8004422: 019b lsls r3, r3, #6 8004424: 431a orrs r2, r3 8004426: 69fb ldr r3, [r7, #28] 8004428: 085b lsrs r3, r3, #1 800442a: 3b01 subs r3, #1 800442c: 041b lsls r3, r3, #16 800442e: 431a orrs r2, r3 8004430: 687b ldr r3, [r7, #4] 8004432: 691b ldr r3, [r3, #16] 8004434: 061b lsls r3, r3, #24 8004436: 431a orrs r2, r3 8004438: 697b ldr r3, [r7, #20] 800443a: 071b lsls r3, r3, #28 800443c: 4943 ldr r1, [pc, #268] @ (800454c ) 800443e: 4313 orrs r3, r2 8004440: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 8004444: 4b41 ldr r3, [pc, #260] @ (800454c ) 8004446: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800444a: f023 021f bic.w r2, r3, #31 800444e: 687b ldr r3, [r7, #4] 8004450: 6a9b ldr r3, [r3, #40] @ 0x28 8004452: 3b01 subs r3, #1 8004454: 493d ldr r1, [pc, #244] @ (800454c ) 8004456: 4313 orrs r3, r2 8004458: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 800445c: 687b ldr r3, [r7, #4] 800445e: 681b ldr r3, [r3, #0] 8004460: f403 6380 and.w r3, r3, #1024 @ 0x400 8004464: 2b00 cmp r3, #0 8004466: d029 beq.n 80044bc && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 8004468: 687b ldr r3, [r7, #4] 800446a: 6d1b ldr r3, [r3, #80] @ 0x50 800446c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004470: d124 bne.n 80044bc { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004472: 4b36 ldr r3, [pc, #216] @ (800454c ) 8004474: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004478: 0c1b lsrs r3, r3, #16 800447a: f003 0303 and.w r3, r3, #3 800447e: 3301 adds r3, #1 8004480: 005b lsls r3, r3, #1 8004482: 61bb str r3, [r7, #24] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004484: 4b31 ldr r3, [pc, #196] @ (800454c ) 8004486: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800448a: 0f1b lsrs r3, r3, #28 800448c: f003 0307 and.w r3, r3, #7 8004490: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 8004492: 687b ldr r3, [r7, #4] 8004494: 685a ldr r2, [r3, #4] 8004496: 687b ldr r3, [r7, #4] 8004498: 689b ldr r3, [r3, #8] 800449a: 019b lsls r3, r3, #6 800449c: 431a orrs r2, r3 800449e: 687b ldr r3, [r7, #4] 80044a0: 68db ldr r3, [r3, #12] 80044a2: 085b lsrs r3, r3, #1 80044a4: 3b01 subs r3, #1 80044a6: 041b lsls r3, r3, #16 80044a8: 431a orrs r2, r3 80044aa: 69bb ldr r3, [r7, #24] 80044ac: 061b lsls r3, r3, #24 80044ae: 431a orrs r2, r3 80044b0: 697b ldr r3, [r7, #20] 80044b2: 071b lsls r3, r3, #28 80044b4: 4925 ldr r1, [pc, #148] @ (800454c ) 80044b6: 4313 orrs r3, r2 80044b8: f8c1 3084 str.w r3, [r1, #132] @ 0x84 plli2sq, plli2sr); } /*----------------- In Case of PLLI2S is just selected -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 80044bc: 687b ldr r3, [r7, #4] 80044be: 681b ldr r3, [r3, #0] 80044c0: f403 6300 and.w r3, r3, #2048 @ 0x800 80044c4: 2b00 cmp r3, #0 80044c6: d016 beq.n 80044f6 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 80044c8: 687b ldr r3, [r7, #4] 80044ca: 685a ldr r2, [r3, #4] 80044cc: 687b ldr r3, [r7, #4] 80044ce: 689b ldr r3, [r3, #8] 80044d0: 019b lsls r3, r3, #6 80044d2: 431a orrs r2, r3 80044d4: 687b ldr r3, [r7, #4] 80044d6: 68db ldr r3, [r3, #12] 80044d8: 085b lsrs r3, r3, #1 80044da: 3b01 subs r3, #1 80044dc: 041b lsls r3, r3, #16 80044de: 431a orrs r2, r3 80044e0: 687b ldr r3, [r7, #4] 80044e2: 691b ldr r3, [r3, #16] 80044e4: 061b lsls r3, r3, #24 80044e6: 431a orrs r2, r3 80044e8: 687b ldr r3, [r7, #4] 80044ea: 695b ldr r3, [r3, #20] 80044ec: 071b lsls r3, r3, #28 80044ee: 4917 ldr r1, [pc, #92] @ (800454c ) 80044f0: 4313 orrs r3, r2 80044f2: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 80044f6: 4b16 ldr r3, [pc, #88] @ (8004550 ) 80044f8: 2201 movs r2, #1 80044fa: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80044fc: f7fd f99c bl 8001838 8004500: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004502: e008 b.n 8004516 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004504: f7fd f998 bl 8001838 8004508: 4602 mov r2, r0 800450a: 6a7b ldr r3, [r7, #36] @ 0x24 800450c: 1ad3 subs r3, r2, r3 800450e: 2b02 cmp r3, #2 8004510: d901 bls.n 8004516 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004512: 2303 movs r3, #3 8004514: e09f b.n 8004656 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004516: 4b0d ldr r3, [pc, #52] @ (800454c ) 8004518: 681b ldr r3, [r3, #0] 800451a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800451e: 2b00 cmp r3, #0 8004520: d0f0 beq.n 8004504 } /*--------------------------------------------------------------------------*/ /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ if (pllsaiused == 1U) 8004522: 6abb ldr r3, [r7, #40] @ 0x28 8004524: 2b01 cmp r3, #1 8004526: f040 8095 bne.w 8004654 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 800452a: 4b0a ldr r3, [pc, #40] @ (8004554 ) 800452c: 2200 movs r2, #0 800452e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004530: f7fd f982 bl 8001838 8004534: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is disabled */ while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004536: e00f b.n 8004558 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004538: f7fd f97e bl 8001838 800453c: 4602 mov r2, r0 800453e: 6a7b ldr r3, [r7, #36] @ 0x24 8004540: 1ad3 subs r3, r2, r3 8004542: 2b02 cmp r3, #2 8004544: d908 bls.n 8004558 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004546: 2303 movs r3, #3 8004548: e085 b.n 8004656 800454a: bf00 nop 800454c: 40023800 .word 0x40023800 8004550: 42470068 .word 0x42470068 8004554: 42470070 .word 0x42470070 while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004558: 4b41 ldr r3, [pc, #260] @ (8004660 ) 800455a: 681b ldr r3, [r3, #0] 800455c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004560: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004564: d0e8 beq.n 8004538 /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8004566: 687b ldr r3, [r7, #4] 8004568: 681b ldr r3, [r3, #0] 800456a: f003 0304 and.w r3, r3, #4 800456e: 2b00 cmp r3, #0 8004570: d003 beq.n 800457a && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8004572: 687b ldr r3, [r7, #4] 8004574: 6b1b ldr r3, [r3, #48] @ 0x30 8004576: 2b00 cmp r3, #0 8004578: d009 beq.n 800458e ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 800457a: 687b ldr r3, [r7, #4] 800457c: 681b ldr r3, [r3, #0] 800457e: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8004582: 2b00 cmp r3, #0 8004584: d02b beq.n 80045de ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8004586: 687b ldr r3, [r7, #4] 8004588: 6b5b ldr r3, [r3, #52] @ 0x34 800458a: 2b00 cmp r3, #0 800458c: d127 bne.n 80045de assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); 800458e: 4b34 ldr r3, [pc, #208] @ (8004660 ) 8004590: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004594: 0c1b lsrs r3, r3, #16 8004596: f003 0303 and.w r3, r3, #3 800459a: 3301 adds r3, #1 800459c: 005b lsls r3, r3, #1 800459e: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, 80045a0: 687b ldr r3, [r7, #4] 80045a2: 699a ldr r2, [r3, #24] 80045a4: 687b ldr r3, [r7, #4] 80045a6: 69db ldr r3, [r3, #28] 80045a8: 019b lsls r3, r3, #6 80045aa: 431a orrs r2, r3 80045ac: 693b ldr r3, [r7, #16] 80045ae: 085b lsrs r3, r3, #1 80045b0: 3b01 subs r3, #1 80045b2: 041b lsls r3, r3, #16 80045b4: 431a orrs r2, r3 80045b6: 687b ldr r3, [r7, #4] 80045b8: 6a5b ldr r3, [r3, #36] @ 0x24 80045ba: 061b lsls r3, r3, #24 80045bc: 4928 ldr r1, [pc, #160] @ (8004660 ) 80045be: 4313 orrs r3, r2 80045c0: f8c1 3088 str.w r3, [r1, #136] @ 0x88 PeriphClkInit->PLLSAI.PLLSAIQ, 0U); /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 80045c4: 4b26 ldr r3, [pc, #152] @ (8004660 ) 80045c6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80045ca: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 80045ce: 687b ldr r3, [r7, #4] 80045d0: 6adb ldr r3, [r3, #44] @ 0x2c 80045d2: 3b01 subs r3, #1 80045d4: 021b lsls r3, r3, #8 80045d6: 4922 ldr r1, [pc, #136] @ (8004660 ) 80045d8: 4313 orrs r3, r2 80045da: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ /* In Case of PLLI2S is selected as source clock for CLK48 */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 80045de: 687b ldr r3, [r7, #4] 80045e0: 681b ldr r3, [r3, #0] 80045e2: f403 7380 and.w r3, r3, #256 @ 0x100 80045e6: 2b00 cmp r3, #0 80045e8: d01d beq.n 8004626 && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) 80045ea: 687b ldr r3, [r7, #4] 80045ec: 6d5b ldr r3, [r3, #84] @ 0x54 80045ee: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80045f2: d118 bne.n 8004626 { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 80045f4: 4b1a ldr r3, [pc, #104] @ (8004660 ) 80045f6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80045fa: 0e1b lsrs r3, r3, #24 80045fc: f003 030f and.w r3, r3, #15 8004600: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, 8004602: 687b ldr r3, [r7, #4] 8004604: 699a ldr r2, [r3, #24] 8004606: 687b ldr r3, [r7, #4] 8004608: 69db ldr r3, [r3, #28] 800460a: 019b lsls r3, r3, #6 800460c: 431a orrs r2, r3 800460e: 687b ldr r3, [r7, #4] 8004610: 6a1b ldr r3, [r3, #32] 8004612: 085b lsrs r3, r3, #1 8004614: 3b01 subs r3, #1 8004616: 041b lsls r3, r3, #16 8004618: 431a orrs r2, r3 800461a: 68fb ldr r3, [r7, #12] 800461c: 061b lsls r3, r3, #24 800461e: 4910 ldr r1, [pc, #64] @ (8004660 ) 8004620: 4313 orrs r3, r2 8004622: f8c1 3088 str.w r3, [r1, #136] @ 0x88 pllsaiq, 0U); } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 8004626: 4b0f ldr r3, [pc, #60] @ (8004664 ) 8004628: 2201 movs r2, #1 800462a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800462c: f7fd f904 bl 8001838 8004630: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is ready */ while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004632: e008 b.n 8004646 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004634: f7fd f900 bl 8001838 8004638: 4602 mov r2, r0 800463a: 6a7b ldr r3, [r7, #36] @ 0x24 800463c: 1ad3 subs r3, r2, r3 800463e: 2b02 cmp r3, #2 8004640: d901 bls.n 8004646 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004642: 2303 movs r3, #3 8004644: e007 b.n 8004656 while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004646: 4b06 ldr r3, [pc, #24] @ (8004660 ) 8004648: 681b ldr r3, [r3, #0] 800464a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800464e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004652: d1ef bne.n 8004634 } } } return HAL_OK; 8004654: 2300 movs r3, #0 } 8004656: 4618 mov r0, r3 8004658: 3730 adds r7, #48 @ 0x30 800465a: 46bd mov sp, r7 800465c: bd80 pop {r7, pc} 800465e: bf00 nop 8004660: 40023800 .word 0x40023800 8004664: 42470070 .word 0x42470070 08004668 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8004668: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800466c: b0ae sub sp, #184 @ 0xb8 800466e: af00 add r7, sp, #0 uint32_t pllm = 0U; 8004670: 2300 movs r3, #0 8004672: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t pllvco = 0U; 8004676: 2300 movs r3, #0 8004678: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t pllp = 0U; 800467c: 2300 movs r3, #0 800467e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 uint32_t pllr = 0U; 8004682: 2300 movs r3, #0 8004684: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t sysclockfreq = 0U; 8004688: 2300 movs r3, #0 800468a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800468e: 4bcb ldr r3, [pc, #812] @ (80049bc ) 8004690: 689b ldr r3, [r3, #8] 8004692: f003 030c and.w r3, r3, #12 8004696: 2b0c cmp r3, #12 8004698: f200 8206 bhi.w 8004aa8 800469c: a201 add r2, pc, #4 @ (adr r2, 80046a4 ) 800469e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80046a2: bf00 nop 80046a4: 080046d9 .word 0x080046d9 80046a8: 08004aa9 .word 0x08004aa9 80046ac: 08004aa9 .word 0x08004aa9 80046b0: 08004aa9 .word 0x08004aa9 80046b4: 080046e1 .word 0x080046e1 80046b8: 08004aa9 .word 0x08004aa9 80046bc: 08004aa9 .word 0x08004aa9 80046c0: 08004aa9 .word 0x08004aa9 80046c4: 080046e9 .word 0x080046e9 80046c8: 08004aa9 .word 0x08004aa9 80046cc: 08004aa9 .word 0x08004aa9 80046d0: 08004aa9 .word 0x08004aa9 80046d4: 080048d9 .word 0x080048d9 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 80046d8: 4bb9 ldr r3, [pc, #740] @ (80049c0 ) 80046da: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 80046de: e1e7 b.n 8004ab0 } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 80046e0: 4bb8 ldr r3, [pc, #736] @ (80049c4 ) 80046e2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 80046e6: e1e3 b.n 8004ab0 } case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 80046e8: 4bb4 ldr r3, [pc, #720] @ (80049bc ) 80046ea: 685b ldr r3, [r3, #4] 80046ec: f003 033f and.w r3, r3, #63 @ 0x3f 80046f0: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 80046f4: 4bb1 ldr r3, [pc, #708] @ (80049bc ) 80046f6: 685b ldr r3, [r3, #4] 80046f8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80046fc: 2b00 cmp r3, #0 80046fe: d071 beq.n 80047e4 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004700: 4bae ldr r3, [pc, #696] @ (80049bc ) 8004702: 685b ldr r3, [r3, #4] 8004704: 099b lsrs r3, r3, #6 8004706: 2200 movs r2, #0 8004708: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800470c: f8c7 209c str.w r2, [r7, #156] @ 0x9c 8004710: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8004714: f3c3 0308 ubfx r3, r3, #0, #9 8004718: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800471c: 2300 movs r3, #0 800471e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8004722: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8004726: 4622 mov r2, r4 8004728: 462b mov r3, r5 800472a: f04f 0000 mov.w r0, #0 800472e: f04f 0100 mov.w r1, #0 8004732: 0159 lsls r1, r3, #5 8004734: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004738: 0150 lsls r0, r2, #5 800473a: 4602 mov r2, r0 800473c: 460b mov r3, r1 800473e: 4621 mov r1, r4 8004740: 1a51 subs r1, r2, r1 8004742: 6439 str r1, [r7, #64] @ 0x40 8004744: 4629 mov r1, r5 8004746: eb63 0301 sbc.w r3, r3, r1 800474a: 647b str r3, [r7, #68] @ 0x44 800474c: f04f 0200 mov.w r2, #0 8004750: f04f 0300 mov.w r3, #0 8004754: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40 8004758: 4649 mov r1, r9 800475a: 018b lsls r3, r1, #6 800475c: 4641 mov r1, r8 800475e: ea43 6391 orr.w r3, r3, r1, lsr #26 8004762: 4641 mov r1, r8 8004764: 018a lsls r2, r1, #6 8004766: 4641 mov r1, r8 8004768: 1a51 subs r1, r2, r1 800476a: 63b9 str r1, [r7, #56] @ 0x38 800476c: 4649 mov r1, r9 800476e: eb63 0301 sbc.w r3, r3, r1 8004772: 63fb str r3, [r7, #60] @ 0x3c 8004774: f04f 0200 mov.w r2, #0 8004778: f04f 0300 mov.w r3, #0 800477c: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38 8004780: 4649 mov r1, r9 8004782: 00cb lsls r3, r1, #3 8004784: 4641 mov r1, r8 8004786: ea43 7351 orr.w r3, r3, r1, lsr #29 800478a: 4641 mov r1, r8 800478c: 00ca lsls r2, r1, #3 800478e: 4610 mov r0, r2 8004790: 4619 mov r1, r3 8004792: 4603 mov r3, r0 8004794: 4622 mov r2, r4 8004796: 189b adds r3, r3, r2 8004798: 633b str r3, [r7, #48] @ 0x30 800479a: 462b mov r3, r5 800479c: 460a mov r2, r1 800479e: eb42 0303 adc.w r3, r2, r3 80047a2: 637b str r3, [r7, #52] @ 0x34 80047a4: f04f 0200 mov.w r2, #0 80047a8: f04f 0300 mov.w r3, #0 80047ac: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 80047b0: 4629 mov r1, r5 80047b2: 024b lsls r3, r1, #9 80047b4: 4621 mov r1, r4 80047b6: ea43 53d1 orr.w r3, r3, r1, lsr #23 80047ba: 4621 mov r1, r4 80047bc: 024a lsls r2, r1, #9 80047be: 4610 mov r0, r2 80047c0: 4619 mov r1, r3 80047c2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80047c6: 2200 movs r2, #0 80047c8: f8c7 3088 str.w r3, [r7, #136] @ 0x88 80047cc: f8c7 208c str.w r2, [r7, #140] @ 0x8c 80047d0: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88 80047d4: f7fb fd16 bl 8000204 <__aeabi_uldivmod> 80047d8: 4602 mov r2, r0 80047da: 460b mov r3, r1 80047dc: 4613 mov r3, r2 80047de: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 80047e2: e067 b.n 80048b4 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 80047e4: 4b75 ldr r3, [pc, #468] @ (80049bc ) 80047e6: 685b ldr r3, [r3, #4] 80047e8: 099b lsrs r3, r3, #6 80047ea: 2200 movs r2, #0 80047ec: f8c7 3080 str.w r3, [r7, #128] @ 0x80 80047f0: f8c7 2084 str.w r2, [r7, #132] @ 0x84 80047f4: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80047f8: f3c3 0308 ubfx r3, r3, #0, #9 80047fc: 67bb str r3, [r7, #120] @ 0x78 80047fe: 2300 movs r3, #0 8004800: 67fb str r3, [r7, #124] @ 0x7c 8004802: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78 8004806: 4622 mov r2, r4 8004808: 462b mov r3, r5 800480a: f04f 0000 mov.w r0, #0 800480e: f04f 0100 mov.w r1, #0 8004812: 0159 lsls r1, r3, #5 8004814: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004818: 0150 lsls r0, r2, #5 800481a: 4602 mov r2, r0 800481c: 460b mov r3, r1 800481e: 4621 mov r1, r4 8004820: 1a51 subs r1, r2, r1 8004822: 62b9 str r1, [r7, #40] @ 0x28 8004824: 4629 mov r1, r5 8004826: eb63 0301 sbc.w r3, r3, r1 800482a: 62fb str r3, [r7, #44] @ 0x2c 800482c: f04f 0200 mov.w r2, #0 8004830: f04f 0300 mov.w r3, #0 8004834: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28 8004838: 4649 mov r1, r9 800483a: 018b lsls r3, r1, #6 800483c: 4641 mov r1, r8 800483e: ea43 6391 orr.w r3, r3, r1, lsr #26 8004842: 4641 mov r1, r8 8004844: 018a lsls r2, r1, #6 8004846: 4641 mov r1, r8 8004848: ebb2 0a01 subs.w sl, r2, r1 800484c: 4649 mov r1, r9 800484e: eb63 0b01 sbc.w fp, r3, r1 8004852: f04f 0200 mov.w r2, #0 8004856: f04f 0300 mov.w r3, #0 800485a: ea4f 03cb mov.w r3, fp, lsl #3 800485e: ea43 735a orr.w r3, r3, sl, lsr #29 8004862: ea4f 02ca mov.w r2, sl, lsl #3 8004866: 4692 mov sl, r2 8004868: 469b mov fp, r3 800486a: 4623 mov r3, r4 800486c: eb1a 0303 adds.w r3, sl, r3 8004870: 623b str r3, [r7, #32] 8004872: 462b mov r3, r5 8004874: eb4b 0303 adc.w r3, fp, r3 8004878: 627b str r3, [r7, #36] @ 0x24 800487a: f04f 0200 mov.w r2, #0 800487e: f04f 0300 mov.w r3, #0 8004882: e9d7 4508 ldrd r4, r5, [r7, #32] 8004886: 4629 mov r1, r5 8004888: 028b lsls r3, r1, #10 800488a: 4621 mov r1, r4 800488c: ea43 5391 orr.w r3, r3, r1, lsr #22 8004890: 4621 mov r1, r4 8004892: 028a lsls r2, r1, #10 8004894: 4610 mov r0, r2 8004896: 4619 mov r1, r3 8004898: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800489c: 2200 movs r2, #0 800489e: 673b str r3, [r7, #112] @ 0x70 80048a0: 677a str r2, [r7, #116] @ 0x74 80048a2: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70 80048a6: f7fb fcad bl 8000204 <__aeabi_uldivmod> 80048aa: 4602 mov r2, r0 80048ac: 460b mov r3, r1 80048ae: 4613 mov r3, r2 80048b0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); 80048b4: 4b41 ldr r3, [pc, #260] @ (80049bc ) 80048b6: 685b ldr r3, [r3, #4] 80048b8: 0c1b lsrs r3, r3, #16 80048ba: f003 0303 and.w r3, r3, #3 80048be: 3301 adds r3, #1 80048c0: 005b lsls r3, r3, #1 80048c2: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 sysclockfreq = pllvco / pllp; 80048c6: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 80048ca: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 80048ce: fbb2 f3f3 udiv r3, r2, r3 80048d2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 80048d6: e0eb b.n 8004ab0 } case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 80048d8: 4b38 ldr r3, [pc, #224] @ (80049bc ) 80048da: 685b ldr r3, [r3, #4] 80048dc: f003 033f and.w r3, r3, #63 @ 0x3f 80048e0: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 80048e4: 4b35 ldr r3, [pc, #212] @ (80049bc ) 80048e6: 685b ldr r3, [r3, #4] 80048e8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80048ec: 2b00 cmp r3, #0 80048ee: d06b beq.n 80049c8 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 80048f0: 4b32 ldr r3, [pc, #200] @ (80049bc ) 80048f2: 685b ldr r3, [r3, #4] 80048f4: 099b lsrs r3, r3, #6 80048f6: 2200 movs r2, #0 80048f8: 66bb str r3, [r7, #104] @ 0x68 80048fa: 66fa str r2, [r7, #108] @ 0x6c 80048fc: 6ebb ldr r3, [r7, #104] @ 0x68 80048fe: f3c3 0308 ubfx r3, r3, #0, #9 8004902: 663b str r3, [r7, #96] @ 0x60 8004904: 2300 movs r3, #0 8004906: 667b str r3, [r7, #100] @ 0x64 8004908: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60 800490c: 4622 mov r2, r4 800490e: 462b mov r3, r5 8004910: f04f 0000 mov.w r0, #0 8004914: f04f 0100 mov.w r1, #0 8004918: 0159 lsls r1, r3, #5 800491a: ea41 61d2 orr.w r1, r1, r2, lsr #27 800491e: 0150 lsls r0, r2, #5 8004920: 4602 mov r2, r0 8004922: 460b mov r3, r1 8004924: 4621 mov r1, r4 8004926: 1a51 subs r1, r2, r1 8004928: 61b9 str r1, [r7, #24] 800492a: 4629 mov r1, r5 800492c: eb63 0301 sbc.w r3, r3, r1 8004930: 61fb str r3, [r7, #28] 8004932: f04f 0200 mov.w r2, #0 8004936: f04f 0300 mov.w r3, #0 800493a: e9d7 ab06 ldrd sl, fp, [r7, #24] 800493e: 4659 mov r1, fp 8004940: 018b lsls r3, r1, #6 8004942: 4651 mov r1, sl 8004944: ea43 6391 orr.w r3, r3, r1, lsr #26 8004948: 4651 mov r1, sl 800494a: 018a lsls r2, r1, #6 800494c: 4651 mov r1, sl 800494e: ebb2 0801 subs.w r8, r2, r1 8004952: 4659 mov r1, fp 8004954: eb63 0901 sbc.w r9, r3, r1 8004958: f04f 0200 mov.w r2, #0 800495c: f04f 0300 mov.w r3, #0 8004960: ea4f 03c9 mov.w r3, r9, lsl #3 8004964: ea43 7358 orr.w r3, r3, r8, lsr #29 8004968: ea4f 02c8 mov.w r2, r8, lsl #3 800496c: 4690 mov r8, r2 800496e: 4699 mov r9, r3 8004970: 4623 mov r3, r4 8004972: eb18 0303 adds.w r3, r8, r3 8004976: 613b str r3, [r7, #16] 8004978: 462b mov r3, r5 800497a: eb49 0303 adc.w r3, r9, r3 800497e: 617b str r3, [r7, #20] 8004980: f04f 0200 mov.w r2, #0 8004984: f04f 0300 mov.w r3, #0 8004988: e9d7 4504 ldrd r4, r5, [r7, #16] 800498c: 4629 mov r1, r5 800498e: 024b lsls r3, r1, #9 8004990: 4621 mov r1, r4 8004992: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004996: 4621 mov r1, r4 8004998: 024a lsls r2, r1, #9 800499a: 4610 mov r0, r2 800499c: 4619 mov r1, r3 800499e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80049a2: 2200 movs r2, #0 80049a4: 65bb str r3, [r7, #88] @ 0x58 80049a6: 65fa str r2, [r7, #92] @ 0x5c 80049a8: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 80049ac: f7fb fc2a bl 8000204 <__aeabi_uldivmod> 80049b0: 4602 mov r2, r0 80049b2: 460b mov r3, r1 80049b4: 4613 mov r3, r2 80049b6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 80049ba: e065 b.n 8004a88 80049bc: 40023800 .word 0x40023800 80049c0: 00f42400 .word 0x00f42400 80049c4: 007a1200 .word 0x007a1200 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 80049c8: 4b3d ldr r3, [pc, #244] @ (8004ac0 ) 80049ca: 685b ldr r3, [r3, #4] 80049cc: 099b lsrs r3, r3, #6 80049ce: 2200 movs r2, #0 80049d0: 4618 mov r0, r3 80049d2: 4611 mov r1, r2 80049d4: f3c0 0308 ubfx r3, r0, #0, #9 80049d8: 653b str r3, [r7, #80] @ 0x50 80049da: 2300 movs r3, #0 80049dc: 657b str r3, [r7, #84] @ 0x54 80049de: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50 80049e2: 4642 mov r2, r8 80049e4: 464b mov r3, r9 80049e6: f04f 0000 mov.w r0, #0 80049ea: f04f 0100 mov.w r1, #0 80049ee: 0159 lsls r1, r3, #5 80049f0: ea41 61d2 orr.w r1, r1, r2, lsr #27 80049f4: 0150 lsls r0, r2, #5 80049f6: 4602 mov r2, r0 80049f8: 460b mov r3, r1 80049fa: 4641 mov r1, r8 80049fc: 1a51 subs r1, r2, r1 80049fe: 60b9 str r1, [r7, #8] 8004a00: 4649 mov r1, r9 8004a02: eb63 0301 sbc.w r3, r3, r1 8004a06: 60fb str r3, [r7, #12] 8004a08: f04f 0200 mov.w r2, #0 8004a0c: f04f 0300 mov.w r3, #0 8004a10: e9d7 ab02 ldrd sl, fp, [r7, #8] 8004a14: 4659 mov r1, fp 8004a16: 018b lsls r3, r1, #6 8004a18: 4651 mov r1, sl 8004a1a: ea43 6391 orr.w r3, r3, r1, lsr #26 8004a1e: 4651 mov r1, sl 8004a20: 018a lsls r2, r1, #6 8004a22: 4651 mov r1, sl 8004a24: 1a54 subs r4, r2, r1 8004a26: 4659 mov r1, fp 8004a28: eb63 0501 sbc.w r5, r3, r1 8004a2c: f04f 0200 mov.w r2, #0 8004a30: f04f 0300 mov.w r3, #0 8004a34: 00eb lsls r3, r5, #3 8004a36: ea43 7354 orr.w r3, r3, r4, lsr #29 8004a3a: 00e2 lsls r2, r4, #3 8004a3c: 4614 mov r4, r2 8004a3e: 461d mov r5, r3 8004a40: 4643 mov r3, r8 8004a42: 18e3 adds r3, r4, r3 8004a44: 603b str r3, [r7, #0] 8004a46: 464b mov r3, r9 8004a48: eb45 0303 adc.w r3, r5, r3 8004a4c: 607b str r3, [r7, #4] 8004a4e: f04f 0200 mov.w r2, #0 8004a52: f04f 0300 mov.w r3, #0 8004a56: e9d7 4500 ldrd r4, r5, [r7] 8004a5a: 4629 mov r1, r5 8004a5c: 028b lsls r3, r1, #10 8004a5e: 4621 mov r1, r4 8004a60: ea43 5391 orr.w r3, r3, r1, lsr #22 8004a64: 4621 mov r1, r4 8004a66: 028a lsls r2, r1, #10 8004a68: 4610 mov r0, r2 8004a6a: 4619 mov r1, r3 8004a6c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004a70: 2200 movs r2, #0 8004a72: 64bb str r3, [r7, #72] @ 0x48 8004a74: 64fa str r2, [r7, #76] @ 0x4c 8004a76: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8004a7a: f7fb fbc3 bl 8000204 <__aeabi_uldivmod> 8004a7e: 4602 mov r2, r0 8004a80: 460b mov r3, r1 8004a82: 4613 mov r3, r2 8004a84: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); 8004a88: 4b0d ldr r3, [pc, #52] @ (8004ac0 ) 8004a8a: 685b ldr r3, [r3, #4] 8004a8c: 0f1b lsrs r3, r3, #28 8004a8e: f003 0307 and.w r3, r3, #7 8004a92: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 sysclockfreq = pllvco / pllr; 8004a96: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004a9a: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8004a9e: fbb2 f3f3 udiv r3, r2, r3 8004aa2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004aa6: e003 b.n 8004ab0 } default: { sysclockfreq = HSI_VALUE; 8004aa8: 4b06 ldr r3, [pc, #24] @ (8004ac4 ) 8004aaa: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004aae: bf00 nop } } return sysclockfreq; 8004ab0: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 } 8004ab4: 4618 mov r0, r3 8004ab6: 37b8 adds r7, #184 @ 0xb8 8004ab8: 46bd mov sp, r7 8004aba: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8004abe: bf00 nop 8004ac0: 40023800 .word 0x40023800 8004ac4: 00f42400 .word 0x00f42400 08004ac8 : * @note This function add the PLL/PLLR factor management during PLL configuration this feature * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 8004ac8: b580 push {r7, lr} 8004aca: b086 sub sp, #24 8004acc: af00 add r7, sp, #0 8004ace: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8004ad0: 687b ldr r3, [r7, #4] 8004ad2: 2b00 cmp r3, #0 8004ad4: d101 bne.n 8004ada { return HAL_ERROR; 8004ad6: 2301 movs r3, #1 8004ad8: e28d b.n 8004ff6 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8004ada: 687b ldr r3, [r7, #4] 8004adc: 681b ldr r3, [r3, #0] 8004ade: f003 0301 and.w r3, r3, #1 8004ae2: 2b00 cmp r3, #0 8004ae4: f000 8083 beq.w 8004bee { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 8004ae8: 4b94 ldr r3, [pc, #592] @ (8004d3c ) 8004aea: 689b ldr r3, [r3, #8] 8004aec: f003 030c and.w r3, r3, #12 8004af0: 2b04 cmp r3, #4 8004af2: d019 beq.n 8004b28 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004af4: 4b91 ldr r3, [pc, #580] @ (8004d3c ) 8004af6: 689b ldr r3, [r3, #8] 8004af8: f003 030c and.w r3, r3, #12 || \ 8004afc: 2b08 cmp r3, #8 8004afe: d106 bne.n 8004b0e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004b00: 4b8e ldr r3, [pc, #568] @ (8004d3c ) 8004b02: 685b ldr r3, [r3, #4] 8004b04: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004b08: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004b0c: d00c beq.n 8004b28 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8004b0e: 4b8b ldr r3, [pc, #556] @ (8004d3c ) 8004b10: 689b ldr r3, [r3, #8] 8004b12: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004b16: 2b0c cmp r3, #12 8004b18: d112 bne.n 8004b40 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8004b1a: 4b88 ldr r3, [pc, #544] @ (8004d3c ) 8004b1c: 685b ldr r3, [r3, #4] 8004b1e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004b22: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004b26: d10b bne.n 8004b40 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) #endif /* STM32F446xx */ { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004b28: 4b84 ldr r3, [pc, #528] @ (8004d3c ) 8004b2a: 681b ldr r3, [r3, #0] 8004b2c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004b30: 2b00 cmp r3, #0 8004b32: d05b beq.n 8004bec 8004b34: 687b ldr r3, [r7, #4] 8004b36: 685b ldr r3, [r3, #4] 8004b38: 2b00 cmp r3, #0 8004b3a: d157 bne.n 8004bec { return HAL_ERROR; 8004b3c: 2301 movs r3, #1 8004b3e: e25a b.n 8004ff6 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8004b40: 687b ldr r3, [r7, #4] 8004b42: 685b ldr r3, [r3, #4] 8004b44: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004b48: d106 bne.n 8004b58 8004b4a: 4b7c ldr r3, [pc, #496] @ (8004d3c ) 8004b4c: 681b ldr r3, [r3, #0] 8004b4e: 4a7b ldr r2, [pc, #492] @ (8004d3c ) 8004b50: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004b54: 6013 str r3, [r2, #0] 8004b56: e01d b.n 8004b94 8004b58: 687b ldr r3, [r7, #4] 8004b5a: 685b ldr r3, [r3, #4] 8004b5c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8004b60: d10c bne.n 8004b7c 8004b62: 4b76 ldr r3, [pc, #472] @ (8004d3c ) 8004b64: 681b ldr r3, [r3, #0] 8004b66: 4a75 ldr r2, [pc, #468] @ (8004d3c ) 8004b68: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8004b6c: 6013 str r3, [r2, #0] 8004b6e: 4b73 ldr r3, [pc, #460] @ (8004d3c ) 8004b70: 681b ldr r3, [r3, #0] 8004b72: 4a72 ldr r2, [pc, #456] @ (8004d3c ) 8004b74: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004b78: 6013 str r3, [r2, #0] 8004b7a: e00b b.n 8004b94 8004b7c: 4b6f ldr r3, [pc, #444] @ (8004d3c ) 8004b7e: 681b ldr r3, [r3, #0] 8004b80: 4a6e ldr r2, [pc, #440] @ (8004d3c ) 8004b82: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8004b86: 6013 str r3, [r2, #0] 8004b88: 4b6c ldr r3, [pc, #432] @ (8004d3c ) 8004b8a: 681b ldr r3, [r3, #0] 8004b8c: 4a6b ldr r2, [pc, #428] @ (8004d3c ) 8004b8e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8004b92: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 8004b94: 687b ldr r3, [r7, #4] 8004b96: 685b ldr r3, [r3, #4] 8004b98: 2b00 cmp r3, #0 8004b9a: d013 beq.n 8004bc4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004b9c: f7fc fe4c bl 8001838 8004ba0: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004ba2: e008 b.n 8004bb6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004ba4: f7fc fe48 bl 8001838 8004ba8: 4602 mov r2, r0 8004baa: 693b ldr r3, [r7, #16] 8004bac: 1ad3 subs r3, r2, r3 8004bae: 2b64 cmp r3, #100 @ 0x64 8004bb0: d901 bls.n 8004bb6 { return HAL_TIMEOUT; 8004bb2: 2303 movs r3, #3 8004bb4: e21f b.n 8004ff6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004bb6: 4b61 ldr r3, [pc, #388] @ (8004d3c ) 8004bb8: 681b ldr r3, [r3, #0] 8004bba: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004bbe: 2b00 cmp r3, #0 8004bc0: d0f0 beq.n 8004ba4 8004bc2: e014 b.n 8004bee } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004bc4: f7fc fe38 bl 8001838 8004bc8: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004bca: e008 b.n 8004bde { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004bcc: f7fc fe34 bl 8001838 8004bd0: 4602 mov r2, r0 8004bd2: 693b ldr r3, [r7, #16] 8004bd4: 1ad3 subs r3, r2, r3 8004bd6: 2b64 cmp r3, #100 @ 0x64 8004bd8: d901 bls.n 8004bde { return HAL_TIMEOUT; 8004bda: 2303 movs r3, #3 8004bdc: e20b b.n 8004ff6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004bde: 4b57 ldr r3, [pc, #348] @ (8004d3c ) 8004be0: 681b ldr r3, [r3, #0] 8004be2: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004be6: 2b00 cmp r3, #0 8004be8: d1f0 bne.n 8004bcc 8004bea: e000 b.n 8004bee if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004bec: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8004bee: 687b ldr r3, [r7, #4] 8004bf0: 681b ldr r3, [r3, #0] 8004bf2: f003 0302 and.w r3, r3, #2 8004bf6: 2b00 cmp r3, #0 8004bf8: d06f beq.n 8004cda assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 8004bfa: 4b50 ldr r3, [pc, #320] @ (8004d3c ) 8004bfc: 689b ldr r3, [r3, #8] 8004bfe: f003 030c and.w r3, r3, #12 8004c02: 2b00 cmp r3, #0 8004c04: d017 beq.n 8004c36 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004c06: 4b4d ldr r3, [pc, #308] @ (8004d3c ) 8004c08: 689b ldr r3, [r3, #8] 8004c0a: f003 030c and.w r3, r3, #12 || \ 8004c0e: 2b08 cmp r3, #8 8004c10: d105 bne.n 8004c1e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004c12: 4b4a ldr r3, [pc, #296] @ (8004d3c ) 8004c14: 685b ldr r3, [r3, #4] 8004c16: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004c1a: 2b00 cmp r3, #0 8004c1c: d00b beq.n 8004c36 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004c1e: 4b47 ldr r3, [pc, #284] @ (8004d3c ) 8004c20: 689b ldr r3, [r3, #8] 8004c22: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004c26: 2b0c cmp r3, #12 8004c28: d11c bne.n 8004c64 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004c2a: 4b44 ldr r3, [pc, #272] @ (8004d3c ) 8004c2c: 685b ldr r3, [r3, #4] 8004c2e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004c32: 2b00 cmp r3, #0 8004c34: d116 bne.n 8004c64 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) #endif /* STM32F446xx */ { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004c36: 4b41 ldr r3, [pc, #260] @ (8004d3c ) 8004c38: 681b ldr r3, [r3, #0] 8004c3a: f003 0302 and.w r3, r3, #2 8004c3e: 2b00 cmp r3, #0 8004c40: d005 beq.n 8004c4e 8004c42: 687b ldr r3, [r7, #4] 8004c44: 68db ldr r3, [r3, #12] 8004c46: 2b01 cmp r3, #1 8004c48: d001 beq.n 8004c4e { return HAL_ERROR; 8004c4a: 2301 movs r3, #1 8004c4c: e1d3 b.n 8004ff6 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004c4e: 4b3b ldr r3, [pc, #236] @ (8004d3c ) 8004c50: 681b ldr r3, [r3, #0] 8004c52: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004c56: 687b ldr r3, [r7, #4] 8004c58: 691b ldr r3, [r3, #16] 8004c5a: 00db lsls r3, r3, #3 8004c5c: 4937 ldr r1, [pc, #220] @ (8004d3c ) 8004c5e: 4313 orrs r3, r2 8004c60: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004c62: e03a b.n 8004cda } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8004c64: 687b ldr r3, [r7, #4] 8004c66: 68db ldr r3, [r3, #12] 8004c68: 2b00 cmp r3, #0 8004c6a: d020 beq.n 8004cae { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8004c6c: 4b34 ldr r3, [pc, #208] @ (8004d40 ) 8004c6e: 2201 movs r2, #1 8004c70: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004c72: f7fc fde1 bl 8001838 8004c76: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004c78: e008 b.n 8004c8c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004c7a: f7fc fddd bl 8001838 8004c7e: 4602 mov r2, r0 8004c80: 693b ldr r3, [r7, #16] 8004c82: 1ad3 subs r3, r2, r3 8004c84: 2b02 cmp r3, #2 8004c86: d901 bls.n 8004c8c { return HAL_TIMEOUT; 8004c88: 2303 movs r3, #3 8004c8a: e1b4 b.n 8004ff6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004c8c: 4b2b ldr r3, [pc, #172] @ (8004d3c ) 8004c8e: 681b ldr r3, [r3, #0] 8004c90: f003 0302 and.w r3, r3, #2 8004c94: 2b00 cmp r3, #0 8004c96: d0f0 beq.n 8004c7a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004c98: 4b28 ldr r3, [pc, #160] @ (8004d3c ) 8004c9a: 681b ldr r3, [r3, #0] 8004c9c: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004ca0: 687b ldr r3, [r7, #4] 8004ca2: 691b ldr r3, [r3, #16] 8004ca4: 00db lsls r3, r3, #3 8004ca6: 4925 ldr r1, [pc, #148] @ (8004d3c ) 8004ca8: 4313 orrs r3, r2 8004caa: 600b str r3, [r1, #0] 8004cac: e015 b.n 8004cda } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8004cae: 4b24 ldr r3, [pc, #144] @ (8004d40 ) 8004cb0: 2200 movs r2, #0 8004cb2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004cb4: f7fc fdc0 bl 8001838 8004cb8: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004cba: e008 b.n 8004cce { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004cbc: f7fc fdbc bl 8001838 8004cc0: 4602 mov r2, r0 8004cc2: 693b ldr r3, [r7, #16] 8004cc4: 1ad3 subs r3, r2, r3 8004cc6: 2b02 cmp r3, #2 8004cc8: d901 bls.n 8004cce { return HAL_TIMEOUT; 8004cca: 2303 movs r3, #3 8004ccc: e193 b.n 8004ff6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004cce: 4b1b ldr r3, [pc, #108] @ (8004d3c ) 8004cd0: 681b ldr r3, [r3, #0] 8004cd2: f003 0302 and.w r3, r3, #2 8004cd6: 2b00 cmp r3, #0 8004cd8: d1f0 bne.n 8004cbc } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8004cda: 687b ldr r3, [r7, #4] 8004cdc: 681b ldr r3, [r3, #0] 8004cde: f003 0308 and.w r3, r3, #8 8004ce2: 2b00 cmp r3, #0 8004ce4: d036 beq.n 8004d54 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 8004ce6: 687b ldr r3, [r7, #4] 8004ce8: 695b ldr r3, [r3, #20] 8004cea: 2b00 cmp r3, #0 8004cec: d016 beq.n 8004d1c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8004cee: 4b15 ldr r3, [pc, #84] @ (8004d44 ) 8004cf0: 2201 movs r2, #1 8004cf2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004cf4: f7fc fda0 bl 8001838 8004cf8: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004cfa: e008 b.n 8004d0e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004cfc: f7fc fd9c bl 8001838 8004d00: 4602 mov r2, r0 8004d02: 693b ldr r3, [r7, #16] 8004d04: 1ad3 subs r3, r2, r3 8004d06: 2b02 cmp r3, #2 8004d08: d901 bls.n 8004d0e { return HAL_TIMEOUT; 8004d0a: 2303 movs r3, #3 8004d0c: e173 b.n 8004ff6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004d0e: 4b0b ldr r3, [pc, #44] @ (8004d3c ) 8004d10: 6f5b ldr r3, [r3, #116] @ 0x74 8004d12: f003 0302 and.w r3, r3, #2 8004d16: 2b00 cmp r3, #0 8004d18: d0f0 beq.n 8004cfc 8004d1a: e01b b.n 8004d54 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8004d1c: 4b09 ldr r3, [pc, #36] @ (8004d44 ) 8004d1e: 2200 movs r2, #0 8004d20: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004d22: f7fc fd89 bl 8001838 8004d26: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004d28: e00e b.n 8004d48 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004d2a: f7fc fd85 bl 8001838 8004d2e: 4602 mov r2, r0 8004d30: 693b ldr r3, [r7, #16] 8004d32: 1ad3 subs r3, r2, r3 8004d34: 2b02 cmp r3, #2 8004d36: d907 bls.n 8004d48 { return HAL_TIMEOUT; 8004d38: 2303 movs r3, #3 8004d3a: e15c b.n 8004ff6 8004d3c: 40023800 .word 0x40023800 8004d40: 42470000 .word 0x42470000 8004d44: 42470e80 .word 0x42470e80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004d48: 4b8a ldr r3, [pc, #552] @ (8004f74 ) 8004d4a: 6f5b ldr r3, [r3, #116] @ 0x74 8004d4c: f003 0302 and.w r3, r3, #2 8004d50: 2b00 cmp r3, #0 8004d52: d1ea bne.n 8004d2a } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8004d54: 687b ldr r3, [r7, #4] 8004d56: 681b ldr r3, [r3, #0] 8004d58: f003 0304 and.w r3, r3, #4 8004d5c: 2b00 cmp r3, #0 8004d5e: f000 8097 beq.w 8004e90 { FlagStatus pwrclkchanged = RESET; 8004d62: 2300 movs r3, #0 8004d64: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8004d66: 4b83 ldr r3, [pc, #524] @ (8004f74 ) 8004d68: 6c1b ldr r3, [r3, #64] @ 0x40 8004d6a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004d6e: 2b00 cmp r3, #0 8004d70: d10f bne.n 8004d92 { __HAL_RCC_PWR_CLK_ENABLE(); 8004d72: 2300 movs r3, #0 8004d74: 60bb str r3, [r7, #8] 8004d76: 4b7f ldr r3, [pc, #508] @ (8004f74 ) 8004d78: 6c1b ldr r3, [r3, #64] @ 0x40 8004d7a: 4a7e ldr r2, [pc, #504] @ (8004f74 ) 8004d7c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004d80: 6413 str r3, [r2, #64] @ 0x40 8004d82: 4b7c ldr r3, [pc, #496] @ (8004f74 ) 8004d84: 6c1b ldr r3, [r3, #64] @ 0x40 8004d86: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004d8a: 60bb str r3, [r7, #8] 8004d8c: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8004d8e: 2301 movs r3, #1 8004d90: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004d92: 4b79 ldr r3, [pc, #484] @ (8004f78 ) 8004d94: 681b ldr r3, [r3, #0] 8004d96: f403 7380 and.w r3, r3, #256 @ 0x100 8004d9a: 2b00 cmp r3, #0 8004d9c: d118 bne.n 8004dd0 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8004d9e: 4b76 ldr r3, [pc, #472] @ (8004f78 ) 8004da0: 681b ldr r3, [r3, #0] 8004da2: 4a75 ldr r2, [pc, #468] @ (8004f78 ) 8004da4: f443 7380 orr.w r3, r3, #256 @ 0x100 8004da8: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8004daa: f7fc fd45 bl 8001838 8004dae: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004db0: e008 b.n 8004dc4 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004db2: f7fc fd41 bl 8001838 8004db6: 4602 mov r2, r0 8004db8: 693b ldr r3, [r7, #16] 8004dba: 1ad3 subs r3, r2, r3 8004dbc: 2b02 cmp r3, #2 8004dbe: d901 bls.n 8004dc4 { return HAL_TIMEOUT; 8004dc0: 2303 movs r3, #3 8004dc2: e118 b.n 8004ff6 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004dc4: 4b6c ldr r3, [pc, #432] @ (8004f78 ) 8004dc6: 681b ldr r3, [r3, #0] 8004dc8: f403 7380 and.w r3, r3, #256 @ 0x100 8004dcc: 2b00 cmp r3, #0 8004dce: d0f0 beq.n 8004db2 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8004dd0: 687b ldr r3, [r7, #4] 8004dd2: 689b ldr r3, [r3, #8] 8004dd4: 2b01 cmp r3, #1 8004dd6: d106 bne.n 8004de6 8004dd8: 4b66 ldr r3, [pc, #408] @ (8004f74 ) 8004dda: 6f1b ldr r3, [r3, #112] @ 0x70 8004ddc: 4a65 ldr r2, [pc, #404] @ (8004f74 ) 8004dde: f043 0301 orr.w r3, r3, #1 8004de2: 6713 str r3, [r2, #112] @ 0x70 8004de4: e01c b.n 8004e20 8004de6: 687b ldr r3, [r7, #4] 8004de8: 689b ldr r3, [r3, #8] 8004dea: 2b05 cmp r3, #5 8004dec: d10c bne.n 8004e08 8004dee: 4b61 ldr r3, [pc, #388] @ (8004f74 ) 8004df0: 6f1b ldr r3, [r3, #112] @ 0x70 8004df2: 4a60 ldr r2, [pc, #384] @ (8004f74 ) 8004df4: f043 0304 orr.w r3, r3, #4 8004df8: 6713 str r3, [r2, #112] @ 0x70 8004dfa: 4b5e ldr r3, [pc, #376] @ (8004f74 ) 8004dfc: 6f1b ldr r3, [r3, #112] @ 0x70 8004dfe: 4a5d ldr r2, [pc, #372] @ (8004f74 ) 8004e00: f043 0301 orr.w r3, r3, #1 8004e04: 6713 str r3, [r2, #112] @ 0x70 8004e06: e00b b.n 8004e20 8004e08: 4b5a ldr r3, [pc, #360] @ (8004f74 ) 8004e0a: 6f1b ldr r3, [r3, #112] @ 0x70 8004e0c: 4a59 ldr r2, [pc, #356] @ (8004f74 ) 8004e0e: f023 0301 bic.w r3, r3, #1 8004e12: 6713 str r3, [r2, #112] @ 0x70 8004e14: 4b57 ldr r3, [pc, #348] @ (8004f74 ) 8004e16: 6f1b ldr r3, [r3, #112] @ 0x70 8004e18: 4a56 ldr r2, [pc, #344] @ (8004f74 ) 8004e1a: f023 0304 bic.w r3, r3, #4 8004e1e: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8004e20: 687b ldr r3, [r7, #4] 8004e22: 689b ldr r3, [r3, #8] 8004e24: 2b00 cmp r3, #0 8004e26: d015 beq.n 8004e54 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004e28: f7fc fd06 bl 8001838 8004e2c: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004e2e: e00a b.n 8004e46 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004e30: f7fc fd02 bl 8001838 8004e34: 4602 mov r2, r0 8004e36: 693b ldr r3, [r7, #16] 8004e38: 1ad3 subs r3, r2, r3 8004e3a: f241 3288 movw r2, #5000 @ 0x1388 8004e3e: 4293 cmp r3, r2 8004e40: d901 bls.n 8004e46 { return HAL_TIMEOUT; 8004e42: 2303 movs r3, #3 8004e44: e0d7 b.n 8004ff6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004e46: 4b4b ldr r3, [pc, #300] @ (8004f74 ) 8004e48: 6f1b ldr r3, [r3, #112] @ 0x70 8004e4a: f003 0302 and.w r3, r3, #2 8004e4e: 2b00 cmp r3, #0 8004e50: d0ee beq.n 8004e30 8004e52: e014 b.n 8004e7e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004e54: f7fc fcf0 bl 8001838 8004e58: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8004e5a: e00a b.n 8004e72 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004e5c: f7fc fcec bl 8001838 8004e60: 4602 mov r2, r0 8004e62: 693b ldr r3, [r7, #16] 8004e64: 1ad3 subs r3, r2, r3 8004e66: f241 3288 movw r2, #5000 @ 0x1388 8004e6a: 4293 cmp r3, r2 8004e6c: d901 bls.n 8004e72 { return HAL_TIMEOUT; 8004e6e: 2303 movs r3, #3 8004e70: e0c1 b.n 8004ff6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8004e72: 4b40 ldr r3, [pc, #256] @ (8004f74 ) 8004e74: 6f1b ldr r3, [r3, #112] @ 0x70 8004e76: f003 0302 and.w r3, r3, #2 8004e7a: 2b00 cmp r3, #0 8004e7c: d1ee bne.n 8004e5c } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 8004e7e: 7dfb ldrb r3, [r7, #23] 8004e80: 2b01 cmp r3, #1 8004e82: d105 bne.n 8004e90 { __HAL_RCC_PWR_CLK_DISABLE(); 8004e84: 4b3b ldr r3, [pc, #236] @ (8004f74 ) 8004e86: 6c1b ldr r3, [r3, #64] @ 0x40 8004e88: 4a3a ldr r2, [pc, #232] @ (8004f74 ) 8004e8a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8004e8e: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8004e90: 687b ldr r3, [r7, #4] 8004e92: 699b ldr r3, [r3, #24] 8004e94: 2b00 cmp r3, #0 8004e96: f000 80ad beq.w 8004ff4 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 8004e9a: 4b36 ldr r3, [pc, #216] @ (8004f74 ) 8004e9c: 689b ldr r3, [r3, #8] 8004e9e: f003 030c and.w r3, r3, #12 8004ea2: 2b08 cmp r3, #8 8004ea4: d060 beq.n 8004f68 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8004ea6: 687b ldr r3, [r7, #4] 8004ea8: 699b ldr r3, [r3, #24] 8004eaa: 2b02 cmp r3, #2 8004eac: d145 bne.n 8004f3a assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8004eae: 4b33 ldr r3, [pc, #204] @ (8004f7c ) 8004eb0: 2200 movs r2, #0 8004eb2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004eb4: f7fc fcc0 bl 8001838 8004eb8: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004eba: e008 b.n 8004ece { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8004ebc: f7fc fcbc bl 8001838 8004ec0: 4602 mov r2, r0 8004ec2: 693b ldr r3, [r7, #16] 8004ec4: 1ad3 subs r3, r2, r3 8004ec6: 2b02 cmp r3, #2 8004ec8: d901 bls.n 8004ece { return HAL_TIMEOUT; 8004eca: 2303 movs r3, #3 8004ecc: e093 b.n 8004ff6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004ece: 4b29 ldr r3, [pc, #164] @ (8004f74 ) 8004ed0: 681b ldr r3, [r3, #0] 8004ed2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004ed6: 2b00 cmp r3, #0 8004ed8: d1f0 bne.n 8004ebc } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 8004eda: 687b ldr r3, [r7, #4] 8004edc: 69da ldr r2, [r3, #28] 8004ede: 687b ldr r3, [r7, #4] 8004ee0: 6a1b ldr r3, [r3, #32] 8004ee2: 431a orrs r2, r3 8004ee4: 687b ldr r3, [r7, #4] 8004ee6: 6a5b ldr r3, [r3, #36] @ 0x24 8004ee8: 019b lsls r3, r3, #6 8004eea: 431a orrs r2, r3 8004eec: 687b ldr r3, [r7, #4] 8004eee: 6a9b ldr r3, [r3, #40] @ 0x28 8004ef0: 085b lsrs r3, r3, #1 8004ef2: 3b01 subs r3, #1 8004ef4: 041b lsls r3, r3, #16 8004ef6: 431a orrs r2, r3 8004ef8: 687b ldr r3, [r7, #4] 8004efa: 6adb ldr r3, [r3, #44] @ 0x2c 8004efc: 061b lsls r3, r3, #24 8004efe: 431a orrs r2, r3 8004f00: 687b ldr r3, [r7, #4] 8004f02: 6b1b ldr r3, [r3, #48] @ 0x30 8004f04: 071b lsls r3, r3, #28 8004f06: 491b ldr r1, [pc, #108] @ (8004f74 ) 8004f08: 4313 orrs r3, r2 8004f0a: 604b str r3, [r1, #4] (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8004f0c: 4b1b ldr r3, [pc, #108] @ (8004f7c ) 8004f0e: 2201 movs r2, #1 8004f10: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004f12: f7fc fc91 bl 8001838 8004f16: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8004f18: e008 b.n 8004f2c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8004f1a: f7fc fc8d bl 8001838 8004f1e: 4602 mov r2, r0 8004f20: 693b ldr r3, [r7, #16] 8004f22: 1ad3 subs r3, r2, r3 8004f24: 2b02 cmp r3, #2 8004f26: d901 bls.n 8004f2c { return HAL_TIMEOUT; 8004f28: 2303 movs r3, #3 8004f2a: e064 b.n 8004ff6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8004f2c: 4b11 ldr r3, [pc, #68] @ (8004f74 ) 8004f2e: 681b ldr r3, [r3, #0] 8004f30: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004f34: 2b00 cmp r3, #0 8004f36: d0f0 beq.n 8004f1a 8004f38: e05c b.n 8004ff4 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8004f3a: 4b10 ldr r3, [pc, #64] @ (8004f7c ) 8004f3c: 2200 movs r2, #0 8004f3e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004f40: f7fc fc7a bl 8001838 8004f44: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004f46: e008 b.n 8004f5a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8004f48: f7fc fc76 bl 8001838 8004f4c: 4602 mov r2, r0 8004f4e: 693b ldr r3, [r7, #16] 8004f50: 1ad3 subs r3, r2, r3 8004f52: 2b02 cmp r3, #2 8004f54: d901 bls.n 8004f5a { return HAL_TIMEOUT; 8004f56: 2303 movs r3, #3 8004f58: e04d b.n 8004ff6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004f5a: 4b06 ldr r3, [pc, #24] @ (8004f74 ) 8004f5c: 681b ldr r3, [r3, #0] 8004f5e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004f62: 2b00 cmp r3, #0 8004f64: d1f0 bne.n 8004f48 8004f66: e045 b.n 8004ff4 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8004f68: 687b ldr r3, [r7, #4] 8004f6a: 699b ldr r3, [r3, #24] 8004f6c: 2b01 cmp r3, #1 8004f6e: d107 bne.n 8004f80 { return HAL_ERROR; 8004f70: 2301 movs r3, #1 8004f72: e040 b.n 8004ff6 8004f74: 40023800 .word 0x40023800 8004f78: 40007000 .word 0x40007000 8004f7c: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 8004f80: 4b1f ldr r3, [pc, #124] @ (8005000 ) 8004f82: 685b ldr r3, [r3, #4] 8004f84: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8004f86: 687b ldr r3, [r7, #4] 8004f88: 699b ldr r3, [r3, #24] 8004f8a: 2b01 cmp r3, #1 8004f8c: d030 beq.n 8004ff0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8004f8e: 68fb ldr r3, [r7, #12] 8004f90: f403 0280 and.w r2, r3, #4194304 @ 0x400000 8004f94: 687b ldr r3, [r7, #4] 8004f96: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8004f98: 429a cmp r2, r3 8004f9a: d129 bne.n 8004ff0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 8004f9c: 68fb ldr r3, [r7, #12] 8004f9e: f003 023f and.w r2, r3, #63 @ 0x3f 8004fa2: 687b ldr r3, [r7, #4] 8004fa4: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8004fa6: 429a cmp r2, r3 8004fa8: d122 bne.n 8004ff0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 8004faa: 68fa ldr r2, [r7, #12] 8004fac: f647 73c0 movw r3, #32704 @ 0x7fc0 8004fb0: 4013 ands r3, r2 8004fb2: 687a ldr r2, [r7, #4] 8004fb4: 6a52 ldr r2, [r2, #36] @ 0x24 8004fb6: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 8004fb8: 4293 cmp r3, r2 8004fba: d119 bne.n 8004ff0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8004fbc: 68fb ldr r3, [r7, #12] 8004fbe: f403 3240 and.w r2, r3, #196608 @ 0x30000 8004fc2: 687b ldr r3, [r7, #4] 8004fc4: 6a9b ldr r3, [r3, #40] @ 0x28 8004fc6: 085b lsrs r3, r3, #1 8004fc8: 3b01 subs r3, #1 8004fca: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 8004fcc: 429a cmp r2, r3 8004fce: d10f bne.n 8004ff0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 8004fd0: 68fb ldr r3, [r7, #12] 8004fd2: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 8004fd6: 687b ldr r3, [r7, #4] 8004fd8: 6adb ldr r3, [r3, #44] @ 0x2c 8004fda: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8004fdc: 429a cmp r2, r3 8004fde: d107 bne.n 8004ff0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) 8004fe0: 68fb ldr r3, [r7, #12] 8004fe2: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000 8004fe6: 687b ldr r3, [r7, #4] 8004fe8: 6b1b ldr r3, [r3, #48] @ 0x30 8004fea: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 8004fec: 429a cmp r2, r3 8004fee: d001 beq.n 8004ff4 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; 8004ff0: 2301 movs r3, #1 8004ff2: e000 b.n 8004ff6 } } } } return HAL_OK; 8004ff4: 2300 movs r3, #0 } 8004ff6: 4618 mov r0, r3 8004ff8: 3718 adds r7, #24 8004ffa: 46bd mov sp, r7 8004ffc: bd80 pop {r7, pc} 8004ffe: bf00 nop 8005000: 40023800 .word 0x40023800 08005004 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8005004: b580 push {r7, lr} 8005006: b082 sub sp, #8 8005008: af00 add r7, sp, #0 800500a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800500c: 687b ldr r3, [r7, #4] 800500e: 2b00 cmp r3, #0 8005010: d101 bne.n 8005016 { return HAL_ERROR; 8005012: 2301 movs r3, #1 8005014: e041 b.n 800509a assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8005016: 687b ldr r3, [r7, #4] 8005018: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800501c: b2db uxtb r3, r3 800501e: 2b00 cmp r3, #0 8005020: d106 bne.n 8005030 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005022: 687b ldr r3, [r7, #4] 8005024: 2200 movs r2, #0 8005026: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 800502a: 6878 ldr r0, [r7, #4] 800502c: f7fb ff6a bl 8000f04 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005030: 687b ldr r3, [r7, #4] 8005032: 2202 movs r2, #2 8005034: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005038: 687b ldr r3, [r7, #4] 800503a: 681a ldr r2, [r3, #0] 800503c: 687b ldr r3, [r7, #4] 800503e: 3304 adds r3, #4 8005040: 4619 mov r1, r3 8005042: 4610 mov r0, r2 8005044: f000 f930 bl 80052a8 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005048: 687b ldr r3, [r7, #4] 800504a: 2201 movs r2, #1 800504c: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005050: 687b ldr r3, [r7, #4] 8005052: 2201 movs r2, #1 8005054: f883 203e strb.w r2, [r3, #62] @ 0x3e 8005058: 687b ldr r3, [r7, #4] 800505a: 2201 movs r2, #1 800505c: f883 203f strb.w r2, [r3, #63] @ 0x3f 8005060: 687b ldr r3, [r7, #4] 8005062: 2201 movs r2, #1 8005064: f883 2040 strb.w r2, [r3, #64] @ 0x40 8005068: 687b ldr r3, [r7, #4] 800506a: 2201 movs r2, #1 800506c: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005070: 687b ldr r3, [r7, #4] 8005072: 2201 movs r2, #1 8005074: f883 2042 strb.w r2, [r3, #66] @ 0x42 8005078: 687b ldr r3, [r7, #4] 800507a: 2201 movs r2, #1 800507c: f883 2043 strb.w r2, [r3, #67] @ 0x43 8005080: 687b ldr r3, [r7, #4] 8005082: 2201 movs r2, #1 8005084: f883 2044 strb.w r2, [r3, #68] @ 0x44 8005088: 687b ldr r3, [r7, #4] 800508a: 2201 movs r2, #1 800508c: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005090: 687b ldr r3, [r7, #4] 8005092: 2201 movs r2, #1 8005094: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8005098: 2300 movs r3, #0 } 800509a: 4618 mov r0, r3 800509c: 3708 adds r7, #8 800509e: 46bd mov sp, r7 80050a0: bd80 pop {r7, pc} 080050a2 : * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { 80050a2: b580 push {r7, lr} 80050a4: b086 sub sp, #24 80050a6: af00 add r7, sp, #0 80050a8: 6078 str r0, [r7, #4] 80050aa: 6039 str r1, [r7, #0] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) 80050ac: 687b ldr r3, [r7, #4] 80050ae: 2b00 cmp r3, #0 80050b0: d101 bne.n 80050b6 { return HAL_ERROR; 80050b2: 2301 movs r3, #1 80050b4: e097 b.n 80051e6 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) 80050b6: 687b ldr r3, [r7, #4] 80050b8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80050bc: b2db uxtb r3, r3 80050be: 2b00 cmp r3, #0 80050c0: d106 bne.n 80050d0 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80050c2: 687b ldr r3, [r7, #4] 80050c4: 2200 movs r2, #0 80050c6: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); 80050ca: 6878 ldr r0, [r7, #4] 80050cc: f7fb ff3a bl 8000f44 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80050d0: 687b ldr r3, [r7, #4] 80050d2: 2202 movs r2, #2 80050d4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); 80050d8: 687b ldr r3, [r7, #4] 80050da: 681b ldr r3, [r3, #0] 80050dc: 689b ldr r3, [r3, #8] 80050de: 687a ldr r2, [r7, #4] 80050e0: 6812 ldr r2, [r2, #0] 80050e2: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80050e6: f023 0307 bic.w r3, r3, #7 80050ea: 6093 str r3, [r2, #8] /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80050ec: 687b ldr r3, [r7, #4] 80050ee: 681a ldr r2, [r3, #0] 80050f0: 687b ldr r3, [r7, #4] 80050f2: 3304 adds r3, #4 80050f4: 4619 mov r1, r3 80050f6: 4610 mov r0, r2 80050f8: f000 f8d6 bl 80052a8 /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80050fc: 687b ldr r3, [r7, #4] 80050fe: 681b ldr r3, [r3, #0] 8005100: 689b ldr r3, [r3, #8] 8005102: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; 8005104: 687b ldr r3, [r7, #4] 8005106: 681b ldr r3, [r3, #0] 8005108: 699b ldr r3, [r3, #24] 800510a: 613b str r3, [r7, #16] /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; 800510c: 687b ldr r3, [r7, #4] 800510e: 681b ldr r3, [r3, #0] 8005110: 6a1b ldr r3, [r3, #32] 8005112: 60fb str r3, [r7, #12] /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; 8005114: 683b ldr r3, [r7, #0] 8005116: 681b ldr r3, [r3, #0] 8005118: 697a ldr r2, [r7, #20] 800511a: 4313 orrs r3, r2 800511c: 617b str r3, [r7, #20] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 800511e: 693b ldr r3, [r7, #16] 8005120: f423 7340 bic.w r3, r3, #768 @ 0x300 8005124: f023 0303 bic.w r3, r3, #3 8005128: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); 800512a: 683b ldr r3, [r7, #0] 800512c: 689a ldr r2, [r3, #8] 800512e: 683b ldr r3, [r7, #0] 8005130: 699b ldr r3, [r3, #24] 8005132: 021b lsls r3, r3, #8 8005134: 4313 orrs r3, r2 8005136: 693a ldr r2, [r7, #16] 8005138: 4313 orrs r3, r2 800513a: 613b str r3, [r7, #16] /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 800513c: 693b ldr r3, [r7, #16] 800513e: f423 6340 bic.w r3, r3, #3072 @ 0xc00 8005142: f023 030c bic.w r3, r3, #12 8005146: 613b str r3, [r7, #16] tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 8005148: 693b ldr r3, [r7, #16] 800514a: f423 4370 bic.w r3, r3, #61440 @ 0xf000 800514e: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8005152: 613b str r3, [r7, #16] tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); 8005154: 683b ldr r3, [r7, #0] 8005156: 68da ldr r2, [r3, #12] 8005158: 683b ldr r3, [r7, #0] 800515a: 69db ldr r3, [r3, #28] 800515c: 021b lsls r3, r3, #8 800515e: 4313 orrs r3, r2 8005160: 693a ldr r2, [r7, #16] 8005162: 4313 orrs r3, r2 8005164: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); 8005166: 683b ldr r3, [r7, #0] 8005168: 691b ldr r3, [r3, #16] 800516a: 011a lsls r2, r3, #4 800516c: 683b ldr r3, [r7, #0] 800516e: 6a1b ldr r3, [r3, #32] 8005170: 031b lsls r3, r3, #12 8005172: 4313 orrs r3, r2 8005174: 693a ldr r2, [r7, #16] 8005176: 4313 orrs r3, r2 8005178: 613b str r3, [r7, #16] /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 800517a: 68fb ldr r3, [r7, #12] 800517c: f023 0322 bic.w r3, r3, #34 @ 0x22 8005180: 60fb str r3, [r7, #12] tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 8005182: 68fb ldr r3, [r7, #12] 8005184: f023 0388 bic.w r3, r3, #136 @ 0x88 8005188: 60fb str r3, [r7, #12] tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); 800518a: 683b ldr r3, [r7, #0] 800518c: 685a ldr r2, [r3, #4] 800518e: 683b ldr r3, [r7, #0] 8005190: 695b ldr r3, [r3, #20] 8005192: 011b lsls r3, r3, #4 8005194: 4313 orrs r3, r2 8005196: 68fa ldr r2, [r7, #12] 8005198: 4313 orrs r3, r2 800519a: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800519c: 687b ldr r3, [r7, #4] 800519e: 681b ldr r3, [r3, #0] 80051a0: 697a ldr r2, [r7, #20] 80051a2: 609a str r2, [r3, #8] /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; 80051a4: 687b ldr r3, [r7, #4] 80051a6: 681b ldr r3, [r3, #0] 80051a8: 693a ldr r2, [r7, #16] 80051aa: 619a str r2, [r3, #24] /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; 80051ac: 687b ldr r3, [r7, #4] 80051ae: 681b ldr r3, [r3, #0] 80051b0: 68fa ldr r2, [r7, #12] 80051b2: 621a str r2, [r3, #32] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 80051b4: 687b ldr r3, [r7, #4] 80051b6: 2201 movs r2, #1 80051b8: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 80051bc: 687b ldr r3, [r7, #4] 80051be: 2201 movs r2, #1 80051c0: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 80051c4: 687b ldr r3, [r7, #4] 80051c6: 2201 movs r2, #1 80051c8: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 80051cc: 687b ldr r3, [r7, #4] 80051ce: 2201 movs r2, #1 80051d0: f883 2042 strb.w r2, [r3, #66] @ 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 80051d4: 687b ldr r3, [r7, #4] 80051d6: 2201 movs r2, #1 80051d8: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80051dc: 687b ldr r3, [r7, #4] 80051de: 2201 movs r2, #1 80051e0: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80051e4: 2300 movs r3, #0 } 80051e6: 4618 mov r0, r3 80051e8: 3718 adds r7, #24 80051ea: 46bd mov sp, r7 80051ec: bd80 pop {r7, pc} ... 080051f0 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80051f0: b580 push {r7, lr} 80051f2: b086 sub sp, #24 80051f4: af00 add r7, sp, #0 80051f6: 60f8 str r0, [r7, #12] 80051f8: 60b9 str r1, [r7, #8] 80051fa: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80051fc: 2300 movs r3, #0 80051fe: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 8005200: 68fb ldr r3, [r7, #12] 8005202: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005206: 2b01 cmp r3, #1 8005208: d101 bne.n 800520e 800520a: 2302 movs r3, #2 800520c: e048 b.n 80052a0 800520e: 68fb ldr r3, [r7, #12] 8005210: 2201 movs r2, #1 8005212: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8005216: 687b ldr r3, [r7, #4] 8005218: 2b0c cmp r3, #12 800521a: d839 bhi.n 8005290 800521c: a201 add r2, pc, #4 @ (adr r2, 8005224 ) 800521e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005222: bf00 nop 8005224: 08005259 .word 0x08005259 8005228: 08005291 .word 0x08005291 800522c: 08005291 .word 0x08005291 8005230: 08005291 .word 0x08005291 8005234: 08005267 .word 0x08005267 8005238: 08005291 .word 0x08005291 800523c: 08005291 .word 0x08005291 8005240: 08005291 .word 0x08005291 8005244: 08005275 .word 0x08005275 8005248: 08005291 .word 0x08005291 800524c: 08005291 .word 0x08005291 8005250: 08005291 .word 0x08005291 8005254: 08005283 .word 0x08005283 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8005258: 68fb ldr r3, [r7, #12] 800525a: 681b ldr r3, [r3, #0] 800525c: 68b9 ldr r1, [r7, #8] 800525e: 4618 mov r0, r3 8005260: f000 f8c8 bl 80053f4 break; 8005264: e017 b.n 8005296 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8005266: 68fb ldr r3, [r7, #12] 8005268: 681b ldr r3, [r3, #0] 800526a: 68b9 ldr r1, [r7, #8] 800526c: 4618 mov r0, r3 800526e: f000 f931 bl 80054d4 break; 8005272: e010 b.n 8005296 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8005274: 68fb ldr r3, [r7, #12] 8005276: 681b ldr r3, [r3, #0] 8005278: 68b9 ldr r1, [r7, #8] 800527a: 4618 mov r0, r3 800527c: f000 f9a0 bl 80055c0 break; 8005280: e009 b.n 8005296 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8005282: 68fb ldr r3, [r7, #12] 8005284: 681b ldr r3, [r3, #0] 8005286: 68b9 ldr r1, [r7, #8] 8005288: 4618 mov r0, r3 800528a: f000 fa0d bl 80056a8 break; 800528e: e002 b.n 8005296 } default: status = HAL_ERROR; 8005290: 2301 movs r3, #1 8005292: 75fb strb r3, [r7, #23] break; 8005294: bf00 nop } __HAL_UNLOCK(htim); 8005296: 68fb ldr r3, [r7, #12] 8005298: 2200 movs r2, #0 800529a: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800529e: 7dfb ldrb r3, [r7, #23] } 80052a0: 4618 mov r0, r3 80052a2: 3718 adds r7, #24 80052a4: 46bd mov sp, r7 80052a6: bd80 pop {r7, pc} 080052a8 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 80052a8: b480 push {r7} 80052aa: b085 sub sp, #20 80052ac: af00 add r7, sp, #0 80052ae: 6078 str r0, [r7, #4] 80052b0: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80052b2: 687b ldr r3, [r7, #4] 80052b4: 681b ldr r3, [r3, #0] 80052b6: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80052b8: 687b ldr r3, [r7, #4] 80052ba: 4a43 ldr r2, [pc, #268] @ (80053c8 ) 80052bc: 4293 cmp r3, r2 80052be: d013 beq.n 80052e8 80052c0: 687b ldr r3, [r7, #4] 80052c2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80052c6: d00f beq.n 80052e8 80052c8: 687b ldr r3, [r7, #4] 80052ca: 4a40 ldr r2, [pc, #256] @ (80053cc ) 80052cc: 4293 cmp r3, r2 80052ce: d00b beq.n 80052e8 80052d0: 687b ldr r3, [r7, #4] 80052d2: 4a3f ldr r2, [pc, #252] @ (80053d0 ) 80052d4: 4293 cmp r3, r2 80052d6: d007 beq.n 80052e8 80052d8: 687b ldr r3, [r7, #4] 80052da: 4a3e ldr r2, [pc, #248] @ (80053d4 ) 80052dc: 4293 cmp r3, r2 80052de: d003 beq.n 80052e8 80052e0: 687b ldr r3, [r7, #4] 80052e2: 4a3d ldr r2, [pc, #244] @ (80053d8 ) 80052e4: 4293 cmp r3, r2 80052e6: d108 bne.n 80052fa { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80052e8: 68fb ldr r3, [r7, #12] 80052ea: f023 0370 bic.w r3, r3, #112 @ 0x70 80052ee: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80052f0: 683b ldr r3, [r7, #0] 80052f2: 685b ldr r3, [r3, #4] 80052f4: 68fa ldr r2, [r7, #12] 80052f6: 4313 orrs r3, r2 80052f8: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80052fa: 687b ldr r3, [r7, #4] 80052fc: 4a32 ldr r2, [pc, #200] @ (80053c8 ) 80052fe: 4293 cmp r3, r2 8005300: d02b beq.n 800535a 8005302: 687b ldr r3, [r7, #4] 8005304: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005308: d027 beq.n 800535a 800530a: 687b ldr r3, [r7, #4] 800530c: 4a2f ldr r2, [pc, #188] @ (80053cc ) 800530e: 4293 cmp r3, r2 8005310: d023 beq.n 800535a 8005312: 687b ldr r3, [r7, #4] 8005314: 4a2e ldr r2, [pc, #184] @ (80053d0 ) 8005316: 4293 cmp r3, r2 8005318: d01f beq.n 800535a 800531a: 687b ldr r3, [r7, #4] 800531c: 4a2d ldr r2, [pc, #180] @ (80053d4 ) 800531e: 4293 cmp r3, r2 8005320: d01b beq.n 800535a 8005322: 687b ldr r3, [r7, #4] 8005324: 4a2c ldr r2, [pc, #176] @ (80053d8 ) 8005326: 4293 cmp r3, r2 8005328: d017 beq.n 800535a 800532a: 687b ldr r3, [r7, #4] 800532c: 4a2b ldr r2, [pc, #172] @ (80053dc ) 800532e: 4293 cmp r3, r2 8005330: d013 beq.n 800535a 8005332: 687b ldr r3, [r7, #4] 8005334: 4a2a ldr r2, [pc, #168] @ (80053e0 ) 8005336: 4293 cmp r3, r2 8005338: d00f beq.n 800535a 800533a: 687b ldr r3, [r7, #4] 800533c: 4a29 ldr r2, [pc, #164] @ (80053e4 ) 800533e: 4293 cmp r3, r2 8005340: d00b beq.n 800535a 8005342: 687b ldr r3, [r7, #4] 8005344: 4a28 ldr r2, [pc, #160] @ (80053e8 ) 8005346: 4293 cmp r3, r2 8005348: d007 beq.n 800535a 800534a: 687b ldr r3, [r7, #4] 800534c: 4a27 ldr r2, [pc, #156] @ (80053ec ) 800534e: 4293 cmp r3, r2 8005350: d003 beq.n 800535a 8005352: 687b ldr r3, [r7, #4] 8005354: 4a26 ldr r2, [pc, #152] @ (80053f0 ) 8005356: 4293 cmp r3, r2 8005358: d108 bne.n 800536c { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800535a: 68fb ldr r3, [r7, #12] 800535c: f423 7340 bic.w r3, r3, #768 @ 0x300 8005360: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8005362: 683b ldr r3, [r7, #0] 8005364: 68db ldr r3, [r3, #12] 8005366: 68fa ldr r2, [r7, #12] 8005368: 4313 orrs r3, r2 800536a: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800536c: 68fb ldr r3, [r7, #12] 800536e: f023 0280 bic.w r2, r3, #128 @ 0x80 8005372: 683b ldr r3, [r7, #0] 8005374: 695b ldr r3, [r3, #20] 8005376: 4313 orrs r3, r2 8005378: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800537a: 683b ldr r3, [r7, #0] 800537c: 689a ldr r2, [r3, #8] 800537e: 687b ldr r3, [r7, #4] 8005380: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8005382: 683b ldr r3, [r7, #0] 8005384: 681a ldr r2, [r3, #0] 8005386: 687b ldr r3, [r7, #4] 8005388: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800538a: 687b ldr r3, [r7, #4] 800538c: 4a0e ldr r2, [pc, #56] @ (80053c8 ) 800538e: 4293 cmp r3, r2 8005390: d003 beq.n 800539a 8005392: 687b ldr r3, [r7, #4] 8005394: 4a10 ldr r2, [pc, #64] @ (80053d8 ) 8005396: 4293 cmp r3, r2 8005398: d103 bne.n 80053a2 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800539a: 683b ldr r3, [r7, #0] 800539c: 691a ldr r2, [r3, #16] 800539e: 687b ldr r3, [r7, #4] 80053a0: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 80053a2: 687b ldr r3, [r7, #4] 80053a4: 681b ldr r3, [r3, #0] 80053a6: f043 0204 orr.w r2, r3, #4 80053aa: 687b ldr r3, [r7, #4] 80053ac: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 80053ae: 687b ldr r3, [r7, #4] 80053b0: 2201 movs r2, #1 80053b2: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 80053b4: 687b ldr r3, [r7, #4] 80053b6: 68fa ldr r2, [r7, #12] 80053b8: 601a str r2, [r3, #0] } 80053ba: bf00 nop 80053bc: 3714 adds r7, #20 80053be: 46bd mov sp, r7 80053c0: f85d 7b04 ldr.w r7, [sp], #4 80053c4: 4770 bx lr 80053c6: bf00 nop 80053c8: 40010000 .word 0x40010000 80053cc: 40000400 .word 0x40000400 80053d0: 40000800 .word 0x40000800 80053d4: 40000c00 .word 0x40000c00 80053d8: 40010400 .word 0x40010400 80053dc: 40014000 .word 0x40014000 80053e0: 40014400 .word 0x40014400 80053e4: 40014800 .word 0x40014800 80053e8: 40001800 .word 0x40001800 80053ec: 40001c00 .word 0x40001c00 80053f0: 40002000 .word 0x40002000 080053f4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80053f4: b480 push {r7} 80053f6: b087 sub sp, #28 80053f8: af00 add r7, sp, #0 80053fa: 6078 str r0, [r7, #4] 80053fc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80053fe: 687b ldr r3, [r7, #4] 8005400: 6a1b ldr r3, [r3, #32] 8005402: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8005404: 687b ldr r3, [r7, #4] 8005406: 6a1b ldr r3, [r3, #32] 8005408: f023 0201 bic.w r2, r3, #1 800540c: 687b ldr r3, [r7, #4] 800540e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005410: 687b ldr r3, [r7, #4] 8005412: 685b ldr r3, [r3, #4] 8005414: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8005416: 687b ldr r3, [r7, #4] 8005418: 699b ldr r3, [r3, #24] 800541a: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 800541c: 68fb ldr r3, [r7, #12] 800541e: f023 0370 bic.w r3, r3, #112 @ 0x70 8005422: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8005424: 68fb ldr r3, [r7, #12] 8005426: f023 0303 bic.w r3, r3, #3 800542a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800542c: 683b ldr r3, [r7, #0] 800542e: 681b ldr r3, [r3, #0] 8005430: 68fa ldr r2, [r7, #12] 8005432: 4313 orrs r3, r2 8005434: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8005436: 697b ldr r3, [r7, #20] 8005438: f023 0302 bic.w r3, r3, #2 800543c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800543e: 683b ldr r3, [r7, #0] 8005440: 689b ldr r3, [r3, #8] 8005442: 697a ldr r2, [r7, #20] 8005444: 4313 orrs r3, r2 8005446: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8005448: 687b ldr r3, [r7, #4] 800544a: 4a20 ldr r2, [pc, #128] @ (80054cc ) 800544c: 4293 cmp r3, r2 800544e: d003 beq.n 8005458 8005450: 687b ldr r3, [r7, #4] 8005452: 4a1f ldr r2, [pc, #124] @ (80054d0 ) 8005454: 4293 cmp r3, r2 8005456: d10c bne.n 8005472 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8005458: 697b ldr r3, [r7, #20] 800545a: f023 0308 bic.w r3, r3, #8 800545e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8005460: 683b ldr r3, [r7, #0] 8005462: 68db ldr r3, [r3, #12] 8005464: 697a ldr r2, [r7, #20] 8005466: 4313 orrs r3, r2 8005468: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 800546a: 697b ldr r3, [r7, #20] 800546c: f023 0304 bic.w r3, r3, #4 8005470: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005472: 687b ldr r3, [r7, #4] 8005474: 4a15 ldr r2, [pc, #84] @ (80054cc ) 8005476: 4293 cmp r3, r2 8005478: d003 beq.n 8005482 800547a: 687b ldr r3, [r7, #4] 800547c: 4a14 ldr r2, [pc, #80] @ (80054d0 ) 800547e: 4293 cmp r3, r2 8005480: d111 bne.n 80054a6 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8005482: 693b ldr r3, [r7, #16] 8005484: f423 7380 bic.w r3, r3, #256 @ 0x100 8005488: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 800548a: 693b ldr r3, [r7, #16] 800548c: f423 7300 bic.w r3, r3, #512 @ 0x200 8005490: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8005492: 683b ldr r3, [r7, #0] 8005494: 695b ldr r3, [r3, #20] 8005496: 693a ldr r2, [r7, #16] 8005498: 4313 orrs r3, r2 800549a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800549c: 683b ldr r3, [r7, #0] 800549e: 699b ldr r3, [r3, #24] 80054a0: 693a ldr r2, [r7, #16] 80054a2: 4313 orrs r3, r2 80054a4: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80054a6: 687b ldr r3, [r7, #4] 80054a8: 693a ldr r2, [r7, #16] 80054aa: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80054ac: 687b ldr r3, [r7, #4] 80054ae: 68fa ldr r2, [r7, #12] 80054b0: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 80054b2: 683b ldr r3, [r7, #0] 80054b4: 685a ldr r2, [r3, #4] 80054b6: 687b ldr r3, [r7, #4] 80054b8: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80054ba: 687b ldr r3, [r7, #4] 80054bc: 697a ldr r2, [r7, #20] 80054be: 621a str r2, [r3, #32] } 80054c0: bf00 nop 80054c2: 371c adds r7, #28 80054c4: 46bd mov sp, r7 80054c6: f85d 7b04 ldr.w r7, [sp], #4 80054ca: 4770 bx lr 80054cc: 40010000 .word 0x40010000 80054d0: 40010400 .word 0x40010400 080054d4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80054d4: b480 push {r7} 80054d6: b087 sub sp, #28 80054d8: af00 add r7, sp, #0 80054da: 6078 str r0, [r7, #4] 80054dc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80054de: 687b ldr r3, [r7, #4] 80054e0: 6a1b ldr r3, [r3, #32] 80054e2: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80054e4: 687b ldr r3, [r7, #4] 80054e6: 6a1b ldr r3, [r3, #32] 80054e8: f023 0210 bic.w r2, r3, #16 80054ec: 687b ldr r3, [r7, #4] 80054ee: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80054f0: 687b ldr r3, [r7, #4] 80054f2: 685b ldr r3, [r3, #4] 80054f4: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80054f6: 687b ldr r3, [r7, #4] 80054f8: 699b ldr r3, [r3, #24] 80054fa: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80054fc: 68fb ldr r3, [r7, #12] 80054fe: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8005502: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8005504: 68fb ldr r3, [r7, #12] 8005506: f423 7340 bic.w r3, r3, #768 @ 0x300 800550a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800550c: 683b ldr r3, [r7, #0] 800550e: 681b ldr r3, [r3, #0] 8005510: 021b lsls r3, r3, #8 8005512: 68fa ldr r2, [r7, #12] 8005514: 4313 orrs r3, r2 8005516: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8005518: 697b ldr r3, [r7, #20] 800551a: f023 0320 bic.w r3, r3, #32 800551e: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8005520: 683b ldr r3, [r7, #0] 8005522: 689b ldr r3, [r3, #8] 8005524: 011b lsls r3, r3, #4 8005526: 697a ldr r2, [r7, #20] 8005528: 4313 orrs r3, r2 800552a: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 800552c: 687b ldr r3, [r7, #4] 800552e: 4a22 ldr r2, [pc, #136] @ (80055b8 ) 8005530: 4293 cmp r3, r2 8005532: d003 beq.n 800553c 8005534: 687b ldr r3, [r7, #4] 8005536: 4a21 ldr r2, [pc, #132] @ (80055bc ) 8005538: 4293 cmp r3, r2 800553a: d10d bne.n 8005558 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 800553c: 697b ldr r3, [r7, #20] 800553e: f023 0380 bic.w r3, r3, #128 @ 0x80 8005542: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8005544: 683b ldr r3, [r7, #0] 8005546: 68db ldr r3, [r3, #12] 8005548: 011b lsls r3, r3, #4 800554a: 697a ldr r2, [r7, #20] 800554c: 4313 orrs r3, r2 800554e: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8005550: 697b ldr r3, [r7, #20] 8005552: f023 0340 bic.w r3, r3, #64 @ 0x40 8005556: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005558: 687b ldr r3, [r7, #4] 800555a: 4a17 ldr r2, [pc, #92] @ (80055b8 ) 800555c: 4293 cmp r3, r2 800555e: d003 beq.n 8005568 8005560: 687b ldr r3, [r7, #4] 8005562: 4a16 ldr r2, [pc, #88] @ (80055bc ) 8005564: 4293 cmp r3, r2 8005566: d113 bne.n 8005590 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8005568: 693b ldr r3, [r7, #16] 800556a: f423 6380 bic.w r3, r3, #1024 @ 0x400 800556e: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8005570: 693b ldr r3, [r7, #16] 8005572: f423 6300 bic.w r3, r3, #2048 @ 0x800 8005576: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8005578: 683b ldr r3, [r7, #0] 800557a: 695b ldr r3, [r3, #20] 800557c: 009b lsls r3, r3, #2 800557e: 693a ldr r2, [r7, #16] 8005580: 4313 orrs r3, r2 8005582: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8005584: 683b ldr r3, [r7, #0] 8005586: 699b ldr r3, [r3, #24] 8005588: 009b lsls r3, r3, #2 800558a: 693a ldr r2, [r7, #16] 800558c: 4313 orrs r3, r2 800558e: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005590: 687b ldr r3, [r7, #4] 8005592: 693a ldr r2, [r7, #16] 8005594: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8005596: 687b ldr r3, [r7, #4] 8005598: 68fa ldr r2, [r7, #12] 800559a: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 800559c: 683b ldr r3, [r7, #0] 800559e: 685a ldr r2, [r3, #4] 80055a0: 687b ldr r3, [r7, #4] 80055a2: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80055a4: 687b ldr r3, [r7, #4] 80055a6: 697a ldr r2, [r7, #20] 80055a8: 621a str r2, [r3, #32] } 80055aa: bf00 nop 80055ac: 371c adds r7, #28 80055ae: 46bd mov sp, r7 80055b0: f85d 7b04 ldr.w r7, [sp], #4 80055b4: 4770 bx lr 80055b6: bf00 nop 80055b8: 40010000 .word 0x40010000 80055bc: 40010400 .word 0x40010400 080055c0 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80055c0: b480 push {r7} 80055c2: b087 sub sp, #28 80055c4: af00 add r7, sp, #0 80055c6: 6078 str r0, [r7, #4] 80055c8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80055ca: 687b ldr r3, [r7, #4] 80055cc: 6a1b ldr r3, [r3, #32] 80055ce: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 80055d0: 687b ldr r3, [r7, #4] 80055d2: 6a1b ldr r3, [r3, #32] 80055d4: f423 7280 bic.w r2, r3, #256 @ 0x100 80055d8: 687b ldr r3, [r7, #4] 80055da: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80055dc: 687b ldr r3, [r7, #4] 80055de: 685b ldr r3, [r3, #4] 80055e0: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80055e2: 687b ldr r3, [r7, #4] 80055e4: 69db ldr r3, [r3, #28] 80055e6: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 80055e8: 68fb ldr r3, [r7, #12] 80055ea: f023 0370 bic.w r3, r3, #112 @ 0x70 80055ee: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 80055f0: 68fb ldr r3, [r7, #12] 80055f2: f023 0303 bic.w r3, r3, #3 80055f6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80055f8: 683b ldr r3, [r7, #0] 80055fa: 681b ldr r3, [r3, #0] 80055fc: 68fa ldr r2, [r7, #12] 80055fe: 4313 orrs r3, r2 8005600: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8005602: 697b ldr r3, [r7, #20] 8005604: f423 7300 bic.w r3, r3, #512 @ 0x200 8005608: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 800560a: 683b ldr r3, [r7, #0] 800560c: 689b ldr r3, [r3, #8] 800560e: 021b lsls r3, r3, #8 8005610: 697a ldr r2, [r7, #20] 8005612: 4313 orrs r3, r2 8005614: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8005616: 687b ldr r3, [r7, #4] 8005618: 4a21 ldr r2, [pc, #132] @ (80056a0 ) 800561a: 4293 cmp r3, r2 800561c: d003 beq.n 8005626 800561e: 687b ldr r3, [r7, #4] 8005620: 4a20 ldr r2, [pc, #128] @ (80056a4 ) 8005622: 4293 cmp r3, r2 8005624: d10d bne.n 8005642 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8005626: 697b ldr r3, [r7, #20] 8005628: f423 6300 bic.w r3, r3, #2048 @ 0x800 800562c: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 800562e: 683b ldr r3, [r7, #0] 8005630: 68db ldr r3, [r3, #12] 8005632: 021b lsls r3, r3, #8 8005634: 697a ldr r2, [r7, #20] 8005636: 4313 orrs r3, r2 8005638: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 800563a: 697b ldr r3, [r7, #20] 800563c: f423 6380 bic.w r3, r3, #1024 @ 0x400 8005640: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005642: 687b ldr r3, [r7, #4] 8005644: 4a16 ldr r2, [pc, #88] @ (80056a0 ) 8005646: 4293 cmp r3, r2 8005648: d003 beq.n 8005652 800564a: 687b ldr r3, [r7, #4] 800564c: 4a15 ldr r2, [pc, #84] @ (80056a4 ) 800564e: 4293 cmp r3, r2 8005650: d113 bne.n 800567a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8005652: 693b ldr r3, [r7, #16] 8005654: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8005658: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 800565a: 693b ldr r3, [r7, #16] 800565c: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8005660: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8005662: 683b ldr r3, [r7, #0] 8005664: 695b ldr r3, [r3, #20] 8005666: 011b lsls r3, r3, #4 8005668: 693a ldr r2, [r7, #16] 800566a: 4313 orrs r3, r2 800566c: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 800566e: 683b ldr r3, [r7, #0] 8005670: 699b ldr r3, [r3, #24] 8005672: 011b lsls r3, r3, #4 8005674: 693a ldr r2, [r7, #16] 8005676: 4313 orrs r3, r2 8005678: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800567a: 687b ldr r3, [r7, #4] 800567c: 693a ldr r2, [r7, #16] 800567e: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8005680: 687b ldr r3, [r7, #4] 8005682: 68fa ldr r2, [r7, #12] 8005684: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8005686: 683b ldr r3, [r7, #0] 8005688: 685a ldr r2, [r3, #4] 800568a: 687b ldr r3, [r7, #4] 800568c: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800568e: 687b ldr r3, [r7, #4] 8005690: 697a ldr r2, [r7, #20] 8005692: 621a str r2, [r3, #32] } 8005694: bf00 nop 8005696: 371c adds r7, #28 8005698: 46bd mov sp, r7 800569a: f85d 7b04 ldr.w r7, [sp], #4 800569e: 4770 bx lr 80056a0: 40010000 .word 0x40010000 80056a4: 40010400 .word 0x40010400 080056a8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80056a8: b480 push {r7} 80056aa: b087 sub sp, #28 80056ac: af00 add r7, sp, #0 80056ae: 6078 str r0, [r7, #4] 80056b0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80056b2: 687b ldr r3, [r7, #4] 80056b4: 6a1b ldr r3, [r3, #32] 80056b6: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 80056b8: 687b ldr r3, [r7, #4] 80056ba: 6a1b ldr r3, [r3, #32] 80056bc: f423 5280 bic.w r2, r3, #4096 @ 0x1000 80056c0: 687b ldr r3, [r7, #4] 80056c2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80056c4: 687b ldr r3, [r7, #4] 80056c6: 685b ldr r3, [r3, #4] 80056c8: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80056ca: 687b ldr r3, [r7, #4] 80056cc: 69db ldr r3, [r3, #28] 80056ce: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 80056d0: 68fb ldr r3, [r7, #12] 80056d2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80056d6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 80056d8: 68fb ldr r3, [r7, #12] 80056da: f423 7340 bic.w r3, r3, #768 @ 0x300 80056de: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80056e0: 683b ldr r3, [r7, #0] 80056e2: 681b ldr r3, [r3, #0] 80056e4: 021b lsls r3, r3, #8 80056e6: 68fa ldr r2, [r7, #12] 80056e8: 4313 orrs r3, r2 80056ea: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 80056ec: 693b ldr r3, [r7, #16] 80056ee: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80056f2: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 80056f4: 683b ldr r3, [r7, #0] 80056f6: 689b ldr r3, [r3, #8] 80056f8: 031b lsls r3, r3, #12 80056fa: 693a ldr r2, [r7, #16] 80056fc: 4313 orrs r3, r2 80056fe: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005700: 687b ldr r3, [r7, #4] 8005702: 4a12 ldr r2, [pc, #72] @ (800574c ) 8005704: 4293 cmp r3, r2 8005706: d003 beq.n 8005710 8005708: 687b ldr r3, [r7, #4] 800570a: 4a11 ldr r2, [pc, #68] @ (8005750 ) 800570c: 4293 cmp r3, r2 800570e: d109 bne.n 8005724 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8005710: 697b ldr r3, [r7, #20] 8005712: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8005716: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8005718: 683b ldr r3, [r7, #0] 800571a: 695b ldr r3, [r3, #20] 800571c: 019b lsls r3, r3, #6 800571e: 697a ldr r2, [r7, #20] 8005720: 4313 orrs r3, r2 8005722: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005724: 687b ldr r3, [r7, #4] 8005726: 697a ldr r2, [r7, #20] 8005728: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800572a: 687b ldr r3, [r7, #4] 800572c: 68fa ldr r2, [r7, #12] 800572e: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8005730: 683b ldr r3, [r7, #0] 8005732: 685a ldr r2, [r3, #4] 8005734: 687b ldr r3, [r7, #4] 8005736: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005738: 687b ldr r3, [r7, #4] 800573a: 693a ldr r2, [r7, #16] 800573c: 621a str r2, [r3, #32] } 800573e: bf00 nop 8005740: 371c adds r7, #28 8005742: 46bd mov sp, r7 8005744: f85d 7b04 ldr.w r7, [sp], #4 8005748: 4770 bx lr 800574a: bf00 nop 800574c: 40010000 .word 0x40010000 8005750: 40010400 .word 0x40010400 08005754 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8005754: b480 push {r7} 8005756: b085 sub sp, #20 8005758: af00 add r7, sp, #0 800575a: 6078 str r0, [r7, #4] 800575c: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800575e: 687b ldr r3, [r7, #4] 8005760: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005764: 2b01 cmp r3, #1 8005766: d101 bne.n 800576c 8005768: 2302 movs r3, #2 800576a: e05a b.n 8005822 800576c: 687b ldr r3, [r7, #4] 800576e: 2201 movs r2, #1 8005770: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8005774: 687b ldr r3, [r7, #4] 8005776: 2202 movs r2, #2 8005778: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 800577c: 687b ldr r3, [r7, #4] 800577e: 681b ldr r3, [r3, #0] 8005780: 685b ldr r3, [r3, #4] 8005782: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005784: 687b ldr r3, [r7, #4] 8005786: 681b ldr r3, [r3, #0] 8005788: 689b ldr r3, [r3, #8] 800578a: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 800578c: 68fb ldr r3, [r7, #12] 800578e: f023 0370 bic.w r3, r3, #112 @ 0x70 8005792: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8005794: 683b ldr r3, [r7, #0] 8005796: 681b ldr r3, [r3, #0] 8005798: 68fa ldr r2, [r7, #12] 800579a: 4313 orrs r3, r2 800579c: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 800579e: 687b ldr r3, [r7, #4] 80057a0: 681b ldr r3, [r3, #0] 80057a2: 68fa ldr r2, [r7, #12] 80057a4: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80057a6: 687b ldr r3, [r7, #4] 80057a8: 681b ldr r3, [r3, #0] 80057aa: 4a21 ldr r2, [pc, #132] @ (8005830 ) 80057ac: 4293 cmp r3, r2 80057ae: d022 beq.n 80057f6 80057b0: 687b ldr r3, [r7, #4] 80057b2: 681b ldr r3, [r3, #0] 80057b4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80057b8: d01d beq.n 80057f6 80057ba: 687b ldr r3, [r7, #4] 80057bc: 681b ldr r3, [r3, #0] 80057be: 4a1d ldr r2, [pc, #116] @ (8005834 ) 80057c0: 4293 cmp r3, r2 80057c2: d018 beq.n 80057f6 80057c4: 687b ldr r3, [r7, #4] 80057c6: 681b ldr r3, [r3, #0] 80057c8: 4a1b ldr r2, [pc, #108] @ (8005838 ) 80057ca: 4293 cmp r3, r2 80057cc: d013 beq.n 80057f6 80057ce: 687b ldr r3, [r7, #4] 80057d0: 681b ldr r3, [r3, #0] 80057d2: 4a1a ldr r2, [pc, #104] @ (800583c ) 80057d4: 4293 cmp r3, r2 80057d6: d00e beq.n 80057f6 80057d8: 687b ldr r3, [r7, #4] 80057da: 681b ldr r3, [r3, #0] 80057dc: 4a18 ldr r2, [pc, #96] @ (8005840 ) 80057de: 4293 cmp r3, r2 80057e0: d009 beq.n 80057f6 80057e2: 687b ldr r3, [r7, #4] 80057e4: 681b ldr r3, [r3, #0] 80057e6: 4a17 ldr r2, [pc, #92] @ (8005844 ) 80057e8: 4293 cmp r3, r2 80057ea: d004 beq.n 80057f6 80057ec: 687b ldr r3, [r7, #4] 80057ee: 681b ldr r3, [r3, #0] 80057f0: 4a15 ldr r2, [pc, #84] @ (8005848 ) 80057f2: 4293 cmp r3, r2 80057f4: d10c bne.n 8005810 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80057f6: 68bb ldr r3, [r7, #8] 80057f8: f023 0380 bic.w r3, r3, #128 @ 0x80 80057fc: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80057fe: 683b ldr r3, [r7, #0] 8005800: 685b ldr r3, [r3, #4] 8005802: 68ba ldr r2, [r7, #8] 8005804: 4313 orrs r3, r2 8005806: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005808: 687b ldr r3, [r7, #4] 800580a: 681b ldr r3, [r3, #0] 800580c: 68ba ldr r2, [r7, #8] 800580e: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8005810: 687b ldr r3, [r7, #4] 8005812: 2201 movs r2, #1 8005814: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8005818: 687b ldr r3, [r7, #4] 800581a: 2200 movs r2, #0 800581c: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8005820: 2300 movs r3, #0 } 8005822: 4618 mov r0, r3 8005824: 3714 adds r7, #20 8005826: 46bd mov sp, r7 8005828: f85d 7b04 ldr.w r7, [sp], #4 800582c: 4770 bx lr 800582e: bf00 nop 8005830: 40010000 .word 0x40010000 8005834: 40000400 .word 0x40000400 8005838: 40000800 .word 0x40000800 800583c: 40000c00 .word 0x40000c00 8005840: 40010400 .word 0x40010400 8005844: 40014000 .word 0x40014000 8005848: 40001800 .word 0x40001800 0800584c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 800584c: b580 push {r7, lr} 800584e: b082 sub sp, #8 8005850: af00 add r7, sp, #0 8005852: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8005854: 687b ldr r3, [r7, #4] 8005856: 2b00 cmp r3, #0 8005858: d101 bne.n 800585e { return HAL_ERROR; 800585a: 2301 movs r3, #1 800585c: e042 b.n 80058e4 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 800585e: 687b ldr r3, [r7, #4] 8005860: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005864: b2db uxtb r3, r3 8005866: 2b00 cmp r3, #0 8005868: d106 bne.n 8005878 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800586a: 687b ldr r3, [r7, #4] 800586c: 2200 movs r2, #0 800586e: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8005872: 6878 ldr r0, [r7, #4] 8005874: f7fb fc8e bl 8001194 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8005878: 687b ldr r3, [r7, #4] 800587a: 2224 movs r2, #36 @ 0x24 800587c: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8005880: 687b ldr r3, [r7, #4] 8005882: 681b ldr r3, [r3, #0] 8005884: 68da ldr r2, [r3, #12] 8005886: 687b ldr r3, [r7, #4] 8005888: 681b ldr r3, [r3, #0] 800588a: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800588e: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8005890: 6878 ldr r0, [r7, #4] 8005892: f000 fde3 bl 800645c /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8005896: 687b ldr r3, [r7, #4] 8005898: 681b ldr r3, [r3, #0] 800589a: 691a ldr r2, [r3, #16] 800589c: 687b ldr r3, [r7, #4] 800589e: 681b ldr r3, [r3, #0] 80058a0: f422 4290 bic.w r2, r2, #18432 @ 0x4800 80058a4: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80058a6: 687b ldr r3, [r7, #4] 80058a8: 681b ldr r3, [r3, #0] 80058aa: 695a ldr r2, [r3, #20] 80058ac: 687b ldr r3, [r7, #4] 80058ae: 681b ldr r3, [r3, #0] 80058b0: f022 022a bic.w r2, r2, #42 @ 0x2a 80058b4: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 80058b6: 687b ldr r3, [r7, #4] 80058b8: 681b ldr r3, [r3, #0] 80058ba: 68da ldr r2, [r3, #12] 80058bc: 687b ldr r3, [r7, #4] 80058be: 681b ldr r3, [r3, #0] 80058c0: f442 5200 orr.w r2, r2, #8192 @ 0x2000 80058c4: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80058c6: 687b ldr r3, [r7, #4] 80058c8: 2200 movs r2, #0 80058ca: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 80058cc: 687b ldr r3, [r7, #4] 80058ce: 2220 movs r2, #32 80058d0: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 80058d4: 687b ldr r3, [r7, #4] 80058d6: 2220 movs r2, #32 80058d8: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 80058dc: 687b ldr r3, [r7, #4] 80058de: 2200 movs r2, #0 80058e0: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 80058e2: 2300 movs r3, #0 } 80058e4: 4618 mov r0, r3 80058e6: 3708 adds r7, #8 80058e8: 46bd mov sp, r7 80058ea: bd80 pop {r7, pc} 080058ec : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 80058ec: b580 push {r7, lr} 80058ee: b08c sub sp, #48 @ 0x30 80058f0: af00 add r7, sp, #0 80058f2: 60f8 str r0, [r7, #12] 80058f4: 60b9 str r1, [r7, #8] 80058f6: 4613 mov r3, r2 80058f8: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80058fa: 68fb ldr r3, [r7, #12] 80058fc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005900: b2db uxtb r3, r3 8005902: 2b20 cmp r3, #32 8005904: d162 bne.n 80059cc { if ((pData == NULL) || (Size == 0U)) 8005906: 68bb ldr r3, [r7, #8] 8005908: 2b00 cmp r3, #0 800590a: d002 beq.n 8005912 800590c: 88fb ldrh r3, [r7, #6] 800590e: 2b00 cmp r3, #0 8005910: d101 bne.n 8005916 { return HAL_ERROR; 8005912: 2301 movs r3, #1 8005914: e05b b.n 80059ce } huart->pTxBuffPtr = pData; 8005916: 68ba ldr r2, [r7, #8] 8005918: 68fb ldr r3, [r7, #12] 800591a: 621a str r2, [r3, #32] huart->TxXferSize = Size; 800591c: 68fb ldr r3, [r7, #12] 800591e: 88fa ldrh r2, [r7, #6] 8005920: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8005922: 68fb ldr r3, [r7, #12] 8005924: 88fa ldrh r2, [r7, #6] 8005926: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8005928: 68fb ldr r3, [r7, #12] 800592a: 2200 movs r2, #0 800592c: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 800592e: 68fb ldr r3, [r7, #12] 8005930: 2221 movs r2, #33 @ 0x21 8005932: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 8005936: 68fb ldr r3, [r7, #12] 8005938: 6b9b ldr r3, [r3, #56] @ 0x38 800593a: 4a27 ldr r2, [pc, #156] @ (80059d8 ) 800593c: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 800593e: 68fb ldr r3, [r7, #12] 8005940: 6b9b ldr r3, [r3, #56] @ 0x38 8005942: 4a26 ldr r2, [pc, #152] @ (80059dc ) 8005944: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 8005946: 68fb ldr r3, [r7, #12] 8005948: 6b9b ldr r3, [r3, #56] @ 0x38 800594a: 4a25 ldr r2, [pc, #148] @ (80059e0 ) 800594c: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 800594e: 68fb ldr r3, [r7, #12] 8005950: 6b9b ldr r3, [r3, #56] @ 0x38 8005952: 2200 movs r2, #0 8005954: 651a str r2, [r3, #80] @ 0x50 /* Enable the UART transmit DMA stream */ tmp = (const uint32_t *)&pData; 8005956: f107 0308 add.w r3, r7, #8 800595a: 62fb str r3, [r7, #44] @ 0x2c if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK) 800595c: 68fb ldr r3, [r7, #12] 800595e: 6b98 ldr r0, [r3, #56] @ 0x38 8005960: 6afb ldr r3, [r7, #44] @ 0x2c 8005962: 6819 ldr r1, [r3, #0] 8005964: 68fb ldr r3, [r7, #12] 8005966: 681b ldr r3, [r3, #0] 8005968: 3304 adds r3, #4 800596a: 461a mov r2, r3 800596c: 88fb ldrh r3, [r7, #6] 800596e: f7fc f953 bl 8001c18 8005972: 4603 mov r3, r0 8005974: 2b00 cmp r3, #0 8005976: d008 beq.n 800598a { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8005978: 68fb ldr r3, [r7, #12] 800597a: 2210 movs r2, #16 800597c: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; 800597e: 68fb ldr r3, [r7, #12] 8005980: 2220 movs r2, #32 8005982: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_ERROR; 8005986: 2301 movs r3, #1 8005988: e021 b.n 80059ce } /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 800598a: 68fb ldr r3, [r7, #12] 800598c: 681b ldr r3, [r3, #0] 800598e: f06f 0240 mvn.w r2, #64 @ 0x40 8005992: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8005994: 68fb ldr r3, [r7, #12] 8005996: 681b ldr r3, [r3, #0] 8005998: 3314 adds r3, #20 800599a: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800599c: 69bb ldr r3, [r7, #24] 800599e: e853 3f00 ldrex r3, [r3] 80059a2: 617b str r3, [r7, #20] return(result); 80059a4: 697b ldr r3, [r7, #20] 80059a6: f043 0380 orr.w r3, r3, #128 @ 0x80 80059aa: 62bb str r3, [r7, #40] @ 0x28 80059ac: 68fb ldr r3, [r7, #12] 80059ae: 681b ldr r3, [r3, #0] 80059b0: 3314 adds r3, #20 80059b2: 6aba ldr r2, [r7, #40] @ 0x28 80059b4: 627a str r2, [r7, #36] @ 0x24 80059b6: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80059b8: 6a39 ldr r1, [r7, #32] 80059ba: 6a7a ldr r2, [r7, #36] @ 0x24 80059bc: e841 2300 strex r3, r2, [r1] 80059c0: 61fb str r3, [r7, #28] return(result); 80059c2: 69fb ldr r3, [r7, #28] 80059c4: 2b00 cmp r3, #0 80059c6: d1e5 bne.n 8005994 return HAL_OK; 80059c8: 2300 movs r3, #0 80059ca: e000 b.n 80059ce } else { return HAL_BUSY; 80059cc: 2302 movs r3, #2 } } 80059ce: 4618 mov r0, r3 80059d0: 3730 adds r7, #48 @ 0x30 80059d2: 46bd mov sp, r7 80059d4: bd80 pop {r7, pc} 80059d6: bf00 nop 80059d8: 08005f8d .word 0x08005f8d 80059dc: 08006027 .word 0x08006027 80059e0: 08006043 .word 0x08006043 080059e4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 80059e4: b580 push {r7, lr} 80059e6: b0ba sub sp, #232 @ 0xe8 80059e8: af00 add r7, sp, #0 80059ea: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 80059ec: 687b ldr r3, [r7, #4] 80059ee: 681b ldr r3, [r3, #0] 80059f0: 681b ldr r3, [r3, #0] 80059f2: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 80059f6: 687b ldr r3, [r7, #4] 80059f8: 681b ldr r3, [r3, #0] 80059fa: 68db ldr r3, [r3, #12] 80059fc: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8005a00: 687b ldr r3, [r7, #4] 8005a02: 681b ldr r3, [r3, #0] 8005a04: 695b ldr r3, [r3, #20] 8005a06: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8005a0a: 2300 movs r3, #0 8005a0c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8005a10: 2300 movs r3, #0 8005a12: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8005a16: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005a1a: f003 030f and.w r3, r3, #15 8005a1e: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8005a22: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8005a26: 2b00 cmp r3, #0 8005a28: d10f bne.n 8005a4a { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005a2a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005a2e: f003 0320 and.w r3, r3, #32 8005a32: 2b00 cmp r3, #0 8005a34: d009 beq.n 8005a4a 8005a36: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005a3a: f003 0320 and.w r3, r3, #32 8005a3e: 2b00 cmp r3, #0 8005a40: d003 beq.n 8005a4a { UART_Receive_IT(huart); 8005a42: 6878 ldr r0, [r7, #4] 8005a44: f000 fc4b bl 80062de return; 8005a48: e273 b.n 8005f32 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8005a4a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8005a4e: 2b00 cmp r3, #0 8005a50: f000 80de beq.w 8005c10 8005a54: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005a58: f003 0301 and.w r3, r3, #1 8005a5c: 2b00 cmp r3, #0 8005a5e: d106 bne.n 8005a6e || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8005a60: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005a64: f403 7390 and.w r3, r3, #288 @ 0x120 8005a68: 2b00 cmp r3, #0 8005a6a: f000 80d1 beq.w 8005c10 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8005a6e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005a72: f003 0301 and.w r3, r3, #1 8005a76: 2b00 cmp r3, #0 8005a78: d00b beq.n 8005a92 8005a7a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005a7e: f403 7380 and.w r3, r3, #256 @ 0x100 8005a82: 2b00 cmp r3, #0 8005a84: d005 beq.n 8005a92 { huart->ErrorCode |= HAL_UART_ERROR_PE; 8005a86: 687b ldr r3, [r7, #4] 8005a88: 6c5b ldr r3, [r3, #68] @ 0x44 8005a8a: f043 0201 orr.w r2, r3, #1 8005a8e: 687b ldr r3, [r7, #4] 8005a90: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005a92: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005a96: f003 0304 and.w r3, r3, #4 8005a9a: 2b00 cmp r3, #0 8005a9c: d00b beq.n 8005ab6 8005a9e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005aa2: f003 0301 and.w r3, r3, #1 8005aa6: 2b00 cmp r3, #0 8005aa8: d005 beq.n 8005ab6 { huart->ErrorCode |= HAL_UART_ERROR_NE; 8005aaa: 687b ldr r3, [r7, #4] 8005aac: 6c5b ldr r3, [r3, #68] @ 0x44 8005aae: f043 0202 orr.w r2, r3, #2 8005ab2: 687b ldr r3, [r7, #4] 8005ab4: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005ab6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005aba: f003 0302 and.w r3, r3, #2 8005abe: 2b00 cmp r3, #0 8005ac0: d00b beq.n 8005ada 8005ac2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005ac6: f003 0301 and.w r3, r3, #1 8005aca: 2b00 cmp r3, #0 8005acc: d005 beq.n 8005ada { huart->ErrorCode |= HAL_UART_ERROR_FE; 8005ace: 687b ldr r3, [r7, #4] 8005ad0: 6c5b ldr r3, [r3, #68] @ 0x44 8005ad2: f043 0204 orr.w r2, r3, #4 8005ad6: 687b ldr r3, [r7, #4] 8005ad8: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8005ada: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005ade: f003 0308 and.w r3, r3, #8 8005ae2: 2b00 cmp r3, #0 8005ae4: d011 beq.n 8005b0a 8005ae6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005aea: f003 0320 and.w r3, r3, #32 8005aee: 2b00 cmp r3, #0 8005af0: d105 bne.n 8005afe || ((cr3its & USART_CR3_EIE) != RESET))) 8005af2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005af6: f003 0301 and.w r3, r3, #1 8005afa: 2b00 cmp r3, #0 8005afc: d005 beq.n 8005b0a { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8005afe: 687b ldr r3, [r7, #4] 8005b00: 6c5b ldr r3, [r3, #68] @ 0x44 8005b02: f043 0208 orr.w r2, r3, #8 8005b06: 687b ldr r3, [r7, #4] 8005b08: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8005b0a: 687b ldr r3, [r7, #4] 8005b0c: 6c5b ldr r3, [r3, #68] @ 0x44 8005b0e: 2b00 cmp r3, #0 8005b10: f000 820a beq.w 8005f28 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005b14: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005b18: f003 0320 and.w r3, r3, #32 8005b1c: 2b00 cmp r3, #0 8005b1e: d008 beq.n 8005b32 8005b20: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005b24: f003 0320 and.w r3, r3, #32 8005b28: 2b00 cmp r3, #0 8005b2a: d002 beq.n 8005b32 { UART_Receive_IT(huart); 8005b2c: 6878 ldr r0, [r7, #4] 8005b2e: f000 fbd6 bl 80062de } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8005b32: 687b ldr r3, [r7, #4] 8005b34: 681b ldr r3, [r3, #0] 8005b36: 695b ldr r3, [r3, #20] 8005b38: f003 0340 and.w r3, r3, #64 @ 0x40 8005b3c: 2b40 cmp r3, #64 @ 0x40 8005b3e: bf0c ite eq 8005b40: 2301 moveq r3, #1 8005b42: 2300 movne r3, #0 8005b44: b2db uxtb r3, r3 8005b46: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8005b4a: 687b ldr r3, [r7, #4] 8005b4c: 6c5b ldr r3, [r3, #68] @ 0x44 8005b4e: f003 0308 and.w r3, r3, #8 8005b52: 2b00 cmp r3, #0 8005b54: d103 bne.n 8005b5e 8005b56: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8005b5a: 2b00 cmp r3, #0 8005b5c: d04f beq.n 8005bfe { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8005b5e: 6878 ldr r0, [r7, #4] 8005b60: f000 fae1 bl 8006126 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005b64: 687b ldr r3, [r7, #4] 8005b66: 681b ldr r3, [r3, #0] 8005b68: 695b ldr r3, [r3, #20] 8005b6a: f003 0340 and.w r3, r3, #64 @ 0x40 8005b6e: 2b40 cmp r3, #64 @ 0x40 8005b70: d141 bne.n 8005bf6 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005b72: 687b ldr r3, [r7, #4] 8005b74: 681b ldr r3, [r3, #0] 8005b76: 3314 adds r3, #20 8005b78: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005b7c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8005b80: e853 3f00 ldrex r3, [r3] 8005b84: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8005b88: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8005b8c: f023 0340 bic.w r3, r3, #64 @ 0x40 8005b90: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8005b94: 687b ldr r3, [r7, #4] 8005b96: 681b ldr r3, [r3, #0] 8005b98: 3314 adds r3, #20 8005b9a: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8005b9e: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8005ba2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005ba6: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8005baa: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8005bae: e841 2300 strex r3, r2, [r1] 8005bb2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8005bb6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8005bba: 2b00 cmp r3, #0 8005bbc: d1d9 bne.n 8005b72 /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) 8005bbe: 687b ldr r3, [r7, #4] 8005bc0: 6bdb ldr r3, [r3, #60] @ 0x3c 8005bc2: 2b00 cmp r3, #0 8005bc4: d013 beq.n 8005bee { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8005bc6: 687b ldr r3, [r7, #4] 8005bc8: 6bdb ldr r3, [r3, #60] @ 0x3c 8005bca: 4a8a ldr r2, [pc, #552] @ (8005df4 ) 8005bcc: 651a str r2, [r3, #80] @ 0x50 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8005bce: 687b ldr r3, [r7, #4] 8005bd0: 6bdb ldr r3, [r3, #60] @ 0x3c 8005bd2: 4618 mov r0, r3 8005bd4: f7fc f8e8 bl 8001da8 8005bd8: 4603 mov r3, r0 8005bda: 2b00 cmp r3, #0 8005bdc: d016 beq.n 8005c0c { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8005bde: 687b ldr r3, [r7, #4] 8005be0: 6bdb ldr r3, [r3, #60] @ 0x3c 8005be2: 6d1b ldr r3, [r3, #80] @ 0x50 8005be4: 687a ldr r2, [r7, #4] 8005be6: 6bd2 ldr r2, [r2, #60] @ 0x3c 8005be8: 4610 mov r0, r2 8005bea: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005bec: e00e b.n 8005c0c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005bee: 6878 ldr r0, [r7, #4] 8005bf0: f000 f9b6 bl 8005f60 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005bf4: e00a b.n 8005c0c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005bf6: 6878 ldr r0, [r7, #4] 8005bf8: f000 f9b2 bl 8005f60 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005bfc: e006 b.n 8005c0c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005bfe: 6878 ldr r0, [r7, #4] 8005c00: f000 f9ae bl 8005f60 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005c04: 687b ldr r3, [r7, #4] 8005c06: 2200 movs r2, #0 8005c08: 645a str r2, [r3, #68] @ 0x44 } } return; 8005c0a: e18d b.n 8005f28 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005c0c: bf00 nop return; 8005c0e: e18b b.n 8005f28 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005c10: 687b ldr r3, [r7, #4] 8005c12: 6b1b ldr r3, [r3, #48] @ 0x30 8005c14: 2b01 cmp r3, #1 8005c16: f040 8167 bne.w 8005ee8 && ((isrflags & USART_SR_IDLE) != 0U) 8005c1a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005c1e: f003 0310 and.w r3, r3, #16 8005c22: 2b00 cmp r3, #0 8005c24: f000 8160 beq.w 8005ee8 && ((cr1its & USART_CR1_IDLEIE) != 0U)) 8005c28: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005c2c: f003 0310 and.w r3, r3, #16 8005c30: 2b00 cmp r3, #0 8005c32: f000 8159 beq.w 8005ee8 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8005c36: 2300 movs r3, #0 8005c38: 60bb str r3, [r7, #8] 8005c3a: 687b ldr r3, [r7, #4] 8005c3c: 681b ldr r3, [r3, #0] 8005c3e: 681b ldr r3, [r3, #0] 8005c40: 60bb str r3, [r7, #8] 8005c42: 687b ldr r3, [r7, #4] 8005c44: 681b ldr r3, [r3, #0] 8005c46: 685b ldr r3, [r3, #4] 8005c48: 60bb str r3, [r7, #8] 8005c4a: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005c4c: 687b ldr r3, [r7, #4] 8005c4e: 681b ldr r3, [r3, #0] 8005c50: 695b ldr r3, [r3, #20] 8005c52: f003 0340 and.w r3, r3, #64 @ 0x40 8005c56: 2b40 cmp r3, #64 @ 0x40 8005c58: f040 80ce bne.w 8005df8 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8005c5c: 687b ldr r3, [r7, #4] 8005c5e: 6bdb ldr r3, [r3, #60] @ 0x3c 8005c60: 681b ldr r3, [r3, #0] 8005c62: 685b ldr r3, [r3, #4] 8005c64: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8005c68: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8005c6c: 2b00 cmp r3, #0 8005c6e: f000 80a9 beq.w 8005dc4 && (nb_remaining_rx_data < huart->RxXferSize)) 8005c72: 687b ldr r3, [r7, #4] 8005c74: 8d9b ldrh r3, [r3, #44] @ 0x2c 8005c76: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005c7a: 429a cmp r2, r3 8005c7c: f080 80a2 bcs.w 8005dc4 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8005c80: 687b ldr r3, [r7, #4] 8005c82: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005c86: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8005c88: 687b ldr r3, [r7, #4] 8005c8a: 6bdb ldr r3, [r3, #60] @ 0x3c 8005c8c: 69db ldr r3, [r3, #28] 8005c8e: f5b3 7f80 cmp.w r3, #256 @ 0x100 8005c92: f000 8088 beq.w 8005da6 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8005c96: 687b ldr r3, [r7, #4] 8005c98: 681b ldr r3, [r3, #0] 8005c9a: 330c adds r3, #12 8005c9c: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005ca0: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8005ca4: e853 3f00 ldrex r3, [r3] 8005ca8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8005cac: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8005cb0: f423 7380 bic.w r3, r3, #256 @ 0x100 8005cb4: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8005cb8: 687b ldr r3, [r7, #4] 8005cba: 681b ldr r3, [r3, #0] 8005cbc: 330c adds r3, #12 8005cbe: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8005cc2: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8005cc6: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005cca: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8005cce: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8005cd2: e841 2300 strex r3, r2, [r1] 8005cd6: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8005cda: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005cde: 2b00 cmp r3, #0 8005ce0: d1d9 bne.n 8005c96 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005ce2: 687b ldr r3, [r7, #4] 8005ce4: 681b ldr r3, [r3, #0] 8005ce6: 3314 adds r3, #20 8005ce8: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005cea: 6f7b ldr r3, [r7, #116] @ 0x74 8005cec: e853 3f00 ldrex r3, [r3] 8005cf0: 673b str r3, [r7, #112] @ 0x70 return(result); 8005cf2: 6f3b ldr r3, [r7, #112] @ 0x70 8005cf4: f023 0301 bic.w r3, r3, #1 8005cf8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8005cfc: 687b ldr r3, [r7, #4] 8005cfe: 681b ldr r3, [r3, #0] 8005d00: 3314 adds r3, #20 8005d02: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8005d06: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8005d0a: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005d0c: 6ff9 ldr r1, [r7, #124] @ 0x7c 8005d0e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8005d12: e841 2300 strex r3, r2, [r1] 8005d16: 67bb str r3, [r7, #120] @ 0x78 return(result); 8005d18: 6fbb ldr r3, [r7, #120] @ 0x78 8005d1a: 2b00 cmp r3, #0 8005d1c: d1e1 bne.n 8005ce2 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005d1e: 687b ldr r3, [r7, #4] 8005d20: 681b ldr r3, [r3, #0] 8005d22: 3314 adds r3, #20 8005d24: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005d26: 6e3b ldr r3, [r7, #96] @ 0x60 8005d28: e853 3f00 ldrex r3, [r3] 8005d2c: 65fb str r3, [r7, #92] @ 0x5c return(result); 8005d2e: 6dfb ldr r3, [r7, #92] @ 0x5c 8005d30: f023 0340 bic.w r3, r3, #64 @ 0x40 8005d34: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8005d38: 687b ldr r3, [r7, #4] 8005d3a: 681b ldr r3, [r3, #0] 8005d3c: 3314 adds r3, #20 8005d3e: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8005d42: 66fa str r2, [r7, #108] @ 0x6c 8005d44: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005d46: 6eb9 ldr r1, [r7, #104] @ 0x68 8005d48: 6efa ldr r2, [r7, #108] @ 0x6c 8005d4a: e841 2300 strex r3, r2, [r1] 8005d4e: 667b str r3, [r7, #100] @ 0x64 return(result); 8005d50: 6e7b ldr r3, [r7, #100] @ 0x64 8005d52: 2b00 cmp r3, #0 8005d54: d1e3 bne.n 8005d1e /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8005d56: 687b ldr r3, [r7, #4] 8005d58: 2220 movs r2, #32 8005d5a: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005d5e: 687b ldr r3, [r7, #4] 8005d60: 2200 movs r2, #0 8005d62: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8005d64: 687b ldr r3, [r7, #4] 8005d66: 681b ldr r3, [r3, #0] 8005d68: 330c adds r3, #12 8005d6a: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005d6c: 6cfb ldr r3, [r7, #76] @ 0x4c 8005d6e: e853 3f00 ldrex r3, [r3] 8005d72: 64bb str r3, [r7, #72] @ 0x48 return(result); 8005d74: 6cbb ldr r3, [r7, #72] @ 0x48 8005d76: f023 0310 bic.w r3, r3, #16 8005d7a: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8005d7e: 687b ldr r3, [r7, #4] 8005d80: 681b ldr r3, [r3, #0] 8005d82: 330c adds r3, #12 8005d84: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 8005d88: 65ba str r2, [r7, #88] @ 0x58 8005d8a: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005d8c: 6d79 ldr r1, [r7, #84] @ 0x54 8005d8e: 6dba ldr r2, [r7, #88] @ 0x58 8005d90: e841 2300 strex r3, r2, [r1] 8005d94: 653b str r3, [r7, #80] @ 0x50 return(result); 8005d96: 6d3b ldr r3, [r7, #80] @ 0x50 8005d98: 2b00 cmp r3, #0 8005d9a: d1e3 bne.n 8005d64 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8005d9c: 687b ldr r3, [r7, #4] 8005d9e: 6bdb ldr r3, [r3, #60] @ 0x3c 8005da0: 4618 mov r0, r3 8005da2: f7fb ff91 bl 8001cc8 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8005da6: 687b ldr r3, [r7, #4] 8005da8: 2202 movs r2, #2 8005daa: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8005dac: 687b ldr r3, [r7, #4] 8005dae: 8d9a ldrh r2, [r3, #44] @ 0x2c 8005db0: 687b ldr r3, [r7, #4] 8005db2: 8ddb ldrh r3, [r3, #46] @ 0x2e 8005db4: b29b uxth r3, r3 8005db6: 1ad3 subs r3, r2, r3 8005db8: b29b uxth r3, r3 8005dba: 4619 mov r1, r3 8005dbc: 6878 ldr r0, [r7, #4] 8005dbe: f000 f8d9 bl 8005f74 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 8005dc2: e0b3 b.n 8005f2c if (nb_remaining_rx_data == huart->RxXferSize) 8005dc4: 687b ldr r3, [r7, #4] 8005dc6: 8d9b ldrh r3, [r3, #44] @ 0x2c 8005dc8: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005dcc: 429a cmp r2, r3 8005dce: f040 80ad bne.w 8005f2c if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) 8005dd2: 687b ldr r3, [r7, #4] 8005dd4: 6bdb ldr r3, [r3, #60] @ 0x3c 8005dd6: 69db ldr r3, [r3, #28] 8005dd8: f5b3 7f80 cmp.w r3, #256 @ 0x100 8005ddc: f040 80a6 bne.w 8005f2c huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8005de0: 687b ldr r3, [r7, #4] 8005de2: 2202 movs r2, #2 8005de4: 635a str r2, [r3, #52] @ 0x34 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8005de6: 687b ldr r3, [r7, #4] 8005de8: 8d9b ldrh r3, [r3, #44] @ 0x2c 8005dea: 4619 mov r1, r3 8005dec: 6878 ldr r0, [r7, #4] 8005dee: f000 f8c1 bl 8005f74 return; 8005df2: e09b b.n 8005f2c 8005df4: 080061ed .word 0x080061ed else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8005df8: 687b ldr r3, [r7, #4] 8005dfa: 8d9a ldrh r2, [r3, #44] @ 0x2c 8005dfc: 687b ldr r3, [r7, #4] 8005dfe: 8ddb ldrh r3, [r3, #46] @ 0x2e 8005e00: b29b uxth r3, r3 8005e02: 1ad3 subs r3, r2, r3 8005e04: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8005e08: 687b ldr r3, [r7, #4] 8005e0a: 8ddb ldrh r3, [r3, #46] @ 0x2e 8005e0c: b29b uxth r3, r3 8005e0e: 2b00 cmp r3, #0 8005e10: f000 808e beq.w 8005f30 && (nb_rx_data > 0U)) 8005e14: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8005e18: 2b00 cmp r3, #0 8005e1a: f000 8089 beq.w 8005f30 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8005e1e: 687b ldr r3, [r7, #4] 8005e20: 681b ldr r3, [r3, #0] 8005e22: 330c adds r3, #12 8005e24: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005e26: 6bbb ldr r3, [r7, #56] @ 0x38 8005e28: e853 3f00 ldrex r3, [r3] 8005e2c: 637b str r3, [r7, #52] @ 0x34 return(result); 8005e2e: 6b7b ldr r3, [r7, #52] @ 0x34 8005e30: f423 7390 bic.w r3, r3, #288 @ 0x120 8005e34: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8005e38: 687b ldr r3, [r7, #4] 8005e3a: 681b ldr r3, [r3, #0] 8005e3c: 330c adds r3, #12 8005e3e: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 8005e42: 647a str r2, [r7, #68] @ 0x44 8005e44: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005e46: 6c39 ldr r1, [r7, #64] @ 0x40 8005e48: 6c7a ldr r2, [r7, #68] @ 0x44 8005e4a: e841 2300 strex r3, r2, [r1] 8005e4e: 63fb str r3, [r7, #60] @ 0x3c return(result); 8005e50: 6bfb ldr r3, [r7, #60] @ 0x3c 8005e52: 2b00 cmp r3, #0 8005e54: d1e3 bne.n 8005e1e /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005e56: 687b ldr r3, [r7, #4] 8005e58: 681b ldr r3, [r3, #0] 8005e5a: 3314 adds r3, #20 8005e5c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005e5e: 6a7b ldr r3, [r7, #36] @ 0x24 8005e60: e853 3f00 ldrex r3, [r3] 8005e64: 623b str r3, [r7, #32] return(result); 8005e66: 6a3b ldr r3, [r7, #32] 8005e68: f023 0301 bic.w r3, r3, #1 8005e6c: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8005e70: 687b ldr r3, [r7, #4] 8005e72: 681b ldr r3, [r3, #0] 8005e74: 3314 adds r3, #20 8005e76: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8005e7a: 633a str r2, [r7, #48] @ 0x30 8005e7c: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005e7e: 6af9 ldr r1, [r7, #44] @ 0x2c 8005e80: 6b3a ldr r2, [r7, #48] @ 0x30 8005e82: e841 2300 strex r3, r2, [r1] 8005e86: 62bb str r3, [r7, #40] @ 0x28 return(result); 8005e88: 6abb ldr r3, [r7, #40] @ 0x28 8005e8a: 2b00 cmp r3, #0 8005e8c: d1e3 bne.n 8005e56 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8005e8e: 687b ldr r3, [r7, #4] 8005e90: 2220 movs r2, #32 8005e92: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005e96: 687b ldr r3, [r7, #4] 8005e98: 2200 movs r2, #0 8005e9a: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8005e9c: 687b ldr r3, [r7, #4] 8005e9e: 681b ldr r3, [r3, #0] 8005ea0: 330c adds r3, #12 8005ea2: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005ea4: 693b ldr r3, [r7, #16] 8005ea6: e853 3f00 ldrex r3, [r3] 8005eaa: 60fb str r3, [r7, #12] return(result); 8005eac: 68fb ldr r3, [r7, #12] 8005eae: f023 0310 bic.w r3, r3, #16 8005eb2: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8005eb6: 687b ldr r3, [r7, #4] 8005eb8: 681b ldr r3, [r3, #0] 8005eba: 330c adds r3, #12 8005ebc: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8005ec0: 61fa str r2, [r7, #28] 8005ec2: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005ec4: 69b9 ldr r1, [r7, #24] 8005ec6: 69fa ldr r2, [r7, #28] 8005ec8: e841 2300 strex r3, r2, [r1] 8005ecc: 617b str r3, [r7, #20] return(result); 8005ece: 697b ldr r3, [r7, #20] 8005ed0: 2b00 cmp r3, #0 8005ed2: d1e3 bne.n 8005e9c /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8005ed4: 687b ldr r3, [r7, #4] 8005ed6: 2202 movs r2, #2 8005ed8: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8005eda: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8005ede: 4619 mov r1, r3 8005ee0: 6878 ldr r0, [r7, #4] 8005ee2: f000 f847 bl 8005f74 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8005ee6: e023 b.n 8005f30 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8005ee8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005eec: f003 0380 and.w r3, r3, #128 @ 0x80 8005ef0: 2b00 cmp r3, #0 8005ef2: d009 beq.n 8005f08 8005ef4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005ef8: f003 0380 and.w r3, r3, #128 @ 0x80 8005efc: 2b00 cmp r3, #0 8005efe: d003 beq.n 8005f08 { UART_Transmit_IT(huart); 8005f00: 6878 ldr r0, [r7, #4] 8005f02: f000 f984 bl 800620e return; 8005f06: e014 b.n 8005f32 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8005f08: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005f0c: f003 0340 and.w r3, r3, #64 @ 0x40 8005f10: 2b00 cmp r3, #0 8005f12: d00e beq.n 8005f32 8005f14: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005f18: f003 0340 and.w r3, r3, #64 @ 0x40 8005f1c: 2b00 cmp r3, #0 8005f1e: d008 beq.n 8005f32 { UART_EndTransmit_IT(huart); 8005f20: 6878 ldr r0, [r7, #4] 8005f22: f000 f9c4 bl 80062ae return; 8005f26: e004 b.n 8005f32 return; 8005f28: bf00 nop 8005f2a: e002 b.n 8005f32 return; 8005f2c: bf00 nop 8005f2e: e000 b.n 8005f32 return; 8005f30: bf00 nop } } 8005f32: 37e8 adds r7, #232 @ 0xe8 8005f34: 46bd mov sp, r7 8005f36: bd80 pop {r7, pc} 08005f38 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8005f38: b480 push {r7} 8005f3a: b083 sub sp, #12 8005f3c: af00 add r7, sp, #0 8005f3e: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8005f40: bf00 nop 8005f42: 370c adds r7, #12 8005f44: 46bd mov sp, r7 8005f46: f85d 7b04 ldr.w r7, [sp], #4 8005f4a: 4770 bx lr 08005f4c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8005f4c: b480 push {r7} 8005f4e: b083 sub sp, #12 8005f50: af00 add r7, sp, #0 8005f52: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 8005f54: bf00 nop 8005f56: 370c adds r7, #12 8005f58: 46bd mov sp, r7 8005f5a: f85d 7b04 ldr.w r7, [sp], #4 8005f5e: 4770 bx lr 08005f60 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8005f60: b480 push {r7} 8005f62: b083 sub sp, #12 8005f64: af00 add r7, sp, #0 8005f66: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 8005f68: bf00 nop 8005f6a: 370c adds r7, #12 8005f6c: 46bd mov sp, r7 8005f6e: f85d 7b04 ldr.w r7, [sp], #4 8005f72: 4770 bx lr 08005f74 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 8005f74: b480 push {r7} 8005f76: b083 sub sp, #12 8005f78: af00 add r7, sp, #0 8005f7a: 6078 str r0, [r7, #4] 8005f7c: 460b mov r3, r1 8005f7e: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 8005f80: bf00 nop 8005f82: 370c adds r7, #12 8005f84: 46bd mov sp, r7 8005f86: f85d 7b04 ldr.w r7, [sp], #4 8005f8a: 4770 bx lr 08005f8c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 8005f8c: b580 push {r7, lr} 8005f8e: b090 sub sp, #64 @ 0x40 8005f90: af00 add r7, sp, #0 8005f92: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8005f94: 687b ldr r3, [r7, #4] 8005f96: 6b9b ldr r3, [r3, #56] @ 0x38 8005f98: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 8005f9a: 687b ldr r3, [r7, #4] 8005f9c: 681b ldr r3, [r3, #0] 8005f9e: 681b ldr r3, [r3, #0] 8005fa0: f403 7380 and.w r3, r3, #256 @ 0x100 8005fa4: 2b00 cmp r3, #0 8005fa6: d137 bne.n 8006018 { huart->TxXferCount = 0x00U; 8005fa8: 6bfb ldr r3, [r7, #60] @ 0x3c 8005faa: 2200 movs r2, #0 8005fac: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8005fae: 6bfb ldr r3, [r7, #60] @ 0x3c 8005fb0: 681b ldr r3, [r3, #0] 8005fb2: 3314 adds r3, #20 8005fb4: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005fb6: 6a7b ldr r3, [r7, #36] @ 0x24 8005fb8: e853 3f00 ldrex r3, [r3] 8005fbc: 623b str r3, [r7, #32] return(result); 8005fbe: 6a3b ldr r3, [r7, #32] 8005fc0: f023 0380 bic.w r3, r3, #128 @ 0x80 8005fc4: 63bb str r3, [r7, #56] @ 0x38 8005fc6: 6bfb ldr r3, [r7, #60] @ 0x3c 8005fc8: 681b ldr r3, [r3, #0] 8005fca: 3314 adds r3, #20 8005fcc: 6bba ldr r2, [r7, #56] @ 0x38 8005fce: 633a str r2, [r7, #48] @ 0x30 8005fd0: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005fd2: 6af9 ldr r1, [r7, #44] @ 0x2c 8005fd4: 6b3a ldr r2, [r7, #48] @ 0x30 8005fd6: e841 2300 strex r3, r2, [r1] 8005fda: 62bb str r3, [r7, #40] @ 0x28 return(result); 8005fdc: 6abb ldr r3, [r7, #40] @ 0x28 8005fde: 2b00 cmp r3, #0 8005fe0: d1e5 bne.n 8005fae /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8005fe2: 6bfb ldr r3, [r7, #60] @ 0x3c 8005fe4: 681b ldr r3, [r3, #0] 8005fe6: 330c adds r3, #12 8005fe8: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005fea: 693b ldr r3, [r7, #16] 8005fec: e853 3f00 ldrex r3, [r3] 8005ff0: 60fb str r3, [r7, #12] return(result); 8005ff2: 68fb ldr r3, [r7, #12] 8005ff4: f043 0340 orr.w r3, r3, #64 @ 0x40 8005ff8: 637b str r3, [r7, #52] @ 0x34 8005ffa: 6bfb ldr r3, [r7, #60] @ 0x3c 8005ffc: 681b ldr r3, [r3, #0] 8005ffe: 330c adds r3, #12 8006000: 6b7a ldr r2, [r7, #52] @ 0x34 8006002: 61fa str r2, [r7, #28] 8006004: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006006: 69b9 ldr r1, [r7, #24] 8006008: 69fa ldr r2, [r7, #28] 800600a: e841 2300 strex r3, r2, [r1] 800600e: 617b str r3, [r7, #20] return(result); 8006010: 697b ldr r3, [r7, #20] 8006012: 2b00 cmp r3, #0 8006014: d1e5 bne.n 8005fe2 #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8006016: e002 b.n 800601e HAL_UART_TxCpltCallback(huart); 8006018: 6bf8 ldr r0, [r7, #60] @ 0x3c 800601a: f7ff ff8d bl 8005f38 } 800601e: bf00 nop 8006020: 3740 adds r7, #64 @ 0x40 8006022: 46bd mov sp, r7 8006024: bd80 pop {r7, pc} 08006026 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 8006026: b580 push {r7, lr} 8006028: b084 sub sp, #16 800602a: af00 add r7, sp, #0 800602c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800602e: 687b ldr r3, [r7, #4] 8006030: 6b9b ldr r3, [r3, #56] @ 0x38 8006032: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 8006034: 68f8 ldr r0, [r7, #12] 8006036: f7ff ff89 bl 8005f4c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800603a: bf00 nop 800603c: 3710 adds r7, #16 800603e: 46bd mov sp, r7 8006040: bd80 pop {r7, pc} 08006042 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8006042: b580 push {r7, lr} 8006044: b084 sub sp, #16 8006046: af00 add r7, sp, #0 8006048: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 800604a: 2300 movs r3, #0 800604c: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800604e: 687b ldr r3, [r7, #4] 8006050: 6b9b ldr r3, [r3, #56] @ 0x38 8006052: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8006054: 68bb ldr r3, [r7, #8] 8006056: 681b ldr r3, [r3, #0] 8006058: 695b ldr r3, [r3, #20] 800605a: f003 0380 and.w r3, r3, #128 @ 0x80 800605e: 2b80 cmp r3, #128 @ 0x80 8006060: bf0c ite eq 8006062: 2301 moveq r3, #1 8006064: 2300 movne r3, #0 8006066: b2db uxtb r3, r3 8006068: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 800606a: 68bb ldr r3, [r7, #8] 800606c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8006070: b2db uxtb r3, r3 8006072: 2b21 cmp r3, #33 @ 0x21 8006074: d108 bne.n 8006088 8006076: 68fb ldr r3, [r7, #12] 8006078: 2b00 cmp r3, #0 800607a: d005 beq.n 8006088 { huart->TxXferCount = 0x00U; 800607c: 68bb ldr r3, [r7, #8] 800607e: 2200 movs r2, #0 8006080: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 8006082: 68b8 ldr r0, [r7, #8] 8006084: f000 f827 bl 80060d6 } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8006088: 68bb ldr r3, [r7, #8] 800608a: 681b ldr r3, [r3, #0] 800608c: 695b ldr r3, [r3, #20] 800608e: f003 0340 and.w r3, r3, #64 @ 0x40 8006092: 2b40 cmp r3, #64 @ 0x40 8006094: bf0c ite eq 8006096: 2301 moveq r3, #1 8006098: 2300 movne r3, #0 800609a: b2db uxtb r3, r3 800609c: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 800609e: 68bb ldr r3, [r7, #8] 80060a0: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80060a4: b2db uxtb r3, r3 80060a6: 2b22 cmp r3, #34 @ 0x22 80060a8: d108 bne.n 80060bc 80060aa: 68fb ldr r3, [r7, #12] 80060ac: 2b00 cmp r3, #0 80060ae: d005 beq.n 80060bc { huart->RxXferCount = 0x00U; 80060b0: 68bb ldr r3, [r7, #8] 80060b2: 2200 movs r2, #0 80060b4: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 80060b6: 68b8 ldr r0, [r7, #8] 80060b8: f000 f835 bl 8006126 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 80060bc: 68bb ldr r3, [r7, #8] 80060be: 6c5b ldr r3, [r3, #68] @ 0x44 80060c0: f043 0210 orr.w r2, r3, #16 80060c4: 68bb ldr r3, [r7, #8] 80060c6: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80060c8: 68b8 ldr r0, [r7, #8] 80060ca: f7ff ff49 bl 8005f60 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80060ce: bf00 nop 80060d0: 3710 adds r7, #16 80060d2: 46bd mov sp, r7 80060d4: bd80 pop {r7, pc} 080060d6 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 80060d6: b480 push {r7} 80060d8: b089 sub sp, #36 @ 0x24 80060da: af00 add r7, sp, #0 80060dc: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 80060de: 687b ldr r3, [r7, #4] 80060e0: 681b ldr r3, [r3, #0] 80060e2: 330c adds r3, #12 80060e4: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80060e6: 68fb ldr r3, [r7, #12] 80060e8: e853 3f00 ldrex r3, [r3] 80060ec: 60bb str r3, [r7, #8] return(result); 80060ee: 68bb ldr r3, [r7, #8] 80060f0: f023 03c0 bic.w r3, r3, #192 @ 0xc0 80060f4: 61fb str r3, [r7, #28] 80060f6: 687b ldr r3, [r7, #4] 80060f8: 681b ldr r3, [r3, #0] 80060fa: 330c adds r3, #12 80060fc: 69fa ldr r2, [r7, #28] 80060fe: 61ba str r2, [r7, #24] 8006100: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006102: 6979 ldr r1, [r7, #20] 8006104: 69ba ldr r2, [r7, #24] 8006106: e841 2300 strex r3, r2, [r1] 800610a: 613b str r3, [r7, #16] return(result); 800610c: 693b ldr r3, [r7, #16] 800610e: 2b00 cmp r3, #0 8006110: d1e5 bne.n 80060de /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8006112: 687b ldr r3, [r7, #4] 8006114: 2220 movs r2, #32 8006116: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 800611a: bf00 nop 800611c: 3724 adds r7, #36 @ 0x24 800611e: 46bd mov sp, r7 8006120: f85d 7b04 ldr.w r7, [sp], #4 8006124: 4770 bx lr 08006126 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8006126: b480 push {r7} 8006128: b095 sub sp, #84 @ 0x54 800612a: af00 add r7, sp, #0 800612c: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 800612e: 687b ldr r3, [r7, #4] 8006130: 681b ldr r3, [r3, #0] 8006132: 330c adds r3, #12 8006134: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006136: 6b7b ldr r3, [r7, #52] @ 0x34 8006138: e853 3f00 ldrex r3, [r3] 800613c: 633b str r3, [r7, #48] @ 0x30 return(result); 800613e: 6b3b ldr r3, [r7, #48] @ 0x30 8006140: f423 7390 bic.w r3, r3, #288 @ 0x120 8006144: 64fb str r3, [r7, #76] @ 0x4c 8006146: 687b ldr r3, [r7, #4] 8006148: 681b ldr r3, [r3, #0] 800614a: 330c adds r3, #12 800614c: 6cfa ldr r2, [r7, #76] @ 0x4c 800614e: 643a str r2, [r7, #64] @ 0x40 8006150: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006152: 6bf9 ldr r1, [r7, #60] @ 0x3c 8006154: 6c3a ldr r2, [r7, #64] @ 0x40 8006156: e841 2300 strex r3, r2, [r1] 800615a: 63bb str r3, [r7, #56] @ 0x38 return(result); 800615c: 6bbb ldr r3, [r7, #56] @ 0x38 800615e: 2b00 cmp r3, #0 8006160: d1e5 bne.n 800612e ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006162: 687b ldr r3, [r7, #4] 8006164: 681b ldr r3, [r3, #0] 8006166: 3314 adds r3, #20 8006168: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800616a: 6a3b ldr r3, [r7, #32] 800616c: e853 3f00 ldrex r3, [r3] 8006170: 61fb str r3, [r7, #28] return(result); 8006172: 69fb ldr r3, [r7, #28] 8006174: f023 0301 bic.w r3, r3, #1 8006178: 64bb str r3, [r7, #72] @ 0x48 800617a: 687b ldr r3, [r7, #4] 800617c: 681b ldr r3, [r3, #0] 800617e: 3314 adds r3, #20 8006180: 6cba ldr r2, [r7, #72] @ 0x48 8006182: 62fa str r2, [r7, #44] @ 0x2c 8006184: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006186: 6ab9 ldr r1, [r7, #40] @ 0x28 8006188: 6afa ldr r2, [r7, #44] @ 0x2c 800618a: e841 2300 strex r3, r2, [r1] 800618e: 627b str r3, [r7, #36] @ 0x24 return(result); 8006190: 6a7b ldr r3, [r7, #36] @ 0x24 8006192: 2b00 cmp r3, #0 8006194: d1e5 bne.n 8006162 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006196: 687b ldr r3, [r7, #4] 8006198: 6b1b ldr r3, [r3, #48] @ 0x30 800619a: 2b01 cmp r3, #1 800619c: d119 bne.n 80061d2 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800619e: 687b ldr r3, [r7, #4] 80061a0: 681b ldr r3, [r3, #0] 80061a2: 330c adds r3, #12 80061a4: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80061a6: 68fb ldr r3, [r7, #12] 80061a8: e853 3f00 ldrex r3, [r3] 80061ac: 60bb str r3, [r7, #8] return(result); 80061ae: 68bb ldr r3, [r7, #8] 80061b0: f023 0310 bic.w r3, r3, #16 80061b4: 647b str r3, [r7, #68] @ 0x44 80061b6: 687b ldr r3, [r7, #4] 80061b8: 681b ldr r3, [r3, #0] 80061ba: 330c adds r3, #12 80061bc: 6c7a ldr r2, [r7, #68] @ 0x44 80061be: 61ba str r2, [r7, #24] 80061c0: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80061c2: 6979 ldr r1, [r7, #20] 80061c4: 69ba ldr r2, [r7, #24] 80061c6: e841 2300 strex r3, r2, [r1] 80061ca: 613b str r3, [r7, #16] return(result); 80061cc: 693b ldr r3, [r7, #16] 80061ce: 2b00 cmp r3, #0 80061d0: d1e5 bne.n 800619e } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80061d2: 687b ldr r3, [r7, #4] 80061d4: 2220 movs r2, #32 80061d6: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80061da: 687b ldr r3, [r7, #4] 80061dc: 2200 movs r2, #0 80061de: 631a str r2, [r3, #48] @ 0x30 } 80061e0: bf00 nop 80061e2: 3754 adds r7, #84 @ 0x54 80061e4: 46bd mov sp, r7 80061e6: f85d 7b04 ldr.w r7, [sp], #4 80061ea: 4770 bx lr 080061ec : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 80061ec: b580 push {r7, lr} 80061ee: b084 sub sp, #16 80061f0: af00 add r7, sp, #0 80061f2: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80061f4: 687b ldr r3, [r7, #4] 80061f6: 6b9b ldr r3, [r3, #56] @ 0x38 80061f8: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 80061fa: 68fb ldr r3, [r7, #12] 80061fc: 2200 movs r2, #0 80061fe: 85da strh r2, [r3, #46] @ 0x2e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006200: 68f8 ldr r0, [r7, #12] 8006202: f7ff fead bl 8005f60 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006206: bf00 nop 8006208: 3710 adds r7, #16 800620a: 46bd mov sp, r7 800620c: bd80 pop {r7, pc} 0800620e : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 800620e: b480 push {r7} 8006210: b085 sub sp, #20 8006212: af00 add r7, sp, #0 8006214: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8006216: 687b ldr r3, [r7, #4] 8006218: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800621c: b2db uxtb r3, r3 800621e: 2b21 cmp r3, #33 @ 0x21 8006220: d13e bne.n 80062a0 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006222: 687b ldr r3, [r7, #4] 8006224: 689b ldr r3, [r3, #8] 8006226: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800622a: d114 bne.n 8006256 800622c: 687b ldr r3, [r7, #4] 800622e: 691b ldr r3, [r3, #16] 8006230: 2b00 cmp r3, #0 8006232: d110 bne.n 8006256 { tmp = (const uint16_t *) huart->pTxBuffPtr; 8006234: 687b ldr r3, [r7, #4] 8006236: 6a1b ldr r3, [r3, #32] 8006238: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 800623a: 68fb ldr r3, [r7, #12] 800623c: 881b ldrh r3, [r3, #0] 800623e: 461a mov r2, r3 8006240: 687b ldr r3, [r7, #4] 8006242: 681b ldr r3, [r3, #0] 8006244: f3c2 0208 ubfx r2, r2, #0, #9 8006248: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 800624a: 687b ldr r3, [r7, #4] 800624c: 6a1b ldr r3, [r3, #32] 800624e: 1c9a adds r2, r3, #2 8006250: 687b ldr r3, [r7, #4] 8006252: 621a str r2, [r3, #32] 8006254: e008 b.n 8006268 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8006256: 687b ldr r3, [r7, #4] 8006258: 6a1b ldr r3, [r3, #32] 800625a: 1c59 adds r1, r3, #1 800625c: 687a ldr r2, [r7, #4] 800625e: 6211 str r1, [r2, #32] 8006260: 781a ldrb r2, [r3, #0] 8006262: 687b ldr r3, [r7, #4] 8006264: 681b ldr r3, [r3, #0] 8006266: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8006268: 687b ldr r3, [r7, #4] 800626a: 8cdb ldrh r3, [r3, #38] @ 0x26 800626c: b29b uxth r3, r3 800626e: 3b01 subs r3, #1 8006270: b29b uxth r3, r3 8006272: 687a ldr r2, [r7, #4] 8006274: 4619 mov r1, r3 8006276: 84d1 strh r1, [r2, #38] @ 0x26 8006278: 2b00 cmp r3, #0 800627a: d10f bne.n 800629c { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 800627c: 687b ldr r3, [r7, #4] 800627e: 681b ldr r3, [r3, #0] 8006280: 68da ldr r2, [r3, #12] 8006282: 687b ldr r3, [r7, #4] 8006284: 681b ldr r3, [r3, #0] 8006286: f022 0280 bic.w r2, r2, #128 @ 0x80 800628a: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 800628c: 687b ldr r3, [r7, #4] 800628e: 681b ldr r3, [r3, #0] 8006290: 68da ldr r2, [r3, #12] 8006292: 687b ldr r3, [r7, #4] 8006294: 681b ldr r3, [r3, #0] 8006296: f042 0240 orr.w r2, r2, #64 @ 0x40 800629a: 60da str r2, [r3, #12] } return HAL_OK; 800629c: 2300 movs r3, #0 800629e: e000 b.n 80062a2 } else { return HAL_BUSY; 80062a0: 2302 movs r3, #2 } } 80062a2: 4618 mov r0, r3 80062a4: 3714 adds r7, #20 80062a6: 46bd mov sp, r7 80062a8: f85d 7b04 ldr.w r7, [sp], #4 80062ac: 4770 bx lr 080062ae : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80062ae: b580 push {r7, lr} 80062b0: b082 sub sp, #8 80062b2: af00 add r7, sp, #0 80062b4: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 80062b6: 687b ldr r3, [r7, #4] 80062b8: 681b ldr r3, [r3, #0] 80062ba: 68da ldr r2, [r3, #12] 80062bc: 687b ldr r3, [r7, #4] 80062be: 681b ldr r3, [r3, #0] 80062c0: f022 0240 bic.w r2, r2, #64 @ 0x40 80062c4: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80062c6: 687b ldr r3, [r7, #4] 80062c8: 2220 movs r2, #32 80062ca: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 80062ce: 6878 ldr r0, [r7, #4] 80062d0: f7ff fe32 bl 8005f38 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 80062d4: 2300 movs r3, #0 } 80062d6: 4618 mov r0, r3 80062d8: 3708 adds r7, #8 80062da: 46bd mov sp, r7 80062dc: bd80 pop {r7, pc} 080062de : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 80062de: b580 push {r7, lr} 80062e0: b08c sub sp, #48 @ 0x30 80062e2: af00 add r7, sp, #0 80062e4: 6078 str r0, [r7, #4] uint8_t *pdata8bits = NULL; 80062e6: 2300 movs r3, #0 80062e8: 62fb str r3, [r7, #44] @ 0x2c uint16_t *pdata16bits = NULL; 80062ea: 2300 movs r3, #0 80062ec: 62bb str r3, [r7, #40] @ 0x28 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80062ee: 687b ldr r3, [r7, #4] 80062f0: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80062f4: b2db uxtb r3, r3 80062f6: 2b22 cmp r3, #34 @ 0x22 80062f8: f040 80aa bne.w 8006450 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80062fc: 687b ldr r3, [r7, #4] 80062fe: 689b ldr r3, [r3, #8] 8006300: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006304: d115 bne.n 8006332 8006306: 687b ldr r3, [r7, #4] 8006308: 691b ldr r3, [r3, #16] 800630a: 2b00 cmp r3, #0 800630c: d111 bne.n 8006332 { /* Unused pdata8bits */ UNUSED(pdata8bits); pdata16bits = (uint16_t *) huart->pRxBuffPtr; 800630e: 687b ldr r3, [r7, #4] 8006310: 6a9b ldr r3, [r3, #40] @ 0x28 8006312: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8006314: 687b ldr r3, [r7, #4] 8006316: 681b ldr r3, [r3, #0] 8006318: 685b ldr r3, [r3, #4] 800631a: b29b uxth r3, r3 800631c: f3c3 0308 ubfx r3, r3, #0, #9 8006320: b29a uxth r2, r3 8006322: 6abb ldr r3, [r7, #40] @ 0x28 8006324: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8006326: 687b ldr r3, [r7, #4] 8006328: 6a9b ldr r3, [r3, #40] @ 0x28 800632a: 1c9a adds r2, r3, #2 800632c: 687b ldr r3, [r7, #4] 800632e: 629a str r2, [r3, #40] @ 0x28 8006330: e024 b.n 800637c } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8006332: 687b ldr r3, [r7, #4] 8006334: 6a9b ldr r3, [r3, #40] @ 0x28 8006336: 62fb str r3, [r7, #44] @ 0x2c /* Unused pdata16bits */ UNUSED(pdata16bits); if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8006338: 687b ldr r3, [r7, #4] 800633a: 689b ldr r3, [r3, #8] 800633c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006340: d007 beq.n 8006352 8006342: 687b ldr r3, [r7, #4] 8006344: 689b ldr r3, [r3, #8] 8006346: 2b00 cmp r3, #0 8006348: d10a bne.n 8006360 800634a: 687b ldr r3, [r7, #4] 800634c: 691b ldr r3, [r3, #16] 800634e: 2b00 cmp r3, #0 8006350: d106 bne.n 8006360 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8006352: 687b ldr r3, [r7, #4] 8006354: 681b ldr r3, [r3, #0] 8006356: 685b ldr r3, [r3, #4] 8006358: b2da uxtb r2, r3 800635a: 6afb ldr r3, [r7, #44] @ 0x2c 800635c: 701a strb r2, [r3, #0] 800635e: e008 b.n 8006372 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8006360: 687b ldr r3, [r7, #4] 8006362: 681b ldr r3, [r3, #0] 8006364: 685b ldr r3, [r3, #4] 8006366: b2db uxtb r3, r3 8006368: f003 037f and.w r3, r3, #127 @ 0x7f 800636c: b2da uxtb r2, r3 800636e: 6afb ldr r3, [r7, #44] @ 0x2c 8006370: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8006372: 687b ldr r3, [r7, #4] 8006374: 6a9b ldr r3, [r3, #40] @ 0x28 8006376: 1c5a adds r2, r3, #1 8006378: 687b ldr r3, [r7, #4] 800637a: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 800637c: 687b ldr r3, [r7, #4] 800637e: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006380: b29b uxth r3, r3 8006382: 3b01 subs r3, #1 8006384: b29b uxth r3, r3 8006386: 687a ldr r2, [r7, #4] 8006388: 4619 mov r1, r3 800638a: 85d1 strh r1, [r2, #46] @ 0x2e 800638c: 2b00 cmp r3, #0 800638e: d15d bne.n 800644c { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8006390: 687b ldr r3, [r7, #4] 8006392: 681b ldr r3, [r3, #0] 8006394: 68da ldr r2, [r3, #12] 8006396: 687b ldr r3, [r7, #4] 8006398: 681b ldr r3, [r3, #0] 800639a: f022 0220 bic.w r2, r2, #32 800639e: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 80063a0: 687b ldr r3, [r7, #4] 80063a2: 681b ldr r3, [r3, #0] 80063a4: 68da ldr r2, [r3, #12] 80063a6: 687b ldr r3, [r7, #4] 80063a8: 681b ldr r3, [r3, #0] 80063aa: f422 7280 bic.w r2, r2, #256 @ 0x100 80063ae: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 80063b0: 687b ldr r3, [r7, #4] 80063b2: 681b ldr r3, [r3, #0] 80063b4: 695a ldr r2, [r3, #20] 80063b6: 687b ldr r3, [r7, #4] 80063b8: 681b ldr r3, [r3, #0] 80063ba: f022 0201 bic.w r2, r2, #1 80063be: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80063c0: 687b ldr r3, [r7, #4] 80063c2: 2220 movs r2, #32 80063c4: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80063c8: 687b ldr r3, [r7, #4] 80063ca: 2200 movs r2, #0 80063cc: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80063ce: 687b ldr r3, [r7, #4] 80063d0: 6b1b ldr r3, [r3, #48] @ 0x30 80063d2: 2b01 cmp r3, #1 80063d4: d135 bne.n 8006442 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80063d6: 687b ldr r3, [r7, #4] 80063d8: 2200 movs r2, #0 80063da: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80063dc: 687b ldr r3, [r7, #4] 80063de: 681b ldr r3, [r3, #0] 80063e0: 330c adds r3, #12 80063e2: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80063e4: 697b ldr r3, [r7, #20] 80063e6: e853 3f00 ldrex r3, [r3] 80063ea: 613b str r3, [r7, #16] return(result); 80063ec: 693b ldr r3, [r7, #16] 80063ee: f023 0310 bic.w r3, r3, #16 80063f2: 627b str r3, [r7, #36] @ 0x24 80063f4: 687b ldr r3, [r7, #4] 80063f6: 681b ldr r3, [r3, #0] 80063f8: 330c adds r3, #12 80063fa: 6a7a ldr r2, [r7, #36] @ 0x24 80063fc: 623a str r2, [r7, #32] 80063fe: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006400: 69f9 ldr r1, [r7, #28] 8006402: 6a3a ldr r2, [r7, #32] 8006404: e841 2300 strex r3, r2, [r1] 8006408: 61bb str r3, [r7, #24] return(result); 800640a: 69bb ldr r3, [r7, #24] 800640c: 2b00 cmp r3, #0 800640e: d1e5 bne.n 80063dc /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8006410: 687b ldr r3, [r7, #4] 8006412: 681b ldr r3, [r3, #0] 8006414: 681b ldr r3, [r3, #0] 8006416: f003 0310 and.w r3, r3, #16 800641a: 2b10 cmp r3, #16 800641c: d10a bne.n 8006434 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 800641e: 2300 movs r3, #0 8006420: 60fb str r3, [r7, #12] 8006422: 687b ldr r3, [r7, #4] 8006424: 681b ldr r3, [r3, #0] 8006426: 681b ldr r3, [r3, #0] 8006428: 60fb str r3, [r7, #12] 800642a: 687b ldr r3, [r7, #4] 800642c: 681b ldr r3, [r3, #0] 800642e: 685b ldr r3, [r3, #4] 8006430: 60fb str r3, [r7, #12] 8006432: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006434: 687b ldr r3, [r7, #4] 8006436: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006438: 4619 mov r1, r3 800643a: 6878 ldr r0, [r7, #4] 800643c: f7ff fd9a bl 8005f74 8006440: e002 b.n 8006448 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8006442: 6878 ldr r0, [r7, #4] 8006444: f7fa fade bl 8000a04 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8006448: 2300 movs r3, #0 800644a: e002 b.n 8006452 } return HAL_OK; 800644c: 2300 movs r3, #0 800644e: e000 b.n 8006452 } else { return HAL_BUSY; 8006450: 2302 movs r3, #2 } } 8006452: 4618 mov r0, r3 8006454: 3730 adds r7, #48 @ 0x30 8006456: 46bd mov sp, r7 8006458: bd80 pop {r7, pc} ... 0800645c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 800645c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8006460: b0c0 sub sp, #256 @ 0x100 8006462: af00 add r7, sp, #0 8006464: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4 assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8006468: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800646c: 681b ldr r3, [r3, #0] 800646e: 691b ldr r3, [r3, #16] 8006470: f423 5040 bic.w r0, r3, #12288 @ 0x3000 8006474: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006478: 68d9 ldr r1, [r3, #12] 800647a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800647e: 681a ldr r2, [r3, #0] 8006480: ea40 0301 orr.w r3, r0, r1 8006484: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 8006486: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800648a: 689a ldr r2, [r3, #8] 800648c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006490: 691b ldr r3, [r3, #16] 8006492: 431a orrs r2, r3 8006494: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006498: 695b ldr r3, [r3, #20] 800649a: 431a orrs r2, r3 800649c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80064a0: 69db ldr r3, [r3, #28] 80064a2: 4313 orrs r3, r2 80064a4: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 MODIFY_REG(huart->Instance->CR1, 80064a8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80064ac: 681b ldr r3, [r3, #0] 80064ae: 68db ldr r3, [r3, #12] 80064b0: f423 4116 bic.w r1, r3, #38400 @ 0x9600 80064b4: f021 010c bic.w r1, r1, #12 80064b8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80064bc: 681a ldr r2, [r3, #0] 80064be: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 80064c2: 430b orrs r3, r1 80064c4: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 80064c6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80064ca: 681b ldr r3, [r3, #0] 80064cc: 695b ldr r3, [r3, #20] 80064ce: f423 7040 bic.w r0, r3, #768 @ 0x300 80064d2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80064d6: 6999 ldr r1, [r3, #24] 80064d8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80064dc: 681a ldr r2, [r3, #0] 80064de: ea40 0301 orr.w r3, r0, r1 80064e2: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 80064e4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80064e8: 681a ldr r2, [r3, #0] 80064ea: 4b8f ldr r3, [pc, #572] @ (8006728 ) 80064ec: 429a cmp r2, r3 80064ee: d005 beq.n 80064fc 80064f0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80064f4: 681a ldr r2, [r3, #0] 80064f6: 4b8d ldr r3, [pc, #564] @ (800672c ) 80064f8: 429a cmp r2, r3 80064fa: d104 bne.n 8006506 { pclk = HAL_RCC_GetPCLK2Freq(); 80064fc: f7fd fd76 bl 8003fec 8006500: f8c7 00fc str.w r0, [r7, #252] @ 0xfc 8006504: e003 b.n 800650e pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); 8006506: f7fd fd5d bl 8003fc4 800650a: f8c7 00fc str.w r0, [r7, #252] @ 0xfc } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800650e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006512: 69db ldr r3, [r3, #28] 8006514: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8006518: f040 810c bne.w 8006734 { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 800651c: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006520: 2200 movs r2, #0 8006522: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 8006526: f8c7 20ec str.w r2, [r7, #236] @ 0xec 800652a: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8 800652e: 4622 mov r2, r4 8006530: 462b mov r3, r5 8006532: 1891 adds r1, r2, r2 8006534: 65b9 str r1, [r7, #88] @ 0x58 8006536: 415b adcs r3, r3 8006538: 65fb str r3, [r7, #92] @ 0x5c 800653a: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 800653e: 4621 mov r1, r4 8006540: eb12 0801 adds.w r8, r2, r1 8006544: 4629 mov r1, r5 8006546: eb43 0901 adc.w r9, r3, r1 800654a: f04f 0200 mov.w r2, #0 800654e: f04f 0300 mov.w r3, #0 8006552: ea4f 03c9 mov.w r3, r9, lsl #3 8006556: ea43 7358 orr.w r3, r3, r8, lsr #29 800655a: ea4f 02c8 mov.w r2, r8, lsl #3 800655e: 4690 mov r8, r2 8006560: 4699 mov r9, r3 8006562: 4623 mov r3, r4 8006564: eb18 0303 adds.w r3, r8, r3 8006568: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800656c: 462b mov r3, r5 800656e: eb49 0303 adc.w r3, r9, r3 8006572: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 8006576: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800657a: 685b ldr r3, [r3, #4] 800657c: 2200 movs r2, #0 800657e: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 8006582: f8c7 20dc str.w r2, [r7, #220] @ 0xdc 8006586: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 800658a: 460b mov r3, r1 800658c: 18db adds r3, r3, r3 800658e: 653b str r3, [r7, #80] @ 0x50 8006590: 4613 mov r3, r2 8006592: eb42 0303 adc.w r3, r2, r3 8006596: 657b str r3, [r7, #84] @ 0x54 8006598: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50 800659c: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0 80065a0: f7f9 fe30 bl 8000204 <__aeabi_uldivmod> 80065a4: 4602 mov r2, r0 80065a6: 460b mov r3, r1 80065a8: 4b61 ldr r3, [pc, #388] @ (8006730 ) 80065aa: fba3 2302 umull r2, r3, r3, r2 80065ae: 095b lsrs r3, r3, #5 80065b0: 011c lsls r4, r3, #4 80065b2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 80065b6: 2200 movs r2, #0 80065b8: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 80065bc: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4 80065c0: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0 80065c4: 4642 mov r2, r8 80065c6: 464b mov r3, r9 80065c8: 1891 adds r1, r2, r2 80065ca: 64b9 str r1, [r7, #72] @ 0x48 80065cc: 415b adcs r3, r3 80065ce: 64fb str r3, [r7, #76] @ 0x4c 80065d0: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 80065d4: 4641 mov r1, r8 80065d6: eb12 0a01 adds.w sl, r2, r1 80065da: 4649 mov r1, r9 80065dc: eb43 0b01 adc.w fp, r3, r1 80065e0: f04f 0200 mov.w r2, #0 80065e4: f04f 0300 mov.w r3, #0 80065e8: ea4f 03cb mov.w r3, fp, lsl #3 80065ec: ea43 735a orr.w r3, r3, sl, lsr #29 80065f0: ea4f 02ca mov.w r2, sl, lsl #3 80065f4: 4692 mov sl, r2 80065f6: 469b mov fp, r3 80065f8: 4643 mov r3, r8 80065fa: eb1a 0303 adds.w r3, sl, r3 80065fe: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8006602: 464b mov r3, r9 8006604: eb4b 0303 adc.w r3, fp, r3 8006608: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 800660c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006610: 685b ldr r3, [r3, #4] 8006612: 2200 movs r2, #0 8006614: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8006618: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4 800661c: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 8006620: 460b mov r3, r1 8006622: 18db adds r3, r3, r3 8006624: 643b str r3, [r7, #64] @ 0x40 8006626: 4613 mov r3, r2 8006628: eb42 0303 adc.w r3, r2, r3 800662c: 647b str r3, [r7, #68] @ 0x44 800662e: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40 8006632: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8 8006636: f7f9 fde5 bl 8000204 <__aeabi_uldivmod> 800663a: 4602 mov r2, r0 800663c: 460b mov r3, r1 800663e: 4611 mov r1, r2 8006640: 4b3b ldr r3, [pc, #236] @ (8006730 ) 8006642: fba3 2301 umull r2, r3, r3, r1 8006646: 095b lsrs r3, r3, #5 8006648: 2264 movs r2, #100 @ 0x64 800664a: fb02 f303 mul.w r3, r2, r3 800664e: 1acb subs r3, r1, r3 8006650: 00db lsls r3, r3, #3 8006652: f103 0232 add.w r2, r3, #50 @ 0x32 8006656: 4b36 ldr r3, [pc, #216] @ (8006730 ) 8006658: fba3 2302 umull r2, r3, r3, r2 800665c: 095b lsrs r3, r3, #5 800665e: 005b lsls r3, r3, #1 8006660: f403 73f8 and.w r3, r3, #496 @ 0x1f0 8006664: 441c add r4, r3 8006666: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 800666a: 2200 movs r2, #0 800666c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006670: f8c7 20bc str.w r2, [r7, #188] @ 0xbc 8006674: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8 8006678: 4642 mov r2, r8 800667a: 464b mov r3, r9 800667c: 1891 adds r1, r2, r2 800667e: 63b9 str r1, [r7, #56] @ 0x38 8006680: 415b adcs r3, r3 8006682: 63fb str r3, [r7, #60] @ 0x3c 8006684: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38 8006688: 4641 mov r1, r8 800668a: 1851 adds r1, r2, r1 800668c: 6339 str r1, [r7, #48] @ 0x30 800668e: 4649 mov r1, r9 8006690: 414b adcs r3, r1 8006692: 637b str r3, [r7, #52] @ 0x34 8006694: f04f 0200 mov.w r2, #0 8006698: f04f 0300 mov.w r3, #0 800669c: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30 80066a0: 4659 mov r1, fp 80066a2: 00cb lsls r3, r1, #3 80066a4: 4651 mov r1, sl 80066a6: ea43 7351 orr.w r3, r3, r1, lsr #29 80066aa: 4651 mov r1, sl 80066ac: 00ca lsls r2, r1, #3 80066ae: 4610 mov r0, r2 80066b0: 4619 mov r1, r3 80066b2: 4603 mov r3, r0 80066b4: 4642 mov r2, r8 80066b6: 189b adds r3, r3, r2 80066b8: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 80066bc: 464b mov r3, r9 80066be: 460a mov r2, r1 80066c0: eb42 0303 adc.w r3, r2, r3 80066c4: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 80066c8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80066cc: 685b ldr r3, [r3, #4] 80066ce: 2200 movs r2, #0 80066d0: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 80066d4: f8c7 20ac str.w r2, [r7, #172] @ 0xac 80066d8: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 80066dc: 460b mov r3, r1 80066de: 18db adds r3, r3, r3 80066e0: 62bb str r3, [r7, #40] @ 0x28 80066e2: 4613 mov r3, r2 80066e4: eb42 0303 adc.w r3, r2, r3 80066e8: 62fb str r3, [r7, #44] @ 0x2c 80066ea: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 80066ee: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0 80066f2: f7f9 fd87 bl 8000204 <__aeabi_uldivmod> 80066f6: 4602 mov r2, r0 80066f8: 460b mov r3, r1 80066fa: 4b0d ldr r3, [pc, #52] @ (8006730 ) 80066fc: fba3 1302 umull r1, r3, r3, r2 8006700: 095b lsrs r3, r3, #5 8006702: 2164 movs r1, #100 @ 0x64 8006704: fb01 f303 mul.w r3, r1, r3 8006708: 1ad3 subs r3, r2, r3 800670a: 00db lsls r3, r3, #3 800670c: 3332 adds r3, #50 @ 0x32 800670e: 4a08 ldr r2, [pc, #32] @ (8006730 ) 8006710: fba2 2303 umull r2, r3, r2, r3 8006714: 095b lsrs r3, r3, #5 8006716: f003 0207 and.w r2, r3, #7 800671a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800671e: 681b ldr r3, [r3, #0] 8006720: 4422 add r2, r4 8006722: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } 8006724: e106 b.n 8006934 8006726: bf00 nop 8006728: 40011000 .word 0x40011000 800672c: 40011400 .word 0x40011400 8006730: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8006734: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006738: 2200 movs r2, #0 800673a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800673e: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4 8006742: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0 8006746: 4642 mov r2, r8 8006748: 464b mov r3, r9 800674a: 1891 adds r1, r2, r2 800674c: 6239 str r1, [r7, #32] 800674e: 415b adcs r3, r3 8006750: 627b str r3, [r7, #36] @ 0x24 8006752: e9d7 2308 ldrd r2, r3, [r7, #32] 8006756: 4641 mov r1, r8 8006758: 1854 adds r4, r2, r1 800675a: 4649 mov r1, r9 800675c: eb43 0501 adc.w r5, r3, r1 8006760: f04f 0200 mov.w r2, #0 8006764: f04f 0300 mov.w r3, #0 8006768: 00eb lsls r3, r5, #3 800676a: ea43 7354 orr.w r3, r3, r4, lsr #29 800676e: 00e2 lsls r2, r4, #3 8006770: 4614 mov r4, r2 8006772: 461d mov r5, r3 8006774: 4643 mov r3, r8 8006776: 18e3 adds r3, r4, r3 8006778: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800677c: 464b mov r3, r9 800677e: eb45 0303 adc.w r3, r5, r3 8006782: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8006786: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800678a: 685b ldr r3, [r3, #4] 800678c: 2200 movs r2, #0 800678e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8006792: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8006796: f04f 0200 mov.w r2, #0 800679a: f04f 0300 mov.w r3, #0 800679e: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 80067a2: 4629 mov r1, r5 80067a4: 008b lsls r3, r1, #2 80067a6: 4621 mov r1, r4 80067a8: ea43 7391 orr.w r3, r3, r1, lsr #30 80067ac: 4621 mov r1, r4 80067ae: 008a lsls r2, r1, #2 80067b0: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98 80067b4: f7f9 fd26 bl 8000204 <__aeabi_uldivmod> 80067b8: 4602 mov r2, r0 80067ba: 460b mov r3, r1 80067bc: 4b60 ldr r3, [pc, #384] @ (8006940 ) 80067be: fba3 2302 umull r2, r3, r3, r2 80067c2: 095b lsrs r3, r3, #5 80067c4: 011c lsls r4, r3, #4 80067c6: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 80067ca: 2200 movs r2, #0 80067cc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 80067d0: f8c7 208c str.w r2, [r7, #140] @ 0x8c 80067d4: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88 80067d8: 4642 mov r2, r8 80067da: 464b mov r3, r9 80067dc: 1891 adds r1, r2, r2 80067de: 61b9 str r1, [r7, #24] 80067e0: 415b adcs r3, r3 80067e2: 61fb str r3, [r7, #28] 80067e4: e9d7 2306 ldrd r2, r3, [r7, #24] 80067e8: 4641 mov r1, r8 80067ea: 1851 adds r1, r2, r1 80067ec: 6139 str r1, [r7, #16] 80067ee: 4649 mov r1, r9 80067f0: 414b adcs r3, r1 80067f2: 617b str r3, [r7, #20] 80067f4: f04f 0200 mov.w r2, #0 80067f8: f04f 0300 mov.w r3, #0 80067fc: e9d7 ab04 ldrd sl, fp, [r7, #16] 8006800: 4659 mov r1, fp 8006802: 00cb lsls r3, r1, #3 8006804: 4651 mov r1, sl 8006806: ea43 7351 orr.w r3, r3, r1, lsr #29 800680a: 4651 mov r1, sl 800680c: 00ca lsls r2, r1, #3 800680e: 4610 mov r0, r2 8006810: 4619 mov r1, r3 8006812: 4603 mov r3, r0 8006814: 4642 mov r2, r8 8006816: 189b adds r3, r3, r2 8006818: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800681c: 464b mov r3, r9 800681e: 460a mov r2, r1 8006820: eb42 0303 adc.w r3, r2, r3 8006824: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8006828: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800682c: 685b ldr r3, [r3, #4] 800682e: 2200 movs r2, #0 8006830: 67bb str r3, [r7, #120] @ 0x78 8006832: 67fa str r2, [r7, #124] @ 0x7c 8006834: f04f 0200 mov.w r2, #0 8006838: f04f 0300 mov.w r3, #0 800683c: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78 8006840: 4649 mov r1, r9 8006842: 008b lsls r3, r1, #2 8006844: 4641 mov r1, r8 8006846: ea43 7391 orr.w r3, r3, r1, lsr #30 800684a: 4641 mov r1, r8 800684c: 008a lsls r2, r1, #2 800684e: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80 8006852: f7f9 fcd7 bl 8000204 <__aeabi_uldivmod> 8006856: 4602 mov r2, r0 8006858: 460b mov r3, r1 800685a: 4611 mov r1, r2 800685c: 4b38 ldr r3, [pc, #224] @ (8006940 ) 800685e: fba3 2301 umull r2, r3, r3, r1 8006862: 095b lsrs r3, r3, #5 8006864: 2264 movs r2, #100 @ 0x64 8006866: fb02 f303 mul.w r3, r2, r3 800686a: 1acb subs r3, r1, r3 800686c: 011b lsls r3, r3, #4 800686e: 3332 adds r3, #50 @ 0x32 8006870: 4a33 ldr r2, [pc, #204] @ (8006940 ) 8006872: fba2 2303 umull r2, r3, r2, r3 8006876: 095b lsrs r3, r3, #5 8006878: f003 03f0 and.w r3, r3, #240 @ 0xf0 800687c: 441c add r4, r3 800687e: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006882: 2200 movs r2, #0 8006884: 673b str r3, [r7, #112] @ 0x70 8006886: 677a str r2, [r7, #116] @ 0x74 8006888: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70 800688c: 4642 mov r2, r8 800688e: 464b mov r3, r9 8006890: 1891 adds r1, r2, r2 8006892: 60b9 str r1, [r7, #8] 8006894: 415b adcs r3, r3 8006896: 60fb str r3, [r7, #12] 8006898: e9d7 2302 ldrd r2, r3, [r7, #8] 800689c: 4641 mov r1, r8 800689e: 1851 adds r1, r2, r1 80068a0: 6039 str r1, [r7, #0] 80068a2: 4649 mov r1, r9 80068a4: 414b adcs r3, r1 80068a6: 607b str r3, [r7, #4] 80068a8: f04f 0200 mov.w r2, #0 80068ac: f04f 0300 mov.w r3, #0 80068b0: e9d7 ab00 ldrd sl, fp, [r7] 80068b4: 4659 mov r1, fp 80068b6: 00cb lsls r3, r1, #3 80068b8: 4651 mov r1, sl 80068ba: ea43 7351 orr.w r3, r3, r1, lsr #29 80068be: 4651 mov r1, sl 80068c0: 00ca lsls r2, r1, #3 80068c2: 4610 mov r0, r2 80068c4: 4619 mov r1, r3 80068c6: 4603 mov r3, r0 80068c8: 4642 mov r2, r8 80068ca: 189b adds r3, r3, r2 80068cc: 66bb str r3, [r7, #104] @ 0x68 80068ce: 464b mov r3, r9 80068d0: 460a mov r2, r1 80068d2: eb42 0303 adc.w r3, r2, r3 80068d6: 66fb str r3, [r7, #108] @ 0x6c 80068d8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80068dc: 685b ldr r3, [r3, #4] 80068de: 2200 movs r2, #0 80068e0: 663b str r3, [r7, #96] @ 0x60 80068e2: 667a str r2, [r7, #100] @ 0x64 80068e4: f04f 0200 mov.w r2, #0 80068e8: f04f 0300 mov.w r3, #0 80068ec: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60 80068f0: 4649 mov r1, r9 80068f2: 008b lsls r3, r1, #2 80068f4: 4641 mov r1, r8 80068f6: ea43 7391 orr.w r3, r3, r1, lsr #30 80068fa: 4641 mov r1, r8 80068fc: 008a lsls r2, r1, #2 80068fe: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68 8006902: f7f9 fc7f bl 8000204 <__aeabi_uldivmod> 8006906: 4602 mov r2, r0 8006908: 460b mov r3, r1 800690a: 4b0d ldr r3, [pc, #52] @ (8006940 ) 800690c: fba3 1302 umull r1, r3, r3, r2 8006910: 095b lsrs r3, r3, #5 8006912: 2164 movs r1, #100 @ 0x64 8006914: fb01 f303 mul.w r3, r1, r3 8006918: 1ad3 subs r3, r2, r3 800691a: 011b lsls r3, r3, #4 800691c: 3332 adds r3, #50 @ 0x32 800691e: 4a08 ldr r2, [pc, #32] @ (8006940 ) 8006920: fba2 2303 umull r2, r3, r2, r3 8006924: 095b lsrs r3, r3, #5 8006926: f003 020f and.w r2, r3, #15 800692a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800692e: 681b ldr r3, [r3, #0] 8006930: 4422 add r2, r4 8006932: 609a str r2, [r3, #8] } 8006934: bf00 nop 8006936: f507 7780 add.w r7, r7, #256 @ 0x100 800693a: 46bd mov sp, r7 800693c: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8006940: 51eb851f .word 0x51eb851f 08006944 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8006944: b084 sub sp, #16 8006946: b580 push {r7, lr} 8006948: b084 sub sp, #16 800694a: af00 add r7, sp, #0 800694c: 6078 str r0, [r7, #4] 800694e: f107 001c add.w r0, r7, #28 8006952: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8006956: f897 3021 ldrb.w r3, [r7, #33] @ 0x21 800695a: 2b01 cmp r3, #1 800695c: d123 bne.n 80069a6 { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 800695e: 687b ldr r3, [r7, #4] 8006960: 6b9b ldr r3, [r3, #56] @ 0x38 8006962: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8006966: 687b ldr r3, [r7, #4] 8006968: 639a str r2, [r3, #56] @ 0x38 /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); 800696a: 687b ldr r3, [r7, #4] 800696c: 68db ldr r3, [r3, #12] 800696e: f423 0384 bic.w r3, r3, #4325376 @ 0x420000 8006972: f023 0340 bic.w r3, r3, #64 @ 0x40 8006976: 687a ldr r2, [r7, #4] 8006978: 60d3 str r3, [r2, #12] /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); 800697a: 687b ldr r3, [r7, #4] 800697c: 68db ldr r3, [r3, #12] 800697e: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 8006982: 687b ldr r3, [r7, #4] 8006984: 60da str r2, [r3, #12] if (cfg.use_external_vbus == 1U) 8006986: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 800698a: 2b01 cmp r3, #1 800698c: d105 bne.n 800699a { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; 800698e: 687b ldr r3, [r7, #4] 8006990: 68db ldr r3, [r3, #12] 8006992: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 8006996: 687b ldr r3, [r7, #4] 8006998: 60da str r2, [r3, #12] } /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 800699a: 6878 ldr r0, [r7, #4] 800699c: f001 fae2 bl 8007f64 80069a0: 4603 mov r3, r0 80069a2: 73fb strb r3, [r7, #15] 80069a4: e01b b.n 80069de } else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 80069a6: 687b ldr r3, [r7, #4] 80069a8: 68db ldr r3, [r3, #12] 80069aa: f043 0240 orr.w r2, r3, #64 @ 0x40 80069ae: 687b ldr r3, [r7, #4] 80069b0: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 80069b2: 6878 ldr r0, [r7, #4] 80069b4: f001 fad6 bl 8007f64 80069b8: 4603 mov r3, r0 80069ba: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 80069bc: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 80069c0: 2b00 cmp r3, #0 80069c2: d106 bne.n 80069d2 { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 80069c4: 687b ldr r3, [r7, #4] 80069c6: 6b9b ldr r3, [r3, #56] @ 0x38 80069c8: f443 3280 orr.w r2, r3, #65536 @ 0x10000 80069cc: 687b ldr r3, [r7, #4] 80069ce: 639a str r2, [r3, #56] @ 0x38 80069d0: e005 b.n 80069de } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 80069d2: 687b ldr r3, [r7, #4] 80069d4: 6b9b ldr r3, [r3, #56] @ 0x38 80069d6: f423 3280 bic.w r2, r3, #65536 @ 0x10000 80069da: 687b ldr r3, [r7, #4] 80069dc: 639a str r2, [r3, #56] @ 0x38 } } if (cfg.dma_enable == 1U) 80069de: 7fbb ldrb r3, [r7, #30] 80069e0: 2b01 cmp r3, #1 80069e2: d10b bne.n 80069fc { USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; 80069e4: 687b ldr r3, [r7, #4] 80069e6: 689b ldr r3, [r3, #8] 80069e8: f043 0206 orr.w r2, r3, #6 80069ec: 687b ldr r3, [r7, #4] 80069ee: 609a str r2, [r3, #8] USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; 80069f0: 687b ldr r3, [r7, #4] 80069f2: 689b ldr r3, [r3, #8] 80069f4: f043 0220 orr.w r2, r3, #32 80069f8: 687b ldr r3, [r7, #4] 80069fa: 609a str r2, [r3, #8] } return ret; 80069fc: 7bfb ldrb r3, [r7, #15] } 80069fe: 4618 mov r0, r3 8006a00: 3710 adds r7, #16 8006a02: 46bd mov sp, r7 8006a04: e8bd 4080 ldmia.w sp!, {r7, lr} 8006a08: b004 add sp, #16 8006a0a: 4770 bx lr 08006a0c : * @param hclk: AHB clock frequency * @retval USB turnaround time In PHY Clocks number */ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed) { 8006a0c: b480 push {r7} 8006a0e: b087 sub sp, #28 8006a10: af00 add r7, sp, #0 8006a12: 60f8 str r0, [r7, #12] 8006a14: 60b9 str r1, [r7, #8] 8006a16: 4613 mov r3, r2 8006a18: 71fb strb r3, [r7, #7] /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ if (speed == USBD_FS_SPEED) 8006a1a: 79fb ldrb r3, [r7, #7] 8006a1c: 2b02 cmp r3, #2 8006a1e: d165 bne.n 8006aec { if ((hclk >= 14200000U) && (hclk < 15000000U)) 8006a20: 68bb ldr r3, [r7, #8] 8006a22: 4a41 ldr r2, [pc, #260] @ (8006b28 ) 8006a24: 4293 cmp r3, r2 8006a26: d906 bls.n 8006a36 8006a28: 68bb ldr r3, [r7, #8] 8006a2a: 4a40 ldr r2, [pc, #256] @ (8006b2c ) 8006a2c: 4293 cmp r3, r2 8006a2e: d202 bcs.n 8006a36 { /* hclk Clock Range between 14.2-15 MHz */ UsbTrd = 0xFU; 8006a30: 230f movs r3, #15 8006a32: 617b str r3, [r7, #20] 8006a34: e062 b.n 8006afc } else if ((hclk >= 15000000U) && (hclk < 16000000U)) 8006a36: 68bb ldr r3, [r7, #8] 8006a38: 4a3c ldr r2, [pc, #240] @ (8006b2c ) 8006a3a: 4293 cmp r3, r2 8006a3c: d306 bcc.n 8006a4c 8006a3e: 68bb ldr r3, [r7, #8] 8006a40: 4a3b ldr r2, [pc, #236] @ (8006b30 ) 8006a42: 4293 cmp r3, r2 8006a44: d202 bcs.n 8006a4c { /* hclk Clock Range between 15-16 MHz */ UsbTrd = 0xEU; 8006a46: 230e movs r3, #14 8006a48: 617b str r3, [r7, #20] 8006a4a: e057 b.n 8006afc } else if ((hclk >= 16000000U) && (hclk < 17200000U)) 8006a4c: 68bb ldr r3, [r7, #8] 8006a4e: 4a38 ldr r2, [pc, #224] @ (8006b30 ) 8006a50: 4293 cmp r3, r2 8006a52: d306 bcc.n 8006a62 8006a54: 68bb ldr r3, [r7, #8] 8006a56: 4a37 ldr r2, [pc, #220] @ (8006b34 ) 8006a58: 4293 cmp r3, r2 8006a5a: d202 bcs.n 8006a62 { /* hclk Clock Range between 16-17.2 MHz */ UsbTrd = 0xDU; 8006a5c: 230d movs r3, #13 8006a5e: 617b str r3, [r7, #20] 8006a60: e04c b.n 8006afc } else if ((hclk >= 17200000U) && (hclk < 18500000U)) 8006a62: 68bb ldr r3, [r7, #8] 8006a64: 4a33 ldr r2, [pc, #204] @ (8006b34 ) 8006a66: 4293 cmp r3, r2 8006a68: d306 bcc.n 8006a78 8006a6a: 68bb ldr r3, [r7, #8] 8006a6c: 4a32 ldr r2, [pc, #200] @ (8006b38 ) 8006a6e: 4293 cmp r3, r2 8006a70: d802 bhi.n 8006a78 { /* hclk Clock Range between 17.2-18.5 MHz */ UsbTrd = 0xCU; 8006a72: 230c movs r3, #12 8006a74: 617b str r3, [r7, #20] 8006a76: e041 b.n 8006afc } else if ((hclk >= 18500000U) && (hclk < 20000000U)) 8006a78: 68bb ldr r3, [r7, #8] 8006a7a: 4a2f ldr r2, [pc, #188] @ (8006b38 ) 8006a7c: 4293 cmp r3, r2 8006a7e: d906 bls.n 8006a8e 8006a80: 68bb ldr r3, [r7, #8] 8006a82: 4a2e ldr r2, [pc, #184] @ (8006b3c ) 8006a84: 4293 cmp r3, r2 8006a86: d802 bhi.n 8006a8e { /* hclk Clock Range between 18.5-20 MHz */ UsbTrd = 0xBU; 8006a88: 230b movs r3, #11 8006a8a: 617b str r3, [r7, #20] 8006a8c: e036 b.n 8006afc } else if ((hclk >= 20000000U) && (hclk < 21800000U)) 8006a8e: 68bb ldr r3, [r7, #8] 8006a90: 4a2a ldr r2, [pc, #168] @ (8006b3c ) 8006a92: 4293 cmp r3, r2 8006a94: d906 bls.n 8006aa4 8006a96: 68bb ldr r3, [r7, #8] 8006a98: 4a29 ldr r2, [pc, #164] @ (8006b40 ) 8006a9a: 4293 cmp r3, r2 8006a9c: d802 bhi.n 8006aa4 { /* hclk Clock Range between 20-21.8 MHz */ UsbTrd = 0xAU; 8006a9e: 230a movs r3, #10 8006aa0: 617b str r3, [r7, #20] 8006aa2: e02b b.n 8006afc } else if ((hclk >= 21800000U) && (hclk < 24000000U)) 8006aa4: 68bb ldr r3, [r7, #8] 8006aa6: 4a26 ldr r2, [pc, #152] @ (8006b40 ) 8006aa8: 4293 cmp r3, r2 8006aaa: d906 bls.n 8006aba 8006aac: 68bb ldr r3, [r7, #8] 8006aae: 4a25 ldr r2, [pc, #148] @ (8006b44 ) 8006ab0: 4293 cmp r3, r2 8006ab2: d202 bcs.n 8006aba { /* hclk Clock Range between 21.8-24 MHz */ UsbTrd = 0x9U; 8006ab4: 2309 movs r3, #9 8006ab6: 617b str r3, [r7, #20] 8006ab8: e020 b.n 8006afc } else if ((hclk >= 24000000U) && (hclk < 27700000U)) 8006aba: 68bb ldr r3, [r7, #8] 8006abc: 4a21 ldr r2, [pc, #132] @ (8006b44 ) 8006abe: 4293 cmp r3, r2 8006ac0: d306 bcc.n 8006ad0 8006ac2: 68bb ldr r3, [r7, #8] 8006ac4: 4a20 ldr r2, [pc, #128] @ (8006b48 ) 8006ac6: 4293 cmp r3, r2 8006ac8: d802 bhi.n 8006ad0 { /* hclk Clock Range between 24-27.7 MHz */ UsbTrd = 0x8U; 8006aca: 2308 movs r3, #8 8006acc: 617b str r3, [r7, #20] 8006ace: e015 b.n 8006afc } else if ((hclk >= 27700000U) && (hclk < 32000000U)) 8006ad0: 68bb ldr r3, [r7, #8] 8006ad2: 4a1d ldr r2, [pc, #116] @ (8006b48 ) 8006ad4: 4293 cmp r3, r2 8006ad6: d906 bls.n 8006ae6 8006ad8: 68bb ldr r3, [r7, #8] 8006ada: 4a1c ldr r2, [pc, #112] @ (8006b4c ) 8006adc: 4293 cmp r3, r2 8006ade: d202 bcs.n 8006ae6 { /* hclk Clock Range between 27.7-32 MHz */ UsbTrd = 0x7U; 8006ae0: 2307 movs r3, #7 8006ae2: 617b str r3, [r7, #20] 8006ae4: e00a b.n 8006afc } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ UsbTrd = 0x6U; 8006ae6: 2306 movs r3, #6 8006ae8: 617b str r3, [r7, #20] 8006aea: e007 b.n 8006afc } } else if (speed == USBD_HS_SPEED) 8006aec: 79fb ldrb r3, [r7, #7] 8006aee: 2b00 cmp r3, #0 8006af0: d102 bne.n 8006af8 { UsbTrd = USBD_HS_TRDT_VALUE; 8006af2: 2309 movs r3, #9 8006af4: 617b str r3, [r7, #20] 8006af6: e001 b.n 8006afc } else { UsbTrd = USBD_DEFAULT_TRDT_VALUE; 8006af8: 2309 movs r3, #9 8006afa: 617b str r3, [r7, #20] } USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; 8006afc: 68fb ldr r3, [r7, #12] 8006afe: 68db ldr r3, [r3, #12] 8006b00: f423 5270 bic.w r2, r3, #15360 @ 0x3c00 8006b04: 68fb ldr r3, [r7, #12] 8006b06: 60da str r2, [r3, #12] USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); 8006b08: 68fb ldr r3, [r7, #12] 8006b0a: 68da ldr r2, [r3, #12] 8006b0c: 697b ldr r3, [r7, #20] 8006b0e: 029b lsls r3, r3, #10 8006b10: f403 5370 and.w r3, r3, #15360 @ 0x3c00 8006b14: 431a orrs r2, r3 8006b16: 68fb ldr r3, [r7, #12] 8006b18: 60da str r2, [r3, #12] return HAL_OK; 8006b1a: 2300 movs r3, #0 } 8006b1c: 4618 mov r0, r3 8006b1e: 371c adds r7, #28 8006b20: 46bd mov sp, r7 8006b22: f85d 7b04 ldr.w r7, [sp], #4 8006b26: 4770 bx lr 8006b28: 00d8acbf .word 0x00d8acbf 8006b2c: 00e4e1c0 .word 0x00e4e1c0 8006b30: 00f42400 .word 0x00f42400 8006b34: 01067380 .word 0x01067380 8006b38: 011a499f .word 0x011a499f 8006b3c: 01312cff .word 0x01312cff 8006b40: 014ca43f .word 0x014ca43f 8006b44: 016e3600 .word 0x016e3600 8006b48: 01a6ab1f .word 0x01a6ab1f 8006b4c: 01e84800 .word 0x01e84800 08006b50 : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8006b50: b480 push {r7} 8006b52: b083 sub sp, #12 8006b54: af00 add r7, sp, #0 8006b56: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 8006b58: 687b ldr r3, [r7, #4] 8006b5a: 689b ldr r3, [r3, #8] 8006b5c: f043 0201 orr.w r2, r3, #1 8006b60: 687b ldr r3, [r7, #4] 8006b62: 609a str r2, [r3, #8] return HAL_OK; 8006b64: 2300 movs r3, #0 } 8006b66: 4618 mov r0, r3 8006b68: 370c adds r7, #12 8006b6a: 46bd mov sp, r7 8006b6c: f85d 7b04 ldr.w r7, [sp], #4 8006b70: 4770 bx lr 08006b72 : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8006b72: b480 push {r7} 8006b74: b083 sub sp, #12 8006b76: af00 add r7, sp, #0 8006b78: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 8006b7a: 687b ldr r3, [r7, #4] 8006b7c: 689b ldr r3, [r3, #8] 8006b7e: f023 0201 bic.w r2, r3, #1 8006b82: 687b ldr r3, [r7, #4] 8006b84: 609a str r2, [r3, #8] return HAL_OK; 8006b86: 2300 movs r3, #0 } 8006b88: 4618 mov r0, r3 8006b8a: 370c adds r7, #12 8006b8c: 46bd mov sp, r7 8006b8e: f85d 7b04 ldr.w r7, [sp], #4 8006b92: 4770 bx lr 08006b94 : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { 8006b94: b580 push {r7, lr} 8006b96: b084 sub sp, #16 8006b98: af00 add r7, sp, #0 8006b9a: 6078 str r0, [r7, #4] 8006b9c: 460b mov r3, r1 8006b9e: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 8006ba0: 2300 movs r3, #0 8006ba2: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 8006ba4: 687b ldr r3, [r7, #4] 8006ba6: 68db ldr r3, [r3, #12] 8006ba8: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000 8006bac: 687b ldr r3, [r7, #4] 8006bae: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 8006bb0: 78fb ldrb r3, [r7, #3] 8006bb2: 2b01 cmp r3, #1 8006bb4: d115 bne.n 8006be2 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 8006bb6: 687b ldr r3, [r7, #4] 8006bb8: 68db ldr r3, [r3, #12] 8006bba: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 8006bbe: 687b ldr r3, [r7, #4] 8006bc0: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8006bc2: 200a movs r0, #10 8006bc4: f7fa fe44 bl 8001850 ms += 10U; 8006bc8: 68fb ldr r3, [r7, #12] 8006bca: 330a adds r3, #10 8006bcc: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8006bce: 6878 ldr r0, [r7, #4] 8006bd0: f001 f939 bl 8007e46 8006bd4: 4603 mov r3, r0 8006bd6: 2b01 cmp r3, #1 8006bd8: d01e beq.n 8006c18 8006bda: 68fb ldr r3, [r7, #12] 8006bdc: 2bc7 cmp r3, #199 @ 0xc7 8006bde: d9f0 bls.n 8006bc2 8006be0: e01a b.n 8006c18 } else if (mode == USB_DEVICE_MODE) 8006be2: 78fb ldrb r3, [r7, #3] 8006be4: 2b00 cmp r3, #0 8006be6: d115 bne.n 8006c14 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 8006be8: 687b ldr r3, [r7, #4] 8006bea: 68db ldr r3, [r3, #12] 8006bec: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000 8006bf0: 687b ldr r3, [r7, #4] 8006bf2: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8006bf4: 200a movs r0, #10 8006bf6: f7fa fe2b bl 8001850 ms += 10U; 8006bfa: 68fb ldr r3, [r7, #12] 8006bfc: 330a adds r3, #10 8006bfe: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8006c00: 6878 ldr r0, [r7, #4] 8006c02: f001 f920 bl 8007e46 8006c06: 4603 mov r3, r0 8006c08: 2b00 cmp r3, #0 8006c0a: d005 beq.n 8006c18 8006c0c: 68fb ldr r3, [r7, #12] 8006c0e: 2bc7 cmp r3, #199 @ 0xc7 8006c10: d9f0 bls.n 8006bf4 8006c12: e001 b.n 8006c18 } else { return HAL_ERROR; 8006c14: 2301 movs r3, #1 8006c16: e005 b.n 8006c24 } if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) 8006c18: 68fb ldr r3, [r7, #12] 8006c1a: 2bc8 cmp r3, #200 @ 0xc8 8006c1c: d101 bne.n 8006c22 { return HAL_ERROR; 8006c1e: 2301 movs r3, #1 8006c20: e000 b.n 8006c24 } return HAL_OK; 8006c22: 2300 movs r3, #0 } 8006c24: 4618 mov r0, r3 8006c26: 3710 adds r7, #16 8006c28: 46bd mov sp, r7 8006c2a: bd80 pop {r7, pc} 08006c2c : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8006c2c: b084 sub sp, #16 8006c2e: b580 push {r7, lr} 8006c30: b086 sub sp, #24 8006c32: af00 add r7, sp, #0 8006c34: 6078 str r0, [r7, #4] 8006c36: f107 0024 add.w r0, r7, #36 @ 0x24 8006c3a: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 8006c3e: 2300 movs r3, #0 8006c40: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8006c42: 687b ldr r3, [r7, #4] 8006c44: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 8006c46: 2300 movs r3, #0 8006c48: 613b str r3, [r7, #16] 8006c4a: e009 b.n 8006c60 { USBx->DIEPTXF[i] = 0U; 8006c4c: 687a ldr r2, [r7, #4] 8006c4e: 693b ldr r3, [r7, #16] 8006c50: 3340 adds r3, #64 @ 0x40 8006c52: 009b lsls r3, r3, #2 8006c54: 4413 add r3, r2 8006c56: 2200 movs r2, #0 8006c58: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 8006c5a: 693b ldr r3, [r7, #16] 8006c5c: 3301 adds r3, #1 8006c5e: 613b str r3, [r7, #16] 8006c60: 693b ldr r3, [r7, #16] 8006c62: 2b0e cmp r3, #14 8006c64: d9f2 bls.n 8006c4c #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 8006c66: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8006c6a: 2b00 cmp r3, #0 8006c6c: d11c bne.n 8006ca8 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8006c6e: 68fb ldr r3, [r7, #12] 8006c70: f503 6300 add.w r3, r3, #2048 @ 0x800 8006c74: 685b ldr r3, [r3, #4] 8006c76: 68fa ldr r2, [r7, #12] 8006c78: f502 6200 add.w r2, r2, #2048 @ 0x800 8006c7c: f043 0302 orr.w r3, r3, #2 8006c80: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 8006c82: 687b ldr r3, [r7, #4] 8006c84: 6b9b ldr r3, [r3, #56] @ 0x38 8006c86: f423 1200 bic.w r2, r3, #2097152 @ 0x200000 8006c8a: 687b ldr r3, [r7, #4] 8006c8c: 639a str r2, [r3, #56] @ 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 8006c8e: 687b ldr r3, [r7, #4] 8006c90: 681b ldr r3, [r3, #0] 8006c92: f043 0240 orr.w r2, r3, #64 @ 0x40 8006c96: 687b ldr r3, [r7, #4] 8006c98: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 8006c9a: 687b ldr r3, [r7, #4] 8006c9c: 681b ldr r3, [r3, #0] 8006c9e: f043 0280 orr.w r2, r3, #128 @ 0x80 8006ca2: 687b ldr r3, [r7, #4] 8006ca4: 601a str r2, [r3, #0] 8006ca6: e005 b.n 8006cb4 } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 8006ca8: 687b ldr r3, [r7, #4] 8006caa: 6b9b ldr r3, [r3, #56] @ 0x38 8006cac: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 8006cb0: 687b ldr r3, [r7, #4] 8006cb2: 639a str r2, [r3, #56] @ 0x38 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 8006cb4: 68fb ldr r3, [r7, #12] 8006cb6: f503 6360 add.w r3, r3, #3584 @ 0xe00 8006cba: 461a mov r2, r3 8006cbc: 2300 movs r3, #0 8006cbe: 6013 str r3, [r2, #0] if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8006cc0: f897 3029 ldrb.w r3, [r7, #41] @ 0x29 8006cc4: 2b01 cmp r3, #1 8006cc6: d10d bne.n 8006ce4 { if (cfg.speed == USBD_HS_SPEED) 8006cc8: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8006ccc: 2b00 cmp r3, #0 8006cce: d104 bne.n 8006cda { /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); 8006cd0: 2100 movs r1, #0 8006cd2: 6878 ldr r0, [r7, #4] 8006cd4: f000 f968 bl 8006fa8 8006cd8: e008 b.n 8006cec } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); 8006cda: 2101 movs r1, #1 8006cdc: 6878 ldr r0, [r7, #4] 8006cde: f000 f963 bl 8006fa8 8006ce2: e003 b.n 8006cec } } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 8006ce4: 2103 movs r1, #3 8006ce6: 6878 ldr r0, [r7, #4] 8006ce8: f000 f95e bl 8006fa8 } /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 8006cec: 2110 movs r1, #16 8006cee: 6878 ldr r0, [r7, #4] 8006cf0: f000 f8fa bl 8006ee8 8006cf4: 4603 mov r3, r0 8006cf6: 2b00 cmp r3, #0 8006cf8: d001 beq.n 8006cfe { ret = HAL_ERROR; 8006cfa: 2301 movs r3, #1 8006cfc: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 8006cfe: 6878 ldr r0, [r7, #4] 8006d00: f000 f924 bl 8006f4c 8006d04: 4603 mov r3, r0 8006d06: 2b00 cmp r3, #0 8006d08: d001 beq.n 8006d0e { ret = HAL_ERROR; 8006d0a: 2301 movs r3, #1 8006d0c: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 8006d0e: 68fb ldr r3, [r7, #12] 8006d10: f503 6300 add.w r3, r3, #2048 @ 0x800 8006d14: 461a mov r2, r3 8006d16: 2300 movs r3, #0 8006d18: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 8006d1a: 68fb ldr r3, [r7, #12] 8006d1c: f503 6300 add.w r3, r3, #2048 @ 0x800 8006d20: 461a mov r2, r3 8006d22: 2300 movs r3, #0 8006d24: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 8006d26: 68fb ldr r3, [r7, #12] 8006d28: f503 6300 add.w r3, r3, #2048 @ 0x800 8006d2c: 461a mov r2, r3 8006d2e: 2300 movs r3, #0 8006d30: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 8006d32: 2300 movs r3, #0 8006d34: 613b str r3, [r7, #16] 8006d36: e043 b.n 8006dc0 { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8006d38: 693b ldr r3, [r7, #16] 8006d3a: 015a lsls r2, r3, #5 8006d3c: 68fb ldr r3, [r7, #12] 8006d3e: 4413 add r3, r2 8006d40: f503 6310 add.w r3, r3, #2304 @ 0x900 8006d44: 681b ldr r3, [r3, #0] 8006d46: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8006d4a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8006d4e: d118 bne.n 8006d82 { if (i == 0U) 8006d50: 693b ldr r3, [r7, #16] 8006d52: 2b00 cmp r3, #0 8006d54: d10a bne.n 8006d6c { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 8006d56: 693b ldr r3, [r7, #16] 8006d58: 015a lsls r2, r3, #5 8006d5a: 68fb ldr r3, [r7, #12] 8006d5c: 4413 add r3, r2 8006d5e: f503 6310 add.w r3, r3, #2304 @ 0x900 8006d62: 461a mov r2, r3 8006d64: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8006d68: 6013 str r3, [r2, #0] 8006d6a: e013 b.n 8006d94 } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 8006d6c: 693b ldr r3, [r7, #16] 8006d6e: 015a lsls r2, r3, #5 8006d70: 68fb ldr r3, [r7, #12] 8006d72: 4413 add r3, r2 8006d74: f503 6310 add.w r3, r3, #2304 @ 0x900 8006d78: 461a mov r2, r3 8006d7a: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 8006d7e: 6013 str r3, [r2, #0] 8006d80: e008 b.n 8006d94 } } else { USBx_INEP(i)->DIEPCTL = 0U; 8006d82: 693b ldr r3, [r7, #16] 8006d84: 015a lsls r2, r3, #5 8006d86: 68fb ldr r3, [r7, #12] 8006d88: 4413 add r3, r2 8006d8a: f503 6310 add.w r3, r3, #2304 @ 0x900 8006d8e: 461a mov r2, r3 8006d90: 2300 movs r3, #0 8006d92: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 8006d94: 693b ldr r3, [r7, #16] 8006d96: 015a lsls r2, r3, #5 8006d98: 68fb ldr r3, [r7, #12] 8006d9a: 4413 add r3, r2 8006d9c: f503 6310 add.w r3, r3, #2304 @ 0x900 8006da0: 461a mov r2, r3 8006da2: 2300 movs r3, #0 8006da4: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 8006da6: 693b ldr r3, [r7, #16] 8006da8: 015a lsls r2, r3, #5 8006daa: 68fb ldr r3, [r7, #12] 8006dac: 4413 add r3, r2 8006dae: f503 6310 add.w r3, r3, #2304 @ 0x900 8006db2: 461a mov r2, r3 8006db4: f64f 337f movw r3, #64383 @ 0xfb7f 8006db8: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8006dba: 693b ldr r3, [r7, #16] 8006dbc: 3301 adds r3, #1 8006dbe: 613b str r3, [r7, #16] 8006dc0: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8006dc4: 461a mov r2, r3 8006dc6: 693b ldr r3, [r7, #16] 8006dc8: 4293 cmp r3, r2 8006dca: d3b5 bcc.n 8006d38 } for (i = 0U; i < cfg.dev_endpoints; i++) 8006dcc: 2300 movs r3, #0 8006dce: 613b str r3, [r7, #16] 8006dd0: e043 b.n 8006e5a { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8006dd2: 693b ldr r3, [r7, #16] 8006dd4: 015a lsls r2, r3, #5 8006dd6: 68fb ldr r3, [r7, #12] 8006dd8: 4413 add r3, r2 8006dda: f503 6330 add.w r3, r3, #2816 @ 0xb00 8006dde: 681b ldr r3, [r3, #0] 8006de0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8006de4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8006de8: d118 bne.n 8006e1c { if (i == 0U) 8006dea: 693b ldr r3, [r7, #16] 8006dec: 2b00 cmp r3, #0 8006dee: d10a bne.n 8006e06 { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 8006df0: 693b ldr r3, [r7, #16] 8006df2: 015a lsls r2, r3, #5 8006df4: 68fb ldr r3, [r7, #12] 8006df6: 4413 add r3, r2 8006df8: f503 6330 add.w r3, r3, #2816 @ 0xb00 8006dfc: 461a mov r2, r3 8006dfe: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8006e02: 6013 str r3, [r2, #0] 8006e04: e013 b.n 8006e2e } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 8006e06: 693b ldr r3, [r7, #16] 8006e08: 015a lsls r2, r3, #5 8006e0a: 68fb ldr r3, [r7, #12] 8006e0c: 4413 add r3, r2 8006e0e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8006e12: 461a mov r2, r3 8006e14: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 8006e18: 6013 str r3, [r2, #0] 8006e1a: e008 b.n 8006e2e } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 8006e1c: 693b ldr r3, [r7, #16] 8006e1e: 015a lsls r2, r3, #5 8006e20: 68fb ldr r3, [r7, #12] 8006e22: 4413 add r3, r2 8006e24: f503 6330 add.w r3, r3, #2816 @ 0xb00 8006e28: 461a mov r2, r3 8006e2a: 2300 movs r3, #0 8006e2c: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 8006e2e: 693b ldr r3, [r7, #16] 8006e30: 015a lsls r2, r3, #5 8006e32: 68fb ldr r3, [r7, #12] 8006e34: 4413 add r3, r2 8006e36: f503 6330 add.w r3, r3, #2816 @ 0xb00 8006e3a: 461a mov r2, r3 8006e3c: 2300 movs r3, #0 8006e3e: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8006e40: 693b ldr r3, [r7, #16] 8006e42: 015a lsls r2, r3, #5 8006e44: 68fb ldr r3, [r7, #12] 8006e46: 4413 add r3, r2 8006e48: f503 6330 add.w r3, r3, #2816 @ 0xb00 8006e4c: 461a mov r2, r3 8006e4e: f64f 337f movw r3, #64383 @ 0xfb7f 8006e52: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8006e54: 693b ldr r3, [r7, #16] 8006e56: 3301 adds r3, #1 8006e58: 613b str r3, [r7, #16] 8006e5a: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8006e5e: 461a mov r2, r3 8006e60: 693b ldr r3, [r7, #16] 8006e62: 4293 cmp r3, r2 8006e64: d3b5 bcc.n 8006dd2 } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 8006e66: 68fb ldr r3, [r7, #12] 8006e68: f503 6300 add.w r3, r3, #2048 @ 0x800 8006e6c: 691b ldr r3, [r3, #16] 8006e6e: 68fa ldr r2, [r7, #12] 8006e70: f502 6200 add.w r2, r2, #2048 @ 0x800 8006e74: f423 7380 bic.w r3, r3, #256 @ 0x100 8006e78: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 8006e7a: 687b ldr r3, [r7, #4] 8006e7c: 2200 movs r2, #0 8006e7e: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 8006e80: 687b ldr r3, [r7, #4] 8006e82: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000 8006e86: 615a str r2, [r3, #20] /* Enable the common interrupts */ if (cfg.dma_enable == 0U) 8006e88: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8006e8c: 2b00 cmp r3, #0 8006e8e: d105 bne.n 8006e9c { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 8006e90: 687b ldr r3, [r7, #4] 8006e92: 699b ldr r3, [r3, #24] 8006e94: f043 0210 orr.w r2, r3, #16 8006e98: 687b ldr r3, [r7, #4] 8006e9a: 619a str r2, [r3, #24] } /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 8006e9c: 687b ldr r3, [r7, #4] 8006e9e: 699a ldr r2, [r3, #24] 8006ea0: 4b10 ldr r3, [pc, #64] @ (8006ee4 ) 8006ea2: 4313 orrs r3, r2 8006ea4: 687a ldr r2, [r7, #4] 8006ea6: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 8006ea8: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 8006eac: 2b00 cmp r3, #0 8006eae: d005 beq.n 8006ebc { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 8006eb0: 687b ldr r3, [r7, #4] 8006eb2: 699b ldr r3, [r3, #24] 8006eb4: f043 0208 orr.w r2, r3, #8 8006eb8: 687b ldr r3, [r7, #4] 8006eba: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 8006ebc: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8006ec0: 2b01 cmp r3, #1 8006ec2: d107 bne.n 8006ed4 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 8006ec4: 687b ldr r3, [r7, #4] 8006ec6: 699b ldr r3, [r3, #24] 8006ec8: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8006ecc: f043 0304 orr.w r3, r3, #4 8006ed0: 687a ldr r2, [r7, #4] 8006ed2: 6193 str r3, [r2, #24] } return ret; 8006ed4: 7dfb ldrb r3, [r7, #23] } 8006ed6: 4618 mov r0, r3 8006ed8: 3718 adds r7, #24 8006eda: 46bd mov sp, r7 8006edc: e8bd 4080 ldmia.w sp!, {r7, lr} 8006ee0: b004 add sp, #16 8006ee2: 4770 bx lr 8006ee4: 803c3800 .word 0x803c3800 08006ee8 : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 8006ee8: b480 push {r7} 8006eea: b085 sub sp, #20 8006eec: af00 add r7, sp, #0 8006eee: 6078 str r0, [r7, #4] 8006ef0: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8006ef2: 2300 movs r3, #0 8006ef4: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8006ef6: 68fb ldr r3, [r7, #12] 8006ef8: 3301 adds r3, #1 8006efa: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8006efc: 68fb ldr r3, [r7, #12] 8006efe: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8006f02: d901 bls.n 8006f08 { return HAL_TIMEOUT; 8006f04: 2303 movs r3, #3 8006f06: e01b b.n 8006f40 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8006f08: 687b ldr r3, [r7, #4] 8006f0a: 691b ldr r3, [r3, #16] 8006f0c: 2b00 cmp r3, #0 8006f0e: daf2 bge.n 8006ef6 /* Flush TX Fifo */ count = 0U; 8006f10: 2300 movs r3, #0 8006f12: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 8006f14: 683b ldr r3, [r7, #0] 8006f16: 019b lsls r3, r3, #6 8006f18: f043 0220 orr.w r2, r3, #32 8006f1c: 687b ldr r3, [r7, #4] 8006f1e: 611a str r2, [r3, #16] do { count++; 8006f20: 68fb ldr r3, [r7, #12] 8006f22: 3301 adds r3, #1 8006f24: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8006f26: 68fb ldr r3, [r7, #12] 8006f28: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8006f2c: d901 bls.n 8006f32 { return HAL_TIMEOUT; 8006f2e: 2303 movs r3, #3 8006f30: e006 b.n 8006f40 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 8006f32: 687b ldr r3, [r7, #4] 8006f34: 691b ldr r3, [r3, #16] 8006f36: f003 0320 and.w r3, r3, #32 8006f3a: 2b20 cmp r3, #32 8006f3c: d0f0 beq.n 8006f20 return HAL_OK; 8006f3e: 2300 movs r3, #0 } 8006f40: 4618 mov r0, r3 8006f42: 3714 adds r7, #20 8006f44: 46bd mov sp, r7 8006f46: f85d 7b04 ldr.w r7, [sp], #4 8006f4a: 4770 bx lr 08006f4c : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 8006f4c: b480 push {r7} 8006f4e: b085 sub sp, #20 8006f50: af00 add r7, sp, #0 8006f52: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8006f54: 2300 movs r3, #0 8006f56: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8006f58: 68fb ldr r3, [r7, #12] 8006f5a: 3301 adds r3, #1 8006f5c: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8006f5e: 68fb ldr r3, [r7, #12] 8006f60: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8006f64: d901 bls.n 8006f6a { return HAL_TIMEOUT; 8006f66: 2303 movs r3, #3 8006f68: e018 b.n 8006f9c } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8006f6a: 687b ldr r3, [r7, #4] 8006f6c: 691b ldr r3, [r3, #16] 8006f6e: 2b00 cmp r3, #0 8006f70: daf2 bge.n 8006f58 /* Flush RX Fifo */ count = 0U; 8006f72: 2300 movs r3, #0 8006f74: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 8006f76: 687b ldr r3, [r7, #4] 8006f78: 2210 movs r2, #16 8006f7a: 611a str r2, [r3, #16] do { count++; 8006f7c: 68fb ldr r3, [r7, #12] 8006f7e: 3301 adds r3, #1 8006f80: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8006f82: 68fb ldr r3, [r7, #12] 8006f84: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8006f88: d901 bls.n 8006f8e { return HAL_TIMEOUT; 8006f8a: 2303 movs r3, #3 8006f8c: e006 b.n 8006f9c } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 8006f8e: 687b ldr r3, [r7, #4] 8006f90: 691b ldr r3, [r3, #16] 8006f92: f003 0310 and.w r3, r3, #16 8006f96: 2b10 cmp r3, #16 8006f98: d0f0 beq.n 8006f7c return HAL_OK; 8006f9a: 2300 movs r3, #0 } 8006f9c: 4618 mov r0, r3 8006f9e: 3714 adds r7, #20 8006fa0: 46bd mov sp, r7 8006fa2: f85d 7b04 ldr.w r7, [sp], #4 8006fa6: 4770 bx lr 08006fa8 : * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 8006fa8: b480 push {r7} 8006faa: b085 sub sp, #20 8006fac: af00 add r7, sp, #0 8006fae: 6078 str r0, [r7, #4] 8006fb0: 460b mov r3, r1 8006fb2: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8006fb4: 687b ldr r3, [r7, #4] 8006fb6: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 8006fb8: 68fb ldr r3, [r7, #12] 8006fba: f503 6300 add.w r3, r3, #2048 @ 0x800 8006fbe: 681a ldr r2, [r3, #0] 8006fc0: 78fb ldrb r3, [r7, #3] 8006fc2: 68f9 ldr r1, [r7, #12] 8006fc4: f501 6100 add.w r1, r1, #2048 @ 0x800 8006fc8: 4313 orrs r3, r2 8006fca: 600b str r3, [r1, #0] return HAL_OK; 8006fcc: 2300 movs r3, #0 } 8006fce: 4618 mov r0, r3 8006fd0: 3714 adds r7, #20 8006fd2: 46bd mov sp, r7 8006fd4: f85d 7b04 ldr.w r7, [sp], #4 8006fd8: 4770 bx lr 08006fda : * This parameter can be one of these values: * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { 8006fda: b480 push {r7} 8006fdc: b087 sub sp, #28 8006fde: af00 add r7, sp, #0 8006fe0: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8006fe2: 687b ldr r3, [r7, #4] 8006fe4: 613b str r3, [r7, #16] uint8_t speed; uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; 8006fe6: 693b ldr r3, [r7, #16] 8006fe8: f503 6300 add.w r3, r3, #2048 @ 0x800 8006fec: 689b ldr r3, [r3, #8] 8006fee: f003 0306 and.w r3, r3, #6 8006ff2: 60fb str r3, [r7, #12] if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 8006ff4: 68fb ldr r3, [r7, #12] 8006ff6: 2b00 cmp r3, #0 8006ff8: d102 bne.n 8007000 { speed = USBD_HS_SPEED; 8006ffa: 2300 movs r3, #0 8006ffc: 75fb strb r3, [r7, #23] 8006ffe: e00a b.n 8007016 } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || 8007000: 68fb ldr r3, [r7, #12] 8007002: 2b02 cmp r3, #2 8007004: d002 beq.n 800700c 8007006: 68fb ldr r3, [r7, #12] 8007008: 2b06 cmp r3, #6 800700a: d102 bne.n 8007012 (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USBD_FS_SPEED; 800700c: 2302 movs r3, #2 800700e: 75fb strb r3, [r7, #23] 8007010: e001 b.n 8007016 } else { speed = 0xFU; 8007012: 230f movs r3, #15 8007014: 75fb strb r3, [r7, #23] } return speed; 8007016: 7dfb ldrb r3, [r7, #23] } 8007018: 4618 mov r0, r3 800701a: 371c adds r7, #28 800701c: 46bd mov sp, r7 800701e: f85d 7b04 ldr.w r7, [sp], #4 8007022: 4770 bx lr 08007024 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007024: b480 push {r7} 8007026: b085 sub sp, #20 8007028: af00 add r7, sp, #0 800702a: 6078 str r0, [r7, #4] 800702c: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800702e: 687b ldr r3, [r7, #4] 8007030: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007032: 683b ldr r3, [r7, #0] 8007034: 781b ldrb r3, [r3, #0] 8007036: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8007038: 683b ldr r3, [r7, #0] 800703a: 785b ldrb r3, [r3, #1] 800703c: 2b01 cmp r3, #1 800703e: d13a bne.n 80070b6 { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); 8007040: 68fb ldr r3, [r7, #12] 8007042: f503 6300 add.w r3, r3, #2048 @ 0x800 8007046: 69da ldr r2, [r3, #28] 8007048: 683b ldr r3, [r7, #0] 800704a: 781b ldrb r3, [r3, #0] 800704c: f003 030f and.w r3, r3, #15 8007050: 2101 movs r1, #1 8007052: fa01 f303 lsl.w r3, r1, r3 8007056: b29b uxth r3, r3 8007058: 68f9 ldr r1, [r7, #12] 800705a: f501 6100 add.w r1, r1, #2048 @ 0x800 800705e: 4313 orrs r3, r2 8007060: 61cb str r3, [r1, #28] if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) 8007062: 68bb ldr r3, [r7, #8] 8007064: 015a lsls r2, r3, #5 8007066: 68fb ldr r3, [r7, #12] 8007068: 4413 add r3, r2 800706a: f503 6310 add.w r3, r3, #2304 @ 0x900 800706e: 681b ldr r3, [r3, #0] 8007070: f403 4300 and.w r3, r3, #32768 @ 0x8000 8007074: 2b00 cmp r3, #0 8007076: d155 bne.n 8007124 { USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8007078: 68bb ldr r3, [r7, #8] 800707a: 015a lsls r2, r3, #5 800707c: 68fb ldr r3, [r7, #12] 800707e: 4413 add r3, r2 8007080: f503 6310 add.w r3, r3, #2304 @ 0x900 8007084: 681a ldr r2, [r3, #0] 8007086: 683b ldr r3, [r7, #0] 8007088: 689b ldr r3, [r3, #8] 800708a: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | (epnum << 22) | 800708e: 683b ldr r3, [r7, #0] 8007090: 791b ldrb r3, [r3, #4] 8007092: 049b lsls r3, r3, #18 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8007094: 4319 orrs r1, r3 ((uint32_t)ep->type << 18) | (epnum << 22) | 8007096: 68bb ldr r3, [r7, #8] 8007098: 059b lsls r3, r3, #22 800709a: 430b orrs r3, r1 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 800709c: 4313 orrs r3, r2 800709e: 68ba ldr r2, [r7, #8] 80070a0: 0151 lsls r1, r2, #5 80070a2: 68fa ldr r2, [r7, #12] 80070a4: 440a add r2, r1 80070a6: f502 6210 add.w r2, r2, #2304 @ 0x900 80070aa: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80070ae: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80070b2: 6013 str r3, [r2, #0] 80070b4: e036 b.n 8007124 USB_OTG_DIEPCTL_USBAEP; } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); 80070b6: 68fb ldr r3, [r7, #12] 80070b8: f503 6300 add.w r3, r3, #2048 @ 0x800 80070bc: 69da ldr r2, [r3, #28] 80070be: 683b ldr r3, [r7, #0] 80070c0: 781b ldrb r3, [r3, #0] 80070c2: f003 030f and.w r3, r3, #15 80070c6: 2101 movs r1, #1 80070c8: fa01 f303 lsl.w r3, r1, r3 80070cc: 041b lsls r3, r3, #16 80070ce: 68f9 ldr r1, [r7, #12] 80070d0: f501 6100 add.w r1, r1, #2048 @ 0x800 80070d4: 4313 orrs r3, r2 80070d6: 61cb str r3, [r1, #28] if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) 80070d8: 68bb ldr r3, [r7, #8] 80070da: 015a lsls r2, r3, #5 80070dc: 68fb ldr r3, [r7, #12] 80070de: 4413 add r3, r2 80070e0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80070e4: 681b ldr r3, [r3, #0] 80070e6: f403 4300 and.w r3, r3, #32768 @ 0x8000 80070ea: 2b00 cmp r3, #0 80070ec: d11a bne.n 8007124 { USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 80070ee: 68bb ldr r3, [r7, #8] 80070f0: 015a lsls r2, r3, #5 80070f2: 68fb ldr r3, [r7, #12] 80070f4: 4413 add r3, r2 80070f6: f503 6330 add.w r3, r3, #2816 @ 0xb00 80070fa: 681a ldr r2, [r3, #0] 80070fc: 683b ldr r3, [r7, #0] 80070fe: 689b ldr r3, [r3, #8] 8007100: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | 8007104: 683b ldr r3, [r7, #0] 8007106: 791b ldrb r3, [r3, #4] 8007108: 049b lsls r3, r3, #18 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 800710a: 430b orrs r3, r1 800710c: 4313 orrs r3, r2 800710e: 68ba ldr r2, [r7, #8] 8007110: 0151 lsls r1, r2, #5 8007112: 68fa ldr r2, [r7, #12] 8007114: 440a add r2, r1 8007116: f502 6230 add.w r2, r2, #2816 @ 0xb00 800711a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800711e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8007122: 6013 str r3, [r2, #0] USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; 8007124: 2300 movs r3, #0 } 8007126: 4618 mov r0, r3 8007128: 3714 adds r7, #20 800712a: 46bd mov sp, r7 800712c: f85d 7b04 ldr.w r7, [sp], #4 8007130: 4770 bx lr ... 08007134 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007134: b480 push {r7} 8007136: b085 sub sp, #20 8007138: af00 add r7, sp, #0 800713a: 6078 str r0, [r7, #4] 800713c: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800713e: 687b ldr r3, [r7, #4] 8007140: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007142: 683b ldr r3, [r7, #0] 8007144: 781b ldrb r3, [r3, #0] 8007146: 60bb str r3, [r7, #8] /* Read DEPCTLn register */ if (ep->is_in == 1U) 8007148: 683b ldr r3, [r7, #0] 800714a: 785b ldrb r3, [r3, #1] 800714c: 2b01 cmp r3, #1 800714e: d161 bne.n 8007214 { if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007150: 68bb ldr r3, [r7, #8] 8007152: 015a lsls r2, r3, #5 8007154: 68fb ldr r3, [r7, #12] 8007156: 4413 add r3, r2 8007158: f503 6310 add.w r3, r3, #2304 @ 0x900 800715c: 681b ldr r3, [r3, #0] 800715e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007162: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007166: d11f bne.n 80071a8 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 8007168: 68bb ldr r3, [r7, #8] 800716a: 015a lsls r2, r3, #5 800716c: 68fb ldr r3, [r7, #12] 800716e: 4413 add r3, r2 8007170: f503 6310 add.w r3, r3, #2304 @ 0x900 8007174: 681b ldr r3, [r3, #0] 8007176: 68ba ldr r2, [r7, #8] 8007178: 0151 lsls r1, r2, #5 800717a: 68fa ldr r2, [r7, #12] 800717c: 440a add r2, r1 800717e: f502 6210 add.w r2, r2, #2304 @ 0x900 8007182: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007186: 6013 str r3, [r2, #0] USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; 8007188: 68bb ldr r3, [r7, #8] 800718a: 015a lsls r2, r3, #5 800718c: 68fb ldr r3, [r7, #12] 800718e: 4413 add r3, r2 8007190: f503 6310 add.w r3, r3, #2304 @ 0x900 8007194: 681b ldr r3, [r3, #0] 8007196: 68ba ldr r2, [r7, #8] 8007198: 0151 lsls r1, r2, #5 800719a: 68fa ldr r2, [r7, #12] 800719c: 440a add r2, r1 800719e: f502 6210 add.w r2, r2, #2304 @ 0x900 80071a2: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80071a6: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 80071a8: 68fb ldr r3, [r7, #12] 80071aa: f503 6300 add.w r3, r3, #2048 @ 0x800 80071ae: 6bda ldr r2, [r3, #60] @ 0x3c 80071b0: 683b ldr r3, [r7, #0] 80071b2: 781b ldrb r3, [r3, #0] 80071b4: f003 030f and.w r3, r3, #15 80071b8: 2101 movs r1, #1 80071ba: fa01 f303 lsl.w r3, r1, r3 80071be: b29b uxth r3, r3 80071c0: 43db mvns r3, r3 80071c2: 68f9 ldr r1, [r7, #12] 80071c4: f501 6100 add.w r1, r1, #2048 @ 0x800 80071c8: 4013 ands r3, r2 80071ca: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 80071cc: 68fb ldr r3, [r7, #12] 80071ce: f503 6300 add.w r3, r3, #2048 @ 0x800 80071d2: 69da ldr r2, [r3, #28] 80071d4: 683b ldr r3, [r7, #0] 80071d6: 781b ldrb r3, [r3, #0] 80071d8: f003 030f and.w r3, r3, #15 80071dc: 2101 movs r1, #1 80071de: fa01 f303 lsl.w r3, r1, r3 80071e2: b29b uxth r3, r3 80071e4: 43db mvns r3, r3 80071e6: 68f9 ldr r1, [r7, #12] 80071e8: f501 6100 add.w r1, r1, #2048 @ 0x800 80071ec: 4013 ands r3, r2 80071ee: 61cb str r3, [r1, #28] USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | 80071f0: 68bb ldr r3, [r7, #8] 80071f2: 015a lsls r2, r3, #5 80071f4: 68fb ldr r3, [r7, #12] 80071f6: 4413 add r3, r2 80071f8: f503 6310 add.w r3, r3, #2304 @ 0x900 80071fc: 681a ldr r2, [r3, #0] 80071fe: 68bb ldr r3, [r7, #8] 8007200: 0159 lsls r1, r3, #5 8007202: 68fb ldr r3, [r7, #12] 8007204: 440b add r3, r1 8007206: f503 6310 add.w r3, r3, #2304 @ 0x900 800720a: 4619 mov r1, r3 800720c: 4b35 ldr r3, [pc, #212] @ (80072e4 ) 800720e: 4013 ands r3, r2 8007210: 600b str r3, [r1, #0] 8007212: e060 b.n 80072d6 USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_EPTYP); } else { if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007214: 68bb ldr r3, [r7, #8] 8007216: 015a lsls r2, r3, #5 8007218: 68fb ldr r3, [r7, #12] 800721a: 4413 add r3, r2 800721c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007220: 681b ldr r3, [r3, #0] 8007222: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007226: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800722a: d11f bne.n 800726c { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 800722c: 68bb ldr r3, [r7, #8] 800722e: 015a lsls r2, r3, #5 8007230: 68fb ldr r3, [r7, #12] 8007232: 4413 add r3, r2 8007234: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007238: 681b ldr r3, [r3, #0] 800723a: 68ba ldr r2, [r7, #8] 800723c: 0151 lsls r1, r2, #5 800723e: 68fa ldr r2, [r7, #12] 8007240: 440a add r2, r1 8007242: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007246: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800724a: 6013 str r3, [r2, #0] USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; 800724c: 68bb ldr r3, [r7, #8] 800724e: 015a lsls r2, r3, #5 8007250: 68fb ldr r3, [r7, #12] 8007252: 4413 add r3, r2 8007254: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007258: 681b ldr r3, [r3, #0] 800725a: 68ba ldr r2, [r7, #8] 800725c: 0151 lsls r1, r2, #5 800725e: 68fa ldr r2, [r7, #12] 8007260: 440a add r2, r1 8007262: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007266: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800726a: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 800726c: 68fb ldr r3, [r7, #12] 800726e: f503 6300 add.w r3, r3, #2048 @ 0x800 8007272: 6bda ldr r2, [r3, #60] @ 0x3c 8007274: 683b ldr r3, [r7, #0] 8007276: 781b ldrb r3, [r3, #0] 8007278: f003 030f and.w r3, r3, #15 800727c: 2101 movs r1, #1 800727e: fa01 f303 lsl.w r3, r1, r3 8007282: 041b lsls r3, r3, #16 8007284: 43db mvns r3, r3 8007286: 68f9 ldr r1, [r7, #12] 8007288: f501 6100 add.w r1, r1, #2048 @ 0x800 800728c: 4013 ands r3, r2 800728e: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 8007290: 68fb ldr r3, [r7, #12] 8007292: f503 6300 add.w r3, r3, #2048 @ 0x800 8007296: 69da ldr r2, [r3, #28] 8007298: 683b ldr r3, [r7, #0] 800729a: 781b ldrb r3, [r3, #0] 800729c: f003 030f and.w r3, r3, #15 80072a0: 2101 movs r1, #1 80072a2: fa01 f303 lsl.w r3, r1, r3 80072a6: 041b lsls r3, r3, #16 80072a8: 43db mvns r3, r3 80072aa: 68f9 ldr r1, [r7, #12] 80072ac: f501 6100 add.w r1, r1, #2048 @ 0x800 80072b0: 4013 ands r3, r2 80072b2: 61cb str r3, [r1, #28] USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | 80072b4: 68bb ldr r3, [r7, #8] 80072b6: 015a lsls r2, r3, #5 80072b8: 68fb ldr r3, [r7, #12] 80072ba: 4413 add r3, r2 80072bc: f503 6330 add.w r3, r3, #2816 @ 0xb00 80072c0: 681a ldr r2, [r3, #0] 80072c2: 68bb ldr r3, [r7, #8] 80072c4: 0159 lsls r1, r3, #5 80072c6: 68fb ldr r3, [r7, #12] 80072c8: 440b add r3, r1 80072ca: f503 6330 add.w r3, r3, #2816 @ 0xb00 80072ce: 4619 mov r1, r3 80072d0: 4b05 ldr r3, [pc, #20] @ (80072e8 ) 80072d2: 4013 ands r3, r2 80072d4: 600b str r3, [r1, #0] USB_OTG_DOEPCTL_MPSIZ | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_EPTYP); } return HAL_OK; 80072d6: 2300 movs r3, #0 } 80072d8: 4618 mov r0, r3 80072da: 3714 adds r7, #20 80072dc: 46bd mov sp, r7 80072de: f85d 7b04 ldr.w r7, [sp], #4 80072e2: 4770 bx lr 80072e4: ec337800 .word 0xec337800 80072e8: eff37800 .word 0xeff37800 080072ec : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 80072ec: b580 push {r7, lr} 80072ee: b08a sub sp, #40 @ 0x28 80072f0: af02 add r7, sp, #8 80072f2: 60f8 str r0, [r7, #12] 80072f4: 60b9 str r1, [r7, #8] 80072f6: 4613 mov r3, r2 80072f8: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 80072fa: 68fb ldr r3, [r7, #12] 80072fc: 61fb str r3, [r7, #28] uint32_t epnum = (uint32_t)ep->num; 80072fe: 68bb ldr r3, [r7, #8] 8007300: 781b ldrb r3, [r3, #0] 8007302: 61bb str r3, [r7, #24] uint16_t pktcnt; /* IN endpoint */ if (ep->is_in == 1U) 8007304: 68bb ldr r3, [r7, #8] 8007306: 785b ldrb r3, [r3, #1] 8007308: 2b01 cmp r3, #1 800730a: f040 817f bne.w 800760c { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 800730e: 68bb ldr r3, [r7, #8] 8007310: 691b ldr r3, [r3, #16] 8007312: 2b00 cmp r3, #0 8007314: d132 bne.n 800737c { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8007316: 69bb ldr r3, [r7, #24] 8007318: 015a lsls r2, r3, #5 800731a: 69fb ldr r3, [r7, #28] 800731c: 4413 add r3, r2 800731e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007322: 691b ldr r3, [r3, #16] 8007324: 69ba ldr r2, [r7, #24] 8007326: 0151 lsls r1, r2, #5 8007328: 69fa ldr r2, [r7, #28] 800732a: 440a add r2, r1 800732c: f502 6210 add.w r2, r2, #2304 @ 0x900 8007330: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007334: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8007338: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 800733a: 69bb ldr r3, [r7, #24] 800733c: 015a lsls r2, r3, #5 800733e: 69fb ldr r3, [r7, #28] 8007340: 4413 add r3, r2 8007342: f503 6310 add.w r3, r3, #2304 @ 0x900 8007346: 691b ldr r3, [r3, #16] 8007348: 69ba ldr r2, [r7, #24] 800734a: 0151 lsls r1, r2, #5 800734c: 69fa ldr r2, [r7, #28] 800734e: 440a add r2, r1 8007350: f502 6210 add.w r2, r2, #2304 @ 0x900 8007354: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007358: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 800735a: 69bb ldr r3, [r7, #24] 800735c: 015a lsls r2, r3, #5 800735e: 69fb ldr r3, [r7, #28] 8007360: 4413 add r3, r2 8007362: f503 6310 add.w r3, r3, #2304 @ 0x900 8007366: 691b ldr r3, [r3, #16] 8007368: 69ba ldr r2, [r7, #24] 800736a: 0151 lsls r1, r2, #5 800736c: 69fa ldr r2, [r7, #28] 800736e: 440a add r2, r1 8007370: f502 6210 add.w r2, r2, #2304 @ 0x900 8007374: 0cdb lsrs r3, r3, #19 8007376: 04db lsls r3, r3, #19 8007378: 6113 str r3, [r2, #16] 800737a: e097 b.n 80074ac /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 800737c: 69bb ldr r3, [r7, #24] 800737e: 015a lsls r2, r3, #5 8007380: 69fb ldr r3, [r7, #28] 8007382: 4413 add r3, r2 8007384: f503 6310 add.w r3, r3, #2304 @ 0x900 8007388: 691b ldr r3, [r3, #16] 800738a: 69ba ldr r2, [r7, #24] 800738c: 0151 lsls r1, r2, #5 800738e: 69fa ldr r2, [r7, #28] 8007390: 440a add r2, r1 8007392: f502 6210 add.w r2, r2, #2304 @ 0x900 8007396: 0cdb lsrs r3, r3, #19 8007398: 04db lsls r3, r3, #19 800739a: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 800739c: 69bb ldr r3, [r7, #24] 800739e: 015a lsls r2, r3, #5 80073a0: 69fb ldr r3, [r7, #28] 80073a2: 4413 add r3, r2 80073a4: f503 6310 add.w r3, r3, #2304 @ 0x900 80073a8: 691b ldr r3, [r3, #16] 80073aa: 69ba ldr r2, [r7, #24] 80073ac: 0151 lsls r1, r2, #5 80073ae: 69fa ldr r2, [r7, #28] 80073b0: 440a add r2, r1 80073b2: f502 6210 add.w r2, r2, #2304 @ 0x900 80073b6: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 80073ba: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 80073be: 6113 str r3, [r2, #16] if (epnum == 0U) 80073c0: 69bb ldr r3, [r7, #24] 80073c2: 2b00 cmp r3, #0 80073c4: d11a bne.n 80073fc { if (ep->xfer_len > ep->maxpacket) 80073c6: 68bb ldr r3, [r7, #8] 80073c8: 691a ldr r2, [r3, #16] 80073ca: 68bb ldr r3, [r7, #8] 80073cc: 689b ldr r3, [r3, #8] 80073ce: 429a cmp r2, r3 80073d0: d903 bls.n 80073da { ep->xfer_len = ep->maxpacket; 80073d2: 68bb ldr r3, [r7, #8] 80073d4: 689a ldr r2, [r3, #8] 80073d6: 68bb ldr r3, [r7, #8] 80073d8: 611a str r2, [r3, #16] } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 80073da: 69bb ldr r3, [r7, #24] 80073dc: 015a lsls r2, r3, #5 80073de: 69fb ldr r3, [r7, #28] 80073e0: 4413 add r3, r2 80073e2: f503 6310 add.w r3, r3, #2304 @ 0x900 80073e6: 691b ldr r3, [r3, #16] 80073e8: 69ba ldr r2, [r7, #24] 80073ea: 0151 lsls r1, r2, #5 80073ec: 69fa ldr r2, [r7, #28] 80073ee: 440a add r2, r1 80073f0: f502 6210 add.w r2, r2, #2304 @ 0x900 80073f4: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80073f8: 6113 str r3, [r2, #16] 80073fa: e044 b.n 8007486 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 80073fc: 68bb ldr r3, [r7, #8] 80073fe: 691a ldr r2, [r3, #16] 8007400: 68bb ldr r3, [r7, #8] 8007402: 689b ldr r3, [r3, #8] 8007404: 4413 add r3, r2 8007406: 1e5a subs r2, r3, #1 8007408: 68bb ldr r3, [r7, #8] 800740a: 689b ldr r3, [r3, #8] 800740c: fbb2 f3f3 udiv r3, r2, r3 8007410: 82fb strh r3, [r7, #22] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); 8007412: 69bb ldr r3, [r7, #24] 8007414: 015a lsls r2, r3, #5 8007416: 69fb ldr r3, [r7, #28] 8007418: 4413 add r3, r2 800741a: f503 6310 add.w r3, r3, #2304 @ 0x900 800741e: 691a ldr r2, [r3, #16] 8007420: 8afb ldrh r3, [r7, #22] 8007422: 04d9 lsls r1, r3, #19 8007424: 4ba4 ldr r3, [pc, #656] @ (80076b8 ) 8007426: 400b ands r3, r1 8007428: 69b9 ldr r1, [r7, #24] 800742a: 0148 lsls r0, r1, #5 800742c: 69f9 ldr r1, [r7, #28] 800742e: 4401 add r1, r0 8007430: f501 6110 add.w r1, r1, #2304 @ 0x900 8007434: 4313 orrs r3, r2 8007436: 610b str r3, [r1, #16] if (ep->type == EP_TYPE_ISOC) 8007438: 68bb ldr r3, [r7, #8] 800743a: 791b ldrb r3, [r3, #4] 800743c: 2b01 cmp r3, #1 800743e: d122 bne.n 8007486 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 8007440: 69bb ldr r3, [r7, #24] 8007442: 015a lsls r2, r3, #5 8007444: 69fb ldr r3, [r7, #28] 8007446: 4413 add r3, r2 8007448: f503 6310 add.w r3, r3, #2304 @ 0x900 800744c: 691b ldr r3, [r3, #16] 800744e: 69ba ldr r2, [r7, #24] 8007450: 0151 lsls r1, r2, #5 8007452: 69fa ldr r2, [r7, #28] 8007454: 440a add r2, r1 8007456: f502 6210 add.w r2, r2, #2304 @ 0x900 800745a: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000 800745e: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); 8007460: 69bb ldr r3, [r7, #24] 8007462: 015a lsls r2, r3, #5 8007464: 69fb ldr r3, [r7, #28] 8007466: 4413 add r3, r2 8007468: f503 6310 add.w r3, r3, #2304 @ 0x900 800746c: 691a ldr r2, [r3, #16] 800746e: 8afb ldrh r3, [r7, #22] 8007470: 075b lsls r3, r3, #29 8007472: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000 8007476: 69b9 ldr r1, [r7, #24] 8007478: 0148 lsls r0, r1, #5 800747a: 69f9 ldr r1, [r7, #28] 800747c: 4401 add r1, r0 800747e: f501 6110 add.w r1, r1, #2304 @ 0x900 8007482: 4313 orrs r3, r2 8007484: 610b str r3, [r1, #16] } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 8007486: 69bb ldr r3, [r7, #24] 8007488: 015a lsls r2, r3, #5 800748a: 69fb ldr r3, [r7, #28] 800748c: 4413 add r3, r2 800748e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007492: 691a ldr r2, [r3, #16] 8007494: 68bb ldr r3, [r7, #8] 8007496: 691b ldr r3, [r3, #16] 8007498: f3c3 0312 ubfx r3, r3, #0, #19 800749c: 69b9 ldr r1, [r7, #24] 800749e: 0148 lsls r0, r1, #5 80074a0: 69f9 ldr r1, [r7, #28] 80074a2: 4401 add r1, r0 80074a4: f501 6110 add.w r1, r1, #2304 @ 0x900 80074a8: 4313 orrs r3, r2 80074aa: 610b str r3, [r1, #16] } if (dma == 1U) 80074ac: 79fb ldrb r3, [r7, #7] 80074ae: 2b01 cmp r3, #1 80074b0: d14b bne.n 800754a { if ((uint32_t)ep->dma_addr != 0U) 80074b2: 68bb ldr r3, [r7, #8] 80074b4: 69db ldr r3, [r3, #28] 80074b6: 2b00 cmp r3, #0 80074b8: d009 beq.n 80074ce { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 80074ba: 69bb ldr r3, [r7, #24] 80074bc: 015a lsls r2, r3, #5 80074be: 69fb ldr r3, [r7, #28] 80074c0: 4413 add r3, r2 80074c2: f503 6310 add.w r3, r3, #2304 @ 0x900 80074c6: 461a mov r2, r3 80074c8: 68bb ldr r3, [r7, #8] 80074ca: 69db ldr r3, [r3, #28] 80074cc: 6153 str r3, [r2, #20] } if (ep->type == EP_TYPE_ISOC) 80074ce: 68bb ldr r3, [r7, #8] 80074d0: 791b ldrb r3, [r3, #4] 80074d2: 2b01 cmp r3, #1 80074d4: d128 bne.n 8007528 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 80074d6: 69fb ldr r3, [r7, #28] 80074d8: f503 6300 add.w r3, r3, #2048 @ 0x800 80074dc: 689b ldr r3, [r3, #8] 80074de: f403 7380 and.w r3, r3, #256 @ 0x100 80074e2: 2b00 cmp r3, #0 80074e4: d110 bne.n 8007508 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 80074e6: 69bb ldr r3, [r7, #24] 80074e8: 015a lsls r2, r3, #5 80074ea: 69fb ldr r3, [r7, #28] 80074ec: 4413 add r3, r2 80074ee: f503 6310 add.w r3, r3, #2304 @ 0x900 80074f2: 681b ldr r3, [r3, #0] 80074f4: 69ba ldr r2, [r7, #24] 80074f6: 0151 lsls r1, r2, #5 80074f8: 69fa ldr r2, [r7, #28] 80074fa: 440a add r2, r1 80074fc: f502 6210 add.w r2, r2, #2304 @ 0x900 8007500: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007504: 6013 str r3, [r2, #0] 8007506: e00f b.n 8007528 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8007508: 69bb ldr r3, [r7, #24] 800750a: 015a lsls r2, r3, #5 800750c: 69fb ldr r3, [r7, #28] 800750e: 4413 add r3, r2 8007510: f503 6310 add.w r3, r3, #2304 @ 0x900 8007514: 681b ldr r3, [r3, #0] 8007516: 69ba ldr r2, [r7, #24] 8007518: 0151 lsls r1, r2, #5 800751a: 69fa ldr r2, [r7, #28] 800751c: 440a add r2, r1 800751e: f502 6210 add.w r2, r2, #2304 @ 0x900 8007522: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007526: 6013 str r3, [r2, #0] } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8007528: 69bb ldr r3, [r7, #24] 800752a: 015a lsls r2, r3, #5 800752c: 69fb ldr r3, [r7, #28] 800752e: 4413 add r3, r2 8007530: f503 6310 add.w r3, r3, #2304 @ 0x900 8007534: 681b ldr r3, [r3, #0] 8007536: 69ba ldr r2, [r7, #24] 8007538: 0151 lsls r1, r2, #5 800753a: 69fa ldr r2, [r7, #28] 800753c: 440a add r2, r1 800753e: f502 6210 add.w r2, r2, #2304 @ 0x900 8007542: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007546: 6013 str r3, [r2, #0] 8007548: e166 b.n 8007818 } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 800754a: 69bb ldr r3, [r7, #24] 800754c: 015a lsls r2, r3, #5 800754e: 69fb ldr r3, [r7, #28] 8007550: 4413 add r3, r2 8007552: f503 6310 add.w r3, r3, #2304 @ 0x900 8007556: 681b ldr r3, [r3, #0] 8007558: 69ba ldr r2, [r7, #24] 800755a: 0151 lsls r1, r2, #5 800755c: 69fa ldr r2, [r7, #28] 800755e: 440a add r2, r1 8007560: f502 6210 add.w r2, r2, #2304 @ 0x900 8007564: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007568: 6013 str r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 800756a: 68bb ldr r3, [r7, #8] 800756c: 791b ldrb r3, [r3, #4] 800756e: 2b01 cmp r3, #1 8007570: d015 beq.n 800759e { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 8007572: 68bb ldr r3, [r7, #8] 8007574: 691b ldr r3, [r3, #16] 8007576: 2b00 cmp r3, #0 8007578: f000 814e beq.w 8007818 { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 800757c: 69fb ldr r3, [r7, #28] 800757e: f503 6300 add.w r3, r3, #2048 @ 0x800 8007582: 6b5a ldr r2, [r3, #52] @ 0x34 8007584: 68bb ldr r3, [r7, #8] 8007586: 781b ldrb r3, [r3, #0] 8007588: f003 030f and.w r3, r3, #15 800758c: 2101 movs r1, #1 800758e: fa01 f303 lsl.w r3, r1, r3 8007592: 69f9 ldr r1, [r7, #28] 8007594: f501 6100 add.w r1, r1, #2048 @ 0x800 8007598: 4313 orrs r3, r2 800759a: 634b str r3, [r1, #52] @ 0x34 800759c: e13c b.n 8007818 } } else { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 800759e: 69fb ldr r3, [r7, #28] 80075a0: f503 6300 add.w r3, r3, #2048 @ 0x800 80075a4: 689b ldr r3, [r3, #8] 80075a6: f403 7380 and.w r3, r3, #256 @ 0x100 80075aa: 2b00 cmp r3, #0 80075ac: d110 bne.n 80075d0 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 80075ae: 69bb ldr r3, [r7, #24] 80075b0: 015a lsls r2, r3, #5 80075b2: 69fb ldr r3, [r7, #28] 80075b4: 4413 add r3, r2 80075b6: f503 6310 add.w r3, r3, #2304 @ 0x900 80075ba: 681b ldr r3, [r3, #0] 80075bc: 69ba ldr r2, [r7, #24] 80075be: 0151 lsls r1, r2, #5 80075c0: 69fa ldr r2, [r7, #28] 80075c2: 440a add r2, r1 80075c4: f502 6210 add.w r2, r2, #2304 @ 0x900 80075c8: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 80075cc: 6013 str r3, [r2, #0] 80075ce: e00f b.n 80075f0 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 80075d0: 69bb ldr r3, [r7, #24] 80075d2: 015a lsls r2, r3, #5 80075d4: 69fb ldr r3, [r7, #28] 80075d6: 4413 add r3, r2 80075d8: f503 6310 add.w r3, r3, #2304 @ 0x900 80075dc: 681b ldr r3, [r3, #0] 80075de: 69ba ldr r2, [r7, #24] 80075e0: 0151 lsls r1, r2, #5 80075e2: 69fa ldr r2, [r7, #28] 80075e4: 440a add r2, r1 80075e6: f502 6210 add.w r2, r2, #2304 @ 0x900 80075ea: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80075ee: 6013 str r3, [r2, #0] } (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); 80075f0: 68bb ldr r3, [r7, #8] 80075f2: 68d9 ldr r1, [r3, #12] 80075f4: 68bb ldr r3, [r7, #8] 80075f6: 781a ldrb r2, [r3, #0] 80075f8: 68bb ldr r3, [r7, #8] 80075fa: 691b ldr r3, [r3, #16] 80075fc: b298 uxth r0, r3 80075fe: 79fb ldrb r3, [r7, #7] 8007600: 9300 str r3, [sp, #0] 8007602: 4603 mov r3, r0 8007604: 68f8 ldr r0, [r7, #12] 8007606: f000 f9b9 bl 800797c 800760a: e105 b.n 8007818 { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 800760c: 69bb ldr r3, [r7, #24] 800760e: 015a lsls r2, r3, #5 8007610: 69fb ldr r3, [r7, #28] 8007612: 4413 add r3, r2 8007614: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007618: 691b ldr r3, [r3, #16] 800761a: 69ba ldr r2, [r7, #24] 800761c: 0151 lsls r1, r2, #5 800761e: 69fa ldr r2, [r7, #28] 8007620: 440a add r2, r1 8007622: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007626: 0cdb lsrs r3, r3, #19 8007628: 04db lsls r3, r3, #19 800762a: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 800762c: 69bb ldr r3, [r7, #24] 800762e: 015a lsls r2, r3, #5 8007630: 69fb ldr r3, [r7, #28] 8007632: 4413 add r3, r2 8007634: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007638: 691b ldr r3, [r3, #16] 800763a: 69ba ldr r2, [r7, #24] 800763c: 0151 lsls r1, r2, #5 800763e: 69fa ldr r2, [r7, #28] 8007640: 440a add r2, r1 8007642: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007646: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 800764a: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 800764e: 6113 str r3, [r2, #16] if (epnum == 0U) 8007650: 69bb ldr r3, [r7, #24] 8007652: 2b00 cmp r3, #0 8007654: d132 bne.n 80076bc { if (ep->xfer_len > 0U) 8007656: 68bb ldr r3, [r7, #8] 8007658: 691b ldr r3, [r3, #16] 800765a: 2b00 cmp r3, #0 800765c: d003 beq.n 8007666 { ep->xfer_len = ep->maxpacket; 800765e: 68bb ldr r3, [r7, #8] 8007660: 689a ldr r2, [r3, #8] 8007662: 68bb ldr r3, [r7, #8] 8007664: 611a str r2, [r3, #16] } /* Store transfer size, for EP0 this is equal to endpoint max packet size */ ep->xfer_size = ep->maxpacket; 8007666: 68bb ldr r3, [r7, #8] 8007668: 689a ldr r2, [r3, #8] 800766a: 68bb ldr r3, [r7, #8] 800766c: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); 800766e: 69bb ldr r3, [r7, #24] 8007670: 015a lsls r2, r3, #5 8007672: 69fb ldr r3, [r7, #28] 8007674: 4413 add r3, r2 8007676: f503 6330 add.w r3, r3, #2816 @ 0xb00 800767a: 691a ldr r2, [r3, #16] 800767c: 68bb ldr r3, [r7, #8] 800767e: 6a1b ldr r3, [r3, #32] 8007680: f3c3 0312 ubfx r3, r3, #0, #19 8007684: 69b9 ldr r1, [r7, #24] 8007686: 0148 lsls r0, r1, #5 8007688: 69f9 ldr r1, [r7, #28] 800768a: 4401 add r1, r0 800768c: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007690: 4313 orrs r3, r2 8007692: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8007694: 69bb ldr r3, [r7, #24] 8007696: 015a lsls r2, r3, #5 8007698: 69fb ldr r3, [r7, #28] 800769a: 4413 add r3, r2 800769c: f503 6330 add.w r3, r3, #2816 @ 0xb00 80076a0: 691b ldr r3, [r3, #16] 80076a2: 69ba ldr r2, [r7, #24] 80076a4: 0151 lsls r1, r2, #5 80076a6: 69fa ldr r2, [r7, #28] 80076a8: 440a add r2, r1 80076aa: f502 6230 add.w r2, r2, #2816 @ 0xb00 80076ae: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80076b2: 6113 str r3, [r2, #16] 80076b4: e062 b.n 800777c 80076b6: bf00 nop 80076b8: 1ff80000 .word 0x1ff80000 } else { if (ep->xfer_len == 0U) 80076bc: 68bb ldr r3, [r7, #8] 80076be: 691b ldr r3, [r3, #16] 80076c0: 2b00 cmp r3, #0 80076c2: d123 bne.n 800770c { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 80076c4: 69bb ldr r3, [r7, #24] 80076c6: 015a lsls r2, r3, #5 80076c8: 69fb ldr r3, [r7, #28] 80076ca: 4413 add r3, r2 80076cc: f503 6330 add.w r3, r3, #2816 @ 0xb00 80076d0: 691a ldr r2, [r3, #16] 80076d2: 68bb ldr r3, [r7, #8] 80076d4: 689b ldr r3, [r3, #8] 80076d6: f3c3 0312 ubfx r3, r3, #0, #19 80076da: 69b9 ldr r1, [r7, #24] 80076dc: 0148 lsls r0, r1, #5 80076de: 69f9 ldr r1, [r7, #28] 80076e0: 4401 add r1, r0 80076e2: f501 6130 add.w r1, r1, #2816 @ 0xb00 80076e6: 4313 orrs r3, r2 80076e8: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 80076ea: 69bb ldr r3, [r7, #24] 80076ec: 015a lsls r2, r3, #5 80076ee: 69fb ldr r3, [r7, #28] 80076f0: 4413 add r3, r2 80076f2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80076f6: 691b ldr r3, [r3, #16] 80076f8: 69ba ldr r2, [r7, #24] 80076fa: 0151 lsls r1, r2, #5 80076fc: 69fa ldr r2, [r7, #28] 80076fe: 440a add r2, r1 8007700: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007704: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007708: 6113 str r3, [r2, #16] 800770a: e037 b.n 800777c } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 800770c: 68bb ldr r3, [r7, #8] 800770e: 691a ldr r2, [r3, #16] 8007710: 68bb ldr r3, [r7, #8] 8007712: 689b ldr r3, [r3, #8] 8007714: 4413 add r3, r2 8007716: 1e5a subs r2, r3, #1 8007718: 68bb ldr r3, [r7, #8] 800771a: 689b ldr r3, [r3, #8] 800771c: fbb2 f3f3 udiv r3, r2, r3 8007720: 82fb strh r3, [r7, #22] ep->xfer_size = ep->maxpacket * pktcnt; 8007722: 68bb ldr r3, [r7, #8] 8007724: 689b ldr r3, [r3, #8] 8007726: 8afa ldrh r2, [r7, #22] 8007728: fb03 f202 mul.w r2, r3, r2 800772c: 68bb ldr r3, [r7, #8] 800772e: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); 8007730: 69bb ldr r3, [r7, #24] 8007732: 015a lsls r2, r3, #5 8007734: 69fb ldr r3, [r7, #28] 8007736: 4413 add r3, r2 8007738: f503 6330 add.w r3, r3, #2816 @ 0xb00 800773c: 691a ldr r2, [r3, #16] 800773e: 8afb ldrh r3, [r7, #22] 8007740: 04d9 lsls r1, r3, #19 8007742: 4b38 ldr r3, [pc, #224] @ (8007824 ) 8007744: 400b ands r3, r1 8007746: 69b9 ldr r1, [r7, #24] 8007748: 0148 lsls r0, r1, #5 800774a: 69f9 ldr r1, [r7, #28] 800774c: 4401 add r1, r0 800774e: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007752: 4313 orrs r3, r2 8007754: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; 8007756: 69bb ldr r3, [r7, #24] 8007758: 015a lsls r2, r3, #5 800775a: 69fb ldr r3, [r7, #28] 800775c: 4413 add r3, r2 800775e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007762: 691a ldr r2, [r3, #16] 8007764: 68bb ldr r3, [r7, #8] 8007766: 6a1b ldr r3, [r3, #32] 8007768: f3c3 0312 ubfx r3, r3, #0, #19 800776c: 69b9 ldr r1, [r7, #24] 800776e: 0148 lsls r0, r1, #5 8007770: 69f9 ldr r1, [r7, #28] 8007772: 4401 add r1, r0 8007774: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007778: 4313 orrs r3, r2 800777a: 610b str r3, [r1, #16] } } if (dma == 1U) 800777c: 79fb ldrb r3, [r7, #7] 800777e: 2b01 cmp r3, #1 8007780: d10d bne.n 800779e { if ((uint32_t)ep->xfer_buff != 0U) 8007782: 68bb ldr r3, [r7, #8] 8007784: 68db ldr r3, [r3, #12] 8007786: 2b00 cmp r3, #0 8007788: d009 beq.n 800779e { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 800778a: 68bb ldr r3, [r7, #8] 800778c: 68d9 ldr r1, [r3, #12] 800778e: 69bb ldr r3, [r7, #24] 8007790: 015a lsls r2, r3, #5 8007792: 69fb ldr r3, [r7, #28] 8007794: 4413 add r3, r2 8007796: f503 6330 add.w r3, r3, #2816 @ 0xb00 800779a: 460a mov r2, r1 800779c: 615a str r2, [r3, #20] } } if (ep->type == EP_TYPE_ISOC) 800779e: 68bb ldr r3, [r7, #8] 80077a0: 791b ldrb r3, [r3, #4] 80077a2: 2b01 cmp r3, #1 80077a4: d128 bne.n 80077f8 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 80077a6: 69fb ldr r3, [r7, #28] 80077a8: f503 6300 add.w r3, r3, #2048 @ 0x800 80077ac: 689b ldr r3, [r3, #8] 80077ae: f403 7380 and.w r3, r3, #256 @ 0x100 80077b2: 2b00 cmp r3, #0 80077b4: d110 bne.n 80077d8 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 80077b6: 69bb ldr r3, [r7, #24] 80077b8: 015a lsls r2, r3, #5 80077ba: 69fb ldr r3, [r7, #28] 80077bc: 4413 add r3, r2 80077be: f503 6330 add.w r3, r3, #2816 @ 0xb00 80077c2: 681b ldr r3, [r3, #0] 80077c4: 69ba ldr r2, [r7, #24] 80077c6: 0151 lsls r1, r2, #5 80077c8: 69fa ldr r2, [r7, #28] 80077ca: 440a add r2, r1 80077cc: f502 6230 add.w r2, r2, #2816 @ 0xb00 80077d0: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 80077d4: 6013 str r3, [r2, #0] 80077d6: e00f b.n 80077f8 } else { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 80077d8: 69bb ldr r3, [r7, #24] 80077da: 015a lsls r2, r3, #5 80077dc: 69fb ldr r3, [r7, #28] 80077de: 4413 add r3, r2 80077e0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80077e4: 681b ldr r3, [r3, #0] 80077e6: 69ba ldr r2, [r7, #24] 80077e8: 0151 lsls r1, r2, #5 80077ea: 69fa ldr r2, [r7, #28] 80077ec: 440a add r2, r1 80077ee: f502 6230 add.w r2, r2, #2816 @ 0xb00 80077f2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80077f6: 6013 str r3, [r2, #0] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 80077f8: 69bb ldr r3, [r7, #24] 80077fa: 015a lsls r2, r3, #5 80077fc: 69fb ldr r3, [r7, #28] 80077fe: 4413 add r3, r2 8007800: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007804: 681b ldr r3, [r3, #0] 8007806: 69ba ldr r2, [r7, #24] 8007808: 0151 lsls r1, r2, #5 800780a: 69fa ldr r2, [r7, #28] 800780c: 440a add r2, r1 800780e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007812: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007816: 6013 str r3, [r2, #0] } return HAL_OK; 8007818: 2300 movs r3, #0 } 800781a: 4618 mov r0, r3 800781c: 3720 adds r7, #32 800781e: 46bd mov sp, r7 8007820: bd80 pop {r7, pc} 8007822: bf00 nop 8007824: 1ff80000 .word 0x1ff80000 08007828 : * @param USBx usb device instance * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8007828: b480 push {r7} 800782a: b087 sub sp, #28 800782c: af00 add r7, sp, #0 800782e: 6078 str r0, [r7, #4] 8007830: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8007832: 2300 movs r3, #0 8007834: 60fb str r3, [r7, #12] HAL_StatusTypeDef ret = HAL_OK; 8007836: 2300 movs r3, #0 8007838: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 800783a: 687b ldr r3, [r7, #4] 800783c: 613b str r3, [r7, #16] /* IN endpoint */ if (ep->is_in == 1U) 800783e: 683b ldr r3, [r7, #0] 8007840: 785b ldrb r3, [r3, #1] 8007842: 2b01 cmp r3, #1 8007844: d14a bne.n 80078dc { /* EP enable, IN data in FIFO */ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007846: 683b ldr r3, [r7, #0] 8007848: 781b ldrb r3, [r3, #0] 800784a: 015a lsls r2, r3, #5 800784c: 693b ldr r3, [r7, #16] 800784e: 4413 add r3, r2 8007850: f503 6310 add.w r3, r3, #2304 @ 0x900 8007854: 681b ldr r3, [r3, #0] 8007856: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800785a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800785e: f040 8086 bne.w 800796e { USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); 8007862: 683b ldr r3, [r7, #0] 8007864: 781b ldrb r3, [r3, #0] 8007866: 015a lsls r2, r3, #5 8007868: 693b ldr r3, [r7, #16] 800786a: 4413 add r3, r2 800786c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007870: 681b ldr r3, [r3, #0] 8007872: 683a ldr r2, [r7, #0] 8007874: 7812 ldrb r2, [r2, #0] 8007876: 0151 lsls r1, r2, #5 8007878: 693a ldr r2, [r7, #16] 800787a: 440a add r2, r1 800787c: f502 6210 add.w r2, r2, #2304 @ 0x900 8007880: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007884: 6013 str r3, [r2, #0] USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); 8007886: 683b ldr r3, [r7, #0] 8007888: 781b ldrb r3, [r3, #0] 800788a: 015a lsls r2, r3, #5 800788c: 693b ldr r3, [r7, #16] 800788e: 4413 add r3, r2 8007890: f503 6310 add.w r3, r3, #2304 @ 0x900 8007894: 681b ldr r3, [r3, #0] 8007896: 683a ldr r2, [r7, #0] 8007898: 7812 ldrb r2, [r2, #0] 800789a: 0151 lsls r1, r2, #5 800789c: 693a ldr r2, [r7, #16] 800789e: 440a add r2, r1 80078a0: f502 6210 add.w r2, r2, #2304 @ 0x900 80078a4: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80078a8: 6013 str r3, [r2, #0] do { count++; 80078aa: 68fb ldr r3, [r7, #12] 80078ac: 3301 adds r3, #1 80078ae: 60fb str r3, [r7, #12] if (count > 10000U) 80078b0: 68fb ldr r3, [r7, #12] 80078b2: f242 7210 movw r2, #10000 @ 0x2710 80078b6: 4293 cmp r3, r2 80078b8: d902 bls.n 80078c0 { ret = HAL_ERROR; 80078ba: 2301 movs r3, #1 80078bc: 75fb strb r3, [r7, #23] break; 80078be: e056 b.n 800796e } } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); 80078c0: 683b ldr r3, [r7, #0] 80078c2: 781b ldrb r3, [r3, #0] 80078c4: 015a lsls r2, r3, #5 80078c6: 693b ldr r3, [r7, #16] 80078c8: 4413 add r3, r2 80078ca: f503 6310 add.w r3, r3, #2304 @ 0x900 80078ce: 681b ldr r3, [r3, #0] 80078d0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80078d4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80078d8: d0e7 beq.n 80078aa 80078da: e048 b.n 800796e } } else /* OUT endpoint */ { if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80078dc: 683b ldr r3, [r7, #0] 80078de: 781b ldrb r3, [r3, #0] 80078e0: 015a lsls r2, r3, #5 80078e2: 693b ldr r3, [r7, #16] 80078e4: 4413 add r3, r2 80078e6: f503 6330 add.w r3, r3, #2816 @ 0xb00 80078ea: 681b ldr r3, [r3, #0] 80078ec: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80078f0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80078f4: d13b bne.n 800796e { USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); 80078f6: 683b ldr r3, [r7, #0] 80078f8: 781b ldrb r3, [r3, #0] 80078fa: 015a lsls r2, r3, #5 80078fc: 693b ldr r3, [r7, #16] 80078fe: 4413 add r3, r2 8007900: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007904: 681b ldr r3, [r3, #0] 8007906: 683a ldr r2, [r7, #0] 8007908: 7812 ldrb r2, [r2, #0] 800790a: 0151 lsls r1, r2, #5 800790c: 693a ldr r2, [r7, #16] 800790e: 440a add r2, r1 8007910: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007914: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007918: 6013 str r3, [r2, #0] USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); 800791a: 683b ldr r3, [r7, #0] 800791c: 781b ldrb r3, [r3, #0] 800791e: 015a lsls r2, r3, #5 8007920: 693b ldr r3, [r7, #16] 8007922: 4413 add r3, r2 8007924: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007928: 681b ldr r3, [r3, #0] 800792a: 683a ldr r2, [r7, #0] 800792c: 7812 ldrb r2, [r2, #0] 800792e: 0151 lsls r1, r2, #5 8007930: 693a ldr r2, [r7, #16] 8007932: 440a add r2, r1 8007934: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007938: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800793c: 6013 str r3, [r2, #0] do { count++; 800793e: 68fb ldr r3, [r7, #12] 8007940: 3301 adds r3, #1 8007942: 60fb str r3, [r7, #12] if (count > 10000U) 8007944: 68fb ldr r3, [r7, #12] 8007946: f242 7210 movw r2, #10000 @ 0x2710 800794a: 4293 cmp r3, r2 800794c: d902 bls.n 8007954 { ret = HAL_ERROR; 800794e: 2301 movs r3, #1 8007950: 75fb strb r3, [r7, #23] break; 8007952: e00c b.n 800796e } } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); 8007954: 683b ldr r3, [r7, #0] 8007956: 781b ldrb r3, [r3, #0] 8007958: 015a lsls r2, r3, #5 800795a: 693b ldr r3, [r7, #16] 800795c: 4413 add r3, r2 800795e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007962: 681b ldr r3, [r3, #0] 8007964: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007968: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800796c: d0e7 beq.n 800793e } } return ret; 800796e: 7dfb ldrb r3, [r7, #23] } 8007970: 4618 mov r0, r3 8007972: 371c adds r7, #28 8007974: 46bd mov sp, r7 8007976: f85d 7b04 ldr.w r7, [sp], #4 800797a: 4770 bx lr 0800797c : * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { 800797c: b480 push {r7} 800797e: b089 sub sp, #36 @ 0x24 8007980: af00 add r7, sp, #0 8007982: 60f8 str r0, [r7, #12] 8007984: 60b9 str r1, [r7, #8] 8007986: 4611 mov r1, r2 8007988: 461a mov r2, r3 800798a: 460b mov r3, r1 800798c: 71fb strb r3, [r7, #7] 800798e: 4613 mov r3, r2 8007990: 80bb strh r3, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007992: 68fb ldr r3, [r7, #12] 8007994: 617b str r3, [r7, #20] uint8_t *pSrc = src; 8007996: 68bb ldr r3, [r7, #8] 8007998: 61fb str r3, [r7, #28] uint32_t count32b; uint32_t i; if (dma == 0U) 800799a: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 800799e: 2b00 cmp r3, #0 80079a0: d123 bne.n 80079ea { count32b = ((uint32_t)len + 3U) / 4U; 80079a2: 88bb ldrh r3, [r7, #4] 80079a4: 3303 adds r3, #3 80079a6: 089b lsrs r3, r3, #2 80079a8: 613b str r3, [r7, #16] for (i = 0U; i < count32b; i++) 80079aa: 2300 movs r3, #0 80079ac: 61bb str r3, [r7, #24] 80079ae: e018 b.n 80079e2 { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); 80079b0: 79fb ldrb r3, [r7, #7] 80079b2: 031a lsls r2, r3, #12 80079b4: 697b ldr r3, [r7, #20] 80079b6: 4413 add r3, r2 80079b8: f503 5380 add.w r3, r3, #4096 @ 0x1000 80079bc: 461a mov r2, r3 80079be: 69fb ldr r3, [r7, #28] 80079c0: 681b ldr r3, [r3, #0] 80079c2: 6013 str r3, [r2, #0] pSrc++; 80079c4: 69fb ldr r3, [r7, #28] 80079c6: 3301 adds r3, #1 80079c8: 61fb str r3, [r7, #28] pSrc++; 80079ca: 69fb ldr r3, [r7, #28] 80079cc: 3301 adds r3, #1 80079ce: 61fb str r3, [r7, #28] pSrc++; 80079d0: 69fb ldr r3, [r7, #28] 80079d2: 3301 adds r3, #1 80079d4: 61fb str r3, [r7, #28] pSrc++; 80079d6: 69fb ldr r3, [r7, #28] 80079d8: 3301 adds r3, #1 80079da: 61fb str r3, [r7, #28] for (i = 0U; i < count32b; i++) 80079dc: 69bb ldr r3, [r7, #24] 80079de: 3301 adds r3, #1 80079e0: 61bb str r3, [r7, #24] 80079e2: 69ba ldr r2, [r7, #24] 80079e4: 693b ldr r3, [r7, #16] 80079e6: 429a cmp r2, r3 80079e8: d3e2 bcc.n 80079b0 } } return HAL_OK; 80079ea: 2300 movs r3, #0 } 80079ec: 4618 mov r0, r3 80079ee: 3724 adds r7, #36 @ 0x24 80079f0: 46bd mov sp, r7 80079f2: f85d 7b04 ldr.w r7, [sp], #4 80079f6: 4770 bx lr 080079f8 : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 80079f8: b480 push {r7} 80079fa: b08b sub sp, #44 @ 0x2c 80079fc: af00 add r7, sp, #0 80079fe: 60f8 str r0, [r7, #12] 8007a00: 60b9 str r1, [r7, #8] 8007a02: 4613 mov r3, r2 8007a04: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 8007a06: 68fb ldr r3, [r7, #12] 8007a08: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 8007a0a: 68bb ldr r3, [r7, #8] 8007a0c: 627b str r3, [r7, #36] @ 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 8007a0e: 88fb ldrh r3, [r7, #6] 8007a10: 089b lsrs r3, r3, #2 8007a12: b29b uxth r3, r3 8007a14: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 8007a16: 88fb ldrh r3, [r7, #6] 8007a18: f003 0303 and.w r3, r3, #3 8007a1c: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 8007a1e: 2300 movs r3, #0 8007a20: 623b str r3, [r7, #32] 8007a22: e014 b.n 8007a4e { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 8007a24: 69bb ldr r3, [r7, #24] 8007a26: f503 5380 add.w r3, r3, #4096 @ 0x1000 8007a2a: 681a ldr r2, [r3, #0] 8007a2c: 6a7b ldr r3, [r7, #36] @ 0x24 8007a2e: 601a str r2, [r3, #0] pDest++; 8007a30: 6a7b ldr r3, [r7, #36] @ 0x24 8007a32: 3301 adds r3, #1 8007a34: 627b str r3, [r7, #36] @ 0x24 pDest++; 8007a36: 6a7b ldr r3, [r7, #36] @ 0x24 8007a38: 3301 adds r3, #1 8007a3a: 627b str r3, [r7, #36] @ 0x24 pDest++; 8007a3c: 6a7b ldr r3, [r7, #36] @ 0x24 8007a3e: 3301 adds r3, #1 8007a40: 627b str r3, [r7, #36] @ 0x24 pDest++; 8007a42: 6a7b ldr r3, [r7, #36] @ 0x24 8007a44: 3301 adds r3, #1 8007a46: 627b str r3, [r7, #36] @ 0x24 for (i = 0U; i < count32b; i++) 8007a48: 6a3b ldr r3, [r7, #32] 8007a4a: 3301 adds r3, #1 8007a4c: 623b str r3, [r7, #32] 8007a4e: 6a3a ldr r2, [r7, #32] 8007a50: 697b ldr r3, [r7, #20] 8007a52: 429a cmp r2, r3 8007a54: d3e6 bcc.n 8007a24 } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 8007a56: 8bfb ldrh r3, [r7, #30] 8007a58: 2b00 cmp r3, #0 8007a5a: d01e beq.n 8007a9a { i = 0U; 8007a5c: 2300 movs r3, #0 8007a5e: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 8007a60: 69bb ldr r3, [r7, #24] 8007a62: f503 5380 add.w r3, r3, #4096 @ 0x1000 8007a66: 461a mov r2, r3 8007a68: f107 0310 add.w r3, r7, #16 8007a6c: 6812 ldr r2, [r2, #0] 8007a6e: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 8007a70: 693a ldr r2, [r7, #16] 8007a72: 6a3b ldr r3, [r7, #32] 8007a74: b2db uxtb r3, r3 8007a76: 00db lsls r3, r3, #3 8007a78: fa22 f303 lsr.w r3, r2, r3 8007a7c: b2da uxtb r2, r3 8007a7e: 6a7b ldr r3, [r7, #36] @ 0x24 8007a80: 701a strb r2, [r3, #0] i++; 8007a82: 6a3b ldr r3, [r7, #32] 8007a84: 3301 adds r3, #1 8007a86: 623b str r3, [r7, #32] pDest++; 8007a88: 6a7b ldr r3, [r7, #36] @ 0x24 8007a8a: 3301 adds r3, #1 8007a8c: 627b str r3, [r7, #36] @ 0x24 remaining_bytes--; 8007a8e: 8bfb ldrh r3, [r7, #30] 8007a90: 3b01 subs r3, #1 8007a92: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 8007a94: 8bfb ldrh r3, [r7, #30] 8007a96: 2b00 cmp r3, #0 8007a98: d1ea bne.n 8007a70 } return ((void *)pDest); 8007a9a: 6a7b ldr r3, [r7, #36] @ 0x24 } 8007a9c: 4618 mov r0, r3 8007a9e: 372c adds r7, #44 @ 0x2c 8007aa0: 46bd mov sp, r7 8007aa2: f85d 7b04 ldr.w r7, [sp], #4 8007aa6: 4770 bx lr 08007aa8 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007aa8: b480 push {r7} 8007aaa: b085 sub sp, #20 8007aac: af00 add r7, sp, #0 8007aae: 6078 str r0, [r7, #4] 8007ab0: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8007ab2: 687b ldr r3, [r7, #4] 8007ab4: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007ab6: 683b ldr r3, [r7, #0] 8007ab8: 781b ldrb r3, [r3, #0] 8007aba: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8007abc: 683b ldr r3, [r7, #0] 8007abe: 785b ldrb r3, [r3, #1] 8007ac0: 2b01 cmp r3, #1 8007ac2: d12c bne.n 8007b1e { if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) 8007ac4: 68bb ldr r3, [r7, #8] 8007ac6: 015a lsls r2, r3, #5 8007ac8: 68fb ldr r3, [r7, #12] 8007aca: 4413 add r3, r2 8007acc: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ad0: 681b ldr r3, [r3, #0] 8007ad2: 2b00 cmp r3, #0 8007ad4: db12 blt.n 8007afc 8007ad6: 68bb ldr r3, [r7, #8] 8007ad8: 2b00 cmp r3, #0 8007ada: d00f beq.n 8007afc { USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 8007adc: 68bb ldr r3, [r7, #8] 8007ade: 015a lsls r2, r3, #5 8007ae0: 68fb ldr r3, [r7, #12] 8007ae2: 4413 add r3, r2 8007ae4: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ae8: 681b ldr r3, [r3, #0] 8007aea: 68ba ldr r2, [r7, #8] 8007aec: 0151 lsls r1, r2, #5 8007aee: 68fa ldr r2, [r7, #12] 8007af0: 440a add r2, r1 8007af2: f502 6210 add.w r2, r2, #2304 @ 0x900 8007af6: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8007afa: 6013 str r3, [r2, #0] } USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 8007afc: 68bb ldr r3, [r7, #8] 8007afe: 015a lsls r2, r3, #5 8007b00: 68fb ldr r3, [r7, #12] 8007b02: 4413 add r3, r2 8007b04: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b08: 681b ldr r3, [r3, #0] 8007b0a: 68ba ldr r2, [r7, #8] 8007b0c: 0151 lsls r1, r2, #5 8007b0e: 68fa ldr r2, [r7, #12] 8007b10: 440a add r2, r1 8007b12: f502 6210 add.w r2, r2, #2304 @ 0x900 8007b16: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8007b1a: 6013 str r3, [r2, #0] 8007b1c: e02b b.n 8007b76 } else { if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) 8007b1e: 68bb ldr r3, [r7, #8] 8007b20: 015a lsls r2, r3, #5 8007b22: 68fb ldr r3, [r7, #12] 8007b24: 4413 add r3, r2 8007b26: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007b2a: 681b ldr r3, [r3, #0] 8007b2c: 2b00 cmp r3, #0 8007b2e: db12 blt.n 8007b56 8007b30: 68bb ldr r3, [r7, #8] 8007b32: 2b00 cmp r3, #0 8007b34: d00f beq.n 8007b56 { USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 8007b36: 68bb ldr r3, [r7, #8] 8007b38: 015a lsls r2, r3, #5 8007b3a: 68fb ldr r3, [r7, #12] 8007b3c: 4413 add r3, r2 8007b3e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007b42: 681b ldr r3, [r3, #0] 8007b44: 68ba ldr r2, [r7, #8] 8007b46: 0151 lsls r1, r2, #5 8007b48: 68fa ldr r2, [r7, #12] 8007b4a: 440a add r2, r1 8007b4c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007b50: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8007b54: 6013 str r3, [r2, #0] } USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 8007b56: 68bb ldr r3, [r7, #8] 8007b58: 015a lsls r2, r3, #5 8007b5a: 68fb ldr r3, [r7, #12] 8007b5c: 4413 add r3, r2 8007b5e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007b62: 681b ldr r3, [r3, #0] 8007b64: 68ba ldr r2, [r7, #8] 8007b66: 0151 lsls r1, r2, #5 8007b68: 68fa ldr r2, [r7, #12] 8007b6a: 440a add r2, r1 8007b6c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007b70: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8007b74: 6013 str r3, [r2, #0] } return HAL_OK; 8007b76: 2300 movs r3, #0 } 8007b78: 4618 mov r0, r3 8007b7a: 3714 adds r7, #20 8007b7c: 46bd mov sp, r7 8007b7e: f85d 7b04 ldr.w r7, [sp], #4 8007b82: 4770 bx lr 08007b84 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007b84: b480 push {r7} 8007b86: b085 sub sp, #20 8007b88: af00 add r7, sp, #0 8007b8a: 6078 str r0, [r7, #4] 8007b8c: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8007b8e: 687b ldr r3, [r7, #4] 8007b90: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007b92: 683b ldr r3, [r7, #0] 8007b94: 781b ldrb r3, [r3, #0] 8007b96: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8007b98: 683b ldr r3, [r7, #0] 8007b9a: 785b ldrb r3, [r3, #1] 8007b9c: 2b01 cmp r3, #1 8007b9e: d128 bne.n 8007bf2 { USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 8007ba0: 68bb ldr r3, [r7, #8] 8007ba2: 015a lsls r2, r3, #5 8007ba4: 68fb ldr r3, [r7, #12] 8007ba6: 4413 add r3, r2 8007ba8: f503 6310 add.w r3, r3, #2304 @ 0x900 8007bac: 681b ldr r3, [r3, #0] 8007bae: 68ba ldr r2, [r7, #8] 8007bb0: 0151 lsls r1, r2, #5 8007bb2: 68fa ldr r2, [r7, #12] 8007bb4: 440a add r2, r1 8007bb6: f502 6210 add.w r2, r2, #2304 @ 0x900 8007bba: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8007bbe: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8007bc0: 683b ldr r3, [r7, #0] 8007bc2: 791b ldrb r3, [r3, #4] 8007bc4: 2b03 cmp r3, #3 8007bc6: d003 beq.n 8007bd0 8007bc8: 683b ldr r3, [r7, #0] 8007bca: 791b ldrb r3, [r3, #4] 8007bcc: 2b02 cmp r3, #2 8007bce: d138 bne.n 8007c42 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8007bd0: 68bb ldr r3, [r7, #8] 8007bd2: 015a lsls r2, r3, #5 8007bd4: 68fb ldr r3, [r7, #12] 8007bd6: 4413 add r3, r2 8007bd8: f503 6310 add.w r3, r3, #2304 @ 0x900 8007bdc: 681b ldr r3, [r3, #0] 8007bde: 68ba ldr r2, [r7, #8] 8007be0: 0151 lsls r1, r2, #5 8007be2: 68fa ldr r2, [r7, #12] 8007be4: 440a add r2, r1 8007be6: f502 6210 add.w r2, r2, #2304 @ 0x900 8007bea: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007bee: 6013 str r3, [r2, #0] 8007bf0: e027 b.n 8007c42 } } else { USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 8007bf2: 68bb ldr r3, [r7, #8] 8007bf4: 015a lsls r2, r3, #5 8007bf6: 68fb ldr r3, [r7, #12] 8007bf8: 4413 add r3, r2 8007bfa: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007bfe: 681b ldr r3, [r3, #0] 8007c00: 68ba ldr r2, [r7, #8] 8007c02: 0151 lsls r1, r2, #5 8007c04: 68fa ldr r2, [r7, #12] 8007c06: 440a add r2, r1 8007c08: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007c0c: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8007c10: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8007c12: 683b ldr r3, [r7, #0] 8007c14: 791b ldrb r3, [r3, #4] 8007c16: 2b03 cmp r3, #3 8007c18: d003 beq.n 8007c22 8007c1a: 683b ldr r3, [r7, #0] 8007c1c: 791b ldrb r3, [r3, #4] 8007c1e: 2b02 cmp r3, #2 8007c20: d10f bne.n 8007c42 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8007c22: 68bb ldr r3, [r7, #8] 8007c24: 015a lsls r2, r3, #5 8007c26: 68fb ldr r3, [r7, #12] 8007c28: 4413 add r3, r2 8007c2a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007c2e: 681b ldr r3, [r3, #0] 8007c30: 68ba ldr r2, [r7, #8] 8007c32: 0151 lsls r1, r2, #5 8007c34: 68fa ldr r2, [r7, #12] 8007c36: 440a add r2, r1 8007c38: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007c3c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007c40: 6013 str r3, [r2, #0] } } return HAL_OK; 8007c42: 2300 movs r3, #0 } 8007c44: 4618 mov r0, r3 8007c46: 3714 adds r7, #20 8007c48: 46bd mov sp, r7 8007c4a: f85d 7b04 ldr.w r7, [sp], #4 8007c4e: 4770 bx lr 08007c50 : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { 8007c50: b480 push {r7} 8007c52: b085 sub sp, #20 8007c54: af00 add r7, sp, #0 8007c56: 6078 str r0, [r7, #4] 8007c58: 460b mov r3, r1 8007c5a: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8007c5c: 687b ldr r3, [r7, #4] 8007c5e: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); 8007c60: 68fb ldr r3, [r7, #12] 8007c62: f503 6300 add.w r3, r3, #2048 @ 0x800 8007c66: 681b ldr r3, [r3, #0] 8007c68: 68fa ldr r2, [r7, #12] 8007c6a: f502 6200 add.w r2, r2, #2048 @ 0x800 8007c6e: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 8007c72: 6013 str r3, [r2, #0] USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; 8007c74: 68fb ldr r3, [r7, #12] 8007c76: f503 6300 add.w r3, r3, #2048 @ 0x800 8007c7a: 681a ldr r2, [r3, #0] 8007c7c: 78fb ldrb r3, [r7, #3] 8007c7e: 011b lsls r3, r3, #4 8007c80: f403 63fe and.w r3, r3, #2032 @ 0x7f0 8007c84: 68f9 ldr r1, [r7, #12] 8007c86: f501 6100 add.w r1, r1, #2048 @ 0x800 8007c8a: 4313 orrs r3, r2 8007c8c: 600b str r3, [r1, #0] return HAL_OK; 8007c8e: 2300 movs r3, #0 } 8007c90: 4618 mov r0, r3 8007c92: 3714 adds r7, #20 8007c94: 46bd mov sp, r7 8007c96: f85d 7b04 ldr.w r7, [sp], #4 8007c9a: 4770 bx lr 08007c9c : * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { 8007c9c: b480 push {r7} 8007c9e: b085 sub sp, #20 8007ca0: af00 add r7, sp, #0 8007ca2: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007ca4: 687b ldr r3, [r7, #4] 8007ca6: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8007ca8: 68fb ldr r3, [r7, #12] 8007caa: f503 6360 add.w r3, r3, #3584 @ 0xe00 8007cae: 681b ldr r3, [r3, #0] 8007cb0: 68fa ldr r2, [r7, #12] 8007cb2: f502 6260 add.w r2, r2, #3584 @ 0xe00 8007cb6: f023 0303 bic.w r3, r3, #3 8007cba: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; 8007cbc: 68fb ldr r3, [r7, #12] 8007cbe: f503 6300 add.w r3, r3, #2048 @ 0x800 8007cc2: 685b ldr r3, [r3, #4] 8007cc4: 68fa ldr r2, [r7, #12] 8007cc6: f502 6200 add.w r2, r2, #2048 @ 0x800 8007cca: f023 0302 bic.w r3, r3, #2 8007cce: 6053 str r3, [r2, #4] return HAL_OK; 8007cd0: 2300 movs r3, #0 } 8007cd2: 4618 mov r0, r3 8007cd4: 3714 adds r7, #20 8007cd6: 46bd mov sp, r7 8007cd8: f85d 7b04 ldr.w r7, [sp], #4 8007cdc: 4770 bx lr 08007cde : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { 8007cde: b480 push {r7} 8007ce0: b085 sub sp, #20 8007ce2: af00 add r7, sp, #0 8007ce4: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007ce6: 687b ldr r3, [r7, #4] 8007ce8: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8007cea: 68fb ldr r3, [r7, #12] 8007cec: f503 6360 add.w r3, r3, #3584 @ 0xe00 8007cf0: 681b ldr r3, [r3, #0] 8007cf2: 68fa ldr r2, [r7, #12] 8007cf4: f502 6260 add.w r2, r2, #3584 @ 0xe00 8007cf8: f023 0303 bic.w r3, r3, #3 8007cfc: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8007cfe: 68fb ldr r3, [r7, #12] 8007d00: f503 6300 add.w r3, r3, #2048 @ 0x800 8007d04: 685b ldr r3, [r3, #4] 8007d06: 68fa ldr r2, [r7, #12] 8007d08: f502 6200 add.w r2, r2, #2048 @ 0x800 8007d0c: f043 0302 orr.w r3, r3, #2 8007d10: 6053 str r3, [r2, #4] return HAL_OK; 8007d12: 2300 movs r3, #0 } 8007d14: 4618 mov r0, r3 8007d16: 3714 adds r7, #20 8007d18: 46bd mov sp, r7 8007d1a: f85d 7b04 ldr.w r7, [sp], #4 8007d1e: 4770 bx lr 08007d20 : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { 8007d20: b480 push {r7} 8007d22: b085 sub sp, #20 8007d24: af00 add r7, sp, #0 8007d26: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 8007d28: 687b ldr r3, [r7, #4] 8007d2a: 695b ldr r3, [r3, #20] 8007d2c: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 8007d2e: 687b ldr r3, [r7, #4] 8007d30: 699b ldr r3, [r3, #24] 8007d32: 68fa ldr r2, [r7, #12] 8007d34: 4013 ands r3, r2 8007d36: 60fb str r3, [r7, #12] return tmpreg; 8007d38: 68fb ldr r3, [r7, #12] } 8007d3a: 4618 mov r0, r3 8007d3c: 3714 adds r7, #20 8007d3e: 46bd mov sp, r7 8007d40: f85d 7b04 ldr.w r7, [sp], #4 8007d44: 4770 bx lr 08007d46 : * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device * @retval USB Device OUT EP interrupt status */ uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 8007d46: b480 push {r7} 8007d48: b085 sub sp, #20 8007d4a: af00 add r7, sp, #0 8007d4c: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007d4e: 687b ldr r3, [r7, #4] 8007d50: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8007d52: 68fb ldr r3, [r7, #12] 8007d54: f503 6300 add.w r3, r3, #2048 @ 0x800 8007d58: 699b ldr r3, [r3, #24] 8007d5a: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 8007d5c: 68fb ldr r3, [r7, #12] 8007d5e: f503 6300 add.w r3, r3, #2048 @ 0x800 8007d62: 69db ldr r3, [r3, #28] 8007d64: 68ba ldr r2, [r7, #8] 8007d66: 4013 ands r3, r2 8007d68: 60bb str r3, [r7, #8] return ((tmpreg & 0xffff0000U) >> 16); 8007d6a: 68bb ldr r3, [r7, #8] 8007d6c: 0c1b lsrs r3, r3, #16 } 8007d6e: 4618 mov r0, r3 8007d70: 3714 adds r7, #20 8007d72: 46bd mov sp, r7 8007d74: f85d 7b04 ldr.w r7, [sp], #4 8007d78: 4770 bx lr 08007d7a : * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device * @retval USB Device IN EP interrupt status */ uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 8007d7a: b480 push {r7} 8007d7c: b085 sub sp, #20 8007d7e: af00 add r7, sp, #0 8007d80: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007d82: 687b ldr r3, [r7, #4] 8007d84: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8007d86: 68fb ldr r3, [r7, #12] 8007d88: f503 6300 add.w r3, r3, #2048 @ 0x800 8007d8c: 699b ldr r3, [r3, #24] 8007d8e: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 8007d90: 68fb ldr r3, [r7, #12] 8007d92: f503 6300 add.w r3, r3, #2048 @ 0x800 8007d96: 69db ldr r3, [r3, #28] 8007d98: 68ba ldr r2, [r7, #8] 8007d9a: 4013 ands r3, r2 8007d9c: 60bb str r3, [r7, #8] return ((tmpreg & 0xFFFFU)); 8007d9e: 68bb ldr r3, [r7, #8] 8007da0: b29b uxth r3, r3 } 8007da2: 4618 mov r0, r3 8007da4: 3714 adds r7, #20 8007da6: 46bd mov sp, r7 8007da8: f85d 7b04 ldr.w r7, [sp], #4 8007dac: 4770 bx lr 08007dae : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 8007dae: b480 push {r7} 8007db0: b085 sub sp, #20 8007db2: af00 add r7, sp, #0 8007db4: 6078 str r0, [r7, #4] 8007db6: 460b mov r3, r1 8007db8: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8007dba: 687b ldr r3, [r7, #4] 8007dbc: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; 8007dbe: 78fb ldrb r3, [r7, #3] 8007dc0: 015a lsls r2, r3, #5 8007dc2: 68fb ldr r3, [r7, #12] 8007dc4: 4413 add r3, r2 8007dc6: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007dca: 689b ldr r3, [r3, #8] 8007dcc: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DOEPMSK; 8007dce: 68fb ldr r3, [r7, #12] 8007dd0: f503 6300 add.w r3, r3, #2048 @ 0x800 8007dd4: 695b ldr r3, [r3, #20] 8007dd6: 68ba ldr r2, [r7, #8] 8007dd8: 4013 ands r3, r2 8007dda: 60bb str r3, [r7, #8] return tmpreg; 8007ddc: 68bb ldr r3, [r7, #8] } 8007dde: 4618 mov r0, r3 8007de0: 3714 adds r7, #20 8007de2: 46bd mov sp, r7 8007de4: f85d 7b04 ldr.w r7, [sp], #4 8007de8: 4770 bx lr 08007dea : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 8007dea: b480 push {r7} 8007dec: b087 sub sp, #28 8007dee: af00 add r7, sp, #0 8007df0: 6078 str r0, [r7, #4] 8007df2: 460b mov r3, r1 8007df4: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8007df6: 687b ldr r3, [r7, #4] 8007df8: 617b str r3, [r7, #20] uint32_t tmpreg; uint32_t msk; uint32_t emp; msk = USBx_DEVICE->DIEPMSK; 8007dfa: 697b ldr r3, [r7, #20] 8007dfc: f503 6300 add.w r3, r3, #2048 @ 0x800 8007e00: 691b ldr r3, [r3, #16] 8007e02: 613b str r3, [r7, #16] emp = USBx_DEVICE->DIEPEMPMSK; 8007e04: 697b ldr r3, [r7, #20] 8007e06: f503 6300 add.w r3, r3, #2048 @ 0x800 8007e0a: 6b5b ldr r3, [r3, #52] @ 0x34 8007e0c: 60fb str r3, [r7, #12] msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; 8007e0e: 78fb ldrb r3, [r7, #3] 8007e10: f003 030f and.w r3, r3, #15 8007e14: 68fa ldr r2, [r7, #12] 8007e16: fa22 f303 lsr.w r3, r2, r3 8007e1a: 01db lsls r3, r3, #7 8007e1c: b2db uxtb r3, r3 8007e1e: 693a ldr r2, [r7, #16] 8007e20: 4313 orrs r3, r2 8007e22: 613b str r3, [r7, #16] tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; 8007e24: 78fb ldrb r3, [r7, #3] 8007e26: 015a lsls r2, r3, #5 8007e28: 697b ldr r3, [r7, #20] 8007e2a: 4413 add r3, r2 8007e2c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007e30: 689b ldr r3, [r3, #8] 8007e32: 693a ldr r2, [r7, #16] 8007e34: 4013 ands r3, r2 8007e36: 60bb str r3, [r7, #8] return tmpreg; 8007e38: 68bb ldr r3, [r7, #8] } 8007e3a: 4618 mov r0, r3 8007e3c: 371c adds r7, #28 8007e3e: 46bd mov sp, r7 8007e40: f85d 7b04 ldr.w r7, [sp], #4 8007e44: 4770 bx lr 08007e46 : * This parameter can be one of these values: * 1 : Host * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { 8007e46: b480 push {r7} 8007e48: b083 sub sp, #12 8007e4a: af00 add r7, sp, #0 8007e4c: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 8007e4e: 687b ldr r3, [r7, #4] 8007e50: 695b ldr r3, [r3, #20] 8007e52: f003 0301 and.w r3, r3, #1 } 8007e56: 4618 mov r0, r3 8007e58: 370c adds r7, #12 8007e5a: 46bd mov sp, r7 8007e5c: f85d 7b04 ldr.w r7, [sp], #4 8007e60: 4770 bx lr 08007e62 : * @brief Activate EP0 for Setup transactions * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { 8007e62: b480 push {r7} 8007e64: b085 sub sp, #20 8007e66: af00 add r7, sp, #0 8007e68: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007e6a: 687b ldr r3, [r7, #4] 8007e6c: 60fb str r3, [r7, #12] /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 8007e6e: 68fb ldr r3, [r7, #12] 8007e70: f503 6310 add.w r3, r3, #2304 @ 0x900 8007e74: 681b ldr r3, [r3, #0] 8007e76: 68fa ldr r2, [r7, #12] 8007e78: f502 6210 add.w r2, r2, #2304 @ 0x900 8007e7c: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 8007e80: f023 0307 bic.w r3, r3, #7 8007e84: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 8007e86: 68fb ldr r3, [r7, #12] 8007e88: f503 6300 add.w r3, r3, #2048 @ 0x800 8007e8c: 685b ldr r3, [r3, #4] 8007e8e: 68fa ldr r2, [r7, #12] 8007e90: f502 6200 add.w r2, r2, #2048 @ 0x800 8007e94: f443 7380 orr.w r3, r3, #256 @ 0x100 8007e98: 6053 str r3, [r2, #4] return HAL_OK; 8007e9a: 2300 movs r3, #0 } 8007e9c: 4618 mov r0, r3 8007e9e: 3714 adds r7, #20 8007ea0: 46bd mov sp, r7 8007ea2: f85d 7b04 ldr.w r7, [sp], #4 8007ea6: 4770 bx lr 08007ea8 : * 1 : DMA feature used * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { 8007ea8: b480 push {r7} 8007eaa: b087 sub sp, #28 8007eac: af00 add r7, sp, #0 8007eae: 60f8 str r0, [r7, #12] 8007eb0: 460b mov r3, r1 8007eb2: 607a str r2, [r7, #4] 8007eb4: 72fb strb r3, [r7, #11] uint32_t USBx_BASE = (uint32_t)USBx; 8007eb6: 68fb ldr r3, [r7, #12] 8007eb8: 617b str r3, [r7, #20] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8007eba: 68fb ldr r3, [r7, #12] 8007ebc: 333c adds r3, #60 @ 0x3c 8007ebe: 3304 adds r3, #4 8007ec0: 681b ldr r3, [r3, #0] 8007ec2: 613b str r3, [r7, #16] if (gSNPSiD > USB_OTG_CORE_ID_300A) 8007ec4: 693b ldr r3, [r7, #16] 8007ec6: 4a26 ldr r2, [pc, #152] @ (8007f60 ) 8007ec8: 4293 cmp r3, r2 8007eca: d90a bls.n 8007ee2 { if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007ecc: 697b ldr r3, [r7, #20] 8007ece: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007ed2: 681b ldr r3, [r3, #0] 8007ed4: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007ed8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007edc: d101 bne.n 8007ee2 { return HAL_OK; 8007ede: 2300 movs r3, #0 8007ee0: e037 b.n 8007f52 } } USBx_OUTEP(0U)->DOEPTSIZ = 0U; 8007ee2: 697b ldr r3, [r7, #20] 8007ee4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007ee8: 461a mov r2, r3 8007eea: 2300 movs r3, #0 8007eec: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8007eee: 697b ldr r3, [r7, #20] 8007ef0: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007ef4: 691b ldr r3, [r3, #16] 8007ef6: 697a ldr r2, [r7, #20] 8007ef8: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007efc: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007f00: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); 8007f02: 697b ldr r3, [r7, #20] 8007f04: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f08: 691b ldr r3, [r3, #16] 8007f0a: 697a ldr r2, [r7, #20] 8007f0c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007f10: f043 0318 orr.w r3, r3, #24 8007f14: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 8007f16: 697b ldr r3, [r7, #20] 8007f18: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f1c: 691b ldr r3, [r3, #16] 8007f1e: 697a ldr r2, [r7, #20] 8007f20: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007f24: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000 8007f28: 6113 str r3, [r2, #16] if (dma == 1U) 8007f2a: 7afb ldrb r3, [r7, #11] 8007f2c: 2b01 cmp r3, #1 8007f2e: d10f bne.n 8007f50 { USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; 8007f30: 697b ldr r3, [r7, #20] 8007f32: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f36: 461a mov r2, r3 8007f38: 687b ldr r3, [r7, #4] 8007f3a: 6153 str r3, [r2, #20] /* EP enable */ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; 8007f3c: 697b ldr r3, [r7, #20] 8007f3e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f42: 681b ldr r3, [r3, #0] 8007f44: 697a ldr r2, [r7, #20] 8007f46: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007f4a: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000 8007f4e: 6013 str r3, [r2, #0] } return HAL_OK; 8007f50: 2300 movs r3, #0 } 8007f52: 4618 mov r0, r3 8007f54: 371c adds r7, #28 8007f56: 46bd mov sp, r7 8007f58: f85d 7b04 ldr.w r7, [sp], #4 8007f5c: 4770 bx lr 8007f5e: bf00 nop 8007f60: 4f54300a .word 0x4f54300a 08007f64 : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 8007f64: b480 push {r7} 8007f66: b085 sub sp, #20 8007f68: af00 add r7, sp, #0 8007f6a: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8007f6c: 2300 movs r3, #0 8007f6e: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8007f70: 68fb ldr r3, [r7, #12] 8007f72: 3301 adds r3, #1 8007f74: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007f76: 68fb ldr r3, [r7, #12] 8007f78: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007f7c: d901 bls.n 8007f82 { return HAL_TIMEOUT; 8007f7e: 2303 movs r3, #3 8007f80: e022 b.n 8007fc8 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8007f82: 687b ldr r3, [r7, #4] 8007f84: 691b ldr r3, [r3, #16] 8007f86: 2b00 cmp r3, #0 8007f88: daf2 bge.n 8007f70 count = 10U; 8007f8a: 230a movs r3, #10 8007f8c: 60fb str r3, [r7, #12] /* few cycles before setting core reset */ while (count > 0U) 8007f8e: e002 b.n 8007f96 { count--; 8007f90: 68fb ldr r3, [r7, #12] 8007f92: 3b01 subs r3, #1 8007f94: 60fb str r3, [r7, #12] while (count > 0U) 8007f96: 68fb ldr r3, [r7, #12] 8007f98: 2b00 cmp r3, #0 8007f9a: d1f9 bne.n 8007f90 } /* Core Soft Reset */ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 8007f9c: 687b ldr r3, [r7, #4] 8007f9e: 691b ldr r3, [r3, #16] 8007fa0: f043 0201 orr.w r2, r3, #1 8007fa4: 687b ldr r3, [r7, #4] 8007fa6: 611a str r2, [r3, #16] do { count++; 8007fa8: 68fb ldr r3, [r7, #12] 8007faa: 3301 adds r3, #1 8007fac: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007fae: 68fb ldr r3, [r7, #12] 8007fb0: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007fb4: d901 bls.n 8007fba { return HAL_TIMEOUT; 8007fb6: 2303 movs r3, #3 8007fb8: e006 b.n 8007fc8 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 8007fba: 687b ldr r3, [r7, #4] 8007fbc: 691b ldr r3, [r3, #16] 8007fbe: f003 0301 and.w r3, r3, #1 8007fc2: 2b01 cmp r3, #1 8007fc4: d0f0 beq.n 8007fa8 return HAL_OK; 8007fc6: 2300 movs r3, #0 } 8007fc8: 4618 mov r0, r3 8007fca: 3714 adds r7, #20 8007fcc: 46bd mov sp, r7 8007fce: f85d 7b04 ldr.w r7, [sp], #4 8007fd2: 4770 bx lr 08007fd4 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8007fd4: b580 push {r7, lr} 8007fd6: b084 sub sp, #16 8007fd8: af00 add r7, sp, #0 8007fda: 6078 str r0, [r7, #4] 8007fdc: 460b mov r3, r1 8007fde: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_HID_HandleTypeDef *hhid; hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); 8007fe0: 2010 movs r0, #16 8007fe2: f002 f9e3 bl 800a3ac 8007fe6: 60f8 str r0, [r7, #12] if (hhid == NULL) 8007fe8: 68fb ldr r3, [r7, #12] 8007fea: 2b00 cmp r3, #0 8007fec: d109 bne.n 8008002 { pdev->pClassDataCmsit[pdev->classId] = NULL; 8007fee: 687b ldr r3, [r7, #4] 8007ff0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8007ff4: 687b ldr r3, [r7, #4] 8007ff6: 32b0 adds r2, #176 @ 0xb0 8007ff8: 2100 movs r1, #0 8007ffa: f843 1022 str.w r1, [r3, r2, lsl #2] return (uint8_t)USBD_EMEM; 8007ffe: 2302 movs r3, #2 8008000: e048 b.n 8008094 } pdev->pClassDataCmsit[pdev->classId] = (void *)hhid; 8008002: 687b ldr r3, [r7, #4] 8008004: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008008: 687b ldr r3, [r7, #4] 800800a: 32b0 adds r2, #176 @ 0xb0 800800c: 68f9 ldr r1, [r7, #12] 800800e: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; 8008012: 687b ldr r3, [r7, #4] 8008014: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008018: 687b ldr r3, [r7, #4] 800801a: 32b0 adds r2, #176 @ 0xb0 800801c: f853 2022 ldr.w r2, [r3, r2, lsl #2] 8008020: 687b ldr r3, [r7, #4] 8008022: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_speed == USBD_SPEED_HIGH) 8008026: 687b ldr r3, [r7, #4] 8008028: 7c1b ldrb r3, [r3, #16] 800802a: 2b00 cmp r3, #0 800802c: d10d bne.n 800804a { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL; 800802e: 4b1b ldr r3, [pc, #108] @ (800809c ) 8008030: 781b ldrb r3, [r3, #0] 8008032: f003 020f and.w r2, r3, #15 8008036: 6879 ldr r1, [r7, #4] 8008038: 4613 mov r3, r2 800803a: 009b lsls r3, r3, #2 800803c: 4413 add r3, r2 800803e: 009b lsls r3, r3, #2 8008040: 440b add r3, r1 8008042: 331c adds r3, #28 8008044: 2207 movs r2, #7 8008046: 601a str r2, [r3, #0] 8008048: e00c b.n 8008064 } else /* LOW and FULL-speed endpoints */ { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL; 800804a: 4b14 ldr r3, [pc, #80] @ (800809c ) 800804c: 781b ldrb r3, [r3, #0] 800804e: f003 020f and.w r2, r3, #15 8008052: 6879 ldr r1, [r7, #4] 8008054: 4613 mov r3, r2 8008056: 009b lsls r3, r3, #2 8008058: 4413 add r3, r2 800805a: 009b lsls r3, r3, #2 800805c: 440b add r3, r1 800805e: 331c adds r3, #28 8008060: 220a movs r2, #10 8008062: 601a str r2, [r3, #0] } /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); 8008064: 4b0d ldr r3, [pc, #52] @ (800809c ) 8008066: 7819 ldrb r1, [r3, #0] 8008068: 2304 movs r3, #4 800806a: 2203 movs r2, #3 800806c: 6878 ldr r0, [r7, #4] 800806e: f002 f83e bl 800a0ee pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U; 8008072: 4b0a ldr r3, [pc, #40] @ (800809c ) 8008074: 781b ldrb r3, [r3, #0] 8008076: f003 020f and.w r2, r3, #15 800807a: 6879 ldr r1, [r7, #4] 800807c: 4613 mov r3, r2 800807e: 009b lsls r3, r3, #2 8008080: 4413 add r3, r2 8008082: 009b lsls r3, r3, #2 8008084: 440b add r3, r1 8008086: 3323 adds r3, #35 @ 0x23 8008088: 2201 movs r2, #1 800808a: 701a strb r2, [r3, #0] hhid->state = USBD_HID_IDLE; 800808c: 68fb ldr r3, [r7, #12] 800808e: 2200 movs r2, #0 8008090: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 8008092: 2300 movs r3, #0 } 8008094: 4618 mov r0, r3 8008096: 3710 adds r7, #16 8008098: 46bd mov sp, r7 800809a: bd80 pop {r7, pc} 800809c: 2000015a .word 0x2000015a 080080a0 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80080a0: b580 push {r7, lr} 80080a2: b082 sub sp, #8 80080a4: af00 add r7, sp, #0 80080a6: 6078 str r0, [r7, #4] 80080a8: 460b mov r3, r1 80080aa: 70fb strb r3, [r7, #3] /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ /* Close HID EPs */ (void)USBD_LL_CloseEP(pdev, HIDInEpAdd); 80080ac: 4b1f ldr r3, [pc, #124] @ (800812c ) 80080ae: 781b ldrb r3, [r3, #0] 80080b0: 4619 mov r1, r3 80080b2: 6878 ldr r0, [r7, #4] 80080b4: f002 f841 bl 800a13a pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U; 80080b8: 4b1c ldr r3, [pc, #112] @ (800812c ) 80080ba: 781b ldrb r3, [r3, #0] 80080bc: f003 020f and.w r2, r3, #15 80080c0: 6879 ldr r1, [r7, #4] 80080c2: 4613 mov r3, r2 80080c4: 009b lsls r3, r3, #2 80080c6: 4413 add r3, r2 80080c8: 009b lsls r3, r3, #2 80080ca: 440b add r3, r1 80080cc: 3323 adds r3, #35 @ 0x23 80080ce: 2200 movs r2, #0 80080d0: 701a strb r2, [r3, #0] pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U; 80080d2: 4b16 ldr r3, [pc, #88] @ (800812c ) 80080d4: 781b ldrb r3, [r3, #0] 80080d6: f003 020f and.w r2, r3, #15 80080da: 6879 ldr r1, [r7, #4] 80080dc: 4613 mov r3, r2 80080de: 009b lsls r3, r3, #2 80080e0: 4413 add r3, r2 80080e2: 009b lsls r3, r3, #2 80080e4: 440b add r3, r1 80080e6: 331c adds r3, #28 80080e8: 2200 movs r2, #0 80080ea: 601a str r2, [r3, #0] /* Free allocated memory */ if (pdev->pClassDataCmsit[pdev->classId] != NULL) 80080ec: 687b ldr r3, [r7, #4] 80080ee: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80080f2: 687b ldr r3, [r7, #4] 80080f4: 32b0 adds r2, #176 @ 0xb0 80080f6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80080fa: 2b00 cmp r3, #0 80080fc: d011 beq.n 8008122 { (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); 80080fe: 687b ldr r3, [r7, #4] 8008100: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008104: 687b ldr r3, [r7, #4] 8008106: 32b0 adds r2, #176 @ 0xb0 8008108: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800810c: 4618 mov r0, r3 800810e: f002 f95b bl 800a3c8 pdev->pClassDataCmsit[pdev->classId] = NULL; 8008112: 687b ldr r3, [r7, #4] 8008114: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008118: 687b ldr r3, [r7, #4] 800811a: 32b0 adds r2, #176 @ 0xb0 800811c: 2100 movs r1, #0 800811e: f843 1022 str.w r1, [r3, r2, lsl #2] } return (uint8_t)USBD_OK; 8008122: 2300 movs r3, #0 } 8008124: 4618 mov r0, r3 8008126: 3708 adds r7, #8 8008128: 46bd mov sp, r7 800812a: bd80 pop {r7, pc} 800812c: 2000015a .word 0x2000015a 08008130 : * @param pdev: instance * @param req: usb requests * @retval status */ static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008130: b580 push {r7, lr} 8008132: b086 sub sp, #24 8008134: af00 add r7, sp, #0 8008136: 6078 str r0, [r7, #4] 8008138: 6039 str r1, [r7, #0] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 800813a: 687b ldr r3, [r7, #4] 800813c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008140: 687b ldr r3, [r7, #4] 8008142: 32b0 adds r2, #176 @ 0xb0 8008144: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008148: 60fb str r3, [r7, #12] USBD_StatusTypeDef ret = USBD_OK; 800814a: 2300 movs r3, #0 800814c: 75fb strb r3, [r7, #23] uint16_t len; uint8_t *pbuf; uint16_t status_info = 0U; 800814e: 2300 movs r3, #0 8008150: 817b strh r3, [r7, #10] if (hhid == NULL) 8008152: 68fb ldr r3, [r7, #12] 8008154: 2b00 cmp r3, #0 8008156: d101 bne.n 800815c { return (uint8_t)USBD_FAIL; 8008158: 2303 movs r3, #3 800815a: e0e8 b.n 800832e } switch (req->bmRequest & USB_REQ_TYPE_MASK) 800815c: 683b ldr r3, [r7, #0] 800815e: 781b ldrb r3, [r3, #0] 8008160: f003 0360 and.w r3, r3, #96 @ 0x60 8008164: 2b00 cmp r3, #0 8008166: d046 beq.n 80081f6 8008168: 2b20 cmp r3, #32 800816a: f040 80d8 bne.w 800831e { case USB_REQ_TYPE_CLASS : switch (req->bRequest) 800816e: 683b ldr r3, [r7, #0] 8008170: 785b ldrb r3, [r3, #1] 8008172: 3b02 subs r3, #2 8008174: 2b09 cmp r3, #9 8008176: d836 bhi.n 80081e6 8008178: a201 add r2, pc, #4 @ (adr r2, 8008180 ) 800817a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800817e: bf00 nop 8008180: 080081d7 .word 0x080081d7 8008184: 080081b7 .word 0x080081b7 8008188: 080081e7 .word 0x080081e7 800818c: 080081e7 .word 0x080081e7 8008190: 080081e7 .word 0x080081e7 8008194: 080081e7 .word 0x080081e7 8008198: 080081e7 .word 0x080081e7 800819c: 080081e7 .word 0x080081e7 80081a0: 080081c5 .word 0x080081c5 80081a4: 080081a9 .word 0x080081a9 { case USBD_HID_REQ_SET_PROTOCOL: hhid->Protocol = (uint8_t)(req->wValue); 80081a8: 683b ldr r3, [r7, #0] 80081aa: 885b ldrh r3, [r3, #2] 80081ac: b2db uxtb r3, r3 80081ae: 461a mov r2, r3 80081b0: 68fb ldr r3, [r7, #12] 80081b2: 601a str r2, [r3, #0] break; 80081b4: e01e b.n 80081f4 case USBD_HID_REQ_GET_PROTOCOL: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); 80081b6: 68fb ldr r3, [r7, #12] 80081b8: 2201 movs r2, #1 80081ba: 4619 mov r1, r3 80081bc: 6878 ldr r0, [r7, #4] 80081be: f001 fc25 bl 8009a0c break; 80081c2: e017 b.n 80081f4 case USBD_HID_REQ_SET_IDLE: hhid->IdleState = (uint8_t)(req->wValue >> 8); 80081c4: 683b ldr r3, [r7, #0] 80081c6: 885b ldrh r3, [r3, #2] 80081c8: 0a1b lsrs r3, r3, #8 80081ca: b29b uxth r3, r3 80081cc: b2db uxtb r3, r3 80081ce: 461a mov r2, r3 80081d0: 68fb ldr r3, [r7, #12] 80081d2: 605a str r2, [r3, #4] break; 80081d4: e00e b.n 80081f4 case USBD_HID_REQ_GET_IDLE: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); 80081d6: 68fb ldr r3, [r7, #12] 80081d8: 3304 adds r3, #4 80081da: 2201 movs r2, #1 80081dc: 4619 mov r1, r3 80081de: 6878 ldr r0, [r7, #4] 80081e0: f001 fc14 bl 8009a0c break; 80081e4: e006 b.n 80081f4 default: USBD_CtlError(pdev, req); 80081e6: 6839 ldr r1, [r7, #0] 80081e8: 6878 ldr r0, [r7, #4] 80081ea: f001 fb92 bl 8009912 ret = USBD_FAIL; 80081ee: 2303 movs r3, #3 80081f0: 75fb strb r3, [r7, #23] break; 80081f2: bf00 nop } break; 80081f4: e09a b.n 800832c case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80081f6: 683b ldr r3, [r7, #0] 80081f8: 785b ldrb r3, [r3, #1] 80081fa: 2b0b cmp r3, #11 80081fc: f200 8086 bhi.w 800830c 8008200: a201 add r2, pc, #4 @ (adr r2, 8008208 ) 8008202: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008206: bf00 nop 8008208: 08008239 .word 0x08008239 800820c: 0800831b .word 0x0800831b 8008210: 0800830d .word 0x0800830d 8008214: 0800830d .word 0x0800830d 8008218: 0800830d .word 0x0800830d 800821c: 0800830d .word 0x0800830d 8008220: 08008263 .word 0x08008263 8008224: 0800830d .word 0x0800830d 8008228: 0800830d .word 0x0800830d 800822c: 0800830d .word 0x0800830d 8008230: 080082bb .word 0x080082bb 8008234: 080082e5 .word 0x080082e5 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008238: 687b ldr r3, [r7, #4] 800823a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800823e: b2db uxtb r3, r3 8008240: 2b03 cmp r3, #3 8008242: d107 bne.n 8008254 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 8008244: f107 030a add.w r3, r7, #10 8008248: 2202 movs r2, #2 800824a: 4619 mov r1, r3 800824c: 6878 ldr r0, [r7, #4] 800824e: f001 fbdd bl 8009a0c else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8008252: e063 b.n 800831c USBD_CtlError(pdev, req); 8008254: 6839 ldr r1, [r7, #0] 8008256: 6878 ldr r0, [r7, #4] 8008258: f001 fb5b bl 8009912 ret = USBD_FAIL; 800825c: 2303 movs r3, #3 800825e: 75fb strb r3, [r7, #23] break; 8008260: e05c b.n 800831c case USB_REQ_GET_DESCRIPTOR: if ((req->wValue >> 8) == HID_REPORT_DESC) 8008262: 683b ldr r3, [r7, #0] 8008264: 885b ldrh r3, [r3, #2] 8008266: 0a1b lsrs r3, r3, #8 8008268: b29b uxth r3, r3 800826a: 2b22 cmp r3, #34 @ 0x22 800826c: d108 bne.n 8008280 { len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); 800826e: 683b ldr r3, [r7, #0] 8008270: 88db ldrh r3, [r3, #6] 8008272: 2b4a cmp r3, #74 @ 0x4a 8008274: bf28 it cs 8008276: 234a movcs r3, #74 @ 0x4a 8008278: 82bb strh r3, [r7, #20] pbuf = HID_MOUSE_ReportDesc; 800827a: 4b2f ldr r3, [pc, #188] @ (8008338 ) 800827c: 613b str r3, [r7, #16] 800827e: e015 b.n 80082ac } else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) 8008280: 683b ldr r3, [r7, #0] 8008282: 885b ldrh r3, [r3, #2] 8008284: 0a1b lsrs r3, r3, #8 8008286: b29b uxth r3, r3 8008288: 2b21 cmp r3, #33 @ 0x21 800828a: d108 bne.n 800829e { pbuf = USBD_HID_Desc; 800828c: 4b2b ldr r3, [pc, #172] @ (800833c ) 800828e: 613b str r3, [r7, #16] len = MIN(USB_HID_DESC_SIZ, req->wLength); 8008290: 683b ldr r3, [r7, #0] 8008292: 88db ldrh r3, [r3, #6] 8008294: 2b09 cmp r3, #9 8008296: bf28 it cs 8008298: 2309 movcs r3, #9 800829a: 82bb strh r3, [r7, #20] 800829c: e006 b.n 80082ac } else { USBD_CtlError(pdev, req); 800829e: 6839 ldr r1, [r7, #0] 80082a0: 6878 ldr r0, [r7, #4] 80082a2: f001 fb36 bl 8009912 ret = USBD_FAIL; 80082a6: 2303 movs r3, #3 80082a8: 75fb strb r3, [r7, #23] break; 80082aa: e037 b.n 800831c } (void)USBD_CtlSendData(pdev, pbuf, len); 80082ac: 8abb ldrh r3, [r7, #20] 80082ae: 461a mov r2, r3 80082b0: 6939 ldr r1, [r7, #16] 80082b2: 6878 ldr r0, [r7, #4] 80082b4: f001 fbaa bl 8009a0c break; 80082b8: e030 b.n 800831c case USB_REQ_GET_INTERFACE : if (pdev->dev_state == USBD_STATE_CONFIGURED) 80082ba: 687b ldr r3, [r7, #4] 80082bc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80082c0: b2db uxtb r3, r3 80082c2: 2b03 cmp r3, #3 80082c4: d107 bne.n 80082d6 { (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); 80082c6: 68fb ldr r3, [r7, #12] 80082c8: 3308 adds r3, #8 80082ca: 2201 movs r2, #1 80082cc: 4619 mov r1, r3 80082ce: 6878 ldr r0, [r7, #4] 80082d0: f001 fb9c bl 8009a0c else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 80082d4: e022 b.n 800831c USBD_CtlError(pdev, req); 80082d6: 6839 ldr r1, [r7, #0] 80082d8: 6878 ldr r0, [r7, #4] 80082da: f001 fb1a bl 8009912 ret = USBD_FAIL; 80082de: 2303 movs r3, #3 80082e0: 75fb strb r3, [r7, #23] break; 80082e2: e01b b.n 800831c case USB_REQ_SET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 80082e4: 687b ldr r3, [r7, #4] 80082e6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80082ea: b2db uxtb r3, r3 80082ec: 2b03 cmp r3, #3 80082ee: d106 bne.n 80082fe { hhid->AltSetting = (uint8_t)(req->wValue); 80082f0: 683b ldr r3, [r7, #0] 80082f2: 885b ldrh r3, [r3, #2] 80082f4: b2db uxtb r3, r3 80082f6: 461a mov r2, r3 80082f8: 68fb ldr r3, [r7, #12] 80082fa: 609a str r2, [r3, #8] else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 80082fc: e00e b.n 800831c USBD_CtlError(pdev, req); 80082fe: 6839 ldr r1, [r7, #0] 8008300: 6878 ldr r0, [r7, #4] 8008302: f001 fb06 bl 8009912 ret = USBD_FAIL; 8008306: 2303 movs r3, #3 8008308: 75fb strb r3, [r7, #23] break; 800830a: e007 b.n 800831c case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 800830c: 6839 ldr r1, [r7, #0] 800830e: 6878 ldr r0, [r7, #4] 8008310: f001 faff bl 8009912 ret = USBD_FAIL; 8008314: 2303 movs r3, #3 8008316: 75fb strb r3, [r7, #23] break; 8008318: e000 b.n 800831c break; 800831a: bf00 nop } break; 800831c: e006 b.n 800832c default: USBD_CtlError(pdev, req); 800831e: 6839 ldr r1, [r7, #0] 8008320: 6878 ldr r0, [r7, #4] 8008322: f001 faf6 bl 8009912 ret = USBD_FAIL; 8008326: 2303 movs r3, #3 8008328: 75fb strb r3, [r7, #23] break; 800832a: bf00 nop } return (uint8_t)ret; 800832c: 7dfb ldrb r3, [r7, #23] } 800832e: 4618 mov r0, r3 8008330: 3718 adds r7, #24 8008332: 46bd mov sp, r7 8008334: bd80 pop {r7, pc} 8008336: bf00 nop 8008338: 20000110 .word 0x20000110 800833c: 200000f8 .word 0x200000f8 08008340 : uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId) { USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) { 8008340: b580 push {r7, lr} 8008342: b086 sub sp, #24 8008344: af00 add r7, sp, #0 8008346: 60f8 str r0, [r7, #12] 8008348: 60b9 str r1, [r7, #8] 800834a: 4613 mov r3, r2 800834c: 80fb strh r3, [r7, #6] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 800834e: 68fb ldr r3, [r7, #12] 8008350: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008354: 68fb ldr r3, [r7, #12] 8008356: 32b0 adds r2, #176 @ 0xb0 8008358: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800835c: 617b str r3, [r7, #20] #endif /* USE_USBD_COMPOSITE */ if (hhid == NULL) 800835e: 697b ldr r3, [r7, #20] 8008360: 2b00 cmp r3, #0 8008362: d101 bne.n 8008368 { return (uint8_t)USBD_FAIL; 8008364: 2303 movs r3, #3 8008366: e014 b.n 8008392 #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008368: 68fb ldr r3, [r7, #12] 800836a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800836e: b2db uxtb r3, r3 8008370: 2b03 cmp r3, #3 8008372: d10d bne.n 8008390 { if (hhid->state == USBD_HID_IDLE) 8008374: 697b ldr r3, [r7, #20] 8008376: 7b1b ldrb r3, [r3, #12] 8008378: 2b00 cmp r3, #0 800837a: d109 bne.n 8008390 { hhid->state = USBD_HID_BUSY; 800837c: 697b ldr r3, [r7, #20] 800837e: 2201 movs r2, #1 8008380: 731a strb r2, [r3, #12] (void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len); 8008382: 4b06 ldr r3, [pc, #24] @ (800839c ) 8008384: 7819 ldrb r1, [r3, #0] 8008386: 88fb ldrh r3, [r7, #6] 8008388: 68ba ldr r2, [r7, #8] 800838a: 68f8 ldr r0, [r7, #12] 800838c: f001 ff7d bl 800a28a } } return (uint8_t)USBD_OK; 8008390: 2300 movs r3, #0 } 8008392: 4618 mov r0, r3 8008394: 3718 adds r7, #24 8008396: 46bd mov sp, r7 8008398: bd80 pop {r7, pc} 800839a: bf00 nop 800839c: 2000015a .word 0x2000015a 080083a0 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) { 80083a0: b580 push {r7, lr} 80083a2: b084 sub sp, #16 80083a4: af00 add r7, sp, #0 80083a6: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 80083a8: 2181 movs r1, #129 @ 0x81 80083aa: 4809 ldr r0, [pc, #36] @ (80083d0 ) 80083ac: f000 fc4e bl 8008c4c 80083b0: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 80083b2: 68fb ldr r3, [r7, #12] 80083b4: 2b00 cmp r3, #0 80083b6: d002 beq.n 80083be { pEpDesc->bInterval = HID_FS_BINTERVAL; 80083b8: 68fb ldr r3, [r7, #12] 80083ba: 220a movs r2, #10 80083bc: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 80083be: 687b ldr r3, [r7, #4] 80083c0: 2222 movs r2, #34 @ 0x22 80083c2: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 80083c4: 4b02 ldr r3, [pc, #8] @ (80083d0 ) } 80083c6: 4618 mov r0, r3 80083c8: 3710 adds r7, #16 80083ca: 46bd mov sp, r7 80083cc: bd80 pop {r7, pc} 80083ce: bf00 nop 80083d0: 200000d4 .word 0x200000d4 080083d4 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) { 80083d4: b580 push {r7, lr} 80083d6: b084 sub sp, #16 80083d8: af00 add r7, sp, #0 80083da: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 80083dc: 2181 movs r1, #129 @ 0x81 80083de: 4809 ldr r0, [pc, #36] @ (8008404 ) 80083e0: f000 fc34 bl 8008c4c 80083e4: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 80083e6: 68fb ldr r3, [r7, #12] 80083e8: 2b00 cmp r3, #0 80083ea: d002 beq.n 80083f2 { pEpDesc->bInterval = HID_HS_BINTERVAL; 80083ec: 68fb ldr r3, [r7, #12] 80083ee: 2207 movs r2, #7 80083f0: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 80083f2: 687b ldr r3, [r7, #4] 80083f4: 2222 movs r2, #34 @ 0x22 80083f6: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 80083f8: 4b02 ldr r3, [pc, #8] @ (8008404 ) } 80083fa: 4618 mov r0, r3 80083fc: 3710 adds r7, #16 80083fe: 46bd mov sp, r7 8008400: bd80 pop {r7, pc} 8008402: bf00 nop 8008404: 200000d4 .word 0x200000d4 08008408 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) { 8008408: b580 push {r7, lr} 800840a: b084 sub sp, #16 800840c: af00 add r7, sp, #0 800840e: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8008410: 2181 movs r1, #129 @ 0x81 8008412: 4809 ldr r0, [pc, #36] @ (8008438 ) 8008414: f000 fc1a bl 8008c4c 8008418: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 800841a: 68fb ldr r3, [r7, #12] 800841c: 2b00 cmp r3, #0 800841e: d002 beq.n 8008426 { pEpDesc->bInterval = HID_FS_BINTERVAL; 8008420: 68fb ldr r3, [r7, #12] 8008422: 220a movs r2, #10 8008424: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 8008426: 687b ldr r3, [r7, #4] 8008428: 2222 movs r2, #34 @ 0x22 800842a: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 800842c: 4b02 ldr r3, [pc, #8] @ (8008438 ) } 800842e: 4618 mov r0, r3 8008430: 3710 adds r7, #16 8008432: 46bd mov sp, r7 8008434: bd80 pop {r7, pc} 8008436: bf00 nop 8008438: 200000d4 .word 0x200000d4 0800843c : * @param pdev: device instance * @param epnum: endpoint index * @retval status */ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 800843c: b480 push {r7} 800843e: b083 sub sp, #12 8008440: af00 add r7, sp, #0 8008442: 6078 str r0, [r7, #4] 8008444: 460b mov r3, r1 8008446: 70fb strb r3, [r7, #3] UNUSED(epnum); /* Ensure that the FIFO is empty before a new transfer, this condition could be caused by a new transfer before the end of the previous transfer */ ((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE; 8008448: 687b ldr r3, [r7, #4] 800844a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800844e: 687b ldr r3, [r7, #4] 8008450: 32b0 adds r2, #176 @ 0xb0 8008452: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008456: 2200 movs r2, #0 8008458: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 800845a: 2300 movs r3, #0 } 800845c: 4618 mov r0, r3 800845e: 370c adds r7, #12 8008460: 46bd mov sp, r7 8008462: f85d 7b04 ldr.w r7, [sp], #4 8008466: 4770 bx lr 08008468 : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) { 8008468: b480 push {r7} 800846a: b083 sub sp, #12 800846c: af00 add r7, sp, #0 800846e: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); 8008470: 687b ldr r3, [r7, #4] 8008472: 220a movs r2, #10 8008474: 801a strh r2, [r3, #0] return USBD_HID_DeviceQualifierDesc; 8008476: 4b03 ldr r3, [pc, #12] @ (8008484 ) } 8008478: 4618 mov r0, r3 800847a: 370c adds r7, #12 800847c: 46bd mov sp, r7 800847e: f85d 7b04 ldr.w r7, [sp], #4 8008482: 4770 bx lr 8008484: 20000104 .word 0x20000104 08008488 : * @param id: Low level core index * @retval status: USBD Status */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 8008488: b580 push {r7, lr} 800848a: b086 sub sp, #24 800848c: af00 add r7, sp, #0 800848e: 60f8 str r0, [r7, #12] 8008490: 60b9 str r1, [r7, #8] 8008492: 4613 mov r3, r2 8008494: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 8008496: 68fb ldr r3, [r7, #12] 8008498: 2b00 cmp r3, #0 800849a: d101 bne.n 80084a0 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 800849c: 2303 movs r3, #3 800849e: e01f b.n 80084e0 pdev->NumClasses = 0; pdev->classId = 0; } #else /* Unlink previous class*/ pdev->pClass[0] = NULL; 80084a0: 68fb ldr r3, [r7, #12] 80084a2: 2200 movs r2, #0 80084a4: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 pdev->pUserData[0] = NULL; 80084a8: 68fb ldr r3, [r7, #12] 80084aa: 2200 movs r2, #0 80084ac: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4 #endif /* USE_USBD_COMPOSITE */ pdev->pConfDesc = NULL; 80084b0: 68fb ldr r3, [r7, #12] 80084b2: 2200 movs r2, #0 80084b4: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 /* Assign USBD Descriptors */ if (pdesc != NULL) 80084b8: 68bb ldr r3, [r7, #8] 80084ba: 2b00 cmp r3, #0 80084bc: d003 beq.n 80084c6 { pdev->pDesc = pdesc; 80084be: 68fb ldr r3, [r7, #12] 80084c0: 68ba ldr r2, [r7, #8] 80084c2: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 80084c6: 68fb ldr r3, [r7, #12] 80084c8: 2201 movs r2, #1 80084ca: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->id = id; 80084ce: 68fb ldr r3, [r7, #12] 80084d0: 79fa ldrb r2, [r7, #7] 80084d2: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 80084d4: 68f8 ldr r0, [r7, #12] 80084d6: f001 fda3 bl 800a020 80084da: 4603 mov r3, r0 80084dc: 75fb strb r3, [r7, #23] return ret; 80084de: 7dfb ldrb r3, [r7, #23] } 80084e0: 4618 mov r0, r3 80084e2: 3718 adds r7, #24 80084e4: 46bd mov sp, r7 80084e6: bd80 pop {r7, pc} 080084e8 : * @param pdev: Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 80084e8: b580 push {r7, lr} 80084ea: b084 sub sp, #16 80084ec: af00 add r7, sp, #0 80084ee: 6078 str r0, [r7, #4] 80084f0: 6039 str r1, [r7, #0] uint16_t len = 0U; 80084f2: 2300 movs r3, #0 80084f4: 81fb strh r3, [r7, #14] if (pclass == NULL) 80084f6: 683b ldr r3, [r7, #0] 80084f8: 2b00 cmp r3, #0 80084fa: d101 bne.n 8008500 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 80084fc: 2303 movs r3, #3 80084fe: e025 b.n 800854c } /* link the class to the USB Device handle */ pdev->pClass[0] = pclass; 8008500: 687b ldr r3, [r7, #4] 8008502: 683a ldr r2, [r7, #0] 8008504: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) 8008508: 687b ldr r3, [r7, #4] 800850a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800850e: 687b ldr r3, [r7, #4] 8008510: 32ae adds r2, #174 @ 0xae 8008512: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008516: 6adb ldr r3, [r3, #44] @ 0x2c 8008518: 2b00 cmp r3, #0 800851a: d00f beq.n 800853c { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); 800851c: 687b ldr r3, [r7, #4] 800851e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008522: 687b ldr r3, [r7, #4] 8008524: 32ae adds r2, #174 @ 0xae 8008526: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800852a: 6adb ldr r3, [r3, #44] @ 0x2c 800852c: f107 020e add.w r2, r7, #14 8008530: 4610 mov r0, r2 8008532: 4798 blx r3 8008534: 4602 mov r2, r0 8008536: 687b ldr r3, [r7, #4] 8008538: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 } #endif /* USE_USB_FS */ /* Increment the NumClasses */ pdev->NumClasses++; 800853c: 687b ldr r3, [r7, #4] 800853e: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8008542: 1c5a adds r2, r3, #1 8008544: 687b ldr r3, [r7, #4] 8008546: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8 return USBD_OK; 800854a: 2300 movs r3, #0 } 800854c: 4618 mov r0, r3 800854e: 3710 adds r7, #16 8008550: 46bd mov sp, r7 8008552: bd80 pop {r7, pc} 08008554 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 8008554: b580 push {r7, lr} 8008556: b082 sub sp, #8 8008558: af00 add r7, sp, #0 800855a: 6078 str r0, [r7, #4] #ifdef USE_USBD_COMPOSITE pdev->classId = 0U; #endif /* USE_USBD_COMPOSITE */ /* Start the low level driver */ return USBD_LL_Start(pdev); 800855c: 6878 ldr r0, [r7, #4] 800855e: f001 fdab bl 800a0b8 8008562: 4603 mov r3, r0 } 8008564: 4618 mov r0, r3 8008566: 3708 adds r7, #8 8008568: 46bd mov sp, r7 800856a: bd80 pop {r7, pc} 0800856c : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 800856c: b480 push {r7} 800856e: b083 sub sp, #12 8008570: af00 add r7, sp, #0 8008572: 6078 str r0, [r7, #4] return ret; #else /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8008574: 2300 movs r3, #0 #endif /* USBD_HS_TESTMODE_ENABLE */ } 8008576: 4618 mov r0, r3 8008578: 370c adds r7, #12 800857a: 46bd mov sp, r7 800857c: f85d 7b04 ldr.w r7, [sp], #4 8008580: 4770 bx lr 08008582 : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008582: b580 push {r7, lr} 8008584: b084 sub sp, #16 8008586: af00 add r7, sp, #0 8008588: 6078 str r0, [r7, #4] 800858a: 460b mov r3, r1 800858c: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 800858e: 2300 movs r3, #0 8008590: 73fb strb r3, [r7, #15] } } } } #else if (pdev->pClass[0] != NULL) 8008592: 687b ldr r3, [r7, #4] 8008594: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008598: 2b00 cmp r3, #0 800859a: d009 beq.n 80085b0 { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); 800859c: 687b ldr r3, [r7, #4] 800859e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80085a2: 681b ldr r3, [r3, #0] 80085a4: 78fa ldrb r2, [r7, #3] 80085a6: 4611 mov r1, r2 80085a8: 6878 ldr r0, [r7, #4] 80085aa: 4798 blx r3 80085ac: 4603 mov r3, r0 80085ae: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 80085b0: 7bfb ldrb r3, [r7, #15] } 80085b2: 4618 mov r0, r3 80085b4: 3710 adds r7, #16 80085b6: 46bd mov sp, r7 80085b8: bd80 pop {r7, pc} 080085ba : * @param pdev: device instance * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80085ba: b580 push {r7, lr} 80085bc: b084 sub sp, #16 80085be: af00 add r7, sp, #0 80085c0: 6078 str r0, [r7, #4] 80085c2: 460b mov r3, r1 80085c4: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 80085c6: 2300 movs r3, #0 80085c8: 73fb strb r3, [r7, #15] } } } #else /* Clear configuration and De-initialize the Class process */ if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) 80085ca: 687b ldr r3, [r7, #4] 80085cc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80085d0: 685b ldr r3, [r3, #4] 80085d2: 78fa ldrb r2, [r7, #3] 80085d4: 4611 mov r1, r2 80085d6: 6878 ldr r0, [r7, #4] 80085d8: 4798 blx r3 80085da: 4603 mov r3, r0 80085dc: 2b00 cmp r3, #0 80085de: d001 beq.n 80085e4 { ret = USBD_FAIL; 80085e0: 2303 movs r3, #3 80085e2: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 80085e4: 7bfb ldrb r3, [r7, #15] } 80085e6: 4618 mov r0, r3 80085e8: 3710 adds r7, #16 80085ea: 46bd mov sp, r7 80085ec: bd80 pop {r7, pc} 080085ee : * @param pdev: device instance * @param psetup: setup packet buffer pointer * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 80085ee: b580 push {r7, lr} 80085f0: b084 sub sp, #16 80085f2: af00 add r7, sp, #0 80085f4: 6078 str r0, [r7, #4] 80085f6: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 80085f8: 687b ldr r3, [r7, #4] 80085fa: f203 23aa addw r3, r3, #682 @ 0x2aa 80085fe: 6839 ldr r1, [r7, #0] 8008600: 4618 mov r0, r3 8008602: f001 f94c bl 800989e pdev->ep0_state = USBD_EP0_SETUP; 8008606: 687b ldr r3, [r7, #4] 8008608: 2201 movs r2, #1 800860a: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep0_data_len = pdev->request.wLength; 800860e: 687b ldr r3, [r7, #4] 8008610: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0 8008614: 461a mov r2, r3 8008616: 687b ldr r3, [r7, #4] 8008618: f8c3 2298 str.w r2, [r3, #664] @ 0x298 switch (pdev->request.bmRequest & 0x1FU) 800861c: 687b ldr r3, [r7, #4] 800861e: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008622: f003 031f and.w r3, r3, #31 8008626: 2b02 cmp r3, #2 8008628: d01a beq.n 8008660 800862a: 2b02 cmp r3, #2 800862c: d822 bhi.n 8008674 800862e: 2b00 cmp r3, #0 8008630: d002 beq.n 8008638 8008632: 2b01 cmp r3, #1 8008634: d00a beq.n 800864c 8008636: e01d b.n 8008674 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 8008638: 687b ldr r3, [r7, #4] 800863a: f203 23aa addw r3, r3, #682 @ 0x2aa 800863e: 4619 mov r1, r3 8008640: 6878 ldr r0, [r7, #4] 8008642: f000 fb77 bl 8008d34 8008646: 4603 mov r3, r0 8008648: 73fb strb r3, [r7, #15] break; 800864a: e020 b.n 800868e case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 800864c: 687b ldr r3, [r7, #4] 800864e: f203 23aa addw r3, r3, #682 @ 0x2aa 8008652: 4619 mov r1, r3 8008654: 6878 ldr r0, [r7, #4] 8008656: f000 fbdf bl 8008e18 800865a: 4603 mov r3, r0 800865c: 73fb strb r3, [r7, #15] break; 800865e: e016 b.n 800868e case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 8008660: 687b ldr r3, [r7, #4] 8008662: f203 23aa addw r3, r3, #682 @ 0x2aa 8008666: 4619 mov r1, r3 8008668: 6878 ldr r0, [r7, #4] 800866a: f000 fc41 bl 8008ef0 800866e: 4603 mov r3, r0 8008670: 73fb strb r3, [r7, #15] break; 8008672: e00c b.n 800868e default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 8008674: 687b ldr r3, [r7, #4] 8008676: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 800867a: f023 037f bic.w r3, r3, #127 @ 0x7f 800867e: b2db uxtb r3, r3 8008680: 4619 mov r1, r3 8008682: 6878 ldr r0, [r7, #4] 8008684: f001 fd78 bl 800a178 8008688: 4603 mov r3, r0 800868a: 73fb strb r3, [r7, #15] break; 800868c: bf00 nop } return ret; 800868e: 7bfb ldrb r3, [r7, #15] } 8008690: 4618 mov r0, r3 8008692: 3710 adds r7, #16 8008694: 46bd mov sp, r7 8008696: bd80 pop {r7, pc} 08008698 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8008698: b580 push {r7, lr} 800869a: b086 sub sp, #24 800869c: af00 add r7, sp, #0 800869e: 60f8 str r0, [r7, #12] 80086a0: 460b mov r3, r1 80086a2: 607a str r2, [r7, #4] 80086a4: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret = USBD_OK; 80086a6: 2300 movs r3, #0 80086a8: 75fb strb r3, [r7, #23] uint8_t idx; UNUSED(pdata); if (epnum == 0U) 80086aa: 7afb ldrb r3, [r7, #11] 80086ac: 2b00 cmp r3, #0 80086ae: d177 bne.n 80087a0 { pep = &pdev->ep_out[0]; 80086b0: 68fb ldr r3, [r7, #12] 80086b2: f503 73aa add.w r3, r3, #340 @ 0x154 80086b6: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 80086b8: 68fb ldr r3, [r7, #12] 80086ba: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 80086be: 2b03 cmp r3, #3 80086c0: f040 80a1 bne.w 8008806 { if (pep->rem_length > pep->maxpacket) 80086c4: 693b ldr r3, [r7, #16] 80086c6: 685b ldr r3, [r3, #4] 80086c8: 693a ldr r2, [r7, #16] 80086ca: 8992 ldrh r2, [r2, #12] 80086cc: 4293 cmp r3, r2 80086ce: d91c bls.n 800870a { pep->rem_length -= pep->maxpacket; 80086d0: 693b ldr r3, [r7, #16] 80086d2: 685b ldr r3, [r3, #4] 80086d4: 693a ldr r2, [r7, #16] 80086d6: 8992 ldrh r2, [r2, #12] 80086d8: 1a9a subs r2, r3, r2 80086da: 693b ldr r3, [r7, #16] 80086dc: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 80086de: 693b ldr r3, [r7, #16] 80086e0: 691b ldr r3, [r3, #16] 80086e2: 693a ldr r2, [r7, #16] 80086e4: 8992 ldrh r2, [r2, #12] 80086e6: 441a add r2, r3 80086e8: 693b ldr r3, [r7, #16] 80086ea: 611a str r2, [r3, #16] (void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket)); 80086ec: 693b ldr r3, [r7, #16] 80086ee: 6919 ldr r1, [r3, #16] 80086f0: 693b ldr r3, [r7, #16] 80086f2: 899b ldrh r3, [r3, #12] 80086f4: 461a mov r2, r3 80086f6: 693b ldr r3, [r7, #16] 80086f8: 685b ldr r3, [r3, #4] 80086fa: 4293 cmp r3, r2 80086fc: bf38 it cc 80086fe: 4613 movcc r3, r2 8008700: 461a mov r2, r3 8008702: 68f8 ldr r0, [r7, #12] 8008704: f001 f9b1 bl 8009a6a 8008708: e07d b.n 8008806 } else { /* Find the class ID relative to the current request */ switch (pdev->request.bmRequest & 0x1FU) 800870a: 68fb ldr r3, [r7, #12] 800870c: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008710: f003 031f and.w r3, r3, #31 8008714: 2b02 cmp r3, #2 8008716: d014 beq.n 8008742 8008718: 2b02 cmp r3, #2 800871a: d81d bhi.n 8008758 800871c: 2b00 cmp r3, #0 800871e: d002 beq.n 8008726 8008720: 2b01 cmp r3, #1 8008722: d003 beq.n 800872c 8008724: e018 b.n 8008758 { case USB_REQ_RECIPIENT_DEVICE: /* Device requests must be managed by the first instantiated class (or duplicated by all classes for simplicity) */ idx = 0U; 8008726: 2300 movs r3, #0 8008728: 75bb strb r3, [r7, #22] break; 800872a: e018 b.n 800875e case USB_REQ_RECIPIENT_INTERFACE: idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); 800872c: 68fb ldr r3, [r7, #12] 800872e: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8008732: b2db uxtb r3, r3 8008734: 4619 mov r1, r3 8008736: 68f8 ldr r0, [r7, #12] 8008738: f000 fa6e bl 8008c18 800873c: 4603 mov r3, r0 800873e: 75bb strb r3, [r7, #22] break; 8008740: e00d b.n 800875e case USB_REQ_RECIPIENT_ENDPOINT: idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); 8008742: 68fb ldr r3, [r7, #12] 8008744: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8008748: b2db uxtb r3, r3 800874a: 4619 mov r1, r3 800874c: 68f8 ldr r0, [r7, #12] 800874e: f000 fa70 bl 8008c32 8008752: 4603 mov r3, r0 8008754: 75bb strb r3, [r7, #22] break; 8008756: e002 b.n 800875e default: /* Back to the first class in case of doubt */ idx = 0U; 8008758: 2300 movs r3, #0 800875a: 75bb strb r3, [r7, #22] break; 800875c: bf00 nop } if (idx < USBD_MAX_SUPPORTED_CLASS) 800875e: 7dbb ldrb r3, [r7, #22] 8008760: 2b00 cmp r3, #0 8008762: d119 bne.n 8008798 { /* Setup the class ID and route the request to the relative class function */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008764: 68fb ldr r3, [r7, #12] 8008766: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800876a: b2db uxtb r3, r3 800876c: 2b03 cmp r3, #3 800876e: d113 bne.n 8008798 { if (pdev->pClass[idx]->EP0_RxReady != NULL) 8008770: 7dba ldrb r2, [r7, #22] 8008772: 68fb ldr r3, [r7, #12] 8008774: 32ae adds r2, #174 @ 0xae 8008776: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800877a: 691b ldr r3, [r3, #16] 800877c: 2b00 cmp r3, #0 800877e: d00b beq.n 8008798 { pdev->classId = idx; 8008780: 7dba ldrb r2, [r7, #22] 8008782: 68fb ldr r3, [r7, #12] 8008784: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[idx]->EP0_RxReady(pdev); 8008788: 7dba ldrb r2, [r7, #22] 800878a: 68fb ldr r3, [r7, #12] 800878c: 32ae adds r2, #174 @ 0xae 800878e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008792: 691b ldr r3, [r3, #16] 8008794: 68f8 ldr r0, [r7, #12] 8008796: 4798 blx r3 } } } (void)USBD_CtlSendStatus(pdev); 8008798: 68f8 ldr r0, [r7, #12] 800879a: f001 f977 bl 8009a8c 800879e: e032 b.n 8008806 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); 80087a0: 7afb ldrb r3, [r7, #11] 80087a2: f003 037f and.w r3, r3, #127 @ 0x7f 80087a6: b2db uxtb r3, r3 80087a8: 4619 mov r1, r3 80087aa: 68f8 ldr r0, [r7, #12] 80087ac: f000 fa41 bl 8008c32 80087b0: 4603 mov r3, r0 80087b2: 75bb strb r3, [r7, #22] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 80087b4: 7dbb ldrb r3, [r7, #22] 80087b6: 2bff cmp r3, #255 @ 0xff 80087b8: d025 beq.n 8008806 80087ba: 7dbb ldrb r3, [r7, #22] 80087bc: 2b00 cmp r3, #0 80087be: d122 bne.n 8008806 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 80087c0: 68fb ldr r3, [r7, #12] 80087c2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80087c6: b2db uxtb r3, r3 80087c8: 2b03 cmp r3, #3 80087ca: d117 bne.n 80087fc { if (pdev->pClass[idx]->DataOut != NULL) 80087cc: 7dba ldrb r2, [r7, #22] 80087ce: 68fb ldr r3, [r7, #12] 80087d0: 32ae adds r2, #174 @ 0xae 80087d2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80087d6: 699b ldr r3, [r3, #24] 80087d8: 2b00 cmp r3, #0 80087da: d00f beq.n 80087fc { pdev->classId = idx; 80087dc: 7dba ldrb r2, [r7, #22] 80087de: 68fb ldr r3, [r7, #12] 80087e0: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); 80087e4: 7dba ldrb r2, [r7, #22] 80087e6: 68fb ldr r3, [r7, #12] 80087e8: 32ae adds r2, #174 @ 0xae 80087ea: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80087ee: 699b ldr r3, [r3, #24] 80087f0: 7afa ldrb r2, [r7, #11] 80087f2: 4611 mov r1, r2 80087f4: 68f8 ldr r0, [r7, #12] 80087f6: 4798 blx r3 80087f8: 4603 mov r3, r0 80087fa: 75fb strb r3, [r7, #23] } } if (ret != USBD_OK) 80087fc: 7dfb ldrb r3, [r7, #23] 80087fe: 2b00 cmp r3, #0 8008800: d001 beq.n 8008806 { return ret; 8008802: 7dfb ldrb r3, [r7, #23] 8008804: e000 b.n 8008808 } } } return USBD_OK; 8008806: 2300 movs r3, #0 } 8008808: 4618 mov r0, r3 800880a: 3718 adds r7, #24 800880c: 46bd mov sp, r7 800880e: bd80 pop {r7, pc} 08008810 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8008810: b580 push {r7, lr} 8008812: b086 sub sp, #24 8008814: af00 add r7, sp, #0 8008816: 60f8 str r0, [r7, #12] 8008818: 460b mov r3, r1 800881a: 607a str r2, [r7, #4] 800881c: 72fb strb r3, [r7, #11] USBD_StatusTypeDef ret; uint8_t idx; UNUSED(pdata); if (epnum == 0U) 800881e: 7afb ldrb r3, [r7, #11] 8008820: 2b00 cmp r3, #0 8008822: d178 bne.n 8008916 { pep = &pdev->ep_in[0]; 8008824: 68fb ldr r3, [r7, #12] 8008826: 3314 adds r3, #20 8008828: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 800882a: 68fb ldr r3, [r7, #12] 800882c: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8008830: 2b02 cmp r3, #2 8008832: d163 bne.n 80088fc { if (pep->rem_length > pep->maxpacket) 8008834: 693b ldr r3, [r7, #16] 8008836: 685b ldr r3, [r3, #4] 8008838: 693a ldr r2, [r7, #16] 800883a: 8992 ldrh r2, [r2, #12] 800883c: 4293 cmp r3, r2 800883e: d91c bls.n 800887a { pep->rem_length -= pep->maxpacket; 8008840: 693b ldr r3, [r7, #16] 8008842: 685b ldr r3, [r3, #4] 8008844: 693a ldr r2, [r7, #16] 8008846: 8992 ldrh r2, [r2, #12] 8008848: 1a9a subs r2, r3, r2 800884a: 693b ldr r3, [r7, #16] 800884c: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 800884e: 693b ldr r3, [r7, #16] 8008850: 691b ldr r3, [r3, #16] 8008852: 693a ldr r2, [r7, #16] 8008854: 8992 ldrh r2, [r2, #12] 8008856: 441a add r2, r3 8008858: 693b ldr r3, [r7, #16] 800885a: 611a str r2, [r3, #16] (void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length); 800885c: 693b ldr r3, [r7, #16] 800885e: 6919 ldr r1, [r3, #16] 8008860: 693b ldr r3, [r7, #16] 8008862: 685b ldr r3, [r3, #4] 8008864: 461a mov r2, r3 8008866: 68f8 ldr r0, [r7, #12] 8008868: f001 f8ee bl 8009a48 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 800886c: 2300 movs r3, #0 800886e: 2200 movs r2, #0 8008870: 2100 movs r1, #0 8008872: 68f8 ldr r0, [r7, #12] 8008874: f001 fd2a bl 800a2cc 8008878: e040 b.n 80088fc } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 800887a: 693b ldr r3, [r7, #16] 800887c: 899b ldrh r3, [r3, #12] 800887e: 461a mov r2, r3 8008880: 693b ldr r3, [r7, #16] 8008882: 685b ldr r3, [r3, #4] 8008884: 429a cmp r2, r3 8008886: d11c bne.n 80088c2 (pep->total_length >= pep->maxpacket) && 8008888: 693b ldr r3, [r7, #16] 800888a: 681b ldr r3, [r3, #0] 800888c: 693a ldr r2, [r7, #16] 800888e: 8992 ldrh r2, [r2, #12] if ((pep->maxpacket == pep->rem_length) && 8008890: 4293 cmp r3, r2 8008892: d316 bcc.n 80088c2 (pep->total_length < pdev->ep0_data_len)) 8008894: 693b ldr r3, [r7, #16] 8008896: 681a ldr r2, [r3, #0] 8008898: 68fb ldr r3, [r7, #12] 800889a: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 (pep->total_length >= pep->maxpacket) && 800889e: 429a cmp r2, r3 80088a0: d20f bcs.n 80088c2 { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 80088a2: 2200 movs r2, #0 80088a4: 2100 movs r1, #0 80088a6: 68f8 ldr r0, [r7, #12] 80088a8: f001 f8ce bl 8009a48 pdev->ep0_data_len = 0U; 80088ac: 68fb ldr r3, [r7, #12] 80088ae: 2200 movs r2, #0 80088b0: f8c3 2298 str.w r2, [r3, #664] @ 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 80088b4: 2300 movs r3, #0 80088b6: 2200 movs r2, #0 80088b8: 2100 movs r1, #0 80088ba: 68f8 ldr r0, [r7, #12] 80088bc: f001 fd06 bl 800a2cc 80088c0: e01c b.n 80088fc } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 80088c2: 68fb ldr r3, [r7, #12] 80088c4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80088c8: b2db uxtb r3, r3 80088ca: 2b03 cmp r3, #3 80088cc: d10f bne.n 80088ee { if (pdev->pClass[0]->EP0_TxSent != NULL) 80088ce: 68fb ldr r3, [r7, #12] 80088d0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80088d4: 68db ldr r3, [r3, #12] 80088d6: 2b00 cmp r3, #0 80088d8: d009 beq.n 80088ee { pdev->classId = 0U; 80088da: 68fb ldr r3, [r7, #12] 80088dc: 2200 movs r2, #0 80088de: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[0]->EP0_TxSent(pdev); 80088e2: 68fb ldr r3, [r7, #12] 80088e4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80088e8: 68db ldr r3, [r3, #12] 80088ea: 68f8 ldr r0, [r7, #12] 80088ec: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 80088ee: 2180 movs r1, #128 @ 0x80 80088f0: 68f8 ldr r0, [r7, #12] 80088f2: f001 fc41 bl 800a178 (void)USBD_CtlReceiveStatus(pdev); 80088f6: 68f8 ldr r0, [r7, #12] 80088f8: f001 f8db bl 8009ab2 } } } if (pdev->dev_test_mode != 0U) 80088fc: 68fb ldr r3, [r7, #12] 80088fe: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 8008902: 2b00 cmp r3, #0 8008904: d03a beq.n 800897c { (void)USBD_RunTestMode(pdev); 8008906: 68f8 ldr r0, [r7, #12] 8008908: f7ff fe30 bl 800856c pdev->dev_test_mode = 0U; 800890c: 68fb ldr r3, [r7, #12] 800890e: 2200 movs r2, #0 8008910: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 8008914: e032 b.n 800897c } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); 8008916: 7afb ldrb r3, [r7, #11] 8008918: f063 037f orn r3, r3, #127 @ 0x7f 800891c: b2db uxtb r3, r3 800891e: 4619 mov r1, r3 8008920: 68f8 ldr r0, [r7, #12] 8008922: f000 f986 bl 8008c32 8008926: 4603 mov r3, r0 8008928: 75fb strb r3, [r7, #23] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800892a: 7dfb ldrb r3, [r7, #23] 800892c: 2bff cmp r3, #255 @ 0xff 800892e: d025 beq.n 800897c 8008930: 7dfb ldrb r3, [r7, #23] 8008932: 2b00 cmp r3, #0 8008934: d122 bne.n 800897c { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008936: 68fb ldr r3, [r7, #12] 8008938: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800893c: b2db uxtb r3, r3 800893e: 2b03 cmp r3, #3 8008940: d11c bne.n 800897c { if (pdev->pClass[idx]->DataIn != NULL) 8008942: 7dfa ldrb r2, [r7, #23] 8008944: 68fb ldr r3, [r7, #12] 8008946: 32ae adds r2, #174 @ 0xae 8008948: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800894c: 695b ldr r3, [r3, #20] 800894e: 2b00 cmp r3, #0 8008950: d014 beq.n 800897c { pdev->classId = idx; 8008952: 7dfa ldrb r2, [r7, #23] 8008954: 68fb ldr r3, [r7, #12] 8008956: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); 800895a: 7dfa ldrb r2, [r7, #23] 800895c: 68fb ldr r3, [r7, #12] 800895e: 32ae adds r2, #174 @ 0xae 8008960: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008964: 695b ldr r3, [r3, #20] 8008966: 7afa ldrb r2, [r7, #11] 8008968: 4611 mov r1, r2 800896a: 68f8 ldr r0, [r7, #12] 800896c: 4798 blx r3 800896e: 4603 mov r3, r0 8008970: 75bb strb r3, [r7, #22] if (ret != USBD_OK) 8008972: 7dbb ldrb r3, [r7, #22] 8008974: 2b00 cmp r3, #0 8008976: d001 beq.n 800897c { return ret; 8008978: 7dbb ldrb r3, [r7, #22] 800897a: e000 b.n 800897e } } } } return USBD_OK; 800897c: 2300 movs r3, #0 } 800897e: 4618 mov r0, r3 8008980: 3718 adds r7, #24 8008982: 46bd mov sp, r7 8008984: bd80 pop {r7, pc} 08008986 : * Handle Reset event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 8008986: b580 push {r7, lr} 8008988: b084 sub sp, #16 800898a: af00 add r7, sp, #0 800898c: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 800898e: 2300 movs r3, #0 8008990: 73fb strb r3, [r7, #15] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 8008992: 687b ldr r3, [r7, #4] 8008994: 2201 movs r2, #1 8008996: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->ep0_state = USBD_EP0_IDLE; 800899a: 687b ldr r3, [r7, #4] 800899c: 2200 movs r2, #0 800899e: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->dev_config = 0U; 80089a2: 687b ldr r3, [r7, #4] 80089a4: 2200 movs r2, #0 80089a6: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 80089a8: 687b ldr r3, [r7, #4] 80089aa: 2200 movs r2, #0 80089ac: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 pdev->dev_test_mode = 0U; 80089b0: 687b ldr r3, [r7, #4] 80089b2: 2200 movs r2, #0 80089b4: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 } } } #else if (pdev->pClass[0] != NULL) 80089b8: 687b ldr r3, [r7, #4] 80089ba: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80089be: 2b00 cmp r3, #0 80089c0: d014 beq.n 80089ec { if (pdev->pClass[0]->DeInit != NULL) 80089c2: 687b ldr r3, [r7, #4] 80089c4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80089c8: 685b ldr r3, [r3, #4] 80089ca: 2b00 cmp r3, #0 80089cc: d00e beq.n 80089ec { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) 80089ce: 687b ldr r3, [r7, #4] 80089d0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80089d4: 685b ldr r3, [r3, #4] 80089d6: 687a ldr r2, [r7, #4] 80089d8: 6852 ldr r2, [r2, #4] 80089da: b2d2 uxtb r2, r2 80089dc: 4611 mov r1, r2 80089de: 6878 ldr r0, [r7, #4] 80089e0: 4798 blx r3 80089e2: 4603 mov r3, r0 80089e4: 2b00 cmp r3, #0 80089e6: d001 beq.n 80089ec { ret = USBD_FAIL; 80089e8: 2303 movs r3, #3 80089ea: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 80089ec: 2340 movs r3, #64 @ 0x40 80089ee: 2200 movs r2, #0 80089f0: 2100 movs r1, #0 80089f2: 6878 ldr r0, [r7, #4] 80089f4: f001 fb7b bl 800a0ee pdev->ep_out[0x00U & 0xFU].is_used = 1U; 80089f8: 687b ldr r3, [r7, #4] 80089fa: 2201 movs r2, #1 80089fc: f883 2163 strb.w r2, [r3, #355] @ 0x163 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 8008a00: 687b ldr r3, [r7, #4] 8008a02: 2240 movs r2, #64 @ 0x40 8008a04: f8a3 2160 strh.w r2, [r3, #352] @ 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8008a08: 2340 movs r3, #64 @ 0x40 8008a0a: 2200 movs r2, #0 8008a0c: 2180 movs r1, #128 @ 0x80 8008a0e: 6878 ldr r0, [r7, #4] 8008a10: f001 fb6d bl 800a0ee pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8008a14: 687b ldr r3, [r7, #4] 8008a16: 2201 movs r2, #1 8008a18: f883 2023 strb.w r2, [r3, #35] @ 0x23 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8008a1c: 687b ldr r3, [r7, #4] 8008a1e: 2240 movs r2, #64 @ 0x40 8008a20: 841a strh r2, [r3, #32] return ret; 8008a22: 7bfb ldrb r3, [r7, #15] } 8008a24: 4618 mov r0, r3 8008a26: 3710 adds r7, #16 8008a28: 46bd mov sp, r7 8008a2a: bd80 pop {r7, pc} 08008a2c : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8008a2c: b480 push {r7} 8008a2e: b083 sub sp, #12 8008a30: af00 add r7, sp, #0 8008a32: 6078 str r0, [r7, #4] 8008a34: 460b mov r3, r1 8008a36: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 8008a38: 687b ldr r3, [r7, #4] 8008a3a: 78fa ldrb r2, [r7, #3] 8008a3c: 741a strb r2, [r3, #16] return USBD_OK; 8008a3e: 2300 movs r3, #0 } 8008a40: 4618 mov r0, r3 8008a42: 370c adds r7, #12 8008a44: 46bd mov sp, r7 8008a46: f85d 7b04 ldr.w r7, [sp], #4 8008a4a: 4770 bx lr 08008a4c : * Handle Suspend event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 8008a4c: b480 push {r7} 8008a4e: b083 sub sp, #12 8008a50: af00 add r7, sp, #0 8008a52: 6078 str r0, [r7, #4] if (pdev->dev_state != USBD_STATE_SUSPENDED) 8008a54: 687b ldr r3, [r7, #4] 8008a56: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008a5a: b2db uxtb r3, r3 8008a5c: 2b04 cmp r3, #4 8008a5e: d006 beq.n 8008a6e { pdev->dev_old_state = pdev->dev_state; 8008a60: 687b ldr r3, [r7, #4] 8008a62: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008a66: b2da uxtb r2, r3 8008a68: 687b ldr r3, [r7, #4] 8008a6a: f883 229d strb.w r2, [r3, #669] @ 0x29d } pdev->dev_state = USBD_STATE_SUSPENDED; 8008a6e: 687b ldr r3, [r7, #4] 8008a70: 2204 movs r2, #4 8008a72: f883 229c strb.w r2, [r3, #668] @ 0x29c return USBD_OK; 8008a76: 2300 movs r3, #0 } 8008a78: 4618 mov r0, r3 8008a7a: 370c adds r7, #12 8008a7c: 46bd mov sp, r7 8008a7e: f85d 7b04 ldr.w r7, [sp], #4 8008a82: 4770 bx lr 08008a84 : * Handle Resume event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 8008a84: b480 push {r7} 8008a86: b083 sub sp, #12 8008a88: af00 add r7, sp, #0 8008a8a: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 8008a8c: 687b ldr r3, [r7, #4] 8008a8e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008a92: b2db uxtb r3, r3 8008a94: 2b04 cmp r3, #4 8008a96: d106 bne.n 8008aa6 { pdev->dev_state = pdev->dev_old_state; 8008a98: 687b ldr r3, [r7, #4] 8008a9a: f893 329d ldrb.w r3, [r3, #669] @ 0x29d 8008a9e: b2da uxtb r2, r3 8008aa0: 687b ldr r3, [r7, #4] 8008aa2: f883 229c strb.w r2, [r3, #668] @ 0x29c } return USBD_OK; 8008aa6: 2300 movs r3, #0 } 8008aa8: 4618 mov r0, r3 8008aaa: 370c adds r7, #12 8008aac: 46bd mov sp, r7 8008aae: f85d 7b04 ldr.w r7, [sp], #4 8008ab2: 4770 bx lr 08008ab4 : * Handle SOF event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 8008ab4: b580 push {r7, lr} 8008ab6: b082 sub sp, #8 8008ab8: af00 add r7, sp, #0 8008aba: 6078 str r0, [r7, #4] /* The SOF event can be distributed for all classes that support it */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008abc: 687b ldr r3, [r7, #4] 8008abe: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008ac2: b2db uxtb r3, r3 8008ac4: 2b03 cmp r3, #3 8008ac6: d110 bne.n 8008aea } } } } #else if (pdev->pClass[0] != NULL) 8008ac8: 687b ldr r3, [r7, #4] 8008aca: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008ace: 2b00 cmp r3, #0 8008ad0: d00b beq.n 8008aea { if (pdev->pClass[0]->SOF != NULL) 8008ad2: 687b ldr r3, [r7, #4] 8008ad4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008ad8: 69db ldr r3, [r3, #28] 8008ada: 2b00 cmp r3, #0 8008adc: d005 beq.n 8008aea { (void)pdev->pClass[0]->SOF(pdev); 8008ade: 687b ldr r3, [r7, #4] 8008ae0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008ae4: 69db ldr r3, [r3, #28] 8008ae6: 6878 ldr r0, [r7, #4] 8008ae8: 4798 blx r3 } } #endif /* USE_USBD_COMPOSITE */ } return USBD_OK; 8008aea: 2300 movs r3, #0 } 8008aec: 4618 mov r0, r3 8008aee: 3708 adds r7, #8 8008af0: 46bd mov sp, r7 8008af2: bd80 pop {r7, pc} 08008af4 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8008af4: b580 push {r7, lr} 8008af6: b082 sub sp, #8 8008af8: af00 add r7, sp, #0 8008afa: 6078 str r0, [r7, #4] 8008afc: 460b mov r3, r1 8008afe: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8008b00: 687b ldr r3, [r7, #4] 8008b02: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008b06: 687b ldr r3, [r7, #4] 8008b08: 32ae adds r2, #174 @ 0xae 8008b0a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008b0e: 2b00 cmp r3, #0 8008b10: d101 bne.n 8008b16 { return USBD_FAIL; 8008b12: 2303 movs r3, #3 8008b14: e01c b.n 8008b50 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008b16: 687b ldr r3, [r7, #4] 8008b18: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008b1c: b2db uxtb r3, r3 8008b1e: 2b03 cmp r3, #3 8008b20: d115 bne.n 8008b4e { if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL) 8008b22: 687b ldr r3, [r7, #4] 8008b24: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008b28: 687b ldr r3, [r7, #4] 8008b2a: 32ae adds r2, #174 @ 0xae 8008b2c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008b30: 6a1b ldr r3, [r3, #32] 8008b32: 2b00 cmp r3, #0 8008b34: d00b beq.n 8008b4e { (void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum); 8008b36: 687b ldr r3, [r7, #4] 8008b38: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008b3c: 687b ldr r3, [r7, #4] 8008b3e: 32ae adds r2, #174 @ 0xae 8008b40: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008b44: 6a1b ldr r3, [r3, #32] 8008b46: 78fa ldrb r2, [r7, #3] 8008b48: 4611 mov r1, r2 8008b4a: 6878 ldr r0, [r7, #4] 8008b4c: 4798 blx r3 } } return USBD_OK; 8008b4e: 2300 movs r3, #0 } 8008b50: 4618 mov r0, r3 8008b52: 3708 adds r7, #8 8008b54: 46bd mov sp, r7 8008b56: bd80 pop {r7, pc} 08008b58 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8008b58: b580 push {r7, lr} 8008b5a: b082 sub sp, #8 8008b5c: af00 add r7, sp, #0 8008b5e: 6078 str r0, [r7, #4] 8008b60: 460b mov r3, r1 8008b62: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8008b64: 687b ldr r3, [r7, #4] 8008b66: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008b6a: 687b ldr r3, [r7, #4] 8008b6c: 32ae adds r2, #174 @ 0xae 8008b6e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008b72: 2b00 cmp r3, #0 8008b74: d101 bne.n 8008b7a { return USBD_FAIL; 8008b76: 2303 movs r3, #3 8008b78: e01c b.n 8008bb4 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008b7a: 687b ldr r3, [r7, #4] 8008b7c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008b80: b2db uxtb r3, r3 8008b82: 2b03 cmp r3, #3 8008b84: d115 bne.n 8008bb2 { if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL) 8008b86: 687b ldr r3, [r7, #4] 8008b88: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008b8c: 687b ldr r3, [r7, #4] 8008b8e: 32ae adds r2, #174 @ 0xae 8008b90: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008b94: 6a5b ldr r3, [r3, #36] @ 0x24 8008b96: 2b00 cmp r3, #0 8008b98: d00b beq.n 8008bb2 { (void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum); 8008b9a: 687b ldr r3, [r7, #4] 8008b9c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008ba0: 687b ldr r3, [r7, #4] 8008ba2: 32ae adds r2, #174 @ 0xae 8008ba4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008ba8: 6a5b ldr r3, [r3, #36] @ 0x24 8008baa: 78fa ldrb r2, [r7, #3] 8008bac: 4611 mov r1, r2 8008bae: 6878 ldr r0, [r7, #4] 8008bb0: 4798 blx r3 } } return USBD_OK; 8008bb2: 2300 movs r3, #0 } 8008bb4: 4618 mov r0, r3 8008bb6: 3708 adds r7, #8 8008bb8: 46bd mov sp, r7 8008bba: bd80 pop {r7, pc} 08008bbc : * Handle device connection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { 8008bbc: b480 push {r7} 8008bbe: b083 sub sp, #12 8008bc0: af00 add r7, sp, #0 8008bc2: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8008bc4: 2300 movs r3, #0 } 8008bc6: 4618 mov r0, r3 8008bc8: 370c adds r7, #12 8008bca: 46bd mov sp, r7 8008bcc: f85d 7b04 ldr.w r7, [sp], #4 8008bd0: 4770 bx lr 08008bd2 : * Handle device disconnection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { 8008bd2: b580 push {r7, lr} 8008bd4: b084 sub sp, #16 8008bd6: af00 add r7, sp, #0 8008bd8: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 8008bda: 2300 movs r3, #0 8008bdc: 73fb strb r3, [r7, #15] /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; 8008bde: 687b ldr r3, [r7, #4] 8008be0: 2201 movs r2, #1 8008be2: f883 229c strb.w r2, [r3, #668] @ 0x29c } } } } #else if (pdev->pClass[0] != NULL) 8008be6: 687b ldr r3, [r7, #4] 8008be8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008bec: 2b00 cmp r3, #0 8008bee: d00e beq.n 8008c0e { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U) 8008bf0: 687b ldr r3, [r7, #4] 8008bf2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008bf6: 685b ldr r3, [r3, #4] 8008bf8: 687a ldr r2, [r7, #4] 8008bfa: 6852 ldr r2, [r2, #4] 8008bfc: b2d2 uxtb r2, r2 8008bfe: 4611 mov r1, r2 8008c00: 6878 ldr r0, [r7, #4] 8008c02: 4798 blx r3 8008c04: 4603 mov r3, r0 8008c06: 2b00 cmp r3, #0 8008c08: d001 beq.n 8008c0e { ret = USBD_FAIL; 8008c0a: 2303 movs r3, #3 8008c0c: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ return ret; 8008c0e: 7bfb ldrb r3, [r7, #15] } 8008c10: 4618 mov r0, r3 8008c12: 3710 adds r7, #16 8008c14: 46bd mov sp, r7 8008c16: bd80 pop {r7, pc} 08008c18 : * @param pdev: device instance * @param index : selected interface number * @retval index of the class using the selected interface number. OxFF if no class found. */ uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) { 8008c18: b480 push {r7} 8008c1a: b083 sub sp, #12 8008c1c: af00 add r7, sp, #0 8008c1e: 6078 str r0, [r7, #4] 8008c20: 460b mov r3, r1 8008c22: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8008c24: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8008c26: 4618 mov r0, r3 8008c28: 370c adds r7, #12 8008c2a: 46bd mov sp, r7 8008c2c: f85d 7b04 ldr.w r7, [sp], #4 8008c30: 4770 bx lr 08008c32 : * @param pdev: device instance * @param index : selected endpoint number * @retval index of the class using the selected endpoint number. 0xFF if no class found. */ uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) { 8008c32: b480 push {r7} 8008c34: b083 sub sp, #12 8008c36: af00 add r7, sp, #0 8008c38: 6078 str r0, [r7, #4] 8008c3a: 460b mov r3, r1 8008c3c: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8008c3e: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8008c40: 4618 mov r0, r3 8008c42: 370c adds r7, #12 8008c44: 46bd mov sp, r7 8008c46: f85d 7b04 ldr.w r7, [sp], #4 8008c4a: 4770 bx lr 08008c4c : * @param pConfDesc: pointer to Bos descriptor * @param EpAddr: endpoint address * @retval pointer to video endpoint descriptor */ void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) { 8008c4c: b580 push {r7, lr} 8008c4e: b086 sub sp, #24 8008c50: af00 add r7, sp, #0 8008c52: 6078 str r0, [r7, #4] 8008c54: 460b mov r3, r1 8008c56: 70fb strb r3, [r7, #3] USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; 8008c58: 687b ldr r3, [r7, #4] 8008c5a: 617b str r3, [r7, #20] USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; 8008c5c: 687b ldr r3, [r7, #4] 8008c5e: 60fb str r3, [r7, #12] USBD_EpDescTypeDef *pEpDesc = NULL; 8008c60: 2300 movs r3, #0 8008c62: 613b str r3, [r7, #16] uint16_t ptr; if (desc->wTotalLength > desc->bLength) 8008c64: 68fb ldr r3, [r7, #12] 8008c66: 885b ldrh r3, [r3, #2] 8008c68: b29b uxth r3, r3 8008c6a: 68fa ldr r2, [r7, #12] 8008c6c: 7812 ldrb r2, [r2, #0] 8008c6e: 4293 cmp r3, r2 8008c70: d91f bls.n 8008cb2 { ptr = desc->bLength; 8008c72: 68fb ldr r3, [r7, #12] 8008c74: 781b ldrb r3, [r3, #0] 8008c76: 817b strh r3, [r7, #10] while (ptr < desc->wTotalLength) 8008c78: e013 b.n 8008ca2 { pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); 8008c7a: f107 030a add.w r3, r7, #10 8008c7e: 4619 mov r1, r3 8008c80: 6978 ldr r0, [r7, #20] 8008c82: f000 f81b bl 8008cbc 8008c86: 6178 str r0, [r7, #20] if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) 8008c88: 697b ldr r3, [r7, #20] 8008c8a: 785b ldrb r3, [r3, #1] 8008c8c: 2b05 cmp r3, #5 8008c8e: d108 bne.n 8008ca2 { pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; 8008c90: 697b ldr r3, [r7, #20] 8008c92: 613b str r3, [r7, #16] if (pEpDesc->bEndpointAddress == EpAddr) 8008c94: 693b ldr r3, [r7, #16] 8008c96: 789b ldrb r3, [r3, #2] 8008c98: 78fa ldrb r2, [r7, #3] 8008c9a: 429a cmp r2, r3 8008c9c: d008 beq.n 8008cb0 { break; } else { pEpDesc = NULL; 8008c9e: 2300 movs r3, #0 8008ca0: 613b str r3, [r7, #16] while (ptr < desc->wTotalLength) 8008ca2: 68fb ldr r3, [r7, #12] 8008ca4: 885b ldrh r3, [r3, #2] 8008ca6: b29a uxth r2, r3 8008ca8: 897b ldrh r3, [r7, #10] 8008caa: 429a cmp r2, r3 8008cac: d8e5 bhi.n 8008c7a 8008cae: e000 b.n 8008cb2 break; 8008cb0: bf00 nop } } } } return (void *)pEpDesc; 8008cb2: 693b ldr r3, [r7, #16] } 8008cb4: 4618 mov r0, r3 8008cb6: 3718 adds r7, #24 8008cb8: 46bd mov sp, r7 8008cba: bd80 pop {r7, pc} 08008cbc : * @param buf: Buffer where the descriptor is available * @param ptr: data pointer inside the descriptor * @retval next header */ USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) { 8008cbc: b480 push {r7} 8008cbe: b085 sub sp, #20 8008cc0: af00 add r7, sp, #0 8008cc2: 6078 str r0, [r7, #4] 8008cc4: 6039 str r1, [r7, #0] USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; 8008cc6: 687b ldr r3, [r7, #4] 8008cc8: 60fb str r3, [r7, #12] *ptr += pnext->bLength; 8008cca: 683b ldr r3, [r7, #0] 8008ccc: 881b ldrh r3, [r3, #0] 8008cce: 68fa ldr r2, [r7, #12] 8008cd0: 7812 ldrb r2, [r2, #0] 8008cd2: 4413 add r3, r2 8008cd4: b29a uxth r2, r3 8008cd6: 683b ldr r3, [r7, #0] 8008cd8: 801a strh r2, [r3, #0] pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); 8008cda: 68fb ldr r3, [r7, #12] 8008cdc: 781b ldrb r3, [r3, #0] 8008cde: 461a mov r2, r3 8008ce0: 687b ldr r3, [r7, #4] 8008ce2: 4413 add r3, r2 8008ce4: 60fb str r3, [r7, #12] return (pnext); 8008ce6: 68fb ldr r3, [r7, #12] } 8008ce8: 4618 mov r0, r3 8008cea: 3714 adds r7, #20 8008cec: 46bd mov sp, r7 8008cee: f85d 7b04 ldr.w r7, [sp], #4 8008cf2: 4770 bx lr 08008cf4 : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 8008cf4: b480 push {r7} 8008cf6: b087 sub sp, #28 8008cf8: af00 add r7, sp, #0 8008cfa: 6078 str r0, [r7, #4] uint16_t _SwapVal; uint16_t _Byte1; uint16_t _Byte2; uint8_t *_pbuff = addr; 8008cfc: 687b ldr r3, [r7, #4] 8008cfe: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 8008d00: 697b ldr r3, [r7, #20] 8008d02: 781b ldrb r3, [r3, #0] 8008d04: 827b strh r3, [r7, #18] _pbuff++; 8008d06: 697b ldr r3, [r7, #20] 8008d08: 3301 adds r3, #1 8008d0a: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 8008d0c: 697b ldr r3, [r7, #20] 8008d0e: 781b ldrb r3, [r3, #0] 8008d10: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 8008d12: f9b7 3010 ldrsh.w r3, [r7, #16] 8008d16: 021b lsls r3, r3, #8 8008d18: b21a sxth r2, r3 8008d1a: f9b7 3012 ldrsh.w r3, [r7, #18] 8008d1e: 4313 orrs r3, r2 8008d20: b21b sxth r3, r3 8008d22: 81fb strh r3, [r7, #14] return _SwapVal; 8008d24: 89fb ldrh r3, [r7, #14] } 8008d26: 4618 mov r0, r3 8008d28: 371c adds r7, #28 8008d2a: 46bd mov sp, r7 8008d2c: f85d 7b04 ldr.w r7, [sp], #4 8008d30: 4770 bx lr ... 08008d34 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008d34: b580 push {r7, lr} 8008d36: b084 sub sp, #16 8008d38: af00 add r7, sp, #0 8008d3a: 6078 str r0, [r7, #4] 8008d3c: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8008d3e: 2300 movs r3, #0 8008d40: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8008d42: 683b ldr r3, [r7, #0] 8008d44: 781b ldrb r3, [r3, #0] 8008d46: f003 0360 and.w r3, r3, #96 @ 0x60 8008d4a: 2b40 cmp r3, #64 @ 0x40 8008d4c: d005 beq.n 8008d5a 8008d4e: 2b40 cmp r3, #64 @ 0x40 8008d50: d857 bhi.n 8008e02 8008d52: 2b00 cmp r3, #0 8008d54: d00f beq.n 8008d76 8008d56: 2b20 cmp r3, #32 8008d58: d153 bne.n 8008e02 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); 8008d5a: 687b ldr r3, [r7, #4] 8008d5c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008d60: 687b ldr r3, [r7, #4] 8008d62: 32ae adds r2, #174 @ 0xae 8008d64: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008d68: 689b ldr r3, [r3, #8] 8008d6a: 6839 ldr r1, [r7, #0] 8008d6c: 6878 ldr r0, [r7, #4] 8008d6e: 4798 blx r3 8008d70: 4603 mov r3, r0 8008d72: 73fb strb r3, [r7, #15] break; 8008d74: e04a b.n 8008e0c case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8008d76: 683b ldr r3, [r7, #0] 8008d78: 785b ldrb r3, [r3, #1] 8008d7a: 2b09 cmp r3, #9 8008d7c: d83b bhi.n 8008df6 8008d7e: a201 add r2, pc, #4 @ (adr r2, 8008d84 ) 8008d80: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008d84: 08008dd9 .word 0x08008dd9 8008d88: 08008ded .word 0x08008ded 8008d8c: 08008df7 .word 0x08008df7 8008d90: 08008de3 .word 0x08008de3 8008d94: 08008df7 .word 0x08008df7 8008d98: 08008db7 .word 0x08008db7 8008d9c: 08008dad .word 0x08008dad 8008da0: 08008df7 .word 0x08008df7 8008da4: 08008dcf .word 0x08008dcf 8008da8: 08008dc1 .word 0x08008dc1 { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 8008dac: 6839 ldr r1, [r7, #0] 8008dae: 6878 ldr r0, [r7, #4] 8008db0: f000 fa3e bl 8009230 break; 8008db4: e024 b.n 8008e00 case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 8008db6: 6839 ldr r1, [r7, #0] 8008db8: 6878 ldr r0, [r7, #4] 8008dba: f000 fbcd bl 8009558 break; 8008dbe: e01f b.n 8008e00 case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 8008dc0: 6839 ldr r1, [r7, #0] 8008dc2: 6878 ldr r0, [r7, #4] 8008dc4: f000 fc0c bl 80095e0 8008dc8: 4603 mov r3, r0 8008dca: 73fb strb r3, [r7, #15] break; 8008dcc: e018 b.n 8008e00 case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 8008dce: 6839 ldr r1, [r7, #0] 8008dd0: 6878 ldr r0, [r7, #4] 8008dd2: f000 fcaf bl 8009734 break; 8008dd6: e013 b.n 8008e00 case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 8008dd8: 6839 ldr r1, [r7, #0] 8008dda: 6878 ldr r0, [r7, #4] 8008ddc: f000 fce0 bl 80097a0 break; 8008de0: e00e b.n 8008e00 case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 8008de2: 6839 ldr r1, [r7, #0] 8008de4: 6878 ldr r0, [r7, #4] 8008de6: f000 fd0f bl 8009808 break; 8008dea: e009 b.n 8008e00 case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 8008dec: 6839 ldr r1, [r7, #0] 8008dee: 6878 ldr r0, [r7, #4] 8008df0: f000 fd33 bl 800985a break; 8008df4: e004 b.n 8008e00 default: USBD_CtlError(pdev, req); 8008df6: 6839 ldr r1, [r7, #0] 8008df8: 6878 ldr r0, [r7, #4] 8008dfa: f000 fd8a bl 8009912 break; 8008dfe: bf00 nop } break; 8008e00: e004 b.n 8008e0c default: USBD_CtlError(pdev, req); 8008e02: 6839 ldr r1, [r7, #0] 8008e04: 6878 ldr r0, [r7, #4] 8008e06: f000 fd84 bl 8009912 break; 8008e0a: bf00 nop } return ret; 8008e0c: 7bfb ldrb r3, [r7, #15] } 8008e0e: 4618 mov r0, r3 8008e10: 3710 adds r7, #16 8008e12: 46bd mov sp, r7 8008e14: bd80 pop {r7, pc} 8008e16: bf00 nop 08008e18 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008e18: b580 push {r7, lr} 8008e1a: b084 sub sp, #16 8008e1c: af00 add r7, sp, #0 8008e1e: 6078 str r0, [r7, #4] 8008e20: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8008e22: 2300 movs r3, #0 8008e24: 73fb strb r3, [r7, #15] uint8_t idx; switch (req->bmRequest & USB_REQ_TYPE_MASK) 8008e26: 683b ldr r3, [r7, #0] 8008e28: 781b ldrb r3, [r3, #0] 8008e2a: f003 0360 and.w r3, r3, #96 @ 0x60 8008e2e: 2b40 cmp r3, #64 @ 0x40 8008e30: d005 beq.n 8008e3e 8008e32: 2b40 cmp r3, #64 @ 0x40 8008e34: d852 bhi.n 8008edc 8008e36: 2b00 cmp r3, #0 8008e38: d001 beq.n 8008e3e 8008e3a: 2b20 cmp r3, #32 8008e3c: d14e bne.n 8008edc { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 8008e3e: 687b ldr r3, [r7, #4] 8008e40: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008e44: b2db uxtb r3, r3 8008e46: 3b01 subs r3, #1 8008e48: 2b02 cmp r3, #2 8008e4a: d840 bhi.n 8008ece { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 8008e4c: 683b ldr r3, [r7, #0] 8008e4e: 889b ldrh r3, [r3, #4] 8008e50: b2db uxtb r3, r3 8008e52: 2b01 cmp r3, #1 8008e54: d836 bhi.n 8008ec4 { /* Get the class index relative to this interface */ idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); 8008e56: 683b ldr r3, [r7, #0] 8008e58: 889b ldrh r3, [r3, #4] 8008e5a: b2db uxtb r3, r3 8008e5c: 4619 mov r1, r3 8008e5e: 6878 ldr r0, [r7, #4] 8008e60: f7ff feda bl 8008c18 8008e64: 4603 mov r3, r0 8008e66: 73bb strb r3, [r7, #14] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8008e68: 7bbb ldrb r3, [r7, #14] 8008e6a: 2bff cmp r3, #255 @ 0xff 8008e6c: d01d beq.n 8008eaa 8008e6e: 7bbb ldrb r3, [r7, #14] 8008e70: 2b00 cmp r3, #0 8008e72: d11a bne.n 8008eaa { /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8008e74: 7bba ldrb r2, [r7, #14] 8008e76: 687b ldr r3, [r7, #4] 8008e78: 32ae adds r2, #174 @ 0xae 8008e7a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008e7e: 689b ldr r3, [r3, #8] 8008e80: 2b00 cmp r3, #0 8008e82: d00f beq.n 8008ea4 { pdev->classId = idx; 8008e84: 7bba ldrb r2, [r7, #14] 8008e86: 687b ldr r3, [r7, #4] 8008e88: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 8008e8c: 7bba ldrb r2, [r7, #14] 8008e8e: 687b ldr r3, [r7, #4] 8008e90: 32ae adds r2, #174 @ 0xae 8008e92: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008e96: 689b ldr r3, [r3, #8] 8008e98: 6839 ldr r1, [r7, #0] 8008e9a: 6878 ldr r0, [r7, #4] 8008e9c: 4798 blx r3 8008e9e: 4603 mov r3, r0 8008ea0: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 8008ea2: e004 b.n 8008eae } else { /* should never reach this condition */ ret = USBD_FAIL; 8008ea4: 2303 movs r3, #3 8008ea6: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 8008ea8: e001 b.n 8008eae } } else { /* No relative interface found */ ret = USBD_FAIL; 8008eaa: 2303 movs r3, #3 8008eac: 73fb strb r3, [r7, #15] } if ((req->wLength == 0U) && (ret == USBD_OK)) 8008eae: 683b ldr r3, [r7, #0] 8008eb0: 88db ldrh r3, [r3, #6] 8008eb2: 2b00 cmp r3, #0 8008eb4: d110 bne.n 8008ed8 8008eb6: 7bfb ldrb r3, [r7, #15] 8008eb8: 2b00 cmp r3, #0 8008eba: d10d bne.n 8008ed8 { (void)USBD_CtlSendStatus(pdev); 8008ebc: 6878 ldr r0, [r7, #4] 8008ebe: f000 fde5 bl 8009a8c } else { USBD_CtlError(pdev, req); } break; 8008ec2: e009 b.n 8008ed8 USBD_CtlError(pdev, req); 8008ec4: 6839 ldr r1, [r7, #0] 8008ec6: 6878 ldr r0, [r7, #4] 8008ec8: f000 fd23 bl 8009912 break; 8008ecc: e004 b.n 8008ed8 default: USBD_CtlError(pdev, req); 8008ece: 6839 ldr r1, [r7, #0] 8008ed0: 6878 ldr r0, [r7, #4] 8008ed2: f000 fd1e bl 8009912 break; 8008ed6: e000 b.n 8008eda break; 8008ed8: bf00 nop } break; 8008eda: e004 b.n 8008ee6 default: USBD_CtlError(pdev, req); 8008edc: 6839 ldr r1, [r7, #0] 8008ede: 6878 ldr r0, [r7, #4] 8008ee0: f000 fd17 bl 8009912 break; 8008ee4: bf00 nop } return ret; 8008ee6: 7bfb ldrb r3, [r7, #15] } 8008ee8: 4618 mov r0, r3 8008eea: 3710 adds r7, #16 8008eec: 46bd mov sp, r7 8008eee: bd80 pop {r7, pc} 08008ef0 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008ef0: b580 push {r7, lr} 8008ef2: b084 sub sp, #16 8008ef4: af00 add r7, sp, #0 8008ef6: 6078 str r0, [r7, #4] 8008ef8: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; uint8_t idx; USBD_StatusTypeDef ret = USBD_OK; 8008efa: 2300 movs r3, #0 8008efc: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 8008efe: 683b ldr r3, [r7, #0] 8008f00: 889b ldrh r3, [r3, #4] 8008f02: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8008f04: 683b ldr r3, [r7, #0] 8008f06: 781b ldrb r3, [r3, #0] 8008f08: f003 0360 and.w r3, r3, #96 @ 0x60 8008f0c: 2b40 cmp r3, #64 @ 0x40 8008f0e: d007 beq.n 8008f20 8008f10: 2b40 cmp r3, #64 @ 0x40 8008f12: f200 8181 bhi.w 8009218 8008f16: 2b00 cmp r3, #0 8008f18: d02a beq.n 8008f70 8008f1a: 2b20 cmp r3, #32 8008f1c: f040 817c bne.w 8009218 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: /* Get the class index relative to this endpoint */ idx = USBD_CoreFindEP(pdev, ep_addr); 8008f20: 7bbb ldrb r3, [r7, #14] 8008f22: 4619 mov r1, r3 8008f24: 6878 ldr r0, [r7, #4] 8008f26: f7ff fe84 bl 8008c32 8008f2a: 4603 mov r3, r0 8008f2c: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8008f2e: 7b7b ldrb r3, [r7, #13] 8008f30: 2bff cmp r3, #255 @ 0xff 8008f32: f000 8176 beq.w 8009222 8008f36: 7b7b ldrb r3, [r7, #13] 8008f38: 2b00 cmp r3, #0 8008f3a: f040 8172 bne.w 8009222 { pdev->classId = idx; 8008f3e: 7b7a ldrb r2, [r7, #13] 8008f40: 687b ldr r3, [r7, #4] 8008f42: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8008f46: 7b7a ldrb r2, [r7, #13] 8008f48: 687b ldr r3, [r7, #4] 8008f4a: 32ae adds r2, #174 @ 0xae 8008f4c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008f50: 689b ldr r3, [r3, #8] 8008f52: 2b00 cmp r3, #0 8008f54: f000 8165 beq.w 8009222 { ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); 8008f58: 7b7a ldrb r2, [r7, #13] 8008f5a: 687b ldr r3, [r7, #4] 8008f5c: 32ae adds r2, #174 @ 0xae 8008f5e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008f62: 689b ldr r3, [r3, #8] 8008f64: 6839 ldr r1, [r7, #0] 8008f66: 6878 ldr r0, [r7, #4] 8008f68: 4798 blx r3 8008f6a: 4603 mov r3, r0 8008f6c: 73fb strb r3, [r7, #15] } } break; 8008f6e: e158 b.n 8009222 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8008f70: 683b ldr r3, [r7, #0] 8008f72: 785b ldrb r3, [r3, #1] 8008f74: 2b03 cmp r3, #3 8008f76: d008 beq.n 8008f8a 8008f78: 2b03 cmp r3, #3 8008f7a: f300 8147 bgt.w 800920c 8008f7e: 2b00 cmp r3, #0 8008f80: f000 809b beq.w 80090ba 8008f84: 2b01 cmp r3, #1 8008f86: d03c beq.n 8009002 8008f88: e140 b.n 800920c { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 8008f8a: 687b ldr r3, [r7, #4] 8008f8c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008f90: b2db uxtb r3, r3 8008f92: 2b02 cmp r3, #2 8008f94: d002 beq.n 8008f9c 8008f96: 2b03 cmp r3, #3 8008f98: d016 beq.n 8008fc8 8008f9a: e02c b.n 8008ff6 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8008f9c: 7bbb ldrb r3, [r7, #14] 8008f9e: 2b00 cmp r3, #0 8008fa0: d00d beq.n 8008fbe 8008fa2: 7bbb ldrb r3, [r7, #14] 8008fa4: 2b80 cmp r3, #128 @ 0x80 8008fa6: d00a beq.n 8008fbe { (void)USBD_LL_StallEP(pdev, ep_addr); 8008fa8: 7bbb ldrb r3, [r7, #14] 8008faa: 4619 mov r1, r3 8008fac: 6878 ldr r0, [r7, #4] 8008fae: f001 f8e3 bl 800a178 (void)USBD_LL_StallEP(pdev, 0x80U); 8008fb2: 2180 movs r1, #128 @ 0x80 8008fb4: 6878 ldr r0, [r7, #4] 8008fb6: f001 f8df bl 800a178 8008fba: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8008fbc: e020 b.n 8009000 USBD_CtlError(pdev, req); 8008fbe: 6839 ldr r1, [r7, #0] 8008fc0: 6878 ldr r0, [r7, #4] 8008fc2: f000 fca6 bl 8009912 break; 8008fc6: e01b b.n 8009000 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8008fc8: 683b ldr r3, [r7, #0] 8008fca: 885b ldrh r3, [r3, #2] 8008fcc: 2b00 cmp r3, #0 8008fce: d10e bne.n 8008fee { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 8008fd0: 7bbb ldrb r3, [r7, #14] 8008fd2: 2b00 cmp r3, #0 8008fd4: d00b beq.n 8008fee 8008fd6: 7bbb ldrb r3, [r7, #14] 8008fd8: 2b80 cmp r3, #128 @ 0x80 8008fda: d008 beq.n 8008fee 8008fdc: 683b ldr r3, [r7, #0] 8008fde: 88db ldrh r3, [r3, #6] 8008fe0: 2b00 cmp r3, #0 8008fe2: d104 bne.n 8008fee { (void)USBD_LL_StallEP(pdev, ep_addr); 8008fe4: 7bbb ldrb r3, [r7, #14] 8008fe6: 4619 mov r1, r3 8008fe8: 6878 ldr r0, [r7, #4] 8008fea: f001 f8c5 bl 800a178 } } (void)USBD_CtlSendStatus(pdev); 8008fee: 6878 ldr r0, [r7, #4] 8008ff0: f000 fd4c bl 8009a8c break; 8008ff4: e004 b.n 8009000 default: USBD_CtlError(pdev, req); 8008ff6: 6839 ldr r1, [r7, #0] 8008ff8: 6878 ldr r0, [r7, #4] 8008ffa: f000 fc8a bl 8009912 break; 8008ffe: bf00 nop } break; 8009000: e109 b.n 8009216 case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 8009002: 687b ldr r3, [r7, #4] 8009004: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009008: b2db uxtb r3, r3 800900a: 2b02 cmp r3, #2 800900c: d002 beq.n 8009014 800900e: 2b03 cmp r3, #3 8009010: d016 beq.n 8009040 8009012: e04b b.n 80090ac { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8009014: 7bbb ldrb r3, [r7, #14] 8009016: 2b00 cmp r3, #0 8009018: d00d beq.n 8009036 800901a: 7bbb ldrb r3, [r7, #14] 800901c: 2b80 cmp r3, #128 @ 0x80 800901e: d00a beq.n 8009036 { (void)USBD_LL_StallEP(pdev, ep_addr); 8009020: 7bbb ldrb r3, [r7, #14] 8009022: 4619 mov r1, r3 8009024: 6878 ldr r0, [r7, #4] 8009026: f001 f8a7 bl 800a178 (void)USBD_LL_StallEP(pdev, 0x80U); 800902a: 2180 movs r1, #128 @ 0x80 800902c: 6878 ldr r0, [r7, #4] 800902e: f001 f8a3 bl 800a178 8009032: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8009034: e040 b.n 80090b8 USBD_CtlError(pdev, req); 8009036: 6839 ldr r1, [r7, #0] 8009038: 6878 ldr r0, [r7, #4] 800903a: f000 fc6a bl 8009912 break; 800903e: e03b b.n 80090b8 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8009040: 683b ldr r3, [r7, #0] 8009042: 885b ldrh r3, [r3, #2] 8009044: 2b00 cmp r3, #0 8009046: d136 bne.n 80090b6 { if ((ep_addr & 0x7FU) != 0x00U) 8009048: 7bbb ldrb r3, [r7, #14] 800904a: f003 037f and.w r3, r3, #127 @ 0x7f 800904e: 2b00 cmp r3, #0 8009050: d004 beq.n 800905c { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 8009052: 7bbb ldrb r3, [r7, #14] 8009054: 4619 mov r1, r3 8009056: 6878 ldr r0, [r7, #4] 8009058: f001 f8ad bl 800a1b6 } (void)USBD_CtlSendStatus(pdev); 800905c: 6878 ldr r0, [r7, #4] 800905e: f000 fd15 bl 8009a8c /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ep_addr); 8009062: 7bbb ldrb r3, [r7, #14] 8009064: 4619 mov r1, r3 8009066: 6878 ldr r0, [r7, #4] 8009068: f7ff fde3 bl 8008c32 800906c: 4603 mov r3, r0 800906e: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009070: 7b7b ldrb r3, [r7, #13] 8009072: 2bff cmp r3, #255 @ 0xff 8009074: d01f beq.n 80090b6 8009076: 7b7b ldrb r3, [r7, #13] 8009078: 2b00 cmp r3, #0 800907a: d11c bne.n 80090b6 { pdev->classId = idx; 800907c: 7b7a ldrb r2, [r7, #13] 800907e: 687b ldr r3, [r7, #4] 8009080: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8009084: 7b7a ldrb r2, [r7, #13] 8009086: 687b ldr r3, [r7, #4] 8009088: 32ae adds r2, #174 @ 0xae 800908a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800908e: 689b ldr r3, [r3, #8] 8009090: 2b00 cmp r3, #0 8009092: d010 beq.n 80090b6 { ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 8009094: 7b7a ldrb r2, [r7, #13] 8009096: 687b ldr r3, [r7, #4] 8009098: 32ae adds r2, #174 @ 0xae 800909a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800909e: 689b ldr r3, [r3, #8] 80090a0: 6839 ldr r1, [r7, #0] 80090a2: 6878 ldr r0, [r7, #4] 80090a4: 4798 blx r3 80090a6: 4603 mov r3, r0 80090a8: 73fb strb r3, [r7, #15] } } } break; 80090aa: e004 b.n 80090b6 default: USBD_CtlError(pdev, req); 80090ac: 6839 ldr r1, [r7, #0] 80090ae: 6878 ldr r0, [r7, #4] 80090b0: f000 fc2f bl 8009912 break; 80090b4: e000 b.n 80090b8 break; 80090b6: bf00 nop } break; 80090b8: e0ad b.n 8009216 case USB_REQ_GET_STATUS: switch (pdev->dev_state) 80090ba: 687b ldr r3, [r7, #4] 80090bc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80090c0: b2db uxtb r3, r3 80090c2: 2b02 cmp r3, #2 80090c4: d002 beq.n 80090cc 80090c6: 2b03 cmp r3, #3 80090c8: d033 beq.n 8009132 80090ca: e099 b.n 8009200 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80090cc: 7bbb ldrb r3, [r7, #14] 80090ce: 2b00 cmp r3, #0 80090d0: d007 beq.n 80090e2 80090d2: 7bbb ldrb r3, [r7, #14] 80090d4: 2b80 cmp r3, #128 @ 0x80 80090d6: d004 beq.n 80090e2 { USBD_CtlError(pdev, req); 80090d8: 6839 ldr r1, [r7, #0] 80090da: 6878 ldr r0, [r7, #4] 80090dc: f000 fc19 bl 8009912 break; 80090e0: e093 b.n 800920a } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80090e2: f997 300e ldrsb.w r3, [r7, #14] 80090e6: 2b00 cmp r3, #0 80090e8: da0b bge.n 8009102 80090ea: 7bbb ldrb r3, [r7, #14] 80090ec: f003 027f and.w r2, r3, #127 @ 0x7f 80090f0: 4613 mov r3, r2 80090f2: 009b lsls r3, r3, #2 80090f4: 4413 add r3, r2 80090f6: 009b lsls r3, r3, #2 80090f8: 3310 adds r3, #16 80090fa: 687a ldr r2, [r7, #4] 80090fc: 4413 add r3, r2 80090fe: 3304 adds r3, #4 8009100: e00b b.n 800911a &pdev->ep_out[ep_addr & 0x7FU]; 8009102: 7bbb ldrb r3, [r7, #14] 8009104: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8009108: 4613 mov r3, r2 800910a: 009b lsls r3, r3, #2 800910c: 4413 add r3, r2 800910e: 009b lsls r3, r3, #2 8009110: f503 73a8 add.w r3, r3, #336 @ 0x150 8009114: 687a ldr r2, [r7, #4] 8009116: 4413 add r3, r2 8009118: 3304 adds r3, #4 800911a: 60bb str r3, [r7, #8] pep->status = 0x0000U; 800911c: 68bb ldr r3, [r7, #8] 800911e: 2200 movs r2, #0 8009120: 739a strb r2, [r3, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 8009122: 68bb ldr r3, [r7, #8] 8009124: 330e adds r3, #14 8009126: 2202 movs r2, #2 8009128: 4619 mov r1, r3 800912a: 6878 ldr r0, [r7, #4] 800912c: f000 fc6e bl 8009a0c break; 8009130: e06b b.n 800920a case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 8009132: f997 300e ldrsb.w r3, [r7, #14] 8009136: 2b00 cmp r3, #0 8009138: da11 bge.n 800915e { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 800913a: 7bbb ldrb r3, [r7, #14] 800913c: f003 020f and.w r2, r3, #15 8009140: 6879 ldr r1, [r7, #4] 8009142: 4613 mov r3, r2 8009144: 009b lsls r3, r3, #2 8009146: 4413 add r3, r2 8009148: 009b lsls r3, r3, #2 800914a: 440b add r3, r1 800914c: 3323 adds r3, #35 @ 0x23 800914e: 781b ldrb r3, [r3, #0] 8009150: 2b00 cmp r3, #0 8009152: d117 bne.n 8009184 { USBD_CtlError(pdev, req); 8009154: 6839 ldr r1, [r7, #0] 8009156: 6878 ldr r0, [r7, #4] 8009158: f000 fbdb bl 8009912 break; 800915c: e055 b.n 800920a } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 800915e: 7bbb ldrb r3, [r7, #14] 8009160: f003 020f and.w r2, r3, #15 8009164: 6879 ldr r1, [r7, #4] 8009166: 4613 mov r3, r2 8009168: 009b lsls r3, r3, #2 800916a: 4413 add r3, r2 800916c: 009b lsls r3, r3, #2 800916e: 440b add r3, r1 8009170: f203 1363 addw r3, r3, #355 @ 0x163 8009174: 781b ldrb r3, [r3, #0] 8009176: 2b00 cmp r3, #0 8009178: d104 bne.n 8009184 { USBD_CtlError(pdev, req); 800917a: 6839 ldr r1, [r7, #0] 800917c: 6878 ldr r0, [r7, #4] 800917e: f000 fbc8 bl 8009912 break; 8009182: e042 b.n 800920a } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8009184: f997 300e ldrsb.w r3, [r7, #14] 8009188: 2b00 cmp r3, #0 800918a: da0b bge.n 80091a4 800918c: 7bbb ldrb r3, [r7, #14] 800918e: f003 027f and.w r2, r3, #127 @ 0x7f 8009192: 4613 mov r3, r2 8009194: 009b lsls r3, r3, #2 8009196: 4413 add r3, r2 8009198: 009b lsls r3, r3, #2 800919a: 3310 adds r3, #16 800919c: 687a ldr r2, [r7, #4] 800919e: 4413 add r3, r2 80091a0: 3304 adds r3, #4 80091a2: e00b b.n 80091bc &pdev->ep_out[ep_addr & 0x7FU]; 80091a4: 7bbb ldrb r3, [r7, #14] 80091a6: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80091aa: 4613 mov r3, r2 80091ac: 009b lsls r3, r3, #2 80091ae: 4413 add r3, r2 80091b0: 009b lsls r3, r3, #2 80091b2: f503 73a8 add.w r3, r3, #336 @ 0x150 80091b6: 687a ldr r2, [r7, #4] 80091b8: 4413 add r3, r2 80091ba: 3304 adds r3, #4 80091bc: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 80091be: 7bbb ldrb r3, [r7, #14] 80091c0: 2b00 cmp r3, #0 80091c2: d002 beq.n 80091ca 80091c4: 7bbb ldrb r3, [r7, #14] 80091c6: 2b80 cmp r3, #128 @ 0x80 80091c8: d103 bne.n 80091d2 { pep->status = 0x0000U; 80091ca: 68bb ldr r3, [r7, #8] 80091cc: 2200 movs r2, #0 80091ce: 739a strb r2, [r3, #14] 80091d0: e00e b.n 80091f0 } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 80091d2: 7bbb ldrb r3, [r7, #14] 80091d4: 4619 mov r1, r3 80091d6: 6878 ldr r0, [r7, #4] 80091d8: f001 f80c bl 800a1f4 80091dc: 4603 mov r3, r0 80091de: 2b00 cmp r3, #0 80091e0: d003 beq.n 80091ea { pep->status = 0x0001U; 80091e2: 68bb ldr r3, [r7, #8] 80091e4: 2201 movs r2, #1 80091e6: 739a strb r2, [r3, #14] 80091e8: e002 b.n 80091f0 } else { pep->status = 0x0000U; 80091ea: 68bb ldr r3, [r7, #8] 80091ec: 2200 movs r2, #0 80091ee: 739a strb r2, [r3, #14] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 80091f0: 68bb ldr r3, [r7, #8] 80091f2: 330e adds r3, #14 80091f4: 2202 movs r2, #2 80091f6: 4619 mov r1, r3 80091f8: 6878 ldr r0, [r7, #4] 80091fa: f000 fc07 bl 8009a0c break; 80091fe: e004 b.n 800920a default: USBD_CtlError(pdev, req); 8009200: 6839 ldr r1, [r7, #0] 8009202: 6878 ldr r0, [r7, #4] 8009204: f000 fb85 bl 8009912 break; 8009208: bf00 nop } break; 800920a: e004 b.n 8009216 default: USBD_CtlError(pdev, req); 800920c: 6839 ldr r1, [r7, #0] 800920e: 6878 ldr r0, [r7, #4] 8009210: f000 fb7f bl 8009912 break; 8009214: bf00 nop } break; 8009216: e005 b.n 8009224 default: USBD_CtlError(pdev, req); 8009218: 6839 ldr r1, [r7, #0] 800921a: 6878 ldr r0, [r7, #4] 800921c: f000 fb79 bl 8009912 break; 8009220: e000 b.n 8009224 break; 8009222: bf00 nop } return ret; 8009224: 7bfb ldrb r3, [r7, #15] } 8009226: 4618 mov r0, r3 8009228: 3710 adds r7, #16 800922a: 46bd mov sp, r7 800922c: bd80 pop {r7, pc} ... 08009230 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009230: b580 push {r7, lr} 8009232: b084 sub sp, #16 8009234: af00 add r7, sp, #0 8009236: 6078 str r0, [r7, #4] 8009238: 6039 str r1, [r7, #0] uint16_t len = 0U; 800923a: 2300 movs r3, #0 800923c: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 800923e: 2300 movs r3, #0 8009240: 60fb str r3, [r7, #12] uint8_t err = 0U; 8009242: 2300 movs r3, #0 8009244: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 8009246: 683b ldr r3, [r7, #0] 8009248: 885b ldrh r3, [r3, #2] 800924a: 0a1b lsrs r3, r3, #8 800924c: b29b uxth r3, r3 800924e: 3b01 subs r3, #1 8009250: 2b0e cmp r3, #14 8009252: f200 8152 bhi.w 80094fa 8009256: a201 add r2, pc, #4 @ (adr r2, 800925c ) 8009258: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800925c: 080092cd .word 0x080092cd 8009260: 080092e5 .word 0x080092e5 8009264: 08009325 .word 0x08009325 8009268: 080094fb .word 0x080094fb 800926c: 080094fb .word 0x080094fb 8009270: 0800949b .word 0x0800949b 8009274: 080094c7 .word 0x080094c7 8009278: 080094fb .word 0x080094fb 800927c: 080094fb .word 0x080094fb 8009280: 080094fb .word 0x080094fb 8009284: 080094fb .word 0x080094fb 8009288: 080094fb .word 0x080094fb 800928c: 080094fb .word 0x080094fb 8009290: 080094fb .word 0x080094fb 8009294: 08009299 .word 0x08009299 { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) 8009298: 687b ldr r3, [r7, #4] 800929a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800929e: 69db ldr r3, [r3, #28] 80092a0: 2b00 cmp r3, #0 80092a2: d00b beq.n 80092bc { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); 80092a4: 687b ldr r3, [r7, #4] 80092a6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80092aa: 69db ldr r3, [r3, #28] 80092ac: 687a ldr r2, [r7, #4] 80092ae: 7c12 ldrb r2, [r2, #16] 80092b0: f107 0108 add.w r1, r7, #8 80092b4: 4610 mov r0, r2 80092b6: 4798 blx r3 80092b8: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80092ba: e126 b.n 800950a USBD_CtlError(pdev, req); 80092bc: 6839 ldr r1, [r7, #0] 80092be: 6878 ldr r0, [r7, #4] 80092c0: f000 fb27 bl 8009912 err++; 80092c4: 7afb ldrb r3, [r7, #11] 80092c6: 3301 adds r3, #1 80092c8: 72fb strb r3, [r7, #11] break; 80092ca: e11e b.n 800950a #endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 80092cc: 687b ldr r3, [r7, #4] 80092ce: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80092d2: 681b ldr r3, [r3, #0] 80092d4: 687a ldr r2, [r7, #4] 80092d6: 7c12 ldrb r2, [r2, #16] 80092d8: f107 0108 add.w r1, r7, #8 80092dc: 4610 mov r0, r2 80092de: 4798 blx r3 80092e0: 60f8 str r0, [r7, #12] break; 80092e2: e112 b.n 800950a case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 80092e4: 687b ldr r3, [r7, #4] 80092e6: 7c1b ldrb r3, [r3, #16] 80092e8: 2b00 cmp r3, #0 80092ea: d10d bne.n 8009308 pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); 80092ec: 687b ldr r3, [r7, #4] 80092ee: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80092f2: 6a9b ldr r3, [r3, #40] @ 0x28 80092f4: f107 0208 add.w r2, r7, #8 80092f8: 4610 mov r0, r2 80092fa: 4798 blx r3 80092fc: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 80092fe: 68fb ldr r3, [r7, #12] 8009300: 3301 adds r3, #1 8009302: 2202 movs r2, #2 8009304: 701a strb r2, [r3, #0] { pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 8009306: e100 b.n 800950a pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); 8009308: 687b ldr r3, [r7, #4] 800930a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800930e: 6adb ldr r3, [r3, #44] @ 0x2c 8009310: f107 0208 add.w r2, r7, #8 8009314: 4610 mov r0, r2 8009316: 4798 blx r3 8009318: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800931a: 68fb ldr r3, [r7, #12] 800931c: 3301 adds r3, #1 800931e: 2202 movs r2, #2 8009320: 701a strb r2, [r3, #0] break; 8009322: e0f2 b.n 800950a case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 8009324: 683b ldr r3, [r7, #0] 8009326: 885b ldrh r3, [r3, #2] 8009328: b2db uxtb r3, r3 800932a: 2b05 cmp r3, #5 800932c: f200 80ac bhi.w 8009488 8009330: a201 add r2, pc, #4 @ (adr r2, 8009338 ) 8009332: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009336: bf00 nop 8009338: 08009351 .word 0x08009351 800933c: 08009385 .word 0x08009385 8009340: 080093b9 .word 0x080093b9 8009344: 080093ed .word 0x080093ed 8009348: 08009421 .word 0x08009421 800934c: 08009455 .word 0x08009455 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 8009350: 687b ldr r3, [r7, #4] 8009352: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009356: 685b ldr r3, [r3, #4] 8009358: 2b00 cmp r3, #0 800935a: d00b beq.n 8009374 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 800935c: 687b ldr r3, [r7, #4] 800935e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009362: 685b ldr r3, [r3, #4] 8009364: 687a ldr r2, [r7, #4] 8009366: 7c12 ldrb r2, [r2, #16] 8009368: f107 0108 add.w r1, r7, #8 800936c: 4610 mov r0, r2 800936e: 4798 blx r3 8009370: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009372: e091 b.n 8009498 USBD_CtlError(pdev, req); 8009374: 6839 ldr r1, [r7, #0] 8009376: 6878 ldr r0, [r7, #4] 8009378: f000 facb bl 8009912 err++; 800937c: 7afb ldrb r3, [r7, #11] 800937e: 3301 adds r3, #1 8009380: 72fb strb r3, [r7, #11] break; 8009382: e089 b.n 8009498 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 8009384: 687b ldr r3, [r7, #4] 8009386: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800938a: 689b ldr r3, [r3, #8] 800938c: 2b00 cmp r3, #0 800938e: d00b beq.n 80093a8 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 8009390: 687b ldr r3, [r7, #4] 8009392: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009396: 689b ldr r3, [r3, #8] 8009398: 687a ldr r2, [r7, #4] 800939a: 7c12 ldrb r2, [r2, #16] 800939c: f107 0108 add.w r1, r7, #8 80093a0: 4610 mov r0, r2 80093a2: 4798 blx r3 80093a4: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80093a6: e077 b.n 8009498 USBD_CtlError(pdev, req); 80093a8: 6839 ldr r1, [r7, #0] 80093aa: 6878 ldr r0, [r7, #4] 80093ac: f000 fab1 bl 8009912 err++; 80093b0: 7afb ldrb r3, [r7, #11] 80093b2: 3301 adds r3, #1 80093b4: 72fb strb r3, [r7, #11] break; 80093b6: e06f b.n 8009498 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 80093b8: 687b ldr r3, [r7, #4] 80093ba: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80093be: 68db ldr r3, [r3, #12] 80093c0: 2b00 cmp r3, #0 80093c2: d00b beq.n 80093dc { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 80093c4: 687b ldr r3, [r7, #4] 80093c6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80093ca: 68db ldr r3, [r3, #12] 80093cc: 687a ldr r2, [r7, #4] 80093ce: 7c12 ldrb r2, [r2, #16] 80093d0: f107 0108 add.w r1, r7, #8 80093d4: 4610 mov r0, r2 80093d6: 4798 blx r3 80093d8: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80093da: e05d b.n 8009498 USBD_CtlError(pdev, req); 80093dc: 6839 ldr r1, [r7, #0] 80093de: 6878 ldr r0, [r7, #4] 80093e0: f000 fa97 bl 8009912 err++; 80093e4: 7afb ldrb r3, [r7, #11] 80093e6: 3301 adds r3, #1 80093e8: 72fb strb r3, [r7, #11] break; 80093ea: e055 b.n 8009498 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 80093ec: 687b ldr r3, [r7, #4] 80093ee: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80093f2: 691b ldr r3, [r3, #16] 80093f4: 2b00 cmp r3, #0 80093f6: d00b beq.n 8009410 { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 80093f8: 687b ldr r3, [r7, #4] 80093fa: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80093fe: 691b ldr r3, [r3, #16] 8009400: 687a ldr r2, [r7, #4] 8009402: 7c12 ldrb r2, [r2, #16] 8009404: f107 0108 add.w r1, r7, #8 8009408: 4610 mov r0, r2 800940a: 4798 blx r3 800940c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800940e: e043 b.n 8009498 USBD_CtlError(pdev, req); 8009410: 6839 ldr r1, [r7, #0] 8009412: 6878 ldr r0, [r7, #4] 8009414: f000 fa7d bl 8009912 err++; 8009418: 7afb ldrb r3, [r7, #11] 800941a: 3301 adds r3, #1 800941c: 72fb strb r3, [r7, #11] break; 800941e: e03b b.n 8009498 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 8009420: 687b ldr r3, [r7, #4] 8009422: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009426: 695b ldr r3, [r3, #20] 8009428: 2b00 cmp r3, #0 800942a: d00b beq.n 8009444 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 800942c: 687b ldr r3, [r7, #4] 800942e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009432: 695b ldr r3, [r3, #20] 8009434: 687a ldr r2, [r7, #4] 8009436: 7c12 ldrb r2, [r2, #16] 8009438: f107 0108 add.w r1, r7, #8 800943c: 4610 mov r0, r2 800943e: 4798 blx r3 8009440: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009442: e029 b.n 8009498 USBD_CtlError(pdev, req); 8009444: 6839 ldr r1, [r7, #0] 8009446: 6878 ldr r0, [r7, #4] 8009448: f000 fa63 bl 8009912 err++; 800944c: 7afb ldrb r3, [r7, #11] 800944e: 3301 adds r3, #1 8009450: 72fb strb r3, [r7, #11] break; 8009452: e021 b.n 8009498 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 8009454: 687b ldr r3, [r7, #4] 8009456: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800945a: 699b ldr r3, [r3, #24] 800945c: 2b00 cmp r3, #0 800945e: d00b beq.n 8009478 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 8009460: 687b ldr r3, [r7, #4] 8009462: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009466: 699b ldr r3, [r3, #24] 8009468: 687a ldr r2, [r7, #4] 800946a: 7c12 ldrb r2, [r2, #16] 800946c: f107 0108 add.w r1, r7, #8 8009470: 4610 mov r0, r2 8009472: 4798 blx r3 8009474: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009476: e00f b.n 8009498 USBD_CtlError(pdev, req); 8009478: 6839 ldr r1, [r7, #0] 800947a: 6878 ldr r0, [r7, #4] 800947c: f000 fa49 bl 8009912 err++; 8009480: 7afb ldrb r3, [r7, #11] 8009482: 3301 adds r3, #1 8009484: 72fb strb r3, [r7, #11] break; 8009486: e007 b.n 8009498 err++; } #endif /* USBD_SUPPORT_USER_STRING_DESC */ #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 8009488: 6839 ldr r1, [r7, #0] 800948a: 6878 ldr r0, [r7, #4] 800948c: f000 fa41 bl 8009912 err++; 8009490: 7afb ldrb r3, [r7, #11] 8009492: 3301 adds r3, #1 8009494: 72fb strb r3, [r7, #11] #endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ break; 8009496: bf00 nop } break; 8009498: e037 b.n 800950a case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 800949a: 687b ldr r3, [r7, #4] 800949c: 7c1b ldrb r3, [r3, #16] 800949e: 2b00 cmp r3, #0 80094a0: d109 bne.n 80094b6 pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); 80094a2: 687b ldr r3, [r7, #4] 80094a4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80094a8: 6b5b ldr r3, [r3, #52] @ 0x34 80094aa: f107 0208 add.w r2, r7, #8 80094ae: 4610 mov r0, r2 80094b0: 4798 blx r3 80094b2: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80094b4: e029 b.n 800950a USBD_CtlError(pdev, req); 80094b6: 6839 ldr r1, [r7, #0] 80094b8: 6878 ldr r0, [r7, #4] 80094ba: f000 fa2a bl 8009912 err++; 80094be: 7afb ldrb r3, [r7, #11] 80094c0: 3301 adds r3, #1 80094c2: 72fb strb r3, [r7, #11] break; 80094c4: e021 b.n 800950a case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 80094c6: 687b ldr r3, [r7, #4] 80094c8: 7c1b ldrb r3, [r3, #16] 80094ca: 2b00 cmp r3, #0 80094cc: d10d bne.n 80094ea pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); 80094ce: 687b ldr r3, [r7, #4] 80094d0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80094d4: 6b1b ldr r3, [r3, #48] @ 0x30 80094d6: f107 0208 add.w r2, r7, #8 80094da: 4610 mov r0, r2 80094dc: 4798 blx r3 80094de: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 80094e0: 68fb ldr r3, [r7, #12] 80094e2: 3301 adds r3, #1 80094e4: 2207 movs r2, #7 80094e6: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 80094e8: e00f b.n 800950a USBD_CtlError(pdev, req); 80094ea: 6839 ldr r1, [r7, #0] 80094ec: 6878 ldr r0, [r7, #4] 80094ee: f000 fa10 bl 8009912 err++; 80094f2: 7afb ldrb r3, [r7, #11] 80094f4: 3301 adds r3, #1 80094f6: 72fb strb r3, [r7, #11] break; 80094f8: e007 b.n 800950a default: USBD_CtlError(pdev, req); 80094fa: 6839 ldr r1, [r7, #0] 80094fc: 6878 ldr r0, [r7, #4] 80094fe: f000 fa08 bl 8009912 err++; 8009502: 7afb ldrb r3, [r7, #11] 8009504: 3301 adds r3, #1 8009506: 72fb strb r3, [r7, #11] break; 8009508: bf00 nop } if (err != 0U) 800950a: 7afb ldrb r3, [r7, #11] 800950c: 2b00 cmp r3, #0 800950e: d11e bne.n 800954e { return; } if (req->wLength != 0U) 8009510: 683b ldr r3, [r7, #0] 8009512: 88db ldrh r3, [r3, #6] 8009514: 2b00 cmp r3, #0 8009516: d016 beq.n 8009546 { if (len != 0U) 8009518: 893b ldrh r3, [r7, #8] 800951a: 2b00 cmp r3, #0 800951c: d00e beq.n 800953c { len = MIN(len, req->wLength); 800951e: 683b ldr r3, [r7, #0] 8009520: 88da ldrh r2, [r3, #6] 8009522: 893b ldrh r3, [r7, #8] 8009524: 4293 cmp r3, r2 8009526: bf28 it cs 8009528: 4613 movcs r3, r2 800952a: b29b uxth r3, r3 800952c: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 800952e: 893b ldrh r3, [r7, #8] 8009530: 461a mov r2, r3 8009532: 68f9 ldr r1, [r7, #12] 8009534: 6878 ldr r0, [r7, #4] 8009536: f000 fa69 bl 8009a0c 800953a: e009 b.n 8009550 } else { USBD_CtlError(pdev, req); 800953c: 6839 ldr r1, [r7, #0] 800953e: 6878 ldr r0, [r7, #4] 8009540: f000 f9e7 bl 8009912 8009544: e004 b.n 8009550 } } else { (void)USBD_CtlSendStatus(pdev); 8009546: 6878 ldr r0, [r7, #4] 8009548: f000 faa0 bl 8009a8c 800954c: e000 b.n 8009550 return; 800954e: bf00 nop } } 8009550: 3710 adds r7, #16 8009552: 46bd mov sp, r7 8009554: bd80 pop {r7, pc} 8009556: bf00 nop 08009558 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009558: b580 push {r7, lr} 800955a: b084 sub sp, #16 800955c: af00 add r7, sp, #0 800955e: 6078 str r0, [r7, #4] 8009560: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 8009562: 683b ldr r3, [r7, #0] 8009564: 889b ldrh r3, [r3, #4] 8009566: 2b00 cmp r3, #0 8009568: d131 bne.n 80095ce 800956a: 683b ldr r3, [r7, #0] 800956c: 88db ldrh r3, [r3, #6] 800956e: 2b00 cmp r3, #0 8009570: d12d bne.n 80095ce 8009572: 683b ldr r3, [r7, #0] 8009574: 885b ldrh r3, [r3, #2] 8009576: 2b7f cmp r3, #127 @ 0x7f 8009578: d829 bhi.n 80095ce { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 800957a: 683b ldr r3, [r7, #0] 800957c: 885b ldrh r3, [r3, #2] 800957e: b2db uxtb r3, r3 8009580: f003 037f and.w r3, r3, #127 @ 0x7f 8009584: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009586: 687b ldr r3, [r7, #4] 8009588: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800958c: b2db uxtb r3, r3 800958e: 2b03 cmp r3, #3 8009590: d104 bne.n 800959c { USBD_CtlError(pdev, req); 8009592: 6839 ldr r1, [r7, #0] 8009594: 6878 ldr r0, [r7, #4] 8009596: f000 f9bc bl 8009912 if (pdev->dev_state == USBD_STATE_CONFIGURED) 800959a: e01d b.n 80095d8 } else { pdev->dev_address = dev_addr; 800959c: 687b ldr r3, [r7, #4] 800959e: 7bfa ldrb r2, [r7, #15] 80095a0: f883 229e strb.w r2, [r3, #670] @ 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 80095a4: 7bfb ldrb r3, [r7, #15] 80095a6: 4619 mov r1, r3 80095a8: 6878 ldr r0, [r7, #4] 80095aa: f000 fe4f bl 800a24c (void)USBD_CtlSendStatus(pdev); 80095ae: 6878 ldr r0, [r7, #4] 80095b0: f000 fa6c bl 8009a8c if (dev_addr != 0U) 80095b4: 7bfb ldrb r3, [r7, #15] 80095b6: 2b00 cmp r3, #0 80095b8: d004 beq.n 80095c4 { pdev->dev_state = USBD_STATE_ADDRESSED; 80095ba: 687b ldr r3, [r7, #4] 80095bc: 2202 movs r2, #2 80095be: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 80095c2: e009 b.n 80095d8 } else { pdev->dev_state = USBD_STATE_DEFAULT; 80095c4: 687b ldr r3, [r7, #4] 80095c6: 2201 movs r2, #1 80095c8: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 80095cc: e004 b.n 80095d8 } } } else { USBD_CtlError(pdev, req); 80095ce: 6839 ldr r1, [r7, #0] 80095d0: 6878 ldr r0, [r7, #4] 80095d2: f000 f99e bl 8009912 } } 80095d6: bf00 nop 80095d8: bf00 nop 80095da: 3710 adds r7, #16 80095dc: 46bd mov sp, r7 80095de: bd80 pop {r7, pc} 080095e0 : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80095e0: b580 push {r7, lr} 80095e2: b084 sub sp, #16 80095e4: af00 add r7, sp, #0 80095e6: 6078 str r0, [r7, #4] 80095e8: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 80095ea: 2300 movs r3, #0 80095ec: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 80095ee: 683b ldr r3, [r7, #0] 80095f0: 885b ldrh r3, [r3, #2] 80095f2: b2da uxtb r2, r3 80095f4: 4b4e ldr r3, [pc, #312] @ (8009730 ) 80095f6: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 80095f8: 4b4d ldr r3, [pc, #308] @ (8009730 ) 80095fa: 781b ldrb r3, [r3, #0] 80095fc: 2b01 cmp r3, #1 80095fe: d905 bls.n 800960c { USBD_CtlError(pdev, req); 8009600: 6839 ldr r1, [r7, #0] 8009602: 6878 ldr r0, [r7, #4] 8009604: f000 f985 bl 8009912 return USBD_FAIL; 8009608: 2303 movs r3, #3 800960a: e08c b.n 8009726 } switch (pdev->dev_state) 800960c: 687b ldr r3, [r7, #4] 800960e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009612: b2db uxtb r3, r3 8009614: 2b02 cmp r3, #2 8009616: d002 beq.n 800961e 8009618: 2b03 cmp r3, #3 800961a: d029 beq.n 8009670 800961c: e075 b.n 800970a { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 800961e: 4b44 ldr r3, [pc, #272] @ (8009730 ) 8009620: 781b ldrb r3, [r3, #0] 8009622: 2b00 cmp r3, #0 8009624: d020 beq.n 8009668 { pdev->dev_config = cfgidx; 8009626: 4b42 ldr r3, [pc, #264] @ (8009730 ) 8009628: 781b ldrb r3, [r3, #0] 800962a: 461a mov r2, r3 800962c: 687b ldr r3, [r7, #4] 800962e: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8009630: 4b3f ldr r3, [pc, #252] @ (8009730 ) 8009632: 781b ldrb r3, [r3, #0] 8009634: 4619 mov r1, r3 8009636: 6878 ldr r0, [r7, #4] 8009638: f7fe ffa3 bl 8008582 800963c: 4603 mov r3, r0 800963e: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8009640: 7bfb ldrb r3, [r7, #15] 8009642: 2b00 cmp r3, #0 8009644: d008 beq.n 8009658 { USBD_CtlError(pdev, req); 8009646: 6839 ldr r1, [r7, #0] 8009648: 6878 ldr r0, [r7, #4] 800964a: f000 f962 bl 8009912 pdev->dev_state = USBD_STATE_ADDRESSED; 800964e: 687b ldr r3, [r7, #4] 8009650: 2202 movs r2, #2 8009652: f883 229c strb.w r2, [r3, #668] @ 0x29c } else { (void)USBD_CtlSendStatus(pdev); } break; 8009656: e065 b.n 8009724 (void)USBD_CtlSendStatus(pdev); 8009658: 6878 ldr r0, [r7, #4] 800965a: f000 fa17 bl 8009a8c pdev->dev_state = USBD_STATE_CONFIGURED; 800965e: 687b ldr r3, [r7, #4] 8009660: 2203 movs r2, #3 8009662: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8009666: e05d b.n 8009724 (void)USBD_CtlSendStatus(pdev); 8009668: 6878 ldr r0, [r7, #4] 800966a: f000 fa0f bl 8009a8c break; 800966e: e059 b.n 8009724 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 8009670: 4b2f ldr r3, [pc, #188] @ (8009730 ) 8009672: 781b ldrb r3, [r3, #0] 8009674: 2b00 cmp r3, #0 8009676: d112 bne.n 800969e { pdev->dev_state = USBD_STATE_ADDRESSED; 8009678: 687b ldr r3, [r7, #4] 800967a: 2202 movs r2, #2 800967c: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->dev_config = cfgidx; 8009680: 4b2b ldr r3, [pc, #172] @ (8009730 ) 8009682: 781b ldrb r3, [r3, #0] 8009684: 461a mov r2, r3 8009686: 687b ldr r3, [r7, #4] 8009688: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 800968a: 4b29 ldr r3, [pc, #164] @ (8009730 ) 800968c: 781b ldrb r3, [r3, #0] 800968e: 4619 mov r1, r3 8009690: 6878 ldr r0, [r7, #4] 8009692: f7fe ff92 bl 80085ba (void)USBD_CtlSendStatus(pdev); 8009696: 6878 ldr r0, [r7, #4] 8009698: f000 f9f8 bl 8009a8c } else { (void)USBD_CtlSendStatus(pdev); } break; 800969c: e042 b.n 8009724 else if (cfgidx != pdev->dev_config) 800969e: 4b24 ldr r3, [pc, #144] @ (8009730 ) 80096a0: 781b ldrb r3, [r3, #0] 80096a2: 461a mov r2, r3 80096a4: 687b ldr r3, [r7, #4] 80096a6: 685b ldr r3, [r3, #4] 80096a8: 429a cmp r2, r3 80096aa: d02a beq.n 8009702 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 80096ac: 687b ldr r3, [r7, #4] 80096ae: 685b ldr r3, [r3, #4] 80096b0: b2db uxtb r3, r3 80096b2: 4619 mov r1, r3 80096b4: 6878 ldr r0, [r7, #4] 80096b6: f7fe ff80 bl 80085ba pdev->dev_config = cfgidx; 80096ba: 4b1d ldr r3, [pc, #116] @ (8009730 ) 80096bc: 781b ldrb r3, [r3, #0] 80096be: 461a mov r2, r3 80096c0: 687b ldr r3, [r7, #4] 80096c2: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 80096c4: 4b1a ldr r3, [pc, #104] @ (8009730 ) 80096c6: 781b ldrb r3, [r3, #0] 80096c8: 4619 mov r1, r3 80096ca: 6878 ldr r0, [r7, #4] 80096cc: f7fe ff59 bl 8008582 80096d0: 4603 mov r3, r0 80096d2: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 80096d4: 7bfb ldrb r3, [r7, #15] 80096d6: 2b00 cmp r3, #0 80096d8: d00f beq.n 80096fa USBD_CtlError(pdev, req); 80096da: 6839 ldr r1, [r7, #0] 80096dc: 6878 ldr r0, [r7, #4] 80096de: f000 f918 bl 8009912 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 80096e2: 687b ldr r3, [r7, #4] 80096e4: 685b ldr r3, [r3, #4] 80096e6: b2db uxtb r3, r3 80096e8: 4619 mov r1, r3 80096ea: 6878 ldr r0, [r7, #4] 80096ec: f7fe ff65 bl 80085ba pdev->dev_state = USBD_STATE_ADDRESSED; 80096f0: 687b ldr r3, [r7, #4] 80096f2: 2202 movs r2, #2 80096f4: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 80096f8: e014 b.n 8009724 (void)USBD_CtlSendStatus(pdev); 80096fa: 6878 ldr r0, [r7, #4] 80096fc: f000 f9c6 bl 8009a8c break; 8009700: e010 b.n 8009724 (void)USBD_CtlSendStatus(pdev); 8009702: 6878 ldr r0, [r7, #4] 8009704: f000 f9c2 bl 8009a8c break; 8009708: e00c b.n 8009724 default: USBD_CtlError(pdev, req); 800970a: 6839 ldr r1, [r7, #0] 800970c: 6878 ldr r0, [r7, #4] 800970e: f000 f900 bl 8009912 (void)USBD_ClrClassConfig(pdev, cfgidx); 8009712: 4b07 ldr r3, [pc, #28] @ (8009730 ) 8009714: 781b ldrb r3, [r3, #0] 8009716: 4619 mov r1, r3 8009718: 6878 ldr r0, [r7, #4] 800971a: f7fe ff4e bl 80085ba ret = USBD_FAIL; 800971e: 2303 movs r3, #3 8009720: 73fb strb r3, [r7, #15] break; 8009722: bf00 nop } return ret; 8009724: 7bfb ldrb r3, [r7, #15] } 8009726: 4618 mov r0, r3 8009728: 3710 adds r7, #16 800972a: 46bd mov sp, r7 800972c: bd80 pop {r7, pc} 800972e: bf00 nop 8009730: 200006f8 .word 0x200006f8 08009734 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009734: b580 push {r7, lr} 8009736: b082 sub sp, #8 8009738: af00 add r7, sp, #0 800973a: 6078 str r0, [r7, #4] 800973c: 6039 str r1, [r7, #0] if (req->wLength != 1U) 800973e: 683b ldr r3, [r7, #0] 8009740: 88db ldrh r3, [r3, #6] 8009742: 2b01 cmp r3, #1 8009744: d004 beq.n 8009750 { USBD_CtlError(pdev, req); 8009746: 6839 ldr r1, [r7, #0] 8009748: 6878 ldr r0, [r7, #4] 800974a: f000 f8e2 bl 8009912 default: USBD_CtlError(pdev, req); break; } } } 800974e: e023 b.n 8009798 switch (pdev->dev_state) 8009750: 687b ldr r3, [r7, #4] 8009752: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009756: b2db uxtb r3, r3 8009758: 2b02 cmp r3, #2 800975a: dc02 bgt.n 8009762 800975c: 2b00 cmp r3, #0 800975e: dc03 bgt.n 8009768 8009760: e015 b.n 800978e 8009762: 2b03 cmp r3, #3 8009764: d00b beq.n 800977e 8009766: e012 b.n 800978e pdev->dev_default_config = 0U; 8009768: 687b ldr r3, [r7, #4] 800976a: 2200 movs r2, #0 800976c: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 800976e: 687b ldr r3, [r7, #4] 8009770: 3308 adds r3, #8 8009772: 2201 movs r2, #1 8009774: 4619 mov r1, r3 8009776: 6878 ldr r0, [r7, #4] 8009778: f000 f948 bl 8009a0c break; 800977c: e00c b.n 8009798 (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 800977e: 687b ldr r3, [r7, #4] 8009780: 3304 adds r3, #4 8009782: 2201 movs r2, #1 8009784: 4619 mov r1, r3 8009786: 6878 ldr r0, [r7, #4] 8009788: f000 f940 bl 8009a0c break; 800978c: e004 b.n 8009798 USBD_CtlError(pdev, req); 800978e: 6839 ldr r1, [r7, #0] 8009790: 6878 ldr r0, [r7, #4] 8009792: f000 f8be bl 8009912 break; 8009796: bf00 nop } 8009798: bf00 nop 800979a: 3708 adds r7, #8 800979c: 46bd mov sp, r7 800979e: bd80 pop {r7, pc} 080097a0 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80097a0: b580 push {r7, lr} 80097a2: b082 sub sp, #8 80097a4: af00 add r7, sp, #0 80097a6: 6078 str r0, [r7, #4] 80097a8: 6039 str r1, [r7, #0] switch (pdev->dev_state) 80097aa: 687b ldr r3, [r7, #4] 80097ac: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80097b0: b2db uxtb r3, r3 80097b2: 3b01 subs r3, #1 80097b4: 2b02 cmp r3, #2 80097b6: d81e bhi.n 80097f6 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 80097b8: 683b ldr r3, [r7, #0] 80097ba: 88db ldrh r3, [r3, #6] 80097bc: 2b02 cmp r3, #2 80097be: d004 beq.n 80097ca { USBD_CtlError(pdev, req); 80097c0: 6839 ldr r1, [r7, #0] 80097c2: 6878 ldr r0, [r7, #4] 80097c4: f000 f8a5 bl 8009912 break; 80097c8: e01a b.n 8009800 } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 80097ca: 687b ldr r3, [r7, #4] 80097cc: 2201 movs r2, #1 80097ce: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif /* USBD_SELF_POWERED */ if (pdev->dev_remote_wakeup != 0U) 80097d0: 687b ldr r3, [r7, #4] 80097d2: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 80097d6: 2b00 cmp r3, #0 80097d8: d005 beq.n 80097e6 { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 80097da: 687b ldr r3, [r7, #4] 80097dc: 68db ldr r3, [r3, #12] 80097de: f043 0202 orr.w r2, r3, #2 80097e2: 687b ldr r3, [r7, #4] 80097e4: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 80097e6: 687b ldr r3, [r7, #4] 80097e8: 330c adds r3, #12 80097ea: 2202 movs r2, #2 80097ec: 4619 mov r1, r3 80097ee: 6878 ldr r0, [r7, #4] 80097f0: f000 f90c bl 8009a0c break; 80097f4: e004 b.n 8009800 default: USBD_CtlError(pdev, req); 80097f6: 6839 ldr r1, [r7, #0] 80097f8: 6878 ldr r0, [r7, #4] 80097fa: f000 f88a bl 8009912 break; 80097fe: bf00 nop } } 8009800: bf00 nop 8009802: 3708 adds r7, #8 8009804: 46bd mov sp, r7 8009806: bd80 pop {r7, pc} 08009808 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009808: b580 push {r7, lr} 800980a: b082 sub sp, #8 800980c: af00 add r7, sp, #0 800980e: 6078 str r0, [r7, #4] 8009810: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8009812: 683b ldr r3, [r7, #0] 8009814: 885b ldrh r3, [r3, #2] 8009816: 2b01 cmp r3, #1 8009818: d107 bne.n 800982a { pdev->dev_remote_wakeup = 1U; 800981a: 687b ldr r3, [r7, #4] 800981c: 2201 movs r2, #1 800981e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8009822: 6878 ldr r0, [r7, #4] 8009824: f000 f932 bl 8009a8c } else { USBD_CtlError(pdev, req); } } 8009828: e013 b.n 8009852 else if (req->wValue == USB_FEATURE_TEST_MODE) 800982a: 683b ldr r3, [r7, #0] 800982c: 885b ldrh r3, [r3, #2] 800982e: 2b02 cmp r3, #2 8009830: d10b bne.n 800984a pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); 8009832: 683b ldr r3, [r7, #0] 8009834: 889b ldrh r3, [r3, #4] 8009836: 0a1b lsrs r3, r3, #8 8009838: b29b uxth r3, r3 800983a: b2da uxtb r2, r3 800983c: 687b ldr r3, [r7, #4] 800983e: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 (void)USBD_CtlSendStatus(pdev); 8009842: 6878 ldr r0, [r7, #4] 8009844: f000 f922 bl 8009a8c } 8009848: e003 b.n 8009852 USBD_CtlError(pdev, req); 800984a: 6839 ldr r1, [r7, #0] 800984c: 6878 ldr r0, [r7, #4] 800984e: f000 f860 bl 8009912 } 8009852: bf00 nop 8009854: 3708 adds r7, #8 8009856: 46bd mov sp, r7 8009858: bd80 pop {r7, pc} 0800985a : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800985a: b580 push {r7, lr} 800985c: b082 sub sp, #8 800985e: af00 add r7, sp, #0 8009860: 6078 str r0, [r7, #4] 8009862: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8009864: 687b ldr r3, [r7, #4] 8009866: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800986a: b2db uxtb r3, r3 800986c: 3b01 subs r3, #1 800986e: 2b02 cmp r3, #2 8009870: d80b bhi.n 800988a { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8009872: 683b ldr r3, [r7, #0] 8009874: 885b ldrh r3, [r3, #2] 8009876: 2b01 cmp r3, #1 8009878: d10c bne.n 8009894 { pdev->dev_remote_wakeup = 0U; 800987a: 687b ldr r3, [r7, #4] 800987c: 2200 movs r2, #0 800987e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8009882: 6878 ldr r0, [r7, #4] 8009884: f000 f902 bl 8009a8c } break; 8009888: e004 b.n 8009894 default: USBD_CtlError(pdev, req); 800988a: 6839 ldr r1, [r7, #0] 800988c: 6878 ldr r0, [r7, #4] 800988e: f000 f840 bl 8009912 break; 8009892: e000 b.n 8009896 break; 8009894: bf00 nop } } 8009896: bf00 nop 8009898: 3708 adds r7, #8 800989a: 46bd mov sp, r7 800989c: bd80 pop {r7, pc} 0800989e : * @param req: usb request * @param pdata: setup data pointer * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 800989e: b580 push {r7, lr} 80098a0: b084 sub sp, #16 80098a2: af00 add r7, sp, #0 80098a4: 6078 str r0, [r7, #4] 80098a6: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 80098a8: 683b ldr r3, [r7, #0] 80098aa: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 80098ac: 68fb ldr r3, [r7, #12] 80098ae: 781a ldrb r2, [r3, #0] 80098b0: 687b ldr r3, [r7, #4] 80098b2: 701a strb r2, [r3, #0] pbuff++; 80098b4: 68fb ldr r3, [r7, #12] 80098b6: 3301 adds r3, #1 80098b8: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 80098ba: 68fb ldr r3, [r7, #12] 80098bc: 781a ldrb r2, [r3, #0] 80098be: 687b ldr r3, [r7, #4] 80098c0: 705a strb r2, [r3, #1] pbuff++; 80098c2: 68fb ldr r3, [r7, #12] 80098c4: 3301 adds r3, #1 80098c6: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 80098c8: 68f8 ldr r0, [r7, #12] 80098ca: f7ff fa13 bl 8008cf4 80098ce: 4603 mov r3, r0 80098d0: 461a mov r2, r3 80098d2: 687b ldr r3, [r7, #4] 80098d4: 805a strh r2, [r3, #2] pbuff++; 80098d6: 68fb ldr r3, [r7, #12] 80098d8: 3301 adds r3, #1 80098da: 60fb str r3, [r7, #12] pbuff++; 80098dc: 68fb ldr r3, [r7, #12] 80098de: 3301 adds r3, #1 80098e0: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 80098e2: 68f8 ldr r0, [r7, #12] 80098e4: f7ff fa06 bl 8008cf4 80098e8: 4603 mov r3, r0 80098ea: 461a mov r2, r3 80098ec: 687b ldr r3, [r7, #4] 80098ee: 809a strh r2, [r3, #4] pbuff++; 80098f0: 68fb ldr r3, [r7, #12] 80098f2: 3301 adds r3, #1 80098f4: 60fb str r3, [r7, #12] pbuff++; 80098f6: 68fb ldr r3, [r7, #12] 80098f8: 3301 adds r3, #1 80098fa: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 80098fc: 68f8 ldr r0, [r7, #12] 80098fe: f7ff f9f9 bl 8008cf4 8009902: 4603 mov r3, r0 8009904: 461a mov r2, r3 8009906: 687b ldr r3, [r7, #4] 8009908: 80da strh r2, [r3, #6] } 800990a: bf00 nop 800990c: 3710 adds r7, #16 800990e: 46bd mov sp, r7 8009910: bd80 pop {r7, pc} 08009912 : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009912: b580 push {r7, lr} 8009914: b082 sub sp, #8 8009916: af00 add r7, sp, #0 8009918: 6078 str r0, [r7, #4] 800991a: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 800991c: 2180 movs r1, #128 @ 0x80 800991e: 6878 ldr r0, [r7, #4] 8009920: f000 fc2a bl 800a178 (void)USBD_LL_StallEP(pdev, 0U); 8009924: 2100 movs r1, #0 8009926: 6878 ldr r0, [r7, #4] 8009928: f000 fc26 bl 800a178 } 800992c: bf00 nop 800992e: 3708 adds r7, #8 8009930: 46bd mov sp, r7 8009932: bd80 pop {r7, pc} 08009934 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 8009934: b580 push {r7, lr} 8009936: b086 sub sp, #24 8009938: af00 add r7, sp, #0 800993a: 60f8 str r0, [r7, #12] 800993c: 60b9 str r1, [r7, #8] 800993e: 607a str r2, [r7, #4] uint8_t idx = 0U; 8009940: 2300 movs r3, #0 8009942: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 8009944: 68fb ldr r3, [r7, #12] 8009946: 2b00 cmp r3, #0 8009948: d042 beq.n 80099d0 { return; } pdesc = desc; 800994a: 68fb ldr r3, [r7, #12] 800994c: 613b str r3, [r7, #16] *len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U); 800994e: 6938 ldr r0, [r7, #16] 8009950: f000 f842 bl 80099d8 8009954: 4603 mov r3, r0 8009956: 3301 adds r3, #1 8009958: 005b lsls r3, r3, #1 800995a: f5b3 7f00 cmp.w r3, #512 @ 0x200 800995e: d808 bhi.n 8009972 8009960: 6938 ldr r0, [r7, #16] 8009962: f000 f839 bl 80099d8 8009966: 4603 mov r3, r0 8009968: 3301 adds r3, #1 800996a: b29b uxth r3, r3 800996c: 005b lsls r3, r3, #1 800996e: b29a uxth r2, r3 8009970: e001 b.n 8009976 8009972: f44f 7200 mov.w r2, #512 @ 0x200 8009976: 687b ldr r3, [r7, #4] 8009978: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 800997a: 7dfb ldrb r3, [r7, #23] 800997c: 68ba ldr r2, [r7, #8] 800997e: 4413 add r3, r2 8009980: 687a ldr r2, [r7, #4] 8009982: 7812 ldrb r2, [r2, #0] 8009984: 701a strb r2, [r3, #0] idx++; 8009986: 7dfb ldrb r3, [r7, #23] 8009988: 3301 adds r3, #1 800998a: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 800998c: 7dfb ldrb r3, [r7, #23] 800998e: 68ba ldr r2, [r7, #8] 8009990: 4413 add r3, r2 8009992: 2203 movs r2, #3 8009994: 701a strb r2, [r3, #0] idx++; 8009996: 7dfb ldrb r3, [r7, #23] 8009998: 3301 adds r3, #1 800999a: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 800999c: e013 b.n 80099c6 { unicode[idx] = *pdesc; 800999e: 7dfb ldrb r3, [r7, #23] 80099a0: 68ba ldr r2, [r7, #8] 80099a2: 4413 add r3, r2 80099a4: 693a ldr r2, [r7, #16] 80099a6: 7812 ldrb r2, [r2, #0] 80099a8: 701a strb r2, [r3, #0] pdesc++; 80099aa: 693b ldr r3, [r7, #16] 80099ac: 3301 adds r3, #1 80099ae: 613b str r3, [r7, #16] idx++; 80099b0: 7dfb ldrb r3, [r7, #23] 80099b2: 3301 adds r3, #1 80099b4: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 80099b6: 7dfb ldrb r3, [r7, #23] 80099b8: 68ba ldr r2, [r7, #8] 80099ba: 4413 add r3, r2 80099bc: 2200 movs r2, #0 80099be: 701a strb r2, [r3, #0] idx++; 80099c0: 7dfb ldrb r3, [r7, #23] 80099c2: 3301 adds r3, #1 80099c4: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 80099c6: 693b ldr r3, [r7, #16] 80099c8: 781b ldrb r3, [r3, #0] 80099ca: 2b00 cmp r3, #0 80099cc: d1e7 bne.n 800999e 80099ce: e000 b.n 80099d2 return; 80099d0: bf00 nop } } 80099d2: 3718 adds r7, #24 80099d4: 46bd mov sp, r7 80099d6: bd80 pop {r7, pc} 080099d8 : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 80099d8: b480 push {r7} 80099da: b085 sub sp, #20 80099dc: af00 add r7, sp, #0 80099de: 6078 str r0, [r7, #4] uint8_t len = 0U; 80099e0: 2300 movs r3, #0 80099e2: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 80099e4: 687b ldr r3, [r7, #4] 80099e6: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 80099e8: e005 b.n 80099f6 { len++; 80099ea: 7bfb ldrb r3, [r7, #15] 80099ec: 3301 adds r3, #1 80099ee: 73fb strb r3, [r7, #15] pbuff++; 80099f0: 68bb ldr r3, [r7, #8] 80099f2: 3301 adds r3, #1 80099f4: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 80099f6: 68bb ldr r3, [r7, #8] 80099f8: 781b ldrb r3, [r3, #0] 80099fa: 2b00 cmp r3, #0 80099fc: d1f5 bne.n 80099ea } return len; 80099fe: 7bfb ldrb r3, [r7, #15] } 8009a00: 4618 mov r0, r3 8009a02: 3714 adds r7, #20 8009a04: 46bd mov sp, r7 8009a06: f85d 7b04 ldr.w r7, [sp], #4 8009a0a: 4770 bx lr 08009a0c : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8009a0c: b580 push {r7, lr} 8009a0e: b084 sub sp, #16 8009a10: af00 add r7, sp, #0 8009a12: 60f8 str r0, [r7, #12] 8009a14: 60b9 str r1, [r7, #8] 8009a16: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 8009a18: 68fb ldr r3, [r7, #12] 8009a1a: 2202 movs r2, #2 8009a1c: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_in[0].total_length = len; 8009a20: 68fb ldr r3, [r7, #12] 8009a22: 687a ldr r2, [r7, #4] 8009a24: 615a str r2, [r3, #20] pdev->ep_in[0].pbuffer = pbuf; 8009a26: 68fb ldr r3, [r7, #12] 8009a28: 68ba ldr r2, [r7, #8] 8009a2a: 625a str r2, [r3, #36] @ 0x24 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 8009a2c: 68fb ldr r3, [r7, #12] 8009a2e: 687a ldr r2, [r7, #4] 8009a30: 619a str r2, [r3, #24] #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8009a32: 687b ldr r3, [r7, #4] 8009a34: 68ba ldr r2, [r7, #8] 8009a36: 2100 movs r1, #0 8009a38: 68f8 ldr r0, [r7, #12] 8009a3a: f000 fc26 bl 800a28a return USBD_OK; 8009a3e: 2300 movs r3, #0 } 8009a40: 4618 mov r0, r3 8009a42: 3710 adds r7, #16 8009a44: 46bd mov sp, r7 8009a46: bd80 pop {r7, pc} 08009a48 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8009a48: b580 push {r7, lr} 8009a4a: b084 sub sp, #16 8009a4c: af00 add r7, sp, #0 8009a4e: 60f8 str r0, [r7, #12] 8009a50: 60b9 str r1, [r7, #8] 8009a52: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8009a54: 687b ldr r3, [r7, #4] 8009a56: 68ba ldr r2, [r7, #8] 8009a58: 2100 movs r1, #0 8009a5a: 68f8 ldr r0, [r7, #12] 8009a5c: f000 fc15 bl 800a28a return USBD_OK; 8009a60: 2300 movs r3, #0 } 8009a62: 4618 mov r0, r3 8009a64: 3710 adds r7, #16 8009a66: 46bd mov sp, r7 8009a68: bd80 pop {r7, pc} 08009a6a : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8009a6a: b580 push {r7, lr} 8009a6c: b084 sub sp, #16 8009a6e: af00 add r7, sp, #0 8009a70: 60f8 str r0, [r7, #12] 8009a72: 60b9 str r1, [r7, #8] 8009a74: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 8009a76: 687b ldr r3, [r7, #4] 8009a78: 68ba ldr r2, [r7, #8] 8009a7a: 2100 movs r1, #0 8009a7c: 68f8 ldr r0, [r7, #12] 8009a7e: f000 fc25 bl 800a2cc return USBD_OK; 8009a82: 2300 movs r3, #0 } 8009a84: 4618 mov r0, r3 8009a86: 3710 adds r7, #16 8009a88: 46bd mov sp, r7 8009a8a: bd80 pop {r7, pc} 08009a8c : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 8009a8c: b580 push {r7, lr} 8009a8e: b082 sub sp, #8 8009a90: af00 add r7, sp, #0 8009a92: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 8009a94: 687b ldr r3, [r7, #4] 8009a96: 2204 movs r2, #4 8009a98: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 8009a9c: 2300 movs r3, #0 8009a9e: 2200 movs r2, #0 8009aa0: 2100 movs r1, #0 8009aa2: 6878 ldr r0, [r7, #4] 8009aa4: f000 fbf1 bl 800a28a return USBD_OK; 8009aa8: 2300 movs r3, #0 } 8009aaa: 4618 mov r0, r3 8009aac: 3708 adds r7, #8 8009aae: 46bd mov sp, r7 8009ab0: bd80 pop {r7, pc} 08009ab2 : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 8009ab2: b580 push {r7, lr} 8009ab4: b082 sub sp, #8 8009ab6: af00 add r7, sp, #0 8009ab8: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 8009aba: 687b ldr r3, [r7, #4] 8009abc: 2205 movs r2, #5 8009abe: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8009ac2: 2300 movs r3, #0 8009ac4: 2200 movs r2, #0 8009ac6: 2100 movs r1, #0 8009ac8: 6878 ldr r0, [r7, #4] 8009aca: f000 fbff bl 800a2cc return USBD_OK; 8009ace: 2300 movs r3, #0 } 8009ad0: 4618 mov r0, r3 8009ad2: 3708 adds r7, #8 8009ad4: 46bd mov sp, r7 8009ad6: bd80 pop {r7, pc} 08009ad8 : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 8009ad8: b580 push {r7, lr} 8009ada: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) 8009adc: 2200 movs r2, #0 8009ade: 490e ldr r1, [pc, #56] @ (8009b18 ) 8009ae0: 480e ldr r0, [pc, #56] @ (8009b1c ) 8009ae2: f7fe fcd1 bl 8008488 8009ae6: 4603 mov r3, r0 8009ae8: 2b00 cmp r3, #0 8009aea: d001 beq.n 8009af0 { Error_Handler(); 8009aec: f7f7 f86c bl 8000bc8 } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) 8009af0: 490b ldr r1, [pc, #44] @ (8009b20 ) 8009af2: 480a ldr r0, [pc, #40] @ (8009b1c ) 8009af4: f7fe fcf8 bl 80084e8 8009af8: 4603 mov r3, r0 8009afa: 2b00 cmp r3, #0 8009afc: d001 beq.n 8009b02 { Error_Handler(); 8009afe: f7f7 f863 bl 8000bc8 } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) 8009b02: 4806 ldr r0, [pc, #24] @ (8009b1c ) 8009b04: f7fe fd26 bl 8008554 8009b08: 4603 mov r3, r0 8009b0a: 2b00 cmp r3, #0 8009b0c: d001 beq.n 8009b12 { Error_Handler(); 8009b0e: f7f7 f85b bl 8000bc8 } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 8009b12: bf00 nop 8009b14: bd80 pop {r7, pc} 8009b16: bf00 nop 8009b18: 2000015c .word 0x2000015c 8009b1c: 200006fc .word 0x200006fc 8009b20: 2000009c .word 0x2000009c 08009b24 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009b24: b480 push {r7} 8009b26: b083 sub sp, #12 8009b28: af00 add r7, sp, #0 8009b2a: 4603 mov r3, r0 8009b2c: 6039 str r1, [r7, #0] 8009b2e: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_DeviceDesc); 8009b30: 683b ldr r3, [r7, #0] 8009b32: 2212 movs r2, #18 8009b34: 801a strh r2, [r3, #0] return USBD_FS_DeviceDesc; 8009b36: 4b03 ldr r3, [pc, #12] @ (8009b44 ) } 8009b38: 4618 mov r0, r3 8009b3a: 370c adds r7, #12 8009b3c: 46bd mov sp, r7 8009b3e: f85d 7b04 ldr.w r7, [sp], #4 8009b42: 4770 bx lr 8009b44: 2000017c .word 0x2000017c 08009b48 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009b48: b480 push {r7} 8009b4a: b083 sub sp, #12 8009b4c: af00 add r7, sp, #0 8009b4e: 4603 mov r3, r0 8009b50: 6039 str r1, [r7, #0] 8009b52: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 8009b54: 683b ldr r3, [r7, #0] 8009b56: 2204 movs r2, #4 8009b58: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 8009b5a: 4b03 ldr r3, [pc, #12] @ (8009b68 ) } 8009b5c: 4618 mov r0, r3 8009b5e: 370c adds r7, #12 8009b60: 46bd mov sp, r7 8009b62: f85d 7b04 ldr.w r7, [sp], #4 8009b66: 4770 bx lr 8009b68: 2000019c .word 0x2000019c 08009b6c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009b6c: b580 push {r7, lr} 8009b6e: b082 sub sp, #8 8009b70: af00 add r7, sp, #0 8009b72: 4603 mov r3, r0 8009b74: 6039 str r1, [r7, #0] 8009b76: 71fb strb r3, [r7, #7] if(speed == 0) 8009b78: 79fb ldrb r3, [r7, #7] 8009b7a: 2b00 cmp r3, #0 8009b7c: d105 bne.n 8009b8a { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 8009b7e: 683a ldr r2, [r7, #0] 8009b80: 4907 ldr r1, [pc, #28] @ (8009ba0 ) 8009b82: 4808 ldr r0, [pc, #32] @ (8009ba4 ) 8009b84: f7ff fed6 bl 8009934 8009b88: e004 b.n 8009b94 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 8009b8a: 683a ldr r2, [r7, #0] 8009b8c: 4904 ldr r1, [pc, #16] @ (8009ba0 ) 8009b8e: 4805 ldr r0, [pc, #20] @ (8009ba4 ) 8009b90: f7ff fed0 bl 8009934 } return USBD_StrDesc; 8009b94: 4b02 ldr r3, [pc, #8] @ (8009ba0 ) } 8009b96: 4618 mov r0, r3 8009b98: 3708 adds r7, #8 8009b9a: 46bd mov sp, r7 8009b9c: bd80 pop {r7, pc} 8009b9e: bf00 nop 8009ba0: 200009d8 .word 0x200009d8 8009ba4: 0800a4a4 .word 0x0800a4a4 08009ba8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009ba8: b580 push {r7, lr} 8009baa: b082 sub sp, #8 8009bac: af00 add r7, sp, #0 8009bae: 4603 mov r3, r0 8009bb0: 6039 str r1, [r7, #0] 8009bb2: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 8009bb4: 683a ldr r2, [r7, #0] 8009bb6: 4904 ldr r1, [pc, #16] @ (8009bc8 ) 8009bb8: 4804 ldr r0, [pc, #16] @ (8009bcc ) 8009bba: f7ff febb bl 8009934 return USBD_StrDesc; 8009bbe: 4b02 ldr r3, [pc, #8] @ (8009bc8 ) } 8009bc0: 4618 mov r0, r3 8009bc2: 3708 adds r7, #8 8009bc4: 46bd mov sp, r7 8009bc6: bd80 pop {r7, pc} 8009bc8: 200009d8 .word 0x200009d8 8009bcc: 0800a4b8 .word 0x0800a4b8 08009bd0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009bd0: b580 push {r7, lr} 8009bd2: b082 sub sp, #8 8009bd4: af00 add r7, sp, #0 8009bd6: 4603 mov r3, r0 8009bd8: 6039 str r1, [r7, #0] 8009bda: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 8009bdc: 683b ldr r3, [r7, #0] 8009bde: 221a movs r2, #26 8009be0: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 8009be2: f000 f855 bl 8009c90 /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ /* USER CODE END USBD_FS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 8009be6: 4b02 ldr r3, [pc, #8] @ (8009bf0 ) } 8009be8: 4618 mov r0, r3 8009bea: 3708 adds r7, #8 8009bec: 46bd mov sp, r7 8009bee: bd80 pop {r7, pc} 8009bf0: 200001a0 .word 0x200001a0 08009bf4 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009bf4: b580 push {r7, lr} 8009bf6: b082 sub sp, #8 8009bf8: af00 add r7, sp, #0 8009bfa: 4603 mov r3, r0 8009bfc: 6039 str r1, [r7, #0] 8009bfe: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 8009c00: 79fb ldrb r3, [r7, #7] 8009c02: 2b00 cmp r3, #0 8009c04: d105 bne.n 8009c12 { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 8009c06: 683a ldr r2, [r7, #0] 8009c08: 4907 ldr r1, [pc, #28] @ (8009c28 ) 8009c0a: 4808 ldr r0, [pc, #32] @ (8009c2c ) 8009c0c: f7ff fe92 bl 8009934 8009c10: e004 b.n 8009c1c } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 8009c12: 683a ldr r2, [r7, #0] 8009c14: 4904 ldr r1, [pc, #16] @ (8009c28 ) 8009c16: 4805 ldr r0, [pc, #20] @ (8009c2c ) 8009c18: f7ff fe8c bl 8009934 } return USBD_StrDesc; 8009c1c: 4b02 ldr r3, [pc, #8] @ (8009c28 ) } 8009c1e: 4618 mov r0, r3 8009c20: 3708 adds r7, #8 8009c22: 46bd mov sp, r7 8009c24: bd80 pop {r7, pc} 8009c26: bf00 nop 8009c28: 200009d8 .word 0x200009d8 8009c2c: 0800a4c4 .word 0x0800a4c4 08009c30 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009c30: b580 push {r7, lr} 8009c32: b082 sub sp, #8 8009c34: af00 add r7, sp, #0 8009c36: 4603 mov r3, r0 8009c38: 6039 str r1, [r7, #0] 8009c3a: 71fb strb r3, [r7, #7] if(speed == 0) 8009c3c: 79fb ldrb r3, [r7, #7] 8009c3e: 2b00 cmp r3, #0 8009c40: d105 bne.n 8009c4e { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 8009c42: 683a ldr r2, [r7, #0] 8009c44: 4907 ldr r1, [pc, #28] @ (8009c64 ) 8009c46: 4808 ldr r0, [pc, #32] @ (8009c68 ) 8009c48: f7ff fe74 bl 8009934 8009c4c: e004 b.n 8009c58 } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 8009c4e: 683a ldr r2, [r7, #0] 8009c50: 4904 ldr r1, [pc, #16] @ (8009c64 ) 8009c52: 4805 ldr r0, [pc, #20] @ (8009c68 ) 8009c54: f7ff fe6e bl 8009934 } return USBD_StrDesc; 8009c58: 4b02 ldr r3, [pc, #8] @ (8009c64 ) } 8009c5a: 4618 mov r0, r3 8009c5c: 3708 adds r7, #8 8009c5e: 46bd mov sp, r7 8009c60: bd80 pop {r7, pc} 8009c62: bf00 nop 8009c64: 200009d8 .word 0x200009d8 8009c68: 0800a4d0 .word 0x0800a4d0 08009c6c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8009c6c: b480 push {r7} 8009c6e: b083 sub sp, #12 8009c70: af00 add r7, sp, #0 8009c72: 4603 mov r3, r0 8009c74: 6039 str r1, [r7, #0] 8009c76: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_BOSDesc); 8009c78: 683b ldr r3, [r7, #0] 8009c7a: 220c movs r2, #12 8009c7c: 801a strh r2, [r3, #0] return (uint8_t*)USBD_FS_BOSDesc; 8009c7e: 4b03 ldr r3, [pc, #12] @ (8009c8c ) } 8009c80: 4618 mov r0, r3 8009c82: 370c adds r7, #12 8009c84: 46bd mov sp, r7 8009c86: f85d 7b04 ldr.w r7, [sp], #4 8009c8a: 4770 bx lr 8009c8c: 20000190 .word 0x20000190 08009c90 : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 8009c90: b580 push {r7, lr} 8009c92: b084 sub sp, #16 8009c94: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 8009c96: 4b0f ldr r3, [pc, #60] @ (8009cd4 ) 8009c98: 681b ldr r3, [r3, #0] 8009c9a: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 8009c9c: 4b0e ldr r3, [pc, #56] @ (8009cd8 ) 8009c9e: 681b ldr r3, [r3, #0] 8009ca0: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 8009ca2: 4b0e ldr r3, [pc, #56] @ (8009cdc ) 8009ca4: 681b ldr r3, [r3, #0] 8009ca6: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 8009ca8: 68fa ldr r2, [r7, #12] 8009caa: 687b ldr r3, [r7, #4] 8009cac: 4413 add r3, r2 8009cae: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 8009cb0: 68fb ldr r3, [r7, #12] 8009cb2: 2b00 cmp r3, #0 8009cb4: d009 beq.n 8009cca { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 8009cb6: 2208 movs r2, #8 8009cb8: 4909 ldr r1, [pc, #36] @ (8009ce0 ) 8009cba: 68f8 ldr r0, [r7, #12] 8009cbc: f000 f814 bl 8009ce8 IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 8009cc0: 2204 movs r2, #4 8009cc2: 4908 ldr r1, [pc, #32] @ (8009ce4 ) 8009cc4: 68b8 ldr r0, [r7, #8] 8009cc6: f000 f80f bl 8009ce8 } } 8009cca: bf00 nop 8009ccc: 3710 adds r7, #16 8009cce: 46bd mov sp, r7 8009cd0: bd80 pop {r7, pc} 8009cd2: bf00 nop 8009cd4: 1fff7a10 .word 0x1fff7a10 8009cd8: 1fff7a14 .word 0x1fff7a14 8009cdc: 1fff7a18 .word 0x1fff7a18 8009ce0: 200001a2 .word 0x200001a2 8009ce4: 200001b2 .word 0x200001b2 08009ce8 : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 8009ce8: b480 push {r7} 8009cea: b087 sub sp, #28 8009cec: af00 add r7, sp, #0 8009cee: 60f8 str r0, [r7, #12] 8009cf0: 60b9 str r1, [r7, #8] 8009cf2: 4613 mov r3, r2 8009cf4: 71fb strb r3, [r7, #7] uint8_t idx = 0; 8009cf6: 2300 movs r3, #0 8009cf8: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 8009cfa: 2300 movs r3, #0 8009cfc: 75fb strb r3, [r7, #23] 8009cfe: e027 b.n 8009d50 { if (((value >> 28)) < 0xA) 8009d00: 68fb ldr r3, [r7, #12] 8009d02: 0f1b lsrs r3, r3, #28 8009d04: 2b09 cmp r3, #9 8009d06: d80b bhi.n 8009d20 { pbuf[2 * idx] = (value >> 28) + '0'; 8009d08: 68fb ldr r3, [r7, #12] 8009d0a: 0f1b lsrs r3, r3, #28 8009d0c: b2da uxtb r2, r3 8009d0e: 7dfb ldrb r3, [r7, #23] 8009d10: 005b lsls r3, r3, #1 8009d12: 4619 mov r1, r3 8009d14: 68bb ldr r3, [r7, #8] 8009d16: 440b add r3, r1 8009d18: 3230 adds r2, #48 @ 0x30 8009d1a: b2d2 uxtb r2, r2 8009d1c: 701a strb r2, [r3, #0] 8009d1e: e00a b.n 8009d36 } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 8009d20: 68fb ldr r3, [r7, #12] 8009d22: 0f1b lsrs r3, r3, #28 8009d24: b2da uxtb r2, r3 8009d26: 7dfb ldrb r3, [r7, #23] 8009d28: 005b lsls r3, r3, #1 8009d2a: 4619 mov r1, r3 8009d2c: 68bb ldr r3, [r7, #8] 8009d2e: 440b add r3, r1 8009d30: 3237 adds r2, #55 @ 0x37 8009d32: b2d2 uxtb r2, r2 8009d34: 701a strb r2, [r3, #0] } value = value << 4; 8009d36: 68fb ldr r3, [r7, #12] 8009d38: 011b lsls r3, r3, #4 8009d3a: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 8009d3c: 7dfb ldrb r3, [r7, #23] 8009d3e: 005b lsls r3, r3, #1 8009d40: 3301 adds r3, #1 8009d42: 68ba ldr r2, [r7, #8] 8009d44: 4413 add r3, r2 8009d46: 2200 movs r2, #0 8009d48: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 8009d4a: 7dfb ldrb r3, [r7, #23] 8009d4c: 3301 adds r3, #1 8009d4e: 75fb strb r3, [r7, #23] 8009d50: 7dfa ldrb r2, [r7, #23] 8009d52: 79fb ldrb r3, [r7, #7] 8009d54: 429a cmp r2, r3 8009d56: d3d3 bcc.n 8009d00 } } 8009d58: bf00 nop 8009d5a: bf00 nop 8009d5c: 371c adds r7, #28 8009d5e: 46bd mov sp, r7 8009d60: f85d 7b04 ldr.w r7, [sp], #4 8009d64: 4770 bx lr ... 08009d68 : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 8009d68: b580 push {r7, lr} 8009d6a: b0a0 sub sp, #128 @ 0x80 8009d6c: af00 add r7, sp, #0 8009d6e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8009d70: f107 036c add.w r3, r7, #108 @ 0x6c 8009d74: 2200 movs r2, #0 8009d76: 601a str r2, [r3, #0] 8009d78: 605a str r2, [r3, #4] 8009d7a: 609a str r2, [r3, #8] 8009d7c: 60da str r2, [r3, #12] 8009d7e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8009d80: f107 0310 add.w r3, r7, #16 8009d84: 225c movs r2, #92 @ 0x5c 8009d86: 2100 movs r1, #0 8009d88: 4618 mov r0, r3 8009d8a: f000 fb53 bl 800a434 if(pcdHandle->Instance==USB_OTG_FS) 8009d8e: 687b ldr r3, [r7, #4] 8009d90: 681b ldr r3, [r3, #0] 8009d92: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8009d96: d149 bne.n 8009e2c /* USER CODE END USB_OTG_FS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; 8009d98: f44f 7380 mov.w r3, #256 @ 0x100 8009d9c: 613b str r3, [r7, #16] PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; 8009d9e: 2300 movs r3, #0 8009da0: 667b str r3, [r7, #100] @ 0x64 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8009da2: f107 0310 add.w r3, r7, #16 8009da6: 4618 mov r0, r3 8009da8: f7fa f934 bl 8004014 8009dac: 4603 mov r3, r0 8009dae: 2b00 cmp r3, #0 8009db0: d001 beq.n 8009db6 { Error_Handler(); 8009db2: f7f6 ff09 bl 8000bc8 } __HAL_RCC_GPIOA_CLK_ENABLE(); 8009db6: 2300 movs r3, #0 8009db8: 60fb str r3, [r7, #12] 8009dba: 4b1e ldr r3, [pc, #120] @ (8009e34 ) 8009dbc: 6b1b ldr r3, [r3, #48] @ 0x30 8009dbe: 4a1d ldr r2, [pc, #116] @ (8009e34 ) 8009dc0: f043 0301 orr.w r3, r3, #1 8009dc4: 6313 str r3, [r2, #48] @ 0x30 8009dc6: 4b1b ldr r3, [pc, #108] @ (8009e34 ) 8009dc8: 6b1b ldr r3, [r3, #48] @ 0x30 8009dca: f003 0301 and.w r3, r3, #1 8009dce: 60fb str r3, [r7, #12] 8009dd0: 68fb ldr r3, [r7, #12] /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 8009dd2: f44f 53c0 mov.w r3, #6144 @ 0x1800 8009dd6: 66fb str r3, [r7, #108] @ 0x6c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8009dd8: 2302 movs r3, #2 8009dda: 673b str r3, [r7, #112] @ 0x70 GPIO_InitStruct.Pull = GPIO_NOPULL; 8009ddc: 2300 movs r3, #0 8009dde: 677b str r3, [r7, #116] @ 0x74 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8009de0: 2303 movs r3, #3 8009de2: 67bb str r3, [r7, #120] @ 0x78 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 8009de4: 230a movs r3, #10 8009de6: 67fb str r3, [r7, #124] @ 0x7c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8009de8: f107 036c add.w r3, r7, #108 @ 0x6c 8009dec: 4619 mov r1, r3 8009dee: 4812 ldr r0, [pc, #72] @ (8009e38 ) 8009df0: f7f8 fa66 bl 80022c0 /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 8009df4: 4b0f ldr r3, [pc, #60] @ (8009e34 ) 8009df6: 6b5b ldr r3, [r3, #52] @ 0x34 8009df8: 4a0e ldr r2, [pc, #56] @ (8009e34 ) 8009dfa: f043 0380 orr.w r3, r3, #128 @ 0x80 8009dfe: 6353 str r3, [r2, #52] @ 0x34 8009e00: 2300 movs r3, #0 8009e02: 60bb str r3, [r7, #8] 8009e04: 4b0b ldr r3, [pc, #44] @ (8009e34 ) 8009e06: 6c5b ldr r3, [r3, #68] @ 0x44 8009e08: 4a0a ldr r2, [pc, #40] @ (8009e34 ) 8009e0a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8009e0e: 6453 str r3, [r2, #68] @ 0x44 8009e10: 4b08 ldr r3, [pc, #32] @ (8009e34 ) 8009e12: 6c5b ldr r3, [r3, #68] @ 0x44 8009e14: f403 4380 and.w r3, r3, #16384 @ 0x4000 8009e18: 60bb str r3, [r7, #8] 8009e1a: 68bb ldr r3, [r7, #8] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); 8009e1c: 2200 movs r2, #0 8009e1e: 2100 movs r1, #0 8009e20: 2043 movs r0, #67 @ 0x43 8009e22: f7f7 fe14 bl 8001a4e HAL_NVIC_EnableIRQ(OTG_FS_IRQn); 8009e26: 2043 movs r0, #67 @ 0x43 8009e28: f7f7 fe2d bl 8001a86 /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 8009e2c: bf00 nop 8009e2e: 3780 adds r7, #128 @ 0x80 8009e30: 46bd mov sp, r7 8009e32: bd80 pop {r7, pc} 8009e34: 40023800 .word 0x40023800 8009e38: 40020000 .word 0x40020000 08009e3c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009e3c: b580 push {r7, lr} 8009e3e: b082 sub sp, #8 8009e40: af00 add r7, sp, #0 8009e42: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 8009e44: 687b ldr r3, [r7, #4] 8009e46: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0 8009e4a: 687b ldr r3, [r7, #4] 8009e4c: f203 439c addw r3, r3, #1180 @ 0x49c 8009e50: 4619 mov r1, r3 8009e52: 4610 mov r0, r2 8009e54: f7fe fbcb bl 80085ee } 8009e58: bf00 nop 8009e5a: 3708 adds r7, #8 8009e5c: 46bd mov sp, r7 8009e5e: bd80 pop {r7, pc} 08009e60 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009e60: b580 push {r7, lr} 8009e62: b082 sub sp, #8 8009e64: af00 add r7, sp, #0 8009e66: 6078 str r0, [r7, #4] 8009e68: 460b mov r3, r1 8009e6a: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 8009e6c: 687b ldr r3, [r7, #4] 8009e6e: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 8009e72: 78fa ldrb r2, [r7, #3] 8009e74: 6879 ldr r1, [r7, #4] 8009e76: 4613 mov r3, r2 8009e78: 00db lsls r3, r3, #3 8009e7a: 4413 add r3, r2 8009e7c: 009b lsls r3, r3, #2 8009e7e: 440b add r3, r1 8009e80: f503 7318 add.w r3, r3, #608 @ 0x260 8009e84: 681a ldr r2, [r3, #0] 8009e86: 78fb ldrb r3, [r7, #3] 8009e88: 4619 mov r1, r3 8009e8a: f7fe fc05 bl 8008698 } 8009e8e: bf00 nop 8009e90: 3708 adds r7, #8 8009e92: 46bd mov sp, r7 8009e94: bd80 pop {r7, pc} 08009e96 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009e96: b580 push {r7, lr} 8009e98: b082 sub sp, #8 8009e9a: af00 add r7, sp, #0 8009e9c: 6078 str r0, [r7, #4] 8009e9e: 460b mov r3, r1 8009ea0: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 8009ea2: 687b ldr r3, [r7, #4] 8009ea4: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 8009ea8: 78fa ldrb r2, [r7, #3] 8009eaa: 6879 ldr r1, [r7, #4] 8009eac: 4613 mov r3, r2 8009eae: 00db lsls r3, r3, #3 8009eb0: 4413 add r3, r2 8009eb2: 009b lsls r3, r3, #2 8009eb4: 440b add r3, r1 8009eb6: 3320 adds r3, #32 8009eb8: 681a ldr r2, [r3, #0] 8009eba: 78fb ldrb r3, [r7, #3] 8009ebc: 4619 mov r1, r3 8009ebe: f7fe fca7 bl 8008810 } 8009ec2: bf00 nop 8009ec4: 3708 adds r7, #8 8009ec6: 46bd mov sp, r7 8009ec8: bd80 pop {r7, pc} 08009eca : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009eca: b580 push {r7, lr} 8009ecc: b082 sub sp, #8 8009ece: af00 add r7, sp, #0 8009ed0: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 8009ed2: 687b ldr r3, [r7, #4] 8009ed4: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 8009ed8: 4618 mov r0, r3 8009eda: f7fe fdeb bl 8008ab4 } 8009ede: bf00 nop 8009ee0: 3708 adds r7, #8 8009ee2: 46bd mov sp, r7 8009ee4: bd80 pop {r7, pc} 08009ee6 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009ee6: b580 push {r7, lr} 8009ee8: b084 sub sp, #16 8009eea: af00 add r7, sp, #0 8009eec: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 8009eee: 2301 movs r3, #1 8009ef0: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed == PCD_SPEED_HIGH) 8009ef2: 687b ldr r3, [r7, #4] 8009ef4: 79db ldrb r3, [r3, #7] 8009ef6: 2b00 cmp r3, #0 8009ef8: d102 bne.n 8009f00 { speed = USBD_SPEED_HIGH; 8009efa: 2300 movs r3, #0 8009efc: 73fb strb r3, [r7, #15] 8009efe: e008 b.n 8009f12 } else if ( hpcd->Init.speed == PCD_SPEED_FULL) 8009f00: 687b ldr r3, [r7, #4] 8009f02: 79db ldrb r3, [r3, #7] 8009f04: 2b02 cmp r3, #2 8009f06: d102 bne.n 8009f0e { speed = USBD_SPEED_FULL; 8009f08: 2301 movs r3, #1 8009f0a: 73fb strb r3, [r7, #15] 8009f0c: e001 b.n 8009f12 } else { Error_Handler(); 8009f0e: f7f6 fe5b bl 8000bc8 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 8009f12: 687b ldr r3, [r7, #4] 8009f14: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 8009f18: 7bfa ldrb r2, [r7, #15] 8009f1a: 4611 mov r1, r2 8009f1c: 4618 mov r0, r3 8009f1e: f7fe fd85 bl 8008a2c /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 8009f22: 687b ldr r3, [r7, #4] 8009f24: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 8009f28: 4618 mov r0, r3 8009f2a: f7fe fd2c bl 8008986 } 8009f2e: bf00 nop 8009f30: 3710 adds r7, #16 8009f32: 46bd mov sp, r7 8009f34: bd80 pop {r7, pc} ... 08009f38 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009f38: b580 push {r7, lr} 8009f3a: b082 sub sp, #8 8009f3c: af00 add r7, sp, #0 8009f3e: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 8009f40: 687b ldr r3, [r7, #4] 8009f42: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 8009f46: 4618 mov r0, r3 8009f48: f7fe fd80 bl 8008a4c __HAL_PCD_GATE_PHYCLOCK(hpcd); 8009f4c: 687b ldr r3, [r7, #4] 8009f4e: 681b ldr r3, [r3, #0] 8009f50: f503 6360 add.w r3, r3, #3584 @ 0xe00 8009f54: 681b ldr r3, [r3, #0] 8009f56: 687a ldr r2, [r7, #4] 8009f58: 6812 ldr r2, [r2, #0] 8009f5a: f502 6260 add.w r2, r2, #3584 @ 0xe00 8009f5e: f043 0301 orr.w r3, r3, #1 8009f62: 6013 str r3, [r2, #0] /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 8009f64: 687b ldr r3, [r7, #4] 8009f66: 7adb ldrb r3, [r3, #11] 8009f68: 2b00 cmp r3, #0 8009f6a: d005 beq.n 8009f78 { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 8009f6c: 4b04 ldr r3, [pc, #16] @ (8009f80 ) 8009f6e: 691b ldr r3, [r3, #16] 8009f70: 4a03 ldr r2, [pc, #12] @ (8009f80 ) 8009f72: f043 0306 orr.w r3, r3, #6 8009f76: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 8009f78: bf00 nop 8009f7a: 3708 adds r7, #8 8009f7c: 46bd mov sp, r7 8009f7e: bd80 pop {r7, pc} 8009f80: e000ed00 .word 0xe000ed00 08009f84 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009f84: b580 push {r7, lr} 8009f86: b082 sub sp, #8 8009f88: af00 add r7, sp, #0 8009f8a: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 8009f8c: 687b ldr r3, [r7, #4] 8009f8e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 8009f92: 4618 mov r0, r3 8009f94: f7fe fd76 bl 8008a84 } 8009f98: bf00 nop 8009f9a: 3708 adds r7, #8 8009f9c: 46bd mov sp, r7 8009f9e: bd80 pop {r7, pc} 08009fa0 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009fa0: b580 push {r7, lr} 8009fa2: b082 sub sp, #8 8009fa4: af00 add r7, sp, #0 8009fa6: 6078 str r0, [r7, #4] 8009fa8: 460b mov r3, r1 8009faa: 70fb strb r3, [r7, #3] USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 8009fac: 687b ldr r3, [r7, #4] 8009fae: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 8009fb2: 78fa ldrb r2, [r7, #3] 8009fb4: 4611 mov r1, r2 8009fb6: 4618 mov r0, r3 8009fb8: f7fe fdce bl 8008b58 } 8009fbc: bf00 nop 8009fbe: 3708 adds r7, #8 8009fc0: 46bd mov sp, r7 8009fc2: bd80 pop {r7, pc} 08009fc4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009fc4: b580 push {r7, lr} 8009fc6: b082 sub sp, #8 8009fc8: af00 add r7, sp, #0 8009fca: 6078 str r0, [r7, #4] 8009fcc: 460b mov r3, r1 8009fce: 70fb strb r3, [r7, #3] USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 8009fd0: 687b ldr r3, [r7, #4] 8009fd2: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 8009fd6: 78fa ldrb r2, [r7, #3] 8009fd8: 4611 mov r1, r2 8009fda: 4618 mov r0, r3 8009fdc: f7fe fd8a bl 8008af4 } 8009fe0: bf00 nop 8009fe2: 3708 adds r7, #8 8009fe4: 46bd mov sp, r7 8009fe6: bd80 pop {r7, pc} 08009fe8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8009fe8: b580 push {r7, lr} 8009fea: b082 sub sp, #8 8009fec: af00 add r7, sp, #0 8009fee: 6078 str r0, [r7, #4] USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); 8009ff0: 687b ldr r3, [r7, #4] 8009ff2: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 8009ff6: 4618 mov r0, r3 8009ff8: f7fe fde0 bl 8008bbc } 8009ffc: bf00 nop 8009ffe: 3708 adds r7, #8 800a000: 46bd mov sp, r7 800a002: bd80 pop {r7, pc} 0800a004 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a004: b580 push {r7, lr} 800a006: b082 sub sp, #8 800a008: af00 add r7, sp, #0 800a00a: 6078 str r0, [r7, #4] USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); 800a00c: 687b ldr r3, [r7, #4] 800a00e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a012: 4618 mov r0, r3 800a014: f7fe fddd bl 8008bd2 } 800a018: bf00 nop 800a01a: 3708 adds r7, #8 800a01c: 46bd mov sp, r7 800a01e: bd80 pop {r7, pc} 0800a020 : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 800a020: b580 push {r7, lr} 800a022: b082 sub sp, #8 800a024: af00 add r7, sp, #0 800a026: 6078 str r0, [r7, #4] /* Init USB Ip. */ if (pdev->id == DEVICE_FS) { 800a028: 687b ldr r3, [r7, #4] 800a02a: 781b ldrb r3, [r3, #0] 800a02c: 2b00 cmp r3, #0 800a02e: d13c bne.n 800a0aa /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; 800a030: 4a20 ldr r2, [pc, #128] @ (800a0b4 ) 800a032: 687b ldr r3, [r7, #4] 800a034: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0 pdev->pData = &hpcd_USB_OTG_FS; 800a038: 687b ldr r3, [r7, #4] 800a03a: 4a1e ldr r2, [pc, #120] @ (800a0b4 ) 800a03c: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8 hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 800a040: 4b1c ldr r3, [pc, #112] @ (800a0b4 ) 800a042: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 800a046: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 6; 800a048: 4b1a ldr r3, [pc, #104] @ (800a0b4 ) 800a04a: 2206 movs r2, #6 800a04c: 711a strb r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 800a04e: 4b19 ldr r3, [pc, #100] @ (800a0b4 ) 800a050: 2202 movs r2, #2 800a052: 71da strb r2, [r3, #7] hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; 800a054: 4b17 ldr r3, [pc, #92] @ (800a0b4 ) 800a056: 2200 movs r2, #0 800a058: 719a strb r2, [r3, #6] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 800a05a: 4b16 ldr r3, [pc, #88] @ (800a0b4 ) 800a05c: 2202 movs r2, #2 800a05e: 725a strb r2, [r3, #9] hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; 800a060: 4b14 ldr r3, [pc, #80] @ (800a0b4 ) 800a062: 2200 movs r2, #0 800a064: 729a strb r2, [r3, #10] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 800a066: 4b13 ldr r3, [pc, #76] @ (800a0b4 ) 800a068: 2200 movs r2, #0 800a06a: 72da strb r2, [r3, #11] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 800a06c: 4b11 ldr r3, [pc, #68] @ (800a0b4 ) 800a06e: 2200 movs r2, #0 800a070: 731a strb r2, [r3, #12] hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; 800a072: 4b10 ldr r3, [pc, #64] @ (800a0b4 ) 800a074: 2200 movs r2, #0 800a076: 739a strb r2, [r3, #14] hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 800a078: 4b0e ldr r3, [pc, #56] @ (800a0b4 ) 800a07a: 2200 movs r2, #0 800a07c: 73da strb r2, [r3, #15] if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 800a07e: 480d ldr r0, [pc, #52] @ (800a0b4 ) 800a080: f7f8 fc28 bl 80028d4 800a084: 4603 mov r3, r0 800a086: 2b00 cmp r3, #0 800a088: d001 beq.n 800a08e { Error_Handler( ); 800a08a: f7f6 fd9d bl 8000bc8 HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback); HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); 800a08e: 2180 movs r1, #128 @ 0x80 800a090: 4808 ldr r0, [pc, #32] @ (800a0b4 ) 800a092: f7f9 fe70 bl 8003d76 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); 800a096: 2240 movs r2, #64 @ 0x40 800a098: 2100 movs r1, #0 800a09a: 4806 ldr r0, [pc, #24] @ (800a0b4 ) 800a09c: f7f9 fe24 bl 8003ce8 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); 800a0a0: 2280 movs r2, #128 @ 0x80 800a0a2: 2101 movs r1, #1 800a0a4: 4803 ldr r0, [pc, #12] @ (800a0b4 ) 800a0a6: f7f9 fe1f bl 8003ce8 } return USBD_OK; 800a0aa: 2300 movs r3, #0 } 800a0ac: 4618 mov r0, r3 800a0ae: 3708 adds r7, #8 800a0b0: 46bd mov sp, r7 800a0b2: bd80 pop {r7, pc} 800a0b4: 20000bd8 .word 0x20000bd8 0800a0b8 : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 800a0b8: b580 push {r7, lr} 800a0ba: b084 sub sp, #16 800a0bc: af00 add r7, sp, #0 800a0be: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 800a0c0: 2300 movs r3, #0 800a0c2: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a0c4: 2300 movs r3, #0 800a0c6: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 800a0c8: 687b ldr r3, [r7, #4] 800a0ca: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a0ce: 4618 mov r0, r3 800a0d0: f7f8 fd16 bl 8002b00 800a0d4: 4603 mov r3, r0 800a0d6: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a0d8: 7bfb ldrb r3, [r7, #15] 800a0da: 4618 mov r0, r3 800a0dc: f000 f97e bl 800a3dc 800a0e0: 4603 mov r3, r0 800a0e2: 73bb strb r3, [r7, #14] return usb_status; 800a0e4: 7bbb ldrb r3, [r7, #14] } 800a0e6: 4618 mov r0, r3 800a0e8: 3710 adds r7, #16 800a0ea: 46bd mov sp, r7 800a0ec: bd80 pop {r7, pc} 0800a0ee : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 800a0ee: b580 push {r7, lr} 800a0f0: b084 sub sp, #16 800a0f2: af00 add r7, sp, #0 800a0f4: 6078 str r0, [r7, #4] 800a0f6: 4608 mov r0, r1 800a0f8: 4611 mov r1, r2 800a0fa: 461a mov r2, r3 800a0fc: 4603 mov r3, r0 800a0fe: 70fb strb r3, [r7, #3] 800a100: 460b mov r3, r1 800a102: 70bb strb r3, [r7, #2] 800a104: 4613 mov r3, r2 800a106: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 800a108: 2300 movs r3, #0 800a10a: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a10c: 2300 movs r3, #0 800a10e: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 800a110: 687b ldr r3, [r7, #4] 800a112: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a116: 78bb ldrb r3, [r7, #2] 800a118: 883a ldrh r2, [r7, #0] 800a11a: 78f9 ldrb r1, [r7, #3] 800a11c: f7f9 fa17 bl 800354e 800a120: 4603 mov r3, r0 800a122: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a124: 7bfb ldrb r3, [r7, #15] 800a126: 4618 mov r0, r3 800a128: f000 f958 bl 800a3dc 800a12c: 4603 mov r3, r0 800a12e: 73bb strb r3, [r7, #14] return usb_status; 800a130: 7bbb ldrb r3, [r7, #14] } 800a132: 4618 mov r0, r3 800a134: 3710 adds r7, #16 800a136: 46bd mov sp, r7 800a138: bd80 pop {r7, pc} 0800a13a : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a13a: b580 push {r7, lr} 800a13c: b084 sub sp, #16 800a13e: af00 add r7, sp, #0 800a140: 6078 str r0, [r7, #4] 800a142: 460b mov r3, r1 800a144: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a146: 2300 movs r3, #0 800a148: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a14a: 2300 movs r3, #0 800a14c: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 800a14e: 687b ldr r3, [r7, #4] 800a150: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a154: 78fa ldrb r2, [r7, #3] 800a156: 4611 mov r1, r2 800a158: 4618 mov r0, r3 800a15a: f7f9 fa62 bl 8003622 800a15e: 4603 mov r3, r0 800a160: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a162: 7bfb ldrb r3, [r7, #15] 800a164: 4618 mov r0, r3 800a166: f000 f939 bl 800a3dc 800a16a: 4603 mov r3, r0 800a16c: 73bb strb r3, [r7, #14] return usb_status; 800a16e: 7bbb ldrb r3, [r7, #14] } 800a170: 4618 mov r0, r3 800a172: 3710 adds r7, #16 800a174: 46bd mov sp, r7 800a176: bd80 pop {r7, pc} 0800a178 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a178: b580 push {r7, lr} 800a17a: b084 sub sp, #16 800a17c: af00 add r7, sp, #0 800a17e: 6078 str r0, [r7, #4] 800a180: 460b mov r3, r1 800a182: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a184: 2300 movs r3, #0 800a186: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a188: 2300 movs r3, #0 800a18a: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 800a18c: 687b ldr r3, [r7, #4] 800a18e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a192: 78fa ldrb r2, [r7, #3] 800a194: 4611 mov r1, r2 800a196: 4618 mov r0, r3 800a198: f7f9 fb02 bl 80037a0 800a19c: 4603 mov r3, r0 800a19e: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a1a0: 7bfb ldrb r3, [r7, #15] 800a1a2: 4618 mov r0, r3 800a1a4: f000 f91a bl 800a3dc 800a1a8: 4603 mov r3, r0 800a1aa: 73bb strb r3, [r7, #14] return usb_status; 800a1ac: 7bbb ldrb r3, [r7, #14] } 800a1ae: 4618 mov r0, r3 800a1b0: 3710 adds r7, #16 800a1b2: 46bd mov sp, r7 800a1b4: bd80 pop {r7, pc} 0800a1b6 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a1b6: b580 push {r7, lr} 800a1b8: b084 sub sp, #16 800a1ba: af00 add r7, sp, #0 800a1bc: 6078 str r0, [r7, #4] 800a1be: 460b mov r3, r1 800a1c0: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a1c2: 2300 movs r3, #0 800a1c4: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a1c6: 2300 movs r3, #0 800a1c8: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 800a1ca: 687b ldr r3, [r7, #4] 800a1cc: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a1d0: 78fa ldrb r2, [r7, #3] 800a1d2: 4611 mov r1, r2 800a1d4: 4618 mov r0, r3 800a1d6: f7f9 fb46 bl 8003866 800a1da: 4603 mov r3, r0 800a1dc: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a1de: 7bfb ldrb r3, [r7, #15] 800a1e0: 4618 mov r0, r3 800a1e2: f000 f8fb bl 800a3dc 800a1e6: 4603 mov r3, r0 800a1e8: 73bb strb r3, [r7, #14] return usb_status; 800a1ea: 7bbb ldrb r3, [r7, #14] } 800a1ec: 4618 mov r0, r3 800a1ee: 3710 adds r7, #16 800a1f0: 46bd mov sp, r7 800a1f2: bd80 pop {r7, pc} 0800a1f4 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a1f4: b480 push {r7} 800a1f6: b085 sub sp, #20 800a1f8: af00 add r7, sp, #0 800a1fa: 6078 str r0, [r7, #4] 800a1fc: 460b mov r3, r1 800a1fe: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 800a200: 687b ldr r3, [r7, #4] 800a202: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a206: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 800a208: f997 3003 ldrsb.w r3, [r7, #3] 800a20c: 2b00 cmp r3, #0 800a20e: da0b bge.n 800a228 { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 800a210: 78fb ldrb r3, [r7, #3] 800a212: f003 027f and.w r2, r3, #127 @ 0x7f 800a216: 68f9 ldr r1, [r7, #12] 800a218: 4613 mov r3, r2 800a21a: 00db lsls r3, r3, #3 800a21c: 4413 add r3, r2 800a21e: 009b lsls r3, r3, #2 800a220: 440b add r3, r1 800a222: 3316 adds r3, #22 800a224: 781b ldrb r3, [r3, #0] 800a226: e00b b.n 800a240 } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 800a228: 78fb ldrb r3, [r7, #3] 800a22a: f003 027f and.w r2, r3, #127 @ 0x7f 800a22e: 68f9 ldr r1, [r7, #12] 800a230: 4613 mov r3, r2 800a232: 00db lsls r3, r3, #3 800a234: 4413 add r3, r2 800a236: 009b lsls r3, r3, #2 800a238: 440b add r3, r1 800a23a: f203 2356 addw r3, r3, #598 @ 0x256 800a23e: 781b ldrb r3, [r3, #0] } } 800a240: 4618 mov r0, r3 800a242: 3714 adds r7, #20 800a244: 46bd mov sp, r7 800a246: f85d 7b04 ldr.w r7, [sp], #4 800a24a: 4770 bx lr 0800a24c : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 800a24c: b580 push {r7, lr} 800a24e: b084 sub sp, #16 800a250: af00 add r7, sp, #0 800a252: 6078 str r0, [r7, #4] 800a254: 460b mov r3, r1 800a256: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a258: 2300 movs r3, #0 800a25a: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a25c: 2300 movs r3, #0 800a25e: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 800a260: 687b ldr r3, [r7, #4] 800a262: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a266: 78fa ldrb r2, [r7, #3] 800a268: 4611 mov r1, r2 800a26a: 4618 mov r0, r3 800a26c: f7f9 f94b bl 8003506 800a270: 4603 mov r3, r0 800a272: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a274: 7bfb ldrb r3, [r7, #15] 800a276: 4618 mov r0, r3 800a278: f000 f8b0 bl 800a3dc 800a27c: 4603 mov r3, r0 800a27e: 73bb strb r3, [r7, #14] return usb_status; 800a280: 7bbb ldrb r3, [r7, #14] } 800a282: 4618 mov r0, r3 800a284: 3710 adds r7, #16 800a286: 46bd mov sp, r7 800a288: bd80 pop {r7, pc} 0800a28a : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800a28a: b580 push {r7, lr} 800a28c: b086 sub sp, #24 800a28e: af00 add r7, sp, #0 800a290: 60f8 str r0, [r7, #12] 800a292: 607a str r2, [r7, #4] 800a294: 603b str r3, [r7, #0] 800a296: 460b mov r3, r1 800a298: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800a29a: 2300 movs r3, #0 800a29c: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800a29e: 2300 movs r3, #0 800a2a0: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 800a2a2: 68fb ldr r3, [r7, #12] 800a2a4: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a2a8: 7af9 ldrb r1, [r7, #11] 800a2aa: 683b ldr r3, [r7, #0] 800a2ac: 687a ldr r2, [r7, #4] 800a2ae: f7f9 fa3d bl 800372c 800a2b2: 4603 mov r3, r0 800a2b4: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800a2b6: 7dfb ldrb r3, [r7, #23] 800a2b8: 4618 mov r0, r3 800a2ba: f000 f88f bl 800a3dc 800a2be: 4603 mov r3, r0 800a2c0: 75bb strb r3, [r7, #22] return usb_status; 800a2c2: 7dbb ldrb r3, [r7, #22] } 800a2c4: 4618 mov r0, r3 800a2c6: 3718 adds r7, #24 800a2c8: 46bd mov sp, r7 800a2ca: bd80 pop {r7, pc} 0800a2cc : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800a2cc: b580 push {r7, lr} 800a2ce: b086 sub sp, #24 800a2d0: af00 add r7, sp, #0 800a2d2: 60f8 str r0, [r7, #12] 800a2d4: 607a str r2, [r7, #4] 800a2d6: 603b str r3, [r7, #0] 800a2d8: 460b mov r3, r1 800a2da: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800a2dc: 2300 movs r3, #0 800a2de: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800a2e0: 2300 movs r3, #0 800a2e2: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 800a2e4: 68fb ldr r3, [r7, #12] 800a2e6: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a2ea: 7af9 ldrb r1, [r7, #11] 800a2ec: 683b ldr r3, [r7, #0] 800a2ee: 687a ldr r2, [r7, #4] 800a2f0: f7f9 f9e1 bl 80036b6 800a2f4: 4603 mov r3, r0 800a2f6: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800a2f8: 7dfb ldrb r3, [r7, #23] 800a2fa: 4618 mov r0, r3 800a2fc: f000 f86e bl 800a3dc 800a300: 4603 mov r3, r0 800a302: 75bb strb r3, [r7, #22] return usb_status; 800a304: 7dbb ldrb r3, [r7, #22] } 800a306: 4618 mov r0, r3 800a308: 3718 adds r7, #24 800a30a: 46bd mov sp, r7 800a30c: bd80 pop {r7, pc} ... 0800a310 : * @param hpcd: PCD handle * @param msg: LPM message * @retval None */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { 800a310: b580 push {r7, lr} 800a312: b082 sub sp, #8 800a314: af00 add r7, sp, #0 800a316: 6078 str r0, [r7, #4] 800a318: 460b mov r3, r1 800a31a: 70fb strb r3, [r7, #3] switch (msg) 800a31c: 78fb ldrb r3, [r7, #3] 800a31e: 2b00 cmp r3, #0 800a320: d002 beq.n 800a328 800a322: 2b01 cmp r3, #1 800a324: d01f beq.n 800a366 /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } } 800a326: e03b b.n 800a3a0 if (hpcd->Init.low_power_enable) 800a328: 687b ldr r3, [r7, #4] 800a32a: 7adb ldrb r3, [r3, #11] 800a32c: 2b00 cmp r3, #0 800a32e: d007 beq.n 800a340 SystemClock_Config(); 800a330: f7f6 fafc bl 800092c SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a334: 4b1c ldr r3, [pc, #112] @ (800a3a8 ) 800a336: 691b ldr r3, [r3, #16] 800a338: 4a1b ldr r2, [pc, #108] @ (800a3a8 ) 800a33a: f023 0306 bic.w r3, r3, #6 800a33e: 6113 str r3, [r2, #16] __HAL_PCD_UNGATE_PHYCLOCK(hpcd); 800a340: 687b ldr r3, [r7, #4] 800a342: 681b ldr r3, [r3, #0] 800a344: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a348: 681b ldr r3, [r3, #0] 800a34a: 687a ldr r2, [r7, #4] 800a34c: 6812 ldr r2, [r2, #0] 800a34e: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a352: f023 0301 bic.w r3, r3, #1 800a356: 6013 str r3, [r2, #0] USBD_LL_Resume(hpcd->pData); 800a358: 687b ldr r3, [r7, #4] 800a35a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a35e: 4618 mov r0, r3 800a360: f7fe fb90 bl 8008a84 break; 800a364: e01c b.n 800a3a0 __HAL_PCD_GATE_PHYCLOCK(hpcd); 800a366: 687b ldr r3, [r7, #4] 800a368: 681b ldr r3, [r3, #0] 800a36a: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a36e: 681b ldr r3, [r3, #0] 800a370: 687a ldr r2, [r7, #4] 800a372: 6812 ldr r2, [r2, #0] 800a374: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a378: f043 0301 orr.w r3, r3, #1 800a37c: 6013 str r3, [r2, #0] USBD_LL_Suspend(hpcd->pData); 800a37e: 687b ldr r3, [r7, #4] 800a380: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a384: 4618 mov r0, r3 800a386: f7fe fb61 bl 8008a4c if (hpcd->Init.low_power_enable) 800a38a: 687b ldr r3, [r7, #4] 800a38c: 7adb ldrb r3, [r3, #11] 800a38e: 2b00 cmp r3, #0 800a390: d005 beq.n 800a39e SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a392: 4b05 ldr r3, [pc, #20] @ (800a3a8 ) 800a394: 691b ldr r3, [r3, #16] 800a396: 4a04 ldr r2, [pc, #16] @ (800a3a8 ) 800a398: f043 0306 orr.w r3, r3, #6 800a39c: 6113 str r3, [r2, #16] break; 800a39e: bf00 nop } 800a3a0: bf00 nop 800a3a2: 3708 adds r7, #8 800a3a4: 46bd mov sp, r7 800a3a6: bd80 pop {r7, pc} 800a3a8: e000ed00 .word 0xe000ed00 0800a3ac : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 800a3ac: b480 push {r7} 800a3ae: b083 sub sp, #12 800a3b0: af00 add r7, sp, #0 800a3b2: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 800a3b4: 4b03 ldr r3, [pc, #12] @ (800a3c4 ) } 800a3b6: 4618 mov r0, r3 800a3b8: 370c adds r7, #12 800a3ba: 46bd mov sp, r7 800a3bc: f85d 7b04 ldr.w r7, [sp], #4 800a3c0: 4770 bx lr 800a3c2: bf00 nop 800a3c4: 200010bc .word 0x200010bc 0800a3c8 : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 800a3c8: b480 push {r7} 800a3ca: b083 sub sp, #12 800a3cc: af00 add r7, sp, #0 800a3ce: 6078 str r0, [r7, #4] } 800a3d0: bf00 nop 800a3d2: 370c adds r7, #12 800a3d4: 46bd mov sp, r7 800a3d6: f85d 7b04 ldr.w r7, [sp], #4 800a3da: 4770 bx lr 0800a3dc : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 800a3dc: b480 push {r7} 800a3de: b085 sub sp, #20 800a3e0: af00 add r7, sp, #0 800a3e2: 4603 mov r3, r0 800a3e4: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 800a3e6: 2300 movs r3, #0 800a3e8: 73fb strb r3, [r7, #15] switch (hal_status) 800a3ea: 79fb ldrb r3, [r7, #7] 800a3ec: 2b03 cmp r3, #3 800a3ee: d817 bhi.n 800a420 800a3f0: a201 add r2, pc, #4 @ (adr r2, 800a3f8 ) 800a3f2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a3f6: bf00 nop 800a3f8: 0800a409 .word 0x0800a409 800a3fc: 0800a40f .word 0x0800a40f 800a400: 0800a415 .word 0x0800a415 800a404: 0800a41b .word 0x0800a41b { case HAL_OK : usb_status = USBD_OK; 800a408: 2300 movs r3, #0 800a40a: 73fb strb r3, [r7, #15] break; 800a40c: e00b b.n 800a426 case HAL_ERROR : usb_status = USBD_FAIL; 800a40e: 2303 movs r3, #3 800a410: 73fb strb r3, [r7, #15] break; 800a412: e008 b.n 800a426 case HAL_BUSY : usb_status = USBD_BUSY; 800a414: 2301 movs r3, #1 800a416: 73fb strb r3, [r7, #15] break; 800a418: e005 b.n 800a426 case HAL_TIMEOUT : usb_status = USBD_FAIL; 800a41a: 2303 movs r3, #3 800a41c: 73fb strb r3, [r7, #15] break; 800a41e: e002 b.n 800a426 default : usb_status = USBD_FAIL; 800a420: 2303 movs r3, #3 800a422: 73fb strb r3, [r7, #15] break; 800a424: bf00 nop } return usb_status; 800a426: 7bfb ldrb r3, [r7, #15] } 800a428: 4618 mov r0, r3 800a42a: 3714 adds r7, #20 800a42c: 46bd mov sp, r7 800a42e: f85d 7b04 ldr.w r7, [sp], #4 800a432: 4770 bx lr 0800a434 : 800a434: 4402 add r2, r0 800a436: 4603 mov r3, r0 800a438: 4293 cmp r3, r2 800a43a: d100 bne.n 800a43e 800a43c: 4770 bx lr 800a43e: f803 1b01 strb.w r1, [r3], #1 800a442: e7f9 b.n 800a438 0800a444 <__libc_init_array>: 800a444: b570 push {r4, r5, r6, lr} 800a446: 4d0d ldr r5, [pc, #52] @ (800a47c <__libc_init_array+0x38>) 800a448: 4c0d ldr r4, [pc, #52] @ (800a480 <__libc_init_array+0x3c>) 800a44a: 1b64 subs r4, r4, r5 800a44c: 10a4 asrs r4, r4, #2 800a44e: 2600 movs r6, #0 800a450: 42a6 cmp r6, r4 800a452: d109 bne.n 800a468 <__libc_init_array+0x24> 800a454: 4d0b ldr r5, [pc, #44] @ (800a484 <__libc_init_array+0x40>) 800a456: 4c0c ldr r4, [pc, #48] @ (800a488 <__libc_init_array+0x44>) 800a458: f000 f818 bl 800a48c <_init> 800a45c: 1b64 subs r4, r4, r5 800a45e: 10a4 asrs r4, r4, #2 800a460: 2600 movs r6, #0 800a462: 42a6 cmp r6, r4 800a464: d105 bne.n 800a472 <__libc_init_array+0x2e> 800a466: bd70 pop {r4, r5, r6, pc} 800a468: f855 3b04 ldr.w r3, [r5], #4 800a46c: 4798 blx r3 800a46e: 3601 adds r6, #1 800a470: e7ee b.n 800a450 <__libc_init_array+0xc> 800a472: f855 3b04 ldr.w r3, [r5], #4 800a476: 4798 blx r3 800a478: 3601 adds r6, #1 800a47a: e7f2 b.n 800a462 <__libc_init_array+0x1e> 800a47c: 0800a508 .word 0x0800a508 800a480: 0800a508 .word 0x0800a508 800a484: 0800a508 .word 0x0800a508 800a488: 0800a50c .word 0x0800a50c 0800a48c <_init>: 800a48c: b5f8 push {r3, r4, r5, r6, r7, lr} 800a48e: bf00 nop 800a490: bcf8 pop {r3, r4, r5, r6, r7} 800a492: bc08 pop {r3} 800a494: 469e mov lr, r3 800a496: 4770 bx lr 0800a498 <_fini>: 800a498: b5f8 push {r3, r4, r5, r6, r7, lr} 800a49a: bf00 nop 800a49c: bcf8 pop {r3, r4, r5, r6, r7} 800a49e: bc08 pop {r3} 800a4a0: 469e mov lr, r3 800a4a2: 4770 bx lr