modularkbd.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001c4 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000a800 080001c4 080001c4 000011c4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000005c 0800a9c4 0800a9c4 0000b9c4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800aa20 0800aa20 0000c1a0 2**0 CONTENTS, READONLY 4 .ARM 00000008 0800aa20 0800aa20 0000ba20 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800aa28 0800aa28 0000c1a0 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800aa28 0800aa28 0000ba28 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 0800aa2c 0800aa2c 0000ba2c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 000001a0 20000000 0800aa30 0000c000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000f58 200001a0 0800abd0 0000c1a0 2**2 ALLOC 10 ._user_heap_stack 00000600 200010f8 0800abd0 0000d0f8 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000c1a0 2**0 CONTENTS, READONLY 12 .debug_info 0001af6f 00000000 00000000 0000c1d0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00004057 00000000 00000000 0002713f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001780 00000000 00000000 0002b198 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 0000123f 00000000 00000000 0002c918 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00026060 00000000 00000000 0002db57 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001e65d 00000000 00000000 00053bb7 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000d7ebb 00000000 00000000 00072214 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0014a0cf 2**0 CONTENTS, READONLY 20 .debug_frame 000062c0 00000000 00000000 0014a114 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000062 00000000 00000000 001503d4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001c4 <__do_global_dtors_aux>: 80001c4: b510 push {r4, lr} 80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>) 80001c8: 7823 ldrb r3, [r4, #0] 80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16> 80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>) 80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12> 80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>) 80001d2: f3af 8000 nop.w 80001d6: 2301 movs r3, #1 80001d8: 7023 strb r3, [r4, #0] 80001da: bd10 pop {r4, pc} 80001dc: 200001a0 .word 0x200001a0 80001e0: 00000000 .word 0x00000000 80001e4: 0800a9ac .word 0x0800a9ac 080001e8 : 80001e8: b508 push {r3, lr} 80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 ) 80001ec: b11b cbz r3, 80001f6 80001ee: 4903 ldr r1, [pc, #12] @ (80001fc ) 80001f0: 4803 ldr r0, [pc, #12] @ (8000200 ) 80001f2: f3af 8000 nop.w 80001f6: bd08 pop {r3, pc} 80001f8: 00000000 .word 0x00000000 80001fc: 200001a4 .word 0x200001a4 8000200: 0800a9ac .word 0x0800a9ac 08000204 <__aeabi_uldivmod>: 8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18> 8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18> 8000208: 2900 cmp r1, #0 800020a: bf08 it eq 800020c: 2800 cmpeq r0, #0 800020e: bf1c itt ne 8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000218: f000 b988 b.w 800052c <__aeabi_idiv0> 800021c: f1ad 0c08 sub.w ip, sp, #8 8000220: e96d ce04 strd ip, lr, [sp, #-16]! 8000224: f000 f806 bl 8000234 <__udivmoddi4> 8000228: f8dd e004 ldr.w lr, [sp, #4] 800022c: e9dd 2302 ldrd r2, r3, [sp, #8] 8000230: b004 add sp, #16 8000232: 4770 bx lr 08000234 <__udivmoddi4>: 8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000238: 9d08 ldr r5, [sp, #32] 800023a: 468e mov lr, r1 800023c: 4604 mov r4, r0 800023e: 4688 mov r8, r1 8000240: 2b00 cmp r3, #0 8000242: d14a bne.n 80002da <__udivmoddi4+0xa6> 8000244: 428a cmp r2, r1 8000246: 4617 mov r7, r2 8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc> 800024a: fab2 f682 clz r6, r2 800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30> 8000250: f1c6 0320 rsb r3, r6, #32 8000254: fa01 f806 lsl.w r8, r1, r6 8000258: fa20 f303 lsr.w r3, r0, r3 800025c: 40b7 lsls r7, r6 800025e: ea43 0808 orr.w r8, r3, r8 8000262: 40b4 lsls r4, r6 8000264: ea4f 4e17 mov.w lr, r7, lsr #16 8000268: fa1f fc87 uxth.w ip, r7 800026c: fbb8 f1fe udiv r1, r8, lr 8000270: 0c23 lsrs r3, r4, #16 8000272: fb0e 8811 mls r8, lr, r1, r8 8000276: ea43 4308 orr.w r3, r3, r8, lsl #16 800027a: fb01 f20c mul.w r2, r1, ip 800027e: 429a cmp r2, r3 8000280: d909 bls.n 8000296 <__udivmoddi4+0x62> 8000282: 18fb adds r3, r7, r3 8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c> 800028c: 429a cmp r2, r3 800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c> 8000292: 3902 subs r1, #2 8000294: 443b add r3, r7 8000296: 1a9a subs r2, r3, r2 8000298: b2a3 uxth r3, r4 800029a: fbb2 f0fe udiv r0, r2, lr 800029e: fb0e 2210 mls r2, lr, r0, r2 80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16 80002a6: fb00 fc0c mul.w ip, r0, ip 80002aa: 459c cmp ip, r3 80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e> 80002ae: 18fb adds r3, r7, r3 80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230> 80002b8: 459c cmp ip, r3 80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230> 80002be: 443b add r3, r7 80002c0: 3802 subs r0, #2 80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16 80002c6: eba3 030c sub.w r3, r3, ip 80002ca: 2100 movs r1, #0 80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2> 80002ce: 40f3 lsrs r3, r6 80002d0: 2200 movs r2, #0 80002d2: e9c5 3200 strd r3, r2, [r5] 80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002da: 428b cmp r3, r1 80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6> 80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0> 80002e0: e9c5 0100 strd r0, r1, [r5] 80002e4: 2100 movs r1, #0 80002e6: 4608 mov r0, r1 80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2> 80002ea: fab3 f183 clz r1, r3 80002ee: 2900 cmp r1, #0 80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c> 80002f2: 4573 cmp r3, lr 80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8> 80002f6: 4282 cmp r2, r0 80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2> 80002fc: 1a84 subs r4, r0, r2 80002fe: eb6e 0203 sbc.w r2, lr, r3 8000302: 2001 movs r0, #1 8000304: 4690 mov r8, r2 8000306: 2d00 cmp r5, #0 8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2> 800030a: e9c5 4800 strd r4, r8, [r5] 800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2> 8000310: 2a00 cmp r2, #0 8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202> 8000316: fab2 f682 clz r6, r2 800031a: 2e00 cmp r6, #0 800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234> 8000320: 1a8a subs r2, r1, r2 8000322: 0c03 lsrs r3, r0, #16 8000324: ea4f 4e17 mov.w lr, r7, lsr #16 8000328: b280 uxth r0, r0 800032a: b2bc uxth r4, r7 800032c: 2101 movs r1, #1 800032e: fbb2 fcfe udiv ip, r2, lr 8000332: fb0e 221c mls r2, lr, ip, r2 8000336: ea43 4302 orr.w r3, r3, r2, lsl #16 800033a: fb04 f20c mul.w r2, r4, ip 800033e: 429a cmp r2, r3 8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e> 8000342: 18fb adds r3, r7, r3 8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c> 800034a: 429a cmp r2, r3 800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc> 8000350: 46c4 mov ip, r8 8000352: 1a9b subs r3, r3, r2 8000354: fbb3 f2fe udiv r2, r3, lr 8000358: fb0e 3312 mls r3, lr, r2, r3 800035c: ea40 4303 orr.w r3, r0, r3, lsl #16 8000360: fb02 f404 mul.w r4, r2, r4 8000364: 429c cmp r4, r3 8000366: d907 bls.n 8000378 <__udivmoddi4+0x144> 8000368: 18fb adds r3, r7, r3 800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142> 8000370: 429c cmp r4, r3 8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6> 8000376: 4602 mov r2, r0 8000378: 1b1b subs r3, r3, r4 800037a: ea42 400c orr.w r0, r2, ip, lsl #16 800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98> 8000380: f1c1 0620 rsb r6, r1, #32 8000384: 408b lsls r3, r1 8000386: fa22 f706 lsr.w r7, r2, r6 800038a: 431f orrs r7, r3 800038c: fa0e f401 lsl.w r4, lr, r1 8000390: fa20 f306 lsr.w r3, r0, r6 8000394: fa2e fe06 lsr.w lr, lr, r6 8000398: ea4f 4917 mov.w r9, r7, lsr #16 800039c: 4323 orrs r3, r4 800039e: fa00 f801 lsl.w r8, r0, r1 80003a2: fa1f fc87 uxth.w ip, r7 80003a6: fbbe f0f9 udiv r0, lr, r9 80003aa: 0c1c lsrs r4, r3, #16 80003ac: fb09 ee10 mls lr, r9, r0, lr 80003b0: ea44 440e orr.w r4, r4, lr, lsl #16 80003b4: fb00 fe0c mul.w lr, r0, ip 80003b8: 45a6 cmp lr, r4 80003ba: fa02 f201 lsl.w r2, r2, r1 80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0> 80003c0: 193c adds r4, r7, r4 80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce> 80003ca: 45a6 cmp lr, r4 80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce> 80003d0: 3802 subs r0, #2 80003d2: 443c add r4, r7 80003d4: eba4 040e sub.w r4, r4, lr 80003d8: fa1f fe83 uxth.w lr, r3 80003dc: fbb4 f3f9 udiv r3, r4, r9 80003e0: fb09 4413 mls r4, r9, r3, r4 80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003e8: fb03 fc0c mul.w ip, r3, ip 80003ec: 45a4 cmp ip, r4 80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce> 80003f0: 193c adds r4, r7, r4 80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca> 80003fa: 45a4 cmp ip, r4 80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca> 80003fe: 3b02 subs r3, #2 8000400: 443c add r4, r7 8000402: ea43 4000 orr.w r0, r3, r0, lsl #16 8000406: eba4 040c sub.w r4, r4, ip 800040a: fba0 ec02 umull lr, ip, r0, r2 800040e: 4564 cmp r4, ip 8000410: 4673 mov r3, lr 8000412: 46e1 mov r9, ip 8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8> 8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4> 8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe> 800041a: ebb8 0203 subs.w r2, r8, r3 800041e: eb64 0409 sbc.w r4, r4, r9 8000422: fa04 f606 lsl.w r6, r4, r6 8000426: fa22 f301 lsr.w r3, r2, r1 800042a: 431e orrs r6, r3 800042c: 40cc lsrs r4, r1 800042e: e9c5 6400 strd r6, r4, [r5] 8000432: 2100 movs r1, #0 8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2> 8000436: fbb1 fcf2 udiv ip, r1, r2 800043a: 0c01 lsrs r1, r0, #16 800043c: ea41 410e orr.w r1, r1, lr, lsl #16 8000440: b280 uxth r0, r0 8000442: ea40 4201 orr.w r2, r0, r1, lsl #16 8000446: 463b mov r3, r7 8000448: 4638 mov r0, r7 800044a: 463c mov r4, r7 800044c: 46b8 mov r8, r7 800044e: 46be mov lr, r7 8000450: 2620 movs r6, #32 8000452: fbb1 f1f7 udiv r1, r1, r7 8000456: eba2 0208 sub.w r2, r2, r8 800045a: ea41 410c orr.w r1, r1, ip, lsl #16 800045e: e766 b.n 800032e <__udivmoddi4+0xfa> 8000460: 4601 mov r1, r0 8000462: e718 b.n 8000296 <__udivmoddi4+0x62> 8000464: 4610 mov r0, r2 8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e> 8000468: f1c6 0220 rsb r2, r6, #32 800046c: fa2e f302 lsr.w r3, lr, r2 8000470: 40b7 lsls r7, r6 8000472: 40b1 lsls r1, r6 8000474: fa20 f202 lsr.w r2, r0, r2 8000478: ea4f 4e17 mov.w lr, r7, lsr #16 800047c: 430a orrs r2, r1 800047e: fbb3 f8fe udiv r8, r3, lr 8000482: b2bc uxth r4, r7 8000484: fb0e 3318 mls r3, lr, r8, r3 8000488: 0c11 lsrs r1, r2, #16 800048a: ea41 4103 orr.w r1, r1, r3, lsl #16 800048e: fb08 f904 mul.w r9, r8, r4 8000492: 40b0 lsls r0, r6 8000494: 4589 cmp r9, r1 8000496: ea4f 4310 mov.w r3, r0, lsr #16 800049a: b280 uxth r0, r0 800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8> 800049e: 1879 adds r1, r7, r1 80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276> 80004a6: 4589 cmp r9, r1 80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6> 80004aa: eba1 0109 sub.w r1, r1, r9 80004ae: fbb1 f9fe udiv r9, r1, lr 80004b2: fb09 f804 mul.w r8, r9, r4 80004b6: fb0e 1119 mls r1, lr, r9, r1 80004ba: b292 uxth r2, r2 80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16 80004c0: 4542 cmp r2, r8 80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4> 80004c4: 18ba adds r2, r7, r2 80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222> 80004cc: 4542 cmp r2, r8 80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222> 80004d0: f1a9 0102 sub.w r1, r9, #2 80004d4: 443a add r2, r7 80004d6: e7be b.n 8000456 <__udivmoddi4+0x222> 80004d8: 45f0 cmp r8, lr 80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4> 80004dc: ebbe 0302 subs.w r3, lr, r2 80004e0: eb6c 0c07 sbc.w ip, ip, r7 80004e4: 3801 subs r0, #1 80004e6: 46e1 mov r9, ip 80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4> 80004ea: eba7 0909 sub.w r9, r7, r9 80004ee: 4449 add r1, r9 80004f0: f1a8 0c02 sub.w ip, r8, #2 80004f4: fbb1 f9fe udiv r9, r1, lr 80004f8: fb09 f804 mul.w r8, r9, r4 80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282> 80004fe: 4673 mov r3, lr 8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce> 8000502: 4650 mov r0, sl 8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0> 8000506: 4608 mov r0, r1 8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2> 800050a: 443b add r3, r7 800050c: 3a02 subs r2, #2 800050e: e733 b.n 8000378 <__udivmoddi4+0x144> 8000510: f1ac 0c02 sub.w ip, ip, #2 8000514: 443b add r3, r7 8000516: e71c b.n 8000352 <__udivmoddi4+0x11e> 8000518: 4649 mov r1, r9 800051a: e79c b.n 8000456 <__udivmoddi4+0x222> 800051c: eba1 0109 sub.w r1, r1, r9 8000520: 46c4 mov ip, r8 8000522: fbb1 f9fe udiv r9, r1, lr 8000526: fb09 f804 mul.w r8, r9, r4 800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282> 0800052c <__aeabi_idiv0>: 800052c: 4770 bx lr 800052e: bf00 nop 08000530 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 8000530: b580 push {r7, lr} 8000532: b082 sub sp, #8 8000534: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8000536: 2300 movs r3, #0 8000538: 607b str r3, [r7, #4] 800053a: 4b2f ldr r3, [pc, #188] @ (80005f8 ) 800053c: 6b1b ldr r3, [r3, #48] @ 0x30 800053e: 4a2e ldr r2, [pc, #184] @ (80005f8 ) 8000540: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000544: 6313 str r3, [r2, #48] @ 0x30 8000546: 4b2c ldr r3, [pc, #176] @ (80005f8 ) 8000548: 6b1b ldr r3, [r3, #48] @ 0x30 800054a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800054e: 607b str r3, [r7, #4] 8000550: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); 8000552: 2300 movs r3, #0 8000554: 603b str r3, [r7, #0] 8000556: 4b28 ldr r3, [pc, #160] @ (80005f8 ) 8000558: 6b1b ldr r3, [r3, #48] @ 0x30 800055a: 4a27 ldr r2, [pc, #156] @ (80005f8 ) 800055c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8000560: 6313 str r3, [r2, #48] @ 0x30 8000562: 4b25 ldr r3, [pc, #148] @ (80005f8 ) 8000564: 6b1b ldr r3, [r3, #48] @ 0x30 8000566: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800056a: 603b str r3, [r7, #0] 800056c: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); 800056e: 2200 movs r2, #0 8000570: 2100 movs r1, #0 8000572: 200b movs r0, #11 8000574: f001 fb63 bl 8001c3e HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8000578: 200b movs r0, #11 800057a: f001 fb7c bl 8001c76 /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); 800057e: 2200 movs r2, #0 8000580: 2100 movs r1, #0 8000582: 200d movs r0, #13 8000584: f001 fb5b bl 8001c3e HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8000588: 200d movs r0, #13 800058a: f001 fb74 bl 8001c76 /* DMA1_Stream4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0); 800058e: 2200 movs r2, #0 8000590: 2100 movs r1, #0 8000592: 200f movs r0, #15 8000594: f001 fb53 bl 8001c3e HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); 8000598: 200f movs r0, #15 800059a: f001 fb6c bl 8001c76 /* DMA1_Stream5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); 800059e: 2200 movs r2, #0 80005a0: 2100 movs r1, #0 80005a2: 2010 movs r0, #16 80005a4: f001 fb4b bl 8001c3e HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); 80005a8: 2010 movs r0, #16 80005aa: f001 fb64 bl 8001c76 /* DMA1_Stream6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0); 80005ae: 2200 movs r2, #0 80005b0: 2100 movs r1, #0 80005b2: 2011 movs r0, #17 80005b4: f001 fb43 bl 8001c3e HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); 80005b8: 2011 movs r0, #17 80005ba: f001 fb5c bl 8001c76 /* DMA1_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0); 80005be: 2200 movs r2, #0 80005c0: 2100 movs r1, #0 80005c2: 202f movs r0, #47 @ 0x2f 80005c4: f001 fb3b bl 8001c3e HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); 80005c8: 202f movs r0, #47 @ 0x2f 80005ca: f001 fb54 bl 8001c76 /* DMA2_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); 80005ce: 2200 movs r2, #0 80005d0: 2100 movs r1, #0 80005d2: 203a movs r0, #58 @ 0x3a 80005d4: f001 fb33 bl 8001c3e HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); 80005d8: 203a movs r0, #58 @ 0x3a 80005da: f001 fb4c bl 8001c76 /* DMA2_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 80005de: 2200 movs r2, #0 80005e0: 2100 movs r1, #0 80005e2: 2046 movs r0, #70 @ 0x46 80005e4: f001 fb2b bl 8001c3e HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 80005e8: 2046 movs r0, #70 @ 0x46 80005ea: f001 fb44 bl 8001c76 } 80005ee: bf00 nop 80005f0: 3708 adds r7, #8 80005f2: 46bd mov sp, r7 80005f4: bd80 pop {r7, pc} 80005f6: bf00 nop 80005f8: 40023800 .word 0x40023800 080005fc : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 80005fc: b580 push {r7, lr} 80005fe: b08a sub sp, #40 @ 0x28 8000600: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000602: f107 0314 add.w r3, r7, #20 8000606: 2200 movs r2, #0 8000608: 601a str r2, [r3, #0] 800060a: 605a str r2, [r3, #4] 800060c: 609a str r2, [r3, #8] 800060e: 60da str r2, [r3, #12] 8000610: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8000612: 2300 movs r3, #0 8000614: 613b str r3, [r7, #16] 8000616: 4b45 ldr r3, [pc, #276] @ (800072c ) 8000618: 6b1b ldr r3, [r3, #48] @ 0x30 800061a: 4a44 ldr r2, [pc, #272] @ (800072c ) 800061c: f043 0380 orr.w r3, r3, #128 @ 0x80 8000620: 6313 str r3, [r2, #48] @ 0x30 8000622: 4b42 ldr r3, [pc, #264] @ (800072c ) 8000624: 6b1b ldr r3, [r3, #48] @ 0x30 8000626: f003 0380 and.w r3, r3, #128 @ 0x80 800062a: 613b str r3, [r7, #16] 800062c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800062e: 2300 movs r3, #0 8000630: 60fb str r3, [r7, #12] 8000632: 4b3e ldr r3, [pc, #248] @ (800072c ) 8000634: 6b1b ldr r3, [r3, #48] @ 0x30 8000636: 4a3d ldr r2, [pc, #244] @ (800072c ) 8000638: f043 0301 orr.w r3, r3, #1 800063c: 6313 str r3, [r2, #48] @ 0x30 800063e: 4b3b ldr r3, [pc, #236] @ (800072c ) 8000640: 6b1b ldr r3, [r3, #48] @ 0x30 8000642: f003 0301 and.w r3, r3, #1 8000646: 60fb str r3, [r7, #12] 8000648: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); 800064a: 2300 movs r3, #0 800064c: 60bb str r3, [r7, #8] 800064e: 4b37 ldr r3, [pc, #220] @ (800072c ) 8000650: 6b1b ldr r3, [r3, #48] @ 0x30 8000652: 4a36 ldr r2, [pc, #216] @ (800072c ) 8000654: f043 0304 orr.w r3, r3, #4 8000658: 6313 str r3, [r2, #48] @ 0x30 800065a: 4b34 ldr r3, [pc, #208] @ (800072c ) 800065c: 6b1b ldr r3, [r3, #48] @ 0x30 800065e: f003 0304 and.w r3, r3, #4 8000662: 60bb str r3, [r7, #8] 8000664: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000666: 2300 movs r3, #0 8000668: 607b str r3, [r7, #4] 800066a: 4b30 ldr r3, [pc, #192] @ (800072c ) 800066c: 6b1b ldr r3, [r3, #48] @ 0x30 800066e: 4a2f ldr r2, [pc, #188] @ (800072c ) 8000670: f043 0302 orr.w r3, r3, #2 8000674: 6313 str r3, [r2, #48] @ 0x30 8000676: 4b2d ldr r3, [pc, #180] @ (800072c ) 8000678: 6b1b ldr r3, [r3, #48] @ 0x30 800067a: f003 0302 and.w r3, r3, #2 800067e: 607b str r3, [r7, #4] 8000680: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000682: 2300 movs r3, #0 8000684: 603b str r3, [r7, #0] 8000686: 4b29 ldr r3, [pc, #164] @ (800072c ) 8000688: 6b1b ldr r3, [r3, #48] @ 0x30 800068a: 4a28 ldr r2, [pc, #160] @ (800072c ) 800068c: f043 0308 orr.w r3, r3, #8 8000690: 6313 str r3, [r2, #48] @ 0x30 8000692: 4b26 ldr r3, [pc, #152] @ (800072c ) 8000694: 6b1b ldr r3, [r3, #48] @ 0x30 8000696: f003 0308 and.w r3, r3, #8 800069a: 603b str r3, [r7, #0] 800069c: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET); 800069e: 2200 movs r2, #0 80006a0: f44f 7170 mov.w r1, #960 @ 0x3c0 80006a4: 4822 ldr r0, [pc, #136] @ (8000730 ) 80006a6: f002 f8af bl 8002808 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); 80006aa: 2200 movs r2, #0 80006ac: f44f 7180 mov.w r1, #256 @ 0x100 80006b0: 4820 ldr r0, [pc, #128] @ (8000734 ) 80006b2: f002 f8a9 bl 8002808 /*Configure GPIO pins : PC4 PC5 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80006b6: 2330 movs r3, #48 @ 0x30 80006b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006ba: 2300 movs r3, #0 80006bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006be: 2302 movs r3, #2 80006c0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006c2: f107 0314 add.w r3, r7, #20 80006c6: 4619 mov r1, r3 80006c8: 4819 ldr r0, [pc, #100] @ (8000730 ) 80006ca: f001 fef1 bl 80024b0 /*Configure GPIO pins : PB0 PB1 PB2 PB10 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10; 80006ce: f240 4307 movw r3, #1031 @ 0x407 80006d2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006d4: 2300 movs r3, #0 80006d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006d8: 2302 movs r3, #2 80006da: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80006dc: f107 0314 add.w r3, r7, #20 80006e0: 4619 mov r1, r3 80006e2: 4815 ldr r0, [pc, #84] @ (8000738 ) 80006e4: f001 fee4 bl 80024b0 /*Configure GPIO pins : PC6 PC7 PC8 PC9 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 80006e8: f44f 7370 mov.w r3, #960 @ 0x3c0 80006ec: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006ee: 2301 movs r3, #1 80006f0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80006f2: 2300 movs r3, #0 80006f4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80006f6: 2300 movs r3, #0 80006f8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006fa: f107 0314 add.w r3, r7, #20 80006fe: 4619 mov r1, r3 8000700: 480b ldr r0, [pc, #44] @ (8000730 ) 8000702: f001 fed5 bl 80024b0 /*Configure GPIO pin : PA8 */ GPIO_InitStruct.Pin = GPIO_PIN_8; 8000706: f44f 7380 mov.w r3, #256 @ 0x100 800070a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800070c: 2301 movs r3, #1 800070e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000710: 2300 movs r3, #0 8000712: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000714: 2300 movs r3, #0 8000716: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000718: f107 0314 add.w r3, r7, #20 800071c: 4619 mov r1, r3 800071e: 4805 ldr r0, [pc, #20] @ (8000734 ) 8000720: f001 fec6 bl 80024b0 } 8000724: bf00 nop 8000726: 3728 adds r7, #40 @ 0x28 8000728: 46bd mov sp, r7 800072a: bd80 pop {r7, pc} 800072c: 40023800 .word 0x40023800 8000730: 40020800 .word 0x40020800 8000734: 40020000 .word 0x40020000 8000738: 40020400 .word 0x40020400 0800073c : I2C_HandleTypeDef hi2c1; /* I2C1 init function */ void MX_I2C1_Init(void) { 800073c: b580 push {r7, lr} 800073e: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8000740: 4b12 ldr r3, [pc, #72] @ (800078c ) 8000742: 4a13 ldr r2, [pc, #76] @ (8000790 ) 8000744: 601a str r2, [r3, #0] hi2c1.Init.ClockSpeed = 100000; 8000746: 4b11 ldr r3, [pc, #68] @ (800078c ) 8000748: 4a12 ldr r2, [pc, #72] @ (8000794 ) 800074a: 605a str r2, [r3, #4] hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; 800074c: 4b0f ldr r3, [pc, #60] @ (800078c ) 800074e: 2200 movs r2, #0 8000750: 609a str r2, [r3, #8] hi2c1.Init.OwnAddress1 = 0; 8000752: 4b0e ldr r3, [pc, #56] @ (800078c ) 8000754: 2200 movs r2, #0 8000756: 60da str r2, [r3, #12] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8000758: 4b0c ldr r3, [pc, #48] @ (800078c ) 800075a: f44f 4280 mov.w r2, #16384 @ 0x4000 800075e: 611a str r2, [r3, #16] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000760: 4b0a ldr r3, [pc, #40] @ (800078c ) 8000762: 2200 movs r2, #0 8000764: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2 = 0; 8000766: 4b09 ldr r3, [pc, #36] @ (800078c ) 8000768: 2200 movs r2, #0 800076a: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 800076c: 4b07 ldr r3, [pc, #28] @ (800078c ) 800076e: 2200 movs r2, #0 8000770: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8000772: 4b06 ldr r3, [pc, #24] @ (800078c ) 8000774: 2200 movs r2, #0 8000776: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8000778: 4804 ldr r0, [pc, #16] @ (800078c ) 800077a: f002 f85f bl 800283c 800077e: 4603 mov r3, r0 8000780: 2b00 cmp r3, #0 8000782: d001 beq.n 8000788 { Error_Handler(); 8000784: f000 fb18 bl 8000db8 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8000788: bf00 nop 800078a: bd80 pop {r7, pc} 800078c: 200001bc .word 0x200001bc 8000790: 40005400 .word 0x40005400 8000794: 000186a0 .word 0x000186a0 08000798 : void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) { 8000798: b580 push {r7, lr} 800079a: b08a sub sp, #40 @ 0x28 800079c: af00 add r7, sp, #0 800079e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007a0: f107 0314 add.w r3, r7, #20 80007a4: 2200 movs r2, #0 80007a6: 601a str r2, [r3, #0] 80007a8: 605a str r2, [r3, #4] 80007aa: 609a str r2, [r3, #8] 80007ac: 60da str r2, [r3, #12] 80007ae: 611a str r2, [r3, #16] if(i2cHandle->Instance==I2C1) 80007b0: 687b ldr r3, [r7, #4] 80007b2: 681b ldr r3, [r3, #0] 80007b4: 4a19 ldr r2, [pc, #100] @ (800081c ) 80007b6: 4293 cmp r3, r2 80007b8: d12b bne.n 8000812 { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80007ba: 2300 movs r3, #0 80007bc: 613b str r3, [r7, #16] 80007be: 4b18 ldr r3, [pc, #96] @ (8000820 ) 80007c0: 6b1b ldr r3, [r3, #48] @ 0x30 80007c2: 4a17 ldr r2, [pc, #92] @ (8000820 ) 80007c4: f043 0302 orr.w r3, r3, #2 80007c8: 6313 str r3, [r2, #48] @ 0x30 80007ca: 4b15 ldr r3, [pc, #84] @ (8000820 ) 80007cc: 6b1b ldr r3, [r3, #48] @ 0x30 80007ce: f003 0302 and.w r3, r3, #2 80007d2: 613b str r3, [r7, #16] 80007d4: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80007d6: 23c0 movs r3, #192 @ 0xc0 80007d8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80007da: 2312 movs r3, #18 80007dc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80007de: 2300 movs r3, #0 80007e0: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80007e2: 2303 movs r3, #3 80007e4: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 80007e6: 2304 movs r3, #4 80007e8: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80007ea: f107 0314 add.w r3, r7, #20 80007ee: 4619 mov r1, r3 80007f0: 480c ldr r0, [pc, #48] @ (8000824 ) 80007f2: f001 fe5d bl 80024b0 /* I2C1 clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 80007f6: 2300 movs r3, #0 80007f8: 60fb str r3, [r7, #12] 80007fa: 4b09 ldr r3, [pc, #36] @ (8000820 ) 80007fc: 6c1b ldr r3, [r3, #64] @ 0x40 80007fe: 4a08 ldr r2, [pc, #32] @ (8000820 ) 8000800: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000804: 6413 str r3, [r2, #64] @ 0x40 8000806: 4b06 ldr r3, [pc, #24] @ (8000820 ) 8000808: 6c1b ldr r3, [r3, #64] @ 0x40 800080a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800080e: 60fb str r3, [r7, #12] 8000810: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8000812: bf00 nop 8000814: 3728 adds r7, #40 @ 0x28 8000816: 46bd mov sp, r7 8000818: bd80 pop {r7, pc} 800081a: bf00 nop 800081c: 40005400 .word 0x40005400 8000820: 40023800 .word 0x40023800 8000824: 40020400 .word 0x40020400 08000828
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000828: b580 push {r7, lr} 800082a: b088 sub sp, #32 800082c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800082e: f001 f895 bl 800195c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000832: f000 f8af bl 8000994 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000836: f7ff fee1 bl 80005fc MX_DMA_Init(); 800083a: f7ff fe79 bl 8000530 MX_TIM2_Init(); 800083e: f000 fbad bl 8000f9c MX_TIM3_Init(); 8000842: f000 fc03 bl 800104c MX_UART4_Init(); 8000846: f000 fcf5 bl 8001234 MX_UART5_Init(); 800084a: f000 fd1d bl 8001288 MX_USART1_UART_Init(); 800084e: f000 fd45 bl 80012dc MX_USART2_UART_Init(); 8000852: f000 fd6d bl 8001330 MX_I2C1_Init(); 8000856: f7ff ff71 bl 800073c MX_USB_DEVICE_Init(); 800085a: f009 fbbf bl 8009fdc /* USER CODE BEGIN 2 */ //Enable UART RX DMA for all ports HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 800085e: 2210 movs r2, #16 8000860: 493f ldr r1, [pc, #252] @ (8000960 ) 8000862: 4840 ldr r0, [pc, #256] @ (8000964 ) 8000864: f005 f9b6 bl 8005bd4 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000868: 2210 movs r2, #16 800086a: 493f ldr r1, [pc, #252] @ (8000968 ) 800086c: 483f ldr r0, [pc, #252] @ (800096c ) 800086e: f005 f9b1 bl 8005bd4 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000872: 2210 movs r2, #16 8000874: 493e ldr r1, [pc, #248] @ (8000970 ) 8000876: 483f ldr r0, [pc, #252] @ (8000974 ) 8000878: f005 f9ac bl 8005bd4 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 800087c: 2210 movs r2, #16 800087e: 493e ldr r1, [pc, #248] @ (8000978 ) 8000880: 483e ldr r0, [pc, #248] @ (800097c ) 8000882: f005 f9a7 bl 8005bd4 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { switch (MODE){ 8000886: 4b3e ldr r3, [pc, #248] @ (8000980 ) 8000888: 781b ldrb r3, [r3, #0] 800088a: b2db uxtb r3, r3 800088c: 2b02 cmp r3, #2 800088e: d006 beq.n 800089e 8000890: 2b02 cmp r3, #2 8000892: dc5f bgt.n 8000954 8000894: 2b00 cmp r3, #0 8000896: d01c beq.n 80008d2 8000898: 2b01 cmp r3, #1 800089a: d051 beq.n 8000940 matrixScan(); USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); break; default: break; 800089c: e05a b.n 8000954 resetReport(); 800089e: f000 fa7b bl 8000d98 matrixScan(); 80008a2: f000 fa1f bl 8000ce4 UARTREPORT.DEPTH = DEPTH; 80008a6: 4b37 ldr r3, [pc, #220] @ (8000984 ) 80008a8: 881b ldrh r3, [r3, #0] 80008aa: 823b strh r3, [r7, #16] UARTREPORT.TYPE = 0xEE; 80008ac: 23ee movs r3, #238 @ 0xee 80008ae: 827b strh r3, [r7, #18] memcpy(UARTREPORT.KEYPRESS, REPORT.KEYPRESS, sizeof(UARTREPORT.KEYPRESS)); 80008b0: 4a35 ldr r2, [pc, #212] @ (8000988 ) 80008b2: f107 0314 add.w r3, r7, #20 80008b6: 3202 adds r2, #2 80008b8: 6810 ldr r0, [r2, #0] 80008ba: 6851 ldr r1, [r2, #4] 80008bc: 6892 ldr r2, [r2, #8] 80008be: c307 stmia r3!, {r0, r1, r2} HAL_UART_Transmit_DMA(PARENT, (uint8_t*)&UARTREPORT, sizeof(UARTREPORT)); 80008c0: 4b32 ldr r3, [pc, #200] @ (800098c ) 80008c2: 681b ldr r3, [r3, #0] 80008c4: f107 0110 add.w r1, r7, #16 80008c8: 2210 movs r2, #16 80008ca: 4618 mov r0, r3 80008cc: f005 f906 bl 8005adc break; 80008d0: e041 b.n 8000956 if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){ 80008d2: 4b2f ldr r3, [pc, #188] @ (8000990 ) 80008d4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80008d8: b2db uxtb r3, r3 80008da: 2b03 cmp r3, #3 80008dc: d106 bne.n 80008ec MODE = MODE_MAINBOARD; 80008de: 4b28 ldr r3, [pc, #160] @ (8000980 ) 80008e0: 2201 movs r2, #1 80008e2: 701a strb r2, [r3, #0] DEPTH = 0; 80008e4: 4b27 ldr r3, [pc, #156] @ (8000984 ) 80008e6: 2200 movs r2, #0 80008e8: 801a strh r2, [r3, #0] break; 80008ea: e034 b.n 8000956 REQ.DEPTH = 0; 80008ec: 2300 movs r3, #0 80008ee: 803b strh r3, [r7, #0] REQ.TYPE = 0xFF; //Message code for request is 0xFF 80008f0: 23ff movs r3, #255 @ 0xff 80008f2: 807b strh r3, [r7, #2] memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS)); 80008f4: 463b mov r3, r7 80008f6: 3304 adds r3, #4 80008f8: 220c movs r2, #12 80008fa: 2100 movs r1, #0 80008fc: 4618 mov r0, r3 80008fe: f00a f81b bl 800a938 HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ)); 8000902: 463b mov r3, r7 8000904: 2210 movs r2, #16 8000906: 4619 mov r1, r3 8000908: 4816 ldr r0, [pc, #88] @ (8000964 ) 800090a: f005 f8e7 bl 8005adc HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ)); 800090e: 463b mov r3, r7 8000910: 2210 movs r2, #16 8000912: 4619 mov r1, r3 8000914: 4815 ldr r0, [pc, #84] @ (800096c ) 8000916: f005 f8e1 bl 8005adc HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); 800091a: 463b mov r3, r7 800091c: 2210 movs r2, #16 800091e: 4619 mov r1, r3 8000920: 4814 ldr r0, [pc, #80] @ (8000974 ) 8000922: f005 f8db bl 8005adc HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); 8000926: 463b mov r3, r7 8000928: 2210 movs r2, #16 800092a: 4619 mov r1, r3 800092c: 4813 ldr r0, [pc, #76] @ (800097c ) 800092e: f005 f8d5 bl 8005adc HAL_Delay(500); 8000932: f44f 70fa mov.w r0, #500 @ 0x1f4 8000936: f001 f883 bl 8001a40 findBestParent(); //So true... 800093a: f000 f8f3 bl 8000b24 break; 800093e: e00a b.n 8000956 resetReport(); 8000940: f000 fa2a bl 8000d98 matrixScan(); 8000944: f000 f9ce bl 8000ce4 USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); 8000948: 220e movs r2, #14 800094a: 490f ldr r1, [pc, #60] @ (8000988 ) 800094c: 4810 ldr r0, [pc, #64] @ (8000990 ) 800094e: f007 ff79 bl 8008844 break; 8000952: e000 b.n 8000956 break; 8000954: bf00 nop } HAL_Delay(50); 8000956: 2032 movs r0, #50 @ 0x32 8000958: f001 f872 bl 8001a40 switch (MODE){ 800095c: e793 b.n 8000886 800095e: bf00 nop 8000960: 20000230 .word 0x20000230 8000964: 2000038c .word 0x2000038c 8000968: 20000240 .word 0x20000240 800096c: 200003d4 .word 0x200003d4 8000970: 20000250 .word 0x20000250 8000974: 200002fc .word 0x200002fc 8000978: 20000220 .word 0x20000220 800097c: 20000344 .word 0x20000344 8000980: 20000268 .word 0x20000268 8000984: 20000260 .word 0x20000260 8000988: 20000210 .word 0x20000210 800098c: 20000264 .word 0x20000264 8000990: 20000724 .word 0x20000724 08000994 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000994: b580 push {r7, lr} 8000996: b094 sub sp, #80 @ 0x50 8000998: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800099a: f107 031c add.w r3, r7, #28 800099e: 2234 movs r2, #52 @ 0x34 80009a0: 2100 movs r1, #0 80009a2: 4618 mov r0, r3 80009a4: f009 ffc8 bl 800a938 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80009a8: f107 0308 add.w r3, r7, #8 80009ac: 2200 movs r2, #0 80009ae: 601a str r2, [r3, #0] 80009b0: 605a str r2, [r3, #4] 80009b2: 609a str r2, [r3, #8] 80009b4: 60da str r2, [r3, #12] 80009b6: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 80009b8: 2300 movs r3, #0 80009ba: 607b str r3, [r7, #4] 80009bc: 4b29 ldr r3, [pc, #164] @ (8000a64 ) 80009be: 6c1b ldr r3, [r3, #64] @ 0x40 80009c0: 4a28 ldr r2, [pc, #160] @ (8000a64 ) 80009c2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80009c6: 6413 str r3, [r2, #64] @ 0x40 80009c8: 4b26 ldr r3, [pc, #152] @ (8000a64 ) 80009ca: 6c1b ldr r3, [r3, #64] @ 0x40 80009cc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80009d0: 607b str r3, [r7, #4] 80009d2: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 80009d4: 2300 movs r3, #0 80009d6: 603b str r3, [r7, #0] 80009d8: 4b23 ldr r3, [pc, #140] @ (8000a68 ) 80009da: 681b ldr r3, [r3, #0] 80009dc: f423 4340 bic.w r3, r3, #49152 @ 0xc000 80009e0: 4a21 ldr r2, [pc, #132] @ (8000a68 ) 80009e2: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80009e6: 6013 str r3, [r2, #0] 80009e8: 4b1f ldr r3, [pc, #124] @ (8000a68 ) 80009ea: 681b ldr r3, [r3, #0] 80009ec: f403 4340 and.w r3, r3, #49152 @ 0xc000 80009f0: 603b str r3, [r7, #0] 80009f2: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 80009f4: 2301 movs r3, #1 80009f6: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80009f8: f44f 3380 mov.w r3, #65536 @ 0x10000 80009fc: 623b str r3, [r7, #32] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80009fe: 2302 movs r3, #2 8000a00: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000a02: f44f 0380 mov.w r3, #4194304 @ 0x400000 8000a06: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLM = 4; 8000a08: 2304 movs r3, #4 8000a0a: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLN = 96; 8000a0c: 2360 movs r3, #96 @ 0x60 8000a0e: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8000a10: 2302 movs r3, #2 8000a12: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLQ = 4; 8000a14: 2304 movs r3, #4 8000a16: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLR = 2; 8000a18: 2302 movs r3, #2 8000a1a: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000a1c: f107 031c add.w r3, r7, #28 8000a20: 4618 mov r0, r3 8000a22: f004 f949 bl 8004cb8 8000a26: 4603 mov r3, r0 8000a28: 2b00 cmp r3, #0 8000a2a: d001 beq.n 8000a30 { Error_Handler(); 8000a2c: f000 f9c4 bl 8000db8 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000a30: 230f movs r3, #15 8000a32: 60bb str r3, [r7, #8] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000a34: 2302 movs r3, #2 8000a36: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; 8000a38: 2380 movs r3, #128 @ 0x80 8000a3a: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000a3c: f44f 5380 mov.w r3, #4096 @ 0x1000 8000a40: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000a42: 2300 movs r3, #0 8000a44: 61bb str r3, [r7, #24] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000a46: f107 0308 add.w r3, r7, #8 8000a4a: 2101 movs r1, #1 8000a4c: 4618 mov r0, r3 8000a4e: f003 fabf bl 8003fd0 8000a52: 4603 mov r3, r0 8000a54: 2b00 cmp r3, #0 8000a56: d001 beq.n 8000a5c { Error_Handler(); 8000a58: f000 f9ae bl 8000db8 } } 8000a5c: bf00 nop 8000a5e: 3750 adds r7, #80 @ 0x50 8000a60: 46bd mov sp, r7 8000a62: bd80 pop {r7, pc} 8000a64: 40023800 .word 0x40023800 8000a68: 40007000 .word 0x40007000 08000a6c : /* USER CODE BEGIN 4 */ // UART Message Requests Goes Here void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8000a6c: b580 push {r7, lr} 8000a6e: b082 sub sp, #8 8000a70: af00 add r7, sp, #0 8000a72: 6078 str r0, [r7, #4] if (huart->Instance == USART1) { 8000a74: 687b ldr r3, [r7, #4] 8000a76: 681b ldr r3, [r3, #0] 8000a78: 4a1e ldr r2, [pc, #120] @ (8000af4 ) 8000a7a: 4293 cmp r3, r2 8000a7c: d109 bne.n 8000a92 handleUARTMessages((uint8_t*)&RX1Msg, &huart1); 8000a7e: 491e ldr r1, [pc, #120] @ (8000af8 ) 8000a80: 481e ldr r0, [pc, #120] @ (8000afc ) 8000a82: f000 f891 bl 8000ba8 HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000a86: 2210 movs r2, #16 8000a88: 491c ldr r1, [pc, #112] @ (8000afc ) 8000a8a: 481b ldr r0, [pc, #108] @ (8000af8 ) 8000a8c: f005 f8a2 bl 8005bd4 } else if (huart->Instance == UART5) { handleUARTMessages((uint8_t*)&RX5Msg, &huart5); HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000a90: e02b b.n 8000aea else if (huart->Instance == USART2) { 8000a92: 687b ldr r3, [r7, #4] 8000a94: 681b ldr r3, [r3, #0] 8000a96: 4a1a ldr r2, [pc, #104] @ (8000b00 ) 8000a98: 4293 cmp r3, r2 8000a9a: d109 bne.n 8000ab0 handleUARTMessages((uint8_t*)&RX2Msg, &huart2); 8000a9c: 4919 ldr r1, [pc, #100] @ (8000b04 ) 8000a9e: 481a ldr r0, [pc, #104] @ (8000b08 ) 8000aa0: f000 f882 bl 8000ba8 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000aa4: 2210 movs r2, #16 8000aa6: 4918 ldr r1, [pc, #96] @ (8000b08 ) 8000aa8: 4816 ldr r0, [pc, #88] @ (8000b04 ) 8000aaa: f005 f893 bl 8005bd4 } 8000aae: e01c b.n 8000aea else if (huart->Instance == UART4) { 8000ab0: 687b ldr r3, [r7, #4] 8000ab2: 681b ldr r3, [r3, #0] 8000ab4: 4a15 ldr r2, [pc, #84] @ (8000b0c ) 8000ab6: 4293 cmp r3, r2 8000ab8: d109 bne.n 8000ace handleUARTMessages((uint8_t*)&RX4Msg, &huart4); 8000aba: 4915 ldr r1, [pc, #84] @ (8000b10 ) 8000abc: 4815 ldr r0, [pc, #84] @ (8000b14 ) 8000abe: f000 f873 bl 8000ba8 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000ac2: 2210 movs r2, #16 8000ac4: 4913 ldr r1, [pc, #76] @ (8000b14 ) 8000ac6: 4812 ldr r0, [pc, #72] @ (8000b10 ) 8000ac8: f005 f884 bl 8005bd4 } 8000acc: e00d b.n 8000aea else if (huart->Instance == UART5) { 8000ace: 687b ldr r3, [r7, #4] 8000ad0: 681b ldr r3, [r3, #0] 8000ad2: 4a11 ldr r2, [pc, #68] @ (8000b18 ) 8000ad4: 4293 cmp r3, r2 8000ad6: d108 bne.n 8000aea handleUARTMessages((uint8_t*)&RX5Msg, &huart5); 8000ad8: 4910 ldr r1, [pc, #64] @ (8000b1c ) 8000ada: 4811 ldr r0, [pc, #68] @ (8000b20 ) 8000adc: f000 f864 bl 8000ba8 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000ae0: 2210 movs r2, #16 8000ae2: 490f ldr r1, [pc, #60] @ (8000b20 ) 8000ae4: 480d ldr r0, [pc, #52] @ (8000b1c ) 8000ae6: f005 f875 bl 8005bd4 } 8000aea: bf00 nop 8000aec: 3708 adds r7, #8 8000aee: 46bd mov sp, r7 8000af0: bd80 pop {r7, pc} 8000af2: bf00 nop 8000af4: 40011000 .word 0x40011000 8000af8: 2000038c .word 0x2000038c 8000afc: 20000230 .word 0x20000230 8000b00: 40004400 .word 0x40004400 8000b04: 200003d4 .word 0x200003d4 8000b08: 20000240 .word 0x20000240 8000b0c: 40004c00 .word 0x40004c00 8000b10: 200002fc .word 0x200002fc 8000b14: 20000250 .word 0x20000250 8000b18: 40005000 .word 0x40005000 8000b1c: 20000344 .word 0x20000344 8000b20: 20000220 .word 0x20000220 08000b24 : void findBestParent(){ 8000b24: b580 push {r7, lr} 8000b26: b084 sub sp, #16 8000b28: af00 add r7, sp, #0 //Find least depth parent uint16_t least_val = 0xFF; 8000b2a: 23ff movs r3, #255 @ 0xff 8000b2c: 81fb strh r3, [r7, #14] UART_HandleTypeDef* least_port = NULL; 8000b2e: 2300 movs r3, #0 8000b30: 60bb str r3, [r7, #8] for(uint8_t i = 0; i < 4; i++){ 8000b32: 2300 movs r3, #0 8000b34: 71fb strb r3, [r7, #7] 8000b36: e013 b.n 8000b60 if(PORT_DEPTH[i]) 8000b3c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000b40: 89fa ldrh r2, [r7, #14] 8000b42: 429a cmp r2, r3 8000b44: d909 bls.n 8000b5a least_port = PORTS[i]; 8000b46: 79fb ldrb r3, [r7, #7] 8000b48: 4a13 ldr r2, [pc, #76] @ (8000b98 ) 8000b4a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000b4e: 60bb str r3, [r7, #8] least_val = PORT_DEPTH[i]; 8000b50: 79fb ldrb r3, [r7, #7] 8000b52: 4a10 ldr r2, [pc, #64] @ (8000b94 ) 8000b54: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000b58: 81fb strh r3, [r7, #14] for(uint8_t i = 0; i < 4; i++){ 8000b5a: 79fb ldrb r3, [r7, #7] 8000b5c: 3301 adds r3, #1 8000b5e: 71fb strb r3, [r7, #7] 8000b60: 79fb ldrb r3, [r7, #7] 8000b62: 2b03 cmp r3, #3 8000b64: d9e8 bls.n 8000b38 } } //Assign if valid if(least_val < 0xFF){ 8000b66: 89fb ldrh r3, [r7, #14] 8000b68: 2bfe cmp r3, #254 @ 0xfe 8000b6a: d80e bhi.n 8000b8a PARENT = least_port; 8000b6c: 4a0b ldr r2, [pc, #44] @ (8000b9c ) 8000b6e: 68bb ldr r3, [r7, #8] 8000b70: 6013 str r3, [r2, #0] DEPTH = least_val + 1; 8000b72: 89fb ldrh r3, [r7, #14] 8000b74: 3301 adds r3, #1 8000b76: b29a uxth r2, r3 8000b78: 4b09 ldr r3, [pc, #36] @ (8000ba0 ) 8000b7a: 801a strh r2, [r3, #0] MODE = MODE_ACTIVE; 8000b7c: 4b09 ldr r3, [pc, #36] @ (8000ba4 ) 8000b7e: 2202 movs r2, #2 8000b80: 701a strb r2, [r3, #0] HAL_Delay(500); 8000b82: f44f 70fa mov.w r0, #500 @ 0x1f4 8000b86: f000 ff5b bl 8001a40 } } 8000b8a: bf00 nop 8000b8c: 3710 adds r7, #16 8000b8e: 46bd mov sp, r7 8000b90: bd80 pop {r7, pc} 8000b92: bf00 nop 8000b94: 20000078 .word 0x20000078 8000b98: 20000080 .word 0x20000080 8000b9c: 20000264 .word 0x20000264 8000ba0: 20000260 .word 0x20000260 8000ba4: 20000268 .word 0x20000268 08000ba8 : // Called when UART RX interrupt completes void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender) { 8000ba8: b580 push {r7, lr} 8000baa: b08a sub sp, #40 @ 0x28 8000bac: af00 add r7, sp, #0 8000bae: 6078 str r0, [r7, #4] 8000bb0: 6039 str r1, [r7, #0] UARTMessage msg; UARTMessage reply; // Parse incoming message into struct memcpy(&msg, data, sizeof(UARTMessage)); 8000bb2: f107 0318 add.w r3, r7, #24 8000bb6: 2210 movs r2, #16 8000bb8: 6879 ldr r1, [r7, #4] 8000bba: 4618 mov r0, r3 8000bbc: f009 fee8 bl 800a990 switch(msg.TYPE) { 8000bc0: 8b7b ldrh r3, [r7, #26] 8000bc2: 2bff cmp r3, #255 @ 0xff 8000bc4: d026 beq.n 8000c14 8000bc6: 2bff cmp r3, #255 @ 0xff 8000bc8: dc3e bgt.n 8000c48 8000bca: 2baa cmp r3, #170 @ 0xaa 8000bcc: d002 beq.n 8000bd4 8000bce: 2bee cmp r3, #238 @ 0xee 8000bd0: d03c beq.n 8000c4c case 0xEE: //TODO: Append message to the thingy break; default: break; 8000bd2: e039 b.n 8000c48 if(sender == &huart5) { 8000bd4: 683b ldr r3, [r7, #0] 8000bd6: 4a22 ldr r2, [pc, #136] @ (8000c60 ) 8000bd8: 4293 cmp r3, r2 8000bda: d103 bne.n 8000be4 PORT_DEPTH[0] = msg.DEPTH; 8000bdc: 8b3a ldrh r2, [r7, #24] 8000bde: 4b21 ldr r3, [pc, #132] @ (8000c64 ) 8000be0: 801a strh r2, [r3, #0] break; 8000be2: e035 b.n 8000c50 } else if(sender == &huart1) { 8000be4: 683b ldr r3, [r7, #0] 8000be6: 4a20 ldr r2, [pc, #128] @ (8000c68 ) 8000be8: 4293 cmp r3, r2 8000bea: d103 bne.n 8000bf4 PORT_DEPTH[1] = msg.DEPTH; 8000bec: 8b3a ldrh r2, [r7, #24] 8000bee: 4b1d ldr r3, [pc, #116] @ (8000c64 ) 8000bf0: 805a strh r2, [r3, #2] break; 8000bf2: e02d b.n 8000c50 } else if(sender == &huart2) { 8000bf4: 683b ldr r3, [r7, #0] 8000bf6: 4a1d ldr r2, [pc, #116] @ (8000c6c ) 8000bf8: 4293 cmp r3, r2 8000bfa: d103 bne.n 8000c04 PORT_DEPTH[2] = msg.DEPTH; 8000bfc: 8b3a ldrh r2, [r7, #24] 8000bfe: 4b19 ldr r3, [pc, #100] @ (8000c64 ) 8000c00: 809a strh r2, [r3, #4] break; 8000c02: e025 b.n 8000c50 } else if(sender == &huart4) { 8000c04: 683b ldr r3, [r7, #0] 8000c06: 4a1a ldr r2, [pc, #104] @ (8000c70 ) 8000c08: 4293 cmp r3, r2 8000c0a: d121 bne.n 8000c50 PORT_DEPTH[3] = msg.DEPTH; 8000c0c: 8b3a ldrh r2, [r7, #24] 8000c0e: 4b15 ldr r3, [pc, #84] @ (8000c64 ) 8000c10: 80da strh r2, [r3, #6] break; 8000c12: e01d b.n 8000c50 if(MODE!=MODE_INACTIVE){ 8000c14: 4b17 ldr r3, [pc, #92] @ (8000c74 ) 8000c16: 781b ldrb r3, [r3, #0] 8000c18: b2db uxtb r3, r3 8000c1a: 2b00 cmp r3, #0 8000c1c: d01a beq.n 8000c54 reply.TYPE = 0xAA; 8000c1e: 23aa movs r3, #170 @ 0xaa 8000c20: 817b strh r3, [r7, #10] reply.DEPTH = DEPTH; // use your local DEPTH 8000c22: 4b15 ldr r3, [pc, #84] @ (8000c78 ) 8000c24: 881b ldrh r3, [r3, #0] 8000c26: 813b strh r3, [r7, #8] memset(reply.KEYPRESS, 0, sizeof(reply.KEYPRESS)); 8000c28: f107 0308 add.w r3, r7, #8 8000c2c: 3304 adds r3, #4 8000c2e: 220c movs r2, #12 8000c30: 2100 movs r1, #0 8000c32: 4618 mov r0, r3 8000c34: f009 fe80 bl 800a938 HAL_UART_Transmit_DMA(sender, (uint8_t*)&reply, sizeof(reply)); 8000c38: f107 0308 add.w r3, r7, #8 8000c3c: 2210 movs r2, #16 8000c3e: 4619 mov r1, r3 8000c40: 6838 ldr r0, [r7, #0] 8000c42: f004 ff4b bl 8005adc break; 8000c46: e005 b.n 8000c54 break; 8000c48: bf00 nop 8000c4a: e004 b.n 8000c56 break; 8000c4c: bf00 nop 8000c4e: e002 b.n 8000c56 break; 8000c50: bf00 nop 8000c52: e000 b.n 8000c56 break; 8000c54: bf00 nop } } 8000c56: bf00 nop 8000c58: 3728 adds r7, #40 @ 0x28 8000c5a: 46bd mov sp, r7 8000c5c: bd80 pop {r7, pc} 8000c5e: bf00 nop 8000c60: 20000344 .word 0x20000344 8000c64: 20000078 .word 0x20000078 8000c68: 2000038c .word 0x2000038c 8000c6c: 200003d4 .word 0x200003d4 8000c70: 200002fc .word 0x200002fc 8000c74: 20000268 .word 0x20000268 8000c78: 20000260 .word 0x20000260 08000c7c : void addUSBReport(uint8_t usageID){ 8000c7c: b480 push {r7} 8000c7e: b085 sub sp, #20 8000c80: af00 add r7, sp, #0 8000c82: 4603 mov r3, r0 8000c84: 71fb strb r3, [r7, #7] if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8000c86: 79fb ldrb r3, [r7, #7] 8000c88: 2b03 cmp r3, #3 8000c8a: d922 bls.n 8000cd2 8000c8c: 79fb ldrb r3, [r7, #7] 8000c8e: 2b73 cmp r3, #115 @ 0x73 8000c90: d81f bhi.n 8000cd2 uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit 8000c92: 79fb ldrb r3, [r7, #7] 8000c94: b29b uxth r3, r3 8000c96: 3b04 subs r3, #4 8000c98: 81fb strh r3, [r7, #14] uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array 8000c9a: 89fb ldrh r3, [r7, #14] 8000c9c: 08db lsrs r3, r3, #3 8000c9e: b29b uxth r3, r3 8000ca0: 737b strb r3, [r7, #13] uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset 8000ca2: 89fb ldrh r3, [r7, #14] 8000ca4: b2db uxtb r3, r3 8000ca6: f003 0307 and.w r3, r3, #7 8000caa: 733b strb r3, [r7, #12] REPORT.KEYPRESS[byte_index] |= (1 << bit_offset); 8000cac: 7b7b ldrb r3, [r7, #13] 8000cae: 4a0c ldr r2, [pc, #48] @ (8000ce0 ) 8000cb0: 4413 add r3, r2 8000cb2: 789b ldrb r3, [r3, #2] 8000cb4: b25a sxtb r2, r3 8000cb6: 7b3b ldrb r3, [r7, #12] 8000cb8: 2101 movs r1, #1 8000cba: fa01 f303 lsl.w r3, r1, r3 8000cbe: b25b sxtb r3, r3 8000cc0: 4313 orrs r3, r2 8000cc2: b25a sxtb r2, r3 8000cc4: 7b7b ldrb r3, [r7, #13] 8000cc6: b2d1 uxtb r1, r2 8000cc8: 4a05 ldr r2, [pc, #20] @ (8000ce0 ) 8000cca: 4413 add r3, r2 8000ccc: 460a mov r2, r1 8000cce: 709a strb r2, [r3, #2] 8000cd0: e000 b.n 8000cd4 if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8000cd2: bf00 nop } 8000cd4: 3714 adds r7, #20 8000cd6: 46bd mov sp, r7 8000cd8: f85d 7b04 ldr.w r7, [sp], #4 8000cdc: 4770 bx lr 8000cde: bf00 nop 8000ce0: 20000210 .word 0x20000210 08000ce4 : void matrixScan(void){ 8000ce4: b580 push {r7, lr} 8000ce6: b082 sub sp, #8 8000ce8: af00 add r7, sp, #0 for (uint8_t col = 0; col < COL; col++){ 8000cea: 2300 movs r3, #0 8000cec: 71fb strb r3, [r7, #7] 8000cee: e044 b.n 8000d7a HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET); 8000cf0: 79fb ldrb r3, [r7, #7] 8000cf2: 4a26 ldr r2, [pc, #152] @ (8000d8c ) 8000cf4: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000cf8: 79fb ldrb r3, [r7, #7] 8000cfa: 4a24 ldr r2, [pc, #144] @ (8000d8c ) 8000cfc: 00db lsls r3, r3, #3 8000cfe: 4413 add r3, r2 8000d00: 889b ldrh r3, [r3, #4] 8000d02: 2201 movs r2, #1 8000d04: 4619 mov r1, r3 8000d06: f001 fd7f bl 8002808 HAL_Delay(1); 8000d0a: 2001 movs r0, #1 8000d0c: f000 fe98 bl 8001a40 for(uint8_t row = 0; row < ROW; row++){ 8000d10: 2300 movs r3, #0 8000d12: 71bb strb r3, [r7, #6] 8000d14: e01e b.n 8000d54 if(HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN)){ 8000d16: 79bb ldrb r3, [r7, #6] 8000d18: 4a1d ldr r2, [pc, #116] @ (8000d90 ) 8000d1a: f852 2033 ldr.w r2, [r2, r3, lsl #3] 8000d1e: 79bb ldrb r3, [r7, #6] 8000d20: 491b ldr r1, [pc, #108] @ (8000d90 ) 8000d22: 00db lsls r3, r3, #3 8000d24: 440b add r3, r1 8000d26: 889b ldrh r3, [r3, #4] 8000d28: 4619 mov r1, r3 8000d2a: 4610 mov r0, r2 8000d2c: f001 fd54 bl 80027d8 8000d30: 4603 mov r3, r0 8000d32: 2b00 cmp r3, #0 8000d34: d00b beq.n 8000d4e addUSBReport(KEYCODES[row][col]); 8000d36: 79ba ldrb r2, [r7, #6] 8000d38: 79f9 ldrb r1, [r7, #7] 8000d3a: 4816 ldr r0, [pc, #88] @ (8000d94 ) 8000d3c: 4613 mov r3, r2 8000d3e: 009b lsls r3, r3, #2 8000d40: 4413 add r3, r2 8000d42: 4403 add r3, r0 8000d44: 440b add r3, r1 8000d46: 781b ldrb r3, [r3, #0] 8000d48: 4618 mov r0, r3 8000d4a: f7ff ff97 bl 8000c7c for(uint8_t row = 0; row < ROW; row++){ 8000d4e: 79bb ldrb r3, [r7, #6] 8000d50: 3301 adds r3, #1 8000d52: 71bb strb r3, [r7, #6] 8000d54: 79bb ldrb r3, [r7, #6] 8000d56: 2b05 cmp r3, #5 8000d58: d9dd bls.n 8000d16 } } HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET); 8000d5a: 79fb ldrb r3, [r7, #7] 8000d5c: 4a0b ldr r2, [pc, #44] @ (8000d8c ) 8000d5e: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000d62: 79fb ldrb r3, [r7, #7] 8000d64: 4a09 ldr r2, [pc, #36] @ (8000d8c ) 8000d66: 00db lsls r3, r3, #3 8000d68: 4413 add r3, r2 8000d6a: 889b ldrh r3, [r3, #4] 8000d6c: 2200 movs r2, #0 8000d6e: 4619 mov r1, r3 8000d70: f001 fd4a bl 8002808 for (uint8_t col = 0; col < COL; col++){ 8000d74: 79fb ldrb r3, [r7, #7] 8000d76: 3301 adds r3, #1 8000d78: 71fb strb r3, [r7, #7] 8000d7a: 79fb ldrb r3, [r7, #7] 8000d7c: 2b04 cmp r3, #4 8000d7e: d9b7 bls.n 8000cf0 } } 8000d80: bf00 nop 8000d82: bf00 nop 8000d84: 3708 adds r7, #8 8000d86: 46bd mov sp, r7 8000d88: bd80 pop {r7, pc} 8000d8a: bf00 nop 8000d8c: 20000030 .word 0x20000030 8000d90: 20000000 .word 0x20000000 8000d94: 20000058 .word 0x20000058 08000d98 : void resetReport(void){ 8000d98: b580 push {r7, lr} 8000d9a: af00 add r7, sp, #0 REPORT.MODIFIER = 0; 8000d9c: 4b04 ldr r3, [pc, #16] @ (8000db0 ) 8000d9e: 2200 movs r2, #0 8000da0: 701a strb r2, [r3, #0] memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS)); 8000da2: 220c movs r2, #12 8000da4: 2100 movs r1, #0 8000da6: 4803 ldr r0, [pc, #12] @ (8000db4 ) 8000da8: f009 fdc6 bl 800a938 } 8000dac: bf00 nop 8000dae: bd80 pop {r7, pc} 8000db0: 20000210 .word 0x20000210 8000db4: 20000212 .word 0x20000212 08000db8 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000db8: b480 push {r7} 8000dba: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000dbc: b672 cpsid i } 8000dbe: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000dc0: bf00 nop 8000dc2: e7fd b.n 8000dc0 08000dc4 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000dc4: b480 push {r7} 8000dc6: b083 sub sp, #12 8000dc8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000dca: 2300 movs r3, #0 8000dcc: 607b str r3, [r7, #4] 8000dce: 4b10 ldr r3, [pc, #64] @ (8000e10 ) 8000dd0: 6c5b ldr r3, [r3, #68] @ 0x44 8000dd2: 4a0f ldr r2, [pc, #60] @ (8000e10 ) 8000dd4: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000dd8: 6453 str r3, [r2, #68] @ 0x44 8000dda: 4b0d ldr r3, [pc, #52] @ (8000e10 ) 8000ddc: 6c5b ldr r3, [r3, #68] @ 0x44 8000dde: f403 4380 and.w r3, r3, #16384 @ 0x4000 8000de2: 607b str r3, [r7, #4] 8000de4: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000de6: 2300 movs r3, #0 8000de8: 603b str r3, [r7, #0] 8000dea: 4b09 ldr r3, [pc, #36] @ (8000e10 ) 8000dec: 6c1b ldr r3, [r3, #64] @ 0x40 8000dee: 4a08 ldr r2, [pc, #32] @ (8000e10 ) 8000df0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000df4: 6413 str r3, [r2, #64] @ 0x40 8000df6: 4b06 ldr r3, [pc, #24] @ (8000e10 ) 8000df8: 6c1b ldr r3, [r3, #64] @ 0x40 8000dfa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000dfe: 603b str r3, [r7, #0] 8000e00: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000e02: bf00 nop 8000e04: 370c adds r7, #12 8000e06: 46bd mov sp, r7 8000e08: f85d 7b04 ldr.w r7, [sp], #4 8000e0c: 4770 bx lr 8000e0e: bf00 nop 8000e10: 40023800 .word 0x40023800 08000e14 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000e14: b480 push {r7} 8000e16: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000e18: bf00 nop 8000e1a: e7fd b.n 8000e18 08000e1c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000e1c: b480 push {r7} 8000e1e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000e20: bf00 nop 8000e22: e7fd b.n 8000e20 08000e24 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000e24: b480 push {r7} 8000e26: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000e28: bf00 nop 8000e2a: e7fd b.n 8000e28 08000e2c : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000e2c: b480 push {r7} 8000e2e: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000e30: bf00 nop 8000e32: e7fd b.n 8000e30 08000e34 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000e34: b480 push {r7} 8000e36: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000e38: bf00 nop 8000e3a: e7fd b.n 8000e38 08000e3c : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000e3c: b480 push {r7} 8000e3e: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000e40: bf00 nop 8000e42: 46bd mov sp, r7 8000e44: f85d 7b04 ldr.w r7, [sp], #4 8000e48: 4770 bx lr 08000e4a : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000e4a: b480 push {r7} 8000e4c: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000e4e: bf00 nop 8000e50: 46bd mov sp, r7 8000e52: f85d 7b04 ldr.w r7, [sp], #4 8000e56: 4770 bx lr 08000e58 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000e58: b480 push {r7} 8000e5a: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000e5c: bf00 nop 8000e5e: 46bd mov sp, r7 8000e60: f85d 7b04 ldr.w r7, [sp], #4 8000e64: 4770 bx lr 08000e66 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000e66: b580 push {r7, lr} 8000e68: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000e6a: f000 fdc9 bl 8001a00 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000e6e: bf00 nop 8000e70: bd80 pop {r7, pc} ... 08000e74 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8000e74: b580 push {r7, lr} 8000e76: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_rx); 8000e78: 4802 ldr r0, [pc, #8] @ (8000e84 ) 8000e7a: f001 f8af bl 8001fdc /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 8000e7e: bf00 nop 8000e80: bd80 pop {r7, pc} 8000e82: bf00 nop 8000e84: 200004dc .word 0x200004dc 08000e88 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 8000e88: b580 push {r7, lr} 8000e8a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_rx); 8000e8c: 4802 ldr r0, [pc, #8] @ (8000e98 ) 8000e8e: f001 f8a5 bl 8001fdc /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 8000e92: bf00 nop 8000e94: bd80 pop {r7, pc} 8000e96: bf00 nop 8000e98: 2000041c .word 0x2000041c 08000e9c : /** * @brief This function handles DMA1 stream4 global interrupt. */ void DMA1_Stream4_IRQHandler(void) { 8000e9c: b580 push {r7, lr} 8000e9e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ /* USER CODE END DMA1_Stream4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_tx); 8000ea0: 4802 ldr r0, [pc, #8] @ (8000eac ) 8000ea2: f001 f89b bl 8001fdc /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ /* USER CODE END DMA1_Stream4_IRQn 1 */ } 8000ea6: bf00 nop 8000ea8: bd80 pop {r7, pc} 8000eaa: bf00 nop 8000eac: 2000047c .word 0x2000047c 08000eb0 : /** * @brief This function handles DMA1 stream5 global interrupt. */ void DMA1_Stream5_IRQHandler(void) { 8000eb0: b580 push {r7, lr} 8000eb2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ /* USER CODE END DMA1_Stream5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 8000eb4: 4802 ldr r0, [pc, #8] @ (8000ec0 ) 8000eb6: f001 f891 bl 8001fdc /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ /* USER CODE END DMA1_Stream5_IRQn 1 */ } 8000eba: bf00 nop 8000ebc: bd80 pop {r7, pc} 8000ebe: bf00 nop 8000ec0: 2000065c .word 0x2000065c 08000ec4 : /** * @brief This function handles DMA1 stream6 global interrupt. */ void DMA1_Stream6_IRQHandler(void) { 8000ec4: b580 push {r7, lr} 8000ec6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ /* USER CODE END DMA1_Stream6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 8000ec8: 4802 ldr r0, [pc, #8] @ (8000ed4 ) 8000eca: f001 f887 bl 8001fdc /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ /* USER CODE END DMA1_Stream6_IRQn 1 */ } 8000ece: bf00 nop 8000ed0: bd80 pop {r7, pc} 8000ed2: bf00 nop 8000ed4: 200006bc .word 0x200006bc 08000ed8 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8000ed8: b580 push {r7, lr} 8000eda: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8000edc: 4802 ldr r0, [pc, #8] @ (8000ee8 ) 8000ede: f004 fe9f bl 8005c20 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8000ee2: bf00 nop 8000ee4: bd80 pop {r7, pc} 8000ee6: bf00 nop 8000ee8: 2000038c .word 0x2000038c 08000eec : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 8000eec: b580 push {r7, lr} 8000eee: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 8000ef0: 4802 ldr r0, [pc, #8] @ (8000efc ) 8000ef2: f004 fe95 bl 8005c20 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 8000ef6: bf00 nop 8000ef8: bd80 pop {r7, pc} 8000efa: bf00 nop 8000efc: 200003d4 .word 0x200003d4 08000f00 : /** * @brief This function handles DMA1 stream7 global interrupt. */ void DMA1_Stream7_IRQHandler(void) { 8000f00: b580 push {r7, lr} 8000f02: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ /* USER CODE END DMA1_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_tx); 8000f04: 4802 ldr r0, [pc, #8] @ (8000f10 ) 8000f06: f001 f869 bl 8001fdc /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ /* USER CODE END DMA1_Stream7_IRQn 1 */ } 8000f0a: bf00 nop 8000f0c: bd80 pop {r7, pc} 8000f0e: bf00 nop 8000f10: 2000053c .word 0x2000053c 08000f14 : /** * @brief This function handles UART4 global interrupt. */ void UART4_IRQHandler(void) { 8000f14: b580 push {r7, lr} 8000f16: af00 add r7, sp, #0 /* USER CODE BEGIN UART4_IRQn 0 */ /* USER CODE END UART4_IRQn 0 */ HAL_UART_IRQHandler(&huart4); 8000f18: 4802 ldr r0, [pc, #8] @ (8000f24 ) 8000f1a: f004 fe81 bl 8005c20 /* USER CODE BEGIN UART4_IRQn 1 */ /* USER CODE END UART4_IRQn 1 */ } 8000f1e: bf00 nop 8000f20: bd80 pop {r7, pc} 8000f22: bf00 nop 8000f24: 200002fc .word 0x200002fc 08000f28 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 8000f28: b580 push {r7, lr} 8000f2a: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 8000f2c: 4802 ldr r0, [pc, #8] @ (8000f38 ) 8000f2e: f004 fe77 bl 8005c20 /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 8000f32: bf00 nop 8000f34: bd80 pop {r7, pc} 8000f36: bf00 nop 8000f38: 20000344 .word 0x20000344 08000f3c : /** * @brief This function handles DMA2 stream2 global interrupt. */ void DMA2_Stream2_IRQHandler(void) { 8000f3c: b580 push {r7, lr} 8000f3e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ /* USER CODE END DMA2_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_rx); 8000f40: 4802 ldr r0, [pc, #8] @ (8000f4c ) 8000f42: f001 f84b bl 8001fdc /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ /* USER CODE END DMA2_Stream2_IRQn 1 */ } 8000f46: bf00 nop 8000f48: bd80 pop {r7, pc} 8000f4a: bf00 nop 8000f4c: 2000059c .word 0x2000059c 08000f50 : /** * @brief This function handles USB On The Go FS global interrupt. */ void OTG_FS_IRQHandler(void) { 8000f50: b580 push {r7, lr} 8000f52: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_FS_IRQn 0 */ /* USER CODE END OTG_FS_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); 8000f54: 4802 ldr r0, [pc, #8] @ (8000f60 ) 8000f56: f001 ff00 bl 8002d5a /* USER CODE BEGIN OTG_FS_IRQn 1 */ /* USER CODE END OTG_FS_IRQn 1 */ } 8000f5a: bf00 nop 8000f5c: bd80 pop {r7, pc} 8000f5e: bf00 nop 8000f60: 20000c00 .word 0x20000c00 08000f64 : /** * @brief This function handles DMA2 stream7 global interrupt. */ void DMA2_Stream7_IRQHandler(void) { 8000f64: b580 push {r7, lr} 8000f66: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ /* USER CODE END DMA2_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 8000f68: 4802 ldr r0, [pc, #8] @ (8000f74 ) 8000f6a: f001 f837 bl 8001fdc /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ /* USER CODE END DMA2_Stream7_IRQn 1 */ } 8000f6e: bf00 nop 8000f70: bd80 pop {r7, pc} 8000f72: bf00 nop 8000f74: 200005fc .word 0x200005fc 08000f78 : * configuration. * @param None * @retval None */ void SystemInit(void) { 8000f78: b480 push {r7} 8000f7a: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8000f7c: 4b06 ldr r3, [pc, #24] @ (8000f98 ) 8000f7e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8000f82: 4a05 ldr r2, [pc, #20] @ (8000f98 ) 8000f84: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8000f88: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8000f8c: bf00 nop 8000f8e: 46bd mov sp, r7 8000f90: f85d 7b04 ldr.w r7, [sp], #4 8000f94: 4770 bx lr 8000f96: bf00 nop 8000f98: e000ed00 .word 0xe000ed00 08000f9c : TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; /* TIM2 init function */ void MX_TIM2_Init(void) { 8000f9c: b580 push {r7, lr} 8000f9e: b08a sub sp, #40 @ 0x28 8000fa0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000fa2: f107 0320 add.w r3, r7, #32 8000fa6: 2200 movs r2, #0 8000fa8: 601a str r2, [r3, #0] 8000faa: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 8000fac: 1d3b adds r3, r7, #4 8000fae: 2200 movs r2, #0 8000fb0: 601a str r2, [r3, #0] 8000fb2: 605a str r2, [r3, #4] 8000fb4: 609a str r2, [r3, #8] 8000fb6: 60da str r2, [r3, #12] 8000fb8: 611a str r2, [r3, #16] 8000fba: 615a str r2, [r3, #20] 8000fbc: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 8000fbe: 4b22 ldr r3, [pc, #136] @ (8001048 ) 8000fc0: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 8000fc4: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 8000fc6: 4b20 ldr r3, [pc, #128] @ (8001048 ) 8000fc8: 2200 movs r2, #0 8000fca: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8000fcc: 4b1e ldr r3, [pc, #120] @ (8001048 ) 8000fce: 2200 movs r2, #0 8000fd0: 609a str r2, [r3, #8] htim2.Init.Period = 4294967295; 8000fd2: 4b1d ldr r3, [pc, #116] @ (8001048 ) 8000fd4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000fd8: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000fda: 4b1b ldr r3, [pc, #108] @ (8001048 ) 8000fdc: 2200 movs r2, #0 8000fde: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000fe0: 4b19 ldr r3, [pc, #100] @ (8001048 ) 8000fe2: 2200 movs r2, #0 8000fe4: 619a str r2, [r3, #24] if (HAL_TIM_OC_Init(&htim2) != HAL_OK) 8000fe6: 4818 ldr r0, [pc, #96] @ (8001048 ) 8000fe8: f004 f904 bl 80051f4 8000fec: 4603 mov r3, r0 8000fee: 2b00 cmp r3, #0 8000ff0: d001 beq.n 8000ff6 { Error_Handler(); 8000ff2: f7ff fee1 bl 8000db8 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000ff6: 2300 movs r3, #0 8000ff8: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000ffa: 2300 movs r3, #0 8000ffc: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8000ffe: f107 0320 add.w r3, r7, #32 8001002: 4619 mov r1, r3 8001004: 4810 ldr r0, [pc, #64] @ (8001048 ) 8001006: f004 fc9d bl 8005944 800100a: 4603 mov r3, r0 800100c: 2b00 cmp r3, #0 800100e: d001 beq.n 8001014 { Error_Handler(); 8001010: f7ff fed2 bl 8000db8 } sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE; 8001014: 2350 movs r3, #80 @ 0x50 8001016: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 8001018: 2300 movs r3, #0 800101a: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800101c: 2300 movs r3, #0 800101e: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001020: 2300 movs r3, #0 8001022: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8001024: 1d3b adds r3, r7, #4 8001026: 2200 movs r2, #0 8001028: 4619 mov r1, r3 800102a: 4807 ldr r0, [pc, #28] @ (8001048 ) 800102c: f004 f9d8 bl 80053e0 8001030: 4603 mov r3, r0 8001032: 2b00 cmp r3, #0 8001034: d001 beq.n 800103a { Error_Handler(); 8001036: f7ff febf bl 8000db8 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 800103a: 4803 ldr r0, [pc, #12] @ (8001048 ) 800103c: f000 f8c2 bl 80011c4 } 8001040: bf00 nop 8001042: 3728 adds r7, #40 @ 0x28 8001044: 46bd mov sp, r7 8001046: bd80 pop {r7, pc} 8001048: 2000026c .word 0x2000026c 0800104c : /* TIM3 init function */ void MX_TIM3_Init(void) { 800104c: b580 push {r7, lr} 800104e: b08c sub sp, #48 @ 0x30 8001050: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_Encoder_InitTypeDef sConfig = {0}; 8001052: f107 030c add.w r3, r7, #12 8001056: 2224 movs r2, #36 @ 0x24 8001058: 2100 movs r1, #0 800105a: 4618 mov r0, r3 800105c: f009 fc6c bl 800a938 TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001060: 1d3b adds r3, r7, #4 8001062: 2200 movs r2, #0 8001064: 601a str r2, [r3, #0] 8001066: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8001068: 4b20 ldr r3, [pc, #128] @ (80010ec ) 800106a: 4a21 ldr r2, [pc, #132] @ (80010f0 ) 800106c: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800106e: 4b1f ldr r3, [pc, #124] @ (80010ec ) 8001070: 2200 movs r2, #0 8001072: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8001074: 4b1d ldr r3, [pc, #116] @ (80010ec ) 8001076: 2200 movs r2, #0 8001078: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800107a: 4b1c ldr r3, [pc, #112] @ (80010ec ) 800107c: f64f 72ff movw r2, #65535 @ 0xffff 8001080: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8001082: 4b1a ldr r3, [pc, #104] @ (80010ec ) 8001084: 2200 movs r2, #0 8001086: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001088: 4b18 ldr r3, [pc, #96] @ (80010ec ) 800108a: 2200 movs r2, #0 800108c: 619a str r2, [r3, #24] sConfig.EncoderMode = TIM_ENCODERMODE_TI1; 800108e: 2301 movs r3, #1 8001090: 60fb str r3, [r7, #12] sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; 8001092: 2300 movs r3, #0 8001094: 613b str r3, [r7, #16] sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; 8001096: 2301 movs r3, #1 8001098: 617b str r3, [r7, #20] sConfig.IC1Prescaler = TIM_ICPSC_DIV1; 800109a: 2300 movs r3, #0 800109c: 61bb str r3, [r7, #24] sConfig.IC1Filter = 0; 800109e: 2300 movs r3, #0 80010a0: 61fb str r3, [r7, #28] sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; 80010a2: 2300 movs r3, #0 80010a4: 623b str r3, [r7, #32] sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; 80010a6: 2301 movs r3, #1 80010a8: 627b str r3, [r7, #36] @ 0x24 sConfig.IC2Prescaler = TIM_ICPSC_DIV1; 80010aa: 2300 movs r3, #0 80010ac: 62bb str r3, [r7, #40] @ 0x28 sConfig.IC2Filter = 0; 80010ae: 2300 movs r3, #0 80010b0: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) 80010b2: f107 030c add.w r3, r7, #12 80010b6: 4619 mov r1, r3 80010b8: 480c ldr r0, [pc, #48] @ (80010ec ) 80010ba: f004 f8ea bl 8005292 80010be: 4603 mov r3, r0 80010c0: 2b00 cmp r3, #0 80010c2: d001 beq.n 80010c8 { Error_Handler(); 80010c4: f7ff fe78 bl 8000db8 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80010c8: 2300 movs r3, #0 80010ca: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80010cc: 2300 movs r3, #0 80010ce: 60bb str r3, [r7, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80010d0: 1d3b adds r3, r7, #4 80010d2: 4619 mov r1, r3 80010d4: 4805 ldr r0, [pc, #20] @ (80010ec ) 80010d6: f004 fc35 bl 8005944 80010da: 4603 mov r3, r0 80010dc: 2b00 cmp r3, #0 80010de: d001 beq.n 80010e4 { Error_Handler(); 80010e0: f7ff fe6a bl 8000db8 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 80010e4: bf00 nop 80010e6: 3730 adds r7, #48 @ 0x30 80010e8: 46bd mov sp, r7 80010ea: bd80 pop {r7, pc} 80010ec: 200002b4 .word 0x200002b4 80010f0: 40000400 .word 0x40000400 080010f4 : void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle) { 80010f4: b480 push {r7} 80010f6: b085 sub sp, #20 80010f8: af00 add r7, sp, #0 80010fa: 6078 str r0, [r7, #4] if(tim_ocHandle->Instance==TIM2) 80010fc: 687b ldr r3, [r7, #4] 80010fe: 681b ldr r3, [r3, #0] 8001100: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001104: d10d bne.n 8001122 { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* TIM2 clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 8001106: 2300 movs r3, #0 8001108: 60fb str r3, [r7, #12] 800110a: 4b09 ldr r3, [pc, #36] @ (8001130 ) 800110c: 6c1b ldr r3, [r3, #64] @ 0x40 800110e: 4a08 ldr r2, [pc, #32] @ (8001130 ) 8001110: f043 0301 orr.w r3, r3, #1 8001114: 6413 str r3, [r2, #64] @ 0x40 8001116: 4b06 ldr r3, [pc, #24] @ (8001130 ) 8001118: 6c1b ldr r3, [r3, #64] @ 0x40 800111a: f003 0301 and.w r3, r3, #1 800111e: 60fb str r3, [r7, #12] 8001120: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } } 8001122: bf00 nop 8001124: 3714 adds r7, #20 8001126: 46bd mov sp, r7 8001128: f85d 7b04 ldr.w r7, [sp], #4 800112c: 4770 bx lr 800112e: bf00 nop 8001130: 40023800 .word 0x40023800 08001134 : void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) { 8001134: b580 push {r7, lr} 8001136: b08a sub sp, #40 @ 0x28 8001138: af00 add r7, sp, #0 800113a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800113c: f107 0314 add.w r3, r7, #20 8001140: 2200 movs r2, #0 8001142: 601a str r2, [r3, #0] 8001144: 605a str r2, [r3, #4] 8001146: 609a str r2, [r3, #8] 8001148: 60da str r2, [r3, #12] 800114a: 611a str r2, [r3, #16] if(tim_encoderHandle->Instance==TIM3) 800114c: 687b ldr r3, [r7, #4] 800114e: 681b ldr r3, [r3, #0] 8001150: 4a19 ldr r2, [pc, #100] @ (80011b8 ) 8001152: 4293 cmp r3, r2 8001154: d12b bne.n 80011ae { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 8001156: 2300 movs r3, #0 8001158: 613b str r3, [r7, #16] 800115a: 4b18 ldr r3, [pc, #96] @ (80011bc ) 800115c: 6c1b ldr r3, [r3, #64] @ 0x40 800115e: 4a17 ldr r2, [pc, #92] @ (80011bc ) 8001160: f043 0302 orr.w r3, r3, #2 8001164: 6413 str r3, [r2, #64] @ 0x40 8001166: 4b15 ldr r3, [pc, #84] @ (80011bc ) 8001168: 6c1b ldr r3, [r3, #64] @ 0x40 800116a: f003 0302 and.w r3, r3, #2 800116e: 613b str r3, [r7, #16] 8001170: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001172: 2300 movs r3, #0 8001174: 60fb str r3, [r7, #12] 8001176: 4b11 ldr r3, [pc, #68] @ (80011bc ) 8001178: 6b1b ldr r3, [r3, #48] @ 0x30 800117a: 4a10 ldr r2, [pc, #64] @ (80011bc ) 800117c: f043 0301 orr.w r3, r3, #1 8001180: 6313 str r3, [r2, #48] @ 0x30 8001182: 4b0e ldr r3, [pc, #56] @ (80011bc ) 8001184: 6b1b ldr r3, [r3, #48] @ 0x30 8001186: f003 0301 and.w r3, r3, #1 800118a: 60fb str r3, [r7, #12] 800118c: 68fb ldr r3, [r7, #12] /**TIM3 GPIO Configuration PA6 ------> TIM3_CH1 PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 800118e: 23c0 movs r3, #192 @ 0xc0 8001190: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001192: 2302 movs r3, #2 8001194: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001196: 2300 movs r3, #0 8001198: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800119a: 2300 movs r3, #0 800119c: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 800119e: 2302 movs r3, #2 80011a0: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80011a2: f107 0314 add.w r3, r7, #20 80011a6: 4619 mov r1, r3 80011a8: 4805 ldr r0, [pc, #20] @ (80011c0 ) 80011aa: f001 f981 bl 80024b0 /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 80011ae: bf00 nop 80011b0: 3728 adds r7, #40 @ 0x28 80011b2: 46bd mov sp, r7 80011b4: bd80 pop {r7, pc} 80011b6: bf00 nop 80011b8: 40000400 .word 0x40000400 80011bc: 40023800 .word 0x40023800 80011c0: 40020000 .word 0x40020000 080011c4 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 80011c4: b580 push {r7, lr} 80011c6: b088 sub sp, #32 80011c8: af00 add r7, sp, #0 80011ca: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80011cc: f107 030c add.w r3, r7, #12 80011d0: 2200 movs r2, #0 80011d2: 601a str r2, [r3, #0] 80011d4: 605a str r2, [r3, #4] 80011d6: 609a str r2, [r3, #8] 80011d8: 60da str r2, [r3, #12] 80011da: 611a str r2, [r3, #16] if(timHandle->Instance==TIM2) 80011dc: 687b ldr r3, [r7, #4] 80011de: 681b ldr r3, [r3, #0] 80011e0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80011e4: d11d bne.n 8001222 { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 80011e6: 2300 movs r3, #0 80011e8: 60bb str r3, [r7, #8] 80011ea: 4b10 ldr r3, [pc, #64] @ (800122c ) 80011ec: 6b1b ldr r3, [r3, #48] @ 0x30 80011ee: 4a0f ldr r2, [pc, #60] @ (800122c ) 80011f0: f043 0301 orr.w r3, r3, #1 80011f4: 6313 str r3, [r2, #48] @ 0x30 80011f6: 4b0d ldr r3, [pc, #52] @ (800122c ) 80011f8: 6b1b ldr r3, [r3, #48] @ 0x30 80011fa: f003 0301 and.w r3, r3, #1 80011fe: 60bb str r3, [r7, #8] 8001200: 68bb ldr r3, [r7, #8] /**TIM2 GPIO Configuration PA5 ------> TIM2_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_5; 8001202: 2320 movs r3, #32 8001204: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001206: 2302 movs r3, #2 8001208: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800120a: 2300 movs r3, #0 800120c: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800120e: 2300 movs r3, #0 8001210: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 8001212: 2301 movs r3, #1 8001214: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001216: f107 030c add.w r3, r7, #12 800121a: 4619 mov r1, r3 800121c: 4804 ldr r0, [pc, #16] @ (8001230 ) 800121e: f001 f947 bl 80024b0 /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8001222: bf00 nop 8001224: 3720 adds r7, #32 8001226: 46bd mov sp, r7 8001228: bd80 pop {r7, pc} 800122a: bf00 nop 800122c: 40023800 .word 0x40023800 8001230: 40020000 .word 0x40020000 08001234 : DMA_HandleTypeDef hdma_usart2_rx; DMA_HandleTypeDef hdma_usart2_tx; /* UART4 init function */ void MX_UART4_Init(void) { 8001234: b580 push {r7, lr} 8001236: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; 8001238: 4b11 ldr r3, [pc, #68] @ (8001280 ) 800123a: 4a12 ldr r2, [pc, #72] @ (8001284 ) 800123c: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; 800123e: 4b10 ldr r3, [pc, #64] @ (8001280 ) 8001240: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001244: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; 8001246: 4b0e ldr r3, [pc, #56] @ (8001280 ) 8001248: 2200 movs r2, #0 800124a: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; 800124c: 4b0c ldr r3, [pc, #48] @ (8001280 ) 800124e: 2200 movs r2, #0 8001250: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; 8001252: 4b0b ldr r3, [pc, #44] @ (8001280 ) 8001254: 2200 movs r2, #0 8001256: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; 8001258: 4b09 ldr r3, [pc, #36] @ (8001280 ) 800125a: 220c movs r2, #12 800125c: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800125e: 4b08 ldr r3, [pc, #32] @ (8001280 ) 8001260: 2200 movs r2, #0 8001262: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; 8001264: 4b06 ldr r3, [pc, #24] @ (8001280 ) 8001266: 2200 movs r2, #0 8001268: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart4) != HAL_OK) 800126a: 4805 ldr r0, [pc, #20] @ (8001280 ) 800126c: f004 fbe6 bl 8005a3c 8001270: 4603 mov r3, r0 8001272: 2b00 cmp r3, #0 8001274: d001 beq.n 800127a { Error_Handler(); 8001276: f7ff fd9f bl 8000db8 } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } 800127a: bf00 nop 800127c: bd80 pop {r7, pc} 800127e: bf00 nop 8001280: 200002fc .word 0x200002fc 8001284: 40004c00 .word 0x40004c00 08001288 : /* UART5 init function */ void MX_UART5_Init(void) { 8001288: b580 push {r7, lr} 800128a: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800128c: 4b11 ldr r3, [pc, #68] @ (80012d4 ) 800128e: 4a12 ldr r2, [pc, #72] @ (80012d8 ) 8001290: 601a str r2, [r3, #0] huart5.Init.BaudRate = 115200; 8001292: 4b10 ldr r3, [pc, #64] @ (80012d4 ) 8001294: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001298: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 800129a: 4b0e ldr r3, [pc, #56] @ (80012d4 ) 800129c: 2200 movs r2, #0 800129e: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 80012a0: 4b0c ldr r3, [pc, #48] @ (80012d4 ) 80012a2: 2200 movs r2, #0 80012a4: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 80012a6: 4b0b ldr r3, [pc, #44] @ (80012d4 ) 80012a8: 2200 movs r2, #0 80012aa: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 80012ac: 4b09 ldr r3, [pc, #36] @ (80012d4 ) 80012ae: 220c movs r2, #12 80012b0: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80012b2: 4b08 ldr r3, [pc, #32] @ (80012d4 ) 80012b4: 2200 movs r2, #0 80012b6: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 80012b8: 4b06 ldr r3, [pc, #24] @ (80012d4 ) 80012ba: 2200 movs r2, #0 80012bc: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 80012be: 4805 ldr r0, [pc, #20] @ (80012d4 ) 80012c0: f004 fbbc bl 8005a3c 80012c4: 4603 mov r3, r0 80012c6: 2b00 cmp r3, #0 80012c8: d001 beq.n 80012ce { Error_Handler(); 80012ca: f7ff fd75 bl 8000db8 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 80012ce: bf00 nop 80012d0: bd80 pop {r7, pc} 80012d2: bf00 nop 80012d4: 20000344 .word 0x20000344 80012d8: 40005000 .word 0x40005000 080012dc : /* USART1 init function */ void MX_USART1_UART_Init(void) { 80012dc: b580 push {r7, lr} 80012de: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 80012e0: 4b11 ldr r3, [pc, #68] @ (8001328 ) 80012e2: 4a12 ldr r2, [pc, #72] @ (800132c ) 80012e4: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 80012e6: 4b10 ldr r3, [pc, #64] @ (8001328 ) 80012e8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80012ec: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 80012ee: 4b0e ldr r3, [pc, #56] @ (8001328 ) 80012f0: 2200 movs r2, #0 80012f2: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80012f4: 4b0c ldr r3, [pc, #48] @ (8001328 ) 80012f6: 2200 movs r2, #0 80012f8: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80012fa: 4b0b ldr r3, [pc, #44] @ (8001328 ) 80012fc: 2200 movs r2, #0 80012fe: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001300: 4b09 ldr r3, [pc, #36] @ (8001328 ) 8001302: 220c movs r2, #12 8001304: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001306: 4b08 ldr r3, [pc, #32] @ (8001328 ) 8001308: 2200 movs r2, #0 800130a: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800130c: 4b06 ldr r3, [pc, #24] @ (8001328 ) 800130e: 2200 movs r2, #0 8001310: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8001312: 4805 ldr r0, [pc, #20] @ (8001328 ) 8001314: f004 fb92 bl 8005a3c 8001318: 4603 mov r3, r0 800131a: 2b00 cmp r3, #0 800131c: d001 beq.n 8001322 { Error_Handler(); 800131e: f7ff fd4b bl 8000db8 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8001322: bf00 nop 8001324: bd80 pop {r7, pc} 8001326: bf00 nop 8001328: 2000038c .word 0x2000038c 800132c: 40011000 .word 0x40011000 08001330 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 8001330: b580 push {r7, lr} 8001332: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8001334: 4b11 ldr r3, [pc, #68] @ (800137c ) 8001336: 4a12 ldr r2, [pc, #72] @ (8001380 ) 8001338: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800133a: 4b10 ldr r3, [pc, #64] @ (800137c ) 800133c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001340: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8001342: 4b0e ldr r3, [pc, #56] @ (800137c ) 8001344: 2200 movs r2, #0 8001346: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8001348: 4b0c ldr r3, [pc, #48] @ (800137c ) 800134a: 2200 movs r2, #0 800134c: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800134e: 4b0b ldr r3, [pc, #44] @ (800137c ) 8001350: 2200 movs r2, #0 8001352: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8001354: 4b09 ldr r3, [pc, #36] @ (800137c ) 8001356: 220c movs r2, #12 8001358: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800135a: 4b08 ldr r3, [pc, #32] @ (800137c ) 800135c: 2200 movs r2, #0 800135e: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8001360: 4b06 ldr r3, [pc, #24] @ (800137c ) 8001362: 2200 movs r2, #0 8001364: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 8001366: 4805 ldr r0, [pc, #20] @ (800137c ) 8001368: f004 fb68 bl 8005a3c 800136c: 4603 mov r3, r0 800136e: 2b00 cmp r3, #0 8001370: d001 beq.n 8001376 { Error_Handler(); 8001372: f7ff fd21 bl 8000db8 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8001376: bf00 nop 8001378: bd80 pop {r7, pc} 800137a: bf00 nop 800137c: 200003d4 .word 0x200003d4 8001380: 40004400 .word 0x40004400 08001384 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8001384: b580 push {r7, lr} 8001386: b090 sub sp, #64 @ 0x40 8001388: af00 add r7, sp, #0 800138a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800138c: f107 032c add.w r3, r7, #44 @ 0x2c 8001390: 2200 movs r2, #0 8001392: 601a str r2, [r3, #0] 8001394: 605a str r2, [r3, #4] 8001396: 609a str r2, [r3, #8] 8001398: 60da str r2, [r3, #12] 800139a: 611a str r2, [r3, #16] if(uartHandle->Instance==UART4) 800139c: 687b ldr r3, [r7, #4] 800139e: 681b ldr r3, [r3, #0] 80013a0: 4a4a ldr r2, [pc, #296] @ (80014cc ) 80013a2: 4293 cmp r3, r2 80013a4: f040 80a0 bne.w 80014e8 { /* USER CODE BEGIN UART4_MspInit 0 */ /* USER CODE END UART4_MspInit 0 */ /* UART4 clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); 80013a8: 2300 movs r3, #0 80013aa: 62bb str r3, [r7, #40] @ 0x28 80013ac: 4b48 ldr r3, [pc, #288] @ (80014d0 ) 80013ae: 6c1b ldr r3, [r3, #64] @ 0x40 80013b0: 4a47 ldr r2, [pc, #284] @ (80014d0 ) 80013b2: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80013b6: 6413 str r3, [r2, #64] @ 0x40 80013b8: 4b45 ldr r3, [pc, #276] @ (80014d0 ) 80013ba: 6c1b ldr r3, [r3, #64] @ 0x40 80013bc: f403 2300 and.w r3, r3, #524288 @ 0x80000 80013c0: 62bb str r3, [r7, #40] @ 0x28 80013c2: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOA_CLK_ENABLE(); 80013c4: 2300 movs r3, #0 80013c6: 627b str r3, [r7, #36] @ 0x24 80013c8: 4b41 ldr r3, [pc, #260] @ (80014d0 ) 80013ca: 6b1b ldr r3, [r3, #48] @ 0x30 80013cc: 4a40 ldr r2, [pc, #256] @ (80014d0 ) 80013ce: f043 0301 orr.w r3, r3, #1 80013d2: 6313 str r3, [r2, #48] @ 0x30 80013d4: 4b3e ldr r3, [pc, #248] @ (80014d0 ) 80013d6: 6b1b ldr r3, [r3, #48] @ 0x30 80013d8: f003 0301 and.w r3, r3, #1 80013dc: 627b str r3, [r7, #36] @ 0x24 80013de: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART4 GPIO Configuration PA0-WKUP ------> UART4_TX PA1 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 80013e0: 2303 movs r3, #3 80013e2: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80013e4: 2302 movs r3, #2 80013e6: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80013e8: 2300 movs r3, #0 80013ea: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80013ec: 2303 movs r3, #3 80013ee: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 80013f0: 2308 movs r3, #8 80013f2: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80013f4: f107 032c add.w r3, r7, #44 @ 0x2c 80013f8: 4619 mov r1, r3 80013fa: 4836 ldr r0, [pc, #216] @ (80014d4 ) 80013fc: f001 f858 bl 80024b0 /* UART4 DMA Init */ /* UART4_RX Init */ hdma_uart4_rx.Instance = DMA1_Stream2; 8001400: 4b35 ldr r3, [pc, #212] @ (80014d8 ) 8001402: 4a36 ldr r2, [pc, #216] @ (80014dc ) 8001404: 601a str r2, [r3, #0] hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4; 8001406: 4b34 ldr r3, [pc, #208] @ (80014d8 ) 8001408: f04f 6200 mov.w r2, #134217728 @ 0x8000000 800140c: 605a str r2, [r3, #4] hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800140e: 4b32 ldr r3, [pc, #200] @ (80014d8 ) 8001410: 2200 movs r2, #0 8001412: 609a str r2, [r3, #8] hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001414: 4b30 ldr r3, [pc, #192] @ (80014d8 ) 8001416: 2200 movs r2, #0 8001418: 60da str r2, [r3, #12] hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE; 800141a: 4b2f ldr r3, [pc, #188] @ (80014d8 ) 800141c: f44f 6280 mov.w r2, #1024 @ 0x400 8001420: 611a str r2, [r3, #16] hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001422: 4b2d ldr r3, [pc, #180] @ (80014d8 ) 8001424: 2200 movs r2, #0 8001426: 615a str r2, [r3, #20] hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001428: 4b2b ldr r3, [pc, #172] @ (80014d8 ) 800142a: 2200 movs r2, #0 800142c: 619a str r2, [r3, #24] hdma_uart4_rx.Init.Mode = DMA_NORMAL; 800142e: 4b2a ldr r3, [pc, #168] @ (80014d8 ) 8001430: 2200 movs r2, #0 8001432: 61da str r2, [r3, #28] hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW; 8001434: 4b28 ldr r3, [pc, #160] @ (80014d8 ) 8001436: 2200 movs r2, #0 8001438: 621a str r2, [r3, #32] hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800143a: 4b27 ldr r3, [pc, #156] @ (80014d8 ) 800143c: 2200 movs r2, #0 800143e: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK) 8001440: 4825 ldr r0, [pc, #148] @ (80014d8 ) 8001442: f000 fc33 bl 8001cac 8001446: 4603 mov r3, r0 8001448: 2b00 cmp r3, #0 800144a: d001 beq.n 8001450 { Error_Handler(); 800144c: f7ff fcb4 bl 8000db8 } __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx); 8001450: 687b ldr r3, [r7, #4] 8001452: 4a21 ldr r2, [pc, #132] @ (80014d8 ) 8001454: 63da str r2, [r3, #60] @ 0x3c 8001456: 4a20 ldr r2, [pc, #128] @ (80014d8 ) 8001458: 687b ldr r3, [r7, #4] 800145a: 6393 str r3, [r2, #56] @ 0x38 /* UART4_TX Init */ hdma_uart4_tx.Instance = DMA1_Stream4; 800145c: 4b20 ldr r3, [pc, #128] @ (80014e0 ) 800145e: 4a21 ldr r2, [pc, #132] @ (80014e4 ) 8001460: 601a str r2, [r3, #0] hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4; 8001462: 4b1f ldr r3, [pc, #124] @ (80014e0 ) 8001464: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001468: 605a str r2, [r3, #4] hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800146a: 4b1d ldr r3, [pc, #116] @ (80014e0 ) 800146c: 2240 movs r2, #64 @ 0x40 800146e: 609a str r2, [r3, #8] hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001470: 4b1b ldr r3, [pc, #108] @ (80014e0 ) 8001472: 2200 movs r2, #0 8001474: 60da str r2, [r3, #12] hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE; 8001476: 4b1a ldr r3, [pc, #104] @ (80014e0 ) 8001478: f44f 6280 mov.w r2, #1024 @ 0x400 800147c: 611a str r2, [r3, #16] hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800147e: 4b18 ldr r3, [pc, #96] @ (80014e0 ) 8001480: 2200 movs r2, #0 8001482: 615a str r2, [r3, #20] hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001484: 4b16 ldr r3, [pc, #88] @ (80014e0 ) 8001486: 2200 movs r2, #0 8001488: 619a str r2, [r3, #24] hdma_uart4_tx.Init.Mode = DMA_NORMAL; 800148a: 4b15 ldr r3, [pc, #84] @ (80014e0 ) 800148c: 2200 movs r2, #0 800148e: 61da str r2, [r3, #28] hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW; 8001490: 4b13 ldr r3, [pc, #76] @ (80014e0 ) 8001492: 2200 movs r2, #0 8001494: 621a str r2, [r3, #32] hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001496: 4b12 ldr r3, [pc, #72] @ (80014e0 ) 8001498: 2200 movs r2, #0 800149a: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK) 800149c: 4810 ldr r0, [pc, #64] @ (80014e0 ) 800149e: f000 fc05 bl 8001cac 80014a2: 4603 mov r3, r0 80014a4: 2b00 cmp r3, #0 80014a6: d001 beq.n 80014ac { Error_Handler(); 80014a8: f7ff fc86 bl 8000db8 } __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); 80014ac: 687b ldr r3, [r7, #4] 80014ae: 4a0c ldr r2, [pc, #48] @ (80014e0 ) 80014b0: 639a str r2, [r3, #56] @ 0x38 80014b2: 4a0b ldr r2, [pc, #44] @ (80014e0 ) 80014b4: 687b ldr r3, [r7, #4] 80014b6: 6393 str r3, [r2, #56] @ 0x38 /* UART4 interrupt Init */ HAL_NVIC_SetPriority(UART4_IRQn, 0, 0); 80014b8: 2200 movs r2, #0 80014ba: 2100 movs r1, #0 80014bc: 2034 movs r0, #52 @ 0x34 80014be: f000 fbbe bl 8001c3e HAL_NVIC_EnableIRQ(UART4_IRQn); 80014c2: 2034 movs r0, #52 @ 0x34 80014c4: f000 fbd7 bl 8001c76 HAL_NVIC_EnableIRQ(USART2_IRQn); /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 80014c8: e202 b.n 80018d0 80014ca: bf00 nop 80014cc: 40004c00 .word 0x40004c00 80014d0: 40023800 .word 0x40023800 80014d4: 40020000 .word 0x40020000 80014d8: 2000041c .word 0x2000041c 80014dc: 40026040 .word 0x40026040 80014e0: 2000047c .word 0x2000047c 80014e4: 40026070 .word 0x40026070 else if(uartHandle->Instance==UART5) 80014e8: 687b ldr r3, [r7, #4] 80014ea: 681b ldr r3, [r3, #0] 80014ec: 4a59 ldr r2, [pc, #356] @ (8001654 ) 80014ee: 4293 cmp r3, r2 80014f0: f040 80c0 bne.w 8001674 __HAL_RCC_UART5_CLK_ENABLE(); 80014f4: 2300 movs r3, #0 80014f6: 623b str r3, [r7, #32] 80014f8: 4b57 ldr r3, [pc, #348] @ (8001658 ) 80014fa: 6c1b ldr r3, [r3, #64] @ 0x40 80014fc: 4a56 ldr r2, [pc, #344] @ (8001658 ) 80014fe: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8001502: 6413 str r3, [r2, #64] @ 0x40 8001504: 4b54 ldr r3, [pc, #336] @ (8001658 ) 8001506: 6c1b ldr r3, [r3, #64] @ 0x40 8001508: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800150c: 623b str r3, [r7, #32] 800150e: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001510: 2300 movs r3, #0 8001512: 61fb str r3, [r7, #28] 8001514: 4b50 ldr r3, [pc, #320] @ (8001658 ) 8001516: 6b1b ldr r3, [r3, #48] @ 0x30 8001518: 4a4f ldr r2, [pc, #316] @ (8001658 ) 800151a: f043 0304 orr.w r3, r3, #4 800151e: 6313 str r3, [r2, #48] @ 0x30 8001520: 4b4d ldr r3, [pc, #308] @ (8001658 ) 8001522: 6b1b ldr r3, [r3, #48] @ 0x30 8001524: f003 0304 and.w r3, r3, #4 8001528: 61fb str r3, [r7, #28] 800152a: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOD_CLK_ENABLE(); 800152c: 2300 movs r3, #0 800152e: 61bb str r3, [r7, #24] 8001530: 4b49 ldr r3, [pc, #292] @ (8001658 ) 8001532: 6b1b ldr r3, [r3, #48] @ 0x30 8001534: 4a48 ldr r2, [pc, #288] @ (8001658 ) 8001536: f043 0308 orr.w r3, r3, #8 800153a: 6313 str r3, [r2, #48] @ 0x30 800153c: 4b46 ldr r3, [pc, #280] @ (8001658 ) 800153e: 6b1b ldr r3, [r3, #48] @ 0x30 8001540: f003 0308 and.w r3, r3, #8 8001544: 61bb str r3, [r7, #24] 8001546: 69bb ldr r3, [r7, #24] GPIO_InitStruct.Pin = GPIO_PIN_12; 8001548: f44f 5380 mov.w r3, #4096 @ 0x1000 800154c: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800154e: 2302 movs r3, #2 8001550: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001552: 2300 movs r3, #0 8001554: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001556: 2303 movs r3, #3 8001558: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 800155a: 2308 movs r3, #8 800155c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800155e: f107 032c add.w r3, r7, #44 @ 0x2c 8001562: 4619 mov r1, r3 8001564: 483d ldr r0, [pc, #244] @ (800165c ) 8001566: f000 ffa3 bl 80024b0 GPIO_InitStruct.Pin = GPIO_PIN_2; 800156a: 2304 movs r3, #4 800156c: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800156e: 2302 movs r3, #2 8001570: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001572: 2300 movs r3, #0 8001574: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001576: 2303 movs r3, #3 8001578: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 800157a: 2308 movs r3, #8 800157c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800157e: f107 032c add.w r3, r7, #44 @ 0x2c 8001582: 4619 mov r1, r3 8001584: 4836 ldr r0, [pc, #216] @ (8001660 ) 8001586: f000 ff93 bl 80024b0 hdma_uart5_rx.Instance = DMA1_Stream0; 800158a: 4b36 ldr r3, [pc, #216] @ (8001664 ) 800158c: 4a36 ldr r2, [pc, #216] @ (8001668 ) 800158e: 601a str r2, [r3, #0] hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4; 8001590: 4b34 ldr r3, [pc, #208] @ (8001664 ) 8001592: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001596: 605a str r2, [r3, #4] hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001598: 4b32 ldr r3, [pc, #200] @ (8001664 ) 800159a: 2200 movs r2, #0 800159c: 609a str r2, [r3, #8] hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800159e: 4b31 ldr r3, [pc, #196] @ (8001664 ) 80015a0: 2200 movs r2, #0 80015a2: 60da str r2, [r3, #12] hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE; 80015a4: 4b2f ldr r3, [pc, #188] @ (8001664 ) 80015a6: f44f 6280 mov.w r2, #1024 @ 0x400 80015aa: 611a str r2, [r3, #16] hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80015ac: 4b2d ldr r3, [pc, #180] @ (8001664 ) 80015ae: 2200 movs r2, #0 80015b0: 615a str r2, [r3, #20] hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80015b2: 4b2c ldr r3, [pc, #176] @ (8001664 ) 80015b4: 2200 movs r2, #0 80015b6: 619a str r2, [r3, #24] hdma_uart5_rx.Init.Mode = DMA_NORMAL; 80015b8: 4b2a ldr r3, [pc, #168] @ (8001664 ) 80015ba: 2200 movs r2, #0 80015bc: 61da str r2, [r3, #28] hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; 80015be: 4b29 ldr r3, [pc, #164] @ (8001664 ) 80015c0: 2200 movs r2, #0 80015c2: 621a str r2, [r3, #32] hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80015c4: 4b27 ldr r3, [pc, #156] @ (8001664 ) 80015c6: 2200 movs r2, #0 80015c8: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) 80015ca: 4826 ldr r0, [pc, #152] @ (8001664 ) 80015cc: f000 fb6e bl 8001cac 80015d0: 4603 mov r3, r0 80015d2: 2b00 cmp r3, #0 80015d4: d001 beq.n 80015da Error_Handler(); 80015d6: f7ff fbef bl 8000db8 __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx); 80015da: 687b ldr r3, [r7, #4] 80015dc: 4a21 ldr r2, [pc, #132] @ (8001664 ) 80015de: 63da str r2, [r3, #60] @ 0x3c 80015e0: 4a20 ldr r2, [pc, #128] @ (8001664 ) 80015e2: 687b ldr r3, [r7, #4] 80015e4: 6393 str r3, [r2, #56] @ 0x38 hdma_uart5_tx.Instance = DMA1_Stream7; 80015e6: 4b21 ldr r3, [pc, #132] @ (800166c ) 80015e8: 4a21 ldr r2, [pc, #132] @ (8001670 ) 80015ea: 601a str r2, [r3, #0] hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4; 80015ec: 4b1f ldr r3, [pc, #124] @ (800166c ) 80015ee: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80015f2: 605a str r2, [r3, #4] hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80015f4: 4b1d ldr r3, [pc, #116] @ (800166c ) 80015f6: 2240 movs r2, #64 @ 0x40 80015f8: 609a str r2, [r3, #8] hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE; 80015fa: 4b1c ldr r3, [pc, #112] @ (800166c ) 80015fc: 2200 movs r2, #0 80015fe: 60da str r2, [r3, #12] hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE; 8001600: 4b1a ldr r3, [pc, #104] @ (800166c ) 8001602: f44f 6280 mov.w r2, #1024 @ 0x400 8001606: 611a str r2, [r3, #16] hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001608: 4b18 ldr r3, [pc, #96] @ (800166c ) 800160a: 2200 movs r2, #0 800160c: 615a str r2, [r3, #20] hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800160e: 4b17 ldr r3, [pc, #92] @ (800166c ) 8001610: 2200 movs r2, #0 8001612: 619a str r2, [r3, #24] hdma_uart5_tx.Init.Mode = DMA_NORMAL; 8001614: 4b15 ldr r3, [pc, #84] @ (800166c ) 8001616: 2200 movs r2, #0 8001618: 61da str r2, [r3, #28] hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; 800161a: 4b14 ldr r3, [pc, #80] @ (800166c ) 800161c: 2200 movs r2, #0 800161e: 621a str r2, [r3, #32] hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001620: 4b12 ldr r3, [pc, #72] @ (800166c ) 8001622: 2200 movs r2, #0 8001624: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) 8001626: 4811 ldr r0, [pc, #68] @ (800166c ) 8001628: f000 fb40 bl 8001cac 800162c: 4603 mov r3, r0 800162e: 2b00 cmp r3, #0 8001630: d001 beq.n 8001636 Error_Handler(); 8001632: f7ff fbc1 bl 8000db8 __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); 8001636: 687b ldr r3, [r7, #4] 8001638: 4a0c ldr r2, [pc, #48] @ (800166c ) 800163a: 639a str r2, [r3, #56] @ 0x38 800163c: 4a0b ldr r2, [pc, #44] @ (800166c ) 800163e: 687b ldr r3, [r7, #4] 8001640: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(UART5_IRQn, 0, 0); 8001642: 2200 movs r2, #0 8001644: 2100 movs r1, #0 8001646: 2035 movs r0, #53 @ 0x35 8001648: f000 faf9 bl 8001c3e HAL_NVIC_EnableIRQ(UART5_IRQn); 800164c: 2035 movs r0, #53 @ 0x35 800164e: f000 fb12 bl 8001c76 } 8001652: e13d b.n 80018d0 8001654: 40005000 .word 0x40005000 8001658: 40023800 .word 0x40023800 800165c: 40020800 .word 0x40020800 8001660: 40020c00 .word 0x40020c00 8001664: 200004dc .word 0x200004dc 8001668: 40026010 .word 0x40026010 800166c: 2000053c .word 0x2000053c 8001670: 400260b8 .word 0x400260b8 else if(uartHandle->Instance==USART1) 8001674: 687b ldr r3, [r7, #4] 8001676: 681b ldr r3, [r3, #0] 8001678: 4a97 ldr r2, [pc, #604] @ (80018d8 ) 800167a: 4293 cmp r3, r2 800167c: f040 8092 bne.w 80017a4 __HAL_RCC_USART1_CLK_ENABLE(); 8001680: 2300 movs r3, #0 8001682: 617b str r3, [r7, #20] 8001684: 4b95 ldr r3, [pc, #596] @ (80018dc ) 8001686: 6c5b ldr r3, [r3, #68] @ 0x44 8001688: 4a94 ldr r2, [pc, #592] @ (80018dc ) 800168a: f043 0310 orr.w r3, r3, #16 800168e: 6453 str r3, [r2, #68] @ 0x44 8001690: 4b92 ldr r3, [pc, #584] @ (80018dc ) 8001692: 6c5b ldr r3, [r3, #68] @ 0x44 8001694: f003 0310 and.w r3, r3, #16 8001698: 617b str r3, [r7, #20] 800169a: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 800169c: 2300 movs r3, #0 800169e: 613b str r3, [r7, #16] 80016a0: 4b8e ldr r3, [pc, #568] @ (80018dc ) 80016a2: 6b1b ldr r3, [r3, #48] @ 0x30 80016a4: 4a8d ldr r2, [pc, #564] @ (80018dc ) 80016a6: f043 0301 orr.w r3, r3, #1 80016aa: 6313 str r3, [r2, #48] @ 0x30 80016ac: 4b8b ldr r3, [pc, #556] @ (80018dc ) 80016ae: 6b1b ldr r3, [r3, #48] @ 0x30 80016b0: f003 0301 and.w r3, r3, #1 80016b4: 613b str r3, [r7, #16] 80016b6: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 80016b8: f44f 63c0 mov.w r3, #1536 @ 0x600 80016bc: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80016be: 2302 movs r3, #2 80016c0: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80016c2: 2300 movs r3, #0 80016c4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80016c6: 2303 movs r3, #3 80016c8: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 80016ca: 2307 movs r3, #7 80016cc: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80016ce: f107 032c add.w r3, r7, #44 @ 0x2c 80016d2: 4619 mov r1, r3 80016d4: 4882 ldr r0, [pc, #520] @ (80018e0 ) 80016d6: f000 feeb bl 80024b0 hdma_usart1_rx.Instance = DMA2_Stream2; 80016da: 4b82 ldr r3, [pc, #520] @ (80018e4 ) 80016dc: 4a82 ldr r2, [pc, #520] @ (80018e8 ) 80016de: 601a str r2, [r3, #0] hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; 80016e0: 4b80 ldr r3, [pc, #512] @ (80018e4 ) 80016e2: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80016e6: 605a str r2, [r3, #4] hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80016e8: 4b7e ldr r3, [pc, #504] @ (80018e4 ) 80016ea: 2200 movs r2, #0 80016ec: 609a str r2, [r3, #8] hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 80016ee: 4b7d ldr r3, [pc, #500] @ (80018e4 ) 80016f0: 2200 movs r2, #0 80016f2: 60da str r2, [r3, #12] hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 80016f4: 4b7b ldr r3, [pc, #492] @ (80018e4 ) 80016f6: f44f 6280 mov.w r2, #1024 @ 0x400 80016fa: 611a str r2, [r3, #16] hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80016fc: 4b79 ldr r3, [pc, #484] @ (80018e4 ) 80016fe: 2200 movs r2, #0 8001700: 615a str r2, [r3, #20] hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001702: 4b78 ldr r3, [pc, #480] @ (80018e4 ) 8001704: 2200 movs r2, #0 8001706: 619a str r2, [r3, #24] hdma_usart1_rx.Init.Mode = DMA_NORMAL; 8001708: 4b76 ldr r3, [pc, #472] @ (80018e4 ) 800170a: 2200 movs r2, #0 800170c: 61da str r2, [r3, #28] hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; 800170e: 4b75 ldr r3, [pc, #468] @ (80018e4 ) 8001710: 2200 movs r2, #0 8001712: 621a str r2, [r3, #32] hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001714: 4b73 ldr r3, [pc, #460] @ (80018e4 ) 8001716: 2200 movs r2, #0 8001718: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 800171a: 4872 ldr r0, [pc, #456] @ (80018e4 ) 800171c: f000 fac6 bl 8001cac 8001720: 4603 mov r3, r0 8001722: 2b00 cmp r3, #0 8001724: d001 beq.n 800172a Error_Handler(); 8001726: f7ff fb47 bl 8000db8 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); 800172a: 687b ldr r3, [r7, #4] 800172c: 4a6d ldr r2, [pc, #436] @ (80018e4 ) 800172e: 63da str r2, [r3, #60] @ 0x3c 8001730: 4a6c ldr r2, [pc, #432] @ (80018e4 ) 8001732: 687b ldr r3, [r7, #4] 8001734: 6393 str r3, [r2, #56] @ 0x38 hdma_usart1_tx.Instance = DMA2_Stream7; 8001736: 4b6d ldr r3, [pc, #436] @ (80018ec ) 8001738: 4a6d ldr r2, [pc, #436] @ (80018f0 ) 800173a: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; 800173c: 4b6b ldr r3, [pc, #428] @ (80018ec ) 800173e: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001742: 605a str r2, [r3, #4] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001744: 4b69 ldr r3, [pc, #420] @ (80018ec ) 8001746: 2240 movs r2, #64 @ 0x40 8001748: 609a str r2, [r3, #8] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800174a: 4b68 ldr r3, [pc, #416] @ (80018ec ) 800174c: 2200 movs r2, #0 800174e: 60da str r2, [r3, #12] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 8001750: 4b66 ldr r3, [pc, #408] @ (80018ec ) 8001752: f44f 6280 mov.w r2, #1024 @ 0x400 8001756: 611a str r2, [r3, #16] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001758: 4b64 ldr r3, [pc, #400] @ (80018ec ) 800175a: 2200 movs r2, #0 800175c: 615a str r2, [r3, #20] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800175e: 4b63 ldr r3, [pc, #396] @ (80018ec ) 8001760: 2200 movs r2, #0 8001762: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 8001764: 4b61 ldr r3, [pc, #388] @ (80018ec ) 8001766: 2200 movs r2, #0 8001768: 61da str r2, [r3, #28] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 800176a: 4b60 ldr r3, [pc, #384] @ (80018ec ) 800176c: 2200 movs r2, #0 800176e: 621a str r2, [r3, #32] hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001770: 4b5e ldr r3, [pc, #376] @ (80018ec ) 8001772: 2200 movs r2, #0 8001774: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 8001776: 485d ldr r0, [pc, #372] @ (80018ec ) 8001778: f000 fa98 bl 8001cac 800177c: 4603 mov r3, r0 800177e: 2b00 cmp r3, #0 8001780: d001 beq.n 8001786 Error_Handler(); 8001782: f7ff fb19 bl 8000db8 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); 8001786: 687b ldr r3, [r7, #4] 8001788: 4a58 ldr r2, [pc, #352] @ (80018ec ) 800178a: 639a str r2, [r3, #56] @ 0x38 800178c: 4a57 ldr r2, [pc, #348] @ (80018ec ) 800178e: 687b ldr r3, [r7, #4] 8001790: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8001792: 2200 movs r2, #0 8001794: 2100 movs r1, #0 8001796: 2025 movs r0, #37 @ 0x25 8001798: f000 fa51 bl 8001c3e HAL_NVIC_EnableIRQ(USART1_IRQn); 800179c: 2025 movs r0, #37 @ 0x25 800179e: f000 fa6a bl 8001c76 } 80017a2: e095 b.n 80018d0 else if(uartHandle->Instance==USART2) 80017a4: 687b ldr r3, [r7, #4] 80017a6: 681b ldr r3, [r3, #0] 80017a8: 4a52 ldr r2, [pc, #328] @ (80018f4 ) 80017aa: 4293 cmp r3, r2 80017ac: f040 8090 bne.w 80018d0 __HAL_RCC_USART2_CLK_ENABLE(); 80017b0: 2300 movs r3, #0 80017b2: 60fb str r3, [r7, #12] 80017b4: 4b49 ldr r3, [pc, #292] @ (80018dc ) 80017b6: 6c1b ldr r3, [r3, #64] @ 0x40 80017b8: 4a48 ldr r2, [pc, #288] @ (80018dc ) 80017ba: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80017be: 6413 str r3, [r2, #64] @ 0x40 80017c0: 4b46 ldr r3, [pc, #280] @ (80018dc ) 80017c2: 6c1b ldr r3, [r3, #64] @ 0x40 80017c4: f403 3300 and.w r3, r3, #131072 @ 0x20000 80017c8: 60fb str r3, [r7, #12] 80017ca: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 80017cc: 2300 movs r3, #0 80017ce: 60bb str r3, [r7, #8] 80017d0: 4b42 ldr r3, [pc, #264] @ (80018dc ) 80017d2: 6b1b ldr r3, [r3, #48] @ 0x30 80017d4: 4a41 ldr r2, [pc, #260] @ (80018dc ) 80017d6: f043 0301 orr.w r3, r3, #1 80017da: 6313 str r3, [r2, #48] @ 0x30 80017dc: 4b3f ldr r3, [pc, #252] @ (80018dc ) 80017de: 6b1b ldr r3, [r3, #48] @ 0x30 80017e0: f003 0301 and.w r3, r3, #1 80017e4: 60bb str r3, [r7, #8] 80017e6: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; 80017e8: 230c movs r3, #12 80017ea: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80017ec: 2302 movs r3, #2 80017ee: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80017f0: 2300 movs r3, #0 80017f2: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80017f4: 2303 movs r3, #3 80017f6: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 80017f8: 2307 movs r3, #7 80017fa: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80017fc: f107 032c add.w r3, r7, #44 @ 0x2c 8001800: 4619 mov r1, r3 8001802: 4837 ldr r0, [pc, #220] @ (80018e0 ) 8001804: f000 fe54 bl 80024b0 hdma_usart2_rx.Instance = DMA1_Stream5; 8001808: 4b3b ldr r3, [pc, #236] @ (80018f8 ) 800180a: 4a3c ldr r2, [pc, #240] @ (80018fc ) 800180c: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; 800180e: 4b3a ldr r3, [pc, #232] @ (80018f8 ) 8001810: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001814: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001816: 4b38 ldr r3, [pc, #224] @ (80018f8 ) 8001818: 2200 movs r2, #0 800181a: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800181c: 4b36 ldr r3, [pc, #216] @ (80018f8 ) 800181e: 2200 movs r2, #0 8001820: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 8001822: 4b35 ldr r3, [pc, #212] @ (80018f8 ) 8001824: f44f 6280 mov.w r2, #1024 @ 0x400 8001828: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800182a: 4b33 ldr r3, [pc, #204] @ (80018f8 ) 800182c: 2200 movs r2, #0 800182e: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001830: 4b31 ldr r3, [pc, #196] @ (80018f8 ) 8001832: 2200 movs r2, #0 8001834: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 8001836: 4b30 ldr r3, [pc, #192] @ (80018f8 ) 8001838: 2200 movs r2, #0 800183a: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; 800183c: 4b2e ldr r3, [pc, #184] @ (80018f8 ) 800183e: 2200 movs r2, #0 8001840: 621a str r2, [r3, #32] hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001842: 4b2d ldr r3, [pc, #180] @ (80018f8 ) 8001844: 2200 movs r2, #0 8001846: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 8001848: 482b ldr r0, [pc, #172] @ (80018f8 ) 800184a: f000 fa2f bl 8001cac 800184e: 4603 mov r3, r0 8001850: 2b00 cmp r3, #0 8001852: d001 beq.n 8001858 Error_Handler(); 8001854: f7ff fab0 bl 8000db8 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 8001858: 687b ldr r3, [r7, #4] 800185a: 4a27 ldr r2, [pc, #156] @ (80018f8 ) 800185c: 63da str r2, [r3, #60] @ 0x3c 800185e: 4a26 ldr r2, [pc, #152] @ (80018f8 ) 8001860: 687b ldr r3, [r7, #4] 8001862: 6393 str r3, [r2, #56] @ 0x38 hdma_usart2_tx.Instance = DMA1_Stream6; 8001864: 4b26 ldr r3, [pc, #152] @ (8001900 ) 8001866: 4a27 ldr r2, [pc, #156] @ (8001904 ) 8001868: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; 800186a: 4b25 ldr r3, [pc, #148] @ (8001900 ) 800186c: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001870: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001872: 4b23 ldr r3, [pc, #140] @ (8001900 ) 8001874: 2240 movs r2, #64 @ 0x40 8001876: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001878: 4b21 ldr r3, [pc, #132] @ (8001900 ) 800187a: 2200 movs r2, #0 800187c: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 800187e: 4b20 ldr r3, [pc, #128] @ (8001900 ) 8001880: f44f 6280 mov.w r2, #1024 @ 0x400 8001884: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001886: 4b1e ldr r3, [pc, #120] @ (8001900 ) 8001888: 2200 movs r2, #0 800188a: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800188c: 4b1c ldr r3, [pc, #112] @ (8001900 ) 800188e: 2200 movs r2, #0 8001890: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 8001892: 4b1b ldr r3, [pc, #108] @ (8001900 ) 8001894: 2200 movs r2, #0 8001896: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; 8001898: 4b19 ldr r3, [pc, #100] @ (8001900 ) 800189a: 2200 movs r2, #0 800189c: 621a str r2, [r3, #32] hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800189e: 4b18 ldr r3, [pc, #96] @ (8001900 ) 80018a0: 2200 movs r2, #0 80018a2: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 80018a4: 4816 ldr r0, [pc, #88] @ (8001900 ) 80018a6: f000 fa01 bl 8001cac 80018aa: 4603 mov r3, r0 80018ac: 2b00 cmp r3, #0 80018ae: d001 beq.n 80018b4 Error_Handler(); 80018b0: f7ff fa82 bl 8000db8 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 80018b4: 687b ldr r3, [r7, #4] 80018b6: 4a12 ldr r2, [pc, #72] @ (8001900 ) 80018b8: 639a str r2, [r3, #56] @ 0x38 80018ba: 4a11 ldr r2, [pc, #68] @ (8001900 ) 80018bc: 687b ldr r3, [r7, #4] 80018be: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 80018c0: 2200 movs r2, #0 80018c2: 2100 movs r1, #0 80018c4: 2026 movs r0, #38 @ 0x26 80018c6: f000 f9ba bl 8001c3e HAL_NVIC_EnableIRQ(USART2_IRQn); 80018ca: 2026 movs r0, #38 @ 0x26 80018cc: f000 f9d3 bl 8001c76 } 80018d0: bf00 nop 80018d2: 3740 adds r7, #64 @ 0x40 80018d4: 46bd mov sp, r7 80018d6: bd80 pop {r7, pc} 80018d8: 40011000 .word 0x40011000 80018dc: 40023800 .word 0x40023800 80018e0: 40020000 .word 0x40020000 80018e4: 2000059c .word 0x2000059c 80018e8: 40026440 .word 0x40026440 80018ec: 200005fc .word 0x200005fc 80018f0: 400264b8 .word 0x400264b8 80018f4: 40004400 .word 0x40004400 80018f8: 2000065c .word 0x2000065c 80018fc: 40026088 .word 0x40026088 8001900: 200006bc .word 0x200006bc 8001904: 400260a0 .word 0x400260a0 08001908 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001908: f8df d034 ldr.w sp, [pc, #52] @ 8001940 /* Call the clock system initialization function.*/ bl SystemInit 800190c: f7ff fb34 bl 8000f78 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001910: 480c ldr r0, [pc, #48] @ (8001944 ) ldr r1, =_edata 8001912: 490d ldr r1, [pc, #52] @ (8001948 ) ldr r2, =_sidata 8001914: 4a0d ldr r2, [pc, #52] @ (800194c ) movs r3, #0 8001916: 2300 movs r3, #0 b LoopCopyDataInit 8001918: e002 b.n 8001920 0800191a : CopyDataInit: ldr r4, [r2, r3] 800191a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800191c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800191e: 3304 adds r3, #4 08001920 : LoopCopyDataInit: adds r4, r0, r3 8001920: 18c4 adds r4, r0, r3 cmp r4, r1 8001922: 428c cmp r4, r1 bcc CopyDataInit 8001924: d3f9 bcc.n 800191a /* Zero fill the bss segment. */ ldr r2, =_sbss 8001926: 4a0a ldr r2, [pc, #40] @ (8001950 ) ldr r4, =_ebss 8001928: 4c0a ldr r4, [pc, #40] @ (8001954 ) movs r3, #0 800192a: 2300 movs r3, #0 b LoopFillZerobss 800192c: e001 b.n 8001932 0800192e : FillZerobss: str r3, [r2] 800192e: 6013 str r3, [r2, #0] adds r2, r2, #4 8001930: 3204 adds r2, #4 08001932 : LoopFillZerobss: cmp r2, r4 8001932: 42a2 cmp r2, r4 bcc FillZerobss 8001934: d3fb bcc.n 800192e /* Call static constructors */ bl __libc_init_array 8001936: f009 f807 bl 800a948 <__libc_init_array> /* Call the application's entry point.*/ bl main 800193a: f7fe ff75 bl 8000828
bx lr 800193e: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001940: 20020000 .word 0x20020000 ldr r0, =_sdata 8001944: 20000000 .word 0x20000000 ldr r1, =_edata 8001948: 200001a0 .word 0x200001a0 ldr r2, =_sidata 800194c: 0800aa30 .word 0x0800aa30 ldr r2, =_sbss 8001950: 200001a0 .word 0x200001a0 ldr r4, =_ebss 8001954: 200010f8 .word 0x200010f8 08001958 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001958: e7fe b.n 8001958 ... 0800195c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800195c: b580 push {r7, lr} 800195e: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 8001960: 4b0e ldr r3, [pc, #56] @ (800199c ) 8001962: 681b ldr r3, [r3, #0] 8001964: 4a0d ldr r2, [pc, #52] @ (800199c ) 8001966: f443 7300 orr.w r3, r3, #512 @ 0x200 800196a: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 800196c: 4b0b ldr r3, [pc, #44] @ (800199c ) 800196e: 681b ldr r3, [r3, #0] 8001970: 4a0a ldr r2, [pc, #40] @ (800199c ) 8001972: f443 6380 orr.w r3, r3, #1024 @ 0x400 8001976: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001978: 4b08 ldr r3, [pc, #32] @ (800199c ) 800197a: 681b ldr r3, [r3, #0] 800197c: 4a07 ldr r2, [pc, #28] @ (800199c ) 800197e: f443 7380 orr.w r3, r3, #256 @ 0x100 8001982: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001984: 2003 movs r0, #3 8001986: f000 f94f bl 8001c28 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800198a: 200f movs r0, #15 800198c: f000 f808 bl 80019a0 /* Init the low level hardware */ HAL_MspInit(); 8001990: f7ff fa18 bl 8000dc4 /* Return function status */ return HAL_OK; 8001994: 2300 movs r3, #0 } 8001996: 4618 mov r0, r3 8001998: bd80 pop {r7, pc} 800199a: bf00 nop 800199c: 40023c00 .word 0x40023c00 080019a0 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80019a0: b580 push {r7, lr} 80019a2: b082 sub sp, #8 80019a4: af00 add r7, sp, #0 80019a6: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80019a8: 4b12 ldr r3, [pc, #72] @ (80019f4 ) 80019aa: 681a ldr r2, [r3, #0] 80019ac: 4b12 ldr r3, [pc, #72] @ (80019f8 ) 80019ae: 781b ldrb r3, [r3, #0] 80019b0: 4619 mov r1, r3 80019b2: f44f 737a mov.w r3, #1000 @ 0x3e8 80019b6: fbb3 f3f1 udiv r3, r3, r1 80019ba: fbb2 f3f3 udiv r3, r2, r3 80019be: 4618 mov r0, r3 80019c0: f000 f967 bl 8001c92 80019c4: 4603 mov r3, r0 80019c6: 2b00 cmp r3, #0 80019c8: d001 beq.n 80019ce { return HAL_ERROR; 80019ca: 2301 movs r3, #1 80019cc: e00e b.n 80019ec } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80019ce: 687b ldr r3, [r7, #4] 80019d0: 2b0f cmp r3, #15 80019d2: d80a bhi.n 80019ea { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80019d4: 2200 movs r2, #0 80019d6: 6879 ldr r1, [r7, #4] 80019d8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80019dc: f000 f92f bl 8001c3e uwTickPrio = TickPriority; 80019e0: 4a06 ldr r2, [pc, #24] @ (80019fc ) 80019e2: 687b ldr r3, [r7, #4] 80019e4: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80019e6: 2300 movs r3, #0 80019e8: e000 b.n 80019ec return HAL_ERROR; 80019ea: 2301 movs r3, #1 } 80019ec: 4618 mov r0, r3 80019ee: 3708 adds r7, #8 80019f0: 46bd mov sp, r7 80019f2: bd80 pop {r7, pc} 80019f4: 20000090 .word 0x20000090 80019f8: 20000098 .word 0x20000098 80019fc: 20000094 .word 0x20000094 08001a00 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001a00: b480 push {r7} 8001a02: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001a04: 4b06 ldr r3, [pc, #24] @ (8001a20 ) 8001a06: 781b ldrb r3, [r3, #0] 8001a08: 461a mov r2, r3 8001a0a: 4b06 ldr r3, [pc, #24] @ (8001a24 ) 8001a0c: 681b ldr r3, [r3, #0] 8001a0e: 4413 add r3, r2 8001a10: 4a04 ldr r2, [pc, #16] @ (8001a24 ) 8001a12: 6013 str r3, [r2, #0] } 8001a14: bf00 nop 8001a16: 46bd mov sp, r7 8001a18: f85d 7b04 ldr.w r7, [sp], #4 8001a1c: 4770 bx lr 8001a1e: bf00 nop 8001a20: 20000098 .word 0x20000098 8001a24: 2000071c .word 0x2000071c 08001a28 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001a28: b480 push {r7} 8001a2a: af00 add r7, sp, #0 return uwTick; 8001a2c: 4b03 ldr r3, [pc, #12] @ (8001a3c ) 8001a2e: 681b ldr r3, [r3, #0] } 8001a30: 4618 mov r0, r3 8001a32: 46bd mov sp, r7 8001a34: f85d 7b04 ldr.w r7, [sp], #4 8001a38: 4770 bx lr 8001a3a: bf00 nop 8001a3c: 2000071c .word 0x2000071c 08001a40 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001a40: b580 push {r7, lr} 8001a42: b084 sub sp, #16 8001a44: af00 add r7, sp, #0 8001a46: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001a48: f7ff ffee bl 8001a28 8001a4c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001a4e: 687b ldr r3, [r7, #4] 8001a50: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001a52: 68fb ldr r3, [r7, #12] 8001a54: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8001a58: d005 beq.n 8001a66 { wait += (uint32_t)(uwTickFreq); 8001a5a: 4b0a ldr r3, [pc, #40] @ (8001a84 ) 8001a5c: 781b ldrb r3, [r3, #0] 8001a5e: 461a mov r2, r3 8001a60: 68fb ldr r3, [r7, #12] 8001a62: 4413 add r3, r2 8001a64: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8001a66: bf00 nop 8001a68: f7ff ffde bl 8001a28 8001a6c: 4602 mov r2, r0 8001a6e: 68bb ldr r3, [r7, #8] 8001a70: 1ad3 subs r3, r2, r3 8001a72: 68fa ldr r2, [r7, #12] 8001a74: 429a cmp r2, r3 8001a76: d8f7 bhi.n 8001a68 { } } 8001a78: bf00 nop 8001a7a: bf00 nop 8001a7c: 3710 adds r7, #16 8001a7e: 46bd mov sp, r7 8001a80: bd80 pop {r7, pc} 8001a82: bf00 nop 8001a84: 20000098 .word 0x20000098 08001a88 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001a88: b480 push {r7} 8001a8a: b085 sub sp, #20 8001a8c: af00 add r7, sp, #0 8001a8e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001a90: 687b ldr r3, [r7, #4] 8001a92: f003 0307 and.w r3, r3, #7 8001a96: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001a98: 4b0c ldr r3, [pc, #48] @ (8001acc <__NVIC_SetPriorityGrouping+0x44>) 8001a9a: 68db ldr r3, [r3, #12] 8001a9c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001a9e: 68ba ldr r2, [r7, #8] 8001aa0: f64f 03ff movw r3, #63743 @ 0xf8ff 8001aa4: 4013 ands r3, r2 8001aa6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001aa8: 68fb ldr r3, [r7, #12] 8001aaa: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001aac: 68bb ldr r3, [r7, #8] 8001aae: 4313 orrs r3, r2 reg_value = (reg_value | 8001ab0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8001ab4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001ab8: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001aba: 4a04 ldr r2, [pc, #16] @ (8001acc <__NVIC_SetPriorityGrouping+0x44>) 8001abc: 68bb ldr r3, [r7, #8] 8001abe: 60d3 str r3, [r2, #12] } 8001ac0: bf00 nop 8001ac2: 3714 adds r7, #20 8001ac4: 46bd mov sp, r7 8001ac6: f85d 7b04 ldr.w r7, [sp], #4 8001aca: 4770 bx lr 8001acc: e000ed00 .word 0xe000ed00 08001ad0 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001ad0: b480 push {r7} 8001ad2: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001ad4: 4b04 ldr r3, [pc, #16] @ (8001ae8 <__NVIC_GetPriorityGrouping+0x18>) 8001ad6: 68db ldr r3, [r3, #12] 8001ad8: 0a1b lsrs r3, r3, #8 8001ada: f003 0307 and.w r3, r3, #7 } 8001ade: 4618 mov r0, r3 8001ae0: 46bd mov sp, r7 8001ae2: f85d 7b04 ldr.w r7, [sp], #4 8001ae6: 4770 bx lr 8001ae8: e000ed00 .word 0xe000ed00 08001aec <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8001aec: b480 push {r7} 8001aee: b083 sub sp, #12 8001af0: af00 add r7, sp, #0 8001af2: 4603 mov r3, r0 8001af4: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001af6: f997 3007 ldrsb.w r3, [r7, #7] 8001afa: 2b00 cmp r3, #0 8001afc: db0b blt.n 8001b16 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001afe: 79fb ldrb r3, [r7, #7] 8001b00: f003 021f and.w r2, r3, #31 8001b04: 4907 ldr r1, [pc, #28] @ (8001b24 <__NVIC_EnableIRQ+0x38>) 8001b06: f997 3007 ldrsb.w r3, [r7, #7] 8001b0a: 095b lsrs r3, r3, #5 8001b0c: 2001 movs r0, #1 8001b0e: fa00 f202 lsl.w r2, r0, r2 8001b12: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8001b16: bf00 nop 8001b18: 370c adds r7, #12 8001b1a: 46bd mov sp, r7 8001b1c: f85d 7b04 ldr.w r7, [sp], #4 8001b20: 4770 bx lr 8001b22: bf00 nop 8001b24: e000e100 .word 0xe000e100 08001b28 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001b28: b480 push {r7} 8001b2a: b083 sub sp, #12 8001b2c: af00 add r7, sp, #0 8001b2e: 4603 mov r3, r0 8001b30: 6039 str r1, [r7, #0] 8001b32: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001b34: f997 3007 ldrsb.w r3, [r7, #7] 8001b38: 2b00 cmp r3, #0 8001b3a: db0a blt.n 8001b52 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001b3c: 683b ldr r3, [r7, #0] 8001b3e: b2da uxtb r2, r3 8001b40: 490c ldr r1, [pc, #48] @ (8001b74 <__NVIC_SetPriority+0x4c>) 8001b42: f997 3007 ldrsb.w r3, [r7, #7] 8001b46: 0112 lsls r2, r2, #4 8001b48: b2d2 uxtb r2, r2 8001b4a: 440b add r3, r1 8001b4c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001b50: e00a b.n 8001b68 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001b52: 683b ldr r3, [r7, #0] 8001b54: b2da uxtb r2, r3 8001b56: 4908 ldr r1, [pc, #32] @ (8001b78 <__NVIC_SetPriority+0x50>) 8001b58: 79fb ldrb r3, [r7, #7] 8001b5a: f003 030f and.w r3, r3, #15 8001b5e: 3b04 subs r3, #4 8001b60: 0112 lsls r2, r2, #4 8001b62: b2d2 uxtb r2, r2 8001b64: 440b add r3, r1 8001b66: 761a strb r2, [r3, #24] } 8001b68: bf00 nop 8001b6a: 370c adds r7, #12 8001b6c: 46bd mov sp, r7 8001b6e: f85d 7b04 ldr.w r7, [sp], #4 8001b72: 4770 bx lr 8001b74: e000e100 .word 0xe000e100 8001b78: e000ed00 .word 0xe000ed00 08001b7c : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001b7c: b480 push {r7} 8001b7e: b089 sub sp, #36 @ 0x24 8001b80: af00 add r7, sp, #0 8001b82: 60f8 str r0, [r7, #12] 8001b84: 60b9 str r1, [r7, #8] 8001b86: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001b88: 68fb ldr r3, [r7, #12] 8001b8a: f003 0307 and.w r3, r3, #7 8001b8e: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001b90: 69fb ldr r3, [r7, #28] 8001b92: f1c3 0307 rsb r3, r3, #7 8001b96: 2b04 cmp r3, #4 8001b98: bf28 it cs 8001b9a: 2304 movcs r3, #4 8001b9c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001b9e: 69fb ldr r3, [r7, #28] 8001ba0: 3304 adds r3, #4 8001ba2: 2b06 cmp r3, #6 8001ba4: d902 bls.n 8001bac 8001ba6: 69fb ldr r3, [r7, #28] 8001ba8: 3b03 subs r3, #3 8001baa: e000 b.n 8001bae 8001bac: 2300 movs r3, #0 8001bae: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001bb0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8001bb4: 69bb ldr r3, [r7, #24] 8001bb6: fa02 f303 lsl.w r3, r2, r3 8001bba: 43da mvns r2, r3 8001bbc: 68bb ldr r3, [r7, #8] 8001bbe: 401a ands r2, r3 8001bc0: 697b ldr r3, [r7, #20] 8001bc2: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001bc4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001bc8: 697b ldr r3, [r7, #20] 8001bca: fa01 f303 lsl.w r3, r1, r3 8001bce: 43d9 mvns r1, r3 8001bd0: 687b ldr r3, [r7, #4] 8001bd2: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001bd4: 4313 orrs r3, r2 ); } 8001bd6: 4618 mov r0, r3 8001bd8: 3724 adds r7, #36 @ 0x24 8001bda: 46bd mov sp, r7 8001bdc: f85d 7b04 ldr.w r7, [sp], #4 8001be0: 4770 bx lr ... 08001be4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001be4: b580 push {r7, lr} 8001be6: b082 sub sp, #8 8001be8: af00 add r7, sp, #0 8001bea: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001bec: 687b ldr r3, [r7, #4] 8001bee: 3b01 subs r3, #1 8001bf0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8001bf4: d301 bcc.n 8001bfa { return (1UL); /* Reload value impossible */ 8001bf6: 2301 movs r3, #1 8001bf8: e00f b.n 8001c1a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001bfa: 4a0a ldr r2, [pc, #40] @ (8001c24 ) 8001bfc: 687b ldr r3, [r7, #4] 8001bfe: 3b01 subs r3, #1 8001c00: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001c02: 210f movs r1, #15 8001c04: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8001c08: f7ff ff8e bl 8001b28 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001c0c: 4b05 ldr r3, [pc, #20] @ (8001c24 ) 8001c0e: 2200 movs r2, #0 8001c10: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001c12: 4b04 ldr r3, [pc, #16] @ (8001c24 ) 8001c14: 2207 movs r2, #7 8001c16: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001c18: 2300 movs r3, #0 } 8001c1a: 4618 mov r0, r3 8001c1c: 3708 adds r7, #8 8001c1e: 46bd mov sp, r7 8001c20: bd80 pop {r7, pc} 8001c22: bf00 nop 8001c24: e000e010 .word 0xe000e010 08001c28 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001c28: b580 push {r7, lr} 8001c2a: b082 sub sp, #8 8001c2c: af00 add r7, sp, #0 8001c2e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001c30: 6878 ldr r0, [r7, #4] 8001c32: f7ff ff29 bl 8001a88 <__NVIC_SetPriorityGrouping> } 8001c36: bf00 nop 8001c38: 3708 adds r7, #8 8001c3a: 46bd mov sp, r7 8001c3c: bd80 pop {r7, pc} 08001c3e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001c3e: b580 push {r7, lr} 8001c40: b086 sub sp, #24 8001c42: af00 add r7, sp, #0 8001c44: 4603 mov r3, r0 8001c46: 60b9 str r1, [r7, #8] 8001c48: 607a str r2, [r7, #4] 8001c4a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001c4c: 2300 movs r3, #0 8001c4e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001c50: f7ff ff3e bl 8001ad0 <__NVIC_GetPriorityGrouping> 8001c54: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001c56: 687a ldr r2, [r7, #4] 8001c58: 68b9 ldr r1, [r7, #8] 8001c5a: 6978 ldr r0, [r7, #20] 8001c5c: f7ff ff8e bl 8001b7c 8001c60: 4602 mov r2, r0 8001c62: f997 300f ldrsb.w r3, [r7, #15] 8001c66: 4611 mov r1, r2 8001c68: 4618 mov r0, r3 8001c6a: f7ff ff5d bl 8001b28 <__NVIC_SetPriority> } 8001c6e: bf00 nop 8001c70: 3718 adds r7, #24 8001c72: 46bd mov sp, r7 8001c74: bd80 pop {r7, pc} 08001c76 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8001c76: b580 push {r7, lr} 8001c78: b082 sub sp, #8 8001c7a: af00 add r7, sp, #0 8001c7c: 4603 mov r3, r0 8001c7e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001c80: f997 3007 ldrsb.w r3, [r7, #7] 8001c84: 4618 mov r0, r3 8001c86: f7ff ff31 bl 8001aec <__NVIC_EnableIRQ> } 8001c8a: bf00 nop 8001c8c: 3708 adds r7, #8 8001c8e: 46bd mov sp, r7 8001c90: bd80 pop {r7, pc} 08001c92 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001c92: b580 push {r7, lr} 8001c94: b082 sub sp, #8 8001c96: af00 add r7, sp, #0 8001c98: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001c9a: 6878 ldr r0, [r7, #4] 8001c9c: f7ff ffa2 bl 8001be4 8001ca0: 4603 mov r3, r0 } 8001ca2: 4618 mov r0, r3 8001ca4: 3708 adds r7, #8 8001ca6: 46bd mov sp, r7 8001ca8: bd80 pop {r7, pc} ... 08001cac : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8001cac: b580 push {r7, lr} 8001cae: b086 sub sp, #24 8001cb0: af00 add r7, sp, #0 8001cb2: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 8001cb4: 2300 movs r3, #0 8001cb6: 617b str r3, [r7, #20] uint32_t tickstart = HAL_GetTick(); 8001cb8: f7ff feb6 bl 8001a28 8001cbc: 6138 str r0, [r7, #16] DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) 8001cbe: 687b ldr r3, [r7, #4] 8001cc0: 2b00 cmp r3, #0 8001cc2: d101 bne.n 8001cc8 { return HAL_ERROR; 8001cc4: 2301 movs r3, #1 8001cc6: e099 b.n 8001dfc assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001cc8: 687b ldr r3, [r7, #4] 8001cca: 2202 movs r2, #2 8001ccc: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8001cd0: 687b ldr r3, [r7, #4] 8001cd2: 2200 movs r2, #0 8001cd4: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8001cd8: 687b ldr r3, [r7, #4] 8001cda: 681b ldr r3, [r3, #0] 8001cdc: 681a ldr r2, [r3, #0] 8001cde: 687b ldr r3, [r7, #4] 8001ce0: 681b ldr r3, [r3, #0] 8001ce2: f022 0201 bic.w r2, r2, #1 8001ce6: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001ce8: e00f b.n 8001d0a { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8001cea: f7ff fe9d bl 8001a28 8001cee: 4602 mov r2, r0 8001cf0: 693b ldr r3, [r7, #16] 8001cf2: 1ad3 subs r3, r2, r3 8001cf4: 2b05 cmp r3, #5 8001cf6: d908 bls.n 8001d0a { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8001cf8: 687b ldr r3, [r7, #4] 8001cfa: 2220 movs r2, #32 8001cfc: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8001cfe: 687b ldr r3, [r7, #4] 8001d00: 2203 movs r2, #3 8001d02: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_TIMEOUT; 8001d06: 2303 movs r3, #3 8001d08: e078 b.n 8001dfc while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001d0a: 687b ldr r3, [r7, #4] 8001d0c: 681b ldr r3, [r3, #0] 8001d0e: 681b ldr r3, [r3, #0] 8001d10: f003 0301 and.w r3, r3, #1 8001d14: 2b00 cmp r3, #0 8001d16: d1e8 bne.n 8001cea } } /* Get the CR register value */ tmp = hdma->Instance->CR; 8001d18: 687b ldr r3, [r7, #4] 8001d1a: 681b ldr r3, [r3, #0] 8001d1c: 681b ldr r3, [r3, #0] 8001d1e: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8001d20: 697a ldr r2, [r7, #20] 8001d22: 4b38 ldr r3, [pc, #224] @ (8001e04 ) 8001d24: 4013 ands r3, r2 8001d26: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001d28: 687b ldr r3, [r7, #4] 8001d2a: 685a ldr r2, [r3, #4] 8001d2c: 687b ldr r3, [r7, #4] 8001d2e: 689b ldr r3, [r3, #8] 8001d30: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001d32: 687b ldr r3, [r7, #4] 8001d34: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001d36: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001d38: 687b ldr r3, [r7, #4] 8001d3a: 691b ldr r3, [r3, #16] 8001d3c: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001d3e: 687b ldr r3, [r7, #4] 8001d40: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8001d42: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001d44: 687b ldr r3, [r7, #4] 8001d46: 699b ldr r3, [r3, #24] 8001d48: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001d4a: 687b ldr r3, [r7, #4] 8001d4c: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001d4e: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001d50: 687b ldr r3, [r7, #4] 8001d52: 6a1b ldr r3, [r3, #32] 8001d54: 4313 orrs r3, r2 tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001d56: 697a ldr r2, [r7, #20] 8001d58: 4313 orrs r3, r2 8001d5a: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001d5c: 687b ldr r3, [r7, #4] 8001d5e: 6a5b ldr r3, [r3, #36] @ 0x24 8001d60: 2b04 cmp r3, #4 8001d62: d107 bne.n 8001d74 { /* Get memory burst and peripheral burst */ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8001d64: 687b ldr r3, [r7, #4] 8001d66: 6ada ldr r2, [r3, #44] @ 0x2c 8001d68: 687b ldr r3, [r7, #4] 8001d6a: 6b1b ldr r3, [r3, #48] @ 0x30 8001d6c: 4313 orrs r3, r2 8001d6e: 697a ldr r2, [r7, #20] 8001d70: 4313 orrs r3, r2 8001d72: 617b str r3, [r7, #20] } /* Write to DMA Stream CR register */ hdma->Instance->CR = tmp; 8001d74: 687b ldr r3, [r7, #4] 8001d76: 681b ldr r3, [r3, #0] 8001d78: 697a ldr r2, [r7, #20] 8001d7a: 601a str r2, [r3, #0] /* Get the FCR register value */ tmp = hdma->Instance->FCR; 8001d7c: 687b ldr r3, [r7, #4] 8001d7e: 681b ldr r3, [r3, #0] 8001d80: 695b ldr r3, [r3, #20] 8001d82: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8001d84: 697b ldr r3, [r7, #20] 8001d86: f023 0307 bic.w r3, r3, #7 8001d8a: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ tmp |= hdma->Init.FIFOMode; 8001d8c: 687b ldr r3, [r7, #4] 8001d8e: 6a5b ldr r3, [r3, #36] @ 0x24 8001d90: 697a ldr r2, [r7, #20] 8001d92: 4313 orrs r3, r2 8001d94: 617b str r3, [r7, #20] /* The FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001d96: 687b ldr r3, [r7, #4] 8001d98: 6a5b ldr r3, [r3, #36] @ 0x24 8001d9a: 2b04 cmp r3, #4 8001d9c: d117 bne.n 8001dce { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; 8001d9e: 687b ldr r3, [r7, #4] 8001da0: 6a9b ldr r3, [r3, #40] @ 0x28 8001da2: 697a ldr r2, [r7, #20] 8001da4: 4313 orrs r3, r2 8001da6: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 bursts */ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8001da8: 687b ldr r3, [r7, #4] 8001daa: 6adb ldr r3, [r3, #44] @ 0x2c 8001dac: 2b00 cmp r3, #0 8001dae: d00e beq.n 8001dce { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8001db0: 6878 ldr r0, [r7, #4] 8001db2: f000 fb01 bl 80023b8 8001db6: 4603 mov r3, r0 8001db8: 2b00 cmp r3, #0 8001dba: d008 beq.n 8001dce { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8001dbc: 687b ldr r3, [r7, #4] 8001dbe: 2240 movs r2, #64 @ 0x40 8001dc0: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001dc2: 687b ldr r3, [r7, #4] 8001dc4: 2201 movs r2, #1 8001dc6: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8001dca: 2301 movs r3, #1 8001dcc: e016 b.n 8001dfc } } } /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; 8001dce: 687b ldr r3, [r7, #4] 8001dd0: 681b ldr r3, [r3, #0] 8001dd2: 697a ldr r2, [r7, #20] 8001dd4: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8001dd6: 6878 ldr r0, [r7, #4] 8001dd8: f000 fab8 bl 800234c 8001ddc: 4603 mov r3, r0 8001dde: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001de0: 687b ldr r3, [r7, #4] 8001de2: 6ddb ldr r3, [r3, #92] @ 0x5c 8001de4: 223f movs r2, #63 @ 0x3f 8001de6: 409a lsls r2, r3 8001de8: 68fb ldr r3, [r7, #12] 8001dea: 609a str r2, [r3, #8] /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001dec: 687b ldr r3, [r7, #4] 8001dee: 2200 movs r2, #0 8001df0: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001df2: 687b ldr r3, [r7, #4] 8001df4: 2201 movs r2, #1 8001df6: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8001dfa: 2300 movs r3, #0 } 8001dfc: 4618 mov r0, r3 8001dfe: 3718 adds r7, #24 8001e00: 46bd mov sp, r7 8001e02: bd80 pop {r7, pc} 8001e04: f010803f .word 0xf010803f 08001e08 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8001e08: b580 push {r7, lr} 8001e0a: b086 sub sp, #24 8001e0c: af00 add r7, sp, #0 8001e0e: 60f8 str r0, [r7, #12] 8001e10: 60b9 str r1, [r7, #8] 8001e12: 607a str r2, [r7, #4] 8001e14: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8001e16: 2300 movs r3, #0 8001e18: 75fb strb r3, [r7, #23] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001e1a: 68fb ldr r3, [r7, #12] 8001e1c: 6d9b ldr r3, [r3, #88] @ 0x58 8001e1e: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8001e20: 68fb ldr r3, [r7, #12] 8001e22: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8001e26: 2b01 cmp r3, #1 8001e28: d101 bne.n 8001e2e 8001e2a: 2302 movs r3, #2 8001e2c: e040 b.n 8001eb0 8001e2e: 68fb ldr r3, [r7, #12] 8001e30: 2201 movs r2, #1 8001e32: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8001e36: 68fb ldr r3, [r7, #12] 8001e38: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001e3c: b2db uxtb r3, r3 8001e3e: 2b01 cmp r3, #1 8001e40: d12f bne.n 8001ea2 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001e42: 68fb ldr r3, [r7, #12] 8001e44: 2202 movs r2, #2 8001e46: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001e4a: 68fb ldr r3, [r7, #12] 8001e4c: 2200 movs r2, #0 8001e4e: 655a str r2, [r3, #84] @ 0x54 /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8001e50: 683b ldr r3, [r7, #0] 8001e52: 687a ldr r2, [r7, #4] 8001e54: 68b9 ldr r1, [r7, #8] 8001e56: 68f8 ldr r0, [r7, #12] 8001e58: f000 fa4a bl 80022f0 /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001e5c: 68fb ldr r3, [r7, #12] 8001e5e: 6ddb ldr r3, [r3, #92] @ 0x5c 8001e60: 223f movs r2, #63 @ 0x3f 8001e62: 409a lsls r2, r3 8001e64: 693b ldr r3, [r7, #16] 8001e66: 609a str r2, [r3, #8] /* Enable Common interrupts*/ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; 8001e68: 68fb ldr r3, [r7, #12] 8001e6a: 681b ldr r3, [r3, #0] 8001e6c: 681a ldr r2, [r3, #0] 8001e6e: 68fb ldr r3, [r7, #12] 8001e70: 681b ldr r3, [r3, #0] 8001e72: f042 0216 orr.w r2, r2, #22 8001e76: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8001e78: 68fb ldr r3, [r7, #12] 8001e7a: 6c1b ldr r3, [r3, #64] @ 0x40 8001e7c: 2b00 cmp r3, #0 8001e7e: d007 beq.n 8001e90 { hdma->Instance->CR |= DMA_IT_HT; 8001e80: 68fb ldr r3, [r7, #12] 8001e82: 681b ldr r3, [r3, #0] 8001e84: 681a ldr r2, [r3, #0] 8001e86: 68fb ldr r3, [r7, #12] 8001e88: 681b ldr r3, [r3, #0] 8001e8a: f042 0208 orr.w r2, r2, #8 8001e8e: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8001e90: 68fb ldr r3, [r7, #12] 8001e92: 681b ldr r3, [r3, #0] 8001e94: 681a ldr r2, [r3, #0] 8001e96: 68fb ldr r3, [r7, #12] 8001e98: 681b ldr r3, [r3, #0] 8001e9a: f042 0201 orr.w r2, r2, #1 8001e9e: 601a str r2, [r3, #0] 8001ea0: e005 b.n 8001eae } else { /* Process unlocked */ __HAL_UNLOCK(hdma); 8001ea2: 68fb ldr r3, [r7, #12] 8001ea4: 2200 movs r2, #0 8001ea6: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_BUSY; 8001eaa: 2302 movs r3, #2 8001eac: 75fb strb r3, [r7, #23] } return status; 8001eae: 7dfb ldrb r3, [r7, #23] } 8001eb0: 4618 mov r0, r3 8001eb2: 3718 adds r7, #24 8001eb4: 46bd mov sp, r7 8001eb6: bd80 pop {r7, pc} 08001eb8 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8001eb8: b580 push {r7, lr} 8001eba: b084 sub sp, #16 8001ebc: af00 add r7, sp, #0 8001ebe: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001ec0: 687b ldr r3, [r7, #4] 8001ec2: 6d9b ldr r3, [r3, #88] @ 0x58 8001ec4: 60fb str r3, [r7, #12] uint32_t tickstart = HAL_GetTick(); 8001ec6: f7ff fdaf bl 8001a28 8001eca: 60b8 str r0, [r7, #8] if(hdma->State != HAL_DMA_STATE_BUSY) 8001ecc: 687b ldr r3, [r7, #4] 8001ece: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001ed2: b2db uxtb r3, r3 8001ed4: 2b02 cmp r3, #2 8001ed6: d008 beq.n 8001eea { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001ed8: 687b ldr r3, [r7, #4] 8001eda: 2280 movs r2, #128 @ 0x80 8001edc: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001ede: 687b ldr r3, [r7, #4] 8001ee0: 2200 movs r2, #0 8001ee2: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8001ee6: 2301 movs r3, #1 8001ee8: e052 b.n 8001f90 } else { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8001eea: 687b ldr r3, [r7, #4] 8001eec: 681b ldr r3, [r3, #0] 8001eee: 681a ldr r2, [r3, #0] 8001ef0: 687b ldr r3, [r7, #4] 8001ef2: 681b ldr r3, [r3, #0] 8001ef4: f022 0216 bic.w r2, r2, #22 8001ef8: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 8001efa: 687b ldr r3, [r7, #4] 8001efc: 681b ldr r3, [r3, #0] 8001efe: 695a ldr r2, [r3, #20] 8001f00: 687b ldr r3, [r7, #4] 8001f02: 681b ldr r3, [r3, #0] 8001f04: f022 0280 bic.w r2, r2, #128 @ 0x80 8001f08: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8001f0a: 687b ldr r3, [r7, #4] 8001f0c: 6c1b ldr r3, [r3, #64] @ 0x40 8001f0e: 2b00 cmp r3, #0 8001f10: d103 bne.n 8001f1a 8001f12: 687b ldr r3, [r7, #4] 8001f14: 6c9b ldr r3, [r3, #72] @ 0x48 8001f16: 2b00 cmp r3, #0 8001f18: d007 beq.n 8001f2a { hdma->Instance->CR &= ~(DMA_IT_HT); 8001f1a: 687b ldr r3, [r7, #4] 8001f1c: 681b ldr r3, [r3, #0] 8001f1e: 681a ldr r2, [r3, #0] 8001f20: 687b ldr r3, [r7, #4] 8001f22: 681b ldr r3, [r3, #0] 8001f24: f022 0208 bic.w r2, r2, #8 8001f28: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8001f2a: 687b ldr r3, [r7, #4] 8001f2c: 681b ldr r3, [r3, #0] 8001f2e: 681a ldr r2, [r3, #0] 8001f30: 687b ldr r3, [r7, #4] 8001f32: 681b ldr r3, [r3, #0] 8001f34: f022 0201 bic.w r2, r2, #1 8001f38: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001f3a: e013 b.n 8001f64 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8001f3c: f7ff fd74 bl 8001a28 8001f40: 4602 mov r2, r0 8001f42: 68bb ldr r3, [r7, #8] 8001f44: 1ad3 subs r3, r2, r3 8001f46: 2b05 cmp r3, #5 8001f48: d90c bls.n 8001f64 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8001f4a: 687b ldr r3, [r7, #4] 8001f4c: 2220 movs r2, #32 8001f4e: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8001f50: 687b ldr r3, [r7, #4] 8001f52: 2203 movs r2, #3 8001f54: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001f58: 687b ldr r3, [r7, #4] 8001f5a: 2200 movs r2, #0 8001f5c: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_TIMEOUT; 8001f60: 2303 movs r3, #3 8001f62: e015 b.n 8001f90 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001f64: 687b ldr r3, [r7, #4] 8001f66: 681b ldr r3, [r3, #0] 8001f68: 681b ldr r3, [r3, #0] 8001f6a: f003 0301 and.w r3, r3, #1 8001f6e: 2b00 cmp r3, #0 8001f70: d1e4 bne.n 8001f3c } } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001f72: 687b ldr r3, [r7, #4] 8001f74: 6ddb ldr r3, [r3, #92] @ 0x5c 8001f76: 223f movs r2, #63 @ 0x3f 8001f78: 409a lsls r2, r3 8001f7a: 68fb ldr r3, [r7, #12] 8001f7c: 609a str r2, [r3, #8] /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8001f7e: 687b ldr r3, [r7, #4] 8001f80: 2201 movs r2, #1 8001f82: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001f86: 687b ldr r3, [r7, #4] 8001f88: 2200 movs r2, #0 8001f8a: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 8001f8e: 2300 movs r3, #0 } 8001f90: 4618 mov r0, r3 8001f92: 3710 adds r7, #16 8001f94: 46bd mov sp, r7 8001f96: bd80 pop {r7, pc} 08001f98 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8001f98: b480 push {r7} 8001f9a: b083 sub sp, #12 8001f9c: af00 add r7, sp, #0 8001f9e: 6078 str r0, [r7, #4] if(hdma->State != HAL_DMA_STATE_BUSY) 8001fa0: 687b ldr r3, [r7, #4] 8001fa2: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001fa6: b2db uxtb r3, r3 8001fa8: 2b02 cmp r3, #2 8001faa: d004 beq.n 8001fb6 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001fac: 687b ldr r3, [r7, #4] 8001fae: 2280 movs r2, #128 @ 0x80 8001fb0: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 8001fb2: 2301 movs r3, #1 8001fb4: e00c b.n 8001fd0 } else { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 8001fb6: 687b ldr r3, [r7, #4] 8001fb8: 2205 movs r2, #5 8001fba: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8001fbe: 687b ldr r3, [r7, #4] 8001fc0: 681b ldr r3, [r3, #0] 8001fc2: 681a ldr r2, [r3, #0] 8001fc4: 687b ldr r3, [r7, #4] 8001fc6: 681b ldr r3, [r3, #0] 8001fc8: f022 0201 bic.w r2, r2, #1 8001fcc: 601a str r2, [r3, #0] } return HAL_OK; 8001fce: 2300 movs r3, #0 } 8001fd0: 4618 mov r0, r3 8001fd2: 370c adds r7, #12 8001fd4: 46bd mov sp, r7 8001fd6: f85d 7b04 ldr.w r7, [sp], #4 8001fda: 4770 bx lr 08001fdc : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8001fdc: b580 push {r7, lr} 8001fde: b086 sub sp, #24 8001fe0: af00 add r7, sp, #0 8001fe2: 6078 str r0, [r7, #4] uint32_t tmpisr; __IO uint32_t count = 0U; 8001fe4: 2300 movs r3, #0 8001fe6: 60bb str r3, [r7, #8] uint32_t timeout = SystemCoreClock / 9600U; 8001fe8: 4b8e ldr r3, [pc, #568] @ (8002224 ) 8001fea: 681b ldr r3, [r3, #0] 8001fec: 4a8e ldr r2, [pc, #568] @ (8002228 ) 8001fee: fba2 2303 umull r2, r3, r2, r3 8001ff2: 0a9b lsrs r3, r3, #10 8001ff4: 617b str r3, [r7, #20] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001ff6: 687b ldr r3, [r7, #4] 8001ff8: 6d9b ldr r3, [r3, #88] @ 0x58 8001ffa: 613b str r3, [r7, #16] tmpisr = regs->ISR; 8001ffc: 693b ldr r3, [r7, #16] 8001ffe: 681b ldr r3, [r3, #0] 8002000: 60fb str r3, [r7, #12] /* Transfer Error Interrupt management ***************************************/ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) 8002002: 687b ldr r3, [r7, #4] 8002004: 6ddb ldr r3, [r3, #92] @ 0x5c 8002006: 2208 movs r2, #8 8002008: 409a lsls r2, r3 800200a: 68fb ldr r3, [r7, #12] 800200c: 4013 ands r3, r2 800200e: 2b00 cmp r3, #0 8002010: d01a beq.n 8002048 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) 8002012: 687b ldr r3, [r7, #4] 8002014: 681b ldr r3, [r3, #0] 8002016: 681b ldr r3, [r3, #0] 8002018: f003 0304 and.w r3, r3, #4 800201c: 2b00 cmp r3, #0 800201e: d013 beq.n 8002048 { /* Disable the transfer error interrupt */ hdma->Instance->CR &= ~(DMA_IT_TE); 8002020: 687b ldr r3, [r7, #4] 8002022: 681b ldr r3, [r3, #0] 8002024: 681a ldr r2, [r3, #0] 8002026: 687b ldr r3, [r7, #4] 8002028: 681b ldr r3, [r3, #0] 800202a: f022 0204 bic.w r2, r2, #4 800202e: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; 8002030: 687b ldr r3, [r7, #4] 8002032: 6ddb ldr r3, [r3, #92] @ 0x5c 8002034: 2208 movs r2, #8 8002036: 409a lsls r2, r3 8002038: 693b ldr r3, [r7, #16] 800203a: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 800203c: 687b ldr r3, [r7, #4] 800203e: 6d5b ldr r3, [r3, #84] @ 0x54 8002040: f043 0201 orr.w r2, r3, #1 8002044: 687b ldr r3, [r7, #4] 8002046: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) 8002048: 687b ldr r3, [r7, #4] 800204a: 6ddb ldr r3, [r3, #92] @ 0x5c 800204c: 2201 movs r2, #1 800204e: 409a lsls r2, r3 8002050: 68fb ldr r3, [r7, #12] 8002052: 4013 ands r3, r2 8002054: 2b00 cmp r3, #0 8002056: d012 beq.n 800207e { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) 8002058: 687b ldr r3, [r7, #4] 800205a: 681b ldr r3, [r3, #0] 800205c: 695b ldr r3, [r3, #20] 800205e: f003 0380 and.w r3, r3, #128 @ 0x80 8002062: 2b00 cmp r3, #0 8002064: d00b beq.n 800207e { /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; 8002066: 687b ldr r3, [r7, #4] 8002068: 6ddb ldr r3, [r3, #92] @ 0x5c 800206a: 2201 movs r2, #1 800206c: 409a lsls r2, r3 800206e: 693b ldr r3, [r7, #16] 8002070: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8002072: 687b ldr r3, [r7, #4] 8002074: 6d5b ldr r3, [r3, #84] @ 0x54 8002076: f043 0202 orr.w r2, r3, #2 800207a: 687b ldr r3, [r7, #4] 800207c: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) 800207e: 687b ldr r3, [r7, #4] 8002080: 6ddb ldr r3, [r3, #92] @ 0x5c 8002082: 2204 movs r2, #4 8002084: 409a lsls r2, r3 8002086: 68fb ldr r3, [r7, #12] 8002088: 4013 ands r3, r2 800208a: 2b00 cmp r3, #0 800208c: d012 beq.n 80020b4 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) 800208e: 687b ldr r3, [r7, #4] 8002090: 681b ldr r3, [r3, #0] 8002092: 681b ldr r3, [r3, #0] 8002094: f003 0302 and.w r3, r3, #2 8002098: 2b00 cmp r3, #0 800209a: d00b beq.n 80020b4 { /* Clear the direct mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; 800209c: 687b ldr r3, [r7, #4] 800209e: 6ddb ldr r3, [r3, #92] @ 0x5c 80020a0: 2204 movs r2, #4 80020a2: 409a lsls r2, r3 80020a4: 693b ldr r3, [r7, #16] 80020a6: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 80020a8: 687b ldr r3, [r7, #4] 80020aa: 6d5b ldr r3, [r3, #84] @ 0x54 80020ac: f043 0204 orr.w r2, r3, #4 80020b0: 687b ldr r3, [r7, #4] 80020b2: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) 80020b4: 687b ldr r3, [r7, #4] 80020b6: 6ddb ldr r3, [r3, #92] @ 0x5c 80020b8: 2210 movs r2, #16 80020ba: 409a lsls r2, r3 80020bc: 68fb ldr r3, [r7, #12] 80020be: 4013 ands r3, r2 80020c0: 2b00 cmp r3, #0 80020c2: d043 beq.n 800214c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) 80020c4: 687b ldr r3, [r7, #4] 80020c6: 681b ldr r3, [r3, #0] 80020c8: 681b ldr r3, [r3, #0] 80020ca: f003 0308 and.w r3, r3, #8 80020ce: 2b00 cmp r3, #0 80020d0: d03c beq.n 800214c { /* Clear the half transfer complete flag */ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; 80020d2: 687b ldr r3, [r7, #4] 80020d4: 6ddb ldr r3, [r3, #92] @ 0x5c 80020d6: 2210 movs r2, #16 80020d8: 409a lsls r2, r3 80020da: 693b ldr r3, [r7, #16] 80020dc: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 80020de: 687b ldr r3, [r7, #4] 80020e0: 681b ldr r3, [r3, #0] 80020e2: 681b ldr r3, [r3, #0] 80020e4: f403 2380 and.w r3, r3, #262144 @ 0x40000 80020e8: 2b00 cmp r3, #0 80020ea: d018 beq.n 800211e { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 80020ec: 687b ldr r3, [r7, #4] 80020ee: 681b ldr r3, [r3, #0] 80020f0: 681b ldr r3, [r3, #0] 80020f2: f403 2300 and.w r3, r3, #524288 @ 0x80000 80020f6: 2b00 cmp r3, #0 80020f8: d108 bne.n 800210c { if(hdma->XferHalfCpltCallback != NULL) 80020fa: 687b ldr r3, [r7, #4] 80020fc: 6c1b ldr r3, [r3, #64] @ 0x40 80020fe: 2b00 cmp r3, #0 8002100: d024 beq.n 800214c { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002102: 687b ldr r3, [r7, #4] 8002104: 6c1b ldr r3, [r3, #64] @ 0x40 8002106: 6878 ldr r0, [r7, #4] 8002108: 4798 blx r3 800210a: e01f b.n 800214c } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 800210c: 687b ldr r3, [r7, #4] 800210e: 6c9b ldr r3, [r3, #72] @ 0x48 8002110: 2b00 cmp r3, #0 8002112: d01b beq.n 800214c { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8002114: 687b ldr r3, [r7, #4] 8002116: 6c9b ldr r3, [r3, #72] @ 0x48 8002118: 6878 ldr r0, [r7, #4] 800211a: 4798 blx r3 800211c: e016 b.n 800214c } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 800211e: 687b ldr r3, [r7, #4] 8002120: 681b ldr r3, [r3, #0] 8002122: 681b ldr r3, [r3, #0] 8002124: f403 7380 and.w r3, r3, #256 @ 0x100 8002128: 2b00 cmp r3, #0 800212a: d107 bne.n 800213c { /* Disable the half transfer interrupt */ hdma->Instance->CR &= ~(DMA_IT_HT); 800212c: 687b ldr r3, [r7, #4] 800212e: 681b ldr r3, [r3, #0] 8002130: 681a ldr r2, [r3, #0] 8002132: 687b ldr r3, [r7, #4] 8002134: 681b ldr r3, [r3, #0] 8002136: f022 0208 bic.w r2, r2, #8 800213a: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 800213c: 687b ldr r3, [r7, #4] 800213e: 6c1b ldr r3, [r3, #64] @ 0x40 8002140: 2b00 cmp r3, #0 8002142: d003 beq.n 800214c { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002144: 687b ldr r3, [r7, #4] 8002146: 6c1b ldr r3, [r3, #64] @ 0x40 8002148: 6878 ldr r0, [r7, #4] 800214a: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) 800214c: 687b ldr r3, [r7, #4] 800214e: 6ddb ldr r3, [r3, #92] @ 0x5c 8002150: 2220 movs r2, #32 8002152: 409a lsls r2, r3 8002154: 68fb ldr r3, [r7, #12] 8002156: 4013 ands r3, r2 8002158: 2b00 cmp r3, #0 800215a: f000 808f beq.w 800227c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) 800215e: 687b ldr r3, [r7, #4] 8002160: 681b ldr r3, [r3, #0] 8002162: 681b ldr r3, [r3, #0] 8002164: f003 0310 and.w r3, r3, #16 8002168: 2b00 cmp r3, #0 800216a: f000 8087 beq.w 800227c { /* Clear the transfer complete flag */ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; 800216e: 687b ldr r3, [r7, #4] 8002170: 6ddb ldr r3, [r3, #92] @ 0x5c 8002172: 2220 movs r2, #32 8002174: 409a lsls r2, r3 8002176: 693b ldr r3, [r7, #16] 8002178: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 800217a: 687b ldr r3, [r7, #4] 800217c: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8002180: b2db uxtb r3, r3 8002182: 2b05 cmp r3, #5 8002184: d136 bne.n 80021f4 { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8002186: 687b ldr r3, [r7, #4] 8002188: 681b ldr r3, [r3, #0] 800218a: 681a ldr r2, [r3, #0] 800218c: 687b ldr r3, [r7, #4] 800218e: 681b ldr r3, [r3, #0] 8002190: f022 0216 bic.w r2, r2, #22 8002194: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 8002196: 687b ldr r3, [r7, #4] 8002198: 681b ldr r3, [r3, #0] 800219a: 695a ldr r2, [r3, #20] 800219c: 687b ldr r3, [r7, #4] 800219e: 681b ldr r3, [r3, #0] 80021a0: f022 0280 bic.w r2, r2, #128 @ 0x80 80021a4: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 80021a6: 687b ldr r3, [r7, #4] 80021a8: 6c1b ldr r3, [r3, #64] @ 0x40 80021aa: 2b00 cmp r3, #0 80021ac: d103 bne.n 80021b6 80021ae: 687b ldr r3, [r7, #4] 80021b0: 6c9b ldr r3, [r3, #72] @ 0x48 80021b2: 2b00 cmp r3, #0 80021b4: d007 beq.n 80021c6 { hdma->Instance->CR &= ~(DMA_IT_HT); 80021b6: 687b ldr r3, [r7, #4] 80021b8: 681b ldr r3, [r3, #0] 80021ba: 681a ldr r2, [r3, #0] 80021bc: 687b ldr r3, [r7, #4] 80021be: 681b ldr r3, [r3, #0] 80021c0: f022 0208 bic.w r2, r2, #8 80021c4: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 80021c6: 687b ldr r3, [r7, #4] 80021c8: 6ddb ldr r3, [r3, #92] @ 0x5c 80021ca: 223f movs r2, #63 @ 0x3f 80021cc: 409a lsls r2, r3 80021ce: 693b ldr r3, [r7, #16] 80021d0: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80021d2: 687b ldr r3, [r7, #4] 80021d4: 2201 movs r2, #1 80021d6: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80021da: 687b ldr r3, [r7, #4] 80021dc: 2200 movs r2, #0 80021de: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 80021e2: 687b ldr r3, [r7, #4] 80021e4: 6d1b ldr r3, [r3, #80] @ 0x50 80021e6: 2b00 cmp r3, #0 80021e8: d07e beq.n 80022e8 { hdma->XferAbortCallback(hdma); 80021ea: 687b ldr r3, [r7, #4] 80021ec: 6d1b ldr r3, [r3, #80] @ 0x50 80021ee: 6878 ldr r0, [r7, #4] 80021f0: 4798 blx r3 } return; 80021f2: e079 b.n 80022e8 } if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 80021f4: 687b ldr r3, [r7, #4] 80021f6: 681b ldr r3, [r3, #0] 80021f8: 681b ldr r3, [r3, #0] 80021fa: f403 2380 and.w r3, r3, #262144 @ 0x40000 80021fe: 2b00 cmp r3, #0 8002200: d01d beq.n 800223e { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 8002202: 687b ldr r3, [r7, #4] 8002204: 681b ldr r3, [r3, #0] 8002206: 681b ldr r3, [r3, #0] 8002208: f403 2300 and.w r3, r3, #524288 @ 0x80000 800220c: 2b00 cmp r3, #0 800220e: d10d bne.n 800222c { if(hdma->XferM1CpltCallback != NULL) 8002210: 687b ldr r3, [r7, #4] 8002212: 6c5b ldr r3, [r3, #68] @ 0x44 8002214: 2b00 cmp r3, #0 8002216: d031 beq.n 800227c { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 8002218: 687b ldr r3, [r7, #4] 800221a: 6c5b ldr r3, [r3, #68] @ 0x44 800221c: 6878 ldr r0, [r7, #4] 800221e: 4798 blx r3 8002220: e02c b.n 800227c 8002222: bf00 nop 8002224: 20000090 .word 0x20000090 8002228: 1b4e81b5 .word 0x1b4e81b5 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800222c: 687b ldr r3, [r7, #4] 800222e: 6bdb ldr r3, [r3, #60] @ 0x3c 8002230: 2b00 cmp r3, #0 8002232: d023 beq.n 800227c { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8002234: 687b ldr r3, [r7, #4] 8002236: 6bdb ldr r3, [r3, #60] @ 0x3c 8002238: 6878 ldr r0, [r7, #4] 800223a: 4798 blx r3 800223c: e01e b.n 800227c } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 800223e: 687b ldr r3, [r7, #4] 8002240: 681b ldr r3, [r3, #0] 8002242: 681b ldr r3, [r3, #0] 8002244: f403 7380 and.w r3, r3, #256 @ 0x100 8002248: 2b00 cmp r3, #0 800224a: d10f bne.n 800226c { /* Disable the transfer complete interrupt */ hdma->Instance->CR &= ~(DMA_IT_TC); 800224c: 687b ldr r3, [r7, #4] 800224e: 681b ldr r3, [r3, #0] 8002250: 681a ldr r2, [r3, #0] 8002252: 687b ldr r3, [r7, #4] 8002254: 681b ldr r3, [r3, #0] 8002256: f022 0210 bic.w r2, r2, #16 800225a: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800225c: 687b ldr r3, [r7, #4] 800225e: 2201 movs r2, #1 8002260: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002264: 687b ldr r3, [r7, #4] 8002266: 2200 movs r2, #0 8002268: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800226c: 687b ldr r3, [r7, #4] 800226e: 6bdb ldr r3, [r3, #60] @ 0x3c 8002270: 2b00 cmp r3, #0 8002272: d003 beq.n 800227c { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8002274: 687b ldr r3, [r7, #4] 8002276: 6bdb ldr r3, [r3, #60] @ 0x3c 8002278: 6878 ldr r0, [r7, #4] 800227a: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 800227c: 687b ldr r3, [r7, #4] 800227e: 6d5b ldr r3, [r3, #84] @ 0x54 8002280: 2b00 cmp r3, #0 8002282: d032 beq.n 80022ea { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) 8002284: 687b ldr r3, [r7, #4] 8002286: 6d5b ldr r3, [r3, #84] @ 0x54 8002288: f003 0301 and.w r3, r3, #1 800228c: 2b00 cmp r3, #0 800228e: d022 beq.n 80022d6 { hdma->State = HAL_DMA_STATE_ABORT; 8002290: 687b ldr r3, [r7, #4] 8002292: 2205 movs r2, #5 8002294: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8002298: 687b ldr r3, [r7, #4] 800229a: 681b ldr r3, [r3, #0] 800229c: 681a ldr r2, [r3, #0] 800229e: 687b ldr r3, [r7, #4] 80022a0: 681b ldr r3, [r3, #0] 80022a2: f022 0201 bic.w r2, r2, #1 80022a6: 601a str r2, [r3, #0] do { if (++count > timeout) 80022a8: 68bb ldr r3, [r7, #8] 80022aa: 3301 adds r3, #1 80022ac: 60bb str r3, [r7, #8] 80022ae: 697a ldr r2, [r7, #20] 80022b0: 429a cmp r2, r3 80022b2: d307 bcc.n 80022c4 { break; } } while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); 80022b4: 687b ldr r3, [r7, #4] 80022b6: 681b ldr r3, [r3, #0] 80022b8: 681b ldr r3, [r3, #0] 80022ba: f003 0301 and.w r3, r3, #1 80022be: 2b00 cmp r3, #0 80022c0: d1f2 bne.n 80022a8 80022c2: e000 b.n 80022c6 break; 80022c4: bf00 nop /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80022c6: 687b ldr r3, [r7, #4] 80022c8: 2201 movs r2, #1 80022ca: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80022ce: 687b ldr r3, [r7, #4] 80022d0: 2200 movs r2, #0 80022d2: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 80022d6: 687b ldr r3, [r7, #4] 80022d8: 6cdb ldr r3, [r3, #76] @ 0x4c 80022da: 2b00 cmp r3, #0 80022dc: d005 beq.n 80022ea { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 80022de: 687b ldr r3, [r7, #4] 80022e0: 6cdb ldr r3, [r3, #76] @ 0x4c 80022e2: 6878 ldr r0, [r7, #4] 80022e4: 4798 blx r3 80022e6: e000 b.n 80022ea return; 80022e8: bf00 nop } } } 80022ea: 3718 adds r7, #24 80022ec: 46bd mov sp, r7 80022ee: bd80 pop {r7, pc} 080022f0 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 80022f0: b480 push {r7} 80022f2: b085 sub sp, #20 80022f4: af00 add r7, sp, #0 80022f6: 60f8 str r0, [r7, #12] 80022f8: 60b9 str r1, [r7, #8] 80022fa: 607a str r2, [r7, #4] 80022fc: 603b str r3, [r7, #0] /* Clear DBM bit */ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); 80022fe: 68fb ldr r3, [r7, #12] 8002300: 681b ldr r3, [r3, #0] 8002302: 681a ldr r2, [r3, #0] 8002304: 68fb ldr r3, [r7, #12] 8002306: 681b ldr r3, [r3, #0] 8002308: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800230c: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; 800230e: 68fb ldr r3, [r7, #12] 8002310: 681b ldr r3, [r3, #0] 8002312: 683a ldr r2, [r7, #0] 8002314: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8002316: 68fb ldr r3, [r7, #12] 8002318: 689b ldr r3, [r3, #8] 800231a: 2b40 cmp r3, #64 @ 0x40 800231c: d108 bne.n 8002330 { /* Configure DMA Stream destination address */ hdma->Instance->PAR = DstAddress; 800231e: 68fb ldr r3, [r7, #12] 8002320: 681b ldr r3, [r3, #0] 8002322: 687a ldr r2, [r7, #4] 8002324: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; 8002326: 68fb ldr r3, [r7, #12] 8002328: 681b ldr r3, [r3, #0] 800232a: 68ba ldr r2, [r7, #8] 800232c: 60da str r2, [r3, #12] hdma->Instance->PAR = SrcAddress; /* Configure DMA Stream destination address */ hdma->Instance->M0AR = DstAddress; } } 800232e: e007 b.n 8002340 hdma->Instance->PAR = SrcAddress; 8002330: 68fb ldr r3, [r7, #12] 8002332: 681b ldr r3, [r3, #0] 8002334: 68ba ldr r2, [r7, #8] 8002336: 609a str r2, [r3, #8] hdma->Instance->M0AR = DstAddress; 8002338: 68fb ldr r3, [r7, #12] 800233a: 681b ldr r3, [r3, #0] 800233c: 687a ldr r2, [r7, #4] 800233e: 60da str r2, [r3, #12] } 8002340: bf00 nop 8002342: 3714 adds r7, #20 8002344: 46bd mov sp, r7 8002346: f85d 7b04 ldr.w r7, [sp], #4 800234a: 4770 bx lr 0800234c : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 800234c: b480 push {r7} 800234e: b085 sub sp, #20 8002350: af00 add r7, sp, #0 8002352: 6078 str r0, [r7, #4] uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; 8002354: 687b ldr r3, [r7, #4] 8002356: 681b ldr r3, [r3, #0] 8002358: b2db uxtb r3, r3 800235a: 3b10 subs r3, #16 800235c: 4a14 ldr r2, [pc, #80] @ (80023b0 ) 800235e: fba2 2303 umull r2, r3, r2, r3 8002362: 091b lsrs r3, r3, #4 8002364: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number]; 8002366: 4a13 ldr r2, [pc, #76] @ (80023b4 ) 8002368: 68fb ldr r3, [r7, #12] 800236a: 4413 add r3, r2 800236c: 781b ldrb r3, [r3, #0] 800236e: 461a mov r2, r3 8002370: 687b ldr r3, [r7, #4] 8002372: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 8002374: 68fb ldr r3, [r7, #12] 8002376: 2b03 cmp r3, #3 8002378: d909 bls.n 800238e { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); 800237a: 687b ldr r3, [r7, #4] 800237c: 681b ldr r3, [r3, #0] 800237e: f423 737f bic.w r3, r3, #1020 @ 0x3fc 8002382: f023 0303 bic.w r3, r3, #3 8002386: 1d1a adds r2, r3, #4 8002388: 687b ldr r3, [r7, #4] 800238a: 659a str r2, [r3, #88] @ 0x58 800238c: e007 b.n 800239e } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); 800238e: 687b ldr r3, [r7, #4] 8002390: 681b ldr r3, [r3, #0] 8002392: f423 737f bic.w r3, r3, #1020 @ 0x3fc 8002396: f023 0303 bic.w r3, r3, #3 800239a: 687a ldr r2, [r7, #4] 800239c: 6593 str r3, [r2, #88] @ 0x58 } return hdma->StreamBaseAddress; 800239e: 687b ldr r3, [r7, #4] 80023a0: 6d9b ldr r3, [r3, #88] @ 0x58 } 80023a2: 4618 mov r0, r3 80023a4: 3714 adds r7, #20 80023a6: 46bd mov sp, r7 80023a8: f85d 7b04 ldr.w r7, [sp], #4 80023ac: 4770 bx lr 80023ae: bf00 nop 80023b0: aaaaaaab .word 0xaaaaaaab 80023b4: 0800aa18 .word 0x0800aa18 080023b8 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 80023b8: b480 push {r7} 80023ba: b085 sub sp, #20 80023bc: af00 add r7, sp, #0 80023be: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80023c0: 2300 movs r3, #0 80023c2: 73fb strb r3, [r7, #15] uint32_t tmp = hdma->Init.FIFOThreshold; 80023c4: 687b ldr r3, [r7, #4] 80023c6: 6a9b ldr r3, [r3, #40] @ 0x28 80023c8: 60bb str r3, [r7, #8] /* Memory Data size equal to Byte */ if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 80023ca: 687b ldr r3, [r7, #4] 80023cc: 699b ldr r3, [r3, #24] 80023ce: 2b00 cmp r3, #0 80023d0: d11f bne.n 8002412 { switch (tmp) 80023d2: 68bb ldr r3, [r7, #8] 80023d4: 2b03 cmp r3, #3 80023d6: d856 bhi.n 8002486 80023d8: a201 add r2, pc, #4 @ (adr r2, 80023e0 ) 80023da: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80023de: bf00 nop 80023e0: 080023f1 .word 0x080023f1 80023e4: 08002403 .word 0x08002403 80023e8: 080023f1 .word 0x080023f1 80023ec: 08002487 .word 0x08002487 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 80023f0: 687b ldr r3, [r7, #4] 80023f2: 6adb ldr r3, [r3, #44] @ 0x2c 80023f4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80023f8: 2b00 cmp r3, #0 80023fa: d046 beq.n 800248a { status = HAL_ERROR; 80023fc: 2301 movs r3, #1 80023fe: 73fb strb r3, [r7, #15] } break; 8002400: e043 b.n 800248a case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8002402: 687b ldr r3, [r7, #4] 8002404: 6adb ldr r3, [r3, #44] @ 0x2c 8002406: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800240a: d140 bne.n 800248e { status = HAL_ERROR; 800240c: 2301 movs r3, #1 800240e: 73fb strb r3, [r7, #15] } break; 8002410: e03d b.n 800248e break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 8002412: 687b ldr r3, [r7, #4] 8002414: 699b ldr r3, [r3, #24] 8002416: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800241a: d121 bne.n 8002460 { switch (tmp) 800241c: 68bb ldr r3, [r7, #8] 800241e: 2b03 cmp r3, #3 8002420: d837 bhi.n 8002492 8002422: a201 add r2, pc, #4 @ (adr r2, 8002428 ) 8002424: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002428: 08002439 .word 0x08002439 800242c: 0800243f .word 0x0800243f 8002430: 08002439 .word 0x08002439 8002434: 08002451 .word 0x08002451 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 8002438: 2301 movs r3, #1 800243a: 73fb strb r3, [r7, #15] break; 800243c: e030 b.n 80024a0 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800243e: 687b ldr r3, [r7, #4] 8002440: 6adb ldr r3, [r3, #44] @ 0x2c 8002442: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002446: 2b00 cmp r3, #0 8002448: d025 beq.n 8002496 { status = HAL_ERROR; 800244a: 2301 movs r3, #1 800244c: 73fb strb r3, [r7, #15] } break; 800244e: e022 b.n 8002496 case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8002450: 687b ldr r3, [r7, #4] 8002452: 6adb ldr r3, [r3, #44] @ 0x2c 8002454: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 8002458: d11f bne.n 800249a { status = HAL_ERROR; 800245a: 2301 movs r3, #1 800245c: 73fb strb r3, [r7, #15] } break; 800245e: e01c b.n 800249a } /* Memory Data size equal to Word */ else { switch (tmp) 8002460: 68bb ldr r3, [r7, #8] 8002462: 2b02 cmp r3, #2 8002464: d903 bls.n 800246e 8002466: 68bb ldr r3, [r7, #8] 8002468: 2b03 cmp r3, #3 800246a: d003 beq.n 8002474 { status = HAL_ERROR; } break; default: break; 800246c: e018 b.n 80024a0 status = HAL_ERROR; 800246e: 2301 movs r3, #1 8002470: 73fb strb r3, [r7, #15] break; 8002472: e015 b.n 80024a0 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002474: 687b ldr r3, [r7, #4] 8002476: 6adb ldr r3, [r3, #44] @ 0x2c 8002478: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800247c: 2b00 cmp r3, #0 800247e: d00e beq.n 800249e status = HAL_ERROR; 8002480: 2301 movs r3, #1 8002482: 73fb strb r3, [r7, #15] break; 8002484: e00b b.n 800249e break; 8002486: bf00 nop 8002488: e00a b.n 80024a0 break; 800248a: bf00 nop 800248c: e008 b.n 80024a0 break; 800248e: bf00 nop 8002490: e006 b.n 80024a0 break; 8002492: bf00 nop 8002494: e004 b.n 80024a0 break; 8002496: bf00 nop 8002498: e002 b.n 80024a0 break; 800249a: bf00 nop 800249c: e000 b.n 80024a0 break; 800249e: bf00 nop } } return status; 80024a0: 7bfb ldrb r3, [r7, #15] } 80024a2: 4618 mov r0, r3 80024a4: 3714 adds r7, #20 80024a6: 46bd mov sp, r7 80024a8: f85d 7b04 ldr.w r7, [sp], #4 80024ac: 4770 bx lr 80024ae: bf00 nop 080024b0 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80024b0: b480 push {r7} 80024b2: b089 sub sp, #36 @ 0x24 80024b4: af00 add r7, sp, #0 80024b6: 6078 str r0, [r7, #4] 80024b8: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 80024ba: 2300 movs r3, #0 80024bc: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 80024be: 2300 movs r3, #0 80024c0: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 80024c2: 2300 movs r3, #0 80024c4: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 80024c6: 2300 movs r3, #0 80024c8: 61fb str r3, [r7, #28] 80024ca: e165 b.n 8002798 { /* Get the IO position */ ioposition = 0x01U << position; 80024cc: 2201 movs r2, #1 80024ce: 69fb ldr r3, [r7, #28] 80024d0: fa02 f303 lsl.w r3, r2, r3 80024d4: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80024d6: 683b ldr r3, [r7, #0] 80024d8: 681b ldr r3, [r3, #0] 80024da: 697a ldr r2, [r7, #20] 80024dc: 4013 ands r3, r2 80024de: 613b str r3, [r7, #16] if(iocurrent == ioposition) 80024e0: 693a ldr r2, [r7, #16] 80024e2: 697b ldr r3, [r7, #20] 80024e4: 429a cmp r2, r3 80024e6: f040 8154 bne.w 8002792 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 80024ea: 683b ldr r3, [r7, #0] 80024ec: 685b ldr r3, [r3, #4] 80024ee: f003 0303 and.w r3, r3, #3 80024f2: 2b01 cmp r3, #1 80024f4: d005 beq.n 8002502 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80024f6: 683b ldr r3, [r7, #0] 80024f8: 685b ldr r3, [r3, #4] 80024fa: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 80024fe: 2b02 cmp r3, #2 8002500: d130 bne.n 8002564 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8002502: 687b ldr r3, [r7, #4] 8002504: 689b ldr r3, [r3, #8] 8002506: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8002508: 69fb ldr r3, [r7, #28] 800250a: 005b lsls r3, r3, #1 800250c: 2203 movs r2, #3 800250e: fa02 f303 lsl.w r3, r2, r3 8002512: 43db mvns r3, r3 8002514: 69ba ldr r2, [r7, #24] 8002516: 4013 ands r3, r2 8002518: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800251a: 683b ldr r3, [r7, #0] 800251c: 68da ldr r2, [r3, #12] 800251e: 69fb ldr r3, [r7, #28] 8002520: 005b lsls r3, r3, #1 8002522: fa02 f303 lsl.w r3, r2, r3 8002526: 69ba ldr r2, [r7, #24] 8002528: 4313 orrs r3, r2 800252a: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800252c: 687b ldr r3, [r7, #4] 800252e: 69ba ldr r2, [r7, #24] 8002530: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8002532: 687b ldr r3, [r7, #4] 8002534: 685b ldr r3, [r3, #4] 8002536: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8002538: 2201 movs r2, #1 800253a: 69fb ldr r3, [r7, #28] 800253c: fa02 f303 lsl.w r3, r2, r3 8002540: 43db mvns r3, r3 8002542: 69ba ldr r2, [r7, #24] 8002544: 4013 ands r3, r2 8002546: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8002548: 683b ldr r3, [r7, #0] 800254a: 685b ldr r3, [r3, #4] 800254c: 091b lsrs r3, r3, #4 800254e: f003 0201 and.w r2, r3, #1 8002552: 69fb ldr r3, [r7, #28] 8002554: fa02 f303 lsl.w r3, r2, r3 8002558: 69ba ldr r2, [r7, #24] 800255a: 4313 orrs r3, r2 800255c: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 800255e: 687b ldr r3, [r7, #4] 8002560: 69ba ldr r2, [r7, #24] 8002562: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8002564: 683b ldr r3, [r7, #0] 8002566: 685b ldr r3, [r3, #4] 8002568: f003 0303 and.w r3, r3, #3 800256c: 2b03 cmp r3, #3 800256e: d017 beq.n 80025a0 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8002570: 687b ldr r3, [r7, #4] 8002572: 68db ldr r3, [r3, #12] 8002574: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8002576: 69fb ldr r3, [r7, #28] 8002578: 005b lsls r3, r3, #1 800257a: 2203 movs r2, #3 800257c: fa02 f303 lsl.w r3, r2, r3 8002580: 43db mvns r3, r3 8002582: 69ba ldr r2, [r7, #24] 8002584: 4013 ands r3, r2 8002586: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8002588: 683b ldr r3, [r7, #0] 800258a: 689a ldr r2, [r3, #8] 800258c: 69fb ldr r3, [r7, #28] 800258e: 005b lsls r3, r3, #1 8002590: fa02 f303 lsl.w r3, r2, r3 8002594: 69ba ldr r2, [r7, #24] 8002596: 4313 orrs r3, r2 8002598: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 800259a: 687b ldr r3, [r7, #4] 800259c: 69ba ldr r2, [r7, #24] 800259e: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80025a0: 683b ldr r3, [r7, #0] 80025a2: 685b ldr r3, [r3, #4] 80025a4: f003 0303 and.w r3, r3, #3 80025a8: 2b02 cmp r3, #2 80025aa: d123 bne.n 80025f4 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 80025ac: 69fb ldr r3, [r7, #28] 80025ae: 08da lsrs r2, r3, #3 80025b0: 687b ldr r3, [r7, #4] 80025b2: 3208 adds r2, #8 80025b4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80025b8: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 80025ba: 69fb ldr r3, [r7, #28] 80025bc: f003 0307 and.w r3, r3, #7 80025c0: 009b lsls r3, r3, #2 80025c2: 220f movs r2, #15 80025c4: fa02 f303 lsl.w r3, r2, r3 80025c8: 43db mvns r3, r3 80025ca: 69ba ldr r2, [r7, #24] 80025cc: 4013 ands r3, r2 80025ce: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 80025d0: 683b ldr r3, [r7, #0] 80025d2: 691a ldr r2, [r3, #16] 80025d4: 69fb ldr r3, [r7, #28] 80025d6: f003 0307 and.w r3, r3, #7 80025da: 009b lsls r3, r3, #2 80025dc: fa02 f303 lsl.w r3, r2, r3 80025e0: 69ba ldr r2, [r7, #24] 80025e2: 4313 orrs r3, r2 80025e4: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 80025e6: 69fb ldr r3, [r7, #28] 80025e8: 08da lsrs r2, r3, #3 80025ea: 687b ldr r3, [r7, #4] 80025ec: 3208 adds r2, #8 80025ee: 69b9 ldr r1, [r7, #24] 80025f0: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 80025f4: 687b ldr r3, [r7, #4] 80025f6: 681b ldr r3, [r3, #0] 80025f8: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 80025fa: 69fb ldr r3, [r7, #28] 80025fc: 005b lsls r3, r3, #1 80025fe: 2203 movs r2, #3 8002600: fa02 f303 lsl.w r3, r2, r3 8002604: 43db mvns r3, r3 8002606: 69ba ldr r2, [r7, #24] 8002608: 4013 ands r3, r2 800260a: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800260c: 683b ldr r3, [r7, #0] 800260e: 685b ldr r3, [r3, #4] 8002610: f003 0203 and.w r2, r3, #3 8002614: 69fb ldr r3, [r7, #28] 8002616: 005b lsls r3, r3, #1 8002618: fa02 f303 lsl.w r3, r2, r3 800261c: 69ba ldr r2, [r7, #24] 800261e: 4313 orrs r3, r2 8002620: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8002622: 687b ldr r3, [r7, #4] 8002624: 69ba ldr r2, [r7, #24] 8002626: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8002628: 683b ldr r3, [r7, #0] 800262a: 685b ldr r3, [r3, #4] 800262c: f403 3340 and.w r3, r3, #196608 @ 0x30000 8002630: 2b00 cmp r3, #0 8002632: f000 80ae beq.w 8002792 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002636: 2300 movs r3, #0 8002638: 60fb str r3, [r7, #12] 800263a: 4b5d ldr r3, [pc, #372] @ (80027b0 ) 800263c: 6c5b ldr r3, [r3, #68] @ 0x44 800263e: 4a5c ldr r2, [pc, #368] @ (80027b0 ) 8002640: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002644: 6453 str r3, [r2, #68] @ 0x44 8002646: 4b5a ldr r3, [pc, #360] @ (80027b0 ) 8002648: 6c5b ldr r3, [r3, #68] @ 0x44 800264a: f403 4380 and.w r3, r3, #16384 @ 0x4000 800264e: 60fb str r3, [r7, #12] 8002650: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8002652: 4a58 ldr r2, [pc, #352] @ (80027b4 ) 8002654: 69fb ldr r3, [r7, #28] 8002656: 089b lsrs r3, r3, #2 8002658: 3302 adds r3, #2 800265a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800265e: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8002660: 69fb ldr r3, [r7, #28] 8002662: f003 0303 and.w r3, r3, #3 8002666: 009b lsls r3, r3, #2 8002668: 220f movs r2, #15 800266a: fa02 f303 lsl.w r3, r2, r3 800266e: 43db mvns r3, r3 8002670: 69ba ldr r2, [r7, #24] 8002672: 4013 ands r3, r2 8002674: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8002676: 687b ldr r3, [r7, #4] 8002678: 4a4f ldr r2, [pc, #316] @ (80027b8 ) 800267a: 4293 cmp r3, r2 800267c: d025 beq.n 80026ca 800267e: 687b ldr r3, [r7, #4] 8002680: 4a4e ldr r2, [pc, #312] @ (80027bc ) 8002682: 4293 cmp r3, r2 8002684: d01f beq.n 80026c6 8002686: 687b ldr r3, [r7, #4] 8002688: 4a4d ldr r2, [pc, #308] @ (80027c0 ) 800268a: 4293 cmp r3, r2 800268c: d019 beq.n 80026c2 800268e: 687b ldr r3, [r7, #4] 8002690: 4a4c ldr r2, [pc, #304] @ (80027c4 ) 8002692: 4293 cmp r3, r2 8002694: d013 beq.n 80026be 8002696: 687b ldr r3, [r7, #4] 8002698: 4a4b ldr r2, [pc, #300] @ (80027c8 ) 800269a: 4293 cmp r3, r2 800269c: d00d beq.n 80026ba 800269e: 687b ldr r3, [r7, #4] 80026a0: 4a4a ldr r2, [pc, #296] @ (80027cc ) 80026a2: 4293 cmp r3, r2 80026a4: d007 beq.n 80026b6 80026a6: 687b ldr r3, [r7, #4] 80026a8: 4a49 ldr r2, [pc, #292] @ (80027d0 ) 80026aa: 4293 cmp r3, r2 80026ac: d101 bne.n 80026b2 80026ae: 2306 movs r3, #6 80026b0: e00c b.n 80026cc 80026b2: 2307 movs r3, #7 80026b4: e00a b.n 80026cc 80026b6: 2305 movs r3, #5 80026b8: e008 b.n 80026cc 80026ba: 2304 movs r3, #4 80026bc: e006 b.n 80026cc 80026be: 2303 movs r3, #3 80026c0: e004 b.n 80026cc 80026c2: 2302 movs r3, #2 80026c4: e002 b.n 80026cc 80026c6: 2301 movs r3, #1 80026c8: e000 b.n 80026cc 80026ca: 2300 movs r3, #0 80026cc: 69fa ldr r2, [r7, #28] 80026ce: f002 0203 and.w r2, r2, #3 80026d2: 0092 lsls r2, r2, #2 80026d4: 4093 lsls r3, r2 80026d6: 69ba ldr r2, [r7, #24] 80026d8: 4313 orrs r3, r2 80026da: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 80026dc: 4935 ldr r1, [pc, #212] @ (80027b4 ) 80026de: 69fb ldr r3, [r7, #28] 80026e0: 089b lsrs r3, r3, #2 80026e2: 3302 adds r3, #2 80026e4: 69ba ldr r2, [r7, #24] 80026e6: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 80026ea: 4b3a ldr r3, [pc, #232] @ (80027d4 ) 80026ec: 689b ldr r3, [r3, #8] 80026ee: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 80026f0: 693b ldr r3, [r7, #16] 80026f2: 43db mvns r3, r3 80026f4: 69ba ldr r2, [r7, #24] 80026f6: 4013 ands r3, r2 80026f8: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 80026fa: 683b ldr r3, [r7, #0] 80026fc: 685b ldr r3, [r3, #4] 80026fe: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8002702: 2b00 cmp r3, #0 8002704: d003 beq.n 800270e { temp |= iocurrent; 8002706: 69ba ldr r2, [r7, #24] 8002708: 693b ldr r3, [r7, #16] 800270a: 4313 orrs r3, r2 800270c: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 800270e: 4a31 ldr r2, [pc, #196] @ (80027d4 ) 8002710: 69bb ldr r3, [r7, #24] 8002712: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8002714: 4b2f ldr r3, [pc, #188] @ (80027d4 ) 8002716: 68db ldr r3, [r3, #12] 8002718: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 800271a: 693b ldr r3, [r7, #16] 800271c: 43db mvns r3, r3 800271e: 69ba ldr r2, [r7, #24] 8002720: 4013 ands r3, r2 8002722: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8002724: 683b ldr r3, [r7, #0] 8002726: 685b ldr r3, [r3, #4] 8002728: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800272c: 2b00 cmp r3, #0 800272e: d003 beq.n 8002738 { temp |= iocurrent; 8002730: 69ba ldr r2, [r7, #24] 8002732: 693b ldr r3, [r7, #16] 8002734: 4313 orrs r3, r2 8002736: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8002738: 4a26 ldr r2, [pc, #152] @ (80027d4 ) 800273a: 69bb ldr r3, [r7, #24] 800273c: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 800273e: 4b25 ldr r3, [pc, #148] @ (80027d4 ) 8002740: 685b ldr r3, [r3, #4] 8002742: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002744: 693b ldr r3, [r7, #16] 8002746: 43db mvns r3, r3 8002748: 69ba ldr r2, [r7, #24] 800274a: 4013 ands r3, r2 800274c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800274e: 683b ldr r3, [r7, #0] 8002750: 685b ldr r3, [r3, #4] 8002752: f403 3300 and.w r3, r3, #131072 @ 0x20000 8002756: 2b00 cmp r3, #0 8002758: d003 beq.n 8002762 { temp |= iocurrent; 800275a: 69ba ldr r2, [r7, #24] 800275c: 693b ldr r3, [r7, #16] 800275e: 4313 orrs r3, r2 8002760: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 8002762: 4a1c ldr r2, [pc, #112] @ (80027d4 ) 8002764: 69bb ldr r3, [r7, #24] 8002766: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8002768: 4b1a ldr r3, [pc, #104] @ (80027d4 ) 800276a: 681b ldr r3, [r3, #0] 800276c: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 800276e: 693b ldr r3, [r7, #16] 8002770: 43db mvns r3, r3 8002772: 69ba ldr r2, [r7, #24] 8002774: 4013 ands r3, r2 8002776: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8002778: 683b ldr r3, [r7, #0] 800277a: 685b ldr r3, [r3, #4] 800277c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8002780: 2b00 cmp r3, #0 8002782: d003 beq.n 800278c { temp |= iocurrent; 8002784: 69ba ldr r2, [r7, #24] 8002786: 693b ldr r3, [r7, #16] 8002788: 4313 orrs r3, r2 800278a: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 800278c: 4a11 ldr r2, [pc, #68] @ (80027d4 ) 800278e: 69bb ldr r3, [r7, #24] 8002790: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 8002792: 69fb ldr r3, [r7, #28] 8002794: 3301 adds r3, #1 8002796: 61fb str r3, [r7, #28] 8002798: 69fb ldr r3, [r7, #28] 800279a: 2b0f cmp r3, #15 800279c: f67f ae96 bls.w 80024cc } } } } 80027a0: bf00 nop 80027a2: bf00 nop 80027a4: 3724 adds r7, #36 @ 0x24 80027a6: 46bd mov sp, r7 80027a8: f85d 7b04 ldr.w r7, [sp], #4 80027ac: 4770 bx lr 80027ae: bf00 nop 80027b0: 40023800 .word 0x40023800 80027b4: 40013800 .word 0x40013800 80027b8: 40020000 .word 0x40020000 80027bc: 40020400 .word 0x40020400 80027c0: 40020800 .word 0x40020800 80027c4: 40020c00 .word 0x40020c00 80027c8: 40021000 .word 0x40021000 80027cc: 40021400 .word 0x40021400 80027d0: 40021800 .word 0x40021800 80027d4: 40013c00 .word 0x40013c00 080027d8 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 80027d8: b480 push {r7} 80027da: b085 sub sp, #20 80027dc: af00 add r7, sp, #0 80027de: 6078 str r0, [r7, #4] 80027e0: 460b mov r3, r1 80027e2: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 80027e4: 687b ldr r3, [r7, #4] 80027e6: 691a ldr r2, [r3, #16] 80027e8: 887b ldrh r3, [r7, #2] 80027ea: 4013 ands r3, r2 80027ec: 2b00 cmp r3, #0 80027ee: d002 beq.n 80027f6 { bitstatus = GPIO_PIN_SET; 80027f0: 2301 movs r3, #1 80027f2: 73fb strb r3, [r7, #15] 80027f4: e001 b.n 80027fa } else { bitstatus = GPIO_PIN_RESET; 80027f6: 2300 movs r3, #0 80027f8: 73fb strb r3, [r7, #15] } return bitstatus; 80027fa: 7bfb ldrb r3, [r7, #15] } 80027fc: 4618 mov r0, r3 80027fe: 3714 adds r7, #20 8002800: 46bd mov sp, r7 8002802: f85d 7b04 ldr.w r7, [sp], #4 8002806: 4770 bx lr 08002808 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8002808: b480 push {r7} 800280a: b083 sub sp, #12 800280c: af00 add r7, sp, #0 800280e: 6078 str r0, [r7, #4] 8002810: 460b mov r3, r1 8002812: 807b strh r3, [r7, #2] 8002814: 4613 mov r3, r2 8002816: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8002818: 787b ldrb r3, [r7, #1] 800281a: 2b00 cmp r3, #0 800281c: d003 beq.n 8002826 { GPIOx->BSRR = GPIO_Pin; 800281e: 887a ldrh r2, [r7, #2] 8002820: 687b ldr r3, [r7, #4] 8002822: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8002824: e003 b.n 800282e GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8002826: 887b ldrh r3, [r7, #2] 8002828: 041a lsls r2, r3, #16 800282a: 687b ldr r3, [r7, #4] 800282c: 619a str r2, [r3, #24] } 800282e: bf00 nop 8002830: 370c adds r7, #12 8002832: 46bd mov sp, r7 8002834: f85d 7b04 ldr.w r7, [sp], #4 8002838: 4770 bx lr ... 0800283c : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 800283c: b580 push {r7, lr} 800283e: b084 sub sp, #16 8002840: af00 add r7, sp, #0 8002842: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8002844: 687b ldr r3, [r7, #4] 8002846: 2b00 cmp r3, #0 8002848: d101 bne.n 800284e { return HAL_ERROR; 800284a: 2301 movs r3, #1 800284c: e12b b.n 8002aa6 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 800284e: 687b ldr r3, [r7, #4] 8002850: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8002854: b2db uxtb r3, r3 8002856: 2b00 cmp r3, #0 8002858: d106 bne.n 8002868 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 800285a: 687b ldr r3, [r7, #4] 800285c: 2200 movs r2, #0 800285e: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8002862: 6878 ldr r0, [r7, #4] 8002864: f7fd ff98 bl 8000798 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8002868: 687b ldr r3, [r7, #4] 800286a: 2224 movs r2, #36 @ 0x24 800286c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8002870: 687b ldr r3, [r7, #4] 8002872: 681b ldr r3, [r3, #0] 8002874: 681a ldr r2, [r3, #0] 8002876: 687b ldr r3, [r7, #4] 8002878: 681b ldr r3, [r3, #0] 800287a: f022 0201 bic.w r2, r2, #1 800287e: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8002880: 687b ldr r3, [r7, #4] 8002882: 681b ldr r3, [r3, #0] 8002884: 681a ldr r2, [r3, #0] 8002886: 687b ldr r3, [r7, #4] 8002888: 681b ldr r3, [r3, #0] 800288a: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800288e: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 8002890: 687b ldr r3, [r7, #4] 8002892: 681b ldr r3, [r3, #0] 8002894: 681a ldr r2, [r3, #0] 8002896: 687b ldr r3, [r7, #4] 8002898: 681b ldr r3, [r3, #0] 800289a: f422 4200 bic.w r2, r2, #32768 @ 0x8000 800289e: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 80028a0: f001 fc88 bl 80041b4 80028a4: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 80028a6: 687b ldr r3, [r7, #4] 80028a8: 685b ldr r3, [r3, #4] 80028aa: 4a81 ldr r2, [pc, #516] @ (8002ab0 ) 80028ac: 4293 cmp r3, r2 80028ae: d807 bhi.n 80028c0 80028b0: 68fb ldr r3, [r7, #12] 80028b2: 4a80 ldr r2, [pc, #512] @ (8002ab4 ) 80028b4: 4293 cmp r3, r2 80028b6: bf94 ite ls 80028b8: 2301 movls r3, #1 80028ba: 2300 movhi r3, #0 80028bc: b2db uxtb r3, r3 80028be: e006 b.n 80028ce 80028c0: 68fb ldr r3, [r7, #12] 80028c2: 4a7d ldr r2, [pc, #500] @ (8002ab8 ) 80028c4: 4293 cmp r3, r2 80028c6: bf94 ite ls 80028c8: 2301 movls r3, #1 80028ca: 2300 movhi r3, #0 80028cc: b2db uxtb r3, r3 80028ce: 2b00 cmp r3, #0 80028d0: d001 beq.n 80028d6 { return HAL_ERROR; 80028d2: 2301 movs r3, #1 80028d4: e0e7 b.n 8002aa6 } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 80028d6: 68fb ldr r3, [r7, #12] 80028d8: 4a78 ldr r2, [pc, #480] @ (8002abc ) 80028da: fba2 2303 umull r2, r3, r2, r3 80028de: 0c9b lsrs r3, r3, #18 80028e0: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 80028e2: 687b ldr r3, [r7, #4] 80028e4: 681b ldr r3, [r3, #0] 80028e6: 685b ldr r3, [r3, #4] 80028e8: f023 013f bic.w r1, r3, #63 @ 0x3f 80028ec: 687b ldr r3, [r7, #4] 80028ee: 681b ldr r3, [r3, #0] 80028f0: 68ba ldr r2, [r7, #8] 80028f2: 430a orrs r2, r1 80028f4: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 80028f6: 687b ldr r3, [r7, #4] 80028f8: 681b ldr r3, [r3, #0] 80028fa: 6a1b ldr r3, [r3, #32] 80028fc: f023 013f bic.w r1, r3, #63 @ 0x3f 8002900: 687b ldr r3, [r7, #4] 8002902: 685b ldr r3, [r3, #4] 8002904: 4a6a ldr r2, [pc, #424] @ (8002ab0 ) 8002906: 4293 cmp r3, r2 8002908: d802 bhi.n 8002910 800290a: 68bb ldr r3, [r7, #8] 800290c: 3301 adds r3, #1 800290e: e009 b.n 8002924 8002910: 68bb ldr r3, [r7, #8] 8002912: f44f 7296 mov.w r2, #300 @ 0x12c 8002916: fb02 f303 mul.w r3, r2, r3 800291a: 4a69 ldr r2, [pc, #420] @ (8002ac0 ) 800291c: fba2 2303 umull r2, r3, r2, r3 8002920: 099b lsrs r3, r3, #6 8002922: 3301 adds r3, #1 8002924: 687a ldr r2, [r7, #4] 8002926: 6812 ldr r2, [r2, #0] 8002928: 430b orrs r3, r1 800292a: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 800292c: 687b ldr r3, [r7, #4] 800292e: 681b ldr r3, [r3, #0] 8002930: 69db ldr r3, [r3, #28] 8002932: f423 424f bic.w r2, r3, #52992 @ 0xcf00 8002936: f022 02ff bic.w r2, r2, #255 @ 0xff 800293a: 687b ldr r3, [r7, #4] 800293c: 685b ldr r3, [r3, #4] 800293e: 495c ldr r1, [pc, #368] @ (8002ab0 ) 8002940: 428b cmp r3, r1 8002942: d819 bhi.n 8002978 8002944: 68fb ldr r3, [r7, #12] 8002946: 1e59 subs r1, r3, #1 8002948: 687b ldr r3, [r7, #4] 800294a: 685b ldr r3, [r3, #4] 800294c: 005b lsls r3, r3, #1 800294e: fbb1 f3f3 udiv r3, r1, r3 8002952: 1c59 adds r1, r3, #1 8002954: f640 73fc movw r3, #4092 @ 0xffc 8002958: 400b ands r3, r1 800295a: 2b00 cmp r3, #0 800295c: d00a beq.n 8002974 800295e: 68fb ldr r3, [r7, #12] 8002960: 1e59 subs r1, r3, #1 8002962: 687b ldr r3, [r7, #4] 8002964: 685b ldr r3, [r3, #4] 8002966: 005b lsls r3, r3, #1 8002968: fbb1 f3f3 udiv r3, r1, r3 800296c: 3301 adds r3, #1 800296e: f3c3 030b ubfx r3, r3, #0, #12 8002972: e051 b.n 8002a18 8002974: 2304 movs r3, #4 8002976: e04f b.n 8002a18 8002978: 687b ldr r3, [r7, #4] 800297a: 689b ldr r3, [r3, #8] 800297c: 2b00 cmp r3, #0 800297e: d111 bne.n 80029a4 8002980: 68fb ldr r3, [r7, #12] 8002982: 1e58 subs r0, r3, #1 8002984: 687b ldr r3, [r7, #4] 8002986: 6859 ldr r1, [r3, #4] 8002988: 460b mov r3, r1 800298a: 005b lsls r3, r3, #1 800298c: 440b add r3, r1 800298e: fbb0 f3f3 udiv r3, r0, r3 8002992: 3301 adds r3, #1 8002994: f3c3 030b ubfx r3, r3, #0, #12 8002998: 2b00 cmp r3, #0 800299a: bf0c ite eq 800299c: 2301 moveq r3, #1 800299e: 2300 movne r3, #0 80029a0: b2db uxtb r3, r3 80029a2: e012 b.n 80029ca 80029a4: 68fb ldr r3, [r7, #12] 80029a6: 1e58 subs r0, r3, #1 80029a8: 687b ldr r3, [r7, #4] 80029aa: 6859 ldr r1, [r3, #4] 80029ac: 460b mov r3, r1 80029ae: 009b lsls r3, r3, #2 80029b0: 440b add r3, r1 80029b2: 0099 lsls r1, r3, #2 80029b4: 440b add r3, r1 80029b6: fbb0 f3f3 udiv r3, r0, r3 80029ba: 3301 adds r3, #1 80029bc: f3c3 030b ubfx r3, r3, #0, #12 80029c0: 2b00 cmp r3, #0 80029c2: bf0c ite eq 80029c4: 2301 moveq r3, #1 80029c6: 2300 movne r3, #0 80029c8: b2db uxtb r3, r3 80029ca: 2b00 cmp r3, #0 80029cc: d001 beq.n 80029d2 80029ce: 2301 movs r3, #1 80029d0: e022 b.n 8002a18 80029d2: 687b ldr r3, [r7, #4] 80029d4: 689b ldr r3, [r3, #8] 80029d6: 2b00 cmp r3, #0 80029d8: d10e bne.n 80029f8 80029da: 68fb ldr r3, [r7, #12] 80029dc: 1e58 subs r0, r3, #1 80029de: 687b ldr r3, [r7, #4] 80029e0: 6859 ldr r1, [r3, #4] 80029e2: 460b mov r3, r1 80029e4: 005b lsls r3, r3, #1 80029e6: 440b add r3, r1 80029e8: fbb0 f3f3 udiv r3, r0, r3 80029ec: 3301 adds r3, #1 80029ee: f3c3 030b ubfx r3, r3, #0, #12 80029f2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80029f6: e00f b.n 8002a18 80029f8: 68fb ldr r3, [r7, #12] 80029fa: 1e58 subs r0, r3, #1 80029fc: 687b ldr r3, [r7, #4] 80029fe: 6859 ldr r1, [r3, #4] 8002a00: 460b mov r3, r1 8002a02: 009b lsls r3, r3, #2 8002a04: 440b add r3, r1 8002a06: 0099 lsls r1, r3, #2 8002a08: 440b add r3, r1 8002a0a: fbb0 f3f3 udiv r3, r0, r3 8002a0e: 3301 adds r3, #1 8002a10: f3c3 030b ubfx r3, r3, #0, #12 8002a14: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8002a18: 6879 ldr r1, [r7, #4] 8002a1a: 6809 ldr r1, [r1, #0] 8002a1c: 4313 orrs r3, r2 8002a1e: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8002a20: 687b ldr r3, [r7, #4] 8002a22: 681b ldr r3, [r3, #0] 8002a24: 681b ldr r3, [r3, #0] 8002a26: f023 01c0 bic.w r1, r3, #192 @ 0xc0 8002a2a: 687b ldr r3, [r7, #4] 8002a2c: 69da ldr r2, [r3, #28] 8002a2e: 687b ldr r3, [r7, #4] 8002a30: 6a1b ldr r3, [r3, #32] 8002a32: 431a orrs r2, r3 8002a34: 687b ldr r3, [r7, #4] 8002a36: 681b ldr r3, [r3, #0] 8002a38: 430a orrs r2, r1 8002a3a: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 8002a3c: 687b ldr r3, [r7, #4] 8002a3e: 681b ldr r3, [r3, #0] 8002a40: 689b ldr r3, [r3, #8] 8002a42: f423 4303 bic.w r3, r3, #33536 @ 0x8300 8002a46: f023 03ff bic.w r3, r3, #255 @ 0xff 8002a4a: 687a ldr r2, [r7, #4] 8002a4c: 6911 ldr r1, [r2, #16] 8002a4e: 687a ldr r2, [r7, #4] 8002a50: 68d2 ldr r2, [r2, #12] 8002a52: 4311 orrs r1, r2 8002a54: 687a ldr r2, [r7, #4] 8002a56: 6812 ldr r2, [r2, #0] 8002a58: 430b orrs r3, r1 8002a5a: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 8002a5c: 687b ldr r3, [r7, #4] 8002a5e: 681b ldr r3, [r3, #0] 8002a60: 68db ldr r3, [r3, #12] 8002a62: f023 01ff bic.w r1, r3, #255 @ 0xff 8002a66: 687b ldr r3, [r7, #4] 8002a68: 695a ldr r2, [r3, #20] 8002a6a: 687b ldr r3, [r7, #4] 8002a6c: 699b ldr r3, [r3, #24] 8002a6e: 431a orrs r2, r3 8002a70: 687b ldr r3, [r7, #4] 8002a72: 681b ldr r3, [r3, #0] 8002a74: 430a orrs r2, r1 8002a76: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002a78: 687b ldr r3, [r7, #4] 8002a7a: 681b ldr r3, [r3, #0] 8002a7c: 681a ldr r2, [r3, #0] 8002a7e: 687b ldr r3, [r7, #4] 8002a80: 681b ldr r3, [r3, #0] 8002a82: f042 0201 orr.w r2, r2, #1 8002a86: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002a88: 687b ldr r3, [r7, #4] 8002a8a: 2200 movs r2, #0 8002a8c: 641a str r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_READY; 8002a8e: 687b ldr r3, [r7, #4] 8002a90: 2220 movs r2, #32 8002a92: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->PreviousState = I2C_STATE_NONE; 8002a96: 687b ldr r3, [r7, #4] 8002a98: 2200 movs r2, #0 8002a9a: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8002a9c: 687b ldr r3, [r7, #4] 8002a9e: 2200 movs r2, #0 8002aa0: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 8002aa4: 2300 movs r3, #0 } 8002aa6: 4618 mov r0, r3 8002aa8: 3710 adds r7, #16 8002aaa: 46bd mov sp, r7 8002aac: bd80 pop {r7, pc} 8002aae: bf00 nop 8002ab0: 000186a0 .word 0x000186a0 8002ab4: 001e847f .word 0x001e847f 8002ab8: 003d08ff .word 0x003d08ff 8002abc: 431bde83 .word 0x431bde83 8002ac0: 10624dd3 .word 0x10624dd3 08002ac4 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8002ac4: b580 push {r7, lr} 8002ac6: b086 sub sp, #24 8002ac8: af02 add r7, sp, #8 8002aca: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx; #endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8002acc: 687b ldr r3, [r7, #4] 8002ace: 2b00 cmp r3, #0 8002ad0: d101 bne.n 8002ad6 { return HAL_ERROR; 8002ad2: 2301 movs r3, #1 8002ad4: e108 b.n 8002ce8 /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); #if defined (USB_OTG_FS) USBx = hpcd->Instance; 8002ad6: 687b ldr r3, [r7, #4] 8002ad8: 681b ldr r3, [r3, #0] 8002ada: 60bb str r3, [r7, #8] #endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) 8002adc: 687b ldr r3, [r7, #4] 8002ade: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495 8002ae2: b2db uxtb r3, r3 8002ae4: 2b00 cmp r3, #0 8002ae6: d106 bne.n 8002af6 { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 8002ae8: 687b ldr r3, [r7, #4] 8002aea: 2200 movs r2, #0 8002aec: f883 2494 strb.w r2, [r3, #1172] @ 0x494 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8002af0: 6878 ldr r0, [r7, #4] 8002af2: f007 fbbb bl 800a26c #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8002af6: 687b ldr r3, [r7, #4] 8002af8: 2203 movs r2, #3 8002afa: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ if (USBx == USB_OTG_FS) 8002afe: 68bb ldr r3, [r7, #8] 8002b00: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002b04: d102 bne.n 8002b0c { hpcd->Init.dma_enable = 0U; 8002b06: 687b ldr r3, [r7, #4] 8002b08: 2200 movs r2, #0 8002b0a: 719a strb r2, [r3, #6] } #endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8002b0c: 687b ldr r3, [r7, #4] 8002b0e: 681b ldr r3, [r3, #0] 8002b10: 4618 mov r0, r3 8002b12: f004 fab0 bl 8007076 /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002b16: 687b ldr r3, [r7, #4] 8002b18: 6818 ldr r0, [r3, #0] 8002b1a: 687b ldr r3, [r7, #4] 8002b1c: 7c1a ldrb r2, [r3, #16] 8002b1e: f88d 2000 strb.w r2, [sp] 8002b22: 3304 adds r3, #4 8002b24: cb0e ldmia r3, {r1, r2, r3} 8002b26: f004 f98f bl 8006e48 8002b2a: 4603 mov r3, r0 8002b2c: 2b00 cmp r3, #0 8002b2e: d005 beq.n 8002b3c { hpcd->State = HAL_PCD_STATE_ERROR; 8002b30: 687b ldr r3, [r7, #4] 8002b32: 2202 movs r2, #2 8002b34: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002b38: 2301 movs r3, #1 8002b3a: e0d5 b.n 8002ce8 } /* Force Device Mode */ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) 8002b3c: 687b ldr r3, [r7, #4] 8002b3e: 681b ldr r3, [r3, #0] 8002b40: 2100 movs r1, #0 8002b42: 4618 mov r0, r3 8002b44: f004 faa8 bl 8007098 8002b48: 4603 mov r3, r0 8002b4a: 2b00 cmp r3, #0 8002b4c: d005 beq.n 8002b5a { hpcd->State = HAL_PCD_STATE_ERROR; 8002b4e: 687b ldr r3, [r7, #4] 8002b50: 2202 movs r2, #2 8002b52: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002b56: 2301 movs r3, #1 8002b58: e0c6 b.n 8002ce8 } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002b5a: 2300 movs r3, #0 8002b5c: 73fb strb r3, [r7, #15] 8002b5e: e04a b.n 8002bf6 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8002b60: 7bfa ldrb r2, [r7, #15] 8002b62: 6879 ldr r1, [r7, #4] 8002b64: 4613 mov r3, r2 8002b66: 00db lsls r3, r3, #3 8002b68: 4413 add r3, r2 8002b6a: 009b lsls r3, r3, #2 8002b6c: 440b add r3, r1 8002b6e: 3315 adds r3, #21 8002b70: 2201 movs r2, #1 8002b72: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8002b74: 7bfa ldrb r2, [r7, #15] 8002b76: 6879 ldr r1, [r7, #4] 8002b78: 4613 mov r3, r2 8002b7a: 00db lsls r3, r3, #3 8002b7c: 4413 add r3, r2 8002b7e: 009b lsls r3, r3, #2 8002b80: 440b add r3, r1 8002b82: 3314 adds r3, #20 8002b84: 7bfa ldrb r2, [r7, #15] 8002b86: 701a strb r2, [r3, #0] hpcd->IN_ep[i].tx_fifo_num = i; 8002b88: 7bfa ldrb r2, [r7, #15] 8002b8a: 7bfb ldrb r3, [r7, #15] 8002b8c: b298 uxth r0, r3 8002b8e: 6879 ldr r1, [r7, #4] 8002b90: 4613 mov r3, r2 8002b92: 00db lsls r3, r3, #3 8002b94: 4413 add r3, r2 8002b96: 009b lsls r3, r3, #2 8002b98: 440b add r3, r1 8002b9a: 332e adds r3, #46 @ 0x2e 8002b9c: 4602 mov r2, r0 8002b9e: 801a strh r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 8002ba0: 7bfa ldrb r2, [r7, #15] 8002ba2: 6879 ldr r1, [r7, #4] 8002ba4: 4613 mov r3, r2 8002ba6: 00db lsls r3, r3, #3 8002ba8: 4413 add r3, r2 8002baa: 009b lsls r3, r3, #2 8002bac: 440b add r3, r1 8002bae: 3318 adds r3, #24 8002bb0: 2200 movs r2, #0 8002bb2: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8002bb4: 7bfa ldrb r2, [r7, #15] 8002bb6: 6879 ldr r1, [r7, #4] 8002bb8: 4613 mov r3, r2 8002bba: 00db lsls r3, r3, #3 8002bbc: 4413 add r3, r2 8002bbe: 009b lsls r3, r3, #2 8002bc0: 440b add r3, r1 8002bc2: 331c adds r3, #28 8002bc4: 2200 movs r2, #0 8002bc6: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 8002bc8: 7bfa ldrb r2, [r7, #15] 8002bca: 6879 ldr r1, [r7, #4] 8002bcc: 4613 mov r3, r2 8002bce: 00db lsls r3, r3, #3 8002bd0: 4413 add r3, r2 8002bd2: 009b lsls r3, r3, #2 8002bd4: 440b add r3, r1 8002bd6: 3320 adds r3, #32 8002bd8: 2200 movs r2, #0 8002bda: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 8002bdc: 7bfa ldrb r2, [r7, #15] 8002bde: 6879 ldr r1, [r7, #4] 8002be0: 4613 mov r3, r2 8002be2: 00db lsls r3, r3, #3 8002be4: 4413 add r3, r2 8002be6: 009b lsls r3, r3, #2 8002be8: 440b add r3, r1 8002bea: 3324 adds r3, #36 @ 0x24 8002bec: 2200 movs r2, #0 8002bee: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002bf0: 7bfb ldrb r3, [r7, #15] 8002bf2: 3301 adds r3, #1 8002bf4: 73fb strb r3, [r7, #15] 8002bf6: 687b ldr r3, [r7, #4] 8002bf8: 791b ldrb r3, [r3, #4] 8002bfa: 7bfa ldrb r2, [r7, #15] 8002bfc: 429a cmp r2, r3 8002bfe: d3af bcc.n 8002b60 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002c00: 2300 movs r3, #0 8002c02: 73fb strb r3, [r7, #15] 8002c04: e044 b.n 8002c90 { hpcd->OUT_ep[i].is_in = 0U; 8002c06: 7bfa ldrb r2, [r7, #15] 8002c08: 6879 ldr r1, [r7, #4] 8002c0a: 4613 mov r3, r2 8002c0c: 00db lsls r3, r3, #3 8002c0e: 4413 add r3, r2 8002c10: 009b lsls r3, r3, #2 8002c12: 440b add r3, r1 8002c14: f203 2355 addw r3, r3, #597 @ 0x255 8002c18: 2200 movs r2, #0 8002c1a: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 8002c1c: 7bfa ldrb r2, [r7, #15] 8002c1e: 6879 ldr r1, [r7, #4] 8002c20: 4613 mov r3, r2 8002c22: 00db lsls r3, r3, #3 8002c24: 4413 add r3, r2 8002c26: 009b lsls r3, r3, #2 8002c28: 440b add r3, r1 8002c2a: f503 7315 add.w r3, r3, #596 @ 0x254 8002c2e: 7bfa ldrb r2, [r7, #15] 8002c30: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8002c32: 7bfa ldrb r2, [r7, #15] 8002c34: 6879 ldr r1, [r7, #4] 8002c36: 4613 mov r3, r2 8002c38: 00db lsls r3, r3, #3 8002c3a: 4413 add r3, r2 8002c3c: 009b lsls r3, r3, #2 8002c3e: 440b add r3, r1 8002c40: f503 7316 add.w r3, r3, #600 @ 0x258 8002c44: 2200 movs r2, #0 8002c46: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8002c48: 7bfa ldrb r2, [r7, #15] 8002c4a: 6879 ldr r1, [r7, #4] 8002c4c: 4613 mov r3, r2 8002c4e: 00db lsls r3, r3, #3 8002c50: 4413 add r3, r2 8002c52: 009b lsls r3, r3, #2 8002c54: 440b add r3, r1 8002c56: f503 7317 add.w r3, r3, #604 @ 0x25c 8002c5a: 2200 movs r2, #0 8002c5c: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 8002c5e: 7bfa ldrb r2, [r7, #15] 8002c60: 6879 ldr r1, [r7, #4] 8002c62: 4613 mov r3, r2 8002c64: 00db lsls r3, r3, #3 8002c66: 4413 add r3, r2 8002c68: 009b lsls r3, r3, #2 8002c6a: 440b add r3, r1 8002c6c: f503 7318 add.w r3, r3, #608 @ 0x260 8002c70: 2200 movs r2, #0 8002c72: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8002c74: 7bfa ldrb r2, [r7, #15] 8002c76: 6879 ldr r1, [r7, #4] 8002c78: 4613 mov r3, r2 8002c7a: 00db lsls r3, r3, #3 8002c7c: 4413 add r3, r2 8002c7e: 009b lsls r3, r3, #2 8002c80: 440b add r3, r1 8002c82: f503 7319 add.w r3, r3, #612 @ 0x264 8002c86: 2200 movs r2, #0 8002c88: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002c8a: 7bfb ldrb r3, [r7, #15] 8002c8c: 3301 adds r3, #1 8002c8e: 73fb strb r3, [r7, #15] 8002c90: 687b ldr r3, [r7, #4] 8002c92: 791b ldrb r3, [r3, #4] 8002c94: 7bfa ldrb r2, [r7, #15] 8002c96: 429a cmp r2, r3 8002c98: d3b5 bcc.n 8002c06 } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002c9a: 687b ldr r3, [r7, #4] 8002c9c: 6818 ldr r0, [r3, #0] 8002c9e: 687b ldr r3, [r7, #4] 8002ca0: 7c1a ldrb r2, [r3, #16] 8002ca2: f88d 2000 strb.w r2, [sp] 8002ca6: 3304 adds r3, #4 8002ca8: cb0e ldmia r3, {r1, r2, r3} 8002caa: f004 fa41 bl 8007130 8002cae: 4603 mov r3, r0 8002cb0: 2b00 cmp r3, #0 8002cb2: d005 beq.n 8002cc0 { hpcd->State = HAL_PCD_STATE_ERROR; 8002cb4: 687b ldr r3, [r7, #4] 8002cb6: 2202 movs r2, #2 8002cb8: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002cbc: 2301 movs r3, #1 8002cbe: e013 b.n 8002ce8 } hpcd->USB_Address = 0U; 8002cc0: 687b ldr r3, [r7, #4] 8002cc2: 2200 movs r2, #0 8002cc4: 745a strb r2, [r3, #17] hpcd->State = HAL_PCD_STATE_READY; 8002cc6: 687b ldr r3, [r7, #4] 8002cc8: 2201 movs r2, #1 8002cca: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 8002cce: 687b ldr r3, [r7, #4] 8002cd0: 7b1b ldrb r3, [r3, #12] 8002cd2: 2b01 cmp r3, #1 8002cd4: d102 bne.n 8002cdc { (void)HAL_PCDEx_ActivateLPM(hpcd); 8002cd6: 6878 ldr r0, [r7, #4] 8002cd8: f001 f956 bl 8003f88 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); 8002cdc: 687b ldr r3, [r7, #4] 8002cde: 681b ldr r3, [r3, #0] 8002ce0: 4618 mov r0, r3 8002ce2: f005 fa7e bl 80081e2 return HAL_OK; 8002ce6: 2300 movs r3, #0 } 8002ce8: 4618 mov r0, r3 8002cea: 3710 adds r7, #16 8002cec: 46bd mov sp, r7 8002cee: bd80 pop {r7, pc} 08002cf0 : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 8002cf0: b580 push {r7, lr} 8002cf2: b084 sub sp, #16 8002cf4: af00 add r7, sp, #0 8002cf6: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002cf8: 687b ldr r3, [r7, #4] 8002cfa: 681b ldr r3, [r3, #0] 8002cfc: 60fb str r3, [r7, #12] __HAL_LOCK(hpcd); 8002cfe: 687b ldr r3, [r7, #4] 8002d00: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8002d04: 2b01 cmp r3, #1 8002d06: d101 bne.n 8002d0c 8002d08: 2302 movs r3, #2 8002d0a: e022 b.n 8002d52 8002d0c: 687b ldr r3, [r7, #4] 8002d0e: 2201 movs r2, #1 8002d10: f883 2494 strb.w r2, [r3, #1172] @ 0x494 if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8002d14: 68fb ldr r3, [r7, #12] 8002d16: 68db ldr r3, [r3, #12] 8002d18: f003 0340 and.w r3, r3, #64 @ 0x40 8002d1c: 2b00 cmp r3, #0 8002d1e: d009 beq.n 8002d34 (hpcd->Init.battery_charging_enable == 1U)) 8002d20: 687b ldr r3, [r7, #4] 8002d22: 7b5b ldrb r3, [r3, #13] if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8002d24: 2b01 cmp r3, #1 8002d26: d105 bne.n 8002d34 { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8002d28: 68fb ldr r3, [r7, #12] 8002d2a: 6b9b ldr r3, [r3, #56] @ 0x38 8002d2c: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8002d30: 68fb ldr r3, [r7, #12] 8002d32: 639a str r2, [r3, #56] @ 0x38 } __HAL_PCD_ENABLE(hpcd); 8002d34: 687b ldr r3, [r7, #4] 8002d36: 681b ldr r3, [r3, #0] 8002d38: 4618 mov r0, r3 8002d3a: f004 f98b bl 8007054 (void)USB_DevConnect(hpcd->Instance); 8002d3e: 687b ldr r3, [r7, #4] 8002d40: 681b ldr r3, [r3, #0] 8002d42: 4618 mov r0, r3 8002d44: f005 fa2c bl 80081a0 __HAL_UNLOCK(hpcd); 8002d48: 687b ldr r3, [r7, #4] 8002d4a: 2200 movs r2, #0 8002d4c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8002d50: 2300 movs r3, #0 } 8002d52: 4618 mov r0, r3 8002d54: 3710 adds r7, #16 8002d56: 46bd mov sp, r7 8002d58: bd80 pop {r7, pc} 08002d5a : * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 8002d5a: b590 push {r4, r7, lr} 8002d5c: b08d sub sp, #52 @ 0x34 8002d5e: af00 add r7, sp, #0 8002d60: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002d62: 687b ldr r3, [r7, #4] 8002d64: 681b ldr r3, [r3, #0] 8002d66: 623b str r3, [r7, #32] uint32_t USBx_BASE = (uint32_t)USBx; 8002d68: 6a3b ldr r3, [r7, #32] 8002d6a: 61fb str r3, [r7, #28] uint32_t epnum; uint32_t fifoemptymsk; uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) 8002d6c: 687b ldr r3, [r7, #4] 8002d6e: 681b ldr r3, [r3, #0] 8002d70: 4618 mov r0, r3 8002d72: f005 faea bl 800834a 8002d76: 4603 mov r3, r0 8002d78: 2b00 cmp r3, #0 8002d7a: f040 84b9 bne.w 80036f0 { /* avoid spurious interrupt */ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 8002d7e: 687b ldr r3, [r7, #4] 8002d80: 681b ldr r3, [r3, #0] 8002d82: 4618 mov r0, r3 8002d84: f005 fa4e bl 8008224 8002d88: 4603 mov r3, r0 8002d8a: 2b00 cmp r3, #0 8002d8c: f000 84af beq.w 80036ee { return; } /* store current frame number */ hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; 8002d90: 69fb ldr r3, [r7, #28] 8002d92: f503 6300 add.w r3, r3, #2048 @ 0x800 8002d96: 689b ldr r3, [r3, #8] 8002d98: 0a1b lsrs r3, r3, #8 8002d9a: f3c3 020d ubfx r2, r3, #0, #14 8002d9e: 687b ldr r3, [r7, #4] 8002da0: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4 if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) 8002da4: 687b ldr r3, [r7, #4] 8002da6: 681b ldr r3, [r3, #0] 8002da8: 4618 mov r0, r3 8002daa: f005 fa3b bl 8008224 8002dae: 4603 mov r3, r0 8002db0: f003 0302 and.w r3, r3, #2 8002db4: 2b02 cmp r3, #2 8002db6: d107 bne.n 8002dc8 { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); 8002db8: 687b ldr r3, [r7, #4] 8002dba: 681b ldr r3, [r3, #0] 8002dbc: 695a ldr r2, [r3, #20] 8002dbe: 687b ldr r3, [r7, #4] 8002dc0: 681b ldr r3, [r3, #0] 8002dc2: f002 0202 and.w r2, r2, #2 8002dc6: 615a str r2, [r3, #20] } /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) 8002dc8: 687b ldr r3, [r7, #4] 8002dca: 681b ldr r3, [r3, #0] 8002dcc: 4618 mov r0, r3 8002dce: f005 fa29 bl 8008224 8002dd2: 4603 mov r3, r0 8002dd4: f003 0310 and.w r3, r3, #16 8002dd8: 2b10 cmp r3, #16 8002dda: d161 bne.n 8002ea0 { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002ddc: 687b ldr r3, [r7, #4] 8002dde: 681b ldr r3, [r3, #0] 8002de0: 699a ldr r2, [r3, #24] 8002de2: 687b ldr r3, [r7, #4] 8002de4: 681b ldr r3, [r3, #0] 8002de6: f022 0210 bic.w r2, r2, #16 8002dea: 619a str r2, [r3, #24] RegVal = USBx->GRXSTSP; 8002dec: 6a3b ldr r3, [r7, #32] 8002dee: 6a1b ldr r3, [r3, #32] 8002df0: 61bb str r3, [r7, #24] ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; 8002df2: 69bb ldr r3, [r7, #24] 8002df4: f003 020f and.w r2, r3, #15 8002df8: 4613 mov r3, r2 8002dfa: 00db lsls r3, r3, #3 8002dfc: 4413 add r3, r2 8002dfe: 009b lsls r3, r3, #2 8002e00: f503 7314 add.w r3, r3, #592 @ 0x250 8002e04: 687a ldr r2, [r7, #4] 8002e06: 4413 add r3, r2 8002e08: 3304 adds r3, #4 8002e0a: 617b str r3, [r7, #20] if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) 8002e0c: 69bb ldr r3, [r7, #24] 8002e0e: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8002e12: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8002e16: d124 bne.n 8002e62 { if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) 8002e18: 69ba ldr r2, [r7, #24] 8002e1a: f647 73f0 movw r3, #32752 @ 0x7ff0 8002e1e: 4013 ands r3, r2 8002e20: 2b00 cmp r3, #0 8002e22: d035 beq.n 8002e90 { (void)USB_ReadPacket(USBx, ep->xfer_buff, 8002e24: 697b ldr r3, [r7, #20] 8002e26: 68d9 ldr r1, [r3, #12] (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); 8002e28: 69bb ldr r3, [r7, #24] 8002e2a: 091b lsrs r3, r3, #4 8002e2c: b29b uxth r3, r3 (void)USB_ReadPacket(USBx, ep->xfer_buff, 8002e2e: f3c3 030a ubfx r3, r3, #0, #11 8002e32: b29b uxth r3, r3 8002e34: 461a mov r2, r3 8002e36: 6a38 ldr r0, [r7, #32] 8002e38: f005 f860 bl 8007efc ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002e3c: 697b ldr r3, [r7, #20] 8002e3e: 68da ldr r2, [r3, #12] 8002e40: 69bb ldr r3, [r7, #24] 8002e42: 091b lsrs r3, r3, #4 8002e44: f3c3 030a ubfx r3, r3, #0, #11 8002e48: 441a add r2, r3 8002e4a: 697b ldr r3, [r7, #20] 8002e4c: 60da str r2, [r3, #12] ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002e4e: 697b ldr r3, [r7, #20] 8002e50: 695a ldr r2, [r3, #20] 8002e52: 69bb ldr r3, [r7, #24] 8002e54: 091b lsrs r3, r3, #4 8002e56: f3c3 030a ubfx r3, r3, #0, #11 8002e5a: 441a add r2, r3 8002e5c: 697b ldr r3, [r7, #20] 8002e5e: 615a str r2, [r3, #20] 8002e60: e016 b.n 8002e90 } } else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) 8002e62: 69bb ldr r3, [r7, #24] 8002e64: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8002e68: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8002e6c: d110 bne.n 8002e90 { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); 8002e6e: 687b ldr r3, [r7, #4] 8002e70: f203 439c addw r3, r3, #1180 @ 0x49c 8002e74: 2208 movs r2, #8 8002e76: 4619 mov r1, r3 8002e78: 6a38 ldr r0, [r7, #32] 8002e7a: f005 f83f bl 8007efc ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002e7e: 697b ldr r3, [r7, #20] 8002e80: 695a ldr r2, [r3, #20] 8002e82: 69bb ldr r3, [r7, #24] 8002e84: 091b lsrs r3, r3, #4 8002e86: f3c3 030a ubfx r3, r3, #0, #11 8002e8a: 441a add r2, r3 8002e8c: 697b ldr r3, [r7, #20] 8002e8e: 615a str r2, [r3, #20] else { /* ... */ } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002e90: 687b ldr r3, [r7, #4] 8002e92: 681b ldr r3, [r3, #0] 8002e94: 699a ldr r2, [r3, #24] 8002e96: 687b ldr r3, [r7, #4] 8002e98: 681b ldr r3, [r3, #0] 8002e9a: f042 0210 orr.w r2, r2, #16 8002e9e: 619a str r2, [r3, #24] } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) 8002ea0: 687b ldr r3, [r7, #4] 8002ea2: 681b ldr r3, [r3, #0] 8002ea4: 4618 mov r0, r3 8002ea6: f005 f9bd bl 8008224 8002eaa: 4603 mov r3, r0 8002eac: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002eb0: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8002eb4: f040 80a7 bne.w 8003006 { epnum = 0U; 8002eb8: 2300 movs r3, #0 8002eba: 627b str r3, [r7, #36] @ 0x24 /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); 8002ebc: 687b ldr r3, [r7, #4] 8002ebe: 681b ldr r3, [r3, #0] 8002ec0: 4618 mov r0, r3 8002ec2: f005 f9c2 bl 800824a 8002ec6: 62b8 str r0, [r7, #40] @ 0x28 while (ep_intr != 0U) 8002ec8: e099 b.n 8002ffe { if ((ep_intr & 0x1U) != 0U) 8002eca: 6abb ldr r3, [r7, #40] @ 0x28 8002ecc: f003 0301 and.w r3, r3, #1 8002ed0: 2b00 cmp r3, #0 8002ed2: f000 808e beq.w 8002ff2 { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8002ed6: 687b ldr r3, [r7, #4] 8002ed8: 681b ldr r3, [r3, #0] 8002eda: 6a7a ldr r2, [r7, #36] @ 0x24 8002edc: b2d2 uxtb r2, r2 8002ede: 4611 mov r1, r2 8002ee0: 4618 mov r0, r3 8002ee2: f005 f9e6 bl 80082b2 8002ee6: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) 8002ee8: 693b ldr r3, [r7, #16] 8002eea: f003 0301 and.w r3, r3, #1 8002eee: 2b00 cmp r3, #0 8002ef0: d00c beq.n 8002f0c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); 8002ef2: 6a7b ldr r3, [r7, #36] @ 0x24 8002ef4: 015a lsls r2, r3, #5 8002ef6: 69fb ldr r3, [r7, #28] 8002ef8: 4413 add r3, r2 8002efa: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002efe: 461a mov r2, r3 8002f00: 2301 movs r3, #1 8002f02: 6093 str r3, [r2, #8] (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); 8002f04: 6a79 ldr r1, [r7, #36] @ 0x24 8002f06: 6878 ldr r0, [r7, #4] 8002f08: f000 feb8 bl 8003c7c } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) 8002f0c: 693b ldr r3, [r7, #16] 8002f0e: f003 0308 and.w r3, r3, #8 8002f12: 2b00 cmp r3, #0 8002f14: d00c beq.n 8002f30 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); 8002f16: 6a7b ldr r3, [r7, #36] @ 0x24 8002f18: 015a lsls r2, r3, #5 8002f1a: 69fb ldr r3, [r7, #28] 8002f1c: 4413 add r3, r2 8002f1e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002f22: 461a mov r2, r3 8002f24: 2308 movs r3, #8 8002f26: 6093 str r3, [r2, #8] /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); 8002f28: 6a79 ldr r1, [r7, #36] @ 0x24 8002f2a: 6878 ldr r0, [r7, #4] 8002f2c: f000 ff8e bl 8003e4c } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) 8002f30: 693b ldr r3, [r7, #16] 8002f32: f003 0310 and.w r3, r3, #16 8002f36: 2b00 cmp r3, #0 8002f38: d008 beq.n 8002f4c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); 8002f3a: 6a7b ldr r3, [r7, #36] @ 0x24 8002f3c: 015a lsls r2, r3, #5 8002f3e: 69fb ldr r3, [r7, #28] 8002f40: 4413 add r3, r2 8002f42: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002f46: 461a mov r2, r3 8002f48: 2310 movs r3, #16 8002f4a: 6093 str r3, [r2, #8] } /* Clear OUT Endpoint disable interrupt */ if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) 8002f4c: 693b ldr r3, [r7, #16] 8002f4e: f003 0302 and.w r3, r3, #2 8002f52: 2b00 cmp r3, #0 8002f54: d030 beq.n 8002fb8 { if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) 8002f56: 6a3b ldr r3, [r7, #32] 8002f58: 695b ldr r3, [r3, #20] 8002f5a: f003 0380 and.w r3, r3, #128 @ 0x80 8002f5e: 2b80 cmp r3, #128 @ 0x80 8002f60: d109 bne.n 8002f76 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; 8002f62: 69fb ldr r3, [r7, #28] 8002f64: f503 6300 add.w r3, r3, #2048 @ 0x800 8002f68: 685b ldr r3, [r3, #4] 8002f6a: 69fa ldr r2, [r7, #28] 8002f6c: f502 6200 add.w r2, r2, #2048 @ 0x800 8002f70: f443 6380 orr.w r3, r3, #1024 @ 0x400 8002f74: 6053 str r3, [r2, #4] } ep = &hpcd->OUT_ep[epnum]; 8002f76: 6a7a ldr r2, [r7, #36] @ 0x24 8002f78: 4613 mov r3, r2 8002f7a: 00db lsls r3, r3, #3 8002f7c: 4413 add r3, r2 8002f7e: 009b lsls r3, r3, #2 8002f80: f503 7314 add.w r3, r3, #592 @ 0x250 8002f84: 687a ldr r2, [r7, #4] 8002f86: 4413 add r3, r2 8002f88: 3304 adds r3, #4 8002f8a: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 8002f8c: 697b ldr r3, [r7, #20] 8002f8e: 78db ldrb r3, [r3, #3] 8002f90: 2b01 cmp r3, #1 8002f92: d108 bne.n 8002fa6 { ep->is_iso_incomplete = 0U; 8002f94: 697b ldr r3, [r7, #20] 8002f96: 2200 movs r2, #0 8002f98: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); 8002f9a: 6a7b ldr r3, [r7, #36] @ 0x24 8002f9c: b2db uxtb r3, r3 8002f9e: 4619 mov r1, r3 8002fa0: 6878 ldr r0, [r7, #4] 8002fa2: f007 fa7f bl 800a4a4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); 8002fa6: 6a7b ldr r3, [r7, #36] @ 0x24 8002fa8: 015a lsls r2, r3, #5 8002faa: 69fb ldr r3, [r7, #28] 8002fac: 4413 add r3, r2 8002fae: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002fb2: 461a mov r2, r3 8002fb4: 2302 movs r3, #2 8002fb6: 6093 str r3, [r2, #8] } /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8002fb8: 693b ldr r3, [r7, #16] 8002fba: f003 0320 and.w r3, r3, #32 8002fbe: 2b00 cmp r3, #0 8002fc0: d008 beq.n 8002fd4 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8002fc2: 6a7b ldr r3, [r7, #36] @ 0x24 8002fc4: 015a lsls r2, r3, #5 8002fc6: 69fb ldr r3, [r7, #28] 8002fc8: 4413 add r3, r2 8002fca: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002fce: 461a mov r2, r3 8002fd0: 2320 movs r3, #32 8002fd2: 6093 str r3, [r2, #8] } /* Clear OUT NAK interrupt */ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) 8002fd4: 693b ldr r3, [r7, #16] 8002fd6: f403 5300 and.w r3, r3, #8192 @ 0x2000 8002fda: 2b00 cmp r3, #0 8002fdc: d009 beq.n 8002ff2 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); 8002fde: 6a7b ldr r3, [r7, #36] @ 0x24 8002fe0: 015a lsls r2, r3, #5 8002fe2: 69fb ldr r3, [r7, #28] 8002fe4: 4413 add r3, r2 8002fe6: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002fea: 461a mov r2, r3 8002fec: f44f 5300 mov.w r3, #8192 @ 0x2000 8002ff0: 6093 str r3, [r2, #8] } } epnum++; 8002ff2: 6a7b ldr r3, [r7, #36] @ 0x24 8002ff4: 3301 adds r3, #1 8002ff6: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 8002ff8: 6abb ldr r3, [r7, #40] @ 0x28 8002ffa: 085b lsrs r3, r3, #1 8002ffc: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 8002ffe: 6abb ldr r3, [r7, #40] @ 0x28 8003000: 2b00 cmp r3, #0 8003002: f47f af62 bne.w 8002eca } } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) 8003006: 687b ldr r3, [r7, #4] 8003008: 681b ldr r3, [r3, #0] 800300a: 4618 mov r0, r3 800300c: f005 f90a bl 8008224 8003010: 4603 mov r3, r0 8003012: f403 2380 and.w r3, r3, #262144 @ 0x40000 8003016: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800301a: f040 80db bne.w 80031d4 { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); 800301e: 687b ldr r3, [r7, #4] 8003020: 681b ldr r3, [r3, #0] 8003022: 4618 mov r0, r3 8003024: f005 f92b bl 800827e 8003028: 62b8 str r0, [r7, #40] @ 0x28 epnum = 0U; 800302a: 2300 movs r3, #0 800302c: 627b str r3, [r7, #36] @ 0x24 while (ep_intr != 0U) 800302e: e0cd b.n 80031cc { if ((ep_intr & 0x1U) != 0U) /* In ITR */ 8003030: 6abb ldr r3, [r7, #40] @ 0x28 8003032: f003 0301 and.w r3, r3, #1 8003036: 2b00 cmp r3, #0 8003038: f000 80c2 beq.w 80031c0 { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); 800303c: 687b ldr r3, [r7, #4] 800303e: 681b ldr r3, [r3, #0] 8003040: 6a7a ldr r2, [r7, #36] @ 0x24 8003042: b2d2 uxtb r2, r2 8003044: 4611 mov r1, r2 8003046: 4618 mov r0, r3 8003048: f005 f951 bl 80082ee 800304c: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) 800304e: 693b ldr r3, [r7, #16] 8003050: f003 0301 and.w r3, r3, #1 8003054: 2b00 cmp r3, #0 8003056: d057 beq.n 8003108 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8003058: 6a7b ldr r3, [r7, #36] @ 0x24 800305a: f003 030f and.w r3, r3, #15 800305e: 2201 movs r2, #1 8003060: fa02 f303 lsl.w r3, r2, r3 8003064: 60fb str r3, [r7, #12] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8003066: 69fb ldr r3, [r7, #28] 8003068: f503 6300 add.w r3, r3, #2048 @ 0x800 800306c: 6b5a ldr r2, [r3, #52] @ 0x34 800306e: 68fb ldr r3, [r7, #12] 8003070: 43db mvns r3, r3 8003072: 69f9 ldr r1, [r7, #28] 8003074: f501 6100 add.w r1, r1, #2048 @ 0x800 8003078: 4013 ands r3, r2 800307a: 634b str r3, [r1, #52] @ 0x34 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); 800307c: 6a7b ldr r3, [r7, #36] @ 0x24 800307e: 015a lsls r2, r3, #5 8003080: 69fb ldr r3, [r7, #28] 8003082: 4413 add r3, r2 8003084: f503 6310 add.w r3, r3, #2304 @ 0x900 8003088: 461a mov r2, r3 800308a: 2301 movs r3, #1 800308c: 6093 str r3, [r2, #8] if (hpcd->Init.dma_enable == 1U) 800308e: 687b ldr r3, [r7, #4] 8003090: 799b ldrb r3, [r3, #6] 8003092: 2b01 cmp r3, #1 8003094: d132 bne.n 80030fc { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 8003096: 6879 ldr r1, [r7, #4] 8003098: 6a7a ldr r2, [r7, #36] @ 0x24 800309a: 4613 mov r3, r2 800309c: 00db lsls r3, r3, #3 800309e: 4413 add r3, r2 80030a0: 009b lsls r3, r3, #2 80030a2: 440b add r3, r1 80030a4: 3320 adds r3, #32 80030a6: 6819 ldr r1, [r3, #0] 80030a8: 6878 ldr r0, [r7, #4] 80030aa: 6a7a ldr r2, [r7, #36] @ 0x24 80030ac: 4613 mov r3, r2 80030ae: 00db lsls r3, r3, #3 80030b0: 4413 add r3, r2 80030b2: 009b lsls r3, r3, #2 80030b4: 4403 add r3, r0 80030b6: 331c adds r3, #28 80030b8: 681b ldr r3, [r3, #0] 80030ba: 4419 add r1, r3 80030bc: 6878 ldr r0, [r7, #4] 80030be: 6a7a ldr r2, [r7, #36] @ 0x24 80030c0: 4613 mov r3, r2 80030c2: 00db lsls r3, r3, #3 80030c4: 4413 add r3, r2 80030c6: 009b lsls r3, r3, #2 80030c8: 4403 add r3, r0 80030ca: 3320 adds r3, #32 80030cc: 6019 str r1, [r3, #0] /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) 80030ce: 6a7b ldr r3, [r7, #36] @ 0x24 80030d0: 2b00 cmp r3, #0 80030d2: d113 bne.n 80030fc 80030d4: 6879 ldr r1, [r7, #4] 80030d6: 6a7a ldr r2, [r7, #36] @ 0x24 80030d8: 4613 mov r3, r2 80030da: 00db lsls r3, r3, #3 80030dc: 4413 add r3, r2 80030de: 009b lsls r3, r3, #2 80030e0: 440b add r3, r1 80030e2: 3324 adds r3, #36 @ 0x24 80030e4: 681b ldr r3, [r3, #0] 80030e6: 2b00 cmp r3, #0 80030e8: d108 bne.n 80030fc { /* prepare to rx more setup packets */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 80030ea: 687b ldr r3, [r7, #4] 80030ec: 6818 ldr r0, [r3, #0] 80030ee: 687b ldr r3, [r7, #4] 80030f0: f203 439c addw r3, r3, #1180 @ 0x49c 80030f4: 461a mov r2, r3 80030f6: 2101 movs r1, #1 80030f8: f005 f958 bl 80083ac } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); 80030fc: 6a7b ldr r3, [r7, #36] @ 0x24 80030fe: b2db uxtb r3, r3 8003100: 4619 mov r1, r3 8003102: 6878 ldr r0, [r7, #4] 8003104: f007 f949 bl 800a39a #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) 8003108: 693b ldr r3, [r7, #16] 800310a: f003 0308 and.w r3, r3, #8 800310e: 2b00 cmp r3, #0 8003110: d008 beq.n 8003124 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); 8003112: 6a7b ldr r3, [r7, #36] @ 0x24 8003114: 015a lsls r2, r3, #5 8003116: 69fb ldr r3, [r7, #28] 8003118: 4413 add r3, r2 800311a: f503 6310 add.w r3, r3, #2304 @ 0x900 800311e: 461a mov r2, r3 8003120: 2308 movs r3, #8 8003122: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) 8003124: 693b ldr r3, [r7, #16] 8003126: f003 0310 and.w r3, r3, #16 800312a: 2b00 cmp r3, #0 800312c: d008 beq.n 8003140 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); 800312e: 6a7b ldr r3, [r7, #36] @ 0x24 8003130: 015a lsls r2, r3, #5 8003132: 69fb ldr r3, [r7, #28] 8003134: 4413 add r3, r2 8003136: f503 6310 add.w r3, r3, #2304 @ 0x900 800313a: 461a mov r2, r3 800313c: 2310 movs r3, #16 800313e: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) 8003140: 693b ldr r3, [r7, #16] 8003142: f003 0340 and.w r3, r3, #64 @ 0x40 8003146: 2b00 cmp r3, #0 8003148: d008 beq.n 800315c { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); 800314a: 6a7b ldr r3, [r7, #36] @ 0x24 800314c: 015a lsls r2, r3, #5 800314e: 69fb ldr r3, [r7, #28] 8003150: 4413 add r3, r2 8003152: f503 6310 add.w r3, r3, #2304 @ 0x900 8003156: 461a mov r2, r3 8003158: 2340 movs r3, #64 @ 0x40 800315a: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) 800315c: 693b ldr r3, [r7, #16] 800315e: f003 0302 and.w r3, r3, #2 8003162: 2b00 cmp r3, #0 8003164: d023 beq.n 80031ae { (void)USB_FlushTxFifo(USBx, epnum); 8003166: 6a79 ldr r1, [r7, #36] @ 0x24 8003168: 6a38 ldr r0, [r7, #32] 800316a: f004 f93f bl 80073ec ep = &hpcd->IN_ep[epnum]; 800316e: 6a7a ldr r2, [r7, #36] @ 0x24 8003170: 4613 mov r3, r2 8003172: 00db lsls r3, r3, #3 8003174: 4413 add r3, r2 8003176: 009b lsls r3, r3, #2 8003178: 3310 adds r3, #16 800317a: 687a ldr r2, [r7, #4] 800317c: 4413 add r3, r2 800317e: 3304 adds r3, #4 8003180: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 8003182: 697b ldr r3, [r7, #20] 8003184: 78db ldrb r3, [r3, #3] 8003186: 2b01 cmp r3, #1 8003188: d108 bne.n 800319c { ep->is_iso_incomplete = 0U; 800318a: 697b ldr r3, [r7, #20] 800318c: 2200 movs r2, #0 800318e: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); 8003190: 6a7b ldr r3, [r7, #36] @ 0x24 8003192: b2db uxtb r3, r3 8003194: 4619 mov r1, r3 8003196: 6878 ldr r0, [r7, #4] 8003198: f007 f996 bl 800a4c8 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); 800319c: 6a7b ldr r3, [r7, #36] @ 0x24 800319e: 015a lsls r2, r3, #5 80031a0: 69fb ldr r3, [r7, #28] 80031a2: 4413 add r3, r2 80031a4: f503 6310 add.w r3, r3, #2304 @ 0x900 80031a8: 461a mov r2, r3 80031aa: 2302 movs r3, #2 80031ac: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) 80031ae: 693b ldr r3, [r7, #16] 80031b0: f003 0380 and.w r3, r3, #128 @ 0x80 80031b4: 2b00 cmp r3, #0 80031b6: d003 beq.n 80031c0 { (void)PCD_WriteEmptyTxFifo(hpcd, epnum); 80031b8: 6a79 ldr r1, [r7, #36] @ 0x24 80031ba: 6878 ldr r0, [r7, #4] 80031bc: f000 fcd2 bl 8003b64 } } epnum++; 80031c0: 6a7b ldr r3, [r7, #36] @ 0x24 80031c2: 3301 adds r3, #1 80031c4: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 80031c6: 6abb ldr r3, [r7, #40] @ 0x28 80031c8: 085b lsrs r3, r3, #1 80031ca: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 80031cc: 6abb ldr r3, [r7, #40] @ 0x28 80031ce: 2b00 cmp r3, #0 80031d0: f47f af2e bne.w 8003030 } } /* Handle Resume Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) 80031d4: 687b ldr r3, [r7, #4] 80031d6: 681b ldr r3, [r3, #0] 80031d8: 4618 mov r0, r3 80031da: f005 f823 bl 8008224 80031de: 4603 mov r3, r0 80031e0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80031e4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80031e8: d122 bne.n 8003230 { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 80031ea: 69fb ldr r3, [r7, #28] 80031ec: f503 6300 add.w r3, r3, #2048 @ 0x800 80031f0: 685b ldr r3, [r3, #4] 80031f2: 69fa ldr r2, [r7, #28] 80031f4: f502 6200 add.w r2, r2, #2048 @ 0x800 80031f8: f023 0301 bic.w r3, r3, #1 80031fc: 6053 str r3, [r2, #4] if (hpcd->LPM_State == LPM_L1) 80031fe: 687b ldr r3, [r7, #4] 8003200: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 8003204: 2b01 cmp r3, #1 8003206: d108 bne.n 800321a { hpcd->LPM_State = LPM_L0; 8003208: 687b ldr r3, [r7, #4] 800320a: 2200 movs r2, #0 800320c: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 8003210: 2100 movs r1, #0 8003212: 6878 ldr r0, [r7, #4] 8003214: f007 fafe bl 800a814 8003218: e002 b.n 8003220 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 800321a: 6878 ldr r0, [r7, #4] 800321c: f007 f934 bl 800a488 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); 8003220: 687b ldr r3, [r7, #4] 8003222: 681b ldr r3, [r3, #0] 8003224: 695a ldr r2, [r3, #20] 8003226: 687b ldr r3, [r7, #4] 8003228: 681b ldr r3, [r3, #0] 800322a: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000 800322e: 615a str r2, [r3, #20] } /* Handle Suspend Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) 8003230: 687b ldr r3, [r7, #4] 8003232: 681b ldr r3, [r3, #0] 8003234: 4618 mov r0, r3 8003236: f004 fff5 bl 8008224 800323a: 4603 mov r3, r0 800323c: f403 6300 and.w r3, r3, #2048 @ 0x800 8003240: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8003244: d112 bne.n 800326c { if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 8003246: 69fb ldr r3, [r7, #28] 8003248: f503 6300 add.w r3, r3, #2048 @ 0x800 800324c: 689b ldr r3, [r3, #8] 800324e: f003 0301 and.w r3, r3, #1 8003252: 2b01 cmp r3, #1 8003254: d102 bne.n 800325c { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 8003256: 6878 ldr r0, [r7, #4] 8003258: f007 f8f0 bl 800a43c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); 800325c: 687b ldr r3, [r7, #4] 800325e: 681b ldr r3, [r3, #0] 8003260: 695a ldr r2, [r3, #20] 8003262: 687b ldr r3, [r7, #4] 8003264: 681b ldr r3, [r3, #0] 8003266: f402 6200 and.w r2, r2, #2048 @ 0x800 800326a: 615a str r2, [r3, #20] } #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) 800326c: 687b ldr r3, [r7, #4] 800326e: 681b ldr r3, [r3, #0] 8003270: 4618 mov r0, r3 8003272: f004 ffd7 bl 8008224 8003276: 4603 mov r3, r0 8003278: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800327c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8003280: d121 bne.n 80032c6 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); 8003282: 687b ldr r3, [r7, #4] 8003284: 681b ldr r3, [r3, #0] 8003286: 695a ldr r2, [r3, #20] 8003288: 687b ldr r3, [r7, #4] 800328a: 681b ldr r3, [r3, #0] 800328c: f002 6200 and.w r2, r2, #134217728 @ 0x8000000 8003290: 615a str r2, [r3, #20] if (hpcd->LPM_State == LPM_L0) 8003292: 687b ldr r3, [r7, #4] 8003294: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 8003298: 2b00 cmp r3, #0 800329a: d111 bne.n 80032c0 { hpcd->LPM_State = LPM_L1; 800329c: 687b ldr r3, [r7, #4] 800329e: 2201 movs r2, #1 80032a0: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; 80032a4: 687b ldr r3, [r7, #4] 80032a6: 681b ldr r3, [r3, #0] 80032a8: 6d5b ldr r3, [r3, #84] @ 0x54 80032aa: 089b lsrs r3, r3, #2 80032ac: f003 020f and.w r2, r3, #15 80032b0: 687b ldr r3, [r7, #4] 80032b2: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 80032b6: 2101 movs r1, #1 80032b8: 6878 ldr r0, [r7, #4] 80032ba: f007 faab bl 800a814 80032be: e002 b.n 80032c6 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 80032c0: 6878 ldr r0, [r7, #4] 80032c2: f007 f8bb bl 800a43c } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) 80032c6: 687b ldr r3, [r7, #4] 80032c8: 681b ldr r3, [r3, #0] 80032ca: 4618 mov r0, r3 80032cc: f004 ffaa bl 8008224 80032d0: 4603 mov r3, r0 80032d2: f403 5380 and.w r3, r3, #4096 @ 0x1000 80032d6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80032da: f040 80b7 bne.w 800344c { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 80032de: 69fb ldr r3, [r7, #28] 80032e0: f503 6300 add.w r3, r3, #2048 @ 0x800 80032e4: 685b ldr r3, [r3, #4] 80032e6: 69fa ldr r2, [r7, #28] 80032e8: f502 6200 add.w r2, r2, #2048 @ 0x800 80032ec: f023 0301 bic.w r3, r3, #1 80032f0: 6053 str r3, [r2, #4] (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); 80032f2: 687b ldr r3, [r7, #4] 80032f4: 681b ldr r3, [r3, #0] 80032f6: 2110 movs r1, #16 80032f8: 4618 mov r0, r3 80032fa: f004 f877 bl 80073ec for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80032fe: 2300 movs r3, #0 8003300: 62fb str r3, [r7, #44] @ 0x2c 8003302: e046 b.n 8003392 { USBx_INEP(i)->DIEPINT = 0xFB7FU; 8003304: 6afb ldr r3, [r7, #44] @ 0x2c 8003306: 015a lsls r2, r3, #5 8003308: 69fb ldr r3, [r7, #28] 800330a: 4413 add r3, r2 800330c: f503 6310 add.w r3, r3, #2304 @ 0x900 8003310: 461a mov r2, r3 8003312: f64f 337f movw r3, #64383 @ 0xfb7f 8003316: 6093 str r3, [r2, #8] USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 8003318: 6afb ldr r3, [r7, #44] @ 0x2c 800331a: 015a lsls r2, r3, #5 800331c: 69fb ldr r3, [r7, #28] 800331e: 4413 add r3, r2 8003320: f503 6310 add.w r3, r3, #2304 @ 0x900 8003324: 681b ldr r3, [r3, #0] 8003326: 6afa ldr r2, [r7, #44] @ 0x2c 8003328: 0151 lsls r1, r2, #5 800332a: 69fa ldr r2, [r7, #28] 800332c: 440a add r2, r1 800332e: f502 6210 add.w r2, r2, #2304 @ 0x900 8003332: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8003336: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8003338: 6afb ldr r3, [r7, #44] @ 0x2c 800333a: 015a lsls r2, r3, #5 800333c: 69fb ldr r3, [r7, #28] 800333e: 4413 add r3, r2 8003340: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003344: 461a mov r2, r3 8003346: f64f 337f movw r3, #64383 @ 0xfb7f 800334a: 6093 str r3, [r2, #8] USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 800334c: 6afb ldr r3, [r7, #44] @ 0x2c 800334e: 015a lsls r2, r3, #5 8003350: 69fb ldr r3, [r7, #28] 8003352: 4413 add r3, r2 8003354: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003358: 681b ldr r3, [r3, #0] 800335a: 6afa ldr r2, [r7, #44] @ 0x2c 800335c: 0151 lsls r1, r2, #5 800335e: 69fa ldr r2, [r7, #28] 8003360: 440a add r2, r1 8003362: f502 6230 add.w r2, r2, #2816 @ 0xb00 8003366: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 800336a: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 800336c: 6afb ldr r3, [r7, #44] @ 0x2c 800336e: 015a lsls r2, r3, #5 8003370: 69fb ldr r3, [r7, #28] 8003372: 4413 add r3, r2 8003374: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003378: 681b ldr r3, [r3, #0] 800337a: 6afa ldr r2, [r7, #44] @ 0x2c 800337c: 0151 lsls r1, r2, #5 800337e: 69fa ldr r2, [r7, #28] 8003380: 440a add r2, r1 8003382: f502 6230 add.w r2, r2, #2816 @ 0xb00 8003386: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800338a: 6013 str r3, [r2, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800338c: 6afb ldr r3, [r7, #44] @ 0x2c 800338e: 3301 adds r3, #1 8003390: 62fb str r3, [r7, #44] @ 0x2c 8003392: 687b ldr r3, [r7, #4] 8003394: 791b ldrb r3, [r3, #4] 8003396: 461a mov r2, r3 8003398: 6afb ldr r3, [r7, #44] @ 0x2c 800339a: 4293 cmp r3, r2 800339c: d3b2 bcc.n 8003304 } USBx_DEVICE->DAINTMSK |= 0x10001U; 800339e: 69fb ldr r3, [r7, #28] 80033a0: f503 6300 add.w r3, r3, #2048 @ 0x800 80033a4: 69db ldr r3, [r3, #28] 80033a6: 69fa ldr r2, [r7, #28] 80033a8: f502 6200 add.w r2, r2, #2048 @ 0x800 80033ac: f043 1301 orr.w r3, r3, #65537 @ 0x10001 80033b0: 61d3 str r3, [r2, #28] if (hpcd->Init.use_dedicated_ep1 != 0U) 80033b2: 687b ldr r3, [r7, #4] 80033b4: 7bdb ldrb r3, [r3, #15] 80033b6: 2b00 cmp r3, #0 80033b8: d016 beq.n 80033e8 { USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | 80033ba: 69fb ldr r3, [r7, #28] 80033bc: f503 6300 add.w r3, r3, #2048 @ 0x800 80033c0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80033c4: 69fa ldr r2, [r7, #28] 80033c6: f502 6200 add.w r2, r2, #2048 @ 0x800 80033ca: f043 030b orr.w r3, r3, #11 80033ce: f8c2 3084 str.w r3, [r2, #132] @ 0x84 USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM; USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | 80033d2: 69fb ldr r3, [r7, #28] 80033d4: f503 6300 add.w r3, r3, #2048 @ 0x800 80033d8: 6c5b ldr r3, [r3, #68] @ 0x44 80033da: 69fa ldr r2, [r7, #28] 80033dc: f502 6200 add.w r2, r2, #2048 @ 0x800 80033e0: f043 030b orr.w r3, r3, #11 80033e4: 6453 str r3, [r2, #68] @ 0x44 80033e6: e015 b.n 8003414 USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } else { USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | 80033e8: 69fb ldr r3, [r7, #28] 80033ea: f503 6300 add.w r3, r3, #2048 @ 0x800 80033ee: 695b ldr r3, [r3, #20] 80033f0: 69fa ldr r2, [r7, #28] 80033f2: f502 6200 add.w r2, r2, #2048 @ 0x800 80033f6: f443 5300 orr.w r3, r3, #8192 @ 0x2000 80033fa: f043 032b orr.w r3, r3, #43 @ 0x2b 80033fe: 6153 str r3, [r2, #20] USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM | USB_OTG_DOEPMSK_NAKM; USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | 8003400: 69fb ldr r3, [r7, #28] 8003402: f503 6300 add.w r3, r3, #2048 @ 0x800 8003406: 691b ldr r3, [r3, #16] 8003408: 69fa ldr r2, [r7, #28] 800340a: f502 6200 add.w r2, r2, #2048 @ 0x800 800340e: f043 030b orr.w r3, r3, #11 8003412: 6113 str r3, [r2, #16] USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; 8003414: 69fb ldr r3, [r7, #28] 8003416: f503 6300 add.w r3, r3, #2048 @ 0x800 800341a: 681b ldr r3, [r3, #0] 800341c: 69fa ldr r2, [r7, #28] 800341e: f502 6200 add.w r2, r2, #2048 @ 0x800 8003422: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 8003426: 6013 str r3, [r2, #0] /* setup EP0 to receive SETUP packets */ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 8003428: 687b ldr r3, [r7, #4] 800342a: 6818 ldr r0, [r3, #0] 800342c: 687b ldr r3, [r7, #4] 800342e: 7999 ldrb r1, [r3, #6] (uint8_t *)hpcd->Setup); 8003430: 687b ldr r3, [r7, #4] 8003432: f203 439c addw r3, r3, #1180 @ 0x49c (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 8003436: 461a mov r2, r3 8003438: f004 ffb8 bl 80083ac __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); 800343c: 687b ldr r3, [r7, #4] 800343e: 681b ldr r3, [r3, #0] 8003440: 695a ldr r2, [r3, #20] 8003442: 687b ldr r3, [r7, #4] 8003444: 681b ldr r3, [r3, #0] 8003446: f402 5280 and.w r2, r2, #4096 @ 0x1000 800344a: 615a str r2, [r3, #20] } /* Handle Enumeration done Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) 800344c: 687b ldr r3, [r7, #4] 800344e: 681b ldr r3, [r3, #0] 8003450: 4618 mov r0, r3 8003452: f004 fee7 bl 8008224 8003456: 4603 mov r3, r0 8003458: f403 5300 and.w r3, r3, #8192 @ 0x2000 800345c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8003460: d123 bne.n 80034aa { (void)USB_ActivateSetup(hpcd->Instance); 8003462: 687b ldr r3, [r7, #4] 8003464: 681b ldr r3, [r3, #0] 8003466: 4618 mov r0, r3 8003468: f004 ff7d bl 8008366 hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); 800346c: 687b ldr r3, [r7, #4] 800346e: 681b ldr r3, [r3, #0] 8003470: 4618 mov r0, r3 8003472: f004 f834 bl 80074de 8003476: 4603 mov r3, r0 8003478: 461a mov r2, r3 800347a: 687b ldr r3, [r7, #4] 800347c: 71da strb r2, [r3, #7] /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, 800347e: 687b ldr r3, [r7, #4] 8003480: 681c ldr r4, [r3, #0] 8003482: f000 fe8b bl 800419c 8003486: 4601 mov r1, r0 HAL_RCC_GetHCLKFreq(), (uint8_t)hpcd->Init.speed); 8003488: 687b ldr r3, [r7, #4] 800348a: 79db ldrb r3, [r3, #7] (void)USB_SetTurnaroundTime(hpcd->Instance, 800348c: 461a mov r2, r3 800348e: 4620 mov r0, r4 8003490: f003 fd3e bl 8006f10 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 8003494: 6878 ldr r0, [r7, #4] 8003496: f006 ffa8 bl 800a3ea #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); 800349a: 687b ldr r3, [r7, #4] 800349c: 681b ldr r3, [r3, #0] 800349e: 695a ldr r2, [r3, #20] 80034a0: 687b ldr r3, [r7, #4] 80034a2: 681b ldr r3, [r3, #0] 80034a4: f402 5200 and.w r2, r2, #8192 @ 0x2000 80034a8: 615a str r2, [r3, #20] } /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) 80034aa: 687b ldr r3, [r7, #4] 80034ac: 681b ldr r3, [r3, #0] 80034ae: 4618 mov r0, r3 80034b0: f004 feb8 bl 8008224 80034b4: 4603 mov r3, r0 80034b6: f003 0308 and.w r3, r3, #8 80034ba: 2b08 cmp r3, #8 80034bc: d10a bne.n 80034d4 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 80034be: 6878 ldr r0, [r7, #4] 80034c0: f006 ff85 bl 800a3ce #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); 80034c4: 687b ldr r3, [r7, #4] 80034c6: 681b ldr r3, [r3, #0] 80034c8: 695a ldr r2, [r3, #20] 80034ca: 687b ldr r3, [r7, #4] 80034cc: 681b ldr r3, [r3, #0] 80034ce: f002 0208 and.w r2, r2, #8 80034d2: 615a str r2, [r3, #20] } /* Handle Global OUT NAK effective Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) 80034d4: 687b ldr r3, [r7, #4] 80034d6: 681b ldr r3, [r3, #0] 80034d8: 4618 mov r0, r3 80034da: f004 fea3 bl 8008224 80034de: 4603 mov r3, r0 80034e0: f003 0380 and.w r3, r3, #128 @ 0x80 80034e4: 2b80 cmp r3, #128 @ 0x80 80034e6: d123 bne.n 8003530 { USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; 80034e8: 6a3b ldr r3, [r7, #32] 80034ea: 699b ldr r3, [r3, #24] 80034ec: f023 0280 bic.w r2, r3, #128 @ 0x80 80034f0: 6a3b ldr r3, [r7, #32] 80034f2: 619a str r2, [r3, #24] for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80034f4: 2301 movs r3, #1 80034f6: 627b str r3, [r7, #36] @ 0x24 80034f8: e014 b.n 8003524 { if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) 80034fa: 6879 ldr r1, [r7, #4] 80034fc: 6a7a ldr r2, [r7, #36] @ 0x24 80034fe: 4613 mov r3, r2 8003500: 00db lsls r3, r3, #3 8003502: 4413 add r3, r2 8003504: 009b lsls r3, r3, #2 8003506: 440b add r3, r1 8003508: f203 2357 addw r3, r3, #599 @ 0x257 800350c: 781b ldrb r3, [r3, #0] 800350e: 2b01 cmp r3, #1 8003510: d105 bne.n 800351e { /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); 8003512: 6a7b ldr r3, [r7, #36] @ 0x24 8003514: b2db uxtb r3, r3 8003516: 4619 mov r1, r3 8003518: 6878 ldr r0, [r7, #4] 800351a: f000 faf2 bl 8003b02 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 800351e: 6a7b ldr r3, [r7, #36] @ 0x24 8003520: 3301 adds r3, #1 8003522: 627b str r3, [r7, #36] @ 0x24 8003524: 687b ldr r3, [r7, #4] 8003526: 791b ldrb r3, [r3, #4] 8003528: 461a mov r2, r3 800352a: 6a7b ldr r3, [r7, #36] @ 0x24 800352c: 4293 cmp r3, r2 800352e: d3e4 bcc.n 80034fa } } } /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) 8003530: 687b ldr r3, [r7, #4] 8003532: 681b ldr r3, [r3, #0] 8003534: 4618 mov r0, r3 8003536: f004 fe75 bl 8008224 800353a: 4603 mov r3, r0 800353c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8003540: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8003544: d13c bne.n 80035c0 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003546: 2301 movs r3, #1 8003548: 627b str r3, [r7, #36] @ 0x24 800354a: e02b b.n 80035a4 { RegVal = USBx_INEP(epnum)->DIEPCTL; 800354c: 6a7b ldr r3, [r7, #36] @ 0x24 800354e: 015a lsls r2, r3, #5 8003550: 69fb ldr r3, [r7, #28] 8003552: 4413 add r3, r2 8003554: f503 6310 add.w r3, r3, #2304 @ 0x900 8003558: 681b ldr r3, [r3, #0] 800355a: 61bb str r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 800355c: 6879 ldr r1, [r7, #4] 800355e: 6a7a ldr r2, [r7, #36] @ 0x24 8003560: 4613 mov r3, r2 8003562: 00db lsls r3, r3, #3 8003564: 4413 add r3, r2 8003566: 009b lsls r3, r3, #2 8003568: 440b add r3, r1 800356a: 3318 adds r3, #24 800356c: 781b ldrb r3, [r3, #0] 800356e: 2b01 cmp r3, #1 8003570: d115 bne.n 800359e ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) 8003572: 69bb ldr r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 8003574: 2b00 cmp r3, #0 8003576: da12 bge.n 800359e { hpcd->IN_ep[epnum].is_iso_incomplete = 1U; 8003578: 6879 ldr r1, [r7, #4] 800357a: 6a7a ldr r2, [r7, #36] @ 0x24 800357c: 4613 mov r3, r2 800357e: 00db lsls r3, r3, #3 8003580: 4413 add r3, r2 8003582: 009b lsls r3, r3, #2 8003584: 440b add r3, r1 8003586: 3317 adds r3, #23 8003588: 2201 movs r2, #1 800358a: 701a strb r2, [r3, #0] /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); 800358c: 6a7b ldr r3, [r7, #36] @ 0x24 800358e: b2db uxtb r3, r3 8003590: f063 037f orn r3, r3, #127 @ 0x7f 8003594: b2db uxtb r3, r3 8003596: 4619 mov r1, r3 8003598: 6878 ldr r0, [r7, #4] 800359a: f000 fab2 bl 8003b02 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 800359e: 6a7b ldr r3, [r7, #36] @ 0x24 80035a0: 3301 adds r3, #1 80035a2: 627b str r3, [r7, #36] @ 0x24 80035a4: 687b ldr r3, [r7, #4] 80035a6: 791b ldrb r3, [r3, #4] 80035a8: 461a mov r2, r3 80035aa: 6a7b ldr r3, [r7, #36] @ 0x24 80035ac: 4293 cmp r3, r2 80035ae: d3cd bcc.n 800354c } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); 80035b0: 687b ldr r3, [r7, #4] 80035b2: 681b ldr r3, [r3, #0] 80035b4: 695a ldr r2, [r3, #20] 80035b6: 687b ldr r3, [r7, #4] 80035b8: 681b ldr r3, [r3, #0] 80035ba: f402 1280 and.w r2, r2, #1048576 @ 0x100000 80035be: 615a str r2, [r3, #20] } /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 80035c0: 687b ldr r3, [r7, #4] 80035c2: 681b ldr r3, [r3, #0] 80035c4: 4618 mov r0, r3 80035c6: f004 fe2d bl 8008224 80035ca: 4603 mov r3, r0 80035cc: f403 1300 and.w r3, r3, #2097152 @ 0x200000 80035d0: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80035d4: d156 bne.n 8003684 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80035d6: 2301 movs r3, #1 80035d8: 627b str r3, [r7, #36] @ 0x24 80035da: e045 b.n 8003668 { RegVal = USBx_OUTEP(epnum)->DOEPCTL; 80035dc: 6a7b ldr r3, [r7, #36] @ 0x24 80035de: 015a lsls r2, r3, #5 80035e0: 69fb ldr r3, [r7, #28] 80035e2: 4413 add r3, r2 80035e4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80035e8: 681b ldr r3, [r3, #0] 80035ea: 61bb str r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 80035ec: 6879 ldr r1, [r7, #4] 80035ee: 6a7a ldr r2, [r7, #36] @ 0x24 80035f0: 4613 mov r3, r2 80035f2: 00db lsls r3, r3, #3 80035f4: 4413 add r3, r2 80035f6: 009b lsls r3, r3, #2 80035f8: 440b add r3, r1 80035fa: f503 7316 add.w r3, r3, #600 @ 0x258 80035fe: 781b ldrb r3, [r3, #0] 8003600: 2b01 cmp r3, #1 8003602: d12e bne.n 8003662 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 8003604: 69bb ldr r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 8003606: 2b00 cmp r3, #0 8003608: da2b bge.n 8003662 (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) 800360a: 69bb ldr r3, [r7, #24] 800360c: 0c1a lsrs r2, r3, #16 800360e: 687b ldr r3, [r7, #4] 8003610: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4 8003614: 4053 eors r3, r2 8003616: f003 0301 and.w r3, r3, #1 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 800361a: 2b00 cmp r3, #0 800361c: d121 bne.n 8003662 { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; 800361e: 6879 ldr r1, [r7, #4] 8003620: 6a7a ldr r2, [r7, #36] @ 0x24 8003622: 4613 mov r3, r2 8003624: 00db lsls r3, r3, #3 8003626: 4413 add r3, r2 8003628: 009b lsls r3, r3, #2 800362a: 440b add r3, r1 800362c: f203 2357 addw r3, r3, #599 @ 0x257 8003630: 2201 movs r2, #1 8003632: 701a strb r2, [r3, #0] USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; 8003634: 6a3b ldr r3, [r7, #32] 8003636: 699b ldr r3, [r3, #24] 8003638: f043 0280 orr.w r2, r3, #128 @ 0x80 800363c: 6a3b ldr r3, [r7, #32] 800363e: 619a str r2, [r3, #24] if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) 8003640: 6a3b ldr r3, [r7, #32] 8003642: 695b ldr r3, [r3, #20] 8003644: f003 0380 and.w r3, r3, #128 @ 0x80 8003648: 2b00 cmp r3, #0 800364a: d10a bne.n 8003662 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; 800364c: 69fb ldr r3, [r7, #28] 800364e: f503 6300 add.w r3, r3, #2048 @ 0x800 8003652: 685b ldr r3, [r3, #4] 8003654: 69fa ldr r2, [r7, #28] 8003656: f502 6200 add.w r2, r2, #2048 @ 0x800 800365a: f443 7300 orr.w r3, r3, #512 @ 0x200 800365e: 6053 str r3, [r2, #4] break; 8003660: e008 b.n 8003674 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003662: 6a7b ldr r3, [r7, #36] @ 0x24 8003664: 3301 adds r3, #1 8003666: 627b str r3, [r7, #36] @ 0x24 8003668: 687b ldr r3, [r7, #4] 800366a: 791b ldrb r3, [r3, #4] 800366c: 461a mov r2, r3 800366e: 6a7b ldr r3, [r7, #36] @ 0x24 8003670: 4293 cmp r3, r2 8003672: d3b3 bcc.n 80035dc } } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 8003674: 687b ldr r3, [r7, #4] 8003676: 681b ldr r3, [r3, #0] 8003678: 695a ldr r2, [r3, #20] 800367a: 687b ldr r3, [r7, #4] 800367c: 681b ldr r3, [r3, #0] 800367e: f402 1200 and.w r2, r2, #2097152 @ 0x200000 8003682: 615a str r2, [r3, #20] } /* Handle Connection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) 8003684: 687b ldr r3, [r7, #4] 8003686: 681b ldr r3, [r3, #0] 8003688: 4618 mov r0, r3 800368a: f004 fdcb bl 8008224 800368e: 4603 mov r3, r0 8003690: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8003694: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8003698: d10a bne.n 80036b0 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ConnectCallback(hpcd); #else HAL_PCD_ConnectCallback(hpcd); 800369a: 6878 ldr r0, [r7, #4] 800369c: f006 ff26 bl 800a4ec #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); 80036a0: 687b ldr r3, [r7, #4] 80036a2: 681b ldr r3, [r3, #0] 80036a4: 695a ldr r2, [r3, #20] 80036a6: 687b ldr r3, [r7, #4] 80036a8: 681b ldr r3, [r3, #0] 80036aa: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 80036ae: 615a str r2, [r3, #20] } /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) 80036b0: 687b ldr r3, [r7, #4] 80036b2: 681b ldr r3, [r3, #0] 80036b4: 4618 mov r0, r3 80036b6: f004 fdb5 bl 8008224 80036ba: 4603 mov r3, r0 80036bc: f003 0304 and.w r3, r3, #4 80036c0: 2b04 cmp r3, #4 80036c2: d115 bne.n 80036f0 { RegVal = hpcd->Instance->GOTGINT; 80036c4: 687b ldr r3, [r7, #4] 80036c6: 681b ldr r3, [r3, #0] 80036c8: 685b ldr r3, [r3, #4] 80036ca: 61bb str r3, [r7, #24] if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) 80036cc: 69bb ldr r3, [r7, #24] 80036ce: f003 0304 and.w r3, r3, #4 80036d2: 2b00 cmp r3, #0 80036d4: d002 beq.n 80036dc { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); #else HAL_PCD_DisconnectCallback(hpcd); 80036d6: 6878 ldr r0, [r7, #4] 80036d8: f006 ff16 bl 800a508 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= RegVal; 80036dc: 687b ldr r3, [r7, #4] 80036de: 681b ldr r3, [r3, #0] 80036e0: 6859 ldr r1, [r3, #4] 80036e2: 687b ldr r3, [r7, #4] 80036e4: 681b ldr r3, [r3, #0] 80036e6: 69ba ldr r2, [r7, #24] 80036e8: 430a orrs r2, r1 80036ea: 605a str r2, [r3, #4] 80036ec: e000 b.n 80036f0 return; 80036ee: bf00 nop } } } 80036f0: 3734 adds r7, #52 @ 0x34 80036f2: 46bd mov sp, r7 80036f4: bd90 pop {r4, r7, pc} 080036f6 : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 80036f6: b580 push {r7, lr} 80036f8: b082 sub sp, #8 80036fa: af00 add r7, sp, #0 80036fc: 6078 str r0, [r7, #4] 80036fe: 460b mov r3, r1 8003700: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 8003702: 687b ldr r3, [r7, #4] 8003704: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003708: 2b01 cmp r3, #1 800370a: d101 bne.n 8003710 800370c: 2302 movs r3, #2 800370e: e012 b.n 8003736 8003710: 687b ldr r3, [r7, #4] 8003712: 2201 movs r2, #1 8003714: f883 2494 strb.w r2, [r3, #1172] @ 0x494 hpcd->USB_Address = address; 8003718: 687b ldr r3, [r7, #4] 800371a: 78fa ldrb r2, [r7, #3] 800371c: 745a strb r2, [r3, #17] (void)USB_SetDevAddress(hpcd->Instance, address); 800371e: 687b ldr r3, [r7, #4] 8003720: 681b ldr r3, [r3, #0] 8003722: 78fa ldrb r2, [r7, #3] 8003724: 4611 mov r1, r2 8003726: 4618 mov r0, r3 8003728: f004 fd14 bl 8008154 __HAL_UNLOCK(hpcd); 800372c: 687b ldr r3, [r7, #4] 800372e: 2200 movs r2, #0 8003730: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003734: 2300 movs r3, #0 } 8003736: 4618 mov r0, r3 8003738: 3708 adds r7, #8 800373a: 46bd mov sp, r7 800373c: bd80 pop {r7, pc} 0800373e : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 800373e: b580 push {r7, lr} 8003740: b084 sub sp, #16 8003742: af00 add r7, sp, #0 8003744: 6078 str r0, [r7, #4] 8003746: 4608 mov r0, r1 8003748: 4611 mov r1, r2 800374a: 461a mov r2, r3 800374c: 4603 mov r3, r0 800374e: 70fb strb r3, [r7, #3] 8003750: 460b mov r3, r1 8003752: 803b strh r3, [r7, #0] 8003754: 4613 mov r3, r2 8003756: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 8003758: 2300 movs r3, #0 800375a: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 800375c: f997 3003 ldrsb.w r3, [r7, #3] 8003760: 2b00 cmp r3, #0 8003762: da0f bge.n 8003784 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003764: 78fb ldrb r3, [r7, #3] 8003766: f003 020f and.w r2, r3, #15 800376a: 4613 mov r3, r2 800376c: 00db lsls r3, r3, #3 800376e: 4413 add r3, r2 8003770: 009b lsls r3, r3, #2 8003772: 3310 adds r3, #16 8003774: 687a ldr r2, [r7, #4] 8003776: 4413 add r3, r2 8003778: 3304 adds r3, #4 800377a: 60fb str r3, [r7, #12] ep->is_in = 1U; 800377c: 68fb ldr r3, [r7, #12] 800377e: 2201 movs r2, #1 8003780: 705a strb r2, [r3, #1] 8003782: e00f b.n 80037a4 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003784: 78fb ldrb r3, [r7, #3] 8003786: f003 020f and.w r2, r3, #15 800378a: 4613 mov r3, r2 800378c: 00db lsls r3, r3, #3 800378e: 4413 add r3, r2 8003790: 009b lsls r3, r3, #2 8003792: f503 7314 add.w r3, r3, #592 @ 0x250 8003796: 687a ldr r2, [r7, #4] 8003798: 4413 add r3, r2 800379a: 3304 adds r3, #4 800379c: 60fb str r3, [r7, #12] ep->is_in = 0U; 800379e: 68fb ldr r3, [r7, #12] 80037a0: 2200 movs r2, #0 80037a2: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 80037a4: 78fb ldrb r3, [r7, #3] 80037a6: f003 030f and.w r3, r3, #15 80037aa: b2da uxtb r2, r3 80037ac: 68fb ldr r3, [r7, #12] 80037ae: 701a strb r2, [r3, #0] ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; 80037b0: 883b ldrh r3, [r7, #0] 80037b2: f3c3 020a ubfx r2, r3, #0, #11 80037b6: 68fb ldr r3, [r7, #12] 80037b8: 609a str r2, [r3, #8] ep->type = ep_type; 80037ba: 68fb ldr r3, [r7, #12] 80037bc: 78ba ldrb r2, [r7, #2] 80037be: 711a strb r2, [r3, #4] if (ep->is_in != 0U) 80037c0: 68fb ldr r3, [r7, #12] 80037c2: 785b ldrb r3, [r3, #1] 80037c4: 2b00 cmp r3, #0 80037c6: d004 beq.n 80037d2 { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; 80037c8: 68fb ldr r3, [r7, #12] 80037ca: 781b ldrb r3, [r3, #0] 80037cc: 461a mov r2, r3 80037ce: 68fb ldr r3, [r7, #12] 80037d0: 835a strh r2, [r3, #26] } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 80037d2: 78bb ldrb r3, [r7, #2] 80037d4: 2b02 cmp r3, #2 80037d6: d102 bne.n 80037de { ep->data_pid_start = 0U; 80037d8: 68fb ldr r3, [r7, #12] 80037da: 2200 movs r2, #0 80037dc: 715a strb r2, [r3, #5] } __HAL_LOCK(hpcd); 80037de: 687b ldr r3, [r7, #4] 80037e0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 80037e4: 2b01 cmp r3, #1 80037e6: d101 bne.n 80037ec 80037e8: 2302 movs r3, #2 80037ea: e00e b.n 800380a 80037ec: 687b ldr r3, [r7, #4] 80037ee: 2201 movs r2, #1 80037f0: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_ActivateEndpoint(hpcd->Instance, ep); 80037f4: 687b ldr r3, [r7, #4] 80037f6: 681b ldr r3, [r3, #0] 80037f8: 68f9 ldr r1, [r7, #12] 80037fa: 4618 mov r0, r3 80037fc: f003 fe94 bl 8007528 __HAL_UNLOCK(hpcd); 8003800: 687b ldr r3, [r7, #4] 8003802: 2200 movs r2, #0 8003804: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return ret; 8003808: 7afb ldrb r3, [r7, #11] } 800380a: 4618 mov r0, r3 800380c: 3710 adds r7, #16 800380e: 46bd mov sp, r7 8003810: bd80 pop {r7, pc} 08003812 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003812: b580 push {r7, lr} 8003814: b084 sub sp, #16 8003816: af00 add r7, sp, #0 8003818: 6078 str r0, [r7, #4] 800381a: 460b mov r3, r1 800381c: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 800381e: f997 3003 ldrsb.w r3, [r7, #3] 8003822: 2b00 cmp r3, #0 8003824: da0f bge.n 8003846 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003826: 78fb ldrb r3, [r7, #3] 8003828: f003 020f and.w r2, r3, #15 800382c: 4613 mov r3, r2 800382e: 00db lsls r3, r3, #3 8003830: 4413 add r3, r2 8003832: 009b lsls r3, r3, #2 8003834: 3310 adds r3, #16 8003836: 687a ldr r2, [r7, #4] 8003838: 4413 add r3, r2 800383a: 3304 adds r3, #4 800383c: 60fb str r3, [r7, #12] ep->is_in = 1U; 800383e: 68fb ldr r3, [r7, #12] 8003840: 2201 movs r2, #1 8003842: 705a strb r2, [r3, #1] 8003844: e00f b.n 8003866 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003846: 78fb ldrb r3, [r7, #3] 8003848: f003 020f and.w r2, r3, #15 800384c: 4613 mov r3, r2 800384e: 00db lsls r3, r3, #3 8003850: 4413 add r3, r2 8003852: 009b lsls r3, r3, #2 8003854: f503 7314 add.w r3, r3, #592 @ 0x250 8003858: 687a ldr r2, [r7, #4] 800385a: 4413 add r3, r2 800385c: 3304 adds r3, #4 800385e: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003860: 68fb ldr r3, [r7, #12] 8003862: 2200 movs r2, #0 8003864: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8003866: 78fb ldrb r3, [r7, #3] 8003868: f003 030f and.w r3, r3, #15 800386c: b2da uxtb r2, r3 800386e: 68fb ldr r3, [r7, #12] 8003870: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003872: 687b ldr r3, [r7, #4] 8003874: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003878: 2b01 cmp r3, #1 800387a: d101 bne.n 8003880 800387c: 2302 movs r3, #2 800387e: e00e b.n 800389e 8003880: 687b ldr r3, [r7, #4] 8003882: 2201 movs r2, #1 8003884: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 8003888: 687b ldr r3, [r7, #4] 800388a: 681b ldr r3, [r3, #0] 800388c: 68f9 ldr r1, [r7, #12] 800388e: 4618 mov r0, r3 8003890: f003 fed2 bl 8007638 __HAL_UNLOCK(hpcd); 8003894: 687b ldr r3, [r7, #4] 8003896: 2200 movs r2, #0 8003898: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 800389c: 2300 movs r3, #0 } 800389e: 4618 mov r0, r3 80038a0: 3710 adds r7, #16 80038a2: 46bd mov sp, r7 80038a4: bd80 pop {r7, pc} 080038a6 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 80038a6: b580 push {r7, lr} 80038a8: b086 sub sp, #24 80038aa: af00 add r7, sp, #0 80038ac: 60f8 str r0, [r7, #12] 80038ae: 607a str r2, [r7, #4] 80038b0: 603b str r3, [r7, #0] 80038b2: 460b mov r3, r1 80038b4: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80038b6: 7afb ldrb r3, [r7, #11] 80038b8: f003 020f and.w r2, r3, #15 80038bc: 4613 mov r3, r2 80038be: 00db lsls r3, r3, #3 80038c0: 4413 add r3, r2 80038c2: 009b lsls r3, r3, #2 80038c4: f503 7314 add.w r3, r3, #592 @ 0x250 80038c8: 68fa ldr r2, [r7, #12] 80038ca: 4413 add r3, r2 80038cc: 3304 adds r3, #4 80038ce: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 80038d0: 697b ldr r3, [r7, #20] 80038d2: 687a ldr r2, [r7, #4] 80038d4: 60da str r2, [r3, #12] ep->xfer_len = len; 80038d6: 697b ldr r3, [r7, #20] 80038d8: 683a ldr r2, [r7, #0] 80038da: 611a str r2, [r3, #16] ep->xfer_count = 0U; 80038dc: 697b ldr r3, [r7, #20] 80038de: 2200 movs r2, #0 80038e0: 615a str r2, [r3, #20] ep->is_in = 0U; 80038e2: 697b ldr r3, [r7, #20] 80038e4: 2200 movs r2, #0 80038e6: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 80038e8: 7afb ldrb r3, [r7, #11] 80038ea: f003 030f and.w r3, r3, #15 80038ee: b2da uxtb r2, r3 80038f0: 697b ldr r3, [r7, #20] 80038f2: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 80038f4: 68fb ldr r3, [r7, #12] 80038f6: 799b ldrb r3, [r3, #6] 80038f8: 2b01 cmp r3, #1 80038fa: d102 bne.n 8003902 { ep->dma_addr = (uint32_t)pBuf; 80038fc: 687a ldr r2, [r7, #4] 80038fe: 697b ldr r3, [r7, #20] 8003900: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003902: 68fb ldr r3, [r7, #12] 8003904: 6818 ldr r0, [r3, #0] 8003906: 68fb ldr r3, [r7, #12] 8003908: 799b ldrb r3, [r3, #6] 800390a: 461a mov r2, r3 800390c: 6979 ldr r1, [r7, #20] 800390e: f003 ff6f bl 80077f0 return HAL_OK; 8003912: 2300 movs r3, #0 } 8003914: 4618 mov r0, r3 8003916: 3718 adds r7, #24 8003918: 46bd mov sp, r7 800391a: bd80 pop {r7, pc} 0800391c : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 800391c: b580 push {r7, lr} 800391e: b086 sub sp, #24 8003920: af00 add r7, sp, #0 8003922: 60f8 str r0, [r7, #12] 8003924: 607a str r2, [r7, #4] 8003926: 603b str r3, [r7, #0] 8003928: 460b mov r3, r1 800392a: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800392c: 7afb ldrb r3, [r7, #11] 800392e: f003 020f and.w r2, r3, #15 8003932: 4613 mov r3, r2 8003934: 00db lsls r3, r3, #3 8003936: 4413 add r3, r2 8003938: 009b lsls r3, r3, #2 800393a: 3310 adds r3, #16 800393c: 68fa ldr r2, [r7, #12] 800393e: 4413 add r3, r2 8003940: 3304 adds r3, #4 8003942: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003944: 697b ldr r3, [r7, #20] 8003946: 687a ldr r2, [r7, #4] 8003948: 60da str r2, [r3, #12] ep->xfer_len = len; 800394a: 697b ldr r3, [r7, #20] 800394c: 683a ldr r2, [r7, #0] 800394e: 611a str r2, [r3, #16] ep->xfer_count = 0U; 8003950: 697b ldr r3, [r7, #20] 8003952: 2200 movs r2, #0 8003954: 615a str r2, [r3, #20] ep->is_in = 1U; 8003956: 697b ldr r3, [r7, #20] 8003958: 2201 movs r2, #1 800395a: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 800395c: 7afb ldrb r3, [r7, #11] 800395e: f003 030f and.w r3, r3, #15 8003962: b2da uxtb r2, r3 8003964: 697b ldr r3, [r7, #20] 8003966: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003968: 68fb ldr r3, [r7, #12] 800396a: 799b ldrb r3, [r3, #6] 800396c: 2b01 cmp r3, #1 800396e: d102 bne.n 8003976 { ep->dma_addr = (uint32_t)pBuf; 8003970: 687a ldr r2, [r7, #4] 8003972: 697b ldr r3, [r7, #20] 8003974: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003976: 68fb ldr r3, [r7, #12] 8003978: 6818 ldr r0, [r3, #0] 800397a: 68fb ldr r3, [r7, #12] 800397c: 799b ldrb r3, [r3, #6] 800397e: 461a mov r2, r3 8003980: 6979 ldr r1, [r7, #20] 8003982: f003 ff35 bl 80077f0 return HAL_OK; 8003986: 2300 movs r3, #0 } 8003988: 4618 mov r0, r3 800398a: 3718 adds r7, #24 800398c: 46bd mov sp, r7 800398e: bd80 pop {r7, pc} 08003990 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003990: b580 push {r7, lr} 8003992: b084 sub sp, #16 8003994: af00 add r7, sp, #0 8003996: 6078 str r0, [r7, #4] 8003998: 460b mov r3, r1 800399a: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 800399c: 78fb ldrb r3, [r7, #3] 800399e: f003 030f and.w r3, r3, #15 80039a2: 687a ldr r2, [r7, #4] 80039a4: 7912 ldrb r2, [r2, #4] 80039a6: 4293 cmp r3, r2 80039a8: d901 bls.n 80039ae { return HAL_ERROR; 80039aa: 2301 movs r3, #1 80039ac: e04f b.n 8003a4e } if ((0x80U & ep_addr) == 0x80U) 80039ae: f997 3003 ldrsb.w r3, [r7, #3] 80039b2: 2b00 cmp r3, #0 80039b4: da0f bge.n 80039d6 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 80039b6: 78fb ldrb r3, [r7, #3] 80039b8: f003 020f and.w r2, r3, #15 80039bc: 4613 mov r3, r2 80039be: 00db lsls r3, r3, #3 80039c0: 4413 add r3, r2 80039c2: 009b lsls r3, r3, #2 80039c4: 3310 adds r3, #16 80039c6: 687a ldr r2, [r7, #4] 80039c8: 4413 add r3, r2 80039ca: 3304 adds r3, #4 80039cc: 60fb str r3, [r7, #12] ep->is_in = 1U; 80039ce: 68fb ldr r3, [r7, #12] 80039d0: 2201 movs r2, #1 80039d2: 705a strb r2, [r3, #1] 80039d4: e00d b.n 80039f2 } else { ep = &hpcd->OUT_ep[ep_addr]; 80039d6: 78fa ldrb r2, [r7, #3] 80039d8: 4613 mov r3, r2 80039da: 00db lsls r3, r3, #3 80039dc: 4413 add r3, r2 80039de: 009b lsls r3, r3, #2 80039e0: f503 7314 add.w r3, r3, #592 @ 0x250 80039e4: 687a ldr r2, [r7, #4] 80039e6: 4413 add r3, r2 80039e8: 3304 adds r3, #4 80039ea: 60fb str r3, [r7, #12] ep->is_in = 0U; 80039ec: 68fb ldr r3, [r7, #12] 80039ee: 2200 movs r2, #0 80039f0: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 80039f2: 68fb ldr r3, [r7, #12] 80039f4: 2201 movs r2, #1 80039f6: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 80039f8: 78fb ldrb r3, [r7, #3] 80039fa: f003 030f and.w r3, r3, #15 80039fe: b2da uxtb r2, r3 8003a00: 68fb ldr r3, [r7, #12] 8003a02: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003a04: 687b ldr r3, [r7, #4] 8003a06: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003a0a: 2b01 cmp r3, #1 8003a0c: d101 bne.n 8003a12 8003a0e: 2302 movs r3, #2 8003a10: e01d b.n 8003a4e 8003a12: 687b ldr r3, [r7, #4] 8003a14: 2201 movs r2, #1 8003a16: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPSetStall(hpcd->Instance, ep); 8003a1a: 687b ldr r3, [r7, #4] 8003a1c: 681b ldr r3, [r3, #0] 8003a1e: 68f9 ldr r1, [r7, #12] 8003a20: 4618 mov r0, r3 8003a22: f004 fac3 bl 8007fac if ((ep_addr & EP_ADDR_MSK) == 0U) 8003a26: 78fb ldrb r3, [r7, #3] 8003a28: f003 030f and.w r3, r3, #15 8003a2c: 2b00 cmp r3, #0 8003a2e: d109 bne.n 8003a44 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); 8003a30: 687b ldr r3, [r7, #4] 8003a32: 6818 ldr r0, [r3, #0] 8003a34: 687b ldr r3, [r7, #4] 8003a36: 7999 ldrb r1, [r3, #6] 8003a38: 687b ldr r3, [r7, #4] 8003a3a: f203 439c addw r3, r3, #1180 @ 0x49c 8003a3e: 461a mov r2, r3 8003a40: f004 fcb4 bl 80083ac } __HAL_UNLOCK(hpcd); 8003a44: 687b ldr r3, [r7, #4] 8003a46: 2200 movs r2, #0 8003a48: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003a4c: 2300 movs r3, #0 } 8003a4e: 4618 mov r0, r3 8003a50: 3710 adds r7, #16 8003a52: 46bd mov sp, r7 8003a54: bd80 pop {r7, pc} 08003a56 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003a56: b580 push {r7, lr} 8003a58: b084 sub sp, #16 8003a5a: af00 add r7, sp, #0 8003a5c: 6078 str r0, [r7, #4] 8003a5e: 460b mov r3, r1 8003a60: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8003a62: 78fb ldrb r3, [r7, #3] 8003a64: f003 030f and.w r3, r3, #15 8003a68: 687a ldr r2, [r7, #4] 8003a6a: 7912 ldrb r2, [r2, #4] 8003a6c: 4293 cmp r3, r2 8003a6e: d901 bls.n 8003a74 { return HAL_ERROR; 8003a70: 2301 movs r3, #1 8003a72: e042 b.n 8003afa } if ((0x80U & ep_addr) == 0x80U) 8003a74: f997 3003 ldrsb.w r3, [r7, #3] 8003a78: 2b00 cmp r3, #0 8003a7a: da0f bge.n 8003a9c { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003a7c: 78fb ldrb r3, [r7, #3] 8003a7e: f003 020f and.w r2, r3, #15 8003a82: 4613 mov r3, r2 8003a84: 00db lsls r3, r3, #3 8003a86: 4413 add r3, r2 8003a88: 009b lsls r3, r3, #2 8003a8a: 3310 adds r3, #16 8003a8c: 687a ldr r2, [r7, #4] 8003a8e: 4413 add r3, r2 8003a90: 3304 adds r3, #4 8003a92: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003a94: 68fb ldr r3, [r7, #12] 8003a96: 2201 movs r2, #1 8003a98: 705a strb r2, [r3, #1] 8003a9a: e00f b.n 8003abc } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003a9c: 78fb ldrb r3, [r7, #3] 8003a9e: f003 020f and.w r2, r3, #15 8003aa2: 4613 mov r3, r2 8003aa4: 00db lsls r3, r3, #3 8003aa6: 4413 add r3, r2 8003aa8: 009b lsls r3, r3, #2 8003aaa: f503 7314 add.w r3, r3, #592 @ 0x250 8003aae: 687a ldr r2, [r7, #4] 8003ab0: 4413 add r3, r2 8003ab2: 3304 adds r3, #4 8003ab4: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003ab6: 68fb ldr r3, [r7, #12] 8003ab8: 2200 movs r2, #0 8003aba: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8003abc: 68fb ldr r3, [r7, #12] 8003abe: 2200 movs r2, #0 8003ac0: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003ac2: 78fb ldrb r3, [r7, #3] 8003ac4: f003 030f and.w r3, r3, #15 8003ac8: b2da uxtb r2, r3 8003aca: 68fb ldr r3, [r7, #12] 8003acc: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003ace: 687b ldr r3, [r7, #4] 8003ad0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003ad4: 2b01 cmp r3, #1 8003ad6: d101 bne.n 8003adc 8003ad8: 2302 movs r3, #2 8003ada: e00e b.n 8003afa 8003adc: 687b ldr r3, [r7, #4] 8003ade: 2201 movs r2, #1 8003ae0: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPClearStall(hpcd->Instance, ep); 8003ae4: 687b ldr r3, [r7, #4] 8003ae6: 681b ldr r3, [r3, #0] 8003ae8: 68f9 ldr r1, [r7, #12] 8003aea: 4618 mov r0, r3 8003aec: f004 facc bl 8008088 __HAL_UNLOCK(hpcd); 8003af0: 687b ldr r3, [r7, #4] 8003af2: 2200 movs r2, #0 8003af4: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003af8: 2300 movs r3, #0 } 8003afa: 4618 mov r0, r3 8003afc: 3710 adds r7, #16 8003afe: 46bd mov sp, r7 8003b00: bd80 pop {r7, pc} 08003b02 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003b02: b580 push {r7, lr} 8003b04: b084 sub sp, #16 8003b06: af00 add r7, sp, #0 8003b08: 6078 str r0, [r7, #4] 8003b0a: 460b mov r3, r1 8003b0c: 70fb strb r3, [r7, #3] HAL_StatusTypeDef ret; PCD_EPTypeDef *ep; if ((0x80U & ep_addr) == 0x80U) 8003b0e: f997 3003 ldrsb.w r3, [r7, #3] 8003b12: 2b00 cmp r3, #0 8003b14: da0c bge.n 8003b30 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003b16: 78fb ldrb r3, [r7, #3] 8003b18: f003 020f and.w r2, r3, #15 8003b1c: 4613 mov r3, r2 8003b1e: 00db lsls r3, r3, #3 8003b20: 4413 add r3, r2 8003b22: 009b lsls r3, r3, #2 8003b24: 3310 adds r3, #16 8003b26: 687a ldr r2, [r7, #4] 8003b28: 4413 add r3, r2 8003b2a: 3304 adds r3, #4 8003b2c: 60fb str r3, [r7, #12] 8003b2e: e00c b.n 8003b4a } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003b30: 78fb ldrb r3, [r7, #3] 8003b32: f003 020f and.w r2, r3, #15 8003b36: 4613 mov r3, r2 8003b38: 00db lsls r3, r3, #3 8003b3a: 4413 add r3, r2 8003b3c: 009b lsls r3, r3, #2 8003b3e: f503 7314 add.w r3, r3, #592 @ 0x250 8003b42: 687a ldr r2, [r7, #4] 8003b44: 4413 add r3, r2 8003b46: 3304 adds r3, #4 8003b48: 60fb str r3, [r7, #12] } /* Stop Xfer */ ret = USB_EPStopXfer(hpcd->Instance, ep); 8003b4a: 687b ldr r3, [r7, #4] 8003b4c: 681b ldr r3, [r3, #0] 8003b4e: 68f9 ldr r1, [r7, #12] 8003b50: 4618 mov r0, r3 8003b52: f004 f8eb bl 8007d2c 8003b56: 4603 mov r3, r0 8003b58: 72fb strb r3, [r7, #11] return ret; 8003b5a: 7afb ldrb r3, [r7, #11] } 8003b5c: 4618 mov r0, r3 8003b5e: 3710 adds r7, #16 8003b60: 46bd mov sp, r7 8003b62: bd80 pop {r7, pc} 08003b64 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003b64: b580 push {r7, lr} 8003b66: b08a sub sp, #40 @ 0x28 8003b68: af02 add r7, sp, #8 8003b6a: 6078 str r0, [r7, #4] 8003b6c: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003b6e: 687b ldr r3, [r7, #4] 8003b70: 681b ldr r3, [r3, #0] 8003b72: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003b74: 697b ldr r3, [r7, #20] 8003b76: 613b str r3, [r7, #16] USB_OTG_EPTypeDef *ep; uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; 8003b78: 683a ldr r2, [r7, #0] 8003b7a: 4613 mov r3, r2 8003b7c: 00db lsls r3, r3, #3 8003b7e: 4413 add r3, r2 8003b80: 009b lsls r3, r3, #2 8003b82: 3310 adds r3, #16 8003b84: 687a ldr r2, [r7, #4] 8003b86: 4413 add r3, r2 8003b88: 3304 adds r3, #4 8003b8a: 60fb str r3, [r7, #12] if (ep->xfer_count > ep->xfer_len) 8003b8c: 68fb ldr r3, [r7, #12] 8003b8e: 695a ldr r2, [r3, #20] 8003b90: 68fb ldr r3, [r7, #12] 8003b92: 691b ldr r3, [r3, #16] 8003b94: 429a cmp r2, r3 8003b96: d901 bls.n 8003b9c { return HAL_ERROR; 8003b98: 2301 movs r3, #1 8003b9a: e06b b.n 8003c74 } len = ep->xfer_len - ep->xfer_count; 8003b9c: 68fb ldr r3, [r7, #12] 8003b9e: 691a ldr r2, [r3, #16] 8003ba0: 68fb ldr r3, [r7, #12] 8003ba2: 695b ldr r3, [r3, #20] 8003ba4: 1ad3 subs r3, r2, r3 8003ba6: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8003ba8: 68fb ldr r3, [r7, #12] 8003baa: 689b ldr r3, [r3, #8] 8003bac: 69fa ldr r2, [r7, #28] 8003bae: 429a cmp r2, r3 8003bb0: d902 bls.n 8003bb8 { len = ep->maxpacket; 8003bb2: 68fb ldr r3, [r7, #12] 8003bb4: 689b ldr r3, [r3, #8] 8003bb6: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8003bb8: 69fb ldr r3, [r7, #28] 8003bba: 3303 adds r3, #3 8003bbc: 089b lsrs r3, r3, #2 8003bbe: 61bb str r3, [r7, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003bc0: e02a b.n 8003c18 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; 8003bc2: 68fb ldr r3, [r7, #12] 8003bc4: 691a ldr r2, [r3, #16] 8003bc6: 68fb ldr r3, [r7, #12] 8003bc8: 695b ldr r3, [r3, #20] 8003bca: 1ad3 subs r3, r2, r3 8003bcc: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8003bce: 68fb ldr r3, [r7, #12] 8003bd0: 689b ldr r3, [r3, #8] 8003bd2: 69fa ldr r2, [r7, #28] 8003bd4: 429a cmp r2, r3 8003bd6: d902 bls.n 8003bde { len = ep->maxpacket; 8003bd8: 68fb ldr r3, [r7, #12] 8003bda: 689b ldr r3, [r3, #8] 8003bdc: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8003bde: 69fb ldr r3, [r7, #28] 8003be0: 3303 adds r3, #3 8003be2: 089b lsrs r3, r3, #2 8003be4: 61bb str r3, [r7, #24] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8003be6: 68fb ldr r3, [r7, #12] 8003be8: 68d9 ldr r1, [r3, #12] 8003bea: 683b ldr r3, [r7, #0] 8003bec: b2da uxtb r2, r3 8003bee: 69fb ldr r3, [r7, #28] 8003bf0: b298 uxth r0, r3 (uint8_t)hpcd->Init.dma_enable); 8003bf2: 687b ldr r3, [r7, #4] 8003bf4: 799b ldrb r3, [r3, #6] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8003bf6: 9300 str r3, [sp, #0] 8003bf8: 4603 mov r3, r0 8003bfa: 6978 ldr r0, [r7, #20] 8003bfc: f004 f940 bl 8007e80 ep->xfer_buff += len; 8003c00: 68fb ldr r3, [r7, #12] 8003c02: 68da ldr r2, [r3, #12] 8003c04: 69fb ldr r3, [r7, #28] 8003c06: 441a add r2, r3 8003c08: 68fb ldr r3, [r7, #12] 8003c0a: 60da str r2, [r3, #12] ep->xfer_count += len; 8003c0c: 68fb ldr r3, [r7, #12] 8003c0e: 695a ldr r2, [r3, #20] 8003c10: 69fb ldr r3, [r7, #28] 8003c12: 441a add r2, r3 8003c14: 68fb ldr r3, [r7, #12] 8003c16: 615a str r2, [r3, #20] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003c18: 683b ldr r3, [r7, #0] 8003c1a: 015a lsls r2, r3, #5 8003c1c: 693b ldr r3, [r7, #16] 8003c1e: 4413 add r3, r2 8003c20: f503 6310 add.w r3, r3, #2304 @ 0x900 8003c24: 699b ldr r3, [r3, #24] 8003c26: b29b uxth r3, r3 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8003c28: 69ba ldr r2, [r7, #24] 8003c2a: 429a cmp r2, r3 8003c2c: d809 bhi.n 8003c42 8003c2e: 68fb ldr r3, [r7, #12] 8003c30: 695a ldr r2, [r3, #20] 8003c32: 68fb ldr r3, [r7, #12] 8003c34: 691b ldr r3, [r3, #16] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003c36: 429a cmp r2, r3 8003c38: d203 bcs.n 8003c42 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8003c3a: 68fb ldr r3, [r7, #12] 8003c3c: 691b ldr r3, [r3, #16] 8003c3e: 2b00 cmp r3, #0 8003c40: d1bf bne.n 8003bc2 } if (ep->xfer_len <= ep->xfer_count) 8003c42: 68fb ldr r3, [r7, #12] 8003c44: 691a ldr r2, [r3, #16] 8003c46: 68fb ldr r3, [r7, #12] 8003c48: 695b ldr r3, [r3, #20] 8003c4a: 429a cmp r2, r3 8003c4c: d811 bhi.n 8003c72 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8003c4e: 683b ldr r3, [r7, #0] 8003c50: f003 030f and.w r3, r3, #15 8003c54: 2201 movs r2, #1 8003c56: fa02 f303 lsl.w r3, r2, r3 8003c5a: 60bb str r3, [r7, #8] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8003c5c: 693b ldr r3, [r7, #16] 8003c5e: f503 6300 add.w r3, r3, #2048 @ 0x800 8003c62: 6b5a ldr r2, [r3, #52] @ 0x34 8003c64: 68bb ldr r3, [r7, #8] 8003c66: 43db mvns r3, r3 8003c68: 6939 ldr r1, [r7, #16] 8003c6a: f501 6100 add.w r1, r1, #2048 @ 0x800 8003c6e: 4013 ands r3, r2 8003c70: 634b str r3, [r1, #52] @ 0x34 } return HAL_OK; 8003c72: 2300 movs r3, #0 } 8003c74: 4618 mov r0, r3 8003c76: 3720 adds r7, #32 8003c78: 46bd mov sp, r7 8003c7a: bd80 pop {r7, pc} 08003c7c : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003c7c: b580 push {r7, lr} 8003c7e: b088 sub sp, #32 8003c80: af00 add r7, sp, #0 8003c82: 6078 str r0, [r7, #4] 8003c84: 6039 str r1, [r7, #0] USB_OTG_EPTypeDef *ep; const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003c86: 687b ldr r3, [r7, #4] 8003c88: 681b ldr r3, [r3, #0] 8003c8a: 61fb str r3, [r7, #28] uint32_t USBx_BASE = (uint32_t)USBx; 8003c8c: 69fb ldr r3, [r7, #28] 8003c8e: 61bb str r3, [r7, #24] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8003c90: 69fb ldr r3, [r7, #28] 8003c92: 333c adds r3, #60 @ 0x3c 8003c94: 3304 adds r3, #4 8003c96: 681b ldr r3, [r3, #0] 8003c98: 617b str r3, [r7, #20] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003c9a: 683b ldr r3, [r7, #0] 8003c9c: 015a lsls r2, r3, #5 8003c9e: 69bb ldr r3, [r7, #24] 8003ca0: 4413 add r3, r2 8003ca2: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003ca6: 689b ldr r3, [r3, #8] 8003ca8: 613b str r3, [r7, #16] if (hpcd->Init.dma_enable == 1U) 8003caa: 687b ldr r3, [r7, #4] 8003cac: 799b ldrb r3, [r3, #6] 8003cae: 2b01 cmp r3, #1 8003cb0: d17b bne.n 8003daa { if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ 8003cb2: 693b ldr r3, [r7, #16] 8003cb4: f003 0308 and.w r3, r3, #8 8003cb8: 2b00 cmp r3, #0 8003cba: d015 beq.n 8003ce8 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003cbc: 697b ldr r3, [r7, #20] 8003cbe: 4a61 ldr r2, [pc, #388] @ (8003e44 ) 8003cc0: 4293 cmp r3, r2 8003cc2: f240 80b9 bls.w 8003e38 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003cc6: 693b ldr r3, [r7, #16] 8003cc8: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003ccc: 2b00 cmp r3, #0 8003cce: f000 80b3 beq.w 8003e38 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003cd2: 683b ldr r3, [r7, #0] 8003cd4: 015a lsls r2, r3, #5 8003cd6: 69bb ldr r3, [r7, #24] 8003cd8: 4413 add r3, r2 8003cda: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003cde: 461a mov r2, r3 8003ce0: f44f 4300 mov.w r3, #32768 @ 0x8000 8003ce4: 6093 str r3, [r2, #8] 8003ce6: e0a7 b.n 8003e38 } } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ 8003ce8: 693b ldr r3, [r7, #16] 8003cea: f003 0320 and.w r3, r3, #32 8003cee: 2b00 cmp r3, #0 8003cf0: d009 beq.n 8003d06 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003cf2: 683b ldr r3, [r7, #0] 8003cf4: 015a lsls r2, r3, #5 8003cf6: 69bb ldr r3, [r7, #24] 8003cf8: 4413 add r3, r2 8003cfa: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003cfe: 461a mov r2, r3 8003d00: 2320 movs r3, #32 8003d02: 6093 str r3, [r2, #8] 8003d04: e098 b.n 8003e38 } else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) 8003d06: 693b ldr r3, [r7, #16] 8003d08: f003 0328 and.w r3, r3, #40 @ 0x28 8003d0c: 2b00 cmp r3, #0 8003d0e: f040 8093 bne.w 8003e38 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003d12: 697b ldr r3, [r7, #20] 8003d14: 4a4b ldr r2, [pc, #300] @ (8003e44 ) 8003d16: 4293 cmp r3, r2 8003d18: d90f bls.n 8003d3a ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003d1a: 693b ldr r3, [r7, #16] 8003d1c: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003d20: 2b00 cmp r3, #0 8003d22: d00a beq.n 8003d3a { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003d24: 683b ldr r3, [r7, #0] 8003d26: 015a lsls r2, r3, #5 8003d28: 69bb ldr r3, [r7, #24] 8003d2a: 4413 add r3, r2 8003d2c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003d30: 461a mov r2, r3 8003d32: f44f 4300 mov.w r3, #32768 @ 0x8000 8003d36: 6093 str r3, [r2, #8] 8003d38: e07e b.n 8003e38 } else { ep = &hpcd->OUT_ep[epnum]; 8003d3a: 683a ldr r2, [r7, #0] 8003d3c: 4613 mov r3, r2 8003d3e: 00db lsls r3, r3, #3 8003d40: 4413 add r3, r2 8003d42: 009b lsls r3, r3, #2 8003d44: f503 7314 add.w r3, r3, #592 @ 0x250 8003d48: 687a ldr r2, [r7, #4] 8003d4a: 4413 add r3, r2 8003d4c: 3304 adds r3, #4 8003d4e: 60fb str r3, [r7, #12] /* out data packet received over EP */ ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 8003d50: 68fb ldr r3, [r7, #12] 8003d52: 6a1a ldr r2, [r3, #32] 8003d54: 683b ldr r3, [r7, #0] 8003d56: 0159 lsls r1, r3, #5 8003d58: 69bb ldr r3, [r7, #24] 8003d5a: 440b add r3, r1 8003d5c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003d60: 691b ldr r3, [r3, #16] 8003d62: f3c3 0312 ubfx r3, r3, #0, #19 8003d66: 1ad2 subs r2, r2, r3 8003d68: 68fb ldr r3, [r7, #12] 8003d6a: 615a str r2, [r3, #20] if (epnum == 0U) 8003d6c: 683b ldr r3, [r7, #0] 8003d6e: 2b00 cmp r3, #0 8003d70: d114 bne.n 8003d9c { if (ep->xfer_len == 0U) 8003d72: 68fb ldr r3, [r7, #12] 8003d74: 691b ldr r3, [r3, #16] 8003d76: 2b00 cmp r3, #0 8003d78: d109 bne.n 8003d8e { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003d7a: 687b ldr r3, [r7, #4] 8003d7c: 6818 ldr r0, [r3, #0] 8003d7e: 687b ldr r3, [r7, #4] 8003d80: f203 439c addw r3, r3, #1180 @ 0x49c 8003d84: 461a mov r2, r3 8003d86: 2101 movs r1, #1 8003d88: f004 fb10 bl 80083ac 8003d8c: e006 b.n 8003d9c } else { ep->xfer_buff += ep->xfer_count; 8003d8e: 68fb ldr r3, [r7, #12] 8003d90: 68da ldr r2, [r3, #12] 8003d92: 68fb ldr r3, [r7, #12] 8003d94: 695b ldr r3, [r3, #20] 8003d96: 441a add r2, r3 8003d98: 68fb ldr r3, [r7, #12] 8003d9a: 60da str r2, [r3, #12] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003d9c: 683b ldr r3, [r7, #0] 8003d9e: b2db uxtb r3, r3 8003da0: 4619 mov r1, r3 8003da2: 6878 ldr r0, [r7, #4] 8003da4: f006 fade bl 800a364 8003da8: e046 b.n 8003e38 /* ... */ } } else { if (gSNPSiD == USB_OTG_CORE_ID_310A) 8003daa: 697b ldr r3, [r7, #20] 8003dac: 4a26 ldr r2, [pc, #152] @ (8003e48 ) 8003dae: 4293 cmp r3, r2 8003db0: d124 bne.n 8003dfc { /* StupPktRcvd = 1 this is a setup packet */ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) 8003db2: 693b ldr r3, [r7, #16] 8003db4: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003db8: 2b00 cmp r3, #0 8003dba: d00a beq.n 8003dd2 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003dbc: 683b ldr r3, [r7, #0] 8003dbe: 015a lsls r2, r3, #5 8003dc0: 69bb ldr r3, [r7, #24] 8003dc2: 4413 add r3, r2 8003dc4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003dc8: 461a mov r2, r3 8003dca: f44f 4300 mov.w r3, #32768 @ 0x8000 8003dce: 6093 str r3, [r2, #8] 8003dd0: e032 b.n 8003e38 } else { if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8003dd2: 693b ldr r3, [r7, #16] 8003dd4: f003 0320 and.w r3, r3, #32 8003dd8: 2b00 cmp r3, #0 8003dda: d008 beq.n 8003dee { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003ddc: 683b ldr r3, [r7, #0] 8003dde: 015a lsls r2, r3, #5 8003de0: 69bb ldr r3, [r7, #24] 8003de2: 4413 add r3, r2 8003de4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003de8: 461a mov r2, r3 8003dea: 2320 movs r3, #32 8003dec: 6093 str r3, [r2, #8] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003dee: 683b ldr r3, [r7, #0] 8003df0: b2db uxtb r3, r3 8003df2: 4619 mov r1, r3 8003df4: 6878 ldr r0, [r7, #4] 8003df6: f006 fab5 bl 800a364 8003dfa: e01d b.n 8003e38 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else { if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8003dfc: 683b ldr r3, [r7, #0] 8003dfe: 2b00 cmp r3, #0 8003e00: d114 bne.n 8003e2c 8003e02: 6879 ldr r1, [r7, #4] 8003e04: 683a ldr r2, [r7, #0] 8003e06: 4613 mov r3, r2 8003e08: 00db lsls r3, r3, #3 8003e0a: 4413 add r3, r2 8003e0c: 009b lsls r3, r3, #2 8003e0e: 440b add r3, r1 8003e10: f503 7319 add.w r3, r3, #612 @ 0x264 8003e14: 681b ldr r3, [r3, #0] 8003e16: 2b00 cmp r3, #0 8003e18: d108 bne.n 8003e2c { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); 8003e1a: 687b ldr r3, [r7, #4] 8003e1c: 6818 ldr r0, [r3, #0] 8003e1e: 687b ldr r3, [r7, #4] 8003e20: f203 439c addw r3, r3, #1180 @ 0x49c 8003e24: 461a mov r2, r3 8003e26: 2100 movs r1, #0 8003e28: f004 fac0 bl 80083ac } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003e2c: 683b ldr r3, [r7, #0] 8003e2e: b2db uxtb r3, r3 8003e30: 4619 mov r1, r3 8003e32: 6878 ldr r0, [r7, #4] 8003e34: f006 fa96 bl 800a364 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } return HAL_OK; 8003e38: 2300 movs r3, #0 } 8003e3a: 4618 mov r0, r3 8003e3c: 3720 adds r7, #32 8003e3e: 46bd mov sp, r7 8003e40: bd80 pop {r7, pc} 8003e42: bf00 nop 8003e44: 4f54300a .word 0x4f54300a 8003e48: 4f54310a .word 0x4f54310a 08003e4c : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003e4c: b580 push {r7, lr} 8003e4e: b086 sub sp, #24 8003e50: af00 add r7, sp, #0 8003e52: 6078 str r0, [r7, #4] 8003e54: 6039 str r1, [r7, #0] const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003e56: 687b ldr r3, [r7, #4] 8003e58: 681b ldr r3, [r3, #0] 8003e5a: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003e5c: 697b ldr r3, [r7, #20] 8003e5e: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8003e60: 697b ldr r3, [r7, #20] 8003e62: 333c adds r3, #60 @ 0x3c 8003e64: 3304 adds r3, #4 8003e66: 681b ldr r3, [r3, #0] 8003e68: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003e6a: 683b ldr r3, [r7, #0] 8003e6c: 015a lsls r2, r3, #5 8003e6e: 693b ldr r3, [r7, #16] 8003e70: 4413 add r3, r2 8003e72: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003e76: 689b ldr r3, [r3, #8] 8003e78: 60bb str r3, [r7, #8] if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003e7a: 68fb ldr r3, [r7, #12] 8003e7c: 4a15 ldr r2, [pc, #84] @ (8003ed4 ) 8003e7e: 4293 cmp r3, r2 8003e80: d90e bls.n 8003ea0 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003e82: 68bb ldr r3, [r7, #8] 8003e84: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003e88: 2b00 cmp r3, #0 8003e8a: d009 beq.n 8003ea0 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003e8c: 683b ldr r3, [r7, #0] 8003e8e: 015a lsls r2, r3, #5 8003e90: 693b ldr r3, [r7, #16] 8003e92: 4413 add r3, r2 8003e94: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003e98: 461a mov r2, r3 8003e9a: f44f 4300 mov.w r3, #32768 @ 0x8000 8003e9e: 6093 str r3, [r2, #8] /* Inform the upper layer that a setup packet is available */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 8003ea0: 6878 ldr r0, [r7, #4] 8003ea2: f006 fa4d bl 800a340 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) 8003ea6: 68fb ldr r3, [r7, #12] 8003ea8: 4a0a ldr r2, [pc, #40] @ (8003ed4 ) 8003eaa: 4293 cmp r3, r2 8003eac: d90c bls.n 8003ec8 8003eae: 687b ldr r3, [r7, #4] 8003eb0: 799b ldrb r3, [r3, #6] 8003eb2: 2b01 cmp r3, #1 8003eb4: d108 bne.n 8003ec8 { (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003eb6: 687b ldr r3, [r7, #4] 8003eb8: 6818 ldr r0, [r3, #0] 8003eba: 687b ldr r3, [r7, #4] 8003ebc: f203 439c addw r3, r3, #1180 @ 0x49c 8003ec0: 461a mov r2, r3 8003ec2: 2101 movs r1, #1 8003ec4: f004 fa72 bl 80083ac } return HAL_OK; 8003ec8: 2300 movs r3, #0 } 8003eca: 4618 mov r0, r3 8003ecc: 3718 adds r7, #24 8003ece: 46bd mov sp, r7 8003ed0: bd80 pop {r7, pc} 8003ed2: bf00 nop 8003ed4: 4f54300a .word 0x4f54300a 08003ed8 : * @param fifo The number of Tx fifo * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { 8003ed8: b480 push {r7} 8003eda: b085 sub sp, #20 8003edc: af00 add r7, sp, #0 8003ede: 6078 str r0, [r7, #4] 8003ee0: 460b mov r3, r1 8003ee2: 70fb strb r3, [r7, #3] 8003ee4: 4613 mov r3, r2 8003ee6: 803b strh r3, [r7, #0] --> Txn should be configured with the minimum space of 16 words The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ Tx_Offset = hpcd->Instance->GRXFSIZ; 8003ee8: 687b ldr r3, [r7, #4] 8003eea: 681b ldr r3, [r3, #0] 8003eec: 6a5b ldr r3, [r3, #36] @ 0x24 8003eee: 60bb str r3, [r7, #8] if (fifo == 0U) 8003ef0: 78fb ldrb r3, [r7, #3] 8003ef2: 2b00 cmp r3, #0 8003ef4: d107 bne.n 8003f06 { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; 8003ef6: 883b ldrh r3, [r7, #0] 8003ef8: 0419 lsls r1, r3, #16 8003efa: 687b ldr r3, [r7, #4] 8003efc: 681b ldr r3, [r3, #0] 8003efe: 68ba ldr r2, [r7, #8] 8003f00: 430a orrs r2, r1 8003f02: 629a str r2, [r3, #40] @ 0x28 8003f04: e028 b.n 8003f58 } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; 8003f06: 687b ldr r3, [r7, #4] 8003f08: 681b ldr r3, [r3, #0] 8003f0a: 6a9b ldr r3, [r3, #40] @ 0x28 8003f0c: 0c1b lsrs r3, r3, #16 8003f0e: 68ba ldr r2, [r7, #8] 8003f10: 4413 add r3, r2 8003f12: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8003f14: 2300 movs r3, #0 8003f16: 73fb strb r3, [r7, #15] 8003f18: e00d b.n 8003f36 { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); 8003f1a: 687b ldr r3, [r7, #4] 8003f1c: 681a ldr r2, [r3, #0] 8003f1e: 7bfb ldrb r3, [r7, #15] 8003f20: 3340 adds r3, #64 @ 0x40 8003f22: 009b lsls r3, r3, #2 8003f24: 4413 add r3, r2 8003f26: 685b ldr r3, [r3, #4] 8003f28: 0c1b lsrs r3, r3, #16 8003f2a: 68ba ldr r2, [r7, #8] 8003f2c: 4413 add r3, r2 8003f2e: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8003f30: 7bfb ldrb r3, [r7, #15] 8003f32: 3301 adds r3, #1 8003f34: 73fb strb r3, [r7, #15] 8003f36: 7bfa ldrb r2, [r7, #15] 8003f38: 78fb ldrb r3, [r7, #3] 8003f3a: 3b01 subs r3, #1 8003f3c: 429a cmp r2, r3 8003f3e: d3ec bcc.n 8003f1a } /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; 8003f40: 883b ldrh r3, [r7, #0] 8003f42: 0418 lsls r0, r3, #16 8003f44: 687b ldr r3, [r7, #4] 8003f46: 6819 ldr r1, [r3, #0] 8003f48: 78fb ldrb r3, [r7, #3] 8003f4a: 3b01 subs r3, #1 8003f4c: 68ba ldr r2, [r7, #8] 8003f4e: 4302 orrs r2, r0 8003f50: 3340 adds r3, #64 @ 0x40 8003f52: 009b lsls r3, r3, #2 8003f54: 440b add r3, r1 8003f56: 605a str r2, [r3, #4] } return HAL_OK; 8003f58: 2300 movs r3, #0 } 8003f5a: 4618 mov r0, r3 8003f5c: 3714 adds r7, #20 8003f5e: 46bd mov sp, r7 8003f60: f85d 7b04 ldr.w r7, [sp], #4 8003f64: 4770 bx lr 08003f66 : * @param hpcd PCD handle * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { 8003f66: b480 push {r7} 8003f68: b083 sub sp, #12 8003f6a: af00 add r7, sp, #0 8003f6c: 6078 str r0, [r7, #4] 8003f6e: 460b mov r3, r1 8003f70: 807b strh r3, [r7, #2] hpcd->Instance->GRXFSIZ = size; 8003f72: 687b ldr r3, [r7, #4] 8003f74: 681b ldr r3, [r3, #0] 8003f76: 887a ldrh r2, [r7, #2] 8003f78: 625a str r2, [r3, #36] @ 0x24 return HAL_OK; 8003f7a: 2300 movs r3, #0 } 8003f7c: 4618 mov r0, r3 8003f7e: 370c adds r7, #12 8003f80: 46bd mov sp, r7 8003f82: f85d 7b04 ldr.w r7, [sp], #4 8003f86: 4770 bx lr 08003f88 : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 8003f88: b480 push {r7} 8003f8a: b085 sub sp, #20 8003f8c: af00 add r7, sp, #0 8003f8e: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003f90: 687b ldr r3, [r7, #4] 8003f92: 681b ldr r3, [r3, #0] 8003f94: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 8003f96: 687b ldr r3, [r7, #4] 8003f98: 2201 movs r2, #1 8003f9a: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8 hpcd->LPM_State = LPM_L0; 8003f9e: 687b ldr r3, [r7, #4] 8003fa0: 2200 movs r2, #0 8003fa2: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 8003fa6: 68fb ldr r3, [r7, #12] 8003fa8: 699b ldr r3, [r3, #24] 8003faa: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 8003fae: 68fb ldr r3, [r7, #12] 8003fb0: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 8003fb2: 68fb ldr r3, [r7, #12] 8003fb4: 6d5b ldr r3, [r3, #84] @ 0x54 8003fb6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003fba: f043 0303 orr.w r3, r3, #3 8003fbe: 68fa ldr r2, [r7, #12] 8003fc0: 6553 str r3, [r2, #84] @ 0x54 return HAL_OK; 8003fc2: 2300 movs r3, #0 } 8003fc4: 4618 mov r0, r3 8003fc6: 3714 adds r7, #20 8003fc8: 46bd mov sp, r7 8003fca: f85d 7b04 ldr.w r7, [sp], #4 8003fce: 4770 bx lr 08003fd0 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003fd0: b580 push {r7, lr} 8003fd2: b084 sub sp, #16 8003fd4: af00 add r7, sp, #0 8003fd6: 6078 str r0, [r7, #4] 8003fd8: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8003fda: 687b ldr r3, [r7, #4] 8003fdc: 2b00 cmp r3, #0 8003fde: d101 bne.n 8003fe4 { return HAL_ERROR; 8003fe0: 2301 movs r3, #1 8003fe2: e0cc b.n 800417e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8003fe4: 4b68 ldr r3, [pc, #416] @ (8004188 ) 8003fe6: 681b ldr r3, [r3, #0] 8003fe8: f003 030f and.w r3, r3, #15 8003fec: 683a ldr r2, [r7, #0] 8003fee: 429a cmp r2, r3 8003ff0: d90c bls.n 800400c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003ff2: 4b65 ldr r3, [pc, #404] @ (8004188 ) 8003ff4: 683a ldr r2, [r7, #0] 8003ff6: b2d2 uxtb r2, r2 8003ff8: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8003ffa: 4b63 ldr r3, [pc, #396] @ (8004188 ) 8003ffc: 681b ldr r3, [r3, #0] 8003ffe: f003 030f and.w r3, r3, #15 8004002: 683a ldr r2, [r7, #0] 8004004: 429a cmp r2, r3 8004006: d001 beq.n 800400c { return HAL_ERROR; 8004008: 2301 movs r3, #1 800400a: e0b8 b.n 800417e } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800400c: 687b ldr r3, [r7, #4] 800400e: 681b ldr r3, [r3, #0] 8004010: f003 0302 and.w r3, r3, #2 8004014: 2b00 cmp r3, #0 8004016: d020 beq.n 800405a { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004018: 687b ldr r3, [r7, #4] 800401a: 681b ldr r3, [r3, #0] 800401c: f003 0304 and.w r3, r3, #4 8004020: 2b00 cmp r3, #0 8004022: d005 beq.n 8004030 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8004024: 4b59 ldr r3, [pc, #356] @ (800418c ) 8004026: 689b ldr r3, [r3, #8] 8004028: 4a58 ldr r2, [pc, #352] @ (800418c ) 800402a: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 800402e: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004030: 687b ldr r3, [r7, #4] 8004032: 681b ldr r3, [r3, #0] 8004034: f003 0308 and.w r3, r3, #8 8004038: 2b00 cmp r3, #0 800403a: d005 beq.n 8004048 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 800403c: 4b53 ldr r3, [pc, #332] @ (800418c ) 800403e: 689b ldr r3, [r3, #8] 8004040: 4a52 ldr r2, [pc, #328] @ (800418c ) 8004042: f443 4360 orr.w r3, r3, #57344 @ 0xe000 8004046: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8004048: 4b50 ldr r3, [pc, #320] @ (800418c ) 800404a: 689b ldr r3, [r3, #8] 800404c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8004050: 687b ldr r3, [r7, #4] 8004052: 689b ldr r3, [r3, #8] 8004054: 494d ldr r1, [pc, #308] @ (800418c ) 8004056: 4313 orrs r3, r2 8004058: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800405a: 687b ldr r3, [r7, #4] 800405c: 681b ldr r3, [r3, #0] 800405e: f003 0301 and.w r3, r3, #1 8004062: 2b00 cmp r3, #0 8004064: d044 beq.n 80040f0 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004066: 687b ldr r3, [r7, #4] 8004068: 685b ldr r3, [r3, #4] 800406a: 2b01 cmp r3, #1 800406c: d107 bne.n 800407e { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800406e: 4b47 ldr r3, [pc, #284] @ (800418c ) 8004070: 681b ldr r3, [r3, #0] 8004072: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004076: 2b00 cmp r3, #0 8004078: d119 bne.n 80040ae { return HAL_ERROR; 800407a: 2301 movs r3, #1 800407c: e07f b.n 800417e } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 800407e: 687b ldr r3, [r7, #4] 8004080: 685b ldr r3, [r3, #4] 8004082: 2b02 cmp r3, #2 8004084: d003 beq.n 800408e (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 8004086: 687b ldr r3, [r7, #4] 8004088: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 800408a: 2b03 cmp r3, #3 800408c: d107 bne.n 800409e { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800408e: 4b3f ldr r3, [pc, #252] @ (800418c ) 8004090: 681b ldr r3, [r3, #0] 8004092: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004096: 2b00 cmp r3, #0 8004098: d109 bne.n 80040ae { return HAL_ERROR; 800409a: 2301 movs r3, #1 800409c: e06f b.n 800417e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800409e: 4b3b ldr r3, [pc, #236] @ (800418c ) 80040a0: 681b ldr r3, [r3, #0] 80040a2: f003 0302 and.w r3, r3, #2 80040a6: 2b00 cmp r3, #0 80040a8: d101 bne.n 80040ae { return HAL_ERROR; 80040aa: 2301 movs r3, #1 80040ac: e067 b.n 800417e } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80040ae: 4b37 ldr r3, [pc, #220] @ (800418c ) 80040b0: 689b ldr r3, [r3, #8] 80040b2: f023 0203 bic.w r2, r3, #3 80040b6: 687b ldr r3, [r7, #4] 80040b8: 685b ldr r3, [r3, #4] 80040ba: 4934 ldr r1, [pc, #208] @ (800418c ) 80040bc: 4313 orrs r3, r2 80040be: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 80040c0: f7fd fcb2 bl 8001a28 80040c4: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80040c6: e00a b.n 80040de { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80040c8: f7fd fcae bl 8001a28 80040cc: 4602 mov r2, r0 80040ce: 68fb ldr r3, [r7, #12] 80040d0: 1ad3 subs r3, r2, r3 80040d2: f241 3288 movw r2, #5000 @ 0x1388 80040d6: 4293 cmp r3, r2 80040d8: d901 bls.n 80040de { return HAL_TIMEOUT; 80040da: 2303 movs r3, #3 80040dc: e04f b.n 800417e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80040de: 4b2b ldr r3, [pc, #172] @ (800418c ) 80040e0: 689b ldr r3, [r3, #8] 80040e2: f003 020c and.w r2, r3, #12 80040e6: 687b ldr r3, [r7, #4] 80040e8: 685b ldr r3, [r3, #4] 80040ea: 009b lsls r3, r3, #2 80040ec: 429a cmp r2, r3 80040ee: d1eb bne.n 80040c8 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80040f0: 4b25 ldr r3, [pc, #148] @ (8004188 ) 80040f2: 681b ldr r3, [r3, #0] 80040f4: f003 030f and.w r3, r3, #15 80040f8: 683a ldr r2, [r7, #0] 80040fa: 429a cmp r2, r3 80040fc: d20c bcs.n 8004118 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80040fe: 4b22 ldr r3, [pc, #136] @ (8004188 ) 8004100: 683a ldr r2, [r7, #0] 8004102: b2d2 uxtb r2, r2 8004104: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004106: 4b20 ldr r3, [pc, #128] @ (8004188 ) 8004108: 681b ldr r3, [r3, #0] 800410a: f003 030f and.w r3, r3, #15 800410e: 683a ldr r2, [r7, #0] 8004110: 429a cmp r2, r3 8004112: d001 beq.n 8004118 { return HAL_ERROR; 8004114: 2301 movs r3, #1 8004116: e032 b.n 800417e } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004118: 687b ldr r3, [r7, #4] 800411a: 681b ldr r3, [r3, #0] 800411c: f003 0304 and.w r3, r3, #4 8004120: 2b00 cmp r3, #0 8004122: d008 beq.n 8004136 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8004124: 4b19 ldr r3, [pc, #100] @ (800418c ) 8004126: 689b ldr r3, [r3, #8] 8004128: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 800412c: 687b ldr r3, [r7, #4] 800412e: 68db ldr r3, [r3, #12] 8004130: 4916 ldr r1, [pc, #88] @ (800418c ) 8004132: 4313 orrs r3, r2 8004134: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004136: 687b ldr r3, [r7, #4] 8004138: 681b ldr r3, [r3, #0] 800413a: f003 0308 and.w r3, r3, #8 800413e: 2b00 cmp r3, #0 8004140: d009 beq.n 8004156 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8004142: 4b12 ldr r3, [pc, #72] @ (800418c ) 8004144: 689b ldr r3, [r3, #8] 8004146: f423 4260 bic.w r2, r3, #57344 @ 0xe000 800414a: 687b ldr r3, [r7, #4] 800414c: 691b ldr r3, [r3, #16] 800414e: 00db lsls r3, r3, #3 8004150: 490e ldr r1, [pc, #56] @ (800418c ) 8004152: 4313 orrs r3, r2 8004154: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8004156: f000 fb7f bl 8004858 800415a: 4602 mov r2, r0 800415c: 4b0b ldr r3, [pc, #44] @ (800418c ) 800415e: 689b ldr r3, [r3, #8] 8004160: 091b lsrs r3, r3, #4 8004162: f003 030f and.w r3, r3, #15 8004166: 490a ldr r1, [pc, #40] @ (8004190 ) 8004168: 5ccb ldrb r3, [r1, r3] 800416a: fa22 f303 lsr.w r3, r2, r3 800416e: 4a09 ldr r2, [pc, #36] @ (8004194 ) 8004170: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); 8004172: 4b09 ldr r3, [pc, #36] @ (8004198 ) 8004174: 681b ldr r3, [r3, #0] 8004176: 4618 mov r0, r3 8004178: f7fd fc12 bl 80019a0 return HAL_OK; 800417c: 2300 movs r3, #0 } 800417e: 4618 mov r0, r3 8004180: 3710 adds r7, #16 8004182: 46bd mov sp, r7 8004184: bd80 pop {r7, pc} 8004186: bf00 nop 8004188: 40023c00 .word 0x40023c00 800418c: 40023800 .word 0x40023800 8004190: 0800aa00 .word 0x0800aa00 8004194: 20000090 .word 0x20000090 8004198: 20000094 .word 0x20000094 0800419c : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 800419c: b480 push {r7} 800419e: af00 add r7, sp, #0 return SystemCoreClock; 80041a0: 4b03 ldr r3, [pc, #12] @ (80041b0 ) 80041a2: 681b ldr r3, [r3, #0] } 80041a4: 4618 mov r0, r3 80041a6: 46bd mov sp, r7 80041a8: f85d 7b04 ldr.w r7, [sp], #4 80041ac: 4770 bx lr 80041ae: bf00 nop 80041b0: 20000090 .word 0x20000090 080041b4 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80041b4: b580 push {r7, lr} 80041b6: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 80041b8: f7ff fff0 bl 800419c 80041bc: 4602 mov r2, r0 80041be: 4b05 ldr r3, [pc, #20] @ (80041d4 ) 80041c0: 689b ldr r3, [r3, #8] 80041c2: 0a9b lsrs r3, r3, #10 80041c4: f003 0307 and.w r3, r3, #7 80041c8: 4903 ldr r1, [pc, #12] @ (80041d8 ) 80041ca: 5ccb ldrb r3, [r1, r3] 80041cc: fa22 f303 lsr.w r3, r2, r3 } 80041d0: 4618 mov r0, r3 80041d2: bd80 pop {r7, pc} 80041d4: 40023800 .word 0x40023800 80041d8: 0800aa10 .word 0x0800aa10 080041dc : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 80041dc: b580 push {r7, lr} 80041de: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 80041e0: f7ff ffdc bl 800419c 80041e4: 4602 mov r2, r0 80041e6: 4b05 ldr r3, [pc, #20] @ (80041fc ) 80041e8: 689b ldr r3, [r3, #8] 80041ea: 0b5b lsrs r3, r3, #13 80041ec: f003 0307 and.w r3, r3, #7 80041f0: 4903 ldr r1, [pc, #12] @ (8004200 ) 80041f2: 5ccb ldrb r3, [r1, r3] 80041f4: fa22 f303 lsr.w r3, r2, r3 } 80041f8: 4618 mov r0, r3 80041fa: bd80 pop {r7, pc} 80041fc: 40023800 .word 0x40023800 8004200: 0800aa10 .word 0x0800aa10 08004204 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8004204: b580 push {r7, lr} 8004206: b08c sub sp, #48 @ 0x30 8004208: af00 add r7, sp, #0 800420a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800420c: 2300 movs r3, #0 800420e: 627b str r3, [r7, #36] @ 0x24 uint32_t tmpreg1 = 0U; 8004210: 2300 movs r3, #0 8004212: 623b str r3, [r7, #32] uint32_t plli2sp = 0U; 8004214: 2300 movs r3, #0 8004216: 61fb str r3, [r7, #28] uint32_t plli2sq = 0U; 8004218: 2300 movs r3, #0 800421a: 61bb str r3, [r7, #24] uint32_t plli2sr = 0U; 800421c: 2300 movs r3, #0 800421e: 617b str r3, [r7, #20] uint32_t pllsaip = 0U; 8004220: 2300 movs r3, #0 8004222: 613b str r3, [r7, #16] uint32_t pllsaiq = 0U; 8004224: 2300 movs r3, #0 8004226: 60fb str r3, [r7, #12] uint32_t plli2sused = 0U; 8004228: 2300 movs r3, #0 800422a: 62fb str r3, [r7, #44] @ 0x2c uint32_t pllsaiused = 0U; 800422c: 2300 movs r3, #0 800422e: 62bb str r3, [r7, #40] @ 0x28 /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------ I2S APB1 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) 8004230: 687b ldr r3, [r7, #4] 8004232: 681b ldr r3, [r3, #0] 8004234: f003 0301 and.w r3, r3, #1 8004238: 2b00 cmp r3, #0 800423a: d010 beq.n 800425e { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); 800423c: 4b6f ldr r3, [pc, #444] @ (80043fc ) 800423e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004242: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000 8004246: 687b ldr r3, [r7, #4] 8004248: 6b9b ldr r3, [r3, #56] @ 0x38 800424a: 496c ldr r1, [pc, #432] @ (80043fc ) 800424c: 4313 orrs r3, r2 800424e: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) 8004252: 687b ldr r3, [r7, #4] 8004254: 6b9b ldr r3, [r3, #56] @ 0x38 8004256: 2b00 cmp r3, #0 8004258: d101 bne.n 800425e { plli2sused = 1U; 800425a: 2301 movs r3, #1 800425c: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*---------------------------- I2S APB2 configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) 800425e: 687b ldr r3, [r7, #4] 8004260: 681b ldr r3, [r3, #0] 8004262: f003 0302 and.w r3, r3, #2 8004266: 2b00 cmp r3, #0 8004268: d010 beq.n 800428c { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); 800426a: 4b64 ldr r3, [pc, #400] @ (80043fc ) 800426c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004270: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000 8004274: 687b ldr r3, [r7, #4] 8004276: 6bdb ldr r3, [r3, #60] @ 0x3c 8004278: 4960 ldr r1, [pc, #384] @ (80043fc ) 800427a: 4313 orrs r3, r2 800427c: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) 8004280: 687b ldr r3, [r7, #4] 8004282: 6bdb ldr r3, [r3, #60] @ 0x3c 8004284: 2b00 cmp r3, #0 8004286: d101 bne.n 800428c { plli2sused = 1U; 8004288: 2301 movs r3, #1 800428a: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*--------------------------- SAI1 configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) 800428c: 687b ldr r3, [r7, #4] 800428e: 681b ldr r3, [r3, #0] 8004290: f003 0304 and.w r3, r3, #4 8004294: 2b00 cmp r3, #0 8004296: d017 beq.n 80042c8 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8004298: 4b58 ldr r3, [pc, #352] @ (80043fc ) 800429a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800429e: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 80042a2: 687b ldr r3, [r7, #4] 80042a4: 6b1b ldr r3, [r3, #48] @ 0x30 80042a6: 4955 ldr r1, [pc, #340] @ (80043fc ) 80042a8: 4313 orrs r3, r2 80042aa: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) 80042ae: 687b ldr r3, [r7, #4] 80042b0: 6b1b ldr r3, [r3, #48] @ 0x30 80042b2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80042b6: d101 bne.n 80042bc { plli2sused = 1U; 80042b8: 2301 movs r3, #1 80042ba: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) 80042bc: 687b ldr r3, [r7, #4] 80042be: 6b1b ldr r3, [r3, #48] @ 0x30 80042c0: 2b00 cmp r3, #0 80042c2: d101 bne.n 80042c8 { pllsaiused = 1U; 80042c4: 2301 movs r3, #1 80042c6: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*-------------------------- SAI2 configuration ----------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) 80042c8: 687b ldr r3, [r7, #4] 80042ca: 681b ldr r3, [r3, #0] 80042cc: f003 0308 and.w r3, r3, #8 80042d0: 2b00 cmp r3, #0 80042d2: d017 beq.n 8004304 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 80042d4: 4b49 ldr r3, [pc, #292] @ (80043fc ) 80042d6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80042da: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 80042de: 687b ldr r3, [r7, #4] 80042e0: 6b5b ldr r3, [r3, #52] @ 0x34 80042e2: 4946 ldr r1, [pc, #280] @ (80043fc ) 80042e4: 4313 orrs r3, r2 80042e6: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) 80042ea: 687b ldr r3, [r7, #4] 80042ec: 6b5b ldr r3, [r3, #52] @ 0x34 80042ee: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80042f2: d101 bne.n 80042f8 { plli2sused = 1U; 80042f4: 2301 movs r3, #1 80042f6: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) 80042f8: 687b ldr r3, [r7, #4] 80042fa: 6b5b ldr r3, [r3, #52] @ 0x34 80042fc: 2b00 cmp r3, #0 80042fe: d101 bne.n 8004304 { pllsaiused = 1U; 8004300: 2301 movs r3, #1 8004302: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- RTC configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 8004304: 687b ldr r3, [r7, #4] 8004306: 681b ldr r3, [r3, #0] 8004308: f003 0320 and.w r3, r3, #32 800430c: 2b00 cmp r3, #0 800430e: f000 808a beq.w 8004426 { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 8004312: 2300 movs r3, #0 8004314: 60bb str r3, [r7, #8] 8004316: 4b39 ldr r3, [pc, #228] @ (80043fc ) 8004318: 6c1b ldr r3, [r3, #64] @ 0x40 800431a: 4a38 ldr r2, [pc, #224] @ (80043fc ) 800431c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004320: 6413 str r3, [r2, #64] @ 0x40 8004322: 4b36 ldr r3, [pc, #216] @ (80043fc ) 8004324: 6c1b ldr r3, [r3, #64] @ 0x40 8004326: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800432a: 60bb str r3, [r7, #8] 800432c: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; 800432e: 4b34 ldr r3, [pc, #208] @ (8004400 ) 8004330: 681b ldr r3, [r3, #0] 8004332: 4a33 ldr r2, [pc, #204] @ (8004400 ) 8004334: f443 7380 orr.w r3, r3, #256 @ 0x100 8004338: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 800433a: f7fd fb75 bl 8001a28 800433e: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR & PWR_CR_DBP) == RESET) 8004340: e008 b.n 8004354 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004342: f7fd fb71 bl 8001a28 8004346: 4602 mov r2, r0 8004348: 6a7b ldr r3, [r7, #36] @ 0x24 800434a: 1ad3 subs r3, r2, r3 800434c: 2b02 cmp r3, #2 800434e: d901 bls.n 8004354 { return HAL_TIMEOUT; 8004350: 2303 movs r3, #3 8004352: e278 b.n 8004846 while ((PWR->CR & PWR_CR_DBP) == RESET) 8004354: 4b2a ldr r3, [pc, #168] @ (8004400 ) 8004356: 681b ldr r3, [r3, #0] 8004358: f403 7380 and.w r3, r3, #256 @ 0x100 800435c: 2b00 cmp r3, #0 800435e: d0f0 beq.n 8004342 } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); 8004360: 4b26 ldr r3, [pc, #152] @ (80043fc ) 8004362: 6f1b ldr r3, [r3, #112] @ 0x70 8004364: f403 7340 and.w r3, r3, #768 @ 0x300 8004368: 623b str r3, [r7, #32] if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 800436a: 6a3b ldr r3, [r7, #32] 800436c: 2b00 cmp r3, #0 800436e: d02f beq.n 80043d0 8004370: 687b ldr r3, [r7, #4] 8004372: 6c1b ldr r3, [r3, #64] @ 0x40 8004374: f403 7340 and.w r3, r3, #768 @ 0x300 8004378: 6a3a ldr r2, [r7, #32] 800437a: 429a cmp r2, r3 800437c: d028 beq.n 80043d0 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800437e: 4b1f ldr r3, [pc, #124] @ (80043fc ) 8004380: 6f1b ldr r3, [r3, #112] @ 0x70 8004382: f423 7340 bic.w r3, r3, #768 @ 0x300 8004386: 623b str r3, [r7, #32] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8004388: 4b1e ldr r3, [pc, #120] @ (8004404 ) 800438a: 2201 movs r2, #1 800438c: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 800438e: 4b1d ldr r3, [pc, #116] @ (8004404 ) 8004390: 2200 movs r2, #0 8004392: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; 8004394: 4a19 ldr r2, [pc, #100] @ (80043fc ) 8004396: 6a3b ldr r3, [r7, #32] 8004398: 6713 str r3, [r2, #112] @ 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 800439a: 4b18 ldr r3, [pc, #96] @ (80043fc ) 800439c: 6f1b ldr r3, [r3, #112] @ 0x70 800439e: f003 0301 and.w r3, r3, #1 80043a2: 2b01 cmp r3, #1 80043a4: d114 bne.n 80043d0 { /* Get tick */ tickstart = HAL_GetTick(); 80043a6: f7fd fb3f bl 8001a28 80043aa: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80043ac: e00a b.n 80043c4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80043ae: f7fd fb3b bl 8001a28 80043b2: 4602 mov r2, r0 80043b4: 6a7b ldr r3, [r7, #36] @ 0x24 80043b6: 1ad3 subs r3, r2, r3 80043b8: f241 3288 movw r2, #5000 @ 0x1388 80043bc: 4293 cmp r3, r2 80043be: d901 bls.n 80043c4 { return HAL_TIMEOUT; 80043c0: 2303 movs r3, #3 80043c2: e240 b.n 8004846 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80043c4: 4b0d ldr r3, [pc, #52] @ (80043fc ) 80043c6: 6f1b ldr r3, [r3, #112] @ 0x70 80043c8: f003 0302 and.w r3, r3, #2 80043cc: 2b00 cmp r3, #0 80043ce: d0ee beq.n 80043ae } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80043d0: 687b ldr r3, [r7, #4] 80043d2: 6c1b ldr r3, [r3, #64] @ 0x40 80043d4: f403 7340 and.w r3, r3, #768 @ 0x300 80043d8: f5b3 7f40 cmp.w r3, #768 @ 0x300 80043dc: d114 bne.n 8004408 80043de: 4b07 ldr r3, [pc, #28] @ (80043fc ) 80043e0: 689b ldr r3, [r3, #8] 80043e2: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000 80043e6: 687b ldr r3, [r7, #4] 80043e8: 6c1b ldr r3, [r3, #64] @ 0x40 80043ea: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 80043ee: f423 7340 bic.w r3, r3, #768 @ 0x300 80043f2: 4902 ldr r1, [pc, #8] @ (80043fc ) 80043f4: 4313 orrs r3, r2 80043f6: 608b str r3, [r1, #8] 80043f8: e00c b.n 8004414 80043fa: bf00 nop 80043fc: 40023800 .word 0x40023800 8004400: 40007000 .word 0x40007000 8004404: 42470e40 .word 0x42470e40 8004408: 4b4a ldr r3, [pc, #296] @ (8004534 ) 800440a: 689b ldr r3, [r3, #8] 800440c: 4a49 ldr r2, [pc, #292] @ (8004534 ) 800440e: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000 8004412: 6093 str r3, [r2, #8] 8004414: 4b47 ldr r3, [pc, #284] @ (8004534 ) 8004416: 6f1a ldr r2, [r3, #112] @ 0x70 8004418: 687b ldr r3, [r7, #4] 800441a: 6c1b ldr r3, [r3, #64] @ 0x40 800441c: f3c3 030b ubfx r3, r3, #0, #12 8004420: 4944 ldr r1, [pc, #272] @ (8004534 ) 8004422: 4313 orrs r3, r2 8004424: 670b str r3, [r1, #112] @ 0x70 } /*--------------------------------------------------------------------------*/ /*---------------------------- TIM configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 8004426: 687b ldr r3, [r7, #4] 8004428: 681b ldr r3, [r3, #0] 800442a: f003 0310 and.w r3, r3, #16 800442e: 2b00 cmp r3, #0 8004430: d004 beq.n 800443c { /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8004432: 687b ldr r3, [r7, #4] 8004434: f893 2058 ldrb.w r2, [r3, #88] @ 0x58 8004438: 4b3f ldr r3, [pc, #252] @ (8004538 ) 800443a: 601a str r2, [r3, #0] } /*--------------------------------------------------------------------------*/ /*---------------------------- FMPI2C1 Configuration -----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) 800443c: 687b ldr r3, [r7, #4] 800443e: 681b ldr r3, [r3, #0] 8004440: f003 0380 and.w r3, r3, #128 @ 0x80 8004444: 2b00 cmp r3, #0 8004446: d00a beq.n 800445e { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); 8004448: 4b3a ldr r3, [pc, #232] @ (8004534 ) 800444a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800444e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 8004452: 687b ldr r3, [r7, #4] 8004454: 6cdb ldr r3, [r3, #76] @ 0x4c 8004456: 4937 ldr r1, [pc, #220] @ (8004534 ) 8004458: 4313 orrs r3, r2 800445a: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ CEC Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800445e: 687b ldr r3, [r7, #4] 8004460: 681b ldr r3, [r3, #0] 8004462: f003 0340 and.w r3, r3, #64 @ 0x40 8004466: 2b00 cmp r3, #0 8004468: d00a beq.n 8004480 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800446a: 4b32 ldr r3, [pc, #200] @ (8004534 ) 800446c: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004470: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000 8004474: 687b ldr r3, [r7, #4] 8004476: 6c9b ldr r3, [r3, #72] @ 0x48 8004478: 492e ldr r1, [pc, #184] @ (8004534 ) 800447a: 4313 orrs r3, r2 800447c: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*----------------------------- CLK48 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 8004480: 687b ldr r3, [r7, #4] 8004482: 681b ldr r3, [r3, #0] 8004484: f403 7380 and.w r3, r3, #256 @ 0x100 8004488: 2b00 cmp r3, #0 800448a: d011 beq.n 80044b0 { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); 800448c: 4b29 ldr r3, [pc, #164] @ (8004534 ) 800448e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004492: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000 8004496: 687b ldr r3, [r7, #4] 8004498: 6d5b ldr r3, [r3, #84] @ 0x54 800449a: 4926 ldr r1, [pc, #152] @ (8004534 ) 800449c: 4313 orrs r3, r2 800449e: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLSAI when it's used as clock source for CLK48 */ if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) 80044a2: 687b ldr r3, [r7, #4] 80044a4: 6d5b ldr r3, [r3, #84] @ 0x54 80044a6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80044aa: d101 bne.n 80044b0 { pllsaiused = 1U; 80044ac: 2301 movs r3, #1 80044ae: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- SDIO Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) 80044b0: 687b ldr r3, [r7, #4] 80044b2: 681b ldr r3, [r3, #0] 80044b4: f403 7300 and.w r3, r3, #512 @ 0x200 80044b8: 2b00 cmp r3, #0 80044ba: d00a beq.n 80044d2 { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); 80044bc: 4b1d ldr r3, [pc, #116] @ (8004534 ) 80044be: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80044c2: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000 80044c6: 687b ldr r3, [r7, #4] 80044c8: 6c5b ldr r3, [r3, #68] @ 0x44 80044ca: 491a ldr r1, [pc, #104] @ (8004534 ) 80044cc: 4313 orrs r3, r2 80044ce: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ SPDIFRX Configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 80044d2: 687b ldr r3, [r7, #4] 80044d4: 681b ldr r3, [r3, #0] 80044d6: f403 6380 and.w r3, r3, #1024 @ 0x400 80044da: 2b00 cmp r3, #0 80044dc: d011 beq.n 8004502 { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); /* Configure the SPDIFRX clock source */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); 80044de: 4b15 ldr r3, [pc, #84] @ (8004534 ) 80044e0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80044e4: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000 80044e8: 687b ldr r3, [r7, #4] 80044ea: 6d1b ldr r3, [r3, #80] @ 0x50 80044ec: 4911 ldr r1, [pc, #68] @ (8004534 ) 80044ee: 4313 orrs r3, r2 80044f0: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) 80044f4: 687b ldr r3, [r7, #4] 80044f6: 6d1b ldr r3, [r3, #80] @ 0x50 80044f8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80044fc: d101 bne.n 8004502 { plli2sused = 1U; 80044fe: 2301 movs r3, #1 8004500: 62fb str r3, [r7, #44] @ 0x2c /*--------------------------------------------------------------------------*/ /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) 8004502: 6afb ldr r3, [r7, #44] @ 0x2c 8004504: 2b01 cmp r3, #1 8004506: d005 beq.n 8004514 8004508: 687b ldr r3, [r7, #4] 800450a: 681b ldr r3, [r3, #0] 800450c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8004510: f040 80ff bne.w 8004712 { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 8004514: 4b09 ldr r3, [pc, #36] @ (800453c ) 8004516: 2200 movs r2, #0 8004518: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800451a: f7fd fa85 bl 8001a28 800451e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004520: e00e b.n 8004540 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004522: f7fd fa81 bl 8001a28 8004526: 4602 mov r2, r0 8004528: 6a7b ldr r3, [r7, #36] @ 0x24 800452a: 1ad3 subs r3, r2, r3 800452c: 2b02 cmp r3, #2 800452e: d907 bls.n 8004540 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004530: 2303 movs r3, #3 8004532: e188 b.n 8004846 8004534: 40023800 .word 0x40023800 8004538: 424711e0 .word 0x424711e0 800453c: 42470068 .word 0x42470068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004540: 4b7e ldr r3, [pc, #504] @ (800473c ) 8004542: 681b ldr r3, [r3, #0] 8004544: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004548: 2b00 cmp r3, #0 800454a: d1ea bne.n 8004522 /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) 800454c: 687b ldr r3, [r7, #4] 800454e: 681b ldr r3, [r3, #0] 8004550: f003 0301 and.w r3, r3, #1 8004554: 2b00 cmp r3, #0 8004556: d003 beq.n 8004560 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8004558: 687b ldr r3, [r7, #4] 800455a: 6b9b ldr r3, [r3, #56] @ 0x38 800455c: 2b00 cmp r3, #0 800455e: d009 beq.n 8004574 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 8004560: 687b ldr r3, [r7, #4] 8004562: 681b ldr r3, [r3, #0] 8004564: f003 0302 and.w r3, r3, #2 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8004568: 2b00 cmp r3, #0 800456a: d028 beq.n 80045be ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 800456c: 687b ldr r3, [r7, #4] 800456e: 6bdb ldr r3, [r3, #60] @ 0x3c 8004570: 2b00 cmp r3, #0 8004572: d124 bne.n 80045be { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004574: 4b71 ldr r3, [pc, #452] @ (800473c ) 8004576: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800457a: 0c1b lsrs r3, r3, #16 800457c: f003 0303 and.w r3, r3, #3 8004580: 3301 adds r3, #1 8004582: 005b lsls r3, r3, #1 8004584: 61fb str r3, [r7, #28] plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); 8004586: 4b6d ldr r3, [pc, #436] @ (800473c ) 8004588: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800458c: 0e1b lsrs r3, r3, #24 800458e: f003 030f and.w r3, r3, #15 8004592: 61bb str r3, [r7, #24] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq, 8004594: 687b ldr r3, [r7, #4] 8004596: 685a ldr r2, [r3, #4] 8004598: 687b ldr r3, [r7, #4] 800459a: 689b ldr r3, [r3, #8] 800459c: 019b lsls r3, r3, #6 800459e: 431a orrs r2, r3 80045a0: 69fb ldr r3, [r7, #28] 80045a2: 085b lsrs r3, r3, #1 80045a4: 3b01 subs r3, #1 80045a6: 041b lsls r3, r3, #16 80045a8: 431a orrs r2, r3 80045aa: 69bb ldr r3, [r7, #24] 80045ac: 061b lsls r3, r3, #24 80045ae: 431a orrs r2, r3 80045b0: 687b ldr r3, [r7, #4] 80045b2: 695b ldr r3, [r3, #20] 80045b4: 071b lsls r3, r3, #28 80045b6: 4961 ldr r1, [pc, #388] @ (800473c ) 80045b8: 4313 orrs r3, r2 80045ba: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SR); } /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 80045be: 687b ldr r3, [r7, #4] 80045c0: 681b ldr r3, [r3, #0] 80045c2: f003 0304 and.w r3, r3, #4 80045c6: 2b00 cmp r3, #0 80045c8: d004 beq.n 80045d4 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 80045ca: 687b ldr r3, [r7, #4] 80045cc: 6b1b ldr r3, [r3, #48] @ 0x30 80045ce: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80045d2: d00a beq.n 80045ea ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 80045d4: 687b ldr r3, [r7, #4] 80045d6: 681b ldr r3, [r3, #0] 80045d8: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 80045dc: 2b00 cmp r3, #0 80045de: d035 beq.n 800464c ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 80045e0: 687b ldr r3, [r7, #4] 80045e2: 6b5b ldr r3, [r3, #52] @ 0x34 80045e4: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80045e8: d130 bne.n 800464c assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 80045ea: 4b54 ldr r3, [pc, #336] @ (800473c ) 80045ec: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80045f0: 0c1b lsrs r3, r3, #16 80045f2: f003 0303 and.w r3, r3, #3 80045f6: 3301 adds r3, #1 80045f8: 005b lsls r3, r3, #1 80045fa: 61fb str r3, [r7, #28] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 80045fc: 4b4f ldr r3, [pc, #316] @ (800473c ) 80045fe: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004602: 0f1b lsrs r3, r3, #28 8004604: f003 0307 and.w r3, r3, #7 8004608: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, 800460a: 687b ldr r3, [r7, #4] 800460c: 685a ldr r2, [r3, #4] 800460e: 687b ldr r3, [r7, #4] 8004610: 689b ldr r3, [r3, #8] 8004612: 019b lsls r3, r3, #6 8004614: 431a orrs r2, r3 8004616: 69fb ldr r3, [r7, #28] 8004618: 085b lsrs r3, r3, #1 800461a: 3b01 subs r3, #1 800461c: 041b lsls r3, r3, #16 800461e: 431a orrs r2, r3 8004620: 687b ldr r3, [r7, #4] 8004622: 691b ldr r3, [r3, #16] 8004624: 061b lsls r3, r3, #24 8004626: 431a orrs r2, r3 8004628: 697b ldr r3, [r7, #20] 800462a: 071b lsls r3, r3, #28 800462c: 4943 ldr r1, [pc, #268] @ (800473c ) 800462e: 4313 orrs r3, r2 8004630: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 8004634: 4b41 ldr r3, [pc, #260] @ (800473c ) 8004636: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800463a: f023 021f bic.w r2, r3, #31 800463e: 687b ldr r3, [r7, #4] 8004640: 6a9b ldr r3, [r3, #40] @ 0x28 8004642: 3b01 subs r3, #1 8004644: 493d ldr r1, [pc, #244] @ (800473c ) 8004646: 4313 orrs r3, r2 8004648: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 800464c: 687b ldr r3, [r7, #4] 800464e: 681b ldr r3, [r3, #0] 8004650: f403 6380 and.w r3, r3, #1024 @ 0x400 8004654: 2b00 cmp r3, #0 8004656: d029 beq.n 80046ac && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 8004658: 687b ldr r3, [r7, #4] 800465a: 6d1b ldr r3, [r3, #80] @ 0x50 800465c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004660: d124 bne.n 80046ac { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004662: 4b36 ldr r3, [pc, #216] @ (800473c ) 8004664: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004668: 0c1b lsrs r3, r3, #16 800466a: f003 0303 and.w r3, r3, #3 800466e: 3301 adds r3, #1 8004670: 005b lsls r3, r3, #1 8004672: 61bb str r3, [r7, #24] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004674: 4b31 ldr r3, [pc, #196] @ (800473c ) 8004676: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800467a: 0f1b lsrs r3, r3, #28 800467c: f003 0307 and.w r3, r3, #7 8004680: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 8004682: 687b ldr r3, [r7, #4] 8004684: 685a ldr r2, [r3, #4] 8004686: 687b ldr r3, [r7, #4] 8004688: 689b ldr r3, [r3, #8] 800468a: 019b lsls r3, r3, #6 800468c: 431a orrs r2, r3 800468e: 687b ldr r3, [r7, #4] 8004690: 68db ldr r3, [r3, #12] 8004692: 085b lsrs r3, r3, #1 8004694: 3b01 subs r3, #1 8004696: 041b lsls r3, r3, #16 8004698: 431a orrs r2, r3 800469a: 69bb ldr r3, [r7, #24] 800469c: 061b lsls r3, r3, #24 800469e: 431a orrs r2, r3 80046a0: 697b ldr r3, [r7, #20] 80046a2: 071b lsls r3, r3, #28 80046a4: 4925 ldr r1, [pc, #148] @ (800473c ) 80046a6: 4313 orrs r3, r2 80046a8: f8c1 3084 str.w r3, [r1, #132] @ 0x84 plli2sq, plli2sr); } /*----------------- In Case of PLLI2S is just selected -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 80046ac: 687b ldr r3, [r7, #4] 80046ae: 681b ldr r3, [r3, #0] 80046b0: f403 6300 and.w r3, r3, #2048 @ 0x800 80046b4: 2b00 cmp r3, #0 80046b6: d016 beq.n 80046e6 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 80046b8: 687b ldr r3, [r7, #4] 80046ba: 685a ldr r2, [r3, #4] 80046bc: 687b ldr r3, [r7, #4] 80046be: 689b ldr r3, [r3, #8] 80046c0: 019b lsls r3, r3, #6 80046c2: 431a orrs r2, r3 80046c4: 687b ldr r3, [r7, #4] 80046c6: 68db ldr r3, [r3, #12] 80046c8: 085b lsrs r3, r3, #1 80046ca: 3b01 subs r3, #1 80046cc: 041b lsls r3, r3, #16 80046ce: 431a orrs r2, r3 80046d0: 687b ldr r3, [r7, #4] 80046d2: 691b ldr r3, [r3, #16] 80046d4: 061b lsls r3, r3, #24 80046d6: 431a orrs r2, r3 80046d8: 687b ldr r3, [r7, #4] 80046da: 695b ldr r3, [r3, #20] 80046dc: 071b lsls r3, r3, #28 80046de: 4917 ldr r1, [pc, #92] @ (800473c ) 80046e0: 4313 orrs r3, r2 80046e2: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 80046e6: 4b16 ldr r3, [pc, #88] @ (8004740 ) 80046e8: 2201 movs r2, #1 80046ea: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80046ec: f7fd f99c bl 8001a28 80046f0: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80046f2: e008 b.n 8004706 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 80046f4: f7fd f998 bl 8001a28 80046f8: 4602 mov r2, r0 80046fa: 6a7b ldr r3, [r7, #36] @ 0x24 80046fc: 1ad3 subs r3, r2, r3 80046fe: 2b02 cmp r3, #2 8004700: d901 bls.n 8004706 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004702: 2303 movs r3, #3 8004704: e09f b.n 8004846 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004706: 4b0d ldr r3, [pc, #52] @ (800473c ) 8004708: 681b ldr r3, [r3, #0] 800470a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800470e: 2b00 cmp r3, #0 8004710: d0f0 beq.n 80046f4 } /*--------------------------------------------------------------------------*/ /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ if (pllsaiused == 1U) 8004712: 6abb ldr r3, [r7, #40] @ 0x28 8004714: 2b01 cmp r3, #1 8004716: f040 8095 bne.w 8004844 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 800471a: 4b0a ldr r3, [pc, #40] @ (8004744 ) 800471c: 2200 movs r2, #0 800471e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004720: f7fd f982 bl 8001a28 8004724: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is disabled */ while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004726: e00f b.n 8004748 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004728: f7fd f97e bl 8001a28 800472c: 4602 mov r2, r0 800472e: 6a7b ldr r3, [r7, #36] @ 0x24 8004730: 1ad3 subs r3, r2, r3 8004732: 2b02 cmp r3, #2 8004734: d908 bls.n 8004748 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004736: 2303 movs r3, #3 8004738: e085 b.n 8004846 800473a: bf00 nop 800473c: 40023800 .word 0x40023800 8004740: 42470068 .word 0x42470068 8004744: 42470070 .word 0x42470070 while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004748: 4b41 ldr r3, [pc, #260] @ (8004850 ) 800474a: 681b ldr r3, [r3, #0] 800474c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004750: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004754: d0e8 beq.n 8004728 /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8004756: 687b ldr r3, [r7, #4] 8004758: 681b ldr r3, [r3, #0] 800475a: f003 0304 and.w r3, r3, #4 800475e: 2b00 cmp r3, #0 8004760: d003 beq.n 800476a && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8004762: 687b ldr r3, [r7, #4] 8004764: 6b1b ldr r3, [r3, #48] @ 0x30 8004766: 2b00 cmp r3, #0 8004768: d009 beq.n 800477e ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 800476a: 687b ldr r3, [r7, #4] 800476c: 681b ldr r3, [r3, #0] 800476e: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8004772: 2b00 cmp r3, #0 8004774: d02b beq.n 80047ce ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8004776: 687b ldr r3, [r7, #4] 8004778: 6b5b ldr r3, [r3, #52] @ 0x34 800477a: 2b00 cmp r3, #0 800477c: d127 bne.n 80047ce assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); 800477e: 4b34 ldr r3, [pc, #208] @ (8004850 ) 8004780: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004784: 0c1b lsrs r3, r3, #16 8004786: f003 0303 and.w r3, r3, #3 800478a: 3301 adds r3, #1 800478c: 005b lsls r3, r3, #1 800478e: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, 8004790: 687b ldr r3, [r7, #4] 8004792: 699a ldr r2, [r3, #24] 8004794: 687b ldr r3, [r7, #4] 8004796: 69db ldr r3, [r3, #28] 8004798: 019b lsls r3, r3, #6 800479a: 431a orrs r2, r3 800479c: 693b ldr r3, [r7, #16] 800479e: 085b lsrs r3, r3, #1 80047a0: 3b01 subs r3, #1 80047a2: 041b lsls r3, r3, #16 80047a4: 431a orrs r2, r3 80047a6: 687b ldr r3, [r7, #4] 80047a8: 6a5b ldr r3, [r3, #36] @ 0x24 80047aa: 061b lsls r3, r3, #24 80047ac: 4928 ldr r1, [pc, #160] @ (8004850 ) 80047ae: 4313 orrs r3, r2 80047b0: f8c1 3088 str.w r3, [r1, #136] @ 0x88 PeriphClkInit->PLLSAI.PLLSAIQ, 0U); /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 80047b4: 4b26 ldr r3, [pc, #152] @ (8004850 ) 80047b6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80047ba: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 80047be: 687b ldr r3, [r7, #4] 80047c0: 6adb ldr r3, [r3, #44] @ 0x2c 80047c2: 3b01 subs r3, #1 80047c4: 021b lsls r3, r3, #8 80047c6: 4922 ldr r1, [pc, #136] @ (8004850 ) 80047c8: 4313 orrs r3, r2 80047ca: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ /* In Case of PLLI2S is selected as source clock for CLK48 */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 80047ce: 687b ldr r3, [r7, #4] 80047d0: 681b ldr r3, [r3, #0] 80047d2: f403 7380 and.w r3, r3, #256 @ 0x100 80047d6: 2b00 cmp r3, #0 80047d8: d01d beq.n 8004816 && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) 80047da: 687b ldr r3, [r7, #4] 80047dc: 6d5b ldr r3, [r3, #84] @ 0x54 80047de: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80047e2: d118 bne.n 8004816 { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 80047e4: 4b1a ldr r3, [pc, #104] @ (8004850 ) 80047e6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80047ea: 0e1b lsrs r3, r3, #24 80047ec: f003 030f and.w r3, r3, #15 80047f0: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, 80047f2: 687b ldr r3, [r7, #4] 80047f4: 699a ldr r2, [r3, #24] 80047f6: 687b ldr r3, [r7, #4] 80047f8: 69db ldr r3, [r3, #28] 80047fa: 019b lsls r3, r3, #6 80047fc: 431a orrs r2, r3 80047fe: 687b ldr r3, [r7, #4] 8004800: 6a1b ldr r3, [r3, #32] 8004802: 085b lsrs r3, r3, #1 8004804: 3b01 subs r3, #1 8004806: 041b lsls r3, r3, #16 8004808: 431a orrs r2, r3 800480a: 68fb ldr r3, [r7, #12] 800480c: 061b lsls r3, r3, #24 800480e: 4910 ldr r1, [pc, #64] @ (8004850 ) 8004810: 4313 orrs r3, r2 8004812: f8c1 3088 str.w r3, [r1, #136] @ 0x88 pllsaiq, 0U); } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 8004816: 4b0f ldr r3, [pc, #60] @ (8004854 ) 8004818: 2201 movs r2, #1 800481a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800481c: f7fd f904 bl 8001a28 8004820: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is ready */ while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004822: e008 b.n 8004836 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004824: f7fd f900 bl 8001a28 8004828: 4602 mov r2, r0 800482a: 6a7b ldr r3, [r7, #36] @ 0x24 800482c: 1ad3 subs r3, r2, r3 800482e: 2b02 cmp r3, #2 8004830: d901 bls.n 8004836 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004832: 2303 movs r3, #3 8004834: e007 b.n 8004846 while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004836: 4b06 ldr r3, [pc, #24] @ (8004850 ) 8004838: 681b ldr r3, [r3, #0] 800483a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800483e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004842: d1ef bne.n 8004824 } } } return HAL_OK; 8004844: 2300 movs r3, #0 } 8004846: 4618 mov r0, r3 8004848: 3730 adds r7, #48 @ 0x30 800484a: 46bd mov sp, r7 800484c: bd80 pop {r7, pc} 800484e: bf00 nop 8004850: 40023800 .word 0x40023800 8004854: 42470070 .word 0x42470070 08004858 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8004858: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800485c: b0ae sub sp, #184 @ 0xb8 800485e: af00 add r7, sp, #0 uint32_t pllm = 0U; 8004860: 2300 movs r3, #0 8004862: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t pllvco = 0U; 8004866: 2300 movs r3, #0 8004868: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t pllp = 0U; 800486c: 2300 movs r3, #0 800486e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 uint32_t pllr = 0U; 8004872: 2300 movs r3, #0 8004874: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t sysclockfreq = 0U; 8004878: 2300 movs r3, #0 800487a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800487e: 4bcb ldr r3, [pc, #812] @ (8004bac ) 8004880: 689b ldr r3, [r3, #8] 8004882: f003 030c and.w r3, r3, #12 8004886: 2b0c cmp r3, #12 8004888: f200 8206 bhi.w 8004c98 800488c: a201 add r2, pc, #4 @ (adr r2, 8004894 ) 800488e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004892: bf00 nop 8004894: 080048c9 .word 0x080048c9 8004898: 08004c99 .word 0x08004c99 800489c: 08004c99 .word 0x08004c99 80048a0: 08004c99 .word 0x08004c99 80048a4: 080048d1 .word 0x080048d1 80048a8: 08004c99 .word 0x08004c99 80048ac: 08004c99 .word 0x08004c99 80048b0: 08004c99 .word 0x08004c99 80048b4: 080048d9 .word 0x080048d9 80048b8: 08004c99 .word 0x08004c99 80048bc: 08004c99 .word 0x08004c99 80048c0: 08004c99 .word 0x08004c99 80048c4: 08004ac9 .word 0x08004ac9 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 80048c8: 4bb9 ldr r3, [pc, #740] @ (8004bb0 ) 80048ca: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 80048ce: e1e7 b.n 8004ca0 } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 80048d0: 4bb8 ldr r3, [pc, #736] @ (8004bb4 ) 80048d2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 80048d6: e1e3 b.n 8004ca0 } case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 80048d8: 4bb4 ldr r3, [pc, #720] @ (8004bac ) 80048da: 685b ldr r3, [r3, #4] 80048dc: f003 033f and.w r3, r3, #63 @ 0x3f 80048e0: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 80048e4: 4bb1 ldr r3, [pc, #708] @ (8004bac ) 80048e6: 685b ldr r3, [r3, #4] 80048e8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80048ec: 2b00 cmp r3, #0 80048ee: d071 beq.n 80049d4 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 80048f0: 4bae ldr r3, [pc, #696] @ (8004bac ) 80048f2: 685b ldr r3, [r3, #4] 80048f4: 099b lsrs r3, r3, #6 80048f6: 2200 movs r2, #0 80048f8: f8c7 3098 str.w r3, [r7, #152] @ 0x98 80048fc: f8c7 209c str.w r2, [r7, #156] @ 0x9c 8004900: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8004904: f3c3 0308 ubfx r3, r3, #0, #9 8004908: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800490c: 2300 movs r3, #0 800490e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8004912: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8004916: 4622 mov r2, r4 8004918: 462b mov r3, r5 800491a: f04f 0000 mov.w r0, #0 800491e: f04f 0100 mov.w r1, #0 8004922: 0159 lsls r1, r3, #5 8004924: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004928: 0150 lsls r0, r2, #5 800492a: 4602 mov r2, r0 800492c: 460b mov r3, r1 800492e: 4621 mov r1, r4 8004930: 1a51 subs r1, r2, r1 8004932: 6439 str r1, [r7, #64] @ 0x40 8004934: 4629 mov r1, r5 8004936: eb63 0301 sbc.w r3, r3, r1 800493a: 647b str r3, [r7, #68] @ 0x44 800493c: f04f 0200 mov.w r2, #0 8004940: f04f 0300 mov.w r3, #0 8004944: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40 8004948: 4649 mov r1, r9 800494a: 018b lsls r3, r1, #6 800494c: 4641 mov r1, r8 800494e: ea43 6391 orr.w r3, r3, r1, lsr #26 8004952: 4641 mov r1, r8 8004954: 018a lsls r2, r1, #6 8004956: 4641 mov r1, r8 8004958: 1a51 subs r1, r2, r1 800495a: 63b9 str r1, [r7, #56] @ 0x38 800495c: 4649 mov r1, r9 800495e: eb63 0301 sbc.w r3, r3, r1 8004962: 63fb str r3, [r7, #60] @ 0x3c 8004964: f04f 0200 mov.w r2, #0 8004968: f04f 0300 mov.w r3, #0 800496c: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38 8004970: 4649 mov r1, r9 8004972: 00cb lsls r3, r1, #3 8004974: 4641 mov r1, r8 8004976: ea43 7351 orr.w r3, r3, r1, lsr #29 800497a: 4641 mov r1, r8 800497c: 00ca lsls r2, r1, #3 800497e: 4610 mov r0, r2 8004980: 4619 mov r1, r3 8004982: 4603 mov r3, r0 8004984: 4622 mov r2, r4 8004986: 189b adds r3, r3, r2 8004988: 633b str r3, [r7, #48] @ 0x30 800498a: 462b mov r3, r5 800498c: 460a mov r2, r1 800498e: eb42 0303 adc.w r3, r2, r3 8004992: 637b str r3, [r7, #52] @ 0x34 8004994: f04f 0200 mov.w r2, #0 8004998: f04f 0300 mov.w r3, #0 800499c: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 80049a0: 4629 mov r1, r5 80049a2: 024b lsls r3, r1, #9 80049a4: 4621 mov r1, r4 80049a6: ea43 53d1 orr.w r3, r3, r1, lsr #23 80049aa: 4621 mov r1, r4 80049ac: 024a lsls r2, r1, #9 80049ae: 4610 mov r0, r2 80049b0: 4619 mov r1, r3 80049b2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80049b6: 2200 movs r2, #0 80049b8: f8c7 3088 str.w r3, [r7, #136] @ 0x88 80049bc: f8c7 208c str.w r2, [r7, #140] @ 0x8c 80049c0: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88 80049c4: f7fb fc1e bl 8000204 <__aeabi_uldivmod> 80049c8: 4602 mov r2, r0 80049ca: 460b mov r3, r1 80049cc: 4613 mov r3, r2 80049ce: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 80049d2: e067 b.n 8004aa4 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 80049d4: 4b75 ldr r3, [pc, #468] @ (8004bac ) 80049d6: 685b ldr r3, [r3, #4] 80049d8: 099b lsrs r3, r3, #6 80049da: 2200 movs r2, #0 80049dc: f8c7 3080 str.w r3, [r7, #128] @ 0x80 80049e0: f8c7 2084 str.w r2, [r7, #132] @ 0x84 80049e4: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80049e8: f3c3 0308 ubfx r3, r3, #0, #9 80049ec: 67bb str r3, [r7, #120] @ 0x78 80049ee: 2300 movs r3, #0 80049f0: 67fb str r3, [r7, #124] @ 0x7c 80049f2: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78 80049f6: 4622 mov r2, r4 80049f8: 462b mov r3, r5 80049fa: f04f 0000 mov.w r0, #0 80049fe: f04f 0100 mov.w r1, #0 8004a02: 0159 lsls r1, r3, #5 8004a04: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004a08: 0150 lsls r0, r2, #5 8004a0a: 4602 mov r2, r0 8004a0c: 460b mov r3, r1 8004a0e: 4621 mov r1, r4 8004a10: 1a51 subs r1, r2, r1 8004a12: 62b9 str r1, [r7, #40] @ 0x28 8004a14: 4629 mov r1, r5 8004a16: eb63 0301 sbc.w r3, r3, r1 8004a1a: 62fb str r3, [r7, #44] @ 0x2c 8004a1c: f04f 0200 mov.w r2, #0 8004a20: f04f 0300 mov.w r3, #0 8004a24: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28 8004a28: 4649 mov r1, r9 8004a2a: 018b lsls r3, r1, #6 8004a2c: 4641 mov r1, r8 8004a2e: ea43 6391 orr.w r3, r3, r1, lsr #26 8004a32: 4641 mov r1, r8 8004a34: 018a lsls r2, r1, #6 8004a36: 4641 mov r1, r8 8004a38: ebb2 0a01 subs.w sl, r2, r1 8004a3c: 4649 mov r1, r9 8004a3e: eb63 0b01 sbc.w fp, r3, r1 8004a42: f04f 0200 mov.w r2, #0 8004a46: f04f 0300 mov.w r3, #0 8004a4a: ea4f 03cb mov.w r3, fp, lsl #3 8004a4e: ea43 735a orr.w r3, r3, sl, lsr #29 8004a52: ea4f 02ca mov.w r2, sl, lsl #3 8004a56: 4692 mov sl, r2 8004a58: 469b mov fp, r3 8004a5a: 4623 mov r3, r4 8004a5c: eb1a 0303 adds.w r3, sl, r3 8004a60: 623b str r3, [r7, #32] 8004a62: 462b mov r3, r5 8004a64: eb4b 0303 adc.w r3, fp, r3 8004a68: 627b str r3, [r7, #36] @ 0x24 8004a6a: f04f 0200 mov.w r2, #0 8004a6e: f04f 0300 mov.w r3, #0 8004a72: e9d7 4508 ldrd r4, r5, [r7, #32] 8004a76: 4629 mov r1, r5 8004a78: 028b lsls r3, r1, #10 8004a7a: 4621 mov r1, r4 8004a7c: ea43 5391 orr.w r3, r3, r1, lsr #22 8004a80: 4621 mov r1, r4 8004a82: 028a lsls r2, r1, #10 8004a84: 4610 mov r0, r2 8004a86: 4619 mov r1, r3 8004a88: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004a8c: 2200 movs r2, #0 8004a8e: 673b str r3, [r7, #112] @ 0x70 8004a90: 677a str r2, [r7, #116] @ 0x74 8004a92: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70 8004a96: f7fb fbb5 bl 8000204 <__aeabi_uldivmod> 8004a9a: 4602 mov r2, r0 8004a9c: 460b mov r3, r1 8004a9e: 4613 mov r3, r2 8004aa0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); 8004aa4: 4b41 ldr r3, [pc, #260] @ (8004bac ) 8004aa6: 685b ldr r3, [r3, #4] 8004aa8: 0c1b lsrs r3, r3, #16 8004aaa: f003 0303 and.w r3, r3, #3 8004aae: 3301 adds r3, #1 8004ab0: 005b lsls r3, r3, #1 8004ab2: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 sysclockfreq = pllvco / pllp; 8004ab6: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004aba: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8004abe: fbb2 f3f3 udiv r3, r2, r3 8004ac2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004ac6: e0eb b.n 8004ca0 } case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004ac8: 4b38 ldr r3, [pc, #224] @ (8004bac ) 8004aca: 685b ldr r3, [r3, #4] 8004acc: f003 033f and.w r3, r3, #63 @ 0x3f 8004ad0: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004ad4: 4b35 ldr r3, [pc, #212] @ (8004bac ) 8004ad6: 685b ldr r3, [r3, #4] 8004ad8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004adc: 2b00 cmp r3, #0 8004ade: d06b beq.n 8004bb8 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004ae0: 4b32 ldr r3, [pc, #200] @ (8004bac ) 8004ae2: 685b ldr r3, [r3, #4] 8004ae4: 099b lsrs r3, r3, #6 8004ae6: 2200 movs r2, #0 8004ae8: 66bb str r3, [r7, #104] @ 0x68 8004aea: 66fa str r2, [r7, #108] @ 0x6c 8004aec: 6ebb ldr r3, [r7, #104] @ 0x68 8004aee: f3c3 0308 ubfx r3, r3, #0, #9 8004af2: 663b str r3, [r7, #96] @ 0x60 8004af4: 2300 movs r3, #0 8004af6: 667b str r3, [r7, #100] @ 0x64 8004af8: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60 8004afc: 4622 mov r2, r4 8004afe: 462b mov r3, r5 8004b00: f04f 0000 mov.w r0, #0 8004b04: f04f 0100 mov.w r1, #0 8004b08: 0159 lsls r1, r3, #5 8004b0a: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004b0e: 0150 lsls r0, r2, #5 8004b10: 4602 mov r2, r0 8004b12: 460b mov r3, r1 8004b14: 4621 mov r1, r4 8004b16: 1a51 subs r1, r2, r1 8004b18: 61b9 str r1, [r7, #24] 8004b1a: 4629 mov r1, r5 8004b1c: eb63 0301 sbc.w r3, r3, r1 8004b20: 61fb str r3, [r7, #28] 8004b22: f04f 0200 mov.w r2, #0 8004b26: f04f 0300 mov.w r3, #0 8004b2a: e9d7 ab06 ldrd sl, fp, [r7, #24] 8004b2e: 4659 mov r1, fp 8004b30: 018b lsls r3, r1, #6 8004b32: 4651 mov r1, sl 8004b34: ea43 6391 orr.w r3, r3, r1, lsr #26 8004b38: 4651 mov r1, sl 8004b3a: 018a lsls r2, r1, #6 8004b3c: 4651 mov r1, sl 8004b3e: ebb2 0801 subs.w r8, r2, r1 8004b42: 4659 mov r1, fp 8004b44: eb63 0901 sbc.w r9, r3, r1 8004b48: f04f 0200 mov.w r2, #0 8004b4c: f04f 0300 mov.w r3, #0 8004b50: ea4f 03c9 mov.w r3, r9, lsl #3 8004b54: ea43 7358 orr.w r3, r3, r8, lsr #29 8004b58: ea4f 02c8 mov.w r2, r8, lsl #3 8004b5c: 4690 mov r8, r2 8004b5e: 4699 mov r9, r3 8004b60: 4623 mov r3, r4 8004b62: eb18 0303 adds.w r3, r8, r3 8004b66: 613b str r3, [r7, #16] 8004b68: 462b mov r3, r5 8004b6a: eb49 0303 adc.w r3, r9, r3 8004b6e: 617b str r3, [r7, #20] 8004b70: f04f 0200 mov.w r2, #0 8004b74: f04f 0300 mov.w r3, #0 8004b78: e9d7 4504 ldrd r4, r5, [r7, #16] 8004b7c: 4629 mov r1, r5 8004b7e: 024b lsls r3, r1, #9 8004b80: 4621 mov r1, r4 8004b82: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004b86: 4621 mov r1, r4 8004b88: 024a lsls r2, r1, #9 8004b8a: 4610 mov r0, r2 8004b8c: 4619 mov r1, r3 8004b8e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004b92: 2200 movs r2, #0 8004b94: 65bb str r3, [r7, #88] @ 0x58 8004b96: 65fa str r2, [r7, #92] @ 0x5c 8004b98: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8004b9c: f7fb fb32 bl 8000204 <__aeabi_uldivmod> 8004ba0: 4602 mov r2, r0 8004ba2: 460b mov r3, r1 8004ba4: 4613 mov r3, r2 8004ba6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8004baa: e065 b.n 8004c78 8004bac: 40023800 .word 0x40023800 8004bb0: 00f42400 .word 0x00f42400 8004bb4: 007a1200 .word 0x007a1200 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004bb8: 4b3d ldr r3, [pc, #244] @ (8004cb0 ) 8004bba: 685b ldr r3, [r3, #4] 8004bbc: 099b lsrs r3, r3, #6 8004bbe: 2200 movs r2, #0 8004bc0: 4618 mov r0, r3 8004bc2: 4611 mov r1, r2 8004bc4: f3c0 0308 ubfx r3, r0, #0, #9 8004bc8: 653b str r3, [r7, #80] @ 0x50 8004bca: 2300 movs r3, #0 8004bcc: 657b str r3, [r7, #84] @ 0x54 8004bce: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50 8004bd2: 4642 mov r2, r8 8004bd4: 464b mov r3, r9 8004bd6: f04f 0000 mov.w r0, #0 8004bda: f04f 0100 mov.w r1, #0 8004bde: 0159 lsls r1, r3, #5 8004be0: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004be4: 0150 lsls r0, r2, #5 8004be6: 4602 mov r2, r0 8004be8: 460b mov r3, r1 8004bea: 4641 mov r1, r8 8004bec: 1a51 subs r1, r2, r1 8004bee: 60b9 str r1, [r7, #8] 8004bf0: 4649 mov r1, r9 8004bf2: eb63 0301 sbc.w r3, r3, r1 8004bf6: 60fb str r3, [r7, #12] 8004bf8: f04f 0200 mov.w r2, #0 8004bfc: f04f 0300 mov.w r3, #0 8004c00: e9d7 ab02 ldrd sl, fp, [r7, #8] 8004c04: 4659 mov r1, fp 8004c06: 018b lsls r3, r1, #6 8004c08: 4651 mov r1, sl 8004c0a: ea43 6391 orr.w r3, r3, r1, lsr #26 8004c0e: 4651 mov r1, sl 8004c10: 018a lsls r2, r1, #6 8004c12: 4651 mov r1, sl 8004c14: 1a54 subs r4, r2, r1 8004c16: 4659 mov r1, fp 8004c18: eb63 0501 sbc.w r5, r3, r1 8004c1c: f04f 0200 mov.w r2, #0 8004c20: f04f 0300 mov.w r3, #0 8004c24: 00eb lsls r3, r5, #3 8004c26: ea43 7354 orr.w r3, r3, r4, lsr #29 8004c2a: 00e2 lsls r2, r4, #3 8004c2c: 4614 mov r4, r2 8004c2e: 461d mov r5, r3 8004c30: 4643 mov r3, r8 8004c32: 18e3 adds r3, r4, r3 8004c34: 603b str r3, [r7, #0] 8004c36: 464b mov r3, r9 8004c38: eb45 0303 adc.w r3, r5, r3 8004c3c: 607b str r3, [r7, #4] 8004c3e: f04f 0200 mov.w r2, #0 8004c42: f04f 0300 mov.w r3, #0 8004c46: e9d7 4500 ldrd r4, r5, [r7] 8004c4a: 4629 mov r1, r5 8004c4c: 028b lsls r3, r1, #10 8004c4e: 4621 mov r1, r4 8004c50: ea43 5391 orr.w r3, r3, r1, lsr #22 8004c54: 4621 mov r1, r4 8004c56: 028a lsls r2, r1, #10 8004c58: 4610 mov r0, r2 8004c5a: 4619 mov r1, r3 8004c5c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004c60: 2200 movs r2, #0 8004c62: 64bb str r3, [r7, #72] @ 0x48 8004c64: 64fa str r2, [r7, #76] @ 0x4c 8004c66: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8004c6a: f7fb facb bl 8000204 <__aeabi_uldivmod> 8004c6e: 4602 mov r2, r0 8004c70: 460b mov r3, r1 8004c72: 4613 mov r3, r2 8004c74: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); 8004c78: 4b0d ldr r3, [pc, #52] @ (8004cb0 ) 8004c7a: 685b ldr r3, [r3, #4] 8004c7c: 0f1b lsrs r3, r3, #28 8004c7e: f003 0307 and.w r3, r3, #7 8004c82: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 sysclockfreq = pllvco / pllr; 8004c86: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004c8a: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8004c8e: fbb2 f3f3 udiv r3, r2, r3 8004c92: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004c96: e003 b.n 8004ca0 } default: { sysclockfreq = HSI_VALUE; 8004c98: 4b06 ldr r3, [pc, #24] @ (8004cb4 ) 8004c9a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004c9e: bf00 nop } } return sysclockfreq; 8004ca0: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 } 8004ca4: 4618 mov r0, r3 8004ca6: 37b8 adds r7, #184 @ 0xb8 8004ca8: 46bd mov sp, r7 8004caa: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8004cae: bf00 nop 8004cb0: 40023800 .word 0x40023800 8004cb4: 00f42400 .word 0x00f42400 08004cb8 : * @note This function add the PLL/PLLR factor management during PLL configuration this feature * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 8004cb8: b580 push {r7, lr} 8004cba: b086 sub sp, #24 8004cbc: af00 add r7, sp, #0 8004cbe: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8004cc0: 687b ldr r3, [r7, #4] 8004cc2: 2b00 cmp r3, #0 8004cc4: d101 bne.n 8004cca { return HAL_ERROR; 8004cc6: 2301 movs r3, #1 8004cc8: e28d b.n 80051e6 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8004cca: 687b ldr r3, [r7, #4] 8004ccc: 681b ldr r3, [r3, #0] 8004cce: f003 0301 and.w r3, r3, #1 8004cd2: 2b00 cmp r3, #0 8004cd4: f000 8083 beq.w 8004dde { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 8004cd8: 4b94 ldr r3, [pc, #592] @ (8004f2c ) 8004cda: 689b ldr r3, [r3, #8] 8004cdc: f003 030c and.w r3, r3, #12 8004ce0: 2b04 cmp r3, #4 8004ce2: d019 beq.n 8004d18 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004ce4: 4b91 ldr r3, [pc, #580] @ (8004f2c ) 8004ce6: 689b ldr r3, [r3, #8] 8004ce8: f003 030c and.w r3, r3, #12 || \ 8004cec: 2b08 cmp r3, #8 8004cee: d106 bne.n 8004cfe ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004cf0: 4b8e ldr r3, [pc, #568] @ (8004f2c ) 8004cf2: 685b ldr r3, [r3, #4] 8004cf4: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004cf8: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004cfc: d00c beq.n 8004d18 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8004cfe: 4b8b ldr r3, [pc, #556] @ (8004f2c ) 8004d00: 689b ldr r3, [r3, #8] 8004d02: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004d06: 2b0c cmp r3, #12 8004d08: d112 bne.n 8004d30 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8004d0a: 4b88 ldr r3, [pc, #544] @ (8004f2c ) 8004d0c: 685b ldr r3, [r3, #4] 8004d0e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004d12: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004d16: d10b bne.n 8004d30 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) #endif /* STM32F446xx */ { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004d18: 4b84 ldr r3, [pc, #528] @ (8004f2c ) 8004d1a: 681b ldr r3, [r3, #0] 8004d1c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004d20: 2b00 cmp r3, #0 8004d22: d05b beq.n 8004ddc 8004d24: 687b ldr r3, [r7, #4] 8004d26: 685b ldr r3, [r3, #4] 8004d28: 2b00 cmp r3, #0 8004d2a: d157 bne.n 8004ddc { return HAL_ERROR; 8004d2c: 2301 movs r3, #1 8004d2e: e25a b.n 80051e6 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8004d30: 687b ldr r3, [r7, #4] 8004d32: 685b ldr r3, [r3, #4] 8004d34: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004d38: d106 bne.n 8004d48 8004d3a: 4b7c ldr r3, [pc, #496] @ (8004f2c ) 8004d3c: 681b ldr r3, [r3, #0] 8004d3e: 4a7b ldr r2, [pc, #492] @ (8004f2c ) 8004d40: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004d44: 6013 str r3, [r2, #0] 8004d46: e01d b.n 8004d84 8004d48: 687b ldr r3, [r7, #4] 8004d4a: 685b ldr r3, [r3, #4] 8004d4c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8004d50: d10c bne.n 8004d6c 8004d52: 4b76 ldr r3, [pc, #472] @ (8004f2c ) 8004d54: 681b ldr r3, [r3, #0] 8004d56: 4a75 ldr r2, [pc, #468] @ (8004f2c ) 8004d58: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8004d5c: 6013 str r3, [r2, #0] 8004d5e: 4b73 ldr r3, [pc, #460] @ (8004f2c ) 8004d60: 681b ldr r3, [r3, #0] 8004d62: 4a72 ldr r2, [pc, #456] @ (8004f2c ) 8004d64: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004d68: 6013 str r3, [r2, #0] 8004d6a: e00b b.n 8004d84 8004d6c: 4b6f ldr r3, [pc, #444] @ (8004f2c ) 8004d6e: 681b ldr r3, [r3, #0] 8004d70: 4a6e ldr r2, [pc, #440] @ (8004f2c ) 8004d72: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8004d76: 6013 str r3, [r2, #0] 8004d78: 4b6c ldr r3, [pc, #432] @ (8004f2c ) 8004d7a: 681b ldr r3, [r3, #0] 8004d7c: 4a6b ldr r2, [pc, #428] @ (8004f2c ) 8004d7e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8004d82: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 8004d84: 687b ldr r3, [r7, #4] 8004d86: 685b ldr r3, [r3, #4] 8004d88: 2b00 cmp r3, #0 8004d8a: d013 beq.n 8004db4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004d8c: f7fc fe4c bl 8001a28 8004d90: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004d92: e008 b.n 8004da6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004d94: f7fc fe48 bl 8001a28 8004d98: 4602 mov r2, r0 8004d9a: 693b ldr r3, [r7, #16] 8004d9c: 1ad3 subs r3, r2, r3 8004d9e: 2b64 cmp r3, #100 @ 0x64 8004da0: d901 bls.n 8004da6 { return HAL_TIMEOUT; 8004da2: 2303 movs r3, #3 8004da4: e21f b.n 80051e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004da6: 4b61 ldr r3, [pc, #388] @ (8004f2c ) 8004da8: 681b ldr r3, [r3, #0] 8004daa: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004dae: 2b00 cmp r3, #0 8004db0: d0f0 beq.n 8004d94 8004db2: e014 b.n 8004dde } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004db4: f7fc fe38 bl 8001a28 8004db8: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004dba: e008 b.n 8004dce { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004dbc: f7fc fe34 bl 8001a28 8004dc0: 4602 mov r2, r0 8004dc2: 693b ldr r3, [r7, #16] 8004dc4: 1ad3 subs r3, r2, r3 8004dc6: 2b64 cmp r3, #100 @ 0x64 8004dc8: d901 bls.n 8004dce { return HAL_TIMEOUT; 8004dca: 2303 movs r3, #3 8004dcc: e20b b.n 80051e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004dce: 4b57 ldr r3, [pc, #348] @ (8004f2c ) 8004dd0: 681b ldr r3, [r3, #0] 8004dd2: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004dd6: 2b00 cmp r3, #0 8004dd8: d1f0 bne.n 8004dbc 8004dda: e000 b.n 8004dde if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004ddc: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8004dde: 687b ldr r3, [r7, #4] 8004de0: 681b ldr r3, [r3, #0] 8004de2: f003 0302 and.w r3, r3, #2 8004de6: 2b00 cmp r3, #0 8004de8: d06f beq.n 8004eca assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 8004dea: 4b50 ldr r3, [pc, #320] @ (8004f2c ) 8004dec: 689b ldr r3, [r3, #8] 8004dee: f003 030c and.w r3, r3, #12 8004df2: 2b00 cmp r3, #0 8004df4: d017 beq.n 8004e26 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004df6: 4b4d ldr r3, [pc, #308] @ (8004f2c ) 8004df8: 689b ldr r3, [r3, #8] 8004dfa: f003 030c and.w r3, r3, #12 || \ 8004dfe: 2b08 cmp r3, #8 8004e00: d105 bne.n 8004e0e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004e02: 4b4a ldr r3, [pc, #296] @ (8004f2c ) 8004e04: 685b ldr r3, [r3, #4] 8004e06: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004e0a: 2b00 cmp r3, #0 8004e0c: d00b beq.n 8004e26 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004e0e: 4b47 ldr r3, [pc, #284] @ (8004f2c ) 8004e10: 689b ldr r3, [r3, #8] 8004e12: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004e16: 2b0c cmp r3, #12 8004e18: d11c bne.n 8004e54 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004e1a: 4b44 ldr r3, [pc, #272] @ (8004f2c ) 8004e1c: 685b ldr r3, [r3, #4] 8004e1e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004e22: 2b00 cmp r3, #0 8004e24: d116 bne.n 8004e54 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) #endif /* STM32F446xx */ { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004e26: 4b41 ldr r3, [pc, #260] @ (8004f2c ) 8004e28: 681b ldr r3, [r3, #0] 8004e2a: f003 0302 and.w r3, r3, #2 8004e2e: 2b00 cmp r3, #0 8004e30: d005 beq.n 8004e3e 8004e32: 687b ldr r3, [r7, #4] 8004e34: 68db ldr r3, [r3, #12] 8004e36: 2b01 cmp r3, #1 8004e38: d001 beq.n 8004e3e { return HAL_ERROR; 8004e3a: 2301 movs r3, #1 8004e3c: e1d3 b.n 80051e6 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004e3e: 4b3b ldr r3, [pc, #236] @ (8004f2c ) 8004e40: 681b ldr r3, [r3, #0] 8004e42: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004e46: 687b ldr r3, [r7, #4] 8004e48: 691b ldr r3, [r3, #16] 8004e4a: 00db lsls r3, r3, #3 8004e4c: 4937 ldr r1, [pc, #220] @ (8004f2c ) 8004e4e: 4313 orrs r3, r2 8004e50: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004e52: e03a b.n 8004eca } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8004e54: 687b ldr r3, [r7, #4] 8004e56: 68db ldr r3, [r3, #12] 8004e58: 2b00 cmp r3, #0 8004e5a: d020 beq.n 8004e9e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8004e5c: 4b34 ldr r3, [pc, #208] @ (8004f30 ) 8004e5e: 2201 movs r2, #1 8004e60: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004e62: f7fc fde1 bl 8001a28 8004e66: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004e68: e008 b.n 8004e7c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004e6a: f7fc fddd bl 8001a28 8004e6e: 4602 mov r2, r0 8004e70: 693b ldr r3, [r7, #16] 8004e72: 1ad3 subs r3, r2, r3 8004e74: 2b02 cmp r3, #2 8004e76: d901 bls.n 8004e7c { return HAL_TIMEOUT; 8004e78: 2303 movs r3, #3 8004e7a: e1b4 b.n 80051e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004e7c: 4b2b ldr r3, [pc, #172] @ (8004f2c ) 8004e7e: 681b ldr r3, [r3, #0] 8004e80: f003 0302 and.w r3, r3, #2 8004e84: 2b00 cmp r3, #0 8004e86: d0f0 beq.n 8004e6a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004e88: 4b28 ldr r3, [pc, #160] @ (8004f2c ) 8004e8a: 681b ldr r3, [r3, #0] 8004e8c: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004e90: 687b ldr r3, [r7, #4] 8004e92: 691b ldr r3, [r3, #16] 8004e94: 00db lsls r3, r3, #3 8004e96: 4925 ldr r1, [pc, #148] @ (8004f2c ) 8004e98: 4313 orrs r3, r2 8004e9a: 600b str r3, [r1, #0] 8004e9c: e015 b.n 8004eca } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8004e9e: 4b24 ldr r3, [pc, #144] @ (8004f30 ) 8004ea0: 2200 movs r2, #0 8004ea2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004ea4: f7fc fdc0 bl 8001a28 8004ea8: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004eaa: e008 b.n 8004ebe { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004eac: f7fc fdbc bl 8001a28 8004eb0: 4602 mov r2, r0 8004eb2: 693b ldr r3, [r7, #16] 8004eb4: 1ad3 subs r3, r2, r3 8004eb6: 2b02 cmp r3, #2 8004eb8: d901 bls.n 8004ebe { return HAL_TIMEOUT; 8004eba: 2303 movs r3, #3 8004ebc: e193 b.n 80051e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004ebe: 4b1b ldr r3, [pc, #108] @ (8004f2c ) 8004ec0: 681b ldr r3, [r3, #0] 8004ec2: f003 0302 and.w r3, r3, #2 8004ec6: 2b00 cmp r3, #0 8004ec8: d1f0 bne.n 8004eac } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8004eca: 687b ldr r3, [r7, #4] 8004ecc: 681b ldr r3, [r3, #0] 8004ece: f003 0308 and.w r3, r3, #8 8004ed2: 2b00 cmp r3, #0 8004ed4: d036 beq.n 8004f44 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 8004ed6: 687b ldr r3, [r7, #4] 8004ed8: 695b ldr r3, [r3, #20] 8004eda: 2b00 cmp r3, #0 8004edc: d016 beq.n 8004f0c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8004ede: 4b15 ldr r3, [pc, #84] @ (8004f34 ) 8004ee0: 2201 movs r2, #1 8004ee2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004ee4: f7fc fda0 bl 8001a28 8004ee8: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004eea: e008 b.n 8004efe { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004eec: f7fc fd9c bl 8001a28 8004ef0: 4602 mov r2, r0 8004ef2: 693b ldr r3, [r7, #16] 8004ef4: 1ad3 subs r3, r2, r3 8004ef6: 2b02 cmp r3, #2 8004ef8: d901 bls.n 8004efe { return HAL_TIMEOUT; 8004efa: 2303 movs r3, #3 8004efc: e173 b.n 80051e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004efe: 4b0b ldr r3, [pc, #44] @ (8004f2c ) 8004f00: 6f5b ldr r3, [r3, #116] @ 0x74 8004f02: f003 0302 and.w r3, r3, #2 8004f06: 2b00 cmp r3, #0 8004f08: d0f0 beq.n 8004eec 8004f0a: e01b b.n 8004f44 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8004f0c: 4b09 ldr r3, [pc, #36] @ (8004f34 ) 8004f0e: 2200 movs r2, #0 8004f10: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004f12: f7fc fd89 bl 8001a28 8004f16: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004f18: e00e b.n 8004f38 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004f1a: f7fc fd85 bl 8001a28 8004f1e: 4602 mov r2, r0 8004f20: 693b ldr r3, [r7, #16] 8004f22: 1ad3 subs r3, r2, r3 8004f24: 2b02 cmp r3, #2 8004f26: d907 bls.n 8004f38 { return HAL_TIMEOUT; 8004f28: 2303 movs r3, #3 8004f2a: e15c b.n 80051e6 8004f2c: 40023800 .word 0x40023800 8004f30: 42470000 .word 0x42470000 8004f34: 42470e80 .word 0x42470e80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004f38: 4b8a ldr r3, [pc, #552] @ (8005164 ) 8004f3a: 6f5b ldr r3, [r3, #116] @ 0x74 8004f3c: f003 0302 and.w r3, r3, #2 8004f40: 2b00 cmp r3, #0 8004f42: d1ea bne.n 8004f1a } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8004f44: 687b ldr r3, [r7, #4] 8004f46: 681b ldr r3, [r3, #0] 8004f48: f003 0304 and.w r3, r3, #4 8004f4c: 2b00 cmp r3, #0 8004f4e: f000 8097 beq.w 8005080 { FlagStatus pwrclkchanged = RESET; 8004f52: 2300 movs r3, #0 8004f54: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8004f56: 4b83 ldr r3, [pc, #524] @ (8005164 ) 8004f58: 6c1b ldr r3, [r3, #64] @ 0x40 8004f5a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004f5e: 2b00 cmp r3, #0 8004f60: d10f bne.n 8004f82 { __HAL_RCC_PWR_CLK_ENABLE(); 8004f62: 2300 movs r3, #0 8004f64: 60bb str r3, [r7, #8] 8004f66: 4b7f ldr r3, [pc, #508] @ (8005164 ) 8004f68: 6c1b ldr r3, [r3, #64] @ 0x40 8004f6a: 4a7e ldr r2, [pc, #504] @ (8005164 ) 8004f6c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004f70: 6413 str r3, [r2, #64] @ 0x40 8004f72: 4b7c ldr r3, [pc, #496] @ (8005164 ) 8004f74: 6c1b ldr r3, [r3, #64] @ 0x40 8004f76: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004f7a: 60bb str r3, [r7, #8] 8004f7c: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8004f7e: 2301 movs r3, #1 8004f80: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004f82: 4b79 ldr r3, [pc, #484] @ (8005168 ) 8004f84: 681b ldr r3, [r3, #0] 8004f86: f403 7380 and.w r3, r3, #256 @ 0x100 8004f8a: 2b00 cmp r3, #0 8004f8c: d118 bne.n 8004fc0 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8004f8e: 4b76 ldr r3, [pc, #472] @ (8005168 ) 8004f90: 681b ldr r3, [r3, #0] 8004f92: 4a75 ldr r2, [pc, #468] @ (8005168 ) 8004f94: f443 7380 orr.w r3, r3, #256 @ 0x100 8004f98: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8004f9a: f7fc fd45 bl 8001a28 8004f9e: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004fa0: e008 b.n 8004fb4 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004fa2: f7fc fd41 bl 8001a28 8004fa6: 4602 mov r2, r0 8004fa8: 693b ldr r3, [r7, #16] 8004faa: 1ad3 subs r3, r2, r3 8004fac: 2b02 cmp r3, #2 8004fae: d901 bls.n 8004fb4 { return HAL_TIMEOUT; 8004fb0: 2303 movs r3, #3 8004fb2: e118 b.n 80051e6 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004fb4: 4b6c ldr r3, [pc, #432] @ (8005168 ) 8004fb6: 681b ldr r3, [r3, #0] 8004fb8: f403 7380 and.w r3, r3, #256 @ 0x100 8004fbc: 2b00 cmp r3, #0 8004fbe: d0f0 beq.n 8004fa2 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8004fc0: 687b ldr r3, [r7, #4] 8004fc2: 689b ldr r3, [r3, #8] 8004fc4: 2b01 cmp r3, #1 8004fc6: d106 bne.n 8004fd6 8004fc8: 4b66 ldr r3, [pc, #408] @ (8005164 ) 8004fca: 6f1b ldr r3, [r3, #112] @ 0x70 8004fcc: 4a65 ldr r2, [pc, #404] @ (8005164 ) 8004fce: f043 0301 orr.w r3, r3, #1 8004fd2: 6713 str r3, [r2, #112] @ 0x70 8004fd4: e01c b.n 8005010 8004fd6: 687b ldr r3, [r7, #4] 8004fd8: 689b ldr r3, [r3, #8] 8004fda: 2b05 cmp r3, #5 8004fdc: d10c bne.n 8004ff8 8004fde: 4b61 ldr r3, [pc, #388] @ (8005164 ) 8004fe0: 6f1b ldr r3, [r3, #112] @ 0x70 8004fe2: 4a60 ldr r2, [pc, #384] @ (8005164 ) 8004fe4: f043 0304 orr.w r3, r3, #4 8004fe8: 6713 str r3, [r2, #112] @ 0x70 8004fea: 4b5e ldr r3, [pc, #376] @ (8005164 ) 8004fec: 6f1b ldr r3, [r3, #112] @ 0x70 8004fee: 4a5d ldr r2, [pc, #372] @ (8005164 ) 8004ff0: f043 0301 orr.w r3, r3, #1 8004ff4: 6713 str r3, [r2, #112] @ 0x70 8004ff6: e00b b.n 8005010 8004ff8: 4b5a ldr r3, [pc, #360] @ (8005164 ) 8004ffa: 6f1b ldr r3, [r3, #112] @ 0x70 8004ffc: 4a59 ldr r2, [pc, #356] @ (8005164 ) 8004ffe: f023 0301 bic.w r3, r3, #1 8005002: 6713 str r3, [r2, #112] @ 0x70 8005004: 4b57 ldr r3, [pc, #348] @ (8005164 ) 8005006: 6f1b ldr r3, [r3, #112] @ 0x70 8005008: 4a56 ldr r2, [pc, #344] @ (8005164 ) 800500a: f023 0304 bic.w r3, r3, #4 800500e: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8005010: 687b ldr r3, [r7, #4] 8005012: 689b ldr r3, [r3, #8] 8005014: 2b00 cmp r3, #0 8005016: d015 beq.n 8005044 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005018: f7fc fd06 bl 8001a28 800501c: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800501e: e00a b.n 8005036 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005020: f7fc fd02 bl 8001a28 8005024: 4602 mov r2, r0 8005026: 693b ldr r3, [r7, #16] 8005028: 1ad3 subs r3, r2, r3 800502a: f241 3288 movw r2, #5000 @ 0x1388 800502e: 4293 cmp r3, r2 8005030: d901 bls.n 8005036 { return HAL_TIMEOUT; 8005032: 2303 movs r3, #3 8005034: e0d7 b.n 80051e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005036: 4b4b ldr r3, [pc, #300] @ (8005164 ) 8005038: 6f1b ldr r3, [r3, #112] @ 0x70 800503a: f003 0302 and.w r3, r3, #2 800503e: 2b00 cmp r3, #0 8005040: d0ee beq.n 8005020 8005042: e014 b.n 800506e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005044: f7fc fcf0 bl 8001a28 8005048: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800504a: e00a b.n 8005062 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800504c: f7fc fcec bl 8001a28 8005050: 4602 mov r2, r0 8005052: 693b ldr r3, [r7, #16] 8005054: 1ad3 subs r3, r2, r3 8005056: f241 3288 movw r2, #5000 @ 0x1388 800505a: 4293 cmp r3, r2 800505c: d901 bls.n 8005062 { return HAL_TIMEOUT; 800505e: 2303 movs r3, #3 8005060: e0c1 b.n 80051e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8005062: 4b40 ldr r3, [pc, #256] @ (8005164 ) 8005064: 6f1b ldr r3, [r3, #112] @ 0x70 8005066: f003 0302 and.w r3, r3, #2 800506a: 2b00 cmp r3, #0 800506c: d1ee bne.n 800504c } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 800506e: 7dfb ldrb r3, [r7, #23] 8005070: 2b01 cmp r3, #1 8005072: d105 bne.n 8005080 { __HAL_RCC_PWR_CLK_DISABLE(); 8005074: 4b3b ldr r3, [pc, #236] @ (8005164 ) 8005076: 6c1b ldr r3, [r3, #64] @ 0x40 8005078: 4a3a ldr r2, [pc, #232] @ (8005164 ) 800507a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800507e: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8005080: 687b ldr r3, [r7, #4] 8005082: 699b ldr r3, [r3, #24] 8005084: 2b00 cmp r3, #0 8005086: f000 80ad beq.w 80051e4 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 800508a: 4b36 ldr r3, [pc, #216] @ (8005164 ) 800508c: 689b ldr r3, [r3, #8] 800508e: f003 030c and.w r3, r3, #12 8005092: 2b08 cmp r3, #8 8005094: d060 beq.n 8005158 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8005096: 687b ldr r3, [r7, #4] 8005098: 699b ldr r3, [r3, #24] 800509a: 2b02 cmp r3, #2 800509c: d145 bne.n 800512a assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800509e: 4b33 ldr r3, [pc, #204] @ (800516c ) 80050a0: 2200 movs r2, #0 80050a2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80050a4: f7fc fcc0 bl 8001a28 80050a8: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80050aa: e008 b.n 80050be { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80050ac: f7fc fcbc bl 8001a28 80050b0: 4602 mov r2, r0 80050b2: 693b ldr r3, [r7, #16] 80050b4: 1ad3 subs r3, r2, r3 80050b6: 2b02 cmp r3, #2 80050b8: d901 bls.n 80050be { return HAL_TIMEOUT; 80050ba: 2303 movs r3, #3 80050bc: e093 b.n 80051e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80050be: 4b29 ldr r3, [pc, #164] @ (8005164 ) 80050c0: 681b ldr r3, [r3, #0] 80050c2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80050c6: 2b00 cmp r3, #0 80050c8: d1f0 bne.n 80050ac } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 80050ca: 687b ldr r3, [r7, #4] 80050cc: 69da ldr r2, [r3, #28] 80050ce: 687b ldr r3, [r7, #4] 80050d0: 6a1b ldr r3, [r3, #32] 80050d2: 431a orrs r2, r3 80050d4: 687b ldr r3, [r7, #4] 80050d6: 6a5b ldr r3, [r3, #36] @ 0x24 80050d8: 019b lsls r3, r3, #6 80050da: 431a orrs r2, r3 80050dc: 687b ldr r3, [r7, #4] 80050de: 6a9b ldr r3, [r3, #40] @ 0x28 80050e0: 085b lsrs r3, r3, #1 80050e2: 3b01 subs r3, #1 80050e4: 041b lsls r3, r3, #16 80050e6: 431a orrs r2, r3 80050e8: 687b ldr r3, [r7, #4] 80050ea: 6adb ldr r3, [r3, #44] @ 0x2c 80050ec: 061b lsls r3, r3, #24 80050ee: 431a orrs r2, r3 80050f0: 687b ldr r3, [r7, #4] 80050f2: 6b1b ldr r3, [r3, #48] @ 0x30 80050f4: 071b lsls r3, r3, #28 80050f6: 491b ldr r1, [pc, #108] @ (8005164 ) 80050f8: 4313 orrs r3, r2 80050fa: 604b str r3, [r1, #4] (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80050fc: 4b1b ldr r3, [pc, #108] @ (800516c ) 80050fe: 2201 movs r2, #1 8005100: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005102: f7fc fc91 bl 8001a28 8005106: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8005108: e008 b.n 800511c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800510a: f7fc fc8d bl 8001a28 800510e: 4602 mov r2, r0 8005110: 693b ldr r3, [r7, #16] 8005112: 1ad3 subs r3, r2, r3 8005114: 2b02 cmp r3, #2 8005116: d901 bls.n 800511c { return HAL_TIMEOUT; 8005118: 2303 movs r3, #3 800511a: e064 b.n 80051e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800511c: 4b11 ldr r3, [pc, #68] @ (8005164 ) 800511e: 681b ldr r3, [r3, #0] 8005120: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005124: 2b00 cmp r3, #0 8005126: d0f0 beq.n 800510a 8005128: e05c b.n 80051e4 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800512a: 4b10 ldr r3, [pc, #64] @ (800516c ) 800512c: 2200 movs r2, #0 800512e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005130: f7fc fc7a bl 8001a28 8005134: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005136: e008 b.n 800514a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005138: f7fc fc76 bl 8001a28 800513c: 4602 mov r2, r0 800513e: 693b ldr r3, [r7, #16] 8005140: 1ad3 subs r3, r2, r3 8005142: 2b02 cmp r3, #2 8005144: d901 bls.n 800514a { return HAL_TIMEOUT; 8005146: 2303 movs r3, #3 8005148: e04d b.n 80051e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800514a: 4b06 ldr r3, [pc, #24] @ (8005164 ) 800514c: 681b ldr r3, [r3, #0] 800514e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005152: 2b00 cmp r3, #0 8005154: d1f0 bne.n 8005138 8005156: e045 b.n 80051e4 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8005158: 687b ldr r3, [r7, #4] 800515a: 699b ldr r3, [r3, #24] 800515c: 2b01 cmp r3, #1 800515e: d107 bne.n 8005170 { return HAL_ERROR; 8005160: 2301 movs r3, #1 8005162: e040 b.n 80051e6 8005164: 40023800 .word 0x40023800 8005168: 40007000 .word 0x40007000 800516c: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 8005170: 4b1f ldr r3, [pc, #124] @ (80051f0 ) 8005172: 685b ldr r3, [r3, #4] 8005174: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8005176: 687b ldr r3, [r7, #4] 8005178: 699b ldr r3, [r3, #24] 800517a: 2b01 cmp r3, #1 800517c: d030 beq.n 80051e0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800517e: 68fb ldr r3, [r7, #12] 8005180: f403 0280 and.w r2, r3, #4194304 @ 0x400000 8005184: 687b ldr r3, [r7, #4] 8005186: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8005188: 429a cmp r2, r3 800518a: d129 bne.n 80051e0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 800518c: 68fb ldr r3, [r7, #12] 800518e: f003 023f and.w r2, r3, #63 @ 0x3f 8005192: 687b ldr r3, [r7, #4] 8005194: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8005196: 429a cmp r2, r3 8005198: d122 bne.n 80051e0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 800519a: 68fa ldr r2, [r7, #12] 800519c: f647 73c0 movw r3, #32704 @ 0x7fc0 80051a0: 4013 ands r3, r2 80051a2: 687a ldr r2, [r7, #4] 80051a4: 6a52 ldr r2, [r2, #36] @ 0x24 80051a6: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80051a8: 4293 cmp r3, r2 80051aa: d119 bne.n 80051e0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 80051ac: 68fb ldr r3, [r7, #12] 80051ae: f403 3240 and.w r2, r3, #196608 @ 0x30000 80051b2: 687b ldr r3, [r7, #4] 80051b4: 6a9b ldr r3, [r3, #40] @ 0x28 80051b6: 085b lsrs r3, r3, #1 80051b8: 3b01 subs r3, #1 80051ba: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 80051bc: 429a cmp r2, r3 80051be: d10f bne.n 80051e0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 80051c0: 68fb ldr r3, [r7, #12] 80051c2: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 80051c6: 687b ldr r3, [r7, #4] 80051c8: 6adb ldr r3, [r3, #44] @ 0x2c 80051ca: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 80051cc: 429a cmp r2, r3 80051ce: d107 bne.n 80051e0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) 80051d0: 68fb ldr r3, [r7, #12] 80051d2: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000 80051d6: 687b ldr r3, [r7, #4] 80051d8: 6b1b ldr r3, [r3, #48] @ 0x30 80051da: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 80051dc: 429a cmp r2, r3 80051de: d001 beq.n 80051e4 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; 80051e0: 2301 movs r3, #1 80051e2: e000 b.n 80051e6 } } } } return HAL_OK; 80051e4: 2300 movs r3, #0 } 80051e6: 4618 mov r0, r3 80051e8: 3718 adds r7, #24 80051ea: 46bd mov sp, r7 80051ec: bd80 pop {r7, pc} 80051ee: bf00 nop 80051f0: 40023800 .word 0x40023800 080051f4 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 80051f4: b580 push {r7, lr} 80051f6: b082 sub sp, #8 80051f8: af00 add r7, sp, #0 80051fa: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 80051fc: 687b ldr r3, [r7, #4] 80051fe: 2b00 cmp r3, #0 8005200: d101 bne.n 8005206 { return HAL_ERROR; 8005202: 2301 movs r3, #1 8005204: e041 b.n 800528a assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8005206: 687b ldr r3, [r7, #4] 8005208: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800520c: b2db uxtb r3, r3 800520e: 2b00 cmp r3, #0 8005210: d106 bne.n 8005220 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005212: 687b ldr r3, [r7, #4] 8005214: 2200 movs r2, #0 8005216: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 800521a: 6878 ldr r0, [r7, #4] 800521c: f7fb ff6a bl 80010f4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005220: 687b ldr r3, [r7, #4] 8005222: 2202 movs r2, #2 8005224: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005228: 687b ldr r3, [r7, #4] 800522a: 681a ldr r2, [r3, #0] 800522c: 687b ldr r3, [r7, #4] 800522e: 3304 adds r3, #4 8005230: 4619 mov r1, r3 8005232: 4610 mov r0, r2 8005234: f000 f930 bl 8005498 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005238: 687b ldr r3, [r7, #4] 800523a: 2201 movs r2, #1 800523c: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005240: 687b ldr r3, [r7, #4] 8005242: 2201 movs r2, #1 8005244: f883 203e strb.w r2, [r3, #62] @ 0x3e 8005248: 687b ldr r3, [r7, #4] 800524a: 2201 movs r2, #1 800524c: f883 203f strb.w r2, [r3, #63] @ 0x3f 8005250: 687b ldr r3, [r7, #4] 8005252: 2201 movs r2, #1 8005254: f883 2040 strb.w r2, [r3, #64] @ 0x40 8005258: 687b ldr r3, [r7, #4] 800525a: 2201 movs r2, #1 800525c: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005260: 687b ldr r3, [r7, #4] 8005262: 2201 movs r2, #1 8005264: f883 2042 strb.w r2, [r3, #66] @ 0x42 8005268: 687b ldr r3, [r7, #4] 800526a: 2201 movs r2, #1 800526c: f883 2043 strb.w r2, [r3, #67] @ 0x43 8005270: 687b ldr r3, [r7, #4] 8005272: 2201 movs r2, #1 8005274: f883 2044 strb.w r2, [r3, #68] @ 0x44 8005278: 687b ldr r3, [r7, #4] 800527a: 2201 movs r2, #1 800527c: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005280: 687b ldr r3, [r7, #4] 8005282: 2201 movs r2, #1 8005284: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8005288: 2300 movs r3, #0 } 800528a: 4618 mov r0, r3 800528c: 3708 adds r7, #8 800528e: 46bd mov sp, r7 8005290: bd80 pop {r7, pc} 08005292 : * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { 8005292: b580 push {r7, lr} 8005294: b086 sub sp, #24 8005296: af00 add r7, sp, #0 8005298: 6078 str r0, [r7, #4] 800529a: 6039 str r1, [r7, #0] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) 800529c: 687b ldr r3, [r7, #4] 800529e: 2b00 cmp r3, #0 80052a0: d101 bne.n 80052a6 { return HAL_ERROR; 80052a2: 2301 movs r3, #1 80052a4: e097 b.n 80053d6 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) 80052a6: 687b ldr r3, [r7, #4] 80052a8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80052ac: b2db uxtb r3, r3 80052ae: 2b00 cmp r3, #0 80052b0: d106 bne.n 80052c0 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80052b2: 687b ldr r3, [r7, #4] 80052b4: 2200 movs r2, #0 80052b6: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); 80052ba: 6878 ldr r0, [r7, #4] 80052bc: f7fb ff3a bl 8001134 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80052c0: 687b ldr r3, [r7, #4] 80052c2: 2202 movs r2, #2 80052c4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); 80052c8: 687b ldr r3, [r7, #4] 80052ca: 681b ldr r3, [r3, #0] 80052cc: 689b ldr r3, [r3, #8] 80052ce: 687a ldr r2, [r7, #4] 80052d0: 6812 ldr r2, [r2, #0] 80052d2: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80052d6: f023 0307 bic.w r3, r3, #7 80052da: 6093 str r3, [r2, #8] /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80052dc: 687b ldr r3, [r7, #4] 80052de: 681a ldr r2, [r3, #0] 80052e0: 687b ldr r3, [r7, #4] 80052e2: 3304 adds r3, #4 80052e4: 4619 mov r1, r3 80052e6: 4610 mov r0, r2 80052e8: f000 f8d6 bl 8005498 /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80052ec: 687b ldr r3, [r7, #4] 80052ee: 681b ldr r3, [r3, #0] 80052f0: 689b ldr r3, [r3, #8] 80052f2: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; 80052f4: 687b ldr r3, [r7, #4] 80052f6: 681b ldr r3, [r3, #0] 80052f8: 699b ldr r3, [r3, #24] 80052fa: 613b str r3, [r7, #16] /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; 80052fc: 687b ldr r3, [r7, #4] 80052fe: 681b ldr r3, [r3, #0] 8005300: 6a1b ldr r3, [r3, #32] 8005302: 60fb str r3, [r7, #12] /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; 8005304: 683b ldr r3, [r7, #0] 8005306: 681b ldr r3, [r3, #0] 8005308: 697a ldr r2, [r7, #20] 800530a: 4313 orrs r3, r2 800530c: 617b str r3, [r7, #20] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 800530e: 693b ldr r3, [r7, #16] 8005310: f423 7340 bic.w r3, r3, #768 @ 0x300 8005314: f023 0303 bic.w r3, r3, #3 8005318: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); 800531a: 683b ldr r3, [r7, #0] 800531c: 689a ldr r2, [r3, #8] 800531e: 683b ldr r3, [r7, #0] 8005320: 699b ldr r3, [r3, #24] 8005322: 021b lsls r3, r3, #8 8005324: 4313 orrs r3, r2 8005326: 693a ldr r2, [r7, #16] 8005328: 4313 orrs r3, r2 800532a: 613b str r3, [r7, #16] /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 800532c: 693b ldr r3, [r7, #16] 800532e: f423 6340 bic.w r3, r3, #3072 @ 0xc00 8005332: f023 030c bic.w r3, r3, #12 8005336: 613b str r3, [r7, #16] tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 8005338: 693b ldr r3, [r7, #16] 800533a: f423 4370 bic.w r3, r3, #61440 @ 0xf000 800533e: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8005342: 613b str r3, [r7, #16] tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); 8005344: 683b ldr r3, [r7, #0] 8005346: 68da ldr r2, [r3, #12] 8005348: 683b ldr r3, [r7, #0] 800534a: 69db ldr r3, [r3, #28] 800534c: 021b lsls r3, r3, #8 800534e: 4313 orrs r3, r2 8005350: 693a ldr r2, [r7, #16] 8005352: 4313 orrs r3, r2 8005354: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); 8005356: 683b ldr r3, [r7, #0] 8005358: 691b ldr r3, [r3, #16] 800535a: 011a lsls r2, r3, #4 800535c: 683b ldr r3, [r7, #0] 800535e: 6a1b ldr r3, [r3, #32] 8005360: 031b lsls r3, r3, #12 8005362: 4313 orrs r3, r2 8005364: 693a ldr r2, [r7, #16] 8005366: 4313 orrs r3, r2 8005368: 613b str r3, [r7, #16] /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 800536a: 68fb ldr r3, [r7, #12] 800536c: f023 0322 bic.w r3, r3, #34 @ 0x22 8005370: 60fb str r3, [r7, #12] tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 8005372: 68fb ldr r3, [r7, #12] 8005374: f023 0388 bic.w r3, r3, #136 @ 0x88 8005378: 60fb str r3, [r7, #12] tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); 800537a: 683b ldr r3, [r7, #0] 800537c: 685a ldr r2, [r3, #4] 800537e: 683b ldr r3, [r7, #0] 8005380: 695b ldr r3, [r3, #20] 8005382: 011b lsls r3, r3, #4 8005384: 4313 orrs r3, r2 8005386: 68fa ldr r2, [r7, #12] 8005388: 4313 orrs r3, r2 800538a: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800538c: 687b ldr r3, [r7, #4] 800538e: 681b ldr r3, [r3, #0] 8005390: 697a ldr r2, [r7, #20] 8005392: 609a str r2, [r3, #8] /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; 8005394: 687b ldr r3, [r7, #4] 8005396: 681b ldr r3, [r3, #0] 8005398: 693a ldr r2, [r7, #16] 800539a: 619a str r2, [r3, #24] /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; 800539c: 687b ldr r3, [r7, #4] 800539e: 681b ldr r3, [r3, #0] 80053a0: 68fa ldr r2, [r7, #12] 80053a2: 621a str r2, [r3, #32] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 80053a4: 687b ldr r3, [r7, #4] 80053a6: 2201 movs r2, #1 80053a8: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 80053ac: 687b ldr r3, [r7, #4] 80053ae: 2201 movs r2, #1 80053b0: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 80053b4: 687b ldr r3, [r7, #4] 80053b6: 2201 movs r2, #1 80053b8: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 80053bc: 687b ldr r3, [r7, #4] 80053be: 2201 movs r2, #1 80053c0: f883 2042 strb.w r2, [r3, #66] @ 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 80053c4: 687b ldr r3, [r7, #4] 80053c6: 2201 movs r2, #1 80053c8: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80053cc: 687b ldr r3, [r7, #4] 80053ce: 2201 movs r2, #1 80053d0: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80053d4: 2300 movs r3, #0 } 80053d6: 4618 mov r0, r3 80053d8: 3718 adds r7, #24 80053da: 46bd mov sp, r7 80053dc: bd80 pop {r7, pc} ... 080053e0 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80053e0: b580 push {r7, lr} 80053e2: b086 sub sp, #24 80053e4: af00 add r7, sp, #0 80053e6: 60f8 str r0, [r7, #12] 80053e8: 60b9 str r1, [r7, #8] 80053ea: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80053ec: 2300 movs r3, #0 80053ee: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 80053f0: 68fb ldr r3, [r7, #12] 80053f2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80053f6: 2b01 cmp r3, #1 80053f8: d101 bne.n 80053fe 80053fa: 2302 movs r3, #2 80053fc: e048 b.n 8005490 80053fe: 68fb ldr r3, [r7, #12] 8005400: 2201 movs r2, #1 8005402: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8005406: 687b ldr r3, [r7, #4] 8005408: 2b0c cmp r3, #12 800540a: d839 bhi.n 8005480 800540c: a201 add r2, pc, #4 @ (adr r2, 8005414 ) 800540e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005412: bf00 nop 8005414: 08005449 .word 0x08005449 8005418: 08005481 .word 0x08005481 800541c: 08005481 .word 0x08005481 8005420: 08005481 .word 0x08005481 8005424: 08005457 .word 0x08005457 8005428: 08005481 .word 0x08005481 800542c: 08005481 .word 0x08005481 8005430: 08005481 .word 0x08005481 8005434: 08005465 .word 0x08005465 8005438: 08005481 .word 0x08005481 800543c: 08005481 .word 0x08005481 8005440: 08005481 .word 0x08005481 8005444: 08005473 .word 0x08005473 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8005448: 68fb ldr r3, [r7, #12] 800544a: 681b ldr r3, [r3, #0] 800544c: 68b9 ldr r1, [r7, #8] 800544e: 4618 mov r0, r3 8005450: f000 f8c8 bl 80055e4 break; 8005454: e017 b.n 8005486 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8005456: 68fb ldr r3, [r7, #12] 8005458: 681b ldr r3, [r3, #0] 800545a: 68b9 ldr r1, [r7, #8] 800545c: 4618 mov r0, r3 800545e: f000 f931 bl 80056c4 break; 8005462: e010 b.n 8005486 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8005464: 68fb ldr r3, [r7, #12] 8005466: 681b ldr r3, [r3, #0] 8005468: 68b9 ldr r1, [r7, #8] 800546a: 4618 mov r0, r3 800546c: f000 f9a0 bl 80057b0 break; 8005470: e009 b.n 8005486 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8005472: 68fb ldr r3, [r7, #12] 8005474: 681b ldr r3, [r3, #0] 8005476: 68b9 ldr r1, [r7, #8] 8005478: 4618 mov r0, r3 800547a: f000 fa0d bl 8005898 break; 800547e: e002 b.n 8005486 } default: status = HAL_ERROR; 8005480: 2301 movs r3, #1 8005482: 75fb strb r3, [r7, #23] break; 8005484: bf00 nop } __HAL_UNLOCK(htim); 8005486: 68fb ldr r3, [r7, #12] 8005488: 2200 movs r2, #0 800548a: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800548e: 7dfb ldrb r3, [r7, #23] } 8005490: 4618 mov r0, r3 8005492: 3718 adds r7, #24 8005494: 46bd mov sp, r7 8005496: bd80 pop {r7, pc} 08005498 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8005498: b480 push {r7} 800549a: b085 sub sp, #20 800549c: af00 add r7, sp, #0 800549e: 6078 str r0, [r7, #4] 80054a0: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80054a2: 687b ldr r3, [r7, #4] 80054a4: 681b ldr r3, [r3, #0] 80054a6: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80054a8: 687b ldr r3, [r7, #4] 80054aa: 4a43 ldr r2, [pc, #268] @ (80055b8 ) 80054ac: 4293 cmp r3, r2 80054ae: d013 beq.n 80054d8 80054b0: 687b ldr r3, [r7, #4] 80054b2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80054b6: d00f beq.n 80054d8 80054b8: 687b ldr r3, [r7, #4] 80054ba: 4a40 ldr r2, [pc, #256] @ (80055bc ) 80054bc: 4293 cmp r3, r2 80054be: d00b beq.n 80054d8 80054c0: 687b ldr r3, [r7, #4] 80054c2: 4a3f ldr r2, [pc, #252] @ (80055c0 ) 80054c4: 4293 cmp r3, r2 80054c6: d007 beq.n 80054d8 80054c8: 687b ldr r3, [r7, #4] 80054ca: 4a3e ldr r2, [pc, #248] @ (80055c4 ) 80054cc: 4293 cmp r3, r2 80054ce: d003 beq.n 80054d8 80054d0: 687b ldr r3, [r7, #4] 80054d2: 4a3d ldr r2, [pc, #244] @ (80055c8 ) 80054d4: 4293 cmp r3, r2 80054d6: d108 bne.n 80054ea { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80054d8: 68fb ldr r3, [r7, #12] 80054da: f023 0370 bic.w r3, r3, #112 @ 0x70 80054de: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80054e0: 683b ldr r3, [r7, #0] 80054e2: 685b ldr r3, [r3, #4] 80054e4: 68fa ldr r2, [r7, #12] 80054e6: 4313 orrs r3, r2 80054e8: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80054ea: 687b ldr r3, [r7, #4] 80054ec: 4a32 ldr r2, [pc, #200] @ (80055b8 ) 80054ee: 4293 cmp r3, r2 80054f0: d02b beq.n 800554a 80054f2: 687b ldr r3, [r7, #4] 80054f4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80054f8: d027 beq.n 800554a 80054fa: 687b ldr r3, [r7, #4] 80054fc: 4a2f ldr r2, [pc, #188] @ (80055bc ) 80054fe: 4293 cmp r3, r2 8005500: d023 beq.n 800554a 8005502: 687b ldr r3, [r7, #4] 8005504: 4a2e ldr r2, [pc, #184] @ (80055c0 ) 8005506: 4293 cmp r3, r2 8005508: d01f beq.n 800554a 800550a: 687b ldr r3, [r7, #4] 800550c: 4a2d ldr r2, [pc, #180] @ (80055c4 ) 800550e: 4293 cmp r3, r2 8005510: d01b beq.n 800554a 8005512: 687b ldr r3, [r7, #4] 8005514: 4a2c ldr r2, [pc, #176] @ (80055c8 ) 8005516: 4293 cmp r3, r2 8005518: d017 beq.n 800554a 800551a: 687b ldr r3, [r7, #4] 800551c: 4a2b ldr r2, [pc, #172] @ (80055cc ) 800551e: 4293 cmp r3, r2 8005520: d013 beq.n 800554a 8005522: 687b ldr r3, [r7, #4] 8005524: 4a2a ldr r2, [pc, #168] @ (80055d0 ) 8005526: 4293 cmp r3, r2 8005528: d00f beq.n 800554a 800552a: 687b ldr r3, [r7, #4] 800552c: 4a29 ldr r2, [pc, #164] @ (80055d4 ) 800552e: 4293 cmp r3, r2 8005530: d00b beq.n 800554a 8005532: 687b ldr r3, [r7, #4] 8005534: 4a28 ldr r2, [pc, #160] @ (80055d8 ) 8005536: 4293 cmp r3, r2 8005538: d007 beq.n 800554a 800553a: 687b ldr r3, [r7, #4] 800553c: 4a27 ldr r2, [pc, #156] @ (80055dc ) 800553e: 4293 cmp r3, r2 8005540: d003 beq.n 800554a 8005542: 687b ldr r3, [r7, #4] 8005544: 4a26 ldr r2, [pc, #152] @ (80055e0 ) 8005546: 4293 cmp r3, r2 8005548: d108 bne.n 800555c { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800554a: 68fb ldr r3, [r7, #12] 800554c: f423 7340 bic.w r3, r3, #768 @ 0x300 8005550: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8005552: 683b ldr r3, [r7, #0] 8005554: 68db ldr r3, [r3, #12] 8005556: 68fa ldr r2, [r7, #12] 8005558: 4313 orrs r3, r2 800555a: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800555c: 68fb ldr r3, [r7, #12] 800555e: f023 0280 bic.w r2, r3, #128 @ 0x80 8005562: 683b ldr r3, [r7, #0] 8005564: 695b ldr r3, [r3, #20] 8005566: 4313 orrs r3, r2 8005568: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800556a: 683b ldr r3, [r7, #0] 800556c: 689a ldr r2, [r3, #8] 800556e: 687b ldr r3, [r7, #4] 8005570: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8005572: 683b ldr r3, [r7, #0] 8005574: 681a ldr r2, [r3, #0] 8005576: 687b ldr r3, [r7, #4] 8005578: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800557a: 687b ldr r3, [r7, #4] 800557c: 4a0e ldr r2, [pc, #56] @ (80055b8 ) 800557e: 4293 cmp r3, r2 8005580: d003 beq.n 800558a 8005582: 687b ldr r3, [r7, #4] 8005584: 4a10 ldr r2, [pc, #64] @ (80055c8 ) 8005586: 4293 cmp r3, r2 8005588: d103 bne.n 8005592 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800558a: 683b ldr r3, [r7, #0] 800558c: 691a ldr r2, [r3, #16] 800558e: 687b ldr r3, [r7, #4] 8005590: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 8005592: 687b ldr r3, [r7, #4] 8005594: 681b ldr r3, [r3, #0] 8005596: f043 0204 orr.w r2, r3, #4 800559a: 687b ldr r3, [r7, #4] 800559c: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800559e: 687b ldr r3, [r7, #4] 80055a0: 2201 movs r2, #1 80055a2: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 80055a4: 687b ldr r3, [r7, #4] 80055a6: 68fa ldr r2, [r7, #12] 80055a8: 601a str r2, [r3, #0] } 80055aa: bf00 nop 80055ac: 3714 adds r7, #20 80055ae: 46bd mov sp, r7 80055b0: f85d 7b04 ldr.w r7, [sp], #4 80055b4: 4770 bx lr 80055b6: bf00 nop 80055b8: 40010000 .word 0x40010000 80055bc: 40000400 .word 0x40000400 80055c0: 40000800 .word 0x40000800 80055c4: 40000c00 .word 0x40000c00 80055c8: 40010400 .word 0x40010400 80055cc: 40014000 .word 0x40014000 80055d0: 40014400 .word 0x40014400 80055d4: 40014800 .word 0x40014800 80055d8: 40001800 .word 0x40001800 80055dc: 40001c00 .word 0x40001c00 80055e0: 40002000 .word 0x40002000 080055e4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80055e4: b480 push {r7} 80055e6: b087 sub sp, #28 80055e8: af00 add r7, sp, #0 80055ea: 6078 str r0, [r7, #4] 80055ec: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80055ee: 687b ldr r3, [r7, #4] 80055f0: 6a1b ldr r3, [r3, #32] 80055f2: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80055f4: 687b ldr r3, [r7, #4] 80055f6: 6a1b ldr r3, [r3, #32] 80055f8: f023 0201 bic.w r2, r3, #1 80055fc: 687b ldr r3, [r7, #4] 80055fe: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005600: 687b ldr r3, [r7, #4] 8005602: 685b ldr r3, [r3, #4] 8005604: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8005606: 687b ldr r3, [r7, #4] 8005608: 699b ldr r3, [r3, #24] 800560a: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 800560c: 68fb ldr r3, [r7, #12] 800560e: f023 0370 bic.w r3, r3, #112 @ 0x70 8005612: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8005614: 68fb ldr r3, [r7, #12] 8005616: f023 0303 bic.w r3, r3, #3 800561a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800561c: 683b ldr r3, [r7, #0] 800561e: 681b ldr r3, [r3, #0] 8005620: 68fa ldr r2, [r7, #12] 8005622: 4313 orrs r3, r2 8005624: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8005626: 697b ldr r3, [r7, #20] 8005628: f023 0302 bic.w r3, r3, #2 800562c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800562e: 683b ldr r3, [r7, #0] 8005630: 689b ldr r3, [r3, #8] 8005632: 697a ldr r2, [r7, #20] 8005634: 4313 orrs r3, r2 8005636: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8005638: 687b ldr r3, [r7, #4] 800563a: 4a20 ldr r2, [pc, #128] @ (80056bc ) 800563c: 4293 cmp r3, r2 800563e: d003 beq.n 8005648 8005640: 687b ldr r3, [r7, #4] 8005642: 4a1f ldr r2, [pc, #124] @ (80056c0 ) 8005644: 4293 cmp r3, r2 8005646: d10c bne.n 8005662 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8005648: 697b ldr r3, [r7, #20] 800564a: f023 0308 bic.w r3, r3, #8 800564e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8005650: 683b ldr r3, [r7, #0] 8005652: 68db ldr r3, [r3, #12] 8005654: 697a ldr r2, [r7, #20] 8005656: 4313 orrs r3, r2 8005658: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 800565a: 697b ldr r3, [r7, #20] 800565c: f023 0304 bic.w r3, r3, #4 8005660: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005662: 687b ldr r3, [r7, #4] 8005664: 4a15 ldr r2, [pc, #84] @ (80056bc ) 8005666: 4293 cmp r3, r2 8005668: d003 beq.n 8005672 800566a: 687b ldr r3, [r7, #4] 800566c: 4a14 ldr r2, [pc, #80] @ (80056c0 ) 800566e: 4293 cmp r3, r2 8005670: d111 bne.n 8005696 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8005672: 693b ldr r3, [r7, #16] 8005674: f423 7380 bic.w r3, r3, #256 @ 0x100 8005678: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 800567a: 693b ldr r3, [r7, #16] 800567c: f423 7300 bic.w r3, r3, #512 @ 0x200 8005680: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8005682: 683b ldr r3, [r7, #0] 8005684: 695b ldr r3, [r3, #20] 8005686: 693a ldr r2, [r7, #16] 8005688: 4313 orrs r3, r2 800568a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800568c: 683b ldr r3, [r7, #0] 800568e: 699b ldr r3, [r3, #24] 8005690: 693a ldr r2, [r7, #16] 8005692: 4313 orrs r3, r2 8005694: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005696: 687b ldr r3, [r7, #4] 8005698: 693a ldr r2, [r7, #16] 800569a: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800569c: 687b ldr r3, [r7, #4] 800569e: 68fa ldr r2, [r7, #12] 80056a0: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 80056a2: 683b ldr r3, [r7, #0] 80056a4: 685a ldr r2, [r3, #4] 80056a6: 687b ldr r3, [r7, #4] 80056a8: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80056aa: 687b ldr r3, [r7, #4] 80056ac: 697a ldr r2, [r7, #20] 80056ae: 621a str r2, [r3, #32] } 80056b0: bf00 nop 80056b2: 371c adds r7, #28 80056b4: 46bd mov sp, r7 80056b6: f85d 7b04 ldr.w r7, [sp], #4 80056ba: 4770 bx lr 80056bc: 40010000 .word 0x40010000 80056c0: 40010400 .word 0x40010400 080056c4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80056c4: b480 push {r7} 80056c6: b087 sub sp, #28 80056c8: af00 add r7, sp, #0 80056ca: 6078 str r0, [r7, #4] 80056cc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80056ce: 687b ldr r3, [r7, #4] 80056d0: 6a1b ldr r3, [r3, #32] 80056d2: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80056d4: 687b ldr r3, [r7, #4] 80056d6: 6a1b ldr r3, [r3, #32] 80056d8: f023 0210 bic.w r2, r3, #16 80056dc: 687b ldr r3, [r7, #4] 80056de: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80056e0: 687b ldr r3, [r7, #4] 80056e2: 685b ldr r3, [r3, #4] 80056e4: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80056e6: 687b ldr r3, [r7, #4] 80056e8: 699b ldr r3, [r3, #24] 80056ea: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80056ec: 68fb ldr r3, [r7, #12] 80056ee: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80056f2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80056f4: 68fb ldr r3, [r7, #12] 80056f6: f423 7340 bic.w r3, r3, #768 @ 0x300 80056fa: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80056fc: 683b ldr r3, [r7, #0] 80056fe: 681b ldr r3, [r3, #0] 8005700: 021b lsls r3, r3, #8 8005702: 68fa ldr r2, [r7, #12] 8005704: 4313 orrs r3, r2 8005706: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8005708: 697b ldr r3, [r7, #20] 800570a: f023 0320 bic.w r3, r3, #32 800570e: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8005710: 683b ldr r3, [r7, #0] 8005712: 689b ldr r3, [r3, #8] 8005714: 011b lsls r3, r3, #4 8005716: 697a ldr r2, [r7, #20] 8005718: 4313 orrs r3, r2 800571a: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 800571c: 687b ldr r3, [r7, #4] 800571e: 4a22 ldr r2, [pc, #136] @ (80057a8 ) 8005720: 4293 cmp r3, r2 8005722: d003 beq.n 800572c 8005724: 687b ldr r3, [r7, #4] 8005726: 4a21 ldr r2, [pc, #132] @ (80057ac ) 8005728: 4293 cmp r3, r2 800572a: d10d bne.n 8005748 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 800572c: 697b ldr r3, [r7, #20] 800572e: f023 0380 bic.w r3, r3, #128 @ 0x80 8005732: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8005734: 683b ldr r3, [r7, #0] 8005736: 68db ldr r3, [r3, #12] 8005738: 011b lsls r3, r3, #4 800573a: 697a ldr r2, [r7, #20] 800573c: 4313 orrs r3, r2 800573e: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8005740: 697b ldr r3, [r7, #20] 8005742: f023 0340 bic.w r3, r3, #64 @ 0x40 8005746: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005748: 687b ldr r3, [r7, #4] 800574a: 4a17 ldr r2, [pc, #92] @ (80057a8 ) 800574c: 4293 cmp r3, r2 800574e: d003 beq.n 8005758 8005750: 687b ldr r3, [r7, #4] 8005752: 4a16 ldr r2, [pc, #88] @ (80057ac ) 8005754: 4293 cmp r3, r2 8005756: d113 bne.n 8005780 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8005758: 693b ldr r3, [r7, #16] 800575a: f423 6380 bic.w r3, r3, #1024 @ 0x400 800575e: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8005760: 693b ldr r3, [r7, #16] 8005762: f423 6300 bic.w r3, r3, #2048 @ 0x800 8005766: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8005768: 683b ldr r3, [r7, #0] 800576a: 695b ldr r3, [r3, #20] 800576c: 009b lsls r3, r3, #2 800576e: 693a ldr r2, [r7, #16] 8005770: 4313 orrs r3, r2 8005772: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8005774: 683b ldr r3, [r7, #0] 8005776: 699b ldr r3, [r3, #24] 8005778: 009b lsls r3, r3, #2 800577a: 693a ldr r2, [r7, #16] 800577c: 4313 orrs r3, r2 800577e: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005780: 687b ldr r3, [r7, #4] 8005782: 693a ldr r2, [r7, #16] 8005784: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8005786: 687b ldr r3, [r7, #4] 8005788: 68fa ldr r2, [r7, #12] 800578a: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 800578c: 683b ldr r3, [r7, #0] 800578e: 685a ldr r2, [r3, #4] 8005790: 687b ldr r3, [r7, #4] 8005792: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005794: 687b ldr r3, [r7, #4] 8005796: 697a ldr r2, [r7, #20] 8005798: 621a str r2, [r3, #32] } 800579a: bf00 nop 800579c: 371c adds r7, #28 800579e: 46bd mov sp, r7 80057a0: f85d 7b04 ldr.w r7, [sp], #4 80057a4: 4770 bx lr 80057a6: bf00 nop 80057a8: 40010000 .word 0x40010000 80057ac: 40010400 .word 0x40010400 080057b0 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80057b0: b480 push {r7} 80057b2: b087 sub sp, #28 80057b4: af00 add r7, sp, #0 80057b6: 6078 str r0, [r7, #4] 80057b8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80057ba: 687b ldr r3, [r7, #4] 80057bc: 6a1b ldr r3, [r3, #32] 80057be: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 80057c0: 687b ldr r3, [r7, #4] 80057c2: 6a1b ldr r3, [r3, #32] 80057c4: f423 7280 bic.w r2, r3, #256 @ 0x100 80057c8: 687b ldr r3, [r7, #4] 80057ca: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80057cc: 687b ldr r3, [r7, #4] 80057ce: 685b ldr r3, [r3, #4] 80057d0: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80057d2: 687b ldr r3, [r7, #4] 80057d4: 69db ldr r3, [r3, #28] 80057d6: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 80057d8: 68fb ldr r3, [r7, #12] 80057da: f023 0370 bic.w r3, r3, #112 @ 0x70 80057de: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 80057e0: 68fb ldr r3, [r7, #12] 80057e2: f023 0303 bic.w r3, r3, #3 80057e6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80057e8: 683b ldr r3, [r7, #0] 80057ea: 681b ldr r3, [r3, #0] 80057ec: 68fa ldr r2, [r7, #12] 80057ee: 4313 orrs r3, r2 80057f0: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 80057f2: 697b ldr r3, [r7, #20] 80057f4: f423 7300 bic.w r3, r3, #512 @ 0x200 80057f8: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 80057fa: 683b ldr r3, [r7, #0] 80057fc: 689b ldr r3, [r3, #8] 80057fe: 021b lsls r3, r3, #8 8005800: 697a ldr r2, [r7, #20] 8005802: 4313 orrs r3, r2 8005804: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8005806: 687b ldr r3, [r7, #4] 8005808: 4a21 ldr r2, [pc, #132] @ (8005890 ) 800580a: 4293 cmp r3, r2 800580c: d003 beq.n 8005816 800580e: 687b ldr r3, [r7, #4] 8005810: 4a20 ldr r2, [pc, #128] @ (8005894 ) 8005812: 4293 cmp r3, r2 8005814: d10d bne.n 8005832 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8005816: 697b ldr r3, [r7, #20] 8005818: f423 6300 bic.w r3, r3, #2048 @ 0x800 800581c: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 800581e: 683b ldr r3, [r7, #0] 8005820: 68db ldr r3, [r3, #12] 8005822: 021b lsls r3, r3, #8 8005824: 697a ldr r2, [r7, #20] 8005826: 4313 orrs r3, r2 8005828: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 800582a: 697b ldr r3, [r7, #20] 800582c: f423 6380 bic.w r3, r3, #1024 @ 0x400 8005830: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005832: 687b ldr r3, [r7, #4] 8005834: 4a16 ldr r2, [pc, #88] @ (8005890 ) 8005836: 4293 cmp r3, r2 8005838: d003 beq.n 8005842 800583a: 687b ldr r3, [r7, #4] 800583c: 4a15 ldr r2, [pc, #84] @ (8005894 ) 800583e: 4293 cmp r3, r2 8005840: d113 bne.n 800586a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8005842: 693b ldr r3, [r7, #16] 8005844: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8005848: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 800584a: 693b ldr r3, [r7, #16] 800584c: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8005850: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8005852: 683b ldr r3, [r7, #0] 8005854: 695b ldr r3, [r3, #20] 8005856: 011b lsls r3, r3, #4 8005858: 693a ldr r2, [r7, #16] 800585a: 4313 orrs r3, r2 800585c: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 800585e: 683b ldr r3, [r7, #0] 8005860: 699b ldr r3, [r3, #24] 8005862: 011b lsls r3, r3, #4 8005864: 693a ldr r2, [r7, #16] 8005866: 4313 orrs r3, r2 8005868: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800586a: 687b ldr r3, [r7, #4] 800586c: 693a ldr r2, [r7, #16] 800586e: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8005870: 687b ldr r3, [r7, #4] 8005872: 68fa ldr r2, [r7, #12] 8005874: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8005876: 683b ldr r3, [r7, #0] 8005878: 685a ldr r2, [r3, #4] 800587a: 687b ldr r3, [r7, #4] 800587c: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800587e: 687b ldr r3, [r7, #4] 8005880: 697a ldr r2, [r7, #20] 8005882: 621a str r2, [r3, #32] } 8005884: bf00 nop 8005886: 371c adds r7, #28 8005888: 46bd mov sp, r7 800588a: f85d 7b04 ldr.w r7, [sp], #4 800588e: 4770 bx lr 8005890: 40010000 .word 0x40010000 8005894: 40010400 .word 0x40010400 08005898 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005898: b480 push {r7} 800589a: b087 sub sp, #28 800589c: af00 add r7, sp, #0 800589e: 6078 str r0, [r7, #4] 80058a0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80058a2: 687b ldr r3, [r7, #4] 80058a4: 6a1b ldr r3, [r3, #32] 80058a6: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 80058a8: 687b ldr r3, [r7, #4] 80058aa: 6a1b ldr r3, [r3, #32] 80058ac: f423 5280 bic.w r2, r3, #4096 @ 0x1000 80058b0: 687b ldr r3, [r7, #4] 80058b2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80058b4: 687b ldr r3, [r7, #4] 80058b6: 685b ldr r3, [r3, #4] 80058b8: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80058ba: 687b ldr r3, [r7, #4] 80058bc: 69db ldr r3, [r3, #28] 80058be: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 80058c0: 68fb ldr r3, [r7, #12] 80058c2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80058c6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 80058c8: 68fb ldr r3, [r7, #12] 80058ca: f423 7340 bic.w r3, r3, #768 @ 0x300 80058ce: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80058d0: 683b ldr r3, [r7, #0] 80058d2: 681b ldr r3, [r3, #0] 80058d4: 021b lsls r3, r3, #8 80058d6: 68fa ldr r2, [r7, #12] 80058d8: 4313 orrs r3, r2 80058da: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 80058dc: 693b ldr r3, [r7, #16] 80058de: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80058e2: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 80058e4: 683b ldr r3, [r7, #0] 80058e6: 689b ldr r3, [r3, #8] 80058e8: 031b lsls r3, r3, #12 80058ea: 693a ldr r2, [r7, #16] 80058ec: 4313 orrs r3, r2 80058ee: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 80058f0: 687b ldr r3, [r7, #4] 80058f2: 4a12 ldr r2, [pc, #72] @ (800593c ) 80058f4: 4293 cmp r3, r2 80058f6: d003 beq.n 8005900 80058f8: 687b ldr r3, [r7, #4] 80058fa: 4a11 ldr r2, [pc, #68] @ (8005940 ) 80058fc: 4293 cmp r3, r2 80058fe: d109 bne.n 8005914 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8005900: 697b ldr r3, [r7, #20] 8005902: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8005906: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8005908: 683b ldr r3, [r7, #0] 800590a: 695b ldr r3, [r3, #20] 800590c: 019b lsls r3, r3, #6 800590e: 697a ldr r2, [r7, #20] 8005910: 4313 orrs r3, r2 8005912: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005914: 687b ldr r3, [r7, #4] 8005916: 697a ldr r2, [r7, #20] 8005918: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800591a: 687b ldr r3, [r7, #4] 800591c: 68fa ldr r2, [r7, #12] 800591e: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8005920: 683b ldr r3, [r7, #0] 8005922: 685a ldr r2, [r3, #4] 8005924: 687b ldr r3, [r7, #4] 8005926: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005928: 687b ldr r3, [r7, #4] 800592a: 693a ldr r2, [r7, #16] 800592c: 621a str r2, [r3, #32] } 800592e: bf00 nop 8005930: 371c adds r7, #28 8005932: 46bd mov sp, r7 8005934: f85d 7b04 ldr.w r7, [sp], #4 8005938: 4770 bx lr 800593a: bf00 nop 800593c: 40010000 .word 0x40010000 8005940: 40010400 .word 0x40010400 08005944 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8005944: b480 push {r7} 8005946: b085 sub sp, #20 8005948: af00 add r7, sp, #0 800594a: 6078 str r0, [r7, #4] 800594c: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800594e: 687b ldr r3, [r7, #4] 8005950: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005954: 2b01 cmp r3, #1 8005956: d101 bne.n 800595c 8005958: 2302 movs r3, #2 800595a: e05a b.n 8005a12 800595c: 687b ldr r3, [r7, #4] 800595e: 2201 movs r2, #1 8005960: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8005964: 687b ldr r3, [r7, #4] 8005966: 2202 movs r2, #2 8005968: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 800596c: 687b ldr r3, [r7, #4] 800596e: 681b ldr r3, [r3, #0] 8005970: 685b ldr r3, [r3, #4] 8005972: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005974: 687b ldr r3, [r7, #4] 8005976: 681b ldr r3, [r3, #0] 8005978: 689b ldr r3, [r3, #8] 800597a: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 800597c: 68fb ldr r3, [r7, #12] 800597e: f023 0370 bic.w r3, r3, #112 @ 0x70 8005982: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8005984: 683b ldr r3, [r7, #0] 8005986: 681b ldr r3, [r3, #0] 8005988: 68fa ldr r2, [r7, #12] 800598a: 4313 orrs r3, r2 800598c: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 800598e: 687b ldr r3, [r7, #4] 8005990: 681b ldr r3, [r3, #0] 8005992: 68fa ldr r2, [r7, #12] 8005994: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005996: 687b ldr r3, [r7, #4] 8005998: 681b ldr r3, [r3, #0] 800599a: 4a21 ldr r2, [pc, #132] @ (8005a20 ) 800599c: 4293 cmp r3, r2 800599e: d022 beq.n 80059e6 80059a0: 687b ldr r3, [r7, #4] 80059a2: 681b ldr r3, [r3, #0] 80059a4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80059a8: d01d beq.n 80059e6 80059aa: 687b ldr r3, [r7, #4] 80059ac: 681b ldr r3, [r3, #0] 80059ae: 4a1d ldr r2, [pc, #116] @ (8005a24 ) 80059b0: 4293 cmp r3, r2 80059b2: d018 beq.n 80059e6 80059b4: 687b ldr r3, [r7, #4] 80059b6: 681b ldr r3, [r3, #0] 80059b8: 4a1b ldr r2, [pc, #108] @ (8005a28 ) 80059ba: 4293 cmp r3, r2 80059bc: d013 beq.n 80059e6 80059be: 687b ldr r3, [r7, #4] 80059c0: 681b ldr r3, [r3, #0] 80059c2: 4a1a ldr r2, [pc, #104] @ (8005a2c ) 80059c4: 4293 cmp r3, r2 80059c6: d00e beq.n 80059e6 80059c8: 687b ldr r3, [r7, #4] 80059ca: 681b ldr r3, [r3, #0] 80059cc: 4a18 ldr r2, [pc, #96] @ (8005a30 ) 80059ce: 4293 cmp r3, r2 80059d0: d009 beq.n 80059e6 80059d2: 687b ldr r3, [r7, #4] 80059d4: 681b ldr r3, [r3, #0] 80059d6: 4a17 ldr r2, [pc, #92] @ (8005a34 ) 80059d8: 4293 cmp r3, r2 80059da: d004 beq.n 80059e6 80059dc: 687b ldr r3, [r7, #4] 80059de: 681b ldr r3, [r3, #0] 80059e0: 4a15 ldr r2, [pc, #84] @ (8005a38 ) 80059e2: 4293 cmp r3, r2 80059e4: d10c bne.n 8005a00 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80059e6: 68bb ldr r3, [r7, #8] 80059e8: f023 0380 bic.w r3, r3, #128 @ 0x80 80059ec: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80059ee: 683b ldr r3, [r7, #0] 80059f0: 685b ldr r3, [r3, #4] 80059f2: 68ba ldr r2, [r7, #8] 80059f4: 4313 orrs r3, r2 80059f6: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80059f8: 687b ldr r3, [r7, #4] 80059fa: 681b ldr r3, [r3, #0] 80059fc: 68ba ldr r2, [r7, #8] 80059fe: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8005a00: 687b ldr r3, [r7, #4] 8005a02: 2201 movs r2, #1 8005a04: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8005a08: 687b ldr r3, [r7, #4] 8005a0a: 2200 movs r2, #0 8005a0c: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8005a10: 2300 movs r3, #0 } 8005a12: 4618 mov r0, r3 8005a14: 3714 adds r7, #20 8005a16: 46bd mov sp, r7 8005a18: f85d 7b04 ldr.w r7, [sp], #4 8005a1c: 4770 bx lr 8005a1e: bf00 nop 8005a20: 40010000 .word 0x40010000 8005a24: 40000400 .word 0x40000400 8005a28: 40000800 .word 0x40000800 8005a2c: 40000c00 .word 0x40000c00 8005a30: 40010400 .word 0x40010400 8005a34: 40014000 .word 0x40014000 8005a38: 40001800 .word 0x40001800 08005a3c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8005a3c: b580 push {r7, lr} 8005a3e: b082 sub sp, #8 8005a40: af00 add r7, sp, #0 8005a42: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8005a44: 687b ldr r3, [r7, #4] 8005a46: 2b00 cmp r3, #0 8005a48: d101 bne.n 8005a4e { return HAL_ERROR; 8005a4a: 2301 movs r3, #1 8005a4c: e042 b.n 8005ad4 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 8005a4e: 687b ldr r3, [r7, #4] 8005a50: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005a54: b2db uxtb r3, r3 8005a56: 2b00 cmp r3, #0 8005a58: d106 bne.n 8005a68 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8005a5a: 687b ldr r3, [r7, #4] 8005a5c: 2200 movs r2, #0 8005a5e: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8005a62: 6878 ldr r0, [r7, #4] 8005a64: f7fb fc8e bl 8001384 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8005a68: 687b ldr r3, [r7, #4] 8005a6a: 2224 movs r2, #36 @ 0x24 8005a6c: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8005a70: 687b ldr r3, [r7, #4] 8005a72: 681b ldr r3, [r3, #0] 8005a74: 68da ldr r2, [r3, #12] 8005a76: 687b ldr r3, [r7, #4] 8005a78: 681b ldr r3, [r3, #0] 8005a7a: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8005a7e: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8005a80: 6878 ldr r0, [r7, #4] 8005a82: f000 ff6d bl 8006960 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8005a86: 687b ldr r3, [r7, #4] 8005a88: 681b ldr r3, [r3, #0] 8005a8a: 691a ldr r2, [r3, #16] 8005a8c: 687b ldr r3, [r7, #4] 8005a8e: 681b ldr r3, [r3, #0] 8005a90: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8005a94: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8005a96: 687b ldr r3, [r7, #4] 8005a98: 681b ldr r3, [r3, #0] 8005a9a: 695a ldr r2, [r3, #20] 8005a9c: 687b ldr r3, [r7, #4] 8005a9e: 681b ldr r3, [r3, #0] 8005aa0: f022 022a bic.w r2, r2, #42 @ 0x2a 8005aa4: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8005aa6: 687b ldr r3, [r7, #4] 8005aa8: 681b ldr r3, [r3, #0] 8005aaa: 68da ldr r2, [r3, #12] 8005aac: 687b ldr r3, [r7, #4] 8005aae: 681b ldr r3, [r3, #0] 8005ab0: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8005ab4: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005ab6: 687b ldr r3, [r7, #4] 8005ab8: 2200 movs r2, #0 8005aba: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8005abc: 687b ldr r3, [r7, #4] 8005abe: 2220 movs r2, #32 8005ac0: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8005ac4: 687b ldr r3, [r7, #4] 8005ac6: 2220 movs r2, #32 8005ac8: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8005acc: 687b ldr r3, [r7, #4] 8005ace: 2200 movs r2, #0 8005ad0: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8005ad2: 2300 movs r3, #0 } 8005ad4: 4618 mov r0, r3 8005ad6: 3708 adds r7, #8 8005ad8: 46bd mov sp, r7 8005ada: bd80 pop {r7, pc} 08005adc : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8005adc: b580 push {r7, lr} 8005ade: b08c sub sp, #48 @ 0x30 8005ae0: af00 add r7, sp, #0 8005ae2: 60f8 str r0, [r7, #12] 8005ae4: 60b9 str r1, [r7, #8] 8005ae6: 4613 mov r3, r2 8005ae8: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8005aea: 68fb ldr r3, [r7, #12] 8005aec: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005af0: b2db uxtb r3, r3 8005af2: 2b20 cmp r3, #32 8005af4: d162 bne.n 8005bbc { if ((pData == NULL) || (Size == 0U)) 8005af6: 68bb ldr r3, [r7, #8] 8005af8: 2b00 cmp r3, #0 8005afa: d002 beq.n 8005b02 8005afc: 88fb ldrh r3, [r7, #6] 8005afe: 2b00 cmp r3, #0 8005b00: d101 bne.n 8005b06 { return HAL_ERROR; 8005b02: 2301 movs r3, #1 8005b04: e05b b.n 8005bbe } huart->pTxBuffPtr = pData; 8005b06: 68ba ldr r2, [r7, #8] 8005b08: 68fb ldr r3, [r7, #12] 8005b0a: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8005b0c: 68fb ldr r3, [r7, #12] 8005b0e: 88fa ldrh r2, [r7, #6] 8005b10: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8005b12: 68fb ldr r3, [r7, #12] 8005b14: 88fa ldrh r2, [r7, #6] 8005b16: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8005b18: 68fb ldr r3, [r7, #12] 8005b1a: 2200 movs r2, #0 8005b1c: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8005b1e: 68fb ldr r3, [r7, #12] 8005b20: 2221 movs r2, #33 @ 0x21 8005b22: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 8005b26: 68fb ldr r3, [r7, #12] 8005b28: 6b9b ldr r3, [r3, #56] @ 0x38 8005b2a: 4a27 ldr r2, [pc, #156] @ (8005bc8 ) 8005b2c: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8005b2e: 68fb ldr r3, [r7, #12] 8005b30: 6b9b ldr r3, [r3, #56] @ 0x38 8005b32: 4a26 ldr r2, [pc, #152] @ (8005bcc ) 8005b34: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 8005b36: 68fb ldr r3, [r7, #12] 8005b38: 6b9b ldr r3, [r3, #56] @ 0x38 8005b3a: 4a25 ldr r2, [pc, #148] @ (8005bd0 ) 8005b3c: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8005b3e: 68fb ldr r3, [r7, #12] 8005b40: 6b9b ldr r3, [r3, #56] @ 0x38 8005b42: 2200 movs r2, #0 8005b44: 651a str r2, [r3, #80] @ 0x50 /* Enable the UART transmit DMA stream */ tmp = (const uint32_t *)&pData; 8005b46: f107 0308 add.w r3, r7, #8 8005b4a: 62fb str r3, [r7, #44] @ 0x2c if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK) 8005b4c: 68fb ldr r3, [r7, #12] 8005b4e: 6b98 ldr r0, [r3, #56] @ 0x38 8005b50: 6afb ldr r3, [r7, #44] @ 0x2c 8005b52: 6819 ldr r1, [r3, #0] 8005b54: 68fb ldr r3, [r7, #12] 8005b56: 681b ldr r3, [r3, #0] 8005b58: 3304 adds r3, #4 8005b5a: 461a mov r2, r3 8005b5c: 88fb ldrh r3, [r7, #6] 8005b5e: f7fc f953 bl 8001e08 8005b62: 4603 mov r3, r0 8005b64: 2b00 cmp r3, #0 8005b66: d008 beq.n 8005b7a { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8005b68: 68fb ldr r3, [r7, #12] 8005b6a: 2210 movs r2, #16 8005b6c: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; 8005b6e: 68fb ldr r3, [r7, #12] 8005b70: 2220 movs r2, #32 8005b72: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_ERROR; 8005b76: 2301 movs r3, #1 8005b78: e021 b.n 8005bbe } /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 8005b7a: 68fb ldr r3, [r7, #12] 8005b7c: 681b ldr r3, [r3, #0] 8005b7e: f06f 0240 mvn.w r2, #64 @ 0x40 8005b82: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8005b84: 68fb ldr r3, [r7, #12] 8005b86: 681b ldr r3, [r3, #0] 8005b88: 3314 adds r3, #20 8005b8a: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005b8c: 69bb ldr r3, [r7, #24] 8005b8e: e853 3f00 ldrex r3, [r3] 8005b92: 617b str r3, [r7, #20] return(result); 8005b94: 697b ldr r3, [r7, #20] 8005b96: f043 0380 orr.w r3, r3, #128 @ 0x80 8005b9a: 62bb str r3, [r7, #40] @ 0x28 8005b9c: 68fb ldr r3, [r7, #12] 8005b9e: 681b ldr r3, [r3, #0] 8005ba0: 3314 adds r3, #20 8005ba2: 6aba ldr r2, [r7, #40] @ 0x28 8005ba4: 627a str r2, [r7, #36] @ 0x24 8005ba6: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005ba8: 6a39 ldr r1, [r7, #32] 8005baa: 6a7a ldr r2, [r7, #36] @ 0x24 8005bac: e841 2300 strex r3, r2, [r1] 8005bb0: 61fb str r3, [r7, #28] return(result); 8005bb2: 69fb ldr r3, [r7, #28] 8005bb4: 2b00 cmp r3, #0 8005bb6: d1e5 bne.n 8005b84 return HAL_OK; 8005bb8: 2300 movs r3, #0 8005bba: e000 b.n 8005bbe } else { return HAL_BUSY; 8005bbc: 2302 movs r3, #2 } } 8005bbe: 4618 mov r0, r3 8005bc0: 3730 adds r7, #48 @ 0x30 8005bc2: 46bd mov sp, r7 8005bc4: bd80 pop {r7, pc} 8005bc6: bf00 nop 8005bc8: 080061dd .word 0x080061dd 8005bcc: 08006277 .word 0x08006277 8005bd0: 080063fb .word 0x080063fb 08005bd4 : * @param Size Amount of data elements (u8 or u16) to be received. * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8005bd4: b580 push {r7, lr} 8005bd6: b084 sub sp, #16 8005bd8: af00 add r7, sp, #0 8005bda: 60f8 str r0, [r7, #12] 8005bdc: 60b9 str r1, [r7, #8] 8005bde: 4613 mov r3, r2 8005be0: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8005be2: 68fb ldr r3, [r7, #12] 8005be4: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8005be8: b2db uxtb r3, r3 8005bea: 2b20 cmp r3, #32 8005bec: d112 bne.n 8005c14 { if ((pData == NULL) || (Size == 0U)) 8005bee: 68bb ldr r3, [r7, #8] 8005bf0: 2b00 cmp r3, #0 8005bf2: d002 beq.n 8005bfa 8005bf4: 88fb ldrh r3, [r7, #6] 8005bf6: 2b00 cmp r3, #0 8005bf8: d101 bne.n 8005bfe { return HAL_ERROR; 8005bfa: 2301 movs r3, #1 8005bfc: e00b b.n 8005c16 } /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005bfe: 68fb ldr r3, [r7, #12] 8005c00: 2200 movs r2, #0 8005c02: 631a str r2, [r3, #48] @ 0x30 return (UART_Start_Receive_DMA(huart, pData, Size)); 8005c04: 88fb ldrh r3, [r7, #6] 8005c06: 461a mov r2, r3 8005c08: 68b9 ldr r1, [r7, #8] 8005c0a: 68f8 ldr r0, [r7, #12] 8005c0c: f000 fc40 bl 8006490 8005c10: 4603 mov r3, r0 8005c12: e000 b.n 8005c16 } else { return HAL_BUSY; 8005c14: 2302 movs r3, #2 } } 8005c16: 4618 mov r0, r3 8005c18: 3710 adds r7, #16 8005c1a: 46bd mov sp, r7 8005c1c: bd80 pop {r7, pc} ... 08005c20 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8005c20: b580 push {r7, lr} 8005c22: b0ba sub sp, #232 @ 0xe8 8005c24: af00 add r7, sp, #0 8005c26: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8005c28: 687b ldr r3, [r7, #4] 8005c2a: 681b ldr r3, [r3, #0] 8005c2c: 681b ldr r3, [r3, #0] 8005c2e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8005c32: 687b ldr r3, [r7, #4] 8005c34: 681b ldr r3, [r3, #0] 8005c36: 68db ldr r3, [r3, #12] 8005c38: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8005c3c: 687b ldr r3, [r7, #4] 8005c3e: 681b ldr r3, [r3, #0] 8005c40: 695b ldr r3, [r3, #20] 8005c42: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8005c46: 2300 movs r3, #0 8005c48: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8005c4c: 2300 movs r3, #0 8005c4e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8005c52: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005c56: f003 030f and.w r3, r3, #15 8005c5a: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8005c5e: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8005c62: 2b00 cmp r3, #0 8005c64: d10f bne.n 8005c86 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005c66: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005c6a: f003 0320 and.w r3, r3, #32 8005c6e: 2b00 cmp r3, #0 8005c70: d009 beq.n 8005c86 8005c72: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005c76: f003 0320 and.w r3, r3, #32 8005c7a: 2b00 cmp r3, #0 8005c7c: d003 beq.n 8005c86 { UART_Receive_IT(huart); 8005c7e: 6878 ldr r0, [r7, #4] 8005c80: f000 fdb0 bl 80067e4 return; 8005c84: e273 b.n 800616e } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8005c86: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8005c8a: 2b00 cmp r3, #0 8005c8c: f000 80de beq.w 8005e4c 8005c90: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005c94: f003 0301 and.w r3, r3, #1 8005c98: 2b00 cmp r3, #0 8005c9a: d106 bne.n 8005caa || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8005c9c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005ca0: f403 7390 and.w r3, r3, #288 @ 0x120 8005ca4: 2b00 cmp r3, #0 8005ca6: f000 80d1 beq.w 8005e4c { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8005caa: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005cae: f003 0301 and.w r3, r3, #1 8005cb2: 2b00 cmp r3, #0 8005cb4: d00b beq.n 8005cce 8005cb6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005cba: f403 7380 and.w r3, r3, #256 @ 0x100 8005cbe: 2b00 cmp r3, #0 8005cc0: d005 beq.n 8005cce { huart->ErrorCode |= HAL_UART_ERROR_PE; 8005cc2: 687b ldr r3, [r7, #4] 8005cc4: 6c5b ldr r3, [r3, #68] @ 0x44 8005cc6: f043 0201 orr.w r2, r3, #1 8005cca: 687b ldr r3, [r7, #4] 8005ccc: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005cce: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005cd2: f003 0304 and.w r3, r3, #4 8005cd6: 2b00 cmp r3, #0 8005cd8: d00b beq.n 8005cf2 8005cda: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005cde: f003 0301 and.w r3, r3, #1 8005ce2: 2b00 cmp r3, #0 8005ce4: d005 beq.n 8005cf2 { huart->ErrorCode |= HAL_UART_ERROR_NE; 8005ce6: 687b ldr r3, [r7, #4] 8005ce8: 6c5b ldr r3, [r3, #68] @ 0x44 8005cea: f043 0202 orr.w r2, r3, #2 8005cee: 687b ldr r3, [r7, #4] 8005cf0: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005cf2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005cf6: f003 0302 and.w r3, r3, #2 8005cfa: 2b00 cmp r3, #0 8005cfc: d00b beq.n 8005d16 8005cfe: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005d02: f003 0301 and.w r3, r3, #1 8005d06: 2b00 cmp r3, #0 8005d08: d005 beq.n 8005d16 { huart->ErrorCode |= HAL_UART_ERROR_FE; 8005d0a: 687b ldr r3, [r7, #4] 8005d0c: 6c5b ldr r3, [r3, #68] @ 0x44 8005d0e: f043 0204 orr.w r2, r3, #4 8005d12: 687b ldr r3, [r7, #4] 8005d14: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8005d16: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005d1a: f003 0308 and.w r3, r3, #8 8005d1e: 2b00 cmp r3, #0 8005d20: d011 beq.n 8005d46 8005d22: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005d26: f003 0320 and.w r3, r3, #32 8005d2a: 2b00 cmp r3, #0 8005d2c: d105 bne.n 8005d3a || ((cr3its & USART_CR3_EIE) != RESET))) 8005d2e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005d32: f003 0301 and.w r3, r3, #1 8005d36: 2b00 cmp r3, #0 8005d38: d005 beq.n 8005d46 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8005d3a: 687b ldr r3, [r7, #4] 8005d3c: 6c5b ldr r3, [r3, #68] @ 0x44 8005d3e: f043 0208 orr.w r2, r3, #8 8005d42: 687b ldr r3, [r7, #4] 8005d44: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8005d46: 687b ldr r3, [r7, #4] 8005d48: 6c5b ldr r3, [r3, #68] @ 0x44 8005d4a: 2b00 cmp r3, #0 8005d4c: f000 820a beq.w 8006164 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005d50: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005d54: f003 0320 and.w r3, r3, #32 8005d58: 2b00 cmp r3, #0 8005d5a: d008 beq.n 8005d6e 8005d5c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005d60: f003 0320 and.w r3, r3, #32 8005d64: 2b00 cmp r3, #0 8005d66: d002 beq.n 8005d6e { UART_Receive_IT(huart); 8005d68: 6878 ldr r0, [r7, #4] 8005d6a: f000 fd3b bl 80067e4 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8005d6e: 687b ldr r3, [r7, #4] 8005d70: 681b ldr r3, [r3, #0] 8005d72: 695b ldr r3, [r3, #20] 8005d74: f003 0340 and.w r3, r3, #64 @ 0x40 8005d78: 2b40 cmp r3, #64 @ 0x40 8005d7a: bf0c ite eq 8005d7c: 2301 moveq r3, #1 8005d7e: 2300 movne r3, #0 8005d80: b2db uxtb r3, r3 8005d82: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8005d86: 687b ldr r3, [r7, #4] 8005d88: 6c5b ldr r3, [r3, #68] @ 0x44 8005d8a: f003 0308 and.w r3, r3, #8 8005d8e: 2b00 cmp r3, #0 8005d90: d103 bne.n 8005d9a 8005d92: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8005d96: 2b00 cmp r3, #0 8005d98: d04f beq.n 8005e3a { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8005d9a: 6878 ldr r0, [r7, #4] 8005d9c: f000 fc46 bl 800662c /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005da0: 687b ldr r3, [r7, #4] 8005da2: 681b ldr r3, [r3, #0] 8005da4: 695b ldr r3, [r3, #20] 8005da6: f003 0340 and.w r3, r3, #64 @ 0x40 8005daa: 2b40 cmp r3, #64 @ 0x40 8005dac: d141 bne.n 8005e32 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005dae: 687b ldr r3, [r7, #4] 8005db0: 681b ldr r3, [r3, #0] 8005db2: 3314 adds r3, #20 8005db4: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005db8: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8005dbc: e853 3f00 ldrex r3, [r3] 8005dc0: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8005dc4: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8005dc8: f023 0340 bic.w r3, r3, #64 @ 0x40 8005dcc: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8005dd0: 687b ldr r3, [r7, #4] 8005dd2: 681b ldr r3, [r3, #0] 8005dd4: 3314 adds r3, #20 8005dd6: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8005dda: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8005dde: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005de2: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8005de6: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8005dea: e841 2300 strex r3, r2, [r1] 8005dee: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8005df2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8005df6: 2b00 cmp r3, #0 8005df8: d1d9 bne.n 8005dae /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) 8005dfa: 687b ldr r3, [r7, #4] 8005dfc: 6bdb ldr r3, [r3, #60] @ 0x3c 8005dfe: 2b00 cmp r3, #0 8005e00: d013 beq.n 8005e2a { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8005e02: 687b ldr r3, [r7, #4] 8005e04: 6bdb ldr r3, [r3, #60] @ 0x3c 8005e06: 4a8a ldr r2, [pc, #552] @ (8006030 ) 8005e08: 651a str r2, [r3, #80] @ 0x50 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8005e0a: 687b ldr r3, [r7, #4] 8005e0c: 6bdb ldr r3, [r3, #60] @ 0x3c 8005e0e: 4618 mov r0, r3 8005e10: f7fc f8c2 bl 8001f98 8005e14: 4603 mov r3, r0 8005e16: 2b00 cmp r3, #0 8005e18: d016 beq.n 8005e48 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8005e1a: 687b ldr r3, [r7, #4] 8005e1c: 6bdb ldr r3, [r3, #60] @ 0x3c 8005e1e: 6d1b ldr r3, [r3, #80] @ 0x50 8005e20: 687a ldr r2, [r7, #4] 8005e22: 6bd2 ldr r2, [r2, #60] @ 0x3c 8005e24: 4610 mov r0, r2 8005e26: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005e28: e00e b.n 8005e48 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005e2a: 6878 ldr r0, [r7, #4] 8005e2c: f000 f9c0 bl 80061b0 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005e30: e00a b.n 8005e48 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005e32: 6878 ldr r0, [r7, #4] 8005e34: f000 f9bc bl 80061b0 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005e38: e006 b.n 8005e48 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005e3a: 6878 ldr r0, [r7, #4] 8005e3c: f000 f9b8 bl 80061b0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005e40: 687b ldr r3, [r7, #4] 8005e42: 2200 movs r2, #0 8005e44: 645a str r2, [r3, #68] @ 0x44 } } return; 8005e46: e18d b.n 8006164 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005e48: bf00 nop return; 8005e4a: e18b b.n 8006164 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005e4c: 687b ldr r3, [r7, #4] 8005e4e: 6b1b ldr r3, [r3, #48] @ 0x30 8005e50: 2b01 cmp r3, #1 8005e52: f040 8167 bne.w 8006124 && ((isrflags & USART_SR_IDLE) != 0U) 8005e56: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005e5a: f003 0310 and.w r3, r3, #16 8005e5e: 2b00 cmp r3, #0 8005e60: f000 8160 beq.w 8006124 && ((cr1its & USART_CR1_IDLEIE) != 0U)) 8005e64: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005e68: f003 0310 and.w r3, r3, #16 8005e6c: 2b00 cmp r3, #0 8005e6e: f000 8159 beq.w 8006124 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8005e72: 2300 movs r3, #0 8005e74: 60bb str r3, [r7, #8] 8005e76: 687b ldr r3, [r7, #4] 8005e78: 681b ldr r3, [r3, #0] 8005e7a: 681b ldr r3, [r3, #0] 8005e7c: 60bb str r3, [r7, #8] 8005e7e: 687b ldr r3, [r7, #4] 8005e80: 681b ldr r3, [r3, #0] 8005e82: 685b ldr r3, [r3, #4] 8005e84: 60bb str r3, [r7, #8] 8005e86: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005e88: 687b ldr r3, [r7, #4] 8005e8a: 681b ldr r3, [r3, #0] 8005e8c: 695b ldr r3, [r3, #20] 8005e8e: f003 0340 and.w r3, r3, #64 @ 0x40 8005e92: 2b40 cmp r3, #64 @ 0x40 8005e94: f040 80ce bne.w 8006034 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8005e98: 687b ldr r3, [r7, #4] 8005e9a: 6bdb ldr r3, [r3, #60] @ 0x3c 8005e9c: 681b ldr r3, [r3, #0] 8005e9e: 685b ldr r3, [r3, #4] 8005ea0: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8005ea4: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8005ea8: 2b00 cmp r3, #0 8005eaa: f000 80a9 beq.w 8006000 && (nb_remaining_rx_data < huart->RxXferSize)) 8005eae: 687b ldr r3, [r7, #4] 8005eb0: 8d9b ldrh r3, [r3, #44] @ 0x2c 8005eb2: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005eb6: 429a cmp r2, r3 8005eb8: f080 80a2 bcs.w 8006000 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8005ebc: 687b ldr r3, [r7, #4] 8005ebe: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005ec2: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8005ec4: 687b ldr r3, [r7, #4] 8005ec6: 6bdb ldr r3, [r3, #60] @ 0x3c 8005ec8: 69db ldr r3, [r3, #28] 8005eca: f5b3 7f80 cmp.w r3, #256 @ 0x100 8005ece: f000 8088 beq.w 8005fe2 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8005ed2: 687b ldr r3, [r7, #4] 8005ed4: 681b ldr r3, [r3, #0] 8005ed6: 330c adds r3, #12 8005ed8: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005edc: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8005ee0: e853 3f00 ldrex r3, [r3] 8005ee4: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8005ee8: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8005eec: f423 7380 bic.w r3, r3, #256 @ 0x100 8005ef0: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8005ef4: 687b ldr r3, [r7, #4] 8005ef6: 681b ldr r3, [r3, #0] 8005ef8: 330c adds r3, #12 8005efa: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8005efe: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8005f02: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005f06: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8005f0a: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8005f0e: e841 2300 strex r3, r2, [r1] 8005f12: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8005f16: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005f1a: 2b00 cmp r3, #0 8005f1c: d1d9 bne.n 8005ed2 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005f1e: 687b ldr r3, [r7, #4] 8005f20: 681b ldr r3, [r3, #0] 8005f22: 3314 adds r3, #20 8005f24: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005f26: 6f7b ldr r3, [r7, #116] @ 0x74 8005f28: e853 3f00 ldrex r3, [r3] 8005f2c: 673b str r3, [r7, #112] @ 0x70 return(result); 8005f2e: 6f3b ldr r3, [r7, #112] @ 0x70 8005f30: f023 0301 bic.w r3, r3, #1 8005f34: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8005f38: 687b ldr r3, [r7, #4] 8005f3a: 681b ldr r3, [r3, #0] 8005f3c: 3314 adds r3, #20 8005f3e: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8005f42: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8005f46: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005f48: 6ff9 ldr r1, [r7, #124] @ 0x7c 8005f4a: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8005f4e: e841 2300 strex r3, r2, [r1] 8005f52: 67bb str r3, [r7, #120] @ 0x78 return(result); 8005f54: 6fbb ldr r3, [r7, #120] @ 0x78 8005f56: 2b00 cmp r3, #0 8005f58: d1e1 bne.n 8005f1e /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005f5a: 687b ldr r3, [r7, #4] 8005f5c: 681b ldr r3, [r3, #0] 8005f5e: 3314 adds r3, #20 8005f60: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005f62: 6e3b ldr r3, [r7, #96] @ 0x60 8005f64: e853 3f00 ldrex r3, [r3] 8005f68: 65fb str r3, [r7, #92] @ 0x5c return(result); 8005f6a: 6dfb ldr r3, [r7, #92] @ 0x5c 8005f6c: f023 0340 bic.w r3, r3, #64 @ 0x40 8005f70: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8005f74: 687b ldr r3, [r7, #4] 8005f76: 681b ldr r3, [r3, #0] 8005f78: 3314 adds r3, #20 8005f7a: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8005f7e: 66fa str r2, [r7, #108] @ 0x6c 8005f80: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005f82: 6eb9 ldr r1, [r7, #104] @ 0x68 8005f84: 6efa ldr r2, [r7, #108] @ 0x6c 8005f86: e841 2300 strex r3, r2, [r1] 8005f8a: 667b str r3, [r7, #100] @ 0x64 return(result); 8005f8c: 6e7b ldr r3, [r7, #100] @ 0x64 8005f8e: 2b00 cmp r3, #0 8005f90: d1e3 bne.n 8005f5a /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8005f92: 687b ldr r3, [r7, #4] 8005f94: 2220 movs r2, #32 8005f96: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005f9a: 687b ldr r3, [r7, #4] 8005f9c: 2200 movs r2, #0 8005f9e: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8005fa0: 687b ldr r3, [r7, #4] 8005fa2: 681b ldr r3, [r3, #0] 8005fa4: 330c adds r3, #12 8005fa6: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005fa8: 6cfb ldr r3, [r7, #76] @ 0x4c 8005faa: e853 3f00 ldrex r3, [r3] 8005fae: 64bb str r3, [r7, #72] @ 0x48 return(result); 8005fb0: 6cbb ldr r3, [r7, #72] @ 0x48 8005fb2: f023 0310 bic.w r3, r3, #16 8005fb6: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8005fba: 687b ldr r3, [r7, #4] 8005fbc: 681b ldr r3, [r3, #0] 8005fbe: 330c adds r3, #12 8005fc0: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 8005fc4: 65ba str r2, [r7, #88] @ 0x58 8005fc6: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005fc8: 6d79 ldr r1, [r7, #84] @ 0x54 8005fca: 6dba ldr r2, [r7, #88] @ 0x58 8005fcc: e841 2300 strex r3, r2, [r1] 8005fd0: 653b str r3, [r7, #80] @ 0x50 return(result); 8005fd2: 6d3b ldr r3, [r7, #80] @ 0x50 8005fd4: 2b00 cmp r3, #0 8005fd6: d1e3 bne.n 8005fa0 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8005fd8: 687b ldr r3, [r7, #4] 8005fda: 6bdb ldr r3, [r3, #60] @ 0x3c 8005fdc: 4618 mov r0, r3 8005fde: f7fb ff6b bl 8001eb8 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8005fe2: 687b ldr r3, [r7, #4] 8005fe4: 2202 movs r2, #2 8005fe6: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8005fe8: 687b ldr r3, [r7, #4] 8005fea: 8d9a ldrh r2, [r3, #44] @ 0x2c 8005fec: 687b ldr r3, [r7, #4] 8005fee: 8ddb ldrh r3, [r3, #46] @ 0x2e 8005ff0: b29b uxth r3, r3 8005ff2: 1ad3 subs r3, r2, r3 8005ff4: b29b uxth r3, r3 8005ff6: 4619 mov r1, r3 8005ff8: 6878 ldr r0, [r7, #4] 8005ffa: f000 f8e3 bl 80061c4 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 8005ffe: e0b3 b.n 8006168 if (nb_remaining_rx_data == huart->RxXferSize) 8006000: 687b ldr r3, [r7, #4] 8006002: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006004: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8006008: 429a cmp r2, r3 800600a: f040 80ad bne.w 8006168 if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) 800600e: 687b ldr r3, [r7, #4] 8006010: 6bdb ldr r3, [r3, #60] @ 0x3c 8006012: 69db ldr r3, [r3, #28] 8006014: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006018: f040 80a6 bne.w 8006168 huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800601c: 687b ldr r3, [r7, #4] 800601e: 2202 movs r2, #2 8006020: 635a str r2, [r3, #52] @ 0x34 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006022: 687b ldr r3, [r7, #4] 8006024: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006026: 4619 mov r1, r3 8006028: 6878 ldr r0, [r7, #4] 800602a: f000 f8cb bl 80061c4 return; 800602e: e09b b.n 8006168 8006030: 080066f3 .word 0x080066f3 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8006034: 687b ldr r3, [r7, #4] 8006036: 8d9a ldrh r2, [r3, #44] @ 0x2c 8006038: 687b ldr r3, [r7, #4] 800603a: 8ddb ldrh r3, [r3, #46] @ 0x2e 800603c: b29b uxth r3, r3 800603e: 1ad3 subs r3, r2, r3 8006040: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8006044: 687b ldr r3, [r7, #4] 8006046: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006048: b29b uxth r3, r3 800604a: 2b00 cmp r3, #0 800604c: f000 808e beq.w 800616c && (nb_rx_data > 0U)) 8006050: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8006054: 2b00 cmp r3, #0 8006056: f000 8089 beq.w 800616c { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 800605a: 687b ldr r3, [r7, #4] 800605c: 681b ldr r3, [r3, #0] 800605e: 330c adds r3, #12 8006060: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006062: 6bbb ldr r3, [r7, #56] @ 0x38 8006064: e853 3f00 ldrex r3, [r3] 8006068: 637b str r3, [r7, #52] @ 0x34 return(result); 800606a: 6b7b ldr r3, [r7, #52] @ 0x34 800606c: f423 7390 bic.w r3, r3, #288 @ 0x120 8006070: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8006074: 687b ldr r3, [r7, #4] 8006076: 681b ldr r3, [r3, #0] 8006078: 330c adds r3, #12 800607a: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 800607e: 647a str r2, [r7, #68] @ 0x44 8006080: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006082: 6c39 ldr r1, [r7, #64] @ 0x40 8006084: 6c7a ldr r2, [r7, #68] @ 0x44 8006086: e841 2300 strex r3, r2, [r1] 800608a: 63fb str r3, [r7, #60] @ 0x3c return(result); 800608c: 6bfb ldr r3, [r7, #60] @ 0x3c 800608e: 2b00 cmp r3, #0 8006090: d1e3 bne.n 800605a /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006092: 687b ldr r3, [r7, #4] 8006094: 681b ldr r3, [r3, #0] 8006096: 3314 adds r3, #20 8006098: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800609a: 6a7b ldr r3, [r7, #36] @ 0x24 800609c: e853 3f00 ldrex r3, [r3] 80060a0: 623b str r3, [r7, #32] return(result); 80060a2: 6a3b ldr r3, [r7, #32] 80060a4: f023 0301 bic.w r3, r3, #1 80060a8: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 80060ac: 687b ldr r3, [r7, #4] 80060ae: 681b ldr r3, [r3, #0] 80060b0: 3314 adds r3, #20 80060b2: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80060b6: 633a str r2, [r7, #48] @ 0x30 80060b8: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80060ba: 6af9 ldr r1, [r7, #44] @ 0x2c 80060bc: 6b3a ldr r2, [r7, #48] @ 0x30 80060be: e841 2300 strex r3, r2, [r1] 80060c2: 62bb str r3, [r7, #40] @ 0x28 return(result); 80060c4: 6abb ldr r3, [r7, #40] @ 0x28 80060c6: 2b00 cmp r3, #0 80060c8: d1e3 bne.n 8006092 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80060ca: 687b ldr r3, [r7, #4] 80060cc: 2220 movs r2, #32 80060ce: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80060d2: 687b ldr r3, [r7, #4] 80060d4: 2200 movs r2, #0 80060d6: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80060d8: 687b ldr r3, [r7, #4] 80060da: 681b ldr r3, [r3, #0] 80060dc: 330c adds r3, #12 80060de: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80060e0: 693b ldr r3, [r7, #16] 80060e2: e853 3f00 ldrex r3, [r3] 80060e6: 60fb str r3, [r7, #12] return(result); 80060e8: 68fb ldr r3, [r7, #12] 80060ea: f023 0310 bic.w r3, r3, #16 80060ee: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 80060f2: 687b ldr r3, [r7, #4] 80060f4: 681b ldr r3, [r3, #0] 80060f6: 330c adds r3, #12 80060f8: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 80060fc: 61fa str r2, [r7, #28] 80060fe: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006100: 69b9 ldr r1, [r7, #24] 8006102: 69fa ldr r2, [r7, #28] 8006104: e841 2300 strex r3, r2, [r1] 8006108: 617b str r3, [r7, #20] return(result); 800610a: 697b ldr r3, [r7, #20] 800610c: 2b00 cmp r3, #0 800610e: d1e3 bne.n 80060d8 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006110: 687b ldr r3, [r7, #4] 8006112: 2202 movs r2, #2 8006114: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8006116: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 800611a: 4619 mov r1, r3 800611c: 6878 ldr r0, [r7, #4] 800611e: f000 f851 bl 80061c4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8006122: e023 b.n 800616c } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8006124: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006128: f003 0380 and.w r3, r3, #128 @ 0x80 800612c: 2b00 cmp r3, #0 800612e: d009 beq.n 8006144 8006130: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006134: f003 0380 and.w r3, r3, #128 @ 0x80 8006138: 2b00 cmp r3, #0 800613a: d003 beq.n 8006144 { UART_Transmit_IT(huart); 800613c: 6878 ldr r0, [r7, #4] 800613e: f000 fae9 bl 8006714 return; 8006142: e014 b.n 800616e } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8006144: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006148: f003 0340 and.w r3, r3, #64 @ 0x40 800614c: 2b00 cmp r3, #0 800614e: d00e beq.n 800616e 8006150: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006154: f003 0340 and.w r3, r3, #64 @ 0x40 8006158: 2b00 cmp r3, #0 800615a: d008 beq.n 800616e { UART_EndTransmit_IT(huart); 800615c: 6878 ldr r0, [r7, #4] 800615e: f000 fb29 bl 80067b4 return; 8006162: e004 b.n 800616e return; 8006164: bf00 nop 8006166: e002 b.n 800616e return; 8006168: bf00 nop 800616a: e000 b.n 800616e return; 800616c: bf00 nop } } 800616e: 37e8 adds r7, #232 @ 0xe8 8006170: 46bd mov sp, r7 8006172: bd80 pop {r7, pc} 08006174 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8006174: b480 push {r7} 8006176: b083 sub sp, #12 8006178: af00 add r7, sp, #0 800617a: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 800617c: bf00 nop 800617e: 370c adds r7, #12 8006180: 46bd mov sp, r7 8006182: f85d 7b04 ldr.w r7, [sp], #4 8006186: 4770 bx lr 08006188 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8006188: b480 push {r7} 800618a: b083 sub sp, #12 800618c: af00 add r7, sp, #0 800618e: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 8006190: bf00 nop 8006192: 370c adds r7, #12 8006194: 46bd mov sp, r7 8006196: f85d 7b04 ldr.w r7, [sp], #4 800619a: 4770 bx lr 0800619c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 800619c: b480 push {r7} 800619e: b083 sub sp, #12 80061a0: af00 add r7, sp, #0 80061a2: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 80061a4: bf00 nop 80061a6: 370c adds r7, #12 80061a8: 46bd mov sp, r7 80061aa: f85d 7b04 ldr.w r7, [sp], #4 80061ae: 4770 bx lr 080061b0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 80061b0: b480 push {r7} 80061b2: b083 sub sp, #12 80061b4: af00 add r7, sp, #0 80061b6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 80061b8: bf00 nop 80061ba: 370c adds r7, #12 80061bc: 46bd mov sp, r7 80061be: f85d 7b04 ldr.w r7, [sp], #4 80061c2: 4770 bx lr 080061c4 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 80061c4: b480 push {r7} 80061c6: b083 sub sp, #12 80061c8: af00 add r7, sp, #0 80061ca: 6078 str r0, [r7, #4] 80061cc: 460b mov r3, r1 80061ce: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 80061d0: bf00 nop 80061d2: 370c adds r7, #12 80061d4: 46bd mov sp, r7 80061d6: f85d 7b04 ldr.w r7, [sp], #4 80061da: 4770 bx lr 080061dc : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 80061dc: b580 push {r7, lr} 80061de: b090 sub sp, #64 @ 0x40 80061e0: af00 add r7, sp, #0 80061e2: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80061e4: 687b ldr r3, [r7, #4] 80061e6: 6b9b ldr r3, [r3, #56] @ 0x38 80061e8: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 80061ea: 687b ldr r3, [r7, #4] 80061ec: 681b ldr r3, [r3, #0] 80061ee: 681b ldr r3, [r3, #0] 80061f0: f403 7380 and.w r3, r3, #256 @ 0x100 80061f4: 2b00 cmp r3, #0 80061f6: d137 bne.n 8006268 { huart->TxXferCount = 0x00U; 80061f8: 6bfb ldr r3, [r7, #60] @ 0x3c 80061fa: 2200 movs r2, #0 80061fc: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 80061fe: 6bfb ldr r3, [r7, #60] @ 0x3c 8006200: 681b ldr r3, [r3, #0] 8006202: 3314 adds r3, #20 8006204: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006206: 6a7b ldr r3, [r7, #36] @ 0x24 8006208: e853 3f00 ldrex r3, [r3] 800620c: 623b str r3, [r7, #32] return(result); 800620e: 6a3b ldr r3, [r7, #32] 8006210: f023 0380 bic.w r3, r3, #128 @ 0x80 8006214: 63bb str r3, [r7, #56] @ 0x38 8006216: 6bfb ldr r3, [r7, #60] @ 0x3c 8006218: 681b ldr r3, [r3, #0] 800621a: 3314 adds r3, #20 800621c: 6bba ldr r2, [r7, #56] @ 0x38 800621e: 633a str r2, [r7, #48] @ 0x30 8006220: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006222: 6af9 ldr r1, [r7, #44] @ 0x2c 8006224: 6b3a ldr r2, [r7, #48] @ 0x30 8006226: e841 2300 strex r3, r2, [r1] 800622a: 62bb str r3, [r7, #40] @ 0x28 return(result); 800622c: 6abb ldr r3, [r7, #40] @ 0x28 800622e: 2b00 cmp r3, #0 8006230: d1e5 bne.n 80061fe /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8006232: 6bfb ldr r3, [r7, #60] @ 0x3c 8006234: 681b ldr r3, [r3, #0] 8006236: 330c adds r3, #12 8006238: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800623a: 693b ldr r3, [r7, #16] 800623c: e853 3f00 ldrex r3, [r3] 8006240: 60fb str r3, [r7, #12] return(result); 8006242: 68fb ldr r3, [r7, #12] 8006244: f043 0340 orr.w r3, r3, #64 @ 0x40 8006248: 637b str r3, [r7, #52] @ 0x34 800624a: 6bfb ldr r3, [r7, #60] @ 0x3c 800624c: 681b ldr r3, [r3, #0] 800624e: 330c adds r3, #12 8006250: 6b7a ldr r2, [r7, #52] @ 0x34 8006252: 61fa str r2, [r7, #28] 8006254: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006256: 69b9 ldr r1, [r7, #24] 8006258: 69fa ldr r2, [r7, #28] 800625a: e841 2300 strex r3, r2, [r1] 800625e: 617b str r3, [r7, #20] return(result); 8006260: 697b ldr r3, [r7, #20] 8006262: 2b00 cmp r3, #0 8006264: d1e5 bne.n 8006232 #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8006266: e002 b.n 800626e HAL_UART_TxCpltCallback(huart); 8006268: 6bf8 ldr r0, [r7, #60] @ 0x3c 800626a: f7ff ff83 bl 8006174 } 800626e: bf00 nop 8006270: 3740 adds r7, #64 @ 0x40 8006272: 46bd mov sp, r7 8006274: bd80 pop {r7, pc} 08006276 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 8006276: b580 push {r7, lr} 8006278: b084 sub sp, #16 800627a: af00 add r7, sp, #0 800627c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800627e: 687b ldr r3, [r7, #4] 8006280: 6b9b ldr r3, [r3, #56] @ 0x38 8006282: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 8006284: 68f8 ldr r0, [r7, #12] 8006286: f7ff ff7f bl 8006188 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800628a: bf00 nop 800628c: 3710 adds r7, #16 800628e: 46bd mov sp, r7 8006290: bd80 pop {r7, pc} 08006292 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 8006292: b580 push {r7, lr} 8006294: b09c sub sp, #112 @ 0x70 8006296: af00 add r7, sp, #0 8006298: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800629a: 687b ldr r3, [r7, #4] 800629c: 6b9b ldr r3, [r3, #56] @ 0x38 800629e: 66fb str r3, [r7, #108] @ 0x6c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 80062a0: 687b ldr r3, [r7, #4] 80062a2: 681b ldr r3, [r3, #0] 80062a4: 681b ldr r3, [r3, #0] 80062a6: f403 7380 and.w r3, r3, #256 @ 0x100 80062aa: 2b00 cmp r3, #0 80062ac: d172 bne.n 8006394 { huart->RxXferCount = 0U; 80062ae: 6efb ldr r3, [r7, #108] @ 0x6c 80062b0: 2200 movs r2, #0 80062b2: 85da strh r2, [r3, #46] @ 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80062b4: 6efb ldr r3, [r7, #108] @ 0x6c 80062b6: 681b ldr r3, [r3, #0] 80062b8: 330c adds r3, #12 80062ba: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80062bc: 6cfb ldr r3, [r7, #76] @ 0x4c 80062be: e853 3f00 ldrex r3, [r3] 80062c2: 64bb str r3, [r7, #72] @ 0x48 return(result); 80062c4: 6cbb ldr r3, [r7, #72] @ 0x48 80062c6: f423 7380 bic.w r3, r3, #256 @ 0x100 80062ca: 66bb str r3, [r7, #104] @ 0x68 80062cc: 6efb ldr r3, [r7, #108] @ 0x6c 80062ce: 681b ldr r3, [r3, #0] 80062d0: 330c adds r3, #12 80062d2: 6eba ldr r2, [r7, #104] @ 0x68 80062d4: 65ba str r2, [r7, #88] @ 0x58 80062d6: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80062d8: 6d79 ldr r1, [r7, #84] @ 0x54 80062da: 6dba ldr r2, [r7, #88] @ 0x58 80062dc: e841 2300 strex r3, r2, [r1] 80062e0: 653b str r3, [r7, #80] @ 0x50 return(result); 80062e2: 6d3b ldr r3, [r7, #80] @ 0x50 80062e4: 2b00 cmp r3, #0 80062e6: d1e5 bne.n 80062b4 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80062e8: 6efb ldr r3, [r7, #108] @ 0x6c 80062ea: 681b ldr r3, [r3, #0] 80062ec: 3314 adds r3, #20 80062ee: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80062f0: 6bbb ldr r3, [r7, #56] @ 0x38 80062f2: e853 3f00 ldrex r3, [r3] 80062f6: 637b str r3, [r7, #52] @ 0x34 return(result); 80062f8: 6b7b ldr r3, [r7, #52] @ 0x34 80062fa: f023 0301 bic.w r3, r3, #1 80062fe: 667b str r3, [r7, #100] @ 0x64 8006300: 6efb ldr r3, [r7, #108] @ 0x6c 8006302: 681b ldr r3, [r3, #0] 8006304: 3314 adds r3, #20 8006306: 6e7a ldr r2, [r7, #100] @ 0x64 8006308: 647a str r2, [r7, #68] @ 0x44 800630a: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800630c: 6c39 ldr r1, [r7, #64] @ 0x40 800630e: 6c7a ldr r2, [r7, #68] @ 0x44 8006310: e841 2300 strex r3, r2, [r1] 8006314: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006316: 6bfb ldr r3, [r7, #60] @ 0x3c 8006318: 2b00 cmp r3, #0 800631a: d1e5 bne.n 80062e8 /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800631c: 6efb ldr r3, [r7, #108] @ 0x6c 800631e: 681b ldr r3, [r3, #0] 8006320: 3314 adds r3, #20 8006322: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006324: 6a7b ldr r3, [r7, #36] @ 0x24 8006326: e853 3f00 ldrex r3, [r3] 800632a: 623b str r3, [r7, #32] return(result); 800632c: 6a3b ldr r3, [r7, #32] 800632e: f023 0340 bic.w r3, r3, #64 @ 0x40 8006332: 663b str r3, [r7, #96] @ 0x60 8006334: 6efb ldr r3, [r7, #108] @ 0x6c 8006336: 681b ldr r3, [r3, #0] 8006338: 3314 adds r3, #20 800633a: 6e3a ldr r2, [r7, #96] @ 0x60 800633c: 633a str r2, [r7, #48] @ 0x30 800633e: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006340: 6af9 ldr r1, [r7, #44] @ 0x2c 8006342: 6b3a ldr r2, [r7, #48] @ 0x30 8006344: e841 2300 strex r3, r2, [r1] 8006348: 62bb str r3, [r7, #40] @ 0x28 return(result); 800634a: 6abb ldr r3, [r7, #40] @ 0x28 800634c: 2b00 cmp r3, #0 800634e: d1e5 bne.n 800631c /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006350: 6efb ldr r3, [r7, #108] @ 0x6c 8006352: 2220 movs r2, #32 8006354: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006358: 6efb ldr r3, [r7, #108] @ 0x6c 800635a: 6b1b ldr r3, [r3, #48] @ 0x30 800635c: 2b01 cmp r3, #1 800635e: d119 bne.n 8006394 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006360: 6efb ldr r3, [r7, #108] @ 0x6c 8006362: 681b ldr r3, [r3, #0] 8006364: 330c adds r3, #12 8006366: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006368: 693b ldr r3, [r7, #16] 800636a: e853 3f00 ldrex r3, [r3] 800636e: 60fb str r3, [r7, #12] return(result); 8006370: 68fb ldr r3, [r7, #12] 8006372: f023 0310 bic.w r3, r3, #16 8006376: 65fb str r3, [r7, #92] @ 0x5c 8006378: 6efb ldr r3, [r7, #108] @ 0x6c 800637a: 681b ldr r3, [r3, #0] 800637c: 330c adds r3, #12 800637e: 6dfa ldr r2, [r7, #92] @ 0x5c 8006380: 61fa str r2, [r7, #28] 8006382: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006384: 69b9 ldr r1, [r7, #24] 8006386: 69fa ldr r2, [r7, #28] 8006388: e841 2300 strex r3, r2, [r1] 800638c: 617b str r3, [r7, #20] return(result); 800638e: 697b ldr r3, [r7, #20] 8006390: 2b00 cmp r3, #0 8006392: d1e5 bne.n 8006360 } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8006394: 6efb ldr r3, [r7, #108] @ 0x6c 8006396: 2200 movs r2, #0 8006398: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800639a: 6efb ldr r3, [r7, #108] @ 0x6c 800639c: 6b1b ldr r3, [r3, #48] @ 0x30 800639e: 2b01 cmp r3, #1 80063a0: d106 bne.n 80063b0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80063a2: 6efb ldr r3, [r7, #108] @ 0x6c 80063a4: 8d9b ldrh r3, [r3, #44] @ 0x2c 80063a6: 4619 mov r1, r3 80063a8: 6ef8 ldr r0, [r7, #108] @ 0x6c 80063aa: f7ff ff0b bl 80061c4 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 80063ae: e002 b.n 80063b6 HAL_UART_RxCpltCallback(huart); 80063b0: 6ef8 ldr r0, [r7, #108] @ 0x6c 80063b2: f7fa fb5b bl 8000a6c } 80063b6: bf00 nop 80063b8: 3770 adds r7, #112 @ 0x70 80063ba: 46bd mov sp, r7 80063bc: bd80 pop {r7, pc} 080063be : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 80063be: b580 push {r7, lr} 80063c0: b084 sub sp, #16 80063c2: af00 add r7, sp, #0 80063c4: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80063c6: 687b ldr r3, [r7, #4] 80063c8: 6b9b ldr r3, [r3, #56] @ 0x38 80063ca: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 80063cc: 68fb ldr r3, [r7, #12] 80063ce: 2201 movs r2, #1 80063d0: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80063d2: 68fb ldr r3, [r7, #12] 80063d4: 6b1b ldr r3, [r3, #48] @ 0x30 80063d6: 2b01 cmp r3, #1 80063d8: d108 bne.n 80063ec #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 80063da: 68fb ldr r3, [r7, #12] 80063dc: 8d9b ldrh r3, [r3, #44] @ 0x2c 80063de: 085b lsrs r3, r3, #1 80063e0: b29b uxth r3, r3 80063e2: 4619 mov r1, r3 80063e4: 68f8 ldr r0, [r7, #12] 80063e6: f7ff feed bl 80061c4 #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 80063ea: e002 b.n 80063f2 HAL_UART_RxHalfCpltCallback(huart); 80063ec: 68f8 ldr r0, [r7, #12] 80063ee: f7ff fed5 bl 800619c } 80063f2: bf00 nop 80063f4: 3710 adds r7, #16 80063f6: 46bd mov sp, r7 80063f8: bd80 pop {r7, pc} 080063fa : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 80063fa: b580 push {r7, lr} 80063fc: b084 sub sp, #16 80063fe: af00 add r7, sp, #0 8006400: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 8006402: 2300 movs r3, #0 8006404: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006406: 687b ldr r3, [r7, #4] 8006408: 6b9b ldr r3, [r3, #56] @ 0x38 800640a: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 800640c: 68bb ldr r3, [r7, #8] 800640e: 681b ldr r3, [r3, #0] 8006410: 695b ldr r3, [r3, #20] 8006412: f003 0380 and.w r3, r3, #128 @ 0x80 8006416: 2b80 cmp r3, #128 @ 0x80 8006418: bf0c ite eq 800641a: 2301 moveq r3, #1 800641c: 2300 movne r3, #0 800641e: b2db uxtb r3, r3 8006420: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 8006422: 68bb ldr r3, [r7, #8] 8006424: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8006428: b2db uxtb r3, r3 800642a: 2b21 cmp r3, #33 @ 0x21 800642c: d108 bne.n 8006440 800642e: 68fb ldr r3, [r7, #12] 8006430: 2b00 cmp r3, #0 8006432: d005 beq.n 8006440 { huart->TxXferCount = 0x00U; 8006434: 68bb ldr r3, [r7, #8] 8006436: 2200 movs r2, #0 8006438: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 800643a: 68b8 ldr r0, [r7, #8] 800643c: f000 f8ce bl 80065dc } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8006440: 68bb ldr r3, [r7, #8] 8006442: 681b ldr r3, [r3, #0] 8006444: 695b ldr r3, [r3, #20] 8006446: f003 0340 and.w r3, r3, #64 @ 0x40 800644a: 2b40 cmp r3, #64 @ 0x40 800644c: bf0c ite eq 800644e: 2301 moveq r3, #1 8006450: 2300 movne r3, #0 8006452: b2db uxtb r3, r3 8006454: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8006456: 68bb ldr r3, [r7, #8] 8006458: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800645c: b2db uxtb r3, r3 800645e: 2b22 cmp r3, #34 @ 0x22 8006460: d108 bne.n 8006474 8006462: 68fb ldr r3, [r7, #12] 8006464: 2b00 cmp r3, #0 8006466: d005 beq.n 8006474 { huart->RxXferCount = 0x00U; 8006468: 68bb ldr r3, [r7, #8] 800646a: 2200 movs r2, #0 800646c: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 800646e: 68b8 ldr r0, [r7, #8] 8006470: f000 f8dc bl 800662c } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8006474: 68bb ldr r3, [r7, #8] 8006476: 6c5b ldr r3, [r3, #68] @ 0x44 8006478: f043 0210 orr.w r2, r3, #16 800647c: 68bb ldr r3, [r7, #8] 800647e: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006480: 68b8 ldr r0, [r7, #8] 8006482: f7ff fe95 bl 80061b0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006486: bf00 nop 8006488: 3710 adds r7, #16 800648a: 46bd mov sp, r7 800648c: bd80 pop {r7, pc} ... 08006490 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8006490: b580 push {r7, lr} 8006492: b098 sub sp, #96 @ 0x60 8006494: af00 add r7, sp, #0 8006496: 60f8 str r0, [r7, #12] 8006498: 60b9 str r1, [r7, #8] 800649a: 4613 mov r3, r2 800649c: 80fb strh r3, [r7, #6] uint32_t *tmp; huart->pRxBuffPtr = pData; 800649e: 68ba ldr r2, [r7, #8] 80064a0: 68fb ldr r3, [r7, #12] 80064a2: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 80064a4: 68fb ldr r3, [r7, #12] 80064a6: 88fa ldrh r2, [r7, #6] 80064a8: 859a strh r2, [r3, #44] @ 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 80064aa: 68fb ldr r3, [r7, #12] 80064ac: 2200 movs r2, #0 80064ae: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 80064b0: 68fb ldr r3, [r7, #12] 80064b2: 2222 movs r2, #34 @ 0x22 80064b4: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 80064b8: 68fb ldr r3, [r7, #12] 80064ba: 6bdb ldr r3, [r3, #60] @ 0x3c 80064bc: 4a44 ldr r2, [pc, #272] @ (80065d0 ) 80064be: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 80064c0: 68fb ldr r3, [r7, #12] 80064c2: 6bdb ldr r3, [r3, #60] @ 0x3c 80064c4: 4a43 ldr r2, [pc, #268] @ (80065d4 ) 80064c6: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 80064c8: 68fb ldr r3, [r7, #12] 80064ca: 6bdb ldr r3, [r3, #60] @ 0x3c 80064cc: 4a42 ldr r2, [pc, #264] @ (80065d8 ) 80064ce: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 80064d0: 68fb ldr r3, [r7, #12] 80064d2: 6bdb ldr r3, [r3, #60] @ 0x3c 80064d4: 2200 movs r2, #0 80064d6: 651a str r2, [r3, #80] @ 0x50 /* Enable the DMA stream */ tmp = (uint32_t *)&pData; 80064d8: f107 0308 add.w r3, r7, #8 80064dc: 65fb str r3, [r7, #92] @ 0x5c if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK) 80064de: 68fb ldr r3, [r7, #12] 80064e0: 6bd8 ldr r0, [r3, #60] @ 0x3c 80064e2: 68fb ldr r3, [r7, #12] 80064e4: 681b ldr r3, [r3, #0] 80064e6: 3304 adds r3, #4 80064e8: 4619 mov r1, r3 80064ea: 6dfb ldr r3, [r7, #92] @ 0x5c 80064ec: 681a ldr r2, [r3, #0] 80064ee: 88fb ldrh r3, [r7, #6] 80064f0: f7fb fc8a bl 8001e08 80064f4: 4603 mov r3, r0 80064f6: 2b00 cmp r3, #0 80064f8: d008 beq.n 800650c { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 80064fa: 68fb ldr r3, [r7, #12] 80064fc: 2210 movs r2, #16 80064fe: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; 8006500: 68fb ldr r3, [r7, #12] 8006502: 2220 movs r2, #32 8006504: f883 2042 strb.w r2, [r3, #66] @ 0x42 return HAL_ERROR; 8006508: 2301 movs r3, #1 800650a: e05d b.n 80065c8 } /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 800650c: 2300 movs r3, #0 800650e: 613b str r3, [r7, #16] 8006510: 68fb ldr r3, [r7, #12] 8006512: 681b ldr r3, [r3, #0] 8006514: 681b ldr r3, [r3, #0] 8006516: 613b str r3, [r7, #16] 8006518: 68fb ldr r3, [r7, #12] 800651a: 681b ldr r3, [r3, #0] 800651c: 685b ldr r3, [r3, #4] 800651e: 613b str r3, [r7, #16] 8006520: 693b ldr r3, [r7, #16] if (huart->Init.Parity != UART_PARITY_NONE) 8006522: 68fb ldr r3, [r7, #12] 8006524: 691b ldr r3, [r3, #16] 8006526: 2b00 cmp r3, #0 8006528: d019 beq.n 800655e { /* Enable the UART Parity Error Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800652a: 68fb ldr r3, [r7, #12] 800652c: 681b ldr r3, [r3, #0] 800652e: 330c adds r3, #12 8006530: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006532: 6c3b ldr r3, [r7, #64] @ 0x40 8006534: e853 3f00 ldrex r3, [r3] 8006538: 63fb str r3, [r7, #60] @ 0x3c return(result); 800653a: 6bfb ldr r3, [r7, #60] @ 0x3c 800653c: f443 7380 orr.w r3, r3, #256 @ 0x100 8006540: 65bb str r3, [r7, #88] @ 0x58 8006542: 68fb ldr r3, [r7, #12] 8006544: 681b ldr r3, [r3, #0] 8006546: 330c adds r3, #12 8006548: 6dba ldr r2, [r7, #88] @ 0x58 800654a: 64fa str r2, [r7, #76] @ 0x4c 800654c: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800654e: 6cb9 ldr r1, [r7, #72] @ 0x48 8006550: 6cfa ldr r2, [r7, #76] @ 0x4c 8006552: e841 2300 strex r3, r2, [r1] 8006556: 647b str r3, [r7, #68] @ 0x44 return(result); 8006558: 6c7b ldr r3, [r7, #68] @ 0x44 800655a: 2b00 cmp r3, #0 800655c: d1e5 bne.n 800652a } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 800655e: 68fb ldr r3, [r7, #12] 8006560: 681b ldr r3, [r3, #0] 8006562: 3314 adds r3, #20 8006564: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006566: 6afb ldr r3, [r7, #44] @ 0x2c 8006568: e853 3f00 ldrex r3, [r3] 800656c: 62bb str r3, [r7, #40] @ 0x28 return(result); 800656e: 6abb ldr r3, [r7, #40] @ 0x28 8006570: f043 0301 orr.w r3, r3, #1 8006574: 657b str r3, [r7, #84] @ 0x54 8006576: 68fb ldr r3, [r7, #12] 8006578: 681b ldr r3, [r3, #0] 800657a: 3314 adds r3, #20 800657c: 6d7a ldr r2, [r7, #84] @ 0x54 800657e: 63ba str r2, [r7, #56] @ 0x38 8006580: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006582: 6b79 ldr r1, [r7, #52] @ 0x34 8006584: 6bba ldr r2, [r7, #56] @ 0x38 8006586: e841 2300 strex r3, r2, [r1] 800658a: 633b str r3, [r7, #48] @ 0x30 return(result); 800658c: 6b3b ldr r3, [r7, #48] @ 0x30 800658e: 2b00 cmp r3, #0 8006590: d1e5 bne.n 800655e /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8006592: 68fb ldr r3, [r7, #12] 8006594: 681b ldr r3, [r3, #0] 8006596: 3314 adds r3, #20 8006598: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800659a: 69bb ldr r3, [r7, #24] 800659c: e853 3f00 ldrex r3, [r3] 80065a0: 617b str r3, [r7, #20] return(result); 80065a2: 697b ldr r3, [r7, #20] 80065a4: f043 0340 orr.w r3, r3, #64 @ 0x40 80065a8: 653b str r3, [r7, #80] @ 0x50 80065aa: 68fb ldr r3, [r7, #12] 80065ac: 681b ldr r3, [r3, #0] 80065ae: 3314 adds r3, #20 80065b0: 6d3a ldr r2, [r7, #80] @ 0x50 80065b2: 627a str r2, [r7, #36] @ 0x24 80065b4: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80065b6: 6a39 ldr r1, [r7, #32] 80065b8: 6a7a ldr r2, [r7, #36] @ 0x24 80065ba: e841 2300 strex r3, r2, [r1] 80065be: 61fb str r3, [r7, #28] return(result); 80065c0: 69fb ldr r3, [r7, #28] 80065c2: 2b00 cmp r3, #0 80065c4: d1e5 bne.n 8006592 return HAL_OK; 80065c6: 2300 movs r3, #0 } 80065c8: 4618 mov r0, r3 80065ca: 3760 adds r7, #96 @ 0x60 80065cc: 46bd mov sp, r7 80065ce: bd80 pop {r7, pc} 80065d0: 08006293 .word 0x08006293 80065d4: 080063bf .word 0x080063bf 80065d8: 080063fb .word 0x080063fb 080065dc : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 80065dc: b480 push {r7} 80065de: b089 sub sp, #36 @ 0x24 80065e0: af00 add r7, sp, #0 80065e2: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 80065e4: 687b ldr r3, [r7, #4] 80065e6: 681b ldr r3, [r3, #0] 80065e8: 330c adds r3, #12 80065ea: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80065ec: 68fb ldr r3, [r7, #12] 80065ee: e853 3f00 ldrex r3, [r3] 80065f2: 60bb str r3, [r7, #8] return(result); 80065f4: 68bb ldr r3, [r7, #8] 80065f6: f023 03c0 bic.w r3, r3, #192 @ 0xc0 80065fa: 61fb str r3, [r7, #28] 80065fc: 687b ldr r3, [r7, #4] 80065fe: 681b ldr r3, [r3, #0] 8006600: 330c adds r3, #12 8006602: 69fa ldr r2, [r7, #28] 8006604: 61ba str r2, [r7, #24] 8006606: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006608: 6979 ldr r1, [r7, #20] 800660a: 69ba ldr r2, [r7, #24] 800660c: e841 2300 strex r3, r2, [r1] 8006610: 613b str r3, [r7, #16] return(result); 8006612: 693b ldr r3, [r7, #16] 8006614: 2b00 cmp r3, #0 8006616: d1e5 bne.n 80065e4 /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8006618: 687b ldr r3, [r7, #4] 800661a: 2220 movs r2, #32 800661c: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 8006620: bf00 nop 8006622: 3724 adds r7, #36 @ 0x24 8006624: 46bd mov sp, r7 8006626: f85d 7b04 ldr.w r7, [sp], #4 800662a: 4770 bx lr 0800662c : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 800662c: b480 push {r7} 800662e: b095 sub sp, #84 @ 0x54 8006630: af00 add r7, sp, #0 8006632: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8006634: 687b ldr r3, [r7, #4] 8006636: 681b ldr r3, [r3, #0] 8006638: 330c adds r3, #12 800663a: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800663c: 6b7b ldr r3, [r7, #52] @ 0x34 800663e: e853 3f00 ldrex r3, [r3] 8006642: 633b str r3, [r7, #48] @ 0x30 return(result); 8006644: 6b3b ldr r3, [r7, #48] @ 0x30 8006646: f423 7390 bic.w r3, r3, #288 @ 0x120 800664a: 64fb str r3, [r7, #76] @ 0x4c 800664c: 687b ldr r3, [r7, #4] 800664e: 681b ldr r3, [r3, #0] 8006650: 330c adds r3, #12 8006652: 6cfa ldr r2, [r7, #76] @ 0x4c 8006654: 643a str r2, [r7, #64] @ 0x40 8006656: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006658: 6bf9 ldr r1, [r7, #60] @ 0x3c 800665a: 6c3a ldr r2, [r7, #64] @ 0x40 800665c: e841 2300 strex r3, r2, [r1] 8006660: 63bb str r3, [r7, #56] @ 0x38 return(result); 8006662: 6bbb ldr r3, [r7, #56] @ 0x38 8006664: 2b00 cmp r3, #0 8006666: d1e5 bne.n 8006634 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006668: 687b ldr r3, [r7, #4] 800666a: 681b ldr r3, [r3, #0] 800666c: 3314 adds r3, #20 800666e: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006670: 6a3b ldr r3, [r7, #32] 8006672: e853 3f00 ldrex r3, [r3] 8006676: 61fb str r3, [r7, #28] return(result); 8006678: 69fb ldr r3, [r7, #28] 800667a: f023 0301 bic.w r3, r3, #1 800667e: 64bb str r3, [r7, #72] @ 0x48 8006680: 687b ldr r3, [r7, #4] 8006682: 681b ldr r3, [r3, #0] 8006684: 3314 adds r3, #20 8006686: 6cba ldr r2, [r7, #72] @ 0x48 8006688: 62fa str r2, [r7, #44] @ 0x2c 800668a: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800668c: 6ab9 ldr r1, [r7, #40] @ 0x28 800668e: 6afa ldr r2, [r7, #44] @ 0x2c 8006690: e841 2300 strex r3, r2, [r1] 8006694: 627b str r3, [r7, #36] @ 0x24 return(result); 8006696: 6a7b ldr r3, [r7, #36] @ 0x24 8006698: 2b00 cmp r3, #0 800669a: d1e5 bne.n 8006668 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800669c: 687b ldr r3, [r7, #4] 800669e: 6b1b ldr r3, [r3, #48] @ 0x30 80066a0: 2b01 cmp r3, #1 80066a2: d119 bne.n 80066d8 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80066a4: 687b ldr r3, [r7, #4] 80066a6: 681b ldr r3, [r3, #0] 80066a8: 330c adds r3, #12 80066aa: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80066ac: 68fb ldr r3, [r7, #12] 80066ae: e853 3f00 ldrex r3, [r3] 80066b2: 60bb str r3, [r7, #8] return(result); 80066b4: 68bb ldr r3, [r7, #8] 80066b6: f023 0310 bic.w r3, r3, #16 80066ba: 647b str r3, [r7, #68] @ 0x44 80066bc: 687b ldr r3, [r7, #4] 80066be: 681b ldr r3, [r3, #0] 80066c0: 330c adds r3, #12 80066c2: 6c7a ldr r2, [r7, #68] @ 0x44 80066c4: 61ba str r2, [r7, #24] 80066c6: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80066c8: 6979 ldr r1, [r7, #20] 80066ca: 69ba ldr r2, [r7, #24] 80066cc: e841 2300 strex r3, r2, [r1] 80066d0: 613b str r3, [r7, #16] return(result); 80066d2: 693b ldr r3, [r7, #16] 80066d4: 2b00 cmp r3, #0 80066d6: d1e5 bne.n 80066a4 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80066d8: 687b ldr r3, [r7, #4] 80066da: 2220 movs r2, #32 80066dc: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80066e0: 687b ldr r3, [r7, #4] 80066e2: 2200 movs r2, #0 80066e4: 631a str r2, [r3, #48] @ 0x30 } 80066e6: bf00 nop 80066e8: 3754 adds r7, #84 @ 0x54 80066ea: 46bd mov sp, r7 80066ec: f85d 7b04 ldr.w r7, [sp], #4 80066f0: 4770 bx lr 080066f2 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 80066f2: b580 push {r7, lr} 80066f4: b084 sub sp, #16 80066f6: af00 add r7, sp, #0 80066f8: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80066fa: 687b ldr r3, [r7, #4] 80066fc: 6b9b ldr r3, [r3, #56] @ 0x38 80066fe: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8006700: 68fb ldr r3, [r7, #12] 8006702: 2200 movs r2, #0 8006704: 85da strh r2, [r3, #46] @ 0x2e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006706: 68f8 ldr r0, [r7, #12] 8006708: f7ff fd52 bl 80061b0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800670c: bf00 nop 800670e: 3710 adds r7, #16 8006710: 46bd mov sp, r7 8006712: bd80 pop {r7, pc} 08006714 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8006714: b480 push {r7} 8006716: b085 sub sp, #20 8006718: af00 add r7, sp, #0 800671a: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 800671c: 687b ldr r3, [r7, #4] 800671e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8006722: b2db uxtb r3, r3 8006724: 2b21 cmp r3, #33 @ 0x21 8006726: d13e bne.n 80067a6 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006728: 687b ldr r3, [r7, #4] 800672a: 689b ldr r3, [r3, #8] 800672c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006730: d114 bne.n 800675c 8006732: 687b ldr r3, [r7, #4] 8006734: 691b ldr r3, [r3, #16] 8006736: 2b00 cmp r3, #0 8006738: d110 bne.n 800675c { tmp = (const uint16_t *) huart->pTxBuffPtr; 800673a: 687b ldr r3, [r7, #4] 800673c: 6a1b ldr r3, [r3, #32] 800673e: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8006740: 68fb ldr r3, [r7, #12] 8006742: 881b ldrh r3, [r3, #0] 8006744: 461a mov r2, r3 8006746: 687b ldr r3, [r7, #4] 8006748: 681b ldr r3, [r3, #0] 800674a: f3c2 0208 ubfx r2, r2, #0, #9 800674e: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8006750: 687b ldr r3, [r7, #4] 8006752: 6a1b ldr r3, [r3, #32] 8006754: 1c9a adds r2, r3, #2 8006756: 687b ldr r3, [r7, #4] 8006758: 621a str r2, [r3, #32] 800675a: e008 b.n 800676e } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 800675c: 687b ldr r3, [r7, #4] 800675e: 6a1b ldr r3, [r3, #32] 8006760: 1c59 adds r1, r3, #1 8006762: 687a ldr r2, [r7, #4] 8006764: 6211 str r1, [r2, #32] 8006766: 781a ldrb r2, [r3, #0] 8006768: 687b ldr r3, [r7, #4] 800676a: 681b ldr r3, [r3, #0] 800676c: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 800676e: 687b ldr r3, [r7, #4] 8006770: 8cdb ldrh r3, [r3, #38] @ 0x26 8006772: b29b uxth r3, r3 8006774: 3b01 subs r3, #1 8006776: b29b uxth r3, r3 8006778: 687a ldr r2, [r7, #4] 800677a: 4619 mov r1, r3 800677c: 84d1 strh r1, [r2, #38] @ 0x26 800677e: 2b00 cmp r3, #0 8006780: d10f bne.n 80067a2 { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8006782: 687b ldr r3, [r7, #4] 8006784: 681b ldr r3, [r3, #0] 8006786: 68da ldr r2, [r3, #12] 8006788: 687b ldr r3, [r7, #4] 800678a: 681b ldr r3, [r3, #0] 800678c: f022 0280 bic.w r2, r2, #128 @ 0x80 8006790: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8006792: 687b ldr r3, [r7, #4] 8006794: 681b ldr r3, [r3, #0] 8006796: 68da ldr r2, [r3, #12] 8006798: 687b ldr r3, [r7, #4] 800679a: 681b ldr r3, [r3, #0] 800679c: f042 0240 orr.w r2, r2, #64 @ 0x40 80067a0: 60da str r2, [r3, #12] } return HAL_OK; 80067a2: 2300 movs r3, #0 80067a4: e000 b.n 80067a8 } else { return HAL_BUSY; 80067a6: 2302 movs r3, #2 } } 80067a8: 4618 mov r0, r3 80067aa: 3714 adds r7, #20 80067ac: 46bd mov sp, r7 80067ae: f85d 7b04 ldr.w r7, [sp], #4 80067b2: 4770 bx lr 080067b4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80067b4: b580 push {r7, lr} 80067b6: b082 sub sp, #8 80067b8: af00 add r7, sp, #0 80067ba: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 80067bc: 687b ldr r3, [r7, #4] 80067be: 681b ldr r3, [r3, #0] 80067c0: 68da ldr r2, [r3, #12] 80067c2: 687b ldr r3, [r7, #4] 80067c4: 681b ldr r3, [r3, #0] 80067c6: f022 0240 bic.w r2, r2, #64 @ 0x40 80067ca: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80067cc: 687b ldr r3, [r7, #4] 80067ce: 2220 movs r2, #32 80067d0: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 80067d4: 6878 ldr r0, [r7, #4] 80067d6: f7ff fccd bl 8006174 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 80067da: 2300 movs r3, #0 } 80067dc: 4618 mov r0, r3 80067de: 3708 adds r7, #8 80067e0: 46bd mov sp, r7 80067e2: bd80 pop {r7, pc} 080067e4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 80067e4: b580 push {r7, lr} 80067e6: b08c sub sp, #48 @ 0x30 80067e8: af00 add r7, sp, #0 80067ea: 6078 str r0, [r7, #4] uint8_t *pdata8bits = NULL; 80067ec: 2300 movs r3, #0 80067ee: 62fb str r3, [r7, #44] @ 0x2c uint16_t *pdata16bits = NULL; 80067f0: 2300 movs r3, #0 80067f2: 62bb str r3, [r7, #40] @ 0x28 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80067f4: 687b ldr r3, [r7, #4] 80067f6: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80067fa: b2db uxtb r3, r3 80067fc: 2b22 cmp r3, #34 @ 0x22 80067fe: f040 80aa bne.w 8006956 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006802: 687b ldr r3, [r7, #4] 8006804: 689b ldr r3, [r3, #8] 8006806: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800680a: d115 bne.n 8006838 800680c: 687b ldr r3, [r7, #4] 800680e: 691b ldr r3, [r3, #16] 8006810: 2b00 cmp r3, #0 8006812: d111 bne.n 8006838 { /* Unused pdata8bits */ UNUSED(pdata8bits); pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8006814: 687b ldr r3, [r7, #4] 8006816: 6a9b ldr r3, [r3, #40] @ 0x28 8006818: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 800681a: 687b ldr r3, [r7, #4] 800681c: 681b ldr r3, [r3, #0] 800681e: 685b ldr r3, [r3, #4] 8006820: b29b uxth r3, r3 8006822: f3c3 0308 ubfx r3, r3, #0, #9 8006826: b29a uxth r2, r3 8006828: 6abb ldr r3, [r7, #40] @ 0x28 800682a: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 800682c: 687b ldr r3, [r7, #4] 800682e: 6a9b ldr r3, [r3, #40] @ 0x28 8006830: 1c9a adds r2, r3, #2 8006832: 687b ldr r3, [r7, #4] 8006834: 629a str r2, [r3, #40] @ 0x28 8006836: e024 b.n 8006882 } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8006838: 687b ldr r3, [r7, #4] 800683a: 6a9b ldr r3, [r3, #40] @ 0x28 800683c: 62fb str r3, [r7, #44] @ 0x2c /* Unused pdata16bits */ UNUSED(pdata16bits); if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 800683e: 687b ldr r3, [r7, #4] 8006840: 689b ldr r3, [r3, #8] 8006842: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006846: d007 beq.n 8006858 8006848: 687b ldr r3, [r7, #4] 800684a: 689b ldr r3, [r3, #8] 800684c: 2b00 cmp r3, #0 800684e: d10a bne.n 8006866 8006850: 687b ldr r3, [r7, #4] 8006852: 691b ldr r3, [r3, #16] 8006854: 2b00 cmp r3, #0 8006856: d106 bne.n 8006866 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8006858: 687b ldr r3, [r7, #4] 800685a: 681b ldr r3, [r3, #0] 800685c: 685b ldr r3, [r3, #4] 800685e: b2da uxtb r2, r3 8006860: 6afb ldr r3, [r7, #44] @ 0x2c 8006862: 701a strb r2, [r3, #0] 8006864: e008 b.n 8006878 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8006866: 687b ldr r3, [r7, #4] 8006868: 681b ldr r3, [r3, #0] 800686a: 685b ldr r3, [r3, #4] 800686c: b2db uxtb r3, r3 800686e: f003 037f and.w r3, r3, #127 @ 0x7f 8006872: b2da uxtb r2, r3 8006874: 6afb ldr r3, [r7, #44] @ 0x2c 8006876: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8006878: 687b ldr r3, [r7, #4] 800687a: 6a9b ldr r3, [r3, #40] @ 0x28 800687c: 1c5a adds r2, r3, #1 800687e: 687b ldr r3, [r7, #4] 8006880: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8006882: 687b ldr r3, [r7, #4] 8006884: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006886: b29b uxth r3, r3 8006888: 3b01 subs r3, #1 800688a: b29b uxth r3, r3 800688c: 687a ldr r2, [r7, #4] 800688e: 4619 mov r1, r3 8006890: 85d1 strh r1, [r2, #46] @ 0x2e 8006892: 2b00 cmp r3, #0 8006894: d15d bne.n 8006952 { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8006896: 687b ldr r3, [r7, #4] 8006898: 681b ldr r3, [r3, #0] 800689a: 68da ldr r2, [r3, #12] 800689c: 687b ldr r3, [r7, #4] 800689e: 681b ldr r3, [r3, #0] 80068a0: f022 0220 bic.w r2, r2, #32 80068a4: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 80068a6: 687b ldr r3, [r7, #4] 80068a8: 681b ldr r3, [r3, #0] 80068aa: 68da ldr r2, [r3, #12] 80068ac: 687b ldr r3, [r7, #4] 80068ae: 681b ldr r3, [r3, #0] 80068b0: f422 7280 bic.w r2, r2, #256 @ 0x100 80068b4: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 80068b6: 687b ldr r3, [r7, #4] 80068b8: 681b ldr r3, [r3, #0] 80068ba: 695a ldr r2, [r3, #20] 80068bc: 687b ldr r3, [r7, #4] 80068be: 681b ldr r3, [r3, #0] 80068c0: f022 0201 bic.w r2, r2, #1 80068c4: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80068c6: 687b ldr r3, [r7, #4] 80068c8: 2220 movs r2, #32 80068ca: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80068ce: 687b ldr r3, [r7, #4] 80068d0: 2200 movs r2, #0 80068d2: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80068d4: 687b ldr r3, [r7, #4] 80068d6: 6b1b ldr r3, [r3, #48] @ 0x30 80068d8: 2b01 cmp r3, #1 80068da: d135 bne.n 8006948 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80068dc: 687b ldr r3, [r7, #4] 80068de: 2200 movs r2, #0 80068e0: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80068e2: 687b ldr r3, [r7, #4] 80068e4: 681b ldr r3, [r3, #0] 80068e6: 330c adds r3, #12 80068e8: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80068ea: 697b ldr r3, [r7, #20] 80068ec: e853 3f00 ldrex r3, [r3] 80068f0: 613b str r3, [r7, #16] return(result); 80068f2: 693b ldr r3, [r7, #16] 80068f4: f023 0310 bic.w r3, r3, #16 80068f8: 627b str r3, [r7, #36] @ 0x24 80068fa: 687b ldr r3, [r7, #4] 80068fc: 681b ldr r3, [r3, #0] 80068fe: 330c adds r3, #12 8006900: 6a7a ldr r2, [r7, #36] @ 0x24 8006902: 623a str r2, [r7, #32] 8006904: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006906: 69f9 ldr r1, [r7, #28] 8006908: 6a3a ldr r2, [r7, #32] 800690a: e841 2300 strex r3, r2, [r1] 800690e: 61bb str r3, [r7, #24] return(result); 8006910: 69bb ldr r3, [r7, #24] 8006912: 2b00 cmp r3, #0 8006914: d1e5 bne.n 80068e2 /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8006916: 687b ldr r3, [r7, #4] 8006918: 681b ldr r3, [r3, #0] 800691a: 681b ldr r3, [r3, #0] 800691c: f003 0310 and.w r3, r3, #16 8006920: 2b10 cmp r3, #16 8006922: d10a bne.n 800693a { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8006924: 2300 movs r3, #0 8006926: 60fb str r3, [r7, #12] 8006928: 687b ldr r3, [r7, #4] 800692a: 681b ldr r3, [r3, #0] 800692c: 681b ldr r3, [r3, #0] 800692e: 60fb str r3, [r7, #12] 8006930: 687b ldr r3, [r7, #4] 8006932: 681b ldr r3, [r3, #0] 8006934: 685b ldr r3, [r3, #4] 8006936: 60fb str r3, [r7, #12] 8006938: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800693a: 687b ldr r3, [r7, #4] 800693c: 8d9b ldrh r3, [r3, #44] @ 0x2c 800693e: 4619 mov r1, r3 8006940: 6878 ldr r0, [r7, #4] 8006942: f7ff fc3f bl 80061c4 8006946: e002 b.n 800694e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8006948: 6878 ldr r0, [r7, #4] 800694a: f7fa f88f bl 8000a6c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 800694e: 2300 movs r3, #0 8006950: e002 b.n 8006958 } return HAL_OK; 8006952: 2300 movs r3, #0 8006954: e000 b.n 8006958 } else { return HAL_BUSY; 8006956: 2302 movs r3, #2 } } 8006958: 4618 mov r0, r3 800695a: 3730 adds r7, #48 @ 0x30 800695c: 46bd mov sp, r7 800695e: bd80 pop {r7, pc} 08006960 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8006960: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8006964: b0c0 sub sp, #256 @ 0x100 8006966: af00 add r7, sp, #0 8006968: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4 assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 800696c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006970: 681b ldr r3, [r3, #0] 8006972: 691b ldr r3, [r3, #16] 8006974: f423 5040 bic.w r0, r3, #12288 @ 0x3000 8006978: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800697c: 68d9 ldr r1, [r3, #12] 800697e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006982: 681a ldr r2, [r3, #0] 8006984: ea40 0301 orr.w r3, r0, r1 8006988: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 800698a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800698e: 689a ldr r2, [r3, #8] 8006990: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006994: 691b ldr r3, [r3, #16] 8006996: 431a orrs r2, r3 8006998: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800699c: 695b ldr r3, [r3, #20] 800699e: 431a orrs r2, r3 80069a0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80069a4: 69db ldr r3, [r3, #28] 80069a6: 4313 orrs r3, r2 80069a8: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 MODIFY_REG(huart->Instance->CR1, 80069ac: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80069b0: 681b ldr r3, [r3, #0] 80069b2: 68db ldr r3, [r3, #12] 80069b4: f423 4116 bic.w r1, r3, #38400 @ 0x9600 80069b8: f021 010c bic.w r1, r1, #12 80069bc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80069c0: 681a ldr r2, [r3, #0] 80069c2: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 80069c6: 430b orrs r3, r1 80069c8: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 80069ca: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80069ce: 681b ldr r3, [r3, #0] 80069d0: 695b ldr r3, [r3, #20] 80069d2: f423 7040 bic.w r0, r3, #768 @ 0x300 80069d6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80069da: 6999 ldr r1, [r3, #24] 80069dc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80069e0: 681a ldr r2, [r3, #0] 80069e2: ea40 0301 orr.w r3, r0, r1 80069e6: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 80069e8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80069ec: 681a ldr r2, [r3, #0] 80069ee: 4b8f ldr r3, [pc, #572] @ (8006c2c ) 80069f0: 429a cmp r2, r3 80069f2: d005 beq.n 8006a00 80069f4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80069f8: 681a ldr r2, [r3, #0] 80069fa: 4b8d ldr r3, [pc, #564] @ (8006c30 ) 80069fc: 429a cmp r2, r3 80069fe: d104 bne.n 8006a0a { pclk = HAL_RCC_GetPCLK2Freq(); 8006a00: f7fd fbec bl 80041dc 8006a04: f8c7 00fc str.w r0, [r7, #252] @ 0xfc 8006a08: e003 b.n 8006a12 pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); 8006a0a: f7fd fbd3 bl 80041b4 8006a0e: f8c7 00fc str.w r0, [r7, #252] @ 0xfc } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8006a12: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006a16: 69db ldr r3, [r3, #28] 8006a18: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8006a1c: f040 810c bne.w 8006c38 { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8006a20: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006a24: 2200 movs r2, #0 8006a26: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 8006a2a: f8c7 20ec str.w r2, [r7, #236] @ 0xec 8006a2e: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8 8006a32: 4622 mov r2, r4 8006a34: 462b mov r3, r5 8006a36: 1891 adds r1, r2, r2 8006a38: 65b9 str r1, [r7, #88] @ 0x58 8006a3a: 415b adcs r3, r3 8006a3c: 65fb str r3, [r7, #92] @ 0x5c 8006a3e: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8006a42: 4621 mov r1, r4 8006a44: eb12 0801 adds.w r8, r2, r1 8006a48: 4629 mov r1, r5 8006a4a: eb43 0901 adc.w r9, r3, r1 8006a4e: f04f 0200 mov.w r2, #0 8006a52: f04f 0300 mov.w r3, #0 8006a56: ea4f 03c9 mov.w r3, r9, lsl #3 8006a5a: ea43 7358 orr.w r3, r3, r8, lsr #29 8006a5e: ea4f 02c8 mov.w r2, r8, lsl #3 8006a62: 4690 mov r8, r2 8006a64: 4699 mov r9, r3 8006a66: 4623 mov r3, r4 8006a68: eb18 0303 adds.w r3, r8, r3 8006a6c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 8006a70: 462b mov r3, r5 8006a72: eb49 0303 adc.w r3, r9, r3 8006a76: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 8006a7a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006a7e: 685b ldr r3, [r3, #4] 8006a80: 2200 movs r2, #0 8006a82: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 8006a86: f8c7 20dc str.w r2, [r7, #220] @ 0xdc 8006a8a: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 8006a8e: 460b mov r3, r1 8006a90: 18db adds r3, r3, r3 8006a92: 653b str r3, [r7, #80] @ 0x50 8006a94: 4613 mov r3, r2 8006a96: eb42 0303 adc.w r3, r2, r3 8006a9a: 657b str r3, [r7, #84] @ 0x54 8006a9c: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50 8006aa0: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0 8006aa4: f7f9 fbae bl 8000204 <__aeabi_uldivmod> 8006aa8: 4602 mov r2, r0 8006aaa: 460b mov r3, r1 8006aac: 4b61 ldr r3, [pc, #388] @ (8006c34 ) 8006aae: fba3 2302 umull r2, r3, r3, r2 8006ab2: 095b lsrs r3, r3, #5 8006ab4: 011c lsls r4, r3, #4 8006ab6: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006aba: 2200 movs r2, #0 8006abc: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8006ac0: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4 8006ac4: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0 8006ac8: 4642 mov r2, r8 8006aca: 464b mov r3, r9 8006acc: 1891 adds r1, r2, r2 8006ace: 64b9 str r1, [r7, #72] @ 0x48 8006ad0: 415b adcs r3, r3 8006ad2: 64fb str r3, [r7, #76] @ 0x4c 8006ad4: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8006ad8: 4641 mov r1, r8 8006ada: eb12 0a01 adds.w sl, r2, r1 8006ade: 4649 mov r1, r9 8006ae0: eb43 0b01 adc.w fp, r3, r1 8006ae4: f04f 0200 mov.w r2, #0 8006ae8: f04f 0300 mov.w r3, #0 8006aec: ea4f 03cb mov.w r3, fp, lsl #3 8006af0: ea43 735a orr.w r3, r3, sl, lsr #29 8006af4: ea4f 02ca mov.w r2, sl, lsl #3 8006af8: 4692 mov sl, r2 8006afa: 469b mov fp, r3 8006afc: 4643 mov r3, r8 8006afe: eb1a 0303 adds.w r3, sl, r3 8006b02: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8006b06: 464b mov r3, r9 8006b08: eb4b 0303 adc.w r3, fp, r3 8006b0c: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 8006b10: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b14: 685b ldr r3, [r3, #4] 8006b16: 2200 movs r2, #0 8006b18: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8006b1c: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4 8006b20: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 8006b24: 460b mov r3, r1 8006b26: 18db adds r3, r3, r3 8006b28: 643b str r3, [r7, #64] @ 0x40 8006b2a: 4613 mov r3, r2 8006b2c: eb42 0303 adc.w r3, r2, r3 8006b30: 647b str r3, [r7, #68] @ 0x44 8006b32: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40 8006b36: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8 8006b3a: f7f9 fb63 bl 8000204 <__aeabi_uldivmod> 8006b3e: 4602 mov r2, r0 8006b40: 460b mov r3, r1 8006b42: 4611 mov r1, r2 8006b44: 4b3b ldr r3, [pc, #236] @ (8006c34 ) 8006b46: fba3 2301 umull r2, r3, r3, r1 8006b4a: 095b lsrs r3, r3, #5 8006b4c: 2264 movs r2, #100 @ 0x64 8006b4e: fb02 f303 mul.w r3, r2, r3 8006b52: 1acb subs r3, r1, r3 8006b54: 00db lsls r3, r3, #3 8006b56: f103 0232 add.w r2, r3, #50 @ 0x32 8006b5a: 4b36 ldr r3, [pc, #216] @ (8006c34 ) 8006b5c: fba3 2302 umull r2, r3, r3, r2 8006b60: 095b lsrs r3, r3, #5 8006b62: 005b lsls r3, r3, #1 8006b64: f403 73f8 and.w r3, r3, #496 @ 0x1f0 8006b68: 441c add r4, r3 8006b6a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006b6e: 2200 movs r2, #0 8006b70: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006b74: f8c7 20bc str.w r2, [r7, #188] @ 0xbc 8006b78: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8 8006b7c: 4642 mov r2, r8 8006b7e: 464b mov r3, r9 8006b80: 1891 adds r1, r2, r2 8006b82: 63b9 str r1, [r7, #56] @ 0x38 8006b84: 415b adcs r3, r3 8006b86: 63fb str r3, [r7, #60] @ 0x3c 8006b88: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38 8006b8c: 4641 mov r1, r8 8006b8e: 1851 adds r1, r2, r1 8006b90: 6339 str r1, [r7, #48] @ 0x30 8006b92: 4649 mov r1, r9 8006b94: 414b adcs r3, r1 8006b96: 637b str r3, [r7, #52] @ 0x34 8006b98: f04f 0200 mov.w r2, #0 8006b9c: f04f 0300 mov.w r3, #0 8006ba0: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30 8006ba4: 4659 mov r1, fp 8006ba6: 00cb lsls r3, r1, #3 8006ba8: 4651 mov r1, sl 8006baa: ea43 7351 orr.w r3, r3, r1, lsr #29 8006bae: 4651 mov r1, sl 8006bb0: 00ca lsls r2, r1, #3 8006bb2: 4610 mov r0, r2 8006bb4: 4619 mov r1, r3 8006bb6: 4603 mov r3, r0 8006bb8: 4642 mov r2, r8 8006bba: 189b adds r3, r3, r2 8006bbc: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8006bc0: 464b mov r3, r9 8006bc2: 460a mov r2, r1 8006bc4: eb42 0303 adc.w r3, r2, r3 8006bc8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8006bcc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006bd0: 685b ldr r3, [r3, #4] 8006bd2: 2200 movs r2, #0 8006bd4: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 8006bd8: f8c7 20ac str.w r2, [r7, #172] @ 0xac 8006bdc: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 8006be0: 460b mov r3, r1 8006be2: 18db adds r3, r3, r3 8006be4: 62bb str r3, [r7, #40] @ 0x28 8006be6: 4613 mov r3, r2 8006be8: eb42 0303 adc.w r3, r2, r3 8006bec: 62fb str r3, [r7, #44] @ 0x2c 8006bee: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 8006bf2: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0 8006bf6: f7f9 fb05 bl 8000204 <__aeabi_uldivmod> 8006bfa: 4602 mov r2, r0 8006bfc: 460b mov r3, r1 8006bfe: 4b0d ldr r3, [pc, #52] @ (8006c34 ) 8006c00: fba3 1302 umull r1, r3, r3, r2 8006c04: 095b lsrs r3, r3, #5 8006c06: 2164 movs r1, #100 @ 0x64 8006c08: fb01 f303 mul.w r3, r1, r3 8006c0c: 1ad3 subs r3, r2, r3 8006c0e: 00db lsls r3, r3, #3 8006c10: 3332 adds r3, #50 @ 0x32 8006c12: 4a08 ldr r2, [pc, #32] @ (8006c34 ) 8006c14: fba2 2303 umull r2, r3, r2, r3 8006c18: 095b lsrs r3, r3, #5 8006c1a: f003 0207 and.w r2, r3, #7 8006c1e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006c22: 681b ldr r3, [r3, #0] 8006c24: 4422 add r2, r4 8006c26: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } 8006c28: e106 b.n 8006e38 8006c2a: bf00 nop 8006c2c: 40011000 .word 0x40011000 8006c30: 40011400 .word 0x40011400 8006c34: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8006c38: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006c3c: 2200 movs r2, #0 8006c3e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 8006c42: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4 8006c46: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0 8006c4a: 4642 mov r2, r8 8006c4c: 464b mov r3, r9 8006c4e: 1891 adds r1, r2, r2 8006c50: 6239 str r1, [r7, #32] 8006c52: 415b adcs r3, r3 8006c54: 627b str r3, [r7, #36] @ 0x24 8006c56: e9d7 2308 ldrd r2, r3, [r7, #32] 8006c5a: 4641 mov r1, r8 8006c5c: 1854 adds r4, r2, r1 8006c5e: 4649 mov r1, r9 8006c60: eb43 0501 adc.w r5, r3, r1 8006c64: f04f 0200 mov.w r2, #0 8006c68: f04f 0300 mov.w r3, #0 8006c6c: 00eb lsls r3, r5, #3 8006c6e: ea43 7354 orr.w r3, r3, r4, lsr #29 8006c72: 00e2 lsls r2, r4, #3 8006c74: 4614 mov r4, r2 8006c76: 461d mov r5, r3 8006c78: 4643 mov r3, r8 8006c7a: 18e3 adds r3, r4, r3 8006c7c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8006c80: 464b mov r3, r9 8006c82: eb45 0303 adc.w r3, r5, r3 8006c86: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8006c8a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006c8e: 685b ldr r3, [r3, #4] 8006c90: 2200 movs r2, #0 8006c92: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8006c96: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8006c9a: f04f 0200 mov.w r2, #0 8006c9e: f04f 0300 mov.w r3, #0 8006ca2: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8006ca6: 4629 mov r1, r5 8006ca8: 008b lsls r3, r1, #2 8006caa: 4621 mov r1, r4 8006cac: ea43 7391 orr.w r3, r3, r1, lsr #30 8006cb0: 4621 mov r1, r4 8006cb2: 008a lsls r2, r1, #2 8006cb4: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98 8006cb8: f7f9 faa4 bl 8000204 <__aeabi_uldivmod> 8006cbc: 4602 mov r2, r0 8006cbe: 460b mov r3, r1 8006cc0: 4b60 ldr r3, [pc, #384] @ (8006e44 ) 8006cc2: fba3 2302 umull r2, r3, r3, r2 8006cc6: 095b lsrs r3, r3, #5 8006cc8: 011c lsls r4, r3, #4 8006cca: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006cce: 2200 movs r2, #0 8006cd0: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8006cd4: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8006cd8: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88 8006cdc: 4642 mov r2, r8 8006cde: 464b mov r3, r9 8006ce0: 1891 adds r1, r2, r2 8006ce2: 61b9 str r1, [r7, #24] 8006ce4: 415b adcs r3, r3 8006ce6: 61fb str r3, [r7, #28] 8006ce8: e9d7 2306 ldrd r2, r3, [r7, #24] 8006cec: 4641 mov r1, r8 8006cee: 1851 adds r1, r2, r1 8006cf0: 6139 str r1, [r7, #16] 8006cf2: 4649 mov r1, r9 8006cf4: 414b adcs r3, r1 8006cf6: 617b str r3, [r7, #20] 8006cf8: f04f 0200 mov.w r2, #0 8006cfc: f04f 0300 mov.w r3, #0 8006d00: e9d7 ab04 ldrd sl, fp, [r7, #16] 8006d04: 4659 mov r1, fp 8006d06: 00cb lsls r3, r1, #3 8006d08: 4651 mov r1, sl 8006d0a: ea43 7351 orr.w r3, r3, r1, lsr #29 8006d0e: 4651 mov r1, sl 8006d10: 00ca lsls r2, r1, #3 8006d12: 4610 mov r0, r2 8006d14: 4619 mov r1, r3 8006d16: 4603 mov r3, r0 8006d18: 4642 mov r2, r8 8006d1a: 189b adds r3, r3, r2 8006d1c: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8006d20: 464b mov r3, r9 8006d22: 460a mov r2, r1 8006d24: eb42 0303 adc.w r3, r2, r3 8006d28: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8006d2c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006d30: 685b ldr r3, [r3, #4] 8006d32: 2200 movs r2, #0 8006d34: 67bb str r3, [r7, #120] @ 0x78 8006d36: 67fa str r2, [r7, #124] @ 0x7c 8006d38: f04f 0200 mov.w r2, #0 8006d3c: f04f 0300 mov.w r3, #0 8006d40: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78 8006d44: 4649 mov r1, r9 8006d46: 008b lsls r3, r1, #2 8006d48: 4641 mov r1, r8 8006d4a: ea43 7391 orr.w r3, r3, r1, lsr #30 8006d4e: 4641 mov r1, r8 8006d50: 008a lsls r2, r1, #2 8006d52: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80 8006d56: f7f9 fa55 bl 8000204 <__aeabi_uldivmod> 8006d5a: 4602 mov r2, r0 8006d5c: 460b mov r3, r1 8006d5e: 4611 mov r1, r2 8006d60: 4b38 ldr r3, [pc, #224] @ (8006e44 ) 8006d62: fba3 2301 umull r2, r3, r3, r1 8006d66: 095b lsrs r3, r3, #5 8006d68: 2264 movs r2, #100 @ 0x64 8006d6a: fb02 f303 mul.w r3, r2, r3 8006d6e: 1acb subs r3, r1, r3 8006d70: 011b lsls r3, r3, #4 8006d72: 3332 adds r3, #50 @ 0x32 8006d74: 4a33 ldr r2, [pc, #204] @ (8006e44 ) 8006d76: fba2 2303 umull r2, r3, r2, r3 8006d7a: 095b lsrs r3, r3, #5 8006d7c: f003 03f0 and.w r3, r3, #240 @ 0xf0 8006d80: 441c add r4, r3 8006d82: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006d86: 2200 movs r2, #0 8006d88: 673b str r3, [r7, #112] @ 0x70 8006d8a: 677a str r2, [r7, #116] @ 0x74 8006d8c: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70 8006d90: 4642 mov r2, r8 8006d92: 464b mov r3, r9 8006d94: 1891 adds r1, r2, r2 8006d96: 60b9 str r1, [r7, #8] 8006d98: 415b adcs r3, r3 8006d9a: 60fb str r3, [r7, #12] 8006d9c: e9d7 2302 ldrd r2, r3, [r7, #8] 8006da0: 4641 mov r1, r8 8006da2: 1851 adds r1, r2, r1 8006da4: 6039 str r1, [r7, #0] 8006da6: 4649 mov r1, r9 8006da8: 414b adcs r3, r1 8006daa: 607b str r3, [r7, #4] 8006dac: f04f 0200 mov.w r2, #0 8006db0: f04f 0300 mov.w r3, #0 8006db4: e9d7 ab00 ldrd sl, fp, [r7] 8006db8: 4659 mov r1, fp 8006dba: 00cb lsls r3, r1, #3 8006dbc: 4651 mov r1, sl 8006dbe: ea43 7351 orr.w r3, r3, r1, lsr #29 8006dc2: 4651 mov r1, sl 8006dc4: 00ca lsls r2, r1, #3 8006dc6: 4610 mov r0, r2 8006dc8: 4619 mov r1, r3 8006dca: 4603 mov r3, r0 8006dcc: 4642 mov r2, r8 8006dce: 189b adds r3, r3, r2 8006dd0: 66bb str r3, [r7, #104] @ 0x68 8006dd2: 464b mov r3, r9 8006dd4: 460a mov r2, r1 8006dd6: eb42 0303 adc.w r3, r2, r3 8006dda: 66fb str r3, [r7, #108] @ 0x6c 8006ddc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006de0: 685b ldr r3, [r3, #4] 8006de2: 2200 movs r2, #0 8006de4: 663b str r3, [r7, #96] @ 0x60 8006de6: 667a str r2, [r7, #100] @ 0x64 8006de8: f04f 0200 mov.w r2, #0 8006dec: f04f 0300 mov.w r3, #0 8006df0: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60 8006df4: 4649 mov r1, r9 8006df6: 008b lsls r3, r1, #2 8006df8: 4641 mov r1, r8 8006dfa: ea43 7391 orr.w r3, r3, r1, lsr #30 8006dfe: 4641 mov r1, r8 8006e00: 008a lsls r2, r1, #2 8006e02: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68 8006e06: f7f9 f9fd bl 8000204 <__aeabi_uldivmod> 8006e0a: 4602 mov r2, r0 8006e0c: 460b mov r3, r1 8006e0e: 4b0d ldr r3, [pc, #52] @ (8006e44 ) 8006e10: fba3 1302 umull r1, r3, r3, r2 8006e14: 095b lsrs r3, r3, #5 8006e16: 2164 movs r1, #100 @ 0x64 8006e18: fb01 f303 mul.w r3, r1, r3 8006e1c: 1ad3 subs r3, r2, r3 8006e1e: 011b lsls r3, r3, #4 8006e20: 3332 adds r3, #50 @ 0x32 8006e22: 4a08 ldr r2, [pc, #32] @ (8006e44 ) 8006e24: fba2 2303 umull r2, r3, r2, r3 8006e28: 095b lsrs r3, r3, #5 8006e2a: f003 020f and.w r2, r3, #15 8006e2e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006e32: 681b ldr r3, [r3, #0] 8006e34: 4422 add r2, r4 8006e36: 609a str r2, [r3, #8] } 8006e38: bf00 nop 8006e3a: f507 7780 add.w r7, r7, #256 @ 0x100 8006e3e: 46bd mov sp, r7 8006e40: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8006e44: 51eb851f .word 0x51eb851f 08006e48 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8006e48: b084 sub sp, #16 8006e4a: b580 push {r7, lr} 8006e4c: b084 sub sp, #16 8006e4e: af00 add r7, sp, #0 8006e50: 6078 str r0, [r7, #4] 8006e52: f107 001c add.w r0, r7, #28 8006e56: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8006e5a: f897 3021 ldrb.w r3, [r7, #33] @ 0x21 8006e5e: 2b01 cmp r3, #1 8006e60: d123 bne.n 8006eaa { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8006e62: 687b ldr r3, [r7, #4] 8006e64: 6b9b ldr r3, [r3, #56] @ 0x38 8006e66: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8006e6a: 687b ldr r3, [r7, #4] 8006e6c: 639a str r2, [r3, #56] @ 0x38 /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); 8006e6e: 687b ldr r3, [r7, #4] 8006e70: 68db ldr r3, [r3, #12] 8006e72: f423 0384 bic.w r3, r3, #4325376 @ 0x420000 8006e76: f023 0340 bic.w r3, r3, #64 @ 0x40 8006e7a: 687a ldr r2, [r7, #4] 8006e7c: 60d3 str r3, [r2, #12] /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); 8006e7e: 687b ldr r3, [r7, #4] 8006e80: 68db ldr r3, [r3, #12] 8006e82: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 8006e86: 687b ldr r3, [r7, #4] 8006e88: 60da str r2, [r3, #12] if (cfg.use_external_vbus == 1U) 8006e8a: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8006e8e: 2b01 cmp r3, #1 8006e90: d105 bne.n 8006e9e { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; 8006e92: 687b ldr r3, [r7, #4] 8006e94: 68db ldr r3, [r3, #12] 8006e96: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 8006e9a: 687b ldr r3, [r7, #4] 8006e9c: 60da str r2, [r3, #12] } /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8006e9e: 6878 ldr r0, [r7, #4] 8006ea0: f001 fae2 bl 8008468 8006ea4: 4603 mov r3, r0 8006ea6: 73fb strb r3, [r7, #15] 8006ea8: e01b b.n 8006ee2 } else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 8006eaa: 687b ldr r3, [r7, #4] 8006eac: 68db ldr r3, [r3, #12] 8006eae: f043 0240 orr.w r2, r3, #64 @ 0x40 8006eb2: 687b ldr r3, [r7, #4] 8006eb4: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8006eb6: 6878 ldr r0, [r7, #4] 8006eb8: f001 fad6 bl 8008468 8006ebc: 4603 mov r3, r0 8006ebe: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 8006ec0: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 8006ec4: 2b00 cmp r3, #0 8006ec6: d106 bne.n 8006ed6 { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8006ec8: 687b ldr r3, [r7, #4] 8006eca: 6b9b ldr r3, [r3, #56] @ 0x38 8006ecc: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8006ed0: 687b ldr r3, [r7, #4] 8006ed2: 639a str r2, [r3, #56] @ 0x38 8006ed4: e005 b.n 8006ee2 } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8006ed6: 687b ldr r3, [r7, #4] 8006ed8: 6b9b ldr r3, [r3, #56] @ 0x38 8006eda: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8006ede: 687b ldr r3, [r7, #4] 8006ee0: 639a str r2, [r3, #56] @ 0x38 } } if (cfg.dma_enable == 1U) 8006ee2: 7fbb ldrb r3, [r7, #30] 8006ee4: 2b01 cmp r3, #1 8006ee6: d10b bne.n 8006f00 { USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; 8006ee8: 687b ldr r3, [r7, #4] 8006eea: 689b ldr r3, [r3, #8] 8006eec: f043 0206 orr.w r2, r3, #6 8006ef0: 687b ldr r3, [r7, #4] 8006ef2: 609a str r2, [r3, #8] USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; 8006ef4: 687b ldr r3, [r7, #4] 8006ef6: 689b ldr r3, [r3, #8] 8006ef8: f043 0220 orr.w r2, r3, #32 8006efc: 687b ldr r3, [r7, #4] 8006efe: 609a str r2, [r3, #8] } return ret; 8006f00: 7bfb ldrb r3, [r7, #15] } 8006f02: 4618 mov r0, r3 8006f04: 3710 adds r7, #16 8006f06: 46bd mov sp, r7 8006f08: e8bd 4080 ldmia.w sp!, {r7, lr} 8006f0c: b004 add sp, #16 8006f0e: 4770 bx lr 08006f10 : * @param hclk: AHB clock frequency * @retval USB turnaround time In PHY Clocks number */ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed) { 8006f10: b480 push {r7} 8006f12: b087 sub sp, #28 8006f14: af00 add r7, sp, #0 8006f16: 60f8 str r0, [r7, #12] 8006f18: 60b9 str r1, [r7, #8] 8006f1a: 4613 mov r3, r2 8006f1c: 71fb strb r3, [r7, #7] /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ if (speed == USBD_FS_SPEED) 8006f1e: 79fb ldrb r3, [r7, #7] 8006f20: 2b02 cmp r3, #2 8006f22: d165 bne.n 8006ff0 { if ((hclk >= 14200000U) && (hclk < 15000000U)) 8006f24: 68bb ldr r3, [r7, #8] 8006f26: 4a41 ldr r2, [pc, #260] @ (800702c ) 8006f28: 4293 cmp r3, r2 8006f2a: d906 bls.n 8006f3a 8006f2c: 68bb ldr r3, [r7, #8] 8006f2e: 4a40 ldr r2, [pc, #256] @ (8007030 ) 8006f30: 4293 cmp r3, r2 8006f32: d202 bcs.n 8006f3a { /* hclk Clock Range between 14.2-15 MHz */ UsbTrd = 0xFU; 8006f34: 230f movs r3, #15 8006f36: 617b str r3, [r7, #20] 8006f38: e062 b.n 8007000 } else if ((hclk >= 15000000U) && (hclk < 16000000U)) 8006f3a: 68bb ldr r3, [r7, #8] 8006f3c: 4a3c ldr r2, [pc, #240] @ (8007030 ) 8006f3e: 4293 cmp r3, r2 8006f40: d306 bcc.n 8006f50 8006f42: 68bb ldr r3, [r7, #8] 8006f44: 4a3b ldr r2, [pc, #236] @ (8007034 ) 8006f46: 4293 cmp r3, r2 8006f48: d202 bcs.n 8006f50 { /* hclk Clock Range between 15-16 MHz */ UsbTrd = 0xEU; 8006f4a: 230e movs r3, #14 8006f4c: 617b str r3, [r7, #20] 8006f4e: e057 b.n 8007000 } else if ((hclk >= 16000000U) && (hclk < 17200000U)) 8006f50: 68bb ldr r3, [r7, #8] 8006f52: 4a38 ldr r2, [pc, #224] @ (8007034 ) 8006f54: 4293 cmp r3, r2 8006f56: d306 bcc.n 8006f66 8006f58: 68bb ldr r3, [r7, #8] 8006f5a: 4a37 ldr r2, [pc, #220] @ (8007038 ) 8006f5c: 4293 cmp r3, r2 8006f5e: d202 bcs.n 8006f66 { /* hclk Clock Range between 16-17.2 MHz */ UsbTrd = 0xDU; 8006f60: 230d movs r3, #13 8006f62: 617b str r3, [r7, #20] 8006f64: e04c b.n 8007000 } else if ((hclk >= 17200000U) && (hclk < 18500000U)) 8006f66: 68bb ldr r3, [r7, #8] 8006f68: 4a33 ldr r2, [pc, #204] @ (8007038 ) 8006f6a: 4293 cmp r3, r2 8006f6c: d306 bcc.n 8006f7c 8006f6e: 68bb ldr r3, [r7, #8] 8006f70: 4a32 ldr r2, [pc, #200] @ (800703c ) 8006f72: 4293 cmp r3, r2 8006f74: d802 bhi.n 8006f7c { /* hclk Clock Range between 17.2-18.5 MHz */ UsbTrd = 0xCU; 8006f76: 230c movs r3, #12 8006f78: 617b str r3, [r7, #20] 8006f7a: e041 b.n 8007000 } else if ((hclk >= 18500000U) && (hclk < 20000000U)) 8006f7c: 68bb ldr r3, [r7, #8] 8006f7e: 4a2f ldr r2, [pc, #188] @ (800703c ) 8006f80: 4293 cmp r3, r2 8006f82: d906 bls.n 8006f92 8006f84: 68bb ldr r3, [r7, #8] 8006f86: 4a2e ldr r2, [pc, #184] @ (8007040 ) 8006f88: 4293 cmp r3, r2 8006f8a: d802 bhi.n 8006f92 { /* hclk Clock Range between 18.5-20 MHz */ UsbTrd = 0xBU; 8006f8c: 230b movs r3, #11 8006f8e: 617b str r3, [r7, #20] 8006f90: e036 b.n 8007000 } else if ((hclk >= 20000000U) && (hclk < 21800000U)) 8006f92: 68bb ldr r3, [r7, #8] 8006f94: 4a2a ldr r2, [pc, #168] @ (8007040 ) 8006f96: 4293 cmp r3, r2 8006f98: d906 bls.n 8006fa8 8006f9a: 68bb ldr r3, [r7, #8] 8006f9c: 4a29 ldr r2, [pc, #164] @ (8007044 ) 8006f9e: 4293 cmp r3, r2 8006fa0: d802 bhi.n 8006fa8 { /* hclk Clock Range between 20-21.8 MHz */ UsbTrd = 0xAU; 8006fa2: 230a movs r3, #10 8006fa4: 617b str r3, [r7, #20] 8006fa6: e02b b.n 8007000 } else if ((hclk >= 21800000U) && (hclk < 24000000U)) 8006fa8: 68bb ldr r3, [r7, #8] 8006faa: 4a26 ldr r2, [pc, #152] @ (8007044 ) 8006fac: 4293 cmp r3, r2 8006fae: d906 bls.n 8006fbe 8006fb0: 68bb ldr r3, [r7, #8] 8006fb2: 4a25 ldr r2, [pc, #148] @ (8007048 ) 8006fb4: 4293 cmp r3, r2 8006fb6: d202 bcs.n 8006fbe { /* hclk Clock Range between 21.8-24 MHz */ UsbTrd = 0x9U; 8006fb8: 2309 movs r3, #9 8006fba: 617b str r3, [r7, #20] 8006fbc: e020 b.n 8007000 } else if ((hclk >= 24000000U) && (hclk < 27700000U)) 8006fbe: 68bb ldr r3, [r7, #8] 8006fc0: 4a21 ldr r2, [pc, #132] @ (8007048 ) 8006fc2: 4293 cmp r3, r2 8006fc4: d306 bcc.n 8006fd4 8006fc6: 68bb ldr r3, [r7, #8] 8006fc8: 4a20 ldr r2, [pc, #128] @ (800704c ) 8006fca: 4293 cmp r3, r2 8006fcc: d802 bhi.n 8006fd4 { /* hclk Clock Range between 24-27.7 MHz */ UsbTrd = 0x8U; 8006fce: 2308 movs r3, #8 8006fd0: 617b str r3, [r7, #20] 8006fd2: e015 b.n 8007000 } else if ((hclk >= 27700000U) && (hclk < 32000000U)) 8006fd4: 68bb ldr r3, [r7, #8] 8006fd6: 4a1d ldr r2, [pc, #116] @ (800704c ) 8006fd8: 4293 cmp r3, r2 8006fda: d906 bls.n 8006fea 8006fdc: 68bb ldr r3, [r7, #8] 8006fde: 4a1c ldr r2, [pc, #112] @ (8007050 ) 8006fe0: 4293 cmp r3, r2 8006fe2: d202 bcs.n 8006fea { /* hclk Clock Range between 27.7-32 MHz */ UsbTrd = 0x7U; 8006fe4: 2307 movs r3, #7 8006fe6: 617b str r3, [r7, #20] 8006fe8: e00a b.n 8007000 } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ UsbTrd = 0x6U; 8006fea: 2306 movs r3, #6 8006fec: 617b str r3, [r7, #20] 8006fee: e007 b.n 8007000 } } else if (speed == USBD_HS_SPEED) 8006ff0: 79fb ldrb r3, [r7, #7] 8006ff2: 2b00 cmp r3, #0 8006ff4: d102 bne.n 8006ffc { UsbTrd = USBD_HS_TRDT_VALUE; 8006ff6: 2309 movs r3, #9 8006ff8: 617b str r3, [r7, #20] 8006ffa: e001 b.n 8007000 } else { UsbTrd = USBD_DEFAULT_TRDT_VALUE; 8006ffc: 2309 movs r3, #9 8006ffe: 617b str r3, [r7, #20] } USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; 8007000: 68fb ldr r3, [r7, #12] 8007002: 68db ldr r3, [r3, #12] 8007004: f423 5270 bic.w r2, r3, #15360 @ 0x3c00 8007008: 68fb ldr r3, [r7, #12] 800700a: 60da str r2, [r3, #12] USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); 800700c: 68fb ldr r3, [r7, #12] 800700e: 68da ldr r2, [r3, #12] 8007010: 697b ldr r3, [r7, #20] 8007012: 029b lsls r3, r3, #10 8007014: f403 5370 and.w r3, r3, #15360 @ 0x3c00 8007018: 431a orrs r2, r3 800701a: 68fb ldr r3, [r7, #12] 800701c: 60da str r2, [r3, #12] return HAL_OK; 800701e: 2300 movs r3, #0 } 8007020: 4618 mov r0, r3 8007022: 371c adds r7, #28 8007024: 46bd mov sp, r7 8007026: f85d 7b04 ldr.w r7, [sp], #4 800702a: 4770 bx lr 800702c: 00d8acbf .word 0x00d8acbf 8007030: 00e4e1c0 .word 0x00e4e1c0 8007034: 00f42400 .word 0x00f42400 8007038: 01067380 .word 0x01067380 800703c: 011a499f .word 0x011a499f 8007040: 01312cff .word 0x01312cff 8007044: 014ca43f .word 0x014ca43f 8007048: 016e3600 .word 0x016e3600 800704c: 01a6ab1f .word 0x01a6ab1f 8007050: 01e84800 .word 0x01e84800 08007054 : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8007054: b480 push {r7} 8007056: b083 sub sp, #12 8007058: af00 add r7, sp, #0 800705a: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 800705c: 687b ldr r3, [r7, #4] 800705e: 689b ldr r3, [r3, #8] 8007060: f043 0201 orr.w r2, r3, #1 8007064: 687b ldr r3, [r7, #4] 8007066: 609a str r2, [r3, #8] return HAL_OK; 8007068: 2300 movs r3, #0 } 800706a: 4618 mov r0, r3 800706c: 370c adds r7, #12 800706e: 46bd mov sp, r7 8007070: f85d 7b04 ldr.w r7, [sp], #4 8007074: 4770 bx lr 08007076 : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8007076: b480 push {r7} 8007078: b083 sub sp, #12 800707a: af00 add r7, sp, #0 800707c: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 800707e: 687b ldr r3, [r7, #4] 8007080: 689b ldr r3, [r3, #8] 8007082: f023 0201 bic.w r2, r3, #1 8007086: 687b ldr r3, [r7, #4] 8007088: 609a str r2, [r3, #8] return HAL_OK; 800708a: 2300 movs r3, #0 } 800708c: 4618 mov r0, r3 800708e: 370c adds r7, #12 8007090: 46bd mov sp, r7 8007092: f85d 7b04 ldr.w r7, [sp], #4 8007096: 4770 bx lr 08007098 : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { 8007098: b580 push {r7, lr} 800709a: b084 sub sp, #16 800709c: af00 add r7, sp, #0 800709e: 6078 str r0, [r7, #4] 80070a0: 460b mov r3, r1 80070a2: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 80070a4: 2300 movs r3, #0 80070a6: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 80070a8: 687b ldr r3, [r7, #4] 80070aa: 68db ldr r3, [r3, #12] 80070ac: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000 80070b0: 687b ldr r3, [r7, #4] 80070b2: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 80070b4: 78fb ldrb r3, [r7, #3] 80070b6: 2b01 cmp r3, #1 80070b8: d115 bne.n 80070e6 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 80070ba: 687b ldr r3, [r7, #4] 80070bc: 68db ldr r3, [r3, #12] 80070be: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 80070c2: 687b ldr r3, [r7, #4] 80070c4: 60da str r2, [r3, #12] do { HAL_Delay(10U); 80070c6: 200a movs r0, #10 80070c8: f7fa fcba bl 8001a40 ms += 10U; 80070cc: 68fb ldr r3, [r7, #12] 80070ce: 330a adds r3, #10 80070d0: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 80070d2: 6878 ldr r0, [r7, #4] 80070d4: f001 f939 bl 800834a 80070d8: 4603 mov r3, r0 80070da: 2b01 cmp r3, #1 80070dc: d01e beq.n 800711c 80070de: 68fb ldr r3, [r7, #12] 80070e0: 2bc7 cmp r3, #199 @ 0xc7 80070e2: d9f0 bls.n 80070c6 80070e4: e01a b.n 800711c } else if (mode == USB_DEVICE_MODE) 80070e6: 78fb ldrb r3, [r7, #3] 80070e8: 2b00 cmp r3, #0 80070ea: d115 bne.n 8007118 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 80070ec: 687b ldr r3, [r7, #4] 80070ee: 68db ldr r3, [r3, #12] 80070f0: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000 80070f4: 687b ldr r3, [r7, #4] 80070f6: 60da str r2, [r3, #12] do { HAL_Delay(10U); 80070f8: 200a movs r0, #10 80070fa: f7fa fca1 bl 8001a40 ms += 10U; 80070fe: 68fb ldr r3, [r7, #12] 8007100: 330a adds r3, #10 8007102: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8007104: 6878 ldr r0, [r7, #4] 8007106: f001 f920 bl 800834a 800710a: 4603 mov r3, r0 800710c: 2b00 cmp r3, #0 800710e: d005 beq.n 800711c 8007110: 68fb ldr r3, [r7, #12] 8007112: 2bc7 cmp r3, #199 @ 0xc7 8007114: d9f0 bls.n 80070f8 8007116: e001 b.n 800711c } else { return HAL_ERROR; 8007118: 2301 movs r3, #1 800711a: e005 b.n 8007128 } if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) 800711c: 68fb ldr r3, [r7, #12] 800711e: 2bc8 cmp r3, #200 @ 0xc8 8007120: d101 bne.n 8007126 { return HAL_ERROR; 8007122: 2301 movs r3, #1 8007124: e000 b.n 8007128 } return HAL_OK; 8007126: 2300 movs r3, #0 } 8007128: 4618 mov r0, r3 800712a: 3710 adds r7, #16 800712c: 46bd mov sp, r7 800712e: bd80 pop {r7, pc} 08007130 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8007130: b084 sub sp, #16 8007132: b580 push {r7, lr} 8007134: b086 sub sp, #24 8007136: af00 add r7, sp, #0 8007138: 6078 str r0, [r7, #4] 800713a: f107 0024 add.w r0, r7, #36 @ 0x24 800713e: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 8007142: 2300 movs r3, #0 8007144: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8007146: 687b ldr r3, [r7, #4] 8007148: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 800714a: 2300 movs r3, #0 800714c: 613b str r3, [r7, #16] 800714e: e009 b.n 8007164 { USBx->DIEPTXF[i] = 0U; 8007150: 687a ldr r2, [r7, #4] 8007152: 693b ldr r3, [r7, #16] 8007154: 3340 adds r3, #64 @ 0x40 8007156: 009b lsls r3, r3, #2 8007158: 4413 add r3, r2 800715a: 2200 movs r2, #0 800715c: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 800715e: 693b ldr r3, [r7, #16] 8007160: 3301 adds r3, #1 8007162: 613b str r3, [r7, #16] 8007164: 693b ldr r3, [r7, #16] 8007166: 2b0e cmp r3, #14 8007168: d9f2 bls.n 8007150 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 800716a: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800716e: 2b00 cmp r3, #0 8007170: d11c bne.n 80071ac { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8007172: 68fb ldr r3, [r7, #12] 8007174: f503 6300 add.w r3, r3, #2048 @ 0x800 8007178: 685b ldr r3, [r3, #4] 800717a: 68fa ldr r2, [r7, #12] 800717c: f502 6200 add.w r2, r2, #2048 @ 0x800 8007180: f043 0302 orr.w r3, r3, #2 8007184: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 8007186: 687b ldr r3, [r7, #4] 8007188: 6b9b ldr r3, [r3, #56] @ 0x38 800718a: f423 1200 bic.w r2, r3, #2097152 @ 0x200000 800718e: 687b ldr r3, [r7, #4] 8007190: 639a str r2, [r3, #56] @ 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 8007192: 687b ldr r3, [r7, #4] 8007194: 681b ldr r3, [r3, #0] 8007196: f043 0240 orr.w r2, r3, #64 @ 0x40 800719a: 687b ldr r3, [r7, #4] 800719c: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 800719e: 687b ldr r3, [r7, #4] 80071a0: 681b ldr r3, [r3, #0] 80071a2: f043 0280 orr.w r2, r3, #128 @ 0x80 80071a6: 687b ldr r3, [r7, #4] 80071a8: 601a str r2, [r3, #0] 80071aa: e005 b.n 80071b8 } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 80071ac: 687b ldr r3, [r7, #4] 80071ae: 6b9b ldr r3, [r3, #56] @ 0x38 80071b0: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 80071b4: 687b ldr r3, [r7, #4] 80071b6: 639a str r2, [r3, #56] @ 0x38 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 80071b8: 68fb ldr r3, [r7, #12] 80071ba: f503 6360 add.w r3, r3, #3584 @ 0xe00 80071be: 461a mov r2, r3 80071c0: 2300 movs r3, #0 80071c2: 6013 str r3, [r2, #0] if (cfg.phy_itface == USB_OTG_ULPI_PHY) 80071c4: f897 3029 ldrb.w r3, [r7, #41] @ 0x29 80071c8: 2b01 cmp r3, #1 80071ca: d10d bne.n 80071e8 { if (cfg.speed == USBD_HS_SPEED) 80071cc: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 80071d0: 2b00 cmp r3, #0 80071d2: d104 bne.n 80071de { /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); 80071d4: 2100 movs r1, #0 80071d6: 6878 ldr r0, [r7, #4] 80071d8: f000 f968 bl 80074ac 80071dc: e008 b.n 80071f0 } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); 80071de: 2101 movs r1, #1 80071e0: 6878 ldr r0, [r7, #4] 80071e2: f000 f963 bl 80074ac 80071e6: e003 b.n 80071f0 } } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 80071e8: 2103 movs r1, #3 80071ea: 6878 ldr r0, [r7, #4] 80071ec: f000 f95e bl 80074ac } /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 80071f0: 2110 movs r1, #16 80071f2: 6878 ldr r0, [r7, #4] 80071f4: f000 f8fa bl 80073ec 80071f8: 4603 mov r3, r0 80071fa: 2b00 cmp r3, #0 80071fc: d001 beq.n 8007202 { ret = HAL_ERROR; 80071fe: 2301 movs r3, #1 8007200: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 8007202: 6878 ldr r0, [r7, #4] 8007204: f000 f924 bl 8007450 8007208: 4603 mov r3, r0 800720a: 2b00 cmp r3, #0 800720c: d001 beq.n 8007212 { ret = HAL_ERROR; 800720e: 2301 movs r3, #1 8007210: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 8007212: 68fb ldr r3, [r7, #12] 8007214: f503 6300 add.w r3, r3, #2048 @ 0x800 8007218: 461a mov r2, r3 800721a: 2300 movs r3, #0 800721c: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 800721e: 68fb ldr r3, [r7, #12] 8007220: f503 6300 add.w r3, r3, #2048 @ 0x800 8007224: 461a mov r2, r3 8007226: 2300 movs r3, #0 8007228: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 800722a: 68fb ldr r3, [r7, #12] 800722c: f503 6300 add.w r3, r3, #2048 @ 0x800 8007230: 461a mov r2, r3 8007232: 2300 movs r3, #0 8007234: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 8007236: 2300 movs r3, #0 8007238: 613b str r3, [r7, #16] 800723a: e043 b.n 80072c4 { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 800723c: 693b ldr r3, [r7, #16] 800723e: 015a lsls r2, r3, #5 8007240: 68fb ldr r3, [r7, #12] 8007242: 4413 add r3, r2 8007244: f503 6310 add.w r3, r3, #2304 @ 0x900 8007248: 681b ldr r3, [r3, #0] 800724a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800724e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007252: d118 bne.n 8007286 { if (i == 0U) 8007254: 693b ldr r3, [r7, #16] 8007256: 2b00 cmp r3, #0 8007258: d10a bne.n 8007270 { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 800725a: 693b ldr r3, [r7, #16] 800725c: 015a lsls r2, r3, #5 800725e: 68fb ldr r3, [r7, #12] 8007260: 4413 add r3, r2 8007262: f503 6310 add.w r3, r3, #2304 @ 0x900 8007266: 461a mov r2, r3 8007268: f04f 6300 mov.w r3, #134217728 @ 0x8000000 800726c: 6013 str r3, [r2, #0] 800726e: e013 b.n 8007298 } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 8007270: 693b ldr r3, [r7, #16] 8007272: 015a lsls r2, r3, #5 8007274: 68fb ldr r3, [r7, #12] 8007276: 4413 add r3, r2 8007278: f503 6310 add.w r3, r3, #2304 @ 0x900 800727c: 461a mov r2, r3 800727e: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 8007282: 6013 str r3, [r2, #0] 8007284: e008 b.n 8007298 } } else { USBx_INEP(i)->DIEPCTL = 0U; 8007286: 693b ldr r3, [r7, #16] 8007288: 015a lsls r2, r3, #5 800728a: 68fb ldr r3, [r7, #12] 800728c: 4413 add r3, r2 800728e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007292: 461a mov r2, r3 8007294: 2300 movs r3, #0 8007296: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 8007298: 693b ldr r3, [r7, #16] 800729a: 015a lsls r2, r3, #5 800729c: 68fb ldr r3, [r7, #12] 800729e: 4413 add r3, r2 80072a0: f503 6310 add.w r3, r3, #2304 @ 0x900 80072a4: 461a mov r2, r3 80072a6: 2300 movs r3, #0 80072a8: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 80072aa: 693b ldr r3, [r7, #16] 80072ac: 015a lsls r2, r3, #5 80072ae: 68fb ldr r3, [r7, #12] 80072b0: 4413 add r3, r2 80072b2: f503 6310 add.w r3, r3, #2304 @ 0x900 80072b6: 461a mov r2, r3 80072b8: f64f 337f movw r3, #64383 @ 0xfb7f 80072bc: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 80072be: 693b ldr r3, [r7, #16] 80072c0: 3301 adds r3, #1 80072c2: 613b str r3, [r7, #16] 80072c4: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 80072c8: 461a mov r2, r3 80072ca: 693b ldr r3, [r7, #16] 80072cc: 4293 cmp r3, r2 80072ce: d3b5 bcc.n 800723c } for (i = 0U; i < cfg.dev_endpoints; i++) 80072d0: 2300 movs r3, #0 80072d2: 613b str r3, [r7, #16] 80072d4: e043 b.n 800735e { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80072d6: 693b ldr r3, [r7, #16] 80072d8: 015a lsls r2, r3, #5 80072da: 68fb ldr r3, [r7, #12] 80072dc: 4413 add r3, r2 80072de: f503 6330 add.w r3, r3, #2816 @ 0xb00 80072e2: 681b ldr r3, [r3, #0] 80072e4: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80072e8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80072ec: d118 bne.n 8007320 { if (i == 0U) 80072ee: 693b ldr r3, [r7, #16] 80072f0: 2b00 cmp r3, #0 80072f2: d10a bne.n 800730a { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 80072f4: 693b ldr r3, [r7, #16] 80072f6: 015a lsls r2, r3, #5 80072f8: 68fb ldr r3, [r7, #12] 80072fa: 4413 add r3, r2 80072fc: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007300: 461a mov r2, r3 8007302: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8007306: 6013 str r3, [r2, #0] 8007308: e013 b.n 8007332 } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 800730a: 693b ldr r3, [r7, #16] 800730c: 015a lsls r2, r3, #5 800730e: 68fb ldr r3, [r7, #12] 8007310: 4413 add r3, r2 8007312: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007316: 461a mov r2, r3 8007318: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 800731c: 6013 str r3, [r2, #0] 800731e: e008 b.n 8007332 } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 8007320: 693b ldr r3, [r7, #16] 8007322: 015a lsls r2, r3, #5 8007324: 68fb ldr r3, [r7, #12] 8007326: 4413 add r3, r2 8007328: f503 6330 add.w r3, r3, #2816 @ 0xb00 800732c: 461a mov r2, r3 800732e: 2300 movs r3, #0 8007330: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 8007332: 693b ldr r3, [r7, #16] 8007334: 015a lsls r2, r3, #5 8007336: 68fb ldr r3, [r7, #12] 8007338: 4413 add r3, r2 800733a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800733e: 461a mov r2, r3 8007340: 2300 movs r3, #0 8007342: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8007344: 693b ldr r3, [r7, #16] 8007346: 015a lsls r2, r3, #5 8007348: 68fb ldr r3, [r7, #12] 800734a: 4413 add r3, r2 800734c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007350: 461a mov r2, r3 8007352: f64f 337f movw r3, #64383 @ 0xfb7f 8007356: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8007358: 693b ldr r3, [r7, #16] 800735a: 3301 adds r3, #1 800735c: 613b str r3, [r7, #16] 800735e: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8007362: 461a mov r2, r3 8007364: 693b ldr r3, [r7, #16] 8007366: 4293 cmp r3, r2 8007368: d3b5 bcc.n 80072d6 } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 800736a: 68fb ldr r3, [r7, #12] 800736c: f503 6300 add.w r3, r3, #2048 @ 0x800 8007370: 691b ldr r3, [r3, #16] 8007372: 68fa ldr r2, [r7, #12] 8007374: f502 6200 add.w r2, r2, #2048 @ 0x800 8007378: f423 7380 bic.w r3, r3, #256 @ 0x100 800737c: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 800737e: 687b ldr r3, [r7, #4] 8007380: 2200 movs r2, #0 8007382: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 8007384: 687b ldr r3, [r7, #4] 8007386: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000 800738a: 615a str r2, [r3, #20] /* Enable the common interrupts */ if (cfg.dma_enable == 0U) 800738c: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8007390: 2b00 cmp r3, #0 8007392: d105 bne.n 80073a0 { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 8007394: 687b ldr r3, [r7, #4] 8007396: 699b ldr r3, [r3, #24] 8007398: f043 0210 orr.w r2, r3, #16 800739c: 687b ldr r3, [r7, #4] 800739e: 619a str r2, [r3, #24] } /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 80073a0: 687b ldr r3, [r7, #4] 80073a2: 699a ldr r2, [r3, #24] 80073a4: 4b10 ldr r3, [pc, #64] @ (80073e8 ) 80073a6: 4313 orrs r3, r2 80073a8: 687a ldr r2, [r7, #4] 80073aa: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 80073ac: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 80073b0: 2b00 cmp r3, #0 80073b2: d005 beq.n 80073c0 { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 80073b4: 687b ldr r3, [r7, #4] 80073b6: 699b ldr r3, [r3, #24] 80073b8: f043 0208 orr.w r2, r3, #8 80073bc: 687b ldr r3, [r7, #4] 80073be: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 80073c0: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 80073c4: 2b01 cmp r3, #1 80073c6: d107 bne.n 80073d8 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 80073c8: 687b ldr r3, [r7, #4] 80073ca: 699b ldr r3, [r3, #24] 80073cc: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80073d0: f043 0304 orr.w r3, r3, #4 80073d4: 687a ldr r2, [r7, #4] 80073d6: 6193 str r3, [r2, #24] } return ret; 80073d8: 7dfb ldrb r3, [r7, #23] } 80073da: 4618 mov r0, r3 80073dc: 3718 adds r7, #24 80073de: 46bd mov sp, r7 80073e0: e8bd 4080 ldmia.w sp!, {r7, lr} 80073e4: b004 add sp, #16 80073e6: 4770 bx lr 80073e8: 803c3800 .word 0x803c3800 080073ec : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 80073ec: b480 push {r7} 80073ee: b085 sub sp, #20 80073f0: af00 add r7, sp, #0 80073f2: 6078 str r0, [r7, #4] 80073f4: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 80073f6: 2300 movs r3, #0 80073f8: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 80073fa: 68fb ldr r3, [r7, #12] 80073fc: 3301 adds r3, #1 80073fe: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007400: 68fb ldr r3, [r7, #12] 8007402: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007406: d901 bls.n 800740c { return HAL_TIMEOUT; 8007408: 2303 movs r3, #3 800740a: e01b b.n 8007444 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 800740c: 687b ldr r3, [r7, #4] 800740e: 691b ldr r3, [r3, #16] 8007410: 2b00 cmp r3, #0 8007412: daf2 bge.n 80073fa /* Flush TX Fifo */ count = 0U; 8007414: 2300 movs r3, #0 8007416: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 8007418: 683b ldr r3, [r7, #0] 800741a: 019b lsls r3, r3, #6 800741c: f043 0220 orr.w r2, r3, #32 8007420: 687b ldr r3, [r7, #4] 8007422: 611a str r2, [r3, #16] do { count++; 8007424: 68fb ldr r3, [r7, #12] 8007426: 3301 adds r3, #1 8007428: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800742a: 68fb ldr r3, [r7, #12] 800742c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007430: d901 bls.n 8007436 { return HAL_TIMEOUT; 8007432: 2303 movs r3, #3 8007434: e006 b.n 8007444 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 8007436: 687b ldr r3, [r7, #4] 8007438: 691b ldr r3, [r3, #16] 800743a: f003 0320 and.w r3, r3, #32 800743e: 2b20 cmp r3, #32 8007440: d0f0 beq.n 8007424 return HAL_OK; 8007442: 2300 movs r3, #0 } 8007444: 4618 mov r0, r3 8007446: 3714 adds r7, #20 8007448: 46bd mov sp, r7 800744a: f85d 7b04 ldr.w r7, [sp], #4 800744e: 4770 bx lr 08007450 : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 8007450: b480 push {r7} 8007452: b085 sub sp, #20 8007454: af00 add r7, sp, #0 8007456: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8007458: 2300 movs r3, #0 800745a: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 800745c: 68fb ldr r3, [r7, #12] 800745e: 3301 adds r3, #1 8007460: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007462: 68fb ldr r3, [r7, #12] 8007464: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007468: d901 bls.n 800746e { return HAL_TIMEOUT; 800746a: 2303 movs r3, #3 800746c: e018 b.n 80074a0 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 800746e: 687b ldr r3, [r7, #4] 8007470: 691b ldr r3, [r3, #16] 8007472: 2b00 cmp r3, #0 8007474: daf2 bge.n 800745c /* Flush RX Fifo */ count = 0U; 8007476: 2300 movs r3, #0 8007478: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 800747a: 687b ldr r3, [r7, #4] 800747c: 2210 movs r2, #16 800747e: 611a str r2, [r3, #16] do { count++; 8007480: 68fb ldr r3, [r7, #12] 8007482: 3301 adds r3, #1 8007484: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007486: 68fb ldr r3, [r7, #12] 8007488: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 800748c: d901 bls.n 8007492 { return HAL_TIMEOUT; 800748e: 2303 movs r3, #3 8007490: e006 b.n 80074a0 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 8007492: 687b ldr r3, [r7, #4] 8007494: 691b ldr r3, [r3, #16] 8007496: f003 0310 and.w r3, r3, #16 800749a: 2b10 cmp r3, #16 800749c: d0f0 beq.n 8007480 return HAL_OK; 800749e: 2300 movs r3, #0 } 80074a0: 4618 mov r0, r3 80074a2: 3714 adds r7, #20 80074a4: 46bd mov sp, r7 80074a6: f85d 7b04 ldr.w r7, [sp], #4 80074aa: 4770 bx lr 080074ac : * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 80074ac: b480 push {r7} 80074ae: b085 sub sp, #20 80074b0: af00 add r7, sp, #0 80074b2: 6078 str r0, [r7, #4] 80074b4: 460b mov r3, r1 80074b6: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80074b8: 687b ldr r3, [r7, #4] 80074ba: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 80074bc: 68fb ldr r3, [r7, #12] 80074be: f503 6300 add.w r3, r3, #2048 @ 0x800 80074c2: 681a ldr r2, [r3, #0] 80074c4: 78fb ldrb r3, [r7, #3] 80074c6: 68f9 ldr r1, [r7, #12] 80074c8: f501 6100 add.w r1, r1, #2048 @ 0x800 80074cc: 4313 orrs r3, r2 80074ce: 600b str r3, [r1, #0] return HAL_OK; 80074d0: 2300 movs r3, #0 } 80074d2: 4618 mov r0, r3 80074d4: 3714 adds r7, #20 80074d6: 46bd mov sp, r7 80074d8: f85d 7b04 ldr.w r7, [sp], #4 80074dc: 4770 bx lr 080074de : * This parameter can be one of these values: * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { 80074de: b480 push {r7} 80074e0: b087 sub sp, #28 80074e2: af00 add r7, sp, #0 80074e4: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80074e6: 687b ldr r3, [r7, #4] 80074e8: 613b str r3, [r7, #16] uint8_t speed; uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; 80074ea: 693b ldr r3, [r7, #16] 80074ec: f503 6300 add.w r3, r3, #2048 @ 0x800 80074f0: 689b ldr r3, [r3, #8] 80074f2: f003 0306 and.w r3, r3, #6 80074f6: 60fb str r3, [r7, #12] if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 80074f8: 68fb ldr r3, [r7, #12] 80074fa: 2b00 cmp r3, #0 80074fc: d102 bne.n 8007504 { speed = USBD_HS_SPEED; 80074fe: 2300 movs r3, #0 8007500: 75fb strb r3, [r7, #23] 8007502: e00a b.n 800751a } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || 8007504: 68fb ldr r3, [r7, #12] 8007506: 2b02 cmp r3, #2 8007508: d002 beq.n 8007510 800750a: 68fb ldr r3, [r7, #12] 800750c: 2b06 cmp r3, #6 800750e: d102 bne.n 8007516 (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USBD_FS_SPEED; 8007510: 2302 movs r3, #2 8007512: 75fb strb r3, [r7, #23] 8007514: e001 b.n 800751a } else { speed = 0xFU; 8007516: 230f movs r3, #15 8007518: 75fb strb r3, [r7, #23] } return speed; 800751a: 7dfb ldrb r3, [r7, #23] } 800751c: 4618 mov r0, r3 800751e: 371c adds r7, #28 8007520: 46bd mov sp, r7 8007522: f85d 7b04 ldr.w r7, [sp], #4 8007526: 4770 bx lr 08007528 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007528: b480 push {r7} 800752a: b085 sub sp, #20 800752c: af00 add r7, sp, #0 800752e: 6078 str r0, [r7, #4] 8007530: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8007532: 687b ldr r3, [r7, #4] 8007534: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007536: 683b ldr r3, [r7, #0] 8007538: 781b ldrb r3, [r3, #0] 800753a: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 800753c: 683b ldr r3, [r7, #0] 800753e: 785b ldrb r3, [r3, #1] 8007540: 2b01 cmp r3, #1 8007542: d13a bne.n 80075ba { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); 8007544: 68fb ldr r3, [r7, #12] 8007546: f503 6300 add.w r3, r3, #2048 @ 0x800 800754a: 69da ldr r2, [r3, #28] 800754c: 683b ldr r3, [r7, #0] 800754e: 781b ldrb r3, [r3, #0] 8007550: f003 030f and.w r3, r3, #15 8007554: 2101 movs r1, #1 8007556: fa01 f303 lsl.w r3, r1, r3 800755a: b29b uxth r3, r3 800755c: 68f9 ldr r1, [r7, #12] 800755e: f501 6100 add.w r1, r1, #2048 @ 0x800 8007562: 4313 orrs r3, r2 8007564: 61cb str r3, [r1, #28] if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) 8007566: 68bb ldr r3, [r7, #8] 8007568: 015a lsls r2, r3, #5 800756a: 68fb ldr r3, [r7, #12] 800756c: 4413 add r3, r2 800756e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007572: 681b ldr r3, [r3, #0] 8007574: f403 4300 and.w r3, r3, #32768 @ 0x8000 8007578: 2b00 cmp r3, #0 800757a: d155 bne.n 8007628 { USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 800757c: 68bb ldr r3, [r7, #8] 800757e: 015a lsls r2, r3, #5 8007580: 68fb ldr r3, [r7, #12] 8007582: 4413 add r3, r2 8007584: f503 6310 add.w r3, r3, #2304 @ 0x900 8007588: 681a ldr r2, [r3, #0] 800758a: 683b ldr r3, [r7, #0] 800758c: 689b ldr r3, [r3, #8] 800758e: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | (epnum << 22) | 8007592: 683b ldr r3, [r7, #0] 8007594: 791b ldrb r3, [r3, #4] 8007596: 049b lsls r3, r3, #18 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8007598: 4319 orrs r1, r3 ((uint32_t)ep->type << 18) | (epnum << 22) | 800759a: 68bb ldr r3, [r7, #8] 800759c: 059b lsls r3, r3, #22 800759e: 430b orrs r3, r1 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 80075a0: 4313 orrs r3, r2 80075a2: 68ba ldr r2, [r7, #8] 80075a4: 0151 lsls r1, r2, #5 80075a6: 68fa ldr r2, [r7, #12] 80075a8: 440a add r2, r1 80075aa: f502 6210 add.w r2, r2, #2304 @ 0x900 80075ae: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80075b2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80075b6: 6013 str r3, [r2, #0] 80075b8: e036 b.n 8007628 USB_OTG_DIEPCTL_USBAEP; } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); 80075ba: 68fb ldr r3, [r7, #12] 80075bc: f503 6300 add.w r3, r3, #2048 @ 0x800 80075c0: 69da ldr r2, [r3, #28] 80075c2: 683b ldr r3, [r7, #0] 80075c4: 781b ldrb r3, [r3, #0] 80075c6: f003 030f and.w r3, r3, #15 80075ca: 2101 movs r1, #1 80075cc: fa01 f303 lsl.w r3, r1, r3 80075d0: 041b lsls r3, r3, #16 80075d2: 68f9 ldr r1, [r7, #12] 80075d4: f501 6100 add.w r1, r1, #2048 @ 0x800 80075d8: 4313 orrs r3, r2 80075da: 61cb str r3, [r1, #28] if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) 80075dc: 68bb ldr r3, [r7, #8] 80075de: 015a lsls r2, r3, #5 80075e0: 68fb ldr r3, [r7, #12] 80075e2: 4413 add r3, r2 80075e4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80075e8: 681b ldr r3, [r3, #0] 80075ea: f403 4300 and.w r3, r3, #32768 @ 0x8000 80075ee: 2b00 cmp r3, #0 80075f0: d11a bne.n 8007628 { USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 80075f2: 68bb ldr r3, [r7, #8] 80075f4: 015a lsls r2, r3, #5 80075f6: 68fb ldr r3, [r7, #12] 80075f8: 4413 add r3, r2 80075fa: f503 6330 add.w r3, r3, #2816 @ 0xb00 80075fe: 681a ldr r2, [r3, #0] 8007600: 683b ldr r3, [r7, #0] 8007602: 689b ldr r3, [r3, #8] 8007604: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | 8007608: 683b ldr r3, [r7, #0] 800760a: 791b ldrb r3, [r3, #4] 800760c: 049b lsls r3, r3, #18 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 800760e: 430b orrs r3, r1 8007610: 4313 orrs r3, r2 8007612: 68ba ldr r2, [r7, #8] 8007614: 0151 lsls r1, r2, #5 8007616: 68fa ldr r2, [r7, #12] 8007618: 440a add r2, r1 800761a: f502 6230 add.w r2, r2, #2816 @ 0xb00 800761e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007622: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8007626: 6013 str r3, [r2, #0] USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; 8007628: 2300 movs r3, #0 } 800762a: 4618 mov r0, r3 800762c: 3714 adds r7, #20 800762e: 46bd mov sp, r7 8007630: f85d 7b04 ldr.w r7, [sp], #4 8007634: 4770 bx lr ... 08007638 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007638: b480 push {r7} 800763a: b085 sub sp, #20 800763c: af00 add r7, sp, #0 800763e: 6078 str r0, [r7, #4] 8007640: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8007642: 687b ldr r3, [r7, #4] 8007644: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007646: 683b ldr r3, [r7, #0] 8007648: 781b ldrb r3, [r3, #0] 800764a: 60bb str r3, [r7, #8] /* Read DEPCTLn register */ if (ep->is_in == 1U) 800764c: 683b ldr r3, [r7, #0] 800764e: 785b ldrb r3, [r3, #1] 8007650: 2b01 cmp r3, #1 8007652: d161 bne.n 8007718 { if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007654: 68bb ldr r3, [r7, #8] 8007656: 015a lsls r2, r3, #5 8007658: 68fb ldr r3, [r7, #12] 800765a: 4413 add r3, r2 800765c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007660: 681b ldr r3, [r3, #0] 8007662: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007666: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800766a: d11f bne.n 80076ac { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 800766c: 68bb ldr r3, [r7, #8] 800766e: 015a lsls r2, r3, #5 8007670: 68fb ldr r3, [r7, #12] 8007672: 4413 add r3, r2 8007674: f503 6310 add.w r3, r3, #2304 @ 0x900 8007678: 681b ldr r3, [r3, #0] 800767a: 68ba ldr r2, [r7, #8] 800767c: 0151 lsls r1, r2, #5 800767e: 68fa ldr r2, [r7, #12] 8007680: 440a add r2, r1 8007682: f502 6210 add.w r2, r2, #2304 @ 0x900 8007686: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800768a: 6013 str r3, [r2, #0] USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; 800768c: 68bb ldr r3, [r7, #8] 800768e: 015a lsls r2, r3, #5 8007690: 68fb ldr r3, [r7, #12] 8007692: 4413 add r3, r2 8007694: f503 6310 add.w r3, r3, #2304 @ 0x900 8007698: 681b ldr r3, [r3, #0] 800769a: 68ba ldr r2, [r7, #8] 800769c: 0151 lsls r1, r2, #5 800769e: 68fa ldr r2, [r7, #12] 80076a0: 440a add r2, r1 80076a2: f502 6210 add.w r2, r2, #2304 @ 0x900 80076a6: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80076aa: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 80076ac: 68fb ldr r3, [r7, #12] 80076ae: f503 6300 add.w r3, r3, #2048 @ 0x800 80076b2: 6bda ldr r2, [r3, #60] @ 0x3c 80076b4: 683b ldr r3, [r7, #0] 80076b6: 781b ldrb r3, [r3, #0] 80076b8: f003 030f and.w r3, r3, #15 80076bc: 2101 movs r1, #1 80076be: fa01 f303 lsl.w r3, r1, r3 80076c2: b29b uxth r3, r3 80076c4: 43db mvns r3, r3 80076c6: 68f9 ldr r1, [r7, #12] 80076c8: f501 6100 add.w r1, r1, #2048 @ 0x800 80076cc: 4013 ands r3, r2 80076ce: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 80076d0: 68fb ldr r3, [r7, #12] 80076d2: f503 6300 add.w r3, r3, #2048 @ 0x800 80076d6: 69da ldr r2, [r3, #28] 80076d8: 683b ldr r3, [r7, #0] 80076da: 781b ldrb r3, [r3, #0] 80076dc: f003 030f and.w r3, r3, #15 80076e0: 2101 movs r1, #1 80076e2: fa01 f303 lsl.w r3, r1, r3 80076e6: b29b uxth r3, r3 80076e8: 43db mvns r3, r3 80076ea: 68f9 ldr r1, [r7, #12] 80076ec: f501 6100 add.w r1, r1, #2048 @ 0x800 80076f0: 4013 ands r3, r2 80076f2: 61cb str r3, [r1, #28] USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | 80076f4: 68bb ldr r3, [r7, #8] 80076f6: 015a lsls r2, r3, #5 80076f8: 68fb ldr r3, [r7, #12] 80076fa: 4413 add r3, r2 80076fc: f503 6310 add.w r3, r3, #2304 @ 0x900 8007700: 681a ldr r2, [r3, #0] 8007702: 68bb ldr r3, [r7, #8] 8007704: 0159 lsls r1, r3, #5 8007706: 68fb ldr r3, [r7, #12] 8007708: 440b add r3, r1 800770a: f503 6310 add.w r3, r3, #2304 @ 0x900 800770e: 4619 mov r1, r3 8007710: 4b35 ldr r3, [pc, #212] @ (80077e8 ) 8007712: 4013 ands r3, r2 8007714: 600b str r3, [r1, #0] 8007716: e060 b.n 80077da USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_EPTYP); } else { if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007718: 68bb ldr r3, [r7, #8] 800771a: 015a lsls r2, r3, #5 800771c: 68fb ldr r3, [r7, #12] 800771e: 4413 add r3, r2 8007720: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007724: 681b ldr r3, [r3, #0] 8007726: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800772a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800772e: d11f bne.n 8007770 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 8007730: 68bb ldr r3, [r7, #8] 8007732: 015a lsls r2, r3, #5 8007734: 68fb ldr r3, [r7, #12] 8007736: 4413 add r3, r2 8007738: f503 6330 add.w r3, r3, #2816 @ 0xb00 800773c: 681b ldr r3, [r3, #0] 800773e: 68ba ldr r2, [r7, #8] 8007740: 0151 lsls r1, r2, #5 8007742: 68fa ldr r2, [r7, #12] 8007744: 440a add r2, r1 8007746: f502 6230 add.w r2, r2, #2816 @ 0xb00 800774a: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800774e: 6013 str r3, [r2, #0] USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; 8007750: 68bb ldr r3, [r7, #8] 8007752: 015a lsls r2, r3, #5 8007754: 68fb ldr r3, [r7, #12] 8007756: 4413 add r3, r2 8007758: f503 6330 add.w r3, r3, #2816 @ 0xb00 800775c: 681b ldr r3, [r3, #0] 800775e: 68ba ldr r2, [r7, #8] 8007760: 0151 lsls r1, r2, #5 8007762: 68fa ldr r2, [r7, #12] 8007764: 440a add r2, r1 8007766: f502 6230 add.w r2, r2, #2816 @ 0xb00 800776a: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800776e: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 8007770: 68fb ldr r3, [r7, #12] 8007772: f503 6300 add.w r3, r3, #2048 @ 0x800 8007776: 6bda ldr r2, [r3, #60] @ 0x3c 8007778: 683b ldr r3, [r7, #0] 800777a: 781b ldrb r3, [r3, #0] 800777c: f003 030f and.w r3, r3, #15 8007780: 2101 movs r1, #1 8007782: fa01 f303 lsl.w r3, r1, r3 8007786: 041b lsls r3, r3, #16 8007788: 43db mvns r3, r3 800778a: 68f9 ldr r1, [r7, #12] 800778c: f501 6100 add.w r1, r1, #2048 @ 0x800 8007790: 4013 ands r3, r2 8007792: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 8007794: 68fb ldr r3, [r7, #12] 8007796: f503 6300 add.w r3, r3, #2048 @ 0x800 800779a: 69da ldr r2, [r3, #28] 800779c: 683b ldr r3, [r7, #0] 800779e: 781b ldrb r3, [r3, #0] 80077a0: f003 030f and.w r3, r3, #15 80077a4: 2101 movs r1, #1 80077a6: fa01 f303 lsl.w r3, r1, r3 80077aa: 041b lsls r3, r3, #16 80077ac: 43db mvns r3, r3 80077ae: 68f9 ldr r1, [r7, #12] 80077b0: f501 6100 add.w r1, r1, #2048 @ 0x800 80077b4: 4013 ands r3, r2 80077b6: 61cb str r3, [r1, #28] USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | 80077b8: 68bb ldr r3, [r7, #8] 80077ba: 015a lsls r2, r3, #5 80077bc: 68fb ldr r3, [r7, #12] 80077be: 4413 add r3, r2 80077c0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80077c4: 681a ldr r2, [r3, #0] 80077c6: 68bb ldr r3, [r7, #8] 80077c8: 0159 lsls r1, r3, #5 80077ca: 68fb ldr r3, [r7, #12] 80077cc: 440b add r3, r1 80077ce: f503 6330 add.w r3, r3, #2816 @ 0xb00 80077d2: 4619 mov r1, r3 80077d4: 4b05 ldr r3, [pc, #20] @ (80077ec ) 80077d6: 4013 ands r3, r2 80077d8: 600b str r3, [r1, #0] USB_OTG_DOEPCTL_MPSIZ | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_EPTYP); } return HAL_OK; 80077da: 2300 movs r3, #0 } 80077dc: 4618 mov r0, r3 80077de: 3714 adds r7, #20 80077e0: 46bd mov sp, r7 80077e2: f85d 7b04 ldr.w r7, [sp], #4 80077e6: 4770 bx lr 80077e8: ec337800 .word 0xec337800 80077ec: eff37800 .word 0xeff37800 080077f0 : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 80077f0: b580 push {r7, lr} 80077f2: b08a sub sp, #40 @ 0x28 80077f4: af02 add r7, sp, #8 80077f6: 60f8 str r0, [r7, #12] 80077f8: 60b9 str r1, [r7, #8] 80077fa: 4613 mov r3, r2 80077fc: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 80077fe: 68fb ldr r3, [r7, #12] 8007800: 61fb str r3, [r7, #28] uint32_t epnum = (uint32_t)ep->num; 8007802: 68bb ldr r3, [r7, #8] 8007804: 781b ldrb r3, [r3, #0] 8007806: 61bb str r3, [r7, #24] uint16_t pktcnt; /* IN endpoint */ if (ep->is_in == 1U) 8007808: 68bb ldr r3, [r7, #8] 800780a: 785b ldrb r3, [r3, #1] 800780c: 2b01 cmp r3, #1 800780e: f040 817f bne.w 8007b10 { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 8007812: 68bb ldr r3, [r7, #8] 8007814: 691b ldr r3, [r3, #16] 8007816: 2b00 cmp r3, #0 8007818: d132 bne.n 8007880 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 800781a: 69bb ldr r3, [r7, #24] 800781c: 015a lsls r2, r3, #5 800781e: 69fb ldr r3, [r7, #28] 8007820: 4413 add r3, r2 8007822: f503 6310 add.w r3, r3, #2304 @ 0x900 8007826: 691b ldr r3, [r3, #16] 8007828: 69ba ldr r2, [r7, #24] 800782a: 0151 lsls r1, r2, #5 800782c: 69fa ldr r2, [r7, #28] 800782e: 440a add r2, r1 8007830: f502 6210 add.w r2, r2, #2304 @ 0x900 8007834: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007838: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 800783c: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 800783e: 69bb ldr r3, [r7, #24] 8007840: 015a lsls r2, r3, #5 8007842: 69fb ldr r3, [r7, #28] 8007844: 4413 add r3, r2 8007846: f503 6310 add.w r3, r3, #2304 @ 0x900 800784a: 691b ldr r3, [r3, #16] 800784c: 69ba ldr r2, [r7, #24] 800784e: 0151 lsls r1, r2, #5 8007850: 69fa ldr r2, [r7, #28] 8007852: 440a add r2, r1 8007854: f502 6210 add.w r2, r2, #2304 @ 0x900 8007858: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800785c: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 800785e: 69bb ldr r3, [r7, #24] 8007860: 015a lsls r2, r3, #5 8007862: 69fb ldr r3, [r7, #28] 8007864: 4413 add r3, r2 8007866: f503 6310 add.w r3, r3, #2304 @ 0x900 800786a: 691b ldr r3, [r3, #16] 800786c: 69ba ldr r2, [r7, #24] 800786e: 0151 lsls r1, r2, #5 8007870: 69fa ldr r2, [r7, #28] 8007872: 440a add r2, r1 8007874: f502 6210 add.w r2, r2, #2304 @ 0x900 8007878: 0cdb lsrs r3, r3, #19 800787a: 04db lsls r3, r3, #19 800787c: 6113 str r3, [r2, #16] 800787e: e097 b.n 80079b0 /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8007880: 69bb ldr r3, [r7, #24] 8007882: 015a lsls r2, r3, #5 8007884: 69fb ldr r3, [r7, #28] 8007886: 4413 add r3, r2 8007888: f503 6310 add.w r3, r3, #2304 @ 0x900 800788c: 691b ldr r3, [r3, #16] 800788e: 69ba ldr r2, [r7, #24] 8007890: 0151 lsls r1, r2, #5 8007892: 69fa ldr r2, [r7, #28] 8007894: 440a add r2, r1 8007896: f502 6210 add.w r2, r2, #2304 @ 0x900 800789a: 0cdb lsrs r3, r3, #19 800789c: 04db lsls r3, r3, #19 800789e: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 80078a0: 69bb ldr r3, [r7, #24] 80078a2: 015a lsls r2, r3, #5 80078a4: 69fb ldr r3, [r7, #28] 80078a6: 4413 add r3, r2 80078a8: f503 6310 add.w r3, r3, #2304 @ 0x900 80078ac: 691b ldr r3, [r3, #16] 80078ae: 69ba ldr r2, [r7, #24] 80078b0: 0151 lsls r1, r2, #5 80078b2: 69fa ldr r2, [r7, #28] 80078b4: 440a add r2, r1 80078b6: f502 6210 add.w r2, r2, #2304 @ 0x900 80078ba: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 80078be: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 80078c2: 6113 str r3, [r2, #16] if (epnum == 0U) 80078c4: 69bb ldr r3, [r7, #24] 80078c6: 2b00 cmp r3, #0 80078c8: d11a bne.n 8007900 { if (ep->xfer_len > ep->maxpacket) 80078ca: 68bb ldr r3, [r7, #8] 80078cc: 691a ldr r2, [r3, #16] 80078ce: 68bb ldr r3, [r7, #8] 80078d0: 689b ldr r3, [r3, #8] 80078d2: 429a cmp r2, r3 80078d4: d903 bls.n 80078de { ep->xfer_len = ep->maxpacket; 80078d6: 68bb ldr r3, [r7, #8] 80078d8: 689a ldr r2, [r3, #8] 80078da: 68bb ldr r3, [r7, #8] 80078dc: 611a str r2, [r3, #16] } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 80078de: 69bb ldr r3, [r7, #24] 80078e0: 015a lsls r2, r3, #5 80078e2: 69fb ldr r3, [r7, #28] 80078e4: 4413 add r3, r2 80078e6: f503 6310 add.w r3, r3, #2304 @ 0x900 80078ea: 691b ldr r3, [r3, #16] 80078ec: 69ba ldr r2, [r7, #24] 80078ee: 0151 lsls r1, r2, #5 80078f0: 69fa ldr r2, [r7, #28] 80078f2: 440a add r2, r1 80078f4: f502 6210 add.w r2, r2, #2304 @ 0x900 80078f8: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80078fc: 6113 str r3, [r2, #16] 80078fe: e044 b.n 800798a } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8007900: 68bb ldr r3, [r7, #8] 8007902: 691a ldr r2, [r3, #16] 8007904: 68bb ldr r3, [r7, #8] 8007906: 689b ldr r3, [r3, #8] 8007908: 4413 add r3, r2 800790a: 1e5a subs r2, r3, #1 800790c: 68bb ldr r3, [r7, #8] 800790e: 689b ldr r3, [r3, #8] 8007910: fbb2 f3f3 udiv r3, r2, r3 8007914: 82fb strh r3, [r7, #22] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); 8007916: 69bb ldr r3, [r7, #24] 8007918: 015a lsls r2, r3, #5 800791a: 69fb ldr r3, [r7, #28] 800791c: 4413 add r3, r2 800791e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007922: 691a ldr r2, [r3, #16] 8007924: 8afb ldrh r3, [r7, #22] 8007926: 04d9 lsls r1, r3, #19 8007928: 4ba4 ldr r3, [pc, #656] @ (8007bbc ) 800792a: 400b ands r3, r1 800792c: 69b9 ldr r1, [r7, #24] 800792e: 0148 lsls r0, r1, #5 8007930: 69f9 ldr r1, [r7, #28] 8007932: 4401 add r1, r0 8007934: f501 6110 add.w r1, r1, #2304 @ 0x900 8007938: 4313 orrs r3, r2 800793a: 610b str r3, [r1, #16] if (ep->type == EP_TYPE_ISOC) 800793c: 68bb ldr r3, [r7, #8] 800793e: 791b ldrb r3, [r3, #4] 8007940: 2b01 cmp r3, #1 8007942: d122 bne.n 800798a { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 8007944: 69bb ldr r3, [r7, #24] 8007946: 015a lsls r2, r3, #5 8007948: 69fb ldr r3, [r7, #28] 800794a: 4413 add r3, r2 800794c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007950: 691b ldr r3, [r3, #16] 8007952: 69ba ldr r2, [r7, #24] 8007954: 0151 lsls r1, r2, #5 8007956: 69fa ldr r2, [r7, #28] 8007958: 440a add r2, r1 800795a: f502 6210 add.w r2, r2, #2304 @ 0x900 800795e: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000 8007962: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); 8007964: 69bb ldr r3, [r7, #24] 8007966: 015a lsls r2, r3, #5 8007968: 69fb ldr r3, [r7, #28] 800796a: 4413 add r3, r2 800796c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007970: 691a ldr r2, [r3, #16] 8007972: 8afb ldrh r3, [r7, #22] 8007974: 075b lsls r3, r3, #29 8007976: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000 800797a: 69b9 ldr r1, [r7, #24] 800797c: 0148 lsls r0, r1, #5 800797e: 69f9 ldr r1, [r7, #28] 8007980: 4401 add r1, r0 8007982: f501 6110 add.w r1, r1, #2304 @ 0x900 8007986: 4313 orrs r3, r2 8007988: 610b str r3, [r1, #16] } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 800798a: 69bb ldr r3, [r7, #24] 800798c: 015a lsls r2, r3, #5 800798e: 69fb ldr r3, [r7, #28] 8007990: 4413 add r3, r2 8007992: f503 6310 add.w r3, r3, #2304 @ 0x900 8007996: 691a ldr r2, [r3, #16] 8007998: 68bb ldr r3, [r7, #8] 800799a: 691b ldr r3, [r3, #16] 800799c: f3c3 0312 ubfx r3, r3, #0, #19 80079a0: 69b9 ldr r1, [r7, #24] 80079a2: 0148 lsls r0, r1, #5 80079a4: 69f9 ldr r1, [r7, #28] 80079a6: 4401 add r1, r0 80079a8: f501 6110 add.w r1, r1, #2304 @ 0x900 80079ac: 4313 orrs r3, r2 80079ae: 610b str r3, [r1, #16] } if (dma == 1U) 80079b0: 79fb ldrb r3, [r7, #7] 80079b2: 2b01 cmp r3, #1 80079b4: d14b bne.n 8007a4e { if ((uint32_t)ep->dma_addr != 0U) 80079b6: 68bb ldr r3, [r7, #8] 80079b8: 69db ldr r3, [r3, #28] 80079ba: 2b00 cmp r3, #0 80079bc: d009 beq.n 80079d2 { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 80079be: 69bb ldr r3, [r7, #24] 80079c0: 015a lsls r2, r3, #5 80079c2: 69fb ldr r3, [r7, #28] 80079c4: 4413 add r3, r2 80079c6: f503 6310 add.w r3, r3, #2304 @ 0x900 80079ca: 461a mov r2, r3 80079cc: 68bb ldr r3, [r7, #8] 80079ce: 69db ldr r3, [r3, #28] 80079d0: 6153 str r3, [r2, #20] } if (ep->type == EP_TYPE_ISOC) 80079d2: 68bb ldr r3, [r7, #8] 80079d4: 791b ldrb r3, [r3, #4] 80079d6: 2b01 cmp r3, #1 80079d8: d128 bne.n 8007a2c { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 80079da: 69fb ldr r3, [r7, #28] 80079dc: f503 6300 add.w r3, r3, #2048 @ 0x800 80079e0: 689b ldr r3, [r3, #8] 80079e2: f403 7380 and.w r3, r3, #256 @ 0x100 80079e6: 2b00 cmp r3, #0 80079e8: d110 bne.n 8007a0c { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 80079ea: 69bb ldr r3, [r7, #24] 80079ec: 015a lsls r2, r3, #5 80079ee: 69fb ldr r3, [r7, #28] 80079f0: 4413 add r3, r2 80079f2: f503 6310 add.w r3, r3, #2304 @ 0x900 80079f6: 681b ldr r3, [r3, #0] 80079f8: 69ba ldr r2, [r7, #24] 80079fa: 0151 lsls r1, r2, #5 80079fc: 69fa ldr r2, [r7, #28] 80079fe: 440a add r2, r1 8007a00: f502 6210 add.w r2, r2, #2304 @ 0x900 8007a04: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007a08: 6013 str r3, [r2, #0] 8007a0a: e00f b.n 8007a2c } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8007a0c: 69bb ldr r3, [r7, #24] 8007a0e: 015a lsls r2, r3, #5 8007a10: 69fb ldr r3, [r7, #28] 8007a12: 4413 add r3, r2 8007a14: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a18: 681b ldr r3, [r3, #0] 8007a1a: 69ba ldr r2, [r7, #24] 8007a1c: 0151 lsls r1, r2, #5 8007a1e: 69fa ldr r2, [r7, #28] 8007a20: 440a add r2, r1 8007a22: f502 6210 add.w r2, r2, #2304 @ 0x900 8007a26: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007a2a: 6013 str r3, [r2, #0] } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8007a2c: 69bb ldr r3, [r7, #24] 8007a2e: 015a lsls r2, r3, #5 8007a30: 69fb ldr r3, [r7, #28] 8007a32: 4413 add r3, r2 8007a34: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a38: 681b ldr r3, [r3, #0] 8007a3a: 69ba ldr r2, [r7, #24] 8007a3c: 0151 lsls r1, r2, #5 8007a3e: 69fa ldr r2, [r7, #28] 8007a40: 440a add r2, r1 8007a42: f502 6210 add.w r2, r2, #2304 @ 0x900 8007a46: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007a4a: 6013 str r3, [r2, #0] 8007a4c: e166 b.n 8007d1c } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8007a4e: 69bb ldr r3, [r7, #24] 8007a50: 015a lsls r2, r3, #5 8007a52: 69fb ldr r3, [r7, #28] 8007a54: 4413 add r3, r2 8007a56: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a5a: 681b ldr r3, [r3, #0] 8007a5c: 69ba ldr r2, [r7, #24] 8007a5e: 0151 lsls r1, r2, #5 8007a60: 69fa ldr r2, [r7, #28] 8007a62: 440a add r2, r1 8007a64: f502 6210 add.w r2, r2, #2304 @ 0x900 8007a68: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007a6c: 6013 str r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 8007a6e: 68bb ldr r3, [r7, #8] 8007a70: 791b ldrb r3, [r3, #4] 8007a72: 2b01 cmp r3, #1 8007a74: d015 beq.n 8007aa2 { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 8007a76: 68bb ldr r3, [r7, #8] 8007a78: 691b ldr r3, [r3, #16] 8007a7a: 2b00 cmp r3, #0 8007a7c: f000 814e beq.w 8007d1c { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 8007a80: 69fb ldr r3, [r7, #28] 8007a82: f503 6300 add.w r3, r3, #2048 @ 0x800 8007a86: 6b5a ldr r2, [r3, #52] @ 0x34 8007a88: 68bb ldr r3, [r7, #8] 8007a8a: 781b ldrb r3, [r3, #0] 8007a8c: f003 030f and.w r3, r3, #15 8007a90: 2101 movs r1, #1 8007a92: fa01 f303 lsl.w r3, r1, r3 8007a96: 69f9 ldr r1, [r7, #28] 8007a98: f501 6100 add.w r1, r1, #2048 @ 0x800 8007a9c: 4313 orrs r3, r2 8007a9e: 634b str r3, [r1, #52] @ 0x34 8007aa0: e13c b.n 8007d1c } } else { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007aa2: 69fb ldr r3, [r7, #28] 8007aa4: f503 6300 add.w r3, r3, #2048 @ 0x800 8007aa8: 689b ldr r3, [r3, #8] 8007aaa: f403 7380 and.w r3, r3, #256 @ 0x100 8007aae: 2b00 cmp r3, #0 8007ab0: d110 bne.n 8007ad4 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8007ab2: 69bb ldr r3, [r7, #24] 8007ab4: 015a lsls r2, r3, #5 8007ab6: 69fb ldr r3, [r7, #28] 8007ab8: 4413 add r3, r2 8007aba: f503 6310 add.w r3, r3, #2304 @ 0x900 8007abe: 681b ldr r3, [r3, #0] 8007ac0: 69ba ldr r2, [r7, #24] 8007ac2: 0151 lsls r1, r2, #5 8007ac4: 69fa ldr r2, [r7, #28] 8007ac6: 440a add r2, r1 8007ac8: f502 6210 add.w r2, r2, #2304 @ 0x900 8007acc: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007ad0: 6013 str r3, [r2, #0] 8007ad2: e00f b.n 8007af4 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8007ad4: 69bb ldr r3, [r7, #24] 8007ad6: 015a lsls r2, r3, #5 8007ad8: 69fb ldr r3, [r7, #28] 8007ada: 4413 add r3, r2 8007adc: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ae0: 681b ldr r3, [r3, #0] 8007ae2: 69ba ldr r2, [r7, #24] 8007ae4: 0151 lsls r1, r2, #5 8007ae6: 69fa ldr r2, [r7, #28] 8007ae8: 440a add r2, r1 8007aea: f502 6210 add.w r2, r2, #2304 @ 0x900 8007aee: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007af2: 6013 str r3, [r2, #0] } (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); 8007af4: 68bb ldr r3, [r7, #8] 8007af6: 68d9 ldr r1, [r3, #12] 8007af8: 68bb ldr r3, [r7, #8] 8007afa: 781a ldrb r2, [r3, #0] 8007afc: 68bb ldr r3, [r7, #8] 8007afe: 691b ldr r3, [r3, #16] 8007b00: b298 uxth r0, r3 8007b02: 79fb ldrb r3, [r7, #7] 8007b04: 9300 str r3, [sp, #0] 8007b06: 4603 mov r3, r0 8007b08: 68f8 ldr r0, [r7, #12] 8007b0a: f000 f9b9 bl 8007e80 8007b0e: e105 b.n 8007d1c { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 8007b10: 69bb ldr r3, [r7, #24] 8007b12: 015a lsls r2, r3, #5 8007b14: 69fb ldr r3, [r7, #28] 8007b16: 4413 add r3, r2 8007b18: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007b1c: 691b ldr r3, [r3, #16] 8007b1e: 69ba ldr r2, [r7, #24] 8007b20: 0151 lsls r1, r2, #5 8007b22: 69fa ldr r2, [r7, #28] 8007b24: 440a add r2, r1 8007b26: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007b2a: 0cdb lsrs r3, r3, #19 8007b2c: 04db lsls r3, r3, #19 8007b2e: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 8007b30: 69bb ldr r3, [r7, #24] 8007b32: 015a lsls r2, r3, #5 8007b34: 69fb ldr r3, [r7, #28] 8007b36: 4413 add r3, r2 8007b38: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007b3c: 691b ldr r3, [r3, #16] 8007b3e: 69ba ldr r2, [r7, #24] 8007b40: 0151 lsls r1, r2, #5 8007b42: 69fa ldr r2, [r7, #28] 8007b44: 440a add r2, r1 8007b46: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007b4a: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007b4e: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8007b52: 6113 str r3, [r2, #16] if (epnum == 0U) 8007b54: 69bb ldr r3, [r7, #24] 8007b56: 2b00 cmp r3, #0 8007b58: d132 bne.n 8007bc0 { if (ep->xfer_len > 0U) 8007b5a: 68bb ldr r3, [r7, #8] 8007b5c: 691b ldr r3, [r3, #16] 8007b5e: 2b00 cmp r3, #0 8007b60: d003 beq.n 8007b6a { ep->xfer_len = ep->maxpacket; 8007b62: 68bb ldr r3, [r7, #8] 8007b64: 689a ldr r2, [r3, #8] 8007b66: 68bb ldr r3, [r7, #8] 8007b68: 611a str r2, [r3, #16] } /* Store transfer size, for EP0 this is equal to endpoint max packet size */ ep->xfer_size = ep->maxpacket; 8007b6a: 68bb ldr r3, [r7, #8] 8007b6c: 689a ldr r2, [r3, #8] 8007b6e: 68bb ldr r3, [r7, #8] 8007b70: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); 8007b72: 69bb ldr r3, [r7, #24] 8007b74: 015a lsls r2, r3, #5 8007b76: 69fb ldr r3, [r7, #28] 8007b78: 4413 add r3, r2 8007b7a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007b7e: 691a ldr r2, [r3, #16] 8007b80: 68bb ldr r3, [r7, #8] 8007b82: 6a1b ldr r3, [r3, #32] 8007b84: f3c3 0312 ubfx r3, r3, #0, #19 8007b88: 69b9 ldr r1, [r7, #24] 8007b8a: 0148 lsls r0, r1, #5 8007b8c: 69f9 ldr r1, [r7, #28] 8007b8e: 4401 add r1, r0 8007b90: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007b94: 4313 orrs r3, r2 8007b96: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8007b98: 69bb ldr r3, [r7, #24] 8007b9a: 015a lsls r2, r3, #5 8007b9c: 69fb ldr r3, [r7, #28] 8007b9e: 4413 add r3, r2 8007ba0: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007ba4: 691b ldr r3, [r3, #16] 8007ba6: 69ba ldr r2, [r7, #24] 8007ba8: 0151 lsls r1, r2, #5 8007baa: 69fa ldr r2, [r7, #28] 8007bac: 440a add r2, r1 8007bae: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007bb2: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007bb6: 6113 str r3, [r2, #16] 8007bb8: e062 b.n 8007c80 8007bba: bf00 nop 8007bbc: 1ff80000 .word 0x1ff80000 } else { if (ep->xfer_len == 0U) 8007bc0: 68bb ldr r3, [r7, #8] 8007bc2: 691b ldr r3, [r3, #16] 8007bc4: 2b00 cmp r3, #0 8007bc6: d123 bne.n 8007c10 { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 8007bc8: 69bb ldr r3, [r7, #24] 8007bca: 015a lsls r2, r3, #5 8007bcc: 69fb ldr r3, [r7, #28] 8007bce: 4413 add r3, r2 8007bd0: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007bd4: 691a ldr r2, [r3, #16] 8007bd6: 68bb ldr r3, [r7, #8] 8007bd8: 689b ldr r3, [r3, #8] 8007bda: f3c3 0312 ubfx r3, r3, #0, #19 8007bde: 69b9 ldr r1, [r7, #24] 8007be0: 0148 lsls r0, r1, #5 8007be2: 69f9 ldr r1, [r7, #28] 8007be4: 4401 add r1, r0 8007be6: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007bea: 4313 orrs r3, r2 8007bec: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8007bee: 69bb ldr r3, [r7, #24] 8007bf0: 015a lsls r2, r3, #5 8007bf2: 69fb ldr r3, [r7, #28] 8007bf4: 4413 add r3, r2 8007bf6: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007bfa: 691b ldr r3, [r3, #16] 8007bfc: 69ba ldr r2, [r7, #24] 8007bfe: 0151 lsls r1, r2, #5 8007c00: 69fa ldr r2, [r7, #28] 8007c02: 440a add r2, r1 8007c04: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007c08: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007c0c: 6113 str r3, [r2, #16] 8007c0e: e037 b.n 8007c80 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8007c10: 68bb ldr r3, [r7, #8] 8007c12: 691a ldr r2, [r3, #16] 8007c14: 68bb ldr r3, [r7, #8] 8007c16: 689b ldr r3, [r3, #8] 8007c18: 4413 add r3, r2 8007c1a: 1e5a subs r2, r3, #1 8007c1c: 68bb ldr r3, [r7, #8] 8007c1e: 689b ldr r3, [r3, #8] 8007c20: fbb2 f3f3 udiv r3, r2, r3 8007c24: 82fb strh r3, [r7, #22] ep->xfer_size = ep->maxpacket * pktcnt; 8007c26: 68bb ldr r3, [r7, #8] 8007c28: 689b ldr r3, [r3, #8] 8007c2a: 8afa ldrh r2, [r7, #22] 8007c2c: fb03 f202 mul.w r2, r3, r2 8007c30: 68bb ldr r3, [r7, #8] 8007c32: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); 8007c34: 69bb ldr r3, [r7, #24] 8007c36: 015a lsls r2, r3, #5 8007c38: 69fb ldr r3, [r7, #28] 8007c3a: 4413 add r3, r2 8007c3c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007c40: 691a ldr r2, [r3, #16] 8007c42: 8afb ldrh r3, [r7, #22] 8007c44: 04d9 lsls r1, r3, #19 8007c46: 4b38 ldr r3, [pc, #224] @ (8007d28 ) 8007c48: 400b ands r3, r1 8007c4a: 69b9 ldr r1, [r7, #24] 8007c4c: 0148 lsls r0, r1, #5 8007c4e: 69f9 ldr r1, [r7, #28] 8007c50: 4401 add r1, r0 8007c52: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007c56: 4313 orrs r3, r2 8007c58: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; 8007c5a: 69bb ldr r3, [r7, #24] 8007c5c: 015a lsls r2, r3, #5 8007c5e: 69fb ldr r3, [r7, #28] 8007c60: 4413 add r3, r2 8007c62: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007c66: 691a ldr r2, [r3, #16] 8007c68: 68bb ldr r3, [r7, #8] 8007c6a: 6a1b ldr r3, [r3, #32] 8007c6c: f3c3 0312 ubfx r3, r3, #0, #19 8007c70: 69b9 ldr r1, [r7, #24] 8007c72: 0148 lsls r0, r1, #5 8007c74: 69f9 ldr r1, [r7, #28] 8007c76: 4401 add r1, r0 8007c78: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007c7c: 4313 orrs r3, r2 8007c7e: 610b str r3, [r1, #16] } } if (dma == 1U) 8007c80: 79fb ldrb r3, [r7, #7] 8007c82: 2b01 cmp r3, #1 8007c84: d10d bne.n 8007ca2 { if ((uint32_t)ep->xfer_buff != 0U) 8007c86: 68bb ldr r3, [r7, #8] 8007c88: 68db ldr r3, [r3, #12] 8007c8a: 2b00 cmp r3, #0 8007c8c: d009 beq.n 8007ca2 { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 8007c8e: 68bb ldr r3, [r7, #8] 8007c90: 68d9 ldr r1, [r3, #12] 8007c92: 69bb ldr r3, [r7, #24] 8007c94: 015a lsls r2, r3, #5 8007c96: 69fb ldr r3, [r7, #28] 8007c98: 4413 add r3, r2 8007c9a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007c9e: 460a mov r2, r1 8007ca0: 615a str r2, [r3, #20] } } if (ep->type == EP_TYPE_ISOC) 8007ca2: 68bb ldr r3, [r7, #8] 8007ca4: 791b ldrb r3, [r3, #4] 8007ca6: 2b01 cmp r3, #1 8007ca8: d128 bne.n 8007cfc { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007caa: 69fb ldr r3, [r7, #28] 8007cac: f503 6300 add.w r3, r3, #2048 @ 0x800 8007cb0: 689b ldr r3, [r3, #8] 8007cb2: f403 7380 and.w r3, r3, #256 @ 0x100 8007cb6: 2b00 cmp r3, #0 8007cb8: d110 bne.n 8007cdc { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 8007cba: 69bb ldr r3, [r7, #24] 8007cbc: 015a lsls r2, r3, #5 8007cbe: 69fb ldr r3, [r7, #28] 8007cc0: 4413 add r3, r2 8007cc2: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007cc6: 681b ldr r3, [r3, #0] 8007cc8: 69ba ldr r2, [r7, #24] 8007cca: 0151 lsls r1, r2, #5 8007ccc: 69fa ldr r2, [r7, #28] 8007cce: 440a add r2, r1 8007cd0: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007cd4: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007cd8: 6013 str r3, [r2, #0] 8007cda: e00f b.n 8007cfc } else { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 8007cdc: 69bb ldr r3, [r7, #24] 8007cde: 015a lsls r2, r3, #5 8007ce0: 69fb ldr r3, [r7, #28] 8007ce2: 4413 add r3, r2 8007ce4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007ce8: 681b ldr r3, [r3, #0] 8007cea: 69ba ldr r2, [r7, #24] 8007cec: 0151 lsls r1, r2, #5 8007cee: 69fa ldr r2, [r7, #28] 8007cf0: 440a add r2, r1 8007cf2: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007cf6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007cfa: 6013 str r3, [r2, #0] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8007cfc: 69bb ldr r3, [r7, #24] 8007cfe: 015a lsls r2, r3, #5 8007d00: 69fb ldr r3, [r7, #28] 8007d02: 4413 add r3, r2 8007d04: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d08: 681b ldr r3, [r3, #0] 8007d0a: 69ba ldr r2, [r7, #24] 8007d0c: 0151 lsls r1, r2, #5 8007d0e: 69fa ldr r2, [r7, #28] 8007d10: 440a add r2, r1 8007d12: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007d16: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007d1a: 6013 str r3, [r2, #0] } return HAL_OK; 8007d1c: 2300 movs r3, #0 } 8007d1e: 4618 mov r0, r3 8007d20: 3720 adds r7, #32 8007d22: 46bd mov sp, r7 8007d24: bd80 pop {r7, pc} 8007d26: bf00 nop 8007d28: 1ff80000 .word 0x1ff80000 08007d2c : * @param USBx usb device instance * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8007d2c: b480 push {r7} 8007d2e: b087 sub sp, #28 8007d30: af00 add r7, sp, #0 8007d32: 6078 str r0, [r7, #4] 8007d34: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8007d36: 2300 movs r3, #0 8007d38: 60fb str r3, [r7, #12] HAL_StatusTypeDef ret = HAL_OK; 8007d3a: 2300 movs r3, #0 8007d3c: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8007d3e: 687b ldr r3, [r7, #4] 8007d40: 613b str r3, [r7, #16] /* IN endpoint */ if (ep->is_in == 1U) 8007d42: 683b ldr r3, [r7, #0] 8007d44: 785b ldrb r3, [r3, #1] 8007d46: 2b01 cmp r3, #1 8007d48: d14a bne.n 8007de0 { /* EP enable, IN data in FIFO */ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007d4a: 683b ldr r3, [r7, #0] 8007d4c: 781b ldrb r3, [r3, #0] 8007d4e: 015a lsls r2, r3, #5 8007d50: 693b ldr r3, [r7, #16] 8007d52: 4413 add r3, r2 8007d54: f503 6310 add.w r3, r3, #2304 @ 0x900 8007d58: 681b ldr r3, [r3, #0] 8007d5a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007d5e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007d62: f040 8086 bne.w 8007e72 { USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); 8007d66: 683b ldr r3, [r7, #0] 8007d68: 781b ldrb r3, [r3, #0] 8007d6a: 015a lsls r2, r3, #5 8007d6c: 693b ldr r3, [r7, #16] 8007d6e: 4413 add r3, r2 8007d70: f503 6310 add.w r3, r3, #2304 @ 0x900 8007d74: 681b ldr r3, [r3, #0] 8007d76: 683a ldr r2, [r7, #0] 8007d78: 7812 ldrb r2, [r2, #0] 8007d7a: 0151 lsls r1, r2, #5 8007d7c: 693a ldr r2, [r7, #16] 8007d7e: 440a add r2, r1 8007d80: f502 6210 add.w r2, r2, #2304 @ 0x900 8007d84: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007d88: 6013 str r3, [r2, #0] USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); 8007d8a: 683b ldr r3, [r7, #0] 8007d8c: 781b ldrb r3, [r3, #0] 8007d8e: 015a lsls r2, r3, #5 8007d90: 693b ldr r3, [r7, #16] 8007d92: 4413 add r3, r2 8007d94: f503 6310 add.w r3, r3, #2304 @ 0x900 8007d98: 681b ldr r3, [r3, #0] 8007d9a: 683a ldr r2, [r7, #0] 8007d9c: 7812 ldrb r2, [r2, #0] 8007d9e: 0151 lsls r1, r2, #5 8007da0: 693a ldr r2, [r7, #16] 8007da2: 440a add r2, r1 8007da4: f502 6210 add.w r2, r2, #2304 @ 0x900 8007da8: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007dac: 6013 str r3, [r2, #0] do { count++; 8007dae: 68fb ldr r3, [r7, #12] 8007db0: 3301 adds r3, #1 8007db2: 60fb str r3, [r7, #12] if (count > 10000U) 8007db4: 68fb ldr r3, [r7, #12] 8007db6: f242 7210 movw r2, #10000 @ 0x2710 8007dba: 4293 cmp r3, r2 8007dbc: d902 bls.n 8007dc4 { ret = HAL_ERROR; 8007dbe: 2301 movs r3, #1 8007dc0: 75fb strb r3, [r7, #23] break; 8007dc2: e056 b.n 8007e72 } } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); 8007dc4: 683b ldr r3, [r7, #0] 8007dc6: 781b ldrb r3, [r3, #0] 8007dc8: 015a lsls r2, r3, #5 8007dca: 693b ldr r3, [r7, #16] 8007dcc: 4413 add r3, r2 8007dce: f503 6310 add.w r3, r3, #2304 @ 0x900 8007dd2: 681b ldr r3, [r3, #0] 8007dd4: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007dd8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007ddc: d0e7 beq.n 8007dae 8007dde: e048 b.n 8007e72 } } else /* OUT endpoint */ { if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007de0: 683b ldr r3, [r7, #0] 8007de2: 781b ldrb r3, [r3, #0] 8007de4: 015a lsls r2, r3, #5 8007de6: 693b ldr r3, [r7, #16] 8007de8: 4413 add r3, r2 8007dea: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007dee: 681b ldr r3, [r3, #0] 8007df0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007df4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007df8: d13b bne.n 8007e72 { USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); 8007dfa: 683b ldr r3, [r7, #0] 8007dfc: 781b ldrb r3, [r3, #0] 8007dfe: 015a lsls r2, r3, #5 8007e00: 693b ldr r3, [r7, #16] 8007e02: 4413 add r3, r2 8007e04: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e08: 681b ldr r3, [r3, #0] 8007e0a: 683a ldr r2, [r7, #0] 8007e0c: 7812 ldrb r2, [r2, #0] 8007e0e: 0151 lsls r1, r2, #5 8007e10: 693a ldr r2, [r7, #16] 8007e12: 440a add r2, r1 8007e14: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007e18: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007e1c: 6013 str r3, [r2, #0] USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); 8007e1e: 683b ldr r3, [r7, #0] 8007e20: 781b ldrb r3, [r3, #0] 8007e22: 015a lsls r2, r3, #5 8007e24: 693b ldr r3, [r7, #16] 8007e26: 4413 add r3, r2 8007e28: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e2c: 681b ldr r3, [r3, #0] 8007e2e: 683a ldr r2, [r7, #0] 8007e30: 7812 ldrb r2, [r2, #0] 8007e32: 0151 lsls r1, r2, #5 8007e34: 693a ldr r2, [r7, #16] 8007e36: 440a add r2, r1 8007e38: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007e3c: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007e40: 6013 str r3, [r2, #0] do { count++; 8007e42: 68fb ldr r3, [r7, #12] 8007e44: 3301 adds r3, #1 8007e46: 60fb str r3, [r7, #12] if (count > 10000U) 8007e48: 68fb ldr r3, [r7, #12] 8007e4a: f242 7210 movw r2, #10000 @ 0x2710 8007e4e: 4293 cmp r3, r2 8007e50: d902 bls.n 8007e58 { ret = HAL_ERROR; 8007e52: 2301 movs r3, #1 8007e54: 75fb strb r3, [r7, #23] break; 8007e56: e00c b.n 8007e72 } } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); 8007e58: 683b ldr r3, [r7, #0] 8007e5a: 781b ldrb r3, [r3, #0] 8007e5c: 015a lsls r2, r3, #5 8007e5e: 693b ldr r3, [r7, #16] 8007e60: 4413 add r3, r2 8007e62: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e66: 681b ldr r3, [r3, #0] 8007e68: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007e6c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007e70: d0e7 beq.n 8007e42 } } return ret; 8007e72: 7dfb ldrb r3, [r7, #23] } 8007e74: 4618 mov r0, r3 8007e76: 371c adds r7, #28 8007e78: 46bd mov sp, r7 8007e7a: f85d 7b04 ldr.w r7, [sp], #4 8007e7e: 4770 bx lr 08007e80 : * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { 8007e80: b480 push {r7} 8007e82: b089 sub sp, #36 @ 0x24 8007e84: af00 add r7, sp, #0 8007e86: 60f8 str r0, [r7, #12] 8007e88: 60b9 str r1, [r7, #8] 8007e8a: 4611 mov r1, r2 8007e8c: 461a mov r2, r3 8007e8e: 460b mov r3, r1 8007e90: 71fb strb r3, [r7, #7] 8007e92: 4613 mov r3, r2 8007e94: 80bb strh r3, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007e96: 68fb ldr r3, [r7, #12] 8007e98: 617b str r3, [r7, #20] uint8_t *pSrc = src; 8007e9a: 68bb ldr r3, [r7, #8] 8007e9c: 61fb str r3, [r7, #28] uint32_t count32b; uint32_t i; if (dma == 0U) 8007e9e: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8007ea2: 2b00 cmp r3, #0 8007ea4: d123 bne.n 8007eee { count32b = ((uint32_t)len + 3U) / 4U; 8007ea6: 88bb ldrh r3, [r7, #4] 8007ea8: 3303 adds r3, #3 8007eaa: 089b lsrs r3, r3, #2 8007eac: 613b str r3, [r7, #16] for (i = 0U; i < count32b; i++) 8007eae: 2300 movs r3, #0 8007eb0: 61bb str r3, [r7, #24] 8007eb2: e018 b.n 8007ee6 { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); 8007eb4: 79fb ldrb r3, [r7, #7] 8007eb6: 031a lsls r2, r3, #12 8007eb8: 697b ldr r3, [r7, #20] 8007eba: 4413 add r3, r2 8007ebc: f503 5380 add.w r3, r3, #4096 @ 0x1000 8007ec0: 461a mov r2, r3 8007ec2: 69fb ldr r3, [r7, #28] 8007ec4: 681b ldr r3, [r3, #0] 8007ec6: 6013 str r3, [r2, #0] pSrc++; 8007ec8: 69fb ldr r3, [r7, #28] 8007eca: 3301 adds r3, #1 8007ecc: 61fb str r3, [r7, #28] pSrc++; 8007ece: 69fb ldr r3, [r7, #28] 8007ed0: 3301 adds r3, #1 8007ed2: 61fb str r3, [r7, #28] pSrc++; 8007ed4: 69fb ldr r3, [r7, #28] 8007ed6: 3301 adds r3, #1 8007ed8: 61fb str r3, [r7, #28] pSrc++; 8007eda: 69fb ldr r3, [r7, #28] 8007edc: 3301 adds r3, #1 8007ede: 61fb str r3, [r7, #28] for (i = 0U; i < count32b; i++) 8007ee0: 69bb ldr r3, [r7, #24] 8007ee2: 3301 adds r3, #1 8007ee4: 61bb str r3, [r7, #24] 8007ee6: 69ba ldr r2, [r7, #24] 8007ee8: 693b ldr r3, [r7, #16] 8007eea: 429a cmp r2, r3 8007eec: d3e2 bcc.n 8007eb4 } } return HAL_OK; 8007eee: 2300 movs r3, #0 } 8007ef0: 4618 mov r0, r3 8007ef2: 3724 adds r7, #36 @ 0x24 8007ef4: 46bd mov sp, r7 8007ef6: f85d 7b04 ldr.w r7, [sp], #4 8007efa: 4770 bx lr 08007efc : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 8007efc: b480 push {r7} 8007efe: b08b sub sp, #44 @ 0x2c 8007f00: af00 add r7, sp, #0 8007f02: 60f8 str r0, [r7, #12] 8007f04: 60b9 str r1, [r7, #8] 8007f06: 4613 mov r3, r2 8007f08: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 8007f0a: 68fb ldr r3, [r7, #12] 8007f0c: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 8007f0e: 68bb ldr r3, [r7, #8] 8007f10: 627b str r3, [r7, #36] @ 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 8007f12: 88fb ldrh r3, [r7, #6] 8007f14: 089b lsrs r3, r3, #2 8007f16: b29b uxth r3, r3 8007f18: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 8007f1a: 88fb ldrh r3, [r7, #6] 8007f1c: f003 0303 and.w r3, r3, #3 8007f20: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 8007f22: 2300 movs r3, #0 8007f24: 623b str r3, [r7, #32] 8007f26: e014 b.n 8007f52 { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 8007f28: 69bb ldr r3, [r7, #24] 8007f2a: f503 5380 add.w r3, r3, #4096 @ 0x1000 8007f2e: 681a ldr r2, [r3, #0] 8007f30: 6a7b ldr r3, [r7, #36] @ 0x24 8007f32: 601a str r2, [r3, #0] pDest++; 8007f34: 6a7b ldr r3, [r7, #36] @ 0x24 8007f36: 3301 adds r3, #1 8007f38: 627b str r3, [r7, #36] @ 0x24 pDest++; 8007f3a: 6a7b ldr r3, [r7, #36] @ 0x24 8007f3c: 3301 adds r3, #1 8007f3e: 627b str r3, [r7, #36] @ 0x24 pDest++; 8007f40: 6a7b ldr r3, [r7, #36] @ 0x24 8007f42: 3301 adds r3, #1 8007f44: 627b str r3, [r7, #36] @ 0x24 pDest++; 8007f46: 6a7b ldr r3, [r7, #36] @ 0x24 8007f48: 3301 adds r3, #1 8007f4a: 627b str r3, [r7, #36] @ 0x24 for (i = 0U; i < count32b; i++) 8007f4c: 6a3b ldr r3, [r7, #32] 8007f4e: 3301 adds r3, #1 8007f50: 623b str r3, [r7, #32] 8007f52: 6a3a ldr r2, [r7, #32] 8007f54: 697b ldr r3, [r7, #20] 8007f56: 429a cmp r2, r3 8007f58: d3e6 bcc.n 8007f28 } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 8007f5a: 8bfb ldrh r3, [r7, #30] 8007f5c: 2b00 cmp r3, #0 8007f5e: d01e beq.n 8007f9e { i = 0U; 8007f60: 2300 movs r3, #0 8007f62: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 8007f64: 69bb ldr r3, [r7, #24] 8007f66: f503 5380 add.w r3, r3, #4096 @ 0x1000 8007f6a: 461a mov r2, r3 8007f6c: f107 0310 add.w r3, r7, #16 8007f70: 6812 ldr r2, [r2, #0] 8007f72: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 8007f74: 693a ldr r2, [r7, #16] 8007f76: 6a3b ldr r3, [r7, #32] 8007f78: b2db uxtb r3, r3 8007f7a: 00db lsls r3, r3, #3 8007f7c: fa22 f303 lsr.w r3, r2, r3 8007f80: b2da uxtb r2, r3 8007f82: 6a7b ldr r3, [r7, #36] @ 0x24 8007f84: 701a strb r2, [r3, #0] i++; 8007f86: 6a3b ldr r3, [r7, #32] 8007f88: 3301 adds r3, #1 8007f8a: 623b str r3, [r7, #32] pDest++; 8007f8c: 6a7b ldr r3, [r7, #36] @ 0x24 8007f8e: 3301 adds r3, #1 8007f90: 627b str r3, [r7, #36] @ 0x24 remaining_bytes--; 8007f92: 8bfb ldrh r3, [r7, #30] 8007f94: 3b01 subs r3, #1 8007f96: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 8007f98: 8bfb ldrh r3, [r7, #30] 8007f9a: 2b00 cmp r3, #0 8007f9c: d1ea bne.n 8007f74 } return ((void *)pDest); 8007f9e: 6a7b ldr r3, [r7, #36] @ 0x24 } 8007fa0: 4618 mov r0, r3 8007fa2: 372c adds r7, #44 @ 0x2c 8007fa4: 46bd mov sp, r7 8007fa6: f85d 7b04 ldr.w r7, [sp], #4 8007faa: 4770 bx lr 08007fac : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007fac: b480 push {r7} 8007fae: b085 sub sp, #20 8007fb0: af00 add r7, sp, #0 8007fb2: 6078 str r0, [r7, #4] 8007fb4: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8007fb6: 687b ldr r3, [r7, #4] 8007fb8: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007fba: 683b ldr r3, [r7, #0] 8007fbc: 781b ldrb r3, [r3, #0] 8007fbe: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8007fc0: 683b ldr r3, [r7, #0] 8007fc2: 785b ldrb r3, [r3, #1] 8007fc4: 2b01 cmp r3, #1 8007fc6: d12c bne.n 8008022 { if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) 8007fc8: 68bb ldr r3, [r7, #8] 8007fca: 015a lsls r2, r3, #5 8007fcc: 68fb ldr r3, [r7, #12] 8007fce: 4413 add r3, r2 8007fd0: f503 6310 add.w r3, r3, #2304 @ 0x900 8007fd4: 681b ldr r3, [r3, #0] 8007fd6: 2b00 cmp r3, #0 8007fd8: db12 blt.n 8008000 8007fda: 68bb ldr r3, [r7, #8] 8007fdc: 2b00 cmp r3, #0 8007fde: d00f beq.n 8008000 { USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 8007fe0: 68bb ldr r3, [r7, #8] 8007fe2: 015a lsls r2, r3, #5 8007fe4: 68fb ldr r3, [r7, #12] 8007fe6: 4413 add r3, r2 8007fe8: f503 6310 add.w r3, r3, #2304 @ 0x900 8007fec: 681b ldr r3, [r3, #0] 8007fee: 68ba ldr r2, [r7, #8] 8007ff0: 0151 lsls r1, r2, #5 8007ff2: 68fa ldr r2, [r7, #12] 8007ff4: 440a add r2, r1 8007ff6: f502 6210 add.w r2, r2, #2304 @ 0x900 8007ffa: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8007ffe: 6013 str r3, [r2, #0] } USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 8008000: 68bb ldr r3, [r7, #8] 8008002: 015a lsls r2, r3, #5 8008004: 68fb ldr r3, [r7, #12] 8008006: 4413 add r3, r2 8008008: f503 6310 add.w r3, r3, #2304 @ 0x900 800800c: 681b ldr r3, [r3, #0] 800800e: 68ba ldr r2, [r7, #8] 8008010: 0151 lsls r1, r2, #5 8008012: 68fa ldr r2, [r7, #12] 8008014: 440a add r2, r1 8008016: f502 6210 add.w r2, r2, #2304 @ 0x900 800801a: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 800801e: 6013 str r3, [r2, #0] 8008020: e02b b.n 800807a } else { if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) 8008022: 68bb ldr r3, [r7, #8] 8008024: 015a lsls r2, r3, #5 8008026: 68fb ldr r3, [r7, #12] 8008028: 4413 add r3, r2 800802a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800802e: 681b ldr r3, [r3, #0] 8008030: 2b00 cmp r3, #0 8008032: db12 blt.n 800805a 8008034: 68bb ldr r3, [r7, #8] 8008036: 2b00 cmp r3, #0 8008038: d00f beq.n 800805a { USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 800803a: 68bb ldr r3, [r7, #8] 800803c: 015a lsls r2, r3, #5 800803e: 68fb ldr r3, [r7, #12] 8008040: 4413 add r3, r2 8008042: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008046: 681b ldr r3, [r3, #0] 8008048: 68ba ldr r2, [r7, #8] 800804a: 0151 lsls r1, r2, #5 800804c: 68fa ldr r2, [r7, #12] 800804e: 440a add r2, r1 8008050: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008054: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8008058: 6013 str r3, [r2, #0] } USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 800805a: 68bb ldr r3, [r7, #8] 800805c: 015a lsls r2, r3, #5 800805e: 68fb ldr r3, [r7, #12] 8008060: 4413 add r3, r2 8008062: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008066: 681b ldr r3, [r3, #0] 8008068: 68ba ldr r2, [r7, #8] 800806a: 0151 lsls r1, r2, #5 800806c: 68fa ldr r2, [r7, #12] 800806e: 440a add r2, r1 8008070: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008074: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8008078: 6013 str r3, [r2, #0] } return HAL_OK; 800807a: 2300 movs r3, #0 } 800807c: 4618 mov r0, r3 800807e: 3714 adds r7, #20 8008080: 46bd mov sp, r7 8008082: f85d 7b04 ldr.w r7, [sp], #4 8008086: 4770 bx lr 08008088 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8008088: b480 push {r7} 800808a: b085 sub sp, #20 800808c: af00 add r7, sp, #0 800808e: 6078 str r0, [r7, #4] 8008090: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8008092: 687b ldr r3, [r7, #4] 8008094: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8008096: 683b ldr r3, [r7, #0] 8008098: 781b ldrb r3, [r3, #0] 800809a: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 800809c: 683b ldr r3, [r7, #0] 800809e: 785b ldrb r3, [r3, #1] 80080a0: 2b01 cmp r3, #1 80080a2: d128 bne.n 80080f6 { USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 80080a4: 68bb ldr r3, [r7, #8] 80080a6: 015a lsls r2, r3, #5 80080a8: 68fb ldr r3, [r7, #12] 80080aa: 4413 add r3, r2 80080ac: f503 6310 add.w r3, r3, #2304 @ 0x900 80080b0: 681b ldr r3, [r3, #0] 80080b2: 68ba ldr r2, [r7, #8] 80080b4: 0151 lsls r1, r2, #5 80080b6: 68fa ldr r2, [r7, #12] 80080b8: 440a add r2, r1 80080ba: f502 6210 add.w r2, r2, #2304 @ 0x900 80080be: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 80080c2: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 80080c4: 683b ldr r3, [r7, #0] 80080c6: 791b ldrb r3, [r3, #4] 80080c8: 2b03 cmp r3, #3 80080ca: d003 beq.n 80080d4 80080cc: 683b ldr r3, [r7, #0] 80080ce: 791b ldrb r3, [r3, #4] 80080d0: 2b02 cmp r3, #2 80080d2: d138 bne.n 8008146 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 80080d4: 68bb ldr r3, [r7, #8] 80080d6: 015a lsls r2, r3, #5 80080d8: 68fb ldr r3, [r7, #12] 80080da: 4413 add r3, r2 80080dc: f503 6310 add.w r3, r3, #2304 @ 0x900 80080e0: 681b ldr r3, [r3, #0] 80080e2: 68ba ldr r2, [r7, #8] 80080e4: 0151 lsls r1, r2, #5 80080e6: 68fa ldr r2, [r7, #12] 80080e8: 440a add r2, r1 80080ea: f502 6210 add.w r2, r2, #2304 @ 0x900 80080ee: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80080f2: 6013 str r3, [r2, #0] 80080f4: e027 b.n 8008146 } } else { USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 80080f6: 68bb ldr r3, [r7, #8] 80080f8: 015a lsls r2, r3, #5 80080fa: 68fb ldr r3, [r7, #12] 80080fc: 4413 add r3, r2 80080fe: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008102: 681b ldr r3, [r3, #0] 8008104: 68ba ldr r2, [r7, #8] 8008106: 0151 lsls r1, r2, #5 8008108: 68fa ldr r2, [r7, #12] 800810a: 440a add r2, r1 800810c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008110: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8008114: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8008116: 683b ldr r3, [r7, #0] 8008118: 791b ldrb r3, [r3, #4] 800811a: 2b03 cmp r3, #3 800811c: d003 beq.n 8008126 800811e: 683b ldr r3, [r7, #0] 8008120: 791b ldrb r3, [r3, #4] 8008122: 2b02 cmp r3, #2 8008124: d10f bne.n 8008146 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8008126: 68bb ldr r3, [r7, #8] 8008128: 015a lsls r2, r3, #5 800812a: 68fb ldr r3, [r7, #12] 800812c: 4413 add r3, r2 800812e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008132: 681b ldr r3, [r3, #0] 8008134: 68ba ldr r2, [r7, #8] 8008136: 0151 lsls r1, r2, #5 8008138: 68fa ldr r2, [r7, #12] 800813a: 440a add r2, r1 800813c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008140: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008144: 6013 str r3, [r2, #0] } } return HAL_OK; 8008146: 2300 movs r3, #0 } 8008148: 4618 mov r0, r3 800814a: 3714 adds r7, #20 800814c: 46bd mov sp, r7 800814e: f85d 7b04 ldr.w r7, [sp], #4 8008152: 4770 bx lr 08008154 : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { 8008154: b480 push {r7} 8008156: b085 sub sp, #20 8008158: af00 add r7, sp, #0 800815a: 6078 str r0, [r7, #4] 800815c: 460b mov r3, r1 800815e: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008160: 687b ldr r3, [r7, #4] 8008162: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); 8008164: 68fb ldr r3, [r7, #12] 8008166: f503 6300 add.w r3, r3, #2048 @ 0x800 800816a: 681b ldr r3, [r3, #0] 800816c: 68fa ldr r2, [r7, #12] 800816e: f502 6200 add.w r2, r2, #2048 @ 0x800 8008172: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 8008176: 6013 str r3, [r2, #0] USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; 8008178: 68fb ldr r3, [r7, #12] 800817a: f503 6300 add.w r3, r3, #2048 @ 0x800 800817e: 681a ldr r2, [r3, #0] 8008180: 78fb ldrb r3, [r7, #3] 8008182: 011b lsls r3, r3, #4 8008184: f403 63fe and.w r3, r3, #2032 @ 0x7f0 8008188: 68f9 ldr r1, [r7, #12] 800818a: f501 6100 add.w r1, r1, #2048 @ 0x800 800818e: 4313 orrs r3, r2 8008190: 600b str r3, [r1, #0] return HAL_OK; 8008192: 2300 movs r3, #0 } 8008194: 4618 mov r0, r3 8008196: 3714 adds r7, #20 8008198: 46bd mov sp, r7 800819a: f85d 7b04 ldr.w r7, [sp], #4 800819e: 4770 bx lr 080081a0 : * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { 80081a0: b480 push {r7} 80081a2: b085 sub sp, #20 80081a4: af00 add r7, sp, #0 80081a6: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80081a8: 687b ldr r3, [r7, #4] 80081aa: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 80081ac: 68fb ldr r3, [r7, #12] 80081ae: f503 6360 add.w r3, r3, #3584 @ 0xe00 80081b2: 681b ldr r3, [r3, #0] 80081b4: 68fa ldr r2, [r7, #12] 80081b6: f502 6260 add.w r2, r2, #3584 @ 0xe00 80081ba: f023 0303 bic.w r3, r3, #3 80081be: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; 80081c0: 68fb ldr r3, [r7, #12] 80081c2: f503 6300 add.w r3, r3, #2048 @ 0x800 80081c6: 685b ldr r3, [r3, #4] 80081c8: 68fa ldr r2, [r7, #12] 80081ca: f502 6200 add.w r2, r2, #2048 @ 0x800 80081ce: f023 0302 bic.w r3, r3, #2 80081d2: 6053 str r3, [r2, #4] return HAL_OK; 80081d4: 2300 movs r3, #0 } 80081d6: 4618 mov r0, r3 80081d8: 3714 adds r7, #20 80081da: 46bd mov sp, r7 80081dc: f85d 7b04 ldr.w r7, [sp], #4 80081e0: 4770 bx lr 080081e2 : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { 80081e2: b480 push {r7} 80081e4: b085 sub sp, #20 80081e6: af00 add r7, sp, #0 80081e8: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80081ea: 687b ldr r3, [r7, #4] 80081ec: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 80081ee: 68fb ldr r3, [r7, #12] 80081f0: f503 6360 add.w r3, r3, #3584 @ 0xe00 80081f4: 681b ldr r3, [r3, #0] 80081f6: 68fa ldr r2, [r7, #12] 80081f8: f502 6260 add.w r2, r2, #3584 @ 0xe00 80081fc: f023 0303 bic.w r3, r3, #3 8008200: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8008202: 68fb ldr r3, [r7, #12] 8008204: f503 6300 add.w r3, r3, #2048 @ 0x800 8008208: 685b ldr r3, [r3, #4] 800820a: 68fa ldr r2, [r7, #12] 800820c: f502 6200 add.w r2, r2, #2048 @ 0x800 8008210: f043 0302 orr.w r3, r3, #2 8008214: 6053 str r3, [r2, #4] return HAL_OK; 8008216: 2300 movs r3, #0 } 8008218: 4618 mov r0, r3 800821a: 3714 adds r7, #20 800821c: 46bd mov sp, r7 800821e: f85d 7b04 ldr.w r7, [sp], #4 8008222: 4770 bx lr 08008224 : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { 8008224: b480 push {r7} 8008226: b085 sub sp, #20 8008228: af00 add r7, sp, #0 800822a: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 800822c: 687b ldr r3, [r7, #4] 800822e: 695b ldr r3, [r3, #20] 8008230: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 8008232: 687b ldr r3, [r7, #4] 8008234: 699b ldr r3, [r3, #24] 8008236: 68fa ldr r2, [r7, #12] 8008238: 4013 ands r3, r2 800823a: 60fb str r3, [r7, #12] return tmpreg; 800823c: 68fb ldr r3, [r7, #12] } 800823e: 4618 mov r0, r3 8008240: 3714 adds r7, #20 8008242: 46bd mov sp, r7 8008244: f85d 7b04 ldr.w r7, [sp], #4 8008248: 4770 bx lr 0800824a : * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device * @retval USB Device OUT EP interrupt status */ uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 800824a: b480 push {r7} 800824c: b085 sub sp, #20 800824e: af00 add r7, sp, #0 8008250: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008252: 687b ldr r3, [r7, #4] 8008254: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8008256: 68fb ldr r3, [r7, #12] 8008258: f503 6300 add.w r3, r3, #2048 @ 0x800 800825c: 699b ldr r3, [r3, #24] 800825e: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 8008260: 68fb ldr r3, [r7, #12] 8008262: f503 6300 add.w r3, r3, #2048 @ 0x800 8008266: 69db ldr r3, [r3, #28] 8008268: 68ba ldr r2, [r7, #8] 800826a: 4013 ands r3, r2 800826c: 60bb str r3, [r7, #8] return ((tmpreg & 0xffff0000U) >> 16); 800826e: 68bb ldr r3, [r7, #8] 8008270: 0c1b lsrs r3, r3, #16 } 8008272: 4618 mov r0, r3 8008274: 3714 adds r7, #20 8008276: 46bd mov sp, r7 8008278: f85d 7b04 ldr.w r7, [sp], #4 800827c: 4770 bx lr 0800827e : * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device * @retval USB Device IN EP interrupt status */ uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 800827e: b480 push {r7} 8008280: b085 sub sp, #20 8008282: af00 add r7, sp, #0 8008284: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008286: 687b ldr r3, [r7, #4] 8008288: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 800828a: 68fb ldr r3, [r7, #12] 800828c: f503 6300 add.w r3, r3, #2048 @ 0x800 8008290: 699b ldr r3, [r3, #24] 8008292: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 8008294: 68fb ldr r3, [r7, #12] 8008296: f503 6300 add.w r3, r3, #2048 @ 0x800 800829a: 69db ldr r3, [r3, #28] 800829c: 68ba ldr r2, [r7, #8] 800829e: 4013 ands r3, r2 80082a0: 60bb str r3, [r7, #8] return ((tmpreg & 0xFFFFU)); 80082a2: 68bb ldr r3, [r7, #8] 80082a4: b29b uxth r3, r3 } 80082a6: 4618 mov r0, r3 80082a8: 3714 adds r7, #20 80082aa: 46bd mov sp, r7 80082ac: f85d 7b04 ldr.w r7, [sp], #4 80082b0: 4770 bx lr 080082b2 : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 80082b2: b480 push {r7} 80082b4: b085 sub sp, #20 80082b6: af00 add r7, sp, #0 80082b8: 6078 str r0, [r7, #4] 80082ba: 460b mov r3, r1 80082bc: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80082be: 687b ldr r3, [r7, #4] 80082c0: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; 80082c2: 78fb ldrb r3, [r7, #3] 80082c4: 015a lsls r2, r3, #5 80082c6: 68fb ldr r3, [r7, #12] 80082c8: 4413 add r3, r2 80082ca: f503 6330 add.w r3, r3, #2816 @ 0xb00 80082ce: 689b ldr r3, [r3, #8] 80082d0: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DOEPMSK; 80082d2: 68fb ldr r3, [r7, #12] 80082d4: f503 6300 add.w r3, r3, #2048 @ 0x800 80082d8: 695b ldr r3, [r3, #20] 80082da: 68ba ldr r2, [r7, #8] 80082dc: 4013 ands r3, r2 80082de: 60bb str r3, [r7, #8] return tmpreg; 80082e0: 68bb ldr r3, [r7, #8] } 80082e2: 4618 mov r0, r3 80082e4: 3714 adds r7, #20 80082e6: 46bd mov sp, r7 80082e8: f85d 7b04 ldr.w r7, [sp], #4 80082ec: 4770 bx lr 080082ee : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 80082ee: b480 push {r7} 80082f0: b087 sub sp, #28 80082f2: af00 add r7, sp, #0 80082f4: 6078 str r0, [r7, #4] 80082f6: 460b mov r3, r1 80082f8: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80082fa: 687b ldr r3, [r7, #4] 80082fc: 617b str r3, [r7, #20] uint32_t tmpreg; uint32_t msk; uint32_t emp; msk = USBx_DEVICE->DIEPMSK; 80082fe: 697b ldr r3, [r7, #20] 8008300: f503 6300 add.w r3, r3, #2048 @ 0x800 8008304: 691b ldr r3, [r3, #16] 8008306: 613b str r3, [r7, #16] emp = USBx_DEVICE->DIEPEMPMSK; 8008308: 697b ldr r3, [r7, #20] 800830a: f503 6300 add.w r3, r3, #2048 @ 0x800 800830e: 6b5b ldr r3, [r3, #52] @ 0x34 8008310: 60fb str r3, [r7, #12] msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; 8008312: 78fb ldrb r3, [r7, #3] 8008314: f003 030f and.w r3, r3, #15 8008318: 68fa ldr r2, [r7, #12] 800831a: fa22 f303 lsr.w r3, r2, r3 800831e: 01db lsls r3, r3, #7 8008320: b2db uxtb r3, r3 8008322: 693a ldr r2, [r7, #16] 8008324: 4313 orrs r3, r2 8008326: 613b str r3, [r7, #16] tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; 8008328: 78fb ldrb r3, [r7, #3] 800832a: 015a lsls r2, r3, #5 800832c: 697b ldr r3, [r7, #20] 800832e: 4413 add r3, r2 8008330: f503 6310 add.w r3, r3, #2304 @ 0x900 8008334: 689b ldr r3, [r3, #8] 8008336: 693a ldr r2, [r7, #16] 8008338: 4013 ands r3, r2 800833a: 60bb str r3, [r7, #8] return tmpreg; 800833c: 68bb ldr r3, [r7, #8] } 800833e: 4618 mov r0, r3 8008340: 371c adds r7, #28 8008342: 46bd mov sp, r7 8008344: f85d 7b04 ldr.w r7, [sp], #4 8008348: 4770 bx lr 0800834a : * This parameter can be one of these values: * 1 : Host * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { 800834a: b480 push {r7} 800834c: b083 sub sp, #12 800834e: af00 add r7, sp, #0 8008350: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 8008352: 687b ldr r3, [r7, #4] 8008354: 695b ldr r3, [r3, #20] 8008356: f003 0301 and.w r3, r3, #1 } 800835a: 4618 mov r0, r3 800835c: 370c adds r7, #12 800835e: 46bd mov sp, r7 8008360: f85d 7b04 ldr.w r7, [sp], #4 8008364: 4770 bx lr 08008366 : * @brief Activate EP0 for Setup transactions * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { 8008366: b480 push {r7} 8008368: b085 sub sp, #20 800836a: af00 add r7, sp, #0 800836c: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800836e: 687b ldr r3, [r7, #4] 8008370: 60fb str r3, [r7, #12] /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 8008372: 68fb ldr r3, [r7, #12] 8008374: f503 6310 add.w r3, r3, #2304 @ 0x900 8008378: 681b ldr r3, [r3, #0] 800837a: 68fa ldr r2, [r7, #12] 800837c: f502 6210 add.w r2, r2, #2304 @ 0x900 8008380: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 8008384: f023 0307 bic.w r3, r3, #7 8008388: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 800838a: 68fb ldr r3, [r7, #12] 800838c: f503 6300 add.w r3, r3, #2048 @ 0x800 8008390: 685b ldr r3, [r3, #4] 8008392: 68fa ldr r2, [r7, #12] 8008394: f502 6200 add.w r2, r2, #2048 @ 0x800 8008398: f443 7380 orr.w r3, r3, #256 @ 0x100 800839c: 6053 str r3, [r2, #4] return HAL_OK; 800839e: 2300 movs r3, #0 } 80083a0: 4618 mov r0, r3 80083a2: 3714 adds r7, #20 80083a4: 46bd mov sp, r7 80083a6: f85d 7b04 ldr.w r7, [sp], #4 80083aa: 4770 bx lr 080083ac : * 1 : DMA feature used * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { 80083ac: b480 push {r7} 80083ae: b087 sub sp, #28 80083b0: af00 add r7, sp, #0 80083b2: 60f8 str r0, [r7, #12] 80083b4: 460b mov r3, r1 80083b6: 607a str r2, [r7, #4] 80083b8: 72fb strb r3, [r7, #11] uint32_t USBx_BASE = (uint32_t)USBx; 80083ba: 68fb ldr r3, [r7, #12] 80083bc: 617b str r3, [r7, #20] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 80083be: 68fb ldr r3, [r7, #12] 80083c0: 333c adds r3, #60 @ 0x3c 80083c2: 3304 adds r3, #4 80083c4: 681b ldr r3, [r3, #0] 80083c6: 613b str r3, [r7, #16] if (gSNPSiD > USB_OTG_CORE_ID_300A) 80083c8: 693b ldr r3, [r7, #16] 80083ca: 4a26 ldr r2, [pc, #152] @ (8008464 ) 80083cc: 4293 cmp r3, r2 80083ce: d90a bls.n 80083e6 { if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80083d0: 697b ldr r3, [r7, #20] 80083d2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80083d6: 681b ldr r3, [r3, #0] 80083d8: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80083dc: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80083e0: d101 bne.n 80083e6 { return HAL_OK; 80083e2: 2300 movs r3, #0 80083e4: e037 b.n 8008456 } } USBx_OUTEP(0U)->DOEPTSIZ = 0U; 80083e6: 697b ldr r3, [r7, #20] 80083e8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80083ec: 461a mov r2, r3 80083ee: 2300 movs r3, #0 80083f0: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 80083f2: 697b ldr r3, [r7, #20] 80083f4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80083f8: 691b ldr r3, [r3, #16] 80083fa: 697a ldr r2, [r7, #20] 80083fc: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008400: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8008404: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); 8008406: 697b ldr r3, [r7, #20] 8008408: f503 6330 add.w r3, r3, #2816 @ 0xb00 800840c: 691b ldr r3, [r3, #16] 800840e: 697a ldr r2, [r7, #20] 8008410: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008414: f043 0318 orr.w r3, r3, #24 8008418: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 800841a: 697b ldr r3, [r7, #20] 800841c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008420: 691b ldr r3, [r3, #16] 8008422: 697a ldr r2, [r7, #20] 8008424: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008428: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000 800842c: 6113 str r3, [r2, #16] if (dma == 1U) 800842e: 7afb ldrb r3, [r7, #11] 8008430: 2b01 cmp r3, #1 8008432: d10f bne.n 8008454 { USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; 8008434: 697b ldr r3, [r7, #20] 8008436: f503 6330 add.w r3, r3, #2816 @ 0xb00 800843a: 461a mov r2, r3 800843c: 687b ldr r3, [r7, #4] 800843e: 6153 str r3, [r2, #20] /* EP enable */ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; 8008440: 697b ldr r3, [r7, #20] 8008442: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008446: 681b ldr r3, [r3, #0] 8008448: 697a ldr r2, [r7, #20] 800844a: f502 6230 add.w r2, r2, #2816 @ 0xb00 800844e: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000 8008452: 6013 str r3, [r2, #0] } return HAL_OK; 8008454: 2300 movs r3, #0 } 8008456: 4618 mov r0, r3 8008458: 371c adds r7, #28 800845a: 46bd mov sp, r7 800845c: f85d 7b04 ldr.w r7, [sp], #4 8008460: 4770 bx lr 8008462: bf00 nop 8008464: 4f54300a .word 0x4f54300a 08008468 : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 8008468: b480 push {r7} 800846a: b085 sub sp, #20 800846c: af00 add r7, sp, #0 800846e: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8008470: 2300 movs r3, #0 8008472: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8008474: 68fb ldr r3, [r7, #12] 8008476: 3301 adds r3, #1 8008478: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800847a: 68fb ldr r3, [r7, #12] 800847c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8008480: d901 bls.n 8008486 { return HAL_TIMEOUT; 8008482: 2303 movs r3, #3 8008484: e022 b.n 80084cc } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8008486: 687b ldr r3, [r7, #4] 8008488: 691b ldr r3, [r3, #16] 800848a: 2b00 cmp r3, #0 800848c: daf2 bge.n 8008474 count = 10U; 800848e: 230a movs r3, #10 8008490: 60fb str r3, [r7, #12] /* few cycles before setting core reset */ while (count > 0U) 8008492: e002 b.n 800849a { count--; 8008494: 68fb ldr r3, [r7, #12] 8008496: 3b01 subs r3, #1 8008498: 60fb str r3, [r7, #12] while (count > 0U) 800849a: 68fb ldr r3, [r7, #12] 800849c: 2b00 cmp r3, #0 800849e: d1f9 bne.n 8008494 } /* Core Soft Reset */ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 80084a0: 687b ldr r3, [r7, #4] 80084a2: 691b ldr r3, [r3, #16] 80084a4: f043 0201 orr.w r2, r3, #1 80084a8: 687b ldr r3, [r7, #4] 80084aa: 611a str r2, [r3, #16] do { count++; 80084ac: 68fb ldr r3, [r7, #12] 80084ae: 3301 adds r3, #1 80084b0: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80084b2: 68fb ldr r3, [r7, #12] 80084b4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80084b8: d901 bls.n 80084be { return HAL_TIMEOUT; 80084ba: 2303 movs r3, #3 80084bc: e006 b.n 80084cc } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 80084be: 687b ldr r3, [r7, #4] 80084c0: 691b ldr r3, [r3, #16] 80084c2: f003 0301 and.w r3, r3, #1 80084c6: 2b01 cmp r3, #1 80084c8: d0f0 beq.n 80084ac return HAL_OK; 80084ca: 2300 movs r3, #0 } 80084cc: 4618 mov r0, r3 80084ce: 3714 adds r7, #20 80084d0: 46bd mov sp, r7 80084d2: f85d 7b04 ldr.w r7, [sp], #4 80084d6: 4770 bx lr 080084d8 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80084d8: b580 push {r7, lr} 80084da: b084 sub sp, #16 80084dc: af00 add r7, sp, #0 80084de: 6078 str r0, [r7, #4] 80084e0: 460b mov r3, r1 80084e2: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_HID_HandleTypeDef *hhid; hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); 80084e4: 2010 movs r0, #16 80084e6: f002 f9e3 bl 800a8b0 80084ea: 60f8 str r0, [r7, #12] if (hhid == NULL) 80084ec: 68fb ldr r3, [r7, #12] 80084ee: 2b00 cmp r3, #0 80084f0: d109 bne.n 8008506 { pdev->pClassDataCmsit[pdev->classId] = NULL; 80084f2: 687b ldr r3, [r7, #4] 80084f4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80084f8: 687b ldr r3, [r7, #4] 80084fa: 32b0 adds r2, #176 @ 0xb0 80084fc: 2100 movs r1, #0 80084fe: f843 1022 str.w r1, [r3, r2, lsl #2] return (uint8_t)USBD_EMEM; 8008502: 2302 movs r3, #2 8008504: e048 b.n 8008598 } pdev->pClassDataCmsit[pdev->classId] = (void *)hhid; 8008506: 687b ldr r3, [r7, #4] 8008508: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800850c: 687b ldr r3, [r7, #4] 800850e: 32b0 adds r2, #176 @ 0xb0 8008510: 68f9 ldr r1, [r7, #12] 8008512: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; 8008516: 687b ldr r3, [r7, #4] 8008518: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800851c: 687b ldr r3, [r7, #4] 800851e: 32b0 adds r2, #176 @ 0xb0 8008520: f853 2022 ldr.w r2, [r3, r2, lsl #2] 8008524: 687b ldr r3, [r7, #4] 8008526: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_speed == USBD_SPEED_HIGH) 800852a: 687b ldr r3, [r7, #4] 800852c: 7c1b ldrb r3, [r3, #16] 800852e: 2b00 cmp r3, #0 8008530: d10d bne.n 800854e { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL; 8008532: 4b1b ldr r3, [pc, #108] @ (80085a0 ) 8008534: 781b ldrb r3, [r3, #0] 8008536: f003 020f and.w r2, r3, #15 800853a: 6879 ldr r1, [r7, #4] 800853c: 4613 mov r3, r2 800853e: 009b lsls r3, r3, #2 8008540: 4413 add r3, r2 8008542: 009b lsls r3, r3, #2 8008544: 440b add r3, r1 8008546: 331c adds r3, #28 8008548: 2207 movs r2, #7 800854a: 601a str r2, [r3, #0] 800854c: e00c b.n 8008568 } else /* LOW and FULL-speed endpoints */ { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL; 800854e: 4b14 ldr r3, [pc, #80] @ (80085a0 ) 8008550: 781b ldrb r3, [r3, #0] 8008552: f003 020f and.w r2, r3, #15 8008556: 6879 ldr r1, [r7, #4] 8008558: 4613 mov r3, r2 800855a: 009b lsls r3, r3, #2 800855c: 4413 add r3, r2 800855e: 009b lsls r3, r3, #2 8008560: 440b add r3, r1 8008562: 331c adds r3, #28 8008564: 220a movs r2, #10 8008566: 601a str r2, [r3, #0] } /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); 8008568: 4b0d ldr r3, [pc, #52] @ (80085a0 ) 800856a: 7819 ldrb r1, [r3, #0] 800856c: 230e movs r3, #14 800856e: 2203 movs r2, #3 8008570: 6878 ldr r0, [r7, #4] 8008572: f002 f83e bl 800a5f2 pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U; 8008576: 4b0a ldr r3, [pc, #40] @ (80085a0 ) 8008578: 781b ldrb r3, [r3, #0] 800857a: f003 020f and.w r2, r3, #15 800857e: 6879 ldr r1, [r7, #4] 8008580: 4613 mov r3, r2 8008582: 009b lsls r3, r3, #2 8008584: 4413 add r3, r2 8008586: 009b lsls r3, r3, #2 8008588: 440b add r3, r1 800858a: 3323 adds r3, #35 @ 0x23 800858c: 2201 movs r2, #1 800858e: 701a strb r2, [r3, #0] hhid->state = USBD_HID_IDLE; 8008590: 68fb ldr r3, [r7, #12] 8008592: 2200 movs r2, #0 8008594: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 8008596: 2300 movs r3, #0 } 8008598: 4618 mov r0, r3 800859a: 3710 adds r7, #16 800859c: 46bd mov sp, r7 800859e: bd80 pop {r7, pc} 80085a0: 2000013d .word 0x2000013d 080085a4 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80085a4: b580 push {r7, lr} 80085a6: b082 sub sp, #8 80085a8: af00 add r7, sp, #0 80085aa: 6078 str r0, [r7, #4] 80085ac: 460b mov r3, r1 80085ae: 70fb strb r3, [r7, #3] /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ /* Close HID EPs */ (void)USBD_LL_CloseEP(pdev, HIDInEpAdd); 80085b0: 4b1f ldr r3, [pc, #124] @ (8008630 ) 80085b2: 781b ldrb r3, [r3, #0] 80085b4: 4619 mov r1, r3 80085b6: 6878 ldr r0, [r7, #4] 80085b8: f002 f841 bl 800a63e pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U; 80085bc: 4b1c ldr r3, [pc, #112] @ (8008630 ) 80085be: 781b ldrb r3, [r3, #0] 80085c0: f003 020f and.w r2, r3, #15 80085c4: 6879 ldr r1, [r7, #4] 80085c6: 4613 mov r3, r2 80085c8: 009b lsls r3, r3, #2 80085ca: 4413 add r3, r2 80085cc: 009b lsls r3, r3, #2 80085ce: 440b add r3, r1 80085d0: 3323 adds r3, #35 @ 0x23 80085d2: 2200 movs r2, #0 80085d4: 701a strb r2, [r3, #0] pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U; 80085d6: 4b16 ldr r3, [pc, #88] @ (8008630 ) 80085d8: 781b ldrb r3, [r3, #0] 80085da: f003 020f and.w r2, r3, #15 80085de: 6879 ldr r1, [r7, #4] 80085e0: 4613 mov r3, r2 80085e2: 009b lsls r3, r3, #2 80085e4: 4413 add r3, r2 80085e6: 009b lsls r3, r3, #2 80085e8: 440b add r3, r1 80085ea: 331c adds r3, #28 80085ec: 2200 movs r2, #0 80085ee: 601a str r2, [r3, #0] /* Free allocated memory */ if (pdev->pClassDataCmsit[pdev->classId] != NULL) 80085f0: 687b ldr r3, [r7, #4] 80085f2: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80085f6: 687b ldr r3, [r7, #4] 80085f8: 32b0 adds r2, #176 @ 0xb0 80085fa: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80085fe: 2b00 cmp r3, #0 8008600: d011 beq.n 8008626 { (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); 8008602: 687b ldr r3, [r7, #4] 8008604: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008608: 687b ldr r3, [r7, #4] 800860a: 32b0 adds r2, #176 @ 0xb0 800860c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008610: 4618 mov r0, r3 8008612: f002 f95b bl 800a8cc pdev->pClassDataCmsit[pdev->classId] = NULL; 8008616: 687b ldr r3, [r7, #4] 8008618: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800861c: 687b ldr r3, [r7, #4] 800861e: 32b0 adds r2, #176 @ 0xb0 8008620: 2100 movs r1, #0 8008622: f843 1022 str.w r1, [r3, r2, lsl #2] } return (uint8_t)USBD_OK; 8008626: 2300 movs r3, #0 } 8008628: 4618 mov r0, r3 800862a: 3708 adds r7, #8 800862c: 46bd mov sp, r7 800862e: bd80 pop {r7, pc} 8008630: 2000013d .word 0x2000013d 08008634 : * @param pdev: instance * @param req: usb requests * @retval status */ static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008634: b580 push {r7, lr} 8008636: b086 sub sp, #24 8008638: af00 add r7, sp, #0 800863a: 6078 str r0, [r7, #4] 800863c: 6039 str r1, [r7, #0] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 800863e: 687b ldr r3, [r7, #4] 8008640: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008644: 687b ldr r3, [r7, #4] 8008646: 32b0 adds r2, #176 @ 0xb0 8008648: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800864c: 60fb str r3, [r7, #12] USBD_StatusTypeDef ret = USBD_OK; 800864e: 2300 movs r3, #0 8008650: 75fb strb r3, [r7, #23] uint16_t len; uint8_t *pbuf; uint16_t status_info = 0U; 8008652: 2300 movs r3, #0 8008654: 817b strh r3, [r7, #10] if (hhid == NULL) 8008656: 68fb ldr r3, [r7, #12] 8008658: 2b00 cmp r3, #0 800865a: d101 bne.n 8008660 { return (uint8_t)USBD_FAIL; 800865c: 2303 movs r3, #3 800865e: e0e8 b.n 8008832 } switch (req->bmRequest & USB_REQ_TYPE_MASK) 8008660: 683b ldr r3, [r7, #0] 8008662: 781b ldrb r3, [r3, #0] 8008664: f003 0360 and.w r3, r3, #96 @ 0x60 8008668: 2b00 cmp r3, #0 800866a: d046 beq.n 80086fa 800866c: 2b20 cmp r3, #32 800866e: f040 80d8 bne.w 8008822 { case USB_REQ_TYPE_CLASS : switch (req->bRequest) 8008672: 683b ldr r3, [r7, #0] 8008674: 785b ldrb r3, [r3, #1] 8008676: 3b02 subs r3, #2 8008678: 2b09 cmp r3, #9 800867a: d836 bhi.n 80086ea 800867c: a201 add r2, pc, #4 @ (adr r2, 8008684 ) 800867e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008682: bf00 nop 8008684: 080086db .word 0x080086db 8008688: 080086bb .word 0x080086bb 800868c: 080086eb .word 0x080086eb 8008690: 080086eb .word 0x080086eb 8008694: 080086eb .word 0x080086eb 8008698: 080086eb .word 0x080086eb 800869c: 080086eb .word 0x080086eb 80086a0: 080086eb .word 0x080086eb 80086a4: 080086c9 .word 0x080086c9 80086a8: 080086ad .word 0x080086ad { case USBD_HID_REQ_SET_PROTOCOL: hhid->Protocol = (uint8_t)(req->wValue); 80086ac: 683b ldr r3, [r7, #0] 80086ae: 885b ldrh r3, [r3, #2] 80086b0: b2db uxtb r3, r3 80086b2: 461a mov r2, r3 80086b4: 68fb ldr r3, [r7, #12] 80086b6: 601a str r2, [r3, #0] break; 80086b8: e01e b.n 80086f8 case USBD_HID_REQ_GET_PROTOCOL: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); 80086ba: 68fb ldr r3, [r7, #12] 80086bc: 2201 movs r2, #1 80086be: 4619 mov r1, r3 80086c0: 6878 ldr r0, [r7, #4] 80086c2: f001 fc25 bl 8009f10 break; 80086c6: e017 b.n 80086f8 case USBD_HID_REQ_SET_IDLE: hhid->IdleState = (uint8_t)(req->wValue >> 8); 80086c8: 683b ldr r3, [r7, #0] 80086ca: 885b ldrh r3, [r3, #2] 80086cc: 0a1b lsrs r3, r3, #8 80086ce: b29b uxth r3, r3 80086d0: b2db uxtb r3, r3 80086d2: 461a mov r2, r3 80086d4: 68fb ldr r3, [r7, #12] 80086d6: 605a str r2, [r3, #4] break; 80086d8: e00e b.n 80086f8 case USBD_HID_REQ_GET_IDLE: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); 80086da: 68fb ldr r3, [r7, #12] 80086dc: 3304 adds r3, #4 80086de: 2201 movs r2, #1 80086e0: 4619 mov r1, r3 80086e2: 6878 ldr r0, [r7, #4] 80086e4: f001 fc14 bl 8009f10 break; 80086e8: e006 b.n 80086f8 default: USBD_CtlError(pdev, req); 80086ea: 6839 ldr r1, [r7, #0] 80086ec: 6878 ldr r0, [r7, #4] 80086ee: f001 fb92 bl 8009e16 ret = USBD_FAIL; 80086f2: 2303 movs r3, #3 80086f4: 75fb strb r3, [r7, #23] break; 80086f6: bf00 nop } break; 80086f8: e09a b.n 8008830 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80086fa: 683b ldr r3, [r7, #0] 80086fc: 785b ldrb r3, [r3, #1] 80086fe: 2b0b cmp r3, #11 8008700: f200 8086 bhi.w 8008810 8008704: a201 add r2, pc, #4 @ (adr r2, 800870c ) 8008706: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800870a: bf00 nop 800870c: 0800873d .word 0x0800873d 8008710: 0800881f .word 0x0800881f 8008714: 08008811 .word 0x08008811 8008718: 08008811 .word 0x08008811 800871c: 08008811 .word 0x08008811 8008720: 08008811 .word 0x08008811 8008724: 08008767 .word 0x08008767 8008728: 08008811 .word 0x08008811 800872c: 08008811 .word 0x08008811 8008730: 08008811 .word 0x08008811 8008734: 080087bf .word 0x080087bf 8008738: 080087e9 .word 0x080087e9 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 800873c: 687b ldr r3, [r7, #4] 800873e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008742: b2db uxtb r3, r3 8008744: 2b03 cmp r3, #3 8008746: d107 bne.n 8008758 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 8008748: f107 030a add.w r3, r7, #10 800874c: 2202 movs r2, #2 800874e: 4619 mov r1, r3 8008750: 6878 ldr r0, [r7, #4] 8008752: f001 fbdd bl 8009f10 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8008756: e063 b.n 8008820 USBD_CtlError(pdev, req); 8008758: 6839 ldr r1, [r7, #0] 800875a: 6878 ldr r0, [r7, #4] 800875c: f001 fb5b bl 8009e16 ret = USBD_FAIL; 8008760: 2303 movs r3, #3 8008762: 75fb strb r3, [r7, #23] break; 8008764: e05c b.n 8008820 case USB_REQ_GET_DESCRIPTOR: if ((req->wValue >> 8) == HID_REPORT_DESC) 8008766: 683b ldr r3, [r7, #0] 8008768: 885b ldrh r3, [r3, #2] 800876a: 0a1b lsrs r3, r3, #8 800876c: b29b uxth r3, r3 800876e: 2b22 cmp r3, #34 @ 0x22 8008770: d108 bne.n 8008784 { len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); 8008772: 683b ldr r3, [r7, #0] 8008774: 88db ldrh r3, [r3, #6] 8008776: 2b2d cmp r3, #45 @ 0x2d 8008778: bf28 it cs 800877a: 232d movcs r3, #45 @ 0x2d 800877c: 82bb strh r3, [r7, #20] pbuf = HID_MOUSE_ReportDesc; 800877e: 4b2f ldr r3, [pc, #188] @ (800883c ) 8008780: 613b str r3, [r7, #16] 8008782: e015 b.n 80087b0 } else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) 8008784: 683b ldr r3, [r7, #0] 8008786: 885b ldrh r3, [r3, #2] 8008788: 0a1b lsrs r3, r3, #8 800878a: b29b uxth r3, r3 800878c: 2b21 cmp r3, #33 @ 0x21 800878e: d108 bne.n 80087a2 { pbuf = USBD_HID_Desc; 8008790: 4b2b ldr r3, [pc, #172] @ (8008840 ) 8008792: 613b str r3, [r7, #16] len = MIN(USB_HID_DESC_SIZ, req->wLength); 8008794: 683b ldr r3, [r7, #0] 8008796: 88db ldrh r3, [r3, #6] 8008798: 2b09 cmp r3, #9 800879a: bf28 it cs 800879c: 2309 movcs r3, #9 800879e: 82bb strh r3, [r7, #20] 80087a0: e006 b.n 80087b0 } else { USBD_CtlError(pdev, req); 80087a2: 6839 ldr r1, [r7, #0] 80087a4: 6878 ldr r0, [r7, #4] 80087a6: f001 fb36 bl 8009e16 ret = USBD_FAIL; 80087aa: 2303 movs r3, #3 80087ac: 75fb strb r3, [r7, #23] break; 80087ae: e037 b.n 8008820 } (void)USBD_CtlSendData(pdev, pbuf, len); 80087b0: 8abb ldrh r3, [r7, #20] 80087b2: 461a mov r2, r3 80087b4: 6939 ldr r1, [r7, #16] 80087b6: 6878 ldr r0, [r7, #4] 80087b8: f001 fbaa bl 8009f10 break; 80087bc: e030 b.n 8008820 case USB_REQ_GET_INTERFACE : if (pdev->dev_state == USBD_STATE_CONFIGURED) 80087be: 687b ldr r3, [r7, #4] 80087c0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80087c4: b2db uxtb r3, r3 80087c6: 2b03 cmp r3, #3 80087c8: d107 bne.n 80087da { (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); 80087ca: 68fb ldr r3, [r7, #12] 80087cc: 3308 adds r3, #8 80087ce: 2201 movs r2, #1 80087d0: 4619 mov r1, r3 80087d2: 6878 ldr r0, [r7, #4] 80087d4: f001 fb9c bl 8009f10 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 80087d8: e022 b.n 8008820 USBD_CtlError(pdev, req); 80087da: 6839 ldr r1, [r7, #0] 80087dc: 6878 ldr r0, [r7, #4] 80087de: f001 fb1a bl 8009e16 ret = USBD_FAIL; 80087e2: 2303 movs r3, #3 80087e4: 75fb strb r3, [r7, #23] break; 80087e6: e01b b.n 8008820 case USB_REQ_SET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 80087e8: 687b ldr r3, [r7, #4] 80087ea: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80087ee: b2db uxtb r3, r3 80087f0: 2b03 cmp r3, #3 80087f2: d106 bne.n 8008802 { hhid->AltSetting = (uint8_t)(req->wValue); 80087f4: 683b ldr r3, [r7, #0] 80087f6: 885b ldrh r3, [r3, #2] 80087f8: b2db uxtb r3, r3 80087fa: 461a mov r2, r3 80087fc: 68fb ldr r3, [r7, #12] 80087fe: 609a str r2, [r3, #8] else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8008800: e00e b.n 8008820 USBD_CtlError(pdev, req); 8008802: 6839 ldr r1, [r7, #0] 8008804: 6878 ldr r0, [r7, #4] 8008806: f001 fb06 bl 8009e16 ret = USBD_FAIL; 800880a: 2303 movs r3, #3 800880c: 75fb strb r3, [r7, #23] break; 800880e: e007 b.n 8008820 case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 8008810: 6839 ldr r1, [r7, #0] 8008812: 6878 ldr r0, [r7, #4] 8008814: f001 faff bl 8009e16 ret = USBD_FAIL; 8008818: 2303 movs r3, #3 800881a: 75fb strb r3, [r7, #23] break; 800881c: e000 b.n 8008820 break; 800881e: bf00 nop } break; 8008820: e006 b.n 8008830 default: USBD_CtlError(pdev, req); 8008822: 6839 ldr r1, [r7, #0] 8008824: 6878 ldr r0, [r7, #4] 8008826: f001 faf6 bl 8009e16 ret = USBD_FAIL; 800882a: 2303 movs r3, #3 800882c: 75fb strb r3, [r7, #23] break; 800882e: bf00 nop } return (uint8_t)ret; 8008830: 7dfb ldrb r3, [r7, #23] } 8008832: 4618 mov r0, r3 8008834: 3718 adds r7, #24 8008836: 46bd mov sp, r7 8008838: bd80 pop {r7, pc} 800883a: bf00 nop 800883c: 20000110 .word 0x20000110 8008840: 200000f8 .word 0x200000f8 08008844 : uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId) { USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) { 8008844: b580 push {r7, lr} 8008846: b086 sub sp, #24 8008848: af00 add r7, sp, #0 800884a: 60f8 str r0, [r7, #12] 800884c: 60b9 str r1, [r7, #8] 800884e: 4613 mov r3, r2 8008850: 80fb strh r3, [r7, #6] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8008852: 68fb ldr r3, [r7, #12] 8008854: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008858: 68fb ldr r3, [r7, #12] 800885a: 32b0 adds r2, #176 @ 0xb0 800885c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008860: 617b str r3, [r7, #20] #endif /* USE_USBD_COMPOSITE */ if (hhid == NULL) 8008862: 697b ldr r3, [r7, #20] 8008864: 2b00 cmp r3, #0 8008866: d101 bne.n 800886c { return (uint8_t)USBD_FAIL; 8008868: 2303 movs r3, #3 800886a: e014 b.n 8008896 #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 800886c: 68fb ldr r3, [r7, #12] 800886e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008872: b2db uxtb r3, r3 8008874: 2b03 cmp r3, #3 8008876: d10d bne.n 8008894 { if (hhid->state == USBD_HID_IDLE) 8008878: 697b ldr r3, [r7, #20] 800887a: 7b1b ldrb r3, [r3, #12] 800887c: 2b00 cmp r3, #0 800887e: d109 bne.n 8008894 { hhid->state = USBD_HID_BUSY; 8008880: 697b ldr r3, [r7, #20] 8008882: 2201 movs r2, #1 8008884: 731a strb r2, [r3, #12] (void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len); 8008886: 4b06 ldr r3, [pc, #24] @ (80088a0 ) 8008888: 7819 ldrb r1, [r3, #0] 800888a: 88fb ldrh r3, [r7, #6] 800888c: 68ba ldr r2, [r7, #8] 800888e: 68f8 ldr r0, [r7, #12] 8008890: f001 ff7d bl 800a78e } } return (uint8_t)USBD_OK; 8008894: 2300 movs r3, #0 } 8008896: 4618 mov r0, r3 8008898: 3718 adds r7, #24 800889a: 46bd mov sp, r7 800889c: bd80 pop {r7, pc} 800889e: bf00 nop 80088a0: 2000013d .word 0x2000013d 080088a4 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) { 80088a4: b580 push {r7, lr} 80088a6: b084 sub sp, #16 80088a8: af00 add r7, sp, #0 80088aa: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 80088ac: 2181 movs r1, #129 @ 0x81 80088ae: 4809 ldr r0, [pc, #36] @ (80088d4 ) 80088b0: f000 fc4e bl 8009150 80088b4: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 80088b6: 68fb ldr r3, [r7, #12] 80088b8: 2b00 cmp r3, #0 80088ba: d002 beq.n 80088c2 { pEpDesc->bInterval = HID_FS_BINTERVAL; 80088bc: 68fb ldr r3, [r7, #12] 80088be: 220a movs r2, #10 80088c0: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 80088c2: 687b ldr r3, [r7, #4] 80088c4: 2222 movs r2, #34 @ 0x22 80088c6: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 80088c8: 4b02 ldr r3, [pc, #8] @ (80088d4 ) } 80088ca: 4618 mov r0, r3 80088cc: 3710 adds r7, #16 80088ce: 46bd mov sp, r7 80088d0: bd80 pop {r7, pc} 80088d2: bf00 nop 80088d4: 200000d4 .word 0x200000d4 080088d8 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) { 80088d8: b580 push {r7, lr} 80088da: b084 sub sp, #16 80088dc: af00 add r7, sp, #0 80088de: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 80088e0: 2181 movs r1, #129 @ 0x81 80088e2: 4809 ldr r0, [pc, #36] @ (8008908 ) 80088e4: f000 fc34 bl 8009150 80088e8: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 80088ea: 68fb ldr r3, [r7, #12] 80088ec: 2b00 cmp r3, #0 80088ee: d002 beq.n 80088f6 { pEpDesc->bInterval = HID_HS_BINTERVAL; 80088f0: 68fb ldr r3, [r7, #12] 80088f2: 2207 movs r2, #7 80088f4: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 80088f6: 687b ldr r3, [r7, #4] 80088f8: 2222 movs r2, #34 @ 0x22 80088fa: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 80088fc: 4b02 ldr r3, [pc, #8] @ (8008908 ) } 80088fe: 4618 mov r0, r3 8008900: 3710 adds r7, #16 8008902: 46bd mov sp, r7 8008904: bd80 pop {r7, pc} 8008906: bf00 nop 8008908: 200000d4 .word 0x200000d4 0800890c : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) { 800890c: b580 push {r7, lr} 800890e: b084 sub sp, #16 8008910: af00 add r7, sp, #0 8008912: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8008914: 2181 movs r1, #129 @ 0x81 8008916: 4809 ldr r0, [pc, #36] @ (800893c ) 8008918: f000 fc1a bl 8009150 800891c: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 800891e: 68fb ldr r3, [r7, #12] 8008920: 2b00 cmp r3, #0 8008922: d002 beq.n 800892a { pEpDesc->bInterval = HID_FS_BINTERVAL; 8008924: 68fb ldr r3, [r7, #12] 8008926: 220a movs r2, #10 8008928: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 800892a: 687b ldr r3, [r7, #4] 800892c: 2222 movs r2, #34 @ 0x22 800892e: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8008930: 4b02 ldr r3, [pc, #8] @ (800893c ) } 8008932: 4618 mov r0, r3 8008934: 3710 adds r7, #16 8008936: 46bd mov sp, r7 8008938: bd80 pop {r7, pc} 800893a: bf00 nop 800893c: 200000d4 .word 0x200000d4 08008940 : * @param pdev: device instance * @param epnum: endpoint index * @retval status */ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8008940: b480 push {r7} 8008942: b083 sub sp, #12 8008944: af00 add r7, sp, #0 8008946: 6078 str r0, [r7, #4] 8008948: 460b mov r3, r1 800894a: 70fb strb r3, [r7, #3] UNUSED(epnum); /* Ensure that the FIFO is empty before a new transfer, this condition could be caused by a new transfer before the end of the previous transfer */ ((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE; 800894c: 687b ldr r3, [r7, #4] 800894e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008952: 687b ldr r3, [r7, #4] 8008954: 32b0 adds r2, #176 @ 0xb0 8008956: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800895a: 2200 movs r2, #0 800895c: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 800895e: 2300 movs r3, #0 } 8008960: 4618 mov r0, r3 8008962: 370c adds r7, #12 8008964: 46bd mov sp, r7 8008966: f85d 7b04 ldr.w r7, [sp], #4 800896a: 4770 bx lr 0800896c : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) { 800896c: b480 push {r7} 800896e: b083 sub sp, #12 8008970: af00 add r7, sp, #0 8008972: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); 8008974: 687b ldr r3, [r7, #4] 8008976: 220a movs r2, #10 8008978: 801a strh r2, [r3, #0] return USBD_HID_DeviceQualifierDesc; 800897a: 4b03 ldr r3, [pc, #12] @ (8008988 ) } 800897c: 4618 mov r0, r3 800897e: 370c adds r7, #12 8008980: 46bd mov sp, r7 8008982: f85d 7b04 ldr.w r7, [sp], #4 8008986: 4770 bx lr 8008988: 20000104 .word 0x20000104 0800898c : * @param id: Low level core index * @retval status: USBD Status */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 800898c: b580 push {r7, lr} 800898e: b086 sub sp, #24 8008990: af00 add r7, sp, #0 8008992: 60f8 str r0, [r7, #12] 8008994: 60b9 str r1, [r7, #8] 8008996: 4613 mov r3, r2 8008998: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 800899a: 68fb ldr r3, [r7, #12] 800899c: 2b00 cmp r3, #0 800899e: d101 bne.n 80089a4 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 80089a0: 2303 movs r3, #3 80089a2: e01f b.n 80089e4 pdev->NumClasses = 0; pdev->classId = 0; } #else /* Unlink previous class*/ pdev->pClass[0] = NULL; 80089a4: 68fb ldr r3, [r7, #12] 80089a6: 2200 movs r2, #0 80089a8: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 pdev->pUserData[0] = NULL; 80089ac: 68fb ldr r3, [r7, #12] 80089ae: 2200 movs r2, #0 80089b0: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4 #endif /* USE_USBD_COMPOSITE */ pdev->pConfDesc = NULL; 80089b4: 68fb ldr r3, [r7, #12] 80089b6: 2200 movs r2, #0 80089b8: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 /* Assign USBD Descriptors */ if (pdesc != NULL) 80089bc: 68bb ldr r3, [r7, #8] 80089be: 2b00 cmp r3, #0 80089c0: d003 beq.n 80089ca { pdev->pDesc = pdesc; 80089c2: 68fb ldr r3, [r7, #12] 80089c4: 68ba ldr r2, [r7, #8] 80089c6: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 80089ca: 68fb ldr r3, [r7, #12] 80089cc: 2201 movs r2, #1 80089ce: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->id = id; 80089d2: 68fb ldr r3, [r7, #12] 80089d4: 79fa ldrb r2, [r7, #7] 80089d6: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 80089d8: 68f8 ldr r0, [r7, #12] 80089da: f001 fda3 bl 800a524 80089de: 4603 mov r3, r0 80089e0: 75fb strb r3, [r7, #23] return ret; 80089e2: 7dfb ldrb r3, [r7, #23] } 80089e4: 4618 mov r0, r3 80089e6: 3718 adds r7, #24 80089e8: 46bd mov sp, r7 80089ea: bd80 pop {r7, pc} 080089ec : * @param pdev: Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 80089ec: b580 push {r7, lr} 80089ee: b084 sub sp, #16 80089f0: af00 add r7, sp, #0 80089f2: 6078 str r0, [r7, #4] 80089f4: 6039 str r1, [r7, #0] uint16_t len = 0U; 80089f6: 2300 movs r3, #0 80089f8: 81fb strh r3, [r7, #14] if (pclass == NULL) 80089fa: 683b ldr r3, [r7, #0] 80089fc: 2b00 cmp r3, #0 80089fe: d101 bne.n 8008a04 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8008a00: 2303 movs r3, #3 8008a02: e025 b.n 8008a50 } /* link the class to the USB Device handle */ pdev->pClass[0] = pclass; 8008a04: 687b ldr r3, [r7, #4] 8008a06: 683a ldr r2, [r7, #0] 8008a08: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) 8008a0c: 687b ldr r3, [r7, #4] 8008a0e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008a12: 687b ldr r3, [r7, #4] 8008a14: 32ae adds r2, #174 @ 0xae 8008a16: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008a1a: 6adb ldr r3, [r3, #44] @ 0x2c 8008a1c: 2b00 cmp r3, #0 8008a1e: d00f beq.n 8008a40 { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); 8008a20: 687b ldr r3, [r7, #4] 8008a22: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008a26: 687b ldr r3, [r7, #4] 8008a28: 32ae adds r2, #174 @ 0xae 8008a2a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008a2e: 6adb ldr r3, [r3, #44] @ 0x2c 8008a30: f107 020e add.w r2, r7, #14 8008a34: 4610 mov r0, r2 8008a36: 4798 blx r3 8008a38: 4602 mov r2, r0 8008a3a: 687b ldr r3, [r7, #4] 8008a3c: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 } #endif /* USE_USB_FS */ /* Increment the NumClasses */ pdev->NumClasses++; 8008a40: 687b ldr r3, [r7, #4] 8008a42: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8008a46: 1c5a adds r2, r3, #1 8008a48: 687b ldr r3, [r7, #4] 8008a4a: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8 return USBD_OK; 8008a4e: 2300 movs r3, #0 } 8008a50: 4618 mov r0, r3 8008a52: 3710 adds r7, #16 8008a54: 46bd mov sp, r7 8008a56: bd80 pop {r7, pc} 08008a58 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 8008a58: b580 push {r7, lr} 8008a5a: b082 sub sp, #8 8008a5c: af00 add r7, sp, #0 8008a5e: 6078 str r0, [r7, #4] #ifdef USE_USBD_COMPOSITE pdev->classId = 0U; #endif /* USE_USBD_COMPOSITE */ /* Start the low level driver */ return USBD_LL_Start(pdev); 8008a60: 6878 ldr r0, [r7, #4] 8008a62: f001 fdab bl 800a5bc 8008a66: 4603 mov r3, r0 } 8008a68: 4618 mov r0, r3 8008a6a: 3708 adds r7, #8 8008a6c: 46bd mov sp, r7 8008a6e: bd80 pop {r7, pc} 08008a70 : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 8008a70: b480 push {r7} 8008a72: b083 sub sp, #12 8008a74: af00 add r7, sp, #0 8008a76: 6078 str r0, [r7, #4] return ret; #else /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8008a78: 2300 movs r3, #0 #endif /* USBD_HS_TESTMODE_ENABLE */ } 8008a7a: 4618 mov r0, r3 8008a7c: 370c adds r7, #12 8008a7e: 46bd mov sp, r7 8008a80: f85d 7b04 ldr.w r7, [sp], #4 8008a84: 4770 bx lr 08008a86 : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008a86: b580 push {r7, lr} 8008a88: b084 sub sp, #16 8008a8a: af00 add r7, sp, #0 8008a8c: 6078 str r0, [r7, #4] 8008a8e: 460b mov r3, r1 8008a90: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8008a92: 2300 movs r3, #0 8008a94: 73fb strb r3, [r7, #15] } } } } #else if (pdev->pClass[0] != NULL) 8008a96: 687b ldr r3, [r7, #4] 8008a98: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008a9c: 2b00 cmp r3, #0 8008a9e: d009 beq.n 8008ab4 { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); 8008aa0: 687b ldr r3, [r7, #4] 8008aa2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008aa6: 681b ldr r3, [r3, #0] 8008aa8: 78fa ldrb r2, [r7, #3] 8008aaa: 4611 mov r1, r2 8008aac: 6878 ldr r0, [r7, #4] 8008aae: 4798 blx r3 8008ab0: 4603 mov r3, r0 8008ab2: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8008ab4: 7bfb ldrb r3, [r7, #15] } 8008ab6: 4618 mov r0, r3 8008ab8: 3710 adds r7, #16 8008aba: 46bd mov sp, r7 8008abc: bd80 pop {r7, pc} 08008abe : * @param pdev: device instance * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008abe: b580 push {r7, lr} 8008ac0: b084 sub sp, #16 8008ac2: af00 add r7, sp, #0 8008ac4: 6078 str r0, [r7, #4] 8008ac6: 460b mov r3, r1 8008ac8: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8008aca: 2300 movs r3, #0 8008acc: 73fb strb r3, [r7, #15] } } } #else /* Clear configuration and De-initialize the Class process */ if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) 8008ace: 687b ldr r3, [r7, #4] 8008ad0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008ad4: 685b ldr r3, [r3, #4] 8008ad6: 78fa ldrb r2, [r7, #3] 8008ad8: 4611 mov r1, r2 8008ada: 6878 ldr r0, [r7, #4] 8008adc: 4798 blx r3 8008ade: 4603 mov r3, r0 8008ae0: 2b00 cmp r3, #0 8008ae2: d001 beq.n 8008ae8 { ret = USBD_FAIL; 8008ae4: 2303 movs r3, #3 8008ae6: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8008ae8: 7bfb ldrb r3, [r7, #15] } 8008aea: 4618 mov r0, r3 8008aec: 3710 adds r7, #16 8008aee: 46bd mov sp, r7 8008af0: bd80 pop {r7, pc} 08008af2 : * @param pdev: device instance * @param psetup: setup packet buffer pointer * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 8008af2: b580 push {r7, lr} 8008af4: b084 sub sp, #16 8008af6: af00 add r7, sp, #0 8008af8: 6078 str r0, [r7, #4] 8008afa: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 8008afc: 687b ldr r3, [r7, #4] 8008afe: f203 23aa addw r3, r3, #682 @ 0x2aa 8008b02: 6839 ldr r1, [r7, #0] 8008b04: 4618 mov r0, r3 8008b06: f001 f94c bl 8009da2 pdev->ep0_state = USBD_EP0_SETUP; 8008b0a: 687b ldr r3, [r7, #4] 8008b0c: 2201 movs r2, #1 8008b0e: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep0_data_len = pdev->request.wLength; 8008b12: 687b ldr r3, [r7, #4] 8008b14: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0 8008b18: 461a mov r2, r3 8008b1a: 687b ldr r3, [r7, #4] 8008b1c: f8c3 2298 str.w r2, [r3, #664] @ 0x298 switch (pdev->request.bmRequest & 0x1FU) 8008b20: 687b ldr r3, [r7, #4] 8008b22: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008b26: f003 031f and.w r3, r3, #31 8008b2a: 2b02 cmp r3, #2 8008b2c: d01a beq.n 8008b64 8008b2e: 2b02 cmp r3, #2 8008b30: d822 bhi.n 8008b78 8008b32: 2b00 cmp r3, #0 8008b34: d002 beq.n 8008b3c 8008b36: 2b01 cmp r3, #1 8008b38: d00a beq.n 8008b50 8008b3a: e01d b.n 8008b78 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 8008b3c: 687b ldr r3, [r7, #4] 8008b3e: f203 23aa addw r3, r3, #682 @ 0x2aa 8008b42: 4619 mov r1, r3 8008b44: 6878 ldr r0, [r7, #4] 8008b46: f000 fb77 bl 8009238 8008b4a: 4603 mov r3, r0 8008b4c: 73fb strb r3, [r7, #15] break; 8008b4e: e020 b.n 8008b92 case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 8008b50: 687b ldr r3, [r7, #4] 8008b52: f203 23aa addw r3, r3, #682 @ 0x2aa 8008b56: 4619 mov r1, r3 8008b58: 6878 ldr r0, [r7, #4] 8008b5a: f000 fbdf bl 800931c 8008b5e: 4603 mov r3, r0 8008b60: 73fb strb r3, [r7, #15] break; 8008b62: e016 b.n 8008b92 case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 8008b64: 687b ldr r3, [r7, #4] 8008b66: f203 23aa addw r3, r3, #682 @ 0x2aa 8008b6a: 4619 mov r1, r3 8008b6c: 6878 ldr r0, [r7, #4] 8008b6e: f000 fc41 bl 80093f4 8008b72: 4603 mov r3, r0 8008b74: 73fb strb r3, [r7, #15] break; 8008b76: e00c b.n 8008b92 default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 8008b78: 687b ldr r3, [r7, #4] 8008b7a: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008b7e: f023 037f bic.w r3, r3, #127 @ 0x7f 8008b82: b2db uxtb r3, r3 8008b84: 4619 mov r1, r3 8008b86: 6878 ldr r0, [r7, #4] 8008b88: f001 fd78 bl 800a67c 8008b8c: 4603 mov r3, r0 8008b8e: 73fb strb r3, [r7, #15] break; 8008b90: bf00 nop } return ret; 8008b92: 7bfb ldrb r3, [r7, #15] } 8008b94: 4618 mov r0, r3 8008b96: 3710 adds r7, #16 8008b98: 46bd mov sp, r7 8008b9a: bd80 pop {r7, pc} 08008b9c : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8008b9c: b580 push {r7, lr} 8008b9e: b086 sub sp, #24 8008ba0: af00 add r7, sp, #0 8008ba2: 60f8 str r0, [r7, #12] 8008ba4: 460b mov r3, r1 8008ba6: 607a str r2, [r7, #4] 8008ba8: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret = USBD_OK; 8008baa: 2300 movs r3, #0 8008bac: 75fb strb r3, [r7, #23] uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8008bae: 7afb ldrb r3, [r7, #11] 8008bb0: 2b00 cmp r3, #0 8008bb2: d177 bne.n 8008ca4 { pep = &pdev->ep_out[0]; 8008bb4: 68fb ldr r3, [r7, #12] 8008bb6: f503 73aa add.w r3, r3, #340 @ 0x154 8008bba: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 8008bbc: 68fb ldr r3, [r7, #12] 8008bbe: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8008bc2: 2b03 cmp r3, #3 8008bc4: f040 80a1 bne.w 8008d0a { if (pep->rem_length > pep->maxpacket) 8008bc8: 693b ldr r3, [r7, #16] 8008bca: 685b ldr r3, [r3, #4] 8008bcc: 693a ldr r2, [r7, #16] 8008bce: 8992 ldrh r2, [r2, #12] 8008bd0: 4293 cmp r3, r2 8008bd2: d91c bls.n 8008c0e { pep->rem_length -= pep->maxpacket; 8008bd4: 693b ldr r3, [r7, #16] 8008bd6: 685b ldr r3, [r3, #4] 8008bd8: 693a ldr r2, [r7, #16] 8008bda: 8992 ldrh r2, [r2, #12] 8008bdc: 1a9a subs r2, r3, r2 8008bde: 693b ldr r3, [r7, #16] 8008be0: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8008be2: 693b ldr r3, [r7, #16] 8008be4: 691b ldr r3, [r3, #16] 8008be6: 693a ldr r2, [r7, #16] 8008be8: 8992 ldrh r2, [r2, #12] 8008bea: 441a add r2, r3 8008bec: 693b ldr r3, [r7, #16] 8008bee: 611a str r2, [r3, #16] (void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket)); 8008bf0: 693b ldr r3, [r7, #16] 8008bf2: 6919 ldr r1, [r3, #16] 8008bf4: 693b ldr r3, [r7, #16] 8008bf6: 899b ldrh r3, [r3, #12] 8008bf8: 461a mov r2, r3 8008bfa: 693b ldr r3, [r7, #16] 8008bfc: 685b ldr r3, [r3, #4] 8008bfe: 4293 cmp r3, r2 8008c00: bf38 it cc 8008c02: 4613 movcc r3, r2 8008c04: 461a mov r2, r3 8008c06: 68f8 ldr r0, [r7, #12] 8008c08: f001 f9b1 bl 8009f6e 8008c0c: e07d b.n 8008d0a } else { /* Find the class ID relative to the current request */ switch (pdev->request.bmRequest & 0x1FU) 8008c0e: 68fb ldr r3, [r7, #12] 8008c10: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008c14: f003 031f and.w r3, r3, #31 8008c18: 2b02 cmp r3, #2 8008c1a: d014 beq.n 8008c46 8008c1c: 2b02 cmp r3, #2 8008c1e: d81d bhi.n 8008c5c 8008c20: 2b00 cmp r3, #0 8008c22: d002 beq.n 8008c2a 8008c24: 2b01 cmp r3, #1 8008c26: d003 beq.n 8008c30 8008c28: e018 b.n 8008c5c { case USB_REQ_RECIPIENT_DEVICE: /* Device requests must be managed by the first instantiated class (or duplicated by all classes for simplicity) */ idx = 0U; 8008c2a: 2300 movs r3, #0 8008c2c: 75bb strb r3, [r7, #22] break; 8008c2e: e018 b.n 8008c62 case USB_REQ_RECIPIENT_INTERFACE: idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); 8008c30: 68fb ldr r3, [r7, #12] 8008c32: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8008c36: b2db uxtb r3, r3 8008c38: 4619 mov r1, r3 8008c3a: 68f8 ldr r0, [r7, #12] 8008c3c: f000 fa6e bl 800911c 8008c40: 4603 mov r3, r0 8008c42: 75bb strb r3, [r7, #22] break; 8008c44: e00d b.n 8008c62 case USB_REQ_RECIPIENT_ENDPOINT: idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); 8008c46: 68fb ldr r3, [r7, #12] 8008c48: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8008c4c: b2db uxtb r3, r3 8008c4e: 4619 mov r1, r3 8008c50: 68f8 ldr r0, [r7, #12] 8008c52: f000 fa70 bl 8009136 8008c56: 4603 mov r3, r0 8008c58: 75bb strb r3, [r7, #22] break; 8008c5a: e002 b.n 8008c62 default: /* Back to the first class in case of doubt */ idx = 0U; 8008c5c: 2300 movs r3, #0 8008c5e: 75bb strb r3, [r7, #22] break; 8008c60: bf00 nop } if (idx < USBD_MAX_SUPPORTED_CLASS) 8008c62: 7dbb ldrb r3, [r7, #22] 8008c64: 2b00 cmp r3, #0 8008c66: d119 bne.n 8008c9c { /* Setup the class ID and route the request to the relative class function */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008c68: 68fb ldr r3, [r7, #12] 8008c6a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008c6e: b2db uxtb r3, r3 8008c70: 2b03 cmp r3, #3 8008c72: d113 bne.n 8008c9c { if (pdev->pClass[idx]->EP0_RxReady != NULL) 8008c74: 7dba ldrb r2, [r7, #22] 8008c76: 68fb ldr r3, [r7, #12] 8008c78: 32ae adds r2, #174 @ 0xae 8008c7a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008c7e: 691b ldr r3, [r3, #16] 8008c80: 2b00 cmp r3, #0 8008c82: d00b beq.n 8008c9c { pdev->classId = idx; 8008c84: 7dba ldrb r2, [r7, #22] 8008c86: 68fb ldr r3, [r7, #12] 8008c88: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[idx]->EP0_RxReady(pdev); 8008c8c: 7dba ldrb r2, [r7, #22] 8008c8e: 68fb ldr r3, [r7, #12] 8008c90: 32ae adds r2, #174 @ 0xae 8008c92: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008c96: 691b ldr r3, [r3, #16] 8008c98: 68f8 ldr r0, [r7, #12] 8008c9a: 4798 blx r3 } } } (void)USBD_CtlSendStatus(pdev); 8008c9c: 68f8 ldr r0, [r7, #12] 8008c9e: f001 f977 bl 8009f90 8008ca2: e032 b.n 8008d0a } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); 8008ca4: 7afb ldrb r3, [r7, #11] 8008ca6: f003 037f and.w r3, r3, #127 @ 0x7f 8008caa: b2db uxtb r3, r3 8008cac: 4619 mov r1, r3 8008cae: 68f8 ldr r0, [r7, #12] 8008cb0: f000 fa41 bl 8009136 8008cb4: 4603 mov r3, r0 8008cb6: 75bb strb r3, [r7, #22] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8008cb8: 7dbb ldrb r3, [r7, #22] 8008cba: 2bff cmp r3, #255 @ 0xff 8008cbc: d025 beq.n 8008d0a 8008cbe: 7dbb ldrb r3, [r7, #22] 8008cc0: 2b00 cmp r3, #0 8008cc2: d122 bne.n 8008d0a { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008cc4: 68fb ldr r3, [r7, #12] 8008cc6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008cca: b2db uxtb r3, r3 8008ccc: 2b03 cmp r3, #3 8008cce: d117 bne.n 8008d00 { if (pdev->pClass[idx]->DataOut != NULL) 8008cd0: 7dba ldrb r2, [r7, #22] 8008cd2: 68fb ldr r3, [r7, #12] 8008cd4: 32ae adds r2, #174 @ 0xae 8008cd6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008cda: 699b ldr r3, [r3, #24] 8008cdc: 2b00 cmp r3, #0 8008cde: d00f beq.n 8008d00 { pdev->classId = idx; 8008ce0: 7dba ldrb r2, [r7, #22] 8008ce2: 68fb ldr r3, [r7, #12] 8008ce4: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); 8008ce8: 7dba ldrb r2, [r7, #22] 8008cea: 68fb ldr r3, [r7, #12] 8008cec: 32ae adds r2, #174 @ 0xae 8008cee: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008cf2: 699b ldr r3, [r3, #24] 8008cf4: 7afa ldrb r2, [r7, #11] 8008cf6: 4611 mov r1, r2 8008cf8: 68f8 ldr r0, [r7, #12] 8008cfa: 4798 blx r3 8008cfc: 4603 mov r3, r0 8008cfe: 75fb strb r3, [r7, #23] } } if (ret != USBD_OK) 8008d00: 7dfb ldrb r3, [r7, #23] 8008d02: 2b00 cmp r3, #0 8008d04: d001 beq.n 8008d0a { return ret; 8008d06: 7dfb ldrb r3, [r7, #23] 8008d08: e000 b.n 8008d0c } } } return USBD_OK; 8008d0a: 2300 movs r3, #0 } 8008d0c: 4618 mov r0, r3 8008d0e: 3718 adds r7, #24 8008d10: 46bd mov sp, r7 8008d12: bd80 pop {r7, pc} 08008d14 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8008d14: b580 push {r7, lr} 8008d16: b086 sub sp, #24 8008d18: af00 add r7, sp, #0 8008d1a: 60f8 str r0, [r7, #12] 8008d1c: 460b mov r3, r1 8008d1e: 607a str r2, [r7, #4] 8008d20: 72fb strb r3, [r7, #11] USBD_StatusTypeDef ret; uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8008d22: 7afb ldrb r3, [r7, #11] 8008d24: 2b00 cmp r3, #0 8008d26: d178 bne.n 8008e1a { pep = &pdev->ep_in[0]; 8008d28: 68fb ldr r3, [r7, #12] 8008d2a: 3314 adds r3, #20 8008d2c: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 8008d2e: 68fb ldr r3, [r7, #12] 8008d30: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8008d34: 2b02 cmp r3, #2 8008d36: d163 bne.n 8008e00 { if (pep->rem_length > pep->maxpacket) 8008d38: 693b ldr r3, [r7, #16] 8008d3a: 685b ldr r3, [r3, #4] 8008d3c: 693a ldr r2, [r7, #16] 8008d3e: 8992 ldrh r2, [r2, #12] 8008d40: 4293 cmp r3, r2 8008d42: d91c bls.n 8008d7e { pep->rem_length -= pep->maxpacket; 8008d44: 693b ldr r3, [r7, #16] 8008d46: 685b ldr r3, [r3, #4] 8008d48: 693a ldr r2, [r7, #16] 8008d4a: 8992 ldrh r2, [r2, #12] 8008d4c: 1a9a subs r2, r3, r2 8008d4e: 693b ldr r3, [r7, #16] 8008d50: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8008d52: 693b ldr r3, [r7, #16] 8008d54: 691b ldr r3, [r3, #16] 8008d56: 693a ldr r2, [r7, #16] 8008d58: 8992 ldrh r2, [r2, #12] 8008d5a: 441a add r2, r3 8008d5c: 693b ldr r3, [r7, #16] 8008d5e: 611a str r2, [r3, #16] (void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length); 8008d60: 693b ldr r3, [r7, #16] 8008d62: 6919 ldr r1, [r3, #16] 8008d64: 693b ldr r3, [r7, #16] 8008d66: 685b ldr r3, [r3, #4] 8008d68: 461a mov r2, r3 8008d6a: 68f8 ldr r0, [r7, #12] 8008d6c: f001 f8ee bl 8009f4c /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8008d70: 2300 movs r3, #0 8008d72: 2200 movs r2, #0 8008d74: 2100 movs r1, #0 8008d76: 68f8 ldr r0, [r7, #12] 8008d78: f001 fd2a bl 800a7d0 8008d7c: e040 b.n 8008e00 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 8008d7e: 693b ldr r3, [r7, #16] 8008d80: 899b ldrh r3, [r3, #12] 8008d82: 461a mov r2, r3 8008d84: 693b ldr r3, [r7, #16] 8008d86: 685b ldr r3, [r3, #4] 8008d88: 429a cmp r2, r3 8008d8a: d11c bne.n 8008dc6 (pep->total_length >= pep->maxpacket) && 8008d8c: 693b ldr r3, [r7, #16] 8008d8e: 681b ldr r3, [r3, #0] 8008d90: 693a ldr r2, [r7, #16] 8008d92: 8992 ldrh r2, [r2, #12] if ((pep->maxpacket == pep->rem_length) && 8008d94: 4293 cmp r3, r2 8008d96: d316 bcc.n 8008dc6 (pep->total_length < pdev->ep0_data_len)) 8008d98: 693b ldr r3, [r7, #16] 8008d9a: 681a ldr r2, [r3, #0] 8008d9c: 68fb ldr r3, [r7, #12] 8008d9e: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 (pep->total_length >= pep->maxpacket) && 8008da2: 429a cmp r2, r3 8008da4: d20f bcs.n 8008dc6 { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 8008da6: 2200 movs r2, #0 8008da8: 2100 movs r1, #0 8008daa: 68f8 ldr r0, [r7, #12] 8008dac: f001 f8ce bl 8009f4c pdev->ep0_data_len = 0U; 8008db0: 68fb ldr r3, [r7, #12] 8008db2: 2200 movs r2, #0 8008db4: f8c3 2298 str.w r2, [r3, #664] @ 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8008db8: 2300 movs r3, #0 8008dba: 2200 movs r2, #0 8008dbc: 2100 movs r1, #0 8008dbe: 68f8 ldr r0, [r7, #12] 8008dc0: f001 fd06 bl 800a7d0 8008dc4: e01c b.n 8008e00 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008dc6: 68fb ldr r3, [r7, #12] 8008dc8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008dcc: b2db uxtb r3, r3 8008dce: 2b03 cmp r3, #3 8008dd0: d10f bne.n 8008df2 { if (pdev->pClass[0]->EP0_TxSent != NULL) 8008dd2: 68fb ldr r3, [r7, #12] 8008dd4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008dd8: 68db ldr r3, [r3, #12] 8008dda: 2b00 cmp r3, #0 8008ddc: d009 beq.n 8008df2 { pdev->classId = 0U; 8008dde: 68fb ldr r3, [r7, #12] 8008de0: 2200 movs r2, #0 8008de2: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[0]->EP0_TxSent(pdev); 8008de6: 68fb ldr r3, [r7, #12] 8008de8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008dec: 68db ldr r3, [r3, #12] 8008dee: 68f8 ldr r0, [r7, #12] 8008df0: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 8008df2: 2180 movs r1, #128 @ 0x80 8008df4: 68f8 ldr r0, [r7, #12] 8008df6: f001 fc41 bl 800a67c (void)USBD_CtlReceiveStatus(pdev); 8008dfa: 68f8 ldr r0, [r7, #12] 8008dfc: f001 f8db bl 8009fb6 } } } if (pdev->dev_test_mode != 0U) 8008e00: 68fb ldr r3, [r7, #12] 8008e02: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 8008e06: 2b00 cmp r3, #0 8008e08: d03a beq.n 8008e80 { (void)USBD_RunTestMode(pdev); 8008e0a: 68f8 ldr r0, [r7, #12] 8008e0c: f7ff fe30 bl 8008a70 pdev->dev_test_mode = 0U; 8008e10: 68fb ldr r3, [r7, #12] 8008e12: 2200 movs r2, #0 8008e14: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 8008e18: e032 b.n 8008e80 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); 8008e1a: 7afb ldrb r3, [r7, #11] 8008e1c: f063 037f orn r3, r3, #127 @ 0x7f 8008e20: b2db uxtb r3, r3 8008e22: 4619 mov r1, r3 8008e24: 68f8 ldr r0, [r7, #12] 8008e26: f000 f986 bl 8009136 8008e2a: 4603 mov r3, r0 8008e2c: 75fb strb r3, [r7, #23] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8008e2e: 7dfb ldrb r3, [r7, #23] 8008e30: 2bff cmp r3, #255 @ 0xff 8008e32: d025 beq.n 8008e80 8008e34: 7dfb ldrb r3, [r7, #23] 8008e36: 2b00 cmp r3, #0 8008e38: d122 bne.n 8008e80 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008e3a: 68fb ldr r3, [r7, #12] 8008e3c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008e40: b2db uxtb r3, r3 8008e42: 2b03 cmp r3, #3 8008e44: d11c bne.n 8008e80 { if (pdev->pClass[idx]->DataIn != NULL) 8008e46: 7dfa ldrb r2, [r7, #23] 8008e48: 68fb ldr r3, [r7, #12] 8008e4a: 32ae adds r2, #174 @ 0xae 8008e4c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008e50: 695b ldr r3, [r3, #20] 8008e52: 2b00 cmp r3, #0 8008e54: d014 beq.n 8008e80 { pdev->classId = idx; 8008e56: 7dfa ldrb r2, [r7, #23] 8008e58: 68fb ldr r3, [r7, #12] 8008e5a: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); 8008e5e: 7dfa ldrb r2, [r7, #23] 8008e60: 68fb ldr r3, [r7, #12] 8008e62: 32ae adds r2, #174 @ 0xae 8008e64: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008e68: 695b ldr r3, [r3, #20] 8008e6a: 7afa ldrb r2, [r7, #11] 8008e6c: 4611 mov r1, r2 8008e6e: 68f8 ldr r0, [r7, #12] 8008e70: 4798 blx r3 8008e72: 4603 mov r3, r0 8008e74: 75bb strb r3, [r7, #22] if (ret != USBD_OK) 8008e76: 7dbb ldrb r3, [r7, #22] 8008e78: 2b00 cmp r3, #0 8008e7a: d001 beq.n 8008e80 { return ret; 8008e7c: 7dbb ldrb r3, [r7, #22] 8008e7e: e000 b.n 8008e82 } } } } return USBD_OK; 8008e80: 2300 movs r3, #0 } 8008e82: 4618 mov r0, r3 8008e84: 3718 adds r7, #24 8008e86: 46bd mov sp, r7 8008e88: bd80 pop {r7, pc} 08008e8a : * Handle Reset event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 8008e8a: b580 push {r7, lr} 8008e8c: b084 sub sp, #16 8008e8e: af00 add r7, sp, #0 8008e90: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 8008e92: 2300 movs r3, #0 8008e94: 73fb strb r3, [r7, #15] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 8008e96: 687b ldr r3, [r7, #4] 8008e98: 2201 movs r2, #1 8008e9a: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->ep0_state = USBD_EP0_IDLE; 8008e9e: 687b ldr r3, [r7, #4] 8008ea0: 2200 movs r2, #0 8008ea2: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->dev_config = 0U; 8008ea6: 687b ldr r3, [r7, #4] 8008ea8: 2200 movs r2, #0 8008eaa: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 8008eac: 687b ldr r3, [r7, #4] 8008eae: 2200 movs r2, #0 8008eb0: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 pdev->dev_test_mode = 0U; 8008eb4: 687b ldr r3, [r7, #4] 8008eb6: 2200 movs r2, #0 8008eb8: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 } } } #else if (pdev->pClass[0] != NULL) 8008ebc: 687b ldr r3, [r7, #4] 8008ebe: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008ec2: 2b00 cmp r3, #0 8008ec4: d014 beq.n 8008ef0 { if (pdev->pClass[0]->DeInit != NULL) 8008ec6: 687b ldr r3, [r7, #4] 8008ec8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008ecc: 685b ldr r3, [r3, #4] 8008ece: 2b00 cmp r3, #0 8008ed0: d00e beq.n 8008ef0 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) 8008ed2: 687b ldr r3, [r7, #4] 8008ed4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008ed8: 685b ldr r3, [r3, #4] 8008eda: 687a ldr r2, [r7, #4] 8008edc: 6852 ldr r2, [r2, #4] 8008ede: b2d2 uxtb r2, r2 8008ee0: 4611 mov r1, r2 8008ee2: 6878 ldr r0, [r7, #4] 8008ee4: 4798 blx r3 8008ee6: 4603 mov r3, r0 8008ee8: 2b00 cmp r3, #0 8008eea: d001 beq.n 8008ef0 { ret = USBD_FAIL; 8008eec: 2303 movs r3, #3 8008eee: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8008ef0: 2340 movs r3, #64 @ 0x40 8008ef2: 2200 movs r2, #0 8008ef4: 2100 movs r1, #0 8008ef6: 6878 ldr r0, [r7, #4] 8008ef8: f001 fb7b bl 800a5f2 pdev->ep_out[0x00U & 0xFU].is_used = 1U; 8008efc: 687b ldr r3, [r7, #4] 8008efe: 2201 movs r2, #1 8008f00: f883 2163 strb.w r2, [r3, #355] @ 0x163 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 8008f04: 687b ldr r3, [r7, #4] 8008f06: 2240 movs r2, #64 @ 0x40 8008f08: f8a3 2160 strh.w r2, [r3, #352] @ 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8008f0c: 2340 movs r3, #64 @ 0x40 8008f0e: 2200 movs r2, #0 8008f10: 2180 movs r1, #128 @ 0x80 8008f12: 6878 ldr r0, [r7, #4] 8008f14: f001 fb6d bl 800a5f2 pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8008f18: 687b ldr r3, [r7, #4] 8008f1a: 2201 movs r2, #1 8008f1c: f883 2023 strb.w r2, [r3, #35] @ 0x23 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8008f20: 687b ldr r3, [r7, #4] 8008f22: 2240 movs r2, #64 @ 0x40 8008f24: 841a strh r2, [r3, #32] return ret; 8008f26: 7bfb ldrb r3, [r7, #15] } 8008f28: 4618 mov r0, r3 8008f2a: 3710 adds r7, #16 8008f2c: 46bd mov sp, r7 8008f2e: bd80 pop {r7, pc} 08008f30 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8008f30: b480 push {r7} 8008f32: b083 sub sp, #12 8008f34: af00 add r7, sp, #0 8008f36: 6078 str r0, [r7, #4] 8008f38: 460b mov r3, r1 8008f3a: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 8008f3c: 687b ldr r3, [r7, #4] 8008f3e: 78fa ldrb r2, [r7, #3] 8008f40: 741a strb r2, [r3, #16] return USBD_OK; 8008f42: 2300 movs r3, #0 } 8008f44: 4618 mov r0, r3 8008f46: 370c adds r7, #12 8008f48: 46bd mov sp, r7 8008f4a: f85d 7b04 ldr.w r7, [sp], #4 8008f4e: 4770 bx lr 08008f50 : * Handle Suspend event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 8008f50: b480 push {r7} 8008f52: b083 sub sp, #12 8008f54: af00 add r7, sp, #0 8008f56: 6078 str r0, [r7, #4] if (pdev->dev_state != USBD_STATE_SUSPENDED) 8008f58: 687b ldr r3, [r7, #4] 8008f5a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008f5e: b2db uxtb r3, r3 8008f60: 2b04 cmp r3, #4 8008f62: d006 beq.n 8008f72 { pdev->dev_old_state = pdev->dev_state; 8008f64: 687b ldr r3, [r7, #4] 8008f66: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008f6a: b2da uxtb r2, r3 8008f6c: 687b ldr r3, [r7, #4] 8008f6e: f883 229d strb.w r2, [r3, #669] @ 0x29d } pdev->dev_state = USBD_STATE_SUSPENDED; 8008f72: 687b ldr r3, [r7, #4] 8008f74: 2204 movs r2, #4 8008f76: f883 229c strb.w r2, [r3, #668] @ 0x29c return USBD_OK; 8008f7a: 2300 movs r3, #0 } 8008f7c: 4618 mov r0, r3 8008f7e: 370c adds r7, #12 8008f80: 46bd mov sp, r7 8008f82: f85d 7b04 ldr.w r7, [sp], #4 8008f86: 4770 bx lr 08008f88 : * Handle Resume event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 8008f88: b480 push {r7} 8008f8a: b083 sub sp, #12 8008f8c: af00 add r7, sp, #0 8008f8e: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 8008f90: 687b ldr r3, [r7, #4] 8008f92: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008f96: b2db uxtb r3, r3 8008f98: 2b04 cmp r3, #4 8008f9a: d106 bne.n 8008faa { pdev->dev_state = pdev->dev_old_state; 8008f9c: 687b ldr r3, [r7, #4] 8008f9e: f893 329d ldrb.w r3, [r3, #669] @ 0x29d 8008fa2: b2da uxtb r2, r3 8008fa4: 687b ldr r3, [r7, #4] 8008fa6: f883 229c strb.w r2, [r3, #668] @ 0x29c } return USBD_OK; 8008faa: 2300 movs r3, #0 } 8008fac: 4618 mov r0, r3 8008fae: 370c adds r7, #12 8008fb0: 46bd mov sp, r7 8008fb2: f85d 7b04 ldr.w r7, [sp], #4 8008fb6: 4770 bx lr 08008fb8 : * Handle SOF event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 8008fb8: b580 push {r7, lr} 8008fba: b082 sub sp, #8 8008fbc: af00 add r7, sp, #0 8008fbe: 6078 str r0, [r7, #4] /* The SOF event can be distributed for all classes that support it */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008fc0: 687b ldr r3, [r7, #4] 8008fc2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008fc6: b2db uxtb r3, r3 8008fc8: 2b03 cmp r3, #3 8008fca: d110 bne.n 8008fee } } } } #else if (pdev->pClass[0] != NULL) 8008fcc: 687b ldr r3, [r7, #4] 8008fce: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008fd2: 2b00 cmp r3, #0 8008fd4: d00b beq.n 8008fee { if (pdev->pClass[0]->SOF != NULL) 8008fd6: 687b ldr r3, [r7, #4] 8008fd8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008fdc: 69db ldr r3, [r3, #28] 8008fde: 2b00 cmp r3, #0 8008fe0: d005 beq.n 8008fee { (void)pdev->pClass[0]->SOF(pdev); 8008fe2: 687b ldr r3, [r7, #4] 8008fe4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008fe8: 69db ldr r3, [r3, #28] 8008fea: 6878 ldr r0, [r7, #4] 8008fec: 4798 blx r3 } } #endif /* USE_USBD_COMPOSITE */ } return USBD_OK; 8008fee: 2300 movs r3, #0 } 8008ff0: 4618 mov r0, r3 8008ff2: 3708 adds r7, #8 8008ff4: 46bd mov sp, r7 8008ff6: bd80 pop {r7, pc} 08008ff8 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8008ff8: b580 push {r7, lr} 8008ffa: b082 sub sp, #8 8008ffc: af00 add r7, sp, #0 8008ffe: 6078 str r0, [r7, #4] 8009000: 460b mov r3, r1 8009002: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009004: 687b ldr r3, [r7, #4] 8009006: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800900a: 687b ldr r3, [r7, #4] 800900c: 32ae adds r2, #174 @ 0xae 800900e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009012: 2b00 cmp r3, #0 8009014: d101 bne.n 800901a { return USBD_FAIL; 8009016: 2303 movs r3, #3 8009018: e01c b.n 8009054 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 800901a: 687b ldr r3, [r7, #4] 800901c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009020: b2db uxtb r3, r3 8009022: 2b03 cmp r3, #3 8009024: d115 bne.n 8009052 { if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL) 8009026: 687b ldr r3, [r7, #4] 8009028: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800902c: 687b ldr r3, [r7, #4] 800902e: 32ae adds r2, #174 @ 0xae 8009030: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009034: 6a1b ldr r3, [r3, #32] 8009036: 2b00 cmp r3, #0 8009038: d00b beq.n 8009052 { (void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum); 800903a: 687b ldr r3, [r7, #4] 800903c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009040: 687b ldr r3, [r7, #4] 8009042: 32ae adds r2, #174 @ 0xae 8009044: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009048: 6a1b ldr r3, [r3, #32] 800904a: 78fa ldrb r2, [r7, #3] 800904c: 4611 mov r1, r2 800904e: 6878 ldr r0, [r7, #4] 8009050: 4798 blx r3 } } return USBD_OK; 8009052: 2300 movs r3, #0 } 8009054: 4618 mov r0, r3 8009056: 3708 adds r7, #8 8009058: 46bd mov sp, r7 800905a: bd80 pop {r7, pc} 0800905c : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 800905c: b580 push {r7, lr} 800905e: b082 sub sp, #8 8009060: af00 add r7, sp, #0 8009062: 6078 str r0, [r7, #4] 8009064: 460b mov r3, r1 8009066: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009068: 687b ldr r3, [r7, #4] 800906a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800906e: 687b ldr r3, [r7, #4] 8009070: 32ae adds r2, #174 @ 0xae 8009072: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009076: 2b00 cmp r3, #0 8009078: d101 bne.n 800907e { return USBD_FAIL; 800907a: 2303 movs r3, #3 800907c: e01c b.n 80090b8 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 800907e: 687b ldr r3, [r7, #4] 8009080: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009084: b2db uxtb r3, r3 8009086: 2b03 cmp r3, #3 8009088: d115 bne.n 80090b6 { if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL) 800908a: 687b ldr r3, [r7, #4] 800908c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009090: 687b ldr r3, [r7, #4] 8009092: 32ae adds r2, #174 @ 0xae 8009094: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009098: 6a5b ldr r3, [r3, #36] @ 0x24 800909a: 2b00 cmp r3, #0 800909c: d00b beq.n 80090b6 { (void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum); 800909e: 687b ldr r3, [r7, #4] 80090a0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80090a4: 687b ldr r3, [r7, #4] 80090a6: 32ae adds r2, #174 @ 0xae 80090a8: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80090ac: 6a5b ldr r3, [r3, #36] @ 0x24 80090ae: 78fa ldrb r2, [r7, #3] 80090b0: 4611 mov r1, r2 80090b2: 6878 ldr r0, [r7, #4] 80090b4: 4798 blx r3 } } return USBD_OK; 80090b6: 2300 movs r3, #0 } 80090b8: 4618 mov r0, r3 80090ba: 3708 adds r7, #8 80090bc: 46bd mov sp, r7 80090be: bd80 pop {r7, pc} 080090c0 : * Handle device connection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { 80090c0: b480 push {r7} 80090c2: b083 sub sp, #12 80090c4: af00 add r7, sp, #0 80090c6: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 80090c8: 2300 movs r3, #0 } 80090ca: 4618 mov r0, r3 80090cc: 370c adds r7, #12 80090ce: 46bd mov sp, r7 80090d0: f85d 7b04 ldr.w r7, [sp], #4 80090d4: 4770 bx lr 080090d6 : * Handle device disconnection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { 80090d6: b580 push {r7, lr} 80090d8: b084 sub sp, #16 80090da: af00 add r7, sp, #0 80090dc: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 80090de: 2300 movs r3, #0 80090e0: 73fb strb r3, [r7, #15] /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; 80090e2: 687b ldr r3, [r7, #4] 80090e4: 2201 movs r2, #1 80090e6: f883 229c strb.w r2, [r3, #668] @ 0x29c } } } } #else if (pdev->pClass[0] != NULL) 80090ea: 687b ldr r3, [r7, #4] 80090ec: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80090f0: 2b00 cmp r3, #0 80090f2: d00e beq.n 8009112 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U) 80090f4: 687b ldr r3, [r7, #4] 80090f6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80090fa: 685b ldr r3, [r3, #4] 80090fc: 687a ldr r2, [r7, #4] 80090fe: 6852 ldr r2, [r2, #4] 8009100: b2d2 uxtb r2, r2 8009102: 4611 mov r1, r2 8009104: 6878 ldr r0, [r7, #4] 8009106: 4798 blx r3 8009108: 4603 mov r3, r0 800910a: 2b00 cmp r3, #0 800910c: d001 beq.n 8009112 { ret = USBD_FAIL; 800910e: 2303 movs r3, #3 8009110: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ return ret; 8009112: 7bfb ldrb r3, [r7, #15] } 8009114: 4618 mov r0, r3 8009116: 3710 adds r7, #16 8009118: 46bd mov sp, r7 800911a: bd80 pop {r7, pc} 0800911c : * @param pdev: device instance * @param index : selected interface number * @retval index of the class using the selected interface number. OxFF if no class found. */ uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) { 800911c: b480 push {r7} 800911e: b083 sub sp, #12 8009120: af00 add r7, sp, #0 8009122: 6078 str r0, [r7, #4] 8009124: 460b mov r3, r1 8009126: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009128: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 800912a: 4618 mov r0, r3 800912c: 370c adds r7, #12 800912e: 46bd mov sp, r7 8009130: f85d 7b04 ldr.w r7, [sp], #4 8009134: 4770 bx lr 08009136 : * @param pdev: device instance * @param index : selected endpoint number * @retval index of the class using the selected endpoint number. 0xFF if no class found. */ uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) { 8009136: b480 push {r7} 8009138: b083 sub sp, #12 800913a: af00 add r7, sp, #0 800913c: 6078 str r0, [r7, #4] 800913e: 460b mov r3, r1 8009140: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009142: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8009144: 4618 mov r0, r3 8009146: 370c adds r7, #12 8009148: 46bd mov sp, r7 800914a: f85d 7b04 ldr.w r7, [sp], #4 800914e: 4770 bx lr 08009150 : * @param pConfDesc: pointer to Bos descriptor * @param EpAddr: endpoint address * @retval pointer to video endpoint descriptor */ void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) { 8009150: b580 push {r7, lr} 8009152: b086 sub sp, #24 8009154: af00 add r7, sp, #0 8009156: 6078 str r0, [r7, #4] 8009158: 460b mov r3, r1 800915a: 70fb strb r3, [r7, #3] USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; 800915c: 687b ldr r3, [r7, #4] 800915e: 617b str r3, [r7, #20] USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; 8009160: 687b ldr r3, [r7, #4] 8009162: 60fb str r3, [r7, #12] USBD_EpDescTypeDef *pEpDesc = NULL; 8009164: 2300 movs r3, #0 8009166: 613b str r3, [r7, #16] uint16_t ptr; if (desc->wTotalLength > desc->bLength) 8009168: 68fb ldr r3, [r7, #12] 800916a: 885b ldrh r3, [r3, #2] 800916c: b29b uxth r3, r3 800916e: 68fa ldr r2, [r7, #12] 8009170: 7812 ldrb r2, [r2, #0] 8009172: 4293 cmp r3, r2 8009174: d91f bls.n 80091b6 { ptr = desc->bLength; 8009176: 68fb ldr r3, [r7, #12] 8009178: 781b ldrb r3, [r3, #0] 800917a: 817b strh r3, [r7, #10] while (ptr < desc->wTotalLength) 800917c: e013 b.n 80091a6 { pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); 800917e: f107 030a add.w r3, r7, #10 8009182: 4619 mov r1, r3 8009184: 6978 ldr r0, [r7, #20] 8009186: f000 f81b bl 80091c0 800918a: 6178 str r0, [r7, #20] if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) 800918c: 697b ldr r3, [r7, #20] 800918e: 785b ldrb r3, [r3, #1] 8009190: 2b05 cmp r3, #5 8009192: d108 bne.n 80091a6 { pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; 8009194: 697b ldr r3, [r7, #20] 8009196: 613b str r3, [r7, #16] if (pEpDesc->bEndpointAddress == EpAddr) 8009198: 693b ldr r3, [r7, #16] 800919a: 789b ldrb r3, [r3, #2] 800919c: 78fa ldrb r2, [r7, #3] 800919e: 429a cmp r2, r3 80091a0: d008 beq.n 80091b4 { break; } else { pEpDesc = NULL; 80091a2: 2300 movs r3, #0 80091a4: 613b str r3, [r7, #16] while (ptr < desc->wTotalLength) 80091a6: 68fb ldr r3, [r7, #12] 80091a8: 885b ldrh r3, [r3, #2] 80091aa: b29a uxth r2, r3 80091ac: 897b ldrh r3, [r7, #10] 80091ae: 429a cmp r2, r3 80091b0: d8e5 bhi.n 800917e 80091b2: e000 b.n 80091b6 break; 80091b4: bf00 nop } } } } return (void *)pEpDesc; 80091b6: 693b ldr r3, [r7, #16] } 80091b8: 4618 mov r0, r3 80091ba: 3718 adds r7, #24 80091bc: 46bd mov sp, r7 80091be: bd80 pop {r7, pc} 080091c0 : * @param buf: Buffer where the descriptor is available * @param ptr: data pointer inside the descriptor * @retval next header */ USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) { 80091c0: b480 push {r7} 80091c2: b085 sub sp, #20 80091c4: af00 add r7, sp, #0 80091c6: 6078 str r0, [r7, #4] 80091c8: 6039 str r1, [r7, #0] USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; 80091ca: 687b ldr r3, [r7, #4] 80091cc: 60fb str r3, [r7, #12] *ptr += pnext->bLength; 80091ce: 683b ldr r3, [r7, #0] 80091d0: 881b ldrh r3, [r3, #0] 80091d2: 68fa ldr r2, [r7, #12] 80091d4: 7812 ldrb r2, [r2, #0] 80091d6: 4413 add r3, r2 80091d8: b29a uxth r2, r3 80091da: 683b ldr r3, [r7, #0] 80091dc: 801a strh r2, [r3, #0] pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); 80091de: 68fb ldr r3, [r7, #12] 80091e0: 781b ldrb r3, [r3, #0] 80091e2: 461a mov r2, r3 80091e4: 687b ldr r3, [r7, #4] 80091e6: 4413 add r3, r2 80091e8: 60fb str r3, [r7, #12] return (pnext); 80091ea: 68fb ldr r3, [r7, #12] } 80091ec: 4618 mov r0, r3 80091ee: 3714 adds r7, #20 80091f0: 46bd mov sp, r7 80091f2: f85d 7b04 ldr.w r7, [sp], #4 80091f6: 4770 bx lr 080091f8 : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 80091f8: b480 push {r7} 80091fa: b087 sub sp, #28 80091fc: af00 add r7, sp, #0 80091fe: 6078 str r0, [r7, #4] uint16_t _SwapVal; uint16_t _Byte1; uint16_t _Byte2; uint8_t *_pbuff = addr; 8009200: 687b ldr r3, [r7, #4] 8009202: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 8009204: 697b ldr r3, [r7, #20] 8009206: 781b ldrb r3, [r3, #0] 8009208: 827b strh r3, [r7, #18] _pbuff++; 800920a: 697b ldr r3, [r7, #20] 800920c: 3301 adds r3, #1 800920e: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 8009210: 697b ldr r3, [r7, #20] 8009212: 781b ldrb r3, [r3, #0] 8009214: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 8009216: f9b7 3010 ldrsh.w r3, [r7, #16] 800921a: 021b lsls r3, r3, #8 800921c: b21a sxth r2, r3 800921e: f9b7 3012 ldrsh.w r3, [r7, #18] 8009222: 4313 orrs r3, r2 8009224: b21b sxth r3, r3 8009226: 81fb strh r3, [r7, #14] return _SwapVal; 8009228: 89fb ldrh r3, [r7, #14] } 800922a: 4618 mov r0, r3 800922c: 371c adds r7, #28 800922e: 46bd mov sp, r7 8009230: f85d 7b04 ldr.w r7, [sp], #4 8009234: 4770 bx lr ... 08009238 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009238: b580 push {r7, lr} 800923a: b084 sub sp, #16 800923c: af00 add r7, sp, #0 800923e: 6078 str r0, [r7, #4] 8009240: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8009242: 2300 movs r3, #0 8009244: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009246: 683b ldr r3, [r7, #0] 8009248: 781b ldrb r3, [r3, #0] 800924a: f003 0360 and.w r3, r3, #96 @ 0x60 800924e: 2b40 cmp r3, #64 @ 0x40 8009250: d005 beq.n 800925e 8009252: 2b40 cmp r3, #64 @ 0x40 8009254: d857 bhi.n 8009306 8009256: 2b00 cmp r3, #0 8009258: d00f beq.n 800927a 800925a: 2b20 cmp r3, #32 800925c: d153 bne.n 8009306 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); 800925e: 687b ldr r3, [r7, #4] 8009260: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009264: 687b ldr r3, [r7, #4] 8009266: 32ae adds r2, #174 @ 0xae 8009268: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800926c: 689b ldr r3, [r3, #8] 800926e: 6839 ldr r1, [r7, #0] 8009270: 6878 ldr r0, [r7, #4] 8009272: 4798 blx r3 8009274: 4603 mov r3, r0 8009276: 73fb strb r3, [r7, #15] break; 8009278: e04a b.n 8009310 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 800927a: 683b ldr r3, [r7, #0] 800927c: 785b ldrb r3, [r3, #1] 800927e: 2b09 cmp r3, #9 8009280: d83b bhi.n 80092fa 8009282: a201 add r2, pc, #4 @ (adr r2, 8009288 ) 8009284: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009288: 080092dd .word 0x080092dd 800928c: 080092f1 .word 0x080092f1 8009290: 080092fb .word 0x080092fb 8009294: 080092e7 .word 0x080092e7 8009298: 080092fb .word 0x080092fb 800929c: 080092bb .word 0x080092bb 80092a0: 080092b1 .word 0x080092b1 80092a4: 080092fb .word 0x080092fb 80092a8: 080092d3 .word 0x080092d3 80092ac: 080092c5 .word 0x080092c5 { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 80092b0: 6839 ldr r1, [r7, #0] 80092b2: 6878 ldr r0, [r7, #4] 80092b4: f000 fa3e bl 8009734 break; 80092b8: e024 b.n 8009304 case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 80092ba: 6839 ldr r1, [r7, #0] 80092bc: 6878 ldr r0, [r7, #4] 80092be: f000 fbcd bl 8009a5c break; 80092c2: e01f b.n 8009304 case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 80092c4: 6839 ldr r1, [r7, #0] 80092c6: 6878 ldr r0, [r7, #4] 80092c8: f000 fc0c bl 8009ae4 80092cc: 4603 mov r3, r0 80092ce: 73fb strb r3, [r7, #15] break; 80092d0: e018 b.n 8009304 case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 80092d2: 6839 ldr r1, [r7, #0] 80092d4: 6878 ldr r0, [r7, #4] 80092d6: f000 fcaf bl 8009c38 break; 80092da: e013 b.n 8009304 case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 80092dc: 6839 ldr r1, [r7, #0] 80092de: 6878 ldr r0, [r7, #4] 80092e0: f000 fce0 bl 8009ca4 break; 80092e4: e00e b.n 8009304 case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 80092e6: 6839 ldr r1, [r7, #0] 80092e8: 6878 ldr r0, [r7, #4] 80092ea: f000 fd0f bl 8009d0c break; 80092ee: e009 b.n 8009304 case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 80092f0: 6839 ldr r1, [r7, #0] 80092f2: 6878 ldr r0, [r7, #4] 80092f4: f000 fd33 bl 8009d5e break; 80092f8: e004 b.n 8009304 default: USBD_CtlError(pdev, req); 80092fa: 6839 ldr r1, [r7, #0] 80092fc: 6878 ldr r0, [r7, #4] 80092fe: f000 fd8a bl 8009e16 break; 8009302: bf00 nop } break; 8009304: e004 b.n 8009310 default: USBD_CtlError(pdev, req); 8009306: 6839 ldr r1, [r7, #0] 8009308: 6878 ldr r0, [r7, #4] 800930a: f000 fd84 bl 8009e16 break; 800930e: bf00 nop } return ret; 8009310: 7bfb ldrb r3, [r7, #15] } 8009312: 4618 mov r0, r3 8009314: 3710 adds r7, #16 8009316: 46bd mov sp, r7 8009318: bd80 pop {r7, pc} 800931a: bf00 nop 0800931c : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800931c: b580 push {r7, lr} 800931e: b084 sub sp, #16 8009320: af00 add r7, sp, #0 8009322: 6078 str r0, [r7, #4] 8009324: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8009326: 2300 movs r3, #0 8009328: 73fb strb r3, [r7, #15] uint8_t idx; switch (req->bmRequest & USB_REQ_TYPE_MASK) 800932a: 683b ldr r3, [r7, #0] 800932c: 781b ldrb r3, [r3, #0] 800932e: f003 0360 and.w r3, r3, #96 @ 0x60 8009332: 2b40 cmp r3, #64 @ 0x40 8009334: d005 beq.n 8009342 8009336: 2b40 cmp r3, #64 @ 0x40 8009338: d852 bhi.n 80093e0 800933a: 2b00 cmp r3, #0 800933c: d001 beq.n 8009342 800933e: 2b20 cmp r3, #32 8009340: d14e bne.n 80093e0 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 8009342: 687b ldr r3, [r7, #4] 8009344: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009348: b2db uxtb r3, r3 800934a: 3b01 subs r3, #1 800934c: 2b02 cmp r3, #2 800934e: d840 bhi.n 80093d2 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 8009350: 683b ldr r3, [r7, #0] 8009352: 889b ldrh r3, [r3, #4] 8009354: b2db uxtb r3, r3 8009356: 2b01 cmp r3, #1 8009358: d836 bhi.n 80093c8 { /* Get the class index relative to this interface */ idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); 800935a: 683b ldr r3, [r7, #0] 800935c: 889b ldrh r3, [r3, #4] 800935e: b2db uxtb r3, r3 8009360: 4619 mov r1, r3 8009362: 6878 ldr r0, [r7, #4] 8009364: f7ff feda bl 800911c 8009368: 4603 mov r3, r0 800936a: 73bb strb r3, [r7, #14] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800936c: 7bbb ldrb r3, [r7, #14] 800936e: 2bff cmp r3, #255 @ 0xff 8009370: d01d beq.n 80093ae 8009372: 7bbb ldrb r3, [r7, #14] 8009374: 2b00 cmp r3, #0 8009376: d11a bne.n 80093ae { /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8009378: 7bba ldrb r2, [r7, #14] 800937a: 687b ldr r3, [r7, #4] 800937c: 32ae adds r2, #174 @ 0xae 800937e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009382: 689b ldr r3, [r3, #8] 8009384: 2b00 cmp r3, #0 8009386: d00f beq.n 80093a8 { pdev->classId = idx; 8009388: 7bba ldrb r2, [r7, #14] 800938a: 687b ldr r3, [r7, #4] 800938c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 8009390: 7bba ldrb r2, [r7, #14] 8009392: 687b ldr r3, [r7, #4] 8009394: 32ae adds r2, #174 @ 0xae 8009396: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800939a: 689b ldr r3, [r3, #8] 800939c: 6839 ldr r1, [r7, #0] 800939e: 6878 ldr r0, [r7, #4] 80093a0: 4798 blx r3 80093a2: 4603 mov r3, r0 80093a4: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 80093a6: e004 b.n 80093b2 } else { /* should never reach this condition */ ret = USBD_FAIL; 80093a8: 2303 movs r3, #3 80093aa: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 80093ac: e001 b.n 80093b2 } } else { /* No relative interface found */ ret = USBD_FAIL; 80093ae: 2303 movs r3, #3 80093b0: 73fb strb r3, [r7, #15] } if ((req->wLength == 0U) && (ret == USBD_OK)) 80093b2: 683b ldr r3, [r7, #0] 80093b4: 88db ldrh r3, [r3, #6] 80093b6: 2b00 cmp r3, #0 80093b8: d110 bne.n 80093dc 80093ba: 7bfb ldrb r3, [r7, #15] 80093bc: 2b00 cmp r3, #0 80093be: d10d bne.n 80093dc { (void)USBD_CtlSendStatus(pdev); 80093c0: 6878 ldr r0, [r7, #4] 80093c2: f000 fde5 bl 8009f90 } else { USBD_CtlError(pdev, req); } break; 80093c6: e009 b.n 80093dc USBD_CtlError(pdev, req); 80093c8: 6839 ldr r1, [r7, #0] 80093ca: 6878 ldr r0, [r7, #4] 80093cc: f000 fd23 bl 8009e16 break; 80093d0: e004 b.n 80093dc default: USBD_CtlError(pdev, req); 80093d2: 6839 ldr r1, [r7, #0] 80093d4: 6878 ldr r0, [r7, #4] 80093d6: f000 fd1e bl 8009e16 break; 80093da: e000 b.n 80093de break; 80093dc: bf00 nop } break; 80093de: e004 b.n 80093ea default: USBD_CtlError(pdev, req); 80093e0: 6839 ldr r1, [r7, #0] 80093e2: 6878 ldr r0, [r7, #4] 80093e4: f000 fd17 bl 8009e16 break; 80093e8: bf00 nop } return ret; 80093ea: 7bfb ldrb r3, [r7, #15] } 80093ec: 4618 mov r0, r3 80093ee: 3710 adds r7, #16 80093f0: 46bd mov sp, r7 80093f2: bd80 pop {r7, pc} 080093f4 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80093f4: b580 push {r7, lr} 80093f6: b084 sub sp, #16 80093f8: af00 add r7, sp, #0 80093fa: 6078 str r0, [r7, #4] 80093fc: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; uint8_t idx; USBD_StatusTypeDef ret = USBD_OK; 80093fe: 2300 movs r3, #0 8009400: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 8009402: 683b ldr r3, [r7, #0] 8009404: 889b ldrh r3, [r3, #4] 8009406: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009408: 683b ldr r3, [r7, #0] 800940a: 781b ldrb r3, [r3, #0] 800940c: f003 0360 and.w r3, r3, #96 @ 0x60 8009410: 2b40 cmp r3, #64 @ 0x40 8009412: d007 beq.n 8009424 8009414: 2b40 cmp r3, #64 @ 0x40 8009416: f200 8181 bhi.w 800971c 800941a: 2b00 cmp r3, #0 800941c: d02a beq.n 8009474 800941e: 2b20 cmp r3, #32 8009420: f040 817c bne.w 800971c { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: /* Get the class index relative to this endpoint */ idx = USBD_CoreFindEP(pdev, ep_addr); 8009424: 7bbb ldrb r3, [r7, #14] 8009426: 4619 mov r1, r3 8009428: 6878 ldr r0, [r7, #4] 800942a: f7ff fe84 bl 8009136 800942e: 4603 mov r3, r0 8009430: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009432: 7b7b ldrb r3, [r7, #13] 8009434: 2bff cmp r3, #255 @ 0xff 8009436: f000 8176 beq.w 8009726 800943a: 7b7b ldrb r3, [r7, #13] 800943c: 2b00 cmp r3, #0 800943e: f040 8172 bne.w 8009726 { pdev->classId = idx; 8009442: 7b7a ldrb r2, [r7, #13] 8009444: 687b ldr r3, [r7, #4] 8009446: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 800944a: 7b7a ldrb r2, [r7, #13] 800944c: 687b ldr r3, [r7, #4] 800944e: 32ae adds r2, #174 @ 0xae 8009450: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009454: 689b ldr r3, [r3, #8] 8009456: 2b00 cmp r3, #0 8009458: f000 8165 beq.w 8009726 { ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); 800945c: 7b7a ldrb r2, [r7, #13] 800945e: 687b ldr r3, [r7, #4] 8009460: 32ae adds r2, #174 @ 0xae 8009462: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009466: 689b ldr r3, [r3, #8] 8009468: 6839 ldr r1, [r7, #0] 800946a: 6878 ldr r0, [r7, #4] 800946c: 4798 blx r3 800946e: 4603 mov r3, r0 8009470: 73fb strb r3, [r7, #15] } } break; 8009472: e158 b.n 8009726 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8009474: 683b ldr r3, [r7, #0] 8009476: 785b ldrb r3, [r3, #1] 8009478: 2b03 cmp r3, #3 800947a: d008 beq.n 800948e 800947c: 2b03 cmp r3, #3 800947e: f300 8147 bgt.w 8009710 8009482: 2b00 cmp r3, #0 8009484: f000 809b beq.w 80095be 8009488: 2b01 cmp r3, #1 800948a: d03c beq.n 8009506 800948c: e140 b.n 8009710 { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 800948e: 687b ldr r3, [r7, #4] 8009490: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009494: b2db uxtb r3, r3 8009496: 2b02 cmp r3, #2 8009498: d002 beq.n 80094a0 800949a: 2b03 cmp r3, #3 800949c: d016 beq.n 80094cc 800949e: e02c b.n 80094fa { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80094a0: 7bbb ldrb r3, [r7, #14] 80094a2: 2b00 cmp r3, #0 80094a4: d00d beq.n 80094c2 80094a6: 7bbb ldrb r3, [r7, #14] 80094a8: 2b80 cmp r3, #128 @ 0x80 80094aa: d00a beq.n 80094c2 { (void)USBD_LL_StallEP(pdev, ep_addr); 80094ac: 7bbb ldrb r3, [r7, #14] 80094ae: 4619 mov r1, r3 80094b0: 6878 ldr r0, [r7, #4] 80094b2: f001 f8e3 bl 800a67c (void)USBD_LL_StallEP(pdev, 0x80U); 80094b6: 2180 movs r1, #128 @ 0x80 80094b8: 6878 ldr r0, [r7, #4] 80094ba: f001 f8df bl 800a67c 80094be: bf00 nop } else { USBD_CtlError(pdev, req); } break; 80094c0: e020 b.n 8009504 USBD_CtlError(pdev, req); 80094c2: 6839 ldr r1, [r7, #0] 80094c4: 6878 ldr r0, [r7, #4] 80094c6: f000 fca6 bl 8009e16 break; 80094ca: e01b b.n 8009504 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 80094cc: 683b ldr r3, [r7, #0] 80094ce: 885b ldrh r3, [r3, #2] 80094d0: 2b00 cmp r3, #0 80094d2: d10e bne.n 80094f2 { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 80094d4: 7bbb ldrb r3, [r7, #14] 80094d6: 2b00 cmp r3, #0 80094d8: d00b beq.n 80094f2 80094da: 7bbb ldrb r3, [r7, #14] 80094dc: 2b80 cmp r3, #128 @ 0x80 80094de: d008 beq.n 80094f2 80094e0: 683b ldr r3, [r7, #0] 80094e2: 88db ldrh r3, [r3, #6] 80094e4: 2b00 cmp r3, #0 80094e6: d104 bne.n 80094f2 { (void)USBD_LL_StallEP(pdev, ep_addr); 80094e8: 7bbb ldrb r3, [r7, #14] 80094ea: 4619 mov r1, r3 80094ec: 6878 ldr r0, [r7, #4] 80094ee: f001 f8c5 bl 800a67c } } (void)USBD_CtlSendStatus(pdev); 80094f2: 6878 ldr r0, [r7, #4] 80094f4: f000 fd4c bl 8009f90 break; 80094f8: e004 b.n 8009504 default: USBD_CtlError(pdev, req); 80094fa: 6839 ldr r1, [r7, #0] 80094fc: 6878 ldr r0, [r7, #4] 80094fe: f000 fc8a bl 8009e16 break; 8009502: bf00 nop } break; 8009504: e109 b.n 800971a case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 8009506: 687b ldr r3, [r7, #4] 8009508: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800950c: b2db uxtb r3, r3 800950e: 2b02 cmp r3, #2 8009510: d002 beq.n 8009518 8009512: 2b03 cmp r3, #3 8009514: d016 beq.n 8009544 8009516: e04b b.n 80095b0 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8009518: 7bbb ldrb r3, [r7, #14] 800951a: 2b00 cmp r3, #0 800951c: d00d beq.n 800953a 800951e: 7bbb ldrb r3, [r7, #14] 8009520: 2b80 cmp r3, #128 @ 0x80 8009522: d00a beq.n 800953a { (void)USBD_LL_StallEP(pdev, ep_addr); 8009524: 7bbb ldrb r3, [r7, #14] 8009526: 4619 mov r1, r3 8009528: 6878 ldr r0, [r7, #4] 800952a: f001 f8a7 bl 800a67c (void)USBD_LL_StallEP(pdev, 0x80U); 800952e: 2180 movs r1, #128 @ 0x80 8009530: 6878 ldr r0, [r7, #4] 8009532: f001 f8a3 bl 800a67c 8009536: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8009538: e040 b.n 80095bc USBD_CtlError(pdev, req); 800953a: 6839 ldr r1, [r7, #0] 800953c: 6878 ldr r0, [r7, #4] 800953e: f000 fc6a bl 8009e16 break; 8009542: e03b b.n 80095bc case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8009544: 683b ldr r3, [r7, #0] 8009546: 885b ldrh r3, [r3, #2] 8009548: 2b00 cmp r3, #0 800954a: d136 bne.n 80095ba { if ((ep_addr & 0x7FU) != 0x00U) 800954c: 7bbb ldrb r3, [r7, #14] 800954e: f003 037f and.w r3, r3, #127 @ 0x7f 8009552: 2b00 cmp r3, #0 8009554: d004 beq.n 8009560 { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 8009556: 7bbb ldrb r3, [r7, #14] 8009558: 4619 mov r1, r3 800955a: 6878 ldr r0, [r7, #4] 800955c: f001 f8ad bl 800a6ba } (void)USBD_CtlSendStatus(pdev); 8009560: 6878 ldr r0, [r7, #4] 8009562: f000 fd15 bl 8009f90 /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ep_addr); 8009566: 7bbb ldrb r3, [r7, #14] 8009568: 4619 mov r1, r3 800956a: 6878 ldr r0, [r7, #4] 800956c: f7ff fde3 bl 8009136 8009570: 4603 mov r3, r0 8009572: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009574: 7b7b ldrb r3, [r7, #13] 8009576: 2bff cmp r3, #255 @ 0xff 8009578: d01f beq.n 80095ba 800957a: 7b7b ldrb r3, [r7, #13] 800957c: 2b00 cmp r3, #0 800957e: d11c bne.n 80095ba { pdev->classId = idx; 8009580: 7b7a ldrb r2, [r7, #13] 8009582: 687b ldr r3, [r7, #4] 8009584: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8009588: 7b7a ldrb r2, [r7, #13] 800958a: 687b ldr r3, [r7, #4] 800958c: 32ae adds r2, #174 @ 0xae 800958e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009592: 689b ldr r3, [r3, #8] 8009594: 2b00 cmp r3, #0 8009596: d010 beq.n 80095ba { ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 8009598: 7b7a ldrb r2, [r7, #13] 800959a: 687b ldr r3, [r7, #4] 800959c: 32ae adds r2, #174 @ 0xae 800959e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80095a2: 689b ldr r3, [r3, #8] 80095a4: 6839 ldr r1, [r7, #0] 80095a6: 6878 ldr r0, [r7, #4] 80095a8: 4798 blx r3 80095aa: 4603 mov r3, r0 80095ac: 73fb strb r3, [r7, #15] } } } break; 80095ae: e004 b.n 80095ba default: USBD_CtlError(pdev, req); 80095b0: 6839 ldr r1, [r7, #0] 80095b2: 6878 ldr r0, [r7, #4] 80095b4: f000 fc2f bl 8009e16 break; 80095b8: e000 b.n 80095bc break; 80095ba: bf00 nop } break; 80095bc: e0ad b.n 800971a case USB_REQ_GET_STATUS: switch (pdev->dev_state) 80095be: 687b ldr r3, [r7, #4] 80095c0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80095c4: b2db uxtb r3, r3 80095c6: 2b02 cmp r3, #2 80095c8: d002 beq.n 80095d0 80095ca: 2b03 cmp r3, #3 80095cc: d033 beq.n 8009636 80095ce: e099 b.n 8009704 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80095d0: 7bbb ldrb r3, [r7, #14] 80095d2: 2b00 cmp r3, #0 80095d4: d007 beq.n 80095e6 80095d6: 7bbb ldrb r3, [r7, #14] 80095d8: 2b80 cmp r3, #128 @ 0x80 80095da: d004 beq.n 80095e6 { USBD_CtlError(pdev, req); 80095dc: 6839 ldr r1, [r7, #0] 80095de: 6878 ldr r0, [r7, #4] 80095e0: f000 fc19 bl 8009e16 break; 80095e4: e093 b.n 800970e } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80095e6: f997 300e ldrsb.w r3, [r7, #14] 80095ea: 2b00 cmp r3, #0 80095ec: da0b bge.n 8009606 80095ee: 7bbb ldrb r3, [r7, #14] 80095f0: f003 027f and.w r2, r3, #127 @ 0x7f 80095f4: 4613 mov r3, r2 80095f6: 009b lsls r3, r3, #2 80095f8: 4413 add r3, r2 80095fa: 009b lsls r3, r3, #2 80095fc: 3310 adds r3, #16 80095fe: 687a ldr r2, [r7, #4] 8009600: 4413 add r3, r2 8009602: 3304 adds r3, #4 8009604: e00b b.n 800961e &pdev->ep_out[ep_addr & 0x7FU]; 8009606: 7bbb ldrb r3, [r7, #14] 8009608: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800960c: 4613 mov r3, r2 800960e: 009b lsls r3, r3, #2 8009610: 4413 add r3, r2 8009612: 009b lsls r3, r3, #2 8009614: f503 73a8 add.w r3, r3, #336 @ 0x150 8009618: 687a ldr r2, [r7, #4] 800961a: 4413 add r3, r2 800961c: 3304 adds r3, #4 800961e: 60bb str r3, [r7, #8] pep->status = 0x0000U; 8009620: 68bb ldr r3, [r7, #8] 8009622: 2200 movs r2, #0 8009624: 739a strb r2, [r3, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 8009626: 68bb ldr r3, [r7, #8] 8009628: 330e adds r3, #14 800962a: 2202 movs r2, #2 800962c: 4619 mov r1, r3 800962e: 6878 ldr r0, [r7, #4] 8009630: f000 fc6e bl 8009f10 break; 8009634: e06b b.n 800970e case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 8009636: f997 300e ldrsb.w r3, [r7, #14] 800963a: 2b00 cmp r3, #0 800963c: da11 bge.n 8009662 { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 800963e: 7bbb ldrb r3, [r7, #14] 8009640: f003 020f and.w r2, r3, #15 8009644: 6879 ldr r1, [r7, #4] 8009646: 4613 mov r3, r2 8009648: 009b lsls r3, r3, #2 800964a: 4413 add r3, r2 800964c: 009b lsls r3, r3, #2 800964e: 440b add r3, r1 8009650: 3323 adds r3, #35 @ 0x23 8009652: 781b ldrb r3, [r3, #0] 8009654: 2b00 cmp r3, #0 8009656: d117 bne.n 8009688 { USBD_CtlError(pdev, req); 8009658: 6839 ldr r1, [r7, #0] 800965a: 6878 ldr r0, [r7, #4] 800965c: f000 fbdb bl 8009e16 break; 8009660: e055 b.n 800970e } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 8009662: 7bbb ldrb r3, [r7, #14] 8009664: f003 020f and.w r2, r3, #15 8009668: 6879 ldr r1, [r7, #4] 800966a: 4613 mov r3, r2 800966c: 009b lsls r3, r3, #2 800966e: 4413 add r3, r2 8009670: 009b lsls r3, r3, #2 8009672: 440b add r3, r1 8009674: f203 1363 addw r3, r3, #355 @ 0x163 8009678: 781b ldrb r3, [r3, #0] 800967a: 2b00 cmp r3, #0 800967c: d104 bne.n 8009688 { USBD_CtlError(pdev, req); 800967e: 6839 ldr r1, [r7, #0] 8009680: 6878 ldr r0, [r7, #4] 8009682: f000 fbc8 bl 8009e16 break; 8009686: e042 b.n 800970e } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8009688: f997 300e ldrsb.w r3, [r7, #14] 800968c: 2b00 cmp r3, #0 800968e: da0b bge.n 80096a8 8009690: 7bbb ldrb r3, [r7, #14] 8009692: f003 027f and.w r2, r3, #127 @ 0x7f 8009696: 4613 mov r3, r2 8009698: 009b lsls r3, r3, #2 800969a: 4413 add r3, r2 800969c: 009b lsls r3, r3, #2 800969e: 3310 adds r3, #16 80096a0: 687a ldr r2, [r7, #4] 80096a2: 4413 add r3, r2 80096a4: 3304 adds r3, #4 80096a6: e00b b.n 80096c0 &pdev->ep_out[ep_addr & 0x7FU]; 80096a8: 7bbb ldrb r3, [r7, #14] 80096aa: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80096ae: 4613 mov r3, r2 80096b0: 009b lsls r3, r3, #2 80096b2: 4413 add r3, r2 80096b4: 009b lsls r3, r3, #2 80096b6: f503 73a8 add.w r3, r3, #336 @ 0x150 80096ba: 687a ldr r2, [r7, #4] 80096bc: 4413 add r3, r2 80096be: 3304 adds r3, #4 80096c0: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 80096c2: 7bbb ldrb r3, [r7, #14] 80096c4: 2b00 cmp r3, #0 80096c6: d002 beq.n 80096ce 80096c8: 7bbb ldrb r3, [r7, #14] 80096ca: 2b80 cmp r3, #128 @ 0x80 80096cc: d103 bne.n 80096d6 { pep->status = 0x0000U; 80096ce: 68bb ldr r3, [r7, #8] 80096d0: 2200 movs r2, #0 80096d2: 739a strb r2, [r3, #14] 80096d4: e00e b.n 80096f4 } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 80096d6: 7bbb ldrb r3, [r7, #14] 80096d8: 4619 mov r1, r3 80096da: 6878 ldr r0, [r7, #4] 80096dc: f001 f80c bl 800a6f8 80096e0: 4603 mov r3, r0 80096e2: 2b00 cmp r3, #0 80096e4: d003 beq.n 80096ee { pep->status = 0x0001U; 80096e6: 68bb ldr r3, [r7, #8] 80096e8: 2201 movs r2, #1 80096ea: 739a strb r2, [r3, #14] 80096ec: e002 b.n 80096f4 } else { pep->status = 0x0000U; 80096ee: 68bb ldr r3, [r7, #8] 80096f0: 2200 movs r2, #0 80096f2: 739a strb r2, [r3, #14] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 80096f4: 68bb ldr r3, [r7, #8] 80096f6: 330e adds r3, #14 80096f8: 2202 movs r2, #2 80096fa: 4619 mov r1, r3 80096fc: 6878 ldr r0, [r7, #4] 80096fe: f000 fc07 bl 8009f10 break; 8009702: e004 b.n 800970e default: USBD_CtlError(pdev, req); 8009704: 6839 ldr r1, [r7, #0] 8009706: 6878 ldr r0, [r7, #4] 8009708: f000 fb85 bl 8009e16 break; 800970c: bf00 nop } break; 800970e: e004 b.n 800971a default: USBD_CtlError(pdev, req); 8009710: 6839 ldr r1, [r7, #0] 8009712: 6878 ldr r0, [r7, #4] 8009714: f000 fb7f bl 8009e16 break; 8009718: bf00 nop } break; 800971a: e005 b.n 8009728 default: USBD_CtlError(pdev, req); 800971c: 6839 ldr r1, [r7, #0] 800971e: 6878 ldr r0, [r7, #4] 8009720: f000 fb79 bl 8009e16 break; 8009724: e000 b.n 8009728 break; 8009726: bf00 nop } return ret; 8009728: 7bfb ldrb r3, [r7, #15] } 800972a: 4618 mov r0, r3 800972c: 3710 adds r7, #16 800972e: 46bd mov sp, r7 8009730: bd80 pop {r7, pc} ... 08009734 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009734: b580 push {r7, lr} 8009736: b084 sub sp, #16 8009738: af00 add r7, sp, #0 800973a: 6078 str r0, [r7, #4] 800973c: 6039 str r1, [r7, #0] uint16_t len = 0U; 800973e: 2300 movs r3, #0 8009740: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 8009742: 2300 movs r3, #0 8009744: 60fb str r3, [r7, #12] uint8_t err = 0U; 8009746: 2300 movs r3, #0 8009748: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 800974a: 683b ldr r3, [r7, #0] 800974c: 885b ldrh r3, [r3, #2] 800974e: 0a1b lsrs r3, r3, #8 8009750: b29b uxth r3, r3 8009752: 3b01 subs r3, #1 8009754: 2b0e cmp r3, #14 8009756: f200 8152 bhi.w 80099fe 800975a: a201 add r2, pc, #4 @ (adr r2, 8009760 ) 800975c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009760: 080097d1 .word 0x080097d1 8009764: 080097e9 .word 0x080097e9 8009768: 08009829 .word 0x08009829 800976c: 080099ff .word 0x080099ff 8009770: 080099ff .word 0x080099ff 8009774: 0800999f .word 0x0800999f 8009778: 080099cb .word 0x080099cb 800977c: 080099ff .word 0x080099ff 8009780: 080099ff .word 0x080099ff 8009784: 080099ff .word 0x080099ff 8009788: 080099ff .word 0x080099ff 800978c: 080099ff .word 0x080099ff 8009790: 080099ff .word 0x080099ff 8009794: 080099ff .word 0x080099ff 8009798: 0800979d .word 0x0800979d { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) 800979c: 687b ldr r3, [r7, #4] 800979e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80097a2: 69db ldr r3, [r3, #28] 80097a4: 2b00 cmp r3, #0 80097a6: d00b beq.n 80097c0 { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); 80097a8: 687b ldr r3, [r7, #4] 80097aa: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80097ae: 69db ldr r3, [r3, #28] 80097b0: 687a ldr r2, [r7, #4] 80097b2: 7c12 ldrb r2, [r2, #16] 80097b4: f107 0108 add.w r1, r7, #8 80097b8: 4610 mov r0, r2 80097ba: 4798 blx r3 80097bc: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80097be: e126 b.n 8009a0e USBD_CtlError(pdev, req); 80097c0: 6839 ldr r1, [r7, #0] 80097c2: 6878 ldr r0, [r7, #4] 80097c4: f000 fb27 bl 8009e16 err++; 80097c8: 7afb ldrb r3, [r7, #11] 80097ca: 3301 adds r3, #1 80097cc: 72fb strb r3, [r7, #11] break; 80097ce: e11e b.n 8009a0e #endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 80097d0: 687b ldr r3, [r7, #4] 80097d2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80097d6: 681b ldr r3, [r3, #0] 80097d8: 687a ldr r2, [r7, #4] 80097da: 7c12 ldrb r2, [r2, #16] 80097dc: f107 0108 add.w r1, r7, #8 80097e0: 4610 mov r0, r2 80097e2: 4798 blx r3 80097e4: 60f8 str r0, [r7, #12] break; 80097e6: e112 b.n 8009a0e case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 80097e8: 687b ldr r3, [r7, #4] 80097ea: 7c1b ldrb r3, [r3, #16] 80097ec: 2b00 cmp r3, #0 80097ee: d10d bne.n 800980c pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); 80097f0: 687b ldr r3, [r7, #4] 80097f2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80097f6: 6a9b ldr r3, [r3, #40] @ 0x28 80097f8: f107 0208 add.w r2, r7, #8 80097fc: 4610 mov r0, r2 80097fe: 4798 blx r3 8009800: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 8009802: 68fb ldr r3, [r7, #12] 8009804: 3301 adds r3, #1 8009806: 2202 movs r2, #2 8009808: 701a strb r2, [r3, #0] { pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 800980a: e100 b.n 8009a0e pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); 800980c: 687b ldr r3, [r7, #4] 800980e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009812: 6adb ldr r3, [r3, #44] @ 0x2c 8009814: f107 0208 add.w r2, r7, #8 8009818: 4610 mov r0, r2 800981a: 4798 blx r3 800981c: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800981e: 68fb ldr r3, [r7, #12] 8009820: 3301 adds r3, #1 8009822: 2202 movs r2, #2 8009824: 701a strb r2, [r3, #0] break; 8009826: e0f2 b.n 8009a0e case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 8009828: 683b ldr r3, [r7, #0] 800982a: 885b ldrh r3, [r3, #2] 800982c: b2db uxtb r3, r3 800982e: 2b05 cmp r3, #5 8009830: f200 80ac bhi.w 800998c 8009834: a201 add r2, pc, #4 @ (adr r2, 800983c ) 8009836: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800983a: bf00 nop 800983c: 08009855 .word 0x08009855 8009840: 08009889 .word 0x08009889 8009844: 080098bd .word 0x080098bd 8009848: 080098f1 .word 0x080098f1 800984c: 08009925 .word 0x08009925 8009850: 08009959 .word 0x08009959 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 8009854: 687b ldr r3, [r7, #4] 8009856: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800985a: 685b ldr r3, [r3, #4] 800985c: 2b00 cmp r3, #0 800985e: d00b beq.n 8009878 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 8009860: 687b ldr r3, [r7, #4] 8009862: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009866: 685b ldr r3, [r3, #4] 8009868: 687a ldr r2, [r7, #4] 800986a: 7c12 ldrb r2, [r2, #16] 800986c: f107 0108 add.w r1, r7, #8 8009870: 4610 mov r0, r2 8009872: 4798 blx r3 8009874: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009876: e091 b.n 800999c USBD_CtlError(pdev, req); 8009878: 6839 ldr r1, [r7, #0] 800987a: 6878 ldr r0, [r7, #4] 800987c: f000 facb bl 8009e16 err++; 8009880: 7afb ldrb r3, [r7, #11] 8009882: 3301 adds r3, #1 8009884: 72fb strb r3, [r7, #11] break; 8009886: e089 b.n 800999c case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 8009888: 687b ldr r3, [r7, #4] 800988a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800988e: 689b ldr r3, [r3, #8] 8009890: 2b00 cmp r3, #0 8009892: d00b beq.n 80098ac { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 8009894: 687b ldr r3, [r7, #4] 8009896: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800989a: 689b ldr r3, [r3, #8] 800989c: 687a ldr r2, [r7, #4] 800989e: 7c12 ldrb r2, [r2, #16] 80098a0: f107 0108 add.w r1, r7, #8 80098a4: 4610 mov r0, r2 80098a6: 4798 blx r3 80098a8: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80098aa: e077 b.n 800999c USBD_CtlError(pdev, req); 80098ac: 6839 ldr r1, [r7, #0] 80098ae: 6878 ldr r0, [r7, #4] 80098b0: f000 fab1 bl 8009e16 err++; 80098b4: 7afb ldrb r3, [r7, #11] 80098b6: 3301 adds r3, #1 80098b8: 72fb strb r3, [r7, #11] break; 80098ba: e06f b.n 800999c case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 80098bc: 687b ldr r3, [r7, #4] 80098be: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80098c2: 68db ldr r3, [r3, #12] 80098c4: 2b00 cmp r3, #0 80098c6: d00b beq.n 80098e0 { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 80098c8: 687b ldr r3, [r7, #4] 80098ca: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80098ce: 68db ldr r3, [r3, #12] 80098d0: 687a ldr r2, [r7, #4] 80098d2: 7c12 ldrb r2, [r2, #16] 80098d4: f107 0108 add.w r1, r7, #8 80098d8: 4610 mov r0, r2 80098da: 4798 blx r3 80098dc: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80098de: e05d b.n 800999c USBD_CtlError(pdev, req); 80098e0: 6839 ldr r1, [r7, #0] 80098e2: 6878 ldr r0, [r7, #4] 80098e4: f000 fa97 bl 8009e16 err++; 80098e8: 7afb ldrb r3, [r7, #11] 80098ea: 3301 adds r3, #1 80098ec: 72fb strb r3, [r7, #11] break; 80098ee: e055 b.n 800999c case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 80098f0: 687b ldr r3, [r7, #4] 80098f2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80098f6: 691b ldr r3, [r3, #16] 80098f8: 2b00 cmp r3, #0 80098fa: d00b beq.n 8009914 { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 80098fc: 687b ldr r3, [r7, #4] 80098fe: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009902: 691b ldr r3, [r3, #16] 8009904: 687a ldr r2, [r7, #4] 8009906: 7c12 ldrb r2, [r2, #16] 8009908: f107 0108 add.w r1, r7, #8 800990c: 4610 mov r0, r2 800990e: 4798 blx r3 8009910: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009912: e043 b.n 800999c USBD_CtlError(pdev, req); 8009914: 6839 ldr r1, [r7, #0] 8009916: 6878 ldr r0, [r7, #4] 8009918: f000 fa7d bl 8009e16 err++; 800991c: 7afb ldrb r3, [r7, #11] 800991e: 3301 adds r3, #1 8009920: 72fb strb r3, [r7, #11] break; 8009922: e03b b.n 800999c case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 8009924: 687b ldr r3, [r7, #4] 8009926: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800992a: 695b ldr r3, [r3, #20] 800992c: 2b00 cmp r3, #0 800992e: d00b beq.n 8009948 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 8009930: 687b ldr r3, [r7, #4] 8009932: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009936: 695b ldr r3, [r3, #20] 8009938: 687a ldr r2, [r7, #4] 800993a: 7c12 ldrb r2, [r2, #16] 800993c: f107 0108 add.w r1, r7, #8 8009940: 4610 mov r0, r2 8009942: 4798 blx r3 8009944: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009946: e029 b.n 800999c USBD_CtlError(pdev, req); 8009948: 6839 ldr r1, [r7, #0] 800994a: 6878 ldr r0, [r7, #4] 800994c: f000 fa63 bl 8009e16 err++; 8009950: 7afb ldrb r3, [r7, #11] 8009952: 3301 adds r3, #1 8009954: 72fb strb r3, [r7, #11] break; 8009956: e021 b.n 800999c case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 8009958: 687b ldr r3, [r7, #4] 800995a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800995e: 699b ldr r3, [r3, #24] 8009960: 2b00 cmp r3, #0 8009962: d00b beq.n 800997c { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 8009964: 687b ldr r3, [r7, #4] 8009966: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800996a: 699b ldr r3, [r3, #24] 800996c: 687a ldr r2, [r7, #4] 800996e: 7c12 ldrb r2, [r2, #16] 8009970: f107 0108 add.w r1, r7, #8 8009974: 4610 mov r0, r2 8009976: 4798 blx r3 8009978: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800997a: e00f b.n 800999c USBD_CtlError(pdev, req); 800997c: 6839 ldr r1, [r7, #0] 800997e: 6878 ldr r0, [r7, #4] 8009980: f000 fa49 bl 8009e16 err++; 8009984: 7afb ldrb r3, [r7, #11] 8009986: 3301 adds r3, #1 8009988: 72fb strb r3, [r7, #11] break; 800998a: e007 b.n 800999c err++; } #endif /* USBD_SUPPORT_USER_STRING_DESC */ #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 800998c: 6839 ldr r1, [r7, #0] 800998e: 6878 ldr r0, [r7, #4] 8009990: f000 fa41 bl 8009e16 err++; 8009994: 7afb ldrb r3, [r7, #11] 8009996: 3301 adds r3, #1 8009998: 72fb strb r3, [r7, #11] #endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ break; 800999a: bf00 nop } break; 800999c: e037 b.n 8009a0e case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 800999e: 687b ldr r3, [r7, #4] 80099a0: 7c1b ldrb r3, [r3, #16] 80099a2: 2b00 cmp r3, #0 80099a4: d109 bne.n 80099ba pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); 80099a6: 687b ldr r3, [r7, #4] 80099a8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80099ac: 6b5b ldr r3, [r3, #52] @ 0x34 80099ae: f107 0208 add.w r2, r7, #8 80099b2: 4610 mov r0, r2 80099b4: 4798 blx r3 80099b6: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80099b8: e029 b.n 8009a0e USBD_CtlError(pdev, req); 80099ba: 6839 ldr r1, [r7, #0] 80099bc: 6878 ldr r0, [r7, #4] 80099be: f000 fa2a bl 8009e16 err++; 80099c2: 7afb ldrb r3, [r7, #11] 80099c4: 3301 adds r3, #1 80099c6: 72fb strb r3, [r7, #11] break; 80099c8: e021 b.n 8009a0e case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 80099ca: 687b ldr r3, [r7, #4] 80099cc: 7c1b ldrb r3, [r3, #16] 80099ce: 2b00 cmp r3, #0 80099d0: d10d bne.n 80099ee pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); 80099d2: 687b ldr r3, [r7, #4] 80099d4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80099d8: 6b1b ldr r3, [r3, #48] @ 0x30 80099da: f107 0208 add.w r2, r7, #8 80099de: 4610 mov r0, r2 80099e0: 4798 blx r3 80099e2: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 80099e4: 68fb ldr r3, [r7, #12] 80099e6: 3301 adds r3, #1 80099e8: 2207 movs r2, #7 80099ea: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 80099ec: e00f b.n 8009a0e USBD_CtlError(pdev, req); 80099ee: 6839 ldr r1, [r7, #0] 80099f0: 6878 ldr r0, [r7, #4] 80099f2: f000 fa10 bl 8009e16 err++; 80099f6: 7afb ldrb r3, [r7, #11] 80099f8: 3301 adds r3, #1 80099fa: 72fb strb r3, [r7, #11] break; 80099fc: e007 b.n 8009a0e default: USBD_CtlError(pdev, req); 80099fe: 6839 ldr r1, [r7, #0] 8009a00: 6878 ldr r0, [r7, #4] 8009a02: f000 fa08 bl 8009e16 err++; 8009a06: 7afb ldrb r3, [r7, #11] 8009a08: 3301 adds r3, #1 8009a0a: 72fb strb r3, [r7, #11] break; 8009a0c: bf00 nop } if (err != 0U) 8009a0e: 7afb ldrb r3, [r7, #11] 8009a10: 2b00 cmp r3, #0 8009a12: d11e bne.n 8009a52 { return; } if (req->wLength != 0U) 8009a14: 683b ldr r3, [r7, #0] 8009a16: 88db ldrh r3, [r3, #6] 8009a18: 2b00 cmp r3, #0 8009a1a: d016 beq.n 8009a4a { if (len != 0U) 8009a1c: 893b ldrh r3, [r7, #8] 8009a1e: 2b00 cmp r3, #0 8009a20: d00e beq.n 8009a40 { len = MIN(len, req->wLength); 8009a22: 683b ldr r3, [r7, #0] 8009a24: 88da ldrh r2, [r3, #6] 8009a26: 893b ldrh r3, [r7, #8] 8009a28: 4293 cmp r3, r2 8009a2a: bf28 it cs 8009a2c: 4613 movcs r3, r2 8009a2e: b29b uxth r3, r3 8009a30: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 8009a32: 893b ldrh r3, [r7, #8] 8009a34: 461a mov r2, r3 8009a36: 68f9 ldr r1, [r7, #12] 8009a38: 6878 ldr r0, [r7, #4] 8009a3a: f000 fa69 bl 8009f10 8009a3e: e009 b.n 8009a54 } else { USBD_CtlError(pdev, req); 8009a40: 6839 ldr r1, [r7, #0] 8009a42: 6878 ldr r0, [r7, #4] 8009a44: f000 f9e7 bl 8009e16 8009a48: e004 b.n 8009a54 } } else { (void)USBD_CtlSendStatus(pdev); 8009a4a: 6878 ldr r0, [r7, #4] 8009a4c: f000 faa0 bl 8009f90 8009a50: e000 b.n 8009a54 return; 8009a52: bf00 nop } } 8009a54: 3710 adds r7, #16 8009a56: 46bd mov sp, r7 8009a58: bd80 pop {r7, pc} 8009a5a: bf00 nop 08009a5c : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009a5c: b580 push {r7, lr} 8009a5e: b084 sub sp, #16 8009a60: af00 add r7, sp, #0 8009a62: 6078 str r0, [r7, #4] 8009a64: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 8009a66: 683b ldr r3, [r7, #0] 8009a68: 889b ldrh r3, [r3, #4] 8009a6a: 2b00 cmp r3, #0 8009a6c: d131 bne.n 8009ad2 8009a6e: 683b ldr r3, [r7, #0] 8009a70: 88db ldrh r3, [r3, #6] 8009a72: 2b00 cmp r3, #0 8009a74: d12d bne.n 8009ad2 8009a76: 683b ldr r3, [r7, #0] 8009a78: 885b ldrh r3, [r3, #2] 8009a7a: 2b7f cmp r3, #127 @ 0x7f 8009a7c: d829 bhi.n 8009ad2 { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 8009a7e: 683b ldr r3, [r7, #0] 8009a80: 885b ldrh r3, [r3, #2] 8009a82: b2db uxtb r3, r3 8009a84: f003 037f and.w r3, r3, #127 @ 0x7f 8009a88: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009a8a: 687b ldr r3, [r7, #4] 8009a8c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009a90: b2db uxtb r3, r3 8009a92: 2b03 cmp r3, #3 8009a94: d104 bne.n 8009aa0 { USBD_CtlError(pdev, req); 8009a96: 6839 ldr r1, [r7, #0] 8009a98: 6878 ldr r0, [r7, #4] 8009a9a: f000 f9bc bl 8009e16 if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009a9e: e01d b.n 8009adc } else { pdev->dev_address = dev_addr; 8009aa0: 687b ldr r3, [r7, #4] 8009aa2: 7bfa ldrb r2, [r7, #15] 8009aa4: f883 229e strb.w r2, [r3, #670] @ 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 8009aa8: 7bfb ldrb r3, [r7, #15] 8009aaa: 4619 mov r1, r3 8009aac: 6878 ldr r0, [r7, #4] 8009aae: f000 fe4f bl 800a750 (void)USBD_CtlSendStatus(pdev); 8009ab2: 6878 ldr r0, [r7, #4] 8009ab4: f000 fa6c bl 8009f90 if (dev_addr != 0U) 8009ab8: 7bfb ldrb r3, [r7, #15] 8009aba: 2b00 cmp r3, #0 8009abc: d004 beq.n 8009ac8 { pdev->dev_state = USBD_STATE_ADDRESSED; 8009abe: 687b ldr r3, [r7, #4] 8009ac0: 2202 movs r2, #2 8009ac2: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009ac6: e009 b.n 8009adc } else { pdev->dev_state = USBD_STATE_DEFAULT; 8009ac8: 687b ldr r3, [r7, #4] 8009aca: 2201 movs r2, #1 8009acc: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009ad0: e004 b.n 8009adc } } } else { USBD_CtlError(pdev, req); 8009ad2: 6839 ldr r1, [r7, #0] 8009ad4: 6878 ldr r0, [r7, #4] 8009ad6: f000 f99e bl 8009e16 } } 8009ada: bf00 nop 8009adc: bf00 nop 8009ade: 3710 adds r7, #16 8009ae0: 46bd mov sp, r7 8009ae2: bd80 pop {r7, pc} 08009ae4 : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009ae4: b580 push {r7, lr} 8009ae6: b084 sub sp, #16 8009ae8: af00 add r7, sp, #0 8009aea: 6078 str r0, [r7, #4] 8009aec: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8009aee: 2300 movs r3, #0 8009af0: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 8009af2: 683b ldr r3, [r7, #0] 8009af4: 885b ldrh r3, [r3, #2] 8009af6: b2da uxtb r2, r3 8009af8: 4b4e ldr r3, [pc, #312] @ (8009c34 ) 8009afa: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 8009afc: 4b4d ldr r3, [pc, #308] @ (8009c34 ) 8009afe: 781b ldrb r3, [r3, #0] 8009b00: 2b01 cmp r3, #1 8009b02: d905 bls.n 8009b10 { USBD_CtlError(pdev, req); 8009b04: 6839 ldr r1, [r7, #0] 8009b06: 6878 ldr r0, [r7, #4] 8009b08: f000 f985 bl 8009e16 return USBD_FAIL; 8009b0c: 2303 movs r3, #3 8009b0e: e08c b.n 8009c2a } switch (pdev->dev_state) 8009b10: 687b ldr r3, [r7, #4] 8009b12: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009b16: b2db uxtb r3, r3 8009b18: 2b02 cmp r3, #2 8009b1a: d002 beq.n 8009b22 8009b1c: 2b03 cmp r3, #3 8009b1e: d029 beq.n 8009b74 8009b20: e075 b.n 8009c0e { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 8009b22: 4b44 ldr r3, [pc, #272] @ (8009c34 ) 8009b24: 781b ldrb r3, [r3, #0] 8009b26: 2b00 cmp r3, #0 8009b28: d020 beq.n 8009b6c { pdev->dev_config = cfgidx; 8009b2a: 4b42 ldr r3, [pc, #264] @ (8009c34 ) 8009b2c: 781b ldrb r3, [r3, #0] 8009b2e: 461a mov r2, r3 8009b30: 687b ldr r3, [r7, #4] 8009b32: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8009b34: 4b3f ldr r3, [pc, #252] @ (8009c34 ) 8009b36: 781b ldrb r3, [r3, #0] 8009b38: 4619 mov r1, r3 8009b3a: 6878 ldr r0, [r7, #4] 8009b3c: f7fe ffa3 bl 8008a86 8009b40: 4603 mov r3, r0 8009b42: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8009b44: 7bfb ldrb r3, [r7, #15] 8009b46: 2b00 cmp r3, #0 8009b48: d008 beq.n 8009b5c { USBD_CtlError(pdev, req); 8009b4a: 6839 ldr r1, [r7, #0] 8009b4c: 6878 ldr r0, [r7, #4] 8009b4e: f000 f962 bl 8009e16 pdev->dev_state = USBD_STATE_ADDRESSED; 8009b52: 687b ldr r3, [r7, #4] 8009b54: 2202 movs r2, #2 8009b56: f883 229c strb.w r2, [r3, #668] @ 0x29c } else { (void)USBD_CtlSendStatus(pdev); } break; 8009b5a: e065 b.n 8009c28 (void)USBD_CtlSendStatus(pdev); 8009b5c: 6878 ldr r0, [r7, #4] 8009b5e: f000 fa17 bl 8009f90 pdev->dev_state = USBD_STATE_CONFIGURED; 8009b62: 687b ldr r3, [r7, #4] 8009b64: 2203 movs r2, #3 8009b66: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8009b6a: e05d b.n 8009c28 (void)USBD_CtlSendStatus(pdev); 8009b6c: 6878 ldr r0, [r7, #4] 8009b6e: f000 fa0f bl 8009f90 break; 8009b72: e059 b.n 8009c28 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 8009b74: 4b2f ldr r3, [pc, #188] @ (8009c34 ) 8009b76: 781b ldrb r3, [r3, #0] 8009b78: 2b00 cmp r3, #0 8009b7a: d112 bne.n 8009ba2 { pdev->dev_state = USBD_STATE_ADDRESSED; 8009b7c: 687b ldr r3, [r7, #4] 8009b7e: 2202 movs r2, #2 8009b80: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->dev_config = cfgidx; 8009b84: 4b2b ldr r3, [pc, #172] @ (8009c34 ) 8009b86: 781b ldrb r3, [r3, #0] 8009b88: 461a mov r2, r3 8009b8a: 687b ldr r3, [r7, #4] 8009b8c: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 8009b8e: 4b29 ldr r3, [pc, #164] @ (8009c34 ) 8009b90: 781b ldrb r3, [r3, #0] 8009b92: 4619 mov r1, r3 8009b94: 6878 ldr r0, [r7, #4] 8009b96: f7fe ff92 bl 8008abe (void)USBD_CtlSendStatus(pdev); 8009b9a: 6878 ldr r0, [r7, #4] 8009b9c: f000 f9f8 bl 8009f90 } else { (void)USBD_CtlSendStatus(pdev); } break; 8009ba0: e042 b.n 8009c28 else if (cfgidx != pdev->dev_config) 8009ba2: 4b24 ldr r3, [pc, #144] @ (8009c34 ) 8009ba4: 781b ldrb r3, [r3, #0] 8009ba6: 461a mov r2, r3 8009ba8: 687b ldr r3, [r7, #4] 8009baa: 685b ldr r3, [r3, #4] 8009bac: 429a cmp r2, r3 8009bae: d02a beq.n 8009c06 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8009bb0: 687b ldr r3, [r7, #4] 8009bb2: 685b ldr r3, [r3, #4] 8009bb4: b2db uxtb r3, r3 8009bb6: 4619 mov r1, r3 8009bb8: 6878 ldr r0, [r7, #4] 8009bba: f7fe ff80 bl 8008abe pdev->dev_config = cfgidx; 8009bbe: 4b1d ldr r3, [pc, #116] @ (8009c34 ) 8009bc0: 781b ldrb r3, [r3, #0] 8009bc2: 461a mov r2, r3 8009bc4: 687b ldr r3, [r7, #4] 8009bc6: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8009bc8: 4b1a ldr r3, [pc, #104] @ (8009c34 ) 8009bca: 781b ldrb r3, [r3, #0] 8009bcc: 4619 mov r1, r3 8009bce: 6878 ldr r0, [r7, #4] 8009bd0: f7fe ff59 bl 8008a86 8009bd4: 4603 mov r3, r0 8009bd6: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8009bd8: 7bfb ldrb r3, [r7, #15] 8009bda: 2b00 cmp r3, #0 8009bdc: d00f beq.n 8009bfe USBD_CtlError(pdev, req); 8009bde: 6839 ldr r1, [r7, #0] 8009be0: 6878 ldr r0, [r7, #4] 8009be2: f000 f918 bl 8009e16 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8009be6: 687b ldr r3, [r7, #4] 8009be8: 685b ldr r3, [r3, #4] 8009bea: b2db uxtb r3, r3 8009bec: 4619 mov r1, r3 8009bee: 6878 ldr r0, [r7, #4] 8009bf0: f7fe ff65 bl 8008abe pdev->dev_state = USBD_STATE_ADDRESSED; 8009bf4: 687b ldr r3, [r7, #4] 8009bf6: 2202 movs r2, #2 8009bf8: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8009bfc: e014 b.n 8009c28 (void)USBD_CtlSendStatus(pdev); 8009bfe: 6878 ldr r0, [r7, #4] 8009c00: f000 f9c6 bl 8009f90 break; 8009c04: e010 b.n 8009c28 (void)USBD_CtlSendStatus(pdev); 8009c06: 6878 ldr r0, [r7, #4] 8009c08: f000 f9c2 bl 8009f90 break; 8009c0c: e00c b.n 8009c28 default: USBD_CtlError(pdev, req); 8009c0e: 6839 ldr r1, [r7, #0] 8009c10: 6878 ldr r0, [r7, #4] 8009c12: f000 f900 bl 8009e16 (void)USBD_ClrClassConfig(pdev, cfgidx); 8009c16: 4b07 ldr r3, [pc, #28] @ (8009c34 ) 8009c18: 781b ldrb r3, [r3, #0] 8009c1a: 4619 mov r1, r3 8009c1c: 6878 ldr r0, [r7, #4] 8009c1e: f7fe ff4e bl 8008abe ret = USBD_FAIL; 8009c22: 2303 movs r3, #3 8009c24: 73fb strb r3, [r7, #15] break; 8009c26: bf00 nop } return ret; 8009c28: 7bfb ldrb r3, [r7, #15] } 8009c2a: 4618 mov r0, r3 8009c2c: 3710 adds r7, #16 8009c2e: 46bd mov sp, r7 8009c30: bd80 pop {r7, pc} 8009c32: bf00 nop 8009c34: 20000720 .word 0x20000720 08009c38 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009c38: b580 push {r7, lr} 8009c3a: b082 sub sp, #8 8009c3c: af00 add r7, sp, #0 8009c3e: 6078 str r0, [r7, #4] 8009c40: 6039 str r1, [r7, #0] if (req->wLength != 1U) 8009c42: 683b ldr r3, [r7, #0] 8009c44: 88db ldrh r3, [r3, #6] 8009c46: 2b01 cmp r3, #1 8009c48: d004 beq.n 8009c54 { USBD_CtlError(pdev, req); 8009c4a: 6839 ldr r1, [r7, #0] 8009c4c: 6878 ldr r0, [r7, #4] 8009c4e: f000 f8e2 bl 8009e16 default: USBD_CtlError(pdev, req); break; } } } 8009c52: e023 b.n 8009c9c switch (pdev->dev_state) 8009c54: 687b ldr r3, [r7, #4] 8009c56: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009c5a: b2db uxtb r3, r3 8009c5c: 2b02 cmp r3, #2 8009c5e: dc02 bgt.n 8009c66 8009c60: 2b00 cmp r3, #0 8009c62: dc03 bgt.n 8009c6c 8009c64: e015 b.n 8009c92 8009c66: 2b03 cmp r3, #3 8009c68: d00b beq.n 8009c82 8009c6a: e012 b.n 8009c92 pdev->dev_default_config = 0U; 8009c6c: 687b ldr r3, [r7, #4] 8009c6e: 2200 movs r2, #0 8009c70: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 8009c72: 687b ldr r3, [r7, #4] 8009c74: 3308 adds r3, #8 8009c76: 2201 movs r2, #1 8009c78: 4619 mov r1, r3 8009c7a: 6878 ldr r0, [r7, #4] 8009c7c: f000 f948 bl 8009f10 break; 8009c80: e00c b.n 8009c9c (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 8009c82: 687b ldr r3, [r7, #4] 8009c84: 3304 adds r3, #4 8009c86: 2201 movs r2, #1 8009c88: 4619 mov r1, r3 8009c8a: 6878 ldr r0, [r7, #4] 8009c8c: f000 f940 bl 8009f10 break; 8009c90: e004 b.n 8009c9c USBD_CtlError(pdev, req); 8009c92: 6839 ldr r1, [r7, #0] 8009c94: 6878 ldr r0, [r7, #4] 8009c96: f000 f8be bl 8009e16 break; 8009c9a: bf00 nop } 8009c9c: bf00 nop 8009c9e: 3708 adds r7, #8 8009ca0: 46bd mov sp, r7 8009ca2: bd80 pop {r7, pc} 08009ca4 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009ca4: b580 push {r7, lr} 8009ca6: b082 sub sp, #8 8009ca8: af00 add r7, sp, #0 8009caa: 6078 str r0, [r7, #4] 8009cac: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8009cae: 687b ldr r3, [r7, #4] 8009cb0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009cb4: b2db uxtb r3, r3 8009cb6: 3b01 subs r3, #1 8009cb8: 2b02 cmp r3, #2 8009cba: d81e bhi.n 8009cfa { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 8009cbc: 683b ldr r3, [r7, #0] 8009cbe: 88db ldrh r3, [r3, #6] 8009cc0: 2b02 cmp r3, #2 8009cc2: d004 beq.n 8009cce { USBD_CtlError(pdev, req); 8009cc4: 6839 ldr r1, [r7, #0] 8009cc6: 6878 ldr r0, [r7, #4] 8009cc8: f000 f8a5 bl 8009e16 break; 8009ccc: e01a b.n 8009d04 } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 8009cce: 687b ldr r3, [r7, #4] 8009cd0: 2201 movs r2, #1 8009cd2: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif /* USBD_SELF_POWERED */ if (pdev->dev_remote_wakeup != 0U) 8009cd4: 687b ldr r3, [r7, #4] 8009cd6: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 8009cda: 2b00 cmp r3, #0 8009cdc: d005 beq.n 8009cea { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 8009cde: 687b ldr r3, [r7, #4] 8009ce0: 68db ldr r3, [r3, #12] 8009ce2: f043 0202 orr.w r2, r3, #2 8009ce6: 687b ldr r3, [r7, #4] 8009ce8: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 8009cea: 687b ldr r3, [r7, #4] 8009cec: 330c adds r3, #12 8009cee: 2202 movs r2, #2 8009cf0: 4619 mov r1, r3 8009cf2: 6878 ldr r0, [r7, #4] 8009cf4: f000 f90c bl 8009f10 break; 8009cf8: e004 b.n 8009d04 default: USBD_CtlError(pdev, req); 8009cfa: 6839 ldr r1, [r7, #0] 8009cfc: 6878 ldr r0, [r7, #4] 8009cfe: f000 f88a bl 8009e16 break; 8009d02: bf00 nop } } 8009d04: bf00 nop 8009d06: 3708 adds r7, #8 8009d08: 46bd mov sp, r7 8009d0a: bd80 pop {r7, pc} 08009d0c : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009d0c: b580 push {r7, lr} 8009d0e: b082 sub sp, #8 8009d10: af00 add r7, sp, #0 8009d12: 6078 str r0, [r7, #4] 8009d14: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8009d16: 683b ldr r3, [r7, #0] 8009d18: 885b ldrh r3, [r3, #2] 8009d1a: 2b01 cmp r3, #1 8009d1c: d107 bne.n 8009d2e { pdev->dev_remote_wakeup = 1U; 8009d1e: 687b ldr r3, [r7, #4] 8009d20: 2201 movs r2, #1 8009d22: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8009d26: 6878 ldr r0, [r7, #4] 8009d28: f000 f932 bl 8009f90 } else { USBD_CtlError(pdev, req); } } 8009d2c: e013 b.n 8009d56 else if (req->wValue == USB_FEATURE_TEST_MODE) 8009d2e: 683b ldr r3, [r7, #0] 8009d30: 885b ldrh r3, [r3, #2] 8009d32: 2b02 cmp r3, #2 8009d34: d10b bne.n 8009d4e pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); 8009d36: 683b ldr r3, [r7, #0] 8009d38: 889b ldrh r3, [r3, #4] 8009d3a: 0a1b lsrs r3, r3, #8 8009d3c: b29b uxth r3, r3 8009d3e: b2da uxtb r2, r3 8009d40: 687b ldr r3, [r7, #4] 8009d42: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 (void)USBD_CtlSendStatus(pdev); 8009d46: 6878 ldr r0, [r7, #4] 8009d48: f000 f922 bl 8009f90 } 8009d4c: e003 b.n 8009d56 USBD_CtlError(pdev, req); 8009d4e: 6839 ldr r1, [r7, #0] 8009d50: 6878 ldr r0, [r7, #4] 8009d52: f000 f860 bl 8009e16 } 8009d56: bf00 nop 8009d58: 3708 adds r7, #8 8009d5a: 46bd mov sp, r7 8009d5c: bd80 pop {r7, pc} 08009d5e : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009d5e: b580 push {r7, lr} 8009d60: b082 sub sp, #8 8009d62: af00 add r7, sp, #0 8009d64: 6078 str r0, [r7, #4] 8009d66: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8009d68: 687b ldr r3, [r7, #4] 8009d6a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009d6e: b2db uxtb r3, r3 8009d70: 3b01 subs r3, #1 8009d72: 2b02 cmp r3, #2 8009d74: d80b bhi.n 8009d8e { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8009d76: 683b ldr r3, [r7, #0] 8009d78: 885b ldrh r3, [r3, #2] 8009d7a: 2b01 cmp r3, #1 8009d7c: d10c bne.n 8009d98 { pdev->dev_remote_wakeup = 0U; 8009d7e: 687b ldr r3, [r7, #4] 8009d80: 2200 movs r2, #0 8009d82: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8009d86: 6878 ldr r0, [r7, #4] 8009d88: f000 f902 bl 8009f90 } break; 8009d8c: e004 b.n 8009d98 default: USBD_CtlError(pdev, req); 8009d8e: 6839 ldr r1, [r7, #0] 8009d90: 6878 ldr r0, [r7, #4] 8009d92: f000 f840 bl 8009e16 break; 8009d96: e000 b.n 8009d9a break; 8009d98: bf00 nop } } 8009d9a: bf00 nop 8009d9c: 3708 adds r7, #8 8009d9e: 46bd mov sp, r7 8009da0: bd80 pop {r7, pc} 08009da2 : * @param req: usb request * @param pdata: setup data pointer * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 8009da2: b580 push {r7, lr} 8009da4: b084 sub sp, #16 8009da6: af00 add r7, sp, #0 8009da8: 6078 str r0, [r7, #4] 8009daa: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 8009dac: 683b ldr r3, [r7, #0] 8009dae: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 8009db0: 68fb ldr r3, [r7, #12] 8009db2: 781a ldrb r2, [r3, #0] 8009db4: 687b ldr r3, [r7, #4] 8009db6: 701a strb r2, [r3, #0] pbuff++; 8009db8: 68fb ldr r3, [r7, #12] 8009dba: 3301 adds r3, #1 8009dbc: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 8009dbe: 68fb ldr r3, [r7, #12] 8009dc0: 781a ldrb r2, [r3, #0] 8009dc2: 687b ldr r3, [r7, #4] 8009dc4: 705a strb r2, [r3, #1] pbuff++; 8009dc6: 68fb ldr r3, [r7, #12] 8009dc8: 3301 adds r3, #1 8009dca: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 8009dcc: 68f8 ldr r0, [r7, #12] 8009dce: f7ff fa13 bl 80091f8 8009dd2: 4603 mov r3, r0 8009dd4: 461a mov r2, r3 8009dd6: 687b ldr r3, [r7, #4] 8009dd8: 805a strh r2, [r3, #2] pbuff++; 8009dda: 68fb ldr r3, [r7, #12] 8009ddc: 3301 adds r3, #1 8009dde: 60fb str r3, [r7, #12] pbuff++; 8009de0: 68fb ldr r3, [r7, #12] 8009de2: 3301 adds r3, #1 8009de4: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 8009de6: 68f8 ldr r0, [r7, #12] 8009de8: f7ff fa06 bl 80091f8 8009dec: 4603 mov r3, r0 8009dee: 461a mov r2, r3 8009df0: 687b ldr r3, [r7, #4] 8009df2: 809a strh r2, [r3, #4] pbuff++; 8009df4: 68fb ldr r3, [r7, #12] 8009df6: 3301 adds r3, #1 8009df8: 60fb str r3, [r7, #12] pbuff++; 8009dfa: 68fb ldr r3, [r7, #12] 8009dfc: 3301 adds r3, #1 8009dfe: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 8009e00: 68f8 ldr r0, [r7, #12] 8009e02: f7ff f9f9 bl 80091f8 8009e06: 4603 mov r3, r0 8009e08: 461a mov r2, r3 8009e0a: 687b ldr r3, [r7, #4] 8009e0c: 80da strh r2, [r3, #6] } 8009e0e: bf00 nop 8009e10: 3710 adds r7, #16 8009e12: 46bd mov sp, r7 8009e14: bd80 pop {r7, pc} 08009e16 : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009e16: b580 push {r7, lr} 8009e18: b082 sub sp, #8 8009e1a: af00 add r7, sp, #0 8009e1c: 6078 str r0, [r7, #4] 8009e1e: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 8009e20: 2180 movs r1, #128 @ 0x80 8009e22: 6878 ldr r0, [r7, #4] 8009e24: f000 fc2a bl 800a67c (void)USBD_LL_StallEP(pdev, 0U); 8009e28: 2100 movs r1, #0 8009e2a: 6878 ldr r0, [r7, #4] 8009e2c: f000 fc26 bl 800a67c } 8009e30: bf00 nop 8009e32: 3708 adds r7, #8 8009e34: 46bd mov sp, r7 8009e36: bd80 pop {r7, pc} 08009e38 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 8009e38: b580 push {r7, lr} 8009e3a: b086 sub sp, #24 8009e3c: af00 add r7, sp, #0 8009e3e: 60f8 str r0, [r7, #12] 8009e40: 60b9 str r1, [r7, #8] 8009e42: 607a str r2, [r7, #4] uint8_t idx = 0U; 8009e44: 2300 movs r3, #0 8009e46: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 8009e48: 68fb ldr r3, [r7, #12] 8009e4a: 2b00 cmp r3, #0 8009e4c: d042 beq.n 8009ed4 { return; } pdesc = desc; 8009e4e: 68fb ldr r3, [r7, #12] 8009e50: 613b str r3, [r7, #16] *len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U); 8009e52: 6938 ldr r0, [r7, #16] 8009e54: f000 f842 bl 8009edc 8009e58: 4603 mov r3, r0 8009e5a: 3301 adds r3, #1 8009e5c: 005b lsls r3, r3, #1 8009e5e: f5b3 7f00 cmp.w r3, #512 @ 0x200 8009e62: d808 bhi.n 8009e76 8009e64: 6938 ldr r0, [r7, #16] 8009e66: f000 f839 bl 8009edc 8009e6a: 4603 mov r3, r0 8009e6c: 3301 adds r3, #1 8009e6e: b29b uxth r3, r3 8009e70: 005b lsls r3, r3, #1 8009e72: b29a uxth r2, r3 8009e74: e001 b.n 8009e7a 8009e76: f44f 7200 mov.w r2, #512 @ 0x200 8009e7a: 687b ldr r3, [r7, #4] 8009e7c: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 8009e7e: 7dfb ldrb r3, [r7, #23] 8009e80: 68ba ldr r2, [r7, #8] 8009e82: 4413 add r3, r2 8009e84: 687a ldr r2, [r7, #4] 8009e86: 7812 ldrb r2, [r2, #0] 8009e88: 701a strb r2, [r3, #0] idx++; 8009e8a: 7dfb ldrb r3, [r7, #23] 8009e8c: 3301 adds r3, #1 8009e8e: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 8009e90: 7dfb ldrb r3, [r7, #23] 8009e92: 68ba ldr r2, [r7, #8] 8009e94: 4413 add r3, r2 8009e96: 2203 movs r2, #3 8009e98: 701a strb r2, [r3, #0] idx++; 8009e9a: 7dfb ldrb r3, [r7, #23] 8009e9c: 3301 adds r3, #1 8009e9e: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8009ea0: e013 b.n 8009eca { unicode[idx] = *pdesc; 8009ea2: 7dfb ldrb r3, [r7, #23] 8009ea4: 68ba ldr r2, [r7, #8] 8009ea6: 4413 add r3, r2 8009ea8: 693a ldr r2, [r7, #16] 8009eaa: 7812 ldrb r2, [r2, #0] 8009eac: 701a strb r2, [r3, #0] pdesc++; 8009eae: 693b ldr r3, [r7, #16] 8009eb0: 3301 adds r3, #1 8009eb2: 613b str r3, [r7, #16] idx++; 8009eb4: 7dfb ldrb r3, [r7, #23] 8009eb6: 3301 adds r3, #1 8009eb8: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 8009eba: 7dfb ldrb r3, [r7, #23] 8009ebc: 68ba ldr r2, [r7, #8] 8009ebe: 4413 add r3, r2 8009ec0: 2200 movs r2, #0 8009ec2: 701a strb r2, [r3, #0] idx++; 8009ec4: 7dfb ldrb r3, [r7, #23] 8009ec6: 3301 adds r3, #1 8009ec8: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8009eca: 693b ldr r3, [r7, #16] 8009ecc: 781b ldrb r3, [r3, #0] 8009ece: 2b00 cmp r3, #0 8009ed0: d1e7 bne.n 8009ea2 8009ed2: e000 b.n 8009ed6 return; 8009ed4: bf00 nop } } 8009ed6: 3718 adds r7, #24 8009ed8: 46bd mov sp, r7 8009eda: bd80 pop {r7, pc} 08009edc : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 8009edc: b480 push {r7} 8009ede: b085 sub sp, #20 8009ee0: af00 add r7, sp, #0 8009ee2: 6078 str r0, [r7, #4] uint8_t len = 0U; 8009ee4: 2300 movs r3, #0 8009ee6: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 8009ee8: 687b ldr r3, [r7, #4] 8009eea: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 8009eec: e005 b.n 8009efa { len++; 8009eee: 7bfb ldrb r3, [r7, #15] 8009ef0: 3301 adds r3, #1 8009ef2: 73fb strb r3, [r7, #15] pbuff++; 8009ef4: 68bb ldr r3, [r7, #8] 8009ef6: 3301 adds r3, #1 8009ef8: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 8009efa: 68bb ldr r3, [r7, #8] 8009efc: 781b ldrb r3, [r3, #0] 8009efe: 2b00 cmp r3, #0 8009f00: d1f5 bne.n 8009eee } return len; 8009f02: 7bfb ldrb r3, [r7, #15] } 8009f04: 4618 mov r0, r3 8009f06: 3714 adds r7, #20 8009f08: 46bd mov sp, r7 8009f0a: f85d 7b04 ldr.w r7, [sp], #4 8009f0e: 4770 bx lr 08009f10 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8009f10: b580 push {r7, lr} 8009f12: b084 sub sp, #16 8009f14: af00 add r7, sp, #0 8009f16: 60f8 str r0, [r7, #12] 8009f18: 60b9 str r1, [r7, #8] 8009f1a: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 8009f1c: 68fb ldr r3, [r7, #12] 8009f1e: 2202 movs r2, #2 8009f20: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_in[0].total_length = len; 8009f24: 68fb ldr r3, [r7, #12] 8009f26: 687a ldr r2, [r7, #4] 8009f28: 615a str r2, [r3, #20] pdev->ep_in[0].pbuffer = pbuf; 8009f2a: 68fb ldr r3, [r7, #12] 8009f2c: 68ba ldr r2, [r7, #8] 8009f2e: 625a str r2, [r3, #36] @ 0x24 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 8009f30: 68fb ldr r3, [r7, #12] 8009f32: 687a ldr r2, [r7, #4] 8009f34: 619a str r2, [r3, #24] #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8009f36: 687b ldr r3, [r7, #4] 8009f38: 68ba ldr r2, [r7, #8] 8009f3a: 2100 movs r1, #0 8009f3c: 68f8 ldr r0, [r7, #12] 8009f3e: f000 fc26 bl 800a78e return USBD_OK; 8009f42: 2300 movs r3, #0 } 8009f44: 4618 mov r0, r3 8009f46: 3710 adds r7, #16 8009f48: 46bd mov sp, r7 8009f4a: bd80 pop {r7, pc} 08009f4c : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8009f4c: b580 push {r7, lr} 8009f4e: b084 sub sp, #16 8009f50: af00 add r7, sp, #0 8009f52: 60f8 str r0, [r7, #12] 8009f54: 60b9 str r1, [r7, #8] 8009f56: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8009f58: 687b ldr r3, [r7, #4] 8009f5a: 68ba ldr r2, [r7, #8] 8009f5c: 2100 movs r1, #0 8009f5e: 68f8 ldr r0, [r7, #12] 8009f60: f000 fc15 bl 800a78e return USBD_OK; 8009f64: 2300 movs r3, #0 } 8009f66: 4618 mov r0, r3 8009f68: 3710 adds r7, #16 8009f6a: 46bd mov sp, r7 8009f6c: bd80 pop {r7, pc} 08009f6e : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8009f6e: b580 push {r7, lr} 8009f70: b084 sub sp, #16 8009f72: af00 add r7, sp, #0 8009f74: 60f8 str r0, [r7, #12] 8009f76: 60b9 str r1, [r7, #8] 8009f78: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 8009f7a: 687b ldr r3, [r7, #4] 8009f7c: 68ba ldr r2, [r7, #8] 8009f7e: 2100 movs r1, #0 8009f80: 68f8 ldr r0, [r7, #12] 8009f82: f000 fc25 bl 800a7d0 return USBD_OK; 8009f86: 2300 movs r3, #0 } 8009f88: 4618 mov r0, r3 8009f8a: 3710 adds r7, #16 8009f8c: 46bd mov sp, r7 8009f8e: bd80 pop {r7, pc} 08009f90 : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 8009f90: b580 push {r7, lr} 8009f92: b082 sub sp, #8 8009f94: af00 add r7, sp, #0 8009f96: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 8009f98: 687b ldr r3, [r7, #4] 8009f9a: 2204 movs r2, #4 8009f9c: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 8009fa0: 2300 movs r3, #0 8009fa2: 2200 movs r2, #0 8009fa4: 2100 movs r1, #0 8009fa6: 6878 ldr r0, [r7, #4] 8009fa8: f000 fbf1 bl 800a78e return USBD_OK; 8009fac: 2300 movs r3, #0 } 8009fae: 4618 mov r0, r3 8009fb0: 3708 adds r7, #8 8009fb2: 46bd mov sp, r7 8009fb4: bd80 pop {r7, pc} 08009fb6 : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 8009fb6: b580 push {r7, lr} 8009fb8: b082 sub sp, #8 8009fba: af00 add r7, sp, #0 8009fbc: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 8009fbe: 687b ldr r3, [r7, #4] 8009fc0: 2205 movs r2, #5 8009fc2: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8009fc6: 2300 movs r3, #0 8009fc8: 2200 movs r2, #0 8009fca: 2100 movs r1, #0 8009fcc: 6878 ldr r0, [r7, #4] 8009fce: f000 fbff bl 800a7d0 return USBD_OK; 8009fd2: 2300 movs r3, #0 } 8009fd4: 4618 mov r0, r3 8009fd6: 3708 adds r7, #8 8009fd8: 46bd mov sp, r7 8009fda: bd80 pop {r7, pc} 08009fdc : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 8009fdc: b580 push {r7, lr} 8009fde: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) 8009fe0: 2200 movs r2, #0 8009fe2: 490e ldr r1, [pc, #56] @ (800a01c ) 8009fe4: 480e ldr r0, [pc, #56] @ (800a020 ) 8009fe6: f7fe fcd1 bl 800898c 8009fea: 4603 mov r3, r0 8009fec: 2b00 cmp r3, #0 8009fee: d001 beq.n 8009ff4 { Error_Handler(); 8009ff0: f7f6 fee2 bl 8000db8 } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) 8009ff4: 490b ldr r1, [pc, #44] @ (800a024 ) 8009ff6: 480a ldr r0, [pc, #40] @ (800a020 ) 8009ff8: f7fe fcf8 bl 80089ec 8009ffc: 4603 mov r3, r0 8009ffe: 2b00 cmp r3, #0 800a000: d001 beq.n 800a006 { Error_Handler(); 800a002: f7f6 fed9 bl 8000db8 } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) 800a006: 4806 ldr r0, [pc, #24] @ (800a020 ) 800a008: f7fe fd26 bl 8008a58 800a00c: 4603 mov r3, r0 800a00e: 2b00 cmp r3, #0 800a010: d001 beq.n 800a016 { Error_Handler(); 800a012: f7f6 fed1 bl 8000db8 } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 800a016: bf00 nop 800a018: bd80 pop {r7, pc} 800a01a: bf00 nop 800a01c: 20000140 .word 0x20000140 800a020: 20000724 .word 0x20000724 800a024: 2000009c .word 0x2000009c 0800a028 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a028: b480 push {r7} 800a02a: b083 sub sp, #12 800a02c: af00 add r7, sp, #0 800a02e: 4603 mov r3, r0 800a030: 6039 str r1, [r7, #0] 800a032: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_DeviceDesc); 800a034: 683b ldr r3, [r7, #0] 800a036: 2212 movs r2, #18 800a038: 801a strh r2, [r3, #0] return USBD_FS_DeviceDesc; 800a03a: 4b03 ldr r3, [pc, #12] @ (800a048 ) } 800a03c: 4618 mov r0, r3 800a03e: 370c adds r7, #12 800a040: 46bd mov sp, r7 800a042: f85d 7b04 ldr.w r7, [sp], #4 800a046: 4770 bx lr 800a048: 20000160 .word 0x20000160 0800a04c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a04c: b480 push {r7} 800a04e: b083 sub sp, #12 800a050: af00 add r7, sp, #0 800a052: 4603 mov r3, r0 800a054: 6039 str r1, [r7, #0] 800a056: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 800a058: 683b ldr r3, [r7, #0] 800a05a: 2204 movs r2, #4 800a05c: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 800a05e: 4b03 ldr r3, [pc, #12] @ (800a06c ) } 800a060: 4618 mov r0, r3 800a062: 370c adds r7, #12 800a064: 46bd mov sp, r7 800a066: f85d 7b04 ldr.w r7, [sp], #4 800a06a: 4770 bx lr 800a06c: 20000180 .word 0x20000180 0800a070 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a070: b580 push {r7, lr} 800a072: b082 sub sp, #8 800a074: af00 add r7, sp, #0 800a076: 4603 mov r3, r0 800a078: 6039 str r1, [r7, #0] 800a07a: 71fb strb r3, [r7, #7] if(speed == 0) 800a07c: 79fb ldrb r3, [r7, #7] 800a07e: 2b00 cmp r3, #0 800a080: d105 bne.n 800a08e { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800a082: 683a ldr r2, [r7, #0] 800a084: 4907 ldr r1, [pc, #28] @ (800a0a4 ) 800a086: 4808 ldr r0, [pc, #32] @ (800a0a8 ) 800a088: f7ff fed6 bl 8009e38 800a08c: e004 b.n 800a098 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800a08e: 683a ldr r2, [r7, #0] 800a090: 4904 ldr r1, [pc, #16] @ (800a0a4 ) 800a092: 4805 ldr r0, [pc, #20] @ (800a0a8 ) 800a094: f7ff fed0 bl 8009e38 } return USBD_StrDesc; 800a098: 4b02 ldr r3, [pc, #8] @ (800a0a4 ) } 800a09a: 4618 mov r0, r3 800a09c: 3708 adds r7, #8 800a09e: 46bd mov sp, r7 800a0a0: bd80 pop {r7, pc} 800a0a2: bf00 nop 800a0a4: 20000a00 .word 0x20000a00 800a0a8: 0800a9c4 .word 0x0800a9c4 0800a0ac : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a0ac: b580 push {r7, lr} 800a0ae: b082 sub sp, #8 800a0b0: af00 add r7, sp, #0 800a0b2: 4603 mov r3, r0 800a0b4: 6039 str r1, [r7, #0] 800a0b6: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 800a0b8: 683a ldr r2, [r7, #0] 800a0ba: 4904 ldr r1, [pc, #16] @ (800a0cc ) 800a0bc: 4804 ldr r0, [pc, #16] @ (800a0d0 ) 800a0be: f7ff febb bl 8009e38 return USBD_StrDesc; 800a0c2: 4b02 ldr r3, [pc, #8] @ (800a0cc ) } 800a0c4: 4618 mov r0, r3 800a0c6: 3708 adds r7, #8 800a0c8: 46bd mov sp, r7 800a0ca: bd80 pop {r7, pc} 800a0cc: 20000a00 .word 0x20000a00 800a0d0: 0800a9d8 .word 0x0800a9d8 0800a0d4 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a0d4: b580 push {r7, lr} 800a0d6: b082 sub sp, #8 800a0d8: af00 add r7, sp, #0 800a0da: 4603 mov r3, r0 800a0dc: 6039 str r1, [r7, #0] 800a0de: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 800a0e0: 683b ldr r3, [r7, #0] 800a0e2: 221a movs r2, #26 800a0e4: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 800a0e6: f000 f855 bl 800a194 /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ /* USER CODE END USBD_FS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 800a0ea: 4b02 ldr r3, [pc, #8] @ (800a0f4 ) } 800a0ec: 4618 mov r0, r3 800a0ee: 3708 adds r7, #8 800a0f0: 46bd mov sp, r7 800a0f2: bd80 pop {r7, pc} 800a0f4: 20000184 .word 0x20000184 0800a0f8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a0f8: b580 push {r7, lr} 800a0fa: b082 sub sp, #8 800a0fc: af00 add r7, sp, #0 800a0fe: 4603 mov r3, r0 800a100: 6039 str r1, [r7, #0] 800a102: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 800a104: 79fb ldrb r3, [r7, #7] 800a106: 2b00 cmp r3, #0 800a108: d105 bne.n 800a116 { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800a10a: 683a ldr r2, [r7, #0] 800a10c: 4907 ldr r1, [pc, #28] @ (800a12c ) 800a10e: 4808 ldr r0, [pc, #32] @ (800a130 ) 800a110: f7ff fe92 bl 8009e38 800a114: e004 b.n 800a120 } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800a116: 683a ldr r2, [r7, #0] 800a118: 4904 ldr r1, [pc, #16] @ (800a12c ) 800a11a: 4805 ldr r0, [pc, #20] @ (800a130 ) 800a11c: f7ff fe8c bl 8009e38 } return USBD_StrDesc; 800a120: 4b02 ldr r3, [pc, #8] @ (800a12c ) } 800a122: 4618 mov r0, r3 800a124: 3708 adds r7, #8 800a126: 46bd mov sp, r7 800a128: bd80 pop {r7, pc} 800a12a: bf00 nop 800a12c: 20000a00 .word 0x20000a00 800a130: 0800a9e4 .word 0x0800a9e4 0800a134 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a134: b580 push {r7, lr} 800a136: b082 sub sp, #8 800a138: af00 add r7, sp, #0 800a13a: 4603 mov r3, r0 800a13c: 6039 str r1, [r7, #0] 800a13e: 71fb strb r3, [r7, #7] if(speed == 0) 800a140: 79fb ldrb r3, [r7, #7] 800a142: 2b00 cmp r3, #0 800a144: d105 bne.n 800a152 { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800a146: 683a ldr r2, [r7, #0] 800a148: 4907 ldr r1, [pc, #28] @ (800a168 ) 800a14a: 4808 ldr r0, [pc, #32] @ (800a16c ) 800a14c: f7ff fe74 bl 8009e38 800a150: e004 b.n 800a15c } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800a152: 683a ldr r2, [r7, #0] 800a154: 4904 ldr r1, [pc, #16] @ (800a168 ) 800a156: 4805 ldr r0, [pc, #20] @ (800a16c ) 800a158: f7ff fe6e bl 8009e38 } return USBD_StrDesc; 800a15c: 4b02 ldr r3, [pc, #8] @ (800a168 ) } 800a15e: 4618 mov r0, r3 800a160: 3708 adds r7, #8 800a162: 46bd mov sp, r7 800a164: bd80 pop {r7, pc} 800a166: bf00 nop 800a168: 20000a00 .word 0x20000a00 800a16c: 0800a9f0 .word 0x0800a9f0 0800a170 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a170: b480 push {r7} 800a172: b083 sub sp, #12 800a174: af00 add r7, sp, #0 800a176: 4603 mov r3, r0 800a178: 6039 str r1, [r7, #0] 800a17a: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_BOSDesc); 800a17c: 683b ldr r3, [r7, #0] 800a17e: 220c movs r2, #12 800a180: 801a strh r2, [r3, #0] return (uint8_t*)USBD_FS_BOSDesc; 800a182: 4b03 ldr r3, [pc, #12] @ (800a190 ) } 800a184: 4618 mov r0, r3 800a186: 370c adds r7, #12 800a188: 46bd mov sp, r7 800a18a: f85d 7b04 ldr.w r7, [sp], #4 800a18e: 4770 bx lr 800a190: 20000174 .word 0x20000174 0800a194 : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 800a194: b580 push {r7, lr} 800a196: b084 sub sp, #16 800a198: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 800a19a: 4b0f ldr r3, [pc, #60] @ (800a1d8 ) 800a19c: 681b ldr r3, [r3, #0] 800a19e: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 800a1a0: 4b0e ldr r3, [pc, #56] @ (800a1dc ) 800a1a2: 681b ldr r3, [r3, #0] 800a1a4: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 800a1a6: 4b0e ldr r3, [pc, #56] @ (800a1e0 ) 800a1a8: 681b ldr r3, [r3, #0] 800a1aa: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 800a1ac: 68fa ldr r2, [r7, #12] 800a1ae: 687b ldr r3, [r7, #4] 800a1b0: 4413 add r3, r2 800a1b2: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 800a1b4: 68fb ldr r3, [r7, #12] 800a1b6: 2b00 cmp r3, #0 800a1b8: d009 beq.n 800a1ce { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 800a1ba: 2208 movs r2, #8 800a1bc: 4909 ldr r1, [pc, #36] @ (800a1e4 ) 800a1be: 68f8 ldr r0, [r7, #12] 800a1c0: f000 f814 bl 800a1ec IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 800a1c4: 2204 movs r2, #4 800a1c6: 4908 ldr r1, [pc, #32] @ (800a1e8 ) 800a1c8: 68b8 ldr r0, [r7, #8] 800a1ca: f000 f80f bl 800a1ec } } 800a1ce: bf00 nop 800a1d0: 3710 adds r7, #16 800a1d2: 46bd mov sp, r7 800a1d4: bd80 pop {r7, pc} 800a1d6: bf00 nop 800a1d8: 1fff7a10 .word 0x1fff7a10 800a1dc: 1fff7a14 .word 0x1fff7a14 800a1e0: 1fff7a18 .word 0x1fff7a18 800a1e4: 20000186 .word 0x20000186 800a1e8: 20000196 .word 0x20000196 0800a1ec : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 800a1ec: b480 push {r7} 800a1ee: b087 sub sp, #28 800a1f0: af00 add r7, sp, #0 800a1f2: 60f8 str r0, [r7, #12] 800a1f4: 60b9 str r1, [r7, #8] 800a1f6: 4613 mov r3, r2 800a1f8: 71fb strb r3, [r7, #7] uint8_t idx = 0; 800a1fa: 2300 movs r3, #0 800a1fc: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 800a1fe: 2300 movs r3, #0 800a200: 75fb strb r3, [r7, #23] 800a202: e027 b.n 800a254 { if (((value >> 28)) < 0xA) 800a204: 68fb ldr r3, [r7, #12] 800a206: 0f1b lsrs r3, r3, #28 800a208: 2b09 cmp r3, #9 800a20a: d80b bhi.n 800a224 { pbuf[2 * idx] = (value >> 28) + '0'; 800a20c: 68fb ldr r3, [r7, #12] 800a20e: 0f1b lsrs r3, r3, #28 800a210: b2da uxtb r2, r3 800a212: 7dfb ldrb r3, [r7, #23] 800a214: 005b lsls r3, r3, #1 800a216: 4619 mov r1, r3 800a218: 68bb ldr r3, [r7, #8] 800a21a: 440b add r3, r1 800a21c: 3230 adds r2, #48 @ 0x30 800a21e: b2d2 uxtb r2, r2 800a220: 701a strb r2, [r3, #0] 800a222: e00a b.n 800a23a } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 800a224: 68fb ldr r3, [r7, #12] 800a226: 0f1b lsrs r3, r3, #28 800a228: b2da uxtb r2, r3 800a22a: 7dfb ldrb r3, [r7, #23] 800a22c: 005b lsls r3, r3, #1 800a22e: 4619 mov r1, r3 800a230: 68bb ldr r3, [r7, #8] 800a232: 440b add r3, r1 800a234: 3237 adds r2, #55 @ 0x37 800a236: b2d2 uxtb r2, r2 800a238: 701a strb r2, [r3, #0] } value = value << 4; 800a23a: 68fb ldr r3, [r7, #12] 800a23c: 011b lsls r3, r3, #4 800a23e: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 800a240: 7dfb ldrb r3, [r7, #23] 800a242: 005b lsls r3, r3, #1 800a244: 3301 adds r3, #1 800a246: 68ba ldr r2, [r7, #8] 800a248: 4413 add r3, r2 800a24a: 2200 movs r2, #0 800a24c: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 800a24e: 7dfb ldrb r3, [r7, #23] 800a250: 3301 adds r3, #1 800a252: 75fb strb r3, [r7, #23] 800a254: 7dfa ldrb r2, [r7, #23] 800a256: 79fb ldrb r3, [r7, #7] 800a258: 429a cmp r2, r3 800a25a: d3d3 bcc.n 800a204 } } 800a25c: bf00 nop 800a25e: bf00 nop 800a260: 371c adds r7, #28 800a262: 46bd mov sp, r7 800a264: f85d 7b04 ldr.w r7, [sp], #4 800a268: 4770 bx lr ... 0800a26c : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 800a26c: b580 push {r7, lr} 800a26e: b0a0 sub sp, #128 @ 0x80 800a270: af00 add r7, sp, #0 800a272: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a274: f107 036c add.w r3, r7, #108 @ 0x6c 800a278: 2200 movs r2, #0 800a27a: 601a str r2, [r3, #0] 800a27c: 605a str r2, [r3, #4] 800a27e: 609a str r2, [r3, #8] 800a280: 60da str r2, [r3, #12] 800a282: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 800a284: f107 0310 add.w r3, r7, #16 800a288: 225c movs r2, #92 @ 0x5c 800a28a: 2100 movs r1, #0 800a28c: 4618 mov r0, r3 800a28e: f000 fb53 bl 800a938 if(pcdHandle->Instance==USB_OTG_FS) 800a292: 687b ldr r3, [r7, #4] 800a294: 681b ldr r3, [r3, #0] 800a296: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800a29a: d149 bne.n 800a330 /* USER CODE END USB_OTG_FS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; 800a29c: f44f 7380 mov.w r3, #256 @ 0x100 800a2a0: 613b str r3, [r7, #16] PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; 800a2a2: 2300 movs r3, #0 800a2a4: 667b str r3, [r7, #100] @ 0x64 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800a2a6: f107 0310 add.w r3, r7, #16 800a2aa: 4618 mov r0, r3 800a2ac: f7f9 ffaa bl 8004204 800a2b0: 4603 mov r3, r0 800a2b2: 2b00 cmp r3, #0 800a2b4: d001 beq.n 800a2ba { Error_Handler(); 800a2b6: f7f6 fd7f bl 8000db8 } __HAL_RCC_GPIOA_CLK_ENABLE(); 800a2ba: 2300 movs r3, #0 800a2bc: 60fb str r3, [r7, #12] 800a2be: 4b1e ldr r3, [pc, #120] @ (800a338 ) 800a2c0: 6b1b ldr r3, [r3, #48] @ 0x30 800a2c2: 4a1d ldr r2, [pc, #116] @ (800a338 ) 800a2c4: f043 0301 orr.w r3, r3, #1 800a2c8: 6313 str r3, [r2, #48] @ 0x30 800a2ca: 4b1b ldr r3, [pc, #108] @ (800a338 ) 800a2cc: 6b1b ldr r3, [r3, #48] @ 0x30 800a2ce: f003 0301 and.w r3, r3, #1 800a2d2: 60fb str r3, [r7, #12] 800a2d4: 68fb ldr r3, [r7, #12] /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 800a2d6: f44f 53c0 mov.w r3, #6144 @ 0x1800 800a2da: 66fb str r3, [r7, #108] @ 0x6c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800a2dc: 2302 movs r3, #2 800a2de: 673b str r3, [r7, #112] @ 0x70 GPIO_InitStruct.Pull = GPIO_NOPULL; 800a2e0: 2300 movs r3, #0 800a2e2: 677b str r3, [r7, #116] @ 0x74 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800a2e4: 2303 movs r3, #3 800a2e6: 67bb str r3, [r7, #120] @ 0x78 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 800a2e8: 230a movs r3, #10 800a2ea: 67fb str r3, [r7, #124] @ 0x7c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800a2ec: f107 036c add.w r3, r7, #108 @ 0x6c 800a2f0: 4619 mov r1, r3 800a2f2: 4812 ldr r0, [pc, #72] @ (800a33c ) 800a2f4: f7f8 f8dc bl 80024b0 /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 800a2f8: 4b0f ldr r3, [pc, #60] @ (800a338 ) 800a2fa: 6b5b ldr r3, [r3, #52] @ 0x34 800a2fc: 4a0e ldr r2, [pc, #56] @ (800a338 ) 800a2fe: f043 0380 orr.w r3, r3, #128 @ 0x80 800a302: 6353 str r3, [r2, #52] @ 0x34 800a304: 2300 movs r3, #0 800a306: 60bb str r3, [r7, #8] 800a308: 4b0b ldr r3, [pc, #44] @ (800a338 ) 800a30a: 6c5b ldr r3, [r3, #68] @ 0x44 800a30c: 4a0a ldr r2, [pc, #40] @ (800a338 ) 800a30e: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800a312: 6453 str r3, [r2, #68] @ 0x44 800a314: 4b08 ldr r3, [pc, #32] @ (800a338 ) 800a316: 6c5b ldr r3, [r3, #68] @ 0x44 800a318: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a31c: 60bb str r3, [r7, #8] 800a31e: 68bb ldr r3, [r7, #8] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); 800a320: 2200 movs r2, #0 800a322: 2100 movs r1, #0 800a324: 2043 movs r0, #67 @ 0x43 800a326: f7f7 fc8a bl 8001c3e HAL_NVIC_EnableIRQ(OTG_FS_IRQn); 800a32a: 2043 movs r0, #67 @ 0x43 800a32c: f7f7 fca3 bl 8001c76 /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 800a330: bf00 nop 800a332: 3780 adds r7, #128 @ 0x80 800a334: 46bd mov sp, r7 800a336: bd80 pop {r7, pc} 800a338: 40023800 .word 0x40023800 800a33c: 40020000 .word 0x40020000 0800a340 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a340: b580 push {r7, lr} 800a342: b082 sub sp, #8 800a344: af00 add r7, sp, #0 800a346: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 800a348: 687b ldr r3, [r7, #4] 800a34a: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0 800a34e: 687b ldr r3, [r7, #4] 800a350: f203 439c addw r3, r3, #1180 @ 0x49c 800a354: 4619 mov r1, r3 800a356: 4610 mov r0, r2 800a358: f7fe fbcb bl 8008af2 } 800a35c: bf00 nop 800a35e: 3708 adds r7, #8 800a360: 46bd mov sp, r7 800a362: bd80 pop {r7, pc} 0800a364 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a364: b580 push {r7, lr} 800a366: b082 sub sp, #8 800a368: af00 add r7, sp, #0 800a36a: 6078 str r0, [r7, #4] 800a36c: 460b mov r3, r1 800a36e: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 800a370: 687b ldr r3, [r7, #4] 800a372: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800a376: 78fa ldrb r2, [r7, #3] 800a378: 6879 ldr r1, [r7, #4] 800a37a: 4613 mov r3, r2 800a37c: 00db lsls r3, r3, #3 800a37e: 4413 add r3, r2 800a380: 009b lsls r3, r3, #2 800a382: 440b add r3, r1 800a384: f503 7318 add.w r3, r3, #608 @ 0x260 800a388: 681a ldr r2, [r3, #0] 800a38a: 78fb ldrb r3, [r7, #3] 800a38c: 4619 mov r1, r3 800a38e: f7fe fc05 bl 8008b9c } 800a392: bf00 nop 800a394: 3708 adds r7, #8 800a396: 46bd mov sp, r7 800a398: bd80 pop {r7, pc} 0800a39a : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a39a: b580 push {r7, lr} 800a39c: b082 sub sp, #8 800a39e: af00 add r7, sp, #0 800a3a0: 6078 str r0, [r7, #4] 800a3a2: 460b mov r3, r1 800a3a4: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 800a3a6: 687b ldr r3, [r7, #4] 800a3a8: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800a3ac: 78fa ldrb r2, [r7, #3] 800a3ae: 6879 ldr r1, [r7, #4] 800a3b0: 4613 mov r3, r2 800a3b2: 00db lsls r3, r3, #3 800a3b4: 4413 add r3, r2 800a3b6: 009b lsls r3, r3, #2 800a3b8: 440b add r3, r1 800a3ba: 3320 adds r3, #32 800a3bc: 681a ldr r2, [r3, #0] 800a3be: 78fb ldrb r3, [r7, #3] 800a3c0: 4619 mov r1, r3 800a3c2: f7fe fca7 bl 8008d14 } 800a3c6: bf00 nop 800a3c8: 3708 adds r7, #8 800a3ca: 46bd mov sp, r7 800a3cc: bd80 pop {r7, pc} 0800a3ce : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a3ce: b580 push {r7, lr} 800a3d0: b082 sub sp, #8 800a3d2: af00 add r7, sp, #0 800a3d4: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 800a3d6: 687b ldr r3, [r7, #4] 800a3d8: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a3dc: 4618 mov r0, r3 800a3de: f7fe fdeb bl 8008fb8 } 800a3e2: bf00 nop 800a3e4: 3708 adds r7, #8 800a3e6: 46bd mov sp, r7 800a3e8: bd80 pop {r7, pc} 0800a3ea : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a3ea: b580 push {r7, lr} 800a3ec: b084 sub sp, #16 800a3ee: af00 add r7, sp, #0 800a3f0: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 800a3f2: 2301 movs r3, #1 800a3f4: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed == PCD_SPEED_HIGH) 800a3f6: 687b ldr r3, [r7, #4] 800a3f8: 79db ldrb r3, [r3, #7] 800a3fa: 2b00 cmp r3, #0 800a3fc: d102 bne.n 800a404 { speed = USBD_SPEED_HIGH; 800a3fe: 2300 movs r3, #0 800a400: 73fb strb r3, [r7, #15] 800a402: e008 b.n 800a416 } else if ( hpcd->Init.speed == PCD_SPEED_FULL) 800a404: 687b ldr r3, [r7, #4] 800a406: 79db ldrb r3, [r3, #7] 800a408: 2b02 cmp r3, #2 800a40a: d102 bne.n 800a412 { speed = USBD_SPEED_FULL; 800a40c: 2301 movs r3, #1 800a40e: 73fb strb r3, [r7, #15] 800a410: e001 b.n 800a416 } else { Error_Handler(); 800a412: f7f6 fcd1 bl 8000db8 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 800a416: 687b ldr r3, [r7, #4] 800a418: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a41c: 7bfa ldrb r2, [r7, #15] 800a41e: 4611 mov r1, r2 800a420: 4618 mov r0, r3 800a422: f7fe fd85 bl 8008f30 /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 800a426: 687b ldr r3, [r7, #4] 800a428: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a42c: 4618 mov r0, r3 800a42e: f7fe fd2c bl 8008e8a } 800a432: bf00 nop 800a434: 3710 adds r7, #16 800a436: 46bd mov sp, r7 800a438: bd80 pop {r7, pc} ... 0800a43c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a43c: b580 push {r7, lr} 800a43e: b082 sub sp, #8 800a440: af00 add r7, sp, #0 800a442: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 800a444: 687b ldr r3, [r7, #4] 800a446: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a44a: 4618 mov r0, r3 800a44c: f7fe fd80 bl 8008f50 __HAL_PCD_GATE_PHYCLOCK(hpcd); 800a450: 687b ldr r3, [r7, #4] 800a452: 681b ldr r3, [r3, #0] 800a454: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a458: 681b ldr r3, [r3, #0] 800a45a: 687a ldr r2, [r7, #4] 800a45c: 6812 ldr r2, [r2, #0] 800a45e: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a462: f043 0301 orr.w r3, r3, #1 800a466: 6013 str r3, [r2, #0] /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 800a468: 687b ldr r3, [r7, #4] 800a46a: 7adb ldrb r3, [r3, #11] 800a46c: 2b00 cmp r3, #0 800a46e: d005 beq.n 800a47c { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a470: 4b04 ldr r3, [pc, #16] @ (800a484 ) 800a472: 691b ldr r3, [r3, #16] 800a474: 4a03 ldr r2, [pc, #12] @ (800a484 ) 800a476: f043 0306 orr.w r3, r3, #6 800a47a: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 800a47c: bf00 nop 800a47e: 3708 adds r7, #8 800a480: 46bd mov sp, r7 800a482: bd80 pop {r7, pc} 800a484: e000ed00 .word 0xe000ed00 0800a488 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a488: b580 push {r7, lr} 800a48a: b082 sub sp, #8 800a48c: af00 add r7, sp, #0 800a48e: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 800a490: 687b ldr r3, [r7, #4] 800a492: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a496: 4618 mov r0, r3 800a498: f7fe fd76 bl 8008f88 } 800a49c: bf00 nop 800a49e: 3708 adds r7, #8 800a4a0: 46bd mov sp, r7 800a4a2: bd80 pop {r7, pc} 0800a4a4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a4a4: b580 push {r7, lr} 800a4a6: b082 sub sp, #8 800a4a8: af00 add r7, sp, #0 800a4aa: 6078 str r0, [r7, #4] 800a4ac: 460b mov r3, r1 800a4ae: 70fb strb r3, [r7, #3] USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800a4b0: 687b ldr r3, [r7, #4] 800a4b2: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a4b6: 78fa ldrb r2, [r7, #3] 800a4b8: 4611 mov r1, r2 800a4ba: 4618 mov r0, r3 800a4bc: f7fe fdce bl 800905c } 800a4c0: bf00 nop 800a4c2: 3708 adds r7, #8 800a4c4: 46bd mov sp, r7 800a4c6: bd80 pop {r7, pc} 0800a4c8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a4c8: b580 push {r7, lr} 800a4ca: b082 sub sp, #8 800a4cc: af00 add r7, sp, #0 800a4ce: 6078 str r0, [r7, #4] 800a4d0: 460b mov r3, r1 800a4d2: 70fb strb r3, [r7, #3] USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800a4d4: 687b ldr r3, [r7, #4] 800a4d6: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a4da: 78fa ldrb r2, [r7, #3] 800a4dc: 4611 mov r1, r2 800a4de: 4618 mov r0, r3 800a4e0: f7fe fd8a bl 8008ff8 } 800a4e4: bf00 nop 800a4e6: 3708 adds r7, #8 800a4e8: 46bd mov sp, r7 800a4ea: bd80 pop {r7, pc} 0800a4ec : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a4ec: b580 push {r7, lr} 800a4ee: b082 sub sp, #8 800a4f0: af00 add r7, sp, #0 800a4f2: 6078 str r0, [r7, #4] USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); 800a4f4: 687b ldr r3, [r7, #4] 800a4f6: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a4fa: 4618 mov r0, r3 800a4fc: f7fe fde0 bl 80090c0 } 800a500: bf00 nop 800a502: 3708 adds r7, #8 800a504: 46bd mov sp, r7 800a506: bd80 pop {r7, pc} 0800a508 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a508: b580 push {r7, lr} 800a50a: b082 sub sp, #8 800a50c: af00 add r7, sp, #0 800a50e: 6078 str r0, [r7, #4] USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); 800a510: 687b ldr r3, [r7, #4] 800a512: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a516: 4618 mov r0, r3 800a518: f7fe fddd bl 80090d6 } 800a51c: bf00 nop 800a51e: 3708 adds r7, #8 800a520: 46bd mov sp, r7 800a522: bd80 pop {r7, pc} 0800a524 : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 800a524: b580 push {r7, lr} 800a526: b082 sub sp, #8 800a528: af00 add r7, sp, #0 800a52a: 6078 str r0, [r7, #4] /* Init USB Ip. */ if (pdev->id == DEVICE_FS) { 800a52c: 687b ldr r3, [r7, #4] 800a52e: 781b ldrb r3, [r3, #0] 800a530: 2b00 cmp r3, #0 800a532: d13c bne.n 800a5ae /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; 800a534: 4a20 ldr r2, [pc, #128] @ (800a5b8 ) 800a536: 687b ldr r3, [r7, #4] 800a538: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0 pdev->pData = &hpcd_USB_OTG_FS; 800a53c: 687b ldr r3, [r7, #4] 800a53e: 4a1e ldr r2, [pc, #120] @ (800a5b8 ) 800a540: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8 hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 800a544: 4b1c ldr r3, [pc, #112] @ (800a5b8 ) 800a546: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 800a54a: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 6; 800a54c: 4b1a ldr r3, [pc, #104] @ (800a5b8 ) 800a54e: 2206 movs r2, #6 800a550: 711a strb r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 800a552: 4b19 ldr r3, [pc, #100] @ (800a5b8 ) 800a554: 2202 movs r2, #2 800a556: 71da strb r2, [r3, #7] hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; 800a558: 4b17 ldr r3, [pc, #92] @ (800a5b8 ) 800a55a: 2200 movs r2, #0 800a55c: 719a strb r2, [r3, #6] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 800a55e: 4b16 ldr r3, [pc, #88] @ (800a5b8 ) 800a560: 2202 movs r2, #2 800a562: 725a strb r2, [r3, #9] hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; 800a564: 4b14 ldr r3, [pc, #80] @ (800a5b8 ) 800a566: 2200 movs r2, #0 800a568: 729a strb r2, [r3, #10] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 800a56a: 4b13 ldr r3, [pc, #76] @ (800a5b8 ) 800a56c: 2200 movs r2, #0 800a56e: 72da strb r2, [r3, #11] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 800a570: 4b11 ldr r3, [pc, #68] @ (800a5b8 ) 800a572: 2200 movs r2, #0 800a574: 731a strb r2, [r3, #12] hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; 800a576: 4b10 ldr r3, [pc, #64] @ (800a5b8 ) 800a578: 2200 movs r2, #0 800a57a: 739a strb r2, [r3, #14] hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 800a57c: 4b0e ldr r3, [pc, #56] @ (800a5b8 ) 800a57e: 2200 movs r2, #0 800a580: 73da strb r2, [r3, #15] if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 800a582: 480d ldr r0, [pc, #52] @ (800a5b8 ) 800a584: f7f8 fa9e bl 8002ac4 800a588: 4603 mov r3, r0 800a58a: 2b00 cmp r3, #0 800a58c: d001 beq.n 800a592 { Error_Handler( ); 800a58e: f7f6 fc13 bl 8000db8 HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback); HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); 800a592: 2180 movs r1, #128 @ 0x80 800a594: 4808 ldr r0, [pc, #32] @ (800a5b8 ) 800a596: f7f9 fce6 bl 8003f66 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); 800a59a: 2240 movs r2, #64 @ 0x40 800a59c: 2100 movs r1, #0 800a59e: 4806 ldr r0, [pc, #24] @ (800a5b8 ) 800a5a0: f7f9 fc9a bl 8003ed8 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); 800a5a4: 2280 movs r2, #128 @ 0x80 800a5a6: 2101 movs r1, #1 800a5a8: 4803 ldr r0, [pc, #12] @ (800a5b8 ) 800a5aa: f7f9 fc95 bl 8003ed8 } return USBD_OK; 800a5ae: 2300 movs r3, #0 } 800a5b0: 4618 mov r0, r3 800a5b2: 3708 adds r7, #8 800a5b4: 46bd mov sp, r7 800a5b6: bd80 pop {r7, pc} 800a5b8: 20000c00 .word 0x20000c00 0800a5bc : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 800a5bc: b580 push {r7, lr} 800a5be: b084 sub sp, #16 800a5c0: af00 add r7, sp, #0 800a5c2: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 800a5c4: 2300 movs r3, #0 800a5c6: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a5c8: 2300 movs r3, #0 800a5ca: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 800a5cc: 687b ldr r3, [r7, #4] 800a5ce: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a5d2: 4618 mov r0, r3 800a5d4: f7f8 fb8c bl 8002cf0 800a5d8: 4603 mov r3, r0 800a5da: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a5dc: 7bfb ldrb r3, [r7, #15] 800a5de: 4618 mov r0, r3 800a5e0: f000 f97e bl 800a8e0 800a5e4: 4603 mov r3, r0 800a5e6: 73bb strb r3, [r7, #14] return usb_status; 800a5e8: 7bbb ldrb r3, [r7, #14] } 800a5ea: 4618 mov r0, r3 800a5ec: 3710 adds r7, #16 800a5ee: 46bd mov sp, r7 800a5f0: bd80 pop {r7, pc} 0800a5f2 : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 800a5f2: b580 push {r7, lr} 800a5f4: b084 sub sp, #16 800a5f6: af00 add r7, sp, #0 800a5f8: 6078 str r0, [r7, #4] 800a5fa: 4608 mov r0, r1 800a5fc: 4611 mov r1, r2 800a5fe: 461a mov r2, r3 800a600: 4603 mov r3, r0 800a602: 70fb strb r3, [r7, #3] 800a604: 460b mov r3, r1 800a606: 70bb strb r3, [r7, #2] 800a608: 4613 mov r3, r2 800a60a: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 800a60c: 2300 movs r3, #0 800a60e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a610: 2300 movs r3, #0 800a612: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 800a614: 687b ldr r3, [r7, #4] 800a616: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a61a: 78bb ldrb r3, [r7, #2] 800a61c: 883a ldrh r2, [r7, #0] 800a61e: 78f9 ldrb r1, [r7, #3] 800a620: f7f9 f88d bl 800373e 800a624: 4603 mov r3, r0 800a626: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a628: 7bfb ldrb r3, [r7, #15] 800a62a: 4618 mov r0, r3 800a62c: f000 f958 bl 800a8e0 800a630: 4603 mov r3, r0 800a632: 73bb strb r3, [r7, #14] return usb_status; 800a634: 7bbb ldrb r3, [r7, #14] } 800a636: 4618 mov r0, r3 800a638: 3710 adds r7, #16 800a63a: 46bd mov sp, r7 800a63c: bd80 pop {r7, pc} 0800a63e : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a63e: b580 push {r7, lr} 800a640: b084 sub sp, #16 800a642: af00 add r7, sp, #0 800a644: 6078 str r0, [r7, #4] 800a646: 460b mov r3, r1 800a648: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a64a: 2300 movs r3, #0 800a64c: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a64e: 2300 movs r3, #0 800a650: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 800a652: 687b ldr r3, [r7, #4] 800a654: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a658: 78fa ldrb r2, [r7, #3] 800a65a: 4611 mov r1, r2 800a65c: 4618 mov r0, r3 800a65e: f7f9 f8d8 bl 8003812 800a662: 4603 mov r3, r0 800a664: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a666: 7bfb ldrb r3, [r7, #15] 800a668: 4618 mov r0, r3 800a66a: f000 f939 bl 800a8e0 800a66e: 4603 mov r3, r0 800a670: 73bb strb r3, [r7, #14] return usb_status; 800a672: 7bbb ldrb r3, [r7, #14] } 800a674: 4618 mov r0, r3 800a676: 3710 adds r7, #16 800a678: 46bd mov sp, r7 800a67a: bd80 pop {r7, pc} 0800a67c : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a67c: b580 push {r7, lr} 800a67e: b084 sub sp, #16 800a680: af00 add r7, sp, #0 800a682: 6078 str r0, [r7, #4] 800a684: 460b mov r3, r1 800a686: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a688: 2300 movs r3, #0 800a68a: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a68c: 2300 movs r3, #0 800a68e: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 800a690: 687b ldr r3, [r7, #4] 800a692: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a696: 78fa ldrb r2, [r7, #3] 800a698: 4611 mov r1, r2 800a69a: 4618 mov r0, r3 800a69c: f7f9 f978 bl 8003990 800a6a0: 4603 mov r3, r0 800a6a2: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a6a4: 7bfb ldrb r3, [r7, #15] 800a6a6: 4618 mov r0, r3 800a6a8: f000 f91a bl 800a8e0 800a6ac: 4603 mov r3, r0 800a6ae: 73bb strb r3, [r7, #14] return usb_status; 800a6b0: 7bbb ldrb r3, [r7, #14] } 800a6b2: 4618 mov r0, r3 800a6b4: 3710 adds r7, #16 800a6b6: 46bd mov sp, r7 800a6b8: bd80 pop {r7, pc} 0800a6ba : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a6ba: b580 push {r7, lr} 800a6bc: b084 sub sp, #16 800a6be: af00 add r7, sp, #0 800a6c0: 6078 str r0, [r7, #4] 800a6c2: 460b mov r3, r1 800a6c4: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a6c6: 2300 movs r3, #0 800a6c8: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a6ca: 2300 movs r3, #0 800a6cc: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 800a6ce: 687b ldr r3, [r7, #4] 800a6d0: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a6d4: 78fa ldrb r2, [r7, #3] 800a6d6: 4611 mov r1, r2 800a6d8: 4618 mov r0, r3 800a6da: f7f9 f9bc bl 8003a56 800a6de: 4603 mov r3, r0 800a6e0: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a6e2: 7bfb ldrb r3, [r7, #15] 800a6e4: 4618 mov r0, r3 800a6e6: f000 f8fb bl 800a8e0 800a6ea: 4603 mov r3, r0 800a6ec: 73bb strb r3, [r7, #14] return usb_status; 800a6ee: 7bbb ldrb r3, [r7, #14] } 800a6f0: 4618 mov r0, r3 800a6f2: 3710 adds r7, #16 800a6f4: 46bd mov sp, r7 800a6f6: bd80 pop {r7, pc} 0800a6f8 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a6f8: b480 push {r7} 800a6fa: b085 sub sp, #20 800a6fc: af00 add r7, sp, #0 800a6fe: 6078 str r0, [r7, #4] 800a700: 460b mov r3, r1 800a702: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 800a704: 687b ldr r3, [r7, #4] 800a706: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a70a: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 800a70c: f997 3003 ldrsb.w r3, [r7, #3] 800a710: 2b00 cmp r3, #0 800a712: da0b bge.n 800a72c { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 800a714: 78fb ldrb r3, [r7, #3] 800a716: f003 027f and.w r2, r3, #127 @ 0x7f 800a71a: 68f9 ldr r1, [r7, #12] 800a71c: 4613 mov r3, r2 800a71e: 00db lsls r3, r3, #3 800a720: 4413 add r3, r2 800a722: 009b lsls r3, r3, #2 800a724: 440b add r3, r1 800a726: 3316 adds r3, #22 800a728: 781b ldrb r3, [r3, #0] 800a72a: e00b b.n 800a744 } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 800a72c: 78fb ldrb r3, [r7, #3] 800a72e: f003 027f and.w r2, r3, #127 @ 0x7f 800a732: 68f9 ldr r1, [r7, #12] 800a734: 4613 mov r3, r2 800a736: 00db lsls r3, r3, #3 800a738: 4413 add r3, r2 800a73a: 009b lsls r3, r3, #2 800a73c: 440b add r3, r1 800a73e: f203 2356 addw r3, r3, #598 @ 0x256 800a742: 781b ldrb r3, [r3, #0] } } 800a744: 4618 mov r0, r3 800a746: 3714 adds r7, #20 800a748: 46bd mov sp, r7 800a74a: f85d 7b04 ldr.w r7, [sp], #4 800a74e: 4770 bx lr 0800a750 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 800a750: b580 push {r7, lr} 800a752: b084 sub sp, #16 800a754: af00 add r7, sp, #0 800a756: 6078 str r0, [r7, #4] 800a758: 460b mov r3, r1 800a75a: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a75c: 2300 movs r3, #0 800a75e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a760: 2300 movs r3, #0 800a762: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 800a764: 687b ldr r3, [r7, #4] 800a766: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a76a: 78fa ldrb r2, [r7, #3] 800a76c: 4611 mov r1, r2 800a76e: 4618 mov r0, r3 800a770: f7f8 ffc1 bl 80036f6 800a774: 4603 mov r3, r0 800a776: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a778: 7bfb ldrb r3, [r7, #15] 800a77a: 4618 mov r0, r3 800a77c: f000 f8b0 bl 800a8e0 800a780: 4603 mov r3, r0 800a782: 73bb strb r3, [r7, #14] return usb_status; 800a784: 7bbb ldrb r3, [r7, #14] } 800a786: 4618 mov r0, r3 800a788: 3710 adds r7, #16 800a78a: 46bd mov sp, r7 800a78c: bd80 pop {r7, pc} 0800a78e : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800a78e: b580 push {r7, lr} 800a790: b086 sub sp, #24 800a792: af00 add r7, sp, #0 800a794: 60f8 str r0, [r7, #12] 800a796: 607a str r2, [r7, #4] 800a798: 603b str r3, [r7, #0] 800a79a: 460b mov r3, r1 800a79c: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800a79e: 2300 movs r3, #0 800a7a0: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800a7a2: 2300 movs r3, #0 800a7a4: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 800a7a6: 68fb ldr r3, [r7, #12] 800a7a8: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a7ac: 7af9 ldrb r1, [r7, #11] 800a7ae: 683b ldr r3, [r7, #0] 800a7b0: 687a ldr r2, [r7, #4] 800a7b2: f7f9 f8b3 bl 800391c 800a7b6: 4603 mov r3, r0 800a7b8: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800a7ba: 7dfb ldrb r3, [r7, #23] 800a7bc: 4618 mov r0, r3 800a7be: f000 f88f bl 800a8e0 800a7c2: 4603 mov r3, r0 800a7c4: 75bb strb r3, [r7, #22] return usb_status; 800a7c6: 7dbb ldrb r3, [r7, #22] } 800a7c8: 4618 mov r0, r3 800a7ca: 3718 adds r7, #24 800a7cc: 46bd mov sp, r7 800a7ce: bd80 pop {r7, pc} 0800a7d0 : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800a7d0: b580 push {r7, lr} 800a7d2: b086 sub sp, #24 800a7d4: af00 add r7, sp, #0 800a7d6: 60f8 str r0, [r7, #12] 800a7d8: 607a str r2, [r7, #4] 800a7da: 603b str r3, [r7, #0] 800a7dc: 460b mov r3, r1 800a7de: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800a7e0: 2300 movs r3, #0 800a7e2: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800a7e4: 2300 movs r3, #0 800a7e6: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 800a7e8: 68fb ldr r3, [r7, #12] 800a7ea: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a7ee: 7af9 ldrb r1, [r7, #11] 800a7f0: 683b ldr r3, [r7, #0] 800a7f2: 687a ldr r2, [r7, #4] 800a7f4: f7f9 f857 bl 80038a6 800a7f8: 4603 mov r3, r0 800a7fa: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800a7fc: 7dfb ldrb r3, [r7, #23] 800a7fe: 4618 mov r0, r3 800a800: f000 f86e bl 800a8e0 800a804: 4603 mov r3, r0 800a806: 75bb strb r3, [r7, #22] return usb_status; 800a808: 7dbb ldrb r3, [r7, #22] } 800a80a: 4618 mov r0, r3 800a80c: 3718 adds r7, #24 800a80e: 46bd mov sp, r7 800a810: bd80 pop {r7, pc} ... 0800a814 : * @param hpcd: PCD handle * @param msg: LPM message * @retval None */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { 800a814: b580 push {r7, lr} 800a816: b082 sub sp, #8 800a818: af00 add r7, sp, #0 800a81a: 6078 str r0, [r7, #4] 800a81c: 460b mov r3, r1 800a81e: 70fb strb r3, [r7, #3] switch (msg) 800a820: 78fb ldrb r3, [r7, #3] 800a822: 2b00 cmp r3, #0 800a824: d002 beq.n 800a82c 800a826: 2b01 cmp r3, #1 800a828: d01f beq.n 800a86a /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } } 800a82a: e03b b.n 800a8a4 if (hpcd->Init.low_power_enable) 800a82c: 687b ldr r3, [r7, #4] 800a82e: 7adb ldrb r3, [r3, #11] 800a830: 2b00 cmp r3, #0 800a832: d007 beq.n 800a844 SystemClock_Config(); 800a834: f7f6 f8ae bl 8000994 SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a838: 4b1c ldr r3, [pc, #112] @ (800a8ac ) 800a83a: 691b ldr r3, [r3, #16] 800a83c: 4a1b ldr r2, [pc, #108] @ (800a8ac ) 800a83e: f023 0306 bic.w r3, r3, #6 800a842: 6113 str r3, [r2, #16] __HAL_PCD_UNGATE_PHYCLOCK(hpcd); 800a844: 687b ldr r3, [r7, #4] 800a846: 681b ldr r3, [r3, #0] 800a848: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a84c: 681b ldr r3, [r3, #0] 800a84e: 687a ldr r2, [r7, #4] 800a850: 6812 ldr r2, [r2, #0] 800a852: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a856: f023 0301 bic.w r3, r3, #1 800a85a: 6013 str r3, [r2, #0] USBD_LL_Resume(hpcd->pData); 800a85c: 687b ldr r3, [r7, #4] 800a85e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a862: 4618 mov r0, r3 800a864: f7fe fb90 bl 8008f88 break; 800a868: e01c b.n 800a8a4 __HAL_PCD_GATE_PHYCLOCK(hpcd); 800a86a: 687b ldr r3, [r7, #4] 800a86c: 681b ldr r3, [r3, #0] 800a86e: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a872: 681b ldr r3, [r3, #0] 800a874: 687a ldr r2, [r7, #4] 800a876: 6812 ldr r2, [r2, #0] 800a878: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a87c: f043 0301 orr.w r3, r3, #1 800a880: 6013 str r3, [r2, #0] USBD_LL_Suspend(hpcd->pData); 800a882: 687b ldr r3, [r7, #4] 800a884: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a888: 4618 mov r0, r3 800a88a: f7fe fb61 bl 8008f50 if (hpcd->Init.low_power_enable) 800a88e: 687b ldr r3, [r7, #4] 800a890: 7adb ldrb r3, [r3, #11] 800a892: 2b00 cmp r3, #0 800a894: d005 beq.n 800a8a2 SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a896: 4b05 ldr r3, [pc, #20] @ (800a8ac ) 800a898: 691b ldr r3, [r3, #16] 800a89a: 4a04 ldr r2, [pc, #16] @ (800a8ac ) 800a89c: f043 0306 orr.w r3, r3, #6 800a8a0: 6113 str r3, [r2, #16] break; 800a8a2: bf00 nop } 800a8a4: bf00 nop 800a8a6: 3708 adds r7, #8 800a8a8: 46bd mov sp, r7 800a8aa: bd80 pop {r7, pc} 800a8ac: e000ed00 .word 0xe000ed00 0800a8b0 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 800a8b0: b480 push {r7} 800a8b2: b083 sub sp, #12 800a8b4: af00 add r7, sp, #0 800a8b6: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 800a8b8: 4b03 ldr r3, [pc, #12] @ (800a8c8 ) } 800a8ba: 4618 mov r0, r3 800a8bc: 370c adds r7, #12 800a8be: 46bd mov sp, r7 800a8c0: f85d 7b04 ldr.w r7, [sp], #4 800a8c4: 4770 bx lr 800a8c6: bf00 nop 800a8c8: 200010e4 .word 0x200010e4 0800a8cc : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 800a8cc: b480 push {r7} 800a8ce: b083 sub sp, #12 800a8d0: af00 add r7, sp, #0 800a8d2: 6078 str r0, [r7, #4] } 800a8d4: bf00 nop 800a8d6: 370c adds r7, #12 800a8d8: 46bd mov sp, r7 800a8da: f85d 7b04 ldr.w r7, [sp], #4 800a8de: 4770 bx lr 0800a8e0 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 800a8e0: b480 push {r7} 800a8e2: b085 sub sp, #20 800a8e4: af00 add r7, sp, #0 800a8e6: 4603 mov r3, r0 800a8e8: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 800a8ea: 2300 movs r3, #0 800a8ec: 73fb strb r3, [r7, #15] switch (hal_status) 800a8ee: 79fb ldrb r3, [r7, #7] 800a8f0: 2b03 cmp r3, #3 800a8f2: d817 bhi.n 800a924 800a8f4: a201 add r2, pc, #4 @ (adr r2, 800a8fc ) 800a8f6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a8fa: bf00 nop 800a8fc: 0800a90d .word 0x0800a90d 800a900: 0800a913 .word 0x0800a913 800a904: 0800a919 .word 0x0800a919 800a908: 0800a91f .word 0x0800a91f { case HAL_OK : usb_status = USBD_OK; 800a90c: 2300 movs r3, #0 800a90e: 73fb strb r3, [r7, #15] break; 800a910: e00b b.n 800a92a case HAL_ERROR : usb_status = USBD_FAIL; 800a912: 2303 movs r3, #3 800a914: 73fb strb r3, [r7, #15] break; 800a916: e008 b.n 800a92a case HAL_BUSY : usb_status = USBD_BUSY; 800a918: 2301 movs r3, #1 800a91a: 73fb strb r3, [r7, #15] break; 800a91c: e005 b.n 800a92a case HAL_TIMEOUT : usb_status = USBD_FAIL; 800a91e: 2303 movs r3, #3 800a920: 73fb strb r3, [r7, #15] break; 800a922: e002 b.n 800a92a default : usb_status = USBD_FAIL; 800a924: 2303 movs r3, #3 800a926: 73fb strb r3, [r7, #15] break; 800a928: bf00 nop } return usb_status; 800a92a: 7bfb ldrb r3, [r7, #15] } 800a92c: 4618 mov r0, r3 800a92e: 3714 adds r7, #20 800a930: 46bd mov sp, r7 800a932: f85d 7b04 ldr.w r7, [sp], #4 800a936: 4770 bx lr 0800a938 : 800a938: 4402 add r2, r0 800a93a: 4603 mov r3, r0 800a93c: 4293 cmp r3, r2 800a93e: d100 bne.n 800a942 800a940: 4770 bx lr 800a942: f803 1b01 strb.w r1, [r3], #1 800a946: e7f9 b.n 800a93c 0800a948 <__libc_init_array>: 800a948: b570 push {r4, r5, r6, lr} 800a94a: 4d0d ldr r5, [pc, #52] @ (800a980 <__libc_init_array+0x38>) 800a94c: 4c0d ldr r4, [pc, #52] @ (800a984 <__libc_init_array+0x3c>) 800a94e: 1b64 subs r4, r4, r5 800a950: 10a4 asrs r4, r4, #2 800a952: 2600 movs r6, #0 800a954: 42a6 cmp r6, r4 800a956: d109 bne.n 800a96c <__libc_init_array+0x24> 800a958: 4d0b ldr r5, [pc, #44] @ (800a988 <__libc_init_array+0x40>) 800a95a: 4c0c ldr r4, [pc, #48] @ (800a98c <__libc_init_array+0x44>) 800a95c: f000 f826 bl 800a9ac <_init> 800a960: 1b64 subs r4, r4, r5 800a962: 10a4 asrs r4, r4, #2 800a964: 2600 movs r6, #0 800a966: 42a6 cmp r6, r4 800a968: d105 bne.n 800a976 <__libc_init_array+0x2e> 800a96a: bd70 pop {r4, r5, r6, pc} 800a96c: f855 3b04 ldr.w r3, [r5], #4 800a970: 4798 blx r3 800a972: 3601 adds r6, #1 800a974: e7ee b.n 800a954 <__libc_init_array+0xc> 800a976: f855 3b04 ldr.w r3, [r5], #4 800a97a: 4798 blx r3 800a97c: 3601 adds r6, #1 800a97e: e7f2 b.n 800a966 <__libc_init_array+0x1e> 800a980: 0800aa28 .word 0x0800aa28 800a984: 0800aa28 .word 0x0800aa28 800a988: 0800aa28 .word 0x0800aa28 800a98c: 0800aa2c .word 0x0800aa2c 0800a990 : 800a990: 440a add r2, r1 800a992: 4291 cmp r1, r2 800a994: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 800a998: d100 bne.n 800a99c 800a99a: 4770 bx lr 800a99c: b510 push {r4, lr} 800a99e: f811 4b01 ldrb.w r4, [r1], #1 800a9a2: f803 4f01 strb.w r4, [r3, #1]! 800a9a6: 4291 cmp r1, r2 800a9a8: d1f9 bne.n 800a99e 800a9aa: bd10 pop {r4, pc} 0800a9ac <_init>: 800a9ac: b5f8 push {r3, r4, r5, r6, r7, lr} 800a9ae: bf00 nop 800a9b0: bcf8 pop {r3, r4, r5, r6, r7} 800a9b2: bc08 pop {r3} 800a9b4: 469e mov lr, r3 800a9b6: 4770 bx lr 0800a9b8 <_fini>: 800a9b8: b5f8 push {r3, r4, r5, r6, r7, lr} 800a9ba: bf00 nop 800a9bc: bcf8 pop {r3, r4, r5, r6, r7} 800a9be: bc08 pop {r3} 800a9c0: 469e mov lr, r3 800a9c2: 4770 bx lr