modularkbd.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001c4 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000a968 080001c4 080001c4 000011c4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000005c 0800ab2c 0800ab2c 0000bb2c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800ab88 0800ab88 0000c1a0 2**0 CONTENTS, READONLY 4 .ARM 00000008 0800ab88 0800ab88 0000bb88 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800ab90 0800ab90 0000c1a0 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800ab90 0800ab90 0000bb90 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 0800ab94 0800ab94 0000bb94 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 000001a0 20000000 0800ab98 0000c000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000f58 200001a0 0800ad38 0000c1a0 2**2 ALLOC 10 ._user_heap_stack 00000600 200010f8 0800ad38 0000d0f8 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000c1a0 2**0 CONTENTS, READONLY 12 .debug_info 0001af7a 00000000 00000000 0000c1d0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00004057 00000000 00000000 0002714a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001780 00000000 00000000 0002b1a8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 0000123e 00000000 00000000 0002c928 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00026060 00000000 00000000 0002db66 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001e635 00000000 00000000 00053bc6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000d7eb7 00000000 00000000 000721fb 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0014a0b2 2**0 CONTENTS, READONLY 20 .debug_frame 000062c4 00000000 00000000 0014a0f8 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000062 00000000 00000000 001503bc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001c4 <__do_global_dtors_aux>: 80001c4: b510 push {r4, lr} 80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>) 80001c8: 7823 ldrb r3, [r4, #0] 80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16> 80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>) 80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12> 80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>) 80001d2: f3af 8000 nop.w 80001d6: 2301 movs r3, #1 80001d8: 7023 strb r3, [r4, #0] 80001da: bd10 pop {r4, pc} 80001dc: 200001a0 .word 0x200001a0 80001e0: 00000000 .word 0x00000000 80001e4: 0800ab14 .word 0x0800ab14 080001e8 : 80001e8: b508 push {r3, lr} 80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 ) 80001ec: b11b cbz r3, 80001f6 80001ee: 4903 ldr r1, [pc, #12] @ (80001fc ) 80001f0: 4803 ldr r0, [pc, #12] @ (8000200 ) 80001f2: f3af 8000 nop.w 80001f6: bd08 pop {r3, pc} 80001f8: 00000000 .word 0x00000000 80001fc: 200001a4 .word 0x200001a4 8000200: 0800ab14 .word 0x0800ab14 08000204 <__aeabi_uldivmod>: 8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18> 8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18> 8000208: 2900 cmp r1, #0 800020a: bf08 it eq 800020c: 2800 cmpeq r0, #0 800020e: bf1c itt ne 8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000218: f000 b988 b.w 800052c <__aeabi_idiv0> 800021c: f1ad 0c08 sub.w ip, sp, #8 8000220: e96d ce04 strd ip, lr, [sp, #-16]! 8000224: f000 f806 bl 8000234 <__udivmoddi4> 8000228: f8dd e004 ldr.w lr, [sp, #4] 800022c: e9dd 2302 ldrd r2, r3, [sp, #8] 8000230: b004 add sp, #16 8000232: 4770 bx lr 08000234 <__udivmoddi4>: 8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000238: 9d08 ldr r5, [sp, #32] 800023a: 468e mov lr, r1 800023c: 4604 mov r4, r0 800023e: 4688 mov r8, r1 8000240: 2b00 cmp r3, #0 8000242: d14a bne.n 80002da <__udivmoddi4+0xa6> 8000244: 428a cmp r2, r1 8000246: 4617 mov r7, r2 8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc> 800024a: fab2 f682 clz r6, r2 800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30> 8000250: f1c6 0320 rsb r3, r6, #32 8000254: fa01 f806 lsl.w r8, r1, r6 8000258: fa20 f303 lsr.w r3, r0, r3 800025c: 40b7 lsls r7, r6 800025e: ea43 0808 orr.w r8, r3, r8 8000262: 40b4 lsls r4, r6 8000264: ea4f 4e17 mov.w lr, r7, lsr #16 8000268: fa1f fc87 uxth.w ip, r7 800026c: fbb8 f1fe udiv r1, r8, lr 8000270: 0c23 lsrs r3, r4, #16 8000272: fb0e 8811 mls r8, lr, r1, r8 8000276: ea43 4308 orr.w r3, r3, r8, lsl #16 800027a: fb01 f20c mul.w r2, r1, ip 800027e: 429a cmp r2, r3 8000280: d909 bls.n 8000296 <__udivmoddi4+0x62> 8000282: 18fb adds r3, r7, r3 8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c> 800028c: 429a cmp r2, r3 800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c> 8000292: 3902 subs r1, #2 8000294: 443b add r3, r7 8000296: 1a9a subs r2, r3, r2 8000298: b2a3 uxth r3, r4 800029a: fbb2 f0fe udiv r0, r2, lr 800029e: fb0e 2210 mls r2, lr, r0, r2 80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16 80002a6: fb00 fc0c mul.w ip, r0, ip 80002aa: 459c cmp ip, r3 80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e> 80002ae: 18fb adds r3, r7, r3 80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230> 80002b8: 459c cmp ip, r3 80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230> 80002be: 443b add r3, r7 80002c0: 3802 subs r0, #2 80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16 80002c6: eba3 030c sub.w r3, r3, ip 80002ca: 2100 movs r1, #0 80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2> 80002ce: 40f3 lsrs r3, r6 80002d0: 2200 movs r2, #0 80002d2: e9c5 3200 strd r3, r2, [r5] 80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002da: 428b cmp r3, r1 80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6> 80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0> 80002e0: e9c5 0100 strd r0, r1, [r5] 80002e4: 2100 movs r1, #0 80002e6: 4608 mov r0, r1 80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2> 80002ea: fab3 f183 clz r1, r3 80002ee: 2900 cmp r1, #0 80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c> 80002f2: 4573 cmp r3, lr 80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8> 80002f6: 4282 cmp r2, r0 80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2> 80002fc: 1a84 subs r4, r0, r2 80002fe: eb6e 0203 sbc.w r2, lr, r3 8000302: 2001 movs r0, #1 8000304: 4690 mov r8, r2 8000306: 2d00 cmp r5, #0 8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2> 800030a: e9c5 4800 strd r4, r8, [r5] 800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2> 8000310: 2a00 cmp r2, #0 8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202> 8000316: fab2 f682 clz r6, r2 800031a: 2e00 cmp r6, #0 800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234> 8000320: 1a8a subs r2, r1, r2 8000322: 0c03 lsrs r3, r0, #16 8000324: ea4f 4e17 mov.w lr, r7, lsr #16 8000328: b280 uxth r0, r0 800032a: b2bc uxth r4, r7 800032c: 2101 movs r1, #1 800032e: fbb2 fcfe udiv ip, r2, lr 8000332: fb0e 221c mls r2, lr, ip, r2 8000336: ea43 4302 orr.w r3, r3, r2, lsl #16 800033a: fb04 f20c mul.w r2, r4, ip 800033e: 429a cmp r2, r3 8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e> 8000342: 18fb adds r3, r7, r3 8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c> 800034a: 429a cmp r2, r3 800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc> 8000350: 46c4 mov ip, r8 8000352: 1a9b subs r3, r3, r2 8000354: fbb3 f2fe udiv r2, r3, lr 8000358: fb0e 3312 mls r3, lr, r2, r3 800035c: ea40 4303 orr.w r3, r0, r3, lsl #16 8000360: fb02 f404 mul.w r4, r2, r4 8000364: 429c cmp r4, r3 8000366: d907 bls.n 8000378 <__udivmoddi4+0x144> 8000368: 18fb adds r3, r7, r3 800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142> 8000370: 429c cmp r4, r3 8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6> 8000376: 4602 mov r2, r0 8000378: 1b1b subs r3, r3, r4 800037a: ea42 400c orr.w r0, r2, ip, lsl #16 800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98> 8000380: f1c1 0620 rsb r6, r1, #32 8000384: 408b lsls r3, r1 8000386: fa22 f706 lsr.w r7, r2, r6 800038a: 431f orrs r7, r3 800038c: fa0e f401 lsl.w r4, lr, r1 8000390: fa20 f306 lsr.w r3, r0, r6 8000394: fa2e fe06 lsr.w lr, lr, r6 8000398: ea4f 4917 mov.w r9, r7, lsr #16 800039c: 4323 orrs r3, r4 800039e: fa00 f801 lsl.w r8, r0, r1 80003a2: fa1f fc87 uxth.w ip, r7 80003a6: fbbe f0f9 udiv r0, lr, r9 80003aa: 0c1c lsrs r4, r3, #16 80003ac: fb09 ee10 mls lr, r9, r0, lr 80003b0: ea44 440e orr.w r4, r4, lr, lsl #16 80003b4: fb00 fe0c mul.w lr, r0, ip 80003b8: 45a6 cmp lr, r4 80003ba: fa02 f201 lsl.w r2, r2, r1 80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0> 80003c0: 193c adds r4, r7, r4 80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce> 80003ca: 45a6 cmp lr, r4 80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce> 80003d0: 3802 subs r0, #2 80003d2: 443c add r4, r7 80003d4: eba4 040e sub.w r4, r4, lr 80003d8: fa1f fe83 uxth.w lr, r3 80003dc: fbb4 f3f9 udiv r3, r4, r9 80003e0: fb09 4413 mls r4, r9, r3, r4 80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003e8: fb03 fc0c mul.w ip, r3, ip 80003ec: 45a4 cmp ip, r4 80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce> 80003f0: 193c adds r4, r7, r4 80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca> 80003fa: 45a4 cmp ip, r4 80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca> 80003fe: 3b02 subs r3, #2 8000400: 443c add r4, r7 8000402: ea43 4000 orr.w r0, r3, r0, lsl #16 8000406: eba4 040c sub.w r4, r4, ip 800040a: fba0 ec02 umull lr, ip, r0, r2 800040e: 4564 cmp r4, ip 8000410: 4673 mov r3, lr 8000412: 46e1 mov r9, ip 8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8> 8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4> 8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe> 800041a: ebb8 0203 subs.w r2, r8, r3 800041e: eb64 0409 sbc.w r4, r4, r9 8000422: fa04 f606 lsl.w r6, r4, r6 8000426: fa22 f301 lsr.w r3, r2, r1 800042a: 431e orrs r6, r3 800042c: 40cc lsrs r4, r1 800042e: e9c5 6400 strd r6, r4, [r5] 8000432: 2100 movs r1, #0 8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2> 8000436: fbb1 fcf2 udiv ip, r1, r2 800043a: 0c01 lsrs r1, r0, #16 800043c: ea41 410e orr.w r1, r1, lr, lsl #16 8000440: b280 uxth r0, r0 8000442: ea40 4201 orr.w r2, r0, r1, lsl #16 8000446: 463b mov r3, r7 8000448: 4638 mov r0, r7 800044a: 463c mov r4, r7 800044c: 46b8 mov r8, r7 800044e: 46be mov lr, r7 8000450: 2620 movs r6, #32 8000452: fbb1 f1f7 udiv r1, r1, r7 8000456: eba2 0208 sub.w r2, r2, r8 800045a: ea41 410c orr.w r1, r1, ip, lsl #16 800045e: e766 b.n 800032e <__udivmoddi4+0xfa> 8000460: 4601 mov r1, r0 8000462: e718 b.n 8000296 <__udivmoddi4+0x62> 8000464: 4610 mov r0, r2 8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e> 8000468: f1c6 0220 rsb r2, r6, #32 800046c: fa2e f302 lsr.w r3, lr, r2 8000470: 40b7 lsls r7, r6 8000472: 40b1 lsls r1, r6 8000474: fa20 f202 lsr.w r2, r0, r2 8000478: ea4f 4e17 mov.w lr, r7, lsr #16 800047c: 430a orrs r2, r1 800047e: fbb3 f8fe udiv r8, r3, lr 8000482: b2bc uxth r4, r7 8000484: fb0e 3318 mls r3, lr, r8, r3 8000488: 0c11 lsrs r1, r2, #16 800048a: ea41 4103 orr.w r1, r1, r3, lsl #16 800048e: fb08 f904 mul.w r9, r8, r4 8000492: 40b0 lsls r0, r6 8000494: 4589 cmp r9, r1 8000496: ea4f 4310 mov.w r3, r0, lsr #16 800049a: b280 uxth r0, r0 800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8> 800049e: 1879 adds r1, r7, r1 80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276> 80004a6: 4589 cmp r9, r1 80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6> 80004aa: eba1 0109 sub.w r1, r1, r9 80004ae: fbb1 f9fe udiv r9, r1, lr 80004b2: fb09 f804 mul.w r8, r9, r4 80004b6: fb0e 1119 mls r1, lr, r9, r1 80004ba: b292 uxth r2, r2 80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16 80004c0: 4542 cmp r2, r8 80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4> 80004c4: 18ba adds r2, r7, r2 80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222> 80004cc: 4542 cmp r2, r8 80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222> 80004d0: f1a9 0102 sub.w r1, r9, #2 80004d4: 443a add r2, r7 80004d6: e7be b.n 8000456 <__udivmoddi4+0x222> 80004d8: 45f0 cmp r8, lr 80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4> 80004dc: ebbe 0302 subs.w r3, lr, r2 80004e0: eb6c 0c07 sbc.w ip, ip, r7 80004e4: 3801 subs r0, #1 80004e6: 46e1 mov r9, ip 80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4> 80004ea: eba7 0909 sub.w r9, r7, r9 80004ee: 4449 add r1, r9 80004f0: f1a8 0c02 sub.w ip, r8, #2 80004f4: fbb1 f9fe udiv r9, r1, lr 80004f8: fb09 f804 mul.w r8, r9, r4 80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282> 80004fe: 4673 mov r3, lr 8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce> 8000502: 4650 mov r0, sl 8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0> 8000506: 4608 mov r0, r1 8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2> 800050a: 443b add r3, r7 800050c: 3a02 subs r2, #2 800050e: e733 b.n 8000378 <__udivmoddi4+0x144> 8000510: f1ac 0c02 sub.w ip, ip, #2 8000514: 443b add r3, r7 8000516: e71c b.n 8000352 <__udivmoddi4+0x11e> 8000518: 4649 mov r1, r9 800051a: e79c b.n 8000456 <__udivmoddi4+0x222> 800051c: eba1 0109 sub.w r1, r1, r9 8000520: 46c4 mov ip, r8 8000522: fbb1 f9fe udiv r9, r1, lr 8000526: fb09 f804 mul.w r8, r9, r4 800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282> 0800052c <__aeabi_idiv0>: 800052c: 4770 bx lr 800052e: bf00 nop 08000530 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 8000530: b580 push {r7, lr} 8000532: b082 sub sp, #8 8000534: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8000536: 2300 movs r3, #0 8000538: 607b str r3, [r7, #4] 800053a: 4b2f ldr r3, [pc, #188] @ (80005f8 ) 800053c: 6b1b ldr r3, [r3, #48] @ 0x30 800053e: 4a2e ldr r2, [pc, #184] @ (80005f8 ) 8000540: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000544: 6313 str r3, [r2, #48] @ 0x30 8000546: 4b2c ldr r3, [pc, #176] @ (80005f8 ) 8000548: 6b1b ldr r3, [r3, #48] @ 0x30 800054a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800054e: 607b str r3, [r7, #4] 8000550: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); 8000552: 2300 movs r3, #0 8000554: 603b str r3, [r7, #0] 8000556: 4b28 ldr r3, [pc, #160] @ (80005f8 ) 8000558: 6b1b ldr r3, [r3, #48] @ 0x30 800055a: 4a27 ldr r2, [pc, #156] @ (80005f8 ) 800055c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8000560: 6313 str r3, [r2, #48] @ 0x30 8000562: 4b25 ldr r3, [pc, #148] @ (80005f8 ) 8000564: 6b1b ldr r3, [r3, #48] @ 0x30 8000566: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800056a: 603b str r3, [r7, #0] 800056c: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); 800056e: 2200 movs r2, #0 8000570: 2100 movs r1, #0 8000572: 200b movs r0, #11 8000574: f001 fb33 bl 8001bde HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8000578: 200b movs r0, #11 800057a: f001 fb4c bl 8001c16 /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); 800057e: 2200 movs r2, #0 8000580: 2100 movs r1, #0 8000582: 200d movs r0, #13 8000584: f001 fb2b bl 8001bde HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8000588: 200d movs r0, #13 800058a: f001 fb44 bl 8001c16 /* DMA1_Stream4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0); 800058e: 2200 movs r2, #0 8000590: 2100 movs r1, #0 8000592: 200f movs r0, #15 8000594: f001 fb23 bl 8001bde HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); 8000598: 200f movs r0, #15 800059a: f001 fb3c bl 8001c16 /* DMA1_Stream5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); 800059e: 2200 movs r2, #0 80005a0: 2100 movs r1, #0 80005a2: 2010 movs r0, #16 80005a4: f001 fb1b bl 8001bde HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); 80005a8: 2010 movs r0, #16 80005aa: f001 fb34 bl 8001c16 /* DMA1_Stream6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0); 80005ae: 2200 movs r2, #0 80005b0: 2100 movs r1, #0 80005b2: 2011 movs r0, #17 80005b4: f001 fb13 bl 8001bde HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); 80005b8: 2011 movs r0, #17 80005ba: f001 fb2c bl 8001c16 /* DMA1_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0); 80005be: 2200 movs r2, #0 80005c0: 2100 movs r1, #0 80005c2: 202f movs r0, #47 @ 0x2f 80005c4: f001 fb0b bl 8001bde HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); 80005c8: 202f movs r0, #47 @ 0x2f 80005ca: f001 fb24 bl 8001c16 /* DMA2_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); 80005ce: 2200 movs r2, #0 80005d0: 2100 movs r1, #0 80005d2: 203a movs r0, #58 @ 0x3a 80005d4: f001 fb03 bl 8001bde HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); 80005d8: 203a movs r0, #58 @ 0x3a 80005da: f001 fb1c bl 8001c16 /* DMA2_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 80005de: 2200 movs r2, #0 80005e0: 2100 movs r1, #0 80005e2: 2046 movs r0, #70 @ 0x46 80005e4: f001 fafb bl 8001bde HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 80005e8: 2046 movs r0, #70 @ 0x46 80005ea: f001 fb14 bl 8001c16 } 80005ee: bf00 nop 80005f0: 3708 adds r7, #8 80005f2: 46bd mov sp, r7 80005f4: bd80 pop {r7, pc} 80005f6: bf00 nop 80005f8: 40023800 .word 0x40023800 080005fc : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 80005fc: b580 push {r7, lr} 80005fe: b08a sub sp, #40 @ 0x28 8000600: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000602: f107 0314 add.w r3, r7, #20 8000606: 2200 movs r2, #0 8000608: 601a str r2, [r3, #0] 800060a: 605a str r2, [r3, #4] 800060c: 609a str r2, [r3, #8] 800060e: 60da str r2, [r3, #12] 8000610: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8000612: 2300 movs r3, #0 8000614: 613b str r3, [r7, #16] 8000616: 4b45 ldr r3, [pc, #276] @ (800072c ) 8000618: 6b1b ldr r3, [r3, #48] @ 0x30 800061a: 4a44 ldr r2, [pc, #272] @ (800072c ) 800061c: f043 0380 orr.w r3, r3, #128 @ 0x80 8000620: 6313 str r3, [r2, #48] @ 0x30 8000622: 4b42 ldr r3, [pc, #264] @ (800072c ) 8000624: 6b1b ldr r3, [r3, #48] @ 0x30 8000626: f003 0380 and.w r3, r3, #128 @ 0x80 800062a: 613b str r3, [r7, #16] 800062c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800062e: 2300 movs r3, #0 8000630: 60fb str r3, [r7, #12] 8000632: 4b3e ldr r3, [pc, #248] @ (800072c ) 8000634: 6b1b ldr r3, [r3, #48] @ 0x30 8000636: 4a3d ldr r2, [pc, #244] @ (800072c ) 8000638: f043 0301 orr.w r3, r3, #1 800063c: 6313 str r3, [r2, #48] @ 0x30 800063e: 4b3b ldr r3, [pc, #236] @ (800072c ) 8000640: 6b1b ldr r3, [r3, #48] @ 0x30 8000642: f003 0301 and.w r3, r3, #1 8000646: 60fb str r3, [r7, #12] 8000648: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); 800064a: 2300 movs r3, #0 800064c: 60bb str r3, [r7, #8] 800064e: 4b37 ldr r3, [pc, #220] @ (800072c ) 8000650: 6b1b ldr r3, [r3, #48] @ 0x30 8000652: 4a36 ldr r2, [pc, #216] @ (800072c ) 8000654: f043 0304 orr.w r3, r3, #4 8000658: 6313 str r3, [r2, #48] @ 0x30 800065a: 4b34 ldr r3, [pc, #208] @ (800072c ) 800065c: 6b1b ldr r3, [r3, #48] @ 0x30 800065e: f003 0304 and.w r3, r3, #4 8000662: 60bb str r3, [r7, #8] 8000664: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000666: 2300 movs r3, #0 8000668: 607b str r3, [r7, #4] 800066a: 4b30 ldr r3, [pc, #192] @ (800072c ) 800066c: 6b1b ldr r3, [r3, #48] @ 0x30 800066e: 4a2f ldr r2, [pc, #188] @ (800072c ) 8000670: f043 0302 orr.w r3, r3, #2 8000674: 6313 str r3, [r2, #48] @ 0x30 8000676: 4b2d ldr r3, [pc, #180] @ (800072c ) 8000678: 6b1b ldr r3, [r3, #48] @ 0x30 800067a: f003 0302 and.w r3, r3, #2 800067e: 607b str r3, [r7, #4] 8000680: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000682: 2300 movs r3, #0 8000684: 603b str r3, [r7, #0] 8000686: 4b29 ldr r3, [pc, #164] @ (800072c ) 8000688: 6b1b ldr r3, [r3, #48] @ 0x30 800068a: 4a28 ldr r2, [pc, #160] @ (800072c ) 800068c: f043 0308 orr.w r3, r3, #8 8000690: 6313 str r3, [r2, #48] @ 0x30 8000692: 4b26 ldr r3, [pc, #152] @ (800072c ) 8000694: 6b1b ldr r3, [r3, #48] @ 0x30 8000696: f003 0308 and.w r3, r3, #8 800069a: 603b str r3, [r7, #0] 800069c: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET); 800069e: 2200 movs r2, #0 80006a0: f44f 7170 mov.w r1, #960 @ 0x3c0 80006a4: 4822 ldr r0, [pc, #136] @ (8000730 ) 80006a6: f002 f87f bl 80027a8 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); 80006aa: 2200 movs r2, #0 80006ac: f44f 7180 mov.w r1, #256 @ 0x100 80006b0: 4820 ldr r0, [pc, #128] @ (8000734 ) 80006b2: f002 f879 bl 80027a8 /*Configure GPIO pins : PC4 PC5 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80006b6: 2330 movs r3, #48 @ 0x30 80006b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006ba: 2300 movs r3, #0 80006bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006be: 2302 movs r3, #2 80006c0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006c2: f107 0314 add.w r3, r7, #20 80006c6: 4619 mov r1, r3 80006c8: 4819 ldr r0, [pc, #100] @ (8000730 ) 80006ca: f001 fec1 bl 8002450 /*Configure GPIO pins : PB0 PB1 PB2 PB10 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10; 80006ce: f240 4307 movw r3, #1031 @ 0x407 80006d2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006d4: 2300 movs r3, #0 80006d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006d8: 2302 movs r3, #2 80006da: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80006dc: f107 0314 add.w r3, r7, #20 80006e0: 4619 mov r1, r3 80006e2: 4815 ldr r0, [pc, #84] @ (8000738 ) 80006e4: f001 feb4 bl 8002450 /*Configure GPIO pins : PC6 PC7 PC8 PC9 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 80006e8: f44f 7370 mov.w r3, #960 @ 0x3c0 80006ec: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006ee: 2301 movs r3, #1 80006f0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80006f2: 2300 movs r3, #0 80006f4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80006f6: 2300 movs r3, #0 80006f8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006fa: f107 0314 add.w r3, r7, #20 80006fe: 4619 mov r1, r3 8000700: 480b ldr r0, [pc, #44] @ (8000730 ) 8000702: f001 fea5 bl 8002450 /*Configure GPIO pin : PA8 */ GPIO_InitStruct.Pin = GPIO_PIN_8; 8000706: f44f 7380 mov.w r3, #256 @ 0x100 800070a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800070c: 2301 movs r3, #1 800070e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000710: 2300 movs r3, #0 8000712: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000714: 2300 movs r3, #0 8000716: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000718: f107 0314 add.w r3, r7, #20 800071c: 4619 mov r1, r3 800071e: 4805 ldr r0, [pc, #20] @ (8000734 ) 8000720: f001 fe96 bl 8002450 } 8000724: bf00 nop 8000726: 3728 adds r7, #40 @ 0x28 8000728: 46bd mov sp, r7 800072a: bd80 pop {r7, pc} 800072c: 40023800 .word 0x40023800 8000730: 40020800 .word 0x40020800 8000734: 40020000 .word 0x40020000 8000738: 40020400 .word 0x40020400 0800073c : I2C_HandleTypeDef hi2c1; /* I2C1 init function */ void MX_I2C1_Init(void) { 800073c: b580 push {r7, lr} 800073e: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8000740: 4b12 ldr r3, [pc, #72] @ (800078c ) 8000742: 4a13 ldr r2, [pc, #76] @ (8000790 ) 8000744: 601a str r2, [r3, #0] hi2c1.Init.ClockSpeed = 100000; 8000746: 4b11 ldr r3, [pc, #68] @ (800078c ) 8000748: 4a12 ldr r2, [pc, #72] @ (8000794 ) 800074a: 605a str r2, [r3, #4] hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; 800074c: 4b0f ldr r3, [pc, #60] @ (800078c ) 800074e: 2200 movs r2, #0 8000750: 609a str r2, [r3, #8] hi2c1.Init.OwnAddress1 = 0; 8000752: 4b0e ldr r3, [pc, #56] @ (800078c ) 8000754: 2200 movs r2, #0 8000756: 60da str r2, [r3, #12] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8000758: 4b0c ldr r3, [pc, #48] @ (800078c ) 800075a: f44f 4280 mov.w r2, #16384 @ 0x4000 800075e: 611a str r2, [r3, #16] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000760: 4b0a ldr r3, [pc, #40] @ (800078c ) 8000762: 2200 movs r2, #0 8000764: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2 = 0; 8000766: 4b09 ldr r3, [pc, #36] @ (800078c ) 8000768: 2200 movs r2, #0 800076a: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 800076c: 4b07 ldr r3, [pc, #28] @ (800078c ) 800076e: 2200 movs r2, #0 8000770: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8000772: 4b06 ldr r3, [pc, #24] @ (800078c ) 8000774: 2200 movs r2, #0 8000776: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8000778: 4804 ldr r0, [pc, #16] @ (800078c ) 800077a: f002 f82f bl 80027dc 800077e: 4603 mov r3, r0 8000780: 2b00 cmp r3, #0 8000782: d001 beq.n 8000788 { Error_Handler(); 8000784: f000 fae8 bl 8000d58 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8000788: bf00 nop 800078a: bd80 pop {r7, pc} 800078c: 200001bc .word 0x200001bc 8000790: 40005400 .word 0x40005400 8000794: 000186a0 .word 0x000186a0 08000798 : void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) { 8000798: b580 push {r7, lr} 800079a: b08a sub sp, #40 @ 0x28 800079c: af00 add r7, sp, #0 800079e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007a0: f107 0314 add.w r3, r7, #20 80007a4: 2200 movs r2, #0 80007a6: 601a str r2, [r3, #0] 80007a8: 605a str r2, [r3, #4] 80007aa: 609a str r2, [r3, #8] 80007ac: 60da str r2, [r3, #12] 80007ae: 611a str r2, [r3, #16] if(i2cHandle->Instance==I2C1) 80007b0: 687b ldr r3, [r7, #4] 80007b2: 681b ldr r3, [r3, #0] 80007b4: 4a19 ldr r2, [pc, #100] @ (800081c ) 80007b6: 4293 cmp r3, r2 80007b8: d12b bne.n 8000812 { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80007ba: 2300 movs r3, #0 80007bc: 613b str r3, [r7, #16] 80007be: 4b18 ldr r3, [pc, #96] @ (8000820 ) 80007c0: 6b1b ldr r3, [r3, #48] @ 0x30 80007c2: 4a17 ldr r2, [pc, #92] @ (8000820 ) 80007c4: f043 0302 orr.w r3, r3, #2 80007c8: 6313 str r3, [r2, #48] @ 0x30 80007ca: 4b15 ldr r3, [pc, #84] @ (8000820 ) 80007cc: 6b1b ldr r3, [r3, #48] @ 0x30 80007ce: f003 0302 and.w r3, r3, #2 80007d2: 613b str r3, [r7, #16] 80007d4: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80007d6: 23c0 movs r3, #192 @ 0xc0 80007d8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80007da: 2312 movs r3, #18 80007dc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80007de: 2300 movs r3, #0 80007e0: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80007e2: 2303 movs r3, #3 80007e4: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 80007e6: 2304 movs r3, #4 80007e8: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80007ea: f107 0314 add.w r3, r7, #20 80007ee: 4619 mov r1, r3 80007f0: 480c ldr r0, [pc, #48] @ (8000824 ) 80007f2: f001 fe2d bl 8002450 /* I2C1 clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 80007f6: 2300 movs r3, #0 80007f8: 60fb str r3, [r7, #12] 80007fa: 4b09 ldr r3, [pc, #36] @ (8000820 ) 80007fc: 6c1b ldr r3, [r3, #64] @ 0x40 80007fe: 4a08 ldr r2, [pc, #32] @ (8000820 ) 8000800: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000804: 6413 str r3, [r2, #64] @ 0x40 8000806: 4b06 ldr r3, [pc, #24] @ (8000820 ) 8000808: 6c1b ldr r3, [r3, #64] @ 0x40 800080a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800080e: 60fb str r3, [r7, #12] 8000810: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8000812: bf00 nop 8000814: 3728 adds r7, #40 @ 0x28 8000816: 46bd mov sp, r7 8000818: bd80 pop {r7, pc} 800081a: bf00 nop 800081c: 40005400 .word 0x40005400 8000820: 40023800 .word 0x40023800 8000824: 40020400 .word 0x40020400 08000828
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000828: b580 push {r7, lr} 800082a: b084 sub sp, #16 800082c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800082e: f001 f865 bl 80018fc /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000832: f000 f897 bl 8000964 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000836: f7ff fee1 bl 80005fc MX_DMA_Init(); 800083a: f7ff fe79 bl 8000530 MX_TIM2_Init(); 800083e: f000 fb7d bl 8000f3c MX_TIM3_Init(); 8000842: f000 fbd3 bl 8000fec MX_UART4_Init(); 8000846: f000 fcc5 bl 80011d4 MX_UART5_Init(); 800084a: f000 fced bl 8001228 MX_USART1_UART_Init(); 800084e: f000 fd15 bl 800127c MX_USART2_UART_Init(); 8000852: f000 fd3d bl 80012d0 MX_I2C1_Init(); 8000856: f7ff ff71 bl 800073c MX_USB_DEVICE_Init(); 800085a: f009 fc73 bl 800a144 /* USER CODE BEGIN 2 */ //Enable UART RX DMA for all ports HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 800085e: 2210 movs r2, #16 8000860: 4934 ldr r1, [pc, #208] @ (8000934 ) 8000862: 4835 ldr r0, [pc, #212] @ (8000938 ) 8000864: f005 fa12 bl 8005c8c HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000868: 2210 movs r2, #16 800086a: 4934 ldr r1, [pc, #208] @ (800093c ) 800086c: 4834 ldr r0, [pc, #208] @ (8000940 ) 800086e: f005 fa0d bl 8005c8c HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000872: 2210 movs r2, #16 8000874: 4933 ldr r1, [pc, #204] @ (8000944 ) 8000876: 4834 ldr r0, [pc, #208] @ (8000948 ) 8000878: f005 fa08 bl 8005c8c HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 800087c: 2210 movs r2, #16 800087e: 4933 ldr r1, [pc, #204] @ (800094c ) 8000880: 4833 ldr r0, [pc, #204] @ (8000950 ) 8000882: f005 fa03 bl 8005c8c /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { switch (MODE){ 8000886: 4b33 ldr r3, [pc, #204] @ (8000954 ) 8000888: 781b ldrb r3, [r3, #0] 800088a: b2db uxtb r3, r3 800088c: 2b02 cmp r3, #2 800088e: d006 beq.n 800089e 8000890: 2b02 cmp r3, #2 8000892: dc4a bgt.n 800092a 8000894: 2b00 cmp r3, #0 8000896: d007 beq.n 80008a8 8000898: 2b01 cmp r3, #1 800089a: d03c beq.n 8000916 800089c: e045 b.n 800092a case MODE_ACTIVE: resetReport(); 800089e: f000 fa4b bl 8000d38 matrixScan(); 80008a2: f000 f9ef bl 8000c84 break; 80008a6: e040 b.n 800092a case MODE_INACTIVE: //If the module is connected through the USB then mode is mainboard if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){ 80008a8: 4b2b ldr r3, [pc, #172] @ (8000958 ) 80008aa: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80008ae: b2db uxtb r3, r3 80008b0: 2b03 cmp r3, #3 80008b2: d106 bne.n 80008c2 MODE = MODE_MAINBOARD; 80008b4: 4b27 ldr r3, [pc, #156] @ (8000954 ) 80008b6: 2201 movs r2, #1 80008b8: 701a strb r2, [r3, #0] DEPTH = 0; 80008ba: 4b28 ldr r3, [pc, #160] @ (800095c ) 80008bc: 2200 movs r2, #0 80008be: 801a strh r2, [r3, #0] HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); HAL_Delay(500); findBestParent(); //So true... } break; 80008c0: e033 b.n 800092a REQ.DEPTH = 0; 80008c2: 2300 movs r3, #0 80008c4: 803b strh r3, [r7, #0] REQ.TYPE = 0xFF; //Message code for request is 0xFF 80008c6: 23ff movs r3, #255 @ 0xff 80008c8: 807b strh r3, [r7, #2] memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS)); 80008ca: 463b mov r3, r7 80008cc: 3304 adds r3, #4 80008ce: 220c movs r2, #12 80008d0: 2100 movs r1, #0 80008d2: 4618 mov r0, r3 80008d4: f00a f8e4 bl 800aaa0 HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ)); 80008d8: 463b mov r3, r7 80008da: 2210 movs r2, #16 80008dc: 4619 mov r1, r3 80008de: 4816 ldr r0, [pc, #88] @ (8000938 ) 80008e0: f005 f958 bl 8005b94 HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ)); 80008e4: 463b mov r3, r7 80008e6: 2210 movs r2, #16 80008e8: 4619 mov r1, r3 80008ea: 4815 ldr r0, [pc, #84] @ (8000940 ) 80008ec: f005 f952 bl 8005b94 HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); 80008f0: 463b mov r3, r7 80008f2: 2210 movs r2, #16 80008f4: 4619 mov r1, r3 80008f6: 4814 ldr r0, [pc, #80] @ (8000948 ) 80008f8: f005 f94c bl 8005b94 HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); 80008fc: 463b mov r3, r7 80008fe: 2210 movs r2, #16 8000900: 4619 mov r1, r3 8000902: 4813 ldr r0, [pc, #76] @ (8000950 ) 8000904: f005 f946 bl 8005b94 HAL_Delay(500); 8000908: f44f 70fa mov.w r0, #500 @ 0x1f4 800090c: f001 f868 bl 80019e0 findBestParent(); //So true... 8000910: f000 f8f0 bl 8000af4 break; 8000914: e009 b.n 800092a case MODE_MAINBOARD: resetReport(); 8000916: f000 fa0f bl 8000d38 matrixScan(); 800091a: f000 f9b3 bl 8000c84 USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); 800091e: 220e movs r2, #14 8000920: 490f ldr r1, [pc, #60] @ (8000960 ) 8000922: 480d ldr r0, [pc, #52] @ (8000958 ) 8000924: f008 f842 bl 80089ac break; 8000928: bf00 nop } HAL_Delay(50); 800092a: 2032 movs r0, #50 @ 0x32 800092c: f001 f858 bl 80019e0 switch (MODE){ 8000930: e7a9 b.n 8000886 8000932: bf00 nop 8000934: 20000230 .word 0x20000230 8000938: 2000038c .word 0x2000038c 800093c: 20000240 .word 0x20000240 8000940: 200003d4 .word 0x200003d4 8000944: 20000250 .word 0x20000250 8000948: 200002fc .word 0x200002fc 800094c: 20000220 .word 0x20000220 8000950: 20000344 .word 0x20000344 8000954: 20000268 .word 0x20000268 8000958: 20000724 .word 0x20000724 800095c: 20000260 .word 0x20000260 8000960: 20000210 .word 0x20000210 08000964 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000964: b580 push {r7, lr} 8000966: b094 sub sp, #80 @ 0x50 8000968: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800096a: f107 031c add.w r3, r7, #28 800096e: 2234 movs r2, #52 @ 0x34 8000970: 2100 movs r1, #0 8000972: 4618 mov r0, r3 8000974: f00a f894 bl 800aaa0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000978: f107 0308 add.w r3, r7, #8 800097c: 2200 movs r2, #0 800097e: 601a str r2, [r3, #0] 8000980: 605a str r2, [r3, #4] 8000982: 609a str r2, [r3, #8] 8000984: 60da str r2, [r3, #12] 8000986: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 8000988: 2300 movs r3, #0 800098a: 607b str r3, [r7, #4] 800098c: 4b29 ldr r3, [pc, #164] @ (8000a34 ) 800098e: 6c1b ldr r3, [r3, #64] @ 0x40 8000990: 4a28 ldr r2, [pc, #160] @ (8000a34 ) 8000992: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000996: 6413 str r3, [r2, #64] @ 0x40 8000998: 4b26 ldr r3, [pc, #152] @ (8000a34 ) 800099a: 6c1b ldr r3, [r3, #64] @ 0x40 800099c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80009a0: 607b str r3, [r7, #4] 80009a2: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 80009a4: 2300 movs r3, #0 80009a6: 603b str r3, [r7, #0] 80009a8: 4b23 ldr r3, [pc, #140] @ (8000a38 ) 80009aa: 681b ldr r3, [r3, #0] 80009ac: f423 4340 bic.w r3, r3, #49152 @ 0xc000 80009b0: 4a21 ldr r2, [pc, #132] @ (8000a38 ) 80009b2: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80009b6: 6013 str r3, [r2, #0] 80009b8: 4b1f ldr r3, [pc, #124] @ (8000a38 ) 80009ba: 681b ldr r3, [r3, #0] 80009bc: f403 4340 and.w r3, r3, #49152 @ 0xc000 80009c0: 603b str r3, [r7, #0] 80009c2: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 80009c4: 2301 movs r3, #1 80009c6: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80009c8: f44f 3380 mov.w r3, #65536 @ 0x10000 80009cc: 623b str r3, [r7, #32] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80009ce: 2302 movs r3, #2 80009d0: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80009d2: f44f 0380 mov.w r3, #4194304 @ 0x400000 80009d6: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLM = 4; 80009d8: 2304 movs r3, #4 80009da: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLN = 96; 80009dc: 2360 movs r3, #96 @ 0x60 80009de: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 80009e0: 2302 movs r3, #2 80009e2: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLQ = 4; 80009e4: 2304 movs r3, #4 80009e6: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLR = 2; 80009e8: 2302 movs r3, #2 80009ea: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80009ec: f107 031c add.w r3, r7, #28 80009f0: 4618 mov r0, r3 80009f2: f004 f931 bl 8004c58 80009f6: 4603 mov r3, r0 80009f8: 2b00 cmp r3, #0 80009fa: d001 beq.n 8000a00 { Error_Handler(); 80009fc: f000 f9ac bl 8000d58 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000a00: 230f movs r3, #15 8000a02: 60bb str r3, [r7, #8] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000a04: 2302 movs r3, #2 8000a06: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; 8000a08: 2380 movs r3, #128 @ 0x80 8000a0a: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000a0c: f44f 5380 mov.w r3, #4096 @ 0x1000 8000a10: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000a12: 2300 movs r3, #0 8000a14: 61bb str r3, [r7, #24] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000a16: f107 0308 add.w r3, r7, #8 8000a1a: 2101 movs r1, #1 8000a1c: 4618 mov r0, r3 8000a1e: f003 faa7 bl 8003f70 8000a22: 4603 mov r3, r0 8000a24: 2b00 cmp r3, #0 8000a26: d001 beq.n 8000a2c { Error_Handler(); 8000a28: f000 f996 bl 8000d58 } } 8000a2c: bf00 nop 8000a2e: 3750 adds r7, #80 @ 0x50 8000a30: 46bd mov sp, r7 8000a32: bd80 pop {r7, pc} 8000a34: 40023800 .word 0x40023800 8000a38: 40007000 .word 0x40007000 08000a3c : /* USER CODE BEGIN 4 */ // UART Message Requests Goes Here void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8000a3c: b580 push {r7, lr} 8000a3e: b082 sub sp, #8 8000a40: af00 add r7, sp, #0 8000a42: 6078 str r0, [r7, #4] if (huart->Instance == USART1) { 8000a44: 687b ldr r3, [r7, #4] 8000a46: 681b ldr r3, [r3, #0] 8000a48: 4a1e ldr r2, [pc, #120] @ (8000ac4 ) 8000a4a: 4293 cmp r3, r2 8000a4c: d109 bne.n 8000a62 handleUARTMessages((uint8_t*)&RX1Msg, huart); 8000a4e: 6879 ldr r1, [r7, #4] 8000a50: 481d ldr r0, [pc, #116] @ (8000ac8 ) 8000a52: f000 f889 bl 8000b68 HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000a56: 2210 movs r2, #16 8000a58: 491b ldr r1, [pc, #108] @ (8000ac8 ) 8000a5a: 481c ldr r0, [pc, #112] @ (8000acc ) 8000a5c: f005 f916 bl 8005c8c } else if (huart->Instance == UART5) { handleUARTMessages((uint8_t*)&RX5Msg, huart); HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000a60: e02b b.n 8000aba else if (huart->Instance == USART2) { 8000a62: 687b ldr r3, [r7, #4] 8000a64: 681b ldr r3, [r3, #0] 8000a66: 4a1a ldr r2, [pc, #104] @ (8000ad0 ) 8000a68: 4293 cmp r3, r2 8000a6a: d109 bne.n 8000a80 handleUARTMessages((uint8_t*)&RX2Msg, huart); 8000a6c: 6879 ldr r1, [r7, #4] 8000a6e: 4819 ldr r0, [pc, #100] @ (8000ad4 ) 8000a70: f000 f87a bl 8000b68 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000a74: 2210 movs r2, #16 8000a76: 4917 ldr r1, [pc, #92] @ (8000ad4 ) 8000a78: 4817 ldr r0, [pc, #92] @ (8000ad8 ) 8000a7a: f005 f907 bl 8005c8c } 8000a7e: e01c b.n 8000aba else if (huart->Instance == UART4) { 8000a80: 687b ldr r3, [r7, #4] 8000a82: 681b ldr r3, [r3, #0] 8000a84: 4a15 ldr r2, [pc, #84] @ (8000adc ) 8000a86: 4293 cmp r3, r2 8000a88: d109 bne.n 8000a9e handleUARTMessages((uint8_t*)&RX4Msg, huart); 8000a8a: 6879 ldr r1, [r7, #4] 8000a8c: 4814 ldr r0, [pc, #80] @ (8000ae0 ) 8000a8e: f000 f86b bl 8000b68 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000a92: 2210 movs r2, #16 8000a94: 4912 ldr r1, [pc, #72] @ (8000ae0 ) 8000a96: 4813 ldr r0, [pc, #76] @ (8000ae4 ) 8000a98: f005 f8f8 bl 8005c8c } 8000a9c: e00d b.n 8000aba else if (huart->Instance == UART5) { 8000a9e: 687b ldr r3, [r7, #4] 8000aa0: 681b ldr r3, [r3, #0] 8000aa2: 4a11 ldr r2, [pc, #68] @ (8000ae8 ) 8000aa4: 4293 cmp r3, r2 8000aa6: d108 bne.n 8000aba handleUARTMessages((uint8_t*)&RX5Msg, huart); 8000aa8: 6879 ldr r1, [r7, #4] 8000aaa: 4810 ldr r0, [pc, #64] @ (8000aec ) 8000aac: f000 f85c bl 8000b68 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000ab0: 2210 movs r2, #16 8000ab2: 490e ldr r1, [pc, #56] @ (8000aec ) 8000ab4: 480e ldr r0, [pc, #56] @ (8000af0 ) 8000ab6: f005 f8e9 bl 8005c8c } 8000aba: bf00 nop 8000abc: 3708 adds r7, #8 8000abe: 46bd mov sp, r7 8000ac0: bd80 pop {r7, pc} 8000ac2: bf00 nop 8000ac4: 40011000 .word 0x40011000 8000ac8: 20000230 .word 0x20000230 8000acc: 2000038c .word 0x2000038c 8000ad0: 40004400 .word 0x40004400 8000ad4: 20000240 .word 0x20000240 8000ad8: 200003d4 .word 0x200003d4 8000adc: 40004c00 .word 0x40004c00 8000ae0: 20000250 .word 0x20000250 8000ae4: 200002fc .word 0x200002fc 8000ae8: 40005000 .word 0x40005000 8000aec: 20000220 .word 0x20000220 8000af0: 20000344 .word 0x20000344 08000af4 : void findBestParent(){ 8000af4: b480 push {r7} 8000af6: b085 sub sp, #20 8000af8: af00 add r7, sp, #0 //Find least depth parent uint16_t least_val = 0xFF; 8000afa: 23ff movs r3, #255 @ 0xff 8000afc: 81fb strh r3, [r7, #14] UART_HandleTypeDef* least_port = NULL; 8000afe: 2300 movs r3, #0 8000b00: 60bb str r3, [r7, #8] for(uint8_t i = 0; i < 4; i++){ 8000b02: 2300 movs r3, #0 8000b04: 71fb strb r3, [r7, #7] 8000b06: e013 b.n 8000b30 if(PORT_DEPTH[i]) 8000b0c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000b10: 89fa ldrh r2, [r7, #14] 8000b12: 429a cmp r2, r3 8000b14: d909 bls.n 8000b2a least_port = PORTS[i]; 8000b16: 79fb ldrb r3, [r7, #7] 8000b18: 4a10 ldr r2, [pc, #64] @ (8000b5c ) 8000b1a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000b1e: 60bb str r3, [r7, #8] least_val = PORT_DEPTH[i]; 8000b20: 79fb ldrb r3, [r7, #7] 8000b22: 4a0d ldr r2, [pc, #52] @ (8000b58 ) 8000b24: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000b28: 81fb strh r3, [r7, #14] for(uint8_t i = 0; i < 4; i++){ 8000b2a: 79fb ldrb r3, [r7, #7] 8000b2c: 3301 adds r3, #1 8000b2e: 71fb strb r3, [r7, #7] 8000b30: 79fb ldrb r3, [r7, #7] 8000b32: 2b03 cmp r3, #3 8000b34: d9e8 bls.n 8000b08 } } //Assign if valid if(least_val < 0xFF){ 8000b36: 89fb ldrh r3, [r7, #14] 8000b38: 2bfe cmp r3, #254 @ 0xfe 8000b3a: d807 bhi.n 8000b4c PARENT = least_port; 8000b3c: 4a08 ldr r2, [pc, #32] @ (8000b60 ) 8000b3e: 68bb ldr r3, [r7, #8] 8000b40: 6013 str r3, [r2, #0] DEPTH = least_val + 1; 8000b42: 89fb ldrh r3, [r7, #14] 8000b44: 3301 adds r3, #1 8000b46: b29a uxth r2, r3 8000b48: 4b06 ldr r3, [pc, #24] @ (8000b64 ) 8000b4a: 801a strh r2, [r3, #0] } } 8000b4c: bf00 nop 8000b4e: 3714 adds r7, #20 8000b50: 46bd mov sp, r7 8000b52: f85d 7b04 ldr.w r7, [sp], #4 8000b56: 4770 bx lr 8000b58: 20000078 .word 0x20000078 8000b5c: 20000080 .word 0x20000080 8000b60: 20000264 .word 0x20000264 8000b64: 20000260 .word 0x20000260 08000b68 : // Called when UART RX interrupt completes void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender) { 8000b68: b580 push {r7, lr} 8000b6a: b08a sub sp, #40 @ 0x28 8000b6c: af00 add r7, sp, #0 8000b6e: 6078 str r0, [r7, #4] 8000b70: 6039 str r1, [r7, #0] UARTMessage msg; UARTMessage reply; // Parse incoming message into struct memcpy(&msg, data, sizeof(UARTMessage)); 8000b72: f107 0318 add.w r3, r7, #24 8000b76: 2210 movs r2, #16 8000b78: 6879 ldr r1, [r7, #4] 8000b7a: 4618 mov r0, r3 8000b7c: f009 ffbc bl 800aaf8 switch(msg.TYPE) { 8000b80: 8b7b ldrh r3, [r7, #26] 8000b82: 2baa cmp r3, #170 @ 0xaa 8000b84: d002 beq.n 8000b8c 8000b86: 2bff cmp r3, #255 @ 0xff 8000b88: d020 beq.n 8000bcc HAL_UART_Transmit(sender, (uint8_t*)&reply, sizeof(reply), HAL_MAX_DELAY); break; } } 8000b8a: e036 b.n 8000bfa if(sender == &huart5) { 8000b8c: 683b ldr r3, [r7, #0] 8000b8e: 4a1d ldr r2, [pc, #116] @ (8000c04 ) 8000b90: 4293 cmp r3, r2 8000b92: d103 bne.n 8000b9c PORT_DEPTH[0] = msg.DEPTH; 8000b94: 8b3a ldrh r2, [r7, #24] 8000b96: 4b1c ldr r3, [pc, #112] @ (8000c08 ) 8000b98: 801a strh r2, [r3, #0] break; 8000b9a: e02d b.n 8000bf8 } else if(sender == &huart1) { 8000b9c: 683b ldr r3, [r7, #0] 8000b9e: 4a1b ldr r2, [pc, #108] @ (8000c0c ) 8000ba0: 4293 cmp r3, r2 8000ba2: d103 bne.n 8000bac PORT_DEPTH[1] = msg.DEPTH; 8000ba4: 8b3a ldrh r2, [r7, #24] 8000ba6: 4b18 ldr r3, [pc, #96] @ (8000c08 ) 8000ba8: 805a strh r2, [r3, #2] break; 8000baa: e025 b.n 8000bf8 } else if(sender == &huart2) { 8000bac: 683b ldr r3, [r7, #0] 8000bae: 4a18 ldr r2, [pc, #96] @ (8000c10 ) 8000bb0: 4293 cmp r3, r2 8000bb2: d103 bne.n 8000bbc PORT_DEPTH[2] = msg.DEPTH; 8000bb4: 8b3a ldrh r2, [r7, #24] 8000bb6: 4b14 ldr r3, [pc, #80] @ (8000c08 ) 8000bb8: 809a strh r2, [r3, #4] break; 8000bba: e01d b.n 8000bf8 } else if(sender == &huart4) { 8000bbc: 683b ldr r3, [r7, #0] 8000bbe: 4a15 ldr r2, [pc, #84] @ (8000c14 ) 8000bc0: 4293 cmp r3, r2 8000bc2: d119 bne.n 8000bf8 PORT_DEPTH[3] = msg.DEPTH; 8000bc4: 8b3a ldrh r2, [r7, #24] 8000bc6: 4b10 ldr r3, [pc, #64] @ (8000c08 ) 8000bc8: 80da strh r2, [r3, #6] break; 8000bca: e015 b.n 8000bf8 reply.TYPE = 0xAA; 8000bcc: 23aa movs r3, #170 @ 0xaa 8000bce: 817b strh r3, [r7, #10] reply.DEPTH = DEPTH; // use your local DEPTH 8000bd0: 4b11 ldr r3, [pc, #68] @ (8000c18 ) 8000bd2: 881b ldrh r3, [r3, #0] 8000bd4: 813b strh r3, [r7, #8] memset(reply.KEYPRESS, 0, sizeof(reply.KEYPRESS)); 8000bd6: f107 0308 add.w r3, r7, #8 8000bda: 3304 adds r3, #4 8000bdc: 220c movs r2, #12 8000bde: 2100 movs r1, #0 8000be0: 4618 mov r0, r3 8000be2: f009 ff5d bl 800aaa0 HAL_UART_Transmit(sender, (uint8_t*)&reply, sizeof(reply), HAL_MAX_DELAY); 8000be6: f107 0108 add.w r1, r7, #8 8000bea: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8000bee: 2210 movs r2, #16 8000bf0: 6838 ldr r0, [r7, #0] 8000bf2: f004 ff43 bl 8005a7c break; 8000bf6: e000 b.n 8000bfa break; 8000bf8: bf00 nop } 8000bfa: bf00 nop 8000bfc: 3728 adds r7, #40 @ 0x28 8000bfe: 46bd mov sp, r7 8000c00: bd80 pop {r7, pc} 8000c02: bf00 nop 8000c04: 20000344 .word 0x20000344 8000c08: 20000078 .word 0x20000078 8000c0c: 2000038c .word 0x2000038c 8000c10: 200003d4 .word 0x200003d4 8000c14: 200002fc .word 0x200002fc 8000c18: 20000260 .word 0x20000260 08000c1c : void addUSBReport(uint8_t usageID){ 8000c1c: b480 push {r7} 8000c1e: b085 sub sp, #20 8000c20: af00 add r7, sp, #0 8000c22: 4603 mov r3, r0 8000c24: 71fb strb r3, [r7, #7] if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8000c26: 79fb ldrb r3, [r7, #7] 8000c28: 2b03 cmp r3, #3 8000c2a: d922 bls.n 8000c72 8000c2c: 79fb ldrb r3, [r7, #7] 8000c2e: 2b73 cmp r3, #115 @ 0x73 8000c30: d81f bhi.n 8000c72 uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit 8000c32: 79fb ldrb r3, [r7, #7] 8000c34: b29b uxth r3, r3 8000c36: 3b04 subs r3, #4 8000c38: 81fb strh r3, [r7, #14] uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array 8000c3a: 89fb ldrh r3, [r7, #14] 8000c3c: 08db lsrs r3, r3, #3 8000c3e: b29b uxth r3, r3 8000c40: 737b strb r3, [r7, #13] uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset 8000c42: 89fb ldrh r3, [r7, #14] 8000c44: b2db uxtb r3, r3 8000c46: f003 0307 and.w r3, r3, #7 8000c4a: 733b strb r3, [r7, #12] REPORT.KEYPRESS[byte_index] |= (1 << bit_offset); 8000c4c: 7b7b ldrb r3, [r7, #13] 8000c4e: 4a0c ldr r2, [pc, #48] @ (8000c80 ) 8000c50: 4413 add r3, r2 8000c52: 789b ldrb r3, [r3, #2] 8000c54: b25a sxtb r2, r3 8000c56: 7b3b ldrb r3, [r7, #12] 8000c58: 2101 movs r1, #1 8000c5a: fa01 f303 lsl.w r3, r1, r3 8000c5e: b25b sxtb r3, r3 8000c60: 4313 orrs r3, r2 8000c62: b25a sxtb r2, r3 8000c64: 7b7b ldrb r3, [r7, #13] 8000c66: b2d1 uxtb r1, r2 8000c68: 4a05 ldr r2, [pc, #20] @ (8000c80 ) 8000c6a: 4413 add r3, r2 8000c6c: 460a mov r2, r1 8000c6e: 709a strb r2, [r3, #2] 8000c70: e000 b.n 8000c74 if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8000c72: bf00 nop } 8000c74: 3714 adds r7, #20 8000c76: 46bd mov sp, r7 8000c78: f85d 7b04 ldr.w r7, [sp], #4 8000c7c: 4770 bx lr 8000c7e: bf00 nop 8000c80: 20000210 .word 0x20000210 08000c84 : void matrixScan(void){ 8000c84: b580 push {r7, lr} 8000c86: b082 sub sp, #8 8000c88: af00 add r7, sp, #0 for (uint8_t col = 0; col < COL; col++){ 8000c8a: 2300 movs r3, #0 8000c8c: 71fb strb r3, [r7, #7] 8000c8e: e044 b.n 8000d1a HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET); 8000c90: 79fb ldrb r3, [r7, #7] 8000c92: 4a26 ldr r2, [pc, #152] @ (8000d2c ) 8000c94: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000c98: 79fb ldrb r3, [r7, #7] 8000c9a: 4a24 ldr r2, [pc, #144] @ (8000d2c ) 8000c9c: 00db lsls r3, r3, #3 8000c9e: 4413 add r3, r2 8000ca0: 889b ldrh r3, [r3, #4] 8000ca2: 2201 movs r2, #1 8000ca4: 4619 mov r1, r3 8000ca6: f001 fd7f bl 80027a8 HAL_Delay(1); 8000caa: 2001 movs r0, #1 8000cac: f000 fe98 bl 80019e0 for(uint8_t row = 0; row < ROW; row++){ 8000cb0: 2300 movs r3, #0 8000cb2: 71bb strb r3, [r7, #6] 8000cb4: e01e b.n 8000cf4 if(HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN)){ 8000cb6: 79bb ldrb r3, [r7, #6] 8000cb8: 4a1d ldr r2, [pc, #116] @ (8000d30 ) 8000cba: f852 2033 ldr.w r2, [r2, r3, lsl #3] 8000cbe: 79bb ldrb r3, [r7, #6] 8000cc0: 491b ldr r1, [pc, #108] @ (8000d30 ) 8000cc2: 00db lsls r3, r3, #3 8000cc4: 440b add r3, r1 8000cc6: 889b ldrh r3, [r3, #4] 8000cc8: 4619 mov r1, r3 8000cca: 4610 mov r0, r2 8000ccc: f001 fd54 bl 8002778 8000cd0: 4603 mov r3, r0 8000cd2: 2b00 cmp r3, #0 8000cd4: d00b beq.n 8000cee addUSBReport(KEYCODES[row][col]); 8000cd6: 79ba ldrb r2, [r7, #6] 8000cd8: 79f9 ldrb r1, [r7, #7] 8000cda: 4816 ldr r0, [pc, #88] @ (8000d34 ) 8000cdc: 4613 mov r3, r2 8000cde: 009b lsls r3, r3, #2 8000ce0: 4413 add r3, r2 8000ce2: 4403 add r3, r0 8000ce4: 440b add r3, r1 8000ce6: 781b ldrb r3, [r3, #0] 8000ce8: 4618 mov r0, r3 8000cea: f7ff ff97 bl 8000c1c for(uint8_t row = 0; row < ROW; row++){ 8000cee: 79bb ldrb r3, [r7, #6] 8000cf0: 3301 adds r3, #1 8000cf2: 71bb strb r3, [r7, #6] 8000cf4: 79bb ldrb r3, [r7, #6] 8000cf6: 2b05 cmp r3, #5 8000cf8: d9dd bls.n 8000cb6 } } HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET); 8000cfa: 79fb ldrb r3, [r7, #7] 8000cfc: 4a0b ldr r2, [pc, #44] @ (8000d2c ) 8000cfe: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000d02: 79fb ldrb r3, [r7, #7] 8000d04: 4a09 ldr r2, [pc, #36] @ (8000d2c ) 8000d06: 00db lsls r3, r3, #3 8000d08: 4413 add r3, r2 8000d0a: 889b ldrh r3, [r3, #4] 8000d0c: 2200 movs r2, #0 8000d0e: 4619 mov r1, r3 8000d10: f001 fd4a bl 80027a8 for (uint8_t col = 0; col < COL; col++){ 8000d14: 79fb ldrb r3, [r7, #7] 8000d16: 3301 adds r3, #1 8000d18: 71fb strb r3, [r7, #7] 8000d1a: 79fb ldrb r3, [r7, #7] 8000d1c: 2b04 cmp r3, #4 8000d1e: d9b7 bls.n 8000c90 } } 8000d20: bf00 nop 8000d22: bf00 nop 8000d24: 3708 adds r7, #8 8000d26: 46bd mov sp, r7 8000d28: bd80 pop {r7, pc} 8000d2a: bf00 nop 8000d2c: 20000030 .word 0x20000030 8000d30: 20000000 .word 0x20000000 8000d34: 20000058 .word 0x20000058 08000d38 : void resetReport(void){ 8000d38: b580 push {r7, lr} 8000d3a: af00 add r7, sp, #0 REPORT.MODIFIER = 0; 8000d3c: 4b04 ldr r3, [pc, #16] @ (8000d50 ) 8000d3e: 2200 movs r2, #0 8000d40: 701a strb r2, [r3, #0] memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS)); 8000d42: 220c movs r2, #12 8000d44: 2100 movs r1, #0 8000d46: 4803 ldr r0, [pc, #12] @ (8000d54 ) 8000d48: f009 feaa bl 800aaa0 } 8000d4c: bf00 nop 8000d4e: bd80 pop {r7, pc} 8000d50: 20000210 .word 0x20000210 8000d54: 20000212 .word 0x20000212 08000d58 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000d58: b480 push {r7} 8000d5a: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000d5c: b672 cpsid i } 8000d5e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000d60: bf00 nop 8000d62: e7fd b.n 8000d60 08000d64 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000d64: b480 push {r7} 8000d66: b083 sub sp, #12 8000d68: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000d6a: 2300 movs r3, #0 8000d6c: 607b str r3, [r7, #4] 8000d6e: 4b10 ldr r3, [pc, #64] @ (8000db0 ) 8000d70: 6c5b ldr r3, [r3, #68] @ 0x44 8000d72: 4a0f ldr r2, [pc, #60] @ (8000db0 ) 8000d74: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000d78: 6453 str r3, [r2, #68] @ 0x44 8000d7a: 4b0d ldr r3, [pc, #52] @ (8000db0 ) 8000d7c: 6c5b ldr r3, [r3, #68] @ 0x44 8000d7e: f403 4380 and.w r3, r3, #16384 @ 0x4000 8000d82: 607b str r3, [r7, #4] 8000d84: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000d86: 2300 movs r3, #0 8000d88: 603b str r3, [r7, #0] 8000d8a: 4b09 ldr r3, [pc, #36] @ (8000db0 ) 8000d8c: 6c1b ldr r3, [r3, #64] @ 0x40 8000d8e: 4a08 ldr r2, [pc, #32] @ (8000db0 ) 8000d90: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000d94: 6413 str r3, [r2, #64] @ 0x40 8000d96: 4b06 ldr r3, [pc, #24] @ (8000db0 ) 8000d98: 6c1b ldr r3, [r3, #64] @ 0x40 8000d9a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000d9e: 603b str r3, [r7, #0] 8000da0: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000da2: bf00 nop 8000da4: 370c adds r7, #12 8000da6: 46bd mov sp, r7 8000da8: f85d 7b04 ldr.w r7, [sp], #4 8000dac: 4770 bx lr 8000dae: bf00 nop 8000db0: 40023800 .word 0x40023800 08000db4 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000db4: b480 push {r7} 8000db6: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000db8: bf00 nop 8000dba: e7fd b.n 8000db8 08000dbc : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000dbc: b480 push {r7} 8000dbe: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000dc0: bf00 nop 8000dc2: e7fd b.n 8000dc0 08000dc4 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000dc4: b480 push {r7} 8000dc6: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000dc8: bf00 nop 8000dca: e7fd b.n 8000dc8 08000dcc : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000dcc: b480 push {r7} 8000dce: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000dd0: bf00 nop 8000dd2: e7fd b.n 8000dd0 08000dd4 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000dd4: b480 push {r7} 8000dd6: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000dd8: bf00 nop 8000dda: e7fd b.n 8000dd8 08000ddc : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000ddc: b480 push {r7} 8000dde: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000de0: bf00 nop 8000de2: 46bd mov sp, r7 8000de4: f85d 7b04 ldr.w r7, [sp], #4 8000de8: 4770 bx lr 08000dea : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000dea: b480 push {r7} 8000dec: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000dee: bf00 nop 8000df0: 46bd mov sp, r7 8000df2: f85d 7b04 ldr.w r7, [sp], #4 8000df6: 4770 bx lr 08000df8 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000df8: b480 push {r7} 8000dfa: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000dfc: bf00 nop 8000dfe: 46bd mov sp, r7 8000e00: f85d 7b04 ldr.w r7, [sp], #4 8000e04: 4770 bx lr 08000e06 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000e06: b580 push {r7, lr} 8000e08: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000e0a: f000 fdc9 bl 80019a0 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000e0e: bf00 nop 8000e10: bd80 pop {r7, pc} ... 08000e14 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8000e14: b580 push {r7, lr} 8000e16: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_rx); 8000e18: 4802 ldr r0, [pc, #8] @ (8000e24 ) 8000e1a: f001 f8af bl 8001f7c /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 8000e1e: bf00 nop 8000e20: bd80 pop {r7, pc} 8000e22: bf00 nop 8000e24: 200004dc .word 0x200004dc 08000e28 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 8000e28: b580 push {r7, lr} 8000e2a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_rx); 8000e2c: 4802 ldr r0, [pc, #8] @ (8000e38 ) 8000e2e: f001 f8a5 bl 8001f7c /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 8000e32: bf00 nop 8000e34: bd80 pop {r7, pc} 8000e36: bf00 nop 8000e38: 2000041c .word 0x2000041c 08000e3c : /** * @brief This function handles DMA1 stream4 global interrupt. */ void DMA1_Stream4_IRQHandler(void) { 8000e3c: b580 push {r7, lr} 8000e3e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ /* USER CODE END DMA1_Stream4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_tx); 8000e40: 4802 ldr r0, [pc, #8] @ (8000e4c ) 8000e42: f001 f89b bl 8001f7c /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ /* USER CODE END DMA1_Stream4_IRQn 1 */ } 8000e46: bf00 nop 8000e48: bd80 pop {r7, pc} 8000e4a: bf00 nop 8000e4c: 2000047c .word 0x2000047c 08000e50 : /** * @brief This function handles DMA1 stream5 global interrupt. */ void DMA1_Stream5_IRQHandler(void) { 8000e50: b580 push {r7, lr} 8000e52: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ /* USER CODE END DMA1_Stream5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 8000e54: 4802 ldr r0, [pc, #8] @ (8000e60 ) 8000e56: f001 f891 bl 8001f7c /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ /* USER CODE END DMA1_Stream5_IRQn 1 */ } 8000e5a: bf00 nop 8000e5c: bd80 pop {r7, pc} 8000e5e: bf00 nop 8000e60: 2000065c .word 0x2000065c 08000e64 : /** * @brief This function handles DMA1 stream6 global interrupt. */ void DMA1_Stream6_IRQHandler(void) { 8000e64: b580 push {r7, lr} 8000e66: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ /* USER CODE END DMA1_Stream6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 8000e68: 4802 ldr r0, [pc, #8] @ (8000e74 ) 8000e6a: f001 f887 bl 8001f7c /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ /* USER CODE END DMA1_Stream6_IRQn 1 */ } 8000e6e: bf00 nop 8000e70: bd80 pop {r7, pc} 8000e72: bf00 nop 8000e74: 200006bc .word 0x200006bc 08000e78 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8000e78: b580 push {r7, lr} 8000e7a: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8000e7c: 4802 ldr r0, [pc, #8] @ (8000e88 ) 8000e7e: f004 ff2b bl 8005cd8 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8000e82: bf00 nop 8000e84: bd80 pop {r7, pc} 8000e86: bf00 nop 8000e88: 2000038c .word 0x2000038c 08000e8c : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 8000e8c: b580 push {r7, lr} 8000e8e: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 8000e90: 4802 ldr r0, [pc, #8] @ (8000e9c ) 8000e92: f004 ff21 bl 8005cd8 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 8000e96: bf00 nop 8000e98: bd80 pop {r7, pc} 8000e9a: bf00 nop 8000e9c: 200003d4 .word 0x200003d4 08000ea0 : /** * @brief This function handles DMA1 stream7 global interrupt. */ void DMA1_Stream7_IRQHandler(void) { 8000ea0: b580 push {r7, lr} 8000ea2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ /* USER CODE END DMA1_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_tx); 8000ea4: 4802 ldr r0, [pc, #8] @ (8000eb0 ) 8000ea6: f001 f869 bl 8001f7c /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ /* USER CODE END DMA1_Stream7_IRQn 1 */ } 8000eaa: bf00 nop 8000eac: bd80 pop {r7, pc} 8000eae: bf00 nop 8000eb0: 2000053c .word 0x2000053c 08000eb4 : /** * @brief This function handles UART4 global interrupt. */ void UART4_IRQHandler(void) { 8000eb4: b580 push {r7, lr} 8000eb6: af00 add r7, sp, #0 /* USER CODE BEGIN UART4_IRQn 0 */ /* USER CODE END UART4_IRQn 0 */ HAL_UART_IRQHandler(&huart4); 8000eb8: 4802 ldr r0, [pc, #8] @ (8000ec4 ) 8000eba: f004 ff0d bl 8005cd8 /* USER CODE BEGIN UART4_IRQn 1 */ /* USER CODE END UART4_IRQn 1 */ } 8000ebe: bf00 nop 8000ec0: bd80 pop {r7, pc} 8000ec2: bf00 nop 8000ec4: 200002fc .word 0x200002fc 08000ec8 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 8000ec8: b580 push {r7, lr} 8000eca: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 8000ecc: 4802 ldr r0, [pc, #8] @ (8000ed8 ) 8000ece: f004 ff03 bl 8005cd8 /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 8000ed2: bf00 nop 8000ed4: bd80 pop {r7, pc} 8000ed6: bf00 nop 8000ed8: 20000344 .word 0x20000344 08000edc : /** * @brief This function handles DMA2 stream2 global interrupt. */ void DMA2_Stream2_IRQHandler(void) { 8000edc: b580 push {r7, lr} 8000ede: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ /* USER CODE END DMA2_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_rx); 8000ee0: 4802 ldr r0, [pc, #8] @ (8000eec ) 8000ee2: f001 f84b bl 8001f7c /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ /* USER CODE END DMA2_Stream2_IRQn 1 */ } 8000ee6: bf00 nop 8000ee8: bd80 pop {r7, pc} 8000eea: bf00 nop 8000eec: 2000059c .word 0x2000059c 08000ef0 : /** * @brief This function handles USB On The Go FS global interrupt. */ void OTG_FS_IRQHandler(void) { 8000ef0: b580 push {r7, lr} 8000ef2: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_FS_IRQn 0 */ /* USER CODE END OTG_FS_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); 8000ef4: 4802 ldr r0, [pc, #8] @ (8000f00 ) 8000ef6: f001 ff00 bl 8002cfa /* USER CODE BEGIN OTG_FS_IRQn 1 */ /* USER CODE END OTG_FS_IRQn 1 */ } 8000efa: bf00 nop 8000efc: bd80 pop {r7, pc} 8000efe: bf00 nop 8000f00: 20000c00 .word 0x20000c00 08000f04 : /** * @brief This function handles DMA2 stream7 global interrupt. */ void DMA2_Stream7_IRQHandler(void) { 8000f04: b580 push {r7, lr} 8000f06: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ /* USER CODE END DMA2_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 8000f08: 4802 ldr r0, [pc, #8] @ (8000f14 ) 8000f0a: f001 f837 bl 8001f7c /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ /* USER CODE END DMA2_Stream7_IRQn 1 */ } 8000f0e: bf00 nop 8000f10: bd80 pop {r7, pc} 8000f12: bf00 nop 8000f14: 200005fc .word 0x200005fc 08000f18 : * configuration. * @param None * @retval None */ void SystemInit(void) { 8000f18: b480 push {r7} 8000f1a: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8000f1c: 4b06 ldr r3, [pc, #24] @ (8000f38 ) 8000f1e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8000f22: 4a05 ldr r2, [pc, #20] @ (8000f38 ) 8000f24: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8000f28: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8000f2c: bf00 nop 8000f2e: 46bd mov sp, r7 8000f30: f85d 7b04 ldr.w r7, [sp], #4 8000f34: 4770 bx lr 8000f36: bf00 nop 8000f38: e000ed00 .word 0xe000ed00 08000f3c : TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; /* TIM2 init function */ void MX_TIM2_Init(void) { 8000f3c: b580 push {r7, lr} 8000f3e: b08a sub sp, #40 @ 0x28 8000f40: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000f42: f107 0320 add.w r3, r7, #32 8000f46: 2200 movs r2, #0 8000f48: 601a str r2, [r3, #0] 8000f4a: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 8000f4c: 1d3b adds r3, r7, #4 8000f4e: 2200 movs r2, #0 8000f50: 601a str r2, [r3, #0] 8000f52: 605a str r2, [r3, #4] 8000f54: 609a str r2, [r3, #8] 8000f56: 60da str r2, [r3, #12] 8000f58: 611a str r2, [r3, #16] 8000f5a: 615a str r2, [r3, #20] 8000f5c: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 8000f5e: 4b22 ldr r3, [pc, #136] @ (8000fe8 ) 8000f60: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 8000f64: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 8000f66: 4b20 ldr r3, [pc, #128] @ (8000fe8 ) 8000f68: 2200 movs r2, #0 8000f6a: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8000f6c: 4b1e ldr r3, [pc, #120] @ (8000fe8 ) 8000f6e: 2200 movs r2, #0 8000f70: 609a str r2, [r3, #8] htim2.Init.Period = 4294967295; 8000f72: 4b1d ldr r3, [pc, #116] @ (8000fe8 ) 8000f74: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000f78: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000f7a: 4b1b ldr r3, [pc, #108] @ (8000fe8 ) 8000f7c: 2200 movs r2, #0 8000f7e: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000f80: 4b19 ldr r3, [pc, #100] @ (8000fe8 ) 8000f82: 2200 movs r2, #0 8000f84: 619a str r2, [r3, #24] if (HAL_TIM_OC_Init(&htim2) != HAL_OK) 8000f86: 4818 ldr r0, [pc, #96] @ (8000fe8 ) 8000f88: f004 f904 bl 8005194 8000f8c: 4603 mov r3, r0 8000f8e: 2b00 cmp r3, #0 8000f90: d001 beq.n 8000f96 { Error_Handler(); 8000f92: f7ff fee1 bl 8000d58 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000f96: 2300 movs r3, #0 8000f98: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000f9a: 2300 movs r3, #0 8000f9c: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8000f9e: f107 0320 add.w r3, r7, #32 8000fa2: 4619 mov r1, r3 8000fa4: 4810 ldr r0, [pc, #64] @ (8000fe8 ) 8000fa6: f004 fc9d bl 80058e4 8000faa: 4603 mov r3, r0 8000fac: 2b00 cmp r3, #0 8000fae: d001 beq.n 8000fb4 { Error_Handler(); 8000fb0: f7ff fed2 bl 8000d58 } sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE; 8000fb4: 2350 movs r3, #80 @ 0x50 8000fb6: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 8000fb8: 2300 movs r3, #0 8000fba: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8000fbc: 2300 movs r3, #0 8000fbe: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8000fc0: 2300 movs r3, #0 8000fc2: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8000fc4: 1d3b adds r3, r7, #4 8000fc6: 2200 movs r2, #0 8000fc8: 4619 mov r1, r3 8000fca: 4807 ldr r0, [pc, #28] @ (8000fe8 ) 8000fcc: f004 f9d8 bl 8005380 8000fd0: 4603 mov r3, r0 8000fd2: 2b00 cmp r3, #0 8000fd4: d001 beq.n 8000fda { Error_Handler(); 8000fd6: f7ff febf bl 8000d58 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 8000fda: 4803 ldr r0, [pc, #12] @ (8000fe8 ) 8000fdc: f000 f8c2 bl 8001164 } 8000fe0: bf00 nop 8000fe2: 3728 adds r7, #40 @ 0x28 8000fe4: 46bd mov sp, r7 8000fe6: bd80 pop {r7, pc} 8000fe8: 2000026c .word 0x2000026c 08000fec : /* TIM3 init function */ void MX_TIM3_Init(void) { 8000fec: b580 push {r7, lr} 8000fee: b08c sub sp, #48 @ 0x30 8000ff0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_Encoder_InitTypeDef sConfig = {0}; 8000ff2: f107 030c add.w r3, r7, #12 8000ff6: 2224 movs r2, #36 @ 0x24 8000ff8: 2100 movs r1, #0 8000ffa: 4618 mov r0, r3 8000ffc: f009 fd50 bl 800aaa0 TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001000: 1d3b adds r3, r7, #4 8001002: 2200 movs r2, #0 8001004: 601a str r2, [r3, #0] 8001006: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8001008: 4b20 ldr r3, [pc, #128] @ (800108c ) 800100a: 4a21 ldr r2, [pc, #132] @ (8001090 ) 800100c: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800100e: 4b1f ldr r3, [pc, #124] @ (800108c ) 8001010: 2200 movs r2, #0 8001012: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8001014: 4b1d ldr r3, [pc, #116] @ (800108c ) 8001016: 2200 movs r2, #0 8001018: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800101a: 4b1c ldr r3, [pc, #112] @ (800108c ) 800101c: f64f 72ff movw r2, #65535 @ 0xffff 8001020: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8001022: 4b1a ldr r3, [pc, #104] @ (800108c ) 8001024: 2200 movs r2, #0 8001026: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001028: 4b18 ldr r3, [pc, #96] @ (800108c ) 800102a: 2200 movs r2, #0 800102c: 619a str r2, [r3, #24] sConfig.EncoderMode = TIM_ENCODERMODE_TI1; 800102e: 2301 movs r3, #1 8001030: 60fb str r3, [r7, #12] sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; 8001032: 2300 movs r3, #0 8001034: 613b str r3, [r7, #16] sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; 8001036: 2301 movs r3, #1 8001038: 617b str r3, [r7, #20] sConfig.IC1Prescaler = TIM_ICPSC_DIV1; 800103a: 2300 movs r3, #0 800103c: 61bb str r3, [r7, #24] sConfig.IC1Filter = 0; 800103e: 2300 movs r3, #0 8001040: 61fb str r3, [r7, #28] sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; 8001042: 2300 movs r3, #0 8001044: 623b str r3, [r7, #32] sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; 8001046: 2301 movs r3, #1 8001048: 627b str r3, [r7, #36] @ 0x24 sConfig.IC2Prescaler = TIM_ICPSC_DIV1; 800104a: 2300 movs r3, #0 800104c: 62bb str r3, [r7, #40] @ 0x28 sConfig.IC2Filter = 0; 800104e: 2300 movs r3, #0 8001050: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) 8001052: f107 030c add.w r3, r7, #12 8001056: 4619 mov r1, r3 8001058: 480c ldr r0, [pc, #48] @ (800108c ) 800105a: f004 f8ea bl 8005232 800105e: 4603 mov r3, r0 8001060: 2b00 cmp r3, #0 8001062: d001 beq.n 8001068 { Error_Handler(); 8001064: f7ff fe78 bl 8000d58 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001068: 2300 movs r3, #0 800106a: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800106c: 2300 movs r3, #0 800106e: 60bb str r3, [r7, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8001070: 1d3b adds r3, r7, #4 8001072: 4619 mov r1, r3 8001074: 4805 ldr r0, [pc, #20] @ (800108c ) 8001076: f004 fc35 bl 80058e4 800107a: 4603 mov r3, r0 800107c: 2b00 cmp r3, #0 800107e: d001 beq.n 8001084 { Error_Handler(); 8001080: f7ff fe6a bl 8000d58 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8001084: bf00 nop 8001086: 3730 adds r7, #48 @ 0x30 8001088: 46bd mov sp, r7 800108a: bd80 pop {r7, pc} 800108c: 200002b4 .word 0x200002b4 8001090: 40000400 .word 0x40000400 08001094 : void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle) { 8001094: b480 push {r7} 8001096: b085 sub sp, #20 8001098: af00 add r7, sp, #0 800109a: 6078 str r0, [r7, #4] if(tim_ocHandle->Instance==TIM2) 800109c: 687b ldr r3, [r7, #4] 800109e: 681b ldr r3, [r3, #0] 80010a0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80010a4: d10d bne.n 80010c2 { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* TIM2 clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 80010a6: 2300 movs r3, #0 80010a8: 60fb str r3, [r7, #12] 80010aa: 4b09 ldr r3, [pc, #36] @ (80010d0 ) 80010ac: 6c1b ldr r3, [r3, #64] @ 0x40 80010ae: 4a08 ldr r2, [pc, #32] @ (80010d0 ) 80010b0: f043 0301 orr.w r3, r3, #1 80010b4: 6413 str r3, [r2, #64] @ 0x40 80010b6: 4b06 ldr r3, [pc, #24] @ (80010d0 ) 80010b8: 6c1b ldr r3, [r3, #64] @ 0x40 80010ba: f003 0301 and.w r3, r3, #1 80010be: 60fb str r3, [r7, #12] 80010c0: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } } 80010c2: bf00 nop 80010c4: 3714 adds r7, #20 80010c6: 46bd mov sp, r7 80010c8: f85d 7b04 ldr.w r7, [sp], #4 80010cc: 4770 bx lr 80010ce: bf00 nop 80010d0: 40023800 .word 0x40023800 080010d4 : void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) { 80010d4: b580 push {r7, lr} 80010d6: b08a sub sp, #40 @ 0x28 80010d8: af00 add r7, sp, #0 80010da: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80010dc: f107 0314 add.w r3, r7, #20 80010e0: 2200 movs r2, #0 80010e2: 601a str r2, [r3, #0] 80010e4: 605a str r2, [r3, #4] 80010e6: 609a str r2, [r3, #8] 80010e8: 60da str r2, [r3, #12] 80010ea: 611a str r2, [r3, #16] if(tim_encoderHandle->Instance==TIM3) 80010ec: 687b ldr r3, [r7, #4] 80010ee: 681b ldr r3, [r3, #0] 80010f0: 4a19 ldr r2, [pc, #100] @ (8001158 ) 80010f2: 4293 cmp r3, r2 80010f4: d12b bne.n 800114e { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 80010f6: 2300 movs r3, #0 80010f8: 613b str r3, [r7, #16] 80010fa: 4b18 ldr r3, [pc, #96] @ (800115c ) 80010fc: 6c1b ldr r3, [r3, #64] @ 0x40 80010fe: 4a17 ldr r2, [pc, #92] @ (800115c ) 8001100: f043 0302 orr.w r3, r3, #2 8001104: 6413 str r3, [r2, #64] @ 0x40 8001106: 4b15 ldr r3, [pc, #84] @ (800115c ) 8001108: 6c1b ldr r3, [r3, #64] @ 0x40 800110a: f003 0302 and.w r3, r3, #2 800110e: 613b str r3, [r7, #16] 8001110: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001112: 2300 movs r3, #0 8001114: 60fb str r3, [r7, #12] 8001116: 4b11 ldr r3, [pc, #68] @ (800115c ) 8001118: 6b1b ldr r3, [r3, #48] @ 0x30 800111a: 4a10 ldr r2, [pc, #64] @ (800115c ) 800111c: f043 0301 orr.w r3, r3, #1 8001120: 6313 str r3, [r2, #48] @ 0x30 8001122: 4b0e ldr r3, [pc, #56] @ (800115c ) 8001124: 6b1b ldr r3, [r3, #48] @ 0x30 8001126: f003 0301 and.w r3, r3, #1 800112a: 60fb str r3, [r7, #12] 800112c: 68fb ldr r3, [r7, #12] /**TIM3 GPIO Configuration PA6 ------> TIM3_CH1 PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 800112e: 23c0 movs r3, #192 @ 0xc0 8001130: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001132: 2302 movs r3, #2 8001134: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001136: 2300 movs r3, #0 8001138: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800113a: 2300 movs r3, #0 800113c: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 800113e: 2302 movs r3, #2 8001140: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001142: f107 0314 add.w r3, r7, #20 8001146: 4619 mov r1, r3 8001148: 4805 ldr r0, [pc, #20] @ (8001160 ) 800114a: f001 f981 bl 8002450 /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 800114e: bf00 nop 8001150: 3728 adds r7, #40 @ 0x28 8001152: 46bd mov sp, r7 8001154: bd80 pop {r7, pc} 8001156: bf00 nop 8001158: 40000400 .word 0x40000400 800115c: 40023800 .word 0x40023800 8001160: 40020000 .word 0x40020000 08001164 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 8001164: b580 push {r7, lr} 8001166: b088 sub sp, #32 8001168: af00 add r7, sp, #0 800116a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800116c: f107 030c add.w r3, r7, #12 8001170: 2200 movs r2, #0 8001172: 601a str r2, [r3, #0] 8001174: 605a str r2, [r3, #4] 8001176: 609a str r2, [r3, #8] 8001178: 60da str r2, [r3, #12] 800117a: 611a str r2, [r3, #16] if(timHandle->Instance==TIM2) 800117c: 687b ldr r3, [r7, #4] 800117e: 681b ldr r3, [r3, #0] 8001180: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001184: d11d bne.n 80011c2 { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8001186: 2300 movs r3, #0 8001188: 60bb str r3, [r7, #8] 800118a: 4b10 ldr r3, [pc, #64] @ (80011cc ) 800118c: 6b1b ldr r3, [r3, #48] @ 0x30 800118e: 4a0f ldr r2, [pc, #60] @ (80011cc ) 8001190: f043 0301 orr.w r3, r3, #1 8001194: 6313 str r3, [r2, #48] @ 0x30 8001196: 4b0d ldr r3, [pc, #52] @ (80011cc ) 8001198: 6b1b ldr r3, [r3, #48] @ 0x30 800119a: f003 0301 and.w r3, r3, #1 800119e: 60bb str r3, [r7, #8] 80011a0: 68bb ldr r3, [r7, #8] /**TIM2 GPIO Configuration PA5 ------> TIM2_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_5; 80011a2: 2320 movs r3, #32 80011a4: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80011a6: 2302 movs r3, #2 80011a8: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 80011aa: 2300 movs r3, #0 80011ac: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80011ae: 2300 movs r3, #0 80011b0: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 80011b2: 2301 movs r3, #1 80011b4: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80011b6: f107 030c add.w r3, r7, #12 80011ba: 4619 mov r1, r3 80011bc: 4804 ldr r0, [pc, #16] @ (80011d0 ) 80011be: f001 f947 bl 8002450 /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 80011c2: bf00 nop 80011c4: 3720 adds r7, #32 80011c6: 46bd mov sp, r7 80011c8: bd80 pop {r7, pc} 80011ca: bf00 nop 80011cc: 40023800 .word 0x40023800 80011d0: 40020000 .word 0x40020000 080011d4 : DMA_HandleTypeDef hdma_usart2_rx; DMA_HandleTypeDef hdma_usart2_tx; /* UART4 init function */ void MX_UART4_Init(void) { 80011d4: b580 push {r7, lr} 80011d6: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; 80011d8: 4b11 ldr r3, [pc, #68] @ (8001220 ) 80011da: 4a12 ldr r2, [pc, #72] @ (8001224 ) 80011dc: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; 80011de: 4b10 ldr r3, [pc, #64] @ (8001220 ) 80011e0: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80011e4: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; 80011e6: 4b0e ldr r3, [pc, #56] @ (8001220 ) 80011e8: 2200 movs r2, #0 80011ea: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; 80011ec: 4b0c ldr r3, [pc, #48] @ (8001220 ) 80011ee: 2200 movs r2, #0 80011f0: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; 80011f2: 4b0b ldr r3, [pc, #44] @ (8001220 ) 80011f4: 2200 movs r2, #0 80011f6: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; 80011f8: 4b09 ldr r3, [pc, #36] @ (8001220 ) 80011fa: 220c movs r2, #12 80011fc: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80011fe: 4b08 ldr r3, [pc, #32] @ (8001220 ) 8001200: 2200 movs r2, #0 8001202: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; 8001204: 4b06 ldr r3, [pc, #24] @ (8001220 ) 8001206: 2200 movs r2, #0 8001208: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart4) != HAL_OK) 800120a: 4805 ldr r0, [pc, #20] @ (8001220 ) 800120c: f004 fbe6 bl 80059dc 8001210: 4603 mov r3, r0 8001212: 2b00 cmp r3, #0 8001214: d001 beq.n 800121a { Error_Handler(); 8001216: f7ff fd9f bl 8000d58 } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } 800121a: bf00 nop 800121c: bd80 pop {r7, pc} 800121e: bf00 nop 8001220: 200002fc .word 0x200002fc 8001224: 40004c00 .word 0x40004c00 08001228 : /* UART5 init function */ void MX_UART5_Init(void) { 8001228: b580 push {r7, lr} 800122a: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 800122c: 4b11 ldr r3, [pc, #68] @ (8001274 ) 800122e: 4a12 ldr r2, [pc, #72] @ (8001278 ) 8001230: 601a str r2, [r3, #0] huart5.Init.BaudRate = 115200; 8001232: 4b10 ldr r3, [pc, #64] @ (8001274 ) 8001234: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001238: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 800123a: 4b0e ldr r3, [pc, #56] @ (8001274 ) 800123c: 2200 movs r2, #0 800123e: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 8001240: 4b0c ldr r3, [pc, #48] @ (8001274 ) 8001242: 2200 movs r2, #0 8001244: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 8001246: 4b0b ldr r3, [pc, #44] @ (8001274 ) 8001248: 2200 movs r2, #0 800124a: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 800124c: 4b09 ldr r3, [pc, #36] @ (8001274 ) 800124e: 220c movs r2, #12 8001250: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001252: 4b08 ldr r3, [pc, #32] @ (8001274 ) 8001254: 2200 movs r2, #0 8001256: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 8001258: 4b06 ldr r3, [pc, #24] @ (8001274 ) 800125a: 2200 movs r2, #0 800125c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800125e: 4805 ldr r0, [pc, #20] @ (8001274 ) 8001260: f004 fbbc bl 80059dc 8001264: 4603 mov r3, r0 8001266: 2b00 cmp r3, #0 8001268: d001 beq.n 800126e { Error_Handler(); 800126a: f7ff fd75 bl 8000d58 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800126e: bf00 nop 8001270: bd80 pop {r7, pc} 8001272: bf00 nop 8001274: 20000344 .word 0x20000344 8001278: 40005000 .word 0x40005000 0800127c : /* USART1 init function */ void MX_USART1_UART_Init(void) { 800127c: b580 push {r7, lr} 800127e: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8001280: 4b11 ldr r3, [pc, #68] @ (80012c8 ) 8001282: 4a12 ldr r2, [pc, #72] @ (80012cc ) 8001284: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8001286: 4b10 ldr r3, [pc, #64] @ (80012c8 ) 8001288: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800128c: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800128e: 4b0e ldr r3, [pc, #56] @ (80012c8 ) 8001290: 2200 movs r2, #0 8001292: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8001294: 4b0c ldr r3, [pc, #48] @ (80012c8 ) 8001296: 2200 movs r2, #0 8001298: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800129a: 4b0b ldr r3, [pc, #44] @ (80012c8 ) 800129c: 2200 movs r2, #0 800129e: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80012a0: 4b09 ldr r3, [pc, #36] @ (80012c8 ) 80012a2: 220c movs r2, #12 80012a4: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80012a6: 4b08 ldr r3, [pc, #32] @ (80012c8 ) 80012a8: 2200 movs r2, #0 80012aa: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80012ac: 4b06 ldr r3, [pc, #24] @ (80012c8 ) 80012ae: 2200 movs r2, #0 80012b0: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 80012b2: 4805 ldr r0, [pc, #20] @ (80012c8 ) 80012b4: f004 fb92 bl 80059dc 80012b8: 4603 mov r3, r0 80012ba: 2b00 cmp r3, #0 80012bc: d001 beq.n 80012c2 { Error_Handler(); 80012be: f7ff fd4b bl 8000d58 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 80012c2: bf00 nop 80012c4: bd80 pop {r7, pc} 80012c6: bf00 nop 80012c8: 2000038c .word 0x2000038c 80012cc: 40011000 .word 0x40011000 080012d0 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 80012d0: b580 push {r7, lr} 80012d2: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 80012d4: 4b11 ldr r3, [pc, #68] @ (800131c ) 80012d6: 4a12 ldr r2, [pc, #72] @ (8001320 ) 80012d8: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 80012da: 4b10 ldr r3, [pc, #64] @ (800131c ) 80012dc: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80012e0: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 80012e2: 4b0e ldr r3, [pc, #56] @ (800131c ) 80012e4: 2200 movs r2, #0 80012e6: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 80012e8: 4b0c ldr r3, [pc, #48] @ (800131c ) 80012ea: 2200 movs r2, #0 80012ec: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 80012ee: 4b0b ldr r3, [pc, #44] @ (800131c ) 80012f0: 2200 movs r2, #0 80012f2: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 80012f4: 4b09 ldr r3, [pc, #36] @ (800131c ) 80012f6: 220c movs r2, #12 80012f8: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80012fa: 4b08 ldr r3, [pc, #32] @ (800131c ) 80012fc: 2200 movs r2, #0 80012fe: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8001300: 4b06 ldr r3, [pc, #24] @ (800131c ) 8001302: 2200 movs r2, #0 8001304: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 8001306: 4805 ldr r0, [pc, #20] @ (800131c ) 8001308: f004 fb68 bl 80059dc 800130c: 4603 mov r3, r0 800130e: 2b00 cmp r3, #0 8001310: d001 beq.n 8001316 { Error_Handler(); 8001312: f7ff fd21 bl 8000d58 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8001316: bf00 nop 8001318: bd80 pop {r7, pc} 800131a: bf00 nop 800131c: 200003d4 .word 0x200003d4 8001320: 40004400 .word 0x40004400 08001324 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8001324: b580 push {r7, lr} 8001326: b090 sub sp, #64 @ 0x40 8001328: af00 add r7, sp, #0 800132a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800132c: f107 032c add.w r3, r7, #44 @ 0x2c 8001330: 2200 movs r2, #0 8001332: 601a str r2, [r3, #0] 8001334: 605a str r2, [r3, #4] 8001336: 609a str r2, [r3, #8] 8001338: 60da str r2, [r3, #12] 800133a: 611a str r2, [r3, #16] if(uartHandle->Instance==UART4) 800133c: 687b ldr r3, [r7, #4] 800133e: 681b ldr r3, [r3, #0] 8001340: 4a4a ldr r2, [pc, #296] @ (800146c ) 8001342: 4293 cmp r3, r2 8001344: f040 80a0 bne.w 8001488 { /* USER CODE BEGIN UART4_MspInit 0 */ /* USER CODE END UART4_MspInit 0 */ /* UART4 clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); 8001348: 2300 movs r3, #0 800134a: 62bb str r3, [r7, #40] @ 0x28 800134c: 4b48 ldr r3, [pc, #288] @ (8001470 ) 800134e: 6c1b ldr r3, [r3, #64] @ 0x40 8001350: 4a47 ldr r2, [pc, #284] @ (8001470 ) 8001352: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8001356: 6413 str r3, [r2, #64] @ 0x40 8001358: 4b45 ldr r3, [pc, #276] @ (8001470 ) 800135a: 6c1b ldr r3, [r3, #64] @ 0x40 800135c: f403 2300 and.w r3, r3, #524288 @ 0x80000 8001360: 62bb str r3, [r7, #40] @ 0x28 8001362: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOA_CLK_ENABLE(); 8001364: 2300 movs r3, #0 8001366: 627b str r3, [r7, #36] @ 0x24 8001368: 4b41 ldr r3, [pc, #260] @ (8001470 ) 800136a: 6b1b ldr r3, [r3, #48] @ 0x30 800136c: 4a40 ldr r2, [pc, #256] @ (8001470 ) 800136e: f043 0301 orr.w r3, r3, #1 8001372: 6313 str r3, [r2, #48] @ 0x30 8001374: 4b3e ldr r3, [pc, #248] @ (8001470 ) 8001376: 6b1b ldr r3, [r3, #48] @ 0x30 8001378: f003 0301 and.w r3, r3, #1 800137c: 627b str r3, [r7, #36] @ 0x24 800137e: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART4 GPIO Configuration PA0-WKUP ------> UART4_TX PA1 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8001380: 2303 movs r3, #3 8001382: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001384: 2302 movs r3, #2 8001386: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001388: 2300 movs r3, #0 800138a: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800138c: 2303 movs r3, #3 800138e: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 8001390: 2308 movs r3, #8 8001392: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001394: f107 032c add.w r3, r7, #44 @ 0x2c 8001398: 4619 mov r1, r3 800139a: 4836 ldr r0, [pc, #216] @ (8001474 ) 800139c: f001 f858 bl 8002450 /* UART4 DMA Init */ /* UART4_RX Init */ hdma_uart4_rx.Instance = DMA1_Stream2; 80013a0: 4b35 ldr r3, [pc, #212] @ (8001478 ) 80013a2: 4a36 ldr r2, [pc, #216] @ (800147c ) 80013a4: 601a str r2, [r3, #0] hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4; 80013a6: 4b34 ldr r3, [pc, #208] @ (8001478 ) 80013a8: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80013ac: 605a str r2, [r3, #4] hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80013ae: 4b32 ldr r3, [pc, #200] @ (8001478 ) 80013b0: 2200 movs r2, #0 80013b2: 609a str r2, [r3, #8] hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE; 80013b4: 4b30 ldr r3, [pc, #192] @ (8001478 ) 80013b6: 2200 movs r2, #0 80013b8: 60da str r2, [r3, #12] hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE; 80013ba: 4b2f ldr r3, [pc, #188] @ (8001478 ) 80013bc: f44f 6280 mov.w r2, #1024 @ 0x400 80013c0: 611a str r2, [r3, #16] hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80013c2: 4b2d ldr r3, [pc, #180] @ (8001478 ) 80013c4: 2200 movs r2, #0 80013c6: 615a str r2, [r3, #20] hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80013c8: 4b2b ldr r3, [pc, #172] @ (8001478 ) 80013ca: 2200 movs r2, #0 80013cc: 619a str r2, [r3, #24] hdma_uart4_rx.Init.Mode = DMA_NORMAL; 80013ce: 4b2a ldr r3, [pc, #168] @ (8001478 ) 80013d0: 2200 movs r2, #0 80013d2: 61da str r2, [r3, #28] hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW; 80013d4: 4b28 ldr r3, [pc, #160] @ (8001478 ) 80013d6: 2200 movs r2, #0 80013d8: 621a str r2, [r3, #32] hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80013da: 4b27 ldr r3, [pc, #156] @ (8001478 ) 80013dc: 2200 movs r2, #0 80013de: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK) 80013e0: 4825 ldr r0, [pc, #148] @ (8001478 ) 80013e2: f000 fc33 bl 8001c4c 80013e6: 4603 mov r3, r0 80013e8: 2b00 cmp r3, #0 80013ea: d001 beq.n 80013f0 { Error_Handler(); 80013ec: f7ff fcb4 bl 8000d58 } __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx); 80013f0: 687b ldr r3, [r7, #4] 80013f2: 4a21 ldr r2, [pc, #132] @ (8001478 ) 80013f4: 63da str r2, [r3, #60] @ 0x3c 80013f6: 4a20 ldr r2, [pc, #128] @ (8001478 ) 80013f8: 687b ldr r3, [r7, #4] 80013fa: 6393 str r3, [r2, #56] @ 0x38 /* UART4_TX Init */ hdma_uart4_tx.Instance = DMA1_Stream4; 80013fc: 4b20 ldr r3, [pc, #128] @ (8001480 ) 80013fe: 4a21 ldr r2, [pc, #132] @ (8001484 ) 8001400: 601a str r2, [r3, #0] hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4; 8001402: 4b1f ldr r3, [pc, #124] @ (8001480 ) 8001404: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001408: 605a str r2, [r3, #4] hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800140a: 4b1d ldr r3, [pc, #116] @ (8001480 ) 800140c: 2240 movs r2, #64 @ 0x40 800140e: 609a str r2, [r3, #8] hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001410: 4b1b ldr r3, [pc, #108] @ (8001480 ) 8001412: 2200 movs r2, #0 8001414: 60da str r2, [r3, #12] hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE; 8001416: 4b1a ldr r3, [pc, #104] @ (8001480 ) 8001418: f44f 6280 mov.w r2, #1024 @ 0x400 800141c: 611a str r2, [r3, #16] hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800141e: 4b18 ldr r3, [pc, #96] @ (8001480 ) 8001420: 2200 movs r2, #0 8001422: 615a str r2, [r3, #20] hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001424: 4b16 ldr r3, [pc, #88] @ (8001480 ) 8001426: 2200 movs r2, #0 8001428: 619a str r2, [r3, #24] hdma_uart4_tx.Init.Mode = DMA_NORMAL; 800142a: 4b15 ldr r3, [pc, #84] @ (8001480 ) 800142c: 2200 movs r2, #0 800142e: 61da str r2, [r3, #28] hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW; 8001430: 4b13 ldr r3, [pc, #76] @ (8001480 ) 8001432: 2200 movs r2, #0 8001434: 621a str r2, [r3, #32] hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001436: 4b12 ldr r3, [pc, #72] @ (8001480 ) 8001438: 2200 movs r2, #0 800143a: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK) 800143c: 4810 ldr r0, [pc, #64] @ (8001480 ) 800143e: f000 fc05 bl 8001c4c 8001442: 4603 mov r3, r0 8001444: 2b00 cmp r3, #0 8001446: d001 beq.n 800144c { Error_Handler(); 8001448: f7ff fc86 bl 8000d58 } __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); 800144c: 687b ldr r3, [r7, #4] 800144e: 4a0c ldr r2, [pc, #48] @ (8001480 ) 8001450: 639a str r2, [r3, #56] @ 0x38 8001452: 4a0b ldr r2, [pc, #44] @ (8001480 ) 8001454: 687b ldr r3, [r7, #4] 8001456: 6393 str r3, [r2, #56] @ 0x38 /* UART4 interrupt Init */ HAL_NVIC_SetPriority(UART4_IRQn, 0, 0); 8001458: 2200 movs r2, #0 800145a: 2100 movs r1, #0 800145c: 2034 movs r0, #52 @ 0x34 800145e: f000 fbbe bl 8001bde HAL_NVIC_EnableIRQ(UART4_IRQn); 8001462: 2034 movs r0, #52 @ 0x34 8001464: f000 fbd7 bl 8001c16 HAL_NVIC_EnableIRQ(USART2_IRQn); /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8001468: e202 b.n 8001870 800146a: bf00 nop 800146c: 40004c00 .word 0x40004c00 8001470: 40023800 .word 0x40023800 8001474: 40020000 .word 0x40020000 8001478: 2000041c .word 0x2000041c 800147c: 40026040 .word 0x40026040 8001480: 2000047c .word 0x2000047c 8001484: 40026070 .word 0x40026070 else if(uartHandle->Instance==UART5) 8001488: 687b ldr r3, [r7, #4] 800148a: 681b ldr r3, [r3, #0] 800148c: 4a59 ldr r2, [pc, #356] @ (80015f4 ) 800148e: 4293 cmp r3, r2 8001490: f040 80c0 bne.w 8001614 __HAL_RCC_UART5_CLK_ENABLE(); 8001494: 2300 movs r3, #0 8001496: 623b str r3, [r7, #32] 8001498: 4b57 ldr r3, [pc, #348] @ (80015f8 ) 800149a: 6c1b ldr r3, [r3, #64] @ 0x40 800149c: 4a56 ldr r2, [pc, #344] @ (80015f8 ) 800149e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80014a2: 6413 str r3, [r2, #64] @ 0x40 80014a4: 4b54 ldr r3, [pc, #336] @ (80015f8 ) 80014a6: 6c1b ldr r3, [r3, #64] @ 0x40 80014a8: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80014ac: 623b str r3, [r7, #32] 80014ae: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOC_CLK_ENABLE(); 80014b0: 2300 movs r3, #0 80014b2: 61fb str r3, [r7, #28] 80014b4: 4b50 ldr r3, [pc, #320] @ (80015f8 ) 80014b6: 6b1b ldr r3, [r3, #48] @ 0x30 80014b8: 4a4f ldr r2, [pc, #316] @ (80015f8 ) 80014ba: f043 0304 orr.w r3, r3, #4 80014be: 6313 str r3, [r2, #48] @ 0x30 80014c0: 4b4d ldr r3, [pc, #308] @ (80015f8 ) 80014c2: 6b1b ldr r3, [r3, #48] @ 0x30 80014c4: f003 0304 and.w r3, r3, #4 80014c8: 61fb str r3, [r7, #28] 80014ca: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOD_CLK_ENABLE(); 80014cc: 2300 movs r3, #0 80014ce: 61bb str r3, [r7, #24] 80014d0: 4b49 ldr r3, [pc, #292] @ (80015f8 ) 80014d2: 6b1b ldr r3, [r3, #48] @ 0x30 80014d4: 4a48 ldr r2, [pc, #288] @ (80015f8 ) 80014d6: f043 0308 orr.w r3, r3, #8 80014da: 6313 str r3, [r2, #48] @ 0x30 80014dc: 4b46 ldr r3, [pc, #280] @ (80015f8 ) 80014de: 6b1b ldr r3, [r3, #48] @ 0x30 80014e0: f003 0308 and.w r3, r3, #8 80014e4: 61bb str r3, [r7, #24] 80014e6: 69bb ldr r3, [r7, #24] GPIO_InitStruct.Pin = GPIO_PIN_12; 80014e8: f44f 5380 mov.w r3, #4096 @ 0x1000 80014ec: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80014ee: 2302 movs r3, #2 80014f0: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80014f2: 2300 movs r3, #0 80014f4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80014f6: 2303 movs r3, #3 80014f8: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 80014fa: 2308 movs r3, #8 80014fc: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80014fe: f107 032c add.w r3, r7, #44 @ 0x2c 8001502: 4619 mov r1, r3 8001504: 483d ldr r0, [pc, #244] @ (80015fc ) 8001506: f000 ffa3 bl 8002450 GPIO_InitStruct.Pin = GPIO_PIN_2; 800150a: 2304 movs r3, #4 800150c: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800150e: 2302 movs r3, #2 8001510: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001512: 2300 movs r3, #0 8001514: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001516: 2303 movs r3, #3 8001518: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 800151a: 2308 movs r3, #8 800151c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800151e: f107 032c add.w r3, r7, #44 @ 0x2c 8001522: 4619 mov r1, r3 8001524: 4836 ldr r0, [pc, #216] @ (8001600 ) 8001526: f000 ff93 bl 8002450 hdma_uart5_rx.Instance = DMA1_Stream0; 800152a: 4b36 ldr r3, [pc, #216] @ (8001604 ) 800152c: 4a36 ldr r2, [pc, #216] @ (8001608 ) 800152e: 601a str r2, [r3, #0] hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4; 8001530: 4b34 ldr r3, [pc, #208] @ (8001604 ) 8001532: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001536: 605a str r2, [r3, #4] hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001538: 4b32 ldr r3, [pc, #200] @ (8001604 ) 800153a: 2200 movs r2, #0 800153c: 609a str r2, [r3, #8] hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800153e: 4b31 ldr r3, [pc, #196] @ (8001604 ) 8001540: 2200 movs r2, #0 8001542: 60da str r2, [r3, #12] hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE; 8001544: 4b2f ldr r3, [pc, #188] @ (8001604 ) 8001546: f44f 6280 mov.w r2, #1024 @ 0x400 800154a: 611a str r2, [r3, #16] hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800154c: 4b2d ldr r3, [pc, #180] @ (8001604 ) 800154e: 2200 movs r2, #0 8001550: 615a str r2, [r3, #20] hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001552: 4b2c ldr r3, [pc, #176] @ (8001604 ) 8001554: 2200 movs r2, #0 8001556: 619a str r2, [r3, #24] hdma_uart5_rx.Init.Mode = DMA_NORMAL; 8001558: 4b2a ldr r3, [pc, #168] @ (8001604 ) 800155a: 2200 movs r2, #0 800155c: 61da str r2, [r3, #28] hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; 800155e: 4b29 ldr r3, [pc, #164] @ (8001604 ) 8001560: 2200 movs r2, #0 8001562: 621a str r2, [r3, #32] hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001564: 4b27 ldr r3, [pc, #156] @ (8001604 ) 8001566: 2200 movs r2, #0 8001568: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) 800156a: 4826 ldr r0, [pc, #152] @ (8001604 ) 800156c: f000 fb6e bl 8001c4c 8001570: 4603 mov r3, r0 8001572: 2b00 cmp r3, #0 8001574: d001 beq.n 800157a Error_Handler(); 8001576: f7ff fbef bl 8000d58 __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx); 800157a: 687b ldr r3, [r7, #4] 800157c: 4a21 ldr r2, [pc, #132] @ (8001604 ) 800157e: 63da str r2, [r3, #60] @ 0x3c 8001580: 4a20 ldr r2, [pc, #128] @ (8001604 ) 8001582: 687b ldr r3, [r7, #4] 8001584: 6393 str r3, [r2, #56] @ 0x38 hdma_uart5_tx.Instance = DMA1_Stream7; 8001586: 4b21 ldr r3, [pc, #132] @ (800160c ) 8001588: 4a21 ldr r2, [pc, #132] @ (8001610 ) 800158a: 601a str r2, [r3, #0] hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4; 800158c: 4b1f ldr r3, [pc, #124] @ (800160c ) 800158e: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001592: 605a str r2, [r3, #4] hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001594: 4b1d ldr r3, [pc, #116] @ (800160c ) 8001596: 2240 movs r2, #64 @ 0x40 8001598: 609a str r2, [r3, #8] hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800159a: 4b1c ldr r3, [pc, #112] @ (800160c ) 800159c: 2200 movs r2, #0 800159e: 60da str r2, [r3, #12] hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE; 80015a0: 4b1a ldr r3, [pc, #104] @ (800160c ) 80015a2: f44f 6280 mov.w r2, #1024 @ 0x400 80015a6: 611a str r2, [r3, #16] hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80015a8: 4b18 ldr r3, [pc, #96] @ (800160c ) 80015aa: 2200 movs r2, #0 80015ac: 615a str r2, [r3, #20] hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80015ae: 4b17 ldr r3, [pc, #92] @ (800160c ) 80015b0: 2200 movs r2, #0 80015b2: 619a str r2, [r3, #24] hdma_uart5_tx.Init.Mode = DMA_NORMAL; 80015b4: 4b15 ldr r3, [pc, #84] @ (800160c ) 80015b6: 2200 movs r2, #0 80015b8: 61da str r2, [r3, #28] hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; 80015ba: 4b14 ldr r3, [pc, #80] @ (800160c ) 80015bc: 2200 movs r2, #0 80015be: 621a str r2, [r3, #32] hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80015c0: 4b12 ldr r3, [pc, #72] @ (800160c ) 80015c2: 2200 movs r2, #0 80015c4: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) 80015c6: 4811 ldr r0, [pc, #68] @ (800160c ) 80015c8: f000 fb40 bl 8001c4c 80015cc: 4603 mov r3, r0 80015ce: 2b00 cmp r3, #0 80015d0: d001 beq.n 80015d6 Error_Handler(); 80015d2: f7ff fbc1 bl 8000d58 __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); 80015d6: 687b ldr r3, [r7, #4] 80015d8: 4a0c ldr r2, [pc, #48] @ (800160c ) 80015da: 639a str r2, [r3, #56] @ 0x38 80015dc: 4a0b ldr r2, [pc, #44] @ (800160c ) 80015de: 687b ldr r3, [r7, #4] 80015e0: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(UART5_IRQn, 0, 0); 80015e2: 2200 movs r2, #0 80015e4: 2100 movs r1, #0 80015e6: 2035 movs r0, #53 @ 0x35 80015e8: f000 faf9 bl 8001bde HAL_NVIC_EnableIRQ(UART5_IRQn); 80015ec: 2035 movs r0, #53 @ 0x35 80015ee: f000 fb12 bl 8001c16 } 80015f2: e13d b.n 8001870 80015f4: 40005000 .word 0x40005000 80015f8: 40023800 .word 0x40023800 80015fc: 40020800 .word 0x40020800 8001600: 40020c00 .word 0x40020c00 8001604: 200004dc .word 0x200004dc 8001608: 40026010 .word 0x40026010 800160c: 2000053c .word 0x2000053c 8001610: 400260b8 .word 0x400260b8 else if(uartHandle->Instance==USART1) 8001614: 687b ldr r3, [r7, #4] 8001616: 681b ldr r3, [r3, #0] 8001618: 4a97 ldr r2, [pc, #604] @ (8001878 ) 800161a: 4293 cmp r3, r2 800161c: f040 8092 bne.w 8001744 __HAL_RCC_USART1_CLK_ENABLE(); 8001620: 2300 movs r3, #0 8001622: 617b str r3, [r7, #20] 8001624: 4b95 ldr r3, [pc, #596] @ (800187c ) 8001626: 6c5b ldr r3, [r3, #68] @ 0x44 8001628: 4a94 ldr r2, [pc, #592] @ (800187c ) 800162a: f043 0310 orr.w r3, r3, #16 800162e: 6453 str r3, [r2, #68] @ 0x44 8001630: 4b92 ldr r3, [pc, #584] @ (800187c ) 8001632: 6c5b ldr r3, [r3, #68] @ 0x44 8001634: f003 0310 and.w r3, r3, #16 8001638: 617b str r3, [r7, #20] 800163a: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 800163c: 2300 movs r3, #0 800163e: 613b str r3, [r7, #16] 8001640: 4b8e ldr r3, [pc, #568] @ (800187c ) 8001642: 6b1b ldr r3, [r3, #48] @ 0x30 8001644: 4a8d ldr r2, [pc, #564] @ (800187c ) 8001646: f043 0301 orr.w r3, r3, #1 800164a: 6313 str r3, [r2, #48] @ 0x30 800164c: 4b8b ldr r3, [pc, #556] @ (800187c ) 800164e: 6b1b ldr r3, [r3, #48] @ 0x30 8001650: f003 0301 and.w r3, r3, #1 8001654: 613b str r3, [r7, #16] 8001656: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 8001658: f44f 63c0 mov.w r3, #1536 @ 0x600 800165c: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800165e: 2302 movs r3, #2 8001660: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001662: 2300 movs r3, #0 8001664: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001666: 2303 movs r3, #3 8001668: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 800166a: 2307 movs r3, #7 800166c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800166e: f107 032c add.w r3, r7, #44 @ 0x2c 8001672: 4619 mov r1, r3 8001674: 4882 ldr r0, [pc, #520] @ (8001880 ) 8001676: f000 feeb bl 8002450 hdma_usart1_rx.Instance = DMA2_Stream2; 800167a: 4b82 ldr r3, [pc, #520] @ (8001884 ) 800167c: 4a82 ldr r2, [pc, #520] @ (8001888 ) 800167e: 601a str r2, [r3, #0] hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; 8001680: 4b80 ldr r3, [pc, #512] @ (8001884 ) 8001682: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001686: 605a str r2, [r3, #4] hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001688: 4b7e ldr r3, [pc, #504] @ (8001884 ) 800168a: 2200 movs r2, #0 800168c: 609a str r2, [r3, #8] hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800168e: 4b7d ldr r3, [pc, #500] @ (8001884 ) 8001690: 2200 movs r2, #0 8001692: 60da str r2, [r3, #12] hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 8001694: 4b7b ldr r3, [pc, #492] @ (8001884 ) 8001696: f44f 6280 mov.w r2, #1024 @ 0x400 800169a: 611a str r2, [r3, #16] hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800169c: 4b79 ldr r3, [pc, #484] @ (8001884 ) 800169e: 2200 movs r2, #0 80016a0: 615a str r2, [r3, #20] hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80016a2: 4b78 ldr r3, [pc, #480] @ (8001884 ) 80016a4: 2200 movs r2, #0 80016a6: 619a str r2, [r3, #24] hdma_usart1_rx.Init.Mode = DMA_NORMAL; 80016a8: 4b76 ldr r3, [pc, #472] @ (8001884 ) 80016aa: 2200 movs r2, #0 80016ac: 61da str r2, [r3, #28] hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; 80016ae: 4b75 ldr r3, [pc, #468] @ (8001884 ) 80016b0: 2200 movs r2, #0 80016b2: 621a str r2, [r3, #32] hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80016b4: 4b73 ldr r3, [pc, #460] @ (8001884 ) 80016b6: 2200 movs r2, #0 80016b8: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 80016ba: 4872 ldr r0, [pc, #456] @ (8001884 ) 80016bc: f000 fac6 bl 8001c4c 80016c0: 4603 mov r3, r0 80016c2: 2b00 cmp r3, #0 80016c4: d001 beq.n 80016ca Error_Handler(); 80016c6: f7ff fb47 bl 8000d58 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); 80016ca: 687b ldr r3, [r7, #4] 80016cc: 4a6d ldr r2, [pc, #436] @ (8001884 ) 80016ce: 63da str r2, [r3, #60] @ 0x3c 80016d0: 4a6c ldr r2, [pc, #432] @ (8001884 ) 80016d2: 687b ldr r3, [r7, #4] 80016d4: 6393 str r3, [r2, #56] @ 0x38 hdma_usart1_tx.Instance = DMA2_Stream7; 80016d6: 4b6d ldr r3, [pc, #436] @ (800188c ) 80016d8: 4a6d ldr r2, [pc, #436] @ (8001890 ) 80016da: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; 80016dc: 4b6b ldr r3, [pc, #428] @ (800188c ) 80016de: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80016e2: 605a str r2, [r3, #4] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80016e4: 4b69 ldr r3, [pc, #420] @ (800188c ) 80016e6: 2240 movs r2, #64 @ 0x40 80016e8: 609a str r2, [r3, #8] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 80016ea: 4b68 ldr r3, [pc, #416] @ (800188c ) 80016ec: 2200 movs r2, #0 80016ee: 60da str r2, [r3, #12] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 80016f0: 4b66 ldr r3, [pc, #408] @ (800188c ) 80016f2: f44f 6280 mov.w r2, #1024 @ 0x400 80016f6: 611a str r2, [r3, #16] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80016f8: 4b64 ldr r3, [pc, #400] @ (800188c ) 80016fa: 2200 movs r2, #0 80016fc: 615a str r2, [r3, #20] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80016fe: 4b63 ldr r3, [pc, #396] @ (800188c ) 8001700: 2200 movs r2, #0 8001702: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 8001704: 4b61 ldr r3, [pc, #388] @ (800188c ) 8001706: 2200 movs r2, #0 8001708: 61da str r2, [r3, #28] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 800170a: 4b60 ldr r3, [pc, #384] @ (800188c ) 800170c: 2200 movs r2, #0 800170e: 621a str r2, [r3, #32] hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001710: 4b5e ldr r3, [pc, #376] @ (800188c ) 8001712: 2200 movs r2, #0 8001714: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 8001716: 485d ldr r0, [pc, #372] @ (800188c ) 8001718: f000 fa98 bl 8001c4c 800171c: 4603 mov r3, r0 800171e: 2b00 cmp r3, #0 8001720: d001 beq.n 8001726 Error_Handler(); 8001722: f7ff fb19 bl 8000d58 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); 8001726: 687b ldr r3, [r7, #4] 8001728: 4a58 ldr r2, [pc, #352] @ (800188c ) 800172a: 639a str r2, [r3, #56] @ 0x38 800172c: 4a57 ldr r2, [pc, #348] @ (800188c ) 800172e: 687b ldr r3, [r7, #4] 8001730: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8001732: 2200 movs r2, #0 8001734: 2100 movs r1, #0 8001736: 2025 movs r0, #37 @ 0x25 8001738: f000 fa51 bl 8001bde HAL_NVIC_EnableIRQ(USART1_IRQn); 800173c: 2025 movs r0, #37 @ 0x25 800173e: f000 fa6a bl 8001c16 } 8001742: e095 b.n 8001870 else if(uartHandle->Instance==USART2) 8001744: 687b ldr r3, [r7, #4] 8001746: 681b ldr r3, [r3, #0] 8001748: 4a52 ldr r2, [pc, #328] @ (8001894 ) 800174a: 4293 cmp r3, r2 800174c: f040 8090 bne.w 8001870 __HAL_RCC_USART2_CLK_ENABLE(); 8001750: 2300 movs r3, #0 8001752: 60fb str r3, [r7, #12] 8001754: 4b49 ldr r3, [pc, #292] @ (800187c ) 8001756: 6c1b ldr r3, [r3, #64] @ 0x40 8001758: 4a48 ldr r2, [pc, #288] @ (800187c ) 800175a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800175e: 6413 str r3, [r2, #64] @ 0x40 8001760: 4b46 ldr r3, [pc, #280] @ (800187c ) 8001762: 6c1b ldr r3, [r3, #64] @ 0x40 8001764: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001768: 60fb str r3, [r7, #12] 800176a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 800176c: 2300 movs r3, #0 800176e: 60bb str r3, [r7, #8] 8001770: 4b42 ldr r3, [pc, #264] @ (800187c ) 8001772: 6b1b ldr r3, [r3, #48] @ 0x30 8001774: 4a41 ldr r2, [pc, #260] @ (800187c ) 8001776: f043 0301 orr.w r3, r3, #1 800177a: 6313 str r3, [r2, #48] @ 0x30 800177c: 4b3f ldr r3, [pc, #252] @ (800187c ) 800177e: 6b1b ldr r3, [r3, #48] @ 0x30 8001780: f003 0301 and.w r3, r3, #1 8001784: 60bb str r3, [r7, #8] 8001786: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; 8001788: 230c movs r3, #12 800178a: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800178c: 2302 movs r3, #2 800178e: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001790: 2300 movs r3, #0 8001792: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001794: 2303 movs r3, #3 8001796: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 8001798: 2307 movs r3, #7 800179a: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800179c: f107 032c add.w r3, r7, #44 @ 0x2c 80017a0: 4619 mov r1, r3 80017a2: 4837 ldr r0, [pc, #220] @ (8001880 ) 80017a4: f000 fe54 bl 8002450 hdma_usart2_rx.Instance = DMA1_Stream5; 80017a8: 4b3b ldr r3, [pc, #236] @ (8001898 ) 80017aa: 4a3c ldr r2, [pc, #240] @ (800189c ) 80017ac: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; 80017ae: 4b3a ldr r3, [pc, #232] @ (8001898 ) 80017b0: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80017b4: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80017b6: 4b38 ldr r3, [pc, #224] @ (8001898 ) 80017b8: 2200 movs r2, #0 80017ba: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 80017bc: 4b36 ldr r3, [pc, #216] @ (8001898 ) 80017be: 2200 movs r2, #0 80017c0: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 80017c2: 4b35 ldr r3, [pc, #212] @ (8001898 ) 80017c4: f44f 6280 mov.w r2, #1024 @ 0x400 80017c8: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80017ca: 4b33 ldr r3, [pc, #204] @ (8001898 ) 80017cc: 2200 movs r2, #0 80017ce: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80017d0: 4b31 ldr r3, [pc, #196] @ (8001898 ) 80017d2: 2200 movs r2, #0 80017d4: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 80017d6: 4b30 ldr r3, [pc, #192] @ (8001898 ) 80017d8: 2200 movs r2, #0 80017da: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; 80017dc: 4b2e ldr r3, [pc, #184] @ (8001898 ) 80017de: 2200 movs r2, #0 80017e0: 621a str r2, [r3, #32] hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80017e2: 4b2d ldr r3, [pc, #180] @ (8001898 ) 80017e4: 2200 movs r2, #0 80017e6: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 80017e8: 482b ldr r0, [pc, #172] @ (8001898 ) 80017ea: f000 fa2f bl 8001c4c 80017ee: 4603 mov r3, r0 80017f0: 2b00 cmp r3, #0 80017f2: d001 beq.n 80017f8 Error_Handler(); 80017f4: f7ff fab0 bl 8000d58 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 80017f8: 687b ldr r3, [r7, #4] 80017fa: 4a27 ldr r2, [pc, #156] @ (8001898 ) 80017fc: 63da str r2, [r3, #60] @ 0x3c 80017fe: 4a26 ldr r2, [pc, #152] @ (8001898 ) 8001800: 687b ldr r3, [r7, #4] 8001802: 6393 str r3, [r2, #56] @ 0x38 hdma_usart2_tx.Instance = DMA1_Stream6; 8001804: 4b26 ldr r3, [pc, #152] @ (80018a0 ) 8001806: 4a27 ldr r2, [pc, #156] @ (80018a4 ) 8001808: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; 800180a: 4b25 ldr r3, [pc, #148] @ (80018a0 ) 800180c: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001810: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001812: 4b23 ldr r3, [pc, #140] @ (80018a0 ) 8001814: 2240 movs r2, #64 @ 0x40 8001816: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001818: 4b21 ldr r3, [pc, #132] @ (80018a0 ) 800181a: 2200 movs r2, #0 800181c: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 800181e: 4b20 ldr r3, [pc, #128] @ (80018a0 ) 8001820: f44f 6280 mov.w r2, #1024 @ 0x400 8001824: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001826: 4b1e ldr r3, [pc, #120] @ (80018a0 ) 8001828: 2200 movs r2, #0 800182a: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800182c: 4b1c ldr r3, [pc, #112] @ (80018a0 ) 800182e: 2200 movs r2, #0 8001830: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 8001832: 4b1b ldr r3, [pc, #108] @ (80018a0 ) 8001834: 2200 movs r2, #0 8001836: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; 8001838: 4b19 ldr r3, [pc, #100] @ (80018a0 ) 800183a: 2200 movs r2, #0 800183c: 621a str r2, [r3, #32] hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800183e: 4b18 ldr r3, [pc, #96] @ (80018a0 ) 8001840: 2200 movs r2, #0 8001842: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 8001844: 4816 ldr r0, [pc, #88] @ (80018a0 ) 8001846: f000 fa01 bl 8001c4c 800184a: 4603 mov r3, r0 800184c: 2b00 cmp r3, #0 800184e: d001 beq.n 8001854 Error_Handler(); 8001850: f7ff fa82 bl 8000d58 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 8001854: 687b ldr r3, [r7, #4] 8001856: 4a12 ldr r2, [pc, #72] @ (80018a0 ) 8001858: 639a str r2, [r3, #56] @ 0x38 800185a: 4a11 ldr r2, [pc, #68] @ (80018a0 ) 800185c: 687b ldr r3, [r7, #4] 800185e: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 8001860: 2200 movs r2, #0 8001862: 2100 movs r1, #0 8001864: 2026 movs r0, #38 @ 0x26 8001866: f000 f9ba bl 8001bde HAL_NVIC_EnableIRQ(USART2_IRQn); 800186a: 2026 movs r0, #38 @ 0x26 800186c: f000 f9d3 bl 8001c16 } 8001870: bf00 nop 8001872: 3740 adds r7, #64 @ 0x40 8001874: 46bd mov sp, r7 8001876: bd80 pop {r7, pc} 8001878: 40011000 .word 0x40011000 800187c: 40023800 .word 0x40023800 8001880: 40020000 .word 0x40020000 8001884: 2000059c .word 0x2000059c 8001888: 40026440 .word 0x40026440 800188c: 200005fc .word 0x200005fc 8001890: 400264b8 .word 0x400264b8 8001894: 40004400 .word 0x40004400 8001898: 2000065c .word 0x2000065c 800189c: 40026088 .word 0x40026088 80018a0: 200006bc .word 0x200006bc 80018a4: 400260a0 .word 0x400260a0 080018a8 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 80018a8: f8df d034 ldr.w sp, [pc, #52] @ 80018e0 /* Call the clock system initialization function.*/ bl SystemInit 80018ac: f7ff fb34 bl 8000f18 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80018b0: 480c ldr r0, [pc, #48] @ (80018e4 ) ldr r1, =_edata 80018b2: 490d ldr r1, [pc, #52] @ (80018e8 ) ldr r2, =_sidata 80018b4: 4a0d ldr r2, [pc, #52] @ (80018ec ) movs r3, #0 80018b6: 2300 movs r3, #0 b LoopCopyDataInit 80018b8: e002 b.n 80018c0 080018ba : CopyDataInit: ldr r4, [r2, r3] 80018ba: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80018bc: 50c4 str r4, [r0, r3] adds r3, r3, #4 80018be: 3304 adds r3, #4 080018c0 : LoopCopyDataInit: adds r4, r0, r3 80018c0: 18c4 adds r4, r0, r3 cmp r4, r1 80018c2: 428c cmp r4, r1 bcc CopyDataInit 80018c4: d3f9 bcc.n 80018ba /* Zero fill the bss segment. */ ldr r2, =_sbss 80018c6: 4a0a ldr r2, [pc, #40] @ (80018f0 ) ldr r4, =_ebss 80018c8: 4c0a ldr r4, [pc, #40] @ (80018f4 ) movs r3, #0 80018ca: 2300 movs r3, #0 b LoopFillZerobss 80018cc: e001 b.n 80018d2 080018ce : FillZerobss: str r3, [r2] 80018ce: 6013 str r3, [r2, #0] adds r2, r2, #4 80018d0: 3204 adds r2, #4 080018d2 : LoopFillZerobss: cmp r2, r4 80018d2: 42a2 cmp r2, r4 bcc FillZerobss 80018d4: d3fb bcc.n 80018ce /* Call static constructors */ bl __libc_init_array 80018d6: f009 f8eb bl 800aab0 <__libc_init_array> /* Call the application's entry point.*/ bl main 80018da: f7fe ffa5 bl 8000828
bx lr 80018de: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 80018e0: 20020000 .word 0x20020000 ldr r0, =_sdata 80018e4: 20000000 .word 0x20000000 ldr r1, =_edata 80018e8: 200001a0 .word 0x200001a0 ldr r2, =_sidata 80018ec: 0800ab98 .word 0x0800ab98 ldr r2, =_sbss 80018f0: 200001a0 .word 0x200001a0 ldr r4, =_ebss 80018f4: 200010f8 .word 0x200010f8 080018f8 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80018f8: e7fe b.n 80018f8 ... 080018fc : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80018fc: b580 push {r7, lr} 80018fe: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 8001900: 4b0e ldr r3, [pc, #56] @ (800193c ) 8001902: 681b ldr r3, [r3, #0] 8001904: 4a0d ldr r2, [pc, #52] @ (800193c ) 8001906: f443 7300 orr.w r3, r3, #512 @ 0x200 800190a: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 800190c: 4b0b ldr r3, [pc, #44] @ (800193c ) 800190e: 681b ldr r3, [r3, #0] 8001910: 4a0a ldr r2, [pc, #40] @ (800193c ) 8001912: f443 6380 orr.w r3, r3, #1024 @ 0x400 8001916: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001918: 4b08 ldr r3, [pc, #32] @ (800193c ) 800191a: 681b ldr r3, [r3, #0] 800191c: 4a07 ldr r2, [pc, #28] @ (800193c ) 800191e: f443 7380 orr.w r3, r3, #256 @ 0x100 8001922: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001924: 2003 movs r0, #3 8001926: f000 f94f bl 8001bc8 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800192a: 200f movs r0, #15 800192c: f000 f808 bl 8001940 /* Init the low level hardware */ HAL_MspInit(); 8001930: f7ff fa18 bl 8000d64 /* Return function status */ return HAL_OK; 8001934: 2300 movs r3, #0 } 8001936: 4618 mov r0, r3 8001938: bd80 pop {r7, pc} 800193a: bf00 nop 800193c: 40023c00 .word 0x40023c00 08001940 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001940: b580 push {r7, lr} 8001942: b082 sub sp, #8 8001944: af00 add r7, sp, #0 8001946: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8001948: 4b12 ldr r3, [pc, #72] @ (8001994 ) 800194a: 681a ldr r2, [r3, #0] 800194c: 4b12 ldr r3, [pc, #72] @ (8001998 ) 800194e: 781b ldrb r3, [r3, #0] 8001950: 4619 mov r1, r3 8001952: f44f 737a mov.w r3, #1000 @ 0x3e8 8001956: fbb3 f3f1 udiv r3, r3, r1 800195a: fbb2 f3f3 udiv r3, r2, r3 800195e: 4618 mov r0, r3 8001960: f000 f967 bl 8001c32 8001964: 4603 mov r3, r0 8001966: 2b00 cmp r3, #0 8001968: d001 beq.n 800196e { return HAL_ERROR; 800196a: 2301 movs r3, #1 800196c: e00e b.n 800198c } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800196e: 687b ldr r3, [r7, #4] 8001970: 2b0f cmp r3, #15 8001972: d80a bhi.n 800198a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001974: 2200 movs r2, #0 8001976: 6879 ldr r1, [r7, #4] 8001978: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800197c: f000 f92f bl 8001bde uwTickPrio = TickPriority; 8001980: 4a06 ldr r2, [pc, #24] @ (800199c ) 8001982: 687b ldr r3, [r7, #4] 8001984: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8001986: 2300 movs r3, #0 8001988: e000 b.n 800198c return HAL_ERROR; 800198a: 2301 movs r3, #1 } 800198c: 4618 mov r0, r3 800198e: 3708 adds r7, #8 8001990: 46bd mov sp, r7 8001992: bd80 pop {r7, pc} 8001994: 20000090 .word 0x20000090 8001998: 20000098 .word 0x20000098 800199c: 20000094 .word 0x20000094 080019a0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80019a0: b480 push {r7} 80019a2: af00 add r7, sp, #0 uwTick += uwTickFreq; 80019a4: 4b06 ldr r3, [pc, #24] @ (80019c0 ) 80019a6: 781b ldrb r3, [r3, #0] 80019a8: 461a mov r2, r3 80019aa: 4b06 ldr r3, [pc, #24] @ (80019c4 ) 80019ac: 681b ldr r3, [r3, #0] 80019ae: 4413 add r3, r2 80019b0: 4a04 ldr r2, [pc, #16] @ (80019c4 ) 80019b2: 6013 str r3, [r2, #0] } 80019b4: bf00 nop 80019b6: 46bd mov sp, r7 80019b8: f85d 7b04 ldr.w r7, [sp], #4 80019bc: 4770 bx lr 80019be: bf00 nop 80019c0: 20000098 .word 0x20000098 80019c4: 2000071c .word 0x2000071c 080019c8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80019c8: b480 push {r7} 80019ca: af00 add r7, sp, #0 return uwTick; 80019cc: 4b03 ldr r3, [pc, #12] @ (80019dc ) 80019ce: 681b ldr r3, [r3, #0] } 80019d0: 4618 mov r0, r3 80019d2: 46bd mov sp, r7 80019d4: f85d 7b04 ldr.w r7, [sp], #4 80019d8: 4770 bx lr 80019da: bf00 nop 80019dc: 2000071c .word 0x2000071c 080019e0 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80019e0: b580 push {r7, lr} 80019e2: b084 sub sp, #16 80019e4: af00 add r7, sp, #0 80019e6: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80019e8: f7ff ffee bl 80019c8 80019ec: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80019ee: 687b ldr r3, [r7, #4] 80019f0: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80019f2: 68fb ldr r3, [r7, #12] 80019f4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80019f8: d005 beq.n 8001a06 { wait += (uint32_t)(uwTickFreq); 80019fa: 4b0a ldr r3, [pc, #40] @ (8001a24 ) 80019fc: 781b ldrb r3, [r3, #0] 80019fe: 461a mov r2, r3 8001a00: 68fb ldr r3, [r7, #12] 8001a02: 4413 add r3, r2 8001a04: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8001a06: bf00 nop 8001a08: f7ff ffde bl 80019c8 8001a0c: 4602 mov r2, r0 8001a0e: 68bb ldr r3, [r7, #8] 8001a10: 1ad3 subs r3, r2, r3 8001a12: 68fa ldr r2, [r7, #12] 8001a14: 429a cmp r2, r3 8001a16: d8f7 bhi.n 8001a08 { } } 8001a18: bf00 nop 8001a1a: bf00 nop 8001a1c: 3710 adds r7, #16 8001a1e: 46bd mov sp, r7 8001a20: bd80 pop {r7, pc} 8001a22: bf00 nop 8001a24: 20000098 .word 0x20000098 08001a28 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001a28: b480 push {r7} 8001a2a: b085 sub sp, #20 8001a2c: af00 add r7, sp, #0 8001a2e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001a30: 687b ldr r3, [r7, #4] 8001a32: f003 0307 and.w r3, r3, #7 8001a36: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001a38: 4b0c ldr r3, [pc, #48] @ (8001a6c <__NVIC_SetPriorityGrouping+0x44>) 8001a3a: 68db ldr r3, [r3, #12] 8001a3c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001a3e: 68ba ldr r2, [r7, #8] 8001a40: f64f 03ff movw r3, #63743 @ 0xf8ff 8001a44: 4013 ands r3, r2 8001a46: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001a48: 68fb ldr r3, [r7, #12] 8001a4a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001a4c: 68bb ldr r3, [r7, #8] 8001a4e: 4313 orrs r3, r2 reg_value = (reg_value | 8001a50: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8001a54: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001a58: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001a5a: 4a04 ldr r2, [pc, #16] @ (8001a6c <__NVIC_SetPriorityGrouping+0x44>) 8001a5c: 68bb ldr r3, [r7, #8] 8001a5e: 60d3 str r3, [r2, #12] } 8001a60: bf00 nop 8001a62: 3714 adds r7, #20 8001a64: 46bd mov sp, r7 8001a66: f85d 7b04 ldr.w r7, [sp], #4 8001a6a: 4770 bx lr 8001a6c: e000ed00 .word 0xe000ed00 08001a70 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001a70: b480 push {r7} 8001a72: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001a74: 4b04 ldr r3, [pc, #16] @ (8001a88 <__NVIC_GetPriorityGrouping+0x18>) 8001a76: 68db ldr r3, [r3, #12] 8001a78: 0a1b lsrs r3, r3, #8 8001a7a: f003 0307 and.w r3, r3, #7 } 8001a7e: 4618 mov r0, r3 8001a80: 46bd mov sp, r7 8001a82: f85d 7b04 ldr.w r7, [sp], #4 8001a86: 4770 bx lr 8001a88: e000ed00 .word 0xe000ed00 08001a8c <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8001a8c: b480 push {r7} 8001a8e: b083 sub sp, #12 8001a90: af00 add r7, sp, #0 8001a92: 4603 mov r3, r0 8001a94: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001a96: f997 3007 ldrsb.w r3, [r7, #7] 8001a9a: 2b00 cmp r3, #0 8001a9c: db0b blt.n 8001ab6 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001a9e: 79fb ldrb r3, [r7, #7] 8001aa0: f003 021f and.w r2, r3, #31 8001aa4: 4907 ldr r1, [pc, #28] @ (8001ac4 <__NVIC_EnableIRQ+0x38>) 8001aa6: f997 3007 ldrsb.w r3, [r7, #7] 8001aaa: 095b lsrs r3, r3, #5 8001aac: 2001 movs r0, #1 8001aae: fa00 f202 lsl.w r2, r0, r2 8001ab2: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8001ab6: bf00 nop 8001ab8: 370c adds r7, #12 8001aba: 46bd mov sp, r7 8001abc: f85d 7b04 ldr.w r7, [sp], #4 8001ac0: 4770 bx lr 8001ac2: bf00 nop 8001ac4: e000e100 .word 0xe000e100 08001ac8 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001ac8: b480 push {r7} 8001aca: b083 sub sp, #12 8001acc: af00 add r7, sp, #0 8001ace: 4603 mov r3, r0 8001ad0: 6039 str r1, [r7, #0] 8001ad2: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001ad4: f997 3007 ldrsb.w r3, [r7, #7] 8001ad8: 2b00 cmp r3, #0 8001ada: db0a blt.n 8001af2 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001adc: 683b ldr r3, [r7, #0] 8001ade: b2da uxtb r2, r3 8001ae0: 490c ldr r1, [pc, #48] @ (8001b14 <__NVIC_SetPriority+0x4c>) 8001ae2: f997 3007 ldrsb.w r3, [r7, #7] 8001ae6: 0112 lsls r2, r2, #4 8001ae8: b2d2 uxtb r2, r2 8001aea: 440b add r3, r1 8001aec: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001af0: e00a b.n 8001b08 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001af2: 683b ldr r3, [r7, #0] 8001af4: b2da uxtb r2, r3 8001af6: 4908 ldr r1, [pc, #32] @ (8001b18 <__NVIC_SetPriority+0x50>) 8001af8: 79fb ldrb r3, [r7, #7] 8001afa: f003 030f and.w r3, r3, #15 8001afe: 3b04 subs r3, #4 8001b00: 0112 lsls r2, r2, #4 8001b02: b2d2 uxtb r2, r2 8001b04: 440b add r3, r1 8001b06: 761a strb r2, [r3, #24] } 8001b08: bf00 nop 8001b0a: 370c adds r7, #12 8001b0c: 46bd mov sp, r7 8001b0e: f85d 7b04 ldr.w r7, [sp], #4 8001b12: 4770 bx lr 8001b14: e000e100 .word 0xe000e100 8001b18: e000ed00 .word 0xe000ed00 08001b1c : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001b1c: b480 push {r7} 8001b1e: b089 sub sp, #36 @ 0x24 8001b20: af00 add r7, sp, #0 8001b22: 60f8 str r0, [r7, #12] 8001b24: 60b9 str r1, [r7, #8] 8001b26: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001b28: 68fb ldr r3, [r7, #12] 8001b2a: f003 0307 and.w r3, r3, #7 8001b2e: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001b30: 69fb ldr r3, [r7, #28] 8001b32: f1c3 0307 rsb r3, r3, #7 8001b36: 2b04 cmp r3, #4 8001b38: bf28 it cs 8001b3a: 2304 movcs r3, #4 8001b3c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001b3e: 69fb ldr r3, [r7, #28] 8001b40: 3304 adds r3, #4 8001b42: 2b06 cmp r3, #6 8001b44: d902 bls.n 8001b4c 8001b46: 69fb ldr r3, [r7, #28] 8001b48: 3b03 subs r3, #3 8001b4a: e000 b.n 8001b4e 8001b4c: 2300 movs r3, #0 8001b4e: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001b50: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8001b54: 69bb ldr r3, [r7, #24] 8001b56: fa02 f303 lsl.w r3, r2, r3 8001b5a: 43da mvns r2, r3 8001b5c: 68bb ldr r3, [r7, #8] 8001b5e: 401a ands r2, r3 8001b60: 697b ldr r3, [r7, #20] 8001b62: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001b64: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001b68: 697b ldr r3, [r7, #20] 8001b6a: fa01 f303 lsl.w r3, r1, r3 8001b6e: 43d9 mvns r1, r3 8001b70: 687b ldr r3, [r7, #4] 8001b72: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001b74: 4313 orrs r3, r2 ); } 8001b76: 4618 mov r0, r3 8001b78: 3724 adds r7, #36 @ 0x24 8001b7a: 46bd mov sp, r7 8001b7c: f85d 7b04 ldr.w r7, [sp], #4 8001b80: 4770 bx lr ... 08001b84 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001b84: b580 push {r7, lr} 8001b86: b082 sub sp, #8 8001b88: af00 add r7, sp, #0 8001b8a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001b8c: 687b ldr r3, [r7, #4] 8001b8e: 3b01 subs r3, #1 8001b90: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8001b94: d301 bcc.n 8001b9a { return (1UL); /* Reload value impossible */ 8001b96: 2301 movs r3, #1 8001b98: e00f b.n 8001bba } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001b9a: 4a0a ldr r2, [pc, #40] @ (8001bc4 ) 8001b9c: 687b ldr r3, [r7, #4] 8001b9e: 3b01 subs r3, #1 8001ba0: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001ba2: 210f movs r1, #15 8001ba4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8001ba8: f7ff ff8e bl 8001ac8 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001bac: 4b05 ldr r3, [pc, #20] @ (8001bc4 ) 8001bae: 2200 movs r2, #0 8001bb0: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001bb2: 4b04 ldr r3, [pc, #16] @ (8001bc4 ) 8001bb4: 2207 movs r2, #7 8001bb6: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001bb8: 2300 movs r3, #0 } 8001bba: 4618 mov r0, r3 8001bbc: 3708 adds r7, #8 8001bbe: 46bd mov sp, r7 8001bc0: bd80 pop {r7, pc} 8001bc2: bf00 nop 8001bc4: e000e010 .word 0xe000e010 08001bc8 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001bc8: b580 push {r7, lr} 8001bca: b082 sub sp, #8 8001bcc: af00 add r7, sp, #0 8001bce: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001bd0: 6878 ldr r0, [r7, #4] 8001bd2: f7ff ff29 bl 8001a28 <__NVIC_SetPriorityGrouping> } 8001bd6: bf00 nop 8001bd8: 3708 adds r7, #8 8001bda: 46bd mov sp, r7 8001bdc: bd80 pop {r7, pc} 08001bde : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001bde: b580 push {r7, lr} 8001be0: b086 sub sp, #24 8001be2: af00 add r7, sp, #0 8001be4: 4603 mov r3, r0 8001be6: 60b9 str r1, [r7, #8] 8001be8: 607a str r2, [r7, #4] 8001bea: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001bec: 2300 movs r3, #0 8001bee: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001bf0: f7ff ff3e bl 8001a70 <__NVIC_GetPriorityGrouping> 8001bf4: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001bf6: 687a ldr r2, [r7, #4] 8001bf8: 68b9 ldr r1, [r7, #8] 8001bfa: 6978 ldr r0, [r7, #20] 8001bfc: f7ff ff8e bl 8001b1c 8001c00: 4602 mov r2, r0 8001c02: f997 300f ldrsb.w r3, [r7, #15] 8001c06: 4611 mov r1, r2 8001c08: 4618 mov r0, r3 8001c0a: f7ff ff5d bl 8001ac8 <__NVIC_SetPriority> } 8001c0e: bf00 nop 8001c10: 3718 adds r7, #24 8001c12: 46bd mov sp, r7 8001c14: bd80 pop {r7, pc} 08001c16 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8001c16: b580 push {r7, lr} 8001c18: b082 sub sp, #8 8001c1a: af00 add r7, sp, #0 8001c1c: 4603 mov r3, r0 8001c1e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001c20: f997 3007 ldrsb.w r3, [r7, #7] 8001c24: 4618 mov r0, r3 8001c26: f7ff ff31 bl 8001a8c <__NVIC_EnableIRQ> } 8001c2a: bf00 nop 8001c2c: 3708 adds r7, #8 8001c2e: 46bd mov sp, r7 8001c30: bd80 pop {r7, pc} 08001c32 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001c32: b580 push {r7, lr} 8001c34: b082 sub sp, #8 8001c36: af00 add r7, sp, #0 8001c38: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001c3a: 6878 ldr r0, [r7, #4] 8001c3c: f7ff ffa2 bl 8001b84 8001c40: 4603 mov r3, r0 } 8001c42: 4618 mov r0, r3 8001c44: 3708 adds r7, #8 8001c46: 46bd mov sp, r7 8001c48: bd80 pop {r7, pc} ... 08001c4c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8001c4c: b580 push {r7, lr} 8001c4e: b086 sub sp, #24 8001c50: af00 add r7, sp, #0 8001c52: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 8001c54: 2300 movs r3, #0 8001c56: 617b str r3, [r7, #20] uint32_t tickstart = HAL_GetTick(); 8001c58: f7ff feb6 bl 80019c8 8001c5c: 6138 str r0, [r7, #16] DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) 8001c5e: 687b ldr r3, [r7, #4] 8001c60: 2b00 cmp r3, #0 8001c62: d101 bne.n 8001c68 { return HAL_ERROR; 8001c64: 2301 movs r3, #1 8001c66: e099 b.n 8001d9c assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001c68: 687b ldr r3, [r7, #4] 8001c6a: 2202 movs r2, #2 8001c6c: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8001c70: 687b ldr r3, [r7, #4] 8001c72: 2200 movs r2, #0 8001c74: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8001c78: 687b ldr r3, [r7, #4] 8001c7a: 681b ldr r3, [r3, #0] 8001c7c: 681a ldr r2, [r3, #0] 8001c7e: 687b ldr r3, [r7, #4] 8001c80: 681b ldr r3, [r3, #0] 8001c82: f022 0201 bic.w r2, r2, #1 8001c86: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001c88: e00f b.n 8001caa { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8001c8a: f7ff fe9d bl 80019c8 8001c8e: 4602 mov r2, r0 8001c90: 693b ldr r3, [r7, #16] 8001c92: 1ad3 subs r3, r2, r3 8001c94: 2b05 cmp r3, #5 8001c96: d908 bls.n 8001caa { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8001c98: 687b ldr r3, [r7, #4] 8001c9a: 2220 movs r2, #32 8001c9c: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8001c9e: 687b ldr r3, [r7, #4] 8001ca0: 2203 movs r2, #3 8001ca2: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_TIMEOUT; 8001ca6: 2303 movs r3, #3 8001ca8: e078 b.n 8001d9c while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001caa: 687b ldr r3, [r7, #4] 8001cac: 681b ldr r3, [r3, #0] 8001cae: 681b ldr r3, [r3, #0] 8001cb0: f003 0301 and.w r3, r3, #1 8001cb4: 2b00 cmp r3, #0 8001cb6: d1e8 bne.n 8001c8a } } /* Get the CR register value */ tmp = hdma->Instance->CR; 8001cb8: 687b ldr r3, [r7, #4] 8001cba: 681b ldr r3, [r3, #0] 8001cbc: 681b ldr r3, [r3, #0] 8001cbe: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8001cc0: 697a ldr r2, [r7, #20] 8001cc2: 4b38 ldr r3, [pc, #224] @ (8001da4 ) 8001cc4: 4013 ands r3, r2 8001cc6: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001cc8: 687b ldr r3, [r7, #4] 8001cca: 685a ldr r2, [r3, #4] 8001ccc: 687b ldr r3, [r7, #4] 8001cce: 689b ldr r3, [r3, #8] 8001cd0: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001cd2: 687b ldr r3, [r7, #4] 8001cd4: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001cd6: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001cd8: 687b ldr r3, [r7, #4] 8001cda: 691b ldr r3, [r3, #16] 8001cdc: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001cde: 687b ldr r3, [r7, #4] 8001ce0: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8001ce2: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001ce4: 687b ldr r3, [r7, #4] 8001ce6: 699b ldr r3, [r3, #24] 8001ce8: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001cea: 687b ldr r3, [r7, #4] 8001cec: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001cee: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001cf0: 687b ldr r3, [r7, #4] 8001cf2: 6a1b ldr r3, [r3, #32] 8001cf4: 4313 orrs r3, r2 tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001cf6: 697a ldr r2, [r7, #20] 8001cf8: 4313 orrs r3, r2 8001cfa: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001cfc: 687b ldr r3, [r7, #4] 8001cfe: 6a5b ldr r3, [r3, #36] @ 0x24 8001d00: 2b04 cmp r3, #4 8001d02: d107 bne.n 8001d14 { /* Get memory burst and peripheral burst */ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8001d04: 687b ldr r3, [r7, #4] 8001d06: 6ada ldr r2, [r3, #44] @ 0x2c 8001d08: 687b ldr r3, [r7, #4] 8001d0a: 6b1b ldr r3, [r3, #48] @ 0x30 8001d0c: 4313 orrs r3, r2 8001d0e: 697a ldr r2, [r7, #20] 8001d10: 4313 orrs r3, r2 8001d12: 617b str r3, [r7, #20] } /* Write to DMA Stream CR register */ hdma->Instance->CR = tmp; 8001d14: 687b ldr r3, [r7, #4] 8001d16: 681b ldr r3, [r3, #0] 8001d18: 697a ldr r2, [r7, #20] 8001d1a: 601a str r2, [r3, #0] /* Get the FCR register value */ tmp = hdma->Instance->FCR; 8001d1c: 687b ldr r3, [r7, #4] 8001d1e: 681b ldr r3, [r3, #0] 8001d20: 695b ldr r3, [r3, #20] 8001d22: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8001d24: 697b ldr r3, [r7, #20] 8001d26: f023 0307 bic.w r3, r3, #7 8001d2a: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ tmp |= hdma->Init.FIFOMode; 8001d2c: 687b ldr r3, [r7, #4] 8001d2e: 6a5b ldr r3, [r3, #36] @ 0x24 8001d30: 697a ldr r2, [r7, #20] 8001d32: 4313 orrs r3, r2 8001d34: 617b str r3, [r7, #20] /* The FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001d36: 687b ldr r3, [r7, #4] 8001d38: 6a5b ldr r3, [r3, #36] @ 0x24 8001d3a: 2b04 cmp r3, #4 8001d3c: d117 bne.n 8001d6e { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; 8001d3e: 687b ldr r3, [r7, #4] 8001d40: 6a9b ldr r3, [r3, #40] @ 0x28 8001d42: 697a ldr r2, [r7, #20] 8001d44: 4313 orrs r3, r2 8001d46: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 bursts */ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8001d48: 687b ldr r3, [r7, #4] 8001d4a: 6adb ldr r3, [r3, #44] @ 0x2c 8001d4c: 2b00 cmp r3, #0 8001d4e: d00e beq.n 8001d6e { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8001d50: 6878 ldr r0, [r7, #4] 8001d52: f000 fb01 bl 8002358 8001d56: 4603 mov r3, r0 8001d58: 2b00 cmp r3, #0 8001d5a: d008 beq.n 8001d6e { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8001d5c: 687b ldr r3, [r7, #4] 8001d5e: 2240 movs r2, #64 @ 0x40 8001d60: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001d62: 687b ldr r3, [r7, #4] 8001d64: 2201 movs r2, #1 8001d66: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8001d6a: 2301 movs r3, #1 8001d6c: e016 b.n 8001d9c } } } /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; 8001d6e: 687b ldr r3, [r7, #4] 8001d70: 681b ldr r3, [r3, #0] 8001d72: 697a ldr r2, [r7, #20] 8001d74: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8001d76: 6878 ldr r0, [r7, #4] 8001d78: f000 fab8 bl 80022ec 8001d7c: 4603 mov r3, r0 8001d7e: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001d80: 687b ldr r3, [r7, #4] 8001d82: 6ddb ldr r3, [r3, #92] @ 0x5c 8001d84: 223f movs r2, #63 @ 0x3f 8001d86: 409a lsls r2, r3 8001d88: 68fb ldr r3, [r7, #12] 8001d8a: 609a str r2, [r3, #8] /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001d8c: 687b ldr r3, [r7, #4] 8001d8e: 2200 movs r2, #0 8001d90: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001d92: 687b ldr r3, [r7, #4] 8001d94: 2201 movs r2, #1 8001d96: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8001d9a: 2300 movs r3, #0 } 8001d9c: 4618 mov r0, r3 8001d9e: 3718 adds r7, #24 8001da0: 46bd mov sp, r7 8001da2: bd80 pop {r7, pc} 8001da4: f010803f .word 0xf010803f 08001da8 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8001da8: b580 push {r7, lr} 8001daa: b086 sub sp, #24 8001dac: af00 add r7, sp, #0 8001dae: 60f8 str r0, [r7, #12] 8001db0: 60b9 str r1, [r7, #8] 8001db2: 607a str r2, [r7, #4] 8001db4: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8001db6: 2300 movs r3, #0 8001db8: 75fb strb r3, [r7, #23] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001dba: 68fb ldr r3, [r7, #12] 8001dbc: 6d9b ldr r3, [r3, #88] @ 0x58 8001dbe: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8001dc0: 68fb ldr r3, [r7, #12] 8001dc2: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8001dc6: 2b01 cmp r3, #1 8001dc8: d101 bne.n 8001dce 8001dca: 2302 movs r3, #2 8001dcc: e040 b.n 8001e50 8001dce: 68fb ldr r3, [r7, #12] 8001dd0: 2201 movs r2, #1 8001dd2: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8001dd6: 68fb ldr r3, [r7, #12] 8001dd8: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001ddc: b2db uxtb r3, r3 8001dde: 2b01 cmp r3, #1 8001de0: d12f bne.n 8001e42 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001de2: 68fb ldr r3, [r7, #12] 8001de4: 2202 movs r2, #2 8001de6: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001dea: 68fb ldr r3, [r7, #12] 8001dec: 2200 movs r2, #0 8001dee: 655a str r2, [r3, #84] @ 0x54 /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8001df0: 683b ldr r3, [r7, #0] 8001df2: 687a ldr r2, [r7, #4] 8001df4: 68b9 ldr r1, [r7, #8] 8001df6: 68f8 ldr r0, [r7, #12] 8001df8: f000 fa4a bl 8002290 /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001dfc: 68fb ldr r3, [r7, #12] 8001dfe: 6ddb ldr r3, [r3, #92] @ 0x5c 8001e00: 223f movs r2, #63 @ 0x3f 8001e02: 409a lsls r2, r3 8001e04: 693b ldr r3, [r7, #16] 8001e06: 609a str r2, [r3, #8] /* Enable Common interrupts*/ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; 8001e08: 68fb ldr r3, [r7, #12] 8001e0a: 681b ldr r3, [r3, #0] 8001e0c: 681a ldr r2, [r3, #0] 8001e0e: 68fb ldr r3, [r7, #12] 8001e10: 681b ldr r3, [r3, #0] 8001e12: f042 0216 orr.w r2, r2, #22 8001e16: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8001e18: 68fb ldr r3, [r7, #12] 8001e1a: 6c1b ldr r3, [r3, #64] @ 0x40 8001e1c: 2b00 cmp r3, #0 8001e1e: d007 beq.n 8001e30 { hdma->Instance->CR |= DMA_IT_HT; 8001e20: 68fb ldr r3, [r7, #12] 8001e22: 681b ldr r3, [r3, #0] 8001e24: 681a ldr r2, [r3, #0] 8001e26: 68fb ldr r3, [r7, #12] 8001e28: 681b ldr r3, [r3, #0] 8001e2a: f042 0208 orr.w r2, r2, #8 8001e2e: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8001e30: 68fb ldr r3, [r7, #12] 8001e32: 681b ldr r3, [r3, #0] 8001e34: 681a ldr r2, [r3, #0] 8001e36: 68fb ldr r3, [r7, #12] 8001e38: 681b ldr r3, [r3, #0] 8001e3a: f042 0201 orr.w r2, r2, #1 8001e3e: 601a str r2, [r3, #0] 8001e40: e005 b.n 8001e4e } else { /* Process unlocked */ __HAL_UNLOCK(hdma); 8001e42: 68fb ldr r3, [r7, #12] 8001e44: 2200 movs r2, #0 8001e46: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_BUSY; 8001e4a: 2302 movs r3, #2 8001e4c: 75fb strb r3, [r7, #23] } return status; 8001e4e: 7dfb ldrb r3, [r7, #23] } 8001e50: 4618 mov r0, r3 8001e52: 3718 adds r7, #24 8001e54: 46bd mov sp, r7 8001e56: bd80 pop {r7, pc} 08001e58 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8001e58: b580 push {r7, lr} 8001e5a: b084 sub sp, #16 8001e5c: af00 add r7, sp, #0 8001e5e: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001e60: 687b ldr r3, [r7, #4] 8001e62: 6d9b ldr r3, [r3, #88] @ 0x58 8001e64: 60fb str r3, [r7, #12] uint32_t tickstart = HAL_GetTick(); 8001e66: f7ff fdaf bl 80019c8 8001e6a: 60b8 str r0, [r7, #8] if(hdma->State != HAL_DMA_STATE_BUSY) 8001e6c: 687b ldr r3, [r7, #4] 8001e6e: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001e72: b2db uxtb r3, r3 8001e74: 2b02 cmp r3, #2 8001e76: d008 beq.n 8001e8a { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001e78: 687b ldr r3, [r7, #4] 8001e7a: 2280 movs r2, #128 @ 0x80 8001e7c: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001e7e: 687b ldr r3, [r7, #4] 8001e80: 2200 movs r2, #0 8001e82: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8001e86: 2301 movs r3, #1 8001e88: e052 b.n 8001f30 } else { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8001e8a: 687b ldr r3, [r7, #4] 8001e8c: 681b ldr r3, [r3, #0] 8001e8e: 681a ldr r2, [r3, #0] 8001e90: 687b ldr r3, [r7, #4] 8001e92: 681b ldr r3, [r3, #0] 8001e94: f022 0216 bic.w r2, r2, #22 8001e98: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 8001e9a: 687b ldr r3, [r7, #4] 8001e9c: 681b ldr r3, [r3, #0] 8001e9e: 695a ldr r2, [r3, #20] 8001ea0: 687b ldr r3, [r7, #4] 8001ea2: 681b ldr r3, [r3, #0] 8001ea4: f022 0280 bic.w r2, r2, #128 @ 0x80 8001ea8: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8001eaa: 687b ldr r3, [r7, #4] 8001eac: 6c1b ldr r3, [r3, #64] @ 0x40 8001eae: 2b00 cmp r3, #0 8001eb0: d103 bne.n 8001eba 8001eb2: 687b ldr r3, [r7, #4] 8001eb4: 6c9b ldr r3, [r3, #72] @ 0x48 8001eb6: 2b00 cmp r3, #0 8001eb8: d007 beq.n 8001eca { hdma->Instance->CR &= ~(DMA_IT_HT); 8001eba: 687b ldr r3, [r7, #4] 8001ebc: 681b ldr r3, [r3, #0] 8001ebe: 681a ldr r2, [r3, #0] 8001ec0: 687b ldr r3, [r7, #4] 8001ec2: 681b ldr r3, [r3, #0] 8001ec4: f022 0208 bic.w r2, r2, #8 8001ec8: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8001eca: 687b ldr r3, [r7, #4] 8001ecc: 681b ldr r3, [r3, #0] 8001ece: 681a ldr r2, [r3, #0] 8001ed0: 687b ldr r3, [r7, #4] 8001ed2: 681b ldr r3, [r3, #0] 8001ed4: f022 0201 bic.w r2, r2, #1 8001ed8: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001eda: e013 b.n 8001f04 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8001edc: f7ff fd74 bl 80019c8 8001ee0: 4602 mov r2, r0 8001ee2: 68bb ldr r3, [r7, #8] 8001ee4: 1ad3 subs r3, r2, r3 8001ee6: 2b05 cmp r3, #5 8001ee8: d90c bls.n 8001f04 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8001eea: 687b ldr r3, [r7, #4] 8001eec: 2220 movs r2, #32 8001eee: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8001ef0: 687b ldr r3, [r7, #4] 8001ef2: 2203 movs r2, #3 8001ef4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001ef8: 687b ldr r3, [r7, #4] 8001efa: 2200 movs r2, #0 8001efc: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_TIMEOUT; 8001f00: 2303 movs r3, #3 8001f02: e015 b.n 8001f30 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001f04: 687b ldr r3, [r7, #4] 8001f06: 681b ldr r3, [r3, #0] 8001f08: 681b ldr r3, [r3, #0] 8001f0a: f003 0301 and.w r3, r3, #1 8001f0e: 2b00 cmp r3, #0 8001f10: d1e4 bne.n 8001edc } } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001f12: 687b ldr r3, [r7, #4] 8001f14: 6ddb ldr r3, [r3, #92] @ 0x5c 8001f16: 223f movs r2, #63 @ 0x3f 8001f18: 409a lsls r2, r3 8001f1a: 68fb ldr r3, [r7, #12] 8001f1c: 609a str r2, [r3, #8] /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8001f1e: 687b ldr r3, [r7, #4] 8001f20: 2201 movs r2, #1 8001f22: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001f26: 687b ldr r3, [r7, #4] 8001f28: 2200 movs r2, #0 8001f2a: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 8001f2e: 2300 movs r3, #0 } 8001f30: 4618 mov r0, r3 8001f32: 3710 adds r7, #16 8001f34: 46bd mov sp, r7 8001f36: bd80 pop {r7, pc} 08001f38 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8001f38: b480 push {r7} 8001f3a: b083 sub sp, #12 8001f3c: af00 add r7, sp, #0 8001f3e: 6078 str r0, [r7, #4] if(hdma->State != HAL_DMA_STATE_BUSY) 8001f40: 687b ldr r3, [r7, #4] 8001f42: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001f46: b2db uxtb r3, r3 8001f48: 2b02 cmp r3, #2 8001f4a: d004 beq.n 8001f56 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001f4c: 687b ldr r3, [r7, #4] 8001f4e: 2280 movs r2, #128 @ 0x80 8001f50: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 8001f52: 2301 movs r3, #1 8001f54: e00c b.n 8001f70 } else { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 8001f56: 687b ldr r3, [r7, #4] 8001f58: 2205 movs r2, #5 8001f5a: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8001f5e: 687b ldr r3, [r7, #4] 8001f60: 681b ldr r3, [r3, #0] 8001f62: 681a ldr r2, [r3, #0] 8001f64: 687b ldr r3, [r7, #4] 8001f66: 681b ldr r3, [r3, #0] 8001f68: f022 0201 bic.w r2, r2, #1 8001f6c: 601a str r2, [r3, #0] } return HAL_OK; 8001f6e: 2300 movs r3, #0 } 8001f70: 4618 mov r0, r3 8001f72: 370c adds r7, #12 8001f74: 46bd mov sp, r7 8001f76: f85d 7b04 ldr.w r7, [sp], #4 8001f7a: 4770 bx lr 08001f7c : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8001f7c: b580 push {r7, lr} 8001f7e: b086 sub sp, #24 8001f80: af00 add r7, sp, #0 8001f82: 6078 str r0, [r7, #4] uint32_t tmpisr; __IO uint32_t count = 0U; 8001f84: 2300 movs r3, #0 8001f86: 60bb str r3, [r7, #8] uint32_t timeout = SystemCoreClock / 9600U; 8001f88: 4b8e ldr r3, [pc, #568] @ (80021c4 ) 8001f8a: 681b ldr r3, [r3, #0] 8001f8c: 4a8e ldr r2, [pc, #568] @ (80021c8 ) 8001f8e: fba2 2303 umull r2, r3, r2, r3 8001f92: 0a9b lsrs r3, r3, #10 8001f94: 617b str r3, [r7, #20] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001f96: 687b ldr r3, [r7, #4] 8001f98: 6d9b ldr r3, [r3, #88] @ 0x58 8001f9a: 613b str r3, [r7, #16] tmpisr = regs->ISR; 8001f9c: 693b ldr r3, [r7, #16] 8001f9e: 681b ldr r3, [r3, #0] 8001fa0: 60fb str r3, [r7, #12] /* Transfer Error Interrupt management ***************************************/ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) 8001fa2: 687b ldr r3, [r7, #4] 8001fa4: 6ddb ldr r3, [r3, #92] @ 0x5c 8001fa6: 2208 movs r2, #8 8001fa8: 409a lsls r2, r3 8001faa: 68fb ldr r3, [r7, #12] 8001fac: 4013 ands r3, r2 8001fae: 2b00 cmp r3, #0 8001fb0: d01a beq.n 8001fe8 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) 8001fb2: 687b ldr r3, [r7, #4] 8001fb4: 681b ldr r3, [r3, #0] 8001fb6: 681b ldr r3, [r3, #0] 8001fb8: f003 0304 and.w r3, r3, #4 8001fbc: 2b00 cmp r3, #0 8001fbe: d013 beq.n 8001fe8 { /* Disable the transfer error interrupt */ hdma->Instance->CR &= ~(DMA_IT_TE); 8001fc0: 687b ldr r3, [r7, #4] 8001fc2: 681b ldr r3, [r3, #0] 8001fc4: 681a ldr r2, [r3, #0] 8001fc6: 687b ldr r3, [r7, #4] 8001fc8: 681b ldr r3, [r3, #0] 8001fca: f022 0204 bic.w r2, r2, #4 8001fce: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; 8001fd0: 687b ldr r3, [r7, #4] 8001fd2: 6ddb ldr r3, [r3, #92] @ 0x5c 8001fd4: 2208 movs r2, #8 8001fd6: 409a lsls r2, r3 8001fd8: 693b ldr r3, [r7, #16] 8001fda: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8001fdc: 687b ldr r3, [r7, #4] 8001fde: 6d5b ldr r3, [r3, #84] @ 0x54 8001fe0: f043 0201 orr.w r2, r3, #1 8001fe4: 687b ldr r3, [r7, #4] 8001fe6: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) 8001fe8: 687b ldr r3, [r7, #4] 8001fea: 6ddb ldr r3, [r3, #92] @ 0x5c 8001fec: 2201 movs r2, #1 8001fee: 409a lsls r2, r3 8001ff0: 68fb ldr r3, [r7, #12] 8001ff2: 4013 ands r3, r2 8001ff4: 2b00 cmp r3, #0 8001ff6: d012 beq.n 800201e { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) 8001ff8: 687b ldr r3, [r7, #4] 8001ffa: 681b ldr r3, [r3, #0] 8001ffc: 695b ldr r3, [r3, #20] 8001ffe: f003 0380 and.w r3, r3, #128 @ 0x80 8002002: 2b00 cmp r3, #0 8002004: d00b beq.n 800201e { /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; 8002006: 687b ldr r3, [r7, #4] 8002008: 6ddb ldr r3, [r3, #92] @ 0x5c 800200a: 2201 movs r2, #1 800200c: 409a lsls r2, r3 800200e: 693b ldr r3, [r7, #16] 8002010: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8002012: 687b ldr r3, [r7, #4] 8002014: 6d5b ldr r3, [r3, #84] @ 0x54 8002016: f043 0202 orr.w r2, r3, #2 800201a: 687b ldr r3, [r7, #4] 800201c: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) 800201e: 687b ldr r3, [r7, #4] 8002020: 6ddb ldr r3, [r3, #92] @ 0x5c 8002022: 2204 movs r2, #4 8002024: 409a lsls r2, r3 8002026: 68fb ldr r3, [r7, #12] 8002028: 4013 ands r3, r2 800202a: 2b00 cmp r3, #0 800202c: d012 beq.n 8002054 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) 800202e: 687b ldr r3, [r7, #4] 8002030: 681b ldr r3, [r3, #0] 8002032: 681b ldr r3, [r3, #0] 8002034: f003 0302 and.w r3, r3, #2 8002038: 2b00 cmp r3, #0 800203a: d00b beq.n 8002054 { /* Clear the direct mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; 800203c: 687b ldr r3, [r7, #4] 800203e: 6ddb ldr r3, [r3, #92] @ 0x5c 8002040: 2204 movs r2, #4 8002042: 409a lsls r2, r3 8002044: 693b ldr r3, [r7, #16] 8002046: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8002048: 687b ldr r3, [r7, #4] 800204a: 6d5b ldr r3, [r3, #84] @ 0x54 800204c: f043 0204 orr.w r2, r3, #4 8002050: 687b ldr r3, [r7, #4] 8002052: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) 8002054: 687b ldr r3, [r7, #4] 8002056: 6ddb ldr r3, [r3, #92] @ 0x5c 8002058: 2210 movs r2, #16 800205a: 409a lsls r2, r3 800205c: 68fb ldr r3, [r7, #12] 800205e: 4013 ands r3, r2 8002060: 2b00 cmp r3, #0 8002062: d043 beq.n 80020ec { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) 8002064: 687b ldr r3, [r7, #4] 8002066: 681b ldr r3, [r3, #0] 8002068: 681b ldr r3, [r3, #0] 800206a: f003 0308 and.w r3, r3, #8 800206e: 2b00 cmp r3, #0 8002070: d03c beq.n 80020ec { /* Clear the half transfer complete flag */ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; 8002072: 687b ldr r3, [r7, #4] 8002074: 6ddb ldr r3, [r3, #92] @ 0x5c 8002076: 2210 movs r2, #16 8002078: 409a lsls r2, r3 800207a: 693b ldr r3, [r7, #16] 800207c: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 800207e: 687b ldr r3, [r7, #4] 8002080: 681b ldr r3, [r3, #0] 8002082: 681b ldr r3, [r3, #0] 8002084: f403 2380 and.w r3, r3, #262144 @ 0x40000 8002088: 2b00 cmp r3, #0 800208a: d018 beq.n 80020be { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 800208c: 687b ldr r3, [r7, #4] 800208e: 681b ldr r3, [r3, #0] 8002090: 681b ldr r3, [r3, #0] 8002092: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002096: 2b00 cmp r3, #0 8002098: d108 bne.n 80020ac { if(hdma->XferHalfCpltCallback != NULL) 800209a: 687b ldr r3, [r7, #4] 800209c: 6c1b ldr r3, [r3, #64] @ 0x40 800209e: 2b00 cmp r3, #0 80020a0: d024 beq.n 80020ec { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 80020a2: 687b ldr r3, [r7, #4] 80020a4: 6c1b ldr r3, [r3, #64] @ 0x40 80020a6: 6878 ldr r0, [r7, #4] 80020a8: 4798 blx r3 80020aa: e01f b.n 80020ec } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 80020ac: 687b ldr r3, [r7, #4] 80020ae: 6c9b ldr r3, [r3, #72] @ 0x48 80020b0: 2b00 cmp r3, #0 80020b2: d01b beq.n 80020ec { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 80020b4: 687b ldr r3, [r7, #4] 80020b6: 6c9b ldr r3, [r3, #72] @ 0x48 80020b8: 6878 ldr r0, [r7, #4] 80020ba: 4798 blx r3 80020bc: e016 b.n 80020ec } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 80020be: 687b ldr r3, [r7, #4] 80020c0: 681b ldr r3, [r3, #0] 80020c2: 681b ldr r3, [r3, #0] 80020c4: f403 7380 and.w r3, r3, #256 @ 0x100 80020c8: 2b00 cmp r3, #0 80020ca: d107 bne.n 80020dc { /* Disable the half transfer interrupt */ hdma->Instance->CR &= ~(DMA_IT_HT); 80020cc: 687b ldr r3, [r7, #4] 80020ce: 681b ldr r3, [r3, #0] 80020d0: 681a ldr r2, [r3, #0] 80020d2: 687b ldr r3, [r7, #4] 80020d4: 681b ldr r3, [r3, #0] 80020d6: f022 0208 bic.w r2, r2, #8 80020da: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 80020dc: 687b ldr r3, [r7, #4] 80020de: 6c1b ldr r3, [r3, #64] @ 0x40 80020e0: 2b00 cmp r3, #0 80020e2: d003 beq.n 80020ec { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 80020e4: 687b ldr r3, [r7, #4] 80020e6: 6c1b ldr r3, [r3, #64] @ 0x40 80020e8: 6878 ldr r0, [r7, #4] 80020ea: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) 80020ec: 687b ldr r3, [r7, #4] 80020ee: 6ddb ldr r3, [r3, #92] @ 0x5c 80020f0: 2220 movs r2, #32 80020f2: 409a lsls r2, r3 80020f4: 68fb ldr r3, [r7, #12] 80020f6: 4013 ands r3, r2 80020f8: 2b00 cmp r3, #0 80020fa: f000 808f beq.w 800221c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) 80020fe: 687b ldr r3, [r7, #4] 8002100: 681b ldr r3, [r3, #0] 8002102: 681b ldr r3, [r3, #0] 8002104: f003 0310 and.w r3, r3, #16 8002108: 2b00 cmp r3, #0 800210a: f000 8087 beq.w 800221c { /* Clear the transfer complete flag */ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; 800210e: 687b ldr r3, [r7, #4] 8002110: 6ddb ldr r3, [r3, #92] @ 0x5c 8002112: 2220 movs r2, #32 8002114: 409a lsls r2, r3 8002116: 693b ldr r3, [r7, #16] 8002118: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 800211a: 687b ldr r3, [r7, #4] 800211c: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8002120: b2db uxtb r3, r3 8002122: 2b05 cmp r3, #5 8002124: d136 bne.n 8002194 { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8002126: 687b ldr r3, [r7, #4] 8002128: 681b ldr r3, [r3, #0] 800212a: 681a ldr r2, [r3, #0] 800212c: 687b ldr r3, [r7, #4] 800212e: 681b ldr r3, [r3, #0] 8002130: f022 0216 bic.w r2, r2, #22 8002134: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 8002136: 687b ldr r3, [r7, #4] 8002138: 681b ldr r3, [r3, #0] 800213a: 695a ldr r2, [r3, #20] 800213c: 687b ldr r3, [r7, #4] 800213e: 681b ldr r3, [r3, #0] 8002140: f022 0280 bic.w r2, r2, #128 @ 0x80 8002144: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8002146: 687b ldr r3, [r7, #4] 8002148: 6c1b ldr r3, [r3, #64] @ 0x40 800214a: 2b00 cmp r3, #0 800214c: d103 bne.n 8002156 800214e: 687b ldr r3, [r7, #4] 8002150: 6c9b ldr r3, [r3, #72] @ 0x48 8002152: 2b00 cmp r3, #0 8002154: d007 beq.n 8002166 { hdma->Instance->CR &= ~(DMA_IT_HT); 8002156: 687b ldr r3, [r7, #4] 8002158: 681b ldr r3, [r3, #0] 800215a: 681a ldr r2, [r3, #0] 800215c: 687b ldr r3, [r7, #4] 800215e: 681b ldr r3, [r3, #0] 8002160: f022 0208 bic.w r2, r2, #8 8002164: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8002166: 687b ldr r3, [r7, #4] 8002168: 6ddb ldr r3, [r3, #92] @ 0x5c 800216a: 223f movs r2, #63 @ 0x3f 800216c: 409a lsls r2, r3 800216e: 693b ldr r3, [r7, #16] 8002170: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002172: 687b ldr r3, [r7, #4] 8002174: 2201 movs r2, #1 8002176: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800217a: 687b ldr r3, [r7, #4] 800217c: 2200 movs r2, #0 800217e: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 8002182: 687b ldr r3, [r7, #4] 8002184: 6d1b ldr r3, [r3, #80] @ 0x50 8002186: 2b00 cmp r3, #0 8002188: d07e beq.n 8002288 { hdma->XferAbortCallback(hdma); 800218a: 687b ldr r3, [r7, #4] 800218c: 6d1b ldr r3, [r3, #80] @ 0x50 800218e: 6878 ldr r0, [r7, #4] 8002190: 4798 blx r3 } return; 8002192: e079 b.n 8002288 } if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 8002194: 687b ldr r3, [r7, #4] 8002196: 681b ldr r3, [r3, #0] 8002198: 681b ldr r3, [r3, #0] 800219a: f403 2380 and.w r3, r3, #262144 @ 0x40000 800219e: 2b00 cmp r3, #0 80021a0: d01d beq.n 80021de { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 80021a2: 687b ldr r3, [r7, #4] 80021a4: 681b ldr r3, [r3, #0] 80021a6: 681b ldr r3, [r3, #0] 80021a8: f403 2300 and.w r3, r3, #524288 @ 0x80000 80021ac: 2b00 cmp r3, #0 80021ae: d10d bne.n 80021cc { if(hdma->XferM1CpltCallback != NULL) 80021b0: 687b ldr r3, [r7, #4] 80021b2: 6c5b ldr r3, [r3, #68] @ 0x44 80021b4: 2b00 cmp r3, #0 80021b6: d031 beq.n 800221c { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 80021b8: 687b ldr r3, [r7, #4] 80021ba: 6c5b ldr r3, [r3, #68] @ 0x44 80021bc: 6878 ldr r0, [r7, #4] 80021be: 4798 blx r3 80021c0: e02c b.n 800221c 80021c2: bf00 nop 80021c4: 20000090 .word 0x20000090 80021c8: 1b4e81b5 .word 0x1b4e81b5 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 80021cc: 687b ldr r3, [r7, #4] 80021ce: 6bdb ldr r3, [r3, #60] @ 0x3c 80021d0: 2b00 cmp r3, #0 80021d2: d023 beq.n 800221c { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 80021d4: 687b ldr r3, [r7, #4] 80021d6: 6bdb ldr r3, [r3, #60] @ 0x3c 80021d8: 6878 ldr r0, [r7, #4] 80021da: 4798 blx r3 80021dc: e01e b.n 800221c } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 80021de: 687b ldr r3, [r7, #4] 80021e0: 681b ldr r3, [r3, #0] 80021e2: 681b ldr r3, [r3, #0] 80021e4: f403 7380 and.w r3, r3, #256 @ 0x100 80021e8: 2b00 cmp r3, #0 80021ea: d10f bne.n 800220c { /* Disable the transfer complete interrupt */ hdma->Instance->CR &= ~(DMA_IT_TC); 80021ec: 687b ldr r3, [r7, #4] 80021ee: 681b ldr r3, [r3, #0] 80021f0: 681a ldr r2, [r3, #0] 80021f2: 687b ldr r3, [r7, #4] 80021f4: 681b ldr r3, [r3, #0] 80021f6: f022 0210 bic.w r2, r2, #16 80021fa: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80021fc: 687b ldr r3, [r7, #4] 80021fe: 2201 movs r2, #1 8002200: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002204: 687b ldr r3, [r7, #4] 8002206: 2200 movs r2, #0 8002208: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800220c: 687b ldr r3, [r7, #4] 800220e: 6bdb ldr r3, [r3, #60] @ 0x3c 8002210: 2b00 cmp r3, #0 8002212: d003 beq.n 800221c { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8002214: 687b ldr r3, [r7, #4] 8002216: 6bdb ldr r3, [r3, #60] @ 0x3c 8002218: 6878 ldr r0, [r7, #4] 800221a: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 800221c: 687b ldr r3, [r7, #4] 800221e: 6d5b ldr r3, [r3, #84] @ 0x54 8002220: 2b00 cmp r3, #0 8002222: d032 beq.n 800228a { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) 8002224: 687b ldr r3, [r7, #4] 8002226: 6d5b ldr r3, [r3, #84] @ 0x54 8002228: f003 0301 and.w r3, r3, #1 800222c: 2b00 cmp r3, #0 800222e: d022 beq.n 8002276 { hdma->State = HAL_DMA_STATE_ABORT; 8002230: 687b ldr r3, [r7, #4] 8002232: 2205 movs r2, #5 8002234: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8002238: 687b ldr r3, [r7, #4] 800223a: 681b ldr r3, [r3, #0] 800223c: 681a ldr r2, [r3, #0] 800223e: 687b ldr r3, [r7, #4] 8002240: 681b ldr r3, [r3, #0] 8002242: f022 0201 bic.w r2, r2, #1 8002246: 601a str r2, [r3, #0] do { if (++count > timeout) 8002248: 68bb ldr r3, [r7, #8] 800224a: 3301 adds r3, #1 800224c: 60bb str r3, [r7, #8] 800224e: 697a ldr r2, [r7, #20] 8002250: 429a cmp r2, r3 8002252: d307 bcc.n 8002264 { break; } } while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); 8002254: 687b ldr r3, [r7, #4] 8002256: 681b ldr r3, [r3, #0] 8002258: 681b ldr r3, [r3, #0] 800225a: f003 0301 and.w r3, r3, #1 800225e: 2b00 cmp r3, #0 8002260: d1f2 bne.n 8002248 8002262: e000 b.n 8002266 break; 8002264: bf00 nop /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002266: 687b ldr r3, [r7, #4] 8002268: 2201 movs r2, #1 800226a: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800226e: 687b ldr r3, [r7, #4] 8002270: 2200 movs r2, #0 8002272: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 8002276: 687b ldr r3, [r7, #4] 8002278: 6cdb ldr r3, [r3, #76] @ 0x4c 800227a: 2b00 cmp r3, #0 800227c: d005 beq.n 800228a { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800227e: 687b ldr r3, [r7, #4] 8002280: 6cdb ldr r3, [r3, #76] @ 0x4c 8002282: 6878 ldr r0, [r7, #4] 8002284: 4798 blx r3 8002286: e000 b.n 800228a return; 8002288: bf00 nop } } } 800228a: 3718 adds r7, #24 800228c: 46bd mov sp, r7 800228e: bd80 pop {r7, pc} 08002290 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002290: b480 push {r7} 8002292: b085 sub sp, #20 8002294: af00 add r7, sp, #0 8002296: 60f8 str r0, [r7, #12] 8002298: 60b9 str r1, [r7, #8] 800229a: 607a str r2, [r7, #4] 800229c: 603b str r3, [r7, #0] /* Clear DBM bit */ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); 800229e: 68fb ldr r3, [r7, #12] 80022a0: 681b ldr r3, [r3, #0] 80022a2: 681a ldr r2, [r3, #0] 80022a4: 68fb ldr r3, [r7, #12] 80022a6: 681b ldr r3, [r3, #0] 80022a8: f422 2280 bic.w r2, r2, #262144 @ 0x40000 80022ac: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; 80022ae: 68fb ldr r3, [r7, #12] 80022b0: 681b ldr r3, [r3, #0] 80022b2: 683a ldr r2, [r7, #0] 80022b4: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 80022b6: 68fb ldr r3, [r7, #12] 80022b8: 689b ldr r3, [r3, #8] 80022ba: 2b40 cmp r3, #64 @ 0x40 80022bc: d108 bne.n 80022d0 { /* Configure DMA Stream destination address */ hdma->Instance->PAR = DstAddress; 80022be: 68fb ldr r3, [r7, #12] 80022c0: 681b ldr r3, [r3, #0] 80022c2: 687a ldr r2, [r7, #4] 80022c4: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; 80022c6: 68fb ldr r3, [r7, #12] 80022c8: 681b ldr r3, [r3, #0] 80022ca: 68ba ldr r2, [r7, #8] 80022cc: 60da str r2, [r3, #12] hdma->Instance->PAR = SrcAddress; /* Configure DMA Stream destination address */ hdma->Instance->M0AR = DstAddress; } } 80022ce: e007 b.n 80022e0 hdma->Instance->PAR = SrcAddress; 80022d0: 68fb ldr r3, [r7, #12] 80022d2: 681b ldr r3, [r3, #0] 80022d4: 68ba ldr r2, [r7, #8] 80022d6: 609a str r2, [r3, #8] hdma->Instance->M0AR = DstAddress; 80022d8: 68fb ldr r3, [r7, #12] 80022da: 681b ldr r3, [r3, #0] 80022dc: 687a ldr r2, [r7, #4] 80022de: 60da str r2, [r3, #12] } 80022e0: bf00 nop 80022e2: 3714 adds r7, #20 80022e4: 46bd mov sp, r7 80022e6: f85d 7b04 ldr.w r7, [sp], #4 80022ea: 4770 bx lr 080022ec : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 80022ec: b480 push {r7} 80022ee: b085 sub sp, #20 80022f0: af00 add r7, sp, #0 80022f2: 6078 str r0, [r7, #4] uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; 80022f4: 687b ldr r3, [r7, #4] 80022f6: 681b ldr r3, [r3, #0] 80022f8: b2db uxtb r3, r3 80022fa: 3b10 subs r3, #16 80022fc: 4a14 ldr r2, [pc, #80] @ (8002350 ) 80022fe: fba2 2303 umull r2, r3, r2, r3 8002302: 091b lsrs r3, r3, #4 8002304: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number]; 8002306: 4a13 ldr r2, [pc, #76] @ (8002354 ) 8002308: 68fb ldr r3, [r7, #12] 800230a: 4413 add r3, r2 800230c: 781b ldrb r3, [r3, #0] 800230e: 461a mov r2, r3 8002310: 687b ldr r3, [r7, #4] 8002312: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 8002314: 68fb ldr r3, [r7, #12] 8002316: 2b03 cmp r3, #3 8002318: d909 bls.n 800232e { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); 800231a: 687b ldr r3, [r7, #4] 800231c: 681b ldr r3, [r3, #0] 800231e: f423 737f bic.w r3, r3, #1020 @ 0x3fc 8002322: f023 0303 bic.w r3, r3, #3 8002326: 1d1a adds r2, r3, #4 8002328: 687b ldr r3, [r7, #4] 800232a: 659a str r2, [r3, #88] @ 0x58 800232c: e007 b.n 800233e } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); 800232e: 687b ldr r3, [r7, #4] 8002330: 681b ldr r3, [r3, #0] 8002332: f423 737f bic.w r3, r3, #1020 @ 0x3fc 8002336: f023 0303 bic.w r3, r3, #3 800233a: 687a ldr r2, [r7, #4] 800233c: 6593 str r3, [r2, #88] @ 0x58 } return hdma->StreamBaseAddress; 800233e: 687b ldr r3, [r7, #4] 8002340: 6d9b ldr r3, [r3, #88] @ 0x58 } 8002342: 4618 mov r0, r3 8002344: 3714 adds r7, #20 8002346: 46bd mov sp, r7 8002348: f85d 7b04 ldr.w r7, [sp], #4 800234c: 4770 bx lr 800234e: bf00 nop 8002350: aaaaaaab .word 0xaaaaaaab 8002354: 0800ab80 .word 0x0800ab80 08002358 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 8002358: b480 push {r7} 800235a: b085 sub sp, #20 800235c: af00 add r7, sp, #0 800235e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002360: 2300 movs r3, #0 8002362: 73fb strb r3, [r7, #15] uint32_t tmp = hdma->Init.FIFOThreshold; 8002364: 687b ldr r3, [r7, #4] 8002366: 6a9b ldr r3, [r3, #40] @ 0x28 8002368: 60bb str r3, [r7, #8] /* Memory Data size equal to Byte */ if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 800236a: 687b ldr r3, [r7, #4] 800236c: 699b ldr r3, [r3, #24] 800236e: 2b00 cmp r3, #0 8002370: d11f bne.n 80023b2 { switch (tmp) 8002372: 68bb ldr r3, [r7, #8] 8002374: 2b03 cmp r3, #3 8002376: d856 bhi.n 8002426 8002378: a201 add r2, pc, #4 @ (adr r2, 8002380 ) 800237a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800237e: bf00 nop 8002380: 08002391 .word 0x08002391 8002384: 080023a3 .word 0x080023a3 8002388: 08002391 .word 0x08002391 800238c: 08002427 .word 0x08002427 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002390: 687b ldr r3, [r7, #4] 8002392: 6adb ldr r3, [r3, #44] @ 0x2c 8002394: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002398: 2b00 cmp r3, #0 800239a: d046 beq.n 800242a { status = HAL_ERROR; 800239c: 2301 movs r3, #1 800239e: 73fb strb r3, [r7, #15] } break; 80023a0: e043 b.n 800242a case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 80023a2: 687b ldr r3, [r7, #4] 80023a4: 6adb ldr r3, [r3, #44] @ 0x2c 80023a6: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 80023aa: d140 bne.n 800242e { status = HAL_ERROR; 80023ac: 2301 movs r3, #1 80023ae: 73fb strb r3, [r7, #15] } break; 80023b0: e03d b.n 800242e break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 80023b2: 687b ldr r3, [r7, #4] 80023b4: 699b ldr r3, [r3, #24] 80023b6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80023ba: d121 bne.n 8002400 { switch (tmp) 80023bc: 68bb ldr r3, [r7, #8] 80023be: 2b03 cmp r3, #3 80023c0: d837 bhi.n 8002432 80023c2: a201 add r2, pc, #4 @ (adr r2, 80023c8 ) 80023c4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80023c8: 080023d9 .word 0x080023d9 80023cc: 080023df .word 0x080023df 80023d0: 080023d9 .word 0x080023d9 80023d4: 080023f1 .word 0x080023f1 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 80023d8: 2301 movs r3, #1 80023da: 73fb strb r3, [r7, #15] break; 80023dc: e030 b.n 8002440 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 80023de: 687b ldr r3, [r7, #4] 80023e0: 6adb ldr r3, [r3, #44] @ 0x2c 80023e2: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80023e6: 2b00 cmp r3, #0 80023e8: d025 beq.n 8002436 { status = HAL_ERROR; 80023ea: 2301 movs r3, #1 80023ec: 73fb strb r3, [r7, #15] } break; 80023ee: e022 b.n 8002436 case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 80023f0: 687b ldr r3, [r7, #4] 80023f2: 6adb ldr r3, [r3, #44] @ 0x2c 80023f4: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 80023f8: d11f bne.n 800243a { status = HAL_ERROR; 80023fa: 2301 movs r3, #1 80023fc: 73fb strb r3, [r7, #15] } break; 80023fe: e01c b.n 800243a } /* Memory Data size equal to Word */ else { switch (tmp) 8002400: 68bb ldr r3, [r7, #8] 8002402: 2b02 cmp r3, #2 8002404: d903 bls.n 800240e 8002406: 68bb ldr r3, [r7, #8] 8002408: 2b03 cmp r3, #3 800240a: d003 beq.n 8002414 { status = HAL_ERROR; } break; default: break; 800240c: e018 b.n 8002440 status = HAL_ERROR; 800240e: 2301 movs r3, #1 8002410: 73fb strb r3, [r7, #15] break; 8002412: e015 b.n 8002440 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002414: 687b ldr r3, [r7, #4] 8002416: 6adb ldr r3, [r3, #44] @ 0x2c 8002418: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800241c: 2b00 cmp r3, #0 800241e: d00e beq.n 800243e status = HAL_ERROR; 8002420: 2301 movs r3, #1 8002422: 73fb strb r3, [r7, #15] break; 8002424: e00b b.n 800243e break; 8002426: bf00 nop 8002428: e00a b.n 8002440 break; 800242a: bf00 nop 800242c: e008 b.n 8002440 break; 800242e: bf00 nop 8002430: e006 b.n 8002440 break; 8002432: bf00 nop 8002434: e004 b.n 8002440 break; 8002436: bf00 nop 8002438: e002 b.n 8002440 break; 800243a: bf00 nop 800243c: e000 b.n 8002440 break; 800243e: bf00 nop } } return status; 8002440: 7bfb ldrb r3, [r7, #15] } 8002442: 4618 mov r0, r3 8002444: 3714 adds r7, #20 8002446: 46bd mov sp, r7 8002448: f85d 7b04 ldr.w r7, [sp], #4 800244c: 4770 bx lr 800244e: bf00 nop 08002450 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8002450: b480 push {r7} 8002452: b089 sub sp, #36 @ 0x24 8002454: af00 add r7, sp, #0 8002456: 6078 str r0, [r7, #4] 8002458: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 800245a: 2300 movs r3, #0 800245c: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 800245e: 2300 movs r3, #0 8002460: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 8002462: 2300 movs r3, #0 8002464: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 8002466: 2300 movs r3, #0 8002468: 61fb str r3, [r7, #28] 800246a: e165 b.n 8002738 { /* Get the IO position */ ioposition = 0x01U << position; 800246c: 2201 movs r2, #1 800246e: 69fb ldr r3, [r7, #28] 8002470: fa02 f303 lsl.w r3, r2, r3 8002474: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8002476: 683b ldr r3, [r7, #0] 8002478: 681b ldr r3, [r3, #0] 800247a: 697a ldr r2, [r7, #20] 800247c: 4013 ands r3, r2 800247e: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8002480: 693a ldr r2, [r7, #16] 8002482: 697b ldr r3, [r7, #20] 8002484: 429a cmp r2, r3 8002486: f040 8154 bne.w 8002732 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 800248a: 683b ldr r3, [r7, #0] 800248c: 685b ldr r3, [r3, #4] 800248e: f003 0303 and.w r3, r3, #3 8002492: 2b01 cmp r3, #1 8002494: d005 beq.n 80024a2 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002496: 683b ldr r3, [r7, #0] 8002498: 685b ldr r3, [r3, #4] 800249a: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 800249e: 2b02 cmp r3, #2 80024a0: d130 bne.n 8002504 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 80024a2: 687b ldr r3, [r7, #4] 80024a4: 689b ldr r3, [r3, #8] 80024a6: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 80024a8: 69fb ldr r3, [r7, #28] 80024aa: 005b lsls r3, r3, #1 80024ac: 2203 movs r2, #3 80024ae: fa02 f303 lsl.w r3, r2, r3 80024b2: 43db mvns r3, r3 80024b4: 69ba ldr r2, [r7, #24] 80024b6: 4013 ands r3, r2 80024b8: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 80024ba: 683b ldr r3, [r7, #0] 80024bc: 68da ldr r2, [r3, #12] 80024be: 69fb ldr r3, [r7, #28] 80024c0: 005b lsls r3, r3, #1 80024c2: fa02 f303 lsl.w r3, r2, r3 80024c6: 69ba ldr r2, [r7, #24] 80024c8: 4313 orrs r3, r2 80024ca: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 80024cc: 687b ldr r3, [r7, #4] 80024ce: 69ba ldr r2, [r7, #24] 80024d0: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 80024d2: 687b ldr r3, [r7, #4] 80024d4: 685b ldr r3, [r3, #4] 80024d6: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 80024d8: 2201 movs r2, #1 80024da: 69fb ldr r3, [r7, #28] 80024dc: fa02 f303 lsl.w r3, r2, r3 80024e0: 43db mvns r3, r3 80024e2: 69ba ldr r2, [r7, #24] 80024e4: 4013 ands r3, r2 80024e6: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80024e8: 683b ldr r3, [r7, #0] 80024ea: 685b ldr r3, [r3, #4] 80024ec: 091b lsrs r3, r3, #4 80024ee: f003 0201 and.w r2, r3, #1 80024f2: 69fb ldr r3, [r7, #28] 80024f4: fa02 f303 lsl.w r3, r2, r3 80024f8: 69ba ldr r2, [r7, #24] 80024fa: 4313 orrs r3, r2 80024fc: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 80024fe: 687b ldr r3, [r7, #4] 8002500: 69ba ldr r2, [r7, #24] 8002502: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8002504: 683b ldr r3, [r7, #0] 8002506: 685b ldr r3, [r3, #4] 8002508: f003 0303 and.w r3, r3, #3 800250c: 2b03 cmp r3, #3 800250e: d017 beq.n 8002540 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8002510: 687b ldr r3, [r7, #4] 8002512: 68db ldr r3, [r3, #12] 8002514: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8002516: 69fb ldr r3, [r7, #28] 8002518: 005b lsls r3, r3, #1 800251a: 2203 movs r2, #3 800251c: fa02 f303 lsl.w r3, r2, r3 8002520: 43db mvns r3, r3 8002522: 69ba ldr r2, [r7, #24] 8002524: 4013 ands r3, r2 8002526: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8002528: 683b ldr r3, [r7, #0] 800252a: 689a ldr r2, [r3, #8] 800252c: 69fb ldr r3, [r7, #28] 800252e: 005b lsls r3, r3, #1 8002530: fa02 f303 lsl.w r3, r2, r3 8002534: 69ba ldr r2, [r7, #24] 8002536: 4313 orrs r3, r2 8002538: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 800253a: 687b ldr r3, [r7, #4] 800253c: 69ba ldr r2, [r7, #24] 800253e: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002540: 683b ldr r3, [r7, #0] 8002542: 685b ldr r3, [r3, #4] 8002544: f003 0303 and.w r3, r3, #3 8002548: 2b02 cmp r3, #2 800254a: d123 bne.n 8002594 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800254c: 69fb ldr r3, [r7, #28] 800254e: 08da lsrs r2, r3, #3 8002550: 687b ldr r3, [r7, #4] 8002552: 3208 adds r2, #8 8002554: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8002558: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 800255a: 69fb ldr r3, [r7, #28] 800255c: f003 0307 and.w r3, r3, #7 8002560: 009b lsls r3, r3, #2 8002562: 220f movs r2, #15 8002564: fa02 f303 lsl.w r3, r2, r3 8002568: 43db mvns r3, r3 800256a: 69ba ldr r2, [r7, #24] 800256c: 4013 ands r3, r2 800256e: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 8002570: 683b ldr r3, [r7, #0] 8002572: 691a ldr r2, [r3, #16] 8002574: 69fb ldr r3, [r7, #28] 8002576: f003 0307 and.w r3, r3, #7 800257a: 009b lsls r3, r3, #2 800257c: fa02 f303 lsl.w r3, r2, r3 8002580: 69ba ldr r2, [r7, #24] 8002582: 4313 orrs r3, r2 8002584: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8002586: 69fb ldr r3, [r7, #28] 8002588: 08da lsrs r2, r3, #3 800258a: 687b ldr r3, [r7, #4] 800258c: 3208 adds r2, #8 800258e: 69b9 ldr r1, [r7, #24] 8002590: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8002594: 687b ldr r3, [r7, #4] 8002596: 681b ldr r3, [r3, #0] 8002598: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 800259a: 69fb ldr r3, [r7, #28] 800259c: 005b lsls r3, r3, #1 800259e: 2203 movs r2, #3 80025a0: fa02 f303 lsl.w r3, r2, r3 80025a4: 43db mvns r3, r3 80025a6: 69ba ldr r2, [r7, #24] 80025a8: 4013 ands r3, r2 80025aa: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 80025ac: 683b ldr r3, [r7, #0] 80025ae: 685b ldr r3, [r3, #4] 80025b0: f003 0203 and.w r2, r3, #3 80025b4: 69fb ldr r3, [r7, #28] 80025b6: 005b lsls r3, r3, #1 80025b8: fa02 f303 lsl.w r3, r2, r3 80025bc: 69ba ldr r2, [r7, #24] 80025be: 4313 orrs r3, r2 80025c0: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 80025c2: 687b ldr r3, [r7, #4] 80025c4: 69ba ldr r2, [r7, #24] 80025c6: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 80025c8: 683b ldr r3, [r7, #0] 80025ca: 685b ldr r3, [r3, #4] 80025cc: f403 3340 and.w r3, r3, #196608 @ 0x30000 80025d0: 2b00 cmp r3, #0 80025d2: f000 80ae beq.w 8002732 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80025d6: 2300 movs r3, #0 80025d8: 60fb str r3, [r7, #12] 80025da: 4b5d ldr r3, [pc, #372] @ (8002750 ) 80025dc: 6c5b ldr r3, [r3, #68] @ 0x44 80025de: 4a5c ldr r2, [pc, #368] @ (8002750 ) 80025e0: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80025e4: 6453 str r3, [r2, #68] @ 0x44 80025e6: 4b5a ldr r3, [pc, #360] @ (8002750 ) 80025e8: 6c5b ldr r3, [r3, #68] @ 0x44 80025ea: f403 4380 and.w r3, r3, #16384 @ 0x4000 80025ee: 60fb str r3, [r7, #12] 80025f0: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 80025f2: 4a58 ldr r2, [pc, #352] @ (8002754 ) 80025f4: 69fb ldr r3, [r7, #28] 80025f6: 089b lsrs r3, r3, #2 80025f8: 3302 adds r3, #2 80025fa: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80025fe: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8002600: 69fb ldr r3, [r7, #28] 8002602: f003 0303 and.w r3, r3, #3 8002606: 009b lsls r3, r3, #2 8002608: 220f movs r2, #15 800260a: fa02 f303 lsl.w r3, r2, r3 800260e: 43db mvns r3, r3 8002610: 69ba ldr r2, [r7, #24] 8002612: 4013 ands r3, r2 8002614: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8002616: 687b ldr r3, [r7, #4] 8002618: 4a4f ldr r2, [pc, #316] @ (8002758 ) 800261a: 4293 cmp r3, r2 800261c: d025 beq.n 800266a 800261e: 687b ldr r3, [r7, #4] 8002620: 4a4e ldr r2, [pc, #312] @ (800275c ) 8002622: 4293 cmp r3, r2 8002624: d01f beq.n 8002666 8002626: 687b ldr r3, [r7, #4] 8002628: 4a4d ldr r2, [pc, #308] @ (8002760 ) 800262a: 4293 cmp r3, r2 800262c: d019 beq.n 8002662 800262e: 687b ldr r3, [r7, #4] 8002630: 4a4c ldr r2, [pc, #304] @ (8002764 ) 8002632: 4293 cmp r3, r2 8002634: d013 beq.n 800265e 8002636: 687b ldr r3, [r7, #4] 8002638: 4a4b ldr r2, [pc, #300] @ (8002768 ) 800263a: 4293 cmp r3, r2 800263c: d00d beq.n 800265a 800263e: 687b ldr r3, [r7, #4] 8002640: 4a4a ldr r2, [pc, #296] @ (800276c ) 8002642: 4293 cmp r3, r2 8002644: d007 beq.n 8002656 8002646: 687b ldr r3, [r7, #4] 8002648: 4a49 ldr r2, [pc, #292] @ (8002770 ) 800264a: 4293 cmp r3, r2 800264c: d101 bne.n 8002652 800264e: 2306 movs r3, #6 8002650: e00c b.n 800266c 8002652: 2307 movs r3, #7 8002654: e00a b.n 800266c 8002656: 2305 movs r3, #5 8002658: e008 b.n 800266c 800265a: 2304 movs r3, #4 800265c: e006 b.n 800266c 800265e: 2303 movs r3, #3 8002660: e004 b.n 800266c 8002662: 2302 movs r3, #2 8002664: e002 b.n 800266c 8002666: 2301 movs r3, #1 8002668: e000 b.n 800266c 800266a: 2300 movs r3, #0 800266c: 69fa ldr r2, [r7, #28] 800266e: f002 0203 and.w r2, r2, #3 8002672: 0092 lsls r2, r2, #2 8002674: 4093 lsls r3, r2 8002676: 69ba ldr r2, [r7, #24] 8002678: 4313 orrs r3, r2 800267a: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 800267c: 4935 ldr r1, [pc, #212] @ (8002754 ) 800267e: 69fb ldr r3, [r7, #28] 8002680: 089b lsrs r3, r3, #2 8002682: 3302 adds r3, #2 8002684: 69ba ldr r2, [r7, #24] 8002686: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 800268a: 4b3a ldr r3, [pc, #232] @ (8002774 ) 800268c: 689b ldr r3, [r3, #8] 800268e: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002690: 693b ldr r3, [r7, #16] 8002692: 43db mvns r3, r3 8002694: 69ba ldr r2, [r7, #24] 8002696: 4013 ands r3, r2 8002698: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800269a: 683b ldr r3, [r7, #0] 800269c: 685b ldr r3, [r3, #4] 800269e: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80026a2: 2b00 cmp r3, #0 80026a4: d003 beq.n 80026ae { temp |= iocurrent; 80026a6: 69ba ldr r2, [r7, #24] 80026a8: 693b ldr r3, [r7, #16] 80026aa: 4313 orrs r3, r2 80026ac: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 80026ae: 4a31 ldr r2, [pc, #196] @ (8002774 ) 80026b0: 69bb ldr r3, [r7, #24] 80026b2: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 80026b4: 4b2f ldr r3, [pc, #188] @ (8002774 ) 80026b6: 68db ldr r3, [r3, #12] 80026b8: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 80026ba: 693b ldr r3, [r7, #16] 80026bc: 43db mvns r3, r3 80026be: 69ba ldr r2, [r7, #24] 80026c0: 4013 ands r3, r2 80026c2: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 80026c4: 683b ldr r3, [r7, #0] 80026c6: 685b ldr r3, [r3, #4] 80026c8: f403 1300 and.w r3, r3, #2097152 @ 0x200000 80026cc: 2b00 cmp r3, #0 80026ce: d003 beq.n 80026d8 { temp |= iocurrent; 80026d0: 69ba ldr r2, [r7, #24] 80026d2: 693b ldr r3, [r7, #16] 80026d4: 4313 orrs r3, r2 80026d6: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 80026d8: 4a26 ldr r2, [pc, #152] @ (8002774 ) 80026da: 69bb ldr r3, [r7, #24] 80026dc: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 80026de: 4b25 ldr r3, [pc, #148] @ (8002774 ) 80026e0: 685b ldr r3, [r3, #4] 80026e2: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 80026e4: 693b ldr r3, [r7, #16] 80026e6: 43db mvns r3, r3 80026e8: 69ba ldr r2, [r7, #24] 80026ea: 4013 ands r3, r2 80026ec: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 80026ee: 683b ldr r3, [r7, #0] 80026f0: 685b ldr r3, [r3, #4] 80026f2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80026f6: 2b00 cmp r3, #0 80026f8: d003 beq.n 8002702 { temp |= iocurrent; 80026fa: 69ba ldr r2, [r7, #24] 80026fc: 693b ldr r3, [r7, #16] 80026fe: 4313 orrs r3, r2 8002700: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 8002702: 4a1c ldr r2, [pc, #112] @ (8002774 ) 8002704: 69bb ldr r3, [r7, #24] 8002706: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8002708: 4b1a ldr r3, [pc, #104] @ (8002774 ) 800270a: 681b ldr r3, [r3, #0] 800270c: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 800270e: 693b ldr r3, [r7, #16] 8002710: 43db mvns r3, r3 8002712: 69ba ldr r2, [r7, #24] 8002714: 4013 ands r3, r2 8002716: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8002718: 683b ldr r3, [r7, #0] 800271a: 685b ldr r3, [r3, #4] 800271c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8002720: 2b00 cmp r3, #0 8002722: d003 beq.n 800272c { temp |= iocurrent; 8002724: 69ba ldr r2, [r7, #24] 8002726: 693b ldr r3, [r7, #16] 8002728: 4313 orrs r3, r2 800272a: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 800272c: 4a11 ldr r2, [pc, #68] @ (8002774 ) 800272e: 69bb ldr r3, [r7, #24] 8002730: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 8002732: 69fb ldr r3, [r7, #28] 8002734: 3301 adds r3, #1 8002736: 61fb str r3, [r7, #28] 8002738: 69fb ldr r3, [r7, #28] 800273a: 2b0f cmp r3, #15 800273c: f67f ae96 bls.w 800246c } } } } 8002740: bf00 nop 8002742: bf00 nop 8002744: 3724 adds r7, #36 @ 0x24 8002746: 46bd mov sp, r7 8002748: f85d 7b04 ldr.w r7, [sp], #4 800274c: 4770 bx lr 800274e: bf00 nop 8002750: 40023800 .word 0x40023800 8002754: 40013800 .word 0x40013800 8002758: 40020000 .word 0x40020000 800275c: 40020400 .word 0x40020400 8002760: 40020800 .word 0x40020800 8002764: 40020c00 .word 0x40020c00 8002768: 40021000 .word 0x40021000 800276c: 40021400 .word 0x40021400 8002770: 40021800 .word 0x40021800 8002774: 40013c00 .word 0x40013c00 08002778 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8002778: b480 push {r7} 800277a: b085 sub sp, #20 800277c: af00 add r7, sp, #0 800277e: 6078 str r0, [r7, #4] 8002780: 460b mov r3, r1 8002782: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8002784: 687b ldr r3, [r7, #4] 8002786: 691a ldr r2, [r3, #16] 8002788: 887b ldrh r3, [r7, #2] 800278a: 4013 ands r3, r2 800278c: 2b00 cmp r3, #0 800278e: d002 beq.n 8002796 { bitstatus = GPIO_PIN_SET; 8002790: 2301 movs r3, #1 8002792: 73fb strb r3, [r7, #15] 8002794: e001 b.n 800279a } else { bitstatus = GPIO_PIN_RESET; 8002796: 2300 movs r3, #0 8002798: 73fb strb r3, [r7, #15] } return bitstatus; 800279a: 7bfb ldrb r3, [r7, #15] } 800279c: 4618 mov r0, r3 800279e: 3714 adds r7, #20 80027a0: 46bd mov sp, r7 80027a2: f85d 7b04 ldr.w r7, [sp], #4 80027a6: 4770 bx lr 080027a8 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80027a8: b480 push {r7} 80027aa: b083 sub sp, #12 80027ac: af00 add r7, sp, #0 80027ae: 6078 str r0, [r7, #4] 80027b0: 460b mov r3, r1 80027b2: 807b strh r3, [r7, #2] 80027b4: 4613 mov r3, r2 80027b6: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 80027b8: 787b ldrb r3, [r7, #1] 80027ba: 2b00 cmp r3, #0 80027bc: d003 beq.n 80027c6 { GPIOx->BSRR = GPIO_Pin; 80027be: 887a ldrh r2, [r7, #2] 80027c0: 687b ldr r3, [r7, #4] 80027c2: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 80027c4: e003 b.n 80027ce GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 80027c6: 887b ldrh r3, [r7, #2] 80027c8: 041a lsls r2, r3, #16 80027ca: 687b ldr r3, [r7, #4] 80027cc: 619a str r2, [r3, #24] } 80027ce: bf00 nop 80027d0: 370c adds r7, #12 80027d2: 46bd mov sp, r7 80027d4: f85d 7b04 ldr.w r7, [sp], #4 80027d8: 4770 bx lr ... 080027dc : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 80027dc: b580 push {r7, lr} 80027de: b084 sub sp, #16 80027e0: af00 add r7, sp, #0 80027e2: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 80027e4: 687b ldr r3, [r7, #4] 80027e6: 2b00 cmp r3, #0 80027e8: d101 bne.n 80027ee { return HAL_ERROR; 80027ea: 2301 movs r3, #1 80027ec: e12b b.n 8002a46 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 80027ee: 687b ldr r3, [r7, #4] 80027f0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80027f4: b2db uxtb r3, r3 80027f6: 2b00 cmp r3, #0 80027f8: d106 bne.n 8002808 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 80027fa: 687b ldr r3, [r7, #4] 80027fc: 2200 movs r2, #0 80027fe: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8002802: 6878 ldr r0, [r7, #4] 8002804: f7fd ffc8 bl 8000798 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8002808: 687b ldr r3, [r7, #4] 800280a: 2224 movs r2, #36 @ 0x24 800280c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8002810: 687b ldr r3, [r7, #4] 8002812: 681b ldr r3, [r3, #0] 8002814: 681a ldr r2, [r3, #0] 8002816: 687b ldr r3, [r7, #4] 8002818: 681b ldr r3, [r3, #0] 800281a: f022 0201 bic.w r2, r2, #1 800281e: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8002820: 687b ldr r3, [r7, #4] 8002822: 681b ldr r3, [r3, #0] 8002824: 681a ldr r2, [r3, #0] 8002826: 687b ldr r3, [r7, #4] 8002828: 681b ldr r3, [r3, #0] 800282a: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800282e: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 8002830: 687b ldr r3, [r7, #4] 8002832: 681b ldr r3, [r3, #0] 8002834: 681a ldr r2, [r3, #0] 8002836: 687b ldr r3, [r7, #4] 8002838: 681b ldr r3, [r3, #0] 800283a: f422 4200 bic.w r2, r2, #32768 @ 0x8000 800283e: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 8002840: f001 fc88 bl 8004154 8002844: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 8002846: 687b ldr r3, [r7, #4] 8002848: 685b ldr r3, [r3, #4] 800284a: 4a81 ldr r2, [pc, #516] @ (8002a50 ) 800284c: 4293 cmp r3, r2 800284e: d807 bhi.n 8002860 8002850: 68fb ldr r3, [r7, #12] 8002852: 4a80 ldr r2, [pc, #512] @ (8002a54 ) 8002854: 4293 cmp r3, r2 8002856: bf94 ite ls 8002858: 2301 movls r3, #1 800285a: 2300 movhi r3, #0 800285c: b2db uxtb r3, r3 800285e: e006 b.n 800286e 8002860: 68fb ldr r3, [r7, #12] 8002862: 4a7d ldr r2, [pc, #500] @ (8002a58 ) 8002864: 4293 cmp r3, r2 8002866: bf94 ite ls 8002868: 2301 movls r3, #1 800286a: 2300 movhi r3, #0 800286c: b2db uxtb r3, r3 800286e: 2b00 cmp r3, #0 8002870: d001 beq.n 8002876 { return HAL_ERROR; 8002872: 2301 movs r3, #1 8002874: e0e7 b.n 8002a46 } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 8002876: 68fb ldr r3, [r7, #12] 8002878: 4a78 ldr r2, [pc, #480] @ (8002a5c ) 800287a: fba2 2303 umull r2, r3, r2, r3 800287e: 0c9b lsrs r3, r3, #18 8002880: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8002882: 687b ldr r3, [r7, #4] 8002884: 681b ldr r3, [r3, #0] 8002886: 685b ldr r3, [r3, #4] 8002888: f023 013f bic.w r1, r3, #63 @ 0x3f 800288c: 687b ldr r3, [r7, #4] 800288e: 681b ldr r3, [r3, #0] 8002890: 68ba ldr r2, [r7, #8] 8002892: 430a orrs r2, r1 8002894: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 8002896: 687b ldr r3, [r7, #4] 8002898: 681b ldr r3, [r3, #0] 800289a: 6a1b ldr r3, [r3, #32] 800289c: f023 013f bic.w r1, r3, #63 @ 0x3f 80028a0: 687b ldr r3, [r7, #4] 80028a2: 685b ldr r3, [r3, #4] 80028a4: 4a6a ldr r2, [pc, #424] @ (8002a50 ) 80028a6: 4293 cmp r3, r2 80028a8: d802 bhi.n 80028b0 80028aa: 68bb ldr r3, [r7, #8] 80028ac: 3301 adds r3, #1 80028ae: e009 b.n 80028c4 80028b0: 68bb ldr r3, [r7, #8] 80028b2: f44f 7296 mov.w r2, #300 @ 0x12c 80028b6: fb02 f303 mul.w r3, r2, r3 80028ba: 4a69 ldr r2, [pc, #420] @ (8002a60 ) 80028bc: fba2 2303 umull r2, r3, r2, r3 80028c0: 099b lsrs r3, r3, #6 80028c2: 3301 adds r3, #1 80028c4: 687a ldr r2, [r7, #4] 80028c6: 6812 ldr r2, [r2, #0] 80028c8: 430b orrs r3, r1 80028ca: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 80028cc: 687b ldr r3, [r7, #4] 80028ce: 681b ldr r3, [r3, #0] 80028d0: 69db ldr r3, [r3, #28] 80028d2: f423 424f bic.w r2, r3, #52992 @ 0xcf00 80028d6: f022 02ff bic.w r2, r2, #255 @ 0xff 80028da: 687b ldr r3, [r7, #4] 80028dc: 685b ldr r3, [r3, #4] 80028de: 495c ldr r1, [pc, #368] @ (8002a50 ) 80028e0: 428b cmp r3, r1 80028e2: d819 bhi.n 8002918 80028e4: 68fb ldr r3, [r7, #12] 80028e6: 1e59 subs r1, r3, #1 80028e8: 687b ldr r3, [r7, #4] 80028ea: 685b ldr r3, [r3, #4] 80028ec: 005b lsls r3, r3, #1 80028ee: fbb1 f3f3 udiv r3, r1, r3 80028f2: 1c59 adds r1, r3, #1 80028f4: f640 73fc movw r3, #4092 @ 0xffc 80028f8: 400b ands r3, r1 80028fa: 2b00 cmp r3, #0 80028fc: d00a beq.n 8002914 80028fe: 68fb ldr r3, [r7, #12] 8002900: 1e59 subs r1, r3, #1 8002902: 687b ldr r3, [r7, #4] 8002904: 685b ldr r3, [r3, #4] 8002906: 005b lsls r3, r3, #1 8002908: fbb1 f3f3 udiv r3, r1, r3 800290c: 3301 adds r3, #1 800290e: f3c3 030b ubfx r3, r3, #0, #12 8002912: e051 b.n 80029b8 8002914: 2304 movs r3, #4 8002916: e04f b.n 80029b8 8002918: 687b ldr r3, [r7, #4] 800291a: 689b ldr r3, [r3, #8] 800291c: 2b00 cmp r3, #0 800291e: d111 bne.n 8002944 8002920: 68fb ldr r3, [r7, #12] 8002922: 1e58 subs r0, r3, #1 8002924: 687b ldr r3, [r7, #4] 8002926: 6859 ldr r1, [r3, #4] 8002928: 460b mov r3, r1 800292a: 005b lsls r3, r3, #1 800292c: 440b add r3, r1 800292e: fbb0 f3f3 udiv r3, r0, r3 8002932: 3301 adds r3, #1 8002934: f3c3 030b ubfx r3, r3, #0, #12 8002938: 2b00 cmp r3, #0 800293a: bf0c ite eq 800293c: 2301 moveq r3, #1 800293e: 2300 movne r3, #0 8002940: b2db uxtb r3, r3 8002942: e012 b.n 800296a 8002944: 68fb ldr r3, [r7, #12] 8002946: 1e58 subs r0, r3, #1 8002948: 687b ldr r3, [r7, #4] 800294a: 6859 ldr r1, [r3, #4] 800294c: 460b mov r3, r1 800294e: 009b lsls r3, r3, #2 8002950: 440b add r3, r1 8002952: 0099 lsls r1, r3, #2 8002954: 440b add r3, r1 8002956: fbb0 f3f3 udiv r3, r0, r3 800295a: 3301 adds r3, #1 800295c: f3c3 030b ubfx r3, r3, #0, #12 8002960: 2b00 cmp r3, #0 8002962: bf0c ite eq 8002964: 2301 moveq r3, #1 8002966: 2300 movne r3, #0 8002968: b2db uxtb r3, r3 800296a: 2b00 cmp r3, #0 800296c: d001 beq.n 8002972 800296e: 2301 movs r3, #1 8002970: e022 b.n 80029b8 8002972: 687b ldr r3, [r7, #4] 8002974: 689b ldr r3, [r3, #8] 8002976: 2b00 cmp r3, #0 8002978: d10e bne.n 8002998 800297a: 68fb ldr r3, [r7, #12] 800297c: 1e58 subs r0, r3, #1 800297e: 687b ldr r3, [r7, #4] 8002980: 6859 ldr r1, [r3, #4] 8002982: 460b mov r3, r1 8002984: 005b lsls r3, r3, #1 8002986: 440b add r3, r1 8002988: fbb0 f3f3 udiv r3, r0, r3 800298c: 3301 adds r3, #1 800298e: f3c3 030b ubfx r3, r3, #0, #12 8002992: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8002996: e00f b.n 80029b8 8002998: 68fb ldr r3, [r7, #12] 800299a: 1e58 subs r0, r3, #1 800299c: 687b ldr r3, [r7, #4] 800299e: 6859 ldr r1, [r3, #4] 80029a0: 460b mov r3, r1 80029a2: 009b lsls r3, r3, #2 80029a4: 440b add r3, r1 80029a6: 0099 lsls r1, r3, #2 80029a8: 440b add r3, r1 80029aa: fbb0 f3f3 udiv r3, r0, r3 80029ae: 3301 adds r3, #1 80029b0: f3c3 030b ubfx r3, r3, #0, #12 80029b4: f443 4340 orr.w r3, r3, #49152 @ 0xc000 80029b8: 6879 ldr r1, [r7, #4] 80029ba: 6809 ldr r1, [r1, #0] 80029bc: 4313 orrs r3, r2 80029be: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 80029c0: 687b ldr r3, [r7, #4] 80029c2: 681b ldr r3, [r3, #0] 80029c4: 681b ldr r3, [r3, #0] 80029c6: f023 01c0 bic.w r1, r3, #192 @ 0xc0 80029ca: 687b ldr r3, [r7, #4] 80029cc: 69da ldr r2, [r3, #28] 80029ce: 687b ldr r3, [r7, #4] 80029d0: 6a1b ldr r3, [r3, #32] 80029d2: 431a orrs r2, r3 80029d4: 687b ldr r3, [r7, #4] 80029d6: 681b ldr r3, [r3, #0] 80029d8: 430a orrs r2, r1 80029da: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 80029dc: 687b ldr r3, [r7, #4] 80029de: 681b ldr r3, [r3, #0] 80029e0: 689b ldr r3, [r3, #8] 80029e2: f423 4303 bic.w r3, r3, #33536 @ 0x8300 80029e6: f023 03ff bic.w r3, r3, #255 @ 0xff 80029ea: 687a ldr r2, [r7, #4] 80029ec: 6911 ldr r1, [r2, #16] 80029ee: 687a ldr r2, [r7, #4] 80029f0: 68d2 ldr r2, [r2, #12] 80029f2: 4311 orrs r1, r2 80029f4: 687a ldr r2, [r7, #4] 80029f6: 6812 ldr r2, [r2, #0] 80029f8: 430b orrs r3, r1 80029fa: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 80029fc: 687b ldr r3, [r7, #4] 80029fe: 681b ldr r3, [r3, #0] 8002a00: 68db ldr r3, [r3, #12] 8002a02: f023 01ff bic.w r1, r3, #255 @ 0xff 8002a06: 687b ldr r3, [r7, #4] 8002a08: 695a ldr r2, [r3, #20] 8002a0a: 687b ldr r3, [r7, #4] 8002a0c: 699b ldr r3, [r3, #24] 8002a0e: 431a orrs r2, r3 8002a10: 687b ldr r3, [r7, #4] 8002a12: 681b ldr r3, [r3, #0] 8002a14: 430a orrs r2, r1 8002a16: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002a18: 687b ldr r3, [r7, #4] 8002a1a: 681b ldr r3, [r3, #0] 8002a1c: 681a ldr r2, [r3, #0] 8002a1e: 687b ldr r3, [r7, #4] 8002a20: 681b ldr r3, [r3, #0] 8002a22: f042 0201 orr.w r2, r2, #1 8002a26: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002a28: 687b ldr r3, [r7, #4] 8002a2a: 2200 movs r2, #0 8002a2c: 641a str r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_READY; 8002a2e: 687b ldr r3, [r7, #4] 8002a30: 2220 movs r2, #32 8002a32: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->PreviousState = I2C_STATE_NONE; 8002a36: 687b ldr r3, [r7, #4] 8002a38: 2200 movs r2, #0 8002a3a: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8002a3c: 687b ldr r3, [r7, #4] 8002a3e: 2200 movs r2, #0 8002a40: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 8002a44: 2300 movs r3, #0 } 8002a46: 4618 mov r0, r3 8002a48: 3710 adds r7, #16 8002a4a: 46bd mov sp, r7 8002a4c: bd80 pop {r7, pc} 8002a4e: bf00 nop 8002a50: 000186a0 .word 0x000186a0 8002a54: 001e847f .word 0x001e847f 8002a58: 003d08ff .word 0x003d08ff 8002a5c: 431bde83 .word 0x431bde83 8002a60: 10624dd3 .word 0x10624dd3 08002a64 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8002a64: b580 push {r7, lr} 8002a66: b086 sub sp, #24 8002a68: af02 add r7, sp, #8 8002a6a: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx; #endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8002a6c: 687b ldr r3, [r7, #4] 8002a6e: 2b00 cmp r3, #0 8002a70: d101 bne.n 8002a76 { return HAL_ERROR; 8002a72: 2301 movs r3, #1 8002a74: e108 b.n 8002c88 /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); #if defined (USB_OTG_FS) USBx = hpcd->Instance; 8002a76: 687b ldr r3, [r7, #4] 8002a78: 681b ldr r3, [r3, #0] 8002a7a: 60bb str r3, [r7, #8] #endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) 8002a7c: 687b ldr r3, [r7, #4] 8002a7e: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495 8002a82: b2db uxtb r3, r3 8002a84: 2b00 cmp r3, #0 8002a86: d106 bne.n 8002a96 { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 8002a88: 687b ldr r3, [r7, #4] 8002a8a: 2200 movs r2, #0 8002a8c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8002a90: 6878 ldr r0, [r7, #4] 8002a92: f007 fc9f bl 800a3d4 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8002a96: 687b ldr r3, [r7, #4] 8002a98: 2203 movs r2, #3 8002a9a: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ if (USBx == USB_OTG_FS) 8002a9e: 68bb ldr r3, [r7, #8] 8002aa0: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002aa4: d102 bne.n 8002aac { hpcd->Init.dma_enable = 0U; 8002aa6: 687b ldr r3, [r7, #4] 8002aa8: 2200 movs r2, #0 8002aaa: 719a strb r2, [r3, #6] } #endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8002aac: 687b ldr r3, [r7, #4] 8002aae: 681b ldr r3, [r3, #0] 8002ab0: 4618 mov r0, r3 8002ab2: f004 fb94 bl 80071de /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002ab6: 687b ldr r3, [r7, #4] 8002ab8: 6818 ldr r0, [r3, #0] 8002aba: 687b ldr r3, [r7, #4] 8002abc: 7c1a ldrb r2, [r3, #16] 8002abe: f88d 2000 strb.w r2, [sp] 8002ac2: 3304 adds r3, #4 8002ac4: cb0e ldmia r3, {r1, r2, r3} 8002ac6: f004 fa73 bl 8006fb0 8002aca: 4603 mov r3, r0 8002acc: 2b00 cmp r3, #0 8002ace: d005 beq.n 8002adc { hpcd->State = HAL_PCD_STATE_ERROR; 8002ad0: 687b ldr r3, [r7, #4] 8002ad2: 2202 movs r2, #2 8002ad4: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002ad8: 2301 movs r3, #1 8002ada: e0d5 b.n 8002c88 } /* Force Device Mode */ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) 8002adc: 687b ldr r3, [r7, #4] 8002ade: 681b ldr r3, [r3, #0] 8002ae0: 2100 movs r1, #0 8002ae2: 4618 mov r0, r3 8002ae4: f004 fb8c bl 8007200 8002ae8: 4603 mov r3, r0 8002aea: 2b00 cmp r3, #0 8002aec: d005 beq.n 8002afa { hpcd->State = HAL_PCD_STATE_ERROR; 8002aee: 687b ldr r3, [r7, #4] 8002af0: 2202 movs r2, #2 8002af2: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002af6: 2301 movs r3, #1 8002af8: e0c6 b.n 8002c88 } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002afa: 2300 movs r3, #0 8002afc: 73fb strb r3, [r7, #15] 8002afe: e04a b.n 8002b96 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8002b00: 7bfa ldrb r2, [r7, #15] 8002b02: 6879 ldr r1, [r7, #4] 8002b04: 4613 mov r3, r2 8002b06: 00db lsls r3, r3, #3 8002b08: 4413 add r3, r2 8002b0a: 009b lsls r3, r3, #2 8002b0c: 440b add r3, r1 8002b0e: 3315 adds r3, #21 8002b10: 2201 movs r2, #1 8002b12: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8002b14: 7bfa ldrb r2, [r7, #15] 8002b16: 6879 ldr r1, [r7, #4] 8002b18: 4613 mov r3, r2 8002b1a: 00db lsls r3, r3, #3 8002b1c: 4413 add r3, r2 8002b1e: 009b lsls r3, r3, #2 8002b20: 440b add r3, r1 8002b22: 3314 adds r3, #20 8002b24: 7bfa ldrb r2, [r7, #15] 8002b26: 701a strb r2, [r3, #0] hpcd->IN_ep[i].tx_fifo_num = i; 8002b28: 7bfa ldrb r2, [r7, #15] 8002b2a: 7bfb ldrb r3, [r7, #15] 8002b2c: b298 uxth r0, r3 8002b2e: 6879 ldr r1, [r7, #4] 8002b30: 4613 mov r3, r2 8002b32: 00db lsls r3, r3, #3 8002b34: 4413 add r3, r2 8002b36: 009b lsls r3, r3, #2 8002b38: 440b add r3, r1 8002b3a: 332e adds r3, #46 @ 0x2e 8002b3c: 4602 mov r2, r0 8002b3e: 801a strh r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 8002b40: 7bfa ldrb r2, [r7, #15] 8002b42: 6879 ldr r1, [r7, #4] 8002b44: 4613 mov r3, r2 8002b46: 00db lsls r3, r3, #3 8002b48: 4413 add r3, r2 8002b4a: 009b lsls r3, r3, #2 8002b4c: 440b add r3, r1 8002b4e: 3318 adds r3, #24 8002b50: 2200 movs r2, #0 8002b52: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8002b54: 7bfa ldrb r2, [r7, #15] 8002b56: 6879 ldr r1, [r7, #4] 8002b58: 4613 mov r3, r2 8002b5a: 00db lsls r3, r3, #3 8002b5c: 4413 add r3, r2 8002b5e: 009b lsls r3, r3, #2 8002b60: 440b add r3, r1 8002b62: 331c adds r3, #28 8002b64: 2200 movs r2, #0 8002b66: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 8002b68: 7bfa ldrb r2, [r7, #15] 8002b6a: 6879 ldr r1, [r7, #4] 8002b6c: 4613 mov r3, r2 8002b6e: 00db lsls r3, r3, #3 8002b70: 4413 add r3, r2 8002b72: 009b lsls r3, r3, #2 8002b74: 440b add r3, r1 8002b76: 3320 adds r3, #32 8002b78: 2200 movs r2, #0 8002b7a: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 8002b7c: 7bfa ldrb r2, [r7, #15] 8002b7e: 6879 ldr r1, [r7, #4] 8002b80: 4613 mov r3, r2 8002b82: 00db lsls r3, r3, #3 8002b84: 4413 add r3, r2 8002b86: 009b lsls r3, r3, #2 8002b88: 440b add r3, r1 8002b8a: 3324 adds r3, #36 @ 0x24 8002b8c: 2200 movs r2, #0 8002b8e: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002b90: 7bfb ldrb r3, [r7, #15] 8002b92: 3301 adds r3, #1 8002b94: 73fb strb r3, [r7, #15] 8002b96: 687b ldr r3, [r7, #4] 8002b98: 791b ldrb r3, [r3, #4] 8002b9a: 7bfa ldrb r2, [r7, #15] 8002b9c: 429a cmp r2, r3 8002b9e: d3af bcc.n 8002b00 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002ba0: 2300 movs r3, #0 8002ba2: 73fb strb r3, [r7, #15] 8002ba4: e044 b.n 8002c30 { hpcd->OUT_ep[i].is_in = 0U; 8002ba6: 7bfa ldrb r2, [r7, #15] 8002ba8: 6879 ldr r1, [r7, #4] 8002baa: 4613 mov r3, r2 8002bac: 00db lsls r3, r3, #3 8002bae: 4413 add r3, r2 8002bb0: 009b lsls r3, r3, #2 8002bb2: 440b add r3, r1 8002bb4: f203 2355 addw r3, r3, #597 @ 0x255 8002bb8: 2200 movs r2, #0 8002bba: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 8002bbc: 7bfa ldrb r2, [r7, #15] 8002bbe: 6879 ldr r1, [r7, #4] 8002bc0: 4613 mov r3, r2 8002bc2: 00db lsls r3, r3, #3 8002bc4: 4413 add r3, r2 8002bc6: 009b lsls r3, r3, #2 8002bc8: 440b add r3, r1 8002bca: f503 7315 add.w r3, r3, #596 @ 0x254 8002bce: 7bfa ldrb r2, [r7, #15] 8002bd0: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8002bd2: 7bfa ldrb r2, [r7, #15] 8002bd4: 6879 ldr r1, [r7, #4] 8002bd6: 4613 mov r3, r2 8002bd8: 00db lsls r3, r3, #3 8002bda: 4413 add r3, r2 8002bdc: 009b lsls r3, r3, #2 8002bde: 440b add r3, r1 8002be0: f503 7316 add.w r3, r3, #600 @ 0x258 8002be4: 2200 movs r2, #0 8002be6: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8002be8: 7bfa ldrb r2, [r7, #15] 8002bea: 6879 ldr r1, [r7, #4] 8002bec: 4613 mov r3, r2 8002bee: 00db lsls r3, r3, #3 8002bf0: 4413 add r3, r2 8002bf2: 009b lsls r3, r3, #2 8002bf4: 440b add r3, r1 8002bf6: f503 7317 add.w r3, r3, #604 @ 0x25c 8002bfa: 2200 movs r2, #0 8002bfc: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 8002bfe: 7bfa ldrb r2, [r7, #15] 8002c00: 6879 ldr r1, [r7, #4] 8002c02: 4613 mov r3, r2 8002c04: 00db lsls r3, r3, #3 8002c06: 4413 add r3, r2 8002c08: 009b lsls r3, r3, #2 8002c0a: 440b add r3, r1 8002c0c: f503 7318 add.w r3, r3, #608 @ 0x260 8002c10: 2200 movs r2, #0 8002c12: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8002c14: 7bfa ldrb r2, [r7, #15] 8002c16: 6879 ldr r1, [r7, #4] 8002c18: 4613 mov r3, r2 8002c1a: 00db lsls r3, r3, #3 8002c1c: 4413 add r3, r2 8002c1e: 009b lsls r3, r3, #2 8002c20: 440b add r3, r1 8002c22: f503 7319 add.w r3, r3, #612 @ 0x264 8002c26: 2200 movs r2, #0 8002c28: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002c2a: 7bfb ldrb r3, [r7, #15] 8002c2c: 3301 adds r3, #1 8002c2e: 73fb strb r3, [r7, #15] 8002c30: 687b ldr r3, [r7, #4] 8002c32: 791b ldrb r3, [r3, #4] 8002c34: 7bfa ldrb r2, [r7, #15] 8002c36: 429a cmp r2, r3 8002c38: d3b5 bcc.n 8002ba6 } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002c3a: 687b ldr r3, [r7, #4] 8002c3c: 6818 ldr r0, [r3, #0] 8002c3e: 687b ldr r3, [r7, #4] 8002c40: 7c1a ldrb r2, [r3, #16] 8002c42: f88d 2000 strb.w r2, [sp] 8002c46: 3304 adds r3, #4 8002c48: cb0e ldmia r3, {r1, r2, r3} 8002c4a: f004 fb25 bl 8007298 8002c4e: 4603 mov r3, r0 8002c50: 2b00 cmp r3, #0 8002c52: d005 beq.n 8002c60 { hpcd->State = HAL_PCD_STATE_ERROR; 8002c54: 687b ldr r3, [r7, #4] 8002c56: 2202 movs r2, #2 8002c58: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002c5c: 2301 movs r3, #1 8002c5e: e013 b.n 8002c88 } hpcd->USB_Address = 0U; 8002c60: 687b ldr r3, [r7, #4] 8002c62: 2200 movs r2, #0 8002c64: 745a strb r2, [r3, #17] hpcd->State = HAL_PCD_STATE_READY; 8002c66: 687b ldr r3, [r7, #4] 8002c68: 2201 movs r2, #1 8002c6a: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 8002c6e: 687b ldr r3, [r7, #4] 8002c70: 7b1b ldrb r3, [r3, #12] 8002c72: 2b01 cmp r3, #1 8002c74: d102 bne.n 8002c7c { (void)HAL_PCDEx_ActivateLPM(hpcd); 8002c76: 6878 ldr r0, [r7, #4] 8002c78: f001 f956 bl 8003f28 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); 8002c7c: 687b ldr r3, [r7, #4] 8002c7e: 681b ldr r3, [r3, #0] 8002c80: 4618 mov r0, r3 8002c82: f005 fb62 bl 800834a return HAL_OK; 8002c86: 2300 movs r3, #0 } 8002c88: 4618 mov r0, r3 8002c8a: 3710 adds r7, #16 8002c8c: 46bd mov sp, r7 8002c8e: bd80 pop {r7, pc} 08002c90 : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 8002c90: b580 push {r7, lr} 8002c92: b084 sub sp, #16 8002c94: af00 add r7, sp, #0 8002c96: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002c98: 687b ldr r3, [r7, #4] 8002c9a: 681b ldr r3, [r3, #0] 8002c9c: 60fb str r3, [r7, #12] __HAL_LOCK(hpcd); 8002c9e: 687b ldr r3, [r7, #4] 8002ca0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8002ca4: 2b01 cmp r3, #1 8002ca6: d101 bne.n 8002cac 8002ca8: 2302 movs r3, #2 8002caa: e022 b.n 8002cf2 8002cac: 687b ldr r3, [r7, #4] 8002cae: 2201 movs r2, #1 8002cb0: f883 2494 strb.w r2, [r3, #1172] @ 0x494 if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8002cb4: 68fb ldr r3, [r7, #12] 8002cb6: 68db ldr r3, [r3, #12] 8002cb8: f003 0340 and.w r3, r3, #64 @ 0x40 8002cbc: 2b00 cmp r3, #0 8002cbe: d009 beq.n 8002cd4 (hpcd->Init.battery_charging_enable == 1U)) 8002cc0: 687b ldr r3, [r7, #4] 8002cc2: 7b5b ldrb r3, [r3, #13] if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8002cc4: 2b01 cmp r3, #1 8002cc6: d105 bne.n 8002cd4 { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8002cc8: 68fb ldr r3, [r7, #12] 8002cca: 6b9b ldr r3, [r3, #56] @ 0x38 8002ccc: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8002cd0: 68fb ldr r3, [r7, #12] 8002cd2: 639a str r2, [r3, #56] @ 0x38 } __HAL_PCD_ENABLE(hpcd); 8002cd4: 687b ldr r3, [r7, #4] 8002cd6: 681b ldr r3, [r3, #0] 8002cd8: 4618 mov r0, r3 8002cda: f004 fa6f bl 80071bc (void)USB_DevConnect(hpcd->Instance); 8002cde: 687b ldr r3, [r7, #4] 8002ce0: 681b ldr r3, [r3, #0] 8002ce2: 4618 mov r0, r3 8002ce4: f005 fb10 bl 8008308 __HAL_UNLOCK(hpcd); 8002ce8: 687b ldr r3, [r7, #4] 8002cea: 2200 movs r2, #0 8002cec: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8002cf0: 2300 movs r3, #0 } 8002cf2: 4618 mov r0, r3 8002cf4: 3710 adds r7, #16 8002cf6: 46bd mov sp, r7 8002cf8: bd80 pop {r7, pc} 08002cfa : * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 8002cfa: b590 push {r4, r7, lr} 8002cfc: b08d sub sp, #52 @ 0x34 8002cfe: af00 add r7, sp, #0 8002d00: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002d02: 687b ldr r3, [r7, #4] 8002d04: 681b ldr r3, [r3, #0] 8002d06: 623b str r3, [r7, #32] uint32_t USBx_BASE = (uint32_t)USBx; 8002d08: 6a3b ldr r3, [r7, #32] 8002d0a: 61fb str r3, [r7, #28] uint32_t epnum; uint32_t fifoemptymsk; uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) 8002d0c: 687b ldr r3, [r7, #4] 8002d0e: 681b ldr r3, [r3, #0] 8002d10: 4618 mov r0, r3 8002d12: f005 fbce bl 80084b2 8002d16: 4603 mov r3, r0 8002d18: 2b00 cmp r3, #0 8002d1a: f040 84b9 bne.w 8003690 { /* avoid spurious interrupt */ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 8002d1e: 687b ldr r3, [r7, #4] 8002d20: 681b ldr r3, [r3, #0] 8002d22: 4618 mov r0, r3 8002d24: f005 fb32 bl 800838c 8002d28: 4603 mov r3, r0 8002d2a: 2b00 cmp r3, #0 8002d2c: f000 84af beq.w 800368e { return; } /* store current frame number */ hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; 8002d30: 69fb ldr r3, [r7, #28] 8002d32: f503 6300 add.w r3, r3, #2048 @ 0x800 8002d36: 689b ldr r3, [r3, #8] 8002d38: 0a1b lsrs r3, r3, #8 8002d3a: f3c3 020d ubfx r2, r3, #0, #14 8002d3e: 687b ldr r3, [r7, #4] 8002d40: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4 if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) 8002d44: 687b ldr r3, [r7, #4] 8002d46: 681b ldr r3, [r3, #0] 8002d48: 4618 mov r0, r3 8002d4a: f005 fb1f bl 800838c 8002d4e: 4603 mov r3, r0 8002d50: f003 0302 and.w r3, r3, #2 8002d54: 2b02 cmp r3, #2 8002d56: d107 bne.n 8002d68 { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); 8002d58: 687b ldr r3, [r7, #4] 8002d5a: 681b ldr r3, [r3, #0] 8002d5c: 695a ldr r2, [r3, #20] 8002d5e: 687b ldr r3, [r7, #4] 8002d60: 681b ldr r3, [r3, #0] 8002d62: f002 0202 and.w r2, r2, #2 8002d66: 615a str r2, [r3, #20] } /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) 8002d68: 687b ldr r3, [r7, #4] 8002d6a: 681b ldr r3, [r3, #0] 8002d6c: 4618 mov r0, r3 8002d6e: f005 fb0d bl 800838c 8002d72: 4603 mov r3, r0 8002d74: f003 0310 and.w r3, r3, #16 8002d78: 2b10 cmp r3, #16 8002d7a: d161 bne.n 8002e40 { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002d7c: 687b ldr r3, [r7, #4] 8002d7e: 681b ldr r3, [r3, #0] 8002d80: 699a ldr r2, [r3, #24] 8002d82: 687b ldr r3, [r7, #4] 8002d84: 681b ldr r3, [r3, #0] 8002d86: f022 0210 bic.w r2, r2, #16 8002d8a: 619a str r2, [r3, #24] RegVal = USBx->GRXSTSP; 8002d8c: 6a3b ldr r3, [r7, #32] 8002d8e: 6a1b ldr r3, [r3, #32] 8002d90: 61bb str r3, [r7, #24] ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; 8002d92: 69bb ldr r3, [r7, #24] 8002d94: f003 020f and.w r2, r3, #15 8002d98: 4613 mov r3, r2 8002d9a: 00db lsls r3, r3, #3 8002d9c: 4413 add r3, r2 8002d9e: 009b lsls r3, r3, #2 8002da0: f503 7314 add.w r3, r3, #592 @ 0x250 8002da4: 687a ldr r2, [r7, #4] 8002da6: 4413 add r3, r2 8002da8: 3304 adds r3, #4 8002daa: 617b str r3, [r7, #20] if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) 8002dac: 69bb ldr r3, [r7, #24] 8002dae: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8002db2: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8002db6: d124 bne.n 8002e02 { if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) 8002db8: 69ba ldr r2, [r7, #24] 8002dba: f647 73f0 movw r3, #32752 @ 0x7ff0 8002dbe: 4013 ands r3, r2 8002dc0: 2b00 cmp r3, #0 8002dc2: d035 beq.n 8002e30 { (void)USB_ReadPacket(USBx, ep->xfer_buff, 8002dc4: 697b ldr r3, [r7, #20] 8002dc6: 68d9 ldr r1, [r3, #12] (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); 8002dc8: 69bb ldr r3, [r7, #24] 8002dca: 091b lsrs r3, r3, #4 8002dcc: b29b uxth r3, r3 (void)USB_ReadPacket(USBx, ep->xfer_buff, 8002dce: f3c3 030a ubfx r3, r3, #0, #11 8002dd2: b29b uxth r3, r3 8002dd4: 461a mov r2, r3 8002dd6: 6a38 ldr r0, [r7, #32] 8002dd8: f005 f944 bl 8008064 ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002ddc: 697b ldr r3, [r7, #20] 8002dde: 68da ldr r2, [r3, #12] 8002de0: 69bb ldr r3, [r7, #24] 8002de2: 091b lsrs r3, r3, #4 8002de4: f3c3 030a ubfx r3, r3, #0, #11 8002de8: 441a add r2, r3 8002dea: 697b ldr r3, [r7, #20] 8002dec: 60da str r2, [r3, #12] ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002dee: 697b ldr r3, [r7, #20] 8002df0: 695a ldr r2, [r3, #20] 8002df2: 69bb ldr r3, [r7, #24] 8002df4: 091b lsrs r3, r3, #4 8002df6: f3c3 030a ubfx r3, r3, #0, #11 8002dfa: 441a add r2, r3 8002dfc: 697b ldr r3, [r7, #20] 8002dfe: 615a str r2, [r3, #20] 8002e00: e016 b.n 8002e30 } } else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) 8002e02: 69bb ldr r3, [r7, #24] 8002e04: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8002e08: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8002e0c: d110 bne.n 8002e30 { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); 8002e0e: 687b ldr r3, [r7, #4] 8002e10: f203 439c addw r3, r3, #1180 @ 0x49c 8002e14: 2208 movs r2, #8 8002e16: 4619 mov r1, r3 8002e18: 6a38 ldr r0, [r7, #32] 8002e1a: f005 f923 bl 8008064 ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002e1e: 697b ldr r3, [r7, #20] 8002e20: 695a ldr r2, [r3, #20] 8002e22: 69bb ldr r3, [r7, #24] 8002e24: 091b lsrs r3, r3, #4 8002e26: f3c3 030a ubfx r3, r3, #0, #11 8002e2a: 441a add r2, r3 8002e2c: 697b ldr r3, [r7, #20] 8002e2e: 615a str r2, [r3, #20] else { /* ... */ } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002e30: 687b ldr r3, [r7, #4] 8002e32: 681b ldr r3, [r3, #0] 8002e34: 699a ldr r2, [r3, #24] 8002e36: 687b ldr r3, [r7, #4] 8002e38: 681b ldr r3, [r3, #0] 8002e3a: f042 0210 orr.w r2, r2, #16 8002e3e: 619a str r2, [r3, #24] } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) 8002e40: 687b ldr r3, [r7, #4] 8002e42: 681b ldr r3, [r3, #0] 8002e44: 4618 mov r0, r3 8002e46: f005 faa1 bl 800838c 8002e4a: 4603 mov r3, r0 8002e4c: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002e50: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8002e54: f040 80a7 bne.w 8002fa6 { epnum = 0U; 8002e58: 2300 movs r3, #0 8002e5a: 627b str r3, [r7, #36] @ 0x24 /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); 8002e5c: 687b ldr r3, [r7, #4] 8002e5e: 681b ldr r3, [r3, #0] 8002e60: 4618 mov r0, r3 8002e62: f005 faa6 bl 80083b2 8002e66: 62b8 str r0, [r7, #40] @ 0x28 while (ep_intr != 0U) 8002e68: e099 b.n 8002f9e { if ((ep_intr & 0x1U) != 0U) 8002e6a: 6abb ldr r3, [r7, #40] @ 0x28 8002e6c: f003 0301 and.w r3, r3, #1 8002e70: 2b00 cmp r3, #0 8002e72: f000 808e beq.w 8002f92 { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8002e76: 687b ldr r3, [r7, #4] 8002e78: 681b ldr r3, [r3, #0] 8002e7a: 6a7a ldr r2, [r7, #36] @ 0x24 8002e7c: b2d2 uxtb r2, r2 8002e7e: 4611 mov r1, r2 8002e80: 4618 mov r0, r3 8002e82: f005 faca bl 800841a 8002e86: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) 8002e88: 693b ldr r3, [r7, #16] 8002e8a: f003 0301 and.w r3, r3, #1 8002e8e: 2b00 cmp r3, #0 8002e90: d00c beq.n 8002eac { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); 8002e92: 6a7b ldr r3, [r7, #36] @ 0x24 8002e94: 015a lsls r2, r3, #5 8002e96: 69fb ldr r3, [r7, #28] 8002e98: 4413 add r3, r2 8002e9a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002e9e: 461a mov r2, r3 8002ea0: 2301 movs r3, #1 8002ea2: 6093 str r3, [r2, #8] (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); 8002ea4: 6a79 ldr r1, [r7, #36] @ 0x24 8002ea6: 6878 ldr r0, [r7, #4] 8002ea8: f000 feb8 bl 8003c1c } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) 8002eac: 693b ldr r3, [r7, #16] 8002eae: f003 0308 and.w r3, r3, #8 8002eb2: 2b00 cmp r3, #0 8002eb4: d00c beq.n 8002ed0 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); 8002eb6: 6a7b ldr r3, [r7, #36] @ 0x24 8002eb8: 015a lsls r2, r3, #5 8002eba: 69fb ldr r3, [r7, #28] 8002ebc: 4413 add r3, r2 8002ebe: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002ec2: 461a mov r2, r3 8002ec4: 2308 movs r3, #8 8002ec6: 6093 str r3, [r2, #8] /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); 8002ec8: 6a79 ldr r1, [r7, #36] @ 0x24 8002eca: 6878 ldr r0, [r7, #4] 8002ecc: f000 ff8e bl 8003dec } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) 8002ed0: 693b ldr r3, [r7, #16] 8002ed2: f003 0310 and.w r3, r3, #16 8002ed6: 2b00 cmp r3, #0 8002ed8: d008 beq.n 8002eec { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); 8002eda: 6a7b ldr r3, [r7, #36] @ 0x24 8002edc: 015a lsls r2, r3, #5 8002ede: 69fb ldr r3, [r7, #28] 8002ee0: 4413 add r3, r2 8002ee2: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002ee6: 461a mov r2, r3 8002ee8: 2310 movs r3, #16 8002eea: 6093 str r3, [r2, #8] } /* Clear OUT Endpoint disable interrupt */ if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) 8002eec: 693b ldr r3, [r7, #16] 8002eee: f003 0302 and.w r3, r3, #2 8002ef2: 2b00 cmp r3, #0 8002ef4: d030 beq.n 8002f58 { if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) 8002ef6: 6a3b ldr r3, [r7, #32] 8002ef8: 695b ldr r3, [r3, #20] 8002efa: f003 0380 and.w r3, r3, #128 @ 0x80 8002efe: 2b80 cmp r3, #128 @ 0x80 8002f00: d109 bne.n 8002f16 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; 8002f02: 69fb ldr r3, [r7, #28] 8002f04: f503 6300 add.w r3, r3, #2048 @ 0x800 8002f08: 685b ldr r3, [r3, #4] 8002f0a: 69fa ldr r2, [r7, #28] 8002f0c: f502 6200 add.w r2, r2, #2048 @ 0x800 8002f10: f443 6380 orr.w r3, r3, #1024 @ 0x400 8002f14: 6053 str r3, [r2, #4] } ep = &hpcd->OUT_ep[epnum]; 8002f16: 6a7a ldr r2, [r7, #36] @ 0x24 8002f18: 4613 mov r3, r2 8002f1a: 00db lsls r3, r3, #3 8002f1c: 4413 add r3, r2 8002f1e: 009b lsls r3, r3, #2 8002f20: f503 7314 add.w r3, r3, #592 @ 0x250 8002f24: 687a ldr r2, [r7, #4] 8002f26: 4413 add r3, r2 8002f28: 3304 adds r3, #4 8002f2a: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 8002f2c: 697b ldr r3, [r7, #20] 8002f2e: 78db ldrb r3, [r3, #3] 8002f30: 2b01 cmp r3, #1 8002f32: d108 bne.n 8002f46 { ep->is_iso_incomplete = 0U; 8002f34: 697b ldr r3, [r7, #20] 8002f36: 2200 movs r2, #0 8002f38: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); 8002f3a: 6a7b ldr r3, [r7, #36] @ 0x24 8002f3c: b2db uxtb r3, r3 8002f3e: 4619 mov r1, r3 8002f40: 6878 ldr r0, [r7, #4] 8002f42: f007 fb63 bl 800a60c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); 8002f46: 6a7b ldr r3, [r7, #36] @ 0x24 8002f48: 015a lsls r2, r3, #5 8002f4a: 69fb ldr r3, [r7, #28] 8002f4c: 4413 add r3, r2 8002f4e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002f52: 461a mov r2, r3 8002f54: 2302 movs r3, #2 8002f56: 6093 str r3, [r2, #8] } /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8002f58: 693b ldr r3, [r7, #16] 8002f5a: f003 0320 and.w r3, r3, #32 8002f5e: 2b00 cmp r3, #0 8002f60: d008 beq.n 8002f74 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8002f62: 6a7b ldr r3, [r7, #36] @ 0x24 8002f64: 015a lsls r2, r3, #5 8002f66: 69fb ldr r3, [r7, #28] 8002f68: 4413 add r3, r2 8002f6a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002f6e: 461a mov r2, r3 8002f70: 2320 movs r3, #32 8002f72: 6093 str r3, [r2, #8] } /* Clear OUT NAK interrupt */ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) 8002f74: 693b ldr r3, [r7, #16] 8002f76: f403 5300 and.w r3, r3, #8192 @ 0x2000 8002f7a: 2b00 cmp r3, #0 8002f7c: d009 beq.n 8002f92 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); 8002f7e: 6a7b ldr r3, [r7, #36] @ 0x24 8002f80: 015a lsls r2, r3, #5 8002f82: 69fb ldr r3, [r7, #28] 8002f84: 4413 add r3, r2 8002f86: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002f8a: 461a mov r2, r3 8002f8c: f44f 5300 mov.w r3, #8192 @ 0x2000 8002f90: 6093 str r3, [r2, #8] } } epnum++; 8002f92: 6a7b ldr r3, [r7, #36] @ 0x24 8002f94: 3301 adds r3, #1 8002f96: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 8002f98: 6abb ldr r3, [r7, #40] @ 0x28 8002f9a: 085b lsrs r3, r3, #1 8002f9c: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 8002f9e: 6abb ldr r3, [r7, #40] @ 0x28 8002fa0: 2b00 cmp r3, #0 8002fa2: f47f af62 bne.w 8002e6a } } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) 8002fa6: 687b ldr r3, [r7, #4] 8002fa8: 681b ldr r3, [r3, #0] 8002faa: 4618 mov r0, r3 8002fac: f005 f9ee bl 800838c 8002fb0: 4603 mov r3, r0 8002fb2: f403 2380 and.w r3, r3, #262144 @ 0x40000 8002fb6: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8002fba: f040 80db bne.w 8003174 { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); 8002fbe: 687b ldr r3, [r7, #4] 8002fc0: 681b ldr r3, [r3, #0] 8002fc2: 4618 mov r0, r3 8002fc4: f005 fa0f bl 80083e6 8002fc8: 62b8 str r0, [r7, #40] @ 0x28 epnum = 0U; 8002fca: 2300 movs r3, #0 8002fcc: 627b str r3, [r7, #36] @ 0x24 while (ep_intr != 0U) 8002fce: e0cd b.n 800316c { if ((ep_intr & 0x1U) != 0U) /* In ITR */ 8002fd0: 6abb ldr r3, [r7, #40] @ 0x28 8002fd2: f003 0301 and.w r3, r3, #1 8002fd6: 2b00 cmp r3, #0 8002fd8: f000 80c2 beq.w 8003160 { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8002fdc: 687b ldr r3, [r7, #4] 8002fde: 681b ldr r3, [r3, #0] 8002fe0: 6a7a ldr r2, [r7, #36] @ 0x24 8002fe2: b2d2 uxtb r2, r2 8002fe4: 4611 mov r1, r2 8002fe6: 4618 mov r0, r3 8002fe8: f005 fa35 bl 8008456 8002fec: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) 8002fee: 693b ldr r3, [r7, #16] 8002ff0: f003 0301 and.w r3, r3, #1 8002ff4: 2b00 cmp r3, #0 8002ff6: d057 beq.n 80030a8 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8002ff8: 6a7b ldr r3, [r7, #36] @ 0x24 8002ffa: f003 030f and.w r3, r3, #15 8002ffe: 2201 movs r2, #1 8003000: fa02 f303 lsl.w r3, r2, r3 8003004: 60fb str r3, [r7, #12] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8003006: 69fb ldr r3, [r7, #28] 8003008: f503 6300 add.w r3, r3, #2048 @ 0x800 800300c: 6b5a ldr r2, [r3, #52] @ 0x34 800300e: 68fb ldr r3, [r7, #12] 8003010: 43db mvns r3, r3 8003012: 69f9 ldr r1, [r7, #28] 8003014: f501 6100 add.w r1, r1, #2048 @ 0x800 8003018: 4013 ands r3, r2 800301a: 634b str r3, [r1, #52] @ 0x34 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); 800301c: 6a7b ldr r3, [r7, #36] @ 0x24 800301e: 015a lsls r2, r3, #5 8003020: 69fb ldr r3, [r7, #28] 8003022: 4413 add r3, r2 8003024: f503 6310 add.w r3, r3, #2304 @ 0x900 8003028: 461a mov r2, r3 800302a: 2301 movs r3, #1 800302c: 6093 str r3, [r2, #8] if (hpcd->Init.dma_enable == 1U) 800302e: 687b ldr r3, [r7, #4] 8003030: 799b ldrb r3, [r3, #6] 8003032: 2b01 cmp r3, #1 8003034: d132 bne.n 800309c { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 8003036: 6879 ldr r1, [r7, #4] 8003038: 6a7a ldr r2, [r7, #36] @ 0x24 800303a: 4613 mov r3, r2 800303c: 00db lsls r3, r3, #3 800303e: 4413 add r3, r2 8003040: 009b lsls r3, r3, #2 8003042: 440b add r3, r1 8003044: 3320 adds r3, #32 8003046: 6819 ldr r1, [r3, #0] 8003048: 6878 ldr r0, [r7, #4] 800304a: 6a7a ldr r2, [r7, #36] @ 0x24 800304c: 4613 mov r3, r2 800304e: 00db lsls r3, r3, #3 8003050: 4413 add r3, r2 8003052: 009b lsls r3, r3, #2 8003054: 4403 add r3, r0 8003056: 331c adds r3, #28 8003058: 681b ldr r3, [r3, #0] 800305a: 4419 add r1, r3 800305c: 6878 ldr r0, [r7, #4] 800305e: 6a7a ldr r2, [r7, #36] @ 0x24 8003060: 4613 mov r3, r2 8003062: 00db lsls r3, r3, #3 8003064: 4413 add r3, r2 8003066: 009b lsls r3, r3, #2 8003068: 4403 add r3, r0 800306a: 3320 adds r3, #32 800306c: 6019 str r1, [r3, #0] /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) 800306e: 6a7b ldr r3, [r7, #36] @ 0x24 8003070: 2b00 cmp r3, #0 8003072: d113 bne.n 800309c 8003074: 6879 ldr r1, [r7, #4] 8003076: 6a7a ldr r2, [r7, #36] @ 0x24 8003078: 4613 mov r3, r2 800307a: 00db lsls r3, r3, #3 800307c: 4413 add r3, r2 800307e: 009b lsls r3, r3, #2 8003080: 440b add r3, r1 8003082: 3324 adds r3, #36 @ 0x24 8003084: 681b ldr r3, [r3, #0] 8003086: 2b00 cmp r3, #0 8003088: d108 bne.n 800309c { /* prepare to rx more setup packets */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 800308a: 687b ldr r3, [r7, #4] 800308c: 6818 ldr r0, [r3, #0] 800308e: 687b ldr r3, [r7, #4] 8003090: f203 439c addw r3, r3, #1180 @ 0x49c 8003094: 461a mov r2, r3 8003096: 2101 movs r1, #1 8003098: f005 fa3c bl 8008514 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); 800309c: 6a7b ldr r3, [r7, #36] @ 0x24 800309e: b2db uxtb r3, r3 80030a0: 4619 mov r1, r3 80030a2: 6878 ldr r0, [r7, #4] 80030a4: f007 fa2d bl 800a502 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) 80030a8: 693b ldr r3, [r7, #16] 80030aa: f003 0308 and.w r3, r3, #8 80030ae: 2b00 cmp r3, #0 80030b0: d008 beq.n 80030c4 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); 80030b2: 6a7b ldr r3, [r7, #36] @ 0x24 80030b4: 015a lsls r2, r3, #5 80030b6: 69fb ldr r3, [r7, #28] 80030b8: 4413 add r3, r2 80030ba: f503 6310 add.w r3, r3, #2304 @ 0x900 80030be: 461a mov r2, r3 80030c0: 2308 movs r3, #8 80030c2: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) 80030c4: 693b ldr r3, [r7, #16] 80030c6: f003 0310 and.w r3, r3, #16 80030ca: 2b00 cmp r3, #0 80030cc: d008 beq.n 80030e0 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); 80030ce: 6a7b ldr r3, [r7, #36] @ 0x24 80030d0: 015a lsls r2, r3, #5 80030d2: 69fb ldr r3, [r7, #28] 80030d4: 4413 add r3, r2 80030d6: f503 6310 add.w r3, r3, #2304 @ 0x900 80030da: 461a mov r2, r3 80030dc: 2310 movs r3, #16 80030de: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) 80030e0: 693b ldr r3, [r7, #16] 80030e2: f003 0340 and.w r3, r3, #64 @ 0x40 80030e6: 2b00 cmp r3, #0 80030e8: d008 beq.n 80030fc { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); 80030ea: 6a7b ldr r3, [r7, #36] @ 0x24 80030ec: 015a lsls r2, r3, #5 80030ee: 69fb ldr r3, [r7, #28] 80030f0: 4413 add r3, r2 80030f2: f503 6310 add.w r3, r3, #2304 @ 0x900 80030f6: 461a mov r2, r3 80030f8: 2340 movs r3, #64 @ 0x40 80030fa: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) 80030fc: 693b ldr r3, [r7, #16] 80030fe: f003 0302 and.w r3, r3, #2 8003102: 2b00 cmp r3, #0 8003104: d023 beq.n 800314e { (void)USB_FlushTxFifo(USBx, epnum); 8003106: 6a79 ldr r1, [r7, #36] @ 0x24 8003108: 6a38 ldr r0, [r7, #32] 800310a: f004 fa23 bl 8007554 ep = &hpcd->IN_ep[epnum]; 800310e: 6a7a ldr r2, [r7, #36] @ 0x24 8003110: 4613 mov r3, r2 8003112: 00db lsls r3, r3, #3 8003114: 4413 add r3, r2 8003116: 009b lsls r3, r3, #2 8003118: 3310 adds r3, #16 800311a: 687a ldr r2, [r7, #4] 800311c: 4413 add r3, r2 800311e: 3304 adds r3, #4 8003120: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 8003122: 697b ldr r3, [r7, #20] 8003124: 78db ldrb r3, [r3, #3] 8003126: 2b01 cmp r3, #1 8003128: d108 bne.n 800313c { ep->is_iso_incomplete = 0U; 800312a: 697b ldr r3, [r7, #20] 800312c: 2200 movs r2, #0 800312e: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); 8003130: 6a7b ldr r3, [r7, #36] @ 0x24 8003132: b2db uxtb r3, r3 8003134: 4619 mov r1, r3 8003136: 6878 ldr r0, [r7, #4] 8003138: f007 fa7a bl 800a630 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); 800313c: 6a7b ldr r3, [r7, #36] @ 0x24 800313e: 015a lsls r2, r3, #5 8003140: 69fb ldr r3, [r7, #28] 8003142: 4413 add r3, r2 8003144: f503 6310 add.w r3, r3, #2304 @ 0x900 8003148: 461a mov r2, r3 800314a: 2302 movs r3, #2 800314c: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) 800314e: 693b ldr r3, [r7, #16] 8003150: f003 0380 and.w r3, r3, #128 @ 0x80 8003154: 2b00 cmp r3, #0 8003156: d003 beq.n 8003160 { (void)PCD_WriteEmptyTxFifo(hpcd, epnum); 8003158: 6a79 ldr r1, [r7, #36] @ 0x24 800315a: 6878 ldr r0, [r7, #4] 800315c: f000 fcd2 bl 8003b04 } } epnum++; 8003160: 6a7b ldr r3, [r7, #36] @ 0x24 8003162: 3301 adds r3, #1 8003164: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 8003166: 6abb ldr r3, [r7, #40] @ 0x28 8003168: 085b lsrs r3, r3, #1 800316a: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 800316c: 6abb ldr r3, [r7, #40] @ 0x28 800316e: 2b00 cmp r3, #0 8003170: f47f af2e bne.w 8002fd0 } } /* Handle Resume Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) 8003174: 687b ldr r3, [r7, #4] 8003176: 681b ldr r3, [r3, #0] 8003178: 4618 mov r0, r3 800317a: f005 f907 bl 800838c 800317e: 4603 mov r3, r0 8003180: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8003184: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8003188: d122 bne.n 80031d0 { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 800318a: 69fb ldr r3, [r7, #28] 800318c: f503 6300 add.w r3, r3, #2048 @ 0x800 8003190: 685b ldr r3, [r3, #4] 8003192: 69fa ldr r2, [r7, #28] 8003194: f502 6200 add.w r2, r2, #2048 @ 0x800 8003198: f023 0301 bic.w r3, r3, #1 800319c: 6053 str r3, [r2, #4] if (hpcd->LPM_State == LPM_L1) 800319e: 687b ldr r3, [r7, #4] 80031a0: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 80031a4: 2b01 cmp r3, #1 80031a6: d108 bne.n 80031ba { hpcd->LPM_State = LPM_L0; 80031a8: 687b ldr r3, [r7, #4] 80031aa: 2200 movs r2, #0 80031ac: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 80031b0: 2100 movs r1, #0 80031b2: 6878 ldr r0, [r7, #4] 80031b4: f007 fbe2 bl 800a97c 80031b8: e002 b.n 80031c0 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 80031ba: 6878 ldr r0, [r7, #4] 80031bc: f007 fa18 bl 800a5f0 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); 80031c0: 687b ldr r3, [r7, #4] 80031c2: 681b ldr r3, [r3, #0] 80031c4: 695a ldr r2, [r3, #20] 80031c6: 687b ldr r3, [r7, #4] 80031c8: 681b ldr r3, [r3, #0] 80031ca: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000 80031ce: 615a str r2, [r3, #20] } /* Handle Suspend Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) 80031d0: 687b ldr r3, [r7, #4] 80031d2: 681b ldr r3, [r3, #0] 80031d4: 4618 mov r0, r3 80031d6: f005 f8d9 bl 800838c 80031da: 4603 mov r3, r0 80031dc: f403 6300 and.w r3, r3, #2048 @ 0x800 80031e0: f5b3 6f00 cmp.w r3, #2048 @ 0x800 80031e4: d112 bne.n 800320c { if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 80031e6: 69fb ldr r3, [r7, #28] 80031e8: f503 6300 add.w r3, r3, #2048 @ 0x800 80031ec: 689b ldr r3, [r3, #8] 80031ee: f003 0301 and.w r3, r3, #1 80031f2: 2b01 cmp r3, #1 80031f4: d102 bne.n 80031fc { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 80031f6: 6878 ldr r0, [r7, #4] 80031f8: f007 f9d4 bl 800a5a4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); 80031fc: 687b ldr r3, [r7, #4] 80031fe: 681b ldr r3, [r3, #0] 8003200: 695a ldr r2, [r3, #20] 8003202: 687b ldr r3, [r7, #4] 8003204: 681b ldr r3, [r3, #0] 8003206: f402 6200 and.w r2, r2, #2048 @ 0x800 800320a: 615a str r2, [r3, #20] } #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) 800320c: 687b ldr r3, [r7, #4] 800320e: 681b ldr r3, [r3, #0] 8003210: 4618 mov r0, r3 8003212: f005 f8bb bl 800838c 8003216: 4603 mov r3, r0 8003218: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800321c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8003220: d121 bne.n 8003266 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); 8003222: 687b ldr r3, [r7, #4] 8003224: 681b ldr r3, [r3, #0] 8003226: 695a ldr r2, [r3, #20] 8003228: 687b ldr r3, [r7, #4] 800322a: 681b ldr r3, [r3, #0] 800322c: f002 6200 and.w r2, r2, #134217728 @ 0x8000000 8003230: 615a str r2, [r3, #20] if (hpcd->LPM_State == LPM_L0) 8003232: 687b ldr r3, [r7, #4] 8003234: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 8003238: 2b00 cmp r3, #0 800323a: d111 bne.n 8003260 { hpcd->LPM_State = LPM_L1; 800323c: 687b ldr r3, [r7, #4] 800323e: 2201 movs r2, #1 8003240: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; 8003244: 687b ldr r3, [r7, #4] 8003246: 681b ldr r3, [r3, #0] 8003248: 6d5b ldr r3, [r3, #84] @ 0x54 800324a: 089b lsrs r3, r3, #2 800324c: f003 020f and.w r2, r3, #15 8003250: 687b ldr r3, [r7, #4] 8003252: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 8003256: 2101 movs r1, #1 8003258: 6878 ldr r0, [r7, #4] 800325a: f007 fb8f bl 800a97c 800325e: e002 b.n 8003266 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 8003260: 6878 ldr r0, [r7, #4] 8003262: f007 f99f bl 800a5a4 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) 8003266: 687b ldr r3, [r7, #4] 8003268: 681b ldr r3, [r3, #0] 800326a: 4618 mov r0, r3 800326c: f005 f88e bl 800838c 8003270: 4603 mov r3, r0 8003272: f403 5380 and.w r3, r3, #4096 @ 0x1000 8003276: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800327a: f040 80b7 bne.w 80033ec { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 800327e: 69fb ldr r3, [r7, #28] 8003280: f503 6300 add.w r3, r3, #2048 @ 0x800 8003284: 685b ldr r3, [r3, #4] 8003286: 69fa ldr r2, [r7, #28] 8003288: f502 6200 add.w r2, r2, #2048 @ 0x800 800328c: f023 0301 bic.w r3, r3, #1 8003290: 6053 str r3, [r2, #4] (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); 8003292: 687b ldr r3, [r7, #4] 8003294: 681b ldr r3, [r3, #0] 8003296: 2110 movs r1, #16 8003298: 4618 mov r0, r3 800329a: f004 f95b bl 8007554 for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800329e: 2300 movs r3, #0 80032a0: 62fb str r3, [r7, #44] @ 0x2c 80032a2: e046 b.n 8003332 { USBx_INEP(i)->DIEPINT = 0xFB7FU; 80032a4: 6afb ldr r3, [r7, #44] @ 0x2c 80032a6: 015a lsls r2, r3, #5 80032a8: 69fb ldr r3, [r7, #28] 80032aa: 4413 add r3, r2 80032ac: f503 6310 add.w r3, r3, #2304 @ 0x900 80032b0: 461a mov r2, r3 80032b2: f64f 337f movw r3, #64383 @ 0xfb7f 80032b6: 6093 str r3, [r2, #8] USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 80032b8: 6afb ldr r3, [r7, #44] @ 0x2c 80032ba: 015a lsls r2, r3, #5 80032bc: 69fb ldr r3, [r7, #28] 80032be: 4413 add r3, r2 80032c0: f503 6310 add.w r3, r3, #2304 @ 0x900 80032c4: 681b ldr r3, [r3, #0] 80032c6: 6afa ldr r2, [r7, #44] @ 0x2c 80032c8: 0151 lsls r1, r2, #5 80032ca: 69fa ldr r2, [r7, #28] 80032cc: 440a add r2, r1 80032ce: f502 6210 add.w r2, r2, #2304 @ 0x900 80032d2: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 80032d6: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 80032d8: 6afb ldr r3, [r7, #44] @ 0x2c 80032da: 015a lsls r2, r3, #5 80032dc: 69fb ldr r3, [r7, #28] 80032de: 4413 add r3, r2 80032e0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80032e4: 461a mov r2, r3 80032e6: f64f 337f movw r3, #64383 @ 0xfb7f 80032ea: 6093 str r3, [r2, #8] USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 80032ec: 6afb ldr r3, [r7, #44] @ 0x2c 80032ee: 015a lsls r2, r3, #5 80032f0: 69fb ldr r3, [r7, #28] 80032f2: 4413 add r3, r2 80032f4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80032f8: 681b ldr r3, [r3, #0] 80032fa: 6afa ldr r2, [r7, #44] @ 0x2c 80032fc: 0151 lsls r1, r2, #5 80032fe: 69fa ldr r2, [r7, #28] 8003300: 440a add r2, r1 8003302: f502 6230 add.w r2, r2, #2816 @ 0xb00 8003306: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 800330a: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 800330c: 6afb ldr r3, [r7, #44] @ 0x2c 800330e: 015a lsls r2, r3, #5 8003310: 69fb ldr r3, [r7, #28] 8003312: 4413 add r3, r2 8003314: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003318: 681b ldr r3, [r3, #0] 800331a: 6afa ldr r2, [r7, #44] @ 0x2c 800331c: 0151 lsls r1, r2, #5 800331e: 69fa ldr r2, [r7, #28] 8003320: 440a add r2, r1 8003322: f502 6230 add.w r2, r2, #2816 @ 0xb00 8003326: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800332a: 6013 str r3, [r2, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800332c: 6afb ldr r3, [r7, #44] @ 0x2c 800332e: 3301 adds r3, #1 8003330: 62fb str r3, [r7, #44] @ 0x2c 8003332: 687b ldr r3, [r7, #4] 8003334: 791b ldrb r3, [r3, #4] 8003336: 461a mov r2, r3 8003338: 6afb ldr r3, [r7, #44] @ 0x2c 800333a: 4293 cmp r3, r2 800333c: d3b2 bcc.n 80032a4 } USBx_DEVICE->DAINTMSK |= 0x10001U; 800333e: 69fb ldr r3, [r7, #28] 8003340: f503 6300 add.w r3, r3, #2048 @ 0x800 8003344: 69db ldr r3, [r3, #28] 8003346: 69fa ldr r2, [r7, #28] 8003348: f502 6200 add.w r2, r2, #2048 @ 0x800 800334c: f043 1301 orr.w r3, r3, #65537 @ 0x10001 8003350: 61d3 str r3, [r2, #28] if (hpcd->Init.use_dedicated_ep1 != 0U) 8003352: 687b ldr r3, [r7, #4] 8003354: 7bdb ldrb r3, [r3, #15] 8003356: 2b00 cmp r3, #0 8003358: d016 beq.n 8003388 { USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | 800335a: 69fb ldr r3, [r7, #28] 800335c: f503 6300 add.w r3, r3, #2048 @ 0x800 8003360: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8003364: 69fa ldr r2, [r7, #28] 8003366: f502 6200 add.w r2, r2, #2048 @ 0x800 800336a: f043 030b orr.w r3, r3, #11 800336e: f8c2 3084 str.w r3, [r2, #132] @ 0x84 USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM; USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | 8003372: 69fb ldr r3, [r7, #28] 8003374: f503 6300 add.w r3, r3, #2048 @ 0x800 8003378: 6c5b ldr r3, [r3, #68] @ 0x44 800337a: 69fa ldr r2, [r7, #28] 800337c: f502 6200 add.w r2, r2, #2048 @ 0x800 8003380: f043 030b orr.w r3, r3, #11 8003384: 6453 str r3, [r2, #68] @ 0x44 8003386: e015 b.n 80033b4 USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } else { USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | 8003388: 69fb ldr r3, [r7, #28] 800338a: f503 6300 add.w r3, r3, #2048 @ 0x800 800338e: 695b ldr r3, [r3, #20] 8003390: 69fa ldr r2, [r7, #28] 8003392: f502 6200 add.w r2, r2, #2048 @ 0x800 8003396: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800339a: f043 032b orr.w r3, r3, #43 @ 0x2b 800339e: 6153 str r3, [r2, #20] USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM | USB_OTG_DOEPMSK_NAKM; USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | 80033a0: 69fb ldr r3, [r7, #28] 80033a2: f503 6300 add.w r3, r3, #2048 @ 0x800 80033a6: 691b ldr r3, [r3, #16] 80033a8: 69fa ldr r2, [r7, #28] 80033aa: f502 6200 add.w r2, r2, #2048 @ 0x800 80033ae: f043 030b orr.w r3, r3, #11 80033b2: 6113 str r3, [r2, #16] USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; 80033b4: 69fb ldr r3, [r7, #28] 80033b6: f503 6300 add.w r3, r3, #2048 @ 0x800 80033ba: 681b ldr r3, [r3, #0] 80033bc: 69fa ldr r2, [r7, #28] 80033be: f502 6200 add.w r2, r2, #2048 @ 0x800 80033c2: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 80033c6: 6013 str r3, [r2, #0] /* setup EP0 to receive SETUP packets */ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 80033c8: 687b ldr r3, [r7, #4] 80033ca: 6818 ldr r0, [r3, #0] 80033cc: 687b ldr r3, [r7, #4] 80033ce: 7999 ldrb r1, [r3, #6] (uint8_t *)hpcd->Setup); 80033d0: 687b ldr r3, [r7, #4] 80033d2: f203 439c addw r3, r3, #1180 @ 0x49c (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 80033d6: 461a mov r2, r3 80033d8: f005 f89c bl 8008514 __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); 80033dc: 687b ldr r3, [r7, #4] 80033de: 681b ldr r3, [r3, #0] 80033e0: 695a ldr r2, [r3, #20] 80033e2: 687b ldr r3, [r7, #4] 80033e4: 681b ldr r3, [r3, #0] 80033e6: f402 5280 and.w r2, r2, #4096 @ 0x1000 80033ea: 615a str r2, [r3, #20] } /* Handle Enumeration done Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) 80033ec: 687b ldr r3, [r7, #4] 80033ee: 681b ldr r3, [r3, #0] 80033f0: 4618 mov r0, r3 80033f2: f004 ffcb bl 800838c 80033f6: 4603 mov r3, r0 80033f8: f403 5300 and.w r3, r3, #8192 @ 0x2000 80033fc: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8003400: d123 bne.n 800344a { (void)USB_ActivateSetup(hpcd->Instance); 8003402: 687b ldr r3, [r7, #4] 8003404: 681b ldr r3, [r3, #0] 8003406: 4618 mov r0, r3 8003408: f005 f861 bl 80084ce hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); 800340c: 687b ldr r3, [r7, #4] 800340e: 681b ldr r3, [r3, #0] 8003410: 4618 mov r0, r3 8003412: f004 f918 bl 8007646 8003416: 4603 mov r3, r0 8003418: 461a mov r2, r3 800341a: 687b ldr r3, [r7, #4] 800341c: 71da strb r2, [r3, #7] /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, 800341e: 687b ldr r3, [r7, #4] 8003420: 681c ldr r4, [r3, #0] 8003422: f000 fe8b bl 800413c 8003426: 4601 mov r1, r0 HAL_RCC_GetHCLKFreq(), (uint8_t)hpcd->Init.speed); 8003428: 687b ldr r3, [r7, #4] 800342a: 79db ldrb r3, [r3, #7] (void)USB_SetTurnaroundTime(hpcd->Instance, 800342c: 461a mov r2, r3 800342e: 4620 mov r0, r4 8003430: f003 fe22 bl 8007078 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 8003434: 6878 ldr r0, [r7, #4] 8003436: f007 f88c bl 800a552 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); 800343a: 687b ldr r3, [r7, #4] 800343c: 681b ldr r3, [r3, #0] 800343e: 695a ldr r2, [r3, #20] 8003440: 687b ldr r3, [r7, #4] 8003442: 681b ldr r3, [r3, #0] 8003444: f402 5200 and.w r2, r2, #8192 @ 0x2000 8003448: 615a str r2, [r3, #20] } /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) 800344a: 687b ldr r3, [r7, #4] 800344c: 681b ldr r3, [r3, #0] 800344e: 4618 mov r0, r3 8003450: f004 ff9c bl 800838c 8003454: 4603 mov r3, r0 8003456: f003 0308 and.w r3, r3, #8 800345a: 2b08 cmp r3, #8 800345c: d10a bne.n 8003474 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 800345e: 6878 ldr r0, [r7, #4] 8003460: f007 f869 bl 800a536 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); 8003464: 687b ldr r3, [r7, #4] 8003466: 681b ldr r3, [r3, #0] 8003468: 695a ldr r2, [r3, #20] 800346a: 687b ldr r3, [r7, #4] 800346c: 681b ldr r3, [r3, #0] 800346e: f002 0208 and.w r2, r2, #8 8003472: 615a str r2, [r3, #20] } /* Handle Global OUT NAK effective Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) 8003474: 687b ldr r3, [r7, #4] 8003476: 681b ldr r3, [r3, #0] 8003478: 4618 mov r0, r3 800347a: f004 ff87 bl 800838c 800347e: 4603 mov r3, r0 8003480: f003 0380 and.w r3, r3, #128 @ 0x80 8003484: 2b80 cmp r3, #128 @ 0x80 8003486: d123 bne.n 80034d0 { USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; 8003488: 6a3b ldr r3, [r7, #32] 800348a: 699b ldr r3, [r3, #24] 800348c: f023 0280 bic.w r2, r3, #128 @ 0x80 8003490: 6a3b ldr r3, [r7, #32] 8003492: 619a str r2, [r3, #24] for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003494: 2301 movs r3, #1 8003496: 627b str r3, [r7, #36] @ 0x24 8003498: e014 b.n 80034c4 { if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) 800349a: 6879 ldr r1, [r7, #4] 800349c: 6a7a ldr r2, [r7, #36] @ 0x24 800349e: 4613 mov r3, r2 80034a0: 00db lsls r3, r3, #3 80034a2: 4413 add r3, r2 80034a4: 009b lsls r3, r3, #2 80034a6: 440b add r3, r1 80034a8: f203 2357 addw r3, r3, #599 @ 0x257 80034ac: 781b ldrb r3, [r3, #0] 80034ae: 2b01 cmp r3, #1 80034b0: d105 bne.n 80034be { /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); 80034b2: 6a7b ldr r3, [r7, #36] @ 0x24 80034b4: b2db uxtb r3, r3 80034b6: 4619 mov r1, r3 80034b8: 6878 ldr r0, [r7, #4] 80034ba: f000 faf2 bl 8003aa2 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80034be: 6a7b ldr r3, [r7, #36] @ 0x24 80034c0: 3301 adds r3, #1 80034c2: 627b str r3, [r7, #36] @ 0x24 80034c4: 687b ldr r3, [r7, #4] 80034c6: 791b ldrb r3, [r3, #4] 80034c8: 461a mov r2, r3 80034ca: 6a7b ldr r3, [r7, #36] @ 0x24 80034cc: 4293 cmp r3, r2 80034ce: d3e4 bcc.n 800349a } } } /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) 80034d0: 687b ldr r3, [r7, #4] 80034d2: 681b ldr r3, [r3, #0] 80034d4: 4618 mov r0, r3 80034d6: f004 ff59 bl 800838c 80034da: 4603 mov r3, r0 80034dc: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80034e0: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80034e4: d13c bne.n 8003560 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80034e6: 2301 movs r3, #1 80034e8: 627b str r3, [r7, #36] @ 0x24 80034ea: e02b b.n 8003544 { RegVal = USBx_INEP(epnum)->DIEPCTL; 80034ec: 6a7b ldr r3, [r7, #36] @ 0x24 80034ee: 015a lsls r2, r3, #5 80034f0: 69fb ldr r3, [r7, #28] 80034f2: 4413 add r3, r2 80034f4: f503 6310 add.w r3, r3, #2304 @ 0x900 80034f8: 681b ldr r3, [r3, #0] 80034fa: 61bb str r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 80034fc: 6879 ldr r1, [r7, #4] 80034fe: 6a7a ldr r2, [r7, #36] @ 0x24 8003500: 4613 mov r3, r2 8003502: 00db lsls r3, r3, #3 8003504: 4413 add r3, r2 8003506: 009b lsls r3, r3, #2 8003508: 440b add r3, r1 800350a: 3318 adds r3, #24 800350c: 781b ldrb r3, [r3, #0] 800350e: 2b01 cmp r3, #1 8003510: d115 bne.n 800353e ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) 8003512: 69bb ldr r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 8003514: 2b00 cmp r3, #0 8003516: da12 bge.n 800353e { hpcd->IN_ep[epnum].is_iso_incomplete = 1U; 8003518: 6879 ldr r1, [r7, #4] 800351a: 6a7a ldr r2, [r7, #36] @ 0x24 800351c: 4613 mov r3, r2 800351e: 00db lsls r3, r3, #3 8003520: 4413 add r3, r2 8003522: 009b lsls r3, r3, #2 8003524: 440b add r3, r1 8003526: 3317 adds r3, #23 8003528: 2201 movs r2, #1 800352a: 701a strb r2, [r3, #0] /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); 800352c: 6a7b ldr r3, [r7, #36] @ 0x24 800352e: b2db uxtb r3, r3 8003530: f063 037f orn r3, r3, #127 @ 0x7f 8003534: b2db uxtb r3, r3 8003536: 4619 mov r1, r3 8003538: 6878 ldr r0, [r7, #4] 800353a: f000 fab2 bl 8003aa2 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 800353e: 6a7b ldr r3, [r7, #36] @ 0x24 8003540: 3301 adds r3, #1 8003542: 627b str r3, [r7, #36] @ 0x24 8003544: 687b ldr r3, [r7, #4] 8003546: 791b ldrb r3, [r3, #4] 8003548: 461a mov r2, r3 800354a: 6a7b ldr r3, [r7, #36] @ 0x24 800354c: 4293 cmp r3, r2 800354e: d3cd bcc.n 80034ec } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); 8003550: 687b ldr r3, [r7, #4] 8003552: 681b ldr r3, [r3, #0] 8003554: 695a ldr r2, [r3, #20] 8003556: 687b ldr r3, [r7, #4] 8003558: 681b ldr r3, [r3, #0] 800355a: f402 1280 and.w r2, r2, #1048576 @ 0x100000 800355e: 615a str r2, [r3, #20] } /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 8003560: 687b ldr r3, [r7, #4] 8003562: 681b ldr r3, [r3, #0] 8003564: 4618 mov r0, r3 8003566: f004 ff11 bl 800838c 800356a: 4603 mov r3, r0 800356c: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8003570: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8003574: d156 bne.n 8003624 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003576: 2301 movs r3, #1 8003578: 627b str r3, [r7, #36] @ 0x24 800357a: e045 b.n 8003608 { RegVal = USBx_OUTEP(epnum)->DOEPCTL; 800357c: 6a7b ldr r3, [r7, #36] @ 0x24 800357e: 015a lsls r2, r3, #5 8003580: 69fb ldr r3, [r7, #28] 8003582: 4413 add r3, r2 8003584: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003588: 681b ldr r3, [r3, #0] 800358a: 61bb str r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 800358c: 6879 ldr r1, [r7, #4] 800358e: 6a7a ldr r2, [r7, #36] @ 0x24 8003590: 4613 mov r3, r2 8003592: 00db lsls r3, r3, #3 8003594: 4413 add r3, r2 8003596: 009b lsls r3, r3, #2 8003598: 440b add r3, r1 800359a: f503 7316 add.w r3, r3, #600 @ 0x258 800359e: 781b ldrb r3, [r3, #0] 80035a0: 2b01 cmp r3, #1 80035a2: d12e bne.n 8003602 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 80035a4: 69bb ldr r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 80035a6: 2b00 cmp r3, #0 80035a8: da2b bge.n 8003602 (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) 80035aa: 69bb ldr r3, [r7, #24] 80035ac: 0c1a lsrs r2, r3, #16 80035ae: 687b ldr r3, [r7, #4] 80035b0: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4 80035b4: 4053 eors r3, r2 80035b6: f003 0301 and.w r3, r3, #1 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 80035ba: 2b00 cmp r3, #0 80035bc: d121 bne.n 8003602 { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; 80035be: 6879 ldr r1, [r7, #4] 80035c0: 6a7a ldr r2, [r7, #36] @ 0x24 80035c2: 4613 mov r3, r2 80035c4: 00db lsls r3, r3, #3 80035c6: 4413 add r3, r2 80035c8: 009b lsls r3, r3, #2 80035ca: 440b add r3, r1 80035cc: f203 2357 addw r3, r3, #599 @ 0x257 80035d0: 2201 movs r2, #1 80035d2: 701a strb r2, [r3, #0] USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; 80035d4: 6a3b ldr r3, [r7, #32] 80035d6: 699b ldr r3, [r3, #24] 80035d8: f043 0280 orr.w r2, r3, #128 @ 0x80 80035dc: 6a3b ldr r3, [r7, #32] 80035de: 619a str r2, [r3, #24] if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) 80035e0: 6a3b ldr r3, [r7, #32] 80035e2: 695b ldr r3, [r3, #20] 80035e4: f003 0380 and.w r3, r3, #128 @ 0x80 80035e8: 2b00 cmp r3, #0 80035ea: d10a bne.n 8003602 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; 80035ec: 69fb ldr r3, [r7, #28] 80035ee: f503 6300 add.w r3, r3, #2048 @ 0x800 80035f2: 685b ldr r3, [r3, #4] 80035f4: 69fa ldr r2, [r7, #28] 80035f6: f502 6200 add.w r2, r2, #2048 @ 0x800 80035fa: f443 7300 orr.w r3, r3, #512 @ 0x200 80035fe: 6053 str r3, [r2, #4] break; 8003600: e008 b.n 8003614 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003602: 6a7b ldr r3, [r7, #36] @ 0x24 8003604: 3301 adds r3, #1 8003606: 627b str r3, [r7, #36] @ 0x24 8003608: 687b ldr r3, [r7, #4] 800360a: 791b ldrb r3, [r3, #4] 800360c: 461a mov r2, r3 800360e: 6a7b ldr r3, [r7, #36] @ 0x24 8003610: 4293 cmp r3, r2 8003612: d3b3 bcc.n 800357c } } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 8003614: 687b ldr r3, [r7, #4] 8003616: 681b ldr r3, [r3, #0] 8003618: 695a ldr r2, [r3, #20] 800361a: 687b ldr r3, [r7, #4] 800361c: 681b ldr r3, [r3, #0] 800361e: f402 1200 and.w r2, r2, #2097152 @ 0x200000 8003622: 615a str r2, [r3, #20] } /* Handle Connection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) 8003624: 687b ldr r3, [r7, #4] 8003626: 681b ldr r3, [r3, #0] 8003628: 4618 mov r0, r3 800362a: f004 feaf bl 800838c 800362e: 4603 mov r3, r0 8003630: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8003634: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8003638: d10a bne.n 8003650 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ConnectCallback(hpcd); #else HAL_PCD_ConnectCallback(hpcd); 800363a: 6878 ldr r0, [r7, #4] 800363c: f007 f80a bl 800a654 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); 8003640: 687b ldr r3, [r7, #4] 8003642: 681b ldr r3, [r3, #0] 8003644: 695a ldr r2, [r3, #20] 8003646: 687b ldr r3, [r7, #4] 8003648: 681b ldr r3, [r3, #0] 800364a: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 800364e: 615a str r2, [r3, #20] } /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) 8003650: 687b ldr r3, [r7, #4] 8003652: 681b ldr r3, [r3, #0] 8003654: 4618 mov r0, r3 8003656: f004 fe99 bl 800838c 800365a: 4603 mov r3, r0 800365c: f003 0304 and.w r3, r3, #4 8003660: 2b04 cmp r3, #4 8003662: d115 bne.n 8003690 { RegVal = hpcd->Instance->GOTGINT; 8003664: 687b ldr r3, [r7, #4] 8003666: 681b ldr r3, [r3, #0] 8003668: 685b ldr r3, [r3, #4] 800366a: 61bb str r3, [r7, #24] if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) 800366c: 69bb ldr r3, [r7, #24] 800366e: f003 0304 and.w r3, r3, #4 8003672: 2b00 cmp r3, #0 8003674: d002 beq.n 800367c { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); #else HAL_PCD_DisconnectCallback(hpcd); 8003676: 6878 ldr r0, [r7, #4] 8003678: f006 fffa bl 800a670 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= RegVal; 800367c: 687b ldr r3, [r7, #4] 800367e: 681b ldr r3, [r3, #0] 8003680: 6859 ldr r1, [r3, #4] 8003682: 687b ldr r3, [r7, #4] 8003684: 681b ldr r3, [r3, #0] 8003686: 69ba ldr r2, [r7, #24] 8003688: 430a orrs r2, r1 800368a: 605a str r2, [r3, #4] 800368c: e000 b.n 8003690 return; 800368e: bf00 nop } } } 8003690: 3734 adds r7, #52 @ 0x34 8003692: 46bd mov sp, r7 8003694: bd90 pop {r4, r7, pc} 08003696 : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 8003696: b580 push {r7, lr} 8003698: b082 sub sp, #8 800369a: af00 add r7, sp, #0 800369c: 6078 str r0, [r7, #4] 800369e: 460b mov r3, r1 80036a0: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 80036a2: 687b ldr r3, [r7, #4] 80036a4: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 80036a8: 2b01 cmp r3, #1 80036aa: d101 bne.n 80036b0 80036ac: 2302 movs r3, #2 80036ae: e012 b.n 80036d6 80036b0: 687b ldr r3, [r7, #4] 80036b2: 2201 movs r2, #1 80036b4: f883 2494 strb.w r2, [r3, #1172] @ 0x494 hpcd->USB_Address = address; 80036b8: 687b ldr r3, [r7, #4] 80036ba: 78fa ldrb r2, [r7, #3] 80036bc: 745a strb r2, [r3, #17] (void)USB_SetDevAddress(hpcd->Instance, address); 80036be: 687b ldr r3, [r7, #4] 80036c0: 681b ldr r3, [r3, #0] 80036c2: 78fa ldrb r2, [r7, #3] 80036c4: 4611 mov r1, r2 80036c6: 4618 mov r0, r3 80036c8: f004 fdf8 bl 80082bc __HAL_UNLOCK(hpcd); 80036cc: 687b ldr r3, [r7, #4] 80036ce: 2200 movs r2, #0 80036d0: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 80036d4: 2300 movs r3, #0 } 80036d6: 4618 mov r0, r3 80036d8: 3708 adds r7, #8 80036da: 46bd mov sp, r7 80036dc: bd80 pop {r7, pc} 080036de : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 80036de: b580 push {r7, lr} 80036e0: b084 sub sp, #16 80036e2: af00 add r7, sp, #0 80036e4: 6078 str r0, [r7, #4] 80036e6: 4608 mov r0, r1 80036e8: 4611 mov r1, r2 80036ea: 461a mov r2, r3 80036ec: 4603 mov r3, r0 80036ee: 70fb strb r3, [r7, #3] 80036f0: 460b mov r3, r1 80036f2: 803b strh r3, [r7, #0] 80036f4: 4613 mov r3, r2 80036f6: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 80036f8: 2300 movs r3, #0 80036fa: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 80036fc: f997 3003 ldrsb.w r3, [r7, #3] 8003700: 2b00 cmp r3, #0 8003702: da0f bge.n 8003724 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003704: 78fb ldrb r3, [r7, #3] 8003706: f003 020f and.w r2, r3, #15 800370a: 4613 mov r3, r2 800370c: 00db lsls r3, r3, #3 800370e: 4413 add r3, r2 8003710: 009b lsls r3, r3, #2 8003712: 3310 adds r3, #16 8003714: 687a ldr r2, [r7, #4] 8003716: 4413 add r3, r2 8003718: 3304 adds r3, #4 800371a: 60fb str r3, [r7, #12] ep->is_in = 1U; 800371c: 68fb ldr r3, [r7, #12] 800371e: 2201 movs r2, #1 8003720: 705a strb r2, [r3, #1] 8003722: e00f b.n 8003744 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003724: 78fb ldrb r3, [r7, #3] 8003726: f003 020f and.w r2, r3, #15 800372a: 4613 mov r3, r2 800372c: 00db lsls r3, r3, #3 800372e: 4413 add r3, r2 8003730: 009b lsls r3, r3, #2 8003732: f503 7314 add.w r3, r3, #592 @ 0x250 8003736: 687a ldr r2, [r7, #4] 8003738: 4413 add r3, r2 800373a: 3304 adds r3, #4 800373c: 60fb str r3, [r7, #12] ep->is_in = 0U; 800373e: 68fb ldr r3, [r7, #12] 8003740: 2200 movs r2, #0 8003742: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8003744: 78fb ldrb r3, [r7, #3] 8003746: f003 030f and.w r3, r3, #15 800374a: b2da uxtb r2, r3 800374c: 68fb ldr r3, [r7, #12] 800374e: 701a strb r2, [r3, #0] ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; 8003750: 883b ldrh r3, [r7, #0] 8003752: f3c3 020a ubfx r2, r3, #0, #11 8003756: 68fb ldr r3, [r7, #12] 8003758: 609a str r2, [r3, #8] ep->type = ep_type; 800375a: 68fb ldr r3, [r7, #12] 800375c: 78ba ldrb r2, [r7, #2] 800375e: 711a strb r2, [r3, #4] if (ep->is_in != 0U) 8003760: 68fb ldr r3, [r7, #12] 8003762: 785b ldrb r3, [r3, #1] 8003764: 2b00 cmp r3, #0 8003766: d004 beq.n 8003772 { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; 8003768: 68fb ldr r3, [r7, #12] 800376a: 781b ldrb r3, [r3, #0] 800376c: 461a mov r2, r3 800376e: 68fb ldr r3, [r7, #12] 8003770: 835a strh r2, [r3, #26] } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 8003772: 78bb ldrb r3, [r7, #2] 8003774: 2b02 cmp r3, #2 8003776: d102 bne.n 800377e { ep->data_pid_start = 0U; 8003778: 68fb ldr r3, [r7, #12] 800377a: 2200 movs r2, #0 800377c: 715a strb r2, [r3, #5] } __HAL_LOCK(hpcd); 800377e: 687b ldr r3, [r7, #4] 8003780: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003784: 2b01 cmp r3, #1 8003786: d101 bne.n 800378c 8003788: 2302 movs r3, #2 800378a: e00e b.n 80037aa 800378c: 687b ldr r3, [r7, #4] 800378e: 2201 movs r2, #1 8003790: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_ActivateEndpoint(hpcd->Instance, ep); 8003794: 687b ldr r3, [r7, #4] 8003796: 681b ldr r3, [r3, #0] 8003798: 68f9 ldr r1, [r7, #12] 800379a: 4618 mov r0, r3 800379c: f003 ff78 bl 8007690 __HAL_UNLOCK(hpcd); 80037a0: 687b ldr r3, [r7, #4] 80037a2: 2200 movs r2, #0 80037a4: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return ret; 80037a8: 7afb ldrb r3, [r7, #11] } 80037aa: 4618 mov r0, r3 80037ac: 3710 adds r7, #16 80037ae: 46bd mov sp, r7 80037b0: bd80 pop {r7, pc} 080037b2 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 80037b2: b580 push {r7, lr} 80037b4: b084 sub sp, #16 80037b6: af00 add r7, sp, #0 80037b8: 6078 str r0, [r7, #4] 80037ba: 460b mov r3, r1 80037bc: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 80037be: f997 3003 ldrsb.w r3, [r7, #3] 80037c2: 2b00 cmp r3, #0 80037c4: da0f bge.n 80037e6 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 80037c6: 78fb ldrb r3, [r7, #3] 80037c8: f003 020f and.w r2, r3, #15 80037cc: 4613 mov r3, r2 80037ce: 00db lsls r3, r3, #3 80037d0: 4413 add r3, r2 80037d2: 009b lsls r3, r3, #2 80037d4: 3310 adds r3, #16 80037d6: 687a ldr r2, [r7, #4] 80037d8: 4413 add r3, r2 80037da: 3304 adds r3, #4 80037dc: 60fb str r3, [r7, #12] ep->is_in = 1U; 80037de: 68fb ldr r3, [r7, #12] 80037e0: 2201 movs r2, #1 80037e2: 705a strb r2, [r3, #1] 80037e4: e00f b.n 8003806 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80037e6: 78fb ldrb r3, [r7, #3] 80037e8: f003 020f and.w r2, r3, #15 80037ec: 4613 mov r3, r2 80037ee: 00db lsls r3, r3, #3 80037f0: 4413 add r3, r2 80037f2: 009b lsls r3, r3, #2 80037f4: f503 7314 add.w r3, r3, #592 @ 0x250 80037f8: 687a ldr r2, [r7, #4] 80037fa: 4413 add r3, r2 80037fc: 3304 adds r3, #4 80037fe: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003800: 68fb ldr r3, [r7, #12] 8003802: 2200 movs r2, #0 8003804: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8003806: 78fb ldrb r3, [r7, #3] 8003808: f003 030f and.w r3, r3, #15 800380c: b2da uxtb r2, r3 800380e: 68fb ldr r3, [r7, #12] 8003810: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003812: 687b ldr r3, [r7, #4] 8003814: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003818: 2b01 cmp r3, #1 800381a: d101 bne.n 8003820 800381c: 2302 movs r3, #2 800381e: e00e b.n 800383e 8003820: 687b ldr r3, [r7, #4] 8003822: 2201 movs r2, #1 8003824: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 8003828: 687b ldr r3, [r7, #4] 800382a: 681b ldr r3, [r3, #0] 800382c: 68f9 ldr r1, [r7, #12] 800382e: 4618 mov r0, r3 8003830: f003 ffb6 bl 80077a0 __HAL_UNLOCK(hpcd); 8003834: 687b ldr r3, [r7, #4] 8003836: 2200 movs r2, #0 8003838: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 800383c: 2300 movs r3, #0 } 800383e: 4618 mov r0, r3 8003840: 3710 adds r7, #16 8003842: 46bd mov sp, r7 8003844: bd80 pop {r7, pc} 08003846 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8003846: b580 push {r7, lr} 8003848: b086 sub sp, #24 800384a: af00 add r7, sp, #0 800384c: 60f8 str r0, [r7, #12] 800384e: 607a str r2, [r7, #4] 8003850: 603b str r3, [r7, #0] 8003852: 460b mov r3, r1 8003854: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003856: 7afb ldrb r3, [r7, #11] 8003858: f003 020f and.w r2, r3, #15 800385c: 4613 mov r3, r2 800385e: 00db lsls r3, r3, #3 8003860: 4413 add r3, r2 8003862: 009b lsls r3, r3, #2 8003864: f503 7314 add.w r3, r3, #592 @ 0x250 8003868: 68fa ldr r2, [r7, #12] 800386a: 4413 add r3, r2 800386c: 3304 adds r3, #4 800386e: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003870: 697b ldr r3, [r7, #20] 8003872: 687a ldr r2, [r7, #4] 8003874: 60da str r2, [r3, #12] ep->xfer_len = len; 8003876: 697b ldr r3, [r7, #20] 8003878: 683a ldr r2, [r7, #0] 800387a: 611a str r2, [r3, #16] ep->xfer_count = 0U; 800387c: 697b ldr r3, [r7, #20] 800387e: 2200 movs r2, #0 8003880: 615a str r2, [r3, #20] ep->is_in = 0U; 8003882: 697b ldr r3, [r7, #20] 8003884: 2200 movs r2, #0 8003886: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8003888: 7afb ldrb r3, [r7, #11] 800388a: f003 030f and.w r3, r3, #15 800388e: b2da uxtb r2, r3 8003890: 697b ldr r3, [r7, #20] 8003892: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003894: 68fb ldr r3, [r7, #12] 8003896: 799b ldrb r3, [r3, #6] 8003898: 2b01 cmp r3, #1 800389a: d102 bne.n 80038a2 { ep->dma_addr = (uint32_t)pBuf; 800389c: 687a ldr r2, [r7, #4] 800389e: 697b ldr r3, [r7, #20] 80038a0: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 80038a2: 68fb ldr r3, [r7, #12] 80038a4: 6818 ldr r0, [r3, #0] 80038a6: 68fb ldr r3, [r7, #12] 80038a8: 799b ldrb r3, [r3, #6] 80038aa: 461a mov r2, r3 80038ac: 6979 ldr r1, [r7, #20] 80038ae: f004 f853 bl 8007958 return HAL_OK; 80038b2: 2300 movs r3, #0 } 80038b4: 4618 mov r0, r3 80038b6: 3718 adds r7, #24 80038b8: 46bd mov sp, r7 80038ba: bd80 pop {r7, pc} 080038bc : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 80038bc: b580 push {r7, lr} 80038be: b086 sub sp, #24 80038c0: af00 add r7, sp, #0 80038c2: 60f8 str r0, [r7, #12] 80038c4: 607a str r2, [r7, #4] 80038c6: 603b str r3, [r7, #0] 80038c8: 460b mov r3, r1 80038ca: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 80038cc: 7afb ldrb r3, [r7, #11] 80038ce: f003 020f and.w r2, r3, #15 80038d2: 4613 mov r3, r2 80038d4: 00db lsls r3, r3, #3 80038d6: 4413 add r3, r2 80038d8: 009b lsls r3, r3, #2 80038da: 3310 adds r3, #16 80038dc: 68fa ldr r2, [r7, #12] 80038de: 4413 add r3, r2 80038e0: 3304 adds r3, #4 80038e2: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 80038e4: 697b ldr r3, [r7, #20] 80038e6: 687a ldr r2, [r7, #4] 80038e8: 60da str r2, [r3, #12] ep->xfer_len = len; 80038ea: 697b ldr r3, [r7, #20] 80038ec: 683a ldr r2, [r7, #0] 80038ee: 611a str r2, [r3, #16] ep->xfer_count = 0U; 80038f0: 697b ldr r3, [r7, #20] 80038f2: 2200 movs r2, #0 80038f4: 615a str r2, [r3, #20] ep->is_in = 1U; 80038f6: 697b ldr r3, [r7, #20] 80038f8: 2201 movs r2, #1 80038fa: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 80038fc: 7afb ldrb r3, [r7, #11] 80038fe: f003 030f and.w r3, r3, #15 8003902: b2da uxtb r2, r3 8003904: 697b ldr r3, [r7, #20] 8003906: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003908: 68fb ldr r3, [r7, #12] 800390a: 799b ldrb r3, [r3, #6] 800390c: 2b01 cmp r3, #1 800390e: d102 bne.n 8003916 { ep->dma_addr = (uint32_t)pBuf; 8003910: 687a ldr r2, [r7, #4] 8003912: 697b ldr r3, [r7, #20] 8003914: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003916: 68fb ldr r3, [r7, #12] 8003918: 6818 ldr r0, [r3, #0] 800391a: 68fb ldr r3, [r7, #12] 800391c: 799b ldrb r3, [r3, #6] 800391e: 461a mov r2, r3 8003920: 6979 ldr r1, [r7, #20] 8003922: f004 f819 bl 8007958 return HAL_OK; 8003926: 2300 movs r3, #0 } 8003928: 4618 mov r0, r3 800392a: 3718 adds r7, #24 800392c: 46bd mov sp, r7 800392e: bd80 pop {r7, pc} 08003930 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003930: b580 push {r7, lr} 8003932: b084 sub sp, #16 8003934: af00 add r7, sp, #0 8003936: 6078 str r0, [r7, #4] 8003938: 460b mov r3, r1 800393a: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 800393c: 78fb ldrb r3, [r7, #3] 800393e: f003 030f and.w r3, r3, #15 8003942: 687a ldr r2, [r7, #4] 8003944: 7912 ldrb r2, [r2, #4] 8003946: 4293 cmp r3, r2 8003948: d901 bls.n 800394e { return HAL_ERROR; 800394a: 2301 movs r3, #1 800394c: e04f b.n 80039ee } if ((0x80U & ep_addr) == 0x80U) 800394e: f997 3003 ldrsb.w r3, [r7, #3] 8003952: 2b00 cmp r3, #0 8003954: da0f bge.n 8003976 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003956: 78fb ldrb r3, [r7, #3] 8003958: f003 020f and.w r2, r3, #15 800395c: 4613 mov r3, r2 800395e: 00db lsls r3, r3, #3 8003960: 4413 add r3, r2 8003962: 009b lsls r3, r3, #2 8003964: 3310 adds r3, #16 8003966: 687a ldr r2, [r7, #4] 8003968: 4413 add r3, r2 800396a: 3304 adds r3, #4 800396c: 60fb str r3, [r7, #12] ep->is_in = 1U; 800396e: 68fb ldr r3, [r7, #12] 8003970: 2201 movs r2, #1 8003972: 705a strb r2, [r3, #1] 8003974: e00d b.n 8003992 } else { ep = &hpcd->OUT_ep[ep_addr]; 8003976: 78fa ldrb r2, [r7, #3] 8003978: 4613 mov r3, r2 800397a: 00db lsls r3, r3, #3 800397c: 4413 add r3, r2 800397e: 009b lsls r3, r3, #2 8003980: f503 7314 add.w r3, r3, #592 @ 0x250 8003984: 687a ldr r2, [r7, #4] 8003986: 4413 add r3, r2 8003988: 3304 adds r3, #4 800398a: 60fb str r3, [r7, #12] ep->is_in = 0U; 800398c: 68fb ldr r3, [r7, #12] 800398e: 2200 movs r2, #0 8003990: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8003992: 68fb ldr r3, [r7, #12] 8003994: 2201 movs r2, #1 8003996: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003998: 78fb ldrb r3, [r7, #3] 800399a: f003 030f and.w r3, r3, #15 800399e: b2da uxtb r2, r3 80039a0: 68fb ldr r3, [r7, #12] 80039a2: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 80039a4: 687b ldr r3, [r7, #4] 80039a6: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 80039aa: 2b01 cmp r3, #1 80039ac: d101 bne.n 80039b2 80039ae: 2302 movs r3, #2 80039b0: e01d b.n 80039ee 80039b2: 687b ldr r3, [r7, #4] 80039b4: 2201 movs r2, #1 80039b6: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPSetStall(hpcd->Instance, ep); 80039ba: 687b ldr r3, [r7, #4] 80039bc: 681b ldr r3, [r3, #0] 80039be: 68f9 ldr r1, [r7, #12] 80039c0: 4618 mov r0, r3 80039c2: f004 fba7 bl 8008114 if ((ep_addr & EP_ADDR_MSK) == 0U) 80039c6: 78fb ldrb r3, [r7, #3] 80039c8: f003 030f and.w r3, r3, #15 80039cc: 2b00 cmp r3, #0 80039ce: d109 bne.n 80039e4 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); 80039d0: 687b ldr r3, [r7, #4] 80039d2: 6818 ldr r0, [r3, #0] 80039d4: 687b ldr r3, [r7, #4] 80039d6: 7999 ldrb r1, [r3, #6] 80039d8: 687b ldr r3, [r7, #4] 80039da: f203 439c addw r3, r3, #1180 @ 0x49c 80039de: 461a mov r2, r3 80039e0: f004 fd98 bl 8008514 } __HAL_UNLOCK(hpcd); 80039e4: 687b ldr r3, [r7, #4] 80039e6: 2200 movs r2, #0 80039e8: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 80039ec: 2300 movs r3, #0 } 80039ee: 4618 mov r0, r3 80039f0: 3710 adds r7, #16 80039f2: 46bd mov sp, r7 80039f4: bd80 pop {r7, pc} 080039f6 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 80039f6: b580 push {r7, lr} 80039f8: b084 sub sp, #16 80039fa: af00 add r7, sp, #0 80039fc: 6078 str r0, [r7, #4] 80039fe: 460b mov r3, r1 8003a00: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8003a02: 78fb ldrb r3, [r7, #3] 8003a04: f003 030f and.w r3, r3, #15 8003a08: 687a ldr r2, [r7, #4] 8003a0a: 7912 ldrb r2, [r2, #4] 8003a0c: 4293 cmp r3, r2 8003a0e: d901 bls.n 8003a14 { return HAL_ERROR; 8003a10: 2301 movs r3, #1 8003a12: e042 b.n 8003a9a } if ((0x80U & ep_addr) == 0x80U) 8003a14: f997 3003 ldrsb.w r3, [r7, #3] 8003a18: 2b00 cmp r3, #0 8003a1a: da0f bge.n 8003a3c { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003a1c: 78fb ldrb r3, [r7, #3] 8003a1e: f003 020f and.w r2, r3, #15 8003a22: 4613 mov r3, r2 8003a24: 00db lsls r3, r3, #3 8003a26: 4413 add r3, r2 8003a28: 009b lsls r3, r3, #2 8003a2a: 3310 adds r3, #16 8003a2c: 687a ldr r2, [r7, #4] 8003a2e: 4413 add r3, r2 8003a30: 3304 adds r3, #4 8003a32: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003a34: 68fb ldr r3, [r7, #12] 8003a36: 2201 movs r2, #1 8003a38: 705a strb r2, [r3, #1] 8003a3a: e00f b.n 8003a5c } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003a3c: 78fb ldrb r3, [r7, #3] 8003a3e: f003 020f and.w r2, r3, #15 8003a42: 4613 mov r3, r2 8003a44: 00db lsls r3, r3, #3 8003a46: 4413 add r3, r2 8003a48: 009b lsls r3, r3, #2 8003a4a: f503 7314 add.w r3, r3, #592 @ 0x250 8003a4e: 687a ldr r2, [r7, #4] 8003a50: 4413 add r3, r2 8003a52: 3304 adds r3, #4 8003a54: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003a56: 68fb ldr r3, [r7, #12] 8003a58: 2200 movs r2, #0 8003a5a: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8003a5c: 68fb ldr r3, [r7, #12] 8003a5e: 2200 movs r2, #0 8003a60: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003a62: 78fb ldrb r3, [r7, #3] 8003a64: f003 030f and.w r3, r3, #15 8003a68: b2da uxtb r2, r3 8003a6a: 68fb ldr r3, [r7, #12] 8003a6c: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003a6e: 687b ldr r3, [r7, #4] 8003a70: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003a74: 2b01 cmp r3, #1 8003a76: d101 bne.n 8003a7c 8003a78: 2302 movs r3, #2 8003a7a: e00e b.n 8003a9a 8003a7c: 687b ldr r3, [r7, #4] 8003a7e: 2201 movs r2, #1 8003a80: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPClearStall(hpcd->Instance, ep); 8003a84: 687b ldr r3, [r7, #4] 8003a86: 681b ldr r3, [r3, #0] 8003a88: 68f9 ldr r1, [r7, #12] 8003a8a: 4618 mov r0, r3 8003a8c: f004 fbb0 bl 80081f0 __HAL_UNLOCK(hpcd); 8003a90: 687b ldr r3, [r7, #4] 8003a92: 2200 movs r2, #0 8003a94: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003a98: 2300 movs r3, #0 } 8003a9a: 4618 mov r0, r3 8003a9c: 3710 adds r7, #16 8003a9e: 46bd mov sp, r7 8003aa0: bd80 pop {r7, pc} 08003aa2 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003aa2: b580 push {r7, lr} 8003aa4: b084 sub sp, #16 8003aa6: af00 add r7, sp, #0 8003aa8: 6078 str r0, [r7, #4] 8003aaa: 460b mov r3, r1 8003aac: 70fb strb r3, [r7, #3] HAL_StatusTypeDef ret; PCD_EPTypeDef *ep; if ((0x80U & ep_addr) == 0x80U) 8003aae: f997 3003 ldrsb.w r3, [r7, #3] 8003ab2: 2b00 cmp r3, #0 8003ab4: da0c bge.n 8003ad0 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003ab6: 78fb ldrb r3, [r7, #3] 8003ab8: f003 020f and.w r2, r3, #15 8003abc: 4613 mov r3, r2 8003abe: 00db lsls r3, r3, #3 8003ac0: 4413 add r3, r2 8003ac2: 009b lsls r3, r3, #2 8003ac4: 3310 adds r3, #16 8003ac6: 687a ldr r2, [r7, #4] 8003ac8: 4413 add r3, r2 8003aca: 3304 adds r3, #4 8003acc: 60fb str r3, [r7, #12] 8003ace: e00c b.n 8003aea } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003ad0: 78fb ldrb r3, [r7, #3] 8003ad2: f003 020f and.w r2, r3, #15 8003ad6: 4613 mov r3, r2 8003ad8: 00db lsls r3, r3, #3 8003ada: 4413 add r3, r2 8003adc: 009b lsls r3, r3, #2 8003ade: f503 7314 add.w r3, r3, #592 @ 0x250 8003ae2: 687a ldr r2, [r7, #4] 8003ae4: 4413 add r3, r2 8003ae6: 3304 adds r3, #4 8003ae8: 60fb str r3, [r7, #12] } /* Stop Xfer */ ret = USB_EPStopXfer(hpcd->Instance, ep); 8003aea: 687b ldr r3, [r7, #4] 8003aec: 681b ldr r3, [r3, #0] 8003aee: 68f9 ldr r1, [r7, #12] 8003af0: 4618 mov r0, r3 8003af2: f004 f9cf bl 8007e94 8003af6: 4603 mov r3, r0 8003af8: 72fb strb r3, [r7, #11] return ret; 8003afa: 7afb ldrb r3, [r7, #11] } 8003afc: 4618 mov r0, r3 8003afe: 3710 adds r7, #16 8003b00: 46bd mov sp, r7 8003b02: bd80 pop {r7, pc} 08003b04 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003b04: b580 push {r7, lr} 8003b06: b08a sub sp, #40 @ 0x28 8003b08: af02 add r7, sp, #8 8003b0a: 6078 str r0, [r7, #4] 8003b0c: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003b0e: 687b ldr r3, [r7, #4] 8003b10: 681b ldr r3, [r3, #0] 8003b12: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003b14: 697b ldr r3, [r7, #20] 8003b16: 613b str r3, [r7, #16] USB_OTG_EPTypeDef *ep; uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; 8003b18: 683a ldr r2, [r7, #0] 8003b1a: 4613 mov r3, r2 8003b1c: 00db lsls r3, r3, #3 8003b1e: 4413 add r3, r2 8003b20: 009b lsls r3, r3, #2 8003b22: 3310 adds r3, #16 8003b24: 687a ldr r2, [r7, #4] 8003b26: 4413 add r3, r2 8003b28: 3304 adds r3, #4 8003b2a: 60fb str r3, [r7, #12] if (ep->xfer_count > ep->xfer_len) 8003b2c: 68fb ldr r3, [r7, #12] 8003b2e: 695a ldr r2, [r3, #20] 8003b30: 68fb ldr r3, [r7, #12] 8003b32: 691b ldr r3, [r3, #16] 8003b34: 429a cmp r2, r3 8003b36: d901 bls.n 8003b3c { return HAL_ERROR; 8003b38: 2301 movs r3, #1 8003b3a: e06b b.n 8003c14 } len = ep->xfer_len - ep->xfer_count; 8003b3c: 68fb ldr r3, [r7, #12] 8003b3e: 691a ldr r2, [r3, #16] 8003b40: 68fb ldr r3, [r7, #12] 8003b42: 695b ldr r3, [r3, #20] 8003b44: 1ad3 subs r3, r2, r3 8003b46: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8003b48: 68fb ldr r3, [r7, #12] 8003b4a: 689b ldr r3, [r3, #8] 8003b4c: 69fa ldr r2, [r7, #28] 8003b4e: 429a cmp r2, r3 8003b50: d902 bls.n 8003b58 { len = ep->maxpacket; 8003b52: 68fb ldr r3, [r7, #12] 8003b54: 689b ldr r3, [r3, #8] 8003b56: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8003b58: 69fb ldr r3, [r7, #28] 8003b5a: 3303 adds r3, #3 8003b5c: 089b lsrs r3, r3, #2 8003b5e: 61bb str r3, [r7, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003b60: e02a b.n 8003bb8 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; 8003b62: 68fb ldr r3, [r7, #12] 8003b64: 691a ldr r2, [r3, #16] 8003b66: 68fb ldr r3, [r7, #12] 8003b68: 695b ldr r3, [r3, #20] 8003b6a: 1ad3 subs r3, r2, r3 8003b6c: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8003b6e: 68fb ldr r3, [r7, #12] 8003b70: 689b ldr r3, [r3, #8] 8003b72: 69fa ldr r2, [r7, #28] 8003b74: 429a cmp r2, r3 8003b76: d902 bls.n 8003b7e { len = ep->maxpacket; 8003b78: 68fb ldr r3, [r7, #12] 8003b7a: 689b ldr r3, [r3, #8] 8003b7c: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8003b7e: 69fb ldr r3, [r7, #28] 8003b80: 3303 adds r3, #3 8003b82: 089b lsrs r3, r3, #2 8003b84: 61bb str r3, [r7, #24] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8003b86: 68fb ldr r3, [r7, #12] 8003b88: 68d9 ldr r1, [r3, #12] 8003b8a: 683b ldr r3, [r7, #0] 8003b8c: b2da uxtb r2, r3 8003b8e: 69fb ldr r3, [r7, #28] 8003b90: b298 uxth r0, r3 (uint8_t)hpcd->Init.dma_enable); 8003b92: 687b ldr r3, [r7, #4] 8003b94: 799b ldrb r3, [r3, #6] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8003b96: 9300 str r3, [sp, #0] 8003b98: 4603 mov r3, r0 8003b9a: 6978 ldr r0, [r7, #20] 8003b9c: f004 fa24 bl 8007fe8 ep->xfer_buff += len; 8003ba0: 68fb ldr r3, [r7, #12] 8003ba2: 68da ldr r2, [r3, #12] 8003ba4: 69fb ldr r3, [r7, #28] 8003ba6: 441a add r2, r3 8003ba8: 68fb ldr r3, [r7, #12] 8003baa: 60da str r2, [r3, #12] ep->xfer_count += len; 8003bac: 68fb ldr r3, [r7, #12] 8003bae: 695a ldr r2, [r3, #20] 8003bb0: 69fb ldr r3, [r7, #28] 8003bb2: 441a add r2, r3 8003bb4: 68fb ldr r3, [r7, #12] 8003bb6: 615a str r2, [r3, #20] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003bb8: 683b ldr r3, [r7, #0] 8003bba: 015a lsls r2, r3, #5 8003bbc: 693b ldr r3, [r7, #16] 8003bbe: 4413 add r3, r2 8003bc0: f503 6310 add.w r3, r3, #2304 @ 0x900 8003bc4: 699b ldr r3, [r3, #24] 8003bc6: b29b uxth r3, r3 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8003bc8: 69ba ldr r2, [r7, #24] 8003bca: 429a cmp r2, r3 8003bcc: d809 bhi.n 8003be2 8003bce: 68fb ldr r3, [r7, #12] 8003bd0: 695a ldr r2, [r3, #20] 8003bd2: 68fb ldr r3, [r7, #12] 8003bd4: 691b ldr r3, [r3, #16] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003bd6: 429a cmp r2, r3 8003bd8: d203 bcs.n 8003be2 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8003bda: 68fb ldr r3, [r7, #12] 8003bdc: 691b ldr r3, [r3, #16] 8003bde: 2b00 cmp r3, #0 8003be0: d1bf bne.n 8003b62 } if (ep->xfer_len <= ep->xfer_count) 8003be2: 68fb ldr r3, [r7, #12] 8003be4: 691a ldr r2, [r3, #16] 8003be6: 68fb ldr r3, [r7, #12] 8003be8: 695b ldr r3, [r3, #20] 8003bea: 429a cmp r2, r3 8003bec: d811 bhi.n 8003c12 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8003bee: 683b ldr r3, [r7, #0] 8003bf0: f003 030f and.w r3, r3, #15 8003bf4: 2201 movs r2, #1 8003bf6: fa02 f303 lsl.w r3, r2, r3 8003bfa: 60bb str r3, [r7, #8] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8003bfc: 693b ldr r3, [r7, #16] 8003bfe: f503 6300 add.w r3, r3, #2048 @ 0x800 8003c02: 6b5a ldr r2, [r3, #52] @ 0x34 8003c04: 68bb ldr r3, [r7, #8] 8003c06: 43db mvns r3, r3 8003c08: 6939 ldr r1, [r7, #16] 8003c0a: f501 6100 add.w r1, r1, #2048 @ 0x800 8003c0e: 4013 ands r3, r2 8003c10: 634b str r3, [r1, #52] @ 0x34 } return HAL_OK; 8003c12: 2300 movs r3, #0 } 8003c14: 4618 mov r0, r3 8003c16: 3720 adds r7, #32 8003c18: 46bd mov sp, r7 8003c1a: bd80 pop {r7, pc} 08003c1c : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003c1c: b580 push {r7, lr} 8003c1e: b088 sub sp, #32 8003c20: af00 add r7, sp, #0 8003c22: 6078 str r0, [r7, #4] 8003c24: 6039 str r1, [r7, #0] USB_OTG_EPTypeDef *ep; const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003c26: 687b ldr r3, [r7, #4] 8003c28: 681b ldr r3, [r3, #0] 8003c2a: 61fb str r3, [r7, #28] uint32_t USBx_BASE = (uint32_t)USBx; 8003c2c: 69fb ldr r3, [r7, #28] 8003c2e: 61bb str r3, [r7, #24] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8003c30: 69fb ldr r3, [r7, #28] 8003c32: 333c adds r3, #60 @ 0x3c 8003c34: 3304 adds r3, #4 8003c36: 681b ldr r3, [r3, #0] 8003c38: 617b str r3, [r7, #20] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003c3a: 683b ldr r3, [r7, #0] 8003c3c: 015a lsls r2, r3, #5 8003c3e: 69bb ldr r3, [r7, #24] 8003c40: 4413 add r3, r2 8003c42: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003c46: 689b ldr r3, [r3, #8] 8003c48: 613b str r3, [r7, #16] if (hpcd->Init.dma_enable == 1U) 8003c4a: 687b ldr r3, [r7, #4] 8003c4c: 799b ldrb r3, [r3, #6] 8003c4e: 2b01 cmp r3, #1 8003c50: d17b bne.n 8003d4a { if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ 8003c52: 693b ldr r3, [r7, #16] 8003c54: f003 0308 and.w r3, r3, #8 8003c58: 2b00 cmp r3, #0 8003c5a: d015 beq.n 8003c88 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003c5c: 697b ldr r3, [r7, #20] 8003c5e: 4a61 ldr r2, [pc, #388] @ (8003de4 ) 8003c60: 4293 cmp r3, r2 8003c62: f240 80b9 bls.w 8003dd8 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003c66: 693b ldr r3, [r7, #16] 8003c68: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003c6c: 2b00 cmp r3, #0 8003c6e: f000 80b3 beq.w 8003dd8 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003c72: 683b ldr r3, [r7, #0] 8003c74: 015a lsls r2, r3, #5 8003c76: 69bb ldr r3, [r7, #24] 8003c78: 4413 add r3, r2 8003c7a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003c7e: 461a mov r2, r3 8003c80: f44f 4300 mov.w r3, #32768 @ 0x8000 8003c84: 6093 str r3, [r2, #8] 8003c86: e0a7 b.n 8003dd8 } } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ 8003c88: 693b ldr r3, [r7, #16] 8003c8a: f003 0320 and.w r3, r3, #32 8003c8e: 2b00 cmp r3, #0 8003c90: d009 beq.n 8003ca6 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003c92: 683b ldr r3, [r7, #0] 8003c94: 015a lsls r2, r3, #5 8003c96: 69bb ldr r3, [r7, #24] 8003c98: 4413 add r3, r2 8003c9a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003c9e: 461a mov r2, r3 8003ca0: 2320 movs r3, #32 8003ca2: 6093 str r3, [r2, #8] 8003ca4: e098 b.n 8003dd8 } else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) 8003ca6: 693b ldr r3, [r7, #16] 8003ca8: f003 0328 and.w r3, r3, #40 @ 0x28 8003cac: 2b00 cmp r3, #0 8003cae: f040 8093 bne.w 8003dd8 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003cb2: 697b ldr r3, [r7, #20] 8003cb4: 4a4b ldr r2, [pc, #300] @ (8003de4 ) 8003cb6: 4293 cmp r3, r2 8003cb8: d90f bls.n 8003cda ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003cba: 693b ldr r3, [r7, #16] 8003cbc: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003cc0: 2b00 cmp r3, #0 8003cc2: d00a beq.n 8003cda { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003cc4: 683b ldr r3, [r7, #0] 8003cc6: 015a lsls r2, r3, #5 8003cc8: 69bb ldr r3, [r7, #24] 8003cca: 4413 add r3, r2 8003ccc: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003cd0: 461a mov r2, r3 8003cd2: f44f 4300 mov.w r3, #32768 @ 0x8000 8003cd6: 6093 str r3, [r2, #8] 8003cd8: e07e b.n 8003dd8 } else { ep = &hpcd->OUT_ep[epnum]; 8003cda: 683a ldr r2, [r7, #0] 8003cdc: 4613 mov r3, r2 8003cde: 00db lsls r3, r3, #3 8003ce0: 4413 add r3, r2 8003ce2: 009b lsls r3, r3, #2 8003ce4: f503 7314 add.w r3, r3, #592 @ 0x250 8003ce8: 687a ldr r2, [r7, #4] 8003cea: 4413 add r3, r2 8003cec: 3304 adds r3, #4 8003cee: 60fb str r3, [r7, #12] /* out data packet received over EP */ ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 8003cf0: 68fb ldr r3, [r7, #12] 8003cf2: 6a1a ldr r2, [r3, #32] 8003cf4: 683b ldr r3, [r7, #0] 8003cf6: 0159 lsls r1, r3, #5 8003cf8: 69bb ldr r3, [r7, #24] 8003cfa: 440b add r3, r1 8003cfc: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003d00: 691b ldr r3, [r3, #16] 8003d02: f3c3 0312 ubfx r3, r3, #0, #19 8003d06: 1ad2 subs r2, r2, r3 8003d08: 68fb ldr r3, [r7, #12] 8003d0a: 615a str r2, [r3, #20] if (epnum == 0U) 8003d0c: 683b ldr r3, [r7, #0] 8003d0e: 2b00 cmp r3, #0 8003d10: d114 bne.n 8003d3c { if (ep->xfer_len == 0U) 8003d12: 68fb ldr r3, [r7, #12] 8003d14: 691b ldr r3, [r3, #16] 8003d16: 2b00 cmp r3, #0 8003d18: d109 bne.n 8003d2e { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003d1a: 687b ldr r3, [r7, #4] 8003d1c: 6818 ldr r0, [r3, #0] 8003d1e: 687b ldr r3, [r7, #4] 8003d20: f203 439c addw r3, r3, #1180 @ 0x49c 8003d24: 461a mov r2, r3 8003d26: 2101 movs r1, #1 8003d28: f004 fbf4 bl 8008514 8003d2c: e006 b.n 8003d3c } else { ep->xfer_buff += ep->xfer_count; 8003d2e: 68fb ldr r3, [r7, #12] 8003d30: 68da ldr r2, [r3, #12] 8003d32: 68fb ldr r3, [r7, #12] 8003d34: 695b ldr r3, [r3, #20] 8003d36: 441a add r2, r3 8003d38: 68fb ldr r3, [r7, #12] 8003d3a: 60da str r2, [r3, #12] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003d3c: 683b ldr r3, [r7, #0] 8003d3e: b2db uxtb r3, r3 8003d40: 4619 mov r1, r3 8003d42: 6878 ldr r0, [r7, #4] 8003d44: f006 fbc2 bl 800a4cc 8003d48: e046 b.n 8003dd8 /* ... */ } } else { if (gSNPSiD == USB_OTG_CORE_ID_310A) 8003d4a: 697b ldr r3, [r7, #20] 8003d4c: 4a26 ldr r2, [pc, #152] @ (8003de8 ) 8003d4e: 4293 cmp r3, r2 8003d50: d124 bne.n 8003d9c { /* StupPktRcvd = 1 this is a setup packet */ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) 8003d52: 693b ldr r3, [r7, #16] 8003d54: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003d58: 2b00 cmp r3, #0 8003d5a: d00a beq.n 8003d72 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003d5c: 683b ldr r3, [r7, #0] 8003d5e: 015a lsls r2, r3, #5 8003d60: 69bb ldr r3, [r7, #24] 8003d62: 4413 add r3, r2 8003d64: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003d68: 461a mov r2, r3 8003d6a: f44f 4300 mov.w r3, #32768 @ 0x8000 8003d6e: 6093 str r3, [r2, #8] 8003d70: e032 b.n 8003dd8 } else { if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8003d72: 693b ldr r3, [r7, #16] 8003d74: f003 0320 and.w r3, r3, #32 8003d78: 2b00 cmp r3, #0 8003d7a: d008 beq.n 8003d8e { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003d7c: 683b ldr r3, [r7, #0] 8003d7e: 015a lsls r2, r3, #5 8003d80: 69bb ldr r3, [r7, #24] 8003d82: 4413 add r3, r2 8003d84: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003d88: 461a mov r2, r3 8003d8a: 2320 movs r3, #32 8003d8c: 6093 str r3, [r2, #8] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003d8e: 683b ldr r3, [r7, #0] 8003d90: b2db uxtb r3, r3 8003d92: 4619 mov r1, r3 8003d94: 6878 ldr r0, [r7, #4] 8003d96: f006 fb99 bl 800a4cc 8003d9a: e01d b.n 8003dd8 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else { if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8003d9c: 683b ldr r3, [r7, #0] 8003d9e: 2b00 cmp r3, #0 8003da0: d114 bne.n 8003dcc 8003da2: 6879 ldr r1, [r7, #4] 8003da4: 683a ldr r2, [r7, #0] 8003da6: 4613 mov r3, r2 8003da8: 00db lsls r3, r3, #3 8003daa: 4413 add r3, r2 8003dac: 009b lsls r3, r3, #2 8003dae: 440b add r3, r1 8003db0: f503 7319 add.w r3, r3, #612 @ 0x264 8003db4: 681b ldr r3, [r3, #0] 8003db6: 2b00 cmp r3, #0 8003db8: d108 bne.n 8003dcc { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); 8003dba: 687b ldr r3, [r7, #4] 8003dbc: 6818 ldr r0, [r3, #0] 8003dbe: 687b ldr r3, [r7, #4] 8003dc0: f203 439c addw r3, r3, #1180 @ 0x49c 8003dc4: 461a mov r2, r3 8003dc6: 2100 movs r1, #0 8003dc8: f004 fba4 bl 8008514 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003dcc: 683b ldr r3, [r7, #0] 8003dce: b2db uxtb r3, r3 8003dd0: 4619 mov r1, r3 8003dd2: 6878 ldr r0, [r7, #4] 8003dd4: f006 fb7a bl 800a4cc #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } return HAL_OK; 8003dd8: 2300 movs r3, #0 } 8003dda: 4618 mov r0, r3 8003ddc: 3720 adds r7, #32 8003dde: 46bd mov sp, r7 8003de0: bd80 pop {r7, pc} 8003de2: bf00 nop 8003de4: 4f54300a .word 0x4f54300a 8003de8: 4f54310a .word 0x4f54310a 08003dec : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003dec: b580 push {r7, lr} 8003dee: b086 sub sp, #24 8003df0: af00 add r7, sp, #0 8003df2: 6078 str r0, [r7, #4] 8003df4: 6039 str r1, [r7, #0] const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003df6: 687b ldr r3, [r7, #4] 8003df8: 681b ldr r3, [r3, #0] 8003dfa: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003dfc: 697b ldr r3, [r7, #20] 8003dfe: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8003e00: 697b ldr r3, [r7, #20] 8003e02: 333c adds r3, #60 @ 0x3c 8003e04: 3304 adds r3, #4 8003e06: 681b ldr r3, [r3, #0] 8003e08: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003e0a: 683b ldr r3, [r7, #0] 8003e0c: 015a lsls r2, r3, #5 8003e0e: 693b ldr r3, [r7, #16] 8003e10: 4413 add r3, r2 8003e12: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003e16: 689b ldr r3, [r3, #8] 8003e18: 60bb str r3, [r7, #8] if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003e1a: 68fb ldr r3, [r7, #12] 8003e1c: 4a15 ldr r2, [pc, #84] @ (8003e74 ) 8003e1e: 4293 cmp r3, r2 8003e20: d90e bls.n 8003e40 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003e22: 68bb ldr r3, [r7, #8] 8003e24: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003e28: 2b00 cmp r3, #0 8003e2a: d009 beq.n 8003e40 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003e2c: 683b ldr r3, [r7, #0] 8003e2e: 015a lsls r2, r3, #5 8003e30: 693b ldr r3, [r7, #16] 8003e32: 4413 add r3, r2 8003e34: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003e38: 461a mov r2, r3 8003e3a: f44f 4300 mov.w r3, #32768 @ 0x8000 8003e3e: 6093 str r3, [r2, #8] /* Inform the upper layer that a setup packet is available */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 8003e40: 6878 ldr r0, [r7, #4] 8003e42: f006 fb31 bl 800a4a8 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) 8003e46: 68fb ldr r3, [r7, #12] 8003e48: 4a0a ldr r2, [pc, #40] @ (8003e74 ) 8003e4a: 4293 cmp r3, r2 8003e4c: d90c bls.n 8003e68 8003e4e: 687b ldr r3, [r7, #4] 8003e50: 799b ldrb r3, [r3, #6] 8003e52: 2b01 cmp r3, #1 8003e54: d108 bne.n 8003e68 { (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003e56: 687b ldr r3, [r7, #4] 8003e58: 6818 ldr r0, [r3, #0] 8003e5a: 687b ldr r3, [r7, #4] 8003e5c: f203 439c addw r3, r3, #1180 @ 0x49c 8003e60: 461a mov r2, r3 8003e62: 2101 movs r1, #1 8003e64: f004 fb56 bl 8008514 } return HAL_OK; 8003e68: 2300 movs r3, #0 } 8003e6a: 4618 mov r0, r3 8003e6c: 3718 adds r7, #24 8003e6e: 46bd mov sp, r7 8003e70: bd80 pop {r7, pc} 8003e72: bf00 nop 8003e74: 4f54300a .word 0x4f54300a 08003e78 : * @param fifo The number of Tx fifo * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { 8003e78: b480 push {r7} 8003e7a: b085 sub sp, #20 8003e7c: af00 add r7, sp, #0 8003e7e: 6078 str r0, [r7, #4] 8003e80: 460b mov r3, r1 8003e82: 70fb strb r3, [r7, #3] 8003e84: 4613 mov r3, r2 8003e86: 803b strh r3, [r7, #0] --> Txn should be configured with the minimum space of 16 words The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ Tx_Offset = hpcd->Instance->GRXFSIZ; 8003e88: 687b ldr r3, [r7, #4] 8003e8a: 681b ldr r3, [r3, #0] 8003e8c: 6a5b ldr r3, [r3, #36] @ 0x24 8003e8e: 60bb str r3, [r7, #8] if (fifo == 0U) 8003e90: 78fb ldrb r3, [r7, #3] 8003e92: 2b00 cmp r3, #0 8003e94: d107 bne.n 8003ea6 { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; 8003e96: 883b ldrh r3, [r7, #0] 8003e98: 0419 lsls r1, r3, #16 8003e9a: 687b ldr r3, [r7, #4] 8003e9c: 681b ldr r3, [r3, #0] 8003e9e: 68ba ldr r2, [r7, #8] 8003ea0: 430a orrs r2, r1 8003ea2: 629a str r2, [r3, #40] @ 0x28 8003ea4: e028 b.n 8003ef8 } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; 8003ea6: 687b ldr r3, [r7, #4] 8003ea8: 681b ldr r3, [r3, #0] 8003eaa: 6a9b ldr r3, [r3, #40] @ 0x28 8003eac: 0c1b lsrs r3, r3, #16 8003eae: 68ba ldr r2, [r7, #8] 8003eb0: 4413 add r3, r2 8003eb2: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8003eb4: 2300 movs r3, #0 8003eb6: 73fb strb r3, [r7, #15] 8003eb8: e00d b.n 8003ed6 { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); 8003eba: 687b ldr r3, [r7, #4] 8003ebc: 681a ldr r2, [r3, #0] 8003ebe: 7bfb ldrb r3, [r7, #15] 8003ec0: 3340 adds r3, #64 @ 0x40 8003ec2: 009b lsls r3, r3, #2 8003ec4: 4413 add r3, r2 8003ec6: 685b ldr r3, [r3, #4] 8003ec8: 0c1b lsrs r3, r3, #16 8003eca: 68ba ldr r2, [r7, #8] 8003ecc: 4413 add r3, r2 8003ece: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8003ed0: 7bfb ldrb r3, [r7, #15] 8003ed2: 3301 adds r3, #1 8003ed4: 73fb strb r3, [r7, #15] 8003ed6: 7bfa ldrb r2, [r7, #15] 8003ed8: 78fb ldrb r3, [r7, #3] 8003eda: 3b01 subs r3, #1 8003edc: 429a cmp r2, r3 8003ede: d3ec bcc.n 8003eba } /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; 8003ee0: 883b ldrh r3, [r7, #0] 8003ee2: 0418 lsls r0, r3, #16 8003ee4: 687b ldr r3, [r7, #4] 8003ee6: 6819 ldr r1, [r3, #0] 8003ee8: 78fb ldrb r3, [r7, #3] 8003eea: 3b01 subs r3, #1 8003eec: 68ba ldr r2, [r7, #8] 8003eee: 4302 orrs r2, r0 8003ef0: 3340 adds r3, #64 @ 0x40 8003ef2: 009b lsls r3, r3, #2 8003ef4: 440b add r3, r1 8003ef6: 605a str r2, [r3, #4] } return HAL_OK; 8003ef8: 2300 movs r3, #0 } 8003efa: 4618 mov r0, r3 8003efc: 3714 adds r7, #20 8003efe: 46bd mov sp, r7 8003f00: f85d 7b04 ldr.w r7, [sp], #4 8003f04: 4770 bx lr 08003f06 : * @param hpcd PCD handle * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { 8003f06: b480 push {r7} 8003f08: b083 sub sp, #12 8003f0a: af00 add r7, sp, #0 8003f0c: 6078 str r0, [r7, #4] 8003f0e: 460b mov r3, r1 8003f10: 807b strh r3, [r7, #2] hpcd->Instance->GRXFSIZ = size; 8003f12: 687b ldr r3, [r7, #4] 8003f14: 681b ldr r3, [r3, #0] 8003f16: 887a ldrh r2, [r7, #2] 8003f18: 625a str r2, [r3, #36] @ 0x24 return HAL_OK; 8003f1a: 2300 movs r3, #0 } 8003f1c: 4618 mov r0, r3 8003f1e: 370c adds r7, #12 8003f20: 46bd mov sp, r7 8003f22: f85d 7b04 ldr.w r7, [sp], #4 8003f26: 4770 bx lr 08003f28 : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 8003f28: b480 push {r7} 8003f2a: b085 sub sp, #20 8003f2c: af00 add r7, sp, #0 8003f2e: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003f30: 687b ldr r3, [r7, #4] 8003f32: 681b ldr r3, [r3, #0] 8003f34: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 8003f36: 687b ldr r3, [r7, #4] 8003f38: 2201 movs r2, #1 8003f3a: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8 hpcd->LPM_State = LPM_L0; 8003f3e: 687b ldr r3, [r7, #4] 8003f40: 2200 movs r2, #0 8003f42: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 8003f46: 68fb ldr r3, [r7, #12] 8003f48: 699b ldr r3, [r3, #24] 8003f4a: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 8003f4e: 68fb ldr r3, [r7, #12] 8003f50: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 8003f52: 68fb ldr r3, [r7, #12] 8003f54: 6d5b ldr r3, [r3, #84] @ 0x54 8003f56: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003f5a: f043 0303 orr.w r3, r3, #3 8003f5e: 68fa ldr r2, [r7, #12] 8003f60: 6553 str r3, [r2, #84] @ 0x54 return HAL_OK; 8003f62: 2300 movs r3, #0 } 8003f64: 4618 mov r0, r3 8003f66: 3714 adds r7, #20 8003f68: 46bd mov sp, r7 8003f6a: f85d 7b04 ldr.w r7, [sp], #4 8003f6e: 4770 bx lr 08003f70 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003f70: b580 push {r7, lr} 8003f72: b084 sub sp, #16 8003f74: af00 add r7, sp, #0 8003f76: 6078 str r0, [r7, #4] 8003f78: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8003f7a: 687b ldr r3, [r7, #4] 8003f7c: 2b00 cmp r3, #0 8003f7e: d101 bne.n 8003f84 { return HAL_ERROR; 8003f80: 2301 movs r3, #1 8003f82: e0cc b.n 800411e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8003f84: 4b68 ldr r3, [pc, #416] @ (8004128 ) 8003f86: 681b ldr r3, [r3, #0] 8003f88: f003 030f and.w r3, r3, #15 8003f8c: 683a ldr r2, [r7, #0] 8003f8e: 429a cmp r2, r3 8003f90: d90c bls.n 8003fac { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003f92: 4b65 ldr r3, [pc, #404] @ (8004128 ) 8003f94: 683a ldr r2, [r7, #0] 8003f96: b2d2 uxtb r2, r2 8003f98: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8003f9a: 4b63 ldr r3, [pc, #396] @ (8004128 ) 8003f9c: 681b ldr r3, [r3, #0] 8003f9e: f003 030f and.w r3, r3, #15 8003fa2: 683a ldr r2, [r7, #0] 8003fa4: 429a cmp r2, r3 8003fa6: d001 beq.n 8003fac { return HAL_ERROR; 8003fa8: 2301 movs r3, #1 8003faa: e0b8 b.n 800411e } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003fac: 687b ldr r3, [r7, #4] 8003fae: 681b ldr r3, [r3, #0] 8003fb0: f003 0302 and.w r3, r3, #2 8003fb4: 2b00 cmp r3, #0 8003fb6: d020 beq.n 8003ffa { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003fb8: 687b ldr r3, [r7, #4] 8003fba: 681b ldr r3, [r3, #0] 8003fbc: f003 0304 and.w r3, r3, #4 8003fc0: 2b00 cmp r3, #0 8003fc2: d005 beq.n 8003fd0 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8003fc4: 4b59 ldr r3, [pc, #356] @ (800412c ) 8003fc6: 689b ldr r3, [r3, #8] 8003fc8: 4a58 ldr r2, [pc, #352] @ (800412c ) 8003fca: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 8003fce: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003fd0: 687b ldr r3, [r7, #4] 8003fd2: 681b ldr r3, [r3, #0] 8003fd4: f003 0308 and.w r3, r3, #8 8003fd8: 2b00 cmp r3, #0 8003fda: d005 beq.n 8003fe8 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8003fdc: 4b53 ldr r3, [pc, #332] @ (800412c ) 8003fde: 689b ldr r3, [r3, #8] 8003fe0: 4a52 ldr r2, [pc, #328] @ (800412c ) 8003fe2: f443 4360 orr.w r3, r3, #57344 @ 0xe000 8003fe6: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003fe8: 4b50 ldr r3, [pc, #320] @ (800412c ) 8003fea: 689b ldr r3, [r3, #8] 8003fec: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8003ff0: 687b ldr r3, [r7, #4] 8003ff2: 689b ldr r3, [r3, #8] 8003ff4: 494d ldr r1, [pc, #308] @ (800412c ) 8003ff6: 4313 orrs r3, r2 8003ff8: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003ffa: 687b ldr r3, [r7, #4] 8003ffc: 681b ldr r3, [r3, #0] 8003ffe: f003 0301 and.w r3, r3, #1 8004002: 2b00 cmp r3, #0 8004004: d044 beq.n 8004090 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004006: 687b ldr r3, [r7, #4] 8004008: 685b ldr r3, [r3, #4] 800400a: 2b01 cmp r3, #1 800400c: d107 bne.n 800401e { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800400e: 4b47 ldr r3, [pc, #284] @ (800412c ) 8004010: 681b ldr r3, [r3, #0] 8004012: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004016: 2b00 cmp r3, #0 8004018: d119 bne.n 800404e { return HAL_ERROR; 800401a: 2301 movs r3, #1 800401c: e07f b.n 800411e } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 800401e: 687b ldr r3, [r7, #4] 8004020: 685b ldr r3, [r3, #4] 8004022: 2b02 cmp r3, #2 8004024: d003 beq.n 800402e (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 8004026: 687b ldr r3, [r7, #4] 8004028: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 800402a: 2b03 cmp r3, #3 800402c: d107 bne.n 800403e { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800402e: 4b3f ldr r3, [pc, #252] @ (800412c ) 8004030: 681b ldr r3, [r3, #0] 8004032: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004036: 2b00 cmp r3, #0 8004038: d109 bne.n 800404e { return HAL_ERROR; 800403a: 2301 movs r3, #1 800403c: e06f b.n 800411e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800403e: 4b3b ldr r3, [pc, #236] @ (800412c ) 8004040: 681b ldr r3, [r3, #0] 8004042: f003 0302 and.w r3, r3, #2 8004046: 2b00 cmp r3, #0 8004048: d101 bne.n 800404e { return HAL_ERROR; 800404a: 2301 movs r3, #1 800404c: e067 b.n 800411e } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 800404e: 4b37 ldr r3, [pc, #220] @ (800412c ) 8004050: 689b ldr r3, [r3, #8] 8004052: f023 0203 bic.w r2, r3, #3 8004056: 687b ldr r3, [r7, #4] 8004058: 685b ldr r3, [r3, #4] 800405a: 4934 ldr r1, [pc, #208] @ (800412c ) 800405c: 4313 orrs r3, r2 800405e: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004060: f7fd fcb2 bl 80019c8 8004064: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004066: e00a b.n 800407e { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8004068: f7fd fcae bl 80019c8 800406c: 4602 mov r2, r0 800406e: 68fb ldr r3, [r7, #12] 8004070: 1ad3 subs r3, r2, r3 8004072: f241 3288 movw r2, #5000 @ 0x1388 8004076: 4293 cmp r3, r2 8004078: d901 bls.n 800407e { return HAL_TIMEOUT; 800407a: 2303 movs r3, #3 800407c: e04f b.n 800411e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800407e: 4b2b ldr r3, [pc, #172] @ (800412c ) 8004080: 689b ldr r3, [r3, #8] 8004082: f003 020c and.w r2, r3, #12 8004086: 687b ldr r3, [r7, #4] 8004088: 685b ldr r3, [r3, #4] 800408a: 009b lsls r3, r3, #2 800408c: 429a cmp r2, r3 800408e: d1eb bne.n 8004068 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8004090: 4b25 ldr r3, [pc, #148] @ (8004128 ) 8004092: 681b ldr r3, [r3, #0] 8004094: f003 030f and.w r3, r3, #15 8004098: 683a ldr r2, [r7, #0] 800409a: 429a cmp r2, r3 800409c: d20c bcs.n 80040b8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800409e: 4b22 ldr r3, [pc, #136] @ (8004128 ) 80040a0: 683a ldr r2, [r7, #0] 80040a2: b2d2 uxtb r2, r2 80040a4: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80040a6: 4b20 ldr r3, [pc, #128] @ (8004128 ) 80040a8: 681b ldr r3, [r3, #0] 80040aa: f003 030f and.w r3, r3, #15 80040ae: 683a ldr r2, [r7, #0] 80040b0: 429a cmp r2, r3 80040b2: d001 beq.n 80040b8 { return HAL_ERROR; 80040b4: 2301 movs r3, #1 80040b6: e032 b.n 800411e } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80040b8: 687b ldr r3, [r7, #4] 80040ba: 681b ldr r3, [r3, #0] 80040bc: f003 0304 and.w r3, r3, #4 80040c0: 2b00 cmp r3, #0 80040c2: d008 beq.n 80040d6 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80040c4: 4b19 ldr r3, [pc, #100] @ (800412c ) 80040c6: 689b ldr r3, [r3, #8] 80040c8: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 80040cc: 687b ldr r3, [r7, #4] 80040ce: 68db ldr r3, [r3, #12] 80040d0: 4916 ldr r1, [pc, #88] @ (800412c ) 80040d2: 4313 orrs r3, r2 80040d4: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80040d6: 687b ldr r3, [r7, #4] 80040d8: 681b ldr r3, [r3, #0] 80040da: f003 0308 and.w r3, r3, #8 80040de: 2b00 cmp r3, #0 80040e0: d009 beq.n 80040f6 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 80040e2: 4b12 ldr r3, [pc, #72] @ (800412c ) 80040e4: 689b ldr r3, [r3, #8] 80040e6: f423 4260 bic.w r2, r3, #57344 @ 0xe000 80040ea: 687b ldr r3, [r7, #4] 80040ec: 691b ldr r3, [r3, #16] 80040ee: 00db lsls r3, r3, #3 80040f0: 490e ldr r1, [pc, #56] @ (800412c ) 80040f2: 4313 orrs r3, r2 80040f4: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 80040f6: f000 fb7f bl 80047f8 80040fa: 4602 mov r2, r0 80040fc: 4b0b ldr r3, [pc, #44] @ (800412c ) 80040fe: 689b ldr r3, [r3, #8] 8004100: 091b lsrs r3, r3, #4 8004102: f003 030f and.w r3, r3, #15 8004106: 490a ldr r1, [pc, #40] @ (8004130 ) 8004108: 5ccb ldrb r3, [r1, r3] 800410a: fa22 f303 lsr.w r3, r2, r3 800410e: 4a09 ldr r2, [pc, #36] @ (8004134 ) 8004110: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); 8004112: 4b09 ldr r3, [pc, #36] @ (8004138 ) 8004114: 681b ldr r3, [r3, #0] 8004116: 4618 mov r0, r3 8004118: f7fd fc12 bl 8001940 return HAL_OK; 800411c: 2300 movs r3, #0 } 800411e: 4618 mov r0, r3 8004120: 3710 adds r7, #16 8004122: 46bd mov sp, r7 8004124: bd80 pop {r7, pc} 8004126: bf00 nop 8004128: 40023c00 .word 0x40023c00 800412c: 40023800 .word 0x40023800 8004130: 0800ab68 .word 0x0800ab68 8004134: 20000090 .word 0x20000090 8004138: 20000094 .word 0x20000094 0800413c : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 800413c: b480 push {r7} 800413e: af00 add r7, sp, #0 return SystemCoreClock; 8004140: 4b03 ldr r3, [pc, #12] @ (8004150 ) 8004142: 681b ldr r3, [r3, #0] } 8004144: 4618 mov r0, r3 8004146: 46bd mov sp, r7 8004148: f85d 7b04 ldr.w r7, [sp], #4 800414c: 4770 bx lr 800414e: bf00 nop 8004150: 20000090 .word 0x20000090 08004154 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8004154: b580 push {r7, lr} 8004156: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8004158: f7ff fff0 bl 800413c 800415c: 4602 mov r2, r0 800415e: 4b05 ldr r3, [pc, #20] @ (8004174 ) 8004160: 689b ldr r3, [r3, #8] 8004162: 0a9b lsrs r3, r3, #10 8004164: f003 0307 and.w r3, r3, #7 8004168: 4903 ldr r1, [pc, #12] @ (8004178 ) 800416a: 5ccb ldrb r3, [r1, r3] 800416c: fa22 f303 lsr.w r3, r2, r3 } 8004170: 4618 mov r0, r3 8004172: bd80 pop {r7, pc} 8004174: 40023800 .word 0x40023800 8004178: 0800ab78 .word 0x0800ab78 0800417c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800417c: b580 push {r7, lr} 800417e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8004180: f7ff ffdc bl 800413c 8004184: 4602 mov r2, r0 8004186: 4b05 ldr r3, [pc, #20] @ (800419c ) 8004188: 689b ldr r3, [r3, #8] 800418a: 0b5b lsrs r3, r3, #13 800418c: f003 0307 and.w r3, r3, #7 8004190: 4903 ldr r1, [pc, #12] @ (80041a0 ) 8004192: 5ccb ldrb r3, [r1, r3] 8004194: fa22 f303 lsr.w r3, r2, r3 } 8004198: 4618 mov r0, r3 800419a: bd80 pop {r7, pc} 800419c: 40023800 .word 0x40023800 80041a0: 0800ab78 .word 0x0800ab78 080041a4 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80041a4: b580 push {r7, lr} 80041a6: b08c sub sp, #48 @ 0x30 80041a8: af00 add r7, sp, #0 80041aa: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80041ac: 2300 movs r3, #0 80041ae: 627b str r3, [r7, #36] @ 0x24 uint32_t tmpreg1 = 0U; 80041b0: 2300 movs r3, #0 80041b2: 623b str r3, [r7, #32] uint32_t plli2sp = 0U; 80041b4: 2300 movs r3, #0 80041b6: 61fb str r3, [r7, #28] uint32_t plli2sq = 0U; 80041b8: 2300 movs r3, #0 80041ba: 61bb str r3, [r7, #24] uint32_t plli2sr = 0U; 80041bc: 2300 movs r3, #0 80041be: 617b str r3, [r7, #20] uint32_t pllsaip = 0U; 80041c0: 2300 movs r3, #0 80041c2: 613b str r3, [r7, #16] uint32_t pllsaiq = 0U; 80041c4: 2300 movs r3, #0 80041c6: 60fb str r3, [r7, #12] uint32_t plli2sused = 0U; 80041c8: 2300 movs r3, #0 80041ca: 62fb str r3, [r7, #44] @ 0x2c uint32_t pllsaiused = 0U; 80041cc: 2300 movs r3, #0 80041ce: 62bb str r3, [r7, #40] @ 0x28 /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------ I2S APB1 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) 80041d0: 687b ldr r3, [r7, #4] 80041d2: 681b ldr r3, [r3, #0] 80041d4: f003 0301 and.w r3, r3, #1 80041d8: 2b00 cmp r3, #0 80041da: d010 beq.n 80041fe { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); 80041dc: 4b6f ldr r3, [pc, #444] @ (800439c ) 80041de: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80041e2: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000 80041e6: 687b ldr r3, [r7, #4] 80041e8: 6b9b ldr r3, [r3, #56] @ 0x38 80041ea: 496c ldr r1, [pc, #432] @ (800439c ) 80041ec: 4313 orrs r3, r2 80041ee: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) 80041f2: 687b ldr r3, [r7, #4] 80041f4: 6b9b ldr r3, [r3, #56] @ 0x38 80041f6: 2b00 cmp r3, #0 80041f8: d101 bne.n 80041fe { plli2sused = 1U; 80041fa: 2301 movs r3, #1 80041fc: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*---------------------------- I2S APB2 configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) 80041fe: 687b ldr r3, [r7, #4] 8004200: 681b ldr r3, [r3, #0] 8004202: f003 0302 and.w r3, r3, #2 8004206: 2b00 cmp r3, #0 8004208: d010 beq.n 800422c { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); 800420a: 4b64 ldr r3, [pc, #400] @ (800439c ) 800420c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004210: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000 8004214: 687b ldr r3, [r7, #4] 8004216: 6bdb ldr r3, [r3, #60] @ 0x3c 8004218: 4960 ldr r1, [pc, #384] @ (800439c ) 800421a: 4313 orrs r3, r2 800421c: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) 8004220: 687b ldr r3, [r7, #4] 8004222: 6bdb ldr r3, [r3, #60] @ 0x3c 8004224: 2b00 cmp r3, #0 8004226: d101 bne.n 800422c { plli2sused = 1U; 8004228: 2301 movs r3, #1 800422a: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*--------------------------- SAI1 configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) 800422c: 687b ldr r3, [r7, #4] 800422e: 681b ldr r3, [r3, #0] 8004230: f003 0304 and.w r3, r3, #4 8004234: 2b00 cmp r3, #0 8004236: d017 beq.n 8004268 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8004238: 4b58 ldr r3, [pc, #352] @ (800439c ) 800423a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800423e: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 8004242: 687b ldr r3, [r7, #4] 8004244: 6b1b ldr r3, [r3, #48] @ 0x30 8004246: 4955 ldr r1, [pc, #340] @ (800439c ) 8004248: 4313 orrs r3, r2 800424a: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) 800424e: 687b ldr r3, [r7, #4] 8004250: 6b1b ldr r3, [r3, #48] @ 0x30 8004252: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8004256: d101 bne.n 800425c { plli2sused = 1U; 8004258: 2301 movs r3, #1 800425a: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) 800425c: 687b ldr r3, [r7, #4] 800425e: 6b1b ldr r3, [r3, #48] @ 0x30 8004260: 2b00 cmp r3, #0 8004262: d101 bne.n 8004268 { pllsaiused = 1U; 8004264: 2301 movs r3, #1 8004266: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*-------------------------- SAI2 configuration ----------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) 8004268: 687b ldr r3, [r7, #4] 800426a: 681b ldr r3, [r3, #0] 800426c: f003 0308 and.w r3, r3, #8 8004270: 2b00 cmp r3, #0 8004272: d017 beq.n 80042a4 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 8004274: 4b49 ldr r3, [pc, #292] @ (800439c ) 8004276: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800427a: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 800427e: 687b ldr r3, [r7, #4] 8004280: 6b5b ldr r3, [r3, #52] @ 0x34 8004282: 4946 ldr r1, [pc, #280] @ (800439c ) 8004284: 4313 orrs r3, r2 8004286: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) 800428a: 687b ldr r3, [r7, #4] 800428c: 6b5b ldr r3, [r3, #52] @ 0x34 800428e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004292: d101 bne.n 8004298 { plli2sused = 1U; 8004294: 2301 movs r3, #1 8004296: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) 8004298: 687b ldr r3, [r7, #4] 800429a: 6b5b ldr r3, [r3, #52] @ 0x34 800429c: 2b00 cmp r3, #0 800429e: d101 bne.n 80042a4 { pllsaiused = 1U; 80042a0: 2301 movs r3, #1 80042a2: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- RTC configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 80042a4: 687b ldr r3, [r7, #4] 80042a6: 681b ldr r3, [r3, #0] 80042a8: f003 0320 and.w r3, r3, #32 80042ac: 2b00 cmp r3, #0 80042ae: f000 808a beq.w 80043c6 { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 80042b2: 2300 movs r3, #0 80042b4: 60bb str r3, [r7, #8] 80042b6: 4b39 ldr r3, [pc, #228] @ (800439c ) 80042b8: 6c1b ldr r3, [r3, #64] @ 0x40 80042ba: 4a38 ldr r2, [pc, #224] @ (800439c ) 80042bc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80042c0: 6413 str r3, [r2, #64] @ 0x40 80042c2: 4b36 ldr r3, [pc, #216] @ (800439c ) 80042c4: 6c1b ldr r3, [r3, #64] @ 0x40 80042c6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80042ca: 60bb str r3, [r7, #8] 80042cc: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; 80042ce: 4b34 ldr r3, [pc, #208] @ (80043a0 ) 80042d0: 681b ldr r3, [r3, #0] 80042d2: 4a33 ldr r2, [pc, #204] @ (80043a0 ) 80042d4: f443 7380 orr.w r3, r3, #256 @ 0x100 80042d8: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 80042da: f7fd fb75 bl 80019c8 80042de: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR & PWR_CR_DBP) == RESET) 80042e0: e008 b.n 80042f4 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80042e2: f7fd fb71 bl 80019c8 80042e6: 4602 mov r2, r0 80042e8: 6a7b ldr r3, [r7, #36] @ 0x24 80042ea: 1ad3 subs r3, r2, r3 80042ec: 2b02 cmp r3, #2 80042ee: d901 bls.n 80042f4 { return HAL_TIMEOUT; 80042f0: 2303 movs r3, #3 80042f2: e278 b.n 80047e6 while ((PWR->CR & PWR_CR_DBP) == RESET) 80042f4: 4b2a ldr r3, [pc, #168] @ (80043a0 ) 80042f6: 681b ldr r3, [r3, #0] 80042f8: f403 7380 and.w r3, r3, #256 @ 0x100 80042fc: 2b00 cmp r3, #0 80042fe: d0f0 beq.n 80042e2 } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); 8004300: 4b26 ldr r3, [pc, #152] @ (800439c ) 8004302: 6f1b ldr r3, [r3, #112] @ 0x70 8004304: f403 7340 and.w r3, r3, #768 @ 0x300 8004308: 623b str r3, [r7, #32] if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 800430a: 6a3b ldr r3, [r7, #32] 800430c: 2b00 cmp r3, #0 800430e: d02f beq.n 8004370 8004310: 687b ldr r3, [r7, #4] 8004312: 6c1b ldr r3, [r3, #64] @ 0x40 8004314: f403 7340 and.w r3, r3, #768 @ 0x300 8004318: 6a3a ldr r2, [r7, #32] 800431a: 429a cmp r2, r3 800431c: d028 beq.n 8004370 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800431e: 4b1f ldr r3, [pc, #124] @ (800439c ) 8004320: 6f1b ldr r3, [r3, #112] @ 0x70 8004322: f423 7340 bic.w r3, r3, #768 @ 0x300 8004326: 623b str r3, [r7, #32] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8004328: 4b1e ldr r3, [pc, #120] @ (80043a4 ) 800432a: 2201 movs r2, #1 800432c: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 800432e: 4b1d ldr r3, [pc, #116] @ (80043a4 ) 8004330: 2200 movs r2, #0 8004332: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; 8004334: 4a19 ldr r2, [pc, #100] @ (800439c ) 8004336: 6a3b ldr r3, [r7, #32] 8004338: 6713 str r3, [r2, #112] @ 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 800433a: 4b18 ldr r3, [pc, #96] @ (800439c ) 800433c: 6f1b ldr r3, [r3, #112] @ 0x70 800433e: f003 0301 and.w r3, r3, #1 8004342: 2b01 cmp r3, #1 8004344: d114 bne.n 8004370 { /* Get tick */ tickstart = HAL_GetTick(); 8004346: f7fd fb3f bl 80019c8 800434a: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800434c: e00a b.n 8004364 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800434e: f7fd fb3b bl 80019c8 8004352: 4602 mov r2, r0 8004354: 6a7b ldr r3, [r7, #36] @ 0x24 8004356: 1ad3 subs r3, r2, r3 8004358: f241 3288 movw r2, #5000 @ 0x1388 800435c: 4293 cmp r3, r2 800435e: d901 bls.n 8004364 { return HAL_TIMEOUT; 8004360: 2303 movs r3, #3 8004362: e240 b.n 80047e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004364: 4b0d ldr r3, [pc, #52] @ (800439c ) 8004366: 6f1b ldr r3, [r3, #112] @ 0x70 8004368: f003 0302 and.w r3, r3, #2 800436c: 2b00 cmp r3, #0 800436e: d0ee beq.n 800434e } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8004370: 687b ldr r3, [r7, #4] 8004372: 6c1b ldr r3, [r3, #64] @ 0x40 8004374: f403 7340 and.w r3, r3, #768 @ 0x300 8004378: f5b3 7f40 cmp.w r3, #768 @ 0x300 800437c: d114 bne.n 80043a8 800437e: 4b07 ldr r3, [pc, #28] @ (800439c ) 8004380: 689b ldr r3, [r3, #8] 8004382: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000 8004386: 687b ldr r3, [r7, #4] 8004388: 6c1b ldr r3, [r3, #64] @ 0x40 800438a: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 800438e: f423 7340 bic.w r3, r3, #768 @ 0x300 8004392: 4902 ldr r1, [pc, #8] @ (800439c ) 8004394: 4313 orrs r3, r2 8004396: 608b str r3, [r1, #8] 8004398: e00c b.n 80043b4 800439a: bf00 nop 800439c: 40023800 .word 0x40023800 80043a0: 40007000 .word 0x40007000 80043a4: 42470e40 .word 0x42470e40 80043a8: 4b4a ldr r3, [pc, #296] @ (80044d4 ) 80043aa: 689b ldr r3, [r3, #8] 80043ac: 4a49 ldr r2, [pc, #292] @ (80044d4 ) 80043ae: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000 80043b2: 6093 str r3, [r2, #8] 80043b4: 4b47 ldr r3, [pc, #284] @ (80044d4 ) 80043b6: 6f1a ldr r2, [r3, #112] @ 0x70 80043b8: 687b ldr r3, [r7, #4] 80043ba: 6c1b ldr r3, [r3, #64] @ 0x40 80043bc: f3c3 030b ubfx r3, r3, #0, #12 80043c0: 4944 ldr r1, [pc, #272] @ (80044d4 ) 80043c2: 4313 orrs r3, r2 80043c4: 670b str r3, [r1, #112] @ 0x70 } /*--------------------------------------------------------------------------*/ /*---------------------------- TIM configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 80043c6: 687b ldr r3, [r7, #4] 80043c8: 681b ldr r3, [r3, #0] 80043ca: f003 0310 and.w r3, r3, #16 80043ce: 2b00 cmp r3, #0 80043d0: d004 beq.n 80043dc { /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 80043d2: 687b ldr r3, [r7, #4] 80043d4: f893 2058 ldrb.w r2, [r3, #88] @ 0x58 80043d8: 4b3f ldr r3, [pc, #252] @ (80044d8 ) 80043da: 601a str r2, [r3, #0] } /*--------------------------------------------------------------------------*/ /*---------------------------- FMPI2C1 Configuration -----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) 80043dc: 687b ldr r3, [r7, #4] 80043de: 681b ldr r3, [r3, #0] 80043e0: f003 0380 and.w r3, r3, #128 @ 0x80 80043e4: 2b00 cmp r3, #0 80043e6: d00a beq.n 80043fe { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); 80043e8: 4b3a ldr r3, [pc, #232] @ (80044d4 ) 80043ea: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80043ee: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 80043f2: 687b ldr r3, [r7, #4] 80043f4: 6cdb ldr r3, [r3, #76] @ 0x4c 80043f6: 4937 ldr r1, [pc, #220] @ (80044d4 ) 80043f8: 4313 orrs r3, r2 80043fa: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ CEC Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 80043fe: 687b ldr r3, [r7, #4] 8004400: 681b ldr r3, [r3, #0] 8004402: f003 0340 and.w r3, r3, #64 @ 0x40 8004406: 2b00 cmp r3, #0 8004408: d00a beq.n 8004420 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800440a: 4b32 ldr r3, [pc, #200] @ (80044d4 ) 800440c: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004410: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000 8004414: 687b ldr r3, [r7, #4] 8004416: 6c9b ldr r3, [r3, #72] @ 0x48 8004418: 492e ldr r1, [pc, #184] @ (80044d4 ) 800441a: 4313 orrs r3, r2 800441c: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*----------------------------- CLK48 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 8004420: 687b ldr r3, [r7, #4] 8004422: 681b ldr r3, [r3, #0] 8004424: f403 7380 and.w r3, r3, #256 @ 0x100 8004428: 2b00 cmp r3, #0 800442a: d011 beq.n 8004450 { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); 800442c: 4b29 ldr r3, [pc, #164] @ (80044d4 ) 800442e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004432: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000 8004436: 687b ldr r3, [r7, #4] 8004438: 6d5b ldr r3, [r3, #84] @ 0x54 800443a: 4926 ldr r1, [pc, #152] @ (80044d4 ) 800443c: 4313 orrs r3, r2 800443e: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLSAI when it's used as clock source for CLK48 */ if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) 8004442: 687b ldr r3, [r7, #4] 8004444: 6d5b ldr r3, [r3, #84] @ 0x54 8004446: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800444a: d101 bne.n 8004450 { pllsaiused = 1U; 800444c: 2301 movs r3, #1 800444e: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- SDIO Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) 8004450: 687b ldr r3, [r7, #4] 8004452: 681b ldr r3, [r3, #0] 8004454: f403 7300 and.w r3, r3, #512 @ 0x200 8004458: 2b00 cmp r3, #0 800445a: d00a beq.n 8004472 { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); 800445c: 4b1d ldr r3, [pc, #116] @ (80044d4 ) 800445e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004462: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000 8004466: 687b ldr r3, [r7, #4] 8004468: 6c5b ldr r3, [r3, #68] @ 0x44 800446a: 491a ldr r1, [pc, #104] @ (80044d4 ) 800446c: 4313 orrs r3, r2 800446e: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ SPDIFRX Configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8004472: 687b ldr r3, [r7, #4] 8004474: 681b ldr r3, [r3, #0] 8004476: f403 6380 and.w r3, r3, #1024 @ 0x400 800447a: 2b00 cmp r3, #0 800447c: d011 beq.n 80044a2 { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); /* Configure the SPDIFRX clock source */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); 800447e: 4b15 ldr r3, [pc, #84] @ (80044d4 ) 8004480: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004484: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000 8004488: 687b ldr r3, [r7, #4] 800448a: 6d1b ldr r3, [r3, #80] @ 0x50 800448c: 4911 ldr r1, [pc, #68] @ (80044d4 ) 800448e: 4313 orrs r3, r2 8004490: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) 8004494: 687b ldr r3, [r7, #4] 8004496: 6d1b ldr r3, [r3, #80] @ 0x50 8004498: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800449c: d101 bne.n 80044a2 { plli2sused = 1U; 800449e: 2301 movs r3, #1 80044a0: 62fb str r3, [r7, #44] @ 0x2c /*--------------------------------------------------------------------------*/ /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) 80044a2: 6afb ldr r3, [r7, #44] @ 0x2c 80044a4: 2b01 cmp r3, #1 80044a6: d005 beq.n 80044b4 80044a8: 687b ldr r3, [r7, #4] 80044aa: 681b ldr r3, [r3, #0] 80044ac: f5b3 6f00 cmp.w r3, #2048 @ 0x800 80044b0: f040 80ff bne.w 80046b2 { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 80044b4: 4b09 ldr r3, [pc, #36] @ (80044dc ) 80044b6: 2200 movs r2, #0 80044b8: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80044ba: f7fd fa85 bl 80019c8 80044be: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 80044c0: e00e b.n 80044e0 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 80044c2: f7fd fa81 bl 80019c8 80044c6: 4602 mov r2, r0 80044c8: 6a7b ldr r3, [r7, #36] @ 0x24 80044ca: 1ad3 subs r3, r2, r3 80044cc: 2b02 cmp r3, #2 80044ce: d907 bls.n 80044e0 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 80044d0: 2303 movs r3, #3 80044d2: e188 b.n 80047e6 80044d4: 40023800 .word 0x40023800 80044d8: 424711e0 .word 0x424711e0 80044dc: 42470068 .word 0x42470068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 80044e0: 4b7e ldr r3, [pc, #504] @ (80046dc ) 80044e2: 681b ldr r3, [r3, #0] 80044e4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80044e8: 2b00 cmp r3, #0 80044ea: d1ea bne.n 80044c2 /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) 80044ec: 687b ldr r3, [r7, #4] 80044ee: 681b ldr r3, [r3, #0] 80044f0: f003 0301 and.w r3, r3, #1 80044f4: 2b00 cmp r3, #0 80044f6: d003 beq.n 8004500 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 80044f8: 687b ldr r3, [r7, #4] 80044fa: 6b9b ldr r3, [r3, #56] @ 0x38 80044fc: 2b00 cmp r3, #0 80044fe: d009 beq.n 8004514 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 8004500: 687b ldr r3, [r7, #4] 8004502: 681b ldr r3, [r3, #0] 8004504: f003 0302 and.w r3, r3, #2 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8004508: 2b00 cmp r3, #0 800450a: d028 beq.n 800455e ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 800450c: 687b ldr r3, [r7, #4] 800450e: 6bdb ldr r3, [r3, #60] @ 0x3c 8004510: 2b00 cmp r3, #0 8004512: d124 bne.n 800455e { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004514: 4b71 ldr r3, [pc, #452] @ (80046dc ) 8004516: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800451a: 0c1b lsrs r3, r3, #16 800451c: f003 0303 and.w r3, r3, #3 8004520: 3301 adds r3, #1 8004522: 005b lsls r3, r3, #1 8004524: 61fb str r3, [r7, #28] plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); 8004526: 4b6d ldr r3, [pc, #436] @ (80046dc ) 8004528: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800452c: 0e1b lsrs r3, r3, #24 800452e: f003 030f and.w r3, r3, #15 8004532: 61bb str r3, [r7, #24] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq, 8004534: 687b ldr r3, [r7, #4] 8004536: 685a ldr r2, [r3, #4] 8004538: 687b ldr r3, [r7, #4] 800453a: 689b ldr r3, [r3, #8] 800453c: 019b lsls r3, r3, #6 800453e: 431a orrs r2, r3 8004540: 69fb ldr r3, [r7, #28] 8004542: 085b lsrs r3, r3, #1 8004544: 3b01 subs r3, #1 8004546: 041b lsls r3, r3, #16 8004548: 431a orrs r2, r3 800454a: 69bb ldr r3, [r7, #24] 800454c: 061b lsls r3, r3, #24 800454e: 431a orrs r2, r3 8004550: 687b ldr r3, [r7, #4] 8004552: 695b ldr r3, [r3, #20] 8004554: 071b lsls r3, r3, #28 8004556: 4961 ldr r1, [pc, #388] @ (80046dc ) 8004558: 4313 orrs r3, r2 800455a: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SR); } /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800455e: 687b ldr r3, [r7, #4] 8004560: 681b ldr r3, [r3, #0] 8004562: f003 0304 and.w r3, r3, #4 8004566: 2b00 cmp r3, #0 8004568: d004 beq.n 8004574 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 800456a: 687b ldr r3, [r7, #4] 800456c: 6b1b ldr r3, [r3, #48] @ 0x30 800456e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8004572: d00a beq.n 800458a ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8004574: 687b ldr r3, [r7, #4] 8004576: 681b ldr r3, [r3, #0] 8004578: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 800457c: 2b00 cmp r3, #0 800457e: d035 beq.n 80045ec ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8004580: 687b ldr r3, [r7, #4] 8004582: 6b5b ldr r3, [r3, #52] @ 0x34 8004584: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004588: d130 bne.n 80045ec assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 800458a: 4b54 ldr r3, [pc, #336] @ (80046dc ) 800458c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004590: 0c1b lsrs r3, r3, #16 8004592: f003 0303 and.w r3, r3, #3 8004596: 3301 adds r3, #1 8004598: 005b lsls r3, r3, #1 800459a: 61fb str r3, [r7, #28] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 800459c: 4b4f ldr r3, [pc, #316] @ (80046dc ) 800459e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80045a2: 0f1b lsrs r3, r3, #28 80045a4: f003 0307 and.w r3, r3, #7 80045a8: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, 80045aa: 687b ldr r3, [r7, #4] 80045ac: 685a ldr r2, [r3, #4] 80045ae: 687b ldr r3, [r7, #4] 80045b0: 689b ldr r3, [r3, #8] 80045b2: 019b lsls r3, r3, #6 80045b4: 431a orrs r2, r3 80045b6: 69fb ldr r3, [r7, #28] 80045b8: 085b lsrs r3, r3, #1 80045ba: 3b01 subs r3, #1 80045bc: 041b lsls r3, r3, #16 80045be: 431a orrs r2, r3 80045c0: 687b ldr r3, [r7, #4] 80045c2: 691b ldr r3, [r3, #16] 80045c4: 061b lsls r3, r3, #24 80045c6: 431a orrs r2, r3 80045c8: 697b ldr r3, [r7, #20] 80045ca: 071b lsls r3, r3, #28 80045cc: 4943 ldr r1, [pc, #268] @ (80046dc ) 80045ce: 4313 orrs r3, r2 80045d0: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 80045d4: 4b41 ldr r3, [pc, #260] @ (80046dc ) 80045d6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80045da: f023 021f bic.w r2, r3, #31 80045de: 687b ldr r3, [r7, #4] 80045e0: 6a9b ldr r3, [r3, #40] @ 0x28 80045e2: 3b01 subs r3, #1 80045e4: 493d ldr r1, [pc, #244] @ (80046dc ) 80045e6: 4313 orrs r3, r2 80045e8: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 80045ec: 687b ldr r3, [r7, #4] 80045ee: 681b ldr r3, [r3, #0] 80045f0: f403 6380 and.w r3, r3, #1024 @ 0x400 80045f4: 2b00 cmp r3, #0 80045f6: d029 beq.n 800464c && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 80045f8: 687b ldr r3, [r7, #4] 80045fa: 6d1b ldr r3, [r3, #80] @ 0x50 80045fc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004600: d124 bne.n 800464c { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004602: 4b36 ldr r3, [pc, #216] @ (80046dc ) 8004604: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004608: 0c1b lsrs r3, r3, #16 800460a: f003 0303 and.w r3, r3, #3 800460e: 3301 adds r3, #1 8004610: 005b lsls r3, r3, #1 8004612: 61bb str r3, [r7, #24] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004614: 4b31 ldr r3, [pc, #196] @ (80046dc ) 8004616: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800461a: 0f1b lsrs r3, r3, #28 800461c: f003 0307 and.w r3, r3, #7 8004620: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 8004622: 687b ldr r3, [r7, #4] 8004624: 685a ldr r2, [r3, #4] 8004626: 687b ldr r3, [r7, #4] 8004628: 689b ldr r3, [r3, #8] 800462a: 019b lsls r3, r3, #6 800462c: 431a orrs r2, r3 800462e: 687b ldr r3, [r7, #4] 8004630: 68db ldr r3, [r3, #12] 8004632: 085b lsrs r3, r3, #1 8004634: 3b01 subs r3, #1 8004636: 041b lsls r3, r3, #16 8004638: 431a orrs r2, r3 800463a: 69bb ldr r3, [r7, #24] 800463c: 061b lsls r3, r3, #24 800463e: 431a orrs r2, r3 8004640: 697b ldr r3, [r7, #20] 8004642: 071b lsls r3, r3, #28 8004644: 4925 ldr r1, [pc, #148] @ (80046dc ) 8004646: 4313 orrs r3, r2 8004648: f8c1 3084 str.w r3, [r1, #132] @ 0x84 plli2sq, plli2sr); } /*----------------- In Case of PLLI2S is just selected -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 800464c: 687b ldr r3, [r7, #4] 800464e: 681b ldr r3, [r3, #0] 8004650: f403 6300 and.w r3, r3, #2048 @ 0x800 8004654: 2b00 cmp r3, #0 8004656: d016 beq.n 8004686 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 8004658: 687b ldr r3, [r7, #4] 800465a: 685a ldr r2, [r3, #4] 800465c: 687b ldr r3, [r7, #4] 800465e: 689b ldr r3, [r3, #8] 8004660: 019b lsls r3, r3, #6 8004662: 431a orrs r2, r3 8004664: 687b ldr r3, [r7, #4] 8004666: 68db ldr r3, [r3, #12] 8004668: 085b lsrs r3, r3, #1 800466a: 3b01 subs r3, #1 800466c: 041b lsls r3, r3, #16 800466e: 431a orrs r2, r3 8004670: 687b ldr r3, [r7, #4] 8004672: 691b ldr r3, [r3, #16] 8004674: 061b lsls r3, r3, #24 8004676: 431a orrs r2, r3 8004678: 687b ldr r3, [r7, #4] 800467a: 695b ldr r3, [r3, #20] 800467c: 071b lsls r3, r3, #28 800467e: 4917 ldr r1, [pc, #92] @ (80046dc ) 8004680: 4313 orrs r3, r2 8004682: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 8004686: 4b16 ldr r3, [pc, #88] @ (80046e0 ) 8004688: 2201 movs r2, #1 800468a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800468c: f7fd f99c bl 80019c8 8004690: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004692: e008 b.n 80046a6 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004694: f7fd f998 bl 80019c8 8004698: 4602 mov r2, r0 800469a: 6a7b ldr r3, [r7, #36] @ 0x24 800469c: 1ad3 subs r3, r2, r3 800469e: 2b02 cmp r3, #2 80046a0: d901 bls.n 80046a6 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 80046a2: 2303 movs r3, #3 80046a4: e09f b.n 80047e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80046a6: 4b0d ldr r3, [pc, #52] @ (80046dc ) 80046a8: 681b ldr r3, [r3, #0] 80046aa: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80046ae: 2b00 cmp r3, #0 80046b0: d0f0 beq.n 8004694 } /*--------------------------------------------------------------------------*/ /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ if (pllsaiused == 1U) 80046b2: 6abb ldr r3, [r7, #40] @ 0x28 80046b4: 2b01 cmp r3, #1 80046b6: f040 8095 bne.w 80047e4 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 80046ba: 4b0a ldr r3, [pc, #40] @ (80046e4 ) 80046bc: 2200 movs r2, #0 80046be: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80046c0: f7fd f982 bl 80019c8 80046c4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is disabled */ while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 80046c6: e00f b.n 80046e8 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 80046c8: f7fd f97e bl 80019c8 80046cc: 4602 mov r2, r0 80046ce: 6a7b ldr r3, [r7, #36] @ 0x24 80046d0: 1ad3 subs r3, r2, r3 80046d2: 2b02 cmp r3, #2 80046d4: d908 bls.n 80046e8 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 80046d6: 2303 movs r3, #3 80046d8: e085 b.n 80047e6 80046da: bf00 nop 80046dc: 40023800 .word 0x40023800 80046e0: 42470068 .word 0x42470068 80046e4: 42470070 .word 0x42470070 while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 80046e8: 4b41 ldr r3, [pc, #260] @ (80047f0 ) 80046ea: 681b ldr r3, [r3, #0] 80046ec: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80046f0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80046f4: d0e8 beq.n 80046c8 /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 80046f6: 687b ldr r3, [r7, #4] 80046f8: 681b ldr r3, [r3, #0] 80046fa: f003 0304 and.w r3, r3, #4 80046fe: 2b00 cmp r3, #0 8004700: d003 beq.n 800470a && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8004702: 687b ldr r3, [r7, #4] 8004704: 6b1b ldr r3, [r3, #48] @ 0x30 8004706: 2b00 cmp r3, #0 8004708: d009 beq.n 800471e ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 800470a: 687b ldr r3, [r7, #4] 800470c: 681b ldr r3, [r3, #0] 800470e: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8004712: 2b00 cmp r3, #0 8004714: d02b beq.n 800476e ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8004716: 687b ldr r3, [r7, #4] 8004718: 6b5b ldr r3, [r3, #52] @ 0x34 800471a: 2b00 cmp r3, #0 800471c: d127 bne.n 800476e assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); 800471e: 4b34 ldr r3, [pc, #208] @ (80047f0 ) 8004720: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004724: 0c1b lsrs r3, r3, #16 8004726: f003 0303 and.w r3, r3, #3 800472a: 3301 adds r3, #1 800472c: 005b lsls r3, r3, #1 800472e: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, 8004730: 687b ldr r3, [r7, #4] 8004732: 699a ldr r2, [r3, #24] 8004734: 687b ldr r3, [r7, #4] 8004736: 69db ldr r3, [r3, #28] 8004738: 019b lsls r3, r3, #6 800473a: 431a orrs r2, r3 800473c: 693b ldr r3, [r7, #16] 800473e: 085b lsrs r3, r3, #1 8004740: 3b01 subs r3, #1 8004742: 041b lsls r3, r3, #16 8004744: 431a orrs r2, r3 8004746: 687b ldr r3, [r7, #4] 8004748: 6a5b ldr r3, [r3, #36] @ 0x24 800474a: 061b lsls r3, r3, #24 800474c: 4928 ldr r1, [pc, #160] @ (80047f0 ) 800474e: 4313 orrs r3, r2 8004750: f8c1 3088 str.w r3, [r1, #136] @ 0x88 PeriphClkInit->PLLSAI.PLLSAIQ, 0U); /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 8004754: 4b26 ldr r3, [pc, #152] @ (80047f0 ) 8004756: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800475a: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 800475e: 687b ldr r3, [r7, #4] 8004760: 6adb ldr r3, [r3, #44] @ 0x2c 8004762: 3b01 subs r3, #1 8004764: 021b lsls r3, r3, #8 8004766: 4922 ldr r1, [pc, #136] @ (80047f0 ) 8004768: 4313 orrs r3, r2 800476a: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ /* In Case of PLLI2S is selected as source clock for CLK48 */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 800476e: 687b ldr r3, [r7, #4] 8004770: 681b ldr r3, [r3, #0] 8004772: f403 7380 and.w r3, r3, #256 @ 0x100 8004776: 2b00 cmp r3, #0 8004778: d01d beq.n 80047b6 && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) 800477a: 687b ldr r3, [r7, #4] 800477c: 6d5b ldr r3, [r3, #84] @ 0x54 800477e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8004782: d118 bne.n 80047b6 { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 8004784: 4b1a ldr r3, [pc, #104] @ (80047f0 ) 8004786: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800478a: 0e1b lsrs r3, r3, #24 800478c: f003 030f and.w r3, r3, #15 8004790: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, 8004792: 687b ldr r3, [r7, #4] 8004794: 699a ldr r2, [r3, #24] 8004796: 687b ldr r3, [r7, #4] 8004798: 69db ldr r3, [r3, #28] 800479a: 019b lsls r3, r3, #6 800479c: 431a orrs r2, r3 800479e: 687b ldr r3, [r7, #4] 80047a0: 6a1b ldr r3, [r3, #32] 80047a2: 085b lsrs r3, r3, #1 80047a4: 3b01 subs r3, #1 80047a6: 041b lsls r3, r3, #16 80047a8: 431a orrs r2, r3 80047aa: 68fb ldr r3, [r7, #12] 80047ac: 061b lsls r3, r3, #24 80047ae: 4910 ldr r1, [pc, #64] @ (80047f0 ) 80047b0: 4313 orrs r3, r2 80047b2: f8c1 3088 str.w r3, [r1, #136] @ 0x88 pllsaiq, 0U); } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 80047b6: 4b0f ldr r3, [pc, #60] @ (80047f4 ) 80047b8: 2201 movs r2, #1 80047ba: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80047bc: f7fd f904 bl 80019c8 80047c0: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is ready */ while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 80047c2: e008 b.n 80047d6 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 80047c4: f7fd f900 bl 80019c8 80047c8: 4602 mov r2, r0 80047ca: 6a7b ldr r3, [r7, #36] @ 0x24 80047cc: 1ad3 subs r3, r2, r3 80047ce: 2b02 cmp r3, #2 80047d0: d901 bls.n 80047d6 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 80047d2: 2303 movs r3, #3 80047d4: e007 b.n 80047e6 while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 80047d6: 4b06 ldr r3, [pc, #24] @ (80047f0 ) 80047d8: 681b ldr r3, [r3, #0] 80047da: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80047de: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80047e2: d1ef bne.n 80047c4 } } } return HAL_OK; 80047e4: 2300 movs r3, #0 } 80047e6: 4618 mov r0, r3 80047e8: 3730 adds r7, #48 @ 0x30 80047ea: 46bd mov sp, r7 80047ec: bd80 pop {r7, pc} 80047ee: bf00 nop 80047f0: 40023800 .word 0x40023800 80047f4: 42470070 .word 0x42470070 080047f8 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80047f8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 80047fc: b0ae sub sp, #184 @ 0xb8 80047fe: af00 add r7, sp, #0 uint32_t pllm = 0U; 8004800: 2300 movs r3, #0 8004802: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t pllvco = 0U; 8004806: 2300 movs r3, #0 8004808: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t pllp = 0U; 800480c: 2300 movs r3, #0 800480e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 uint32_t pllr = 0U; 8004812: 2300 movs r3, #0 8004814: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t sysclockfreq = 0U; 8004818: 2300 movs r3, #0 800481a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800481e: 4bcb ldr r3, [pc, #812] @ (8004b4c ) 8004820: 689b ldr r3, [r3, #8] 8004822: f003 030c and.w r3, r3, #12 8004826: 2b0c cmp r3, #12 8004828: f200 8206 bhi.w 8004c38 800482c: a201 add r2, pc, #4 @ (adr r2, 8004834 ) 800482e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004832: bf00 nop 8004834: 08004869 .word 0x08004869 8004838: 08004c39 .word 0x08004c39 800483c: 08004c39 .word 0x08004c39 8004840: 08004c39 .word 0x08004c39 8004844: 08004871 .word 0x08004871 8004848: 08004c39 .word 0x08004c39 800484c: 08004c39 .word 0x08004c39 8004850: 08004c39 .word 0x08004c39 8004854: 08004879 .word 0x08004879 8004858: 08004c39 .word 0x08004c39 800485c: 08004c39 .word 0x08004c39 8004860: 08004c39 .word 0x08004c39 8004864: 08004a69 .word 0x08004a69 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8004868: 4bb9 ldr r3, [pc, #740] @ (8004b50 ) 800486a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 800486e: e1e7 b.n 8004c40 } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 8004870: 4bb8 ldr r3, [pc, #736] @ (8004b54 ) 8004872: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004876: e1e3 b.n 8004c40 } case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004878: 4bb4 ldr r3, [pc, #720] @ (8004b4c ) 800487a: 685b ldr r3, [r3, #4] 800487c: f003 033f and.w r3, r3, #63 @ 0x3f 8004880: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004884: 4bb1 ldr r3, [pc, #708] @ (8004b4c ) 8004886: 685b ldr r3, [r3, #4] 8004888: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800488c: 2b00 cmp r3, #0 800488e: d071 beq.n 8004974 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004890: 4bae ldr r3, [pc, #696] @ (8004b4c ) 8004892: 685b ldr r3, [r3, #4] 8004894: 099b lsrs r3, r3, #6 8004896: 2200 movs r2, #0 8004898: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800489c: f8c7 209c str.w r2, [r7, #156] @ 0x9c 80048a0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 80048a4: f3c3 0308 ubfx r3, r3, #0, #9 80048a8: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80048ac: 2300 movs r3, #0 80048ae: f8c7 3094 str.w r3, [r7, #148] @ 0x94 80048b2: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 80048b6: 4622 mov r2, r4 80048b8: 462b mov r3, r5 80048ba: f04f 0000 mov.w r0, #0 80048be: f04f 0100 mov.w r1, #0 80048c2: 0159 lsls r1, r3, #5 80048c4: ea41 61d2 orr.w r1, r1, r2, lsr #27 80048c8: 0150 lsls r0, r2, #5 80048ca: 4602 mov r2, r0 80048cc: 460b mov r3, r1 80048ce: 4621 mov r1, r4 80048d0: 1a51 subs r1, r2, r1 80048d2: 6439 str r1, [r7, #64] @ 0x40 80048d4: 4629 mov r1, r5 80048d6: eb63 0301 sbc.w r3, r3, r1 80048da: 647b str r3, [r7, #68] @ 0x44 80048dc: f04f 0200 mov.w r2, #0 80048e0: f04f 0300 mov.w r3, #0 80048e4: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40 80048e8: 4649 mov r1, r9 80048ea: 018b lsls r3, r1, #6 80048ec: 4641 mov r1, r8 80048ee: ea43 6391 orr.w r3, r3, r1, lsr #26 80048f2: 4641 mov r1, r8 80048f4: 018a lsls r2, r1, #6 80048f6: 4641 mov r1, r8 80048f8: 1a51 subs r1, r2, r1 80048fa: 63b9 str r1, [r7, #56] @ 0x38 80048fc: 4649 mov r1, r9 80048fe: eb63 0301 sbc.w r3, r3, r1 8004902: 63fb str r3, [r7, #60] @ 0x3c 8004904: f04f 0200 mov.w r2, #0 8004908: f04f 0300 mov.w r3, #0 800490c: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38 8004910: 4649 mov r1, r9 8004912: 00cb lsls r3, r1, #3 8004914: 4641 mov r1, r8 8004916: ea43 7351 orr.w r3, r3, r1, lsr #29 800491a: 4641 mov r1, r8 800491c: 00ca lsls r2, r1, #3 800491e: 4610 mov r0, r2 8004920: 4619 mov r1, r3 8004922: 4603 mov r3, r0 8004924: 4622 mov r2, r4 8004926: 189b adds r3, r3, r2 8004928: 633b str r3, [r7, #48] @ 0x30 800492a: 462b mov r3, r5 800492c: 460a mov r2, r1 800492e: eb42 0303 adc.w r3, r2, r3 8004932: 637b str r3, [r7, #52] @ 0x34 8004934: f04f 0200 mov.w r2, #0 8004938: f04f 0300 mov.w r3, #0 800493c: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 8004940: 4629 mov r1, r5 8004942: 024b lsls r3, r1, #9 8004944: 4621 mov r1, r4 8004946: ea43 53d1 orr.w r3, r3, r1, lsr #23 800494a: 4621 mov r1, r4 800494c: 024a lsls r2, r1, #9 800494e: 4610 mov r0, r2 8004950: 4619 mov r1, r3 8004952: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004956: 2200 movs r2, #0 8004958: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800495c: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8004960: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88 8004964: f7fb fc4e bl 8000204 <__aeabi_uldivmod> 8004968: 4602 mov r2, r0 800496a: 460b mov r3, r1 800496c: 4613 mov r3, r2 800496e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8004972: e067 b.n 8004a44 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004974: 4b75 ldr r3, [pc, #468] @ (8004b4c ) 8004976: 685b ldr r3, [r3, #4] 8004978: 099b lsrs r3, r3, #6 800497a: 2200 movs r2, #0 800497c: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8004980: f8c7 2084 str.w r2, [r7, #132] @ 0x84 8004984: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8004988: f3c3 0308 ubfx r3, r3, #0, #9 800498c: 67bb str r3, [r7, #120] @ 0x78 800498e: 2300 movs r3, #0 8004990: 67fb str r3, [r7, #124] @ 0x7c 8004992: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78 8004996: 4622 mov r2, r4 8004998: 462b mov r3, r5 800499a: f04f 0000 mov.w r0, #0 800499e: f04f 0100 mov.w r1, #0 80049a2: 0159 lsls r1, r3, #5 80049a4: ea41 61d2 orr.w r1, r1, r2, lsr #27 80049a8: 0150 lsls r0, r2, #5 80049aa: 4602 mov r2, r0 80049ac: 460b mov r3, r1 80049ae: 4621 mov r1, r4 80049b0: 1a51 subs r1, r2, r1 80049b2: 62b9 str r1, [r7, #40] @ 0x28 80049b4: 4629 mov r1, r5 80049b6: eb63 0301 sbc.w r3, r3, r1 80049ba: 62fb str r3, [r7, #44] @ 0x2c 80049bc: f04f 0200 mov.w r2, #0 80049c0: f04f 0300 mov.w r3, #0 80049c4: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28 80049c8: 4649 mov r1, r9 80049ca: 018b lsls r3, r1, #6 80049cc: 4641 mov r1, r8 80049ce: ea43 6391 orr.w r3, r3, r1, lsr #26 80049d2: 4641 mov r1, r8 80049d4: 018a lsls r2, r1, #6 80049d6: 4641 mov r1, r8 80049d8: ebb2 0a01 subs.w sl, r2, r1 80049dc: 4649 mov r1, r9 80049de: eb63 0b01 sbc.w fp, r3, r1 80049e2: f04f 0200 mov.w r2, #0 80049e6: f04f 0300 mov.w r3, #0 80049ea: ea4f 03cb mov.w r3, fp, lsl #3 80049ee: ea43 735a orr.w r3, r3, sl, lsr #29 80049f2: ea4f 02ca mov.w r2, sl, lsl #3 80049f6: 4692 mov sl, r2 80049f8: 469b mov fp, r3 80049fa: 4623 mov r3, r4 80049fc: eb1a 0303 adds.w r3, sl, r3 8004a00: 623b str r3, [r7, #32] 8004a02: 462b mov r3, r5 8004a04: eb4b 0303 adc.w r3, fp, r3 8004a08: 627b str r3, [r7, #36] @ 0x24 8004a0a: f04f 0200 mov.w r2, #0 8004a0e: f04f 0300 mov.w r3, #0 8004a12: e9d7 4508 ldrd r4, r5, [r7, #32] 8004a16: 4629 mov r1, r5 8004a18: 028b lsls r3, r1, #10 8004a1a: 4621 mov r1, r4 8004a1c: ea43 5391 orr.w r3, r3, r1, lsr #22 8004a20: 4621 mov r1, r4 8004a22: 028a lsls r2, r1, #10 8004a24: 4610 mov r0, r2 8004a26: 4619 mov r1, r3 8004a28: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004a2c: 2200 movs r2, #0 8004a2e: 673b str r3, [r7, #112] @ 0x70 8004a30: 677a str r2, [r7, #116] @ 0x74 8004a32: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70 8004a36: f7fb fbe5 bl 8000204 <__aeabi_uldivmod> 8004a3a: 4602 mov r2, r0 8004a3c: 460b mov r3, r1 8004a3e: 4613 mov r3, r2 8004a40: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); 8004a44: 4b41 ldr r3, [pc, #260] @ (8004b4c ) 8004a46: 685b ldr r3, [r3, #4] 8004a48: 0c1b lsrs r3, r3, #16 8004a4a: f003 0303 and.w r3, r3, #3 8004a4e: 3301 adds r3, #1 8004a50: 005b lsls r3, r3, #1 8004a52: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 sysclockfreq = pllvco / pllp; 8004a56: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004a5a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8004a5e: fbb2 f3f3 udiv r3, r2, r3 8004a62: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004a66: e0eb b.n 8004c40 } case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004a68: 4b38 ldr r3, [pc, #224] @ (8004b4c ) 8004a6a: 685b ldr r3, [r3, #4] 8004a6c: f003 033f and.w r3, r3, #63 @ 0x3f 8004a70: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004a74: 4b35 ldr r3, [pc, #212] @ (8004b4c ) 8004a76: 685b ldr r3, [r3, #4] 8004a78: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004a7c: 2b00 cmp r3, #0 8004a7e: d06b beq.n 8004b58 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004a80: 4b32 ldr r3, [pc, #200] @ (8004b4c ) 8004a82: 685b ldr r3, [r3, #4] 8004a84: 099b lsrs r3, r3, #6 8004a86: 2200 movs r2, #0 8004a88: 66bb str r3, [r7, #104] @ 0x68 8004a8a: 66fa str r2, [r7, #108] @ 0x6c 8004a8c: 6ebb ldr r3, [r7, #104] @ 0x68 8004a8e: f3c3 0308 ubfx r3, r3, #0, #9 8004a92: 663b str r3, [r7, #96] @ 0x60 8004a94: 2300 movs r3, #0 8004a96: 667b str r3, [r7, #100] @ 0x64 8004a98: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60 8004a9c: 4622 mov r2, r4 8004a9e: 462b mov r3, r5 8004aa0: f04f 0000 mov.w r0, #0 8004aa4: f04f 0100 mov.w r1, #0 8004aa8: 0159 lsls r1, r3, #5 8004aaa: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004aae: 0150 lsls r0, r2, #5 8004ab0: 4602 mov r2, r0 8004ab2: 460b mov r3, r1 8004ab4: 4621 mov r1, r4 8004ab6: 1a51 subs r1, r2, r1 8004ab8: 61b9 str r1, [r7, #24] 8004aba: 4629 mov r1, r5 8004abc: eb63 0301 sbc.w r3, r3, r1 8004ac0: 61fb str r3, [r7, #28] 8004ac2: f04f 0200 mov.w r2, #0 8004ac6: f04f 0300 mov.w r3, #0 8004aca: e9d7 ab06 ldrd sl, fp, [r7, #24] 8004ace: 4659 mov r1, fp 8004ad0: 018b lsls r3, r1, #6 8004ad2: 4651 mov r1, sl 8004ad4: ea43 6391 orr.w r3, r3, r1, lsr #26 8004ad8: 4651 mov r1, sl 8004ada: 018a lsls r2, r1, #6 8004adc: 4651 mov r1, sl 8004ade: ebb2 0801 subs.w r8, r2, r1 8004ae2: 4659 mov r1, fp 8004ae4: eb63 0901 sbc.w r9, r3, r1 8004ae8: f04f 0200 mov.w r2, #0 8004aec: f04f 0300 mov.w r3, #0 8004af0: ea4f 03c9 mov.w r3, r9, lsl #3 8004af4: ea43 7358 orr.w r3, r3, r8, lsr #29 8004af8: ea4f 02c8 mov.w r2, r8, lsl #3 8004afc: 4690 mov r8, r2 8004afe: 4699 mov r9, r3 8004b00: 4623 mov r3, r4 8004b02: eb18 0303 adds.w r3, r8, r3 8004b06: 613b str r3, [r7, #16] 8004b08: 462b mov r3, r5 8004b0a: eb49 0303 adc.w r3, r9, r3 8004b0e: 617b str r3, [r7, #20] 8004b10: f04f 0200 mov.w r2, #0 8004b14: f04f 0300 mov.w r3, #0 8004b18: e9d7 4504 ldrd r4, r5, [r7, #16] 8004b1c: 4629 mov r1, r5 8004b1e: 024b lsls r3, r1, #9 8004b20: 4621 mov r1, r4 8004b22: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004b26: 4621 mov r1, r4 8004b28: 024a lsls r2, r1, #9 8004b2a: 4610 mov r0, r2 8004b2c: 4619 mov r1, r3 8004b2e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004b32: 2200 movs r2, #0 8004b34: 65bb str r3, [r7, #88] @ 0x58 8004b36: 65fa str r2, [r7, #92] @ 0x5c 8004b38: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8004b3c: f7fb fb62 bl 8000204 <__aeabi_uldivmod> 8004b40: 4602 mov r2, r0 8004b42: 460b mov r3, r1 8004b44: 4613 mov r3, r2 8004b46: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8004b4a: e065 b.n 8004c18 8004b4c: 40023800 .word 0x40023800 8004b50: 00f42400 .word 0x00f42400 8004b54: 007a1200 .word 0x007a1200 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004b58: 4b3d ldr r3, [pc, #244] @ (8004c50 ) 8004b5a: 685b ldr r3, [r3, #4] 8004b5c: 099b lsrs r3, r3, #6 8004b5e: 2200 movs r2, #0 8004b60: 4618 mov r0, r3 8004b62: 4611 mov r1, r2 8004b64: f3c0 0308 ubfx r3, r0, #0, #9 8004b68: 653b str r3, [r7, #80] @ 0x50 8004b6a: 2300 movs r3, #0 8004b6c: 657b str r3, [r7, #84] @ 0x54 8004b6e: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50 8004b72: 4642 mov r2, r8 8004b74: 464b mov r3, r9 8004b76: f04f 0000 mov.w r0, #0 8004b7a: f04f 0100 mov.w r1, #0 8004b7e: 0159 lsls r1, r3, #5 8004b80: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004b84: 0150 lsls r0, r2, #5 8004b86: 4602 mov r2, r0 8004b88: 460b mov r3, r1 8004b8a: 4641 mov r1, r8 8004b8c: 1a51 subs r1, r2, r1 8004b8e: 60b9 str r1, [r7, #8] 8004b90: 4649 mov r1, r9 8004b92: eb63 0301 sbc.w r3, r3, r1 8004b96: 60fb str r3, [r7, #12] 8004b98: f04f 0200 mov.w r2, #0 8004b9c: f04f 0300 mov.w r3, #0 8004ba0: e9d7 ab02 ldrd sl, fp, [r7, #8] 8004ba4: 4659 mov r1, fp 8004ba6: 018b lsls r3, r1, #6 8004ba8: 4651 mov r1, sl 8004baa: ea43 6391 orr.w r3, r3, r1, lsr #26 8004bae: 4651 mov r1, sl 8004bb0: 018a lsls r2, r1, #6 8004bb2: 4651 mov r1, sl 8004bb4: 1a54 subs r4, r2, r1 8004bb6: 4659 mov r1, fp 8004bb8: eb63 0501 sbc.w r5, r3, r1 8004bbc: f04f 0200 mov.w r2, #0 8004bc0: f04f 0300 mov.w r3, #0 8004bc4: 00eb lsls r3, r5, #3 8004bc6: ea43 7354 orr.w r3, r3, r4, lsr #29 8004bca: 00e2 lsls r2, r4, #3 8004bcc: 4614 mov r4, r2 8004bce: 461d mov r5, r3 8004bd0: 4643 mov r3, r8 8004bd2: 18e3 adds r3, r4, r3 8004bd4: 603b str r3, [r7, #0] 8004bd6: 464b mov r3, r9 8004bd8: eb45 0303 adc.w r3, r5, r3 8004bdc: 607b str r3, [r7, #4] 8004bde: f04f 0200 mov.w r2, #0 8004be2: f04f 0300 mov.w r3, #0 8004be6: e9d7 4500 ldrd r4, r5, [r7] 8004bea: 4629 mov r1, r5 8004bec: 028b lsls r3, r1, #10 8004bee: 4621 mov r1, r4 8004bf0: ea43 5391 orr.w r3, r3, r1, lsr #22 8004bf4: 4621 mov r1, r4 8004bf6: 028a lsls r2, r1, #10 8004bf8: 4610 mov r0, r2 8004bfa: 4619 mov r1, r3 8004bfc: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004c00: 2200 movs r2, #0 8004c02: 64bb str r3, [r7, #72] @ 0x48 8004c04: 64fa str r2, [r7, #76] @ 0x4c 8004c06: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8004c0a: f7fb fafb bl 8000204 <__aeabi_uldivmod> 8004c0e: 4602 mov r2, r0 8004c10: 460b mov r3, r1 8004c12: 4613 mov r3, r2 8004c14: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); 8004c18: 4b0d ldr r3, [pc, #52] @ (8004c50 ) 8004c1a: 685b ldr r3, [r3, #4] 8004c1c: 0f1b lsrs r3, r3, #28 8004c1e: f003 0307 and.w r3, r3, #7 8004c22: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 sysclockfreq = pllvco / pllr; 8004c26: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004c2a: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8004c2e: fbb2 f3f3 udiv r3, r2, r3 8004c32: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004c36: e003 b.n 8004c40 } default: { sysclockfreq = HSI_VALUE; 8004c38: 4b06 ldr r3, [pc, #24] @ (8004c54 ) 8004c3a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004c3e: bf00 nop } } return sysclockfreq; 8004c40: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 } 8004c44: 4618 mov r0, r3 8004c46: 37b8 adds r7, #184 @ 0xb8 8004c48: 46bd mov sp, r7 8004c4a: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8004c4e: bf00 nop 8004c50: 40023800 .word 0x40023800 8004c54: 00f42400 .word 0x00f42400 08004c58 : * @note This function add the PLL/PLLR factor management during PLL configuration this feature * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 8004c58: b580 push {r7, lr} 8004c5a: b086 sub sp, #24 8004c5c: af00 add r7, sp, #0 8004c5e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8004c60: 687b ldr r3, [r7, #4] 8004c62: 2b00 cmp r3, #0 8004c64: d101 bne.n 8004c6a { return HAL_ERROR; 8004c66: 2301 movs r3, #1 8004c68: e28d b.n 8005186 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8004c6a: 687b ldr r3, [r7, #4] 8004c6c: 681b ldr r3, [r3, #0] 8004c6e: f003 0301 and.w r3, r3, #1 8004c72: 2b00 cmp r3, #0 8004c74: f000 8083 beq.w 8004d7e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 8004c78: 4b94 ldr r3, [pc, #592] @ (8004ecc ) 8004c7a: 689b ldr r3, [r3, #8] 8004c7c: f003 030c and.w r3, r3, #12 8004c80: 2b04 cmp r3, #4 8004c82: d019 beq.n 8004cb8 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004c84: 4b91 ldr r3, [pc, #580] @ (8004ecc ) 8004c86: 689b ldr r3, [r3, #8] 8004c88: f003 030c and.w r3, r3, #12 || \ 8004c8c: 2b08 cmp r3, #8 8004c8e: d106 bne.n 8004c9e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004c90: 4b8e ldr r3, [pc, #568] @ (8004ecc ) 8004c92: 685b ldr r3, [r3, #4] 8004c94: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004c98: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004c9c: d00c beq.n 8004cb8 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8004c9e: 4b8b ldr r3, [pc, #556] @ (8004ecc ) 8004ca0: 689b ldr r3, [r3, #8] 8004ca2: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004ca6: 2b0c cmp r3, #12 8004ca8: d112 bne.n 8004cd0 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8004caa: 4b88 ldr r3, [pc, #544] @ (8004ecc ) 8004cac: 685b ldr r3, [r3, #4] 8004cae: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004cb2: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004cb6: d10b bne.n 8004cd0 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) #endif /* STM32F446xx */ { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004cb8: 4b84 ldr r3, [pc, #528] @ (8004ecc ) 8004cba: 681b ldr r3, [r3, #0] 8004cbc: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004cc0: 2b00 cmp r3, #0 8004cc2: d05b beq.n 8004d7c 8004cc4: 687b ldr r3, [r7, #4] 8004cc6: 685b ldr r3, [r3, #4] 8004cc8: 2b00 cmp r3, #0 8004cca: d157 bne.n 8004d7c { return HAL_ERROR; 8004ccc: 2301 movs r3, #1 8004cce: e25a b.n 8005186 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8004cd0: 687b ldr r3, [r7, #4] 8004cd2: 685b ldr r3, [r3, #4] 8004cd4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004cd8: d106 bne.n 8004ce8 8004cda: 4b7c ldr r3, [pc, #496] @ (8004ecc ) 8004cdc: 681b ldr r3, [r3, #0] 8004cde: 4a7b ldr r2, [pc, #492] @ (8004ecc ) 8004ce0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004ce4: 6013 str r3, [r2, #0] 8004ce6: e01d b.n 8004d24 8004ce8: 687b ldr r3, [r7, #4] 8004cea: 685b ldr r3, [r3, #4] 8004cec: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8004cf0: d10c bne.n 8004d0c 8004cf2: 4b76 ldr r3, [pc, #472] @ (8004ecc ) 8004cf4: 681b ldr r3, [r3, #0] 8004cf6: 4a75 ldr r2, [pc, #468] @ (8004ecc ) 8004cf8: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8004cfc: 6013 str r3, [r2, #0] 8004cfe: 4b73 ldr r3, [pc, #460] @ (8004ecc ) 8004d00: 681b ldr r3, [r3, #0] 8004d02: 4a72 ldr r2, [pc, #456] @ (8004ecc ) 8004d04: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004d08: 6013 str r3, [r2, #0] 8004d0a: e00b b.n 8004d24 8004d0c: 4b6f ldr r3, [pc, #444] @ (8004ecc ) 8004d0e: 681b ldr r3, [r3, #0] 8004d10: 4a6e ldr r2, [pc, #440] @ (8004ecc ) 8004d12: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8004d16: 6013 str r3, [r2, #0] 8004d18: 4b6c ldr r3, [pc, #432] @ (8004ecc ) 8004d1a: 681b ldr r3, [r3, #0] 8004d1c: 4a6b ldr r2, [pc, #428] @ (8004ecc ) 8004d1e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8004d22: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 8004d24: 687b ldr r3, [r7, #4] 8004d26: 685b ldr r3, [r3, #4] 8004d28: 2b00 cmp r3, #0 8004d2a: d013 beq.n 8004d54 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004d2c: f7fc fe4c bl 80019c8 8004d30: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004d32: e008 b.n 8004d46 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004d34: f7fc fe48 bl 80019c8 8004d38: 4602 mov r2, r0 8004d3a: 693b ldr r3, [r7, #16] 8004d3c: 1ad3 subs r3, r2, r3 8004d3e: 2b64 cmp r3, #100 @ 0x64 8004d40: d901 bls.n 8004d46 { return HAL_TIMEOUT; 8004d42: 2303 movs r3, #3 8004d44: e21f b.n 8005186 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004d46: 4b61 ldr r3, [pc, #388] @ (8004ecc ) 8004d48: 681b ldr r3, [r3, #0] 8004d4a: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004d4e: 2b00 cmp r3, #0 8004d50: d0f0 beq.n 8004d34 8004d52: e014 b.n 8004d7e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004d54: f7fc fe38 bl 80019c8 8004d58: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004d5a: e008 b.n 8004d6e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004d5c: f7fc fe34 bl 80019c8 8004d60: 4602 mov r2, r0 8004d62: 693b ldr r3, [r7, #16] 8004d64: 1ad3 subs r3, r2, r3 8004d66: 2b64 cmp r3, #100 @ 0x64 8004d68: d901 bls.n 8004d6e { return HAL_TIMEOUT; 8004d6a: 2303 movs r3, #3 8004d6c: e20b b.n 8005186 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004d6e: 4b57 ldr r3, [pc, #348] @ (8004ecc ) 8004d70: 681b ldr r3, [r3, #0] 8004d72: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004d76: 2b00 cmp r3, #0 8004d78: d1f0 bne.n 8004d5c 8004d7a: e000 b.n 8004d7e if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004d7c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8004d7e: 687b ldr r3, [r7, #4] 8004d80: 681b ldr r3, [r3, #0] 8004d82: f003 0302 and.w r3, r3, #2 8004d86: 2b00 cmp r3, #0 8004d88: d06f beq.n 8004e6a assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 8004d8a: 4b50 ldr r3, [pc, #320] @ (8004ecc ) 8004d8c: 689b ldr r3, [r3, #8] 8004d8e: f003 030c and.w r3, r3, #12 8004d92: 2b00 cmp r3, #0 8004d94: d017 beq.n 8004dc6 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004d96: 4b4d ldr r3, [pc, #308] @ (8004ecc ) 8004d98: 689b ldr r3, [r3, #8] 8004d9a: f003 030c and.w r3, r3, #12 || \ 8004d9e: 2b08 cmp r3, #8 8004da0: d105 bne.n 8004dae ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004da2: 4b4a ldr r3, [pc, #296] @ (8004ecc ) 8004da4: 685b ldr r3, [r3, #4] 8004da6: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004daa: 2b00 cmp r3, #0 8004dac: d00b beq.n 8004dc6 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004dae: 4b47 ldr r3, [pc, #284] @ (8004ecc ) 8004db0: 689b ldr r3, [r3, #8] 8004db2: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004db6: 2b0c cmp r3, #12 8004db8: d11c bne.n 8004df4 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004dba: 4b44 ldr r3, [pc, #272] @ (8004ecc ) 8004dbc: 685b ldr r3, [r3, #4] 8004dbe: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004dc2: 2b00 cmp r3, #0 8004dc4: d116 bne.n 8004df4 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) #endif /* STM32F446xx */ { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004dc6: 4b41 ldr r3, [pc, #260] @ (8004ecc ) 8004dc8: 681b ldr r3, [r3, #0] 8004dca: f003 0302 and.w r3, r3, #2 8004dce: 2b00 cmp r3, #0 8004dd0: d005 beq.n 8004dde 8004dd2: 687b ldr r3, [r7, #4] 8004dd4: 68db ldr r3, [r3, #12] 8004dd6: 2b01 cmp r3, #1 8004dd8: d001 beq.n 8004dde { return HAL_ERROR; 8004dda: 2301 movs r3, #1 8004ddc: e1d3 b.n 8005186 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004dde: 4b3b ldr r3, [pc, #236] @ (8004ecc ) 8004de0: 681b ldr r3, [r3, #0] 8004de2: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004de6: 687b ldr r3, [r7, #4] 8004de8: 691b ldr r3, [r3, #16] 8004dea: 00db lsls r3, r3, #3 8004dec: 4937 ldr r1, [pc, #220] @ (8004ecc ) 8004dee: 4313 orrs r3, r2 8004df0: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004df2: e03a b.n 8004e6a } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8004df4: 687b ldr r3, [r7, #4] 8004df6: 68db ldr r3, [r3, #12] 8004df8: 2b00 cmp r3, #0 8004dfa: d020 beq.n 8004e3e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8004dfc: 4b34 ldr r3, [pc, #208] @ (8004ed0 ) 8004dfe: 2201 movs r2, #1 8004e00: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004e02: f7fc fde1 bl 80019c8 8004e06: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004e08: e008 b.n 8004e1c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004e0a: f7fc fddd bl 80019c8 8004e0e: 4602 mov r2, r0 8004e10: 693b ldr r3, [r7, #16] 8004e12: 1ad3 subs r3, r2, r3 8004e14: 2b02 cmp r3, #2 8004e16: d901 bls.n 8004e1c { return HAL_TIMEOUT; 8004e18: 2303 movs r3, #3 8004e1a: e1b4 b.n 8005186 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004e1c: 4b2b ldr r3, [pc, #172] @ (8004ecc ) 8004e1e: 681b ldr r3, [r3, #0] 8004e20: f003 0302 and.w r3, r3, #2 8004e24: 2b00 cmp r3, #0 8004e26: d0f0 beq.n 8004e0a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004e28: 4b28 ldr r3, [pc, #160] @ (8004ecc ) 8004e2a: 681b ldr r3, [r3, #0] 8004e2c: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004e30: 687b ldr r3, [r7, #4] 8004e32: 691b ldr r3, [r3, #16] 8004e34: 00db lsls r3, r3, #3 8004e36: 4925 ldr r1, [pc, #148] @ (8004ecc ) 8004e38: 4313 orrs r3, r2 8004e3a: 600b str r3, [r1, #0] 8004e3c: e015 b.n 8004e6a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8004e3e: 4b24 ldr r3, [pc, #144] @ (8004ed0 ) 8004e40: 2200 movs r2, #0 8004e42: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004e44: f7fc fdc0 bl 80019c8 8004e48: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004e4a: e008 b.n 8004e5e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004e4c: f7fc fdbc bl 80019c8 8004e50: 4602 mov r2, r0 8004e52: 693b ldr r3, [r7, #16] 8004e54: 1ad3 subs r3, r2, r3 8004e56: 2b02 cmp r3, #2 8004e58: d901 bls.n 8004e5e { return HAL_TIMEOUT; 8004e5a: 2303 movs r3, #3 8004e5c: e193 b.n 8005186 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004e5e: 4b1b ldr r3, [pc, #108] @ (8004ecc ) 8004e60: 681b ldr r3, [r3, #0] 8004e62: f003 0302 and.w r3, r3, #2 8004e66: 2b00 cmp r3, #0 8004e68: d1f0 bne.n 8004e4c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8004e6a: 687b ldr r3, [r7, #4] 8004e6c: 681b ldr r3, [r3, #0] 8004e6e: f003 0308 and.w r3, r3, #8 8004e72: 2b00 cmp r3, #0 8004e74: d036 beq.n 8004ee4 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 8004e76: 687b ldr r3, [r7, #4] 8004e78: 695b ldr r3, [r3, #20] 8004e7a: 2b00 cmp r3, #0 8004e7c: d016 beq.n 8004eac { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8004e7e: 4b15 ldr r3, [pc, #84] @ (8004ed4 ) 8004e80: 2201 movs r2, #1 8004e82: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004e84: f7fc fda0 bl 80019c8 8004e88: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004e8a: e008 b.n 8004e9e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004e8c: f7fc fd9c bl 80019c8 8004e90: 4602 mov r2, r0 8004e92: 693b ldr r3, [r7, #16] 8004e94: 1ad3 subs r3, r2, r3 8004e96: 2b02 cmp r3, #2 8004e98: d901 bls.n 8004e9e { return HAL_TIMEOUT; 8004e9a: 2303 movs r3, #3 8004e9c: e173 b.n 8005186 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004e9e: 4b0b ldr r3, [pc, #44] @ (8004ecc ) 8004ea0: 6f5b ldr r3, [r3, #116] @ 0x74 8004ea2: f003 0302 and.w r3, r3, #2 8004ea6: 2b00 cmp r3, #0 8004ea8: d0f0 beq.n 8004e8c 8004eaa: e01b b.n 8004ee4 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8004eac: 4b09 ldr r3, [pc, #36] @ (8004ed4 ) 8004eae: 2200 movs r2, #0 8004eb0: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004eb2: f7fc fd89 bl 80019c8 8004eb6: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004eb8: e00e b.n 8004ed8 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004eba: f7fc fd85 bl 80019c8 8004ebe: 4602 mov r2, r0 8004ec0: 693b ldr r3, [r7, #16] 8004ec2: 1ad3 subs r3, r2, r3 8004ec4: 2b02 cmp r3, #2 8004ec6: d907 bls.n 8004ed8 { return HAL_TIMEOUT; 8004ec8: 2303 movs r3, #3 8004eca: e15c b.n 8005186 8004ecc: 40023800 .word 0x40023800 8004ed0: 42470000 .word 0x42470000 8004ed4: 42470e80 .word 0x42470e80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004ed8: 4b8a ldr r3, [pc, #552] @ (8005104 ) 8004eda: 6f5b ldr r3, [r3, #116] @ 0x74 8004edc: f003 0302 and.w r3, r3, #2 8004ee0: 2b00 cmp r3, #0 8004ee2: d1ea bne.n 8004eba } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8004ee4: 687b ldr r3, [r7, #4] 8004ee6: 681b ldr r3, [r3, #0] 8004ee8: f003 0304 and.w r3, r3, #4 8004eec: 2b00 cmp r3, #0 8004eee: f000 8097 beq.w 8005020 { FlagStatus pwrclkchanged = RESET; 8004ef2: 2300 movs r3, #0 8004ef4: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8004ef6: 4b83 ldr r3, [pc, #524] @ (8005104 ) 8004ef8: 6c1b ldr r3, [r3, #64] @ 0x40 8004efa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004efe: 2b00 cmp r3, #0 8004f00: d10f bne.n 8004f22 { __HAL_RCC_PWR_CLK_ENABLE(); 8004f02: 2300 movs r3, #0 8004f04: 60bb str r3, [r7, #8] 8004f06: 4b7f ldr r3, [pc, #508] @ (8005104 ) 8004f08: 6c1b ldr r3, [r3, #64] @ 0x40 8004f0a: 4a7e ldr r2, [pc, #504] @ (8005104 ) 8004f0c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004f10: 6413 str r3, [r2, #64] @ 0x40 8004f12: 4b7c ldr r3, [pc, #496] @ (8005104 ) 8004f14: 6c1b ldr r3, [r3, #64] @ 0x40 8004f16: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004f1a: 60bb str r3, [r7, #8] 8004f1c: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8004f1e: 2301 movs r3, #1 8004f20: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004f22: 4b79 ldr r3, [pc, #484] @ (8005108 ) 8004f24: 681b ldr r3, [r3, #0] 8004f26: f403 7380 and.w r3, r3, #256 @ 0x100 8004f2a: 2b00 cmp r3, #0 8004f2c: d118 bne.n 8004f60 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8004f2e: 4b76 ldr r3, [pc, #472] @ (8005108 ) 8004f30: 681b ldr r3, [r3, #0] 8004f32: 4a75 ldr r2, [pc, #468] @ (8005108 ) 8004f34: f443 7380 orr.w r3, r3, #256 @ 0x100 8004f38: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8004f3a: f7fc fd45 bl 80019c8 8004f3e: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004f40: e008 b.n 8004f54 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004f42: f7fc fd41 bl 80019c8 8004f46: 4602 mov r2, r0 8004f48: 693b ldr r3, [r7, #16] 8004f4a: 1ad3 subs r3, r2, r3 8004f4c: 2b02 cmp r3, #2 8004f4e: d901 bls.n 8004f54 { return HAL_TIMEOUT; 8004f50: 2303 movs r3, #3 8004f52: e118 b.n 8005186 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004f54: 4b6c ldr r3, [pc, #432] @ (8005108 ) 8004f56: 681b ldr r3, [r3, #0] 8004f58: f403 7380 and.w r3, r3, #256 @ 0x100 8004f5c: 2b00 cmp r3, #0 8004f5e: d0f0 beq.n 8004f42 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8004f60: 687b ldr r3, [r7, #4] 8004f62: 689b ldr r3, [r3, #8] 8004f64: 2b01 cmp r3, #1 8004f66: d106 bne.n 8004f76 8004f68: 4b66 ldr r3, [pc, #408] @ (8005104 ) 8004f6a: 6f1b ldr r3, [r3, #112] @ 0x70 8004f6c: 4a65 ldr r2, [pc, #404] @ (8005104 ) 8004f6e: f043 0301 orr.w r3, r3, #1 8004f72: 6713 str r3, [r2, #112] @ 0x70 8004f74: e01c b.n 8004fb0 8004f76: 687b ldr r3, [r7, #4] 8004f78: 689b ldr r3, [r3, #8] 8004f7a: 2b05 cmp r3, #5 8004f7c: d10c bne.n 8004f98 8004f7e: 4b61 ldr r3, [pc, #388] @ (8005104 ) 8004f80: 6f1b ldr r3, [r3, #112] @ 0x70 8004f82: 4a60 ldr r2, [pc, #384] @ (8005104 ) 8004f84: f043 0304 orr.w r3, r3, #4 8004f88: 6713 str r3, [r2, #112] @ 0x70 8004f8a: 4b5e ldr r3, [pc, #376] @ (8005104 ) 8004f8c: 6f1b ldr r3, [r3, #112] @ 0x70 8004f8e: 4a5d ldr r2, [pc, #372] @ (8005104 ) 8004f90: f043 0301 orr.w r3, r3, #1 8004f94: 6713 str r3, [r2, #112] @ 0x70 8004f96: e00b b.n 8004fb0 8004f98: 4b5a ldr r3, [pc, #360] @ (8005104 ) 8004f9a: 6f1b ldr r3, [r3, #112] @ 0x70 8004f9c: 4a59 ldr r2, [pc, #356] @ (8005104 ) 8004f9e: f023 0301 bic.w r3, r3, #1 8004fa2: 6713 str r3, [r2, #112] @ 0x70 8004fa4: 4b57 ldr r3, [pc, #348] @ (8005104 ) 8004fa6: 6f1b ldr r3, [r3, #112] @ 0x70 8004fa8: 4a56 ldr r2, [pc, #344] @ (8005104 ) 8004faa: f023 0304 bic.w r3, r3, #4 8004fae: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8004fb0: 687b ldr r3, [r7, #4] 8004fb2: 689b ldr r3, [r3, #8] 8004fb4: 2b00 cmp r3, #0 8004fb6: d015 beq.n 8004fe4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004fb8: f7fc fd06 bl 80019c8 8004fbc: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004fbe: e00a b.n 8004fd6 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004fc0: f7fc fd02 bl 80019c8 8004fc4: 4602 mov r2, r0 8004fc6: 693b ldr r3, [r7, #16] 8004fc8: 1ad3 subs r3, r2, r3 8004fca: f241 3288 movw r2, #5000 @ 0x1388 8004fce: 4293 cmp r3, r2 8004fd0: d901 bls.n 8004fd6 { return HAL_TIMEOUT; 8004fd2: 2303 movs r3, #3 8004fd4: e0d7 b.n 8005186 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004fd6: 4b4b ldr r3, [pc, #300] @ (8005104 ) 8004fd8: 6f1b ldr r3, [r3, #112] @ 0x70 8004fda: f003 0302 and.w r3, r3, #2 8004fde: 2b00 cmp r3, #0 8004fe0: d0ee beq.n 8004fc0 8004fe2: e014 b.n 800500e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004fe4: f7fc fcf0 bl 80019c8 8004fe8: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8004fea: e00a b.n 8005002 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004fec: f7fc fcec bl 80019c8 8004ff0: 4602 mov r2, r0 8004ff2: 693b ldr r3, [r7, #16] 8004ff4: 1ad3 subs r3, r2, r3 8004ff6: f241 3288 movw r2, #5000 @ 0x1388 8004ffa: 4293 cmp r3, r2 8004ffc: d901 bls.n 8005002 { return HAL_TIMEOUT; 8004ffe: 2303 movs r3, #3 8005000: e0c1 b.n 8005186 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8005002: 4b40 ldr r3, [pc, #256] @ (8005104 ) 8005004: 6f1b ldr r3, [r3, #112] @ 0x70 8005006: f003 0302 and.w r3, r3, #2 800500a: 2b00 cmp r3, #0 800500c: d1ee bne.n 8004fec } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 800500e: 7dfb ldrb r3, [r7, #23] 8005010: 2b01 cmp r3, #1 8005012: d105 bne.n 8005020 { __HAL_RCC_PWR_CLK_DISABLE(); 8005014: 4b3b ldr r3, [pc, #236] @ (8005104 ) 8005016: 6c1b ldr r3, [r3, #64] @ 0x40 8005018: 4a3a ldr r2, [pc, #232] @ (8005104 ) 800501a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800501e: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8005020: 687b ldr r3, [r7, #4] 8005022: 699b ldr r3, [r3, #24] 8005024: 2b00 cmp r3, #0 8005026: f000 80ad beq.w 8005184 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 800502a: 4b36 ldr r3, [pc, #216] @ (8005104 ) 800502c: 689b ldr r3, [r3, #8] 800502e: f003 030c and.w r3, r3, #12 8005032: 2b08 cmp r3, #8 8005034: d060 beq.n 80050f8 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8005036: 687b ldr r3, [r7, #4] 8005038: 699b ldr r3, [r3, #24] 800503a: 2b02 cmp r3, #2 800503c: d145 bne.n 80050ca assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800503e: 4b33 ldr r3, [pc, #204] @ (800510c ) 8005040: 2200 movs r2, #0 8005042: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005044: f7fc fcc0 bl 80019c8 8005048: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800504a: e008 b.n 800505e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800504c: f7fc fcbc bl 80019c8 8005050: 4602 mov r2, r0 8005052: 693b ldr r3, [r7, #16] 8005054: 1ad3 subs r3, r2, r3 8005056: 2b02 cmp r3, #2 8005058: d901 bls.n 800505e { return HAL_TIMEOUT; 800505a: 2303 movs r3, #3 800505c: e093 b.n 8005186 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800505e: 4b29 ldr r3, [pc, #164] @ (8005104 ) 8005060: 681b ldr r3, [r3, #0] 8005062: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005066: 2b00 cmp r3, #0 8005068: d1f0 bne.n 800504c } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 800506a: 687b ldr r3, [r7, #4] 800506c: 69da ldr r2, [r3, #28] 800506e: 687b ldr r3, [r7, #4] 8005070: 6a1b ldr r3, [r3, #32] 8005072: 431a orrs r2, r3 8005074: 687b ldr r3, [r7, #4] 8005076: 6a5b ldr r3, [r3, #36] @ 0x24 8005078: 019b lsls r3, r3, #6 800507a: 431a orrs r2, r3 800507c: 687b ldr r3, [r7, #4] 800507e: 6a9b ldr r3, [r3, #40] @ 0x28 8005080: 085b lsrs r3, r3, #1 8005082: 3b01 subs r3, #1 8005084: 041b lsls r3, r3, #16 8005086: 431a orrs r2, r3 8005088: 687b ldr r3, [r7, #4] 800508a: 6adb ldr r3, [r3, #44] @ 0x2c 800508c: 061b lsls r3, r3, #24 800508e: 431a orrs r2, r3 8005090: 687b ldr r3, [r7, #4] 8005092: 6b1b ldr r3, [r3, #48] @ 0x30 8005094: 071b lsls r3, r3, #28 8005096: 491b ldr r1, [pc, #108] @ (8005104 ) 8005098: 4313 orrs r3, r2 800509a: 604b str r3, [r1, #4] (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800509c: 4b1b ldr r3, [pc, #108] @ (800510c ) 800509e: 2201 movs r2, #1 80050a0: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80050a2: f7fc fc91 bl 80019c8 80050a6: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80050a8: e008 b.n 80050bc { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80050aa: f7fc fc8d bl 80019c8 80050ae: 4602 mov r2, r0 80050b0: 693b ldr r3, [r7, #16] 80050b2: 1ad3 subs r3, r2, r3 80050b4: 2b02 cmp r3, #2 80050b6: d901 bls.n 80050bc { return HAL_TIMEOUT; 80050b8: 2303 movs r3, #3 80050ba: e064 b.n 8005186 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80050bc: 4b11 ldr r3, [pc, #68] @ (8005104 ) 80050be: 681b ldr r3, [r3, #0] 80050c0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80050c4: 2b00 cmp r3, #0 80050c6: d0f0 beq.n 80050aa 80050c8: e05c b.n 8005184 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80050ca: 4b10 ldr r3, [pc, #64] @ (800510c ) 80050cc: 2200 movs r2, #0 80050ce: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80050d0: f7fc fc7a bl 80019c8 80050d4: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80050d6: e008 b.n 80050ea { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80050d8: f7fc fc76 bl 80019c8 80050dc: 4602 mov r2, r0 80050de: 693b ldr r3, [r7, #16] 80050e0: 1ad3 subs r3, r2, r3 80050e2: 2b02 cmp r3, #2 80050e4: d901 bls.n 80050ea { return HAL_TIMEOUT; 80050e6: 2303 movs r3, #3 80050e8: e04d b.n 8005186 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80050ea: 4b06 ldr r3, [pc, #24] @ (8005104 ) 80050ec: 681b ldr r3, [r3, #0] 80050ee: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80050f2: 2b00 cmp r3, #0 80050f4: d1f0 bne.n 80050d8 80050f6: e045 b.n 8005184 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80050f8: 687b ldr r3, [r7, #4] 80050fa: 699b ldr r3, [r3, #24] 80050fc: 2b01 cmp r3, #1 80050fe: d107 bne.n 8005110 { return HAL_ERROR; 8005100: 2301 movs r3, #1 8005102: e040 b.n 8005186 8005104: 40023800 .word 0x40023800 8005108: 40007000 .word 0x40007000 800510c: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 8005110: 4b1f ldr r3, [pc, #124] @ (8005190 ) 8005112: 685b ldr r3, [r3, #4] 8005114: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8005116: 687b ldr r3, [r7, #4] 8005118: 699b ldr r3, [r3, #24] 800511a: 2b01 cmp r3, #1 800511c: d030 beq.n 8005180 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800511e: 68fb ldr r3, [r7, #12] 8005120: f403 0280 and.w r2, r3, #4194304 @ 0x400000 8005124: 687b ldr r3, [r7, #4] 8005126: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8005128: 429a cmp r2, r3 800512a: d129 bne.n 8005180 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 800512c: 68fb ldr r3, [r7, #12] 800512e: f003 023f and.w r2, r3, #63 @ 0x3f 8005132: 687b ldr r3, [r7, #4] 8005134: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8005136: 429a cmp r2, r3 8005138: d122 bne.n 8005180 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 800513a: 68fa ldr r2, [r7, #12] 800513c: f647 73c0 movw r3, #32704 @ 0x7fc0 8005140: 4013 ands r3, r2 8005142: 687a ldr r2, [r7, #4] 8005144: 6a52 ldr r2, [r2, #36] @ 0x24 8005146: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 8005148: 4293 cmp r3, r2 800514a: d119 bne.n 8005180 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 800514c: 68fb ldr r3, [r7, #12] 800514e: f403 3240 and.w r2, r3, #196608 @ 0x30000 8005152: 687b ldr r3, [r7, #4] 8005154: 6a9b ldr r3, [r3, #40] @ 0x28 8005156: 085b lsrs r3, r3, #1 8005158: 3b01 subs r3, #1 800515a: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 800515c: 429a cmp r2, r3 800515e: d10f bne.n 8005180 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 8005160: 68fb ldr r3, [r7, #12] 8005162: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 8005166: 687b ldr r3, [r7, #4] 8005168: 6adb ldr r3, [r3, #44] @ 0x2c 800516a: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 800516c: 429a cmp r2, r3 800516e: d107 bne.n 8005180 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) 8005170: 68fb ldr r3, [r7, #12] 8005172: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000 8005176: 687b ldr r3, [r7, #4] 8005178: 6b1b ldr r3, [r3, #48] @ 0x30 800517a: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 800517c: 429a cmp r2, r3 800517e: d001 beq.n 8005184 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; 8005180: 2301 movs r3, #1 8005182: e000 b.n 8005186 } } } } return HAL_OK; 8005184: 2300 movs r3, #0 } 8005186: 4618 mov r0, r3 8005188: 3718 adds r7, #24 800518a: 46bd mov sp, r7 800518c: bd80 pop {r7, pc} 800518e: bf00 nop 8005190: 40023800 .word 0x40023800 08005194 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8005194: b580 push {r7, lr} 8005196: b082 sub sp, #8 8005198: af00 add r7, sp, #0 800519a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800519c: 687b ldr r3, [r7, #4] 800519e: 2b00 cmp r3, #0 80051a0: d101 bne.n 80051a6 { return HAL_ERROR; 80051a2: 2301 movs r3, #1 80051a4: e041 b.n 800522a assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 80051a6: 687b ldr r3, [r7, #4] 80051a8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80051ac: b2db uxtb r3, r3 80051ae: 2b00 cmp r3, #0 80051b0: d106 bne.n 80051c0 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80051b2: 687b ldr r3, [r7, #4] 80051b4: 2200 movs r2, #0 80051b6: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 80051ba: 6878 ldr r0, [r7, #4] 80051bc: f7fb ff6a bl 8001094 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80051c0: 687b ldr r3, [r7, #4] 80051c2: 2202 movs r2, #2 80051c4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80051c8: 687b ldr r3, [r7, #4] 80051ca: 681a ldr r2, [r3, #0] 80051cc: 687b ldr r3, [r7, #4] 80051ce: 3304 adds r3, #4 80051d0: 4619 mov r1, r3 80051d2: 4610 mov r0, r2 80051d4: f000 f930 bl 8005438 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 80051d8: 687b ldr r3, [r7, #4] 80051da: 2201 movs r2, #1 80051dc: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80051e0: 687b ldr r3, [r7, #4] 80051e2: 2201 movs r2, #1 80051e4: f883 203e strb.w r2, [r3, #62] @ 0x3e 80051e8: 687b ldr r3, [r7, #4] 80051ea: 2201 movs r2, #1 80051ec: f883 203f strb.w r2, [r3, #63] @ 0x3f 80051f0: 687b ldr r3, [r7, #4] 80051f2: 2201 movs r2, #1 80051f4: f883 2040 strb.w r2, [r3, #64] @ 0x40 80051f8: 687b ldr r3, [r7, #4] 80051fa: 2201 movs r2, #1 80051fc: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005200: 687b ldr r3, [r7, #4] 8005202: 2201 movs r2, #1 8005204: f883 2042 strb.w r2, [r3, #66] @ 0x42 8005208: 687b ldr r3, [r7, #4] 800520a: 2201 movs r2, #1 800520c: f883 2043 strb.w r2, [r3, #67] @ 0x43 8005210: 687b ldr r3, [r7, #4] 8005212: 2201 movs r2, #1 8005214: f883 2044 strb.w r2, [r3, #68] @ 0x44 8005218: 687b ldr r3, [r7, #4] 800521a: 2201 movs r2, #1 800521c: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005220: 687b ldr r3, [r7, #4] 8005222: 2201 movs r2, #1 8005224: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8005228: 2300 movs r3, #0 } 800522a: 4618 mov r0, r3 800522c: 3708 adds r7, #8 800522e: 46bd mov sp, r7 8005230: bd80 pop {r7, pc} 08005232 : * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { 8005232: b580 push {r7, lr} 8005234: b086 sub sp, #24 8005236: af00 add r7, sp, #0 8005238: 6078 str r0, [r7, #4] 800523a: 6039 str r1, [r7, #0] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) 800523c: 687b ldr r3, [r7, #4] 800523e: 2b00 cmp r3, #0 8005240: d101 bne.n 8005246 { return HAL_ERROR; 8005242: 2301 movs r3, #1 8005244: e097 b.n 8005376 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) 8005246: 687b ldr r3, [r7, #4] 8005248: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800524c: b2db uxtb r3, r3 800524e: 2b00 cmp r3, #0 8005250: d106 bne.n 8005260 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005252: 687b ldr r3, [r7, #4] 8005254: 2200 movs r2, #0 8005256: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); 800525a: 6878 ldr r0, [r7, #4] 800525c: f7fb ff3a bl 80010d4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005260: 687b ldr r3, [r7, #4] 8005262: 2202 movs r2, #2 8005264: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); 8005268: 687b ldr r3, [r7, #4] 800526a: 681b ldr r3, [r3, #0] 800526c: 689b ldr r3, [r3, #8] 800526e: 687a ldr r2, [r7, #4] 8005270: 6812 ldr r2, [r2, #0] 8005272: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8005276: f023 0307 bic.w r3, r3, #7 800527a: 6093 str r3, [r2, #8] /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800527c: 687b ldr r3, [r7, #4] 800527e: 681a ldr r2, [r3, #0] 8005280: 687b ldr r3, [r7, #4] 8005282: 3304 adds r3, #4 8005284: 4619 mov r1, r3 8005286: 4610 mov r0, r2 8005288: f000 f8d6 bl 8005438 /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 800528c: 687b ldr r3, [r7, #4] 800528e: 681b ldr r3, [r3, #0] 8005290: 689b ldr r3, [r3, #8] 8005292: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; 8005294: 687b ldr r3, [r7, #4] 8005296: 681b ldr r3, [r3, #0] 8005298: 699b ldr r3, [r3, #24] 800529a: 613b str r3, [r7, #16] /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; 800529c: 687b ldr r3, [r7, #4] 800529e: 681b ldr r3, [r3, #0] 80052a0: 6a1b ldr r3, [r3, #32] 80052a2: 60fb str r3, [r7, #12] /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; 80052a4: 683b ldr r3, [r7, #0] 80052a6: 681b ldr r3, [r3, #0] 80052a8: 697a ldr r2, [r7, #20] 80052aa: 4313 orrs r3, r2 80052ac: 617b str r3, [r7, #20] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 80052ae: 693b ldr r3, [r7, #16] 80052b0: f423 7340 bic.w r3, r3, #768 @ 0x300 80052b4: f023 0303 bic.w r3, r3, #3 80052b8: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); 80052ba: 683b ldr r3, [r7, #0] 80052bc: 689a ldr r2, [r3, #8] 80052be: 683b ldr r3, [r7, #0] 80052c0: 699b ldr r3, [r3, #24] 80052c2: 021b lsls r3, r3, #8 80052c4: 4313 orrs r3, r2 80052c6: 693a ldr r2, [r7, #16] 80052c8: 4313 orrs r3, r2 80052ca: 613b str r3, [r7, #16] /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 80052cc: 693b ldr r3, [r7, #16] 80052ce: f423 6340 bic.w r3, r3, #3072 @ 0xc00 80052d2: f023 030c bic.w r3, r3, #12 80052d6: 613b str r3, [r7, #16] tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 80052d8: 693b ldr r3, [r7, #16] 80052da: f423 4370 bic.w r3, r3, #61440 @ 0xf000 80052de: f023 03f0 bic.w r3, r3, #240 @ 0xf0 80052e2: 613b str r3, [r7, #16] tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); 80052e4: 683b ldr r3, [r7, #0] 80052e6: 68da ldr r2, [r3, #12] 80052e8: 683b ldr r3, [r7, #0] 80052ea: 69db ldr r3, [r3, #28] 80052ec: 021b lsls r3, r3, #8 80052ee: 4313 orrs r3, r2 80052f0: 693a ldr r2, [r7, #16] 80052f2: 4313 orrs r3, r2 80052f4: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); 80052f6: 683b ldr r3, [r7, #0] 80052f8: 691b ldr r3, [r3, #16] 80052fa: 011a lsls r2, r3, #4 80052fc: 683b ldr r3, [r7, #0] 80052fe: 6a1b ldr r3, [r3, #32] 8005300: 031b lsls r3, r3, #12 8005302: 4313 orrs r3, r2 8005304: 693a ldr r2, [r7, #16] 8005306: 4313 orrs r3, r2 8005308: 613b str r3, [r7, #16] /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 800530a: 68fb ldr r3, [r7, #12] 800530c: f023 0322 bic.w r3, r3, #34 @ 0x22 8005310: 60fb str r3, [r7, #12] tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 8005312: 68fb ldr r3, [r7, #12] 8005314: f023 0388 bic.w r3, r3, #136 @ 0x88 8005318: 60fb str r3, [r7, #12] tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); 800531a: 683b ldr r3, [r7, #0] 800531c: 685a ldr r2, [r3, #4] 800531e: 683b ldr r3, [r7, #0] 8005320: 695b ldr r3, [r3, #20] 8005322: 011b lsls r3, r3, #4 8005324: 4313 orrs r3, r2 8005326: 68fa ldr r2, [r7, #12] 8005328: 4313 orrs r3, r2 800532a: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800532c: 687b ldr r3, [r7, #4] 800532e: 681b ldr r3, [r3, #0] 8005330: 697a ldr r2, [r7, #20] 8005332: 609a str r2, [r3, #8] /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; 8005334: 687b ldr r3, [r7, #4] 8005336: 681b ldr r3, [r3, #0] 8005338: 693a ldr r2, [r7, #16] 800533a: 619a str r2, [r3, #24] /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; 800533c: 687b ldr r3, [r7, #4] 800533e: 681b ldr r3, [r3, #0] 8005340: 68fa ldr r2, [r7, #12] 8005342: 621a str r2, [r3, #32] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005344: 687b ldr r3, [r7, #4] 8005346: 2201 movs r2, #1 8005348: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 800534c: 687b ldr r3, [r7, #4] 800534e: 2201 movs r2, #1 8005350: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005354: 687b ldr r3, [r7, #4] 8005356: 2201 movs r2, #1 8005358: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 800535c: 687b ldr r3, [r7, #4] 800535e: 2201 movs r2, #1 8005360: f883 2042 strb.w r2, [r3, #66] @ 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005364: 687b ldr r3, [r7, #4] 8005366: 2201 movs r2, #1 8005368: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800536c: 687b ldr r3, [r7, #4] 800536e: 2201 movs r2, #1 8005370: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8005374: 2300 movs r3, #0 } 8005376: 4618 mov r0, r3 8005378: 3718 adds r7, #24 800537a: 46bd mov sp, r7 800537c: bd80 pop {r7, pc} ... 08005380 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8005380: b580 push {r7, lr} 8005382: b086 sub sp, #24 8005384: af00 add r7, sp, #0 8005386: 60f8 str r0, [r7, #12] 8005388: 60b9 str r1, [r7, #8] 800538a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800538c: 2300 movs r3, #0 800538e: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 8005390: 68fb ldr r3, [r7, #12] 8005392: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005396: 2b01 cmp r3, #1 8005398: d101 bne.n 800539e 800539a: 2302 movs r3, #2 800539c: e048 b.n 8005430 800539e: 68fb ldr r3, [r7, #12] 80053a0: 2201 movs r2, #1 80053a2: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 80053a6: 687b ldr r3, [r7, #4] 80053a8: 2b0c cmp r3, #12 80053aa: d839 bhi.n 8005420 80053ac: a201 add r2, pc, #4 @ (adr r2, 80053b4 ) 80053ae: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80053b2: bf00 nop 80053b4: 080053e9 .word 0x080053e9 80053b8: 08005421 .word 0x08005421 80053bc: 08005421 .word 0x08005421 80053c0: 08005421 .word 0x08005421 80053c4: 080053f7 .word 0x080053f7 80053c8: 08005421 .word 0x08005421 80053cc: 08005421 .word 0x08005421 80053d0: 08005421 .word 0x08005421 80053d4: 08005405 .word 0x08005405 80053d8: 08005421 .word 0x08005421 80053dc: 08005421 .word 0x08005421 80053e0: 08005421 .word 0x08005421 80053e4: 08005413 .word 0x08005413 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 80053e8: 68fb ldr r3, [r7, #12] 80053ea: 681b ldr r3, [r3, #0] 80053ec: 68b9 ldr r1, [r7, #8] 80053ee: 4618 mov r0, r3 80053f0: f000 f8c8 bl 8005584 break; 80053f4: e017 b.n 8005426 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 80053f6: 68fb ldr r3, [r7, #12] 80053f8: 681b ldr r3, [r3, #0] 80053fa: 68b9 ldr r1, [r7, #8] 80053fc: 4618 mov r0, r3 80053fe: f000 f931 bl 8005664 break; 8005402: e010 b.n 8005426 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8005404: 68fb ldr r3, [r7, #12] 8005406: 681b ldr r3, [r3, #0] 8005408: 68b9 ldr r1, [r7, #8] 800540a: 4618 mov r0, r3 800540c: f000 f9a0 bl 8005750 break; 8005410: e009 b.n 8005426 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8005412: 68fb ldr r3, [r7, #12] 8005414: 681b ldr r3, [r3, #0] 8005416: 68b9 ldr r1, [r7, #8] 8005418: 4618 mov r0, r3 800541a: f000 fa0d bl 8005838 break; 800541e: e002 b.n 8005426 } default: status = HAL_ERROR; 8005420: 2301 movs r3, #1 8005422: 75fb strb r3, [r7, #23] break; 8005424: bf00 nop } __HAL_UNLOCK(htim); 8005426: 68fb ldr r3, [r7, #12] 8005428: 2200 movs r2, #0 800542a: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800542e: 7dfb ldrb r3, [r7, #23] } 8005430: 4618 mov r0, r3 8005432: 3718 adds r7, #24 8005434: 46bd mov sp, r7 8005436: bd80 pop {r7, pc} 08005438 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8005438: b480 push {r7} 800543a: b085 sub sp, #20 800543c: af00 add r7, sp, #0 800543e: 6078 str r0, [r7, #4] 8005440: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8005442: 687b ldr r3, [r7, #4] 8005444: 681b ldr r3, [r3, #0] 8005446: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8005448: 687b ldr r3, [r7, #4] 800544a: 4a43 ldr r2, [pc, #268] @ (8005558 ) 800544c: 4293 cmp r3, r2 800544e: d013 beq.n 8005478 8005450: 687b ldr r3, [r7, #4] 8005452: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005456: d00f beq.n 8005478 8005458: 687b ldr r3, [r7, #4] 800545a: 4a40 ldr r2, [pc, #256] @ (800555c ) 800545c: 4293 cmp r3, r2 800545e: d00b beq.n 8005478 8005460: 687b ldr r3, [r7, #4] 8005462: 4a3f ldr r2, [pc, #252] @ (8005560 ) 8005464: 4293 cmp r3, r2 8005466: d007 beq.n 8005478 8005468: 687b ldr r3, [r7, #4] 800546a: 4a3e ldr r2, [pc, #248] @ (8005564 ) 800546c: 4293 cmp r3, r2 800546e: d003 beq.n 8005478 8005470: 687b ldr r3, [r7, #4] 8005472: 4a3d ldr r2, [pc, #244] @ (8005568 ) 8005474: 4293 cmp r3, r2 8005476: d108 bne.n 800548a { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8005478: 68fb ldr r3, [r7, #12] 800547a: f023 0370 bic.w r3, r3, #112 @ 0x70 800547e: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8005480: 683b ldr r3, [r7, #0] 8005482: 685b ldr r3, [r3, #4] 8005484: 68fa ldr r2, [r7, #12] 8005486: 4313 orrs r3, r2 8005488: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800548a: 687b ldr r3, [r7, #4] 800548c: 4a32 ldr r2, [pc, #200] @ (8005558 ) 800548e: 4293 cmp r3, r2 8005490: d02b beq.n 80054ea 8005492: 687b ldr r3, [r7, #4] 8005494: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005498: d027 beq.n 80054ea 800549a: 687b ldr r3, [r7, #4] 800549c: 4a2f ldr r2, [pc, #188] @ (800555c ) 800549e: 4293 cmp r3, r2 80054a0: d023 beq.n 80054ea 80054a2: 687b ldr r3, [r7, #4] 80054a4: 4a2e ldr r2, [pc, #184] @ (8005560 ) 80054a6: 4293 cmp r3, r2 80054a8: d01f beq.n 80054ea 80054aa: 687b ldr r3, [r7, #4] 80054ac: 4a2d ldr r2, [pc, #180] @ (8005564 ) 80054ae: 4293 cmp r3, r2 80054b0: d01b beq.n 80054ea 80054b2: 687b ldr r3, [r7, #4] 80054b4: 4a2c ldr r2, [pc, #176] @ (8005568 ) 80054b6: 4293 cmp r3, r2 80054b8: d017 beq.n 80054ea 80054ba: 687b ldr r3, [r7, #4] 80054bc: 4a2b ldr r2, [pc, #172] @ (800556c ) 80054be: 4293 cmp r3, r2 80054c0: d013 beq.n 80054ea 80054c2: 687b ldr r3, [r7, #4] 80054c4: 4a2a ldr r2, [pc, #168] @ (8005570 ) 80054c6: 4293 cmp r3, r2 80054c8: d00f beq.n 80054ea 80054ca: 687b ldr r3, [r7, #4] 80054cc: 4a29 ldr r2, [pc, #164] @ (8005574 ) 80054ce: 4293 cmp r3, r2 80054d0: d00b beq.n 80054ea 80054d2: 687b ldr r3, [r7, #4] 80054d4: 4a28 ldr r2, [pc, #160] @ (8005578 ) 80054d6: 4293 cmp r3, r2 80054d8: d007 beq.n 80054ea 80054da: 687b ldr r3, [r7, #4] 80054dc: 4a27 ldr r2, [pc, #156] @ (800557c ) 80054de: 4293 cmp r3, r2 80054e0: d003 beq.n 80054ea 80054e2: 687b ldr r3, [r7, #4] 80054e4: 4a26 ldr r2, [pc, #152] @ (8005580 ) 80054e6: 4293 cmp r3, r2 80054e8: d108 bne.n 80054fc { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80054ea: 68fb ldr r3, [r7, #12] 80054ec: f423 7340 bic.w r3, r3, #768 @ 0x300 80054f0: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80054f2: 683b ldr r3, [r7, #0] 80054f4: 68db ldr r3, [r3, #12] 80054f6: 68fa ldr r2, [r7, #12] 80054f8: 4313 orrs r3, r2 80054fa: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80054fc: 68fb ldr r3, [r7, #12] 80054fe: f023 0280 bic.w r2, r3, #128 @ 0x80 8005502: 683b ldr r3, [r7, #0] 8005504: 695b ldr r3, [r3, #20] 8005506: 4313 orrs r3, r2 8005508: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800550a: 683b ldr r3, [r7, #0] 800550c: 689a ldr r2, [r3, #8] 800550e: 687b ldr r3, [r7, #4] 8005510: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8005512: 683b ldr r3, [r7, #0] 8005514: 681a ldr r2, [r3, #0] 8005516: 687b ldr r3, [r7, #4] 8005518: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800551a: 687b ldr r3, [r7, #4] 800551c: 4a0e ldr r2, [pc, #56] @ (8005558 ) 800551e: 4293 cmp r3, r2 8005520: d003 beq.n 800552a 8005522: 687b ldr r3, [r7, #4] 8005524: 4a10 ldr r2, [pc, #64] @ (8005568 ) 8005526: 4293 cmp r3, r2 8005528: d103 bne.n 8005532 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800552a: 683b ldr r3, [r7, #0] 800552c: 691a ldr r2, [r3, #16] 800552e: 687b ldr r3, [r7, #4] 8005530: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 8005532: 687b ldr r3, [r7, #4] 8005534: 681b ldr r3, [r3, #0] 8005536: f043 0204 orr.w r2, r3, #4 800553a: 687b ldr r3, [r7, #4] 800553c: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800553e: 687b ldr r3, [r7, #4] 8005540: 2201 movs r2, #1 8005542: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 8005544: 687b ldr r3, [r7, #4] 8005546: 68fa ldr r2, [r7, #12] 8005548: 601a str r2, [r3, #0] } 800554a: bf00 nop 800554c: 3714 adds r7, #20 800554e: 46bd mov sp, r7 8005550: f85d 7b04 ldr.w r7, [sp], #4 8005554: 4770 bx lr 8005556: bf00 nop 8005558: 40010000 .word 0x40010000 800555c: 40000400 .word 0x40000400 8005560: 40000800 .word 0x40000800 8005564: 40000c00 .word 0x40000c00 8005568: 40010400 .word 0x40010400 800556c: 40014000 .word 0x40014000 8005570: 40014400 .word 0x40014400 8005574: 40014800 .word 0x40014800 8005578: 40001800 .word 0x40001800 800557c: 40001c00 .word 0x40001c00 8005580: 40002000 .word 0x40002000 08005584 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005584: b480 push {r7} 8005586: b087 sub sp, #28 8005588: af00 add r7, sp, #0 800558a: 6078 str r0, [r7, #4] 800558c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800558e: 687b ldr r3, [r7, #4] 8005590: 6a1b ldr r3, [r3, #32] 8005592: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8005594: 687b ldr r3, [r7, #4] 8005596: 6a1b ldr r3, [r3, #32] 8005598: f023 0201 bic.w r2, r3, #1 800559c: 687b ldr r3, [r7, #4] 800559e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80055a0: 687b ldr r3, [r7, #4] 80055a2: 685b ldr r3, [r3, #4] 80055a4: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80055a6: 687b ldr r3, [r7, #4] 80055a8: 699b ldr r3, [r3, #24] 80055aa: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80055ac: 68fb ldr r3, [r7, #12] 80055ae: f023 0370 bic.w r3, r3, #112 @ 0x70 80055b2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80055b4: 68fb ldr r3, [r7, #12] 80055b6: f023 0303 bic.w r3, r3, #3 80055ba: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80055bc: 683b ldr r3, [r7, #0] 80055be: 681b ldr r3, [r3, #0] 80055c0: 68fa ldr r2, [r7, #12] 80055c2: 4313 orrs r3, r2 80055c4: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 80055c6: 697b ldr r3, [r7, #20] 80055c8: f023 0302 bic.w r3, r3, #2 80055cc: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 80055ce: 683b ldr r3, [r7, #0] 80055d0: 689b ldr r3, [r3, #8] 80055d2: 697a ldr r2, [r7, #20] 80055d4: 4313 orrs r3, r2 80055d6: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 80055d8: 687b ldr r3, [r7, #4] 80055da: 4a20 ldr r2, [pc, #128] @ (800565c ) 80055dc: 4293 cmp r3, r2 80055de: d003 beq.n 80055e8 80055e0: 687b ldr r3, [r7, #4] 80055e2: 4a1f ldr r2, [pc, #124] @ (8005660 ) 80055e4: 4293 cmp r3, r2 80055e6: d10c bne.n 8005602 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 80055e8: 697b ldr r3, [r7, #20] 80055ea: f023 0308 bic.w r3, r3, #8 80055ee: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 80055f0: 683b ldr r3, [r7, #0] 80055f2: 68db ldr r3, [r3, #12] 80055f4: 697a ldr r2, [r7, #20] 80055f6: 4313 orrs r3, r2 80055f8: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 80055fa: 697b ldr r3, [r7, #20] 80055fc: f023 0304 bic.w r3, r3, #4 8005600: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005602: 687b ldr r3, [r7, #4] 8005604: 4a15 ldr r2, [pc, #84] @ (800565c ) 8005606: 4293 cmp r3, r2 8005608: d003 beq.n 8005612 800560a: 687b ldr r3, [r7, #4] 800560c: 4a14 ldr r2, [pc, #80] @ (8005660 ) 800560e: 4293 cmp r3, r2 8005610: d111 bne.n 8005636 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8005612: 693b ldr r3, [r7, #16] 8005614: f423 7380 bic.w r3, r3, #256 @ 0x100 8005618: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 800561a: 693b ldr r3, [r7, #16] 800561c: f423 7300 bic.w r3, r3, #512 @ 0x200 8005620: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8005622: 683b ldr r3, [r7, #0] 8005624: 695b ldr r3, [r3, #20] 8005626: 693a ldr r2, [r7, #16] 8005628: 4313 orrs r3, r2 800562a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800562c: 683b ldr r3, [r7, #0] 800562e: 699b ldr r3, [r3, #24] 8005630: 693a ldr r2, [r7, #16] 8005632: 4313 orrs r3, r2 8005634: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005636: 687b ldr r3, [r7, #4] 8005638: 693a ldr r2, [r7, #16] 800563a: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800563c: 687b ldr r3, [r7, #4] 800563e: 68fa ldr r2, [r7, #12] 8005640: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8005642: 683b ldr r3, [r7, #0] 8005644: 685a ldr r2, [r3, #4] 8005646: 687b ldr r3, [r7, #4] 8005648: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800564a: 687b ldr r3, [r7, #4] 800564c: 697a ldr r2, [r7, #20] 800564e: 621a str r2, [r3, #32] } 8005650: bf00 nop 8005652: 371c adds r7, #28 8005654: 46bd mov sp, r7 8005656: f85d 7b04 ldr.w r7, [sp], #4 800565a: 4770 bx lr 800565c: 40010000 .word 0x40010000 8005660: 40010400 .word 0x40010400 08005664 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005664: b480 push {r7} 8005666: b087 sub sp, #28 8005668: af00 add r7, sp, #0 800566a: 6078 str r0, [r7, #4] 800566c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800566e: 687b ldr r3, [r7, #4] 8005670: 6a1b ldr r3, [r3, #32] 8005672: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8005674: 687b ldr r3, [r7, #4] 8005676: 6a1b ldr r3, [r3, #32] 8005678: f023 0210 bic.w r2, r3, #16 800567c: 687b ldr r3, [r7, #4] 800567e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005680: 687b ldr r3, [r7, #4] 8005682: 685b ldr r3, [r3, #4] 8005684: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8005686: 687b ldr r3, [r7, #4] 8005688: 699b ldr r3, [r3, #24] 800568a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 800568c: 68fb ldr r3, [r7, #12] 800568e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8005692: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8005694: 68fb ldr r3, [r7, #12] 8005696: f423 7340 bic.w r3, r3, #768 @ 0x300 800569a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800569c: 683b ldr r3, [r7, #0] 800569e: 681b ldr r3, [r3, #0] 80056a0: 021b lsls r3, r3, #8 80056a2: 68fa ldr r2, [r7, #12] 80056a4: 4313 orrs r3, r2 80056a6: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80056a8: 697b ldr r3, [r7, #20] 80056aa: f023 0320 bic.w r3, r3, #32 80056ae: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80056b0: 683b ldr r3, [r7, #0] 80056b2: 689b ldr r3, [r3, #8] 80056b4: 011b lsls r3, r3, #4 80056b6: 697a ldr r2, [r7, #20] 80056b8: 4313 orrs r3, r2 80056ba: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80056bc: 687b ldr r3, [r7, #4] 80056be: 4a22 ldr r2, [pc, #136] @ (8005748 ) 80056c0: 4293 cmp r3, r2 80056c2: d003 beq.n 80056cc 80056c4: 687b ldr r3, [r7, #4] 80056c6: 4a21 ldr r2, [pc, #132] @ (800574c ) 80056c8: 4293 cmp r3, r2 80056ca: d10d bne.n 80056e8 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 80056cc: 697b ldr r3, [r7, #20] 80056ce: f023 0380 bic.w r3, r3, #128 @ 0x80 80056d2: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 80056d4: 683b ldr r3, [r7, #0] 80056d6: 68db ldr r3, [r3, #12] 80056d8: 011b lsls r3, r3, #4 80056da: 697a ldr r2, [r7, #20] 80056dc: 4313 orrs r3, r2 80056de: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 80056e0: 697b ldr r3, [r7, #20] 80056e2: f023 0340 bic.w r3, r3, #64 @ 0x40 80056e6: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80056e8: 687b ldr r3, [r7, #4] 80056ea: 4a17 ldr r2, [pc, #92] @ (8005748 ) 80056ec: 4293 cmp r3, r2 80056ee: d003 beq.n 80056f8 80056f0: 687b ldr r3, [r7, #4] 80056f2: 4a16 ldr r2, [pc, #88] @ (800574c ) 80056f4: 4293 cmp r3, r2 80056f6: d113 bne.n 8005720 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 80056f8: 693b ldr r3, [r7, #16] 80056fa: f423 6380 bic.w r3, r3, #1024 @ 0x400 80056fe: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8005700: 693b ldr r3, [r7, #16] 8005702: f423 6300 bic.w r3, r3, #2048 @ 0x800 8005706: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8005708: 683b ldr r3, [r7, #0] 800570a: 695b ldr r3, [r3, #20] 800570c: 009b lsls r3, r3, #2 800570e: 693a ldr r2, [r7, #16] 8005710: 4313 orrs r3, r2 8005712: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8005714: 683b ldr r3, [r7, #0] 8005716: 699b ldr r3, [r3, #24] 8005718: 009b lsls r3, r3, #2 800571a: 693a ldr r2, [r7, #16] 800571c: 4313 orrs r3, r2 800571e: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005720: 687b ldr r3, [r7, #4] 8005722: 693a ldr r2, [r7, #16] 8005724: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8005726: 687b ldr r3, [r7, #4] 8005728: 68fa ldr r2, [r7, #12] 800572a: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 800572c: 683b ldr r3, [r7, #0] 800572e: 685a ldr r2, [r3, #4] 8005730: 687b ldr r3, [r7, #4] 8005732: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005734: 687b ldr r3, [r7, #4] 8005736: 697a ldr r2, [r7, #20] 8005738: 621a str r2, [r3, #32] } 800573a: bf00 nop 800573c: 371c adds r7, #28 800573e: 46bd mov sp, r7 8005740: f85d 7b04 ldr.w r7, [sp], #4 8005744: 4770 bx lr 8005746: bf00 nop 8005748: 40010000 .word 0x40010000 800574c: 40010400 .word 0x40010400 08005750 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005750: b480 push {r7} 8005752: b087 sub sp, #28 8005754: af00 add r7, sp, #0 8005756: 6078 str r0, [r7, #4] 8005758: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800575a: 687b ldr r3, [r7, #4] 800575c: 6a1b ldr r3, [r3, #32] 800575e: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8005760: 687b ldr r3, [r7, #4] 8005762: 6a1b ldr r3, [r3, #32] 8005764: f423 7280 bic.w r2, r3, #256 @ 0x100 8005768: 687b ldr r3, [r7, #4] 800576a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800576c: 687b ldr r3, [r7, #4] 800576e: 685b ldr r3, [r3, #4] 8005770: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8005772: 687b ldr r3, [r7, #4] 8005774: 69db ldr r3, [r3, #28] 8005776: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8005778: 68fb ldr r3, [r7, #12] 800577a: f023 0370 bic.w r3, r3, #112 @ 0x70 800577e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8005780: 68fb ldr r3, [r7, #12] 8005782: f023 0303 bic.w r3, r3, #3 8005786: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8005788: 683b ldr r3, [r7, #0] 800578a: 681b ldr r3, [r3, #0] 800578c: 68fa ldr r2, [r7, #12] 800578e: 4313 orrs r3, r2 8005790: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8005792: 697b ldr r3, [r7, #20] 8005794: f423 7300 bic.w r3, r3, #512 @ 0x200 8005798: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 800579a: 683b ldr r3, [r7, #0] 800579c: 689b ldr r3, [r3, #8] 800579e: 021b lsls r3, r3, #8 80057a0: 697a ldr r2, [r7, #20] 80057a2: 4313 orrs r3, r2 80057a4: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 80057a6: 687b ldr r3, [r7, #4] 80057a8: 4a21 ldr r2, [pc, #132] @ (8005830 ) 80057aa: 4293 cmp r3, r2 80057ac: d003 beq.n 80057b6 80057ae: 687b ldr r3, [r7, #4] 80057b0: 4a20 ldr r2, [pc, #128] @ (8005834 ) 80057b2: 4293 cmp r3, r2 80057b4: d10d bne.n 80057d2 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 80057b6: 697b ldr r3, [r7, #20] 80057b8: f423 6300 bic.w r3, r3, #2048 @ 0x800 80057bc: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 80057be: 683b ldr r3, [r7, #0] 80057c0: 68db ldr r3, [r3, #12] 80057c2: 021b lsls r3, r3, #8 80057c4: 697a ldr r2, [r7, #20] 80057c6: 4313 orrs r3, r2 80057c8: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 80057ca: 697b ldr r3, [r7, #20] 80057cc: f423 6380 bic.w r3, r3, #1024 @ 0x400 80057d0: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80057d2: 687b ldr r3, [r7, #4] 80057d4: 4a16 ldr r2, [pc, #88] @ (8005830 ) 80057d6: 4293 cmp r3, r2 80057d8: d003 beq.n 80057e2 80057da: 687b ldr r3, [r7, #4] 80057dc: 4a15 ldr r2, [pc, #84] @ (8005834 ) 80057de: 4293 cmp r3, r2 80057e0: d113 bne.n 800580a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 80057e2: 693b ldr r3, [r7, #16] 80057e4: f423 5380 bic.w r3, r3, #4096 @ 0x1000 80057e8: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 80057ea: 693b ldr r3, [r7, #16] 80057ec: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80057f0: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 80057f2: 683b ldr r3, [r7, #0] 80057f4: 695b ldr r3, [r3, #20] 80057f6: 011b lsls r3, r3, #4 80057f8: 693a ldr r2, [r7, #16] 80057fa: 4313 orrs r3, r2 80057fc: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 80057fe: 683b ldr r3, [r7, #0] 8005800: 699b ldr r3, [r3, #24] 8005802: 011b lsls r3, r3, #4 8005804: 693a ldr r2, [r7, #16] 8005806: 4313 orrs r3, r2 8005808: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800580a: 687b ldr r3, [r7, #4] 800580c: 693a ldr r2, [r7, #16] 800580e: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8005810: 687b ldr r3, [r7, #4] 8005812: 68fa ldr r2, [r7, #12] 8005814: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8005816: 683b ldr r3, [r7, #0] 8005818: 685a ldr r2, [r3, #4] 800581a: 687b ldr r3, [r7, #4] 800581c: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800581e: 687b ldr r3, [r7, #4] 8005820: 697a ldr r2, [r7, #20] 8005822: 621a str r2, [r3, #32] } 8005824: bf00 nop 8005826: 371c adds r7, #28 8005828: 46bd mov sp, r7 800582a: f85d 7b04 ldr.w r7, [sp], #4 800582e: 4770 bx lr 8005830: 40010000 .word 0x40010000 8005834: 40010400 .word 0x40010400 08005838 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005838: b480 push {r7} 800583a: b087 sub sp, #28 800583c: af00 add r7, sp, #0 800583e: 6078 str r0, [r7, #4] 8005840: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8005842: 687b ldr r3, [r7, #4] 8005844: 6a1b ldr r3, [r3, #32] 8005846: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8005848: 687b ldr r3, [r7, #4] 800584a: 6a1b ldr r3, [r3, #32] 800584c: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8005850: 687b ldr r3, [r7, #4] 8005852: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005854: 687b ldr r3, [r7, #4] 8005856: 685b ldr r3, [r3, #4] 8005858: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800585a: 687b ldr r3, [r7, #4] 800585c: 69db ldr r3, [r3, #28] 800585e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8005860: 68fb ldr r3, [r7, #12] 8005862: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8005866: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8005868: 68fb ldr r3, [r7, #12] 800586a: f423 7340 bic.w r3, r3, #768 @ 0x300 800586e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8005870: 683b ldr r3, [r7, #0] 8005872: 681b ldr r3, [r3, #0] 8005874: 021b lsls r3, r3, #8 8005876: 68fa ldr r2, [r7, #12] 8005878: 4313 orrs r3, r2 800587a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 800587c: 693b ldr r3, [r7, #16] 800587e: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8005882: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8005884: 683b ldr r3, [r7, #0] 8005886: 689b ldr r3, [r3, #8] 8005888: 031b lsls r3, r3, #12 800588a: 693a ldr r2, [r7, #16] 800588c: 4313 orrs r3, r2 800588e: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005890: 687b ldr r3, [r7, #4] 8005892: 4a12 ldr r2, [pc, #72] @ (80058dc ) 8005894: 4293 cmp r3, r2 8005896: d003 beq.n 80058a0 8005898: 687b ldr r3, [r7, #4] 800589a: 4a11 ldr r2, [pc, #68] @ (80058e0 ) 800589c: 4293 cmp r3, r2 800589e: d109 bne.n 80058b4 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 80058a0: 697b ldr r3, [r7, #20] 80058a2: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80058a6: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 80058a8: 683b ldr r3, [r7, #0] 80058aa: 695b ldr r3, [r3, #20] 80058ac: 019b lsls r3, r3, #6 80058ae: 697a ldr r2, [r7, #20] 80058b0: 4313 orrs r3, r2 80058b2: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80058b4: 687b ldr r3, [r7, #4] 80058b6: 697a ldr r2, [r7, #20] 80058b8: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80058ba: 687b ldr r3, [r7, #4] 80058bc: 68fa ldr r2, [r7, #12] 80058be: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 80058c0: 683b ldr r3, [r7, #0] 80058c2: 685a ldr r2, [r3, #4] 80058c4: 687b ldr r3, [r7, #4] 80058c6: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80058c8: 687b ldr r3, [r7, #4] 80058ca: 693a ldr r2, [r7, #16] 80058cc: 621a str r2, [r3, #32] } 80058ce: bf00 nop 80058d0: 371c adds r7, #28 80058d2: 46bd mov sp, r7 80058d4: f85d 7b04 ldr.w r7, [sp], #4 80058d8: 4770 bx lr 80058da: bf00 nop 80058dc: 40010000 .word 0x40010000 80058e0: 40010400 .word 0x40010400 080058e4 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 80058e4: b480 push {r7} 80058e6: b085 sub sp, #20 80058e8: af00 add r7, sp, #0 80058ea: 6078 str r0, [r7, #4] 80058ec: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 80058ee: 687b ldr r3, [r7, #4] 80058f0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80058f4: 2b01 cmp r3, #1 80058f6: d101 bne.n 80058fc 80058f8: 2302 movs r3, #2 80058fa: e05a b.n 80059b2 80058fc: 687b ldr r3, [r7, #4] 80058fe: 2201 movs r2, #1 8005900: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8005904: 687b ldr r3, [r7, #4] 8005906: 2202 movs r2, #2 8005908: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 800590c: 687b ldr r3, [r7, #4] 800590e: 681b ldr r3, [r3, #0] 8005910: 685b ldr r3, [r3, #4] 8005912: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005914: 687b ldr r3, [r7, #4] 8005916: 681b ldr r3, [r3, #0] 8005918: 689b ldr r3, [r3, #8] 800591a: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 800591c: 68fb ldr r3, [r7, #12] 800591e: f023 0370 bic.w r3, r3, #112 @ 0x70 8005922: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8005924: 683b ldr r3, [r7, #0] 8005926: 681b ldr r3, [r3, #0] 8005928: 68fa ldr r2, [r7, #12] 800592a: 4313 orrs r3, r2 800592c: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 800592e: 687b ldr r3, [r7, #4] 8005930: 681b ldr r3, [r3, #0] 8005932: 68fa ldr r2, [r7, #12] 8005934: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005936: 687b ldr r3, [r7, #4] 8005938: 681b ldr r3, [r3, #0] 800593a: 4a21 ldr r2, [pc, #132] @ (80059c0 ) 800593c: 4293 cmp r3, r2 800593e: d022 beq.n 8005986 8005940: 687b ldr r3, [r7, #4] 8005942: 681b ldr r3, [r3, #0] 8005944: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005948: d01d beq.n 8005986 800594a: 687b ldr r3, [r7, #4] 800594c: 681b ldr r3, [r3, #0] 800594e: 4a1d ldr r2, [pc, #116] @ (80059c4 ) 8005950: 4293 cmp r3, r2 8005952: d018 beq.n 8005986 8005954: 687b ldr r3, [r7, #4] 8005956: 681b ldr r3, [r3, #0] 8005958: 4a1b ldr r2, [pc, #108] @ (80059c8 ) 800595a: 4293 cmp r3, r2 800595c: d013 beq.n 8005986 800595e: 687b ldr r3, [r7, #4] 8005960: 681b ldr r3, [r3, #0] 8005962: 4a1a ldr r2, [pc, #104] @ (80059cc ) 8005964: 4293 cmp r3, r2 8005966: d00e beq.n 8005986 8005968: 687b ldr r3, [r7, #4] 800596a: 681b ldr r3, [r3, #0] 800596c: 4a18 ldr r2, [pc, #96] @ (80059d0 ) 800596e: 4293 cmp r3, r2 8005970: d009 beq.n 8005986 8005972: 687b ldr r3, [r7, #4] 8005974: 681b ldr r3, [r3, #0] 8005976: 4a17 ldr r2, [pc, #92] @ (80059d4 ) 8005978: 4293 cmp r3, r2 800597a: d004 beq.n 8005986 800597c: 687b ldr r3, [r7, #4] 800597e: 681b ldr r3, [r3, #0] 8005980: 4a15 ldr r2, [pc, #84] @ (80059d8 ) 8005982: 4293 cmp r3, r2 8005984: d10c bne.n 80059a0 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8005986: 68bb ldr r3, [r7, #8] 8005988: f023 0380 bic.w r3, r3, #128 @ 0x80 800598c: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 800598e: 683b ldr r3, [r7, #0] 8005990: 685b ldr r3, [r3, #4] 8005992: 68ba ldr r2, [r7, #8] 8005994: 4313 orrs r3, r2 8005996: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005998: 687b ldr r3, [r7, #4] 800599a: 681b ldr r3, [r3, #0] 800599c: 68ba ldr r2, [r7, #8] 800599e: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80059a0: 687b ldr r3, [r7, #4] 80059a2: 2201 movs r2, #1 80059a4: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80059a8: 687b ldr r3, [r7, #4] 80059aa: 2200 movs r2, #0 80059ac: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 80059b0: 2300 movs r3, #0 } 80059b2: 4618 mov r0, r3 80059b4: 3714 adds r7, #20 80059b6: 46bd mov sp, r7 80059b8: f85d 7b04 ldr.w r7, [sp], #4 80059bc: 4770 bx lr 80059be: bf00 nop 80059c0: 40010000 .word 0x40010000 80059c4: 40000400 .word 0x40000400 80059c8: 40000800 .word 0x40000800 80059cc: 40000c00 .word 0x40000c00 80059d0: 40010400 .word 0x40010400 80059d4: 40014000 .word 0x40014000 80059d8: 40001800 .word 0x40001800 080059dc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 80059dc: b580 push {r7, lr} 80059de: b082 sub sp, #8 80059e0: af00 add r7, sp, #0 80059e2: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 80059e4: 687b ldr r3, [r7, #4] 80059e6: 2b00 cmp r3, #0 80059e8: d101 bne.n 80059ee { return HAL_ERROR; 80059ea: 2301 movs r3, #1 80059ec: e042 b.n 8005a74 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 80059ee: 687b ldr r3, [r7, #4] 80059f0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80059f4: b2db uxtb r3, r3 80059f6: 2b00 cmp r3, #0 80059f8: d106 bne.n 8005a08 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80059fa: 687b ldr r3, [r7, #4] 80059fc: 2200 movs r2, #0 80059fe: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8005a02: 6878 ldr r0, [r7, #4] 8005a04: f7fb fc8e bl 8001324 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8005a08: 687b ldr r3, [r7, #4] 8005a0a: 2224 movs r2, #36 @ 0x24 8005a0c: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8005a10: 687b ldr r3, [r7, #4] 8005a12: 681b ldr r3, [r3, #0] 8005a14: 68da ldr r2, [r3, #12] 8005a16: 687b ldr r3, [r7, #4] 8005a18: 681b ldr r3, [r3, #0] 8005a1a: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8005a1e: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8005a20: 6878 ldr r0, [r7, #4] 8005a22: f001 f851 bl 8006ac8 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8005a26: 687b ldr r3, [r7, #4] 8005a28: 681b ldr r3, [r3, #0] 8005a2a: 691a ldr r2, [r3, #16] 8005a2c: 687b ldr r3, [r7, #4] 8005a2e: 681b ldr r3, [r3, #0] 8005a30: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8005a34: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8005a36: 687b ldr r3, [r7, #4] 8005a38: 681b ldr r3, [r3, #0] 8005a3a: 695a ldr r2, [r3, #20] 8005a3c: 687b ldr r3, [r7, #4] 8005a3e: 681b ldr r3, [r3, #0] 8005a40: f022 022a bic.w r2, r2, #42 @ 0x2a 8005a44: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8005a46: 687b ldr r3, [r7, #4] 8005a48: 681b ldr r3, [r3, #0] 8005a4a: 68da ldr r2, [r3, #12] 8005a4c: 687b ldr r3, [r7, #4] 8005a4e: 681b ldr r3, [r3, #0] 8005a50: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8005a54: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005a56: 687b ldr r3, [r7, #4] 8005a58: 2200 movs r2, #0 8005a5a: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8005a5c: 687b ldr r3, [r7, #4] 8005a5e: 2220 movs r2, #32 8005a60: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8005a64: 687b ldr r3, [r7, #4] 8005a66: 2220 movs r2, #32 8005a68: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8005a6c: 687b ldr r3, [r7, #4] 8005a6e: 2200 movs r2, #0 8005a70: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8005a72: 2300 movs r3, #0 } 8005a74: 4618 mov r0, r3 8005a76: 3708 adds r7, #8 8005a78: 46bd mov sp, r7 8005a7a: bd80 pop {r7, pc} 08005a7c : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8005a7c: b580 push {r7, lr} 8005a7e: b08a sub sp, #40 @ 0x28 8005a80: af02 add r7, sp, #8 8005a82: 60f8 str r0, [r7, #12] 8005a84: 60b9 str r1, [r7, #8] 8005a86: 603b str r3, [r7, #0] 8005a88: 4613 mov r3, r2 8005a8a: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart = 0U; 8005a8c: 2300 movs r3, #0 8005a8e: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8005a90: 68fb ldr r3, [r7, #12] 8005a92: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005a96: b2db uxtb r3, r3 8005a98: 2b20 cmp r3, #32 8005a9a: d175 bne.n 8005b88 { if ((pData == NULL) || (Size == 0U)) 8005a9c: 68bb ldr r3, [r7, #8] 8005a9e: 2b00 cmp r3, #0 8005aa0: d002 beq.n 8005aa8 8005aa2: 88fb ldrh r3, [r7, #6] 8005aa4: 2b00 cmp r3, #0 8005aa6: d101 bne.n 8005aac { return HAL_ERROR; 8005aa8: 2301 movs r3, #1 8005aaa: e06e b.n 8005b8a } huart->ErrorCode = HAL_UART_ERROR_NONE; 8005aac: 68fb ldr r3, [r7, #12] 8005aae: 2200 movs r2, #0 8005ab0: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8005ab2: 68fb ldr r3, [r7, #12] 8005ab4: 2221 movs r2, #33 @ 0x21 8005ab6: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8005aba: f7fb ff85 bl 80019c8 8005abe: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8005ac0: 68fb ldr r3, [r7, #12] 8005ac2: 88fa ldrh r2, [r7, #6] 8005ac4: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8005ac6: 68fb ldr r3, [r7, #12] 8005ac8: 88fa ldrh r2, [r7, #6] 8005aca: 84da strh r2, [r3, #38] @ 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8005acc: 68fb ldr r3, [r7, #12] 8005ace: 689b ldr r3, [r3, #8] 8005ad0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8005ad4: d108 bne.n 8005ae8 8005ad6: 68fb ldr r3, [r7, #12] 8005ad8: 691b ldr r3, [r3, #16] 8005ada: 2b00 cmp r3, #0 8005adc: d104 bne.n 8005ae8 { pdata8bits = NULL; 8005ade: 2300 movs r3, #0 8005ae0: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 8005ae2: 68bb ldr r3, [r7, #8] 8005ae4: 61bb str r3, [r7, #24] 8005ae6: e003 b.n 8005af0 } else { pdata8bits = pData; 8005ae8: 68bb ldr r3, [r7, #8] 8005aea: 61fb str r3, [r7, #28] pdata16bits = NULL; 8005aec: 2300 movs r3, #0 8005aee: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 8005af0: e02e b.n 8005b50 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8005af2: 683b ldr r3, [r7, #0] 8005af4: 9300 str r3, [sp, #0] 8005af6: 697b ldr r3, [r7, #20] 8005af8: 2200 movs r2, #0 8005afa: 2180 movs r1, #128 @ 0x80 8005afc: 68f8 ldr r0, [r7, #12] 8005afe: f000 fd22 bl 8006546 8005b02: 4603 mov r3, r0 8005b04: 2b00 cmp r3, #0 8005b06: d005 beq.n 8005b14 { huart->gState = HAL_UART_STATE_READY; 8005b08: 68fb ldr r3, [r7, #12] 8005b0a: 2220 movs r2, #32 8005b0c: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 8005b10: 2303 movs r3, #3 8005b12: e03a b.n 8005b8a } if (pdata8bits == NULL) 8005b14: 69fb ldr r3, [r7, #28] 8005b16: 2b00 cmp r3, #0 8005b18: d10b bne.n 8005b32 { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 8005b1a: 69bb ldr r3, [r7, #24] 8005b1c: 881b ldrh r3, [r3, #0] 8005b1e: 461a mov r2, r3 8005b20: 68fb ldr r3, [r7, #12] 8005b22: 681b ldr r3, [r3, #0] 8005b24: f3c2 0208 ubfx r2, r2, #0, #9 8005b28: 605a str r2, [r3, #4] pdata16bits++; 8005b2a: 69bb ldr r3, [r7, #24] 8005b2c: 3302 adds r3, #2 8005b2e: 61bb str r3, [r7, #24] 8005b30: e007 b.n 8005b42 } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 8005b32: 69fb ldr r3, [r7, #28] 8005b34: 781a ldrb r2, [r3, #0] 8005b36: 68fb ldr r3, [r7, #12] 8005b38: 681b ldr r3, [r3, #0] 8005b3a: 605a str r2, [r3, #4] pdata8bits++; 8005b3c: 69fb ldr r3, [r7, #28] 8005b3e: 3301 adds r3, #1 8005b40: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8005b42: 68fb ldr r3, [r7, #12] 8005b44: 8cdb ldrh r3, [r3, #38] @ 0x26 8005b46: b29b uxth r3, r3 8005b48: 3b01 subs r3, #1 8005b4a: b29a uxth r2, r3 8005b4c: 68fb ldr r3, [r7, #12] 8005b4e: 84da strh r2, [r3, #38] @ 0x26 while (huart->TxXferCount > 0U) 8005b50: 68fb ldr r3, [r7, #12] 8005b52: 8cdb ldrh r3, [r3, #38] @ 0x26 8005b54: b29b uxth r3, r3 8005b56: 2b00 cmp r3, #0 8005b58: d1cb bne.n 8005af2 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8005b5a: 683b ldr r3, [r7, #0] 8005b5c: 9300 str r3, [sp, #0] 8005b5e: 697b ldr r3, [r7, #20] 8005b60: 2200 movs r2, #0 8005b62: 2140 movs r1, #64 @ 0x40 8005b64: 68f8 ldr r0, [r7, #12] 8005b66: f000 fcee bl 8006546 8005b6a: 4603 mov r3, r0 8005b6c: 2b00 cmp r3, #0 8005b6e: d005 beq.n 8005b7c { huart->gState = HAL_UART_STATE_READY; 8005b70: 68fb ldr r3, [r7, #12] 8005b72: 2220 movs r2, #32 8005b74: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_TIMEOUT; 8005b78: 2303 movs r3, #3 8005b7a: e006 b.n 8005b8a } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8005b7c: 68fb ldr r3, [r7, #12] 8005b7e: 2220 movs r2, #32 8005b80: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_OK; 8005b84: 2300 movs r3, #0 8005b86: e000 b.n 8005b8a } else { return HAL_BUSY; 8005b88: 2302 movs r3, #2 } } 8005b8a: 4618 mov r0, r3 8005b8c: 3720 adds r7, #32 8005b8e: 46bd mov sp, r7 8005b90: bd80 pop {r7, pc} ... 08005b94 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8005b94: b580 push {r7, lr} 8005b96: b08c sub sp, #48 @ 0x30 8005b98: af00 add r7, sp, #0 8005b9a: 60f8 str r0, [r7, #12] 8005b9c: 60b9 str r1, [r7, #8] 8005b9e: 4613 mov r3, r2 8005ba0: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8005ba2: 68fb ldr r3, [r7, #12] 8005ba4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005ba8: b2db uxtb r3, r3 8005baa: 2b20 cmp r3, #32 8005bac: d162 bne.n 8005c74 { if ((pData == NULL) || (Size == 0U)) 8005bae: 68bb ldr r3, [r7, #8] 8005bb0: 2b00 cmp r3, #0 8005bb2: d002 beq.n 8005bba 8005bb4: 88fb ldrh r3, [r7, #6] 8005bb6: 2b00 cmp r3, #0 8005bb8: d101 bne.n 8005bbe { return HAL_ERROR; 8005bba: 2301 movs r3, #1 8005bbc: e05b b.n 8005c76 } huart->pTxBuffPtr = pData; 8005bbe: 68ba ldr r2, [r7, #8] 8005bc0: 68fb ldr r3, [r7, #12] 8005bc2: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8005bc4: 68fb ldr r3, [r7, #12] 8005bc6: 88fa ldrh r2, [r7, #6] 8005bc8: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8005bca: 68fb ldr r3, [r7, #12] 8005bcc: 88fa ldrh r2, [r7, #6] 8005bce: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8005bd0: 68fb ldr r3, [r7, #12] 8005bd2: 2200 movs r2, #0 8005bd4: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8005bd6: 68fb ldr r3, [r7, #12] 8005bd8: 2221 movs r2, #33 @ 0x21 8005bda: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 8005bde: 68fb ldr r3, [r7, #12] 8005be0: 6b9b ldr r3, [r3, #56] @ 0x38 8005be2: 4a27 ldr r2, [pc, #156] @ (8005c80 ) 8005be4: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8005be6: 68fb ldr r3, [r7, #12] 8005be8: 6b9b ldr r3, [r3, #56] @ 0x38 8005bea: 4a26 ldr r2, [pc, #152] @ (8005c84 ) 8005bec: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 8005bee: 68fb ldr r3, [r7, #12] 8005bf0: 6b9b ldr r3, [r3, #56] @ 0x38 8005bf2: 4a25 ldr r2, [pc, #148] @ (8005c88 ) 8005bf4: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8005bf6: 68fb ldr r3, [r7, #12] 8005bf8: 6b9b ldr r3, [r3, #56] @ 0x38 8005bfa: 2200 movs r2, #0 8005bfc: 651a str r2, [r3, #80] @ 0x50 /* Enable the UART transmit DMA stream */ tmp = (const uint32_t *)&pData; 8005bfe: f107 0308 add.w r3, r7, #8 8005c02: 62fb str r3, [r7, #44] @ 0x2c if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK) 8005c04: 68fb ldr r3, [r7, #12] 8005c06: 6b98 ldr r0, [r3, #56] @ 0x38 8005c08: 6afb ldr r3, [r7, #44] @ 0x2c 8005c0a: 6819 ldr r1, [r3, #0] 8005c0c: 68fb ldr r3, [r7, #12] 8005c0e: 681b ldr r3, [r3, #0] 8005c10: 3304 adds r3, #4 8005c12: 461a mov r2, r3 8005c14: 88fb ldrh r3, [r7, #6] 8005c16: f7fc f8c7 bl 8001da8 8005c1a: 4603 mov r3, r0 8005c1c: 2b00 cmp r3, #0 8005c1e: d008 beq.n 8005c32 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8005c20: 68fb ldr r3, [r7, #12] 8005c22: 2210 movs r2, #16 8005c24: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; 8005c26: 68fb ldr r3, [r7, #12] 8005c28: 2220 movs r2, #32 8005c2a: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_ERROR; 8005c2e: 2301 movs r3, #1 8005c30: e021 b.n 8005c76 } /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 8005c32: 68fb ldr r3, [r7, #12] 8005c34: 681b ldr r3, [r3, #0] 8005c36: f06f 0240 mvn.w r2, #64 @ 0x40 8005c3a: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8005c3c: 68fb ldr r3, [r7, #12] 8005c3e: 681b ldr r3, [r3, #0] 8005c40: 3314 adds r3, #20 8005c42: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005c44: 69bb ldr r3, [r7, #24] 8005c46: e853 3f00 ldrex r3, [r3] 8005c4a: 617b str r3, [r7, #20] return(result); 8005c4c: 697b ldr r3, [r7, #20] 8005c4e: f043 0380 orr.w r3, r3, #128 @ 0x80 8005c52: 62bb str r3, [r7, #40] @ 0x28 8005c54: 68fb ldr r3, [r7, #12] 8005c56: 681b ldr r3, [r3, #0] 8005c58: 3314 adds r3, #20 8005c5a: 6aba ldr r2, [r7, #40] @ 0x28 8005c5c: 627a str r2, [r7, #36] @ 0x24 8005c5e: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005c60: 6a39 ldr r1, [r7, #32] 8005c62: 6a7a ldr r2, [r7, #36] @ 0x24 8005c64: e841 2300 strex r3, r2, [r1] 8005c68: 61fb str r3, [r7, #28] return(result); 8005c6a: 69fb ldr r3, [r7, #28] 8005c6c: 2b00 cmp r3, #0 8005c6e: d1e5 bne.n 8005c3c return HAL_OK; 8005c70: 2300 movs r3, #0 8005c72: e000 b.n 8005c76 } else { return HAL_BUSY; 8005c74: 2302 movs r3, #2 } } 8005c76: 4618 mov r0, r3 8005c78: 3730 adds r7, #48 @ 0x30 8005c7a: 46bd mov sp, r7 8005c7c: bd80 pop {r7, pc} 8005c7e: bf00 nop 8005c80: 08006295 .word 0x08006295 8005c84: 0800632f .word 0x0800632f 8005c88: 080064b3 .word 0x080064b3 08005c8c : * @param Size Amount of data elements (u8 or u16) to be received. * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8005c8c: b580 push {r7, lr} 8005c8e: b084 sub sp, #16 8005c90: af00 add r7, sp, #0 8005c92: 60f8 str r0, [r7, #12] 8005c94: 60b9 str r1, [r7, #8] 8005c96: 4613 mov r3, r2 8005c98: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8005c9a: 68fb ldr r3, [r7, #12] 8005c9c: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8005ca0: b2db uxtb r3, r3 8005ca2: 2b20 cmp r3, #32 8005ca4: d112 bne.n 8005ccc { if ((pData == NULL) || (Size == 0U)) 8005ca6: 68bb ldr r3, [r7, #8] 8005ca8: 2b00 cmp r3, #0 8005caa: d002 beq.n 8005cb2 8005cac: 88fb ldrh r3, [r7, #6] 8005cae: 2b00 cmp r3, #0 8005cb0: d101 bne.n 8005cb6 { return HAL_ERROR; 8005cb2: 2301 movs r3, #1 8005cb4: e00b b.n 8005cce } /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005cb6: 68fb ldr r3, [r7, #12] 8005cb8: 2200 movs r2, #0 8005cba: 631a str r2, [r3, #48] @ 0x30 return (UART_Start_Receive_DMA(huart, pData, Size)); 8005cbc: 88fb ldrh r3, [r7, #6] 8005cbe: 461a mov r2, r3 8005cc0: 68b9 ldr r1, [r7, #8] 8005cc2: 68f8 ldr r0, [r7, #12] 8005cc4: f000 fc98 bl 80065f8 8005cc8: 4603 mov r3, r0 8005cca: e000 b.n 8005cce } else { return HAL_BUSY; 8005ccc: 2302 movs r3, #2 } } 8005cce: 4618 mov r0, r3 8005cd0: 3710 adds r7, #16 8005cd2: 46bd mov sp, r7 8005cd4: bd80 pop {r7, pc} ... 08005cd8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8005cd8: b580 push {r7, lr} 8005cda: b0ba sub sp, #232 @ 0xe8 8005cdc: af00 add r7, sp, #0 8005cde: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8005ce0: 687b ldr r3, [r7, #4] 8005ce2: 681b ldr r3, [r3, #0] 8005ce4: 681b ldr r3, [r3, #0] 8005ce6: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8005cea: 687b ldr r3, [r7, #4] 8005cec: 681b ldr r3, [r3, #0] 8005cee: 68db ldr r3, [r3, #12] 8005cf0: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8005cf4: 687b ldr r3, [r7, #4] 8005cf6: 681b ldr r3, [r3, #0] 8005cf8: 695b ldr r3, [r3, #20] 8005cfa: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8005cfe: 2300 movs r3, #0 8005d00: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8005d04: 2300 movs r3, #0 8005d06: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8005d0a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005d0e: f003 030f and.w r3, r3, #15 8005d12: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8005d16: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8005d1a: 2b00 cmp r3, #0 8005d1c: d10f bne.n 8005d3e { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005d1e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005d22: f003 0320 and.w r3, r3, #32 8005d26: 2b00 cmp r3, #0 8005d28: d009 beq.n 8005d3e 8005d2a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005d2e: f003 0320 and.w r3, r3, #32 8005d32: 2b00 cmp r3, #0 8005d34: d003 beq.n 8005d3e { UART_Receive_IT(huart); 8005d36: 6878 ldr r0, [r7, #4] 8005d38: f000 fe08 bl 800694c return; 8005d3c: e273 b.n 8006226 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8005d3e: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8005d42: 2b00 cmp r3, #0 8005d44: f000 80de beq.w 8005f04 8005d48: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005d4c: f003 0301 and.w r3, r3, #1 8005d50: 2b00 cmp r3, #0 8005d52: d106 bne.n 8005d62 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8005d54: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005d58: f403 7390 and.w r3, r3, #288 @ 0x120 8005d5c: 2b00 cmp r3, #0 8005d5e: f000 80d1 beq.w 8005f04 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8005d62: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005d66: f003 0301 and.w r3, r3, #1 8005d6a: 2b00 cmp r3, #0 8005d6c: d00b beq.n 8005d86 8005d6e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005d72: f403 7380 and.w r3, r3, #256 @ 0x100 8005d76: 2b00 cmp r3, #0 8005d78: d005 beq.n 8005d86 { huart->ErrorCode |= HAL_UART_ERROR_PE; 8005d7a: 687b ldr r3, [r7, #4] 8005d7c: 6c5b ldr r3, [r3, #68] @ 0x44 8005d7e: f043 0201 orr.w r2, r3, #1 8005d82: 687b ldr r3, [r7, #4] 8005d84: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005d86: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005d8a: f003 0304 and.w r3, r3, #4 8005d8e: 2b00 cmp r3, #0 8005d90: d00b beq.n 8005daa 8005d92: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005d96: f003 0301 and.w r3, r3, #1 8005d9a: 2b00 cmp r3, #0 8005d9c: d005 beq.n 8005daa { huart->ErrorCode |= HAL_UART_ERROR_NE; 8005d9e: 687b ldr r3, [r7, #4] 8005da0: 6c5b ldr r3, [r3, #68] @ 0x44 8005da2: f043 0202 orr.w r2, r3, #2 8005da6: 687b ldr r3, [r7, #4] 8005da8: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005daa: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005dae: f003 0302 and.w r3, r3, #2 8005db2: 2b00 cmp r3, #0 8005db4: d00b beq.n 8005dce 8005db6: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005dba: f003 0301 and.w r3, r3, #1 8005dbe: 2b00 cmp r3, #0 8005dc0: d005 beq.n 8005dce { huart->ErrorCode |= HAL_UART_ERROR_FE; 8005dc2: 687b ldr r3, [r7, #4] 8005dc4: 6c5b ldr r3, [r3, #68] @ 0x44 8005dc6: f043 0204 orr.w r2, r3, #4 8005dca: 687b ldr r3, [r7, #4] 8005dcc: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8005dce: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005dd2: f003 0308 and.w r3, r3, #8 8005dd6: 2b00 cmp r3, #0 8005dd8: d011 beq.n 8005dfe 8005dda: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005dde: f003 0320 and.w r3, r3, #32 8005de2: 2b00 cmp r3, #0 8005de4: d105 bne.n 8005df2 || ((cr3its & USART_CR3_EIE) != RESET))) 8005de6: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005dea: f003 0301 and.w r3, r3, #1 8005dee: 2b00 cmp r3, #0 8005df0: d005 beq.n 8005dfe { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8005df2: 687b ldr r3, [r7, #4] 8005df4: 6c5b ldr r3, [r3, #68] @ 0x44 8005df6: f043 0208 orr.w r2, r3, #8 8005dfa: 687b ldr r3, [r7, #4] 8005dfc: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8005dfe: 687b ldr r3, [r7, #4] 8005e00: 6c5b ldr r3, [r3, #68] @ 0x44 8005e02: 2b00 cmp r3, #0 8005e04: f000 820a beq.w 800621c { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005e08: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005e0c: f003 0320 and.w r3, r3, #32 8005e10: 2b00 cmp r3, #0 8005e12: d008 beq.n 8005e26 8005e14: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005e18: f003 0320 and.w r3, r3, #32 8005e1c: 2b00 cmp r3, #0 8005e1e: d002 beq.n 8005e26 { UART_Receive_IT(huart); 8005e20: 6878 ldr r0, [r7, #4] 8005e22: f000 fd93 bl 800694c } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8005e26: 687b ldr r3, [r7, #4] 8005e28: 681b ldr r3, [r3, #0] 8005e2a: 695b ldr r3, [r3, #20] 8005e2c: f003 0340 and.w r3, r3, #64 @ 0x40 8005e30: 2b40 cmp r3, #64 @ 0x40 8005e32: bf0c ite eq 8005e34: 2301 moveq r3, #1 8005e36: 2300 movne r3, #0 8005e38: b2db uxtb r3, r3 8005e3a: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8005e3e: 687b ldr r3, [r7, #4] 8005e40: 6c5b ldr r3, [r3, #68] @ 0x44 8005e42: f003 0308 and.w r3, r3, #8 8005e46: 2b00 cmp r3, #0 8005e48: d103 bne.n 8005e52 8005e4a: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8005e4e: 2b00 cmp r3, #0 8005e50: d04f beq.n 8005ef2 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8005e52: 6878 ldr r0, [r7, #4] 8005e54: f000 fc9e bl 8006794 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005e58: 687b ldr r3, [r7, #4] 8005e5a: 681b ldr r3, [r3, #0] 8005e5c: 695b ldr r3, [r3, #20] 8005e5e: f003 0340 and.w r3, r3, #64 @ 0x40 8005e62: 2b40 cmp r3, #64 @ 0x40 8005e64: d141 bne.n 8005eea { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005e66: 687b ldr r3, [r7, #4] 8005e68: 681b ldr r3, [r3, #0] 8005e6a: 3314 adds r3, #20 8005e6c: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005e70: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8005e74: e853 3f00 ldrex r3, [r3] 8005e78: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8005e7c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8005e80: f023 0340 bic.w r3, r3, #64 @ 0x40 8005e84: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8005e88: 687b ldr r3, [r7, #4] 8005e8a: 681b ldr r3, [r3, #0] 8005e8c: 3314 adds r3, #20 8005e8e: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8005e92: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8005e96: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005e9a: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8005e9e: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8005ea2: e841 2300 strex r3, r2, [r1] 8005ea6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8005eaa: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8005eae: 2b00 cmp r3, #0 8005eb0: d1d9 bne.n 8005e66 /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) 8005eb2: 687b ldr r3, [r7, #4] 8005eb4: 6bdb ldr r3, [r3, #60] @ 0x3c 8005eb6: 2b00 cmp r3, #0 8005eb8: d013 beq.n 8005ee2 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8005eba: 687b ldr r3, [r7, #4] 8005ebc: 6bdb ldr r3, [r3, #60] @ 0x3c 8005ebe: 4a8a ldr r2, [pc, #552] @ (80060e8 ) 8005ec0: 651a str r2, [r3, #80] @ 0x50 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8005ec2: 687b ldr r3, [r7, #4] 8005ec4: 6bdb ldr r3, [r3, #60] @ 0x3c 8005ec6: 4618 mov r0, r3 8005ec8: f7fc f836 bl 8001f38 8005ecc: 4603 mov r3, r0 8005ece: 2b00 cmp r3, #0 8005ed0: d016 beq.n 8005f00 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8005ed2: 687b ldr r3, [r7, #4] 8005ed4: 6bdb ldr r3, [r3, #60] @ 0x3c 8005ed6: 6d1b ldr r3, [r3, #80] @ 0x50 8005ed8: 687a ldr r2, [r7, #4] 8005eda: 6bd2 ldr r2, [r2, #60] @ 0x3c 8005edc: 4610 mov r0, r2 8005ede: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005ee0: e00e b.n 8005f00 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005ee2: 6878 ldr r0, [r7, #4] 8005ee4: f000 f9c0 bl 8006268 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005ee8: e00a b.n 8005f00 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005eea: 6878 ldr r0, [r7, #4] 8005eec: f000 f9bc bl 8006268 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005ef0: e006 b.n 8005f00 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005ef2: 6878 ldr r0, [r7, #4] 8005ef4: f000 f9b8 bl 8006268 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005ef8: 687b ldr r3, [r7, #4] 8005efa: 2200 movs r2, #0 8005efc: 645a str r2, [r3, #68] @ 0x44 } } return; 8005efe: e18d b.n 800621c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005f00: bf00 nop return; 8005f02: e18b b.n 800621c } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005f04: 687b ldr r3, [r7, #4] 8005f06: 6b1b ldr r3, [r3, #48] @ 0x30 8005f08: 2b01 cmp r3, #1 8005f0a: f040 8167 bne.w 80061dc && ((isrflags & USART_SR_IDLE) != 0U) 8005f0e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005f12: f003 0310 and.w r3, r3, #16 8005f16: 2b00 cmp r3, #0 8005f18: f000 8160 beq.w 80061dc && ((cr1its & USART_CR1_IDLEIE) != 0U)) 8005f1c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005f20: f003 0310 and.w r3, r3, #16 8005f24: 2b00 cmp r3, #0 8005f26: f000 8159 beq.w 80061dc { __HAL_UART_CLEAR_IDLEFLAG(huart); 8005f2a: 2300 movs r3, #0 8005f2c: 60bb str r3, [r7, #8] 8005f2e: 687b ldr r3, [r7, #4] 8005f30: 681b ldr r3, [r3, #0] 8005f32: 681b ldr r3, [r3, #0] 8005f34: 60bb str r3, [r7, #8] 8005f36: 687b ldr r3, [r7, #4] 8005f38: 681b ldr r3, [r3, #0] 8005f3a: 685b ldr r3, [r3, #4] 8005f3c: 60bb str r3, [r7, #8] 8005f3e: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005f40: 687b ldr r3, [r7, #4] 8005f42: 681b ldr r3, [r3, #0] 8005f44: 695b ldr r3, [r3, #20] 8005f46: f003 0340 and.w r3, r3, #64 @ 0x40 8005f4a: 2b40 cmp r3, #64 @ 0x40 8005f4c: f040 80ce bne.w 80060ec { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8005f50: 687b ldr r3, [r7, #4] 8005f52: 6bdb ldr r3, [r3, #60] @ 0x3c 8005f54: 681b ldr r3, [r3, #0] 8005f56: 685b ldr r3, [r3, #4] 8005f58: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8005f5c: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8005f60: 2b00 cmp r3, #0 8005f62: f000 80a9 beq.w 80060b8 && (nb_remaining_rx_data < huart->RxXferSize)) 8005f66: 687b ldr r3, [r7, #4] 8005f68: 8d9b ldrh r3, [r3, #44] @ 0x2c 8005f6a: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005f6e: 429a cmp r2, r3 8005f70: f080 80a2 bcs.w 80060b8 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8005f74: 687b ldr r3, [r7, #4] 8005f76: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005f7a: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8005f7c: 687b ldr r3, [r7, #4] 8005f7e: 6bdb ldr r3, [r3, #60] @ 0x3c 8005f80: 69db ldr r3, [r3, #28] 8005f82: f5b3 7f80 cmp.w r3, #256 @ 0x100 8005f86: f000 8088 beq.w 800609a { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8005f8a: 687b ldr r3, [r7, #4] 8005f8c: 681b ldr r3, [r3, #0] 8005f8e: 330c adds r3, #12 8005f90: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005f94: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8005f98: e853 3f00 ldrex r3, [r3] 8005f9c: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8005fa0: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8005fa4: f423 7380 bic.w r3, r3, #256 @ 0x100 8005fa8: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8005fac: 687b ldr r3, [r7, #4] 8005fae: 681b ldr r3, [r3, #0] 8005fb0: 330c adds r3, #12 8005fb2: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8005fb6: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8005fba: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005fbe: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8005fc2: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8005fc6: e841 2300 strex r3, r2, [r1] 8005fca: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8005fce: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005fd2: 2b00 cmp r3, #0 8005fd4: d1d9 bne.n 8005f8a ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005fd6: 687b ldr r3, [r7, #4] 8005fd8: 681b ldr r3, [r3, #0] 8005fda: 3314 adds r3, #20 8005fdc: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005fde: 6f7b ldr r3, [r7, #116] @ 0x74 8005fe0: e853 3f00 ldrex r3, [r3] 8005fe4: 673b str r3, [r7, #112] @ 0x70 return(result); 8005fe6: 6f3b ldr r3, [r7, #112] @ 0x70 8005fe8: f023 0301 bic.w r3, r3, #1 8005fec: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8005ff0: 687b ldr r3, [r7, #4] 8005ff2: 681b ldr r3, [r3, #0] 8005ff4: 3314 adds r3, #20 8005ff6: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8005ffa: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8005ffe: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006000: 6ff9 ldr r1, [r7, #124] @ 0x7c 8006002: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8006006: e841 2300 strex r3, r2, [r1] 800600a: 67bb str r3, [r7, #120] @ 0x78 return(result); 800600c: 6fbb ldr r3, [r7, #120] @ 0x78 800600e: 2b00 cmp r3, #0 8006010: d1e1 bne.n 8005fd6 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8006012: 687b ldr r3, [r7, #4] 8006014: 681b ldr r3, [r3, #0] 8006016: 3314 adds r3, #20 8006018: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800601a: 6e3b ldr r3, [r7, #96] @ 0x60 800601c: e853 3f00 ldrex r3, [r3] 8006020: 65fb str r3, [r7, #92] @ 0x5c return(result); 8006022: 6dfb ldr r3, [r7, #92] @ 0x5c 8006024: f023 0340 bic.w r3, r3, #64 @ 0x40 8006028: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 800602c: 687b ldr r3, [r7, #4] 800602e: 681b ldr r3, [r3, #0] 8006030: 3314 adds r3, #20 8006032: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8006036: 66fa str r2, [r7, #108] @ 0x6c 8006038: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800603a: 6eb9 ldr r1, [r7, #104] @ 0x68 800603c: 6efa ldr r2, [r7, #108] @ 0x6c 800603e: e841 2300 strex r3, r2, [r1] 8006042: 667b str r3, [r7, #100] @ 0x64 return(result); 8006044: 6e7b ldr r3, [r7, #100] @ 0x64 8006046: 2b00 cmp r3, #0 8006048: d1e3 bne.n 8006012 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800604a: 687b ldr r3, [r7, #4] 800604c: 2220 movs r2, #32 800604e: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006052: 687b ldr r3, [r7, #4] 8006054: 2200 movs r2, #0 8006056: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006058: 687b ldr r3, [r7, #4] 800605a: 681b ldr r3, [r3, #0] 800605c: 330c adds r3, #12 800605e: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006060: 6cfb ldr r3, [r7, #76] @ 0x4c 8006062: e853 3f00 ldrex r3, [r3] 8006066: 64bb str r3, [r7, #72] @ 0x48 return(result); 8006068: 6cbb ldr r3, [r7, #72] @ 0x48 800606a: f023 0310 bic.w r3, r3, #16 800606e: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8006072: 687b ldr r3, [r7, #4] 8006074: 681b ldr r3, [r3, #0] 8006076: 330c adds r3, #12 8006078: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 800607c: 65ba str r2, [r7, #88] @ 0x58 800607e: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006080: 6d79 ldr r1, [r7, #84] @ 0x54 8006082: 6dba ldr r2, [r7, #88] @ 0x58 8006084: e841 2300 strex r3, r2, [r1] 8006088: 653b str r3, [r7, #80] @ 0x50 return(result); 800608a: 6d3b ldr r3, [r7, #80] @ 0x50 800608c: 2b00 cmp r3, #0 800608e: d1e3 bne.n 8006058 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8006090: 687b ldr r3, [r7, #4] 8006092: 6bdb ldr r3, [r3, #60] @ 0x3c 8006094: 4618 mov r0, r3 8006096: f7fb fedf bl 8001e58 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800609a: 687b ldr r3, [r7, #4] 800609c: 2202 movs r2, #2 800609e: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 80060a0: 687b ldr r3, [r7, #4] 80060a2: 8d9a ldrh r2, [r3, #44] @ 0x2c 80060a4: 687b ldr r3, [r7, #4] 80060a6: 8ddb ldrh r3, [r3, #46] @ 0x2e 80060a8: b29b uxth r3, r3 80060aa: 1ad3 subs r3, r2, r3 80060ac: b29b uxth r3, r3 80060ae: 4619 mov r1, r3 80060b0: 6878 ldr r0, [r7, #4] 80060b2: f000 f8e3 bl 800627c HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 80060b6: e0b3 b.n 8006220 if (nb_remaining_rx_data == huart->RxXferSize) 80060b8: 687b ldr r3, [r7, #4] 80060ba: 8d9b ldrh r3, [r3, #44] @ 0x2c 80060bc: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80060c0: 429a cmp r2, r3 80060c2: f040 80ad bne.w 8006220 if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) 80060c6: 687b ldr r3, [r7, #4] 80060c8: 6bdb ldr r3, [r3, #60] @ 0x3c 80060ca: 69db ldr r3, [r3, #28] 80060cc: f5b3 7f80 cmp.w r3, #256 @ 0x100 80060d0: f040 80a6 bne.w 8006220 huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80060d4: 687b ldr r3, [r7, #4] 80060d6: 2202 movs r2, #2 80060d8: 635a str r2, [r3, #52] @ 0x34 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80060da: 687b ldr r3, [r7, #4] 80060dc: 8d9b ldrh r3, [r3, #44] @ 0x2c 80060de: 4619 mov r1, r3 80060e0: 6878 ldr r0, [r7, #4] 80060e2: f000 f8cb bl 800627c return; 80060e6: e09b b.n 8006220 80060e8: 0800685b .word 0x0800685b else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 80060ec: 687b ldr r3, [r7, #4] 80060ee: 8d9a ldrh r2, [r3, #44] @ 0x2c 80060f0: 687b ldr r3, [r7, #4] 80060f2: 8ddb ldrh r3, [r3, #46] @ 0x2e 80060f4: b29b uxth r3, r3 80060f6: 1ad3 subs r3, r2, r3 80060f8: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 80060fc: 687b ldr r3, [r7, #4] 80060fe: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006100: b29b uxth r3, r3 8006102: 2b00 cmp r3, #0 8006104: f000 808e beq.w 8006224 && (nb_rx_data > 0U)) 8006108: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 800610c: 2b00 cmp r3, #0 800610e: f000 8089 beq.w 8006224 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8006112: 687b ldr r3, [r7, #4] 8006114: 681b ldr r3, [r3, #0] 8006116: 330c adds r3, #12 8006118: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800611a: 6bbb ldr r3, [r7, #56] @ 0x38 800611c: e853 3f00 ldrex r3, [r3] 8006120: 637b str r3, [r7, #52] @ 0x34 return(result); 8006122: 6b7b ldr r3, [r7, #52] @ 0x34 8006124: f423 7390 bic.w r3, r3, #288 @ 0x120 8006128: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800612c: 687b ldr r3, [r7, #4] 800612e: 681b ldr r3, [r3, #0] 8006130: 330c adds r3, #12 8006132: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 8006136: 647a str r2, [r7, #68] @ 0x44 8006138: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800613a: 6c39 ldr r1, [r7, #64] @ 0x40 800613c: 6c7a ldr r2, [r7, #68] @ 0x44 800613e: e841 2300 strex r3, r2, [r1] 8006142: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006144: 6bfb ldr r3, [r7, #60] @ 0x3c 8006146: 2b00 cmp r3, #0 8006148: d1e3 bne.n 8006112 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800614a: 687b ldr r3, [r7, #4] 800614c: 681b ldr r3, [r3, #0] 800614e: 3314 adds r3, #20 8006150: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006152: 6a7b ldr r3, [r7, #36] @ 0x24 8006154: e853 3f00 ldrex r3, [r3] 8006158: 623b str r3, [r7, #32] return(result); 800615a: 6a3b ldr r3, [r7, #32] 800615c: f023 0301 bic.w r3, r3, #1 8006160: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8006164: 687b ldr r3, [r7, #4] 8006166: 681b ldr r3, [r3, #0] 8006168: 3314 adds r3, #20 800616a: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 800616e: 633a str r2, [r7, #48] @ 0x30 8006170: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006172: 6af9 ldr r1, [r7, #44] @ 0x2c 8006174: 6b3a ldr r2, [r7, #48] @ 0x30 8006176: e841 2300 strex r3, r2, [r1] 800617a: 62bb str r3, [r7, #40] @ 0x28 return(result); 800617c: 6abb ldr r3, [r7, #40] @ 0x28 800617e: 2b00 cmp r3, #0 8006180: d1e3 bne.n 800614a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006182: 687b ldr r3, [r7, #4] 8006184: 2220 movs r2, #32 8006186: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800618a: 687b ldr r3, [r7, #4] 800618c: 2200 movs r2, #0 800618e: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006190: 687b ldr r3, [r7, #4] 8006192: 681b ldr r3, [r3, #0] 8006194: 330c adds r3, #12 8006196: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006198: 693b ldr r3, [r7, #16] 800619a: e853 3f00 ldrex r3, [r3] 800619e: 60fb str r3, [r7, #12] return(result); 80061a0: 68fb ldr r3, [r7, #12] 80061a2: f023 0310 bic.w r3, r3, #16 80061a6: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 80061aa: 687b ldr r3, [r7, #4] 80061ac: 681b ldr r3, [r3, #0] 80061ae: 330c adds r3, #12 80061b0: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 80061b4: 61fa str r2, [r7, #28] 80061b6: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80061b8: 69b9 ldr r1, [r7, #24] 80061ba: 69fa ldr r2, [r7, #28] 80061bc: e841 2300 strex r3, r2, [r1] 80061c0: 617b str r3, [r7, #20] return(result); 80061c2: 697b ldr r3, [r7, #20] 80061c4: 2b00 cmp r3, #0 80061c6: d1e3 bne.n 8006190 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80061c8: 687b ldr r3, [r7, #4] 80061ca: 2202 movs r2, #2 80061cc: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 80061ce: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 80061d2: 4619 mov r1, r3 80061d4: 6878 ldr r0, [r7, #4] 80061d6: f000 f851 bl 800627c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 80061da: e023 b.n 8006224 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 80061dc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80061e0: f003 0380 and.w r3, r3, #128 @ 0x80 80061e4: 2b00 cmp r3, #0 80061e6: d009 beq.n 80061fc 80061e8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80061ec: f003 0380 and.w r3, r3, #128 @ 0x80 80061f0: 2b00 cmp r3, #0 80061f2: d003 beq.n 80061fc { UART_Transmit_IT(huart); 80061f4: 6878 ldr r0, [r7, #4] 80061f6: f000 fb41 bl 800687c return; 80061fa: e014 b.n 8006226 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 80061fc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006200: f003 0340 and.w r3, r3, #64 @ 0x40 8006204: 2b00 cmp r3, #0 8006206: d00e beq.n 8006226 8006208: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800620c: f003 0340 and.w r3, r3, #64 @ 0x40 8006210: 2b00 cmp r3, #0 8006212: d008 beq.n 8006226 { UART_EndTransmit_IT(huart); 8006214: 6878 ldr r0, [r7, #4] 8006216: f000 fb81 bl 800691c return; 800621a: e004 b.n 8006226 return; 800621c: bf00 nop 800621e: e002 b.n 8006226 return; 8006220: bf00 nop 8006222: e000 b.n 8006226 return; 8006224: bf00 nop } } 8006226: 37e8 adds r7, #232 @ 0xe8 8006228: 46bd mov sp, r7 800622a: bd80 pop {r7, pc} 0800622c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 800622c: b480 push {r7} 800622e: b083 sub sp, #12 8006230: af00 add r7, sp, #0 8006232: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8006234: bf00 nop 8006236: 370c adds r7, #12 8006238: 46bd mov sp, r7 800623a: f85d 7b04 ldr.w r7, [sp], #4 800623e: 4770 bx lr 08006240 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8006240: b480 push {r7} 8006242: b083 sub sp, #12 8006244: af00 add r7, sp, #0 8006246: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 8006248: bf00 nop 800624a: 370c adds r7, #12 800624c: 46bd mov sp, r7 800624e: f85d 7b04 ldr.w r7, [sp], #4 8006252: 4770 bx lr 08006254 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8006254: b480 push {r7} 8006256: b083 sub sp, #12 8006258: af00 add r7, sp, #0 800625a: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 800625c: bf00 nop 800625e: 370c adds r7, #12 8006260: 46bd mov sp, r7 8006262: f85d 7b04 ldr.w r7, [sp], #4 8006266: 4770 bx lr 08006268 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8006268: b480 push {r7} 800626a: b083 sub sp, #12 800626c: af00 add r7, sp, #0 800626e: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 8006270: bf00 nop 8006272: 370c adds r7, #12 8006274: 46bd mov sp, r7 8006276: f85d 7b04 ldr.w r7, [sp], #4 800627a: 4770 bx lr 0800627c : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 800627c: b480 push {r7} 800627e: b083 sub sp, #12 8006280: af00 add r7, sp, #0 8006282: 6078 str r0, [r7, #4] 8006284: 460b mov r3, r1 8006286: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 8006288: bf00 nop 800628a: 370c adds r7, #12 800628c: 46bd mov sp, r7 800628e: f85d 7b04 ldr.w r7, [sp], #4 8006292: 4770 bx lr 08006294 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 8006294: b580 push {r7, lr} 8006296: b090 sub sp, #64 @ 0x40 8006298: af00 add r7, sp, #0 800629a: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800629c: 687b ldr r3, [r7, #4] 800629e: 6b9b ldr r3, [r3, #56] @ 0x38 80062a0: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 80062a2: 687b ldr r3, [r7, #4] 80062a4: 681b ldr r3, [r3, #0] 80062a6: 681b ldr r3, [r3, #0] 80062a8: f403 7380 and.w r3, r3, #256 @ 0x100 80062ac: 2b00 cmp r3, #0 80062ae: d137 bne.n 8006320 { huart->TxXferCount = 0x00U; 80062b0: 6bfb ldr r3, [r7, #60] @ 0x3c 80062b2: 2200 movs r2, #0 80062b4: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 80062b6: 6bfb ldr r3, [r7, #60] @ 0x3c 80062b8: 681b ldr r3, [r3, #0] 80062ba: 3314 adds r3, #20 80062bc: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80062be: 6a7b ldr r3, [r7, #36] @ 0x24 80062c0: e853 3f00 ldrex r3, [r3] 80062c4: 623b str r3, [r7, #32] return(result); 80062c6: 6a3b ldr r3, [r7, #32] 80062c8: f023 0380 bic.w r3, r3, #128 @ 0x80 80062cc: 63bb str r3, [r7, #56] @ 0x38 80062ce: 6bfb ldr r3, [r7, #60] @ 0x3c 80062d0: 681b ldr r3, [r3, #0] 80062d2: 3314 adds r3, #20 80062d4: 6bba ldr r2, [r7, #56] @ 0x38 80062d6: 633a str r2, [r7, #48] @ 0x30 80062d8: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80062da: 6af9 ldr r1, [r7, #44] @ 0x2c 80062dc: 6b3a ldr r2, [r7, #48] @ 0x30 80062de: e841 2300 strex r3, r2, [r1] 80062e2: 62bb str r3, [r7, #40] @ 0x28 return(result); 80062e4: 6abb ldr r3, [r7, #40] @ 0x28 80062e6: 2b00 cmp r3, #0 80062e8: d1e5 bne.n 80062b6 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80062ea: 6bfb ldr r3, [r7, #60] @ 0x3c 80062ec: 681b ldr r3, [r3, #0] 80062ee: 330c adds r3, #12 80062f0: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80062f2: 693b ldr r3, [r7, #16] 80062f4: e853 3f00 ldrex r3, [r3] 80062f8: 60fb str r3, [r7, #12] return(result); 80062fa: 68fb ldr r3, [r7, #12] 80062fc: f043 0340 orr.w r3, r3, #64 @ 0x40 8006300: 637b str r3, [r7, #52] @ 0x34 8006302: 6bfb ldr r3, [r7, #60] @ 0x3c 8006304: 681b ldr r3, [r3, #0] 8006306: 330c adds r3, #12 8006308: 6b7a ldr r2, [r7, #52] @ 0x34 800630a: 61fa str r2, [r7, #28] 800630c: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800630e: 69b9 ldr r1, [r7, #24] 8006310: 69fa ldr r2, [r7, #28] 8006312: e841 2300 strex r3, r2, [r1] 8006316: 617b str r3, [r7, #20] return(result); 8006318: 697b ldr r3, [r7, #20] 800631a: 2b00 cmp r3, #0 800631c: d1e5 bne.n 80062ea #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 800631e: e002 b.n 8006326 HAL_UART_TxCpltCallback(huart); 8006320: 6bf8 ldr r0, [r7, #60] @ 0x3c 8006322: f7ff ff83 bl 800622c } 8006326: bf00 nop 8006328: 3740 adds r7, #64 @ 0x40 800632a: 46bd mov sp, r7 800632c: bd80 pop {r7, pc} 0800632e : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 800632e: b580 push {r7, lr} 8006330: b084 sub sp, #16 8006332: af00 add r7, sp, #0 8006334: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006336: 687b ldr r3, [r7, #4] 8006338: 6b9b ldr r3, [r3, #56] @ 0x38 800633a: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 800633c: 68f8 ldr r0, [r7, #12] 800633e: f7ff ff7f bl 8006240 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006342: bf00 nop 8006344: 3710 adds r7, #16 8006346: 46bd mov sp, r7 8006348: bd80 pop {r7, pc} 0800634a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 800634a: b580 push {r7, lr} 800634c: b09c sub sp, #112 @ 0x70 800634e: af00 add r7, sp, #0 8006350: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006352: 687b ldr r3, [r7, #4] 8006354: 6b9b ldr r3, [r3, #56] @ 0x38 8006356: 66fb str r3, [r7, #108] @ 0x6c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 8006358: 687b ldr r3, [r7, #4] 800635a: 681b ldr r3, [r3, #0] 800635c: 681b ldr r3, [r3, #0] 800635e: f403 7380 and.w r3, r3, #256 @ 0x100 8006362: 2b00 cmp r3, #0 8006364: d172 bne.n 800644c { huart->RxXferCount = 0U; 8006366: 6efb ldr r3, [r7, #108] @ 0x6c 8006368: 2200 movs r2, #0 800636a: 85da strh r2, [r3, #46] @ 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800636c: 6efb ldr r3, [r7, #108] @ 0x6c 800636e: 681b ldr r3, [r3, #0] 8006370: 330c adds r3, #12 8006372: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006374: 6cfb ldr r3, [r7, #76] @ 0x4c 8006376: e853 3f00 ldrex r3, [r3] 800637a: 64bb str r3, [r7, #72] @ 0x48 return(result); 800637c: 6cbb ldr r3, [r7, #72] @ 0x48 800637e: f423 7380 bic.w r3, r3, #256 @ 0x100 8006382: 66bb str r3, [r7, #104] @ 0x68 8006384: 6efb ldr r3, [r7, #108] @ 0x6c 8006386: 681b ldr r3, [r3, #0] 8006388: 330c adds r3, #12 800638a: 6eba ldr r2, [r7, #104] @ 0x68 800638c: 65ba str r2, [r7, #88] @ 0x58 800638e: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006390: 6d79 ldr r1, [r7, #84] @ 0x54 8006392: 6dba ldr r2, [r7, #88] @ 0x58 8006394: e841 2300 strex r3, r2, [r1] 8006398: 653b str r3, [r7, #80] @ 0x50 return(result); 800639a: 6d3b ldr r3, [r7, #80] @ 0x50 800639c: 2b00 cmp r3, #0 800639e: d1e5 bne.n 800636c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80063a0: 6efb ldr r3, [r7, #108] @ 0x6c 80063a2: 681b ldr r3, [r3, #0] 80063a4: 3314 adds r3, #20 80063a6: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80063a8: 6bbb ldr r3, [r7, #56] @ 0x38 80063aa: e853 3f00 ldrex r3, [r3] 80063ae: 637b str r3, [r7, #52] @ 0x34 return(result); 80063b0: 6b7b ldr r3, [r7, #52] @ 0x34 80063b2: f023 0301 bic.w r3, r3, #1 80063b6: 667b str r3, [r7, #100] @ 0x64 80063b8: 6efb ldr r3, [r7, #108] @ 0x6c 80063ba: 681b ldr r3, [r3, #0] 80063bc: 3314 adds r3, #20 80063be: 6e7a ldr r2, [r7, #100] @ 0x64 80063c0: 647a str r2, [r7, #68] @ 0x44 80063c2: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80063c4: 6c39 ldr r1, [r7, #64] @ 0x40 80063c6: 6c7a ldr r2, [r7, #68] @ 0x44 80063c8: e841 2300 strex r3, r2, [r1] 80063cc: 63fb str r3, [r7, #60] @ 0x3c return(result); 80063ce: 6bfb ldr r3, [r7, #60] @ 0x3c 80063d0: 2b00 cmp r3, #0 80063d2: d1e5 bne.n 80063a0 /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80063d4: 6efb ldr r3, [r7, #108] @ 0x6c 80063d6: 681b ldr r3, [r3, #0] 80063d8: 3314 adds r3, #20 80063da: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80063dc: 6a7b ldr r3, [r7, #36] @ 0x24 80063de: e853 3f00 ldrex r3, [r3] 80063e2: 623b str r3, [r7, #32] return(result); 80063e4: 6a3b ldr r3, [r7, #32] 80063e6: f023 0340 bic.w r3, r3, #64 @ 0x40 80063ea: 663b str r3, [r7, #96] @ 0x60 80063ec: 6efb ldr r3, [r7, #108] @ 0x6c 80063ee: 681b ldr r3, [r3, #0] 80063f0: 3314 adds r3, #20 80063f2: 6e3a ldr r2, [r7, #96] @ 0x60 80063f4: 633a str r2, [r7, #48] @ 0x30 80063f6: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80063f8: 6af9 ldr r1, [r7, #44] @ 0x2c 80063fa: 6b3a ldr r2, [r7, #48] @ 0x30 80063fc: e841 2300 strex r3, r2, [r1] 8006400: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006402: 6abb ldr r3, [r7, #40] @ 0x28 8006404: 2b00 cmp r3, #0 8006406: d1e5 bne.n 80063d4 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006408: 6efb ldr r3, [r7, #108] @ 0x6c 800640a: 2220 movs r2, #32 800640c: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006410: 6efb ldr r3, [r7, #108] @ 0x6c 8006412: 6b1b ldr r3, [r3, #48] @ 0x30 8006414: 2b01 cmp r3, #1 8006416: d119 bne.n 800644c { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006418: 6efb ldr r3, [r7, #108] @ 0x6c 800641a: 681b ldr r3, [r3, #0] 800641c: 330c adds r3, #12 800641e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006420: 693b ldr r3, [r7, #16] 8006422: e853 3f00 ldrex r3, [r3] 8006426: 60fb str r3, [r7, #12] return(result); 8006428: 68fb ldr r3, [r7, #12] 800642a: f023 0310 bic.w r3, r3, #16 800642e: 65fb str r3, [r7, #92] @ 0x5c 8006430: 6efb ldr r3, [r7, #108] @ 0x6c 8006432: 681b ldr r3, [r3, #0] 8006434: 330c adds r3, #12 8006436: 6dfa ldr r2, [r7, #92] @ 0x5c 8006438: 61fa str r2, [r7, #28] 800643a: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800643c: 69b9 ldr r1, [r7, #24] 800643e: 69fa ldr r2, [r7, #28] 8006440: e841 2300 strex r3, r2, [r1] 8006444: 617b str r3, [r7, #20] return(result); 8006446: 697b ldr r3, [r7, #20] 8006448: 2b00 cmp r3, #0 800644a: d1e5 bne.n 8006418 } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 800644c: 6efb ldr r3, [r7, #108] @ 0x6c 800644e: 2200 movs r2, #0 8006450: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006452: 6efb ldr r3, [r7, #108] @ 0x6c 8006454: 6b1b ldr r3, [r3, #48] @ 0x30 8006456: 2b01 cmp r3, #1 8006458: d106 bne.n 8006468 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800645a: 6efb ldr r3, [r7, #108] @ 0x6c 800645c: 8d9b ldrh r3, [r3, #44] @ 0x2c 800645e: 4619 mov r1, r3 8006460: 6ef8 ldr r0, [r7, #108] @ 0x6c 8006462: f7ff ff0b bl 800627c #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8006466: e002 b.n 800646e HAL_UART_RxCpltCallback(huart); 8006468: 6ef8 ldr r0, [r7, #108] @ 0x6c 800646a: f7fa fae7 bl 8000a3c } 800646e: bf00 nop 8006470: 3770 adds r7, #112 @ 0x70 8006472: 46bd mov sp, r7 8006474: bd80 pop {r7, pc} 08006476 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 8006476: b580 push {r7, lr} 8006478: b084 sub sp, #16 800647a: af00 add r7, sp, #0 800647c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800647e: 687b ldr r3, [r7, #4] 8006480: 6b9b ldr r3, [r3, #56] @ 0x38 8006482: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 8006484: 68fb ldr r3, [r7, #12] 8006486: 2201 movs r2, #1 8006488: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800648a: 68fb ldr r3, [r7, #12] 800648c: 6b1b ldr r3, [r3, #48] @ 0x30 800648e: 2b01 cmp r3, #1 8006490: d108 bne.n 80064a4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 8006492: 68fb ldr r3, [r7, #12] 8006494: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006496: 085b lsrs r3, r3, #1 8006498: b29b uxth r3, r3 800649a: 4619 mov r1, r3 800649c: 68f8 ldr r0, [r7, #12] 800649e: f7ff feed bl 800627c #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 80064a2: e002 b.n 80064aa HAL_UART_RxHalfCpltCallback(huart); 80064a4: 68f8 ldr r0, [r7, #12] 80064a6: f7ff fed5 bl 8006254 } 80064aa: bf00 nop 80064ac: 3710 adds r7, #16 80064ae: 46bd mov sp, r7 80064b0: bd80 pop {r7, pc} 080064b2 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 80064b2: b580 push {r7, lr} 80064b4: b084 sub sp, #16 80064b6: af00 add r7, sp, #0 80064b8: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 80064ba: 2300 movs r3, #0 80064bc: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80064be: 687b ldr r3, [r7, #4] 80064c0: 6b9b ldr r3, [r3, #56] @ 0x38 80064c2: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 80064c4: 68bb ldr r3, [r7, #8] 80064c6: 681b ldr r3, [r3, #0] 80064c8: 695b ldr r3, [r3, #20] 80064ca: f003 0380 and.w r3, r3, #128 @ 0x80 80064ce: 2b80 cmp r3, #128 @ 0x80 80064d0: bf0c ite eq 80064d2: 2301 moveq r3, #1 80064d4: 2300 movne r3, #0 80064d6: b2db uxtb r3, r3 80064d8: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 80064da: 68bb ldr r3, [r7, #8] 80064dc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80064e0: b2db uxtb r3, r3 80064e2: 2b21 cmp r3, #33 @ 0x21 80064e4: d108 bne.n 80064f8 80064e6: 68fb ldr r3, [r7, #12] 80064e8: 2b00 cmp r3, #0 80064ea: d005 beq.n 80064f8 { huart->TxXferCount = 0x00U; 80064ec: 68bb ldr r3, [r7, #8] 80064ee: 2200 movs r2, #0 80064f0: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 80064f2: 68b8 ldr r0, [r7, #8] 80064f4: f000 f926 bl 8006744 } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 80064f8: 68bb ldr r3, [r7, #8] 80064fa: 681b ldr r3, [r3, #0] 80064fc: 695b ldr r3, [r3, #20] 80064fe: f003 0340 and.w r3, r3, #64 @ 0x40 8006502: 2b40 cmp r3, #64 @ 0x40 8006504: bf0c ite eq 8006506: 2301 moveq r3, #1 8006508: 2300 movne r3, #0 800650a: b2db uxtb r3, r3 800650c: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 800650e: 68bb ldr r3, [r7, #8] 8006510: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8006514: b2db uxtb r3, r3 8006516: 2b22 cmp r3, #34 @ 0x22 8006518: d108 bne.n 800652c 800651a: 68fb ldr r3, [r7, #12] 800651c: 2b00 cmp r3, #0 800651e: d005 beq.n 800652c { huart->RxXferCount = 0x00U; 8006520: 68bb ldr r3, [r7, #8] 8006522: 2200 movs r2, #0 8006524: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 8006526: 68b8 ldr r0, [r7, #8] 8006528: f000 f934 bl 8006794 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 800652c: 68bb ldr r3, [r7, #8] 800652e: 6c5b ldr r3, [r3, #68] @ 0x44 8006530: f043 0210 orr.w r2, r3, #16 8006534: 68bb ldr r3, [r7, #8] 8006536: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006538: 68b8 ldr r0, [r7, #8] 800653a: f7ff fe95 bl 8006268 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800653e: bf00 nop 8006540: 3710 adds r7, #16 8006542: 46bd mov sp, r7 8006544: bd80 pop {r7, pc} 08006546 : * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8006546: b580 push {r7, lr} 8006548: b086 sub sp, #24 800654a: af00 add r7, sp, #0 800654c: 60f8 str r0, [r7, #12] 800654e: 60b9 str r1, [r7, #8] 8006550: 603b str r3, [r7, #0] 8006552: 4613 mov r3, r2 8006554: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8006556: e03b b.n 80065d0 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8006558: 6a3b ldr r3, [r7, #32] 800655a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800655e: d037 beq.n 80065d0 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8006560: f7fb fa32 bl 80019c8 8006564: 4602 mov r2, r0 8006566: 683b ldr r3, [r7, #0] 8006568: 1ad3 subs r3, r2, r3 800656a: 6a3a ldr r2, [r7, #32] 800656c: 429a cmp r2, r3 800656e: d302 bcc.n 8006576 8006570: 6a3b ldr r3, [r7, #32] 8006572: 2b00 cmp r3, #0 8006574: d101 bne.n 800657a { return HAL_TIMEOUT; 8006576: 2303 movs r3, #3 8006578: e03a b.n 80065f0 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 800657a: 68fb ldr r3, [r7, #12] 800657c: 681b ldr r3, [r3, #0] 800657e: 68db ldr r3, [r3, #12] 8006580: f003 0304 and.w r3, r3, #4 8006584: 2b00 cmp r3, #0 8006586: d023 beq.n 80065d0 8006588: 68bb ldr r3, [r7, #8] 800658a: 2b80 cmp r3, #128 @ 0x80 800658c: d020 beq.n 80065d0 800658e: 68bb ldr r3, [r7, #8] 8006590: 2b40 cmp r3, #64 @ 0x40 8006592: d01d beq.n 80065d0 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8006594: 68fb ldr r3, [r7, #12] 8006596: 681b ldr r3, [r3, #0] 8006598: 681b ldr r3, [r3, #0] 800659a: f003 0308 and.w r3, r3, #8 800659e: 2b08 cmp r3, #8 80065a0: d116 bne.n 80065d0 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_OREFLAG(huart); 80065a2: 2300 movs r3, #0 80065a4: 617b str r3, [r7, #20] 80065a6: 68fb ldr r3, [r7, #12] 80065a8: 681b ldr r3, [r3, #0] 80065aa: 681b ldr r3, [r3, #0] 80065ac: 617b str r3, [r7, #20] 80065ae: 68fb ldr r3, [r7, #12] 80065b0: 681b ldr r3, [r3, #0] 80065b2: 685b ldr r3, [r3, #4] 80065b4: 617b str r3, [r7, #20] 80065b6: 697b ldr r3, [r7, #20] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 80065b8: 68f8 ldr r0, [r7, #12] 80065ba: f000 f8eb bl 8006794 huart->ErrorCode = HAL_UART_ERROR_ORE; 80065be: 68fb ldr r3, [r7, #12] 80065c0: 2208 movs r2, #8 80065c2: 645a str r2, [r3, #68] @ 0x44 /* Process Unlocked */ __HAL_UNLOCK(huart); 80065c4: 68fb ldr r3, [r7, #12] 80065c6: 2200 movs r2, #0 80065c8: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 80065cc: 2301 movs r3, #1 80065ce: e00f b.n 80065f0 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80065d0: 68fb ldr r3, [r7, #12] 80065d2: 681b ldr r3, [r3, #0] 80065d4: 681a ldr r2, [r3, #0] 80065d6: 68bb ldr r3, [r7, #8] 80065d8: 4013 ands r3, r2 80065da: 68ba ldr r2, [r7, #8] 80065dc: 429a cmp r2, r3 80065de: bf0c ite eq 80065e0: 2301 moveq r3, #1 80065e2: 2300 movne r3, #0 80065e4: b2db uxtb r3, r3 80065e6: 461a mov r2, r3 80065e8: 79fb ldrb r3, [r7, #7] 80065ea: 429a cmp r2, r3 80065ec: d0b4 beq.n 8006558 } } } } return HAL_OK; 80065ee: 2300 movs r3, #0 } 80065f0: 4618 mov r0, r3 80065f2: 3718 adds r7, #24 80065f4: 46bd mov sp, r7 80065f6: bd80 pop {r7, pc} 080065f8 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80065f8: b580 push {r7, lr} 80065fa: b098 sub sp, #96 @ 0x60 80065fc: af00 add r7, sp, #0 80065fe: 60f8 str r0, [r7, #12] 8006600: 60b9 str r1, [r7, #8] 8006602: 4613 mov r3, r2 8006604: 80fb strh r3, [r7, #6] uint32_t *tmp; huart->pRxBuffPtr = pData; 8006606: 68ba ldr r2, [r7, #8] 8006608: 68fb ldr r3, [r7, #12] 800660a: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 800660c: 68fb ldr r3, [r7, #12] 800660e: 88fa ldrh r2, [r7, #6] 8006610: 859a strh r2, [r3, #44] @ 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 8006612: 68fb ldr r3, [r7, #12] 8006614: 2200 movs r2, #0 8006616: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8006618: 68fb ldr r3, [r7, #12] 800661a: 2222 movs r2, #34 @ 0x22 800661c: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 8006620: 68fb ldr r3, [r7, #12] 8006622: 6bdb ldr r3, [r3, #60] @ 0x3c 8006624: 4a44 ldr r2, [pc, #272] @ (8006738 ) 8006626: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 8006628: 68fb ldr r3, [r7, #12] 800662a: 6bdb ldr r3, [r3, #60] @ 0x3c 800662c: 4a43 ldr r2, [pc, #268] @ (800673c ) 800662e: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 8006630: 68fb ldr r3, [r7, #12] 8006632: 6bdb ldr r3, [r3, #60] @ 0x3c 8006634: 4a42 ldr r2, [pc, #264] @ (8006740 ) 8006636: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 8006638: 68fb ldr r3, [r7, #12] 800663a: 6bdb ldr r3, [r3, #60] @ 0x3c 800663c: 2200 movs r2, #0 800663e: 651a str r2, [r3, #80] @ 0x50 /* Enable the DMA stream */ tmp = (uint32_t *)&pData; 8006640: f107 0308 add.w r3, r7, #8 8006644: 65fb str r3, [r7, #92] @ 0x5c if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK) 8006646: 68fb ldr r3, [r7, #12] 8006648: 6bd8 ldr r0, [r3, #60] @ 0x3c 800664a: 68fb ldr r3, [r7, #12] 800664c: 681b ldr r3, [r3, #0] 800664e: 3304 adds r3, #4 8006650: 4619 mov r1, r3 8006652: 6dfb ldr r3, [r7, #92] @ 0x5c 8006654: 681a ldr r2, [r3, #0] 8006656: 88fb ldrh r3, [r7, #6] 8006658: f7fb fba6 bl 8001da8 800665c: 4603 mov r3, r0 800665e: 2b00 cmp r3, #0 8006660: d008 beq.n 8006674 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8006662: 68fb ldr r3, [r7, #12] 8006664: 2210 movs r2, #16 8006666: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; 8006668: 68fb ldr r3, [r7, #12] 800666a: 2220 movs r2, #32 800666c: f883 2042 strb.w r2, [r3, #66] @ 0x42 return HAL_ERROR; 8006670: 2301 movs r3, #1 8006672: e05d b.n 8006730 } /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 8006674: 2300 movs r3, #0 8006676: 613b str r3, [r7, #16] 8006678: 68fb ldr r3, [r7, #12] 800667a: 681b ldr r3, [r3, #0] 800667c: 681b ldr r3, [r3, #0] 800667e: 613b str r3, [r7, #16] 8006680: 68fb ldr r3, [r7, #12] 8006682: 681b ldr r3, [r3, #0] 8006684: 685b ldr r3, [r3, #4] 8006686: 613b str r3, [r7, #16] 8006688: 693b ldr r3, [r7, #16] if (huart->Init.Parity != UART_PARITY_NONE) 800668a: 68fb ldr r3, [r7, #12] 800668c: 691b ldr r3, [r3, #16] 800668e: 2b00 cmp r3, #0 8006690: d019 beq.n 80066c6 { /* Enable the UART Parity Error Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006692: 68fb ldr r3, [r7, #12] 8006694: 681b ldr r3, [r3, #0] 8006696: 330c adds r3, #12 8006698: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800669a: 6c3b ldr r3, [r7, #64] @ 0x40 800669c: e853 3f00 ldrex r3, [r3] 80066a0: 63fb str r3, [r7, #60] @ 0x3c return(result); 80066a2: 6bfb ldr r3, [r7, #60] @ 0x3c 80066a4: f443 7380 orr.w r3, r3, #256 @ 0x100 80066a8: 65bb str r3, [r7, #88] @ 0x58 80066aa: 68fb ldr r3, [r7, #12] 80066ac: 681b ldr r3, [r3, #0] 80066ae: 330c adds r3, #12 80066b0: 6dba ldr r2, [r7, #88] @ 0x58 80066b2: 64fa str r2, [r7, #76] @ 0x4c 80066b4: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80066b6: 6cb9 ldr r1, [r7, #72] @ 0x48 80066b8: 6cfa ldr r2, [r7, #76] @ 0x4c 80066ba: e841 2300 strex r3, r2, [r1] 80066be: 647b str r3, [r7, #68] @ 0x44 return(result); 80066c0: 6c7b ldr r3, [r7, #68] @ 0x44 80066c2: 2b00 cmp r3, #0 80066c4: d1e5 bne.n 8006692 } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 80066c6: 68fb ldr r3, [r7, #12] 80066c8: 681b ldr r3, [r3, #0] 80066ca: 3314 adds r3, #20 80066cc: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80066ce: 6afb ldr r3, [r7, #44] @ 0x2c 80066d0: e853 3f00 ldrex r3, [r3] 80066d4: 62bb str r3, [r7, #40] @ 0x28 return(result); 80066d6: 6abb ldr r3, [r7, #40] @ 0x28 80066d8: f043 0301 orr.w r3, r3, #1 80066dc: 657b str r3, [r7, #84] @ 0x54 80066de: 68fb ldr r3, [r7, #12] 80066e0: 681b ldr r3, [r3, #0] 80066e2: 3314 adds r3, #20 80066e4: 6d7a ldr r2, [r7, #84] @ 0x54 80066e6: 63ba str r2, [r7, #56] @ 0x38 80066e8: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80066ea: 6b79 ldr r1, [r7, #52] @ 0x34 80066ec: 6bba ldr r2, [r7, #56] @ 0x38 80066ee: e841 2300 strex r3, r2, [r1] 80066f2: 633b str r3, [r7, #48] @ 0x30 return(result); 80066f4: 6b3b ldr r3, [r7, #48] @ 0x30 80066f6: 2b00 cmp r3, #0 80066f8: d1e5 bne.n 80066c6 /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80066fa: 68fb ldr r3, [r7, #12] 80066fc: 681b ldr r3, [r3, #0] 80066fe: 3314 adds r3, #20 8006700: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006702: 69bb ldr r3, [r7, #24] 8006704: e853 3f00 ldrex r3, [r3] 8006708: 617b str r3, [r7, #20] return(result); 800670a: 697b ldr r3, [r7, #20] 800670c: f043 0340 orr.w r3, r3, #64 @ 0x40 8006710: 653b str r3, [r7, #80] @ 0x50 8006712: 68fb ldr r3, [r7, #12] 8006714: 681b ldr r3, [r3, #0] 8006716: 3314 adds r3, #20 8006718: 6d3a ldr r2, [r7, #80] @ 0x50 800671a: 627a str r2, [r7, #36] @ 0x24 800671c: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800671e: 6a39 ldr r1, [r7, #32] 8006720: 6a7a ldr r2, [r7, #36] @ 0x24 8006722: e841 2300 strex r3, r2, [r1] 8006726: 61fb str r3, [r7, #28] return(result); 8006728: 69fb ldr r3, [r7, #28] 800672a: 2b00 cmp r3, #0 800672c: d1e5 bne.n 80066fa return HAL_OK; 800672e: 2300 movs r3, #0 } 8006730: 4618 mov r0, r3 8006732: 3760 adds r7, #96 @ 0x60 8006734: 46bd mov sp, r7 8006736: bd80 pop {r7, pc} 8006738: 0800634b .word 0x0800634b 800673c: 08006477 .word 0x08006477 8006740: 080064b3 .word 0x080064b3 08006744 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 8006744: b480 push {r7} 8006746: b089 sub sp, #36 @ 0x24 8006748: af00 add r7, sp, #0 800674a: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 800674c: 687b ldr r3, [r7, #4] 800674e: 681b ldr r3, [r3, #0] 8006750: 330c adds r3, #12 8006752: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006754: 68fb ldr r3, [r7, #12] 8006756: e853 3f00 ldrex r3, [r3] 800675a: 60bb str r3, [r7, #8] return(result); 800675c: 68bb ldr r3, [r7, #8] 800675e: f023 03c0 bic.w r3, r3, #192 @ 0xc0 8006762: 61fb str r3, [r7, #28] 8006764: 687b ldr r3, [r7, #4] 8006766: 681b ldr r3, [r3, #0] 8006768: 330c adds r3, #12 800676a: 69fa ldr r2, [r7, #28] 800676c: 61ba str r2, [r7, #24] 800676e: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006770: 6979 ldr r1, [r7, #20] 8006772: 69ba ldr r2, [r7, #24] 8006774: e841 2300 strex r3, r2, [r1] 8006778: 613b str r3, [r7, #16] return(result); 800677a: 693b ldr r3, [r7, #16] 800677c: 2b00 cmp r3, #0 800677e: d1e5 bne.n 800674c /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8006780: 687b ldr r3, [r7, #4] 8006782: 2220 movs r2, #32 8006784: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 8006788: bf00 nop 800678a: 3724 adds r7, #36 @ 0x24 800678c: 46bd mov sp, r7 800678e: f85d 7b04 ldr.w r7, [sp], #4 8006792: 4770 bx lr 08006794 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8006794: b480 push {r7} 8006796: b095 sub sp, #84 @ 0x54 8006798: af00 add r7, sp, #0 800679a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 800679c: 687b ldr r3, [r7, #4] 800679e: 681b ldr r3, [r3, #0] 80067a0: 330c adds r3, #12 80067a2: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80067a4: 6b7b ldr r3, [r7, #52] @ 0x34 80067a6: e853 3f00 ldrex r3, [r3] 80067aa: 633b str r3, [r7, #48] @ 0x30 return(result); 80067ac: 6b3b ldr r3, [r7, #48] @ 0x30 80067ae: f423 7390 bic.w r3, r3, #288 @ 0x120 80067b2: 64fb str r3, [r7, #76] @ 0x4c 80067b4: 687b ldr r3, [r7, #4] 80067b6: 681b ldr r3, [r3, #0] 80067b8: 330c adds r3, #12 80067ba: 6cfa ldr r2, [r7, #76] @ 0x4c 80067bc: 643a str r2, [r7, #64] @ 0x40 80067be: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80067c0: 6bf9 ldr r1, [r7, #60] @ 0x3c 80067c2: 6c3a ldr r2, [r7, #64] @ 0x40 80067c4: e841 2300 strex r3, r2, [r1] 80067c8: 63bb str r3, [r7, #56] @ 0x38 return(result); 80067ca: 6bbb ldr r3, [r7, #56] @ 0x38 80067cc: 2b00 cmp r3, #0 80067ce: d1e5 bne.n 800679c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80067d0: 687b ldr r3, [r7, #4] 80067d2: 681b ldr r3, [r3, #0] 80067d4: 3314 adds r3, #20 80067d6: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80067d8: 6a3b ldr r3, [r7, #32] 80067da: e853 3f00 ldrex r3, [r3] 80067de: 61fb str r3, [r7, #28] return(result); 80067e0: 69fb ldr r3, [r7, #28] 80067e2: f023 0301 bic.w r3, r3, #1 80067e6: 64bb str r3, [r7, #72] @ 0x48 80067e8: 687b ldr r3, [r7, #4] 80067ea: 681b ldr r3, [r3, #0] 80067ec: 3314 adds r3, #20 80067ee: 6cba ldr r2, [r7, #72] @ 0x48 80067f0: 62fa str r2, [r7, #44] @ 0x2c 80067f2: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80067f4: 6ab9 ldr r1, [r7, #40] @ 0x28 80067f6: 6afa ldr r2, [r7, #44] @ 0x2c 80067f8: e841 2300 strex r3, r2, [r1] 80067fc: 627b str r3, [r7, #36] @ 0x24 return(result); 80067fe: 6a7b ldr r3, [r7, #36] @ 0x24 8006800: 2b00 cmp r3, #0 8006802: d1e5 bne.n 80067d0 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006804: 687b ldr r3, [r7, #4] 8006806: 6b1b ldr r3, [r3, #48] @ 0x30 8006808: 2b01 cmp r3, #1 800680a: d119 bne.n 8006840 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800680c: 687b ldr r3, [r7, #4] 800680e: 681b ldr r3, [r3, #0] 8006810: 330c adds r3, #12 8006812: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006814: 68fb ldr r3, [r7, #12] 8006816: e853 3f00 ldrex r3, [r3] 800681a: 60bb str r3, [r7, #8] return(result); 800681c: 68bb ldr r3, [r7, #8] 800681e: f023 0310 bic.w r3, r3, #16 8006822: 647b str r3, [r7, #68] @ 0x44 8006824: 687b ldr r3, [r7, #4] 8006826: 681b ldr r3, [r3, #0] 8006828: 330c adds r3, #12 800682a: 6c7a ldr r2, [r7, #68] @ 0x44 800682c: 61ba str r2, [r7, #24] 800682e: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006830: 6979 ldr r1, [r7, #20] 8006832: 69ba ldr r2, [r7, #24] 8006834: e841 2300 strex r3, r2, [r1] 8006838: 613b str r3, [r7, #16] return(result); 800683a: 693b ldr r3, [r7, #16] 800683c: 2b00 cmp r3, #0 800683e: d1e5 bne.n 800680c } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006840: 687b ldr r3, [r7, #4] 8006842: 2220 movs r2, #32 8006844: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006848: 687b ldr r3, [r7, #4] 800684a: 2200 movs r2, #0 800684c: 631a str r2, [r3, #48] @ 0x30 } 800684e: bf00 nop 8006850: 3754 adds r7, #84 @ 0x54 8006852: 46bd mov sp, r7 8006854: f85d 7b04 ldr.w r7, [sp], #4 8006858: 4770 bx lr 0800685a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 800685a: b580 push {r7, lr} 800685c: b084 sub sp, #16 800685e: af00 add r7, sp, #0 8006860: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006862: 687b ldr r3, [r7, #4] 8006864: 6b9b ldr r3, [r3, #56] @ 0x38 8006866: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8006868: 68fb ldr r3, [r7, #12] 800686a: 2200 movs r2, #0 800686c: 85da strh r2, [r3, #46] @ 0x2e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800686e: 68f8 ldr r0, [r7, #12] 8006870: f7ff fcfa bl 8006268 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006874: bf00 nop 8006876: 3710 adds r7, #16 8006878: 46bd mov sp, r7 800687a: bd80 pop {r7, pc} 0800687c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 800687c: b480 push {r7} 800687e: b085 sub sp, #20 8006880: af00 add r7, sp, #0 8006882: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8006884: 687b ldr r3, [r7, #4] 8006886: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800688a: b2db uxtb r3, r3 800688c: 2b21 cmp r3, #33 @ 0x21 800688e: d13e bne.n 800690e { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006890: 687b ldr r3, [r7, #4] 8006892: 689b ldr r3, [r3, #8] 8006894: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006898: d114 bne.n 80068c4 800689a: 687b ldr r3, [r7, #4] 800689c: 691b ldr r3, [r3, #16] 800689e: 2b00 cmp r3, #0 80068a0: d110 bne.n 80068c4 { tmp = (const uint16_t *) huart->pTxBuffPtr; 80068a2: 687b ldr r3, [r7, #4] 80068a4: 6a1b ldr r3, [r3, #32] 80068a6: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 80068a8: 68fb ldr r3, [r7, #12] 80068aa: 881b ldrh r3, [r3, #0] 80068ac: 461a mov r2, r3 80068ae: 687b ldr r3, [r7, #4] 80068b0: 681b ldr r3, [r3, #0] 80068b2: f3c2 0208 ubfx r2, r2, #0, #9 80068b6: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 80068b8: 687b ldr r3, [r7, #4] 80068ba: 6a1b ldr r3, [r3, #32] 80068bc: 1c9a adds r2, r3, #2 80068be: 687b ldr r3, [r7, #4] 80068c0: 621a str r2, [r3, #32] 80068c2: e008 b.n 80068d6 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 80068c4: 687b ldr r3, [r7, #4] 80068c6: 6a1b ldr r3, [r3, #32] 80068c8: 1c59 adds r1, r3, #1 80068ca: 687a ldr r2, [r7, #4] 80068cc: 6211 str r1, [r2, #32] 80068ce: 781a ldrb r2, [r3, #0] 80068d0: 687b ldr r3, [r7, #4] 80068d2: 681b ldr r3, [r3, #0] 80068d4: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 80068d6: 687b ldr r3, [r7, #4] 80068d8: 8cdb ldrh r3, [r3, #38] @ 0x26 80068da: b29b uxth r3, r3 80068dc: 3b01 subs r3, #1 80068de: b29b uxth r3, r3 80068e0: 687a ldr r2, [r7, #4] 80068e2: 4619 mov r1, r3 80068e4: 84d1 strh r1, [r2, #38] @ 0x26 80068e6: 2b00 cmp r3, #0 80068e8: d10f bne.n 800690a { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 80068ea: 687b ldr r3, [r7, #4] 80068ec: 681b ldr r3, [r3, #0] 80068ee: 68da ldr r2, [r3, #12] 80068f0: 687b ldr r3, [r7, #4] 80068f2: 681b ldr r3, [r3, #0] 80068f4: f022 0280 bic.w r2, r2, #128 @ 0x80 80068f8: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 80068fa: 687b ldr r3, [r7, #4] 80068fc: 681b ldr r3, [r3, #0] 80068fe: 68da ldr r2, [r3, #12] 8006900: 687b ldr r3, [r7, #4] 8006902: 681b ldr r3, [r3, #0] 8006904: f042 0240 orr.w r2, r2, #64 @ 0x40 8006908: 60da str r2, [r3, #12] } return HAL_OK; 800690a: 2300 movs r3, #0 800690c: e000 b.n 8006910 } else { return HAL_BUSY; 800690e: 2302 movs r3, #2 } } 8006910: 4618 mov r0, r3 8006912: 3714 adds r7, #20 8006914: 46bd mov sp, r7 8006916: f85d 7b04 ldr.w r7, [sp], #4 800691a: 4770 bx lr 0800691c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 800691c: b580 push {r7, lr} 800691e: b082 sub sp, #8 8006920: af00 add r7, sp, #0 8006922: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8006924: 687b ldr r3, [r7, #4] 8006926: 681b ldr r3, [r3, #0] 8006928: 68da ldr r2, [r3, #12] 800692a: 687b ldr r3, [r7, #4] 800692c: 681b ldr r3, [r3, #0] 800692e: f022 0240 bic.w r2, r2, #64 @ 0x40 8006932: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8006934: 687b ldr r3, [r7, #4] 8006936: 2220 movs r2, #32 8006938: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 800693c: 6878 ldr r0, [r7, #4] 800693e: f7ff fc75 bl 800622c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8006942: 2300 movs r3, #0 } 8006944: 4618 mov r0, r3 8006946: 3708 adds r7, #8 8006948: 46bd mov sp, r7 800694a: bd80 pop {r7, pc} 0800694c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 800694c: b580 push {r7, lr} 800694e: b08c sub sp, #48 @ 0x30 8006950: af00 add r7, sp, #0 8006952: 6078 str r0, [r7, #4] uint8_t *pdata8bits = NULL; 8006954: 2300 movs r3, #0 8006956: 62fb str r3, [r7, #44] @ 0x2c uint16_t *pdata16bits = NULL; 8006958: 2300 movs r3, #0 800695a: 62bb str r3, [r7, #40] @ 0x28 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800695c: 687b ldr r3, [r7, #4] 800695e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8006962: b2db uxtb r3, r3 8006964: 2b22 cmp r3, #34 @ 0x22 8006966: f040 80aa bne.w 8006abe { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800696a: 687b ldr r3, [r7, #4] 800696c: 689b ldr r3, [r3, #8] 800696e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006972: d115 bne.n 80069a0 8006974: 687b ldr r3, [r7, #4] 8006976: 691b ldr r3, [r3, #16] 8006978: 2b00 cmp r3, #0 800697a: d111 bne.n 80069a0 { /* Unused pdata8bits */ UNUSED(pdata8bits); pdata16bits = (uint16_t *) huart->pRxBuffPtr; 800697c: 687b ldr r3, [r7, #4] 800697e: 6a9b ldr r3, [r3, #40] @ 0x28 8006980: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8006982: 687b ldr r3, [r7, #4] 8006984: 681b ldr r3, [r3, #0] 8006986: 685b ldr r3, [r3, #4] 8006988: b29b uxth r3, r3 800698a: f3c3 0308 ubfx r3, r3, #0, #9 800698e: b29a uxth r2, r3 8006990: 6abb ldr r3, [r7, #40] @ 0x28 8006992: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8006994: 687b ldr r3, [r7, #4] 8006996: 6a9b ldr r3, [r3, #40] @ 0x28 8006998: 1c9a adds r2, r3, #2 800699a: 687b ldr r3, [r7, #4] 800699c: 629a str r2, [r3, #40] @ 0x28 800699e: e024 b.n 80069ea } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 80069a0: 687b ldr r3, [r7, #4] 80069a2: 6a9b ldr r3, [r3, #40] @ 0x28 80069a4: 62fb str r3, [r7, #44] @ 0x2c /* Unused pdata16bits */ UNUSED(pdata16bits); if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 80069a6: 687b ldr r3, [r7, #4] 80069a8: 689b ldr r3, [r3, #8] 80069aa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80069ae: d007 beq.n 80069c0 80069b0: 687b ldr r3, [r7, #4] 80069b2: 689b ldr r3, [r3, #8] 80069b4: 2b00 cmp r3, #0 80069b6: d10a bne.n 80069ce 80069b8: 687b ldr r3, [r7, #4] 80069ba: 691b ldr r3, [r3, #16] 80069bc: 2b00 cmp r3, #0 80069be: d106 bne.n 80069ce { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 80069c0: 687b ldr r3, [r7, #4] 80069c2: 681b ldr r3, [r3, #0] 80069c4: 685b ldr r3, [r3, #4] 80069c6: b2da uxtb r2, r3 80069c8: 6afb ldr r3, [r7, #44] @ 0x2c 80069ca: 701a strb r2, [r3, #0] 80069cc: e008 b.n 80069e0 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 80069ce: 687b ldr r3, [r7, #4] 80069d0: 681b ldr r3, [r3, #0] 80069d2: 685b ldr r3, [r3, #4] 80069d4: b2db uxtb r3, r3 80069d6: f003 037f and.w r3, r3, #127 @ 0x7f 80069da: b2da uxtb r2, r3 80069dc: 6afb ldr r3, [r7, #44] @ 0x2c 80069de: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 80069e0: 687b ldr r3, [r7, #4] 80069e2: 6a9b ldr r3, [r3, #40] @ 0x28 80069e4: 1c5a adds r2, r3, #1 80069e6: 687b ldr r3, [r7, #4] 80069e8: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 80069ea: 687b ldr r3, [r7, #4] 80069ec: 8ddb ldrh r3, [r3, #46] @ 0x2e 80069ee: b29b uxth r3, r3 80069f0: 3b01 subs r3, #1 80069f2: b29b uxth r3, r3 80069f4: 687a ldr r2, [r7, #4] 80069f6: 4619 mov r1, r3 80069f8: 85d1 strh r1, [r2, #46] @ 0x2e 80069fa: 2b00 cmp r3, #0 80069fc: d15d bne.n 8006aba { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 80069fe: 687b ldr r3, [r7, #4] 8006a00: 681b ldr r3, [r3, #0] 8006a02: 68da ldr r2, [r3, #12] 8006a04: 687b ldr r3, [r7, #4] 8006a06: 681b ldr r3, [r3, #0] 8006a08: f022 0220 bic.w r2, r2, #32 8006a0c: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8006a0e: 687b ldr r3, [r7, #4] 8006a10: 681b ldr r3, [r3, #0] 8006a12: 68da ldr r2, [r3, #12] 8006a14: 687b ldr r3, [r7, #4] 8006a16: 681b ldr r3, [r3, #0] 8006a18: f422 7280 bic.w r2, r2, #256 @ 0x100 8006a1c: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8006a1e: 687b ldr r3, [r7, #4] 8006a20: 681b ldr r3, [r3, #0] 8006a22: 695a ldr r2, [r3, #20] 8006a24: 687b ldr r3, [r7, #4] 8006a26: 681b ldr r3, [r3, #0] 8006a28: f022 0201 bic.w r2, r2, #1 8006a2c: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006a2e: 687b ldr r3, [r7, #4] 8006a30: 2220 movs r2, #32 8006a32: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8006a36: 687b ldr r3, [r7, #4] 8006a38: 2200 movs r2, #0 8006a3a: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006a3c: 687b ldr r3, [r7, #4] 8006a3e: 6b1b ldr r3, [r3, #48] @ 0x30 8006a40: 2b01 cmp r3, #1 8006a42: d135 bne.n 8006ab0 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006a44: 687b ldr r3, [r7, #4] 8006a46: 2200 movs r2, #0 8006a48: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006a4a: 687b ldr r3, [r7, #4] 8006a4c: 681b ldr r3, [r3, #0] 8006a4e: 330c adds r3, #12 8006a50: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006a52: 697b ldr r3, [r7, #20] 8006a54: e853 3f00 ldrex r3, [r3] 8006a58: 613b str r3, [r7, #16] return(result); 8006a5a: 693b ldr r3, [r7, #16] 8006a5c: f023 0310 bic.w r3, r3, #16 8006a60: 627b str r3, [r7, #36] @ 0x24 8006a62: 687b ldr r3, [r7, #4] 8006a64: 681b ldr r3, [r3, #0] 8006a66: 330c adds r3, #12 8006a68: 6a7a ldr r2, [r7, #36] @ 0x24 8006a6a: 623a str r2, [r7, #32] 8006a6c: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006a6e: 69f9 ldr r1, [r7, #28] 8006a70: 6a3a ldr r2, [r7, #32] 8006a72: e841 2300 strex r3, r2, [r1] 8006a76: 61bb str r3, [r7, #24] return(result); 8006a78: 69bb ldr r3, [r7, #24] 8006a7a: 2b00 cmp r3, #0 8006a7c: d1e5 bne.n 8006a4a /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8006a7e: 687b ldr r3, [r7, #4] 8006a80: 681b ldr r3, [r3, #0] 8006a82: 681b ldr r3, [r3, #0] 8006a84: f003 0310 and.w r3, r3, #16 8006a88: 2b10 cmp r3, #16 8006a8a: d10a bne.n 8006aa2 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8006a8c: 2300 movs r3, #0 8006a8e: 60fb str r3, [r7, #12] 8006a90: 687b ldr r3, [r7, #4] 8006a92: 681b ldr r3, [r3, #0] 8006a94: 681b ldr r3, [r3, #0] 8006a96: 60fb str r3, [r7, #12] 8006a98: 687b ldr r3, [r7, #4] 8006a9a: 681b ldr r3, [r3, #0] 8006a9c: 685b ldr r3, [r3, #4] 8006a9e: 60fb str r3, [r7, #12] 8006aa0: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006aa2: 687b ldr r3, [r7, #4] 8006aa4: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006aa6: 4619 mov r1, r3 8006aa8: 6878 ldr r0, [r7, #4] 8006aaa: f7ff fbe7 bl 800627c 8006aae: e002 b.n 8006ab6 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8006ab0: 6878 ldr r0, [r7, #4] 8006ab2: f7f9 ffc3 bl 8000a3c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8006ab6: 2300 movs r3, #0 8006ab8: e002 b.n 8006ac0 } return HAL_OK; 8006aba: 2300 movs r3, #0 8006abc: e000 b.n 8006ac0 } else { return HAL_BUSY; 8006abe: 2302 movs r3, #2 } } 8006ac0: 4618 mov r0, r3 8006ac2: 3730 adds r7, #48 @ 0x30 8006ac4: 46bd mov sp, r7 8006ac6: bd80 pop {r7, pc} 08006ac8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8006ac8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8006acc: b0c0 sub sp, #256 @ 0x100 8006ace: af00 add r7, sp, #0 8006ad0: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4 assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8006ad4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006ad8: 681b ldr r3, [r3, #0] 8006ada: 691b ldr r3, [r3, #16] 8006adc: f423 5040 bic.w r0, r3, #12288 @ 0x3000 8006ae0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006ae4: 68d9 ldr r1, [r3, #12] 8006ae6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006aea: 681a ldr r2, [r3, #0] 8006aec: ea40 0301 orr.w r3, r0, r1 8006af0: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 8006af2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006af6: 689a ldr r2, [r3, #8] 8006af8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006afc: 691b ldr r3, [r3, #16] 8006afe: 431a orrs r2, r3 8006b00: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b04: 695b ldr r3, [r3, #20] 8006b06: 431a orrs r2, r3 8006b08: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b0c: 69db ldr r3, [r3, #28] 8006b0e: 4313 orrs r3, r2 8006b10: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 MODIFY_REG(huart->Instance->CR1, 8006b14: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b18: 681b ldr r3, [r3, #0] 8006b1a: 68db ldr r3, [r3, #12] 8006b1c: f423 4116 bic.w r1, r3, #38400 @ 0x9600 8006b20: f021 010c bic.w r1, r1, #12 8006b24: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b28: 681a ldr r2, [r3, #0] 8006b2a: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 8006b2e: 430b orrs r3, r1 8006b30: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8006b32: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b36: 681b ldr r3, [r3, #0] 8006b38: 695b ldr r3, [r3, #20] 8006b3a: f423 7040 bic.w r0, r3, #768 @ 0x300 8006b3e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b42: 6999 ldr r1, [r3, #24] 8006b44: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b48: 681a ldr r2, [r3, #0] 8006b4a: ea40 0301 orr.w r3, r0, r1 8006b4e: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 8006b50: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b54: 681a ldr r2, [r3, #0] 8006b56: 4b8f ldr r3, [pc, #572] @ (8006d94 ) 8006b58: 429a cmp r2, r3 8006b5a: d005 beq.n 8006b68 8006b5c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b60: 681a ldr r2, [r3, #0] 8006b62: 4b8d ldr r3, [pc, #564] @ (8006d98 ) 8006b64: 429a cmp r2, r3 8006b66: d104 bne.n 8006b72 { pclk = HAL_RCC_GetPCLK2Freq(); 8006b68: f7fd fb08 bl 800417c 8006b6c: f8c7 00fc str.w r0, [r7, #252] @ 0xfc 8006b70: e003 b.n 8006b7a pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); 8006b72: f7fd faef bl 8004154 8006b76: f8c7 00fc str.w r0, [r7, #252] @ 0xfc } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8006b7a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b7e: 69db ldr r3, [r3, #28] 8006b80: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8006b84: f040 810c bne.w 8006da0 { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8006b88: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006b8c: 2200 movs r2, #0 8006b8e: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 8006b92: f8c7 20ec str.w r2, [r7, #236] @ 0xec 8006b96: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8 8006b9a: 4622 mov r2, r4 8006b9c: 462b mov r3, r5 8006b9e: 1891 adds r1, r2, r2 8006ba0: 65b9 str r1, [r7, #88] @ 0x58 8006ba2: 415b adcs r3, r3 8006ba4: 65fb str r3, [r7, #92] @ 0x5c 8006ba6: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8006baa: 4621 mov r1, r4 8006bac: eb12 0801 adds.w r8, r2, r1 8006bb0: 4629 mov r1, r5 8006bb2: eb43 0901 adc.w r9, r3, r1 8006bb6: f04f 0200 mov.w r2, #0 8006bba: f04f 0300 mov.w r3, #0 8006bbe: ea4f 03c9 mov.w r3, r9, lsl #3 8006bc2: ea43 7358 orr.w r3, r3, r8, lsr #29 8006bc6: ea4f 02c8 mov.w r2, r8, lsl #3 8006bca: 4690 mov r8, r2 8006bcc: 4699 mov r9, r3 8006bce: 4623 mov r3, r4 8006bd0: eb18 0303 adds.w r3, r8, r3 8006bd4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 8006bd8: 462b mov r3, r5 8006bda: eb49 0303 adc.w r3, r9, r3 8006bde: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 8006be2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006be6: 685b ldr r3, [r3, #4] 8006be8: 2200 movs r2, #0 8006bea: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 8006bee: f8c7 20dc str.w r2, [r7, #220] @ 0xdc 8006bf2: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 8006bf6: 460b mov r3, r1 8006bf8: 18db adds r3, r3, r3 8006bfa: 653b str r3, [r7, #80] @ 0x50 8006bfc: 4613 mov r3, r2 8006bfe: eb42 0303 adc.w r3, r2, r3 8006c02: 657b str r3, [r7, #84] @ 0x54 8006c04: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50 8006c08: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0 8006c0c: f7f9 fafa bl 8000204 <__aeabi_uldivmod> 8006c10: 4602 mov r2, r0 8006c12: 460b mov r3, r1 8006c14: 4b61 ldr r3, [pc, #388] @ (8006d9c ) 8006c16: fba3 2302 umull r2, r3, r3, r2 8006c1a: 095b lsrs r3, r3, #5 8006c1c: 011c lsls r4, r3, #4 8006c1e: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006c22: 2200 movs r2, #0 8006c24: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8006c28: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4 8006c2c: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0 8006c30: 4642 mov r2, r8 8006c32: 464b mov r3, r9 8006c34: 1891 adds r1, r2, r2 8006c36: 64b9 str r1, [r7, #72] @ 0x48 8006c38: 415b adcs r3, r3 8006c3a: 64fb str r3, [r7, #76] @ 0x4c 8006c3c: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8006c40: 4641 mov r1, r8 8006c42: eb12 0a01 adds.w sl, r2, r1 8006c46: 4649 mov r1, r9 8006c48: eb43 0b01 adc.w fp, r3, r1 8006c4c: f04f 0200 mov.w r2, #0 8006c50: f04f 0300 mov.w r3, #0 8006c54: ea4f 03cb mov.w r3, fp, lsl #3 8006c58: ea43 735a orr.w r3, r3, sl, lsr #29 8006c5c: ea4f 02ca mov.w r2, sl, lsl #3 8006c60: 4692 mov sl, r2 8006c62: 469b mov fp, r3 8006c64: 4643 mov r3, r8 8006c66: eb1a 0303 adds.w r3, sl, r3 8006c6a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8006c6e: 464b mov r3, r9 8006c70: eb4b 0303 adc.w r3, fp, r3 8006c74: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 8006c78: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006c7c: 685b ldr r3, [r3, #4] 8006c7e: 2200 movs r2, #0 8006c80: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8006c84: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4 8006c88: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 8006c8c: 460b mov r3, r1 8006c8e: 18db adds r3, r3, r3 8006c90: 643b str r3, [r7, #64] @ 0x40 8006c92: 4613 mov r3, r2 8006c94: eb42 0303 adc.w r3, r2, r3 8006c98: 647b str r3, [r7, #68] @ 0x44 8006c9a: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40 8006c9e: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8 8006ca2: f7f9 faaf bl 8000204 <__aeabi_uldivmod> 8006ca6: 4602 mov r2, r0 8006ca8: 460b mov r3, r1 8006caa: 4611 mov r1, r2 8006cac: 4b3b ldr r3, [pc, #236] @ (8006d9c ) 8006cae: fba3 2301 umull r2, r3, r3, r1 8006cb2: 095b lsrs r3, r3, #5 8006cb4: 2264 movs r2, #100 @ 0x64 8006cb6: fb02 f303 mul.w r3, r2, r3 8006cba: 1acb subs r3, r1, r3 8006cbc: 00db lsls r3, r3, #3 8006cbe: f103 0232 add.w r2, r3, #50 @ 0x32 8006cc2: 4b36 ldr r3, [pc, #216] @ (8006d9c ) 8006cc4: fba3 2302 umull r2, r3, r3, r2 8006cc8: 095b lsrs r3, r3, #5 8006cca: 005b lsls r3, r3, #1 8006ccc: f403 73f8 and.w r3, r3, #496 @ 0x1f0 8006cd0: 441c add r4, r3 8006cd2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006cd6: 2200 movs r2, #0 8006cd8: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006cdc: f8c7 20bc str.w r2, [r7, #188] @ 0xbc 8006ce0: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8 8006ce4: 4642 mov r2, r8 8006ce6: 464b mov r3, r9 8006ce8: 1891 adds r1, r2, r2 8006cea: 63b9 str r1, [r7, #56] @ 0x38 8006cec: 415b adcs r3, r3 8006cee: 63fb str r3, [r7, #60] @ 0x3c 8006cf0: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38 8006cf4: 4641 mov r1, r8 8006cf6: 1851 adds r1, r2, r1 8006cf8: 6339 str r1, [r7, #48] @ 0x30 8006cfa: 4649 mov r1, r9 8006cfc: 414b adcs r3, r1 8006cfe: 637b str r3, [r7, #52] @ 0x34 8006d00: f04f 0200 mov.w r2, #0 8006d04: f04f 0300 mov.w r3, #0 8006d08: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30 8006d0c: 4659 mov r1, fp 8006d0e: 00cb lsls r3, r1, #3 8006d10: 4651 mov r1, sl 8006d12: ea43 7351 orr.w r3, r3, r1, lsr #29 8006d16: 4651 mov r1, sl 8006d18: 00ca lsls r2, r1, #3 8006d1a: 4610 mov r0, r2 8006d1c: 4619 mov r1, r3 8006d1e: 4603 mov r3, r0 8006d20: 4642 mov r2, r8 8006d22: 189b adds r3, r3, r2 8006d24: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8006d28: 464b mov r3, r9 8006d2a: 460a mov r2, r1 8006d2c: eb42 0303 adc.w r3, r2, r3 8006d30: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8006d34: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006d38: 685b ldr r3, [r3, #4] 8006d3a: 2200 movs r2, #0 8006d3c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 8006d40: f8c7 20ac str.w r2, [r7, #172] @ 0xac 8006d44: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 8006d48: 460b mov r3, r1 8006d4a: 18db adds r3, r3, r3 8006d4c: 62bb str r3, [r7, #40] @ 0x28 8006d4e: 4613 mov r3, r2 8006d50: eb42 0303 adc.w r3, r2, r3 8006d54: 62fb str r3, [r7, #44] @ 0x2c 8006d56: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 8006d5a: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0 8006d5e: f7f9 fa51 bl 8000204 <__aeabi_uldivmod> 8006d62: 4602 mov r2, r0 8006d64: 460b mov r3, r1 8006d66: 4b0d ldr r3, [pc, #52] @ (8006d9c ) 8006d68: fba3 1302 umull r1, r3, r3, r2 8006d6c: 095b lsrs r3, r3, #5 8006d6e: 2164 movs r1, #100 @ 0x64 8006d70: fb01 f303 mul.w r3, r1, r3 8006d74: 1ad3 subs r3, r2, r3 8006d76: 00db lsls r3, r3, #3 8006d78: 3332 adds r3, #50 @ 0x32 8006d7a: 4a08 ldr r2, [pc, #32] @ (8006d9c ) 8006d7c: fba2 2303 umull r2, r3, r2, r3 8006d80: 095b lsrs r3, r3, #5 8006d82: f003 0207 and.w r2, r3, #7 8006d86: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006d8a: 681b ldr r3, [r3, #0] 8006d8c: 4422 add r2, r4 8006d8e: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } 8006d90: e106 b.n 8006fa0 8006d92: bf00 nop 8006d94: 40011000 .word 0x40011000 8006d98: 40011400 .word 0x40011400 8006d9c: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8006da0: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006da4: 2200 movs r2, #0 8006da6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 8006daa: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4 8006dae: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0 8006db2: 4642 mov r2, r8 8006db4: 464b mov r3, r9 8006db6: 1891 adds r1, r2, r2 8006db8: 6239 str r1, [r7, #32] 8006dba: 415b adcs r3, r3 8006dbc: 627b str r3, [r7, #36] @ 0x24 8006dbe: e9d7 2308 ldrd r2, r3, [r7, #32] 8006dc2: 4641 mov r1, r8 8006dc4: 1854 adds r4, r2, r1 8006dc6: 4649 mov r1, r9 8006dc8: eb43 0501 adc.w r5, r3, r1 8006dcc: f04f 0200 mov.w r2, #0 8006dd0: f04f 0300 mov.w r3, #0 8006dd4: 00eb lsls r3, r5, #3 8006dd6: ea43 7354 orr.w r3, r3, r4, lsr #29 8006dda: 00e2 lsls r2, r4, #3 8006ddc: 4614 mov r4, r2 8006dde: 461d mov r5, r3 8006de0: 4643 mov r3, r8 8006de2: 18e3 adds r3, r4, r3 8006de4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8006de8: 464b mov r3, r9 8006dea: eb45 0303 adc.w r3, r5, r3 8006dee: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8006df2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006df6: 685b ldr r3, [r3, #4] 8006df8: 2200 movs r2, #0 8006dfa: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8006dfe: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8006e02: f04f 0200 mov.w r2, #0 8006e06: f04f 0300 mov.w r3, #0 8006e0a: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8006e0e: 4629 mov r1, r5 8006e10: 008b lsls r3, r1, #2 8006e12: 4621 mov r1, r4 8006e14: ea43 7391 orr.w r3, r3, r1, lsr #30 8006e18: 4621 mov r1, r4 8006e1a: 008a lsls r2, r1, #2 8006e1c: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98 8006e20: f7f9 f9f0 bl 8000204 <__aeabi_uldivmod> 8006e24: 4602 mov r2, r0 8006e26: 460b mov r3, r1 8006e28: 4b60 ldr r3, [pc, #384] @ (8006fac ) 8006e2a: fba3 2302 umull r2, r3, r3, r2 8006e2e: 095b lsrs r3, r3, #5 8006e30: 011c lsls r4, r3, #4 8006e32: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006e36: 2200 movs r2, #0 8006e38: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8006e3c: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8006e40: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88 8006e44: 4642 mov r2, r8 8006e46: 464b mov r3, r9 8006e48: 1891 adds r1, r2, r2 8006e4a: 61b9 str r1, [r7, #24] 8006e4c: 415b adcs r3, r3 8006e4e: 61fb str r3, [r7, #28] 8006e50: e9d7 2306 ldrd r2, r3, [r7, #24] 8006e54: 4641 mov r1, r8 8006e56: 1851 adds r1, r2, r1 8006e58: 6139 str r1, [r7, #16] 8006e5a: 4649 mov r1, r9 8006e5c: 414b adcs r3, r1 8006e5e: 617b str r3, [r7, #20] 8006e60: f04f 0200 mov.w r2, #0 8006e64: f04f 0300 mov.w r3, #0 8006e68: e9d7 ab04 ldrd sl, fp, [r7, #16] 8006e6c: 4659 mov r1, fp 8006e6e: 00cb lsls r3, r1, #3 8006e70: 4651 mov r1, sl 8006e72: ea43 7351 orr.w r3, r3, r1, lsr #29 8006e76: 4651 mov r1, sl 8006e78: 00ca lsls r2, r1, #3 8006e7a: 4610 mov r0, r2 8006e7c: 4619 mov r1, r3 8006e7e: 4603 mov r3, r0 8006e80: 4642 mov r2, r8 8006e82: 189b adds r3, r3, r2 8006e84: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8006e88: 464b mov r3, r9 8006e8a: 460a mov r2, r1 8006e8c: eb42 0303 adc.w r3, r2, r3 8006e90: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8006e94: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006e98: 685b ldr r3, [r3, #4] 8006e9a: 2200 movs r2, #0 8006e9c: 67bb str r3, [r7, #120] @ 0x78 8006e9e: 67fa str r2, [r7, #124] @ 0x7c 8006ea0: f04f 0200 mov.w r2, #0 8006ea4: f04f 0300 mov.w r3, #0 8006ea8: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78 8006eac: 4649 mov r1, r9 8006eae: 008b lsls r3, r1, #2 8006eb0: 4641 mov r1, r8 8006eb2: ea43 7391 orr.w r3, r3, r1, lsr #30 8006eb6: 4641 mov r1, r8 8006eb8: 008a lsls r2, r1, #2 8006eba: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80 8006ebe: f7f9 f9a1 bl 8000204 <__aeabi_uldivmod> 8006ec2: 4602 mov r2, r0 8006ec4: 460b mov r3, r1 8006ec6: 4611 mov r1, r2 8006ec8: 4b38 ldr r3, [pc, #224] @ (8006fac ) 8006eca: fba3 2301 umull r2, r3, r3, r1 8006ece: 095b lsrs r3, r3, #5 8006ed0: 2264 movs r2, #100 @ 0x64 8006ed2: fb02 f303 mul.w r3, r2, r3 8006ed6: 1acb subs r3, r1, r3 8006ed8: 011b lsls r3, r3, #4 8006eda: 3332 adds r3, #50 @ 0x32 8006edc: 4a33 ldr r2, [pc, #204] @ (8006fac ) 8006ede: fba2 2303 umull r2, r3, r2, r3 8006ee2: 095b lsrs r3, r3, #5 8006ee4: f003 03f0 and.w r3, r3, #240 @ 0xf0 8006ee8: 441c add r4, r3 8006eea: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006eee: 2200 movs r2, #0 8006ef0: 673b str r3, [r7, #112] @ 0x70 8006ef2: 677a str r2, [r7, #116] @ 0x74 8006ef4: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70 8006ef8: 4642 mov r2, r8 8006efa: 464b mov r3, r9 8006efc: 1891 adds r1, r2, r2 8006efe: 60b9 str r1, [r7, #8] 8006f00: 415b adcs r3, r3 8006f02: 60fb str r3, [r7, #12] 8006f04: e9d7 2302 ldrd r2, r3, [r7, #8] 8006f08: 4641 mov r1, r8 8006f0a: 1851 adds r1, r2, r1 8006f0c: 6039 str r1, [r7, #0] 8006f0e: 4649 mov r1, r9 8006f10: 414b adcs r3, r1 8006f12: 607b str r3, [r7, #4] 8006f14: f04f 0200 mov.w r2, #0 8006f18: f04f 0300 mov.w r3, #0 8006f1c: e9d7 ab00 ldrd sl, fp, [r7] 8006f20: 4659 mov r1, fp 8006f22: 00cb lsls r3, r1, #3 8006f24: 4651 mov r1, sl 8006f26: ea43 7351 orr.w r3, r3, r1, lsr #29 8006f2a: 4651 mov r1, sl 8006f2c: 00ca lsls r2, r1, #3 8006f2e: 4610 mov r0, r2 8006f30: 4619 mov r1, r3 8006f32: 4603 mov r3, r0 8006f34: 4642 mov r2, r8 8006f36: 189b adds r3, r3, r2 8006f38: 66bb str r3, [r7, #104] @ 0x68 8006f3a: 464b mov r3, r9 8006f3c: 460a mov r2, r1 8006f3e: eb42 0303 adc.w r3, r2, r3 8006f42: 66fb str r3, [r7, #108] @ 0x6c 8006f44: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006f48: 685b ldr r3, [r3, #4] 8006f4a: 2200 movs r2, #0 8006f4c: 663b str r3, [r7, #96] @ 0x60 8006f4e: 667a str r2, [r7, #100] @ 0x64 8006f50: f04f 0200 mov.w r2, #0 8006f54: f04f 0300 mov.w r3, #0 8006f58: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60 8006f5c: 4649 mov r1, r9 8006f5e: 008b lsls r3, r1, #2 8006f60: 4641 mov r1, r8 8006f62: ea43 7391 orr.w r3, r3, r1, lsr #30 8006f66: 4641 mov r1, r8 8006f68: 008a lsls r2, r1, #2 8006f6a: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68 8006f6e: f7f9 f949 bl 8000204 <__aeabi_uldivmod> 8006f72: 4602 mov r2, r0 8006f74: 460b mov r3, r1 8006f76: 4b0d ldr r3, [pc, #52] @ (8006fac ) 8006f78: fba3 1302 umull r1, r3, r3, r2 8006f7c: 095b lsrs r3, r3, #5 8006f7e: 2164 movs r1, #100 @ 0x64 8006f80: fb01 f303 mul.w r3, r1, r3 8006f84: 1ad3 subs r3, r2, r3 8006f86: 011b lsls r3, r3, #4 8006f88: 3332 adds r3, #50 @ 0x32 8006f8a: 4a08 ldr r2, [pc, #32] @ (8006fac ) 8006f8c: fba2 2303 umull r2, r3, r2, r3 8006f90: 095b lsrs r3, r3, #5 8006f92: f003 020f and.w r2, r3, #15 8006f96: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006f9a: 681b ldr r3, [r3, #0] 8006f9c: 4422 add r2, r4 8006f9e: 609a str r2, [r3, #8] } 8006fa0: bf00 nop 8006fa2: f507 7780 add.w r7, r7, #256 @ 0x100 8006fa6: 46bd mov sp, r7 8006fa8: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8006fac: 51eb851f .word 0x51eb851f 08006fb0 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8006fb0: b084 sub sp, #16 8006fb2: b580 push {r7, lr} 8006fb4: b084 sub sp, #16 8006fb6: af00 add r7, sp, #0 8006fb8: 6078 str r0, [r7, #4] 8006fba: f107 001c add.w r0, r7, #28 8006fbe: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8006fc2: f897 3021 ldrb.w r3, [r7, #33] @ 0x21 8006fc6: 2b01 cmp r3, #1 8006fc8: d123 bne.n 8007012 { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8006fca: 687b ldr r3, [r7, #4] 8006fcc: 6b9b ldr r3, [r3, #56] @ 0x38 8006fce: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8006fd2: 687b ldr r3, [r7, #4] 8006fd4: 639a str r2, [r3, #56] @ 0x38 /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); 8006fd6: 687b ldr r3, [r7, #4] 8006fd8: 68db ldr r3, [r3, #12] 8006fda: f423 0384 bic.w r3, r3, #4325376 @ 0x420000 8006fde: f023 0340 bic.w r3, r3, #64 @ 0x40 8006fe2: 687a ldr r2, [r7, #4] 8006fe4: 60d3 str r3, [r2, #12] /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); 8006fe6: 687b ldr r3, [r7, #4] 8006fe8: 68db ldr r3, [r3, #12] 8006fea: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 8006fee: 687b ldr r3, [r7, #4] 8006ff0: 60da str r2, [r3, #12] if (cfg.use_external_vbus == 1U) 8006ff2: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8006ff6: 2b01 cmp r3, #1 8006ff8: d105 bne.n 8007006 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; 8006ffa: 687b ldr r3, [r7, #4] 8006ffc: 68db ldr r3, [r3, #12] 8006ffe: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 8007002: 687b ldr r3, [r7, #4] 8007004: 60da str r2, [r3, #12] } /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8007006: 6878 ldr r0, [r7, #4] 8007008: f001 fae2 bl 80085d0 800700c: 4603 mov r3, r0 800700e: 73fb strb r3, [r7, #15] 8007010: e01b b.n 800704a } else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 8007012: 687b ldr r3, [r7, #4] 8007014: 68db ldr r3, [r3, #12] 8007016: f043 0240 orr.w r2, r3, #64 @ 0x40 800701a: 687b ldr r3, [r7, #4] 800701c: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 800701e: 6878 ldr r0, [r7, #4] 8007020: f001 fad6 bl 80085d0 8007024: 4603 mov r3, r0 8007026: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 8007028: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 800702c: 2b00 cmp r3, #0 800702e: d106 bne.n 800703e { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8007030: 687b ldr r3, [r7, #4] 8007032: 6b9b ldr r3, [r3, #56] @ 0x38 8007034: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8007038: 687b ldr r3, [r7, #4] 800703a: 639a str r2, [r3, #56] @ 0x38 800703c: e005 b.n 800704a } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 800703e: 687b ldr r3, [r7, #4] 8007040: 6b9b ldr r3, [r3, #56] @ 0x38 8007042: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8007046: 687b ldr r3, [r7, #4] 8007048: 639a str r2, [r3, #56] @ 0x38 } } if (cfg.dma_enable == 1U) 800704a: 7fbb ldrb r3, [r7, #30] 800704c: 2b01 cmp r3, #1 800704e: d10b bne.n 8007068 { USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; 8007050: 687b ldr r3, [r7, #4] 8007052: 689b ldr r3, [r3, #8] 8007054: f043 0206 orr.w r2, r3, #6 8007058: 687b ldr r3, [r7, #4] 800705a: 609a str r2, [r3, #8] USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; 800705c: 687b ldr r3, [r7, #4] 800705e: 689b ldr r3, [r3, #8] 8007060: f043 0220 orr.w r2, r3, #32 8007064: 687b ldr r3, [r7, #4] 8007066: 609a str r2, [r3, #8] } return ret; 8007068: 7bfb ldrb r3, [r7, #15] } 800706a: 4618 mov r0, r3 800706c: 3710 adds r7, #16 800706e: 46bd mov sp, r7 8007070: e8bd 4080 ldmia.w sp!, {r7, lr} 8007074: b004 add sp, #16 8007076: 4770 bx lr 08007078 : * @param hclk: AHB clock frequency * @retval USB turnaround time In PHY Clocks number */ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed) { 8007078: b480 push {r7} 800707a: b087 sub sp, #28 800707c: af00 add r7, sp, #0 800707e: 60f8 str r0, [r7, #12] 8007080: 60b9 str r1, [r7, #8] 8007082: 4613 mov r3, r2 8007084: 71fb strb r3, [r7, #7] /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ if (speed == USBD_FS_SPEED) 8007086: 79fb ldrb r3, [r7, #7] 8007088: 2b02 cmp r3, #2 800708a: d165 bne.n 8007158 { if ((hclk >= 14200000U) && (hclk < 15000000U)) 800708c: 68bb ldr r3, [r7, #8] 800708e: 4a41 ldr r2, [pc, #260] @ (8007194 ) 8007090: 4293 cmp r3, r2 8007092: d906 bls.n 80070a2 8007094: 68bb ldr r3, [r7, #8] 8007096: 4a40 ldr r2, [pc, #256] @ (8007198 ) 8007098: 4293 cmp r3, r2 800709a: d202 bcs.n 80070a2 { /* hclk Clock Range between 14.2-15 MHz */ UsbTrd = 0xFU; 800709c: 230f movs r3, #15 800709e: 617b str r3, [r7, #20] 80070a0: e062 b.n 8007168 } else if ((hclk >= 15000000U) && (hclk < 16000000U)) 80070a2: 68bb ldr r3, [r7, #8] 80070a4: 4a3c ldr r2, [pc, #240] @ (8007198 ) 80070a6: 4293 cmp r3, r2 80070a8: d306 bcc.n 80070b8 80070aa: 68bb ldr r3, [r7, #8] 80070ac: 4a3b ldr r2, [pc, #236] @ (800719c ) 80070ae: 4293 cmp r3, r2 80070b0: d202 bcs.n 80070b8 { /* hclk Clock Range between 15-16 MHz */ UsbTrd = 0xEU; 80070b2: 230e movs r3, #14 80070b4: 617b str r3, [r7, #20] 80070b6: e057 b.n 8007168 } else if ((hclk >= 16000000U) && (hclk < 17200000U)) 80070b8: 68bb ldr r3, [r7, #8] 80070ba: 4a38 ldr r2, [pc, #224] @ (800719c ) 80070bc: 4293 cmp r3, r2 80070be: d306 bcc.n 80070ce 80070c0: 68bb ldr r3, [r7, #8] 80070c2: 4a37 ldr r2, [pc, #220] @ (80071a0 ) 80070c4: 4293 cmp r3, r2 80070c6: d202 bcs.n 80070ce { /* hclk Clock Range between 16-17.2 MHz */ UsbTrd = 0xDU; 80070c8: 230d movs r3, #13 80070ca: 617b str r3, [r7, #20] 80070cc: e04c b.n 8007168 } else if ((hclk >= 17200000U) && (hclk < 18500000U)) 80070ce: 68bb ldr r3, [r7, #8] 80070d0: 4a33 ldr r2, [pc, #204] @ (80071a0 ) 80070d2: 4293 cmp r3, r2 80070d4: d306 bcc.n 80070e4 80070d6: 68bb ldr r3, [r7, #8] 80070d8: 4a32 ldr r2, [pc, #200] @ (80071a4 ) 80070da: 4293 cmp r3, r2 80070dc: d802 bhi.n 80070e4 { /* hclk Clock Range between 17.2-18.5 MHz */ UsbTrd = 0xCU; 80070de: 230c movs r3, #12 80070e0: 617b str r3, [r7, #20] 80070e2: e041 b.n 8007168 } else if ((hclk >= 18500000U) && (hclk < 20000000U)) 80070e4: 68bb ldr r3, [r7, #8] 80070e6: 4a2f ldr r2, [pc, #188] @ (80071a4 ) 80070e8: 4293 cmp r3, r2 80070ea: d906 bls.n 80070fa 80070ec: 68bb ldr r3, [r7, #8] 80070ee: 4a2e ldr r2, [pc, #184] @ (80071a8 ) 80070f0: 4293 cmp r3, r2 80070f2: d802 bhi.n 80070fa { /* hclk Clock Range between 18.5-20 MHz */ UsbTrd = 0xBU; 80070f4: 230b movs r3, #11 80070f6: 617b str r3, [r7, #20] 80070f8: e036 b.n 8007168 } else if ((hclk >= 20000000U) && (hclk < 21800000U)) 80070fa: 68bb ldr r3, [r7, #8] 80070fc: 4a2a ldr r2, [pc, #168] @ (80071a8 ) 80070fe: 4293 cmp r3, r2 8007100: d906 bls.n 8007110 8007102: 68bb ldr r3, [r7, #8] 8007104: 4a29 ldr r2, [pc, #164] @ (80071ac ) 8007106: 4293 cmp r3, r2 8007108: d802 bhi.n 8007110 { /* hclk Clock Range between 20-21.8 MHz */ UsbTrd = 0xAU; 800710a: 230a movs r3, #10 800710c: 617b str r3, [r7, #20] 800710e: e02b b.n 8007168 } else if ((hclk >= 21800000U) && (hclk < 24000000U)) 8007110: 68bb ldr r3, [r7, #8] 8007112: 4a26 ldr r2, [pc, #152] @ (80071ac ) 8007114: 4293 cmp r3, r2 8007116: d906 bls.n 8007126 8007118: 68bb ldr r3, [r7, #8] 800711a: 4a25 ldr r2, [pc, #148] @ (80071b0 ) 800711c: 4293 cmp r3, r2 800711e: d202 bcs.n 8007126 { /* hclk Clock Range between 21.8-24 MHz */ UsbTrd = 0x9U; 8007120: 2309 movs r3, #9 8007122: 617b str r3, [r7, #20] 8007124: e020 b.n 8007168 } else if ((hclk >= 24000000U) && (hclk < 27700000U)) 8007126: 68bb ldr r3, [r7, #8] 8007128: 4a21 ldr r2, [pc, #132] @ (80071b0 ) 800712a: 4293 cmp r3, r2 800712c: d306 bcc.n 800713c 800712e: 68bb ldr r3, [r7, #8] 8007130: 4a20 ldr r2, [pc, #128] @ (80071b4 ) 8007132: 4293 cmp r3, r2 8007134: d802 bhi.n 800713c { /* hclk Clock Range between 24-27.7 MHz */ UsbTrd = 0x8U; 8007136: 2308 movs r3, #8 8007138: 617b str r3, [r7, #20] 800713a: e015 b.n 8007168 } else if ((hclk >= 27700000U) && (hclk < 32000000U)) 800713c: 68bb ldr r3, [r7, #8] 800713e: 4a1d ldr r2, [pc, #116] @ (80071b4 ) 8007140: 4293 cmp r3, r2 8007142: d906 bls.n 8007152 8007144: 68bb ldr r3, [r7, #8] 8007146: 4a1c ldr r2, [pc, #112] @ (80071b8 ) 8007148: 4293 cmp r3, r2 800714a: d202 bcs.n 8007152 { /* hclk Clock Range between 27.7-32 MHz */ UsbTrd = 0x7U; 800714c: 2307 movs r3, #7 800714e: 617b str r3, [r7, #20] 8007150: e00a b.n 8007168 } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ UsbTrd = 0x6U; 8007152: 2306 movs r3, #6 8007154: 617b str r3, [r7, #20] 8007156: e007 b.n 8007168 } } else if (speed == USBD_HS_SPEED) 8007158: 79fb ldrb r3, [r7, #7] 800715a: 2b00 cmp r3, #0 800715c: d102 bne.n 8007164 { UsbTrd = USBD_HS_TRDT_VALUE; 800715e: 2309 movs r3, #9 8007160: 617b str r3, [r7, #20] 8007162: e001 b.n 8007168 } else { UsbTrd = USBD_DEFAULT_TRDT_VALUE; 8007164: 2309 movs r3, #9 8007166: 617b str r3, [r7, #20] } USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; 8007168: 68fb ldr r3, [r7, #12] 800716a: 68db ldr r3, [r3, #12] 800716c: f423 5270 bic.w r2, r3, #15360 @ 0x3c00 8007170: 68fb ldr r3, [r7, #12] 8007172: 60da str r2, [r3, #12] USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); 8007174: 68fb ldr r3, [r7, #12] 8007176: 68da ldr r2, [r3, #12] 8007178: 697b ldr r3, [r7, #20] 800717a: 029b lsls r3, r3, #10 800717c: f403 5370 and.w r3, r3, #15360 @ 0x3c00 8007180: 431a orrs r2, r3 8007182: 68fb ldr r3, [r7, #12] 8007184: 60da str r2, [r3, #12] return HAL_OK; 8007186: 2300 movs r3, #0 } 8007188: 4618 mov r0, r3 800718a: 371c adds r7, #28 800718c: 46bd mov sp, r7 800718e: f85d 7b04 ldr.w r7, [sp], #4 8007192: 4770 bx lr 8007194: 00d8acbf .word 0x00d8acbf 8007198: 00e4e1c0 .word 0x00e4e1c0 800719c: 00f42400 .word 0x00f42400 80071a0: 01067380 .word 0x01067380 80071a4: 011a499f .word 0x011a499f 80071a8: 01312cff .word 0x01312cff 80071ac: 014ca43f .word 0x014ca43f 80071b0: 016e3600 .word 0x016e3600 80071b4: 01a6ab1f .word 0x01a6ab1f 80071b8: 01e84800 .word 0x01e84800 080071bc : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 80071bc: b480 push {r7} 80071be: b083 sub sp, #12 80071c0: af00 add r7, sp, #0 80071c2: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 80071c4: 687b ldr r3, [r7, #4] 80071c6: 689b ldr r3, [r3, #8] 80071c8: f043 0201 orr.w r2, r3, #1 80071cc: 687b ldr r3, [r7, #4] 80071ce: 609a str r2, [r3, #8] return HAL_OK; 80071d0: 2300 movs r3, #0 } 80071d2: 4618 mov r0, r3 80071d4: 370c adds r7, #12 80071d6: 46bd mov sp, r7 80071d8: f85d 7b04 ldr.w r7, [sp], #4 80071dc: 4770 bx lr 080071de : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 80071de: b480 push {r7} 80071e0: b083 sub sp, #12 80071e2: af00 add r7, sp, #0 80071e4: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 80071e6: 687b ldr r3, [r7, #4] 80071e8: 689b ldr r3, [r3, #8] 80071ea: f023 0201 bic.w r2, r3, #1 80071ee: 687b ldr r3, [r7, #4] 80071f0: 609a str r2, [r3, #8] return HAL_OK; 80071f2: 2300 movs r3, #0 } 80071f4: 4618 mov r0, r3 80071f6: 370c adds r7, #12 80071f8: 46bd mov sp, r7 80071fa: f85d 7b04 ldr.w r7, [sp], #4 80071fe: 4770 bx lr 08007200 : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { 8007200: b580 push {r7, lr} 8007202: b084 sub sp, #16 8007204: af00 add r7, sp, #0 8007206: 6078 str r0, [r7, #4] 8007208: 460b mov r3, r1 800720a: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 800720c: 2300 movs r3, #0 800720e: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 8007210: 687b ldr r3, [r7, #4] 8007212: 68db ldr r3, [r3, #12] 8007214: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000 8007218: 687b ldr r3, [r7, #4] 800721a: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 800721c: 78fb ldrb r3, [r7, #3] 800721e: 2b01 cmp r3, #1 8007220: d115 bne.n 800724e { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 8007222: 687b ldr r3, [r7, #4] 8007224: 68db ldr r3, [r3, #12] 8007226: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 800722a: 687b ldr r3, [r7, #4] 800722c: 60da str r2, [r3, #12] do { HAL_Delay(10U); 800722e: 200a movs r0, #10 8007230: f7fa fbd6 bl 80019e0 ms += 10U; 8007234: 68fb ldr r3, [r7, #12] 8007236: 330a adds r3, #10 8007238: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 800723a: 6878 ldr r0, [r7, #4] 800723c: f001 f939 bl 80084b2 8007240: 4603 mov r3, r0 8007242: 2b01 cmp r3, #1 8007244: d01e beq.n 8007284 8007246: 68fb ldr r3, [r7, #12] 8007248: 2bc7 cmp r3, #199 @ 0xc7 800724a: d9f0 bls.n 800722e 800724c: e01a b.n 8007284 } else if (mode == USB_DEVICE_MODE) 800724e: 78fb ldrb r3, [r7, #3] 8007250: 2b00 cmp r3, #0 8007252: d115 bne.n 8007280 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 8007254: 687b ldr r3, [r7, #4] 8007256: 68db ldr r3, [r3, #12] 8007258: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000 800725c: 687b ldr r3, [r7, #4] 800725e: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8007260: 200a movs r0, #10 8007262: f7fa fbbd bl 80019e0 ms += 10U; 8007266: 68fb ldr r3, [r7, #12] 8007268: 330a adds r3, #10 800726a: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 800726c: 6878 ldr r0, [r7, #4] 800726e: f001 f920 bl 80084b2 8007272: 4603 mov r3, r0 8007274: 2b00 cmp r3, #0 8007276: d005 beq.n 8007284 8007278: 68fb ldr r3, [r7, #12] 800727a: 2bc7 cmp r3, #199 @ 0xc7 800727c: d9f0 bls.n 8007260 800727e: e001 b.n 8007284 } else { return HAL_ERROR; 8007280: 2301 movs r3, #1 8007282: e005 b.n 8007290 } if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) 8007284: 68fb ldr r3, [r7, #12] 8007286: 2bc8 cmp r3, #200 @ 0xc8 8007288: d101 bne.n 800728e { return HAL_ERROR; 800728a: 2301 movs r3, #1 800728c: e000 b.n 8007290 } return HAL_OK; 800728e: 2300 movs r3, #0 } 8007290: 4618 mov r0, r3 8007292: 3710 adds r7, #16 8007294: 46bd mov sp, r7 8007296: bd80 pop {r7, pc} 08007298 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8007298: b084 sub sp, #16 800729a: b580 push {r7, lr} 800729c: b086 sub sp, #24 800729e: af00 add r7, sp, #0 80072a0: 6078 str r0, [r7, #4] 80072a2: f107 0024 add.w r0, r7, #36 @ 0x24 80072a6: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 80072aa: 2300 movs r3, #0 80072ac: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 80072ae: 687b ldr r3, [r7, #4] 80072b0: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 80072b2: 2300 movs r3, #0 80072b4: 613b str r3, [r7, #16] 80072b6: e009 b.n 80072cc { USBx->DIEPTXF[i] = 0U; 80072b8: 687a ldr r2, [r7, #4] 80072ba: 693b ldr r3, [r7, #16] 80072bc: 3340 adds r3, #64 @ 0x40 80072be: 009b lsls r3, r3, #2 80072c0: 4413 add r3, r2 80072c2: 2200 movs r2, #0 80072c4: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 80072c6: 693b ldr r3, [r7, #16] 80072c8: 3301 adds r3, #1 80072ca: 613b str r3, [r7, #16] 80072cc: 693b ldr r3, [r7, #16] 80072ce: 2b0e cmp r3, #14 80072d0: d9f2 bls.n 80072b8 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 80072d2: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 80072d6: 2b00 cmp r3, #0 80072d8: d11c bne.n 8007314 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 80072da: 68fb ldr r3, [r7, #12] 80072dc: f503 6300 add.w r3, r3, #2048 @ 0x800 80072e0: 685b ldr r3, [r3, #4] 80072e2: 68fa ldr r2, [r7, #12] 80072e4: f502 6200 add.w r2, r2, #2048 @ 0x800 80072e8: f043 0302 orr.w r3, r3, #2 80072ec: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 80072ee: 687b ldr r3, [r7, #4] 80072f0: 6b9b ldr r3, [r3, #56] @ 0x38 80072f2: f423 1200 bic.w r2, r3, #2097152 @ 0x200000 80072f6: 687b ldr r3, [r7, #4] 80072f8: 639a str r2, [r3, #56] @ 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 80072fa: 687b ldr r3, [r7, #4] 80072fc: 681b ldr r3, [r3, #0] 80072fe: f043 0240 orr.w r2, r3, #64 @ 0x40 8007302: 687b ldr r3, [r7, #4] 8007304: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 8007306: 687b ldr r3, [r7, #4] 8007308: 681b ldr r3, [r3, #0] 800730a: f043 0280 orr.w r2, r3, #128 @ 0x80 800730e: 687b ldr r3, [r7, #4] 8007310: 601a str r2, [r3, #0] 8007312: e005 b.n 8007320 } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 8007314: 687b ldr r3, [r7, #4] 8007316: 6b9b ldr r3, [r3, #56] @ 0x38 8007318: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 800731c: 687b ldr r3, [r7, #4] 800731e: 639a str r2, [r3, #56] @ 0x38 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 8007320: 68fb ldr r3, [r7, #12] 8007322: f503 6360 add.w r3, r3, #3584 @ 0xe00 8007326: 461a mov r2, r3 8007328: 2300 movs r3, #0 800732a: 6013 str r3, [r2, #0] if (cfg.phy_itface == USB_OTG_ULPI_PHY) 800732c: f897 3029 ldrb.w r3, [r7, #41] @ 0x29 8007330: 2b01 cmp r3, #1 8007332: d10d bne.n 8007350 { if (cfg.speed == USBD_HS_SPEED) 8007334: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8007338: 2b00 cmp r3, #0 800733a: d104 bne.n 8007346 { /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); 800733c: 2100 movs r1, #0 800733e: 6878 ldr r0, [r7, #4] 8007340: f000 f968 bl 8007614 8007344: e008 b.n 8007358 } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); 8007346: 2101 movs r1, #1 8007348: 6878 ldr r0, [r7, #4] 800734a: f000 f963 bl 8007614 800734e: e003 b.n 8007358 } } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 8007350: 2103 movs r1, #3 8007352: 6878 ldr r0, [r7, #4] 8007354: f000 f95e bl 8007614 } /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 8007358: 2110 movs r1, #16 800735a: 6878 ldr r0, [r7, #4] 800735c: f000 f8fa bl 8007554 8007360: 4603 mov r3, r0 8007362: 2b00 cmp r3, #0 8007364: d001 beq.n 800736a { ret = HAL_ERROR; 8007366: 2301 movs r3, #1 8007368: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 800736a: 6878 ldr r0, [r7, #4] 800736c: f000 f924 bl 80075b8 8007370: 4603 mov r3, r0 8007372: 2b00 cmp r3, #0 8007374: d001 beq.n 800737a { ret = HAL_ERROR; 8007376: 2301 movs r3, #1 8007378: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 800737a: 68fb ldr r3, [r7, #12] 800737c: f503 6300 add.w r3, r3, #2048 @ 0x800 8007380: 461a mov r2, r3 8007382: 2300 movs r3, #0 8007384: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 8007386: 68fb ldr r3, [r7, #12] 8007388: f503 6300 add.w r3, r3, #2048 @ 0x800 800738c: 461a mov r2, r3 800738e: 2300 movs r3, #0 8007390: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 8007392: 68fb ldr r3, [r7, #12] 8007394: f503 6300 add.w r3, r3, #2048 @ 0x800 8007398: 461a mov r2, r3 800739a: 2300 movs r3, #0 800739c: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 800739e: 2300 movs r3, #0 80073a0: 613b str r3, [r7, #16] 80073a2: e043 b.n 800742c { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 80073a4: 693b ldr r3, [r7, #16] 80073a6: 015a lsls r2, r3, #5 80073a8: 68fb ldr r3, [r7, #12] 80073aa: 4413 add r3, r2 80073ac: f503 6310 add.w r3, r3, #2304 @ 0x900 80073b0: 681b ldr r3, [r3, #0] 80073b2: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80073b6: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80073ba: d118 bne.n 80073ee { if (i == 0U) 80073bc: 693b ldr r3, [r7, #16] 80073be: 2b00 cmp r3, #0 80073c0: d10a bne.n 80073d8 { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 80073c2: 693b ldr r3, [r7, #16] 80073c4: 015a lsls r2, r3, #5 80073c6: 68fb ldr r3, [r7, #12] 80073c8: 4413 add r3, r2 80073ca: f503 6310 add.w r3, r3, #2304 @ 0x900 80073ce: 461a mov r2, r3 80073d0: f04f 6300 mov.w r3, #134217728 @ 0x8000000 80073d4: 6013 str r3, [r2, #0] 80073d6: e013 b.n 8007400 } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 80073d8: 693b ldr r3, [r7, #16] 80073da: 015a lsls r2, r3, #5 80073dc: 68fb ldr r3, [r7, #12] 80073de: 4413 add r3, r2 80073e0: f503 6310 add.w r3, r3, #2304 @ 0x900 80073e4: 461a mov r2, r3 80073e6: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 80073ea: 6013 str r3, [r2, #0] 80073ec: e008 b.n 8007400 } } else { USBx_INEP(i)->DIEPCTL = 0U; 80073ee: 693b ldr r3, [r7, #16] 80073f0: 015a lsls r2, r3, #5 80073f2: 68fb ldr r3, [r7, #12] 80073f4: 4413 add r3, r2 80073f6: f503 6310 add.w r3, r3, #2304 @ 0x900 80073fa: 461a mov r2, r3 80073fc: 2300 movs r3, #0 80073fe: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 8007400: 693b ldr r3, [r7, #16] 8007402: 015a lsls r2, r3, #5 8007404: 68fb ldr r3, [r7, #12] 8007406: 4413 add r3, r2 8007408: f503 6310 add.w r3, r3, #2304 @ 0x900 800740c: 461a mov r2, r3 800740e: 2300 movs r3, #0 8007410: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 8007412: 693b ldr r3, [r7, #16] 8007414: 015a lsls r2, r3, #5 8007416: 68fb ldr r3, [r7, #12] 8007418: 4413 add r3, r2 800741a: f503 6310 add.w r3, r3, #2304 @ 0x900 800741e: 461a mov r2, r3 8007420: f64f 337f movw r3, #64383 @ 0xfb7f 8007424: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8007426: 693b ldr r3, [r7, #16] 8007428: 3301 adds r3, #1 800742a: 613b str r3, [r7, #16] 800742c: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8007430: 461a mov r2, r3 8007432: 693b ldr r3, [r7, #16] 8007434: 4293 cmp r3, r2 8007436: d3b5 bcc.n 80073a4 } for (i = 0U; i < cfg.dev_endpoints; i++) 8007438: 2300 movs r3, #0 800743a: 613b str r3, [r7, #16] 800743c: e043 b.n 80074c6 { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 800743e: 693b ldr r3, [r7, #16] 8007440: 015a lsls r2, r3, #5 8007442: 68fb ldr r3, [r7, #12] 8007444: 4413 add r3, r2 8007446: f503 6330 add.w r3, r3, #2816 @ 0xb00 800744a: 681b ldr r3, [r3, #0] 800744c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007450: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007454: d118 bne.n 8007488 { if (i == 0U) 8007456: 693b ldr r3, [r7, #16] 8007458: 2b00 cmp r3, #0 800745a: d10a bne.n 8007472 { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 800745c: 693b ldr r3, [r7, #16] 800745e: 015a lsls r2, r3, #5 8007460: 68fb ldr r3, [r7, #12] 8007462: 4413 add r3, r2 8007464: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007468: 461a mov r2, r3 800746a: f04f 6300 mov.w r3, #134217728 @ 0x8000000 800746e: 6013 str r3, [r2, #0] 8007470: e013 b.n 800749a } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 8007472: 693b ldr r3, [r7, #16] 8007474: 015a lsls r2, r3, #5 8007476: 68fb ldr r3, [r7, #12] 8007478: 4413 add r3, r2 800747a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800747e: 461a mov r2, r3 8007480: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 8007484: 6013 str r3, [r2, #0] 8007486: e008 b.n 800749a } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 8007488: 693b ldr r3, [r7, #16] 800748a: 015a lsls r2, r3, #5 800748c: 68fb ldr r3, [r7, #12] 800748e: 4413 add r3, r2 8007490: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007494: 461a mov r2, r3 8007496: 2300 movs r3, #0 8007498: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 800749a: 693b ldr r3, [r7, #16] 800749c: 015a lsls r2, r3, #5 800749e: 68fb ldr r3, [r7, #12] 80074a0: 4413 add r3, r2 80074a2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80074a6: 461a mov r2, r3 80074a8: 2300 movs r3, #0 80074aa: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 80074ac: 693b ldr r3, [r7, #16] 80074ae: 015a lsls r2, r3, #5 80074b0: 68fb ldr r3, [r7, #12] 80074b2: 4413 add r3, r2 80074b4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80074b8: 461a mov r2, r3 80074ba: f64f 337f movw r3, #64383 @ 0xfb7f 80074be: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 80074c0: 693b ldr r3, [r7, #16] 80074c2: 3301 adds r3, #1 80074c4: 613b str r3, [r7, #16] 80074c6: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 80074ca: 461a mov r2, r3 80074cc: 693b ldr r3, [r7, #16] 80074ce: 4293 cmp r3, r2 80074d0: d3b5 bcc.n 800743e } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 80074d2: 68fb ldr r3, [r7, #12] 80074d4: f503 6300 add.w r3, r3, #2048 @ 0x800 80074d8: 691b ldr r3, [r3, #16] 80074da: 68fa ldr r2, [r7, #12] 80074dc: f502 6200 add.w r2, r2, #2048 @ 0x800 80074e0: f423 7380 bic.w r3, r3, #256 @ 0x100 80074e4: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 80074e6: 687b ldr r3, [r7, #4] 80074e8: 2200 movs r2, #0 80074ea: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 80074ec: 687b ldr r3, [r7, #4] 80074ee: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000 80074f2: 615a str r2, [r3, #20] /* Enable the common interrupts */ if (cfg.dma_enable == 0U) 80074f4: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 80074f8: 2b00 cmp r3, #0 80074fa: d105 bne.n 8007508 { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 80074fc: 687b ldr r3, [r7, #4] 80074fe: 699b ldr r3, [r3, #24] 8007500: f043 0210 orr.w r2, r3, #16 8007504: 687b ldr r3, [r7, #4] 8007506: 619a str r2, [r3, #24] } /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 8007508: 687b ldr r3, [r7, #4] 800750a: 699a ldr r2, [r3, #24] 800750c: 4b10 ldr r3, [pc, #64] @ (8007550 ) 800750e: 4313 orrs r3, r2 8007510: 687a ldr r2, [r7, #4] 8007512: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 8007514: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 8007518: 2b00 cmp r3, #0 800751a: d005 beq.n 8007528 { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 800751c: 687b ldr r3, [r7, #4] 800751e: 699b ldr r3, [r3, #24] 8007520: f043 0208 orr.w r2, r3, #8 8007524: 687b ldr r3, [r7, #4] 8007526: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 8007528: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800752c: 2b01 cmp r3, #1 800752e: d107 bne.n 8007540 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 8007530: 687b ldr r3, [r7, #4] 8007532: 699b ldr r3, [r3, #24] 8007534: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007538: f043 0304 orr.w r3, r3, #4 800753c: 687a ldr r2, [r7, #4] 800753e: 6193 str r3, [r2, #24] } return ret; 8007540: 7dfb ldrb r3, [r7, #23] } 8007542: 4618 mov r0, r3 8007544: 3718 adds r7, #24 8007546: 46bd mov sp, r7 8007548: e8bd 4080 ldmia.w sp!, {r7, lr} 800754c: b004 add sp, #16 800754e: 4770 bx lr 8007550: 803c3800 .word 0x803c3800 08007554 : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 8007554: b480 push {r7} 8007556: b085 sub sp, #20 8007558: af00 add r7, sp, #0 800755a: 6078 str r0, [r7, #4] 800755c: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 800755e: 2300 movs r3, #0 8007560: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8007562: 68fb ldr r3, [r7, #12] 8007564: 3301 adds r3, #1 8007566: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007568: 68fb ldr r3, [r7, #12] 800756a: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 800756e: d901 bls.n 8007574 { return HAL_TIMEOUT; 8007570: 2303 movs r3, #3 8007572: e01b b.n 80075ac } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8007574: 687b ldr r3, [r7, #4] 8007576: 691b ldr r3, [r3, #16] 8007578: 2b00 cmp r3, #0 800757a: daf2 bge.n 8007562 /* Flush TX Fifo */ count = 0U; 800757c: 2300 movs r3, #0 800757e: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 8007580: 683b ldr r3, [r7, #0] 8007582: 019b lsls r3, r3, #6 8007584: f043 0220 orr.w r2, r3, #32 8007588: 687b ldr r3, [r7, #4] 800758a: 611a str r2, [r3, #16] do { count++; 800758c: 68fb ldr r3, [r7, #12] 800758e: 3301 adds r3, #1 8007590: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007592: 68fb ldr r3, [r7, #12] 8007594: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007598: d901 bls.n 800759e { return HAL_TIMEOUT; 800759a: 2303 movs r3, #3 800759c: e006 b.n 80075ac } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 800759e: 687b ldr r3, [r7, #4] 80075a0: 691b ldr r3, [r3, #16] 80075a2: f003 0320 and.w r3, r3, #32 80075a6: 2b20 cmp r3, #32 80075a8: d0f0 beq.n 800758c return HAL_OK; 80075aa: 2300 movs r3, #0 } 80075ac: 4618 mov r0, r3 80075ae: 3714 adds r7, #20 80075b0: 46bd mov sp, r7 80075b2: f85d 7b04 ldr.w r7, [sp], #4 80075b6: 4770 bx lr 080075b8 : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 80075b8: b480 push {r7} 80075ba: b085 sub sp, #20 80075bc: af00 add r7, sp, #0 80075be: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 80075c0: 2300 movs r3, #0 80075c2: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 80075c4: 68fb ldr r3, [r7, #12] 80075c6: 3301 adds r3, #1 80075c8: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80075ca: 68fb ldr r3, [r7, #12] 80075cc: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80075d0: d901 bls.n 80075d6 { return HAL_TIMEOUT; 80075d2: 2303 movs r3, #3 80075d4: e018 b.n 8007608 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 80075d6: 687b ldr r3, [r7, #4] 80075d8: 691b ldr r3, [r3, #16] 80075da: 2b00 cmp r3, #0 80075dc: daf2 bge.n 80075c4 /* Flush RX Fifo */ count = 0U; 80075de: 2300 movs r3, #0 80075e0: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 80075e2: 687b ldr r3, [r7, #4] 80075e4: 2210 movs r2, #16 80075e6: 611a str r2, [r3, #16] do { count++; 80075e8: 68fb ldr r3, [r7, #12] 80075ea: 3301 adds r3, #1 80075ec: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80075ee: 68fb ldr r3, [r7, #12] 80075f0: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80075f4: d901 bls.n 80075fa { return HAL_TIMEOUT; 80075f6: 2303 movs r3, #3 80075f8: e006 b.n 8007608 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 80075fa: 687b ldr r3, [r7, #4] 80075fc: 691b ldr r3, [r3, #16] 80075fe: f003 0310 and.w r3, r3, #16 8007602: 2b10 cmp r3, #16 8007604: d0f0 beq.n 80075e8 return HAL_OK; 8007606: 2300 movs r3, #0 } 8007608: 4618 mov r0, r3 800760a: 3714 adds r7, #20 800760c: 46bd mov sp, r7 800760e: f85d 7b04 ldr.w r7, [sp], #4 8007612: 4770 bx lr 08007614 : * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 8007614: b480 push {r7} 8007616: b085 sub sp, #20 8007618: af00 add r7, sp, #0 800761a: 6078 str r0, [r7, #4] 800761c: 460b mov r3, r1 800761e: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8007620: 687b ldr r3, [r7, #4] 8007622: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 8007624: 68fb ldr r3, [r7, #12] 8007626: f503 6300 add.w r3, r3, #2048 @ 0x800 800762a: 681a ldr r2, [r3, #0] 800762c: 78fb ldrb r3, [r7, #3] 800762e: 68f9 ldr r1, [r7, #12] 8007630: f501 6100 add.w r1, r1, #2048 @ 0x800 8007634: 4313 orrs r3, r2 8007636: 600b str r3, [r1, #0] return HAL_OK; 8007638: 2300 movs r3, #0 } 800763a: 4618 mov r0, r3 800763c: 3714 adds r7, #20 800763e: 46bd mov sp, r7 8007640: f85d 7b04 ldr.w r7, [sp], #4 8007644: 4770 bx lr 08007646 : * This parameter can be one of these values: * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { 8007646: b480 push {r7} 8007648: b087 sub sp, #28 800764a: af00 add r7, sp, #0 800764c: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800764e: 687b ldr r3, [r7, #4] 8007650: 613b str r3, [r7, #16] uint8_t speed; uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; 8007652: 693b ldr r3, [r7, #16] 8007654: f503 6300 add.w r3, r3, #2048 @ 0x800 8007658: 689b ldr r3, [r3, #8] 800765a: f003 0306 and.w r3, r3, #6 800765e: 60fb str r3, [r7, #12] if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 8007660: 68fb ldr r3, [r7, #12] 8007662: 2b00 cmp r3, #0 8007664: d102 bne.n 800766c { speed = USBD_HS_SPEED; 8007666: 2300 movs r3, #0 8007668: 75fb strb r3, [r7, #23] 800766a: e00a b.n 8007682 } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || 800766c: 68fb ldr r3, [r7, #12] 800766e: 2b02 cmp r3, #2 8007670: d002 beq.n 8007678 8007672: 68fb ldr r3, [r7, #12] 8007674: 2b06 cmp r3, #6 8007676: d102 bne.n 800767e (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USBD_FS_SPEED; 8007678: 2302 movs r3, #2 800767a: 75fb strb r3, [r7, #23] 800767c: e001 b.n 8007682 } else { speed = 0xFU; 800767e: 230f movs r3, #15 8007680: 75fb strb r3, [r7, #23] } return speed; 8007682: 7dfb ldrb r3, [r7, #23] } 8007684: 4618 mov r0, r3 8007686: 371c adds r7, #28 8007688: 46bd mov sp, r7 800768a: f85d 7b04 ldr.w r7, [sp], #4 800768e: 4770 bx lr 08007690 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007690: b480 push {r7} 8007692: b085 sub sp, #20 8007694: af00 add r7, sp, #0 8007696: 6078 str r0, [r7, #4] 8007698: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800769a: 687b ldr r3, [r7, #4] 800769c: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 800769e: 683b ldr r3, [r7, #0] 80076a0: 781b ldrb r3, [r3, #0] 80076a2: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 80076a4: 683b ldr r3, [r7, #0] 80076a6: 785b ldrb r3, [r3, #1] 80076a8: 2b01 cmp r3, #1 80076aa: d13a bne.n 8007722 { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); 80076ac: 68fb ldr r3, [r7, #12] 80076ae: f503 6300 add.w r3, r3, #2048 @ 0x800 80076b2: 69da ldr r2, [r3, #28] 80076b4: 683b ldr r3, [r7, #0] 80076b6: 781b ldrb r3, [r3, #0] 80076b8: f003 030f and.w r3, r3, #15 80076bc: 2101 movs r1, #1 80076be: fa01 f303 lsl.w r3, r1, r3 80076c2: b29b uxth r3, r3 80076c4: 68f9 ldr r1, [r7, #12] 80076c6: f501 6100 add.w r1, r1, #2048 @ 0x800 80076ca: 4313 orrs r3, r2 80076cc: 61cb str r3, [r1, #28] if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) 80076ce: 68bb ldr r3, [r7, #8] 80076d0: 015a lsls r2, r3, #5 80076d2: 68fb ldr r3, [r7, #12] 80076d4: 4413 add r3, r2 80076d6: f503 6310 add.w r3, r3, #2304 @ 0x900 80076da: 681b ldr r3, [r3, #0] 80076dc: f403 4300 and.w r3, r3, #32768 @ 0x8000 80076e0: 2b00 cmp r3, #0 80076e2: d155 bne.n 8007790 { USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 80076e4: 68bb ldr r3, [r7, #8] 80076e6: 015a lsls r2, r3, #5 80076e8: 68fb ldr r3, [r7, #12] 80076ea: 4413 add r3, r2 80076ec: f503 6310 add.w r3, r3, #2304 @ 0x900 80076f0: 681a ldr r2, [r3, #0] 80076f2: 683b ldr r3, [r7, #0] 80076f4: 689b ldr r3, [r3, #8] 80076f6: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | (epnum << 22) | 80076fa: 683b ldr r3, [r7, #0] 80076fc: 791b ldrb r3, [r3, #4] 80076fe: 049b lsls r3, r3, #18 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8007700: 4319 orrs r1, r3 ((uint32_t)ep->type << 18) | (epnum << 22) | 8007702: 68bb ldr r3, [r7, #8] 8007704: 059b lsls r3, r3, #22 8007706: 430b orrs r3, r1 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8007708: 4313 orrs r3, r2 800770a: 68ba ldr r2, [r7, #8] 800770c: 0151 lsls r1, r2, #5 800770e: 68fa ldr r2, [r7, #12] 8007710: 440a add r2, r1 8007712: f502 6210 add.w r2, r2, #2304 @ 0x900 8007716: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800771a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800771e: 6013 str r3, [r2, #0] 8007720: e036 b.n 8007790 USB_OTG_DIEPCTL_USBAEP; } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); 8007722: 68fb ldr r3, [r7, #12] 8007724: f503 6300 add.w r3, r3, #2048 @ 0x800 8007728: 69da ldr r2, [r3, #28] 800772a: 683b ldr r3, [r7, #0] 800772c: 781b ldrb r3, [r3, #0] 800772e: f003 030f and.w r3, r3, #15 8007732: 2101 movs r1, #1 8007734: fa01 f303 lsl.w r3, r1, r3 8007738: 041b lsls r3, r3, #16 800773a: 68f9 ldr r1, [r7, #12] 800773c: f501 6100 add.w r1, r1, #2048 @ 0x800 8007740: 4313 orrs r3, r2 8007742: 61cb str r3, [r1, #28] if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) 8007744: 68bb ldr r3, [r7, #8] 8007746: 015a lsls r2, r3, #5 8007748: 68fb ldr r3, [r7, #12] 800774a: 4413 add r3, r2 800774c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007750: 681b ldr r3, [r3, #0] 8007752: f403 4300 and.w r3, r3, #32768 @ 0x8000 8007756: 2b00 cmp r3, #0 8007758: d11a bne.n 8007790 { USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 800775a: 68bb ldr r3, [r7, #8] 800775c: 015a lsls r2, r3, #5 800775e: 68fb ldr r3, [r7, #12] 8007760: 4413 add r3, r2 8007762: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007766: 681a ldr r2, [r3, #0] 8007768: 683b ldr r3, [r7, #0] 800776a: 689b ldr r3, [r3, #8] 800776c: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | 8007770: 683b ldr r3, [r7, #0] 8007772: 791b ldrb r3, [r3, #4] 8007774: 049b lsls r3, r3, #18 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 8007776: 430b orrs r3, r1 8007778: 4313 orrs r3, r2 800777a: 68ba ldr r2, [r7, #8] 800777c: 0151 lsls r1, r2, #5 800777e: 68fa ldr r2, [r7, #12] 8007780: 440a add r2, r1 8007782: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007786: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800778a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800778e: 6013 str r3, [r2, #0] USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; 8007790: 2300 movs r3, #0 } 8007792: 4618 mov r0, r3 8007794: 3714 adds r7, #20 8007796: 46bd mov sp, r7 8007798: f85d 7b04 ldr.w r7, [sp], #4 800779c: 4770 bx lr ... 080077a0 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 80077a0: b480 push {r7} 80077a2: b085 sub sp, #20 80077a4: af00 add r7, sp, #0 80077a6: 6078 str r0, [r7, #4] 80077a8: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80077aa: 687b ldr r3, [r7, #4] 80077ac: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80077ae: 683b ldr r3, [r7, #0] 80077b0: 781b ldrb r3, [r3, #0] 80077b2: 60bb str r3, [r7, #8] /* Read DEPCTLn register */ if (ep->is_in == 1U) 80077b4: 683b ldr r3, [r7, #0] 80077b6: 785b ldrb r3, [r3, #1] 80077b8: 2b01 cmp r3, #1 80077ba: d161 bne.n 8007880 { if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 80077bc: 68bb ldr r3, [r7, #8] 80077be: 015a lsls r2, r3, #5 80077c0: 68fb ldr r3, [r7, #12] 80077c2: 4413 add r3, r2 80077c4: f503 6310 add.w r3, r3, #2304 @ 0x900 80077c8: 681b ldr r3, [r3, #0] 80077ca: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80077ce: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80077d2: d11f bne.n 8007814 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 80077d4: 68bb ldr r3, [r7, #8] 80077d6: 015a lsls r2, r3, #5 80077d8: 68fb ldr r3, [r7, #12] 80077da: 4413 add r3, r2 80077dc: f503 6310 add.w r3, r3, #2304 @ 0x900 80077e0: 681b ldr r3, [r3, #0] 80077e2: 68ba ldr r2, [r7, #8] 80077e4: 0151 lsls r1, r2, #5 80077e6: 68fa ldr r2, [r7, #12] 80077e8: 440a add r2, r1 80077ea: f502 6210 add.w r2, r2, #2304 @ 0x900 80077ee: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 80077f2: 6013 str r3, [r2, #0] USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; 80077f4: 68bb ldr r3, [r7, #8] 80077f6: 015a lsls r2, r3, #5 80077f8: 68fb ldr r3, [r7, #12] 80077fa: 4413 add r3, r2 80077fc: f503 6310 add.w r3, r3, #2304 @ 0x900 8007800: 681b ldr r3, [r3, #0] 8007802: 68ba ldr r2, [r7, #8] 8007804: 0151 lsls r1, r2, #5 8007806: 68fa ldr r2, [r7, #12] 8007808: 440a add r2, r1 800780a: f502 6210 add.w r2, r2, #2304 @ 0x900 800780e: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007812: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 8007814: 68fb ldr r3, [r7, #12] 8007816: f503 6300 add.w r3, r3, #2048 @ 0x800 800781a: 6bda ldr r2, [r3, #60] @ 0x3c 800781c: 683b ldr r3, [r7, #0] 800781e: 781b ldrb r3, [r3, #0] 8007820: f003 030f and.w r3, r3, #15 8007824: 2101 movs r1, #1 8007826: fa01 f303 lsl.w r3, r1, r3 800782a: b29b uxth r3, r3 800782c: 43db mvns r3, r3 800782e: 68f9 ldr r1, [r7, #12] 8007830: f501 6100 add.w r1, r1, #2048 @ 0x800 8007834: 4013 ands r3, r2 8007836: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 8007838: 68fb ldr r3, [r7, #12] 800783a: f503 6300 add.w r3, r3, #2048 @ 0x800 800783e: 69da ldr r2, [r3, #28] 8007840: 683b ldr r3, [r7, #0] 8007842: 781b ldrb r3, [r3, #0] 8007844: f003 030f and.w r3, r3, #15 8007848: 2101 movs r1, #1 800784a: fa01 f303 lsl.w r3, r1, r3 800784e: b29b uxth r3, r3 8007850: 43db mvns r3, r3 8007852: 68f9 ldr r1, [r7, #12] 8007854: f501 6100 add.w r1, r1, #2048 @ 0x800 8007858: 4013 ands r3, r2 800785a: 61cb str r3, [r1, #28] USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | 800785c: 68bb ldr r3, [r7, #8] 800785e: 015a lsls r2, r3, #5 8007860: 68fb ldr r3, [r7, #12] 8007862: 4413 add r3, r2 8007864: f503 6310 add.w r3, r3, #2304 @ 0x900 8007868: 681a ldr r2, [r3, #0] 800786a: 68bb ldr r3, [r7, #8] 800786c: 0159 lsls r1, r3, #5 800786e: 68fb ldr r3, [r7, #12] 8007870: 440b add r3, r1 8007872: f503 6310 add.w r3, r3, #2304 @ 0x900 8007876: 4619 mov r1, r3 8007878: 4b35 ldr r3, [pc, #212] @ (8007950 ) 800787a: 4013 ands r3, r2 800787c: 600b str r3, [r1, #0] 800787e: e060 b.n 8007942 USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_EPTYP); } else { if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007880: 68bb ldr r3, [r7, #8] 8007882: 015a lsls r2, r3, #5 8007884: 68fb ldr r3, [r7, #12] 8007886: 4413 add r3, r2 8007888: f503 6330 add.w r3, r3, #2816 @ 0xb00 800788c: 681b ldr r3, [r3, #0] 800788e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007892: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007896: d11f bne.n 80078d8 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 8007898: 68bb ldr r3, [r7, #8] 800789a: 015a lsls r2, r3, #5 800789c: 68fb ldr r3, [r7, #12] 800789e: 4413 add r3, r2 80078a0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80078a4: 681b ldr r3, [r3, #0] 80078a6: 68ba ldr r2, [r7, #8] 80078a8: 0151 lsls r1, r2, #5 80078aa: 68fa ldr r2, [r7, #12] 80078ac: 440a add r2, r1 80078ae: f502 6230 add.w r2, r2, #2816 @ 0xb00 80078b2: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 80078b6: 6013 str r3, [r2, #0] USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; 80078b8: 68bb ldr r3, [r7, #8] 80078ba: 015a lsls r2, r3, #5 80078bc: 68fb ldr r3, [r7, #12] 80078be: 4413 add r3, r2 80078c0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80078c4: 681b ldr r3, [r3, #0] 80078c6: 68ba ldr r2, [r7, #8] 80078c8: 0151 lsls r1, r2, #5 80078ca: 68fa ldr r2, [r7, #12] 80078cc: 440a add r2, r1 80078ce: f502 6230 add.w r2, r2, #2816 @ 0xb00 80078d2: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80078d6: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 80078d8: 68fb ldr r3, [r7, #12] 80078da: f503 6300 add.w r3, r3, #2048 @ 0x800 80078de: 6bda ldr r2, [r3, #60] @ 0x3c 80078e0: 683b ldr r3, [r7, #0] 80078e2: 781b ldrb r3, [r3, #0] 80078e4: f003 030f and.w r3, r3, #15 80078e8: 2101 movs r1, #1 80078ea: fa01 f303 lsl.w r3, r1, r3 80078ee: 041b lsls r3, r3, #16 80078f0: 43db mvns r3, r3 80078f2: 68f9 ldr r1, [r7, #12] 80078f4: f501 6100 add.w r1, r1, #2048 @ 0x800 80078f8: 4013 ands r3, r2 80078fa: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 80078fc: 68fb ldr r3, [r7, #12] 80078fe: f503 6300 add.w r3, r3, #2048 @ 0x800 8007902: 69da ldr r2, [r3, #28] 8007904: 683b ldr r3, [r7, #0] 8007906: 781b ldrb r3, [r3, #0] 8007908: f003 030f and.w r3, r3, #15 800790c: 2101 movs r1, #1 800790e: fa01 f303 lsl.w r3, r1, r3 8007912: 041b lsls r3, r3, #16 8007914: 43db mvns r3, r3 8007916: 68f9 ldr r1, [r7, #12] 8007918: f501 6100 add.w r1, r1, #2048 @ 0x800 800791c: 4013 ands r3, r2 800791e: 61cb str r3, [r1, #28] USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | 8007920: 68bb ldr r3, [r7, #8] 8007922: 015a lsls r2, r3, #5 8007924: 68fb ldr r3, [r7, #12] 8007926: 4413 add r3, r2 8007928: f503 6330 add.w r3, r3, #2816 @ 0xb00 800792c: 681a ldr r2, [r3, #0] 800792e: 68bb ldr r3, [r7, #8] 8007930: 0159 lsls r1, r3, #5 8007932: 68fb ldr r3, [r7, #12] 8007934: 440b add r3, r1 8007936: f503 6330 add.w r3, r3, #2816 @ 0xb00 800793a: 4619 mov r1, r3 800793c: 4b05 ldr r3, [pc, #20] @ (8007954 ) 800793e: 4013 ands r3, r2 8007940: 600b str r3, [r1, #0] USB_OTG_DOEPCTL_MPSIZ | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_EPTYP); } return HAL_OK; 8007942: 2300 movs r3, #0 } 8007944: 4618 mov r0, r3 8007946: 3714 adds r7, #20 8007948: 46bd mov sp, r7 800794a: f85d 7b04 ldr.w r7, [sp], #4 800794e: 4770 bx lr 8007950: ec337800 .word 0xec337800 8007954: eff37800 .word 0xeff37800 08007958 : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 8007958: b580 push {r7, lr} 800795a: b08a sub sp, #40 @ 0x28 800795c: af02 add r7, sp, #8 800795e: 60f8 str r0, [r7, #12] 8007960: 60b9 str r1, [r7, #8] 8007962: 4613 mov r3, r2 8007964: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 8007966: 68fb ldr r3, [r7, #12] 8007968: 61fb str r3, [r7, #28] uint32_t epnum = (uint32_t)ep->num; 800796a: 68bb ldr r3, [r7, #8] 800796c: 781b ldrb r3, [r3, #0] 800796e: 61bb str r3, [r7, #24] uint16_t pktcnt; /* IN endpoint */ if (ep->is_in == 1U) 8007970: 68bb ldr r3, [r7, #8] 8007972: 785b ldrb r3, [r3, #1] 8007974: 2b01 cmp r3, #1 8007976: f040 817f bne.w 8007c78 { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 800797a: 68bb ldr r3, [r7, #8] 800797c: 691b ldr r3, [r3, #16] 800797e: 2b00 cmp r3, #0 8007980: d132 bne.n 80079e8 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8007982: 69bb ldr r3, [r7, #24] 8007984: 015a lsls r2, r3, #5 8007986: 69fb ldr r3, [r7, #28] 8007988: 4413 add r3, r2 800798a: f503 6310 add.w r3, r3, #2304 @ 0x900 800798e: 691b ldr r3, [r3, #16] 8007990: 69ba ldr r2, [r7, #24] 8007992: 0151 lsls r1, r2, #5 8007994: 69fa ldr r2, [r7, #28] 8007996: 440a add r2, r1 8007998: f502 6210 add.w r2, r2, #2304 @ 0x900 800799c: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 80079a0: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 80079a4: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 80079a6: 69bb ldr r3, [r7, #24] 80079a8: 015a lsls r2, r3, #5 80079aa: 69fb ldr r3, [r7, #28] 80079ac: 4413 add r3, r2 80079ae: f503 6310 add.w r3, r3, #2304 @ 0x900 80079b2: 691b ldr r3, [r3, #16] 80079b4: 69ba ldr r2, [r7, #24] 80079b6: 0151 lsls r1, r2, #5 80079b8: 69fa ldr r2, [r7, #28] 80079ba: 440a add r2, r1 80079bc: f502 6210 add.w r2, r2, #2304 @ 0x900 80079c0: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80079c4: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 80079c6: 69bb ldr r3, [r7, #24] 80079c8: 015a lsls r2, r3, #5 80079ca: 69fb ldr r3, [r7, #28] 80079cc: 4413 add r3, r2 80079ce: f503 6310 add.w r3, r3, #2304 @ 0x900 80079d2: 691b ldr r3, [r3, #16] 80079d4: 69ba ldr r2, [r7, #24] 80079d6: 0151 lsls r1, r2, #5 80079d8: 69fa ldr r2, [r7, #28] 80079da: 440a add r2, r1 80079dc: f502 6210 add.w r2, r2, #2304 @ 0x900 80079e0: 0cdb lsrs r3, r3, #19 80079e2: 04db lsls r3, r3, #19 80079e4: 6113 str r3, [r2, #16] 80079e6: e097 b.n 8007b18 /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 80079e8: 69bb ldr r3, [r7, #24] 80079ea: 015a lsls r2, r3, #5 80079ec: 69fb ldr r3, [r7, #28] 80079ee: 4413 add r3, r2 80079f0: f503 6310 add.w r3, r3, #2304 @ 0x900 80079f4: 691b ldr r3, [r3, #16] 80079f6: 69ba ldr r2, [r7, #24] 80079f8: 0151 lsls r1, r2, #5 80079fa: 69fa ldr r2, [r7, #28] 80079fc: 440a add r2, r1 80079fe: f502 6210 add.w r2, r2, #2304 @ 0x900 8007a02: 0cdb lsrs r3, r3, #19 8007a04: 04db lsls r3, r3, #19 8007a06: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8007a08: 69bb ldr r3, [r7, #24] 8007a0a: 015a lsls r2, r3, #5 8007a0c: 69fb ldr r3, [r7, #28] 8007a0e: 4413 add r3, r2 8007a10: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a14: 691b ldr r3, [r3, #16] 8007a16: 69ba ldr r2, [r7, #24] 8007a18: 0151 lsls r1, r2, #5 8007a1a: 69fa ldr r2, [r7, #28] 8007a1c: 440a add r2, r1 8007a1e: f502 6210 add.w r2, r2, #2304 @ 0x900 8007a22: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007a26: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8007a2a: 6113 str r3, [r2, #16] if (epnum == 0U) 8007a2c: 69bb ldr r3, [r7, #24] 8007a2e: 2b00 cmp r3, #0 8007a30: d11a bne.n 8007a68 { if (ep->xfer_len > ep->maxpacket) 8007a32: 68bb ldr r3, [r7, #8] 8007a34: 691a ldr r2, [r3, #16] 8007a36: 68bb ldr r3, [r7, #8] 8007a38: 689b ldr r3, [r3, #8] 8007a3a: 429a cmp r2, r3 8007a3c: d903 bls.n 8007a46 { ep->xfer_len = ep->maxpacket; 8007a3e: 68bb ldr r3, [r7, #8] 8007a40: 689a ldr r2, [r3, #8] 8007a42: 68bb ldr r3, [r7, #8] 8007a44: 611a str r2, [r3, #16] } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8007a46: 69bb ldr r3, [r7, #24] 8007a48: 015a lsls r2, r3, #5 8007a4a: 69fb ldr r3, [r7, #28] 8007a4c: 4413 add r3, r2 8007a4e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a52: 691b ldr r3, [r3, #16] 8007a54: 69ba ldr r2, [r7, #24] 8007a56: 0151 lsls r1, r2, #5 8007a58: 69fa ldr r2, [r7, #28] 8007a5a: 440a add r2, r1 8007a5c: f502 6210 add.w r2, r2, #2304 @ 0x900 8007a60: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007a64: 6113 str r3, [r2, #16] 8007a66: e044 b.n 8007af2 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8007a68: 68bb ldr r3, [r7, #8] 8007a6a: 691a ldr r2, [r3, #16] 8007a6c: 68bb ldr r3, [r7, #8] 8007a6e: 689b ldr r3, [r3, #8] 8007a70: 4413 add r3, r2 8007a72: 1e5a subs r2, r3, #1 8007a74: 68bb ldr r3, [r7, #8] 8007a76: 689b ldr r3, [r3, #8] 8007a78: fbb2 f3f3 udiv r3, r2, r3 8007a7c: 82fb strh r3, [r7, #22] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); 8007a7e: 69bb ldr r3, [r7, #24] 8007a80: 015a lsls r2, r3, #5 8007a82: 69fb ldr r3, [r7, #28] 8007a84: 4413 add r3, r2 8007a86: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a8a: 691a ldr r2, [r3, #16] 8007a8c: 8afb ldrh r3, [r7, #22] 8007a8e: 04d9 lsls r1, r3, #19 8007a90: 4ba4 ldr r3, [pc, #656] @ (8007d24 ) 8007a92: 400b ands r3, r1 8007a94: 69b9 ldr r1, [r7, #24] 8007a96: 0148 lsls r0, r1, #5 8007a98: 69f9 ldr r1, [r7, #28] 8007a9a: 4401 add r1, r0 8007a9c: f501 6110 add.w r1, r1, #2304 @ 0x900 8007aa0: 4313 orrs r3, r2 8007aa2: 610b str r3, [r1, #16] if (ep->type == EP_TYPE_ISOC) 8007aa4: 68bb ldr r3, [r7, #8] 8007aa6: 791b ldrb r3, [r3, #4] 8007aa8: 2b01 cmp r3, #1 8007aaa: d122 bne.n 8007af2 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 8007aac: 69bb ldr r3, [r7, #24] 8007aae: 015a lsls r2, r3, #5 8007ab0: 69fb ldr r3, [r7, #28] 8007ab2: 4413 add r3, r2 8007ab4: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ab8: 691b ldr r3, [r3, #16] 8007aba: 69ba ldr r2, [r7, #24] 8007abc: 0151 lsls r1, r2, #5 8007abe: 69fa ldr r2, [r7, #28] 8007ac0: 440a add r2, r1 8007ac2: f502 6210 add.w r2, r2, #2304 @ 0x900 8007ac6: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000 8007aca: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); 8007acc: 69bb ldr r3, [r7, #24] 8007ace: 015a lsls r2, r3, #5 8007ad0: 69fb ldr r3, [r7, #28] 8007ad2: 4413 add r3, r2 8007ad4: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ad8: 691a ldr r2, [r3, #16] 8007ada: 8afb ldrh r3, [r7, #22] 8007adc: 075b lsls r3, r3, #29 8007ade: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000 8007ae2: 69b9 ldr r1, [r7, #24] 8007ae4: 0148 lsls r0, r1, #5 8007ae6: 69f9 ldr r1, [r7, #28] 8007ae8: 4401 add r1, r0 8007aea: f501 6110 add.w r1, r1, #2304 @ 0x900 8007aee: 4313 orrs r3, r2 8007af0: 610b str r3, [r1, #16] } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 8007af2: 69bb ldr r3, [r7, #24] 8007af4: 015a lsls r2, r3, #5 8007af6: 69fb ldr r3, [r7, #28] 8007af8: 4413 add r3, r2 8007afa: f503 6310 add.w r3, r3, #2304 @ 0x900 8007afe: 691a ldr r2, [r3, #16] 8007b00: 68bb ldr r3, [r7, #8] 8007b02: 691b ldr r3, [r3, #16] 8007b04: f3c3 0312 ubfx r3, r3, #0, #19 8007b08: 69b9 ldr r1, [r7, #24] 8007b0a: 0148 lsls r0, r1, #5 8007b0c: 69f9 ldr r1, [r7, #28] 8007b0e: 4401 add r1, r0 8007b10: f501 6110 add.w r1, r1, #2304 @ 0x900 8007b14: 4313 orrs r3, r2 8007b16: 610b str r3, [r1, #16] } if (dma == 1U) 8007b18: 79fb ldrb r3, [r7, #7] 8007b1a: 2b01 cmp r3, #1 8007b1c: d14b bne.n 8007bb6 { if ((uint32_t)ep->dma_addr != 0U) 8007b1e: 68bb ldr r3, [r7, #8] 8007b20: 69db ldr r3, [r3, #28] 8007b22: 2b00 cmp r3, #0 8007b24: d009 beq.n 8007b3a { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 8007b26: 69bb ldr r3, [r7, #24] 8007b28: 015a lsls r2, r3, #5 8007b2a: 69fb ldr r3, [r7, #28] 8007b2c: 4413 add r3, r2 8007b2e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b32: 461a mov r2, r3 8007b34: 68bb ldr r3, [r7, #8] 8007b36: 69db ldr r3, [r3, #28] 8007b38: 6153 str r3, [r2, #20] } if (ep->type == EP_TYPE_ISOC) 8007b3a: 68bb ldr r3, [r7, #8] 8007b3c: 791b ldrb r3, [r3, #4] 8007b3e: 2b01 cmp r3, #1 8007b40: d128 bne.n 8007b94 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007b42: 69fb ldr r3, [r7, #28] 8007b44: f503 6300 add.w r3, r3, #2048 @ 0x800 8007b48: 689b ldr r3, [r3, #8] 8007b4a: f403 7380 and.w r3, r3, #256 @ 0x100 8007b4e: 2b00 cmp r3, #0 8007b50: d110 bne.n 8007b74 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8007b52: 69bb ldr r3, [r7, #24] 8007b54: 015a lsls r2, r3, #5 8007b56: 69fb ldr r3, [r7, #28] 8007b58: 4413 add r3, r2 8007b5a: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b5e: 681b ldr r3, [r3, #0] 8007b60: 69ba ldr r2, [r7, #24] 8007b62: 0151 lsls r1, r2, #5 8007b64: 69fa ldr r2, [r7, #28] 8007b66: 440a add r2, r1 8007b68: f502 6210 add.w r2, r2, #2304 @ 0x900 8007b6c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007b70: 6013 str r3, [r2, #0] 8007b72: e00f b.n 8007b94 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8007b74: 69bb ldr r3, [r7, #24] 8007b76: 015a lsls r2, r3, #5 8007b78: 69fb ldr r3, [r7, #28] 8007b7a: 4413 add r3, r2 8007b7c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b80: 681b ldr r3, [r3, #0] 8007b82: 69ba ldr r2, [r7, #24] 8007b84: 0151 lsls r1, r2, #5 8007b86: 69fa ldr r2, [r7, #28] 8007b88: 440a add r2, r1 8007b8a: f502 6210 add.w r2, r2, #2304 @ 0x900 8007b8e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007b92: 6013 str r3, [r2, #0] } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8007b94: 69bb ldr r3, [r7, #24] 8007b96: 015a lsls r2, r3, #5 8007b98: 69fb ldr r3, [r7, #28] 8007b9a: 4413 add r3, r2 8007b9c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ba0: 681b ldr r3, [r3, #0] 8007ba2: 69ba ldr r2, [r7, #24] 8007ba4: 0151 lsls r1, r2, #5 8007ba6: 69fa ldr r2, [r7, #28] 8007ba8: 440a add r2, r1 8007baa: f502 6210 add.w r2, r2, #2304 @ 0x900 8007bae: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007bb2: 6013 str r3, [r2, #0] 8007bb4: e166 b.n 8007e84 } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8007bb6: 69bb ldr r3, [r7, #24] 8007bb8: 015a lsls r2, r3, #5 8007bba: 69fb ldr r3, [r7, #28] 8007bbc: 4413 add r3, r2 8007bbe: f503 6310 add.w r3, r3, #2304 @ 0x900 8007bc2: 681b ldr r3, [r3, #0] 8007bc4: 69ba ldr r2, [r7, #24] 8007bc6: 0151 lsls r1, r2, #5 8007bc8: 69fa ldr r2, [r7, #28] 8007bca: 440a add r2, r1 8007bcc: f502 6210 add.w r2, r2, #2304 @ 0x900 8007bd0: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007bd4: 6013 str r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 8007bd6: 68bb ldr r3, [r7, #8] 8007bd8: 791b ldrb r3, [r3, #4] 8007bda: 2b01 cmp r3, #1 8007bdc: d015 beq.n 8007c0a { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 8007bde: 68bb ldr r3, [r7, #8] 8007be0: 691b ldr r3, [r3, #16] 8007be2: 2b00 cmp r3, #0 8007be4: f000 814e beq.w 8007e84 { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 8007be8: 69fb ldr r3, [r7, #28] 8007bea: f503 6300 add.w r3, r3, #2048 @ 0x800 8007bee: 6b5a ldr r2, [r3, #52] @ 0x34 8007bf0: 68bb ldr r3, [r7, #8] 8007bf2: 781b ldrb r3, [r3, #0] 8007bf4: f003 030f and.w r3, r3, #15 8007bf8: 2101 movs r1, #1 8007bfa: fa01 f303 lsl.w r3, r1, r3 8007bfe: 69f9 ldr r1, [r7, #28] 8007c00: f501 6100 add.w r1, r1, #2048 @ 0x800 8007c04: 4313 orrs r3, r2 8007c06: 634b str r3, [r1, #52] @ 0x34 8007c08: e13c b.n 8007e84 } } else { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007c0a: 69fb ldr r3, [r7, #28] 8007c0c: f503 6300 add.w r3, r3, #2048 @ 0x800 8007c10: 689b ldr r3, [r3, #8] 8007c12: f403 7380 and.w r3, r3, #256 @ 0x100 8007c16: 2b00 cmp r3, #0 8007c18: d110 bne.n 8007c3c { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8007c1a: 69bb ldr r3, [r7, #24] 8007c1c: 015a lsls r2, r3, #5 8007c1e: 69fb ldr r3, [r7, #28] 8007c20: 4413 add r3, r2 8007c22: f503 6310 add.w r3, r3, #2304 @ 0x900 8007c26: 681b ldr r3, [r3, #0] 8007c28: 69ba ldr r2, [r7, #24] 8007c2a: 0151 lsls r1, r2, #5 8007c2c: 69fa ldr r2, [r7, #28] 8007c2e: 440a add r2, r1 8007c30: f502 6210 add.w r2, r2, #2304 @ 0x900 8007c34: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007c38: 6013 str r3, [r2, #0] 8007c3a: e00f b.n 8007c5c } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8007c3c: 69bb ldr r3, [r7, #24] 8007c3e: 015a lsls r2, r3, #5 8007c40: 69fb ldr r3, [r7, #28] 8007c42: 4413 add r3, r2 8007c44: f503 6310 add.w r3, r3, #2304 @ 0x900 8007c48: 681b ldr r3, [r3, #0] 8007c4a: 69ba ldr r2, [r7, #24] 8007c4c: 0151 lsls r1, r2, #5 8007c4e: 69fa ldr r2, [r7, #28] 8007c50: 440a add r2, r1 8007c52: f502 6210 add.w r2, r2, #2304 @ 0x900 8007c56: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007c5a: 6013 str r3, [r2, #0] } (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); 8007c5c: 68bb ldr r3, [r7, #8] 8007c5e: 68d9 ldr r1, [r3, #12] 8007c60: 68bb ldr r3, [r7, #8] 8007c62: 781a ldrb r2, [r3, #0] 8007c64: 68bb ldr r3, [r7, #8] 8007c66: 691b ldr r3, [r3, #16] 8007c68: b298 uxth r0, r3 8007c6a: 79fb ldrb r3, [r7, #7] 8007c6c: 9300 str r3, [sp, #0] 8007c6e: 4603 mov r3, r0 8007c70: 68f8 ldr r0, [r7, #12] 8007c72: f000 f9b9 bl 8007fe8 8007c76: e105 b.n 8007e84 { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 8007c78: 69bb ldr r3, [r7, #24] 8007c7a: 015a lsls r2, r3, #5 8007c7c: 69fb ldr r3, [r7, #28] 8007c7e: 4413 add r3, r2 8007c80: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007c84: 691b ldr r3, [r3, #16] 8007c86: 69ba ldr r2, [r7, #24] 8007c88: 0151 lsls r1, r2, #5 8007c8a: 69fa ldr r2, [r7, #28] 8007c8c: 440a add r2, r1 8007c8e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007c92: 0cdb lsrs r3, r3, #19 8007c94: 04db lsls r3, r3, #19 8007c96: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 8007c98: 69bb ldr r3, [r7, #24] 8007c9a: 015a lsls r2, r3, #5 8007c9c: 69fb ldr r3, [r7, #28] 8007c9e: 4413 add r3, r2 8007ca0: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007ca4: 691b ldr r3, [r3, #16] 8007ca6: 69ba ldr r2, [r7, #24] 8007ca8: 0151 lsls r1, r2, #5 8007caa: 69fa ldr r2, [r7, #28] 8007cac: 440a add r2, r1 8007cae: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007cb2: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007cb6: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8007cba: 6113 str r3, [r2, #16] if (epnum == 0U) 8007cbc: 69bb ldr r3, [r7, #24] 8007cbe: 2b00 cmp r3, #0 8007cc0: d132 bne.n 8007d28 { if (ep->xfer_len > 0U) 8007cc2: 68bb ldr r3, [r7, #8] 8007cc4: 691b ldr r3, [r3, #16] 8007cc6: 2b00 cmp r3, #0 8007cc8: d003 beq.n 8007cd2 { ep->xfer_len = ep->maxpacket; 8007cca: 68bb ldr r3, [r7, #8] 8007ccc: 689a ldr r2, [r3, #8] 8007cce: 68bb ldr r3, [r7, #8] 8007cd0: 611a str r2, [r3, #16] } /* Store transfer size, for EP0 this is equal to endpoint max packet size */ ep->xfer_size = ep->maxpacket; 8007cd2: 68bb ldr r3, [r7, #8] 8007cd4: 689a ldr r2, [r3, #8] 8007cd6: 68bb ldr r3, [r7, #8] 8007cd8: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); 8007cda: 69bb ldr r3, [r7, #24] 8007cdc: 015a lsls r2, r3, #5 8007cde: 69fb ldr r3, [r7, #28] 8007ce0: 4413 add r3, r2 8007ce2: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007ce6: 691a ldr r2, [r3, #16] 8007ce8: 68bb ldr r3, [r7, #8] 8007cea: 6a1b ldr r3, [r3, #32] 8007cec: f3c3 0312 ubfx r3, r3, #0, #19 8007cf0: 69b9 ldr r1, [r7, #24] 8007cf2: 0148 lsls r0, r1, #5 8007cf4: 69f9 ldr r1, [r7, #28] 8007cf6: 4401 add r1, r0 8007cf8: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007cfc: 4313 orrs r3, r2 8007cfe: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8007d00: 69bb ldr r3, [r7, #24] 8007d02: 015a lsls r2, r3, #5 8007d04: 69fb ldr r3, [r7, #28] 8007d06: 4413 add r3, r2 8007d08: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d0c: 691b ldr r3, [r3, #16] 8007d0e: 69ba ldr r2, [r7, #24] 8007d10: 0151 lsls r1, r2, #5 8007d12: 69fa ldr r2, [r7, #28] 8007d14: 440a add r2, r1 8007d16: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007d1a: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007d1e: 6113 str r3, [r2, #16] 8007d20: e062 b.n 8007de8 8007d22: bf00 nop 8007d24: 1ff80000 .word 0x1ff80000 } else { if (ep->xfer_len == 0U) 8007d28: 68bb ldr r3, [r7, #8] 8007d2a: 691b ldr r3, [r3, #16] 8007d2c: 2b00 cmp r3, #0 8007d2e: d123 bne.n 8007d78 { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 8007d30: 69bb ldr r3, [r7, #24] 8007d32: 015a lsls r2, r3, #5 8007d34: 69fb ldr r3, [r7, #28] 8007d36: 4413 add r3, r2 8007d38: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d3c: 691a ldr r2, [r3, #16] 8007d3e: 68bb ldr r3, [r7, #8] 8007d40: 689b ldr r3, [r3, #8] 8007d42: f3c3 0312 ubfx r3, r3, #0, #19 8007d46: 69b9 ldr r1, [r7, #24] 8007d48: 0148 lsls r0, r1, #5 8007d4a: 69f9 ldr r1, [r7, #28] 8007d4c: 4401 add r1, r0 8007d4e: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007d52: 4313 orrs r3, r2 8007d54: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8007d56: 69bb ldr r3, [r7, #24] 8007d58: 015a lsls r2, r3, #5 8007d5a: 69fb ldr r3, [r7, #28] 8007d5c: 4413 add r3, r2 8007d5e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d62: 691b ldr r3, [r3, #16] 8007d64: 69ba ldr r2, [r7, #24] 8007d66: 0151 lsls r1, r2, #5 8007d68: 69fa ldr r2, [r7, #28] 8007d6a: 440a add r2, r1 8007d6c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007d70: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007d74: 6113 str r3, [r2, #16] 8007d76: e037 b.n 8007de8 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8007d78: 68bb ldr r3, [r7, #8] 8007d7a: 691a ldr r2, [r3, #16] 8007d7c: 68bb ldr r3, [r7, #8] 8007d7e: 689b ldr r3, [r3, #8] 8007d80: 4413 add r3, r2 8007d82: 1e5a subs r2, r3, #1 8007d84: 68bb ldr r3, [r7, #8] 8007d86: 689b ldr r3, [r3, #8] 8007d88: fbb2 f3f3 udiv r3, r2, r3 8007d8c: 82fb strh r3, [r7, #22] ep->xfer_size = ep->maxpacket * pktcnt; 8007d8e: 68bb ldr r3, [r7, #8] 8007d90: 689b ldr r3, [r3, #8] 8007d92: 8afa ldrh r2, [r7, #22] 8007d94: fb03 f202 mul.w r2, r3, r2 8007d98: 68bb ldr r3, [r7, #8] 8007d9a: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); 8007d9c: 69bb ldr r3, [r7, #24] 8007d9e: 015a lsls r2, r3, #5 8007da0: 69fb ldr r3, [r7, #28] 8007da2: 4413 add r3, r2 8007da4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007da8: 691a ldr r2, [r3, #16] 8007daa: 8afb ldrh r3, [r7, #22] 8007dac: 04d9 lsls r1, r3, #19 8007dae: 4b38 ldr r3, [pc, #224] @ (8007e90 ) 8007db0: 400b ands r3, r1 8007db2: 69b9 ldr r1, [r7, #24] 8007db4: 0148 lsls r0, r1, #5 8007db6: 69f9 ldr r1, [r7, #28] 8007db8: 4401 add r1, r0 8007dba: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007dbe: 4313 orrs r3, r2 8007dc0: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; 8007dc2: 69bb ldr r3, [r7, #24] 8007dc4: 015a lsls r2, r3, #5 8007dc6: 69fb ldr r3, [r7, #28] 8007dc8: 4413 add r3, r2 8007dca: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007dce: 691a ldr r2, [r3, #16] 8007dd0: 68bb ldr r3, [r7, #8] 8007dd2: 6a1b ldr r3, [r3, #32] 8007dd4: f3c3 0312 ubfx r3, r3, #0, #19 8007dd8: 69b9 ldr r1, [r7, #24] 8007dda: 0148 lsls r0, r1, #5 8007ddc: 69f9 ldr r1, [r7, #28] 8007dde: 4401 add r1, r0 8007de0: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007de4: 4313 orrs r3, r2 8007de6: 610b str r3, [r1, #16] } } if (dma == 1U) 8007de8: 79fb ldrb r3, [r7, #7] 8007dea: 2b01 cmp r3, #1 8007dec: d10d bne.n 8007e0a { if ((uint32_t)ep->xfer_buff != 0U) 8007dee: 68bb ldr r3, [r7, #8] 8007df0: 68db ldr r3, [r3, #12] 8007df2: 2b00 cmp r3, #0 8007df4: d009 beq.n 8007e0a { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 8007df6: 68bb ldr r3, [r7, #8] 8007df8: 68d9 ldr r1, [r3, #12] 8007dfa: 69bb ldr r3, [r7, #24] 8007dfc: 015a lsls r2, r3, #5 8007dfe: 69fb ldr r3, [r7, #28] 8007e00: 4413 add r3, r2 8007e02: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e06: 460a mov r2, r1 8007e08: 615a str r2, [r3, #20] } } if (ep->type == EP_TYPE_ISOC) 8007e0a: 68bb ldr r3, [r7, #8] 8007e0c: 791b ldrb r3, [r3, #4] 8007e0e: 2b01 cmp r3, #1 8007e10: d128 bne.n 8007e64 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007e12: 69fb ldr r3, [r7, #28] 8007e14: f503 6300 add.w r3, r3, #2048 @ 0x800 8007e18: 689b ldr r3, [r3, #8] 8007e1a: f403 7380 and.w r3, r3, #256 @ 0x100 8007e1e: 2b00 cmp r3, #0 8007e20: d110 bne.n 8007e44 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 8007e22: 69bb ldr r3, [r7, #24] 8007e24: 015a lsls r2, r3, #5 8007e26: 69fb ldr r3, [r7, #28] 8007e28: 4413 add r3, r2 8007e2a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e2e: 681b ldr r3, [r3, #0] 8007e30: 69ba ldr r2, [r7, #24] 8007e32: 0151 lsls r1, r2, #5 8007e34: 69fa ldr r2, [r7, #28] 8007e36: 440a add r2, r1 8007e38: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007e3c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007e40: 6013 str r3, [r2, #0] 8007e42: e00f b.n 8007e64 } else { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 8007e44: 69bb ldr r3, [r7, #24] 8007e46: 015a lsls r2, r3, #5 8007e48: 69fb ldr r3, [r7, #28] 8007e4a: 4413 add r3, r2 8007e4c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e50: 681b ldr r3, [r3, #0] 8007e52: 69ba ldr r2, [r7, #24] 8007e54: 0151 lsls r1, r2, #5 8007e56: 69fa ldr r2, [r7, #28] 8007e58: 440a add r2, r1 8007e5a: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007e5e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007e62: 6013 str r3, [r2, #0] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8007e64: 69bb ldr r3, [r7, #24] 8007e66: 015a lsls r2, r3, #5 8007e68: 69fb ldr r3, [r7, #28] 8007e6a: 4413 add r3, r2 8007e6c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e70: 681b ldr r3, [r3, #0] 8007e72: 69ba ldr r2, [r7, #24] 8007e74: 0151 lsls r1, r2, #5 8007e76: 69fa ldr r2, [r7, #28] 8007e78: 440a add r2, r1 8007e7a: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007e7e: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007e82: 6013 str r3, [r2, #0] } return HAL_OK; 8007e84: 2300 movs r3, #0 } 8007e86: 4618 mov r0, r3 8007e88: 3720 adds r7, #32 8007e8a: 46bd mov sp, r7 8007e8c: bd80 pop {r7, pc} 8007e8e: bf00 nop 8007e90: 1ff80000 .word 0x1ff80000 08007e94 : * @param USBx usb device instance * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8007e94: b480 push {r7} 8007e96: b087 sub sp, #28 8007e98: af00 add r7, sp, #0 8007e9a: 6078 str r0, [r7, #4] 8007e9c: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8007e9e: 2300 movs r3, #0 8007ea0: 60fb str r3, [r7, #12] HAL_StatusTypeDef ret = HAL_OK; 8007ea2: 2300 movs r3, #0 8007ea4: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8007ea6: 687b ldr r3, [r7, #4] 8007ea8: 613b str r3, [r7, #16] /* IN endpoint */ if (ep->is_in == 1U) 8007eaa: 683b ldr r3, [r7, #0] 8007eac: 785b ldrb r3, [r3, #1] 8007eae: 2b01 cmp r3, #1 8007eb0: d14a bne.n 8007f48 { /* EP enable, IN data in FIFO */ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007eb2: 683b ldr r3, [r7, #0] 8007eb4: 781b ldrb r3, [r3, #0] 8007eb6: 015a lsls r2, r3, #5 8007eb8: 693b ldr r3, [r7, #16] 8007eba: 4413 add r3, r2 8007ebc: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ec0: 681b ldr r3, [r3, #0] 8007ec2: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007ec6: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007eca: f040 8086 bne.w 8007fda { USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); 8007ece: 683b ldr r3, [r7, #0] 8007ed0: 781b ldrb r3, [r3, #0] 8007ed2: 015a lsls r2, r3, #5 8007ed4: 693b ldr r3, [r7, #16] 8007ed6: 4413 add r3, r2 8007ed8: f503 6310 add.w r3, r3, #2304 @ 0x900 8007edc: 681b ldr r3, [r3, #0] 8007ede: 683a ldr r2, [r7, #0] 8007ee0: 7812 ldrb r2, [r2, #0] 8007ee2: 0151 lsls r1, r2, #5 8007ee4: 693a ldr r2, [r7, #16] 8007ee6: 440a add r2, r1 8007ee8: f502 6210 add.w r2, r2, #2304 @ 0x900 8007eec: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007ef0: 6013 str r3, [r2, #0] USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); 8007ef2: 683b ldr r3, [r7, #0] 8007ef4: 781b ldrb r3, [r3, #0] 8007ef6: 015a lsls r2, r3, #5 8007ef8: 693b ldr r3, [r7, #16] 8007efa: 4413 add r3, r2 8007efc: f503 6310 add.w r3, r3, #2304 @ 0x900 8007f00: 681b ldr r3, [r3, #0] 8007f02: 683a ldr r2, [r7, #0] 8007f04: 7812 ldrb r2, [r2, #0] 8007f06: 0151 lsls r1, r2, #5 8007f08: 693a ldr r2, [r7, #16] 8007f0a: 440a add r2, r1 8007f0c: f502 6210 add.w r2, r2, #2304 @ 0x900 8007f10: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007f14: 6013 str r3, [r2, #0] do { count++; 8007f16: 68fb ldr r3, [r7, #12] 8007f18: 3301 adds r3, #1 8007f1a: 60fb str r3, [r7, #12] if (count > 10000U) 8007f1c: 68fb ldr r3, [r7, #12] 8007f1e: f242 7210 movw r2, #10000 @ 0x2710 8007f22: 4293 cmp r3, r2 8007f24: d902 bls.n 8007f2c { ret = HAL_ERROR; 8007f26: 2301 movs r3, #1 8007f28: 75fb strb r3, [r7, #23] break; 8007f2a: e056 b.n 8007fda } } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); 8007f2c: 683b ldr r3, [r7, #0] 8007f2e: 781b ldrb r3, [r3, #0] 8007f30: 015a lsls r2, r3, #5 8007f32: 693b ldr r3, [r7, #16] 8007f34: 4413 add r3, r2 8007f36: f503 6310 add.w r3, r3, #2304 @ 0x900 8007f3a: 681b ldr r3, [r3, #0] 8007f3c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007f40: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007f44: d0e7 beq.n 8007f16 8007f46: e048 b.n 8007fda } } else /* OUT endpoint */ { if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007f48: 683b ldr r3, [r7, #0] 8007f4a: 781b ldrb r3, [r3, #0] 8007f4c: 015a lsls r2, r3, #5 8007f4e: 693b ldr r3, [r7, #16] 8007f50: 4413 add r3, r2 8007f52: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f56: 681b ldr r3, [r3, #0] 8007f58: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007f5c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007f60: d13b bne.n 8007fda { USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); 8007f62: 683b ldr r3, [r7, #0] 8007f64: 781b ldrb r3, [r3, #0] 8007f66: 015a lsls r2, r3, #5 8007f68: 693b ldr r3, [r7, #16] 8007f6a: 4413 add r3, r2 8007f6c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f70: 681b ldr r3, [r3, #0] 8007f72: 683a ldr r2, [r7, #0] 8007f74: 7812 ldrb r2, [r2, #0] 8007f76: 0151 lsls r1, r2, #5 8007f78: 693a ldr r2, [r7, #16] 8007f7a: 440a add r2, r1 8007f7c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007f80: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007f84: 6013 str r3, [r2, #0] USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); 8007f86: 683b ldr r3, [r7, #0] 8007f88: 781b ldrb r3, [r3, #0] 8007f8a: 015a lsls r2, r3, #5 8007f8c: 693b ldr r3, [r7, #16] 8007f8e: 4413 add r3, r2 8007f90: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f94: 681b ldr r3, [r3, #0] 8007f96: 683a ldr r2, [r7, #0] 8007f98: 7812 ldrb r2, [r2, #0] 8007f9a: 0151 lsls r1, r2, #5 8007f9c: 693a ldr r2, [r7, #16] 8007f9e: 440a add r2, r1 8007fa0: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007fa4: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007fa8: 6013 str r3, [r2, #0] do { count++; 8007faa: 68fb ldr r3, [r7, #12] 8007fac: 3301 adds r3, #1 8007fae: 60fb str r3, [r7, #12] if (count > 10000U) 8007fb0: 68fb ldr r3, [r7, #12] 8007fb2: f242 7210 movw r2, #10000 @ 0x2710 8007fb6: 4293 cmp r3, r2 8007fb8: d902 bls.n 8007fc0 { ret = HAL_ERROR; 8007fba: 2301 movs r3, #1 8007fbc: 75fb strb r3, [r7, #23] break; 8007fbe: e00c b.n 8007fda } } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); 8007fc0: 683b ldr r3, [r7, #0] 8007fc2: 781b ldrb r3, [r3, #0] 8007fc4: 015a lsls r2, r3, #5 8007fc6: 693b ldr r3, [r7, #16] 8007fc8: 4413 add r3, r2 8007fca: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007fce: 681b ldr r3, [r3, #0] 8007fd0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007fd4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007fd8: d0e7 beq.n 8007faa } } return ret; 8007fda: 7dfb ldrb r3, [r7, #23] } 8007fdc: 4618 mov r0, r3 8007fde: 371c adds r7, #28 8007fe0: 46bd mov sp, r7 8007fe2: f85d 7b04 ldr.w r7, [sp], #4 8007fe6: 4770 bx lr 08007fe8 : * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { 8007fe8: b480 push {r7} 8007fea: b089 sub sp, #36 @ 0x24 8007fec: af00 add r7, sp, #0 8007fee: 60f8 str r0, [r7, #12] 8007ff0: 60b9 str r1, [r7, #8] 8007ff2: 4611 mov r1, r2 8007ff4: 461a mov r2, r3 8007ff6: 460b mov r3, r1 8007ff8: 71fb strb r3, [r7, #7] 8007ffa: 4613 mov r3, r2 8007ffc: 80bb strh r3, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007ffe: 68fb ldr r3, [r7, #12] 8008000: 617b str r3, [r7, #20] uint8_t *pSrc = src; 8008002: 68bb ldr r3, [r7, #8] 8008004: 61fb str r3, [r7, #28] uint32_t count32b; uint32_t i; if (dma == 0U) 8008006: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 800800a: 2b00 cmp r3, #0 800800c: d123 bne.n 8008056 { count32b = ((uint32_t)len + 3U) / 4U; 800800e: 88bb ldrh r3, [r7, #4] 8008010: 3303 adds r3, #3 8008012: 089b lsrs r3, r3, #2 8008014: 613b str r3, [r7, #16] for (i = 0U; i < count32b; i++) 8008016: 2300 movs r3, #0 8008018: 61bb str r3, [r7, #24] 800801a: e018 b.n 800804e { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); 800801c: 79fb ldrb r3, [r7, #7] 800801e: 031a lsls r2, r3, #12 8008020: 697b ldr r3, [r7, #20] 8008022: 4413 add r3, r2 8008024: f503 5380 add.w r3, r3, #4096 @ 0x1000 8008028: 461a mov r2, r3 800802a: 69fb ldr r3, [r7, #28] 800802c: 681b ldr r3, [r3, #0] 800802e: 6013 str r3, [r2, #0] pSrc++; 8008030: 69fb ldr r3, [r7, #28] 8008032: 3301 adds r3, #1 8008034: 61fb str r3, [r7, #28] pSrc++; 8008036: 69fb ldr r3, [r7, #28] 8008038: 3301 adds r3, #1 800803a: 61fb str r3, [r7, #28] pSrc++; 800803c: 69fb ldr r3, [r7, #28] 800803e: 3301 adds r3, #1 8008040: 61fb str r3, [r7, #28] pSrc++; 8008042: 69fb ldr r3, [r7, #28] 8008044: 3301 adds r3, #1 8008046: 61fb str r3, [r7, #28] for (i = 0U; i < count32b; i++) 8008048: 69bb ldr r3, [r7, #24] 800804a: 3301 adds r3, #1 800804c: 61bb str r3, [r7, #24] 800804e: 69ba ldr r2, [r7, #24] 8008050: 693b ldr r3, [r7, #16] 8008052: 429a cmp r2, r3 8008054: d3e2 bcc.n 800801c } } return HAL_OK; 8008056: 2300 movs r3, #0 } 8008058: 4618 mov r0, r3 800805a: 3724 adds r7, #36 @ 0x24 800805c: 46bd mov sp, r7 800805e: f85d 7b04 ldr.w r7, [sp], #4 8008062: 4770 bx lr 08008064 : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 8008064: b480 push {r7} 8008066: b08b sub sp, #44 @ 0x2c 8008068: af00 add r7, sp, #0 800806a: 60f8 str r0, [r7, #12] 800806c: 60b9 str r1, [r7, #8] 800806e: 4613 mov r3, r2 8008070: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 8008072: 68fb ldr r3, [r7, #12] 8008074: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 8008076: 68bb ldr r3, [r7, #8] 8008078: 627b str r3, [r7, #36] @ 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 800807a: 88fb ldrh r3, [r7, #6] 800807c: 089b lsrs r3, r3, #2 800807e: b29b uxth r3, r3 8008080: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 8008082: 88fb ldrh r3, [r7, #6] 8008084: f003 0303 and.w r3, r3, #3 8008088: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 800808a: 2300 movs r3, #0 800808c: 623b str r3, [r7, #32] 800808e: e014 b.n 80080ba { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 8008090: 69bb ldr r3, [r7, #24] 8008092: f503 5380 add.w r3, r3, #4096 @ 0x1000 8008096: 681a ldr r2, [r3, #0] 8008098: 6a7b ldr r3, [r7, #36] @ 0x24 800809a: 601a str r2, [r3, #0] pDest++; 800809c: 6a7b ldr r3, [r7, #36] @ 0x24 800809e: 3301 adds r3, #1 80080a0: 627b str r3, [r7, #36] @ 0x24 pDest++; 80080a2: 6a7b ldr r3, [r7, #36] @ 0x24 80080a4: 3301 adds r3, #1 80080a6: 627b str r3, [r7, #36] @ 0x24 pDest++; 80080a8: 6a7b ldr r3, [r7, #36] @ 0x24 80080aa: 3301 adds r3, #1 80080ac: 627b str r3, [r7, #36] @ 0x24 pDest++; 80080ae: 6a7b ldr r3, [r7, #36] @ 0x24 80080b0: 3301 adds r3, #1 80080b2: 627b str r3, [r7, #36] @ 0x24 for (i = 0U; i < count32b; i++) 80080b4: 6a3b ldr r3, [r7, #32] 80080b6: 3301 adds r3, #1 80080b8: 623b str r3, [r7, #32] 80080ba: 6a3a ldr r2, [r7, #32] 80080bc: 697b ldr r3, [r7, #20] 80080be: 429a cmp r2, r3 80080c0: d3e6 bcc.n 8008090 } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 80080c2: 8bfb ldrh r3, [r7, #30] 80080c4: 2b00 cmp r3, #0 80080c6: d01e beq.n 8008106 { i = 0U; 80080c8: 2300 movs r3, #0 80080ca: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 80080cc: 69bb ldr r3, [r7, #24] 80080ce: f503 5380 add.w r3, r3, #4096 @ 0x1000 80080d2: 461a mov r2, r3 80080d4: f107 0310 add.w r3, r7, #16 80080d8: 6812 ldr r2, [r2, #0] 80080da: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 80080dc: 693a ldr r2, [r7, #16] 80080de: 6a3b ldr r3, [r7, #32] 80080e0: b2db uxtb r3, r3 80080e2: 00db lsls r3, r3, #3 80080e4: fa22 f303 lsr.w r3, r2, r3 80080e8: b2da uxtb r2, r3 80080ea: 6a7b ldr r3, [r7, #36] @ 0x24 80080ec: 701a strb r2, [r3, #0] i++; 80080ee: 6a3b ldr r3, [r7, #32] 80080f0: 3301 adds r3, #1 80080f2: 623b str r3, [r7, #32] pDest++; 80080f4: 6a7b ldr r3, [r7, #36] @ 0x24 80080f6: 3301 adds r3, #1 80080f8: 627b str r3, [r7, #36] @ 0x24 remaining_bytes--; 80080fa: 8bfb ldrh r3, [r7, #30] 80080fc: 3b01 subs r3, #1 80080fe: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 8008100: 8bfb ldrh r3, [r7, #30] 8008102: 2b00 cmp r3, #0 8008104: d1ea bne.n 80080dc } return ((void *)pDest); 8008106: 6a7b ldr r3, [r7, #36] @ 0x24 } 8008108: 4618 mov r0, r3 800810a: 372c adds r7, #44 @ 0x2c 800810c: 46bd mov sp, r7 800810e: f85d 7b04 ldr.w r7, [sp], #4 8008112: 4770 bx lr 08008114 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8008114: b480 push {r7} 8008116: b085 sub sp, #20 8008118: af00 add r7, sp, #0 800811a: 6078 str r0, [r7, #4] 800811c: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800811e: 687b ldr r3, [r7, #4] 8008120: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8008122: 683b ldr r3, [r7, #0] 8008124: 781b ldrb r3, [r3, #0] 8008126: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8008128: 683b ldr r3, [r7, #0] 800812a: 785b ldrb r3, [r3, #1] 800812c: 2b01 cmp r3, #1 800812e: d12c bne.n 800818a { if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) 8008130: 68bb ldr r3, [r7, #8] 8008132: 015a lsls r2, r3, #5 8008134: 68fb ldr r3, [r7, #12] 8008136: 4413 add r3, r2 8008138: f503 6310 add.w r3, r3, #2304 @ 0x900 800813c: 681b ldr r3, [r3, #0] 800813e: 2b00 cmp r3, #0 8008140: db12 blt.n 8008168 8008142: 68bb ldr r3, [r7, #8] 8008144: 2b00 cmp r3, #0 8008146: d00f beq.n 8008168 { USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 8008148: 68bb ldr r3, [r7, #8] 800814a: 015a lsls r2, r3, #5 800814c: 68fb ldr r3, [r7, #12] 800814e: 4413 add r3, r2 8008150: f503 6310 add.w r3, r3, #2304 @ 0x900 8008154: 681b ldr r3, [r3, #0] 8008156: 68ba ldr r2, [r7, #8] 8008158: 0151 lsls r1, r2, #5 800815a: 68fa ldr r2, [r7, #12] 800815c: 440a add r2, r1 800815e: f502 6210 add.w r2, r2, #2304 @ 0x900 8008162: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8008166: 6013 str r3, [r2, #0] } USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 8008168: 68bb ldr r3, [r7, #8] 800816a: 015a lsls r2, r3, #5 800816c: 68fb ldr r3, [r7, #12] 800816e: 4413 add r3, r2 8008170: f503 6310 add.w r3, r3, #2304 @ 0x900 8008174: 681b ldr r3, [r3, #0] 8008176: 68ba ldr r2, [r7, #8] 8008178: 0151 lsls r1, r2, #5 800817a: 68fa ldr r2, [r7, #12] 800817c: 440a add r2, r1 800817e: f502 6210 add.w r2, r2, #2304 @ 0x900 8008182: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8008186: 6013 str r3, [r2, #0] 8008188: e02b b.n 80081e2 } else { if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) 800818a: 68bb ldr r3, [r7, #8] 800818c: 015a lsls r2, r3, #5 800818e: 68fb ldr r3, [r7, #12] 8008190: 4413 add r3, r2 8008192: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008196: 681b ldr r3, [r3, #0] 8008198: 2b00 cmp r3, #0 800819a: db12 blt.n 80081c2 800819c: 68bb ldr r3, [r7, #8] 800819e: 2b00 cmp r3, #0 80081a0: d00f beq.n 80081c2 { USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 80081a2: 68bb ldr r3, [r7, #8] 80081a4: 015a lsls r2, r3, #5 80081a6: 68fb ldr r3, [r7, #12] 80081a8: 4413 add r3, r2 80081aa: f503 6330 add.w r3, r3, #2816 @ 0xb00 80081ae: 681b ldr r3, [r3, #0] 80081b0: 68ba ldr r2, [r7, #8] 80081b2: 0151 lsls r1, r2, #5 80081b4: 68fa ldr r2, [r7, #12] 80081b6: 440a add r2, r1 80081b8: f502 6230 add.w r2, r2, #2816 @ 0xb00 80081bc: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 80081c0: 6013 str r3, [r2, #0] } USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 80081c2: 68bb ldr r3, [r7, #8] 80081c4: 015a lsls r2, r3, #5 80081c6: 68fb ldr r3, [r7, #12] 80081c8: 4413 add r3, r2 80081ca: f503 6330 add.w r3, r3, #2816 @ 0xb00 80081ce: 681b ldr r3, [r3, #0] 80081d0: 68ba ldr r2, [r7, #8] 80081d2: 0151 lsls r1, r2, #5 80081d4: 68fa ldr r2, [r7, #12] 80081d6: 440a add r2, r1 80081d8: f502 6230 add.w r2, r2, #2816 @ 0xb00 80081dc: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 80081e0: 6013 str r3, [r2, #0] } return HAL_OK; 80081e2: 2300 movs r3, #0 } 80081e4: 4618 mov r0, r3 80081e6: 3714 adds r7, #20 80081e8: 46bd mov sp, r7 80081ea: f85d 7b04 ldr.w r7, [sp], #4 80081ee: 4770 bx lr 080081f0 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 80081f0: b480 push {r7} 80081f2: b085 sub sp, #20 80081f4: af00 add r7, sp, #0 80081f6: 6078 str r0, [r7, #4] 80081f8: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80081fa: 687b ldr r3, [r7, #4] 80081fc: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80081fe: 683b ldr r3, [r7, #0] 8008200: 781b ldrb r3, [r3, #0] 8008202: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8008204: 683b ldr r3, [r7, #0] 8008206: 785b ldrb r3, [r3, #1] 8008208: 2b01 cmp r3, #1 800820a: d128 bne.n 800825e { USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 800820c: 68bb ldr r3, [r7, #8] 800820e: 015a lsls r2, r3, #5 8008210: 68fb ldr r3, [r7, #12] 8008212: 4413 add r3, r2 8008214: f503 6310 add.w r3, r3, #2304 @ 0x900 8008218: 681b ldr r3, [r3, #0] 800821a: 68ba ldr r2, [r7, #8] 800821c: 0151 lsls r1, r2, #5 800821e: 68fa ldr r2, [r7, #12] 8008220: 440a add r2, r1 8008222: f502 6210 add.w r2, r2, #2304 @ 0x900 8008226: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 800822a: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 800822c: 683b ldr r3, [r7, #0] 800822e: 791b ldrb r3, [r3, #4] 8008230: 2b03 cmp r3, #3 8008232: d003 beq.n 800823c 8008234: 683b ldr r3, [r7, #0] 8008236: 791b ldrb r3, [r3, #4] 8008238: 2b02 cmp r3, #2 800823a: d138 bne.n 80082ae { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 800823c: 68bb ldr r3, [r7, #8] 800823e: 015a lsls r2, r3, #5 8008240: 68fb ldr r3, [r7, #12] 8008242: 4413 add r3, r2 8008244: f503 6310 add.w r3, r3, #2304 @ 0x900 8008248: 681b ldr r3, [r3, #0] 800824a: 68ba ldr r2, [r7, #8] 800824c: 0151 lsls r1, r2, #5 800824e: 68fa ldr r2, [r7, #12] 8008250: 440a add r2, r1 8008252: f502 6210 add.w r2, r2, #2304 @ 0x900 8008256: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800825a: 6013 str r3, [r2, #0] 800825c: e027 b.n 80082ae } } else { USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 800825e: 68bb ldr r3, [r7, #8] 8008260: 015a lsls r2, r3, #5 8008262: 68fb ldr r3, [r7, #12] 8008264: 4413 add r3, r2 8008266: f503 6330 add.w r3, r3, #2816 @ 0xb00 800826a: 681b ldr r3, [r3, #0] 800826c: 68ba ldr r2, [r7, #8] 800826e: 0151 lsls r1, r2, #5 8008270: 68fa ldr r2, [r7, #12] 8008272: 440a add r2, r1 8008274: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008278: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 800827c: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 800827e: 683b ldr r3, [r7, #0] 8008280: 791b ldrb r3, [r3, #4] 8008282: 2b03 cmp r3, #3 8008284: d003 beq.n 800828e 8008286: 683b ldr r3, [r7, #0] 8008288: 791b ldrb r3, [r3, #4] 800828a: 2b02 cmp r3, #2 800828c: d10f bne.n 80082ae { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 800828e: 68bb ldr r3, [r7, #8] 8008290: 015a lsls r2, r3, #5 8008292: 68fb ldr r3, [r7, #12] 8008294: 4413 add r3, r2 8008296: f503 6330 add.w r3, r3, #2816 @ 0xb00 800829a: 681b ldr r3, [r3, #0] 800829c: 68ba ldr r2, [r7, #8] 800829e: 0151 lsls r1, r2, #5 80082a0: 68fa ldr r2, [r7, #12] 80082a2: 440a add r2, r1 80082a4: f502 6230 add.w r2, r2, #2816 @ 0xb00 80082a8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80082ac: 6013 str r3, [r2, #0] } } return HAL_OK; 80082ae: 2300 movs r3, #0 } 80082b0: 4618 mov r0, r3 80082b2: 3714 adds r7, #20 80082b4: 46bd mov sp, r7 80082b6: f85d 7b04 ldr.w r7, [sp], #4 80082ba: 4770 bx lr 080082bc : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { 80082bc: b480 push {r7} 80082be: b085 sub sp, #20 80082c0: af00 add r7, sp, #0 80082c2: 6078 str r0, [r7, #4] 80082c4: 460b mov r3, r1 80082c6: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80082c8: 687b ldr r3, [r7, #4] 80082ca: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); 80082cc: 68fb ldr r3, [r7, #12] 80082ce: f503 6300 add.w r3, r3, #2048 @ 0x800 80082d2: 681b ldr r3, [r3, #0] 80082d4: 68fa ldr r2, [r7, #12] 80082d6: f502 6200 add.w r2, r2, #2048 @ 0x800 80082da: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 80082de: 6013 str r3, [r2, #0] USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; 80082e0: 68fb ldr r3, [r7, #12] 80082e2: f503 6300 add.w r3, r3, #2048 @ 0x800 80082e6: 681a ldr r2, [r3, #0] 80082e8: 78fb ldrb r3, [r7, #3] 80082ea: 011b lsls r3, r3, #4 80082ec: f403 63fe and.w r3, r3, #2032 @ 0x7f0 80082f0: 68f9 ldr r1, [r7, #12] 80082f2: f501 6100 add.w r1, r1, #2048 @ 0x800 80082f6: 4313 orrs r3, r2 80082f8: 600b str r3, [r1, #0] return HAL_OK; 80082fa: 2300 movs r3, #0 } 80082fc: 4618 mov r0, r3 80082fe: 3714 adds r7, #20 8008300: 46bd mov sp, r7 8008302: f85d 7b04 ldr.w r7, [sp], #4 8008306: 4770 bx lr 08008308 : * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { 8008308: b480 push {r7} 800830a: b085 sub sp, #20 800830c: af00 add r7, sp, #0 800830e: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008310: 687b ldr r3, [r7, #4] 8008312: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8008314: 68fb ldr r3, [r7, #12] 8008316: f503 6360 add.w r3, r3, #3584 @ 0xe00 800831a: 681b ldr r3, [r3, #0] 800831c: 68fa ldr r2, [r7, #12] 800831e: f502 6260 add.w r2, r2, #3584 @ 0xe00 8008322: f023 0303 bic.w r3, r3, #3 8008326: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; 8008328: 68fb ldr r3, [r7, #12] 800832a: f503 6300 add.w r3, r3, #2048 @ 0x800 800832e: 685b ldr r3, [r3, #4] 8008330: 68fa ldr r2, [r7, #12] 8008332: f502 6200 add.w r2, r2, #2048 @ 0x800 8008336: f023 0302 bic.w r3, r3, #2 800833a: 6053 str r3, [r2, #4] return HAL_OK; 800833c: 2300 movs r3, #0 } 800833e: 4618 mov r0, r3 8008340: 3714 adds r7, #20 8008342: 46bd mov sp, r7 8008344: f85d 7b04 ldr.w r7, [sp], #4 8008348: 4770 bx lr 0800834a : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { 800834a: b480 push {r7} 800834c: b085 sub sp, #20 800834e: af00 add r7, sp, #0 8008350: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008352: 687b ldr r3, [r7, #4] 8008354: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8008356: 68fb ldr r3, [r7, #12] 8008358: f503 6360 add.w r3, r3, #3584 @ 0xe00 800835c: 681b ldr r3, [r3, #0] 800835e: 68fa ldr r2, [r7, #12] 8008360: f502 6260 add.w r2, r2, #3584 @ 0xe00 8008364: f023 0303 bic.w r3, r3, #3 8008368: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 800836a: 68fb ldr r3, [r7, #12] 800836c: f503 6300 add.w r3, r3, #2048 @ 0x800 8008370: 685b ldr r3, [r3, #4] 8008372: 68fa ldr r2, [r7, #12] 8008374: f502 6200 add.w r2, r2, #2048 @ 0x800 8008378: f043 0302 orr.w r3, r3, #2 800837c: 6053 str r3, [r2, #4] return HAL_OK; 800837e: 2300 movs r3, #0 } 8008380: 4618 mov r0, r3 8008382: 3714 adds r7, #20 8008384: 46bd mov sp, r7 8008386: f85d 7b04 ldr.w r7, [sp], #4 800838a: 4770 bx lr 0800838c : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { 800838c: b480 push {r7} 800838e: b085 sub sp, #20 8008390: af00 add r7, sp, #0 8008392: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 8008394: 687b ldr r3, [r7, #4] 8008396: 695b ldr r3, [r3, #20] 8008398: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 800839a: 687b ldr r3, [r7, #4] 800839c: 699b ldr r3, [r3, #24] 800839e: 68fa ldr r2, [r7, #12] 80083a0: 4013 ands r3, r2 80083a2: 60fb str r3, [r7, #12] return tmpreg; 80083a4: 68fb ldr r3, [r7, #12] } 80083a6: 4618 mov r0, r3 80083a8: 3714 adds r7, #20 80083aa: 46bd mov sp, r7 80083ac: f85d 7b04 ldr.w r7, [sp], #4 80083b0: 4770 bx lr 080083b2 : * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device * @retval USB Device OUT EP interrupt status */ uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 80083b2: b480 push {r7} 80083b4: b085 sub sp, #20 80083b6: af00 add r7, sp, #0 80083b8: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80083ba: 687b ldr r3, [r7, #4] 80083bc: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 80083be: 68fb ldr r3, [r7, #12] 80083c0: f503 6300 add.w r3, r3, #2048 @ 0x800 80083c4: 699b ldr r3, [r3, #24] 80083c6: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 80083c8: 68fb ldr r3, [r7, #12] 80083ca: f503 6300 add.w r3, r3, #2048 @ 0x800 80083ce: 69db ldr r3, [r3, #28] 80083d0: 68ba ldr r2, [r7, #8] 80083d2: 4013 ands r3, r2 80083d4: 60bb str r3, [r7, #8] return ((tmpreg & 0xffff0000U) >> 16); 80083d6: 68bb ldr r3, [r7, #8] 80083d8: 0c1b lsrs r3, r3, #16 } 80083da: 4618 mov r0, r3 80083dc: 3714 adds r7, #20 80083de: 46bd mov sp, r7 80083e0: f85d 7b04 ldr.w r7, [sp], #4 80083e4: 4770 bx lr 080083e6 : * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device * @retval USB Device IN EP interrupt status */ uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 80083e6: b480 push {r7} 80083e8: b085 sub sp, #20 80083ea: af00 add r7, sp, #0 80083ec: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80083ee: 687b ldr r3, [r7, #4] 80083f0: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 80083f2: 68fb ldr r3, [r7, #12] 80083f4: f503 6300 add.w r3, r3, #2048 @ 0x800 80083f8: 699b ldr r3, [r3, #24] 80083fa: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 80083fc: 68fb ldr r3, [r7, #12] 80083fe: f503 6300 add.w r3, r3, #2048 @ 0x800 8008402: 69db ldr r3, [r3, #28] 8008404: 68ba ldr r2, [r7, #8] 8008406: 4013 ands r3, r2 8008408: 60bb str r3, [r7, #8] return ((tmpreg & 0xFFFFU)); 800840a: 68bb ldr r3, [r7, #8] 800840c: b29b uxth r3, r3 } 800840e: 4618 mov r0, r3 8008410: 3714 adds r7, #20 8008412: 46bd mov sp, r7 8008414: f85d 7b04 ldr.w r7, [sp], #4 8008418: 4770 bx lr 0800841a : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 800841a: b480 push {r7} 800841c: b085 sub sp, #20 800841e: af00 add r7, sp, #0 8008420: 6078 str r0, [r7, #4] 8008422: 460b mov r3, r1 8008424: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008426: 687b ldr r3, [r7, #4] 8008428: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; 800842a: 78fb ldrb r3, [r7, #3] 800842c: 015a lsls r2, r3, #5 800842e: 68fb ldr r3, [r7, #12] 8008430: 4413 add r3, r2 8008432: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008436: 689b ldr r3, [r3, #8] 8008438: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DOEPMSK; 800843a: 68fb ldr r3, [r7, #12] 800843c: f503 6300 add.w r3, r3, #2048 @ 0x800 8008440: 695b ldr r3, [r3, #20] 8008442: 68ba ldr r2, [r7, #8] 8008444: 4013 ands r3, r2 8008446: 60bb str r3, [r7, #8] return tmpreg; 8008448: 68bb ldr r3, [r7, #8] } 800844a: 4618 mov r0, r3 800844c: 3714 adds r7, #20 800844e: 46bd mov sp, r7 8008450: f85d 7b04 ldr.w r7, [sp], #4 8008454: 4770 bx lr 08008456 : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 8008456: b480 push {r7} 8008458: b087 sub sp, #28 800845a: af00 add r7, sp, #0 800845c: 6078 str r0, [r7, #4] 800845e: 460b mov r3, r1 8008460: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008462: 687b ldr r3, [r7, #4] 8008464: 617b str r3, [r7, #20] uint32_t tmpreg; uint32_t msk; uint32_t emp; msk = USBx_DEVICE->DIEPMSK; 8008466: 697b ldr r3, [r7, #20] 8008468: f503 6300 add.w r3, r3, #2048 @ 0x800 800846c: 691b ldr r3, [r3, #16] 800846e: 613b str r3, [r7, #16] emp = USBx_DEVICE->DIEPEMPMSK; 8008470: 697b ldr r3, [r7, #20] 8008472: f503 6300 add.w r3, r3, #2048 @ 0x800 8008476: 6b5b ldr r3, [r3, #52] @ 0x34 8008478: 60fb str r3, [r7, #12] msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; 800847a: 78fb ldrb r3, [r7, #3] 800847c: f003 030f and.w r3, r3, #15 8008480: 68fa ldr r2, [r7, #12] 8008482: fa22 f303 lsr.w r3, r2, r3 8008486: 01db lsls r3, r3, #7 8008488: b2db uxtb r3, r3 800848a: 693a ldr r2, [r7, #16] 800848c: 4313 orrs r3, r2 800848e: 613b str r3, [r7, #16] tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; 8008490: 78fb ldrb r3, [r7, #3] 8008492: 015a lsls r2, r3, #5 8008494: 697b ldr r3, [r7, #20] 8008496: 4413 add r3, r2 8008498: f503 6310 add.w r3, r3, #2304 @ 0x900 800849c: 689b ldr r3, [r3, #8] 800849e: 693a ldr r2, [r7, #16] 80084a0: 4013 ands r3, r2 80084a2: 60bb str r3, [r7, #8] return tmpreg; 80084a4: 68bb ldr r3, [r7, #8] } 80084a6: 4618 mov r0, r3 80084a8: 371c adds r7, #28 80084aa: 46bd mov sp, r7 80084ac: f85d 7b04 ldr.w r7, [sp], #4 80084b0: 4770 bx lr 080084b2 : * This parameter can be one of these values: * 1 : Host * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { 80084b2: b480 push {r7} 80084b4: b083 sub sp, #12 80084b6: af00 add r7, sp, #0 80084b8: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 80084ba: 687b ldr r3, [r7, #4] 80084bc: 695b ldr r3, [r3, #20] 80084be: f003 0301 and.w r3, r3, #1 } 80084c2: 4618 mov r0, r3 80084c4: 370c adds r7, #12 80084c6: 46bd mov sp, r7 80084c8: f85d 7b04 ldr.w r7, [sp], #4 80084cc: 4770 bx lr 080084ce : * @brief Activate EP0 for Setup transactions * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { 80084ce: b480 push {r7} 80084d0: b085 sub sp, #20 80084d2: af00 add r7, sp, #0 80084d4: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80084d6: 687b ldr r3, [r7, #4] 80084d8: 60fb str r3, [r7, #12] /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 80084da: 68fb ldr r3, [r7, #12] 80084dc: f503 6310 add.w r3, r3, #2304 @ 0x900 80084e0: 681b ldr r3, [r3, #0] 80084e2: 68fa ldr r2, [r7, #12] 80084e4: f502 6210 add.w r2, r2, #2304 @ 0x900 80084e8: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 80084ec: f023 0307 bic.w r3, r3, #7 80084f0: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 80084f2: 68fb ldr r3, [r7, #12] 80084f4: f503 6300 add.w r3, r3, #2048 @ 0x800 80084f8: 685b ldr r3, [r3, #4] 80084fa: 68fa ldr r2, [r7, #12] 80084fc: f502 6200 add.w r2, r2, #2048 @ 0x800 8008500: f443 7380 orr.w r3, r3, #256 @ 0x100 8008504: 6053 str r3, [r2, #4] return HAL_OK; 8008506: 2300 movs r3, #0 } 8008508: 4618 mov r0, r3 800850a: 3714 adds r7, #20 800850c: 46bd mov sp, r7 800850e: f85d 7b04 ldr.w r7, [sp], #4 8008512: 4770 bx lr 08008514 : * 1 : DMA feature used * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { 8008514: b480 push {r7} 8008516: b087 sub sp, #28 8008518: af00 add r7, sp, #0 800851a: 60f8 str r0, [r7, #12] 800851c: 460b mov r3, r1 800851e: 607a str r2, [r7, #4] 8008520: 72fb strb r3, [r7, #11] uint32_t USBx_BASE = (uint32_t)USBx; 8008522: 68fb ldr r3, [r7, #12] 8008524: 617b str r3, [r7, #20] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8008526: 68fb ldr r3, [r7, #12] 8008528: 333c adds r3, #60 @ 0x3c 800852a: 3304 adds r3, #4 800852c: 681b ldr r3, [r3, #0] 800852e: 613b str r3, [r7, #16] if (gSNPSiD > USB_OTG_CORE_ID_300A) 8008530: 693b ldr r3, [r7, #16] 8008532: 4a26 ldr r2, [pc, #152] @ (80085cc ) 8008534: 4293 cmp r3, r2 8008536: d90a bls.n 800854e { if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8008538: 697b ldr r3, [r7, #20] 800853a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800853e: 681b ldr r3, [r3, #0] 8008540: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008544: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008548: d101 bne.n 800854e { return HAL_OK; 800854a: 2300 movs r3, #0 800854c: e037 b.n 80085be } } USBx_OUTEP(0U)->DOEPTSIZ = 0U; 800854e: 697b ldr r3, [r7, #20] 8008550: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008554: 461a mov r2, r3 8008556: 2300 movs r3, #0 8008558: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 800855a: 697b ldr r3, [r7, #20] 800855c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008560: 691b ldr r3, [r3, #16] 8008562: 697a ldr r2, [r7, #20] 8008564: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008568: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800856c: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); 800856e: 697b ldr r3, [r7, #20] 8008570: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008574: 691b ldr r3, [r3, #16] 8008576: 697a ldr r2, [r7, #20] 8008578: f502 6230 add.w r2, r2, #2816 @ 0xb00 800857c: f043 0318 orr.w r3, r3, #24 8008580: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 8008582: 697b ldr r3, [r7, #20] 8008584: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008588: 691b ldr r3, [r3, #16] 800858a: 697a ldr r2, [r7, #20] 800858c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008590: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000 8008594: 6113 str r3, [r2, #16] if (dma == 1U) 8008596: 7afb ldrb r3, [r7, #11] 8008598: 2b01 cmp r3, #1 800859a: d10f bne.n 80085bc { USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; 800859c: 697b ldr r3, [r7, #20] 800859e: f503 6330 add.w r3, r3, #2816 @ 0xb00 80085a2: 461a mov r2, r3 80085a4: 687b ldr r3, [r7, #4] 80085a6: 6153 str r3, [r2, #20] /* EP enable */ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; 80085a8: 697b ldr r3, [r7, #20] 80085aa: f503 6330 add.w r3, r3, #2816 @ 0xb00 80085ae: 681b ldr r3, [r3, #0] 80085b0: 697a ldr r2, [r7, #20] 80085b2: f502 6230 add.w r2, r2, #2816 @ 0xb00 80085b6: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000 80085ba: 6013 str r3, [r2, #0] } return HAL_OK; 80085bc: 2300 movs r3, #0 } 80085be: 4618 mov r0, r3 80085c0: 371c adds r7, #28 80085c2: 46bd mov sp, r7 80085c4: f85d 7b04 ldr.w r7, [sp], #4 80085c8: 4770 bx lr 80085ca: bf00 nop 80085cc: 4f54300a .word 0x4f54300a 080085d0 : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 80085d0: b480 push {r7} 80085d2: b085 sub sp, #20 80085d4: af00 add r7, sp, #0 80085d6: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 80085d8: 2300 movs r3, #0 80085da: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 80085dc: 68fb ldr r3, [r7, #12] 80085de: 3301 adds r3, #1 80085e0: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80085e2: 68fb ldr r3, [r7, #12] 80085e4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80085e8: d901 bls.n 80085ee { return HAL_TIMEOUT; 80085ea: 2303 movs r3, #3 80085ec: e022 b.n 8008634 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 80085ee: 687b ldr r3, [r7, #4] 80085f0: 691b ldr r3, [r3, #16] 80085f2: 2b00 cmp r3, #0 80085f4: daf2 bge.n 80085dc count = 10U; 80085f6: 230a movs r3, #10 80085f8: 60fb str r3, [r7, #12] /* few cycles before setting core reset */ while (count > 0U) 80085fa: e002 b.n 8008602 { count--; 80085fc: 68fb ldr r3, [r7, #12] 80085fe: 3b01 subs r3, #1 8008600: 60fb str r3, [r7, #12] while (count > 0U) 8008602: 68fb ldr r3, [r7, #12] 8008604: 2b00 cmp r3, #0 8008606: d1f9 bne.n 80085fc } /* Core Soft Reset */ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 8008608: 687b ldr r3, [r7, #4] 800860a: 691b ldr r3, [r3, #16] 800860c: f043 0201 orr.w r2, r3, #1 8008610: 687b ldr r3, [r7, #4] 8008612: 611a str r2, [r3, #16] do { count++; 8008614: 68fb ldr r3, [r7, #12] 8008616: 3301 adds r3, #1 8008618: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800861a: 68fb ldr r3, [r7, #12] 800861c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8008620: d901 bls.n 8008626 { return HAL_TIMEOUT; 8008622: 2303 movs r3, #3 8008624: e006 b.n 8008634 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 8008626: 687b ldr r3, [r7, #4] 8008628: 691b ldr r3, [r3, #16] 800862a: f003 0301 and.w r3, r3, #1 800862e: 2b01 cmp r3, #1 8008630: d0f0 beq.n 8008614 return HAL_OK; 8008632: 2300 movs r3, #0 } 8008634: 4618 mov r0, r3 8008636: 3714 adds r7, #20 8008638: 46bd mov sp, r7 800863a: f85d 7b04 ldr.w r7, [sp], #4 800863e: 4770 bx lr 08008640 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008640: b580 push {r7, lr} 8008642: b084 sub sp, #16 8008644: af00 add r7, sp, #0 8008646: 6078 str r0, [r7, #4] 8008648: 460b mov r3, r1 800864a: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_HID_HandleTypeDef *hhid; hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); 800864c: 2010 movs r0, #16 800864e: f002 f9e3 bl 800aa18 8008652: 60f8 str r0, [r7, #12] if (hhid == NULL) 8008654: 68fb ldr r3, [r7, #12] 8008656: 2b00 cmp r3, #0 8008658: d109 bne.n 800866e { pdev->pClassDataCmsit[pdev->classId] = NULL; 800865a: 687b ldr r3, [r7, #4] 800865c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008660: 687b ldr r3, [r7, #4] 8008662: 32b0 adds r2, #176 @ 0xb0 8008664: 2100 movs r1, #0 8008666: f843 1022 str.w r1, [r3, r2, lsl #2] return (uint8_t)USBD_EMEM; 800866a: 2302 movs r3, #2 800866c: e048 b.n 8008700 } pdev->pClassDataCmsit[pdev->classId] = (void *)hhid; 800866e: 687b ldr r3, [r7, #4] 8008670: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008674: 687b ldr r3, [r7, #4] 8008676: 32b0 adds r2, #176 @ 0xb0 8008678: 68f9 ldr r1, [r7, #12] 800867a: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; 800867e: 687b ldr r3, [r7, #4] 8008680: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008684: 687b ldr r3, [r7, #4] 8008686: 32b0 adds r2, #176 @ 0xb0 8008688: f853 2022 ldr.w r2, [r3, r2, lsl #2] 800868c: 687b ldr r3, [r7, #4] 800868e: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_speed == USBD_SPEED_HIGH) 8008692: 687b ldr r3, [r7, #4] 8008694: 7c1b ldrb r3, [r3, #16] 8008696: 2b00 cmp r3, #0 8008698: d10d bne.n 80086b6 { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL; 800869a: 4b1b ldr r3, [pc, #108] @ (8008708 ) 800869c: 781b ldrb r3, [r3, #0] 800869e: f003 020f and.w r2, r3, #15 80086a2: 6879 ldr r1, [r7, #4] 80086a4: 4613 mov r3, r2 80086a6: 009b lsls r3, r3, #2 80086a8: 4413 add r3, r2 80086aa: 009b lsls r3, r3, #2 80086ac: 440b add r3, r1 80086ae: 331c adds r3, #28 80086b0: 2207 movs r2, #7 80086b2: 601a str r2, [r3, #0] 80086b4: e00c b.n 80086d0 } else /* LOW and FULL-speed endpoints */ { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL; 80086b6: 4b14 ldr r3, [pc, #80] @ (8008708 ) 80086b8: 781b ldrb r3, [r3, #0] 80086ba: f003 020f and.w r2, r3, #15 80086be: 6879 ldr r1, [r7, #4] 80086c0: 4613 mov r3, r2 80086c2: 009b lsls r3, r3, #2 80086c4: 4413 add r3, r2 80086c6: 009b lsls r3, r3, #2 80086c8: 440b add r3, r1 80086ca: 331c adds r3, #28 80086cc: 220a movs r2, #10 80086ce: 601a str r2, [r3, #0] } /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); 80086d0: 4b0d ldr r3, [pc, #52] @ (8008708 ) 80086d2: 7819 ldrb r1, [r3, #0] 80086d4: 230e movs r3, #14 80086d6: 2203 movs r2, #3 80086d8: 6878 ldr r0, [r7, #4] 80086da: f002 f83e bl 800a75a pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U; 80086de: 4b0a ldr r3, [pc, #40] @ (8008708 ) 80086e0: 781b ldrb r3, [r3, #0] 80086e2: f003 020f and.w r2, r3, #15 80086e6: 6879 ldr r1, [r7, #4] 80086e8: 4613 mov r3, r2 80086ea: 009b lsls r3, r3, #2 80086ec: 4413 add r3, r2 80086ee: 009b lsls r3, r3, #2 80086f0: 440b add r3, r1 80086f2: 3323 adds r3, #35 @ 0x23 80086f4: 2201 movs r2, #1 80086f6: 701a strb r2, [r3, #0] hhid->state = USBD_HID_IDLE; 80086f8: 68fb ldr r3, [r7, #12] 80086fa: 2200 movs r2, #0 80086fc: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 80086fe: 2300 movs r3, #0 } 8008700: 4618 mov r0, r3 8008702: 3710 adds r7, #16 8008704: 46bd mov sp, r7 8008706: bd80 pop {r7, pc} 8008708: 2000013d .word 0x2000013d 0800870c : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 800870c: b580 push {r7, lr} 800870e: b082 sub sp, #8 8008710: af00 add r7, sp, #0 8008712: 6078 str r0, [r7, #4] 8008714: 460b mov r3, r1 8008716: 70fb strb r3, [r7, #3] /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ /* Close HID EPs */ (void)USBD_LL_CloseEP(pdev, HIDInEpAdd); 8008718: 4b1f ldr r3, [pc, #124] @ (8008798 ) 800871a: 781b ldrb r3, [r3, #0] 800871c: 4619 mov r1, r3 800871e: 6878 ldr r0, [r7, #4] 8008720: f002 f841 bl 800a7a6 pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U; 8008724: 4b1c ldr r3, [pc, #112] @ (8008798 ) 8008726: 781b ldrb r3, [r3, #0] 8008728: f003 020f and.w r2, r3, #15 800872c: 6879 ldr r1, [r7, #4] 800872e: 4613 mov r3, r2 8008730: 009b lsls r3, r3, #2 8008732: 4413 add r3, r2 8008734: 009b lsls r3, r3, #2 8008736: 440b add r3, r1 8008738: 3323 adds r3, #35 @ 0x23 800873a: 2200 movs r2, #0 800873c: 701a strb r2, [r3, #0] pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U; 800873e: 4b16 ldr r3, [pc, #88] @ (8008798 ) 8008740: 781b ldrb r3, [r3, #0] 8008742: f003 020f and.w r2, r3, #15 8008746: 6879 ldr r1, [r7, #4] 8008748: 4613 mov r3, r2 800874a: 009b lsls r3, r3, #2 800874c: 4413 add r3, r2 800874e: 009b lsls r3, r3, #2 8008750: 440b add r3, r1 8008752: 331c adds r3, #28 8008754: 2200 movs r2, #0 8008756: 601a str r2, [r3, #0] /* Free allocated memory */ if (pdev->pClassDataCmsit[pdev->classId] != NULL) 8008758: 687b ldr r3, [r7, #4] 800875a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800875e: 687b ldr r3, [r7, #4] 8008760: 32b0 adds r2, #176 @ 0xb0 8008762: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008766: 2b00 cmp r3, #0 8008768: d011 beq.n 800878e { (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); 800876a: 687b ldr r3, [r7, #4] 800876c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008770: 687b ldr r3, [r7, #4] 8008772: 32b0 adds r2, #176 @ 0xb0 8008774: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008778: 4618 mov r0, r3 800877a: f002 f95b bl 800aa34 pdev->pClassDataCmsit[pdev->classId] = NULL; 800877e: 687b ldr r3, [r7, #4] 8008780: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008784: 687b ldr r3, [r7, #4] 8008786: 32b0 adds r2, #176 @ 0xb0 8008788: 2100 movs r1, #0 800878a: f843 1022 str.w r1, [r3, r2, lsl #2] } return (uint8_t)USBD_OK; 800878e: 2300 movs r3, #0 } 8008790: 4618 mov r0, r3 8008792: 3708 adds r7, #8 8008794: 46bd mov sp, r7 8008796: bd80 pop {r7, pc} 8008798: 2000013d .word 0x2000013d 0800879c : * @param pdev: instance * @param req: usb requests * @retval status */ static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800879c: b580 push {r7, lr} 800879e: b086 sub sp, #24 80087a0: af00 add r7, sp, #0 80087a2: 6078 str r0, [r7, #4] 80087a4: 6039 str r1, [r7, #0] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 80087a6: 687b ldr r3, [r7, #4] 80087a8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80087ac: 687b ldr r3, [r7, #4] 80087ae: 32b0 adds r2, #176 @ 0xb0 80087b0: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80087b4: 60fb str r3, [r7, #12] USBD_StatusTypeDef ret = USBD_OK; 80087b6: 2300 movs r3, #0 80087b8: 75fb strb r3, [r7, #23] uint16_t len; uint8_t *pbuf; uint16_t status_info = 0U; 80087ba: 2300 movs r3, #0 80087bc: 817b strh r3, [r7, #10] if (hhid == NULL) 80087be: 68fb ldr r3, [r7, #12] 80087c0: 2b00 cmp r3, #0 80087c2: d101 bne.n 80087c8 { return (uint8_t)USBD_FAIL; 80087c4: 2303 movs r3, #3 80087c6: e0e8 b.n 800899a } switch (req->bmRequest & USB_REQ_TYPE_MASK) 80087c8: 683b ldr r3, [r7, #0] 80087ca: 781b ldrb r3, [r3, #0] 80087cc: f003 0360 and.w r3, r3, #96 @ 0x60 80087d0: 2b00 cmp r3, #0 80087d2: d046 beq.n 8008862 80087d4: 2b20 cmp r3, #32 80087d6: f040 80d8 bne.w 800898a { case USB_REQ_TYPE_CLASS : switch (req->bRequest) 80087da: 683b ldr r3, [r7, #0] 80087dc: 785b ldrb r3, [r3, #1] 80087de: 3b02 subs r3, #2 80087e0: 2b09 cmp r3, #9 80087e2: d836 bhi.n 8008852 80087e4: a201 add r2, pc, #4 @ (adr r2, 80087ec ) 80087e6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80087ea: bf00 nop 80087ec: 08008843 .word 0x08008843 80087f0: 08008823 .word 0x08008823 80087f4: 08008853 .word 0x08008853 80087f8: 08008853 .word 0x08008853 80087fc: 08008853 .word 0x08008853 8008800: 08008853 .word 0x08008853 8008804: 08008853 .word 0x08008853 8008808: 08008853 .word 0x08008853 800880c: 08008831 .word 0x08008831 8008810: 08008815 .word 0x08008815 { case USBD_HID_REQ_SET_PROTOCOL: hhid->Protocol = (uint8_t)(req->wValue); 8008814: 683b ldr r3, [r7, #0] 8008816: 885b ldrh r3, [r3, #2] 8008818: b2db uxtb r3, r3 800881a: 461a mov r2, r3 800881c: 68fb ldr r3, [r7, #12] 800881e: 601a str r2, [r3, #0] break; 8008820: e01e b.n 8008860 case USBD_HID_REQ_GET_PROTOCOL: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); 8008822: 68fb ldr r3, [r7, #12] 8008824: 2201 movs r2, #1 8008826: 4619 mov r1, r3 8008828: 6878 ldr r0, [r7, #4] 800882a: f001 fc25 bl 800a078 break; 800882e: e017 b.n 8008860 case USBD_HID_REQ_SET_IDLE: hhid->IdleState = (uint8_t)(req->wValue >> 8); 8008830: 683b ldr r3, [r7, #0] 8008832: 885b ldrh r3, [r3, #2] 8008834: 0a1b lsrs r3, r3, #8 8008836: b29b uxth r3, r3 8008838: b2db uxtb r3, r3 800883a: 461a mov r2, r3 800883c: 68fb ldr r3, [r7, #12] 800883e: 605a str r2, [r3, #4] break; 8008840: e00e b.n 8008860 case USBD_HID_REQ_GET_IDLE: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); 8008842: 68fb ldr r3, [r7, #12] 8008844: 3304 adds r3, #4 8008846: 2201 movs r2, #1 8008848: 4619 mov r1, r3 800884a: 6878 ldr r0, [r7, #4] 800884c: f001 fc14 bl 800a078 break; 8008850: e006 b.n 8008860 default: USBD_CtlError(pdev, req); 8008852: 6839 ldr r1, [r7, #0] 8008854: 6878 ldr r0, [r7, #4] 8008856: f001 fb92 bl 8009f7e ret = USBD_FAIL; 800885a: 2303 movs r3, #3 800885c: 75fb strb r3, [r7, #23] break; 800885e: bf00 nop } break; 8008860: e09a b.n 8008998 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8008862: 683b ldr r3, [r7, #0] 8008864: 785b ldrb r3, [r3, #1] 8008866: 2b0b cmp r3, #11 8008868: f200 8086 bhi.w 8008978 800886c: a201 add r2, pc, #4 @ (adr r2, 8008874 ) 800886e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008872: bf00 nop 8008874: 080088a5 .word 0x080088a5 8008878: 08008987 .word 0x08008987 800887c: 08008979 .word 0x08008979 8008880: 08008979 .word 0x08008979 8008884: 08008979 .word 0x08008979 8008888: 08008979 .word 0x08008979 800888c: 080088cf .word 0x080088cf 8008890: 08008979 .word 0x08008979 8008894: 08008979 .word 0x08008979 8008898: 08008979 .word 0x08008979 800889c: 08008927 .word 0x08008927 80088a0: 08008951 .word 0x08008951 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 80088a4: 687b ldr r3, [r7, #4] 80088a6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80088aa: b2db uxtb r3, r3 80088ac: 2b03 cmp r3, #3 80088ae: d107 bne.n 80088c0 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 80088b0: f107 030a add.w r3, r7, #10 80088b4: 2202 movs r2, #2 80088b6: 4619 mov r1, r3 80088b8: 6878 ldr r0, [r7, #4] 80088ba: f001 fbdd bl 800a078 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 80088be: e063 b.n 8008988 USBD_CtlError(pdev, req); 80088c0: 6839 ldr r1, [r7, #0] 80088c2: 6878 ldr r0, [r7, #4] 80088c4: f001 fb5b bl 8009f7e ret = USBD_FAIL; 80088c8: 2303 movs r3, #3 80088ca: 75fb strb r3, [r7, #23] break; 80088cc: e05c b.n 8008988 case USB_REQ_GET_DESCRIPTOR: if ((req->wValue >> 8) == HID_REPORT_DESC) 80088ce: 683b ldr r3, [r7, #0] 80088d0: 885b ldrh r3, [r3, #2] 80088d2: 0a1b lsrs r3, r3, #8 80088d4: b29b uxth r3, r3 80088d6: 2b22 cmp r3, #34 @ 0x22 80088d8: d108 bne.n 80088ec { len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); 80088da: 683b ldr r3, [r7, #0] 80088dc: 88db ldrh r3, [r3, #6] 80088de: 2b2d cmp r3, #45 @ 0x2d 80088e0: bf28 it cs 80088e2: 232d movcs r3, #45 @ 0x2d 80088e4: 82bb strh r3, [r7, #20] pbuf = HID_MOUSE_ReportDesc; 80088e6: 4b2f ldr r3, [pc, #188] @ (80089a4 ) 80088e8: 613b str r3, [r7, #16] 80088ea: e015 b.n 8008918 } else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) 80088ec: 683b ldr r3, [r7, #0] 80088ee: 885b ldrh r3, [r3, #2] 80088f0: 0a1b lsrs r3, r3, #8 80088f2: b29b uxth r3, r3 80088f4: 2b21 cmp r3, #33 @ 0x21 80088f6: d108 bne.n 800890a { pbuf = USBD_HID_Desc; 80088f8: 4b2b ldr r3, [pc, #172] @ (80089a8 ) 80088fa: 613b str r3, [r7, #16] len = MIN(USB_HID_DESC_SIZ, req->wLength); 80088fc: 683b ldr r3, [r7, #0] 80088fe: 88db ldrh r3, [r3, #6] 8008900: 2b09 cmp r3, #9 8008902: bf28 it cs 8008904: 2309 movcs r3, #9 8008906: 82bb strh r3, [r7, #20] 8008908: e006 b.n 8008918 } else { USBD_CtlError(pdev, req); 800890a: 6839 ldr r1, [r7, #0] 800890c: 6878 ldr r0, [r7, #4] 800890e: f001 fb36 bl 8009f7e ret = USBD_FAIL; 8008912: 2303 movs r3, #3 8008914: 75fb strb r3, [r7, #23] break; 8008916: e037 b.n 8008988 } (void)USBD_CtlSendData(pdev, pbuf, len); 8008918: 8abb ldrh r3, [r7, #20] 800891a: 461a mov r2, r3 800891c: 6939 ldr r1, [r7, #16] 800891e: 6878 ldr r0, [r7, #4] 8008920: f001 fbaa bl 800a078 break; 8008924: e030 b.n 8008988 case USB_REQ_GET_INTERFACE : if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008926: 687b ldr r3, [r7, #4] 8008928: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800892c: b2db uxtb r3, r3 800892e: 2b03 cmp r3, #3 8008930: d107 bne.n 8008942 { (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); 8008932: 68fb ldr r3, [r7, #12] 8008934: 3308 adds r3, #8 8008936: 2201 movs r2, #1 8008938: 4619 mov r1, r3 800893a: 6878 ldr r0, [r7, #4] 800893c: f001 fb9c bl 800a078 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8008940: e022 b.n 8008988 USBD_CtlError(pdev, req); 8008942: 6839 ldr r1, [r7, #0] 8008944: 6878 ldr r0, [r7, #4] 8008946: f001 fb1a bl 8009f7e ret = USBD_FAIL; 800894a: 2303 movs r3, #3 800894c: 75fb strb r3, [r7, #23] break; 800894e: e01b b.n 8008988 case USB_REQ_SET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008950: 687b ldr r3, [r7, #4] 8008952: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008956: b2db uxtb r3, r3 8008958: 2b03 cmp r3, #3 800895a: d106 bne.n 800896a { hhid->AltSetting = (uint8_t)(req->wValue); 800895c: 683b ldr r3, [r7, #0] 800895e: 885b ldrh r3, [r3, #2] 8008960: b2db uxtb r3, r3 8008962: 461a mov r2, r3 8008964: 68fb ldr r3, [r7, #12] 8008966: 609a str r2, [r3, #8] else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8008968: e00e b.n 8008988 USBD_CtlError(pdev, req); 800896a: 6839 ldr r1, [r7, #0] 800896c: 6878 ldr r0, [r7, #4] 800896e: f001 fb06 bl 8009f7e ret = USBD_FAIL; 8008972: 2303 movs r3, #3 8008974: 75fb strb r3, [r7, #23] break; 8008976: e007 b.n 8008988 case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 8008978: 6839 ldr r1, [r7, #0] 800897a: 6878 ldr r0, [r7, #4] 800897c: f001 faff bl 8009f7e ret = USBD_FAIL; 8008980: 2303 movs r3, #3 8008982: 75fb strb r3, [r7, #23] break; 8008984: e000 b.n 8008988 break; 8008986: bf00 nop } break; 8008988: e006 b.n 8008998 default: USBD_CtlError(pdev, req); 800898a: 6839 ldr r1, [r7, #0] 800898c: 6878 ldr r0, [r7, #4] 800898e: f001 faf6 bl 8009f7e ret = USBD_FAIL; 8008992: 2303 movs r3, #3 8008994: 75fb strb r3, [r7, #23] break; 8008996: bf00 nop } return (uint8_t)ret; 8008998: 7dfb ldrb r3, [r7, #23] } 800899a: 4618 mov r0, r3 800899c: 3718 adds r7, #24 800899e: 46bd mov sp, r7 80089a0: bd80 pop {r7, pc} 80089a2: bf00 nop 80089a4: 20000110 .word 0x20000110 80089a8: 200000f8 .word 0x200000f8 080089ac : uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId) { USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) { 80089ac: b580 push {r7, lr} 80089ae: b086 sub sp, #24 80089b0: af00 add r7, sp, #0 80089b2: 60f8 str r0, [r7, #12] 80089b4: 60b9 str r1, [r7, #8] 80089b6: 4613 mov r3, r2 80089b8: 80fb strh r3, [r7, #6] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 80089ba: 68fb ldr r3, [r7, #12] 80089bc: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80089c0: 68fb ldr r3, [r7, #12] 80089c2: 32b0 adds r2, #176 @ 0xb0 80089c4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80089c8: 617b str r3, [r7, #20] #endif /* USE_USBD_COMPOSITE */ if (hhid == NULL) 80089ca: 697b ldr r3, [r7, #20] 80089cc: 2b00 cmp r3, #0 80089ce: d101 bne.n 80089d4 { return (uint8_t)USBD_FAIL; 80089d0: 2303 movs r3, #3 80089d2: e014 b.n 80089fe #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 80089d4: 68fb ldr r3, [r7, #12] 80089d6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80089da: b2db uxtb r3, r3 80089dc: 2b03 cmp r3, #3 80089de: d10d bne.n 80089fc { if (hhid->state == USBD_HID_IDLE) 80089e0: 697b ldr r3, [r7, #20] 80089e2: 7b1b ldrb r3, [r3, #12] 80089e4: 2b00 cmp r3, #0 80089e6: d109 bne.n 80089fc { hhid->state = USBD_HID_BUSY; 80089e8: 697b ldr r3, [r7, #20] 80089ea: 2201 movs r2, #1 80089ec: 731a strb r2, [r3, #12] (void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len); 80089ee: 4b06 ldr r3, [pc, #24] @ (8008a08 ) 80089f0: 7819 ldrb r1, [r3, #0] 80089f2: 88fb ldrh r3, [r7, #6] 80089f4: 68ba ldr r2, [r7, #8] 80089f6: 68f8 ldr r0, [r7, #12] 80089f8: f001 ff7d bl 800a8f6 } } return (uint8_t)USBD_OK; 80089fc: 2300 movs r3, #0 } 80089fe: 4618 mov r0, r3 8008a00: 3718 adds r7, #24 8008a02: 46bd mov sp, r7 8008a04: bd80 pop {r7, pc} 8008a06: bf00 nop 8008a08: 2000013d .word 0x2000013d 08008a0c : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) { 8008a0c: b580 push {r7, lr} 8008a0e: b084 sub sp, #16 8008a10: af00 add r7, sp, #0 8008a12: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8008a14: 2181 movs r1, #129 @ 0x81 8008a16: 4809 ldr r0, [pc, #36] @ (8008a3c ) 8008a18: f000 fc4e bl 80092b8 8008a1c: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 8008a1e: 68fb ldr r3, [r7, #12] 8008a20: 2b00 cmp r3, #0 8008a22: d002 beq.n 8008a2a { pEpDesc->bInterval = HID_FS_BINTERVAL; 8008a24: 68fb ldr r3, [r7, #12] 8008a26: 220a movs r2, #10 8008a28: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 8008a2a: 687b ldr r3, [r7, #4] 8008a2c: 2222 movs r2, #34 @ 0x22 8008a2e: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8008a30: 4b02 ldr r3, [pc, #8] @ (8008a3c ) } 8008a32: 4618 mov r0, r3 8008a34: 3710 adds r7, #16 8008a36: 46bd mov sp, r7 8008a38: bd80 pop {r7, pc} 8008a3a: bf00 nop 8008a3c: 200000d4 .word 0x200000d4 08008a40 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) { 8008a40: b580 push {r7, lr} 8008a42: b084 sub sp, #16 8008a44: af00 add r7, sp, #0 8008a46: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8008a48: 2181 movs r1, #129 @ 0x81 8008a4a: 4809 ldr r0, [pc, #36] @ (8008a70 ) 8008a4c: f000 fc34 bl 80092b8 8008a50: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 8008a52: 68fb ldr r3, [r7, #12] 8008a54: 2b00 cmp r3, #0 8008a56: d002 beq.n 8008a5e { pEpDesc->bInterval = HID_HS_BINTERVAL; 8008a58: 68fb ldr r3, [r7, #12] 8008a5a: 2207 movs r2, #7 8008a5c: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 8008a5e: 687b ldr r3, [r7, #4] 8008a60: 2222 movs r2, #34 @ 0x22 8008a62: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8008a64: 4b02 ldr r3, [pc, #8] @ (8008a70 ) } 8008a66: 4618 mov r0, r3 8008a68: 3710 adds r7, #16 8008a6a: 46bd mov sp, r7 8008a6c: bd80 pop {r7, pc} 8008a6e: bf00 nop 8008a70: 200000d4 .word 0x200000d4 08008a74 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) { 8008a74: b580 push {r7, lr} 8008a76: b084 sub sp, #16 8008a78: af00 add r7, sp, #0 8008a7a: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8008a7c: 2181 movs r1, #129 @ 0x81 8008a7e: 4809 ldr r0, [pc, #36] @ (8008aa4 ) 8008a80: f000 fc1a bl 80092b8 8008a84: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 8008a86: 68fb ldr r3, [r7, #12] 8008a88: 2b00 cmp r3, #0 8008a8a: d002 beq.n 8008a92 { pEpDesc->bInterval = HID_FS_BINTERVAL; 8008a8c: 68fb ldr r3, [r7, #12] 8008a8e: 220a movs r2, #10 8008a90: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 8008a92: 687b ldr r3, [r7, #4] 8008a94: 2222 movs r2, #34 @ 0x22 8008a96: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8008a98: 4b02 ldr r3, [pc, #8] @ (8008aa4 ) } 8008a9a: 4618 mov r0, r3 8008a9c: 3710 adds r7, #16 8008a9e: 46bd mov sp, r7 8008aa0: bd80 pop {r7, pc} 8008aa2: bf00 nop 8008aa4: 200000d4 .word 0x200000d4 08008aa8 : * @param pdev: device instance * @param epnum: endpoint index * @retval status */ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8008aa8: b480 push {r7} 8008aaa: b083 sub sp, #12 8008aac: af00 add r7, sp, #0 8008aae: 6078 str r0, [r7, #4] 8008ab0: 460b mov r3, r1 8008ab2: 70fb strb r3, [r7, #3] UNUSED(epnum); /* Ensure that the FIFO is empty before a new transfer, this condition could be caused by a new transfer before the end of the previous transfer */ ((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE; 8008ab4: 687b ldr r3, [r7, #4] 8008ab6: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008aba: 687b ldr r3, [r7, #4] 8008abc: 32b0 adds r2, #176 @ 0xb0 8008abe: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008ac2: 2200 movs r2, #0 8008ac4: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 8008ac6: 2300 movs r3, #0 } 8008ac8: 4618 mov r0, r3 8008aca: 370c adds r7, #12 8008acc: 46bd mov sp, r7 8008ace: f85d 7b04 ldr.w r7, [sp], #4 8008ad2: 4770 bx lr 08008ad4 : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) { 8008ad4: b480 push {r7} 8008ad6: b083 sub sp, #12 8008ad8: af00 add r7, sp, #0 8008ada: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); 8008adc: 687b ldr r3, [r7, #4] 8008ade: 220a movs r2, #10 8008ae0: 801a strh r2, [r3, #0] return USBD_HID_DeviceQualifierDesc; 8008ae2: 4b03 ldr r3, [pc, #12] @ (8008af0 ) } 8008ae4: 4618 mov r0, r3 8008ae6: 370c adds r7, #12 8008ae8: 46bd mov sp, r7 8008aea: f85d 7b04 ldr.w r7, [sp], #4 8008aee: 4770 bx lr 8008af0: 20000104 .word 0x20000104 08008af4 : * @param id: Low level core index * @retval status: USBD Status */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 8008af4: b580 push {r7, lr} 8008af6: b086 sub sp, #24 8008af8: af00 add r7, sp, #0 8008afa: 60f8 str r0, [r7, #12] 8008afc: 60b9 str r1, [r7, #8] 8008afe: 4613 mov r3, r2 8008b00: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 8008b02: 68fb ldr r3, [r7, #12] 8008b04: 2b00 cmp r3, #0 8008b06: d101 bne.n 8008b0c { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8008b08: 2303 movs r3, #3 8008b0a: e01f b.n 8008b4c pdev->NumClasses = 0; pdev->classId = 0; } #else /* Unlink previous class*/ pdev->pClass[0] = NULL; 8008b0c: 68fb ldr r3, [r7, #12] 8008b0e: 2200 movs r2, #0 8008b10: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 pdev->pUserData[0] = NULL; 8008b14: 68fb ldr r3, [r7, #12] 8008b16: 2200 movs r2, #0 8008b18: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4 #endif /* USE_USBD_COMPOSITE */ pdev->pConfDesc = NULL; 8008b1c: 68fb ldr r3, [r7, #12] 8008b1e: 2200 movs r2, #0 8008b20: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 /* Assign USBD Descriptors */ if (pdesc != NULL) 8008b24: 68bb ldr r3, [r7, #8] 8008b26: 2b00 cmp r3, #0 8008b28: d003 beq.n 8008b32 { pdev->pDesc = pdesc; 8008b2a: 68fb ldr r3, [r7, #12] 8008b2c: 68ba ldr r2, [r7, #8] 8008b2e: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 8008b32: 68fb ldr r3, [r7, #12] 8008b34: 2201 movs r2, #1 8008b36: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->id = id; 8008b3a: 68fb ldr r3, [r7, #12] 8008b3c: 79fa ldrb r2, [r7, #7] 8008b3e: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 8008b40: 68f8 ldr r0, [r7, #12] 8008b42: f001 fda3 bl 800a68c 8008b46: 4603 mov r3, r0 8008b48: 75fb strb r3, [r7, #23] return ret; 8008b4a: 7dfb ldrb r3, [r7, #23] } 8008b4c: 4618 mov r0, r3 8008b4e: 3718 adds r7, #24 8008b50: 46bd mov sp, r7 8008b52: bd80 pop {r7, pc} 08008b54 : * @param pdev: Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 8008b54: b580 push {r7, lr} 8008b56: b084 sub sp, #16 8008b58: af00 add r7, sp, #0 8008b5a: 6078 str r0, [r7, #4] 8008b5c: 6039 str r1, [r7, #0] uint16_t len = 0U; 8008b5e: 2300 movs r3, #0 8008b60: 81fb strh r3, [r7, #14] if (pclass == NULL) 8008b62: 683b ldr r3, [r7, #0] 8008b64: 2b00 cmp r3, #0 8008b66: d101 bne.n 8008b6c { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8008b68: 2303 movs r3, #3 8008b6a: e025 b.n 8008bb8 } /* link the class to the USB Device handle */ pdev->pClass[0] = pclass; 8008b6c: 687b ldr r3, [r7, #4] 8008b6e: 683a ldr r2, [r7, #0] 8008b70: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) 8008b74: 687b ldr r3, [r7, #4] 8008b76: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008b7a: 687b ldr r3, [r7, #4] 8008b7c: 32ae adds r2, #174 @ 0xae 8008b7e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008b82: 6adb ldr r3, [r3, #44] @ 0x2c 8008b84: 2b00 cmp r3, #0 8008b86: d00f beq.n 8008ba8 { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); 8008b88: 687b ldr r3, [r7, #4] 8008b8a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008b8e: 687b ldr r3, [r7, #4] 8008b90: 32ae adds r2, #174 @ 0xae 8008b92: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008b96: 6adb ldr r3, [r3, #44] @ 0x2c 8008b98: f107 020e add.w r2, r7, #14 8008b9c: 4610 mov r0, r2 8008b9e: 4798 blx r3 8008ba0: 4602 mov r2, r0 8008ba2: 687b ldr r3, [r7, #4] 8008ba4: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 } #endif /* USE_USB_FS */ /* Increment the NumClasses */ pdev->NumClasses++; 8008ba8: 687b ldr r3, [r7, #4] 8008baa: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8008bae: 1c5a adds r2, r3, #1 8008bb0: 687b ldr r3, [r7, #4] 8008bb2: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8 return USBD_OK; 8008bb6: 2300 movs r3, #0 } 8008bb8: 4618 mov r0, r3 8008bba: 3710 adds r7, #16 8008bbc: 46bd mov sp, r7 8008bbe: bd80 pop {r7, pc} 08008bc0 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 8008bc0: b580 push {r7, lr} 8008bc2: b082 sub sp, #8 8008bc4: af00 add r7, sp, #0 8008bc6: 6078 str r0, [r7, #4] #ifdef USE_USBD_COMPOSITE pdev->classId = 0U; #endif /* USE_USBD_COMPOSITE */ /* Start the low level driver */ return USBD_LL_Start(pdev); 8008bc8: 6878 ldr r0, [r7, #4] 8008bca: f001 fdab bl 800a724 8008bce: 4603 mov r3, r0 } 8008bd0: 4618 mov r0, r3 8008bd2: 3708 adds r7, #8 8008bd4: 46bd mov sp, r7 8008bd6: bd80 pop {r7, pc} 08008bd8 : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 8008bd8: b480 push {r7} 8008bda: b083 sub sp, #12 8008bdc: af00 add r7, sp, #0 8008bde: 6078 str r0, [r7, #4] return ret; #else /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8008be0: 2300 movs r3, #0 #endif /* USBD_HS_TESTMODE_ENABLE */ } 8008be2: 4618 mov r0, r3 8008be4: 370c adds r7, #12 8008be6: 46bd mov sp, r7 8008be8: f85d 7b04 ldr.w r7, [sp], #4 8008bec: 4770 bx lr 08008bee : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008bee: b580 push {r7, lr} 8008bf0: b084 sub sp, #16 8008bf2: af00 add r7, sp, #0 8008bf4: 6078 str r0, [r7, #4] 8008bf6: 460b mov r3, r1 8008bf8: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8008bfa: 2300 movs r3, #0 8008bfc: 73fb strb r3, [r7, #15] } } } } #else if (pdev->pClass[0] != NULL) 8008bfe: 687b ldr r3, [r7, #4] 8008c00: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008c04: 2b00 cmp r3, #0 8008c06: d009 beq.n 8008c1c { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); 8008c08: 687b ldr r3, [r7, #4] 8008c0a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008c0e: 681b ldr r3, [r3, #0] 8008c10: 78fa ldrb r2, [r7, #3] 8008c12: 4611 mov r1, r2 8008c14: 6878 ldr r0, [r7, #4] 8008c16: 4798 blx r3 8008c18: 4603 mov r3, r0 8008c1a: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8008c1c: 7bfb ldrb r3, [r7, #15] } 8008c1e: 4618 mov r0, r3 8008c20: 3710 adds r7, #16 8008c22: 46bd mov sp, r7 8008c24: bd80 pop {r7, pc} 08008c26 : * @param pdev: device instance * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008c26: b580 push {r7, lr} 8008c28: b084 sub sp, #16 8008c2a: af00 add r7, sp, #0 8008c2c: 6078 str r0, [r7, #4] 8008c2e: 460b mov r3, r1 8008c30: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8008c32: 2300 movs r3, #0 8008c34: 73fb strb r3, [r7, #15] } } } #else /* Clear configuration and De-initialize the Class process */ if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) 8008c36: 687b ldr r3, [r7, #4] 8008c38: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008c3c: 685b ldr r3, [r3, #4] 8008c3e: 78fa ldrb r2, [r7, #3] 8008c40: 4611 mov r1, r2 8008c42: 6878 ldr r0, [r7, #4] 8008c44: 4798 blx r3 8008c46: 4603 mov r3, r0 8008c48: 2b00 cmp r3, #0 8008c4a: d001 beq.n 8008c50 { ret = USBD_FAIL; 8008c4c: 2303 movs r3, #3 8008c4e: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8008c50: 7bfb ldrb r3, [r7, #15] } 8008c52: 4618 mov r0, r3 8008c54: 3710 adds r7, #16 8008c56: 46bd mov sp, r7 8008c58: bd80 pop {r7, pc} 08008c5a : * @param pdev: device instance * @param psetup: setup packet buffer pointer * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 8008c5a: b580 push {r7, lr} 8008c5c: b084 sub sp, #16 8008c5e: af00 add r7, sp, #0 8008c60: 6078 str r0, [r7, #4] 8008c62: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 8008c64: 687b ldr r3, [r7, #4] 8008c66: f203 23aa addw r3, r3, #682 @ 0x2aa 8008c6a: 6839 ldr r1, [r7, #0] 8008c6c: 4618 mov r0, r3 8008c6e: f001 f94c bl 8009f0a pdev->ep0_state = USBD_EP0_SETUP; 8008c72: 687b ldr r3, [r7, #4] 8008c74: 2201 movs r2, #1 8008c76: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep0_data_len = pdev->request.wLength; 8008c7a: 687b ldr r3, [r7, #4] 8008c7c: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0 8008c80: 461a mov r2, r3 8008c82: 687b ldr r3, [r7, #4] 8008c84: f8c3 2298 str.w r2, [r3, #664] @ 0x298 switch (pdev->request.bmRequest & 0x1FU) 8008c88: 687b ldr r3, [r7, #4] 8008c8a: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008c8e: f003 031f and.w r3, r3, #31 8008c92: 2b02 cmp r3, #2 8008c94: d01a beq.n 8008ccc 8008c96: 2b02 cmp r3, #2 8008c98: d822 bhi.n 8008ce0 8008c9a: 2b00 cmp r3, #0 8008c9c: d002 beq.n 8008ca4 8008c9e: 2b01 cmp r3, #1 8008ca0: d00a beq.n 8008cb8 8008ca2: e01d b.n 8008ce0 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 8008ca4: 687b ldr r3, [r7, #4] 8008ca6: f203 23aa addw r3, r3, #682 @ 0x2aa 8008caa: 4619 mov r1, r3 8008cac: 6878 ldr r0, [r7, #4] 8008cae: f000 fb77 bl 80093a0 8008cb2: 4603 mov r3, r0 8008cb4: 73fb strb r3, [r7, #15] break; 8008cb6: e020 b.n 8008cfa case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 8008cb8: 687b ldr r3, [r7, #4] 8008cba: f203 23aa addw r3, r3, #682 @ 0x2aa 8008cbe: 4619 mov r1, r3 8008cc0: 6878 ldr r0, [r7, #4] 8008cc2: f000 fbdf bl 8009484 8008cc6: 4603 mov r3, r0 8008cc8: 73fb strb r3, [r7, #15] break; 8008cca: e016 b.n 8008cfa case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 8008ccc: 687b ldr r3, [r7, #4] 8008cce: f203 23aa addw r3, r3, #682 @ 0x2aa 8008cd2: 4619 mov r1, r3 8008cd4: 6878 ldr r0, [r7, #4] 8008cd6: f000 fc41 bl 800955c 8008cda: 4603 mov r3, r0 8008cdc: 73fb strb r3, [r7, #15] break; 8008cde: e00c b.n 8008cfa default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 8008ce0: 687b ldr r3, [r7, #4] 8008ce2: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008ce6: f023 037f bic.w r3, r3, #127 @ 0x7f 8008cea: b2db uxtb r3, r3 8008cec: 4619 mov r1, r3 8008cee: 6878 ldr r0, [r7, #4] 8008cf0: f001 fd78 bl 800a7e4 8008cf4: 4603 mov r3, r0 8008cf6: 73fb strb r3, [r7, #15] break; 8008cf8: bf00 nop } return ret; 8008cfa: 7bfb ldrb r3, [r7, #15] } 8008cfc: 4618 mov r0, r3 8008cfe: 3710 adds r7, #16 8008d00: 46bd mov sp, r7 8008d02: bd80 pop {r7, pc} 08008d04 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8008d04: b580 push {r7, lr} 8008d06: b086 sub sp, #24 8008d08: af00 add r7, sp, #0 8008d0a: 60f8 str r0, [r7, #12] 8008d0c: 460b mov r3, r1 8008d0e: 607a str r2, [r7, #4] 8008d10: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret = USBD_OK; 8008d12: 2300 movs r3, #0 8008d14: 75fb strb r3, [r7, #23] uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8008d16: 7afb ldrb r3, [r7, #11] 8008d18: 2b00 cmp r3, #0 8008d1a: d177 bne.n 8008e0c { pep = &pdev->ep_out[0]; 8008d1c: 68fb ldr r3, [r7, #12] 8008d1e: f503 73aa add.w r3, r3, #340 @ 0x154 8008d22: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 8008d24: 68fb ldr r3, [r7, #12] 8008d26: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8008d2a: 2b03 cmp r3, #3 8008d2c: f040 80a1 bne.w 8008e72 { if (pep->rem_length > pep->maxpacket) 8008d30: 693b ldr r3, [r7, #16] 8008d32: 685b ldr r3, [r3, #4] 8008d34: 693a ldr r2, [r7, #16] 8008d36: 8992 ldrh r2, [r2, #12] 8008d38: 4293 cmp r3, r2 8008d3a: d91c bls.n 8008d76 { pep->rem_length -= pep->maxpacket; 8008d3c: 693b ldr r3, [r7, #16] 8008d3e: 685b ldr r3, [r3, #4] 8008d40: 693a ldr r2, [r7, #16] 8008d42: 8992 ldrh r2, [r2, #12] 8008d44: 1a9a subs r2, r3, r2 8008d46: 693b ldr r3, [r7, #16] 8008d48: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8008d4a: 693b ldr r3, [r7, #16] 8008d4c: 691b ldr r3, [r3, #16] 8008d4e: 693a ldr r2, [r7, #16] 8008d50: 8992 ldrh r2, [r2, #12] 8008d52: 441a add r2, r3 8008d54: 693b ldr r3, [r7, #16] 8008d56: 611a str r2, [r3, #16] (void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket)); 8008d58: 693b ldr r3, [r7, #16] 8008d5a: 6919 ldr r1, [r3, #16] 8008d5c: 693b ldr r3, [r7, #16] 8008d5e: 899b ldrh r3, [r3, #12] 8008d60: 461a mov r2, r3 8008d62: 693b ldr r3, [r7, #16] 8008d64: 685b ldr r3, [r3, #4] 8008d66: 4293 cmp r3, r2 8008d68: bf38 it cc 8008d6a: 4613 movcc r3, r2 8008d6c: 461a mov r2, r3 8008d6e: 68f8 ldr r0, [r7, #12] 8008d70: f001 f9b1 bl 800a0d6 8008d74: e07d b.n 8008e72 } else { /* Find the class ID relative to the current request */ switch (pdev->request.bmRequest & 0x1FU) 8008d76: 68fb ldr r3, [r7, #12] 8008d78: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008d7c: f003 031f and.w r3, r3, #31 8008d80: 2b02 cmp r3, #2 8008d82: d014 beq.n 8008dae 8008d84: 2b02 cmp r3, #2 8008d86: d81d bhi.n 8008dc4 8008d88: 2b00 cmp r3, #0 8008d8a: d002 beq.n 8008d92 8008d8c: 2b01 cmp r3, #1 8008d8e: d003 beq.n 8008d98 8008d90: e018 b.n 8008dc4 { case USB_REQ_RECIPIENT_DEVICE: /* Device requests must be managed by the first instantiated class (or duplicated by all classes for simplicity) */ idx = 0U; 8008d92: 2300 movs r3, #0 8008d94: 75bb strb r3, [r7, #22] break; 8008d96: e018 b.n 8008dca case USB_REQ_RECIPIENT_INTERFACE: idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); 8008d98: 68fb ldr r3, [r7, #12] 8008d9a: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8008d9e: b2db uxtb r3, r3 8008da0: 4619 mov r1, r3 8008da2: 68f8 ldr r0, [r7, #12] 8008da4: f000 fa6e bl 8009284 8008da8: 4603 mov r3, r0 8008daa: 75bb strb r3, [r7, #22] break; 8008dac: e00d b.n 8008dca case USB_REQ_RECIPIENT_ENDPOINT: idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); 8008dae: 68fb ldr r3, [r7, #12] 8008db0: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8008db4: b2db uxtb r3, r3 8008db6: 4619 mov r1, r3 8008db8: 68f8 ldr r0, [r7, #12] 8008dba: f000 fa70 bl 800929e 8008dbe: 4603 mov r3, r0 8008dc0: 75bb strb r3, [r7, #22] break; 8008dc2: e002 b.n 8008dca default: /* Back to the first class in case of doubt */ idx = 0U; 8008dc4: 2300 movs r3, #0 8008dc6: 75bb strb r3, [r7, #22] break; 8008dc8: bf00 nop } if (idx < USBD_MAX_SUPPORTED_CLASS) 8008dca: 7dbb ldrb r3, [r7, #22] 8008dcc: 2b00 cmp r3, #0 8008dce: d119 bne.n 8008e04 { /* Setup the class ID and route the request to the relative class function */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008dd0: 68fb ldr r3, [r7, #12] 8008dd2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008dd6: b2db uxtb r3, r3 8008dd8: 2b03 cmp r3, #3 8008dda: d113 bne.n 8008e04 { if (pdev->pClass[idx]->EP0_RxReady != NULL) 8008ddc: 7dba ldrb r2, [r7, #22] 8008dde: 68fb ldr r3, [r7, #12] 8008de0: 32ae adds r2, #174 @ 0xae 8008de2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008de6: 691b ldr r3, [r3, #16] 8008de8: 2b00 cmp r3, #0 8008dea: d00b beq.n 8008e04 { pdev->classId = idx; 8008dec: 7dba ldrb r2, [r7, #22] 8008dee: 68fb ldr r3, [r7, #12] 8008df0: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[idx]->EP0_RxReady(pdev); 8008df4: 7dba ldrb r2, [r7, #22] 8008df6: 68fb ldr r3, [r7, #12] 8008df8: 32ae adds r2, #174 @ 0xae 8008dfa: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008dfe: 691b ldr r3, [r3, #16] 8008e00: 68f8 ldr r0, [r7, #12] 8008e02: 4798 blx r3 } } } (void)USBD_CtlSendStatus(pdev); 8008e04: 68f8 ldr r0, [r7, #12] 8008e06: f001 f977 bl 800a0f8 8008e0a: e032 b.n 8008e72 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); 8008e0c: 7afb ldrb r3, [r7, #11] 8008e0e: f003 037f and.w r3, r3, #127 @ 0x7f 8008e12: b2db uxtb r3, r3 8008e14: 4619 mov r1, r3 8008e16: 68f8 ldr r0, [r7, #12] 8008e18: f000 fa41 bl 800929e 8008e1c: 4603 mov r3, r0 8008e1e: 75bb strb r3, [r7, #22] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8008e20: 7dbb ldrb r3, [r7, #22] 8008e22: 2bff cmp r3, #255 @ 0xff 8008e24: d025 beq.n 8008e72 8008e26: 7dbb ldrb r3, [r7, #22] 8008e28: 2b00 cmp r3, #0 8008e2a: d122 bne.n 8008e72 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008e2c: 68fb ldr r3, [r7, #12] 8008e2e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008e32: b2db uxtb r3, r3 8008e34: 2b03 cmp r3, #3 8008e36: d117 bne.n 8008e68 { if (pdev->pClass[idx]->DataOut != NULL) 8008e38: 7dba ldrb r2, [r7, #22] 8008e3a: 68fb ldr r3, [r7, #12] 8008e3c: 32ae adds r2, #174 @ 0xae 8008e3e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008e42: 699b ldr r3, [r3, #24] 8008e44: 2b00 cmp r3, #0 8008e46: d00f beq.n 8008e68 { pdev->classId = idx; 8008e48: 7dba ldrb r2, [r7, #22] 8008e4a: 68fb ldr r3, [r7, #12] 8008e4c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); 8008e50: 7dba ldrb r2, [r7, #22] 8008e52: 68fb ldr r3, [r7, #12] 8008e54: 32ae adds r2, #174 @ 0xae 8008e56: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008e5a: 699b ldr r3, [r3, #24] 8008e5c: 7afa ldrb r2, [r7, #11] 8008e5e: 4611 mov r1, r2 8008e60: 68f8 ldr r0, [r7, #12] 8008e62: 4798 blx r3 8008e64: 4603 mov r3, r0 8008e66: 75fb strb r3, [r7, #23] } } if (ret != USBD_OK) 8008e68: 7dfb ldrb r3, [r7, #23] 8008e6a: 2b00 cmp r3, #0 8008e6c: d001 beq.n 8008e72 { return ret; 8008e6e: 7dfb ldrb r3, [r7, #23] 8008e70: e000 b.n 8008e74 } } } return USBD_OK; 8008e72: 2300 movs r3, #0 } 8008e74: 4618 mov r0, r3 8008e76: 3718 adds r7, #24 8008e78: 46bd mov sp, r7 8008e7a: bd80 pop {r7, pc} 08008e7c : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8008e7c: b580 push {r7, lr} 8008e7e: b086 sub sp, #24 8008e80: af00 add r7, sp, #0 8008e82: 60f8 str r0, [r7, #12] 8008e84: 460b mov r3, r1 8008e86: 607a str r2, [r7, #4] 8008e88: 72fb strb r3, [r7, #11] USBD_StatusTypeDef ret; uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8008e8a: 7afb ldrb r3, [r7, #11] 8008e8c: 2b00 cmp r3, #0 8008e8e: d178 bne.n 8008f82 { pep = &pdev->ep_in[0]; 8008e90: 68fb ldr r3, [r7, #12] 8008e92: 3314 adds r3, #20 8008e94: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 8008e96: 68fb ldr r3, [r7, #12] 8008e98: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8008e9c: 2b02 cmp r3, #2 8008e9e: d163 bne.n 8008f68 { if (pep->rem_length > pep->maxpacket) 8008ea0: 693b ldr r3, [r7, #16] 8008ea2: 685b ldr r3, [r3, #4] 8008ea4: 693a ldr r2, [r7, #16] 8008ea6: 8992 ldrh r2, [r2, #12] 8008ea8: 4293 cmp r3, r2 8008eaa: d91c bls.n 8008ee6 { pep->rem_length -= pep->maxpacket; 8008eac: 693b ldr r3, [r7, #16] 8008eae: 685b ldr r3, [r3, #4] 8008eb0: 693a ldr r2, [r7, #16] 8008eb2: 8992 ldrh r2, [r2, #12] 8008eb4: 1a9a subs r2, r3, r2 8008eb6: 693b ldr r3, [r7, #16] 8008eb8: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8008eba: 693b ldr r3, [r7, #16] 8008ebc: 691b ldr r3, [r3, #16] 8008ebe: 693a ldr r2, [r7, #16] 8008ec0: 8992 ldrh r2, [r2, #12] 8008ec2: 441a add r2, r3 8008ec4: 693b ldr r3, [r7, #16] 8008ec6: 611a str r2, [r3, #16] (void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length); 8008ec8: 693b ldr r3, [r7, #16] 8008eca: 6919 ldr r1, [r3, #16] 8008ecc: 693b ldr r3, [r7, #16] 8008ece: 685b ldr r3, [r3, #4] 8008ed0: 461a mov r2, r3 8008ed2: 68f8 ldr r0, [r7, #12] 8008ed4: f001 f8ee bl 800a0b4 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8008ed8: 2300 movs r3, #0 8008eda: 2200 movs r2, #0 8008edc: 2100 movs r1, #0 8008ede: 68f8 ldr r0, [r7, #12] 8008ee0: f001 fd2a bl 800a938 8008ee4: e040 b.n 8008f68 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 8008ee6: 693b ldr r3, [r7, #16] 8008ee8: 899b ldrh r3, [r3, #12] 8008eea: 461a mov r2, r3 8008eec: 693b ldr r3, [r7, #16] 8008eee: 685b ldr r3, [r3, #4] 8008ef0: 429a cmp r2, r3 8008ef2: d11c bne.n 8008f2e (pep->total_length >= pep->maxpacket) && 8008ef4: 693b ldr r3, [r7, #16] 8008ef6: 681b ldr r3, [r3, #0] 8008ef8: 693a ldr r2, [r7, #16] 8008efa: 8992 ldrh r2, [r2, #12] if ((pep->maxpacket == pep->rem_length) && 8008efc: 4293 cmp r3, r2 8008efe: d316 bcc.n 8008f2e (pep->total_length < pdev->ep0_data_len)) 8008f00: 693b ldr r3, [r7, #16] 8008f02: 681a ldr r2, [r3, #0] 8008f04: 68fb ldr r3, [r7, #12] 8008f06: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 (pep->total_length >= pep->maxpacket) && 8008f0a: 429a cmp r2, r3 8008f0c: d20f bcs.n 8008f2e { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 8008f0e: 2200 movs r2, #0 8008f10: 2100 movs r1, #0 8008f12: 68f8 ldr r0, [r7, #12] 8008f14: f001 f8ce bl 800a0b4 pdev->ep0_data_len = 0U; 8008f18: 68fb ldr r3, [r7, #12] 8008f1a: 2200 movs r2, #0 8008f1c: f8c3 2298 str.w r2, [r3, #664] @ 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8008f20: 2300 movs r3, #0 8008f22: 2200 movs r2, #0 8008f24: 2100 movs r1, #0 8008f26: 68f8 ldr r0, [r7, #12] 8008f28: f001 fd06 bl 800a938 8008f2c: e01c b.n 8008f68 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008f2e: 68fb ldr r3, [r7, #12] 8008f30: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008f34: b2db uxtb r3, r3 8008f36: 2b03 cmp r3, #3 8008f38: d10f bne.n 8008f5a { if (pdev->pClass[0]->EP0_TxSent != NULL) 8008f3a: 68fb ldr r3, [r7, #12] 8008f3c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008f40: 68db ldr r3, [r3, #12] 8008f42: 2b00 cmp r3, #0 8008f44: d009 beq.n 8008f5a { pdev->classId = 0U; 8008f46: 68fb ldr r3, [r7, #12] 8008f48: 2200 movs r2, #0 8008f4a: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[0]->EP0_TxSent(pdev); 8008f4e: 68fb ldr r3, [r7, #12] 8008f50: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008f54: 68db ldr r3, [r3, #12] 8008f56: 68f8 ldr r0, [r7, #12] 8008f58: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 8008f5a: 2180 movs r1, #128 @ 0x80 8008f5c: 68f8 ldr r0, [r7, #12] 8008f5e: f001 fc41 bl 800a7e4 (void)USBD_CtlReceiveStatus(pdev); 8008f62: 68f8 ldr r0, [r7, #12] 8008f64: f001 f8db bl 800a11e } } } if (pdev->dev_test_mode != 0U) 8008f68: 68fb ldr r3, [r7, #12] 8008f6a: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 8008f6e: 2b00 cmp r3, #0 8008f70: d03a beq.n 8008fe8 { (void)USBD_RunTestMode(pdev); 8008f72: 68f8 ldr r0, [r7, #12] 8008f74: f7ff fe30 bl 8008bd8 pdev->dev_test_mode = 0U; 8008f78: 68fb ldr r3, [r7, #12] 8008f7a: 2200 movs r2, #0 8008f7c: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 8008f80: e032 b.n 8008fe8 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); 8008f82: 7afb ldrb r3, [r7, #11] 8008f84: f063 037f orn r3, r3, #127 @ 0x7f 8008f88: b2db uxtb r3, r3 8008f8a: 4619 mov r1, r3 8008f8c: 68f8 ldr r0, [r7, #12] 8008f8e: f000 f986 bl 800929e 8008f92: 4603 mov r3, r0 8008f94: 75fb strb r3, [r7, #23] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8008f96: 7dfb ldrb r3, [r7, #23] 8008f98: 2bff cmp r3, #255 @ 0xff 8008f9a: d025 beq.n 8008fe8 8008f9c: 7dfb ldrb r3, [r7, #23] 8008f9e: 2b00 cmp r3, #0 8008fa0: d122 bne.n 8008fe8 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008fa2: 68fb ldr r3, [r7, #12] 8008fa4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008fa8: b2db uxtb r3, r3 8008faa: 2b03 cmp r3, #3 8008fac: d11c bne.n 8008fe8 { if (pdev->pClass[idx]->DataIn != NULL) 8008fae: 7dfa ldrb r2, [r7, #23] 8008fb0: 68fb ldr r3, [r7, #12] 8008fb2: 32ae adds r2, #174 @ 0xae 8008fb4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008fb8: 695b ldr r3, [r3, #20] 8008fba: 2b00 cmp r3, #0 8008fbc: d014 beq.n 8008fe8 { pdev->classId = idx; 8008fbe: 7dfa ldrb r2, [r7, #23] 8008fc0: 68fb ldr r3, [r7, #12] 8008fc2: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); 8008fc6: 7dfa ldrb r2, [r7, #23] 8008fc8: 68fb ldr r3, [r7, #12] 8008fca: 32ae adds r2, #174 @ 0xae 8008fcc: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008fd0: 695b ldr r3, [r3, #20] 8008fd2: 7afa ldrb r2, [r7, #11] 8008fd4: 4611 mov r1, r2 8008fd6: 68f8 ldr r0, [r7, #12] 8008fd8: 4798 blx r3 8008fda: 4603 mov r3, r0 8008fdc: 75bb strb r3, [r7, #22] if (ret != USBD_OK) 8008fde: 7dbb ldrb r3, [r7, #22] 8008fe0: 2b00 cmp r3, #0 8008fe2: d001 beq.n 8008fe8 { return ret; 8008fe4: 7dbb ldrb r3, [r7, #22] 8008fe6: e000 b.n 8008fea } } } } return USBD_OK; 8008fe8: 2300 movs r3, #0 } 8008fea: 4618 mov r0, r3 8008fec: 3718 adds r7, #24 8008fee: 46bd mov sp, r7 8008ff0: bd80 pop {r7, pc} 08008ff2 : * Handle Reset event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 8008ff2: b580 push {r7, lr} 8008ff4: b084 sub sp, #16 8008ff6: af00 add r7, sp, #0 8008ff8: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 8008ffa: 2300 movs r3, #0 8008ffc: 73fb strb r3, [r7, #15] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 8008ffe: 687b ldr r3, [r7, #4] 8009000: 2201 movs r2, #1 8009002: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->ep0_state = USBD_EP0_IDLE; 8009006: 687b ldr r3, [r7, #4] 8009008: 2200 movs r2, #0 800900a: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->dev_config = 0U; 800900e: 687b ldr r3, [r7, #4] 8009010: 2200 movs r2, #0 8009012: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 8009014: 687b ldr r3, [r7, #4] 8009016: 2200 movs r2, #0 8009018: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 pdev->dev_test_mode = 0U; 800901c: 687b ldr r3, [r7, #4] 800901e: 2200 movs r2, #0 8009020: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 } } } #else if (pdev->pClass[0] != NULL) 8009024: 687b ldr r3, [r7, #4] 8009026: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800902a: 2b00 cmp r3, #0 800902c: d014 beq.n 8009058 { if (pdev->pClass[0]->DeInit != NULL) 800902e: 687b ldr r3, [r7, #4] 8009030: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009034: 685b ldr r3, [r3, #4] 8009036: 2b00 cmp r3, #0 8009038: d00e beq.n 8009058 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) 800903a: 687b ldr r3, [r7, #4] 800903c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009040: 685b ldr r3, [r3, #4] 8009042: 687a ldr r2, [r7, #4] 8009044: 6852 ldr r2, [r2, #4] 8009046: b2d2 uxtb r2, r2 8009048: 4611 mov r1, r2 800904a: 6878 ldr r0, [r7, #4] 800904c: 4798 blx r3 800904e: 4603 mov r3, r0 8009050: 2b00 cmp r3, #0 8009052: d001 beq.n 8009058 { ret = USBD_FAIL; 8009054: 2303 movs r3, #3 8009056: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8009058: 2340 movs r3, #64 @ 0x40 800905a: 2200 movs r2, #0 800905c: 2100 movs r1, #0 800905e: 6878 ldr r0, [r7, #4] 8009060: f001 fb7b bl 800a75a pdev->ep_out[0x00U & 0xFU].is_used = 1U; 8009064: 687b ldr r3, [r7, #4] 8009066: 2201 movs r2, #1 8009068: f883 2163 strb.w r2, [r3, #355] @ 0x163 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 800906c: 687b ldr r3, [r7, #4] 800906e: 2240 movs r2, #64 @ 0x40 8009070: f8a3 2160 strh.w r2, [r3, #352] @ 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8009074: 2340 movs r3, #64 @ 0x40 8009076: 2200 movs r2, #0 8009078: 2180 movs r1, #128 @ 0x80 800907a: 6878 ldr r0, [r7, #4] 800907c: f001 fb6d bl 800a75a pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8009080: 687b ldr r3, [r7, #4] 8009082: 2201 movs r2, #1 8009084: f883 2023 strb.w r2, [r3, #35] @ 0x23 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8009088: 687b ldr r3, [r7, #4] 800908a: 2240 movs r2, #64 @ 0x40 800908c: 841a strh r2, [r3, #32] return ret; 800908e: 7bfb ldrb r3, [r7, #15] } 8009090: 4618 mov r0, r3 8009092: 3710 adds r7, #16 8009094: 46bd mov sp, r7 8009096: bd80 pop {r7, pc} 08009098 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8009098: b480 push {r7} 800909a: b083 sub sp, #12 800909c: af00 add r7, sp, #0 800909e: 6078 str r0, [r7, #4] 80090a0: 460b mov r3, r1 80090a2: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 80090a4: 687b ldr r3, [r7, #4] 80090a6: 78fa ldrb r2, [r7, #3] 80090a8: 741a strb r2, [r3, #16] return USBD_OK; 80090aa: 2300 movs r3, #0 } 80090ac: 4618 mov r0, r3 80090ae: 370c adds r7, #12 80090b0: 46bd mov sp, r7 80090b2: f85d 7b04 ldr.w r7, [sp], #4 80090b6: 4770 bx lr 080090b8 : * Handle Suspend event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 80090b8: b480 push {r7} 80090ba: b083 sub sp, #12 80090bc: af00 add r7, sp, #0 80090be: 6078 str r0, [r7, #4] if (pdev->dev_state != USBD_STATE_SUSPENDED) 80090c0: 687b ldr r3, [r7, #4] 80090c2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80090c6: b2db uxtb r3, r3 80090c8: 2b04 cmp r3, #4 80090ca: d006 beq.n 80090da { pdev->dev_old_state = pdev->dev_state; 80090cc: 687b ldr r3, [r7, #4] 80090ce: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80090d2: b2da uxtb r2, r3 80090d4: 687b ldr r3, [r7, #4] 80090d6: f883 229d strb.w r2, [r3, #669] @ 0x29d } pdev->dev_state = USBD_STATE_SUSPENDED; 80090da: 687b ldr r3, [r7, #4] 80090dc: 2204 movs r2, #4 80090de: f883 229c strb.w r2, [r3, #668] @ 0x29c return USBD_OK; 80090e2: 2300 movs r3, #0 } 80090e4: 4618 mov r0, r3 80090e6: 370c adds r7, #12 80090e8: 46bd mov sp, r7 80090ea: f85d 7b04 ldr.w r7, [sp], #4 80090ee: 4770 bx lr 080090f0 : * Handle Resume event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 80090f0: b480 push {r7} 80090f2: b083 sub sp, #12 80090f4: af00 add r7, sp, #0 80090f6: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 80090f8: 687b ldr r3, [r7, #4] 80090fa: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80090fe: b2db uxtb r3, r3 8009100: 2b04 cmp r3, #4 8009102: d106 bne.n 8009112 { pdev->dev_state = pdev->dev_old_state; 8009104: 687b ldr r3, [r7, #4] 8009106: f893 329d ldrb.w r3, [r3, #669] @ 0x29d 800910a: b2da uxtb r2, r3 800910c: 687b ldr r3, [r7, #4] 800910e: f883 229c strb.w r2, [r3, #668] @ 0x29c } return USBD_OK; 8009112: 2300 movs r3, #0 } 8009114: 4618 mov r0, r3 8009116: 370c adds r7, #12 8009118: 46bd mov sp, r7 800911a: f85d 7b04 ldr.w r7, [sp], #4 800911e: 4770 bx lr 08009120 : * Handle SOF event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 8009120: b580 push {r7, lr} 8009122: b082 sub sp, #8 8009124: af00 add r7, sp, #0 8009126: 6078 str r0, [r7, #4] /* The SOF event can be distributed for all classes that support it */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009128: 687b ldr r3, [r7, #4] 800912a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800912e: b2db uxtb r3, r3 8009130: 2b03 cmp r3, #3 8009132: d110 bne.n 8009156 } } } } #else if (pdev->pClass[0] != NULL) 8009134: 687b ldr r3, [r7, #4] 8009136: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800913a: 2b00 cmp r3, #0 800913c: d00b beq.n 8009156 { if (pdev->pClass[0]->SOF != NULL) 800913e: 687b ldr r3, [r7, #4] 8009140: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009144: 69db ldr r3, [r3, #28] 8009146: 2b00 cmp r3, #0 8009148: d005 beq.n 8009156 { (void)pdev->pClass[0]->SOF(pdev); 800914a: 687b ldr r3, [r7, #4] 800914c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009150: 69db ldr r3, [r3, #28] 8009152: 6878 ldr r0, [r7, #4] 8009154: 4798 blx r3 } } #endif /* USE_USBD_COMPOSITE */ } return USBD_OK; 8009156: 2300 movs r3, #0 } 8009158: 4618 mov r0, r3 800915a: 3708 adds r7, #8 800915c: 46bd mov sp, r7 800915e: bd80 pop {r7, pc} 08009160 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009160: b580 push {r7, lr} 8009162: b082 sub sp, #8 8009164: af00 add r7, sp, #0 8009166: 6078 str r0, [r7, #4] 8009168: 460b mov r3, r1 800916a: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 800916c: 687b ldr r3, [r7, #4] 800916e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009172: 687b ldr r3, [r7, #4] 8009174: 32ae adds r2, #174 @ 0xae 8009176: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800917a: 2b00 cmp r3, #0 800917c: d101 bne.n 8009182 { return USBD_FAIL; 800917e: 2303 movs r3, #3 8009180: e01c b.n 80091bc } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009182: 687b ldr r3, [r7, #4] 8009184: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009188: b2db uxtb r3, r3 800918a: 2b03 cmp r3, #3 800918c: d115 bne.n 80091ba { if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL) 800918e: 687b ldr r3, [r7, #4] 8009190: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009194: 687b ldr r3, [r7, #4] 8009196: 32ae adds r2, #174 @ 0xae 8009198: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800919c: 6a1b ldr r3, [r3, #32] 800919e: 2b00 cmp r3, #0 80091a0: d00b beq.n 80091ba { (void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum); 80091a2: 687b ldr r3, [r7, #4] 80091a4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80091a8: 687b ldr r3, [r7, #4] 80091aa: 32ae adds r2, #174 @ 0xae 80091ac: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80091b0: 6a1b ldr r3, [r3, #32] 80091b2: 78fa ldrb r2, [r7, #3] 80091b4: 4611 mov r1, r2 80091b6: 6878 ldr r0, [r7, #4] 80091b8: 4798 blx r3 } } return USBD_OK; 80091ba: 2300 movs r3, #0 } 80091bc: 4618 mov r0, r3 80091be: 3708 adds r7, #8 80091c0: 46bd mov sp, r7 80091c2: bd80 pop {r7, pc} 080091c4 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 80091c4: b580 push {r7, lr} 80091c6: b082 sub sp, #8 80091c8: af00 add r7, sp, #0 80091ca: 6078 str r0, [r7, #4] 80091cc: 460b mov r3, r1 80091ce: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 80091d0: 687b ldr r3, [r7, #4] 80091d2: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80091d6: 687b ldr r3, [r7, #4] 80091d8: 32ae adds r2, #174 @ 0xae 80091da: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80091de: 2b00 cmp r3, #0 80091e0: d101 bne.n 80091e6 { return USBD_FAIL; 80091e2: 2303 movs r3, #3 80091e4: e01c b.n 8009220 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 80091e6: 687b ldr r3, [r7, #4] 80091e8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80091ec: b2db uxtb r3, r3 80091ee: 2b03 cmp r3, #3 80091f0: d115 bne.n 800921e { if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL) 80091f2: 687b ldr r3, [r7, #4] 80091f4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80091f8: 687b ldr r3, [r7, #4] 80091fa: 32ae adds r2, #174 @ 0xae 80091fc: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009200: 6a5b ldr r3, [r3, #36] @ 0x24 8009202: 2b00 cmp r3, #0 8009204: d00b beq.n 800921e { (void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum); 8009206: 687b ldr r3, [r7, #4] 8009208: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800920c: 687b ldr r3, [r7, #4] 800920e: 32ae adds r2, #174 @ 0xae 8009210: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009214: 6a5b ldr r3, [r3, #36] @ 0x24 8009216: 78fa ldrb r2, [r7, #3] 8009218: 4611 mov r1, r2 800921a: 6878 ldr r0, [r7, #4] 800921c: 4798 blx r3 } } return USBD_OK; 800921e: 2300 movs r3, #0 } 8009220: 4618 mov r0, r3 8009222: 3708 adds r7, #8 8009224: 46bd mov sp, r7 8009226: bd80 pop {r7, pc} 08009228 : * Handle device connection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { 8009228: b480 push {r7} 800922a: b083 sub sp, #12 800922c: af00 add r7, sp, #0 800922e: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8009230: 2300 movs r3, #0 } 8009232: 4618 mov r0, r3 8009234: 370c adds r7, #12 8009236: 46bd mov sp, r7 8009238: f85d 7b04 ldr.w r7, [sp], #4 800923c: 4770 bx lr 0800923e : * Handle device disconnection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { 800923e: b580 push {r7, lr} 8009240: b084 sub sp, #16 8009242: af00 add r7, sp, #0 8009244: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 8009246: 2300 movs r3, #0 8009248: 73fb strb r3, [r7, #15] /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; 800924a: 687b ldr r3, [r7, #4] 800924c: 2201 movs r2, #1 800924e: f883 229c strb.w r2, [r3, #668] @ 0x29c } } } } #else if (pdev->pClass[0] != NULL) 8009252: 687b ldr r3, [r7, #4] 8009254: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009258: 2b00 cmp r3, #0 800925a: d00e beq.n 800927a { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U) 800925c: 687b ldr r3, [r7, #4] 800925e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009262: 685b ldr r3, [r3, #4] 8009264: 687a ldr r2, [r7, #4] 8009266: 6852 ldr r2, [r2, #4] 8009268: b2d2 uxtb r2, r2 800926a: 4611 mov r1, r2 800926c: 6878 ldr r0, [r7, #4] 800926e: 4798 blx r3 8009270: 4603 mov r3, r0 8009272: 2b00 cmp r3, #0 8009274: d001 beq.n 800927a { ret = USBD_FAIL; 8009276: 2303 movs r3, #3 8009278: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ return ret; 800927a: 7bfb ldrb r3, [r7, #15] } 800927c: 4618 mov r0, r3 800927e: 3710 adds r7, #16 8009280: 46bd mov sp, r7 8009282: bd80 pop {r7, pc} 08009284 : * @param pdev: device instance * @param index : selected interface number * @retval index of the class using the selected interface number. OxFF if no class found. */ uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) { 8009284: b480 push {r7} 8009286: b083 sub sp, #12 8009288: af00 add r7, sp, #0 800928a: 6078 str r0, [r7, #4] 800928c: 460b mov r3, r1 800928e: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009290: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8009292: 4618 mov r0, r3 8009294: 370c adds r7, #12 8009296: 46bd mov sp, r7 8009298: f85d 7b04 ldr.w r7, [sp], #4 800929c: 4770 bx lr 0800929e : * @param pdev: device instance * @param index : selected endpoint number * @retval index of the class using the selected endpoint number. 0xFF if no class found. */ uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) { 800929e: b480 push {r7} 80092a0: b083 sub sp, #12 80092a2: af00 add r7, sp, #0 80092a4: 6078 str r0, [r7, #4] 80092a6: 460b mov r3, r1 80092a8: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 80092aa: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 80092ac: 4618 mov r0, r3 80092ae: 370c adds r7, #12 80092b0: 46bd mov sp, r7 80092b2: f85d 7b04 ldr.w r7, [sp], #4 80092b6: 4770 bx lr 080092b8 : * @param pConfDesc: pointer to Bos descriptor * @param EpAddr: endpoint address * @retval pointer to video endpoint descriptor */ void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) { 80092b8: b580 push {r7, lr} 80092ba: b086 sub sp, #24 80092bc: af00 add r7, sp, #0 80092be: 6078 str r0, [r7, #4] 80092c0: 460b mov r3, r1 80092c2: 70fb strb r3, [r7, #3] USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; 80092c4: 687b ldr r3, [r7, #4] 80092c6: 617b str r3, [r7, #20] USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; 80092c8: 687b ldr r3, [r7, #4] 80092ca: 60fb str r3, [r7, #12] USBD_EpDescTypeDef *pEpDesc = NULL; 80092cc: 2300 movs r3, #0 80092ce: 613b str r3, [r7, #16] uint16_t ptr; if (desc->wTotalLength > desc->bLength) 80092d0: 68fb ldr r3, [r7, #12] 80092d2: 885b ldrh r3, [r3, #2] 80092d4: b29b uxth r3, r3 80092d6: 68fa ldr r2, [r7, #12] 80092d8: 7812 ldrb r2, [r2, #0] 80092da: 4293 cmp r3, r2 80092dc: d91f bls.n 800931e { ptr = desc->bLength; 80092de: 68fb ldr r3, [r7, #12] 80092e0: 781b ldrb r3, [r3, #0] 80092e2: 817b strh r3, [r7, #10] while (ptr < desc->wTotalLength) 80092e4: e013 b.n 800930e { pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); 80092e6: f107 030a add.w r3, r7, #10 80092ea: 4619 mov r1, r3 80092ec: 6978 ldr r0, [r7, #20] 80092ee: f000 f81b bl 8009328 80092f2: 6178 str r0, [r7, #20] if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) 80092f4: 697b ldr r3, [r7, #20] 80092f6: 785b ldrb r3, [r3, #1] 80092f8: 2b05 cmp r3, #5 80092fa: d108 bne.n 800930e { pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; 80092fc: 697b ldr r3, [r7, #20] 80092fe: 613b str r3, [r7, #16] if (pEpDesc->bEndpointAddress == EpAddr) 8009300: 693b ldr r3, [r7, #16] 8009302: 789b ldrb r3, [r3, #2] 8009304: 78fa ldrb r2, [r7, #3] 8009306: 429a cmp r2, r3 8009308: d008 beq.n 800931c { break; } else { pEpDesc = NULL; 800930a: 2300 movs r3, #0 800930c: 613b str r3, [r7, #16] while (ptr < desc->wTotalLength) 800930e: 68fb ldr r3, [r7, #12] 8009310: 885b ldrh r3, [r3, #2] 8009312: b29a uxth r2, r3 8009314: 897b ldrh r3, [r7, #10] 8009316: 429a cmp r2, r3 8009318: d8e5 bhi.n 80092e6 800931a: e000 b.n 800931e break; 800931c: bf00 nop } } } } return (void *)pEpDesc; 800931e: 693b ldr r3, [r7, #16] } 8009320: 4618 mov r0, r3 8009322: 3718 adds r7, #24 8009324: 46bd mov sp, r7 8009326: bd80 pop {r7, pc} 08009328 : * @param buf: Buffer where the descriptor is available * @param ptr: data pointer inside the descriptor * @retval next header */ USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) { 8009328: b480 push {r7} 800932a: b085 sub sp, #20 800932c: af00 add r7, sp, #0 800932e: 6078 str r0, [r7, #4] 8009330: 6039 str r1, [r7, #0] USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; 8009332: 687b ldr r3, [r7, #4] 8009334: 60fb str r3, [r7, #12] *ptr += pnext->bLength; 8009336: 683b ldr r3, [r7, #0] 8009338: 881b ldrh r3, [r3, #0] 800933a: 68fa ldr r2, [r7, #12] 800933c: 7812 ldrb r2, [r2, #0] 800933e: 4413 add r3, r2 8009340: b29a uxth r2, r3 8009342: 683b ldr r3, [r7, #0] 8009344: 801a strh r2, [r3, #0] pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); 8009346: 68fb ldr r3, [r7, #12] 8009348: 781b ldrb r3, [r3, #0] 800934a: 461a mov r2, r3 800934c: 687b ldr r3, [r7, #4] 800934e: 4413 add r3, r2 8009350: 60fb str r3, [r7, #12] return (pnext); 8009352: 68fb ldr r3, [r7, #12] } 8009354: 4618 mov r0, r3 8009356: 3714 adds r7, #20 8009358: 46bd mov sp, r7 800935a: f85d 7b04 ldr.w r7, [sp], #4 800935e: 4770 bx lr 08009360 : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 8009360: b480 push {r7} 8009362: b087 sub sp, #28 8009364: af00 add r7, sp, #0 8009366: 6078 str r0, [r7, #4] uint16_t _SwapVal; uint16_t _Byte1; uint16_t _Byte2; uint8_t *_pbuff = addr; 8009368: 687b ldr r3, [r7, #4] 800936a: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 800936c: 697b ldr r3, [r7, #20] 800936e: 781b ldrb r3, [r3, #0] 8009370: 827b strh r3, [r7, #18] _pbuff++; 8009372: 697b ldr r3, [r7, #20] 8009374: 3301 adds r3, #1 8009376: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 8009378: 697b ldr r3, [r7, #20] 800937a: 781b ldrb r3, [r3, #0] 800937c: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 800937e: f9b7 3010 ldrsh.w r3, [r7, #16] 8009382: 021b lsls r3, r3, #8 8009384: b21a sxth r2, r3 8009386: f9b7 3012 ldrsh.w r3, [r7, #18] 800938a: 4313 orrs r3, r2 800938c: b21b sxth r3, r3 800938e: 81fb strh r3, [r7, #14] return _SwapVal; 8009390: 89fb ldrh r3, [r7, #14] } 8009392: 4618 mov r0, r3 8009394: 371c adds r7, #28 8009396: 46bd mov sp, r7 8009398: f85d 7b04 ldr.w r7, [sp], #4 800939c: 4770 bx lr ... 080093a0 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80093a0: b580 push {r7, lr} 80093a2: b084 sub sp, #16 80093a4: af00 add r7, sp, #0 80093a6: 6078 str r0, [r7, #4] 80093a8: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 80093aa: 2300 movs r3, #0 80093ac: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 80093ae: 683b ldr r3, [r7, #0] 80093b0: 781b ldrb r3, [r3, #0] 80093b2: f003 0360 and.w r3, r3, #96 @ 0x60 80093b6: 2b40 cmp r3, #64 @ 0x40 80093b8: d005 beq.n 80093c6 80093ba: 2b40 cmp r3, #64 @ 0x40 80093bc: d857 bhi.n 800946e 80093be: 2b00 cmp r3, #0 80093c0: d00f beq.n 80093e2 80093c2: 2b20 cmp r3, #32 80093c4: d153 bne.n 800946e { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); 80093c6: 687b ldr r3, [r7, #4] 80093c8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80093cc: 687b ldr r3, [r7, #4] 80093ce: 32ae adds r2, #174 @ 0xae 80093d0: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80093d4: 689b ldr r3, [r3, #8] 80093d6: 6839 ldr r1, [r7, #0] 80093d8: 6878 ldr r0, [r7, #4] 80093da: 4798 blx r3 80093dc: 4603 mov r3, r0 80093de: 73fb strb r3, [r7, #15] break; 80093e0: e04a b.n 8009478 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80093e2: 683b ldr r3, [r7, #0] 80093e4: 785b ldrb r3, [r3, #1] 80093e6: 2b09 cmp r3, #9 80093e8: d83b bhi.n 8009462 80093ea: a201 add r2, pc, #4 @ (adr r2, 80093f0 ) 80093ec: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80093f0: 08009445 .word 0x08009445 80093f4: 08009459 .word 0x08009459 80093f8: 08009463 .word 0x08009463 80093fc: 0800944f .word 0x0800944f 8009400: 08009463 .word 0x08009463 8009404: 08009423 .word 0x08009423 8009408: 08009419 .word 0x08009419 800940c: 08009463 .word 0x08009463 8009410: 0800943b .word 0x0800943b 8009414: 0800942d .word 0x0800942d { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 8009418: 6839 ldr r1, [r7, #0] 800941a: 6878 ldr r0, [r7, #4] 800941c: f000 fa3e bl 800989c break; 8009420: e024 b.n 800946c case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 8009422: 6839 ldr r1, [r7, #0] 8009424: 6878 ldr r0, [r7, #4] 8009426: f000 fbcd bl 8009bc4 break; 800942a: e01f b.n 800946c case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 800942c: 6839 ldr r1, [r7, #0] 800942e: 6878 ldr r0, [r7, #4] 8009430: f000 fc0c bl 8009c4c 8009434: 4603 mov r3, r0 8009436: 73fb strb r3, [r7, #15] break; 8009438: e018 b.n 800946c case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 800943a: 6839 ldr r1, [r7, #0] 800943c: 6878 ldr r0, [r7, #4] 800943e: f000 fcaf bl 8009da0 break; 8009442: e013 b.n 800946c case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 8009444: 6839 ldr r1, [r7, #0] 8009446: 6878 ldr r0, [r7, #4] 8009448: f000 fce0 bl 8009e0c break; 800944c: e00e b.n 800946c case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 800944e: 6839 ldr r1, [r7, #0] 8009450: 6878 ldr r0, [r7, #4] 8009452: f000 fd0f bl 8009e74 break; 8009456: e009 b.n 800946c case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 8009458: 6839 ldr r1, [r7, #0] 800945a: 6878 ldr r0, [r7, #4] 800945c: f000 fd33 bl 8009ec6 break; 8009460: e004 b.n 800946c default: USBD_CtlError(pdev, req); 8009462: 6839 ldr r1, [r7, #0] 8009464: 6878 ldr r0, [r7, #4] 8009466: f000 fd8a bl 8009f7e break; 800946a: bf00 nop } break; 800946c: e004 b.n 8009478 default: USBD_CtlError(pdev, req); 800946e: 6839 ldr r1, [r7, #0] 8009470: 6878 ldr r0, [r7, #4] 8009472: f000 fd84 bl 8009f7e break; 8009476: bf00 nop } return ret; 8009478: 7bfb ldrb r3, [r7, #15] } 800947a: 4618 mov r0, r3 800947c: 3710 adds r7, #16 800947e: 46bd mov sp, r7 8009480: bd80 pop {r7, pc} 8009482: bf00 nop 08009484 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009484: b580 push {r7, lr} 8009486: b084 sub sp, #16 8009488: af00 add r7, sp, #0 800948a: 6078 str r0, [r7, #4] 800948c: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800948e: 2300 movs r3, #0 8009490: 73fb strb r3, [r7, #15] uint8_t idx; switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009492: 683b ldr r3, [r7, #0] 8009494: 781b ldrb r3, [r3, #0] 8009496: f003 0360 and.w r3, r3, #96 @ 0x60 800949a: 2b40 cmp r3, #64 @ 0x40 800949c: d005 beq.n 80094aa 800949e: 2b40 cmp r3, #64 @ 0x40 80094a0: d852 bhi.n 8009548 80094a2: 2b00 cmp r3, #0 80094a4: d001 beq.n 80094aa 80094a6: 2b20 cmp r3, #32 80094a8: d14e bne.n 8009548 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 80094aa: 687b ldr r3, [r7, #4] 80094ac: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80094b0: b2db uxtb r3, r3 80094b2: 3b01 subs r3, #1 80094b4: 2b02 cmp r3, #2 80094b6: d840 bhi.n 800953a { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 80094b8: 683b ldr r3, [r7, #0] 80094ba: 889b ldrh r3, [r3, #4] 80094bc: b2db uxtb r3, r3 80094be: 2b01 cmp r3, #1 80094c0: d836 bhi.n 8009530 { /* Get the class index relative to this interface */ idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); 80094c2: 683b ldr r3, [r7, #0] 80094c4: 889b ldrh r3, [r3, #4] 80094c6: b2db uxtb r3, r3 80094c8: 4619 mov r1, r3 80094ca: 6878 ldr r0, [r7, #4] 80094cc: f7ff feda bl 8009284 80094d0: 4603 mov r3, r0 80094d2: 73bb strb r3, [r7, #14] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 80094d4: 7bbb ldrb r3, [r7, #14] 80094d6: 2bff cmp r3, #255 @ 0xff 80094d8: d01d beq.n 8009516 80094da: 7bbb ldrb r3, [r7, #14] 80094dc: 2b00 cmp r3, #0 80094de: d11a bne.n 8009516 { /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 80094e0: 7bba ldrb r2, [r7, #14] 80094e2: 687b ldr r3, [r7, #4] 80094e4: 32ae adds r2, #174 @ 0xae 80094e6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80094ea: 689b ldr r3, [r3, #8] 80094ec: 2b00 cmp r3, #0 80094ee: d00f beq.n 8009510 { pdev->classId = idx; 80094f0: 7bba ldrb r2, [r7, #14] 80094f2: 687b ldr r3, [r7, #4] 80094f4: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 80094f8: 7bba ldrb r2, [r7, #14] 80094fa: 687b ldr r3, [r7, #4] 80094fc: 32ae adds r2, #174 @ 0xae 80094fe: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009502: 689b ldr r3, [r3, #8] 8009504: 6839 ldr r1, [r7, #0] 8009506: 6878 ldr r0, [r7, #4] 8009508: 4798 blx r3 800950a: 4603 mov r3, r0 800950c: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 800950e: e004 b.n 800951a } else { /* should never reach this condition */ ret = USBD_FAIL; 8009510: 2303 movs r3, #3 8009512: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 8009514: e001 b.n 800951a } } else { /* No relative interface found */ ret = USBD_FAIL; 8009516: 2303 movs r3, #3 8009518: 73fb strb r3, [r7, #15] } if ((req->wLength == 0U) && (ret == USBD_OK)) 800951a: 683b ldr r3, [r7, #0] 800951c: 88db ldrh r3, [r3, #6] 800951e: 2b00 cmp r3, #0 8009520: d110 bne.n 8009544 8009522: 7bfb ldrb r3, [r7, #15] 8009524: 2b00 cmp r3, #0 8009526: d10d bne.n 8009544 { (void)USBD_CtlSendStatus(pdev); 8009528: 6878 ldr r0, [r7, #4] 800952a: f000 fde5 bl 800a0f8 } else { USBD_CtlError(pdev, req); } break; 800952e: e009 b.n 8009544 USBD_CtlError(pdev, req); 8009530: 6839 ldr r1, [r7, #0] 8009532: 6878 ldr r0, [r7, #4] 8009534: f000 fd23 bl 8009f7e break; 8009538: e004 b.n 8009544 default: USBD_CtlError(pdev, req); 800953a: 6839 ldr r1, [r7, #0] 800953c: 6878 ldr r0, [r7, #4] 800953e: f000 fd1e bl 8009f7e break; 8009542: e000 b.n 8009546 break; 8009544: bf00 nop } break; 8009546: e004 b.n 8009552 default: USBD_CtlError(pdev, req); 8009548: 6839 ldr r1, [r7, #0] 800954a: 6878 ldr r0, [r7, #4] 800954c: f000 fd17 bl 8009f7e break; 8009550: bf00 nop } return ret; 8009552: 7bfb ldrb r3, [r7, #15] } 8009554: 4618 mov r0, r3 8009556: 3710 adds r7, #16 8009558: 46bd mov sp, r7 800955a: bd80 pop {r7, pc} 0800955c : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800955c: b580 push {r7, lr} 800955e: b084 sub sp, #16 8009560: af00 add r7, sp, #0 8009562: 6078 str r0, [r7, #4] 8009564: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; uint8_t idx; USBD_StatusTypeDef ret = USBD_OK; 8009566: 2300 movs r3, #0 8009568: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 800956a: 683b ldr r3, [r7, #0] 800956c: 889b ldrh r3, [r3, #4] 800956e: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009570: 683b ldr r3, [r7, #0] 8009572: 781b ldrb r3, [r3, #0] 8009574: f003 0360 and.w r3, r3, #96 @ 0x60 8009578: 2b40 cmp r3, #64 @ 0x40 800957a: d007 beq.n 800958c 800957c: 2b40 cmp r3, #64 @ 0x40 800957e: f200 8181 bhi.w 8009884 8009582: 2b00 cmp r3, #0 8009584: d02a beq.n 80095dc 8009586: 2b20 cmp r3, #32 8009588: f040 817c bne.w 8009884 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: /* Get the class index relative to this endpoint */ idx = USBD_CoreFindEP(pdev, ep_addr); 800958c: 7bbb ldrb r3, [r7, #14] 800958e: 4619 mov r1, r3 8009590: 6878 ldr r0, [r7, #4] 8009592: f7ff fe84 bl 800929e 8009596: 4603 mov r3, r0 8009598: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800959a: 7b7b ldrb r3, [r7, #13] 800959c: 2bff cmp r3, #255 @ 0xff 800959e: f000 8176 beq.w 800988e 80095a2: 7b7b ldrb r3, [r7, #13] 80095a4: 2b00 cmp r3, #0 80095a6: f040 8172 bne.w 800988e { pdev->classId = idx; 80095aa: 7b7a ldrb r2, [r7, #13] 80095ac: 687b ldr r3, [r7, #4] 80095ae: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 80095b2: 7b7a ldrb r2, [r7, #13] 80095b4: 687b ldr r3, [r7, #4] 80095b6: 32ae adds r2, #174 @ 0xae 80095b8: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80095bc: 689b ldr r3, [r3, #8] 80095be: 2b00 cmp r3, #0 80095c0: f000 8165 beq.w 800988e { ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); 80095c4: 7b7a ldrb r2, [r7, #13] 80095c6: 687b ldr r3, [r7, #4] 80095c8: 32ae adds r2, #174 @ 0xae 80095ca: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80095ce: 689b ldr r3, [r3, #8] 80095d0: 6839 ldr r1, [r7, #0] 80095d2: 6878 ldr r0, [r7, #4] 80095d4: 4798 blx r3 80095d6: 4603 mov r3, r0 80095d8: 73fb strb r3, [r7, #15] } } break; 80095da: e158 b.n 800988e case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80095dc: 683b ldr r3, [r7, #0] 80095de: 785b ldrb r3, [r3, #1] 80095e0: 2b03 cmp r3, #3 80095e2: d008 beq.n 80095f6 80095e4: 2b03 cmp r3, #3 80095e6: f300 8147 bgt.w 8009878 80095ea: 2b00 cmp r3, #0 80095ec: f000 809b beq.w 8009726 80095f0: 2b01 cmp r3, #1 80095f2: d03c beq.n 800966e 80095f4: e140 b.n 8009878 { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 80095f6: 687b ldr r3, [r7, #4] 80095f8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80095fc: b2db uxtb r3, r3 80095fe: 2b02 cmp r3, #2 8009600: d002 beq.n 8009608 8009602: 2b03 cmp r3, #3 8009604: d016 beq.n 8009634 8009606: e02c b.n 8009662 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8009608: 7bbb ldrb r3, [r7, #14] 800960a: 2b00 cmp r3, #0 800960c: d00d beq.n 800962a 800960e: 7bbb ldrb r3, [r7, #14] 8009610: 2b80 cmp r3, #128 @ 0x80 8009612: d00a beq.n 800962a { (void)USBD_LL_StallEP(pdev, ep_addr); 8009614: 7bbb ldrb r3, [r7, #14] 8009616: 4619 mov r1, r3 8009618: 6878 ldr r0, [r7, #4] 800961a: f001 f8e3 bl 800a7e4 (void)USBD_LL_StallEP(pdev, 0x80U); 800961e: 2180 movs r1, #128 @ 0x80 8009620: 6878 ldr r0, [r7, #4] 8009622: f001 f8df bl 800a7e4 8009626: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8009628: e020 b.n 800966c USBD_CtlError(pdev, req); 800962a: 6839 ldr r1, [r7, #0] 800962c: 6878 ldr r0, [r7, #4] 800962e: f000 fca6 bl 8009f7e break; 8009632: e01b b.n 800966c case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8009634: 683b ldr r3, [r7, #0] 8009636: 885b ldrh r3, [r3, #2] 8009638: 2b00 cmp r3, #0 800963a: d10e bne.n 800965a { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 800963c: 7bbb ldrb r3, [r7, #14] 800963e: 2b00 cmp r3, #0 8009640: d00b beq.n 800965a 8009642: 7bbb ldrb r3, [r7, #14] 8009644: 2b80 cmp r3, #128 @ 0x80 8009646: d008 beq.n 800965a 8009648: 683b ldr r3, [r7, #0] 800964a: 88db ldrh r3, [r3, #6] 800964c: 2b00 cmp r3, #0 800964e: d104 bne.n 800965a { (void)USBD_LL_StallEP(pdev, ep_addr); 8009650: 7bbb ldrb r3, [r7, #14] 8009652: 4619 mov r1, r3 8009654: 6878 ldr r0, [r7, #4] 8009656: f001 f8c5 bl 800a7e4 } } (void)USBD_CtlSendStatus(pdev); 800965a: 6878 ldr r0, [r7, #4] 800965c: f000 fd4c bl 800a0f8 break; 8009660: e004 b.n 800966c default: USBD_CtlError(pdev, req); 8009662: 6839 ldr r1, [r7, #0] 8009664: 6878 ldr r0, [r7, #4] 8009666: f000 fc8a bl 8009f7e break; 800966a: bf00 nop } break; 800966c: e109 b.n 8009882 case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 800966e: 687b ldr r3, [r7, #4] 8009670: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009674: b2db uxtb r3, r3 8009676: 2b02 cmp r3, #2 8009678: d002 beq.n 8009680 800967a: 2b03 cmp r3, #3 800967c: d016 beq.n 80096ac 800967e: e04b b.n 8009718 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8009680: 7bbb ldrb r3, [r7, #14] 8009682: 2b00 cmp r3, #0 8009684: d00d beq.n 80096a2 8009686: 7bbb ldrb r3, [r7, #14] 8009688: 2b80 cmp r3, #128 @ 0x80 800968a: d00a beq.n 80096a2 { (void)USBD_LL_StallEP(pdev, ep_addr); 800968c: 7bbb ldrb r3, [r7, #14] 800968e: 4619 mov r1, r3 8009690: 6878 ldr r0, [r7, #4] 8009692: f001 f8a7 bl 800a7e4 (void)USBD_LL_StallEP(pdev, 0x80U); 8009696: 2180 movs r1, #128 @ 0x80 8009698: 6878 ldr r0, [r7, #4] 800969a: f001 f8a3 bl 800a7e4 800969e: bf00 nop } else { USBD_CtlError(pdev, req); } break; 80096a0: e040 b.n 8009724 USBD_CtlError(pdev, req); 80096a2: 6839 ldr r1, [r7, #0] 80096a4: 6878 ldr r0, [r7, #4] 80096a6: f000 fc6a bl 8009f7e break; 80096aa: e03b b.n 8009724 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 80096ac: 683b ldr r3, [r7, #0] 80096ae: 885b ldrh r3, [r3, #2] 80096b0: 2b00 cmp r3, #0 80096b2: d136 bne.n 8009722 { if ((ep_addr & 0x7FU) != 0x00U) 80096b4: 7bbb ldrb r3, [r7, #14] 80096b6: f003 037f and.w r3, r3, #127 @ 0x7f 80096ba: 2b00 cmp r3, #0 80096bc: d004 beq.n 80096c8 { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 80096be: 7bbb ldrb r3, [r7, #14] 80096c0: 4619 mov r1, r3 80096c2: 6878 ldr r0, [r7, #4] 80096c4: f001 f8ad bl 800a822 } (void)USBD_CtlSendStatus(pdev); 80096c8: 6878 ldr r0, [r7, #4] 80096ca: f000 fd15 bl 800a0f8 /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ep_addr); 80096ce: 7bbb ldrb r3, [r7, #14] 80096d0: 4619 mov r1, r3 80096d2: 6878 ldr r0, [r7, #4] 80096d4: f7ff fde3 bl 800929e 80096d8: 4603 mov r3, r0 80096da: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 80096dc: 7b7b ldrb r3, [r7, #13] 80096de: 2bff cmp r3, #255 @ 0xff 80096e0: d01f beq.n 8009722 80096e2: 7b7b ldrb r3, [r7, #13] 80096e4: 2b00 cmp r3, #0 80096e6: d11c bne.n 8009722 { pdev->classId = idx; 80096e8: 7b7a ldrb r2, [r7, #13] 80096ea: 687b ldr r3, [r7, #4] 80096ec: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 80096f0: 7b7a ldrb r2, [r7, #13] 80096f2: 687b ldr r3, [r7, #4] 80096f4: 32ae adds r2, #174 @ 0xae 80096f6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80096fa: 689b ldr r3, [r3, #8] 80096fc: 2b00 cmp r3, #0 80096fe: d010 beq.n 8009722 { ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 8009700: 7b7a ldrb r2, [r7, #13] 8009702: 687b ldr r3, [r7, #4] 8009704: 32ae adds r2, #174 @ 0xae 8009706: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800970a: 689b ldr r3, [r3, #8] 800970c: 6839 ldr r1, [r7, #0] 800970e: 6878 ldr r0, [r7, #4] 8009710: 4798 blx r3 8009712: 4603 mov r3, r0 8009714: 73fb strb r3, [r7, #15] } } } break; 8009716: e004 b.n 8009722 default: USBD_CtlError(pdev, req); 8009718: 6839 ldr r1, [r7, #0] 800971a: 6878 ldr r0, [r7, #4] 800971c: f000 fc2f bl 8009f7e break; 8009720: e000 b.n 8009724 break; 8009722: bf00 nop } break; 8009724: e0ad b.n 8009882 case USB_REQ_GET_STATUS: switch (pdev->dev_state) 8009726: 687b ldr r3, [r7, #4] 8009728: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800972c: b2db uxtb r3, r3 800972e: 2b02 cmp r3, #2 8009730: d002 beq.n 8009738 8009732: 2b03 cmp r3, #3 8009734: d033 beq.n 800979e 8009736: e099 b.n 800986c { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8009738: 7bbb ldrb r3, [r7, #14] 800973a: 2b00 cmp r3, #0 800973c: d007 beq.n 800974e 800973e: 7bbb ldrb r3, [r7, #14] 8009740: 2b80 cmp r3, #128 @ 0x80 8009742: d004 beq.n 800974e { USBD_CtlError(pdev, req); 8009744: 6839 ldr r1, [r7, #0] 8009746: 6878 ldr r0, [r7, #4] 8009748: f000 fc19 bl 8009f7e break; 800974c: e093 b.n 8009876 } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800974e: f997 300e ldrsb.w r3, [r7, #14] 8009752: 2b00 cmp r3, #0 8009754: da0b bge.n 800976e 8009756: 7bbb ldrb r3, [r7, #14] 8009758: f003 027f and.w r2, r3, #127 @ 0x7f 800975c: 4613 mov r3, r2 800975e: 009b lsls r3, r3, #2 8009760: 4413 add r3, r2 8009762: 009b lsls r3, r3, #2 8009764: 3310 adds r3, #16 8009766: 687a ldr r2, [r7, #4] 8009768: 4413 add r3, r2 800976a: 3304 adds r3, #4 800976c: e00b b.n 8009786 &pdev->ep_out[ep_addr & 0x7FU]; 800976e: 7bbb ldrb r3, [r7, #14] 8009770: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8009774: 4613 mov r3, r2 8009776: 009b lsls r3, r3, #2 8009778: 4413 add r3, r2 800977a: 009b lsls r3, r3, #2 800977c: f503 73a8 add.w r3, r3, #336 @ 0x150 8009780: 687a ldr r2, [r7, #4] 8009782: 4413 add r3, r2 8009784: 3304 adds r3, #4 8009786: 60bb str r3, [r7, #8] pep->status = 0x0000U; 8009788: 68bb ldr r3, [r7, #8] 800978a: 2200 movs r2, #0 800978c: 739a strb r2, [r3, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 800978e: 68bb ldr r3, [r7, #8] 8009790: 330e adds r3, #14 8009792: 2202 movs r2, #2 8009794: 4619 mov r1, r3 8009796: 6878 ldr r0, [r7, #4] 8009798: f000 fc6e bl 800a078 break; 800979c: e06b b.n 8009876 case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 800979e: f997 300e ldrsb.w r3, [r7, #14] 80097a2: 2b00 cmp r3, #0 80097a4: da11 bge.n 80097ca { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 80097a6: 7bbb ldrb r3, [r7, #14] 80097a8: f003 020f and.w r2, r3, #15 80097ac: 6879 ldr r1, [r7, #4] 80097ae: 4613 mov r3, r2 80097b0: 009b lsls r3, r3, #2 80097b2: 4413 add r3, r2 80097b4: 009b lsls r3, r3, #2 80097b6: 440b add r3, r1 80097b8: 3323 adds r3, #35 @ 0x23 80097ba: 781b ldrb r3, [r3, #0] 80097bc: 2b00 cmp r3, #0 80097be: d117 bne.n 80097f0 { USBD_CtlError(pdev, req); 80097c0: 6839 ldr r1, [r7, #0] 80097c2: 6878 ldr r0, [r7, #4] 80097c4: f000 fbdb bl 8009f7e break; 80097c8: e055 b.n 8009876 } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 80097ca: 7bbb ldrb r3, [r7, #14] 80097cc: f003 020f and.w r2, r3, #15 80097d0: 6879 ldr r1, [r7, #4] 80097d2: 4613 mov r3, r2 80097d4: 009b lsls r3, r3, #2 80097d6: 4413 add r3, r2 80097d8: 009b lsls r3, r3, #2 80097da: 440b add r3, r1 80097dc: f203 1363 addw r3, r3, #355 @ 0x163 80097e0: 781b ldrb r3, [r3, #0] 80097e2: 2b00 cmp r3, #0 80097e4: d104 bne.n 80097f0 { USBD_CtlError(pdev, req); 80097e6: 6839 ldr r1, [r7, #0] 80097e8: 6878 ldr r0, [r7, #4] 80097ea: f000 fbc8 bl 8009f7e break; 80097ee: e042 b.n 8009876 } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80097f0: f997 300e ldrsb.w r3, [r7, #14] 80097f4: 2b00 cmp r3, #0 80097f6: da0b bge.n 8009810 80097f8: 7bbb ldrb r3, [r7, #14] 80097fa: f003 027f and.w r2, r3, #127 @ 0x7f 80097fe: 4613 mov r3, r2 8009800: 009b lsls r3, r3, #2 8009802: 4413 add r3, r2 8009804: 009b lsls r3, r3, #2 8009806: 3310 adds r3, #16 8009808: 687a ldr r2, [r7, #4] 800980a: 4413 add r3, r2 800980c: 3304 adds r3, #4 800980e: e00b b.n 8009828 &pdev->ep_out[ep_addr & 0x7FU]; 8009810: 7bbb ldrb r3, [r7, #14] 8009812: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8009816: 4613 mov r3, r2 8009818: 009b lsls r3, r3, #2 800981a: 4413 add r3, r2 800981c: 009b lsls r3, r3, #2 800981e: f503 73a8 add.w r3, r3, #336 @ 0x150 8009822: 687a ldr r2, [r7, #4] 8009824: 4413 add r3, r2 8009826: 3304 adds r3, #4 8009828: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 800982a: 7bbb ldrb r3, [r7, #14] 800982c: 2b00 cmp r3, #0 800982e: d002 beq.n 8009836 8009830: 7bbb ldrb r3, [r7, #14] 8009832: 2b80 cmp r3, #128 @ 0x80 8009834: d103 bne.n 800983e { pep->status = 0x0000U; 8009836: 68bb ldr r3, [r7, #8] 8009838: 2200 movs r2, #0 800983a: 739a strb r2, [r3, #14] 800983c: e00e b.n 800985c } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 800983e: 7bbb ldrb r3, [r7, #14] 8009840: 4619 mov r1, r3 8009842: 6878 ldr r0, [r7, #4] 8009844: f001 f80c bl 800a860 8009848: 4603 mov r3, r0 800984a: 2b00 cmp r3, #0 800984c: d003 beq.n 8009856 { pep->status = 0x0001U; 800984e: 68bb ldr r3, [r7, #8] 8009850: 2201 movs r2, #1 8009852: 739a strb r2, [r3, #14] 8009854: e002 b.n 800985c } else { pep->status = 0x0000U; 8009856: 68bb ldr r3, [r7, #8] 8009858: 2200 movs r2, #0 800985a: 739a strb r2, [r3, #14] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 800985c: 68bb ldr r3, [r7, #8] 800985e: 330e adds r3, #14 8009860: 2202 movs r2, #2 8009862: 4619 mov r1, r3 8009864: 6878 ldr r0, [r7, #4] 8009866: f000 fc07 bl 800a078 break; 800986a: e004 b.n 8009876 default: USBD_CtlError(pdev, req); 800986c: 6839 ldr r1, [r7, #0] 800986e: 6878 ldr r0, [r7, #4] 8009870: f000 fb85 bl 8009f7e break; 8009874: bf00 nop } break; 8009876: e004 b.n 8009882 default: USBD_CtlError(pdev, req); 8009878: 6839 ldr r1, [r7, #0] 800987a: 6878 ldr r0, [r7, #4] 800987c: f000 fb7f bl 8009f7e break; 8009880: bf00 nop } break; 8009882: e005 b.n 8009890 default: USBD_CtlError(pdev, req); 8009884: 6839 ldr r1, [r7, #0] 8009886: 6878 ldr r0, [r7, #4] 8009888: f000 fb79 bl 8009f7e break; 800988c: e000 b.n 8009890 break; 800988e: bf00 nop } return ret; 8009890: 7bfb ldrb r3, [r7, #15] } 8009892: 4618 mov r0, r3 8009894: 3710 adds r7, #16 8009896: 46bd mov sp, r7 8009898: bd80 pop {r7, pc} ... 0800989c : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800989c: b580 push {r7, lr} 800989e: b084 sub sp, #16 80098a0: af00 add r7, sp, #0 80098a2: 6078 str r0, [r7, #4] 80098a4: 6039 str r1, [r7, #0] uint16_t len = 0U; 80098a6: 2300 movs r3, #0 80098a8: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 80098aa: 2300 movs r3, #0 80098ac: 60fb str r3, [r7, #12] uint8_t err = 0U; 80098ae: 2300 movs r3, #0 80098b0: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 80098b2: 683b ldr r3, [r7, #0] 80098b4: 885b ldrh r3, [r3, #2] 80098b6: 0a1b lsrs r3, r3, #8 80098b8: b29b uxth r3, r3 80098ba: 3b01 subs r3, #1 80098bc: 2b0e cmp r3, #14 80098be: f200 8152 bhi.w 8009b66 80098c2: a201 add r2, pc, #4 @ (adr r2, 80098c8 ) 80098c4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80098c8: 08009939 .word 0x08009939 80098cc: 08009951 .word 0x08009951 80098d0: 08009991 .word 0x08009991 80098d4: 08009b67 .word 0x08009b67 80098d8: 08009b67 .word 0x08009b67 80098dc: 08009b07 .word 0x08009b07 80098e0: 08009b33 .word 0x08009b33 80098e4: 08009b67 .word 0x08009b67 80098e8: 08009b67 .word 0x08009b67 80098ec: 08009b67 .word 0x08009b67 80098f0: 08009b67 .word 0x08009b67 80098f4: 08009b67 .word 0x08009b67 80098f8: 08009b67 .word 0x08009b67 80098fc: 08009b67 .word 0x08009b67 8009900: 08009905 .word 0x08009905 { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) 8009904: 687b ldr r3, [r7, #4] 8009906: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800990a: 69db ldr r3, [r3, #28] 800990c: 2b00 cmp r3, #0 800990e: d00b beq.n 8009928 { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); 8009910: 687b ldr r3, [r7, #4] 8009912: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009916: 69db ldr r3, [r3, #28] 8009918: 687a ldr r2, [r7, #4] 800991a: 7c12 ldrb r2, [r2, #16] 800991c: f107 0108 add.w r1, r7, #8 8009920: 4610 mov r0, r2 8009922: 4798 blx r3 8009924: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009926: e126 b.n 8009b76 USBD_CtlError(pdev, req); 8009928: 6839 ldr r1, [r7, #0] 800992a: 6878 ldr r0, [r7, #4] 800992c: f000 fb27 bl 8009f7e err++; 8009930: 7afb ldrb r3, [r7, #11] 8009932: 3301 adds r3, #1 8009934: 72fb strb r3, [r7, #11] break; 8009936: e11e b.n 8009b76 #endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 8009938: 687b ldr r3, [r7, #4] 800993a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800993e: 681b ldr r3, [r3, #0] 8009940: 687a ldr r2, [r7, #4] 8009942: 7c12 ldrb r2, [r2, #16] 8009944: f107 0108 add.w r1, r7, #8 8009948: 4610 mov r0, r2 800994a: 4798 blx r3 800994c: 60f8 str r0, [r7, #12] break; 800994e: e112 b.n 8009b76 case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8009950: 687b ldr r3, [r7, #4] 8009952: 7c1b ldrb r3, [r3, #16] 8009954: 2b00 cmp r3, #0 8009956: d10d bne.n 8009974 pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); 8009958: 687b ldr r3, [r7, #4] 800995a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800995e: 6a9b ldr r3, [r3, #40] @ 0x28 8009960: f107 0208 add.w r2, r7, #8 8009964: 4610 mov r0, r2 8009966: 4798 blx r3 8009968: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800996a: 68fb ldr r3, [r7, #12] 800996c: 3301 adds r3, #1 800996e: 2202 movs r2, #2 8009970: 701a strb r2, [r3, #0] { pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 8009972: e100 b.n 8009b76 pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); 8009974: 687b ldr r3, [r7, #4] 8009976: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800997a: 6adb ldr r3, [r3, #44] @ 0x2c 800997c: f107 0208 add.w r2, r7, #8 8009980: 4610 mov r0, r2 8009982: 4798 blx r3 8009984: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 8009986: 68fb ldr r3, [r7, #12] 8009988: 3301 adds r3, #1 800998a: 2202 movs r2, #2 800998c: 701a strb r2, [r3, #0] break; 800998e: e0f2 b.n 8009b76 case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 8009990: 683b ldr r3, [r7, #0] 8009992: 885b ldrh r3, [r3, #2] 8009994: b2db uxtb r3, r3 8009996: 2b05 cmp r3, #5 8009998: f200 80ac bhi.w 8009af4 800999c: a201 add r2, pc, #4 @ (adr r2, 80099a4 ) 800999e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80099a2: bf00 nop 80099a4: 080099bd .word 0x080099bd 80099a8: 080099f1 .word 0x080099f1 80099ac: 08009a25 .word 0x08009a25 80099b0: 08009a59 .word 0x08009a59 80099b4: 08009a8d .word 0x08009a8d 80099b8: 08009ac1 .word 0x08009ac1 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 80099bc: 687b ldr r3, [r7, #4] 80099be: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80099c2: 685b ldr r3, [r3, #4] 80099c4: 2b00 cmp r3, #0 80099c6: d00b beq.n 80099e0 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 80099c8: 687b ldr r3, [r7, #4] 80099ca: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80099ce: 685b ldr r3, [r3, #4] 80099d0: 687a ldr r2, [r7, #4] 80099d2: 7c12 ldrb r2, [r2, #16] 80099d4: f107 0108 add.w r1, r7, #8 80099d8: 4610 mov r0, r2 80099da: 4798 blx r3 80099dc: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80099de: e091 b.n 8009b04 USBD_CtlError(pdev, req); 80099e0: 6839 ldr r1, [r7, #0] 80099e2: 6878 ldr r0, [r7, #4] 80099e4: f000 facb bl 8009f7e err++; 80099e8: 7afb ldrb r3, [r7, #11] 80099ea: 3301 adds r3, #1 80099ec: 72fb strb r3, [r7, #11] break; 80099ee: e089 b.n 8009b04 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 80099f0: 687b ldr r3, [r7, #4] 80099f2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80099f6: 689b ldr r3, [r3, #8] 80099f8: 2b00 cmp r3, #0 80099fa: d00b beq.n 8009a14 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 80099fc: 687b ldr r3, [r7, #4] 80099fe: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a02: 689b ldr r3, [r3, #8] 8009a04: 687a ldr r2, [r7, #4] 8009a06: 7c12 ldrb r2, [r2, #16] 8009a08: f107 0108 add.w r1, r7, #8 8009a0c: 4610 mov r0, r2 8009a0e: 4798 blx r3 8009a10: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009a12: e077 b.n 8009b04 USBD_CtlError(pdev, req); 8009a14: 6839 ldr r1, [r7, #0] 8009a16: 6878 ldr r0, [r7, #4] 8009a18: f000 fab1 bl 8009f7e err++; 8009a1c: 7afb ldrb r3, [r7, #11] 8009a1e: 3301 adds r3, #1 8009a20: 72fb strb r3, [r7, #11] break; 8009a22: e06f b.n 8009b04 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 8009a24: 687b ldr r3, [r7, #4] 8009a26: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a2a: 68db ldr r3, [r3, #12] 8009a2c: 2b00 cmp r3, #0 8009a2e: d00b beq.n 8009a48 { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 8009a30: 687b ldr r3, [r7, #4] 8009a32: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a36: 68db ldr r3, [r3, #12] 8009a38: 687a ldr r2, [r7, #4] 8009a3a: 7c12 ldrb r2, [r2, #16] 8009a3c: f107 0108 add.w r1, r7, #8 8009a40: 4610 mov r0, r2 8009a42: 4798 blx r3 8009a44: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009a46: e05d b.n 8009b04 USBD_CtlError(pdev, req); 8009a48: 6839 ldr r1, [r7, #0] 8009a4a: 6878 ldr r0, [r7, #4] 8009a4c: f000 fa97 bl 8009f7e err++; 8009a50: 7afb ldrb r3, [r7, #11] 8009a52: 3301 adds r3, #1 8009a54: 72fb strb r3, [r7, #11] break; 8009a56: e055 b.n 8009b04 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 8009a58: 687b ldr r3, [r7, #4] 8009a5a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a5e: 691b ldr r3, [r3, #16] 8009a60: 2b00 cmp r3, #0 8009a62: d00b beq.n 8009a7c { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 8009a64: 687b ldr r3, [r7, #4] 8009a66: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a6a: 691b ldr r3, [r3, #16] 8009a6c: 687a ldr r2, [r7, #4] 8009a6e: 7c12 ldrb r2, [r2, #16] 8009a70: f107 0108 add.w r1, r7, #8 8009a74: 4610 mov r0, r2 8009a76: 4798 blx r3 8009a78: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009a7a: e043 b.n 8009b04 USBD_CtlError(pdev, req); 8009a7c: 6839 ldr r1, [r7, #0] 8009a7e: 6878 ldr r0, [r7, #4] 8009a80: f000 fa7d bl 8009f7e err++; 8009a84: 7afb ldrb r3, [r7, #11] 8009a86: 3301 adds r3, #1 8009a88: 72fb strb r3, [r7, #11] break; 8009a8a: e03b b.n 8009b04 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 8009a8c: 687b ldr r3, [r7, #4] 8009a8e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a92: 695b ldr r3, [r3, #20] 8009a94: 2b00 cmp r3, #0 8009a96: d00b beq.n 8009ab0 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 8009a98: 687b ldr r3, [r7, #4] 8009a9a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a9e: 695b ldr r3, [r3, #20] 8009aa0: 687a ldr r2, [r7, #4] 8009aa2: 7c12 ldrb r2, [r2, #16] 8009aa4: f107 0108 add.w r1, r7, #8 8009aa8: 4610 mov r0, r2 8009aaa: 4798 blx r3 8009aac: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009aae: e029 b.n 8009b04 USBD_CtlError(pdev, req); 8009ab0: 6839 ldr r1, [r7, #0] 8009ab2: 6878 ldr r0, [r7, #4] 8009ab4: f000 fa63 bl 8009f7e err++; 8009ab8: 7afb ldrb r3, [r7, #11] 8009aba: 3301 adds r3, #1 8009abc: 72fb strb r3, [r7, #11] break; 8009abe: e021 b.n 8009b04 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 8009ac0: 687b ldr r3, [r7, #4] 8009ac2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009ac6: 699b ldr r3, [r3, #24] 8009ac8: 2b00 cmp r3, #0 8009aca: d00b beq.n 8009ae4 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 8009acc: 687b ldr r3, [r7, #4] 8009ace: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009ad2: 699b ldr r3, [r3, #24] 8009ad4: 687a ldr r2, [r7, #4] 8009ad6: 7c12 ldrb r2, [r2, #16] 8009ad8: f107 0108 add.w r1, r7, #8 8009adc: 4610 mov r0, r2 8009ade: 4798 blx r3 8009ae0: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009ae2: e00f b.n 8009b04 USBD_CtlError(pdev, req); 8009ae4: 6839 ldr r1, [r7, #0] 8009ae6: 6878 ldr r0, [r7, #4] 8009ae8: f000 fa49 bl 8009f7e err++; 8009aec: 7afb ldrb r3, [r7, #11] 8009aee: 3301 adds r3, #1 8009af0: 72fb strb r3, [r7, #11] break; 8009af2: e007 b.n 8009b04 err++; } #endif /* USBD_SUPPORT_USER_STRING_DESC */ #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 8009af4: 6839 ldr r1, [r7, #0] 8009af6: 6878 ldr r0, [r7, #4] 8009af8: f000 fa41 bl 8009f7e err++; 8009afc: 7afb ldrb r3, [r7, #11] 8009afe: 3301 adds r3, #1 8009b00: 72fb strb r3, [r7, #11] #endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ break; 8009b02: bf00 nop } break; 8009b04: e037 b.n 8009b76 case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 8009b06: 687b ldr r3, [r7, #4] 8009b08: 7c1b ldrb r3, [r3, #16] 8009b0a: 2b00 cmp r3, #0 8009b0c: d109 bne.n 8009b22 pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); 8009b0e: 687b ldr r3, [r7, #4] 8009b10: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009b14: 6b5b ldr r3, [r3, #52] @ 0x34 8009b16: f107 0208 add.w r2, r7, #8 8009b1a: 4610 mov r0, r2 8009b1c: 4798 blx r3 8009b1e: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009b20: e029 b.n 8009b76 USBD_CtlError(pdev, req); 8009b22: 6839 ldr r1, [r7, #0] 8009b24: 6878 ldr r0, [r7, #4] 8009b26: f000 fa2a bl 8009f7e err++; 8009b2a: 7afb ldrb r3, [r7, #11] 8009b2c: 3301 adds r3, #1 8009b2e: 72fb strb r3, [r7, #11] break; 8009b30: e021 b.n 8009b76 case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8009b32: 687b ldr r3, [r7, #4] 8009b34: 7c1b ldrb r3, [r3, #16] 8009b36: 2b00 cmp r3, #0 8009b38: d10d bne.n 8009b56 pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); 8009b3a: 687b ldr r3, [r7, #4] 8009b3c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009b40: 6b1b ldr r3, [r3, #48] @ 0x30 8009b42: f107 0208 add.w r2, r7, #8 8009b46: 4610 mov r0, r2 8009b48: 4798 blx r3 8009b4a: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 8009b4c: 68fb ldr r3, [r7, #12] 8009b4e: 3301 adds r3, #1 8009b50: 2207 movs r2, #7 8009b52: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 8009b54: e00f b.n 8009b76 USBD_CtlError(pdev, req); 8009b56: 6839 ldr r1, [r7, #0] 8009b58: 6878 ldr r0, [r7, #4] 8009b5a: f000 fa10 bl 8009f7e err++; 8009b5e: 7afb ldrb r3, [r7, #11] 8009b60: 3301 adds r3, #1 8009b62: 72fb strb r3, [r7, #11] break; 8009b64: e007 b.n 8009b76 default: USBD_CtlError(pdev, req); 8009b66: 6839 ldr r1, [r7, #0] 8009b68: 6878 ldr r0, [r7, #4] 8009b6a: f000 fa08 bl 8009f7e err++; 8009b6e: 7afb ldrb r3, [r7, #11] 8009b70: 3301 adds r3, #1 8009b72: 72fb strb r3, [r7, #11] break; 8009b74: bf00 nop } if (err != 0U) 8009b76: 7afb ldrb r3, [r7, #11] 8009b78: 2b00 cmp r3, #0 8009b7a: d11e bne.n 8009bba { return; } if (req->wLength != 0U) 8009b7c: 683b ldr r3, [r7, #0] 8009b7e: 88db ldrh r3, [r3, #6] 8009b80: 2b00 cmp r3, #0 8009b82: d016 beq.n 8009bb2 { if (len != 0U) 8009b84: 893b ldrh r3, [r7, #8] 8009b86: 2b00 cmp r3, #0 8009b88: d00e beq.n 8009ba8 { len = MIN(len, req->wLength); 8009b8a: 683b ldr r3, [r7, #0] 8009b8c: 88da ldrh r2, [r3, #6] 8009b8e: 893b ldrh r3, [r7, #8] 8009b90: 4293 cmp r3, r2 8009b92: bf28 it cs 8009b94: 4613 movcs r3, r2 8009b96: b29b uxth r3, r3 8009b98: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 8009b9a: 893b ldrh r3, [r7, #8] 8009b9c: 461a mov r2, r3 8009b9e: 68f9 ldr r1, [r7, #12] 8009ba0: 6878 ldr r0, [r7, #4] 8009ba2: f000 fa69 bl 800a078 8009ba6: e009 b.n 8009bbc } else { USBD_CtlError(pdev, req); 8009ba8: 6839 ldr r1, [r7, #0] 8009baa: 6878 ldr r0, [r7, #4] 8009bac: f000 f9e7 bl 8009f7e 8009bb0: e004 b.n 8009bbc } } else { (void)USBD_CtlSendStatus(pdev); 8009bb2: 6878 ldr r0, [r7, #4] 8009bb4: f000 faa0 bl 800a0f8 8009bb8: e000 b.n 8009bbc return; 8009bba: bf00 nop } } 8009bbc: 3710 adds r7, #16 8009bbe: 46bd mov sp, r7 8009bc0: bd80 pop {r7, pc} 8009bc2: bf00 nop 08009bc4 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009bc4: b580 push {r7, lr} 8009bc6: b084 sub sp, #16 8009bc8: af00 add r7, sp, #0 8009bca: 6078 str r0, [r7, #4] 8009bcc: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 8009bce: 683b ldr r3, [r7, #0] 8009bd0: 889b ldrh r3, [r3, #4] 8009bd2: 2b00 cmp r3, #0 8009bd4: d131 bne.n 8009c3a 8009bd6: 683b ldr r3, [r7, #0] 8009bd8: 88db ldrh r3, [r3, #6] 8009bda: 2b00 cmp r3, #0 8009bdc: d12d bne.n 8009c3a 8009bde: 683b ldr r3, [r7, #0] 8009be0: 885b ldrh r3, [r3, #2] 8009be2: 2b7f cmp r3, #127 @ 0x7f 8009be4: d829 bhi.n 8009c3a { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 8009be6: 683b ldr r3, [r7, #0] 8009be8: 885b ldrh r3, [r3, #2] 8009bea: b2db uxtb r3, r3 8009bec: f003 037f and.w r3, r3, #127 @ 0x7f 8009bf0: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009bf2: 687b ldr r3, [r7, #4] 8009bf4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009bf8: b2db uxtb r3, r3 8009bfa: 2b03 cmp r3, #3 8009bfc: d104 bne.n 8009c08 { USBD_CtlError(pdev, req); 8009bfe: 6839 ldr r1, [r7, #0] 8009c00: 6878 ldr r0, [r7, #4] 8009c02: f000 f9bc bl 8009f7e if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009c06: e01d b.n 8009c44 } else { pdev->dev_address = dev_addr; 8009c08: 687b ldr r3, [r7, #4] 8009c0a: 7bfa ldrb r2, [r7, #15] 8009c0c: f883 229e strb.w r2, [r3, #670] @ 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 8009c10: 7bfb ldrb r3, [r7, #15] 8009c12: 4619 mov r1, r3 8009c14: 6878 ldr r0, [r7, #4] 8009c16: f000 fe4f bl 800a8b8 (void)USBD_CtlSendStatus(pdev); 8009c1a: 6878 ldr r0, [r7, #4] 8009c1c: f000 fa6c bl 800a0f8 if (dev_addr != 0U) 8009c20: 7bfb ldrb r3, [r7, #15] 8009c22: 2b00 cmp r3, #0 8009c24: d004 beq.n 8009c30 { pdev->dev_state = USBD_STATE_ADDRESSED; 8009c26: 687b ldr r3, [r7, #4] 8009c28: 2202 movs r2, #2 8009c2a: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009c2e: e009 b.n 8009c44 } else { pdev->dev_state = USBD_STATE_DEFAULT; 8009c30: 687b ldr r3, [r7, #4] 8009c32: 2201 movs r2, #1 8009c34: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009c38: e004 b.n 8009c44 } } } else { USBD_CtlError(pdev, req); 8009c3a: 6839 ldr r1, [r7, #0] 8009c3c: 6878 ldr r0, [r7, #4] 8009c3e: f000 f99e bl 8009f7e } } 8009c42: bf00 nop 8009c44: bf00 nop 8009c46: 3710 adds r7, #16 8009c48: 46bd mov sp, r7 8009c4a: bd80 pop {r7, pc} 08009c4c : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009c4c: b580 push {r7, lr} 8009c4e: b084 sub sp, #16 8009c50: af00 add r7, sp, #0 8009c52: 6078 str r0, [r7, #4] 8009c54: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8009c56: 2300 movs r3, #0 8009c58: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 8009c5a: 683b ldr r3, [r7, #0] 8009c5c: 885b ldrh r3, [r3, #2] 8009c5e: b2da uxtb r2, r3 8009c60: 4b4e ldr r3, [pc, #312] @ (8009d9c ) 8009c62: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 8009c64: 4b4d ldr r3, [pc, #308] @ (8009d9c ) 8009c66: 781b ldrb r3, [r3, #0] 8009c68: 2b01 cmp r3, #1 8009c6a: d905 bls.n 8009c78 { USBD_CtlError(pdev, req); 8009c6c: 6839 ldr r1, [r7, #0] 8009c6e: 6878 ldr r0, [r7, #4] 8009c70: f000 f985 bl 8009f7e return USBD_FAIL; 8009c74: 2303 movs r3, #3 8009c76: e08c b.n 8009d92 } switch (pdev->dev_state) 8009c78: 687b ldr r3, [r7, #4] 8009c7a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009c7e: b2db uxtb r3, r3 8009c80: 2b02 cmp r3, #2 8009c82: d002 beq.n 8009c8a 8009c84: 2b03 cmp r3, #3 8009c86: d029 beq.n 8009cdc 8009c88: e075 b.n 8009d76 { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 8009c8a: 4b44 ldr r3, [pc, #272] @ (8009d9c ) 8009c8c: 781b ldrb r3, [r3, #0] 8009c8e: 2b00 cmp r3, #0 8009c90: d020 beq.n 8009cd4 { pdev->dev_config = cfgidx; 8009c92: 4b42 ldr r3, [pc, #264] @ (8009d9c ) 8009c94: 781b ldrb r3, [r3, #0] 8009c96: 461a mov r2, r3 8009c98: 687b ldr r3, [r7, #4] 8009c9a: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8009c9c: 4b3f ldr r3, [pc, #252] @ (8009d9c ) 8009c9e: 781b ldrb r3, [r3, #0] 8009ca0: 4619 mov r1, r3 8009ca2: 6878 ldr r0, [r7, #4] 8009ca4: f7fe ffa3 bl 8008bee 8009ca8: 4603 mov r3, r0 8009caa: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8009cac: 7bfb ldrb r3, [r7, #15] 8009cae: 2b00 cmp r3, #0 8009cb0: d008 beq.n 8009cc4 { USBD_CtlError(pdev, req); 8009cb2: 6839 ldr r1, [r7, #0] 8009cb4: 6878 ldr r0, [r7, #4] 8009cb6: f000 f962 bl 8009f7e pdev->dev_state = USBD_STATE_ADDRESSED; 8009cba: 687b ldr r3, [r7, #4] 8009cbc: 2202 movs r2, #2 8009cbe: f883 229c strb.w r2, [r3, #668] @ 0x29c } else { (void)USBD_CtlSendStatus(pdev); } break; 8009cc2: e065 b.n 8009d90 (void)USBD_CtlSendStatus(pdev); 8009cc4: 6878 ldr r0, [r7, #4] 8009cc6: f000 fa17 bl 800a0f8 pdev->dev_state = USBD_STATE_CONFIGURED; 8009cca: 687b ldr r3, [r7, #4] 8009ccc: 2203 movs r2, #3 8009cce: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8009cd2: e05d b.n 8009d90 (void)USBD_CtlSendStatus(pdev); 8009cd4: 6878 ldr r0, [r7, #4] 8009cd6: f000 fa0f bl 800a0f8 break; 8009cda: e059 b.n 8009d90 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 8009cdc: 4b2f ldr r3, [pc, #188] @ (8009d9c ) 8009cde: 781b ldrb r3, [r3, #0] 8009ce0: 2b00 cmp r3, #0 8009ce2: d112 bne.n 8009d0a { pdev->dev_state = USBD_STATE_ADDRESSED; 8009ce4: 687b ldr r3, [r7, #4] 8009ce6: 2202 movs r2, #2 8009ce8: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->dev_config = cfgidx; 8009cec: 4b2b ldr r3, [pc, #172] @ (8009d9c ) 8009cee: 781b ldrb r3, [r3, #0] 8009cf0: 461a mov r2, r3 8009cf2: 687b ldr r3, [r7, #4] 8009cf4: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 8009cf6: 4b29 ldr r3, [pc, #164] @ (8009d9c ) 8009cf8: 781b ldrb r3, [r3, #0] 8009cfa: 4619 mov r1, r3 8009cfc: 6878 ldr r0, [r7, #4] 8009cfe: f7fe ff92 bl 8008c26 (void)USBD_CtlSendStatus(pdev); 8009d02: 6878 ldr r0, [r7, #4] 8009d04: f000 f9f8 bl 800a0f8 } else { (void)USBD_CtlSendStatus(pdev); } break; 8009d08: e042 b.n 8009d90 else if (cfgidx != pdev->dev_config) 8009d0a: 4b24 ldr r3, [pc, #144] @ (8009d9c ) 8009d0c: 781b ldrb r3, [r3, #0] 8009d0e: 461a mov r2, r3 8009d10: 687b ldr r3, [r7, #4] 8009d12: 685b ldr r3, [r3, #4] 8009d14: 429a cmp r2, r3 8009d16: d02a beq.n 8009d6e (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8009d18: 687b ldr r3, [r7, #4] 8009d1a: 685b ldr r3, [r3, #4] 8009d1c: b2db uxtb r3, r3 8009d1e: 4619 mov r1, r3 8009d20: 6878 ldr r0, [r7, #4] 8009d22: f7fe ff80 bl 8008c26 pdev->dev_config = cfgidx; 8009d26: 4b1d ldr r3, [pc, #116] @ (8009d9c ) 8009d28: 781b ldrb r3, [r3, #0] 8009d2a: 461a mov r2, r3 8009d2c: 687b ldr r3, [r7, #4] 8009d2e: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8009d30: 4b1a ldr r3, [pc, #104] @ (8009d9c ) 8009d32: 781b ldrb r3, [r3, #0] 8009d34: 4619 mov r1, r3 8009d36: 6878 ldr r0, [r7, #4] 8009d38: f7fe ff59 bl 8008bee 8009d3c: 4603 mov r3, r0 8009d3e: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8009d40: 7bfb ldrb r3, [r7, #15] 8009d42: 2b00 cmp r3, #0 8009d44: d00f beq.n 8009d66 USBD_CtlError(pdev, req); 8009d46: 6839 ldr r1, [r7, #0] 8009d48: 6878 ldr r0, [r7, #4] 8009d4a: f000 f918 bl 8009f7e (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8009d4e: 687b ldr r3, [r7, #4] 8009d50: 685b ldr r3, [r3, #4] 8009d52: b2db uxtb r3, r3 8009d54: 4619 mov r1, r3 8009d56: 6878 ldr r0, [r7, #4] 8009d58: f7fe ff65 bl 8008c26 pdev->dev_state = USBD_STATE_ADDRESSED; 8009d5c: 687b ldr r3, [r7, #4] 8009d5e: 2202 movs r2, #2 8009d60: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8009d64: e014 b.n 8009d90 (void)USBD_CtlSendStatus(pdev); 8009d66: 6878 ldr r0, [r7, #4] 8009d68: f000 f9c6 bl 800a0f8 break; 8009d6c: e010 b.n 8009d90 (void)USBD_CtlSendStatus(pdev); 8009d6e: 6878 ldr r0, [r7, #4] 8009d70: f000 f9c2 bl 800a0f8 break; 8009d74: e00c b.n 8009d90 default: USBD_CtlError(pdev, req); 8009d76: 6839 ldr r1, [r7, #0] 8009d78: 6878 ldr r0, [r7, #4] 8009d7a: f000 f900 bl 8009f7e (void)USBD_ClrClassConfig(pdev, cfgidx); 8009d7e: 4b07 ldr r3, [pc, #28] @ (8009d9c ) 8009d80: 781b ldrb r3, [r3, #0] 8009d82: 4619 mov r1, r3 8009d84: 6878 ldr r0, [r7, #4] 8009d86: f7fe ff4e bl 8008c26 ret = USBD_FAIL; 8009d8a: 2303 movs r3, #3 8009d8c: 73fb strb r3, [r7, #15] break; 8009d8e: bf00 nop } return ret; 8009d90: 7bfb ldrb r3, [r7, #15] } 8009d92: 4618 mov r0, r3 8009d94: 3710 adds r7, #16 8009d96: 46bd mov sp, r7 8009d98: bd80 pop {r7, pc} 8009d9a: bf00 nop 8009d9c: 20000720 .word 0x20000720 08009da0 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009da0: b580 push {r7, lr} 8009da2: b082 sub sp, #8 8009da4: af00 add r7, sp, #0 8009da6: 6078 str r0, [r7, #4] 8009da8: 6039 str r1, [r7, #0] if (req->wLength != 1U) 8009daa: 683b ldr r3, [r7, #0] 8009dac: 88db ldrh r3, [r3, #6] 8009dae: 2b01 cmp r3, #1 8009db0: d004 beq.n 8009dbc { USBD_CtlError(pdev, req); 8009db2: 6839 ldr r1, [r7, #0] 8009db4: 6878 ldr r0, [r7, #4] 8009db6: f000 f8e2 bl 8009f7e default: USBD_CtlError(pdev, req); break; } } } 8009dba: e023 b.n 8009e04 switch (pdev->dev_state) 8009dbc: 687b ldr r3, [r7, #4] 8009dbe: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009dc2: b2db uxtb r3, r3 8009dc4: 2b02 cmp r3, #2 8009dc6: dc02 bgt.n 8009dce 8009dc8: 2b00 cmp r3, #0 8009dca: dc03 bgt.n 8009dd4 8009dcc: e015 b.n 8009dfa 8009dce: 2b03 cmp r3, #3 8009dd0: d00b beq.n 8009dea 8009dd2: e012 b.n 8009dfa pdev->dev_default_config = 0U; 8009dd4: 687b ldr r3, [r7, #4] 8009dd6: 2200 movs r2, #0 8009dd8: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 8009dda: 687b ldr r3, [r7, #4] 8009ddc: 3308 adds r3, #8 8009dde: 2201 movs r2, #1 8009de0: 4619 mov r1, r3 8009de2: 6878 ldr r0, [r7, #4] 8009de4: f000 f948 bl 800a078 break; 8009de8: e00c b.n 8009e04 (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 8009dea: 687b ldr r3, [r7, #4] 8009dec: 3304 adds r3, #4 8009dee: 2201 movs r2, #1 8009df0: 4619 mov r1, r3 8009df2: 6878 ldr r0, [r7, #4] 8009df4: f000 f940 bl 800a078 break; 8009df8: e004 b.n 8009e04 USBD_CtlError(pdev, req); 8009dfa: 6839 ldr r1, [r7, #0] 8009dfc: 6878 ldr r0, [r7, #4] 8009dfe: f000 f8be bl 8009f7e break; 8009e02: bf00 nop } 8009e04: bf00 nop 8009e06: 3708 adds r7, #8 8009e08: 46bd mov sp, r7 8009e0a: bd80 pop {r7, pc} 08009e0c : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009e0c: b580 push {r7, lr} 8009e0e: b082 sub sp, #8 8009e10: af00 add r7, sp, #0 8009e12: 6078 str r0, [r7, #4] 8009e14: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8009e16: 687b ldr r3, [r7, #4] 8009e18: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009e1c: b2db uxtb r3, r3 8009e1e: 3b01 subs r3, #1 8009e20: 2b02 cmp r3, #2 8009e22: d81e bhi.n 8009e62 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 8009e24: 683b ldr r3, [r7, #0] 8009e26: 88db ldrh r3, [r3, #6] 8009e28: 2b02 cmp r3, #2 8009e2a: d004 beq.n 8009e36 { USBD_CtlError(pdev, req); 8009e2c: 6839 ldr r1, [r7, #0] 8009e2e: 6878 ldr r0, [r7, #4] 8009e30: f000 f8a5 bl 8009f7e break; 8009e34: e01a b.n 8009e6c } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 8009e36: 687b ldr r3, [r7, #4] 8009e38: 2201 movs r2, #1 8009e3a: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif /* USBD_SELF_POWERED */ if (pdev->dev_remote_wakeup != 0U) 8009e3c: 687b ldr r3, [r7, #4] 8009e3e: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 8009e42: 2b00 cmp r3, #0 8009e44: d005 beq.n 8009e52 { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 8009e46: 687b ldr r3, [r7, #4] 8009e48: 68db ldr r3, [r3, #12] 8009e4a: f043 0202 orr.w r2, r3, #2 8009e4e: 687b ldr r3, [r7, #4] 8009e50: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 8009e52: 687b ldr r3, [r7, #4] 8009e54: 330c adds r3, #12 8009e56: 2202 movs r2, #2 8009e58: 4619 mov r1, r3 8009e5a: 6878 ldr r0, [r7, #4] 8009e5c: f000 f90c bl 800a078 break; 8009e60: e004 b.n 8009e6c default: USBD_CtlError(pdev, req); 8009e62: 6839 ldr r1, [r7, #0] 8009e64: 6878 ldr r0, [r7, #4] 8009e66: f000 f88a bl 8009f7e break; 8009e6a: bf00 nop } } 8009e6c: bf00 nop 8009e6e: 3708 adds r7, #8 8009e70: 46bd mov sp, r7 8009e72: bd80 pop {r7, pc} 08009e74 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009e74: b580 push {r7, lr} 8009e76: b082 sub sp, #8 8009e78: af00 add r7, sp, #0 8009e7a: 6078 str r0, [r7, #4] 8009e7c: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8009e7e: 683b ldr r3, [r7, #0] 8009e80: 885b ldrh r3, [r3, #2] 8009e82: 2b01 cmp r3, #1 8009e84: d107 bne.n 8009e96 { pdev->dev_remote_wakeup = 1U; 8009e86: 687b ldr r3, [r7, #4] 8009e88: 2201 movs r2, #1 8009e8a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8009e8e: 6878 ldr r0, [r7, #4] 8009e90: f000 f932 bl 800a0f8 } else { USBD_CtlError(pdev, req); } } 8009e94: e013 b.n 8009ebe else if (req->wValue == USB_FEATURE_TEST_MODE) 8009e96: 683b ldr r3, [r7, #0] 8009e98: 885b ldrh r3, [r3, #2] 8009e9a: 2b02 cmp r3, #2 8009e9c: d10b bne.n 8009eb6 pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); 8009e9e: 683b ldr r3, [r7, #0] 8009ea0: 889b ldrh r3, [r3, #4] 8009ea2: 0a1b lsrs r3, r3, #8 8009ea4: b29b uxth r3, r3 8009ea6: b2da uxtb r2, r3 8009ea8: 687b ldr r3, [r7, #4] 8009eaa: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 (void)USBD_CtlSendStatus(pdev); 8009eae: 6878 ldr r0, [r7, #4] 8009eb0: f000 f922 bl 800a0f8 } 8009eb4: e003 b.n 8009ebe USBD_CtlError(pdev, req); 8009eb6: 6839 ldr r1, [r7, #0] 8009eb8: 6878 ldr r0, [r7, #4] 8009eba: f000 f860 bl 8009f7e } 8009ebe: bf00 nop 8009ec0: 3708 adds r7, #8 8009ec2: 46bd mov sp, r7 8009ec4: bd80 pop {r7, pc} 08009ec6 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009ec6: b580 push {r7, lr} 8009ec8: b082 sub sp, #8 8009eca: af00 add r7, sp, #0 8009ecc: 6078 str r0, [r7, #4] 8009ece: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8009ed0: 687b ldr r3, [r7, #4] 8009ed2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009ed6: b2db uxtb r3, r3 8009ed8: 3b01 subs r3, #1 8009eda: 2b02 cmp r3, #2 8009edc: d80b bhi.n 8009ef6 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8009ede: 683b ldr r3, [r7, #0] 8009ee0: 885b ldrh r3, [r3, #2] 8009ee2: 2b01 cmp r3, #1 8009ee4: d10c bne.n 8009f00 { pdev->dev_remote_wakeup = 0U; 8009ee6: 687b ldr r3, [r7, #4] 8009ee8: 2200 movs r2, #0 8009eea: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8009eee: 6878 ldr r0, [r7, #4] 8009ef0: f000 f902 bl 800a0f8 } break; 8009ef4: e004 b.n 8009f00 default: USBD_CtlError(pdev, req); 8009ef6: 6839 ldr r1, [r7, #0] 8009ef8: 6878 ldr r0, [r7, #4] 8009efa: f000 f840 bl 8009f7e break; 8009efe: e000 b.n 8009f02 break; 8009f00: bf00 nop } } 8009f02: bf00 nop 8009f04: 3708 adds r7, #8 8009f06: 46bd mov sp, r7 8009f08: bd80 pop {r7, pc} 08009f0a : * @param req: usb request * @param pdata: setup data pointer * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 8009f0a: b580 push {r7, lr} 8009f0c: b084 sub sp, #16 8009f0e: af00 add r7, sp, #0 8009f10: 6078 str r0, [r7, #4] 8009f12: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 8009f14: 683b ldr r3, [r7, #0] 8009f16: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 8009f18: 68fb ldr r3, [r7, #12] 8009f1a: 781a ldrb r2, [r3, #0] 8009f1c: 687b ldr r3, [r7, #4] 8009f1e: 701a strb r2, [r3, #0] pbuff++; 8009f20: 68fb ldr r3, [r7, #12] 8009f22: 3301 adds r3, #1 8009f24: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 8009f26: 68fb ldr r3, [r7, #12] 8009f28: 781a ldrb r2, [r3, #0] 8009f2a: 687b ldr r3, [r7, #4] 8009f2c: 705a strb r2, [r3, #1] pbuff++; 8009f2e: 68fb ldr r3, [r7, #12] 8009f30: 3301 adds r3, #1 8009f32: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 8009f34: 68f8 ldr r0, [r7, #12] 8009f36: f7ff fa13 bl 8009360 8009f3a: 4603 mov r3, r0 8009f3c: 461a mov r2, r3 8009f3e: 687b ldr r3, [r7, #4] 8009f40: 805a strh r2, [r3, #2] pbuff++; 8009f42: 68fb ldr r3, [r7, #12] 8009f44: 3301 adds r3, #1 8009f46: 60fb str r3, [r7, #12] pbuff++; 8009f48: 68fb ldr r3, [r7, #12] 8009f4a: 3301 adds r3, #1 8009f4c: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 8009f4e: 68f8 ldr r0, [r7, #12] 8009f50: f7ff fa06 bl 8009360 8009f54: 4603 mov r3, r0 8009f56: 461a mov r2, r3 8009f58: 687b ldr r3, [r7, #4] 8009f5a: 809a strh r2, [r3, #4] pbuff++; 8009f5c: 68fb ldr r3, [r7, #12] 8009f5e: 3301 adds r3, #1 8009f60: 60fb str r3, [r7, #12] pbuff++; 8009f62: 68fb ldr r3, [r7, #12] 8009f64: 3301 adds r3, #1 8009f66: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 8009f68: 68f8 ldr r0, [r7, #12] 8009f6a: f7ff f9f9 bl 8009360 8009f6e: 4603 mov r3, r0 8009f70: 461a mov r2, r3 8009f72: 687b ldr r3, [r7, #4] 8009f74: 80da strh r2, [r3, #6] } 8009f76: bf00 nop 8009f78: 3710 adds r7, #16 8009f7a: 46bd mov sp, r7 8009f7c: bd80 pop {r7, pc} 08009f7e : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009f7e: b580 push {r7, lr} 8009f80: b082 sub sp, #8 8009f82: af00 add r7, sp, #0 8009f84: 6078 str r0, [r7, #4] 8009f86: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 8009f88: 2180 movs r1, #128 @ 0x80 8009f8a: 6878 ldr r0, [r7, #4] 8009f8c: f000 fc2a bl 800a7e4 (void)USBD_LL_StallEP(pdev, 0U); 8009f90: 2100 movs r1, #0 8009f92: 6878 ldr r0, [r7, #4] 8009f94: f000 fc26 bl 800a7e4 } 8009f98: bf00 nop 8009f9a: 3708 adds r7, #8 8009f9c: 46bd mov sp, r7 8009f9e: bd80 pop {r7, pc} 08009fa0 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 8009fa0: b580 push {r7, lr} 8009fa2: b086 sub sp, #24 8009fa4: af00 add r7, sp, #0 8009fa6: 60f8 str r0, [r7, #12] 8009fa8: 60b9 str r1, [r7, #8] 8009faa: 607a str r2, [r7, #4] uint8_t idx = 0U; 8009fac: 2300 movs r3, #0 8009fae: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 8009fb0: 68fb ldr r3, [r7, #12] 8009fb2: 2b00 cmp r3, #0 8009fb4: d042 beq.n 800a03c { return; } pdesc = desc; 8009fb6: 68fb ldr r3, [r7, #12] 8009fb8: 613b str r3, [r7, #16] *len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U); 8009fba: 6938 ldr r0, [r7, #16] 8009fbc: f000 f842 bl 800a044 8009fc0: 4603 mov r3, r0 8009fc2: 3301 adds r3, #1 8009fc4: 005b lsls r3, r3, #1 8009fc6: f5b3 7f00 cmp.w r3, #512 @ 0x200 8009fca: d808 bhi.n 8009fde 8009fcc: 6938 ldr r0, [r7, #16] 8009fce: f000 f839 bl 800a044 8009fd2: 4603 mov r3, r0 8009fd4: 3301 adds r3, #1 8009fd6: b29b uxth r3, r3 8009fd8: 005b lsls r3, r3, #1 8009fda: b29a uxth r2, r3 8009fdc: e001 b.n 8009fe2 8009fde: f44f 7200 mov.w r2, #512 @ 0x200 8009fe2: 687b ldr r3, [r7, #4] 8009fe4: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 8009fe6: 7dfb ldrb r3, [r7, #23] 8009fe8: 68ba ldr r2, [r7, #8] 8009fea: 4413 add r3, r2 8009fec: 687a ldr r2, [r7, #4] 8009fee: 7812 ldrb r2, [r2, #0] 8009ff0: 701a strb r2, [r3, #0] idx++; 8009ff2: 7dfb ldrb r3, [r7, #23] 8009ff4: 3301 adds r3, #1 8009ff6: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 8009ff8: 7dfb ldrb r3, [r7, #23] 8009ffa: 68ba ldr r2, [r7, #8] 8009ffc: 4413 add r3, r2 8009ffe: 2203 movs r2, #3 800a000: 701a strb r2, [r3, #0] idx++; 800a002: 7dfb ldrb r3, [r7, #23] 800a004: 3301 adds r3, #1 800a006: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 800a008: e013 b.n 800a032 { unicode[idx] = *pdesc; 800a00a: 7dfb ldrb r3, [r7, #23] 800a00c: 68ba ldr r2, [r7, #8] 800a00e: 4413 add r3, r2 800a010: 693a ldr r2, [r7, #16] 800a012: 7812 ldrb r2, [r2, #0] 800a014: 701a strb r2, [r3, #0] pdesc++; 800a016: 693b ldr r3, [r7, #16] 800a018: 3301 adds r3, #1 800a01a: 613b str r3, [r7, #16] idx++; 800a01c: 7dfb ldrb r3, [r7, #23] 800a01e: 3301 adds r3, #1 800a020: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 800a022: 7dfb ldrb r3, [r7, #23] 800a024: 68ba ldr r2, [r7, #8] 800a026: 4413 add r3, r2 800a028: 2200 movs r2, #0 800a02a: 701a strb r2, [r3, #0] idx++; 800a02c: 7dfb ldrb r3, [r7, #23] 800a02e: 3301 adds r3, #1 800a030: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 800a032: 693b ldr r3, [r7, #16] 800a034: 781b ldrb r3, [r3, #0] 800a036: 2b00 cmp r3, #0 800a038: d1e7 bne.n 800a00a 800a03a: e000 b.n 800a03e return; 800a03c: bf00 nop } } 800a03e: 3718 adds r7, #24 800a040: 46bd mov sp, r7 800a042: bd80 pop {r7, pc} 0800a044 : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 800a044: b480 push {r7} 800a046: b085 sub sp, #20 800a048: af00 add r7, sp, #0 800a04a: 6078 str r0, [r7, #4] uint8_t len = 0U; 800a04c: 2300 movs r3, #0 800a04e: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 800a050: 687b ldr r3, [r7, #4] 800a052: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 800a054: e005 b.n 800a062 { len++; 800a056: 7bfb ldrb r3, [r7, #15] 800a058: 3301 adds r3, #1 800a05a: 73fb strb r3, [r7, #15] pbuff++; 800a05c: 68bb ldr r3, [r7, #8] 800a05e: 3301 adds r3, #1 800a060: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 800a062: 68bb ldr r3, [r7, #8] 800a064: 781b ldrb r3, [r3, #0] 800a066: 2b00 cmp r3, #0 800a068: d1f5 bne.n 800a056 } return len; 800a06a: 7bfb ldrb r3, [r7, #15] } 800a06c: 4618 mov r0, r3 800a06e: 3714 adds r7, #20 800a070: 46bd mov sp, r7 800a072: f85d 7b04 ldr.w r7, [sp], #4 800a076: 4770 bx lr 0800a078 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a078: b580 push {r7, lr} 800a07a: b084 sub sp, #16 800a07c: af00 add r7, sp, #0 800a07e: 60f8 str r0, [r7, #12] 800a080: 60b9 str r1, [r7, #8] 800a082: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 800a084: 68fb ldr r3, [r7, #12] 800a086: 2202 movs r2, #2 800a088: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_in[0].total_length = len; 800a08c: 68fb ldr r3, [r7, #12] 800a08e: 687a ldr r2, [r7, #4] 800a090: 615a str r2, [r3, #20] pdev->ep_in[0].pbuffer = pbuf; 800a092: 68fb ldr r3, [r7, #12] 800a094: 68ba ldr r2, [r7, #8] 800a096: 625a str r2, [r3, #36] @ 0x24 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 800a098: 68fb ldr r3, [r7, #12] 800a09a: 687a ldr r2, [r7, #4] 800a09c: 619a str r2, [r3, #24] #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800a09e: 687b ldr r3, [r7, #4] 800a0a0: 68ba ldr r2, [r7, #8] 800a0a2: 2100 movs r1, #0 800a0a4: 68f8 ldr r0, [r7, #12] 800a0a6: f000 fc26 bl 800a8f6 return USBD_OK; 800a0aa: 2300 movs r3, #0 } 800a0ac: 4618 mov r0, r3 800a0ae: 3710 adds r7, #16 800a0b0: 46bd mov sp, r7 800a0b2: bd80 pop {r7, pc} 0800a0b4 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a0b4: b580 push {r7, lr} 800a0b6: b084 sub sp, #16 800a0b8: af00 add r7, sp, #0 800a0ba: 60f8 str r0, [r7, #12] 800a0bc: 60b9 str r1, [r7, #8] 800a0be: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800a0c0: 687b ldr r3, [r7, #4] 800a0c2: 68ba ldr r2, [r7, #8] 800a0c4: 2100 movs r1, #0 800a0c6: 68f8 ldr r0, [r7, #12] 800a0c8: f000 fc15 bl 800a8f6 return USBD_OK; 800a0cc: 2300 movs r3, #0 } 800a0ce: 4618 mov r0, r3 800a0d0: 3710 adds r7, #16 800a0d2: 46bd mov sp, r7 800a0d4: bd80 pop {r7, pc} 0800a0d6 : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a0d6: b580 push {r7, lr} 800a0d8: b084 sub sp, #16 800a0da: af00 add r7, sp, #0 800a0dc: 60f8 str r0, [r7, #12] 800a0de: 60b9 str r1, [r7, #8] 800a0e0: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 800a0e2: 687b ldr r3, [r7, #4] 800a0e4: 68ba ldr r2, [r7, #8] 800a0e6: 2100 movs r1, #0 800a0e8: 68f8 ldr r0, [r7, #12] 800a0ea: f000 fc25 bl 800a938 return USBD_OK; 800a0ee: 2300 movs r3, #0 } 800a0f0: 4618 mov r0, r3 800a0f2: 3710 adds r7, #16 800a0f4: 46bd mov sp, r7 800a0f6: bd80 pop {r7, pc} 0800a0f8 : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 800a0f8: b580 push {r7, lr} 800a0fa: b082 sub sp, #8 800a0fc: af00 add r7, sp, #0 800a0fe: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 800a100: 687b ldr r3, [r7, #4] 800a102: 2204 movs r2, #4 800a104: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 800a108: 2300 movs r3, #0 800a10a: 2200 movs r2, #0 800a10c: 2100 movs r1, #0 800a10e: 6878 ldr r0, [r7, #4] 800a110: f000 fbf1 bl 800a8f6 return USBD_OK; 800a114: 2300 movs r3, #0 } 800a116: 4618 mov r0, r3 800a118: 3708 adds r7, #8 800a11a: 46bd mov sp, r7 800a11c: bd80 pop {r7, pc} 0800a11e : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 800a11e: b580 push {r7, lr} 800a120: b082 sub sp, #8 800a122: af00 add r7, sp, #0 800a124: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 800a126: 687b ldr r3, [r7, #4] 800a128: 2205 movs r2, #5 800a12a: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 800a12e: 2300 movs r3, #0 800a130: 2200 movs r2, #0 800a132: 2100 movs r1, #0 800a134: 6878 ldr r0, [r7, #4] 800a136: f000 fbff bl 800a938 return USBD_OK; 800a13a: 2300 movs r3, #0 } 800a13c: 4618 mov r0, r3 800a13e: 3708 adds r7, #8 800a140: 46bd mov sp, r7 800a142: bd80 pop {r7, pc} 0800a144 : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 800a144: b580 push {r7, lr} 800a146: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) 800a148: 2200 movs r2, #0 800a14a: 490e ldr r1, [pc, #56] @ (800a184 ) 800a14c: 480e ldr r0, [pc, #56] @ (800a188 ) 800a14e: f7fe fcd1 bl 8008af4 800a152: 4603 mov r3, r0 800a154: 2b00 cmp r3, #0 800a156: d001 beq.n 800a15c { Error_Handler(); 800a158: f7f6 fdfe bl 8000d58 } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) 800a15c: 490b ldr r1, [pc, #44] @ (800a18c ) 800a15e: 480a ldr r0, [pc, #40] @ (800a188 ) 800a160: f7fe fcf8 bl 8008b54 800a164: 4603 mov r3, r0 800a166: 2b00 cmp r3, #0 800a168: d001 beq.n 800a16e { Error_Handler(); 800a16a: f7f6 fdf5 bl 8000d58 } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) 800a16e: 4806 ldr r0, [pc, #24] @ (800a188 ) 800a170: f7fe fd26 bl 8008bc0 800a174: 4603 mov r3, r0 800a176: 2b00 cmp r3, #0 800a178: d001 beq.n 800a17e { Error_Handler(); 800a17a: f7f6 fded bl 8000d58 } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 800a17e: bf00 nop 800a180: bd80 pop {r7, pc} 800a182: bf00 nop 800a184: 20000140 .word 0x20000140 800a188: 20000724 .word 0x20000724 800a18c: 2000009c .word 0x2000009c 0800a190 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a190: b480 push {r7} 800a192: b083 sub sp, #12 800a194: af00 add r7, sp, #0 800a196: 4603 mov r3, r0 800a198: 6039 str r1, [r7, #0] 800a19a: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_DeviceDesc); 800a19c: 683b ldr r3, [r7, #0] 800a19e: 2212 movs r2, #18 800a1a0: 801a strh r2, [r3, #0] return USBD_FS_DeviceDesc; 800a1a2: 4b03 ldr r3, [pc, #12] @ (800a1b0 ) } 800a1a4: 4618 mov r0, r3 800a1a6: 370c adds r7, #12 800a1a8: 46bd mov sp, r7 800a1aa: f85d 7b04 ldr.w r7, [sp], #4 800a1ae: 4770 bx lr 800a1b0: 20000160 .word 0x20000160 0800a1b4 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a1b4: b480 push {r7} 800a1b6: b083 sub sp, #12 800a1b8: af00 add r7, sp, #0 800a1ba: 4603 mov r3, r0 800a1bc: 6039 str r1, [r7, #0] 800a1be: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 800a1c0: 683b ldr r3, [r7, #0] 800a1c2: 2204 movs r2, #4 800a1c4: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 800a1c6: 4b03 ldr r3, [pc, #12] @ (800a1d4 ) } 800a1c8: 4618 mov r0, r3 800a1ca: 370c adds r7, #12 800a1cc: 46bd mov sp, r7 800a1ce: f85d 7b04 ldr.w r7, [sp], #4 800a1d2: 4770 bx lr 800a1d4: 20000180 .word 0x20000180 0800a1d8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a1d8: b580 push {r7, lr} 800a1da: b082 sub sp, #8 800a1dc: af00 add r7, sp, #0 800a1de: 4603 mov r3, r0 800a1e0: 6039 str r1, [r7, #0] 800a1e2: 71fb strb r3, [r7, #7] if(speed == 0) 800a1e4: 79fb ldrb r3, [r7, #7] 800a1e6: 2b00 cmp r3, #0 800a1e8: d105 bne.n 800a1f6 { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800a1ea: 683a ldr r2, [r7, #0] 800a1ec: 4907 ldr r1, [pc, #28] @ (800a20c ) 800a1ee: 4808 ldr r0, [pc, #32] @ (800a210 ) 800a1f0: f7ff fed6 bl 8009fa0 800a1f4: e004 b.n 800a200 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800a1f6: 683a ldr r2, [r7, #0] 800a1f8: 4904 ldr r1, [pc, #16] @ (800a20c ) 800a1fa: 4805 ldr r0, [pc, #20] @ (800a210 ) 800a1fc: f7ff fed0 bl 8009fa0 } return USBD_StrDesc; 800a200: 4b02 ldr r3, [pc, #8] @ (800a20c ) } 800a202: 4618 mov r0, r3 800a204: 3708 adds r7, #8 800a206: 46bd mov sp, r7 800a208: bd80 pop {r7, pc} 800a20a: bf00 nop 800a20c: 20000a00 .word 0x20000a00 800a210: 0800ab2c .word 0x0800ab2c 0800a214 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a214: b580 push {r7, lr} 800a216: b082 sub sp, #8 800a218: af00 add r7, sp, #0 800a21a: 4603 mov r3, r0 800a21c: 6039 str r1, [r7, #0] 800a21e: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 800a220: 683a ldr r2, [r7, #0] 800a222: 4904 ldr r1, [pc, #16] @ (800a234 ) 800a224: 4804 ldr r0, [pc, #16] @ (800a238 ) 800a226: f7ff febb bl 8009fa0 return USBD_StrDesc; 800a22a: 4b02 ldr r3, [pc, #8] @ (800a234 ) } 800a22c: 4618 mov r0, r3 800a22e: 3708 adds r7, #8 800a230: 46bd mov sp, r7 800a232: bd80 pop {r7, pc} 800a234: 20000a00 .word 0x20000a00 800a238: 0800ab40 .word 0x0800ab40 0800a23c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a23c: b580 push {r7, lr} 800a23e: b082 sub sp, #8 800a240: af00 add r7, sp, #0 800a242: 4603 mov r3, r0 800a244: 6039 str r1, [r7, #0] 800a246: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 800a248: 683b ldr r3, [r7, #0] 800a24a: 221a movs r2, #26 800a24c: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 800a24e: f000 f855 bl 800a2fc /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ /* USER CODE END USBD_FS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 800a252: 4b02 ldr r3, [pc, #8] @ (800a25c ) } 800a254: 4618 mov r0, r3 800a256: 3708 adds r7, #8 800a258: 46bd mov sp, r7 800a25a: bd80 pop {r7, pc} 800a25c: 20000184 .word 0x20000184 0800a260 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a260: b580 push {r7, lr} 800a262: b082 sub sp, #8 800a264: af00 add r7, sp, #0 800a266: 4603 mov r3, r0 800a268: 6039 str r1, [r7, #0] 800a26a: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 800a26c: 79fb ldrb r3, [r7, #7] 800a26e: 2b00 cmp r3, #0 800a270: d105 bne.n 800a27e { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800a272: 683a ldr r2, [r7, #0] 800a274: 4907 ldr r1, [pc, #28] @ (800a294 ) 800a276: 4808 ldr r0, [pc, #32] @ (800a298 ) 800a278: f7ff fe92 bl 8009fa0 800a27c: e004 b.n 800a288 } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800a27e: 683a ldr r2, [r7, #0] 800a280: 4904 ldr r1, [pc, #16] @ (800a294 ) 800a282: 4805 ldr r0, [pc, #20] @ (800a298 ) 800a284: f7ff fe8c bl 8009fa0 } return USBD_StrDesc; 800a288: 4b02 ldr r3, [pc, #8] @ (800a294 ) } 800a28a: 4618 mov r0, r3 800a28c: 3708 adds r7, #8 800a28e: 46bd mov sp, r7 800a290: bd80 pop {r7, pc} 800a292: bf00 nop 800a294: 20000a00 .word 0x20000a00 800a298: 0800ab4c .word 0x0800ab4c 0800a29c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a29c: b580 push {r7, lr} 800a29e: b082 sub sp, #8 800a2a0: af00 add r7, sp, #0 800a2a2: 4603 mov r3, r0 800a2a4: 6039 str r1, [r7, #0] 800a2a6: 71fb strb r3, [r7, #7] if(speed == 0) 800a2a8: 79fb ldrb r3, [r7, #7] 800a2aa: 2b00 cmp r3, #0 800a2ac: d105 bne.n 800a2ba { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800a2ae: 683a ldr r2, [r7, #0] 800a2b0: 4907 ldr r1, [pc, #28] @ (800a2d0 ) 800a2b2: 4808 ldr r0, [pc, #32] @ (800a2d4 ) 800a2b4: f7ff fe74 bl 8009fa0 800a2b8: e004 b.n 800a2c4 } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800a2ba: 683a ldr r2, [r7, #0] 800a2bc: 4904 ldr r1, [pc, #16] @ (800a2d0 ) 800a2be: 4805 ldr r0, [pc, #20] @ (800a2d4 ) 800a2c0: f7ff fe6e bl 8009fa0 } return USBD_StrDesc; 800a2c4: 4b02 ldr r3, [pc, #8] @ (800a2d0 ) } 800a2c6: 4618 mov r0, r3 800a2c8: 3708 adds r7, #8 800a2ca: 46bd mov sp, r7 800a2cc: bd80 pop {r7, pc} 800a2ce: bf00 nop 800a2d0: 20000a00 .word 0x20000a00 800a2d4: 0800ab58 .word 0x0800ab58 0800a2d8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a2d8: b480 push {r7} 800a2da: b083 sub sp, #12 800a2dc: af00 add r7, sp, #0 800a2de: 4603 mov r3, r0 800a2e0: 6039 str r1, [r7, #0] 800a2e2: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_BOSDesc); 800a2e4: 683b ldr r3, [r7, #0] 800a2e6: 220c movs r2, #12 800a2e8: 801a strh r2, [r3, #0] return (uint8_t*)USBD_FS_BOSDesc; 800a2ea: 4b03 ldr r3, [pc, #12] @ (800a2f8 ) } 800a2ec: 4618 mov r0, r3 800a2ee: 370c adds r7, #12 800a2f0: 46bd mov sp, r7 800a2f2: f85d 7b04 ldr.w r7, [sp], #4 800a2f6: 4770 bx lr 800a2f8: 20000174 .word 0x20000174 0800a2fc : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 800a2fc: b580 push {r7, lr} 800a2fe: b084 sub sp, #16 800a300: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 800a302: 4b0f ldr r3, [pc, #60] @ (800a340 ) 800a304: 681b ldr r3, [r3, #0] 800a306: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 800a308: 4b0e ldr r3, [pc, #56] @ (800a344 ) 800a30a: 681b ldr r3, [r3, #0] 800a30c: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 800a30e: 4b0e ldr r3, [pc, #56] @ (800a348 ) 800a310: 681b ldr r3, [r3, #0] 800a312: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 800a314: 68fa ldr r2, [r7, #12] 800a316: 687b ldr r3, [r7, #4] 800a318: 4413 add r3, r2 800a31a: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 800a31c: 68fb ldr r3, [r7, #12] 800a31e: 2b00 cmp r3, #0 800a320: d009 beq.n 800a336 { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 800a322: 2208 movs r2, #8 800a324: 4909 ldr r1, [pc, #36] @ (800a34c ) 800a326: 68f8 ldr r0, [r7, #12] 800a328: f000 f814 bl 800a354 IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 800a32c: 2204 movs r2, #4 800a32e: 4908 ldr r1, [pc, #32] @ (800a350 ) 800a330: 68b8 ldr r0, [r7, #8] 800a332: f000 f80f bl 800a354 } } 800a336: bf00 nop 800a338: 3710 adds r7, #16 800a33a: 46bd mov sp, r7 800a33c: bd80 pop {r7, pc} 800a33e: bf00 nop 800a340: 1fff7a10 .word 0x1fff7a10 800a344: 1fff7a14 .word 0x1fff7a14 800a348: 1fff7a18 .word 0x1fff7a18 800a34c: 20000186 .word 0x20000186 800a350: 20000196 .word 0x20000196 0800a354 : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 800a354: b480 push {r7} 800a356: b087 sub sp, #28 800a358: af00 add r7, sp, #0 800a35a: 60f8 str r0, [r7, #12] 800a35c: 60b9 str r1, [r7, #8] 800a35e: 4613 mov r3, r2 800a360: 71fb strb r3, [r7, #7] uint8_t idx = 0; 800a362: 2300 movs r3, #0 800a364: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 800a366: 2300 movs r3, #0 800a368: 75fb strb r3, [r7, #23] 800a36a: e027 b.n 800a3bc { if (((value >> 28)) < 0xA) 800a36c: 68fb ldr r3, [r7, #12] 800a36e: 0f1b lsrs r3, r3, #28 800a370: 2b09 cmp r3, #9 800a372: d80b bhi.n 800a38c { pbuf[2 * idx] = (value >> 28) + '0'; 800a374: 68fb ldr r3, [r7, #12] 800a376: 0f1b lsrs r3, r3, #28 800a378: b2da uxtb r2, r3 800a37a: 7dfb ldrb r3, [r7, #23] 800a37c: 005b lsls r3, r3, #1 800a37e: 4619 mov r1, r3 800a380: 68bb ldr r3, [r7, #8] 800a382: 440b add r3, r1 800a384: 3230 adds r2, #48 @ 0x30 800a386: b2d2 uxtb r2, r2 800a388: 701a strb r2, [r3, #0] 800a38a: e00a b.n 800a3a2 } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 800a38c: 68fb ldr r3, [r7, #12] 800a38e: 0f1b lsrs r3, r3, #28 800a390: b2da uxtb r2, r3 800a392: 7dfb ldrb r3, [r7, #23] 800a394: 005b lsls r3, r3, #1 800a396: 4619 mov r1, r3 800a398: 68bb ldr r3, [r7, #8] 800a39a: 440b add r3, r1 800a39c: 3237 adds r2, #55 @ 0x37 800a39e: b2d2 uxtb r2, r2 800a3a0: 701a strb r2, [r3, #0] } value = value << 4; 800a3a2: 68fb ldr r3, [r7, #12] 800a3a4: 011b lsls r3, r3, #4 800a3a6: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 800a3a8: 7dfb ldrb r3, [r7, #23] 800a3aa: 005b lsls r3, r3, #1 800a3ac: 3301 adds r3, #1 800a3ae: 68ba ldr r2, [r7, #8] 800a3b0: 4413 add r3, r2 800a3b2: 2200 movs r2, #0 800a3b4: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 800a3b6: 7dfb ldrb r3, [r7, #23] 800a3b8: 3301 adds r3, #1 800a3ba: 75fb strb r3, [r7, #23] 800a3bc: 7dfa ldrb r2, [r7, #23] 800a3be: 79fb ldrb r3, [r7, #7] 800a3c0: 429a cmp r2, r3 800a3c2: d3d3 bcc.n 800a36c } } 800a3c4: bf00 nop 800a3c6: bf00 nop 800a3c8: 371c adds r7, #28 800a3ca: 46bd mov sp, r7 800a3cc: f85d 7b04 ldr.w r7, [sp], #4 800a3d0: 4770 bx lr ... 0800a3d4 : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 800a3d4: b580 push {r7, lr} 800a3d6: b0a0 sub sp, #128 @ 0x80 800a3d8: af00 add r7, sp, #0 800a3da: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a3dc: f107 036c add.w r3, r7, #108 @ 0x6c 800a3e0: 2200 movs r2, #0 800a3e2: 601a str r2, [r3, #0] 800a3e4: 605a str r2, [r3, #4] 800a3e6: 609a str r2, [r3, #8] 800a3e8: 60da str r2, [r3, #12] 800a3ea: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 800a3ec: f107 0310 add.w r3, r7, #16 800a3f0: 225c movs r2, #92 @ 0x5c 800a3f2: 2100 movs r1, #0 800a3f4: 4618 mov r0, r3 800a3f6: f000 fb53 bl 800aaa0 if(pcdHandle->Instance==USB_OTG_FS) 800a3fa: 687b ldr r3, [r7, #4] 800a3fc: 681b ldr r3, [r3, #0] 800a3fe: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800a402: d149 bne.n 800a498 /* USER CODE END USB_OTG_FS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; 800a404: f44f 7380 mov.w r3, #256 @ 0x100 800a408: 613b str r3, [r7, #16] PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; 800a40a: 2300 movs r3, #0 800a40c: 667b str r3, [r7, #100] @ 0x64 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800a40e: f107 0310 add.w r3, r7, #16 800a412: 4618 mov r0, r3 800a414: f7f9 fec6 bl 80041a4 800a418: 4603 mov r3, r0 800a41a: 2b00 cmp r3, #0 800a41c: d001 beq.n 800a422 { Error_Handler(); 800a41e: f7f6 fc9b bl 8000d58 } __HAL_RCC_GPIOA_CLK_ENABLE(); 800a422: 2300 movs r3, #0 800a424: 60fb str r3, [r7, #12] 800a426: 4b1e ldr r3, [pc, #120] @ (800a4a0 ) 800a428: 6b1b ldr r3, [r3, #48] @ 0x30 800a42a: 4a1d ldr r2, [pc, #116] @ (800a4a0 ) 800a42c: f043 0301 orr.w r3, r3, #1 800a430: 6313 str r3, [r2, #48] @ 0x30 800a432: 4b1b ldr r3, [pc, #108] @ (800a4a0 ) 800a434: 6b1b ldr r3, [r3, #48] @ 0x30 800a436: f003 0301 and.w r3, r3, #1 800a43a: 60fb str r3, [r7, #12] 800a43c: 68fb ldr r3, [r7, #12] /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 800a43e: f44f 53c0 mov.w r3, #6144 @ 0x1800 800a442: 66fb str r3, [r7, #108] @ 0x6c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800a444: 2302 movs r3, #2 800a446: 673b str r3, [r7, #112] @ 0x70 GPIO_InitStruct.Pull = GPIO_NOPULL; 800a448: 2300 movs r3, #0 800a44a: 677b str r3, [r7, #116] @ 0x74 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800a44c: 2303 movs r3, #3 800a44e: 67bb str r3, [r7, #120] @ 0x78 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 800a450: 230a movs r3, #10 800a452: 67fb str r3, [r7, #124] @ 0x7c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800a454: f107 036c add.w r3, r7, #108 @ 0x6c 800a458: 4619 mov r1, r3 800a45a: 4812 ldr r0, [pc, #72] @ (800a4a4 ) 800a45c: f7f7 fff8 bl 8002450 /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 800a460: 4b0f ldr r3, [pc, #60] @ (800a4a0 ) 800a462: 6b5b ldr r3, [r3, #52] @ 0x34 800a464: 4a0e ldr r2, [pc, #56] @ (800a4a0 ) 800a466: f043 0380 orr.w r3, r3, #128 @ 0x80 800a46a: 6353 str r3, [r2, #52] @ 0x34 800a46c: 2300 movs r3, #0 800a46e: 60bb str r3, [r7, #8] 800a470: 4b0b ldr r3, [pc, #44] @ (800a4a0 ) 800a472: 6c5b ldr r3, [r3, #68] @ 0x44 800a474: 4a0a ldr r2, [pc, #40] @ (800a4a0 ) 800a476: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800a47a: 6453 str r3, [r2, #68] @ 0x44 800a47c: 4b08 ldr r3, [pc, #32] @ (800a4a0 ) 800a47e: 6c5b ldr r3, [r3, #68] @ 0x44 800a480: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a484: 60bb str r3, [r7, #8] 800a486: 68bb ldr r3, [r7, #8] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); 800a488: 2200 movs r2, #0 800a48a: 2100 movs r1, #0 800a48c: 2043 movs r0, #67 @ 0x43 800a48e: f7f7 fba6 bl 8001bde HAL_NVIC_EnableIRQ(OTG_FS_IRQn); 800a492: 2043 movs r0, #67 @ 0x43 800a494: f7f7 fbbf bl 8001c16 /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 800a498: bf00 nop 800a49a: 3780 adds r7, #128 @ 0x80 800a49c: 46bd mov sp, r7 800a49e: bd80 pop {r7, pc} 800a4a0: 40023800 .word 0x40023800 800a4a4: 40020000 .word 0x40020000 0800a4a8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a4a8: b580 push {r7, lr} 800a4aa: b082 sub sp, #8 800a4ac: af00 add r7, sp, #0 800a4ae: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 800a4b0: 687b ldr r3, [r7, #4] 800a4b2: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0 800a4b6: 687b ldr r3, [r7, #4] 800a4b8: f203 439c addw r3, r3, #1180 @ 0x49c 800a4bc: 4619 mov r1, r3 800a4be: 4610 mov r0, r2 800a4c0: f7fe fbcb bl 8008c5a } 800a4c4: bf00 nop 800a4c6: 3708 adds r7, #8 800a4c8: 46bd mov sp, r7 800a4ca: bd80 pop {r7, pc} 0800a4cc : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a4cc: b580 push {r7, lr} 800a4ce: b082 sub sp, #8 800a4d0: af00 add r7, sp, #0 800a4d2: 6078 str r0, [r7, #4] 800a4d4: 460b mov r3, r1 800a4d6: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 800a4d8: 687b ldr r3, [r7, #4] 800a4da: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800a4de: 78fa ldrb r2, [r7, #3] 800a4e0: 6879 ldr r1, [r7, #4] 800a4e2: 4613 mov r3, r2 800a4e4: 00db lsls r3, r3, #3 800a4e6: 4413 add r3, r2 800a4e8: 009b lsls r3, r3, #2 800a4ea: 440b add r3, r1 800a4ec: f503 7318 add.w r3, r3, #608 @ 0x260 800a4f0: 681a ldr r2, [r3, #0] 800a4f2: 78fb ldrb r3, [r7, #3] 800a4f4: 4619 mov r1, r3 800a4f6: f7fe fc05 bl 8008d04 } 800a4fa: bf00 nop 800a4fc: 3708 adds r7, #8 800a4fe: 46bd mov sp, r7 800a500: bd80 pop {r7, pc} 0800a502 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a502: b580 push {r7, lr} 800a504: b082 sub sp, #8 800a506: af00 add r7, sp, #0 800a508: 6078 str r0, [r7, #4] 800a50a: 460b mov r3, r1 800a50c: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 800a50e: 687b ldr r3, [r7, #4] 800a510: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800a514: 78fa ldrb r2, [r7, #3] 800a516: 6879 ldr r1, [r7, #4] 800a518: 4613 mov r3, r2 800a51a: 00db lsls r3, r3, #3 800a51c: 4413 add r3, r2 800a51e: 009b lsls r3, r3, #2 800a520: 440b add r3, r1 800a522: 3320 adds r3, #32 800a524: 681a ldr r2, [r3, #0] 800a526: 78fb ldrb r3, [r7, #3] 800a528: 4619 mov r1, r3 800a52a: f7fe fca7 bl 8008e7c } 800a52e: bf00 nop 800a530: 3708 adds r7, #8 800a532: 46bd mov sp, r7 800a534: bd80 pop {r7, pc} 0800a536 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a536: b580 push {r7, lr} 800a538: b082 sub sp, #8 800a53a: af00 add r7, sp, #0 800a53c: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 800a53e: 687b ldr r3, [r7, #4] 800a540: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a544: 4618 mov r0, r3 800a546: f7fe fdeb bl 8009120 } 800a54a: bf00 nop 800a54c: 3708 adds r7, #8 800a54e: 46bd mov sp, r7 800a550: bd80 pop {r7, pc} 0800a552 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a552: b580 push {r7, lr} 800a554: b084 sub sp, #16 800a556: af00 add r7, sp, #0 800a558: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 800a55a: 2301 movs r3, #1 800a55c: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed == PCD_SPEED_HIGH) 800a55e: 687b ldr r3, [r7, #4] 800a560: 79db ldrb r3, [r3, #7] 800a562: 2b00 cmp r3, #0 800a564: d102 bne.n 800a56c { speed = USBD_SPEED_HIGH; 800a566: 2300 movs r3, #0 800a568: 73fb strb r3, [r7, #15] 800a56a: e008 b.n 800a57e } else if ( hpcd->Init.speed == PCD_SPEED_FULL) 800a56c: 687b ldr r3, [r7, #4] 800a56e: 79db ldrb r3, [r3, #7] 800a570: 2b02 cmp r3, #2 800a572: d102 bne.n 800a57a { speed = USBD_SPEED_FULL; 800a574: 2301 movs r3, #1 800a576: 73fb strb r3, [r7, #15] 800a578: e001 b.n 800a57e } else { Error_Handler(); 800a57a: f7f6 fbed bl 8000d58 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 800a57e: 687b ldr r3, [r7, #4] 800a580: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a584: 7bfa ldrb r2, [r7, #15] 800a586: 4611 mov r1, r2 800a588: 4618 mov r0, r3 800a58a: f7fe fd85 bl 8009098 /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 800a58e: 687b ldr r3, [r7, #4] 800a590: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a594: 4618 mov r0, r3 800a596: f7fe fd2c bl 8008ff2 } 800a59a: bf00 nop 800a59c: 3710 adds r7, #16 800a59e: 46bd mov sp, r7 800a5a0: bd80 pop {r7, pc} ... 0800a5a4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a5a4: b580 push {r7, lr} 800a5a6: b082 sub sp, #8 800a5a8: af00 add r7, sp, #0 800a5aa: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 800a5ac: 687b ldr r3, [r7, #4] 800a5ae: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a5b2: 4618 mov r0, r3 800a5b4: f7fe fd80 bl 80090b8 __HAL_PCD_GATE_PHYCLOCK(hpcd); 800a5b8: 687b ldr r3, [r7, #4] 800a5ba: 681b ldr r3, [r3, #0] 800a5bc: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a5c0: 681b ldr r3, [r3, #0] 800a5c2: 687a ldr r2, [r7, #4] 800a5c4: 6812 ldr r2, [r2, #0] 800a5c6: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a5ca: f043 0301 orr.w r3, r3, #1 800a5ce: 6013 str r3, [r2, #0] /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 800a5d0: 687b ldr r3, [r7, #4] 800a5d2: 7adb ldrb r3, [r3, #11] 800a5d4: 2b00 cmp r3, #0 800a5d6: d005 beq.n 800a5e4 { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a5d8: 4b04 ldr r3, [pc, #16] @ (800a5ec ) 800a5da: 691b ldr r3, [r3, #16] 800a5dc: 4a03 ldr r2, [pc, #12] @ (800a5ec ) 800a5de: f043 0306 orr.w r3, r3, #6 800a5e2: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 800a5e4: bf00 nop 800a5e6: 3708 adds r7, #8 800a5e8: 46bd mov sp, r7 800a5ea: bd80 pop {r7, pc} 800a5ec: e000ed00 .word 0xe000ed00 0800a5f0 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a5f0: b580 push {r7, lr} 800a5f2: b082 sub sp, #8 800a5f4: af00 add r7, sp, #0 800a5f6: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 800a5f8: 687b ldr r3, [r7, #4] 800a5fa: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a5fe: 4618 mov r0, r3 800a600: f7fe fd76 bl 80090f0 } 800a604: bf00 nop 800a606: 3708 adds r7, #8 800a608: 46bd mov sp, r7 800a60a: bd80 pop {r7, pc} 0800a60c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a60c: b580 push {r7, lr} 800a60e: b082 sub sp, #8 800a610: af00 add r7, sp, #0 800a612: 6078 str r0, [r7, #4] 800a614: 460b mov r3, r1 800a616: 70fb strb r3, [r7, #3] USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800a618: 687b ldr r3, [r7, #4] 800a61a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a61e: 78fa ldrb r2, [r7, #3] 800a620: 4611 mov r1, r2 800a622: 4618 mov r0, r3 800a624: f7fe fdce bl 80091c4 } 800a628: bf00 nop 800a62a: 3708 adds r7, #8 800a62c: 46bd mov sp, r7 800a62e: bd80 pop {r7, pc} 0800a630 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a630: b580 push {r7, lr} 800a632: b082 sub sp, #8 800a634: af00 add r7, sp, #0 800a636: 6078 str r0, [r7, #4] 800a638: 460b mov r3, r1 800a63a: 70fb strb r3, [r7, #3] USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800a63c: 687b ldr r3, [r7, #4] 800a63e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a642: 78fa ldrb r2, [r7, #3] 800a644: 4611 mov r1, r2 800a646: 4618 mov r0, r3 800a648: f7fe fd8a bl 8009160 } 800a64c: bf00 nop 800a64e: 3708 adds r7, #8 800a650: 46bd mov sp, r7 800a652: bd80 pop {r7, pc} 0800a654 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a654: b580 push {r7, lr} 800a656: b082 sub sp, #8 800a658: af00 add r7, sp, #0 800a65a: 6078 str r0, [r7, #4] USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); 800a65c: 687b ldr r3, [r7, #4] 800a65e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a662: 4618 mov r0, r3 800a664: f7fe fde0 bl 8009228 } 800a668: bf00 nop 800a66a: 3708 adds r7, #8 800a66c: 46bd mov sp, r7 800a66e: bd80 pop {r7, pc} 0800a670 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a670: b580 push {r7, lr} 800a672: b082 sub sp, #8 800a674: af00 add r7, sp, #0 800a676: 6078 str r0, [r7, #4] USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); 800a678: 687b ldr r3, [r7, #4] 800a67a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a67e: 4618 mov r0, r3 800a680: f7fe fddd bl 800923e } 800a684: bf00 nop 800a686: 3708 adds r7, #8 800a688: 46bd mov sp, r7 800a68a: bd80 pop {r7, pc} 0800a68c : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 800a68c: b580 push {r7, lr} 800a68e: b082 sub sp, #8 800a690: af00 add r7, sp, #0 800a692: 6078 str r0, [r7, #4] /* Init USB Ip. */ if (pdev->id == DEVICE_FS) { 800a694: 687b ldr r3, [r7, #4] 800a696: 781b ldrb r3, [r3, #0] 800a698: 2b00 cmp r3, #0 800a69a: d13c bne.n 800a716 /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; 800a69c: 4a20 ldr r2, [pc, #128] @ (800a720 ) 800a69e: 687b ldr r3, [r7, #4] 800a6a0: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0 pdev->pData = &hpcd_USB_OTG_FS; 800a6a4: 687b ldr r3, [r7, #4] 800a6a6: 4a1e ldr r2, [pc, #120] @ (800a720 ) 800a6a8: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8 hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 800a6ac: 4b1c ldr r3, [pc, #112] @ (800a720 ) 800a6ae: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 800a6b2: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 6; 800a6b4: 4b1a ldr r3, [pc, #104] @ (800a720 ) 800a6b6: 2206 movs r2, #6 800a6b8: 711a strb r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 800a6ba: 4b19 ldr r3, [pc, #100] @ (800a720 ) 800a6bc: 2202 movs r2, #2 800a6be: 71da strb r2, [r3, #7] hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; 800a6c0: 4b17 ldr r3, [pc, #92] @ (800a720 ) 800a6c2: 2200 movs r2, #0 800a6c4: 719a strb r2, [r3, #6] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 800a6c6: 4b16 ldr r3, [pc, #88] @ (800a720 ) 800a6c8: 2202 movs r2, #2 800a6ca: 725a strb r2, [r3, #9] hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; 800a6cc: 4b14 ldr r3, [pc, #80] @ (800a720 ) 800a6ce: 2200 movs r2, #0 800a6d0: 729a strb r2, [r3, #10] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 800a6d2: 4b13 ldr r3, [pc, #76] @ (800a720 ) 800a6d4: 2200 movs r2, #0 800a6d6: 72da strb r2, [r3, #11] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 800a6d8: 4b11 ldr r3, [pc, #68] @ (800a720 ) 800a6da: 2200 movs r2, #0 800a6dc: 731a strb r2, [r3, #12] hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; 800a6de: 4b10 ldr r3, [pc, #64] @ (800a720 ) 800a6e0: 2200 movs r2, #0 800a6e2: 739a strb r2, [r3, #14] hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 800a6e4: 4b0e ldr r3, [pc, #56] @ (800a720 ) 800a6e6: 2200 movs r2, #0 800a6e8: 73da strb r2, [r3, #15] if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 800a6ea: 480d ldr r0, [pc, #52] @ (800a720 ) 800a6ec: f7f8 f9ba bl 8002a64 800a6f0: 4603 mov r3, r0 800a6f2: 2b00 cmp r3, #0 800a6f4: d001 beq.n 800a6fa { Error_Handler( ); 800a6f6: f7f6 fb2f bl 8000d58 HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback); HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); 800a6fa: 2180 movs r1, #128 @ 0x80 800a6fc: 4808 ldr r0, [pc, #32] @ (800a720 ) 800a6fe: f7f9 fc02 bl 8003f06 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); 800a702: 2240 movs r2, #64 @ 0x40 800a704: 2100 movs r1, #0 800a706: 4806 ldr r0, [pc, #24] @ (800a720 ) 800a708: f7f9 fbb6 bl 8003e78 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); 800a70c: 2280 movs r2, #128 @ 0x80 800a70e: 2101 movs r1, #1 800a710: 4803 ldr r0, [pc, #12] @ (800a720 ) 800a712: f7f9 fbb1 bl 8003e78 } return USBD_OK; 800a716: 2300 movs r3, #0 } 800a718: 4618 mov r0, r3 800a71a: 3708 adds r7, #8 800a71c: 46bd mov sp, r7 800a71e: bd80 pop {r7, pc} 800a720: 20000c00 .word 0x20000c00 0800a724 : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 800a724: b580 push {r7, lr} 800a726: b084 sub sp, #16 800a728: af00 add r7, sp, #0 800a72a: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 800a72c: 2300 movs r3, #0 800a72e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a730: 2300 movs r3, #0 800a732: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 800a734: 687b ldr r3, [r7, #4] 800a736: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a73a: 4618 mov r0, r3 800a73c: f7f8 faa8 bl 8002c90 800a740: 4603 mov r3, r0 800a742: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a744: 7bfb ldrb r3, [r7, #15] 800a746: 4618 mov r0, r3 800a748: f000 f97e bl 800aa48 800a74c: 4603 mov r3, r0 800a74e: 73bb strb r3, [r7, #14] return usb_status; 800a750: 7bbb ldrb r3, [r7, #14] } 800a752: 4618 mov r0, r3 800a754: 3710 adds r7, #16 800a756: 46bd mov sp, r7 800a758: bd80 pop {r7, pc} 0800a75a : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 800a75a: b580 push {r7, lr} 800a75c: b084 sub sp, #16 800a75e: af00 add r7, sp, #0 800a760: 6078 str r0, [r7, #4] 800a762: 4608 mov r0, r1 800a764: 4611 mov r1, r2 800a766: 461a mov r2, r3 800a768: 4603 mov r3, r0 800a76a: 70fb strb r3, [r7, #3] 800a76c: 460b mov r3, r1 800a76e: 70bb strb r3, [r7, #2] 800a770: 4613 mov r3, r2 800a772: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 800a774: 2300 movs r3, #0 800a776: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a778: 2300 movs r3, #0 800a77a: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 800a77c: 687b ldr r3, [r7, #4] 800a77e: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a782: 78bb ldrb r3, [r7, #2] 800a784: 883a ldrh r2, [r7, #0] 800a786: 78f9 ldrb r1, [r7, #3] 800a788: f7f8 ffa9 bl 80036de 800a78c: 4603 mov r3, r0 800a78e: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a790: 7bfb ldrb r3, [r7, #15] 800a792: 4618 mov r0, r3 800a794: f000 f958 bl 800aa48 800a798: 4603 mov r3, r0 800a79a: 73bb strb r3, [r7, #14] return usb_status; 800a79c: 7bbb ldrb r3, [r7, #14] } 800a79e: 4618 mov r0, r3 800a7a0: 3710 adds r7, #16 800a7a2: 46bd mov sp, r7 800a7a4: bd80 pop {r7, pc} 0800a7a6 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a7a6: b580 push {r7, lr} 800a7a8: b084 sub sp, #16 800a7aa: af00 add r7, sp, #0 800a7ac: 6078 str r0, [r7, #4] 800a7ae: 460b mov r3, r1 800a7b0: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a7b2: 2300 movs r3, #0 800a7b4: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a7b6: 2300 movs r3, #0 800a7b8: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 800a7ba: 687b ldr r3, [r7, #4] 800a7bc: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a7c0: 78fa ldrb r2, [r7, #3] 800a7c2: 4611 mov r1, r2 800a7c4: 4618 mov r0, r3 800a7c6: f7f8 fff4 bl 80037b2 800a7ca: 4603 mov r3, r0 800a7cc: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a7ce: 7bfb ldrb r3, [r7, #15] 800a7d0: 4618 mov r0, r3 800a7d2: f000 f939 bl 800aa48 800a7d6: 4603 mov r3, r0 800a7d8: 73bb strb r3, [r7, #14] return usb_status; 800a7da: 7bbb ldrb r3, [r7, #14] } 800a7dc: 4618 mov r0, r3 800a7de: 3710 adds r7, #16 800a7e0: 46bd mov sp, r7 800a7e2: bd80 pop {r7, pc} 0800a7e4 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a7e4: b580 push {r7, lr} 800a7e6: b084 sub sp, #16 800a7e8: af00 add r7, sp, #0 800a7ea: 6078 str r0, [r7, #4] 800a7ec: 460b mov r3, r1 800a7ee: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a7f0: 2300 movs r3, #0 800a7f2: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a7f4: 2300 movs r3, #0 800a7f6: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 800a7f8: 687b ldr r3, [r7, #4] 800a7fa: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a7fe: 78fa ldrb r2, [r7, #3] 800a800: 4611 mov r1, r2 800a802: 4618 mov r0, r3 800a804: f7f9 f894 bl 8003930 800a808: 4603 mov r3, r0 800a80a: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a80c: 7bfb ldrb r3, [r7, #15] 800a80e: 4618 mov r0, r3 800a810: f000 f91a bl 800aa48 800a814: 4603 mov r3, r0 800a816: 73bb strb r3, [r7, #14] return usb_status; 800a818: 7bbb ldrb r3, [r7, #14] } 800a81a: 4618 mov r0, r3 800a81c: 3710 adds r7, #16 800a81e: 46bd mov sp, r7 800a820: bd80 pop {r7, pc} 0800a822 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a822: b580 push {r7, lr} 800a824: b084 sub sp, #16 800a826: af00 add r7, sp, #0 800a828: 6078 str r0, [r7, #4] 800a82a: 460b mov r3, r1 800a82c: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a82e: 2300 movs r3, #0 800a830: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a832: 2300 movs r3, #0 800a834: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 800a836: 687b ldr r3, [r7, #4] 800a838: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a83c: 78fa ldrb r2, [r7, #3] 800a83e: 4611 mov r1, r2 800a840: 4618 mov r0, r3 800a842: f7f9 f8d8 bl 80039f6 800a846: 4603 mov r3, r0 800a848: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a84a: 7bfb ldrb r3, [r7, #15] 800a84c: 4618 mov r0, r3 800a84e: f000 f8fb bl 800aa48 800a852: 4603 mov r3, r0 800a854: 73bb strb r3, [r7, #14] return usb_status; 800a856: 7bbb ldrb r3, [r7, #14] } 800a858: 4618 mov r0, r3 800a85a: 3710 adds r7, #16 800a85c: 46bd mov sp, r7 800a85e: bd80 pop {r7, pc} 0800a860 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a860: b480 push {r7} 800a862: b085 sub sp, #20 800a864: af00 add r7, sp, #0 800a866: 6078 str r0, [r7, #4] 800a868: 460b mov r3, r1 800a86a: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 800a86c: 687b ldr r3, [r7, #4] 800a86e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a872: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 800a874: f997 3003 ldrsb.w r3, [r7, #3] 800a878: 2b00 cmp r3, #0 800a87a: da0b bge.n 800a894 { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 800a87c: 78fb ldrb r3, [r7, #3] 800a87e: f003 027f and.w r2, r3, #127 @ 0x7f 800a882: 68f9 ldr r1, [r7, #12] 800a884: 4613 mov r3, r2 800a886: 00db lsls r3, r3, #3 800a888: 4413 add r3, r2 800a88a: 009b lsls r3, r3, #2 800a88c: 440b add r3, r1 800a88e: 3316 adds r3, #22 800a890: 781b ldrb r3, [r3, #0] 800a892: e00b b.n 800a8ac } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 800a894: 78fb ldrb r3, [r7, #3] 800a896: f003 027f and.w r2, r3, #127 @ 0x7f 800a89a: 68f9 ldr r1, [r7, #12] 800a89c: 4613 mov r3, r2 800a89e: 00db lsls r3, r3, #3 800a8a0: 4413 add r3, r2 800a8a2: 009b lsls r3, r3, #2 800a8a4: 440b add r3, r1 800a8a6: f203 2356 addw r3, r3, #598 @ 0x256 800a8aa: 781b ldrb r3, [r3, #0] } } 800a8ac: 4618 mov r0, r3 800a8ae: 3714 adds r7, #20 800a8b0: 46bd mov sp, r7 800a8b2: f85d 7b04 ldr.w r7, [sp], #4 800a8b6: 4770 bx lr 0800a8b8 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 800a8b8: b580 push {r7, lr} 800a8ba: b084 sub sp, #16 800a8bc: af00 add r7, sp, #0 800a8be: 6078 str r0, [r7, #4] 800a8c0: 460b mov r3, r1 800a8c2: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a8c4: 2300 movs r3, #0 800a8c6: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a8c8: 2300 movs r3, #0 800a8ca: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 800a8cc: 687b ldr r3, [r7, #4] 800a8ce: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a8d2: 78fa ldrb r2, [r7, #3] 800a8d4: 4611 mov r1, r2 800a8d6: 4618 mov r0, r3 800a8d8: f7f8 fedd bl 8003696 800a8dc: 4603 mov r3, r0 800a8de: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a8e0: 7bfb ldrb r3, [r7, #15] 800a8e2: 4618 mov r0, r3 800a8e4: f000 f8b0 bl 800aa48 800a8e8: 4603 mov r3, r0 800a8ea: 73bb strb r3, [r7, #14] return usb_status; 800a8ec: 7bbb ldrb r3, [r7, #14] } 800a8ee: 4618 mov r0, r3 800a8f0: 3710 adds r7, #16 800a8f2: 46bd mov sp, r7 800a8f4: bd80 pop {r7, pc} 0800a8f6 : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800a8f6: b580 push {r7, lr} 800a8f8: b086 sub sp, #24 800a8fa: af00 add r7, sp, #0 800a8fc: 60f8 str r0, [r7, #12] 800a8fe: 607a str r2, [r7, #4] 800a900: 603b str r3, [r7, #0] 800a902: 460b mov r3, r1 800a904: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800a906: 2300 movs r3, #0 800a908: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800a90a: 2300 movs r3, #0 800a90c: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 800a90e: 68fb ldr r3, [r7, #12] 800a910: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a914: 7af9 ldrb r1, [r7, #11] 800a916: 683b ldr r3, [r7, #0] 800a918: 687a ldr r2, [r7, #4] 800a91a: f7f8 ffcf bl 80038bc 800a91e: 4603 mov r3, r0 800a920: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800a922: 7dfb ldrb r3, [r7, #23] 800a924: 4618 mov r0, r3 800a926: f000 f88f bl 800aa48 800a92a: 4603 mov r3, r0 800a92c: 75bb strb r3, [r7, #22] return usb_status; 800a92e: 7dbb ldrb r3, [r7, #22] } 800a930: 4618 mov r0, r3 800a932: 3718 adds r7, #24 800a934: 46bd mov sp, r7 800a936: bd80 pop {r7, pc} 0800a938 : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800a938: b580 push {r7, lr} 800a93a: b086 sub sp, #24 800a93c: af00 add r7, sp, #0 800a93e: 60f8 str r0, [r7, #12] 800a940: 607a str r2, [r7, #4] 800a942: 603b str r3, [r7, #0] 800a944: 460b mov r3, r1 800a946: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800a948: 2300 movs r3, #0 800a94a: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800a94c: 2300 movs r3, #0 800a94e: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 800a950: 68fb ldr r3, [r7, #12] 800a952: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a956: 7af9 ldrb r1, [r7, #11] 800a958: 683b ldr r3, [r7, #0] 800a95a: 687a ldr r2, [r7, #4] 800a95c: f7f8 ff73 bl 8003846 800a960: 4603 mov r3, r0 800a962: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800a964: 7dfb ldrb r3, [r7, #23] 800a966: 4618 mov r0, r3 800a968: f000 f86e bl 800aa48 800a96c: 4603 mov r3, r0 800a96e: 75bb strb r3, [r7, #22] return usb_status; 800a970: 7dbb ldrb r3, [r7, #22] } 800a972: 4618 mov r0, r3 800a974: 3718 adds r7, #24 800a976: 46bd mov sp, r7 800a978: bd80 pop {r7, pc} ... 0800a97c : * @param hpcd: PCD handle * @param msg: LPM message * @retval None */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { 800a97c: b580 push {r7, lr} 800a97e: b082 sub sp, #8 800a980: af00 add r7, sp, #0 800a982: 6078 str r0, [r7, #4] 800a984: 460b mov r3, r1 800a986: 70fb strb r3, [r7, #3] switch (msg) 800a988: 78fb ldrb r3, [r7, #3] 800a98a: 2b00 cmp r3, #0 800a98c: d002 beq.n 800a994 800a98e: 2b01 cmp r3, #1 800a990: d01f beq.n 800a9d2 /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } } 800a992: e03b b.n 800aa0c if (hpcd->Init.low_power_enable) 800a994: 687b ldr r3, [r7, #4] 800a996: 7adb ldrb r3, [r3, #11] 800a998: 2b00 cmp r3, #0 800a99a: d007 beq.n 800a9ac SystemClock_Config(); 800a99c: f7f5 ffe2 bl 8000964 SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a9a0: 4b1c ldr r3, [pc, #112] @ (800aa14 ) 800a9a2: 691b ldr r3, [r3, #16] 800a9a4: 4a1b ldr r2, [pc, #108] @ (800aa14 ) 800a9a6: f023 0306 bic.w r3, r3, #6 800a9aa: 6113 str r3, [r2, #16] __HAL_PCD_UNGATE_PHYCLOCK(hpcd); 800a9ac: 687b ldr r3, [r7, #4] 800a9ae: 681b ldr r3, [r3, #0] 800a9b0: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a9b4: 681b ldr r3, [r3, #0] 800a9b6: 687a ldr r2, [r7, #4] 800a9b8: 6812 ldr r2, [r2, #0] 800a9ba: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a9be: f023 0301 bic.w r3, r3, #1 800a9c2: 6013 str r3, [r2, #0] USBD_LL_Resume(hpcd->pData); 800a9c4: 687b ldr r3, [r7, #4] 800a9c6: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a9ca: 4618 mov r0, r3 800a9cc: f7fe fb90 bl 80090f0 break; 800a9d0: e01c b.n 800aa0c __HAL_PCD_GATE_PHYCLOCK(hpcd); 800a9d2: 687b ldr r3, [r7, #4] 800a9d4: 681b ldr r3, [r3, #0] 800a9d6: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a9da: 681b ldr r3, [r3, #0] 800a9dc: 687a ldr r2, [r7, #4] 800a9de: 6812 ldr r2, [r2, #0] 800a9e0: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a9e4: f043 0301 orr.w r3, r3, #1 800a9e8: 6013 str r3, [r2, #0] USBD_LL_Suspend(hpcd->pData); 800a9ea: 687b ldr r3, [r7, #4] 800a9ec: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a9f0: 4618 mov r0, r3 800a9f2: f7fe fb61 bl 80090b8 if (hpcd->Init.low_power_enable) 800a9f6: 687b ldr r3, [r7, #4] 800a9f8: 7adb ldrb r3, [r3, #11] 800a9fa: 2b00 cmp r3, #0 800a9fc: d005 beq.n 800aa0a SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a9fe: 4b05 ldr r3, [pc, #20] @ (800aa14 ) 800aa00: 691b ldr r3, [r3, #16] 800aa02: 4a04 ldr r2, [pc, #16] @ (800aa14 ) 800aa04: f043 0306 orr.w r3, r3, #6 800aa08: 6113 str r3, [r2, #16] break; 800aa0a: bf00 nop } 800aa0c: bf00 nop 800aa0e: 3708 adds r7, #8 800aa10: 46bd mov sp, r7 800aa12: bd80 pop {r7, pc} 800aa14: e000ed00 .word 0xe000ed00 0800aa18 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 800aa18: b480 push {r7} 800aa1a: b083 sub sp, #12 800aa1c: af00 add r7, sp, #0 800aa1e: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 800aa20: 4b03 ldr r3, [pc, #12] @ (800aa30 ) } 800aa22: 4618 mov r0, r3 800aa24: 370c adds r7, #12 800aa26: 46bd mov sp, r7 800aa28: f85d 7b04 ldr.w r7, [sp], #4 800aa2c: 4770 bx lr 800aa2e: bf00 nop 800aa30: 200010e4 .word 0x200010e4 0800aa34 : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 800aa34: b480 push {r7} 800aa36: b083 sub sp, #12 800aa38: af00 add r7, sp, #0 800aa3a: 6078 str r0, [r7, #4] } 800aa3c: bf00 nop 800aa3e: 370c adds r7, #12 800aa40: 46bd mov sp, r7 800aa42: f85d 7b04 ldr.w r7, [sp], #4 800aa46: 4770 bx lr 0800aa48 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 800aa48: b480 push {r7} 800aa4a: b085 sub sp, #20 800aa4c: af00 add r7, sp, #0 800aa4e: 4603 mov r3, r0 800aa50: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 800aa52: 2300 movs r3, #0 800aa54: 73fb strb r3, [r7, #15] switch (hal_status) 800aa56: 79fb ldrb r3, [r7, #7] 800aa58: 2b03 cmp r3, #3 800aa5a: d817 bhi.n 800aa8c 800aa5c: a201 add r2, pc, #4 @ (adr r2, 800aa64 ) 800aa5e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800aa62: bf00 nop 800aa64: 0800aa75 .word 0x0800aa75 800aa68: 0800aa7b .word 0x0800aa7b 800aa6c: 0800aa81 .word 0x0800aa81 800aa70: 0800aa87 .word 0x0800aa87 { case HAL_OK : usb_status = USBD_OK; 800aa74: 2300 movs r3, #0 800aa76: 73fb strb r3, [r7, #15] break; 800aa78: e00b b.n 800aa92 case HAL_ERROR : usb_status = USBD_FAIL; 800aa7a: 2303 movs r3, #3 800aa7c: 73fb strb r3, [r7, #15] break; 800aa7e: e008 b.n 800aa92 case HAL_BUSY : usb_status = USBD_BUSY; 800aa80: 2301 movs r3, #1 800aa82: 73fb strb r3, [r7, #15] break; 800aa84: e005 b.n 800aa92 case HAL_TIMEOUT : usb_status = USBD_FAIL; 800aa86: 2303 movs r3, #3 800aa88: 73fb strb r3, [r7, #15] break; 800aa8a: e002 b.n 800aa92 default : usb_status = USBD_FAIL; 800aa8c: 2303 movs r3, #3 800aa8e: 73fb strb r3, [r7, #15] break; 800aa90: bf00 nop } return usb_status; 800aa92: 7bfb ldrb r3, [r7, #15] } 800aa94: 4618 mov r0, r3 800aa96: 3714 adds r7, #20 800aa98: 46bd mov sp, r7 800aa9a: f85d 7b04 ldr.w r7, [sp], #4 800aa9e: 4770 bx lr 0800aaa0 : 800aaa0: 4402 add r2, r0 800aaa2: 4603 mov r3, r0 800aaa4: 4293 cmp r3, r2 800aaa6: d100 bne.n 800aaaa 800aaa8: 4770 bx lr 800aaaa: f803 1b01 strb.w r1, [r3], #1 800aaae: e7f9 b.n 800aaa4 0800aab0 <__libc_init_array>: 800aab0: b570 push {r4, r5, r6, lr} 800aab2: 4d0d ldr r5, [pc, #52] @ (800aae8 <__libc_init_array+0x38>) 800aab4: 4c0d ldr r4, [pc, #52] @ (800aaec <__libc_init_array+0x3c>) 800aab6: 1b64 subs r4, r4, r5 800aab8: 10a4 asrs r4, r4, #2 800aaba: 2600 movs r6, #0 800aabc: 42a6 cmp r6, r4 800aabe: d109 bne.n 800aad4 <__libc_init_array+0x24> 800aac0: 4d0b ldr r5, [pc, #44] @ (800aaf0 <__libc_init_array+0x40>) 800aac2: 4c0c ldr r4, [pc, #48] @ (800aaf4 <__libc_init_array+0x44>) 800aac4: f000 f826 bl 800ab14 <_init> 800aac8: 1b64 subs r4, r4, r5 800aaca: 10a4 asrs r4, r4, #2 800aacc: 2600 movs r6, #0 800aace: 42a6 cmp r6, r4 800aad0: d105 bne.n 800aade <__libc_init_array+0x2e> 800aad2: bd70 pop {r4, r5, r6, pc} 800aad4: f855 3b04 ldr.w r3, [r5], #4 800aad8: 4798 blx r3 800aada: 3601 adds r6, #1 800aadc: e7ee b.n 800aabc <__libc_init_array+0xc> 800aade: f855 3b04 ldr.w r3, [r5], #4 800aae2: 4798 blx r3 800aae4: 3601 adds r6, #1 800aae6: e7f2 b.n 800aace <__libc_init_array+0x1e> 800aae8: 0800ab90 .word 0x0800ab90 800aaec: 0800ab90 .word 0x0800ab90 800aaf0: 0800ab90 .word 0x0800ab90 800aaf4: 0800ab94 .word 0x0800ab94 0800aaf8 : 800aaf8: 440a add r2, r1 800aafa: 4291 cmp r1, r2 800aafc: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 800ab00: d100 bne.n 800ab04 800ab02: 4770 bx lr 800ab04: b510 push {r4, lr} 800ab06: f811 4b01 ldrb.w r4, [r1], #1 800ab0a: f803 4f01 strb.w r4, [r3, #1]! 800ab0e: 4291 cmp r1, r2 800ab10: d1f9 bne.n 800ab06 800ab12: bd10 pop {r4, pc} 0800ab14 <_init>: 800ab14: b5f8 push {r3, r4, r5, r6, r7, lr} 800ab16: bf00 nop 800ab18: bcf8 pop {r3, r4, r5, r6, r7} 800ab1a: bc08 pop {r3} 800ab1c: 469e mov lr, r3 800ab1e: 4770 bx lr 0800ab20 <_fini>: 800ab20: b5f8 push {r3, r4, r5, r6, r7, lr} 800ab22: bf00 nop 800ab24: bcf8 pop {r3, r4, r5, r6, r7} 800ab26: bc08 pop {r3} 800ab28: 469e mov lr, r3 800ab2a: 4770 bx lr