modularkbd.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001c4 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000aa2c 080001c4 080001c4 000011c4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000005c 0800abf0 0800abf0 0000bbf0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800ac4c 0800ac4c 0000c1a0 2**0 CONTENTS, READONLY 4 .ARM 00000008 0800ac4c 0800ac4c 0000bc4c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800ac54 0800ac54 0000c1a0 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800ac54 0800ac54 0000bc54 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 0800ac58 0800ac58 0000bc58 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 000001a0 20000000 0800ac5c 0000c000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000f58 200001a0 0800adfc 0000c1a0 2**2 ALLOC 10 ._user_heap_stack 00000600 200010f8 0800adfc 0000d0f8 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000c1a0 2**0 CONTENTS, READONLY 12 .debug_info 0001b2e3 00000000 00000000 0000c1d0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00004059 00000000 00000000 000274b3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001780 00000000 00000000 0002b510 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 0000123f 00000000 00000000 0002cc90 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00026060 00000000 00000000 0002decf 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001e684 00000000 00000000 00053f2f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000d7ebb 00000000 00000000 000725b3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0014a46e 2**0 CONTENTS, READONLY 20 .debug_frame 000062c0 00000000 00000000 0014a4b4 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000062 00000000 00000000 00150774 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001c4 <__do_global_dtors_aux>: 80001c4: b510 push {r4, lr} 80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>) 80001c8: 7823 ldrb r3, [r4, #0] 80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16> 80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>) 80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12> 80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>) 80001d2: f3af 8000 nop.w 80001d6: 2301 movs r3, #1 80001d8: 7023 strb r3, [r4, #0] 80001da: bd10 pop {r4, pc} 80001dc: 200001a0 .word 0x200001a0 80001e0: 00000000 .word 0x00000000 80001e4: 0800abd8 .word 0x0800abd8 080001e8 : 80001e8: b508 push {r3, lr} 80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 ) 80001ec: b11b cbz r3, 80001f6 80001ee: 4903 ldr r1, [pc, #12] @ (80001fc ) 80001f0: 4803 ldr r0, [pc, #12] @ (8000200 ) 80001f2: f3af 8000 nop.w 80001f6: bd08 pop {r3, pc} 80001f8: 00000000 .word 0x00000000 80001fc: 200001a4 .word 0x200001a4 8000200: 0800abd8 .word 0x0800abd8 08000204 <__aeabi_uldivmod>: 8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18> 8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18> 8000208: 2900 cmp r1, #0 800020a: bf08 it eq 800020c: 2800 cmpeq r0, #0 800020e: bf1c itt ne 8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000218: f000 b988 b.w 800052c <__aeabi_idiv0> 800021c: f1ad 0c08 sub.w ip, sp, #8 8000220: e96d ce04 strd ip, lr, [sp, #-16]! 8000224: f000 f806 bl 8000234 <__udivmoddi4> 8000228: f8dd e004 ldr.w lr, [sp, #4] 800022c: e9dd 2302 ldrd r2, r3, [sp, #8] 8000230: b004 add sp, #16 8000232: 4770 bx lr 08000234 <__udivmoddi4>: 8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000238: 9d08 ldr r5, [sp, #32] 800023a: 468e mov lr, r1 800023c: 4604 mov r4, r0 800023e: 4688 mov r8, r1 8000240: 2b00 cmp r3, #0 8000242: d14a bne.n 80002da <__udivmoddi4+0xa6> 8000244: 428a cmp r2, r1 8000246: 4617 mov r7, r2 8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc> 800024a: fab2 f682 clz r6, r2 800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30> 8000250: f1c6 0320 rsb r3, r6, #32 8000254: fa01 f806 lsl.w r8, r1, r6 8000258: fa20 f303 lsr.w r3, r0, r3 800025c: 40b7 lsls r7, r6 800025e: ea43 0808 orr.w r8, r3, r8 8000262: 40b4 lsls r4, r6 8000264: ea4f 4e17 mov.w lr, r7, lsr #16 8000268: fa1f fc87 uxth.w ip, r7 800026c: fbb8 f1fe udiv r1, r8, lr 8000270: 0c23 lsrs r3, r4, #16 8000272: fb0e 8811 mls r8, lr, r1, r8 8000276: ea43 4308 orr.w r3, r3, r8, lsl #16 800027a: fb01 f20c mul.w r2, r1, ip 800027e: 429a cmp r2, r3 8000280: d909 bls.n 8000296 <__udivmoddi4+0x62> 8000282: 18fb adds r3, r7, r3 8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c> 800028c: 429a cmp r2, r3 800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c> 8000292: 3902 subs r1, #2 8000294: 443b add r3, r7 8000296: 1a9a subs r2, r3, r2 8000298: b2a3 uxth r3, r4 800029a: fbb2 f0fe udiv r0, r2, lr 800029e: fb0e 2210 mls r2, lr, r0, r2 80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16 80002a6: fb00 fc0c mul.w ip, r0, ip 80002aa: 459c cmp ip, r3 80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e> 80002ae: 18fb adds r3, r7, r3 80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230> 80002b8: 459c cmp ip, r3 80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230> 80002be: 443b add r3, r7 80002c0: 3802 subs r0, #2 80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16 80002c6: eba3 030c sub.w r3, r3, ip 80002ca: 2100 movs r1, #0 80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2> 80002ce: 40f3 lsrs r3, r6 80002d0: 2200 movs r2, #0 80002d2: e9c5 3200 strd r3, r2, [r5] 80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002da: 428b cmp r3, r1 80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6> 80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0> 80002e0: e9c5 0100 strd r0, r1, [r5] 80002e4: 2100 movs r1, #0 80002e6: 4608 mov r0, r1 80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2> 80002ea: fab3 f183 clz r1, r3 80002ee: 2900 cmp r1, #0 80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c> 80002f2: 4573 cmp r3, lr 80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8> 80002f6: 4282 cmp r2, r0 80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2> 80002fc: 1a84 subs r4, r0, r2 80002fe: eb6e 0203 sbc.w r2, lr, r3 8000302: 2001 movs r0, #1 8000304: 4690 mov r8, r2 8000306: 2d00 cmp r5, #0 8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2> 800030a: e9c5 4800 strd r4, r8, [r5] 800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2> 8000310: 2a00 cmp r2, #0 8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202> 8000316: fab2 f682 clz r6, r2 800031a: 2e00 cmp r6, #0 800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234> 8000320: 1a8a subs r2, r1, r2 8000322: 0c03 lsrs r3, r0, #16 8000324: ea4f 4e17 mov.w lr, r7, lsr #16 8000328: b280 uxth r0, r0 800032a: b2bc uxth r4, r7 800032c: 2101 movs r1, #1 800032e: fbb2 fcfe udiv ip, r2, lr 8000332: fb0e 221c mls r2, lr, ip, r2 8000336: ea43 4302 orr.w r3, r3, r2, lsl #16 800033a: fb04 f20c mul.w r2, r4, ip 800033e: 429a cmp r2, r3 8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e> 8000342: 18fb adds r3, r7, r3 8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c> 800034a: 429a cmp r2, r3 800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc> 8000350: 46c4 mov ip, r8 8000352: 1a9b subs r3, r3, r2 8000354: fbb3 f2fe udiv r2, r3, lr 8000358: fb0e 3312 mls r3, lr, r2, r3 800035c: ea40 4303 orr.w r3, r0, r3, lsl #16 8000360: fb02 f404 mul.w r4, r2, r4 8000364: 429c cmp r4, r3 8000366: d907 bls.n 8000378 <__udivmoddi4+0x144> 8000368: 18fb adds r3, r7, r3 800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142> 8000370: 429c cmp r4, r3 8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6> 8000376: 4602 mov r2, r0 8000378: 1b1b subs r3, r3, r4 800037a: ea42 400c orr.w r0, r2, ip, lsl #16 800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98> 8000380: f1c1 0620 rsb r6, r1, #32 8000384: 408b lsls r3, r1 8000386: fa22 f706 lsr.w r7, r2, r6 800038a: 431f orrs r7, r3 800038c: fa0e f401 lsl.w r4, lr, r1 8000390: fa20 f306 lsr.w r3, r0, r6 8000394: fa2e fe06 lsr.w lr, lr, r6 8000398: ea4f 4917 mov.w r9, r7, lsr #16 800039c: 4323 orrs r3, r4 800039e: fa00 f801 lsl.w r8, r0, r1 80003a2: fa1f fc87 uxth.w ip, r7 80003a6: fbbe f0f9 udiv r0, lr, r9 80003aa: 0c1c lsrs r4, r3, #16 80003ac: fb09 ee10 mls lr, r9, r0, lr 80003b0: ea44 440e orr.w r4, r4, lr, lsl #16 80003b4: fb00 fe0c mul.w lr, r0, ip 80003b8: 45a6 cmp lr, r4 80003ba: fa02 f201 lsl.w r2, r2, r1 80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0> 80003c0: 193c adds r4, r7, r4 80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce> 80003ca: 45a6 cmp lr, r4 80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce> 80003d0: 3802 subs r0, #2 80003d2: 443c add r4, r7 80003d4: eba4 040e sub.w r4, r4, lr 80003d8: fa1f fe83 uxth.w lr, r3 80003dc: fbb4 f3f9 udiv r3, r4, r9 80003e0: fb09 4413 mls r4, r9, r3, r4 80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003e8: fb03 fc0c mul.w ip, r3, ip 80003ec: 45a4 cmp ip, r4 80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce> 80003f0: 193c adds r4, r7, r4 80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca> 80003fa: 45a4 cmp ip, r4 80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca> 80003fe: 3b02 subs r3, #2 8000400: 443c add r4, r7 8000402: ea43 4000 orr.w r0, r3, r0, lsl #16 8000406: eba4 040c sub.w r4, r4, ip 800040a: fba0 ec02 umull lr, ip, r0, r2 800040e: 4564 cmp r4, ip 8000410: 4673 mov r3, lr 8000412: 46e1 mov r9, ip 8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8> 8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4> 8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe> 800041a: ebb8 0203 subs.w r2, r8, r3 800041e: eb64 0409 sbc.w r4, r4, r9 8000422: fa04 f606 lsl.w r6, r4, r6 8000426: fa22 f301 lsr.w r3, r2, r1 800042a: 431e orrs r6, r3 800042c: 40cc lsrs r4, r1 800042e: e9c5 6400 strd r6, r4, [r5] 8000432: 2100 movs r1, #0 8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2> 8000436: fbb1 fcf2 udiv ip, r1, r2 800043a: 0c01 lsrs r1, r0, #16 800043c: ea41 410e orr.w r1, r1, lr, lsl #16 8000440: b280 uxth r0, r0 8000442: ea40 4201 orr.w r2, r0, r1, lsl #16 8000446: 463b mov r3, r7 8000448: 4638 mov r0, r7 800044a: 463c mov r4, r7 800044c: 46b8 mov r8, r7 800044e: 46be mov lr, r7 8000450: 2620 movs r6, #32 8000452: fbb1 f1f7 udiv r1, r1, r7 8000456: eba2 0208 sub.w r2, r2, r8 800045a: ea41 410c orr.w r1, r1, ip, lsl #16 800045e: e766 b.n 800032e <__udivmoddi4+0xfa> 8000460: 4601 mov r1, r0 8000462: e718 b.n 8000296 <__udivmoddi4+0x62> 8000464: 4610 mov r0, r2 8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e> 8000468: f1c6 0220 rsb r2, r6, #32 800046c: fa2e f302 lsr.w r3, lr, r2 8000470: 40b7 lsls r7, r6 8000472: 40b1 lsls r1, r6 8000474: fa20 f202 lsr.w r2, r0, r2 8000478: ea4f 4e17 mov.w lr, r7, lsr #16 800047c: 430a orrs r2, r1 800047e: fbb3 f8fe udiv r8, r3, lr 8000482: b2bc uxth r4, r7 8000484: fb0e 3318 mls r3, lr, r8, r3 8000488: 0c11 lsrs r1, r2, #16 800048a: ea41 4103 orr.w r1, r1, r3, lsl #16 800048e: fb08 f904 mul.w r9, r8, r4 8000492: 40b0 lsls r0, r6 8000494: 4589 cmp r9, r1 8000496: ea4f 4310 mov.w r3, r0, lsr #16 800049a: b280 uxth r0, r0 800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8> 800049e: 1879 adds r1, r7, r1 80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276> 80004a6: 4589 cmp r9, r1 80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6> 80004aa: eba1 0109 sub.w r1, r1, r9 80004ae: fbb1 f9fe udiv r9, r1, lr 80004b2: fb09 f804 mul.w r8, r9, r4 80004b6: fb0e 1119 mls r1, lr, r9, r1 80004ba: b292 uxth r2, r2 80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16 80004c0: 4542 cmp r2, r8 80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4> 80004c4: 18ba adds r2, r7, r2 80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222> 80004cc: 4542 cmp r2, r8 80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222> 80004d0: f1a9 0102 sub.w r1, r9, #2 80004d4: 443a add r2, r7 80004d6: e7be b.n 8000456 <__udivmoddi4+0x222> 80004d8: 45f0 cmp r8, lr 80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4> 80004dc: ebbe 0302 subs.w r3, lr, r2 80004e0: eb6c 0c07 sbc.w ip, ip, r7 80004e4: 3801 subs r0, #1 80004e6: 46e1 mov r9, ip 80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4> 80004ea: eba7 0909 sub.w r9, r7, r9 80004ee: 4449 add r1, r9 80004f0: f1a8 0c02 sub.w ip, r8, #2 80004f4: fbb1 f9fe udiv r9, r1, lr 80004f8: fb09 f804 mul.w r8, r9, r4 80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282> 80004fe: 4673 mov r3, lr 8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce> 8000502: 4650 mov r0, sl 8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0> 8000506: 4608 mov r0, r1 8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2> 800050a: 443b add r3, r7 800050c: 3a02 subs r2, #2 800050e: e733 b.n 8000378 <__udivmoddi4+0x144> 8000510: f1ac 0c02 sub.w ip, ip, #2 8000514: 443b add r3, r7 8000516: e71c b.n 8000352 <__udivmoddi4+0x11e> 8000518: 4649 mov r1, r9 800051a: e79c b.n 8000456 <__udivmoddi4+0x222> 800051c: eba1 0109 sub.w r1, r1, r9 8000520: 46c4 mov ip, r8 8000522: fbb1 f9fe udiv r9, r1, lr 8000526: fb09 f804 mul.w r8, r9, r4 800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282> 0800052c <__aeabi_idiv0>: 800052c: 4770 bx lr 800052e: bf00 nop 08000530 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 8000530: b580 push {r7, lr} 8000532: b082 sub sp, #8 8000534: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8000536: 2300 movs r3, #0 8000538: 607b str r3, [r7, #4] 800053a: 4b2f ldr r3, [pc, #188] @ (80005f8 ) 800053c: 6b1b ldr r3, [r3, #48] @ 0x30 800053e: 4a2e ldr r2, [pc, #184] @ (80005f8 ) 8000540: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000544: 6313 str r3, [r2, #48] @ 0x30 8000546: 4b2c ldr r3, [pc, #176] @ (80005f8 ) 8000548: 6b1b ldr r3, [r3, #48] @ 0x30 800054a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800054e: 607b str r3, [r7, #4] 8000550: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); 8000552: 2300 movs r3, #0 8000554: 603b str r3, [r7, #0] 8000556: 4b28 ldr r3, [pc, #160] @ (80005f8 ) 8000558: 6b1b ldr r3, [r3, #48] @ 0x30 800055a: 4a27 ldr r2, [pc, #156] @ (80005f8 ) 800055c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8000560: 6313 str r3, [r2, #48] @ 0x30 8000562: 4b25 ldr r3, [pc, #148] @ (80005f8 ) 8000564: 6b1b ldr r3, [r3, #48] @ 0x30 8000566: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800056a: 603b str r3, [r7, #0] 800056c: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); 800056e: 2200 movs r2, #0 8000570: 2100 movs r1, #0 8000572: 200b movs r0, #11 8000574: f001 fb8b bl 8001c8e HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8000578: 200b movs r0, #11 800057a: f001 fba4 bl 8001cc6 /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); 800057e: 2200 movs r2, #0 8000580: 2100 movs r1, #0 8000582: 200d movs r0, #13 8000584: f001 fb83 bl 8001c8e HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8000588: 200d movs r0, #13 800058a: f001 fb9c bl 8001cc6 /* DMA1_Stream4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0); 800058e: 2200 movs r2, #0 8000590: 2100 movs r1, #0 8000592: 200f movs r0, #15 8000594: f001 fb7b bl 8001c8e HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); 8000598: 200f movs r0, #15 800059a: f001 fb94 bl 8001cc6 /* DMA1_Stream5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); 800059e: 2200 movs r2, #0 80005a0: 2100 movs r1, #0 80005a2: 2010 movs r0, #16 80005a4: f001 fb73 bl 8001c8e HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); 80005a8: 2010 movs r0, #16 80005aa: f001 fb8c bl 8001cc6 /* DMA1_Stream6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0); 80005ae: 2200 movs r2, #0 80005b0: 2100 movs r1, #0 80005b2: 2011 movs r0, #17 80005b4: f001 fb6b bl 8001c8e HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); 80005b8: 2011 movs r0, #17 80005ba: f001 fb84 bl 8001cc6 /* DMA1_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0); 80005be: 2200 movs r2, #0 80005c0: 2100 movs r1, #0 80005c2: 202f movs r0, #47 @ 0x2f 80005c4: f001 fb63 bl 8001c8e HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); 80005c8: 202f movs r0, #47 @ 0x2f 80005ca: f001 fb7c bl 8001cc6 /* DMA2_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); 80005ce: 2200 movs r2, #0 80005d0: 2100 movs r1, #0 80005d2: 203a movs r0, #58 @ 0x3a 80005d4: f001 fb5b bl 8001c8e HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); 80005d8: 203a movs r0, #58 @ 0x3a 80005da: f001 fb74 bl 8001cc6 /* DMA2_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 80005de: 2200 movs r2, #0 80005e0: 2100 movs r1, #0 80005e2: 2046 movs r0, #70 @ 0x46 80005e4: f001 fb53 bl 8001c8e HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 80005e8: 2046 movs r0, #70 @ 0x46 80005ea: f001 fb6c bl 8001cc6 } 80005ee: bf00 nop 80005f0: 3708 adds r7, #8 80005f2: 46bd mov sp, r7 80005f4: bd80 pop {r7, pc} 80005f6: bf00 nop 80005f8: 40023800 .word 0x40023800 080005fc : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 80005fc: b580 push {r7, lr} 80005fe: b08a sub sp, #40 @ 0x28 8000600: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000602: f107 0314 add.w r3, r7, #20 8000606: 2200 movs r2, #0 8000608: 601a str r2, [r3, #0] 800060a: 605a str r2, [r3, #4] 800060c: 609a str r2, [r3, #8] 800060e: 60da str r2, [r3, #12] 8000610: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8000612: 2300 movs r3, #0 8000614: 613b str r3, [r7, #16] 8000616: 4b45 ldr r3, [pc, #276] @ (800072c ) 8000618: 6b1b ldr r3, [r3, #48] @ 0x30 800061a: 4a44 ldr r2, [pc, #272] @ (800072c ) 800061c: f043 0380 orr.w r3, r3, #128 @ 0x80 8000620: 6313 str r3, [r2, #48] @ 0x30 8000622: 4b42 ldr r3, [pc, #264] @ (800072c ) 8000624: 6b1b ldr r3, [r3, #48] @ 0x30 8000626: f003 0380 and.w r3, r3, #128 @ 0x80 800062a: 613b str r3, [r7, #16] 800062c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800062e: 2300 movs r3, #0 8000630: 60fb str r3, [r7, #12] 8000632: 4b3e ldr r3, [pc, #248] @ (800072c ) 8000634: 6b1b ldr r3, [r3, #48] @ 0x30 8000636: 4a3d ldr r2, [pc, #244] @ (800072c ) 8000638: f043 0301 orr.w r3, r3, #1 800063c: 6313 str r3, [r2, #48] @ 0x30 800063e: 4b3b ldr r3, [pc, #236] @ (800072c ) 8000640: 6b1b ldr r3, [r3, #48] @ 0x30 8000642: f003 0301 and.w r3, r3, #1 8000646: 60fb str r3, [r7, #12] 8000648: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); 800064a: 2300 movs r3, #0 800064c: 60bb str r3, [r7, #8] 800064e: 4b37 ldr r3, [pc, #220] @ (800072c ) 8000650: 6b1b ldr r3, [r3, #48] @ 0x30 8000652: 4a36 ldr r2, [pc, #216] @ (800072c ) 8000654: f043 0304 orr.w r3, r3, #4 8000658: 6313 str r3, [r2, #48] @ 0x30 800065a: 4b34 ldr r3, [pc, #208] @ (800072c ) 800065c: 6b1b ldr r3, [r3, #48] @ 0x30 800065e: f003 0304 and.w r3, r3, #4 8000662: 60bb str r3, [r7, #8] 8000664: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000666: 2300 movs r3, #0 8000668: 607b str r3, [r7, #4] 800066a: 4b30 ldr r3, [pc, #192] @ (800072c ) 800066c: 6b1b ldr r3, [r3, #48] @ 0x30 800066e: 4a2f ldr r2, [pc, #188] @ (800072c ) 8000670: f043 0302 orr.w r3, r3, #2 8000674: 6313 str r3, [r2, #48] @ 0x30 8000676: 4b2d ldr r3, [pc, #180] @ (800072c ) 8000678: 6b1b ldr r3, [r3, #48] @ 0x30 800067a: f003 0302 and.w r3, r3, #2 800067e: 607b str r3, [r7, #4] 8000680: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000682: 2300 movs r3, #0 8000684: 603b str r3, [r7, #0] 8000686: 4b29 ldr r3, [pc, #164] @ (800072c ) 8000688: 6b1b ldr r3, [r3, #48] @ 0x30 800068a: 4a28 ldr r2, [pc, #160] @ (800072c ) 800068c: f043 0308 orr.w r3, r3, #8 8000690: 6313 str r3, [r2, #48] @ 0x30 8000692: 4b26 ldr r3, [pc, #152] @ (800072c ) 8000694: 6b1b ldr r3, [r3, #48] @ 0x30 8000696: f003 0308 and.w r3, r3, #8 800069a: 603b str r3, [r7, #0] 800069c: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET); 800069e: 2200 movs r2, #0 80006a0: f44f 7170 mov.w r1, #960 @ 0x3c0 80006a4: 4822 ldr r0, [pc, #136] @ (8000730 ) 80006a6: f002 f8d7 bl 8002858 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); 80006aa: 2200 movs r2, #0 80006ac: f44f 7180 mov.w r1, #256 @ 0x100 80006b0: 4820 ldr r0, [pc, #128] @ (8000734 ) 80006b2: f002 f8d1 bl 8002858 /*Configure GPIO pins : PC4 PC5 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80006b6: 2330 movs r3, #48 @ 0x30 80006b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006ba: 2300 movs r3, #0 80006bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006be: 2302 movs r3, #2 80006c0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006c2: f107 0314 add.w r3, r7, #20 80006c6: 4619 mov r1, r3 80006c8: 4819 ldr r0, [pc, #100] @ (8000730 ) 80006ca: f001 ff19 bl 8002500 /*Configure GPIO pins : PB0 PB1 PB2 PB10 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10; 80006ce: f240 4307 movw r3, #1031 @ 0x407 80006d2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006d4: 2300 movs r3, #0 80006d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006d8: 2302 movs r3, #2 80006da: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80006dc: f107 0314 add.w r3, r7, #20 80006e0: 4619 mov r1, r3 80006e2: 4815 ldr r0, [pc, #84] @ (8000738 ) 80006e4: f001 ff0c bl 8002500 /*Configure GPIO pins : PC6 PC7 PC8 PC9 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 80006e8: f44f 7370 mov.w r3, #960 @ 0x3c0 80006ec: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006ee: 2301 movs r3, #1 80006f0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80006f2: 2300 movs r3, #0 80006f4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80006f6: 2300 movs r3, #0 80006f8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006fa: f107 0314 add.w r3, r7, #20 80006fe: 4619 mov r1, r3 8000700: 480b ldr r0, [pc, #44] @ (8000730 ) 8000702: f001 fefd bl 8002500 /*Configure GPIO pin : PA8 */ GPIO_InitStruct.Pin = GPIO_PIN_8; 8000706: f44f 7380 mov.w r3, #256 @ 0x100 800070a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800070c: 2301 movs r3, #1 800070e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000710: 2300 movs r3, #0 8000712: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000714: 2300 movs r3, #0 8000716: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000718: f107 0314 add.w r3, r7, #20 800071c: 4619 mov r1, r3 800071e: 4805 ldr r0, [pc, #20] @ (8000734 ) 8000720: f001 feee bl 8002500 } 8000724: bf00 nop 8000726: 3728 adds r7, #40 @ 0x28 8000728: 46bd mov sp, r7 800072a: bd80 pop {r7, pc} 800072c: 40023800 .word 0x40023800 8000730: 40020800 .word 0x40020800 8000734: 40020000 .word 0x40020000 8000738: 40020400 .word 0x40020400 0800073c : I2C_HandleTypeDef hi2c1; /* I2C1 init function */ void MX_I2C1_Init(void) { 800073c: b580 push {r7, lr} 800073e: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8000740: 4b12 ldr r3, [pc, #72] @ (800078c ) 8000742: 4a13 ldr r2, [pc, #76] @ (8000790 ) 8000744: 601a str r2, [r3, #0] hi2c1.Init.ClockSpeed = 100000; 8000746: 4b11 ldr r3, [pc, #68] @ (800078c ) 8000748: 4a12 ldr r2, [pc, #72] @ (8000794 ) 800074a: 605a str r2, [r3, #4] hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; 800074c: 4b0f ldr r3, [pc, #60] @ (800078c ) 800074e: 2200 movs r2, #0 8000750: 609a str r2, [r3, #8] hi2c1.Init.OwnAddress1 = 0; 8000752: 4b0e ldr r3, [pc, #56] @ (800078c ) 8000754: 2200 movs r2, #0 8000756: 60da str r2, [r3, #12] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8000758: 4b0c ldr r3, [pc, #48] @ (800078c ) 800075a: f44f 4280 mov.w r2, #16384 @ 0x4000 800075e: 611a str r2, [r3, #16] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000760: 4b0a ldr r3, [pc, #40] @ (800078c ) 8000762: 2200 movs r2, #0 8000764: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2 = 0; 8000766: 4b09 ldr r3, [pc, #36] @ (800078c ) 8000768: 2200 movs r2, #0 800076a: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 800076c: 4b07 ldr r3, [pc, #28] @ (800078c ) 800076e: 2200 movs r2, #0 8000770: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8000772: 4b06 ldr r3, [pc, #24] @ (800078c ) 8000774: 2200 movs r2, #0 8000776: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8000778: 4804 ldr r0, [pc, #16] @ (800078c ) 800077a: f002 f887 bl 800288c 800077e: 4603 mov r3, r0 8000780: 2b00 cmp r3, #0 8000782: d001 beq.n 8000788 { Error_Handler(); 8000784: f000 fb40 bl 8000e08 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8000788: bf00 nop 800078a: bd80 pop {r7, pc} 800078c: 200001bc .word 0x200001bc 8000790: 40005400 .word 0x40005400 8000794: 000186a0 .word 0x000186a0 08000798 : void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) { 8000798: b580 push {r7, lr} 800079a: b08a sub sp, #40 @ 0x28 800079c: af00 add r7, sp, #0 800079e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007a0: f107 0314 add.w r3, r7, #20 80007a4: 2200 movs r2, #0 80007a6: 601a str r2, [r3, #0] 80007a8: 605a str r2, [r3, #4] 80007aa: 609a str r2, [r3, #8] 80007ac: 60da str r2, [r3, #12] 80007ae: 611a str r2, [r3, #16] if(i2cHandle->Instance==I2C1) 80007b0: 687b ldr r3, [r7, #4] 80007b2: 681b ldr r3, [r3, #0] 80007b4: 4a19 ldr r2, [pc, #100] @ (800081c ) 80007b6: 4293 cmp r3, r2 80007b8: d12b bne.n 8000812 { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80007ba: 2300 movs r3, #0 80007bc: 613b str r3, [r7, #16] 80007be: 4b18 ldr r3, [pc, #96] @ (8000820 ) 80007c0: 6b1b ldr r3, [r3, #48] @ 0x30 80007c2: 4a17 ldr r2, [pc, #92] @ (8000820 ) 80007c4: f043 0302 orr.w r3, r3, #2 80007c8: 6313 str r3, [r2, #48] @ 0x30 80007ca: 4b15 ldr r3, [pc, #84] @ (8000820 ) 80007cc: 6b1b ldr r3, [r3, #48] @ 0x30 80007ce: f003 0302 and.w r3, r3, #2 80007d2: 613b str r3, [r7, #16] 80007d4: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80007d6: 23c0 movs r3, #192 @ 0xc0 80007d8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80007da: 2312 movs r3, #18 80007dc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80007de: 2300 movs r3, #0 80007e0: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80007e2: 2303 movs r3, #3 80007e4: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 80007e6: 2304 movs r3, #4 80007e8: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80007ea: f107 0314 add.w r3, r7, #20 80007ee: 4619 mov r1, r3 80007f0: 480c ldr r0, [pc, #48] @ (8000824 ) 80007f2: f001 fe85 bl 8002500 /* I2C1 clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 80007f6: 2300 movs r3, #0 80007f8: 60fb str r3, [r7, #12] 80007fa: 4b09 ldr r3, [pc, #36] @ (8000820 ) 80007fc: 6c1b ldr r3, [r3, #64] @ 0x40 80007fe: 4a08 ldr r2, [pc, #32] @ (8000820 ) 8000800: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000804: 6413 str r3, [r2, #64] @ 0x40 8000806: 4b06 ldr r3, [pc, #24] @ (8000820 ) 8000808: 6c1b ldr r3, [r3, #64] @ 0x40 800080a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800080e: 60fb str r3, [r7, #12] 8000810: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8000812: bf00 nop 8000814: 3728 adds r7, #40 @ 0x28 8000816: 46bd mov sp, r7 8000818: bd80 pop {r7, pc} 800081a: bf00 nop 800081c: 40005400 .word 0x40005400 8000820: 40023800 .word 0x40023800 8000824: 40020400 .word 0x40020400 08000828
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000828: b580 push {r7, lr} 800082a: b088 sub sp, #32 800082c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800082e: f001 f8bd bl 80019ac /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000832: f000 f8b5 bl 80009a0 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000836: f7ff fee1 bl 80005fc MX_DMA_Init(); 800083a: f7ff fe79 bl 8000530 MX_TIM2_Init(); 800083e: f000 fbd5 bl 8000fec MX_TIM3_Init(); 8000842: f000 fc2b bl 800109c MX_UART4_Init(); 8000846: f000 fd1d bl 8001284 MX_UART5_Init(); 800084a: f000 fd45 bl 80012d8 MX_USART1_UART_Init(); 800084e: f000 fd6d bl 800132c MX_USART2_UART_Init(); 8000852: f000 fd95 bl 8001380 MX_I2C1_Init(); 8000856: f7ff ff71 bl 800073c MX_USB_DEVICE_Init(); 800085a: f009 fcd5 bl 800a208 /* USER CODE BEGIN 2 */ //Enable UART RX DMA for all ports HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 800085e: 2210 movs r2, #16 8000860: 4941 ldr r1, [pc, #260] @ (8000968 ) 8000862: 4842 ldr r0, [pc, #264] @ (800096c ) 8000864: f005 facc bl 8005e00 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000868: 2210 movs r2, #16 800086a: 4941 ldr r1, [pc, #260] @ (8000970 ) 800086c: 4841 ldr r0, [pc, #260] @ (8000974 ) 800086e: f005 fac7 bl 8005e00 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000872: 2210 movs r2, #16 8000874: 4940 ldr r1, [pc, #256] @ (8000978 ) 8000876: 4841 ldr r0, [pc, #260] @ (800097c ) 8000878: f005 fac2 bl 8005e00 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 800087c: 2210 movs r2, #16 800087e: 4940 ldr r1, [pc, #256] @ (8000980 ) 8000880: 4840 ldr r0, [pc, #256] @ (8000984 ) 8000882: f005 fabd bl 8005e00 HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); 8000886: 2100 movs r1, #0 8000888: 483f ldr r0, [pc, #252] @ (8000988 ) 800088a: f004 fd2b bl 80052e4 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { switch (MODE){ 800088e: 4b3f ldr r3, [pc, #252] @ (800098c ) 8000890: 781b ldrb r3, [r3, #0] 8000892: b2db uxtb r3, r3 8000894: 2b02 cmp r3, #2 8000896: d006 beq.n 80008a6 8000898: 2b02 cmp r3, #2 800089a: dc5f bgt.n 800095c 800089c: 2b00 cmp r3, #0 800089e: d01c beq.n 80008da 80008a0: 2b01 cmp r3, #1 80008a2: d051 beq.n 8000948 matrixScan(); USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); break; default: break; 80008a4: e05a b.n 800095c resetReport(); 80008a6: f000 fa9f bl 8000de8 matrixScan(); 80008aa: f000 fa43 bl 8000d34 UARTREPORT.DEPTH = DEPTH; 80008ae: 4b38 ldr r3, [pc, #224] @ (8000990 ) 80008b0: 881b ldrh r3, [r3, #0] 80008b2: 823b strh r3, [r7, #16] UARTREPORT.TYPE = 0xEE; 80008b4: 23ee movs r3, #238 @ 0xee 80008b6: 827b strh r3, [r7, #18] memcpy(UARTREPORT.KEYPRESS, REPORT.KEYPRESS, sizeof(UARTREPORT.KEYPRESS)); 80008b8: 4a36 ldr r2, [pc, #216] @ (8000994 ) 80008ba: f107 0314 add.w r3, r7, #20 80008be: 3202 adds r2, #2 80008c0: 6810 ldr r0, [r2, #0] 80008c2: 6851 ldr r1, [r2, #4] 80008c4: 6892 ldr r2, [r2, #8] 80008c6: c307 stmia r3!, {r0, r1, r2} HAL_UART_Transmit_DMA(PARENT, (uint8_t*)&UARTREPORT, sizeof(UARTREPORT)); 80008c8: 4b33 ldr r3, [pc, #204] @ (8000998 ) 80008ca: 681b ldr r3, [r3, #0] 80008cc: f107 0110 add.w r1, r7, #16 80008d0: 2210 movs r2, #16 80008d2: 4618 mov r0, r3 80008d4: f005 fa18 bl 8005d08 break; 80008d8: e041 b.n 800095e if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){ 80008da: 4b30 ldr r3, [pc, #192] @ (800099c ) 80008dc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80008e0: b2db uxtb r3, r3 80008e2: 2b03 cmp r3, #3 80008e4: d106 bne.n 80008f4 MODE = MODE_MAINBOARD; 80008e6: 4b29 ldr r3, [pc, #164] @ (800098c ) 80008e8: 2201 movs r2, #1 80008ea: 701a strb r2, [r3, #0] DEPTH = 0; 80008ec: 4b28 ldr r3, [pc, #160] @ (8000990 ) 80008ee: 2200 movs r2, #0 80008f0: 801a strh r2, [r3, #0] break; 80008f2: e034 b.n 800095e REQ.DEPTH = 0; 80008f4: 2300 movs r3, #0 80008f6: 803b strh r3, [r7, #0] REQ.TYPE = 0xFF; //Message code for request is 0xFF 80008f8: 23ff movs r3, #255 @ 0xff 80008fa: 807b strh r3, [r7, #2] memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS)); 80008fc: 463b mov r3, r7 80008fe: 3304 adds r3, #4 8000900: 220c movs r2, #12 8000902: 2100 movs r1, #0 8000904: 4618 mov r0, r3 8000906: f00a f92d bl 800ab64 HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ)); 800090a: 463b mov r3, r7 800090c: 2210 movs r2, #16 800090e: 4619 mov r1, r3 8000910: 4816 ldr r0, [pc, #88] @ (800096c ) 8000912: f005 f9f9 bl 8005d08 HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ)); 8000916: 463b mov r3, r7 8000918: 2210 movs r2, #16 800091a: 4619 mov r1, r3 800091c: 4815 ldr r0, [pc, #84] @ (8000974 ) 800091e: f005 f9f3 bl 8005d08 HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); 8000922: 463b mov r3, r7 8000924: 2210 movs r2, #16 8000926: 4619 mov r1, r3 8000928: 4814 ldr r0, [pc, #80] @ (800097c ) 800092a: f005 f9ed bl 8005d08 HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); 800092e: 463b mov r3, r7 8000930: 2210 movs r2, #16 8000932: 4619 mov r1, r3 8000934: 4813 ldr r0, [pc, #76] @ (8000984 ) 8000936: f005 f9e7 bl 8005d08 HAL_Delay(500); 800093a: f44f 70fa mov.w r0, #500 @ 0x1f4 800093e: f001 f8a7 bl 8001a90 findBestParent(); //So true... 8000942: f000 f8f5 bl 8000b30 break; 8000946: e00a b.n 800095e resetReport(); 8000948: f000 fa4e bl 8000de8 matrixScan(); 800094c: f000 f9f2 bl 8000d34 USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); 8000950: 220e movs r2, #14 8000952: 4910 ldr r1, [pc, #64] @ (8000994 ) 8000954: 4811 ldr r0, [pc, #68] @ (800099c ) 8000956: f008 f88b bl 8008a70 break; 800095a: e000 b.n 800095e break; 800095c: bf00 nop } HAL_Delay(50); 800095e: 2032 movs r0, #50 @ 0x32 8000960: f001 f896 bl 8001a90 switch (MODE){ 8000964: e793 b.n 800088e 8000966: bf00 nop 8000968: 20000230 .word 0x20000230 800096c: 2000038c .word 0x2000038c 8000970: 20000240 .word 0x20000240 8000974: 200003d4 .word 0x200003d4 8000978: 20000250 .word 0x20000250 800097c: 200002fc .word 0x200002fc 8000980: 20000220 .word 0x20000220 8000984: 20000344 .word 0x20000344 8000988: 2000026c .word 0x2000026c 800098c: 20000268 .word 0x20000268 8000990: 20000260 .word 0x20000260 8000994: 20000210 .word 0x20000210 8000998: 20000264 .word 0x20000264 800099c: 20000724 .word 0x20000724 080009a0 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80009a0: b580 push {r7, lr} 80009a2: b094 sub sp, #80 @ 0x50 80009a4: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80009a6: f107 031c add.w r3, r7, #28 80009aa: 2234 movs r2, #52 @ 0x34 80009ac: 2100 movs r1, #0 80009ae: 4618 mov r0, r3 80009b0: f00a f8d8 bl 800ab64 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80009b4: f107 0308 add.w r3, r7, #8 80009b8: 2200 movs r2, #0 80009ba: 601a str r2, [r3, #0] 80009bc: 605a str r2, [r3, #4] 80009be: 609a str r2, [r3, #8] 80009c0: 60da str r2, [r3, #12] 80009c2: 611a str r2, [r3, #16] /** Configure the main internal regulator out put voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 80009c4: 2300 movs r3, #0 80009c6: 607b str r3, [r7, #4] 80009c8: 4b29 ldr r3, [pc, #164] @ (8000a70 ) 80009ca: 6c1b ldr r3, [r3, #64] @ 0x40 80009cc: 4a28 ldr r2, [pc, #160] @ (8000a70 ) 80009ce: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80009d2: 6413 str r3, [r2, #64] @ 0x40 80009d4: 4b26 ldr r3, [pc, #152] @ (8000a70 ) 80009d6: 6c1b ldr r3, [r3, #64] @ 0x40 80009d8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80009dc: 607b str r3, [r7, #4] 80009de: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 80009e0: 2300 movs r3, #0 80009e2: 603b str r3, [r7, #0] 80009e4: 4b23 ldr r3, [pc, #140] @ (8000a74 ) 80009e6: 681b ldr r3, [r3, #0] 80009e8: f423 4340 bic.w r3, r3, #49152 @ 0xc000 80009ec: 4a21 ldr r2, [pc, #132] @ (8000a74 ) 80009ee: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80009f2: 6013 str r3, [r2, #0] 80009f4: 4b1f ldr r3, [pc, #124] @ (8000a74 ) 80009f6: 681b ldr r3, [r3, #0] 80009f8: f403 4340 and.w r3, r3, #49152 @ 0xc000 80009fc: 603b str r3, [r7, #0] 80009fe: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000a00: 2301 movs r3, #1 8000a02: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000a04: f44f 3380 mov.w r3, #65536 @ 0x10000 8000a08: 623b str r3, [r7, #32] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000a0a: 2302 movs r3, #2 8000a0c: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000a0e: f44f 0380 mov.w r3, #4194304 @ 0x400000 8000a12: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLM = 4; 8000a14: 2304 movs r3, #4 8000a16: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLN = 96; 8000a18: 2360 movs r3, #96 @ 0x60 8000a1a: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8000a1c: 2302 movs r3, #2 8000a1e: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLQ = 4; 8000a20: 2304 movs r3, #4 8000a22: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLR = 2; 8000a24: 2302 movs r3, #2 8000a26: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000a28: f107 031c add.w r3, r7, #28 8000a2c: 4618 mov r0, r3 8000a2e: f004 f96b bl 8004d08 8000a32: 4603 mov r3, r0 8000a34: 2b00 cmp r3, #0 8000a36: d001 beq.n 8000a3c { Error_Handler(); 8000a38: f000 f9e6 bl 8000e08 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000a3c: 230f movs r3, #15 8000a3e: 60bb str r3, [r7, #8] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000a40: 2302 movs r3, #2 8000a42: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; 8000a44: 2380 movs r3, #128 @ 0x80 8000a46: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000a48: f44f 5380 mov.w r3, #4096 @ 0x1000 8000a4c: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000a4e: 2300 movs r3, #0 8000a50: 61bb str r3, [r7, #24] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000a52: f107 0308 add.w r3, r7, #8 8000a56: 2101 movs r1, #1 8000a58: 4618 mov r0, r3 8000a5a: f003 fae1 bl 8004020 8000a5e: 4603 mov r3, r0 8000a60: 2b00 cmp r3, #0 8000a62: d001 beq.n 8000a68 { Error_Handler(); 8000a64: f000 f9d0 bl 8000e08 } } 8000a68: bf00 nop 8000a6a: 3750 adds r7, #80 @ 0x50 8000a6c: 46bd mov sp, r7 8000a6e: bd80 pop {r7, pc} 8000a70: 40023800 .word 0x40023800 8000a74: 40007000 .word 0x40007000 08000a78 : /* USER CODE BEGIN 4 */ // UART Message Requests Goes Here void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8000a78: b580 push {r7, lr} 8000a7a: b082 sub sp, #8 8000a7c: af00 add r7, sp, #0 8000a7e: 6078 str r0, [r7, #4] if (huart->Instance == USART1) { 8000a80: 687b ldr r3, [r7, #4] 8000a82: 681b ldr r3, [r3, #0] 8000a84: 4a1e ldr r2, [pc, #120] @ (8000b00 ) 8000a86: 4293 cmp r3, r2 8000a88: d109 bne.n 8000a9e handleUARTMessages((uint8_t*)&RX1Msg, &huart1); 8000a8a: 491e ldr r1, [pc, #120] @ (8000b04 ) 8000a8c: 481e ldr r0, [pc, #120] @ (8000b08 ) 8000a8e: f000 f891 bl 8000bb4 HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000a92: 2210 movs r2, #16 8000a94: 491c ldr r1, [pc, #112] @ (8000b08 ) 8000a96: 481b ldr r0, [pc, #108] @ (8000b04 ) 8000a98: f005 f9b2 bl 8005e00 } else if (huart->Instance == UART5) { handleUARTMessages((uint8_t*)&RX5Msg, &huart5); HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000a9c: e02b b.n 8000af6 else if (huart->Instance == USART2) { 8000a9e: 687b ldr r3, [r7, #4] 8000aa0: 681b ldr r3, [r3, #0] 8000aa2: 4a1a ldr r2, [pc, #104] @ (8000b0c ) 8000aa4: 4293 cmp r3, r2 8000aa6: d109 bne.n 8000abc handleUARTMessages((uint8_t*)&RX2Msg, &huart2); 8000aa8: 4919 ldr r1, [pc, #100] @ (8000b10 ) 8000aaa: 481a ldr r0, [pc, #104] @ (8000b14 ) 8000aac: f000 f882 bl 8000bb4 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000ab0: 2210 movs r2, #16 8000ab2: 4918 ldr r1, [pc, #96] @ (8000b14 ) 8000ab4: 4816 ldr r0, [pc, #88] @ (8000b10 ) 8000ab6: f005 f9a3 bl 8005e00 } 8000aba: e01c b.n 8000af6 else if (huart->Instance == UART4) { 8000abc: 687b ldr r3, [r7, #4] 8000abe: 681b ldr r3, [r3, #0] 8000ac0: 4a15 ldr r2, [pc, #84] @ (8000b18 ) 8000ac2: 4293 cmp r3, r2 8000ac4: d109 bne.n 8000ada handleUARTMessages((uint8_t*)&RX4Msg, &huart4); 8000ac6: 4915 ldr r1, [pc, #84] @ (8000b1c ) 8000ac8: 4815 ldr r0, [pc, #84] @ (8000b20 ) 8000aca: f000 f873 bl 8000bb4 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000ace: 2210 movs r2, #16 8000ad0: 4913 ldr r1, [pc, #76] @ (8000b20 ) 8000ad2: 4812 ldr r0, [pc, #72] @ (8000b1c ) 8000ad4: f005 f994 bl 8005e00 } 8000ad8: e00d b.n 8000af6 else if (huart->Instance == UART5) { 8000ada: 687b ldr r3, [r7, #4] 8000adc: 681b ldr r3, [r3, #0] 8000ade: 4a11 ldr r2, [pc, #68] @ (8000b24 ) 8000ae0: 4293 cmp r3, r2 8000ae2: d108 bne.n 8000af6 handleUARTMessages((uint8_t*)&RX5Msg, &huart5); 8000ae4: 4910 ldr r1, [pc, #64] @ (8000b28 ) 8000ae6: 4811 ldr r0, [pc, #68] @ (8000b2c ) 8000ae8: f000 f864 bl 8000bb4 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000aec: 2210 movs r2, #16 8000aee: 490f ldr r1, [pc, #60] @ (8000b2c ) 8000af0: 480d ldr r0, [pc, #52] @ (8000b28 ) 8000af2: f005 f985 bl 8005e00 } 8000af6: bf00 nop 8000af8: 3708 adds r7, #8 8000afa: 46bd mov sp, r7 8000afc: bd80 pop {r7, pc} 8000afe: bf00 nop 8000b00: 40011000 .word 0x40011000 8000b04: 2000038c .word 0x2000038c 8000b08: 20000230 .word 0x20000230 8000b0c: 40004400 .word 0x40004400 8000b10: 200003d4 .word 0x200003d4 8000b14: 20000240 .word 0x20000240 8000b18: 40004c00 .word 0x40004c00 8000b1c: 200002fc .word 0x200002fc 8000b20: 20000250 .word 0x20000250 8000b24: 40005000 .word 0x40005000 8000b28: 20000344 .word 0x20000344 8000b2c: 20000220 .word 0x20000220 08000b30 : void findBestParent(){ 8000b30: b580 push {r7, lr} 8000b32: b084 sub sp, #16 8000b34: af00 add r7, sp, #0 //Find least depth parent uint16_t least_val = 0xFF; 8000b36: 23ff movs r3, #255 @ 0xff 8000b38: 81fb strh r3, [r7, #14] UART_HandleTypeDef* least_port = NULL; 8000b3a: 2300 movs r3, #0 8000b3c: 60bb str r3, [r7, #8] for(uint8_t i = 0; i < 4; i++){ 8000b3e: 2300 movs r3, #0 8000b40: 71fb strb r3, [r7, #7] 8000b42: e013 b.n 8000b6c if(PORT_DEPTH[i]) 8000b48: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000b4c: 89fa ldrh r2, [r7, #14] 8000b4e: 429a cmp r2, r3 8000b50: d909 bls.n 8000b66 least_port = PORTS[i]; 8000b52: 79fb ldrb r3, [r7, #7] 8000b54: 4a13 ldr r2, [pc, #76] @ (8000ba4 ) 8000b56: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000b5a: 60bb str r3, [r7, #8] least_val = PORT_DEPTH[i]; 8000b5c: 79fb ldrb r3, [r7, #7] 8000b5e: 4a10 ldr r2, [pc, #64] @ (8000ba0 ) 8000b60: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000b64: 81fb strh r3, [r7, #14] for(uint8_t i = 0; i < 4; i++){ 8000b66: 79fb ldrb r3, [r7, #7] 8000b68: 3301 adds r3, #1 8000b6a: 71fb strb r3, [r7, #7] 8000b6c: 79fb ldrb r3, [r7, #7] 8000b6e: 2b03 cmp r3, #3 8000b70: d9e8 bls.n 8000b44 } } //Assign if valid if(least_val < 0xFF){ 8000b72: 89fb ldrh r3, [r7, #14] 8000b74: 2bfe cmp r3, #254 @ 0xfe 8000b76: d80e bhi.n 8000b96 PARENT = least_port; 8000b78: 4a0b ldr r2, [pc, #44] @ (8000ba8 ) 8000b7a: 68bb ldr r3, [r7, #8] 8000b7c: 6013 str r3, [r2, #0] DEPTH = least_val + 1; 8000b7e: 89fb ldrh r3, [r7, #14] 8000b80: 3301 adds r3, #1 8000b82: b29a uxth r2, r3 8000b84: 4b09 ldr r3, [pc, #36] @ (8000bac ) 8000b86: 801a strh r2, [r3, #0] MODE = MODE_ACTIVE; 8000b88: 4b09 ldr r3, [pc, #36] @ (8000bb0 ) 8000b8a: 2202 movs r2, #2 8000b8c: 701a strb r2, [r3, #0] HAL_Delay(500); 8000b8e: f44f 70fa mov.w r0, #500 @ 0x1f4 8000b92: f000 ff7d bl 8001a90 } } 8000b96: bf00 nop 8000b98: 3710 adds r7, #16 8000b9a: 46bd mov sp, r7 8000b9c: bd80 pop {r7, pc} 8000b9e: bf00 nop 8000ba0: 20000078 .word 0x20000078 8000ba4: 20000080 .word 0x20000080 8000ba8: 20000264 .word 0x20000264 8000bac: 20000260 .word 0x20000260 8000bb0: 20000268 .word 0x20000268 08000bb4 : // Called when UART RX interrupt completes void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender) { 8000bb4: b580 push {r7, lr} 8000bb6: b08c sub sp, #48 @ 0x30 8000bb8: af00 add r7, sp, #0 8000bba: 6078 str r0, [r7, #4] 8000bbc: 6039 str r1, [r7, #0] UARTMessage msg; UARTMessage reply; // Parse incoming message into struct memcpy(&msg, data, sizeof(UARTMessage)); 8000bbe: f107 031c add.w r3, r7, #28 8000bc2: 2210 movs r2, #16 8000bc4: 6879 ldr r1, [r7, #4] 8000bc6: 4618 mov r0, r3 8000bc8: f009 fff8 bl 800abbc switch(msg.TYPE) { 8000bcc: 8bfb ldrh r3, [r7, #30] 8000bce: 2bff cmp r3, #255 @ 0xff 8000bd0: d026 beq.n 8000c20 8000bd2: 2bff cmp r3, #255 @ 0xff 8000bd4: dc5f bgt.n 8000c96 8000bd6: 2baa cmp r3, #170 @ 0xaa 8000bd8: d002 beq.n 8000be0 8000bda: 2bee cmp r3, #238 @ 0xee 8000bdc: d03a beq.n 8000c54 } } break; default: break; 8000bde: e05a b.n 8000c96 if(sender == &huart5) { 8000be0: 683b ldr r3, [r7, #0] 8000be2: 4a32 ldr r2, [pc, #200] @ (8000cac ) 8000be4: 4293 cmp r3, r2 8000be6: d103 bne.n 8000bf0 PORT_DEPTH[0] = msg.DEPTH; 8000be8: 8bba ldrh r2, [r7, #28] 8000bea: 4b31 ldr r3, [pc, #196] @ (8000cb0 ) 8000bec: 801a strh r2, [r3, #0] break; 8000bee: e054 b.n 8000c9a } else if(sender == &huart1) { 8000bf0: 683b ldr r3, [r7, #0] 8000bf2: 4a30 ldr r2, [pc, #192] @ (8000cb4 ) 8000bf4: 4293 cmp r3, r2 8000bf6: d103 bne.n 8000c00 PORT_DEPTH[1] = msg.DEPTH; 8000bf8: 8bba ldrh r2, [r7, #28] 8000bfa: 4b2d ldr r3, [pc, #180] @ (8000cb0 ) 8000bfc: 805a strh r2, [r3, #2] break; 8000bfe: e04c b.n 8000c9a } else if(sender == &huart2) { 8000c00: 683b ldr r3, [r7, #0] 8000c02: 4a2d ldr r2, [pc, #180] @ (8000cb8 ) 8000c04: 4293 cmp r3, r2 8000c06: d103 bne.n 8000c10 PORT_DEPTH[2] = msg.DEPTH; 8000c08: 8bba ldrh r2, [r7, #28] 8000c0a: 4b29 ldr r3, [pc, #164] @ (8000cb0 ) 8000c0c: 809a strh r2, [r3, #4] break; 8000c0e: e044 b.n 8000c9a } else if(sender == &huart4) { 8000c10: 683b ldr r3, [r7, #0] 8000c12: 4a2a ldr r2, [pc, #168] @ (8000cbc ) 8000c14: 4293 cmp r3, r2 8000c16: d140 bne.n 8000c9a PORT_DEPTH[3] = msg.DEPTH; 8000c18: 8bba ldrh r2, [r7, #28] 8000c1a: 4b25 ldr r3, [pc, #148] @ (8000cb0 ) 8000c1c: 80da strh r2, [r3, #6] break; 8000c1e: e03c b.n 8000c9a if(MODE!=MODE_INACTIVE){ 8000c20: 4b27 ldr r3, [pc, #156] @ (8000cc0 ) 8000c22: 781b ldrb r3, [r3, #0] 8000c24: b2db uxtb r3, r3 8000c26: 2b00 cmp r3, #0 8000c28: d039 beq.n 8000c9e reply.TYPE = 0xAA; 8000c2a: 23aa movs r3, #170 @ 0xaa 8000c2c: 81fb strh r3, [r7, #14] reply.DEPTH = DEPTH; // use your local DEPTH 8000c2e: 4b25 ldr r3, [pc, #148] @ (8000cc4 ) 8000c30: 881b ldrh r3, [r3, #0] 8000c32: 81bb strh r3, [r7, #12] memset(reply.KEYPRESS, 0, sizeof(reply.KEYPRESS)); 8000c34: f107 030c add.w r3, r7, #12 8000c38: 3304 adds r3, #4 8000c3a: 220c movs r2, #12 8000c3c: 2100 movs r1, #0 8000c3e: 4618 mov r0, r3 8000c40: f009 ff90 bl 800ab64 HAL_UART_Transmit_DMA(sender, (uint8_t*)&reply, sizeof(reply)); 8000c44: f107 030c add.w r3, r7, #12 8000c48: 2210 movs r2, #16 8000c4a: 4619 mov r1, r3 8000c4c: 6838 ldr r0, [r7, #0] 8000c4e: f005 f85b bl 8005d08 break; 8000c52: e024 b.n 8000c9e if(MODE!=MODE_INACTIVE){ 8000c54: 4b1a ldr r3, [pc, #104] @ (8000cc0 ) 8000c56: 781b ldrb r3, [r3, #0] 8000c58: b2db uxtb r3, r3 8000c5a: 2b00 cmp r3, #0 8000c5c: d021 beq.n 8000ca2 for (int i = 0; i < sizeof(REPORT.KEYPRESS); i++) { 8000c5e: 2300 movs r3, #0 8000c60: 62fb str r3, [r7, #44] @ 0x2c 8000c62: e014 b.n 8000c8e REPORT.KEYPRESS[i] |= msg.KEYPRESS[i]; // bitwise merge keys 8000c64: 4a18 ldr r2, [pc, #96] @ (8000cc8 ) 8000c66: 6afb ldr r3, [r7, #44] @ 0x2c 8000c68: 4413 add r3, r2 8000c6a: 3302 adds r3, #2 8000c6c: 781a ldrb r2, [r3, #0] 8000c6e: f107 0120 add.w r1, r7, #32 8000c72: 6afb ldr r3, [r7, #44] @ 0x2c 8000c74: 440b add r3, r1 8000c76: 781b ldrb r3, [r3, #0] 8000c78: 4313 orrs r3, r2 8000c7a: b2d9 uxtb r1, r3 8000c7c: 4a12 ldr r2, [pc, #72] @ (8000cc8 ) 8000c7e: 6afb ldr r3, [r7, #44] @ 0x2c 8000c80: 4413 add r3, r2 8000c82: 3302 adds r3, #2 8000c84: 460a mov r2, r1 8000c86: 701a strb r2, [r3, #0] for (int i = 0; i < sizeof(REPORT.KEYPRESS); i++) { 8000c88: 6afb ldr r3, [r7, #44] @ 0x2c 8000c8a: 3301 adds r3, #1 8000c8c: 62fb str r3, [r7, #44] @ 0x2c 8000c8e: 6afb ldr r3, [r7, #44] @ 0x2c 8000c90: 2b0b cmp r3, #11 8000c92: d9e7 bls.n 8000c64 break; 8000c94: e005 b.n 8000ca2 break; 8000c96: bf00 nop 8000c98: e004 b.n 8000ca4 break; 8000c9a: bf00 nop 8000c9c: e002 b.n 8000ca4 break; 8000c9e: bf00 nop 8000ca0: e000 b.n 8000ca4 break; 8000ca2: bf00 nop } } 8000ca4: bf00 nop 8000ca6: 3730 adds r7, #48 @ 0x30 8000ca8: 46bd mov sp, r7 8000caa: bd80 pop {r7, pc} 8000cac: 20000344 .word 0x20000344 8000cb0: 20000078 .word 0x20000078 8000cb4: 2000038c .word 0x2000038c 8000cb8: 200003d4 .word 0x200003d4 8000cbc: 200002fc .word 0x200002fc 8000cc0: 20000268 .word 0x20000268 8000cc4: 20000260 .word 0x20000260 8000cc8: 20000210 .word 0x20000210 08000ccc : void addUSBReport(uint8_t usageID){ 8000ccc: b480 push {r7} 8000cce: b085 sub sp, #20 8000cd0: af00 add r7, sp, #0 8000cd2: 4603 mov r3, r0 8000cd4: 71fb strb r3, [r7, #7] if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8000cd6: 79fb ldrb r3, [r7, #7] 8000cd8: 2b03 cmp r3, #3 8000cda: d922 bls.n 8000d22 8000cdc: 79fb ldrb r3, [r7, #7] 8000cde: 2b73 cmp r3, #115 @ 0x73 8000ce0: d81f bhi.n 8000d22 uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit 8000ce2: 79fb ldrb r3, [r7, #7] 8000ce4: b29b uxth r3, r3 8000ce6: 3b04 subs r3, #4 8000ce8: 81fb strh r3, [r7, #14] uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array 8000cea: 89fb ldrh r3, [r7, #14] 8000cec: 08db lsrs r3, r3, #3 8000cee: b29b uxth r3, r3 8000cf0: 737b strb r3, [r7, #13] uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset 8000cf2: 89fb ldrh r3, [r7, #14] 8000cf4: b2db uxtb r3, r3 8000cf6: f003 0307 and.w r3, r3, #7 8000cfa: 733b strb r3, [r7, #12] REPORT.KEYPRESS[byte_index] |= (1 << bit_offset); 8000cfc: 7b7b ldrb r3, [r7, #13] 8000cfe: 4a0c ldr r2, [pc, #48] @ (8000d30 ) 8000d00: 4413 add r3, r2 8000d02: 789b ldrb r3, [r3, #2] 8000d04: b25a sxtb r2, r3 8000d06: 7b3b ldrb r3, [r7, #12] 8000d08: 2101 movs r1, #1 8000d0a: fa01 f303 lsl.w r3, r1, r3 8000d0e: b25b sxtb r3, r3 8000d10: 4313 orrs r3, r2 8000d12: b25a sxtb r2, r3 8000d14: 7b7b ldrb r3, [r7, #13] 8000d16: b2d1 uxtb r1, r2 8000d18: 4a05 ldr r2, [pc, #20] @ (8000d30 ) 8000d1a: 4413 add r3, r2 8000d1c: 460a mov r2, r1 8000d1e: 709a strb r2, [r3, #2] 8000d20: e000 b.n 8000d24 if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8000d22: bf00 nop } 8000d24: 3714 adds r7, #20 8000d26: 46bd mov sp, r7 8000d28: f85d 7b04 ldr.w r7, [sp], #4 8000d2c: 4770 bx lr 8000d2e: bf00 nop 8000d30: 20000210 .word 0x20000210 08000d34 : void matrixScan(void){ 8000d34: b580 push {r7, lr} 8000d36: b082 sub sp, #8 8000d38: af00 add r7, sp, #0 for (uint8_t col = 0; col < COL; col++){ 8000d3a: 2300 movs r3, #0 8000d3c: 71fb strb r3, [r7, #7] 8000d3e: e044 b.n 8000dca HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET); 8000d40: 79fb ldrb r3, [r7, #7] 8000d42: 4a26 ldr r2, [pc, #152] @ (8000ddc ) 8000d44: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000d48: 79fb ldrb r3, [r7, #7] 8000d4a: 4a24 ldr r2, [pc, #144] @ (8000ddc ) 8000d4c: 00db lsls r3, r3, #3 8000d4e: 4413 add r3, r2 8000d50: 889b ldrh r3, [r3, #4] 8000d52: 2201 movs r2, #1 8000d54: 4619 mov r1, r3 8000d56: f001 fd7f bl 8002858 HAL_Delay(1); 8000d5a: 2001 movs r0, #1 8000d5c: f000 fe98 bl 8001a90 for(uint8_t row = 0; row < ROW; row++){ 8000d60: 2300 movs r3, #0 8000d62: 71bb strb r3, [r7, #6] 8000d64: e01e b.n 8000da4 if(HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN)){ 8000d66: 79bb ldrb r3, [r7, #6] 8000d68: 4a1d ldr r2, [pc, #116] @ (8000de0 ) 8000d6a: f852 2033 ldr.w r2, [r2, r3, lsl #3] 8000d6e: 79bb ldrb r3, [r7, #6] 8000d70: 491b ldr r1, [pc, #108] @ (8000de0 ) 8000d72: 00db lsls r3, r3, #3 8000d74: 440b add r3, r1 8000d76: 889b ldrh r3, [r3, #4] 8000d78: 4619 mov r1, r3 8000d7a: 4610 mov r0, r2 8000d7c: f001 fd54 bl 8002828 8000d80: 4603 mov r3, r0 8000d82: 2b00 cmp r3, #0 8000d84: d00b beq.n 8000d9e addUSBReport(KEYCODES[row][col]); 8000d86: 79ba ldrb r2, [r7, #6] 8000d88: 79f9 ldrb r1, [r7, #7] 8000d8a: 4816 ldr r0, [pc, #88] @ (8000de4 ) 8000d8c: 4613 mov r3, r2 8000d8e: 009b lsls r3, r3, #2 8000d90: 4413 add r3, r2 8000d92: 4403 add r3, r0 8000d94: 440b add r3, r1 8000d96: 781b ldrb r3, [r3, #0] 8000d98: 4618 mov r0, r3 8000d9a: f7ff ff97 bl 8000ccc for(uint8_t row = 0; row < ROW; row++){ 8000d9e: 79bb ldrb r3, [r7, #6] 8000da0: 3301 adds r3, #1 8000da2: 71bb strb r3, [r7, #6] 8000da4: 79bb ldrb r3, [r7, #6] 8000da6: 2b05 cmp r3, #5 8000da8: d9dd bls.n 8000d66 } } HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET); 8000daa: 79fb ldrb r3, [r7, #7] 8000dac: 4a0b ldr r2, [pc, #44] @ (8000ddc ) 8000dae: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000db2: 79fb ldrb r3, [r7, #7] 8000db4: 4a09 ldr r2, [pc, #36] @ (8000ddc ) 8000db6: 00db lsls r3, r3, #3 8000db8: 4413 add r3, r2 8000dba: 889b ldrh r3, [r3, #4] 8000dbc: 2200 movs r2, #0 8000dbe: 4619 mov r1, r3 8000dc0: f001 fd4a bl 8002858 for (uint8_t col = 0; col < COL; col++){ 8000dc4: 79fb ldrb r3, [r7, #7] 8000dc6: 3301 adds r3, #1 8000dc8: 71fb strb r3, [r7, #7] 8000dca: 79fb ldrb r3, [r7, #7] 8000dcc: 2b04 cmp r3, #4 8000dce: d9b7 bls.n 8000d40 } } 8000dd0: bf00 nop 8000dd2: bf00 nop 8000dd4: 3708 adds r7, #8 8000dd6: 46bd mov sp, r7 8000dd8: bd80 pop {r7, pc} 8000dda: bf00 nop 8000ddc: 20000030 .word 0x20000030 8000de0: 20000000 .word 0x20000000 8000de4: 20000058 .word 0x20000058 08000de8 : void resetReport(void){ 8000de8: b580 push {r7, lr} 8000dea: af00 add r7, sp, #0 REPORT.MODIFIER = 0; 8000dec: 4b04 ldr r3, [pc, #16] @ (8000e00 ) 8000dee: 2200 movs r2, #0 8000df0: 701a strb r2, [r3, #0] memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS)); 8000df2: 220c movs r2, #12 8000df4: 2100 movs r1, #0 8000df6: 4803 ldr r0, [pc, #12] @ (8000e04 ) 8000df8: f009 feb4 bl 800ab64 } 8000dfc: bf00 nop 8000dfe: bd80 pop {r7, pc} 8000e00: 20000210 .word 0x20000210 8000e04: 20000212 .word 0x20000212 08000e08 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000e08: b480 push {r7} 8000e0a: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000e0c: b672 cpsid i } 8000e0e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000e10: bf00 nop 8000e12: e7fd b.n 8000e10 08000e14 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000e14: b480 push {r7} 8000e16: b083 sub sp, #12 8000e18: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000e1a: 2300 movs r3, #0 8000e1c: 607b str r3, [r7, #4] 8000e1e: 4b10 ldr r3, [pc, #64] @ (8000e60 ) 8000e20: 6c5b ldr r3, [r3, #68] @ 0x44 8000e22: 4a0f ldr r2, [pc, #60] @ (8000e60 ) 8000e24: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000e28: 6453 str r3, [r2, #68] @ 0x44 8000e2a: 4b0d ldr r3, [pc, #52] @ (8000e60 ) 8000e2c: 6c5b ldr r3, [r3, #68] @ 0x44 8000e2e: f403 4380 and.w r3, r3, #16384 @ 0x4000 8000e32: 607b str r3, [r7, #4] 8000e34: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000e36: 2300 movs r3, #0 8000e38: 603b str r3, [r7, #0] 8000e3a: 4b09 ldr r3, [pc, #36] @ (8000e60 ) 8000e3c: 6c1b ldr r3, [r3, #64] @ 0x40 8000e3e: 4a08 ldr r2, [pc, #32] @ (8000e60 ) 8000e40: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000e44: 6413 str r3, [r2, #64] @ 0x40 8000e46: 4b06 ldr r3, [pc, #24] @ (8000e60 ) 8000e48: 6c1b ldr r3, [r3, #64] @ 0x40 8000e4a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000e4e: 603b str r3, [r7, #0] 8000e50: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000e52: bf00 nop 8000e54: 370c adds r7, #12 8000e56: 46bd mov sp, r7 8000e58: f85d 7b04 ldr.w r7, [sp], #4 8000e5c: 4770 bx lr 8000e5e: bf00 nop 8000e60: 40023800 .word 0x40023800 08000e64 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000e64: b480 push {r7} 8000e66: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000e68: bf00 nop 8000e6a: e7fd b.n 8000e68 08000e6c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000e6c: b480 push {r7} 8000e6e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000e70: bf00 nop 8000e72: e7fd b.n 8000e70 08000e74 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000e74: b480 push {r7} 8000e76: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000e78: bf00 nop 8000e7a: e7fd b.n 8000e78 08000e7c : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000e7c: b480 push {r7} 8000e7e: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000e80: bf00 nop 8000e82: e7fd b.n 8000e80 08000e84 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000e84: b480 push {r7} 8000e86: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000e88: bf00 nop 8000e8a: e7fd b.n 8000e88 08000e8c : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000e8c: b480 push {r7} 8000e8e: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000e90: bf00 nop 8000e92: 46bd mov sp, r7 8000e94: f85d 7b04 ldr.w r7, [sp], #4 8000e98: 4770 bx lr 08000e9a : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000e9a: b480 push {r7} 8000e9c: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000e9e: bf00 nop 8000ea0: 46bd mov sp, r7 8000ea2: f85d 7b04 ldr.w r7, [sp], #4 8000ea6: 4770 bx lr 08000ea8 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000ea8: b480 push {r7} 8000eaa: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000eac: bf00 nop 8000eae: 46bd mov sp, r7 8000eb0: f85d 7b04 ldr.w r7, [sp], #4 8000eb4: 4770 bx lr 08000eb6 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000eb6: b580 push {r7, lr} 8000eb8: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000eba: f000 fdc9 bl 8001a50 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000ebe: bf00 nop 8000ec0: bd80 pop {r7, pc} ... 08000ec4 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8000ec4: b580 push {r7, lr} 8000ec6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_rx); 8000ec8: 4802 ldr r0, [pc, #8] @ (8000ed4 ) 8000eca: f001 f8af bl 800202c /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 8000ece: bf00 nop 8000ed0: bd80 pop {r7, pc} 8000ed2: bf00 nop 8000ed4: 200004dc .word 0x200004dc 08000ed8 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 8000ed8: b580 push {r7, lr} 8000eda: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_rx); 8000edc: 4802 ldr r0, [pc, #8] @ (8000ee8 ) 8000ede: f001 f8a5 bl 800202c /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 8000ee2: bf00 nop 8000ee4: bd80 pop {r7, pc} 8000ee6: bf00 nop 8000ee8: 2000041c .word 0x2000041c 08000eec : /** * @brief This function handles DMA1 stream4 global interrupt. */ void DMA1_Stream4_IRQHandler(void) { 8000eec: b580 push {r7, lr} 8000eee: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ /* USER CODE END DMA1_Stream4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_tx); 8000ef0: 4802 ldr r0, [pc, #8] @ (8000efc ) 8000ef2: f001 f89b bl 800202c /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ /* USER CODE END DMA1_Stream4_IRQn 1 */ } 8000ef6: bf00 nop 8000ef8: bd80 pop {r7, pc} 8000efa: bf00 nop 8000efc: 2000047c .word 0x2000047c 08000f00 : /** * @brief This function handles DMA1 stream5 global interrupt. */ void DMA1_Stream5_IRQHandler(void) { 8000f00: b580 push {r7, lr} 8000f02: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ /* USER CODE END DMA1_Stream5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 8000f04: 4802 ldr r0, [pc, #8] @ (8000f10 ) 8000f06: f001 f891 bl 800202c /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ /* USER CODE END DMA1_Stream5_IRQn 1 */ } 8000f0a: bf00 nop 8000f0c: bd80 pop {r7, pc} 8000f0e: bf00 nop 8000f10: 2000065c .word 0x2000065c 08000f14 : /** * @brief This function handles DMA1 stream6 global interrupt. */ void DMA1_Stream6_IRQHandler(void) { 8000f14: b580 push {r7, lr} 8000f16: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ /* USER CODE END DMA1_Stream6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 8000f18: 4802 ldr r0, [pc, #8] @ (8000f24 ) 8000f1a: f001 f887 bl 800202c /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ /* USER CODE END DMA1_Stream6_IRQn 1 */ } 8000f1e: bf00 nop 8000f20: bd80 pop {r7, pc} 8000f22: bf00 nop 8000f24: 200006bc .word 0x200006bc 08000f28 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8000f28: b580 push {r7, lr} 8000f2a: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8000f2c: 4802 ldr r0, [pc, #8] @ (8000f38 ) 8000f2e: f004 ff8d bl 8005e4c /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8000f32: bf00 nop 8000f34: bd80 pop {r7, pc} 8000f36: bf00 nop 8000f38: 2000038c .word 0x2000038c 08000f3c : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 8000f3c: b580 push {r7, lr} 8000f3e: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 8000f40: 4802 ldr r0, [pc, #8] @ (8000f4c ) 8000f42: f004 ff83 bl 8005e4c /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 8000f46: bf00 nop 8000f48: bd80 pop {r7, pc} 8000f4a: bf00 nop 8000f4c: 200003d4 .word 0x200003d4 08000f50 : /** * @brief This function handles DMA1 stream7 global interrupt. */ void DMA1_Stream7_IRQHandler(void) { 8000f50: b580 push {r7, lr} 8000f52: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ /* USER CODE END DMA1_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_tx); 8000f54: 4802 ldr r0, [pc, #8] @ (8000f60 ) 8000f56: f001 f869 bl 800202c /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ /* USER CODE END DMA1_Stream7_IRQn 1 */ } 8000f5a: bf00 nop 8000f5c: bd80 pop {r7, pc} 8000f5e: bf00 nop 8000f60: 2000053c .word 0x2000053c 08000f64 : /** * @brief This function handles UART4 global interrupt. */ void UART4_IRQHandler(void) { 8000f64: b580 push {r7, lr} 8000f66: af00 add r7, sp, #0 /* USER CODE BEGIN UART4_IRQn 0 */ /* USER CODE END UART4_IRQn 0 */ HAL_UART_IRQHandler(&huart4); 8000f68: 4802 ldr r0, [pc, #8] @ (8000f74 ) 8000f6a: f004 ff6f bl 8005e4c /* USER CODE BEGIN UART4_IRQn 1 */ /* USER CODE END UART4_IRQn 1 */ } 8000f6e: bf00 nop 8000f70: bd80 pop {r7, pc} 8000f72: bf00 nop 8000f74: 200002fc .word 0x200002fc 08000f78 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 8000f78: b580 push {r7, lr} 8000f7a: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 8000f7c: 4802 ldr r0, [pc, #8] @ (8000f88 ) 8000f7e: f004 ff65 bl 8005e4c /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 8000f82: bf00 nop 8000f84: bd80 pop {r7, pc} 8000f86: bf00 nop 8000f88: 20000344 .word 0x20000344 08000f8c : /** * @brief This function handles DMA2 stream2 global interrupt. */ void DMA2_Stream2_IRQHandler(void) { 8000f8c: b580 push {r7, lr} 8000f8e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ /* USER CODE END DMA2_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_rx); 8000f90: 4802 ldr r0, [pc, #8] @ (8000f9c ) 8000f92: f001 f84b bl 800202c /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ /* USER CODE END DMA2_Stream2_IRQn 1 */ } 8000f96: bf00 nop 8000f98: bd80 pop {r7, pc} 8000f9a: bf00 nop 8000f9c: 2000059c .word 0x2000059c 08000fa0 : /** * @brief This function handles USB On The Go FS global interrupt. */ void OTG_FS_IRQHandler(void) { 8000fa0: b580 push {r7, lr} 8000fa2: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_FS_IRQn 0 */ /* USER CODE END OTG_FS_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); 8000fa4: 4802 ldr r0, [pc, #8] @ (8000fb0 ) 8000fa6: f001 ff00 bl 8002daa /* USER CODE BEGIN OTG_FS_IRQn 1 */ /* USER CODE END OTG_FS_IRQn 1 */ } 8000faa: bf00 nop 8000fac: bd80 pop {r7, pc} 8000fae: bf00 nop 8000fb0: 20000c00 .word 0x20000c00 08000fb4 : /** * @brief This function handles DMA2 stream7 global interrupt. */ void DMA2_Stream7_IRQHandler(void) { 8000fb4: b580 push {r7, lr} 8000fb6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ /* USER CODE END DMA2_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 8000fb8: 4802 ldr r0, [pc, #8] @ (8000fc4 ) 8000fba: f001 f837 bl 800202c /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ /* USER CODE END DMA2_Stream7_IRQn 1 */ } 8000fbe: bf00 nop 8000fc0: bd80 pop {r7, pc} 8000fc2: bf00 nop 8000fc4: 200005fc .word 0x200005fc 08000fc8 : * configuration. * @param None * @retval None */ void SystemInit(void) { 8000fc8: b480 push {r7} 8000fca: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8000fcc: 4b06 ldr r3, [pc, #24] @ (8000fe8 ) 8000fce: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8000fd2: 4a05 ldr r2, [pc, #20] @ (8000fe8 ) 8000fd4: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8000fd8: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8000fdc: bf00 nop 8000fde: 46bd mov sp, r7 8000fe0: f85d 7b04 ldr.w r7, [sp], #4 8000fe4: 4770 bx lr 8000fe6: bf00 nop 8000fe8: e000ed00 .word 0xe000ed00 08000fec : TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; /* TIM2 init function */ void MX_TIM2_Init(void) { 8000fec: b580 push {r7, lr} 8000fee: b08a sub sp, #40 @ 0x28 8000ff0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000ff2: f107 0320 add.w r3, r7, #32 8000ff6: 2200 movs r2, #0 8000ff8: 601a str r2, [r3, #0] 8000ffa: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 8000ffc: 1d3b adds r3, r7, #4 8000ffe: 2200 movs r2, #0 8001000: 601a str r2, [r3, #0] 8001002: 605a str r2, [r3, #4] 8001004: 609a str r2, [r3, #8] 8001006: 60da str r2, [r3, #12] 8001008: 611a str r2, [r3, #16] 800100a: 615a str r2, [r3, #20] 800100c: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 800100e: 4b22 ldr r3, [pc, #136] @ (8001098 ) 8001010: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 8001014: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 8001016: 4b20 ldr r3, [pc, #128] @ (8001098 ) 8001018: 2200 movs r2, #0 800101a: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 800101c: 4b1e ldr r3, [pc, #120] @ (8001098 ) 800101e: 2200 movs r2, #0 8001020: 609a str r2, [r3, #8] htim2.Init.Period = 4294967295; 8001022: 4b1d ldr r3, [pc, #116] @ (8001098 ) 8001024: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8001028: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800102a: 4b1b ldr r3, [pc, #108] @ (8001098 ) 800102c: 2200 movs r2, #0 800102e: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001030: 4b19 ldr r3, [pc, #100] @ (8001098 ) 8001032: 2200 movs r2, #0 8001034: 619a str r2, [r3, #24] if (HAL_TIM_OC_Init(&htim2) != HAL_OK) 8001036: 4818 ldr r0, [pc, #96] @ (8001098 ) 8001038: f004 f904 bl 8005244 800103c: 4603 mov r3, r0 800103e: 2b00 cmp r3, #0 8001040: d001 beq.n 8001046 { Error_Handler(); 8001042: f7ff fee1 bl 8000e08 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001046: 2300 movs r3, #0 8001048: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800104a: 2300 movs r3, #0 800104c: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 800104e: f107 0320 add.w r3, r7, #32 8001052: 4619 mov r1, r3 8001054: 4810 ldr r0, [pc, #64] @ (8001098 ) 8001056: f004 fd8b bl 8005b70 800105a: 4603 mov r3, r0 800105c: 2b00 cmp r3, #0 800105e: d001 beq.n 8001064 { Error_Handler(); 8001060: f7ff fed2 bl 8000e08 } sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE; 8001064: 2350 movs r3, #80 @ 0x50 8001066: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 8001068: 2300 movs r3, #0 800106a: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800106c: 2300 movs r3, #0 800106e: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001070: 2300 movs r3, #0 8001072: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8001074: 1d3b adds r3, r7, #4 8001076: 2200 movs r2, #0 8001078: 4619 mov r1, r3 800107a: 4807 ldr r0, [pc, #28] @ (8001098 ) 800107c: f004 faa0 bl 80055c0 8001080: 4603 mov r3, r0 8001082: 2b00 cmp r3, #0 8001084: d001 beq.n 800108a { Error_Handler(); 8001086: f7ff febf bl 8000e08 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 800108a: 4803 ldr r0, [pc, #12] @ (8001098 ) 800108c: f000 f8c2 bl 8001214 } 8001090: bf00 nop 8001092: 3728 adds r7, #40 @ 0x28 8001094: 46bd mov sp, r7 8001096: bd80 pop {r7, pc} 8001098: 2000026c .word 0x2000026c 0800109c : /* TIM3 init function */ void MX_TIM3_Init(void) { 800109c: b580 push {r7, lr} 800109e: b08c sub sp, #48 @ 0x30 80010a0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_Encoder_InitTypeDef sConfig = {0}; 80010a2: f107 030c add.w r3, r7, #12 80010a6: 2224 movs r2, #36 @ 0x24 80010a8: 2100 movs r1, #0 80010aa: 4618 mov r0, r3 80010ac: f009 fd5a bl 800ab64 TIM_MasterConfigTypeDef sMasterConfig = {0}; 80010b0: 1d3b adds r3, r7, #4 80010b2: 2200 movs r2, #0 80010b4: 601a str r2, [r3, #0] 80010b6: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 80010b8: 4b20 ldr r3, [pc, #128] @ (800113c ) 80010ba: 4a21 ldr r2, [pc, #132] @ (8001140 ) 80010bc: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 80010be: 4b1f ldr r3, [pc, #124] @ (800113c ) 80010c0: 2200 movs r2, #0 80010c2: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 80010c4: 4b1d ldr r3, [pc, #116] @ (800113c ) 80010c6: 2200 movs r2, #0 80010c8: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 80010ca: 4b1c ldr r3, [pc, #112] @ (800113c ) 80010cc: f64f 72ff movw r2, #65535 @ 0xffff 80010d0: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80010d2: 4b1a ldr r3, [pc, #104] @ (800113c ) 80010d4: 2200 movs r2, #0 80010d6: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80010d8: 4b18 ldr r3, [pc, #96] @ (800113c ) 80010da: 2200 movs r2, #0 80010dc: 619a str r2, [r3, #24] sConfig.EncoderMode = TIM_ENCODERMODE_TI1; 80010de: 2301 movs r3, #1 80010e0: 60fb str r3, [r7, #12] sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; 80010e2: 2300 movs r3, #0 80010e4: 613b str r3, [r7, #16] sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; 80010e6: 2301 movs r3, #1 80010e8: 617b str r3, [r7, #20] sConfig.IC1Prescaler = TIM_ICPSC_DIV1; 80010ea: 2300 movs r3, #0 80010ec: 61bb str r3, [r7, #24] sConfig.IC1Filter = 0; 80010ee: 2300 movs r3, #0 80010f0: 61fb str r3, [r7, #28] sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; 80010f2: 2300 movs r3, #0 80010f4: 623b str r3, [r7, #32] sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; 80010f6: 2301 movs r3, #1 80010f8: 627b str r3, [r7, #36] @ 0x24 sConfig.IC2Prescaler = TIM_ICPSC_DIV1; 80010fa: 2300 movs r3, #0 80010fc: 62bb str r3, [r7, #40] @ 0x28 sConfig.IC2Filter = 0; 80010fe: 2300 movs r3, #0 8001100: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) 8001102: f107 030c add.w r3, r7, #12 8001106: 4619 mov r1, r3 8001108: 480c ldr r0, [pc, #48] @ (800113c ) 800110a: f004 f9b3 bl 8005474 800110e: 4603 mov r3, r0 8001110: 2b00 cmp r3, #0 8001112: d001 beq.n 8001118 { Error_Handler(); 8001114: f7ff fe78 bl 8000e08 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001118: 2300 movs r3, #0 800111a: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800111c: 2300 movs r3, #0 800111e: 60bb str r3, [r7, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8001120: 1d3b adds r3, r7, #4 8001122: 4619 mov r1, r3 8001124: 4805 ldr r0, [pc, #20] @ (800113c ) 8001126: f004 fd23 bl 8005b70 800112a: 4603 mov r3, r0 800112c: 2b00 cmp r3, #0 800112e: d001 beq.n 8001134 { Error_Handler(); 8001130: f7ff fe6a bl 8000e08 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8001134: bf00 nop 8001136: 3730 adds r7, #48 @ 0x30 8001138: 46bd mov sp, r7 800113a: bd80 pop {r7, pc} 800113c: 200002b4 .word 0x200002b4 8001140: 40000400 .word 0x40000400 08001144 : void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle) { 8001144: b480 push {r7} 8001146: b085 sub sp, #20 8001148: af00 add r7, sp, #0 800114a: 6078 str r0, [r7, #4] if(tim_ocHandle->Instance==TIM2) 800114c: 687b ldr r3, [r7, #4] 800114e: 681b ldr r3, [r3, #0] 8001150: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001154: d10d bne.n 8001172 { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* TIM2 clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 8001156: 2300 movs r3, #0 8001158: 60fb str r3, [r7, #12] 800115a: 4b09 ldr r3, [pc, #36] @ (8001180 ) 800115c: 6c1b ldr r3, [r3, #64] @ 0x40 800115e: 4a08 ldr r2, [pc, #32] @ (8001180 ) 8001160: f043 0301 orr.w r3, r3, #1 8001164: 6413 str r3, [r2, #64] @ 0x40 8001166: 4b06 ldr r3, [pc, #24] @ (8001180 ) 8001168: 6c1b ldr r3, [r3, #64] @ 0x40 800116a: f003 0301 and.w r3, r3, #1 800116e: 60fb str r3, [r7, #12] 8001170: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } } 8001172: bf00 nop 8001174: 3714 adds r7, #20 8001176: 46bd mov sp, r7 8001178: f85d 7b04 ldr.w r7, [sp], #4 800117c: 4770 bx lr 800117e: bf00 nop 8001180: 40023800 .word 0x40023800 08001184 : void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) { 8001184: b580 push {r7, lr} 8001186: b08a sub sp, #40 @ 0x28 8001188: af00 add r7, sp, #0 800118a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800118c: f107 0314 add.w r3, r7, #20 8001190: 2200 movs r2, #0 8001192: 601a str r2, [r3, #0] 8001194: 605a str r2, [r3, #4] 8001196: 609a str r2, [r3, #8] 8001198: 60da str r2, [r3, #12] 800119a: 611a str r2, [r3, #16] if(tim_encoderHandle->Instance==TIM3) 800119c: 687b ldr r3, [r7, #4] 800119e: 681b ldr r3, [r3, #0] 80011a0: 4a19 ldr r2, [pc, #100] @ (8001208 ) 80011a2: 4293 cmp r3, r2 80011a4: d12b bne.n 80011fe { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 80011a6: 2300 movs r3, #0 80011a8: 613b str r3, [r7, #16] 80011aa: 4b18 ldr r3, [pc, #96] @ (800120c ) 80011ac: 6c1b ldr r3, [r3, #64] @ 0x40 80011ae: 4a17 ldr r2, [pc, #92] @ (800120c ) 80011b0: f043 0302 orr.w r3, r3, #2 80011b4: 6413 str r3, [r2, #64] @ 0x40 80011b6: 4b15 ldr r3, [pc, #84] @ (800120c ) 80011b8: 6c1b ldr r3, [r3, #64] @ 0x40 80011ba: f003 0302 and.w r3, r3, #2 80011be: 613b str r3, [r7, #16] 80011c0: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80011c2: 2300 movs r3, #0 80011c4: 60fb str r3, [r7, #12] 80011c6: 4b11 ldr r3, [pc, #68] @ (800120c ) 80011c8: 6b1b ldr r3, [r3, #48] @ 0x30 80011ca: 4a10 ldr r2, [pc, #64] @ (800120c ) 80011cc: f043 0301 orr.w r3, r3, #1 80011d0: 6313 str r3, [r2, #48] @ 0x30 80011d2: 4b0e ldr r3, [pc, #56] @ (800120c ) 80011d4: 6b1b ldr r3, [r3, #48] @ 0x30 80011d6: f003 0301 and.w r3, r3, #1 80011da: 60fb str r3, [r7, #12] 80011dc: 68fb ldr r3, [r7, #12] /**TIM3 GPIO Configuration PA6 ------> TIM3_CH1 PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80011de: 23c0 movs r3, #192 @ 0xc0 80011e0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80011e2: 2302 movs r3, #2 80011e4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80011e6: 2300 movs r3, #0 80011e8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80011ea: 2300 movs r3, #0 80011ec: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 80011ee: 2302 movs r3, #2 80011f0: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80011f2: f107 0314 add.w r3, r7, #20 80011f6: 4619 mov r1, r3 80011f8: 4805 ldr r0, [pc, #20] @ (8001210 ) 80011fa: f001 f981 bl 8002500 /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 80011fe: bf00 nop 8001200: 3728 adds r7, #40 @ 0x28 8001202: 46bd mov sp, r7 8001204: bd80 pop {r7, pc} 8001206: bf00 nop 8001208: 40000400 .word 0x40000400 800120c: 40023800 .word 0x40023800 8001210: 40020000 .word 0x40020000 08001214 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 8001214: b580 push {r7, lr} 8001216: b088 sub sp, #32 8001218: af00 add r7, sp, #0 800121a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800121c: f107 030c add.w r3, r7, #12 8001220: 2200 movs r2, #0 8001222: 601a str r2, [r3, #0] 8001224: 605a str r2, [r3, #4] 8001226: 609a str r2, [r3, #8] 8001228: 60da str r2, [r3, #12] 800122a: 611a str r2, [r3, #16] if(timHandle->Instance==TIM2) 800122c: 687b ldr r3, [r7, #4] 800122e: 681b ldr r3, [r3, #0] 8001230: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001234: d11d bne.n 8001272 { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8001236: 2300 movs r3, #0 8001238: 60bb str r3, [r7, #8] 800123a: 4b10 ldr r3, [pc, #64] @ (800127c ) 800123c: 6b1b ldr r3, [r3, #48] @ 0x30 800123e: 4a0f ldr r2, [pc, #60] @ (800127c ) 8001240: f043 0301 orr.w r3, r3, #1 8001244: 6313 str r3, [r2, #48] @ 0x30 8001246: 4b0d ldr r3, [pc, #52] @ (800127c ) 8001248: 6b1b ldr r3, [r3, #48] @ 0x30 800124a: f003 0301 and.w r3, r3, #1 800124e: 60bb str r3, [r7, #8] 8001250: 68bb ldr r3, [r7, #8] /**TIM2 GPIO Configuration PA5 ------> TIM2_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_5; 8001252: 2320 movs r3, #32 8001254: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001256: 2302 movs r3, #2 8001258: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800125a: 2300 movs r3, #0 800125c: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800125e: 2300 movs r3, #0 8001260: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 8001262: 2301 movs r3, #1 8001264: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001266: f107 030c add.w r3, r7, #12 800126a: 4619 mov r1, r3 800126c: 4804 ldr r0, [pc, #16] @ (8001280 ) 800126e: f001 f947 bl 8002500 /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8001272: bf00 nop 8001274: 3720 adds r7, #32 8001276: 46bd mov sp, r7 8001278: bd80 pop {r7, pc} 800127a: bf00 nop 800127c: 40023800 .word 0x40023800 8001280: 40020000 .word 0x40020000 08001284 : DMA_HandleTypeDef hdma_usart2_rx; DMA_HandleTypeDef hdma_usart2_tx; /* UART4 init function */ void MX_UART4_Init(void) { 8001284: b580 push {r7, lr} 8001286: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; 8001288: 4b11 ldr r3, [pc, #68] @ (80012d0 ) 800128a: 4a12 ldr r2, [pc, #72] @ (80012d4 ) 800128c: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; 800128e: 4b10 ldr r3, [pc, #64] @ (80012d0 ) 8001290: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001294: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; 8001296: 4b0e ldr r3, [pc, #56] @ (80012d0 ) 8001298: 2200 movs r2, #0 800129a: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; 800129c: 4b0c ldr r3, [pc, #48] @ (80012d0 ) 800129e: 2200 movs r2, #0 80012a0: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; 80012a2: 4b0b ldr r3, [pc, #44] @ (80012d0 ) 80012a4: 2200 movs r2, #0 80012a6: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; 80012a8: 4b09 ldr r3, [pc, #36] @ (80012d0 ) 80012aa: 220c movs r2, #12 80012ac: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80012ae: 4b08 ldr r3, [pc, #32] @ (80012d0 ) 80012b0: 2200 movs r2, #0 80012b2: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; 80012b4: 4b06 ldr r3, [pc, #24] @ (80012d0 ) 80012b6: 2200 movs r2, #0 80012b8: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart4) != HAL_OK) 80012ba: 4805 ldr r0, [pc, #20] @ (80012d0 ) 80012bc: f004 fcd4 bl 8005c68 80012c0: 4603 mov r3, r0 80012c2: 2b00 cmp r3, #0 80012c4: d001 beq.n 80012ca { Error_Handler(); 80012c6: f7ff fd9f bl 8000e08 } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } 80012ca: bf00 nop 80012cc: bd80 pop {r7, pc} 80012ce: bf00 nop 80012d0: 200002fc .word 0x200002fc 80012d4: 40004c00 .word 0x40004c00 080012d8 : /* UART5 init function */ void MX_UART5_Init(void) { 80012d8: b580 push {r7, lr} 80012da: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 80012dc: 4b11 ldr r3, [pc, #68] @ (8001324 ) 80012de: 4a12 ldr r2, [pc, #72] @ (8001328 ) 80012e0: 601a str r2, [r3, #0] huart5.Init.BaudRate = 115200; 80012e2: 4b10 ldr r3, [pc, #64] @ (8001324 ) 80012e4: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80012e8: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 80012ea: 4b0e ldr r3, [pc, #56] @ (8001324 ) 80012ec: 2200 movs r2, #0 80012ee: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 80012f0: 4b0c ldr r3, [pc, #48] @ (8001324 ) 80012f2: 2200 movs r2, #0 80012f4: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 80012f6: 4b0b ldr r3, [pc, #44] @ (8001324 ) 80012f8: 2200 movs r2, #0 80012fa: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 80012fc: 4b09 ldr r3, [pc, #36] @ (8001324 ) 80012fe: 220c movs r2, #12 8001300: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001302: 4b08 ldr r3, [pc, #32] @ (8001324 ) 8001304: 2200 movs r2, #0 8001306: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 8001308: 4b06 ldr r3, [pc, #24] @ (8001324 ) 800130a: 2200 movs r2, #0 800130c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800130e: 4805 ldr r0, [pc, #20] @ (8001324 ) 8001310: f004 fcaa bl 8005c68 8001314: 4603 mov r3, r0 8001316: 2b00 cmp r3, #0 8001318: d001 beq.n 800131e { Error_Handler(); 800131a: f7ff fd75 bl 8000e08 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800131e: bf00 nop 8001320: bd80 pop {r7, pc} 8001322: bf00 nop 8001324: 20000344 .word 0x20000344 8001328: 40005000 .word 0x40005000 0800132c : /* USART1 init function */ void MX_USART1_UART_Init(void) { 800132c: b580 push {r7, lr} 800132e: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8001330: 4b11 ldr r3, [pc, #68] @ (8001378 ) 8001332: 4a12 ldr r2, [pc, #72] @ (800137c ) 8001334: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8001336: 4b10 ldr r3, [pc, #64] @ (8001378 ) 8001338: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800133c: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800133e: 4b0e ldr r3, [pc, #56] @ (8001378 ) 8001340: 2200 movs r2, #0 8001342: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8001344: 4b0c ldr r3, [pc, #48] @ (8001378 ) 8001346: 2200 movs r2, #0 8001348: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800134a: 4b0b ldr r3, [pc, #44] @ (8001378 ) 800134c: 2200 movs r2, #0 800134e: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001350: 4b09 ldr r3, [pc, #36] @ (8001378 ) 8001352: 220c movs r2, #12 8001354: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001356: 4b08 ldr r3, [pc, #32] @ (8001378 ) 8001358: 2200 movs r2, #0 800135a: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800135c: 4b06 ldr r3, [pc, #24] @ (8001378 ) 800135e: 2200 movs r2, #0 8001360: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8001362: 4805 ldr r0, [pc, #20] @ (8001378 ) 8001364: f004 fc80 bl 8005c68 8001368: 4603 mov r3, r0 800136a: 2b00 cmp r3, #0 800136c: d001 beq.n 8001372 { Error_Handler(); 800136e: f7ff fd4b bl 8000e08 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8001372: bf00 nop 8001374: bd80 pop {r7, pc} 8001376: bf00 nop 8001378: 2000038c .word 0x2000038c 800137c: 40011000 .word 0x40011000 08001380 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 8001380: b580 push {r7, lr} 8001382: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8001384: 4b11 ldr r3, [pc, #68] @ (80013cc ) 8001386: 4a12 ldr r2, [pc, #72] @ (80013d0 ) 8001388: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800138a: 4b10 ldr r3, [pc, #64] @ (80013cc ) 800138c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001390: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8001392: 4b0e ldr r3, [pc, #56] @ (80013cc ) 8001394: 2200 movs r2, #0 8001396: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8001398: 4b0c ldr r3, [pc, #48] @ (80013cc ) 800139a: 2200 movs r2, #0 800139c: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800139e: 4b0b ldr r3, [pc, #44] @ (80013cc ) 80013a0: 2200 movs r2, #0 80013a2: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 80013a4: 4b09 ldr r3, [pc, #36] @ (80013cc ) 80013a6: 220c movs r2, #12 80013a8: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80013aa: 4b08 ldr r3, [pc, #32] @ (80013cc ) 80013ac: 2200 movs r2, #0 80013ae: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 80013b0: 4b06 ldr r3, [pc, #24] @ (80013cc ) 80013b2: 2200 movs r2, #0 80013b4: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 80013b6: 4805 ldr r0, [pc, #20] @ (80013cc ) 80013b8: f004 fc56 bl 8005c68 80013bc: 4603 mov r3, r0 80013be: 2b00 cmp r3, #0 80013c0: d001 beq.n 80013c6 { Error_Handler(); 80013c2: f7ff fd21 bl 8000e08 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 80013c6: bf00 nop 80013c8: bd80 pop {r7, pc} 80013ca: bf00 nop 80013cc: 200003d4 .word 0x200003d4 80013d0: 40004400 .word 0x40004400 080013d4 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 80013d4: b580 push {r7, lr} 80013d6: b090 sub sp, #64 @ 0x40 80013d8: af00 add r7, sp, #0 80013da: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80013dc: f107 032c add.w r3, r7, #44 @ 0x2c 80013e0: 2200 movs r2, #0 80013e2: 601a str r2, [r3, #0] 80013e4: 605a str r2, [r3, #4] 80013e6: 609a str r2, [r3, #8] 80013e8: 60da str r2, [r3, #12] 80013ea: 611a str r2, [r3, #16] if(uartHandle->Instance==UART4) 80013ec: 687b ldr r3, [r7, #4] 80013ee: 681b ldr r3, [r3, #0] 80013f0: 4a4a ldr r2, [pc, #296] @ (800151c ) 80013f2: 4293 cmp r3, r2 80013f4: f040 80a0 bne.w 8001538 { /* USER CODE BEGIN UART4_MspInit 0 */ /* USER CODE END UART4_MspInit 0 */ /* UART4 clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); 80013f8: 2300 movs r3, #0 80013fa: 62bb str r3, [r7, #40] @ 0x28 80013fc: 4b48 ldr r3, [pc, #288] @ (8001520 ) 80013fe: 6c1b ldr r3, [r3, #64] @ 0x40 8001400: 4a47 ldr r2, [pc, #284] @ (8001520 ) 8001402: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8001406: 6413 str r3, [r2, #64] @ 0x40 8001408: 4b45 ldr r3, [pc, #276] @ (8001520 ) 800140a: 6c1b ldr r3, [r3, #64] @ 0x40 800140c: f403 2300 and.w r3, r3, #524288 @ 0x80000 8001410: 62bb str r3, [r7, #40] @ 0x28 8001412: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOA_CLK_ENABLE(); 8001414: 2300 movs r3, #0 8001416: 627b str r3, [r7, #36] @ 0x24 8001418: 4b41 ldr r3, [pc, #260] @ (8001520 ) 800141a: 6b1b ldr r3, [r3, #48] @ 0x30 800141c: 4a40 ldr r2, [pc, #256] @ (8001520 ) 800141e: f043 0301 orr.w r3, r3, #1 8001422: 6313 str r3, [r2, #48] @ 0x30 8001424: 4b3e ldr r3, [pc, #248] @ (8001520 ) 8001426: 6b1b ldr r3, [r3, #48] @ 0x30 8001428: f003 0301 and.w r3, r3, #1 800142c: 627b str r3, [r7, #36] @ 0x24 800142e: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART4 GPIO Configuration PA0-WKUP ------> UART4_TX PA1 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8001430: 2303 movs r3, #3 8001432: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001434: 2302 movs r3, #2 8001436: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001438: 2300 movs r3, #0 800143a: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800143c: 2303 movs r3, #3 800143e: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 8001440: 2308 movs r3, #8 8001442: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001444: f107 032c add.w r3, r7, #44 @ 0x2c 8001448: 4619 mov r1, r3 800144a: 4836 ldr r0, [pc, #216] @ (8001524 ) 800144c: f001 f858 bl 8002500 /* UART4 DMA Init */ /* UART4_RX Init */ hdma_uart4_rx.Instance = DMA1_Stream2; 8001450: 4b35 ldr r3, [pc, #212] @ (8001528 ) 8001452: 4a36 ldr r2, [pc, #216] @ (800152c ) 8001454: 601a str r2, [r3, #0] hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4; 8001456: 4b34 ldr r3, [pc, #208] @ (8001528 ) 8001458: f04f 6200 mov.w r2, #134217728 @ 0x8000000 800145c: 605a str r2, [r3, #4] hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800145e: 4b32 ldr r3, [pc, #200] @ (8001528 ) 8001460: 2200 movs r2, #0 8001462: 609a str r2, [r3, #8] hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001464: 4b30 ldr r3, [pc, #192] @ (8001528 ) 8001466: 2200 movs r2, #0 8001468: 60da str r2, [r3, #12] hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE; 800146a: 4b2f ldr r3, [pc, #188] @ (8001528 ) 800146c: f44f 6280 mov.w r2, #1024 @ 0x400 8001470: 611a str r2, [r3, #16] hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001472: 4b2d ldr r3, [pc, #180] @ (8001528 ) 8001474: 2200 movs r2, #0 8001476: 615a str r2, [r3, #20] hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001478: 4b2b ldr r3, [pc, #172] @ (8001528 ) 800147a: 2200 movs r2, #0 800147c: 619a str r2, [r3, #24] hdma_uart4_rx.Init.Mode = DMA_NORMAL; 800147e: 4b2a ldr r3, [pc, #168] @ (8001528 ) 8001480: 2200 movs r2, #0 8001482: 61da str r2, [r3, #28] hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW; 8001484: 4b28 ldr r3, [pc, #160] @ (8001528 ) 8001486: 2200 movs r2, #0 8001488: 621a str r2, [r3, #32] hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800148a: 4b27 ldr r3, [pc, #156] @ (8001528 ) 800148c: 2200 movs r2, #0 800148e: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK) 8001490: 4825 ldr r0, [pc, #148] @ (8001528 ) 8001492: f000 fc33 bl 8001cfc 8001496: 4603 mov r3, r0 8001498: 2b00 cmp r3, #0 800149a: d001 beq.n 80014a0 { Error_Handler(); 800149c: f7ff fcb4 bl 8000e08 } __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx); 80014a0: 687b ldr r3, [r7, #4] 80014a2: 4a21 ldr r2, [pc, #132] @ (8001528 ) 80014a4: 63da str r2, [r3, #60] @ 0x3c 80014a6: 4a20 ldr r2, [pc, #128] @ (8001528 ) 80014a8: 687b ldr r3, [r7, #4] 80014aa: 6393 str r3, [r2, #56] @ 0x38 /* UART4_TX Init */ hdma_uart4_tx.Instance = DMA1_Stream4; 80014ac: 4b20 ldr r3, [pc, #128] @ (8001530 ) 80014ae: 4a21 ldr r2, [pc, #132] @ (8001534 ) 80014b0: 601a str r2, [r3, #0] hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4; 80014b2: 4b1f ldr r3, [pc, #124] @ (8001530 ) 80014b4: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80014b8: 605a str r2, [r3, #4] hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80014ba: 4b1d ldr r3, [pc, #116] @ (8001530 ) 80014bc: 2240 movs r2, #64 @ 0x40 80014be: 609a str r2, [r3, #8] hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE; 80014c0: 4b1b ldr r3, [pc, #108] @ (8001530 ) 80014c2: 2200 movs r2, #0 80014c4: 60da str r2, [r3, #12] hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE; 80014c6: 4b1a ldr r3, [pc, #104] @ (8001530 ) 80014c8: f44f 6280 mov.w r2, #1024 @ 0x400 80014cc: 611a str r2, [r3, #16] hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80014ce: 4b18 ldr r3, [pc, #96] @ (8001530 ) 80014d0: 2200 movs r2, #0 80014d2: 615a str r2, [r3, #20] hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80014d4: 4b16 ldr r3, [pc, #88] @ (8001530 ) 80014d6: 2200 movs r2, #0 80014d8: 619a str r2, [r3, #24] hdma_uart4_tx.Init.Mode = DMA_NORMAL; 80014da: 4b15 ldr r3, [pc, #84] @ (8001530 ) 80014dc: 2200 movs r2, #0 80014de: 61da str r2, [r3, #28] hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW; 80014e0: 4b13 ldr r3, [pc, #76] @ (8001530 ) 80014e2: 2200 movs r2, #0 80014e4: 621a str r2, [r3, #32] hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80014e6: 4b12 ldr r3, [pc, #72] @ (8001530 ) 80014e8: 2200 movs r2, #0 80014ea: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK) 80014ec: 4810 ldr r0, [pc, #64] @ (8001530 ) 80014ee: f000 fc05 bl 8001cfc 80014f2: 4603 mov r3, r0 80014f4: 2b00 cmp r3, #0 80014f6: d001 beq.n 80014fc { Error_Handler(); 80014f8: f7ff fc86 bl 8000e08 } __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); 80014fc: 687b ldr r3, [r7, #4] 80014fe: 4a0c ldr r2, [pc, #48] @ (8001530 ) 8001500: 639a str r2, [r3, #56] @ 0x38 8001502: 4a0b ldr r2, [pc, #44] @ (8001530 ) 8001504: 687b ldr r3, [r7, #4] 8001506: 6393 str r3, [r2, #56] @ 0x38 /* UART4 interrupt Init */ HAL_NVIC_SetPriority(UART4_IRQn, 0, 0); 8001508: 2200 movs r2, #0 800150a: 2100 movs r1, #0 800150c: 2034 movs r0, #52 @ 0x34 800150e: f000 fbbe bl 8001c8e HAL_NVIC_EnableIRQ(UART4_IRQn); 8001512: 2034 movs r0, #52 @ 0x34 8001514: f000 fbd7 bl 8001cc6 HAL_NVIC_EnableIRQ(USART2_IRQn); /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8001518: e202 b.n 8001920 800151a: bf00 nop 800151c: 40004c00 .word 0x40004c00 8001520: 40023800 .word 0x40023800 8001524: 40020000 .word 0x40020000 8001528: 2000041c .word 0x2000041c 800152c: 40026040 .word 0x40026040 8001530: 2000047c .word 0x2000047c 8001534: 40026070 .word 0x40026070 else if(uartHandle->Instance==UART5) 8001538: 687b ldr r3, [r7, #4] 800153a: 681b ldr r3, [r3, #0] 800153c: 4a59 ldr r2, [pc, #356] @ (80016a4 ) 800153e: 4293 cmp r3, r2 8001540: f040 80c0 bne.w 80016c4 __HAL_RCC_UART5_CLK_ENABLE(); 8001544: 2300 movs r3, #0 8001546: 623b str r3, [r7, #32] 8001548: 4b57 ldr r3, [pc, #348] @ (80016a8 ) 800154a: 6c1b ldr r3, [r3, #64] @ 0x40 800154c: 4a56 ldr r2, [pc, #344] @ (80016a8 ) 800154e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8001552: 6413 str r3, [r2, #64] @ 0x40 8001554: 4b54 ldr r3, [pc, #336] @ (80016a8 ) 8001556: 6c1b ldr r3, [r3, #64] @ 0x40 8001558: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800155c: 623b str r3, [r7, #32] 800155e: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001560: 2300 movs r3, #0 8001562: 61fb str r3, [r7, #28] 8001564: 4b50 ldr r3, [pc, #320] @ (80016a8 ) 8001566: 6b1b ldr r3, [r3, #48] @ 0x30 8001568: 4a4f ldr r2, [pc, #316] @ (80016a8 ) 800156a: f043 0304 orr.w r3, r3, #4 800156e: 6313 str r3, [r2, #48] @ 0x30 8001570: 4b4d ldr r3, [pc, #308] @ (80016a8 ) 8001572: 6b1b ldr r3, [r3, #48] @ 0x30 8001574: f003 0304 and.w r3, r3, #4 8001578: 61fb str r3, [r7, #28] 800157a: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOD_CLK_ENABLE(); 800157c: 2300 movs r3, #0 800157e: 61bb str r3, [r7, #24] 8001580: 4b49 ldr r3, [pc, #292] @ (80016a8 ) 8001582: 6b1b ldr r3, [r3, #48] @ 0x30 8001584: 4a48 ldr r2, [pc, #288] @ (80016a8 ) 8001586: f043 0308 orr.w r3, r3, #8 800158a: 6313 str r3, [r2, #48] @ 0x30 800158c: 4b46 ldr r3, [pc, #280] @ (80016a8 ) 800158e: 6b1b ldr r3, [r3, #48] @ 0x30 8001590: f003 0308 and.w r3, r3, #8 8001594: 61bb str r3, [r7, #24] 8001596: 69bb ldr r3, [r7, #24] GPIO_InitStruct.Pin = GPIO_PIN_12; 8001598: f44f 5380 mov.w r3, #4096 @ 0x1000 800159c: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800159e: 2302 movs r3, #2 80015a0: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80015a2: 2300 movs r3, #0 80015a4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80015a6: 2303 movs r3, #3 80015a8: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 80015aa: 2308 movs r3, #8 80015ac: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80015ae: f107 032c add.w r3, r7, #44 @ 0x2c 80015b2: 4619 mov r1, r3 80015b4: 483d ldr r0, [pc, #244] @ (80016ac ) 80015b6: f000 ffa3 bl 8002500 GPIO_InitStruct.Pin = GPIO_PIN_2; 80015ba: 2304 movs r3, #4 80015bc: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80015be: 2302 movs r3, #2 80015c0: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80015c2: 2300 movs r3, #0 80015c4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80015c6: 2303 movs r3, #3 80015c8: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 80015ca: 2308 movs r3, #8 80015cc: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80015ce: f107 032c add.w r3, r7, #44 @ 0x2c 80015d2: 4619 mov r1, r3 80015d4: 4836 ldr r0, [pc, #216] @ (80016b0 ) 80015d6: f000 ff93 bl 8002500 hdma_uart5_rx.Instance = DMA1_Stream0; 80015da: 4b36 ldr r3, [pc, #216] @ (80016b4 ) 80015dc: 4a36 ldr r2, [pc, #216] @ (80016b8 ) 80015de: 601a str r2, [r3, #0] hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4; 80015e0: 4b34 ldr r3, [pc, #208] @ (80016b4 ) 80015e2: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80015e6: 605a str r2, [r3, #4] hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80015e8: 4b32 ldr r3, [pc, #200] @ (80016b4 ) 80015ea: 2200 movs r2, #0 80015ec: 609a str r2, [r3, #8] hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE; 80015ee: 4b31 ldr r3, [pc, #196] @ (80016b4 ) 80015f0: 2200 movs r2, #0 80015f2: 60da str r2, [r3, #12] hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE; 80015f4: 4b2f ldr r3, [pc, #188] @ (80016b4 ) 80015f6: f44f 6280 mov.w r2, #1024 @ 0x400 80015fa: 611a str r2, [r3, #16] hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80015fc: 4b2d ldr r3, [pc, #180] @ (80016b4 ) 80015fe: 2200 movs r2, #0 8001600: 615a str r2, [r3, #20] hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001602: 4b2c ldr r3, [pc, #176] @ (80016b4 ) 8001604: 2200 movs r2, #0 8001606: 619a str r2, [r3, #24] hdma_uart5_rx.Init.Mode = DMA_NORMAL; 8001608: 4b2a ldr r3, [pc, #168] @ (80016b4 ) 800160a: 2200 movs r2, #0 800160c: 61da str r2, [r3, #28] hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; 800160e: 4b29 ldr r3, [pc, #164] @ (80016b4 ) 8001610: 2200 movs r2, #0 8001612: 621a str r2, [r3, #32] hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001614: 4b27 ldr r3, [pc, #156] @ (80016b4 ) 8001616: 2200 movs r2, #0 8001618: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) 800161a: 4826 ldr r0, [pc, #152] @ (80016b4 ) 800161c: f000 fb6e bl 8001cfc 8001620: 4603 mov r3, r0 8001622: 2b00 cmp r3, #0 8001624: d001 beq.n 800162a Error_Handler(); 8001626: f7ff fbef bl 8000e08 __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx); 800162a: 687b ldr r3, [r7, #4] 800162c: 4a21 ldr r2, [pc, #132] @ (80016b4 ) 800162e: 63da str r2, [r3, #60] @ 0x3c 8001630: 4a20 ldr r2, [pc, #128] @ (80016b4 ) 8001632: 687b ldr r3, [r7, #4] 8001634: 6393 str r3, [r2, #56] @ 0x38 hdma_uart5_tx.Instance = DMA1_Stream7; 8001636: 4b21 ldr r3, [pc, #132] @ (80016bc ) 8001638: 4a21 ldr r2, [pc, #132] @ (80016c0 ) 800163a: 601a str r2, [r3, #0] hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4; 800163c: 4b1f ldr r3, [pc, #124] @ (80016bc ) 800163e: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001642: 605a str r2, [r3, #4] hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001644: 4b1d ldr r3, [pc, #116] @ (80016bc ) 8001646: 2240 movs r2, #64 @ 0x40 8001648: 609a str r2, [r3, #8] hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800164a: 4b1c ldr r3, [pc, #112] @ (80016bc ) 800164c: 2200 movs r2, #0 800164e: 60da str r2, [r3, #12] hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE; 8001650: 4b1a ldr r3, [pc, #104] @ (80016bc ) 8001652: f44f 6280 mov.w r2, #1024 @ 0x400 8001656: 611a str r2, [r3, #16] hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001658: 4b18 ldr r3, [pc, #96] @ (80016bc ) 800165a: 2200 movs r2, #0 800165c: 615a str r2, [r3, #20] hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800165e: 4b17 ldr r3, [pc, #92] @ (80016bc ) 8001660: 2200 movs r2, #0 8001662: 619a str r2, [r3, #24] hdma_uart5_tx.Init.Mode = DMA_NORMAL; 8001664: 4b15 ldr r3, [pc, #84] @ (80016bc ) 8001666: 2200 movs r2, #0 8001668: 61da str r2, [r3, #28] hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; 800166a: 4b14 ldr r3, [pc, #80] @ (80016bc ) 800166c: 2200 movs r2, #0 800166e: 621a str r2, [r3, #32] hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001670: 4b12 ldr r3, [pc, #72] @ (80016bc ) 8001672: 2200 movs r2, #0 8001674: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) 8001676: 4811 ldr r0, [pc, #68] @ (80016bc ) 8001678: f000 fb40 bl 8001cfc 800167c: 4603 mov r3, r0 800167e: 2b00 cmp r3, #0 8001680: d001 beq.n 8001686 Error_Handler(); 8001682: f7ff fbc1 bl 8000e08 __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); 8001686: 687b ldr r3, [r7, #4] 8001688: 4a0c ldr r2, [pc, #48] @ (80016bc ) 800168a: 639a str r2, [r3, #56] @ 0x38 800168c: 4a0b ldr r2, [pc, #44] @ (80016bc ) 800168e: 687b ldr r3, [r7, #4] 8001690: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(UART5_IRQn, 0, 0); 8001692: 2200 movs r2, #0 8001694: 2100 movs r1, #0 8001696: 2035 movs r0, #53 @ 0x35 8001698: f000 faf9 bl 8001c8e HAL_NVIC_EnableIRQ(UART5_IRQn); 800169c: 2035 movs r0, #53 @ 0x35 800169e: f000 fb12 bl 8001cc6 } 80016a2: e13d b.n 8001920 80016a4: 40005000 .word 0x40005000 80016a8: 40023800 .word 0x40023800 80016ac: 40020800 .word 0x40020800 80016b0: 40020c00 .word 0x40020c00 80016b4: 200004dc .word 0x200004dc 80016b8: 40026010 .word 0x40026010 80016bc: 2000053c .word 0x2000053c 80016c0: 400260b8 .word 0x400260b8 else if(uartHandle->Instance==USART1) 80016c4: 687b ldr r3, [r7, #4] 80016c6: 681b ldr r3, [r3, #0] 80016c8: 4a97 ldr r2, [pc, #604] @ (8001928 ) 80016ca: 4293 cmp r3, r2 80016cc: f040 8092 bne.w 80017f4 __HAL_RCC_USART1_CLK_ENABLE(); 80016d0: 2300 movs r3, #0 80016d2: 617b str r3, [r7, #20] 80016d4: 4b95 ldr r3, [pc, #596] @ (800192c ) 80016d6: 6c5b ldr r3, [r3, #68] @ 0x44 80016d8: 4a94 ldr r2, [pc, #592] @ (800192c ) 80016da: f043 0310 orr.w r3, r3, #16 80016de: 6453 str r3, [r2, #68] @ 0x44 80016e0: 4b92 ldr r3, [pc, #584] @ (800192c ) 80016e2: 6c5b ldr r3, [r3, #68] @ 0x44 80016e4: f003 0310 and.w r3, r3, #16 80016e8: 617b str r3, [r7, #20] 80016ea: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80016ec: 2300 movs r3, #0 80016ee: 613b str r3, [r7, #16] 80016f0: 4b8e ldr r3, [pc, #568] @ (800192c ) 80016f2: 6b1b ldr r3, [r3, #48] @ 0x30 80016f4: 4a8d ldr r2, [pc, #564] @ (800192c ) 80016f6: f043 0301 orr.w r3, r3, #1 80016fa: 6313 str r3, [r2, #48] @ 0x30 80016fc: 4b8b ldr r3, [pc, #556] @ (800192c ) 80016fe: 6b1b ldr r3, [r3, #48] @ 0x30 8001700: f003 0301 and.w r3, r3, #1 8001704: 613b str r3, [r7, #16] 8001706: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 8001708: f44f 63c0 mov.w r3, #1536 @ 0x600 800170c: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800170e: 2302 movs r3, #2 8001710: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001712: 2300 movs r3, #0 8001714: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001716: 2303 movs r3, #3 8001718: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 800171a: 2307 movs r3, #7 800171c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800171e: f107 032c add.w r3, r7, #44 @ 0x2c 8001722: 4619 mov r1, r3 8001724: 4882 ldr r0, [pc, #520] @ (8001930 ) 8001726: f000 feeb bl 8002500 hdma_usart1_rx.Instance = DMA2_Stream2; 800172a: 4b82 ldr r3, [pc, #520] @ (8001934 ) 800172c: 4a82 ldr r2, [pc, #520] @ (8001938 ) 800172e: 601a str r2, [r3, #0] hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; 8001730: 4b80 ldr r3, [pc, #512] @ (8001934 ) 8001732: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001736: 605a str r2, [r3, #4] hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001738: 4b7e ldr r3, [pc, #504] @ (8001934 ) 800173a: 2200 movs r2, #0 800173c: 609a str r2, [r3, #8] hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800173e: 4b7d ldr r3, [pc, #500] @ (8001934 ) 8001740: 2200 movs r2, #0 8001742: 60da str r2, [r3, #12] hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 8001744: 4b7b ldr r3, [pc, #492] @ (8001934 ) 8001746: f44f 6280 mov.w r2, #1024 @ 0x400 800174a: 611a str r2, [r3, #16] hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800174c: 4b79 ldr r3, [pc, #484] @ (8001934 ) 800174e: 2200 movs r2, #0 8001750: 615a str r2, [r3, #20] hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001752: 4b78 ldr r3, [pc, #480] @ (8001934 ) 8001754: 2200 movs r2, #0 8001756: 619a str r2, [r3, #24] hdma_usart1_rx.Init.Mode = DMA_NORMAL; 8001758: 4b76 ldr r3, [pc, #472] @ (8001934 ) 800175a: 2200 movs r2, #0 800175c: 61da str r2, [r3, #28] hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; 800175e: 4b75 ldr r3, [pc, #468] @ (8001934 ) 8001760: 2200 movs r2, #0 8001762: 621a str r2, [r3, #32] hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001764: 4b73 ldr r3, [pc, #460] @ (8001934 ) 8001766: 2200 movs r2, #0 8001768: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 800176a: 4872 ldr r0, [pc, #456] @ (8001934 ) 800176c: f000 fac6 bl 8001cfc 8001770: 4603 mov r3, r0 8001772: 2b00 cmp r3, #0 8001774: d001 beq.n 800177a Error_Handler(); 8001776: f7ff fb47 bl 8000e08 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); 800177a: 687b ldr r3, [r7, #4] 800177c: 4a6d ldr r2, [pc, #436] @ (8001934 ) 800177e: 63da str r2, [r3, #60] @ 0x3c 8001780: 4a6c ldr r2, [pc, #432] @ (8001934 ) 8001782: 687b ldr r3, [r7, #4] 8001784: 6393 str r3, [r2, #56] @ 0x38 hdma_usart1_tx.Instance = DMA2_Stream7; 8001786: 4b6d ldr r3, [pc, #436] @ (800193c ) 8001788: 4a6d ldr r2, [pc, #436] @ (8001940 ) 800178a: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; 800178c: 4b6b ldr r3, [pc, #428] @ (800193c ) 800178e: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001792: 605a str r2, [r3, #4] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001794: 4b69 ldr r3, [pc, #420] @ (800193c ) 8001796: 2240 movs r2, #64 @ 0x40 8001798: 609a str r2, [r3, #8] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800179a: 4b68 ldr r3, [pc, #416] @ (800193c ) 800179c: 2200 movs r2, #0 800179e: 60da str r2, [r3, #12] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 80017a0: 4b66 ldr r3, [pc, #408] @ (800193c ) 80017a2: f44f 6280 mov.w r2, #1024 @ 0x400 80017a6: 611a str r2, [r3, #16] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80017a8: 4b64 ldr r3, [pc, #400] @ (800193c ) 80017aa: 2200 movs r2, #0 80017ac: 615a str r2, [r3, #20] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80017ae: 4b63 ldr r3, [pc, #396] @ (800193c ) 80017b0: 2200 movs r2, #0 80017b2: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 80017b4: 4b61 ldr r3, [pc, #388] @ (800193c ) 80017b6: 2200 movs r2, #0 80017b8: 61da str r2, [r3, #28] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 80017ba: 4b60 ldr r3, [pc, #384] @ (800193c ) 80017bc: 2200 movs r2, #0 80017be: 621a str r2, [r3, #32] hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80017c0: 4b5e ldr r3, [pc, #376] @ (800193c ) 80017c2: 2200 movs r2, #0 80017c4: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 80017c6: 485d ldr r0, [pc, #372] @ (800193c ) 80017c8: f000 fa98 bl 8001cfc 80017cc: 4603 mov r3, r0 80017ce: 2b00 cmp r3, #0 80017d0: d001 beq.n 80017d6 Error_Handler(); 80017d2: f7ff fb19 bl 8000e08 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); 80017d6: 687b ldr r3, [r7, #4] 80017d8: 4a58 ldr r2, [pc, #352] @ (800193c ) 80017da: 639a str r2, [r3, #56] @ 0x38 80017dc: 4a57 ldr r2, [pc, #348] @ (800193c ) 80017de: 687b ldr r3, [r7, #4] 80017e0: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 80017e2: 2200 movs r2, #0 80017e4: 2100 movs r1, #0 80017e6: 2025 movs r0, #37 @ 0x25 80017e8: f000 fa51 bl 8001c8e HAL_NVIC_EnableIRQ(USART1_IRQn); 80017ec: 2025 movs r0, #37 @ 0x25 80017ee: f000 fa6a bl 8001cc6 } 80017f2: e095 b.n 8001920 else if(uartHandle->Instance==USART2) 80017f4: 687b ldr r3, [r7, #4] 80017f6: 681b ldr r3, [r3, #0] 80017f8: 4a52 ldr r2, [pc, #328] @ (8001944 ) 80017fa: 4293 cmp r3, r2 80017fc: f040 8090 bne.w 8001920 __HAL_RCC_USART2_CLK_ENABLE(); 8001800: 2300 movs r3, #0 8001802: 60fb str r3, [r7, #12] 8001804: 4b49 ldr r3, [pc, #292] @ (800192c ) 8001806: 6c1b ldr r3, [r3, #64] @ 0x40 8001808: 4a48 ldr r2, [pc, #288] @ (800192c ) 800180a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800180e: 6413 str r3, [r2, #64] @ 0x40 8001810: 4b46 ldr r3, [pc, #280] @ (800192c ) 8001812: 6c1b ldr r3, [r3, #64] @ 0x40 8001814: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001818: 60fb str r3, [r7, #12] 800181a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 800181c: 2300 movs r3, #0 800181e: 60bb str r3, [r7, #8] 8001820: 4b42 ldr r3, [pc, #264] @ (800192c ) 8001822: 6b1b ldr r3, [r3, #48] @ 0x30 8001824: 4a41 ldr r2, [pc, #260] @ (800192c ) 8001826: f043 0301 orr.w r3, r3, #1 800182a: 6313 str r3, [r2, #48] @ 0x30 800182c: 4b3f ldr r3, [pc, #252] @ (800192c ) 800182e: 6b1b ldr r3, [r3, #48] @ 0x30 8001830: f003 0301 and.w r3, r3, #1 8001834: 60bb str r3, [r7, #8] 8001836: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; 8001838: 230c movs r3, #12 800183a: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800183c: 2302 movs r3, #2 800183e: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001840: 2300 movs r3, #0 8001842: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001844: 2303 movs r3, #3 8001846: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 8001848: 2307 movs r3, #7 800184a: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800184c: f107 032c add.w r3, r7, #44 @ 0x2c 8001850: 4619 mov r1, r3 8001852: 4837 ldr r0, [pc, #220] @ (8001930 ) 8001854: f000 fe54 bl 8002500 hdma_usart2_rx.Instance = DMA1_Stream5; 8001858: 4b3b ldr r3, [pc, #236] @ (8001948 ) 800185a: 4a3c ldr r2, [pc, #240] @ (800194c ) 800185c: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; 800185e: 4b3a ldr r3, [pc, #232] @ (8001948 ) 8001860: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001864: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001866: 4b38 ldr r3, [pc, #224] @ (8001948 ) 8001868: 2200 movs r2, #0 800186a: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 800186c: 4b36 ldr r3, [pc, #216] @ (8001948 ) 800186e: 2200 movs r2, #0 8001870: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 8001872: 4b35 ldr r3, [pc, #212] @ (8001948 ) 8001874: f44f 6280 mov.w r2, #1024 @ 0x400 8001878: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800187a: 4b33 ldr r3, [pc, #204] @ (8001948 ) 800187c: 2200 movs r2, #0 800187e: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001880: 4b31 ldr r3, [pc, #196] @ (8001948 ) 8001882: 2200 movs r2, #0 8001884: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 8001886: 4b30 ldr r3, [pc, #192] @ (8001948 ) 8001888: 2200 movs r2, #0 800188a: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; 800188c: 4b2e ldr r3, [pc, #184] @ (8001948 ) 800188e: 2200 movs r2, #0 8001890: 621a str r2, [r3, #32] hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001892: 4b2d ldr r3, [pc, #180] @ (8001948 ) 8001894: 2200 movs r2, #0 8001896: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 8001898: 482b ldr r0, [pc, #172] @ (8001948 ) 800189a: f000 fa2f bl 8001cfc 800189e: 4603 mov r3, r0 80018a0: 2b00 cmp r3, #0 80018a2: d001 beq.n 80018a8 Error_Handler(); 80018a4: f7ff fab0 bl 8000e08 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 80018a8: 687b ldr r3, [r7, #4] 80018aa: 4a27 ldr r2, [pc, #156] @ (8001948 ) 80018ac: 63da str r2, [r3, #60] @ 0x3c 80018ae: 4a26 ldr r2, [pc, #152] @ (8001948 ) 80018b0: 687b ldr r3, [r7, #4] 80018b2: 6393 str r3, [r2, #56] @ 0x38 hdma_usart2_tx.Instance = DMA1_Stream6; 80018b4: 4b26 ldr r3, [pc, #152] @ (8001950 ) 80018b6: 4a27 ldr r2, [pc, #156] @ (8001954 ) 80018b8: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; 80018ba: 4b25 ldr r3, [pc, #148] @ (8001950 ) 80018bc: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80018c0: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80018c2: 4b23 ldr r3, [pc, #140] @ (8001950 ) 80018c4: 2240 movs r2, #64 @ 0x40 80018c6: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 80018c8: 4b21 ldr r3, [pc, #132] @ (8001950 ) 80018ca: 2200 movs r2, #0 80018cc: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 80018ce: 4b20 ldr r3, [pc, #128] @ (8001950 ) 80018d0: f44f 6280 mov.w r2, #1024 @ 0x400 80018d4: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80018d6: 4b1e ldr r3, [pc, #120] @ (8001950 ) 80018d8: 2200 movs r2, #0 80018da: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80018dc: 4b1c ldr r3, [pc, #112] @ (8001950 ) 80018de: 2200 movs r2, #0 80018e0: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 80018e2: 4b1b ldr r3, [pc, #108] @ (8001950 ) 80018e4: 2200 movs r2, #0 80018e6: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; 80018e8: 4b19 ldr r3, [pc, #100] @ (8001950 ) 80018ea: 2200 movs r2, #0 80018ec: 621a str r2, [r3, #32] hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80018ee: 4b18 ldr r3, [pc, #96] @ (8001950 ) 80018f0: 2200 movs r2, #0 80018f2: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 80018f4: 4816 ldr r0, [pc, #88] @ (8001950 ) 80018f6: f000 fa01 bl 8001cfc 80018fa: 4603 mov r3, r0 80018fc: 2b00 cmp r3, #0 80018fe: d001 beq.n 8001904 Error_Handler(); 8001900: f7ff fa82 bl 8000e08 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 8001904: 687b ldr r3, [r7, #4] 8001906: 4a12 ldr r2, [pc, #72] @ (8001950 ) 8001908: 639a str r2, [r3, #56] @ 0x38 800190a: 4a11 ldr r2, [pc, #68] @ (8001950 ) 800190c: 687b ldr r3, [r7, #4] 800190e: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 8001910: 2200 movs r2, #0 8001912: 2100 movs r1, #0 8001914: 2026 movs r0, #38 @ 0x26 8001916: f000 f9ba bl 8001c8e HAL_NVIC_EnableIRQ(USART2_IRQn); 800191a: 2026 movs r0, #38 @ 0x26 800191c: f000 f9d3 bl 8001cc6 } 8001920: bf00 nop 8001922: 3740 adds r7, #64 @ 0x40 8001924: 46bd mov sp, r7 8001926: bd80 pop {r7, pc} 8001928: 40011000 .word 0x40011000 800192c: 40023800 .word 0x40023800 8001930: 40020000 .word 0x40020000 8001934: 2000059c .word 0x2000059c 8001938: 40026440 .word 0x40026440 800193c: 200005fc .word 0x200005fc 8001940: 400264b8 .word 0x400264b8 8001944: 40004400 .word 0x40004400 8001948: 2000065c .word 0x2000065c 800194c: 40026088 .word 0x40026088 8001950: 200006bc .word 0x200006bc 8001954: 400260a0 .word 0x400260a0 08001958 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001958: f8df d034 ldr.w sp, [pc, #52] @ 8001990 /* Call the clock system initialization function.*/ bl SystemInit 800195c: f7ff fb34 bl 8000fc8 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001960: 480c ldr r0, [pc, #48] @ (8001994 ) ldr r1, =_edata 8001962: 490d ldr r1, [pc, #52] @ (8001998 ) ldr r2, =_sidata 8001964: 4a0d ldr r2, [pc, #52] @ (800199c ) movs r3, #0 8001966: 2300 movs r3, #0 b LoopCopyDataInit 8001968: e002 b.n 8001970 0800196a : CopyDataInit: ldr r4, [r2, r3] 800196a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800196c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800196e: 3304 adds r3, #4 08001970 : LoopCopyDataInit: adds r4, r0, r3 8001970: 18c4 adds r4, r0, r3 cmp r4, r1 8001972: 428c cmp r4, r1 bcc CopyDataInit 8001974: d3f9 bcc.n 800196a /* Zero fill the bss segment. */ ldr r2, =_sbss 8001976: 4a0a ldr r2, [pc, #40] @ (80019a0 ) ldr r4, =_ebss 8001978: 4c0a ldr r4, [pc, #40] @ (80019a4 ) movs r3, #0 800197a: 2300 movs r3, #0 b LoopFillZerobss 800197c: e001 b.n 8001982 0800197e : FillZerobss: str r3, [r2] 800197e: 6013 str r3, [r2, #0] adds r2, r2, #4 8001980: 3204 adds r2, #4 08001982 : LoopFillZerobss: cmp r2, r4 8001982: 42a2 cmp r2, r4 bcc FillZerobss 8001984: d3fb bcc.n 800197e /* Call static constructors */ bl __libc_init_array 8001986: f009 f8f5 bl 800ab74 <__libc_init_array> /* Call the application's entry point.*/ bl main 800198a: f7fe ff4d bl 8000828
bx lr 800198e: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001990: 20020000 .word 0x20020000 ldr r0, =_sdata 8001994: 20000000 .word 0x20000000 ldr r1, =_edata 8001998: 200001a0 .word 0x200001a0 ldr r2, =_sidata 800199c: 0800ac5c .word 0x0800ac5c ldr r2, =_sbss 80019a0: 200001a0 .word 0x200001a0 ldr r4, =_ebss 80019a4: 200010f8 .word 0x200010f8 080019a8 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80019a8: e7fe b.n 80019a8 ... 080019ac : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80019ac: b580 push {r7, lr} 80019ae: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 80019b0: 4b0e ldr r3, [pc, #56] @ (80019ec ) 80019b2: 681b ldr r3, [r3, #0] 80019b4: 4a0d ldr r2, [pc, #52] @ (80019ec ) 80019b6: f443 7300 orr.w r3, r3, #512 @ 0x200 80019ba: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 80019bc: 4b0b ldr r3, [pc, #44] @ (80019ec ) 80019be: 681b ldr r3, [r3, #0] 80019c0: 4a0a ldr r2, [pc, #40] @ (80019ec ) 80019c2: f443 6380 orr.w r3, r3, #1024 @ 0x400 80019c6: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80019c8: 4b08 ldr r3, [pc, #32] @ (80019ec ) 80019ca: 681b ldr r3, [r3, #0] 80019cc: 4a07 ldr r2, [pc, #28] @ (80019ec ) 80019ce: f443 7380 orr.w r3, r3, #256 @ 0x100 80019d2: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80019d4: 2003 movs r0, #3 80019d6: f000 f94f bl 8001c78 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80019da: 200f movs r0, #15 80019dc: f000 f808 bl 80019f0 /* Init the low level hardware */ HAL_MspInit(); 80019e0: f7ff fa18 bl 8000e14 /* Return function status */ return HAL_OK; 80019e4: 2300 movs r3, #0 } 80019e6: 4618 mov r0, r3 80019e8: bd80 pop {r7, pc} 80019ea: bf00 nop 80019ec: 40023c00 .word 0x40023c00 080019f0 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80019f0: b580 push {r7, lr} 80019f2: b082 sub sp, #8 80019f4: af00 add r7, sp, #0 80019f6: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80019f8: 4b12 ldr r3, [pc, #72] @ (8001a44 ) 80019fa: 681a ldr r2, [r3, #0] 80019fc: 4b12 ldr r3, [pc, #72] @ (8001a48 ) 80019fe: 781b ldrb r3, [r3, #0] 8001a00: 4619 mov r1, r3 8001a02: f44f 737a mov.w r3, #1000 @ 0x3e8 8001a06: fbb3 f3f1 udiv r3, r3, r1 8001a0a: fbb2 f3f3 udiv r3, r2, r3 8001a0e: 4618 mov r0, r3 8001a10: f000 f967 bl 8001ce2 8001a14: 4603 mov r3, r0 8001a16: 2b00 cmp r3, #0 8001a18: d001 beq.n 8001a1e { return HAL_ERROR; 8001a1a: 2301 movs r3, #1 8001a1c: e00e b.n 8001a3c } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001a1e: 687b ldr r3, [r7, #4] 8001a20: 2b0f cmp r3, #15 8001a22: d80a bhi.n 8001a3a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001a24: 2200 movs r2, #0 8001a26: 6879 ldr r1, [r7, #4] 8001a28: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8001a2c: f000 f92f bl 8001c8e uwTickPrio = TickPriority; 8001a30: 4a06 ldr r2, [pc, #24] @ (8001a4c ) 8001a32: 687b ldr r3, [r7, #4] 8001a34: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8001a36: 2300 movs r3, #0 8001a38: e000 b.n 8001a3c return HAL_ERROR; 8001a3a: 2301 movs r3, #1 } 8001a3c: 4618 mov r0, r3 8001a3e: 3708 adds r7, #8 8001a40: 46bd mov sp, r7 8001a42: bd80 pop {r7, pc} 8001a44: 20000090 .word 0x20000090 8001a48: 20000098 .word 0x20000098 8001a4c: 20000094 .word 0x20000094 08001a50 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001a50: b480 push {r7} 8001a52: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001a54: 4b06 ldr r3, [pc, #24] @ (8001a70 ) 8001a56: 781b ldrb r3, [r3, #0] 8001a58: 461a mov r2, r3 8001a5a: 4b06 ldr r3, [pc, #24] @ (8001a74 ) 8001a5c: 681b ldr r3, [r3, #0] 8001a5e: 4413 add r3, r2 8001a60: 4a04 ldr r2, [pc, #16] @ (8001a74 ) 8001a62: 6013 str r3, [r2, #0] } 8001a64: bf00 nop 8001a66: 46bd mov sp, r7 8001a68: f85d 7b04 ldr.w r7, [sp], #4 8001a6c: 4770 bx lr 8001a6e: bf00 nop 8001a70: 20000098 .word 0x20000098 8001a74: 2000071c .word 0x2000071c 08001a78 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001a78: b480 push {r7} 8001a7a: af00 add r7, sp, #0 return uwTick; 8001a7c: 4b03 ldr r3, [pc, #12] @ (8001a8c ) 8001a7e: 681b ldr r3, [r3, #0] } 8001a80: 4618 mov r0, r3 8001a82: 46bd mov sp, r7 8001a84: f85d 7b04 ldr.w r7, [sp], #4 8001a88: 4770 bx lr 8001a8a: bf00 nop 8001a8c: 2000071c .word 0x2000071c 08001a90 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001a90: b580 push {r7, lr} 8001a92: b084 sub sp, #16 8001a94: af00 add r7, sp, #0 8001a96: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001a98: f7ff ffee bl 8001a78 8001a9c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001a9e: 687b ldr r3, [r7, #4] 8001aa0: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001aa2: 68fb ldr r3, [r7, #12] 8001aa4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8001aa8: d005 beq.n 8001ab6 { wait += (uint32_t)(uwTickFreq); 8001aaa: 4b0a ldr r3, [pc, #40] @ (8001ad4 ) 8001aac: 781b ldrb r3, [r3, #0] 8001aae: 461a mov r2, r3 8001ab0: 68fb ldr r3, [r7, #12] 8001ab2: 4413 add r3, r2 8001ab4: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8001ab6: bf00 nop 8001ab8: f7ff ffde bl 8001a78 8001abc: 4602 mov r2, r0 8001abe: 68bb ldr r3, [r7, #8] 8001ac0: 1ad3 subs r3, r2, r3 8001ac2: 68fa ldr r2, [r7, #12] 8001ac4: 429a cmp r2, r3 8001ac6: d8f7 bhi.n 8001ab8 { } } 8001ac8: bf00 nop 8001aca: bf00 nop 8001acc: 3710 adds r7, #16 8001ace: 46bd mov sp, r7 8001ad0: bd80 pop {r7, pc} 8001ad2: bf00 nop 8001ad4: 20000098 .word 0x20000098 08001ad8 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001ad8: b480 push {r7} 8001ada: b085 sub sp, #20 8001adc: af00 add r7, sp, #0 8001ade: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001ae0: 687b ldr r3, [r7, #4] 8001ae2: f003 0307 and.w r3, r3, #7 8001ae6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001ae8: 4b0c ldr r3, [pc, #48] @ (8001b1c <__NVIC_SetPriorityGrouping+0x44>) 8001aea: 68db ldr r3, [r3, #12] 8001aec: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001aee: 68ba ldr r2, [r7, #8] 8001af0: f64f 03ff movw r3, #63743 @ 0xf8ff 8001af4: 4013 ands r3, r2 8001af6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001af8: 68fb ldr r3, [r7, #12] 8001afa: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001afc: 68bb ldr r3, [r7, #8] 8001afe: 4313 orrs r3, r2 reg_value = (reg_value | 8001b00: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8001b04: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001b08: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001b0a: 4a04 ldr r2, [pc, #16] @ (8001b1c <__NVIC_SetPriorityGrouping+0x44>) 8001b0c: 68bb ldr r3, [r7, #8] 8001b0e: 60d3 str r3, [r2, #12] } 8001b10: bf00 nop 8001b12: 3714 adds r7, #20 8001b14: 46bd mov sp, r7 8001b16: f85d 7b04 ldr.w r7, [sp], #4 8001b1a: 4770 bx lr 8001b1c: e000ed00 .word 0xe000ed00 08001b20 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001b20: b480 push {r7} 8001b22: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001b24: 4b04 ldr r3, [pc, #16] @ (8001b38 <__NVIC_GetPriorityGrouping+0x18>) 8001b26: 68db ldr r3, [r3, #12] 8001b28: 0a1b lsrs r3, r3, #8 8001b2a: f003 0307 and.w r3, r3, #7 } 8001b2e: 4618 mov r0, r3 8001b30: 46bd mov sp, r7 8001b32: f85d 7b04 ldr.w r7, [sp], #4 8001b36: 4770 bx lr 8001b38: e000ed00 .word 0xe000ed00 08001b3c <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8001b3c: b480 push {r7} 8001b3e: b083 sub sp, #12 8001b40: af00 add r7, sp, #0 8001b42: 4603 mov r3, r0 8001b44: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001b46: f997 3007 ldrsb.w r3, [r7, #7] 8001b4a: 2b00 cmp r3, #0 8001b4c: db0b blt.n 8001b66 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001b4e: 79fb ldrb r3, [r7, #7] 8001b50: f003 021f and.w r2, r3, #31 8001b54: 4907 ldr r1, [pc, #28] @ (8001b74 <__NVIC_EnableIRQ+0x38>) 8001b56: f997 3007 ldrsb.w r3, [r7, #7] 8001b5a: 095b lsrs r3, r3, #5 8001b5c: 2001 movs r0, #1 8001b5e: fa00 f202 lsl.w r2, r0, r2 8001b62: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8001b66: bf00 nop 8001b68: 370c adds r7, #12 8001b6a: 46bd mov sp, r7 8001b6c: f85d 7b04 ldr.w r7, [sp], #4 8001b70: 4770 bx lr 8001b72: bf00 nop 8001b74: e000e100 .word 0xe000e100 08001b78 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001b78: b480 push {r7} 8001b7a: b083 sub sp, #12 8001b7c: af00 add r7, sp, #0 8001b7e: 4603 mov r3, r0 8001b80: 6039 str r1, [r7, #0] 8001b82: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001b84: f997 3007 ldrsb.w r3, [r7, #7] 8001b88: 2b00 cmp r3, #0 8001b8a: db0a blt.n 8001ba2 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001b8c: 683b ldr r3, [r7, #0] 8001b8e: b2da uxtb r2, r3 8001b90: 490c ldr r1, [pc, #48] @ (8001bc4 <__NVIC_SetPriority+0x4c>) 8001b92: f997 3007 ldrsb.w r3, [r7, #7] 8001b96: 0112 lsls r2, r2, #4 8001b98: b2d2 uxtb r2, r2 8001b9a: 440b add r3, r1 8001b9c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001ba0: e00a b.n 8001bb8 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001ba2: 683b ldr r3, [r7, #0] 8001ba4: b2da uxtb r2, r3 8001ba6: 4908 ldr r1, [pc, #32] @ (8001bc8 <__NVIC_SetPriority+0x50>) 8001ba8: 79fb ldrb r3, [r7, #7] 8001baa: f003 030f and.w r3, r3, #15 8001bae: 3b04 subs r3, #4 8001bb0: 0112 lsls r2, r2, #4 8001bb2: b2d2 uxtb r2, r2 8001bb4: 440b add r3, r1 8001bb6: 761a strb r2, [r3, #24] } 8001bb8: bf00 nop 8001bba: 370c adds r7, #12 8001bbc: 46bd mov sp, r7 8001bbe: f85d 7b04 ldr.w r7, [sp], #4 8001bc2: 4770 bx lr 8001bc4: e000e100 .word 0xe000e100 8001bc8: e000ed00 .word 0xe000ed00 08001bcc : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001bcc: b480 push {r7} 8001bce: b089 sub sp, #36 @ 0x24 8001bd0: af00 add r7, sp, #0 8001bd2: 60f8 str r0, [r7, #12] 8001bd4: 60b9 str r1, [r7, #8] 8001bd6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001bd8: 68fb ldr r3, [r7, #12] 8001bda: f003 0307 and.w r3, r3, #7 8001bde: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001be0: 69fb ldr r3, [r7, #28] 8001be2: f1c3 0307 rsb r3, r3, #7 8001be6: 2b04 cmp r3, #4 8001be8: bf28 it cs 8001bea: 2304 movcs r3, #4 8001bec: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001bee: 69fb ldr r3, [r7, #28] 8001bf0: 3304 adds r3, #4 8001bf2: 2b06 cmp r3, #6 8001bf4: d902 bls.n 8001bfc 8001bf6: 69fb ldr r3, [r7, #28] 8001bf8: 3b03 subs r3, #3 8001bfa: e000 b.n 8001bfe 8001bfc: 2300 movs r3, #0 8001bfe: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001c00: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8001c04: 69bb ldr r3, [r7, #24] 8001c06: fa02 f303 lsl.w r3, r2, r3 8001c0a: 43da mvns r2, r3 8001c0c: 68bb ldr r3, [r7, #8] 8001c0e: 401a ands r2, r3 8001c10: 697b ldr r3, [r7, #20] 8001c12: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001c14: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001c18: 697b ldr r3, [r7, #20] 8001c1a: fa01 f303 lsl.w r3, r1, r3 8001c1e: 43d9 mvns r1, r3 8001c20: 687b ldr r3, [r7, #4] 8001c22: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001c24: 4313 orrs r3, r2 ); } 8001c26: 4618 mov r0, r3 8001c28: 3724 adds r7, #36 @ 0x24 8001c2a: 46bd mov sp, r7 8001c2c: f85d 7b04 ldr.w r7, [sp], #4 8001c30: 4770 bx lr ... 08001c34 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001c34: b580 push {r7, lr} 8001c36: b082 sub sp, #8 8001c38: af00 add r7, sp, #0 8001c3a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001c3c: 687b ldr r3, [r7, #4] 8001c3e: 3b01 subs r3, #1 8001c40: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8001c44: d301 bcc.n 8001c4a { return (1UL); /* Reload value impossible */ 8001c46: 2301 movs r3, #1 8001c48: e00f b.n 8001c6a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001c4a: 4a0a ldr r2, [pc, #40] @ (8001c74 ) 8001c4c: 687b ldr r3, [r7, #4] 8001c4e: 3b01 subs r3, #1 8001c50: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001c52: 210f movs r1, #15 8001c54: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8001c58: f7ff ff8e bl 8001b78 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001c5c: 4b05 ldr r3, [pc, #20] @ (8001c74 ) 8001c5e: 2200 movs r2, #0 8001c60: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001c62: 4b04 ldr r3, [pc, #16] @ (8001c74 ) 8001c64: 2207 movs r2, #7 8001c66: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001c68: 2300 movs r3, #0 } 8001c6a: 4618 mov r0, r3 8001c6c: 3708 adds r7, #8 8001c6e: 46bd mov sp, r7 8001c70: bd80 pop {r7, pc} 8001c72: bf00 nop 8001c74: e000e010 .word 0xe000e010 08001c78 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001c78: b580 push {r7, lr} 8001c7a: b082 sub sp, #8 8001c7c: af00 add r7, sp, #0 8001c7e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001c80: 6878 ldr r0, [r7, #4] 8001c82: f7ff ff29 bl 8001ad8 <__NVIC_SetPriorityGrouping> } 8001c86: bf00 nop 8001c88: 3708 adds r7, #8 8001c8a: 46bd mov sp, r7 8001c8c: bd80 pop {r7, pc} 08001c8e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001c8e: b580 push {r7, lr} 8001c90: b086 sub sp, #24 8001c92: af00 add r7, sp, #0 8001c94: 4603 mov r3, r0 8001c96: 60b9 str r1, [r7, #8] 8001c98: 607a str r2, [r7, #4] 8001c9a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001c9c: 2300 movs r3, #0 8001c9e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001ca0: f7ff ff3e bl 8001b20 <__NVIC_GetPriorityGrouping> 8001ca4: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001ca6: 687a ldr r2, [r7, #4] 8001ca8: 68b9 ldr r1, [r7, #8] 8001caa: 6978 ldr r0, [r7, #20] 8001cac: f7ff ff8e bl 8001bcc 8001cb0: 4602 mov r2, r0 8001cb2: f997 300f ldrsb.w r3, [r7, #15] 8001cb6: 4611 mov r1, r2 8001cb8: 4618 mov r0, r3 8001cba: f7ff ff5d bl 8001b78 <__NVIC_SetPriority> } 8001cbe: bf00 nop 8001cc0: 3718 adds r7, #24 8001cc2: 46bd mov sp, r7 8001cc4: bd80 pop {r7, pc} 08001cc6 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8001cc6: b580 push {r7, lr} 8001cc8: b082 sub sp, #8 8001cca: af00 add r7, sp, #0 8001ccc: 4603 mov r3, r0 8001cce: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001cd0: f997 3007 ldrsb.w r3, [r7, #7] 8001cd4: 4618 mov r0, r3 8001cd6: f7ff ff31 bl 8001b3c <__NVIC_EnableIRQ> } 8001cda: bf00 nop 8001cdc: 3708 adds r7, #8 8001cde: 46bd mov sp, r7 8001ce0: bd80 pop {r7, pc} 08001ce2 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001ce2: b580 push {r7, lr} 8001ce4: b082 sub sp, #8 8001ce6: af00 add r7, sp, #0 8001ce8: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001cea: 6878 ldr r0, [r7, #4] 8001cec: f7ff ffa2 bl 8001c34 8001cf0: 4603 mov r3, r0 } 8001cf2: 4618 mov r0, r3 8001cf4: 3708 adds r7, #8 8001cf6: 46bd mov sp, r7 8001cf8: bd80 pop {r7, pc} ... 08001cfc : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8001cfc: b580 push {r7, lr} 8001cfe: b086 sub sp, #24 8001d00: af00 add r7, sp, #0 8001d02: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 8001d04: 2300 movs r3, #0 8001d06: 617b str r3, [r7, #20] uint32_t tickstart = HAL_GetTick(); 8001d08: f7ff feb6 bl 8001a78 8001d0c: 6138 str r0, [r7, #16] DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) 8001d0e: 687b ldr r3, [r7, #4] 8001d10: 2b00 cmp r3, #0 8001d12: d101 bne.n 8001d18 { return HAL_ERROR; 8001d14: 2301 movs r3, #1 8001d16: e099 b.n 8001e4c assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001d18: 687b ldr r3, [r7, #4] 8001d1a: 2202 movs r2, #2 8001d1c: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8001d20: 687b ldr r3, [r7, #4] 8001d22: 2200 movs r2, #0 8001d24: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8001d28: 687b ldr r3, [r7, #4] 8001d2a: 681b ldr r3, [r3, #0] 8001d2c: 681a ldr r2, [r3, #0] 8001d2e: 687b ldr r3, [r7, #4] 8001d30: 681b ldr r3, [r3, #0] 8001d32: f022 0201 bic.w r2, r2, #1 8001d36: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001d38: e00f b.n 8001d5a { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8001d3a: f7ff fe9d bl 8001a78 8001d3e: 4602 mov r2, r0 8001d40: 693b ldr r3, [r7, #16] 8001d42: 1ad3 subs r3, r2, r3 8001d44: 2b05 cmp r3, #5 8001d46: d908 bls.n 8001d5a { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8001d48: 687b ldr r3, [r7, #4] 8001d4a: 2220 movs r2, #32 8001d4c: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8001d4e: 687b ldr r3, [r7, #4] 8001d50: 2203 movs r2, #3 8001d52: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_TIMEOUT; 8001d56: 2303 movs r3, #3 8001d58: e078 b.n 8001e4c while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001d5a: 687b ldr r3, [r7, #4] 8001d5c: 681b ldr r3, [r3, #0] 8001d5e: 681b ldr r3, [r3, #0] 8001d60: f003 0301 and.w r3, r3, #1 8001d64: 2b00 cmp r3, #0 8001d66: d1e8 bne.n 8001d3a } } /* Get the CR register value */ tmp = hdma->Instance->CR; 8001d68: 687b ldr r3, [r7, #4] 8001d6a: 681b ldr r3, [r3, #0] 8001d6c: 681b ldr r3, [r3, #0] 8001d6e: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8001d70: 697a ldr r2, [r7, #20] 8001d72: 4b38 ldr r3, [pc, #224] @ (8001e54 ) 8001d74: 4013 ands r3, r2 8001d76: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001d78: 687b ldr r3, [r7, #4] 8001d7a: 685a ldr r2, [r3, #4] 8001d7c: 687b ldr r3, [r7, #4] 8001d7e: 689b ldr r3, [r3, #8] 8001d80: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001d82: 687b ldr r3, [r7, #4] 8001d84: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001d86: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001d88: 687b ldr r3, [r7, #4] 8001d8a: 691b ldr r3, [r3, #16] 8001d8c: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001d8e: 687b ldr r3, [r7, #4] 8001d90: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8001d92: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001d94: 687b ldr r3, [r7, #4] 8001d96: 699b ldr r3, [r3, #24] 8001d98: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001d9a: 687b ldr r3, [r7, #4] 8001d9c: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001d9e: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001da0: 687b ldr r3, [r7, #4] 8001da2: 6a1b ldr r3, [r3, #32] 8001da4: 4313 orrs r3, r2 tmp |= hdma->Init.Channel | hdma->Init.Direction | 8001da6: 697a ldr r2, [r7, #20] 8001da8: 4313 orrs r3, r2 8001daa: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001dac: 687b ldr r3, [r7, #4] 8001dae: 6a5b ldr r3, [r3, #36] @ 0x24 8001db0: 2b04 cmp r3, #4 8001db2: d107 bne.n 8001dc4 { /* Get memory burst and peripheral burst */ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8001db4: 687b ldr r3, [r7, #4] 8001db6: 6ada ldr r2, [r3, #44] @ 0x2c 8001db8: 687b ldr r3, [r7, #4] 8001dba: 6b1b ldr r3, [r3, #48] @ 0x30 8001dbc: 4313 orrs r3, r2 8001dbe: 697a ldr r2, [r7, #20] 8001dc0: 4313 orrs r3, r2 8001dc2: 617b str r3, [r7, #20] } /* Write to DMA Stream CR register */ hdma->Instance->CR = tmp; 8001dc4: 687b ldr r3, [r7, #4] 8001dc6: 681b ldr r3, [r3, #0] 8001dc8: 697a ldr r2, [r7, #20] 8001dca: 601a str r2, [r3, #0] /* Get the FCR register value */ tmp = hdma->Instance->FCR; 8001dcc: 687b ldr r3, [r7, #4] 8001dce: 681b ldr r3, [r3, #0] 8001dd0: 695b ldr r3, [r3, #20] 8001dd2: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8001dd4: 697b ldr r3, [r7, #20] 8001dd6: f023 0307 bic.w r3, r3, #7 8001dda: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ tmp |= hdma->Init.FIFOMode; 8001ddc: 687b ldr r3, [r7, #4] 8001dde: 6a5b ldr r3, [r3, #36] @ 0x24 8001de0: 697a ldr r2, [r7, #20] 8001de2: 4313 orrs r3, r2 8001de4: 617b str r3, [r7, #20] /* The FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001de6: 687b ldr r3, [r7, #4] 8001de8: 6a5b ldr r3, [r3, #36] @ 0x24 8001dea: 2b04 cmp r3, #4 8001dec: d117 bne.n 8001e1e { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; 8001dee: 687b ldr r3, [r7, #4] 8001df0: 6a9b ldr r3, [r3, #40] @ 0x28 8001df2: 697a ldr r2, [r7, #20] 8001df4: 4313 orrs r3, r2 8001df6: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 bursts */ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8001df8: 687b ldr r3, [r7, #4] 8001dfa: 6adb ldr r3, [r3, #44] @ 0x2c 8001dfc: 2b00 cmp r3, #0 8001dfe: d00e beq.n 8001e1e { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8001e00: 6878 ldr r0, [r7, #4] 8001e02: f000 fb01 bl 8002408 8001e06: 4603 mov r3, r0 8001e08: 2b00 cmp r3, #0 8001e0a: d008 beq.n 8001e1e { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8001e0c: 687b ldr r3, [r7, #4] 8001e0e: 2240 movs r2, #64 @ 0x40 8001e10: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001e12: 687b ldr r3, [r7, #4] 8001e14: 2201 movs r2, #1 8001e16: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8001e1a: 2301 movs r3, #1 8001e1c: e016 b.n 8001e4c } } } /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; 8001e1e: 687b ldr r3, [r7, #4] 8001e20: 681b ldr r3, [r3, #0] 8001e22: 697a ldr r2, [r7, #20] 8001e24: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8001e26: 6878 ldr r0, [r7, #4] 8001e28: f000 fab8 bl 800239c 8001e2c: 4603 mov r3, r0 8001e2e: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001e30: 687b ldr r3, [r7, #4] 8001e32: 6ddb ldr r3, [r3, #92] @ 0x5c 8001e34: 223f movs r2, #63 @ 0x3f 8001e36: 409a lsls r2, r3 8001e38: 68fb ldr r3, [r7, #12] 8001e3a: 609a str r2, [r3, #8] /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001e3c: 687b ldr r3, [r7, #4] 8001e3e: 2200 movs r2, #0 8001e40: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001e42: 687b ldr r3, [r7, #4] 8001e44: 2201 movs r2, #1 8001e46: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8001e4a: 2300 movs r3, #0 } 8001e4c: 4618 mov r0, r3 8001e4e: 3718 adds r7, #24 8001e50: 46bd mov sp, r7 8001e52: bd80 pop {r7, pc} 8001e54: f010803f .word 0xf010803f 08001e58 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8001e58: b580 push {r7, lr} 8001e5a: b086 sub sp, #24 8001e5c: af00 add r7, sp, #0 8001e5e: 60f8 str r0, [r7, #12] 8001e60: 60b9 str r1, [r7, #8] 8001e62: 607a str r2, [r7, #4] 8001e64: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8001e66: 2300 movs r3, #0 8001e68: 75fb strb r3, [r7, #23] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001e6a: 68fb ldr r3, [r7, #12] 8001e6c: 6d9b ldr r3, [r3, #88] @ 0x58 8001e6e: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8001e70: 68fb ldr r3, [r7, #12] 8001e72: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8001e76: 2b01 cmp r3, #1 8001e78: d101 bne.n 8001e7e 8001e7a: 2302 movs r3, #2 8001e7c: e040 b.n 8001f00 8001e7e: 68fb ldr r3, [r7, #12] 8001e80: 2201 movs r2, #1 8001e82: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8001e86: 68fb ldr r3, [r7, #12] 8001e88: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001e8c: b2db uxtb r3, r3 8001e8e: 2b01 cmp r3, #1 8001e90: d12f bne.n 8001ef2 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001e92: 68fb ldr r3, [r7, #12] 8001e94: 2202 movs r2, #2 8001e96: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001e9a: 68fb ldr r3, [r7, #12] 8001e9c: 2200 movs r2, #0 8001e9e: 655a str r2, [r3, #84] @ 0x54 /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8001ea0: 683b ldr r3, [r7, #0] 8001ea2: 687a ldr r2, [r7, #4] 8001ea4: 68b9 ldr r1, [r7, #8] 8001ea6: 68f8 ldr r0, [r7, #12] 8001ea8: f000 fa4a bl 8002340 /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001eac: 68fb ldr r3, [r7, #12] 8001eae: 6ddb ldr r3, [r3, #92] @ 0x5c 8001eb0: 223f movs r2, #63 @ 0x3f 8001eb2: 409a lsls r2, r3 8001eb4: 693b ldr r3, [r7, #16] 8001eb6: 609a str r2, [r3, #8] /* Enable Common interrupts*/ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; 8001eb8: 68fb ldr r3, [r7, #12] 8001eba: 681b ldr r3, [r3, #0] 8001ebc: 681a ldr r2, [r3, #0] 8001ebe: 68fb ldr r3, [r7, #12] 8001ec0: 681b ldr r3, [r3, #0] 8001ec2: f042 0216 orr.w r2, r2, #22 8001ec6: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8001ec8: 68fb ldr r3, [r7, #12] 8001eca: 6c1b ldr r3, [r3, #64] @ 0x40 8001ecc: 2b00 cmp r3, #0 8001ece: d007 beq.n 8001ee0 { hdma->Instance->CR |= DMA_IT_HT; 8001ed0: 68fb ldr r3, [r7, #12] 8001ed2: 681b ldr r3, [r3, #0] 8001ed4: 681a ldr r2, [r3, #0] 8001ed6: 68fb ldr r3, [r7, #12] 8001ed8: 681b ldr r3, [r3, #0] 8001eda: f042 0208 orr.w r2, r2, #8 8001ede: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8001ee0: 68fb ldr r3, [r7, #12] 8001ee2: 681b ldr r3, [r3, #0] 8001ee4: 681a ldr r2, [r3, #0] 8001ee6: 68fb ldr r3, [r7, #12] 8001ee8: 681b ldr r3, [r3, #0] 8001eea: f042 0201 orr.w r2, r2, #1 8001eee: 601a str r2, [r3, #0] 8001ef0: e005 b.n 8001efe } else { /* Process unlocked */ __HAL_UNLOCK(hdma); 8001ef2: 68fb ldr r3, [r7, #12] 8001ef4: 2200 movs r2, #0 8001ef6: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_BUSY; 8001efa: 2302 movs r3, #2 8001efc: 75fb strb r3, [r7, #23] } return status; 8001efe: 7dfb ldrb r3, [r7, #23] } 8001f00: 4618 mov r0, r3 8001f02: 3718 adds r7, #24 8001f04: 46bd mov sp, r7 8001f06: bd80 pop {r7, pc} 08001f08 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8001f08: b580 push {r7, lr} 8001f0a: b084 sub sp, #16 8001f0c: af00 add r7, sp, #0 8001f0e: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001f10: 687b ldr r3, [r7, #4] 8001f12: 6d9b ldr r3, [r3, #88] @ 0x58 8001f14: 60fb str r3, [r7, #12] uint32_t tickstart = HAL_GetTick(); 8001f16: f7ff fdaf bl 8001a78 8001f1a: 60b8 str r0, [r7, #8] if(hdma->State != HAL_DMA_STATE_BUSY) 8001f1c: 687b ldr r3, [r7, #4] 8001f1e: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001f22: b2db uxtb r3, r3 8001f24: 2b02 cmp r3, #2 8001f26: d008 beq.n 8001f3a { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001f28: 687b ldr r3, [r7, #4] 8001f2a: 2280 movs r2, #128 @ 0x80 8001f2c: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001f2e: 687b ldr r3, [r7, #4] 8001f30: 2200 movs r2, #0 8001f32: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8001f36: 2301 movs r3, #1 8001f38: e052 b.n 8001fe0 } else { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8001f3a: 687b ldr r3, [r7, #4] 8001f3c: 681b ldr r3, [r3, #0] 8001f3e: 681a ldr r2, [r3, #0] 8001f40: 687b ldr r3, [r7, #4] 8001f42: 681b ldr r3, [r3, #0] 8001f44: f022 0216 bic.w r2, r2, #22 8001f48: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 8001f4a: 687b ldr r3, [r7, #4] 8001f4c: 681b ldr r3, [r3, #0] 8001f4e: 695a ldr r2, [r3, #20] 8001f50: 687b ldr r3, [r7, #4] 8001f52: 681b ldr r3, [r3, #0] 8001f54: f022 0280 bic.w r2, r2, #128 @ 0x80 8001f58: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8001f5a: 687b ldr r3, [r7, #4] 8001f5c: 6c1b ldr r3, [r3, #64] @ 0x40 8001f5e: 2b00 cmp r3, #0 8001f60: d103 bne.n 8001f6a 8001f62: 687b ldr r3, [r7, #4] 8001f64: 6c9b ldr r3, [r3, #72] @ 0x48 8001f66: 2b00 cmp r3, #0 8001f68: d007 beq.n 8001f7a { hdma->Instance->CR &= ~(DMA_IT_HT); 8001f6a: 687b ldr r3, [r7, #4] 8001f6c: 681b ldr r3, [r3, #0] 8001f6e: 681a ldr r2, [r3, #0] 8001f70: 687b ldr r3, [r7, #4] 8001f72: 681b ldr r3, [r3, #0] 8001f74: f022 0208 bic.w r2, r2, #8 8001f78: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8001f7a: 687b ldr r3, [r7, #4] 8001f7c: 681b ldr r3, [r3, #0] 8001f7e: 681a ldr r2, [r3, #0] 8001f80: 687b ldr r3, [r7, #4] 8001f82: 681b ldr r3, [r3, #0] 8001f84: f022 0201 bic.w r2, r2, #1 8001f88: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001f8a: e013 b.n 8001fb4 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8001f8c: f7ff fd74 bl 8001a78 8001f90: 4602 mov r2, r0 8001f92: 68bb ldr r3, [r7, #8] 8001f94: 1ad3 subs r3, r2, r3 8001f96: 2b05 cmp r3, #5 8001f98: d90c bls.n 8001fb4 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8001f9a: 687b ldr r3, [r7, #4] 8001f9c: 2220 movs r2, #32 8001f9e: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8001fa0: 687b ldr r3, [r7, #4] 8001fa2: 2203 movs r2, #3 8001fa4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001fa8: 687b ldr r3, [r7, #4] 8001faa: 2200 movs r2, #0 8001fac: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_TIMEOUT; 8001fb0: 2303 movs r3, #3 8001fb2: e015 b.n 8001fe0 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001fb4: 687b ldr r3, [r7, #4] 8001fb6: 681b ldr r3, [r3, #0] 8001fb8: 681b ldr r3, [r3, #0] 8001fba: f003 0301 and.w r3, r3, #1 8001fbe: 2b00 cmp r3, #0 8001fc0: d1e4 bne.n 8001f8c } } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8001fc2: 687b ldr r3, [r7, #4] 8001fc4: 6ddb ldr r3, [r3, #92] @ 0x5c 8001fc6: 223f movs r2, #63 @ 0x3f 8001fc8: 409a lsls r2, r3 8001fca: 68fb ldr r3, [r7, #12] 8001fcc: 609a str r2, [r3, #8] /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8001fce: 687b ldr r3, [r7, #4] 8001fd0: 2201 movs r2, #1 8001fd2: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001fd6: 687b ldr r3, [r7, #4] 8001fd8: 2200 movs r2, #0 8001fda: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 8001fde: 2300 movs r3, #0 } 8001fe0: 4618 mov r0, r3 8001fe2: 3710 adds r7, #16 8001fe4: 46bd mov sp, r7 8001fe6: bd80 pop {r7, pc} 08001fe8 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8001fe8: b480 push {r7} 8001fea: b083 sub sp, #12 8001fec: af00 add r7, sp, #0 8001fee: 6078 str r0, [r7, #4] if(hdma->State != HAL_DMA_STATE_BUSY) 8001ff0: 687b ldr r3, [r7, #4] 8001ff2: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8001ff6: b2db uxtb r3, r3 8001ff8: 2b02 cmp r3, #2 8001ffa: d004 beq.n 8002006 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001ffc: 687b ldr r3, [r7, #4] 8001ffe: 2280 movs r2, #128 @ 0x80 8002000: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 8002002: 2301 movs r3, #1 8002004: e00c b.n 8002020 } else { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 8002006: 687b ldr r3, [r7, #4] 8002008: 2205 movs r2, #5 800200a: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800200e: 687b ldr r3, [r7, #4] 8002010: 681b ldr r3, [r3, #0] 8002012: 681a ldr r2, [r3, #0] 8002014: 687b ldr r3, [r7, #4] 8002016: 681b ldr r3, [r3, #0] 8002018: f022 0201 bic.w r2, r2, #1 800201c: 601a str r2, [r3, #0] } return HAL_OK; 800201e: 2300 movs r3, #0 } 8002020: 4618 mov r0, r3 8002022: 370c adds r7, #12 8002024: 46bd mov sp, r7 8002026: f85d 7b04 ldr.w r7, [sp], #4 800202a: 4770 bx lr 0800202c : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 800202c: b580 push {r7, lr} 800202e: b086 sub sp, #24 8002030: af00 add r7, sp, #0 8002032: 6078 str r0, [r7, #4] uint32_t tmpisr; __IO uint32_t count = 0U; 8002034: 2300 movs r3, #0 8002036: 60bb str r3, [r7, #8] uint32_t timeout = SystemCoreClock / 9600U; 8002038: 4b8e ldr r3, [pc, #568] @ (8002274 ) 800203a: 681b ldr r3, [r3, #0] 800203c: 4a8e ldr r2, [pc, #568] @ (8002278 ) 800203e: fba2 2303 umull r2, r3, r2, r3 8002042: 0a9b lsrs r3, r3, #10 8002044: 617b str r3, [r7, #20] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8002046: 687b ldr r3, [r7, #4] 8002048: 6d9b ldr r3, [r3, #88] @ 0x58 800204a: 613b str r3, [r7, #16] tmpisr = regs->ISR; 800204c: 693b ldr r3, [r7, #16] 800204e: 681b ldr r3, [r3, #0] 8002050: 60fb str r3, [r7, #12] /* Transfer Error Interrupt management ***************************************/ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) 8002052: 687b ldr r3, [r7, #4] 8002054: 6ddb ldr r3, [r3, #92] @ 0x5c 8002056: 2208 movs r2, #8 8002058: 409a lsls r2, r3 800205a: 68fb ldr r3, [r7, #12] 800205c: 4013 ands r3, r2 800205e: 2b00 cmp r3, #0 8002060: d01a beq.n 8002098 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) 8002062: 687b ldr r3, [r7, #4] 8002064: 681b ldr r3, [r3, #0] 8002066: 681b ldr r3, [r3, #0] 8002068: f003 0304 and.w r3, r3, #4 800206c: 2b00 cmp r3, #0 800206e: d013 beq.n 8002098 { /* Disable the transfer error interrupt */ hdma->Instance->CR &= ~(DMA_IT_TE); 8002070: 687b ldr r3, [r7, #4] 8002072: 681b ldr r3, [r3, #0] 8002074: 681a ldr r2, [r3, #0] 8002076: 687b ldr r3, [r7, #4] 8002078: 681b ldr r3, [r3, #0] 800207a: f022 0204 bic.w r2, r2, #4 800207e: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; 8002080: 687b ldr r3, [r7, #4] 8002082: 6ddb ldr r3, [r3, #92] @ 0x5c 8002084: 2208 movs r2, #8 8002086: 409a lsls r2, r3 8002088: 693b ldr r3, [r7, #16] 800208a: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 800208c: 687b ldr r3, [r7, #4] 800208e: 6d5b ldr r3, [r3, #84] @ 0x54 8002090: f043 0201 orr.w r2, r3, #1 8002094: 687b ldr r3, [r7, #4] 8002096: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) 8002098: 687b ldr r3, [r7, #4] 800209a: 6ddb ldr r3, [r3, #92] @ 0x5c 800209c: 2201 movs r2, #1 800209e: 409a lsls r2, r3 80020a0: 68fb ldr r3, [r7, #12] 80020a2: 4013 ands r3, r2 80020a4: 2b00 cmp r3, #0 80020a6: d012 beq.n 80020ce { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) 80020a8: 687b ldr r3, [r7, #4] 80020aa: 681b ldr r3, [r3, #0] 80020ac: 695b ldr r3, [r3, #20] 80020ae: f003 0380 and.w r3, r3, #128 @ 0x80 80020b2: 2b00 cmp r3, #0 80020b4: d00b beq.n 80020ce { /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; 80020b6: 687b ldr r3, [r7, #4] 80020b8: 6ddb ldr r3, [r3, #92] @ 0x5c 80020ba: 2201 movs r2, #1 80020bc: 409a lsls r2, r3 80020be: 693b ldr r3, [r7, #16] 80020c0: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 80020c2: 687b ldr r3, [r7, #4] 80020c4: 6d5b ldr r3, [r3, #84] @ 0x54 80020c6: f043 0202 orr.w r2, r3, #2 80020ca: 687b ldr r3, [r7, #4] 80020cc: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) 80020ce: 687b ldr r3, [r7, #4] 80020d0: 6ddb ldr r3, [r3, #92] @ 0x5c 80020d2: 2204 movs r2, #4 80020d4: 409a lsls r2, r3 80020d6: 68fb ldr r3, [r7, #12] 80020d8: 4013 ands r3, r2 80020da: 2b00 cmp r3, #0 80020dc: d012 beq.n 8002104 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) 80020de: 687b ldr r3, [r7, #4] 80020e0: 681b ldr r3, [r3, #0] 80020e2: 681b ldr r3, [r3, #0] 80020e4: f003 0302 and.w r3, r3, #2 80020e8: 2b00 cmp r3, #0 80020ea: d00b beq.n 8002104 { /* Clear the direct mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; 80020ec: 687b ldr r3, [r7, #4] 80020ee: 6ddb ldr r3, [r3, #92] @ 0x5c 80020f0: 2204 movs r2, #4 80020f2: 409a lsls r2, r3 80020f4: 693b ldr r3, [r7, #16] 80020f6: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 80020f8: 687b ldr r3, [r7, #4] 80020fa: 6d5b ldr r3, [r3, #84] @ 0x54 80020fc: f043 0204 orr.w r2, r3, #4 8002100: 687b ldr r3, [r7, #4] 8002102: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) 8002104: 687b ldr r3, [r7, #4] 8002106: 6ddb ldr r3, [r3, #92] @ 0x5c 8002108: 2210 movs r2, #16 800210a: 409a lsls r2, r3 800210c: 68fb ldr r3, [r7, #12] 800210e: 4013 ands r3, r2 8002110: 2b00 cmp r3, #0 8002112: d043 beq.n 800219c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) 8002114: 687b ldr r3, [r7, #4] 8002116: 681b ldr r3, [r3, #0] 8002118: 681b ldr r3, [r3, #0] 800211a: f003 0308 and.w r3, r3, #8 800211e: 2b00 cmp r3, #0 8002120: d03c beq.n 800219c { /* Clear the half transfer complete flag */ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; 8002122: 687b ldr r3, [r7, #4] 8002124: 6ddb ldr r3, [r3, #92] @ 0x5c 8002126: 2210 movs r2, #16 8002128: 409a lsls r2, r3 800212a: 693b ldr r3, [r7, #16] 800212c: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 800212e: 687b ldr r3, [r7, #4] 8002130: 681b ldr r3, [r3, #0] 8002132: 681b ldr r3, [r3, #0] 8002134: f403 2380 and.w r3, r3, #262144 @ 0x40000 8002138: 2b00 cmp r3, #0 800213a: d018 beq.n 800216e { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 800213c: 687b ldr r3, [r7, #4] 800213e: 681b ldr r3, [r3, #0] 8002140: 681b ldr r3, [r3, #0] 8002142: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002146: 2b00 cmp r3, #0 8002148: d108 bne.n 800215c { if(hdma->XferHalfCpltCallback != NULL) 800214a: 687b ldr r3, [r7, #4] 800214c: 6c1b ldr r3, [r3, #64] @ 0x40 800214e: 2b00 cmp r3, #0 8002150: d024 beq.n 800219c { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002152: 687b ldr r3, [r7, #4] 8002154: 6c1b ldr r3, [r3, #64] @ 0x40 8002156: 6878 ldr r0, [r7, #4] 8002158: 4798 blx r3 800215a: e01f b.n 800219c } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 800215c: 687b ldr r3, [r7, #4] 800215e: 6c9b ldr r3, [r3, #72] @ 0x48 8002160: 2b00 cmp r3, #0 8002162: d01b beq.n 800219c { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8002164: 687b ldr r3, [r7, #4] 8002166: 6c9b ldr r3, [r3, #72] @ 0x48 8002168: 6878 ldr r0, [r7, #4] 800216a: 4798 blx r3 800216c: e016 b.n 800219c } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 800216e: 687b ldr r3, [r7, #4] 8002170: 681b ldr r3, [r3, #0] 8002172: 681b ldr r3, [r3, #0] 8002174: f403 7380 and.w r3, r3, #256 @ 0x100 8002178: 2b00 cmp r3, #0 800217a: d107 bne.n 800218c { /* Disable the half transfer interrupt */ hdma->Instance->CR &= ~(DMA_IT_HT); 800217c: 687b ldr r3, [r7, #4] 800217e: 681b ldr r3, [r3, #0] 8002180: 681a ldr r2, [r3, #0] 8002182: 687b ldr r3, [r7, #4] 8002184: 681b ldr r3, [r3, #0] 8002186: f022 0208 bic.w r2, r2, #8 800218a: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 800218c: 687b ldr r3, [r7, #4] 800218e: 6c1b ldr r3, [r3, #64] @ 0x40 8002190: 2b00 cmp r3, #0 8002192: d003 beq.n 800219c { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002194: 687b ldr r3, [r7, #4] 8002196: 6c1b ldr r3, [r3, #64] @ 0x40 8002198: 6878 ldr r0, [r7, #4] 800219a: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) 800219c: 687b ldr r3, [r7, #4] 800219e: 6ddb ldr r3, [r3, #92] @ 0x5c 80021a0: 2220 movs r2, #32 80021a2: 409a lsls r2, r3 80021a4: 68fb ldr r3, [r7, #12] 80021a6: 4013 ands r3, r2 80021a8: 2b00 cmp r3, #0 80021aa: f000 808f beq.w 80022cc { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) 80021ae: 687b ldr r3, [r7, #4] 80021b0: 681b ldr r3, [r3, #0] 80021b2: 681b ldr r3, [r3, #0] 80021b4: f003 0310 and.w r3, r3, #16 80021b8: 2b00 cmp r3, #0 80021ba: f000 8087 beq.w 80022cc { /* Clear the transfer complete flag */ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; 80021be: 687b ldr r3, [r7, #4] 80021c0: 6ddb ldr r3, [r3, #92] @ 0x5c 80021c2: 2220 movs r2, #32 80021c4: 409a lsls r2, r3 80021c6: 693b ldr r3, [r7, #16] 80021c8: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 80021ca: 687b ldr r3, [r7, #4] 80021cc: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80021d0: b2db uxtb r3, r3 80021d2: 2b05 cmp r3, #5 80021d4: d136 bne.n 8002244 { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 80021d6: 687b ldr r3, [r7, #4] 80021d8: 681b ldr r3, [r3, #0] 80021da: 681a ldr r2, [r3, #0] 80021dc: 687b ldr r3, [r7, #4] 80021de: 681b ldr r3, [r3, #0] 80021e0: f022 0216 bic.w r2, r2, #22 80021e4: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 80021e6: 687b ldr r3, [r7, #4] 80021e8: 681b ldr r3, [r3, #0] 80021ea: 695a ldr r2, [r3, #20] 80021ec: 687b ldr r3, [r7, #4] 80021ee: 681b ldr r3, [r3, #0] 80021f0: f022 0280 bic.w r2, r2, #128 @ 0x80 80021f4: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 80021f6: 687b ldr r3, [r7, #4] 80021f8: 6c1b ldr r3, [r3, #64] @ 0x40 80021fa: 2b00 cmp r3, #0 80021fc: d103 bne.n 8002206 80021fe: 687b ldr r3, [r7, #4] 8002200: 6c9b ldr r3, [r3, #72] @ 0x48 8002202: 2b00 cmp r3, #0 8002204: d007 beq.n 8002216 { hdma->Instance->CR &= ~(DMA_IT_HT); 8002206: 687b ldr r3, [r7, #4] 8002208: 681b ldr r3, [r3, #0] 800220a: 681a ldr r2, [r3, #0] 800220c: 687b ldr r3, [r7, #4] 800220e: 681b ldr r3, [r3, #0] 8002210: f022 0208 bic.w r2, r2, #8 8002214: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8002216: 687b ldr r3, [r7, #4] 8002218: 6ddb ldr r3, [r3, #92] @ 0x5c 800221a: 223f movs r2, #63 @ 0x3f 800221c: 409a lsls r2, r3 800221e: 693b ldr r3, [r7, #16] 8002220: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002222: 687b ldr r3, [r7, #4] 8002224: 2201 movs r2, #1 8002226: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800222a: 687b ldr r3, [r7, #4] 800222c: 2200 movs r2, #0 800222e: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 8002232: 687b ldr r3, [r7, #4] 8002234: 6d1b ldr r3, [r3, #80] @ 0x50 8002236: 2b00 cmp r3, #0 8002238: d07e beq.n 8002338 { hdma->XferAbortCallback(hdma); 800223a: 687b ldr r3, [r7, #4] 800223c: 6d1b ldr r3, [r3, #80] @ 0x50 800223e: 6878 ldr r0, [r7, #4] 8002240: 4798 blx r3 } return; 8002242: e079 b.n 8002338 } if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 8002244: 687b ldr r3, [r7, #4] 8002246: 681b ldr r3, [r3, #0] 8002248: 681b ldr r3, [r3, #0] 800224a: f403 2380 and.w r3, r3, #262144 @ 0x40000 800224e: 2b00 cmp r3, #0 8002250: d01d beq.n 800228e { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 8002252: 687b ldr r3, [r7, #4] 8002254: 681b ldr r3, [r3, #0] 8002256: 681b ldr r3, [r3, #0] 8002258: f403 2300 and.w r3, r3, #524288 @ 0x80000 800225c: 2b00 cmp r3, #0 800225e: d10d bne.n 800227c { if(hdma->XferM1CpltCallback != NULL) 8002260: 687b ldr r3, [r7, #4] 8002262: 6c5b ldr r3, [r3, #68] @ 0x44 8002264: 2b00 cmp r3, #0 8002266: d031 beq.n 80022cc { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 8002268: 687b ldr r3, [r7, #4] 800226a: 6c5b ldr r3, [r3, #68] @ 0x44 800226c: 6878 ldr r0, [r7, #4] 800226e: 4798 blx r3 8002270: e02c b.n 80022cc 8002272: bf00 nop 8002274: 20000090 .word 0x20000090 8002278: 1b4e81b5 .word 0x1b4e81b5 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800227c: 687b ldr r3, [r7, #4] 800227e: 6bdb ldr r3, [r3, #60] @ 0x3c 8002280: 2b00 cmp r3, #0 8002282: d023 beq.n 80022cc { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8002284: 687b ldr r3, [r7, #4] 8002286: 6bdb ldr r3, [r3, #60] @ 0x3c 8002288: 6878 ldr r0, [r7, #4] 800228a: 4798 blx r3 800228c: e01e b.n 80022cc } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 800228e: 687b ldr r3, [r7, #4] 8002290: 681b ldr r3, [r3, #0] 8002292: 681b ldr r3, [r3, #0] 8002294: f403 7380 and.w r3, r3, #256 @ 0x100 8002298: 2b00 cmp r3, #0 800229a: d10f bne.n 80022bc { /* Disable the transfer complete interrupt */ hdma->Instance->CR &= ~(DMA_IT_TC); 800229c: 687b ldr r3, [r7, #4] 800229e: 681b ldr r3, [r3, #0] 80022a0: 681a ldr r2, [r3, #0] 80022a2: 687b ldr r3, [r7, #4] 80022a4: 681b ldr r3, [r3, #0] 80022a6: f022 0210 bic.w r2, r2, #16 80022aa: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80022ac: 687b ldr r3, [r7, #4] 80022ae: 2201 movs r2, #1 80022b0: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80022b4: 687b ldr r3, [r7, #4] 80022b6: 2200 movs r2, #0 80022b8: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 80022bc: 687b ldr r3, [r7, #4] 80022be: 6bdb ldr r3, [r3, #60] @ 0x3c 80022c0: 2b00 cmp r3, #0 80022c2: d003 beq.n 80022cc { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 80022c4: 687b ldr r3, [r7, #4] 80022c6: 6bdb ldr r3, [r3, #60] @ 0x3c 80022c8: 6878 ldr r0, [r7, #4] 80022ca: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 80022cc: 687b ldr r3, [r7, #4] 80022ce: 6d5b ldr r3, [r3, #84] @ 0x54 80022d0: 2b00 cmp r3, #0 80022d2: d032 beq.n 800233a { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) 80022d4: 687b ldr r3, [r7, #4] 80022d6: 6d5b ldr r3, [r3, #84] @ 0x54 80022d8: f003 0301 and.w r3, r3, #1 80022dc: 2b00 cmp r3, #0 80022de: d022 beq.n 8002326 { hdma->State = HAL_DMA_STATE_ABORT; 80022e0: 687b ldr r3, [r7, #4] 80022e2: 2205 movs r2, #5 80022e4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80022e8: 687b ldr r3, [r7, #4] 80022ea: 681b ldr r3, [r3, #0] 80022ec: 681a ldr r2, [r3, #0] 80022ee: 687b ldr r3, [r7, #4] 80022f0: 681b ldr r3, [r3, #0] 80022f2: f022 0201 bic.w r2, r2, #1 80022f6: 601a str r2, [r3, #0] do { if (++count > timeout) 80022f8: 68bb ldr r3, [r7, #8] 80022fa: 3301 adds r3, #1 80022fc: 60bb str r3, [r7, #8] 80022fe: 697a ldr r2, [r7, #20] 8002300: 429a cmp r2, r3 8002302: d307 bcc.n 8002314 { break; } } while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); 8002304: 687b ldr r3, [r7, #4] 8002306: 681b ldr r3, [r3, #0] 8002308: 681b ldr r3, [r3, #0] 800230a: f003 0301 and.w r3, r3, #1 800230e: 2b00 cmp r3, #0 8002310: d1f2 bne.n 80022f8 8002312: e000 b.n 8002316 break; 8002314: bf00 nop /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002316: 687b ldr r3, [r7, #4] 8002318: 2201 movs r2, #1 800231a: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800231e: 687b ldr r3, [r7, #4] 8002320: 2200 movs r2, #0 8002322: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 8002326: 687b ldr r3, [r7, #4] 8002328: 6cdb ldr r3, [r3, #76] @ 0x4c 800232a: 2b00 cmp r3, #0 800232c: d005 beq.n 800233a { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800232e: 687b ldr r3, [r7, #4] 8002330: 6cdb ldr r3, [r3, #76] @ 0x4c 8002332: 6878 ldr r0, [r7, #4] 8002334: 4798 blx r3 8002336: e000 b.n 800233a return; 8002338: bf00 nop } } } 800233a: 3718 adds r7, #24 800233c: 46bd mov sp, r7 800233e: bd80 pop {r7, pc} 08002340 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002340: b480 push {r7} 8002342: b085 sub sp, #20 8002344: af00 add r7, sp, #0 8002346: 60f8 str r0, [r7, #12] 8002348: 60b9 str r1, [r7, #8] 800234a: 607a str r2, [r7, #4] 800234c: 603b str r3, [r7, #0] /* Clear DBM bit */ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); 800234e: 68fb ldr r3, [r7, #12] 8002350: 681b ldr r3, [r3, #0] 8002352: 681a ldr r2, [r3, #0] 8002354: 68fb ldr r3, [r7, #12] 8002356: 681b ldr r3, [r3, #0] 8002358: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800235c: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; 800235e: 68fb ldr r3, [r7, #12] 8002360: 681b ldr r3, [r3, #0] 8002362: 683a ldr r2, [r7, #0] 8002364: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8002366: 68fb ldr r3, [r7, #12] 8002368: 689b ldr r3, [r3, #8] 800236a: 2b40 cmp r3, #64 @ 0x40 800236c: d108 bne.n 8002380 { /* Configure DMA Stream destination address */ hdma->Instance->PAR = DstAddress; 800236e: 68fb ldr r3, [r7, #12] 8002370: 681b ldr r3, [r3, #0] 8002372: 687a ldr r2, [r7, #4] 8002374: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; 8002376: 68fb ldr r3, [r7, #12] 8002378: 681b ldr r3, [r3, #0] 800237a: 68ba ldr r2, [r7, #8] 800237c: 60da str r2, [r3, #12] hdma->Instance->PAR = SrcAddress; /* Configure DMA Stream destination address */ hdma->Instance->M0AR = DstAddress; } } 800237e: e007 b.n 8002390 hdma->Instance->PAR = SrcAddress; 8002380: 68fb ldr r3, [r7, #12] 8002382: 681b ldr r3, [r3, #0] 8002384: 68ba ldr r2, [r7, #8] 8002386: 609a str r2, [r3, #8] hdma->Instance->M0AR = DstAddress; 8002388: 68fb ldr r3, [r7, #12] 800238a: 681b ldr r3, [r3, #0] 800238c: 687a ldr r2, [r7, #4] 800238e: 60da str r2, [r3, #12] } 8002390: bf00 nop 8002392: 3714 adds r7, #20 8002394: 46bd mov sp, r7 8002396: f85d 7b04 ldr.w r7, [sp], #4 800239a: 4770 bx lr 0800239c : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 800239c: b480 push {r7} 800239e: b085 sub sp, #20 80023a0: af00 add r7, sp, #0 80023a2: 6078 str r0, [r7, #4] uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; 80023a4: 687b ldr r3, [r7, #4] 80023a6: 681b ldr r3, [r3, #0] 80023a8: b2db uxtb r3, r3 80023aa: 3b10 subs r3, #16 80023ac: 4a14 ldr r2, [pc, #80] @ (8002400 ) 80023ae: fba2 2303 umull r2, r3, r2, r3 80023b2: 091b lsrs r3, r3, #4 80023b4: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number]; 80023b6: 4a13 ldr r2, [pc, #76] @ (8002404 ) 80023b8: 68fb ldr r3, [r7, #12] 80023ba: 4413 add r3, r2 80023bc: 781b ldrb r3, [r3, #0] 80023be: 461a mov r2, r3 80023c0: 687b ldr r3, [r7, #4] 80023c2: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 80023c4: 68fb ldr r3, [r7, #12] 80023c6: 2b03 cmp r3, #3 80023c8: d909 bls.n 80023de { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); 80023ca: 687b ldr r3, [r7, #4] 80023cc: 681b ldr r3, [r3, #0] 80023ce: f423 737f bic.w r3, r3, #1020 @ 0x3fc 80023d2: f023 0303 bic.w r3, r3, #3 80023d6: 1d1a adds r2, r3, #4 80023d8: 687b ldr r3, [r7, #4] 80023da: 659a str r2, [r3, #88] @ 0x58 80023dc: e007 b.n 80023ee } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); 80023de: 687b ldr r3, [r7, #4] 80023e0: 681b ldr r3, [r3, #0] 80023e2: f423 737f bic.w r3, r3, #1020 @ 0x3fc 80023e6: f023 0303 bic.w r3, r3, #3 80023ea: 687a ldr r2, [r7, #4] 80023ec: 6593 str r3, [r2, #88] @ 0x58 } return hdma->StreamBaseAddress; 80023ee: 687b ldr r3, [r7, #4] 80023f0: 6d9b ldr r3, [r3, #88] @ 0x58 } 80023f2: 4618 mov r0, r3 80023f4: 3714 adds r7, #20 80023f6: 46bd mov sp, r7 80023f8: f85d 7b04 ldr.w r7, [sp], #4 80023fc: 4770 bx lr 80023fe: bf00 nop 8002400: aaaaaaab .word 0xaaaaaaab 8002404: 0800ac44 .word 0x0800ac44 08002408 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 8002408: b480 push {r7} 800240a: b085 sub sp, #20 800240c: af00 add r7, sp, #0 800240e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002410: 2300 movs r3, #0 8002412: 73fb strb r3, [r7, #15] uint32_t tmp = hdma->Init.FIFOThreshold; 8002414: 687b ldr r3, [r7, #4] 8002416: 6a9b ldr r3, [r3, #40] @ 0x28 8002418: 60bb str r3, [r7, #8] /* Memory Data size equal to Byte */ if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 800241a: 687b ldr r3, [r7, #4] 800241c: 699b ldr r3, [r3, #24] 800241e: 2b00 cmp r3, #0 8002420: d11f bne.n 8002462 { switch (tmp) 8002422: 68bb ldr r3, [r7, #8] 8002424: 2b03 cmp r3, #3 8002426: d856 bhi.n 80024d6 8002428: a201 add r2, pc, #4 @ (adr r2, 8002430 ) 800242a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800242e: bf00 nop 8002430: 08002441 .word 0x08002441 8002434: 08002453 .word 0x08002453 8002438: 08002441 .word 0x08002441 800243c: 080024d7 .word 0x080024d7 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002440: 687b ldr r3, [r7, #4] 8002442: 6adb ldr r3, [r3, #44] @ 0x2c 8002444: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002448: 2b00 cmp r3, #0 800244a: d046 beq.n 80024da { status = HAL_ERROR; 800244c: 2301 movs r3, #1 800244e: 73fb strb r3, [r7, #15] } break; 8002450: e043 b.n 80024da case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8002452: 687b ldr r3, [r7, #4] 8002454: 6adb ldr r3, [r3, #44] @ 0x2c 8002456: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800245a: d140 bne.n 80024de { status = HAL_ERROR; 800245c: 2301 movs r3, #1 800245e: 73fb strb r3, [r7, #15] } break; 8002460: e03d b.n 80024de break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 8002462: 687b ldr r3, [r7, #4] 8002464: 699b ldr r3, [r3, #24] 8002466: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800246a: d121 bne.n 80024b0 { switch (tmp) 800246c: 68bb ldr r3, [r7, #8] 800246e: 2b03 cmp r3, #3 8002470: d837 bhi.n 80024e2 8002472: a201 add r2, pc, #4 @ (adr r2, 8002478 ) 8002474: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002478: 08002489 .word 0x08002489 800247c: 0800248f .word 0x0800248f 8002480: 08002489 .word 0x08002489 8002484: 080024a1 .word 0x080024a1 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 8002488: 2301 movs r3, #1 800248a: 73fb strb r3, [r7, #15] break; 800248c: e030 b.n 80024f0 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800248e: 687b ldr r3, [r7, #4] 8002490: 6adb ldr r3, [r3, #44] @ 0x2c 8002492: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002496: 2b00 cmp r3, #0 8002498: d025 beq.n 80024e6 { status = HAL_ERROR; 800249a: 2301 movs r3, #1 800249c: 73fb strb r3, [r7, #15] } break; 800249e: e022 b.n 80024e6 case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 80024a0: 687b ldr r3, [r7, #4] 80024a2: 6adb ldr r3, [r3, #44] @ 0x2c 80024a4: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 80024a8: d11f bne.n 80024ea { status = HAL_ERROR; 80024aa: 2301 movs r3, #1 80024ac: 73fb strb r3, [r7, #15] } break; 80024ae: e01c b.n 80024ea } /* Memory Data size equal to Word */ else { switch (tmp) 80024b0: 68bb ldr r3, [r7, #8] 80024b2: 2b02 cmp r3, #2 80024b4: d903 bls.n 80024be 80024b6: 68bb ldr r3, [r7, #8] 80024b8: 2b03 cmp r3, #3 80024ba: d003 beq.n 80024c4 { status = HAL_ERROR; } break; default: break; 80024bc: e018 b.n 80024f0 status = HAL_ERROR; 80024be: 2301 movs r3, #1 80024c0: 73fb strb r3, [r7, #15] break; 80024c2: e015 b.n 80024f0 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 80024c4: 687b ldr r3, [r7, #4] 80024c6: 6adb ldr r3, [r3, #44] @ 0x2c 80024c8: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80024cc: 2b00 cmp r3, #0 80024ce: d00e beq.n 80024ee status = HAL_ERROR; 80024d0: 2301 movs r3, #1 80024d2: 73fb strb r3, [r7, #15] break; 80024d4: e00b b.n 80024ee break; 80024d6: bf00 nop 80024d8: e00a b.n 80024f0 break; 80024da: bf00 nop 80024dc: e008 b.n 80024f0 break; 80024de: bf00 nop 80024e0: e006 b.n 80024f0 break; 80024e2: bf00 nop 80024e4: e004 b.n 80024f0 break; 80024e6: bf00 nop 80024e8: e002 b.n 80024f0 break; 80024ea: bf00 nop 80024ec: e000 b.n 80024f0 break; 80024ee: bf00 nop } } return status; 80024f0: 7bfb ldrb r3, [r7, #15] } 80024f2: 4618 mov r0, r3 80024f4: 3714 adds r7, #20 80024f6: 46bd mov sp, r7 80024f8: f85d 7b04 ldr.w r7, [sp], #4 80024fc: 4770 bx lr 80024fe: bf00 nop 08002500 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8002500: b480 push {r7} 8002502: b089 sub sp, #36 @ 0x24 8002504: af00 add r7, sp, #0 8002506: 6078 str r0, [r7, #4] 8002508: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 800250a: 2300 movs r3, #0 800250c: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 800250e: 2300 movs r3, #0 8002510: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 8002512: 2300 movs r3, #0 8002514: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 8002516: 2300 movs r3, #0 8002518: 61fb str r3, [r7, #28] 800251a: e165 b.n 80027e8 { /* Get the IO position */ ioposition = 0x01U << position; 800251c: 2201 movs r2, #1 800251e: 69fb ldr r3, [r7, #28] 8002520: fa02 f303 lsl.w r3, r2, r3 8002524: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8002526: 683b ldr r3, [r7, #0] 8002528: 681b ldr r3, [r3, #0] 800252a: 697a ldr r2, [r7, #20] 800252c: 4013 ands r3, r2 800252e: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8002530: 693a ldr r2, [r7, #16] 8002532: 697b ldr r3, [r7, #20] 8002534: 429a cmp r2, r3 8002536: f040 8154 bne.w 80027e2 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 800253a: 683b ldr r3, [r7, #0] 800253c: 685b ldr r3, [r3, #4] 800253e: f003 0303 and.w r3, r3, #3 8002542: 2b01 cmp r3, #1 8002544: d005 beq.n 8002552 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002546: 683b ldr r3, [r7, #0] 8002548: 685b ldr r3, [r3, #4] 800254a: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 800254e: 2b02 cmp r3, #2 8002550: d130 bne.n 80025b4 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8002552: 687b ldr r3, [r7, #4] 8002554: 689b ldr r3, [r3, #8] 8002556: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8002558: 69fb ldr r3, [r7, #28] 800255a: 005b lsls r3, r3, #1 800255c: 2203 movs r2, #3 800255e: fa02 f303 lsl.w r3, r2, r3 8002562: 43db mvns r3, r3 8002564: 69ba ldr r2, [r7, #24] 8002566: 4013 ands r3, r2 8002568: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800256a: 683b ldr r3, [r7, #0] 800256c: 68da ldr r2, [r3, #12] 800256e: 69fb ldr r3, [r7, #28] 8002570: 005b lsls r3, r3, #1 8002572: fa02 f303 lsl.w r3, r2, r3 8002576: 69ba ldr r2, [r7, #24] 8002578: 4313 orrs r3, r2 800257a: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800257c: 687b ldr r3, [r7, #4] 800257e: 69ba ldr r2, [r7, #24] 8002580: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8002582: 687b ldr r3, [r7, #4] 8002584: 685b ldr r3, [r3, #4] 8002586: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8002588: 2201 movs r2, #1 800258a: 69fb ldr r3, [r7, #28] 800258c: fa02 f303 lsl.w r3, r2, r3 8002590: 43db mvns r3, r3 8002592: 69ba ldr r2, [r7, #24] 8002594: 4013 ands r3, r2 8002596: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8002598: 683b ldr r3, [r7, #0] 800259a: 685b ldr r3, [r3, #4] 800259c: 091b lsrs r3, r3, #4 800259e: f003 0201 and.w r2, r3, #1 80025a2: 69fb ldr r3, [r7, #28] 80025a4: fa02 f303 lsl.w r3, r2, r3 80025a8: 69ba ldr r2, [r7, #24] 80025aa: 4313 orrs r3, r2 80025ac: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 80025ae: 687b ldr r3, [r7, #4] 80025b0: 69ba ldr r2, [r7, #24] 80025b2: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 80025b4: 683b ldr r3, [r7, #0] 80025b6: 685b ldr r3, [r3, #4] 80025b8: f003 0303 and.w r3, r3, #3 80025bc: 2b03 cmp r3, #3 80025be: d017 beq.n 80025f0 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 80025c0: 687b ldr r3, [r7, #4] 80025c2: 68db ldr r3, [r3, #12] 80025c4: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 80025c6: 69fb ldr r3, [r7, #28] 80025c8: 005b lsls r3, r3, #1 80025ca: 2203 movs r2, #3 80025cc: fa02 f303 lsl.w r3, r2, r3 80025d0: 43db mvns r3, r3 80025d2: 69ba ldr r2, [r7, #24] 80025d4: 4013 ands r3, r2 80025d6: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 80025d8: 683b ldr r3, [r7, #0] 80025da: 689a ldr r2, [r3, #8] 80025dc: 69fb ldr r3, [r7, #28] 80025de: 005b lsls r3, r3, #1 80025e0: fa02 f303 lsl.w r3, r2, r3 80025e4: 69ba ldr r2, [r7, #24] 80025e6: 4313 orrs r3, r2 80025e8: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 80025ea: 687b ldr r3, [r7, #4] 80025ec: 69ba ldr r2, [r7, #24] 80025ee: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80025f0: 683b ldr r3, [r7, #0] 80025f2: 685b ldr r3, [r3, #4] 80025f4: f003 0303 and.w r3, r3, #3 80025f8: 2b02 cmp r3, #2 80025fa: d123 bne.n 8002644 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 80025fc: 69fb ldr r3, [r7, #28] 80025fe: 08da lsrs r2, r3, #3 8002600: 687b ldr r3, [r7, #4] 8002602: 3208 adds r2, #8 8002604: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8002608: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 800260a: 69fb ldr r3, [r7, #28] 800260c: f003 0307 and.w r3, r3, #7 8002610: 009b lsls r3, r3, #2 8002612: 220f movs r2, #15 8002614: fa02 f303 lsl.w r3, r2, r3 8002618: 43db mvns r3, r3 800261a: 69ba ldr r2, [r7, #24] 800261c: 4013 ands r3, r2 800261e: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 8002620: 683b ldr r3, [r7, #0] 8002622: 691a ldr r2, [r3, #16] 8002624: 69fb ldr r3, [r7, #28] 8002626: f003 0307 and.w r3, r3, #7 800262a: 009b lsls r3, r3, #2 800262c: fa02 f303 lsl.w r3, r2, r3 8002630: 69ba ldr r2, [r7, #24] 8002632: 4313 orrs r3, r2 8002634: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8002636: 69fb ldr r3, [r7, #28] 8002638: 08da lsrs r2, r3, #3 800263a: 687b ldr r3, [r7, #4] 800263c: 3208 adds r2, #8 800263e: 69b9 ldr r1, [r7, #24] 8002640: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8002644: 687b ldr r3, [r7, #4] 8002646: 681b ldr r3, [r3, #0] 8002648: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 800264a: 69fb ldr r3, [r7, #28] 800264c: 005b lsls r3, r3, #1 800264e: 2203 movs r2, #3 8002650: fa02 f303 lsl.w r3, r2, r3 8002654: 43db mvns r3, r3 8002656: 69ba ldr r2, [r7, #24] 8002658: 4013 ands r3, r2 800265a: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800265c: 683b ldr r3, [r7, #0] 800265e: 685b ldr r3, [r3, #4] 8002660: f003 0203 and.w r2, r3, #3 8002664: 69fb ldr r3, [r7, #28] 8002666: 005b lsls r3, r3, #1 8002668: fa02 f303 lsl.w r3, r2, r3 800266c: 69ba ldr r2, [r7, #24] 800266e: 4313 orrs r3, r2 8002670: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8002672: 687b ldr r3, [r7, #4] 8002674: 69ba ldr r2, [r7, #24] 8002676: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8002678: 683b ldr r3, [r7, #0] 800267a: 685b ldr r3, [r3, #4] 800267c: f403 3340 and.w r3, r3, #196608 @ 0x30000 8002680: 2b00 cmp r3, #0 8002682: f000 80ae beq.w 80027e2 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002686: 2300 movs r3, #0 8002688: 60fb str r3, [r7, #12] 800268a: 4b5d ldr r3, [pc, #372] @ (8002800 ) 800268c: 6c5b ldr r3, [r3, #68] @ 0x44 800268e: 4a5c ldr r2, [pc, #368] @ (8002800 ) 8002690: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002694: 6453 str r3, [r2, #68] @ 0x44 8002696: 4b5a ldr r3, [pc, #360] @ (8002800 ) 8002698: 6c5b ldr r3, [r3, #68] @ 0x44 800269a: f403 4380 and.w r3, r3, #16384 @ 0x4000 800269e: 60fb str r3, [r7, #12] 80026a0: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 80026a2: 4a58 ldr r2, [pc, #352] @ (8002804 ) 80026a4: 69fb ldr r3, [r7, #28] 80026a6: 089b lsrs r3, r3, #2 80026a8: 3302 adds r3, #2 80026aa: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80026ae: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 80026b0: 69fb ldr r3, [r7, #28] 80026b2: f003 0303 and.w r3, r3, #3 80026b6: 009b lsls r3, r3, #2 80026b8: 220f movs r2, #15 80026ba: fa02 f303 lsl.w r3, r2, r3 80026be: 43db mvns r3, r3 80026c0: 69ba ldr r2, [r7, #24] 80026c2: 4013 ands r3, r2 80026c4: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 80026c6: 687b ldr r3, [r7, #4] 80026c8: 4a4f ldr r2, [pc, #316] @ (8002808 ) 80026ca: 4293 cmp r3, r2 80026cc: d025 beq.n 800271a 80026ce: 687b ldr r3, [r7, #4] 80026d0: 4a4e ldr r2, [pc, #312] @ (800280c ) 80026d2: 4293 cmp r3, r2 80026d4: d01f beq.n 8002716 80026d6: 687b ldr r3, [r7, #4] 80026d8: 4a4d ldr r2, [pc, #308] @ (8002810 ) 80026da: 4293 cmp r3, r2 80026dc: d019 beq.n 8002712 80026de: 687b ldr r3, [r7, #4] 80026e0: 4a4c ldr r2, [pc, #304] @ (8002814 ) 80026e2: 4293 cmp r3, r2 80026e4: d013 beq.n 800270e 80026e6: 687b ldr r3, [r7, #4] 80026e8: 4a4b ldr r2, [pc, #300] @ (8002818 ) 80026ea: 4293 cmp r3, r2 80026ec: d00d beq.n 800270a 80026ee: 687b ldr r3, [r7, #4] 80026f0: 4a4a ldr r2, [pc, #296] @ (800281c ) 80026f2: 4293 cmp r3, r2 80026f4: d007 beq.n 8002706 80026f6: 687b ldr r3, [r7, #4] 80026f8: 4a49 ldr r2, [pc, #292] @ (8002820 ) 80026fa: 4293 cmp r3, r2 80026fc: d101 bne.n 8002702 80026fe: 2306 movs r3, #6 8002700: e00c b.n 800271c 8002702: 2307 movs r3, #7 8002704: e00a b.n 800271c 8002706: 2305 movs r3, #5 8002708: e008 b.n 800271c 800270a: 2304 movs r3, #4 800270c: e006 b.n 800271c 800270e: 2303 movs r3, #3 8002710: e004 b.n 800271c 8002712: 2302 movs r3, #2 8002714: e002 b.n 800271c 8002716: 2301 movs r3, #1 8002718: e000 b.n 800271c 800271a: 2300 movs r3, #0 800271c: 69fa ldr r2, [r7, #28] 800271e: f002 0203 and.w r2, r2, #3 8002722: 0092 lsls r2, r2, #2 8002724: 4093 lsls r3, r2 8002726: 69ba ldr r2, [r7, #24] 8002728: 4313 orrs r3, r2 800272a: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 800272c: 4935 ldr r1, [pc, #212] @ (8002804 ) 800272e: 69fb ldr r3, [r7, #28] 8002730: 089b lsrs r3, r3, #2 8002732: 3302 adds r3, #2 8002734: 69ba ldr r2, [r7, #24] 8002736: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 800273a: 4b3a ldr r3, [pc, #232] @ (8002824 ) 800273c: 689b ldr r3, [r3, #8] 800273e: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002740: 693b ldr r3, [r7, #16] 8002742: 43db mvns r3, r3 8002744: 69ba ldr r2, [r7, #24] 8002746: 4013 ands r3, r2 8002748: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800274a: 683b ldr r3, [r7, #0] 800274c: 685b ldr r3, [r3, #4] 800274e: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8002752: 2b00 cmp r3, #0 8002754: d003 beq.n 800275e { temp |= iocurrent; 8002756: 69ba ldr r2, [r7, #24] 8002758: 693b ldr r3, [r7, #16] 800275a: 4313 orrs r3, r2 800275c: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 800275e: 4a31 ldr r2, [pc, #196] @ (8002824 ) 8002760: 69bb ldr r3, [r7, #24] 8002762: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8002764: 4b2f ldr r3, [pc, #188] @ (8002824 ) 8002766: 68db ldr r3, [r3, #12] 8002768: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 800276a: 693b ldr r3, [r7, #16] 800276c: 43db mvns r3, r3 800276e: 69ba ldr r2, [r7, #24] 8002770: 4013 ands r3, r2 8002772: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8002774: 683b ldr r3, [r7, #0] 8002776: 685b ldr r3, [r3, #4] 8002778: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800277c: 2b00 cmp r3, #0 800277e: d003 beq.n 8002788 { temp |= iocurrent; 8002780: 69ba ldr r2, [r7, #24] 8002782: 693b ldr r3, [r7, #16] 8002784: 4313 orrs r3, r2 8002786: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8002788: 4a26 ldr r2, [pc, #152] @ (8002824 ) 800278a: 69bb ldr r3, [r7, #24] 800278c: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 800278e: 4b25 ldr r3, [pc, #148] @ (8002824 ) 8002790: 685b ldr r3, [r3, #4] 8002792: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002794: 693b ldr r3, [r7, #16] 8002796: 43db mvns r3, r3 8002798: 69ba ldr r2, [r7, #24] 800279a: 4013 ands r3, r2 800279c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800279e: 683b ldr r3, [r7, #0] 80027a0: 685b ldr r3, [r3, #4] 80027a2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80027a6: 2b00 cmp r3, #0 80027a8: d003 beq.n 80027b2 { temp |= iocurrent; 80027aa: 69ba ldr r2, [r7, #24] 80027ac: 693b ldr r3, [r7, #16] 80027ae: 4313 orrs r3, r2 80027b0: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 80027b2: 4a1c ldr r2, [pc, #112] @ (8002824 ) 80027b4: 69bb ldr r3, [r7, #24] 80027b6: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 80027b8: 4b1a ldr r3, [pc, #104] @ (8002824 ) 80027ba: 681b ldr r3, [r3, #0] 80027bc: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 80027be: 693b ldr r3, [r7, #16] 80027c0: 43db mvns r3, r3 80027c2: 69ba ldr r2, [r7, #24] 80027c4: 4013 ands r3, r2 80027c6: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 80027c8: 683b ldr r3, [r7, #0] 80027ca: 685b ldr r3, [r3, #4] 80027cc: f403 3380 and.w r3, r3, #65536 @ 0x10000 80027d0: 2b00 cmp r3, #0 80027d2: d003 beq.n 80027dc { temp |= iocurrent; 80027d4: 69ba ldr r2, [r7, #24] 80027d6: 693b ldr r3, [r7, #16] 80027d8: 4313 orrs r3, r2 80027da: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 80027dc: 4a11 ldr r2, [pc, #68] @ (8002824 ) 80027de: 69bb ldr r3, [r7, #24] 80027e0: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 80027e2: 69fb ldr r3, [r7, #28] 80027e4: 3301 adds r3, #1 80027e6: 61fb str r3, [r7, #28] 80027e8: 69fb ldr r3, [r7, #28] 80027ea: 2b0f cmp r3, #15 80027ec: f67f ae96 bls.w 800251c } } } } 80027f0: bf00 nop 80027f2: bf00 nop 80027f4: 3724 adds r7, #36 @ 0x24 80027f6: 46bd mov sp, r7 80027f8: f85d 7b04 ldr.w r7, [sp], #4 80027fc: 4770 bx lr 80027fe: bf00 nop 8002800: 40023800 .word 0x40023800 8002804: 40013800 .word 0x40013800 8002808: 40020000 .word 0x40020000 800280c: 40020400 .word 0x40020400 8002810: 40020800 .word 0x40020800 8002814: 40020c00 .word 0x40020c00 8002818: 40021000 .word 0x40021000 800281c: 40021400 .word 0x40021400 8002820: 40021800 .word 0x40021800 8002824: 40013c00 .word 0x40013c00 08002828 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8002828: b480 push {r7} 800282a: b085 sub sp, #20 800282c: af00 add r7, sp, #0 800282e: 6078 str r0, [r7, #4] 8002830: 460b mov r3, r1 8002832: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8002834: 687b ldr r3, [r7, #4] 8002836: 691a ldr r2, [r3, #16] 8002838: 887b ldrh r3, [r7, #2] 800283a: 4013 ands r3, r2 800283c: 2b00 cmp r3, #0 800283e: d002 beq.n 8002846 { bitstatus = GPIO_PIN_SET; 8002840: 2301 movs r3, #1 8002842: 73fb strb r3, [r7, #15] 8002844: e001 b.n 800284a } else { bitstatus = GPIO_PIN_RESET; 8002846: 2300 movs r3, #0 8002848: 73fb strb r3, [r7, #15] } return bitstatus; 800284a: 7bfb ldrb r3, [r7, #15] } 800284c: 4618 mov r0, r3 800284e: 3714 adds r7, #20 8002850: 46bd mov sp, r7 8002852: f85d 7b04 ldr.w r7, [sp], #4 8002856: 4770 bx lr 08002858 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8002858: b480 push {r7} 800285a: b083 sub sp, #12 800285c: af00 add r7, sp, #0 800285e: 6078 str r0, [r7, #4] 8002860: 460b mov r3, r1 8002862: 807b strh r3, [r7, #2] 8002864: 4613 mov r3, r2 8002866: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8002868: 787b ldrb r3, [r7, #1] 800286a: 2b00 cmp r3, #0 800286c: d003 beq.n 8002876 { GPIOx->BSRR = GPIO_Pin; 800286e: 887a ldrh r2, [r7, #2] 8002870: 687b ldr r3, [r7, #4] 8002872: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8002874: e003 b.n 800287e GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8002876: 887b ldrh r3, [r7, #2] 8002878: 041a lsls r2, r3, #16 800287a: 687b ldr r3, [r7, #4] 800287c: 619a str r2, [r3, #24] } 800287e: bf00 nop 8002880: 370c adds r7, #12 8002882: 46bd mov sp, r7 8002884: f85d 7b04 ldr.w r7, [sp], #4 8002888: 4770 bx lr ... 0800288c : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 800288c: b580 push {r7, lr} 800288e: b084 sub sp, #16 8002890: af00 add r7, sp, #0 8002892: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8002894: 687b ldr r3, [r7, #4] 8002896: 2b00 cmp r3, #0 8002898: d101 bne.n 800289e { return HAL_ERROR; 800289a: 2301 movs r3, #1 800289c: e12b b.n 8002af6 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 800289e: 687b ldr r3, [r7, #4] 80028a0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80028a4: b2db uxtb r3, r3 80028a6: 2b00 cmp r3, #0 80028a8: d106 bne.n 80028b8 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 80028aa: 687b ldr r3, [r7, #4] 80028ac: 2200 movs r2, #0 80028ae: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 80028b2: 6878 ldr r0, [r7, #4] 80028b4: f7fd ff70 bl 8000798 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 80028b8: 687b ldr r3, [r7, #4] 80028ba: 2224 movs r2, #36 @ 0x24 80028bc: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 80028c0: 687b ldr r3, [r7, #4] 80028c2: 681b ldr r3, [r3, #0] 80028c4: 681a ldr r2, [r3, #0] 80028c6: 687b ldr r3, [r7, #4] 80028c8: 681b ldr r3, [r3, #0] 80028ca: f022 0201 bic.w r2, r2, #1 80028ce: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 80028d0: 687b ldr r3, [r7, #4] 80028d2: 681b ldr r3, [r3, #0] 80028d4: 681a ldr r2, [r3, #0] 80028d6: 687b ldr r3, [r7, #4] 80028d8: 681b ldr r3, [r3, #0] 80028da: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80028de: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 80028e0: 687b ldr r3, [r7, #4] 80028e2: 681b ldr r3, [r3, #0] 80028e4: 681a ldr r2, [r3, #0] 80028e6: 687b ldr r3, [r7, #4] 80028e8: 681b ldr r3, [r3, #0] 80028ea: f422 4200 bic.w r2, r2, #32768 @ 0x8000 80028ee: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 80028f0: f001 fc88 bl 8004204 80028f4: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 80028f6: 687b ldr r3, [r7, #4] 80028f8: 685b ldr r3, [r3, #4] 80028fa: 4a81 ldr r2, [pc, #516] @ (8002b00 ) 80028fc: 4293 cmp r3, r2 80028fe: d807 bhi.n 8002910 8002900: 68fb ldr r3, [r7, #12] 8002902: 4a80 ldr r2, [pc, #512] @ (8002b04 ) 8002904: 4293 cmp r3, r2 8002906: bf94 ite ls 8002908: 2301 movls r3, #1 800290a: 2300 movhi r3, #0 800290c: b2db uxtb r3, r3 800290e: e006 b.n 800291e 8002910: 68fb ldr r3, [r7, #12] 8002912: 4a7d ldr r2, [pc, #500] @ (8002b08 ) 8002914: 4293 cmp r3, r2 8002916: bf94 ite ls 8002918: 2301 movls r3, #1 800291a: 2300 movhi r3, #0 800291c: b2db uxtb r3, r3 800291e: 2b00 cmp r3, #0 8002920: d001 beq.n 8002926 { return HAL_ERROR; 8002922: 2301 movs r3, #1 8002924: e0e7 b.n 8002af6 } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 8002926: 68fb ldr r3, [r7, #12] 8002928: 4a78 ldr r2, [pc, #480] @ (8002b0c ) 800292a: fba2 2303 umull r2, r3, r2, r3 800292e: 0c9b lsrs r3, r3, #18 8002930: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8002932: 687b ldr r3, [r7, #4] 8002934: 681b ldr r3, [r3, #0] 8002936: 685b ldr r3, [r3, #4] 8002938: f023 013f bic.w r1, r3, #63 @ 0x3f 800293c: 687b ldr r3, [r7, #4] 800293e: 681b ldr r3, [r3, #0] 8002940: 68ba ldr r2, [r7, #8] 8002942: 430a orrs r2, r1 8002944: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 8002946: 687b ldr r3, [r7, #4] 8002948: 681b ldr r3, [r3, #0] 800294a: 6a1b ldr r3, [r3, #32] 800294c: f023 013f bic.w r1, r3, #63 @ 0x3f 8002950: 687b ldr r3, [r7, #4] 8002952: 685b ldr r3, [r3, #4] 8002954: 4a6a ldr r2, [pc, #424] @ (8002b00 ) 8002956: 4293 cmp r3, r2 8002958: d802 bhi.n 8002960 800295a: 68bb ldr r3, [r7, #8] 800295c: 3301 adds r3, #1 800295e: e009 b.n 8002974 8002960: 68bb ldr r3, [r7, #8] 8002962: f44f 7296 mov.w r2, #300 @ 0x12c 8002966: fb02 f303 mul.w r3, r2, r3 800296a: 4a69 ldr r2, [pc, #420] @ (8002b10 ) 800296c: fba2 2303 umull r2, r3, r2, r3 8002970: 099b lsrs r3, r3, #6 8002972: 3301 adds r3, #1 8002974: 687a ldr r2, [r7, #4] 8002976: 6812 ldr r2, [r2, #0] 8002978: 430b orrs r3, r1 800297a: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 800297c: 687b ldr r3, [r7, #4] 800297e: 681b ldr r3, [r3, #0] 8002980: 69db ldr r3, [r3, #28] 8002982: f423 424f bic.w r2, r3, #52992 @ 0xcf00 8002986: f022 02ff bic.w r2, r2, #255 @ 0xff 800298a: 687b ldr r3, [r7, #4] 800298c: 685b ldr r3, [r3, #4] 800298e: 495c ldr r1, [pc, #368] @ (8002b00 ) 8002990: 428b cmp r3, r1 8002992: d819 bhi.n 80029c8 8002994: 68fb ldr r3, [r7, #12] 8002996: 1e59 subs r1, r3, #1 8002998: 687b ldr r3, [r7, #4] 800299a: 685b ldr r3, [r3, #4] 800299c: 005b lsls r3, r3, #1 800299e: fbb1 f3f3 udiv r3, r1, r3 80029a2: 1c59 adds r1, r3, #1 80029a4: f640 73fc movw r3, #4092 @ 0xffc 80029a8: 400b ands r3, r1 80029aa: 2b00 cmp r3, #0 80029ac: d00a beq.n 80029c4 80029ae: 68fb ldr r3, [r7, #12] 80029b0: 1e59 subs r1, r3, #1 80029b2: 687b ldr r3, [r7, #4] 80029b4: 685b ldr r3, [r3, #4] 80029b6: 005b lsls r3, r3, #1 80029b8: fbb1 f3f3 udiv r3, r1, r3 80029bc: 3301 adds r3, #1 80029be: f3c3 030b ubfx r3, r3, #0, #12 80029c2: e051 b.n 8002a68 80029c4: 2304 movs r3, #4 80029c6: e04f b.n 8002a68 80029c8: 687b ldr r3, [r7, #4] 80029ca: 689b ldr r3, [r3, #8] 80029cc: 2b00 cmp r3, #0 80029ce: d111 bne.n 80029f4 80029d0: 68fb ldr r3, [r7, #12] 80029d2: 1e58 subs r0, r3, #1 80029d4: 687b ldr r3, [r7, #4] 80029d6: 6859 ldr r1, [r3, #4] 80029d8: 460b mov r3, r1 80029da: 005b lsls r3, r3, #1 80029dc: 440b add r3, r1 80029de: fbb0 f3f3 udiv r3, r0, r3 80029e2: 3301 adds r3, #1 80029e4: f3c3 030b ubfx r3, r3, #0, #12 80029e8: 2b00 cmp r3, #0 80029ea: bf0c ite eq 80029ec: 2301 moveq r3, #1 80029ee: 2300 movne r3, #0 80029f0: b2db uxtb r3, r3 80029f2: e012 b.n 8002a1a 80029f4: 68fb ldr r3, [r7, #12] 80029f6: 1e58 subs r0, r3, #1 80029f8: 687b ldr r3, [r7, #4] 80029fa: 6859 ldr r1, [r3, #4] 80029fc: 460b mov r3, r1 80029fe: 009b lsls r3, r3, #2 8002a00: 440b add r3, r1 8002a02: 0099 lsls r1, r3, #2 8002a04: 440b add r3, r1 8002a06: fbb0 f3f3 udiv r3, r0, r3 8002a0a: 3301 adds r3, #1 8002a0c: f3c3 030b ubfx r3, r3, #0, #12 8002a10: 2b00 cmp r3, #0 8002a12: bf0c ite eq 8002a14: 2301 moveq r3, #1 8002a16: 2300 movne r3, #0 8002a18: b2db uxtb r3, r3 8002a1a: 2b00 cmp r3, #0 8002a1c: d001 beq.n 8002a22 8002a1e: 2301 movs r3, #1 8002a20: e022 b.n 8002a68 8002a22: 687b ldr r3, [r7, #4] 8002a24: 689b ldr r3, [r3, #8] 8002a26: 2b00 cmp r3, #0 8002a28: d10e bne.n 8002a48 8002a2a: 68fb ldr r3, [r7, #12] 8002a2c: 1e58 subs r0, r3, #1 8002a2e: 687b ldr r3, [r7, #4] 8002a30: 6859 ldr r1, [r3, #4] 8002a32: 460b mov r3, r1 8002a34: 005b lsls r3, r3, #1 8002a36: 440b add r3, r1 8002a38: fbb0 f3f3 udiv r3, r0, r3 8002a3c: 3301 adds r3, #1 8002a3e: f3c3 030b ubfx r3, r3, #0, #12 8002a42: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8002a46: e00f b.n 8002a68 8002a48: 68fb ldr r3, [r7, #12] 8002a4a: 1e58 subs r0, r3, #1 8002a4c: 687b ldr r3, [r7, #4] 8002a4e: 6859 ldr r1, [r3, #4] 8002a50: 460b mov r3, r1 8002a52: 009b lsls r3, r3, #2 8002a54: 440b add r3, r1 8002a56: 0099 lsls r1, r3, #2 8002a58: 440b add r3, r1 8002a5a: fbb0 f3f3 udiv r3, r0, r3 8002a5e: 3301 adds r3, #1 8002a60: f3c3 030b ubfx r3, r3, #0, #12 8002a64: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8002a68: 6879 ldr r1, [r7, #4] 8002a6a: 6809 ldr r1, [r1, #0] 8002a6c: 4313 orrs r3, r2 8002a6e: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8002a70: 687b ldr r3, [r7, #4] 8002a72: 681b ldr r3, [r3, #0] 8002a74: 681b ldr r3, [r3, #0] 8002a76: f023 01c0 bic.w r1, r3, #192 @ 0xc0 8002a7a: 687b ldr r3, [r7, #4] 8002a7c: 69da ldr r2, [r3, #28] 8002a7e: 687b ldr r3, [r7, #4] 8002a80: 6a1b ldr r3, [r3, #32] 8002a82: 431a orrs r2, r3 8002a84: 687b ldr r3, [r7, #4] 8002a86: 681b ldr r3, [r3, #0] 8002a88: 430a orrs r2, r1 8002a8a: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 8002a8c: 687b ldr r3, [r7, #4] 8002a8e: 681b ldr r3, [r3, #0] 8002a90: 689b ldr r3, [r3, #8] 8002a92: f423 4303 bic.w r3, r3, #33536 @ 0x8300 8002a96: f023 03ff bic.w r3, r3, #255 @ 0xff 8002a9a: 687a ldr r2, [r7, #4] 8002a9c: 6911 ldr r1, [r2, #16] 8002a9e: 687a ldr r2, [r7, #4] 8002aa0: 68d2 ldr r2, [r2, #12] 8002aa2: 4311 orrs r1, r2 8002aa4: 687a ldr r2, [r7, #4] 8002aa6: 6812 ldr r2, [r2, #0] 8002aa8: 430b orrs r3, r1 8002aaa: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 8002aac: 687b ldr r3, [r7, #4] 8002aae: 681b ldr r3, [r3, #0] 8002ab0: 68db ldr r3, [r3, #12] 8002ab2: f023 01ff bic.w r1, r3, #255 @ 0xff 8002ab6: 687b ldr r3, [r7, #4] 8002ab8: 695a ldr r2, [r3, #20] 8002aba: 687b ldr r3, [r7, #4] 8002abc: 699b ldr r3, [r3, #24] 8002abe: 431a orrs r2, r3 8002ac0: 687b ldr r3, [r7, #4] 8002ac2: 681b ldr r3, [r3, #0] 8002ac4: 430a orrs r2, r1 8002ac6: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002ac8: 687b ldr r3, [r7, #4] 8002aca: 681b ldr r3, [r3, #0] 8002acc: 681a ldr r2, [r3, #0] 8002ace: 687b ldr r3, [r7, #4] 8002ad0: 681b ldr r3, [r3, #0] 8002ad2: f042 0201 orr.w r2, r2, #1 8002ad6: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002ad8: 687b ldr r3, [r7, #4] 8002ada: 2200 movs r2, #0 8002adc: 641a str r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_READY; 8002ade: 687b ldr r3, [r7, #4] 8002ae0: 2220 movs r2, #32 8002ae2: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->PreviousState = I2C_STATE_NONE; 8002ae6: 687b ldr r3, [r7, #4] 8002ae8: 2200 movs r2, #0 8002aea: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8002aec: 687b ldr r3, [r7, #4] 8002aee: 2200 movs r2, #0 8002af0: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 8002af4: 2300 movs r3, #0 } 8002af6: 4618 mov r0, r3 8002af8: 3710 adds r7, #16 8002afa: 46bd mov sp, r7 8002afc: bd80 pop {r7, pc} 8002afe: bf00 nop 8002b00: 000186a0 .word 0x000186a0 8002b04: 001e847f .word 0x001e847f 8002b08: 003d08ff .word 0x003d08ff 8002b0c: 431bde83 .word 0x431bde83 8002b10: 10624dd3 .word 0x10624dd3 08002b14 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8002b14: b580 push {r7, lr} 8002b16: b086 sub sp, #24 8002b18: af02 add r7, sp, #8 8002b1a: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx; #endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8002b1c: 687b ldr r3, [r7, #4] 8002b1e: 2b00 cmp r3, #0 8002b20: d101 bne.n 8002b26 { return HAL_ERROR; 8002b22: 2301 movs r3, #1 8002b24: e108 b.n 8002d38 /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); #if defined (USB_OTG_FS) USBx = hpcd->Instance; 8002b26: 687b ldr r3, [r7, #4] 8002b28: 681b ldr r3, [r3, #0] 8002b2a: 60bb str r3, [r7, #8] #endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) 8002b2c: 687b ldr r3, [r7, #4] 8002b2e: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495 8002b32: b2db uxtb r3, r3 8002b34: 2b00 cmp r3, #0 8002b36: d106 bne.n 8002b46 { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 8002b38: 687b ldr r3, [r7, #4] 8002b3a: 2200 movs r2, #0 8002b3c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8002b40: 6878 ldr r0, [r7, #4] 8002b42: f007 fca9 bl 800a498 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8002b46: 687b ldr r3, [r7, #4] 8002b48: 2203 movs r2, #3 8002b4a: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ if (USBx == USB_OTG_FS) 8002b4e: 68bb ldr r3, [r7, #8] 8002b50: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002b54: d102 bne.n 8002b5c { hpcd->Init.dma_enable = 0U; 8002b56: 687b ldr r3, [r7, #4] 8002b58: 2200 movs r2, #0 8002b5a: 719a strb r2, [r3, #6] } #endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8002b5c: 687b ldr r3, [r7, #4] 8002b5e: 681b ldr r3, [r3, #0] 8002b60: 4618 mov r0, r3 8002b62: f004 fb9e bl 80072a2 /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002b66: 687b ldr r3, [r7, #4] 8002b68: 6818 ldr r0, [r3, #0] 8002b6a: 687b ldr r3, [r7, #4] 8002b6c: 7c1a ldrb r2, [r3, #16] 8002b6e: f88d 2000 strb.w r2, [sp] 8002b72: 3304 adds r3, #4 8002b74: cb0e ldmia r3, {r1, r2, r3} 8002b76: f004 fa7d bl 8007074 8002b7a: 4603 mov r3, r0 8002b7c: 2b00 cmp r3, #0 8002b7e: d005 beq.n 8002b8c { hpcd->State = HAL_PCD_STATE_ERROR; 8002b80: 687b ldr r3, [r7, #4] 8002b82: 2202 movs r2, #2 8002b84: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002b88: 2301 movs r3, #1 8002b8a: e0d5 b.n 8002d38 } /* Force Device Mode */ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) 8002b8c: 687b ldr r3, [r7, #4] 8002b8e: 681b ldr r3, [r3, #0] 8002b90: 2100 movs r1, #0 8002b92: 4618 mov r0, r3 8002b94: f004 fb96 bl 80072c4 8002b98: 4603 mov r3, r0 8002b9a: 2b00 cmp r3, #0 8002b9c: d005 beq.n 8002baa { hpcd->State = HAL_PCD_STATE_ERROR; 8002b9e: 687b ldr r3, [r7, #4] 8002ba0: 2202 movs r2, #2 8002ba2: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002ba6: 2301 movs r3, #1 8002ba8: e0c6 b.n 8002d38 } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002baa: 2300 movs r3, #0 8002bac: 73fb strb r3, [r7, #15] 8002bae: e04a b.n 8002c46 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8002bb0: 7bfa ldrb r2, [r7, #15] 8002bb2: 6879 ldr r1, [r7, #4] 8002bb4: 4613 mov r3, r2 8002bb6: 00db lsls r3, r3, #3 8002bb8: 4413 add r3, r2 8002bba: 009b lsls r3, r3, #2 8002bbc: 440b add r3, r1 8002bbe: 3315 adds r3, #21 8002bc0: 2201 movs r2, #1 8002bc2: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8002bc4: 7bfa ldrb r2, [r7, #15] 8002bc6: 6879 ldr r1, [r7, #4] 8002bc8: 4613 mov r3, r2 8002bca: 00db lsls r3, r3, #3 8002bcc: 4413 add r3, r2 8002bce: 009b lsls r3, r3, #2 8002bd0: 440b add r3, r1 8002bd2: 3314 adds r3, #20 8002bd4: 7bfa ldrb r2, [r7, #15] 8002bd6: 701a strb r2, [r3, #0] hpcd->IN_ep[i].tx_fifo_num = i; 8002bd8: 7bfa ldrb r2, [r7, #15] 8002bda: 7bfb ldrb r3, [r7, #15] 8002bdc: b298 uxth r0, r3 8002bde: 6879 ldr r1, [r7, #4] 8002be0: 4613 mov r3, r2 8002be2: 00db lsls r3, r3, #3 8002be4: 4413 add r3, r2 8002be6: 009b lsls r3, r3, #2 8002be8: 440b add r3, r1 8002bea: 332e adds r3, #46 @ 0x2e 8002bec: 4602 mov r2, r0 8002bee: 801a strh r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 8002bf0: 7bfa ldrb r2, [r7, #15] 8002bf2: 6879 ldr r1, [r7, #4] 8002bf4: 4613 mov r3, r2 8002bf6: 00db lsls r3, r3, #3 8002bf8: 4413 add r3, r2 8002bfa: 009b lsls r3, r3, #2 8002bfc: 440b add r3, r1 8002bfe: 3318 adds r3, #24 8002c00: 2200 movs r2, #0 8002c02: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8002c04: 7bfa ldrb r2, [r7, #15] 8002c06: 6879 ldr r1, [r7, #4] 8002c08: 4613 mov r3, r2 8002c0a: 00db lsls r3, r3, #3 8002c0c: 4413 add r3, r2 8002c0e: 009b lsls r3, r3, #2 8002c10: 440b add r3, r1 8002c12: 331c adds r3, #28 8002c14: 2200 movs r2, #0 8002c16: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 8002c18: 7bfa ldrb r2, [r7, #15] 8002c1a: 6879 ldr r1, [r7, #4] 8002c1c: 4613 mov r3, r2 8002c1e: 00db lsls r3, r3, #3 8002c20: 4413 add r3, r2 8002c22: 009b lsls r3, r3, #2 8002c24: 440b add r3, r1 8002c26: 3320 adds r3, #32 8002c28: 2200 movs r2, #0 8002c2a: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 8002c2c: 7bfa ldrb r2, [r7, #15] 8002c2e: 6879 ldr r1, [r7, #4] 8002c30: 4613 mov r3, r2 8002c32: 00db lsls r3, r3, #3 8002c34: 4413 add r3, r2 8002c36: 009b lsls r3, r3, #2 8002c38: 440b add r3, r1 8002c3a: 3324 adds r3, #36 @ 0x24 8002c3c: 2200 movs r2, #0 8002c3e: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002c40: 7bfb ldrb r3, [r7, #15] 8002c42: 3301 adds r3, #1 8002c44: 73fb strb r3, [r7, #15] 8002c46: 687b ldr r3, [r7, #4] 8002c48: 791b ldrb r3, [r3, #4] 8002c4a: 7bfa ldrb r2, [r7, #15] 8002c4c: 429a cmp r2, r3 8002c4e: d3af bcc.n 8002bb0 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002c50: 2300 movs r3, #0 8002c52: 73fb strb r3, [r7, #15] 8002c54: e044 b.n 8002ce0 { hpcd->OUT_ep[i].is_in = 0U; 8002c56: 7bfa ldrb r2, [r7, #15] 8002c58: 6879 ldr r1, [r7, #4] 8002c5a: 4613 mov r3, r2 8002c5c: 00db lsls r3, r3, #3 8002c5e: 4413 add r3, r2 8002c60: 009b lsls r3, r3, #2 8002c62: 440b add r3, r1 8002c64: f203 2355 addw r3, r3, #597 @ 0x255 8002c68: 2200 movs r2, #0 8002c6a: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 8002c6c: 7bfa ldrb r2, [r7, #15] 8002c6e: 6879 ldr r1, [r7, #4] 8002c70: 4613 mov r3, r2 8002c72: 00db lsls r3, r3, #3 8002c74: 4413 add r3, r2 8002c76: 009b lsls r3, r3, #2 8002c78: 440b add r3, r1 8002c7a: f503 7315 add.w r3, r3, #596 @ 0x254 8002c7e: 7bfa ldrb r2, [r7, #15] 8002c80: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8002c82: 7bfa ldrb r2, [r7, #15] 8002c84: 6879 ldr r1, [r7, #4] 8002c86: 4613 mov r3, r2 8002c88: 00db lsls r3, r3, #3 8002c8a: 4413 add r3, r2 8002c8c: 009b lsls r3, r3, #2 8002c8e: 440b add r3, r1 8002c90: f503 7316 add.w r3, r3, #600 @ 0x258 8002c94: 2200 movs r2, #0 8002c96: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8002c98: 7bfa ldrb r2, [r7, #15] 8002c9a: 6879 ldr r1, [r7, #4] 8002c9c: 4613 mov r3, r2 8002c9e: 00db lsls r3, r3, #3 8002ca0: 4413 add r3, r2 8002ca2: 009b lsls r3, r3, #2 8002ca4: 440b add r3, r1 8002ca6: f503 7317 add.w r3, r3, #604 @ 0x25c 8002caa: 2200 movs r2, #0 8002cac: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 8002cae: 7bfa ldrb r2, [r7, #15] 8002cb0: 6879 ldr r1, [r7, #4] 8002cb2: 4613 mov r3, r2 8002cb4: 00db lsls r3, r3, #3 8002cb6: 4413 add r3, r2 8002cb8: 009b lsls r3, r3, #2 8002cba: 440b add r3, r1 8002cbc: f503 7318 add.w r3, r3, #608 @ 0x260 8002cc0: 2200 movs r2, #0 8002cc2: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8002cc4: 7bfa ldrb r2, [r7, #15] 8002cc6: 6879 ldr r1, [r7, #4] 8002cc8: 4613 mov r3, r2 8002cca: 00db lsls r3, r3, #3 8002ccc: 4413 add r3, r2 8002cce: 009b lsls r3, r3, #2 8002cd0: 440b add r3, r1 8002cd2: f503 7319 add.w r3, r3, #612 @ 0x264 8002cd6: 2200 movs r2, #0 8002cd8: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002cda: 7bfb ldrb r3, [r7, #15] 8002cdc: 3301 adds r3, #1 8002cde: 73fb strb r3, [r7, #15] 8002ce0: 687b ldr r3, [r7, #4] 8002ce2: 791b ldrb r3, [r3, #4] 8002ce4: 7bfa ldrb r2, [r7, #15] 8002ce6: 429a cmp r2, r3 8002ce8: d3b5 bcc.n 8002c56 } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002cea: 687b ldr r3, [r7, #4] 8002cec: 6818 ldr r0, [r3, #0] 8002cee: 687b ldr r3, [r7, #4] 8002cf0: 7c1a ldrb r2, [r3, #16] 8002cf2: f88d 2000 strb.w r2, [sp] 8002cf6: 3304 adds r3, #4 8002cf8: cb0e ldmia r3, {r1, r2, r3} 8002cfa: f004 fb2f bl 800735c 8002cfe: 4603 mov r3, r0 8002d00: 2b00 cmp r3, #0 8002d02: d005 beq.n 8002d10 { hpcd->State = HAL_PCD_STATE_ERROR; 8002d04: 687b ldr r3, [r7, #4] 8002d06: 2202 movs r2, #2 8002d08: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002d0c: 2301 movs r3, #1 8002d0e: e013 b.n 8002d38 } hpcd->USB_Address = 0U; 8002d10: 687b ldr r3, [r7, #4] 8002d12: 2200 movs r2, #0 8002d14: 745a strb r2, [r3, #17] hpcd->State = HAL_PCD_STATE_READY; 8002d16: 687b ldr r3, [r7, #4] 8002d18: 2201 movs r2, #1 8002d1a: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 8002d1e: 687b ldr r3, [r7, #4] 8002d20: 7b1b ldrb r3, [r3, #12] 8002d22: 2b01 cmp r3, #1 8002d24: d102 bne.n 8002d2c { (void)HAL_PCDEx_ActivateLPM(hpcd); 8002d26: 6878 ldr r0, [r7, #4] 8002d28: f001 f956 bl 8003fd8 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); 8002d2c: 687b ldr r3, [r7, #4] 8002d2e: 681b ldr r3, [r3, #0] 8002d30: 4618 mov r0, r3 8002d32: f005 fb6c bl 800840e return HAL_OK; 8002d36: 2300 movs r3, #0 } 8002d38: 4618 mov r0, r3 8002d3a: 3710 adds r7, #16 8002d3c: 46bd mov sp, r7 8002d3e: bd80 pop {r7, pc} 08002d40 : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 8002d40: b580 push {r7, lr} 8002d42: b084 sub sp, #16 8002d44: af00 add r7, sp, #0 8002d46: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002d48: 687b ldr r3, [r7, #4] 8002d4a: 681b ldr r3, [r3, #0] 8002d4c: 60fb str r3, [r7, #12] __HAL_LOCK(hpcd); 8002d4e: 687b ldr r3, [r7, #4] 8002d50: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8002d54: 2b01 cmp r3, #1 8002d56: d101 bne.n 8002d5c 8002d58: 2302 movs r3, #2 8002d5a: e022 b.n 8002da2 8002d5c: 687b ldr r3, [r7, #4] 8002d5e: 2201 movs r2, #1 8002d60: f883 2494 strb.w r2, [r3, #1172] @ 0x494 if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8002d64: 68fb ldr r3, [r7, #12] 8002d66: 68db ldr r3, [r3, #12] 8002d68: f003 0340 and.w r3, r3, #64 @ 0x40 8002d6c: 2b00 cmp r3, #0 8002d6e: d009 beq.n 8002d84 (hpcd->Init.battery_charging_enable == 1U)) 8002d70: 687b ldr r3, [r7, #4] 8002d72: 7b5b ldrb r3, [r3, #13] if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8002d74: 2b01 cmp r3, #1 8002d76: d105 bne.n 8002d84 { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8002d78: 68fb ldr r3, [r7, #12] 8002d7a: 6b9b ldr r3, [r3, #56] @ 0x38 8002d7c: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8002d80: 68fb ldr r3, [r7, #12] 8002d82: 639a str r2, [r3, #56] @ 0x38 } __HAL_PCD_ENABLE(hpcd); 8002d84: 687b ldr r3, [r7, #4] 8002d86: 681b ldr r3, [r3, #0] 8002d88: 4618 mov r0, r3 8002d8a: f004 fa79 bl 8007280 (void)USB_DevConnect(hpcd->Instance); 8002d8e: 687b ldr r3, [r7, #4] 8002d90: 681b ldr r3, [r3, #0] 8002d92: 4618 mov r0, r3 8002d94: f005 fb1a bl 80083cc __HAL_UNLOCK(hpcd); 8002d98: 687b ldr r3, [r7, #4] 8002d9a: 2200 movs r2, #0 8002d9c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8002da0: 2300 movs r3, #0 } 8002da2: 4618 mov r0, r3 8002da4: 3710 adds r7, #16 8002da6: 46bd mov sp, r7 8002da8: bd80 pop {r7, pc} 08002daa : * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 8002daa: b590 push {r4, r7, lr} 8002dac: b08d sub sp, #52 @ 0x34 8002dae: af00 add r7, sp, #0 8002db0: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002db2: 687b ldr r3, [r7, #4] 8002db4: 681b ldr r3, [r3, #0] 8002db6: 623b str r3, [r7, #32] uint32_t USBx_BASE = (uint32_t)USBx; 8002db8: 6a3b ldr r3, [r7, #32] 8002dba: 61fb str r3, [r7, #28] uint32_t epnum; uint32_t fifoemptymsk; uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) 8002dbc: 687b ldr r3, [r7, #4] 8002dbe: 681b ldr r3, [r3, #0] 8002dc0: 4618 mov r0, r3 8002dc2: f005 fbd8 bl 8008576 8002dc6: 4603 mov r3, r0 8002dc8: 2b00 cmp r3, #0 8002dca: f040 84b9 bne.w 8003740 { /* avoid spurious interrupt */ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 8002dce: 687b ldr r3, [r7, #4] 8002dd0: 681b ldr r3, [r3, #0] 8002dd2: 4618 mov r0, r3 8002dd4: f005 fb3c bl 8008450 8002dd8: 4603 mov r3, r0 8002dda: 2b00 cmp r3, #0 8002ddc: f000 84af beq.w 800373e { return; } /* store current frame number */ hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; 8002de0: 69fb ldr r3, [r7, #28] 8002de2: f503 6300 add.w r3, r3, #2048 @ 0x800 8002de6: 689b ldr r3, [r3, #8] 8002de8: 0a1b lsrs r3, r3, #8 8002dea: f3c3 020d ubfx r2, r3, #0, #14 8002dee: 687b ldr r3, [r7, #4] 8002df0: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4 if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) 8002df4: 687b ldr r3, [r7, #4] 8002df6: 681b ldr r3, [r3, #0] 8002df8: 4618 mov r0, r3 8002dfa: f005 fb29 bl 8008450 8002dfe: 4603 mov r3, r0 8002e00: f003 0302 and.w r3, r3, #2 8002e04: 2b02 cmp r3, #2 8002e06: d107 bne.n 8002e18 { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); 8002e08: 687b ldr r3, [r7, #4] 8002e0a: 681b ldr r3, [r3, #0] 8002e0c: 695a ldr r2, [r3, #20] 8002e0e: 687b ldr r3, [r7, #4] 8002e10: 681b ldr r3, [r3, #0] 8002e12: f002 0202 and.w r2, r2, #2 8002e16: 615a str r2, [r3, #20] } /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) 8002e18: 687b ldr r3, [r7, #4] 8002e1a: 681b ldr r3, [r3, #0] 8002e1c: 4618 mov r0, r3 8002e1e: f005 fb17 bl 8008450 8002e22: 4603 mov r3, r0 8002e24: f003 0310 and.w r3, r3, #16 8002e28: 2b10 cmp r3, #16 8002e2a: d161 bne.n 8002ef0 { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002e2c: 687b ldr r3, [r7, #4] 8002e2e: 681b ldr r3, [r3, #0] 8002e30: 699a ldr r2, [r3, #24] 8002e32: 687b ldr r3, [r7, #4] 8002e34: 681b ldr r3, [r3, #0] 8002e36: f022 0210 bic.w r2, r2, #16 8002e3a: 619a str r2, [r3, #24] RegVal = USBx->GRXSTSP; 8002e3c: 6a3b ldr r3, [r7, #32] 8002e3e: 6a1b ldr r3, [r3, #32] 8002e40: 61bb str r3, [r7, #24] ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; 8002e42: 69bb ldr r3, [r7, #24] 8002e44: f003 020f and.w r2, r3, #15 8002e48: 4613 mov r3, r2 8002e4a: 00db lsls r3, r3, #3 8002e4c: 4413 add r3, r2 8002e4e: 009b lsls r3, r3, #2 8002e50: f503 7314 add.w r3, r3, #592 @ 0x250 8002e54: 687a ldr r2, [r7, #4] 8002e56: 4413 add r3, r2 8002e58: 3304 adds r3, #4 8002e5a: 617b str r3, [r7, #20] if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) 8002e5c: 69bb ldr r3, [r7, #24] 8002e5e: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8002e62: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8002e66: d124 bne.n 8002eb2 { if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) 8002e68: 69ba ldr r2, [r7, #24] 8002e6a: f647 73f0 movw r3, #32752 @ 0x7ff0 8002e6e: 4013 ands r3, r2 8002e70: 2b00 cmp r3, #0 8002e72: d035 beq.n 8002ee0 { (void)USB_ReadPacket(USBx, ep->xfer_buff, 8002e74: 697b ldr r3, [r7, #20] 8002e76: 68d9 ldr r1, [r3, #12] (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); 8002e78: 69bb ldr r3, [r7, #24] 8002e7a: 091b lsrs r3, r3, #4 8002e7c: b29b uxth r3, r3 (void)USB_ReadPacket(USBx, ep->xfer_buff, 8002e7e: f3c3 030a ubfx r3, r3, #0, #11 8002e82: b29b uxth r3, r3 8002e84: 461a mov r2, r3 8002e86: 6a38 ldr r0, [r7, #32] 8002e88: f005 f94e bl 8008128 ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002e8c: 697b ldr r3, [r7, #20] 8002e8e: 68da ldr r2, [r3, #12] 8002e90: 69bb ldr r3, [r7, #24] 8002e92: 091b lsrs r3, r3, #4 8002e94: f3c3 030a ubfx r3, r3, #0, #11 8002e98: 441a add r2, r3 8002e9a: 697b ldr r3, [r7, #20] 8002e9c: 60da str r2, [r3, #12] ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002e9e: 697b ldr r3, [r7, #20] 8002ea0: 695a ldr r2, [r3, #20] 8002ea2: 69bb ldr r3, [r7, #24] 8002ea4: 091b lsrs r3, r3, #4 8002ea6: f3c3 030a ubfx r3, r3, #0, #11 8002eaa: 441a add r2, r3 8002eac: 697b ldr r3, [r7, #20] 8002eae: 615a str r2, [r3, #20] 8002eb0: e016 b.n 8002ee0 } } else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) 8002eb2: 69bb ldr r3, [r7, #24] 8002eb4: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8002eb8: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8002ebc: d110 bne.n 8002ee0 { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); 8002ebe: 687b ldr r3, [r7, #4] 8002ec0: f203 439c addw r3, r3, #1180 @ 0x49c 8002ec4: 2208 movs r2, #8 8002ec6: 4619 mov r1, r3 8002ec8: 6a38 ldr r0, [r7, #32] 8002eca: f005 f92d bl 8008128 ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 8002ece: 697b ldr r3, [r7, #20] 8002ed0: 695a ldr r2, [r3, #20] 8002ed2: 69bb ldr r3, [r7, #24] 8002ed4: 091b lsrs r3, r3, #4 8002ed6: f3c3 030a ubfx r3, r3, #0, #11 8002eda: 441a add r2, r3 8002edc: 697b ldr r3, [r7, #20] 8002ede: 615a str r2, [r3, #20] else { /* ... */ } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002ee0: 687b ldr r3, [r7, #4] 8002ee2: 681b ldr r3, [r3, #0] 8002ee4: 699a ldr r2, [r3, #24] 8002ee6: 687b ldr r3, [r7, #4] 8002ee8: 681b ldr r3, [r3, #0] 8002eea: f042 0210 orr.w r2, r2, #16 8002eee: 619a str r2, [r3, #24] } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) 8002ef0: 687b ldr r3, [r7, #4] 8002ef2: 681b ldr r3, [r3, #0] 8002ef4: 4618 mov r0, r3 8002ef6: f005 faab bl 8008450 8002efa: 4603 mov r3, r0 8002efc: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002f00: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8002f04: f040 80a7 bne.w 8003056 { epnum = 0U; 8002f08: 2300 movs r3, #0 8002f0a: 627b str r3, [r7, #36] @ 0x24 /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); 8002f0c: 687b ldr r3, [r7, #4] 8002f0e: 681b ldr r3, [r3, #0] 8002f10: 4618 mov r0, r3 8002f12: f005 fab0 bl 8008476 8002f16: 62b8 str r0, [r7, #40] @ 0x28 while (ep_intr != 0U) 8002f18: e099 b.n 800304e { if ((ep_intr & 0x1U) != 0U) 8002f1a: 6abb ldr r3, [r7, #40] @ 0x28 8002f1c: f003 0301 and.w r3, r3, #1 8002f20: 2b00 cmp r3, #0 8002f22: f000 808e beq.w 8003042 { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8002f26: 687b ldr r3, [r7, #4] 8002f28: 681b ldr r3, [r3, #0] 8002f2a: 6a7a ldr r2, [r7, #36] @ 0x24 8002f2c: b2d2 uxtb r2, r2 8002f2e: 4611 mov r1, r2 8002f30: 4618 mov r0, r3 8002f32: f005 fad4 bl 80084de 8002f36: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) 8002f38: 693b ldr r3, [r7, #16] 8002f3a: f003 0301 and.w r3, r3, #1 8002f3e: 2b00 cmp r3, #0 8002f40: d00c beq.n 8002f5c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); 8002f42: 6a7b ldr r3, [r7, #36] @ 0x24 8002f44: 015a lsls r2, r3, #5 8002f46: 69fb ldr r3, [r7, #28] 8002f48: 4413 add r3, r2 8002f4a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002f4e: 461a mov r2, r3 8002f50: 2301 movs r3, #1 8002f52: 6093 str r3, [r2, #8] (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); 8002f54: 6a79 ldr r1, [r7, #36] @ 0x24 8002f56: 6878 ldr r0, [r7, #4] 8002f58: f000 feb8 bl 8003ccc } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) 8002f5c: 693b ldr r3, [r7, #16] 8002f5e: f003 0308 and.w r3, r3, #8 8002f62: 2b00 cmp r3, #0 8002f64: d00c beq.n 8002f80 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); 8002f66: 6a7b ldr r3, [r7, #36] @ 0x24 8002f68: 015a lsls r2, r3, #5 8002f6a: 69fb ldr r3, [r7, #28] 8002f6c: 4413 add r3, r2 8002f6e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002f72: 461a mov r2, r3 8002f74: 2308 movs r3, #8 8002f76: 6093 str r3, [r2, #8] /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); 8002f78: 6a79 ldr r1, [r7, #36] @ 0x24 8002f7a: 6878 ldr r0, [r7, #4] 8002f7c: f000 ff8e bl 8003e9c } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) 8002f80: 693b ldr r3, [r7, #16] 8002f82: f003 0310 and.w r3, r3, #16 8002f86: 2b00 cmp r3, #0 8002f88: d008 beq.n 8002f9c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); 8002f8a: 6a7b ldr r3, [r7, #36] @ 0x24 8002f8c: 015a lsls r2, r3, #5 8002f8e: 69fb ldr r3, [r7, #28] 8002f90: 4413 add r3, r2 8002f92: f503 6330 add.w r3, r3, #2816 @ 0xb00 8002f96: 461a mov r2, r3 8002f98: 2310 movs r3, #16 8002f9a: 6093 str r3, [r2, #8] } /* Clear OUT Endpoint disable interrupt */ if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) 8002f9c: 693b ldr r3, [r7, #16] 8002f9e: f003 0302 and.w r3, r3, #2 8002fa2: 2b00 cmp r3, #0 8002fa4: d030 beq.n 8003008 { if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) 8002fa6: 6a3b ldr r3, [r7, #32] 8002fa8: 695b ldr r3, [r3, #20] 8002faa: f003 0380 and.w r3, r3, #128 @ 0x80 8002fae: 2b80 cmp r3, #128 @ 0x80 8002fb0: d109 bne.n 8002fc6 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; 8002fb2: 69fb ldr r3, [r7, #28] 8002fb4: f503 6300 add.w r3, r3, #2048 @ 0x800 8002fb8: 685b ldr r3, [r3, #4] 8002fba: 69fa ldr r2, [r7, #28] 8002fbc: f502 6200 add.w r2, r2, #2048 @ 0x800 8002fc0: f443 6380 orr.w r3, r3, #1024 @ 0x400 8002fc4: 6053 str r3, [r2, #4] } ep = &hpcd->OUT_ep[epnum]; 8002fc6: 6a7a ldr r2, [r7, #36] @ 0x24 8002fc8: 4613 mov r3, r2 8002fca: 00db lsls r3, r3, #3 8002fcc: 4413 add r3, r2 8002fce: 009b lsls r3, r3, #2 8002fd0: f503 7314 add.w r3, r3, #592 @ 0x250 8002fd4: 687a ldr r2, [r7, #4] 8002fd6: 4413 add r3, r2 8002fd8: 3304 adds r3, #4 8002fda: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 8002fdc: 697b ldr r3, [r7, #20] 8002fde: 78db ldrb r3, [r3, #3] 8002fe0: 2b01 cmp r3, #1 8002fe2: d108 bne.n 8002ff6 { ep->is_iso_incomplete = 0U; 8002fe4: 697b ldr r3, [r7, #20] 8002fe6: 2200 movs r2, #0 8002fe8: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); 8002fea: 6a7b ldr r3, [r7, #36] @ 0x24 8002fec: b2db uxtb r3, r3 8002fee: 4619 mov r1, r3 8002ff0: 6878 ldr r0, [r7, #4] 8002ff2: f007 fb6d bl 800a6d0 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); 8002ff6: 6a7b ldr r3, [r7, #36] @ 0x24 8002ff8: 015a lsls r2, r3, #5 8002ffa: 69fb ldr r3, [r7, #28] 8002ffc: 4413 add r3, r2 8002ffe: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003002: 461a mov r2, r3 8003004: 2302 movs r3, #2 8003006: 6093 str r3, [r2, #8] } /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8003008: 693b ldr r3, [r7, #16] 800300a: f003 0320 and.w r3, r3, #32 800300e: 2b00 cmp r3, #0 8003010: d008 beq.n 8003024 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003012: 6a7b ldr r3, [r7, #36] @ 0x24 8003014: 015a lsls r2, r3, #5 8003016: 69fb ldr r3, [r7, #28] 8003018: 4413 add r3, r2 800301a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800301e: 461a mov r2, r3 8003020: 2320 movs r3, #32 8003022: 6093 str r3, [r2, #8] } /* Clear OUT NAK interrupt */ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) 8003024: 693b ldr r3, [r7, #16] 8003026: f403 5300 and.w r3, r3, #8192 @ 0x2000 800302a: 2b00 cmp r3, #0 800302c: d009 beq.n 8003042 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); 800302e: 6a7b ldr r3, [r7, #36] @ 0x24 8003030: 015a lsls r2, r3, #5 8003032: 69fb ldr r3, [r7, #28] 8003034: 4413 add r3, r2 8003036: f503 6330 add.w r3, r3, #2816 @ 0xb00 800303a: 461a mov r2, r3 800303c: f44f 5300 mov.w r3, #8192 @ 0x2000 8003040: 6093 str r3, [r2, #8] } } epnum++; 8003042: 6a7b ldr r3, [r7, #36] @ 0x24 8003044: 3301 adds r3, #1 8003046: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 8003048: 6abb ldr r3, [r7, #40] @ 0x28 800304a: 085b lsrs r3, r3, #1 800304c: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 800304e: 6abb ldr r3, [r7, #40] @ 0x28 8003050: 2b00 cmp r3, #0 8003052: f47f af62 bne.w 8002f1a } } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) 8003056: 687b ldr r3, [r7, #4] 8003058: 681b ldr r3, [r3, #0] 800305a: 4618 mov r0, r3 800305c: f005 f9f8 bl 8008450 8003060: 4603 mov r3, r0 8003062: f403 2380 and.w r3, r3, #262144 @ 0x40000 8003066: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800306a: f040 80db bne.w 8003224 { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); 800306e: 687b ldr r3, [r7, #4] 8003070: 681b ldr r3, [r3, #0] 8003072: 4618 mov r0, r3 8003074: f005 fa19 bl 80084aa 8003078: 62b8 str r0, [r7, #40] @ 0x28 epnum = 0U; 800307a: 2300 movs r3, #0 800307c: 627b str r3, [r7, #36] @ 0x24 while (ep_intr != 0U) 800307e: e0cd b.n 800321c { if ((ep_intr & 0x1U) != 0U) /* In ITR */ 8003080: 6abb ldr r3, [r7, #40] @ 0x28 8003082: f003 0301 and.w r3, r3, #1 8003086: 2b00 cmp r3, #0 8003088: f000 80c2 beq.w 8003210 { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); 800308c: 687b ldr r3, [r7, #4] 800308e: 681b ldr r3, [r3, #0] 8003090: 6a7a ldr r2, [r7, #36] @ 0x24 8003092: b2d2 uxtb r2, r2 8003094: 4611 mov r1, r2 8003096: 4618 mov r0, r3 8003098: f005 fa3f bl 800851a 800309c: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) 800309e: 693b ldr r3, [r7, #16] 80030a0: f003 0301 and.w r3, r3, #1 80030a4: 2b00 cmp r3, #0 80030a6: d057 beq.n 8003158 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 80030a8: 6a7b ldr r3, [r7, #36] @ 0x24 80030aa: f003 030f and.w r3, r3, #15 80030ae: 2201 movs r2, #1 80030b0: fa02 f303 lsl.w r3, r2, r3 80030b4: 60fb str r3, [r7, #12] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 80030b6: 69fb ldr r3, [r7, #28] 80030b8: f503 6300 add.w r3, r3, #2048 @ 0x800 80030bc: 6b5a ldr r2, [r3, #52] @ 0x34 80030be: 68fb ldr r3, [r7, #12] 80030c0: 43db mvns r3, r3 80030c2: 69f9 ldr r1, [r7, #28] 80030c4: f501 6100 add.w r1, r1, #2048 @ 0x800 80030c8: 4013 ands r3, r2 80030ca: 634b str r3, [r1, #52] @ 0x34 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); 80030cc: 6a7b ldr r3, [r7, #36] @ 0x24 80030ce: 015a lsls r2, r3, #5 80030d0: 69fb ldr r3, [r7, #28] 80030d2: 4413 add r3, r2 80030d4: f503 6310 add.w r3, r3, #2304 @ 0x900 80030d8: 461a mov r2, r3 80030da: 2301 movs r3, #1 80030dc: 6093 str r3, [r2, #8] if (hpcd->Init.dma_enable == 1U) 80030de: 687b ldr r3, [r7, #4] 80030e0: 799b ldrb r3, [r3, #6] 80030e2: 2b01 cmp r3, #1 80030e4: d132 bne.n 800314c { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 80030e6: 6879 ldr r1, [r7, #4] 80030e8: 6a7a ldr r2, [r7, #36] @ 0x24 80030ea: 4613 mov r3, r2 80030ec: 00db lsls r3, r3, #3 80030ee: 4413 add r3, r2 80030f0: 009b lsls r3, r3, #2 80030f2: 440b add r3, r1 80030f4: 3320 adds r3, #32 80030f6: 6819 ldr r1, [r3, #0] 80030f8: 6878 ldr r0, [r7, #4] 80030fa: 6a7a ldr r2, [r7, #36] @ 0x24 80030fc: 4613 mov r3, r2 80030fe: 00db lsls r3, r3, #3 8003100: 4413 add r3, r2 8003102: 009b lsls r3, r3, #2 8003104: 4403 add r3, r0 8003106: 331c adds r3, #28 8003108: 681b ldr r3, [r3, #0] 800310a: 4419 add r1, r3 800310c: 6878 ldr r0, [r7, #4] 800310e: 6a7a ldr r2, [r7, #36] @ 0x24 8003110: 4613 mov r3, r2 8003112: 00db lsls r3, r3, #3 8003114: 4413 add r3, r2 8003116: 009b lsls r3, r3, #2 8003118: 4403 add r3, r0 800311a: 3320 adds r3, #32 800311c: 6019 str r1, [r3, #0] /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) 800311e: 6a7b ldr r3, [r7, #36] @ 0x24 8003120: 2b00 cmp r3, #0 8003122: d113 bne.n 800314c 8003124: 6879 ldr r1, [r7, #4] 8003126: 6a7a ldr r2, [r7, #36] @ 0x24 8003128: 4613 mov r3, r2 800312a: 00db lsls r3, r3, #3 800312c: 4413 add r3, r2 800312e: 009b lsls r3, r3, #2 8003130: 440b add r3, r1 8003132: 3324 adds r3, #36 @ 0x24 8003134: 681b ldr r3, [r3, #0] 8003136: 2b00 cmp r3, #0 8003138: d108 bne.n 800314c { /* prepare to rx more setup packets */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 800313a: 687b ldr r3, [r7, #4] 800313c: 6818 ldr r0, [r3, #0] 800313e: 687b ldr r3, [r7, #4] 8003140: f203 439c addw r3, r3, #1180 @ 0x49c 8003144: 461a mov r2, r3 8003146: 2101 movs r1, #1 8003148: f005 fa46 bl 80085d8 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); 800314c: 6a7b ldr r3, [r7, #36] @ 0x24 800314e: b2db uxtb r3, r3 8003150: 4619 mov r1, r3 8003152: 6878 ldr r0, [r7, #4] 8003154: f007 fa37 bl 800a5c6 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) 8003158: 693b ldr r3, [r7, #16] 800315a: f003 0308 and.w r3, r3, #8 800315e: 2b00 cmp r3, #0 8003160: d008 beq.n 8003174 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); 8003162: 6a7b ldr r3, [r7, #36] @ 0x24 8003164: 015a lsls r2, r3, #5 8003166: 69fb ldr r3, [r7, #28] 8003168: 4413 add r3, r2 800316a: f503 6310 add.w r3, r3, #2304 @ 0x900 800316e: 461a mov r2, r3 8003170: 2308 movs r3, #8 8003172: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) 8003174: 693b ldr r3, [r7, #16] 8003176: f003 0310 and.w r3, r3, #16 800317a: 2b00 cmp r3, #0 800317c: d008 beq.n 8003190 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); 800317e: 6a7b ldr r3, [r7, #36] @ 0x24 8003180: 015a lsls r2, r3, #5 8003182: 69fb ldr r3, [r7, #28] 8003184: 4413 add r3, r2 8003186: f503 6310 add.w r3, r3, #2304 @ 0x900 800318a: 461a mov r2, r3 800318c: 2310 movs r3, #16 800318e: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) 8003190: 693b ldr r3, [r7, #16] 8003192: f003 0340 and.w r3, r3, #64 @ 0x40 8003196: 2b00 cmp r3, #0 8003198: d008 beq.n 80031ac { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); 800319a: 6a7b ldr r3, [r7, #36] @ 0x24 800319c: 015a lsls r2, r3, #5 800319e: 69fb ldr r3, [r7, #28] 80031a0: 4413 add r3, r2 80031a2: f503 6310 add.w r3, r3, #2304 @ 0x900 80031a6: 461a mov r2, r3 80031a8: 2340 movs r3, #64 @ 0x40 80031aa: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) 80031ac: 693b ldr r3, [r7, #16] 80031ae: f003 0302 and.w r3, r3, #2 80031b2: 2b00 cmp r3, #0 80031b4: d023 beq.n 80031fe { (void)USB_FlushTxFifo(USBx, epnum); 80031b6: 6a79 ldr r1, [r7, #36] @ 0x24 80031b8: 6a38 ldr r0, [r7, #32] 80031ba: f004 fa2d bl 8007618 ep = &hpcd->IN_ep[epnum]; 80031be: 6a7a ldr r2, [r7, #36] @ 0x24 80031c0: 4613 mov r3, r2 80031c2: 00db lsls r3, r3, #3 80031c4: 4413 add r3, r2 80031c6: 009b lsls r3, r3, #2 80031c8: 3310 adds r3, #16 80031ca: 687a ldr r2, [r7, #4] 80031cc: 4413 add r3, r2 80031ce: 3304 adds r3, #4 80031d0: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 80031d2: 697b ldr r3, [r7, #20] 80031d4: 78db ldrb r3, [r3, #3] 80031d6: 2b01 cmp r3, #1 80031d8: d108 bne.n 80031ec { ep->is_iso_incomplete = 0U; 80031da: 697b ldr r3, [r7, #20] 80031dc: 2200 movs r2, #0 80031de: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); 80031e0: 6a7b ldr r3, [r7, #36] @ 0x24 80031e2: b2db uxtb r3, r3 80031e4: 4619 mov r1, r3 80031e6: 6878 ldr r0, [r7, #4] 80031e8: f007 fa84 bl 800a6f4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); 80031ec: 6a7b ldr r3, [r7, #36] @ 0x24 80031ee: 015a lsls r2, r3, #5 80031f0: 69fb ldr r3, [r7, #28] 80031f2: 4413 add r3, r2 80031f4: f503 6310 add.w r3, r3, #2304 @ 0x900 80031f8: 461a mov r2, r3 80031fa: 2302 movs r3, #2 80031fc: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) 80031fe: 693b ldr r3, [r7, #16] 8003200: f003 0380 and.w r3, r3, #128 @ 0x80 8003204: 2b00 cmp r3, #0 8003206: d003 beq.n 8003210 { (void)PCD_WriteEmptyTxFifo(hpcd, epnum); 8003208: 6a79 ldr r1, [r7, #36] @ 0x24 800320a: 6878 ldr r0, [r7, #4] 800320c: f000 fcd2 bl 8003bb4 } } epnum++; 8003210: 6a7b ldr r3, [r7, #36] @ 0x24 8003212: 3301 adds r3, #1 8003214: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 8003216: 6abb ldr r3, [r7, #40] @ 0x28 8003218: 085b lsrs r3, r3, #1 800321a: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 800321c: 6abb ldr r3, [r7, #40] @ 0x28 800321e: 2b00 cmp r3, #0 8003220: f47f af2e bne.w 8003080 } } /* Handle Resume Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) 8003224: 687b ldr r3, [r7, #4] 8003226: 681b ldr r3, [r3, #0] 8003228: 4618 mov r0, r3 800322a: f005 f911 bl 8008450 800322e: 4603 mov r3, r0 8003230: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8003234: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8003238: d122 bne.n 8003280 { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 800323a: 69fb ldr r3, [r7, #28] 800323c: f503 6300 add.w r3, r3, #2048 @ 0x800 8003240: 685b ldr r3, [r3, #4] 8003242: 69fa ldr r2, [r7, #28] 8003244: f502 6200 add.w r2, r2, #2048 @ 0x800 8003248: f023 0301 bic.w r3, r3, #1 800324c: 6053 str r3, [r2, #4] if (hpcd->LPM_State == LPM_L1) 800324e: 687b ldr r3, [r7, #4] 8003250: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 8003254: 2b01 cmp r3, #1 8003256: d108 bne.n 800326a { hpcd->LPM_State = LPM_L0; 8003258: 687b ldr r3, [r7, #4] 800325a: 2200 movs r2, #0 800325c: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 8003260: 2100 movs r1, #0 8003262: 6878 ldr r0, [r7, #4] 8003264: f007 fbec bl 800aa40 8003268: e002 b.n 8003270 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 800326a: 6878 ldr r0, [r7, #4] 800326c: f007 fa22 bl 800a6b4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); 8003270: 687b ldr r3, [r7, #4] 8003272: 681b ldr r3, [r3, #0] 8003274: 695a ldr r2, [r3, #20] 8003276: 687b ldr r3, [r7, #4] 8003278: 681b ldr r3, [r3, #0] 800327a: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000 800327e: 615a str r2, [r3, #20] } /* Handle Suspend Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) 8003280: 687b ldr r3, [r7, #4] 8003282: 681b ldr r3, [r3, #0] 8003284: 4618 mov r0, r3 8003286: f005 f8e3 bl 8008450 800328a: 4603 mov r3, r0 800328c: f403 6300 and.w r3, r3, #2048 @ 0x800 8003290: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8003294: d112 bne.n 80032bc { if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 8003296: 69fb ldr r3, [r7, #28] 8003298: f503 6300 add.w r3, r3, #2048 @ 0x800 800329c: 689b ldr r3, [r3, #8] 800329e: f003 0301 and.w r3, r3, #1 80032a2: 2b01 cmp r3, #1 80032a4: d102 bne.n 80032ac { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 80032a6: 6878 ldr r0, [r7, #4] 80032a8: f007 f9de bl 800a668 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); 80032ac: 687b ldr r3, [r7, #4] 80032ae: 681b ldr r3, [r3, #0] 80032b0: 695a ldr r2, [r3, #20] 80032b2: 687b ldr r3, [r7, #4] 80032b4: 681b ldr r3, [r3, #0] 80032b6: f402 6200 and.w r2, r2, #2048 @ 0x800 80032ba: 615a str r2, [r3, #20] } #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) 80032bc: 687b ldr r3, [r7, #4] 80032be: 681b ldr r3, [r3, #0] 80032c0: 4618 mov r0, r3 80032c2: f005 f8c5 bl 8008450 80032c6: 4603 mov r3, r0 80032c8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80032cc: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80032d0: d121 bne.n 8003316 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); 80032d2: 687b ldr r3, [r7, #4] 80032d4: 681b ldr r3, [r3, #0] 80032d6: 695a ldr r2, [r3, #20] 80032d8: 687b ldr r3, [r7, #4] 80032da: 681b ldr r3, [r3, #0] 80032dc: f002 6200 and.w r2, r2, #134217728 @ 0x8000000 80032e0: 615a str r2, [r3, #20] if (hpcd->LPM_State == LPM_L0) 80032e2: 687b ldr r3, [r7, #4] 80032e4: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 80032e8: 2b00 cmp r3, #0 80032ea: d111 bne.n 8003310 { hpcd->LPM_State = LPM_L1; 80032ec: 687b ldr r3, [r7, #4] 80032ee: 2201 movs r2, #1 80032f0: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; 80032f4: 687b ldr r3, [r7, #4] 80032f6: 681b ldr r3, [r3, #0] 80032f8: 6d5b ldr r3, [r3, #84] @ 0x54 80032fa: 089b lsrs r3, r3, #2 80032fc: f003 020f and.w r2, r3, #15 8003300: 687b ldr r3, [r7, #4] 8003302: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 8003306: 2101 movs r1, #1 8003308: 6878 ldr r0, [r7, #4] 800330a: f007 fb99 bl 800aa40 800330e: e002 b.n 8003316 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 8003310: 6878 ldr r0, [r7, #4] 8003312: f007 f9a9 bl 800a668 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) 8003316: 687b ldr r3, [r7, #4] 8003318: 681b ldr r3, [r3, #0] 800331a: 4618 mov r0, r3 800331c: f005 f898 bl 8008450 8003320: 4603 mov r3, r0 8003322: f403 5380 and.w r3, r3, #4096 @ 0x1000 8003326: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800332a: f040 80b7 bne.w 800349c { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 800332e: 69fb ldr r3, [r7, #28] 8003330: f503 6300 add.w r3, r3, #2048 @ 0x800 8003334: 685b ldr r3, [r3, #4] 8003336: 69fa ldr r2, [r7, #28] 8003338: f502 6200 add.w r2, r2, #2048 @ 0x800 800333c: f023 0301 bic.w r3, r3, #1 8003340: 6053 str r3, [r2, #4] (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); 8003342: 687b ldr r3, [r7, #4] 8003344: 681b ldr r3, [r3, #0] 8003346: 2110 movs r1, #16 8003348: 4618 mov r0, r3 800334a: f004 f965 bl 8007618 for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800334e: 2300 movs r3, #0 8003350: 62fb str r3, [r7, #44] @ 0x2c 8003352: e046 b.n 80033e2 { USBx_INEP(i)->DIEPINT = 0xFB7FU; 8003354: 6afb ldr r3, [r7, #44] @ 0x2c 8003356: 015a lsls r2, r3, #5 8003358: 69fb ldr r3, [r7, #28] 800335a: 4413 add r3, r2 800335c: f503 6310 add.w r3, r3, #2304 @ 0x900 8003360: 461a mov r2, r3 8003362: f64f 337f movw r3, #64383 @ 0xfb7f 8003366: 6093 str r3, [r2, #8] USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 8003368: 6afb ldr r3, [r7, #44] @ 0x2c 800336a: 015a lsls r2, r3, #5 800336c: 69fb ldr r3, [r7, #28] 800336e: 4413 add r3, r2 8003370: f503 6310 add.w r3, r3, #2304 @ 0x900 8003374: 681b ldr r3, [r3, #0] 8003376: 6afa ldr r2, [r7, #44] @ 0x2c 8003378: 0151 lsls r1, r2, #5 800337a: 69fa ldr r2, [r7, #28] 800337c: 440a add r2, r1 800337e: f502 6210 add.w r2, r2, #2304 @ 0x900 8003382: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8003386: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8003388: 6afb ldr r3, [r7, #44] @ 0x2c 800338a: 015a lsls r2, r3, #5 800338c: 69fb ldr r3, [r7, #28] 800338e: 4413 add r3, r2 8003390: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003394: 461a mov r2, r3 8003396: f64f 337f movw r3, #64383 @ 0xfb7f 800339a: 6093 str r3, [r2, #8] USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 800339c: 6afb ldr r3, [r7, #44] @ 0x2c 800339e: 015a lsls r2, r3, #5 80033a0: 69fb ldr r3, [r7, #28] 80033a2: 4413 add r3, r2 80033a4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80033a8: 681b ldr r3, [r3, #0] 80033aa: 6afa ldr r2, [r7, #44] @ 0x2c 80033ac: 0151 lsls r1, r2, #5 80033ae: 69fa ldr r2, [r7, #28] 80033b0: 440a add r2, r1 80033b2: f502 6230 add.w r2, r2, #2816 @ 0xb00 80033b6: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 80033ba: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 80033bc: 6afb ldr r3, [r7, #44] @ 0x2c 80033be: 015a lsls r2, r3, #5 80033c0: 69fb ldr r3, [r7, #28] 80033c2: 4413 add r3, r2 80033c4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80033c8: 681b ldr r3, [r3, #0] 80033ca: 6afa ldr r2, [r7, #44] @ 0x2c 80033cc: 0151 lsls r1, r2, #5 80033ce: 69fa ldr r2, [r7, #28] 80033d0: 440a add r2, r1 80033d2: f502 6230 add.w r2, r2, #2816 @ 0xb00 80033d6: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 80033da: 6013 str r3, [r2, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80033dc: 6afb ldr r3, [r7, #44] @ 0x2c 80033de: 3301 adds r3, #1 80033e0: 62fb str r3, [r7, #44] @ 0x2c 80033e2: 687b ldr r3, [r7, #4] 80033e4: 791b ldrb r3, [r3, #4] 80033e6: 461a mov r2, r3 80033e8: 6afb ldr r3, [r7, #44] @ 0x2c 80033ea: 4293 cmp r3, r2 80033ec: d3b2 bcc.n 8003354 } USBx_DEVICE->DAINTMSK |= 0x10001U; 80033ee: 69fb ldr r3, [r7, #28] 80033f0: f503 6300 add.w r3, r3, #2048 @ 0x800 80033f4: 69db ldr r3, [r3, #28] 80033f6: 69fa ldr r2, [r7, #28] 80033f8: f502 6200 add.w r2, r2, #2048 @ 0x800 80033fc: f043 1301 orr.w r3, r3, #65537 @ 0x10001 8003400: 61d3 str r3, [r2, #28] if (hpcd->Init.use_dedicated_ep1 != 0U) 8003402: 687b ldr r3, [r7, #4] 8003404: 7bdb ldrb r3, [r3, #15] 8003406: 2b00 cmp r3, #0 8003408: d016 beq.n 8003438 { USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | 800340a: 69fb ldr r3, [r7, #28] 800340c: f503 6300 add.w r3, r3, #2048 @ 0x800 8003410: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8003414: 69fa ldr r2, [r7, #28] 8003416: f502 6200 add.w r2, r2, #2048 @ 0x800 800341a: f043 030b orr.w r3, r3, #11 800341e: f8c2 3084 str.w r3, [r2, #132] @ 0x84 USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM; USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | 8003422: 69fb ldr r3, [r7, #28] 8003424: f503 6300 add.w r3, r3, #2048 @ 0x800 8003428: 6c5b ldr r3, [r3, #68] @ 0x44 800342a: 69fa ldr r2, [r7, #28] 800342c: f502 6200 add.w r2, r2, #2048 @ 0x800 8003430: f043 030b orr.w r3, r3, #11 8003434: 6453 str r3, [r2, #68] @ 0x44 8003436: e015 b.n 8003464 USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } else { USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | 8003438: 69fb ldr r3, [r7, #28] 800343a: f503 6300 add.w r3, r3, #2048 @ 0x800 800343e: 695b ldr r3, [r3, #20] 8003440: 69fa ldr r2, [r7, #28] 8003442: f502 6200 add.w r2, r2, #2048 @ 0x800 8003446: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800344a: f043 032b orr.w r3, r3, #43 @ 0x2b 800344e: 6153 str r3, [r2, #20] USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM | USB_OTG_DOEPMSK_NAKM; USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | 8003450: 69fb ldr r3, [r7, #28] 8003452: f503 6300 add.w r3, r3, #2048 @ 0x800 8003456: 691b ldr r3, [r3, #16] 8003458: 69fa ldr r2, [r7, #28] 800345a: f502 6200 add.w r2, r2, #2048 @ 0x800 800345e: f043 030b orr.w r3, r3, #11 8003462: 6113 str r3, [r2, #16] USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; 8003464: 69fb ldr r3, [r7, #28] 8003466: f503 6300 add.w r3, r3, #2048 @ 0x800 800346a: 681b ldr r3, [r3, #0] 800346c: 69fa ldr r2, [r7, #28] 800346e: f502 6200 add.w r2, r2, #2048 @ 0x800 8003472: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 8003476: 6013 str r3, [r2, #0] /* setup EP0 to receive SETUP packets */ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 8003478: 687b ldr r3, [r7, #4] 800347a: 6818 ldr r0, [r3, #0] 800347c: 687b ldr r3, [r7, #4] 800347e: 7999 ldrb r1, [r3, #6] (uint8_t *)hpcd->Setup); 8003480: 687b ldr r3, [r7, #4] 8003482: f203 439c addw r3, r3, #1180 @ 0x49c (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 8003486: 461a mov r2, r3 8003488: f005 f8a6 bl 80085d8 __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); 800348c: 687b ldr r3, [r7, #4] 800348e: 681b ldr r3, [r3, #0] 8003490: 695a ldr r2, [r3, #20] 8003492: 687b ldr r3, [r7, #4] 8003494: 681b ldr r3, [r3, #0] 8003496: f402 5280 and.w r2, r2, #4096 @ 0x1000 800349a: 615a str r2, [r3, #20] } /* Handle Enumeration done Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) 800349c: 687b ldr r3, [r7, #4] 800349e: 681b ldr r3, [r3, #0] 80034a0: 4618 mov r0, r3 80034a2: f004 ffd5 bl 8008450 80034a6: 4603 mov r3, r0 80034a8: f403 5300 and.w r3, r3, #8192 @ 0x2000 80034ac: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80034b0: d123 bne.n 80034fa { (void)USB_ActivateSetup(hpcd->Instance); 80034b2: 687b ldr r3, [r7, #4] 80034b4: 681b ldr r3, [r3, #0] 80034b6: 4618 mov r0, r3 80034b8: f005 f86b bl 8008592 hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); 80034bc: 687b ldr r3, [r7, #4] 80034be: 681b ldr r3, [r3, #0] 80034c0: 4618 mov r0, r3 80034c2: f004 f922 bl 800770a 80034c6: 4603 mov r3, r0 80034c8: 461a mov r2, r3 80034ca: 687b ldr r3, [r7, #4] 80034cc: 71da strb r2, [r3, #7] /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, 80034ce: 687b ldr r3, [r7, #4] 80034d0: 681c ldr r4, [r3, #0] 80034d2: f000 fe8b bl 80041ec 80034d6: 4601 mov r1, r0 HAL_RCC_GetHCLKFreq(), (uint8_t)hpcd->Init.speed); 80034d8: 687b ldr r3, [r7, #4] 80034da: 79db ldrb r3, [r3, #7] (void)USB_SetTurnaroundTime(hpcd->Instance, 80034dc: 461a mov r2, r3 80034de: 4620 mov r0, r4 80034e0: f003 fe2c bl 800713c #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 80034e4: 6878 ldr r0, [r7, #4] 80034e6: f007 f896 bl 800a616 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); 80034ea: 687b ldr r3, [r7, #4] 80034ec: 681b ldr r3, [r3, #0] 80034ee: 695a ldr r2, [r3, #20] 80034f0: 687b ldr r3, [r7, #4] 80034f2: 681b ldr r3, [r3, #0] 80034f4: f402 5200 and.w r2, r2, #8192 @ 0x2000 80034f8: 615a str r2, [r3, #20] } /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) 80034fa: 687b ldr r3, [r7, #4] 80034fc: 681b ldr r3, [r3, #0] 80034fe: 4618 mov r0, r3 8003500: f004 ffa6 bl 8008450 8003504: 4603 mov r3, r0 8003506: f003 0308 and.w r3, r3, #8 800350a: 2b08 cmp r3, #8 800350c: d10a bne.n 8003524 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 800350e: 6878 ldr r0, [r7, #4] 8003510: f007 f873 bl 800a5fa #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); 8003514: 687b ldr r3, [r7, #4] 8003516: 681b ldr r3, [r3, #0] 8003518: 695a ldr r2, [r3, #20] 800351a: 687b ldr r3, [r7, #4] 800351c: 681b ldr r3, [r3, #0] 800351e: f002 0208 and.w r2, r2, #8 8003522: 615a str r2, [r3, #20] } /* Handle Global OUT NAK effective Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) 8003524: 687b ldr r3, [r7, #4] 8003526: 681b ldr r3, [r3, #0] 8003528: 4618 mov r0, r3 800352a: f004 ff91 bl 8008450 800352e: 4603 mov r3, r0 8003530: f003 0380 and.w r3, r3, #128 @ 0x80 8003534: 2b80 cmp r3, #128 @ 0x80 8003536: d123 bne.n 8003580 { USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; 8003538: 6a3b ldr r3, [r7, #32] 800353a: 699b ldr r3, [r3, #24] 800353c: f023 0280 bic.w r2, r3, #128 @ 0x80 8003540: 6a3b ldr r3, [r7, #32] 8003542: 619a str r2, [r3, #24] for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003544: 2301 movs r3, #1 8003546: 627b str r3, [r7, #36] @ 0x24 8003548: e014 b.n 8003574 { if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) 800354a: 6879 ldr r1, [r7, #4] 800354c: 6a7a ldr r2, [r7, #36] @ 0x24 800354e: 4613 mov r3, r2 8003550: 00db lsls r3, r3, #3 8003552: 4413 add r3, r2 8003554: 009b lsls r3, r3, #2 8003556: 440b add r3, r1 8003558: f203 2357 addw r3, r3, #599 @ 0x257 800355c: 781b ldrb r3, [r3, #0] 800355e: 2b01 cmp r3, #1 8003560: d105 bne.n 800356e { /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); 8003562: 6a7b ldr r3, [r7, #36] @ 0x24 8003564: b2db uxtb r3, r3 8003566: 4619 mov r1, r3 8003568: 6878 ldr r0, [r7, #4] 800356a: f000 faf2 bl 8003b52 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 800356e: 6a7b ldr r3, [r7, #36] @ 0x24 8003570: 3301 adds r3, #1 8003572: 627b str r3, [r7, #36] @ 0x24 8003574: 687b ldr r3, [r7, #4] 8003576: 791b ldrb r3, [r3, #4] 8003578: 461a mov r2, r3 800357a: 6a7b ldr r3, [r7, #36] @ 0x24 800357c: 4293 cmp r3, r2 800357e: d3e4 bcc.n 800354a } } } /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) 8003580: 687b ldr r3, [r7, #4] 8003582: 681b ldr r3, [r3, #0] 8003584: 4618 mov r0, r3 8003586: f004 ff63 bl 8008450 800358a: 4603 mov r3, r0 800358c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8003590: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8003594: d13c bne.n 8003610 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003596: 2301 movs r3, #1 8003598: 627b str r3, [r7, #36] @ 0x24 800359a: e02b b.n 80035f4 { RegVal = USBx_INEP(epnum)->DIEPCTL; 800359c: 6a7b ldr r3, [r7, #36] @ 0x24 800359e: 015a lsls r2, r3, #5 80035a0: 69fb ldr r3, [r7, #28] 80035a2: 4413 add r3, r2 80035a4: f503 6310 add.w r3, r3, #2304 @ 0x900 80035a8: 681b ldr r3, [r3, #0] 80035aa: 61bb str r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 80035ac: 6879 ldr r1, [r7, #4] 80035ae: 6a7a ldr r2, [r7, #36] @ 0x24 80035b0: 4613 mov r3, r2 80035b2: 00db lsls r3, r3, #3 80035b4: 4413 add r3, r2 80035b6: 009b lsls r3, r3, #2 80035b8: 440b add r3, r1 80035ba: 3318 adds r3, #24 80035bc: 781b ldrb r3, [r3, #0] 80035be: 2b01 cmp r3, #1 80035c0: d115 bne.n 80035ee ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) 80035c2: 69bb ldr r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 80035c4: 2b00 cmp r3, #0 80035c6: da12 bge.n 80035ee { hpcd->IN_ep[epnum].is_iso_incomplete = 1U; 80035c8: 6879 ldr r1, [r7, #4] 80035ca: 6a7a ldr r2, [r7, #36] @ 0x24 80035cc: 4613 mov r3, r2 80035ce: 00db lsls r3, r3, #3 80035d0: 4413 add r3, r2 80035d2: 009b lsls r3, r3, #2 80035d4: 440b add r3, r1 80035d6: 3317 adds r3, #23 80035d8: 2201 movs r2, #1 80035da: 701a strb r2, [r3, #0] /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); 80035dc: 6a7b ldr r3, [r7, #36] @ 0x24 80035de: b2db uxtb r3, r3 80035e0: f063 037f orn r3, r3, #127 @ 0x7f 80035e4: b2db uxtb r3, r3 80035e6: 4619 mov r1, r3 80035e8: 6878 ldr r0, [r7, #4] 80035ea: f000 fab2 bl 8003b52 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80035ee: 6a7b ldr r3, [r7, #36] @ 0x24 80035f0: 3301 adds r3, #1 80035f2: 627b str r3, [r7, #36] @ 0x24 80035f4: 687b ldr r3, [r7, #4] 80035f6: 791b ldrb r3, [r3, #4] 80035f8: 461a mov r2, r3 80035fa: 6a7b ldr r3, [r7, #36] @ 0x24 80035fc: 4293 cmp r3, r2 80035fe: d3cd bcc.n 800359c } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); 8003600: 687b ldr r3, [r7, #4] 8003602: 681b ldr r3, [r3, #0] 8003604: 695a ldr r2, [r3, #20] 8003606: 687b ldr r3, [r7, #4] 8003608: 681b ldr r3, [r3, #0] 800360a: f402 1280 and.w r2, r2, #1048576 @ 0x100000 800360e: 615a str r2, [r3, #20] } /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 8003610: 687b ldr r3, [r7, #4] 8003612: 681b ldr r3, [r3, #0] 8003614: 4618 mov r0, r3 8003616: f004 ff1b bl 8008450 800361a: 4603 mov r3, r0 800361c: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8003620: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8003624: d156 bne.n 80036d4 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003626: 2301 movs r3, #1 8003628: 627b str r3, [r7, #36] @ 0x24 800362a: e045 b.n 80036b8 { RegVal = USBx_OUTEP(epnum)->DOEPCTL; 800362c: 6a7b ldr r3, [r7, #36] @ 0x24 800362e: 015a lsls r2, r3, #5 8003630: 69fb ldr r3, [r7, #28] 8003632: 4413 add r3, r2 8003634: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003638: 681b ldr r3, [r3, #0] 800363a: 61bb str r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 800363c: 6879 ldr r1, [r7, #4] 800363e: 6a7a ldr r2, [r7, #36] @ 0x24 8003640: 4613 mov r3, r2 8003642: 00db lsls r3, r3, #3 8003644: 4413 add r3, r2 8003646: 009b lsls r3, r3, #2 8003648: 440b add r3, r1 800364a: f503 7316 add.w r3, r3, #600 @ 0x258 800364e: 781b ldrb r3, [r3, #0] 8003650: 2b01 cmp r3, #1 8003652: d12e bne.n 80036b2 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 8003654: 69bb ldr r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 8003656: 2b00 cmp r3, #0 8003658: da2b bge.n 80036b2 (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) 800365a: 69bb ldr r3, [r7, #24] 800365c: 0c1a lsrs r2, r3, #16 800365e: 687b ldr r3, [r7, #4] 8003660: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4 8003664: 4053 eors r3, r2 8003666: f003 0301 and.w r3, r3, #1 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 800366a: 2b00 cmp r3, #0 800366c: d121 bne.n 80036b2 { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; 800366e: 6879 ldr r1, [r7, #4] 8003670: 6a7a ldr r2, [r7, #36] @ 0x24 8003672: 4613 mov r3, r2 8003674: 00db lsls r3, r3, #3 8003676: 4413 add r3, r2 8003678: 009b lsls r3, r3, #2 800367a: 440b add r3, r1 800367c: f203 2357 addw r3, r3, #599 @ 0x257 8003680: 2201 movs r2, #1 8003682: 701a strb r2, [r3, #0] USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; 8003684: 6a3b ldr r3, [r7, #32] 8003686: 699b ldr r3, [r3, #24] 8003688: f043 0280 orr.w r2, r3, #128 @ 0x80 800368c: 6a3b ldr r3, [r7, #32] 800368e: 619a str r2, [r3, #24] if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) 8003690: 6a3b ldr r3, [r7, #32] 8003692: 695b ldr r3, [r3, #20] 8003694: f003 0380 and.w r3, r3, #128 @ 0x80 8003698: 2b00 cmp r3, #0 800369a: d10a bne.n 80036b2 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; 800369c: 69fb ldr r3, [r7, #28] 800369e: f503 6300 add.w r3, r3, #2048 @ 0x800 80036a2: 685b ldr r3, [r3, #4] 80036a4: 69fa ldr r2, [r7, #28] 80036a6: f502 6200 add.w r2, r2, #2048 @ 0x800 80036aa: f443 7300 orr.w r3, r3, #512 @ 0x200 80036ae: 6053 str r3, [r2, #4] break; 80036b0: e008 b.n 80036c4 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80036b2: 6a7b ldr r3, [r7, #36] @ 0x24 80036b4: 3301 adds r3, #1 80036b6: 627b str r3, [r7, #36] @ 0x24 80036b8: 687b ldr r3, [r7, #4] 80036ba: 791b ldrb r3, [r3, #4] 80036bc: 461a mov r2, r3 80036be: 6a7b ldr r3, [r7, #36] @ 0x24 80036c0: 4293 cmp r3, r2 80036c2: d3b3 bcc.n 800362c } } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 80036c4: 687b ldr r3, [r7, #4] 80036c6: 681b ldr r3, [r3, #0] 80036c8: 695a ldr r2, [r3, #20] 80036ca: 687b ldr r3, [r7, #4] 80036cc: 681b ldr r3, [r3, #0] 80036ce: f402 1200 and.w r2, r2, #2097152 @ 0x200000 80036d2: 615a str r2, [r3, #20] } /* Handle Connection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) 80036d4: 687b ldr r3, [r7, #4] 80036d6: 681b ldr r3, [r3, #0] 80036d8: 4618 mov r0, r3 80036da: f004 feb9 bl 8008450 80036de: 4603 mov r3, r0 80036e0: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 80036e4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80036e8: d10a bne.n 8003700 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ConnectCallback(hpcd); #else HAL_PCD_ConnectCallback(hpcd); 80036ea: 6878 ldr r0, [r7, #4] 80036ec: f007 f814 bl 800a718 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); 80036f0: 687b ldr r3, [r7, #4] 80036f2: 681b ldr r3, [r3, #0] 80036f4: 695a ldr r2, [r3, #20] 80036f6: 687b ldr r3, [r7, #4] 80036f8: 681b ldr r3, [r3, #0] 80036fa: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 80036fe: 615a str r2, [r3, #20] } /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) 8003700: 687b ldr r3, [r7, #4] 8003702: 681b ldr r3, [r3, #0] 8003704: 4618 mov r0, r3 8003706: f004 fea3 bl 8008450 800370a: 4603 mov r3, r0 800370c: f003 0304 and.w r3, r3, #4 8003710: 2b04 cmp r3, #4 8003712: d115 bne.n 8003740 { RegVal = hpcd->Instance->GOTGINT; 8003714: 687b ldr r3, [r7, #4] 8003716: 681b ldr r3, [r3, #0] 8003718: 685b ldr r3, [r3, #4] 800371a: 61bb str r3, [r7, #24] if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) 800371c: 69bb ldr r3, [r7, #24] 800371e: f003 0304 and.w r3, r3, #4 8003722: 2b00 cmp r3, #0 8003724: d002 beq.n 800372c { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); #else HAL_PCD_DisconnectCallback(hpcd); 8003726: 6878 ldr r0, [r7, #4] 8003728: f007 f804 bl 800a734 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= RegVal; 800372c: 687b ldr r3, [r7, #4] 800372e: 681b ldr r3, [r3, #0] 8003730: 6859 ldr r1, [r3, #4] 8003732: 687b ldr r3, [r7, #4] 8003734: 681b ldr r3, [r3, #0] 8003736: 69ba ldr r2, [r7, #24] 8003738: 430a orrs r2, r1 800373a: 605a str r2, [r3, #4] 800373c: e000 b.n 8003740 return; 800373e: bf00 nop } } } 8003740: 3734 adds r7, #52 @ 0x34 8003742: 46bd mov sp, r7 8003744: bd90 pop {r4, r7, pc} 08003746 : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 8003746: b580 push {r7, lr} 8003748: b082 sub sp, #8 800374a: af00 add r7, sp, #0 800374c: 6078 str r0, [r7, #4] 800374e: 460b mov r3, r1 8003750: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 8003752: 687b ldr r3, [r7, #4] 8003754: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003758: 2b01 cmp r3, #1 800375a: d101 bne.n 8003760 800375c: 2302 movs r3, #2 800375e: e012 b.n 8003786 8003760: 687b ldr r3, [r7, #4] 8003762: 2201 movs r2, #1 8003764: f883 2494 strb.w r2, [r3, #1172] @ 0x494 hpcd->USB_Address = address; 8003768: 687b ldr r3, [r7, #4] 800376a: 78fa ldrb r2, [r7, #3] 800376c: 745a strb r2, [r3, #17] (void)USB_SetDevAddress(hpcd->Instance, address); 800376e: 687b ldr r3, [r7, #4] 8003770: 681b ldr r3, [r3, #0] 8003772: 78fa ldrb r2, [r7, #3] 8003774: 4611 mov r1, r2 8003776: 4618 mov r0, r3 8003778: f004 fe02 bl 8008380 __HAL_UNLOCK(hpcd); 800377c: 687b ldr r3, [r7, #4] 800377e: 2200 movs r2, #0 8003780: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003784: 2300 movs r3, #0 } 8003786: 4618 mov r0, r3 8003788: 3708 adds r7, #8 800378a: 46bd mov sp, r7 800378c: bd80 pop {r7, pc} 0800378e : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 800378e: b580 push {r7, lr} 8003790: b084 sub sp, #16 8003792: af00 add r7, sp, #0 8003794: 6078 str r0, [r7, #4] 8003796: 4608 mov r0, r1 8003798: 4611 mov r1, r2 800379a: 461a mov r2, r3 800379c: 4603 mov r3, r0 800379e: 70fb strb r3, [r7, #3] 80037a0: 460b mov r3, r1 80037a2: 803b strh r3, [r7, #0] 80037a4: 4613 mov r3, r2 80037a6: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 80037a8: 2300 movs r3, #0 80037aa: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 80037ac: f997 3003 ldrsb.w r3, [r7, #3] 80037b0: 2b00 cmp r3, #0 80037b2: da0f bge.n 80037d4 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 80037b4: 78fb ldrb r3, [r7, #3] 80037b6: f003 020f and.w r2, r3, #15 80037ba: 4613 mov r3, r2 80037bc: 00db lsls r3, r3, #3 80037be: 4413 add r3, r2 80037c0: 009b lsls r3, r3, #2 80037c2: 3310 adds r3, #16 80037c4: 687a ldr r2, [r7, #4] 80037c6: 4413 add r3, r2 80037c8: 3304 adds r3, #4 80037ca: 60fb str r3, [r7, #12] ep->is_in = 1U; 80037cc: 68fb ldr r3, [r7, #12] 80037ce: 2201 movs r2, #1 80037d0: 705a strb r2, [r3, #1] 80037d2: e00f b.n 80037f4 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80037d4: 78fb ldrb r3, [r7, #3] 80037d6: f003 020f and.w r2, r3, #15 80037da: 4613 mov r3, r2 80037dc: 00db lsls r3, r3, #3 80037de: 4413 add r3, r2 80037e0: 009b lsls r3, r3, #2 80037e2: f503 7314 add.w r3, r3, #592 @ 0x250 80037e6: 687a ldr r2, [r7, #4] 80037e8: 4413 add r3, r2 80037ea: 3304 adds r3, #4 80037ec: 60fb str r3, [r7, #12] ep->is_in = 0U; 80037ee: 68fb ldr r3, [r7, #12] 80037f0: 2200 movs r2, #0 80037f2: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 80037f4: 78fb ldrb r3, [r7, #3] 80037f6: f003 030f and.w r3, r3, #15 80037fa: b2da uxtb r2, r3 80037fc: 68fb ldr r3, [r7, #12] 80037fe: 701a strb r2, [r3, #0] ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; 8003800: 883b ldrh r3, [r7, #0] 8003802: f3c3 020a ubfx r2, r3, #0, #11 8003806: 68fb ldr r3, [r7, #12] 8003808: 609a str r2, [r3, #8] ep->type = ep_type; 800380a: 68fb ldr r3, [r7, #12] 800380c: 78ba ldrb r2, [r7, #2] 800380e: 711a strb r2, [r3, #4] if (ep->is_in != 0U) 8003810: 68fb ldr r3, [r7, #12] 8003812: 785b ldrb r3, [r3, #1] 8003814: 2b00 cmp r3, #0 8003816: d004 beq.n 8003822 { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; 8003818: 68fb ldr r3, [r7, #12] 800381a: 781b ldrb r3, [r3, #0] 800381c: 461a mov r2, r3 800381e: 68fb ldr r3, [r7, #12] 8003820: 835a strh r2, [r3, #26] } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 8003822: 78bb ldrb r3, [r7, #2] 8003824: 2b02 cmp r3, #2 8003826: d102 bne.n 800382e { ep->data_pid_start = 0U; 8003828: 68fb ldr r3, [r7, #12] 800382a: 2200 movs r2, #0 800382c: 715a strb r2, [r3, #5] } __HAL_LOCK(hpcd); 800382e: 687b ldr r3, [r7, #4] 8003830: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003834: 2b01 cmp r3, #1 8003836: d101 bne.n 800383c 8003838: 2302 movs r3, #2 800383a: e00e b.n 800385a 800383c: 687b ldr r3, [r7, #4] 800383e: 2201 movs r2, #1 8003840: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_ActivateEndpoint(hpcd->Instance, ep); 8003844: 687b ldr r3, [r7, #4] 8003846: 681b ldr r3, [r3, #0] 8003848: 68f9 ldr r1, [r7, #12] 800384a: 4618 mov r0, r3 800384c: f003 ff82 bl 8007754 __HAL_UNLOCK(hpcd); 8003850: 687b ldr r3, [r7, #4] 8003852: 2200 movs r2, #0 8003854: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return ret; 8003858: 7afb ldrb r3, [r7, #11] } 800385a: 4618 mov r0, r3 800385c: 3710 adds r7, #16 800385e: 46bd mov sp, r7 8003860: bd80 pop {r7, pc} 08003862 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003862: b580 push {r7, lr} 8003864: b084 sub sp, #16 8003866: af00 add r7, sp, #0 8003868: 6078 str r0, [r7, #4] 800386a: 460b mov r3, r1 800386c: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 800386e: f997 3003 ldrsb.w r3, [r7, #3] 8003872: 2b00 cmp r3, #0 8003874: da0f bge.n 8003896 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003876: 78fb ldrb r3, [r7, #3] 8003878: f003 020f and.w r2, r3, #15 800387c: 4613 mov r3, r2 800387e: 00db lsls r3, r3, #3 8003880: 4413 add r3, r2 8003882: 009b lsls r3, r3, #2 8003884: 3310 adds r3, #16 8003886: 687a ldr r2, [r7, #4] 8003888: 4413 add r3, r2 800388a: 3304 adds r3, #4 800388c: 60fb str r3, [r7, #12] ep->is_in = 1U; 800388e: 68fb ldr r3, [r7, #12] 8003890: 2201 movs r2, #1 8003892: 705a strb r2, [r3, #1] 8003894: e00f b.n 80038b6 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003896: 78fb ldrb r3, [r7, #3] 8003898: f003 020f and.w r2, r3, #15 800389c: 4613 mov r3, r2 800389e: 00db lsls r3, r3, #3 80038a0: 4413 add r3, r2 80038a2: 009b lsls r3, r3, #2 80038a4: f503 7314 add.w r3, r3, #592 @ 0x250 80038a8: 687a ldr r2, [r7, #4] 80038aa: 4413 add r3, r2 80038ac: 3304 adds r3, #4 80038ae: 60fb str r3, [r7, #12] ep->is_in = 0U; 80038b0: 68fb ldr r3, [r7, #12] 80038b2: 2200 movs r2, #0 80038b4: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 80038b6: 78fb ldrb r3, [r7, #3] 80038b8: f003 030f and.w r3, r3, #15 80038bc: b2da uxtb r2, r3 80038be: 68fb ldr r3, [r7, #12] 80038c0: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 80038c2: 687b ldr r3, [r7, #4] 80038c4: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 80038c8: 2b01 cmp r3, #1 80038ca: d101 bne.n 80038d0 80038cc: 2302 movs r3, #2 80038ce: e00e b.n 80038ee 80038d0: 687b ldr r3, [r7, #4] 80038d2: 2201 movs r2, #1 80038d4: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 80038d8: 687b ldr r3, [r7, #4] 80038da: 681b ldr r3, [r3, #0] 80038dc: 68f9 ldr r1, [r7, #12] 80038de: 4618 mov r0, r3 80038e0: f003 ffc0 bl 8007864 __HAL_UNLOCK(hpcd); 80038e4: 687b ldr r3, [r7, #4] 80038e6: 2200 movs r2, #0 80038e8: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 80038ec: 2300 movs r3, #0 } 80038ee: 4618 mov r0, r3 80038f0: 3710 adds r7, #16 80038f2: 46bd mov sp, r7 80038f4: bd80 pop {r7, pc} 080038f6 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 80038f6: b580 push {r7, lr} 80038f8: b086 sub sp, #24 80038fa: af00 add r7, sp, #0 80038fc: 60f8 str r0, [r7, #12] 80038fe: 607a str r2, [r7, #4] 8003900: 603b str r3, [r7, #0] 8003902: 460b mov r3, r1 8003904: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003906: 7afb ldrb r3, [r7, #11] 8003908: f003 020f and.w r2, r3, #15 800390c: 4613 mov r3, r2 800390e: 00db lsls r3, r3, #3 8003910: 4413 add r3, r2 8003912: 009b lsls r3, r3, #2 8003914: f503 7314 add.w r3, r3, #592 @ 0x250 8003918: 68fa ldr r2, [r7, #12] 800391a: 4413 add r3, r2 800391c: 3304 adds r3, #4 800391e: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003920: 697b ldr r3, [r7, #20] 8003922: 687a ldr r2, [r7, #4] 8003924: 60da str r2, [r3, #12] ep->xfer_len = len; 8003926: 697b ldr r3, [r7, #20] 8003928: 683a ldr r2, [r7, #0] 800392a: 611a str r2, [r3, #16] ep->xfer_count = 0U; 800392c: 697b ldr r3, [r7, #20] 800392e: 2200 movs r2, #0 8003930: 615a str r2, [r3, #20] ep->is_in = 0U; 8003932: 697b ldr r3, [r7, #20] 8003934: 2200 movs r2, #0 8003936: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8003938: 7afb ldrb r3, [r7, #11] 800393a: f003 030f and.w r3, r3, #15 800393e: b2da uxtb r2, r3 8003940: 697b ldr r3, [r7, #20] 8003942: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003944: 68fb ldr r3, [r7, #12] 8003946: 799b ldrb r3, [r3, #6] 8003948: 2b01 cmp r3, #1 800394a: d102 bne.n 8003952 { ep->dma_addr = (uint32_t)pBuf; 800394c: 687a ldr r2, [r7, #4] 800394e: 697b ldr r3, [r7, #20] 8003950: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003952: 68fb ldr r3, [r7, #12] 8003954: 6818 ldr r0, [r3, #0] 8003956: 68fb ldr r3, [r7, #12] 8003958: 799b ldrb r3, [r3, #6] 800395a: 461a mov r2, r3 800395c: 6979 ldr r1, [r7, #20] 800395e: f004 f85d bl 8007a1c return HAL_OK; 8003962: 2300 movs r3, #0 } 8003964: 4618 mov r0, r3 8003966: 3718 adds r7, #24 8003968: 46bd mov sp, r7 800396a: bd80 pop {r7, pc} 0800396c : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 800396c: b580 push {r7, lr} 800396e: b086 sub sp, #24 8003970: af00 add r7, sp, #0 8003972: 60f8 str r0, [r7, #12] 8003974: 607a str r2, [r7, #4] 8003976: 603b str r3, [r7, #0] 8003978: 460b mov r3, r1 800397a: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800397c: 7afb ldrb r3, [r7, #11] 800397e: f003 020f and.w r2, r3, #15 8003982: 4613 mov r3, r2 8003984: 00db lsls r3, r3, #3 8003986: 4413 add r3, r2 8003988: 009b lsls r3, r3, #2 800398a: 3310 adds r3, #16 800398c: 68fa ldr r2, [r7, #12] 800398e: 4413 add r3, r2 8003990: 3304 adds r3, #4 8003992: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003994: 697b ldr r3, [r7, #20] 8003996: 687a ldr r2, [r7, #4] 8003998: 60da str r2, [r3, #12] ep->xfer_len = len; 800399a: 697b ldr r3, [r7, #20] 800399c: 683a ldr r2, [r7, #0] 800399e: 611a str r2, [r3, #16] ep->xfer_count = 0U; 80039a0: 697b ldr r3, [r7, #20] 80039a2: 2200 movs r2, #0 80039a4: 615a str r2, [r3, #20] ep->is_in = 1U; 80039a6: 697b ldr r3, [r7, #20] 80039a8: 2201 movs r2, #1 80039aa: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 80039ac: 7afb ldrb r3, [r7, #11] 80039ae: f003 030f and.w r3, r3, #15 80039b2: b2da uxtb r2, r3 80039b4: 697b ldr r3, [r7, #20] 80039b6: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 80039b8: 68fb ldr r3, [r7, #12] 80039ba: 799b ldrb r3, [r3, #6] 80039bc: 2b01 cmp r3, #1 80039be: d102 bne.n 80039c6 { ep->dma_addr = (uint32_t)pBuf; 80039c0: 687a ldr r2, [r7, #4] 80039c2: 697b ldr r3, [r7, #20] 80039c4: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 80039c6: 68fb ldr r3, [r7, #12] 80039c8: 6818 ldr r0, [r3, #0] 80039ca: 68fb ldr r3, [r7, #12] 80039cc: 799b ldrb r3, [r3, #6] 80039ce: 461a mov r2, r3 80039d0: 6979 ldr r1, [r7, #20] 80039d2: f004 f823 bl 8007a1c return HAL_OK; 80039d6: 2300 movs r3, #0 } 80039d8: 4618 mov r0, r3 80039da: 3718 adds r7, #24 80039dc: 46bd mov sp, r7 80039de: bd80 pop {r7, pc} 080039e0 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 80039e0: b580 push {r7, lr} 80039e2: b084 sub sp, #16 80039e4: af00 add r7, sp, #0 80039e6: 6078 str r0, [r7, #4] 80039e8: 460b mov r3, r1 80039ea: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 80039ec: 78fb ldrb r3, [r7, #3] 80039ee: f003 030f and.w r3, r3, #15 80039f2: 687a ldr r2, [r7, #4] 80039f4: 7912 ldrb r2, [r2, #4] 80039f6: 4293 cmp r3, r2 80039f8: d901 bls.n 80039fe { return HAL_ERROR; 80039fa: 2301 movs r3, #1 80039fc: e04f b.n 8003a9e } if ((0x80U & ep_addr) == 0x80U) 80039fe: f997 3003 ldrsb.w r3, [r7, #3] 8003a02: 2b00 cmp r3, #0 8003a04: da0f bge.n 8003a26 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003a06: 78fb ldrb r3, [r7, #3] 8003a08: f003 020f and.w r2, r3, #15 8003a0c: 4613 mov r3, r2 8003a0e: 00db lsls r3, r3, #3 8003a10: 4413 add r3, r2 8003a12: 009b lsls r3, r3, #2 8003a14: 3310 adds r3, #16 8003a16: 687a ldr r2, [r7, #4] 8003a18: 4413 add r3, r2 8003a1a: 3304 adds r3, #4 8003a1c: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003a1e: 68fb ldr r3, [r7, #12] 8003a20: 2201 movs r2, #1 8003a22: 705a strb r2, [r3, #1] 8003a24: e00d b.n 8003a42 } else { ep = &hpcd->OUT_ep[ep_addr]; 8003a26: 78fa ldrb r2, [r7, #3] 8003a28: 4613 mov r3, r2 8003a2a: 00db lsls r3, r3, #3 8003a2c: 4413 add r3, r2 8003a2e: 009b lsls r3, r3, #2 8003a30: f503 7314 add.w r3, r3, #592 @ 0x250 8003a34: 687a ldr r2, [r7, #4] 8003a36: 4413 add r3, r2 8003a38: 3304 adds r3, #4 8003a3a: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003a3c: 68fb ldr r3, [r7, #12] 8003a3e: 2200 movs r2, #0 8003a40: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8003a42: 68fb ldr r3, [r7, #12] 8003a44: 2201 movs r2, #1 8003a46: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003a48: 78fb ldrb r3, [r7, #3] 8003a4a: f003 030f and.w r3, r3, #15 8003a4e: b2da uxtb r2, r3 8003a50: 68fb ldr r3, [r7, #12] 8003a52: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003a54: 687b ldr r3, [r7, #4] 8003a56: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003a5a: 2b01 cmp r3, #1 8003a5c: d101 bne.n 8003a62 8003a5e: 2302 movs r3, #2 8003a60: e01d b.n 8003a9e 8003a62: 687b ldr r3, [r7, #4] 8003a64: 2201 movs r2, #1 8003a66: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPSetStall(hpcd->Instance, ep); 8003a6a: 687b ldr r3, [r7, #4] 8003a6c: 681b ldr r3, [r3, #0] 8003a6e: 68f9 ldr r1, [r7, #12] 8003a70: 4618 mov r0, r3 8003a72: f004 fbb1 bl 80081d8 if ((ep_addr & EP_ADDR_MSK) == 0U) 8003a76: 78fb ldrb r3, [r7, #3] 8003a78: f003 030f and.w r3, r3, #15 8003a7c: 2b00 cmp r3, #0 8003a7e: d109 bne.n 8003a94 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); 8003a80: 687b ldr r3, [r7, #4] 8003a82: 6818 ldr r0, [r3, #0] 8003a84: 687b ldr r3, [r7, #4] 8003a86: 7999 ldrb r1, [r3, #6] 8003a88: 687b ldr r3, [r7, #4] 8003a8a: f203 439c addw r3, r3, #1180 @ 0x49c 8003a8e: 461a mov r2, r3 8003a90: f004 fda2 bl 80085d8 } __HAL_UNLOCK(hpcd); 8003a94: 687b ldr r3, [r7, #4] 8003a96: 2200 movs r2, #0 8003a98: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003a9c: 2300 movs r3, #0 } 8003a9e: 4618 mov r0, r3 8003aa0: 3710 adds r7, #16 8003aa2: 46bd mov sp, r7 8003aa4: bd80 pop {r7, pc} 08003aa6 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003aa6: b580 push {r7, lr} 8003aa8: b084 sub sp, #16 8003aaa: af00 add r7, sp, #0 8003aac: 6078 str r0, [r7, #4] 8003aae: 460b mov r3, r1 8003ab0: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8003ab2: 78fb ldrb r3, [r7, #3] 8003ab4: f003 030f and.w r3, r3, #15 8003ab8: 687a ldr r2, [r7, #4] 8003aba: 7912 ldrb r2, [r2, #4] 8003abc: 4293 cmp r3, r2 8003abe: d901 bls.n 8003ac4 { return HAL_ERROR; 8003ac0: 2301 movs r3, #1 8003ac2: e042 b.n 8003b4a } if ((0x80U & ep_addr) == 0x80U) 8003ac4: f997 3003 ldrsb.w r3, [r7, #3] 8003ac8: 2b00 cmp r3, #0 8003aca: da0f bge.n 8003aec { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003acc: 78fb ldrb r3, [r7, #3] 8003ace: f003 020f and.w r2, r3, #15 8003ad2: 4613 mov r3, r2 8003ad4: 00db lsls r3, r3, #3 8003ad6: 4413 add r3, r2 8003ad8: 009b lsls r3, r3, #2 8003ada: 3310 adds r3, #16 8003adc: 687a ldr r2, [r7, #4] 8003ade: 4413 add r3, r2 8003ae0: 3304 adds r3, #4 8003ae2: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003ae4: 68fb ldr r3, [r7, #12] 8003ae6: 2201 movs r2, #1 8003ae8: 705a strb r2, [r3, #1] 8003aea: e00f b.n 8003b0c } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003aec: 78fb ldrb r3, [r7, #3] 8003aee: f003 020f and.w r2, r3, #15 8003af2: 4613 mov r3, r2 8003af4: 00db lsls r3, r3, #3 8003af6: 4413 add r3, r2 8003af8: 009b lsls r3, r3, #2 8003afa: f503 7314 add.w r3, r3, #592 @ 0x250 8003afe: 687a ldr r2, [r7, #4] 8003b00: 4413 add r3, r2 8003b02: 3304 adds r3, #4 8003b04: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003b06: 68fb ldr r3, [r7, #12] 8003b08: 2200 movs r2, #0 8003b0a: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8003b0c: 68fb ldr r3, [r7, #12] 8003b0e: 2200 movs r2, #0 8003b10: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003b12: 78fb ldrb r3, [r7, #3] 8003b14: f003 030f and.w r3, r3, #15 8003b18: b2da uxtb r2, r3 8003b1a: 68fb ldr r3, [r7, #12] 8003b1c: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003b1e: 687b ldr r3, [r7, #4] 8003b20: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003b24: 2b01 cmp r3, #1 8003b26: d101 bne.n 8003b2c 8003b28: 2302 movs r3, #2 8003b2a: e00e b.n 8003b4a 8003b2c: 687b ldr r3, [r7, #4] 8003b2e: 2201 movs r2, #1 8003b30: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPClearStall(hpcd->Instance, ep); 8003b34: 687b ldr r3, [r7, #4] 8003b36: 681b ldr r3, [r3, #0] 8003b38: 68f9 ldr r1, [r7, #12] 8003b3a: 4618 mov r0, r3 8003b3c: f004 fbba bl 80082b4 __HAL_UNLOCK(hpcd); 8003b40: 687b ldr r3, [r7, #4] 8003b42: 2200 movs r2, #0 8003b44: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003b48: 2300 movs r3, #0 } 8003b4a: 4618 mov r0, r3 8003b4c: 3710 adds r7, #16 8003b4e: 46bd mov sp, r7 8003b50: bd80 pop {r7, pc} 08003b52 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003b52: b580 push {r7, lr} 8003b54: b084 sub sp, #16 8003b56: af00 add r7, sp, #0 8003b58: 6078 str r0, [r7, #4] 8003b5a: 460b mov r3, r1 8003b5c: 70fb strb r3, [r7, #3] HAL_StatusTypeDef ret; PCD_EPTypeDef *ep; if ((0x80U & ep_addr) == 0x80U) 8003b5e: f997 3003 ldrsb.w r3, [r7, #3] 8003b62: 2b00 cmp r3, #0 8003b64: da0c bge.n 8003b80 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003b66: 78fb ldrb r3, [r7, #3] 8003b68: f003 020f and.w r2, r3, #15 8003b6c: 4613 mov r3, r2 8003b6e: 00db lsls r3, r3, #3 8003b70: 4413 add r3, r2 8003b72: 009b lsls r3, r3, #2 8003b74: 3310 adds r3, #16 8003b76: 687a ldr r2, [r7, #4] 8003b78: 4413 add r3, r2 8003b7a: 3304 adds r3, #4 8003b7c: 60fb str r3, [r7, #12] 8003b7e: e00c b.n 8003b9a } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003b80: 78fb ldrb r3, [r7, #3] 8003b82: f003 020f and.w r2, r3, #15 8003b86: 4613 mov r3, r2 8003b88: 00db lsls r3, r3, #3 8003b8a: 4413 add r3, r2 8003b8c: 009b lsls r3, r3, #2 8003b8e: f503 7314 add.w r3, r3, #592 @ 0x250 8003b92: 687a ldr r2, [r7, #4] 8003b94: 4413 add r3, r2 8003b96: 3304 adds r3, #4 8003b98: 60fb str r3, [r7, #12] } /* Stop Xfer */ ret = USB_EPStopXfer(hpcd->Instance, ep); 8003b9a: 687b ldr r3, [r7, #4] 8003b9c: 681b ldr r3, [r3, #0] 8003b9e: 68f9 ldr r1, [r7, #12] 8003ba0: 4618 mov r0, r3 8003ba2: f004 f9d9 bl 8007f58 8003ba6: 4603 mov r3, r0 8003ba8: 72fb strb r3, [r7, #11] return ret; 8003baa: 7afb ldrb r3, [r7, #11] } 8003bac: 4618 mov r0, r3 8003bae: 3710 adds r7, #16 8003bb0: 46bd mov sp, r7 8003bb2: bd80 pop {r7, pc} 08003bb4 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003bb4: b580 push {r7, lr} 8003bb6: b08a sub sp, #40 @ 0x28 8003bb8: af02 add r7, sp, #8 8003bba: 6078 str r0, [r7, #4] 8003bbc: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003bbe: 687b ldr r3, [r7, #4] 8003bc0: 681b ldr r3, [r3, #0] 8003bc2: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003bc4: 697b ldr r3, [r7, #20] 8003bc6: 613b str r3, [r7, #16] USB_OTG_EPTypeDef *ep; uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; 8003bc8: 683a ldr r2, [r7, #0] 8003bca: 4613 mov r3, r2 8003bcc: 00db lsls r3, r3, #3 8003bce: 4413 add r3, r2 8003bd0: 009b lsls r3, r3, #2 8003bd2: 3310 adds r3, #16 8003bd4: 687a ldr r2, [r7, #4] 8003bd6: 4413 add r3, r2 8003bd8: 3304 adds r3, #4 8003bda: 60fb str r3, [r7, #12] if (ep->xfer_count > ep->xfer_len) 8003bdc: 68fb ldr r3, [r7, #12] 8003bde: 695a ldr r2, [r3, #20] 8003be0: 68fb ldr r3, [r7, #12] 8003be2: 691b ldr r3, [r3, #16] 8003be4: 429a cmp r2, r3 8003be6: d901 bls.n 8003bec { return HAL_ERROR; 8003be8: 2301 movs r3, #1 8003bea: e06b b.n 8003cc4 } len = ep->xfer_len - ep->xfer_count; 8003bec: 68fb ldr r3, [r7, #12] 8003bee: 691a ldr r2, [r3, #16] 8003bf0: 68fb ldr r3, [r7, #12] 8003bf2: 695b ldr r3, [r3, #20] 8003bf4: 1ad3 subs r3, r2, r3 8003bf6: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8003bf8: 68fb ldr r3, [r7, #12] 8003bfa: 689b ldr r3, [r3, #8] 8003bfc: 69fa ldr r2, [r7, #28] 8003bfe: 429a cmp r2, r3 8003c00: d902 bls.n 8003c08 { len = ep->maxpacket; 8003c02: 68fb ldr r3, [r7, #12] 8003c04: 689b ldr r3, [r3, #8] 8003c06: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8003c08: 69fb ldr r3, [r7, #28] 8003c0a: 3303 adds r3, #3 8003c0c: 089b lsrs r3, r3, #2 8003c0e: 61bb str r3, [r7, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003c10: e02a b.n 8003c68 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; 8003c12: 68fb ldr r3, [r7, #12] 8003c14: 691a ldr r2, [r3, #16] 8003c16: 68fb ldr r3, [r7, #12] 8003c18: 695b ldr r3, [r3, #20] 8003c1a: 1ad3 subs r3, r2, r3 8003c1c: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8003c1e: 68fb ldr r3, [r7, #12] 8003c20: 689b ldr r3, [r3, #8] 8003c22: 69fa ldr r2, [r7, #28] 8003c24: 429a cmp r2, r3 8003c26: d902 bls.n 8003c2e { len = ep->maxpacket; 8003c28: 68fb ldr r3, [r7, #12] 8003c2a: 689b ldr r3, [r3, #8] 8003c2c: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8003c2e: 69fb ldr r3, [r7, #28] 8003c30: 3303 adds r3, #3 8003c32: 089b lsrs r3, r3, #2 8003c34: 61bb str r3, [r7, #24] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8003c36: 68fb ldr r3, [r7, #12] 8003c38: 68d9 ldr r1, [r3, #12] 8003c3a: 683b ldr r3, [r7, #0] 8003c3c: b2da uxtb r2, r3 8003c3e: 69fb ldr r3, [r7, #28] 8003c40: b298 uxth r0, r3 (uint8_t)hpcd->Init.dma_enable); 8003c42: 687b ldr r3, [r7, #4] 8003c44: 799b ldrb r3, [r3, #6] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8003c46: 9300 str r3, [sp, #0] 8003c48: 4603 mov r3, r0 8003c4a: 6978 ldr r0, [r7, #20] 8003c4c: f004 fa2e bl 80080ac ep->xfer_buff += len; 8003c50: 68fb ldr r3, [r7, #12] 8003c52: 68da ldr r2, [r3, #12] 8003c54: 69fb ldr r3, [r7, #28] 8003c56: 441a add r2, r3 8003c58: 68fb ldr r3, [r7, #12] 8003c5a: 60da str r2, [r3, #12] ep->xfer_count += len; 8003c5c: 68fb ldr r3, [r7, #12] 8003c5e: 695a ldr r2, [r3, #20] 8003c60: 69fb ldr r3, [r7, #28] 8003c62: 441a add r2, r3 8003c64: 68fb ldr r3, [r7, #12] 8003c66: 615a str r2, [r3, #20] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003c68: 683b ldr r3, [r7, #0] 8003c6a: 015a lsls r2, r3, #5 8003c6c: 693b ldr r3, [r7, #16] 8003c6e: 4413 add r3, r2 8003c70: f503 6310 add.w r3, r3, #2304 @ 0x900 8003c74: 699b ldr r3, [r3, #24] 8003c76: b29b uxth r3, r3 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8003c78: 69ba ldr r2, [r7, #24] 8003c7a: 429a cmp r2, r3 8003c7c: d809 bhi.n 8003c92 8003c7e: 68fb ldr r3, [r7, #12] 8003c80: 695a ldr r2, [r3, #20] 8003c82: 68fb ldr r3, [r7, #12] 8003c84: 691b ldr r3, [r3, #16] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8003c86: 429a cmp r2, r3 8003c88: d203 bcs.n 8003c92 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8003c8a: 68fb ldr r3, [r7, #12] 8003c8c: 691b ldr r3, [r3, #16] 8003c8e: 2b00 cmp r3, #0 8003c90: d1bf bne.n 8003c12 } if (ep->xfer_len <= ep->xfer_count) 8003c92: 68fb ldr r3, [r7, #12] 8003c94: 691a ldr r2, [r3, #16] 8003c96: 68fb ldr r3, [r7, #12] 8003c98: 695b ldr r3, [r3, #20] 8003c9a: 429a cmp r2, r3 8003c9c: d811 bhi.n 8003cc2 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8003c9e: 683b ldr r3, [r7, #0] 8003ca0: f003 030f and.w r3, r3, #15 8003ca4: 2201 movs r2, #1 8003ca6: fa02 f303 lsl.w r3, r2, r3 8003caa: 60bb str r3, [r7, #8] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8003cac: 693b ldr r3, [r7, #16] 8003cae: f503 6300 add.w r3, r3, #2048 @ 0x800 8003cb2: 6b5a ldr r2, [r3, #52] @ 0x34 8003cb4: 68bb ldr r3, [r7, #8] 8003cb6: 43db mvns r3, r3 8003cb8: 6939 ldr r1, [r7, #16] 8003cba: f501 6100 add.w r1, r1, #2048 @ 0x800 8003cbe: 4013 ands r3, r2 8003cc0: 634b str r3, [r1, #52] @ 0x34 } return HAL_OK; 8003cc2: 2300 movs r3, #0 } 8003cc4: 4618 mov r0, r3 8003cc6: 3720 adds r7, #32 8003cc8: 46bd mov sp, r7 8003cca: bd80 pop {r7, pc} 08003ccc : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003ccc: b580 push {r7, lr} 8003cce: b088 sub sp, #32 8003cd0: af00 add r7, sp, #0 8003cd2: 6078 str r0, [r7, #4] 8003cd4: 6039 str r1, [r7, #0] USB_OTG_EPTypeDef *ep; const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003cd6: 687b ldr r3, [r7, #4] 8003cd8: 681b ldr r3, [r3, #0] 8003cda: 61fb str r3, [r7, #28] uint32_t USBx_BASE = (uint32_t)USBx; 8003cdc: 69fb ldr r3, [r7, #28] 8003cde: 61bb str r3, [r7, #24] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8003ce0: 69fb ldr r3, [r7, #28] 8003ce2: 333c adds r3, #60 @ 0x3c 8003ce4: 3304 adds r3, #4 8003ce6: 681b ldr r3, [r3, #0] 8003ce8: 617b str r3, [r7, #20] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003cea: 683b ldr r3, [r7, #0] 8003cec: 015a lsls r2, r3, #5 8003cee: 69bb ldr r3, [r7, #24] 8003cf0: 4413 add r3, r2 8003cf2: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003cf6: 689b ldr r3, [r3, #8] 8003cf8: 613b str r3, [r7, #16] if (hpcd->Init.dma_enable == 1U) 8003cfa: 687b ldr r3, [r7, #4] 8003cfc: 799b ldrb r3, [r3, #6] 8003cfe: 2b01 cmp r3, #1 8003d00: d17b bne.n 8003dfa { if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ 8003d02: 693b ldr r3, [r7, #16] 8003d04: f003 0308 and.w r3, r3, #8 8003d08: 2b00 cmp r3, #0 8003d0a: d015 beq.n 8003d38 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003d0c: 697b ldr r3, [r7, #20] 8003d0e: 4a61 ldr r2, [pc, #388] @ (8003e94 ) 8003d10: 4293 cmp r3, r2 8003d12: f240 80b9 bls.w 8003e88 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003d16: 693b ldr r3, [r7, #16] 8003d18: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003d1c: 2b00 cmp r3, #0 8003d1e: f000 80b3 beq.w 8003e88 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003d22: 683b ldr r3, [r7, #0] 8003d24: 015a lsls r2, r3, #5 8003d26: 69bb ldr r3, [r7, #24] 8003d28: 4413 add r3, r2 8003d2a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003d2e: 461a mov r2, r3 8003d30: f44f 4300 mov.w r3, #32768 @ 0x8000 8003d34: 6093 str r3, [r2, #8] 8003d36: e0a7 b.n 8003e88 } } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ 8003d38: 693b ldr r3, [r7, #16] 8003d3a: f003 0320 and.w r3, r3, #32 8003d3e: 2b00 cmp r3, #0 8003d40: d009 beq.n 8003d56 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003d42: 683b ldr r3, [r7, #0] 8003d44: 015a lsls r2, r3, #5 8003d46: 69bb ldr r3, [r7, #24] 8003d48: 4413 add r3, r2 8003d4a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003d4e: 461a mov r2, r3 8003d50: 2320 movs r3, #32 8003d52: 6093 str r3, [r2, #8] 8003d54: e098 b.n 8003e88 } else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) 8003d56: 693b ldr r3, [r7, #16] 8003d58: f003 0328 and.w r3, r3, #40 @ 0x28 8003d5c: 2b00 cmp r3, #0 8003d5e: f040 8093 bne.w 8003e88 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003d62: 697b ldr r3, [r7, #20] 8003d64: 4a4b ldr r2, [pc, #300] @ (8003e94 ) 8003d66: 4293 cmp r3, r2 8003d68: d90f bls.n 8003d8a ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003d6a: 693b ldr r3, [r7, #16] 8003d6c: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003d70: 2b00 cmp r3, #0 8003d72: d00a beq.n 8003d8a { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003d74: 683b ldr r3, [r7, #0] 8003d76: 015a lsls r2, r3, #5 8003d78: 69bb ldr r3, [r7, #24] 8003d7a: 4413 add r3, r2 8003d7c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003d80: 461a mov r2, r3 8003d82: f44f 4300 mov.w r3, #32768 @ 0x8000 8003d86: 6093 str r3, [r2, #8] 8003d88: e07e b.n 8003e88 } else { ep = &hpcd->OUT_ep[epnum]; 8003d8a: 683a ldr r2, [r7, #0] 8003d8c: 4613 mov r3, r2 8003d8e: 00db lsls r3, r3, #3 8003d90: 4413 add r3, r2 8003d92: 009b lsls r3, r3, #2 8003d94: f503 7314 add.w r3, r3, #592 @ 0x250 8003d98: 687a ldr r2, [r7, #4] 8003d9a: 4413 add r3, r2 8003d9c: 3304 adds r3, #4 8003d9e: 60fb str r3, [r7, #12] /* out data packet received over EP */ ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 8003da0: 68fb ldr r3, [r7, #12] 8003da2: 6a1a ldr r2, [r3, #32] 8003da4: 683b ldr r3, [r7, #0] 8003da6: 0159 lsls r1, r3, #5 8003da8: 69bb ldr r3, [r7, #24] 8003daa: 440b add r3, r1 8003dac: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003db0: 691b ldr r3, [r3, #16] 8003db2: f3c3 0312 ubfx r3, r3, #0, #19 8003db6: 1ad2 subs r2, r2, r3 8003db8: 68fb ldr r3, [r7, #12] 8003dba: 615a str r2, [r3, #20] if (epnum == 0U) 8003dbc: 683b ldr r3, [r7, #0] 8003dbe: 2b00 cmp r3, #0 8003dc0: d114 bne.n 8003dec { if (ep->xfer_len == 0U) 8003dc2: 68fb ldr r3, [r7, #12] 8003dc4: 691b ldr r3, [r3, #16] 8003dc6: 2b00 cmp r3, #0 8003dc8: d109 bne.n 8003dde { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003dca: 687b ldr r3, [r7, #4] 8003dcc: 6818 ldr r0, [r3, #0] 8003dce: 687b ldr r3, [r7, #4] 8003dd0: f203 439c addw r3, r3, #1180 @ 0x49c 8003dd4: 461a mov r2, r3 8003dd6: 2101 movs r1, #1 8003dd8: f004 fbfe bl 80085d8 8003ddc: e006 b.n 8003dec } else { ep->xfer_buff += ep->xfer_count; 8003dde: 68fb ldr r3, [r7, #12] 8003de0: 68da ldr r2, [r3, #12] 8003de2: 68fb ldr r3, [r7, #12] 8003de4: 695b ldr r3, [r3, #20] 8003de6: 441a add r2, r3 8003de8: 68fb ldr r3, [r7, #12] 8003dea: 60da str r2, [r3, #12] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003dec: 683b ldr r3, [r7, #0] 8003dee: b2db uxtb r3, r3 8003df0: 4619 mov r1, r3 8003df2: 6878 ldr r0, [r7, #4] 8003df4: f006 fbcc bl 800a590 8003df8: e046 b.n 8003e88 /* ... */ } } else { if (gSNPSiD == USB_OTG_CORE_ID_310A) 8003dfa: 697b ldr r3, [r7, #20] 8003dfc: 4a26 ldr r2, [pc, #152] @ (8003e98 ) 8003dfe: 4293 cmp r3, r2 8003e00: d124 bne.n 8003e4c { /* StupPktRcvd = 1 this is a setup packet */ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) 8003e02: 693b ldr r3, [r7, #16] 8003e04: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003e08: 2b00 cmp r3, #0 8003e0a: d00a beq.n 8003e22 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003e0c: 683b ldr r3, [r7, #0] 8003e0e: 015a lsls r2, r3, #5 8003e10: 69bb ldr r3, [r7, #24] 8003e12: 4413 add r3, r2 8003e14: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003e18: 461a mov r2, r3 8003e1a: f44f 4300 mov.w r3, #32768 @ 0x8000 8003e1e: 6093 str r3, [r2, #8] 8003e20: e032 b.n 8003e88 } else { if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8003e22: 693b ldr r3, [r7, #16] 8003e24: f003 0320 and.w r3, r3, #32 8003e28: 2b00 cmp r3, #0 8003e2a: d008 beq.n 8003e3e { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8003e2c: 683b ldr r3, [r7, #0] 8003e2e: 015a lsls r2, r3, #5 8003e30: 69bb ldr r3, [r7, #24] 8003e32: 4413 add r3, r2 8003e34: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003e38: 461a mov r2, r3 8003e3a: 2320 movs r3, #32 8003e3c: 6093 str r3, [r2, #8] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003e3e: 683b ldr r3, [r7, #0] 8003e40: b2db uxtb r3, r3 8003e42: 4619 mov r1, r3 8003e44: 6878 ldr r0, [r7, #4] 8003e46: f006 fba3 bl 800a590 8003e4a: e01d b.n 8003e88 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else { if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8003e4c: 683b ldr r3, [r7, #0] 8003e4e: 2b00 cmp r3, #0 8003e50: d114 bne.n 8003e7c 8003e52: 6879 ldr r1, [r7, #4] 8003e54: 683a ldr r2, [r7, #0] 8003e56: 4613 mov r3, r2 8003e58: 00db lsls r3, r3, #3 8003e5a: 4413 add r3, r2 8003e5c: 009b lsls r3, r3, #2 8003e5e: 440b add r3, r1 8003e60: f503 7319 add.w r3, r3, #612 @ 0x264 8003e64: 681b ldr r3, [r3, #0] 8003e66: 2b00 cmp r3, #0 8003e68: d108 bne.n 8003e7c { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); 8003e6a: 687b ldr r3, [r7, #4] 8003e6c: 6818 ldr r0, [r3, #0] 8003e6e: 687b ldr r3, [r7, #4] 8003e70: f203 439c addw r3, r3, #1180 @ 0x49c 8003e74: 461a mov r2, r3 8003e76: 2100 movs r1, #0 8003e78: f004 fbae bl 80085d8 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8003e7c: 683b ldr r3, [r7, #0] 8003e7e: b2db uxtb r3, r3 8003e80: 4619 mov r1, r3 8003e82: 6878 ldr r0, [r7, #4] 8003e84: f006 fb84 bl 800a590 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } return HAL_OK; 8003e88: 2300 movs r3, #0 } 8003e8a: 4618 mov r0, r3 8003e8c: 3720 adds r7, #32 8003e8e: 46bd mov sp, r7 8003e90: bd80 pop {r7, pc} 8003e92: bf00 nop 8003e94: 4f54300a .word 0x4f54300a 8003e98: 4f54310a .word 0x4f54310a 08003e9c : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003e9c: b580 push {r7, lr} 8003e9e: b086 sub sp, #24 8003ea0: af00 add r7, sp, #0 8003ea2: 6078 str r0, [r7, #4] 8003ea4: 6039 str r1, [r7, #0] const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003ea6: 687b ldr r3, [r7, #4] 8003ea8: 681b ldr r3, [r3, #0] 8003eaa: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003eac: 697b ldr r3, [r7, #20] 8003eae: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8003eb0: 697b ldr r3, [r7, #20] 8003eb2: 333c adds r3, #60 @ 0x3c 8003eb4: 3304 adds r3, #4 8003eb6: 681b ldr r3, [r3, #0] 8003eb8: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003eba: 683b ldr r3, [r7, #0] 8003ebc: 015a lsls r2, r3, #5 8003ebe: 693b ldr r3, [r7, #16] 8003ec0: 4413 add r3, r2 8003ec2: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003ec6: 689b ldr r3, [r3, #8] 8003ec8: 60bb str r3, [r7, #8] if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003eca: 68fb ldr r3, [r7, #12] 8003ecc: 4a15 ldr r2, [pc, #84] @ (8003f24 ) 8003ece: 4293 cmp r3, r2 8003ed0: d90e bls.n 8003ef0 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8003ed2: 68bb ldr r3, [r7, #8] 8003ed4: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003ed8: 2b00 cmp r3, #0 8003eda: d009 beq.n 8003ef0 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003edc: 683b ldr r3, [r7, #0] 8003ede: 015a lsls r2, r3, #5 8003ee0: 693b ldr r3, [r7, #16] 8003ee2: 4413 add r3, r2 8003ee4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003ee8: 461a mov r2, r3 8003eea: f44f 4300 mov.w r3, #32768 @ 0x8000 8003eee: 6093 str r3, [r2, #8] /* Inform the upper layer that a setup packet is available */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 8003ef0: 6878 ldr r0, [r7, #4] 8003ef2: f006 fb3b bl 800a56c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) 8003ef6: 68fb ldr r3, [r7, #12] 8003ef8: 4a0a ldr r2, [pc, #40] @ (8003f24 ) 8003efa: 4293 cmp r3, r2 8003efc: d90c bls.n 8003f18 8003efe: 687b ldr r3, [r7, #4] 8003f00: 799b ldrb r3, [r3, #6] 8003f02: 2b01 cmp r3, #1 8003f04: d108 bne.n 8003f18 { (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003f06: 687b ldr r3, [r7, #4] 8003f08: 6818 ldr r0, [r3, #0] 8003f0a: 687b ldr r3, [r7, #4] 8003f0c: f203 439c addw r3, r3, #1180 @ 0x49c 8003f10: 461a mov r2, r3 8003f12: 2101 movs r1, #1 8003f14: f004 fb60 bl 80085d8 } return HAL_OK; 8003f18: 2300 movs r3, #0 } 8003f1a: 4618 mov r0, r3 8003f1c: 3718 adds r7, #24 8003f1e: 46bd mov sp, r7 8003f20: bd80 pop {r7, pc} 8003f22: bf00 nop 8003f24: 4f54300a .word 0x4f54300a 08003f28 : * @param fifo The number of Tx fifo * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { 8003f28: b480 push {r7} 8003f2a: b085 sub sp, #20 8003f2c: af00 add r7, sp, #0 8003f2e: 6078 str r0, [r7, #4] 8003f30: 460b mov r3, r1 8003f32: 70fb strb r3, [r7, #3] 8003f34: 4613 mov r3, r2 8003f36: 803b strh r3, [r7, #0] --> Txn should be configured with the minimum space of 16 words The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ Tx_Offset = hpcd->Instance->GRXFSIZ; 8003f38: 687b ldr r3, [r7, #4] 8003f3a: 681b ldr r3, [r3, #0] 8003f3c: 6a5b ldr r3, [r3, #36] @ 0x24 8003f3e: 60bb str r3, [r7, #8] if (fifo == 0U) 8003f40: 78fb ldrb r3, [r7, #3] 8003f42: 2b00 cmp r3, #0 8003f44: d107 bne.n 8003f56 { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; 8003f46: 883b ldrh r3, [r7, #0] 8003f48: 0419 lsls r1, r3, #16 8003f4a: 687b ldr r3, [r7, #4] 8003f4c: 681b ldr r3, [r3, #0] 8003f4e: 68ba ldr r2, [r7, #8] 8003f50: 430a orrs r2, r1 8003f52: 629a str r2, [r3, #40] @ 0x28 8003f54: e028 b.n 8003fa8 } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; 8003f56: 687b ldr r3, [r7, #4] 8003f58: 681b ldr r3, [r3, #0] 8003f5a: 6a9b ldr r3, [r3, #40] @ 0x28 8003f5c: 0c1b lsrs r3, r3, #16 8003f5e: 68ba ldr r2, [r7, #8] 8003f60: 4413 add r3, r2 8003f62: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8003f64: 2300 movs r3, #0 8003f66: 73fb strb r3, [r7, #15] 8003f68: e00d b.n 8003f86 { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); 8003f6a: 687b ldr r3, [r7, #4] 8003f6c: 681a ldr r2, [r3, #0] 8003f6e: 7bfb ldrb r3, [r7, #15] 8003f70: 3340 adds r3, #64 @ 0x40 8003f72: 009b lsls r3, r3, #2 8003f74: 4413 add r3, r2 8003f76: 685b ldr r3, [r3, #4] 8003f78: 0c1b lsrs r3, r3, #16 8003f7a: 68ba ldr r2, [r7, #8] 8003f7c: 4413 add r3, r2 8003f7e: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8003f80: 7bfb ldrb r3, [r7, #15] 8003f82: 3301 adds r3, #1 8003f84: 73fb strb r3, [r7, #15] 8003f86: 7bfa ldrb r2, [r7, #15] 8003f88: 78fb ldrb r3, [r7, #3] 8003f8a: 3b01 subs r3, #1 8003f8c: 429a cmp r2, r3 8003f8e: d3ec bcc.n 8003f6a } /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; 8003f90: 883b ldrh r3, [r7, #0] 8003f92: 0418 lsls r0, r3, #16 8003f94: 687b ldr r3, [r7, #4] 8003f96: 6819 ldr r1, [r3, #0] 8003f98: 78fb ldrb r3, [r7, #3] 8003f9a: 3b01 subs r3, #1 8003f9c: 68ba ldr r2, [r7, #8] 8003f9e: 4302 orrs r2, r0 8003fa0: 3340 adds r3, #64 @ 0x40 8003fa2: 009b lsls r3, r3, #2 8003fa4: 440b add r3, r1 8003fa6: 605a str r2, [r3, #4] } return HAL_OK; 8003fa8: 2300 movs r3, #0 } 8003faa: 4618 mov r0, r3 8003fac: 3714 adds r7, #20 8003fae: 46bd mov sp, r7 8003fb0: f85d 7b04 ldr.w r7, [sp], #4 8003fb4: 4770 bx lr 08003fb6 : * @param hpcd PCD handle * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { 8003fb6: b480 push {r7} 8003fb8: b083 sub sp, #12 8003fba: af00 add r7, sp, #0 8003fbc: 6078 str r0, [r7, #4] 8003fbe: 460b mov r3, r1 8003fc0: 807b strh r3, [r7, #2] hpcd->Instance->GRXFSIZ = size; 8003fc2: 687b ldr r3, [r7, #4] 8003fc4: 681b ldr r3, [r3, #0] 8003fc6: 887a ldrh r2, [r7, #2] 8003fc8: 625a str r2, [r3, #36] @ 0x24 return HAL_OK; 8003fca: 2300 movs r3, #0 } 8003fcc: 4618 mov r0, r3 8003fce: 370c adds r7, #12 8003fd0: 46bd mov sp, r7 8003fd2: f85d 7b04 ldr.w r7, [sp], #4 8003fd6: 4770 bx lr 08003fd8 : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 8003fd8: b480 push {r7} 8003fda: b085 sub sp, #20 8003fdc: af00 add r7, sp, #0 8003fde: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003fe0: 687b ldr r3, [r7, #4] 8003fe2: 681b ldr r3, [r3, #0] 8003fe4: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 8003fe6: 687b ldr r3, [r7, #4] 8003fe8: 2201 movs r2, #1 8003fea: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8 hpcd->LPM_State = LPM_L0; 8003fee: 687b ldr r3, [r7, #4] 8003ff0: 2200 movs r2, #0 8003ff2: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 8003ff6: 68fb ldr r3, [r7, #12] 8003ff8: 699b ldr r3, [r3, #24] 8003ffa: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 8003ffe: 68fb ldr r3, [r7, #12] 8004000: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 8004002: 68fb ldr r3, [r7, #12] 8004004: 6d5b ldr r3, [r3, #84] @ 0x54 8004006: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800400a: f043 0303 orr.w r3, r3, #3 800400e: 68fa ldr r2, [r7, #12] 8004010: 6553 str r3, [r2, #84] @ 0x54 return HAL_OK; 8004012: 2300 movs r3, #0 } 8004014: 4618 mov r0, r3 8004016: 3714 adds r7, #20 8004018: 46bd mov sp, r7 800401a: f85d 7b04 ldr.w r7, [sp], #4 800401e: 4770 bx lr 08004020 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8004020: b580 push {r7, lr} 8004022: b084 sub sp, #16 8004024: af00 add r7, sp, #0 8004026: 6078 str r0, [r7, #4] 8004028: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800402a: 687b ldr r3, [r7, #4] 800402c: 2b00 cmp r3, #0 800402e: d101 bne.n 8004034 { return HAL_ERROR; 8004030: 2301 movs r3, #1 8004032: e0cc b.n 80041ce /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8004034: 4b68 ldr r3, [pc, #416] @ (80041d8 ) 8004036: 681b ldr r3, [r3, #0] 8004038: f003 030f and.w r3, r3, #15 800403c: 683a ldr r2, [r7, #0] 800403e: 429a cmp r2, r3 8004040: d90c bls.n 800405c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004042: 4b65 ldr r3, [pc, #404] @ (80041d8 ) 8004044: 683a ldr r2, [r7, #0] 8004046: b2d2 uxtb r2, r2 8004048: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800404a: 4b63 ldr r3, [pc, #396] @ (80041d8 ) 800404c: 681b ldr r3, [r3, #0] 800404e: f003 030f and.w r3, r3, #15 8004052: 683a ldr r2, [r7, #0] 8004054: 429a cmp r2, r3 8004056: d001 beq.n 800405c { return HAL_ERROR; 8004058: 2301 movs r3, #1 800405a: e0b8 b.n 80041ce } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800405c: 687b ldr r3, [r7, #4] 800405e: 681b ldr r3, [r3, #0] 8004060: f003 0302 and.w r3, r3, #2 8004064: 2b00 cmp r3, #0 8004066: d020 beq.n 80040aa { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004068: 687b ldr r3, [r7, #4] 800406a: 681b ldr r3, [r3, #0] 800406c: f003 0304 and.w r3, r3, #4 8004070: 2b00 cmp r3, #0 8004072: d005 beq.n 8004080 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8004074: 4b59 ldr r3, [pc, #356] @ (80041dc ) 8004076: 689b ldr r3, [r3, #8] 8004078: 4a58 ldr r2, [pc, #352] @ (80041dc ) 800407a: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 800407e: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004080: 687b ldr r3, [r7, #4] 8004082: 681b ldr r3, [r3, #0] 8004084: f003 0308 and.w r3, r3, #8 8004088: 2b00 cmp r3, #0 800408a: d005 beq.n 8004098 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 800408c: 4b53 ldr r3, [pc, #332] @ (80041dc ) 800408e: 689b ldr r3, [r3, #8] 8004090: 4a52 ldr r2, [pc, #328] @ (80041dc ) 8004092: f443 4360 orr.w r3, r3, #57344 @ 0xe000 8004096: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8004098: 4b50 ldr r3, [pc, #320] @ (80041dc ) 800409a: 689b ldr r3, [r3, #8] 800409c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80040a0: 687b ldr r3, [r7, #4] 80040a2: 689b ldr r3, [r3, #8] 80040a4: 494d ldr r1, [pc, #308] @ (80041dc ) 80040a6: 4313 orrs r3, r2 80040a8: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80040aa: 687b ldr r3, [r7, #4] 80040ac: 681b ldr r3, [r3, #0] 80040ae: f003 0301 and.w r3, r3, #1 80040b2: 2b00 cmp r3, #0 80040b4: d044 beq.n 8004140 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80040b6: 687b ldr r3, [r7, #4] 80040b8: 685b ldr r3, [r3, #4] 80040ba: 2b01 cmp r3, #1 80040bc: d107 bne.n 80040ce { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80040be: 4b47 ldr r3, [pc, #284] @ (80041dc ) 80040c0: 681b ldr r3, [r3, #0] 80040c2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80040c6: 2b00 cmp r3, #0 80040c8: d119 bne.n 80040fe { return HAL_ERROR; 80040ca: 2301 movs r3, #1 80040cc: e07f b.n 80041ce } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 80040ce: 687b ldr r3, [r7, #4] 80040d0: 685b ldr r3, [r3, #4] 80040d2: 2b02 cmp r3, #2 80040d4: d003 beq.n 80040de (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 80040d6: 687b ldr r3, [r7, #4] 80040d8: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 80040da: 2b03 cmp r3, #3 80040dc: d107 bne.n 80040ee { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80040de: 4b3f ldr r3, [pc, #252] @ (80041dc ) 80040e0: 681b ldr r3, [r3, #0] 80040e2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80040e6: 2b00 cmp r3, #0 80040e8: d109 bne.n 80040fe { return HAL_ERROR; 80040ea: 2301 movs r3, #1 80040ec: e06f b.n 80041ce } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80040ee: 4b3b ldr r3, [pc, #236] @ (80041dc ) 80040f0: 681b ldr r3, [r3, #0] 80040f2: f003 0302 and.w r3, r3, #2 80040f6: 2b00 cmp r3, #0 80040f8: d101 bne.n 80040fe { return HAL_ERROR; 80040fa: 2301 movs r3, #1 80040fc: e067 b.n 80041ce } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80040fe: 4b37 ldr r3, [pc, #220] @ (80041dc ) 8004100: 689b ldr r3, [r3, #8] 8004102: f023 0203 bic.w r2, r3, #3 8004106: 687b ldr r3, [r7, #4] 8004108: 685b ldr r3, [r3, #4] 800410a: 4934 ldr r1, [pc, #208] @ (80041dc ) 800410c: 4313 orrs r3, r2 800410e: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004110: f7fd fcb2 bl 8001a78 8004114: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004116: e00a b.n 800412e { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8004118: f7fd fcae bl 8001a78 800411c: 4602 mov r2, r0 800411e: 68fb ldr r3, [r7, #12] 8004120: 1ad3 subs r3, r2, r3 8004122: f241 3288 movw r2, #5000 @ 0x1388 8004126: 4293 cmp r3, r2 8004128: d901 bls.n 800412e { return HAL_TIMEOUT; 800412a: 2303 movs r3, #3 800412c: e04f b.n 80041ce while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800412e: 4b2b ldr r3, [pc, #172] @ (80041dc ) 8004130: 689b ldr r3, [r3, #8] 8004132: f003 020c and.w r2, r3, #12 8004136: 687b ldr r3, [r7, #4] 8004138: 685b ldr r3, [r3, #4] 800413a: 009b lsls r3, r3, #2 800413c: 429a cmp r2, r3 800413e: d1eb bne.n 8004118 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8004140: 4b25 ldr r3, [pc, #148] @ (80041d8 ) 8004142: 681b ldr r3, [r3, #0] 8004144: f003 030f and.w r3, r3, #15 8004148: 683a ldr r2, [r7, #0] 800414a: 429a cmp r2, r3 800414c: d20c bcs.n 8004168 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800414e: 4b22 ldr r3, [pc, #136] @ (80041d8 ) 8004150: 683a ldr r2, [r7, #0] 8004152: b2d2 uxtb r2, r2 8004154: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004156: 4b20 ldr r3, [pc, #128] @ (80041d8 ) 8004158: 681b ldr r3, [r3, #0] 800415a: f003 030f and.w r3, r3, #15 800415e: 683a ldr r2, [r7, #0] 8004160: 429a cmp r2, r3 8004162: d001 beq.n 8004168 { return HAL_ERROR; 8004164: 2301 movs r3, #1 8004166: e032 b.n 80041ce } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004168: 687b ldr r3, [r7, #4] 800416a: 681b ldr r3, [r3, #0] 800416c: f003 0304 and.w r3, r3, #4 8004170: 2b00 cmp r3, #0 8004172: d008 beq.n 8004186 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8004174: 4b19 ldr r3, [pc, #100] @ (80041dc ) 8004176: 689b ldr r3, [r3, #8] 8004178: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 800417c: 687b ldr r3, [r7, #4] 800417e: 68db ldr r3, [r3, #12] 8004180: 4916 ldr r1, [pc, #88] @ (80041dc ) 8004182: 4313 orrs r3, r2 8004184: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004186: 687b ldr r3, [r7, #4] 8004188: 681b ldr r3, [r3, #0] 800418a: f003 0308 and.w r3, r3, #8 800418e: 2b00 cmp r3, #0 8004190: d009 beq.n 80041a6 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8004192: 4b12 ldr r3, [pc, #72] @ (80041dc ) 8004194: 689b ldr r3, [r3, #8] 8004196: f423 4260 bic.w r2, r3, #57344 @ 0xe000 800419a: 687b ldr r3, [r7, #4] 800419c: 691b ldr r3, [r3, #16] 800419e: 00db lsls r3, r3, #3 80041a0: 490e ldr r1, [pc, #56] @ (80041dc ) 80041a2: 4313 orrs r3, r2 80041a4: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 80041a6: f000 fb7f bl 80048a8 80041aa: 4602 mov r2, r0 80041ac: 4b0b ldr r3, [pc, #44] @ (80041dc ) 80041ae: 689b ldr r3, [r3, #8] 80041b0: 091b lsrs r3, r3, #4 80041b2: f003 030f and.w r3, r3, #15 80041b6: 490a ldr r1, [pc, #40] @ (80041e0 ) 80041b8: 5ccb ldrb r3, [r1, r3] 80041ba: fa22 f303 lsr.w r3, r2, r3 80041be: 4a09 ldr r2, [pc, #36] @ (80041e4 ) 80041c0: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); 80041c2: 4b09 ldr r3, [pc, #36] @ (80041e8 ) 80041c4: 681b ldr r3, [r3, #0] 80041c6: 4618 mov r0, r3 80041c8: f7fd fc12 bl 80019f0 return HAL_OK; 80041cc: 2300 movs r3, #0 } 80041ce: 4618 mov r0, r3 80041d0: 3710 adds r7, #16 80041d2: 46bd mov sp, r7 80041d4: bd80 pop {r7, pc} 80041d6: bf00 nop 80041d8: 40023c00 .word 0x40023c00 80041dc: 40023800 .word 0x40023800 80041e0: 0800ac2c .word 0x0800ac2c 80041e4: 20000090 .word 0x20000090 80041e8: 20000094 .word 0x20000094 080041ec : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80041ec: b480 push {r7} 80041ee: af00 add r7, sp, #0 return SystemCoreClock; 80041f0: 4b03 ldr r3, [pc, #12] @ (8004200 ) 80041f2: 681b ldr r3, [r3, #0] } 80041f4: 4618 mov r0, r3 80041f6: 46bd mov sp, r7 80041f8: f85d 7b04 ldr.w r7, [sp], #4 80041fc: 4770 bx lr 80041fe: bf00 nop 8004200: 20000090 .word 0x20000090 08004204 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8004204: b580 push {r7, lr} 8004206: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8004208: f7ff fff0 bl 80041ec 800420c: 4602 mov r2, r0 800420e: 4b05 ldr r3, [pc, #20] @ (8004224 ) 8004210: 689b ldr r3, [r3, #8] 8004212: 0a9b lsrs r3, r3, #10 8004214: f003 0307 and.w r3, r3, #7 8004218: 4903 ldr r1, [pc, #12] @ (8004228 ) 800421a: 5ccb ldrb r3, [r1, r3] 800421c: fa22 f303 lsr.w r3, r2, r3 } 8004220: 4618 mov r0, r3 8004222: bd80 pop {r7, pc} 8004224: 40023800 .word 0x40023800 8004228: 0800ac3c .word 0x0800ac3c 0800422c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800422c: b580 push {r7, lr} 800422e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8004230: f7ff ffdc bl 80041ec 8004234: 4602 mov r2, r0 8004236: 4b05 ldr r3, [pc, #20] @ (800424c ) 8004238: 689b ldr r3, [r3, #8] 800423a: 0b5b lsrs r3, r3, #13 800423c: f003 0307 and.w r3, r3, #7 8004240: 4903 ldr r1, [pc, #12] @ (8004250 ) 8004242: 5ccb ldrb r3, [r1, r3] 8004244: fa22 f303 lsr.w r3, r2, r3 } 8004248: 4618 mov r0, r3 800424a: bd80 pop {r7, pc} 800424c: 40023800 .word 0x40023800 8004250: 0800ac3c .word 0x0800ac3c 08004254 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8004254: b580 push {r7, lr} 8004256: b08c sub sp, #48 @ 0x30 8004258: af00 add r7, sp, #0 800425a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800425c: 2300 movs r3, #0 800425e: 627b str r3, [r7, #36] @ 0x24 uint32_t tmpreg1 = 0U; 8004260: 2300 movs r3, #0 8004262: 623b str r3, [r7, #32] uint32_t plli2sp = 0U; 8004264: 2300 movs r3, #0 8004266: 61fb str r3, [r7, #28] uint32_t plli2sq = 0U; 8004268: 2300 movs r3, #0 800426a: 61bb str r3, [r7, #24] uint32_t plli2sr = 0U; 800426c: 2300 movs r3, #0 800426e: 617b str r3, [r7, #20] uint32_t pllsaip = 0U; 8004270: 2300 movs r3, #0 8004272: 613b str r3, [r7, #16] uint32_t pllsaiq = 0U; 8004274: 2300 movs r3, #0 8004276: 60fb str r3, [r7, #12] uint32_t plli2sused = 0U; 8004278: 2300 movs r3, #0 800427a: 62fb str r3, [r7, #44] @ 0x2c uint32_t pllsaiused = 0U; 800427c: 2300 movs r3, #0 800427e: 62bb str r3, [r7, #40] @ 0x28 /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------ I2S APB1 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) 8004280: 687b ldr r3, [r7, #4] 8004282: 681b ldr r3, [r3, #0] 8004284: f003 0301 and.w r3, r3, #1 8004288: 2b00 cmp r3, #0 800428a: d010 beq.n 80042ae { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); 800428c: 4b6f ldr r3, [pc, #444] @ (800444c ) 800428e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004292: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000 8004296: 687b ldr r3, [r7, #4] 8004298: 6b9b ldr r3, [r3, #56] @ 0x38 800429a: 496c ldr r1, [pc, #432] @ (800444c ) 800429c: 4313 orrs r3, r2 800429e: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) 80042a2: 687b ldr r3, [r7, #4] 80042a4: 6b9b ldr r3, [r3, #56] @ 0x38 80042a6: 2b00 cmp r3, #0 80042a8: d101 bne.n 80042ae { plli2sused = 1U; 80042aa: 2301 movs r3, #1 80042ac: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*---------------------------- I2S APB2 configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) 80042ae: 687b ldr r3, [r7, #4] 80042b0: 681b ldr r3, [r3, #0] 80042b2: f003 0302 and.w r3, r3, #2 80042b6: 2b00 cmp r3, #0 80042b8: d010 beq.n 80042dc { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); 80042ba: 4b64 ldr r3, [pc, #400] @ (800444c ) 80042bc: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80042c0: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000 80042c4: 687b ldr r3, [r7, #4] 80042c6: 6bdb ldr r3, [r3, #60] @ 0x3c 80042c8: 4960 ldr r1, [pc, #384] @ (800444c ) 80042ca: 4313 orrs r3, r2 80042cc: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) 80042d0: 687b ldr r3, [r7, #4] 80042d2: 6bdb ldr r3, [r3, #60] @ 0x3c 80042d4: 2b00 cmp r3, #0 80042d6: d101 bne.n 80042dc { plli2sused = 1U; 80042d8: 2301 movs r3, #1 80042da: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*--------------------------- SAI1 configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) 80042dc: 687b ldr r3, [r7, #4] 80042de: 681b ldr r3, [r3, #0] 80042e0: f003 0304 and.w r3, r3, #4 80042e4: 2b00 cmp r3, #0 80042e6: d017 beq.n 8004318 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 80042e8: 4b58 ldr r3, [pc, #352] @ (800444c ) 80042ea: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80042ee: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 80042f2: 687b ldr r3, [r7, #4] 80042f4: 6b1b ldr r3, [r3, #48] @ 0x30 80042f6: 4955 ldr r1, [pc, #340] @ (800444c ) 80042f8: 4313 orrs r3, r2 80042fa: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) 80042fe: 687b ldr r3, [r7, #4] 8004300: 6b1b ldr r3, [r3, #48] @ 0x30 8004302: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8004306: d101 bne.n 800430c { plli2sused = 1U; 8004308: 2301 movs r3, #1 800430a: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) 800430c: 687b ldr r3, [r7, #4] 800430e: 6b1b ldr r3, [r3, #48] @ 0x30 8004310: 2b00 cmp r3, #0 8004312: d101 bne.n 8004318 { pllsaiused = 1U; 8004314: 2301 movs r3, #1 8004316: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*-------------------------- SAI2 configuration ----------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) 8004318: 687b ldr r3, [r7, #4] 800431a: 681b ldr r3, [r3, #0] 800431c: f003 0308 and.w r3, r3, #8 8004320: 2b00 cmp r3, #0 8004322: d017 beq.n 8004354 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 8004324: 4b49 ldr r3, [pc, #292] @ (800444c ) 8004326: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800432a: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 800432e: 687b ldr r3, [r7, #4] 8004330: 6b5b ldr r3, [r3, #52] @ 0x34 8004332: 4946 ldr r1, [pc, #280] @ (800444c ) 8004334: 4313 orrs r3, r2 8004336: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) 800433a: 687b ldr r3, [r7, #4] 800433c: 6b5b ldr r3, [r3, #52] @ 0x34 800433e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004342: d101 bne.n 8004348 { plli2sused = 1U; 8004344: 2301 movs r3, #1 8004346: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) 8004348: 687b ldr r3, [r7, #4] 800434a: 6b5b ldr r3, [r3, #52] @ 0x34 800434c: 2b00 cmp r3, #0 800434e: d101 bne.n 8004354 { pllsaiused = 1U; 8004350: 2301 movs r3, #1 8004352: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- RTC configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 8004354: 687b ldr r3, [r7, #4] 8004356: 681b ldr r3, [r3, #0] 8004358: f003 0320 and.w r3, r3, #32 800435c: 2b00 cmp r3, #0 800435e: f000 808a beq.w 8004476 { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 8004362: 2300 movs r3, #0 8004364: 60bb str r3, [r7, #8] 8004366: 4b39 ldr r3, [pc, #228] @ (800444c ) 8004368: 6c1b ldr r3, [r3, #64] @ 0x40 800436a: 4a38 ldr r2, [pc, #224] @ (800444c ) 800436c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004370: 6413 str r3, [r2, #64] @ 0x40 8004372: 4b36 ldr r3, [pc, #216] @ (800444c ) 8004374: 6c1b ldr r3, [r3, #64] @ 0x40 8004376: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800437a: 60bb str r3, [r7, #8] 800437c: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; 800437e: 4b34 ldr r3, [pc, #208] @ (8004450 ) 8004380: 681b ldr r3, [r3, #0] 8004382: 4a33 ldr r2, [pc, #204] @ (8004450 ) 8004384: f443 7380 orr.w r3, r3, #256 @ 0x100 8004388: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 800438a: f7fd fb75 bl 8001a78 800438e: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR & PWR_CR_DBP) == RESET) 8004390: e008 b.n 80043a4 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004392: f7fd fb71 bl 8001a78 8004396: 4602 mov r2, r0 8004398: 6a7b ldr r3, [r7, #36] @ 0x24 800439a: 1ad3 subs r3, r2, r3 800439c: 2b02 cmp r3, #2 800439e: d901 bls.n 80043a4 { return HAL_TIMEOUT; 80043a0: 2303 movs r3, #3 80043a2: e278 b.n 8004896 while ((PWR->CR & PWR_CR_DBP) == RESET) 80043a4: 4b2a ldr r3, [pc, #168] @ (8004450 ) 80043a6: 681b ldr r3, [r3, #0] 80043a8: f403 7380 and.w r3, r3, #256 @ 0x100 80043ac: 2b00 cmp r3, #0 80043ae: d0f0 beq.n 8004392 } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); 80043b0: 4b26 ldr r3, [pc, #152] @ (800444c ) 80043b2: 6f1b ldr r3, [r3, #112] @ 0x70 80043b4: f403 7340 and.w r3, r3, #768 @ 0x300 80043b8: 623b str r3, [r7, #32] if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 80043ba: 6a3b ldr r3, [r7, #32] 80043bc: 2b00 cmp r3, #0 80043be: d02f beq.n 8004420 80043c0: 687b ldr r3, [r7, #4] 80043c2: 6c1b ldr r3, [r3, #64] @ 0x40 80043c4: f403 7340 and.w r3, r3, #768 @ 0x300 80043c8: 6a3a ldr r2, [r7, #32] 80043ca: 429a cmp r2, r3 80043cc: d028 beq.n 8004420 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80043ce: 4b1f ldr r3, [pc, #124] @ (800444c ) 80043d0: 6f1b ldr r3, [r3, #112] @ 0x70 80043d2: f423 7340 bic.w r3, r3, #768 @ 0x300 80043d6: 623b str r3, [r7, #32] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80043d8: 4b1e ldr r3, [pc, #120] @ (8004454 ) 80043da: 2201 movs r2, #1 80043dc: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 80043de: 4b1d ldr r3, [pc, #116] @ (8004454 ) 80043e0: 2200 movs r2, #0 80043e2: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; 80043e4: 4a19 ldr r2, [pc, #100] @ (800444c ) 80043e6: 6a3b ldr r3, [r7, #32] 80043e8: 6713 str r3, [r2, #112] @ 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 80043ea: 4b18 ldr r3, [pc, #96] @ (800444c ) 80043ec: 6f1b ldr r3, [r3, #112] @ 0x70 80043ee: f003 0301 and.w r3, r3, #1 80043f2: 2b01 cmp r3, #1 80043f4: d114 bne.n 8004420 { /* Get tick */ tickstart = HAL_GetTick(); 80043f6: f7fd fb3f bl 8001a78 80043fa: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80043fc: e00a b.n 8004414 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80043fe: f7fd fb3b bl 8001a78 8004402: 4602 mov r2, r0 8004404: 6a7b ldr r3, [r7, #36] @ 0x24 8004406: 1ad3 subs r3, r2, r3 8004408: f241 3288 movw r2, #5000 @ 0x1388 800440c: 4293 cmp r3, r2 800440e: d901 bls.n 8004414 { return HAL_TIMEOUT; 8004410: 2303 movs r3, #3 8004412: e240 b.n 8004896 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004414: 4b0d ldr r3, [pc, #52] @ (800444c ) 8004416: 6f1b ldr r3, [r3, #112] @ 0x70 8004418: f003 0302 and.w r3, r3, #2 800441c: 2b00 cmp r3, #0 800441e: d0ee beq.n 80043fe } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8004420: 687b ldr r3, [r7, #4] 8004422: 6c1b ldr r3, [r3, #64] @ 0x40 8004424: f403 7340 and.w r3, r3, #768 @ 0x300 8004428: f5b3 7f40 cmp.w r3, #768 @ 0x300 800442c: d114 bne.n 8004458 800442e: 4b07 ldr r3, [pc, #28] @ (800444c ) 8004430: 689b ldr r3, [r3, #8] 8004432: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000 8004436: 687b ldr r3, [r7, #4] 8004438: 6c1b ldr r3, [r3, #64] @ 0x40 800443a: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 800443e: f423 7340 bic.w r3, r3, #768 @ 0x300 8004442: 4902 ldr r1, [pc, #8] @ (800444c ) 8004444: 4313 orrs r3, r2 8004446: 608b str r3, [r1, #8] 8004448: e00c b.n 8004464 800444a: bf00 nop 800444c: 40023800 .word 0x40023800 8004450: 40007000 .word 0x40007000 8004454: 42470e40 .word 0x42470e40 8004458: 4b4a ldr r3, [pc, #296] @ (8004584 ) 800445a: 689b ldr r3, [r3, #8] 800445c: 4a49 ldr r2, [pc, #292] @ (8004584 ) 800445e: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000 8004462: 6093 str r3, [r2, #8] 8004464: 4b47 ldr r3, [pc, #284] @ (8004584 ) 8004466: 6f1a ldr r2, [r3, #112] @ 0x70 8004468: 687b ldr r3, [r7, #4] 800446a: 6c1b ldr r3, [r3, #64] @ 0x40 800446c: f3c3 030b ubfx r3, r3, #0, #12 8004470: 4944 ldr r1, [pc, #272] @ (8004584 ) 8004472: 4313 orrs r3, r2 8004474: 670b str r3, [r1, #112] @ 0x70 } /*--------------------------------------------------------------------------*/ /*---------------------------- TIM configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 8004476: 687b ldr r3, [r7, #4] 8004478: 681b ldr r3, [r3, #0] 800447a: f003 0310 and.w r3, r3, #16 800447e: 2b00 cmp r3, #0 8004480: d004 beq.n 800448c { /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8004482: 687b ldr r3, [r7, #4] 8004484: f893 2058 ldrb.w r2, [r3, #88] @ 0x58 8004488: 4b3f ldr r3, [pc, #252] @ (8004588 ) 800448a: 601a str r2, [r3, #0] } /*--------------------------------------------------------------------------*/ /*---------------------------- FMPI2C1 Configuration -----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) 800448c: 687b ldr r3, [r7, #4] 800448e: 681b ldr r3, [r3, #0] 8004490: f003 0380 and.w r3, r3, #128 @ 0x80 8004494: 2b00 cmp r3, #0 8004496: d00a beq.n 80044ae { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); 8004498: 4b3a ldr r3, [pc, #232] @ (8004584 ) 800449a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800449e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 80044a2: 687b ldr r3, [r7, #4] 80044a4: 6cdb ldr r3, [r3, #76] @ 0x4c 80044a6: 4937 ldr r1, [pc, #220] @ (8004584 ) 80044a8: 4313 orrs r3, r2 80044aa: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ CEC Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 80044ae: 687b ldr r3, [r7, #4] 80044b0: 681b ldr r3, [r3, #0] 80044b2: f003 0340 and.w r3, r3, #64 @ 0x40 80044b6: 2b00 cmp r3, #0 80044b8: d00a beq.n 80044d0 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 80044ba: 4b32 ldr r3, [pc, #200] @ (8004584 ) 80044bc: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80044c0: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000 80044c4: 687b ldr r3, [r7, #4] 80044c6: 6c9b ldr r3, [r3, #72] @ 0x48 80044c8: 492e ldr r1, [pc, #184] @ (8004584 ) 80044ca: 4313 orrs r3, r2 80044cc: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*----------------------------- CLK48 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 80044d0: 687b ldr r3, [r7, #4] 80044d2: 681b ldr r3, [r3, #0] 80044d4: f403 7380 and.w r3, r3, #256 @ 0x100 80044d8: 2b00 cmp r3, #0 80044da: d011 beq.n 8004500 { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); 80044dc: 4b29 ldr r3, [pc, #164] @ (8004584 ) 80044de: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80044e2: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000 80044e6: 687b ldr r3, [r7, #4] 80044e8: 6d5b ldr r3, [r3, #84] @ 0x54 80044ea: 4926 ldr r1, [pc, #152] @ (8004584 ) 80044ec: 4313 orrs r3, r2 80044ee: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLSAI when it's used as clock source for CLK48 */ if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) 80044f2: 687b ldr r3, [r7, #4] 80044f4: 6d5b ldr r3, [r3, #84] @ 0x54 80044f6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80044fa: d101 bne.n 8004500 { pllsaiused = 1U; 80044fc: 2301 movs r3, #1 80044fe: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- SDIO Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) 8004500: 687b ldr r3, [r7, #4] 8004502: 681b ldr r3, [r3, #0] 8004504: f403 7300 and.w r3, r3, #512 @ 0x200 8004508: 2b00 cmp r3, #0 800450a: d00a beq.n 8004522 { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); 800450c: 4b1d ldr r3, [pc, #116] @ (8004584 ) 800450e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004512: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000 8004516: 687b ldr r3, [r7, #4] 8004518: 6c5b ldr r3, [r3, #68] @ 0x44 800451a: 491a ldr r1, [pc, #104] @ (8004584 ) 800451c: 4313 orrs r3, r2 800451e: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ SPDIFRX Configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8004522: 687b ldr r3, [r7, #4] 8004524: 681b ldr r3, [r3, #0] 8004526: f403 6380 and.w r3, r3, #1024 @ 0x400 800452a: 2b00 cmp r3, #0 800452c: d011 beq.n 8004552 { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); /* Configure the SPDIFRX clock source */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); 800452e: 4b15 ldr r3, [pc, #84] @ (8004584 ) 8004530: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004534: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000 8004538: 687b ldr r3, [r7, #4] 800453a: 6d1b ldr r3, [r3, #80] @ 0x50 800453c: 4911 ldr r1, [pc, #68] @ (8004584 ) 800453e: 4313 orrs r3, r2 8004540: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) 8004544: 687b ldr r3, [r7, #4] 8004546: 6d1b ldr r3, [r3, #80] @ 0x50 8004548: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800454c: d101 bne.n 8004552 { plli2sused = 1U; 800454e: 2301 movs r3, #1 8004550: 62fb str r3, [r7, #44] @ 0x2c /*--------------------------------------------------------------------------*/ /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) 8004552: 6afb ldr r3, [r7, #44] @ 0x2c 8004554: 2b01 cmp r3, #1 8004556: d005 beq.n 8004564 8004558: 687b ldr r3, [r7, #4] 800455a: 681b ldr r3, [r3, #0] 800455c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8004560: f040 80ff bne.w 8004762 { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 8004564: 4b09 ldr r3, [pc, #36] @ (800458c ) 8004566: 2200 movs r2, #0 8004568: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800456a: f7fd fa85 bl 8001a78 800456e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004570: e00e b.n 8004590 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004572: f7fd fa81 bl 8001a78 8004576: 4602 mov r2, r0 8004578: 6a7b ldr r3, [r7, #36] @ 0x24 800457a: 1ad3 subs r3, r2, r3 800457c: 2b02 cmp r3, #2 800457e: d907 bls.n 8004590 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004580: 2303 movs r3, #3 8004582: e188 b.n 8004896 8004584: 40023800 .word 0x40023800 8004588: 424711e0 .word 0x424711e0 800458c: 42470068 .word 0x42470068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004590: 4b7e ldr r3, [pc, #504] @ (800478c ) 8004592: 681b ldr r3, [r3, #0] 8004594: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004598: 2b00 cmp r3, #0 800459a: d1ea bne.n 8004572 /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) 800459c: 687b ldr r3, [r7, #4] 800459e: 681b ldr r3, [r3, #0] 80045a0: f003 0301 and.w r3, r3, #1 80045a4: 2b00 cmp r3, #0 80045a6: d003 beq.n 80045b0 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 80045a8: 687b ldr r3, [r7, #4] 80045aa: 6b9b ldr r3, [r3, #56] @ 0x38 80045ac: 2b00 cmp r3, #0 80045ae: d009 beq.n 80045c4 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 80045b0: 687b ldr r3, [r7, #4] 80045b2: 681b ldr r3, [r3, #0] 80045b4: f003 0302 and.w r3, r3, #2 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 80045b8: 2b00 cmp r3, #0 80045ba: d028 beq.n 800460e ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 80045bc: 687b ldr r3, [r7, #4] 80045be: 6bdb ldr r3, [r3, #60] @ 0x3c 80045c0: 2b00 cmp r3, #0 80045c2: d124 bne.n 800460e { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 80045c4: 4b71 ldr r3, [pc, #452] @ (800478c ) 80045c6: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80045ca: 0c1b lsrs r3, r3, #16 80045cc: f003 0303 and.w r3, r3, #3 80045d0: 3301 adds r3, #1 80045d2: 005b lsls r3, r3, #1 80045d4: 61fb str r3, [r7, #28] plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); 80045d6: 4b6d ldr r3, [pc, #436] @ (800478c ) 80045d8: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80045dc: 0e1b lsrs r3, r3, #24 80045de: f003 030f and.w r3, r3, #15 80045e2: 61bb str r3, [r7, #24] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq, 80045e4: 687b ldr r3, [r7, #4] 80045e6: 685a ldr r2, [r3, #4] 80045e8: 687b ldr r3, [r7, #4] 80045ea: 689b ldr r3, [r3, #8] 80045ec: 019b lsls r3, r3, #6 80045ee: 431a orrs r2, r3 80045f0: 69fb ldr r3, [r7, #28] 80045f2: 085b lsrs r3, r3, #1 80045f4: 3b01 subs r3, #1 80045f6: 041b lsls r3, r3, #16 80045f8: 431a orrs r2, r3 80045fa: 69bb ldr r3, [r7, #24] 80045fc: 061b lsls r3, r3, #24 80045fe: 431a orrs r2, r3 8004600: 687b ldr r3, [r7, #4] 8004602: 695b ldr r3, [r3, #20] 8004604: 071b lsls r3, r3, #28 8004606: 4961 ldr r1, [pc, #388] @ (800478c ) 8004608: 4313 orrs r3, r2 800460a: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SR); } /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800460e: 687b ldr r3, [r7, #4] 8004610: 681b ldr r3, [r3, #0] 8004612: f003 0304 and.w r3, r3, #4 8004616: 2b00 cmp r3, #0 8004618: d004 beq.n 8004624 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 800461a: 687b ldr r3, [r7, #4] 800461c: 6b1b ldr r3, [r3, #48] @ 0x30 800461e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8004622: d00a beq.n 800463a ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8004624: 687b ldr r3, [r7, #4] 8004626: 681b ldr r3, [r3, #0] 8004628: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 800462c: 2b00 cmp r3, #0 800462e: d035 beq.n 800469c ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8004630: 687b ldr r3, [r7, #4] 8004632: 6b5b ldr r3, [r3, #52] @ 0x34 8004634: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004638: d130 bne.n 800469c assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 800463a: 4b54 ldr r3, [pc, #336] @ (800478c ) 800463c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004640: 0c1b lsrs r3, r3, #16 8004642: f003 0303 and.w r3, r3, #3 8004646: 3301 adds r3, #1 8004648: 005b lsls r3, r3, #1 800464a: 61fb str r3, [r7, #28] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 800464c: 4b4f ldr r3, [pc, #316] @ (800478c ) 800464e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004652: 0f1b lsrs r3, r3, #28 8004654: f003 0307 and.w r3, r3, #7 8004658: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, 800465a: 687b ldr r3, [r7, #4] 800465c: 685a ldr r2, [r3, #4] 800465e: 687b ldr r3, [r7, #4] 8004660: 689b ldr r3, [r3, #8] 8004662: 019b lsls r3, r3, #6 8004664: 431a orrs r2, r3 8004666: 69fb ldr r3, [r7, #28] 8004668: 085b lsrs r3, r3, #1 800466a: 3b01 subs r3, #1 800466c: 041b lsls r3, r3, #16 800466e: 431a orrs r2, r3 8004670: 687b ldr r3, [r7, #4] 8004672: 691b ldr r3, [r3, #16] 8004674: 061b lsls r3, r3, #24 8004676: 431a orrs r2, r3 8004678: 697b ldr r3, [r7, #20] 800467a: 071b lsls r3, r3, #28 800467c: 4943 ldr r1, [pc, #268] @ (800478c ) 800467e: 4313 orrs r3, r2 8004680: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 8004684: 4b41 ldr r3, [pc, #260] @ (800478c ) 8004686: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800468a: f023 021f bic.w r2, r3, #31 800468e: 687b ldr r3, [r7, #4] 8004690: 6a9b ldr r3, [r3, #40] @ 0x28 8004692: 3b01 subs r3, #1 8004694: 493d ldr r1, [pc, #244] @ (800478c ) 8004696: 4313 orrs r3, r2 8004698: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 800469c: 687b ldr r3, [r7, #4] 800469e: 681b ldr r3, [r3, #0] 80046a0: f403 6380 and.w r3, r3, #1024 @ 0x400 80046a4: 2b00 cmp r3, #0 80046a6: d029 beq.n 80046fc && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 80046a8: 687b ldr r3, [r7, #4] 80046aa: 6d1b ldr r3, [r3, #80] @ 0x50 80046ac: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80046b0: d124 bne.n 80046fc { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 80046b2: 4b36 ldr r3, [pc, #216] @ (800478c ) 80046b4: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80046b8: 0c1b lsrs r3, r3, #16 80046ba: f003 0303 and.w r3, r3, #3 80046be: 3301 adds r3, #1 80046c0: 005b lsls r3, r3, #1 80046c2: 61bb str r3, [r7, #24] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 80046c4: 4b31 ldr r3, [pc, #196] @ (800478c ) 80046c6: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80046ca: 0f1b lsrs r3, r3, #28 80046cc: f003 0307 and.w r3, r3, #7 80046d0: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 80046d2: 687b ldr r3, [r7, #4] 80046d4: 685a ldr r2, [r3, #4] 80046d6: 687b ldr r3, [r7, #4] 80046d8: 689b ldr r3, [r3, #8] 80046da: 019b lsls r3, r3, #6 80046dc: 431a orrs r2, r3 80046de: 687b ldr r3, [r7, #4] 80046e0: 68db ldr r3, [r3, #12] 80046e2: 085b lsrs r3, r3, #1 80046e4: 3b01 subs r3, #1 80046e6: 041b lsls r3, r3, #16 80046e8: 431a orrs r2, r3 80046ea: 69bb ldr r3, [r7, #24] 80046ec: 061b lsls r3, r3, #24 80046ee: 431a orrs r2, r3 80046f0: 697b ldr r3, [r7, #20] 80046f2: 071b lsls r3, r3, #28 80046f4: 4925 ldr r1, [pc, #148] @ (800478c ) 80046f6: 4313 orrs r3, r2 80046f8: f8c1 3084 str.w r3, [r1, #132] @ 0x84 plli2sq, plli2sr); } /*----------------- In Case of PLLI2S is just selected -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 80046fc: 687b ldr r3, [r7, #4] 80046fe: 681b ldr r3, [r3, #0] 8004700: f403 6300 and.w r3, r3, #2048 @ 0x800 8004704: 2b00 cmp r3, #0 8004706: d016 beq.n 8004736 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 8004708: 687b ldr r3, [r7, #4] 800470a: 685a ldr r2, [r3, #4] 800470c: 687b ldr r3, [r7, #4] 800470e: 689b ldr r3, [r3, #8] 8004710: 019b lsls r3, r3, #6 8004712: 431a orrs r2, r3 8004714: 687b ldr r3, [r7, #4] 8004716: 68db ldr r3, [r3, #12] 8004718: 085b lsrs r3, r3, #1 800471a: 3b01 subs r3, #1 800471c: 041b lsls r3, r3, #16 800471e: 431a orrs r2, r3 8004720: 687b ldr r3, [r7, #4] 8004722: 691b ldr r3, [r3, #16] 8004724: 061b lsls r3, r3, #24 8004726: 431a orrs r2, r3 8004728: 687b ldr r3, [r7, #4] 800472a: 695b ldr r3, [r3, #20] 800472c: 071b lsls r3, r3, #28 800472e: 4917 ldr r1, [pc, #92] @ (800478c ) 8004730: 4313 orrs r3, r2 8004732: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 8004736: 4b16 ldr r3, [pc, #88] @ (8004790 ) 8004738: 2201 movs r2, #1 800473a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800473c: f7fd f99c bl 8001a78 8004740: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004742: e008 b.n 8004756 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004744: f7fd f998 bl 8001a78 8004748: 4602 mov r2, r0 800474a: 6a7b ldr r3, [r7, #36] @ 0x24 800474c: 1ad3 subs r3, r2, r3 800474e: 2b02 cmp r3, #2 8004750: d901 bls.n 8004756 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004752: 2303 movs r3, #3 8004754: e09f b.n 8004896 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004756: 4b0d ldr r3, [pc, #52] @ (800478c ) 8004758: 681b ldr r3, [r3, #0] 800475a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800475e: 2b00 cmp r3, #0 8004760: d0f0 beq.n 8004744 } /*--------------------------------------------------------------------------*/ /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ if (pllsaiused == 1U) 8004762: 6abb ldr r3, [r7, #40] @ 0x28 8004764: 2b01 cmp r3, #1 8004766: f040 8095 bne.w 8004894 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 800476a: 4b0a ldr r3, [pc, #40] @ (8004794 ) 800476c: 2200 movs r2, #0 800476e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004770: f7fd f982 bl 8001a78 8004774: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is disabled */ while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004776: e00f b.n 8004798 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004778: f7fd f97e bl 8001a78 800477c: 4602 mov r2, r0 800477e: 6a7b ldr r3, [r7, #36] @ 0x24 8004780: 1ad3 subs r3, r2, r3 8004782: 2b02 cmp r3, #2 8004784: d908 bls.n 8004798 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004786: 2303 movs r3, #3 8004788: e085 b.n 8004896 800478a: bf00 nop 800478c: 40023800 .word 0x40023800 8004790: 42470068 .word 0x42470068 8004794: 42470070 .word 0x42470070 while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004798: 4b41 ldr r3, [pc, #260] @ (80048a0 ) 800479a: 681b ldr r3, [r3, #0] 800479c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80047a0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80047a4: d0e8 beq.n 8004778 /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 80047a6: 687b ldr r3, [r7, #4] 80047a8: 681b ldr r3, [r3, #0] 80047aa: f003 0304 and.w r3, r3, #4 80047ae: 2b00 cmp r3, #0 80047b0: d003 beq.n 80047ba && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 80047b2: 687b ldr r3, [r7, #4] 80047b4: 6b1b ldr r3, [r3, #48] @ 0x30 80047b6: 2b00 cmp r3, #0 80047b8: d009 beq.n 80047ce ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 80047ba: 687b ldr r3, [r7, #4] 80047bc: 681b ldr r3, [r3, #0] 80047be: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 80047c2: 2b00 cmp r3, #0 80047c4: d02b beq.n 800481e ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 80047c6: 687b ldr r3, [r7, #4] 80047c8: 6b5b ldr r3, [r3, #52] @ 0x34 80047ca: 2b00 cmp r3, #0 80047cc: d127 bne.n 800481e assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); 80047ce: 4b34 ldr r3, [pc, #208] @ (80048a0 ) 80047d0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80047d4: 0c1b lsrs r3, r3, #16 80047d6: f003 0303 and.w r3, r3, #3 80047da: 3301 adds r3, #1 80047dc: 005b lsls r3, r3, #1 80047de: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, 80047e0: 687b ldr r3, [r7, #4] 80047e2: 699a ldr r2, [r3, #24] 80047e4: 687b ldr r3, [r7, #4] 80047e6: 69db ldr r3, [r3, #28] 80047e8: 019b lsls r3, r3, #6 80047ea: 431a orrs r2, r3 80047ec: 693b ldr r3, [r7, #16] 80047ee: 085b lsrs r3, r3, #1 80047f0: 3b01 subs r3, #1 80047f2: 041b lsls r3, r3, #16 80047f4: 431a orrs r2, r3 80047f6: 687b ldr r3, [r7, #4] 80047f8: 6a5b ldr r3, [r3, #36] @ 0x24 80047fa: 061b lsls r3, r3, #24 80047fc: 4928 ldr r1, [pc, #160] @ (80048a0 ) 80047fe: 4313 orrs r3, r2 8004800: f8c1 3088 str.w r3, [r1, #136] @ 0x88 PeriphClkInit->PLLSAI.PLLSAIQ, 0U); /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 8004804: 4b26 ldr r3, [pc, #152] @ (80048a0 ) 8004806: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800480a: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 800480e: 687b ldr r3, [r7, #4] 8004810: 6adb ldr r3, [r3, #44] @ 0x2c 8004812: 3b01 subs r3, #1 8004814: 021b lsls r3, r3, #8 8004816: 4922 ldr r1, [pc, #136] @ (80048a0 ) 8004818: 4313 orrs r3, r2 800481a: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ /* In Case of PLLI2S is selected as source clock for CLK48 */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 800481e: 687b ldr r3, [r7, #4] 8004820: 681b ldr r3, [r3, #0] 8004822: f403 7380 and.w r3, r3, #256 @ 0x100 8004826: 2b00 cmp r3, #0 8004828: d01d beq.n 8004866 && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) 800482a: 687b ldr r3, [r7, #4] 800482c: 6d5b ldr r3, [r3, #84] @ 0x54 800482e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8004832: d118 bne.n 8004866 { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 8004834: 4b1a ldr r3, [pc, #104] @ (80048a0 ) 8004836: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800483a: 0e1b lsrs r3, r3, #24 800483c: f003 030f and.w r3, r3, #15 8004840: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, 8004842: 687b ldr r3, [r7, #4] 8004844: 699a ldr r2, [r3, #24] 8004846: 687b ldr r3, [r7, #4] 8004848: 69db ldr r3, [r3, #28] 800484a: 019b lsls r3, r3, #6 800484c: 431a orrs r2, r3 800484e: 687b ldr r3, [r7, #4] 8004850: 6a1b ldr r3, [r3, #32] 8004852: 085b lsrs r3, r3, #1 8004854: 3b01 subs r3, #1 8004856: 041b lsls r3, r3, #16 8004858: 431a orrs r2, r3 800485a: 68fb ldr r3, [r7, #12] 800485c: 061b lsls r3, r3, #24 800485e: 4910 ldr r1, [pc, #64] @ (80048a0 ) 8004860: 4313 orrs r3, r2 8004862: f8c1 3088 str.w r3, [r1, #136] @ 0x88 pllsaiq, 0U); } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 8004866: 4b0f ldr r3, [pc, #60] @ (80048a4 ) 8004868: 2201 movs r2, #1 800486a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800486c: f7fd f904 bl 8001a78 8004870: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is ready */ while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004872: e008 b.n 8004886 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004874: f7fd f900 bl 8001a78 8004878: 4602 mov r2, r0 800487a: 6a7b ldr r3, [r7, #36] @ 0x24 800487c: 1ad3 subs r3, r2, r3 800487e: 2b02 cmp r3, #2 8004880: d901 bls.n 8004886 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004882: 2303 movs r3, #3 8004884: e007 b.n 8004896 while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004886: 4b06 ldr r3, [pc, #24] @ (80048a0 ) 8004888: 681b ldr r3, [r3, #0] 800488a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800488e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004892: d1ef bne.n 8004874 } } } return HAL_OK; 8004894: 2300 movs r3, #0 } 8004896: 4618 mov r0, r3 8004898: 3730 adds r7, #48 @ 0x30 800489a: 46bd mov sp, r7 800489c: bd80 pop {r7, pc} 800489e: bf00 nop 80048a0: 40023800 .word 0x40023800 80048a4: 42470070 .word 0x42470070 080048a8 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80048a8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 80048ac: b0ae sub sp, #184 @ 0xb8 80048ae: af00 add r7, sp, #0 uint32_t pllm = 0U; 80048b0: 2300 movs r3, #0 80048b2: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t pllvco = 0U; 80048b6: 2300 movs r3, #0 80048b8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t pllp = 0U; 80048bc: 2300 movs r3, #0 80048be: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 uint32_t pllr = 0U; 80048c2: 2300 movs r3, #0 80048c4: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t sysclockfreq = 0U; 80048c8: 2300 movs r3, #0 80048ca: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 80048ce: 4bcb ldr r3, [pc, #812] @ (8004bfc ) 80048d0: 689b ldr r3, [r3, #8] 80048d2: f003 030c and.w r3, r3, #12 80048d6: 2b0c cmp r3, #12 80048d8: f200 8206 bhi.w 8004ce8 80048dc: a201 add r2, pc, #4 @ (adr r2, 80048e4 ) 80048de: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80048e2: bf00 nop 80048e4: 08004919 .word 0x08004919 80048e8: 08004ce9 .word 0x08004ce9 80048ec: 08004ce9 .word 0x08004ce9 80048f0: 08004ce9 .word 0x08004ce9 80048f4: 08004921 .word 0x08004921 80048f8: 08004ce9 .word 0x08004ce9 80048fc: 08004ce9 .word 0x08004ce9 8004900: 08004ce9 .word 0x08004ce9 8004904: 08004929 .word 0x08004929 8004908: 08004ce9 .word 0x08004ce9 800490c: 08004ce9 .word 0x08004ce9 8004910: 08004ce9 .word 0x08004ce9 8004914: 08004b19 .word 0x08004b19 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8004918: 4bb9 ldr r3, [pc, #740] @ (8004c00 ) 800491a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 800491e: e1e7 b.n 8004cf0 } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 8004920: 4bb8 ldr r3, [pc, #736] @ (8004c04 ) 8004922: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004926: e1e3 b.n 8004cf0 } case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004928: 4bb4 ldr r3, [pc, #720] @ (8004bfc ) 800492a: 685b ldr r3, [r3, #4] 800492c: f003 033f and.w r3, r3, #63 @ 0x3f 8004930: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004934: 4bb1 ldr r3, [pc, #708] @ (8004bfc ) 8004936: 685b ldr r3, [r3, #4] 8004938: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800493c: 2b00 cmp r3, #0 800493e: d071 beq.n 8004a24 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004940: 4bae ldr r3, [pc, #696] @ (8004bfc ) 8004942: 685b ldr r3, [r3, #4] 8004944: 099b lsrs r3, r3, #6 8004946: 2200 movs r2, #0 8004948: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800494c: f8c7 209c str.w r2, [r7, #156] @ 0x9c 8004950: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8004954: f3c3 0308 ubfx r3, r3, #0, #9 8004958: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800495c: 2300 movs r3, #0 800495e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8004962: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8004966: 4622 mov r2, r4 8004968: 462b mov r3, r5 800496a: f04f 0000 mov.w r0, #0 800496e: f04f 0100 mov.w r1, #0 8004972: 0159 lsls r1, r3, #5 8004974: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004978: 0150 lsls r0, r2, #5 800497a: 4602 mov r2, r0 800497c: 460b mov r3, r1 800497e: 4621 mov r1, r4 8004980: 1a51 subs r1, r2, r1 8004982: 6439 str r1, [r7, #64] @ 0x40 8004984: 4629 mov r1, r5 8004986: eb63 0301 sbc.w r3, r3, r1 800498a: 647b str r3, [r7, #68] @ 0x44 800498c: f04f 0200 mov.w r2, #0 8004990: f04f 0300 mov.w r3, #0 8004994: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40 8004998: 4649 mov r1, r9 800499a: 018b lsls r3, r1, #6 800499c: 4641 mov r1, r8 800499e: ea43 6391 orr.w r3, r3, r1, lsr #26 80049a2: 4641 mov r1, r8 80049a4: 018a lsls r2, r1, #6 80049a6: 4641 mov r1, r8 80049a8: 1a51 subs r1, r2, r1 80049aa: 63b9 str r1, [r7, #56] @ 0x38 80049ac: 4649 mov r1, r9 80049ae: eb63 0301 sbc.w r3, r3, r1 80049b2: 63fb str r3, [r7, #60] @ 0x3c 80049b4: f04f 0200 mov.w r2, #0 80049b8: f04f 0300 mov.w r3, #0 80049bc: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38 80049c0: 4649 mov r1, r9 80049c2: 00cb lsls r3, r1, #3 80049c4: 4641 mov r1, r8 80049c6: ea43 7351 orr.w r3, r3, r1, lsr #29 80049ca: 4641 mov r1, r8 80049cc: 00ca lsls r2, r1, #3 80049ce: 4610 mov r0, r2 80049d0: 4619 mov r1, r3 80049d2: 4603 mov r3, r0 80049d4: 4622 mov r2, r4 80049d6: 189b adds r3, r3, r2 80049d8: 633b str r3, [r7, #48] @ 0x30 80049da: 462b mov r3, r5 80049dc: 460a mov r2, r1 80049de: eb42 0303 adc.w r3, r2, r3 80049e2: 637b str r3, [r7, #52] @ 0x34 80049e4: f04f 0200 mov.w r2, #0 80049e8: f04f 0300 mov.w r3, #0 80049ec: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 80049f0: 4629 mov r1, r5 80049f2: 024b lsls r3, r1, #9 80049f4: 4621 mov r1, r4 80049f6: ea43 53d1 orr.w r3, r3, r1, lsr #23 80049fa: 4621 mov r1, r4 80049fc: 024a lsls r2, r1, #9 80049fe: 4610 mov r0, r2 8004a00: 4619 mov r1, r3 8004a02: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004a06: 2200 movs r2, #0 8004a08: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8004a0c: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8004a10: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88 8004a14: f7fb fbf6 bl 8000204 <__aeabi_uldivmod> 8004a18: 4602 mov r2, r0 8004a1a: 460b mov r3, r1 8004a1c: 4613 mov r3, r2 8004a1e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8004a22: e067 b.n 8004af4 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004a24: 4b75 ldr r3, [pc, #468] @ (8004bfc ) 8004a26: 685b ldr r3, [r3, #4] 8004a28: 099b lsrs r3, r3, #6 8004a2a: 2200 movs r2, #0 8004a2c: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8004a30: f8c7 2084 str.w r2, [r7, #132] @ 0x84 8004a34: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8004a38: f3c3 0308 ubfx r3, r3, #0, #9 8004a3c: 67bb str r3, [r7, #120] @ 0x78 8004a3e: 2300 movs r3, #0 8004a40: 67fb str r3, [r7, #124] @ 0x7c 8004a42: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78 8004a46: 4622 mov r2, r4 8004a48: 462b mov r3, r5 8004a4a: f04f 0000 mov.w r0, #0 8004a4e: f04f 0100 mov.w r1, #0 8004a52: 0159 lsls r1, r3, #5 8004a54: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004a58: 0150 lsls r0, r2, #5 8004a5a: 4602 mov r2, r0 8004a5c: 460b mov r3, r1 8004a5e: 4621 mov r1, r4 8004a60: 1a51 subs r1, r2, r1 8004a62: 62b9 str r1, [r7, #40] @ 0x28 8004a64: 4629 mov r1, r5 8004a66: eb63 0301 sbc.w r3, r3, r1 8004a6a: 62fb str r3, [r7, #44] @ 0x2c 8004a6c: f04f 0200 mov.w r2, #0 8004a70: f04f 0300 mov.w r3, #0 8004a74: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28 8004a78: 4649 mov r1, r9 8004a7a: 018b lsls r3, r1, #6 8004a7c: 4641 mov r1, r8 8004a7e: ea43 6391 orr.w r3, r3, r1, lsr #26 8004a82: 4641 mov r1, r8 8004a84: 018a lsls r2, r1, #6 8004a86: 4641 mov r1, r8 8004a88: ebb2 0a01 subs.w sl, r2, r1 8004a8c: 4649 mov r1, r9 8004a8e: eb63 0b01 sbc.w fp, r3, r1 8004a92: f04f 0200 mov.w r2, #0 8004a96: f04f 0300 mov.w r3, #0 8004a9a: ea4f 03cb mov.w r3, fp, lsl #3 8004a9e: ea43 735a orr.w r3, r3, sl, lsr #29 8004aa2: ea4f 02ca mov.w r2, sl, lsl #3 8004aa6: 4692 mov sl, r2 8004aa8: 469b mov fp, r3 8004aaa: 4623 mov r3, r4 8004aac: eb1a 0303 adds.w r3, sl, r3 8004ab0: 623b str r3, [r7, #32] 8004ab2: 462b mov r3, r5 8004ab4: eb4b 0303 adc.w r3, fp, r3 8004ab8: 627b str r3, [r7, #36] @ 0x24 8004aba: f04f 0200 mov.w r2, #0 8004abe: f04f 0300 mov.w r3, #0 8004ac2: e9d7 4508 ldrd r4, r5, [r7, #32] 8004ac6: 4629 mov r1, r5 8004ac8: 028b lsls r3, r1, #10 8004aca: 4621 mov r1, r4 8004acc: ea43 5391 orr.w r3, r3, r1, lsr #22 8004ad0: 4621 mov r1, r4 8004ad2: 028a lsls r2, r1, #10 8004ad4: 4610 mov r0, r2 8004ad6: 4619 mov r1, r3 8004ad8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004adc: 2200 movs r2, #0 8004ade: 673b str r3, [r7, #112] @ 0x70 8004ae0: 677a str r2, [r7, #116] @ 0x74 8004ae2: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70 8004ae6: f7fb fb8d bl 8000204 <__aeabi_uldivmod> 8004aea: 4602 mov r2, r0 8004aec: 460b mov r3, r1 8004aee: 4613 mov r3, r2 8004af0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); 8004af4: 4b41 ldr r3, [pc, #260] @ (8004bfc ) 8004af6: 685b ldr r3, [r3, #4] 8004af8: 0c1b lsrs r3, r3, #16 8004afa: f003 0303 and.w r3, r3, #3 8004afe: 3301 adds r3, #1 8004b00: 005b lsls r3, r3, #1 8004b02: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 sysclockfreq = pllvco / pllp; 8004b06: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004b0a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8004b0e: fbb2 f3f3 udiv r3, r2, r3 8004b12: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004b16: e0eb b.n 8004cf0 } case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004b18: 4b38 ldr r3, [pc, #224] @ (8004bfc ) 8004b1a: 685b ldr r3, [r3, #4] 8004b1c: f003 033f and.w r3, r3, #63 @ 0x3f 8004b20: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004b24: 4b35 ldr r3, [pc, #212] @ (8004bfc ) 8004b26: 685b ldr r3, [r3, #4] 8004b28: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004b2c: 2b00 cmp r3, #0 8004b2e: d06b beq.n 8004c08 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004b30: 4b32 ldr r3, [pc, #200] @ (8004bfc ) 8004b32: 685b ldr r3, [r3, #4] 8004b34: 099b lsrs r3, r3, #6 8004b36: 2200 movs r2, #0 8004b38: 66bb str r3, [r7, #104] @ 0x68 8004b3a: 66fa str r2, [r7, #108] @ 0x6c 8004b3c: 6ebb ldr r3, [r7, #104] @ 0x68 8004b3e: f3c3 0308 ubfx r3, r3, #0, #9 8004b42: 663b str r3, [r7, #96] @ 0x60 8004b44: 2300 movs r3, #0 8004b46: 667b str r3, [r7, #100] @ 0x64 8004b48: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60 8004b4c: 4622 mov r2, r4 8004b4e: 462b mov r3, r5 8004b50: f04f 0000 mov.w r0, #0 8004b54: f04f 0100 mov.w r1, #0 8004b58: 0159 lsls r1, r3, #5 8004b5a: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004b5e: 0150 lsls r0, r2, #5 8004b60: 4602 mov r2, r0 8004b62: 460b mov r3, r1 8004b64: 4621 mov r1, r4 8004b66: 1a51 subs r1, r2, r1 8004b68: 61b9 str r1, [r7, #24] 8004b6a: 4629 mov r1, r5 8004b6c: eb63 0301 sbc.w r3, r3, r1 8004b70: 61fb str r3, [r7, #28] 8004b72: f04f 0200 mov.w r2, #0 8004b76: f04f 0300 mov.w r3, #0 8004b7a: e9d7 ab06 ldrd sl, fp, [r7, #24] 8004b7e: 4659 mov r1, fp 8004b80: 018b lsls r3, r1, #6 8004b82: 4651 mov r1, sl 8004b84: ea43 6391 orr.w r3, r3, r1, lsr #26 8004b88: 4651 mov r1, sl 8004b8a: 018a lsls r2, r1, #6 8004b8c: 4651 mov r1, sl 8004b8e: ebb2 0801 subs.w r8, r2, r1 8004b92: 4659 mov r1, fp 8004b94: eb63 0901 sbc.w r9, r3, r1 8004b98: f04f 0200 mov.w r2, #0 8004b9c: f04f 0300 mov.w r3, #0 8004ba0: ea4f 03c9 mov.w r3, r9, lsl #3 8004ba4: ea43 7358 orr.w r3, r3, r8, lsr #29 8004ba8: ea4f 02c8 mov.w r2, r8, lsl #3 8004bac: 4690 mov r8, r2 8004bae: 4699 mov r9, r3 8004bb0: 4623 mov r3, r4 8004bb2: eb18 0303 adds.w r3, r8, r3 8004bb6: 613b str r3, [r7, #16] 8004bb8: 462b mov r3, r5 8004bba: eb49 0303 adc.w r3, r9, r3 8004bbe: 617b str r3, [r7, #20] 8004bc0: f04f 0200 mov.w r2, #0 8004bc4: f04f 0300 mov.w r3, #0 8004bc8: e9d7 4504 ldrd r4, r5, [r7, #16] 8004bcc: 4629 mov r1, r5 8004bce: 024b lsls r3, r1, #9 8004bd0: 4621 mov r1, r4 8004bd2: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004bd6: 4621 mov r1, r4 8004bd8: 024a lsls r2, r1, #9 8004bda: 4610 mov r0, r2 8004bdc: 4619 mov r1, r3 8004bde: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004be2: 2200 movs r2, #0 8004be4: 65bb str r3, [r7, #88] @ 0x58 8004be6: 65fa str r2, [r7, #92] @ 0x5c 8004be8: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8004bec: f7fb fb0a bl 8000204 <__aeabi_uldivmod> 8004bf0: 4602 mov r2, r0 8004bf2: 460b mov r3, r1 8004bf4: 4613 mov r3, r2 8004bf6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8004bfa: e065 b.n 8004cc8 8004bfc: 40023800 .word 0x40023800 8004c00: 00f42400 .word 0x00f42400 8004c04: 007a1200 .word 0x007a1200 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004c08: 4b3d ldr r3, [pc, #244] @ (8004d00 ) 8004c0a: 685b ldr r3, [r3, #4] 8004c0c: 099b lsrs r3, r3, #6 8004c0e: 2200 movs r2, #0 8004c10: 4618 mov r0, r3 8004c12: 4611 mov r1, r2 8004c14: f3c0 0308 ubfx r3, r0, #0, #9 8004c18: 653b str r3, [r7, #80] @ 0x50 8004c1a: 2300 movs r3, #0 8004c1c: 657b str r3, [r7, #84] @ 0x54 8004c1e: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50 8004c22: 4642 mov r2, r8 8004c24: 464b mov r3, r9 8004c26: f04f 0000 mov.w r0, #0 8004c2a: f04f 0100 mov.w r1, #0 8004c2e: 0159 lsls r1, r3, #5 8004c30: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004c34: 0150 lsls r0, r2, #5 8004c36: 4602 mov r2, r0 8004c38: 460b mov r3, r1 8004c3a: 4641 mov r1, r8 8004c3c: 1a51 subs r1, r2, r1 8004c3e: 60b9 str r1, [r7, #8] 8004c40: 4649 mov r1, r9 8004c42: eb63 0301 sbc.w r3, r3, r1 8004c46: 60fb str r3, [r7, #12] 8004c48: f04f 0200 mov.w r2, #0 8004c4c: f04f 0300 mov.w r3, #0 8004c50: e9d7 ab02 ldrd sl, fp, [r7, #8] 8004c54: 4659 mov r1, fp 8004c56: 018b lsls r3, r1, #6 8004c58: 4651 mov r1, sl 8004c5a: ea43 6391 orr.w r3, r3, r1, lsr #26 8004c5e: 4651 mov r1, sl 8004c60: 018a lsls r2, r1, #6 8004c62: 4651 mov r1, sl 8004c64: 1a54 subs r4, r2, r1 8004c66: 4659 mov r1, fp 8004c68: eb63 0501 sbc.w r5, r3, r1 8004c6c: f04f 0200 mov.w r2, #0 8004c70: f04f 0300 mov.w r3, #0 8004c74: 00eb lsls r3, r5, #3 8004c76: ea43 7354 orr.w r3, r3, r4, lsr #29 8004c7a: 00e2 lsls r2, r4, #3 8004c7c: 4614 mov r4, r2 8004c7e: 461d mov r5, r3 8004c80: 4643 mov r3, r8 8004c82: 18e3 adds r3, r4, r3 8004c84: 603b str r3, [r7, #0] 8004c86: 464b mov r3, r9 8004c88: eb45 0303 adc.w r3, r5, r3 8004c8c: 607b str r3, [r7, #4] 8004c8e: f04f 0200 mov.w r2, #0 8004c92: f04f 0300 mov.w r3, #0 8004c96: e9d7 4500 ldrd r4, r5, [r7] 8004c9a: 4629 mov r1, r5 8004c9c: 028b lsls r3, r1, #10 8004c9e: 4621 mov r1, r4 8004ca0: ea43 5391 orr.w r3, r3, r1, lsr #22 8004ca4: 4621 mov r1, r4 8004ca6: 028a lsls r2, r1, #10 8004ca8: 4610 mov r0, r2 8004caa: 4619 mov r1, r3 8004cac: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004cb0: 2200 movs r2, #0 8004cb2: 64bb str r3, [r7, #72] @ 0x48 8004cb4: 64fa str r2, [r7, #76] @ 0x4c 8004cb6: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8004cba: f7fb faa3 bl 8000204 <__aeabi_uldivmod> 8004cbe: 4602 mov r2, r0 8004cc0: 460b mov r3, r1 8004cc2: 4613 mov r3, r2 8004cc4: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); 8004cc8: 4b0d ldr r3, [pc, #52] @ (8004d00 ) 8004cca: 685b ldr r3, [r3, #4] 8004ccc: 0f1b lsrs r3, r3, #28 8004cce: f003 0307 and.w r3, r3, #7 8004cd2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 sysclockfreq = pllvco / pllr; 8004cd6: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004cda: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8004cde: fbb2 f3f3 udiv r3, r2, r3 8004ce2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004ce6: e003 b.n 8004cf0 } default: { sysclockfreq = HSI_VALUE; 8004ce8: 4b06 ldr r3, [pc, #24] @ (8004d04 ) 8004cea: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004cee: bf00 nop } } return sysclockfreq; 8004cf0: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 } 8004cf4: 4618 mov r0, r3 8004cf6: 37b8 adds r7, #184 @ 0xb8 8004cf8: 46bd mov sp, r7 8004cfa: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8004cfe: bf00 nop 8004d00: 40023800 .word 0x40023800 8004d04: 00f42400 .word 0x00f42400 08004d08 : * @note This function add the PLL/PLLR factor management during PLL configuration this feature * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 8004d08: b580 push {r7, lr} 8004d0a: b086 sub sp, #24 8004d0c: af00 add r7, sp, #0 8004d0e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8004d10: 687b ldr r3, [r7, #4] 8004d12: 2b00 cmp r3, #0 8004d14: d101 bne.n 8004d1a { return HAL_ERROR; 8004d16: 2301 movs r3, #1 8004d18: e28d b.n 8005236 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8004d1a: 687b ldr r3, [r7, #4] 8004d1c: 681b ldr r3, [r3, #0] 8004d1e: f003 0301 and.w r3, r3, #1 8004d22: 2b00 cmp r3, #0 8004d24: f000 8083 beq.w 8004e2e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 8004d28: 4b94 ldr r3, [pc, #592] @ (8004f7c ) 8004d2a: 689b ldr r3, [r3, #8] 8004d2c: f003 030c and.w r3, r3, #12 8004d30: 2b04 cmp r3, #4 8004d32: d019 beq.n 8004d68 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004d34: 4b91 ldr r3, [pc, #580] @ (8004f7c ) 8004d36: 689b ldr r3, [r3, #8] 8004d38: f003 030c and.w r3, r3, #12 || \ 8004d3c: 2b08 cmp r3, #8 8004d3e: d106 bne.n 8004d4e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004d40: 4b8e ldr r3, [pc, #568] @ (8004f7c ) 8004d42: 685b ldr r3, [r3, #4] 8004d44: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004d48: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004d4c: d00c beq.n 8004d68 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8004d4e: 4b8b ldr r3, [pc, #556] @ (8004f7c ) 8004d50: 689b ldr r3, [r3, #8] 8004d52: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8004d56: 2b0c cmp r3, #12 8004d58: d112 bne.n 8004d80 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8004d5a: 4b88 ldr r3, [pc, #544] @ (8004f7c ) 8004d5c: 685b ldr r3, [r3, #4] 8004d5e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004d62: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004d66: d10b bne.n 8004d80 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) #endif /* STM32F446xx */ { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004d68: 4b84 ldr r3, [pc, #528] @ (8004f7c ) 8004d6a: 681b ldr r3, [r3, #0] 8004d6c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004d70: 2b00 cmp r3, #0 8004d72: d05b beq.n 8004e2c 8004d74: 687b ldr r3, [r7, #4] 8004d76: 685b ldr r3, [r3, #4] 8004d78: 2b00 cmp r3, #0 8004d7a: d157 bne.n 8004e2c { return HAL_ERROR; 8004d7c: 2301 movs r3, #1 8004d7e: e25a b.n 8005236 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8004d80: 687b ldr r3, [r7, #4] 8004d82: 685b ldr r3, [r3, #4] 8004d84: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004d88: d106 bne.n 8004d98 8004d8a: 4b7c ldr r3, [pc, #496] @ (8004f7c ) 8004d8c: 681b ldr r3, [r3, #0] 8004d8e: 4a7b ldr r2, [pc, #492] @ (8004f7c ) 8004d90: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004d94: 6013 str r3, [r2, #0] 8004d96: e01d b.n 8004dd4 8004d98: 687b ldr r3, [r7, #4] 8004d9a: 685b ldr r3, [r3, #4] 8004d9c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8004da0: d10c bne.n 8004dbc 8004da2: 4b76 ldr r3, [pc, #472] @ (8004f7c ) 8004da4: 681b ldr r3, [r3, #0] 8004da6: 4a75 ldr r2, [pc, #468] @ (8004f7c ) 8004da8: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8004dac: 6013 str r3, [r2, #0] 8004dae: 4b73 ldr r3, [pc, #460] @ (8004f7c ) 8004db0: 681b ldr r3, [r3, #0] 8004db2: 4a72 ldr r2, [pc, #456] @ (8004f7c ) 8004db4: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004db8: 6013 str r3, [r2, #0] 8004dba: e00b b.n 8004dd4 8004dbc: 4b6f ldr r3, [pc, #444] @ (8004f7c ) 8004dbe: 681b ldr r3, [r3, #0] 8004dc0: 4a6e ldr r2, [pc, #440] @ (8004f7c ) 8004dc2: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8004dc6: 6013 str r3, [r2, #0] 8004dc8: 4b6c ldr r3, [pc, #432] @ (8004f7c ) 8004dca: 681b ldr r3, [r3, #0] 8004dcc: 4a6b ldr r2, [pc, #428] @ (8004f7c ) 8004dce: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8004dd2: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 8004dd4: 687b ldr r3, [r7, #4] 8004dd6: 685b ldr r3, [r3, #4] 8004dd8: 2b00 cmp r3, #0 8004dda: d013 beq.n 8004e04 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004ddc: f7fc fe4c bl 8001a78 8004de0: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004de2: e008 b.n 8004df6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004de4: f7fc fe48 bl 8001a78 8004de8: 4602 mov r2, r0 8004dea: 693b ldr r3, [r7, #16] 8004dec: 1ad3 subs r3, r2, r3 8004dee: 2b64 cmp r3, #100 @ 0x64 8004df0: d901 bls.n 8004df6 { return HAL_TIMEOUT; 8004df2: 2303 movs r3, #3 8004df4: e21f b.n 8005236 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004df6: 4b61 ldr r3, [pc, #388] @ (8004f7c ) 8004df8: 681b ldr r3, [r3, #0] 8004dfa: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004dfe: 2b00 cmp r3, #0 8004e00: d0f0 beq.n 8004de4 8004e02: e014 b.n 8004e2e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004e04: f7fc fe38 bl 8001a78 8004e08: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004e0a: e008 b.n 8004e1e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004e0c: f7fc fe34 bl 8001a78 8004e10: 4602 mov r2, r0 8004e12: 693b ldr r3, [r7, #16] 8004e14: 1ad3 subs r3, r2, r3 8004e16: 2b64 cmp r3, #100 @ 0x64 8004e18: d901 bls.n 8004e1e { return HAL_TIMEOUT; 8004e1a: 2303 movs r3, #3 8004e1c: e20b b.n 8005236 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004e1e: 4b57 ldr r3, [pc, #348] @ (8004f7c ) 8004e20: 681b ldr r3, [r3, #0] 8004e22: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004e26: 2b00 cmp r3, #0 8004e28: d1f0 bne.n 8004e0c 8004e2a: e000 b.n 8004e2e if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004e2c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8004e2e: 687b ldr r3, [r7, #4] 8004e30: 681b ldr r3, [r3, #0] 8004e32: f003 0302 and.w r3, r3, #2 8004e36: 2b00 cmp r3, #0 8004e38: d06f beq.n 8004f1a assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 8004e3a: 4b50 ldr r3, [pc, #320] @ (8004f7c ) 8004e3c: 689b ldr r3, [r3, #8] 8004e3e: f003 030c and.w r3, r3, #12 8004e42: 2b00 cmp r3, #0 8004e44: d017 beq.n 8004e76 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004e46: 4b4d ldr r3, [pc, #308] @ (8004f7c ) 8004e48: 689b ldr r3, [r3, #8] 8004e4a: f003 030c and.w r3, r3, #12 || \ 8004e4e: 2b08 cmp r3, #8 8004e50: d105 bne.n 8004e5e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004e52: 4b4a ldr r3, [pc, #296] @ (8004f7c ) 8004e54: 685b ldr r3, [r3, #4] 8004e56: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004e5a: 2b00 cmp r3, #0 8004e5c: d00b beq.n 8004e76 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004e5e: 4b47 ldr r3, [pc, #284] @ (8004f7c ) 8004e60: 689b ldr r3, [r3, #8] 8004e62: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8004e66: 2b0c cmp r3, #12 8004e68: d11c bne.n 8004ea4 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004e6a: 4b44 ldr r3, [pc, #272] @ (8004f7c ) 8004e6c: 685b ldr r3, [r3, #4] 8004e6e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004e72: 2b00 cmp r3, #0 8004e74: d116 bne.n 8004ea4 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) #endif /* STM32F446xx */ { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004e76: 4b41 ldr r3, [pc, #260] @ (8004f7c ) 8004e78: 681b ldr r3, [r3, #0] 8004e7a: f003 0302 and.w r3, r3, #2 8004e7e: 2b00 cmp r3, #0 8004e80: d005 beq.n 8004e8e 8004e82: 687b ldr r3, [r7, #4] 8004e84: 68db ldr r3, [r3, #12] 8004e86: 2b01 cmp r3, #1 8004e88: d001 beq.n 8004e8e { return HAL_ERROR; 8004e8a: 2301 movs r3, #1 8004e8c: e1d3 b.n 8005236 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004e8e: 4b3b ldr r3, [pc, #236] @ (8004f7c ) 8004e90: 681b ldr r3, [r3, #0] 8004e92: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004e96: 687b ldr r3, [r7, #4] 8004e98: 691b ldr r3, [r3, #16] 8004e9a: 00db lsls r3, r3, #3 8004e9c: 4937 ldr r1, [pc, #220] @ (8004f7c ) 8004e9e: 4313 orrs r3, r2 8004ea0: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004ea2: e03a b.n 8004f1a } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8004ea4: 687b ldr r3, [r7, #4] 8004ea6: 68db ldr r3, [r3, #12] 8004ea8: 2b00 cmp r3, #0 8004eaa: d020 beq.n 8004eee { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8004eac: 4b34 ldr r3, [pc, #208] @ (8004f80 ) 8004eae: 2201 movs r2, #1 8004eb0: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004eb2: f7fc fde1 bl 8001a78 8004eb6: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004eb8: e008 b.n 8004ecc { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004eba: f7fc fddd bl 8001a78 8004ebe: 4602 mov r2, r0 8004ec0: 693b ldr r3, [r7, #16] 8004ec2: 1ad3 subs r3, r2, r3 8004ec4: 2b02 cmp r3, #2 8004ec6: d901 bls.n 8004ecc { return HAL_TIMEOUT; 8004ec8: 2303 movs r3, #3 8004eca: e1b4 b.n 8005236 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004ecc: 4b2b ldr r3, [pc, #172] @ (8004f7c ) 8004ece: 681b ldr r3, [r3, #0] 8004ed0: f003 0302 and.w r3, r3, #2 8004ed4: 2b00 cmp r3, #0 8004ed6: d0f0 beq.n 8004eba } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004ed8: 4b28 ldr r3, [pc, #160] @ (8004f7c ) 8004eda: 681b ldr r3, [r3, #0] 8004edc: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004ee0: 687b ldr r3, [r7, #4] 8004ee2: 691b ldr r3, [r3, #16] 8004ee4: 00db lsls r3, r3, #3 8004ee6: 4925 ldr r1, [pc, #148] @ (8004f7c ) 8004ee8: 4313 orrs r3, r2 8004eea: 600b str r3, [r1, #0] 8004eec: e015 b.n 8004f1a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8004eee: 4b24 ldr r3, [pc, #144] @ (8004f80 ) 8004ef0: 2200 movs r2, #0 8004ef2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004ef4: f7fc fdc0 bl 8001a78 8004ef8: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004efa: e008 b.n 8004f0e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004efc: f7fc fdbc bl 8001a78 8004f00: 4602 mov r2, r0 8004f02: 693b ldr r3, [r7, #16] 8004f04: 1ad3 subs r3, r2, r3 8004f06: 2b02 cmp r3, #2 8004f08: d901 bls.n 8004f0e { return HAL_TIMEOUT; 8004f0a: 2303 movs r3, #3 8004f0c: e193 b.n 8005236 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004f0e: 4b1b ldr r3, [pc, #108] @ (8004f7c ) 8004f10: 681b ldr r3, [r3, #0] 8004f12: f003 0302 and.w r3, r3, #2 8004f16: 2b00 cmp r3, #0 8004f18: d1f0 bne.n 8004efc } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8004f1a: 687b ldr r3, [r7, #4] 8004f1c: 681b ldr r3, [r3, #0] 8004f1e: f003 0308 and.w r3, r3, #8 8004f22: 2b00 cmp r3, #0 8004f24: d036 beq.n 8004f94 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 8004f26: 687b ldr r3, [r7, #4] 8004f28: 695b ldr r3, [r3, #20] 8004f2a: 2b00 cmp r3, #0 8004f2c: d016 beq.n 8004f5c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8004f2e: 4b15 ldr r3, [pc, #84] @ (8004f84 ) 8004f30: 2201 movs r2, #1 8004f32: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004f34: f7fc fda0 bl 8001a78 8004f38: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004f3a: e008 b.n 8004f4e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004f3c: f7fc fd9c bl 8001a78 8004f40: 4602 mov r2, r0 8004f42: 693b ldr r3, [r7, #16] 8004f44: 1ad3 subs r3, r2, r3 8004f46: 2b02 cmp r3, #2 8004f48: d901 bls.n 8004f4e { return HAL_TIMEOUT; 8004f4a: 2303 movs r3, #3 8004f4c: e173 b.n 8005236 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004f4e: 4b0b ldr r3, [pc, #44] @ (8004f7c ) 8004f50: 6f5b ldr r3, [r3, #116] @ 0x74 8004f52: f003 0302 and.w r3, r3, #2 8004f56: 2b00 cmp r3, #0 8004f58: d0f0 beq.n 8004f3c 8004f5a: e01b b.n 8004f94 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8004f5c: 4b09 ldr r3, [pc, #36] @ (8004f84 ) 8004f5e: 2200 movs r2, #0 8004f60: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004f62: f7fc fd89 bl 8001a78 8004f66: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004f68: e00e b.n 8004f88 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004f6a: f7fc fd85 bl 8001a78 8004f6e: 4602 mov r2, r0 8004f70: 693b ldr r3, [r7, #16] 8004f72: 1ad3 subs r3, r2, r3 8004f74: 2b02 cmp r3, #2 8004f76: d907 bls.n 8004f88 { return HAL_TIMEOUT; 8004f78: 2303 movs r3, #3 8004f7a: e15c b.n 8005236 8004f7c: 40023800 .word 0x40023800 8004f80: 42470000 .word 0x42470000 8004f84: 42470e80 .word 0x42470e80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004f88: 4b8a ldr r3, [pc, #552] @ (80051b4 ) 8004f8a: 6f5b ldr r3, [r3, #116] @ 0x74 8004f8c: f003 0302 and.w r3, r3, #2 8004f90: 2b00 cmp r3, #0 8004f92: d1ea bne.n 8004f6a } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8004f94: 687b ldr r3, [r7, #4] 8004f96: 681b ldr r3, [r3, #0] 8004f98: f003 0304 and.w r3, r3, #4 8004f9c: 2b00 cmp r3, #0 8004f9e: f000 8097 beq.w 80050d0 { FlagStatus pwrclkchanged = RESET; 8004fa2: 2300 movs r3, #0 8004fa4: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8004fa6: 4b83 ldr r3, [pc, #524] @ (80051b4 ) 8004fa8: 6c1b ldr r3, [r3, #64] @ 0x40 8004faa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004fae: 2b00 cmp r3, #0 8004fb0: d10f bne.n 8004fd2 { __HAL_RCC_PWR_CLK_ENABLE(); 8004fb2: 2300 movs r3, #0 8004fb4: 60bb str r3, [r7, #8] 8004fb6: 4b7f ldr r3, [pc, #508] @ (80051b4 ) 8004fb8: 6c1b ldr r3, [r3, #64] @ 0x40 8004fba: 4a7e ldr r2, [pc, #504] @ (80051b4 ) 8004fbc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004fc0: 6413 str r3, [r2, #64] @ 0x40 8004fc2: 4b7c ldr r3, [pc, #496] @ (80051b4 ) 8004fc4: 6c1b ldr r3, [r3, #64] @ 0x40 8004fc6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004fca: 60bb str r3, [r7, #8] 8004fcc: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8004fce: 2301 movs r3, #1 8004fd0: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004fd2: 4b79 ldr r3, [pc, #484] @ (80051b8 ) 8004fd4: 681b ldr r3, [r3, #0] 8004fd6: f403 7380 and.w r3, r3, #256 @ 0x100 8004fda: 2b00 cmp r3, #0 8004fdc: d118 bne.n 8005010 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8004fde: 4b76 ldr r3, [pc, #472] @ (80051b8 ) 8004fe0: 681b ldr r3, [r3, #0] 8004fe2: 4a75 ldr r2, [pc, #468] @ (80051b8 ) 8004fe4: f443 7380 orr.w r3, r3, #256 @ 0x100 8004fe8: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8004fea: f7fc fd45 bl 8001a78 8004fee: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004ff0: e008 b.n 8005004 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004ff2: f7fc fd41 bl 8001a78 8004ff6: 4602 mov r2, r0 8004ff8: 693b ldr r3, [r7, #16] 8004ffa: 1ad3 subs r3, r2, r3 8004ffc: 2b02 cmp r3, #2 8004ffe: d901 bls.n 8005004 { return HAL_TIMEOUT; 8005000: 2303 movs r3, #3 8005002: e118 b.n 8005236 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005004: 4b6c ldr r3, [pc, #432] @ (80051b8 ) 8005006: 681b ldr r3, [r3, #0] 8005008: f403 7380 and.w r3, r3, #256 @ 0x100 800500c: 2b00 cmp r3, #0 800500e: d0f0 beq.n 8004ff2 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8005010: 687b ldr r3, [r7, #4] 8005012: 689b ldr r3, [r3, #8] 8005014: 2b01 cmp r3, #1 8005016: d106 bne.n 8005026 8005018: 4b66 ldr r3, [pc, #408] @ (80051b4 ) 800501a: 6f1b ldr r3, [r3, #112] @ 0x70 800501c: 4a65 ldr r2, [pc, #404] @ (80051b4 ) 800501e: f043 0301 orr.w r3, r3, #1 8005022: 6713 str r3, [r2, #112] @ 0x70 8005024: e01c b.n 8005060 8005026: 687b ldr r3, [r7, #4] 8005028: 689b ldr r3, [r3, #8] 800502a: 2b05 cmp r3, #5 800502c: d10c bne.n 8005048 800502e: 4b61 ldr r3, [pc, #388] @ (80051b4 ) 8005030: 6f1b ldr r3, [r3, #112] @ 0x70 8005032: 4a60 ldr r2, [pc, #384] @ (80051b4 ) 8005034: f043 0304 orr.w r3, r3, #4 8005038: 6713 str r3, [r2, #112] @ 0x70 800503a: 4b5e ldr r3, [pc, #376] @ (80051b4 ) 800503c: 6f1b ldr r3, [r3, #112] @ 0x70 800503e: 4a5d ldr r2, [pc, #372] @ (80051b4 ) 8005040: f043 0301 orr.w r3, r3, #1 8005044: 6713 str r3, [r2, #112] @ 0x70 8005046: e00b b.n 8005060 8005048: 4b5a ldr r3, [pc, #360] @ (80051b4 ) 800504a: 6f1b ldr r3, [r3, #112] @ 0x70 800504c: 4a59 ldr r2, [pc, #356] @ (80051b4 ) 800504e: f023 0301 bic.w r3, r3, #1 8005052: 6713 str r3, [r2, #112] @ 0x70 8005054: 4b57 ldr r3, [pc, #348] @ (80051b4 ) 8005056: 6f1b ldr r3, [r3, #112] @ 0x70 8005058: 4a56 ldr r2, [pc, #344] @ (80051b4 ) 800505a: f023 0304 bic.w r3, r3, #4 800505e: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8005060: 687b ldr r3, [r7, #4] 8005062: 689b ldr r3, [r3, #8] 8005064: 2b00 cmp r3, #0 8005066: d015 beq.n 8005094 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005068: f7fc fd06 bl 8001a78 800506c: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800506e: e00a b.n 8005086 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005070: f7fc fd02 bl 8001a78 8005074: 4602 mov r2, r0 8005076: 693b ldr r3, [r7, #16] 8005078: 1ad3 subs r3, r2, r3 800507a: f241 3288 movw r2, #5000 @ 0x1388 800507e: 4293 cmp r3, r2 8005080: d901 bls.n 8005086 { return HAL_TIMEOUT; 8005082: 2303 movs r3, #3 8005084: e0d7 b.n 8005236 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005086: 4b4b ldr r3, [pc, #300] @ (80051b4 ) 8005088: 6f1b ldr r3, [r3, #112] @ 0x70 800508a: f003 0302 and.w r3, r3, #2 800508e: 2b00 cmp r3, #0 8005090: d0ee beq.n 8005070 8005092: e014 b.n 80050be } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005094: f7fc fcf0 bl 8001a78 8005098: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800509a: e00a b.n 80050b2 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800509c: f7fc fcec bl 8001a78 80050a0: 4602 mov r2, r0 80050a2: 693b ldr r3, [r7, #16] 80050a4: 1ad3 subs r3, r2, r3 80050a6: f241 3288 movw r2, #5000 @ 0x1388 80050aa: 4293 cmp r3, r2 80050ac: d901 bls.n 80050b2 { return HAL_TIMEOUT; 80050ae: 2303 movs r3, #3 80050b0: e0c1 b.n 8005236 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80050b2: 4b40 ldr r3, [pc, #256] @ (80051b4 ) 80050b4: 6f1b ldr r3, [r3, #112] @ 0x70 80050b6: f003 0302 and.w r3, r3, #2 80050ba: 2b00 cmp r3, #0 80050bc: d1ee bne.n 800509c } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 80050be: 7dfb ldrb r3, [r7, #23] 80050c0: 2b01 cmp r3, #1 80050c2: d105 bne.n 80050d0 { __HAL_RCC_PWR_CLK_DISABLE(); 80050c4: 4b3b ldr r3, [pc, #236] @ (80051b4 ) 80050c6: 6c1b ldr r3, [r3, #64] @ 0x40 80050c8: 4a3a ldr r2, [pc, #232] @ (80051b4 ) 80050ca: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80050ce: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80050d0: 687b ldr r3, [r7, #4] 80050d2: 699b ldr r3, [r3, #24] 80050d4: 2b00 cmp r3, #0 80050d6: f000 80ad beq.w 8005234 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 80050da: 4b36 ldr r3, [pc, #216] @ (80051b4 ) 80050dc: 689b ldr r3, [r3, #8] 80050de: f003 030c and.w r3, r3, #12 80050e2: 2b08 cmp r3, #8 80050e4: d060 beq.n 80051a8 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80050e6: 687b ldr r3, [r7, #4] 80050e8: 699b ldr r3, [r3, #24] 80050ea: 2b02 cmp r3, #2 80050ec: d145 bne.n 800517a assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80050ee: 4b33 ldr r3, [pc, #204] @ (80051bc ) 80050f0: 2200 movs r2, #0 80050f2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80050f4: f7fc fcc0 bl 8001a78 80050f8: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80050fa: e008 b.n 800510e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80050fc: f7fc fcbc bl 8001a78 8005100: 4602 mov r2, r0 8005102: 693b ldr r3, [r7, #16] 8005104: 1ad3 subs r3, r2, r3 8005106: 2b02 cmp r3, #2 8005108: d901 bls.n 800510e { return HAL_TIMEOUT; 800510a: 2303 movs r3, #3 800510c: e093 b.n 8005236 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800510e: 4b29 ldr r3, [pc, #164] @ (80051b4 ) 8005110: 681b ldr r3, [r3, #0] 8005112: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005116: 2b00 cmp r3, #0 8005118: d1f0 bne.n 80050fc } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 800511a: 687b ldr r3, [r7, #4] 800511c: 69da ldr r2, [r3, #28] 800511e: 687b ldr r3, [r7, #4] 8005120: 6a1b ldr r3, [r3, #32] 8005122: 431a orrs r2, r3 8005124: 687b ldr r3, [r7, #4] 8005126: 6a5b ldr r3, [r3, #36] @ 0x24 8005128: 019b lsls r3, r3, #6 800512a: 431a orrs r2, r3 800512c: 687b ldr r3, [r7, #4] 800512e: 6a9b ldr r3, [r3, #40] @ 0x28 8005130: 085b lsrs r3, r3, #1 8005132: 3b01 subs r3, #1 8005134: 041b lsls r3, r3, #16 8005136: 431a orrs r2, r3 8005138: 687b ldr r3, [r7, #4] 800513a: 6adb ldr r3, [r3, #44] @ 0x2c 800513c: 061b lsls r3, r3, #24 800513e: 431a orrs r2, r3 8005140: 687b ldr r3, [r7, #4] 8005142: 6b1b ldr r3, [r3, #48] @ 0x30 8005144: 071b lsls r3, r3, #28 8005146: 491b ldr r1, [pc, #108] @ (80051b4 ) 8005148: 4313 orrs r3, r2 800514a: 604b str r3, [r1, #4] (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800514c: 4b1b ldr r3, [pc, #108] @ (80051bc ) 800514e: 2201 movs r2, #1 8005150: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005152: f7fc fc91 bl 8001a78 8005156: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8005158: e008 b.n 800516c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800515a: f7fc fc8d bl 8001a78 800515e: 4602 mov r2, r0 8005160: 693b ldr r3, [r7, #16] 8005162: 1ad3 subs r3, r2, r3 8005164: 2b02 cmp r3, #2 8005166: d901 bls.n 800516c { return HAL_TIMEOUT; 8005168: 2303 movs r3, #3 800516a: e064 b.n 8005236 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800516c: 4b11 ldr r3, [pc, #68] @ (80051b4 ) 800516e: 681b ldr r3, [r3, #0] 8005170: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005174: 2b00 cmp r3, #0 8005176: d0f0 beq.n 800515a 8005178: e05c b.n 8005234 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800517a: 4b10 ldr r3, [pc, #64] @ (80051bc ) 800517c: 2200 movs r2, #0 800517e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005180: f7fc fc7a bl 8001a78 8005184: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005186: e008 b.n 800519a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005188: f7fc fc76 bl 8001a78 800518c: 4602 mov r2, r0 800518e: 693b ldr r3, [r7, #16] 8005190: 1ad3 subs r3, r2, r3 8005192: 2b02 cmp r3, #2 8005194: d901 bls.n 800519a { return HAL_TIMEOUT; 8005196: 2303 movs r3, #3 8005198: e04d b.n 8005236 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800519a: 4b06 ldr r3, [pc, #24] @ (80051b4 ) 800519c: 681b ldr r3, [r3, #0] 800519e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80051a2: 2b00 cmp r3, #0 80051a4: d1f0 bne.n 8005188 80051a6: e045 b.n 8005234 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80051a8: 687b ldr r3, [r7, #4] 80051aa: 699b ldr r3, [r3, #24] 80051ac: 2b01 cmp r3, #1 80051ae: d107 bne.n 80051c0 { return HAL_ERROR; 80051b0: 2301 movs r3, #1 80051b2: e040 b.n 8005236 80051b4: 40023800 .word 0x40023800 80051b8: 40007000 .word 0x40007000 80051bc: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 80051c0: 4b1f ldr r3, [pc, #124] @ (8005240 ) 80051c2: 685b ldr r3, [r3, #4] 80051c4: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80051c6: 687b ldr r3, [r7, #4] 80051c8: 699b ldr r3, [r3, #24] 80051ca: 2b01 cmp r3, #1 80051cc: d030 beq.n 8005230 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80051ce: 68fb ldr r3, [r7, #12] 80051d0: f403 0280 and.w r2, r3, #4194304 @ 0x400000 80051d4: 687b ldr r3, [r7, #4] 80051d6: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80051d8: 429a cmp r2, r3 80051da: d129 bne.n 8005230 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80051dc: 68fb ldr r3, [r7, #12] 80051de: f003 023f and.w r2, r3, #63 @ 0x3f 80051e2: 687b ldr r3, [r7, #4] 80051e4: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80051e6: 429a cmp r2, r3 80051e8: d122 bne.n 8005230 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 80051ea: 68fa ldr r2, [r7, #12] 80051ec: f647 73c0 movw r3, #32704 @ 0x7fc0 80051f0: 4013 ands r3, r2 80051f2: 687a ldr r2, [r7, #4] 80051f4: 6a52 ldr r2, [r2, #36] @ 0x24 80051f6: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80051f8: 4293 cmp r3, r2 80051fa: d119 bne.n 8005230 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 80051fc: 68fb ldr r3, [r7, #12] 80051fe: f403 3240 and.w r2, r3, #196608 @ 0x30000 8005202: 687b ldr r3, [r7, #4] 8005204: 6a9b ldr r3, [r3, #40] @ 0x28 8005206: 085b lsrs r3, r3, #1 8005208: 3b01 subs r3, #1 800520a: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 800520c: 429a cmp r2, r3 800520e: d10f bne.n 8005230 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 8005210: 68fb ldr r3, [r7, #12] 8005212: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 8005216: 687b ldr r3, [r7, #4] 8005218: 6adb ldr r3, [r3, #44] @ 0x2c 800521a: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 800521c: 429a cmp r2, r3 800521e: d107 bne.n 8005230 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) 8005220: 68fb ldr r3, [r7, #12] 8005222: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000 8005226: 687b ldr r3, [r7, #4] 8005228: 6b1b ldr r3, [r3, #48] @ 0x30 800522a: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 800522c: 429a cmp r2, r3 800522e: d001 beq.n 8005234 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; 8005230: 2301 movs r3, #1 8005232: e000 b.n 8005236 } } } } return HAL_OK; 8005234: 2300 movs r3, #0 } 8005236: 4618 mov r0, r3 8005238: 3718 adds r7, #24 800523a: 46bd mov sp, r7 800523c: bd80 pop {r7, pc} 800523e: bf00 nop 8005240: 40023800 .word 0x40023800 08005244 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8005244: b580 push {r7, lr} 8005246: b082 sub sp, #8 8005248: af00 add r7, sp, #0 800524a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800524c: 687b ldr r3, [r7, #4] 800524e: 2b00 cmp r3, #0 8005250: d101 bne.n 8005256 { return HAL_ERROR; 8005252: 2301 movs r3, #1 8005254: e041 b.n 80052da assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8005256: 687b ldr r3, [r7, #4] 8005258: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800525c: b2db uxtb r3, r3 800525e: 2b00 cmp r3, #0 8005260: d106 bne.n 8005270 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005262: 687b ldr r3, [r7, #4] 8005264: 2200 movs r2, #0 8005266: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 800526a: 6878 ldr r0, [r7, #4] 800526c: f7fb ff6a bl 8001144 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005270: 687b ldr r3, [r7, #4] 8005272: 2202 movs r2, #2 8005274: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005278: 687b ldr r3, [r7, #4] 800527a: 681a ldr r2, [r3, #0] 800527c: 687b ldr r3, [r7, #4] 800527e: 3304 adds r3, #4 8005280: 4619 mov r1, r3 8005282: 4610 mov r0, r2 8005284: f000 f9f8 bl 8005678 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005288: 687b ldr r3, [r7, #4] 800528a: 2201 movs r2, #1 800528c: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005290: 687b ldr r3, [r7, #4] 8005292: 2201 movs r2, #1 8005294: f883 203e strb.w r2, [r3, #62] @ 0x3e 8005298: 687b ldr r3, [r7, #4] 800529a: 2201 movs r2, #1 800529c: f883 203f strb.w r2, [r3, #63] @ 0x3f 80052a0: 687b ldr r3, [r7, #4] 80052a2: 2201 movs r2, #1 80052a4: f883 2040 strb.w r2, [r3, #64] @ 0x40 80052a8: 687b ldr r3, [r7, #4] 80052aa: 2201 movs r2, #1 80052ac: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80052b0: 687b ldr r3, [r7, #4] 80052b2: 2201 movs r2, #1 80052b4: f883 2042 strb.w r2, [r3, #66] @ 0x42 80052b8: 687b ldr r3, [r7, #4] 80052ba: 2201 movs r2, #1 80052bc: f883 2043 strb.w r2, [r3, #67] @ 0x43 80052c0: 687b ldr r3, [r7, #4] 80052c2: 2201 movs r2, #1 80052c4: f883 2044 strb.w r2, [r3, #68] @ 0x44 80052c8: 687b ldr r3, [r7, #4] 80052ca: 2201 movs r2, #1 80052cc: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80052d0: 687b ldr r3, [r7, #4] 80052d2: 2201 movs r2, #1 80052d4: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80052d8: 2300 movs r3, #0 } 80052da: 4618 mov r0, r3 80052dc: 3708 adds r7, #8 80052de: 46bd mov sp, r7 80052e0: bd80 pop {r7, pc} ... 080052e4 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 80052e4: b580 push {r7, lr} 80052e6: b084 sub sp, #16 80052e8: af00 add r7, sp, #0 80052ea: 6078 str r0, [r7, #4] 80052ec: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 80052ee: 683b ldr r3, [r7, #0] 80052f0: 2b00 cmp r3, #0 80052f2: d109 bne.n 8005308 80052f4: 687b ldr r3, [r7, #4] 80052f6: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 80052fa: b2db uxtb r3, r3 80052fc: 2b01 cmp r3, #1 80052fe: bf14 ite ne 8005300: 2301 movne r3, #1 8005302: 2300 moveq r3, #0 8005304: b2db uxtb r3, r3 8005306: e022 b.n 800534e 8005308: 683b ldr r3, [r7, #0] 800530a: 2b04 cmp r3, #4 800530c: d109 bne.n 8005322 800530e: 687b ldr r3, [r7, #4] 8005310: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8005314: b2db uxtb r3, r3 8005316: 2b01 cmp r3, #1 8005318: bf14 ite ne 800531a: 2301 movne r3, #1 800531c: 2300 moveq r3, #0 800531e: b2db uxtb r3, r3 8005320: e015 b.n 800534e 8005322: 683b ldr r3, [r7, #0] 8005324: 2b08 cmp r3, #8 8005326: d109 bne.n 800533c 8005328: 687b ldr r3, [r7, #4] 800532a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800532e: b2db uxtb r3, r3 8005330: 2b01 cmp r3, #1 8005332: bf14 ite ne 8005334: 2301 movne r3, #1 8005336: 2300 moveq r3, #0 8005338: b2db uxtb r3, r3 800533a: e008 b.n 800534e 800533c: 687b ldr r3, [r7, #4] 800533e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005342: b2db uxtb r3, r3 8005344: 2b01 cmp r3, #1 8005346: bf14 ite ne 8005348: 2301 movne r3, #1 800534a: 2300 moveq r3, #0 800534c: b2db uxtb r3, r3 800534e: 2b00 cmp r3, #0 8005350: d001 beq.n 8005356 { return HAL_ERROR; 8005352: 2301 movs r3, #1 8005354: e07c b.n 8005450 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8005356: 683b ldr r3, [r7, #0] 8005358: 2b00 cmp r3, #0 800535a: d104 bne.n 8005366 800535c: 687b ldr r3, [r7, #4] 800535e: 2202 movs r2, #2 8005360: f883 203e strb.w r2, [r3, #62] @ 0x3e 8005364: e013 b.n 800538e 8005366: 683b ldr r3, [r7, #0] 8005368: 2b04 cmp r3, #4 800536a: d104 bne.n 8005376 800536c: 687b ldr r3, [r7, #4] 800536e: 2202 movs r2, #2 8005370: f883 203f strb.w r2, [r3, #63] @ 0x3f 8005374: e00b b.n 800538e 8005376: 683b ldr r3, [r7, #0] 8005378: 2b08 cmp r3, #8 800537a: d104 bne.n 8005386 800537c: 687b ldr r3, [r7, #4] 800537e: 2202 movs r2, #2 8005380: f883 2040 strb.w r2, [r3, #64] @ 0x40 8005384: e003 b.n 800538e 8005386: 687b ldr r3, [r7, #4] 8005388: 2202 movs r2, #2 800538a: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800538e: 687b ldr r3, [r7, #4] 8005390: 681b ldr r3, [r3, #0] 8005392: 2201 movs r2, #1 8005394: 6839 ldr r1, [r7, #0] 8005396: 4618 mov r0, r3 8005398: f000 fbc4 bl 8005b24 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800539c: 687b ldr r3, [r7, #4] 800539e: 681b ldr r3, [r3, #0] 80053a0: 4a2d ldr r2, [pc, #180] @ (8005458 ) 80053a2: 4293 cmp r3, r2 80053a4: d004 beq.n 80053b0 80053a6: 687b ldr r3, [r7, #4] 80053a8: 681b ldr r3, [r3, #0] 80053aa: 4a2c ldr r2, [pc, #176] @ (800545c ) 80053ac: 4293 cmp r3, r2 80053ae: d101 bne.n 80053b4 80053b0: 2301 movs r3, #1 80053b2: e000 b.n 80053b6 80053b4: 2300 movs r3, #0 80053b6: 2b00 cmp r3, #0 80053b8: d007 beq.n 80053ca { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 80053ba: 687b ldr r3, [r7, #4] 80053bc: 681b ldr r3, [r3, #0] 80053be: 6c5a ldr r2, [r3, #68] @ 0x44 80053c0: 687b ldr r3, [r7, #4] 80053c2: 681b ldr r3, [r3, #0] 80053c4: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80053c8: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80053ca: 687b ldr r3, [r7, #4] 80053cc: 681b ldr r3, [r3, #0] 80053ce: 4a22 ldr r2, [pc, #136] @ (8005458 ) 80053d0: 4293 cmp r3, r2 80053d2: d022 beq.n 800541a 80053d4: 687b ldr r3, [r7, #4] 80053d6: 681b ldr r3, [r3, #0] 80053d8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80053dc: d01d beq.n 800541a 80053de: 687b ldr r3, [r7, #4] 80053e0: 681b ldr r3, [r3, #0] 80053e2: 4a1f ldr r2, [pc, #124] @ (8005460 ) 80053e4: 4293 cmp r3, r2 80053e6: d018 beq.n 800541a 80053e8: 687b ldr r3, [r7, #4] 80053ea: 681b ldr r3, [r3, #0] 80053ec: 4a1d ldr r2, [pc, #116] @ (8005464 ) 80053ee: 4293 cmp r3, r2 80053f0: d013 beq.n 800541a 80053f2: 687b ldr r3, [r7, #4] 80053f4: 681b ldr r3, [r3, #0] 80053f6: 4a1c ldr r2, [pc, #112] @ (8005468 ) 80053f8: 4293 cmp r3, r2 80053fa: d00e beq.n 800541a 80053fc: 687b ldr r3, [r7, #4] 80053fe: 681b ldr r3, [r3, #0] 8005400: 4a16 ldr r2, [pc, #88] @ (800545c ) 8005402: 4293 cmp r3, r2 8005404: d009 beq.n 800541a 8005406: 687b ldr r3, [r7, #4] 8005408: 681b ldr r3, [r3, #0] 800540a: 4a18 ldr r2, [pc, #96] @ (800546c ) 800540c: 4293 cmp r3, r2 800540e: d004 beq.n 800541a 8005410: 687b ldr r3, [r7, #4] 8005412: 681b ldr r3, [r3, #0] 8005414: 4a16 ldr r2, [pc, #88] @ (8005470 ) 8005416: 4293 cmp r3, r2 8005418: d111 bne.n 800543e { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800541a: 687b ldr r3, [r7, #4] 800541c: 681b ldr r3, [r3, #0] 800541e: 689b ldr r3, [r3, #8] 8005420: f003 0307 and.w r3, r3, #7 8005424: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005426: 68fb ldr r3, [r7, #12] 8005428: 2b06 cmp r3, #6 800542a: d010 beq.n 800544e { __HAL_TIM_ENABLE(htim); 800542c: 687b ldr r3, [r7, #4] 800542e: 681b ldr r3, [r3, #0] 8005430: 681a ldr r2, [r3, #0] 8005432: 687b ldr r3, [r7, #4] 8005434: 681b ldr r3, [r3, #0] 8005436: f042 0201 orr.w r2, r2, #1 800543a: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800543c: e007 b.n 800544e } } else { __HAL_TIM_ENABLE(htim); 800543e: 687b ldr r3, [r7, #4] 8005440: 681b ldr r3, [r3, #0] 8005442: 681a ldr r2, [r3, #0] 8005444: 687b ldr r3, [r7, #4] 8005446: 681b ldr r3, [r3, #0] 8005448: f042 0201 orr.w r2, r2, #1 800544c: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 800544e: 2300 movs r3, #0 } 8005450: 4618 mov r0, r3 8005452: 3710 adds r7, #16 8005454: 46bd mov sp, r7 8005456: bd80 pop {r7, pc} 8005458: 40010000 .word 0x40010000 800545c: 40010400 .word 0x40010400 8005460: 40000400 .word 0x40000400 8005464: 40000800 .word 0x40000800 8005468: 40000c00 .word 0x40000c00 800546c: 40014000 .word 0x40014000 8005470: 40001800 .word 0x40001800 08005474 : * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { 8005474: b580 push {r7, lr} 8005476: b086 sub sp, #24 8005478: af00 add r7, sp, #0 800547a: 6078 str r0, [r7, #4] 800547c: 6039 str r1, [r7, #0] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) 800547e: 687b ldr r3, [r7, #4] 8005480: 2b00 cmp r3, #0 8005482: d101 bne.n 8005488 { return HAL_ERROR; 8005484: 2301 movs r3, #1 8005486: e097 b.n 80055b8 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) 8005488: 687b ldr r3, [r7, #4] 800548a: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800548e: b2db uxtb r3, r3 8005490: 2b00 cmp r3, #0 8005492: d106 bne.n 80054a2 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005494: 687b ldr r3, [r7, #4] 8005496: 2200 movs r2, #0 8005498: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); 800549c: 6878 ldr r0, [r7, #4] 800549e: f7fb fe71 bl 8001184 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80054a2: 687b ldr r3, [r7, #4] 80054a4: 2202 movs r2, #2 80054a6: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); 80054aa: 687b ldr r3, [r7, #4] 80054ac: 681b ldr r3, [r3, #0] 80054ae: 689b ldr r3, [r3, #8] 80054b0: 687a ldr r2, [r7, #4] 80054b2: 6812 ldr r2, [r2, #0] 80054b4: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80054b8: f023 0307 bic.w r3, r3, #7 80054bc: 6093 str r3, [r2, #8] /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80054be: 687b ldr r3, [r7, #4] 80054c0: 681a ldr r2, [r3, #0] 80054c2: 687b ldr r3, [r7, #4] 80054c4: 3304 adds r3, #4 80054c6: 4619 mov r1, r3 80054c8: 4610 mov r0, r2 80054ca: f000 f8d5 bl 8005678 /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80054ce: 687b ldr r3, [r7, #4] 80054d0: 681b ldr r3, [r3, #0] 80054d2: 689b ldr r3, [r3, #8] 80054d4: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; 80054d6: 687b ldr r3, [r7, #4] 80054d8: 681b ldr r3, [r3, #0] 80054da: 699b ldr r3, [r3, #24] 80054dc: 613b str r3, [r7, #16] /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; 80054de: 687b ldr r3, [r7, #4] 80054e0: 681b ldr r3, [r3, #0] 80054e2: 6a1b ldr r3, [r3, #32] 80054e4: 60fb str r3, [r7, #12] /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; 80054e6: 683b ldr r3, [r7, #0] 80054e8: 681b ldr r3, [r3, #0] 80054ea: 697a ldr r2, [r7, #20] 80054ec: 4313 orrs r3, r2 80054ee: 617b str r3, [r7, #20] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 80054f0: 693b ldr r3, [r7, #16] 80054f2: f423 7340 bic.w r3, r3, #768 @ 0x300 80054f6: f023 0303 bic.w r3, r3, #3 80054fa: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); 80054fc: 683b ldr r3, [r7, #0] 80054fe: 689a ldr r2, [r3, #8] 8005500: 683b ldr r3, [r7, #0] 8005502: 699b ldr r3, [r3, #24] 8005504: 021b lsls r3, r3, #8 8005506: 4313 orrs r3, r2 8005508: 693a ldr r2, [r7, #16] 800550a: 4313 orrs r3, r2 800550c: 613b str r3, [r7, #16] /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 800550e: 693b ldr r3, [r7, #16] 8005510: f423 6340 bic.w r3, r3, #3072 @ 0xc00 8005514: f023 030c bic.w r3, r3, #12 8005518: 613b str r3, [r7, #16] tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 800551a: 693b ldr r3, [r7, #16] 800551c: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8005520: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8005524: 613b str r3, [r7, #16] tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); 8005526: 683b ldr r3, [r7, #0] 8005528: 68da ldr r2, [r3, #12] 800552a: 683b ldr r3, [r7, #0] 800552c: 69db ldr r3, [r3, #28] 800552e: 021b lsls r3, r3, #8 8005530: 4313 orrs r3, r2 8005532: 693a ldr r2, [r7, #16] 8005534: 4313 orrs r3, r2 8005536: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); 8005538: 683b ldr r3, [r7, #0] 800553a: 691b ldr r3, [r3, #16] 800553c: 011a lsls r2, r3, #4 800553e: 683b ldr r3, [r7, #0] 8005540: 6a1b ldr r3, [r3, #32] 8005542: 031b lsls r3, r3, #12 8005544: 4313 orrs r3, r2 8005546: 693a ldr r2, [r7, #16] 8005548: 4313 orrs r3, r2 800554a: 613b str r3, [r7, #16] /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 800554c: 68fb ldr r3, [r7, #12] 800554e: f023 0322 bic.w r3, r3, #34 @ 0x22 8005552: 60fb str r3, [r7, #12] tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 8005554: 68fb ldr r3, [r7, #12] 8005556: f023 0388 bic.w r3, r3, #136 @ 0x88 800555a: 60fb str r3, [r7, #12] tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); 800555c: 683b ldr r3, [r7, #0] 800555e: 685a ldr r2, [r3, #4] 8005560: 683b ldr r3, [r7, #0] 8005562: 695b ldr r3, [r3, #20] 8005564: 011b lsls r3, r3, #4 8005566: 4313 orrs r3, r2 8005568: 68fa ldr r2, [r7, #12] 800556a: 4313 orrs r3, r2 800556c: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800556e: 687b ldr r3, [r7, #4] 8005570: 681b ldr r3, [r3, #0] 8005572: 697a ldr r2, [r7, #20] 8005574: 609a str r2, [r3, #8] /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; 8005576: 687b ldr r3, [r7, #4] 8005578: 681b ldr r3, [r3, #0] 800557a: 693a ldr r2, [r7, #16] 800557c: 619a str r2, [r3, #24] /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; 800557e: 687b ldr r3, [r7, #4] 8005580: 681b ldr r3, [r3, #0] 8005582: 68fa ldr r2, [r7, #12] 8005584: 621a str r2, [r3, #32] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005586: 687b ldr r3, [r7, #4] 8005588: 2201 movs r2, #1 800558a: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 800558e: 687b ldr r3, [r7, #4] 8005590: 2201 movs r2, #1 8005592: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005596: 687b ldr r3, [r7, #4] 8005598: 2201 movs r2, #1 800559a: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 800559e: 687b ldr r3, [r7, #4] 80055a0: 2201 movs r2, #1 80055a2: f883 2042 strb.w r2, [r3, #66] @ 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 80055a6: 687b ldr r3, [r7, #4] 80055a8: 2201 movs r2, #1 80055aa: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80055ae: 687b ldr r3, [r7, #4] 80055b0: 2201 movs r2, #1 80055b2: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80055b6: 2300 movs r3, #0 } 80055b8: 4618 mov r0, r3 80055ba: 3718 adds r7, #24 80055bc: 46bd mov sp, r7 80055be: bd80 pop {r7, pc} 080055c0 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80055c0: b580 push {r7, lr} 80055c2: b086 sub sp, #24 80055c4: af00 add r7, sp, #0 80055c6: 60f8 str r0, [r7, #12] 80055c8: 60b9 str r1, [r7, #8] 80055ca: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80055cc: 2300 movs r3, #0 80055ce: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 80055d0: 68fb ldr r3, [r7, #12] 80055d2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80055d6: 2b01 cmp r3, #1 80055d8: d101 bne.n 80055de 80055da: 2302 movs r3, #2 80055dc: e048 b.n 8005670 80055de: 68fb ldr r3, [r7, #12] 80055e0: 2201 movs r2, #1 80055e2: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 80055e6: 687b ldr r3, [r7, #4] 80055e8: 2b0c cmp r3, #12 80055ea: d839 bhi.n 8005660 80055ec: a201 add r2, pc, #4 @ (adr r2, 80055f4 ) 80055ee: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80055f2: bf00 nop 80055f4: 08005629 .word 0x08005629 80055f8: 08005661 .word 0x08005661 80055fc: 08005661 .word 0x08005661 8005600: 08005661 .word 0x08005661 8005604: 08005637 .word 0x08005637 8005608: 08005661 .word 0x08005661 800560c: 08005661 .word 0x08005661 8005610: 08005661 .word 0x08005661 8005614: 08005645 .word 0x08005645 8005618: 08005661 .word 0x08005661 800561c: 08005661 .word 0x08005661 8005620: 08005661 .word 0x08005661 8005624: 08005653 .word 0x08005653 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8005628: 68fb ldr r3, [r7, #12] 800562a: 681b ldr r3, [r3, #0] 800562c: 68b9 ldr r1, [r7, #8] 800562e: 4618 mov r0, r3 8005630: f000 f8c8 bl 80057c4 break; 8005634: e017 b.n 8005666 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8005636: 68fb ldr r3, [r7, #12] 8005638: 681b ldr r3, [r3, #0] 800563a: 68b9 ldr r1, [r7, #8] 800563c: 4618 mov r0, r3 800563e: f000 f931 bl 80058a4 break; 8005642: e010 b.n 8005666 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8005644: 68fb ldr r3, [r7, #12] 8005646: 681b ldr r3, [r3, #0] 8005648: 68b9 ldr r1, [r7, #8] 800564a: 4618 mov r0, r3 800564c: f000 f9a0 bl 8005990 break; 8005650: e009 b.n 8005666 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8005652: 68fb ldr r3, [r7, #12] 8005654: 681b ldr r3, [r3, #0] 8005656: 68b9 ldr r1, [r7, #8] 8005658: 4618 mov r0, r3 800565a: f000 fa0d bl 8005a78 break; 800565e: e002 b.n 8005666 } default: status = HAL_ERROR; 8005660: 2301 movs r3, #1 8005662: 75fb strb r3, [r7, #23] break; 8005664: bf00 nop } __HAL_UNLOCK(htim); 8005666: 68fb ldr r3, [r7, #12] 8005668: 2200 movs r2, #0 800566a: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800566e: 7dfb ldrb r3, [r7, #23] } 8005670: 4618 mov r0, r3 8005672: 3718 adds r7, #24 8005674: 46bd mov sp, r7 8005676: bd80 pop {r7, pc} 08005678 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8005678: b480 push {r7} 800567a: b085 sub sp, #20 800567c: af00 add r7, sp, #0 800567e: 6078 str r0, [r7, #4] 8005680: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8005682: 687b ldr r3, [r7, #4] 8005684: 681b ldr r3, [r3, #0] 8005686: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8005688: 687b ldr r3, [r7, #4] 800568a: 4a43 ldr r2, [pc, #268] @ (8005798 ) 800568c: 4293 cmp r3, r2 800568e: d013 beq.n 80056b8 8005690: 687b ldr r3, [r7, #4] 8005692: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005696: d00f beq.n 80056b8 8005698: 687b ldr r3, [r7, #4] 800569a: 4a40 ldr r2, [pc, #256] @ (800579c ) 800569c: 4293 cmp r3, r2 800569e: d00b beq.n 80056b8 80056a0: 687b ldr r3, [r7, #4] 80056a2: 4a3f ldr r2, [pc, #252] @ (80057a0 ) 80056a4: 4293 cmp r3, r2 80056a6: d007 beq.n 80056b8 80056a8: 687b ldr r3, [r7, #4] 80056aa: 4a3e ldr r2, [pc, #248] @ (80057a4 ) 80056ac: 4293 cmp r3, r2 80056ae: d003 beq.n 80056b8 80056b0: 687b ldr r3, [r7, #4] 80056b2: 4a3d ldr r2, [pc, #244] @ (80057a8 ) 80056b4: 4293 cmp r3, r2 80056b6: d108 bne.n 80056ca { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80056b8: 68fb ldr r3, [r7, #12] 80056ba: f023 0370 bic.w r3, r3, #112 @ 0x70 80056be: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80056c0: 683b ldr r3, [r7, #0] 80056c2: 685b ldr r3, [r3, #4] 80056c4: 68fa ldr r2, [r7, #12] 80056c6: 4313 orrs r3, r2 80056c8: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80056ca: 687b ldr r3, [r7, #4] 80056cc: 4a32 ldr r2, [pc, #200] @ (8005798 ) 80056ce: 4293 cmp r3, r2 80056d0: d02b beq.n 800572a 80056d2: 687b ldr r3, [r7, #4] 80056d4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80056d8: d027 beq.n 800572a 80056da: 687b ldr r3, [r7, #4] 80056dc: 4a2f ldr r2, [pc, #188] @ (800579c ) 80056de: 4293 cmp r3, r2 80056e0: d023 beq.n 800572a 80056e2: 687b ldr r3, [r7, #4] 80056e4: 4a2e ldr r2, [pc, #184] @ (80057a0 ) 80056e6: 4293 cmp r3, r2 80056e8: d01f beq.n 800572a 80056ea: 687b ldr r3, [r7, #4] 80056ec: 4a2d ldr r2, [pc, #180] @ (80057a4 ) 80056ee: 4293 cmp r3, r2 80056f0: d01b beq.n 800572a 80056f2: 687b ldr r3, [r7, #4] 80056f4: 4a2c ldr r2, [pc, #176] @ (80057a8 ) 80056f6: 4293 cmp r3, r2 80056f8: d017 beq.n 800572a 80056fa: 687b ldr r3, [r7, #4] 80056fc: 4a2b ldr r2, [pc, #172] @ (80057ac ) 80056fe: 4293 cmp r3, r2 8005700: d013 beq.n 800572a 8005702: 687b ldr r3, [r7, #4] 8005704: 4a2a ldr r2, [pc, #168] @ (80057b0 ) 8005706: 4293 cmp r3, r2 8005708: d00f beq.n 800572a 800570a: 687b ldr r3, [r7, #4] 800570c: 4a29 ldr r2, [pc, #164] @ (80057b4 ) 800570e: 4293 cmp r3, r2 8005710: d00b beq.n 800572a 8005712: 687b ldr r3, [r7, #4] 8005714: 4a28 ldr r2, [pc, #160] @ (80057b8 ) 8005716: 4293 cmp r3, r2 8005718: d007 beq.n 800572a 800571a: 687b ldr r3, [r7, #4] 800571c: 4a27 ldr r2, [pc, #156] @ (80057bc ) 800571e: 4293 cmp r3, r2 8005720: d003 beq.n 800572a 8005722: 687b ldr r3, [r7, #4] 8005724: 4a26 ldr r2, [pc, #152] @ (80057c0 ) 8005726: 4293 cmp r3, r2 8005728: d108 bne.n 800573c { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800572a: 68fb ldr r3, [r7, #12] 800572c: f423 7340 bic.w r3, r3, #768 @ 0x300 8005730: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8005732: 683b ldr r3, [r7, #0] 8005734: 68db ldr r3, [r3, #12] 8005736: 68fa ldr r2, [r7, #12] 8005738: 4313 orrs r3, r2 800573a: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800573c: 68fb ldr r3, [r7, #12] 800573e: f023 0280 bic.w r2, r3, #128 @ 0x80 8005742: 683b ldr r3, [r7, #0] 8005744: 695b ldr r3, [r3, #20] 8005746: 4313 orrs r3, r2 8005748: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800574a: 683b ldr r3, [r7, #0] 800574c: 689a ldr r2, [r3, #8] 800574e: 687b ldr r3, [r7, #4] 8005750: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8005752: 683b ldr r3, [r7, #0] 8005754: 681a ldr r2, [r3, #0] 8005756: 687b ldr r3, [r7, #4] 8005758: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800575a: 687b ldr r3, [r7, #4] 800575c: 4a0e ldr r2, [pc, #56] @ (8005798 ) 800575e: 4293 cmp r3, r2 8005760: d003 beq.n 800576a 8005762: 687b ldr r3, [r7, #4] 8005764: 4a10 ldr r2, [pc, #64] @ (80057a8 ) 8005766: 4293 cmp r3, r2 8005768: d103 bne.n 8005772 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800576a: 683b ldr r3, [r7, #0] 800576c: 691a ldr r2, [r3, #16] 800576e: 687b ldr r3, [r7, #4] 8005770: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 8005772: 687b ldr r3, [r7, #4] 8005774: 681b ldr r3, [r3, #0] 8005776: f043 0204 orr.w r2, r3, #4 800577a: 687b ldr r3, [r7, #4] 800577c: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800577e: 687b ldr r3, [r7, #4] 8005780: 2201 movs r2, #1 8005782: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 8005784: 687b ldr r3, [r7, #4] 8005786: 68fa ldr r2, [r7, #12] 8005788: 601a str r2, [r3, #0] } 800578a: bf00 nop 800578c: 3714 adds r7, #20 800578e: 46bd mov sp, r7 8005790: f85d 7b04 ldr.w r7, [sp], #4 8005794: 4770 bx lr 8005796: bf00 nop 8005798: 40010000 .word 0x40010000 800579c: 40000400 .word 0x40000400 80057a0: 40000800 .word 0x40000800 80057a4: 40000c00 .word 0x40000c00 80057a8: 40010400 .word 0x40010400 80057ac: 40014000 .word 0x40014000 80057b0: 40014400 .word 0x40014400 80057b4: 40014800 .word 0x40014800 80057b8: 40001800 .word 0x40001800 80057bc: 40001c00 .word 0x40001c00 80057c0: 40002000 .word 0x40002000 080057c4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80057c4: b480 push {r7} 80057c6: b087 sub sp, #28 80057c8: af00 add r7, sp, #0 80057ca: 6078 str r0, [r7, #4] 80057cc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80057ce: 687b ldr r3, [r7, #4] 80057d0: 6a1b ldr r3, [r3, #32] 80057d2: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80057d4: 687b ldr r3, [r7, #4] 80057d6: 6a1b ldr r3, [r3, #32] 80057d8: f023 0201 bic.w r2, r3, #1 80057dc: 687b ldr r3, [r7, #4] 80057de: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80057e0: 687b ldr r3, [r7, #4] 80057e2: 685b ldr r3, [r3, #4] 80057e4: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80057e6: 687b ldr r3, [r7, #4] 80057e8: 699b ldr r3, [r3, #24] 80057ea: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80057ec: 68fb ldr r3, [r7, #12] 80057ee: f023 0370 bic.w r3, r3, #112 @ 0x70 80057f2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80057f4: 68fb ldr r3, [r7, #12] 80057f6: f023 0303 bic.w r3, r3, #3 80057fa: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80057fc: 683b ldr r3, [r7, #0] 80057fe: 681b ldr r3, [r3, #0] 8005800: 68fa ldr r2, [r7, #12] 8005802: 4313 orrs r3, r2 8005804: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8005806: 697b ldr r3, [r7, #20] 8005808: f023 0302 bic.w r3, r3, #2 800580c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800580e: 683b ldr r3, [r7, #0] 8005810: 689b ldr r3, [r3, #8] 8005812: 697a ldr r2, [r7, #20] 8005814: 4313 orrs r3, r2 8005816: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8005818: 687b ldr r3, [r7, #4] 800581a: 4a20 ldr r2, [pc, #128] @ (800589c ) 800581c: 4293 cmp r3, r2 800581e: d003 beq.n 8005828 8005820: 687b ldr r3, [r7, #4] 8005822: 4a1f ldr r2, [pc, #124] @ (80058a0 ) 8005824: 4293 cmp r3, r2 8005826: d10c bne.n 8005842 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8005828: 697b ldr r3, [r7, #20] 800582a: f023 0308 bic.w r3, r3, #8 800582e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8005830: 683b ldr r3, [r7, #0] 8005832: 68db ldr r3, [r3, #12] 8005834: 697a ldr r2, [r7, #20] 8005836: 4313 orrs r3, r2 8005838: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 800583a: 697b ldr r3, [r7, #20] 800583c: f023 0304 bic.w r3, r3, #4 8005840: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005842: 687b ldr r3, [r7, #4] 8005844: 4a15 ldr r2, [pc, #84] @ (800589c ) 8005846: 4293 cmp r3, r2 8005848: d003 beq.n 8005852 800584a: 687b ldr r3, [r7, #4] 800584c: 4a14 ldr r2, [pc, #80] @ (80058a0 ) 800584e: 4293 cmp r3, r2 8005850: d111 bne.n 8005876 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8005852: 693b ldr r3, [r7, #16] 8005854: f423 7380 bic.w r3, r3, #256 @ 0x100 8005858: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 800585a: 693b ldr r3, [r7, #16] 800585c: f423 7300 bic.w r3, r3, #512 @ 0x200 8005860: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8005862: 683b ldr r3, [r7, #0] 8005864: 695b ldr r3, [r3, #20] 8005866: 693a ldr r2, [r7, #16] 8005868: 4313 orrs r3, r2 800586a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800586c: 683b ldr r3, [r7, #0] 800586e: 699b ldr r3, [r3, #24] 8005870: 693a ldr r2, [r7, #16] 8005872: 4313 orrs r3, r2 8005874: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005876: 687b ldr r3, [r7, #4] 8005878: 693a ldr r2, [r7, #16] 800587a: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800587c: 687b ldr r3, [r7, #4] 800587e: 68fa ldr r2, [r7, #12] 8005880: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8005882: 683b ldr r3, [r7, #0] 8005884: 685a ldr r2, [r3, #4] 8005886: 687b ldr r3, [r7, #4] 8005888: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800588a: 687b ldr r3, [r7, #4] 800588c: 697a ldr r2, [r7, #20] 800588e: 621a str r2, [r3, #32] } 8005890: bf00 nop 8005892: 371c adds r7, #28 8005894: 46bd mov sp, r7 8005896: f85d 7b04 ldr.w r7, [sp], #4 800589a: 4770 bx lr 800589c: 40010000 .word 0x40010000 80058a0: 40010400 .word 0x40010400 080058a4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80058a4: b480 push {r7} 80058a6: b087 sub sp, #28 80058a8: af00 add r7, sp, #0 80058aa: 6078 str r0, [r7, #4] 80058ac: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80058ae: 687b ldr r3, [r7, #4] 80058b0: 6a1b ldr r3, [r3, #32] 80058b2: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80058b4: 687b ldr r3, [r7, #4] 80058b6: 6a1b ldr r3, [r3, #32] 80058b8: f023 0210 bic.w r2, r3, #16 80058bc: 687b ldr r3, [r7, #4] 80058be: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80058c0: 687b ldr r3, [r7, #4] 80058c2: 685b ldr r3, [r3, #4] 80058c4: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80058c6: 687b ldr r3, [r7, #4] 80058c8: 699b ldr r3, [r3, #24] 80058ca: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80058cc: 68fb ldr r3, [r7, #12] 80058ce: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80058d2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80058d4: 68fb ldr r3, [r7, #12] 80058d6: f423 7340 bic.w r3, r3, #768 @ 0x300 80058da: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80058dc: 683b ldr r3, [r7, #0] 80058de: 681b ldr r3, [r3, #0] 80058e0: 021b lsls r3, r3, #8 80058e2: 68fa ldr r2, [r7, #12] 80058e4: 4313 orrs r3, r2 80058e6: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80058e8: 697b ldr r3, [r7, #20] 80058ea: f023 0320 bic.w r3, r3, #32 80058ee: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80058f0: 683b ldr r3, [r7, #0] 80058f2: 689b ldr r3, [r3, #8] 80058f4: 011b lsls r3, r3, #4 80058f6: 697a ldr r2, [r7, #20] 80058f8: 4313 orrs r3, r2 80058fa: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80058fc: 687b ldr r3, [r7, #4] 80058fe: 4a22 ldr r2, [pc, #136] @ (8005988 ) 8005900: 4293 cmp r3, r2 8005902: d003 beq.n 800590c 8005904: 687b ldr r3, [r7, #4] 8005906: 4a21 ldr r2, [pc, #132] @ (800598c ) 8005908: 4293 cmp r3, r2 800590a: d10d bne.n 8005928 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 800590c: 697b ldr r3, [r7, #20] 800590e: f023 0380 bic.w r3, r3, #128 @ 0x80 8005912: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8005914: 683b ldr r3, [r7, #0] 8005916: 68db ldr r3, [r3, #12] 8005918: 011b lsls r3, r3, #4 800591a: 697a ldr r2, [r7, #20] 800591c: 4313 orrs r3, r2 800591e: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8005920: 697b ldr r3, [r7, #20] 8005922: f023 0340 bic.w r3, r3, #64 @ 0x40 8005926: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005928: 687b ldr r3, [r7, #4] 800592a: 4a17 ldr r2, [pc, #92] @ (8005988 ) 800592c: 4293 cmp r3, r2 800592e: d003 beq.n 8005938 8005930: 687b ldr r3, [r7, #4] 8005932: 4a16 ldr r2, [pc, #88] @ (800598c ) 8005934: 4293 cmp r3, r2 8005936: d113 bne.n 8005960 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8005938: 693b ldr r3, [r7, #16] 800593a: f423 6380 bic.w r3, r3, #1024 @ 0x400 800593e: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8005940: 693b ldr r3, [r7, #16] 8005942: f423 6300 bic.w r3, r3, #2048 @ 0x800 8005946: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8005948: 683b ldr r3, [r7, #0] 800594a: 695b ldr r3, [r3, #20] 800594c: 009b lsls r3, r3, #2 800594e: 693a ldr r2, [r7, #16] 8005950: 4313 orrs r3, r2 8005952: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8005954: 683b ldr r3, [r7, #0] 8005956: 699b ldr r3, [r3, #24] 8005958: 009b lsls r3, r3, #2 800595a: 693a ldr r2, [r7, #16] 800595c: 4313 orrs r3, r2 800595e: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005960: 687b ldr r3, [r7, #4] 8005962: 693a ldr r2, [r7, #16] 8005964: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8005966: 687b ldr r3, [r7, #4] 8005968: 68fa ldr r2, [r7, #12] 800596a: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 800596c: 683b ldr r3, [r7, #0] 800596e: 685a ldr r2, [r3, #4] 8005970: 687b ldr r3, [r7, #4] 8005972: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005974: 687b ldr r3, [r7, #4] 8005976: 697a ldr r2, [r7, #20] 8005978: 621a str r2, [r3, #32] } 800597a: bf00 nop 800597c: 371c adds r7, #28 800597e: 46bd mov sp, r7 8005980: f85d 7b04 ldr.w r7, [sp], #4 8005984: 4770 bx lr 8005986: bf00 nop 8005988: 40010000 .word 0x40010000 800598c: 40010400 .word 0x40010400 08005990 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005990: b480 push {r7} 8005992: b087 sub sp, #28 8005994: af00 add r7, sp, #0 8005996: 6078 str r0, [r7, #4] 8005998: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800599a: 687b ldr r3, [r7, #4] 800599c: 6a1b ldr r3, [r3, #32] 800599e: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 80059a0: 687b ldr r3, [r7, #4] 80059a2: 6a1b ldr r3, [r3, #32] 80059a4: f423 7280 bic.w r2, r3, #256 @ 0x100 80059a8: 687b ldr r3, [r7, #4] 80059aa: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80059ac: 687b ldr r3, [r7, #4] 80059ae: 685b ldr r3, [r3, #4] 80059b0: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80059b2: 687b ldr r3, [r7, #4] 80059b4: 69db ldr r3, [r3, #28] 80059b6: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 80059b8: 68fb ldr r3, [r7, #12] 80059ba: f023 0370 bic.w r3, r3, #112 @ 0x70 80059be: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 80059c0: 68fb ldr r3, [r7, #12] 80059c2: f023 0303 bic.w r3, r3, #3 80059c6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80059c8: 683b ldr r3, [r7, #0] 80059ca: 681b ldr r3, [r3, #0] 80059cc: 68fa ldr r2, [r7, #12] 80059ce: 4313 orrs r3, r2 80059d0: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 80059d2: 697b ldr r3, [r7, #20] 80059d4: f423 7300 bic.w r3, r3, #512 @ 0x200 80059d8: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 80059da: 683b ldr r3, [r7, #0] 80059dc: 689b ldr r3, [r3, #8] 80059de: 021b lsls r3, r3, #8 80059e0: 697a ldr r2, [r7, #20] 80059e2: 4313 orrs r3, r2 80059e4: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 80059e6: 687b ldr r3, [r7, #4] 80059e8: 4a21 ldr r2, [pc, #132] @ (8005a70 ) 80059ea: 4293 cmp r3, r2 80059ec: d003 beq.n 80059f6 80059ee: 687b ldr r3, [r7, #4] 80059f0: 4a20 ldr r2, [pc, #128] @ (8005a74 ) 80059f2: 4293 cmp r3, r2 80059f4: d10d bne.n 8005a12 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 80059f6: 697b ldr r3, [r7, #20] 80059f8: f423 6300 bic.w r3, r3, #2048 @ 0x800 80059fc: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 80059fe: 683b ldr r3, [r7, #0] 8005a00: 68db ldr r3, [r3, #12] 8005a02: 021b lsls r3, r3, #8 8005a04: 697a ldr r2, [r7, #20] 8005a06: 4313 orrs r3, r2 8005a08: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8005a0a: 697b ldr r3, [r7, #20] 8005a0c: f423 6380 bic.w r3, r3, #1024 @ 0x400 8005a10: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005a12: 687b ldr r3, [r7, #4] 8005a14: 4a16 ldr r2, [pc, #88] @ (8005a70 ) 8005a16: 4293 cmp r3, r2 8005a18: d003 beq.n 8005a22 8005a1a: 687b ldr r3, [r7, #4] 8005a1c: 4a15 ldr r2, [pc, #84] @ (8005a74 ) 8005a1e: 4293 cmp r3, r2 8005a20: d113 bne.n 8005a4a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8005a22: 693b ldr r3, [r7, #16] 8005a24: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8005a28: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8005a2a: 693b ldr r3, [r7, #16] 8005a2c: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8005a30: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8005a32: 683b ldr r3, [r7, #0] 8005a34: 695b ldr r3, [r3, #20] 8005a36: 011b lsls r3, r3, #4 8005a38: 693a ldr r2, [r7, #16] 8005a3a: 4313 orrs r3, r2 8005a3c: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8005a3e: 683b ldr r3, [r7, #0] 8005a40: 699b ldr r3, [r3, #24] 8005a42: 011b lsls r3, r3, #4 8005a44: 693a ldr r2, [r7, #16] 8005a46: 4313 orrs r3, r2 8005a48: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005a4a: 687b ldr r3, [r7, #4] 8005a4c: 693a ldr r2, [r7, #16] 8005a4e: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8005a50: 687b ldr r3, [r7, #4] 8005a52: 68fa ldr r2, [r7, #12] 8005a54: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8005a56: 683b ldr r3, [r7, #0] 8005a58: 685a ldr r2, [r3, #4] 8005a5a: 687b ldr r3, [r7, #4] 8005a5c: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005a5e: 687b ldr r3, [r7, #4] 8005a60: 697a ldr r2, [r7, #20] 8005a62: 621a str r2, [r3, #32] } 8005a64: bf00 nop 8005a66: 371c adds r7, #28 8005a68: 46bd mov sp, r7 8005a6a: f85d 7b04 ldr.w r7, [sp], #4 8005a6e: 4770 bx lr 8005a70: 40010000 .word 0x40010000 8005a74: 40010400 .word 0x40010400 08005a78 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005a78: b480 push {r7} 8005a7a: b087 sub sp, #28 8005a7c: af00 add r7, sp, #0 8005a7e: 6078 str r0, [r7, #4] 8005a80: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8005a82: 687b ldr r3, [r7, #4] 8005a84: 6a1b ldr r3, [r3, #32] 8005a86: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8005a88: 687b ldr r3, [r7, #4] 8005a8a: 6a1b ldr r3, [r3, #32] 8005a8c: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8005a90: 687b ldr r3, [r7, #4] 8005a92: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005a94: 687b ldr r3, [r7, #4] 8005a96: 685b ldr r3, [r3, #4] 8005a98: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8005a9a: 687b ldr r3, [r7, #4] 8005a9c: 69db ldr r3, [r3, #28] 8005a9e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8005aa0: 68fb ldr r3, [r7, #12] 8005aa2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8005aa6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8005aa8: 68fb ldr r3, [r7, #12] 8005aaa: f423 7340 bic.w r3, r3, #768 @ 0x300 8005aae: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8005ab0: 683b ldr r3, [r7, #0] 8005ab2: 681b ldr r3, [r3, #0] 8005ab4: 021b lsls r3, r3, #8 8005ab6: 68fa ldr r2, [r7, #12] 8005ab8: 4313 orrs r3, r2 8005aba: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8005abc: 693b ldr r3, [r7, #16] 8005abe: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8005ac2: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8005ac4: 683b ldr r3, [r7, #0] 8005ac6: 689b ldr r3, [r3, #8] 8005ac8: 031b lsls r3, r3, #12 8005aca: 693a ldr r2, [r7, #16] 8005acc: 4313 orrs r3, r2 8005ace: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005ad0: 687b ldr r3, [r7, #4] 8005ad2: 4a12 ldr r2, [pc, #72] @ (8005b1c ) 8005ad4: 4293 cmp r3, r2 8005ad6: d003 beq.n 8005ae0 8005ad8: 687b ldr r3, [r7, #4] 8005ada: 4a11 ldr r2, [pc, #68] @ (8005b20 ) 8005adc: 4293 cmp r3, r2 8005ade: d109 bne.n 8005af4 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8005ae0: 697b ldr r3, [r7, #20] 8005ae2: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8005ae6: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8005ae8: 683b ldr r3, [r7, #0] 8005aea: 695b ldr r3, [r3, #20] 8005aec: 019b lsls r3, r3, #6 8005aee: 697a ldr r2, [r7, #20] 8005af0: 4313 orrs r3, r2 8005af2: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005af4: 687b ldr r3, [r7, #4] 8005af6: 697a ldr r2, [r7, #20] 8005af8: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8005afa: 687b ldr r3, [r7, #4] 8005afc: 68fa ldr r2, [r7, #12] 8005afe: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8005b00: 683b ldr r3, [r7, #0] 8005b02: 685a ldr r2, [r3, #4] 8005b04: 687b ldr r3, [r7, #4] 8005b06: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005b08: 687b ldr r3, [r7, #4] 8005b0a: 693a ldr r2, [r7, #16] 8005b0c: 621a str r2, [r3, #32] } 8005b0e: bf00 nop 8005b10: 371c adds r7, #28 8005b12: 46bd mov sp, r7 8005b14: f85d 7b04 ldr.w r7, [sp], #4 8005b18: 4770 bx lr 8005b1a: bf00 nop 8005b1c: 40010000 .word 0x40010000 8005b20: 40010400 .word 0x40010400 08005b24 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8005b24: b480 push {r7} 8005b26: b087 sub sp, #28 8005b28: af00 add r7, sp, #0 8005b2a: 60f8 str r0, [r7, #12] 8005b2c: 60b9 str r1, [r7, #8] 8005b2e: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8005b30: 68bb ldr r3, [r7, #8] 8005b32: f003 031f and.w r3, r3, #31 8005b36: 2201 movs r2, #1 8005b38: fa02 f303 lsl.w r3, r2, r3 8005b3c: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8005b3e: 68fb ldr r3, [r7, #12] 8005b40: 6a1a ldr r2, [r3, #32] 8005b42: 697b ldr r3, [r7, #20] 8005b44: 43db mvns r3, r3 8005b46: 401a ands r2, r3 8005b48: 68fb ldr r3, [r7, #12] 8005b4a: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8005b4c: 68fb ldr r3, [r7, #12] 8005b4e: 6a1a ldr r2, [r3, #32] 8005b50: 68bb ldr r3, [r7, #8] 8005b52: f003 031f and.w r3, r3, #31 8005b56: 6879 ldr r1, [r7, #4] 8005b58: fa01 f303 lsl.w r3, r1, r3 8005b5c: 431a orrs r2, r3 8005b5e: 68fb ldr r3, [r7, #12] 8005b60: 621a str r2, [r3, #32] } 8005b62: bf00 nop 8005b64: 371c adds r7, #28 8005b66: 46bd mov sp, r7 8005b68: f85d 7b04 ldr.w r7, [sp], #4 8005b6c: 4770 bx lr ... 08005b70 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8005b70: b480 push {r7} 8005b72: b085 sub sp, #20 8005b74: af00 add r7, sp, #0 8005b76: 6078 str r0, [r7, #4] 8005b78: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8005b7a: 687b ldr r3, [r7, #4] 8005b7c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005b80: 2b01 cmp r3, #1 8005b82: d101 bne.n 8005b88 8005b84: 2302 movs r3, #2 8005b86: e05a b.n 8005c3e 8005b88: 687b ldr r3, [r7, #4] 8005b8a: 2201 movs r2, #1 8005b8c: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8005b90: 687b ldr r3, [r7, #4] 8005b92: 2202 movs r2, #2 8005b94: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8005b98: 687b ldr r3, [r7, #4] 8005b9a: 681b ldr r3, [r3, #0] 8005b9c: 685b ldr r3, [r3, #4] 8005b9e: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005ba0: 687b ldr r3, [r7, #4] 8005ba2: 681b ldr r3, [r3, #0] 8005ba4: 689b ldr r3, [r3, #8] 8005ba6: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8005ba8: 68fb ldr r3, [r7, #12] 8005baa: f023 0370 bic.w r3, r3, #112 @ 0x70 8005bae: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8005bb0: 683b ldr r3, [r7, #0] 8005bb2: 681b ldr r3, [r3, #0] 8005bb4: 68fa ldr r2, [r7, #12] 8005bb6: 4313 orrs r3, r2 8005bb8: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8005bba: 687b ldr r3, [r7, #4] 8005bbc: 681b ldr r3, [r3, #0] 8005bbe: 68fa ldr r2, [r7, #12] 8005bc0: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005bc2: 687b ldr r3, [r7, #4] 8005bc4: 681b ldr r3, [r3, #0] 8005bc6: 4a21 ldr r2, [pc, #132] @ (8005c4c ) 8005bc8: 4293 cmp r3, r2 8005bca: d022 beq.n 8005c12 8005bcc: 687b ldr r3, [r7, #4] 8005bce: 681b ldr r3, [r3, #0] 8005bd0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005bd4: d01d beq.n 8005c12 8005bd6: 687b ldr r3, [r7, #4] 8005bd8: 681b ldr r3, [r3, #0] 8005bda: 4a1d ldr r2, [pc, #116] @ (8005c50 ) 8005bdc: 4293 cmp r3, r2 8005bde: d018 beq.n 8005c12 8005be0: 687b ldr r3, [r7, #4] 8005be2: 681b ldr r3, [r3, #0] 8005be4: 4a1b ldr r2, [pc, #108] @ (8005c54 ) 8005be6: 4293 cmp r3, r2 8005be8: d013 beq.n 8005c12 8005bea: 687b ldr r3, [r7, #4] 8005bec: 681b ldr r3, [r3, #0] 8005bee: 4a1a ldr r2, [pc, #104] @ (8005c58 ) 8005bf0: 4293 cmp r3, r2 8005bf2: d00e beq.n 8005c12 8005bf4: 687b ldr r3, [r7, #4] 8005bf6: 681b ldr r3, [r3, #0] 8005bf8: 4a18 ldr r2, [pc, #96] @ (8005c5c ) 8005bfa: 4293 cmp r3, r2 8005bfc: d009 beq.n 8005c12 8005bfe: 687b ldr r3, [r7, #4] 8005c00: 681b ldr r3, [r3, #0] 8005c02: 4a17 ldr r2, [pc, #92] @ (8005c60 ) 8005c04: 4293 cmp r3, r2 8005c06: d004 beq.n 8005c12 8005c08: 687b ldr r3, [r7, #4] 8005c0a: 681b ldr r3, [r3, #0] 8005c0c: 4a15 ldr r2, [pc, #84] @ (8005c64 ) 8005c0e: 4293 cmp r3, r2 8005c10: d10c bne.n 8005c2c { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8005c12: 68bb ldr r3, [r7, #8] 8005c14: f023 0380 bic.w r3, r3, #128 @ 0x80 8005c18: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8005c1a: 683b ldr r3, [r7, #0] 8005c1c: 685b ldr r3, [r3, #4] 8005c1e: 68ba ldr r2, [r7, #8] 8005c20: 4313 orrs r3, r2 8005c22: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005c24: 687b ldr r3, [r7, #4] 8005c26: 681b ldr r3, [r3, #0] 8005c28: 68ba ldr r2, [r7, #8] 8005c2a: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8005c2c: 687b ldr r3, [r7, #4] 8005c2e: 2201 movs r2, #1 8005c30: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8005c34: 687b ldr r3, [r7, #4] 8005c36: 2200 movs r2, #0 8005c38: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8005c3c: 2300 movs r3, #0 } 8005c3e: 4618 mov r0, r3 8005c40: 3714 adds r7, #20 8005c42: 46bd mov sp, r7 8005c44: f85d 7b04 ldr.w r7, [sp], #4 8005c48: 4770 bx lr 8005c4a: bf00 nop 8005c4c: 40010000 .word 0x40010000 8005c50: 40000400 .word 0x40000400 8005c54: 40000800 .word 0x40000800 8005c58: 40000c00 .word 0x40000c00 8005c5c: 40010400 .word 0x40010400 8005c60: 40014000 .word 0x40014000 8005c64: 40001800 .word 0x40001800 08005c68 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8005c68: b580 push {r7, lr} 8005c6a: b082 sub sp, #8 8005c6c: af00 add r7, sp, #0 8005c6e: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8005c70: 687b ldr r3, [r7, #4] 8005c72: 2b00 cmp r3, #0 8005c74: d101 bne.n 8005c7a { return HAL_ERROR; 8005c76: 2301 movs r3, #1 8005c78: e042 b.n 8005d00 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 8005c7a: 687b ldr r3, [r7, #4] 8005c7c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005c80: b2db uxtb r3, r3 8005c82: 2b00 cmp r3, #0 8005c84: d106 bne.n 8005c94 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8005c86: 687b ldr r3, [r7, #4] 8005c88: 2200 movs r2, #0 8005c8a: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8005c8e: 6878 ldr r0, [r7, #4] 8005c90: f7fb fba0 bl 80013d4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8005c94: 687b ldr r3, [r7, #4] 8005c96: 2224 movs r2, #36 @ 0x24 8005c98: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8005c9c: 687b ldr r3, [r7, #4] 8005c9e: 681b ldr r3, [r3, #0] 8005ca0: 68da ldr r2, [r3, #12] 8005ca2: 687b ldr r3, [r7, #4] 8005ca4: 681b ldr r3, [r3, #0] 8005ca6: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8005caa: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8005cac: 6878 ldr r0, [r7, #4] 8005cae: f000 ff6d bl 8006b8c /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8005cb2: 687b ldr r3, [r7, #4] 8005cb4: 681b ldr r3, [r3, #0] 8005cb6: 691a ldr r2, [r3, #16] 8005cb8: 687b ldr r3, [r7, #4] 8005cba: 681b ldr r3, [r3, #0] 8005cbc: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8005cc0: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8005cc2: 687b ldr r3, [r7, #4] 8005cc4: 681b ldr r3, [r3, #0] 8005cc6: 695a ldr r2, [r3, #20] 8005cc8: 687b ldr r3, [r7, #4] 8005cca: 681b ldr r3, [r3, #0] 8005ccc: f022 022a bic.w r2, r2, #42 @ 0x2a 8005cd0: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8005cd2: 687b ldr r3, [r7, #4] 8005cd4: 681b ldr r3, [r3, #0] 8005cd6: 68da ldr r2, [r3, #12] 8005cd8: 687b ldr r3, [r7, #4] 8005cda: 681b ldr r3, [r3, #0] 8005cdc: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8005ce0: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005ce2: 687b ldr r3, [r7, #4] 8005ce4: 2200 movs r2, #0 8005ce6: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8005ce8: 687b ldr r3, [r7, #4] 8005cea: 2220 movs r2, #32 8005cec: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8005cf0: 687b ldr r3, [r7, #4] 8005cf2: 2220 movs r2, #32 8005cf4: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8005cf8: 687b ldr r3, [r7, #4] 8005cfa: 2200 movs r2, #0 8005cfc: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8005cfe: 2300 movs r3, #0 } 8005d00: 4618 mov r0, r3 8005d02: 3708 adds r7, #8 8005d04: 46bd mov sp, r7 8005d06: bd80 pop {r7, pc} 08005d08 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8005d08: b580 push {r7, lr} 8005d0a: b08c sub sp, #48 @ 0x30 8005d0c: af00 add r7, sp, #0 8005d0e: 60f8 str r0, [r7, #12] 8005d10: 60b9 str r1, [r7, #8] 8005d12: 4613 mov r3, r2 8005d14: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8005d16: 68fb ldr r3, [r7, #12] 8005d18: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005d1c: b2db uxtb r3, r3 8005d1e: 2b20 cmp r3, #32 8005d20: d162 bne.n 8005de8 { if ((pData == NULL) || (Size == 0U)) 8005d22: 68bb ldr r3, [r7, #8] 8005d24: 2b00 cmp r3, #0 8005d26: d002 beq.n 8005d2e 8005d28: 88fb ldrh r3, [r7, #6] 8005d2a: 2b00 cmp r3, #0 8005d2c: d101 bne.n 8005d32 { return HAL_ERROR; 8005d2e: 2301 movs r3, #1 8005d30: e05b b.n 8005dea } huart->pTxBuffPtr = pData; 8005d32: 68ba ldr r2, [r7, #8] 8005d34: 68fb ldr r3, [r7, #12] 8005d36: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8005d38: 68fb ldr r3, [r7, #12] 8005d3a: 88fa ldrh r2, [r7, #6] 8005d3c: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 8005d3e: 68fb ldr r3, [r7, #12] 8005d40: 88fa ldrh r2, [r7, #6] 8005d42: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8005d44: 68fb ldr r3, [r7, #12] 8005d46: 2200 movs r2, #0 8005d48: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8005d4a: 68fb ldr r3, [r7, #12] 8005d4c: 2221 movs r2, #33 @ 0x21 8005d4e: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 8005d52: 68fb ldr r3, [r7, #12] 8005d54: 6b9b ldr r3, [r3, #56] @ 0x38 8005d56: 4a27 ldr r2, [pc, #156] @ (8005df4 ) 8005d58: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8005d5a: 68fb ldr r3, [r7, #12] 8005d5c: 6b9b ldr r3, [r3, #56] @ 0x38 8005d5e: 4a26 ldr r2, [pc, #152] @ (8005df8 ) 8005d60: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 8005d62: 68fb ldr r3, [r7, #12] 8005d64: 6b9b ldr r3, [r3, #56] @ 0x38 8005d66: 4a25 ldr r2, [pc, #148] @ (8005dfc ) 8005d68: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8005d6a: 68fb ldr r3, [r7, #12] 8005d6c: 6b9b ldr r3, [r3, #56] @ 0x38 8005d6e: 2200 movs r2, #0 8005d70: 651a str r2, [r3, #80] @ 0x50 /* Enable the UART transmit DMA stream */ tmp = (const uint32_t *)&pData; 8005d72: f107 0308 add.w r3, r7, #8 8005d76: 62fb str r3, [r7, #44] @ 0x2c if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK) 8005d78: 68fb ldr r3, [r7, #12] 8005d7a: 6b98 ldr r0, [r3, #56] @ 0x38 8005d7c: 6afb ldr r3, [r7, #44] @ 0x2c 8005d7e: 6819 ldr r1, [r3, #0] 8005d80: 68fb ldr r3, [r7, #12] 8005d82: 681b ldr r3, [r3, #0] 8005d84: 3304 adds r3, #4 8005d86: 461a mov r2, r3 8005d88: 88fb ldrh r3, [r7, #6] 8005d8a: f7fc f865 bl 8001e58 8005d8e: 4603 mov r3, r0 8005d90: 2b00 cmp r3, #0 8005d92: d008 beq.n 8005da6 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8005d94: 68fb ldr r3, [r7, #12] 8005d96: 2210 movs r2, #16 8005d98: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; 8005d9a: 68fb ldr r3, [r7, #12] 8005d9c: 2220 movs r2, #32 8005d9e: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_ERROR; 8005da2: 2301 movs r3, #1 8005da4: e021 b.n 8005dea } /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 8005da6: 68fb ldr r3, [r7, #12] 8005da8: 681b ldr r3, [r3, #0] 8005daa: f06f 0240 mvn.w r2, #64 @ 0x40 8005dae: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8005db0: 68fb ldr r3, [r7, #12] 8005db2: 681b ldr r3, [r3, #0] 8005db4: 3314 adds r3, #20 8005db6: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005db8: 69bb ldr r3, [r7, #24] 8005dba: e853 3f00 ldrex r3, [r3] 8005dbe: 617b str r3, [r7, #20] return(result); 8005dc0: 697b ldr r3, [r7, #20] 8005dc2: f043 0380 orr.w r3, r3, #128 @ 0x80 8005dc6: 62bb str r3, [r7, #40] @ 0x28 8005dc8: 68fb ldr r3, [r7, #12] 8005dca: 681b ldr r3, [r3, #0] 8005dcc: 3314 adds r3, #20 8005dce: 6aba ldr r2, [r7, #40] @ 0x28 8005dd0: 627a str r2, [r7, #36] @ 0x24 8005dd2: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005dd4: 6a39 ldr r1, [r7, #32] 8005dd6: 6a7a ldr r2, [r7, #36] @ 0x24 8005dd8: e841 2300 strex r3, r2, [r1] 8005ddc: 61fb str r3, [r7, #28] return(result); 8005dde: 69fb ldr r3, [r7, #28] 8005de0: 2b00 cmp r3, #0 8005de2: d1e5 bne.n 8005db0 return HAL_OK; 8005de4: 2300 movs r3, #0 8005de6: e000 b.n 8005dea } else { return HAL_BUSY; 8005de8: 2302 movs r3, #2 } } 8005dea: 4618 mov r0, r3 8005dec: 3730 adds r7, #48 @ 0x30 8005dee: 46bd mov sp, r7 8005df0: bd80 pop {r7, pc} 8005df2: bf00 nop 8005df4: 08006409 .word 0x08006409 8005df8: 080064a3 .word 0x080064a3 8005dfc: 08006627 .word 0x08006627 08005e00 : * @param Size Amount of data elements (u8 or u16) to be received. * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8005e00: b580 push {r7, lr} 8005e02: b084 sub sp, #16 8005e04: af00 add r7, sp, #0 8005e06: 60f8 str r0, [r7, #12] 8005e08: 60b9 str r1, [r7, #8] 8005e0a: 4613 mov r3, r2 8005e0c: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8005e0e: 68fb ldr r3, [r7, #12] 8005e10: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8005e14: b2db uxtb r3, r3 8005e16: 2b20 cmp r3, #32 8005e18: d112 bne.n 8005e40 { if ((pData == NULL) || (Size == 0U)) 8005e1a: 68bb ldr r3, [r7, #8] 8005e1c: 2b00 cmp r3, #0 8005e1e: d002 beq.n 8005e26 8005e20: 88fb ldrh r3, [r7, #6] 8005e22: 2b00 cmp r3, #0 8005e24: d101 bne.n 8005e2a { return HAL_ERROR; 8005e26: 2301 movs r3, #1 8005e28: e00b b.n 8005e42 } /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005e2a: 68fb ldr r3, [r7, #12] 8005e2c: 2200 movs r2, #0 8005e2e: 631a str r2, [r3, #48] @ 0x30 return (UART_Start_Receive_DMA(huart, pData, Size)); 8005e30: 88fb ldrh r3, [r7, #6] 8005e32: 461a mov r2, r3 8005e34: 68b9 ldr r1, [r7, #8] 8005e36: 68f8 ldr r0, [r7, #12] 8005e38: f000 fc40 bl 80066bc 8005e3c: 4603 mov r3, r0 8005e3e: e000 b.n 8005e42 } else { return HAL_BUSY; 8005e40: 2302 movs r3, #2 } } 8005e42: 4618 mov r0, r3 8005e44: 3710 adds r7, #16 8005e46: 46bd mov sp, r7 8005e48: bd80 pop {r7, pc} ... 08005e4c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8005e4c: b580 push {r7, lr} 8005e4e: b0ba sub sp, #232 @ 0xe8 8005e50: af00 add r7, sp, #0 8005e52: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8005e54: 687b ldr r3, [r7, #4] 8005e56: 681b ldr r3, [r3, #0] 8005e58: 681b ldr r3, [r3, #0] 8005e5a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8005e5e: 687b ldr r3, [r7, #4] 8005e60: 681b ldr r3, [r3, #0] 8005e62: 68db ldr r3, [r3, #12] 8005e64: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8005e68: 687b ldr r3, [r7, #4] 8005e6a: 681b ldr r3, [r3, #0] 8005e6c: 695b ldr r3, [r3, #20] 8005e6e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8005e72: 2300 movs r3, #0 8005e74: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8005e78: 2300 movs r3, #0 8005e7a: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8005e7e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005e82: f003 030f and.w r3, r3, #15 8005e86: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8005e8a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8005e8e: 2b00 cmp r3, #0 8005e90: d10f bne.n 8005eb2 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005e92: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005e96: f003 0320 and.w r3, r3, #32 8005e9a: 2b00 cmp r3, #0 8005e9c: d009 beq.n 8005eb2 8005e9e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005ea2: f003 0320 and.w r3, r3, #32 8005ea6: 2b00 cmp r3, #0 8005ea8: d003 beq.n 8005eb2 { UART_Receive_IT(huart); 8005eaa: 6878 ldr r0, [r7, #4] 8005eac: f000 fdb0 bl 8006a10 return; 8005eb0: e273 b.n 800639a } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8005eb2: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8005eb6: 2b00 cmp r3, #0 8005eb8: f000 80de beq.w 8006078 8005ebc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005ec0: f003 0301 and.w r3, r3, #1 8005ec4: 2b00 cmp r3, #0 8005ec6: d106 bne.n 8005ed6 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8005ec8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005ecc: f403 7390 and.w r3, r3, #288 @ 0x120 8005ed0: 2b00 cmp r3, #0 8005ed2: f000 80d1 beq.w 8006078 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8005ed6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005eda: f003 0301 and.w r3, r3, #1 8005ede: 2b00 cmp r3, #0 8005ee0: d00b beq.n 8005efa 8005ee2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005ee6: f403 7380 and.w r3, r3, #256 @ 0x100 8005eea: 2b00 cmp r3, #0 8005eec: d005 beq.n 8005efa { huart->ErrorCode |= HAL_UART_ERROR_PE; 8005eee: 687b ldr r3, [r7, #4] 8005ef0: 6c5b ldr r3, [r3, #68] @ 0x44 8005ef2: f043 0201 orr.w r2, r3, #1 8005ef6: 687b ldr r3, [r7, #4] 8005ef8: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005efa: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005efe: f003 0304 and.w r3, r3, #4 8005f02: 2b00 cmp r3, #0 8005f04: d00b beq.n 8005f1e 8005f06: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005f0a: f003 0301 and.w r3, r3, #1 8005f0e: 2b00 cmp r3, #0 8005f10: d005 beq.n 8005f1e { huart->ErrorCode |= HAL_UART_ERROR_NE; 8005f12: 687b ldr r3, [r7, #4] 8005f14: 6c5b ldr r3, [r3, #68] @ 0x44 8005f16: f043 0202 orr.w r2, r3, #2 8005f1a: 687b ldr r3, [r7, #4] 8005f1c: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8005f1e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005f22: f003 0302 and.w r3, r3, #2 8005f26: 2b00 cmp r3, #0 8005f28: d00b beq.n 8005f42 8005f2a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005f2e: f003 0301 and.w r3, r3, #1 8005f32: 2b00 cmp r3, #0 8005f34: d005 beq.n 8005f42 { huart->ErrorCode |= HAL_UART_ERROR_FE; 8005f36: 687b ldr r3, [r7, #4] 8005f38: 6c5b ldr r3, [r3, #68] @ 0x44 8005f3a: f043 0204 orr.w r2, r3, #4 8005f3e: 687b ldr r3, [r7, #4] 8005f40: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8005f42: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005f46: f003 0308 and.w r3, r3, #8 8005f4a: 2b00 cmp r3, #0 8005f4c: d011 beq.n 8005f72 8005f4e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005f52: f003 0320 and.w r3, r3, #32 8005f56: 2b00 cmp r3, #0 8005f58: d105 bne.n 8005f66 || ((cr3its & USART_CR3_EIE) != RESET))) 8005f5a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8005f5e: f003 0301 and.w r3, r3, #1 8005f62: 2b00 cmp r3, #0 8005f64: d005 beq.n 8005f72 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8005f66: 687b ldr r3, [r7, #4] 8005f68: 6c5b ldr r3, [r3, #68] @ 0x44 8005f6a: f043 0208 orr.w r2, r3, #8 8005f6e: 687b ldr r3, [r7, #4] 8005f70: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8005f72: 687b ldr r3, [r7, #4] 8005f74: 6c5b ldr r3, [r3, #68] @ 0x44 8005f76: 2b00 cmp r3, #0 8005f78: f000 820a beq.w 8006390 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005f7c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8005f80: f003 0320 and.w r3, r3, #32 8005f84: 2b00 cmp r3, #0 8005f86: d008 beq.n 8005f9a 8005f88: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005f8c: f003 0320 and.w r3, r3, #32 8005f90: 2b00 cmp r3, #0 8005f92: d002 beq.n 8005f9a { UART_Receive_IT(huart); 8005f94: 6878 ldr r0, [r7, #4] 8005f96: f000 fd3b bl 8006a10 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8005f9a: 687b ldr r3, [r7, #4] 8005f9c: 681b ldr r3, [r3, #0] 8005f9e: 695b ldr r3, [r3, #20] 8005fa0: f003 0340 and.w r3, r3, #64 @ 0x40 8005fa4: 2b40 cmp r3, #64 @ 0x40 8005fa6: bf0c ite eq 8005fa8: 2301 moveq r3, #1 8005faa: 2300 movne r3, #0 8005fac: b2db uxtb r3, r3 8005fae: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8005fb2: 687b ldr r3, [r7, #4] 8005fb4: 6c5b ldr r3, [r3, #68] @ 0x44 8005fb6: f003 0308 and.w r3, r3, #8 8005fba: 2b00 cmp r3, #0 8005fbc: d103 bne.n 8005fc6 8005fbe: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8005fc2: 2b00 cmp r3, #0 8005fc4: d04f beq.n 8006066 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8005fc6: 6878 ldr r0, [r7, #4] 8005fc8: f000 fc46 bl 8006858 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8005fcc: 687b ldr r3, [r7, #4] 8005fce: 681b ldr r3, [r3, #0] 8005fd0: 695b ldr r3, [r3, #20] 8005fd2: f003 0340 and.w r3, r3, #64 @ 0x40 8005fd6: 2b40 cmp r3, #64 @ 0x40 8005fd8: d141 bne.n 800605e { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005fda: 687b ldr r3, [r7, #4] 8005fdc: 681b ldr r3, [r3, #0] 8005fde: 3314 adds r3, #20 8005fe0: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005fe4: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8005fe8: e853 3f00 ldrex r3, [r3] 8005fec: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8005ff0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8005ff4: f023 0340 bic.w r3, r3, #64 @ 0x40 8005ff8: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8005ffc: 687b ldr r3, [r7, #4] 8005ffe: 681b ldr r3, [r3, #0] 8006000: 3314 adds r3, #20 8006002: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8006006: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 800600a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800600e: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8006012: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8006016: e841 2300 strex r3, r2, [r1] 800601a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 800601e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8006022: 2b00 cmp r3, #0 8006024: d1d9 bne.n 8005fda /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) 8006026: 687b ldr r3, [r7, #4] 8006028: 6bdb ldr r3, [r3, #60] @ 0x3c 800602a: 2b00 cmp r3, #0 800602c: d013 beq.n 8006056 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 800602e: 687b ldr r3, [r7, #4] 8006030: 6bdb ldr r3, [r3, #60] @ 0x3c 8006032: 4a8a ldr r2, [pc, #552] @ (800625c ) 8006034: 651a str r2, [r3, #80] @ 0x50 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8006036: 687b ldr r3, [r7, #4] 8006038: 6bdb ldr r3, [r3, #60] @ 0x3c 800603a: 4618 mov r0, r3 800603c: f7fb ffd4 bl 8001fe8 8006040: 4603 mov r3, r0 8006042: 2b00 cmp r3, #0 8006044: d016 beq.n 8006074 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8006046: 687b ldr r3, [r7, #4] 8006048: 6bdb ldr r3, [r3, #60] @ 0x3c 800604a: 6d1b ldr r3, [r3, #80] @ 0x50 800604c: 687a ldr r2, [r7, #4] 800604e: 6bd2 ldr r2, [r2, #60] @ 0x3c 8006050: 4610 mov r0, r2 8006052: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006054: e00e b.n 8006074 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006056: 6878 ldr r0, [r7, #4] 8006058: f000 f9c0 bl 80063dc if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800605c: e00a b.n 8006074 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800605e: 6878 ldr r0, [r7, #4] 8006060: f000 f9bc bl 80063dc if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006064: e006 b.n 8006074 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006066: 6878 ldr r0, [r7, #4] 8006068: f000 f9b8 bl 80063dc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 800606c: 687b ldr r3, [r7, #4] 800606e: 2200 movs r2, #0 8006070: 645a str r2, [r3, #68] @ 0x44 } } return; 8006072: e18d b.n 8006390 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006074: bf00 nop return; 8006076: e18b b.n 8006390 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006078: 687b ldr r3, [r7, #4] 800607a: 6b1b ldr r3, [r3, #48] @ 0x30 800607c: 2b01 cmp r3, #1 800607e: f040 8167 bne.w 8006350 && ((isrflags & USART_SR_IDLE) != 0U) 8006082: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006086: f003 0310 and.w r3, r3, #16 800608a: 2b00 cmp r3, #0 800608c: f000 8160 beq.w 8006350 && ((cr1its & USART_CR1_IDLEIE) != 0U)) 8006090: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006094: f003 0310 and.w r3, r3, #16 8006098: 2b00 cmp r3, #0 800609a: f000 8159 beq.w 8006350 { __HAL_UART_CLEAR_IDLEFLAG(huart); 800609e: 2300 movs r3, #0 80060a0: 60bb str r3, [r7, #8] 80060a2: 687b ldr r3, [r7, #4] 80060a4: 681b ldr r3, [r3, #0] 80060a6: 681b ldr r3, [r3, #0] 80060a8: 60bb str r3, [r7, #8] 80060aa: 687b ldr r3, [r7, #4] 80060ac: 681b ldr r3, [r3, #0] 80060ae: 685b ldr r3, [r3, #4] 80060b0: 60bb str r3, [r7, #8] 80060b2: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80060b4: 687b ldr r3, [r7, #4] 80060b6: 681b ldr r3, [r3, #0] 80060b8: 695b ldr r3, [r3, #20] 80060ba: f003 0340 and.w r3, r3, #64 @ 0x40 80060be: 2b40 cmp r3, #64 @ 0x40 80060c0: f040 80ce bne.w 8006260 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 80060c4: 687b ldr r3, [r7, #4] 80060c6: 6bdb ldr r3, [r3, #60] @ 0x3c 80060c8: 681b ldr r3, [r3, #0] 80060ca: 685b ldr r3, [r3, #4] 80060cc: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 80060d0: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 80060d4: 2b00 cmp r3, #0 80060d6: f000 80a9 beq.w 800622c && (nb_remaining_rx_data < huart->RxXferSize)) 80060da: 687b ldr r3, [r7, #4] 80060dc: 8d9b ldrh r3, [r3, #44] @ 0x2c 80060de: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80060e2: 429a cmp r2, r3 80060e4: f080 80a2 bcs.w 800622c { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 80060e8: 687b ldr r3, [r7, #4] 80060ea: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80060ee: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 80060f0: 687b ldr r3, [r7, #4] 80060f2: 6bdb ldr r3, [r3, #60] @ 0x3c 80060f4: 69db ldr r3, [r3, #28] 80060f6: f5b3 7f80 cmp.w r3, #256 @ 0x100 80060fa: f000 8088 beq.w 800620e { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80060fe: 687b ldr r3, [r7, #4] 8006100: 681b ldr r3, [r3, #0] 8006102: 330c adds r3, #12 8006104: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006108: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800610c: e853 3f00 ldrex r3, [r3] 8006110: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8006114: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8006118: f423 7380 bic.w r3, r3, #256 @ 0x100 800611c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006120: 687b ldr r3, [r7, #4] 8006122: 681b ldr r3, [r3, #0] 8006124: 330c adds r3, #12 8006126: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 800612a: f8c7 2094 str.w r2, [r7, #148] @ 0x94 800612e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006132: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8006136: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 800613a: e841 2300 strex r3, r2, [r1] 800613e: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8006142: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8006146: 2b00 cmp r3, #0 8006148: d1d9 bne.n 80060fe ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800614a: 687b ldr r3, [r7, #4] 800614c: 681b ldr r3, [r3, #0] 800614e: 3314 adds r3, #20 8006150: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006152: 6f7b ldr r3, [r7, #116] @ 0x74 8006154: e853 3f00 ldrex r3, [r3] 8006158: 673b str r3, [r7, #112] @ 0x70 return(result); 800615a: 6f3b ldr r3, [r7, #112] @ 0x70 800615c: f023 0301 bic.w r3, r3, #1 8006160: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8006164: 687b ldr r3, [r7, #4] 8006166: 681b ldr r3, [r3, #0] 8006168: 3314 adds r3, #20 800616a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 800616e: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8006172: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006174: 6ff9 ldr r1, [r7, #124] @ 0x7c 8006176: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 800617a: e841 2300 strex r3, r2, [r1] 800617e: 67bb str r3, [r7, #120] @ 0x78 return(result); 8006180: 6fbb ldr r3, [r7, #120] @ 0x78 8006182: 2b00 cmp r3, #0 8006184: d1e1 bne.n 800614a /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8006186: 687b ldr r3, [r7, #4] 8006188: 681b ldr r3, [r3, #0] 800618a: 3314 adds r3, #20 800618c: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800618e: 6e3b ldr r3, [r7, #96] @ 0x60 8006190: e853 3f00 ldrex r3, [r3] 8006194: 65fb str r3, [r7, #92] @ 0x5c return(result); 8006196: 6dfb ldr r3, [r7, #92] @ 0x5c 8006198: f023 0340 bic.w r3, r3, #64 @ 0x40 800619c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 80061a0: 687b ldr r3, [r7, #4] 80061a2: 681b ldr r3, [r3, #0] 80061a4: 3314 adds r3, #20 80061a6: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 80061aa: 66fa str r2, [r7, #108] @ 0x6c 80061ac: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80061ae: 6eb9 ldr r1, [r7, #104] @ 0x68 80061b0: 6efa ldr r2, [r7, #108] @ 0x6c 80061b2: e841 2300 strex r3, r2, [r1] 80061b6: 667b str r3, [r7, #100] @ 0x64 return(result); 80061b8: 6e7b ldr r3, [r7, #100] @ 0x64 80061ba: 2b00 cmp r3, #0 80061bc: d1e3 bne.n 8006186 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80061be: 687b ldr r3, [r7, #4] 80061c0: 2220 movs r2, #32 80061c2: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80061c6: 687b ldr r3, [r7, #4] 80061c8: 2200 movs r2, #0 80061ca: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80061cc: 687b ldr r3, [r7, #4] 80061ce: 681b ldr r3, [r3, #0] 80061d0: 330c adds r3, #12 80061d2: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80061d4: 6cfb ldr r3, [r7, #76] @ 0x4c 80061d6: e853 3f00 ldrex r3, [r3] 80061da: 64bb str r3, [r7, #72] @ 0x48 return(result); 80061dc: 6cbb ldr r3, [r7, #72] @ 0x48 80061de: f023 0310 bic.w r3, r3, #16 80061e2: f8c7 30ac str.w r3, [r7, #172] @ 0xac 80061e6: 687b ldr r3, [r7, #4] 80061e8: 681b ldr r3, [r3, #0] 80061ea: 330c adds r3, #12 80061ec: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 80061f0: 65ba str r2, [r7, #88] @ 0x58 80061f2: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80061f4: 6d79 ldr r1, [r7, #84] @ 0x54 80061f6: 6dba ldr r2, [r7, #88] @ 0x58 80061f8: e841 2300 strex r3, r2, [r1] 80061fc: 653b str r3, [r7, #80] @ 0x50 return(result); 80061fe: 6d3b ldr r3, [r7, #80] @ 0x50 8006200: 2b00 cmp r3, #0 8006202: d1e3 bne.n 80061cc /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8006204: 687b ldr r3, [r7, #4] 8006206: 6bdb ldr r3, [r3, #60] @ 0x3c 8006208: 4618 mov r0, r3 800620a: f7fb fe7d bl 8001f08 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800620e: 687b ldr r3, [r7, #4] 8006210: 2202 movs r2, #2 8006212: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8006214: 687b ldr r3, [r7, #4] 8006216: 8d9a ldrh r2, [r3, #44] @ 0x2c 8006218: 687b ldr r3, [r7, #4] 800621a: 8ddb ldrh r3, [r3, #46] @ 0x2e 800621c: b29b uxth r3, r3 800621e: 1ad3 subs r3, r2, r3 8006220: b29b uxth r3, r3 8006222: 4619 mov r1, r3 8006224: 6878 ldr r0, [r7, #4] 8006226: f000 f8e3 bl 80063f0 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 800622a: e0b3 b.n 8006394 if (nb_remaining_rx_data == huart->RxXferSize) 800622c: 687b ldr r3, [r7, #4] 800622e: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006230: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8006234: 429a cmp r2, r3 8006236: f040 80ad bne.w 8006394 if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) 800623a: 687b ldr r3, [r7, #4] 800623c: 6bdb ldr r3, [r3, #60] @ 0x3c 800623e: 69db ldr r3, [r3, #28] 8006240: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006244: f040 80a6 bne.w 8006394 huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006248: 687b ldr r3, [r7, #4] 800624a: 2202 movs r2, #2 800624c: 635a str r2, [r3, #52] @ 0x34 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800624e: 687b ldr r3, [r7, #4] 8006250: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006252: 4619 mov r1, r3 8006254: 6878 ldr r0, [r7, #4] 8006256: f000 f8cb bl 80063f0 return; 800625a: e09b b.n 8006394 800625c: 0800691f .word 0x0800691f else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8006260: 687b ldr r3, [r7, #4] 8006262: 8d9a ldrh r2, [r3, #44] @ 0x2c 8006264: 687b ldr r3, [r7, #4] 8006266: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006268: b29b uxth r3, r3 800626a: 1ad3 subs r3, r2, r3 800626c: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8006270: 687b ldr r3, [r7, #4] 8006272: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006274: b29b uxth r3, r3 8006276: 2b00 cmp r3, #0 8006278: f000 808e beq.w 8006398 && (nb_rx_data > 0U)) 800627c: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8006280: 2b00 cmp r3, #0 8006282: f000 8089 beq.w 8006398 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8006286: 687b ldr r3, [r7, #4] 8006288: 681b ldr r3, [r3, #0] 800628a: 330c adds r3, #12 800628c: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800628e: 6bbb ldr r3, [r7, #56] @ 0x38 8006290: e853 3f00 ldrex r3, [r3] 8006294: 637b str r3, [r7, #52] @ 0x34 return(result); 8006296: 6b7b ldr r3, [r7, #52] @ 0x34 8006298: f423 7390 bic.w r3, r3, #288 @ 0x120 800629c: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 80062a0: 687b ldr r3, [r7, #4] 80062a2: 681b ldr r3, [r3, #0] 80062a4: 330c adds r3, #12 80062a6: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 80062aa: 647a str r2, [r7, #68] @ 0x44 80062ac: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80062ae: 6c39 ldr r1, [r7, #64] @ 0x40 80062b0: 6c7a ldr r2, [r7, #68] @ 0x44 80062b2: e841 2300 strex r3, r2, [r1] 80062b6: 63fb str r3, [r7, #60] @ 0x3c return(result); 80062b8: 6bfb ldr r3, [r7, #60] @ 0x3c 80062ba: 2b00 cmp r3, #0 80062bc: d1e3 bne.n 8006286 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80062be: 687b ldr r3, [r7, #4] 80062c0: 681b ldr r3, [r3, #0] 80062c2: 3314 adds r3, #20 80062c4: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80062c6: 6a7b ldr r3, [r7, #36] @ 0x24 80062c8: e853 3f00 ldrex r3, [r3] 80062cc: 623b str r3, [r7, #32] return(result); 80062ce: 6a3b ldr r3, [r7, #32] 80062d0: f023 0301 bic.w r3, r3, #1 80062d4: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 80062d8: 687b ldr r3, [r7, #4] 80062da: 681b ldr r3, [r3, #0] 80062dc: 3314 adds r3, #20 80062de: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80062e2: 633a str r2, [r7, #48] @ 0x30 80062e4: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80062e6: 6af9 ldr r1, [r7, #44] @ 0x2c 80062e8: 6b3a ldr r2, [r7, #48] @ 0x30 80062ea: e841 2300 strex r3, r2, [r1] 80062ee: 62bb str r3, [r7, #40] @ 0x28 return(result); 80062f0: 6abb ldr r3, [r7, #40] @ 0x28 80062f2: 2b00 cmp r3, #0 80062f4: d1e3 bne.n 80062be /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80062f6: 687b ldr r3, [r7, #4] 80062f8: 2220 movs r2, #32 80062fa: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80062fe: 687b ldr r3, [r7, #4] 8006300: 2200 movs r2, #0 8006302: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006304: 687b ldr r3, [r7, #4] 8006306: 681b ldr r3, [r3, #0] 8006308: 330c adds r3, #12 800630a: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800630c: 693b ldr r3, [r7, #16] 800630e: e853 3f00 ldrex r3, [r3] 8006312: 60fb str r3, [r7, #12] return(result); 8006314: 68fb ldr r3, [r7, #12] 8006316: f023 0310 bic.w r3, r3, #16 800631a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800631e: 687b ldr r3, [r7, #4] 8006320: 681b ldr r3, [r3, #0] 8006322: 330c adds r3, #12 8006324: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8006328: 61fa str r2, [r7, #28] 800632a: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800632c: 69b9 ldr r1, [r7, #24] 800632e: 69fa ldr r2, [r7, #28] 8006330: e841 2300 strex r3, r2, [r1] 8006334: 617b str r3, [r7, #20] return(result); 8006336: 697b ldr r3, [r7, #20] 8006338: 2b00 cmp r3, #0 800633a: d1e3 bne.n 8006304 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800633c: 687b ldr r3, [r7, #4] 800633e: 2202 movs r2, #2 8006340: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8006342: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8006346: 4619 mov r1, r3 8006348: 6878 ldr r0, [r7, #4] 800634a: f000 f851 bl 80063f0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 800634e: e023 b.n 8006398 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8006350: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006354: f003 0380 and.w r3, r3, #128 @ 0x80 8006358: 2b00 cmp r3, #0 800635a: d009 beq.n 8006370 800635c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006360: f003 0380 and.w r3, r3, #128 @ 0x80 8006364: 2b00 cmp r3, #0 8006366: d003 beq.n 8006370 { UART_Transmit_IT(huart); 8006368: 6878 ldr r0, [r7, #4] 800636a: f000 fae9 bl 8006940 return; 800636e: e014 b.n 800639a } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8006370: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006374: f003 0340 and.w r3, r3, #64 @ 0x40 8006378: 2b00 cmp r3, #0 800637a: d00e beq.n 800639a 800637c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006380: f003 0340 and.w r3, r3, #64 @ 0x40 8006384: 2b00 cmp r3, #0 8006386: d008 beq.n 800639a { UART_EndTransmit_IT(huart); 8006388: 6878 ldr r0, [r7, #4] 800638a: f000 fb29 bl 80069e0 return; 800638e: e004 b.n 800639a return; 8006390: bf00 nop 8006392: e002 b.n 800639a return; 8006394: bf00 nop 8006396: e000 b.n 800639a return; 8006398: bf00 nop } } 800639a: 37e8 adds r7, #232 @ 0xe8 800639c: 46bd mov sp, r7 800639e: bd80 pop {r7, pc} 080063a0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 80063a0: b480 push {r7} 80063a2: b083 sub sp, #12 80063a4: af00 add r7, sp, #0 80063a6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 80063a8: bf00 nop 80063aa: 370c adds r7, #12 80063ac: 46bd mov sp, r7 80063ae: f85d 7b04 ldr.w r7, [sp], #4 80063b2: 4770 bx lr 080063b4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 80063b4: b480 push {r7} 80063b6: b083 sub sp, #12 80063b8: af00 add r7, sp, #0 80063ba: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 80063bc: bf00 nop 80063be: 370c adds r7, #12 80063c0: 46bd mov sp, r7 80063c2: f85d 7b04 ldr.w r7, [sp], #4 80063c6: 4770 bx lr 080063c8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 80063c8: b480 push {r7} 80063ca: b083 sub sp, #12 80063cc: af00 add r7, sp, #0 80063ce: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 80063d0: bf00 nop 80063d2: 370c adds r7, #12 80063d4: 46bd mov sp, r7 80063d6: f85d 7b04 ldr.w r7, [sp], #4 80063da: 4770 bx lr 080063dc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 80063dc: b480 push {r7} 80063de: b083 sub sp, #12 80063e0: af00 add r7, sp, #0 80063e2: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 80063e4: bf00 nop 80063e6: 370c adds r7, #12 80063e8: 46bd mov sp, r7 80063ea: f85d 7b04 ldr.w r7, [sp], #4 80063ee: 4770 bx lr 080063f0 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 80063f0: b480 push {r7} 80063f2: b083 sub sp, #12 80063f4: af00 add r7, sp, #0 80063f6: 6078 str r0, [r7, #4] 80063f8: 460b mov r3, r1 80063fa: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 80063fc: bf00 nop 80063fe: 370c adds r7, #12 8006400: 46bd mov sp, r7 8006402: f85d 7b04 ldr.w r7, [sp], #4 8006406: 4770 bx lr 08006408 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 8006408: b580 push {r7, lr} 800640a: b090 sub sp, #64 @ 0x40 800640c: af00 add r7, sp, #0 800640e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006410: 687b ldr r3, [r7, #4] 8006412: 6b9b ldr r3, [r3, #56] @ 0x38 8006414: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 8006416: 687b ldr r3, [r7, #4] 8006418: 681b ldr r3, [r3, #0] 800641a: 681b ldr r3, [r3, #0] 800641c: f403 7380 and.w r3, r3, #256 @ 0x100 8006420: 2b00 cmp r3, #0 8006422: d137 bne.n 8006494 { huart->TxXferCount = 0x00U; 8006424: 6bfb ldr r3, [r7, #60] @ 0x3c 8006426: 2200 movs r2, #0 8006428: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 800642a: 6bfb ldr r3, [r7, #60] @ 0x3c 800642c: 681b ldr r3, [r3, #0] 800642e: 3314 adds r3, #20 8006430: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006432: 6a7b ldr r3, [r7, #36] @ 0x24 8006434: e853 3f00 ldrex r3, [r3] 8006438: 623b str r3, [r7, #32] return(result); 800643a: 6a3b ldr r3, [r7, #32] 800643c: f023 0380 bic.w r3, r3, #128 @ 0x80 8006440: 63bb str r3, [r7, #56] @ 0x38 8006442: 6bfb ldr r3, [r7, #60] @ 0x3c 8006444: 681b ldr r3, [r3, #0] 8006446: 3314 adds r3, #20 8006448: 6bba ldr r2, [r7, #56] @ 0x38 800644a: 633a str r2, [r7, #48] @ 0x30 800644c: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800644e: 6af9 ldr r1, [r7, #44] @ 0x2c 8006450: 6b3a ldr r2, [r7, #48] @ 0x30 8006452: e841 2300 strex r3, r2, [r1] 8006456: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006458: 6abb ldr r3, [r7, #40] @ 0x28 800645a: 2b00 cmp r3, #0 800645c: d1e5 bne.n 800642a /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800645e: 6bfb ldr r3, [r7, #60] @ 0x3c 8006460: 681b ldr r3, [r3, #0] 8006462: 330c adds r3, #12 8006464: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006466: 693b ldr r3, [r7, #16] 8006468: e853 3f00 ldrex r3, [r3] 800646c: 60fb str r3, [r7, #12] return(result); 800646e: 68fb ldr r3, [r7, #12] 8006470: f043 0340 orr.w r3, r3, #64 @ 0x40 8006474: 637b str r3, [r7, #52] @ 0x34 8006476: 6bfb ldr r3, [r7, #60] @ 0x3c 8006478: 681b ldr r3, [r3, #0] 800647a: 330c adds r3, #12 800647c: 6b7a ldr r2, [r7, #52] @ 0x34 800647e: 61fa str r2, [r7, #28] 8006480: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006482: 69b9 ldr r1, [r7, #24] 8006484: 69fa ldr r2, [r7, #28] 8006486: e841 2300 strex r3, r2, [r1] 800648a: 617b str r3, [r7, #20] return(result); 800648c: 697b ldr r3, [r7, #20] 800648e: 2b00 cmp r3, #0 8006490: d1e5 bne.n 800645e #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8006492: e002 b.n 800649a HAL_UART_TxCpltCallback(huart); 8006494: 6bf8 ldr r0, [r7, #60] @ 0x3c 8006496: f7ff ff83 bl 80063a0 } 800649a: bf00 nop 800649c: 3740 adds r7, #64 @ 0x40 800649e: 46bd mov sp, r7 80064a0: bd80 pop {r7, pc} 080064a2 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 80064a2: b580 push {r7, lr} 80064a4: b084 sub sp, #16 80064a6: af00 add r7, sp, #0 80064a8: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80064aa: 687b ldr r3, [r7, #4] 80064ac: 6b9b ldr r3, [r3, #56] @ 0x38 80064ae: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 80064b0: 68f8 ldr r0, [r7, #12] 80064b2: f7ff ff7f bl 80063b4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80064b6: bf00 nop 80064b8: 3710 adds r7, #16 80064ba: 46bd mov sp, r7 80064bc: bd80 pop {r7, pc} 080064be : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 80064be: b580 push {r7, lr} 80064c0: b09c sub sp, #112 @ 0x70 80064c2: af00 add r7, sp, #0 80064c4: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80064c6: 687b ldr r3, [r7, #4] 80064c8: 6b9b ldr r3, [r3, #56] @ 0x38 80064ca: 66fb str r3, [r7, #108] @ 0x6c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 80064cc: 687b ldr r3, [r7, #4] 80064ce: 681b ldr r3, [r3, #0] 80064d0: 681b ldr r3, [r3, #0] 80064d2: f403 7380 and.w r3, r3, #256 @ 0x100 80064d6: 2b00 cmp r3, #0 80064d8: d172 bne.n 80065c0 { huart->RxXferCount = 0U; 80064da: 6efb ldr r3, [r7, #108] @ 0x6c 80064dc: 2200 movs r2, #0 80064de: 85da strh r2, [r3, #46] @ 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80064e0: 6efb ldr r3, [r7, #108] @ 0x6c 80064e2: 681b ldr r3, [r3, #0] 80064e4: 330c adds r3, #12 80064e6: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80064e8: 6cfb ldr r3, [r7, #76] @ 0x4c 80064ea: e853 3f00 ldrex r3, [r3] 80064ee: 64bb str r3, [r7, #72] @ 0x48 return(result); 80064f0: 6cbb ldr r3, [r7, #72] @ 0x48 80064f2: f423 7380 bic.w r3, r3, #256 @ 0x100 80064f6: 66bb str r3, [r7, #104] @ 0x68 80064f8: 6efb ldr r3, [r7, #108] @ 0x6c 80064fa: 681b ldr r3, [r3, #0] 80064fc: 330c adds r3, #12 80064fe: 6eba ldr r2, [r7, #104] @ 0x68 8006500: 65ba str r2, [r7, #88] @ 0x58 8006502: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006504: 6d79 ldr r1, [r7, #84] @ 0x54 8006506: 6dba ldr r2, [r7, #88] @ 0x58 8006508: e841 2300 strex r3, r2, [r1] 800650c: 653b str r3, [r7, #80] @ 0x50 return(result); 800650e: 6d3b ldr r3, [r7, #80] @ 0x50 8006510: 2b00 cmp r3, #0 8006512: d1e5 bne.n 80064e0 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006514: 6efb ldr r3, [r7, #108] @ 0x6c 8006516: 681b ldr r3, [r3, #0] 8006518: 3314 adds r3, #20 800651a: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800651c: 6bbb ldr r3, [r7, #56] @ 0x38 800651e: e853 3f00 ldrex r3, [r3] 8006522: 637b str r3, [r7, #52] @ 0x34 return(result); 8006524: 6b7b ldr r3, [r7, #52] @ 0x34 8006526: f023 0301 bic.w r3, r3, #1 800652a: 667b str r3, [r7, #100] @ 0x64 800652c: 6efb ldr r3, [r7, #108] @ 0x6c 800652e: 681b ldr r3, [r3, #0] 8006530: 3314 adds r3, #20 8006532: 6e7a ldr r2, [r7, #100] @ 0x64 8006534: 647a str r2, [r7, #68] @ 0x44 8006536: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006538: 6c39 ldr r1, [r7, #64] @ 0x40 800653a: 6c7a ldr r2, [r7, #68] @ 0x44 800653c: e841 2300 strex r3, r2, [r1] 8006540: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006542: 6bfb ldr r3, [r7, #60] @ 0x3c 8006544: 2b00 cmp r3, #0 8006546: d1e5 bne.n 8006514 /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8006548: 6efb ldr r3, [r7, #108] @ 0x6c 800654a: 681b ldr r3, [r3, #0] 800654c: 3314 adds r3, #20 800654e: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006550: 6a7b ldr r3, [r7, #36] @ 0x24 8006552: e853 3f00 ldrex r3, [r3] 8006556: 623b str r3, [r7, #32] return(result); 8006558: 6a3b ldr r3, [r7, #32] 800655a: f023 0340 bic.w r3, r3, #64 @ 0x40 800655e: 663b str r3, [r7, #96] @ 0x60 8006560: 6efb ldr r3, [r7, #108] @ 0x6c 8006562: 681b ldr r3, [r3, #0] 8006564: 3314 adds r3, #20 8006566: 6e3a ldr r2, [r7, #96] @ 0x60 8006568: 633a str r2, [r7, #48] @ 0x30 800656a: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800656c: 6af9 ldr r1, [r7, #44] @ 0x2c 800656e: 6b3a ldr r2, [r7, #48] @ 0x30 8006570: e841 2300 strex r3, r2, [r1] 8006574: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006576: 6abb ldr r3, [r7, #40] @ 0x28 8006578: 2b00 cmp r3, #0 800657a: d1e5 bne.n 8006548 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800657c: 6efb ldr r3, [r7, #108] @ 0x6c 800657e: 2220 movs r2, #32 8006580: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006584: 6efb ldr r3, [r7, #108] @ 0x6c 8006586: 6b1b ldr r3, [r3, #48] @ 0x30 8006588: 2b01 cmp r3, #1 800658a: d119 bne.n 80065c0 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800658c: 6efb ldr r3, [r7, #108] @ 0x6c 800658e: 681b ldr r3, [r3, #0] 8006590: 330c adds r3, #12 8006592: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006594: 693b ldr r3, [r7, #16] 8006596: e853 3f00 ldrex r3, [r3] 800659a: 60fb str r3, [r7, #12] return(result); 800659c: 68fb ldr r3, [r7, #12] 800659e: f023 0310 bic.w r3, r3, #16 80065a2: 65fb str r3, [r7, #92] @ 0x5c 80065a4: 6efb ldr r3, [r7, #108] @ 0x6c 80065a6: 681b ldr r3, [r3, #0] 80065a8: 330c adds r3, #12 80065aa: 6dfa ldr r2, [r7, #92] @ 0x5c 80065ac: 61fa str r2, [r7, #28] 80065ae: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80065b0: 69b9 ldr r1, [r7, #24] 80065b2: 69fa ldr r2, [r7, #28] 80065b4: e841 2300 strex r3, r2, [r1] 80065b8: 617b str r3, [r7, #20] return(result); 80065ba: 697b ldr r3, [r7, #20] 80065bc: 2b00 cmp r3, #0 80065be: d1e5 bne.n 800658c } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80065c0: 6efb ldr r3, [r7, #108] @ 0x6c 80065c2: 2200 movs r2, #0 80065c4: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80065c6: 6efb ldr r3, [r7, #108] @ 0x6c 80065c8: 6b1b ldr r3, [r3, #48] @ 0x30 80065ca: 2b01 cmp r3, #1 80065cc: d106 bne.n 80065dc #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80065ce: 6efb ldr r3, [r7, #108] @ 0x6c 80065d0: 8d9b ldrh r3, [r3, #44] @ 0x2c 80065d2: 4619 mov r1, r3 80065d4: 6ef8 ldr r0, [r7, #108] @ 0x6c 80065d6: f7ff ff0b bl 80063f0 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 80065da: e002 b.n 80065e2 HAL_UART_RxCpltCallback(huart); 80065dc: 6ef8 ldr r0, [r7, #108] @ 0x6c 80065de: f7fa fa4b bl 8000a78 } 80065e2: bf00 nop 80065e4: 3770 adds r7, #112 @ 0x70 80065e6: 46bd mov sp, r7 80065e8: bd80 pop {r7, pc} 080065ea : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 80065ea: b580 push {r7, lr} 80065ec: b084 sub sp, #16 80065ee: af00 add r7, sp, #0 80065f0: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80065f2: 687b ldr r3, [r7, #4] 80065f4: 6b9b ldr r3, [r3, #56] @ 0x38 80065f6: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 80065f8: 68fb ldr r3, [r7, #12] 80065fa: 2201 movs r2, #1 80065fc: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80065fe: 68fb ldr r3, [r7, #12] 8006600: 6b1b ldr r3, [r3, #48] @ 0x30 8006602: 2b01 cmp r3, #1 8006604: d108 bne.n 8006618 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 8006606: 68fb ldr r3, [r7, #12] 8006608: 8d9b ldrh r3, [r3, #44] @ 0x2c 800660a: 085b lsrs r3, r3, #1 800660c: b29b uxth r3, r3 800660e: 4619 mov r1, r3 8006610: 68f8 ldr r0, [r7, #12] 8006612: f7ff feed bl 80063f0 #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8006616: e002 b.n 800661e HAL_UART_RxHalfCpltCallback(huart); 8006618: 68f8 ldr r0, [r7, #12] 800661a: f7ff fed5 bl 80063c8 } 800661e: bf00 nop 8006620: 3710 adds r7, #16 8006622: 46bd mov sp, r7 8006624: bd80 pop {r7, pc} 08006626 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8006626: b580 push {r7, lr} 8006628: b084 sub sp, #16 800662a: af00 add r7, sp, #0 800662c: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 800662e: 2300 movs r3, #0 8006630: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006632: 687b ldr r3, [r7, #4] 8006634: 6b9b ldr r3, [r3, #56] @ 0x38 8006636: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8006638: 68bb ldr r3, [r7, #8] 800663a: 681b ldr r3, [r3, #0] 800663c: 695b ldr r3, [r3, #20] 800663e: f003 0380 and.w r3, r3, #128 @ 0x80 8006642: 2b80 cmp r3, #128 @ 0x80 8006644: bf0c ite eq 8006646: 2301 moveq r3, #1 8006648: 2300 movne r3, #0 800664a: b2db uxtb r3, r3 800664c: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 800664e: 68bb ldr r3, [r7, #8] 8006650: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8006654: b2db uxtb r3, r3 8006656: 2b21 cmp r3, #33 @ 0x21 8006658: d108 bne.n 800666c 800665a: 68fb ldr r3, [r7, #12] 800665c: 2b00 cmp r3, #0 800665e: d005 beq.n 800666c { huart->TxXferCount = 0x00U; 8006660: 68bb ldr r3, [r7, #8] 8006662: 2200 movs r2, #0 8006664: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 8006666: 68b8 ldr r0, [r7, #8] 8006668: f000 f8ce bl 8006808 } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 800666c: 68bb ldr r3, [r7, #8] 800666e: 681b ldr r3, [r3, #0] 8006670: 695b ldr r3, [r3, #20] 8006672: f003 0340 and.w r3, r3, #64 @ 0x40 8006676: 2b40 cmp r3, #64 @ 0x40 8006678: bf0c ite eq 800667a: 2301 moveq r3, #1 800667c: 2300 movne r3, #0 800667e: b2db uxtb r3, r3 8006680: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8006682: 68bb ldr r3, [r7, #8] 8006684: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8006688: b2db uxtb r3, r3 800668a: 2b22 cmp r3, #34 @ 0x22 800668c: d108 bne.n 80066a0 800668e: 68fb ldr r3, [r7, #12] 8006690: 2b00 cmp r3, #0 8006692: d005 beq.n 80066a0 { huart->RxXferCount = 0x00U; 8006694: 68bb ldr r3, [r7, #8] 8006696: 2200 movs r2, #0 8006698: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 800669a: 68b8 ldr r0, [r7, #8] 800669c: f000 f8dc bl 8006858 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 80066a0: 68bb ldr r3, [r7, #8] 80066a2: 6c5b ldr r3, [r3, #68] @ 0x44 80066a4: f043 0210 orr.w r2, r3, #16 80066a8: 68bb ldr r3, [r7, #8] 80066aa: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80066ac: 68b8 ldr r0, [r7, #8] 80066ae: f7ff fe95 bl 80063dc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80066b2: bf00 nop 80066b4: 3710 adds r7, #16 80066b6: 46bd mov sp, r7 80066b8: bd80 pop {r7, pc} ... 080066bc : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80066bc: b580 push {r7, lr} 80066be: b098 sub sp, #96 @ 0x60 80066c0: af00 add r7, sp, #0 80066c2: 60f8 str r0, [r7, #12] 80066c4: 60b9 str r1, [r7, #8] 80066c6: 4613 mov r3, r2 80066c8: 80fb strh r3, [r7, #6] uint32_t *tmp; huart->pRxBuffPtr = pData; 80066ca: 68ba ldr r2, [r7, #8] 80066cc: 68fb ldr r3, [r7, #12] 80066ce: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 80066d0: 68fb ldr r3, [r7, #12] 80066d2: 88fa ldrh r2, [r7, #6] 80066d4: 859a strh r2, [r3, #44] @ 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 80066d6: 68fb ldr r3, [r7, #12] 80066d8: 2200 movs r2, #0 80066da: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 80066dc: 68fb ldr r3, [r7, #12] 80066de: 2222 movs r2, #34 @ 0x22 80066e0: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 80066e4: 68fb ldr r3, [r7, #12] 80066e6: 6bdb ldr r3, [r3, #60] @ 0x3c 80066e8: 4a44 ldr r2, [pc, #272] @ (80067fc ) 80066ea: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 80066ec: 68fb ldr r3, [r7, #12] 80066ee: 6bdb ldr r3, [r3, #60] @ 0x3c 80066f0: 4a43 ldr r2, [pc, #268] @ (8006800 ) 80066f2: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 80066f4: 68fb ldr r3, [r7, #12] 80066f6: 6bdb ldr r3, [r3, #60] @ 0x3c 80066f8: 4a42 ldr r2, [pc, #264] @ (8006804 ) 80066fa: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 80066fc: 68fb ldr r3, [r7, #12] 80066fe: 6bdb ldr r3, [r3, #60] @ 0x3c 8006700: 2200 movs r2, #0 8006702: 651a str r2, [r3, #80] @ 0x50 /* Enable the DMA stream */ tmp = (uint32_t *)&pData; 8006704: f107 0308 add.w r3, r7, #8 8006708: 65fb str r3, [r7, #92] @ 0x5c if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK) 800670a: 68fb ldr r3, [r7, #12] 800670c: 6bd8 ldr r0, [r3, #60] @ 0x3c 800670e: 68fb ldr r3, [r7, #12] 8006710: 681b ldr r3, [r3, #0] 8006712: 3304 adds r3, #4 8006714: 4619 mov r1, r3 8006716: 6dfb ldr r3, [r7, #92] @ 0x5c 8006718: 681a ldr r2, [r3, #0] 800671a: 88fb ldrh r3, [r7, #6] 800671c: f7fb fb9c bl 8001e58 8006720: 4603 mov r3, r0 8006722: 2b00 cmp r3, #0 8006724: d008 beq.n 8006738 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8006726: 68fb ldr r3, [r7, #12] 8006728: 2210 movs r2, #16 800672a: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; 800672c: 68fb ldr r3, [r7, #12] 800672e: 2220 movs r2, #32 8006730: f883 2042 strb.w r2, [r3, #66] @ 0x42 return HAL_ERROR; 8006734: 2301 movs r3, #1 8006736: e05d b.n 80067f4 } /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 8006738: 2300 movs r3, #0 800673a: 613b str r3, [r7, #16] 800673c: 68fb ldr r3, [r7, #12] 800673e: 681b ldr r3, [r3, #0] 8006740: 681b ldr r3, [r3, #0] 8006742: 613b str r3, [r7, #16] 8006744: 68fb ldr r3, [r7, #12] 8006746: 681b ldr r3, [r3, #0] 8006748: 685b ldr r3, [r3, #4] 800674a: 613b str r3, [r7, #16] 800674c: 693b ldr r3, [r7, #16] if (huart->Init.Parity != UART_PARITY_NONE) 800674e: 68fb ldr r3, [r7, #12] 8006750: 691b ldr r3, [r3, #16] 8006752: 2b00 cmp r3, #0 8006754: d019 beq.n 800678a { /* Enable the UART Parity Error Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006756: 68fb ldr r3, [r7, #12] 8006758: 681b ldr r3, [r3, #0] 800675a: 330c adds r3, #12 800675c: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800675e: 6c3b ldr r3, [r7, #64] @ 0x40 8006760: e853 3f00 ldrex r3, [r3] 8006764: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006766: 6bfb ldr r3, [r7, #60] @ 0x3c 8006768: f443 7380 orr.w r3, r3, #256 @ 0x100 800676c: 65bb str r3, [r7, #88] @ 0x58 800676e: 68fb ldr r3, [r7, #12] 8006770: 681b ldr r3, [r3, #0] 8006772: 330c adds r3, #12 8006774: 6dba ldr r2, [r7, #88] @ 0x58 8006776: 64fa str r2, [r7, #76] @ 0x4c 8006778: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800677a: 6cb9 ldr r1, [r7, #72] @ 0x48 800677c: 6cfa ldr r2, [r7, #76] @ 0x4c 800677e: e841 2300 strex r3, r2, [r1] 8006782: 647b str r3, [r7, #68] @ 0x44 return(result); 8006784: 6c7b ldr r3, [r7, #68] @ 0x44 8006786: 2b00 cmp r3, #0 8006788: d1e5 bne.n 8006756 } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 800678a: 68fb ldr r3, [r7, #12] 800678c: 681b ldr r3, [r3, #0] 800678e: 3314 adds r3, #20 8006790: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006792: 6afb ldr r3, [r7, #44] @ 0x2c 8006794: e853 3f00 ldrex r3, [r3] 8006798: 62bb str r3, [r7, #40] @ 0x28 return(result); 800679a: 6abb ldr r3, [r7, #40] @ 0x28 800679c: f043 0301 orr.w r3, r3, #1 80067a0: 657b str r3, [r7, #84] @ 0x54 80067a2: 68fb ldr r3, [r7, #12] 80067a4: 681b ldr r3, [r3, #0] 80067a6: 3314 adds r3, #20 80067a8: 6d7a ldr r2, [r7, #84] @ 0x54 80067aa: 63ba str r2, [r7, #56] @ 0x38 80067ac: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80067ae: 6b79 ldr r1, [r7, #52] @ 0x34 80067b0: 6bba ldr r2, [r7, #56] @ 0x38 80067b2: e841 2300 strex r3, r2, [r1] 80067b6: 633b str r3, [r7, #48] @ 0x30 return(result); 80067b8: 6b3b ldr r3, [r7, #48] @ 0x30 80067ba: 2b00 cmp r3, #0 80067bc: d1e5 bne.n 800678a /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80067be: 68fb ldr r3, [r7, #12] 80067c0: 681b ldr r3, [r3, #0] 80067c2: 3314 adds r3, #20 80067c4: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80067c6: 69bb ldr r3, [r7, #24] 80067c8: e853 3f00 ldrex r3, [r3] 80067cc: 617b str r3, [r7, #20] return(result); 80067ce: 697b ldr r3, [r7, #20] 80067d0: f043 0340 orr.w r3, r3, #64 @ 0x40 80067d4: 653b str r3, [r7, #80] @ 0x50 80067d6: 68fb ldr r3, [r7, #12] 80067d8: 681b ldr r3, [r3, #0] 80067da: 3314 adds r3, #20 80067dc: 6d3a ldr r2, [r7, #80] @ 0x50 80067de: 627a str r2, [r7, #36] @ 0x24 80067e0: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80067e2: 6a39 ldr r1, [r7, #32] 80067e4: 6a7a ldr r2, [r7, #36] @ 0x24 80067e6: e841 2300 strex r3, r2, [r1] 80067ea: 61fb str r3, [r7, #28] return(result); 80067ec: 69fb ldr r3, [r7, #28] 80067ee: 2b00 cmp r3, #0 80067f0: d1e5 bne.n 80067be return HAL_OK; 80067f2: 2300 movs r3, #0 } 80067f4: 4618 mov r0, r3 80067f6: 3760 adds r7, #96 @ 0x60 80067f8: 46bd mov sp, r7 80067fa: bd80 pop {r7, pc} 80067fc: 080064bf .word 0x080064bf 8006800: 080065eb .word 0x080065eb 8006804: 08006627 .word 0x08006627 08006808 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 8006808: b480 push {r7} 800680a: b089 sub sp, #36 @ 0x24 800680c: af00 add r7, sp, #0 800680e: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 8006810: 687b ldr r3, [r7, #4] 8006812: 681b ldr r3, [r3, #0] 8006814: 330c adds r3, #12 8006816: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006818: 68fb ldr r3, [r7, #12] 800681a: e853 3f00 ldrex r3, [r3] 800681e: 60bb str r3, [r7, #8] return(result); 8006820: 68bb ldr r3, [r7, #8] 8006822: f023 03c0 bic.w r3, r3, #192 @ 0xc0 8006826: 61fb str r3, [r7, #28] 8006828: 687b ldr r3, [r7, #4] 800682a: 681b ldr r3, [r3, #0] 800682c: 330c adds r3, #12 800682e: 69fa ldr r2, [r7, #28] 8006830: 61ba str r2, [r7, #24] 8006832: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006834: 6979 ldr r1, [r7, #20] 8006836: 69ba ldr r2, [r7, #24] 8006838: e841 2300 strex r3, r2, [r1] 800683c: 613b str r3, [r7, #16] return(result); 800683e: 693b ldr r3, [r7, #16] 8006840: 2b00 cmp r3, #0 8006842: d1e5 bne.n 8006810 /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8006844: 687b ldr r3, [r7, #4] 8006846: 2220 movs r2, #32 8006848: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 800684c: bf00 nop 800684e: 3724 adds r7, #36 @ 0x24 8006850: 46bd mov sp, r7 8006852: f85d 7b04 ldr.w r7, [sp], #4 8006856: 4770 bx lr 08006858 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8006858: b480 push {r7} 800685a: b095 sub sp, #84 @ 0x54 800685c: af00 add r7, sp, #0 800685e: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8006860: 687b ldr r3, [r7, #4] 8006862: 681b ldr r3, [r3, #0] 8006864: 330c adds r3, #12 8006866: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006868: 6b7b ldr r3, [r7, #52] @ 0x34 800686a: e853 3f00 ldrex r3, [r3] 800686e: 633b str r3, [r7, #48] @ 0x30 return(result); 8006870: 6b3b ldr r3, [r7, #48] @ 0x30 8006872: f423 7390 bic.w r3, r3, #288 @ 0x120 8006876: 64fb str r3, [r7, #76] @ 0x4c 8006878: 687b ldr r3, [r7, #4] 800687a: 681b ldr r3, [r3, #0] 800687c: 330c adds r3, #12 800687e: 6cfa ldr r2, [r7, #76] @ 0x4c 8006880: 643a str r2, [r7, #64] @ 0x40 8006882: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006884: 6bf9 ldr r1, [r7, #60] @ 0x3c 8006886: 6c3a ldr r2, [r7, #64] @ 0x40 8006888: e841 2300 strex r3, r2, [r1] 800688c: 63bb str r3, [r7, #56] @ 0x38 return(result); 800688e: 6bbb ldr r3, [r7, #56] @ 0x38 8006890: 2b00 cmp r3, #0 8006892: d1e5 bne.n 8006860 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006894: 687b ldr r3, [r7, #4] 8006896: 681b ldr r3, [r3, #0] 8006898: 3314 adds r3, #20 800689a: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800689c: 6a3b ldr r3, [r7, #32] 800689e: e853 3f00 ldrex r3, [r3] 80068a2: 61fb str r3, [r7, #28] return(result); 80068a4: 69fb ldr r3, [r7, #28] 80068a6: f023 0301 bic.w r3, r3, #1 80068aa: 64bb str r3, [r7, #72] @ 0x48 80068ac: 687b ldr r3, [r7, #4] 80068ae: 681b ldr r3, [r3, #0] 80068b0: 3314 adds r3, #20 80068b2: 6cba ldr r2, [r7, #72] @ 0x48 80068b4: 62fa str r2, [r7, #44] @ 0x2c 80068b6: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80068b8: 6ab9 ldr r1, [r7, #40] @ 0x28 80068ba: 6afa ldr r2, [r7, #44] @ 0x2c 80068bc: e841 2300 strex r3, r2, [r1] 80068c0: 627b str r3, [r7, #36] @ 0x24 return(result); 80068c2: 6a7b ldr r3, [r7, #36] @ 0x24 80068c4: 2b00 cmp r3, #0 80068c6: d1e5 bne.n 8006894 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80068c8: 687b ldr r3, [r7, #4] 80068ca: 6b1b ldr r3, [r3, #48] @ 0x30 80068cc: 2b01 cmp r3, #1 80068ce: d119 bne.n 8006904 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80068d0: 687b ldr r3, [r7, #4] 80068d2: 681b ldr r3, [r3, #0] 80068d4: 330c adds r3, #12 80068d6: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80068d8: 68fb ldr r3, [r7, #12] 80068da: e853 3f00 ldrex r3, [r3] 80068de: 60bb str r3, [r7, #8] return(result); 80068e0: 68bb ldr r3, [r7, #8] 80068e2: f023 0310 bic.w r3, r3, #16 80068e6: 647b str r3, [r7, #68] @ 0x44 80068e8: 687b ldr r3, [r7, #4] 80068ea: 681b ldr r3, [r3, #0] 80068ec: 330c adds r3, #12 80068ee: 6c7a ldr r2, [r7, #68] @ 0x44 80068f0: 61ba str r2, [r7, #24] 80068f2: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80068f4: 6979 ldr r1, [r7, #20] 80068f6: 69ba ldr r2, [r7, #24] 80068f8: e841 2300 strex r3, r2, [r1] 80068fc: 613b str r3, [r7, #16] return(result); 80068fe: 693b ldr r3, [r7, #16] 8006900: 2b00 cmp r3, #0 8006902: d1e5 bne.n 80068d0 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006904: 687b ldr r3, [r7, #4] 8006906: 2220 movs r2, #32 8006908: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800690c: 687b ldr r3, [r7, #4] 800690e: 2200 movs r2, #0 8006910: 631a str r2, [r3, #48] @ 0x30 } 8006912: bf00 nop 8006914: 3754 adds r7, #84 @ 0x54 8006916: 46bd mov sp, r7 8006918: f85d 7b04 ldr.w r7, [sp], #4 800691c: 4770 bx lr 0800691e : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 800691e: b580 push {r7, lr} 8006920: b084 sub sp, #16 8006922: af00 add r7, sp, #0 8006924: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006926: 687b ldr r3, [r7, #4] 8006928: 6b9b ldr r3, [r3, #56] @ 0x38 800692a: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 800692c: 68fb ldr r3, [r7, #12] 800692e: 2200 movs r2, #0 8006930: 85da strh r2, [r3, #46] @ 0x2e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006932: 68f8 ldr r0, [r7, #12] 8006934: f7ff fd52 bl 80063dc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006938: bf00 nop 800693a: 3710 adds r7, #16 800693c: 46bd mov sp, r7 800693e: bd80 pop {r7, pc} 08006940 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8006940: b480 push {r7} 8006942: b085 sub sp, #20 8006944: af00 add r7, sp, #0 8006946: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8006948: 687b ldr r3, [r7, #4] 800694a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800694e: b2db uxtb r3, r3 8006950: 2b21 cmp r3, #33 @ 0x21 8006952: d13e bne.n 80069d2 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006954: 687b ldr r3, [r7, #4] 8006956: 689b ldr r3, [r3, #8] 8006958: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800695c: d114 bne.n 8006988 800695e: 687b ldr r3, [r7, #4] 8006960: 691b ldr r3, [r3, #16] 8006962: 2b00 cmp r3, #0 8006964: d110 bne.n 8006988 { tmp = (const uint16_t *) huart->pTxBuffPtr; 8006966: 687b ldr r3, [r7, #4] 8006968: 6a1b ldr r3, [r3, #32] 800696a: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 800696c: 68fb ldr r3, [r7, #12] 800696e: 881b ldrh r3, [r3, #0] 8006970: 461a mov r2, r3 8006972: 687b ldr r3, [r7, #4] 8006974: 681b ldr r3, [r3, #0] 8006976: f3c2 0208 ubfx r2, r2, #0, #9 800697a: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 800697c: 687b ldr r3, [r7, #4] 800697e: 6a1b ldr r3, [r3, #32] 8006980: 1c9a adds r2, r3, #2 8006982: 687b ldr r3, [r7, #4] 8006984: 621a str r2, [r3, #32] 8006986: e008 b.n 800699a } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8006988: 687b ldr r3, [r7, #4] 800698a: 6a1b ldr r3, [r3, #32] 800698c: 1c59 adds r1, r3, #1 800698e: 687a ldr r2, [r7, #4] 8006990: 6211 str r1, [r2, #32] 8006992: 781a ldrb r2, [r3, #0] 8006994: 687b ldr r3, [r7, #4] 8006996: 681b ldr r3, [r3, #0] 8006998: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 800699a: 687b ldr r3, [r7, #4] 800699c: 8cdb ldrh r3, [r3, #38] @ 0x26 800699e: b29b uxth r3, r3 80069a0: 3b01 subs r3, #1 80069a2: b29b uxth r3, r3 80069a4: 687a ldr r2, [r7, #4] 80069a6: 4619 mov r1, r3 80069a8: 84d1 strh r1, [r2, #38] @ 0x26 80069aa: 2b00 cmp r3, #0 80069ac: d10f bne.n 80069ce { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 80069ae: 687b ldr r3, [r7, #4] 80069b0: 681b ldr r3, [r3, #0] 80069b2: 68da ldr r2, [r3, #12] 80069b4: 687b ldr r3, [r7, #4] 80069b6: 681b ldr r3, [r3, #0] 80069b8: f022 0280 bic.w r2, r2, #128 @ 0x80 80069bc: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 80069be: 687b ldr r3, [r7, #4] 80069c0: 681b ldr r3, [r3, #0] 80069c2: 68da ldr r2, [r3, #12] 80069c4: 687b ldr r3, [r7, #4] 80069c6: 681b ldr r3, [r3, #0] 80069c8: f042 0240 orr.w r2, r2, #64 @ 0x40 80069cc: 60da str r2, [r3, #12] } return HAL_OK; 80069ce: 2300 movs r3, #0 80069d0: e000 b.n 80069d4 } else { return HAL_BUSY; 80069d2: 2302 movs r3, #2 } } 80069d4: 4618 mov r0, r3 80069d6: 3714 adds r7, #20 80069d8: 46bd mov sp, r7 80069da: f85d 7b04 ldr.w r7, [sp], #4 80069de: 4770 bx lr 080069e0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80069e0: b580 push {r7, lr} 80069e2: b082 sub sp, #8 80069e4: af00 add r7, sp, #0 80069e6: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 80069e8: 687b ldr r3, [r7, #4] 80069ea: 681b ldr r3, [r3, #0] 80069ec: 68da ldr r2, [r3, #12] 80069ee: 687b ldr r3, [r7, #4] 80069f0: 681b ldr r3, [r3, #0] 80069f2: f022 0240 bic.w r2, r2, #64 @ 0x40 80069f6: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80069f8: 687b ldr r3, [r7, #4] 80069fa: 2220 movs r2, #32 80069fc: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8006a00: 6878 ldr r0, [r7, #4] 8006a02: f7ff fccd bl 80063a0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8006a06: 2300 movs r3, #0 } 8006a08: 4618 mov r0, r3 8006a0a: 3708 adds r7, #8 8006a0c: 46bd mov sp, r7 8006a0e: bd80 pop {r7, pc} 08006a10 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8006a10: b580 push {r7, lr} 8006a12: b08c sub sp, #48 @ 0x30 8006a14: af00 add r7, sp, #0 8006a16: 6078 str r0, [r7, #4] uint8_t *pdata8bits = NULL; 8006a18: 2300 movs r3, #0 8006a1a: 62fb str r3, [r7, #44] @ 0x2c uint16_t *pdata16bits = NULL; 8006a1c: 2300 movs r3, #0 8006a1e: 62bb str r3, [r7, #40] @ 0x28 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8006a20: 687b ldr r3, [r7, #4] 8006a22: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8006a26: b2db uxtb r3, r3 8006a28: 2b22 cmp r3, #34 @ 0x22 8006a2a: f040 80aa bne.w 8006b82 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006a2e: 687b ldr r3, [r7, #4] 8006a30: 689b ldr r3, [r3, #8] 8006a32: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006a36: d115 bne.n 8006a64 8006a38: 687b ldr r3, [r7, #4] 8006a3a: 691b ldr r3, [r3, #16] 8006a3c: 2b00 cmp r3, #0 8006a3e: d111 bne.n 8006a64 { /* Unused pdata8bits */ UNUSED(pdata8bits); pdata16bits = (uint16_t *) huart->pRxBuffPtr; 8006a40: 687b ldr r3, [r7, #4] 8006a42: 6a9b ldr r3, [r3, #40] @ 0x28 8006a44: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8006a46: 687b ldr r3, [r7, #4] 8006a48: 681b ldr r3, [r3, #0] 8006a4a: 685b ldr r3, [r3, #4] 8006a4c: b29b uxth r3, r3 8006a4e: f3c3 0308 ubfx r3, r3, #0, #9 8006a52: b29a uxth r2, r3 8006a54: 6abb ldr r3, [r7, #40] @ 0x28 8006a56: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8006a58: 687b ldr r3, [r7, #4] 8006a5a: 6a9b ldr r3, [r3, #40] @ 0x28 8006a5c: 1c9a adds r2, r3, #2 8006a5e: 687b ldr r3, [r7, #4] 8006a60: 629a str r2, [r3, #40] @ 0x28 8006a62: e024 b.n 8006aae } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8006a64: 687b ldr r3, [r7, #4] 8006a66: 6a9b ldr r3, [r3, #40] @ 0x28 8006a68: 62fb str r3, [r7, #44] @ 0x2c /* Unused pdata16bits */ UNUSED(pdata16bits); if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8006a6a: 687b ldr r3, [r7, #4] 8006a6c: 689b ldr r3, [r3, #8] 8006a6e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006a72: d007 beq.n 8006a84 8006a74: 687b ldr r3, [r7, #4] 8006a76: 689b ldr r3, [r3, #8] 8006a78: 2b00 cmp r3, #0 8006a7a: d10a bne.n 8006a92 8006a7c: 687b ldr r3, [r7, #4] 8006a7e: 691b ldr r3, [r3, #16] 8006a80: 2b00 cmp r3, #0 8006a82: d106 bne.n 8006a92 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8006a84: 687b ldr r3, [r7, #4] 8006a86: 681b ldr r3, [r3, #0] 8006a88: 685b ldr r3, [r3, #4] 8006a8a: b2da uxtb r2, r3 8006a8c: 6afb ldr r3, [r7, #44] @ 0x2c 8006a8e: 701a strb r2, [r3, #0] 8006a90: e008 b.n 8006aa4 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8006a92: 687b ldr r3, [r7, #4] 8006a94: 681b ldr r3, [r3, #0] 8006a96: 685b ldr r3, [r3, #4] 8006a98: b2db uxtb r3, r3 8006a9a: f003 037f and.w r3, r3, #127 @ 0x7f 8006a9e: b2da uxtb r2, r3 8006aa0: 6afb ldr r3, [r7, #44] @ 0x2c 8006aa2: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8006aa4: 687b ldr r3, [r7, #4] 8006aa6: 6a9b ldr r3, [r3, #40] @ 0x28 8006aa8: 1c5a adds r2, r3, #1 8006aaa: 687b ldr r3, [r7, #4] 8006aac: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8006aae: 687b ldr r3, [r7, #4] 8006ab0: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006ab2: b29b uxth r3, r3 8006ab4: 3b01 subs r3, #1 8006ab6: b29b uxth r3, r3 8006ab8: 687a ldr r2, [r7, #4] 8006aba: 4619 mov r1, r3 8006abc: 85d1 strh r1, [r2, #46] @ 0x2e 8006abe: 2b00 cmp r3, #0 8006ac0: d15d bne.n 8006b7e { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8006ac2: 687b ldr r3, [r7, #4] 8006ac4: 681b ldr r3, [r3, #0] 8006ac6: 68da ldr r2, [r3, #12] 8006ac8: 687b ldr r3, [r7, #4] 8006aca: 681b ldr r3, [r3, #0] 8006acc: f022 0220 bic.w r2, r2, #32 8006ad0: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8006ad2: 687b ldr r3, [r7, #4] 8006ad4: 681b ldr r3, [r3, #0] 8006ad6: 68da ldr r2, [r3, #12] 8006ad8: 687b ldr r3, [r7, #4] 8006ada: 681b ldr r3, [r3, #0] 8006adc: f422 7280 bic.w r2, r2, #256 @ 0x100 8006ae0: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8006ae2: 687b ldr r3, [r7, #4] 8006ae4: 681b ldr r3, [r3, #0] 8006ae6: 695a ldr r2, [r3, #20] 8006ae8: 687b ldr r3, [r7, #4] 8006aea: 681b ldr r3, [r3, #0] 8006aec: f022 0201 bic.w r2, r2, #1 8006af0: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006af2: 687b ldr r3, [r7, #4] 8006af4: 2220 movs r2, #32 8006af6: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8006afa: 687b ldr r3, [r7, #4] 8006afc: 2200 movs r2, #0 8006afe: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006b00: 687b ldr r3, [r7, #4] 8006b02: 6b1b ldr r3, [r3, #48] @ 0x30 8006b04: 2b01 cmp r3, #1 8006b06: d135 bne.n 8006b74 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006b08: 687b ldr r3, [r7, #4] 8006b0a: 2200 movs r2, #0 8006b0c: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006b0e: 687b ldr r3, [r7, #4] 8006b10: 681b ldr r3, [r3, #0] 8006b12: 330c adds r3, #12 8006b14: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006b16: 697b ldr r3, [r7, #20] 8006b18: e853 3f00 ldrex r3, [r3] 8006b1c: 613b str r3, [r7, #16] return(result); 8006b1e: 693b ldr r3, [r7, #16] 8006b20: f023 0310 bic.w r3, r3, #16 8006b24: 627b str r3, [r7, #36] @ 0x24 8006b26: 687b ldr r3, [r7, #4] 8006b28: 681b ldr r3, [r3, #0] 8006b2a: 330c adds r3, #12 8006b2c: 6a7a ldr r2, [r7, #36] @ 0x24 8006b2e: 623a str r2, [r7, #32] 8006b30: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006b32: 69f9 ldr r1, [r7, #28] 8006b34: 6a3a ldr r2, [r7, #32] 8006b36: e841 2300 strex r3, r2, [r1] 8006b3a: 61bb str r3, [r7, #24] return(result); 8006b3c: 69bb ldr r3, [r7, #24] 8006b3e: 2b00 cmp r3, #0 8006b40: d1e5 bne.n 8006b0e /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 8006b42: 687b ldr r3, [r7, #4] 8006b44: 681b ldr r3, [r3, #0] 8006b46: 681b ldr r3, [r3, #0] 8006b48: f003 0310 and.w r3, r3, #16 8006b4c: 2b10 cmp r3, #16 8006b4e: d10a bne.n 8006b66 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 8006b50: 2300 movs r3, #0 8006b52: 60fb str r3, [r7, #12] 8006b54: 687b ldr r3, [r7, #4] 8006b56: 681b ldr r3, [r3, #0] 8006b58: 681b ldr r3, [r3, #0] 8006b5a: 60fb str r3, [r7, #12] 8006b5c: 687b ldr r3, [r7, #4] 8006b5e: 681b ldr r3, [r3, #0] 8006b60: 685b ldr r3, [r3, #4] 8006b62: 60fb str r3, [r7, #12] 8006b64: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006b66: 687b ldr r3, [r7, #4] 8006b68: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006b6a: 4619 mov r1, r3 8006b6c: 6878 ldr r0, [r7, #4] 8006b6e: f7ff fc3f bl 80063f0 8006b72: e002 b.n 8006b7a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8006b74: 6878 ldr r0, [r7, #4] 8006b76: f7f9 ff7f bl 8000a78 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8006b7a: 2300 movs r3, #0 8006b7c: e002 b.n 8006b84 } return HAL_OK; 8006b7e: 2300 movs r3, #0 8006b80: e000 b.n 8006b84 } else { return HAL_BUSY; 8006b82: 2302 movs r3, #2 } } 8006b84: 4618 mov r0, r3 8006b86: 3730 adds r7, #48 @ 0x30 8006b88: 46bd mov sp, r7 8006b8a: bd80 pop {r7, pc} 08006b8c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8006b8c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8006b90: b0c0 sub sp, #256 @ 0x100 8006b92: af00 add r7, sp, #0 8006b94: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4 assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8006b98: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006b9c: 681b ldr r3, [r3, #0] 8006b9e: 691b ldr r3, [r3, #16] 8006ba0: f423 5040 bic.w r0, r3, #12288 @ 0x3000 8006ba4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006ba8: 68d9 ldr r1, [r3, #12] 8006baa: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006bae: 681a ldr r2, [r3, #0] 8006bb0: ea40 0301 orr.w r3, r0, r1 8006bb4: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 8006bb6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006bba: 689a ldr r2, [r3, #8] 8006bbc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006bc0: 691b ldr r3, [r3, #16] 8006bc2: 431a orrs r2, r3 8006bc4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006bc8: 695b ldr r3, [r3, #20] 8006bca: 431a orrs r2, r3 8006bcc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006bd0: 69db ldr r3, [r3, #28] 8006bd2: 4313 orrs r3, r2 8006bd4: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 MODIFY_REG(huart->Instance->CR1, 8006bd8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006bdc: 681b ldr r3, [r3, #0] 8006bde: 68db ldr r3, [r3, #12] 8006be0: f423 4116 bic.w r1, r3, #38400 @ 0x9600 8006be4: f021 010c bic.w r1, r1, #12 8006be8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006bec: 681a ldr r2, [r3, #0] 8006bee: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 8006bf2: 430b orrs r3, r1 8006bf4: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8006bf6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006bfa: 681b ldr r3, [r3, #0] 8006bfc: 695b ldr r3, [r3, #20] 8006bfe: f423 7040 bic.w r0, r3, #768 @ 0x300 8006c02: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006c06: 6999 ldr r1, [r3, #24] 8006c08: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006c0c: 681a ldr r2, [r3, #0] 8006c0e: ea40 0301 orr.w r3, r0, r1 8006c12: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 8006c14: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006c18: 681a ldr r2, [r3, #0] 8006c1a: 4b8f ldr r3, [pc, #572] @ (8006e58 ) 8006c1c: 429a cmp r2, r3 8006c1e: d005 beq.n 8006c2c 8006c20: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006c24: 681a ldr r2, [r3, #0] 8006c26: 4b8d ldr r3, [pc, #564] @ (8006e5c ) 8006c28: 429a cmp r2, r3 8006c2a: d104 bne.n 8006c36 { pclk = HAL_RCC_GetPCLK2Freq(); 8006c2c: f7fd fafe bl 800422c 8006c30: f8c7 00fc str.w r0, [r7, #252] @ 0xfc 8006c34: e003 b.n 8006c3e pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); 8006c36: f7fd fae5 bl 8004204 8006c3a: f8c7 00fc str.w r0, [r7, #252] @ 0xfc } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8006c3e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006c42: 69db ldr r3, [r3, #28] 8006c44: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8006c48: f040 810c bne.w 8006e64 { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8006c4c: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006c50: 2200 movs r2, #0 8006c52: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 8006c56: f8c7 20ec str.w r2, [r7, #236] @ 0xec 8006c5a: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8 8006c5e: 4622 mov r2, r4 8006c60: 462b mov r3, r5 8006c62: 1891 adds r1, r2, r2 8006c64: 65b9 str r1, [r7, #88] @ 0x58 8006c66: 415b adcs r3, r3 8006c68: 65fb str r3, [r7, #92] @ 0x5c 8006c6a: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8006c6e: 4621 mov r1, r4 8006c70: eb12 0801 adds.w r8, r2, r1 8006c74: 4629 mov r1, r5 8006c76: eb43 0901 adc.w r9, r3, r1 8006c7a: f04f 0200 mov.w r2, #0 8006c7e: f04f 0300 mov.w r3, #0 8006c82: ea4f 03c9 mov.w r3, r9, lsl #3 8006c86: ea43 7358 orr.w r3, r3, r8, lsr #29 8006c8a: ea4f 02c8 mov.w r2, r8, lsl #3 8006c8e: 4690 mov r8, r2 8006c90: 4699 mov r9, r3 8006c92: 4623 mov r3, r4 8006c94: eb18 0303 adds.w r3, r8, r3 8006c98: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 8006c9c: 462b mov r3, r5 8006c9e: eb49 0303 adc.w r3, r9, r3 8006ca2: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 8006ca6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006caa: 685b ldr r3, [r3, #4] 8006cac: 2200 movs r2, #0 8006cae: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 8006cb2: f8c7 20dc str.w r2, [r7, #220] @ 0xdc 8006cb6: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 8006cba: 460b mov r3, r1 8006cbc: 18db adds r3, r3, r3 8006cbe: 653b str r3, [r7, #80] @ 0x50 8006cc0: 4613 mov r3, r2 8006cc2: eb42 0303 adc.w r3, r2, r3 8006cc6: 657b str r3, [r7, #84] @ 0x54 8006cc8: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50 8006ccc: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0 8006cd0: f7f9 fa98 bl 8000204 <__aeabi_uldivmod> 8006cd4: 4602 mov r2, r0 8006cd6: 460b mov r3, r1 8006cd8: 4b61 ldr r3, [pc, #388] @ (8006e60 ) 8006cda: fba3 2302 umull r2, r3, r3, r2 8006cde: 095b lsrs r3, r3, #5 8006ce0: 011c lsls r4, r3, #4 8006ce2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006ce6: 2200 movs r2, #0 8006ce8: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8006cec: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4 8006cf0: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0 8006cf4: 4642 mov r2, r8 8006cf6: 464b mov r3, r9 8006cf8: 1891 adds r1, r2, r2 8006cfa: 64b9 str r1, [r7, #72] @ 0x48 8006cfc: 415b adcs r3, r3 8006cfe: 64fb str r3, [r7, #76] @ 0x4c 8006d00: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8006d04: 4641 mov r1, r8 8006d06: eb12 0a01 adds.w sl, r2, r1 8006d0a: 4649 mov r1, r9 8006d0c: eb43 0b01 adc.w fp, r3, r1 8006d10: f04f 0200 mov.w r2, #0 8006d14: f04f 0300 mov.w r3, #0 8006d18: ea4f 03cb mov.w r3, fp, lsl #3 8006d1c: ea43 735a orr.w r3, r3, sl, lsr #29 8006d20: ea4f 02ca mov.w r2, sl, lsl #3 8006d24: 4692 mov sl, r2 8006d26: 469b mov fp, r3 8006d28: 4643 mov r3, r8 8006d2a: eb1a 0303 adds.w r3, sl, r3 8006d2e: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8006d32: 464b mov r3, r9 8006d34: eb4b 0303 adc.w r3, fp, r3 8006d38: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 8006d3c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006d40: 685b ldr r3, [r3, #4] 8006d42: 2200 movs r2, #0 8006d44: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8006d48: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4 8006d4c: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 8006d50: 460b mov r3, r1 8006d52: 18db adds r3, r3, r3 8006d54: 643b str r3, [r7, #64] @ 0x40 8006d56: 4613 mov r3, r2 8006d58: eb42 0303 adc.w r3, r2, r3 8006d5c: 647b str r3, [r7, #68] @ 0x44 8006d5e: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40 8006d62: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8 8006d66: f7f9 fa4d bl 8000204 <__aeabi_uldivmod> 8006d6a: 4602 mov r2, r0 8006d6c: 460b mov r3, r1 8006d6e: 4611 mov r1, r2 8006d70: 4b3b ldr r3, [pc, #236] @ (8006e60 ) 8006d72: fba3 2301 umull r2, r3, r3, r1 8006d76: 095b lsrs r3, r3, #5 8006d78: 2264 movs r2, #100 @ 0x64 8006d7a: fb02 f303 mul.w r3, r2, r3 8006d7e: 1acb subs r3, r1, r3 8006d80: 00db lsls r3, r3, #3 8006d82: f103 0232 add.w r2, r3, #50 @ 0x32 8006d86: 4b36 ldr r3, [pc, #216] @ (8006e60 ) 8006d88: fba3 2302 umull r2, r3, r3, r2 8006d8c: 095b lsrs r3, r3, #5 8006d8e: 005b lsls r3, r3, #1 8006d90: f403 73f8 and.w r3, r3, #496 @ 0x1f0 8006d94: 441c add r4, r3 8006d96: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006d9a: 2200 movs r2, #0 8006d9c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006da0: f8c7 20bc str.w r2, [r7, #188] @ 0xbc 8006da4: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8 8006da8: 4642 mov r2, r8 8006daa: 464b mov r3, r9 8006dac: 1891 adds r1, r2, r2 8006dae: 63b9 str r1, [r7, #56] @ 0x38 8006db0: 415b adcs r3, r3 8006db2: 63fb str r3, [r7, #60] @ 0x3c 8006db4: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38 8006db8: 4641 mov r1, r8 8006dba: 1851 adds r1, r2, r1 8006dbc: 6339 str r1, [r7, #48] @ 0x30 8006dbe: 4649 mov r1, r9 8006dc0: 414b adcs r3, r1 8006dc2: 637b str r3, [r7, #52] @ 0x34 8006dc4: f04f 0200 mov.w r2, #0 8006dc8: f04f 0300 mov.w r3, #0 8006dcc: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30 8006dd0: 4659 mov r1, fp 8006dd2: 00cb lsls r3, r1, #3 8006dd4: 4651 mov r1, sl 8006dd6: ea43 7351 orr.w r3, r3, r1, lsr #29 8006dda: 4651 mov r1, sl 8006ddc: 00ca lsls r2, r1, #3 8006dde: 4610 mov r0, r2 8006de0: 4619 mov r1, r3 8006de2: 4603 mov r3, r0 8006de4: 4642 mov r2, r8 8006de6: 189b adds r3, r3, r2 8006de8: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8006dec: 464b mov r3, r9 8006dee: 460a mov r2, r1 8006df0: eb42 0303 adc.w r3, r2, r3 8006df4: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8006df8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006dfc: 685b ldr r3, [r3, #4] 8006dfe: 2200 movs r2, #0 8006e00: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 8006e04: f8c7 20ac str.w r2, [r7, #172] @ 0xac 8006e08: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 8006e0c: 460b mov r3, r1 8006e0e: 18db adds r3, r3, r3 8006e10: 62bb str r3, [r7, #40] @ 0x28 8006e12: 4613 mov r3, r2 8006e14: eb42 0303 adc.w r3, r2, r3 8006e18: 62fb str r3, [r7, #44] @ 0x2c 8006e1a: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 8006e1e: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0 8006e22: f7f9 f9ef bl 8000204 <__aeabi_uldivmod> 8006e26: 4602 mov r2, r0 8006e28: 460b mov r3, r1 8006e2a: 4b0d ldr r3, [pc, #52] @ (8006e60 ) 8006e2c: fba3 1302 umull r1, r3, r3, r2 8006e30: 095b lsrs r3, r3, #5 8006e32: 2164 movs r1, #100 @ 0x64 8006e34: fb01 f303 mul.w r3, r1, r3 8006e38: 1ad3 subs r3, r2, r3 8006e3a: 00db lsls r3, r3, #3 8006e3c: 3332 adds r3, #50 @ 0x32 8006e3e: 4a08 ldr r2, [pc, #32] @ (8006e60 ) 8006e40: fba2 2303 umull r2, r3, r2, r3 8006e44: 095b lsrs r3, r3, #5 8006e46: f003 0207 and.w r2, r3, #7 8006e4a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006e4e: 681b ldr r3, [r3, #0] 8006e50: 4422 add r2, r4 8006e52: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } 8006e54: e106 b.n 8007064 8006e56: bf00 nop 8006e58: 40011000 .word 0x40011000 8006e5c: 40011400 .word 0x40011400 8006e60: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8006e64: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006e68: 2200 movs r2, #0 8006e6a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 8006e6e: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4 8006e72: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0 8006e76: 4642 mov r2, r8 8006e78: 464b mov r3, r9 8006e7a: 1891 adds r1, r2, r2 8006e7c: 6239 str r1, [r7, #32] 8006e7e: 415b adcs r3, r3 8006e80: 627b str r3, [r7, #36] @ 0x24 8006e82: e9d7 2308 ldrd r2, r3, [r7, #32] 8006e86: 4641 mov r1, r8 8006e88: 1854 adds r4, r2, r1 8006e8a: 4649 mov r1, r9 8006e8c: eb43 0501 adc.w r5, r3, r1 8006e90: f04f 0200 mov.w r2, #0 8006e94: f04f 0300 mov.w r3, #0 8006e98: 00eb lsls r3, r5, #3 8006e9a: ea43 7354 orr.w r3, r3, r4, lsr #29 8006e9e: 00e2 lsls r2, r4, #3 8006ea0: 4614 mov r4, r2 8006ea2: 461d mov r5, r3 8006ea4: 4643 mov r3, r8 8006ea6: 18e3 adds r3, r4, r3 8006ea8: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8006eac: 464b mov r3, r9 8006eae: eb45 0303 adc.w r3, r5, r3 8006eb2: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8006eb6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006eba: 685b ldr r3, [r3, #4] 8006ebc: 2200 movs r2, #0 8006ebe: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8006ec2: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8006ec6: f04f 0200 mov.w r2, #0 8006eca: f04f 0300 mov.w r3, #0 8006ece: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8006ed2: 4629 mov r1, r5 8006ed4: 008b lsls r3, r1, #2 8006ed6: 4621 mov r1, r4 8006ed8: ea43 7391 orr.w r3, r3, r1, lsr #30 8006edc: 4621 mov r1, r4 8006ede: 008a lsls r2, r1, #2 8006ee0: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98 8006ee4: f7f9 f98e bl 8000204 <__aeabi_uldivmod> 8006ee8: 4602 mov r2, r0 8006eea: 460b mov r3, r1 8006eec: 4b60 ldr r3, [pc, #384] @ (8007070 ) 8006eee: fba3 2302 umull r2, r3, r3, r2 8006ef2: 095b lsrs r3, r3, #5 8006ef4: 011c lsls r4, r3, #4 8006ef6: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006efa: 2200 movs r2, #0 8006efc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8006f00: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8006f04: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88 8006f08: 4642 mov r2, r8 8006f0a: 464b mov r3, r9 8006f0c: 1891 adds r1, r2, r2 8006f0e: 61b9 str r1, [r7, #24] 8006f10: 415b adcs r3, r3 8006f12: 61fb str r3, [r7, #28] 8006f14: e9d7 2306 ldrd r2, r3, [r7, #24] 8006f18: 4641 mov r1, r8 8006f1a: 1851 adds r1, r2, r1 8006f1c: 6139 str r1, [r7, #16] 8006f1e: 4649 mov r1, r9 8006f20: 414b adcs r3, r1 8006f22: 617b str r3, [r7, #20] 8006f24: f04f 0200 mov.w r2, #0 8006f28: f04f 0300 mov.w r3, #0 8006f2c: e9d7 ab04 ldrd sl, fp, [r7, #16] 8006f30: 4659 mov r1, fp 8006f32: 00cb lsls r3, r1, #3 8006f34: 4651 mov r1, sl 8006f36: ea43 7351 orr.w r3, r3, r1, lsr #29 8006f3a: 4651 mov r1, sl 8006f3c: 00ca lsls r2, r1, #3 8006f3e: 4610 mov r0, r2 8006f40: 4619 mov r1, r3 8006f42: 4603 mov r3, r0 8006f44: 4642 mov r2, r8 8006f46: 189b adds r3, r3, r2 8006f48: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8006f4c: 464b mov r3, r9 8006f4e: 460a mov r2, r1 8006f50: eb42 0303 adc.w r3, r2, r3 8006f54: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8006f58: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006f5c: 685b ldr r3, [r3, #4] 8006f5e: 2200 movs r2, #0 8006f60: 67bb str r3, [r7, #120] @ 0x78 8006f62: 67fa str r2, [r7, #124] @ 0x7c 8006f64: f04f 0200 mov.w r2, #0 8006f68: f04f 0300 mov.w r3, #0 8006f6c: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78 8006f70: 4649 mov r1, r9 8006f72: 008b lsls r3, r1, #2 8006f74: 4641 mov r1, r8 8006f76: ea43 7391 orr.w r3, r3, r1, lsr #30 8006f7a: 4641 mov r1, r8 8006f7c: 008a lsls r2, r1, #2 8006f7e: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80 8006f82: f7f9 f93f bl 8000204 <__aeabi_uldivmod> 8006f86: 4602 mov r2, r0 8006f88: 460b mov r3, r1 8006f8a: 4611 mov r1, r2 8006f8c: 4b38 ldr r3, [pc, #224] @ (8007070 ) 8006f8e: fba3 2301 umull r2, r3, r3, r1 8006f92: 095b lsrs r3, r3, #5 8006f94: 2264 movs r2, #100 @ 0x64 8006f96: fb02 f303 mul.w r3, r2, r3 8006f9a: 1acb subs r3, r1, r3 8006f9c: 011b lsls r3, r3, #4 8006f9e: 3332 adds r3, #50 @ 0x32 8006fa0: 4a33 ldr r2, [pc, #204] @ (8007070 ) 8006fa2: fba2 2303 umull r2, r3, r2, r3 8006fa6: 095b lsrs r3, r3, #5 8006fa8: f003 03f0 and.w r3, r3, #240 @ 0xf0 8006fac: 441c add r4, r3 8006fae: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006fb2: 2200 movs r2, #0 8006fb4: 673b str r3, [r7, #112] @ 0x70 8006fb6: 677a str r2, [r7, #116] @ 0x74 8006fb8: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70 8006fbc: 4642 mov r2, r8 8006fbe: 464b mov r3, r9 8006fc0: 1891 adds r1, r2, r2 8006fc2: 60b9 str r1, [r7, #8] 8006fc4: 415b adcs r3, r3 8006fc6: 60fb str r3, [r7, #12] 8006fc8: e9d7 2302 ldrd r2, r3, [r7, #8] 8006fcc: 4641 mov r1, r8 8006fce: 1851 adds r1, r2, r1 8006fd0: 6039 str r1, [r7, #0] 8006fd2: 4649 mov r1, r9 8006fd4: 414b adcs r3, r1 8006fd6: 607b str r3, [r7, #4] 8006fd8: f04f 0200 mov.w r2, #0 8006fdc: f04f 0300 mov.w r3, #0 8006fe0: e9d7 ab00 ldrd sl, fp, [r7] 8006fe4: 4659 mov r1, fp 8006fe6: 00cb lsls r3, r1, #3 8006fe8: 4651 mov r1, sl 8006fea: ea43 7351 orr.w r3, r3, r1, lsr #29 8006fee: 4651 mov r1, sl 8006ff0: 00ca lsls r2, r1, #3 8006ff2: 4610 mov r0, r2 8006ff4: 4619 mov r1, r3 8006ff6: 4603 mov r3, r0 8006ff8: 4642 mov r2, r8 8006ffa: 189b adds r3, r3, r2 8006ffc: 66bb str r3, [r7, #104] @ 0x68 8006ffe: 464b mov r3, r9 8007000: 460a mov r2, r1 8007002: eb42 0303 adc.w r3, r2, r3 8007006: 66fb str r3, [r7, #108] @ 0x6c 8007008: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800700c: 685b ldr r3, [r3, #4] 800700e: 2200 movs r2, #0 8007010: 663b str r3, [r7, #96] @ 0x60 8007012: 667a str r2, [r7, #100] @ 0x64 8007014: f04f 0200 mov.w r2, #0 8007018: f04f 0300 mov.w r3, #0 800701c: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60 8007020: 4649 mov r1, r9 8007022: 008b lsls r3, r1, #2 8007024: 4641 mov r1, r8 8007026: ea43 7391 orr.w r3, r3, r1, lsr #30 800702a: 4641 mov r1, r8 800702c: 008a lsls r2, r1, #2 800702e: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68 8007032: f7f9 f8e7 bl 8000204 <__aeabi_uldivmod> 8007036: 4602 mov r2, r0 8007038: 460b mov r3, r1 800703a: 4b0d ldr r3, [pc, #52] @ (8007070 ) 800703c: fba3 1302 umull r1, r3, r3, r2 8007040: 095b lsrs r3, r3, #5 8007042: 2164 movs r1, #100 @ 0x64 8007044: fb01 f303 mul.w r3, r1, r3 8007048: 1ad3 subs r3, r2, r3 800704a: 011b lsls r3, r3, #4 800704c: 3332 adds r3, #50 @ 0x32 800704e: 4a08 ldr r2, [pc, #32] @ (8007070 ) 8007050: fba2 2303 umull r2, r3, r2, r3 8007054: 095b lsrs r3, r3, #5 8007056: f003 020f and.w r2, r3, #15 800705a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800705e: 681b ldr r3, [r3, #0] 8007060: 4422 add r2, r4 8007062: 609a str r2, [r3, #8] } 8007064: bf00 nop 8007066: f507 7780 add.w r7, r7, #256 @ 0x100 800706a: 46bd mov sp, r7 800706c: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8007070: 51eb851f .word 0x51eb851f 08007074 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8007074: b084 sub sp, #16 8007076: b580 push {r7, lr} 8007078: b084 sub sp, #16 800707a: af00 add r7, sp, #0 800707c: 6078 str r0, [r7, #4] 800707e: f107 001c add.w r0, r7, #28 8007082: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8007086: f897 3021 ldrb.w r3, [r7, #33] @ 0x21 800708a: 2b01 cmp r3, #1 800708c: d123 bne.n 80070d6 { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 800708e: 687b ldr r3, [r7, #4] 8007090: 6b9b ldr r3, [r3, #56] @ 0x38 8007092: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8007096: 687b ldr r3, [r7, #4] 8007098: 639a str r2, [r3, #56] @ 0x38 /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); 800709a: 687b ldr r3, [r7, #4] 800709c: 68db ldr r3, [r3, #12] 800709e: f423 0384 bic.w r3, r3, #4325376 @ 0x420000 80070a2: f023 0340 bic.w r3, r3, #64 @ 0x40 80070a6: 687a ldr r2, [r7, #4] 80070a8: 60d3 str r3, [r2, #12] /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); 80070aa: 687b ldr r3, [r7, #4] 80070ac: 68db ldr r3, [r3, #12] 80070ae: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 80070b2: 687b ldr r3, [r7, #4] 80070b4: 60da str r2, [r3, #12] if (cfg.use_external_vbus == 1U) 80070b6: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 80070ba: 2b01 cmp r3, #1 80070bc: d105 bne.n 80070ca { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; 80070be: 687b ldr r3, [r7, #4] 80070c0: 68db ldr r3, [r3, #12] 80070c2: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 80070c6: 687b ldr r3, [r7, #4] 80070c8: 60da str r2, [r3, #12] } /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 80070ca: 6878 ldr r0, [r7, #4] 80070cc: f001 fae2 bl 8008694 80070d0: 4603 mov r3, r0 80070d2: 73fb strb r3, [r7, #15] 80070d4: e01b b.n 800710e } else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 80070d6: 687b ldr r3, [r7, #4] 80070d8: 68db ldr r3, [r3, #12] 80070da: f043 0240 orr.w r2, r3, #64 @ 0x40 80070de: 687b ldr r3, [r7, #4] 80070e0: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 80070e2: 6878 ldr r0, [r7, #4] 80070e4: f001 fad6 bl 8008694 80070e8: 4603 mov r3, r0 80070ea: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 80070ec: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 80070f0: 2b00 cmp r3, #0 80070f2: d106 bne.n 8007102 { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 80070f4: 687b ldr r3, [r7, #4] 80070f6: 6b9b ldr r3, [r3, #56] @ 0x38 80070f8: f443 3280 orr.w r2, r3, #65536 @ 0x10000 80070fc: 687b ldr r3, [r7, #4] 80070fe: 639a str r2, [r3, #56] @ 0x38 8007100: e005 b.n 800710e } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8007102: 687b ldr r3, [r7, #4] 8007104: 6b9b ldr r3, [r3, #56] @ 0x38 8007106: f423 3280 bic.w r2, r3, #65536 @ 0x10000 800710a: 687b ldr r3, [r7, #4] 800710c: 639a str r2, [r3, #56] @ 0x38 } } if (cfg.dma_enable == 1U) 800710e: 7fbb ldrb r3, [r7, #30] 8007110: 2b01 cmp r3, #1 8007112: d10b bne.n 800712c { USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; 8007114: 687b ldr r3, [r7, #4] 8007116: 689b ldr r3, [r3, #8] 8007118: f043 0206 orr.w r2, r3, #6 800711c: 687b ldr r3, [r7, #4] 800711e: 609a str r2, [r3, #8] USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; 8007120: 687b ldr r3, [r7, #4] 8007122: 689b ldr r3, [r3, #8] 8007124: f043 0220 orr.w r2, r3, #32 8007128: 687b ldr r3, [r7, #4] 800712a: 609a str r2, [r3, #8] } return ret; 800712c: 7bfb ldrb r3, [r7, #15] } 800712e: 4618 mov r0, r3 8007130: 3710 adds r7, #16 8007132: 46bd mov sp, r7 8007134: e8bd 4080 ldmia.w sp!, {r7, lr} 8007138: b004 add sp, #16 800713a: 4770 bx lr 0800713c : * @param hclk: AHB clock frequency * @retval USB turnaround time In PHY Clocks number */ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed) { 800713c: b480 push {r7} 800713e: b087 sub sp, #28 8007140: af00 add r7, sp, #0 8007142: 60f8 str r0, [r7, #12] 8007144: 60b9 str r1, [r7, #8] 8007146: 4613 mov r3, r2 8007148: 71fb strb r3, [r7, #7] /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ if (speed == USBD_FS_SPEED) 800714a: 79fb ldrb r3, [r7, #7] 800714c: 2b02 cmp r3, #2 800714e: d165 bne.n 800721c { if ((hclk >= 14200000U) && (hclk < 15000000U)) 8007150: 68bb ldr r3, [r7, #8] 8007152: 4a41 ldr r2, [pc, #260] @ (8007258 ) 8007154: 4293 cmp r3, r2 8007156: d906 bls.n 8007166 8007158: 68bb ldr r3, [r7, #8] 800715a: 4a40 ldr r2, [pc, #256] @ (800725c ) 800715c: 4293 cmp r3, r2 800715e: d202 bcs.n 8007166 { /* hclk Clock Range between 14.2-15 MHz */ UsbTrd = 0xFU; 8007160: 230f movs r3, #15 8007162: 617b str r3, [r7, #20] 8007164: e062 b.n 800722c } else if ((hclk >= 15000000U) && (hclk < 16000000U)) 8007166: 68bb ldr r3, [r7, #8] 8007168: 4a3c ldr r2, [pc, #240] @ (800725c ) 800716a: 4293 cmp r3, r2 800716c: d306 bcc.n 800717c 800716e: 68bb ldr r3, [r7, #8] 8007170: 4a3b ldr r2, [pc, #236] @ (8007260 ) 8007172: 4293 cmp r3, r2 8007174: d202 bcs.n 800717c { /* hclk Clock Range between 15-16 MHz */ UsbTrd = 0xEU; 8007176: 230e movs r3, #14 8007178: 617b str r3, [r7, #20] 800717a: e057 b.n 800722c } else if ((hclk >= 16000000U) && (hclk < 17200000U)) 800717c: 68bb ldr r3, [r7, #8] 800717e: 4a38 ldr r2, [pc, #224] @ (8007260 ) 8007180: 4293 cmp r3, r2 8007182: d306 bcc.n 8007192 8007184: 68bb ldr r3, [r7, #8] 8007186: 4a37 ldr r2, [pc, #220] @ (8007264 ) 8007188: 4293 cmp r3, r2 800718a: d202 bcs.n 8007192 { /* hclk Clock Range between 16-17.2 MHz */ UsbTrd = 0xDU; 800718c: 230d movs r3, #13 800718e: 617b str r3, [r7, #20] 8007190: e04c b.n 800722c } else if ((hclk >= 17200000U) && (hclk < 18500000U)) 8007192: 68bb ldr r3, [r7, #8] 8007194: 4a33 ldr r2, [pc, #204] @ (8007264 ) 8007196: 4293 cmp r3, r2 8007198: d306 bcc.n 80071a8 800719a: 68bb ldr r3, [r7, #8] 800719c: 4a32 ldr r2, [pc, #200] @ (8007268 ) 800719e: 4293 cmp r3, r2 80071a0: d802 bhi.n 80071a8 { /* hclk Clock Range between 17.2-18.5 MHz */ UsbTrd = 0xCU; 80071a2: 230c movs r3, #12 80071a4: 617b str r3, [r7, #20] 80071a6: e041 b.n 800722c } else if ((hclk >= 18500000U) && (hclk < 20000000U)) 80071a8: 68bb ldr r3, [r7, #8] 80071aa: 4a2f ldr r2, [pc, #188] @ (8007268 ) 80071ac: 4293 cmp r3, r2 80071ae: d906 bls.n 80071be 80071b0: 68bb ldr r3, [r7, #8] 80071b2: 4a2e ldr r2, [pc, #184] @ (800726c ) 80071b4: 4293 cmp r3, r2 80071b6: d802 bhi.n 80071be { /* hclk Clock Range between 18.5-20 MHz */ UsbTrd = 0xBU; 80071b8: 230b movs r3, #11 80071ba: 617b str r3, [r7, #20] 80071bc: e036 b.n 800722c } else if ((hclk >= 20000000U) && (hclk < 21800000U)) 80071be: 68bb ldr r3, [r7, #8] 80071c0: 4a2a ldr r2, [pc, #168] @ (800726c ) 80071c2: 4293 cmp r3, r2 80071c4: d906 bls.n 80071d4 80071c6: 68bb ldr r3, [r7, #8] 80071c8: 4a29 ldr r2, [pc, #164] @ (8007270 ) 80071ca: 4293 cmp r3, r2 80071cc: d802 bhi.n 80071d4 { /* hclk Clock Range between 20-21.8 MHz */ UsbTrd = 0xAU; 80071ce: 230a movs r3, #10 80071d0: 617b str r3, [r7, #20] 80071d2: e02b b.n 800722c } else if ((hclk >= 21800000U) && (hclk < 24000000U)) 80071d4: 68bb ldr r3, [r7, #8] 80071d6: 4a26 ldr r2, [pc, #152] @ (8007270 ) 80071d8: 4293 cmp r3, r2 80071da: d906 bls.n 80071ea 80071dc: 68bb ldr r3, [r7, #8] 80071de: 4a25 ldr r2, [pc, #148] @ (8007274 ) 80071e0: 4293 cmp r3, r2 80071e2: d202 bcs.n 80071ea { /* hclk Clock Range between 21.8-24 MHz */ UsbTrd = 0x9U; 80071e4: 2309 movs r3, #9 80071e6: 617b str r3, [r7, #20] 80071e8: e020 b.n 800722c } else if ((hclk >= 24000000U) && (hclk < 27700000U)) 80071ea: 68bb ldr r3, [r7, #8] 80071ec: 4a21 ldr r2, [pc, #132] @ (8007274 ) 80071ee: 4293 cmp r3, r2 80071f0: d306 bcc.n 8007200 80071f2: 68bb ldr r3, [r7, #8] 80071f4: 4a20 ldr r2, [pc, #128] @ (8007278 ) 80071f6: 4293 cmp r3, r2 80071f8: d802 bhi.n 8007200 { /* hclk Clock Range between 24-27.7 MHz */ UsbTrd = 0x8U; 80071fa: 2308 movs r3, #8 80071fc: 617b str r3, [r7, #20] 80071fe: e015 b.n 800722c } else if ((hclk >= 27700000U) && (hclk < 32000000U)) 8007200: 68bb ldr r3, [r7, #8] 8007202: 4a1d ldr r2, [pc, #116] @ (8007278 ) 8007204: 4293 cmp r3, r2 8007206: d906 bls.n 8007216 8007208: 68bb ldr r3, [r7, #8] 800720a: 4a1c ldr r2, [pc, #112] @ (800727c ) 800720c: 4293 cmp r3, r2 800720e: d202 bcs.n 8007216 { /* hclk Clock Range between 27.7-32 MHz */ UsbTrd = 0x7U; 8007210: 2307 movs r3, #7 8007212: 617b str r3, [r7, #20] 8007214: e00a b.n 800722c } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ UsbTrd = 0x6U; 8007216: 2306 movs r3, #6 8007218: 617b str r3, [r7, #20] 800721a: e007 b.n 800722c } } else if (speed == USBD_HS_SPEED) 800721c: 79fb ldrb r3, [r7, #7] 800721e: 2b00 cmp r3, #0 8007220: d102 bne.n 8007228 { UsbTrd = USBD_HS_TRDT_VALUE; 8007222: 2309 movs r3, #9 8007224: 617b str r3, [r7, #20] 8007226: e001 b.n 800722c } else { UsbTrd = USBD_DEFAULT_TRDT_VALUE; 8007228: 2309 movs r3, #9 800722a: 617b str r3, [r7, #20] } USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; 800722c: 68fb ldr r3, [r7, #12] 800722e: 68db ldr r3, [r3, #12] 8007230: f423 5270 bic.w r2, r3, #15360 @ 0x3c00 8007234: 68fb ldr r3, [r7, #12] 8007236: 60da str r2, [r3, #12] USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); 8007238: 68fb ldr r3, [r7, #12] 800723a: 68da ldr r2, [r3, #12] 800723c: 697b ldr r3, [r7, #20] 800723e: 029b lsls r3, r3, #10 8007240: f403 5370 and.w r3, r3, #15360 @ 0x3c00 8007244: 431a orrs r2, r3 8007246: 68fb ldr r3, [r7, #12] 8007248: 60da str r2, [r3, #12] return HAL_OK; 800724a: 2300 movs r3, #0 } 800724c: 4618 mov r0, r3 800724e: 371c adds r7, #28 8007250: 46bd mov sp, r7 8007252: f85d 7b04 ldr.w r7, [sp], #4 8007256: 4770 bx lr 8007258: 00d8acbf .word 0x00d8acbf 800725c: 00e4e1c0 .word 0x00e4e1c0 8007260: 00f42400 .word 0x00f42400 8007264: 01067380 .word 0x01067380 8007268: 011a499f .word 0x011a499f 800726c: 01312cff .word 0x01312cff 8007270: 014ca43f .word 0x014ca43f 8007274: 016e3600 .word 0x016e3600 8007278: 01a6ab1f .word 0x01a6ab1f 800727c: 01e84800 .word 0x01e84800 08007280 : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8007280: b480 push {r7} 8007282: b083 sub sp, #12 8007284: af00 add r7, sp, #0 8007286: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 8007288: 687b ldr r3, [r7, #4] 800728a: 689b ldr r3, [r3, #8] 800728c: f043 0201 orr.w r2, r3, #1 8007290: 687b ldr r3, [r7, #4] 8007292: 609a str r2, [r3, #8] return HAL_OK; 8007294: 2300 movs r3, #0 } 8007296: 4618 mov r0, r3 8007298: 370c adds r7, #12 800729a: 46bd mov sp, r7 800729c: f85d 7b04 ldr.w r7, [sp], #4 80072a0: 4770 bx lr 080072a2 : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 80072a2: b480 push {r7} 80072a4: b083 sub sp, #12 80072a6: af00 add r7, sp, #0 80072a8: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 80072aa: 687b ldr r3, [r7, #4] 80072ac: 689b ldr r3, [r3, #8] 80072ae: f023 0201 bic.w r2, r3, #1 80072b2: 687b ldr r3, [r7, #4] 80072b4: 609a str r2, [r3, #8] return HAL_OK; 80072b6: 2300 movs r3, #0 } 80072b8: 4618 mov r0, r3 80072ba: 370c adds r7, #12 80072bc: 46bd mov sp, r7 80072be: f85d 7b04 ldr.w r7, [sp], #4 80072c2: 4770 bx lr 080072c4 : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { 80072c4: b580 push {r7, lr} 80072c6: b084 sub sp, #16 80072c8: af00 add r7, sp, #0 80072ca: 6078 str r0, [r7, #4] 80072cc: 460b mov r3, r1 80072ce: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 80072d0: 2300 movs r3, #0 80072d2: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 80072d4: 687b ldr r3, [r7, #4] 80072d6: 68db ldr r3, [r3, #12] 80072d8: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000 80072dc: 687b ldr r3, [r7, #4] 80072de: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 80072e0: 78fb ldrb r3, [r7, #3] 80072e2: 2b01 cmp r3, #1 80072e4: d115 bne.n 8007312 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 80072e6: 687b ldr r3, [r7, #4] 80072e8: 68db ldr r3, [r3, #12] 80072ea: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 80072ee: 687b ldr r3, [r7, #4] 80072f0: 60da str r2, [r3, #12] do { HAL_Delay(10U); 80072f2: 200a movs r0, #10 80072f4: f7fa fbcc bl 8001a90 ms += 10U; 80072f8: 68fb ldr r3, [r7, #12] 80072fa: 330a adds r3, #10 80072fc: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 80072fe: 6878 ldr r0, [r7, #4] 8007300: f001 f939 bl 8008576 8007304: 4603 mov r3, r0 8007306: 2b01 cmp r3, #1 8007308: d01e beq.n 8007348 800730a: 68fb ldr r3, [r7, #12] 800730c: 2bc7 cmp r3, #199 @ 0xc7 800730e: d9f0 bls.n 80072f2 8007310: e01a b.n 8007348 } else if (mode == USB_DEVICE_MODE) 8007312: 78fb ldrb r3, [r7, #3] 8007314: 2b00 cmp r3, #0 8007316: d115 bne.n 8007344 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 8007318: 687b ldr r3, [r7, #4] 800731a: 68db ldr r3, [r3, #12] 800731c: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000 8007320: 687b ldr r3, [r7, #4] 8007322: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8007324: 200a movs r0, #10 8007326: f7fa fbb3 bl 8001a90 ms += 10U; 800732a: 68fb ldr r3, [r7, #12] 800732c: 330a adds r3, #10 800732e: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8007330: 6878 ldr r0, [r7, #4] 8007332: f001 f920 bl 8008576 8007336: 4603 mov r3, r0 8007338: 2b00 cmp r3, #0 800733a: d005 beq.n 8007348 800733c: 68fb ldr r3, [r7, #12] 800733e: 2bc7 cmp r3, #199 @ 0xc7 8007340: d9f0 bls.n 8007324 8007342: e001 b.n 8007348 } else { return HAL_ERROR; 8007344: 2301 movs r3, #1 8007346: e005 b.n 8007354 } if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) 8007348: 68fb ldr r3, [r7, #12] 800734a: 2bc8 cmp r3, #200 @ 0xc8 800734c: d101 bne.n 8007352 { return HAL_ERROR; 800734e: 2301 movs r3, #1 8007350: e000 b.n 8007354 } return HAL_OK; 8007352: 2300 movs r3, #0 } 8007354: 4618 mov r0, r3 8007356: 3710 adds r7, #16 8007358: 46bd mov sp, r7 800735a: bd80 pop {r7, pc} 0800735c : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 800735c: b084 sub sp, #16 800735e: b580 push {r7, lr} 8007360: b086 sub sp, #24 8007362: af00 add r7, sp, #0 8007364: 6078 str r0, [r7, #4] 8007366: f107 0024 add.w r0, r7, #36 @ 0x24 800736a: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 800736e: 2300 movs r3, #0 8007370: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8007372: 687b ldr r3, [r7, #4] 8007374: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 8007376: 2300 movs r3, #0 8007378: 613b str r3, [r7, #16] 800737a: e009 b.n 8007390 { USBx->DIEPTXF[i] = 0U; 800737c: 687a ldr r2, [r7, #4] 800737e: 693b ldr r3, [r7, #16] 8007380: 3340 adds r3, #64 @ 0x40 8007382: 009b lsls r3, r3, #2 8007384: 4413 add r3, r2 8007386: 2200 movs r2, #0 8007388: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 800738a: 693b ldr r3, [r7, #16] 800738c: 3301 adds r3, #1 800738e: 613b str r3, [r7, #16] 8007390: 693b ldr r3, [r7, #16] 8007392: 2b0e cmp r3, #14 8007394: d9f2 bls.n 800737c #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 8007396: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 800739a: 2b00 cmp r3, #0 800739c: d11c bne.n 80073d8 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 800739e: 68fb ldr r3, [r7, #12] 80073a0: f503 6300 add.w r3, r3, #2048 @ 0x800 80073a4: 685b ldr r3, [r3, #4] 80073a6: 68fa ldr r2, [r7, #12] 80073a8: f502 6200 add.w r2, r2, #2048 @ 0x800 80073ac: f043 0302 orr.w r3, r3, #2 80073b0: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 80073b2: 687b ldr r3, [r7, #4] 80073b4: 6b9b ldr r3, [r3, #56] @ 0x38 80073b6: f423 1200 bic.w r2, r3, #2097152 @ 0x200000 80073ba: 687b ldr r3, [r7, #4] 80073bc: 639a str r2, [r3, #56] @ 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 80073be: 687b ldr r3, [r7, #4] 80073c0: 681b ldr r3, [r3, #0] 80073c2: f043 0240 orr.w r2, r3, #64 @ 0x40 80073c6: 687b ldr r3, [r7, #4] 80073c8: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 80073ca: 687b ldr r3, [r7, #4] 80073cc: 681b ldr r3, [r3, #0] 80073ce: f043 0280 orr.w r2, r3, #128 @ 0x80 80073d2: 687b ldr r3, [r7, #4] 80073d4: 601a str r2, [r3, #0] 80073d6: e005 b.n 80073e4 } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 80073d8: 687b ldr r3, [r7, #4] 80073da: 6b9b ldr r3, [r3, #56] @ 0x38 80073dc: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 80073e0: 687b ldr r3, [r7, #4] 80073e2: 639a str r2, [r3, #56] @ 0x38 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 80073e4: 68fb ldr r3, [r7, #12] 80073e6: f503 6360 add.w r3, r3, #3584 @ 0xe00 80073ea: 461a mov r2, r3 80073ec: 2300 movs r3, #0 80073ee: 6013 str r3, [r2, #0] if (cfg.phy_itface == USB_OTG_ULPI_PHY) 80073f0: f897 3029 ldrb.w r3, [r7, #41] @ 0x29 80073f4: 2b01 cmp r3, #1 80073f6: d10d bne.n 8007414 { if (cfg.speed == USBD_HS_SPEED) 80073f8: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 80073fc: 2b00 cmp r3, #0 80073fe: d104 bne.n 800740a { /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); 8007400: 2100 movs r1, #0 8007402: 6878 ldr r0, [r7, #4] 8007404: f000 f968 bl 80076d8 8007408: e008 b.n 800741c } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); 800740a: 2101 movs r1, #1 800740c: 6878 ldr r0, [r7, #4] 800740e: f000 f963 bl 80076d8 8007412: e003 b.n 800741c } } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 8007414: 2103 movs r1, #3 8007416: 6878 ldr r0, [r7, #4] 8007418: f000 f95e bl 80076d8 } /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 800741c: 2110 movs r1, #16 800741e: 6878 ldr r0, [r7, #4] 8007420: f000 f8fa bl 8007618 8007424: 4603 mov r3, r0 8007426: 2b00 cmp r3, #0 8007428: d001 beq.n 800742e { ret = HAL_ERROR; 800742a: 2301 movs r3, #1 800742c: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 800742e: 6878 ldr r0, [r7, #4] 8007430: f000 f924 bl 800767c 8007434: 4603 mov r3, r0 8007436: 2b00 cmp r3, #0 8007438: d001 beq.n 800743e { ret = HAL_ERROR; 800743a: 2301 movs r3, #1 800743c: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 800743e: 68fb ldr r3, [r7, #12] 8007440: f503 6300 add.w r3, r3, #2048 @ 0x800 8007444: 461a mov r2, r3 8007446: 2300 movs r3, #0 8007448: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 800744a: 68fb ldr r3, [r7, #12] 800744c: f503 6300 add.w r3, r3, #2048 @ 0x800 8007450: 461a mov r2, r3 8007452: 2300 movs r3, #0 8007454: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 8007456: 68fb ldr r3, [r7, #12] 8007458: f503 6300 add.w r3, r3, #2048 @ 0x800 800745c: 461a mov r2, r3 800745e: 2300 movs r3, #0 8007460: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 8007462: 2300 movs r3, #0 8007464: 613b str r3, [r7, #16] 8007466: e043 b.n 80074f0 { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007468: 693b ldr r3, [r7, #16] 800746a: 015a lsls r2, r3, #5 800746c: 68fb ldr r3, [r7, #12] 800746e: 4413 add r3, r2 8007470: f503 6310 add.w r3, r3, #2304 @ 0x900 8007474: 681b ldr r3, [r3, #0] 8007476: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800747a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800747e: d118 bne.n 80074b2 { if (i == 0U) 8007480: 693b ldr r3, [r7, #16] 8007482: 2b00 cmp r3, #0 8007484: d10a bne.n 800749c { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 8007486: 693b ldr r3, [r7, #16] 8007488: 015a lsls r2, r3, #5 800748a: 68fb ldr r3, [r7, #12] 800748c: 4413 add r3, r2 800748e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007492: 461a mov r2, r3 8007494: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8007498: 6013 str r3, [r2, #0] 800749a: e013 b.n 80074c4 } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 800749c: 693b ldr r3, [r7, #16] 800749e: 015a lsls r2, r3, #5 80074a0: 68fb ldr r3, [r7, #12] 80074a2: 4413 add r3, r2 80074a4: f503 6310 add.w r3, r3, #2304 @ 0x900 80074a8: 461a mov r2, r3 80074aa: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 80074ae: 6013 str r3, [r2, #0] 80074b0: e008 b.n 80074c4 } } else { USBx_INEP(i)->DIEPCTL = 0U; 80074b2: 693b ldr r3, [r7, #16] 80074b4: 015a lsls r2, r3, #5 80074b6: 68fb ldr r3, [r7, #12] 80074b8: 4413 add r3, r2 80074ba: f503 6310 add.w r3, r3, #2304 @ 0x900 80074be: 461a mov r2, r3 80074c0: 2300 movs r3, #0 80074c2: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 80074c4: 693b ldr r3, [r7, #16] 80074c6: 015a lsls r2, r3, #5 80074c8: 68fb ldr r3, [r7, #12] 80074ca: 4413 add r3, r2 80074cc: f503 6310 add.w r3, r3, #2304 @ 0x900 80074d0: 461a mov r2, r3 80074d2: 2300 movs r3, #0 80074d4: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 80074d6: 693b ldr r3, [r7, #16] 80074d8: 015a lsls r2, r3, #5 80074da: 68fb ldr r3, [r7, #12] 80074dc: 4413 add r3, r2 80074de: f503 6310 add.w r3, r3, #2304 @ 0x900 80074e2: 461a mov r2, r3 80074e4: f64f 337f movw r3, #64383 @ 0xfb7f 80074e8: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 80074ea: 693b ldr r3, [r7, #16] 80074ec: 3301 adds r3, #1 80074ee: 613b str r3, [r7, #16] 80074f0: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 80074f4: 461a mov r2, r3 80074f6: 693b ldr r3, [r7, #16] 80074f8: 4293 cmp r3, r2 80074fa: d3b5 bcc.n 8007468 } for (i = 0U; i < cfg.dev_endpoints; i++) 80074fc: 2300 movs r3, #0 80074fe: 613b str r3, [r7, #16] 8007500: e043 b.n 800758a { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007502: 693b ldr r3, [r7, #16] 8007504: 015a lsls r2, r3, #5 8007506: 68fb ldr r3, [r7, #12] 8007508: 4413 add r3, r2 800750a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800750e: 681b ldr r3, [r3, #0] 8007510: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007514: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007518: d118 bne.n 800754c { if (i == 0U) 800751a: 693b ldr r3, [r7, #16] 800751c: 2b00 cmp r3, #0 800751e: d10a bne.n 8007536 { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 8007520: 693b ldr r3, [r7, #16] 8007522: 015a lsls r2, r3, #5 8007524: 68fb ldr r3, [r7, #12] 8007526: 4413 add r3, r2 8007528: f503 6330 add.w r3, r3, #2816 @ 0xb00 800752c: 461a mov r2, r3 800752e: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8007532: 6013 str r3, [r2, #0] 8007534: e013 b.n 800755e } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 8007536: 693b ldr r3, [r7, #16] 8007538: 015a lsls r2, r3, #5 800753a: 68fb ldr r3, [r7, #12] 800753c: 4413 add r3, r2 800753e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007542: 461a mov r2, r3 8007544: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 8007548: 6013 str r3, [r2, #0] 800754a: e008 b.n 800755e } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 800754c: 693b ldr r3, [r7, #16] 800754e: 015a lsls r2, r3, #5 8007550: 68fb ldr r3, [r7, #12] 8007552: 4413 add r3, r2 8007554: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007558: 461a mov r2, r3 800755a: 2300 movs r3, #0 800755c: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 800755e: 693b ldr r3, [r7, #16] 8007560: 015a lsls r2, r3, #5 8007562: 68fb ldr r3, [r7, #12] 8007564: 4413 add r3, r2 8007566: f503 6330 add.w r3, r3, #2816 @ 0xb00 800756a: 461a mov r2, r3 800756c: 2300 movs r3, #0 800756e: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8007570: 693b ldr r3, [r7, #16] 8007572: 015a lsls r2, r3, #5 8007574: 68fb ldr r3, [r7, #12] 8007576: 4413 add r3, r2 8007578: f503 6330 add.w r3, r3, #2816 @ 0xb00 800757c: 461a mov r2, r3 800757e: f64f 337f movw r3, #64383 @ 0xfb7f 8007582: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8007584: 693b ldr r3, [r7, #16] 8007586: 3301 adds r3, #1 8007588: 613b str r3, [r7, #16] 800758a: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 800758e: 461a mov r2, r3 8007590: 693b ldr r3, [r7, #16] 8007592: 4293 cmp r3, r2 8007594: d3b5 bcc.n 8007502 } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 8007596: 68fb ldr r3, [r7, #12] 8007598: f503 6300 add.w r3, r3, #2048 @ 0x800 800759c: 691b ldr r3, [r3, #16] 800759e: 68fa ldr r2, [r7, #12] 80075a0: f502 6200 add.w r2, r2, #2048 @ 0x800 80075a4: f423 7380 bic.w r3, r3, #256 @ 0x100 80075a8: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 80075aa: 687b ldr r3, [r7, #4] 80075ac: 2200 movs r2, #0 80075ae: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 80075b0: 687b ldr r3, [r7, #4] 80075b2: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000 80075b6: 615a str r2, [r3, #20] /* Enable the common interrupts */ if (cfg.dma_enable == 0U) 80075b8: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 80075bc: 2b00 cmp r3, #0 80075be: d105 bne.n 80075cc { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 80075c0: 687b ldr r3, [r7, #4] 80075c2: 699b ldr r3, [r3, #24] 80075c4: f043 0210 orr.w r2, r3, #16 80075c8: 687b ldr r3, [r7, #4] 80075ca: 619a str r2, [r3, #24] } /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 80075cc: 687b ldr r3, [r7, #4] 80075ce: 699a ldr r2, [r3, #24] 80075d0: 4b10 ldr r3, [pc, #64] @ (8007614 ) 80075d2: 4313 orrs r3, r2 80075d4: 687a ldr r2, [r7, #4] 80075d6: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 80075d8: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 80075dc: 2b00 cmp r3, #0 80075de: d005 beq.n 80075ec { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 80075e0: 687b ldr r3, [r7, #4] 80075e2: 699b ldr r3, [r3, #24] 80075e4: f043 0208 orr.w r2, r3, #8 80075e8: 687b ldr r3, [r7, #4] 80075ea: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 80075ec: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 80075f0: 2b01 cmp r3, #1 80075f2: d107 bne.n 8007604 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 80075f4: 687b ldr r3, [r7, #4] 80075f6: 699b ldr r3, [r3, #24] 80075f8: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80075fc: f043 0304 orr.w r3, r3, #4 8007600: 687a ldr r2, [r7, #4] 8007602: 6193 str r3, [r2, #24] } return ret; 8007604: 7dfb ldrb r3, [r7, #23] } 8007606: 4618 mov r0, r3 8007608: 3718 adds r7, #24 800760a: 46bd mov sp, r7 800760c: e8bd 4080 ldmia.w sp!, {r7, lr} 8007610: b004 add sp, #16 8007612: 4770 bx lr 8007614: 803c3800 .word 0x803c3800 08007618 : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 8007618: b480 push {r7} 800761a: b085 sub sp, #20 800761c: af00 add r7, sp, #0 800761e: 6078 str r0, [r7, #4] 8007620: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8007622: 2300 movs r3, #0 8007624: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8007626: 68fb ldr r3, [r7, #12] 8007628: 3301 adds r3, #1 800762a: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800762c: 68fb ldr r3, [r7, #12] 800762e: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007632: d901 bls.n 8007638 { return HAL_TIMEOUT; 8007634: 2303 movs r3, #3 8007636: e01b b.n 8007670 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8007638: 687b ldr r3, [r7, #4] 800763a: 691b ldr r3, [r3, #16] 800763c: 2b00 cmp r3, #0 800763e: daf2 bge.n 8007626 /* Flush TX Fifo */ count = 0U; 8007640: 2300 movs r3, #0 8007642: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 8007644: 683b ldr r3, [r7, #0] 8007646: 019b lsls r3, r3, #6 8007648: f043 0220 orr.w r2, r3, #32 800764c: 687b ldr r3, [r7, #4] 800764e: 611a str r2, [r3, #16] do { count++; 8007650: 68fb ldr r3, [r7, #12] 8007652: 3301 adds r3, #1 8007654: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007656: 68fb ldr r3, [r7, #12] 8007658: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 800765c: d901 bls.n 8007662 { return HAL_TIMEOUT; 800765e: 2303 movs r3, #3 8007660: e006 b.n 8007670 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 8007662: 687b ldr r3, [r7, #4] 8007664: 691b ldr r3, [r3, #16] 8007666: f003 0320 and.w r3, r3, #32 800766a: 2b20 cmp r3, #32 800766c: d0f0 beq.n 8007650 return HAL_OK; 800766e: 2300 movs r3, #0 } 8007670: 4618 mov r0, r3 8007672: 3714 adds r7, #20 8007674: 46bd mov sp, r7 8007676: f85d 7b04 ldr.w r7, [sp], #4 800767a: 4770 bx lr 0800767c : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 800767c: b480 push {r7} 800767e: b085 sub sp, #20 8007680: af00 add r7, sp, #0 8007682: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8007684: 2300 movs r3, #0 8007686: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8007688: 68fb ldr r3, [r7, #12] 800768a: 3301 adds r3, #1 800768c: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800768e: 68fb ldr r3, [r7, #12] 8007690: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007694: d901 bls.n 800769a { return HAL_TIMEOUT; 8007696: 2303 movs r3, #3 8007698: e018 b.n 80076cc } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 800769a: 687b ldr r3, [r7, #4] 800769c: 691b ldr r3, [r3, #16] 800769e: 2b00 cmp r3, #0 80076a0: daf2 bge.n 8007688 /* Flush RX Fifo */ count = 0U; 80076a2: 2300 movs r3, #0 80076a4: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 80076a6: 687b ldr r3, [r7, #4] 80076a8: 2210 movs r2, #16 80076aa: 611a str r2, [r3, #16] do { count++; 80076ac: 68fb ldr r3, [r7, #12] 80076ae: 3301 adds r3, #1 80076b0: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80076b2: 68fb ldr r3, [r7, #12] 80076b4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80076b8: d901 bls.n 80076be { return HAL_TIMEOUT; 80076ba: 2303 movs r3, #3 80076bc: e006 b.n 80076cc } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 80076be: 687b ldr r3, [r7, #4] 80076c0: 691b ldr r3, [r3, #16] 80076c2: f003 0310 and.w r3, r3, #16 80076c6: 2b10 cmp r3, #16 80076c8: d0f0 beq.n 80076ac return HAL_OK; 80076ca: 2300 movs r3, #0 } 80076cc: 4618 mov r0, r3 80076ce: 3714 adds r7, #20 80076d0: 46bd mov sp, r7 80076d2: f85d 7b04 ldr.w r7, [sp], #4 80076d6: 4770 bx lr 080076d8 : * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 80076d8: b480 push {r7} 80076da: b085 sub sp, #20 80076dc: af00 add r7, sp, #0 80076de: 6078 str r0, [r7, #4] 80076e0: 460b mov r3, r1 80076e2: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80076e4: 687b ldr r3, [r7, #4] 80076e6: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 80076e8: 68fb ldr r3, [r7, #12] 80076ea: f503 6300 add.w r3, r3, #2048 @ 0x800 80076ee: 681a ldr r2, [r3, #0] 80076f0: 78fb ldrb r3, [r7, #3] 80076f2: 68f9 ldr r1, [r7, #12] 80076f4: f501 6100 add.w r1, r1, #2048 @ 0x800 80076f8: 4313 orrs r3, r2 80076fa: 600b str r3, [r1, #0] return HAL_OK; 80076fc: 2300 movs r3, #0 } 80076fe: 4618 mov r0, r3 8007700: 3714 adds r7, #20 8007702: 46bd mov sp, r7 8007704: f85d 7b04 ldr.w r7, [sp], #4 8007708: 4770 bx lr 0800770a : * This parameter can be one of these values: * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { 800770a: b480 push {r7} 800770c: b087 sub sp, #28 800770e: af00 add r7, sp, #0 8007710: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007712: 687b ldr r3, [r7, #4] 8007714: 613b str r3, [r7, #16] uint8_t speed; uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; 8007716: 693b ldr r3, [r7, #16] 8007718: f503 6300 add.w r3, r3, #2048 @ 0x800 800771c: 689b ldr r3, [r3, #8] 800771e: f003 0306 and.w r3, r3, #6 8007722: 60fb str r3, [r7, #12] if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 8007724: 68fb ldr r3, [r7, #12] 8007726: 2b00 cmp r3, #0 8007728: d102 bne.n 8007730 { speed = USBD_HS_SPEED; 800772a: 2300 movs r3, #0 800772c: 75fb strb r3, [r7, #23] 800772e: e00a b.n 8007746 } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || 8007730: 68fb ldr r3, [r7, #12] 8007732: 2b02 cmp r3, #2 8007734: d002 beq.n 800773c 8007736: 68fb ldr r3, [r7, #12] 8007738: 2b06 cmp r3, #6 800773a: d102 bne.n 8007742 (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USBD_FS_SPEED; 800773c: 2302 movs r3, #2 800773e: 75fb strb r3, [r7, #23] 8007740: e001 b.n 8007746 } else { speed = 0xFU; 8007742: 230f movs r3, #15 8007744: 75fb strb r3, [r7, #23] } return speed; 8007746: 7dfb ldrb r3, [r7, #23] } 8007748: 4618 mov r0, r3 800774a: 371c adds r7, #28 800774c: 46bd mov sp, r7 800774e: f85d 7b04 ldr.w r7, [sp], #4 8007752: 4770 bx lr 08007754 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007754: b480 push {r7} 8007756: b085 sub sp, #20 8007758: af00 add r7, sp, #0 800775a: 6078 str r0, [r7, #4] 800775c: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800775e: 687b ldr r3, [r7, #4] 8007760: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007762: 683b ldr r3, [r7, #0] 8007764: 781b ldrb r3, [r3, #0] 8007766: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8007768: 683b ldr r3, [r7, #0] 800776a: 785b ldrb r3, [r3, #1] 800776c: 2b01 cmp r3, #1 800776e: d13a bne.n 80077e6 { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); 8007770: 68fb ldr r3, [r7, #12] 8007772: f503 6300 add.w r3, r3, #2048 @ 0x800 8007776: 69da ldr r2, [r3, #28] 8007778: 683b ldr r3, [r7, #0] 800777a: 781b ldrb r3, [r3, #0] 800777c: f003 030f and.w r3, r3, #15 8007780: 2101 movs r1, #1 8007782: fa01 f303 lsl.w r3, r1, r3 8007786: b29b uxth r3, r3 8007788: 68f9 ldr r1, [r7, #12] 800778a: f501 6100 add.w r1, r1, #2048 @ 0x800 800778e: 4313 orrs r3, r2 8007790: 61cb str r3, [r1, #28] if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) 8007792: 68bb ldr r3, [r7, #8] 8007794: 015a lsls r2, r3, #5 8007796: 68fb ldr r3, [r7, #12] 8007798: 4413 add r3, r2 800779a: f503 6310 add.w r3, r3, #2304 @ 0x900 800779e: 681b ldr r3, [r3, #0] 80077a0: f403 4300 and.w r3, r3, #32768 @ 0x8000 80077a4: 2b00 cmp r3, #0 80077a6: d155 bne.n 8007854 { USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 80077a8: 68bb ldr r3, [r7, #8] 80077aa: 015a lsls r2, r3, #5 80077ac: 68fb ldr r3, [r7, #12] 80077ae: 4413 add r3, r2 80077b0: f503 6310 add.w r3, r3, #2304 @ 0x900 80077b4: 681a ldr r2, [r3, #0] 80077b6: 683b ldr r3, [r7, #0] 80077b8: 689b ldr r3, [r3, #8] 80077ba: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | (epnum << 22) | 80077be: 683b ldr r3, [r7, #0] 80077c0: 791b ldrb r3, [r3, #4] 80077c2: 049b lsls r3, r3, #18 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 80077c4: 4319 orrs r1, r3 ((uint32_t)ep->type << 18) | (epnum << 22) | 80077c6: 68bb ldr r3, [r7, #8] 80077c8: 059b lsls r3, r3, #22 80077ca: 430b orrs r3, r1 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 80077cc: 4313 orrs r3, r2 80077ce: 68ba ldr r2, [r7, #8] 80077d0: 0151 lsls r1, r2, #5 80077d2: 68fa ldr r2, [r7, #12] 80077d4: 440a add r2, r1 80077d6: f502 6210 add.w r2, r2, #2304 @ 0x900 80077da: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80077de: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80077e2: 6013 str r3, [r2, #0] 80077e4: e036 b.n 8007854 USB_OTG_DIEPCTL_USBAEP; } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); 80077e6: 68fb ldr r3, [r7, #12] 80077e8: f503 6300 add.w r3, r3, #2048 @ 0x800 80077ec: 69da ldr r2, [r3, #28] 80077ee: 683b ldr r3, [r7, #0] 80077f0: 781b ldrb r3, [r3, #0] 80077f2: f003 030f and.w r3, r3, #15 80077f6: 2101 movs r1, #1 80077f8: fa01 f303 lsl.w r3, r1, r3 80077fc: 041b lsls r3, r3, #16 80077fe: 68f9 ldr r1, [r7, #12] 8007800: f501 6100 add.w r1, r1, #2048 @ 0x800 8007804: 4313 orrs r3, r2 8007806: 61cb str r3, [r1, #28] if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) 8007808: 68bb ldr r3, [r7, #8] 800780a: 015a lsls r2, r3, #5 800780c: 68fb ldr r3, [r7, #12] 800780e: 4413 add r3, r2 8007810: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007814: 681b ldr r3, [r3, #0] 8007816: f403 4300 and.w r3, r3, #32768 @ 0x8000 800781a: 2b00 cmp r3, #0 800781c: d11a bne.n 8007854 { USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 800781e: 68bb ldr r3, [r7, #8] 8007820: 015a lsls r2, r3, #5 8007822: 68fb ldr r3, [r7, #12] 8007824: 4413 add r3, r2 8007826: f503 6330 add.w r3, r3, #2816 @ 0xb00 800782a: 681a ldr r2, [r3, #0] 800782c: 683b ldr r3, [r7, #0] 800782e: 689b ldr r3, [r3, #8] 8007830: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | 8007834: 683b ldr r3, [r7, #0] 8007836: 791b ldrb r3, [r3, #4] 8007838: 049b lsls r3, r3, #18 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 800783a: 430b orrs r3, r1 800783c: 4313 orrs r3, r2 800783e: 68ba ldr r2, [r7, #8] 8007840: 0151 lsls r1, r2, #5 8007842: 68fa ldr r2, [r7, #12] 8007844: 440a add r2, r1 8007846: f502 6230 add.w r2, r2, #2816 @ 0xb00 800784a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800784e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8007852: 6013 str r3, [r2, #0] USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; 8007854: 2300 movs r3, #0 } 8007856: 4618 mov r0, r3 8007858: 3714 adds r7, #20 800785a: 46bd mov sp, r7 800785c: f85d 7b04 ldr.w r7, [sp], #4 8007860: 4770 bx lr ... 08007864 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007864: b480 push {r7} 8007866: b085 sub sp, #20 8007868: af00 add r7, sp, #0 800786a: 6078 str r0, [r7, #4] 800786c: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800786e: 687b ldr r3, [r7, #4] 8007870: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007872: 683b ldr r3, [r7, #0] 8007874: 781b ldrb r3, [r3, #0] 8007876: 60bb str r3, [r7, #8] /* Read DEPCTLn register */ if (ep->is_in == 1U) 8007878: 683b ldr r3, [r7, #0] 800787a: 785b ldrb r3, [r3, #1] 800787c: 2b01 cmp r3, #1 800787e: d161 bne.n 8007944 { if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007880: 68bb ldr r3, [r7, #8] 8007882: 015a lsls r2, r3, #5 8007884: 68fb ldr r3, [r7, #12] 8007886: 4413 add r3, r2 8007888: f503 6310 add.w r3, r3, #2304 @ 0x900 800788c: 681b ldr r3, [r3, #0] 800788e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007892: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007896: d11f bne.n 80078d8 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 8007898: 68bb ldr r3, [r7, #8] 800789a: 015a lsls r2, r3, #5 800789c: 68fb ldr r3, [r7, #12] 800789e: 4413 add r3, r2 80078a0: f503 6310 add.w r3, r3, #2304 @ 0x900 80078a4: 681b ldr r3, [r3, #0] 80078a6: 68ba ldr r2, [r7, #8] 80078a8: 0151 lsls r1, r2, #5 80078aa: 68fa ldr r2, [r7, #12] 80078ac: 440a add r2, r1 80078ae: f502 6210 add.w r2, r2, #2304 @ 0x900 80078b2: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 80078b6: 6013 str r3, [r2, #0] USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; 80078b8: 68bb ldr r3, [r7, #8] 80078ba: 015a lsls r2, r3, #5 80078bc: 68fb ldr r3, [r7, #12] 80078be: 4413 add r3, r2 80078c0: f503 6310 add.w r3, r3, #2304 @ 0x900 80078c4: 681b ldr r3, [r3, #0] 80078c6: 68ba ldr r2, [r7, #8] 80078c8: 0151 lsls r1, r2, #5 80078ca: 68fa ldr r2, [r7, #12] 80078cc: 440a add r2, r1 80078ce: f502 6210 add.w r2, r2, #2304 @ 0x900 80078d2: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80078d6: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 80078d8: 68fb ldr r3, [r7, #12] 80078da: f503 6300 add.w r3, r3, #2048 @ 0x800 80078de: 6bda ldr r2, [r3, #60] @ 0x3c 80078e0: 683b ldr r3, [r7, #0] 80078e2: 781b ldrb r3, [r3, #0] 80078e4: f003 030f and.w r3, r3, #15 80078e8: 2101 movs r1, #1 80078ea: fa01 f303 lsl.w r3, r1, r3 80078ee: b29b uxth r3, r3 80078f0: 43db mvns r3, r3 80078f2: 68f9 ldr r1, [r7, #12] 80078f4: f501 6100 add.w r1, r1, #2048 @ 0x800 80078f8: 4013 ands r3, r2 80078fa: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 80078fc: 68fb ldr r3, [r7, #12] 80078fe: f503 6300 add.w r3, r3, #2048 @ 0x800 8007902: 69da ldr r2, [r3, #28] 8007904: 683b ldr r3, [r7, #0] 8007906: 781b ldrb r3, [r3, #0] 8007908: f003 030f and.w r3, r3, #15 800790c: 2101 movs r1, #1 800790e: fa01 f303 lsl.w r3, r1, r3 8007912: b29b uxth r3, r3 8007914: 43db mvns r3, r3 8007916: 68f9 ldr r1, [r7, #12] 8007918: f501 6100 add.w r1, r1, #2048 @ 0x800 800791c: 4013 ands r3, r2 800791e: 61cb str r3, [r1, #28] USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | 8007920: 68bb ldr r3, [r7, #8] 8007922: 015a lsls r2, r3, #5 8007924: 68fb ldr r3, [r7, #12] 8007926: 4413 add r3, r2 8007928: f503 6310 add.w r3, r3, #2304 @ 0x900 800792c: 681a ldr r2, [r3, #0] 800792e: 68bb ldr r3, [r7, #8] 8007930: 0159 lsls r1, r3, #5 8007932: 68fb ldr r3, [r7, #12] 8007934: 440b add r3, r1 8007936: f503 6310 add.w r3, r3, #2304 @ 0x900 800793a: 4619 mov r1, r3 800793c: 4b35 ldr r3, [pc, #212] @ (8007a14 ) 800793e: 4013 ands r3, r2 8007940: 600b str r3, [r1, #0] 8007942: e060 b.n 8007a06 USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_EPTYP); } else { if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007944: 68bb ldr r3, [r7, #8] 8007946: 015a lsls r2, r3, #5 8007948: 68fb ldr r3, [r7, #12] 800794a: 4413 add r3, r2 800794c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007950: 681b ldr r3, [r3, #0] 8007952: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007956: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800795a: d11f bne.n 800799c { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 800795c: 68bb ldr r3, [r7, #8] 800795e: 015a lsls r2, r3, #5 8007960: 68fb ldr r3, [r7, #12] 8007962: 4413 add r3, r2 8007964: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007968: 681b ldr r3, [r3, #0] 800796a: 68ba ldr r2, [r7, #8] 800796c: 0151 lsls r1, r2, #5 800796e: 68fa ldr r2, [r7, #12] 8007970: 440a add r2, r1 8007972: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007976: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800797a: 6013 str r3, [r2, #0] USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; 800797c: 68bb ldr r3, [r7, #8] 800797e: 015a lsls r2, r3, #5 8007980: 68fb ldr r3, [r7, #12] 8007982: 4413 add r3, r2 8007984: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007988: 681b ldr r3, [r3, #0] 800798a: 68ba ldr r2, [r7, #8] 800798c: 0151 lsls r1, r2, #5 800798e: 68fa ldr r2, [r7, #12] 8007990: 440a add r2, r1 8007992: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007996: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800799a: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 800799c: 68fb ldr r3, [r7, #12] 800799e: f503 6300 add.w r3, r3, #2048 @ 0x800 80079a2: 6bda ldr r2, [r3, #60] @ 0x3c 80079a4: 683b ldr r3, [r7, #0] 80079a6: 781b ldrb r3, [r3, #0] 80079a8: f003 030f and.w r3, r3, #15 80079ac: 2101 movs r1, #1 80079ae: fa01 f303 lsl.w r3, r1, r3 80079b2: 041b lsls r3, r3, #16 80079b4: 43db mvns r3, r3 80079b6: 68f9 ldr r1, [r7, #12] 80079b8: f501 6100 add.w r1, r1, #2048 @ 0x800 80079bc: 4013 ands r3, r2 80079be: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 80079c0: 68fb ldr r3, [r7, #12] 80079c2: f503 6300 add.w r3, r3, #2048 @ 0x800 80079c6: 69da ldr r2, [r3, #28] 80079c8: 683b ldr r3, [r7, #0] 80079ca: 781b ldrb r3, [r3, #0] 80079cc: f003 030f and.w r3, r3, #15 80079d0: 2101 movs r1, #1 80079d2: fa01 f303 lsl.w r3, r1, r3 80079d6: 041b lsls r3, r3, #16 80079d8: 43db mvns r3, r3 80079da: 68f9 ldr r1, [r7, #12] 80079dc: f501 6100 add.w r1, r1, #2048 @ 0x800 80079e0: 4013 ands r3, r2 80079e2: 61cb str r3, [r1, #28] USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | 80079e4: 68bb ldr r3, [r7, #8] 80079e6: 015a lsls r2, r3, #5 80079e8: 68fb ldr r3, [r7, #12] 80079ea: 4413 add r3, r2 80079ec: f503 6330 add.w r3, r3, #2816 @ 0xb00 80079f0: 681a ldr r2, [r3, #0] 80079f2: 68bb ldr r3, [r7, #8] 80079f4: 0159 lsls r1, r3, #5 80079f6: 68fb ldr r3, [r7, #12] 80079f8: 440b add r3, r1 80079fa: f503 6330 add.w r3, r3, #2816 @ 0xb00 80079fe: 4619 mov r1, r3 8007a00: 4b05 ldr r3, [pc, #20] @ (8007a18 ) 8007a02: 4013 ands r3, r2 8007a04: 600b str r3, [r1, #0] USB_OTG_DOEPCTL_MPSIZ | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_EPTYP); } return HAL_OK; 8007a06: 2300 movs r3, #0 } 8007a08: 4618 mov r0, r3 8007a0a: 3714 adds r7, #20 8007a0c: 46bd mov sp, r7 8007a0e: f85d 7b04 ldr.w r7, [sp], #4 8007a12: 4770 bx lr 8007a14: ec337800 .word 0xec337800 8007a18: eff37800 .word 0xeff37800 08007a1c : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 8007a1c: b580 push {r7, lr} 8007a1e: b08a sub sp, #40 @ 0x28 8007a20: af02 add r7, sp, #8 8007a22: 60f8 str r0, [r7, #12] 8007a24: 60b9 str r1, [r7, #8] 8007a26: 4613 mov r3, r2 8007a28: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 8007a2a: 68fb ldr r3, [r7, #12] 8007a2c: 61fb str r3, [r7, #28] uint32_t epnum = (uint32_t)ep->num; 8007a2e: 68bb ldr r3, [r7, #8] 8007a30: 781b ldrb r3, [r3, #0] 8007a32: 61bb str r3, [r7, #24] uint16_t pktcnt; /* IN endpoint */ if (ep->is_in == 1U) 8007a34: 68bb ldr r3, [r7, #8] 8007a36: 785b ldrb r3, [r3, #1] 8007a38: 2b01 cmp r3, #1 8007a3a: f040 817f bne.w 8007d3c { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 8007a3e: 68bb ldr r3, [r7, #8] 8007a40: 691b ldr r3, [r3, #16] 8007a42: 2b00 cmp r3, #0 8007a44: d132 bne.n 8007aac { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8007a46: 69bb ldr r3, [r7, #24] 8007a48: 015a lsls r2, r3, #5 8007a4a: 69fb ldr r3, [r7, #28] 8007a4c: 4413 add r3, r2 8007a4e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a52: 691b ldr r3, [r3, #16] 8007a54: 69ba ldr r2, [r7, #24] 8007a56: 0151 lsls r1, r2, #5 8007a58: 69fa ldr r2, [r7, #28] 8007a5a: 440a add r2, r1 8007a5c: f502 6210 add.w r2, r2, #2304 @ 0x900 8007a60: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007a64: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8007a68: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8007a6a: 69bb ldr r3, [r7, #24] 8007a6c: 015a lsls r2, r3, #5 8007a6e: 69fb ldr r3, [r7, #28] 8007a70: 4413 add r3, r2 8007a72: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a76: 691b ldr r3, [r3, #16] 8007a78: 69ba ldr r2, [r7, #24] 8007a7a: 0151 lsls r1, r2, #5 8007a7c: 69fa ldr r2, [r7, #28] 8007a7e: 440a add r2, r1 8007a80: f502 6210 add.w r2, r2, #2304 @ 0x900 8007a84: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007a88: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8007a8a: 69bb ldr r3, [r7, #24] 8007a8c: 015a lsls r2, r3, #5 8007a8e: 69fb ldr r3, [r7, #28] 8007a90: 4413 add r3, r2 8007a92: f503 6310 add.w r3, r3, #2304 @ 0x900 8007a96: 691b ldr r3, [r3, #16] 8007a98: 69ba ldr r2, [r7, #24] 8007a9a: 0151 lsls r1, r2, #5 8007a9c: 69fa ldr r2, [r7, #28] 8007a9e: 440a add r2, r1 8007aa0: f502 6210 add.w r2, r2, #2304 @ 0x900 8007aa4: 0cdb lsrs r3, r3, #19 8007aa6: 04db lsls r3, r3, #19 8007aa8: 6113 str r3, [r2, #16] 8007aaa: e097 b.n 8007bdc /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8007aac: 69bb ldr r3, [r7, #24] 8007aae: 015a lsls r2, r3, #5 8007ab0: 69fb ldr r3, [r7, #28] 8007ab2: 4413 add r3, r2 8007ab4: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ab8: 691b ldr r3, [r3, #16] 8007aba: 69ba ldr r2, [r7, #24] 8007abc: 0151 lsls r1, r2, #5 8007abe: 69fa ldr r2, [r7, #28] 8007ac0: 440a add r2, r1 8007ac2: f502 6210 add.w r2, r2, #2304 @ 0x900 8007ac6: 0cdb lsrs r3, r3, #19 8007ac8: 04db lsls r3, r3, #19 8007aca: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8007acc: 69bb ldr r3, [r7, #24] 8007ace: 015a lsls r2, r3, #5 8007ad0: 69fb ldr r3, [r7, #28] 8007ad2: 4413 add r3, r2 8007ad4: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ad8: 691b ldr r3, [r3, #16] 8007ada: 69ba ldr r2, [r7, #24] 8007adc: 0151 lsls r1, r2, #5 8007ade: 69fa ldr r2, [r7, #28] 8007ae0: 440a add r2, r1 8007ae2: f502 6210 add.w r2, r2, #2304 @ 0x900 8007ae6: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007aea: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8007aee: 6113 str r3, [r2, #16] if (epnum == 0U) 8007af0: 69bb ldr r3, [r7, #24] 8007af2: 2b00 cmp r3, #0 8007af4: d11a bne.n 8007b2c { if (ep->xfer_len > ep->maxpacket) 8007af6: 68bb ldr r3, [r7, #8] 8007af8: 691a ldr r2, [r3, #16] 8007afa: 68bb ldr r3, [r7, #8] 8007afc: 689b ldr r3, [r3, #8] 8007afe: 429a cmp r2, r3 8007b00: d903 bls.n 8007b0a { ep->xfer_len = ep->maxpacket; 8007b02: 68bb ldr r3, [r7, #8] 8007b04: 689a ldr r2, [r3, #8] 8007b06: 68bb ldr r3, [r7, #8] 8007b08: 611a str r2, [r3, #16] } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8007b0a: 69bb ldr r3, [r7, #24] 8007b0c: 015a lsls r2, r3, #5 8007b0e: 69fb ldr r3, [r7, #28] 8007b10: 4413 add r3, r2 8007b12: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b16: 691b ldr r3, [r3, #16] 8007b18: 69ba ldr r2, [r7, #24] 8007b1a: 0151 lsls r1, r2, #5 8007b1c: 69fa ldr r2, [r7, #28] 8007b1e: 440a add r2, r1 8007b20: f502 6210 add.w r2, r2, #2304 @ 0x900 8007b24: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007b28: 6113 str r3, [r2, #16] 8007b2a: e044 b.n 8007bb6 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8007b2c: 68bb ldr r3, [r7, #8] 8007b2e: 691a ldr r2, [r3, #16] 8007b30: 68bb ldr r3, [r7, #8] 8007b32: 689b ldr r3, [r3, #8] 8007b34: 4413 add r3, r2 8007b36: 1e5a subs r2, r3, #1 8007b38: 68bb ldr r3, [r7, #8] 8007b3a: 689b ldr r3, [r3, #8] 8007b3c: fbb2 f3f3 udiv r3, r2, r3 8007b40: 82fb strh r3, [r7, #22] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); 8007b42: 69bb ldr r3, [r7, #24] 8007b44: 015a lsls r2, r3, #5 8007b46: 69fb ldr r3, [r7, #28] 8007b48: 4413 add r3, r2 8007b4a: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b4e: 691a ldr r2, [r3, #16] 8007b50: 8afb ldrh r3, [r7, #22] 8007b52: 04d9 lsls r1, r3, #19 8007b54: 4ba4 ldr r3, [pc, #656] @ (8007de8 ) 8007b56: 400b ands r3, r1 8007b58: 69b9 ldr r1, [r7, #24] 8007b5a: 0148 lsls r0, r1, #5 8007b5c: 69f9 ldr r1, [r7, #28] 8007b5e: 4401 add r1, r0 8007b60: f501 6110 add.w r1, r1, #2304 @ 0x900 8007b64: 4313 orrs r3, r2 8007b66: 610b str r3, [r1, #16] if (ep->type == EP_TYPE_ISOC) 8007b68: 68bb ldr r3, [r7, #8] 8007b6a: 791b ldrb r3, [r3, #4] 8007b6c: 2b01 cmp r3, #1 8007b6e: d122 bne.n 8007bb6 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 8007b70: 69bb ldr r3, [r7, #24] 8007b72: 015a lsls r2, r3, #5 8007b74: 69fb ldr r3, [r7, #28] 8007b76: 4413 add r3, r2 8007b78: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b7c: 691b ldr r3, [r3, #16] 8007b7e: 69ba ldr r2, [r7, #24] 8007b80: 0151 lsls r1, r2, #5 8007b82: 69fa ldr r2, [r7, #28] 8007b84: 440a add r2, r1 8007b86: f502 6210 add.w r2, r2, #2304 @ 0x900 8007b8a: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000 8007b8e: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); 8007b90: 69bb ldr r3, [r7, #24] 8007b92: 015a lsls r2, r3, #5 8007b94: 69fb ldr r3, [r7, #28] 8007b96: 4413 add r3, r2 8007b98: f503 6310 add.w r3, r3, #2304 @ 0x900 8007b9c: 691a ldr r2, [r3, #16] 8007b9e: 8afb ldrh r3, [r7, #22] 8007ba0: 075b lsls r3, r3, #29 8007ba2: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000 8007ba6: 69b9 ldr r1, [r7, #24] 8007ba8: 0148 lsls r0, r1, #5 8007baa: 69f9 ldr r1, [r7, #28] 8007bac: 4401 add r1, r0 8007bae: f501 6110 add.w r1, r1, #2304 @ 0x900 8007bb2: 4313 orrs r3, r2 8007bb4: 610b str r3, [r1, #16] } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 8007bb6: 69bb ldr r3, [r7, #24] 8007bb8: 015a lsls r2, r3, #5 8007bba: 69fb ldr r3, [r7, #28] 8007bbc: 4413 add r3, r2 8007bbe: f503 6310 add.w r3, r3, #2304 @ 0x900 8007bc2: 691a ldr r2, [r3, #16] 8007bc4: 68bb ldr r3, [r7, #8] 8007bc6: 691b ldr r3, [r3, #16] 8007bc8: f3c3 0312 ubfx r3, r3, #0, #19 8007bcc: 69b9 ldr r1, [r7, #24] 8007bce: 0148 lsls r0, r1, #5 8007bd0: 69f9 ldr r1, [r7, #28] 8007bd2: 4401 add r1, r0 8007bd4: f501 6110 add.w r1, r1, #2304 @ 0x900 8007bd8: 4313 orrs r3, r2 8007bda: 610b str r3, [r1, #16] } if (dma == 1U) 8007bdc: 79fb ldrb r3, [r7, #7] 8007bde: 2b01 cmp r3, #1 8007be0: d14b bne.n 8007c7a { if ((uint32_t)ep->dma_addr != 0U) 8007be2: 68bb ldr r3, [r7, #8] 8007be4: 69db ldr r3, [r3, #28] 8007be6: 2b00 cmp r3, #0 8007be8: d009 beq.n 8007bfe { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 8007bea: 69bb ldr r3, [r7, #24] 8007bec: 015a lsls r2, r3, #5 8007bee: 69fb ldr r3, [r7, #28] 8007bf0: 4413 add r3, r2 8007bf2: f503 6310 add.w r3, r3, #2304 @ 0x900 8007bf6: 461a mov r2, r3 8007bf8: 68bb ldr r3, [r7, #8] 8007bfa: 69db ldr r3, [r3, #28] 8007bfc: 6153 str r3, [r2, #20] } if (ep->type == EP_TYPE_ISOC) 8007bfe: 68bb ldr r3, [r7, #8] 8007c00: 791b ldrb r3, [r3, #4] 8007c02: 2b01 cmp r3, #1 8007c04: d128 bne.n 8007c58 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007c06: 69fb ldr r3, [r7, #28] 8007c08: f503 6300 add.w r3, r3, #2048 @ 0x800 8007c0c: 689b ldr r3, [r3, #8] 8007c0e: f403 7380 and.w r3, r3, #256 @ 0x100 8007c12: 2b00 cmp r3, #0 8007c14: d110 bne.n 8007c38 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8007c16: 69bb ldr r3, [r7, #24] 8007c18: 015a lsls r2, r3, #5 8007c1a: 69fb ldr r3, [r7, #28] 8007c1c: 4413 add r3, r2 8007c1e: f503 6310 add.w r3, r3, #2304 @ 0x900 8007c22: 681b ldr r3, [r3, #0] 8007c24: 69ba ldr r2, [r7, #24] 8007c26: 0151 lsls r1, r2, #5 8007c28: 69fa ldr r2, [r7, #28] 8007c2a: 440a add r2, r1 8007c2c: f502 6210 add.w r2, r2, #2304 @ 0x900 8007c30: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007c34: 6013 str r3, [r2, #0] 8007c36: e00f b.n 8007c58 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8007c38: 69bb ldr r3, [r7, #24] 8007c3a: 015a lsls r2, r3, #5 8007c3c: 69fb ldr r3, [r7, #28] 8007c3e: 4413 add r3, r2 8007c40: f503 6310 add.w r3, r3, #2304 @ 0x900 8007c44: 681b ldr r3, [r3, #0] 8007c46: 69ba ldr r2, [r7, #24] 8007c48: 0151 lsls r1, r2, #5 8007c4a: 69fa ldr r2, [r7, #28] 8007c4c: 440a add r2, r1 8007c4e: f502 6210 add.w r2, r2, #2304 @ 0x900 8007c52: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007c56: 6013 str r3, [r2, #0] } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8007c58: 69bb ldr r3, [r7, #24] 8007c5a: 015a lsls r2, r3, #5 8007c5c: 69fb ldr r3, [r7, #28] 8007c5e: 4413 add r3, r2 8007c60: f503 6310 add.w r3, r3, #2304 @ 0x900 8007c64: 681b ldr r3, [r3, #0] 8007c66: 69ba ldr r2, [r7, #24] 8007c68: 0151 lsls r1, r2, #5 8007c6a: 69fa ldr r2, [r7, #28] 8007c6c: 440a add r2, r1 8007c6e: f502 6210 add.w r2, r2, #2304 @ 0x900 8007c72: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007c76: 6013 str r3, [r2, #0] 8007c78: e166 b.n 8007f48 } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8007c7a: 69bb ldr r3, [r7, #24] 8007c7c: 015a lsls r2, r3, #5 8007c7e: 69fb ldr r3, [r7, #28] 8007c80: 4413 add r3, r2 8007c82: f503 6310 add.w r3, r3, #2304 @ 0x900 8007c86: 681b ldr r3, [r3, #0] 8007c88: 69ba ldr r2, [r7, #24] 8007c8a: 0151 lsls r1, r2, #5 8007c8c: 69fa ldr r2, [r7, #28] 8007c8e: 440a add r2, r1 8007c90: f502 6210 add.w r2, r2, #2304 @ 0x900 8007c94: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007c98: 6013 str r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 8007c9a: 68bb ldr r3, [r7, #8] 8007c9c: 791b ldrb r3, [r3, #4] 8007c9e: 2b01 cmp r3, #1 8007ca0: d015 beq.n 8007cce { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 8007ca2: 68bb ldr r3, [r7, #8] 8007ca4: 691b ldr r3, [r3, #16] 8007ca6: 2b00 cmp r3, #0 8007ca8: f000 814e beq.w 8007f48 { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 8007cac: 69fb ldr r3, [r7, #28] 8007cae: f503 6300 add.w r3, r3, #2048 @ 0x800 8007cb2: 6b5a ldr r2, [r3, #52] @ 0x34 8007cb4: 68bb ldr r3, [r7, #8] 8007cb6: 781b ldrb r3, [r3, #0] 8007cb8: f003 030f and.w r3, r3, #15 8007cbc: 2101 movs r1, #1 8007cbe: fa01 f303 lsl.w r3, r1, r3 8007cc2: 69f9 ldr r1, [r7, #28] 8007cc4: f501 6100 add.w r1, r1, #2048 @ 0x800 8007cc8: 4313 orrs r3, r2 8007cca: 634b str r3, [r1, #52] @ 0x34 8007ccc: e13c b.n 8007f48 } } else { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007cce: 69fb ldr r3, [r7, #28] 8007cd0: f503 6300 add.w r3, r3, #2048 @ 0x800 8007cd4: 689b ldr r3, [r3, #8] 8007cd6: f403 7380 and.w r3, r3, #256 @ 0x100 8007cda: 2b00 cmp r3, #0 8007cdc: d110 bne.n 8007d00 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8007cde: 69bb ldr r3, [r7, #24] 8007ce0: 015a lsls r2, r3, #5 8007ce2: 69fb ldr r3, [r7, #28] 8007ce4: 4413 add r3, r2 8007ce6: f503 6310 add.w r3, r3, #2304 @ 0x900 8007cea: 681b ldr r3, [r3, #0] 8007cec: 69ba ldr r2, [r7, #24] 8007cee: 0151 lsls r1, r2, #5 8007cf0: 69fa ldr r2, [r7, #28] 8007cf2: 440a add r2, r1 8007cf4: f502 6210 add.w r2, r2, #2304 @ 0x900 8007cf8: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007cfc: 6013 str r3, [r2, #0] 8007cfe: e00f b.n 8007d20 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8007d00: 69bb ldr r3, [r7, #24] 8007d02: 015a lsls r2, r3, #5 8007d04: 69fb ldr r3, [r7, #28] 8007d06: 4413 add r3, r2 8007d08: f503 6310 add.w r3, r3, #2304 @ 0x900 8007d0c: 681b ldr r3, [r3, #0] 8007d0e: 69ba ldr r2, [r7, #24] 8007d10: 0151 lsls r1, r2, #5 8007d12: 69fa ldr r2, [r7, #28] 8007d14: 440a add r2, r1 8007d16: f502 6210 add.w r2, r2, #2304 @ 0x900 8007d1a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007d1e: 6013 str r3, [r2, #0] } (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); 8007d20: 68bb ldr r3, [r7, #8] 8007d22: 68d9 ldr r1, [r3, #12] 8007d24: 68bb ldr r3, [r7, #8] 8007d26: 781a ldrb r2, [r3, #0] 8007d28: 68bb ldr r3, [r7, #8] 8007d2a: 691b ldr r3, [r3, #16] 8007d2c: b298 uxth r0, r3 8007d2e: 79fb ldrb r3, [r7, #7] 8007d30: 9300 str r3, [sp, #0] 8007d32: 4603 mov r3, r0 8007d34: 68f8 ldr r0, [r7, #12] 8007d36: f000 f9b9 bl 80080ac 8007d3a: e105 b.n 8007f48 { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 8007d3c: 69bb ldr r3, [r7, #24] 8007d3e: 015a lsls r2, r3, #5 8007d40: 69fb ldr r3, [r7, #28] 8007d42: 4413 add r3, r2 8007d44: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d48: 691b ldr r3, [r3, #16] 8007d4a: 69ba ldr r2, [r7, #24] 8007d4c: 0151 lsls r1, r2, #5 8007d4e: 69fa ldr r2, [r7, #28] 8007d50: 440a add r2, r1 8007d52: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007d56: 0cdb lsrs r3, r3, #19 8007d58: 04db lsls r3, r3, #19 8007d5a: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 8007d5c: 69bb ldr r3, [r7, #24] 8007d5e: 015a lsls r2, r3, #5 8007d60: 69fb ldr r3, [r7, #28] 8007d62: 4413 add r3, r2 8007d64: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d68: 691b ldr r3, [r3, #16] 8007d6a: 69ba ldr r2, [r7, #24] 8007d6c: 0151 lsls r1, r2, #5 8007d6e: 69fa ldr r2, [r7, #28] 8007d70: 440a add r2, r1 8007d72: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007d76: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8007d7a: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8007d7e: 6113 str r3, [r2, #16] if (epnum == 0U) 8007d80: 69bb ldr r3, [r7, #24] 8007d82: 2b00 cmp r3, #0 8007d84: d132 bne.n 8007dec { if (ep->xfer_len > 0U) 8007d86: 68bb ldr r3, [r7, #8] 8007d88: 691b ldr r3, [r3, #16] 8007d8a: 2b00 cmp r3, #0 8007d8c: d003 beq.n 8007d96 { ep->xfer_len = ep->maxpacket; 8007d8e: 68bb ldr r3, [r7, #8] 8007d90: 689a ldr r2, [r3, #8] 8007d92: 68bb ldr r3, [r7, #8] 8007d94: 611a str r2, [r3, #16] } /* Store transfer size, for EP0 this is equal to endpoint max packet size */ ep->xfer_size = ep->maxpacket; 8007d96: 68bb ldr r3, [r7, #8] 8007d98: 689a ldr r2, [r3, #8] 8007d9a: 68bb ldr r3, [r7, #8] 8007d9c: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); 8007d9e: 69bb ldr r3, [r7, #24] 8007da0: 015a lsls r2, r3, #5 8007da2: 69fb ldr r3, [r7, #28] 8007da4: 4413 add r3, r2 8007da6: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007daa: 691a ldr r2, [r3, #16] 8007dac: 68bb ldr r3, [r7, #8] 8007dae: 6a1b ldr r3, [r3, #32] 8007db0: f3c3 0312 ubfx r3, r3, #0, #19 8007db4: 69b9 ldr r1, [r7, #24] 8007db6: 0148 lsls r0, r1, #5 8007db8: 69f9 ldr r1, [r7, #28] 8007dba: 4401 add r1, r0 8007dbc: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007dc0: 4313 orrs r3, r2 8007dc2: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8007dc4: 69bb ldr r3, [r7, #24] 8007dc6: 015a lsls r2, r3, #5 8007dc8: 69fb ldr r3, [r7, #28] 8007dca: 4413 add r3, r2 8007dcc: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007dd0: 691b ldr r3, [r3, #16] 8007dd2: 69ba ldr r2, [r7, #24] 8007dd4: 0151 lsls r1, r2, #5 8007dd6: 69fa ldr r2, [r7, #28] 8007dd8: 440a add r2, r1 8007dda: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007dde: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007de2: 6113 str r3, [r2, #16] 8007de4: e062 b.n 8007eac 8007de6: bf00 nop 8007de8: 1ff80000 .word 0x1ff80000 } else { if (ep->xfer_len == 0U) 8007dec: 68bb ldr r3, [r7, #8] 8007dee: 691b ldr r3, [r3, #16] 8007df0: 2b00 cmp r3, #0 8007df2: d123 bne.n 8007e3c { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 8007df4: 69bb ldr r3, [r7, #24] 8007df6: 015a lsls r2, r3, #5 8007df8: 69fb ldr r3, [r7, #28] 8007dfa: 4413 add r3, r2 8007dfc: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e00: 691a ldr r2, [r3, #16] 8007e02: 68bb ldr r3, [r7, #8] 8007e04: 689b ldr r3, [r3, #8] 8007e06: f3c3 0312 ubfx r3, r3, #0, #19 8007e0a: 69b9 ldr r1, [r7, #24] 8007e0c: 0148 lsls r0, r1, #5 8007e0e: 69f9 ldr r1, [r7, #28] 8007e10: 4401 add r1, r0 8007e12: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007e16: 4313 orrs r3, r2 8007e18: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8007e1a: 69bb ldr r3, [r7, #24] 8007e1c: 015a lsls r2, r3, #5 8007e1e: 69fb ldr r3, [r7, #28] 8007e20: 4413 add r3, r2 8007e22: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e26: 691b ldr r3, [r3, #16] 8007e28: 69ba ldr r2, [r7, #24] 8007e2a: 0151 lsls r1, r2, #5 8007e2c: 69fa ldr r2, [r7, #28] 8007e2e: 440a add r2, r1 8007e30: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007e34: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8007e38: 6113 str r3, [r2, #16] 8007e3a: e037 b.n 8007eac } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8007e3c: 68bb ldr r3, [r7, #8] 8007e3e: 691a ldr r2, [r3, #16] 8007e40: 68bb ldr r3, [r7, #8] 8007e42: 689b ldr r3, [r3, #8] 8007e44: 4413 add r3, r2 8007e46: 1e5a subs r2, r3, #1 8007e48: 68bb ldr r3, [r7, #8] 8007e4a: 689b ldr r3, [r3, #8] 8007e4c: fbb2 f3f3 udiv r3, r2, r3 8007e50: 82fb strh r3, [r7, #22] ep->xfer_size = ep->maxpacket * pktcnt; 8007e52: 68bb ldr r3, [r7, #8] 8007e54: 689b ldr r3, [r3, #8] 8007e56: 8afa ldrh r2, [r7, #22] 8007e58: fb03 f202 mul.w r2, r3, r2 8007e5c: 68bb ldr r3, [r7, #8] 8007e5e: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); 8007e60: 69bb ldr r3, [r7, #24] 8007e62: 015a lsls r2, r3, #5 8007e64: 69fb ldr r3, [r7, #28] 8007e66: 4413 add r3, r2 8007e68: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e6c: 691a ldr r2, [r3, #16] 8007e6e: 8afb ldrh r3, [r7, #22] 8007e70: 04d9 lsls r1, r3, #19 8007e72: 4b38 ldr r3, [pc, #224] @ (8007f54 ) 8007e74: 400b ands r3, r1 8007e76: 69b9 ldr r1, [r7, #24] 8007e78: 0148 lsls r0, r1, #5 8007e7a: 69f9 ldr r1, [r7, #28] 8007e7c: 4401 add r1, r0 8007e7e: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007e82: 4313 orrs r3, r2 8007e84: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; 8007e86: 69bb ldr r3, [r7, #24] 8007e88: 015a lsls r2, r3, #5 8007e8a: 69fb ldr r3, [r7, #28] 8007e8c: 4413 add r3, r2 8007e8e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007e92: 691a ldr r2, [r3, #16] 8007e94: 68bb ldr r3, [r7, #8] 8007e96: 6a1b ldr r3, [r3, #32] 8007e98: f3c3 0312 ubfx r3, r3, #0, #19 8007e9c: 69b9 ldr r1, [r7, #24] 8007e9e: 0148 lsls r0, r1, #5 8007ea0: 69f9 ldr r1, [r7, #28] 8007ea2: 4401 add r1, r0 8007ea4: f501 6130 add.w r1, r1, #2816 @ 0xb00 8007ea8: 4313 orrs r3, r2 8007eaa: 610b str r3, [r1, #16] } } if (dma == 1U) 8007eac: 79fb ldrb r3, [r7, #7] 8007eae: 2b01 cmp r3, #1 8007eb0: d10d bne.n 8007ece { if ((uint32_t)ep->xfer_buff != 0U) 8007eb2: 68bb ldr r3, [r7, #8] 8007eb4: 68db ldr r3, [r3, #12] 8007eb6: 2b00 cmp r3, #0 8007eb8: d009 beq.n 8007ece { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 8007eba: 68bb ldr r3, [r7, #8] 8007ebc: 68d9 ldr r1, [r3, #12] 8007ebe: 69bb ldr r3, [r7, #24] 8007ec0: 015a lsls r2, r3, #5 8007ec2: 69fb ldr r3, [r7, #28] 8007ec4: 4413 add r3, r2 8007ec6: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007eca: 460a mov r2, r1 8007ecc: 615a str r2, [r3, #20] } } if (ep->type == EP_TYPE_ISOC) 8007ece: 68bb ldr r3, [r7, #8] 8007ed0: 791b ldrb r3, [r3, #4] 8007ed2: 2b01 cmp r3, #1 8007ed4: d128 bne.n 8007f28 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8007ed6: 69fb ldr r3, [r7, #28] 8007ed8: f503 6300 add.w r3, r3, #2048 @ 0x800 8007edc: 689b ldr r3, [r3, #8] 8007ede: f403 7380 and.w r3, r3, #256 @ 0x100 8007ee2: 2b00 cmp r3, #0 8007ee4: d110 bne.n 8007f08 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 8007ee6: 69bb ldr r3, [r7, #24] 8007ee8: 015a lsls r2, r3, #5 8007eea: 69fb ldr r3, [r7, #28] 8007eec: 4413 add r3, r2 8007eee: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007ef2: 681b ldr r3, [r3, #0] 8007ef4: 69ba ldr r2, [r7, #24] 8007ef6: 0151 lsls r1, r2, #5 8007ef8: 69fa ldr r2, [r7, #28] 8007efa: 440a add r2, r1 8007efc: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007f00: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8007f04: 6013 str r3, [r2, #0] 8007f06: e00f b.n 8007f28 } else { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 8007f08: 69bb ldr r3, [r7, #24] 8007f0a: 015a lsls r2, r3, #5 8007f0c: 69fb ldr r3, [r7, #28] 8007f0e: 4413 add r3, r2 8007f10: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f14: 681b ldr r3, [r3, #0] 8007f16: 69ba ldr r2, [r7, #24] 8007f18: 0151 lsls r1, r2, #5 8007f1a: 69fa ldr r2, [r7, #28] 8007f1c: 440a add r2, r1 8007f1e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007f22: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007f26: 6013 str r3, [r2, #0] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8007f28: 69bb ldr r3, [r7, #24] 8007f2a: 015a lsls r2, r3, #5 8007f2c: 69fb ldr r3, [r7, #28] 8007f2e: 4413 add r3, r2 8007f30: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007f34: 681b ldr r3, [r3, #0] 8007f36: 69ba ldr r2, [r7, #24] 8007f38: 0151 lsls r1, r2, #5 8007f3a: 69fa ldr r2, [r7, #28] 8007f3c: 440a add r2, r1 8007f3e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8007f42: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8007f46: 6013 str r3, [r2, #0] } return HAL_OK; 8007f48: 2300 movs r3, #0 } 8007f4a: 4618 mov r0, r3 8007f4c: 3720 adds r7, #32 8007f4e: 46bd mov sp, r7 8007f50: bd80 pop {r7, pc} 8007f52: bf00 nop 8007f54: 1ff80000 .word 0x1ff80000 08007f58 : * @param USBx usb device instance * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8007f58: b480 push {r7} 8007f5a: b087 sub sp, #28 8007f5c: af00 add r7, sp, #0 8007f5e: 6078 str r0, [r7, #4] 8007f60: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8007f62: 2300 movs r3, #0 8007f64: 60fb str r3, [r7, #12] HAL_StatusTypeDef ret = HAL_OK; 8007f66: 2300 movs r3, #0 8007f68: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8007f6a: 687b ldr r3, [r7, #4] 8007f6c: 613b str r3, [r7, #16] /* IN endpoint */ if (ep->is_in == 1U) 8007f6e: 683b ldr r3, [r7, #0] 8007f70: 785b ldrb r3, [r3, #1] 8007f72: 2b01 cmp r3, #1 8007f74: d14a bne.n 800800c { /* EP enable, IN data in FIFO */ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007f76: 683b ldr r3, [r7, #0] 8007f78: 781b ldrb r3, [r3, #0] 8007f7a: 015a lsls r2, r3, #5 8007f7c: 693b ldr r3, [r7, #16] 8007f7e: 4413 add r3, r2 8007f80: f503 6310 add.w r3, r3, #2304 @ 0x900 8007f84: 681b ldr r3, [r3, #0] 8007f86: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007f8a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007f8e: f040 8086 bne.w 800809e { USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); 8007f92: 683b ldr r3, [r7, #0] 8007f94: 781b ldrb r3, [r3, #0] 8007f96: 015a lsls r2, r3, #5 8007f98: 693b ldr r3, [r7, #16] 8007f9a: 4413 add r3, r2 8007f9c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007fa0: 681b ldr r3, [r3, #0] 8007fa2: 683a ldr r2, [r7, #0] 8007fa4: 7812 ldrb r2, [r2, #0] 8007fa6: 0151 lsls r1, r2, #5 8007fa8: 693a ldr r2, [r7, #16] 8007faa: 440a add r2, r1 8007fac: f502 6210 add.w r2, r2, #2304 @ 0x900 8007fb0: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8007fb4: 6013 str r3, [r2, #0] USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); 8007fb6: 683b ldr r3, [r7, #0] 8007fb8: 781b ldrb r3, [r3, #0] 8007fba: 015a lsls r2, r3, #5 8007fbc: 693b ldr r3, [r7, #16] 8007fbe: 4413 add r3, r2 8007fc0: f503 6310 add.w r3, r3, #2304 @ 0x900 8007fc4: 681b ldr r3, [r3, #0] 8007fc6: 683a ldr r2, [r7, #0] 8007fc8: 7812 ldrb r2, [r2, #0] 8007fca: 0151 lsls r1, r2, #5 8007fcc: 693a ldr r2, [r7, #16] 8007fce: 440a add r2, r1 8007fd0: f502 6210 add.w r2, r2, #2304 @ 0x900 8007fd4: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007fd8: 6013 str r3, [r2, #0] do { count++; 8007fda: 68fb ldr r3, [r7, #12] 8007fdc: 3301 adds r3, #1 8007fde: 60fb str r3, [r7, #12] if (count > 10000U) 8007fe0: 68fb ldr r3, [r7, #12] 8007fe2: f242 7210 movw r2, #10000 @ 0x2710 8007fe6: 4293 cmp r3, r2 8007fe8: d902 bls.n 8007ff0 { ret = HAL_ERROR; 8007fea: 2301 movs r3, #1 8007fec: 75fb strb r3, [r7, #23] break; 8007fee: e056 b.n 800809e } } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); 8007ff0: 683b ldr r3, [r7, #0] 8007ff2: 781b ldrb r3, [r3, #0] 8007ff4: 015a lsls r2, r3, #5 8007ff6: 693b ldr r3, [r7, #16] 8007ff8: 4413 add r3, r2 8007ffa: f503 6310 add.w r3, r3, #2304 @ 0x900 8007ffe: 681b ldr r3, [r3, #0] 8008000: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008004: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008008: d0e7 beq.n 8007fda 800800a: e048 b.n 800809e } } else /* OUT endpoint */ { if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 800800c: 683b ldr r3, [r7, #0] 800800e: 781b ldrb r3, [r3, #0] 8008010: 015a lsls r2, r3, #5 8008012: 693b ldr r3, [r7, #16] 8008014: 4413 add r3, r2 8008016: f503 6330 add.w r3, r3, #2816 @ 0xb00 800801a: 681b ldr r3, [r3, #0] 800801c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008020: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008024: d13b bne.n 800809e { USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); 8008026: 683b ldr r3, [r7, #0] 8008028: 781b ldrb r3, [r3, #0] 800802a: 015a lsls r2, r3, #5 800802c: 693b ldr r3, [r7, #16] 800802e: 4413 add r3, r2 8008030: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008034: 681b ldr r3, [r3, #0] 8008036: 683a ldr r2, [r7, #0] 8008038: 7812 ldrb r2, [r2, #0] 800803a: 0151 lsls r1, r2, #5 800803c: 693a ldr r2, [r7, #16] 800803e: 440a add r2, r1 8008040: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008044: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8008048: 6013 str r3, [r2, #0] USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); 800804a: 683b ldr r3, [r7, #0] 800804c: 781b ldrb r3, [r3, #0] 800804e: 015a lsls r2, r3, #5 8008050: 693b ldr r3, [r7, #16] 8008052: 4413 add r3, r2 8008054: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008058: 681b ldr r3, [r3, #0] 800805a: 683a ldr r2, [r7, #0] 800805c: 7812 ldrb r2, [r2, #0] 800805e: 0151 lsls r1, r2, #5 8008060: 693a ldr r2, [r7, #16] 8008062: 440a add r2, r1 8008064: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008068: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800806c: 6013 str r3, [r2, #0] do { count++; 800806e: 68fb ldr r3, [r7, #12] 8008070: 3301 adds r3, #1 8008072: 60fb str r3, [r7, #12] if (count > 10000U) 8008074: 68fb ldr r3, [r7, #12] 8008076: f242 7210 movw r2, #10000 @ 0x2710 800807a: 4293 cmp r3, r2 800807c: d902 bls.n 8008084 { ret = HAL_ERROR; 800807e: 2301 movs r3, #1 8008080: 75fb strb r3, [r7, #23] break; 8008082: e00c b.n 800809e } } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); 8008084: 683b ldr r3, [r7, #0] 8008086: 781b ldrb r3, [r3, #0] 8008088: 015a lsls r2, r3, #5 800808a: 693b ldr r3, [r7, #16] 800808c: 4413 add r3, r2 800808e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008092: 681b ldr r3, [r3, #0] 8008094: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008098: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800809c: d0e7 beq.n 800806e } } return ret; 800809e: 7dfb ldrb r3, [r7, #23] } 80080a0: 4618 mov r0, r3 80080a2: 371c adds r7, #28 80080a4: 46bd mov sp, r7 80080a6: f85d 7b04 ldr.w r7, [sp], #4 80080aa: 4770 bx lr 080080ac : * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { 80080ac: b480 push {r7} 80080ae: b089 sub sp, #36 @ 0x24 80080b0: af00 add r7, sp, #0 80080b2: 60f8 str r0, [r7, #12] 80080b4: 60b9 str r1, [r7, #8] 80080b6: 4611 mov r1, r2 80080b8: 461a mov r2, r3 80080ba: 460b mov r3, r1 80080bc: 71fb strb r3, [r7, #7] 80080be: 4613 mov r3, r2 80080c0: 80bb strh r3, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80080c2: 68fb ldr r3, [r7, #12] 80080c4: 617b str r3, [r7, #20] uint8_t *pSrc = src; 80080c6: 68bb ldr r3, [r7, #8] 80080c8: 61fb str r3, [r7, #28] uint32_t count32b; uint32_t i; if (dma == 0U) 80080ca: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 80080ce: 2b00 cmp r3, #0 80080d0: d123 bne.n 800811a { count32b = ((uint32_t)len + 3U) / 4U; 80080d2: 88bb ldrh r3, [r7, #4] 80080d4: 3303 adds r3, #3 80080d6: 089b lsrs r3, r3, #2 80080d8: 613b str r3, [r7, #16] for (i = 0U; i < count32b; i++) 80080da: 2300 movs r3, #0 80080dc: 61bb str r3, [r7, #24] 80080de: e018 b.n 8008112 { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); 80080e0: 79fb ldrb r3, [r7, #7] 80080e2: 031a lsls r2, r3, #12 80080e4: 697b ldr r3, [r7, #20] 80080e6: 4413 add r3, r2 80080e8: f503 5380 add.w r3, r3, #4096 @ 0x1000 80080ec: 461a mov r2, r3 80080ee: 69fb ldr r3, [r7, #28] 80080f0: 681b ldr r3, [r3, #0] 80080f2: 6013 str r3, [r2, #0] pSrc++; 80080f4: 69fb ldr r3, [r7, #28] 80080f6: 3301 adds r3, #1 80080f8: 61fb str r3, [r7, #28] pSrc++; 80080fa: 69fb ldr r3, [r7, #28] 80080fc: 3301 adds r3, #1 80080fe: 61fb str r3, [r7, #28] pSrc++; 8008100: 69fb ldr r3, [r7, #28] 8008102: 3301 adds r3, #1 8008104: 61fb str r3, [r7, #28] pSrc++; 8008106: 69fb ldr r3, [r7, #28] 8008108: 3301 adds r3, #1 800810a: 61fb str r3, [r7, #28] for (i = 0U; i < count32b; i++) 800810c: 69bb ldr r3, [r7, #24] 800810e: 3301 adds r3, #1 8008110: 61bb str r3, [r7, #24] 8008112: 69ba ldr r2, [r7, #24] 8008114: 693b ldr r3, [r7, #16] 8008116: 429a cmp r2, r3 8008118: d3e2 bcc.n 80080e0 } } return HAL_OK; 800811a: 2300 movs r3, #0 } 800811c: 4618 mov r0, r3 800811e: 3724 adds r7, #36 @ 0x24 8008120: 46bd mov sp, r7 8008122: f85d 7b04 ldr.w r7, [sp], #4 8008126: 4770 bx lr 08008128 : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 8008128: b480 push {r7} 800812a: b08b sub sp, #44 @ 0x2c 800812c: af00 add r7, sp, #0 800812e: 60f8 str r0, [r7, #12] 8008130: 60b9 str r1, [r7, #8] 8008132: 4613 mov r3, r2 8008134: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 8008136: 68fb ldr r3, [r7, #12] 8008138: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 800813a: 68bb ldr r3, [r7, #8] 800813c: 627b str r3, [r7, #36] @ 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 800813e: 88fb ldrh r3, [r7, #6] 8008140: 089b lsrs r3, r3, #2 8008142: b29b uxth r3, r3 8008144: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 8008146: 88fb ldrh r3, [r7, #6] 8008148: f003 0303 and.w r3, r3, #3 800814c: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 800814e: 2300 movs r3, #0 8008150: 623b str r3, [r7, #32] 8008152: e014 b.n 800817e { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 8008154: 69bb ldr r3, [r7, #24] 8008156: f503 5380 add.w r3, r3, #4096 @ 0x1000 800815a: 681a ldr r2, [r3, #0] 800815c: 6a7b ldr r3, [r7, #36] @ 0x24 800815e: 601a str r2, [r3, #0] pDest++; 8008160: 6a7b ldr r3, [r7, #36] @ 0x24 8008162: 3301 adds r3, #1 8008164: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008166: 6a7b ldr r3, [r7, #36] @ 0x24 8008168: 3301 adds r3, #1 800816a: 627b str r3, [r7, #36] @ 0x24 pDest++; 800816c: 6a7b ldr r3, [r7, #36] @ 0x24 800816e: 3301 adds r3, #1 8008170: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008172: 6a7b ldr r3, [r7, #36] @ 0x24 8008174: 3301 adds r3, #1 8008176: 627b str r3, [r7, #36] @ 0x24 for (i = 0U; i < count32b; i++) 8008178: 6a3b ldr r3, [r7, #32] 800817a: 3301 adds r3, #1 800817c: 623b str r3, [r7, #32] 800817e: 6a3a ldr r2, [r7, #32] 8008180: 697b ldr r3, [r7, #20] 8008182: 429a cmp r2, r3 8008184: d3e6 bcc.n 8008154 } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 8008186: 8bfb ldrh r3, [r7, #30] 8008188: 2b00 cmp r3, #0 800818a: d01e beq.n 80081ca { i = 0U; 800818c: 2300 movs r3, #0 800818e: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 8008190: 69bb ldr r3, [r7, #24] 8008192: f503 5380 add.w r3, r3, #4096 @ 0x1000 8008196: 461a mov r2, r3 8008198: f107 0310 add.w r3, r7, #16 800819c: 6812 ldr r2, [r2, #0] 800819e: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 80081a0: 693a ldr r2, [r7, #16] 80081a2: 6a3b ldr r3, [r7, #32] 80081a4: b2db uxtb r3, r3 80081a6: 00db lsls r3, r3, #3 80081a8: fa22 f303 lsr.w r3, r2, r3 80081ac: b2da uxtb r2, r3 80081ae: 6a7b ldr r3, [r7, #36] @ 0x24 80081b0: 701a strb r2, [r3, #0] i++; 80081b2: 6a3b ldr r3, [r7, #32] 80081b4: 3301 adds r3, #1 80081b6: 623b str r3, [r7, #32] pDest++; 80081b8: 6a7b ldr r3, [r7, #36] @ 0x24 80081ba: 3301 adds r3, #1 80081bc: 627b str r3, [r7, #36] @ 0x24 remaining_bytes--; 80081be: 8bfb ldrh r3, [r7, #30] 80081c0: 3b01 subs r3, #1 80081c2: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 80081c4: 8bfb ldrh r3, [r7, #30] 80081c6: 2b00 cmp r3, #0 80081c8: d1ea bne.n 80081a0 } return ((void *)pDest); 80081ca: 6a7b ldr r3, [r7, #36] @ 0x24 } 80081cc: 4618 mov r0, r3 80081ce: 372c adds r7, #44 @ 0x2c 80081d0: 46bd mov sp, r7 80081d2: f85d 7b04 ldr.w r7, [sp], #4 80081d6: 4770 bx lr 080081d8 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 80081d8: b480 push {r7} 80081da: b085 sub sp, #20 80081dc: af00 add r7, sp, #0 80081de: 6078 str r0, [r7, #4] 80081e0: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80081e2: 687b ldr r3, [r7, #4] 80081e4: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80081e6: 683b ldr r3, [r7, #0] 80081e8: 781b ldrb r3, [r3, #0] 80081ea: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 80081ec: 683b ldr r3, [r7, #0] 80081ee: 785b ldrb r3, [r3, #1] 80081f0: 2b01 cmp r3, #1 80081f2: d12c bne.n 800824e { if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) 80081f4: 68bb ldr r3, [r7, #8] 80081f6: 015a lsls r2, r3, #5 80081f8: 68fb ldr r3, [r7, #12] 80081fa: 4413 add r3, r2 80081fc: f503 6310 add.w r3, r3, #2304 @ 0x900 8008200: 681b ldr r3, [r3, #0] 8008202: 2b00 cmp r3, #0 8008204: db12 blt.n 800822c 8008206: 68bb ldr r3, [r7, #8] 8008208: 2b00 cmp r3, #0 800820a: d00f beq.n 800822c { USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 800820c: 68bb ldr r3, [r7, #8] 800820e: 015a lsls r2, r3, #5 8008210: 68fb ldr r3, [r7, #12] 8008212: 4413 add r3, r2 8008214: f503 6310 add.w r3, r3, #2304 @ 0x900 8008218: 681b ldr r3, [r3, #0] 800821a: 68ba ldr r2, [r7, #8] 800821c: 0151 lsls r1, r2, #5 800821e: 68fa ldr r2, [r7, #12] 8008220: 440a add r2, r1 8008222: f502 6210 add.w r2, r2, #2304 @ 0x900 8008226: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 800822a: 6013 str r3, [r2, #0] } USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 800822c: 68bb ldr r3, [r7, #8] 800822e: 015a lsls r2, r3, #5 8008230: 68fb ldr r3, [r7, #12] 8008232: 4413 add r3, r2 8008234: f503 6310 add.w r3, r3, #2304 @ 0x900 8008238: 681b ldr r3, [r3, #0] 800823a: 68ba ldr r2, [r7, #8] 800823c: 0151 lsls r1, r2, #5 800823e: 68fa ldr r2, [r7, #12] 8008240: 440a add r2, r1 8008242: f502 6210 add.w r2, r2, #2304 @ 0x900 8008246: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 800824a: 6013 str r3, [r2, #0] 800824c: e02b b.n 80082a6 } else { if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) 800824e: 68bb ldr r3, [r7, #8] 8008250: 015a lsls r2, r3, #5 8008252: 68fb ldr r3, [r7, #12] 8008254: 4413 add r3, r2 8008256: f503 6330 add.w r3, r3, #2816 @ 0xb00 800825a: 681b ldr r3, [r3, #0] 800825c: 2b00 cmp r3, #0 800825e: db12 blt.n 8008286 8008260: 68bb ldr r3, [r7, #8] 8008262: 2b00 cmp r3, #0 8008264: d00f beq.n 8008286 { USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 8008266: 68bb ldr r3, [r7, #8] 8008268: 015a lsls r2, r3, #5 800826a: 68fb ldr r3, [r7, #12] 800826c: 4413 add r3, r2 800826e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008272: 681b ldr r3, [r3, #0] 8008274: 68ba ldr r2, [r7, #8] 8008276: 0151 lsls r1, r2, #5 8008278: 68fa ldr r2, [r7, #12] 800827a: 440a add r2, r1 800827c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008280: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8008284: 6013 str r3, [r2, #0] } USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 8008286: 68bb ldr r3, [r7, #8] 8008288: 015a lsls r2, r3, #5 800828a: 68fb ldr r3, [r7, #12] 800828c: 4413 add r3, r2 800828e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008292: 681b ldr r3, [r3, #0] 8008294: 68ba ldr r2, [r7, #8] 8008296: 0151 lsls r1, r2, #5 8008298: 68fa ldr r2, [r7, #12] 800829a: 440a add r2, r1 800829c: f502 6230 add.w r2, r2, #2816 @ 0xb00 80082a0: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 80082a4: 6013 str r3, [r2, #0] } return HAL_OK; 80082a6: 2300 movs r3, #0 } 80082a8: 4618 mov r0, r3 80082aa: 3714 adds r7, #20 80082ac: 46bd mov sp, r7 80082ae: f85d 7b04 ldr.w r7, [sp], #4 80082b2: 4770 bx lr 080082b4 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 80082b4: b480 push {r7} 80082b6: b085 sub sp, #20 80082b8: af00 add r7, sp, #0 80082ba: 6078 str r0, [r7, #4] 80082bc: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80082be: 687b ldr r3, [r7, #4] 80082c0: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80082c2: 683b ldr r3, [r7, #0] 80082c4: 781b ldrb r3, [r3, #0] 80082c6: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 80082c8: 683b ldr r3, [r7, #0] 80082ca: 785b ldrb r3, [r3, #1] 80082cc: 2b01 cmp r3, #1 80082ce: d128 bne.n 8008322 { USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 80082d0: 68bb ldr r3, [r7, #8] 80082d2: 015a lsls r2, r3, #5 80082d4: 68fb ldr r3, [r7, #12] 80082d6: 4413 add r3, r2 80082d8: f503 6310 add.w r3, r3, #2304 @ 0x900 80082dc: 681b ldr r3, [r3, #0] 80082de: 68ba ldr r2, [r7, #8] 80082e0: 0151 lsls r1, r2, #5 80082e2: 68fa ldr r2, [r7, #12] 80082e4: 440a add r2, r1 80082e6: f502 6210 add.w r2, r2, #2304 @ 0x900 80082ea: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 80082ee: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 80082f0: 683b ldr r3, [r7, #0] 80082f2: 791b ldrb r3, [r3, #4] 80082f4: 2b03 cmp r3, #3 80082f6: d003 beq.n 8008300 80082f8: 683b ldr r3, [r7, #0] 80082fa: 791b ldrb r3, [r3, #4] 80082fc: 2b02 cmp r3, #2 80082fe: d138 bne.n 8008372 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8008300: 68bb ldr r3, [r7, #8] 8008302: 015a lsls r2, r3, #5 8008304: 68fb ldr r3, [r7, #12] 8008306: 4413 add r3, r2 8008308: f503 6310 add.w r3, r3, #2304 @ 0x900 800830c: 681b ldr r3, [r3, #0] 800830e: 68ba ldr r2, [r7, #8] 8008310: 0151 lsls r1, r2, #5 8008312: 68fa ldr r2, [r7, #12] 8008314: 440a add r2, r1 8008316: f502 6210 add.w r2, r2, #2304 @ 0x900 800831a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800831e: 6013 str r3, [r2, #0] 8008320: e027 b.n 8008372 } } else { USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 8008322: 68bb ldr r3, [r7, #8] 8008324: 015a lsls r2, r3, #5 8008326: 68fb ldr r3, [r7, #12] 8008328: 4413 add r3, r2 800832a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800832e: 681b ldr r3, [r3, #0] 8008330: 68ba ldr r2, [r7, #8] 8008332: 0151 lsls r1, r2, #5 8008334: 68fa ldr r2, [r7, #12] 8008336: 440a add r2, r1 8008338: f502 6230 add.w r2, r2, #2816 @ 0xb00 800833c: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8008340: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8008342: 683b ldr r3, [r7, #0] 8008344: 791b ldrb r3, [r3, #4] 8008346: 2b03 cmp r3, #3 8008348: d003 beq.n 8008352 800834a: 683b ldr r3, [r7, #0] 800834c: 791b ldrb r3, [r3, #4] 800834e: 2b02 cmp r3, #2 8008350: d10f bne.n 8008372 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8008352: 68bb ldr r3, [r7, #8] 8008354: 015a lsls r2, r3, #5 8008356: 68fb ldr r3, [r7, #12] 8008358: 4413 add r3, r2 800835a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800835e: 681b ldr r3, [r3, #0] 8008360: 68ba ldr r2, [r7, #8] 8008362: 0151 lsls r1, r2, #5 8008364: 68fa ldr r2, [r7, #12] 8008366: 440a add r2, r1 8008368: f502 6230 add.w r2, r2, #2816 @ 0xb00 800836c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008370: 6013 str r3, [r2, #0] } } return HAL_OK; 8008372: 2300 movs r3, #0 } 8008374: 4618 mov r0, r3 8008376: 3714 adds r7, #20 8008378: 46bd mov sp, r7 800837a: f85d 7b04 ldr.w r7, [sp], #4 800837e: 4770 bx lr 08008380 : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { 8008380: b480 push {r7} 8008382: b085 sub sp, #20 8008384: af00 add r7, sp, #0 8008386: 6078 str r0, [r7, #4] 8008388: 460b mov r3, r1 800838a: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 800838c: 687b ldr r3, [r7, #4] 800838e: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); 8008390: 68fb ldr r3, [r7, #12] 8008392: f503 6300 add.w r3, r3, #2048 @ 0x800 8008396: 681b ldr r3, [r3, #0] 8008398: 68fa ldr r2, [r7, #12] 800839a: f502 6200 add.w r2, r2, #2048 @ 0x800 800839e: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 80083a2: 6013 str r3, [r2, #0] USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; 80083a4: 68fb ldr r3, [r7, #12] 80083a6: f503 6300 add.w r3, r3, #2048 @ 0x800 80083aa: 681a ldr r2, [r3, #0] 80083ac: 78fb ldrb r3, [r7, #3] 80083ae: 011b lsls r3, r3, #4 80083b0: f403 63fe and.w r3, r3, #2032 @ 0x7f0 80083b4: 68f9 ldr r1, [r7, #12] 80083b6: f501 6100 add.w r1, r1, #2048 @ 0x800 80083ba: 4313 orrs r3, r2 80083bc: 600b str r3, [r1, #0] return HAL_OK; 80083be: 2300 movs r3, #0 } 80083c0: 4618 mov r0, r3 80083c2: 3714 adds r7, #20 80083c4: 46bd mov sp, r7 80083c6: f85d 7b04 ldr.w r7, [sp], #4 80083ca: 4770 bx lr 080083cc : * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { 80083cc: b480 push {r7} 80083ce: b085 sub sp, #20 80083d0: af00 add r7, sp, #0 80083d2: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80083d4: 687b ldr r3, [r7, #4] 80083d6: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 80083d8: 68fb ldr r3, [r7, #12] 80083da: f503 6360 add.w r3, r3, #3584 @ 0xe00 80083de: 681b ldr r3, [r3, #0] 80083e0: 68fa ldr r2, [r7, #12] 80083e2: f502 6260 add.w r2, r2, #3584 @ 0xe00 80083e6: f023 0303 bic.w r3, r3, #3 80083ea: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; 80083ec: 68fb ldr r3, [r7, #12] 80083ee: f503 6300 add.w r3, r3, #2048 @ 0x800 80083f2: 685b ldr r3, [r3, #4] 80083f4: 68fa ldr r2, [r7, #12] 80083f6: f502 6200 add.w r2, r2, #2048 @ 0x800 80083fa: f023 0302 bic.w r3, r3, #2 80083fe: 6053 str r3, [r2, #4] return HAL_OK; 8008400: 2300 movs r3, #0 } 8008402: 4618 mov r0, r3 8008404: 3714 adds r7, #20 8008406: 46bd mov sp, r7 8008408: f85d 7b04 ldr.w r7, [sp], #4 800840c: 4770 bx lr 0800840e : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { 800840e: b480 push {r7} 8008410: b085 sub sp, #20 8008412: af00 add r7, sp, #0 8008414: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008416: 687b ldr r3, [r7, #4] 8008418: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 800841a: 68fb ldr r3, [r7, #12] 800841c: f503 6360 add.w r3, r3, #3584 @ 0xe00 8008420: 681b ldr r3, [r3, #0] 8008422: 68fa ldr r2, [r7, #12] 8008424: f502 6260 add.w r2, r2, #3584 @ 0xe00 8008428: f023 0303 bic.w r3, r3, #3 800842c: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 800842e: 68fb ldr r3, [r7, #12] 8008430: f503 6300 add.w r3, r3, #2048 @ 0x800 8008434: 685b ldr r3, [r3, #4] 8008436: 68fa ldr r2, [r7, #12] 8008438: f502 6200 add.w r2, r2, #2048 @ 0x800 800843c: f043 0302 orr.w r3, r3, #2 8008440: 6053 str r3, [r2, #4] return HAL_OK; 8008442: 2300 movs r3, #0 } 8008444: 4618 mov r0, r3 8008446: 3714 adds r7, #20 8008448: 46bd mov sp, r7 800844a: f85d 7b04 ldr.w r7, [sp], #4 800844e: 4770 bx lr 08008450 : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { 8008450: b480 push {r7} 8008452: b085 sub sp, #20 8008454: af00 add r7, sp, #0 8008456: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 8008458: 687b ldr r3, [r7, #4] 800845a: 695b ldr r3, [r3, #20] 800845c: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 800845e: 687b ldr r3, [r7, #4] 8008460: 699b ldr r3, [r3, #24] 8008462: 68fa ldr r2, [r7, #12] 8008464: 4013 ands r3, r2 8008466: 60fb str r3, [r7, #12] return tmpreg; 8008468: 68fb ldr r3, [r7, #12] } 800846a: 4618 mov r0, r3 800846c: 3714 adds r7, #20 800846e: 46bd mov sp, r7 8008470: f85d 7b04 ldr.w r7, [sp], #4 8008474: 4770 bx lr 08008476 : * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device * @retval USB Device OUT EP interrupt status */ uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 8008476: b480 push {r7} 8008478: b085 sub sp, #20 800847a: af00 add r7, sp, #0 800847c: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800847e: 687b ldr r3, [r7, #4] 8008480: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8008482: 68fb ldr r3, [r7, #12] 8008484: f503 6300 add.w r3, r3, #2048 @ 0x800 8008488: 699b ldr r3, [r3, #24] 800848a: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 800848c: 68fb ldr r3, [r7, #12] 800848e: f503 6300 add.w r3, r3, #2048 @ 0x800 8008492: 69db ldr r3, [r3, #28] 8008494: 68ba ldr r2, [r7, #8] 8008496: 4013 ands r3, r2 8008498: 60bb str r3, [r7, #8] return ((tmpreg & 0xffff0000U) >> 16); 800849a: 68bb ldr r3, [r7, #8] 800849c: 0c1b lsrs r3, r3, #16 } 800849e: 4618 mov r0, r3 80084a0: 3714 adds r7, #20 80084a2: 46bd mov sp, r7 80084a4: f85d 7b04 ldr.w r7, [sp], #4 80084a8: 4770 bx lr 080084aa : * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device * @retval USB Device IN EP interrupt status */ uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 80084aa: b480 push {r7} 80084ac: b085 sub sp, #20 80084ae: af00 add r7, sp, #0 80084b0: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80084b2: 687b ldr r3, [r7, #4] 80084b4: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 80084b6: 68fb ldr r3, [r7, #12] 80084b8: f503 6300 add.w r3, r3, #2048 @ 0x800 80084bc: 699b ldr r3, [r3, #24] 80084be: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 80084c0: 68fb ldr r3, [r7, #12] 80084c2: f503 6300 add.w r3, r3, #2048 @ 0x800 80084c6: 69db ldr r3, [r3, #28] 80084c8: 68ba ldr r2, [r7, #8] 80084ca: 4013 ands r3, r2 80084cc: 60bb str r3, [r7, #8] return ((tmpreg & 0xFFFFU)); 80084ce: 68bb ldr r3, [r7, #8] 80084d0: b29b uxth r3, r3 } 80084d2: 4618 mov r0, r3 80084d4: 3714 adds r7, #20 80084d6: 46bd mov sp, r7 80084d8: f85d 7b04 ldr.w r7, [sp], #4 80084dc: 4770 bx lr 080084de : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 80084de: b480 push {r7} 80084e0: b085 sub sp, #20 80084e2: af00 add r7, sp, #0 80084e4: 6078 str r0, [r7, #4] 80084e6: 460b mov r3, r1 80084e8: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80084ea: 687b ldr r3, [r7, #4] 80084ec: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; 80084ee: 78fb ldrb r3, [r7, #3] 80084f0: 015a lsls r2, r3, #5 80084f2: 68fb ldr r3, [r7, #12] 80084f4: 4413 add r3, r2 80084f6: f503 6330 add.w r3, r3, #2816 @ 0xb00 80084fa: 689b ldr r3, [r3, #8] 80084fc: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DOEPMSK; 80084fe: 68fb ldr r3, [r7, #12] 8008500: f503 6300 add.w r3, r3, #2048 @ 0x800 8008504: 695b ldr r3, [r3, #20] 8008506: 68ba ldr r2, [r7, #8] 8008508: 4013 ands r3, r2 800850a: 60bb str r3, [r7, #8] return tmpreg; 800850c: 68bb ldr r3, [r7, #8] } 800850e: 4618 mov r0, r3 8008510: 3714 adds r7, #20 8008512: 46bd mov sp, r7 8008514: f85d 7b04 ldr.w r7, [sp], #4 8008518: 4770 bx lr 0800851a : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 800851a: b480 push {r7} 800851c: b087 sub sp, #28 800851e: af00 add r7, sp, #0 8008520: 6078 str r0, [r7, #4] 8008522: 460b mov r3, r1 8008524: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008526: 687b ldr r3, [r7, #4] 8008528: 617b str r3, [r7, #20] uint32_t tmpreg; uint32_t msk; uint32_t emp; msk = USBx_DEVICE->DIEPMSK; 800852a: 697b ldr r3, [r7, #20] 800852c: f503 6300 add.w r3, r3, #2048 @ 0x800 8008530: 691b ldr r3, [r3, #16] 8008532: 613b str r3, [r7, #16] emp = USBx_DEVICE->DIEPEMPMSK; 8008534: 697b ldr r3, [r7, #20] 8008536: f503 6300 add.w r3, r3, #2048 @ 0x800 800853a: 6b5b ldr r3, [r3, #52] @ 0x34 800853c: 60fb str r3, [r7, #12] msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; 800853e: 78fb ldrb r3, [r7, #3] 8008540: f003 030f and.w r3, r3, #15 8008544: 68fa ldr r2, [r7, #12] 8008546: fa22 f303 lsr.w r3, r2, r3 800854a: 01db lsls r3, r3, #7 800854c: b2db uxtb r3, r3 800854e: 693a ldr r2, [r7, #16] 8008550: 4313 orrs r3, r2 8008552: 613b str r3, [r7, #16] tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; 8008554: 78fb ldrb r3, [r7, #3] 8008556: 015a lsls r2, r3, #5 8008558: 697b ldr r3, [r7, #20] 800855a: 4413 add r3, r2 800855c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008560: 689b ldr r3, [r3, #8] 8008562: 693a ldr r2, [r7, #16] 8008564: 4013 ands r3, r2 8008566: 60bb str r3, [r7, #8] return tmpreg; 8008568: 68bb ldr r3, [r7, #8] } 800856a: 4618 mov r0, r3 800856c: 371c adds r7, #28 800856e: 46bd mov sp, r7 8008570: f85d 7b04 ldr.w r7, [sp], #4 8008574: 4770 bx lr 08008576 : * This parameter can be one of these values: * 1 : Host * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { 8008576: b480 push {r7} 8008578: b083 sub sp, #12 800857a: af00 add r7, sp, #0 800857c: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 800857e: 687b ldr r3, [r7, #4] 8008580: 695b ldr r3, [r3, #20] 8008582: f003 0301 and.w r3, r3, #1 } 8008586: 4618 mov r0, r3 8008588: 370c adds r7, #12 800858a: 46bd mov sp, r7 800858c: f85d 7b04 ldr.w r7, [sp], #4 8008590: 4770 bx lr 08008592 : * @brief Activate EP0 for Setup transactions * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { 8008592: b480 push {r7} 8008594: b085 sub sp, #20 8008596: af00 add r7, sp, #0 8008598: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800859a: 687b ldr r3, [r7, #4] 800859c: 60fb str r3, [r7, #12] /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 800859e: 68fb ldr r3, [r7, #12] 80085a0: f503 6310 add.w r3, r3, #2304 @ 0x900 80085a4: 681b ldr r3, [r3, #0] 80085a6: 68fa ldr r2, [r7, #12] 80085a8: f502 6210 add.w r2, r2, #2304 @ 0x900 80085ac: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 80085b0: f023 0307 bic.w r3, r3, #7 80085b4: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 80085b6: 68fb ldr r3, [r7, #12] 80085b8: f503 6300 add.w r3, r3, #2048 @ 0x800 80085bc: 685b ldr r3, [r3, #4] 80085be: 68fa ldr r2, [r7, #12] 80085c0: f502 6200 add.w r2, r2, #2048 @ 0x800 80085c4: f443 7380 orr.w r3, r3, #256 @ 0x100 80085c8: 6053 str r3, [r2, #4] return HAL_OK; 80085ca: 2300 movs r3, #0 } 80085cc: 4618 mov r0, r3 80085ce: 3714 adds r7, #20 80085d0: 46bd mov sp, r7 80085d2: f85d 7b04 ldr.w r7, [sp], #4 80085d6: 4770 bx lr 080085d8 : * 1 : DMA feature used * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { 80085d8: b480 push {r7} 80085da: b087 sub sp, #28 80085dc: af00 add r7, sp, #0 80085de: 60f8 str r0, [r7, #12] 80085e0: 460b mov r3, r1 80085e2: 607a str r2, [r7, #4] 80085e4: 72fb strb r3, [r7, #11] uint32_t USBx_BASE = (uint32_t)USBx; 80085e6: 68fb ldr r3, [r7, #12] 80085e8: 617b str r3, [r7, #20] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 80085ea: 68fb ldr r3, [r7, #12] 80085ec: 333c adds r3, #60 @ 0x3c 80085ee: 3304 adds r3, #4 80085f0: 681b ldr r3, [r3, #0] 80085f2: 613b str r3, [r7, #16] if (gSNPSiD > USB_OTG_CORE_ID_300A) 80085f4: 693b ldr r3, [r7, #16] 80085f6: 4a26 ldr r2, [pc, #152] @ (8008690 ) 80085f8: 4293 cmp r3, r2 80085fa: d90a bls.n 8008612 { if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80085fc: 697b ldr r3, [r7, #20] 80085fe: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008602: 681b ldr r3, [r3, #0] 8008604: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008608: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800860c: d101 bne.n 8008612 { return HAL_OK; 800860e: 2300 movs r3, #0 8008610: e037 b.n 8008682 } } USBx_OUTEP(0U)->DOEPTSIZ = 0U; 8008612: 697b ldr r3, [r7, #20] 8008614: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008618: 461a mov r2, r3 800861a: 2300 movs r3, #0 800861c: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 800861e: 697b ldr r3, [r7, #20] 8008620: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008624: 691b ldr r3, [r3, #16] 8008626: 697a ldr r2, [r7, #20] 8008628: f502 6230 add.w r2, r2, #2816 @ 0xb00 800862c: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8008630: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); 8008632: 697b ldr r3, [r7, #20] 8008634: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008638: 691b ldr r3, [r3, #16] 800863a: 697a ldr r2, [r7, #20] 800863c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008640: f043 0318 orr.w r3, r3, #24 8008644: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 8008646: 697b ldr r3, [r7, #20] 8008648: f503 6330 add.w r3, r3, #2816 @ 0xb00 800864c: 691b ldr r3, [r3, #16] 800864e: 697a ldr r2, [r7, #20] 8008650: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008654: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000 8008658: 6113 str r3, [r2, #16] if (dma == 1U) 800865a: 7afb ldrb r3, [r7, #11] 800865c: 2b01 cmp r3, #1 800865e: d10f bne.n 8008680 { USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; 8008660: 697b ldr r3, [r7, #20] 8008662: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008666: 461a mov r2, r3 8008668: 687b ldr r3, [r7, #4] 800866a: 6153 str r3, [r2, #20] /* EP enable */ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; 800866c: 697b ldr r3, [r7, #20] 800866e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008672: 681b ldr r3, [r3, #0] 8008674: 697a ldr r2, [r7, #20] 8008676: f502 6230 add.w r2, r2, #2816 @ 0xb00 800867a: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000 800867e: 6013 str r3, [r2, #0] } return HAL_OK; 8008680: 2300 movs r3, #0 } 8008682: 4618 mov r0, r3 8008684: 371c adds r7, #28 8008686: 46bd mov sp, r7 8008688: f85d 7b04 ldr.w r7, [sp], #4 800868c: 4770 bx lr 800868e: bf00 nop 8008690: 4f54300a .word 0x4f54300a 08008694 : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 8008694: b480 push {r7} 8008696: b085 sub sp, #20 8008698: af00 add r7, sp, #0 800869a: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 800869c: 2300 movs r3, #0 800869e: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 80086a0: 68fb ldr r3, [r7, #12] 80086a2: 3301 adds r3, #1 80086a4: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80086a6: 68fb ldr r3, [r7, #12] 80086a8: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80086ac: d901 bls.n 80086b2 { return HAL_TIMEOUT; 80086ae: 2303 movs r3, #3 80086b0: e022 b.n 80086f8 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 80086b2: 687b ldr r3, [r7, #4] 80086b4: 691b ldr r3, [r3, #16] 80086b6: 2b00 cmp r3, #0 80086b8: daf2 bge.n 80086a0 count = 10U; 80086ba: 230a movs r3, #10 80086bc: 60fb str r3, [r7, #12] /* few cycles before setting core reset */ while (count > 0U) 80086be: e002 b.n 80086c6 { count--; 80086c0: 68fb ldr r3, [r7, #12] 80086c2: 3b01 subs r3, #1 80086c4: 60fb str r3, [r7, #12] while (count > 0U) 80086c6: 68fb ldr r3, [r7, #12] 80086c8: 2b00 cmp r3, #0 80086ca: d1f9 bne.n 80086c0 } /* Core Soft Reset */ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 80086cc: 687b ldr r3, [r7, #4] 80086ce: 691b ldr r3, [r3, #16] 80086d0: f043 0201 orr.w r2, r3, #1 80086d4: 687b ldr r3, [r7, #4] 80086d6: 611a str r2, [r3, #16] do { count++; 80086d8: 68fb ldr r3, [r7, #12] 80086da: 3301 adds r3, #1 80086dc: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80086de: 68fb ldr r3, [r7, #12] 80086e0: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80086e4: d901 bls.n 80086ea { return HAL_TIMEOUT; 80086e6: 2303 movs r3, #3 80086e8: e006 b.n 80086f8 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 80086ea: 687b ldr r3, [r7, #4] 80086ec: 691b ldr r3, [r3, #16] 80086ee: f003 0301 and.w r3, r3, #1 80086f2: 2b01 cmp r3, #1 80086f4: d0f0 beq.n 80086d8 return HAL_OK; 80086f6: 2300 movs r3, #0 } 80086f8: 4618 mov r0, r3 80086fa: 3714 adds r7, #20 80086fc: 46bd mov sp, r7 80086fe: f85d 7b04 ldr.w r7, [sp], #4 8008702: 4770 bx lr 08008704 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008704: b580 push {r7, lr} 8008706: b084 sub sp, #16 8008708: af00 add r7, sp, #0 800870a: 6078 str r0, [r7, #4] 800870c: 460b mov r3, r1 800870e: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_HID_HandleTypeDef *hhid; hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); 8008710: 2010 movs r0, #16 8008712: f002 f9e3 bl 800aadc 8008716: 60f8 str r0, [r7, #12] if (hhid == NULL) 8008718: 68fb ldr r3, [r7, #12] 800871a: 2b00 cmp r3, #0 800871c: d109 bne.n 8008732 { pdev->pClassDataCmsit[pdev->classId] = NULL; 800871e: 687b ldr r3, [r7, #4] 8008720: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008724: 687b ldr r3, [r7, #4] 8008726: 32b0 adds r2, #176 @ 0xb0 8008728: 2100 movs r1, #0 800872a: f843 1022 str.w r1, [r3, r2, lsl #2] return (uint8_t)USBD_EMEM; 800872e: 2302 movs r3, #2 8008730: e048 b.n 80087c4 } pdev->pClassDataCmsit[pdev->classId] = (void *)hhid; 8008732: 687b ldr r3, [r7, #4] 8008734: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008738: 687b ldr r3, [r7, #4] 800873a: 32b0 adds r2, #176 @ 0xb0 800873c: 68f9 ldr r1, [r7, #12] 800873e: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; 8008742: 687b ldr r3, [r7, #4] 8008744: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008748: 687b ldr r3, [r7, #4] 800874a: 32b0 adds r2, #176 @ 0xb0 800874c: f853 2022 ldr.w r2, [r3, r2, lsl #2] 8008750: 687b ldr r3, [r7, #4] 8008752: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_speed == USBD_SPEED_HIGH) 8008756: 687b ldr r3, [r7, #4] 8008758: 7c1b ldrb r3, [r3, #16] 800875a: 2b00 cmp r3, #0 800875c: d10d bne.n 800877a { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL; 800875e: 4b1b ldr r3, [pc, #108] @ (80087cc ) 8008760: 781b ldrb r3, [r3, #0] 8008762: f003 020f and.w r2, r3, #15 8008766: 6879 ldr r1, [r7, #4] 8008768: 4613 mov r3, r2 800876a: 009b lsls r3, r3, #2 800876c: 4413 add r3, r2 800876e: 009b lsls r3, r3, #2 8008770: 440b add r3, r1 8008772: 331c adds r3, #28 8008774: 2207 movs r2, #7 8008776: 601a str r2, [r3, #0] 8008778: e00c b.n 8008794 } else /* LOW and FULL-speed endpoints */ { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL; 800877a: 4b14 ldr r3, [pc, #80] @ (80087cc ) 800877c: 781b ldrb r3, [r3, #0] 800877e: f003 020f and.w r2, r3, #15 8008782: 6879 ldr r1, [r7, #4] 8008784: 4613 mov r3, r2 8008786: 009b lsls r3, r3, #2 8008788: 4413 add r3, r2 800878a: 009b lsls r3, r3, #2 800878c: 440b add r3, r1 800878e: 331c adds r3, #28 8008790: 220a movs r2, #10 8008792: 601a str r2, [r3, #0] } /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); 8008794: 4b0d ldr r3, [pc, #52] @ (80087cc ) 8008796: 7819 ldrb r1, [r3, #0] 8008798: 230e movs r3, #14 800879a: 2203 movs r2, #3 800879c: 6878 ldr r0, [r7, #4] 800879e: f002 f83e bl 800a81e pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U; 80087a2: 4b0a ldr r3, [pc, #40] @ (80087cc ) 80087a4: 781b ldrb r3, [r3, #0] 80087a6: f003 020f and.w r2, r3, #15 80087aa: 6879 ldr r1, [r7, #4] 80087ac: 4613 mov r3, r2 80087ae: 009b lsls r3, r3, #2 80087b0: 4413 add r3, r2 80087b2: 009b lsls r3, r3, #2 80087b4: 440b add r3, r1 80087b6: 3323 adds r3, #35 @ 0x23 80087b8: 2201 movs r2, #1 80087ba: 701a strb r2, [r3, #0] hhid->state = USBD_HID_IDLE; 80087bc: 68fb ldr r3, [r7, #12] 80087be: 2200 movs r2, #0 80087c0: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 80087c2: 2300 movs r3, #0 } 80087c4: 4618 mov r0, r3 80087c6: 3710 adds r7, #16 80087c8: 46bd mov sp, r7 80087ca: bd80 pop {r7, pc} 80087cc: 2000013d .word 0x2000013d 080087d0 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80087d0: b580 push {r7, lr} 80087d2: b082 sub sp, #8 80087d4: af00 add r7, sp, #0 80087d6: 6078 str r0, [r7, #4] 80087d8: 460b mov r3, r1 80087da: 70fb strb r3, [r7, #3] /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ /* Close HID EPs */ (void)USBD_LL_CloseEP(pdev, HIDInEpAdd); 80087dc: 4b1f ldr r3, [pc, #124] @ (800885c ) 80087de: 781b ldrb r3, [r3, #0] 80087e0: 4619 mov r1, r3 80087e2: 6878 ldr r0, [r7, #4] 80087e4: f002 f841 bl 800a86a pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U; 80087e8: 4b1c ldr r3, [pc, #112] @ (800885c ) 80087ea: 781b ldrb r3, [r3, #0] 80087ec: f003 020f and.w r2, r3, #15 80087f0: 6879 ldr r1, [r7, #4] 80087f2: 4613 mov r3, r2 80087f4: 009b lsls r3, r3, #2 80087f6: 4413 add r3, r2 80087f8: 009b lsls r3, r3, #2 80087fa: 440b add r3, r1 80087fc: 3323 adds r3, #35 @ 0x23 80087fe: 2200 movs r2, #0 8008800: 701a strb r2, [r3, #0] pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U; 8008802: 4b16 ldr r3, [pc, #88] @ (800885c ) 8008804: 781b ldrb r3, [r3, #0] 8008806: f003 020f and.w r2, r3, #15 800880a: 6879 ldr r1, [r7, #4] 800880c: 4613 mov r3, r2 800880e: 009b lsls r3, r3, #2 8008810: 4413 add r3, r2 8008812: 009b lsls r3, r3, #2 8008814: 440b add r3, r1 8008816: 331c adds r3, #28 8008818: 2200 movs r2, #0 800881a: 601a str r2, [r3, #0] /* Free allocated memory */ if (pdev->pClassDataCmsit[pdev->classId] != NULL) 800881c: 687b ldr r3, [r7, #4] 800881e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008822: 687b ldr r3, [r7, #4] 8008824: 32b0 adds r2, #176 @ 0xb0 8008826: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800882a: 2b00 cmp r3, #0 800882c: d011 beq.n 8008852 { (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); 800882e: 687b ldr r3, [r7, #4] 8008830: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008834: 687b ldr r3, [r7, #4] 8008836: 32b0 adds r2, #176 @ 0xb0 8008838: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800883c: 4618 mov r0, r3 800883e: f002 f95b bl 800aaf8 pdev->pClassDataCmsit[pdev->classId] = NULL; 8008842: 687b ldr r3, [r7, #4] 8008844: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008848: 687b ldr r3, [r7, #4] 800884a: 32b0 adds r2, #176 @ 0xb0 800884c: 2100 movs r1, #0 800884e: f843 1022 str.w r1, [r3, r2, lsl #2] } return (uint8_t)USBD_OK; 8008852: 2300 movs r3, #0 } 8008854: 4618 mov r0, r3 8008856: 3708 adds r7, #8 8008858: 46bd mov sp, r7 800885a: bd80 pop {r7, pc} 800885c: 2000013d .word 0x2000013d 08008860 : * @param pdev: instance * @param req: usb requests * @retval status */ static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008860: b580 push {r7, lr} 8008862: b086 sub sp, #24 8008864: af00 add r7, sp, #0 8008866: 6078 str r0, [r7, #4] 8008868: 6039 str r1, [r7, #0] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 800886a: 687b ldr r3, [r7, #4] 800886c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008870: 687b ldr r3, [r7, #4] 8008872: 32b0 adds r2, #176 @ 0xb0 8008874: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008878: 60fb str r3, [r7, #12] USBD_StatusTypeDef ret = USBD_OK; 800887a: 2300 movs r3, #0 800887c: 75fb strb r3, [r7, #23] uint16_t len; uint8_t *pbuf; uint16_t status_info = 0U; 800887e: 2300 movs r3, #0 8008880: 817b strh r3, [r7, #10] if (hhid == NULL) 8008882: 68fb ldr r3, [r7, #12] 8008884: 2b00 cmp r3, #0 8008886: d101 bne.n 800888c { return (uint8_t)USBD_FAIL; 8008888: 2303 movs r3, #3 800888a: e0e8 b.n 8008a5e } switch (req->bmRequest & USB_REQ_TYPE_MASK) 800888c: 683b ldr r3, [r7, #0] 800888e: 781b ldrb r3, [r3, #0] 8008890: f003 0360 and.w r3, r3, #96 @ 0x60 8008894: 2b00 cmp r3, #0 8008896: d046 beq.n 8008926 8008898: 2b20 cmp r3, #32 800889a: f040 80d8 bne.w 8008a4e { case USB_REQ_TYPE_CLASS : switch (req->bRequest) 800889e: 683b ldr r3, [r7, #0] 80088a0: 785b ldrb r3, [r3, #1] 80088a2: 3b02 subs r3, #2 80088a4: 2b09 cmp r3, #9 80088a6: d836 bhi.n 8008916 80088a8: a201 add r2, pc, #4 @ (adr r2, 80088b0 ) 80088aa: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80088ae: bf00 nop 80088b0: 08008907 .word 0x08008907 80088b4: 080088e7 .word 0x080088e7 80088b8: 08008917 .word 0x08008917 80088bc: 08008917 .word 0x08008917 80088c0: 08008917 .word 0x08008917 80088c4: 08008917 .word 0x08008917 80088c8: 08008917 .word 0x08008917 80088cc: 08008917 .word 0x08008917 80088d0: 080088f5 .word 0x080088f5 80088d4: 080088d9 .word 0x080088d9 { case USBD_HID_REQ_SET_PROTOCOL: hhid->Protocol = (uint8_t)(req->wValue); 80088d8: 683b ldr r3, [r7, #0] 80088da: 885b ldrh r3, [r3, #2] 80088dc: b2db uxtb r3, r3 80088de: 461a mov r2, r3 80088e0: 68fb ldr r3, [r7, #12] 80088e2: 601a str r2, [r3, #0] break; 80088e4: e01e b.n 8008924 case USBD_HID_REQ_GET_PROTOCOL: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); 80088e6: 68fb ldr r3, [r7, #12] 80088e8: 2201 movs r2, #1 80088ea: 4619 mov r1, r3 80088ec: 6878 ldr r0, [r7, #4] 80088ee: f001 fc25 bl 800a13c break; 80088f2: e017 b.n 8008924 case USBD_HID_REQ_SET_IDLE: hhid->IdleState = (uint8_t)(req->wValue >> 8); 80088f4: 683b ldr r3, [r7, #0] 80088f6: 885b ldrh r3, [r3, #2] 80088f8: 0a1b lsrs r3, r3, #8 80088fa: b29b uxth r3, r3 80088fc: b2db uxtb r3, r3 80088fe: 461a mov r2, r3 8008900: 68fb ldr r3, [r7, #12] 8008902: 605a str r2, [r3, #4] break; 8008904: e00e b.n 8008924 case USBD_HID_REQ_GET_IDLE: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); 8008906: 68fb ldr r3, [r7, #12] 8008908: 3304 adds r3, #4 800890a: 2201 movs r2, #1 800890c: 4619 mov r1, r3 800890e: 6878 ldr r0, [r7, #4] 8008910: f001 fc14 bl 800a13c break; 8008914: e006 b.n 8008924 default: USBD_CtlError(pdev, req); 8008916: 6839 ldr r1, [r7, #0] 8008918: 6878 ldr r0, [r7, #4] 800891a: f001 fb92 bl 800a042 ret = USBD_FAIL; 800891e: 2303 movs r3, #3 8008920: 75fb strb r3, [r7, #23] break; 8008922: bf00 nop } break; 8008924: e09a b.n 8008a5c case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8008926: 683b ldr r3, [r7, #0] 8008928: 785b ldrb r3, [r3, #1] 800892a: 2b0b cmp r3, #11 800892c: f200 8086 bhi.w 8008a3c 8008930: a201 add r2, pc, #4 @ (adr r2, 8008938 ) 8008932: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008936: bf00 nop 8008938: 08008969 .word 0x08008969 800893c: 08008a4b .word 0x08008a4b 8008940: 08008a3d .word 0x08008a3d 8008944: 08008a3d .word 0x08008a3d 8008948: 08008a3d .word 0x08008a3d 800894c: 08008a3d .word 0x08008a3d 8008950: 08008993 .word 0x08008993 8008954: 08008a3d .word 0x08008a3d 8008958: 08008a3d .word 0x08008a3d 800895c: 08008a3d .word 0x08008a3d 8008960: 080089eb .word 0x080089eb 8008964: 08008a15 .word 0x08008a15 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008968: 687b ldr r3, [r7, #4] 800896a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800896e: b2db uxtb r3, r3 8008970: 2b03 cmp r3, #3 8008972: d107 bne.n 8008984 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 8008974: f107 030a add.w r3, r7, #10 8008978: 2202 movs r2, #2 800897a: 4619 mov r1, r3 800897c: 6878 ldr r0, [r7, #4] 800897e: f001 fbdd bl 800a13c else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8008982: e063 b.n 8008a4c USBD_CtlError(pdev, req); 8008984: 6839 ldr r1, [r7, #0] 8008986: 6878 ldr r0, [r7, #4] 8008988: f001 fb5b bl 800a042 ret = USBD_FAIL; 800898c: 2303 movs r3, #3 800898e: 75fb strb r3, [r7, #23] break; 8008990: e05c b.n 8008a4c case USB_REQ_GET_DESCRIPTOR: if ((req->wValue >> 8) == HID_REPORT_DESC) 8008992: 683b ldr r3, [r7, #0] 8008994: 885b ldrh r3, [r3, #2] 8008996: 0a1b lsrs r3, r3, #8 8008998: b29b uxth r3, r3 800899a: 2b22 cmp r3, #34 @ 0x22 800899c: d108 bne.n 80089b0 { len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); 800899e: 683b ldr r3, [r7, #0] 80089a0: 88db ldrh r3, [r3, #6] 80089a2: 2b2d cmp r3, #45 @ 0x2d 80089a4: bf28 it cs 80089a6: 232d movcs r3, #45 @ 0x2d 80089a8: 82bb strh r3, [r7, #20] pbuf = HID_MOUSE_ReportDesc; 80089aa: 4b2f ldr r3, [pc, #188] @ (8008a68 ) 80089ac: 613b str r3, [r7, #16] 80089ae: e015 b.n 80089dc } else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) 80089b0: 683b ldr r3, [r7, #0] 80089b2: 885b ldrh r3, [r3, #2] 80089b4: 0a1b lsrs r3, r3, #8 80089b6: b29b uxth r3, r3 80089b8: 2b21 cmp r3, #33 @ 0x21 80089ba: d108 bne.n 80089ce { pbuf = USBD_HID_Desc; 80089bc: 4b2b ldr r3, [pc, #172] @ (8008a6c ) 80089be: 613b str r3, [r7, #16] len = MIN(USB_HID_DESC_SIZ, req->wLength); 80089c0: 683b ldr r3, [r7, #0] 80089c2: 88db ldrh r3, [r3, #6] 80089c4: 2b09 cmp r3, #9 80089c6: bf28 it cs 80089c8: 2309 movcs r3, #9 80089ca: 82bb strh r3, [r7, #20] 80089cc: e006 b.n 80089dc } else { USBD_CtlError(pdev, req); 80089ce: 6839 ldr r1, [r7, #0] 80089d0: 6878 ldr r0, [r7, #4] 80089d2: f001 fb36 bl 800a042 ret = USBD_FAIL; 80089d6: 2303 movs r3, #3 80089d8: 75fb strb r3, [r7, #23] break; 80089da: e037 b.n 8008a4c } (void)USBD_CtlSendData(pdev, pbuf, len); 80089dc: 8abb ldrh r3, [r7, #20] 80089de: 461a mov r2, r3 80089e0: 6939 ldr r1, [r7, #16] 80089e2: 6878 ldr r0, [r7, #4] 80089e4: f001 fbaa bl 800a13c break; 80089e8: e030 b.n 8008a4c case USB_REQ_GET_INTERFACE : if (pdev->dev_state == USBD_STATE_CONFIGURED) 80089ea: 687b ldr r3, [r7, #4] 80089ec: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80089f0: b2db uxtb r3, r3 80089f2: 2b03 cmp r3, #3 80089f4: d107 bne.n 8008a06 { (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); 80089f6: 68fb ldr r3, [r7, #12] 80089f8: 3308 adds r3, #8 80089fa: 2201 movs r2, #1 80089fc: 4619 mov r1, r3 80089fe: 6878 ldr r0, [r7, #4] 8008a00: f001 fb9c bl 800a13c else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8008a04: e022 b.n 8008a4c USBD_CtlError(pdev, req); 8008a06: 6839 ldr r1, [r7, #0] 8008a08: 6878 ldr r0, [r7, #4] 8008a0a: f001 fb1a bl 800a042 ret = USBD_FAIL; 8008a0e: 2303 movs r3, #3 8008a10: 75fb strb r3, [r7, #23] break; 8008a12: e01b b.n 8008a4c case USB_REQ_SET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008a14: 687b ldr r3, [r7, #4] 8008a16: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008a1a: b2db uxtb r3, r3 8008a1c: 2b03 cmp r3, #3 8008a1e: d106 bne.n 8008a2e { hhid->AltSetting = (uint8_t)(req->wValue); 8008a20: 683b ldr r3, [r7, #0] 8008a22: 885b ldrh r3, [r3, #2] 8008a24: b2db uxtb r3, r3 8008a26: 461a mov r2, r3 8008a28: 68fb ldr r3, [r7, #12] 8008a2a: 609a str r2, [r3, #8] else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8008a2c: e00e b.n 8008a4c USBD_CtlError(pdev, req); 8008a2e: 6839 ldr r1, [r7, #0] 8008a30: 6878 ldr r0, [r7, #4] 8008a32: f001 fb06 bl 800a042 ret = USBD_FAIL; 8008a36: 2303 movs r3, #3 8008a38: 75fb strb r3, [r7, #23] break; 8008a3a: e007 b.n 8008a4c case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 8008a3c: 6839 ldr r1, [r7, #0] 8008a3e: 6878 ldr r0, [r7, #4] 8008a40: f001 faff bl 800a042 ret = USBD_FAIL; 8008a44: 2303 movs r3, #3 8008a46: 75fb strb r3, [r7, #23] break; 8008a48: e000 b.n 8008a4c break; 8008a4a: bf00 nop } break; 8008a4c: e006 b.n 8008a5c default: USBD_CtlError(pdev, req); 8008a4e: 6839 ldr r1, [r7, #0] 8008a50: 6878 ldr r0, [r7, #4] 8008a52: f001 faf6 bl 800a042 ret = USBD_FAIL; 8008a56: 2303 movs r3, #3 8008a58: 75fb strb r3, [r7, #23] break; 8008a5a: bf00 nop } return (uint8_t)ret; 8008a5c: 7dfb ldrb r3, [r7, #23] } 8008a5e: 4618 mov r0, r3 8008a60: 3718 adds r7, #24 8008a62: 46bd mov sp, r7 8008a64: bd80 pop {r7, pc} 8008a66: bf00 nop 8008a68: 20000110 .word 0x20000110 8008a6c: 200000f8 .word 0x200000f8 08008a70 : uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId) { USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) { 8008a70: b580 push {r7, lr} 8008a72: b086 sub sp, #24 8008a74: af00 add r7, sp, #0 8008a76: 60f8 str r0, [r7, #12] 8008a78: 60b9 str r1, [r7, #8] 8008a7a: 4613 mov r3, r2 8008a7c: 80fb strh r3, [r7, #6] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8008a7e: 68fb ldr r3, [r7, #12] 8008a80: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008a84: 68fb ldr r3, [r7, #12] 8008a86: 32b0 adds r2, #176 @ 0xb0 8008a88: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008a8c: 617b str r3, [r7, #20] #endif /* USE_USBD_COMPOSITE */ if (hhid == NULL) 8008a8e: 697b ldr r3, [r7, #20] 8008a90: 2b00 cmp r3, #0 8008a92: d101 bne.n 8008a98 { return (uint8_t)USBD_FAIL; 8008a94: 2303 movs r3, #3 8008a96: e014 b.n 8008ac2 #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008a98: 68fb ldr r3, [r7, #12] 8008a9a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008a9e: b2db uxtb r3, r3 8008aa0: 2b03 cmp r3, #3 8008aa2: d10d bne.n 8008ac0 { if (hhid->state == USBD_HID_IDLE) 8008aa4: 697b ldr r3, [r7, #20] 8008aa6: 7b1b ldrb r3, [r3, #12] 8008aa8: 2b00 cmp r3, #0 8008aaa: d109 bne.n 8008ac0 { hhid->state = USBD_HID_BUSY; 8008aac: 697b ldr r3, [r7, #20] 8008aae: 2201 movs r2, #1 8008ab0: 731a strb r2, [r3, #12] (void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len); 8008ab2: 4b06 ldr r3, [pc, #24] @ (8008acc ) 8008ab4: 7819 ldrb r1, [r3, #0] 8008ab6: 88fb ldrh r3, [r7, #6] 8008ab8: 68ba ldr r2, [r7, #8] 8008aba: 68f8 ldr r0, [r7, #12] 8008abc: f001 ff7d bl 800a9ba } } return (uint8_t)USBD_OK; 8008ac0: 2300 movs r3, #0 } 8008ac2: 4618 mov r0, r3 8008ac4: 3718 adds r7, #24 8008ac6: 46bd mov sp, r7 8008ac8: bd80 pop {r7, pc} 8008aca: bf00 nop 8008acc: 2000013d .word 0x2000013d 08008ad0 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) { 8008ad0: b580 push {r7, lr} 8008ad2: b084 sub sp, #16 8008ad4: af00 add r7, sp, #0 8008ad6: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8008ad8: 2181 movs r1, #129 @ 0x81 8008ada: 4809 ldr r0, [pc, #36] @ (8008b00 ) 8008adc: f000 fc4e bl 800937c 8008ae0: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 8008ae2: 68fb ldr r3, [r7, #12] 8008ae4: 2b00 cmp r3, #0 8008ae6: d002 beq.n 8008aee { pEpDesc->bInterval = HID_FS_BINTERVAL; 8008ae8: 68fb ldr r3, [r7, #12] 8008aea: 220a movs r2, #10 8008aec: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 8008aee: 687b ldr r3, [r7, #4] 8008af0: 2222 movs r2, #34 @ 0x22 8008af2: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8008af4: 4b02 ldr r3, [pc, #8] @ (8008b00 ) } 8008af6: 4618 mov r0, r3 8008af8: 3710 adds r7, #16 8008afa: 46bd mov sp, r7 8008afc: bd80 pop {r7, pc} 8008afe: bf00 nop 8008b00: 200000d4 .word 0x200000d4 08008b04 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) { 8008b04: b580 push {r7, lr} 8008b06: b084 sub sp, #16 8008b08: af00 add r7, sp, #0 8008b0a: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8008b0c: 2181 movs r1, #129 @ 0x81 8008b0e: 4809 ldr r0, [pc, #36] @ (8008b34 ) 8008b10: f000 fc34 bl 800937c 8008b14: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 8008b16: 68fb ldr r3, [r7, #12] 8008b18: 2b00 cmp r3, #0 8008b1a: d002 beq.n 8008b22 { pEpDesc->bInterval = HID_HS_BINTERVAL; 8008b1c: 68fb ldr r3, [r7, #12] 8008b1e: 2207 movs r2, #7 8008b20: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 8008b22: 687b ldr r3, [r7, #4] 8008b24: 2222 movs r2, #34 @ 0x22 8008b26: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8008b28: 4b02 ldr r3, [pc, #8] @ (8008b34 ) } 8008b2a: 4618 mov r0, r3 8008b2c: 3710 adds r7, #16 8008b2e: 46bd mov sp, r7 8008b30: bd80 pop {r7, pc} 8008b32: bf00 nop 8008b34: 200000d4 .word 0x200000d4 08008b38 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) { 8008b38: b580 push {r7, lr} 8008b3a: b084 sub sp, #16 8008b3c: af00 add r7, sp, #0 8008b3e: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8008b40: 2181 movs r1, #129 @ 0x81 8008b42: 4809 ldr r0, [pc, #36] @ (8008b68 ) 8008b44: f000 fc1a bl 800937c 8008b48: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 8008b4a: 68fb ldr r3, [r7, #12] 8008b4c: 2b00 cmp r3, #0 8008b4e: d002 beq.n 8008b56 { pEpDesc->bInterval = HID_FS_BINTERVAL; 8008b50: 68fb ldr r3, [r7, #12] 8008b52: 220a movs r2, #10 8008b54: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 8008b56: 687b ldr r3, [r7, #4] 8008b58: 2222 movs r2, #34 @ 0x22 8008b5a: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8008b5c: 4b02 ldr r3, [pc, #8] @ (8008b68 ) } 8008b5e: 4618 mov r0, r3 8008b60: 3710 adds r7, #16 8008b62: 46bd mov sp, r7 8008b64: bd80 pop {r7, pc} 8008b66: bf00 nop 8008b68: 200000d4 .word 0x200000d4 08008b6c : * @param pdev: device instance * @param epnum: endpoint index * @retval status */ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8008b6c: b480 push {r7} 8008b6e: b083 sub sp, #12 8008b70: af00 add r7, sp, #0 8008b72: 6078 str r0, [r7, #4] 8008b74: 460b mov r3, r1 8008b76: 70fb strb r3, [r7, #3] UNUSED(epnum); /* Ensure that the FIFO is empty before a new transfer, this condition could be caused by a new transfer before the end of the previous transfer */ ((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE; 8008b78: 687b ldr r3, [r7, #4] 8008b7a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008b7e: 687b ldr r3, [r7, #4] 8008b80: 32b0 adds r2, #176 @ 0xb0 8008b82: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008b86: 2200 movs r2, #0 8008b88: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 8008b8a: 2300 movs r3, #0 } 8008b8c: 4618 mov r0, r3 8008b8e: 370c adds r7, #12 8008b90: 46bd mov sp, r7 8008b92: f85d 7b04 ldr.w r7, [sp], #4 8008b96: 4770 bx lr 08008b98 : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) { 8008b98: b480 push {r7} 8008b9a: b083 sub sp, #12 8008b9c: af00 add r7, sp, #0 8008b9e: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); 8008ba0: 687b ldr r3, [r7, #4] 8008ba2: 220a movs r2, #10 8008ba4: 801a strh r2, [r3, #0] return USBD_HID_DeviceQualifierDesc; 8008ba6: 4b03 ldr r3, [pc, #12] @ (8008bb4 ) } 8008ba8: 4618 mov r0, r3 8008baa: 370c adds r7, #12 8008bac: 46bd mov sp, r7 8008bae: f85d 7b04 ldr.w r7, [sp], #4 8008bb2: 4770 bx lr 8008bb4: 20000104 .word 0x20000104 08008bb8 : * @param id: Low level core index * @retval status: USBD Status */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 8008bb8: b580 push {r7, lr} 8008bba: b086 sub sp, #24 8008bbc: af00 add r7, sp, #0 8008bbe: 60f8 str r0, [r7, #12] 8008bc0: 60b9 str r1, [r7, #8] 8008bc2: 4613 mov r3, r2 8008bc4: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 8008bc6: 68fb ldr r3, [r7, #12] 8008bc8: 2b00 cmp r3, #0 8008bca: d101 bne.n 8008bd0 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8008bcc: 2303 movs r3, #3 8008bce: e01f b.n 8008c10 pdev->NumClasses = 0; pdev->classId = 0; } #else /* Unlink previous class*/ pdev->pClass[0] = NULL; 8008bd0: 68fb ldr r3, [r7, #12] 8008bd2: 2200 movs r2, #0 8008bd4: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 pdev->pUserData[0] = NULL; 8008bd8: 68fb ldr r3, [r7, #12] 8008bda: 2200 movs r2, #0 8008bdc: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4 #endif /* USE_USBD_COMPOSITE */ pdev->pConfDesc = NULL; 8008be0: 68fb ldr r3, [r7, #12] 8008be2: 2200 movs r2, #0 8008be4: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 /* Assign USBD Descriptors */ if (pdesc != NULL) 8008be8: 68bb ldr r3, [r7, #8] 8008bea: 2b00 cmp r3, #0 8008bec: d003 beq.n 8008bf6 { pdev->pDesc = pdesc; 8008bee: 68fb ldr r3, [r7, #12] 8008bf0: 68ba ldr r2, [r7, #8] 8008bf2: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 8008bf6: 68fb ldr r3, [r7, #12] 8008bf8: 2201 movs r2, #1 8008bfa: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->id = id; 8008bfe: 68fb ldr r3, [r7, #12] 8008c00: 79fa ldrb r2, [r7, #7] 8008c02: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 8008c04: 68f8 ldr r0, [r7, #12] 8008c06: f001 fda3 bl 800a750 8008c0a: 4603 mov r3, r0 8008c0c: 75fb strb r3, [r7, #23] return ret; 8008c0e: 7dfb ldrb r3, [r7, #23] } 8008c10: 4618 mov r0, r3 8008c12: 3718 adds r7, #24 8008c14: 46bd mov sp, r7 8008c16: bd80 pop {r7, pc} 08008c18 : * @param pdev: Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 8008c18: b580 push {r7, lr} 8008c1a: b084 sub sp, #16 8008c1c: af00 add r7, sp, #0 8008c1e: 6078 str r0, [r7, #4] 8008c20: 6039 str r1, [r7, #0] uint16_t len = 0U; 8008c22: 2300 movs r3, #0 8008c24: 81fb strh r3, [r7, #14] if (pclass == NULL) 8008c26: 683b ldr r3, [r7, #0] 8008c28: 2b00 cmp r3, #0 8008c2a: d101 bne.n 8008c30 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8008c2c: 2303 movs r3, #3 8008c2e: e025 b.n 8008c7c } /* link the class to the USB Device handle */ pdev->pClass[0] = pclass; 8008c30: 687b ldr r3, [r7, #4] 8008c32: 683a ldr r2, [r7, #0] 8008c34: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) 8008c38: 687b ldr r3, [r7, #4] 8008c3a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008c3e: 687b ldr r3, [r7, #4] 8008c40: 32ae adds r2, #174 @ 0xae 8008c42: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008c46: 6adb ldr r3, [r3, #44] @ 0x2c 8008c48: 2b00 cmp r3, #0 8008c4a: d00f beq.n 8008c6c { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); 8008c4c: 687b ldr r3, [r7, #4] 8008c4e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008c52: 687b ldr r3, [r7, #4] 8008c54: 32ae adds r2, #174 @ 0xae 8008c56: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008c5a: 6adb ldr r3, [r3, #44] @ 0x2c 8008c5c: f107 020e add.w r2, r7, #14 8008c60: 4610 mov r0, r2 8008c62: 4798 blx r3 8008c64: 4602 mov r2, r0 8008c66: 687b ldr r3, [r7, #4] 8008c68: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 } #endif /* USE_USB_FS */ /* Increment the NumClasses */ pdev->NumClasses++; 8008c6c: 687b ldr r3, [r7, #4] 8008c6e: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8008c72: 1c5a adds r2, r3, #1 8008c74: 687b ldr r3, [r7, #4] 8008c76: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8 return USBD_OK; 8008c7a: 2300 movs r3, #0 } 8008c7c: 4618 mov r0, r3 8008c7e: 3710 adds r7, #16 8008c80: 46bd mov sp, r7 8008c82: bd80 pop {r7, pc} 08008c84 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 8008c84: b580 push {r7, lr} 8008c86: b082 sub sp, #8 8008c88: af00 add r7, sp, #0 8008c8a: 6078 str r0, [r7, #4] #ifdef USE_USBD_COMPOSITE pdev->classId = 0U; #endif /* USE_USBD_COMPOSITE */ /* Start the low level driver */ return USBD_LL_Start(pdev); 8008c8c: 6878 ldr r0, [r7, #4] 8008c8e: f001 fdab bl 800a7e8 8008c92: 4603 mov r3, r0 } 8008c94: 4618 mov r0, r3 8008c96: 3708 adds r7, #8 8008c98: 46bd mov sp, r7 8008c9a: bd80 pop {r7, pc} 08008c9c : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 8008c9c: b480 push {r7} 8008c9e: b083 sub sp, #12 8008ca0: af00 add r7, sp, #0 8008ca2: 6078 str r0, [r7, #4] return ret; #else /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8008ca4: 2300 movs r3, #0 #endif /* USBD_HS_TESTMODE_ENABLE */ } 8008ca6: 4618 mov r0, r3 8008ca8: 370c adds r7, #12 8008caa: 46bd mov sp, r7 8008cac: f85d 7b04 ldr.w r7, [sp], #4 8008cb0: 4770 bx lr 08008cb2 : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008cb2: b580 push {r7, lr} 8008cb4: b084 sub sp, #16 8008cb6: af00 add r7, sp, #0 8008cb8: 6078 str r0, [r7, #4] 8008cba: 460b mov r3, r1 8008cbc: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8008cbe: 2300 movs r3, #0 8008cc0: 73fb strb r3, [r7, #15] } } } } #else if (pdev->pClass[0] != NULL) 8008cc2: 687b ldr r3, [r7, #4] 8008cc4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008cc8: 2b00 cmp r3, #0 8008cca: d009 beq.n 8008ce0 { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); 8008ccc: 687b ldr r3, [r7, #4] 8008cce: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008cd2: 681b ldr r3, [r3, #0] 8008cd4: 78fa ldrb r2, [r7, #3] 8008cd6: 4611 mov r1, r2 8008cd8: 6878 ldr r0, [r7, #4] 8008cda: 4798 blx r3 8008cdc: 4603 mov r3, r0 8008cde: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8008ce0: 7bfb ldrb r3, [r7, #15] } 8008ce2: 4618 mov r0, r3 8008ce4: 3710 adds r7, #16 8008ce6: 46bd mov sp, r7 8008ce8: bd80 pop {r7, pc} 08008cea : * @param pdev: device instance * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008cea: b580 push {r7, lr} 8008cec: b084 sub sp, #16 8008cee: af00 add r7, sp, #0 8008cf0: 6078 str r0, [r7, #4] 8008cf2: 460b mov r3, r1 8008cf4: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8008cf6: 2300 movs r3, #0 8008cf8: 73fb strb r3, [r7, #15] } } } #else /* Clear configuration and De-initialize the Class process */ if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) 8008cfa: 687b ldr r3, [r7, #4] 8008cfc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8008d00: 685b ldr r3, [r3, #4] 8008d02: 78fa ldrb r2, [r7, #3] 8008d04: 4611 mov r1, r2 8008d06: 6878 ldr r0, [r7, #4] 8008d08: 4798 blx r3 8008d0a: 4603 mov r3, r0 8008d0c: 2b00 cmp r3, #0 8008d0e: d001 beq.n 8008d14 { ret = USBD_FAIL; 8008d10: 2303 movs r3, #3 8008d12: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8008d14: 7bfb ldrb r3, [r7, #15] } 8008d16: 4618 mov r0, r3 8008d18: 3710 adds r7, #16 8008d1a: 46bd mov sp, r7 8008d1c: bd80 pop {r7, pc} 08008d1e : * @param pdev: device instance * @param psetup: setup packet buffer pointer * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 8008d1e: b580 push {r7, lr} 8008d20: b084 sub sp, #16 8008d22: af00 add r7, sp, #0 8008d24: 6078 str r0, [r7, #4] 8008d26: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 8008d28: 687b ldr r3, [r7, #4] 8008d2a: f203 23aa addw r3, r3, #682 @ 0x2aa 8008d2e: 6839 ldr r1, [r7, #0] 8008d30: 4618 mov r0, r3 8008d32: f001 f94c bl 8009fce pdev->ep0_state = USBD_EP0_SETUP; 8008d36: 687b ldr r3, [r7, #4] 8008d38: 2201 movs r2, #1 8008d3a: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep0_data_len = pdev->request.wLength; 8008d3e: 687b ldr r3, [r7, #4] 8008d40: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0 8008d44: 461a mov r2, r3 8008d46: 687b ldr r3, [r7, #4] 8008d48: f8c3 2298 str.w r2, [r3, #664] @ 0x298 switch (pdev->request.bmRequest & 0x1FU) 8008d4c: 687b ldr r3, [r7, #4] 8008d4e: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008d52: f003 031f and.w r3, r3, #31 8008d56: 2b02 cmp r3, #2 8008d58: d01a beq.n 8008d90 8008d5a: 2b02 cmp r3, #2 8008d5c: d822 bhi.n 8008da4 8008d5e: 2b00 cmp r3, #0 8008d60: d002 beq.n 8008d68 8008d62: 2b01 cmp r3, #1 8008d64: d00a beq.n 8008d7c 8008d66: e01d b.n 8008da4 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 8008d68: 687b ldr r3, [r7, #4] 8008d6a: f203 23aa addw r3, r3, #682 @ 0x2aa 8008d6e: 4619 mov r1, r3 8008d70: 6878 ldr r0, [r7, #4] 8008d72: f000 fb77 bl 8009464 8008d76: 4603 mov r3, r0 8008d78: 73fb strb r3, [r7, #15] break; 8008d7a: e020 b.n 8008dbe case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 8008d7c: 687b ldr r3, [r7, #4] 8008d7e: f203 23aa addw r3, r3, #682 @ 0x2aa 8008d82: 4619 mov r1, r3 8008d84: 6878 ldr r0, [r7, #4] 8008d86: f000 fbdf bl 8009548 8008d8a: 4603 mov r3, r0 8008d8c: 73fb strb r3, [r7, #15] break; 8008d8e: e016 b.n 8008dbe case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 8008d90: 687b ldr r3, [r7, #4] 8008d92: f203 23aa addw r3, r3, #682 @ 0x2aa 8008d96: 4619 mov r1, r3 8008d98: 6878 ldr r0, [r7, #4] 8008d9a: f000 fc41 bl 8009620 8008d9e: 4603 mov r3, r0 8008da0: 73fb strb r3, [r7, #15] break; 8008da2: e00c b.n 8008dbe default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 8008da4: 687b ldr r3, [r7, #4] 8008da6: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008daa: f023 037f bic.w r3, r3, #127 @ 0x7f 8008dae: b2db uxtb r3, r3 8008db0: 4619 mov r1, r3 8008db2: 6878 ldr r0, [r7, #4] 8008db4: f001 fd78 bl 800a8a8 8008db8: 4603 mov r3, r0 8008dba: 73fb strb r3, [r7, #15] break; 8008dbc: bf00 nop } return ret; 8008dbe: 7bfb ldrb r3, [r7, #15] } 8008dc0: 4618 mov r0, r3 8008dc2: 3710 adds r7, #16 8008dc4: 46bd mov sp, r7 8008dc6: bd80 pop {r7, pc} 08008dc8 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8008dc8: b580 push {r7, lr} 8008dca: b086 sub sp, #24 8008dcc: af00 add r7, sp, #0 8008dce: 60f8 str r0, [r7, #12] 8008dd0: 460b mov r3, r1 8008dd2: 607a str r2, [r7, #4] 8008dd4: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret = USBD_OK; 8008dd6: 2300 movs r3, #0 8008dd8: 75fb strb r3, [r7, #23] uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8008dda: 7afb ldrb r3, [r7, #11] 8008ddc: 2b00 cmp r3, #0 8008dde: d177 bne.n 8008ed0 { pep = &pdev->ep_out[0]; 8008de0: 68fb ldr r3, [r7, #12] 8008de2: f503 73aa add.w r3, r3, #340 @ 0x154 8008de6: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 8008de8: 68fb ldr r3, [r7, #12] 8008dea: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8008dee: 2b03 cmp r3, #3 8008df0: f040 80a1 bne.w 8008f36 { if (pep->rem_length > pep->maxpacket) 8008df4: 693b ldr r3, [r7, #16] 8008df6: 685b ldr r3, [r3, #4] 8008df8: 693a ldr r2, [r7, #16] 8008dfa: 8992 ldrh r2, [r2, #12] 8008dfc: 4293 cmp r3, r2 8008dfe: d91c bls.n 8008e3a { pep->rem_length -= pep->maxpacket; 8008e00: 693b ldr r3, [r7, #16] 8008e02: 685b ldr r3, [r3, #4] 8008e04: 693a ldr r2, [r7, #16] 8008e06: 8992 ldrh r2, [r2, #12] 8008e08: 1a9a subs r2, r3, r2 8008e0a: 693b ldr r3, [r7, #16] 8008e0c: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8008e0e: 693b ldr r3, [r7, #16] 8008e10: 691b ldr r3, [r3, #16] 8008e12: 693a ldr r2, [r7, #16] 8008e14: 8992 ldrh r2, [r2, #12] 8008e16: 441a add r2, r3 8008e18: 693b ldr r3, [r7, #16] 8008e1a: 611a str r2, [r3, #16] (void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket)); 8008e1c: 693b ldr r3, [r7, #16] 8008e1e: 6919 ldr r1, [r3, #16] 8008e20: 693b ldr r3, [r7, #16] 8008e22: 899b ldrh r3, [r3, #12] 8008e24: 461a mov r2, r3 8008e26: 693b ldr r3, [r7, #16] 8008e28: 685b ldr r3, [r3, #4] 8008e2a: 4293 cmp r3, r2 8008e2c: bf38 it cc 8008e2e: 4613 movcc r3, r2 8008e30: 461a mov r2, r3 8008e32: 68f8 ldr r0, [r7, #12] 8008e34: f001 f9b1 bl 800a19a 8008e38: e07d b.n 8008f36 } else { /* Find the class ID relative to the current request */ switch (pdev->request.bmRequest & 0x1FU) 8008e3a: 68fb ldr r3, [r7, #12] 8008e3c: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8008e40: f003 031f and.w r3, r3, #31 8008e44: 2b02 cmp r3, #2 8008e46: d014 beq.n 8008e72 8008e48: 2b02 cmp r3, #2 8008e4a: d81d bhi.n 8008e88 8008e4c: 2b00 cmp r3, #0 8008e4e: d002 beq.n 8008e56 8008e50: 2b01 cmp r3, #1 8008e52: d003 beq.n 8008e5c 8008e54: e018 b.n 8008e88 { case USB_REQ_RECIPIENT_DEVICE: /* Device requests must be managed by the first instantiated class (or duplicated by all classes for simplicity) */ idx = 0U; 8008e56: 2300 movs r3, #0 8008e58: 75bb strb r3, [r7, #22] break; 8008e5a: e018 b.n 8008e8e case USB_REQ_RECIPIENT_INTERFACE: idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); 8008e5c: 68fb ldr r3, [r7, #12] 8008e5e: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8008e62: b2db uxtb r3, r3 8008e64: 4619 mov r1, r3 8008e66: 68f8 ldr r0, [r7, #12] 8008e68: f000 fa6e bl 8009348 8008e6c: 4603 mov r3, r0 8008e6e: 75bb strb r3, [r7, #22] break; 8008e70: e00d b.n 8008e8e case USB_REQ_RECIPIENT_ENDPOINT: idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); 8008e72: 68fb ldr r3, [r7, #12] 8008e74: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8008e78: b2db uxtb r3, r3 8008e7a: 4619 mov r1, r3 8008e7c: 68f8 ldr r0, [r7, #12] 8008e7e: f000 fa70 bl 8009362 8008e82: 4603 mov r3, r0 8008e84: 75bb strb r3, [r7, #22] break; 8008e86: e002 b.n 8008e8e default: /* Back to the first class in case of doubt */ idx = 0U; 8008e88: 2300 movs r3, #0 8008e8a: 75bb strb r3, [r7, #22] break; 8008e8c: bf00 nop } if (idx < USBD_MAX_SUPPORTED_CLASS) 8008e8e: 7dbb ldrb r3, [r7, #22] 8008e90: 2b00 cmp r3, #0 8008e92: d119 bne.n 8008ec8 { /* Setup the class ID and route the request to the relative class function */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008e94: 68fb ldr r3, [r7, #12] 8008e96: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008e9a: b2db uxtb r3, r3 8008e9c: 2b03 cmp r3, #3 8008e9e: d113 bne.n 8008ec8 { if (pdev->pClass[idx]->EP0_RxReady != NULL) 8008ea0: 7dba ldrb r2, [r7, #22] 8008ea2: 68fb ldr r3, [r7, #12] 8008ea4: 32ae adds r2, #174 @ 0xae 8008ea6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008eaa: 691b ldr r3, [r3, #16] 8008eac: 2b00 cmp r3, #0 8008eae: d00b beq.n 8008ec8 { pdev->classId = idx; 8008eb0: 7dba ldrb r2, [r7, #22] 8008eb2: 68fb ldr r3, [r7, #12] 8008eb4: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[idx]->EP0_RxReady(pdev); 8008eb8: 7dba ldrb r2, [r7, #22] 8008eba: 68fb ldr r3, [r7, #12] 8008ebc: 32ae adds r2, #174 @ 0xae 8008ebe: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008ec2: 691b ldr r3, [r3, #16] 8008ec4: 68f8 ldr r0, [r7, #12] 8008ec6: 4798 blx r3 } } } (void)USBD_CtlSendStatus(pdev); 8008ec8: 68f8 ldr r0, [r7, #12] 8008eca: f001 f977 bl 800a1bc 8008ece: e032 b.n 8008f36 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); 8008ed0: 7afb ldrb r3, [r7, #11] 8008ed2: f003 037f and.w r3, r3, #127 @ 0x7f 8008ed6: b2db uxtb r3, r3 8008ed8: 4619 mov r1, r3 8008eda: 68f8 ldr r0, [r7, #12] 8008edc: f000 fa41 bl 8009362 8008ee0: 4603 mov r3, r0 8008ee2: 75bb strb r3, [r7, #22] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8008ee4: 7dbb ldrb r3, [r7, #22] 8008ee6: 2bff cmp r3, #255 @ 0xff 8008ee8: d025 beq.n 8008f36 8008eea: 7dbb ldrb r3, [r7, #22] 8008eec: 2b00 cmp r3, #0 8008eee: d122 bne.n 8008f36 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008ef0: 68fb ldr r3, [r7, #12] 8008ef2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008ef6: b2db uxtb r3, r3 8008ef8: 2b03 cmp r3, #3 8008efa: d117 bne.n 8008f2c { if (pdev->pClass[idx]->DataOut != NULL) 8008efc: 7dba ldrb r2, [r7, #22] 8008efe: 68fb ldr r3, [r7, #12] 8008f00: 32ae adds r2, #174 @ 0xae 8008f02: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008f06: 699b ldr r3, [r3, #24] 8008f08: 2b00 cmp r3, #0 8008f0a: d00f beq.n 8008f2c { pdev->classId = idx; 8008f0c: 7dba ldrb r2, [r7, #22] 8008f0e: 68fb ldr r3, [r7, #12] 8008f10: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); 8008f14: 7dba ldrb r2, [r7, #22] 8008f16: 68fb ldr r3, [r7, #12] 8008f18: 32ae adds r2, #174 @ 0xae 8008f1a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8008f1e: 699b ldr r3, [r3, #24] 8008f20: 7afa ldrb r2, [r7, #11] 8008f22: 4611 mov r1, r2 8008f24: 68f8 ldr r0, [r7, #12] 8008f26: 4798 blx r3 8008f28: 4603 mov r3, r0 8008f2a: 75fb strb r3, [r7, #23] } } if (ret != USBD_OK) 8008f2c: 7dfb ldrb r3, [r7, #23] 8008f2e: 2b00 cmp r3, #0 8008f30: d001 beq.n 8008f36 { return ret; 8008f32: 7dfb ldrb r3, [r7, #23] 8008f34: e000 b.n 8008f38 } } } return USBD_OK; 8008f36: 2300 movs r3, #0 } 8008f38: 4618 mov r0, r3 8008f3a: 3718 adds r7, #24 8008f3c: 46bd mov sp, r7 8008f3e: bd80 pop {r7, pc} 08008f40 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8008f40: b580 push {r7, lr} 8008f42: b086 sub sp, #24 8008f44: af00 add r7, sp, #0 8008f46: 60f8 str r0, [r7, #12] 8008f48: 460b mov r3, r1 8008f4a: 607a str r2, [r7, #4] 8008f4c: 72fb strb r3, [r7, #11] USBD_StatusTypeDef ret; uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8008f4e: 7afb ldrb r3, [r7, #11] 8008f50: 2b00 cmp r3, #0 8008f52: d178 bne.n 8009046 { pep = &pdev->ep_in[0]; 8008f54: 68fb ldr r3, [r7, #12] 8008f56: 3314 adds r3, #20 8008f58: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 8008f5a: 68fb ldr r3, [r7, #12] 8008f5c: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8008f60: 2b02 cmp r3, #2 8008f62: d163 bne.n 800902c { if (pep->rem_length > pep->maxpacket) 8008f64: 693b ldr r3, [r7, #16] 8008f66: 685b ldr r3, [r3, #4] 8008f68: 693a ldr r2, [r7, #16] 8008f6a: 8992 ldrh r2, [r2, #12] 8008f6c: 4293 cmp r3, r2 8008f6e: d91c bls.n 8008faa { pep->rem_length -= pep->maxpacket; 8008f70: 693b ldr r3, [r7, #16] 8008f72: 685b ldr r3, [r3, #4] 8008f74: 693a ldr r2, [r7, #16] 8008f76: 8992 ldrh r2, [r2, #12] 8008f78: 1a9a subs r2, r3, r2 8008f7a: 693b ldr r3, [r7, #16] 8008f7c: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8008f7e: 693b ldr r3, [r7, #16] 8008f80: 691b ldr r3, [r3, #16] 8008f82: 693a ldr r2, [r7, #16] 8008f84: 8992 ldrh r2, [r2, #12] 8008f86: 441a add r2, r3 8008f88: 693b ldr r3, [r7, #16] 8008f8a: 611a str r2, [r3, #16] (void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length); 8008f8c: 693b ldr r3, [r7, #16] 8008f8e: 6919 ldr r1, [r3, #16] 8008f90: 693b ldr r3, [r7, #16] 8008f92: 685b ldr r3, [r3, #4] 8008f94: 461a mov r2, r3 8008f96: 68f8 ldr r0, [r7, #12] 8008f98: f001 f8ee bl 800a178 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8008f9c: 2300 movs r3, #0 8008f9e: 2200 movs r2, #0 8008fa0: 2100 movs r1, #0 8008fa2: 68f8 ldr r0, [r7, #12] 8008fa4: f001 fd2a bl 800a9fc 8008fa8: e040 b.n 800902c } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 8008faa: 693b ldr r3, [r7, #16] 8008fac: 899b ldrh r3, [r3, #12] 8008fae: 461a mov r2, r3 8008fb0: 693b ldr r3, [r7, #16] 8008fb2: 685b ldr r3, [r3, #4] 8008fb4: 429a cmp r2, r3 8008fb6: d11c bne.n 8008ff2 (pep->total_length >= pep->maxpacket) && 8008fb8: 693b ldr r3, [r7, #16] 8008fba: 681b ldr r3, [r3, #0] 8008fbc: 693a ldr r2, [r7, #16] 8008fbe: 8992 ldrh r2, [r2, #12] if ((pep->maxpacket == pep->rem_length) && 8008fc0: 4293 cmp r3, r2 8008fc2: d316 bcc.n 8008ff2 (pep->total_length < pdev->ep0_data_len)) 8008fc4: 693b ldr r3, [r7, #16] 8008fc6: 681a ldr r2, [r3, #0] 8008fc8: 68fb ldr r3, [r7, #12] 8008fca: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 (pep->total_length >= pep->maxpacket) && 8008fce: 429a cmp r2, r3 8008fd0: d20f bcs.n 8008ff2 { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 8008fd2: 2200 movs r2, #0 8008fd4: 2100 movs r1, #0 8008fd6: 68f8 ldr r0, [r7, #12] 8008fd8: f001 f8ce bl 800a178 pdev->ep0_data_len = 0U; 8008fdc: 68fb ldr r3, [r7, #12] 8008fde: 2200 movs r2, #0 8008fe0: f8c3 2298 str.w r2, [r3, #664] @ 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8008fe4: 2300 movs r3, #0 8008fe6: 2200 movs r2, #0 8008fe8: 2100 movs r1, #0 8008fea: 68f8 ldr r0, [r7, #12] 8008fec: f001 fd06 bl 800a9fc 8008ff0: e01c b.n 800902c } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8008ff2: 68fb ldr r3, [r7, #12] 8008ff4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8008ff8: b2db uxtb r3, r3 8008ffa: 2b03 cmp r3, #3 8008ffc: d10f bne.n 800901e { if (pdev->pClass[0]->EP0_TxSent != NULL) 8008ffe: 68fb ldr r3, [r7, #12] 8009000: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009004: 68db ldr r3, [r3, #12] 8009006: 2b00 cmp r3, #0 8009008: d009 beq.n 800901e { pdev->classId = 0U; 800900a: 68fb ldr r3, [r7, #12] 800900c: 2200 movs r2, #0 800900e: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[0]->EP0_TxSent(pdev); 8009012: 68fb ldr r3, [r7, #12] 8009014: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009018: 68db ldr r3, [r3, #12] 800901a: 68f8 ldr r0, [r7, #12] 800901c: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 800901e: 2180 movs r1, #128 @ 0x80 8009020: 68f8 ldr r0, [r7, #12] 8009022: f001 fc41 bl 800a8a8 (void)USBD_CtlReceiveStatus(pdev); 8009026: 68f8 ldr r0, [r7, #12] 8009028: f001 f8db bl 800a1e2 } } } if (pdev->dev_test_mode != 0U) 800902c: 68fb ldr r3, [r7, #12] 800902e: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 8009032: 2b00 cmp r3, #0 8009034: d03a beq.n 80090ac { (void)USBD_RunTestMode(pdev); 8009036: 68f8 ldr r0, [r7, #12] 8009038: f7ff fe30 bl 8008c9c pdev->dev_test_mode = 0U; 800903c: 68fb ldr r3, [r7, #12] 800903e: 2200 movs r2, #0 8009040: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 8009044: e032 b.n 80090ac } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); 8009046: 7afb ldrb r3, [r7, #11] 8009048: f063 037f orn r3, r3, #127 @ 0x7f 800904c: b2db uxtb r3, r3 800904e: 4619 mov r1, r3 8009050: 68f8 ldr r0, [r7, #12] 8009052: f000 f986 bl 8009362 8009056: 4603 mov r3, r0 8009058: 75fb strb r3, [r7, #23] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800905a: 7dfb ldrb r3, [r7, #23] 800905c: 2bff cmp r3, #255 @ 0xff 800905e: d025 beq.n 80090ac 8009060: 7dfb ldrb r3, [r7, #23] 8009062: 2b00 cmp r3, #0 8009064: d122 bne.n 80090ac { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009066: 68fb ldr r3, [r7, #12] 8009068: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800906c: b2db uxtb r3, r3 800906e: 2b03 cmp r3, #3 8009070: d11c bne.n 80090ac { if (pdev->pClass[idx]->DataIn != NULL) 8009072: 7dfa ldrb r2, [r7, #23] 8009074: 68fb ldr r3, [r7, #12] 8009076: 32ae adds r2, #174 @ 0xae 8009078: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800907c: 695b ldr r3, [r3, #20] 800907e: 2b00 cmp r3, #0 8009080: d014 beq.n 80090ac { pdev->classId = idx; 8009082: 7dfa ldrb r2, [r7, #23] 8009084: 68fb ldr r3, [r7, #12] 8009086: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); 800908a: 7dfa ldrb r2, [r7, #23] 800908c: 68fb ldr r3, [r7, #12] 800908e: 32ae adds r2, #174 @ 0xae 8009090: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009094: 695b ldr r3, [r3, #20] 8009096: 7afa ldrb r2, [r7, #11] 8009098: 4611 mov r1, r2 800909a: 68f8 ldr r0, [r7, #12] 800909c: 4798 blx r3 800909e: 4603 mov r3, r0 80090a0: 75bb strb r3, [r7, #22] if (ret != USBD_OK) 80090a2: 7dbb ldrb r3, [r7, #22] 80090a4: 2b00 cmp r3, #0 80090a6: d001 beq.n 80090ac { return ret; 80090a8: 7dbb ldrb r3, [r7, #22] 80090aa: e000 b.n 80090ae } } } } return USBD_OK; 80090ac: 2300 movs r3, #0 } 80090ae: 4618 mov r0, r3 80090b0: 3718 adds r7, #24 80090b2: 46bd mov sp, r7 80090b4: bd80 pop {r7, pc} 080090b6 : * Handle Reset event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 80090b6: b580 push {r7, lr} 80090b8: b084 sub sp, #16 80090ba: af00 add r7, sp, #0 80090bc: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 80090be: 2300 movs r3, #0 80090c0: 73fb strb r3, [r7, #15] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 80090c2: 687b ldr r3, [r7, #4] 80090c4: 2201 movs r2, #1 80090c6: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->ep0_state = USBD_EP0_IDLE; 80090ca: 687b ldr r3, [r7, #4] 80090cc: 2200 movs r2, #0 80090ce: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->dev_config = 0U; 80090d2: 687b ldr r3, [r7, #4] 80090d4: 2200 movs r2, #0 80090d6: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 80090d8: 687b ldr r3, [r7, #4] 80090da: 2200 movs r2, #0 80090dc: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 pdev->dev_test_mode = 0U; 80090e0: 687b ldr r3, [r7, #4] 80090e2: 2200 movs r2, #0 80090e4: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 } } } #else if (pdev->pClass[0] != NULL) 80090e8: 687b ldr r3, [r7, #4] 80090ea: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80090ee: 2b00 cmp r3, #0 80090f0: d014 beq.n 800911c { if (pdev->pClass[0]->DeInit != NULL) 80090f2: 687b ldr r3, [r7, #4] 80090f4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80090f8: 685b ldr r3, [r3, #4] 80090fa: 2b00 cmp r3, #0 80090fc: d00e beq.n 800911c { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) 80090fe: 687b ldr r3, [r7, #4] 8009100: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009104: 685b ldr r3, [r3, #4] 8009106: 687a ldr r2, [r7, #4] 8009108: 6852 ldr r2, [r2, #4] 800910a: b2d2 uxtb r2, r2 800910c: 4611 mov r1, r2 800910e: 6878 ldr r0, [r7, #4] 8009110: 4798 blx r3 8009112: 4603 mov r3, r0 8009114: 2b00 cmp r3, #0 8009116: d001 beq.n 800911c { ret = USBD_FAIL; 8009118: 2303 movs r3, #3 800911a: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 800911c: 2340 movs r3, #64 @ 0x40 800911e: 2200 movs r2, #0 8009120: 2100 movs r1, #0 8009122: 6878 ldr r0, [r7, #4] 8009124: f001 fb7b bl 800a81e pdev->ep_out[0x00U & 0xFU].is_used = 1U; 8009128: 687b ldr r3, [r7, #4] 800912a: 2201 movs r2, #1 800912c: f883 2163 strb.w r2, [r3, #355] @ 0x163 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 8009130: 687b ldr r3, [r7, #4] 8009132: 2240 movs r2, #64 @ 0x40 8009134: f8a3 2160 strh.w r2, [r3, #352] @ 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8009138: 2340 movs r3, #64 @ 0x40 800913a: 2200 movs r2, #0 800913c: 2180 movs r1, #128 @ 0x80 800913e: 6878 ldr r0, [r7, #4] 8009140: f001 fb6d bl 800a81e pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8009144: 687b ldr r3, [r7, #4] 8009146: 2201 movs r2, #1 8009148: f883 2023 strb.w r2, [r3, #35] @ 0x23 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 800914c: 687b ldr r3, [r7, #4] 800914e: 2240 movs r2, #64 @ 0x40 8009150: 841a strh r2, [r3, #32] return ret; 8009152: 7bfb ldrb r3, [r7, #15] } 8009154: 4618 mov r0, r3 8009156: 3710 adds r7, #16 8009158: 46bd mov sp, r7 800915a: bd80 pop {r7, pc} 0800915c : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 800915c: b480 push {r7} 800915e: b083 sub sp, #12 8009160: af00 add r7, sp, #0 8009162: 6078 str r0, [r7, #4] 8009164: 460b mov r3, r1 8009166: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 8009168: 687b ldr r3, [r7, #4] 800916a: 78fa ldrb r2, [r7, #3] 800916c: 741a strb r2, [r3, #16] return USBD_OK; 800916e: 2300 movs r3, #0 } 8009170: 4618 mov r0, r3 8009172: 370c adds r7, #12 8009174: 46bd mov sp, r7 8009176: f85d 7b04 ldr.w r7, [sp], #4 800917a: 4770 bx lr 0800917c : * Handle Suspend event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 800917c: b480 push {r7} 800917e: b083 sub sp, #12 8009180: af00 add r7, sp, #0 8009182: 6078 str r0, [r7, #4] if (pdev->dev_state != USBD_STATE_SUSPENDED) 8009184: 687b ldr r3, [r7, #4] 8009186: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800918a: b2db uxtb r3, r3 800918c: 2b04 cmp r3, #4 800918e: d006 beq.n 800919e { pdev->dev_old_state = pdev->dev_state; 8009190: 687b ldr r3, [r7, #4] 8009192: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009196: b2da uxtb r2, r3 8009198: 687b ldr r3, [r7, #4] 800919a: f883 229d strb.w r2, [r3, #669] @ 0x29d } pdev->dev_state = USBD_STATE_SUSPENDED; 800919e: 687b ldr r3, [r7, #4] 80091a0: 2204 movs r2, #4 80091a2: f883 229c strb.w r2, [r3, #668] @ 0x29c return USBD_OK; 80091a6: 2300 movs r3, #0 } 80091a8: 4618 mov r0, r3 80091aa: 370c adds r7, #12 80091ac: 46bd mov sp, r7 80091ae: f85d 7b04 ldr.w r7, [sp], #4 80091b2: 4770 bx lr 080091b4 : * Handle Resume event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 80091b4: b480 push {r7} 80091b6: b083 sub sp, #12 80091b8: af00 add r7, sp, #0 80091ba: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 80091bc: 687b ldr r3, [r7, #4] 80091be: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80091c2: b2db uxtb r3, r3 80091c4: 2b04 cmp r3, #4 80091c6: d106 bne.n 80091d6 { pdev->dev_state = pdev->dev_old_state; 80091c8: 687b ldr r3, [r7, #4] 80091ca: f893 329d ldrb.w r3, [r3, #669] @ 0x29d 80091ce: b2da uxtb r2, r3 80091d0: 687b ldr r3, [r7, #4] 80091d2: f883 229c strb.w r2, [r3, #668] @ 0x29c } return USBD_OK; 80091d6: 2300 movs r3, #0 } 80091d8: 4618 mov r0, r3 80091da: 370c adds r7, #12 80091dc: 46bd mov sp, r7 80091de: f85d 7b04 ldr.w r7, [sp], #4 80091e2: 4770 bx lr 080091e4 : * Handle SOF event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 80091e4: b580 push {r7, lr} 80091e6: b082 sub sp, #8 80091e8: af00 add r7, sp, #0 80091ea: 6078 str r0, [r7, #4] /* The SOF event can be distributed for all classes that support it */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 80091ec: 687b ldr r3, [r7, #4] 80091ee: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80091f2: b2db uxtb r3, r3 80091f4: 2b03 cmp r3, #3 80091f6: d110 bne.n 800921a } } } } #else if (pdev->pClass[0] != NULL) 80091f8: 687b ldr r3, [r7, #4] 80091fa: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80091fe: 2b00 cmp r3, #0 8009200: d00b beq.n 800921a { if (pdev->pClass[0]->SOF != NULL) 8009202: 687b ldr r3, [r7, #4] 8009204: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009208: 69db ldr r3, [r3, #28] 800920a: 2b00 cmp r3, #0 800920c: d005 beq.n 800921a { (void)pdev->pClass[0]->SOF(pdev); 800920e: 687b ldr r3, [r7, #4] 8009210: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009214: 69db ldr r3, [r3, #28] 8009216: 6878 ldr r0, [r7, #4] 8009218: 4798 blx r3 } } #endif /* USE_USBD_COMPOSITE */ } return USBD_OK; 800921a: 2300 movs r3, #0 } 800921c: 4618 mov r0, r3 800921e: 3708 adds r7, #8 8009220: 46bd mov sp, r7 8009222: bd80 pop {r7, pc} 08009224 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009224: b580 push {r7, lr} 8009226: b082 sub sp, #8 8009228: af00 add r7, sp, #0 800922a: 6078 str r0, [r7, #4] 800922c: 460b mov r3, r1 800922e: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009230: 687b ldr r3, [r7, #4] 8009232: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009236: 687b ldr r3, [r7, #4] 8009238: 32ae adds r2, #174 @ 0xae 800923a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800923e: 2b00 cmp r3, #0 8009240: d101 bne.n 8009246 { return USBD_FAIL; 8009242: 2303 movs r3, #3 8009244: e01c b.n 8009280 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009246: 687b ldr r3, [r7, #4] 8009248: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800924c: b2db uxtb r3, r3 800924e: 2b03 cmp r3, #3 8009250: d115 bne.n 800927e { if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL) 8009252: 687b ldr r3, [r7, #4] 8009254: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009258: 687b ldr r3, [r7, #4] 800925a: 32ae adds r2, #174 @ 0xae 800925c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009260: 6a1b ldr r3, [r3, #32] 8009262: 2b00 cmp r3, #0 8009264: d00b beq.n 800927e { (void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum); 8009266: 687b ldr r3, [r7, #4] 8009268: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800926c: 687b ldr r3, [r7, #4] 800926e: 32ae adds r2, #174 @ 0xae 8009270: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009274: 6a1b ldr r3, [r3, #32] 8009276: 78fa ldrb r2, [r7, #3] 8009278: 4611 mov r1, r2 800927a: 6878 ldr r0, [r7, #4] 800927c: 4798 blx r3 } } return USBD_OK; 800927e: 2300 movs r3, #0 } 8009280: 4618 mov r0, r3 8009282: 3708 adds r7, #8 8009284: 46bd mov sp, r7 8009286: bd80 pop {r7, pc} 08009288 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009288: b580 push {r7, lr} 800928a: b082 sub sp, #8 800928c: af00 add r7, sp, #0 800928e: 6078 str r0, [r7, #4] 8009290: 460b mov r3, r1 8009292: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009294: 687b ldr r3, [r7, #4] 8009296: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800929a: 687b ldr r3, [r7, #4] 800929c: 32ae adds r2, #174 @ 0xae 800929e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80092a2: 2b00 cmp r3, #0 80092a4: d101 bne.n 80092aa { return USBD_FAIL; 80092a6: 2303 movs r3, #3 80092a8: e01c b.n 80092e4 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 80092aa: 687b ldr r3, [r7, #4] 80092ac: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80092b0: b2db uxtb r3, r3 80092b2: 2b03 cmp r3, #3 80092b4: d115 bne.n 80092e2 { if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL) 80092b6: 687b ldr r3, [r7, #4] 80092b8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80092bc: 687b ldr r3, [r7, #4] 80092be: 32ae adds r2, #174 @ 0xae 80092c0: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80092c4: 6a5b ldr r3, [r3, #36] @ 0x24 80092c6: 2b00 cmp r3, #0 80092c8: d00b beq.n 80092e2 { (void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum); 80092ca: 687b ldr r3, [r7, #4] 80092cc: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80092d0: 687b ldr r3, [r7, #4] 80092d2: 32ae adds r2, #174 @ 0xae 80092d4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80092d8: 6a5b ldr r3, [r3, #36] @ 0x24 80092da: 78fa ldrb r2, [r7, #3] 80092dc: 4611 mov r1, r2 80092de: 6878 ldr r0, [r7, #4] 80092e0: 4798 blx r3 } } return USBD_OK; 80092e2: 2300 movs r3, #0 } 80092e4: 4618 mov r0, r3 80092e6: 3708 adds r7, #8 80092e8: 46bd mov sp, r7 80092ea: bd80 pop {r7, pc} 080092ec : * Handle device connection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { 80092ec: b480 push {r7} 80092ee: b083 sub sp, #12 80092f0: af00 add r7, sp, #0 80092f2: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 80092f4: 2300 movs r3, #0 } 80092f6: 4618 mov r0, r3 80092f8: 370c adds r7, #12 80092fa: 46bd mov sp, r7 80092fc: f85d 7b04 ldr.w r7, [sp], #4 8009300: 4770 bx lr 08009302 : * Handle device disconnection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { 8009302: b580 push {r7, lr} 8009304: b084 sub sp, #16 8009306: af00 add r7, sp, #0 8009308: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 800930a: 2300 movs r3, #0 800930c: 73fb strb r3, [r7, #15] /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; 800930e: 687b ldr r3, [r7, #4] 8009310: 2201 movs r2, #1 8009312: f883 229c strb.w r2, [r3, #668] @ 0x29c } } } } #else if (pdev->pClass[0] != NULL) 8009316: 687b ldr r3, [r7, #4] 8009318: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800931c: 2b00 cmp r3, #0 800931e: d00e beq.n 800933e { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U) 8009320: 687b ldr r3, [r7, #4] 8009322: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009326: 685b ldr r3, [r3, #4] 8009328: 687a ldr r2, [r7, #4] 800932a: 6852 ldr r2, [r2, #4] 800932c: b2d2 uxtb r2, r2 800932e: 4611 mov r1, r2 8009330: 6878 ldr r0, [r7, #4] 8009332: 4798 blx r3 8009334: 4603 mov r3, r0 8009336: 2b00 cmp r3, #0 8009338: d001 beq.n 800933e { ret = USBD_FAIL; 800933a: 2303 movs r3, #3 800933c: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ return ret; 800933e: 7bfb ldrb r3, [r7, #15] } 8009340: 4618 mov r0, r3 8009342: 3710 adds r7, #16 8009344: 46bd mov sp, r7 8009346: bd80 pop {r7, pc} 08009348 : * @param pdev: device instance * @param index : selected interface number * @retval index of the class using the selected interface number. OxFF if no class found. */ uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) { 8009348: b480 push {r7} 800934a: b083 sub sp, #12 800934c: af00 add r7, sp, #0 800934e: 6078 str r0, [r7, #4] 8009350: 460b mov r3, r1 8009352: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009354: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8009356: 4618 mov r0, r3 8009358: 370c adds r7, #12 800935a: 46bd mov sp, r7 800935c: f85d 7b04 ldr.w r7, [sp], #4 8009360: 4770 bx lr 08009362 : * @param pdev: device instance * @param index : selected endpoint number * @retval index of the class using the selected endpoint number. 0xFF if no class found. */ uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) { 8009362: b480 push {r7} 8009364: b083 sub sp, #12 8009366: af00 add r7, sp, #0 8009368: 6078 str r0, [r7, #4] 800936a: 460b mov r3, r1 800936c: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 800936e: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8009370: 4618 mov r0, r3 8009372: 370c adds r7, #12 8009374: 46bd mov sp, r7 8009376: f85d 7b04 ldr.w r7, [sp], #4 800937a: 4770 bx lr 0800937c : * @param pConfDesc: pointer to Bos descriptor * @param EpAddr: endpoint address * @retval pointer to video endpoint descriptor */ void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) { 800937c: b580 push {r7, lr} 800937e: b086 sub sp, #24 8009380: af00 add r7, sp, #0 8009382: 6078 str r0, [r7, #4] 8009384: 460b mov r3, r1 8009386: 70fb strb r3, [r7, #3] USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; 8009388: 687b ldr r3, [r7, #4] 800938a: 617b str r3, [r7, #20] USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; 800938c: 687b ldr r3, [r7, #4] 800938e: 60fb str r3, [r7, #12] USBD_EpDescTypeDef *pEpDesc = NULL; 8009390: 2300 movs r3, #0 8009392: 613b str r3, [r7, #16] uint16_t ptr; if (desc->wTotalLength > desc->bLength) 8009394: 68fb ldr r3, [r7, #12] 8009396: 885b ldrh r3, [r3, #2] 8009398: b29b uxth r3, r3 800939a: 68fa ldr r2, [r7, #12] 800939c: 7812 ldrb r2, [r2, #0] 800939e: 4293 cmp r3, r2 80093a0: d91f bls.n 80093e2 { ptr = desc->bLength; 80093a2: 68fb ldr r3, [r7, #12] 80093a4: 781b ldrb r3, [r3, #0] 80093a6: 817b strh r3, [r7, #10] while (ptr < desc->wTotalLength) 80093a8: e013 b.n 80093d2 { pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); 80093aa: f107 030a add.w r3, r7, #10 80093ae: 4619 mov r1, r3 80093b0: 6978 ldr r0, [r7, #20] 80093b2: f000 f81b bl 80093ec 80093b6: 6178 str r0, [r7, #20] if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) 80093b8: 697b ldr r3, [r7, #20] 80093ba: 785b ldrb r3, [r3, #1] 80093bc: 2b05 cmp r3, #5 80093be: d108 bne.n 80093d2 { pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; 80093c0: 697b ldr r3, [r7, #20] 80093c2: 613b str r3, [r7, #16] if (pEpDesc->bEndpointAddress == EpAddr) 80093c4: 693b ldr r3, [r7, #16] 80093c6: 789b ldrb r3, [r3, #2] 80093c8: 78fa ldrb r2, [r7, #3] 80093ca: 429a cmp r2, r3 80093cc: d008 beq.n 80093e0 { break; } else { pEpDesc = NULL; 80093ce: 2300 movs r3, #0 80093d0: 613b str r3, [r7, #16] while (ptr < desc->wTotalLength) 80093d2: 68fb ldr r3, [r7, #12] 80093d4: 885b ldrh r3, [r3, #2] 80093d6: b29a uxth r2, r3 80093d8: 897b ldrh r3, [r7, #10] 80093da: 429a cmp r2, r3 80093dc: d8e5 bhi.n 80093aa 80093de: e000 b.n 80093e2 break; 80093e0: bf00 nop } } } } return (void *)pEpDesc; 80093e2: 693b ldr r3, [r7, #16] } 80093e4: 4618 mov r0, r3 80093e6: 3718 adds r7, #24 80093e8: 46bd mov sp, r7 80093ea: bd80 pop {r7, pc} 080093ec : * @param buf: Buffer where the descriptor is available * @param ptr: data pointer inside the descriptor * @retval next header */ USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) { 80093ec: b480 push {r7} 80093ee: b085 sub sp, #20 80093f0: af00 add r7, sp, #0 80093f2: 6078 str r0, [r7, #4] 80093f4: 6039 str r1, [r7, #0] USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; 80093f6: 687b ldr r3, [r7, #4] 80093f8: 60fb str r3, [r7, #12] *ptr += pnext->bLength; 80093fa: 683b ldr r3, [r7, #0] 80093fc: 881b ldrh r3, [r3, #0] 80093fe: 68fa ldr r2, [r7, #12] 8009400: 7812 ldrb r2, [r2, #0] 8009402: 4413 add r3, r2 8009404: b29a uxth r2, r3 8009406: 683b ldr r3, [r7, #0] 8009408: 801a strh r2, [r3, #0] pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); 800940a: 68fb ldr r3, [r7, #12] 800940c: 781b ldrb r3, [r3, #0] 800940e: 461a mov r2, r3 8009410: 687b ldr r3, [r7, #4] 8009412: 4413 add r3, r2 8009414: 60fb str r3, [r7, #12] return (pnext); 8009416: 68fb ldr r3, [r7, #12] } 8009418: 4618 mov r0, r3 800941a: 3714 adds r7, #20 800941c: 46bd mov sp, r7 800941e: f85d 7b04 ldr.w r7, [sp], #4 8009422: 4770 bx lr 08009424 : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 8009424: b480 push {r7} 8009426: b087 sub sp, #28 8009428: af00 add r7, sp, #0 800942a: 6078 str r0, [r7, #4] uint16_t _SwapVal; uint16_t _Byte1; uint16_t _Byte2; uint8_t *_pbuff = addr; 800942c: 687b ldr r3, [r7, #4] 800942e: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 8009430: 697b ldr r3, [r7, #20] 8009432: 781b ldrb r3, [r3, #0] 8009434: 827b strh r3, [r7, #18] _pbuff++; 8009436: 697b ldr r3, [r7, #20] 8009438: 3301 adds r3, #1 800943a: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 800943c: 697b ldr r3, [r7, #20] 800943e: 781b ldrb r3, [r3, #0] 8009440: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 8009442: f9b7 3010 ldrsh.w r3, [r7, #16] 8009446: 021b lsls r3, r3, #8 8009448: b21a sxth r2, r3 800944a: f9b7 3012 ldrsh.w r3, [r7, #18] 800944e: 4313 orrs r3, r2 8009450: b21b sxth r3, r3 8009452: 81fb strh r3, [r7, #14] return _SwapVal; 8009454: 89fb ldrh r3, [r7, #14] } 8009456: 4618 mov r0, r3 8009458: 371c adds r7, #28 800945a: 46bd mov sp, r7 800945c: f85d 7b04 ldr.w r7, [sp], #4 8009460: 4770 bx lr ... 08009464 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009464: b580 push {r7, lr} 8009466: b084 sub sp, #16 8009468: af00 add r7, sp, #0 800946a: 6078 str r0, [r7, #4] 800946c: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800946e: 2300 movs r3, #0 8009470: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009472: 683b ldr r3, [r7, #0] 8009474: 781b ldrb r3, [r3, #0] 8009476: f003 0360 and.w r3, r3, #96 @ 0x60 800947a: 2b40 cmp r3, #64 @ 0x40 800947c: d005 beq.n 800948a 800947e: 2b40 cmp r3, #64 @ 0x40 8009480: d857 bhi.n 8009532 8009482: 2b00 cmp r3, #0 8009484: d00f beq.n 80094a6 8009486: 2b20 cmp r3, #32 8009488: d153 bne.n 8009532 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); 800948a: 687b ldr r3, [r7, #4] 800948c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009490: 687b ldr r3, [r7, #4] 8009492: 32ae adds r2, #174 @ 0xae 8009494: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009498: 689b ldr r3, [r3, #8] 800949a: 6839 ldr r1, [r7, #0] 800949c: 6878 ldr r0, [r7, #4] 800949e: 4798 blx r3 80094a0: 4603 mov r3, r0 80094a2: 73fb strb r3, [r7, #15] break; 80094a4: e04a b.n 800953c case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80094a6: 683b ldr r3, [r7, #0] 80094a8: 785b ldrb r3, [r3, #1] 80094aa: 2b09 cmp r3, #9 80094ac: d83b bhi.n 8009526 80094ae: a201 add r2, pc, #4 @ (adr r2, 80094b4 ) 80094b0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80094b4: 08009509 .word 0x08009509 80094b8: 0800951d .word 0x0800951d 80094bc: 08009527 .word 0x08009527 80094c0: 08009513 .word 0x08009513 80094c4: 08009527 .word 0x08009527 80094c8: 080094e7 .word 0x080094e7 80094cc: 080094dd .word 0x080094dd 80094d0: 08009527 .word 0x08009527 80094d4: 080094ff .word 0x080094ff 80094d8: 080094f1 .word 0x080094f1 { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 80094dc: 6839 ldr r1, [r7, #0] 80094de: 6878 ldr r0, [r7, #4] 80094e0: f000 fa3e bl 8009960 break; 80094e4: e024 b.n 8009530 case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 80094e6: 6839 ldr r1, [r7, #0] 80094e8: 6878 ldr r0, [r7, #4] 80094ea: f000 fbcd bl 8009c88 break; 80094ee: e01f b.n 8009530 case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 80094f0: 6839 ldr r1, [r7, #0] 80094f2: 6878 ldr r0, [r7, #4] 80094f4: f000 fc0c bl 8009d10 80094f8: 4603 mov r3, r0 80094fa: 73fb strb r3, [r7, #15] break; 80094fc: e018 b.n 8009530 case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 80094fe: 6839 ldr r1, [r7, #0] 8009500: 6878 ldr r0, [r7, #4] 8009502: f000 fcaf bl 8009e64 break; 8009506: e013 b.n 8009530 case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 8009508: 6839 ldr r1, [r7, #0] 800950a: 6878 ldr r0, [r7, #4] 800950c: f000 fce0 bl 8009ed0 break; 8009510: e00e b.n 8009530 case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 8009512: 6839 ldr r1, [r7, #0] 8009514: 6878 ldr r0, [r7, #4] 8009516: f000 fd0f bl 8009f38 break; 800951a: e009 b.n 8009530 case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 800951c: 6839 ldr r1, [r7, #0] 800951e: 6878 ldr r0, [r7, #4] 8009520: f000 fd33 bl 8009f8a break; 8009524: e004 b.n 8009530 default: USBD_CtlError(pdev, req); 8009526: 6839 ldr r1, [r7, #0] 8009528: 6878 ldr r0, [r7, #4] 800952a: f000 fd8a bl 800a042 break; 800952e: bf00 nop } break; 8009530: e004 b.n 800953c default: USBD_CtlError(pdev, req); 8009532: 6839 ldr r1, [r7, #0] 8009534: 6878 ldr r0, [r7, #4] 8009536: f000 fd84 bl 800a042 break; 800953a: bf00 nop } return ret; 800953c: 7bfb ldrb r3, [r7, #15] } 800953e: 4618 mov r0, r3 8009540: 3710 adds r7, #16 8009542: 46bd mov sp, r7 8009544: bd80 pop {r7, pc} 8009546: bf00 nop 08009548 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009548: b580 push {r7, lr} 800954a: b084 sub sp, #16 800954c: af00 add r7, sp, #0 800954e: 6078 str r0, [r7, #4] 8009550: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8009552: 2300 movs r3, #0 8009554: 73fb strb r3, [r7, #15] uint8_t idx; switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009556: 683b ldr r3, [r7, #0] 8009558: 781b ldrb r3, [r3, #0] 800955a: f003 0360 and.w r3, r3, #96 @ 0x60 800955e: 2b40 cmp r3, #64 @ 0x40 8009560: d005 beq.n 800956e 8009562: 2b40 cmp r3, #64 @ 0x40 8009564: d852 bhi.n 800960c 8009566: 2b00 cmp r3, #0 8009568: d001 beq.n 800956e 800956a: 2b20 cmp r3, #32 800956c: d14e bne.n 800960c { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 800956e: 687b ldr r3, [r7, #4] 8009570: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009574: b2db uxtb r3, r3 8009576: 3b01 subs r3, #1 8009578: 2b02 cmp r3, #2 800957a: d840 bhi.n 80095fe { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 800957c: 683b ldr r3, [r7, #0] 800957e: 889b ldrh r3, [r3, #4] 8009580: b2db uxtb r3, r3 8009582: 2b01 cmp r3, #1 8009584: d836 bhi.n 80095f4 { /* Get the class index relative to this interface */ idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); 8009586: 683b ldr r3, [r7, #0] 8009588: 889b ldrh r3, [r3, #4] 800958a: b2db uxtb r3, r3 800958c: 4619 mov r1, r3 800958e: 6878 ldr r0, [r7, #4] 8009590: f7ff feda bl 8009348 8009594: 4603 mov r3, r0 8009596: 73bb strb r3, [r7, #14] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009598: 7bbb ldrb r3, [r7, #14] 800959a: 2bff cmp r3, #255 @ 0xff 800959c: d01d beq.n 80095da 800959e: 7bbb ldrb r3, [r7, #14] 80095a0: 2b00 cmp r3, #0 80095a2: d11a bne.n 80095da { /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 80095a4: 7bba ldrb r2, [r7, #14] 80095a6: 687b ldr r3, [r7, #4] 80095a8: 32ae adds r2, #174 @ 0xae 80095aa: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80095ae: 689b ldr r3, [r3, #8] 80095b0: 2b00 cmp r3, #0 80095b2: d00f beq.n 80095d4 { pdev->classId = idx; 80095b4: 7bba ldrb r2, [r7, #14] 80095b6: 687b ldr r3, [r7, #4] 80095b8: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 80095bc: 7bba ldrb r2, [r7, #14] 80095be: 687b ldr r3, [r7, #4] 80095c0: 32ae adds r2, #174 @ 0xae 80095c2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80095c6: 689b ldr r3, [r3, #8] 80095c8: 6839 ldr r1, [r7, #0] 80095ca: 6878 ldr r0, [r7, #4] 80095cc: 4798 blx r3 80095ce: 4603 mov r3, r0 80095d0: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 80095d2: e004 b.n 80095de } else { /* should never reach this condition */ ret = USBD_FAIL; 80095d4: 2303 movs r3, #3 80095d6: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 80095d8: e001 b.n 80095de } } else { /* No relative interface found */ ret = USBD_FAIL; 80095da: 2303 movs r3, #3 80095dc: 73fb strb r3, [r7, #15] } if ((req->wLength == 0U) && (ret == USBD_OK)) 80095de: 683b ldr r3, [r7, #0] 80095e0: 88db ldrh r3, [r3, #6] 80095e2: 2b00 cmp r3, #0 80095e4: d110 bne.n 8009608 80095e6: 7bfb ldrb r3, [r7, #15] 80095e8: 2b00 cmp r3, #0 80095ea: d10d bne.n 8009608 { (void)USBD_CtlSendStatus(pdev); 80095ec: 6878 ldr r0, [r7, #4] 80095ee: f000 fde5 bl 800a1bc } else { USBD_CtlError(pdev, req); } break; 80095f2: e009 b.n 8009608 USBD_CtlError(pdev, req); 80095f4: 6839 ldr r1, [r7, #0] 80095f6: 6878 ldr r0, [r7, #4] 80095f8: f000 fd23 bl 800a042 break; 80095fc: e004 b.n 8009608 default: USBD_CtlError(pdev, req); 80095fe: 6839 ldr r1, [r7, #0] 8009600: 6878 ldr r0, [r7, #4] 8009602: f000 fd1e bl 800a042 break; 8009606: e000 b.n 800960a break; 8009608: bf00 nop } break; 800960a: e004 b.n 8009616 default: USBD_CtlError(pdev, req); 800960c: 6839 ldr r1, [r7, #0] 800960e: 6878 ldr r0, [r7, #4] 8009610: f000 fd17 bl 800a042 break; 8009614: bf00 nop } return ret; 8009616: 7bfb ldrb r3, [r7, #15] } 8009618: 4618 mov r0, r3 800961a: 3710 adds r7, #16 800961c: 46bd mov sp, r7 800961e: bd80 pop {r7, pc} 08009620 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009620: b580 push {r7, lr} 8009622: b084 sub sp, #16 8009624: af00 add r7, sp, #0 8009626: 6078 str r0, [r7, #4] 8009628: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; uint8_t idx; USBD_StatusTypeDef ret = USBD_OK; 800962a: 2300 movs r3, #0 800962c: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 800962e: 683b ldr r3, [r7, #0] 8009630: 889b ldrh r3, [r3, #4] 8009632: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009634: 683b ldr r3, [r7, #0] 8009636: 781b ldrb r3, [r3, #0] 8009638: f003 0360 and.w r3, r3, #96 @ 0x60 800963c: 2b40 cmp r3, #64 @ 0x40 800963e: d007 beq.n 8009650 8009640: 2b40 cmp r3, #64 @ 0x40 8009642: f200 8181 bhi.w 8009948 8009646: 2b00 cmp r3, #0 8009648: d02a beq.n 80096a0 800964a: 2b20 cmp r3, #32 800964c: f040 817c bne.w 8009948 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: /* Get the class index relative to this endpoint */ idx = USBD_CoreFindEP(pdev, ep_addr); 8009650: 7bbb ldrb r3, [r7, #14] 8009652: 4619 mov r1, r3 8009654: 6878 ldr r0, [r7, #4] 8009656: f7ff fe84 bl 8009362 800965a: 4603 mov r3, r0 800965c: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800965e: 7b7b ldrb r3, [r7, #13] 8009660: 2bff cmp r3, #255 @ 0xff 8009662: f000 8176 beq.w 8009952 8009666: 7b7b ldrb r3, [r7, #13] 8009668: 2b00 cmp r3, #0 800966a: f040 8172 bne.w 8009952 { pdev->classId = idx; 800966e: 7b7a ldrb r2, [r7, #13] 8009670: 687b ldr r3, [r7, #4] 8009672: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8009676: 7b7a ldrb r2, [r7, #13] 8009678: 687b ldr r3, [r7, #4] 800967a: 32ae adds r2, #174 @ 0xae 800967c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009680: 689b ldr r3, [r3, #8] 8009682: 2b00 cmp r3, #0 8009684: f000 8165 beq.w 8009952 { ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); 8009688: 7b7a ldrb r2, [r7, #13] 800968a: 687b ldr r3, [r7, #4] 800968c: 32ae adds r2, #174 @ 0xae 800968e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009692: 689b ldr r3, [r3, #8] 8009694: 6839 ldr r1, [r7, #0] 8009696: 6878 ldr r0, [r7, #4] 8009698: 4798 blx r3 800969a: 4603 mov r3, r0 800969c: 73fb strb r3, [r7, #15] } } break; 800969e: e158 b.n 8009952 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80096a0: 683b ldr r3, [r7, #0] 80096a2: 785b ldrb r3, [r3, #1] 80096a4: 2b03 cmp r3, #3 80096a6: d008 beq.n 80096ba 80096a8: 2b03 cmp r3, #3 80096aa: f300 8147 bgt.w 800993c 80096ae: 2b00 cmp r3, #0 80096b0: f000 809b beq.w 80097ea 80096b4: 2b01 cmp r3, #1 80096b6: d03c beq.n 8009732 80096b8: e140 b.n 800993c { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 80096ba: 687b ldr r3, [r7, #4] 80096bc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80096c0: b2db uxtb r3, r3 80096c2: 2b02 cmp r3, #2 80096c4: d002 beq.n 80096cc 80096c6: 2b03 cmp r3, #3 80096c8: d016 beq.n 80096f8 80096ca: e02c b.n 8009726 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80096cc: 7bbb ldrb r3, [r7, #14] 80096ce: 2b00 cmp r3, #0 80096d0: d00d beq.n 80096ee 80096d2: 7bbb ldrb r3, [r7, #14] 80096d4: 2b80 cmp r3, #128 @ 0x80 80096d6: d00a beq.n 80096ee { (void)USBD_LL_StallEP(pdev, ep_addr); 80096d8: 7bbb ldrb r3, [r7, #14] 80096da: 4619 mov r1, r3 80096dc: 6878 ldr r0, [r7, #4] 80096de: f001 f8e3 bl 800a8a8 (void)USBD_LL_StallEP(pdev, 0x80U); 80096e2: 2180 movs r1, #128 @ 0x80 80096e4: 6878 ldr r0, [r7, #4] 80096e6: f001 f8df bl 800a8a8 80096ea: bf00 nop } else { USBD_CtlError(pdev, req); } break; 80096ec: e020 b.n 8009730 USBD_CtlError(pdev, req); 80096ee: 6839 ldr r1, [r7, #0] 80096f0: 6878 ldr r0, [r7, #4] 80096f2: f000 fca6 bl 800a042 break; 80096f6: e01b b.n 8009730 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 80096f8: 683b ldr r3, [r7, #0] 80096fa: 885b ldrh r3, [r3, #2] 80096fc: 2b00 cmp r3, #0 80096fe: d10e bne.n 800971e { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 8009700: 7bbb ldrb r3, [r7, #14] 8009702: 2b00 cmp r3, #0 8009704: d00b beq.n 800971e 8009706: 7bbb ldrb r3, [r7, #14] 8009708: 2b80 cmp r3, #128 @ 0x80 800970a: d008 beq.n 800971e 800970c: 683b ldr r3, [r7, #0] 800970e: 88db ldrh r3, [r3, #6] 8009710: 2b00 cmp r3, #0 8009712: d104 bne.n 800971e { (void)USBD_LL_StallEP(pdev, ep_addr); 8009714: 7bbb ldrb r3, [r7, #14] 8009716: 4619 mov r1, r3 8009718: 6878 ldr r0, [r7, #4] 800971a: f001 f8c5 bl 800a8a8 } } (void)USBD_CtlSendStatus(pdev); 800971e: 6878 ldr r0, [r7, #4] 8009720: f000 fd4c bl 800a1bc break; 8009724: e004 b.n 8009730 default: USBD_CtlError(pdev, req); 8009726: 6839 ldr r1, [r7, #0] 8009728: 6878 ldr r0, [r7, #4] 800972a: f000 fc8a bl 800a042 break; 800972e: bf00 nop } break; 8009730: e109 b.n 8009946 case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 8009732: 687b ldr r3, [r7, #4] 8009734: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009738: b2db uxtb r3, r3 800973a: 2b02 cmp r3, #2 800973c: d002 beq.n 8009744 800973e: 2b03 cmp r3, #3 8009740: d016 beq.n 8009770 8009742: e04b b.n 80097dc { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8009744: 7bbb ldrb r3, [r7, #14] 8009746: 2b00 cmp r3, #0 8009748: d00d beq.n 8009766 800974a: 7bbb ldrb r3, [r7, #14] 800974c: 2b80 cmp r3, #128 @ 0x80 800974e: d00a beq.n 8009766 { (void)USBD_LL_StallEP(pdev, ep_addr); 8009750: 7bbb ldrb r3, [r7, #14] 8009752: 4619 mov r1, r3 8009754: 6878 ldr r0, [r7, #4] 8009756: f001 f8a7 bl 800a8a8 (void)USBD_LL_StallEP(pdev, 0x80U); 800975a: 2180 movs r1, #128 @ 0x80 800975c: 6878 ldr r0, [r7, #4] 800975e: f001 f8a3 bl 800a8a8 8009762: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8009764: e040 b.n 80097e8 USBD_CtlError(pdev, req); 8009766: 6839 ldr r1, [r7, #0] 8009768: 6878 ldr r0, [r7, #4] 800976a: f000 fc6a bl 800a042 break; 800976e: e03b b.n 80097e8 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8009770: 683b ldr r3, [r7, #0] 8009772: 885b ldrh r3, [r3, #2] 8009774: 2b00 cmp r3, #0 8009776: d136 bne.n 80097e6 { if ((ep_addr & 0x7FU) != 0x00U) 8009778: 7bbb ldrb r3, [r7, #14] 800977a: f003 037f and.w r3, r3, #127 @ 0x7f 800977e: 2b00 cmp r3, #0 8009780: d004 beq.n 800978c { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 8009782: 7bbb ldrb r3, [r7, #14] 8009784: 4619 mov r1, r3 8009786: 6878 ldr r0, [r7, #4] 8009788: f001 f8ad bl 800a8e6 } (void)USBD_CtlSendStatus(pdev); 800978c: 6878 ldr r0, [r7, #4] 800978e: f000 fd15 bl 800a1bc /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ep_addr); 8009792: 7bbb ldrb r3, [r7, #14] 8009794: 4619 mov r1, r3 8009796: 6878 ldr r0, [r7, #4] 8009798: f7ff fde3 bl 8009362 800979c: 4603 mov r3, r0 800979e: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 80097a0: 7b7b ldrb r3, [r7, #13] 80097a2: 2bff cmp r3, #255 @ 0xff 80097a4: d01f beq.n 80097e6 80097a6: 7b7b ldrb r3, [r7, #13] 80097a8: 2b00 cmp r3, #0 80097aa: d11c bne.n 80097e6 { pdev->classId = idx; 80097ac: 7b7a ldrb r2, [r7, #13] 80097ae: 687b ldr r3, [r7, #4] 80097b0: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 80097b4: 7b7a ldrb r2, [r7, #13] 80097b6: 687b ldr r3, [r7, #4] 80097b8: 32ae adds r2, #174 @ 0xae 80097ba: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80097be: 689b ldr r3, [r3, #8] 80097c0: 2b00 cmp r3, #0 80097c2: d010 beq.n 80097e6 { ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 80097c4: 7b7a ldrb r2, [r7, #13] 80097c6: 687b ldr r3, [r7, #4] 80097c8: 32ae adds r2, #174 @ 0xae 80097ca: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80097ce: 689b ldr r3, [r3, #8] 80097d0: 6839 ldr r1, [r7, #0] 80097d2: 6878 ldr r0, [r7, #4] 80097d4: 4798 blx r3 80097d6: 4603 mov r3, r0 80097d8: 73fb strb r3, [r7, #15] } } } break; 80097da: e004 b.n 80097e6 default: USBD_CtlError(pdev, req); 80097dc: 6839 ldr r1, [r7, #0] 80097de: 6878 ldr r0, [r7, #4] 80097e0: f000 fc2f bl 800a042 break; 80097e4: e000 b.n 80097e8 break; 80097e6: bf00 nop } break; 80097e8: e0ad b.n 8009946 case USB_REQ_GET_STATUS: switch (pdev->dev_state) 80097ea: 687b ldr r3, [r7, #4] 80097ec: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80097f0: b2db uxtb r3, r3 80097f2: 2b02 cmp r3, #2 80097f4: d002 beq.n 80097fc 80097f6: 2b03 cmp r3, #3 80097f8: d033 beq.n 8009862 80097fa: e099 b.n 8009930 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80097fc: 7bbb ldrb r3, [r7, #14] 80097fe: 2b00 cmp r3, #0 8009800: d007 beq.n 8009812 8009802: 7bbb ldrb r3, [r7, #14] 8009804: 2b80 cmp r3, #128 @ 0x80 8009806: d004 beq.n 8009812 { USBD_CtlError(pdev, req); 8009808: 6839 ldr r1, [r7, #0] 800980a: 6878 ldr r0, [r7, #4] 800980c: f000 fc19 bl 800a042 break; 8009810: e093 b.n 800993a } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8009812: f997 300e ldrsb.w r3, [r7, #14] 8009816: 2b00 cmp r3, #0 8009818: da0b bge.n 8009832 800981a: 7bbb ldrb r3, [r7, #14] 800981c: f003 027f and.w r2, r3, #127 @ 0x7f 8009820: 4613 mov r3, r2 8009822: 009b lsls r3, r3, #2 8009824: 4413 add r3, r2 8009826: 009b lsls r3, r3, #2 8009828: 3310 adds r3, #16 800982a: 687a ldr r2, [r7, #4] 800982c: 4413 add r3, r2 800982e: 3304 adds r3, #4 8009830: e00b b.n 800984a &pdev->ep_out[ep_addr & 0x7FU]; 8009832: 7bbb ldrb r3, [r7, #14] 8009834: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8009838: 4613 mov r3, r2 800983a: 009b lsls r3, r3, #2 800983c: 4413 add r3, r2 800983e: 009b lsls r3, r3, #2 8009840: f503 73a8 add.w r3, r3, #336 @ 0x150 8009844: 687a ldr r2, [r7, #4] 8009846: 4413 add r3, r2 8009848: 3304 adds r3, #4 800984a: 60bb str r3, [r7, #8] pep->status = 0x0000U; 800984c: 68bb ldr r3, [r7, #8] 800984e: 2200 movs r2, #0 8009850: 739a strb r2, [r3, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 8009852: 68bb ldr r3, [r7, #8] 8009854: 330e adds r3, #14 8009856: 2202 movs r2, #2 8009858: 4619 mov r1, r3 800985a: 6878 ldr r0, [r7, #4] 800985c: f000 fc6e bl 800a13c break; 8009860: e06b b.n 800993a case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 8009862: f997 300e ldrsb.w r3, [r7, #14] 8009866: 2b00 cmp r3, #0 8009868: da11 bge.n 800988e { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 800986a: 7bbb ldrb r3, [r7, #14] 800986c: f003 020f and.w r2, r3, #15 8009870: 6879 ldr r1, [r7, #4] 8009872: 4613 mov r3, r2 8009874: 009b lsls r3, r3, #2 8009876: 4413 add r3, r2 8009878: 009b lsls r3, r3, #2 800987a: 440b add r3, r1 800987c: 3323 adds r3, #35 @ 0x23 800987e: 781b ldrb r3, [r3, #0] 8009880: 2b00 cmp r3, #0 8009882: d117 bne.n 80098b4 { USBD_CtlError(pdev, req); 8009884: 6839 ldr r1, [r7, #0] 8009886: 6878 ldr r0, [r7, #4] 8009888: f000 fbdb bl 800a042 break; 800988c: e055 b.n 800993a } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 800988e: 7bbb ldrb r3, [r7, #14] 8009890: f003 020f and.w r2, r3, #15 8009894: 6879 ldr r1, [r7, #4] 8009896: 4613 mov r3, r2 8009898: 009b lsls r3, r3, #2 800989a: 4413 add r3, r2 800989c: 009b lsls r3, r3, #2 800989e: 440b add r3, r1 80098a0: f203 1363 addw r3, r3, #355 @ 0x163 80098a4: 781b ldrb r3, [r3, #0] 80098a6: 2b00 cmp r3, #0 80098a8: d104 bne.n 80098b4 { USBD_CtlError(pdev, req); 80098aa: 6839 ldr r1, [r7, #0] 80098ac: 6878 ldr r0, [r7, #4] 80098ae: f000 fbc8 bl 800a042 break; 80098b2: e042 b.n 800993a } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80098b4: f997 300e ldrsb.w r3, [r7, #14] 80098b8: 2b00 cmp r3, #0 80098ba: da0b bge.n 80098d4 80098bc: 7bbb ldrb r3, [r7, #14] 80098be: f003 027f and.w r2, r3, #127 @ 0x7f 80098c2: 4613 mov r3, r2 80098c4: 009b lsls r3, r3, #2 80098c6: 4413 add r3, r2 80098c8: 009b lsls r3, r3, #2 80098ca: 3310 adds r3, #16 80098cc: 687a ldr r2, [r7, #4] 80098ce: 4413 add r3, r2 80098d0: 3304 adds r3, #4 80098d2: e00b b.n 80098ec &pdev->ep_out[ep_addr & 0x7FU]; 80098d4: 7bbb ldrb r3, [r7, #14] 80098d6: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80098da: 4613 mov r3, r2 80098dc: 009b lsls r3, r3, #2 80098de: 4413 add r3, r2 80098e0: 009b lsls r3, r3, #2 80098e2: f503 73a8 add.w r3, r3, #336 @ 0x150 80098e6: 687a ldr r2, [r7, #4] 80098e8: 4413 add r3, r2 80098ea: 3304 adds r3, #4 80098ec: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 80098ee: 7bbb ldrb r3, [r7, #14] 80098f0: 2b00 cmp r3, #0 80098f2: d002 beq.n 80098fa 80098f4: 7bbb ldrb r3, [r7, #14] 80098f6: 2b80 cmp r3, #128 @ 0x80 80098f8: d103 bne.n 8009902 { pep->status = 0x0000U; 80098fa: 68bb ldr r3, [r7, #8] 80098fc: 2200 movs r2, #0 80098fe: 739a strb r2, [r3, #14] 8009900: e00e b.n 8009920 } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 8009902: 7bbb ldrb r3, [r7, #14] 8009904: 4619 mov r1, r3 8009906: 6878 ldr r0, [r7, #4] 8009908: f001 f80c bl 800a924 800990c: 4603 mov r3, r0 800990e: 2b00 cmp r3, #0 8009910: d003 beq.n 800991a { pep->status = 0x0001U; 8009912: 68bb ldr r3, [r7, #8] 8009914: 2201 movs r2, #1 8009916: 739a strb r2, [r3, #14] 8009918: e002 b.n 8009920 } else { pep->status = 0x0000U; 800991a: 68bb ldr r3, [r7, #8] 800991c: 2200 movs r2, #0 800991e: 739a strb r2, [r3, #14] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 8009920: 68bb ldr r3, [r7, #8] 8009922: 330e adds r3, #14 8009924: 2202 movs r2, #2 8009926: 4619 mov r1, r3 8009928: 6878 ldr r0, [r7, #4] 800992a: f000 fc07 bl 800a13c break; 800992e: e004 b.n 800993a default: USBD_CtlError(pdev, req); 8009930: 6839 ldr r1, [r7, #0] 8009932: 6878 ldr r0, [r7, #4] 8009934: f000 fb85 bl 800a042 break; 8009938: bf00 nop } break; 800993a: e004 b.n 8009946 default: USBD_CtlError(pdev, req); 800993c: 6839 ldr r1, [r7, #0] 800993e: 6878 ldr r0, [r7, #4] 8009940: f000 fb7f bl 800a042 break; 8009944: bf00 nop } break; 8009946: e005 b.n 8009954 default: USBD_CtlError(pdev, req); 8009948: 6839 ldr r1, [r7, #0] 800994a: 6878 ldr r0, [r7, #4] 800994c: f000 fb79 bl 800a042 break; 8009950: e000 b.n 8009954 break; 8009952: bf00 nop } return ret; 8009954: 7bfb ldrb r3, [r7, #15] } 8009956: 4618 mov r0, r3 8009958: 3710 adds r7, #16 800995a: 46bd mov sp, r7 800995c: bd80 pop {r7, pc} ... 08009960 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009960: b580 push {r7, lr} 8009962: b084 sub sp, #16 8009964: af00 add r7, sp, #0 8009966: 6078 str r0, [r7, #4] 8009968: 6039 str r1, [r7, #0] uint16_t len = 0U; 800996a: 2300 movs r3, #0 800996c: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 800996e: 2300 movs r3, #0 8009970: 60fb str r3, [r7, #12] uint8_t err = 0U; 8009972: 2300 movs r3, #0 8009974: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 8009976: 683b ldr r3, [r7, #0] 8009978: 885b ldrh r3, [r3, #2] 800997a: 0a1b lsrs r3, r3, #8 800997c: b29b uxth r3, r3 800997e: 3b01 subs r3, #1 8009980: 2b0e cmp r3, #14 8009982: f200 8152 bhi.w 8009c2a 8009986: a201 add r2, pc, #4 @ (adr r2, 800998c ) 8009988: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800998c: 080099fd .word 0x080099fd 8009990: 08009a15 .word 0x08009a15 8009994: 08009a55 .word 0x08009a55 8009998: 08009c2b .word 0x08009c2b 800999c: 08009c2b .word 0x08009c2b 80099a0: 08009bcb .word 0x08009bcb 80099a4: 08009bf7 .word 0x08009bf7 80099a8: 08009c2b .word 0x08009c2b 80099ac: 08009c2b .word 0x08009c2b 80099b0: 08009c2b .word 0x08009c2b 80099b4: 08009c2b .word 0x08009c2b 80099b8: 08009c2b .word 0x08009c2b 80099bc: 08009c2b .word 0x08009c2b 80099c0: 08009c2b .word 0x08009c2b 80099c4: 080099c9 .word 0x080099c9 { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) 80099c8: 687b ldr r3, [r7, #4] 80099ca: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80099ce: 69db ldr r3, [r3, #28] 80099d0: 2b00 cmp r3, #0 80099d2: d00b beq.n 80099ec { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); 80099d4: 687b ldr r3, [r7, #4] 80099d6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80099da: 69db ldr r3, [r3, #28] 80099dc: 687a ldr r2, [r7, #4] 80099de: 7c12 ldrb r2, [r2, #16] 80099e0: f107 0108 add.w r1, r7, #8 80099e4: 4610 mov r0, r2 80099e6: 4798 blx r3 80099e8: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80099ea: e126 b.n 8009c3a USBD_CtlError(pdev, req); 80099ec: 6839 ldr r1, [r7, #0] 80099ee: 6878 ldr r0, [r7, #4] 80099f0: f000 fb27 bl 800a042 err++; 80099f4: 7afb ldrb r3, [r7, #11] 80099f6: 3301 adds r3, #1 80099f8: 72fb strb r3, [r7, #11] break; 80099fa: e11e b.n 8009c3a #endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 80099fc: 687b ldr r3, [r7, #4] 80099fe: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a02: 681b ldr r3, [r3, #0] 8009a04: 687a ldr r2, [r7, #4] 8009a06: 7c12 ldrb r2, [r2, #16] 8009a08: f107 0108 add.w r1, r7, #8 8009a0c: 4610 mov r0, r2 8009a0e: 4798 blx r3 8009a10: 60f8 str r0, [r7, #12] break; 8009a12: e112 b.n 8009c3a case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8009a14: 687b ldr r3, [r7, #4] 8009a16: 7c1b ldrb r3, [r3, #16] 8009a18: 2b00 cmp r3, #0 8009a1a: d10d bne.n 8009a38 pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); 8009a1c: 687b ldr r3, [r7, #4] 8009a1e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009a22: 6a9b ldr r3, [r3, #40] @ 0x28 8009a24: f107 0208 add.w r2, r7, #8 8009a28: 4610 mov r0, r2 8009a2a: 4798 blx r3 8009a2c: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 8009a2e: 68fb ldr r3, [r7, #12] 8009a30: 3301 adds r3, #1 8009a32: 2202 movs r2, #2 8009a34: 701a strb r2, [r3, #0] { pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 8009a36: e100 b.n 8009c3a pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); 8009a38: 687b ldr r3, [r7, #4] 8009a3a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009a3e: 6adb ldr r3, [r3, #44] @ 0x2c 8009a40: f107 0208 add.w r2, r7, #8 8009a44: 4610 mov r0, r2 8009a46: 4798 blx r3 8009a48: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 8009a4a: 68fb ldr r3, [r7, #12] 8009a4c: 3301 adds r3, #1 8009a4e: 2202 movs r2, #2 8009a50: 701a strb r2, [r3, #0] break; 8009a52: e0f2 b.n 8009c3a case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 8009a54: 683b ldr r3, [r7, #0] 8009a56: 885b ldrh r3, [r3, #2] 8009a58: b2db uxtb r3, r3 8009a5a: 2b05 cmp r3, #5 8009a5c: f200 80ac bhi.w 8009bb8 8009a60: a201 add r2, pc, #4 @ (adr r2, 8009a68 ) 8009a62: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009a66: bf00 nop 8009a68: 08009a81 .word 0x08009a81 8009a6c: 08009ab5 .word 0x08009ab5 8009a70: 08009ae9 .word 0x08009ae9 8009a74: 08009b1d .word 0x08009b1d 8009a78: 08009b51 .word 0x08009b51 8009a7c: 08009b85 .word 0x08009b85 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 8009a80: 687b ldr r3, [r7, #4] 8009a82: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a86: 685b ldr r3, [r3, #4] 8009a88: 2b00 cmp r3, #0 8009a8a: d00b beq.n 8009aa4 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 8009a8c: 687b ldr r3, [r7, #4] 8009a8e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009a92: 685b ldr r3, [r3, #4] 8009a94: 687a ldr r2, [r7, #4] 8009a96: 7c12 ldrb r2, [r2, #16] 8009a98: f107 0108 add.w r1, r7, #8 8009a9c: 4610 mov r0, r2 8009a9e: 4798 blx r3 8009aa0: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009aa2: e091 b.n 8009bc8 USBD_CtlError(pdev, req); 8009aa4: 6839 ldr r1, [r7, #0] 8009aa6: 6878 ldr r0, [r7, #4] 8009aa8: f000 facb bl 800a042 err++; 8009aac: 7afb ldrb r3, [r7, #11] 8009aae: 3301 adds r3, #1 8009ab0: 72fb strb r3, [r7, #11] break; 8009ab2: e089 b.n 8009bc8 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 8009ab4: 687b ldr r3, [r7, #4] 8009ab6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009aba: 689b ldr r3, [r3, #8] 8009abc: 2b00 cmp r3, #0 8009abe: d00b beq.n 8009ad8 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 8009ac0: 687b ldr r3, [r7, #4] 8009ac2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009ac6: 689b ldr r3, [r3, #8] 8009ac8: 687a ldr r2, [r7, #4] 8009aca: 7c12 ldrb r2, [r2, #16] 8009acc: f107 0108 add.w r1, r7, #8 8009ad0: 4610 mov r0, r2 8009ad2: 4798 blx r3 8009ad4: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009ad6: e077 b.n 8009bc8 USBD_CtlError(pdev, req); 8009ad8: 6839 ldr r1, [r7, #0] 8009ada: 6878 ldr r0, [r7, #4] 8009adc: f000 fab1 bl 800a042 err++; 8009ae0: 7afb ldrb r3, [r7, #11] 8009ae2: 3301 adds r3, #1 8009ae4: 72fb strb r3, [r7, #11] break; 8009ae6: e06f b.n 8009bc8 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 8009ae8: 687b ldr r3, [r7, #4] 8009aea: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009aee: 68db ldr r3, [r3, #12] 8009af0: 2b00 cmp r3, #0 8009af2: d00b beq.n 8009b0c { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 8009af4: 687b ldr r3, [r7, #4] 8009af6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009afa: 68db ldr r3, [r3, #12] 8009afc: 687a ldr r2, [r7, #4] 8009afe: 7c12 ldrb r2, [r2, #16] 8009b00: f107 0108 add.w r1, r7, #8 8009b04: 4610 mov r0, r2 8009b06: 4798 blx r3 8009b08: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009b0a: e05d b.n 8009bc8 USBD_CtlError(pdev, req); 8009b0c: 6839 ldr r1, [r7, #0] 8009b0e: 6878 ldr r0, [r7, #4] 8009b10: f000 fa97 bl 800a042 err++; 8009b14: 7afb ldrb r3, [r7, #11] 8009b16: 3301 adds r3, #1 8009b18: 72fb strb r3, [r7, #11] break; 8009b1a: e055 b.n 8009bc8 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 8009b1c: 687b ldr r3, [r7, #4] 8009b1e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009b22: 691b ldr r3, [r3, #16] 8009b24: 2b00 cmp r3, #0 8009b26: d00b beq.n 8009b40 { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 8009b28: 687b ldr r3, [r7, #4] 8009b2a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009b2e: 691b ldr r3, [r3, #16] 8009b30: 687a ldr r2, [r7, #4] 8009b32: 7c12 ldrb r2, [r2, #16] 8009b34: f107 0108 add.w r1, r7, #8 8009b38: 4610 mov r0, r2 8009b3a: 4798 blx r3 8009b3c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009b3e: e043 b.n 8009bc8 USBD_CtlError(pdev, req); 8009b40: 6839 ldr r1, [r7, #0] 8009b42: 6878 ldr r0, [r7, #4] 8009b44: f000 fa7d bl 800a042 err++; 8009b48: 7afb ldrb r3, [r7, #11] 8009b4a: 3301 adds r3, #1 8009b4c: 72fb strb r3, [r7, #11] break; 8009b4e: e03b b.n 8009bc8 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 8009b50: 687b ldr r3, [r7, #4] 8009b52: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009b56: 695b ldr r3, [r3, #20] 8009b58: 2b00 cmp r3, #0 8009b5a: d00b beq.n 8009b74 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 8009b5c: 687b ldr r3, [r7, #4] 8009b5e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009b62: 695b ldr r3, [r3, #20] 8009b64: 687a ldr r2, [r7, #4] 8009b66: 7c12 ldrb r2, [r2, #16] 8009b68: f107 0108 add.w r1, r7, #8 8009b6c: 4610 mov r0, r2 8009b6e: 4798 blx r3 8009b70: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009b72: e029 b.n 8009bc8 USBD_CtlError(pdev, req); 8009b74: 6839 ldr r1, [r7, #0] 8009b76: 6878 ldr r0, [r7, #4] 8009b78: f000 fa63 bl 800a042 err++; 8009b7c: 7afb ldrb r3, [r7, #11] 8009b7e: 3301 adds r3, #1 8009b80: 72fb strb r3, [r7, #11] break; 8009b82: e021 b.n 8009bc8 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 8009b84: 687b ldr r3, [r7, #4] 8009b86: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009b8a: 699b ldr r3, [r3, #24] 8009b8c: 2b00 cmp r3, #0 8009b8e: d00b beq.n 8009ba8 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 8009b90: 687b ldr r3, [r7, #4] 8009b92: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8009b96: 699b ldr r3, [r3, #24] 8009b98: 687a ldr r2, [r7, #4] 8009b9a: 7c12 ldrb r2, [r2, #16] 8009b9c: f107 0108 add.w r1, r7, #8 8009ba0: 4610 mov r0, r2 8009ba2: 4798 blx r3 8009ba4: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009ba6: e00f b.n 8009bc8 USBD_CtlError(pdev, req); 8009ba8: 6839 ldr r1, [r7, #0] 8009baa: 6878 ldr r0, [r7, #4] 8009bac: f000 fa49 bl 800a042 err++; 8009bb0: 7afb ldrb r3, [r7, #11] 8009bb2: 3301 adds r3, #1 8009bb4: 72fb strb r3, [r7, #11] break; 8009bb6: e007 b.n 8009bc8 err++; } #endif /* USBD_SUPPORT_USER_STRING_DESC */ #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 8009bb8: 6839 ldr r1, [r7, #0] 8009bba: 6878 ldr r0, [r7, #4] 8009bbc: f000 fa41 bl 800a042 err++; 8009bc0: 7afb ldrb r3, [r7, #11] 8009bc2: 3301 adds r3, #1 8009bc4: 72fb strb r3, [r7, #11] #endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ break; 8009bc6: bf00 nop } break; 8009bc8: e037 b.n 8009c3a case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 8009bca: 687b ldr r3, [r7, #4] 8009bcc: 7c1b ldrb r3, [r3, #16] 8009bce: 2b00 cmp r3, #0 8009bd0: d109 bne.n 8009be6 pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); 8009bd2: 687b ldr r3, [r7, #4] 8009bd4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009bd8: 6b5b ldr r3, [r3, #52] @ 0x34 8009bda: f107 0208 add.w r2, r7, #8 8009bde: 4610 mov r0, r2 8009be0: 4798 blx r3 8009be2: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8009be4: e029 b.n 8009c3a USBD_CtlError(pdev, req); 8009be6: 6839 ldr r1, [r7, #0] 8009be8: 6878 ldr r0, [r7, #4] 8009bea: f000 fa2a bl 800a042 err++; 8009bee: 7afb ldrb r3, [r7, #11] 8009bf0: 3301 adds r3, #1 8009bf2: 72fb strb r3, [r7, #11] break; 8009bf4: e021 b.n 8009c3a case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8009bf6: 687b ldr r3, [r7, #4] 8009bf8: 7c1b ldrb r3, [r3, #16] 8009bfa: 2b00 cmp r3, #0 8009bfc: d10d bne.n 8009c1a pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); 8009bfe: 687b ldr r3, [r7, #4] 8009c00: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009c04: 6b1b ldr r3, [r3, #48] @ 0x30 8009c06: f107 0208 add.w r2, r7, #8 8009c0a: 4610 mov r0, r2 8009c0c: 4798 blx r3 8009c0e: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 8009c10: 68fb ldr r3, [r7, #12] 8009c12: 3301 adds r3, #1 8009c14: 2207 movs r2, #7 8009c16: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 8009c18: e00f b.n 8009c3a USBD_CtlError(pdev, req); 8009c1a: 6839 ldr r1, [r7, #0] 8009c1c: 6878 ldr r0, [r7, #4] 8009c1e: f000 fa10 bl 800a042 err++; 8009c22: 7afb ldrb r3, [r7, #11] 8009c24: 3301 adds r3, #1 8009c26: 72fb strb r3, [r7, #11] break; 8009c28: e007 b.n 8009c3a default: USBD_CtlError(pdev, req); 8009c2a: 6839 ldr r1, [r7, #0] 8009c2c: 6878 ldr r0, [r7, #4] 8009c2e: f000 fa08 bl 800a042 err++; 8009c32: 7afb ldrb r3, [r7, #11] 8009c34: 3301 adds r3, #1 8009c36: 72fb strb r3, [r7, #11] break; 8009c38: bf00 nop } if (err != 0U) 8009c3a: 7afb ldrb r3, [r7, #11] 8009c3c: 2b00 cmp r3, #0 8009c3e: d11e bne.n 8009c7e { return; } if (req->wLength != 0U) 8009c40: 683b ldr r3, [r7, #0] 8009c42: 88db ldrh r3, [r3, #6] 8009c44: 2b00 cmp r3, #0 8009c46: d016 beq.n 8009c76 { if (len != 0U) 8009c48: 893b ldrh r3, [r7, #8] 8009c4a: 2b00 cmp r3, #0 8009c4c: d00e beq.n 8009c6c { len = MIN(len, req->wLength); 8009c4e: 683b ldr r3, [r7, #0] 8009c50: 88da ldrh r2, [r3, #6] 8009c52: 893b ldrh r3, [r7, #8] 8009c54: 4293 cmp r3, r2 8009c56: bf28 it cs 8009c58: 4613 movcs r3, r2 8009c5a: b29b uxth r3, r3 8009c5c: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 8009c5e: 893b ldrh r3, [r7, #8] 8009c60: 461a mov r2, r3 8009c62: 68f9 ldr r1, [r7, #12] 8009c64: 6878 ldr r0, [r7, #4] 8009c66: f000 fa69 bl 800a13c 8009c6a: e009 b.n 8009c80 } else { USBD_CtlError(pdev, req); 8009c6c: 6839 ldr r1, [r7, #0] 8009c6e: 6878 ldr r0, [r7, #4] 8009c70: f000 f9e7 bl 800a042 8009c74: e004 b.n 8009c80 } } else { (void)USBD_CtlSendStatus(pdev); 8009c76: 6878 ldr r0, [r7, #4] 8009c78: f000 faa0 bl 800a1bc 8009c7c: e000 b.n 8009c80 return; 8009c7e: bf00 nop } } 8009c80: 3710 adds r7, #16 8009c82: 46bd mov sp, r7 8009c84: bd80 pop {r7, pc} 8009c86: bf00 nop 08009c88 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009c88: b580 push {r7, lr} 8009c8a: b084 sub sp, #16 8009c8c: af00 add r7, sp, #0 8009c8e: 6078 str r0, [r7, #4] 8009c90: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 8009c92: 683b ldr r3, [r7, #0] 8009c94: 889b ldrh r3, [r3, #4] 8009c96: 2b00 cmp r3, #0 8009c98: d131 bne.n 8009cfe 8009c9a: 683b ldr r3, [r7, #0] 8009c9c: 88db ldrh r3, [r3, #6] 8009c9e: 2b00 cmp r3, #0 8009ca0: d12d bne.n 8009cfe 8009ca2: 683b ldr r3, [r7, #0] 8009ca4: 885b ldrh r3, [r3, #2] 8009ca6: 2b7f cmp r3, #127 @ 0x7f 8009ca8: d829 bhi.n 8009cfe { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 8009caa: 683b ldr r3, [r7, #0] 8009cac: 885b ldrh r3, [r3, #2] 8009cae: b2db uxtb r3, r3 8009cb0: f003 037f and.w r3, r3, #127 @ 0x7f 8009cb4: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009cb6: 687b ldr r3, [r7, #4] 8009cb8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009cbc: b2db uxtb r3, r3 8009cbe: 2b03 cmp r3, #3 8009cc0: d104 bne.n 8009ccc { USBD_CtlError(pdev, req); 8009cc2: 6839 ldr r1, [r7, #0] 8009cc4: 6878 ldr r0, [r7, #4] 8009cc6: f000 f9bc bl 800a042 if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009cca: e01d b.n 8009d08 } else { pdev->dev_address = dev_addr; 8009ccc: 687b ldr r3, [r7, #4] 8009cce: 7bfa ldrb r2, [r7, #15] 8009cd0: f883 229e strb.w r2, [r3, #670] @ 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 8009cd4: 7bfb ldrb r3, [r7, #15] 8009cd6: 4619 mov r1, r3 8009cd8: 6878 ldr r0, [r7, #4] 8009cda: f000 fe4f bl 800a97c (void)USBD_CtlSendStatus(pdev); 8009cde: 6878 ldr r0, [r7, #4] 8009ce0: f000 fa6c bl 800a1bc if (dev_addr != 0U) 8009ce4: 7bfb ldrb r3, [r7, #15] 8009ce6: 2b00 cmp r3, #0 8009ce8: d004 beq.n 8009cf4 { pdev->dev_state = USBD_STATE_ADDRESSED; 8009cea: 687b ldr r3, [r7, #4] 8009cec: 2202 movs r2, #2 8009cee: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009cf2: e009 b.n 8009d08 } else { pdev->dev_state = USBD_STATE_DEFAULT; 8009cf4: 687b ldr r3, [r7, #4] 8009cf6: 2201 movs r2, #1 8009cf8: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009cfc: e004 b.n 8009d08 } } } else { USBD_CtlError(pdev, req); 8009cfe: 6839 ldr r1, [r7, #0] 8009d00: 6878 ldr r0, [r7, #4] 8009d02: f000 f99e bl 800a042 } } 8009d06: bf00 nop 8009d08: bf00 nop 8009d0a: 3710 adds r7, #16 8009d0c: 46bd mov sp, r7 8009d0e: bd80 pop {r7, pc} 08009d10 : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009d10: b580 push {r7, lr} 8009d12: b084 sub sp, #16 8009d14: af00 add r7, sp, #0 8009d16: 6078 str r0, [r7, #4] 8009d18: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8009d1a: 2300 movs r3, #0 8009d1c: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 8009d1e: 683b ldr r3, [r7, #0] 8009d20: 885b ldrh r3, [r3, #2] 8009d22: b2da uxtb r2, r3 8009d24: 4b4e ldr r3, [pc, #312] @ (8009e60 ) 8009d26: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 8009d28: 4b4d ldr r3, [pc, #308] @ (8009e60 ) 8009d2a: 781b ldrb r3, [r3, #0] 8009d2c: 2b01 cmp r3, #1 8009d2e: d905 bls.n 8009d3c { USBD_CtlError(pdev, req); 8009d30: 6839 ldr r1, [r7, #0] 8009d32: 6878 ldr r0, [r7, #4] 8009d34: f000 f985 bl 800a042 return USBD_FAIL; 8009d38: 2303 movs r3, #3 8009d3a: e08c b.n 8009e56 } switch (pdev->dev_state) 8009d3c: 687b ldr r3, [r7, #4] 8009d3e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009d42: b2db uxtb r3, r3 8009d44: 2b02 cmp r3, #2 8009d46: d002 beq.n 8009d4e 8009d48: 2b03 cmp r3, #3 8009d4a: d029 beq.n 8009da0 8009d4c: e075 b.n 8009e3a { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 8009d4e: 4b44 ldr r3, [pc, #272] @ (8009e60 ) 8009d50: 781b ldrb r3, [r3, #0] 8009d52: 2b00 cmp r3, #0 8009d54: d020 beq.n 8009d98 { pdev->dev_config = cfgidx; 8009d56: 4b42 ldr r3, [pc, #264] @ (8009e60 ) 8009d58: 781b ldrb r3, [r3, #0] 8009d5a: 461a mov r2, r3 8009d5c: 687b ldr r3, [r7, #4] 8009d5e: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8009d60: 4b3f ldr r3, [pc, #252] @ (8009e60 ) 8009d62: 781b ldrb r3, [r3, #0] 8009d64: 4619 mov r1, r3 8009d66: 6878 ldr r0, [r7, #4] 8009d68: f7fe ffa3 bl 8008cb2 8009d6c: 4603 mov r3, r0 8009d6e: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8009d70: 7bfb ldrb r3, [r7, #15] 8009d72: 2b00 cmp r3, #0 8009d74: d008 beq.n 8009d88 { USBD_CtlError(pdev, req); 8009d76: 6839 ldr r1, [r7, #0] 8009d78: 6878 ldr r0, [r7, #4] 8009d7a: f000 f962 bl 800a042 pdev->dev_state = USBD_STATE_ADDRESSED; 8009d7e: 687b ldr r3, [r7, #4] 8009d80: 2202 movs r2, #2 8009d82: f883 229c strb.w r2, [r3, #668] @ 0x29c } else { (void)USBD_CtlSendStatus(pdev); } break; 8009d86: e065 b.n 8009e54 (void)USBD_CtlSendStatus(pdev); 8009d88: 6878 ldr r0, [r7, #4] 8009d8a: f000 fa17 bl 800a1bc pdev->dev_state = USBD_STATE_CONFIGURED; 8009d8e: 687b ldr r3, [r7, #4] 8009d90: 2203 movs r2, #3 8009d92: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8009d96: e05d b.n 8009e54 (void)USBD_CtlSendStatus(pdev); 8009d98: 6878 ldr r0, [r7, #4] 8009d9a: f000 fa0f bl 800a1bc break; 8009d9e: e059 b.n 8009e54 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 8009da0: 4b2f ldr r3, [pc, #188] @ (8009e60 ) 8009da2: 781b ldrb r3, [r3, #0] 8009da4: 2b00 cmp r3, #0 8009da6: d112 bne.n 8009dce { pdev->dev_state = USBD_STATE_ADDRESSED; 8009da8: 687b ldr r3, [r7, #4] 8009daa: 2202 movs r2, #2 8009dac: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->dev_config = cfgidx; 8009db0: 4b2b ldr r3, [pc, #172] @ (8009e60 ) 8009db2: 781b ldrb r3, [r3, #0] 8009db4: 461a mov r2, r3 8009db6: 687b ldr r3, [r7, #4] 8009db8: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 8009dba: 4b29 ldr r3, [pc, #164] @ (8009e60 ) 8009dbc: 781b ldrb r3, [r3, #0] 8009dbe: 4619 mov r1, r3 8009dc0: 6878 ldr r0, [r7, #4] 8009dc2: f7fe ff92 bl 8008cea (void)USBD_CtlSendStatus(pdev); 8009dc6: 6878 ldr r0, [r7, #4] 8009dc8: f000 f9f8 bl 800a1bc } else { (void)USBD_CtlSendStatus(pdev); } break; 8009dcc: e042 b.n 8009e54 else if (cfgidx != pdev->dev_config) 8009dce: 4b24 ldr r3, [pc, #144] @ (8009e60 ) 8009dd0: 781b ldrb r3, [r3, #0] 8009dd2: 461a mov r2, r3 8009dd4: 687b ldr r3, [r7, #4] 8009dd6: 685b ldr r3, [r3, #4] 8009dd8: 429a cmp r2, r3 8009dda: d02a beq.n 8009e32 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8009ddc: 687b ldr r3, [r7, #4] 8009dde: 685b ldr r3, [r3, #4] 8009de0: b2db uxtb r3, r3 8009de2: 4619 mov r1, r3 8009de4: 6878 ldr r0, [r7, #4] 8009de6: f7fe ff80 bl 8008cea pdev->dev_config = cfgidx; 8009dea: 4b1d ldr r3, [pc, #116] @ (8009e60 ) 8009dec: 781b ldrb r3, [r3, #0] 8009dee: 461a mov r2, r3 8009df0: 687b ldr r3, [r7, #4] 8009df2: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8009df4: 4b1a ldr r3, [pc, #104] @ (8009e60 ) 8009df6: 781b ldrb r3, [r3, #0] 8009df8: 4619 mov r1, r3 8009dfa: 6878 ldr r0, [r7, #4] 8009dfc: f7fe ff59 bl 8008cb2 8009e00: 4603 mov r3, r0 8009e02: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8009e04: 7bfb ldrb r3, [r7, #15] 8009e06: 2b00 cmp r3, #0 8009e08: d00f beq.n 8009e2a USBD_CtlError(pdev, req); 8009e0a: 6839 ldr r1, [r7, #0] 8009e0c: 6878 ldr r0, [r7, #4] 8009e0e: f000 f918 bl 800a042 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8009e12: 687b ldr r3, [r7, #4] 8009e14: 685b ldr r3, [r3, #4] 8009e16: b2db uxtb r3, r3 8009e18: 4619 mov r1, r3 8009e1a: 6878 ldr r0, [r7, #4] 8009e1c: f7fe ff65 bl 8008cea pdev->dev_state = USBD_STATE_ADDRESSED; 8009e20: 687b ldr r3, [r7, #4] 8009e22: 2202 movs r2, #2 8009e24: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8009e28: e014 b.n 8009e54 (void)USBD_CtlSendStatus(pdev); 8009e2a: 6878 ldr r0, [r7, #4] 8009e2c: f000 f9c6 bl 800a1bc break; 8009e30: e010 b.n 8009e54 (void)USBD_CtlSendStatus(pdev); 8009e32: 6878 ldr r0, [r7, #4] 8009e34: f000 f9c2 bl 800a1bc break; 8009e38: e00c b.n 8009e54 default: USBD_CtlError(pdev, req); 8009e3a: 6839 ldr r1, [r7, #0] 8009e3c: 6878 ldr r0, [r7, #4] 8009e3e: f000 f900 bl 800a042 (void)USBD_ClrClassConfig(pdev, cfgidx); 8009e42: 4b07 ldr r3, [pc, #28] @ (8009e60 ) 8009e44: 781b ldrb r3, [r3, #0] 8009e46: 4619 mov r1, r3 8009e48: 6878 ldr r0, [r7, #4] 8009e4a: f7fe ff4e bl 8008cea ret = USBD_FAIL; 8009e4e: 2303 movs r3, #3 8009e50: 73fb strb r3, [r7, #15] break; 8009e52: bf00 nop } return ret; 8009e54: 7bfb ldrb r3, [r7, #15] } 8009e56: 4618 mov r0, r3 8009e58: 3710 adds r7, #16 8009e5a: 46bd mov sp, r7 8009e5c: bd80 pop {r7, pc} 8009e5e: bf00 nop 8009e60: 20000720 .word 0x20000720 08009e64 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009e64: b580 push {r7, lr} 8009e66: b082 sub sp, #8 8009e68: af00 add r7, sp, #0 8009e6a: 6078 str r0, [r7, #4] 8009e6c: 6039 str r1, [r7, #0] if (req->wLength != 1U) 8009e6e: 683b ldr r3, [r7, #0] 8009e70: 88db ldrh r3, [r3, #6] 8009e72: 2b01 cmp r3, #1 8009e74: d004 beq.n 8009e80 { USBD_CtlError(pdev, req); 8009e76: 6839 ldr r1, [r7, #0] 8009e78: 6878 ldr r0, [r7, #4] 8009e7a: f000 f8e2 bl 800a042 default: USBD_CtlError(pdev, req); break; } } } 8009e7e: e023 b.n 8009ec8 switch (pdev->dev_state) 8009e80: 687b ldr r3, [r7, #4] 8009e82: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009e86: b2db uxtb r3, r3 8009e88: 2b02 cmp r3, #2 8009e8a: dc02 bgt.n 8009e92 8009e8c: 2b00 cmp r3, #0 8009e8e: dc03 bgt.n 8009e98 8009e90: e015 b.n 8009ebe 8009e92: 2b03 cmp r3, #3 8009e94: d00b beq.n 8009eae 8009e96: e012 b.n 8009ebe pdev->dev_default_config = 0U; 8009e98: 687b ldr r3, [r7, #4] 8009e9a: 2200 movs r2, #0 8009e9c: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 8009e9e: 687b ldr r3, [r7, #4] 8009ea0: 3308 adds r3, #8 8009ea2: 2201 movs r2, #1 8009ea4: 4619 mov r1, r3 8009ea6: 6878 ldr r0, [r7, #4] 8009ea8: f000 f948 bl 800a13c break; 8009eac: e00c b.n 8009ec8 (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 8009eae: 687b ldr r3, [r7, #4] 8009eb0: 3304 adds r3, #4 8009eb2: 2201 movs r2, #1 8009eb4: 4619 mov r1, r3 8009eb6: 6878 ldr r0, [r7, #4] 8009eb8: f000 f940 bl 800a13c break; 8009ebc: e004 b.n 8009ec8 USBD_CtlError(pdev, req); 8009ebe: 6839 ldr r1, [r7, #0] 8009ec0: 6878 ldr r0, [r7, #4] 8009ec2: f000 f8be bl 800a042 break; 8009ec6: bf00 nop } 8009ec8: bf00 nop 8009eca: 3708 adds r7, #8 8009ecc: 46bd mov sp, r7 8009ece: bd80 pop {r7, pc} 08009ed0 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009ed0: b580 push {r7, lr} 8009ed2: b082 sub sp, #8 8009ed4: af00 add r7, sp, #0 8009ed6: 6078 str r0, [r7, #4] 8009ed8: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8009eda: 687b ldr r3, [r7, #4] 8009edc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009ee0: b2db uxtb r3, r3 8009ee2: 3b01 subs r3, #1 8009ee4: 2b02 cmp r3, #2 8009ee6: d81e bhi.n 8009f26 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 8009ee8: 683b ldr r3, [r7, #0] 8009eea: 88db ldrh r3, [r3, #6] 8009eec: 2b02 cmp r3, #2 8009eee: d004 beq.n 8009efa { USBD_CtlError(pdev, req); 8009ef0: 6839 ldr r1, [r7, #0] 8009ef2: 6878 ldr r0, [r7, #4] 8009ef4: f000 f8a5 bl 800a042 break; 8009ef8: e01a b.n 8009f30 } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 8009efa: 687b ldr r3, [r7, #4] 8009efc: 2201 movs r2, #1 8009efe: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif /* USBD_SELF_POWERED */ if (pdev->dev_remote_wakeup != 0U) 8009f00: 687b ldr r3, [r7, #4] 8009f02: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 8009f06: 2b00 cmp r3, #0 8009f08: d005 beq.n 8009f16 { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 8009f0a: 687b ldr r3, [r7, #4] 8009f0c: 68db ldr r3, [r3, #12] 8009f0e: f043 0202 orr.w r2, r3, #2 8009f12: 687b ldr r3, [r7, #4] 8009f14: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 8009f16: 687b ldr r3, [r7, #4] 8009f18: 330c adds r3, #12 8009f1a: 2202 movs r2, #2 8009f1c: 4619 mov r1, r3 8009f1e: 6878 ldr r0, [r7, #4] 8009f20: f000 f90c bl 800a13c break; 8009f24: e004 b.n 8009f30 default: USBD_CtlError(pdev, req); 8009f26: 6839 ldr r1, [r7, #0] 8009f28: 6878 ldr r0, [r7, #4] 8009f2a: f000 f88a bl 800a042 break; 8009f2e: bf00 nop } } 8009f30: bf00 nop 8009f32: 3708 adds r7, #8 8009f34: 46bd mov sp, r7 8009f36: bd80 pop {r7, pc} 08009f38 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009f38: b580 push {r7, lr} 8009f3a: b082 sub sp, #8 8009f3c: af00 add r7, sp, #0 8009f3e: 6078 str r0, [r7, #4] 8009f40: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8009f42: 683b ldr r3, [r7, #0] 8009f44: 885b ldrh r3, [r3, #2] 8009f46: 2b01 cmp r3, #1 8009f48: d107 bne.n 8009f5a { pdev->dev_remote_wakeup = 1U; 8009f4a: 687b ldr r3, [r7, #4] 8009f4c: 2201 movs r2, #1 8009f4e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8009f52: 6878 ldr r0, [r7, #4] 8009f54: f000 f932 bl 800a1bc } else { USBD_CtlError(pdev, req); } } 8009f58: e013 b.n 8009f82 else if (req->wValue == USB_FEATURE_TEST_MODE) 8009f5a: 683b ldr r3, [r7, #0] 8009f5c: 885b ldrh r3, [r3, #2] 8009f5e: 2b02 cmp r3, #2 8009f60: d10b bne.n 8009f7a pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); 8009f62: 683b ldr r3, [r7, #0] 8009f64: 889b ldrh r3, [r3, #4] 8009f66: 0a1b lsrs r3, r3, #8 8009f68: b29b uxth r3, r3 8009f6a: b2da uxtb r2, r3 8009f6c: 687b ldr r3, [r7, #4] 8009f6e: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 (void)USBD_CtlSendStatus(pdev); 8009f72: 6878 ldr r0, [r7, #4] 8009f74: f000 f922 bl 800a1bc } 8009f78: e003 b.n 8009f82 USBD_CtlError(pdev, req); 8009f7a: 6839 ldr r1, [r7, #0] 8009f7c: 6878 ldr r0, [r7, #4] 8009f7e: f000 f860 bl 800a042 } 8009f82: bf00 nop 8009f84: 3708 adds r7, #8 8009f86: 46bd mov sp, r7 8009f88: bd80 pop {r7, pc} 08009f8a : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009f8a: b580 push {r7, lr} 8009f8c: b082 sub sp, #8 8009f8e: af00 add r7, sp, #0 8009f90: 6078 str r0, [r7, #4] 8009f92: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8009f94: 687b ldr r3, [r7, #4] 8009f96: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009f9a: b2db uxtb r3, r3 8009f9c: 3b01 subs r3, #1 8009f9e: 2b02 cmp r3, #2 8009fa0: d80b bhi.n 8009fba { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8009fa2: 683b ldr r3, [r7, #0] 8009fa4: 885b ldrh r3, [r3, #2] 8009fa6: 2b01 cmp r3, #1 8009fa8: d10c bne.n 8009fc4 { pdev->dev_remote_wakeup = 0U; 8009faa: 687b ldr r3, [r7, #4] 8009fac: 2200 movs r2, #0 8009fae: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8009fb2: 6878 ldr r0, [r7, #4] 8009fb4: f000 f902 bl 800a1bc } break; 8009fb8: e004 b.n 8009fc4 default: USBD_CtlError(pdev, req); 8009fba: 6839 ldr r1, [r7, #0] 8009fbc: 6878 ldr r0, [r7, #4] 8009fbe: f000 f840 bl 800a042 break; 8009fc2: e000 b.n 8009fc6 break; 8009fc4: bf00 nop } } 8009fc6: bf00 nop 8009fc8: 3708 adds r7, #8 8009fca: 46bd mov sp, r7 8009fcc: bd80 pop {r7, pc} 08009fce : * @param req: usb request * @param pdata: setup data pointer * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 8009fce: b580 push {r7, lr} 8009fd0: b084 sub sp, #16 8009fd2: af00 add r7, sp, #0 8009fd4: 6078 str r0, [r7, #4] 8009fd6: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 8009fd8: 683b ldr r3, [r7, #0] 8009fda: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 8009fdc: 68fb ldr r3, [r7, #12] 8009fde: 781a ldrb r2, [r3, #0] 8009fe0: 687b ldr r3, [r7, #4] 8009fe2: 701a strb r2, [r3, #0] pbuff++; 8009fe4: 68fb ldr r3, [r7, #12] 8009fe6: 3301 adds r3, #1 8009fe8: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 8009fea: 68fb ldr r3, [r7, #12] 8009fec: 781a ldrb r2, [r3, #0] 8009fee: 687b ldr r3, [r7, #4] 8009ff0: 705a strb r2, [r3, #1] pbuff++; 8009ff2: 68fb ldr r3, [r7, #12] 8009ff4: 3301 adds r3, #1 8009ff6: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 8009ff8: 68f8 ldr r0, [r7, #12] 8009ffa: f7ff fa13 bl 8009424 8009ffe: 4603 mov r3, r0 800a000: 461a mov r2, r3 800a002: 687b ldr r3, [r7, #4] 800a004: 805a strh r2, [r3, #2] pbuff++; 800a006: 68fb ldr r3, [r7, #12] 800a008: 3301 adds r3, #1 800a00a: 60fb str r3, [r7, #12] pbuff++; 800a00c: 68fb ldr r3, [r7, #12] 800a00e: 3301 adds r3, #1 800a010: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 800a012: 68f8 ldr r0, [r7, #12] 800a014: f7ff fa06 bl 8009424 800a018: 4603 mov r3, r0 800a01a: 461a mov r2, r3 800a01c: 687b ldr r3, [r7, #4] 800a01e: 809a strh r2, [r3, #4] pbuff++; 800a020: 68fb ldr r3, [r7, #12] 800a022: 3301 adds r3, #1 800a024: 60fb str r3, [r7, #12] pbuff++; 800a026: 68fb ldr r3, [r7, #12] 800a028: 3301 adds r3, #1 800a02a: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 800a02c: 68f8 ldr r0, [r7, #12] 800a02e: f7ff f9f9 bl 8009424 800a032: 4603 mov r3, r0 800a034: 461a mov r2, r3 800a036: 687b ldr r3, [r7, #4] 800a038: 80da strh r2, [r3, #6] } 800a03a: bf00 nop 800a03c: 3710 adds r7, #16 800a03e: 46bd mov sp, r7 800a040: bd80 pop {r7, pc} 0800a042 : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a042: b580 push {r7, lr} 800a044: b082 sub sp, #8 800a046: af00 add r7, sp, #0 800a048: 6078 str r0, [r7, #4] 800a04a: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 800a04c: 2180 movs r1, #128 @ 0x80 800a04e: 6878 ldr r0, [r7, #4] 800a050: f000 fc2a bl 800a8a8 (void)USBD_LL_StallEP(pdev, 0U); 800a054: 2100 movs r1, #0 800a056: 6878 ldr r0, [r7, #4] 800a058: f000 fc26 bl 800a8a8 } 800a05c: bf00 nop 800a05e: 3708 adds r7, #8 800a060: 46bd mov sp, r7 800a062: bd80 pop {r7, pc} 0800a064 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 800a064: b580 push {r7, lr} 800a066: b086 sub sp, #24 800a068: af00 add r7, sp, #0 800a06a: 60f8 str r0, [r7, #12] 800a06c: 60b9 str r1, [r7, #8] 800a06e: 607a str r2, [r7, #4] uint8_t idx = 0U; 800a070: 2300 movs r3, #0 800a072: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 800a074: 68fb ldr r3, [r7, #12] 800a076: 2b00 cmp r3, #0 800a078: d042 beq.n 800a100 { return; } pdesc = desc; 800a07a: 68fb ldr r3, [r7, #12] 800a07c: 613b str r3, [r7, #16] *len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U); 800a07e: 6938 ldr r0, [r7, #16] 800a080: f000 f842 bl 800a108 800a084: 4603 mov r3, r0 800a086: 3301 adds r3, #1 800a088: 005b lsls r3, r3, #1 800a08a: f5b3 7f00 cmp.w r3, #512 @ 0x200 800a08e: d808 bhi.n 800a0a2 800a090: 6938 ldr r0, [r7, #16] 800a092: f000 f839 bl 800a108 800a096: 4603 mov r3, r0 800a098: 3301 adds r3, #1 800a09a: b29b uxth r3, r3 800a09c: 005b lsls r3, r3, #1 800a09e: b29a uxth r2, r3 800a0a0: e001 b.n 800a0a6 800a0a2: f44f 7200 mov.w r2, #512 @ 0x200 800a0a6: 687b ldr r3, [r7, #4] 800a0a8: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 800a0aa: 7dfb ldrb r3, [r7, #23] 800a0ac: 68ba ldr r2, [r7, #8] 800a0ae: 4413 add r3, r2 800a0b0: 687a ldr r2, [r7, #4] 800a0b2: 7812 ldrb r2, [r2, #0] 800a0b4: 701a strb r2, [r3, #0] idx++; 800a0b6: 7dfb ldrb r3, [r7, #23] 800a0b8: 3301 adds r3, #1 800a0ba: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 800a0bc: 7dfb ldrb r3, [r7, #23] 800a0be: 68ba ldr r2, [r7, #8] 800a0c0: 4413 add r3, r2 800a0c2: 2203 movs r2, #3 800a0c4: 701a strb r2, [r3, #0] idx++; 800a0c6: 7dfb ldrb r3, [r7, #23] 800a0c8: 3301 adds r3, #1 800a0ca: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 800a0cc: e013 b.n 800a0f6 { unicode[idx] = *pdesc; 800a0ce: 7dfb ldrb r3, [r7, #23] 800a0d0: 68ba ldr r2, [r7, #8] 800a0d2: 4413 add r3, r2 800a0d4: 693a ldr r2, [r7, #16] 800a0d6: 7812 ldrb r2, [r2, #0] 800a0d8: 701a strb r2, [r3, #0] pdesc++; 800a0da: 693b ldr r3, [r7, #16] 800a0dc: 3301 adds r3, #1 800a0de: 613b str r3, [r7, #16] idx++; 800a0e0: 7dfb ldrb r3, [r7, #23] 800a0e2: 3301 adds r3, #1 800a0e4: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 800a0e6: 7dfb ldrb r3, [r7, #23] 800a0e8: 68ba ldr r2, [r7, #8] 800a0ea: 4413 add r3, r2 800a0ec: 2200 movs r2, #0 800a0ee: 701a strb r2, [r3, #0] idx++; 800a0f0: 7dfb ldrb r3, [r7, #23] 800a0f2: 3301 adds r3, #1 800a0f4: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 800a0f6: 693b ldr r3, [r7, #16] 800a0f8: 781b ldrb r3, [r3, #0] 800a0fa: 2b00 cmp r3, #0 800a0fc: d1e7 bne.n 800a0ce 800a0fe: e000 b.n 800a102 return; 800a100: bf00 nop } } 800a102: 3718 adds r7, #24 800a104: 46bd mov sp, r7 800a106: bd80 pop {r7, pc} 0800a108 : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 800a108: b480 push {r7} 800a10a: b085 sub sp, #20 800a10c: af00 add r7, sp, #0 800a10e: 6078 str r0, [r7, #4] uint8_t len = 0U; 800a110: 2300 movs r3, #0 800a112: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 800a114: 687b ldr r3, [r7, #4] 800a116: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 800a118: e005 b.n 800a126 { len++; 800a11a: 7bfb ldrb r3, [r7, #15] 800a11c: 3301 adds r3, #1 800a11e: 73fb strb r3, [r7, #15] pbuff++; 800a120: 68bb ldr r3, [r7, #8] 800a122: 3301 adds r3, #1 800a124: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 800a126: 68bb ldr r3, [r7, #8] 800a128: 781b ldrb r3, [r3, #0] 800a12a: 2b00 cmp r3, #0 800a12c: d1f5 bne.n 800a11a } return len; 800a12e: 7bfb ldrb r3, [r7, #15] } 800a130: 4618 mov r0, r3 800a132: 3714 adds r7, #20 800a134: 46bd mov sp, r7 800a136: f85d 7b04 ldr.w r7, [sp], #4 800a13a: 4770 bx lr 0800a13c : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a13c: b580 push {r7, lr} 800a13e: b084 sub sp, #16 800a140: af00 add r7, sp, #0 800a142: 60f8 str r0, [r7, #12] 800a144: 60b9 str r1, [r7, #8] 800a146: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 800a148: 68fb ldr r3, [r7, #12] 800a14a: 2202 movs r2, #2 800a14c: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_in[0].total_length = len; 800a150: 68fb ldr r3, [r7, #12] 800a152: 687a ldr r2, [r7, #4] 800a154: 615a str r2, [r3, #20] pdev->ep_in[0].pbuffer = pbuf; 800a156: 68fb ldr r3, [r7, #12] 800a158: 68ba ldr r2, [r7, #8] 800a15a: 625a str r2, [r3, #36] @ 0x24 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 800a15c: 68fb ldr r3, [r7, #12] 800a15e: 687a ldr r2, [r7, #4] 800a160: 619a str r2, [r3, #24] #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800a162: 687b ldr r3, [r7, #4] 800a164: 68ba ldr r2, [r7, #8] 800a166: 2100 movs r1, #0 800a168: 68f8 ldr r0, [r7, #12] 800a16a: f000 fc26 bl 800a9ba return USBD_OK; 800a16e: 2300 movs r3, #0 } 800a170: 4618 mov r0, r3 800a172: 3710 adds r7, #16 800a174: 46bd mov sp, r7 800a176: bd80 pop {r7, pc} 0800a178 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a178: b580 push {r7, lr} 800a17a: b084 sub sp, #16 800a17c: af00 add r7, sp, #0 800a17e: 60f8 str r0, [r7, #12] 800a180: 60b9 str r1, [r7, #8] 800a182: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800a184: 687b ldr r3, [r7, #4] 800a186: 68ba ldr r2, [r7, #8] 800a188: 2100 movs r1, #0 800a18a: 68f8 ldr r0, [r7, #12] 800a18c: f000 fc15 bl 800a9ba return USBD_OK; 800a190: 2300 movs r3, #0 } 800a192: 4618 mov r0, r3 800a194: 3710 adds r7, #16 800a196: 46bd mov sp, r7 800a198: bd80 pop {r7, pc} 0800a19a : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a19a: b580 push {r7, lr} 800a19c: b084 sub sp, #16 800a19e: af00 add r7, sp, #0 800a1a0: 60f8 str r0, [r7, #12] 800a1a2: 60b9 str r1, [r7, #8] 800a1a4: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 800a1a6: 687b ldr r3, [r7, #4] 800a1a8: 68ba ldr r2, [r7, #8] 800a1aa: 2100 movs r1, #0 800a1ac: 68f8 ldr r0, [r7, #12] 800a1ae: f000 fc25 bl 800a9fc return USBD_OK; 800a1b2: 2300 movs r3, #0 } 800a1b4: 4618 mov r0, r3 800a1b6: 3710 adds r7, #16 800a1b8: 46bd mov sp, r7 800a1ba: bd80 pop {r7, pc} 0800a1bc : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 800a1bc: b580 push {r7, lr} 800a1be: b082 sub sp, #8 800a1c0: af00 add r7, sp, #0 800a1c2: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 800a1c4: 687b ldr r3, [r7, #4] 800a1c6: 2204 movs r2, #4 800a1c8: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 800a1cc: 2300 movs r3, #0 800a1ce: 2200 movs r2, #0 800a1d0: 2100 movs r1, #0 800a1d2: 6878 ldr r0, [r7, #4] 800a1d4: f000 fbf1 bl 800a9ba return USBD_OK; 800a1d8: 2300 movs r3, #0 } 800a1da: 4618 mov r0, r3 800a1dc: 3708 adds r7, #8 800a1de: 46bd mov sp, r7 800a1e0: bd80 pop {r7, pc} 0800a1e2 : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 800a1e2: b580 push {r7, lr} 800a1e4: b082 sub sp, #8 800a1e6: af00 add r7, sp, #0 800a1e8: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 800a1ea: 687b ldr r3, [r7, #4] 800a1ec: 2205 movs r2, #5 800a1ee: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 800a1f2: 2300 movs r3, #0 800a1f4: 2200 movs r2, #0 800a1f6: 2100 movs r1, #0 800a1f8: 6878 ldr r0, [r7, #4] 800a1fa: f000 fbff bl 800a9fc return USBD_OK; 800a1fe: 2300 movs r3, #0 } 800a200: 4618 mov r0, r3 800a202: 3708 adds r7, #8 800a204: 46bd mov sp, r7 800a206: bd80 pop {r7, pc} 0800a208 : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 800a208: b580 push {r7, lr} 800a20a: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) 800a20c: 2200 movs r2, #0 800a20e: 490e ldr r1, [pc, #56] @ (800a248 ) 800a210: 480e ldr r0, [pc, #56] @ (800a24c ) 800a212: f7fe fcd1 bl 8008bb8 800a216: 4603 mov r3, r0 800a218: 2b00 cmp r3, #0 800a21a: d001 beq.n 800a220 { Error_Handler(); 800a21c: f7f6 fdf4 bl 8000e08 } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) 800a220: 490b ldr r1, [pc, #44] @ (800a250 ) 800a222: 480a ldr r0, [pc, #40] @ (800a24c ) 800a224: f7fe fcf8 bl 8008c18 800a228: 4603 mov r3, r0 800a22a: 2b00 cmp r3, #0 800a22c: d001 beq.n 800a232 { Error_Handler(); 800a22e: f7f6 fdeb bl 8000e08 } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) 800a232: 4806 ldr r0, [pc, #24] @ (800a24c ) 800a234: f7fe fd26 bl 8008c84 800a238: 4603 mov r3, r0 800a23a: 2b00 cmp r3, #0 800a23c: d001 beq.n 800a242 { Error_Handler(); 800a23e: f7f6 fde3 bl 8000e08 } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 800a242: bf00 nop 800a244: bd80 pop {r7, pc} 800a246: bf00 nop 800a248: 20000140 .word 0x20000140 800a24c: 20000724 .word 0x20000724 800a250: 2000009c .word 0x2000009c 0800a254 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a254: b480 push {r7} 800a256: b083 sub sp, #12 800a258: af00 add r7, sp, #0 800a25a: 4603 mov r3, r0 800a25c: 6039 str r1, [r7, #0] 800a25e: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_DeviceDesc); 800a260: 683b ldr r3, [r7, #0] 800a262: 2212 movs r2, #18 800a264: 801a strh r2, [r3, #0] return USBD_FS_DeviceDesc; 800a266: 4b03 ldr r3, [pc, #12] @ (800a274 ) } 800a268: 4618 mov r0, r3 800a26a: 370c adds r7, #12 800a26c: 46bd mov sp, r7 800a26e: f85d 7b04 ldr.w r7, [sp], #4 800a272: 4770 bx lr 800a274: 20000160 .word 0x20000160 0800a278 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a278: b480 push {r7} 800a27a: b083 sub sp, #12 800a27c: af00 add r7, sp, #0 800a27e: 4603 mov r3, r0 800a280: 6039 str r1, [r7, #0] 800a282: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 800a284: 683b ldr r3, [r7, #0] 800a286: 2204 movs r2, #4 800a288: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 800a28a: 4b03 ldr r3, [pc, #12] @ (800a298 ) } 800a28c: 4618 mov r0, r3 800a28e: 370c adds r7, #12 800a290: 46bd mov sp, r7 800a292: f85d 7b04 ldr.w r7, [sp], #4 800a296: 4770 bx lr 800a298: 20000180 .word 0x20000180 0800a29c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a29c: b580 push {r7, lr} 800a29e: b082 sub sp, #8 800a2a0: af00 add r7, sp, #0 800a2a2: 4603 mov r3, r0 800a2a4: 6039 str r1, [r7, #0] 800a2a6: 71fb strb r3, [r7, #7] if(speed == 0) 800a2a8: 79fb ldrb r3, [r7, #7] 800a2aa: 2b00 cmp r3, #0 800a2ac: d105 bne.n 800a2ba { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800a2ae: 683a ldr r2, [r7, #0] 800a2b0: 4907 ldr r1, [pc, #28] @ (800a2d0 ) 800a2b2: 4808 ldr r0, [pc, #32] @ (800a2d4 ) 800a2b4: f7ff fed6 bl 800a064 800a2b8: e004 b.n 800a2c4 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800a2ba: 683a ldr r2, [r7, #0] 800a2bc: 4904 ldr r1, [pc, #16] @ (800a2d0 ) 800a2be: 4805 ldr r0, [pc, #20] @ (800a2d4 ) 800a2c0: f7ff fed0 bl 800a064 } return USBD_StrDesc; 800a2c4: 4b02 ldr r3, [pc, #8] @ (800a2d0 ) } 800a2c6: 4618 mov r0, r3 800a2c8: 3708 adds r7, #8 800a2ca: 46bd mov sp, r7 800a2cc: bd80 pop {r7, pc} 800a2ce: bf00 nop 800a2d0: 20000a00 .word 0x20000a00 800a2d4: 0800abf0 .word 0x0800abf0 0800a2d8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a2d8: b580 push {r7, lr} 800a2da: b082 sub sp, #8 800a2dc: af00 add r7, sp, #0 800a2de: 4603 mov r3, r0 800a2e0: 6039 str r1, [r7, #0] 800a2e2: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 800a2e4: 683a ldr r2, [r7, #0] 800a2e6: 4904 ldr r1, [pc, #16] @ (800a2f8 ) 800a2e8: 4804 ldr r0, [pc, #16] @ (800a2fc ) 800a2ea: f7ff febb bl 800a064 return USBD_StrDesc; 800a2ee: 4b02 ldr r3, [pc, #8] @ (800a2f8 ) } 800a2f0: 4618 mov r0, r3 800a2f2: 3708 adds r7, #8 800a2f4: 46bd mov sp, r7 800a2f6: bd80 pop {r7, pc} 800a2f8: 20000a00 .word 0x20000a00 800a2fc: 0800ac04 .word 0x0800ac04 0800a300 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a300: b580 push {r7, lr} 800a302: b082 sub sp, #8 800a304: af00 add r7, sp, #0 800a306: 4603 mov r3, r0 800a308: 6039 str r1, [r7, #0] 800a30a: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 800a30c: 683b ldr r3, [r7, #0] 800a30e: 221a movs r2, #26 800a310: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 800a312: f000 f855 bl 800a3c0 /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ /* USER CODE END USBD_FS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 800a316: 4b02 ldr r3, [pc, #8] @ (800a320 ) } 800a318: 4618 mov r0, r3 800a31a: 3708 adds r7, #8 800a31c: 46bd mov sp, r7 800a31e: bd80 pop {r7, pc} 800a320: 20000184 .word 0x20000184 0800a324 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a324: b580 push {r7, lr} 800a326: b082 sub sp, #8 800a328: af00 add r7, sp, #0 800a32a: 4603 mov r3, r0 800a32c: 6039 str r1, [r7, #0] 800a32e: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 800a330: 79fb ldrb r3, [r7, #7] 800a332: 2b00 cmp r3, #0 800a334: d105 bne.n 800a342 { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800a336: 683a ldr r2, [r7, #0] 800a338: 4907 ldr r1, [pc, #28] @ (800a358 ) 800a33a: 4808 ldr r0, [pc, #32] @ (800a35c ) 800a33c: f7ff fe92 bl 800a064 800a340: e004 b.n 800a34c } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800a342: 683a ldr r2, [r7, #0] 800a344: 4904 ldr r1, [pc, #16] @ (800a358 ) 800a346: 4805 ldr r0, [pc, #20] @ (800a35c ) 800a348: f7ff fe8c bl 800a064 } return USBD_StrDesc; 800a34c: 4b02 ldr r3, [pc, #8] @ (800a358 ) } 800a34e: 4618 mov r0, r3 800a350: 3708 adds r7, #8 800a352: 46bd mov sp, r7 800a354: bd80 pop {r7, pc} 800a356: bf00 nop 800a358: 20000a00 .word 0x20000a00 800a35c: 0800ac10 .word 0x0800ac10 0800a360 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a360: b580 push {r7, lr} 800a362: b082 sub sp, #8 800a364: af00 add r7, sp, #0 800a366: 4603 mov r3, r0 800a368: 6039 str r1, [r7, #0] 800a36a: 71fb strb r3, [r7, #7] if(speed == 0) 800a36c: 79fb ldrb r3, [r7, #7] 800a36e: 2b00 cmp r3, #0 800a370: d105 bne.n 800a37e { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800a372: 683a ldr r2, [r7, #0] 800a374: 4907 ldr r1, [pc, #28] @ (800a394 ) 800a376: 4808 ldr r0, [pc, #32] @ (800a398 ) 800a378: f7ff fe74 bl 800a064 800a37c: e004 b.n 800a388 } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800a37e: 683a ldr r2, [r7, #0] 800a380: 4904 ldr r1, [pc, #16] @ (800a394 ) 800a382: 4805 ldr r0, [pc, #20] @ (800a398 ) 800a384: f7ff fe6e bl 800a064 } return USBD_StrDesc; 800a388: 4b02 ldr r3, [pc, #8] @ (800a394 ) } 800a38a: 4618 mov r0, r3 800a38c: 3708 adds r7, #8 800a38e: 46bd mov sp, r7 800a390: bd80 pop {r7, pc} 800a392: bf00 nop 800a394: 20000a00 .word 0x20000a00 800a398: 0800ac1c .word 0x0800ac1c 0800a39c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800a39c: b480 push {r7} 800a39e: b083 sub sp, #12 800a3a0: af00 add r7, sp, #0 800a3a2: 4603 mov r3, r0 800a3a4: 6039 str r1, [r7, #0] 800a3a6: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_BOSDesc); 800a3a8: 683b ldr r3, [r7, #0] 800a3aa: 220c movs r2, #12 800a3ac: 801a strh r2, [r3, #0] return (uint8_t*)USBD_FS_BOSDesc; 800a3ae: 4b03 ldr r3, [pc, #12] @ (800a3bc ) } 800a3b0: 4618 mov r0, r3 800a3b2: 370c adds r7, #12 800a3b4: 46bd mov sp, r7 800a3b6: f85d 7b04 ldr.w r7, [sp], #4 800a3ba: 4770 bx lr 800a3bc: 20000174 .word 0x20000174 0800a3c0 : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 800a3c0: b580 push {r7, lr} 800a3c2: b084 sub sp, #16 800a3c4: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 800a3c6: 4b0f ldr r3, [pc, #60] @ (800a404 ) 800a3c8: 681b ldr r3, [r3, #0] 800a3ca: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 800a3cc: 4b0e ldr r3, [pc, #56] @ (800a408 ) 800a3ce: 681b ldr r3, [r3, #0] 800a3d0: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 800a3d2: 4b0e ldr r3, [pc, #56] @ (800a40c ) 800a3d4: 681b ldr r3, [r3, #0] 800a3d6: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 800a3d8: 68fa ldr r2, [r7, #12] 800a3da: 687b ldr r3, [r7, #4] 800a3dc: 4413 add r3, r2 800a3de: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 800a3e0: 68fb ldr r3, [r7, #12] 800a3e2: 2b00 cmp r3, #0 800a3e4: d009 beq.n 800a3fa { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 800a3e6: 2208 movs r2, #8 800a3e8: 4909 ldr r1, [pc, #36] @ (800a410 ) 800a3ea: 68f8 ldr r0, [r7, #12] 800a3ec: f000 f814 bl 800a418 IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 800a3f0: 2204 movs r2, #4 800a3f2: 4908 ldr r1, [pc, #32] @ (800a414 ) 800a3f4: 68b8 ldr r0, [r7, #8] 800a3f6: f000 f80f bl 800a418 } } 800a3fa: bf00 nop 800a3fc: 3710 adds r7, #16 800a3fe: 46bd mov sp, r7 800a400: bd80 pop {r7, pc} 800a402: bf00 nop 800a404: 1fff7a10 .word 0x1fff7a10 800a408: 1fff7a14 .word 0x1fff7a14 800a40c: 1fff7a18 .word 0x1fff7a18 800a410: 20000186 .word 0x20000186 800a414: 20000196 .word 0x20000196 0800a418 : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 800a418: b480 push {r7} 800a41a: b087 sub sp, #28 800a41c: af00 add r7, sp, #0 800a41e: 60f8 str r0, [r7, #12] 800a420: 60b9 str r1, [r7, #8] 800a422: 4613 mov r3, r2 800a424: 71fb strb r3, [r7, #7] uint8_t idx = 0; 800a426: 2300 movs r3, #0 800a428: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 800a42a: 2300 movs r3, #0 800a42c: 75fb strb r3, [r7, #23] 800a42e: e027 b.n 800a480 { if (((value >> 28)) < 0xA) 800a430: 68fb ldr r3, [r7, #12] 800a432: 0f1b lsrs r3, r3, #28 800a434: 2b09 cmp r3, #9 800a436: d80b bhi.n 800a450 { pbuf[2 * idx] = (value >> 28) + '0'; 800a438: 68fb ldr r3, [r7, #12] 800a43a: 0f1b lsrs r3, r3, #28 800a43c: b2da uxtb r2, r3 800a43e: 7dfb ldrb r3, [r7, #23] 800a440: 005b lsls r3, r3, #1 800a442: 4619 mov r1, r3 800a444: 68bb ldr r3, [r7, #8] 800a446: 440b add r3, r1 800a448: 3230 adds r2, #48 @ 0x30 800a44a: b2d2 uxtb r2, r2 800a44c: 701a strb r2, [r3, #0] 800a44e: e00a b.n 800a466 } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 800a450: 68fb ldr r3, [r7, #12] 800a452: 0f1b lsrs r3, r3, #28 800a454: b2da uxtb r2, r3 800a456: 7dfb ldrb r3, [r7, #23] 800a458: 005b lsls r3, r3, #1 800a45a: 4619 mov r1, r3 800a45c: 68bb ldr r3, [r7, #8] 800a45e: 440b add r3, r1 800a460: 3237 adds r2, #55 @ 0x37 800a462: b2d2 uxtb r2, r2 800a464: 701a strb r2, [r3, #0] } value = value << 4; 800a466: 68fb ldr r3, [r7, #12] 800a468: 011b lsls r3, r3, #4 800a46a: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 800a46c: 7dfb ldrb r3, [r7, #23] 800a46e: 005b lsls r3, r3, #1 800a470: 3301 adds r3, #1 800a472: 68ba ldr r2, [r7, #8] 800a474: 4413 add r3, r2 800a476: 2200 movs r2, #0 800a478: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 800a47a: 7dfb ldrb r3, [r7, #23] 800a47c: 3301 adds r3, #1 800a47e: 75fb strb r3, [r7, #23] 800a480: 7dfa ldrb r2, [r7, #23] 800a482: 79fb ldrb r3, [r7, #7] 800a484: 429a cmp r2, r3 800a486: d3d3 bcc.n 800a430 } } 800a488: bf00 nop 800a48a: bf00 nop 800a48c: 371c adds r7, #28 800a48e: 46bd mov sp, r7 800a490: f85d 7b04 ldr.w r7, [sp], #4 800a494: 4770 bx lr ... 0800a498 : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 800a498: b580 push {r7, lr} 800a49a: b0a0 sub sp, #128 @ 0x80 800a49c: af00 add r7, sp, #0 800a49e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800a4a0: f107 036c add.w r3, r7, #108 @ 0x6c 800a4a4: 2200 movs r2, #0 800a4a6: 601a str r2, [r3, #0] 800a4a8: 605a str r2, [r3, #4] 800a4aa: 609a str r2, [r3, #8] 800a4ac: 60da str r2, [r3, #12] 800a4ae: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 800a4b0: f107 0310 add.w r3, r7, #16 800a4b4: 225c movs r2, #92 @ 0x5c 800a4b6: 2100 movs r1, #0 800a4b8: 4618 mov r0, r3 800a4ba: f000 fb53 bl 800ab64 if(pcdHandle->Instance==USB_OTG_FS) 800a4be: 687b ldr r3, [r7, #4] 800a4c0: 681b ldr r3, [r3, #0] 800a4c2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800a4c6: d149 bne.n 800a55c /* USER CODE END USB_OTG_FS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; 800a4c8: f44f 7380 mov.w r3, #256 @ 0x100 800a4cc: 613b str r3, [r7, #16] PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; 800a4ce: 2300 movs r3, #0 800a4d0: 667b str r3, [r7, #100] @ 0x64 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800a4d2: f107 0310 add.w r3, r7, #16 800a4d6: 4618 mov r0, r3 800a4d8: f7f9 febc bl 8004254 800a4dc: 4603 mov r3, r0 800a4de: 2b00 cmp r3, #0 800a4e0: d001 beq.n 800a4e6 { Error_Handler(); 800a4e2: f7f6 fc91 bl 8000e08 } __HAL_RCC_GPIOA_CLK_ENABLE(); 800a4e6: 2300 movs r3, #0 800a4e8: 60fb str r3, [r7, #12] 800a4ea: 4b1e ldr r3, [pc, #120] @ (800a564 ) 800a4ec: 6b1b ldr r3, [r3, #48] @ 0x30 800a4ee: 4a1d ldr r2, [pc, #116] @ (800a564 ) 800a4f0: f043 0301 orr.w r3, r3, #1 800a4f4: 6313 str r3, [r2, #48] @ 0x30 800a4f6: 4b1b ldr r3, [pc, #108] @ (800a564 ) 800a4f8: 6b1b ldr r3, [r3, #48] @ 0x30 800a4fa: f003 0301 and.w r3, r3, #1 800a4fe: 60fb str r3, [r7, #12] 800a500: 68fb ldr r3, [r7, #12] /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 800a502: f44f 53c0 mov.w r3, #6144 @ 0x1800 800a506: 66fb str r3, [r7, #108] @ 0x6c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800a508: 2302 movs r3, #2 800a50a: 673b str r3, [r7, #112] @ 0x70 GPIO_InitStruct.Pull = GPIO_NOPULL; 800a50c: 2300 movs r3, #0 800a50e: 677b str r3, [r7, #116] @ 0x74 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800a510: 2303 movs r3, #3 800a512: 67bb str r3, [r7, #120] @ 0x78 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 800a514: 230a movs r3, #10 800a516: 67fb str r3, [r7, #124] @ 0x7c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800a518: f107 036c add.w r3, r7, #108 @ 0x6c 800a51c: 4619 mov r1, r3 800a51e: 4812 ldr r0, [pc, #72] @ (800a568 ) 800a520: f7f7 ffee bl 8002500 /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 800a524: 4b0f ldr r3, [pc, #60] @ (800a564 ) 800a526: 6b5b ldr r3, [r3, #52] @ 0x34 800a528: 4a0e ldr r2, [pc, #56] @ (800a564 ) 800a52a: f043 0380 orr.w r3, r3, #128 @ 0x80 800a52e: 6353 str r3, [r2, #52] @ 0x34 800a530: 2300 movs r3, #0 800a532: 60bb str r3, [r7, #8] 800a534: 4b0b ldr r3, [pc, #44] @ (800a564 ) 800a536: 6c5b ldr r3, [r3, #68] @ 0x44 800a538: 4a0a ldr r2, [pc, #40] @ (800a564 ) 800a53a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800a53e: 6453 str r3, [r2, #68] @ 0x44 800a540: 4b08 ldr r3, [pc, #32] @ (800a564 ) 800a542: 6c5b ldr r3, [r3, #68] @ 0x44 800a544: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a548: 60bb str r3, [r7, #8] 800a54a: 68bb ldr r3, [r7, #8] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); 800a54c: 2200 movs r2, #0 800a54e: 2100 movs r1, #0 800a550: 2043 movs r0, #67 @ 0x43 800a552: f7f7 fb9c bl 8001c8e HAL_NVIC_EnableIRQ(OTG_FS_IRQn); 800a556: 2043 movs r0, #67 @ 0x43 800a558: f7f7 fbb5 bl 8001cc6 /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 800a55c: bf00 nop 800a55e: 3780 adds r7, #128 @ 0x80 800a560: 46bd mov sp, r7 800a562: bd80 pop {r7, pc} 800a564: 40023800 .word 0x40023800 800a568: 40020000 .word 0x40020000 0800a56c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a56c: b580 push {r7, lr} 800a56e: b082 sub sp, #8 800a570: af00 add r7, sp, #0 800a572: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 800a574: 687b ldr r3, [r7, #4] 800a576: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0 800a57a: 687b ldr r3, [r7, #4] 800a57c: f203 439c addw r3, r3, #1180 @ 0x49c 800a580: 4619 mov r1, r3 800a582: 4610 mov r0, r2 800a584: f7fe fbcb bl 8008d1e } 800a588: bf00 nop 800a58a: 3708 adds r7, #8 800a58c: 46bd mov sp, r7 800a58e: bd80 pop {r7, pc} 0800a590 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a590: b580 push {r7, lr} 800a592: b082 sub sp, #8 800a594: af00 add r7, sp, #0 800a596: 6078 str r0, [r7, #4] 800a598: 460b mov r3, r1 800a59a: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 800a59c: 687b ldr r3, [r7, #4] 800a59e: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800a5a2: 78fa ldrb r2, [r7, #3] 800a5a4: 6879 ldr r1, [r7, #4] 800a5a6: 4613 mov r3, r2 800a5a8: 00db lsls r3, r3, #3 800a5aa: 4413 add r3, r2 800a5ac: 009b lsls r3, r3, #2 800a5ae: 440b add r3, r1 800a5b0: f503 7318 add.w r3, r3, #608 @ 0x260 800a5b4: 681a ldr r2, [r3, #0] 800a5b6: 78fb ldrb r3, [r7, #3] 800a5b8: 4619 mov r1, r3 800a5ba: f7fe fc05 bl 8008dc8 } 800a5be: bf00 nop 800a5c0: 3708 adds r7, #8 800a5c2: 46bd mov sp, r7 800a5c4: bd80 pop {r7, pc} 0800a5c6 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a5c6: b580 push {r7, lr} 800a5c8: b082 sub sp, #8 800a5ca: af00 add r7, sp, #0 800a5cc: 6078 str r0, [r7, #4] 800a5ce: 460b mov r3, r1 800a5d0: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 800a5d2: 687b ldr r3, [r7, #4] 800a5d4: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800a5d8: 78fa ldrb r2, [r7, #3] 800a5da: 6879 ldr r1, [r7, #4] 800a5dc: 4613 mov r3, r2 800a5de: 00db lsls r3, r3, #3 800a5e0: 4413 add r3, r2 800a5e2: 009b lsls r3, r3, #2 800a5e4: 440b add r3, r1 800a5e6: 3320 adds r3, #32 800a5e8: 681a ldr r2, [r3, #0] 800a5ea: 78fb ldrb r3, [r7, #3] 800a5ec: 4619 mov r1, r3 800a5ee: f7fe fca7 bl 8008f40 } 800a5f2: bf00 nop 800a5f4: 3708 adds r7, #8 800a5f6: 46bd mov sp, r7 800a5f8: bd80 pop {r7, pc} 0800a5fa : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a5fa: b580 push {r7, lr} 800a5fc: b082 sub sp, #8 800a5fe: af00 add r7, sp, #0 800a600: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 800a602: 687b ldr r3, [r7, #4] 800a604: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a608: 4618 mov r0, r3 800a60a: f7fe fdeb bl 80091e4 } 800a60e: bf00 nop 800a610: 3708 adds r7, #8 800a612: 46bd mov sp, r7 800a614: bd80 pop {r7, pc} 0800a616 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a616: b580 push {r7, lr} 800a618: b084 sub sp, #16 800a61a: af00 add r7, sp, #0 800a61c: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 800a61e: 2301 movs r3, #1 800a620: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed == PCD_SPEED_HIGH) 800a622: 687b ldr r3, [r7, #4] 800a624: 79db ldrb r3, [r3, #7] 800a626: 2b00 cmp r3, #0 800a628: d102 bne.n 800a630 { speed = USBD_SPEED_HIGH; 800a62a: 2300 movs r3, #0 800a62c: 73fb strb r3, [r7, #15] 800a62e: e008 b.n 800a642 } else if ( hpcd->Init.speed == PCD_SPEED_FULL) 800a630: 687b ldr r3, [r7, #4] 800a632: 79db ldrb r3, [r3, #7] 800a634: 2b02 cmp r3, #2 800a636: d102 bne.n 800a63e { speed = USBD_SPEED_FULL; 800a638: 2301 movs r3, #1 800a63a: 73fb strb r3, [r7, #15] 800a63c: e001 b.n 800a642 } else { Error_Handler(); 800a63e: f7f6 fbe3 bl 8000e08 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 800a642: 687b ldr r3, [r7, #4] 800a644: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a648: 7bfa ldrb r2, [r7, #15] 800a64a: 4611 mov r1, r2 800a64c: 4618 mov r0, r3 800a64e: f7fe fd85 bl 800915c /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 800a652: 687b ldr r3, [r7, #4] 800a654: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a658: 4618 mov r0, r3 800a65a: f7fe fd2c bl 80090b6 } 800a65e: bf00 nop 800a660: 3710 adds r7, #16 800a662: 46bd mov sp, r7 800a664: bd80 pop {r7, pc} ... 0800a668 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a668: b580 push {r7, lr} 800a66a: b082 sub sp, #8 800a66c: af00 add r7, sp, #0 800a66e: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 800a670: 687b ldr r3, [r7, #4] 800a672: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a676: 4618 mov r0, r3 800a678: f7fe fd80 bl 800917c __HAL_PCD_GATE_PHYCLOCK(hpcd); 800a67c: 687b ldr r3, [r7, #4] 800a67e: 681b ldr r3, [r3, #0] 800a680: f503 6360 add.w r3, r3, #3584 @ 0xe00 800a684: 681b ldr r3, [r3, #0] 800a686: 687a ldr r2, [r7, #4] 800a688: 6812 ldr r2, [r2, #0] 800a68a: f502 6260 add.w r2, r2, #3584 @ 0xe00 800a68e: f043 0301 orr.w r3, r3, #1 800a692: 6013 str r3, [r2, #0] /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 800a694: 687b ldr r3, [r7, #4] 800a696: 7adb ldrb r3, [r3, #11] 800a698: 2b00 cmp r3, #0 800a69a: d005 beq.n 800a6a8 { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800a69c: 4b04 ldr r3, [pc, #16] @ (800a6b0 ) 800a69e: 691b ldr r3, [r3, #16] 800a6a0: 4a03 ldr r2, [pc, #12] @ (800a6b0 ) 800a6a2: f043 0306 orr.w r3, r3, #6 800a6a6: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 800a6a8: bf00 nop 800a6aa: 3708 adds r7, #8 800a6ac: 46bd mov sp, r7 800a6ae: bd80 pop {r7, pc} 800a6b0: e000ed00 .word 0xe000ed00 0800a6b4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a6b4: b580 push {r7, lr} 800a6b6: b082 sub sp, #8 800a6b8: af00 add r7, sp, #0 800a6ba: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 800a6bc: 687b ldr r3, [r7, #4] 800a6be: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a6c2: 4618 mov r0, r3 800a6c4: f7fe fd76 bl 80091b4 } 800a6c8: bf00 nop 800a6ca: 3708 adds r7, #8 800a6cc: 46bd mov sp, r7 800a6ce: bd80 pop {r7, pc} 0800a6d0 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a6d0: b580 push {r7, lr} 800a6d2: b082 sub sp, #8 800a6d4: af00 add r7, sp, #0 800a6d6: 6078 str r0, [r7, #4] 800a6d8: 460b mov r3, r1 800a6da: 70fb strb r3, [r7, #3] USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800a6dc: 687b ldr r3, [r7, #4] 800a6de: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a6e2: 78fa ldrb r2, [r7, #3] 800a6e4: 4611 mov r1, r2 800a6e6: 4618 mov r0, r3 800a6e8: f7fe fdce bl 8009288 } 800a6ec: bf00 nop 800a6ee: 3708 adds r7, #8 800a6f0: 46bd mov sp, r7 800a6f2: bd80 pop {r7, pc} 0800a6f4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a6f4: b580 push {r7, lr} 800a6f6: b082 sub sp, #8 800a6f8: af00 add r7, sp, #0 800a6fa: 6078 str r0, [r7, #4] 800a6fc: 460b mov r3, r1 800a6fe: 70fb strb r3, [r7, #3] USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800a700: 687b ldr r3, [r7, #4] 800a702: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a706: 78fa ldrb r2, [r7, #3] 800a708: 4611 mov r1, r2 800a70a: 4618 mov r0, r3 800a70c: f7fe fd8a bl 8009224 } 800a710: bf00 nop 800a712: 3708 adds r7, #8 800a714: 46bd mov sp, r7 800a716: bd80 pop {r7, pc} 0800a718 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a718: b580 push {r7, lr} 800a71a: b082 sub sp, #8 800a71c: af00 add r7, sp, #0 800a71e: 6078 str r0, [r7, #4] USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); 800a720: 687b ldr r3, [r7, #4] 800a722: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a726: 4618 mov r0, r3 800a728: f7fe fde0 bl 80092ec } 800a72c: bf00 nop 800a72e: 3708 adds r7, #8 800a730: 46bd mov sp, r7 800a732: bd80 pop {r7, pc} 0800a734 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800a734: b580 push {r7, lr} 800a736: b082 sub sp, #8 800a738: af00 add r7, sp, #0 800a73a: 6078 str r0, [r7, #4] USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); 800a73c: 687b ldr r3, [r7, #4] 800a73e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800a742: 4618 mov r0, r3 800a744: f7fe fddd bl 8009302 } 800a748: bf00 nop 800a74a: 3708 adds r7, #8 800a74c: 46bd mov sp, r7 800a74e: bd80 pop {r7, pc} 0800a750 : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 800a750: b580 push {r7, lr} 800a752: b082 sub sp, #8 800a754: af00 add r7, sp, #0 800a756: 6078 str r0, [r7, #4] /* Init USB Ip. */ if (pdev->id == DEVICE_FS) { 800a758: 687b ldr r3, [r7, #4] 800a75a: 781b ldrb r3, [r3, #0] 800a75c: 2b00 cmp r3, #0 800a75e: d13c bne.n 800a7da /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; 800a760: 4a20 ldr r2, [pc, #128] @ (800a7e4 ) 800a762: 687b ldr r3, [r7, #4] 800a764: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0 pdev->pData = &hpcd_USB_OTG_FS; 800a768: 687b ldr r3, [r7, #4] 800a76a: 4a1e ldr r2, [pc, #120] @ (800a7e4 ) 800a76c: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8 hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 800a770: 4b1c ldr r3, [pc, #112] @ (800a7e4 ) 800a772: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 800a776: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 6; 800a778: 4b1a ldr r3, [pc, #104] @ (800a7e4 ) 800a77a: 2206 movs r2, #6 800a77c: 711a strb r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 800a77e: 4b19 ldr r3, [pc, #100] @ (800a7e4 ) 800a780: 2202 movs r2, #2 800a782: 71da strb r2, [r3, #7] hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; 800a784: 4b17 ldr r3, [pc, #92] @ (800a7e4 ) 800a786: 2200 movs r2, #0 800a788: 719a strb r2, [r3, #6] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 800a78a: 4b16 ldr r3, [pc, #88] @ (800a7e4 ) 800a78c: 2202 movs r2, #2 800a78e: 725a strb r2, [r3, #9] hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; 800a790: 4b14 ldr r3, [pc, #80] @ (800a7e4 ) 800a792: 2200 movs r2, #0 800a794: 729a strb r2, [r3, #10] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 800a796: 4b13 ldr r3, [pc, #76] @ (800a7e4 ) 800a798: 2200 movs r2, #0 800a79a: 72da strb r2, [r3, #11] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 800a79c: 4b11 ldr r3, [pc, #68] @ (800a7e4 ) 800a79e: 2200 movs r2, #0 800a7a0: 731a strb r2, [r3, #12] hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; 800a7a2: 4b10 ldr r3, [pc, #64] @ (800a7e4 ) 800a7a4: 2200 movs r2, #0 800a7a6: 739a strb r2, [r3, #14] hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 800a7a8: 4b0e ldr r3, [pc, #56] @ (800a7e4 ) 800a7aa: 2200 movs r2, #0 800a7ac: 73da strb r2, [r3, #15] if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 800a7ae: 480d ldr r0, [pc, #52] @ (800a7e4 ) 800a7b0: f7f8 f9b0 bl 8002b14 800a7b4: 4603 mov r3, r0 800a7b6: 2b00 cmp r3, #0 800a7b8: d001 beq.n 800a7be { Error_Handler( ); 800a7ba: f7f6 fb25 bl 8000e08 HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback); HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); 800a7be: 2180 movs r1, #128 @ 0x80 800a7c0: 4808 ldr r0, [pc, #32] @ (800a7e4 ) 800a7c2: f7f9 fbf8 bl 8003fb6 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); 800a7c6: 2240 movs r2, #64 @ 0x40 800a7c8: 2100 movs r1, #0 800a7ca: 4806 ldr r0, [pc, #24] @ (800a7e4 ) 800a7cc: f7f9 fbac bl 8003f28 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); 800a7d0: 2280 movs r2, #128 @ 0x80 800a7d2: 2101 movs r1, #1 800a7d4: 4803 ldr r0, [pc, #12] @ (800a7e4 ) 800a7d6: f7f9 fba7 bl 8003f28 } return USBD_OK; 800a7da: 2300 movs r3, #0 } 800a7dc: 4618 mov r0, r3 800a7de: 3708 adds r7, #8 800a7e0: 46bd mov sp, r7 800a7e2: bd80 pop {r7, pc} 800a7e4: 20000c00 .word 0x20000c00 0800a7e8 : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 800a7e8: b580 push {r7, lr} 800a7ea: b084 sub sp, #16 800a7ec: af00 add r7, sp, #0 800a7ee: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 800a7f0: 2300 movs r3, #0 800a7f2: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a7f4: 2300 movs r3, #0 800a7f6: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 800a7f8: 687b ldr r3, [r7, #4] 800a7fa: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a7fe: 4618 mov r0, r3 800a800: f7f8 fa9e bl 8002d40 800a804: 4603 mov r3, r0 800a806: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a808: 7bfb ldrb r3, [r7, #15] 800a80a: 4618 mov r0, r3 800a80c: f000 f97e bl 800ab0c 800a810: 4603 mov r3, r0 800a812: 73bb strb r3, [r7, #14] return usb_status; 800a814: 7bbb ldrb r3, [r7, #14] } 800a816: 4618 mov r0, r3 800a818: 3710 adds r7, #16 800a81a: 46bd mov sp, r7 800a81c: bd80 pop {r7, pc} 0800a81e : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 800a81e: b580 push {r7, lr} 800a820: b084 sub sp, #16 800a822: af00 add r7, sp, #0 800a824: 6078 str r0, [r7, #4] 800a826: 4608 mov r0, r1 800a828: 4611 mov r1, r2 800a82a: 461a mov r2, r3 800a82c: 4603 mov r3, r0 800a82e: 70fb strb r3, [r7, #3] 800a830: 460b mov r3, r1 800a832: 70bb strb r3, [r7, #2] 800a834: 4613 mov r3, r2 800a836: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 800a838: 2300 movs r3, #0 800a83a: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a83c: 2300 movs r3, #0 800a83e: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 800a840: 687b ldr r3, [r7, #4] 800a842: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a846: 78bb ldrb r3, [r7, #2] 800a848: 883a ldrh r2, [r7, #0] 800a84a: 78f9 ldrb r1, [r7, #3] 800a84c: f7f8 ff9f bl 800378e 800a850: 4603 mov r3, r0 800a852: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a854: 7bfb ldrb r3, [r7, #15] 800a856: 4618 mov r0, r3 800a858: f000 f958 bl 800ab0c 800a85c: 4603 mov r3, r0 800a85e: 73bb strb r3, [r7, #14] return usb_status; 800a860: 7bbb ldrb r3, [r7, #14] } 800a862: 4618 mov r0, r3 800a864: 3710 adds r7, #16 800a866: 46bd mov sp, r7 800a868: bd80 pop {r7, pc} 0800a86a : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a86a: b580 push {r7, lr} 800a86c: b084 sub sp, #16 800a86e: af00 add r7, sp, #0 800a870: 6078 str r0, [r7, #4] 800a872: 460b mov r3, r1 800a874: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a876: 2300 movs r3, #0 800a878: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a87a: 2300 movs r3, #0 800a87c: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 800a87e: 687b ldr r3, [r7, #4] 800a880: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a884: 78fa ldrb r2, [r7, #3] 800a886: 4611 mov r1, r2 800a888: 4618 mov r0, r3 800a88a: f7f8 ffea bl 8003862 800a88e: 4603 mov r3, r0 800a890: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a892: 7bfb ldrb r3, [r7, #15] 800a894: 4618 mov r0, r3 800a896: f000 f939 bl 800ab0c 800a89a: 4603 mov r3, r0 800a89c: 73bb strb r3, [r7, #14] return usb_status; 800a89e: 7bbb ldrb r3, [r7, #14] } 800a8a0: 4618 mov r0, r3 800a8a2: 3710 adds r7, #16 800a8a4: 46bd mov sp, r7 800a8a6: bd80 pop {r7, pc} 0800a8a8 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a8a8: b580 push {r7, lr} 800a8aa: b084 sub sp, #16 800a8ac: af00 add r7, sp, #0 800a8ae: 6078 str r0, [r7, #4] 800a8b0: 460b mov r3, r1 800a8b2: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a8b4: 2300 movs r3, #0 800a8b6: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a8b8: 2300 movs r3, #0 800a8ba: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 800a8bc: 687b ldr r3, [r7, #4] 800a8be: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a8c2: 78fa ldrb r2, [r7, #3] 800a8c4: 4611 mov r1, r2 800a8c6: 4618 mov r0, r3 800a8c8: f7f9 f88a bl 80039e0 800a8cc: 4603 mov r3, r0 800a8ce: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a8d0: 7bfb ldrb r3, [r7, #15] 800a8d2: 4618 mov r0, r3 800a8d4: f000 f91a bl 800ab0c 800a8d8: 4603 mov r3, r0 800a8da: 73bb strb r3, [r7, #14] return usb_status; 800a8dc: 7bbb ldrb r3, [r7, #14] } 800a8de: 4618 mov r0, r3 800a8e0: 3710 adds r7, #16 800a8e2: 46bd mov sp, r7 800a8e4: bd80 pop {r7, pc} 0800a8e6 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a8e6: b580 push {r7, lr} 800a8e8: b084 sub sp, #16 800a8ea: af00 add r7, sp, #0 800a8ec: 6078 str r0, [r7, #4] 800a8ee: 460b mov r3, r1 800a8f0: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a8f2: 2300 movs r3, #0 800a8f4: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a8f6: 2300 movs r3, #0 800a8f8: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 800a8fa: 687b ldr r3, [r7, #4] 800a8fc: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a900: 78fa ldrb r2, [r7, #3] 800a902: 4611 mov r1, r2 800a904: 4618 mov r0, r3 800a906: f7f9 f8ce bl 8003aa6 800a90a: 4603 mov r3, r0 800a90c: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a90e: 7bfb ldrb r3, [r7, #15] 800a910: 4618 mov r0, r3 800a912: f000 f8fb bl 800ab0c 800a916: 4603 mov r3, r0 800a918: 73bb strb r3, [r7, #14] return usb_status; 800a91a: 7bbb ldrb r3, [r7, #14] } 800a91c: 4618 mov r0, r3 800a91e: 3710 adds r7, #16 800a920: 46bd mov sp, r7 800a922: bd80 pop {r7, pc} 0800a924 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800a924: b480 push {r7} 800a926: b085 sub sp, #20 800a928: af00 add r7, sp, #0 800a92a: 6078 str r0, [r7, #4] 800a92c: 460b mov r3, r1 800a92e: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 800a930: 687b ldr r3, [r7, #4] 800a932: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a936: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 800a938: f997 3003 ldrsb.w r3, [r7, #3] 800a93c: 2b00 cmp r3, #0 800a93e: da0b bge.n 800a958 { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 800a940: 78fb ldrb r3, [r7, #3] 800a942: f003 027f and.w r2, r3, #127 @ 0x7f 800a946: 68f9 ldr r1, [r7, #12] 800a948: 4613 mov r3, r2 800a94a: 00db lsls r3, r3, #3 800a94c: 4413 add r3, r2 800a94e: 009b lsls r3, r3, #2 800a950: 440b add r3, r1 800a952: 3316 adds r3, #22 800a954: 781b ldrb r3, [r3, #0] 800a956: e00b b.n 800a970 } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 800a958: 78fb ldrb r3, [r7, #3] 800a95a: f003 027f and.w r2, r3, #127 @ 0x7f 800a95e: 68f9 ldr r1, [r7, #12] 800a960: 4613 mov r3, r2 800a962: 00db lsls r3, r3, #3 800a964: 4413 add r3, r2 800a966: 009b lsls r3, r3, #2 800a968: 440b add r3, r1 800a96a: f203 2356 addw r3, r3, #598 @ 0x256 800a96e: 781b ldrb r3, [r3, #0] } } 800a970: 4618 mov r0, r3 800a972: 3714 adds r7, #20 800a974: 46bd mov sp, r7 800a976: f85d 7b04 ldr.w r7, [sp], #4 800a97a: 4770 bx lr 0800a97c : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 800a97c: b580 push {r7, lr} 800a97e: b084 sub sp, #16 800a980: af00 add r7, sp, #0 800a982: 6078 str r0, [r7, #4] 800a984: 460b mov r3, r1 800a986: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800a988: 2300 movs r3, #0 800a98a: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800a98c: 2300 movs r3, #0 800a98e: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 800a990: 687b ldr r3, [r7, #4] 800a992: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800a996: 78fa ldrb r2, [r7, #3] 800a998: 4611 mov r1, r2 800a99a: 4618 mov r0, r3 800a99c: f7f8 fed3 bl 8003746 800a9a0: 4603 mov r3, r0 800a9a2: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800a9a4: 7bfb ldrb r3, [r7, #15] 800a9a6: 4618 mov r0, r3 800a9a8: f000 f8b0 bl 800ab0c 800a9ac: 4603 mov r3, r0 800a9ae: 73bb strb r3, [r7, #14] return usb_status; 800a9b0: 7bbb ldrb r3, [r7, #14] } 800a9b2: 4618 mov r0, r3 800a9b4: 3710 adds r7, #16 800a9b6: 46bd mov sp, r7 800a9b8: bd80 pop {r7, pc} 0800a9ba : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800a9ba: b580 push {r7, lr} 800a9bc: b086 sub sp, #24 800a9be: af00 add r7, sp, #0 800a9c0: 60f8 str r0, [r7, #12] 800a9c2: 607a str r2, [r7, #4] 800a9c4: 603b str r3, [r7, #0] 800a9c6: 460b mov r3, r1 800a9c8: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800a9ca: 2300 movs r3, #0 800a9cc: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800a9ce: 2300 movs r3, #0 800a9d0: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 800a9d2: 68fb ldr r3, [r7, #12] 800a9d4: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800a9d8: 7af9 ldrb r1, [r7, #11] 800a9da: 683b ldr r3, [r7, #0] 800a9dc: 687a ldr r2, [r7, #4] 800a9de: f7f8 ffc5 bl 800396c 800a9e2: 4603 mov r3, r0 800a9e4: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800a9e6: 7dfb ldrb r3, [r7, #23] 800a9e8: 4618 mov r0, r3 800a9ea: f000 f88f bl 800ab0c 800a9ee: 4603 mov r3, r0 800a9f0: 75bb strb r3, [r7, #22] return usb_status; 800a9f2: 7dbb ldrb r3, [r7, #22] } 800a9f4: 4618 mov r0, r3 800a9f6: 3718 adds r7, #24 800a9f8: 46bd mov sp, r7 800a9fa: bd80 pop {r7, pc} 0800a9fc : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800a9fc: b580 push {r7, lr} 800a9fe: b086 sub sp, #24 800aa00: af00 add r7, sp, #0 800aa02: 60f8 str r0, [r7, #12] 800aa04: 607a str r2, [r7, #4] 800aa06: 603b str r3, [r7, #0] 800aa08: 460b mov r3, r1 800aa0a: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800aa0c: 2300 movs r3, #0 800aa0e: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800aa10: 2300 movs r3, #0 800aa12: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 800aa14: 68fb ldr r3, [r7, #12] 800aa16: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800aa1a: 7af9 ldrb r1, [r7, #11] 800aa1c: 683b ldr r3, [r7, #0] 800aa1e: 687a ldr r2, [r7, #4] 800aa20: f7f8 ff69 bl 80038f6 800aa24: 4603 mov r3, r0 800aa26: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800aa28: 7dfb ldrb r3, [r7, #23] 800aa2a: 4618 mov r0, r3 800aa2c: f000 f86e bl 800ab0c 800aa30: 4603 mov r3, r0 800aa32: 75bb strb r3, [r7, #22] return usb_status; 800aa34: 7dbb ldrb r3, [r7, #22] } 800aa36: 4618 mov r0, r3 800aa38: 3718 adds r7, #24 800aa3a: 46bd mov sp, r7 800aa3c: bd80 pop {r7, pc} ... 0800aa40 : * @param hpcd: PCD handle * @param msg: LPM message * @retval None */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { 800aa40: b580 push {r7, lr} 800aa42: b082 sub sp, #8 800aa44: af00 add r7, sp, #0 800aa46: 6078 str r0, [r7, #4] 800aa48: 460b mov r3, r1 800aa4a: 70fb strb r3, [r7, #3] switch (msg) 800aa4c: 78fb ldrb r3, [r7, #3] 800aa4e: 2b00 cmp r3, #0 800aa50: d002 beq.n 800aa58 800aa52: 2b01 cmp r3, #1 800aa54: d01f beq.n 800aa96 /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } } 800aa56: e03b b.n 800aad0 if (hpcd->Init.low_power_enable) 800aa58: 687b ldr r3, [r7, #4] 800aa5a: 7adb ldrb r3, [r3, #11] 800aa5c: 2b00 cmp r3, #0 800aa5e: d007 beq.n 800aa70 SystemClock_Config(); 800aa60: f7f5 ff9e bl 80009a0 SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800aa64: 4b1c ldr r3, [pc, #112] @ (800aad8 ) 800aa66: 691b ldr r3, [r3, #16] 800aa68: 4a1b ldr r2, [pc, #108] @ (800aad8 ) 800aa6a: f023 0306 bic.w r3, r3, #6 800aa6e: 6113 str r3, [r2, #16] __HAL_PCD_UNGATE_PHYCLOCK(hpcd); 800aa70: 687b ldr r3, [r7, #4] 800aa72: 681b ldr r3, [r3, #0] 800aa74: f503 6360 add.w r3, r3, #3584 @ 0xe00 800aa78: 681b ldr r3, [r3, #0] 800aa7a: 687a ldr r2, [r7, #4] 800aa7c: 6812 ldr r2, [r2, #0] 800aa7e: f502 6260 add.w r2, r2, #3584 @ 0xe00 800aa82: f023 0301 bic.w r3, r3, #1 800aa86: 6013 str r3, [r2, #0] USBD_LL_Resume(hpcd->pData); 800aa88: 687b ldr r3, [r7, #4] 800aa8a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800aa8e: 4618 mov r0, r3 800aa90: f7fe fb90 bl 80091b4 break; 800aa94: e01c b.n 800aad0 __HAL_PCD_GATE_PHYCLOCK(hpcd); 800aa96: 687b ldr r3, [r7, #4] 800aa98: 681b ldr r3, [r3, #0] 800aa9a: f503 6360 add.w r3, r3, #3584 @ 0xe00 800aa9e: 681b ldr r3, [r3, #0] 800aaa0: 687a ldr r2, [r7, #4] 800aaa2: 6812 ldr r2, [r2, #0] 800aaa4: f502 6260 add.w r2, r2, #3584 @ 0xe00 800aaa8: f043 0301 orr.w r3, r3, #1 800aaac: 6013 str r3, [r2, #0] USBD_LL_Suspend(hpcd->pData); 800aaae: 687b ldr r3, [r7, #4] 800aab0: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800aab4: 4618 mov r0, r3 800aab6: f7fe fb61 bl 800917c if (hpcd->Init.low_power_enable) 800aaba: 687b ldr r3, [r7, #4] 800aabc: 7adb ldrb r3, [r3, #11] 800aabe: 2b00 cmp r3, #0 800aac0: d005 beq.n 800aace SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800aac2: 4b05 ldr r3, [pc, #20] @ (800aad8 ) 800aac4: 691b ldr r3, [r3, #16] 800aac6: 4a04 ldr r2, [pc, #16] @ (800aad8 ) 800aac8: f043 0306 orr.w r3, r3, #6 800aacc: 6113 str r3, [r2, #16] break; 800aace: bf00 nop } 800aad0: bf00 nop 800aad2: 3708 adds r7, #8 800aad4: 46bd mov sp, r7 800aad6: bd80 pop {r7, pc} 800aad8: e000ed00 .word 0xe000ed00 0800aadc : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 800aadc: b480 push {r7} 800aade: b083 sub sp, #12 800aae0: af00 add r7, sp, #0 800aae2: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 800aae4: 4b03 ldr r3, [pc, #12] @ (800aaf4 ) } 800aae6: 4618 mov r0, r3 800aae8: 370c adds r7, #12 800aaea: 46bd mov sp, r7 800aaec: f85d 7b04 ldr.w r7, [sp], #4 800aaf0: 4770 bx lr 800aaf2: bf00 nop 800aaf4: 200010e4 .word 0x200010e4 0800aaf8 : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 800aaf8: b480 push {r7} 800aafa: b083 sub sp, #12 800aafc: af00 add r7, sp, #0 800aafe: 6078 str r0, [r7, #4] } 800ab00: bf00 nop 800ab02: 370c adds r7, #12 800ab04: 46bd mov sp, r7 800ab06: f85d 7b04 ldr.w r7, [sp], #4 800ab0a: 4770 bx lr 0800ab0c : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 800ab0c: b480 push {r7} 800ab0e: b085 sub sp, #20 800ab10: af00 add r7, sp, #0 800ab12: 4603 mov r3, r0 800ab14: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 800ab16: 2300 movs r3, #0 800ab18: 73fb strb r3, [r7, #15] switch (hal_status) 800ab1a: 79fb ldrb r3, [r7, #7] 800ab1c: 2b03 cmp r3, #3 800ab1e: d817 bhi.n 800ab50 800ab20: a201 add r2, pc, #4 @ (adr r2, 800ab28 ) 800ab22: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ab26: bf00 nop 800ab28: 0800ab39 .word 0x0800ab39 800ab2c: 0800ab3f .word 0x0800ab3f 800ab30: 0800ab45 .word 0x0800ab45 800ab34: 0800ab4b .word 0x0800ab4b { case HAL_OK : usb_status = USBD_OK; 800ab38: 2300 movs r3, #0 800ab3a: 73fb strb r3, [r7, #15] break; 800ab3c: e00b b.n 800ab56 case HAL_ERROR : usb_status = USBD_FAIL; 800ab3e: 2303 movs r3, #3 800ab40: 73fb strb r3, [r7, #15] break; 800ab42: e008 b.n 800ab56 case HAL_BUSY : usb_status = USBD_BUSY; 800ab44: 2301 movs r3, #1 800ab46: 73fb strb r3, [r7, #15] break; 800ab48: e005 b.n 800ab56 case HAL_TIMEOUT : usb_status = USBD_FAIL; 800ab4a: 2303 movs r3, #3 800ab4c: 73fb strb r3, [r7, #15] break; 800ab4e: e002 b.n 800ab56 default : usb_status = USBD_FAIL; 800ab50: 2303 movs r3, #3 800ab52: 73fb strb r3, [r7, #15] break; 800ab54: bf00 nop } return usb_status; 800ab56: 7bfb ldrb r3, [r7, #15] } 800ab58: 4618 mov r0, r3 800ab5a: 3714 adds r7, #20 800ab5c: 46bd mov sp, r7 800ab5e: f85d 7b04 ldr.w r7, [sp], #4 800ab62: 4770 bx lr 0800ab64 : 800ab64: 4402 add r2, r0 800ab66: 4603 mov r3, r0 800ab68: 4293 cmp r3, r2 800ab6a: d100 bne.n 800ab6e 800ab6c: 4770 bx lr 800ab6e: f803 1b01 strb.w r1, [r3], #1 800ab72: e7f9 b.n 800ab68 0800ab74 <__libc_init_array>: 800ab74: b570 push {r4, r5, r6, lr} 800ab76: 4d0d ldr r5, [pc, #52] @ (800abac <__libc_init_array+0x38>) 800ab78: 4c0d ldr r4, [pc, #52] @ (800abb0 <__libc_init_array+0x3c>) 800ab7a: 1b64 subs r4, r4, r5 800ab7c: 10a4 asrs r4, r4, #2 800ab7e: 2600 movs r6, #0 800ab80: 42a6 cmp r6, r4 800ab82: d109 bne.n 800ab98 <__libc_init_array+0x24> 800ab84: 4d0b ldr r5, [pc, #44] @ (800abb4 <__libc_init_array+0x40>) 800ab86: 4c0c ldr r4, [pc, #48] @ (800abb8 <__libc_init_array+0x44>) 800ab88: f000 f826 bl 800abd8 <_init> 800ab8c: 1b64 subs r4, r4, r5 800ab8e: 10a4 asrs r4, r4, #2 800ab90: 2600 movs r6, #0 800ab92: 42a6 cmp r6, r4 800ab94: d105 bne.n 800aba2 <__libc_init_array+0x2e> 800ab96: bd70 pop {r4, r5, r6, pc} 800ab98: f855 3b04 ldr.w r3, [r5], #4 800ab9c: 4798 blx r3 800ab9e: 3601 adds r6, #1 800aba0: e7ee b.n 800ab80 <__libc_init_array+0xc> 800aba2: f855 3b04 ldr.w r3, [r5], #4 800aba6: 4798 blx r3 800aba8: 3601 adds r6, #1 800abaa: e7f2 b.n 800ab92 <__libc_init_array+0x1e> 800abac: 0800ac54 .word 0x0800ac54 800abb0: 0800ac54 .word 0x0800ac54 800abb4: 0800ac54 .word 0x0800ac54 800abb8: 0800ac58 .word 0x0800ac58 0800abbc : 800abbc: 440a add r2, r1 800abbe: 4291 cmp r1, r2 800abc0: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 800abc4: d100 bne.n 800abc8 800abc6: 4770 bx lr 800abc8: b510 push {r4, lr} 800abca: f811 4b01 ldrb.w r4, [r1], #1 800abce: f803 4f01 strb.w r4, [r3, #1]! 800abd2: 4291 cmp r1, r2 800abd4: d1f9 bne.n 800abca 800abd6: bd10 pop {r4, pc} 0800abd8 <_init>: 800abd8: b5f8 push {r3, r4, r5, r6, r7, lr} 800abda: bf00 nop 800abdc: bcf8 pop {r3, r4, r5, r6, r7} 800abde: bc08 pop {r3} 800abe0: 469e mov lr, r3 800abe2: 4770 bx lr 0800abe4 <_fini>: 800abe4: b5f8 push {r3, r4, r5, r6, r7, lr} 800abe6: bf00 nop 800abe8: bcf8 pop {r3, r4, r5, r6, r7} 800abea: bc08 pop {r3} 800abec: 469e mov lr, r3 800abee: 4770 bx lr