numpad.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001c4 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000b5d0 080001c4 080001c4 000011c4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000005c 0800b794 0800b794 0000c794 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800b7f0 0800b7f0 0000d1a0 2**0 CONTENTS, READONLY 4 .ARM 00000008 0800b7f0 0800b7f0 0000c7f0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800b7f8 0800b7f8 0000d1a0 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800b7f8 0800b7f8 0000c7f8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 0800b7fc 0800b7fc 0000c7fc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 000001a0 20000000 0800b800 0000d000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 0000173c 200001a0 0800b9a0 0000d1a0 2**2 ALLOC 10 ._user_heap_stack 00000604 200018dc 0800b9a0 0000d8dc 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000d1a0 2**0 CONTENTS, READONLY 12 .debug_info 0001b77c 00000000 00000000 0000d1d0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 000040bb 00000000 00000000 0002894c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000017d0 00000000 00000000 0002ca08 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 0000127f 00000000 00000000 0002e1d8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0002609f 00000000 00000000 0002f457 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001e97c 00000000 00000000 000554f6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000d80c4 00000000 00000000 00073e72 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0014bf36 2**0 CONTENTS, READONLY 20 .debug_frame 00006430 00000000 00000000 0014bf7c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 0000005e 00000000 00000000 001523ac 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001c4 <__do_global_dtors_aux>: 80001c4: b510 push {r4, lr} 80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>) 80001c8: 7823 ldrb r3, [r4, #0] 80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16> 80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>) 80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12> 80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>) 80001d2: f3af 8000 nop.w 80001d6: 2301 movs r3, #1 80001d8: 7023 strb r3, [r4, #0] 80001da: bd10 pop {r4, pc} 80001dc: 200001a0 .word 0x200001a0 80001e0: 00000000 .word 0x00000000 80001e4: 0800b77c .word 0x0800b77c 080001e8 : 80001e8: b508 push {r3, lr} 80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 ) 80001ec: b11b cbz r3, 80001f6 80001ee: 4903 ldr r1, [pc, #12] @ (80001fc ) 80001f0: 4803 ldr r0, [pc, #12] @ (8000200 ) 80001f2: f3af 8000 nop.w 80001f6: bd08 pop {r3, pc} 80001f8: 00000000 .word 0x00000000 80001fc: 200001a4 .word 0x200001a4 8000200: 0800b77c .word 0x0800b77c 08000204 <__aeabi_uldivmod>: 8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18> 8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18> 8000208: 2900 cmp r1, #0 800020a: bf08 it eq 800020c: 2800 cmpeq r0, #0 800020e: bf1c itt ne 8000210: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000214: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000218: f000 b988 b.w 800052c <__aeabi_idiv0> 800021c: f1ad 0c08 sub.w ip, sp, #8 8000220: e96d ce04 strd ip, lr, [sp, #-16]! 8000224: f000 f806 bl 8000234 <__udivmoddi4> 8000228: f8dd e004 ldr.w lr, [sp, #4] 800022c: e9dd 2302 ldrd r2, r3, [sp, #8] 8000230: b004 add sp, #16 8000232: 4770 bx lr 08000234 <__udivmoddi4>: 8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000238: 9d08 ldr r5, [sp, #32] 800023a: 468e mov lr, r1 800023c: 4604 mov r4, r0 800023e: 4688 mov r8, r1 8000240: 2b00 cmp r3, #0 8000242: d14a bne.n 80002da <__udivmoddi4+0xa6> 8000244: 428a cmp r2, r1 8000246: 4617 mov r7, r2 8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc> 800024a: fab2 f682 clz r6, r2 800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30> 8000250: f1c6 0320 rsb r3, r6, #32 8000254: fa01 f806 lsl.w r8, r1, r6 8000258: fa20 f303 lsr.w r3, r0, r3 800025c: 40b7 lsls r7, r6 800025e: ea43 0808 orr.w r8, r3, r8 8000262: 40b4 lsls r4, r6 8000264: ea4f 4e17 mov.w lr, r7, lsr #16 8000268: fa1f fc87 uxth.w ip, r7 800026c: fbb8 f1fe udiv r1, r8, lr 8000270: 0c23 lsrs r3, r4, #16 8000272: fb0e 8811 mls r8, lr, r1, r8 8000276: ea43 4308 orr.w r3, r3, r8, lsl #16 800027a: fb01 f20c mul.w r2, r1, ip 800027e: 429a cmp r2, r3 8000280: d909 bls.n 8000296 <__udivmoddi4+0x62> 8000282: 18fb adds r3, r7, r3 8000284: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c> 800028c: 429a cmp r2, r3 800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c> 8000292: 3902 subs r1, #2 8000294: 443b add r3, r7 8000296: 1a9a subs r2, r3, r2 8000298: b2a3 uxth r3, r4 800029a: fbb2 f0fe udiv r0, r2, lr 800029e: fb0e 2210 mls r2, lr, r0, r2 80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16 80002a6: fb00 fc0c mul.w ip, r0, ip 80002aa: 459c cmp ip, r3 80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e> 80002ae: 18fb adds r3, r7, r3 80002b0: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230> 80002b8: 459c cmp ip, r3 80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230> 80002be: 443b add r3, r7 80002c0: 3802 subs r0, #2 80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16 80002c6: eba3 030c sub.w r3, r3, ip 80002ca: 2100 movs r1, #0 80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2> 80002ce: 40f3 lsrs r3, r6 80002d0: 2200 movs r2, #0 80002d2: e9c5 3200 strd r3, r2, [r5] 80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002da: 428b cmp r3, r1 80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6> 80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0> 80002e0: e9c5 0100 strd r0, r1, [r5] 80002e4: 2100 movs r1, #0 80002e6: 4608 mov r0, r1 80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2> 80002ea: fab3 f183 clz r1, r3 80002ee: 2900 cmp r1, #0 80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c> 80002f2: 4573 cmp r3, lr 80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8> 80002f6: 4282 cmp r2, r0 80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2> 80002fc: 1a84 subs r4, r0, r2 80002fe: eb6e 0203 sbc.w r2, lr, r3 8000302: 2001 movs r0, #1 8000304: 4690 mov r8, r2 8000306: 2d00 cmp r5, #0 8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2> 800030a: e9c5 4800 strd r4, r8, [r5] 800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2> 8000310: 2a00 cmp r2, #0 8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202> 8000316: fab2 f682 clz r6, r2 800031a: 2e00 cmp r6, #0 800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234> 8000320: 1a8a subs r2, r1, r2 8000322: 0c03 lsrs r3, r0, #16 8000324: ea4f 4e17 mov.w lr, r7, lsr #16 8000328: b280 uxth r0, r0 800032a: b2bc uxth r4, r7 800032c: 2101 movs r1, #1 800032e: fbb2 fcfe udiv ip, r2, lr 8000332: fb0e 221c mls r2, lr, ip, r2 8000336: ea43 4302 orr.w r3, r3, r2, lsl #16 800033a: fb04 f20c mul.w r2, r4, ip 800033e: 429a cmp r2, r3 8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e> 8000342: 18fb adds r3, r7, r3 8000344: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c> 800034a: 429a cmp r2, r3 800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc> 8000350: 46c4 mov ip, r8 8000352: 1a9b subs r3, r3, r2 8000354: fbb3 f2fe udiv r2, r3, lr 8000358: fb0e 3312 mls r3, lr, r2, r3 800035c: ea40 4303 orr.w r3, r0, r3, lsl #16 8000360: fb02 f404 mul.w r4, r2, r4 8000364: 429c cmp r4, r3 8000366: d907 bls.n 8000378 <__udivmoddi4+0x144> 8000368: 18fb adds r3, r7, r3 800036a: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142> 8000370: 429c cmp r4, r3 8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6> 8000376: 4602 mov r2, r0 8000378: 1b1b subs r3, r3, r4 800037a: ea42 400c orr.w r0, r2, ip, lsl #16 800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98> 8000380: f1c1 0620 rsb r6, r1, #32 8000384: 408b lsls r3, r1 8000386: fa22 f706 lsr.w r7, r2, r6 800038a: 431f orrs r7, r3 800038c: fa0e f401 lsl.w r4, lr, r1 8000390: fa20 f306 lsr.w r3, r0, r6 8000394: fa2e fe06 lsr.w lr, lr, r6 8000398: ea4f 4917 mov.w r9, r7, lsr #16 800039c: 4323 orrs r3, r4 800039e: fa00 f801 lsl.w r8, r0, r1 80003a2: fa1f fc87 uxth.w ip, r7 80003a6: fbbe f0f9 udiv r0, lr, r9 80003aa: 0c1c lsrs r4, r3, #16 80003ac: fb09 ee10 mls lr, r9, r0, lr 80003b0: ea44 440e orr.w r4, r4, lr, lsl #16 80003b4: fb00 fe0c mul.w lr, r0, ip 80003b8: 45a6 cmp lr, r4 80003ba: fa02 f201 lsl.w r2, r2, r1 80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0> 80003c0: 193c adds r4, r7, r4 80003c2: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce> 80003ca: 45a6 cmp lr, r4 80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce> 80003d0: 3802 subs r0, #2 80003d2: 443c add r4, r7 80003d4: eba4 040e sub.w r4, r4, lr 80003d8: fa1f fe83 uxth.w lr, r3 80003dc: fbb4 f3f9 udiv r3, r4, r9 80003e0: fb09 4413 mls r4, r9, r3, r4 80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003e8: fb03 fc0c mul.w ip, r3, ip 80003ec: 45a4 cmp ip, r4 80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce> 80003f0: 193c adds r4, r7, r4 80003f2: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca> 80003fa: 45a4 cmp ip, r4 80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca> 80003fe: 3b02 subs r3, #2 8000400: 443c add r4, r7 8000402: ea43 4000 orr.w r0, r3, r0, lsl #16 8000406: eba4 040c sub.w r4, r4, ip 800040a: fba0 ec02 umull lr, ip, r0, r2 800040e: 4564 cmp r4, ip 8000410: 4673 mov r3, lr 8000412: 46e1 mov r9, ip 8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8> 8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4> 8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe> 800041a: ebb8 0203 subs.w r2, r8, r3 800041e: eb64 0409 sbc.w r4, r4, r9 8000422: fa04 f606 lsl.w r6, r4, r6 8000426: fa22 f301 lsr.w r3, r2, r1 800042a: 431e orrs r6, r3 800042c: 40cc lsrs r4, r1 800042e: e9c5 6400 strd r6, r4, [r5] 8000432: 2100 movs r1, #0 8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2> 8000436: fbb1 fcf2 udiv ip, r1, r2 800043a: 0c01 lsrs r1, r0, #16 800043c: ea41 410e orr.w r1, r1, lr, lsl #16 8000440: b280 uxth r0, r0 8000442: ea40 4201 orr.w r2, r0, r1, lsl #16 8000446: 463b mov r3, r7 8000448: 4638 mov r0, r7 800044a: 463c mov r4, r7 800044c: 46b8 mov r8, r7 800044e: 46be mov lr, r7 8000450: 2620 movs r6, #32 8000452: fbb1 f1f7 udiv r1, r1, r7 8000456: eba2 0208 sub.w r2, r2, r8 800045a: ea41 410c orr.w r1, r1, ip, lsl #16 800045e: e766 b.n 800032e <__udivmoddi4+0xfa> 8000460: 4601 mov r1, r0 8000462: e718 b.n 8000296 <__udivmoddi4+0x62> 8000464: 4610 mov r0, r2 8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e> 8000468: f1c6 0220 rsb r2, r6, #32 800046c: fa2e f302 lsr.w r3, lr, r2 8000470: 40b7 lsls r7, r6 8000472: 40b1 lsls r1, r6 8000474: fa20 f202 lsr.w r2, r0, r2 8000478: ea4f 4e17 mov.w lr, r7, lsr #16 800047c: 430a orrs r2, r1 800047e: fbb3 f8fe udiv r8, r3, lr 8000482: b2bc uxth r4, r7 8000484: fb0e 3318 mls r3, lr, r8, r3 8000488: 0c11 lsrs r1, r2, #16 800048a: ea41 4103 orr.w r1, r1, r3, lsl #16 800048e: fb08 f904 mul.w r9, r8, r4 8000492: 40b0 lsls r0, r6 8000494: 4589 cmp r9, r1 8000496: ea4f 4310 mov.w r3, r0, lsr #16 800049a: b280 uxth r0, r0 800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8> 800049e: 1879 adds r1, r7, r1 80004a0: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276> 80004a6: 4589 cmp r9, r1 80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6> 80004aa: eba1 0109 sub.w r1, r1, r9 80004ae: fbb1 f9fe udiv r9, r1, lr 80004b2: fb09 f804 mul.w r8, r9, r4 80004b6: fb0e 1119 mls r1, lr, r9, r1 80004ba: b292 uxth r2, r2 80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16 80004c0: 4542 cmp r2, r8 80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4> 80004c4: 18ba adds r2, r7, r2 80004c6: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222> 80004cc: 4542 cmp r2, r8 80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222> 80004d0: f1a9 0102 sub.w r1, r9, #2 80004d4: 443a add r2, r7 80004d6: e7be b.n 8000456 <__udivmoddi4+0x222> 80004d8: 45f0 cmp r8, lr 80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4> 80004dc: ebbe 0302 subs.w r3, lr, r2 80004e0: eb6c 0c07 sbc.w ip, ip, r7 80004e4: 3801 subs r0, #1 80004e6: 46e1 mov r9, ip 80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4> 80004ea: eba7 0909 sub.w r9, r7, r9 80004ee: 4449 add r1, r9 80004f0: f1a8 0c02 sub.w ip, r8, #2 80004f4: fbb1 f9fe udiv r9, r1, lr 80004f8: fb09 f804 mul.w r8, r9, r4 80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282> 80004fe: 4673 mov r3, lr 8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce> 8000502: 4650 mov r0, sl 8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0> 8000506: 4608 mov r0, r1 8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2> 800050a: 443b add r3, r7 800050c: 3a02 subs r2, #2 800050e: e733 b.n 8000378 <__udivmoddi4+0x144> 8000510: f1ac 0c02 sub.w ip, ip, #2 8000514: 443b add r3, r7 8000516: e71c b.n 8000352 <__udivmoddi4+0x11e> 8000518: 4649 mov r1, r9 800051a: e79c b.n 8000456 <__udivmoddi4+0x222> 800051c: eba1 0109 sub.w r1, r1, r9 8000520: 46c4 mov ip, r8 8000522: fbb1 f9fe udiv r9, r1, lr 8000526: fb09 f804 mul.w r8, r9, r4 800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282> 0800052c <__aeabi_idiv0>: 800052c: 4770 bx lr 800052e: bf00 nop 08000530 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 8000530: b580 push {r7, lr} 8000532: b082 sub sp, #8 8000534: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8000536: 2300 movs r3, #0 8000538: 607b str r3, [r7, #4] 800053a: 4b2f ldr r3, [pc, #188] @ (80005f8 ) 800053c: 6b1b ldr r3, [r3, #48] @ 0x30 800053e: 4a2e ldr r2, [pc, #184] @ (80005f8 ) 8000540: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000544: 6313 str r3, [r2, #48] @ 0x30 8000546: 4b2c ldr r3, [pc, #176] @ (80005f8 ) 8000548: 6b1b ldr r3, [r3, #48] @ 0x30 800054a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800054e: 607b str r3, [r7, #4] 8000550: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); 8000552: 2300 movs r3, #0 8000554: 603b str r3, [r7, #0] 8000556: 4b28 ldr r3, [pc, #160] @ (80005f8 ) 8000558: 6b1b ldr r3, [r3, #48] @ 0x30 800055a: 4a27 ldr r2, [pc, #156] @ (80005f8 ) 800055c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8000560: 6313 str r3, [r2, #48] @ 0x30 8000562: 4b25 ldr r3, [pc, #148] @ (80005f8 ) 8000564: 6b1b ldr r3, [r3, #48] @ 0x30 8000566: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800056a: 603b str r3, [r7, #0] 800056c: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); 800056e: 2200 movs r2, #0 8000570: 2100 movs r1, #0 8000572: 200b movs r0, #11 8000574: f001 fdb1 bl 80020da HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8000578: 200b movs r0, #11 800057a: f001 fdca bl 8002112 /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); 800057e: 2200 movs r2, #0 8000580: 2100 movs r1, #0 8000582: 200d movs r0, #13 8000584: f001 fda9 bl 80020da HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8000588: 200d movs r0, #13 800058a: f001 fdc2 bl 8002112 /* DMA1_Stream4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0); 800058e: 2200 movs r2, #0 8000590: 2100 movs r1, #0 8000592: 200f movs r0, #15 8000594: f001 fda1 bl 80020da HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); 8000598: 200f movs r0, #15 800059a: f001 fdba bl 8002112 /* DMA1_Stream5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); 800059e: 2200 movs r2, #0 80005a0: 2100 movs r1, #0 80005a2: 2010 movs r0, #16 80005a4: f001 fd99 bl 80020da HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); 80005a8: 2010 movs r0, #16 80005aa: f001 fdb2 bl 8002112 /* DMA1_Stream6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0); 80005ae: 2200 movs r2, #0 80005b0: 2100 movs r1, #0 80005b2: 2011 movs r0, #17 80005b4: f001 fd91 bl 80020da HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); 80005b8: 2011 movs r0, #17 80005ba: f001 fdaa bl 8002112 /* DMA1_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0); 80005be: 2200 movs r2, #0 80005c0: 2100 movs r1, #0 80005c2: 202f movs r0, #47 @ 0x2f 80005c4: f001 fd89 bl 80020da HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); 80005c8: 202f movs r0, #47 @ 0x2f 80005ca: f001 fda2 bl 8002112 /* DMA2_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); 80005ce: 2200 movs r2, #0 80005d0: 2100 movs r1, #0 80005d2: 203a movs r0, #58 @ 0x3a 80005d4: f001 fd81 bl 80020da HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); 80005d8: 203a movs r0, #58 @ 0x3a 80005da: f001 fd9a bl 8002112 /* DMA2_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 80005de: 2200 movs r2, #0 80005e0: 2100 movs r1, #0 80005e2: 2046 movs r0, #70 @ 0x46 80005e4: f001 fd79 bl 80020da HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 80005e8: 2046 movs r0, #70 @ 0x46 80005ea: f001 fd92 bl 8002112 } 80005ee: bf00 nop 80005f0: 3708 adds r7, #8 80005f2: 46bd mov sp, r7 80005f4: bd80 pop {r7, pc} 80005f6: bf00 nop 80005f8: 40023800 .word 0x40023800 080005fc : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 80005fc: b580 push {r7, lr} 80005fe: b08a sub sp, #40 @ 0x28 8000600: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000602: f107 0314 add.w r3, r7, #20 8000606: 2200 movs r2, #0 8000608: 601a str r2, [r3, #0] 800060a: 605a str r2, [r3, #4] 800060c: 609a str r2, [r3, #8] 800060e: 60da str r2, [r3, #12] 8000610: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8000612: 2300 movs r3, #0 8000614: 613b str r3, [r7, #16] 8000616: 4b45 ldr r3, [pc, #276] @ (800072c ) 8000618: 6b1b ldr r3, [r3, #48] @ 0x30 800061a: 4a44 ldr r2, [pc, #272] @ (800072c ) 800061c: f043 0380 orr.w r3, r3, #128 @ 0x80 8000620: 6313 str r3, [r2, #48] @ 0x30 8000622: 4b42 ldr r3, [pc, #264] @ (800072c ) 8000624: 6b1b ldr r3, [r3, #48] @ 0x30 8000626: f003 0380 and.w r3, r3, #128 @ 0x80 800062a: 613b str r3, [r7, #16] 800062c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800062e: 2300 movs r3, #0 8000630: 60fb str r3, [r7, #12] 8000632: 4b3e ldr r3, [pc, #248] @ (800072c ) 8000634: 6b1b ldr r3, [r3, #48] @ 0x30 8000636: 4a3d ldr r2, [pc, #244] @ (800072c ) 8000638: f043 0301 orr.w r3, r3, #1 800063c: 6313 str r3, [r2, #48] @ 0x30 800063e: 4b3b ldr r3, [pc, #236] @ (800072c ) 8000640: 6b1b ldr r3, [r3, #48] @ 0x30 8000642: f003 0301 and.w r3, r3, #1 8000646: 60fb str r3, [r7, #12] 8000648: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); 800064a: 2300 movs r3, #0 800064c: 60bb str r3, [r7, #8] 800064e: 4b37 ldr r3, [pc, #220] @ (800072c ) 8000650: 6b1b ldr r3, [r3, #48] @ 0x30 8000652: 4a36 ldr r2, [pc, #216] @ (800072c ) 8000654: f043 0304 orr.w r3, r3, #4 8000658: 6313 str r3, [r2, #48] @ 0x30 800065a: 4b34 ldr r3, [pc, #208] @ (800072c ) 800065c: 6b1b ldr r3, [r3, #48] @ 0x30 800065e: f003 0304 and.w r3, r3, #4 8000662: 60bb str r3, [r7, #8] 8000664: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000666: 2300 movs r3, #0 8000668: 607b str r3, [r7, #4] 800066a: 4b30 ldr r3, [pc, #192] @ (800072c ) 800066c: 6b1b ldr r3, [r3, #48] @ 0x30 800066e: 4a2f ldr r2, [pc, #188] @ (800072c ) 8000670: f043 0302 orr.w r3, r3, #2 8000674: 6313 str r3, [r2, #48] @ 0x30 8000676: 4b2d ldr r3, [pc, #180] @ (800072c ) 8000678: 6b1b ldr r3, [r3, #48] @ 0x30 800067a: f003 0302 and.w r3, r3, #2 800067e: 607b str r3, [r7, #4] 8000680: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000682: 2300 movs r3, #0 8000684: 603b str r3, [r7, #0] 8000686: 4b29 ldr r3, [pc, #164] @ (800072c ) 8000688: 6b1b ldr r3, [r3, #48] @ 0x30 800068a: 4a28 ldr r2, [pc, #160] @ (800072c ) 800068c: f043 0308 orr.w r3, r3, #8 8000690: 6313 str r3, [r2, #48] @ 0x30 8000692: 4b26 ldr r3, [pc, #152] @ (800072c ) 8000694: 6b1b ldr r3, [r3, #48] @ 0x30 8000696: f003 0308 and.w r3, r3, #8 800069a: 603b str r3, [r7, #0] 800069c: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET); 800069e: 2200 movs r2, #0 80006a0: f44f 7170 mov.w r1, #960 @ 0x3c0 80006a4: 4822 ldr r0, [pc, #136] @ (8000730 ) 80006a6: f002 fafd bl 8002ca4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); 80006aa: 2200 movs r2, #0 80006ac: f44f 7180 mov.w r1, #256 @ 0x100 80006b0: 4820 ldr r0, [pc, #128] @ (8000734 ) 80006b2: f002 faf7 bl 8002ca4 /*Configure GPIO pins : PC4 PC5 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80006b6: 2330 movs r3, #48 @ 0x30 80006b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006ba: 2300 movs r3, #0 80006bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006be: 2302 movs r3, #2 80006c0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006c2: f107 0314 add.w r3, r7, #20 80006c6: 4619 mov r1, r3 80006c8: 4819 ldr r0, [pc, #100] @ (8000730 ) 80006ca: f002 f93f bl 800294c /*Configure GPIO pins : PB0 PB1 PB2 PB10 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10; 80006ce: f240 4307 movw r3, #1031 @ 0x407 80006d2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006d4: 2300 movs r3, #0 80006d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006d8: 2302 movs r3, #2 80006da: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80006dc: f107 0314 add.w r3, r7, #20 80006e0: 4619 mov r1, r3 80006e2: 4815 ldr r0, [pc, #84] @ (8000738 ) 80006e4: f002 f932 bl 800294c /*Configure GPIO pins : PC6 PC7 PC8 PC9 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 80006e8: f44f 7370 mov.w r3, #960 @ 0x3c0 80006ec: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006ee: 2301 movs r3, #1 80006f0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80006f2: 2300 movs r3, #0 80006f4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80006f6: 2300 movs r3, #0 80006f8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006fa: f107 0314 add.w r3, r7, #20 80006fe: 4619 mov r1, r3 8000700: 480b ldr r0, [pc, #44] @ (8000730 ) 8000702: f002 f923 bl 800294c /*Configure GPIO pin : PA8 */ GPIO_InitStruct.Pin = GPIO_PIN_8; 8000706: f44f 7380 mov.w r3, #256 @ 0x100 800070a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800070c: 2301 movs r3, #1 800070e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000710: 2300 movs r3, #0 8000712: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000714: 2300 movs r3, #0 8000716: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000718: f107 0314 add.w r3, r7, #20 800071c: 4619 mov r1, r3 800071e: 4805 ldr r0, [pc, #20] @ (8000734 ) 8000720: f002 f914 bl 800294c } 8000724: bf00 nop 8000726: 3728 adds r7, #40 @ 0x28 8000728: 46bd mov sp, r7 800072a: bd80 pop {r7, pc} 800072c: 40023800 .word 0x40023800 8000730: 40020800 .word 0x40020800 8000734: 40020000 .word 0x40020000 8000738: 40020400 .word 0x40020400 0800073c : I2C_HandleTypeDef hi2c1; /* I2C1 init function */ void MX_I2C1_Init(void) { 800073c: b580 push {r7, lr} 800073e: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8000740: 4b12 ldr r3, [pc, #72] @ (800078c ) 8000742: 4a13 ldr r2, [pc, #76] @ (8000790 ) 8000744: 601a str r2, [r3, #0] hi2c1.Init.ClockSpeed = 100000; 8000746: 4b11 ldr r3, [pc, #68] @ (800078c ) 8000748: 4a12 ldr r2, [pc, #72] @ (8000794 ) 800074a: 605a str r2, [r3, #4] hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; 800074c: 4b0f ldr r3, [pc, #60] @ (800078c ) 800074e: 2200 movs r2, #0 8000750: 609a str r2, [r3, #8] hi2c1.Init.OwnAddress1 = 0; 8000752: 4b0e ldr r3, [pc, #56] @ (800078c ) 8000754: 2200 movs r2, #0 8000756: 60da str r2, [r3, #12] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8000758: 4b0c ldr r3, [pc, #48] @ (800078c ) 800075a: f44f 4280 mov.w r2, #16384 @ 0x4000 800075e: 611a str r2, [r3, #16] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000760: 4b0a ldr r3, [pc, #40] @ (800078c ) 8000762: 2200 movs r2, #0 8000764: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2 = 0; 8000766: 4b09 ldr r3, [pc, #36] @ (800078c ) 8000768: 2200 movs r2, #0 800076a: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 800076c: 4b07 ldr r3, [pc, #28] @ (800078c ) 800076e: 2200 movs r2, #0 8000770: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8000772: 4b06 ldr r3, [pc, #24] @ (800078c ) 8000774: 2200 movs r2, #0 8000776: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8000778: 4804 ldr r0, [pc, #16] @ (800078c ) 800077a: f002 faad bl 8002cd8 800077e: 4603 mov r3, r0 8000780: 2b00 cmp r3, #0 8000782: d001 beq.n 8000788 { Error_Handler(); 8000784: f000 fd86 bl 8001294 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8000788: bf00 nop 800078a: bd80 pop {r7, pc} 800078c: 200001bc .word 0x200001bc 8000790: 40005400 .word 0x40005400 8000794: 000186a0 .word 0x000186a0 08000798 : void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) { 8000798: b580 push {r7, lr} 800079a: b08a sub sp, #40 @ 0x28 800079c: af00 add r7, sp, #0 800079e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007a0: f107 0314 add.w r3, r7, #20 80007a4: 2200 movs r2, #0 80007a6: 601a str r2, [r3, #0] 80007a8: 605a str r2, [r3, #4] 80007aa: 609a str r2, [r3, #8] 80007ac: 60da str r2, [r3, #12] 80007ae: 611a str r2, [r3, #16] if(i2cHandle->Instance==I2C1) 80007b0: 687b ldr r3, [r7, #4] 80007b2: 681b ldr r3, [r3, #0] 80007b4: 4a19 ldr r2, [pc, #100] @ (800081c ) 80007b6: 4293 cmp r3, r2 80007b8: d12b bne.n 8000812 { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80007ba: 2300 movs r3, #0 80007bc: 613b str r3, [r7, #16] 80007be: 4b18 ldr r3, [pc, #96] @ (8000820 ) 80007c0: 6b1b ldr r3, [r3, #48] @ 0x30 80007c2: 4a17 ldr r2, [pc, #92] @ (8000820 ) 80007c4: f043 0302 orr.w r3, r3, #2 80007c8: 6313 str r3, [r2, #48] @ 0x30 80007ca: 4b15 ldr r3, [pc, #84] @ (8000820 ) 80007cc: 6b1b ldr r3, [r3, #48] @ 0x30 80007ce: f003 0302 and.w r3, r3, #2 80007d2: 613b str r3, [r7, #16] 80007d4: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80007d6: 23c0 movs r3, #192 @ 0xc0 80007d8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80007da: 2312 movs r3, #18 80007dc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80007de: 2300 movs r3, #0 80007e0: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80007e2: 2303 movs r3, #3 80007e4: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 80007e6: 2304 movs r3, #4 80007e8: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80007ea: f107 0314 add.w r3, r7, #20 80007ee: 4619 mov r1, r3 80007f0: 480c ldr r0, [pc, #48] @ (8000824 ) 80007f2: f002 f8ab bl 800294c /* I2C1 clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 80007f6: 2300 movs r3, #0 80007f8: 60fb str r3, [r7, #12] 80007fa: 4b09 ldr r3, [pc, #36] @ (8000820 ) 80007fc: 6c1b ldr r3, [r3, #64] @ 0x40 80007fe: 4a08 ldr r2, [pc, #32] @ (8000820 ) 8000800: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000804: 6413 str r3, [r2, #64] @ 0x40 8000806: 4b06 ldr r3, [pc, #24] @ (8000820 ) 8000808: 6c1b ldr r3, [r3, #64] @ 0x40 800080a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800080e: 60fb str r3, [r7, #12] 8000810: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8000812: bf00 nop 8000814: 3728 adds r7, #40 @ 0x28 8000816: 46bd mov sp, r7 8000818: bd80 pop {r7, pc} 800081a: bf00 nop 800081c: 40005400 .word 0x40005400 8000820: 40023800 .word 0x40023800 8000824: 40020400 .word 0x40020400 08000828 : volatile uint8_t tail; // accessed in ISR volatile uint8_t count; // optional, only if needed } PacketQueue; // Initialize void pq_init(PacketQueue *q){ 8000828: b480 push {r7} 800082a: b083 sub sp, #12 800082c: af00 add r7, sp, #0 800082e: 6078 str r0, [r7, #4] q->head = 0; 8000830: 687b ldr r3, [r7, #4] 8000832: 2200 movs r2, #0 8000834: f883 2180 strb.w r2, [r3, #384] @ 0x180 q->tail = 0; 8000838: 687b ldr r3, [r7, #4] 800083a: 2200 movs r2, #0 800083c: f883 2181 strb.w r2, [r3, #385] @ 0x181 q->count = 0; 8000840: 687b ldr r3, [r7, #4] 8000842: 2200 movs r2, #0 8000844: f883 2182 strb.w r2, [r3, #386] @ 0x182 } 8000848: bf00 nop 800084a: 370c adds r7, #12 800084c: 46bd mov sp, r7 800084e: f85d 7b04 ldr.w r7, [sp], #4 8000852: 4770 bx lr 08000854 : // Called from ISR bool pq_push(PacketQueue *q, const uint8_t packet[PACKET_SIZE]){ 8000854: b580 push {r7, lr} 8000856: b084 sub sp, #16 8000858: af00 add r7, sp, #0 800085a: 6078 str r0, [r7, #4] 800085c: 6039 str r1, [r7, #0] uint8_t nextTail = (q->tail + 1) % QUEUE_CAPACITY; 800085e: 687b ldr r3, [r7, #4] 8000860: f893 3181 ldrb.w r3, [r3, #385] @ 0x181 8000864: b2db uxtb r3, r3 8000866: 3301 adds r3, #1 8000868: 425a negs r2, r3 800086a: f003 031f and.w r3, r3, #31 800086e: f002 021f and.w r2, r2, #31 8000872: bf58 it pl 8000874: 4253 negpl r3, r2 8000876: 73fb strb r3, [r7, #15] if(nextTail == q->head) return false; // queue full 8000878: 687b ldr r3, [r7, #4] 800087a: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 800087e: b2db uxtb r3, r3 8000880: 7bfa ldrb r2, [r7, #15] 8000882: 429a cmp r2, r3 8000884: d101 bne.n 800088a 8000886: 2300 movs r3, #0 8000888: e014 b.n 80008b4 memcpy(q->data[q->tail], packet, PACKET_SIZE); 800088a: 687b ldr r3, [r7, #4] 800088c: f893 3181 ldrb.w r3, [r3, #385] @ 0x181 8000890: b2db uxtb r3, r3 8000892: 461a mov r2, r3 8000894: 4613 mov r3, r2 8000896: 005b lsls r3, r3, #1 8000898: 4413 add r3, r2 800089a: 009b lsls r3, r3, #2 800089c: 687a ldr r2, [r7, #4] 800089e: 4413 add r3, r2 80008a0: 220c movs r2, #12 80008a2: 6839 ldr r1, [r7, #0] 80008a4: 4618 mov r0, r3 80008a6: f00a ff5b bl 800b760 q->tail = nextTail; 80008aa: 687b ldr r3, [r7, #4] 80008ac: 7bfa ldrb r2, [r7, #15] 80008ae: f883 2181 strb.w r2, [r3, #385] @ 0x181 return true; 80008b2: 2301 movs r3, #1 } 80008b4: 4618 mov r0, r3 80008b6: 3710 adds r7, #16 80008b8: 46bd mov sp, r7 80008ba: bd80 pop {r7, pc} 080008bc : // Called from main bool pq_pop(PacketQueue *q, uint8_t out_packet[PACKET_SIZE]){ 80008bc: b580 push {r7, lr} 80008be: b082 sub sp, #8 80008c0: af00 add r7, sp, #0 80008c2: 6078 str r0, [r7, #4] 80008c4: 6039 str r1, [r7, #0] if(q->head == q->tail) return false; // queue empty 80008c6: 687b ldr r3, [r7, #4] 80008c8: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 80008cc: b2da uxtb r2, r3 80008ce: 687b ldr r3, [r7, #4] 80008d0: f893 3181 ldrb.w r3, [r3, #385] @ 0x181 80008d4: b2db uxtb r3, r3 80008d6: 429a cmp r2, r3 80008d8: d101 bne.n 80008de 80008da: 2300 movs r3, #0 80008dc: e020 b.n 8000920 memcpy(out_packet, q->data[q->head], PACKET_SIZE); 80008de: 687b ldr r3, [r7, #4] 80008e0: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 80008e4: b2db uxtb r3, r3 80008e6: 461a mov r2, r3 80008e8: 4613 mov r3, r2 80008ea: 005b lsls r3, r3, #1 80008ec: 4413 add r3, r2 80008ee: 009b lsls r3, r3, #2 80008f0: 687a ldr r2, [r7, #4] 80008f2: 4413 add r3, r2 80008f4: 220c movs r2, #12 80008f6: 4619 mov r1, r3 80008f8: 6838 ldr r0, [r7, #0] 80008fa: f00a ff31 bl 800b760 q->head = (q->head + 1) % QUEUE_CAPACITY; 80008fe: 687b ldr r3, [r7, #4] 8000900: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 8000904: b2db uxtb r3, r3 8000906: 3301 adds r3, #1 8000908: 425a negs r2, r3 800090a: f003 031f and.w r3, r3, #31 800090e: f002 021f and.w r2, r2, #31 8000912: bf58 it pl 8000914: 4253 negpl r3, r2 8000916: b2da uxtb r2, r3 8000918: 687b ldr r3, [r7, #4] 800091a: f883 2180 strb.w r2, [r3, #384] @ 0x180 return true; 800091e: 2301 movs r3, #1 } 8000920: 4618 mov r0, r3 8000922: 3708 adds r7, #8 8000924: 46bd mov sp, r7 8000926: bd80 pop {r7, pc} 08000928
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000928: b580 push {r7, lr} 800092a: b088 sub sp, #32 800092c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800092e: f001 fa63 bl 8001df8 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000932: f000 f9ff bl 8000d34 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000936: f7ff fe61 bl 80005fc MX_DMA_Init(); 800093a: f7ff fdf9 bl 8000530 MX_TIM2_Init(); 800093e: f000 fd9b bl 8001478 MX_TIM3_Init(); 8000942: f000 fdf1 bl 8001528 MX_UART4_Init(); 8000946: f000 fec3 bl 80016d0 MX_UART5_Init(); 800094a: f000 feeb bl 8001724 MX_USART1_UART_Init(); 800094e: f000 ff13 bl 8001778 MX_USART2_UART_Init(); 8000952: f000 ff3b bl 80017cc MX_I2C1_Init(); 8000956: f7ff fef1 bl 800073c MX_USB_DEVICE_Init(); 800095a: f00a fa27 bl 800adac /* USER CODE BEGIN 2 */ //Enable UART RX DMA for all ports HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 800095e: 2210 movs r2, #16 8000960: 4954 ldr r1, [pc, #336] @ (8000ab4 ) 8000962: 4855 ldr r0, [pc, #340] @ (8000ab8 ) 8000964: f006 f828 bl 80069b8 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000968: 2210 movs r2, #16 800096a: 4954 ldr r1, [pc, #336] @ (8000abc ) 800096c: 4854 ldr r0, [pc, #336] @ (8000ac0 ) 800096e: f006 f823 bl 80069b8 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000972: 2210 movs r2, #16 8000974: 4953 ldr r1, [pc, #332] @ (8000ac4 ) 8000976: 4854 ldr r0, [pc, #336] @ (8000ac8 ) 8000978: f006 f81e bl 80069b8 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 800097c: 2210 movs r2, #16 800097e: 4953 ldr r1, [pc, #332] @ (8000acc ) 8000980: 4853 ldr r0, [pc, #332] @ (8000ad0 ) 8000982: f006 f819 bl 80069b8 // Start TIM3 encoder (PA6/PA7) so we can read encoder delta HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL); 8000986: 213c movs r1, #60 @ 0x3c 8000988: 4852 ldr r0, [pc, #328] @ (8000ad4 ) 800098a: f005 fa1b bl 8005dc4 LAST_ENCODER_COUNT = __HAL_TIM_GET_COUNTER(&htim3); 800098e: 4b51 ldr r3, [pc, #324] @ (8000ad4 ) 8000990: 681b ldr r3, [r3, #0] 8000992: 6a5b ldr r3, [r3, #36] @ 0x24 8000994: 461a mov r2, r3 8000996: 4b50 ldr r3, [pc, #320] @ (8000ad8 ) 8000998: 601a str r2, [r3, #0] //Prealloc Kestate matrix memset(KEYSTATE, 0, sizeof(KEYSTATE)); 800099a: 221e movs r2, #30 800099c: 2100 movs r1, #0 800099e: 484f ldr r0, [pc, #316] @ (8000adc ) 80009a0: f00a feb2 bl 800b708 pq_init(&huart1q); 80009a4: 484e ldr r0, [pc, #312] @ (8000ae0 ) 80009a6: f7ff ff3f bl 8000828 pq_init(&huart2q); 80009aa: 484e ldr r0, [pc, #312] @ (8000ae4 ) 80009ac: f7ff ff3c bl 8000828 pq_init(&huart4q); 80009b0: 484d ldr r0, [pc, #308] @ (8000ae8 ) 80009b2: f7ff ff39 bl 8000828 pq_init(&huart5q); 80009b6: 484d ldr r0, [pc, #308] @ (8000aec ) 80009b8: f7ff ff36 bl 8000828 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { switch (MODE){ 80009bc: 4b4c ldr r3, [pc, #304] @ (8000af0 ) 80009be: 781b ldrb r3, [r3, #0] 80009c0: b2db uxtb r3, r3 80009c2: 2b02 cmp r3, #2 80009c4: d006 beq.n 80009d4 80009c6: 2b02 cmp r3, #2 80009c8: dc6a bgt.n 8000aa0 80009ca: 2b00 cmp r3, #0 80009cc: d025 beq.n 8000a1a 80009ce: 2b01 cmp r3, #1 80009d0: d05a beq.n 8000a88 //encoderProcess(); USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); break; default: break; 80009d2: e065 b.n 8000aa0 KEYSTATE_CHANGED_FLAG = 1; 80009d4: 4b47 ldr r3, [pc, #284] @ (8000af4 ) 80009d6: 2201 movs r2, #1 80009d8: 701a strb r2, [r3, #0] resetReport(); 80009da: f000 fc4f bl 800127c matrixScan(); 80009de: f000 fbd5 bl 800118c mergeChild(); 80009e2: f000 f923 bl 8000c2c if(KEYSTATE_CHANGED_FLAG == 1){ 80009e6: 4b43 ldr r3, [pc, #268] @ (8000af4 ) 80009e8: 781b ldrb r3, [r3, #0] 80009ea: 2b01 cmp r3, #1 80009ec: d15a bne.n 8000aa4 UARTREPORT.DEPTH = DEPTH; 80009ee: 4b42 ldr r3, [pc, #264] @ (8000af8 ) 80009f0: 881b ldrh r3, [r3, #0] 80009f2: 823b strh r3, [r7, #16] UARTREPORT.TYPE = 0xEE; 80009f4: 23ee movs r3, #238 @ 0xee 80009f6: 827b strh r3, [r7, #18] memcpy(UARTREPORT.KEYPRESS, REPORT.KEYPRESS, sizeof(UARTREPORT.KEYPRESS)); 80009f8: 4a40 ldr r2, [pc, #256] @ (8000afc ) 80009fa: f107 0314 add.w r3, r7, #20 80009fe: 3202 adds r2, #2 8000a00: 6810 ldr r0, [r2, #0] 8000a02: 6851 ldr r1, [r2, #4] 8000a04: 6892 ldr r2, [r2, #8] 8000a06: c307 stmia r3!, {r0, r1, r2} HAL_UART_Transmit_DMA(PARENT, (uint8_t*)&UARTREPORT, sizeof(UARTREPORT)); 8000a08: 4b3d ldr r3, [pc, #244] @ (8000b00 ) 8000a0a: 681b ldr r3, [r3, #0] 8000a0c: f107 0110 add.w r1, r7, #16 8000a10: 2210 movs r2, #16 8000a12: 4618 mov r0, r3 8000a14: f005 ff54 bl 80068c0 break; 8000a18: e044 b.n 8000aa4 if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){ 8000a1a: 4b3a ldr r3, [pc, #232] @ (8000b04 ) 8000a1c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8000a20: b2db uxtb r3, r3 8000a22: 2b03 cmp r3, #3 8000a24: d106 bne.n 8000a34 MODE = MODE_MAINBOARD; 8000a26: 4b32 ldr r3, [pc, #200] @ (8000af0 ) 8000a28: 2201 movs r2, #1 8000a2a: 701a strb r2, [r3, #0] DEPTH = 0; 8000a2c: 4b32 ldr r3, [pc, #200] @ (8000af8 ) 8000a2e: 2200 movs r2, #0 8000a30: 801a strh r2, [r3, #0] break; 8000a32: e038 b.n 8000aa6 REQ.DEPTH = 0; 8000a34: 2300 movs r3, #0 8000a36: 803b strh r3, [r7, #0] REQ.TYPE = 0xFF; //Message code for request is 0xFF 8000a38: 23ff movs r3, #255 @ 0xff 8000a3a: 807b strh r3, [r7, #2] memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS)); 8000a3c: 463b mov r3, r7 8000a3e: 3304 adds r3, #4 8000a40: 220c movs r2, #12 8000a42: 2100 movs r1, #0 8000a44: 4618 mov r0, r3 8000a46: f00a fe5f bl 800b708 HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ)); 8000a4a: 463b mov r3, r7 8000a4c: 2210 movs r2, #16 8000a4e: 4619 mov r1, r3 8000a50: 4819 ldr r0, [pc, #100] @ (8000ab8 ) 8000a52: f005 ff35 bl 80068c0 HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ)); 8000a56: 463b mov r3, r7 8000a58: 2210 movs r2, #16 8000a5a: 4619 mov r1, r3 8000a5c: 4818 ldr r0, [pc, #96] @ (8000ac0 ) 8000a5e: f005 ff2f bl 80068c0 HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); 8000a62: 463b mov r3, r7 8000a64: 2210 movs r2, #16 8000a66: 4619 mov r1, r3 8000a68: 4817 ldr r0, [pc, #92] @ (8000ac8 ) 8000a6a: f005 ff29 bl 80068c0 HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); 8000a6e: 463b mov r3, r7 8000a70: 2210 movs r2, #16 8000a72: 4619 mov r1, r3 8000a74: 4816 ldr r0, [pc, #88] @ (8000ad0 ) 8000a76: f005 ff23 bl 80068c0 HAL_Delay(500); 8000a7a: f44f 70fa mov.w r0, #500 @ 0x1f4 8000a7e: f001 fa2d bl 8001edc findBestParent(); //So true... 8000a82: f000 fa6b bl 8000f5c break; 8000a86: e00e b.n 8000aa6 resetReport(); 8000a88: f000 fbf8 bl 800127c matrixScan();//Something related to this making the key stick. Likely due to race conditions 8000a8c: f000 fb7e bl 800118c mergeChild(); 8000a90: f000 f8cc bl 8000c2c USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); 8000a94: 220e movs r2, #14 8000a96: 4919 ldr r1, [pc, #100] @ (8000afc ) 8000a98: 481a ldr r0, [pc, #104] @ (8000b04 ) 8000a9a: f008 fdbb bl 8009614 break; 8000a9e: e002 b.n 8000aa6 break; 8000aa0: bf00 nop 8000aa2: e000 b.n 8000aa6 break; 8000aa4: bf00 nop } RGBProcess(); 8000aa6: f000 f82f bl 8000b08 HAL_Delay(20); 8000aaa: 2014 movs r0, #20 8000aac: f001 fa16 bl 8001edc switch (MODE){ 8000ab0: e784 b.n 80009bc 8000ab2: bf00 nop 8000ab4: 200003b0 .word 0x200003b0 8000ab8: 20000b70 .word 0x20000b70 8000abc: 200003c0 .word 0x200003c0 8000ac0: 20000bb8 .word 0x20000bb8 8000ac4: 200003d0 .word 0x200003d0 8000ac8: 20000ae0 .word 0x20000ae0 8000acc: 200003a0 .word 0x200003a0 8000ad0: 20000b28 .word 0x20000b28 8000ad4: 20000a98 .word 0x20000a98 8000ad8: 2000040c .word 0x2000040c 8000adc: 200003ec .word 0x200003ec 8000ae0: 20000440 .word 0x20000440 8000ae4: 200005c4 .word 0x200005c4 8000ae8: 20000748 .word 0x20000748 8000aec: 200008cc .word 0x200008cc 8000af0: 2000040a .word 0x2000040a 8000af4: 200003e8 .word 0x200003e8 8000af8: 200003e0 .word 0x200003e0 8000afc: 20000390 .word 0x20000390 8000b00: 200003e4 .word 0x200003e4 8000b04: 20000f08 .word 0x20000f08 08000b08 : /* USER CODE BEGIN 3 */ } /* USER CODE END 3 */ } void RGBProcess(){ 8000b08: b580 push {r7, lr} 8000b0a: b082 sub sp, #8 8000b0c: af00 add r7, sp, #0 uint8_t red = 255; 8000b0e: 23ff movs r3, #255 @ 0xff 8000b10: 71fb strb r3, [r7, #7] uint8_t blue = 256/2; 8000b12: 2380 movs r3, #128 @ 0x80 8000b14: 71bb strb r3, [r7, #6] uint8_t green = 0; 8000b16: 2300 movs r3, #0 8000b18: 717b strb r3, [r7, #5] for(int i = 0; i < LED_COUNT; i++){ 8000b1a: 2300 movs r3, #0 8000b1c: 603b str r3, [r7, #0] 8000b1e: e011 b.n 8000b44 setRGBcolor(i, red, blue, green); 8000b20: 797b ldrb r3, [r7, #5] 8000b22: 79ba ldrb r2, [r7, #6] 8000b24: 79f9 ldrb r1, [r7, #7] 8000b26: 6838 ldr r0, [r7, #0] 8000b28: f000 f816 bl 8000b58 red += 10; 8000b2c: 79fb ldrb r3, [r7, #7] 8000b2e: 330a adds r3, #10 8000b30: 71fb strb r3, [r7, #7] blue+= 10; 8000b32: 79bb ldrb r3, [r7, #6] 8000b34: 330a adds r3, #10 8000b36: 71bb strb r3, [r7, #6] green += 10; 8000b38: 797b ldrb r3, [r7, #5] 8000b3a: 330a adds r3, #10 8000b3c: 717b strb r3, [r7, #5] for(int i = 0; i < LED_COUNT; i++){ 8000b3e: 683b ldr r3, [r7, #0] 8000b40: 3301 adds r3, #1 8000b42: 603b str r3, [r7, #0] 8000b44: 683b ldr r3, [r7, #0] 8000b46: 2b07 cmp r3, #7 8000b48: ddea ble.n 8000b20 } sendRGBcolor(); 8000b4a: f000 f861 bl 8000c10 } 8000b4e: bf00 nop 8000b50: 3708 adds r7, #8 8000b52: 46bd mov sp, r7 8000b54: bd80 pop {r7, pc} ... 08000b58 : //Sets each bit in the buffer that is going to get sent thru PWM DMA void setRGBcolor(int index, uint8_t r, uint8_t g, uint8_t b) { 8000b58: b480 push {r7} 8000b5a: b087 sub sp, #28 8000b5c: af00 add r7, sp, #0 8000b5e: 6078 str r0, [r7, #4] 8000b60: 4608 mov r0, r1 8000b62: 4611 mov r1, r2 8000b64: 461a mov r2, r3 8000b66: 4603 mov r3, r0 8000b68: 70fb strb r3, [r7, #3] 8000b6a: 460b mov r3, r1 8000b6c: 70bb strb r3, [r7, #2] 8000b6e: 4613 mov r3, r2 8000b70: 707b strb r3, [r7, #1] uint8_t colors[3] = {g, r, b}; 8000b72: 78bb ldrb r3, [r7, #2] 8000b74: 733b strb r3, [r7, #12] 8000b76: 78fb ldrb r3, [r7, #3] 8000b78: 737b strb r3, [r7, #13] 8000b7a: 787b ldrb r3, [r7, #1] 8000b7c: 73bb strb r3, [r7, #14] for (int c = 0; c < 3; c++) { 8000b7e: 2300 movs r3, #0 8000b80: 617b str r3, [r7, #20] 8000b82: e039 b.n 8000bf8 for (int bit = 0; bit < 8; bit++) { 8000b84: 2300 movs r3, #0 8000b86: 613b str r3, [r7, #16] 8000b88: e030 b.n 8000bec if (colors[c] & (1 << (7 - bit))) { 8000b8a: f107 020c add.w r2, r7, #12 8000b8e: 697b ldr r3, [r7, #20] 8000b90: 4413 add r3, r2 8000b92: 781b ldrb r3, [r3, #0] 8000b94: 461a mov r2, r3 8000b96: 693b ldr r3, [r7, #16] 8000b98: f1c3 0307 rsb r3, r3, #7 8000b9c: fa42 f303 asr.w r3, r2, r3 8000ba0: f003 0301 and.w r3, r3, #1 8000ba4: 2b00 cmp r3, #0 8000ba6: d00f beq.n 8000bc8 led_buffer[index * 24 + (c * 8 + bit)] = T1H; 8000ba8: 687a ldr r2, [r7, #4] 8000baa: 4613 mov r3, r2 8000bac: 005b lsls r3, r3, #1 8000bae: 4413 add r3, r2 8000bb0: 00db lsls r3, r3, #3 8000bb2: 4619 mov r1, r3 8000bb4: 697b ldr r3, [r7, #20] 8000bb6: 00da lsls r2, r3, #3 8000bb8: 693b ldr r3, [r7, #16] 8000bba: 4413 add r3, r2 8000bbc: 440b add r3, r1 8000bbe: 4a13 ldr r2, [pc, #76] @ (8000c0c ) 8000bc0: 2104 movs r1, #4 8000bc2: f822 1013 strh.w r1, [r2, r3, lsl #1] 8000bc6: e00e b.n 8000be6 } else { led_buffer[index * 24 + (c * 8 + bit)] = T0H; 8000bc8: 687a ldr r2, [r7, #4] 8000bca: 4613 mov r3, r2 8000bcc: 005b lsls r3, r3, #1 8000bce: 4413 add r3, r2 8000bd0: 00db lsls r3, r3, #3 8000bd2: 4619 mov r1, r3 8000bd4: 697b ldr r3, [r7, #20] 8000bd6: 00da lsls r2, r3, #3 8000bd8: 693b ldr r3, [r7, #16] 8000bda: 4413 add r3, r2 8000bdc: 440b add r3, r1 8000bde: 4a0b ldr r2, [pc, #44] @ (8000c0c ) 8000be0: 2103 movs r1, #3 8000be2: f822 1013 strh.w r1, [r2, r3, lsl #1] for (int bit = 0; bit < 8; bit++) { 8000be6: 693b ldr r3, [r7, #16] 8000be8: 3301 adds r3, #1 8000bea: 613b str r3, [r7, #16] 8000bec: 693b ldr r3, [r7, #16] 8000bee: 2b07 cmp r3, #7 8000bf0: ddcb ble.n 8000b8a for (int c = 0; c < 3; c++) { 8000bf2: 697b ldr r3, [r7, #20] 8000bf4: 3301 adds r3, #1 8000bf6: 617b str r3, [r7, #20] 8000bf8: 697b ldr r3, [r7, #20] 8000bfa: 2b02 cmp r3, #2 8000bfc: ddc2 ble.n 8000b84 } } } } 8000bfe: bf00 nop 8000c00: bf00 nop 8000c02: 371c adds r7, #28 8000c04: 46bd mov sp, r7 8000c06: f85d 7b04 ldr.w r7, [sp], #4 8000c0a: 4770 bx lr 8000c0c: 20000210 .word 0x20000210 08000c10 : //Sends whats on the buffer thru DMA void sendRGBcolor(){ 8000c10: b580 push {r7, lr} 8000c12: af00 add r7, sp, #0 HAL_TIM_PWM_Start_DMA(&htim2, TIM_CHANNEL_1,(uint32_t*)led_buffer,LED_BUFFER_SIZE); 8000c14: 23c0 movs r3, #192 @ 0xc0 8000c16: 4a03 ldr r2, [pc, #12] @ (8000c24 ) 8000c18: 2100 movs r1, #0 8000c1a: 4803 ldr r0, [pc, #12] @ (8000c28 ) 8000c1c: f004 fd92 bl 8005744 } 8000c20: bf00 nop 8000c22: bd80 pop {r7, pc} 8000c24: 20000210 .word 0x20000210 8000c28: 20000a50 .word 0x20000a50 08000c2c : void mergeChild(){ 8000c2c: b590 push {r4, r7, lr} 8000c2e: b087 sub sp, #28 8000c30: af00 add r7, sp, #0 uint8_t packet[12]; if (pq_pop(&huart1q, packet)) { 8000c32: 1d3b adds r3, r7, #4 8000c34: 4619 mov r1, r3 8000c36: 4838 ldr r0, [pc, #224] @ (8000d18 ) 8000c38: f7ff fe40 bl 80008bc 8000c3c: 4603 mov r3, r0 8000c3e: 2b00 cmp r3, #0 8000c40: d008 beq.n 8000c54 memcpy(UART_KEYSTATE[1], packet, 12); 8000c42: 4b36 ldr r3, [pc, #216] @ (8000d1c ) 8000c44: 330c adds r3, #12 8000c46: 1d3a adds r2, r7, #4 8000c48: ca07 ldmia r2, {r0, r1, r2} 8000c4a: e883 0007 stmia.w r3, {r0, r1, r2} KEYSTATE_CHANGED_FLAG = 1; 8000c4e: 4b34 ldr r3, [pc, #208] @ (8000d20 ) 8000c50: 2201 movs r2, #1 8000c52: 701a strb r2, [r3, #0] } if (pq_pop(&huart2q, packet)) { 8000c54: 1d3b adds r3, r7, #4 8000c56: 4619 mov r1, r3 8000c58: 4832 ldr r0, [pc, #200] @ (8000d24 ) 8000c5a: f7ff fe2f bl 80008bc 8000c5e: 4603 mov r3, r0 8000c60: 2b00 cmp r3, #0 8000c62: d008 beq.n 8000c76 memcpy(UART_KEYSTATE[2], packet, 12); 8000c64: 4b2d ldr r3, [pc, #180] @ (8000d1c ) 8000c66: 3318 adds r3, #24 8000c68: 1d3a adds r2, r7, #4 8000c6a: ca07 ldmia r2, {r0, r1, r2} 8000c6c: e883 0007 stmia.w r3, {r0, r1, r2} KEYSTATE_CHANGED_FLAG = 1; 8000c70: 4b2b ldr r3, [pc, #172] @ (8000d20 ) 8000c72: 2201 movs r2, #1 8000c74: 701a strb r2, [r3, #0] } if (pq_pop(&huart4q, packet)) { 8000c76: 1d3b adds r3, r7, #4 8000c78: 4619 mov r1, r3 8000c7a: 482b ldr r0, [pc, #172] @ (8000d28 ) 8000c7c: f7ff fe1e bl 80008bc 8000c80: 4603 mov r3, r0 8000c82: 2b00 cmp r3, #0 8000c84: d008 beq.n 8000c98 memcpy(UART_KEYSTATE[3], packet, 12); 8000c86: 4b25 ldr r3, [pc, #148] @ (8000d1c ) 8000c88: 3324 adds r3, #36 @ 0x24 8000c8a: 1d3a adds r2, r7, #4 8000c8c: ca07 ldmia r2, {r0, r1, r2} 8000c8e: e883 0007 stmia.w r3, {r0, r1, r2} KEYSTATE_CHANGED_FLAG = 1; 8000c92: 4b23 ldr r3, [pc, #140] @ (8000d20 ) 8000c94: 2201 movs r2, #1 8000c96: 701a strb r2, [r3, #0] } if (pq_pop(&huart5q, packet)) { 8000c98: 1d3b adds r3, r7, #4 8000c9a: 4619 mov r1, r3 8000c9c: 4823 ldr r0, [pc, #140] @ (8000d2c ) 8000c9e: f7ff fe0d bl 80008bc 8000ca2: 4603 mov r3, r0 8000ca4: 2b00 cmp r3, #0 8000ca6: d009 beq.n 8000cbc memcpy(UART_KEYSTATE[0], packet, 12); 8000ca8: 4b1c ldr r3, [pc, #112] @ (8000d1c ) 8000caa: 461c mov r4, r3 8000cac: 1d3b adds r3, r7, #4 8000cae: e893 0007 ldmia.w r3, {r0, r1, r2} 8000cb2: e884 0007 stmia.w r4, {r0, r1, r2} KEYSTATE_CHANGED_FLAG = 1; 8000cb6: 4b1a ldr r3, [pc, #104] @ (8000d20 ) 8000cb8: 2201 movs r2, #1 8000cba: 701a strb r2, [r3, #0] } for(int i = 0; i < 4; i++){ 8000cbc: 2300 movs r3, #0 8000cbe: 617b str r3, [r7, #20] 8000cc0: e022 b.n 8000d08 for(int j = 0; j < 12; j++){ 8000cc2: 2300 movs r3, #0 8000cc4: 613b str r3, [r7, #16] 8000cc6: e019 b.n 8000cfc REPORT.KEYPRESS[j] |= UART_KEYSTATE[i][j]; 8000cc8: 4a19 ldr r2, [pc, #100] @ (8000d30 ) 8000cca: 693b ldr r3, [r7, #16] 8000ccc: 4413 add r3, r2 8000cce: 3302 adds r3, #2 8000cd0: 7819 ldrb r1, [r3, #0] 8000cd2: 4812 ldr r0, [pc, #72] @ (8000d1c ) 8000cd4: 697a ldr r2, [r7, #20] 8000cd6: 4613 mov r3, r2 8000cd8: 005b lsls r3, r3, #1 8000cda: 4413 add r3, r2 8000cdc: 009b lsls r3, r3, #2 8000cde: 18c2 adds r2, r0, r3 8000ce0: 693b ldr r3, [r7, #16] 8000ce2: 4413 add r3, r2 8000ce4: 781b ldrb r3, [r3, #0] 8000ce6: 430b orrs r3, r1 8000ce8: b2d9 uxtb r1, r3 8000cea: 4a11 ldr r2, [pc, #68] @ (8000d30 ) 8000cec: 693b ldr r3, [r7, #16] 8000cee: 4413 add r3, r2 8000cf0: 3302 adds r3, #2 8000cf2: 460a mov r2, r1 8000cf4: 701a strb r2, [r3, #0] for(int j = 0; j < 12; j++){ 8000cf6: 693b ldr r3, [r7, #16] 8000cf8: 3301 adds r3, #1 8000cfa: 613b str r3, [r7, #16] 8000cfc: 693b ldr r3, [r7, #16] 8000cfe: 2b0b cmp r3, #11 8000d00: dde2 ble.n 8000cc8 for(int i = 0; i < 4; i++){ 8000d02: 697b ldr r3, [r7, #20] 8000d04: 3301 adds r3, #1 8000d06: 617b str r3, [r7, #20] 8000d08: 697b ldr r3, [r7, #20] 8000d0a: 2b03 cmp r3, #3 8000d0c: ddd9 ble.n 8000cc2 } } } 8000d0e: bf00 nop 8000d10: bf00 nop 8000d12: 371c adds r7, #28 8000d14: 46bd mov sp, r7 8000d16: bd90 pop {r4, r7, pc} 8000d18: 20000440 .word 0x20000440 8000d1c: 20000410 .word 0x20000410 8000d20: 200003e8 .word 0x200003e8 8000d24: 200005c4 .word 0x200005c4 8000d28: 20000748 .word 0x20000748 8000d2c: 200008cc .word 0x200008cc 8000d30: 20000390 .word 0x20000390 08000d34 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000d34: b580 push {r7, lr} 8000d36: b094 sub sp, #80 @ 0x50 8000d38: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000d3a: f107 031c add.w r3, r7, #28 8000d3e: 2234 movs r2, #52 @ 0x34 8000d40: 2100 movs r1, #0 8000d42: 4618 mov r0, r3 8000d44: f00a fce0 bl 800b708 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000d48: f107 0308 add.w r3, r7, #8 8000d4c: 2200 movs r2, #0 8000d4e: 601a str r2, [r3, #0] 8000d50: 605a str r2, [r3, #4] 8000d52: 609a str r2, [r3, #8] 8000d54: 60da str r2, [r3, #12] 8000d56: 611a str r2, [r3, #16] /** Configure the main internal regulator out put voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 8000d58: 2300 movs r3, #0 8000d5a: 607b str r3, [r7, #4] 8000d5c: 4b29 ldr r3, [pc, #164] @ (8000e04 ) 8000d5e: 6c1b ldr r3, [r3, #64] @ 0x40 8000d60: 4a28 ldr r2, [pc, #160] @ (8000e04 ) 8000d62: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000d66: 6413 str r3, [r2, #64] @ 0x40 8000d68: 4b26 ldr r3, [pc, #152] @ (8000e04 ) 8000d6a: 6c1b ldr r3, [r3, #64] @ 0x40 8000d6c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000d70: 607b str r3, [r7, #4] 8000d72: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 8000d74: 2300 movs r3, #0 8000d76: 603b str r3, [r7, #0] 8000d78: 4b23 ldr r3, [pc, #140] @ (8000e08 ) 8000d7a: 681b ldr r3, [r3, #0] 8000d7c: f423 4340 bic.w r3, r3, #49152 @ 0xc000 8000d80: 4a21 ldr r2, [pc, #132] @ (8000e08 ) 8000d82: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000d86: 6013 str r3, [r2, #0] 8000d88: 4b1f ldr r3, [pc, #124] @ (8000e08 ) 8000d8a: 681b ldr r3, [r3, #0] 8000d8c: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000d90: 603b str r3, [r7, #0] 8000d92: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000d94: 2301 movs r3, #1 8000d96: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000d98: f44f 3380 mov.w r3, #65536 @ 0x10000 8000d9c: 623b str r3, [r7, #32] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000d9e: 2302 movs r3, #2 8000da0: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000da2: f44f 0380 mov.w r3, #4194304 @ 0x400000 8000da6: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLM = 4; 8000da8: 2304 movs r3, #4 8000daa: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLN = 96; 8000dac: 2360 movs r3, #96 @ 0x60 8000dae: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8000db0: 2302 movs r3, #2 8000db2: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLQ = 4; 8000db4: 2304 movs r3, #4 8000db6: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLR = 2; 8000db8: 2302 movs r3, #2 8000dba: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000dbc: f107 031c add.w r3, r7, #28 8000dc0: 4618 mov r0, r3 8000dc2: f004 f9c7 bl 8005154 8000dc6: 4603 mov r3, r0 8000dc8: 2b00 cmp r3, #0 8000dca: d001 beq.n 8000dd0 { Error_Handler(); 8000dcc: f000 fa62 bl 8001294 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000dd0: 230f movs r3, #15 8000dd2: 60bb str r3, [r7, #8] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000dd4: 2302 movs r3, #2 8000dd6: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; 8000dd8: 2380 movs r3, #128 @ 0x80 8000dda: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000ddc: f44f 5380 mov.w r3, #4096 @ 0x1000 8000de0: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000de2: 2300 movs r3, #0 8000de4: 61bb str r3, [r7, #24] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000de6: f107 0308 add.w r3, r7, #8 8000dea: 2101 movs r1, #1 8000dec: 4618 mov r0, r3 8000dee: f003 fb3d bl 800446c 8000df2: 4603 mov r3, r0 8000df4: 2b00 cmp r3, #0 8000df6: d001 beq.n 8000dfc { Error_Handler(); 8000df8: f000 fa4c bl 8001294 } } 8000dfc: bf00 nop 8000dfe: 3750 adds r7, #80 @ 0x50 8000e00: 46bd mov sp, r7 8000e02: bd80 pop {r7, pc} 8000e04: 40023800 .word 0x40023800 8000e08: 40007000 .word 0x40007000 08000e0c : /* USER CODE BEGIN 4 */ // UART Message Requests Goes Here void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8000e0c: b580 push {r7, lr} 8000e0e: b082 sub sp, #8 8000e10: af00 add r7, sp, #0 8000e12: 6078 str r0, [r7, #4] if (huart->Instance == USART1) { 8000e14: 687b ldr r3, [r7, #4] 8000e16: 681b ldr r3, [r3, #0] 8000e18: 4a1e ldr r2, [pc, #120] @ (8000e94 ) 8000e1a: 4293 cmp r3, r2 8000e1c: d109 bne.n 8000e32 handleUARTMessages((uint8_t*)&RX1Msg, &huart1); 8000e1e: 491e ldr r1, [pc, #120] @ (8000e98 ) 8000e20: 481e ldr r0, [pc, #120] @ (8000e9c ) 8000e22: f000 f8dd bl 8000fe0 HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000e26: 2210 movs r2, #16 8000e28: 491c ldr r1, [pc, #112] @ (8000e9c ) 8000e2a: 481b ldr r0, [pc, #108] @ (8000e98 ) 8000e2c: f005 fdc4 bl 80069b8 } else if (huart->Instance == UART5) { handleUARTMessages((uint8_t*)&RX5Msg, &huart5); HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000e30: e02b b.n 8000e8a else if (huart->Instance == USART2) { 8000e32: 687b ldr r3, [r7, #4] 8000e34: 681b ldr r3, [r3, #0] 8000e36: 4a1a ldr r2, [pc, #104] @ (8000ea0 ) 8000e38: 4293 cmp r3, r2 8000e3a: d109 bne.n 8000e50 handleUARTMessages((uint8_t*)&RX2Msg, &huart2); 8000e3c: 4919 ldr r1, [pc, #100] @ (8000ea4 ) 8000e3e: 481a ldr r0, [pc, #104] @ (8000ea8 ) 8000e40: f000 f8ce bl 8000fe0 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000e44: 2210 movs r2, #16 8000e46: 4918 ldr r1, [pc, #96] @ (8000ea8 ) 8000e48: 4816 ldr r0, [pc, #88] @ (8000ea4 ) 8000e4a: f005 fdb5 bl 80069b8 } 8000e4e: e01c b.n 8000e8a else if (huart->Instance == UART4) { 8000e50: 687b ldr r3, [r7, #4] 8000e52: 681b ldr r3, [r3, #0] 8000e54: 4a15 ldr r2, [pc, #84] @ (8000eac ) 8000e56: 4293 cmp r3, r2 8000e58: d109 bne.n 8000e6e handleUARTMessages((uint8_t*)&RX4Msg, &huart4); 8000e5a: 4915 ldr r1, [pc, #84] @ (8000eb0 ) 8000e5c: 4815 ldr r0, [pc, #84] @ (8000eb4 ) 8000e5e: f000 f8bf bl 8000fe0 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000e62: 2210 movs r2, #16 8000e64: 4913 ldr r1, [pc, #76] @ (8000eb4 ) 8000e66: 4812 ldr r0, [pc, #72] @ (8000eb0 ) 8000e68: f005 fda6 bl 80069b8 } 8000e6c: e00d b.n 8000e8a else if (huart->Instance == UART5) { 8000e6e: 687b ldr r3, [r7, #4] 8000e70: 681b ldr r3, [r3, #0] 8000e72: 4a11 ldr r2, [pc, #68] @ (8000eb8 ) 8000e74: 4293 cmp r3, r2 8000e76: d108 bne.n 8000e8a handleUARTMessages((uint8_t*)&RX5Msg, &huart5); 8000e78: 4910 ldr r1, [pc, #64] @ (8000ebc ) 8000e7a: 4811 ldr r0, [pc, #68] @ (8000ec0 ) 8000e7c: f000 f8b0 bl 8000fe0 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000e80: 2210 movs r2, #16 8000e82: 490f ldr r1, [pc, #60] @ (8000ec0 ) 8000e84: 480d ldr r0, [pc, #52] @ (8000ebc ) 8000e86: f005 fd97 bl 80069b8 } 8000e8a: bf00 nop 8000e8c: 3708 adds r7, #8 8000e8e: 46bd mov sp, r7 8000e90: bd80 pop {r7, pc} 8000e92: bf00 nop 8000e94: 40011000 .word 0x40011000 8000e98: 20000b70 .word 0x20000b70 8000e9c: 200003b0 .word 0x200003b0 8000ea0: 40004400 .word 0x40004400 8000ea4: 20000bb8 .word 0x20000bb8 8000ea8: 200003c0 .word 0x200003c0 8000eac: 40004c00 .word 0x40004c00 8000eb0: 20000ae0 .word 0x20000ae0 8000eb4: 200003d0 .word 0x200003d0 8000eb8: 40005000 .word 0x40005000 8000ebc: 20000b28 .word 0x20000b28 8000ec0: 200003a0 .word 0x200003a0 08000ec4 : void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8000ec4: b580 push {r7, lr} 8000ec6: b082 sub sp, #8 8000ec8: af00 add r7, sp, #0 8000eca: 6078 str r0, [r7, #4] // Restart DMA on error if (huart->Instance == USART1) { 8000ecc: 687b ldr r3, [r7, #4] 8000ece: 681b ldr r3, [r3, #0] 8000ed0: 4a16 ldr r2, [pc, #88] @ (8000f2c ) 8000ed2: 4293 cmp r3, r2 8000ed4: d105 bne.n 8000ee2 HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000ed6: 2210 movs r2, #16 8000ed8: 4915 ldr r1, [pc, #84] @ (8000f30 ) 8000eda: 4816 ldr r0, [pc, #88] @ (8000f34 ) 8000edc: f005 fd6c bl 80069b8 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); } else if (huart->Instance == UART5) { HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000ee0: e01f b.n 8000f22 else if (huart->Instance == USART2) { 8000ee2: 687b ldr r3, [r7, #4] 8000ee4: 681b ldr r3, [r3, #0] 8000ee6: 4a14 ldr r2, [pc, #80] @ (8000f38 ) 8000ee8: 4293 cmp r3, r2 8000eea: d105 bne.n 8000ef8 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000eec: 2210 movs r2, #16 8000eee: 4913 ldr r1, [pc, #76] @ (8000f3c ) 8000ef0: 4813 ldr r0, [pc, #76] @ (8000f40 ) 8000ef2: f005 fd61 bl 80069b8 } 8000ef6: e014 b.n 8000f22 else if (huart->Instance == UART4) { 8000ef8: 687b ldr r3, [r7, #4] 8000efa: 681b ldr r3, [r3, #0] 8000efc: 4a11 ldr r2, [pc, #68] @ (8000f44 ) 8000efe: 4293 cmp r3, r2 8000f00: d105 bne.n 8000f0e HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000f02: 2210 movs r2, #16 8000f04: 4910 ldr r1, [pc, #64] @ (8000f48 ) 8000f06: 4811 ldr r0, [pc, #68] @ (8000f4c ) 8000f08: f005 fd56 bl 80069b8 } 8000f0c: e009 b.n 8000f22 else if (huart->Instance == UART5) { 8000f0e: 687b ldr r3, [r7, #4] 8000f10: 681b ldr r3, [r3, #0] 8000f12: 4a0f ldr r2, [pc, #60] @ (8000f50 ) 8000f14: 4293 cmp r3, r2 8000f16: d104 bne.n 8000f22 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000f18: 2210 movs r2, #16 8000f1a: 490e ldr r1, [pc, #56] @ (8000f54 ) 8000f1c: 480e ldr r0, [pc, #56] @ (8000f58 ) 8000f1e: f005 fd4b bl 80069b8 } 8000f22: bf00 nop 8000f24: 3708 adds r7, #8 8000f26: 46bd mov sp, r7 8000f28: bd80 pop {r7, pc} 8000f2a: bf00 nop 8000f2c: 40011000 .word 0x40011000 8000f30: 200003b0 .word 0x200003b0 8000f34: 20000b70 .word 0x20000b70 8000f38: 40004400 .word 0x40004400 8000f3c: 200003c0 .word 0x200003c0 8000f40: 20000bb8 .word 0x20000bb8 8000f44: 40004c00 .word 0x40004c00 8000f48: 200003d0 .word 0x200003d0 8000f4c: 20000ae0 .word 0x20000ae0 8000f50: 40005000 .word 0x40005000 8000f54: 200003a0 .word 0x200003a0 8000f58: 20000b28 .word 0x20000b28 08000f5c : void findBestParent(){ 8000f5c: b580 push {r7, lr} 8000f5e: b084 sub sp, #16 8000f60: af00 add r7, sp, #0 //Find least depth parent uint16_t least_val = 0xFF; 8000f62: 23ff movs r3, #255 @ 0xff 8000f64: 81fb strh r3, [r7, #14] UART_HandleTypeDef* least_port = NULL; 8000f66: 2300 movs r3, #0 8000f68: 60bb str r3, [r7, #8] for(uint8_t i = 0; i < 4; i++){ 8000f6a: 2300 movs r3, #0 8000f6c: 71fb strb r3, [r7, #7] 8000f6e: e013 b.n 8000f98 if(PORT_DEPTH[i]) 8000f74: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000f78: 89fa ldrh r2, [r7, #14] 8000f7a: 429a cmp r2, r3 8000f7c: d909 bls.n 8000f92 least_port = PORTS[i]; 8000f7e: 79fb ldrb r3, [r7, #7] 8000f80: 4a13 ldr r2, [pc, #76] @ (8000fd0 ) 8000f82: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000f86: 60bb str r3, [r7, #8] least_val = PORT_DEPTH[i]; 8000f88: 79fb ldrb r3, [r7, #7] 8000f8a: 4a10 ldr r2, [pc, #64] @ (8000fcc ) 8000f8c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000f90: 81fb strh r3, [r7, #14] for(uint8_t i = 0; i < 4; i++){ 8000f92: 79fb ldrb r3, [r7, #7] 8000f94: 3301 adds r3, #1 8000f96: 71fb strb r3, [r7, #7] 8000f98: 79fb ldrb r3, [r7, #7] 8000f9a: 2b03 cmp r3, #3 8000f9c: d9e8 bls.n 8000f70 } } //Assign if valid if(least_val < 0xFF){ 8000f9e: 89fb ldrh r3, [r7, #14] 8000fa0: 2bfe cmp r3, #254 @ 0xfe 8000fa2: d80e bhi.n 8000fc2 PARENT = least_port; 8000fa4: 4a0b ldr r2, [pc, #44] @ (8000fd4 ) 8000fa6: 68bb ldr r3, [r7, #8] 8000fa8: 6013 str r3, [r2, #0] DEPTH = least_val + 1; 8000faa: 89fb ldrh r3, [r7, #14] 8000fac: 3301 adds r3, #1 8000fae: b29a uxth r2, r3 8000fb0: 4b09 ldr r3, [pc, #36] @ (8000fd8 ) 8000fb2: 801a strh r2, [r3, #0] MODE = MODE_ACTIVE; 8000fb4: 4b09 ldr r3, [pc, #36] @ (8000fdc ) 8000fb6: 2202 movs r2, #2 8000fb8: 701a strb r2, [r3, #0] HAL_Delay(500); 8000fba: f44f 70fa mov.w r0, #500 @ 0x1f4 8000fbe: f000 ff8d bl 8001edc } } 8000fc2: bf00 nop 8000fc4: 3710 adds r7, #16 8000fc6: 46bd mov sp, r7 8000fc8: bd80 pop {r7, pc} 8000fca: bf00 nop 8000fcc: 20000078 .word 0x20000078 8000fd0: 20000080 .word 0x20000080 8000fd4: 200003e4 .word 0x200003e4 8000fd8: 200003e0 .word 0x200003e0 8000fdc: 2000040a .word 0x2000040a 08000fe0 : // Called when UART RX interrupt completes void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender) { 8000fe0: b590 push {r4, r7, lr} 8000fe2: b08b sub sp, #44 @ 0x2c 8000fe4: af00 add r7, sp, #0 8000fe6: 6078 str r0, [r7, #4] 8000fe8: 6039 str r1, [r7, #0] UARTMessage msg; UARTMessage reply; // Parse incoming message into struct memcpy(&msg, data, sizeof(UARTMessage)); 8000fea: 687b ldr r3, [r7, #4] 8000fec: f107 0418 add.w r4, r7, #24 8000ff0: 6818 ldr r0, [r3, #0] 8000ff2: 6859 ldr r1, [r3, #4] 8000ff4: 689a ldr r2, [r3, #8] 8000ff6: 68db ldr r3, [r3, #12] 8000ff8: c40f stmia r4!, {r0, r1, r2, r3} switch(msg.TYPE) { 8000ffa: 8b7b ldrh r3, [r7, #26] 8000ffc: 2bff cmp r3, #255 @ 0xff 8000ffe: d026 beq.n 800104e 8001000: 2bff cmp r3, #255 @ 0xff 8001002: dc6e bgt.n 80010e2 8001004: 2baa cmp r3, #170 @ 0xaa 8001006: d002 beq.n 800100e 8001008: 2bee cmp r3, #238 @ 0xee 800100a: d03a beq.n 8001082 } break; default: break; 800100c: e069 b.n 80010e2 if(sender == &huart5) { 800100e: 683b ldr r3, [r7, #0] 8001010: 4a39 ldr r2, [pc, #228] @ (80010f8 ) 8001012: 4293 cmp r3, r2 8001014: d103 bne.n 800101e PORT_DEPTH[0] = msg.DEPTH; 8001016: 8b3a ldrh r2, [r7, #24] 8001018: 4b38 ldr r3, [pc, #224] @ (80010fc ) 800101a: 801a strh r2, [r3, #0] break; 800101c: e063 b.n 80010e6 } else if(sender == &huart1) { 800101e: 683b ldr r3, [r7, #0] 8001020: 4a37 ldr r2, [pc, #220] @ (8001100 ) 8001022: 4293 cmp r3, r2 8001024: d103 bne.n 800102e PORT_DEPTH[1] = msg.DEPTH; 8001026: 8b3a ldrh r2, [r7, #24] 8001028: 4b34 ldr r3, [pc, #208] @ (80010fc ) 800102a: 805a strh r2, [r3, #2] break; 800102c: e05b b.n 80010e6 } else if(sender == &huart2) { 800102e: 683b ldr r3, [r7, #0] 8001030: 4a34 ldr r2, [pc, #208] @ (8001104 ) 8001032: 4293 cmp r3, r2 8001034: d103 bne.n 800103e PORT_DEPTH[2] = msg.DEPTH; 8001036: 8b3a ldrh r2, [r7, #24] 8001038: 4b30 ldr r3, [pc, #192] @ (80010fc ) 800103a: 809a strh r2, [r3, #4] break; 800103c: e053 b.n 80010e6 } else if(sender == &huart4) { 800103e: 683b ldr r3, [r7, #0] 8001040: 4a31 ldr r2, [pc, #196] @ (8001108 ) 8001042: 4293 cmp r3, r2 8001044: d14f bne.n 80010e6 PORT_DEPTH[3] = msg.DEPTH; 8001046: 8b3a ldrh r2, [r7, #24] 8001048: 4b2c ldr r3, [pc, #176] @ (80010fc ) 800104a: 80da strh r2, [r3, #6] break; 800104c: e04b b.n 80010e6 if(MODE!=MODE_INACTIVE){ 800104e: 4b2f ldr r3, [pc, #188] @ (800110c ) 8001050: 781b ldrb r3, [r3, #0] 8001052: b2db uxtb r3, r3 8001054: 2b00 cmp r3, #0 8001056: d048 beq.n 80010ea reply.TYPE = 0xAA; 8001058: 23aa movs r3, #170 @ 0xaa 800105a: 817b strh r3, [r7, #10] reply.DEPTH = DEPTH; // use your local DEPTH 800105c: 4b2c ldr r3, [pc, #176] @ (8001110 ) 800105e: 881b ldrh r3, [r3, #0] 8001060: 813b strh r3, [r7, #8] memset(reply.KEYPRESS, 0, sizeof(reply.KEYPRESS)); 8001062: f107 0308 add.w r3, r7, #8 8001066: 3304 adds r3, #4 8001068: 220c movs r2, #12 800106a: 2100 movs r1, #0 800106c: 4618 mov r0, r3 800106e: f00a fb4b bl 800b708 HAL_UART_Transmit_DMA(sender, (uint8_t*)&reply, sizeof(reply)); 8001072: f107 0308 add.w r3, r7, #8 8001076: 2210 movs r2, #16 8001078: 4619 mov r1, r3 800107a: 6838 ldr r0, [r7, #0] 800107c: f005 fc20 bl 80068c0 break; 8001080: e033 b.n 80010ea if(sender == &huart5) { 8001082: 683b ldr r3, [r7, #0] 8001084: 4a1c ldr r2, [pc, #112] @ (80010f8 ) 8001086: 4293 cmp r3, r2 8001088: d107 bne.n 800109a pq_push(&huart5q, msg.KEYPRESS); 800108a: f107 0318 add.w r3, r7, #24 800108e: 3304 adds r3, #4 8001090: 4619 mov r1, r3 8001092: 4820 ldr r0, [pc, #128] @ (8001114 ) 8001094: f7ff fbde bl 8000854 break; 8001098: e029 b.n 80010ee } else if(sender == &huart1) { 800109a: 683b ldr r3, [r7, #0] 800109c: 4a18 ldr r2, [pc, #96] @ (8001100 ) 800109e: 4293 cmp r3, r2 80010a0: d107 bne.n 80010b2 pq_push(&huart1q, msg.KEYPRESS); 80010a2: f107 0318 add.w r3, r7, #24 80010a6: 3304 adds r3, #4 80010a8: 4619 mov r1, r3 80010aa: 481b ldr r0, [pc, #108] @ (8001118 ) 80010ac: f7ff fbd2 bl 8000854 break; 80010b0: e01d b.n 80010ee } else if(sender == &huart2) { 80010b2: 683b ldr r3, [r7, #0] 80010b4: 4a13 ldr r2, [pc, #76] @ (8001104 ) 80010b6: 4293 cmp r3, r2 80010b8: d107 bne.n 80010ca pq_push(&huart2q, msg.KEYPRESS); 80010ba: f107 0318 add.w r3, r7, #24 80010be: 3304 adds r3, #4 80010c0: 4619 mov r1, r3 80010c2: 4816 ldr r0, [pc, #88] @ (800111c ) 80010c4: f7ff fbc6 bl 8000854 break; 80010c8: e011 b.n 80010ee } else if(sender == &huart4) { 80010ca: 683b ldr r3, [r7, #0] 80010cc: 4a0e ldr r2, [pc, #56] @ (8001108 ) 80010ce: 4293 cmp r3, r2 80010d0: d10d bne.n 80010ee pq_push(&huart4q, msg.KEYPRESS); 80010d2: f107 0318 add.w r3, r7, #24 80010d6: 3304 adds r3, #4 80010d8: 4619 mov r1, r3 80010da: 4811 ldr r0, [pc, #68] @ (8001120 ) 80010dc: f7ff fbba bl 8000854 break; 80010e0: e005 b.n 80010ee break; 80010e2: bf00 nop 80010e4: e004 b.n 80010f0 break; 80010e6: bf00 nop 80010e8: e002 b.n 80010f0 break; 80010ea: bf00 nop 80010ec: e000 b.n 80010f0 break; 80010ee: bf00 nop } } 80010f0: bf00 nop 80010f2: 372c adds r7, #44 @ 0x2c 80010f4: 46bd mov sp, r7 80010f6: bd90 pop {r4, r7, pc} 80010f8: 20000b28 .word 0x20000b28 80010fc: 20000078 .word 0x20000078 8001100: 20000b70 .word 0x20000b70 8001104: 20000bb8 .word 0x20000bb8 8001108: 20000ae0 .word 0x20000ae0 800110c: 2000040a .word 0x2000040a 8001110: 200003e0 .word 0x200003e0 8001114: 200008cc .word 0x200008cc 8001118: 20000440 .word 0x20000440 800111c: 200005c4 .word 0x200005c4 8001120: 20000748 .word 0x20000748 08001124 : void addUSBReport(uint8_t usageID){ 8001124: b480 push {r7} 8001126: b085 sub sp, #20 8001128: af00 add r7, sp, #0 800112a: 4603 mov r3, r0 800112c: 71fb strb r3, [r7, #7] if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 800112e: 79fb ldrb r3, [r7, #7] 8001130: 2b03 cmp r3, #3 8001132: d922 bls.n 800117a 8001134: 79fb ldrb r3, [r7, #7] 8001136: 2b73 cmp r3, #115 @ 0x73 8001138: d81f bhi.n 800117a uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit 800113a: 79fb ldrb r3, [r7, #7] 800113c: b29b uxth r3, r3 800113e: 3b04 subs r3, #4 8001140: 81fb strh r3, [r7, #14] uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array 8001142: 89fb ldrh r3, [r7, #14] 8001144: 08db lsrs r3, r3, #3 8001146: b29b uxth r3, r3 8001148: 737b strb r3, [r7, #13] uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset 800114a: 89fb ldrh r3, [r7, #14] 800114c: b2db uxtb r3, r3 800114e: f003 0307 and.w r3, r3, #7 8001152: 733b strb r3, [r7, #12] REPORT.KEYPRESS[byte_index] |= (1 << bit_offset); 8001154: 7b7b ldrb r3, [r7, #13] 8001156: 4a0c ldr r2, [pc, #48] @ (8001188 ) 8001158: 4413 add r3, r2 800115a: 789b ldrb r3, [r3, #2] 800115c: b25a sxtb r2, r3 800115e: 7b3b ldrb r3, [r7, #12] 8001160: 2101 movs r1, #1 8001162: fa01 f303 lsl.w r3, r1, r3 8001166: b25b sxtb r3, r3 8001168: 4313 orrs r3, r2 800116a: b25a sxtb r2, r3 800116c: 7b7b ldrb r3, [r7, #13] 800116e: b2d1 uxtb r1, r2 8001170: 4a05 ldr r2, [pc, #20] @ (8001188 ) 8001172: 4413 add r3, r2 8001174: 460a mov r2, r1 8001176: 709a strb r2, [r3, #2] 8001178: e000 b.n 800117c if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 800117a: bf00 nop } 800117c: 3714 adds r7, #20 800117e: 46bd mov sp, r7 8001180: f85d 7b04 ldr.w r7, [sp], #4 8001184: 4770 bx lr 8001186: bf00 nop 8001188: 20000390 .word 0x20000390 0800118c : void matrixScan(void){ 800118c: b580 push {r7, lr} 800118e: b082 sub sp, #8 8001190: af00 add r7, sp, #0 for (uint8_t col = 0; col < COL; col++){ 8001192: 2300 movs r3, #0 8001194: 71fb strb r3, [r7, #7] 8001196: e05f b.n 8001258 HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET); 8001198: 79fb ldrb r3, [r7, #7] 800119a: 4a33 ldr r2, [pc, #204] @ (8001268 ) 800119c: f852 0033 ldr.w r0, [r2, r3, lsl #3] 80011a0: 79fb ldrb r3, [r7, #7] 80011a2: 4a31 ldr r2, [pc, #196] @ (8001268 ) 80011a4: 00db lsls r3, r3, #3 80011a6: 4413 add r3, r2 80011a8: 889b ldrh r3, [r3, #4] 80011aa: 2201 movs r2, #1 80011ac: 4619 mov r1, r3 80011ae: f001 fd79 bl 8002ca4 HAL_Delay(1); 80011b2: 2001 movs r0, #1 80011b4: f000 fe92 bl 8001edc for(uint8_t row = 0; row < ROW; row++){ 80011b8: 2300 movs r3, #0 80011ba: 71bb strb r3, [r7, #6] 80011bc: e039 b.n 8001232 uint8_t new_key = HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN); 80011be: 79bb ldrb r3, [r7, #6] 80011c0: 4a2a ldr r2, [pc, #168] @ (800126c ) 80011c2: f852 2033 ldr.w r2, [r2, r3, lsl #3] 80011c6: 79bb ldrb r3, [r7, #6] 80011c8: 4928 ldr r1, [pc, #160] @ (800126c ) 80011ca: 00db lsls r3, r3, #3 80011cc: 440b add r3, r1 80011ce: 889b ldrh r3, [r3, #4] 80011d0: 4619 mov r1, r3 80011d2: 4610 mov r0, r2 80011d4: f001 fd4e bl 8002c74 80011d8: 4603 mov r3, r0 80011da: 717b strb r3, [r7, #5] if(new_key != KEYSTATE[row][col]){ 80011dc: 79ba ldrb r2, [r7, #6] 80011de: 79f9 ldrb r1, [r7, #7] 80011e0: 4823 ldr r0, [pc, #140] @ (8001270 ) 80011e2: 4613 mov r3, r2 80011e4: 009b lsls r3, r3, #2 80011e6: 4413 add r3, r2 80011e8: 4403 add r3, r0 80011ea: 440b add r3, r1 80011ec: 781b ldrb r3, [r3, #0] 80011ee: 797a ldrb r2, [r7, #5] 80011f0: 429a cmp r2, r3 80011f2: d00c beq.n 800120e KEYSTATE_CHANGED_FLAG = 1; 80011f4: 4b1f ldr r3, [pc, #124] @ (8001274 ) 80011f6: 2201 movs r2, #1 80011f8: 701a strb r2, [r3, #0] KEYSTATE[row][col] = new_key; 80011fa: 79ba ldrb r2, [r7, #6] 80011fc: 79f9 ldrb r1, [r7, #7] 80011fe: 481c ldr r0, [pc, #112] @ (8001270 ) 8001200: 4613 mov r3, r2 8001202: 009b lsls r3, r3, #2 8001204: 4413 add r3, r2 8001206: 4403 add r3, r0 8001208: 440b add r3, r1 800120a: 797a ldrb r2, [r7, #5] 800120c: 701a strb r2, [r3, #0] } if(new_key){ 800120e: 797b ldrb r3, [r7, #5] 8001210: 2b00 cmp r3, #0 8001212: d00b beq.n 800122c addUSBReport(KEYCODES[row][col]); 8001214: 79ba ldrb r2, [r7, #6] 8001216: 79f9 ldrb r1, [r7, #7] 8001218: 4817 ldr r0, [pc, #92] @ (8001278 ) 800121a: 4613 mov r3, r2 800121c: 009b lsls r3, r3, #2 800121e: 4413 add r3, r2 8001220: 4403 add r3, r0 8001222: 440b add r3, r1 8001224: 781b ldrb r3, [r3, #0] 8001226: 4618 mov r0, r3 8001228: f7ff ff7c bl 8001124 for(uint8_t row = 0; row < ROW; row++){ 800122c: 79bb ldrb r3, [r7, #6] 800122e: 3301 adds r3, #1 8001230: 71bb strb r3, [r7, #6] 8001232: 79bb ldrb r3, [r7, #6] 8001234: 2b05 cmp r3, #5 8001236: d9c2 bls.n 80011be } } HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET); 8001238: 79fb ldrb r3, [r7, #7] 800123a: 4a0b ldr r2, [pc, #44] @ (8001268 ) 800123c: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8001240: 79fb ldrb r3, [r7, #7] 8001242: 4a09 ldr r2, [pc, #36] @ (8001268 ) 8001244: 00db lsls r3, r3, #3 8001246: 4413 add r3, r2 8001248: 889b ldrh r3, [r3, #4] 800124a: 2200 movs r2, #0 800124c: 4619 mov r1, r3 800124e: f001 fd29 bl 8002ca4 for (uint8_t col = 0; col < COL; col++){ 8001252: 79fb ldrb r3, [r7, #7] 8001254: 3301 adds r3, #1 8001256: 71fb strb r3, [r7, #7] 8001258: 79fb ldrb r3, [r7, #7] 800125a: 2b04 cmp r3, #4 800125c: d99c bls.n 8001198 } } 800125e: bf00 nop 8001260: bf00 nop 8001262: 3708 adds r7, #8 8001264: 46bd mov sp, r7 8001266: bd80 pop {r7, pc} 8001268: 20000030 .word 0x20000030 800126c: 20000000 .word 0x20000000 8001270: 200003ec .word 0x200003ec 8001274: 200003e8 .word 0x200003e8 8001278: 20000058 .word 0x20000058 0800127c : } } LAST_ENCODER_COUNT = cnt; } void resetReport(void){ 800127c: b580 push {r7, lr} 800127e: af00 add r7, sp, #0 memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS)); 8001280: 220c movs r2, #12 8001282: 2100 movs r1, #0 8001284: 4802 ldr r0, [pc, #8] @ (8001290 ) 8001286: f00a fa3f bl 800b708 } 800128a: bf00 nop 800128c: bd80 pop {r7, pc} 800128e: bf00 nop 8001290: 20000392 .word 0x20000392 08001294 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001294: b480 push {r7} 8001296: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001298: b672 cpsid i } 800129a: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800129c: bf00 nop 800129e: e7fd b.n 800129c 080012a0 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80012a0: b480 push {r7} 80012a2: b083 sub sp, #12 80012a4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80012a6: 2300 movs r3, #0 80012a8: 607b str r3, [r7, #4] 80012aa: 4b10 ldr r3, [pc, #64] @ (80012ec ) 80012ac: 6c5b ldr r3, [r3, #68] @ 0x44 80012ae: 4a0f ldr r2, [pc, #60] @ (80012ec ) 80012b0: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80012b4: 6453 str r3, [r2, #68] @ 0x44 80012b6: 4b0d ldr r3, [pc, #52] @ (80012ec ) 80012b8: 6c5b ldr r3, [r3, #68] @ 0x44 80012ba: f403 4380 and.w r3, r3, #16384 @ 0x4000 80012be: 607b str r3, [r7, #4] 80012c0: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 80012c2: 2300 movs r3, #0 80012c4: 603b str r3, [r7, #0] 80012c6: 4b09 ldr r3, [pc, #36] @ (80012ec ) 80012c8: 6c1b ldr r3, [r3, #64] @ 0x40 80012ca: 4a08 ldr r2, [pc, #32] @ (80012ec ) 80012cc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80012d0: 6413 str r3, [r2, #64] @ 0x40 80012d2: 4b06 ldr r3, [pc, #24] @ (80012ec ) 80012d4: 6c1b ldr r3, [r3, #64] @ 0x40 80012d6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80012da: 603b str r3, [r7, #0] 80012dc: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80012de: bf00 nop 80012e0: 370c adds r7, #12 80012e2: 46bd mov sp, r7 80012e4: f85d 7b04 ldr.w r7, [sp], #4 80012e8: 4770 bx lr 80012ea: bf00 nop 80012ec: 40023800 .word 0x40023800 080012f0 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80012f0: b480 push {r7} 80012f2: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80012f4: bf00 nop 80012f6: e7fd b.n 80012f4 080012f8 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80012f8: b480 push {r7} 80012fa: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80012fc: bf00 nop 80012fe: e7fd b.n 80012fc 08001300 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001300: b480 push {r7} 8001302: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8001304: bf00 nop 8001306: e7fd b.n 8001304 08001308 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8001308: b480 push {r7} 800130a: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800130c: bf00 nop 800130e: e7fd b.n 800130c 08001310 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001310: b480 push {r7} 8001312: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8001314: bf00 nop 8001316: e7fd b.n 8001314 08001318 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8001318: b480 push {r7} 800131a: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800131c: bf00 nop 800131e: 46bd mov sp, r7 8001320: f85d 7b04 ldr.w r7, [sp], #4 8001324: 4770 bx lr 08001326 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8001326: b480 push {r7} 8001328: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800132a: bf00 nop 800132c: 46bd mov sp, r7 800132e: f85d 7b04 ldr.w r7, [sp], #4 8001332: 4770 bx lr 08001334 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8001334: b480 push {r7} 8001336: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8001338: bf00 nop 800133a: 46bd mov sp, r7 800133c: f85d 7b04 ldr.w r7, [sp], #4 8001340: 4770 bx lr 08001342 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8001342: b580 push {r7, lr} 8001344: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8001346: f000 fda9 bl 8001e9c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800134a: bf00 nop 800134c: bd80 pop {r7, pc} ... 08001350 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8001350: b580 push {r7, lr} 8001352: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_rx); 8001354: 4802 ldr r0, [pc, #8] @ (8001360 ) 8001356: f001 f88f bl 8002478 /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 800135a: bf00 nop 800135c: bd80 pop {r7, pc} 800135e: bf00 nop 8001360: 20000cc0 .word 0x20000cc0 08001364 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 8001364: b580 push {r7, lr} 8001366: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_rx); 8001368: 4802 ldr r0, [pc, #8] @ (8001374 ) 800136a: f001 f885 bl 8002478 /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 800136e: bf00 nop 8001370: bd80 pop {r7, pc} 8001372: bf00 nop 8001374: 20000c00 .word 0x20000c00 08001378 : /** * @brief This function handles DMA1 stream4 global interrupt. */ void DMA1_Stream4_IRQHandler(void) { 8001378: b580 push {r7, lr} 800137a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ /* USER CODE END DMA1_Stream4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_tx); 800137c: 4802 ldr r0, [pc, #8] @ (8001388 ) 800137e: f001 f87b bl 8002478 /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ /* USER CODE END DMA1_Stream4_IRQn 1 */ } 8001382: bf00 nop 8001384: bd80 pop {r7, pc} 8001386: bf00 nop 8001388: 20000c60 .word 0x20000c60 0800138c : /** * @brief This function handles DMA1 stream5 global interrupt. */ void DMA1_Stream5_IRQHandler(void) { 800138c: b580 push {r7, lr} 800138e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ /* USER CODE END DMA1_Stream5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 8001390: 4802 ldr r0, [pc, #8] @ (800139c ) 8001392: f001 f871 bl 8002478 /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ /* USER CODE END DMA1_Stream5_IRQn 1 */ } 8001396: bf00 nop 8001398: bd80 pop {r7, pc} 800139a: bf00 nop 800139c: 20000e40 .word 0x20000e40 080013a0 : /** * @brief This function handles DMA1 stream6 global interrupt. */ void DMA1_Stream6_IRQHandler(void) { 80013a0: b580 push {r7, lr} 80013a2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ /* USER CODE END DMA1_Stream6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 80013a4: 4802 ldr r0, [pc, #8] @ (80013b0 ) 80013a6: f001 f867 bl 8002478 /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ /* USER CODE END DMA1_Stream6_IRQn 1 */ } 80013aa: bf00 nop 80013ac: bd80 pop {r7, pc} 80013ae: bf00 nop 80013b0: 20000ea0 .word 0x20000ea0 080013b4 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 80013b4: b580 push {r7, lr} 80013b6: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 80013b8: 4802 ldr r0, [pc, #8] @ (80013c4 ) 80013ba: f005 fb23 bl 8006a04 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 80013be: bf00 nop 80013c0: bd80 pop {r7, pc} 80013c2: bf00 nop 80013c4: 20000b70 .word 0x20000b70 080013c8 : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 80013c8: b580 push {r7, lr} 80013ca: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 80013cc: 4802 ldr r0, [pc, #8] @ (80013d8 ) 80013ce: f005 fb19 bl 8006a04 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 80013d2: bf00 nop 80013d4: bd80 pop {r7, pc} 80013d6: bf00 nop 80013d8: 20000bb8 .word 0x20000bb8 080013dc : /** * @brief This function handles DMA1 stream7 global interrupt. */ void DMA1_Stream7_IRQHandler(void) { 80013dc: b580 push {r7, lr} 80013de: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ /* USER CODE END DMA1_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_tx); 80013e0: 4802 ldr r0, [pc, #8] @ (80013ec ) 80013e2: f001 f849 bl 8002478 /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ /* USER CODE END DMA1_Stream7_IRQn 1 */ } 80013e6: bf00 nop 80013e8: bd80 pop {r7, pc} 80013ea: bf00 nop 80013ec: 20000d20 .word 0x20000d20 080013f0 : /** * @brief This function handles UART4 global interrupt. */ void UART4_IRQHandler(void) { 80013f0: b580 push {r7, lr} 80013f2: af00 add r7, sp, #0 /* USER CODE BEGIN UART4_IRQn 0 */ /* USER CODE END UART4_IRQn 0 */ HAL_UART_IRQHandler(&huart4); 80013f4: 4802 ldr r0, [pc, #8] @ (8001400 ) 80013f6: f005 fb05 bl 8006a04 /* USER CODE BEGIN UART4_IRQn 1 */ /* USER CODE END UART4_IRQn 1 */ } 80013fa: bf00 nop 80013fc: bd80 pop {r7, pc} 80013fe: bf00 nop 8001400: 20000ae0 .word 0x20000ae0 08001404 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 8001404: b580 push {r7, lr} 8001406: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 8001408: 4802 ldr r0, [pc, #8] @ (8001414 ) 800140a: f005 fafb bl 8006a04 /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 800140e: bf00 nop 8001410: bd80 pop {r7, pc} 8001412: bf00 nop 8001414: 20000b28 .word 0x20000b28 08001418 : /** * @brief This function handles DMA2 stream2 global interrupt. */ void DMA2_Stream2_IRQHandler(void) { 8001418: b580 push {r7, lr} 800141a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ /* USER CODE END DMA2_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_rx); 800141c: 4802 ldr r0, [pc, #8] @ (8001428 ) 800141e: f001 f82b bl 8002478 /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ /* USER CODE END DMA2_Stream2_IRQn 1 */ } 8001422: bf00 nop 8001424: bd80 pop {r7, pc} 8001426: bf00 nop 8001428: 20000d80 .word 0x20000d80 0800142c : /** * @brief This function handles USB On The Go FS global interrupt. */ void OTG_FS_IRQHandler(void) { 800142c: b580 push {r7, lr} 800142e: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_FS_IRQn 0 */ /* USER CODE END OTG_FS_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); 8001430: 4802 ldr r0, [pc, #8] @ (800143c ) 8001432: f001 fee0 bl 80031f6 /* USER CODE BEGIN OTG_FS_IRQn 1 */ /* USER CODE END OTG_FS_IRQn 1 */ } 8001436: bf00 nop 8001438: bd80 pop {r7, pc} 800143a: bf00 nop 800143c: 200013e4 .word 0x200013e4 08001440 : /** * @brief This function handles DMA2 stream7 global interrupt. */ void DMA2_Stream7_IRQHandler(void) { 8001440: b580 push {r7, lr} 8001442: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ /* USER CODE END DMA2_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 8001444: 4802 ldr r0, [pc, #8] @ (8001450 ) 8001446: f001 f817 bl 8002478 /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ /* USER CODE END DMA2_Stream7_IRQn 1 */ } 800144a: bf00 nop 800144c: bd80 pop {r7, pc} 800144e: bf00 nop 8001450: 20000de0 .word 0x20000de0 08001454 : * configuration. * @param None * @retval None */ void SystemInit(void) { 8001454: b480 push {r7} 8001456: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8001458: 4b06 ldr r3, [pc, #24] @ (8001474 ) 800145a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800145e: 4a05 ldr r2, [pc, #20] @ (8001474 ) 8001460: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8001464: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8001468: bf00 nop 800146a: 46bd mov sp, r7 800146c: f85d 7b04 ldr.w r7, [sp], #4 8001470: 4770 bx lr 8001472: bf00 nop 8001474: e000ed00 .word 0xe000ed00 08001478 : TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; void MX_TIM2_Init(void) { 8001478: b580 push {r7, lr} 800147a: b088 sub sp, #32 800147c: af00 add r7, sp, #0 TIM_OC_InitTypeDef sConfigOC = {0}; 800147e: 1d3b adds r3, r7, #4 8001480: 2200 movs r2, #0 8001482: 601a str r2, [r3, #0] 8001484: 605a str r2, [r3, #4] 8001486: 609a str r2, [r3, #8] 8001488: 60da str r2, [r3, #12] 800148a: 611a str r2, [r3, #16] 800148c: 615a str r2, [r3, #20] 800148e: 619a str r2, [r3, #24] htim2.Instance = TIM2; 8001490: 4b1a ldr r3, [pc, #104] @ (80014fc ) 8001492: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 8001496: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 8001498: 4b18 ldr r3, [pc, #96] @ (80014fc ) 800149a: 2200 movs r2, #0 800149c: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 800149e: 4b17 ldr r3, [pc, #92] @ (80014fc ) 80014a0: 2200 movs r2, #0 80014a2: 609a str r2, [r3, #8] htim2.Init.Period = 9; 80014a4: 4b15 ldr r3, [pc, #84] @ (80014fc ) 80014a6: 2209 movs r2, #9 80014a8: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80014aa: 4b14 ldr r3, [pc, #80] @ (80014fc ) 80014ac: 2200 movs r2, #0 80014ae: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80014b0: 4b12 ldr r3, [pc, #72] @ (80014fc ) 80014b2: 2200 movs r2, #0 80014b4: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) Error_Handler(); 80014b6: 4811 ldr r0, [pc, #68] @ (80014fc ) 80014b8: f004 f8ea bl 8005690 80014bc: 4603 mov r3, r0 80014be: 2b00 cmp r3, #0 80014c0: d001 beq.n 80014c6 80014c2: f7ff fee7 bl 8001294 sConfigOC.OCMode = TIM_OCMODE_PWM1; 80014c6: 2360 movs r3, #96 @ 0x60 80014c8: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 80014ca: 2300 movs r3, #0 80014cc: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 80014ce: 2300 movs r3, #0 80014d0: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 80014d2: 2300 movs r3, #0 80014d4: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) Error_Handler(); 80014d6: 1d3b adds r3, r7, #4 80014d8: 2200 movs r2, #0 80014da: 4619 mov r1, r3 80014dc: 4807 ldr r0, [pc, #28] @ (80014fc ) 80014de: f004 fcff bl 8005ee0 80014e2: 4603 mov r3, r0 80014e4: 2b00 cmp r3, #0 80014e6: d001 beq.n 80014ec 80014e8: f7ff fed4 bl 8001294 HAL_TIM_MspPostInit(&htim2); 80014ec: 4803 ldr r0, [pc, #12] @ (80014fc ) 80014ee: f000 f8b7 bl 8001660 } 80014f2: bf00 nop 80014f4: 3720 adds r7, #32 80014f6: 46bd mov sp, r7 80014f8: bd80 pop {r7, pc} 80014fa: bf00 nop 80014fc: 20000a50 .word 0x20000a50 08001500 : void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8001500: b580 push {r7, lr} 8001502: b082 sub sp, #8 8001504: af00 add r7, sp, #0 8001506: 6078 str r0, [r7, #4] if (htim->Instance == TIM2) { 8001508: 687b ldr r3, [r7, #4] 800150a: 681b ldr r3, [r3, #0] 800150c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001510: d103 bne.n 800151a HAL_TIM_PWM_Stop_DMA(&htim2, TIM_CHANNEL_1); 8001512: 2100 movs r1, #0 8001514: 4803 ldr r0, [pc, #12] @ (8001524 ) 8001516: f004 fadd bl 8005ad4 } } 800151a: bf00 nop 800151c: 3708 adds r7, #8 800151e: 46bd mov sp, r7 8001520: bd80 pop {r7, pc} 8001522: bf00 nop 8001524: 20000a50 .word 0x20000a50 08001528 : /* TIM3 init function */ void MX_TIM3_Init(void) { 8001528: b580 push {r7, lr} 800152a: b08c sub sp, #48 @ 0x30 800152c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_Encoder_InitTypeDef sConfig = {0}; 800152e: f107 030c add.w r3, r7, #12 8001532: 2224 movs r2, #36 @ 0x24 8001534: 2100 movs r1, #0 8001536: 4618 mov r0, r3 8001538: f00a f8e6 bl 800b708 TIM_MasterConfigTypeDef sMasterConfig = {0}; 800153c: 1d3b adds r3, r7, #4 800153e: 2200 movs r2, #0 8001540: 601a str r2, [r3, #0] 8001542: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8001544: 4b20 ldr r3, [pc, #128] @ (80015c8 ) 8001546: 4a21 ldr r2, [pc, #132] @ (80015cc ) 8001548: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800154a: 4b1f ldr r3, [pc, #124] @ (80015c8 ) 800154c: 2200 movs r2, #0 800154e: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8001550: 4b1d ldr r3, [pc, #116] @ (80015c8 ) 8001552: 2200 movs r2, #0 8001554: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 8001556: 4b1c ldr r3, [pc, #112] @ (80015c8 ) 8001558: f64f 72ff movw r2, #65535 @ 0xffff 800155c: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800155e: 4b1a ldr r3, [pc, #104] @ (80015c8 ) 8001560: 2200 movs r2, #0 8001562: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001564: 4b18 ldr r3, [pc, #96] @ (80015c8 ) 8001566: 2200 movs r2, #0 8001568: 619a str r2, [r3, #24] sConfig.EncoderMode = TIM_ENCODERMODE_TI1; 800156a: 2301 movs r3, #1 800156c: 60fb str r3, [r7, #12] sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; 800156e: 2300 movs r3, #0 8001570: 613b str r3, [r7, #16] sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; 8001572: 2301 movs r3, #1 8001574: 617b str r3, [r7, #20] sConfig.IC1Prescaler = TIM_ICPSC_DIV1; 8001576: 2300 movs r3, #0 8001578: 61bb str r3, [r7, #24] sConfig.IC1Filter = 0; 800157a: 2300 movs r3, #0 800157c: 61fb str r3, [r7, #28] sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; 800157e: 2300 movs r3, #0 8001580: 623b str r3, [r7, #32] sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; 8001582: 2301 movs r3, #1 8001584: 627b str r3, [r7, #36] @ 0x24 sConfig.IC2Prescaler = TIM_ICPSC_DIV1; 8001586: 2300 movs r3, #0 8001588: 62bb str r3, [r7, #40] @ 0x28 sConfig.IC2Filter = 0; 800158a: 2300 movs r3, #0 800158c: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) 800158e: f107 030c add.w r3, r7, #12 8001592: 4619 mov r1, r3 8001594: 480c ldr r0, [pc, #48] @ (80015c8 ) 8001596: f004 fb6f bl 8005c78 800159a: 4603 mov r3, r0 800159c: 2b00 cmp r3, #0 800159e: d001 beq.n 80015a4 { Error_Handler(); 80015a0: f7ff fe78 bl 8001294 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80015a4: 2300 movs r3, #0 80015a6: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80015a8: 2300 movs r3, #0 80015aa: 60bb str r3, [r7, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80015ac: 1d3b adds r3, r7, #4 80015ae: 4619 mov r1, r3 80015b0: 4805 ldr r0, [pc, #20] @ (80015c8 ) 80015b2: f005 f8b9 bl 8006728 80015b6: 4603 mov r3, r0 80015b8: 2b00 cmp r3, #0 80015ba: d001 beq.n 80015c0 { Error_Handler(); 80015bc: f7ff fe6a bl 8001294 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 80015c0: bf00 nop 80015c2: 3730 adds r7, #48 @ 0x30 80015c4: 46bd mov sp, r7 80015c6: bd80 pop {r7, pc} 80015c8: 20000a98 .word 0x20000a98 80015cc: 40000400 .word 0x40000400 080015d0 : /* USER CODE END TIM2_MspInit 1 */ } } void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) { 80015d0: b580 push {r7, lr} 80015d2: b08a sub sp, #40 @ 0x28 80015d4: af00 add r7, sp, #0 80015d6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80015d8: f107 0314 add.w r3, r7, #20 80015dc: 2200 movs r2, #0 80015de: 601a str r2, [r3, #0] 80015e0: 605a str r2, [r3, #4] 80015e2: 609a str r2, [r3, #8] 80015e4: 60da str r2, [r3, #12] 80015e6: 611a str r2, [r3, #16] if(tim_encoderHandle->Instance==TIM3) 80015e8: 687b ldr r3, [r7, #4] 80015ea: 681b ldr r3, [r3, #0] 80015ec: 4a19 ldr r2, [pc, #100] @ (8001654 ) 80015ee: 4293 cmp r3, r2 80015f0: d12b bne.n 800164a { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 80015f2: 2300 movs r3, #0 80015f4: 613b str r3, [r7, #16] 80015f6: 4b18 ldr r3, [pc, #96] @ (8001658 ) 80015f8: 6c1b ldr r3, [r3, #64] @ 0x40 80015fa: 4a17 ldr r2, [pc, #92] @ (8001658 ) 80015fc: f043 0302 orr.w r3, r3, #2 8001600: 6413 str r3, [r2, #64] @ 0x40 8001602: 4b15 ldr r3, [pc, #84] @ (8001658 ) 8001604: 6c1b ldr r3, [r3, #64] @ 0x40 8001606: f003 0302 and.w r3, r3, #2 800160a: 613b str r3, [r7, #16] 800160c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800160e: 2300 movs r3, #0 8001610: 60fb str r3, [r7, #12] 8001612: 4b11 ldr r3, [pc, #68] @ (8001658 ) 8001614: 6b1b ldr r3, [r3, #48] @ 0x30 8001616: 4a10 ldr r2, [pc, #64] @ (8001658 ) 8001618: f043 0301 orr.w r3, r3, #1 800161c: 6313 str r3, [r2, #48] @ 0x30 800161e: 4b0e ldr r3, [pc, #56] @ (8001658 ) 8001620: 6b1b ldr r3, [r3, #48] @ 0x30 8001622: f003 0301 and.w r3, r3, #1 8001626: 60fb str r3, [r7, #12] 8001628: 68fb ldr r3, [r7, #12] /**TIM3 GPIO Configuration PA6 ------> TIM3_CH1 PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 800162a: 23c0 movs r3, #192 @ 0xc0 800162c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800162e: 2302 movs r3, #2 8001630: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001632: 2300 movs r3, #0 8001634: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001636: 2300 movs r3, #0 8001638: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 800163a: 2302 movs r3, #2 800163c: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800163e: f107 0314 add.w r3, r7, #20 8001642: 4619 mov r1, r3 8001644: 4805 ldr r0, [pc, #20] @ (800165c ) 8001646: f001 f981 bl 800294c /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 800164a: bf00 nop 800164c: 3728 adds r7, #40 @ 0x28 800164e: 46bd mov sp, r7 8001650: bd80 pop {r7, pc} 8001652: bf00 nop 8001654: 40000400 .word 0x40000400 8001658: 40023800 .word 0x40023800 800165c: 40020000 .word 0x40020000 08001660 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 8001660: b580 push {r7, lr} 8001662: b088 sub sp, #32 8001664: af00 add r7, sp, #0 8001666: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001668: f107 030c add.w r3, r7, #12 800166c: 2200 movs r2, #0 800166e: 601a str r2, [r3, #0] 8001670: 605a str r2, [r3, #4] 8001672: 609a str r2, [r3, #8] 8001674: 60da str r2, [r3, #12] 8001676: 611a str r2, [r3, #16] if(timHandle->Instance==TIM2) 8001678: 687b ldr r3, [r7, #4] 800167a: 681b ldr r3, [r3, #0] 800167c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001680: d11d bne.n 80016be { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8001682: 2300 movs r3, #0 8001684: 60bb str r3, [r7, #8] 8001686: 4b10 ldr r3, [pc, #64] @ (80016c8 ) 8001688: 6b1b ldr r3, [r3, #48] @ 0x30 800168a: 4a0f ldr r2, [pc, #60] @ (80016c8 ) 800168c: f043 0301 orr.w r3, r3, #1 8001690: 6313 str r3, [r2, #48] @ 0x30 8001692: 4b0d ldr r3, [pc, #52] @ (80016c8 ) 8001694: 6b1b ldr r3, [r3, #48] @ 0x30 8001696: f003 0301 and.w r3, r3, #1 800169a: 60bb str r3, [r7, #8] 800169c: 68bb ldr r3, [r7, #8] /**TIM2 GPIO Configuration PA5 ------> TIM2_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_5; 800169e: 2320 movs r3, #32 80016a0: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80016a2: 2302 movs r3, #2 80016a4: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 80016a6: 2300 movs r3, #0 80016a8: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80016aa: 2300 movs r3, #0 80016ac: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 80016ae: 2301 movs r3, #1 80016b0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80016b2: f107 030c add.w r3, r7, #12 80016b6: 4619 mov r1, r3 80016b8: 4804 ldr r0, [pc, #16] @ (80016cc ) 80016ba: f001 f947 bl 800294c /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 80016be: bf00 nop 80016c0: 3720 adds r7, #32 80016c2: 46bd mov sp, r7 80016c4: bd80 pop {r7, pc} 80016c6: bf00 nop 80016c8: 40023800 .word 0x40023800 80016cc: 40020000 .word 0x40020000 080016d0 : DMA_HandleTypeDef hdma_usart2_rx; DMA_HandleTypeDef hdma_usart2_tx; /* UART4 init function */ void MX_UART4_Init(void) { 80016d0: b580 push {r7, lr} 80016d2: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; 80016d4: 4b11 ldr r3, [pc, #68] @ (800171c ) 80016d6: 4a12 ldr r2, [pc, #72] @ (8001720 ) 80016d8: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; 80016da: 4b10 ldr r3, [pc, #64] @ (800171c ) 80016dc: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80016e0: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; 80016e2: 4b0e ldr r3, [pc, #56] @ (800171c ) 80016e4: 2200 movs r2, #0 80016e6: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; 80016e8: 4b0c ldr r3, [pc, #48] @ (800171c ) 80016ea: 2200 movs r2, #0 80016ec: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; 80016ee: 4b0b ldr r3, [pc, #44] @ (800171c ) 80016f0: 2200 movs r2, #0 80016f2: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; 80016f4: 4b09 ldr r3, [pc, #36] @ (800171c ) 80016f6: 220c movs r2, #12 80016f8: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80016fa: 4b08 ldr r3, [pc, #32] @ (800171c ) 80016fc: 2200 movs r2, #0 80016fe: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; 8001700: 4b06 ldr r3, [pc, #24] @ (800171c ) 8001702: 2200 movs r2, #0 8001704: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart4) != HAL_OK) 8001706: 4805 ldr r0, [pc, #20] @ (800171c ) 8001708: f005 f88a bl 8006820 800170c: 4603 mov r3, r0 800170e: 2b00 cmp r3, #0 8001710: d001 beq.n 8001716 { Error_Handler(); 8001712: f7ff fdbf bl 8001294 } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } 8001716: bf00 nop 8001718: bd80 pop {r7, pc} 800171a: bf00 nop 800171c: 20000ae0 .word 0x20000ae0 8001720: 40004c00 .word 0x40004c00 08001724 : /* UART5 init function */ void MX_UART5_Init(void) { 8001724: b580 push {r7, lr} 8001726: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 8001728: 4b11 ldr r3, [pc, #68] @ (8001770 ) 800172a: 4a12 ldr r2, [pc, #72] @ (8001774 ) 800172c: 601a str r2, [r3, #0] huart5.Init.BaudRate = 115200; 800172e: 4b10 ldr r3, [pc, #64] @ (8001770 ) 8001730: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001734: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 8001736: 4b0e ldr r3, [pc, #56] @ (8001770 ) 8001738: 2200 movs r2, #0 800173a: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 800173c: 4b0c ldr r3, [pc, #48] @ (8001770 ) 800173e: 2200 movs r2, #0 8001740: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 8001742: 4b0b ldr r3, [pc, #44] @ (8001770 ) 8001744: 2200 movs r2, #0 8001746: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 8001748: 4b09 ldr r3, [pc, #36] @ (8001770 ) 800174a: 220c movs r2, #12 800174c: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800174e: 4b08 ldr r3, [pc, #32] @ (8001770 ) 8001750: 2200 movs r2, #0 8001752: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 8001754: 4b06 ldr r3, [pc, #24] @ (8001770 ) 8001756: 2200 movs r2, #0 8001758: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 800175a: 4805 ldr r0, [pc, #20] @ (8001770 ) 800175c: f005 f860 bl 8006820 8001760: 4603 mov r3, r0 8001762: 2b00 cmp r3, #0 8001764: d001 beq.n 800176a { Error_Handler(); 8001766: f7ff fd95 bl 8001294 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 800176a: bf00 nop 800176c: bd80 pop {r7, pc} 800176e: bf00 nop 8001770: 20000b28 .word 0x20000b28 8001774: 40005000 .word 0x40005000 08001778 : /* USART1 init function */ void MX_USART1_UART_Init(void) { 8001778: b580 push {r7, lr} 800177a: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800177c: 4b11 ldr r3, [pc, #68] @ (80017c4 ) 800177e: 4a12 ldr r2, [pc, #72] @ (80017c8 ) 8001780: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8001782: 4b10 ldr r3, [pc, #64] @ (80017c4 ) 8001784: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001788: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800178a: 4b0e ldr r3, [pc, #56] @ (80017c4 ) 800178c: 2200 movs r2, #0 800178e: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8001790: 4b0c ldr r3, [pc, #48] @ (80017c4 ) 8001792: 2200 movs r2, #0 8001794: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8001796: 4b0b ldr r3, [pc, #44] @ (80017c4 ) 8001798: 2200 movs r2, #0 800179a: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 800179c: 4b09 ldr r3, [pc, #36] @ (80017c4 ) 800179e: 220c movs r2, #12 80017a0: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80017a2: 4b08 ldr r3, [pc, #32] @ (80017c4 ) 80017a4: 2200 movs r2, #0 80017a6: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80017a8: 4b06 ldr r3, [pc, #24] @ (80017c4 ) 80017aa: 2200 movs r2, #0 80017ac: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 80017ae: 4805 ldr r0, [pc, #20] @ (80017c4 ) 80017b0: f005 f836 bl 8006820 80017b4: 4603 mov r3, r0 80017b6: 2b00 cmp r3, #0 80017b8: d001 beq.n 80017be { Error_Handler(); 80017ba: f7ff fd6b bl 8001294 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 80017be: bf00 nop 80017c0: bd80 pop {r7, pc} 80017c2: bf00 nop 80017c4: 20000b70 .word 0x20000b70 80017c8: 40011000 .word 0x40011000 080017cc : /* USART2 init function */ void MX_USART2_UART_Init(void) { 80017cc: b580 push {r7, lr} 80017ce: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 80017d0: 4b11 ldr r3, [pc, #68] @ (8001818 ) 80017d2: 4a12 ldr r2, [pc, #72] @ (800181c ) 80017d4: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 80017d6: 4b10 ldr r3, [pc, #64] @ (8001818 ) 80017d8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80017dc: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 80017de: 4b0e ldr r3, [pc, #56] @ (8001818 ) 80017e0: 2200 movs r2, #0 80017e2: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 80017e4: 4b0c ldr r3, [pc, #48] @ (8001818 ) 80017e6: 2200 movs r2, #0 80017e8: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 80017ea: 4b0b ldr r3, [pc, #44] @ (8001818 ) 80017ec: 2200 movs r2, #0 80017ee: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 80017f0: 4b09 ldr r3, [pc, #36] @ (8001818 ) 80017f2: 220c movs r2, #12 80017f4: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80017f6: 4b08 ldr r3, [pc, #32] @ (8001818 ) 80017f8: 2200 movs r2, #0 80017fa: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 80017fc: 4b06 ldr r3, [pc, #24] @ (8001818 ) 80017fe: 2200 movs r2, #0 8001800: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 8001802: 4805 ldr r0, [pc, #20] @ (8001818 ) 8001804: f005 f80c bl 8006820 8001808: 4603 mov r3, r0 800180a: 2b00 cmp r3, #0 800180c: d001 beq.n 8001812 { Error_Handler(); 800180e: f7ff fd41 bl 8001294 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8001812: bf00 nop 8001814: bd80 pop {r7, pc} 8001816: bf00 nop 8001818: 20000bb8 .word 0x20000bb8 800181c: 40004400 .word 0x40004400 08001820 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8001820: b580 push {r7, lr} 8001822: b090 sub sp, #64 @ 0x40 8001824: af00 add r7, sp, #0 8001826: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001828: f107 032c add.w r3, r7, #44 @ 0x2c 800182c: 2200 movs r2, #0 800182e: 601a str r2, [r3, #0] 8001830: 605a str r2, [r3, #4] 8001832: 609a str r2, [r3, #8] 8001834: 60da str r2, [r3, #12] 8001836: 611a str r2, [r3, #16] if(uartHandle->Instance==UART4) 8001838: 687b ldr r3, [r7, #4] 800183a: 681b ldr r3, [r3, #0] 800183c: 4a4a ldr r2, [pc, #296] @ (8001968 ) 800183e: 4293 cmp r3, r2 8001840: f040 80a0 bne.w 8001984 { /* USER CODE BEGIN UART4_MspInit 0 */ /* USER CODE END UART4_MspInit 0 */ /* UART4 clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); 8001844: 2300 movs r3, #0 8001846: 62bb str r3, [r7, #40] @ 0x28 8001848: 4b48 ldr r3, [pc, #288] @ (800196c ) 800184a: 6c1b ldr r3, [r3, #64] @ 0x40 800184c: 4a47 ldr r2, [pc, #284] @ (800196c ) 800184e: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8001852: 6413 str r3, [r2, #64] @ 0x40 8001854: 4b45 ldr r3, [pc, #276] @ (800196c ) 8001856: 6c1b ldr r3, [r3, #64] @ 0x40 8001858: f403 2300 and.w r3, r3, #524288 @ 0x80000 800185c: 62bb str r3, [r7, #40] @ 0x28 800185e: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOA_CLK_ENABLE(); 8001860: 2300 movs r3, #0 8001862: 627b str r3, [r7, #36] @ 0x24 8001864: 4b41 ldr r3, [pc, #260] @ (800196c ) 8001866: 6b1b ldr r3, [r3, #48] @ 0x30 8001868: 4a40 ldr r2, [pc, #256] @ (800196c ) 800186a: f043 0301 orr.w r3, r3, #1 800186e: 6313 str r3, [r2, #48] @ 0x30 8001870: 4b3e ldr r3, [pc, #248] @ (800196c ) 8001872: 6b1b ldr r3, [r3, #48] @ 0x30 8001874: f003 0301 and.w r3, r3, #1 8001878: 627b str r3, [r7, #36] @ 0x24 800187a: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART4 GPIO Configuration PA0-WKUP ------> UART4_TX PA1 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 800187c: 2303 movs r3, #3 800187e: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001880: 2302 movs r3, #2 8001882: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001884: 2300 movs r3, #0 8001886: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001888: 2303 movs r3, #3 800188a: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 800188c: 2308 movs r3, #8 800188e: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001890: f107 032c add.w r3, r7, #44 @ 0x2c 8001894: 4619 mov r1, r3 8001896: 4836 ldr r0, [pc, #216] @ (8001970 ) 8001898: f001 f858 bl 800294c /* UART4 DMA Init */ /* UART4_RX Init */ hdma_uart4_rx.Instance = DMA1_Stream2; 800189c: 4b35 ldr r3, [pc, #212] @ (8001974 ) 800189e: 4a36 ldr r2, [pc, #216] @ (8001978 ) 80018a0: 601a str r2, [r3, #0] hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4; 80018a2: 4b34 ldr r3, [pc, #208] @ (8001974 ) 80018a4: f04f 6200 mov.w r2, #134217728 @ 0x8000000 80018a8: 605a str r2, [r3, #4] hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80018aa: 4b32 ldr r3, [pc, #200] @ (8001974 ) 80018ac: 2200 movs r2, #0 80018ae: 609a str r2, [r3, #8] hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE; 80018b0: 4b30 ldr r3, [pc, #192] @ (8001974 ) 80018b2: 2200 movs r2, #0 80018b4: 60da str r2, [r3, #12] hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE; 80018b6: 4b2f ldr r3, [pc, #188] @ (8001974 ) 80018b8: f44f 6280 mov.w r2, #1024 @ 0x400 80018bc: 611a str r2, [r3, #16] hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80018be: 4b2d ldr r3, [pc, #180] @ (8001974 ) 80018c0: 2200 movs r2, #0 80018c2: 615a str r2, [r3, #20] hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80018c4: 4b2b ldr r3, [pc, #172] @ (8001974 ) 80018c6: 2200 movs r2, #0 80018c8: 619a str r2, [r3, #24] hdma_uart4_rx.Init.Mode = DMA_NORMAL; 80018ca: 4b2a ldr r3, [pc, #168] @ (8001974 ) 80018cc: 2200 movs r2, #0 80018ce: 61da str r2, [r3, #28] hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW; 80018d0: 4b28 ldr r3, [pc, #160] @ (8001974 ) 80018d2: 2200 movs r2, #0 80018d4: 621a str r2, [r3, #32] hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80018d6: 4b27 ldr r3, [pc, #156] @ (8001974 ) 80018d8: 2200 movs r2, #0 80018da: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK) 80018dc: 4825 ldr r0, [pc, #148] @ (8001974 ) 80018de: f000 fc33 bl 8002148 80018e2: 4603 mov r3, r0 80018e4: 2b00 cmp r3, #0 80018e6: d001 beq.n 80018ec { Error_Handler(); 80018e8: f7ff fcd4 bl 8001294 } __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx); 80018ec: 687b ldr r3, [r7, #4] 80018ee: 4a21 ldr r2, [pc, #132] @ (8001974 ) 80018f0: 63da str r2, [r3, #60] @ 0x3c 80018f2: 4a20 ldr r2, [pc, #128] @ (8001974 ) 80018f4: 687b ldr r3, [r7, #4] 80018f6: 6393 str r3, [r2, #56] @ 0x38 /* UART4_TX Init */ hdma_uart4_tx.Instance = DMA1_Stream4; 80018f8: 4b20 ldr r3, [pc, #128] @ (800197c ) 80018fa: 4a21 ldr r2, [pc, #132] @ (8001980 ) 80018fc: 601a str r2, [r3, #0] hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4; 80018fe: 4b1f ldr r3, [pc, #124] @ (800197c ) 8001900: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001904: 605a str r2, [r3, #4] hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001906: 4b1d ldr r3, [pc, #116] @ (800197c ) 8001908: 2240 movs r2, #64 @ 0x40 800190a: 609a str r2, [r3, #8] hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800190c: 4b1b ldr r3, [pc, #108] @ (800197c ) 800190e: 2200 movs r2, #0 8001910: 60da str r2, [r3, #12] hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE; 8001912: 4b1a ldr r3, [pc, #104] @ (800197c ) 8001914: f44f 6280 mov.w r2, #1024 @ 0x400 8001918: 611a str r2, [r3, #16] hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800191a: 4b18 ldr r3, [pc, #96] @ (800197c ) 800191c: 2200 movs r2, #0 800191e: 615a str r2, [r3, #20] hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001920: 4b16 ldr r3, [pc, #88] @ (800197c ) 8001922: 2200 movs r2, #0 8001924: 619a str r2, [r3, #24] hdma_uart4_tx.Init.Mode = DMA_NORMAL; 8001926: 4b15 ldr r3, [pc, #84] @ (800197c ) 8001928: 2200 movs r2, #0 800192a: 61da str r2, [r3, #28] hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW; 800192c: 4b13 ldr r3, [pc, #76] @ (800197c ) 800192e: 2200 movs r2, #0 8001930: 621a str r2, [r3, #32] hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001932: 4b12 ldr r3, [pc, #72] @ (800197c ) 8001934: 2200 movs r2, #0 8001936: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK) 8001938: 4810 ldr r0, [pc, #64] @ (800197c ) 800193a: f000 fc05 bl 8002148 800193e: 4603 mov r3, r0 8001940: 2b00 cmp r3, #0 8001942: d001 beq.n 8001948 { Error_Handler(); 8001944: f7ff fca6 bl 8001294 } __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); 8001948: 687b ldr r3, [r7, #4] 800194a: 4a0c ldr r2, [pc, #48] @ (800197c ) 800194c: 639a str r2, [r3, #56] @ 0x38 800194e: 4a0b ldr r2, [pc, #44] @ (800197c ) 8001950: 687b ldr r3, [r7, #4] 8001952: 6393 str r3, [r2, #56] @ 0x38 /* UART4 interrupt Init */ HAL_NVIC_SetPriority(UART4_IRQn, 5, 0); 8001954: 2200 movs r2, #0 8001956: 2105 movs r1, #5 8001958: 2034 movs r0, #52 @ 0x34 800195a: f000 fbbe bl 80020da HAL_NVIC_EnableIRQ(UART4_IRQn); 800195e: 2034 movs r0, #52 @ 0x34 8001960: f000 fbd7 bl 8002112 HAL_NVIC_EnableIRQ(USART2_IRQn); /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8001964: e202 b.n 8001d6c 8001966: bf00 nop 8001968: 40004c00 .word 0x40004c00 800196c: 40023800 .word 0x40023800 8001970: 40020000 .word 0x40020000 8001974: 20000c00 .word 0x20000c00 8001978: 40026040 .word 0x40026040 800197c: 20000c60 .word 0x20000c60 8001980: 40026070 .word 0x40026070 else if(uartHandle->Instance==UART5) 8001984: 687b ldr r3, [r7, #4] 8001986: 681b ldr r3, [r3, #0] 8001988: 4a59 ldr r2, [pc, #356] @ (8001af0 ) 800198a: 4293 cmp r3, r2 800198c: f040 80c0 bne.w 8001b10 __HAL_RCC_UART5_CLK_ENABLE(); 8001990: 2300 movs r3, #0 8001992: 623b str r3, [r7, #32] 8001994: 4b57 ldr r3, [pc, #348] @ (8001af4 ) 8001996: 6c1b ldr r3, [r3, #64] @ 0x40 8001998: 4a56 ldr r2, [pc, #344] @ (8001af4 ) 800199a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800199e: 6413 str r3, [r2, #64] @ 0x40 80019a0: 4b54 ldr r3, [pc, #336] @ (8001af4 ) 80019a2: 6c1b ldr r3, [r3, #64] @ 0x40 80019a4: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80019a8: 623b str r3, [r7, #32] 80019aa: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOC_CLK_ENABLE(); 80019ac: 2300 movs r3, #0 80019ae: 61fb str r3, [r7, #28] 80019b0: 4b50 ldr r3, [pc, #320] @ (8001af4 ) 80019b2: 6b1b ldr r3, [r3, #48] @ 0x30 80019b4: 4a4f ldr r2, [pc, #316] @ (8001af4 ) 80019b6: f043 0304 orr.w r3, r3, #4 80019ba: 6313 str r3, [r2, #48] @ 0x30 80019bc: 4b4d ldr r3, [pc, #308] @ (8001af4 ) 80019be: 6b1b ldr r3, [r3, #48] @ 0x30 80019c0: f003 0304 and.w r3, r3, #4 80019c4: 61fb str r3, [r7, #28] 80019c6: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOD_CLK_ENABLE(); 80019c8: 2300 movs r3, #0 80019ca: 61bb str r3, [r7, #24] 80019cc: 4b49 ldr r3, [pc, #292] @ (8001af4 ) 80019ce: 6b1b ldr r3, [r3, #48] @ 0x30 80019d0: 4a48 ldr r2, [pc, #288] @ (8001af4 ) 80019d2: f043 0308 orr.w r3, r3, #8 80019d6: 6313 str r3, [r2, #48] @ 0x30 80019d8: 4b46 ldr r3, [pc, #280] @ (8001af4 ) 80019da: 6b1b ldr r3, [r3, #48] @ 0x30 80019dc: f003 0308 and.w r3, r3, #8 80019e0: 61bb str r3, [r7, #24] 80019e2: 69bb ldr r3, [r7, #24] GPIO_InitStruct.Pin = GPIO_PIN_12; 80019e4: f44f 5380 mov.w r3, #4096 @ 0x1000 80019e8: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80019ea: 2302 movs r3, #2 80019ec: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80019ee: 2300 movs r3, #0 80019f0: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80019f2: 2303 movs r3, #3 80019f4: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 80019f6: 2308 movs r3, #8 80019f8: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80019fa: f107 032c add.w r3, r7, #44 @ 0x2c 80019fe: 4619 mov r1, r3 8001a00: 483d ldr r0, [pc, #244] @ (8001af8 ) 8001a02: f000 ffa3 bl 800294c GPIO_InitStruct.Pin = GPIO_PIN_2; 8001a06: 2304 movs r3, #4 8001a08: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001a0a: 2302 movs r3, #2 8001a0c: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001a0e: 2300 movs r3, #0 8001a10: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001a12: 2303 movs r3, #3 8001a14: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 8001a16: 2308 movs r3, #8 8001a18: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001a1a: f107 032c add.w r3, r7, #44 @ 0x2c 8001a1e: 4619 mov r1, r3 8001a20: 4836 ldr r0, [pc, #216] @ (8001afc ) 8001a22: f000 ff93 bl 800294c hdma_uart5_rx.Instance = DMA1_Stream0; 8001a26: 4b36 ldr r3, [pc, #216] @ (8001b00 ) 8001a28: 4a36 ldr r2, [pc, #216] @ (8001b04 ) 8001a2a: 601a str r2, [r3, #0] hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4; 8001a2c: 4b34 ldr r3, [pc, #208] @ (8001b00 ) 8001a2e: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001a32: 605a str r2, [r3, #4] hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001a34: 4b32 ldr r3, [pc, #200] @ (8001b00 ) 8001a36: 2200 movs r2, #0 8001a38: 609a str r2, [r3, #8] hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001a3a: 4b31 ldr r3, [pc, #196] @ (8001b00 ) 8001a3c: 2200 movs r2, #0 8001a3e: 60da str r2, [r3, #12] hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE; 8001a40: 4b2f ldr r3, [pc, #188] @ (8001b00 ) 8001a42: f44f 6280 mov.w r2, #1024 @ 0x400 8001a46: 611a str r2, [r3, #16] hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001a48: 4b2d ldr r3, [pc, #180] @ (8001b00 ) 8001a4a: 2200 movs r2, #0 8001a4c: 615a str r2, [r3, #20] hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001a4e: 4b2c ldr r3, [pc, #176] @ (8001b00 ) 8001a50: 2200 movs r2, #0 8001a52: 619a str r2, [r3, #24] hdma_uart5_rx.Init.Mode = DMA_NORMAL; 8001a54: 4b2a ldr r3, [pc, #168] @ (8001b00 ) 8001a56: 2200 movs r2, #0 8001a58: 61da str r2, [r3, #28] hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; 8001a5a: 4b29 ldr r3, [pc, #164] @ (8001b00 ) 8001a5c: 2200 movs r2, #0 8001a5e: 621a str r2, [r3, #32] hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001a60: 4b27 ldr r3, [pc, #156] @ (8001b00 ) 8001a62: 2200 movs r2, #0 8001a64: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) 8001a66: 4826 ldr r0, [pc, #152] @ (8001b00 ) 8001a68: f000 fb6e bl 8002148 8001a6c: 4603 mov r3, r0 8001a6e: 2b00 cmp r3, #0 8001a70: d001 beq.n 8001a76 Error_Handler(); 8001a72: f7ff fc0f bl 8001294 __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx); 8001a76: 687b ldr r3, [r7, #4] 8001a78: 4a21 ldr r2, [pc, #132] @ (8001b00 ) 8001a7a: 63da str r2, [r3, #60] @ 0x3c 8001a7c: 4a20 ldr r2, [pc, #128] @ (8001b00 ) 8001a7e: 687b ldr r3, [r7, #4] 8001a80: 6393 str r3, [r2, #56] @ 0x38 hdma_uart5_tx.Instance = DMA1_Stream7; 8001a82: 4b21 ldr r3, [pc, #132] @ (8001b08 ) 8001a84: 4a21 ldr r2, [pc, #132] @ (8001b0c ) 8001a86: 601a str r2, [r3, #0] hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4; 8001a88: 4b1f ldr r3, [pc, #124] @ (8001b08 ) 8001a8a: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001a8e: 605a str r2, [r3, #4] hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001a90: 4b1d ldr r3, [pc, #116] @ (8001b08 ) 8001a92: 2240 movs r2, #64 @ 0x40 8001a94: 609a str r2, [r3, #8] hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001a96: 4b1c ldr r3, [pc, #112] @ (8001b08 ) 8001a98: 2200 movs r2, #0 8001a9a: 60da str r2, [r3, #12] hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE; 8001a9c: 4b1a ldr r3, [pc, #104] @ (8001b08 ) 8001a9e: f44f 6280 mov.w r2, #1024 @ 0x400 8001aa2: 611a str r2, [r3, #16] hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001aa4: 4b18 ldr r3, [pc, #96] @ (8001b08 ) 8001aa6: 2200 movs r2, #0 8001aa8: 615a str r2, [r3, #20] hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001aaa: 4b17 ldr r3, [pc, #92] @ (8001b08 ) 8001aac: 2200 movs r2, #0 8001aae: 619a str r2, [r3, #24] hdma_uart5_tx.Init.Mode = DMA_NORMAL; 8001ab0: 4b15 ldr r3, [pc, #84] @ (8001b08 ) 8001ab2: 2200 movs r2, #0 8001ab4: 61da str r2, [r3, #28] hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; 8001ab6: 4b14 ldr r3, [pc, #80] @ (8001b08 ) 8001ab8: 2200 movs r2, #0 8001aba: 621a str r2, [r3, #32] hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001abc: 4b12 ldr r3, [pc, #72] @ (8001b08 ) 8001abe: 2200 movs r2, #0 8001ac0: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) 8001ac2: 4811 ldr r0, [pc, #68] @ (8001b08 ) 8001ac4: f000 fb40 bl 8002148 8001ac8: 4603 mov r3, r0 8001aca: 2b00 cmp r3, #0 8001acc: d001 beq.n 8001ad2 Error_Handler(); 8001ace: f7ff fbe1 bl 8001294 __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); 8001ad2: 687b ldr r3, [r7, #4] 8001ad4: 4a0c ldr r2, [pc, #48] @ (8001b08 ) 8001ad6: 639a str r2, [r3, #56] @ 0x38 8001ad8: 4a0b ldr r2, [pc, #44] @ (8001b08 ) 8001ada: 687b ldr r3, [r7, #4] 8001adc: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); 8001ade: 2200 movs r2, #0 8001ae0: 2105 movs r1, #5 8001ae2: 2035 movs r0, #53 @ 0x35 8001ae4: f000 faf9 bl 80020da HAL_NVIC_EnableIRQ(UART5_IRQn); 8001ae8: 2035 movs r0, #53 @ 0x35 8001aea: f000 fb12 bl 8002112 } 8001aee: e13d b.n 8001d6c 8001af0: 40005000 .word 0x40005000 8001af4: 40023800 .word 0x40023800 8001af8: 40020800 .word 0x40020800 8001afc: 40020c00 .word 0x40020c00 8001b00: 20000cc0 .word 0x20000cc0 8001b04: 40026010 .word 0x40026010 8001b08: 20000d20 .word 0x20000d20 8001b0c: 400260b8 .word 0x400260b8 else if(uartHandle->Instance==USART1) 8001b10: 687b ldr r3, [r7, #4] 8001b12: 681b ldr r3, [r3, #0] 8001b14: 4a97 ldr r2, [pc, #604] @ (8001d74 ) 8001b16: 4293 cmp r3, r2 8001b18: f040 8092 bne.w 8001c40 __HAL_RCC_USART1_CLK_ENABLE(); 8001b1c: 2300 movs r3, #0 8001b1e: 617b str r3, [r7, #20] 8001b20: 4b95 ldr r3, [pc, #596] @ (8001d78 ) 8001b22: 6c5b ldr r3, [r3, #68] @ 0x44 8001b24: 4a94 ldr r2, [pc, #592] @ (8001d78 ) 8001b26: f043 0310 orr.w r3, r3, #16 8001b2a: 6453 str r3, [r2, #68] @ 0x44 8001b2c: 4b92 ldr r3, [pc, #584] @ (8001d78 ) 8001b2e: 6c5b ldr r3, [r3, #68] @ 0x44 8001b30: f003 0310 and.w r3, r3, #16 8001b34: 617b str r3, [r7, #20] 8001b36: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001b38: 2300 movs r3, #0 8001b3a: 613b str r3, [r7, #16] 8001b3c: 4b8e ldr r3, [pc, #568] @ (8001d78 ) 8001b3e: 6b1b ldr r3, [r3, #48] @ 0x30 8001b40: 4a8d ldr r2, [pc, #564] @ (8001d78 ) 8001b42: f043 0301 orr.w r3, r3, #1 8001b46: 6313 str r3, [r2, #48] @ 0x30 8001b48: 4b8b ldr r3, [pc, #556] @ (8001d78 ) 8001b4a: 6b1b ldr r3, [r3, #48] @ 0x30 8001b4c: f003 0301 and.w r3, r3, #1 8001b50: 613b str r3, [r7, #16] 8001b52: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 8001b54: f44f 63c0 mov.w r3, #1536 @ 0x600 8001b58: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001b5a: 2302 movs r3, #2 8001b5c: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001b5e: 2300 movs r3, #0 8001b60: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001b62: 2303 movs r3, #3 8001b64: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 8001b66: 2307 movs r3, #7 8001b68: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001b6a: f107 032c add.w r3, r7, #44 @ 0x2c 8001b6e: 4619 mov r1, r3 8001b70: 4882 ldr r0, [pc, #520] @ (8001d7c ) 8001b72: f000 feeb bl 800294c hdma_usart1_rx.Instance = DMA2_Stream2; 8001b76: 4b82 ldr r3, [pc, #520] @ (8001d80 ) 8001b78: 4a82 ldr r2, [pc, #520] @ (8001d84 ) 8001b7a: 601a str r2, [r3, #0] hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; 8001b7c: 4b80 ldr r3, [pc, #512] @ (8001d80 ) 8001b7e: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001b82: 605a str r2, [r3, #4] hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001b84: 4b7e ldr r3, [pc, #504] @ (8001d80 ) 8001b86: 2200 movs r2, #0 8001b88: 609a str r2, [r3, #8] hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001b8a: 4b7d ldr r3, [pc, #500] @ (8001d80 ) 8001b8c: 2200 movs r2, #0 8001b8e: 60da str r2, [r3, #12] hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 8001b90: 4b7b ldr r3, [pc, #492] @ (8001d80 ) 8001b92: f44f 6280 mov.w r2, #1024 @ 0x400 8001b96: 611a str r2, [r3, #16] hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001b98: 4b79 ldr r3, [pc, #484] @ (8001d80 ) 8001b9a: 2200 movs r2, #0 8001b9c: 615a str r2, [r3, #20] hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001b9e: 4b78 ldr r3, [pc, #480] @ (8001d80 ) 8001ba0: 2200 movs r2, #0 8001ba2: 619a str r2, [r3, #24] hdma_usart1_rx.Init.Mode = DMA_NORMAL; 8001ba4: 4b76 ldr r3, [pc, #472] @ (8001d80 ) 8001ba6: 2200 movs r2, #0 8001ba8: 61da str r2, [r3, #28] hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; 8001baa: 4b75 ldr r3, [pc, #468] @ (8001d80 ) 8001bac: 2200 movs r2, #0 8001bae: 621a str r2, [r3, #32] hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001bb0: 4b73 ldr r3, [pc, #460] @ (8001d80 ) 8001bb2: 2200 movs r2, #0 8001bb4: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 8001bb6: 4872 ldr r0, [pc, #456] @ (8001d80 ) 8001bb8: f000 fac6 bl 8002148 8001bbc: 4603 mov r3, r0 8001bbe: 2b00 cmp r3, #0 8001bc0: d001 beq.n 8001bc6 Error_Handler(); 8001bc2: f7ff fb67 bl 8001294 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); 8001bc6: 687b ldr r3, [r7, #4] 8001bc8: 4a6d ldr r2, [pc, #436] @ (8001d80 ) 8001bca: 63da str r2, [r3, #60] @ 0x3c 8001bcc: 4a6c ldr r2, [pc, #432] @ (8001d80 ) 8001bce: 687b ldr r3, [r7, #4] 8001bd0: 6393 str r3, [r2, #56] @ 0x38 hdma_usart1_tx.Instance = DMA2_Stream7; 8001bd2: 4b6d ldr r3, [pc, #436] @ (8001d88 ) 8001bd4: 4a6d ldr r2, [pc, #436] @ (8001d8c ) 8001bd6: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; 8001bd8: 4b6b ldr r3, [pc, #428] @ (8001d88 ) 8001bda: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001bde: 605a str r2, [r3, #4] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001be0: 4b69 ldr r3, [pc, #420] @ (8001d88 ) 8001be2: 2240 movs r2, #64 @ 0x40 8001be4: 609a str r2, [r3, #8] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001be6: 4b68 ldr r3, [pc, #416] @ (8001d88 ) 8001be8: 2200 movs r2, #0 8001bea: 60da str r2, [r3, #12] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 8001bec: 4b66 ldr r3, [pc, #408] @ (8001d88 ) 8001bee: f44f 6280 mov.w r2, #1024 @ 0x400 8001bf2: 611a str r2, [r3, #16] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001bf4: 4b64 ldr r3, [pc, #400] @ (8001d88 ) 8001bf6: 2200 movs r2, #0 8001bf8: 615a str r2, [r3, #20] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001bfa: 4b63 ldr r3, [pc, #396] @ (8001d88 ) 8001bfc: 2200 movs r2, #0 8001bfe: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 8001c00: 4b61 ldr r3, [pc, #388] @ (8001d88 ) 8001c02: 2200 movs r2, #0 8001c04: 61da str r2, [r3, #28] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 8001c06: 4b60 ldr r3, [pc, #384] @ (8001d88 ) 8001c08: 2200 movs r2, #0 8001c0a: 621a str r2, [r3, #32] hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001c0c: 4b5e ldr r3, [pc, #376] @ (8001d88 ) 8001c0e: 2200 movs r2, #0 8001c10: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 8001c12: 485d ldr r0, [pc, #372] @ (8001d88 ) 8001c14: f000 fa98 bl 8002148 8001c18: 4603 mov r3, r0 8001c1a: 2b00 cmp r3, #0 8001c1c: d001 beq.n 8001c22 Error_Handler(); 8001c1e: f7ff fb39 bl 8001294 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); 8001c22: 687b ldr r3, [r7, #4] 8001c24: 4a58 ldr r2, [pc, #352] @ (8001d88 ) 8001c26: 639a str r2, [r3, #56] @ 0x38 8001c28: 4a57 ldr r2, [pc, #348] @ (8001d88 ) 8001c2a: 687b ldr r3, [r7, #4] 8001c2c: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 8001c2e: 2200 movs r2, #0 8001c30: 2105 movs r1, #5 8001c32: 2025 movs r0, #37 @ 0x25 8001c34: f000 fa51 bl 80020da HAL_NVIC_EnableIRQ(USART1_IRQn); 8001c38: 2025 movs r0, #37 @ 0x25 8001c3a: f000 fa6a bl 8002112 } 8001c3e: e095 b.n 8001d6c else if(uartHandle->Instance==USART2) 8001c40: 687b ldr r3, [r7, #4] 8001c42: 681b ldr r3, [r3, #0] 8001c44: 4a52 ldr r2, [pc, #328] @ (8001d90 ) 8001c46: 4293 cmp r3, r2 8001c48: f040 8090 bne.w 8001d6c __HAL_RCC_USART2_CLK_ENABLE(); 8001c4c: 2300 movs r3, #0 8001c4e: 60fb str r3, [r7, #12] 8001c50: 4b49 ldr r3, [pc, #292] @ (8001d78 ) 8001c52: 6c1b ldr r3, [r3, #64] @ 0x40 8001c54: 4a48 ldr r2, [pc, #288] @ (8001d78 ) 8001c56: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001c5a: 6413 str r3, [r2, #64] @ 0x40 8001c5c: 4b46 ldr r3, [pc, #280] @ (8001d78 ) 8001c5e: 6c1b ldr r3, [r3, #64] @ 0x40 8001c60: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001c64: 60fb str r3, [r7, #12] 8001c66: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001c68: 2300 movs r3, #0 8001c6a: 60bb str r3, [r7, #8] 8001c6c: 4b42 ldr r3, [pc, #264] @ (8001d78 ) 8001c6e: 6b1b ldr r3, [r3, #48] @ 0x30 8001c70: 4a41 ldr r2, [pc, #260] @ (8001d78 ) 8001c72: f043 0301 orr.w r3, r3, #1 8001c76: 6313 str r3, [r2, #48] @ 0x30 8001c78: 4b3f ldr r3, [pc, #252] @ (8001d78 ) 8001c7a: 6b1b ldr r3, [r3, #48] @ 0x30 8001c7c: f003 0301 and.w r3, r3, #1 8001c80: 60bb str r3, [r7, #8] 8001c82: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; 8001c84: 230c movs r3, #12 8001c86: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001c88: 2302 movs r3, #2 8001c8a: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001c8c: 2300 movs r3, #0 8001c8e: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001c90: 2303 movs r3, #3 8001c92: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 8001c94: 2307 movs r3, #7 8001c96: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001c98: f107 032c add.w r3, r7, #44 @ 0x2c 8001c9c: 4619 mov r1, r3 8001c9e: 4837 ldr r0, [pc, #220] @ (8001d7c ) 8001ca0: f000 fe54 bl 800294c hdma_usart2_rx.Instance = DMA1_Stream5; 8001ca4: 4b3b ldr r3, [pc, #236] @ (8001d94 ) 8001ca6: 4a3c ldr r2, [pc, #240] @ (8001d98 ) 8001ca8: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; 8001caa: 4b3a ldr r3, [pc, #232] @ (8001d94 ) 8001cac: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001cb0: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001cb2: 4b38 ldr r3, [pc, #224] @ (8001d94 ) 8001cb4: 2200 movs r2, #0 8001cb6: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001cb8: 4b36 ldr r3, [pc, #216] @ (8001d94 ) 8001cba: 2200 movs r2, #0 8001cbc: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 8001cbe: 4b35 ldr r3, [pc, #212] @ (8001d94 ) 8001cc0: f44f 6280 mov.w r2, #1024 @ 0x400 8001cc4: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001cc6: 4b33 ldr r3, [pc, #204] @ (8001d94 ) 8001cc8: 2200 movs r2, #0 8001cca: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001ccc: 4b31 ldr r3, [pc, #196] @ (8001d94 ) 8001cce: 2200 movs r2, #0 8001cd0: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 8001cd2: 4b30 ldr r3, [pc, #192] @ (8001d94 ) 8001cd4: 2200 movs r2, #0 8001cd6: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; 8001cd8: 4b2e ldr r3, [pc, #184] @ (8001d94 ) 8001cda: 2200 movs r2, #0 8001cdc: 621a str r2, [r3, #32] hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001cde: 4b2d ldr r3, [pc, #180] @ (8001d94 ) 8001ce0: 2200 movs r2, #0 8001ce2: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 8001ce4: 482b ldr r0, [pc, #172] @ (8001d94 ) 8001ce6: f000 fa2f bl 8002148 8001cea: 4603 mov r3, r0 8001cec: 2b00 cmp r3, #0 8001cee: d001 beq.n 8001cf4 Error_Handler(); 8001cf0: f7ff fad0 bl 8001294 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 8001cf4: 687b ldr r3, [r7, #4] 8001cf6: 4a27 ldr r2, [pc, #156] @ (8001d94 ) 8001cf8: 63da str r2, [r3, #60] @ 0x3c 8001cfa: 4a26 ldr r2, [pc, #152] @ (8001d94 ) 8001cfc: 687b ldr r3, [r7, #4] 8001cfe: 6393 str r3, [r2, #56] @ 0x38 hdma_usart2_tx.Instance = DMA1_Stream6; 8001d00: 4b26 ldr r3, [pc, #152] @ (8001d9c ) 8001d02: 4a27 ldr r2, [pc, #156] @ (8001da0 ) 8001d04: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; 8001d06: 4b25 ldr r3, [pc, #148] @ (8001d9c ) 8001d08: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001d0c: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001d0e: 4b23 ldr r3, [pc, #140] @ (8001d9c ) 8001d10: 2240 movs r2, #64 @ 0x40 8001d12: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001d14: 4b21 ldr r3, [pc, #132] @ (8001d9c ) 8001d16: 2200 movs r2, #0 8001d18: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 8001d1a: 4b20 ldr r3, [pc, #128] @ (8001d9c ) 8001d1c: f44f 6280 mov.w r2, #1024 @ 0x400 8001d20: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001d22: 4b1e ldr r3, [pc, #120] @ (8001d9c ) 8001d24: 2200 movs r2, #0 8001d26: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001d28: 4b1c ldr r3, [pc, #112] @ (8001d9c ) 8001d2a: 2200 movs r2, #0 8001d2c: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 8001d2e: 4b1b ldr r3, [pc, #108] @ (8001d9c ) 8001d30: 2200 movs r2, #0 8001d32: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; 8001d34: 4b19 ldr r3, [pc, #100] @ (8001d9c ) 8001d36: 2200 movs r2, #0 8001d38: 621a str r2, [r3, #32] hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001d3a: 4b18 ldr r3, [pc, #96] @ (8001d9c ) 8001d3c: 2200 movs r2, #0 8001d3e: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 8001d40: 4816 ldr r0, [pc, #88] @ (8001d9c ) 8001d42: f000 fa01 bl 8002148 8001d46: 4603 mov r3, r0 8001d48: 2b00 cmp r3, #0 8001d4a: d001 beq.n 8001d50 Error_Handler(); 8001d4c: f7ff faa2 bl 8001294 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 8001d50: 687b ldr r3, [r7, #4] 8001d52: 4a12 ldr r2, [pc, #72] @ (8001d9c ) 8001d54: 639a str r2, [r3, #56] @ 0x38 8001d56: 4a11 ldr r2, [pc, #68] @ (8001d9c ) 8001d58: 687b ldr r3, [r7, #4] 8001d5a: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART2_IRQn, 5, 0); 8001d5c: 2200 movs r2, #0 8001d5e: 2105 movs r1, #5 8001d60: 2026 movs r0, #38 @ 0x26 8001d62: f000 f9ba bl 80020da HAL_NVIC_EnableIRQ(USART2_IRQn); 8001d66: 2026 movs r0, #38 @ 0x26 8001d68: f000 f9d3 bl 8002112 } 8001d6c: bf00 nop 8001d6e: 3740 adds r7, #64 @ 0x40 8001d70: 46bd mov sp, r7 8001d72: bd80 pop {r7, pc} 8001d74: 40011000 .word 0x40011000 8001d78: 40023800 .word 0x40023800 8001d7c: 40020000 .word 0x40020000 8001d80: 20000d80 .word 0x20000d80 8001d84: 40026440 .word 0x40026440 8001d88: 20000de0 .word 0x20000de0 8001d8c: 400264b8 .word 0x400264b8 8001d90: 40004400 .word 0x40004400 8001d94: 20000e40 .word 0x20000e40 8001d98: 40026088 .word 0x40026088 8001d9c: 20000ea0 .word 0x20000ea0 8001da0: 400260a0 .word 0x400260a0 08001da4 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001da4: f8df d034 ldr.w sp, [pc, #52] @ 8001ddc /* Call the clock system initialization function.*/ bl SystemInit 8001da8: f7ff fb54 bl 8001454 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001dac: 480c ldr r0, [pc, #48] @ (8001de0 ) ldr r1, =_edata 8001dae: 490d ldr r1, [pc, #52] @ (8001de4 ) ldr r2, =_sidata 8001db0: 4a0d ldr r2, [pc, #52] @ (8001de8 ) movs r3, #0 8001db2: 2300 movs r3, #0 b LoopCopyDataInit 8001db4: e002 b.n 8001dbc 08001db6 : CopyDataInit: ldr r4, [r2, r3] 8001db6: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001db8: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001dba: 3304 adds r3, #4 08001dbc : LoopCopyDataInit: adds r4, r0, r3 8001dbc: 18c4 adds r4, r0, r3 cmp r4, r1 8001dbe: 428c cmp r4, r1 bcc CopyDataInit 8001dc0: d3f9 bcc.n 8001db6 /* Zero fill the bss segment. */ ldr r2, =_sbss 8001dc2: 4a0a ldr r2, [pc, #40] @ (8001dec ) ldr r4, =_ebss 8001dc4: 4c0a ldr r4, [pc, #40] @ (8001df0 ) movs r3, #0 8001dc6: 2300 movs r3, #0 b LoopFillZerobss 8001dc8: e001 b.n 8001dce 08001dca : FillZerobss: str r3, [r2] 8001dca: 6013 str r3, [r2, #0] adds r2, r2, #4 8001dcc: 3204 adds r2, #4 08001dce : LoopFillZerobss: cmp r2, r4 8001dce: 42a2 cmp r2, r4 bcc FillZerobss 8001dd0: d3fb bcc.n 8001dca /* Call static constructors */ bl __libc_init_array 8001dd2: f009 fca1 bl 800b718 <__libc_init_array> /* Call the application's entry point.*/ bl main 8001dd6: f7fe fda7 bl 8000928
bx lr 8001dda: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001ddc: 20020000 .word 0x20020000 ldr r0, =_sdata 8001de0: 20000000 .word 0x20000000 ldr r1, =_edata 8001de4: 200001a0 .word 0x200001a0 ldr r2, =_sidata 8001de8: 0800b800 .word 0x0800b800 ldr r2, =_sbss 8001dec: 200001a0 .word 0x200001a0 ldr r4, =_ebss 8001df0: 200018dc .word 0x200018dc 08001df4 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001df4: e7fe b.n 8001df4 ... 08001df8 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001df8: b580 push {r7, lr} 8001dfa: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 8001dfc: 4b0e ldr r3, [pc, #56] @ (8001e38 ) 8001dfe: 681b ldr r3, [r3, #0] 8001e00: 4a0d ldr r2, [pc, #52] @ (8001e38 ) 8001e02: f443 7300 orr.w r3, r3, #512 @ 0x200 8001e06: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 8001e08: 4b0b ldr r3, [pc, #44] @ (8001e38 ) 8001e0a: 681b ldr r3, [r3, #0] 8001e0c: 4a0a ldr r2, [pc, #40] @ (8001e38 ) 8001e0e: f443 6380 orr.w r3, r3, #1024 @ 0x400 8001e12: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001e14: 4b08 ldr r3, [pc, #32] @ (8001e38 ) 8001e16: 681b ldr r3, [r3, #0] 8001e18: 4a07 ldr r2, [pc, #28] @ (8001e38 ) 8001e1a: f443 7380 orr.w r3, r3, #256 @ 0x100 8001e1e: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001e20: 2003 movs r0, #3 8001e22: f000 f94f bl 80020c4 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8001e26: 200f movs r0, #15 8001e28: f000 f808 bl 8001e3c /* Init the low level hardware */ HAL_MspInit(); 8001e2c: f7ff fa38 bl 80012a0 /* Return function status */ return HAL_OK; 8001e30: 2300 movs r3, #0 } 8001e32: 4618 mov r0, r3 8001e34: bd80 pop {r7, pc} 8001e36: bf00 nop 8001e38: 40023c00 .word 0x40023c00 08001e3c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001e3c: b580 push {r7, lr} 8001e3e: b082 sub sp, #8 8001e40: af00 add r7, sp, #0 8001e42: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8001e44: 4b12 ldr r3, [pc, #72] @ (8001e90 ) 8001e46: 681a ldr r2, [r3, #0] 8001e48: 4b12 ldr r3, [pc, #72] @ (8001e94 ) 8001e4a: 781b ldrb r3, [r3, #0] 8001e4c: 4619 mov r1, r3 8001e4e: f44f 737a mov.w r3, #1000 @ 0x3e8 8001e52: fbb3 f3f1 udiv r3, r3, r1 8001e56: fbb2 f3f3 udiv r3, r2, r3 8001e5a: 4618 mov r0, r3 8001e5c: f000 f967 bl 800212e 8001e60: 4603 mov r3, r0 8001e62: 2b00 cmp r3, #0 8001e64: d001 beq.n 8001e6a { return HAL_ERROR; 8001e66: 2301 movs r3, #1 8001e68: e00e b.n 8001e88 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001e6a: 687b ldr r3, [r7, #4] 8001e6c: 2b0f cmp r3, #15 8001e6e: d80a bhi.n 8001e86 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001e70: 2200 movs r2, #0 8001e72: 6879 ldr r1, [r7, #4] 8001e74: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8001e78: f000 f92f bl 80020da uwTickPrio = TickPriority; 8001e7c: 4a06 ldr r2, [pc, #24] @ (8001e98 ) 8001e7e: 687b ldr r3, [r7, #4] 8001e80: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8001e82: 2300 movs r3, #0 8001e84: e000 b.n 8001e88 return HAL_ERROR; 8001e86: 2301 movs r3, #1 } 8001e88: 4618 mov r0, r3 8001e8a: 3708 adds r7, #8 8001e8c: 46bd mov sp, r7 8001e8e: bd80 pop {r7, pc} 8001e90: 20000090 .word 0x20000090 8001e94: 20000098 .word 0x20000098 8001e98: 20000094 .word 0x20000094 08001e9c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001e9c: b480 push {r7} 8001e9e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001ea0: 4b06 ldr r3, [pc, #24] @ (8001ebc ) 8001ea2: 781b ldrb r3, [r3, #0] 8001ea4: 461a mov r2, r3 8001ea6: 4b06 ldr r3, [pc, #24] @ (8001ec0 ) 8001ea8: 681b ldr r3, [r3, #0] 8001eaa: 4413 add r3, r2 8001eac: 4a04 ldr r2, [pc, #16] @ (8001ec0 ) 8001eae: 6013 str r3, [r2, #0] } 8001eb0: bf00 nop 8001eb2: 46bd mov sp, r7 8001eb4: f85d 7b04 ldr.w r7, [sp], #4 8001eb8: 4770 bx lr 8001eba: bf00 nop 8001ebc: 20000098 .word 0x20000098 8001ec0: 20000f00 .word 0x20000f00 08001ec4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001ec4: b480 push {r7} 8001ec6: af00 add r7, sp, #0 return uwTick; 8001ec8: 4b03 ldr r3, [pc, #12] @ (8001ed8 ) 8001eca: 681b ldr r3, [r3, #0] } 8001ecc: 4618 mov r0, r3 8001ece: 46bd mov sp, r7 8001ed0: f85d 7b04 ldr.w r7, [sp], #4 8001ed4: 4770 bx lr 8001ed6: bf00 nop 8001ed8: 20000f00 .word 0x20000f00 08001edc : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001edc: b580 push {r7, lr} 8001ede: b084 sub sp, #16 8001ee0: af00 add r7, sp, #0 8001ee2: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001ee4: f7ff ffee bl 8001ec4 8001ee8: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001eea: 687b ldr r3, [r7, #4] 8001eec: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001eee: 68fb ldr r3, [r7, #12] 8001ef0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8001ef4: d005 beq.n 8001f02 { wait += (uint32_t)(uwTickFreq); 8001ef6: 4b0a ldr r3, [pc, #40] @ (8001f20 ) 8001ef8: 781b ldrb r3, [r3, #0] 8001efa: 461a mov r2, r3 8001efc: 68fb ldr r3, [r7, #12] 8001efe: 4413 add r3, r2 8001f00: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8001f02: bf00 nop 8001f04: f7ff ffde bl 8001ec4 8001f08: 4602 mov r2, r0 8001f0a: 68bb ldr r3, [r7, #8] 8001f0c: 1ad3 subs r3, r2, r3 8001f0e: 68fa ldr r2, [r7, #12] 8001f10: 429a cmp r2, r3 8001f12: d8f7 bhi.n 8001f04 { } } 8001f14: bf00 nop 8001f16: bf00 nop 8001f18: 3710 adds r7, #16 8001f1a: 46bd mov sp, r7 8001f1c: bd80 pop {r7, pc} 8001f1e: bf00 nop 8001f20: 20000098 .word 0x20000098 08001f24 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001f24: b480 push {r7} 8001f26: b085 sub sp, #20 8001f28: af00 add r7, sp, #0 8001f2a: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001f2c: 687b ldr r3, [r7, #4] 8001f2e: f003 0307 and.w r3, r3, #7 8001f32: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001f34: 4b0c ldr r3, [pc, #48] @ (8001f68 <__NVIC_SetPriorityGrouping+0x44>) 8001f36: 68db ldr r3, [r3, #12] 8001f38: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001f3a: 68ba ldr r2, [r7, #8] 8001f3c: f64f 03ff movw r3, #63743 @ 0xf8ff 8001f40: 4013 ands r3, r2 8001f42: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001f44: 68fb ldr r3, [r7, #12] 8001f46: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001f48: 68bb ldr r3, [r7, #8] 8001f4a: 4313 orrs r3, r2 reg_value = (reg_value | 8001f4c: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8001f50: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001f54: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001f56: 4a04 ldr r2, [pc, #16] @ (8001f68 <__NVIC_SetPriorityGrouping+0x44>) 8001f58: 68bb ldr r3, [r7, #8] 8001f5a: 60d3 str r3, [r2, #12] } 8001f5c: bf00 nop 8001f5e: 3714 adds r7, #20 8001f60: 46bd mov sp, r7 8001f62: f85d 7b04 ldr.w r7, [sp], #4 8001f66: 4770 bx lr 8001f68: e000ed00 .word 0xe000ed00 08001f6c <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001f6c: b480 push {r7} 8001f6e: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001f70: 4b04 ldr r3, [pc, #16] @ (8001f84 <__NVIC_GetPriorityGrouping+0x18>) 8001f72: 68db ldr r3, [r3, #12] 8001f74: 0a1b lsrs r3, r3, #8 8001f76: f003 0307 and.w r3, r3, #7 } 8001f7a: 4618 mov r0, r3 8001f7c: 46bd mov sp, r7 8001f7e: f85d 7b04 ldr.w r7, [sp], #4 8001f82: 4770 bx lr 8001f84: e000ed00 .word 0xe000ed00 08001f88 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8001f88: b480 push {r7} 8001f8a: b083 sub sp, #12 8001f8c: af00 add r7, sp, #0 8001f8e: 4603 mov r3, r0 8001f90: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001f92: f997 3007 ldrsb.w r3, [r7, #7] 8001f96: 2b00 cmp r3, #0 8001f98: db0b blt.n 8001fb2 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001f9a: 79fb ldrb r3, [r7, #7] 8001f9c: f003 021f and.w r2, r3, #31 8001fa0: 4907 ldr r1, [pc, #28] @ (8001fc0 <__NVIC_EnableIRQ+0x38>) 8001fa2: f997 3007 ldrsb.w r3, [r7, #7] 8001fa6: 095b lsrs r3, r3, #5 8001fa8: 2001 movs r0, #1 8001faa: fa00 f202 lsl.w r2, r0, r2 8001fae: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8001fb2: bf00 nop 8001fb4: 370c adds r7, #12 8001fb6: 46bd mov sp, r7 8001fb8: f85d 7b04 ldr.w r7, [sp], #4 8001fbc: 4770 bx lr 8001fbe: bf00 nop 8001fc0: e000e100 .word 0xe000e100 08001fc4 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001fc4: b480 push {r7} 8001fc6: b083 sub sp, #12 8001fc8: af00 add r7, sp, #0 8001fca: 4603 mov r3, r0 8001fcc: 6039 str r1, [r7, #0] 8001fce: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001fd0: f997 3007 ldrsb.w r3, [r7, #7] 8001fd4: 2b00 cmp r3, #0 8001fd6: db0a blt.n 8001fee <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001fd8: 683b ldr r3, [r7, #0] 8001fda: b2da uxtb r2, r3 8001fdc: 490c ldr r1, [pc, #48] @ (8002010 <__NVIC_SetPriority+0x4c>) 8001fde: f997 3007 ldrsb.w r3, [r7, #7] 8001fe2: 0112 lsls r2, r2, #4 8001fe4: b2d2 uxtb r2, r2 8001fe6: 440b add r3, r1 8001fe8: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001fec: e00a b.n 8002004 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001fee: 683b ldr r3, [r7, #0] 8001ff0: b2da uxtb r2, r3 8001ff2: 4908 ldr r1, [pc, #32] @ (8002014 <__NVIC_SetPriority+0x50>) 8001ff4: 79fb ldrb r3, [r7, #7] 8001ff6: f003 030f and.w r3, r3, #15 8001ffa: 3b04 subs r3, #4 8001ffc: 0112 lsls r2, r2, #4 8001ffe: b2d2 uxtb r2, r2 8002000: 440b add r3, r1 8002002: 761a strb r2, [r3, #24] } 8002004: bf00 nop 8002006: 370c adds r7, #12 8002008: 46bd mov sp, r7 800200a: f85d 7b04 ldr.w r7, [sp], #4 800200e: 4770 bx lr 8002010: e000e100 .word 0xe000e100 8002014: e000ed00 .word 0xe000ed00 08002018 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8002018: b480 push {r7} 800201a: b089 sub sp, #36 @ 0x24 800201c: af00 add r7, sp, #0 800201e: 60f8 str r0, [r7, #12] 8002020: 60b9 str r1, [r7, #8] 8002022: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002024: 68fb ldr r3, [r7, #12] 8002026: f003 0307 and.w r3, r3, #7 800202a: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800202c: 69fb ldr r3, [r7, #28] 800202e: f1c3 0307 rsb r3, r3, #7 8002032: 2b04 cmp r3, #4 8002034: bf28 it cs 8002036: 2304 movcs r3, #4 8002038: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800203a: 69fb ldr r3, [r7, #28] 800203c: 3304 adds r3, #4 800203e: 2b06 cmp r3, #6 8002040: d902 bls.n 8002048 8002042: 69fb ldr r3, [r7, #28] 8002044: 3b03 subs r3, #3 8002046: e000 b.n 800204a 8002048: 2300 movs r3, #0 800204a: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800204c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8002050: 69bb ldr r3, [r7, #24] 8002052: fa02 f303 lsl.w r3, r2, r3 8002056: 43da mvns r2, r3 8002058: 68bb ldr r3, [r7, #8] 800205a: 401a ands r2, r3 800205c: 697b ldr r3, [r7, #20] 800205e: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8002060: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002064: 697b ldr r3, [r7, #20] 8002066: fa01 f303 lsl.w r3, r1, r3 800206a: 43d9 mvns r1, r3 800206c: 687b ldr r3, [r7, #4] 800206e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002070: 4313 orrs r3, r2 ); } 8002072: 4618 mov r0, r3 8002074: 3724 adds r7, #36 @ 0x24 8002076: 46bd mov sp, r7 8002078: f85d 7b04 ldr.w r7, [sp], #4 800207c: 4770 bx lr ... 08002080 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8002080: b580 push {r7, lr} 8002082: b082 sub sp, #8 8002084: af00 add r7, sp, #0 8002086: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8002088: 687b ldr r3, [r7, #4] 800208a: 3b01 subs r3, #1 800208c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8002090: d301 bcc.n 8002096 { return (1UL); /* Reload value impossible */ 8002092: 2301 movs r3, #1 8002094: e00f b.n 80020b6 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8002096: 4a0a ldr r2, [pc, #40] @ (80020c0 ) 8002098: 687b ldr r3, [r7, #4] 800209a: 3b01 subs r3, #1 800209c: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800209e: 210f movs r1, #15 80020a0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80020a4: f7ff ff8e bl 8001fc4 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80020a8: 4b05 ldr r3, [pc, #20] @ (80020c0 ) 80020aa: 2200 movs r2, #0 80020ac: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80020ae: 4b04 ldr r3, [pc, #16] @ (80020c0 ) 80020b0: 2207 movs r2, #7 80020b2: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80020b4: 2300 movs r3, #0 } 80020b6: 4618 mov r0, r3 80020b8: 3708 adds r7, #8 80020ba: 46bd mov sp, r7 80020bc: bd80 pop {r7, pc} 80020be: bf00 nop 80020c0: e000e010 .word 0xe000e010 080020c4 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80020c4: b580 push {r7, lr} 80020c6: b082 sub sp, #8 80020c8: af00 add r7, sp, #0 80020ca: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80020cc: 6878 ldr r0, [r7, #4] 80020ce: f7ff ff29 bl 8001f24 <__NVIC_SetPriorityGrouping> } 80020d2: bf00 nop 80020d4: 3708 adds r7, #8 80020d6: 46bd mov sp, r7 80020d8: bd80 pop {r7, pc} 080020da : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80020da: b580 push {r7, lr} 80020dc: b086 sub sp, #24 80020de: af00 add r7, sp, #0 80020e0: 4603 mov r3, r0 80020e2: 60b9 str r1, [r7, #8] 80020e4: 607a str r2, [r7, #4] 80020e6: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 80020e8: 2300 movs r3, #0 80020ea: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80020ec: f7ff ff3e bl 8001f6c <__NVIC_GetPriorityGrouping> 80020f0: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80020f2: 687a ldr r2, [r7, #4] 80020f4: 68b9 ldr r1, [r7, #8] 80020f6: 6978 ldr r0, [r7, #20] 80020f8: f7ff ff8e bl 8002018 80020fc: 4602 mov r2, r0 80020fe: f997 300f ldrsb.w r3, [r7, #15] 8002102: 4611 mov r1, r2 8002104: 4618 mov r0, r3 8002106: f7ff ff5d bl 8001fc4 <__NVIC_SetPriority> } 800210a: bf00 nop 800210c: 3718 adds r7, #24 800210e: 46bd mov sp, r7 8002110: bd80 pop {r7, pc} 08002112 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8002112: b580 push {r7, lr} 8002114: b082 sub sp, #8 8002116: af00 add r7, sp, #0 8002118: 4603 mov r3, r0 800211a: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800211c: f997 3007 ldrsb.w r3, [r7, #7] 8002120: 4618 mov r0, r3 8002122: f7ff ff31 bl 8001f88 <__NVIC_EnableIRQ> } 8002126: bf00 nop 8002128: 3708 adds r7, #8 800212a: 46bd mov sp, r7 800212c: bd80 pop {r7, pc} 0800212e : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800212e: b580 push {r7, lr} 8002130: b082 sub sp, #8 8002132: af00 add r7, sp, #0 8002134: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8002136: 6878 ldr r0, [r7, #4] 8002138: f7ff ffa2 bl 8002080 800213c: 4603 mov r3, r0 } 800213e: 4618 mov r0, r3 8002140: 3708 adds r7, #8 8002142: 46bd mov sp, r7 8002144: bd80 pop {r7, pc} ... 08002148 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8002148: b580 push {r7, lr} 800214a: b086 sub sp, #24 800214c: af00 add r7, sp, #0 800214e: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 8002150: 2300 movs r3, #0 8002152: 617b str r3, [r7, #20] uint32_t tickstart = HAL_GetTick(); 8002154: f7ff feb6 bl 8001ec4 8002158: 6138 str r0, [r7, #16] DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) 800215a: 687b ldr r3, [r7, #4] 800215c: 2b00 cmp r3, #0 800215e: d101 bne.n 8002164 { return HAL_ERROR; 8002160: 2301 movs r3, #1 8002162: e099 b.n 8002298 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002164: 687b ldr r3, [r7, #4] 8002166: 2202 movs r2, #2 8002168: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 800216c: 687b ldr r3, [r7, #4] 800216e: 2200 movs r2, #0 8002170: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8002174: 687b ldr r3, [r7, #4] 8002176: 681b ldr r3, [r3, #0] 8002178: 681a ldr r2, [r3, #0] 800217a: 687b ldr r3, [r7, #4] 800217c: 681b ldr r3, [r3, #0] 800217e: f022 0201 bic.w r2, r2, #1 8002182: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8002184: e00f b.n 80021a6 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8002186: f7ff fe9d bl 8001ec4 800218a: 4602 mov r2, r0 800218c: 693b ldr r3, [r7, #16] 800218e: 1ad3 subs r3, r2, r3 8002190: 2b05 cmp r3, #5 8002192: d908 bls.n 80021a6 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8002194: 687b ldr r3, [r7, #4] 8002196: 2220 movs r2, #32 8002198: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 800219a: 687b ldr r3, [r7, #4] 800219c: 2203 movs r2, #3 800219e: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_TIMEOUT; 80021a2: 2303 movs r3, #3 80021a4: e078 b.n 8002298 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 80021a6: 687b ldr r3, [r7, #4] 80021a8: 681b ldr r3, [r3, #0] 80021aa: 681b ldr r3, [r3, #0] 80021ac: f003 0301 and.w r3, r3, #1 80021b0: 2b00 cmp r3, #0 80021b2: d1e8 bne.n 8002186 } } /* Get the CR register value */ tmp = hdma->Instance->CR; 80021b4: 687b ldr r3, [r7, #4] 80021b6: 681b ldr r3, [r3, #0] 80021b8: 681b ldr r3, [r3, #0] 80021ba: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 80021bc: 697a ldr r2, [r7, #20] 80021be: 4b38 ldr r3, [pc, #224] @ (80022a0 ) 80021c0: 4013 ands r3, r2 80021c2: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ tmp |= hdma->Init.Channel | hdma->Init.Direction | 80021c4: 687b ldr r3, [r7, #4] 80021c6: 685a ldr r2, [r3, #4] 80021c8: 687b ldr r3, [r7, #4] 80021ca: 689b ldr r3, [r3, #8] 80021cc: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 80021ce: 687b ldr r3, [r7, #4] 80021d0: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Channel | hdma->Init.Direction | 80021d2: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 80021d4: 687b ldr r3, [r7, #4] 80021d6: 691b ldr r3, [r3, #16] 80021d8: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80021da: 687b ldr r3, [r7, #4] 80021dc: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 80021de: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80021e0: 687b ldr r3, [r7, #4] 80021e2: 699b ldr r3, [r3, #24] 80021e4: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80021e6: 687b ldr r3, [r7, #4] 80021e8: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80021ea: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80021ec: 687b ldr r3, [r7, #4] 80021ee: 6a1b ldr r3, [r3, #32] 80021f0: 4313 orrs r3, r2 tmp |= hdma->Init.Channel | hdma->Init.Direction | 80021f2: 697a ldr r2, [r7, #20] 80021f4: 4313 orrs r3, r2 80021f6: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 80021f8: 687b ldr r3, [r7, #4] 80021fa: 6a5b ldr r3, [r3, #36] @ 0x24 80021fc: 2b04 cmp r3, #4 80021fe: d107 bne.n 8002210 { /* Get memory burst and peripheral burst */ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8002200: 687b ldr r3, [r7, #4] 8002202: 6ada ldr r2, [r3, #44] @ 0x2c 8002204: 687b ldr r3, [r7, #4] 8002206: 6b1b ldr r3, [r3, #48] @ 0x30 8002208: 4313 orrs r3, r2 800220a: 697a ldr r2, [r7, #20] 800220c: 4313 orrs r3, r2 800220e: 617b str r3, [r7, #20] } /* Write to DMA Stream CR register */ hdma->Instance->CR = tmp; 8002210: 687b ldr r3, [r7, #4] 8002212: 681b ldr r3, [r3, #0] 8002214: 697a ldr r2, [r7, #20] 8002216: 601a str r2, [r3, #0] /* Get the FCR register value */ tmp = hdma->Instance->FCR; 8002218: 687b ldr r3, [r7, #4] 800221a: 681b ldr r3, [r3, #0] 800221c: 695b ldr r3, [r3, #20] 800221e: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8002220: 697b ldr r3, [r7, #20] 8002222: f023 0307 bic.w r3, r3, #7 8002226: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ tmp |= hdma->Init.FIFOMode; 8002228: 687b ldr r3, [r7, #4] 800222a: 6a5b ldr r3, [r3, #36] @ 0x24 800222c: 697a ldr r2, [r7, #20] 800222e: 4313 orrs r3, r2 8002230: 617b str r3, [r7, #20] /* The FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8002232: 687b ldr r3, [r7, #4] 8002234: 6a5b ldr r3, [r3, #36] @ 0x24 8002236: 2b04 cmp r3, #4 8002238: d117 bne.n 800226a { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; 800223a: 687b ldr r3, [r7, #4] 800223c: 6a9b ldr r3, [r3, #40] @ 0x28 800223e: 697a ldr r2, [r7, #20] 8002240: 4313 orrs r3, r2 8002242: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 bursts */ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8002244: 687b ldr r3, [r7, #4] 8002246: 6adb ldr r3, [r3, #44] @ 0x2c 8002248: 2b00 cmp r3, #0 800224a: d00e beq.n 800226a { if (DMA_CheckFifoParam(hdma) != HAL_OK) 800224c: 6878 ldr r0, [r7, #4] 800224e: f000 fb01 bl 8002854 8002252: 4603 mov r3, r0 8002254: 2b00 cmp r3, #0 8002256: d008 beq.n 800226a { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8002258: 687b ldr r3, [r7, #4] 800225a: 2240 movs r2, #64 @ 0x40 800225c: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800225e: 687b ldr r3, [r7, #4] 8002260: 2201 movs r2, #1 8002262: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8002266: 2301 movs r3, #1 8002268: e016 b.n 8002298 } } } /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; 800226a: 687b ldr r3, [r7, #4] 800226c: 681b ldr r3, [r3, #0] 800226e: 697a ldr r2, [r7, #20] 8002270: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8002272: 6878 ldr r0, [r7, #4] 8002274: f000 fab8 bl 80027e8 8002278: 4603 mov r3, r0 800227a: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs->IFCR = 0x3FU << hdma->StreamIndex; 800227c: 687b ldr r3, [r7, #4] 800227e: 6ddb ldr r3, [r3, #92] @ 0x5c 8002280: 223f movs r2, #63 @ 0x3f 8002282: 409a lsls r2, r3 8002284: 68fb ldr r3, [r7, #12] 8002286: 609a str r2, [r3, #8] /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8002288: 687b ldr r3, [r7, #4] 800228a: 2200 movs r2, #0 800228c: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800228e: 687b ldr r3, [r7, #4] 8002290: 2201 movs r2, #1 8002292: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8002296: 2300 movs r3, #0 } 8002298: 4618 mov r0, r3 800229a: 3718 adds r7, #24 800229c: 46bd mov sp, r7 800229e: bd80 pop {r7, pc} 80022a0: f010803f .word 0xf010803f 080022a4 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 80022a4: b580 push {r7, lr} 80022a6: b086 sub sp, #24 80022a8: af00 add r7, sp, #0 80022aa: 60f8 str r0, [r7, #12] 80022ac: 60b9 str r1, [r7, #8] 80022ae: 607a str r2, [r7, #4] 80022b0: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 80022b2: 2300 movs r3, #0 80022b4: 75fb strb r3, [r7, #23] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 80022b6: 68fb ldr r3, [r7, #12] 80022b8: 6d9b ldr r3, [r3, #88] @ 0x58 80022ba: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 80022bc: 68fb ldr r3, [r7, #12] 80022be: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 80022c2: 2b01 cmp r3, #1 80022c4: d101 bne.n 80022ca 80022c6: 2302 movs r3, #2 80022c8: e040 b.n 800234c 80022ca: 68fb ldr r3, [r7, #12] 80022cc: 2201 movs r2, #1 80022ce: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 80022d2: 68fb ldr r3, [r7, #12] 80022d4: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80022d8: b2db uxtb r3, r3 80022da: 2b01 cmp r3, #1 80022dc: d12f bne.n 800233e { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80022de: 68fb ldr r3, [r7, #12] 80022e0: 2202 movs r2, #2 80022e2: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 80022e6: 68fb ldr r3, [r7, #12] 80022e8: 2200 movs r2, #0 80022ea: 655a str r2, [r3, #84] @ 0x54 /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 80022ec: 683b ldr r3, [r7, #0] 80022ee: 687a ldr r2, [r7, #4] 80022f0: 68b9 ldr r1, [r7, #8] 80022f2: 68f8 ldr r0, [r7, #12] 80022f4: f000 fa4a bl 800278c /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 80022f8: 68fb ldr r3, [r7, #12] 80022fa: 6ddb ldr r3, [r3, #92] @ 0x5c 80022fc: 223f movs r2, #63 @ 0x3f 80022fe: 409a lsls r2, r3 8002300: 693b ldr r3, [r7, #16] 8002302: 609a str r2, [r3, #8] /* Enable Common interrupts*/ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; 8002304: 68fb ldr r3, [r7, #12] 8002306: 681b ldr r3, [r3, #0] 8002308: 681a ldr r2, [r3, #0] 800230a: 68fb ldr r3, [r7, #12] 800230c: 681b ldr r3, [r3, #0] 800230e: f042 0216 orr.w r2, r2, #22 8002312: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8002314: 68fb ldr r3, [r7, #12] 8002316: 6c1b ldr r3, [r3, #64] @ 0x40 8002318: 2b00 cmp r3, #0 800231a: d007 beq.n 800232c { hdma->Instance->CR |= DMA_IT_HT; 800231c: 68fb ldr r3, [r7, #12] 800231e: 681b ldr r3, [r3, #0] 8002320: 681a ldr r2, [r3, #0] 8002322: 68fb ldr r3, [r7, #12] 8002324: 681b ldr r3, [r3, #0] 8002326: f042 0208 orr.w r2, r2, #8 800232a: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 800232c: 68fb ldr r3, [r7, #12] 800232e: 681b ldr r3, [r3, #0] 8002330: 681a ldr r2, [r3, #0] 8002332: 68fb ldr r3, [r7, #12] 8002334: 681b ldr r3, [r3, #0] 8002336: f042 0201 orr.w r2, r2, #1 800233a: 601a str r2, [r3, #0] 800233c: e005 b.n 800234a } else { /* Process unlocked */ __HAL_UNLOCK(hdma); 800233e: 68fb ldr r3, [r7, #12] 8002340: 2200 movs r2, #0 8002342: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_BUSY; 8002346: 2302 movs r3, #2 8002348: 75fb strb r3, [r7, #23] } return status; 800234a: 7dfb ldrb r3, [r7, #23] } 800234c: 4618 mov r0, r3 800234e: 3718 adds r7, #24 8002350: 46bd mov sp, r7 8002352: bd80 pop {r7, pc} 08002354 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8002354: b580 push {r7, lr} 8002356: b084 sub sp, #16 8002358: af00 add r7, sp, #0 800235a: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800235c: 687b ldr r3, [r7, #4] 800235e: 6d9b ldr r3, [r3, #88] @ 0x58 8002360: 60fb str r3, [r7, #12] uint32_t tickstart = HAL_GetTick(); 8002362: f7ff fdaf bl 8001ec4 8002366: 60b8 str r0, [r7, #8] if(hdma->State != HAL_DMA_STATE_BUSY) 8002368: 687b ldr r3, [r7, #4] 800236a: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 800236e: b2db uxtb r3, r3 8002370: 2b02 cmp r3, #2 8002372: d008 beq.n 8002386 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002374: 687b ldr r3, [r7, #4] 8002376: 2280 movs r2, #128 @ 0x80 8002378: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800237a: 687b ldr r3, [r7, #4] 800237c: 2200 movs r2, #0 800237e: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8002382: 2301 movs r3, #1 8002384: e052 b.n 800242c } else { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8002386: 687b ldr r3, [r7, #4] 8002388: 681b ldr r3, [r3, #0] 800238a: 681a ldr r2, [r3, #0] 800238c: 687b ldr r3, [r7, #4] 800238e: 681b ldr r3, [r3, #0] 8002390: f022 0216 bic.w r2, r2, #22 8002394: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 8002396: 687b ldr r3, [r7, #4] 8002398: 681b ldr r3, [r3, #0] 800239a: 695a ldr r2, [r3, #20] 800239c: 687b ldr r3, [r7, #4] 800239e: 681b ldr r3, [r3, #0] 80023a0: f022 0280 bic.w r2, r2, #128 @ 0x80 80023a4: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 80023a6: 687b ldr r3, [r7, #4] 80023a8: 6c1b ldr r3, [r3, #64] @ 0x40 80023aa: 2b00 cmp r3, #0 80023ac: d103 bne.n 80023b6 80023ae: 687b ldr r3, [r7, #4] 80023b0: 6c9b ldr r3, [r3, #72] @ 0x48 80023b2: 2b00 cmp r3, #0 80023b4: d007 beq.n 80023c6 { hdma->Instance->CR &= ~(DMA_IT_HT); 80023b6: 687b ldr r3, [r7, #4] 80023b8: 681b ldr r3, [r3, #0] 80023ba: 681a ldr r2, [r3, #0] 80023bc: 687b ldr r3, [r7, #4] 80023be: 681b ldr r3, [r3, #0] 80023c0: f022 0208 bic.w r2, r2, #8 80023c4: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80023c6: 687b ldr r3, [r7, #4] 80023c8: 681b ldr r3, [r3, #0] 80023ca: 681a ldr r2, [r3, #0] 80023cc: 687b ldr r3, [r7, #4] 80023ce: 681b ldr r3, [r3, #0] 80023d0: f022 0201 bic.w r2, r2, #1 80023d4: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 80023d6: e013 b.n 8002400 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 80023d8: f7ff fd74 bl 8001ec4 80023dc: 4602 mov r2, r0 80023de: 68bb ldr r3, [r7, #8] 80023e0: 1ad3 subs r3, r2, r3 80023e2: 2b05 cmp r3, #5 80023e4: d90c bls.n 8002400 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 80023e6: 687b ldr r3, [r7, #4] 80023e8: 2220 movs r2, #32 80023ea: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 80023ec: 687b ldr r3, [r7, #4] 80023ee: 2203 movs r2, #3 80023f0: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80023f4: 687b ldr r3, [r7, #4] 80023f6: 2200 movs r2, #0 80023f8: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_TIMEOUT; 80023fc: 2303 movs r3, #3 80023fe: e015 b.n 800242c while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8002400: 687b ldr r3, [r7, #4] 8002402: 681b ldr r3, [r3, #0] 8002404: 681b ldr r3, [r3, #0] 8002406: f003 0301 and.w r3, r3, #1 800240a: 2b00 cmp r3, #0 800240c: d1e4 bne.n 80023d8 } } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 800240e: 687b ldr r3, [r7, #4] 8002410: 6ddb ldr r3, [r3, #92] @ 0x5c 8002412: 223f movs r2, #63 @ 0x3f 8002414: 409a lsls r2, r3 8002416: 68fb ldr r3, [r7, #12] 8002418: 609a str r2, [r3, #8] /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 800241a: 687b ldr r3, [r7, #4] 800241c: 2201 movs r2, #1 800241e: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002422: 687b ldr r3, [r7, #4] 8002424: 2200 movs r2, #0 8002426: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 800242a: 2300 movs r3, #0 } 800242c: 4618 mov r0, r3 800242e: 3710 adds r7, #16 8002430: 46bd mov sp, r7 8002432: bd80 pop {r7, pc} 08002434 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8002434: b480 push {r7} 8002436: b083 sub sp, #12 8002438: af00 add r7, sp, #0 800243a: 6078 str r0, [r7, #4] if(hdma->State != HAL_DMA_STATE_BUSY) 800243c: 687b ldr r3, [r7, #4] 800243e: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8002442: b2db uxtb r3, r3 8002444: 2b02 cmp r3, #2 8002446: d004 beq.n 8002452 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002448: 687b ldr r3, [r7, #4] 800244a: 2280 movs r2, #128 @ 0x80 800244c: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 800244e: 2301 movs r3, #1 8002450: e00c b.n 800246c } else { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 8002452: 687b ldr r3, [r7, #4] 8002454: 2205 movs r2, #5 8002456: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800245a: 687b ldr r3, [r7, #4] 800245c: 681b ldr r3, [r3, #0] 800245e: 681a ldr r2, [r3, #0] 8002460: 687b ldr r3, [r7, #4] 8002462: 681b ldr r3, [r3, #0] 8002464: f022 0201 bic.w r2, r2, #1 8002468: 601a str r2, [r3, #0] } return HAL_OK; 800246a: 2300 movs r3, #0 } 800246c: 4618 mov r0, r3 800246e: 370c adds r7, #12 8002470: 46bd mov sp, r7 8002472: f85d 7b04 ldr.w r7, [sp], #4 8002476: 4770 bx lr 08002478 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8002478: b580 push {r7, lr} 800247a: b086 sub sp, #24 800247c: af00 add r7, sp, #0 800247e: 6078 str r0, [r7, #4] uint32_t tmpisr; __IO uint32_t count = 0U; 8002480: 2300 movs r3, #0 8002482: 60bb str r3, [r7, #8] uint32_t timeout = SystemCoreClock / 9600U; 8002484: 4b8e ldr r3, [pc, #568] @ (80026c0 ) 8002486: 681b ldr r3, [r3, #0] 8002488: 4a8e ldr r2, [pc, #568] @ (80026c4 ) 800248a: fba2 2303 umull r2, r3, r2, r3 800248e: 0a9b lsrs r3, r3, #10 8002490: 617b str r3, [r7, #20] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8002492: 687b ldr r3, [r7, #4] 8002494: 6d9b ldr r3, [r3, #88] @ 0x58 8002496: 613b str r3, [r7, #16] tmpisr = regs->ISR; 8002498: 693b ldr r3, [r7, #16] 800249a: 681b ldr r3, [r3, #0] 800249c: 60fb str r3, [r7, #12] /* Transfer Error Interrupt management ***************************************/ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) 800249e: 687b ldr r3, [r7, #4] 80024a0: 6ddb ldr r3, [r3, #92] @ 0x5c 80024a2: 2208 movs r2, #8 80024a4: 409a lsls r2, r3 80024a6: 68fb ldr r3, [r7, #12] 80024a8: 4013 ands r3, r2 80024aa: 2b00 cmp r3, #0 80024ac: d01a beq.n 80024e4 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) 80024ae: 687b ldr r3, [r7, #4] 80024b0: 681b ldr r3, [r3, #0] 80024b2: 681b ldr r3, [r3, #0] 80024b4: f003 0304 and.w r3, r3, #4 80024b8: 2b00 cmp r3, #0 80024ba: d013 beq.n 80024e4 { /* Disable the transfer error interrupt */ hdma->Instance->CR &= ~(DMA_IT_TE); 80024bc: 687b ldr r3, [r7, #4] 80024be: 681b ldr r3, [r3, #0] 80024c0: 681a ldr r2, [r3, #0] 80024c2: 687b ldr r3, [r7, #4] 80024c4: 681b ldr r3, [r3, #0] 80024c6: f022 0204 bic.w r2, r2, #4 80024ca: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; 80024cc: 687b ldr r3, [r7, #4] 80024ce: 6ddb ldr r3, [r3, #92] @ 0x5c 80024d0: 2208 movs r2, #8 80024d2: 409a lsls r2, r3 80024d4: 693b ldr r3, [r7, #16] 80024d6: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 80024d8: 687b ldr r3, [r7, #4] 80024da: 6d5b ldr r3, [r3, #84] @ 0x54 80024dc: f043 0201 orr.w r2, r3, #1 80024e0: 687b ldr r3, [r7, #4] 80024e2: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) 80024e4: 687b ldr r3, [r7, #4] 80024e6: 6ddb ldr r3, [r3, #92] @ 0x5c 80024e8: 2201 movs r2, #1 80024ea: 409a lsls r2, r3 80024ec: 68fb ldr r3, [r7, #12] 80024ee: 4013 ands r3, r2 80024f0: 2b00 cmp r3, #0 80024f2: d012 beq.n 800251a { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) 80024f4: 687b ldr r3, [r7, #4] 80024f6: 681b ldr r3, [r3, #0] 80024f8: 695b ldr r3, [r3, #20] 80024fa: f003 0380 and.w r3, r3, #128 @ 0x80 80024fe: 2b00 cmp r3, #0 8002500: d00b beq.n 800251a { /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; 8002502: 687b ldr r3, [r7, #4] 8002504: 6ddb ldr r3, [r3, #92] @ 0x5c 8002506: 2201 movs r2, #1 8002508: 409a lsls r2, r3 800250a: 693b ldr r3, [r7, #16] 800250c: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 800250e: 687b ldr r3, [r7, #4] 8002510: 6d5b ldr r3, [r3, #84] @ 0x54 8002512: f043 0202 orr.w r2, r3, #2 8002516: 687b ldr r3, [r7, #4] 8002518: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) 800251a: 687b ldr r3, [r7, #4] 800251c: 6ddb ldr r3, [r3, #92] @ 0x5c 800251e: 2204 movs r2, #4 8002520: 409a lsls r2, r3 8002522: 68fb ldr r3, [r7, #12] 8002524: 4013 ands r3, r2 8002526: 2b00 cmp r3, #0 8002528: d012 beq.n 8002550 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) 800252a: 687b ldr r3, [r7, #4] 800252c: 681b ldr r3, [r3, #0] 800252e: 681b ldr r3, [r3, #0] 8002530: f003 0302 and.w r3, r3, #2 8002534: 2b00 cmp r3, #0 8002536: d00b beq.n 8002550 { /* Clear the direct mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; 8002538: 687b ldr r3, [r7, #4] 800253a: 6ddb ldr r3, [r3, #92] @ 0x5c 800253c: 2204 movs r2, #4 800253e: 409a lsls r2, r3 8002540: 693b ldr r3, [r7, #16] 8002542: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8002544: 687b ldr r3, [r7, #4] 8002546: 6d5b ldr r3, [r3, #84] @ 0x54 8002548: f043 0204 orr.w r2, r3, #4 800254c: 687b ldr r3, [r7, #4] 800254e: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) 8002550: 687b ldr r3, [r7, #4] 8002552: 6ddb ldr r3, [r3, #92] @ 0x5c 8002554: 2210 movs r2, #16 8002556: 409a lsls r2, r3 8002558: 68fb ldr r3, [r7, #12] 800255a: 4013 ands r3, r2 800255c: 2b00 cmp r3, #0 800255e: d043 beq.n 80025e8 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) 8002560: 687b ldr r3, [r7, #4] 8002562: 681b ldr r3, [r3, #0] 8002564: 681b ldr r3, [r3, #0] 8002566: f003 0308 and.w r3, r3, #8 800256a: 2b00 cmp r3, #0 800256c: d03c beq.n 80025e8 { /* Clear the half transfer complete flag */ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; 800256e: 687b ldr r3, [r7, #4] 8002570: 6ddb ldr r3, [r3, #92] @ 0x5c 8002572: 2210 movs r2, #16 8002574: 409a lsls r2, r3 8002576: 693b ldr r3, [r7, #16] 8002578: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 800257a: 687b ldr r3, [r7, #4] 800257c: 681b ldr r3, [r3, #0] 800257e: 681b ldr r3, [r3, #0] 8002580: f403 2380 and.w r3, r3, #262144 @ 0x40000 8002584: 2b00 cmp r3, #0 8002586: d018 beq.n 80025ba { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 8002588: 687b ldr r3, [r7, #4] 800258a: 681b ldr r3, [r3, #0] 800258c: 681b ldr r3, [r3, #0] 800258e: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002592: 2b00 cmp r3, #0 8002594: d108 bne.n 80025a8 { if(hdma->XferHalfCpltCallback != NULL) 8002596: 687b ldr r3, [r7, #4] 8002598: 6c1b ldr r3, [r3, #64] @ 0x40 800259a: 2b00 cmp r3, #0 800259c: d024 beq.n 80025e8 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800259e: 687b ldr r3, [r7, #4] 80025a0: 6c1b ldr r3, [r3, #64] @ 0x40 80025a2: 6878 ldr r0, [r7, #4] 80025a4: 4798 blx r3 80025a6: e01f b.n 80025e8 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 80025a8: 687b ldr r3, [r7, #4] 80025aa: 6c9b ldr r3, [r3, #72] @ 0x48 80025ac: 2b00 cmp r3, #0 80025ae: d01b beq.n 80025e8 { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 80025b0: 687b ldr r3, [r7, #4] 80025b2: 6c9b ldr r3, [r3, #72] @ 0x48 80025b4: 6878 ldr r0, [r7, #4] 80025b6: 4798 blx r3 80025b8: e016 b.n 80025e8 } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 80025ba: 687b ldr r3, [r7, #4] 80025bc: 681b ldr r3, [r3, #0] 80025be: 681b ldr r3, [r3, #0] 80025c0: f403 7380 and.w r3, r3, #256 @ 0x100 80025c4: 2b00 cmp r3, #0 80025c6: d107 bne.n 80025d8 { /* Disable the half transfer interrupt */ hdma->Instance->CR &= ~(DMA_IT_HT); 80025c8: 687b ldr r3, [r7, #4] 80025ca: 681b ldr r3, [r3, #0] 80025cc: 681a ldr r2, [r3, #0] 80025ce: 687b ldr r3, [r7, #4] 80025d0: 681b ldr r3, [r3, #0] 80025d2: f022 0208 bic.w r2, r2, #8 80025d6: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 80025d8: 687b ldr r3, [r7, #4] 80025da: 6c1b ldr r3, [r3, #64] @ 0x40 80025dc: 2b00 cmp r3, #0 80025de: d003 beq.n 80025e8 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 80025e0: 687b ldr r3, [r7, #4] 80025e2: 6c1b ldr r3, [r3, #64] @ 0x40 80025e4: 6878 ldr r0, [r7, #4] 80025e6: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) 80025e8: 687b ldr r3, [r7, #4] 80025ea: 6ddb ldr r3, [r3, #92] @ 0x5c 80025ec: 2220 movs r2, #32 80025ee: 409a lsls r2, r3 80025f0: 68fb ldr r3, [r7, #12] 80025f2: 4013 ands r3, r2 80025f4: 2b00 cmp r3, #0 80025f6: f000 808f beq.w 8002718 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) 80025fa: 687b ldr r3, [r7, #4] 80025fc: 681b ldr r3, [r3, #0] 80025fe: 681b ldr r3, [r3, #0] 8002600: f003 0310 and.w r3, r3, #16 8002604: 2b00 cmp r3, #0 8002606: f000 8087 beq.w 8002718 { /* Clear the transfer complete flag */ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; 800260a: 687b ldr r3, [r7, #4] 800260c: 6ddb ldr r3, [r3, #92] @ 0x5c 800260e: 2220 movs r2, #32 8002610: 409a lsls r2, r3 8002612: 693b ldr r3, [r7, #16] 8002614: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 8002616: 687b ldr r3, [r7, #4] 8002618: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 800261c: b2db uxtb r3, r3 800261e: 2b05 cmp r3, #5 8002620: d136 bne.n 8002690 { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8002622: 687b ldr r3, [r7, #4] 8002624: 681b ldr r3, [r3, #0] 8002626: 681a ldr r2, [r3, #0] 8002628: 687b ldr r3, [r7, #4] 800262a: 681b ldr r3, [r3, #0] 800262c: f022 0216 bic.w r2, r2, #22 8002630: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 8002632: 687b ldr r3, [r7, #4] 8002634: 681b ldr r3, [r3, #0] 8002636: 695a ldr r2, [r3, #20] 8002638: 687b ldr r3, [r7, #4] 800263a: 681b ldr r3, [r3, #0] 800263c: f022 0280 bic.w r2, r2, #128 @ 0x80 8002640: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8002642: 687b ldr r3, [r7, #4] 8002644: 6c1b ldr r3, [r3, #64] @ 0x40 8002646: 2b00 cmp r3, #0 8002648: d103 bne.n 8002652 800264a: 687b ldr r3, [r7, #4] 800264c: 6c9b ldr r3, [r3, #72] @ 0x48 800264e: 2b00 cmp r3, #0 8002650: d007 beq.n 8002662 { hdma->Instance->CR &= ~(DMA_IT_HT); 8002652: 687b ldr r3, [r7, #4] 8002654: 681b ldr r3, [r3, #0] 8002656: 681a ldr r2, [r3, #0] 8002658: 687b ldr r3, [r7, #4] 800265a: 681b ldr r3, [r3, #0] 800265c: f022 0208 bic.w r2, r2, #8 8002660: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8002662: 687b ldr r3, [r7, #4] 8002664: 6ddb ldr r3, [r3, #92] @ 0x5c 8002666: 223f movs r2, #63 @ 0x3f 8002668: 409a lsls r2, r3 800266a: 693b ldr r3, [r7, #16] 800266c: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800266e: 687b ldr r3, [r7, #4] 8002670: 2201 movs r2, #1 8002672: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002676: 687b ldr r3, [r7, #4] 8002678: 2200 movs r2, #0 800267a: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 800267e: 687b ldr r3, [r7, #4] 8002680: 6d1b ldr r3, [r3, #80] @ 0x50 8002682: 2b00 cmp r3, #0 8002684: d07e beq.n 8002784 { hdma->XferAbortCallback(hdma); 8002686: 687b ldr r3, [r7, #4] 8002688: 6d1b ldr r3, [r3, #80] @ 0x50 800268a: 6878 ldr r0, [r7, #4] 800268c: 4798 blx r3 } return; 800268e: e079 b.n 8002784 } if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 8002690: 687b ldr r3, [r7, #4] 8002692: 681b ldr r3, [r3, #0] 8002694: 681b ldr r3, [r3, #0] 8002696: f403 2380 and.w r3, r3, #262144 @ 0x40000 800269a: 2b00 cmp r3, #0 800269c: d01d beq.n 80026da { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 800269e: 687b ldr r3, [r7, #4] 80026a0: 681b ldr r3, [r3, #0] 80026a2: 681b ldr r3, [r3, #0] 80026a4: f403 2300 and.w r3, r3, #524288 @ 0x80000 80026a8: 2b00 cmp r3, #0 80026aa: d10d bne.n 80026c8 { if(hdma->XferM1CpltCallback != NULL) 80026ac: 687b ldr r3, [r7, #4] 80026ae: 6c5b ldr r3, [r3, #68] @ 0x44 80026b0: 2b00 cmp r3, #0 80026b2: d031 beq.n 8002718 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 80026b4: 687b ldr r3, [r7, #4] 80026b6: 6c5b ldr r3, [r3, #68] @ 0x44 80026b8: 6878 ldr r0, [r7, #4] 80026ba: 4798 blx r3 80026bc: e02c b.n 8002718 80026be: bf00 nop 80026c0: 20000090 .word 0x20000090 80026c4: 1b4e81b5 .word 0x1b4e81b5 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 80026c8: 687b ldr r3, [r7, #4] 80026ca: 6bdb ldr r3, [r3, #60] @ 0x3c 80026cc: 2b00 cmp r3, #0 80026ce: d023 beq.n 8002718 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 80026d0: 687b ldr r3, [r7, #4] 80026d2: 6bdb ldr r3, [r3, #60] @ 0x3c 80026d4: 6878 ldr r0, [r7, #4] 80026d6: 4798 blx r3 80026d8: e01e b.n 8002718 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 80026da: 687b ldr r3, [r7, #4] 80026dc: 681b ldr r3, [r3, #0] 80026de: 681b ldr r3, [r3, #0] 80026e0: f403 7380 and.w r3, r3, #256 @ 0x100 80026e4: 2b00 cmp r3, #0 80026e6: d10f bne.n 8002708 { /* Disable the transfer complete interrupt */ hdma->Instance->CR &= ~(DMA_IT_TC); 80026e8: 687b ldr r3, [r7, #4] 80026ea: 681b ldr r3, [r3, #0] 80026ec: 681a ldr r2, [r3, #0] 80026ee: 687b ldr r3, [r7, #4] 80026f0: 681b ldr r3, [r3, #0] 80026f2: f022 0210 bic.w r2, r2, #16 80026f6: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80026f8: 687b ldr r3, [r7, #4] 80026fa: 2201 movs r2, #1 80026fc: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002700: 687b ldr r3, [r7, #4] 8002702: 2200 movs r2, #0 8002704: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 8002708: 687b ldr r3, [r7, #4] 800270a: 6bdb ldr r3, [r3, #60] @ 0x3c 800270c: 2b00 cmp r3, #0 800270e: d003 beq.n 8002718 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8002710: 687b ldr r3, [r7, #4] 8002712: 6bdb ldr r3, [r3, #60] @ 0x3c 8002714: 6878 ldr r0, [r7, #4] 8002716: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 8002718: 687b ldr r3, [r7, #4] 800271a: 6d5b ldr r3, [r3, #84] @ 0x54 800271c: 2b00 cmp r3, #0 800271e: d032 beq.n 8002786 { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) 8002720: 687b ldr r3, [r7, #4] 8002722: 6d5b ldr r3, [r3, #84] @ 0x54 8002724: f003 0301 and.w r3, r3, #1 8002728: 2b00 cmp r3, #0 800272a: d022 beq.n 8002772 { hdma->State = HAL_DMA_STATE_ABORT; 800272c: 687b ldr r3, [r7, #4] 800272e: 2205 movs r2, #5 8002730: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8002734: 687b ldr r3, [r7, #4] 8002736: 681b ldr r3, [r3, #0] 8002738: 681a ldr r2, [r3, #0] 800273a: 687b ldr r3, [r7, #4] 800273c: 681b ldr r3, [r3, #0] 800273e: f022 0201 bic.w r2, r2, #1 8002742: 601a str r2, [r3, #0] do { if (++count > timeout) 8002744: 68bb ldr r3, [r7, #8] 8002746: 3301 adds r3, #1 8002748: 60bb str r3, [r7, #8] 800274a: 697a ldr r2, [r7, #20] 800274c: 429a cmp r2, r3 800274e: d307 bcc.n 8002760 { break; } } while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); 8002750: 687b ldr r3, [r7, #4] 8002752: 681b ldr r3, [r3, #0] 8002754: 681b ldr r3, [r3, #0] 8002756: f003 0301 and.w r3, r3, #1 800275a: 2b00 cmp r3, #0 800275c: d1f2 bne.n 8002744 800275e: e000 b.n 8002762 break; 8002760: bf00 nop /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002762: 687b ldr r3, [r7, #4] 8002764: 2201 movs r2, #1 8002766: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800276a: 687b ldr r3, [r7, #4] 800276c: 2200 movs r2, #0 800276e: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 8002772: 687b ldr r3, [r7, #4] 8002774: 6cdb ldr r3, [r3, #76] @ 0x4c 8002776: 2b00 cmp r3, #0 8002778: d005 beq.n 8002786 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800277a: 687b ldr r3, [r7, #4] 800277c: 6cdb ldr r3, [r3, #76] @ 0x4c 800277e: 6878 ldr r0, [r7, #4] 8002780: 4798 blx r3 8002782: e000 b.n 8002786 return; 8002784: bf00 nop } } } 8002786: 3718 adds r7, #24 8002788: 46bd mov sp, r7 800278a: bd80 pop {r7, pc} 0800278c : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800278c: b480 push {r7} 800278e: b085 sub sp, #20 8002790: af00 add r7, sp, #0 8002792: 60f8 str r0, [r7, #12] 8002794: 60b9 str r1, [r7, #8] 8002796: 607a str r2, [r7, #4] 8002798: 603b str r3, [r7, #0] /* Clear DBM bit */ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); 800279a: 68fb ldr r3, [r7, #12] 800279c: 681b ldr r3, [r3, #0] 800279e: 681a ldr r2, [r3, #0] 80027a0: 68fb ldr r3, [r7, #12] 80027a2: 681b ldr r3, [r3, #0] 80027a4: f422 2280 bic.w r2, r2, #262144 @ 0x40000 80027a8: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; 80027aa: 68fb ldr r3, [r7, #12] 80027ac: 681b ldr r3, [r3, #0] 80027ae: 683a ldr r2, [r7, #0] 80027b0: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 80027b2: 68fb ldr r3, [r7, #12] 80027b4: 689b ldr r3, [r3, #8] 80027b6: 2b40 cmp r3, #64 @ 0x40 80027b8: d108 bne.n 80027cc { /* Configure DMA Stream destination address */ hdma->Instance->PAR = DstAddress; 80027ba: 68fb ldr r3, [r7, #12] 80027bc: 681b ldr r3, [r3, #0] 80027be: 687a ldr r2, [r7, #4] 80027c0: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; 80027c2: 68fb ldr r3, [r7, #12] 80027c4: 681b ldr r3, [r3, #0] 80027c6: 68ba ldr r2, [r7, #8] 80027c8: 60da str r2, [r3, #12] hdma->Instance->PAR = SrcAddress; /* Configure DMA Stream destination address */ hdma->Instance->M0AR = DstAddress; } } 80027ca: e007 b.n 80027dc hdma->Instance->PAR = SrcAddress; 80027cc: 68fb ldr r3, [r7, #12] 80027ce: 681b ldr r3, [r3, #0] 80027d0: 68ba ldr r2, [r7, #8] 80027d2: 609a str r2, [r3, #8] hdma->Instance->M0AR = DstAddress; 80027d4: 68fb ldr r3, [r7, #12] 80027d6: 681b ldr r3, [r3, #0] 80027d8: 687a ldr r2, [r7, #4] 80027da: 60da str r2, [r3, #12] } 80027dc: bf00 nop 80027de: 3714 adds r7, #20 80027e0: 46bd mov sp, r7 80027e2: f85d 7b04 ldr.w r7, [sp], #4 80027e6: 4770 bx lr 080027e8 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 80027e8: b480 push {r7} 80027ea: b085 sub sp, #20 80027ec: af00 add r7, sp, #0 80027ee: 6078 str r0, [r7, #4] uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; 80027f0: 687b ldr r3, [r7, #4] 80027f2: 681b ldr r3, [r3, #0] 80027f4: b2db uxtb r3, r3 80027f6: 3b10 subs r3, #16 80027f8: 4a14 ldr r2, [pc, #80] @ (800284c ) 80027fa: fba2 2303 umull r2, r3, r2, r3 80027fe: 091b lsrs r3, r3, #4 8002800: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number]; 8002802: 4a13 ldr r2, [pc, #76] @ (8002850 ) 8002804: 68fb ldr r3, [r7, #12] 8002806: 4413 add r3, r2 8002808: 781b ldrb r3, [r3, #0] 800280a: 461a mov r2, r3 800280c: 687b ldr r3, [r7, #4] 800280e: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 8002810: 68fb ldr r3, [r7, #12] 8002812: 2b03 cmp r3, #3 8002814: d909 bls.n 800282a { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); 8002816: 687b ldr r3, [r7, #4] 8002818: 681b ldr r3, [r3, #0] 800281a: f423 737f bic.w r3, r3, #1020 @ 0x3fc 800281e: f023 0303 bic.w r3, r3, #3 8002822: 1d1a adds r2, r3, #4 8002824: 687b ldr r3, [r7, #4] 8002826: 659a str r2, [r3, #88] @ 0x58 8002828: e007 b.n 800283a } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); 800282a: 687b ldr r3, [r7, #4] 800282c: 681b ldr r3, [r3, #0] 800282e: f423 737f bic.w r3, r3, #1020 @ 0x3fc 8002832: f023 0303 bic.w r3, r3, #3 8002836: 687a ldr r2, [r7, #4] 8002838: 6593 str r3, [r2, #88] @ 0x58 } return hdma->StreamBaseAddress; 800283a: 687b ldr r3, [r7, #4] 800283c: 6d9b ldr r3, [r3, #88] @ 0x58 } 800283e: 4618 mov r0, r3 8002840: 3714 adds r7, #20 8002842: 46bd mov sp, r7 8002844: f85d 7b04 ldr.w r7, [sp], #4 8002848: 4770 bx lr 800284a: bf00 nop 800284c: aaaaaaab .word 0xaaaaaaab 8002850: 0800b7e8 .word 0x0800b7e8 08002854 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 8002854: b480 push {r7} 8002856: b085 sub sp, #20 8002858: af00 add r7, sp, #0 800285a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800285c: 2300 movs r3, #0 800285e: 73fb strb r3, [r7, #15] uint32_t tmp = hdma->Init.FIFOThreshold; 8002860: 687b ldr r3, [r7, #4] 8002862: 6a9b ldr r3, [r3, #40] @ 0x28 8002864: 60bb str r3, [r7, #8] /* Memory Data size equal to Byte */ if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 8002866: 687b ldr r3, [r7, #4] 8002868: 699b ldr r3, [r3, #24] 800286a: 2b00 cmp r3, #0 800286c: d11f bne.n 80028ae { switch (tmp) 800286e: 68bb ldr r3, [r7, #8] 8002870: 2b03 cmp r3, #3 8002872: d856 bhi.n 8002922 8002874: a201 add r2, pc, #4 @ (adr r2, 800287c ) 8002876: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800287a: bf00 nop 800287c: 0800288d .word 0x0800288d 8002880: 0800289f .word 0x0800289f 8002884: 0800288d .word 0x0800288d 8002888: 08002923 .word 0x08002923 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800288c: 687b ldr r3, [r7, #4] 800288e: 6adb ldr r3, [r3, #44] @ 0x2c 8002890: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002894: 2b00 cmp r3, #0 8002896: d046 beq.n 8002926 { status = HAL_ERROR; 8002898: 2301 movs r3, #1 800289a: 73fb strb r3, [r7, #15] } break; 800289c: e043 b.n 8002926 case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800289e: 687b ldr r3, [r7, #4] 80028a0: 6adb ldr r3, [r3, #44] @ 0x2c 80028a2: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 80028a6: d140 bne.n 800292a { status = HAL_ERROR; 80028a8: 2301 movs r3, #1 80028aa: 73fb strb r3, [r7, #15] } break; 80028ac: e03d b.n 800292a break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 80028ae: 687b ldr r3, [r7, #4] 80028b0: 699b ldr r3, [r3, #24] 80028b2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80028b6: d121 bne.n 80028fc { switch (tmp) 80028b8: 68bb ldr r3, [r7, #8] 80028ba: 2b03 cmp r3, #3 80028bc: d837 bhi.n 800292e 80028be: a201 add r2, pc, #4 @ (adr r2, 80028c4 ) 80028c0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80028c4: 080028d5 .word 0x080028d5 80028c8: 080028db .word 0x080028db 80028cc: 080028d5 .word 0x080028d5 80028d0: 080028ed .word 0x080028ed { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 80028d4: 2301 movs r3, #1 80028d6: 73fb strb r3, [r7, #15] break; 80028d8: e030 b.n 800293c case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 80028da: 687b ldr r3, [r7, #4] 80028dc: 6adb ldr r3, [r3, #44] @ 0x2c 80028de: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80028e2: 2b00 cmp r3, #0 80028e4: d025 beq.n 8002932 { status = HAL_ERROR; 80028e6: 2301 movs r3, #1 80028e8: 73fb strb r3, [r7, #15] } break; 80028ea: e022 b.n 8002932 case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 80028ec: 687b ldr r3, [r7, #4] 80028ee: 6adb ldr r3, [r3, #44] @ 0x2c 80028f0: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 80028f4: d11f bne.n 8002936 { status = HAL_ERROR; 80028f6: 2301 movs r3, #1 80028f8: 73fb strb r3, [r7, #15] } break; 80028fa: e01c b.n 8002936 } /* Memory Data size equal to Word */ else { switch (tmp) 80028fc: 68bb ldr r3, [r7, #8] 80028fe: 2b02 cmp r3, #2 8002900: d903 bls.n 800290a 8002902: 68bb ldr r3, [r7, #8] 8002904: 2b03 cmp r3, #3 8002906: d003 beq.n 8002910 { status = HAL_ERROR; } break; default: break; 8002908: e018 b.n 800293c status = HAL_ERROR; 800290a: 2301 movs r3, #1 800290c: 73fb strb r3, [r7, #15] break; 800290e: e015 b.n 800293c if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002910: 687b ldr r3, [r7, #4] 8002912: 6adb ldr r3, [r3, #44] @ 0x2c 8002914: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002918: 2b00 cmp r3, #0 800291a: d00e beq.n 800293a status = HAL_ERROR; 800291c: 2301 movs r3, #1 800291e: 73fb strb r3, [r7, #15] break; 8002920: e00b b.n 800293a break; 8002922: bf00 nop 8002924: e00a b.n 800293c break; 8002926: bf00 nop 8002928: e008 b.n 800293c break; 800292a: bf00 nop 800292c: e006 b.n 800293c break; 800292e: bf00 nop 8002930: e004 b.n 800293c break; 8002932: bf00 nop 8002934: e002 b.n 800293c break; 8002936: bf00 nop 8002938: e000 b.n 800293c break; 800293a: bf00 nop } } return status; 800293c: 7bfb ldrb r3, [r7, #15] } 800293e: 4618 mov r0, r3 8002940: 3714 adds r7, #20 8002942: 46bd mov sp, r7 8002944: f85d 7b04 ldr.w r7, [sp], #4 8002948: 4770 bx lr 800294a: bf00 nop 0800294c : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800294c: b480 push {r7} 800294e: b089 sub sp, #36 @ 0x24 8002950: af00 add r7, sp, #0 8002952: 6078 str r0, [r7, #4] 8002954: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 8002956: 2300 movs r3, #0 8002958: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 800295a: 2300 movs r3, #0 800295c: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 800295e: 2300 movs r3, #0 8002960: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 8002962: 2300 movs r3, #0 8002964: 61fb str r3, [r7, #28] 8002966: e165 b.n 8002c34 { /* Get the IO position */ ioposition = 0x01U << position; 8002968: 2201 movs r2, #1 800296a: 69fb ldr r3, [r7, #28] 800296c: fa02 f303 lsl.w r3, r2, r3 8002970: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8002972: 683b ldr r3, [r7, #0] 8002974: 681b ldr r3, [r3, #0] 8002976: 697a ldr r2, [r7, #20] 8002978: 4013 ands r3, r2 800297a: 613b str r3, [r7, #16] if(iocurrent == ioposition) 800297c: 693a ldr r2, [r7, #16] 800297e: 697b ldr r3, [r7, #20] 8002980: 429a cmp r2, r3 8002982: f040 8154 bne.w 8002c2e { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8002986: 683b ldr r3, [r7, #0] 8002988: 685b ldr r3, [r3, #4] 800298a: f003 0303 and.w r3, r3, #3 800298e: 2b01 cmp r3, #1 8002990: d005 beq.n 800299e (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002992: 683b ldr r3, [r7, #0] 8002994: 685b ldr r3, [r3, #4] 8002996: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 800299a: 2b02 cmp r3, #2 800299c: d130 bne.n 8002a00 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800299e: 687b ldr r3, [r7, #4] 80029a0: 689b ldr r3, [r3, #8] 80029a2: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 80029a4: 69fb ldr r3, [r7, #28] 80029a6: 005b lsls r3, r3, #1 80029a8: 2203 movs r2, #3 80029aa: fa02 f303 lsl.w r3, r2, r3 80029ae: 43db mvns r3, r3 80029b0: 69ba ldr r2, [r7, #24] 80029b2: 4013 ands r3, r2 80029b4: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 80029b6: 683b ldr r3, [r7, #0] 80029b8: 68da ldr r2, [r3, #12] 80029ba: 69fb ldr r3, [r7, #28] 80029bc: 005b lsls r3, r3, #1 80029be: fa02 f303 lsl.w r3, r2, r3 80029c2: 69ba ldr r2, [r7, #24] 80029c4: 4313 orrs r3, r2 80029c6: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 80029c8: 687b ldr r3, [r7, #4] 80029ca: 69ba ldr r2, [r7, #24] 80029cc: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 80029ce: 687b ldr r3, [r7, #4] 80029d0: 685b ldr r3, [r3, #4] 80029d2: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 80029d4: 2201 movs r2, #1 80029d6: 69fb ldr r3, [r7, #28] 80029d8: fa02 f303 lsl.w r3, r2, r3 80029dc: 43db mvns r3, r3 80029de: 69ba ldr r2, [r7, #24] 80029e0: 4013 ands r3, r2 80029e2: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80029e4: 683b ldr r3, [r7, #0] 80029e6: 685b ldr r3, [r3, #4] 80029e8: 091b lsrs r3, r3, #4 80029ea: f003 0201 and.w r2, r3, #1 80029ee: 69fb ldr r3, [r7, #28] 80029f0: fa02 f303 lsl.w r3, r2, r3 80029f4: 69ba ldr r2, [r7, #24] 80029f6: 4313 orrs r3, r2 80029f8: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 80029fa: 687b ldr r3, [r7, #4] 80029fc: 69ba ldr r2, [r7, #24] 80029fe: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8002a00: 683b ldr r3, [r7, #0] 8002a02: 685b ldr r3, [r3, #4] 8002a04: f003 0303 and.w r3, r3, #3 8002a08: 2b03 cmp r3, #3 8002a0a: d017 beq.n 8002a3c { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8002a0c: 687b ldr r3, [r7, #4] 8002a0e: 68db ldr r3, [r3, #12] 8002a10: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8002a12: 69fb ldr r3, [r7, #28] 8002a14: 005b lsls r3, r3, #1 8002a16: 2203 movs r2, #3 8002a18: fa02 f303 lsl.w r3, r2, r3 8002a1c: 43db mvns r3, r3 8002a1e: 69ba ldr r2, [r7, #24] 8002a20: 4013 ands r3, r2 8002a22: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8002a24: 683b ldr r3, [r7, #0] 8002a26: 689a ldr r2, [r3, #8] 8002a28: 69fb ldr r3, [r7, #28] 8002a2a: 005b lsls r3, r3, #1 8002a2c: fa02 f303 lsl.w r3, r2, r3 8002a30: 69ba ldr r2, [r7, #24] 8002a32: 4313 orrs r3, r2 8002a34: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8002a36: 687b ldr r3, [r7, #4] 8002a38: 69ba ldr r2, [r7, #24] 8002a3a: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002a3c: 683b ldr r3, [r7, #0] 8002a3e: 685b ldr r3, [r3, #4] 8002a40: f003 0303 and.w r3, r3, #3 8002a44: 2b02 cmp r3, #2 8002a46: d123 bne.n 8002a90 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8002a48: 69fb ldr r3, [r7, #28] 8002a4a: 08da lsrs r2, r3, #3 8002a4c: 687b ldr r3, [r7, #4] 8002a4e: 3208 adds r2, #8 8002a50: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8002a54: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 8002a56: 69fb ldr r3, [r7, #28] 8002a58: f003 0307 and.w r3, r3, #7 8002a5c: 009b lsls r3, r3, #2 8002a5e: 220f movs r2, #15 8002a60: fa02 f303 lsl.w r3, r2, r3 8002a64: 43db mvns r3, r3 8002a66: 69ba ldr r2, [r7, #24] 8002a68: 4013 ands r3, r2 8002a6a: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 8002a6c: 683b ldr r3, [r7, #0] 8002a6e: 691a ldr r2, [r3, #16] 8002a70: 69fb ldr r3, [r7, #28] 8002a72: f003 0307 and.w r3, r3, #7 8002a76: 009b lsls r3, r3, #2 8002a78: fa02 f303 lsl.w r3, r2, r3 8002a7c: 69ba ldr r2, [r7, #24] 8002a7e: 4313 orrs r3, r2 8002a80: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8002a82: 69fb ldr r3, [r7, #28] 8002a84: 08da lsrs r2, r3, #3 8002a86: 687b ldr r3, [r7, #4] 8002a88: 3208 adds r2, #8 8002a8a: 69b9 ldr r1, [r7, #24] 8002a8c: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8002a90: 687b ldr r3, [r7, #4] 8002a92: 681b ldr r3, [r3, #0] 8002a94: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 8002a96: 69fb ldr r3, [r7, #28] 8002a98: 005b lsls r3, r3, #1 8002a9a: 2203 movs r2, #3 8002a9c: fa02 f303 lsl.w r3, r2, r3 8002aa0: 43db mvns r3, r3 8002aa2: 69ba ldr r2, [r7, #24] 8002aa4: 4013 ands r3, r2 8002aa6: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8002aa8: 683b ldr r3, [r7, #0] 8002aaa: 685b ldr r3, [r3, #4] 8002aac: f003 0203 and.w r2, r3, #3 8002ab0: 69fb ldr r3, [r7, #28] 8002ab2: 005b lsls r3, r3, #1 8002ab4: fa02 f303 lsl.w r3, r2, r3 8002ab8: 69ba ldr r2, [r7, #24] 8002aba: 4313 orrs r3, r2 8002abc: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8002abe: 687b ldr r3, [r7, #4] 8002ac0: 69ba ldr r2, [r7, #24] 8002ac2: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8002ac4: 683b ldr r3, [r7, #0] 8002ac6: 685b ldr r3, [r3, #4] 8002ac8: f403 3340 and.w r3, r3, #196608 @ 0x30000 8002acc: 2b00 cmp r3, #0 8002ace: f000 80ae beq.w 8002c2e { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002ad2: 2300 movs r3, #0 8002ad4: 60fb str r3, [r7, #12] 8002ad6: 4b5d ldr r3, [pc, #372] @ (8002c4c ) 8002ad8: 6c5b ldr r3, [r3, #68] @ 0x44 8002ada: 4a5c ldr r2, [pc, #368] @ (8002c4c ) 8002adc: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002ae0: 6453 str r3, [r2, #68] @ 0x44 8002ae2: 4b5a ldr r3, [pc, #360] @ (8002c4c ) 8002ae4: 6c5b ldr r3, [r3, #68] @ 0x44 8002ae6: f403 4380 and.w r3, r3, #16384 @ 0x4000 8002aea: 60fb str r3, [r7, #12] 8002aec: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8002aee: 4a58 ldr r2, [pc, #352] @ (8002c50 ) 8002af0: 69fb ldr r3, [r7, #28] 8002af2: 089b lsrs r3, r3, #2 8002af4: 3302 adds r3, #2 8002af6: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8002afa: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8002afc: 69fb ldr r3, [r7, #28] 8002afe: f003 0303 and.w r3, r3, #3 8002b02: 009b lsls r3, r3, #2 8002b04: 220f movs r2, #15 8002b06: fa02 f303 lsl.w r3, r2, r3 8002b0a: 43db mvns r3, r3 8002b0c: 69ba ldr r2, [r7, #24] 8002b0e: 4013 ands r3, r2 8002b10: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8002b12: 687b ldr r3, [r7, #4] 8002b14: 4a4f ldr r2, [pc, #316] @ (8002c54 ) 8002b16: 4293 cmp r3, r2 8002b18: d025 beq.n 8002b66 8002b1a: 687b ldr r3, [r7, #4] 8002b1c: 4a4e ldr r2, [pc, #312] @ (8002c58 ) 8002b1e: 4293 cmp r3, r2 8002b20: d01f beq.n 8002b62 8002b22: 687b ldr r3, [r7, #4] 8002b24: 4a4d ldr r2, [pc, #308] @ (8002c5c ) 8002b26: 4293 cmp r3, r2 8002b28: d019 beq.n 8002b5e 8002b2a: 687b ldr r3, [r7, #4] 8002b2c: 4a4c ldr r2, [pc, #304] @ (8002c60 ) 8002b2e: 4293 cmp r3, r2 8002b30: d013 beq.n 8002b5a 8002b32: 687b ldr r3, [r7, #4] 8002b34: 4a4b ldr r2, [pc, #300] @ (8002c64 ) 8002b36: 4293 cmp r3, r2 8002b38: d00d beq.n 8002b56 8002b3a: 687b ldr r3, [r7, #4] 8002b3c: 4a4a ldr r2, [pc, #296] @ (8002c68 ) 8002b3e: 4293 cmp r3, r2 8002b40: d007 beq.n 8002b52 8002b42: 687b ldr r3, [r7, #4] 8002b44: 4a49 ldr r2, [pc, #292] @ (8002c6c ) 8002b46: 4293 cmp r3, r2 8002b48: d101 bne.n 8002b4e 8002b4a: 2306 movs r3, #6 8002b4c: e00c b.n 8002b68 8002b4e: 2307 movs r3, #7 8002b50: e00a b.n 8002b68 8002b52: 2305 movs r3, #5 8002b54: e008 b.n 8002b68 8002b56: 2304 movs r3, #4 8002b58: e006 b.n 8002b68 8002b5a: 2303 movs r3, #3 8002b5c: e004 b.n 8002b68 8002b5e: 2302 movs r3, #2 8002b60: e002 b.n 8002b68 8002b62: 2301 movs r3, #1 8002b64: e000 b.n 8002b68 8002b66: 2300 movs r3, #0 8002b68: 69fa ldr r2, [r7, #28] 8002b6a: f002 0203 and.w r2, r2, #3 8002b6e: 0092 lsls r2, r2, #2 8002b70: 4093 lsls r3, r2 8002b72: 69ba ldr r2, [r7, #24] 8002b74: 4313 orrs r3, r2 8002b76: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8002b78: 4935 ldr r1, [pc, #212] @ (8002c50 ) 8002b7a: 69fb ldr r3, [r7, #28] 8002b7c: 089b lsrs r3, r3, #2 8002b7e: 3302 adds r3, #2 8002b80: 69ba ldr r2, [r7, #24] 8002b82: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8002b86: 4b3a ldr r3, [pc, #232] @ (8002c70 ) 8002b88: 689b ldr r3, [r3, #8] 8002b8a: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002b8c: 693b ldr r3, [r7, #16] 8002b8e: 43db mvns r3, r3 8002b90: 69ba ldr r2, [r7, #24] 8002b92: 4013 ands r3, r2 8002b94: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8002b96: 683b ldr r3, [r7, #0] 8002b98: 685b ldr r3, [r3, #4] 8002b9a: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8002b9e: 2b00 cmp r3, #0 8002ba0: d003 beq.n 8002baa { temp |= iocurrent; 8002ba2: 69ba ldr r2, [r7, #24] 8002ba4: 693b ldr r3, [r7, #16] 8002ba6: 4313 orrs r3, r2 8002ba8: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 8002baa: 4a31 ldr r2, [pc, #196] @ (8002c70 ) 8002bac: 69bb ldr r3, [r7, #24] 8002bae: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8002bb0: 4b2f ldr r3, [pc, #188] @ (8002c70 ) 8002bb2: 68db ldr r3, [r3, #12] 8002bb4: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002bb6: 693b ldr r3, [r7, #16] 8002bb8: 43db mvns r3, r3 8002bba: 69ba ldr r2, [r7, #24] 8002bbc: 4013 ands r3, r2 8002bbe: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8002bc0: 683b ldr r3, [r7, #0] 8002bc2: 685b ldr r3, [r3, #4] 8002bc4: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8002bc8: 2b00 cmp r3, #0 8002bca: d003 beq.n 8002bd4 { temp |= iocurrent; 8002bcc: 69ba ldr r2, [r7, #24] 8002bce: 693b ldr r3, [r7, #16] 8002bd0: 4313 orrs r3, r2 8002bd2: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8002bd4: 4a26 ldr r2, [pc, #152] @ (8002c70 ) 8002bd6: 69bb ldr r3, [r7, #24] 8002bd8: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 8002bda: 4b25 ldr r3, [pc, #148] @ (8002c70 ) 8002bdc: 685b ldr r3, [r3, #4] 8002bde: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002be0: 693b ldr r3, [r7, #16] 8002be2: 43db mvns r3, r3 8002be4: 69ba ldr r2, [r7, #24] 8002be6: 4013 ands r3, r2 8002be8: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8002bea: 683b ldr r3, [r7, #0] 8002bec: 685b ldr r3, [r3, #4] 8002bee: f403 3300 and.w r3, r3, #131072 @ 0x20000 8002bf2: 2b00 cmp r3, #0 8002bf4: d003 beq.n 8002bfe { temp |= iocurrent; 8002bf6: 69ba ldr r2, [r7, #24] 8002bf8: 693b ldr r3, [r7, #16] 8002bfa: 4313 orrs r3, r2 8002bfc: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 8002bfe: 4a1c ldr r2, [pc, #112] @ (8002c70 ) 8002c00: 69bb ldr r3, [r7, #24] 8002c02: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8002c04: 4b1a ldr r3, [pc, #104] @ (8002c70 ) 8002c06: 681b ldr r3, [r3, #0] 8002c08: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002c0a: 693b ldr r3, [r7, #16] 8002c0c: 43db mvns r3, r3 8002c0e: 69ba ldr r2, [r7, #24] 8002c10: 4013 ands r3, r2 8002c12: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8002c14: 683b ldr r3, [r7, #0] 8002c16: 685b ldr r3, [r3, #4] 8002c18: f403 3380 and.w r3, r3, #65536 @ 0x10000 8002c1c: 2b00 cmp r3, #0 8002c1e: d003 beq.n 8002c28 { temp |= iocurrent; 8002c20: 69ba ldr r2, [r7, #24] 8002c22: 693b ldr r3, [r7, #16] 8002c24: 4313 orrs r3, r2 8002c26: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 8002c28: 4a11 ldr r2, [pc, #68] @ (8002c70 ) 8002c2a: 69bb ldr r3, [r7, #24] 8002c2c: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 8002c2e: 69fb ldr r3, [r7, #28] 8002c30: 3301 adds r3, #1 8002c32: 61fb str r3, [r7, #28] 8002c34: 69fb ldr r3, [r7, #28] 8002c36: 2b0f cmp r3, #15 8002c38: f67f ae96 bls.w 8002968 } } } } 8002c3c: bf00 nop 8002c3e: bf00 nop 8002c40: 3724 adds r7, #36 @ 0x24 8002c42: 46bd mov sp, r7 8002c44: f85d 7b04 ldr.w r7, [sp], #4 8002c48: 4770 bx lr 8002c4a: bf00 nop 8002c4c: 40023800 .word 0x40023800 8002c50: 40013800 .word 0x40013800 8002c54: 40020000 .word 0x40020000 8002c58: 40020400 .word 0x40020400 8002c5c: 40020800 .word 0x40020800 8002c60: 40020c00 .word 0x40020c00 8002c64: 40021000 .word 0x40021000 8002c68: 40021400 .word 0x40021400 8002c6c: 40021800 .word 0x40021800 8002c70: 40013c00 .word 0x40013c00 08002c74 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8002c74: b480 push {r7} 8002c76: b085 sub sp, #20 8002c78: af00 add r7, sp, #0 8002c7a: 6078 str r0, [r7, #4] 8002c7c: 460b mov r3, r1 8002c7e: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8002c80: 687b ldr r3, [r7, #4] 8002c82: 691a ldr r2, [r3, #16] 8002c84: 887b ldrh r3, [r7, #2] 8002c86: 4013 ands r3, r2 8002c88: 2b00 cmp r3, #0 8002c8a: d002 beq.n 8002c92 { bitstatus = GPIO_PIN_SET; 8002c8c: 2301 movs r3, #1 8002c8e: 73fb strb r3, [r7, #15] 8002c90: e001 b.n 8002c96 } else { bitstatus = GPIO_PIN_RESET; 8002c92: 2300 movs r3, #0 8002c94: 73fb strb r3, [r7, #15] } return bitstatus; 8002c96: 7bfb ldrb r3, [r7, #15] } 8002c98: 4618 mov r0, r3 8002c9a: 3714 adds r7, #20 8002c9c: 46bd mov sp, r7 8002c9e: f85d 7b04 ldr.w r7, [sp], #4 8002ca2: 4770 bx lr 08002ca4 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8002ca4: b480 push {r7} 8002ca6: b083 sub sp, #12 8002ca8: af00 add r7, sp, #0 8002caa: 6078 str r0, [r7, #4] 8002cac: 460b mov r3, r1 8002cae: 807b strh r3, [r7, #2] 8002cb0: 4613 mov r3, r2 8002cb2: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8002cb4: 787b ldrb r3, [r7, #1] 8002cb6: 2b00 cmp r3, #0 8002cb8: d003 beq.n 8002cc2 { GPIOx->BSRR = GPIO_Pin; 8002cba: 887a ldrh r2, [r7, #2] 8002cbc: 687b ldr r3, [r7, #4] 8002cbe: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8002cc0: e003 b.n 8002cca GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8002cc2: 887b ldrh r3, [r7, #2] 8002cc4: 041a lsls r2, r3, #16 8002cc6: 687b ldr r3, [r7, #4] 8002cc8: 619a str r2, [r3, #24] } 8002cca: bf00 nop 8002ccc: 370c adds r7, #12 8002cce: 46bd mov sp, r7 8002cd0: f85d 7b04 ldr.w r7, [sp], #4 8002cd4: 4770 bx lr ... 08002cd8 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8002cd8: b580 push {r7, lr} 8002cda: b084 sub sp, #16 8002cdc: af00 add r7, sp, #0 8002cde: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8002ce0: 687b ldr r3, [r7, #4] 8002ce2: 2b00 cmp r3, #0 8002ce4: d101 bne.n 8002cea { return HAL_ERROR; 8002ce6: 2301 movs r3, #1 8002ce8: e12b b.n 8002f42 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8002cea: 687b ldr r3, [r7, #4] 8002cec: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8002cf0: b2db uxtb r3, r3 8002cf2: 2b00 cmp r3, #0 8002cf4: d106 bne.n 8002d04 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8002cf6: 687b ldr r3, [r7, #4] 8002cf8: 2200 movs r2, #0 8002cfa: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8002cfe: 6878 ldr r0, [r7, #4] 8002d00: f7fd fd4a bl 8000798 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8002d04: 687b ldr r3, [r7, #4] 8002d06: 2224 movs r2, #36 @ 0x24 8002d08: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8002d0c: 687b ldr r3, [r7, #4] 8002d0e: 681b ldr r3, [r3, #0] 8002d10: 681a ldr r2, [r3, #0] 8002d12: 687b ldr r3, [r7, #4] 8002d14: 681b ldr r3, [r3, #0] 8002d16: f022 0201 bic.w r2, r2, #1 8002d1a: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8002d1c: 687b ldr r3, [r7, #4] 8002d1e: 681b ldr r3, [r3, #0] 8002d20: 681a ldr r2, [r3, #0] 8002d22: 687b ldr r3, [r7, #4] 8002d24: 681b ldr r3, [r3, #0] 8002d26: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8002d2a: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 8002d2c: 687b ldr r3, [r7, #4] 8002d2e: 681b ldr r3, [r3, #0] 8002d30: 681a ldr r2, [r3, #0] 8002d32: 687b ldr r3, [r7, #4] 8002d34: 681b ldr r3, [r3, #0] 8002d36: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8002d3a: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 8002d3c: f001 fc88 bl 8004650 8002d40: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 8002d42: 687b ldr r3, [r7, #4] 8002d44: 685b ldr r3, [r3, #4] 8002d46: 4a81 ldr r2, [pc, #516] @ (8002f4c ) 8002d48: 4293 cmp r3, r2 8002d4a: d807 bhi.n 8002d5c 8002d4c: 68fb ldr r3, [r7, #12] 8002d4e: 4a80 ldr r2, [pc, #512] @ (8002f50 ) 8002d50: 4293 cmp r3, r2 8002d52: bf94 ite ls 8002d54: 2301 movls r3, #1 8002d56: 2300 movhi r3, #0 8002d58: b2db uxtb r3, r3 8002d5a: e006 b.n 8002d6a 8002d5c: 68fb ldr r3, [r7, #12] 8002d5e: 4a7d ldr r2, [pc, #500] @ (8002f54 ) 8002d60: 4293 cmp r3, r2 8002d62: bf94 ite ls 8002d64: 2301 movls r3, #1 8002d66: 2300 movhi r3, #0 8002d68: b2db uxtb r3, r3 8002d6a: 2b00 cmp r3, #0 8002d6c: d001 beq.n 8002d72 { return HAL_ERROR; 8002d6e: 2301 movs r3, #1 8002d70: e0e7 b.n 8002f42 } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 8002d72: 68fb ldr r3, [r7, #12] 8002d74: 4a78 ldr r2, [pc, #480] @ (8002f58 ) 8002d76: fba2 2303 umull r2, r3, r2, r3 8002d7a: 0c9b lsrs r3, r3, #18 8002d7c: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8002d7e: 687b ldr r3, [r7, #4] 8002d80: 681b ldr r3, [r3, #0] 8002d82: 685b ldr r3, [r3, #4] 8002d84: f023 013f bic.w r1, r3, #63 @ 0x3f 8002d88: 687b ldr r3, [r7, #4] 8002d8a: 681b ldr r3, [r3, #0] 8002d8c: 68ba ldr r2, [r7, #8] 8002d8e: 430a orrs r2, r1 8002d90: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 8002d92: 687b ldr r3, [r7, #4] 8002d94: 681b ldr r3, [r3, #0] 8002d96: 6a1b ldr r3, [r3, #32] 8002d98: f023 013f bic.w r1, r3, #63 @ 0x3f 8002d9c: 687b ldr r3, [r7, #4] 8002d9e: 685b ldr r3, [r3, #4] 8002da0: 4a6a ldr r2, [pc, #424] @ (8002f4c ) 8002da2: 4293 cmp r3, r2 8002da4: d802 bhi.n 8002dac 8002da6: 68bb ldr r3, [r7, #8] 8002da8: 3301 adds r3, #1 8002daa: e009 b.n 8002dc0 8002dac: 68bb ldr r3, [r7, #8] 8002dae: f44f 7296 mov.w r2, #300 @ 0x12c 8002db2: fb02 f303 mul.w r3, r2, r3 8002db6: 4a69 ldr r2, [pc, #420] @ (8002f5c ) 8002db8: fba2 2303 umull r2, r3, r2, r3 8002dbc: 099b lsrs r3, r3, #6 8002dbe: 3301 adds r3, #1 8002dc0: 687a ldr r2, [r7, #4] 8002dc2: 6812 ldr r2, [r2, #0] 8002dc4: 430b orrs r3, r1 8002dc6: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 8002dc8: 687b ldr r3, [r7, #4] 8002dca: 681b ldr r3, [r3, #0] 8002dcc: 69db ldr r3, [r3, #28] 8002dce: f423 424f bic.w r2, r3, #52992 @ 0xcf00 8002dd2: f022 02ff bic.w r2, r2, #255 @ 0xff 8002dd6: 687b ldr r3, [r7, #4] 8002dd8: 685b ldr r3, [r3, #4] 8002dda: 495c ldr r1, [pc, #368] @ (8002f4c ) 8002ddc: 428b cmp r3, r1 8002dde: d819 bhi.n 8002e14 8002de0: 68fb ldr r3, [r7, #12] 8002de2: 1e59 subs r1, r3, #1 8002de4: 687b ldr r3, [r7, #4] 8002de6: 685b ldr r3, [r3, #4] 8002de8: 005b lsls r3, r3, #1 8002dea: fbb1 f3f3 udiv r3, r1, r3 8002dee: 1c59 adds r1, r3, #1 8002df0: f640 73fc movw r3, #4092 @ 0xffc 8002df4: 400b ands r3, r1 8002df6: 2b00 cmp r3, #0 8002df8: d00a beq.n 8002e10 8002dfa: 68fb ldr r3, [r7, #12] 8002dfc: 1e59 subs r1, r3, #1 8002dfe: 687b ldr r3, [r7, #4] 8002e00: 685b ldr r3, [r3, #4] 8002e02: 005b lsls r3, r3, #1 8002e04: fbb1 f3f3 udiv r3, r1, r3 8002e08: 3301 adds r3, #1 8002e0a: f3c3 030b ubfx r3, r3, #0, #12 8002e0e: e051 b.n 8002eb4 8002e10: 2304 movs r3, #4 8002e12: e04f b.n 8002eb4 8002e14: 687b ldr r3, [r7, #4] 8002e16: 689b ldr r3, [r3, #8] 8002e18: 2b00 cmp r3, #0 8002e1a: d111 bne.n 8002e40 8002e1c: 68fb ldr r3, [r7, #12] 8002e1e: 1e58 subs r0, r3, #1 8002e20: 687b ldr r3, [r7, #4] 8002e22: 6859 ldr r1, [r3, #4] 8002e24: 460b mov r3, r1 8002e26: 005b lsls r3, r3, #1 8002e28: 440b add r3, r1 8002e2a: fbb0 f3f3 udiv r3, r0, r3 8002e2e: 3301 adds r3, #1 8002e30: f3c3 030b ubfx r3, r3, #0, #12 8002e34: 2b00 cmp r3, #0 8002e36: bf0c ite eq 8002e38: 2301 moveq r3, #1 8002e3a: 2300 movne r3, #0 8002e3c: b2db uxtb r3, r3 8002e3e: e012 b.n 8002e66 8002e40: 68fb ldr r3, [r7, #12] 8002e42: 1e58 subs r0, r3, #1 8002e44: 687b ldr r3, [r7, #4] 8002e46: 6859 ldr r1, [r3, #4] 8002e48: 460b mov r3, r1 8002e4a: 009b lsls r3, r3, #2 8002e4c: 440b add r3, r1 8002e4e: 0099 lsls r1, r3, #2 8002e50: 440b add r3, r1 8002e52: fbb0 f3f3 udiv r3, r0, r3 8002e56: 3301 adds r3, #1 8002e58: f3c3 030b ubfx r3, r3, #0, #12 8002e5c: 2b00 cmp r3, #0 8002e5e: bf0c ite eq 8002e60: 2301 moveq r3, #1 8002e62: 2300 movne r3, #0 8002e64: b2db uxtb r3, r3 8002e66: 2b00 cmp r3, #0 8002e68: d001 beq.n 8002e6e 8002e6a: 2301 movs r3, #1 8002e6c: e022 b.n 8002eb4 8002e6e: 687b ldr r3, [r7, #4] 8002e70: 689b ldr r3, [r3, #8] 8002e72: 2b00 cmp r3, #0 8002e74: d10e bne.n 8002e94 8002e76: 68fb ldr r3, [r7, #12] 8002e78: 1e58 subs r0, r3, #1 8002e7a: 687b ldr r3, [r7, #4] 8002e7c: 6859 ldr r1, [r3, #4] 8002e7e: 460b mov r3, r1 8002e80: 005b lsls r3, r3, #1 8002e82: 440b add r3, r1 8002e84: fbb0 f3f3 udiv r3, r0, r3 8002e88: 3301 adds r3, #1 8002e8a: f3c3 030b ubfx r3, r3, #0, #12 8002e8e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8002e92: e00f b.n 8002eb4 8002e94: 68fb ldr r3, [r7, #12] 8002e96: 1e58 subs r0, r3, #1 8002e98: 687b ldr r3, [r7, #4] 8002e9a: 6859 ldr r1, [r3, #4] 8002e9c: 460b mov r3, r1 8002e9e: 009b lsls r3, r3, #2 8002ea0: 440b add r3, r1 8002ea2: 0099 lsls r1, r3, #2 8002ea4: 440b add r3, r1 8002ea6: fbb0 f3f3 udiv r3, r0, r3 8002eaa: 3301 adds r3, #1 8002eac: f3c3 030b ubfx r3, r3, #0, #12 8002eb0: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8002eb4: 6879 ldr r1, [r7, #4] 8002eb6: 6809 ldr r1, [r1, #0] 8002eb8: 4313 orrs r3, r2 8002eba: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8002ebc: 687b ldr r3, [r7, #4] 8002ebe: 681b ldr r3, [r3, #0] 8002ec0: 681b ldr r3, [r3, #0] 8002ec2: f023 01c0 bic.w r1, r3, #192 @ 0xc0 8002ec6: 687b ldr r3, [r7, #4] 8002ec8: 69da ldr r2, [r3, #28] 8002eca: 687b ldr r3, [r7, #4] 8002ecc: 6a1b ldr r3, [r3, #32] 8002ece: 431a orrs r2, r3 8002ed0: 687b ldr r3, [r7, #4] 8002ed2: 681b ldr r3, [r3, #0] 8002ed4: 430a orrs r2, r1 8002ed6: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 8002ed8: 687b ldr r3, [r7, #4] 8002eda: 681b ldr r3, [r3, #0] 8002edc: 689b ldr r3, [r3, #8] 8002ede: f423 4303 bic.w r3, r3, #33536 @ 0x8300 8002ee2: f023 03ff bic.w r3, r3, #255 @ 0xff 8002ee6: 687a ldr r2, [r7, #4] 8002ee8: 6911 ldr r1, [r2, #16] 8002eea: 687a ldr r2, [r7, #4] 8002eec: 68d2 ldr r2, [r2, #12] 8002eee: 4311 orrs r1, r2 8002ef0: 687a ldr r2, [r7, #4] 8002ef2: 6812 ldr r2, [r2, #0] 8002ef4: 430b orrs r3, r1 8002ef6: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 8002ef8: 687b ldr r3, [r7, #4] 8002efa: 681b ldr r3, [r3, #0] 8002efc: 68db ldr r3, [r3, #12] 8002efe: f023 01ff bic.w r1, r3, #255 @ 0xff 8002f02: 687b ldr r3, [r7, #4] 8002f04: 695a ldr r2, [r3, #20] 8002f06: 687b ldr r3, [r7, #4] 8002f08: 699b ldr r3, [r3, #24] 8002f0a: 431a orrs r2, r3 8002f0c: 687b ldr r3, [r7, #4] 8002f0e: 681b ldr r3, [r3, #0] 8002f10: 430a orrs r2, r1 8002f12: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002f14: 687b ldr r3, [r7, #4] 8002f16: 681b ldr r3, [r3, #0] 8002f18: 681a ldr r2, [r3, #0] 8002f1a: 687b ldr r3, [r7, #4] 8002f1c: 681b ldr r3, [r3, #0] 8002f1e: f042 0201 orr.w r2, r2, #1 8002f22: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002f24: 687b ldr r3, [r7, #4] 8002f26: 2200 movs r2, #0 8002f28: 641a str r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_READY; 8002f2a: 687b ldr r3, [r7, #4] 8002f2c: 2220 movs r2, #32 8002f2e: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->PreviousState = I2C_STATE_NONE; 8002f32: 687b ldr r3, [r7, #4] 8002f34: 2200 movs r2, #0 8002f36: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8002f38: 687b ldr r3, [r7, #4] 8002f3a: 2200 movs r2, #0 8002f3c: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 8002f40: 2300 movs r3, #0 } 8002f42: 4618 mov r0, r3 8002f44: 3710 adds r7, #16 8002f46: 46bd mov sp, r7 8002f48: bd80 pop {r7, pc} 8002f4a: bf00 nop 8002f4c: 000186a0 .word 0x000186a0 8002f50: 001e847f .word 0x001e847f 8002f54: 003d08ff .word 0x003d08ff 8002f58: 431bde83 .word 0x431bde83 8002f5c: 10624dd3 .word 0x10624dd3 08002f60 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8002f60: b580 push {r7, lr} 8002f62: b086 sub sp, #24 8002f64: af02 add r7, sp, #8 8002f66: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx; #endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8002f68: 687b ldr r3, [r7, #4] 8002f6a: 2b00 cmp r3, #0 8002f6c: d101 bne.n 8002f72 { return HAL_ERROR; 8002f6e: 2301 movs r3, #1 8002f70: e108 b.n 8003184 /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); #if defined (USB_OTG_FS) USBx = hpcd->Instance; 8002f72: 687b ldr r3, [r7, #4] 8002f74: 681b ldr r3, [r3, #0] 8002f76: 60bb str r3, [r7, #8] #endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) 8002f78: 687b ldr r3, [r7, #4] 8002f7a: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495 8002f7e: b2db uxtb r3, r3 8002f80: 2b00 cmp r3, #0 8002f82: d106 bne.n 8002f92 { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 8002f84: 687b ldr r3, [r7, #4] 8002f86: 2200 movs r2, #0 8002f88: f883 2494 strb.w r2, [r3, #1172] @ 0x494 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8002f8c: 6878 ldr r0, [r7, #4] 8002f8e: f008 f855 bl 800b03c #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8002f92: 687b ldr r3, [r7, #4] 8002f94: 2203 movs r2, #3 8002f96: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ if (USBx == USB_OTG_FS) 8002f9a: 68bb ldr r3, [r7, #8] 8002f9c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002fa0: d102 bne.n 8002fa8 { hpcd->Init.dma_enable = 0U; 8002fa2: 687b ldr r3, [r7, #4] 8002fa4: 2200 movs r2, #0 8002fa6: 719a strb r2, [r3, #6] } #endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8002fa8: 687b ldr r3, [r7, #4] 8002faa: 681b ldr r3, [r3, #0] 8002fac: 4618 mov r0, r3 8002fae: f004 ff4a bl 8007e46 /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8002fb2: 687b ldr r3, [r7, #4] 8002fb4: 6818 ldr r0, [r3, #0] 8002fb6: 687b ldr r3, [r7, #4] 8002fb8: 7c1a ldrb r2, [r3, #16] 8002fba: f88d 2000 strb.w r2, [sp] 8002fbe: 3304 adds r3, #4 8002fc0: cb0e ldmia r3, {r1, r2, r3} 8002fc2: f004 fe29 bl 8007c18 8002fc6: 4603 mov r3, r0 8002fc8: 2b00 cmp r3, #0 8002fca: d005 beq.n 8002fd8 { hpcd->State = HAL_PCD_STATE_ERROR; 8002fcc: 687b ldr r3, [r7, #4] 8002fce: 2202 movs r2, #2 8002fd0: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002fd4: 2301 movs r3, #1 8002fd6: e0d5 b.n 8003184 } /* Force Device Mode */ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) 8002fd8: 687b ldr r3, [r7, #4] 8002fda: 681b ldr r3, [r3, #0] 8002fdc: 2100 movs r1, #0 8002fde: 4618 mov r0, r3 8002fe0: f004 ff42 bl 8007e68 8002fe4: 4603 mov r3, r0 8002fe6: 2b00 cmp r3, #0 8002fe8: d005 beq.n 8002ff6 { hpcd->State = HAL_PCD_STATE_ERROR; 8002fea: 687b ldr r3, [r7, #4] 8002fec: 2202 movs r2, #2 8002fee: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8002ff2: 2301 movs r3, #1 8002ff4: e0c6 b.n 8003184 } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002ff6: 2300 movs r3, #0 8002ff8: 73fb strb r3, [r7, #15] 8002ffa: e04a b.n 8003092 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8002ffc: 7bfa ldrb r2, [r7, #15] 8002ffe: 6879 ldr r1, [r7, #4] 8003000: 4613 mov r3, r2 8003002: 00db lsls r3, r3, #3 8003004: 4413 add r3, r2 8003006: 009b lsls r3, r3, #2 8003008: 440b add r3, r1 800300a: 3315 adds r3, #21 800300c: 2201 movs r2, #1 800300e: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8003010: 7bfa ldrb r2, [r7, #15] 8003012: 6879 ldr r1, [r7, #4] 8003014: 4613 mov r3, r2 8003016: 00db lsls r3, r3, #3 8003018: 4413 add r3, r2 800301a: 009b lsls r3, r3, #2 800301c: 440b add r3, r1 800301e: 3314 adds r3, #20 8003020: 7bfa ldrb r2, [r7, #15] 8003022: 701a strb r2, [r3, #0] hpcd->IN_ep[i].tx_fifo_num = i; 8003024: 7bfa ldrb r2, [r7, #15] 8003026: 7bfb ldrb r3, [r7, #15] 8003028: b298 uxth r0, r3 800302a: 6879 ldr r1, [r7, #4] 800302c: 4613 mov r3, r2 800302e: 00db lsls r3, r3, #3 8003030: 4413 add r3, r2 8003032: 009b lsls r3, r3, #2 8003034: 440b add r3, r1 8003036: 332e adds r3, #46 @ 0x2e 8003038: 4602 mov r2, r0 800303a: 801a strh r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 800303c: 7bfa ldrb r2, [r7, #15] 800303e: 6879 ldr r1, [r7, #4] 8003040: 4613 mov r3, r2 8003042: 00db lsls r3, r3, #3 8003044: 4413 add r3, r2 8003046: 009b lsls r3, r3, #2 8003048: 440b add r3, r1 800304a: 3318 adds r3, #24 800304c: 2200 movs r2, #0 800304e: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8003050: 7bfa ldrb r2, [r7, #15] 8003052: 6879 ldr r1, [r7, #4] 8003054: 4613 mov r3, r2 8003056: 00db lsls r3, r3, #3 8003058: 4413 add r3, r2 800305a: 009b lsls r3, r3, #2 800305c: 440b add r3, r1 800305e: 331c adds r3, #28 8003060: 2200 movs r2, #0 8003062: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 8003064: 7bfa ldrb r2, [r7, #15] 8003066: 6879 ldr r1, [r7, #4] 8003068: 4613 mov r3, r2 800306a: 00db lsls r3, r3, #3 800306c: 4413 add r3, r2 800306e: 009b lsls r3, r3, #2 8003070: 440b add r3, r1 8003072: 3320 adds r3, #32 8003074: 2200 movs r2, #0 8003076: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 8003078: 7bfa ldrb r2, [r7, #15] 800307a: 6879 ldr r1, [r7, #4] 800307c: 4613 mov r3, r2 800307e: 00db lsls r3, r3, #3 8003080: 4413 add r3, r2 8003082: 009b lsls r3, r3, #2 8003084: 440b add r3, r1 8003086: 3324 adds r3, #36 @ 0x24 8003088: 2200 movs r2, #0 800308a: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800308c: 7bfb ldrb r3, [r7, #15] 800308e: 3301 adds r3, #1 8003090: 73fb strb r3, [r7, #15] 8003092: 687b ldr r3, [r7, #4] 8003094: 791b ldrb r3, [r3, #4] 8003096: 7bfa ldrb r2, [r7, #15] 8003098: 429a cmp r2, r3 800309a: d3af bcc.n 8002ffc } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800309c: 2300 movs r3, #0 800309e: 73fb strb r3, [r7, #15] 80030a0: e044 b.n 800312c { hpcd->OUT_ep[i].is_in = 0U; 80030a2: 7bfa ldrb r2, [r7, #15] 80030a4: 6879 ldr r1, [r7, #4] 80030a6: 4613 mov r3, r2 80030a8: 00db lsls r3, r3, #3 80030aa: 4413 add r3, r2 80030ac: 009b lsls r3, r3, #2 80030ae: 440b add r3, r1 80030b0: f203 2355 addw r3, r3, #597 @ 0x255 80030b4: 2200 movs r2, #0 80030b6: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 80030b8: 7bfa ldrb r2, [r7, #15] 80030ba: 6879 ldr r1, [r7, #4] 80030bc: 4613 mov r3, r2 80030be: 00db lsls r3, r3, #3 80030c0: 4413 add r3, r2 80030c2: 009b lsls r3, r3, #2 80030c4: 440b add r3, r1 80030c6: f503 7315 add.w r3, r3, #596 @ 0x254 80030ca: 7bfa ldrb r2, [r7, #15] 80030cc: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 80030ce: 7bfa ldrb r2, [r7, #15] 80030d0: 6879 ldr r1, [r7, #4] 80030d2: 4613 mov r3, r2 80030d4: 00db lsls r3, r3, #3 80030d6: 4413 add r3, r2 80030d8: 009b lsls r3, r3, #2 80030da: 440b add r3, r1 80030dc: f503 7316 add.w r3, r3, #600 @ 0x258 80030e0: 2200 movs r2, #0 80030e2: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 80030e4: 7bfa ldrb r2, [r7, #15] 80030e6: 6879 ldr r1, [r7, #4] 80030e8: 4613 mov r3, r2 80030ea: 00db lsls r3, r3, #3 80030ec: 4413 add r3, r2 80030ee: 009b lsls r3, r3, #2 80030f0: 440b add r3, r1 80030f2: f503 7317 add.w r3, r3, #604 @ 0x25c 80030f6: 2200 movs r2, #0 80030f8: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 80030fa: 7bfa ldrb r2, [r7, #15] 80030fc: 6879 ldr r1, [r7, #4] 80030fe: 4613 mov r3, r2 8003100: 00db lsls r3, r3, #3 8003102: 4413 add r3, r2 8003104: 009b lsls r3, r3, #2 8003106: 440b add r3, r1 8003108: f503 7318 add.w r3, r3, #608 @ 0x260 800310c: 2200 movs r2, #0 800310e: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8003110: 7bfa ldrb r2, [r7, #15] 8003112: 6879 ldr r1, [r7, #4] 8003114: 4613 mov r3, r2 8003116: 00db lsls r3, r3, #3 8003118: 4413 add r3, r2 800311a: 009b lsls r3, r3, #2 800311c: 440b add r3, r1 800311e: f503 7319 add.w r3, r3, #612 @ 0x264 8003122: 2200 movs r2, #0 8003124: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8003126: 7bfb ldrb r3, [r7, #15] 8003128: 3301 adds r3, #1 800312a: 73fb strb r3, [r7, #15] 800312c: 687b ldr r3, [r7, #4] 800312e: 791b ldrb r3, [r3, #4] 8003130: 7bfa ldrb r2, [r7, #15] 8003132: 429a cmp r2, r3 8003134: d3b5 bcc.n 80030a2 } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8003136: 687b ldr r3, [r7, #4] 8003138: 6818 ldr r0, [r3, #0] 800313a: 687b ldr r3, [r7, #4] 800313c: 7c1a ldrb r2, [r3, #16] 800313e: f88d 2000 strb.w r2, [sp] 8003142: 3304 adds r3, #4 8003144: cb0e ldmia r3, {r1, r2, r3} 8003146: f004 fedb bl 8007f00 800314a: 4603 mov r3, r0 800314c: 2b00 cmp r3, #0 800314e: d005 beq.n 800315c { hpcd->State = HAL_PCD_STATE_ERROR; 8003150: 687b ldr r3, [r7, #4] 8003152: 2202 movs r2, #2 8003154: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8003158: 2301 movs r3, #1 800315a: e013 b.n 8003184 } hpcd->USB_Address = 0U; 800315c: 687b ldr r3, [r7, #4] 800315e: 2200 movs r2, #0 8003160: 745a strb r2, [r3, #17] hpcd->State = HAL_PCD_STATE_READY; 8003162: 687b ldr r3, [r7, #4] 8003164: 2201 movs r2, #1 8003166: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 800316a: 687b ldr r3, [r7, #4] 800316c: 7b1b ldrb r3, [r3, #12] 800316e: 2b01 cmp r3, #1 8003170: d102 bne.n 8003178 { (void)HAL_PCDEx_ActivateLPM(hpcd); 8003172: 6878 ldr r0, [r7, #4] 8003174: f001 f956 bl 8004424 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); 8003178: 687b ldr r3, [r7, #4] 800317a: 681b ldr r3, [r3, #0] 800317c: 4618 mov r0, r3 800317e: f005 ff18 bl 8008fb2 return HAL_OK; 8003182: 2300 movs r3, #0 } 8003184: 4618 mov r0, r3 8003186: 3710 adds r7, #16 8003188: 46bd mov sp, r7 800318a: bd80 pop {r7, pc} 0800318c : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 800318c: b580 push {r7, lr} 800318e: b084 sub sp, #16 8003190: af00 add r7, sp, #0 8003192: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003194: 687b ldr r3, [r7, #4] 8003196: 681b ldr r3, [r3, #0] 8003198: 60fb str r3, [r7, #12] __HAL_LOCK(hpcd); 800319a: 687b ldr r3, [r7, #4] 800319c: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 80031a0: 2b01 cmp r3, #1 80031a2: d101 bne.n 80031a8 80031a4: 2302 movs r3, #2 80031a6: e022 b.n 80031ee 80031a8: 687b ldr r3, [r7, #4] 80031aa: 2201 movs r2, #1 80031ac: f883 2494 strb.w r2, [r3, #1172] @ 0x494 if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 80031b0: 68fb ldr r3, [r7, #12] 80031b2: 68db ldr r3, [r3, #12] 80031b4: f003 0340 and.w r3, r3, #64 @ 0x40 80031b8: 2b00 cmp r3, #0 80031ba: d009 beq.n 80031d0 (hpcd->Init.battery_charging_enable == 1U)) 80031bc: 687b ldr r3, [r7, #4] 80031be: 7b5b ldrb r3, [r3, #13] if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 80031c0: 2b01 cmp r3, #1 80031c2: d105 bne.n 80031d0 { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 80031c4: 68fb ldr r3, [r7, #12] 80031c6: 6b9b ldr r3, [r3, #56] @ 0x38 80031c8: f443 3280 orr.w r2, r3, #65536 @ 0x10000 80031cc: 68fb ldr r3, [r7, #12] 80031ce: 639a str r2, [r3, #56] @ 0x38 } __HAL_PCD_ENABLE(hpcd); 80031d0: 687b ldr r3, [r7, #4] 80031d2: 681b ldr r3, [r3, #0] 80031d4: 4618 mov r0, r3 80031d6: f004 fe25 bl 8007e24 (void)USB_DevConnect(hpcd->Instance); 80031da: 687b ldr r3, [r7, #4] 80031dc: 681b ldr r3, [r3, #0] 80031de: 4618 mov r0, r3 80031e0: f005 fec6 bl 8008f70 __HAL_UNLOCK(hpcd); 80031e4: 687b ldr r3, [r7, #4] 80031e6: 2200 movs r2, #0 80031e8: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 80031ec: 2300 movs r3, #0 } 80031ee: 4618 mov r0, r3 80031f0: 3710 adds r7, #16 80031f2: 46bd mov sp, r7 80031f4: bd80 pop {r7, pc} 080031f6 : * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 80031f6: b590 push {r4, r7, lr} 80031f8: b08d sub sp, #52 @ 0x34 80031fa: af00 add r7, sp, #0 80031fc: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 80031fe: 687b ldr r3, [r7, #4] 8003200: 681b ldr r3, [r3, #0] 8003202: 623b str r3, [r7, #32] uint32_t USBx_BASE = (uint32_t)USBx; 8003204: 6a3b ldr r3, [r7, #32] 8003206: 61fb str r3, [r7, #28] uint32_t epnum; uint32_t fifoemptymsk; uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) 8003208: 687b ldr r3, [r7, #4] 800320a: 681b ldr r3, [r3, #0] 800320c: 4618 mov r0, r3 800320e: f005 ff84 bl 800911a 8003212: 4603 mov r3, r0 8003214: 2b00 cmp r3, #0 8003216: f040 84b9 bne.w 8003b8c { /* avoid spurious interrupt */ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 800321a: 687b ldr r3, [r7, #4] 800321c: 681b ldr r3, [r3, #0] 800321e: 4618 mov r0, r3 8003220: f005 fee8 bl 8008ff4 8003224: 4603 mov r3, r0 8003226: 2b00 cmp r3, #0 8003228: f000 84af beq.w 8003b8a { return; } /* store current frame number */ hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; 800322c: 69fb ldr r3, [r7, #28] 800322e: f503 6300 add.w r3, r3, #2048 @ 0x800 8003232: 689b ldr r3, [r3, #8] 8003234: 0a1b lsrs r3, r3, #8 8003236: f3c3 020d ubfx r2, r3, #0, #14 800323a: 687b ldr r3, [r7, #4] 800323c: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4 if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) 8003240: 687b ldr r3, [r7, #4] 8003242: 681b ldr r3, [r3, #0] 8003244: 4618 mov r0, r3 8003246: f005 fed5 bl 8008ff4 800324a: 4603 mov r3, r0 800324c: f003 0302 and.w r3, r3, #2 8003250: 2b02 cmp r3, #2 8003252: d107 bne.n 8003264 { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); 8003254: 687b ldr r3, [r7, #4] 8003256: 681b ldr r3, [r3, #0] 8003258: 695a ldr r2, [r3, #20] 800325a: 687b ldr r3, [r7, #4] 800325c: 681b ldr r3, [r3, #0] 800325e: f002 0202 and.w r2, r2, #2 8003262: 615a str r2, [r3, #20] } /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) 8003264: 687b ldr r3, [r7, #4] 8003266: 681b ldr r3, [r3, #0] 8003268: 4618 mov r0, r3 800326a: f005 fec3 bl 8008ff4 800326e: 4603 mov r3, r0 8003270: f003 0310 and.w r3, r3, #16 8003274: 2b10 cmp r3, #16 8003276: d161 bne.n 800333c { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8003278: 687b ldr r3, [r7, #4] 800327a: 681b ldr r3, [r3, #0] 800327c: 699a ldr r2, [r3, #24] 800327e: 687b ldr r3, [r7, #4] 8003280: 681b ldr r3, [r3, #0] 8003282: f022 0210 bic.w r2, r2, #16 8003286: 619a str r2, [r3, #24] RegVal = USBx->GRXSTSP; 8003288: 6a3b ldr r3, [r7, #32] 800328a: 6a1b ldr r3, [r3, #32] 800328c: 61bb str r3, [r7, #24] ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; 800328e: 69bb ldr r3, [r7, #24] 8003290: f003 020f and.w r2, r3, #15 8003294: 4613 mov r3, r2 8003296: 00db lsls r3, r3, #3 8003298: 4413 add r3, r2 800329a: 009b lsls r3, r3, #2 800329c: f503 7314 add.w r3, r3, #592 @ 0x250 80032a0: 687a ldr r2, [r7, #4] 80032a2: 4413 add r3, r2 80032a4: 3304 adds r3, #4 80032a6: 617b str r3, [r7, #20] if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) 80032a8: 69bb ldr r3, [r7, #24] 80032aa: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 80032ae: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 80032b2: d124 bne.n 80032fe { if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) 80032b4: 69ba ldr r2, [r7, #24] 80032b6: f647 73f0 movw r3, #32752 @ 0x7ff0 80032ba: 4013 ands r3, r2 80032bc: 2b00 cmp r3, #0 80032be: d035 beq.n 800332c { (void)USB_ReadPacket(USBx, ep->xfer_buff, 80032c0: 697b ldr r3, [r7, #20] 80032c2: 68d9 ldr r1, [r3, #12] (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); 80032c4: 69bb ldr r3, [r7, #24] 80032c6: 091b lsrs r3, r3, #4 80032c8: b29b uxth r3, r3 (void)USB_ReadPacket(USBx, ep->xfer_buff, 80032ca: f3c3 030a ubfx r3, r3, #0, #11 80032ce: b29b uxth r3, r3 80032d0: 461a mov r2, r3 80032d2: 6a38 ldr r0, [r7, #32] 80032d4: f005 fcfa bl 8008ccc ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 80032d8: 697b ldr r3, [r7, #20] 80032da: 68da ldr r2, [r3, #12] 80032dc: 69bb ldr r3, [r7, #24] 80032de: 091b lsrs r3, r3, #4 80032e0: f3c3 030a ubfx r3, r3, #0, #11 80032e4: 441a add r2, r3 80032e6: 697b ldr r3, [r7, #20] 80032e8: 60da str r2, [r3, #12] ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 80032ea: 697b ldr r3, [r7, #20] 80032ec: 695a ldr r2, [r3, #20] 80032ee: 69bb ldr r3, [r7, #24] 80032f0: 091b lsrs r3, r3, #4 80032f2: f3c3 030a ubfx r3, r3, #0, #11 80032f6: 441a add r2, r3 80032f8: 697b ldr r3, [r7, #20] 80032fa: 615a str r2, [r3, #20] 80032fc: e016 b.n 800332c } } else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) 80032fe: 69bb ldr r3, [r7, #24] 8003300: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8003304: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8003308: d110 bne.n 800332c { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); 800330a: 687b ldr r3, [r7, #4] 800330c: f203 439c addw r3, r3, #1180 @ 0x49c 8003310: 2208 movs r2, #8 8003312: 4619 mov r1, r3 8003314: 6a38 ldr r0, [r7, #32] 8003316: f005 fcd9 bl 8008ccc ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 800331a: 697b ldr r3, [r7, #20] 800331c: 695a ldr r2, [r3, #20] 800331e: 69bb ldr r3, [r7, #24] 8003320: 091b lsrs r3, r3, #4 8003322: f3c3 030a ubfx r3, r3, #0, #11 8003326: 441a add r2, r3 8003328: 697b ldr r3, [r7, #20] 800332a: 615a str r2, [r3, #20] else { /* ... */ } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 800332c: 687b ldr r3, [r7, #4] 800332e: 681b ldr r3, [r3, #0] 8003330: 699a ldr r2, [r3, #24] 8003332: 687b ldr r3, [r7, #4] 8003334: 681b ldr r3, [r3, #0] 8003336: f042 0210 orr.w r2, r2, #16 800333a: 619a str r2, [r3, #24] } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) 800333c: 687b ldr r3, [r7, #4] 800333e: 681b ldr r3, [r3, #0] 8003340: 4618 mov r0, r3 8003342: f005 fe57 bl 8008ff4 8003346: 4603 mov r3, r0 8003348: f403 2300 and.w r3, r3, #524288 @ 0x80000 800334c: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8003350: f040 80a7 bne.w 80034a2 { epnum = 0U; 8003354: 2300 movs r3, #0 8003356: 627b str r3, [r7, #36] @ 0x24 /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); 8003358: 687b ldr r3, [r7, #4] 800335a: 681b ldr r3, [r3, #0] 800335c: 4618 mov r0, r3 800335e: f005 fe5c bl 800901a 8003362: 62b8 str r0, [r7, #40] @ 0x28 while (ep_intr != 0U) 8003364: e099 b.n 800349a { if ((ep_intr & 0x1U) != 0U) 8003366: 6abb ldr r3, [r7, #40] @ 0x28 8003368: f003 0301 and.w r3, r3, #1 800336c: 2b00 cmp r3, #0 800336e: f000 808e beq.w 800348e { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8003372: 687b ldr r3, [r7, #4] 8003374: 681b ldr r3, [r3, #0] 8003376: 6a7a ldr r2, [r7, #36] @ 0x24 8003378: b2d2 uxtb r2, r2 800337a: 4611 mov r1, r2 800337c: 4618 mov r0, r3 800337e: f005 fe80 bl 8009082 8003382: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) 8003384: 693b ldr r3, [r7, #16] 8003386: f003 0301 and.w r3, r3, #1 800338a: 2b00 cmp r3, #0 800338c: d00c beq.n 80033a8 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); 800338e: 6a7b ldr r3, [r7, #36] @ 0x24 8003390: 015a lsls r2, r3, #5 8003392: 69fb ldr r3, [r7, #28] 8003394: 4413 add r3, r2 8003396: f503 6330 add.w r3, r3, #2816 @ 0xb00 800339a: 461a mov r2, r3 800339c: 2301 movs r3, #1 800339e: 6093 str r3, [r2, #8] (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); 80033a0: 6a79 ldr r1, [r7, #36] @ 0x24 80033a2: 6878 ldr r0, [r7, #4] 80033a4: f000 feb8 bl 8004118 } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) 80033a8: 693b ldr r3, [r7, #16] 80033aa: f003 0308 and.w r3, r3, #8 80033ae: 2b00 cmp r3, #0 80033b0: d00c beq.n 80033cc { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); 80033b2: 6a7b ldr r3, [r7, #36] @ 0x24 80033b4: 015a lsls r2, r3, #5 80033b6: 69fb ldr r3, [r7, #28] 80033b8: 4413 add r3, r2 80033ba: f503 6330 add.w r3, r3, #2816 @ 0xb00 80033be: 461a mov r2, r3 80033c0: 2308 movs r3, #8 80033c2: 6093 str r3, [r2, #8] /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); 80033c4: 6a79 ldr r1, [r7, #36] @ 0x24 80033c6: 6878 ldr r0, [r7, #4] 80033c8: f000 ff8e bl 80042e8 } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) 80033cc: 693b ldr r3, [r7, #16] 80033ce: f003 0310 and.w r3, r3, #16 80033d2: 2b00 cmp r3, #0 80033d4: d008 beq.n 80033e8 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); 80033d6: 6a7b ldr r3, [r7, #36] @ 0x24 80033d8: 015a lsls r2, r3, #5 80033da: 69fb ldr r3, [r7, #28] 80033dc: 4413 add r3, r2 80033de: f503 6330 add.w r3, r3, #2816 @ 0xb00 80033e2: 461a mov r2, r3 80033e4: 2310 movs r3, #16 80033e6: 6093 str r3, [r2, #8] } /* Clear OUT Endpoint disable interrupt */ if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) 80033e8: 693b ldr r3, [r7, #16] 80033ea: f003 0302 and.w r3, r3, #2 80033ee: 2b00 cmp r3, #0 80033f0: d030 beq.n 8003454 { if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) 80033f2: 6a3b ldr r3, [r7, #32] 80033f4: 695b ldr r3, [r3, #20] 80033f6: f003 0380 and.w r3, r3, #128 @ 0x80 80033fa: 2b80 cmp r3, #128 @ 0x80 80033fc: d109 bne.n 8003412 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; 80033fe: 69fb ldr r3, [r7, #28] 8003400: f503 6300 add.w r3, r3, #2048 @ 0x800 8003404: 685b ldr r3, [r3, #4] 8003406: 69fa ldr r2, [r7, #28] 8003408: f502 6200 add.w r2, r2, #2048 @ 0x800 800340c: f443 6380 orr.w r3, r3, #1024 @ 0x400 8003410: 6053 str r3, [r2, #4] } ep = &hpcd->OUT_ep[epnum]; 8003412: 6a7a ldr r2, [r7, #36] @ 0x24 8003414: 4613 mov r3, r2 8003416: 00db lsls r3, r3, #3 8003418: 4413 add r3, r2 800341a: 009b lsls r3, r3, #2 800341c: f503 7314 add.w r3, r3, #592 @ 0x250 8003420: 687a ldr r2, [r7, #4] 8003422: 4413 add r3, r2 8003424: 3304 adds r3, #4 8003426: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 8003428: 697b ldr r3, [r7, #20] 800342a: 78db ldrb r3, [r3, #3] 800342c: 2b01 cmp r3, #1 800342e: d108 bne.n 8003442 { ep->is_iso_incomplete = 0U; 8003430: 697b ldr r3, [r7, #20] 8003432: 2200 movs r2, #0 8003434: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); 8003436: 6a7b ldr r3, [r7, #36] @ 0x24 8003438: b2db uxtb r3, r3 800343a: 4619 mov r1, r3 800343c: 6878 ldr r0, [r7, #4] 800343e: f007 ff19 bl 800b274 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); 8003442: 6a7b ldr r3, [r7, #36] @ 0x24 8003444: 015a lsls r2, r3, #5 8003446: 69fb ldr r3, [r7, #28] 8003448: 4413 add r3, r2 800344a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800344e: 461a mov r2, r3 8003450: 2302 movs r3, #2 8003452: 6093 str r3, [r2, #8] } /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8003454: 693b ldr r3, [r7, #16] 8003456: f003 0320 and.w r3, r3, #32 800345a: 2b00 cmp r3, #0 800345c: d008 beq.n 8003470 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 800345e: 6a7b ldr r3, [r7, #36] @ 0x24 8003460: 015a lsls r2, r3, #5 8003462: 69fb ldr r3, [r7, #28] 8003464: 4413 add r3, r2 8003466: f503 6330 add.w r3, r3, #2816 @ 0xb00 800346a: 461a mov r2, r3 800346c: 2320 movs r3, #32 800346e: 6093 str r3, [r2, #8] } /* Clear OUT NAK interrupt */ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) 8003470: 693b ldr r3, [r7, #16] 8003472: f403 5300 and.w r3, r3, #8192 @ 0x2000 8003476: 2b00 cmp r3, #0 8003478: d009 beq.n 800348e { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); 800347a: 6a7b ldr r3, [r7, #36] @ 0x24 800347c: 015a lsls r2, r3, #5 800347e: 69fb ldr r3, [r7, #28] 8003480: 4413 add r3, r2 8003482: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003486: 461a mov r2, r3 8003488: f44f 5300 mov.w r3, #8192 @ 0x2000 800348c: 6093 str r3, [r2, #8] } } epnum++; 800348e: 6a7b ldr r3, [r7, #36] @ 0x24 8003490: 3301 adds r3, #1 8003492: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 8003494: 6abb ldr r3, [r7, #40] @ 0x28 8003496: 085b lsrs r3, r3, #1 8003498: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 800349a: 6abb ldr r3, [r7, #40] @ 0x28 800349c: 2b00 cmp r3, #0 800349e: f47f af62 bne.w 8003366 } } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) 80034a2: 687b ldr r3, [r7, #4] 80034a4: 681b ldr r3, [r3, #0] 80034a6: 4618 mov r0, r3 80034a8: f005 fda4 bl 8008ff4 80034ac: 4603 mov r3, r0 80034ae: f403 2380 and.w r3, r3, #262144 @ 0x40000 80034b2: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 80034b6: f040 80db bne.w 8003670 { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); 80034ba: 687b ldr r3, [r7, #4] 80034bc: 681b ldr r3, [r3, #0] 80034be: 4618 mov r0, r3 80034c0: f005 fdc5 bl 800904e 80034c4: 62b8 str r0, [r7, #40] @ 0x28 epnum = 0U; 80034c6: 2300 movs r3, #0 80034c8: 627b str r3, [r7, #36] @ 0x24 while (ep_intr != 0U) 80034ca: e0cd b.n 8003668 { if ((ep_intr & 0x1U) != 0U) /* In ITR */ 80034cc: 6abb ldr r3, [r7, #40] @ 0x28 80034ce: f003 0301 and.w r3, r3, #1 80034d2: 2b00 cmp r3, #0 80034d4: f000 80c2 beq.w 800365c { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); 80034d8: 687b ldr r3, [r7, #4] 80034da: 681b ldr r3, [r3, #0] 80034dc: 6a7a ldr r2, [r7, #36] @ 0x24 80034de: b2d2 uxtb r2, r2 80034e0: 4611 mov r1, r2 80034e2: 4618 mov r0, r3 80034e4: f005 fdeb bl 80090be 80034e8: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) 80034ea: 693b ldr r3, [r7, #16] 80034ec: f003 0301 and.w r3, r3, #1 80034f0: 2b00 cmp r3, #0 80034f2: d057 beq.n 80035a4 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 80034f4: 6a7b ldr r3, [r7, #36] @ 0x24 80034f6: f003 030f and.w r3, r3, #15 80034fa: 2201 movs r2, #1 80034fc: fa02 f303 lsl.w r3, r2, r3 8003500: 60fb str r3, [r7, #12] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8003502: 69fb ldr r3, [r7, #28] 8003504: f503 6300 add.w r3, r3, #2048 @ 0x800 8003508: 6b5a ldr r2, [r3, #52] @ 0x34 800350a: 68fb ldr r3, [r7, #12] 800350c: 43db mvns r3, r3 800350e: 69f9 ldr r1, [r7, #28] 8003510: f501 6100 add.w r1, r1, #2048 @ 0x800 8003514: 4013 ands r3, r2 8003516: 634b str r3, [r1, #52] @ 0x34 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); 8003518: 6a7b ldr r3, [r7, #36] @ 0x24 800351a: 015a lsls r2, r3, #5 800351c: 69fb ldr r3, [r7, #28] 800351e: 4413 add r3, r2 8003520: f503 6310 add.w r3, r3, #2304 @ 0x900 8003524: 461a mov r2, r3 8003526: 2301 movs r3, #1 8003528: 6093 str r3, [r2, #8] if (hpcd->Init.dma_enable == 1U) 800352a: 687b ldr r3, [r7, #4] 800352c: 799b ldrb r3, [r3, #6] 800352e: 2b01 cmp r3, #1 8003530: d132 bne.n 8003598 { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 8003532: 6879 ldr r1, [r7, #4] 8003534: 6a7a ldr r2, [r7, #36] @ 0x24 8003536: 4613 mov r3, r2 8003538: 00db lsls r3, r3, #3 800353a: 4413 add r3, r2 800353c: 009b lsls r3, r3, #2 800353e: 440b add r3, r1 8003540: 3320 adds r3, #32 8003542: 6819 ldr r1, [r3, #0] 8003544: 6878 ldr r0, [r7, #4] 8003546: 6a7a ldr r2, [r7, #36] @ 0x24 8003548: 4613 mov r3, r2 800354a: 00db lsls r3, r3, #3 800354c: 4413 add r3, r2 800354e: 009b lsls r3, r3, #2 8003550: 4403 add r3, r0 8003552: 331c adds r3, #28 8003554: 681b ldr r3, [r3, #0] 8003556: 4419 add r1, r3 8003558: 6878 ldr r0, [r7, #4] 800355a: 6a7a ldr r2, [r7, #36] @ 0x24 800355c: 4613 mov r3, r2 800355e: 00db lsls r3, r3, #3 8003560: 4413 add r3, r2 8003562: 009b lsls r3, r3, #2 8003564: 4403 add r3, r0 8003566: 3320 adds r3, #32 8003568: 6019 str r1, [r3, #0] /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) 800356a: 6a7b ldr r3, [r7, #36] @ 0x24 800356c: 2b00 cmp r3, #0 800356e: d113 bne.n 8003598 8003570: 6879 ldr r1, [r7, #4] 8003572: 6a7a ldr r2, [r7, #36] @ 0x24 8003574: 4613 mov r3, r2 8003576: 00db lsls r3, r3, #3 8003578: 4413 add r3, r2 800357a: 009b lsls r3, r3, #2 800357c: 440b add r3, r1 800357e: 3324 adds r3, #36 @ 0x24 8003580: 681b ldr r3, [r3, #0] 8003582: 2b00 cmp r3, #0 8003584: d108 bne.n 8003598 { /* prepare to rx more setup packets */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8003586: 687b ldr r3, [r7, #4] 8003588: 6818 ldr r0, [r3, #0] 800358a: 687b ldr r3, [r7, #4] 800358c: f203 439c addw r3, r3, #1180 @ 0x49c 8003590: 461a mov r2, r3 8003592: 2101 movs r1, #1 8003594: f005 fdf2 bl 800917c } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); 8003598: 6a7b ldr r3, [r7, #36] @ 0x24 800359a: b2db uxtb r3, r3 800359c: 4619 mov r1, r3 800359e: 6878 ldr r0, [r7, #4] 80035a0: f007 fde3 bl 800b16a #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) 80035a4: 693b ldr r3, [r7, #16] 80035a6: f003 0308 and.w r3, r3, #8 80035aa: 2b00 cmp r3, #0 80035ac: d008 beq.n 80035c0 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); 80035ae: 6a7b ldr r3, [r7, #36] @ 0x24 80035b0: 015a lsls r2, r3, #5 80035b2: 69fb ldr r3, [r7, #28] 80035b4: 4413 add r3, r2 80035b6: f503 6310 add.w r3, r3, #2304 @ 0x900 80035ba: 461a mov r2, r3 80035bc: 2308 movs r3, #8 80035be: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) 80035c0: 693b ldr r3, [r7, #16] 80035c2: f003 0310 and.w r3, r3, #16 80035c6: 2b00 cmp r3, #0 80035c8: d008 beq.n 80035dc { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); 80035ca: 6a7b ldr r3, [r7, #36] @ 0x24 80035cc: 015a lsls r2, r3, #5 80035ce: 69fb ldr r3, [r7, #28] 80035d0: 4413 add r3, r2 80035d2: f503 6310 add.w r3, r3, #2304 @ 0x900 80035d6: 461a mov r2, r3 80035d8: 2310 movs r3, #16 80035da: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) 80035dc: 693b ldr r3, [r7, #16] 80035de: f003 0340 and.w r3, r3, #64 @ 0x40 80035e2: 2b00 cmp r3, #0 80035e4: d008 beq.n 80035f8 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); 80035e6: 6a7b ldr r3, [r7, #36] @ 0x24 80035e8: 015a lsls r2, r3, #5 80035ea: 69fb ldr r3, [r7, #28] 80035ec: 4413 add r3, r2 80035ee: f503 6310 add.w r3, r3, #2304 @ 0x900 80035f2: 461a mov r2, r3 80035f4: 2340 movs r3, #64 @ 0x40 80035f6: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) 80035f8: 693b ldr r3, [r7, #16] 80035fa: f003 0302 and.w r3, r3, #2 80035fe: 2b00 cmp r3, #0 8003600: d023 beq.n 800364a { (void)USB_FlushTxFifo(USBx, epnum); 8003602: 6a79 ldr r1, [r7, #36] @ 0x24 8003604: 6a38 ldr r0, [r7, #32] 8003606: f004 fdd9 bl 80081bc ep = &hpcd->IN_ep[epnum]; 800360a: 6a7a ldr r2, [r7, #36] @ 0x24 800360c: 4613 mov r3, r2 800360e: 00db lsls r3, r3, #3 8003610: 4413 add r3, r2 8003612: 009b lsls r3, r3, #2 8003614: 3310 adds r3, #16 8003616: 687a ldr r2, [r7, #4] 8003618: 4413 add r3, r2 800361a: 3304 adds r3, #4 800361c: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 800361e: 697b ldr r3, [r7, #20] 8003620: 78db ldrb r3, [r3, #3] 8003622: 2b01 cmp r3, #1 8003624: d108 bne.n 8003638 { ep->is_iso_incomplete = 0U; 8003626: 697b ldr r3, [r7, #20] 8003628: 2200 movs r2, #0 800362a: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); 800362c: 6a7b ldr r3, [r7, #36] @ 0x24 800362e: b2db uxtb r3, r3 8003630: 4619 mov r1, r3 8003632: 6878 ldr r0, [r7, #4] 8003634: f007 fe30 bl 800b298 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); 8003638: 6a7b ldr r3, [r7, #36] @ 0x24 800363a: 015a lsls r2, r3, #5 800363c: 69fb ldr r3, [r7, #28] 800363e: 4413 add r3, r2 8003640: f503 6310 add.w r3, r3, #2304 @ 0x900 8003644: 461a mov r2, r3 8003646: 2302 movs r3, #2 8003648: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) 800364a: 693b ldr r3, [r7, #16] 800364c: f003 0380 and.w r3, r3, #128 @ 0x80 8003650: 2b00 cmp r3, #0 8003652: d003 beq.n 800365c { (void)PCD_WriteEmptyTxFifo(hpcd, epnum); 8003654: 6a79 ldr r1, [r7, #36] @ 0x24 8003656: 6878 ldr r0, [r7, #4] 8003658: f000 fcd2 bl 8004000 } } epnum++; 800365c: 6a7b ldr r3, [r7, #36] @ 0x24 800365e: 3301 adds r3, #1 8003660: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 8003662: 6abb ldr r3, [r7, #40] @ 0x28 8003664: 085b lsrs r3, r3, #1 8003666: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 8003668: 6abb ldr r3, [r7, #40] @ 0x28 800366a: 2b00 cmp r3, #0 800366c: f47f af2e bne.w 80034cc } } /* Handle Resume Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) 8003670: 687b ldr r3, [r7, #4] 8003672: 681b ldr r3, [r3, #0] 8003674: 4618 mov r0, r3 8003676: f005 fcbd bl 8008ff4 800367a: 4603 mov r3, r0 800367c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8003680: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8003684: d122 bne.n 80036cc { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 8003686: 69fb ldr r3, [r7, #28] 8003688: f503 6300 add.w r3, r3, #2048 @ 0x800 800368c: 685b ldr r3, [r3, #4] 800368e: 69fa ldr r2, [r7, #28] 8003690: f502 6200 add.w r2, r2, #2048 @ 0x800 8003694: f023 0301 bic.w r3, r3, #1 8003698: 6053 str r3, [r2, #4] if (hpcd->LPM_State == LPM_L1) 800369a: 687b ldr r3, [r7, #4] 800369c: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 80036a0: 2b01 cmp r3, #1 80036a2: d108 bne.n 80036b6 { hpcd->LPM_State = LPM_L0; 80036a4: 687b ldr r3, [r7, #4] 80036a6: 2200 movs r2, #0 80036a8: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 80036ac: 2100 movs r1, #0 80036ae: 6878 ldr r0, [r7, #4] 80036b0: f007 ff98 bl 800b5e4 80036b4: e002 b.n 80036bc else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 80036b6: 6878 ldr r0, [r7, #4] 80036b8: f007 fdce bl 800b258 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); 80036bc: 687b ldr r3, [r7, #4] 80036be: 681b ldr r3, [r3, #0] 80036c0: 695a ldr r2, [r3, #20] 80036c2: 687b ldr r3, [r7, #4] 80036c4: 681b ldr r3, [r3, #0] 80036c6: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000 80036ca: 615a str r2, [r3, #20] } /* Handle Suspend Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) 80036cc: 687b ldr r3, [r7, #4] 80036ce: 681b ldr r3, [r3, #0] 80036d0: 4618 mov r0, r3 80036d2: f005 fc8f bl 8008ff4 80036d6: 4603 mov r3, r0 80036d8: f403 6300 and.w r3, r3, #2048 @ 0x800 80036dc: f5b3 6f00 cmp.w r3, #2048 @ 0x800 80036e0: d112 bne.n 8003708 { if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 80036e2: 69fb ldr r3, [r7, #28] 80036e4: f503 6300 add.w r3, r3, #2048 @ 0x800 80036e8: 689b ldr r3, [r3, #8] 80036ea: f003 0301 and.w r3, r3, #1 80036ee: 2b01 cmp r3, #1 80036f0: d102 bne.n 80036f8 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 80036f2: 6878 ldr r0, [r7, #4] 80036f4: f007 fd8a bl 800b20c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); 80036f8: 687b ldr r3, [r7, #4] 80036fa: 681b ldr r3, [r3, #0] 80036fc: 695a ldr r2, [r3, #20] 80036fe: 687b ldr r3, [r7, #4] 8003700: 681b ldr r3, [r3, #0] 8003702: f402 6200 and.w r2, r2, #2048 @ 0x800 8003706: 615a str r2, [r3, #20] } #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) 8003708: 687b ldr r3, [r7, #4] 800370a: 681b ldr r3, [r3, #0] 800370c: 4618 mov r0, r3 800370e: f005 fc71 bl 8008ff4 8003712: 4603 mov r3, r0 8003714: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8003718: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800371c: d121 bne.n 8003762 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); 800371e: 687b ldr r3, [r7, #4] 8003720: 681b ldr r3, [r3, #0] 8003722: 695a ldr r2, [r3, #20] 8003724: 687b ldr r3, [r7, #4] 8003726: 681b ldr r3, [r3, #0] 8003728: f002 6200 and.w r2, r2, #134217728 @ 0x8000000 800372c: 615a str r2, [r3, #20] if (hpcd->LPM_State == LPM_L0) 800372e: 687b ldr r3, [r7, #4] 8003730: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 8003734: 2b00 cmp r3, #0 8003736: d111 bne.n 800375c { hpcd->LPM_State = LPM_L1; 8003738: 687b ldr r3, [r7, #4] 800373a: 2201 movs r2, #1 800373c: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; 8003740: 687b ldr r3, [r7, #4] 8003742: 681b ldr r3, [r3, #0] 8003744: 6d5b ldr r3, [r3, #84] @ 0x54 8003746: 089b lsrs r3, r3, #2 8003748: f003 020f and.w r2, r3, #15 800374c: 687b ldr r3, [r7, #4] 800374e: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 8003752: 2101 movs r1, #1 8003754: 6878 ldr r0, [r7, #4] 8003756: f007 ff45 bl 800b5e4 800375a: e002 b.n 8003762 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 800375c: 6878 ldr r0, [r7, #4] 800375e: f007 fd55 bl 800b20c } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) 8003762: 687b ldr r3, [r7, #4] 8003764: 681b ldr r3, [r3, #0] 8003766: 4618 mov r0, r3 8003768: f005 fc44 bl 8008ff4 800376c: 4603 mov r3, r0 800376e: f403 5380 and.w r3, r3, #4096 @ 0x1000 8003772: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8003776: f040 80b7 bne.w 80038e8 { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 800377a: 69fb ldr r3, [r7, #28] 800377c: f503 6300 add.w r3, r3, #2048 @ 0x800 8003780: 685b ldr r3, [r3, #4] 8003782: 69fa ldr r2, [r7, #28] 8003784: f502 6200 add.w r2, r2, #2048 @ 0x800 8003788: f023 0301 bic.w r3, r3, #1 800378c: 6053 str r3, [r2, #4] (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); 800378e: 687b ldr r3, [r7, #4] 8003790: 681b ldr r3, [r3, #0] 8003792: 2110 movs r1, #16 8003794: 4618 mov r0, r3 8003796: f004 fd11 bl 80081bc for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800379a: 2300 movs r3, #0 800379c: 62fb str r3, [r7, #44] @ 0x2c 800379e: e046 b.n 800382e { USBx_INEP(i)->DIEPINT = 0xFB7FU; 80037a0: 6afb ldr r3, [r7, #44] @ 0x2c 80037a2: 015a lsls r2, r3, #5 80037a4: 69fb ldr r3, [r7, #28] 80037a6: 4413 add r3, r2 80037a8: f503 6310 add.w r3, r3, #2304 @ 0x900 80037ac: 461a mov r2, r3 80037ae: f64f 337f movw r3, #64383 @ 0xfb7f 80037b2: 6093 str r3, [r2, #8] USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 80037b4: 6afb ldr r3, [r7, #44] @ 0x2c 80037b6: 015a lsls r2, r3, #5 80037b8: 69fb ldr r3, [r7, #28] 80037ba: 4413 add r3, r2 80037bc: f503 6310 add.w r3, r3, #2304 @ 0x900 80037c0: 681b ldr r3, [r3, #0] 80037c2: 6afa ldr r2, [r7, #44] @ 0x2c 80037c4: 0151 lsls r1, r2, #5 80037c6: 69fa ldr r2, [r7, #28] 80037c8: 440a add r2, r1 80037ca: f502 6210 add.w r2, r2, #2304 @ 0x900 80037ce: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 80037d2: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 80037d4: 6afb ldr r3, [r7, #44] @ 0x2c 80037d6: 015a lsls r2, r3, #5 80037d8: 69fb ldr r3, [r7, #28] 80037da: 4413 add r3, r2 80037dc: f503 6330 add.w r3, r3, #2816 @ 0xb00 80037e0: 461a mov r2, r3 80037e2: f64f 337f movw r3, #64383 @ 0xfb7f 80037e6: 6093 str r3, [r2, #8] USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 80037e8: 6afb ldr r3, [r7, #44] @ 0x2c 80037ea: 015a lsls r2, r3, #5 80037ec: 69fb ldr r3, [r7, #28] 80037ee: 4413 add r3, r2 80037f0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80037f4: 681b ldr r3, [r3, #0] 80037f6: 6afa ldr r2, [r7, #44] @ 0x2c 80037f8: 0151 lsls r1, r2, #5 80037fa: 69fa ldr r2, [r7, #28] 80037fc: 440a add r2, r1 80037fe: f502 6230 add.w r2, r2, #2816 @ 0xb00 8003802: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8003806: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 8003808: 6afb ldr r3, [r7, #44] @ 0x2c 800380a: 015a lsls r2, r3, #5 800380c: 69fb ldr r3, [r7, #28] 800380e: 4413 add r3, r2 8003810: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003814: 681b ldr r3, [r3, #0] 8003816: 6afa ldr r2, [r7, #44] @ 0x2c 8003818: 0151 lsls r1, r2, #5 800381a: 69fa ldr r2, [r7, #28] 800381c: 440a add r2, r1 800381e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8003822: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8003826: 6013 str r3, [r2, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8003828: 6afb ldr r3, [r7, #44] @ 0x2c 800382a: 3301 adds r3, #1 800382c: 62fb str r3, [r7, #44] @ 0x2c 800382e: 687b ldr r3, [r7, #4] 8003830: 791b ldrb r3, [r3, #4] 8003832: 461a mov r2, r3 8003834: 6afb ldr r3, [r7, #44] @ 0x2c 8003836: 4293 cmp r3, r2 8003838: d3b2 bcc.n 80037a0 } USBx_DEVICE->DAINTMSK |= 0x10001U; 800383a: 69fb ldr r3, [r7, #28] 800383c: f503 6300 add.w r3, r3, #2048 @ 0x800 8003840: 69db ldr r3, [r3, #28] 8003842: 69fa ldr r2, [r7, #28] 8003844: f502 6200 add.w r2, r2, #2048 @ 0x800 8003848: f043 1301 orr.w r3, r3, #65537 @ 0x10001 800384c: 61d3 str r3, [r2, #28] if (hpcd->Init.use_dedicated_ep1 != 0U) 800384e: 687b ldr r3, [r7, #4] 8003850: 7bdb ldrb r3, [r3, #15] 8003852: 2b00 cmp r3, #0 8003854: d016 beq.n 8003884 { USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | 8003856: 69fb ldr r3, [r7, #28] 8003858: f503 6300 add.w r3, r3, #2048 @ 0x800 800385c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8003860: 69fa ldr r2, [r7, #28] 8003862: f502 6200 add.w r2, r2, #2048 @ 0x800 8003866: f043 030b orr.w r3, r3, #11 800386a: f8c2 3084 str.w r3, [r2, #132] @ 0x84 USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM; USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | 800386e: 69fb ldr r3, [r7, #28] 8003870: f503 6300 add.w r3, r3, #2048 @ 0x800 8003874: 6c5b ldr r3, [r3, #68] @ 0x44 8003876: 69fa ldr r2, [r7, #28] 8003878: f502 6200 add.w r2, r2, #2048 @ 0x800 800387c: f043 030b orr.w r3, r3, #11 8003880: 6453 str r3, [r2, #68] @ 0x44 8003882: e015 b.n 80038b0 USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } else { USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | 8003884: 69fb ldr r3, [r7, #28] 8003886: f503 6300 add.w r3, r3, #2048 @ 0x800 800388a: 695b ldr r3, [r3, #20] 800388c: 69fa ldr r2, [r7, #28] 800388e: f502 6200 add.w r2, r2, #2048 @ 0x800 8003892: f443 5300 orr.w r3, r3, #8192 @ 0x2000 8003896: f043 032b orr.w r3, r3, #43 @ 0x2b 800389a: 6153 str r3, [r2, #20] USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM | USB_OTG_DOEPMSK_NAKM; USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | 800389c: 69fb ldr r3, [r7, #28] 800389e: f503 6300 add.w r3, r3, #2048 @ 0x800 80038a2: 691b ldr r3, [r3, #16] 80038a4: 69fa ldr r2, [r7, #28] 80038a6: f502 6200 add.w r2, r2, #2048 @ 0x800 80038aa: f043 030b orr.w r3, r3, #11 80038ae: 6113 str r3, [r2, #16] USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; 80038b0: 69fb ldr r3, [r7, #28] 80038b2: f503 6300 add.w r3, r3, #2048 @ 0x800 80038b6: 681b ldr r3, [r3, #0] 80038b8: 69fa ldr r2, [r7, #28] 80038ba: f502 6200 add.w r2, r2, #2048 @ 0x800 80038be: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 80038c2: 6013 str r3, [r2, #0] /* setup EP0 to receive SETUP packets */ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 80038c4: 687b ldr r3, [r7, #4] 80038c6: 6818 ldr r0, [r3, #0] 80038c8: 687b ldr r3, [r7, #4] 80038ca: 7999 ldrb r1, [r3, #6] (uint8_t *)hpcd->Setup); 80038cc: 687b ldr r3, [r7, #4] 80038ce: f203 439c addw r3, r3, #1180 @ 0x49c (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 80038d2: 461a mov r2, r3 80038d4: f005 fc52 bl 800917c __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); 80038d8: 687b ldr r3, [r7, #4] 80038da: 681b ldr r3, [r3, #0] 80038dc: 695a ldr r2, [r3, #20] 80038de: 687b ldr r3, [r7, #4] 80038e0: 681b ldr r3, [r3, #0] 80038e2: f402 5280 and.w r2, r2, #4096 @ 0x1000 80038e6: 615a str r2, [r3, #20] } /* Handle Enumeration done Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) 80038e8: 687b ldr r3, [r7, #4] 80038ea: 681b ldr r3, [r3, #0] 80038ec: 4618 mov r0, r3 80038ee: f005 fb81 bl 8008ff4 80038f2: 4603 mov r3, r0 80038f4: f403 5300 and.w r3, r3, #8192 @ 0x2000 80038f8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80038fc: d123 bne.n 8003946 { (void)USB_ActivateSetup(hpcd->Instance); 80038fe: 687b ldr r3, [r7, #4] 8003900: 681b ldr r3, [r3, #0] 8003902: 4618 mov r0, r3 8003904: f005 fc17 bl 8009136 hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); 8003908: 687b ldr r3, [r7, #4] 800390a: 681b ldr r3, [r3, #0] 800390c: 4618 mov r0, r3 800390e: f004 fcce bl 80082ae 8003912: 4603 mov r3, r0 8003914: 461a mov r2, r3 8003916: 687b ldr r3, [r7, #4] 8003918: 71da strb r2, [r3, #7] /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, 800391a: 687b ldr r3, [r7, #4] 800391c: 681c ldr r4, [r3, #0] 800391e: f000 fe8b bl 8004638 8003922: 4601 mov r1, r0 HAL_RCC_GetHCLKFreq(), (uint8_t)hpcd->Init.speed); 8003924: 687b ldr r3, [r7, #4] 8003926: 79db ldrb r3, [r3, #7] (void)USB_SetTurnaroundTime(hpcd->Instance, 8003928: 461a mov r2, r3 800392a: 4620 mov r0, r4 800392c: f004 f9d8 bl 8007ce0 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 8003930: 6878 ldr r0, [r7, #4] 8003932: f007 fc42 bl 800b1ba #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); 8003936: 687b ldr r3, [r7, #4] 8003938: 681b ldr r3, [r3, #0] 800393a: 695a ldr r2, [r3, #20] 800393c: 687b ldr r3, [r7, #4] 800393e: 681b ldr r3, [r3, #0] 8003940: f402 5200 and.w r2, r2, #8192 @ 0x2000 8003944: 615a str r2, [r3, #20] } /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) 8003946: 687b ldr r3, [r7, #4] 8003948: 681b ldr r3, [r3, #0] 800394a: 4618 mov r0, r3 800394c: f005 fb52 bl 8008ff4 8003950: 4603 mov r3, r0 8003952: f003 0308 and.w r3, r3, #8 8003956: 2b08 cmp r3, #8 8003958: d10a bne.n 8003970 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 800395a: 6878 ldr r0, [r7, #4] 800395c: f007 fc1f bl 800b19e #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); 8003960: 687b ldr r3, [r7, #4] 8003962: 681b ldr r3, [r3, #0] 8003964: 695a ldr r2, [r3, #20] 8003966: 687b ldr r3, [r7, #4] 8003968: 681b ldr r3, [r3, #0] 800396a: f002 0208 and.w r2, r2, #8 800396e: 615a str r2, [r3, #20] } /* Handle Global OUT NAK effective Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) 8003970: 687b ldr r3, [r7, #4] 8003972: 681b ldr r3, [r3, #0] 8003974: 4618 mov r0, r3 8003976: f005 fb3d bl 8008ff4 800397a: 4603 mov r3, r0 800397c: f003 0380 and.w r3, r3, #128 @ 0x80 8003980: 2b80 cmp r3, #128 @ 0x80 8003982: d123 bne.n 80039cc { USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; 8003984: 6a3b ldr r3, [r7, #32] 8003986: 699b ldr r3, [r3, #24] 8003988: f023 0280 bic.w r2, r3, #128 @ 0x80 800398c: 6a3b ldr r3, [r7, #32] 800398e: 619a str r2, [r3, #24] for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003990: 2301 movs r3, #1 8003992: 627b str r3, [r7, #36] @ 0x24 8003994: e014 b.n 80039c0 { if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) 8003996: 6879 ldr r1, [r7, #4] 8003998: 6a7a ldr r2, [r7, #36] @ 0x24 800399a: 4613 mov r3, r2 800399c: 00db lsls r3, r3, #3 800399e: 4413 add r3, r2 80039a0: 009b lsls r3, r3, #2 80039a2: 440b add r3, r1 80039a4: f203 2357 addw r3, r3, #599 @ 0x257 80039a8: 781b ldrb r3, [r3, #0] 80039aa: 2b01 cmp r3, #1 80039ac: d105 bne.n 80039ba { /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); 80039ae: 6a7b ldr r3, [r7, #36] @ 0x24 80039b0: b2db uxtb r3, r3 80039b2: 4619 mov r1, r3 80039b4: 6878 ldr r0, [r7, #4] 80039b6: f000 faf2 bl 8003f9e for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80039ba: 6a7b ldr r3, [r7, #36] @ 0x24 80039bc: 3301 adds r3, #1 80039be: 627b str r3, [r7, #36] @ 0x24 80039c0: 687b ldr r3, [r7, #4] 80039c2: 791b ldrb r3, [r3, #4] 80039c4: 461a mov r2, r3 80039c6: 6a7b ldr r3, [r7, #36] @ 0x24 80039c8: 4293 cmp r3, r2 80039ca: d3e4 bcc.n 8003996 } } } /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) 80039cc: 687b ldr r3, [r7, #4] 80039ce: 681b ldr r3, [r3, #0] 80039d0: 4618 mov r0, r3 80039d2: f005 fb0f bl 8008ff4 80039d6: 4603 mov r3, r0 80039d8: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80039dc: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80039e0: d13c bne.n 8003a5c { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 80039e2: 2301 movs r3, #1 80039e4: 627b str r3, [r7, #36] @ 0x24 80039e6: e02b b.n 8003a40 { RegVal = USBx_INEP(epnum)->DIEPCTL; 80039e8: 6a7b ldr r3, [r7, #36] @ 0x24 80039ea: 015a lsls r2, r3, #5 80039ec: 69fb ldr r3, [r7, #28] 80039ee: 4413 add r3, r2 80039f0: f503 6310 add.w r3, r3, #2304 @ 0x900 80039f4: 681b ldr r3, [r3, #0] 80039f6: 61bb str r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 80039f8: 6879 ldr r1, [r7, #4] 80039fa: 6a7a ldr r2, [r7, #36] @ 0x24 80039fc: 4613 mov r3, r2 80039fe: 00db lsls r3, r3, #3 8003a00: 4413 add r3, r2 8003a02: 009b lsls r3, r3, #2 8003a04: 440b add r3, r1 8003a06: 3318 adds r3, #24 8003a08: 781b ldrb r3, [r3, #0] 8003a0a: 2b01 cmp r3, #1 8003a0c: d115 bne.n 8003a3a ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) 8003a0e: 69bb ldr r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 8003a10: 2b00 cmp r3, #0 8003a12: da12 bge.n 8003a3a { hpcd->IN_ep[epnum].is_iso_incomplete = 1U; 8003a14: 6879 ldr r1, [r7, #4] 8003a16: 6a7a ldr r2, [r7, #36] @ 0x24 8003a18: 4613 mov r3, r2 8003a1a: 00db lsls r3, r3, #3 8003a1c: 4413 add r3, r2 8003a1e: 009b lsls r3, r3, #2 8003a20: 440b add r3, r1 8003a22: 3317 adds r3, #23 8003a24: 2201 movs r2, #1 8003a26: 701a strb r2, [r3, #0] /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); 8003a28: 6a7b ldr r3, [r7, #36] @ 0x24 8003a2a: b2db uxtb r3, r3 8003a2c: f063 037f orn r3, r3, #127 @ 0x7f 8003a30: b2db uxtb r3, r3 8003a32: 4619 mov r1, r3 8003a34: 6878 ldr r0, [r7, #4] 8003a36: f000 fab2 bl 8003f9e for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003a3a: 6a7b ldr r3, [r7, #36] @ 0x24 8003a3c: 3301 adds r3, #1 8003a3e: 627b str r3, [r7, #36] @ 0x24 8003a40: 687b ldr r3, [r7, #4] 8003a42: 791b ldrb r3, [r3, #4] 8003a44: 461a mov r2, r3 8003a46: 6a7b ldr r3, [r7, #36] @ 0x24 8003a48: 4293 cmp r3, r2 8003a4a: d3cd bcc.n 80039e8 } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); 8003a4c: 687b ldr r3, [r7, #4] 8003a4e: 681b ldr r3, [r3, #0] 8003a50: 695a ldr r2, [r3, #20] 8003a52: 687b ldr r3, [r7, #4] 8003a54: 681b ldr r3, [r3, #0] 8003a56: f402 1280 and.w r2, r2, #1048576 @ 0x100000 8003a5a: 615a str r2, [r3, #20] } /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 8003a5c: 687b ldr r3, [r7, #4] 8003a5e: 681b ldr r3, [r3, #0] 8003a60: 4618 mov r0, r3 8003a62: f005 fac7 bl 8008ff4 8003a66: 4603 mov r3, r0 8003a68: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8003a6c: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8003a70: d156 bne.n 8003b20 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003a72: 2301 movs r3, #1 8003a74: 627b str r3, [r7, #36] @ 0x24 8003a76: e045 b.n 8003b04 { RegVal = USBx_OUTEP(epnum)->DOEPCTL; 8003a78: 6a7b ldr r3, [r7, #36] @ 0x24 8003a7a: 015a lsls r2, r3, #5 8003a7c: 69fb ldr r3, [r7, #28] 8003a7e: 4413 add r3, r2 8003a80: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003a84: 681b ldr r3, [r3, #0] 8003a86: 61bb str r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 8003a88: 6879 ldr r1, [r7, #4] 8003a8a: 6a7a ldr r2, [r7, #36] @ 0x24 8003a8c: 4613 mov r3, r2 8003a8e: 00db lsls r3, r3, #3 8003a90: 4413 add r3, r2 8003a92: 009b lsls r3, r3, #2 8003a94: 440b add r3, r1 8003a96: f503 7316 add.w r3, r3, #600 @ 0x258 8003a9a: 781b ldrb r3, [r3, #0] 8003a9c: 2b01 cmp r3, #1 8003a9e: d12e bne.n 8003afe ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 8003aa0: 69bb ldr r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 8003aa2: 2b00 cmp r3, #0 8003aa4: da2b bge.n 8003afe (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) 8003aa6: 69bb ldr r3, [r7, #24] 8003aa8: 0c1a lsrs r2, r3, #16 8003aaa: 687b ldr r3, [r7, #4] 8003aac: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4 8003ab0: 4053 eors r3, r2 8003ab2: f003 0301 and.w r3, r3, #1 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 8003ab6: 2b00 cmp r3, #0 8003ab8: d121 bne.n 8003afe { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; 8003aba: 6879 ldr r1, [r7, #4] 8003abc: 6a7a ldr r2, [r7, #36] @ 0x24 8003abe: 4613 mov r3, r2 8003ac0: 00db lsls r3, r3, #3 8003ac2: 4413 add r3, r2 8003ac4: 009b lsls r3, r3, #2 8003ac6: 440b add r3, r1 8003ac8: f203 2357 addw r3, r3, #599 @ 0x257 8003acc: 2201 movs r2, #1 8003ace: 701a strb r2, [r3, #0] USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; 8003ad0: 6a3b ldr r3, [r7, #32] 8003ad2: 699b ldr r3, [r3, #24] 8003ad4: f043 0280 orr.w r2, r3, #128 @ 0x80 8003ad8: 6a3b ldr r3, [r7, #32] 8003ada: 619a str r2, [r3, #24] if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) 8003adc: 6a3b ldr r3, [r7, #32] 8003ade: 695b ldr r3, [r3, #20] 8003ae0: f003 0380 and.w r3, r3, #128 @ 0x80 8003ae4: 2b00 cmp r3, #0 8003ae6: d10a bne.n 8003afe { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; 8003ae8: 69fb ldr r3, [r7, #28] 8003aea: f503 6300 add.w r3, r3, #2048 @ 0x800 8003aee: 685b ldr r3, [r3, #4] 8003af0: 69fa ldr r2, [r7, #28] 8003af2: f502 6200 add.w r2, r2, #2048 @ 0x800 8003af6: f443 7300 orr.w r3, r3, #512 @ 0x200 8003afa: 6053 str r3, [r2, #4] break; 8003afc: e008 b.n 8003b10 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003afe: 6a7b ldr r3, [r7, #36] @ 0x24 8003b00: 3301 adds r3, #1 8003b02: 627b str r3, [r7, #36] @ 0x24 8003b04: 687b ldr r3, [r7, #4] 8003b06: 791b ldrb r3, [r3, #4] 8003b08: 461a mov r2, r3 8003b0a: 6a7b ldr r3, [r7, #36] @ 0x24 8003b0c: 4293 cmp r3, r2 8003b0e: d3b3 bcc.n 8003a78 } } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 8003b10: 687b ldr r3, [r7, #4] 8003b12: 681b ldr r3, [r3, #0] 8003b14: 695a ldr r2, [r3, #20] 8003b16: 687b ldr r3, [r7, #4] 8003b18: 681b ldr r3, [r3, #0] 8003b1a: f402 1200 and.w r2, r2, #2097152 @ 0x200000 8003b1e: 615a str r2, [r3, #20] } /* Handle Connection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) 8003b20: 687b ldr r3, [r7, #4] 8003b22: 681b ldr r3, [r3, #0] 8003b24: 4618 mov r0, r3 8003b26: f005 fa65 bl 8008ff4 8003b2a: 4603 mov r3, r0 8003b2c: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8003b30: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8003b34: d10a bne.n 8003b4c { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ConnectCallback(hpcd); #else HAL_PCD_ConnectCallback(hpcd); 8003b36: 6878 ldr r0, [r7, #4] 8003b38: f007 fbc0 bl 800b2bc #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); 8003b3c: 687b ldr r3, [r7, #4] 8003b3e: 681b ldr r3, [r3, #0] 8003b40: 695a ldr r2, [r3, #20] 8003b42: 687b ldr r3, [r7, #4] 8003b44: 681b ldr r3, [r3, #0] 8003b46: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 8003b4a: 615a str r2, [r3, #20] } /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) 8003b4c: 687b ldr r3, [r7, #4] 8003b4e: 681b ldr r3, [r3, #0] 8003b50: 4618 mov r0, r3 8003b52: f005 fa4f bl 8008ff4 8003b56: 4603 mov r3, r0 8003b58: f003 0304 and.w r3, r3, #4 8003b5c: 2b04 cmp r3, #4 8003b5e: d115 bne.n 8003b8c { RegVal = hpcd->Instance->GOTGINT; 8003b60: 687b ldr r3, [r7, #4] 8003b62: 681b ldr r3, [r3, #0] 8003b64: 685b ldr r3, [r3, #4] 8003b66: 61bb str r3, [r7, #24] if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) 8003b68: 69bb ldr r3, [r7, #24] 8003b6a: f003 0304 and.w r3, r3, #4 8003b6e: 2b00 cmp r3, #0 8003b70: d002 beq.n 8003b78 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); #else HAL_PCD_DisconnectCallback(hpcd); 8003b72: 6878 ldr r0, [r7, #4] 8003b74: f007 fbb0 bl 800b2d8 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= RegVal; 8003b78: 687b ldr r3, [r7, #4] 8003b7a: 681b ldr r3, [r3, #0] 8003b7c: 6859 ldr r1, [r3, #4] 8003b7e: 687b ldr r3, [r7, #4] 8003b80: 681b ldr r3, [r3, #0] 8003b82: 69ba ldr r2, [r7, #24] 8003b84: 430a orrs r2, r1 8003b86: 605a str r2, [r3, #4] 8003b88: e000 b.n 8003b8c return; 8003b8a: bf00 nop } } } 8003b8c: 3734 adds r7, #52 @ 0x34 8003b8e: 46bd mov sp, r7 8003b90: bd90 pop {r4, r7, pc} 08003b92 : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 8003b92: b580 push {r7, lr} 8003b94: b082 sub sp, #8 8003b96: af00 add r7, sp, #0 8003b98: 6078 str r0, [r7, #4] 8003b9a: 460b mov r3, r1 8003b9c: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 8003b9e: 687b ldr r3, [r7, #4] 8003ba0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003ba4: 2b01 cmp r3, #1 8003ba6: d101 bne.n 8003bac 8003ba8: 2302 movs r3, #2 8003baa: e012 b.n 8003bd2 8003bac: 687b ldr r3, [r7, #4] 8003bae: 2201 movs r2, #1 8003bb0: f883 2494 strb.w r2, [r3, #1172] @ 0x494 hpcd->USB_Address = address; 8003bb4: 687b ldr r3, [r7, #4] 8003bb6: 78fa ldrb r2, [r7, #3] 8003bb8: 745a strb r2, [r3, #17] (void)USB_SetDevAddress(hpcd->Instance, address); 8003bba: 687b ldr r3, [r7, #4] 8003bbc: 681b ldr r3, [r3, #0] 8003bbe: 78fa ldrb r2, [r7, #3] 8003bc0: 4611 mov r1, r2 8003bc2: 4618 mov r0, r3 8003bc4: f005 f9ae bl 8008f24 __HAL_UNLOCK(hpcd); 8003bc8: 687b ldr r3, [r7, #4] 8003bca: 2200 movs r2, #0 8003bcc: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003bd0: 2300 movs r3, #0 } 8003bd2: 4618 mov r0, r3 8003bd4: 3708 adds r7, #8 8003bd6: 46bd mov sp, r7 8003bd8: bd80 pop {r7, pc} 08003bda : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 8003bda: b580 push {r7, lr} 8003bdc: b084 sub sp, #16 8003bde: af00 add r7, sp, #0 8003be0: 6078 str r0, [r7, #4] 8003be2: 4608 mov r0, r1 8003be4: 4611 mov r1, r2 8003be6: 461a mov r2, r3 8003be8: 4603 mov r3, r0 8003bea: 70fb strb r3, [r7, #3] 8003bec: 460b mov r3, r1 8003bee: 803b strh r3, [r7, #0] 8003bf0: 4613 mov r3, r2 8003bf2: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 8003bf4: 2300 movs r3, #0 8003bf6: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8003bf8: f997 3003 ldrsb.w r3, [r7, #3] 8003bfc: 2b00 cmp r3, #0 8003bfe: da0f bge.n 8003c20 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003c00: 78fb ldrb r3, [r7, #3] 8003c02: f003 020f and.w r2, r3, #15 8003c06: 4613 mov r3, r2 8003c08: 00db lsls r3, r3, #3 8003c0a: 4413 add r3, r2 8003c0c: 009b lsls r3, r3, #2 8003c0e: 3310 adds r3, #16 8003c10: 687a ldr r2, [r7, #4] 8003c12: 4413 add r3, r2 8003c14: 3304 adds r3, #4 8003c16: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003c18: 68fb ldr r3, [r7, #12] 8003c1a: 2201 movs r2, #1 8003c1c: 705a strb r2, [r3, #1] 8003c1e: e00f b.n 8003c40 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003c20: 78fb ldrb r3, [r7, #3] 8003c22: f003 020f and.w r2, r3, #15 8003c26: 4613 mov r3, r2 8003c28: 00db lsls r3, r3, #3 8003c2a: 4413 add r3, r2 8003c2c: 009b lsls r3, r3, #2 8003c2e: f503 7314 add.w r3, r3, #592 @ 0x250 8003c32: 687a ldr r2, [r7, #4] 8003c34: 4413 add r3, r2 8003c36: 3304 adds r3, #4 8003c38: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003c3a: 68fb ldr r3, [r7, #12] 8003c3c: 2200 movs r2, #0 8003c3e: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8003c40: 78fb ldrb r3, [r7, #3] 8003c42: f003 030f and.w r3, r3, #15 8003c46: b2da uxtb r2, r3 8003c48: 68fb ldr r3, [r7, #12] 8003c4a: 701a strb r2, [r3, #0] ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; 8003c4c: 883b ldrh r3, [r7, #0] 8003c4e: f3c3 020a ubfx r2, r3, #0, #11 8003c52: 68fb ldr r3, [r7, #12] 8003c54: 609a str r2, [r3, #8] ep->type = ep_type; 8003c56: 68fb ldr r3, [r7, #12] 8003c58: 78ba ldrb r2, [r7, #2] 8003c5a: 711a strb r2, [r3, #4] if (ep->is_in != 0U) 8003c5c: 68fb ldr r3, [r7, #12] 8003c5e: 785b ldrb r3, [r3, #1] 8003c60: 2b00 cmp r3, #0 8003c62: d004 beq.n 8003c6e { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; 8003c64: 68fb ldr r3, [r7, #12] 8003c66: 781b ldrb r3, [r3, #0] 8003c68: 461a mov r2, r3 8003c6a: 68fb ldr r3, [r7, #12] 8003c6c: 835a strh r2, [r3, #26] } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 8003c6e: 78bb ldrb r3, [r7, #2] 8003c70: 2b02 cmp r3, #2 8003c72: d102 bne.n 8003c7a { ep->data_pid_start = 0U; 8003c74: 68fb ldr r3, [r7, #12] 8003c76: 2200 movs r2, #0 8003c78: 715a strb r2, [r3, #5] } __HAL_LOCK(hpcd); 8003c7a: 687b ldr r3, [r7, #4] 8003c7c: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003c80: 2b01 cmp r3, #1 8003c82: d101 bne.n 8003c88 8003c84: 2302 movs r3, #2 8003c86: e00e b.n 8003ca6 8003c88: 687b ldr r3, [r7, #4] 8003c8a: 2201 movs r2, #1 8003c8c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_ActivateEndpoint(hpcd->Instance, ep); 8003c90: 687b ldr r3, [r7, #4] 8003c92: 681b ldr r3, [r3, #0] 8003c94: 68f9 ldr r1, [r7, #12] 8003c96: 4618 mov r0, r3 8003c98: f004 fb2e bl 80082f8 __HAL_UNLOCK(hpcd); 8003c9c: 687b ldr r3, [r7, #4] 8003c9e: 2200 movs r2, #0 8003ca0: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return ret; 8003ca4: 7afb ldrb r3, [r7, #11] } 8003ca6: 4618 mov r0, r3 8003ca8: 3710 adds r7, #16 8003caa: 46bd mov sp, r7 8003cac: bd80 pop {r7, pc} 08003cae : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003cae: b580 push {r7, lr} 8003cb0: b084 sub sp, #16 8003cb2: af00 add r7, sp, #0 8003cb4: 6078 str r0, [r7, #4] 8003cb6: 460b mov r3, r1 8003cb8: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8003cba: f997 3003 ldrsb.w r3, [r7, #3] 8003cbe: 2b00 cmp r3, #0 8003cc0: da0f bge.n 8003ce2 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003cc2: 78fb ldrb r3, [r7, #3] 8003cc4: f003 020f and.w r2, r3, #15 8003cc8: 4613 mov r3, r2 8003cca: 00db lsls r3, r3, #3 8003ccc: 4413 add r3, r2 8003cce: 009b lsls r3, r3, #2 8003cd0: 3310 adds r3, #16 8003cd2: 687a ldr r2, [r7, #4] 8003cd4: 4413 add r3, r2 8003cd6: 3304 adds r3, #4 8003cd8: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003cda: 68fb ldr r3, [r7, #12] 8003cdc: 2201 movs r2, #1 8003cde: 705a strb r2, [r3, #1] 8003ce0: e00f b.n 8003d02 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003ce2: 78fb ldrb r3, [r7, #3] 8003ce4: f003 020f and.w r2, r3, #15 8003ce8: 4613 mov r3, r2 8003cea: 00db lsls r3, r3, #3 8003cec: 4413 add r3, r2 8003cee: 009b lsls r3, r3, #2 8003cf0: f503 7314 add.w r3, r3, #592 @ 0x250 8003cf4: 687a ldr r2, [r7, #4] 8003cf6: 4413 add r3, r2 8003cf8: 3304 adds r3, #4 8003cfa: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003cfc: 68fb ldr r3, [r7, #12] 8003cfe: 2200 movs r2, #0 8003d00: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8003d02: 78fb ldrb r3, [r7, #3] 8003d04: f003 030f and.w r3, r3, #15 8003d08: b2da uxtb r2, r3 8003d0a: 68fb ldr r3, [r7, #12] 8003d0c: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003d0e: 687b ldr r3, [r7, #4] 8003d10: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003d14: 2b01 cmp r3, #1 8003d16: d101 bne.n 8003d1c 8003d18: 2302 movs r3, #2 8003d1a: e00e b.n 8003d3a 8003d1c: 687b ldr r3, [r7, #4] 8003d1e: 2201 movs r2, #1 8003d20: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 8003d24: 687b ldr r3, [r7, #4] 8003d26: 681b ldr r3, [r3, #0] 8003d28: 68f9 ldr r1, [r7, #12] 8003d2a: 4618 mov r0, r3 8003d2c: f004 fb6c bl 8008408 __HAL_UNLOCK(hpcd); 8003d30: 687b ldr r3, [r7, #4] 8003d32: 2200 movs r2, #0 8003d34: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003d38: 2300 movs r3, #0 } 8003d3a: 4618 mov r0, r3 8003d3c: 3710 adds r7, #16 8003d3e: 46bd mov sp, r7 8003d40: bd80 pop {r7, pc} 08003d42 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8003d42: b580 push {r7, lr} 8003d44: b086 sub sp, #24 8003d46: af00 add r7, sp, #0 8003d48: 60f8 str r0, [r7, #12] 8003d4a: 607a str r2, [r7, #4] 8003d4c: 603b str r3, [r7, #0] 8003d4e: 460b mov r3, r1 8003d50: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003d52: 7afb ldrb r3, [r7, #11] 8003d54: f003 020f and.w r2, r3, #15 8003d58: 4613 mov r3, r2 8003d5a: 00db lsls r3, r3, #3 8003d5c: 4413 add r3, r2 8003d5e: 009b lsls r3, r3, #2 8003d60: f503 7314 add.w r3, r3, #592 @ 0x250 8003d64: 68fa ldr r2, [r7, #12] 8003d66: 4413 add r3, r2 8003d68: 3304 adds r3, #4 8003d6a: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003d6c: 697b ldr r3, [r7, #20] 8003d6e: 687a ldr r2, [r7, #4] 8003d70: 60da str r2, [r3, #12] ep->xfer_len = len; 8003d72: 697b ldr r3, [r7, #20] 8003d74: 683a ldr r2, [r7, #0] 8003d76: 611a str r2, [r3, #16] ep->xfer_count = 0U; 8003d78: 697b ldr r3, [r7, #20] 8003d7a: 2200 movs r2, #0 8003d7c: 615a str r2, [r3, #20] ep->is_in = 0U; 8003d7e: 697b ldr r3, [r7, #20] 8003d80: 2200 movs r2, #0 8003d82: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8003d84: 7afb ldrb r3, [r7, #11] 8003d86: f003 030f and.w r3, r3, #15 8003d8a: b2da uxtb r2, r3 8003d8c: 697b ldr r3, [r7, #20] 8003d8e: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003d90: 68fb ldr r3, [r7, #12] 8003d92: 799b ldrb r3, [r3, #6] 8003d94: 2b01 cmp r3, #1 8003d96: d102 bne.n 8003d9e { ep->dma_addr = (uint32_t)pBuf; 8003d98: 687a ldr r2, [r7, #4] 8003d9a: 697b ldr r3, [r7, #20] 8003d9c: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003d9e: 68fb ldr r3, [r7, #12] 8003da0: 6818 ldr r0, [r3, #0] 8003da2: 68fb ldr r3, [r7, #12] 8003da4: 799b ldrb r3, [r3, #6] 8003da6: 461a mov r2, r3 8003da8: 6979 ldr r1, [r7, #20] 8003daa: f004 fc09 bl 80085c0 return HAL_OK; 8003dae: 2300 movs r3, #0 } 8003db0: 4618 mov r0, r3 8003db2: 3718 adds r7, #24 8003db4: 46bd mov sp, r7 8003db6: bd80 pop {r7, pc} 08003db8 : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8003db8: b580 push {r7, lr} 8003dba: b086 sub sp, #24 8003dbc: af00 add r7, sp, #0 8003dbe: 60f8 str r0, [r7, #12] 8003dc0: 607a str r2, [r7, #4] 8003dc2: 603b str r3, [r7, #0] 8003dc4: 460b mov r3, r1 8003dc6: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003dc8: 7afb ldrb r3, [r7, #11] 8003dca: f003 020f and.w r2, r3, #15 8003dce: 4613 mov r3, r2 8003dd0: 00db lsls r3, r3, #3 8003dd2: 4413 add r3, r2 8003dd4: 009b lsls r3, r3, #2 8003dd6: 3310 adds r3, #16 8003dd8: 68fa ldr r2, [r7, #12] 8003dda: 4413 add r3, r2 8003ddc: 3304 adds r3, #4 8003dde: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003de0: 697b ldr r3, [r7, #20] 8003de2: 687a ldr r2, [r7, #4] 8003de4: 60da str r2, [r3, #12] ep->xfer_len = len; 8003de6: 697b ldr r3, [r7, #20] 8003de8: 683a ldr r2, [r7, #0] 8003dea: 611a str r2, [r3, #16] ep->xfer_count = 0U; 8003dec: 697b ldr r3, [r7, #20] 8003dee: 2200 movs r2, #0 8003df0: 615a str r2, [r3, #20] ep->is_in = 1U; 8003df2: 697b ldr r3, [r7, #20] 8003df4: 2201 movs r2, #1 8003df6: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8003df8: 7afb ldrb r3, [r7, #11] 8003dfa: f003 030f and.w r3, r3, #15 8003dfe: b2da uxtb r2, r3 8003e00: 697b ldr r3, [r7, #20] 8003e02: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003e04: 68fb ldr r3, [r7, #12] 8003e06: 799b ldrb r3, [r3, #6] 8003e08: 2b01 cmp r3, #1 8003e0a: d102 bne.n 8003e12 { ep->dma_addr = (uint32_t)pBuf; 8003e0c: 687a ldr r2, [r7, #4] 8003e0e: 697b ldr r3, [r7, #20] 8003e10: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003e12: 68fb ldr r3, [r7, #12] 8003e14: 6818 ldr r0, [r3, #0] 8003e16: 68fb ldr r3, [r7, #12] 8003e18: 799b ldrb r3, [r3, #6] 8003e1a: 461a mov r2, r3 8003e1c: 6979 ldr r1, [r7, #20] 8003e1e: f004 fbcf bl 80085c0 return HAL_OK; 8003e22: 2300 movs r3, #0 } 8003e24: 4618 mov r0, r3 8003e26: 3718 adds r7, #24 8003e28: 46bd mov sp, r7 8003e2a: bd80 pop {r7, pc} 08003e2c : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003e2c: b580 push {r7, lr} 8003e2e: b084 sub sp, #16 8003e30: af00 add r7, sp, #0 8003e32: 6078 str r0, [r7, #4] 8003e34: 460b mov r3, r1 8003e36: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 8003e38: 78fb ldrb r3, [r7, #3] 8003e3a: f003 030f and.w r3, r3, #15 8003e3e: 687a ldr r2, [r7, #4] 8003e40: 7912 ldrb r2, [r2, #4] 8003e42: 4293 cmp r3, r2 8003e44: d901 bls.n 8003e4a { return HAL_ERROR; 8003e46: 2301 movs r3, #1 8003e48: e04f b.n 8003eea } if ((0x80U & ep_addr) == 0x80U) 8003e4a: f997 3003 ldrsb.w r3, [r7, #3] 8003e4e: 2b00 cmp r3, #0 8003e50: da0f bge.n 8003e72 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003e52: 78fb ldrb r3, [r7, #3] 8003e54: f003 020f and.w r2, r3, #15 8003e58: 4613 mov r3, r2 8003e5a: 00db lsls r3, r3, #3 8003e5c: 4413 add r3, r2 8003e5e: 009b lsls r3, r3, #2 8003e60: 3310 adds r3, #16 8003e62: 687a ldr r2, [r7, #4] 8003e64: 4413 add r3, r2 8003e66: 3304 adds r3, #4 8003e68: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003e6a: 68fb ldr r3, [r7, #12] 8003e6c: 2201 movs r2, #1 8003e6e: 705a strb r2, [r3, #1] 8003e70: e00d b.n 8003e8e } else { ep = &hpcd->OUT_ep[ep_addr]; 8003e72: 78fa ldrb r2, [r7, #3] 8003e74: 4613 mov r3, r2 8003e76: 00db lsls r3, r3, #3 8003e78: 4413 add r3, r2 8003e7a: 009b lsls r3, r3, #2 8003e7c: f503 7314 add.w r3, r3, #592 @ 0x250 8003e80: 687a ldr r2, [r7, #4] 8003e82: 4413 add r3, r2 8003e84: 3304 adds r3, #4 8003e86: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003e88: 68fb ldr r3, [r7, #12] 8003e8a: 2200 movs r2, #0 8003e8c: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8003e8e: 68fb ldr r3, [r7, #12] 8003e90: 2201 movs r2, #1 8003e92: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003e94: 78fb ldrb r3, [r7, #3] 8003e96: f003 030f and.w r3, r3, #15 8003e9a: b2da uxtb r2, r3 8003e9c: 68fb ldr r3, [r7, #12] 8003e9e: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003ea0: 687b ldr r3, [r7, #4] 8003ea2: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003ea6: 2b01 cmp r3, #1 8003ea8: d101 bne.n 8003eae 8003eaa: 2302 movs r3, #2 8003eac: e01d b.n 8003eea 8003eae: 687b ldr r3, [r7, #4] 8003eb0: 2201 movs r2, #1 8003eb2: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPSetStall(hpcd->Instance, ep); 8003eb6: 687b ldr r3, [r7, #4] 8003eb8: 681b ldr r3, [r3, #0] 8003eba: 68f9 ldr r1, [r7, #12] 8003ebc: 4618 mov r0, r3 8003ebe: f004 ff5d bl 8008d7c if ((ep_addr & EP_ADDR_MSK) == 0U) 8003ec2: 78fb ldrb r3, [r7, #3] 8003ec4: f003 030f and.w r3, r3, #15 8003ec8: 2b00 cmp r3, #0 8003eca: d109 bne.n 8003ee0 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); 8003ecc: 687b ldr r3, [r7, #4] 8003ece: 6818 ldr r0, [r3, #0] 8003ed0: 687b ldr r3, [r7, #4] 8003ed2: 7999 ldrb r1, [r3, #6] 8003ed4: 687b ldr r3, [r7, #4] 8003ed6: f203 439c addw r3, r3, #1180 @ 0x49c 8003eda: 461a mov r2, r3 8003edc: f005 f94e bl 800917c } __HAL_UNLOCK(hpcd); 8003ee0: 687b ldr r3, [r7, #4] 8003ee2: 2200 movs r2, #0 8003ee4: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003ee8: 2300 movs r3, #0 } 8003eea: 4618 mov r0, r3 8003eec: 3710 adds r7, #16 8003eee: 46bd mov sp, r7 8003ef0: bd80 pop {r7, pc} 08003ef2 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003ef2: b580 push {r7, lr} 8003ef4: b084 sub sp, #16 8003ef6: af00 add r7, sp, #0 8003ef8: 6078 str r0, [r7, #4] 8003efa: 460b mov r3, r1 8003efc: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8003efe: 78fb ldrb r3, [r7, #3] 8003f00: f003 030f and.w r3, r3, #15 8003f04: 687a ldr r2, [r7, #4] 8003f06: 7912 ldrb r2, [r2, #4] 8003f08: 4293 cmp r3, r2 8003f0a: d901 bls.n 8003f10 { return HAL_ERROR; 8003f0c: 2301 movs r3, #1 8003f0e: e042 b.n 8003f96 } if ((0x80U & ep_addr) == 0x80U) 8003f10: f997 3003 ldrsb.w r3, [r7, #3] 8003f14: 2b00 cmp r3, #0 8003f16: da0f bge.n 8003f38 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003f18: 78fb ldrb r3, [r7, #3] 8003f1a: f003 020f and.w r2, r3, #15 8003f1e: 4613 mov r3, r2 8003f20: 00db lsls r3, r3, #3 8003f22: 4413 add r3, r2 8003f24: 009b lsls r3, r3, #2 8003f26: 3310 adds r3, #16 8003f28: 687a ldr r2, [r7, #4] 8003f2a: 4413 add r3, r2 8003f2c: 3304 adds r3, #4 8003f2e: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003f30: 68fb ldr r3, [r7, #12] 8003f32: 2201 movs r2, #1 8003f34: 705a strb r2, [r3, #1] 8003f36: e00f b.n 8003f58 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003f38: 78fb ldrb r3, [r7, #3] 8003f3a: f003 020f and.w r2, r3, #15 8003f3e: 4613 mov r3, r2 8003f40: 00db lsls r3, r3, #3 8003f42: 4413 add r3, r2 8003f44: 009b lsls r3, r3, #2 8003f46: f503 7314 add.w r3, r3, #592 @ 0x250 8003f4a: 687a ldr r2, [r7, #4] 8003f4c: 4413 add r3, r2 8003f4e: 3304 adds r3, #4 8003f50: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003f52: 68fb ldr r3, [r7, #12] 8003f54: 2200 movs r2, #0 8003f56: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8003f58: 68fb ldr r3, [r7, #12] 8003f5a: 2200 movs r2, #0 8003f5c: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003f5e: 78fb ldrb r3, [r7, #3] 8003f60: f003 030f and.w r3, r3, #15 8003f64: b2da uxtb r2, r3 8003f66: 68fb ldr r3, [r7, #12] 8003f68: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003f6a: 687b ldr r3, [r7, #4] 8003f6c: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003f70: 2b01 cmp r3, #1 8003f72: d101 bne.n 8003f78 8003f74: 2302 movs r3, #2 8003f76: e00e b.n 8003f96 8003f78: 687b ldr r3, [r7, #4] 8003f7a: 2201 movs r2, #1 8003f7c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPClearStall(hpcd->Instance, ep); 8003f80: 687b ldr r3, [r7, #4] 8003f82: 681b ldr r3, [r3, #0] 8003f84: 68f9 ldr r1, [r7, #12] 8003f86: 4618 mov r0, r3 8003f88: f004 ff66 bl 8008e58 __HAL_UNLOCK(hpcd); 8003f8c: 687b ldr r3, [r7, #4] 8003f8e: 2200 movs r2, #0 8003f90: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003f94: 2300 movs r3, #0 } 8003f96: 4618 mov r0, r3 8003f98: 3710 adds r7, #16 8003f9a: 46bd mov sp, r7 8003f9c: bd80 pop {r7, pc} 08003f9e : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003f9e: b580 push {r7, lr} 8003fa0: b084 sub sp, #16 8003fa2: af00 add r7, sp, #0 8003fa4: 6078 str r0, [r7, #4] 8003fa6: 460b mov r3, r1 8003fa8: 70fb strb r3, [r7, #3] HAL_StatusTypeDef ret; PCD_EPTypeDef *ep; if ((0x80U & ep_addr) == 0x80U) 8003faa: f997 3003 ldrsb.w r3, [r7, #3] 8003fae: 2b00 cmp r3, #0 8003fb0: da0c bge.n 8003fcc { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003fb2: 78fb ldrb r3, [r7, #3] 8003fb4: f003 020f and.w r2, r3, #15 8003fb8: 4613 mov r3, r2 8003fba: 00db lsls r3, r3, #3 8003fbc: 4413 add r3, r2 8003fbe: 009b lsls r3, r3, #2 8003fc0: 3310 adds r3, #16 8003fc2: 687a ldr r2, [r7, #4] 8003fc4: 4413 add r3, r2 8003fc6: 3304 adds r3, #4 8003fc8: 60fb str r3, [r7, #12] 8003fca: e00c b.n 8003fe6 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003fcc: 78fb ldrb r3, [r7, #3] 8003fce: f003 020f and.w r2, r3, #15 8003fd2: 4613 mov r3, r2 8003fd4: 00db lsls r3, r3, #3 8003fd6: 4413 add r3, r2 8003fd8: 009b lsls r3, r3, #2 8003fda: f503 7314 add.w r3, r3, #592 @ 0x250 8003fde: 687a ldr r2, [r7, #4] 8003fe0: 4413 add r3, r2 8003fe2: 3304 adds r3, #4 8003fe4: 60fb str r3, [r7, #12] } /* Stop Xfer */ ret = USB_EPStopXfer(hpcd->Instance, ep); 8003fe6: 687b ldr r3, [r7, #4] 8003fe8: 681b ldr r3, [r3, #0] 8003fea: 68f9 ldr r1, [r7, #12] 8003fec: 4618 mov r0, r3 8003fee: f004 fd85 bl 8008afc 8003ff2: 4603 mov r3, r0 8003ff4: 72fb strb r3, [r7, #11] return ret; 8003ff6: 7afb ldrb r3, [r7, #11] } 8003ff8: 4618 mov r0, r3 8003ffa: 3710 adds r7, #16 8003ffc: 46bd mov sp, r7 8003ffe: bd80 pop {r7, pc} 08004000 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8004000: b580 push {r7, lr} 8004002: b08a sub sp, #40 @ 0x28 8004004: af02 add r7, sp, #8 8004006: 6078 str r0, [r7, #4] 8004008: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 800400a: 687b ldr r3, [r7, #4] 800400c: 681b ldr r3, [r3, #0] 800400e: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8004010: 697b ldr r3, [r7, #20] 8004012: 613b str r3, [r7, #16] USB_OTG_EPTypeDef *ep; uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; 8004014: 683a ldr r2, [r7, #0] 8004016: 4613 mov r3, r2 8004018: 00db lsls r3, r3, #3 800401a: 4413 add r3, r2 800401c: 009b lsls r3, r3, #2 800401e: 3310 adds r3, #16 8004020: 687a ldr r2, [r7, #4] 8004022: 4413 add r3, r2 8004024: 3304 adds r3, #4 8004026: 60fb str r3, [r7, #12] if (ep->xfer_count > ep->xfer_len) 8004028: 68fb ldr r3, [r7, #12] 800402a: 695a ldr r2, [r3, #20] 800402c: 68fb ldr r3, [r7, #12] 800402e: 691b ldr r3, [r3, #16] 8004030: 429a cmp r2, r3 8004032: d901 bls.n 8004038 { return HAL_ERROR; 8004034: 2301 movs r3, #1 8004036: e06b b.n 8004110 } len = ep->xfer_len - ep->xfer_count; 8004038: 68fb ldr r3, [r7, #12] 800403a: 691a ldr r2, [r3, #16] 800403c: 68fb ldr r3, [r7, #12] 800403e: 695b ldr r3, [r3, #20] 8004040: 1ad3 subs r3, r2, r3 8004042: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8004044: 68fb ldr r3, [r7, #12] 8004046: 689b ldr r3, [r3, #8] 8004048: 69fa ldr r2, [r7, #28] 800404a: 429a cmp r2, r3 800404c: d902 bls.n 8004054 { len = ep->maxpacket; 800404e: 68fb ldr r3, [r7, #12] 8004050: 689b ldr r3, [r3, #8] 8004052: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8004054: 69fb ldr r3, [r7, #28] 8004056: 3303 adds r3, #3 8004058: 089b lsrs r3, r3, #2 800405a: 61bb str r3, [r7, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 800405c: e02a b.n 80040b4 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; 800405e: 68fb ldr r3, [r7, #12] 8004060: 691a ldr r2, [r3, #16] 8004062: 68fb ldr r3, [r7, #12] 8004064: 695b ldr r3, [r3, #20] 8004066: 1ad3 subs r3, r2, r3 8004068: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 800406a: 68fb ldr r3, [r7, #12] 800406c: 689b ldr r3, [r3, #8] 800406e: 69fa ldr r2, [r7, #28] 8004070: 429a cmp r2, r3 8004072: d902 bls.n 800407a { len = ep->maxpacket; 8004074: 68fb ldr r3, [r7, #12] 8004076: 689b ldr r3, [r3, #8] 8004078: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 800407a: 69fb ldr r3, [r7, #28] 800407c: 3303 adds r3, #3 800407e: 089b lsrs r3, r3, #2 8004080: 61bb str r3, [r7, #24] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8004082: 68fb ldr r3, [r7, #12] 8004084: 68d9 ldr r1, [r3, #12] 8004086: 683b ldr r3, [r7, #0] 8004088: b2da uxtb r2, r3 800408a: 69fb ldr r3, [r7, #28] 800408c: b298 uxth r0, r3 (uint8_t)hpcd->Init.dma_enable); 800408e: 687b ldr r3, [r7, #4] 8004090: 799b ldrb r3, [r3, #6] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8004092: 9300 str r3, [sp, #0] 8004094: 4603 mov r3, r0 8004096: 6978 ldr r0, [r7, #20] 8004098: f004 fdda bl 8008c50 ep->xfer_buff += len; 800409c: 68fb ldr r3, [r7, #12] 800409e: 68da ldr r2, [r3, #12] 80040a0: 69fb ldr r3, [r7, #28] 80040a2: 441a add r2, r3 80040a4: 68fb ldr r3, [r7, #12] 80040a6: 60da str r2, [r3, #12] ep->xfer_count += len; 80040a8: 68fb ldr r3, [r7, #12] 80040aa: 695a ldr r2, [r3, #20] 80040ac: 69fb ldr r3, [r7, #28] 80040ae: 441a add r2, r3 80040b0: 68fb ldr r3, [r7, #12] 80040b2: 615a str r2, [r3, #20] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 80040b4: 683b ldr r3, [r7, #0] 80040b6: 015a lsls r2, r3, #5 80040b8: 693b ldr r3, [r7, #16] 80040ba: 4413 add r3, r2 80040bc: f503 6310 add.w r3, r3, #2304 @ 0x900 80040c0: 699b ldr r3, [r3, #24] 80040c2: b29b uxth r3, r3 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 80040c4: 69ba ldr r2, [r7, #24] 80040c6: 429a cmp r2, r3 80040c8: d809 bhi.n 80040de 80040ca: 68fb ldr r3, [r7, #12] 80040cc: 695a ldr r2, [r3, #20] 80040ce: 68fb ldr r3, [r7, #12] 80040d0: 691b ldr r3, [r3, #16] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 80040d2: 429a cmp r2, r3 80040d4: d203 bcs.n 80040de (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 80040d6: 68fb ldr r3, [r7, #12] 80040d8: 691b ldr r3, [r3, #16] 80040da: 2b00 cmp r3, #0 80040dc: d1bf bne.n 800405e } if (ep->xfer_len <= ep->xfer_count) 80040de: 68fb ldr r3, [r7, #12] 80040e0: 691a ldr r2, [r3, #16] 80040e2: 68fb ldr r3, [r7, #12] 80040e4: 695b ldr r3, [r3, #20] 80040e6: 429a cmp r2, r3 80040e8: d811 bhi.n 800410e { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 80040ea: 683b ldr r3, [r7, #0] 80040ec: f003 030f and.w r3, r3, #15 80040f0: 2201 movs r2, #1 80040f2: fa02 f303 lsl.w r3, r2, r3 80040f6: 60bb str r3, [r7, #8] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 80040f8: 693b ldr r3, [r7, #16] 80040fa: f503 6300 add.w r3, r3, #2048 @ 0x800 80040fe: 6b5a ldr r2, [r3, #52] @ 0x34 8004100: 68bb ldr r3, [r7, #8] 8004102: 43db mvns r3, r3 8004104: 6939 ldr r1, [r7, #16] 8004106: f501 6100 add.w r1, r1, #2048 @ 0x800 800410a: 4013 ands r3, r2 800410c: 634b str r3, [r1, #52] @ 0x34 } return HAL_OK; 800410e: 2300 movs r3, #0 } 8004110: 4618 mov r0, r3 8004112: 3720 adds r7, #32 8004114: 46bd mov sp, r7 8004116: bd80 pop {r7, pc} 08004118 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8004118: b580 push {r7, lr} 800411a: b088 sub sp, #32 800411c: af00 add r7, sp, #0 800411e: 6078 str r0, [r7, #4] 8004120: 6039 str r1, [r7, #0] USB_OTG_EPTypeDef *ep; const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8004122: 687b ldr r3, [r7, #4] 8004124: 681b ldr r3, [r3, #0] 8004126: 61fb str r3, [r7, #28] uint32_t USBx_BASE = (uint32_t)USBx; 8004128: 69fb ldr r3, [r7, #28] 800412a: 61bb str r3, [r7, #24] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 800412c: 69fb ldr r3, [r7, #28] 800412e: 333c adds r3, #60 @ 0x3c 8004130: 3304 adds r3, #4 8004132: 681b ldr r3, [r3, #0] 8004134: 617b str r3, [r7, #20] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8004136: 683b ldr r3, [r7, #0] 8004138: 015a lsls r2, r3, #5 800413a: 69bb ldr r3, [r7, #24] 800413c: 4413 add r3, r2 800413e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004142: 689b ldr r3, [r3, #8] 8004144: 613b str r3, [r7, #16] if (hpcd->Init.dma_enable == 1U) 8004146: 687b ldr r3, [r7, #4] 8004148: 799b ldrb r3, [r3, #6] 800414a: 2b01 cmp r3, #1 800414c: d17b bne.n 8004246 { if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ 800414e: 693b ldr r3, [r7, #16] 8004150: f003 0308 and.w r3, r3, #8 8004154: 2b00 cmp r3, #0 8004156: d015 beq.n 8004184 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8004158: 697b ldr r3, [r7, #20] 800415a: 4a61 ldr r2, [pc, #388] @ (80042e0 ) 800415c: 4293 cmp r3, r2 800415e: f240 80b9 bls.w 80042d4 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8004162: 693b ldr r3, [r7, #16] 8004164: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8004168: 2b00 cmp r3, #0 800416a: f000 80b3 beq.w 80042d4 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 800416e: 683b ldr r3, [r7, #0] 8004170: 015a lsls r2, r3, #5 8004172: 69bb ldr r3, [r7, #24] 8004174: 4413 add r3, r2 8004176: f503 6330 add.w r3, r3, #2816 @ 0xb00 800417a: 461a mov r2, r3 800417c: f44f 4300 mov.w r3, #32768 @ 0x8000 8004180: 6093 str r3, [r2, #8] 8004182: e0a7 b.n 80042d4 } } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ 8004184: 693b ldr r3, [r7, #16] 8004186: f003 0320 and.w r3, r3, #32 800418a: 2b00 cmp r3, #0 800418c: d009 beq.n 80041a2 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 800418e: 683b ldr r3, [r7, #0] 8004190: 015a lsls r2, r3, #5 8004192: 69bb ldr r3, [r7, #24] 8004194: 4413 add r3, r2 8004196: f503 6330 add.w r3, r3, #2816 @ 0xb00 800419a: 461a mov r2, r3 800419c: 2320 movs r3, #32 800419e: 6093 str r3, [r2, #8] 80041a0: e098 b.n 80042d4 } else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) 80041a2: 693b ldr r3, [r7, #16] 80041a4: f003 0328 and.w r3, r3, #40 @ 0x28 80041a8: 2b00 cmp r3, #0 80041aa: f040 8093 bne.w 80042d4 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 80041ae: 697b ldr r3, [r7, #20] 80041b0: 4a4b ldr r2, [pc, #300] @ (80042e0 ) 80041b2: 4293 cmp r3, r2 80041b4: d90f bls.n 80041d6 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 80041b6: 693b ldr r3, [r7, #16] 80041b8: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 80041bc: 2b00 cmp r3, #0 80041be: d00a beq.n 80041d6 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 80041c0: 683b ldr r3, [r7, #0] 80041c2: 015a lsls r2, r3, #5 80041c4: 69bb ldr r3, [r7, #24] 80041c6: 4413 add r3, r2 80041c8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80041cc: 461a mov r2, r3 80041ce: f44f 4300 mov.w r3, #32768 @ 0x8000 80041d2: 6093 str r3, [r2, #8] 80041d4: e07e b.n 80042d4 } else { ep = &hpcd->OUT_ep[epnum]; 80041d6: 683a ldr r2, [r7, #0] 80041d8: 4613 mov r3, r2 80041da: 00db lsls r3, r3, #3 80041dc: 4413 add r3, r2 80041de: 009b lsls r3, r3, #2 80041e0: f503 7314 add.w r3, r3, #592 @ 0x250 80041e4: 687a ldr r2, [r7, #4] 80041e6: 4413 add r3, r2 80041e8: 3304 adds r3, #4 80041ea: 60fb str r3, [r7, #12] /* out data packet received over EP */ ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 80041ec: 68fb ldr r3, [r7, #12] 80041ee: 6a1a ldr r2, [r3, #32] 80041f0: 683b ldr r3, [r7, #0] 80041f2: 0159 lsls r1, r3, #5 80041f4: 69bb ldr r3, [r7, #24] 80041f6: 440b add r3, r1 80041f8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80041fc: 691b ldr r3, [r3, #16] 80041fe: f3c3 0312 ubfx r3, r3, #0, #19 8004202: 1ad2 subs r2, r2, r3 8004204: 68fb ldr r3, [r7, #12] 8004206: 615a str r2, [r3, #20] if (epnum == 0U) 8004208: 683b ldr r3, [r7, #0] 800420a: 2b00 cmp r3, #0 800420c: d114 bne.n 8004238 { if (ep->xfer_len == 0U) 800420e: 68fb ldr r3, [r7, #12] 8004210: 691b ldr r3, [r3, #16] 8004212: 2b00 cmp r3, #0 8004214: d109 bne.n 800422a { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8004216: 687b ldr r3, [r7, #4] 8004218: 6818 ldr r0, [r3, #0] 800421a: 687b ldr r3, [r7, #4] 800421c: f203 439c addw r3, r3, #1180 @ 0x49c 8004220: 461a mov r2, r3 8004222: 2101 movs r1, #1 8004224: f004 ffaa bl 800917c 8004228: e006 b.n 8004238 } else { ep->xfer_buff += ep->xfer_count; 800422a: 68fb ldr r3, [r7, #12] 800422c: 68da ldr r2, [r3, #12] 800422e: 68fb ldr r3, [r7, #12] 8004230: 695b ldr r3, [r3, #20] 8004232: 441a add r2, r3 8004234: 68fb ldr r3, [r7, #12] 8004236: 60da str r2, [r3, #12] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8004238: 683b ldr r3, [r7, #0] 800423a: b2db uxtb r3, r3 800423c: 4619 mov r1, r3 800423e: 6878 ldr r0, [r7, #4] 8004240: f006 ff78 bl 800b134 8004244: e046 b.n 80042d4 /* ... */ } } else { if (gSNPSiD == USB_OTG_CORE_ID_310A) 8004246: 697b ldr r3, [r7, #20] 8004248: 4a26 ldr r2, [pc, #152] @ (80042e4 ) 800424a: 4293 cmp r3, r2 800424c: d124 bne.n 8004298 { /* StupPktRcvd = 1 this is a setup packet */ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) 800424e: 693b ldr r3, [r7, #16] 8004250: f403 4300 and.w r3, r3, #32768 @ 0x8000 8004254: 2b00 cmp r3, #0 8004256: d00a beq.n 800426e { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8004258: 683b ldr r3, [r7, #0] 800425a: 015a lsls r2, r3, #5 800425c: 69bb ldr r3, [r7, #24] 800425e: 4413 add r3, r2 8004260: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004264: 461a mov r2, r3 8004266: f44f 4300 mov.w r3, #32768 @ 0x8000 800426a: 6093 str r3, [r2, #8] 800426c: e032 b.n 80042d4 } else { if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 800426e: 693b ldr r3, [r7, #16] 8004270: f003 0320 and.w r3, r3, #32 8004274: 2b00 cmp r3, #0 8004276: d008 beq.n 800428a { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8004278: 683b ldr r3, [r7, #0] 800427a: 015a lsls r2, r3, #5 800427c: 69bb ldr r3, [r7, #24] 800427e: 4413 add r3, r2 8004280: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004284: 461a mov r2, r3 8004286: 2320 movs r3, #32 8004288: 6093 str r3, [r2, #8] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 800428a: 683b ldr r3, [r7, #0] 800428c: b2db uxtb r3, r3 800428e: 4619 mov r1, r3 8004290: 6878 ldr r0, [r7, #4] 8004292: f006 ff4f bl 800b134 8004296: e01d b.n 80042d4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else { if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8004298: 683b ldr r3, [r7, #0] 800429a: 2b00 cmp r3, #0 800429c: d114 bne.n 80042c8 800429e: 6879 ldr r1, [r7, #4] 80042a0: 683a ldr r2, [r7, #0] 80042a2: 4613 mov r3, r2 80042a4: 00db lsls r3, r3, #3 80042a6: 4413 add r3, r2 80042a8: 009b lsls r3, r3, #2 80042aa: 440b add r3, r1 80042ac: f503 7319 add.w r3, r3, #612 @ 0x264 80042b0: 681b ldr r3, [r3, #0] 80042b2: 2b00 cmp r3, #0 80042b4: d108 bne.n 80042c8 { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); 80042b6: 687b ldr r3, [r7, #4] 80042b8: 6818 ldr r0, [r3, #0] 80042ba: 687b ldr r3, [r7, #4] 80042bc: f203 439c addw r3, r3, #1180 @ 0x49c 80042c0: 461a mov r2, r3 80042c2: 2100 movs r1, #0 80042c4: f004 ff5a bl 800917c } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 80042c8: 683b ldr r3, [r7, #0] 80042ca: b2db uxtb r3, r3 80042cc: 4619 mov r1, r3 80042ce: 6878 ldr r0, [r7, #4] 80042d0: f006 ff30 bl 800b134 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } return HAL_OK; 80042d4: 2300 movs r3, #0 } 80042d6: 4618 mov r0, r3 80042d8: 3720 adds r7, #32 80042da: 46bd mov sp, r7 80042dc: bd80 pop {r7, pc} 80042de: bf00 nop 80042e0: 4f54300a .word 0x4f54300a 80042e4: 4f54310a .word 0x4f54310a 080042e8 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 80042e8: b580 push {r7, lr} 80042ea: b086 sub sp, #24 80042ec: af00 add r7, sp, #0 80042ee: 6078 str r0, [r7, #4] 80042f0: 6039 str r1, [r7, #0] const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 80042f2: 687b ldr r3, [r7, #4] 80042f4: 681b ldr r3, [r3, #0] 80042f6: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 80042f8: 697b ldr r3, [r7, #20] 80042fa: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 80042fc: 697b ldr r3, [r7, #20] 80042fe: 333c adds r3, #60 @ 0x3c 8004300: 3304 adds r3, #4 8004302: 681b ldr r3, [r3, #0] 8004304: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8004306: 683b ldr r3, [r7, #0] 8004308: 015a lsls r2, r3, #5 800430a: 693b ldr r3, [r7, #16] 800430c: 4413 add r3, r2 800430e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004312: 689b ldr r3, [r3, #8] 8004314: 60bb str r3, [r7, #8] if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8004316: 68fb ldr r3, [r7, #12] 8004318: 4a15 ldr r2, [pc, #84] @ (8004370 ) 800431a: 4293 cmp r3, r2 800431c: d90e bls.n 800433c ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 800431e: 68bb ldr r3, [r7, #8] 8004320: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8004324: 2b00 cmp r3, #0 8004326: d009 beq.n 800433c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8004328: 683b ldr r3, [r7, #0] 800432a: 015a lsls r2, r3, #5 800432c: 693b ldr r3, [r7, #16] 800432e: 4413 add r3, r2 8004330: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004334: 461a mov r2, r3 8004336: f44f 4300 mov.w r3, #32768 @ 0x8000 800433a: 6093 str r3, [r2, #8] /* Inform the upper layer that a setup packet is available */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 800433c: 6878 ldr r0, [r7, #4] 800433e: f006 fee7 bl 800b110 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) 8004342: 68fb ldr r3, [r7, #12] 8004344: 4a0a ldr r2, [pc, #40] @ (8004370 ) 8004346: 4293 cmp r3, r2 8004348: d90c bls.n 8004364 800434a: 687b ldr r3, [r7, #4] 800434c: 799b ldrb r3, [r3, #6] 800434e: 2b01 cmp r3, #1 8004350: d108 bne.n 8004364 { (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8004352: 687b ldr r3, [r7, #4] 8004354: 6818 ldr r0, [r3, #0] 8004356: 687b ldr r3, [r7, #4] 8004358: f203 439c addw r3, r3, #1180 @ 0x49c 800435c: 461a mov r2, r3 800435e: 2101 movs r1, #1 8004360: f004 ff0c bl 800917c } return HAL_OK; 8004364: 2300 movs r3, #0 } 8004366: 4618 mov r0, r3 8004368: 3718 adds r7, #24 800436a: 46bd mov sp, r7 800436c: bd80 pop {r7, pc} 800436e: bf00 nop 8004370: 4f54300a .word 0x4f54300a 08004374 : * @param fifo The number of Tx fifo * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { 8004374: b480 push {r7} 8004376: b085 sub sp, #20 8004378: af00 add r7, sp, #0 800437a: 6078 str r0, [r7, #4] 800437c: 460b mov r3, r1 800437e: 70fb strb r3, [r7, #3] 8004380: 4613 mov r3, r2 8004382: 803b strh r3, [r7, #0] --> Txn should be configured with the minimum space of 16 words The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ Tx_Offset = hpcd->Instance->GRXFSIZ; 8004384: 687b ldr r3, [r7, #4] 8004386: 681b ldr r3, [r3, #0] 8004388: 6a5b ldr r3, [r3, #36] @ 0x24 800438a: 60bb str r3, [r7, #8] if (fifo == 0U) 800438c: 78fb ldrb r3, [r7, #3] 800438e: 2b00 cmp r3, #0 8004390: d107 bne.n 80043a2 { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; 8004392: 883b ldrh r3, [r7, #0] 8004394: 0419 lsls r1, r3, #16 8004396: 687b ldr r3, [r7, #4] 8004398: 681b ldr r3, [r3, #0] 800439a: 68ba ldr r2, [r7, #8] 800439c: 430a orrs r2, r1 800439e: 629a str r2, [r3, #40] @ 0x28 80043a0: e028 b.n 80043f4 } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; 80043a2: 687b ldr r3, [r7, #4] 80043a4: 681b ldr r3, [r3, #0] 80043a6: 6a9b ldr r3, [r3, #40] @ 0x28 80043a8: 0c1b lsrs r3, r3, #16 80043aa: 68ba ldr r2, [r7, #8] 80043ac: 4413 add r3, r2 80043ae: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 80043b0: 2300 movs r3, #0 80043b2: 73fb strb r3, [r7, #15] 80043b4: e00d b.n 80043d2 { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); 80043b6: 687b ldr r3, [r7, #4] 80043b8: 681a ldr r2, [r3, #0] 80043ba: 7bfb ldrb r3, [r7, #15] 80043bc: 3340 adds r3, #64 @ 0x40 80043be: 009b lsls r3, r3, #2 80043c0: 4413 add r3, r2 80043c2: 685b ldr r3, [r3, #4] 80043c4: 0c1b lsrs r3, r3, #16 80043c6: 68ba ldr r2, [r7, #8] 80043c8: 4413 add r3, r2 80043ca: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 80043cc: 7bfb ldrb r3, [r7, #15] 80043ce: 3301 adds r3, #1 80043d0: 73fb strb r3, [r7, #15] 80043d2: 7bfa ldrb r2, [r7, #15] 80043d4: 78fb ldrb r3, [r7, #3] 80043d6: 3b01 subs r3, #1 80043d8: 429a cmp r2, r3 80043da: d3ec bcc.n 80043b6 } /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; 80043dc: 883b ldrh r3, [r7, #0] 80043de: 0418 lsls r0, r3, #16 80043e0: 687b ldr r3, [r7, #4] 80043e2: 6819 ldr r1, [r3, #0] 80043e4: 78fb ldrb r3, [r7, #3] 80043e6: 3b01 subs r3, #1 80043e8: 68ba ldr r2, [r7, #8] 80043ea: 4302 orrs r2, r0 80043ec: 3340 adds r3, #64 @ 0x40 80043ee: 009b lsls r3, r3, #2 80043f0: 440b add r3, r1 80043f2: 605a str r2, [r3, #4] } return HAL_OK; 80043f4: 2300 movs r3, #0 } 80043f6: 4618 mov r0, r3 80043f8: 3714 adds r7, #20 80043fa: 46bd mov sp, r7 80043fc: f85d 7b04 ldr.w r7, [sp], #4 8004400: 4770 bx lr 08004402 : * @param hpcd PCD handle * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { 8004402: b480 push {r7} 8004404: b083 sub sp, #12 8004406: af00 add r7, sp, #0 8004408: 6078 str r0, [r7, #4] 800440a: 460b mov r3, r1 800440c: 807b strh r3, [r7, #2] hpcd->Instance->GRXFSIZ = size; 800440e: 687b ldr r3, [r7, #4] 8004410: 681b ldr r3, [r3, #0] 8004412: 887a ldrh r2, [r7, #2] 8004414: 625a str r2, [r3, #36] @ 0x24 return HAL_OK; 8004416: 2300 movs r3, #0 } 8004418: 4618 mov r0, r3 800441a: 370c adds r7, #12 800441c: 46bd mov sp, r7 800441e: f85d 7b04 ldr.w r7, [sp], #4 8004422: 4770 bx lr 08004424 : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 8004424: b480 push {r7} 8004426: b085 sub sp, #20 8004428: af00 add r7, sp, #0 800442a: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 800442c: 687b ldr r3, [r7, #4] 800442e: 681b ldr r3, [r3, #0] 8004430: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 8004432: 687b ldr r3, [r7, #4] 8004434: 2201 movs r2, #1 8004436: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8 hpcd->LPM_State = LPM_L0; 800443a: 687b ldr r3, [r7, #4] 800443c: 2200 movs r2, #0 800443e: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 8004442: 68fb ldr r3, [r7, #12] 8004444: 699b ldr r3, [r3, #24] 8004446: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 800444a: 68fb ldr r3, [r7, #12] 800444c: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 800444e: 68fb ldr r3, [r7, #12] 8004450: 6d5b ldr r3, [r3, #84] @ 0x54 8004452: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004456: f043 0303 orr.w r3, r3, #3 800445a: 68fa ldr r2, [r7, #12] 800445c: 6553 str r3, [r2, #84] @ 0x54 return HAL_OK; 800445e: 2300 movs r3, #0 } 8004460: 4618 mov r0, r3 8004462: 3714 adds r7, #20 8004464: 46bd mov sp, r7 8004466: f85d 7b04 ldr.w r7, [sp], #4 800446a: 4770 bx lr 0800446c : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800446c: b580 push {r7, lr} 800446e: b084 sub sp, #16 8004470: af00 add r7, sp, #0 8004472: 6078 str r0, [r7, #4] 8004474: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8004476: 687b ldr r3, [r7, #4] 8004478: 2b00 cmp r3, #0 800447a: d101 bne.n 8004480 { return HAL_ERROR; 800447c: 2301 movs r3, #1 800447e: e0cc b.n 800461a /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8004480: 4b68 ldr r3, [pc, #416] @ (8004624 ) 8004482: 681b ldr r3, [r3, #0] 8004484: f003 030f and.w r3, r3, #15 8004488: 683a ldr r2, [r7, #0] 800448a: 429a cmp r2, r3 800448c: d90c bls.n 80044a8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800448e: 4b65 ldr r3, [pc, #404] @ (8004624 ) 8004490: 683a ldr r2, [r7, #0] 8004492: b2d2 uxtb r2, r2 8004494: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004496: 4b63 ldr r3, [pc, #396] @ (8004624 ) 8004498: 681b ldr r3, [r3, #0] 800449a: f003 030f and.w r3, r3, #15 800449e: 683a ldr r2, [r7, #0] 80044a0: 429a cmp r2, r3 80044a2: d001 beq.n 80044a8 { return HAL_ERROR; 80044a4: 2301 movs r3, #1 80044a6: e0b8 b.n 800461a } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80044a8: 687b ldr r3, [r7, #4] 80044aa: 681b ldr r3, [r3, #0] 80044ac: f003 0302 and.w r3, r3, #2 80044b0: 2b00 cmp r3, #0 80044b2: d020 beq.n 80044f6 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80044b4: 687b ldr r3, [r7, #4] 80044b6: 681b ldr r3, [r3, #0] 80044b8: f003 0304 and.w r3, r3, #4 80044bc: 2b00 cmp r3, #0 80044be: d005 beq.n 80044cc { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 80044c0: 4b59 ldr r3, [pc, #356] @ (8004628 ) 80044c2: 689b ldr r3, [r3, #8] 80044c4: 4a58 ldr r2, [pc, #352] @ (8004628 ) 80044c6: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 80044ca: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80044cc: 687b ldr r3, [r7, #4] 80044ce: 681b ldr r3, [r3, #0] 80044d0: f003 0308 and.w r3, r3, #8 80044d4: 2b00 cmp r3, #0 80044d6: d005 beq.n 80044e4 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 80044d8: 4b53 ldr r3, [pc, #332] @ (8004628 ) 80044da: 689b ldr r3, [r3, #8] 80044dc: 4a52 ldr r2, [pc, #328] @ (8004628 ) 80044de: f443 4360 orr.w r3, r3, #57344 @ 0xe000 80044e2: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80044e4: 4b50 ldr r3, [pc, #320] @ (8004628 ) 80044e6: 689b ldr r3, [r3, #8] 80044e8: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80044ec: 687b ldr r3, [r7, #4] 80044ee: 689b ldr r3, [r3, #8] 80044f0: 494d ldr r1, [pc, #308] @ (8004628 ) 80044f2: 4313 orrs r3, r2 80044f4: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80044f6: 687b ldr r3, [r7, #4] 80044f8: 681b ldr r3, [r3, #0] 80044fa: f003 0301 and.w r3, r3, #1 80044fe: 2b00 cmp r3, #0 8004500: d044 beq.n 800458c { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004502: 687b ldr r3, [r7, #4] 8004504: 685b ldr r3, [r3, #4] 8004506: 2b01 cmp r3, #1 8004508: d107 bne.n 800451a { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800450a: 4b47 ldr r3, [pc, #284] @ (8004628 ) 800450c: 681b ldr r3, [r3, #0] 800450e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004512: 2b00 cmp r3, #0 8004514: d119 bne.n 800454a { return HAL_ERROR; 8004516: 2301 movs r3, #1 8004518: e07f b.n 800461a } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 800451a: 687b ldr r3, [r7, #4] 800451c: 685b ldr r3, [r3, #4] 800451e: 2b02 cmp r3, #2 8004520: d003 beq.n 800452a (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 8004522: 687b ldr r3, [r7, #4] 8004524: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 8004526: 2b03 cmp r3, #3 8004528: d107 bne.n 800453a { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800452a: 4b3f ldr r3, [pc, #252] @ (8004628 ) 800452c: 681b ldr r3, [r3, #0] 800452e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004532: 2b00 cmp r3, #0 8004534: d109 bne.n 800454a { return HAL_ERROR; 8004536: 2301 movs r3, #1 8004538: e06f b.n 800461a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800453a: 4b3b ldr r3, [pc, #236] @ (8004628 ) 800453c: 681b ldr r3, [r3, #0] 800453e: f003 0302 and.w r3, r3, #2 8004542: 2b00 cmp r3, #0 8004544: d101 bne.n 800454a { return HAL_ERROR; 8004546: 2301 movs r3, #1 8004548: e067 b.n 800461a } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 800454a: 4b37 ldr r3, [pc, #220] @ (8004628 ) 800454c: 689b ldr r3, [r3, #8] 800454e: f023 0203 bic.w r2, r3, #3 8004552: 687b ldr r3, [r7, #4] 8004554: 685b ldr r3, [r3, #4] 8004556: 4934 ldr r1, [pc, #208] @ (8004628 ) 8004558: 4313 orrs r3, r2 800455a: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 800455c: f7fd fcb2 bl 8001ec4 8004560: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004562: e00a b.n 800457a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8004564: f7fd fcae bl 8001ec4 8004568: 4602 mov r2, r0 800456a: 68fb ldr r3, [r7, #12] 800456c: 1ad3 subs r3, r2, r3 800456e: f241 3288 movw r2, #5000 @ 0x1388 8004572: 4293 cmp r3, r2 8004574: d901 bls.n 800457a { return HAL_TIMEOUT; 8004576: 2303 movs r3, #3 8004578: e04f b.n 800461a while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800457a: 4b2b ldr r3, [pc, #172] @ (8004628 ) 800457c: 689b ldr r3, [r3, #8] 800457e: f003 020c and.w r2, r3, #12 8004582: 687b ldr r3, [r7, #4] 8004584: 685b ldr r3, [r3, #4] 8004586: 009b lsls r3, r3, #2 8004588: 429a cmp r2, r3 800458a: d1eb bne.n 8004564 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800458c: 4b25 ldr r3, [pc, #148] @ (8004624 ) 800458e: 681b ldr r3, [r3, #0] 8004590: f003 030f and.w r3, r3, #15 8004594: 683a ldr r2, [r7, #0] 8004596: 429a cmp r2, r3 8004598: d20c bcs.n 80045b4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800459a: 4b22 ldr r3, [pc, #136] @ (8004624 ) 800459c: 683a ldr r2, [r7, #0] 800459e: b2d2 uxtb r2, r2 80045a0: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80045a2: 4b20 ldr r3, [pc, #128] @ (8004624 ) 80045a4: 681b ldr r3, [r3, #0] 80045a6: f003 030f and.w r3, r3, #15 80045aa: 683a ldr r2, [r7, #0] 80045ac: 429a cmp r2, r3 80045ae: d001 beq.n 80045b4 { return HAL_ERROR; 80045b0: 2301 movs r3, #1 80045b2: e032 b.n 800461a } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80045b4: 687b ldr r3, [r7, #4] 80045b6: 681b ldr r3, [r3, #0] 80045b8: f003 0304 and.w r3, r3, #4 80045bc: 2b00 cmp r3, #0 80045be: d008 beq.n 80045d2 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80045c0: 4b19 ldr r3, [pc, #100] @ (8004628 ) 80045c2: 689b ldr r3, [r3, #8] 80045c4: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 80045c8: 687b ldr r3, [r7, #4] 80045ca: 68db ldr r3, [r3, #12] 80045cc: 4916 ldr r1, [pc, #88] @ (8004628 ) 80045ce: 4313 orrs r3, r2 80045d0: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80045d2: 687b ldr r3, [r7, #4] 80045d4: 681b ldr r3, [r3, #0] 80045d6: f003 0308 and.w r3, r3, #8 80045da: 2b00 cmp r3, #0 80045dc: d009 beq.n 80045f2 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 80045de: 4b12 ldr r3, [pc, #72] @ (8004628 ) 80045e0: 689b ldr r3, [r3, #8] 80045e2: f423 4260 bic.w r2, r3, #57344 @ 0xe000 80045e6: 687b ldr r3, [r7, #4] 80045e8: 691b ldr r3, [r3, #16] 80045ea: 00db lsls r3, r3, #3 80045ec: 490e ldr r1, [pc, #56] @ (8004628 ) 80045ee: 4313 orrs r3, r2 80045f0: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 80045f2: f000 fb7f bl 8004cf4 80045f6: 4602 mov r2, r0 80045f8: 4b0b ldr r3, [pc, #44] @ (8004628 ) 80045fa: 689b ldr r3, [r3, #8] 80045fc: 091b lsrs r3, r3, #4 80045fe: f003 030f and.w r3, r3, #15 8004602: 490a ldr r1, [pc, #40] @ (800462c ) 8004604: 5ccb ldrb r3, [r1, r3] 8004606: fa22 f303 lsr.w r3, r2, r3 800460a: 4a09 ldr r2, [pc, #36] @ (8004630 ) 800460c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); 800460e: 4b09 ldr r3, [pc, #36] @ (8004634 ) 8004610: 681b ldr r3, [r3, #0] 8004612: 4618 mov r0, r3 8004614: f7fd fc12 bl 8001e3c return HAL_OK; 8004618: 2300 movs r3, #0 } 800461a: 4618 mov r0, r3 800461c: 3710 adds r7, #16 800461e: 46bd mov sp, r7 8004620: bd80 pop {r7, pc} 8004622: bf00 nop 8004624: 40023c00 .word 0x40023c00 8004628: 40023800 .word 0x40023800 800462c: 0800b7d0 .word 0x0800b7d0 8004630: 20000090 .word 0x20000090 8004634: 20000094 .word 0x20000094 08004638 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8004638: b480 push {r7} 800463a: af00 add r7, sp, #0 return SystemCoreClock; 800463c: 4b03 ldr r3, [pc, #12] @ (800464c ) 800463e: 681b ldr r3, [r3, #0] } 8004640: 4618 mov r0, r3 8004642: 46bd mov sp, r7 8004644: f85d 7b04 ldr.w r7, [sp], #4 8004648: 4770 bx lr 800464a: bf00 nop 800464c: 20000090 .word 0x20000090 08004650 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8004650: b580 push {r7, lr} 8004652: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8004654: f7ff fff0 bl 8004638 8004658: 4602 mov r2, r0 800465a: 4b05 ldr r3, [pc, #20] @ (8004670 ) 800465c: 689b ldr r3, [r3, #8] 800465e: 0a9b lsrs r3, r3, #10 8004660: f003 0307 and.w r3, r3, #7 8004664: 4903 ldr r1, [pc, #12] @ (8004674 ) 8004666: 5ccb ldrb r3, [r1, r3] 8004668: fa22 f303 lsr.w r3, r2, r3 } 800466c: 4618 mov r0, r3 800466e: bd80 pop {r7, pc} 8004670: 40023800 .word 0x40023800 8004674: 0800b7e0 .word 0x0800b7e0 08004678 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8004678: b580 push {r7, lr} 800467a: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 800467c: f7ff ffdc bl 8004638 8004680: 4602 mov r2, r0 8004682: 4b05 ldr r3, [pc, #20] @ (8004698 ) 8004684: 689b ldr r3, [r3, #8] 8004686: 0b5b lsrs r3, r3, #13 8004688: f003 0307 and.w r3, r3, #7 800468c: 4903 ldr r1, [pc, #12] @ (800469c ) 800468e: 5ccb ldrb r3, [r1, r3] 8004690: fa22 f303 lsr.w r3, r2, r3 } 8004694: 4618 mov r0, r3 8004696: bd80 pop {r7, pc} 8004698: 40023800 .word 0x40023800 800469c: 0800b7e0 .word 0x0800b7e0 080046a0 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80046a0: b580 push {r7, lr} 80046a2: b08c sub sp, #48 @ 0x30 80046a4: af00 add r7, sp, #0 80046a6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80046a8: 2300 movs r3, #0 80046aa: 627b str r3, [r7, #36] @ 0x24 uint32_t tmpreg1 = 0U; 80046ac: 2300 movs r3, #0 80046ae: 623b str r3, [r7, #32] uint32_t plli2sp = 0U; 80046b0: 2300 movs r3, #0 80046b2: 61fb str r3, [r7, #28] uint32_t plli2sq = 0U; 80046b4: 2300 movs r3, #0 80046b6: 61bb str r3, [r7, #24] uint32_t plli2sr = 0U; 80046b8: 2300 movs r3, #0 80046ba: 617b str r3, [r7, #20] uint32_t pllsaip = 0U; 80046bc: 2300 movs r3, #0 80046be: 613b str r3, [r7, #16] uint32_t pllsaiq = 0U; 80046c0: 2300 movs r3, #0 80046c2: 60fb str r3, [r7, #12] uint32_t plli2sused = 0U; 80046c4: 2300 movs r3, #0 80046c6: 62fb str r3, [r7, #44] @ 0x2c uint32_t pllsaiused = 0U; 80046c8: 2300 movs r3, #0 80046ca: 62bb str r3, [r7, #40] @ 0x28 /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------ I2S APB1 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) 80046cc: 687b ldr r3, [r7, #4] 80046ce: 681b ldr r3, [r3, #0] 80046d0: f003 0301 and.w r3, r3, #1 80046d4: 2b00 cmp r3, #0 80046d6: d010 beq.n 80046fa { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); 80046d8: 4b6f ldr r3, [pc, #444] @ (8004898 ) 80046da: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80046de: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000 80046e2: 687b ldr r3, [r7, #4] 80046e4: 6b9b ldr r3, [r3, #56] @ 0x38 80046e6: 496c ldr r1, [pc, #432] @ (8004898 ) 80046e8: 4313 orrs r3, r2 80046ea: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) 80046ee: 687b ldr r3, [r7, #4] 80046f0: 6b9b ldr r3, [r3, #56] @ 0x38 80046f2: 2b00 cmp r3, #0 80046f4: d101 bne.n 80046fa { plli2sused = 1U; 80046f6: 2301 movs r3, #1 80046f8: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*---------------------------- I2S APB2 configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) 80046fa: 687b ldr r3, [r7, #4] 80046fc: 681b ldr r3, [r3, #0] 80046fe: f003 0302 and.w r3, r3, #2 8004702: 2b00 cmp r3, #0 8004704: d010 beq.n 8004728 { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); 8004706: 4b64 ldr r3, [pc, #400] @ (8004898 ) 8004708: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800470c: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000 8004710: 687b ldr r3, [r7, #4] 8004712: 6bdb ldr r3, [r3, #60] @ 0x3c 8004714: 4960 ldr r1, [pc, #384] @ (8004898 ) 8004716: 4313 orrs r3, r2 8004718: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) 800471c: 687b ldr r3, [r7, #4] 800471e: 6bdb ldr r3, [r3, #60] @ 0x3c 8004720: 2b00 cmp r3, #0 8004722: d101 bne.n 8004728 { plli2sused = 1U; 8004724: 2301 movs r3, #1 8004726: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*--------------------------- SAI1 configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) 8004728: 687b ldr r3, [r7, #4] 800472a: 681b ldr r3, [r3, #0] 800472c: f003 0304 and.w r3, r3, #4 8004730: 2b00 cmp r3, #0 8004732: d017 beq.n 8004764 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8004734: 4b58 ldr r3, [pc, #352] @ (8004898 ) 8004736: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800473a: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 800473e: 687b ldr r3, [r7, #4] 8004740: 6b1b ldr r3, [r3, #48] @ 0x30 8004742: 4955 ldr r1, [pc, #340] @ (8004898 ) 8004744: 4313 orrs r3, r2 8004746: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) 800474a: 687b ldr r3, [r7, #4] 800474c: 6b1b ldr r3, [r3, #48] @ 0x30 800474e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8004752: d101 bne.n 8004758 { plli2sused = 1U; 8004754: 2301 movs r3, #1 8004756: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) 8004758: 687b ldr r3, [r7, #4] 800475a: 6b1b ldr r3, [r3, #48] @ 0x30 800475c: 2b00 cmp r3, #0 800475e: d101 bne.n 8004764 { pllsaiused = 1U; 8004760: 2301 movs r3, #1 8004762: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*-------------------------- SAI2 configuration ----------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) 8004764: 687b ldr r3, [r7, #4] 8004766: 681b ldr r3, [r3, #0] 8004768: f003 0308 and.w r3, r3, #8 800476c: 2b00 cmp r3, #0 800476e: d017 beq.n 80047a0 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 8004770: 4b49 ldr r3, [pc, #292] @ (8004898 ) 8004772: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004776: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 800477a: 687b ldr r3, [r7, #4] 800477c: 6b5b ldr r3, [r3, #52] @ 0x34 800477e: 4946 ldr r1, [pc, #280] @ (8004898 ) 8004780: 4313 orrs r3, r2 8004782: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) 8004786: 687b ldr r3, [r7, #4] 8004788: 6b5b ldr r3, [r3, #52] @ 0x34 800478a: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800478e: d101 bne.n 8004794 { plli2sused = 1U; 8004790: 2301 movs r3, #1 8004792: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) 8004794: 687b ldr r3, [r7, #4] 8004796: 6b5b ldr r3, [r3, #52] @ 0x34 8004798: 2b00 cmp r3, #0 800479a: d101 bne.n 80047a0 { pllsaiused = 1U; 800479c: 2301 movs r3, #1 800479e: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- RTC configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 80047a0: 687b ldr r3, [r7, #4] 80047a2: 681b ldr r3, [r3, #0] 80047a4: f003 0320 and.w r3, r3, #32 80047a8: 2b00 cmp r3, #0 80047aa: f000 808a beq.w 80048c2 { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 80047ae: 2300 movs r3, #0 80047b0: 60bb str r3, [r7, #8] 80047b2: 4b39 ldr r3, [pc, #228] @ (8004898 ) 80047b4: 6c1b ldr r3, [r3, #64] @ 0x40 80047b6: 4a38 ldr r2, [pc, #224] @ (8004898 ) 80047b8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80047bc: 6413 str r3, [r2, #64] @ 0x40 80047be: 4b36 ldr r3, [pc, #216] @ (8004898 ) 80047c0: 6c1b ldr r3, [r3, #64] @ 0x40 80047c2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80047c6: 60bb str r3, [r7, #8] 80047c8: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; 80047ca: 4b34 ldr r3, [pc, #208] @ (800489c ) 80047cc: 681b ldr r3, [r3, #0] 80047ce: 4a33 ldr r2, [pc, #204] @ (800489c ) 80047d0: f443 7380 orr.w r3, r3, #256 @ 0x100 80047d4: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 80047d6: f7fd fb75 bl 8001ec4 80047da: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR & PWR_CR_DBP) == RESET) 80047dc: e008 b.n 80047f0 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80047de: f7fd fb71 bl 8001ec4 80047e2: 4602 mov r2, r0 80047e4: 6a7b ldr r3, [r7, #36] @ 0x24 80047e6: 1ad3 subs r3, r2, r3 80047e8: 2b02 cmp r3, #2 80047ea: d901 bls.n 80047f0 { return HAL_TIMEOUT; 80047ec: 2303 movs r3, #3 80047ee: e278 b.n 8004ce2 while ((PWR->CR & PWR_CR_DBP) == RESET) 80047f0: 4b2a ldr r3, [pc, #168] @ (800489c ) 80047f2: 681b ldr r3, [r3, #0] 80047f4: f403 7380 and.w r3, r3, #256 @ 0x100 80047f8: 2b00 cmp r3, #0 80047fa: d0f0 beq.n 80047de } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); 80047fc: 4b26 ldr r3, [pc, #152] @ (8004898 ) 80047fe: 6f1b ldr r3, [r3, #112] @ 0x70 8004800: f403 7340 and.w r3, r3, #768 @ 0x300 8004804: 623b str r3, [r7, #32] if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8004806: 6a3b ldr r3, [r7, #32] 8004808: 2b00 cmp r3, #0 800480a: d02f beq.n 800486c 800480c: 687b ldr r3, [r7, #4] 800480e: 6c1b ldr r3, [r3, #64] @ 0x40 8004810: f403 7340 and.w r3, r3, #768 @ 0x300 8004814: 6a3a ldr r2, [r7, #32] 8004816: 429a cmp r2, r3 8004818: d028 beq.n 800486c { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800481a: 4b1f ldr r3, [pc, #124] @ (8004898 ) 800481c: 6f1b ldr r3, [r3, #112] @ 0x70 800481e: f423 7340 bic.w r3, r3, #768 @ 0x300 8004822: 623b str r3, [r7, #32] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8004824: 4b1e ldr r3, [pc, #120] @ (80048a0 ) 8004826: 2201 movs r2, #1 8004828: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 800482a: 4b1d ldr r3, [pc, #116] @ (80048a0 ) 800482c: 2200 movs r2, #0 800482e: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; 8004830: 4a19 ldr r2, [pc, #100] @ (8004898 ) 8004832: 6a3b ldr r3, [r7, #32] 8004834: 6713 str r3, [r2, #112] @ 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 8004836: 4b18 ldr r3, [pc, #96] @ (8004898 ) 8004838: 6f1b ldr r3, [r3, #112] @ 0x70 800483a: f003 0301 and.w r3, r3, #1 800483e: 2b01 cmp r3, #1 8004840: d114 bne.n 800486c { /* Get tick */ tickstart = HAL_GetTick(); 8004842: f7fd fb3f bl 8001ec4 8004846: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004848: e00a b.n 8004860 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800484a: f7fd fb3b bl 8001ec4 800484e: 4602 mov r2, r0 8004850: 6a7b ldr r3, [r7, #36] @ 0x24 8004852: 1ad3 subs r3, r2, r3 8004854: f241 3288 movw r2, #5000 @ 0x1388 8004858: 4293 cmp r3, r2 800485a: d901 bls.n 8004860 { return HAL_TIMEOUT; 800485c: 2303 movs r3, #3 800485e: e240 b.n 8004ce2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004860: 4b0d ldr r3, [pc, #52] @ (8004898 ) 8004862: 6f1b ldr r3, [r3, #112] @ 0x70 8004864: f003 0302 and.w r3, r3, #2 8004868: 2b00 cmp r3, #0 800486a: d0ee beq.n 800484a } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800486c: 687b ldr r3, [r7, #4] 800486e: 6c1b ldr r3, [r3, #64] @ 0x40 8004870: f403 7340 and.w r3, r3, #768 @ 0x300 8004874: f5b3 7f40 cmp.w r3, #768 @ 0x300 8004878: d114 bne.n 80048a4 800487a: 4b07 ldr r3, [pc, #28] @ (8004898 ) 800487c: 689b ldr r3, [r3, #8] 800487e: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000 8004882: 687b ldr r3, [r7, #4] 8004884: 6c1b ldr r3, [r3, #64] @ 0x40 8004886: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 800488a: f423 7340 bic.w r3, r3, #768 @ 0x300 800488e: 4902 ldr r1, [pc, #8] @ (8004898 ) 8004890: 4313 orrs r3, r2 8004892: 608b str r3, [r1, #8] 8004894: e00c b.n 80048b0 8004896: bf00 nop 8004898: 40023800 .word 0x40023800 800489c: 40007000 .word 0x40007000 80048a0: 42470e40 .word 0x42470e40 80048a4: 4b4a ldr r3, [pc, #296] @ (80049d0 ) 80048a6: 689b ldr r3, [r3, #8] 80048a8: 4a49 ldr r2, [pc, #292] @ (80049d0 ) 80048aa: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000 80048ae: 6093 str r3, [r2, #8] 80048b0: 4b47 ldr r3, [pc, #284] @ (80049d0 ) 80048b2: 6f1a ldr r2, [r3, #112] @ 0x70 80048b4: 687b ldr r3, [r7, #4] 80048b6: 6c1b ldr r3, [r3, #64] @ 0x40 80048b8: f3c3 030b ubfx r3, r3, #0, #12 80048bc: 4944 ldr r1, [pc, #272] @ (80049d0 ) 80048be: 4313 orrs r3, r2 80048c0: 670b str r3, [r1, #112] @ 0x70 } /*--------------------------------------------------------------------------*/ /*---------------------------- TIM configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 80048c2: 687b ldr r3, [r7, #4] 80048c4: 681b ldr r3, [r3, #0] 80048c6: f003 0310 and.w r3, r3, #16 80048ca: 2b00 cmp r3, #0 80048cc: d004 beq.n 80048d8 { /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 80048ce: 687b ldr r3, [r7, #4] 80048d0: f893 2058 ldrb.w r2, [r3, #88] @ 0x58 80048d4: 4b3f ldr r3, [pc, #252] @ (80049d4 ) 80048d6: 601a str r2, [r3, #0] } /*--------------------------------------------------------------------------*/ /*---------------------------- FMPI2C1 Configuration -----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) 80048d8: 687b ldr r3, [r7, #4] 80048da: 681b ldr r3, [r3, #0] 80048dc: f003 0380 and.w r3, r3, #128 @ 0x80 80048e0: 2b00 cmp r3, #0 80048e2: d00a beq.n 80048fa { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); 80048e4: 4b3a ldr r3, [pc, #232] @ (80049d0 ) 80048e6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80048ea: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 80048ee: 687b ldr r3, [r7, #4] 80048f0: 6cdb ldr r3, [r3, #76] @ 0x4c 80048f2: 4937 ldr r1, [pc, #220] @ (80049d0 ) 80048f4: 4313 orrs r3, r2 80048f6: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ CEC Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 80048fa: 687b ldr r3, [r7, #4] 80048fc: 681b ldr r3, [r3, #0] 80048fe: f003 0340 and.w r3, r3, #64 @ 0x40 8004902: 2b00 cmp r3, #0 8004904: d00a beq.n 800491c { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 8004906: 4b32 ldr r3, [pc, #200] @ (80049d0 ) 8004908: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800490c: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000 8004910: 687b ldr r3, [r7, #4] 8004912: 6c9b ldr r3, [r3, #72] @ 0x48 8004914: 492e ldr r1, [pc, #184] @ (80049d0 ) 8004916: 4313 orrs r3, r2 8004918: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*----------------------------- CLK48 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 800491c: 687b ldr r3, [r7, #4] 800491e: 681b ldr r3, [r3, #0] 8004920: f403 7380 and.w r3, r3, #256 @ 0x100 8004924: 2b00 cmp r3, #0 8004926: d011 beq.n 800494c { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); 8004928: 4b29 ldr r3, [pc, #164] @ (80049d0 ) 800492a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800492e: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000 8004932: 687b ldr r3, [r7, #4] 8004934: 6d5b ldr r3, [r3, #84] @ 0x54 8004936: 4926 ldr r1, [pc, #152] @ (80049d0 ) 8004938: 4313 orrs r3, r2 800493a: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLSAI when it's used as clock source for CLK48 */ if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) 800493e: 687b ldr r3, [r7, #4] 8004940: 6d5b ldr r3, [r3, #84] @ 0x54 8004942: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8004946: d101 bne.n 800494c { pllsaiused = 1U; 8004948: 2301 movs r3, #1 800494a: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- SDIO Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) 800494c: 687b ldr r3, [r7, #4] 800494e: 681b ldr r3, [r3, #0] 8004950: f403 7300 and.w r3, r3, #512 @ 0x200 8004954: 2b00 cmp r3, #0 8004956: d00a beq.n 800496e { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); 8004958: 4b1d ldr r3, [pc, #116] @ (80049d0 ) 800495a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800495e: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000 8004962: 687b ldr r3, [r7, #4] 8004964: 6c5b ldr r3, [r3, #68] @ 0x44 8004966: 491a ldr r1, [pc, #104] @ (80049d0 ) 8004968: 4313 orrs r3, r2 800496a: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ SPDIFRX Configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 800496e: 687b ldr r3, [r7, #4] 8004970: 681b ldr r3, [r3, #0] 8004972: f403 6380 and.w r3, r3, #1024 @ 0x400 8004976: 2b00 cmp r3, #0 8004978: d011 beq.n 800499e { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); /* Configure the SPDIFRX clock source */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); 800497a: 4b15 ldr r3, [pc, #84] @ (80049d0 ) 800497c: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004980: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000 8004984: 687b ldr r3, [r7, #4] 8004986: 6d1b ldr r3, [r3, #80] @ 0x50 8004988: 4911 ldr r1, [pc, #68] @ (80049d0 ) 800498a: 4313 orrs r3, r2 800498c: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) 8004990: 687b ldr r3, [r7, #4] 8004992: 6d1b ldr r3, [r3, #80] @ 0x50 8004994: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004998: d101 bne.n 800499e { plli2sused = 1U; 800499a: 2301 movs r3, #1 800499c: 62fb str r3, [r7, #44] @ 0x2c /*--------------------------------------------------------------------------*/ /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) 800499e: 6afb ldr r3, [r7, #44] @ 0x2c 80049a0: 2b01 cmp r3, #1 80049a2: d005 beq.n 80049b0 80049a4: 687b ldr r3, [r7, #4] 80049a6: 681b ldr r3, [r3, #0] 80049a8: f5b3 6f00 cmp.w r3, #2048 @ 0x800 80049ac: f040 80ff bne.w 8004bae { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 80049b0: 4b09 ldr r3, [pc, #36] @ (80049d8 ) 80049b2: 2200 movs r2, #0 80049b4: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80049b6: f7fd fa85 bl 8001ec4 80049ba: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 80049bc: e00e b.n 80049dc { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 80049be: f7fd fa81 bl 8001ec4 80049c2: 4602 mov r2, r0 80049c4: 6a7b ldr r3, [r7, #36] @ 0x24 80049c6: 1ad3 subs r3, r2, r3 80049c8: 2b02 cmp r3, #2 80049ca: d907 bls.n 80049dc { /* return in case of Timeout detected */ return HAL_TIMEOUT; 80049cc: 2303 movs r3, #3 80049ce: e188 b.n 8004ce2 80049d0: 40023800 .word 0x40023800 80049d4: 424711e0 .word 0x424711e0 80049d8: 42470068 .word 0x42470068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 80049dc: 4b7e ldr r3, [pc, #504] @ (8004bd8 ) 80049de: 681b ldr r3, [r3, #0] 80049e0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80049e4: 2b00 cmp r3, #0 80049e6: d1ea bne.n 80049be /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) 80049e8: 687b ldr r3, [r7, #4] 80049ea: 681b ldr r3, [r3, #0] 80049ec: f003 0301 and.w r3, r3, #1 80049f0: 2b00 cmp r3, #0 80049f2: d003 beq.n 80049fc && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 80049f4: 687b ldr r3, [r7, #4] 80049f6: 6b9b ldr r3, [r3, #56] @ 0x38 80049f8: 2b00 cmp r3, #0 80049fa: d009 beq.n 8004a10 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 80049fc: 687b ldr r3, [r7, #4] 80049fe: 681b ldr r3, [r3, #0] 8004a00: f003 0302 and.w r3, r3, #2 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8004a04: 2b00 cmp r3, #0 8004a06: d028 beq.n 8004a5a ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 8004a08: 687b ldr r3, [r7, #4] 8004a0a: 6bdb ldr r3, [r3, #60] @ 0x3c 8004a0c: 2b00 cmp r3, #0 8004a0e: d124 bne.n 8004a5a { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004a10: 4b71 ldr r3, [pc, #452] @ (8004bd8 ) 8004a12: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004a16: 0c1b lsrs r3, r3, #16 8004a18: f003 0303 and.w r3, r3, #3 8004a1c: 3301 adds r3, #1 8004a1e: 005b lsls r3, r3, #1 8004a20: 61fb str r3, [r7, #28] plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); 8004a22: 4b6d ldr r3, [pc, #436] @ (8004bd8 ) 8004a24: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004a28: 0e1b lsrs r3, r3, #24 8004a2a: f003 030f and.w r3, r3, #15 8004a2e: 61bb str r3, [r7, #24] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq, 8004a30: 687b ldr r3, [r7, #4] 8004a32: 685a ldr r2, [r3, #4] 8004a34: 687b ldr r3, [r7, #4] 8004a36: 689b ldr r3, [r3, #8] 8004a38: 019b lsls r3, r3, #6 8004a3a: 431a orrs r2, r3 8004a3c: 69fb ldr r3, [r7, #28] 8004a3e: 085b lsrs r3, r3, #1 8004a40: 3b01 subs r3, #1 8004a42: 041b lsls r3, r3, #16 8004a44: 431a orrs r2, r3 8004a46: 69bb ldr r3, [r7, #24] 8004a48: 061b lsls r3, r3, #24 8004a4a: 431a orrs r2, r3 8004a4c: 687b ldr r3, [r7, #4] 8004a4e: 695b ldr r3, [r3, #20] 8004a50: 071b lsls r3, r3, #28 8004a52: 4961 ldr r1, [pc, #388] @ (8004bd8 ) 8004a54: 4313 orrs r3, r2 8004a56: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SR); } /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8004a5a: 687b ldr r3, [r7, #4] 8004a5c: 681b ldr r3, [r3, #0] 8004a5e: f003 0304 and.w r3, r3, #4 8004a62: 2b00 cmp r3, #0 8004a64: d004 beq.n 8004a70 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 8004a66: 687b ldr r3, [r7, #4] 8004a68: 6b1b ldr r3, [r3, #48] @ 0x30 8004a6a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8004a6e: d00a beq.n 8004a86 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8004a70: 687b ldr r3, [r7, #4] 8004a72: 681b ldr r3, [r3, #0] 8004a74: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 8004a78: 2b00 cmp r3, #0 8004a7a: d035 beq.n 8004ae8 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8004a7c: 687b ldr r3, [r7, #4] 8004a7e: 6b5b ldr r3, [r3, #52] @ 0x34 8004a80: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004a84: d130 bne.n 8004ae8 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004a86: 4b54 ldr r3, [pc, #336] @ (8004bd8 ) 8004a88: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004a8c: 0c1b lsrs r3, r3, #16 8004a8e: f003 0303 and.w r3, r3, #3 8004a92: 3301 adds r3, #1 8004a94: 005b lsls r3, r3, #1 8004a96: 61fb str r3, [r7, #28] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004a98: 4b4f ldr r3, [pc, #316] @ (8004bd8 ) 8004a9a: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004a9e: 0f1b lsrs r3, r3, #28 8004aa0: f003 0307 and.w r3, r3, #7 8004aa4: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, 8004aa6: 687b ldr r3, [r7, #4] 8004aa8: 685a ldr r2, [r3, #4] 8004aaa: 687b ldr r3, [r7, #4] 8004aac: 689b ldr r3, [r3, #8] 8004aae: 019b lsls r3, r3, #6 8004ab0: 431a orrs r2, r3 8004ab2: 69fb ldr r3, [r7, #28] 8004ab4: 085b lsrs r3, r3, #1 8004ab6: 3b01 subs r3, #1 8004ab8: 041b lsls r3, r3, #16 8004aba: 431a orrs r2, r3 8004abc: 687b ldr r3, [r7, #4] 8004abe: 691b ldr r3, [r3, #16] 8004ac0: 061b lsls r3, r3, #24 8004ac2: 431a orrs r2, r3 8004ac4: 697b ldr r3, [r7, #20] 8004ac6: 071b lsls r3, r3, #28 8004ac8: 4943 ldr r1, [pc, #268] @ (8004bd8 ) 8004aca: 4313 orrs r3, r2 8004acc: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 8004ad0: 4b41 ldr r3, [pc, #260] @ (8004bd8 ) 8004ad2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004ad6: f023 021f bic.w r2, r3, #31 8004ada: 687b ldr r3, [r7, #4] 8004adc: 6a9b ldr r3, [r3, #40] @ 0x28 8004ade: 3b01 subs r3, #1 8004ae0: 493d ldr r1, [pc, #244] @ (8004bd8 ) 8004ae2: 4313 orrs r3, r2 8004ae4: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8004ae8: 687b ldr r3, [r7, #4] 8004aea: 681b ldr r3, [r3, #0] 8004aec: f403 6380 and.w r3, r3, #1024 @ 0x400 8004af0: 2b00 cmp r3, #0 8004af2: d029 beq.n 8004b48 && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 8004af4: 687b ldr r3, [r7, #4] 8004af6: 6d1b ldr r3, [r3, #80] @ 0x50 8004af8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004afc: d124 bne.n 8004b48 { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004afe: 4b36 ldr r3, [pc, #216] @ (8004bd8 ) 8004b00: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004b04: 0c1b lsrs r3, r3, #16 8004b06: f003 0303 and.w r3, r3, #3 8004b0a: 3301 adds r3, #1 8004b0c: 005b lsls r3, r3, #1 8004b0e: 61bb str r3, [r7, #24] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004b10: 4b31 ldr r3, [pc, #196] @ (8004bd8 ) 8004b12: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004b16: 0f1b lsrs r3, r3, #28 8004b18: f003 0307 and.w r3, r3, #7 8004b1c: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 8004b1e: 687b ldr r3, [r7, #4] 8004b20: 685a ldr r2, [r3, #4] 8004b22: 687b ldr r3, [r7, #4] 8004b24: 689b ldr r3, [r3, #8] 8004b26: 019b lsls r3, r3, #6 8004b28: 431a orrs r2, r3 8004b2a: 687b ldr r3, [r7, #4] 8004b2c: 68db ldr r3, [r3, #12] 8004b2e: 085b lsrs r3, r3, #1 8004b30: 3b01 subs r3, #1 8004b32: 041b lsls r3, r3, #16 8004b34: 431a orrs r2, r3 8004b36: 69bb ldr r3, [r7, #24] 8004b38: 061b lsls r3, r3, #24 8004b3a: 431a orrs r2, r3 8004b3c: 697b ldr r3, [r7, #20] 8004b3e: 071b lsls r3, r3, #28 8004b40: 4925 ldr r1, [pc, #148] @ (8004bd8 ) 8004b42: 4313 orrs r3, r2 8004b44: f8c1 3084 str.w r3, [r1, #132] @ 0x84 plli2sq, plli2sr); } /*----------------- In Case of PLLI2S is just selected -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 8004b48: 687b ldr r3, [r7, #4] 8004b4a: 681b ldr r3, [r3, #0] 8004b4c: f403 6300 and.w r3, r3, #2048 @ 0x800 8004b50: 2b00 cmp r3, #0 8004b52: d016 beq.n 8004b82 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 8004b54: 687b ldr r3, [r7, #4] 8004b56: 685a ldr r2, [r3, #4] 8004b58: 687b ldr r3, [r7, #4] 8004b5a: 689b ldr r3, [r3, #8] 8004b5c: 019b lsls r3, r3, #6 8004b5e: 431a orrs r2, r3 8004b60: 687b ldr r3, [r7, #4] 8004b62: 68db ldr r3, [r3, #12] 8004b64: 085b lsrs r3, r3, #1 8004b66: 3b01 subs r3, #1 8004b68: 041b lsls r3, r3, #16 8004b6a: 431a orrs r2, r3 8004b6c: 687b ldr r3, [r7, #4] 8004b6e: 691b ldr r3, [r3, #16] 8004b70: 061b lsls r3, r3, #24 8004b72: 431a orrs r2, r3 8004b74: 687b ldr r3, [r7, #4] 8004b76: 695b ldr r3, [r3, #20] 8004b78: 071b lsls r3, r3, #28 8004b7a: 4917 ldr r1, [pc, #92] @ (8004bd8 ) 8004b7c: 4313 orrs r3, r2 8004b7e: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 8004b82: 4b16 ldr r3, [pc, #88] @ (8004bdc ) 8004b84: 2201 movs r2, #1 8004b86: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004b88: f7fd f99c bl 8001ec4 8004b8c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004b8e: e008 b.n 8004ba2 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004b90: f7fd f998 bl 8001ec4 8004b94: 4602 mov r2, r0 8004b96: 6a7b ldr r3, [r7, #36] @ 0x24 8004b98: 1ad3 subs r3, r2, r3 8004b9a: 2b02 cmp r3, #2 8004b9c: d901 bls.n 8004ba2 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004b9e: 2303 movs r3, #3 8004ba0: e09f b.n 8004ce2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004ba2: 4b0d ldr r3, [pc, #52] @ (8004bd8 ) 8004ba4: 681b ldr r3, [r3, #0] 8004ba6: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004baa: 2b00 cmp r3, #0 8004bac: d0f0 beq.n 8004b90 } /*--------------------------------------------------------------------------*/ /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ if (pllsaiused == 1U) 8004bae: 6abb ldr r3, [r7, #40] @ 0x28 8004bb0: 2b01 cmp r3, #1 8004bb2: f040 8095 bne.w 8004ce0 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 8004bb6: 4b0a ldr r3, [pc, #40] @ (8004be0 ) 8004bb8: 2200 movs r2, #0 8004bba: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004bbc: f7fd f982 bl 8001ec4 8004bc0: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is disabled */ while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004bc2: e00f b.n 8004be4 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004bc4: f7fd f97e bl 8001ec4 8004bc8: 4602 mov r2, r0 8004bca: 6a7b ldr r3, [r7, #36] @ 0x24 8004bcc: 1ad3 subs r3, r2, r3 8004bce: 2b02 cmp r3, #2 8004bd0: d908 bls.n 8004be4 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004bd2: 2303 movs r3, #3 8004bd4: e085 b.n 8004ce2 8004bd6: bf00 nop 8004bd8: 40023800 .word 0x40023800 8004bdc: 42470068 .word 0x42470068 8004be0: 42470070 .word 0x42470070 while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004be4: 4b41 ldr r3, [pc, #260] @ (8004cec ) 8004be6: 681b ldr r3, [r3, #0] 8004be8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004bec: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004bf0: d0e8 beq.n 8004bc4 /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8004bf2: 687b ldr r3, [r7, #4] 8004bf4: 681b ldr r3, [r3, #0] 8004bf6: f003 0304 and.w r3, r3, #4 8004bfa: 2b00 cmp r3, #0 8004bfc: d003 beq.n 8004c06 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8004bfe: 687b ldr r3, [r7, #4] 8004c00: 6b1b ldr r3, [r3, #48] @ 0x30 8004c02: 2b00 cmp r3, #0 8004c04: d009 beq.n 8004c1a ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8004c06: 687b ldr r3, [r7, #4] 8004c08: 681b ldr r3, [r3, #0] 8004c0a: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8004c0e: 2b00 cmp r3, #0 8004c10: d02b beq.n 8004c6a ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8004c12: 687b ldr r3, [r7, #4] 8004c14: 6b5b ldr r3, [r3, #52] @ 0x34 8004c16: 2b00 cmp r3, #0 8004c18: d127 bne.n 8004c6a assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); 8004c1a: 4b34 ldr r3, [pc, #208] @ (8004cec ) 8004c1c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004c20: 0c1b lsrs r3, r3, #16 8004c22: f003 0303 and.w r3, r3, #3 8004c26: 3301 adds r3, #1 8004c28: 005b lsls r3, r3, #1 8004c2a: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, 8004c2c: 687b ldr r3, [r7, #4] 8004c2e: 699a ldr r2, [r3, #24] 8004c30: 687b ldr r3, [r7, #4] 8004c32: 69db ldr r3, [r3, #28] 8004c34: 019b lsls r3, r3, #6 8004c36: 431a orrs r2, r3 8004c38: 693b ldr r3, [r7, #16] 8004c3a: 085b lsrs r3, r3, #1 8004c3c: 3b01 subs r3, #1 8004c3e: 041b lsls r3, r3, #16 8004c40: 431a orrs r2, r3 8004c42: 687b ldr r3, [r7, #4] 8004c44: 6a5b ldr r3, [r3, #36] @ 0x24 8004c46: 061b lsls r3, r3, #24 8004c48: 4928 ldr r1, [pc, #160] @ (8004cec ) 8004c4a: 4313 orrs r3, r2 8004c4c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 PeriphClkInit->PLLSAI.PLLSAIQ, 0U); /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 8004c50: 4b26 ldr r3, [pc, #152] @ (8004cec ) 8004c52: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004c56: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 8004c5a: 687b ldr r3, [r7, #4] 8004c5c: 6adb ldr r3, [r3, #44] @ 0x2c 8004c5e: 3b01 subs r3, #1 8004c60: 021b lsls r3, r3, #8 8004c62: 4922 ldr r1, [pc, #136] @ (8004cec ) 8004c64: 4313 orrs r3, r2 8004c66: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ /* In Case of PLLI2S is selected as source clock for CLK48 */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 8004c6a: 687b ldr r3, [r7, #4] 8004c6c: 681b ldr r3, [r3, #0] 8004c6e: f403 7380 and.w r3, r3, #256 @ 0x100 8004c72: 2b00 cmp r3, #0 8004c74: d01d beq.n 8004cb2 && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) 8004c76: 687b ldr r3, [r7, #4] 8004c78: 6d5b ldr r3, [r3, #84] @ 0x54 8004c7a: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8004c7e: d118 bne.n 8004cb2 { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 8004c80: 4b1a ldr r3, [pc, #104] @ (8004cec ) 8004c82: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004c86: 0e1b lsrs r3, r3, #24 8004c88: f003 030f and.w r3, r3, #15 8004c8c: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, 8004c8e: 687b ldr r3, [r7, #4] 8004c90: 699a ldr r2, [r3, #24] 8004c92: 687b ldr r3, [r7, #4] 8004c94: 69db ldr r3, [r3, #28] 8004c96: 019b lsls r3, r3, #6 8004c98: 431a orrs r2, r3 8004c9a: 687b ldr r3, [r7, #4] 8004c9c: 6a1b ldr r3, [r3, #32] 8004c9e: 085b lsrs r3, r3, #1 8004ca0: 3b01 subs r3, #1 8004ca2: 041b lsls r3, r3, #16 8004ca4: 431a orrs r2, r3 8004ca6: 68fb ldr r3, [r7, #12] 8004ca8: 061b lsls r3, r3, #24 8004caa: 4910 ldr r1, [pc, #64] @ (8004cec ) 8004cac: 4313 orrs r3, r2 8004cae: f8c1 3088 str.w r3, [r1, #136] @ 0x88 pllsaiq, 0U); } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 8004cb2: 4b0f ldr r3, [pc, #60] @ (8004cf0 ) 8004cb4: 2201 movs r2, #1 8004cb6: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004cb8: f7fd f904 bl 8001ec4 8004cbc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is ready */ while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004cbe: e008 b.n 8004cd2 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004cc0: f7fd f900 bl 8001ec4 8004cc4: 4602 mov r2, r0 8004cc6: 6a7b ldr r3, [r7, #36] @ 0x24 8004cc8: 1ad3 subs r3, r2, r3 8004cca: 2b02 cmp r3, #2 8004ccc: d901 bls.n 8004cd2 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004cce: 2303 movs r3, #3 8004cd0: e007 b.n 8004ce2 while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004cd2: 4b06 ldr r3, [pc, #24] @ (8004cec ) 8004cd4: 681b ldr r3, [r3, #0] 8004cd6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004cda: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004cde: d1ef bne.n 8004cc0 } } } return HAL_OK; 8004ce0: 2300 movs r3, #0 } 8004ce2: 4618 mov r0, r3 8004ce4: 3730 adds r7, #48 @ 0x30 8004ce6: 46bd mov sp, r7 8004ce8: bd80 pop {r7, pc} 8004cea: bf00 nop 8004cec: 40023800 .word 0x40023800 8004cf0: 42470070 .word 0x42470070 08004cf4 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8004cf4: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8004cf8: b0ae sub sp, #184 @ 0xb8 8004cfa: af00 add r7, sp, #0 uint32_t pllm = 0U; 8004cfc: 2300 movs r3, #0 8004cfe: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t pllvco = 0U; 8004d02: 2300 movs r3, #0 8004d04: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t pllp = 0U; 8004d08: 2300 movs r3, #0 8004d0a: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 uint32_t pllr = 0U; 8004d0e: 2300 movs r3, #0 8004d10: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t sysclockfreq = 0U; 8004d14: 2300 movs r3, #0 8004d16: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8004d1a: 4bcb ldr r3, [pc, #812] @ (8005048 ) 8004d1c: 689b ldr r3, [r3, #8] 8004d1e: f003 030c and.w r3, r3, #12 8004d22: 2b0c cmp r3, #12 8004d24: f200 8206 bhi.w 8005134 8004d28: a201 add r2, pc, #4 @ (adr r2, 8004d30 ) 8004d2a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004d2e: bf00 nop 8004d30: 08004d65 .word 0x08004d65 8004d34: 08005135 .word 0x08005135 8004d38: 08005135 .word 0x08005135 8004d3c: 08005135 .word 0x08005135 8004d40: 08004d6d .word 0x08004d6d 8004d44: 08005135 .word 0x08005135 8004d48: 08005135 .word 0x08005135 8004d4c: 08005135 .word 0x08005135 8004d50: 08004d75 .word 0x08004d75 8004d54: 08005135 .word 0x08005135 8004d58: 08005135 .word 0x08005135 8004d5c: 08005135 .word 0x08005135 8004d60: 08004f65 .word 0x08004f65 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8004d64: 4bb9 ldr r3, [pc, #740] @ (800504c ) 8004d66: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004d6a: e1e7 b.n 800513c } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 8004d6c: 4bb8 ldr r3, [pc, #736] @ (8005050 ) 8004d6e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004d72: e1e3 b.n 800513c } case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004d74: 4bb4 ldr r3, [pc, #720] @ (8005048 ) 8004d76: 685b ldr r3, [r3, #4] 8004d78: f003 033f and.w r3, r3, #63 @ 0x3f 8004d7c: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004d80: 4bb1 ldr r3, [pc, #708] @ (8005048 ) 8004d82: 685b ldr r3, [r3, #4] 8004d84: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004d88: 2b00 cmp r3, #0 8004d8a: d071 beq.n 8004e70 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004d8c: 4bae ldr r3, [pc, #696] @ (8005048 ) 8004d8e: 685b ldr r3, [r3, #4] 8004d90: 099b lsrs r3, r3, #6 8004d92: 2200 movs r2, #0 8004d94: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8004d98: f8c7 209c str.w r2, [r7, #156] @ 0x9c 8004d9c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8004da0: f3c3 0308 ubfx r3, r3, #0, #9 8004da4: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8004da8: 2300 movs r3, #0 8004daa: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8004dae: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8004db2: 4622 mov r2, r4 8004db4: 462b mov r3, r5 8004db6: f04f 0000 mov.w r0, #0 8004dba: f04f 0100 mov.w r1, #0 8004dbe: 0159 lsls r1, r3, #5 8004dc0: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004dc4: 0150 lsls r0, r2, #5 8004dc6: 4602 mov r2, r0 8004dc8: 460b mov r3, r1 8004dca: 4621 mov r1, r4 8004dcc: 1a51 subs r1, r2, r1 8004dce: 6439 str r1, [r7, #64] @ 0x40 8004dd0: 4629 mov r1, r5 8004dd2: eb63 0301 sbc.w r3, r3, r1 8004dd6: 647b str r3, [r7, #68] @ 0x44 8004dd8: f04f 0200 mov.w r2, #0 8004ddc: f04f 0300 mov.w r3, #0 8004de0: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40 8004de4: 4649 mov r1, r9 8004de6: 018b lsls r3, r1, #6 8004de8: 4641 mov r1, r8 8004dea: ea43 6391 orr.w r3, r3, r1, lsr #26 8004dee: 4641 mov r1, r8 8004df0: 018a lsls r2, r1, #6 8004df2: 4641 mov r1, r8 8004df4: 1a51 subs r1, r2, r1 8004df6: 63b9 str r1, [r7, #56] @ 0x38 8004df8: 4649 mov r1, r9 8004dfa: eb63 0301 sbc.w r3, r3, r1 8004dfe: 63fb str r3, [r7, #60] @ 0x3c 8004e00: f04f 0200 mov.w r2, #0 8004e04: f04f 0300 mov.w r3, #0 8004e08: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38 8004e0c: 4649 mov r1, r9 8004e0e: 00cb lsls r3, r1, #3 8004e10: 4641 mov r1, r8 8004e12: ea43 7351 orr.w r3, r3, r1, lsr #29 8004e16: 4641 mov r1, r8 8004e18: 00ca lsls r2, r1, #3 8004e1a: 4610 mov r0, r2 8004e1c: 4619 mov r1, r3 8004e1e: 4603 mov r3, r0 8004e20: 4622 mov r2, r4 8004e22: 189b adds r3, r3, r2 8004e24: 633b str r3, [r7, #48] @ 0x30 8004e26: 462b mov r3, r5 8004e28: 460a mov r2, r1 8004e2a: eb42 0303 adc.w r3, r2, r3 8004e2e: 637b str r3, [r7, #52] @ 0x34 8004e30: f04f 0200 mov.w r2, #0 8004e34: f04f 0300 mov.w r3, #0 8004e38: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 8004e3c: 4629 mov r1, r5 8004e3e: 024b lsls r3, r1, #9 8004e40: 4621 mov r1, r4 8004e42: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004e46: 4621 mov r1, r4 8004e48: 024a lsls r2, r1, #9 8004e4a: 4610 mov r0, r2 8004e4c: 4619 mov r1, r3 8004e4e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004e52: 2200 movs r2, #0 8004e54: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8004e58: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8004e5c: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88 8004e60: f7fb f9d0 bl 8000204 <__aeabi_uldivmod> 8004e64: 4602 mov r2, r0 8004e66: 460b mov r3, r1 8004e68: 4613 mov r3, r2 8004e6a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8004e6e: e067 b.n 8004f40 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004e70: 4b75 ldr r3, [pc, #468] @ (8005048 ) 8004e72: 685b ldr r3, [r3, #4] 8004e74: 099b lsrs r3, r3, #6 8004e76: 2200 movs r2, #0 8004e78: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8004e7c: f8c7 2084 str.w r2, [r7, #132] @ 0x84 8004e80: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8004e84: f3c3 0308 ubfx r3, r3, #0, #9 8004e88: 67bb str r3, [r7, #120] @ 0x78 8004e8a: 2300 movs r3, #0 8004e8c: 67fb str r3, [r7, #124] @ 0x7c 8004e8e: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78 8004e92: 4622 mov r2, r4 8004e94: 462b mov r3, r5 8004e96: f04f 0000 mov.w r0, #0 8004e9a: f04f 0100 mov.w r1, #0 8004e9e: 0159 lsls r1, r3, #5 8004ea0: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004ea4: 0150 lsls r0, r2, #5 8004ea6: 4602 mov r2, r0 8004ea8: 460b mov r3, r1 8004eaa: 4621 mov r1, r4 8004eac: 1a51 subs r1, r2, r1 8004eae: 62b9 str r1, [r7, #40] @ 0x28 8004eb0: 4629 mov r1, r5 8004eb2: eb63 0301 sbc.w r3, r3, r1 8004eb6: 62fb str r3, [r7, #44] @ 0x2c 8004eb8: f04f 0200 mov.w r2, #0 8004ebc: f04f 0300 mov.w r3, #0 8004ec0: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28 8004ec4: 4649 mov r1, r9 8004ec6: 018b lsls r3, r1, #6 8004ec8: 4641 mov r1, r8 8004eca: ea43 6391 orr.w r3, r3, r1, lsr #26 8004ece: 4641 mov r1, r8 8004ed0: 018a lsls r2, r1, #6 8004ed2: 4641 mov r1, r8 8004ed4: ebb2 0a01 subs.w sl, r2, r1 8004ed8: 4649 mov r1, r9 8004eda: eb63 0b01 sbc.w fp, r3, r1 8004ede: f04f 0200 mov.w r2, #0 8004ee2: f04f 0300 mov.w r3, #0 8004ee6: ea4f 03cb mov.w r3, fp, lsl #3 8004eea: ea43 735a orr.w r3, r3, sl, lsr #29 8004eee: ea4f 02ca mov.w r2, sl, lsl #3 8004ef2: 4692 mov sl, r2 8004ef4: 469b mov fp, r3 8004ef6: 4623 mov r3, r4 8004ef8: eb1a 0303 adds.w r3, sl, r3 8004efc: 623b str r3, [r7, #32] 8004efe: 462b mov r3, r5 8004f00: eb4b 0303 adc.w r3, fp, r3 8004f04: 627b str r3, [r7, #36] @ 0x24 8004f06: f04f 0200 mov.w r2, #0 8004f0a: f04f 0300 mov.w r3, #0 8004f0e: e9d7 4508 ldrd r4, r5, [r7, #32] 8004f12: 4629 mov r1, r5 8004f14: 028b lsls r3, r1, #10 8004f16: 4621 mov r1, r4 8004f18: ea43 5391 orr.w r3, r3, r1, lsr #22 8004f1c: 4621 mov r1, r4 8004f1e: 028a lsls r2, r1, #10 8004f20: 4610 mov r0, r2 8004f22: 4619 mov r1, r3 8004f24: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004f28: 2200 movs r2, #0 8004f2a: 673b str r3, [r7, #112] @ 0x70 8004f2c: 677a str r2, [r7, #116] @ 0x74 8004f2e: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70 8004f32: f7fb f967 bl 8000204 <__aeabi_uldivmod> 8004f36: 4602 mov r2, r0 8004f38: 460b mov r3, r1 8004f3a: 4613 mov r3, r2 8004f3c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); 8004f40: 4b41 ldr r3, [pc, #260] @ (8005048 ) 8004f42: 685b ldr r3, [r3, #4] 8004f44: 0c1b lsrs r3, r3, #16 8004f46: f003 0303 and.w r3, r3, #3 8004f4a: 3301 adds r3, #1 8004f4c: 005b lsls r3, r3, #1 8004f4e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 sysclockfreq = pllvco / pllp; 8004f52: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004f56: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8004f5a: fbb2 f3f3 udiv r3, r2, r3 8004f5e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004f62: e0eb b.n 800513c } case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004f64: 4b38 ldr r3, [pc, #224] @ (8005048 ) 8004f66: 685b ldr r3, [r3, #4] 8004f68: f003 033f and.w r3, r3, #63 @ 0x3f 8004f6c: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004f70: 4b35 ldr r3, [pc, #212] @ (8005048 ) 8004f72: 685b ldr r3, [r3, #4] 8004f74: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004f78: 2b00 cmp r3, #0 8004f7a: d06b beq.n 8005054 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004f7c: 4b32 ldr r3, [pc, #200] @ (8005048 ) 8004f7e: 685b ldr r3, [r3, #4] 8004f80: 099b lsrs r3, r3, #6 8004f82: 2200 movs r2, #0 8004f84: 66bb str r3, [r7, #104] @ 0x68 8004f86: 66fa str r2, [r7, #108] @ 0x6c 8004f88: 6ebb ldr r3, [r7, #104] @ 0x68 8004f8a: f3c3 0308 ubfx r3, r3, #0, #9 8004f8e: 663b str r3, [r7, #96] @ 0x60 8004f90: 2300 movs r3, #0 8004f92: 667b str r3, [r7, #100] @ 0x64 8004f94: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60 8004f98: 4622 mov r2, r4 8004f9a: 462b mov r3, r5 8004f9c: f04f 0000 mov.w r0, #0 8004fa0: f04f 0100 mov.w r1, #0 8004fa4: 0159 lsls r1, r3, #5 8004fa6: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004faa: 0150 lsls r0, r2, #5 8004fac: 4602 mov r2, r0 8004fae: 460b mov r3, r1 8004fb0: 4621 mov r1, r4 8004fb2: 1a51 subs r1, r2, r1 8004fb4: 61b9 str r1, [r7, #24] 8004fb6: 4629 mov r1, r5 8004fb8: eb63 0301 sbc.w r3, r3, r1 8004fbc: 61fb str r3, [r7, #28] 8004fbe: f04f 0200 mov.w r2, #0 8004fc2: f04f 0300 mov.w r3, #0 8004fc6: e9d7 ab06 ldrd sl, fp, [r7, #24] 8004fca: 4659 mov r1, fp 8004fcc: 018b lsls r3, r1, #6 8004fce: 4651 mov r1, sl 8004fd0: ea43 6391 orr.w r3, r3, r1, lsr #26 8004fd4: 4651 mov r1, sl 8004fd6: 018a lsls r2, r1, #6 8004fd8: 4651 mov r1, sl 8004fda: ebb2 0801 subs.w r8, r2, r1 8004fde: 4659 mov r1, fp 8004fe0: eb63 0901 sbc.w r9, r3, r1 8004fe4: f04f 0200 mov.w r2, #0 8004fe8: f04f 0300 mov.w r3, #0 8004fec: ea4f 03c9 mov.w r3, r9, lsl #3 8004ff0: ea43 7358 orr.w r3, r3, r8, lsr #29 8004ff4: ea4f 02c8 mov.w r2, r8, lsl #3 8004ff8: 4690 mov r8, r2 8004ffa: 4699 mov r9, r3 8004ffc: 4623 mov r3, r4 8004ffe: eb18 0303 adds.w r3, r8, r3 8005002: 613b str r3, [r7, #16] 8005004: 462b mov r3, r5 8005006: eb49 0303 adc.w r3, r9, r3 800500a: 617b str r3, [r7, #20] 800500c: f04f 0200 mov.w r2, #0 8005010: f04f 0300 mov.w r3, #0 8005014: e9d7 4504 ldrd r4, r5, [r7, #16] 8005018: 4629 mov r1, r5 800501a: 024b lsls r3, r1, #9 800501c: 4621 mov r1, r4 800501e: ea43 53d1 orr.w r3, r3, r1, lsr #23 8005022: 4621 mov r1, r4 8005024: 024a lsls r2, r1, #9 8005026: 4610 mov r0, r2 8005028: 4619 mov r1, r3 800502a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800502e: 2200 movs r2, #0 8005030: 65bb str r3, [r7, #88] @ 0x58 8005032: 65fa str r2, [r7, #92] @ 0x5c 8005034: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8005038: f7fb f8e4 bl 8000204 <__aeabi_uldivmod> 800503c: 4602 mov r2, r0 800503e: 460b mov r3, r1 8005040: 4613 mov r3, r2 8005042: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8005046: e065 b.n 8005114 8005048: 40023800 .word 0x40023800 800504c: 00f42400 .word 0x00f42400 8005050: 007a1200 .word 0x007a1200 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8005054: 4b3d ldr r3, [pc, #244] @ (800514c ) 8005056: 685b ldr r3, [r3, #4] 8005058: 099b lsrs r3, r3, #6 800505a: 2200 movs r2, #0 800505c: 4618 mov r0, r3 800505e: 4611 mov r1, r2 8005060: f3c0 0308 ubfx r3, r0, #0, #9 8005064: 653b str r3, [r7, #80] @ 0x50 8005066: 2300 movs r3, #0 8005068: 657b str r3, [r7, #84] @ 0x54 800506a: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50 800506e: 4642 mov r2, r8 8005070: 464b mov r3, r9 8005072: f04f 0000 mov.w r0, #0 8005076: f04f 0100 mov.w r1, #0 800507a: 0159 lsls r1, r3, #5 800507c: ea41 61d2 orr.w r1, r1, r2, lsr #27 8005080: 0150 lsls r0, r2, #5 8005082: 4602 mov r2, r0 8005084: 460b mov r3, r1 8005086: 4641 mov r1, r8 8005088: 1a51 subs r1, r2, r1 800508a: 60b9 str r1, [r7, #8] 800508c: 4649 mov r1, r9 800508e: eb63 0301 sbc.w r3, r3, r1 8005092: 60fb str r3, [r7, #12] 8005094: f04f 0200 mov.w r2, #0 8005098: f04f 0300 mov.w r3, #0 800509c: e9d7 ab02 ldrd sl, fp, [r7, #8] 80050a0: 4659 mov r1, fp 80050a2: 018b lsls r3, r1, #6 80050a4: 4651 mov r1, sl 80050a6: ea43 6391 orr.w r3, r3, r1, lsr #26 80050aa: 4651 mov r1, sl 80050ac: 018a lsls r2, r1, #6 80050ae: 4651 mov r1, sl 80050b0: 1a54 subs r4, r2, r1 80050b2: 4659 mov r1, fp 80050b4: eb63 0501 sbc.w r5, r3, r1 80050b8: f04f 0200 mov.w r2, #0 80050bc: f04f 0300 mov.w r3, #0 80050c0: 00eb lsls r3, r5, #3 80050c2: ea43 7354 orr.w r3, r3, r4, lsr #29 80050c6: 00e2 lsls r2, r4, #3 80050c8: 4614 mov r4, r2 80050ca: 461d mov r5, r3 80050cc: 4643 mov r3, r8 80050ce: 18e3 adds r3, r4, r3 80050d0: 603b str r3, [r7, #0] 80050d2: 464b mov r3, r9 80050d4: eb45 0303 adc.w r3, r5, r3 80050d8: 607b str r3, [r7, #4] 80050da: f04f 0200 mov.w r2, #0 80050de: f04f 0300 mov.w r3, #0 80050e2: e9d7 4500 ldrd r4, r5, [r7] 80050e6: 4629 mov r1, r5 80050e8: 028b lsls r3, r1, #10 80050ea: 4621 mov r1, r4 80050ec: ea43 5391 orr.w r3, r3, r1, lsr #22 80050f0: 4621 mov r1, r4 80050f2: 028a lsls r2, r1, #10 80050f4: 4610 mov r0, r2 80050f6: 4619 mov r1, r3 80050f8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80050fc: 2200 movs r2, #0 80050fe: 64bb str r3, [r7, #72] @ 0x48 8005100: 64fa str r2, [r7, #76] @ 0x4c 8005102: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8005106: f7fb f87d bl 8000204 <__aeabi_uldivmod> 800510a: 4602 mov r2, r0 800510c: 460b mov r3, r1 800510e: 4613 mov r3, r2 8005110: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); 8005114: 4b0d ldr r3, [pc, #52] @ (800514c ) 8005116: 685b ldr r3, [r3, #4] 8005118: 0f1b lsrs r3, r3, #28 800511a: f003 0307 and.w r3, r3, #7 800511e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 sysclockfreq = pllvco / pllr; 8005122: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8005126: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 800512a: fbb2 f3f3 udiv r3, r2, r3 800512e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8005132: e003 b.n 800513c } default: { sysclockfreq = HSI_VALUE; 8005134: 4b06 ldr r3, [pc, #24] @ (8005150 ) 8005136: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 800513a: bf00 nop } } return sysclockfreq; 800513c: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 } 8005140: 4618 mov r0, r3 8005142: 37b8 adds r7, #184 @ 0xb8 8005144: 46bd mov sp, r7 8005146: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800514a: bf00 nop 800514c: 40023800 .word 0x40023800 8005150: 00f42400 .word 0x00f42400 08005154 : * @note This function add the PLL/PLLR factor management during PLL configuration this feature * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 8005154: b580 push {r7, lr} 8005156: b086 sub sp, #24 8005158: af00 add r7, sp, #0 800515a: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800515c: 687b ldr r3, [r7, #4] 800515e: 2b00 cmp r3, #0 8005160: d101 bne.n 8005166 { return HAL_ERROR; 8005162: 2301 movs r3, #1 8005164: e28d b.n 8005682 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8005166: 687b ldr r3, [r7, #4] 8005168: 681b ldr r3, [r3, #0] 800516a: f003 0301 and.w r3, r3, #1 800516e: 2b00 cmp r3, #0 8005170: f000 8083 beq.w 800527a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 8005174: 4b94 ldr r3, [pc, #592] @ (80053c8 ) 8005176: 689b ldr r3, [r3, #8] 8005178: f003 030c and.w r3, r3, #12 800517c: 2b04 cmp r3, #4 800517e: d019 beq.n 80051b4 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8005180: 4b91 ldr r3, [pc, #580] @ (80053c8 ) 8005182: 689b ldr r3, [r3, #8] 8005184: f003 030c and.w r3, r3, #12 || \ 8005188: 2b08 cmp r3, #8 800518a: d106 bne.n 800519a ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 800518c: 4b8e ldr r3, [pc, #568] @ (80053c8 ) 800518e: 685b ldr r3, [r3, #4] 8005190: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8005194: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8005198: d00c beq.n 80051b4 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 800519a: 4b8b ldr r3, [pc, #556] @ (80053c8 ) 800519c: 689b ldr r3, [r3, #8] 800519e: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 80051a2: 2b0c cmp r3, #12 80051a4: d112 bne.n 80051cc ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 80051a6: 4b88 ldr r3, [pc, #544] @ (80053c8 ) 80051a8: 685b ldr r3, [r3, #4] 80051aa: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80051ae: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80051b2: d10b bne.n 80051cc if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) #endif /* STM32F446xx */ { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80051b4: 4b84 ldr r3, [pc, #528] @ (80053c8 ) 80051b6: 681b ldr r3, [r3, #0] 80051b8: f403 3300 and.w r3, r3, #131072 @ 0x20000 80051bc: 2b00 cmp r3, #0 80051be: d05b beq.n 8005278 80051c0: 687b ldr r3, [r7, #4] 80051c2: 685b ldr r3, [r3, #4] 80051c4: 2b00 cmp r3, #0 80051c6: d157 bne.n 8005278 { return HAL_ERROR; 80051c8: 2301 movs r3, #1 80051ca: e25a b.n 8005682 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80051cc: 687b ldr r3, [r7, #4] 80051ce: 685b ldr r3, [r3, #4] 80051d0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80051d4: d106 bne.n 80051e4 80051d6: 4b7c ldr r3, [pc, #496] @ (80053c8 ) 80051d8: 681b ldr r3, [r3, #0] 80051da: 4a7b ldr r2, [pc, #492] @ (80053c8 ) 80051dc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80051e0: 6013 str r3, [r2, #0] 80051e2: e01d b.n 8005220 80051e4: 687b ldr r3, [r7, #4] 80051e6: 685b ldr r3, [r3, #4] 80051e8: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 80051ec: d10c bne.n 8005208 80051ee: 4b76 ldr r3, [pc, #472] @ (80053c8 ) 80051f0: 681b ldr r3, [r3, #0] 80051f2: 4a75 ldr r2, [pc, #468] @ (80053c8 ) 80051f4: f443 2380 orr.w r3, r3, #262144 @ 0x40000 80051f8: 6013 str r3, [r2, #0] 80051fa: 4b73 ldr r3, [pc, #460] @ (80053c8 ) 80051fc: 681b ldr r3, [r3, #0] 80051fe: 4a72 ldr r2, [pc, #456] @ (80053c8 ) 8005200: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8005204: 6013 str r3, [r2, #0] 8005206: e00b b.n 8005220 8005208: 4b6f ldr r3, [pc, #444] @ (80053c8 ) 800520a: 681b ldr r3, [r3, #0] 800520c: 4a6e ldr r2, [pc, #440] @ (80053c8 ) 800520e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8005212: 6013 str r3, [r2, #0] 8005214: 4b6c ldr r3, [pc, #432] @ (80053c8 ) 8005216: 681b ldr r3, [r3, #0] 8005218: 4a6b ldr r2, [pc, #428] @ (80053c8 ) 800521a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800521e: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 8005220: 687b ldr r3, [r7, #4] 8005222: 685b ldr r3, [r3, #4] 8005224: 2b00 cmp r3, #0 8005226: d013 beq.n 8005250 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005228: f7fc fe4c bl 8001ec4 800522c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800522e: e008 b.n 8005242 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8005230: f7fc fe48 bl 8001ec4 8005234: 4602 mov r2, r0 8005236: 693b ldr r3, [r7, #16] 8005238: 1ad3 subs r3, r2, r3 800523a: 2b64 cmp r3, #100 @ 0x64 800523c: d901 bls.n 8005242 { return HAL_TIMEOUT; 800523e: 2303 movs r3, #3 8005240: e21f b.n 8005682 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8005242: 4b61 ldr r3, [pc, #388] @ (80053c8 ) 8005244: 681b ldr r3, [r3, #0] 8005246: f403 3300 and.w r3, r3, #131072 @ 0x20000 800524a: 2b00 cmp r3, #0 800524c: d0f0 beq.n 8005230 800524e: e014 b.n 800527a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005250: f7fc fe38 bl 8001ec4 8005254: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8005256: e008 b.n 800526a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8005258: f7fc fe34 bl 8001ec4 800525c: 4602 mov r2, r0 800525e: 693b ldr r3, [r7, #16] 8005260: 1ad3 subs r3, r2, r3 8005262: 2b64 cmp r3, #100 @ 0x64 8005264: d901 bls.n 800526a { return HAL_TIMEOUT; 8005266: 2303 movs r3, #3 8005268: e20b b.n 8005682 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800526a: 4b57 ldr r3, [pc, #348] @ (80053c8 ) 800526c: 681b ldr r3, [r3, #0] 800526e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005272: 2b00 cmp r3, #0 8005274: d1f0 bne.n 8005258 8005276: e000 b.n 800527a if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8005278: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800527a: 687b ldr r3, [r7, #4] 800527c: 681b ldr r3, [r3, #0] 800527e: f003 0302 and.w r3, r3, #2 8005282: 2b00 cmp r3, #0 8005284: d06f beq.n 8005366 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 8005286: 4b50 ldr r3, [pc, #320] @ (80053c8 ) 8005288: 689b ldr r3, [r3, #8] 800528a: f003 030c and.w r3, r3, #12 800528e: 2b00 cmp r3, #0 8005290: d017 beq.n 80052c2 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8005292: 4b4d ldr r3, [pc, #308] @ (80053c8 ) 8005294: 689b ldr r3, [r3, #8] 8005296: f003 030c and.w r3, r3, #12 || \ 800529a: 2b08 cmp r3, #8 800529c: d105 bne.n 80052aa ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 800529e: 4b4a ldr r3, [pc, #296] @ (80053c8 ) 80052a0: 685b ldr r3, [r3, #4] 80052a2: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80052a6: 2b00 cmp r3, #0 80052a8: d00b beq.n 80052c2 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 80052aa: 4b47 ldr r3, [pc, #284] @ (80053c8 ) 80052ac: 689b ldr r3, [r3, #8] 80052ae: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 80052b2: 2b0c cmp r3, #12 80052b4: d11c bne.n 80052f0 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 80052b6: 4b44 ldr r3, [pc, #272] @ (80053c8 ) 80052b8: 685b ldr r3, [r3, #4] 80052ba: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80052be: 2b00 cmp r3, #0 80052c0: d116 bne.n 80052f0 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) #endif /* STM32F446xx */ { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80052c2: 4b41 ldr r3, [pc, #260] @ (80053c8 ) 80052c4: 681b ldr r3, [r3, #0] 80052c6: f003 0302 and.w r3, r3, #2 80052ca: 2b00 cmp r3, #0 80052cc: d005 beq.n 80052da 80052ce: 687b ldr r3, [r7, #4] 80052d0: 68db ldr r3, [r3, #12] 80052d2: 2b01 cmp r3, #1 80052d4: d001 beq.n 80052da { return HAL_ERROR; 80052d6: 2301 movs r3, #1 80052d8: e1d3 b.n 8005682 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80052da: 4b3b ldr r3, [pc, #236] @ (80053c8 ) 80052dc: 681b ldr r3, [r3, #0] 80052de: f023 02f8 bic.w r2, r3, #248 @ 0xf8 80052e2: 687b ldr r3, [r7, #4] 80052e4: 691b ldr r3, [r3, #16] 80052e6: 00db lsls r3, r3, #3 80052e8: 4937 ldr r1, [pc, #220] @ (80053c8 ) 80052ea: 4313 orrs r3, r2 80052ec: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80052ee: e03a b.n 8005366 } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 80052f0: 687b ldr r3, [r7, #4] 80052f2: 68db ldr r3, [r3, #12] 80052f4: 2b00 cmp r3, #0 80052f6: d020 beq.n 800533a { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80052f8: 4b34 ldr r3, [pc, #208] @ (80053cc ) 80052fa: 2201 movs r2, #1 80052fc: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80052fe: f7fc fde1 bl 8001ec4 8005302: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8005304: e008 b.n 8005318 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005306: f7fc fddd bl 8001ec4 800530a: 4602 mov r2, r0 800530c: 693b ldr r3, [r7, #16] 800530e: 1ad3 subs r3, r2, r3 8005310: 2b02 cmp r3, #2 8005312: d901 bls.n 8005318 { return HAL_TIMEOUT; 8005314: 2303 movs r3, #3 8005316: e1b4 b.n 8005682 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8005318: 4b2b ldr r3, [pc, #172] @ (80053c8 ) 800531a: 681b ldr r3, [r3, #0] 800531c: f003 0302 and.w r3, r3, #2 8005320: 2b00 cmp r3, #0 8005322: d0f0 beq.n 8005306 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8005324: 4b28 ldr r3, [pc, #160] @ (80053c8 ) 8005326: 681b ldr r3, [r3, #0] 8005328: f023 02f8 bic.w r2, r3, #248 @ 0xf8 800532c: 687b ldr r3, [r7, #4] 800532e: 691b ldr r3, [r3, #16] 8005330: 00db lsls r3, r3, #3 8005332: 4925 ldr r1, [pc, #148] @ (80053c8 ) 8005334: 4313 orrs r3, r2 8005336: 600b str r3, [r1, #0] 8005338: e015 b.n 8005366 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800533a: 4b24 ldr r3, [pc, #144] @ (80053cc ) 800533c: 2200 movs r2, #0 800533e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005340: f7fc fdc0 bl 8001ec4 8005344: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8005346: e008 b.n 800535a { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005348: f7fc fdbc bl 8001ec4 800534c: 4602 mov r2, r0 800534e: 693b ldr r3, [r7, #16] 8005350: 1ad3 subs r3, r2, r3 8005352: 2b02 cmp r3, #2 8005354: d901 bls.n 800535a { return HAL_TIMEOUT; 8005356: 2303 movs r3, #3 8005358: e193 b.n 8005682 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800535a: 4b1b ldr r3, [pc, #108] @ (80053c8 ) 800535c: 681b ldr r3, [r3, #0] 800535e: f003 0302 and.w r3, r3, #2 8005362: 2b00 cmp r3, #0 8005364: d1f0 bne.n 8005348 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8005366: 687b ldr r3, [r7, #4] 8005368: 681b ldr r3, [r3, #0] 800536a: f003 0308 and.w r3, r3, #8 800536e: 2b00 cmp r3, #0 8005370: d036 beq.n 80053e0 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 8005372: 687b ldr r3, [r7, #4] 8005374: 695b ldr r3, [r3, #20] 8005376: 2b00 cmp r3, #0 8005378: d016 beq.n 80053a8 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800537a: 4b15 ldr r3, [pc, #84] @ (80053d0 ) 800537c: 2201 movs r2, #1 800537e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005380: f7fc fda0 bl 8001ec4 8005384: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8005386: e008 b.n 800539a { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8005388: f7fc fd9c bl 8001ec4 800538c: 4602 mov r2, r0 800538e: 693b ldr r3, [r7, #16] 8005390: 1ad3 subs r3, r2, r3 8005392: 2b02 cmp r3, #2 8005394: d901 bls.n 800539a { return HAL_TIMEOUT; 8005396: 2303 movs r3, #3 8005398: e173 b.n 8005682 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800539a: 4b0b ldr r3, [pc, #44] @ (80053c8 ) 800539c: 6f5b ldr r3, [r3, #116] @ 0x74 800539e: f003 0302 and.w r3, r3, #2 80053a2: 2b00 cmp r3, #0 80053a4: d0f0 beq.n 8005388 80053a6: e01b b.n 80053e0 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80053a8: 4b09 ldr r3, [pc, #36] @ (80053d0 ) 80053aa: 2200 movs r2, #0 80053ac: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80053ae: f7fc fd89 bl 8001ec4 80053b2: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80053b4: e00e b.n 80053d4 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80053b6: f7fc fd85 bl 8001ec4 80053ba: 4602 mov r2, r0 80053bc: 693b ldr r3, [r7, #16] 80053be: 1ad3 subs r3, r2, r3 80053c0: 2b02 cmp r3, #2 80053c2: d907 bls.n 80053d4 { return HAL_TIMEOUT; 80053c4: 2303 movs r3, #3 80053c6: e15c b.n 8005682 80053c8: 40023800 .word 0x40023800 80053cc: 42470000 .word 0x42470000 80053d0: 42470e80 .word 0x42470e80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80053d4: 4b8a ldr r3, [pc, #552] @ (8005600 ) 80053d6: 6f5b ldr r3, [r3, #116] @ 0x74 80053d8: f003 0302 and.w r3, r3, #2 80053dc: 2b00 cmp r3, #0 80053de: d1ea bne.n 80053b6 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80053e0: 687b ldr r3, [r7, #4] 80053e2: 681b ldr r3, [r3, #0] 80053e4: f003 0304 and.w r3, r3, #4 80053e8: 2b00 cmp r3, #0 80053ea: f000 8097 beq.w 800551c { FlagStatus pwrclkchanged = RESET; 80053ee: 2300 movs r3, #0 80053f0: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80053f2: 4b83 ldr r3, [pc, #524] @ (8005600 ) 80053f4: 6c1b ldr r3, [r3, #64] @ 0x40 80053f6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80053fa: 2b00 cmp r3, #0 80053fc: d10f bne.n 800541e { __HAL_RCC_PWR_CLK_ENABLE(); 80053fe: 2300 movs r3, #0 8005400: 60bb str r3, [r7, #8] 8005402: 4b7f ldr r3, [pc, #508] @ (8005600 ) 8005404: 6c1b ldr r3, [r3, #64] @ 0x40 8005406: 4a7e ldr r2, [pc, #504] @ (8005600 ) 8005408: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800540c: 6413 str r3, [r2, #64] @ 0x40 800540e: 4b7c ldr r3, [pc, #496] @ (8005600 ) 8005410: 6c1b ldr r3, [r3, #64] @ 0x40 8005412: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005416: 60bb str r3, [r7, #8] 8005418: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800541a: 2301 movs r3, #1 800541c: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800541e: 4b79 ldr r3, [pc, #484] @ (8005604 ) 8005420: 681b ldr r3, [r3, #0] 8005422: f403 7380 and.w r3, r3, #256 @ 0x100 8005426: 2b00 cmp r3, #0 8005428: d118 bne.n 800545c { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800542a: 4b76 ldr r3, [pc, #472] @ (8005604 ) 800542c: 681b ldr r3, [r3, #0] 800542e: 4a75 ldr r2, [pc, #468] @ (8005604 ) 8005430: f443 7380 orr.w r3, r3, #256 @ 0x100 8005434: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8005436: f7fc fd45 bl 8001ec4 800543a: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800543c: e008 b.n 8005450 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800543e: f7fc fd41 bl 8001ec4 8005442: 4602 mov r2, r0 8005444: 693b ldr r3, [r7, #16] 8005446: 1ad3 subs r3, r2, r3 8005448: 2b02 cmp r3, #2 800544a: d901 bls.n 8005450 { return HAL_TIMEOUT; 800544c: 2303 movs r3, #3 800544e: e118 b.n 8005682 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005450: 4b6c ldr r3, [pc, #432] @ (8005604 ) 8005452: 681b ldr r3, [r3, #0] 8005454: f403 7380 and.w r3, r3, #256 @ 0x100 8005458: 2b00 cmp r3, #0 800545a: d0f0 beq.n 800543e } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800545c: 687b ldr r3, [r7, #4] 800545e: 689b ldr r3, [r3, #8] 8005460: 2b01 cmp r3, #1 8005462: d106 bne.n 8005472 8005464: 4b66 ldr r3, [pc, #408] @ (8005600 ) 8005466: 6f1b ldr r3, [r3, #112] @ 0x70 8005468: 4a65 ldr r2, [pc, #404] @ (8005600 ) 800546a: f043 0301 orr.w r3, r3, #1 800546e: 6713 str r3, [r2, #112] @ 0x70 8005470: e01c b.n 80054ac 8005472: 687b ldr r3, [r7, #4] 8005474: 689b ldr r3, [r3, #8] 8005476: 2b05 cmp r3, #5 8005478: d10c bne.n 8005494 800547a: 4b61 ldr r3, [pc, #388] @ (8005600 ) 800547c: 6f1b ldr r3, [r3, #112] @ 0x70 800547e: 4a60 ldr r2, [pc, #384] @ (8005600 ) 8005480: f043 0304 orr.w r3, r3, #4 8005484: 6713 str r3, [r2, #112] @ 0x70 8005486: 4b5e ldr r3, [pc, #376] @ (8005600 ) 8005488: 6f1b ldr r3, [r3, #112] @ 0x70 800548a: 4a5d ldr r2, [pc, #372] @ (8005600 ) 800548c: f043 0301 orr.w r3, r3, #1 8005490: 6713 str r3, [r2, #112] @ 0x70 8005492: e00b b.n 80054ac 8005494: 4b5a ldr r3, [pc, #360] @ (8005600 ) 8005496: 6f1b ldr r3, [r3, #112] @ 0x70 8005498: 4a59 ldr r2, [pc, #356] @ (8005600 ) 800549a: f023 0301 bic.w r3, r3, #1 800549e: 6713 str r3, [r2, #112] @ 0x70 80054a0: 4b57 ldr r3, [pc, #348] @ (8005600 ) 80054a2: 6f1b ldr r3, [r3, #112] @ 0x70 80054a4: 4a56 ldr r2, [pc, #344] @ (8005600 ) 80054a6: f023 0304 bic.w r3, r3, #4 80054aa: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 80054ac: 687b ldr r3, [r7, #4] 80054ae: 689b ldr r3, [r3, #8] 80054b0: 2b00 cmp r3, #0 80054b2: d015 beq.n 80054e0 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80054b4: f7fc fd06 bl 8001ec4 80054b8: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80054ba: e00a b.n 80054d2 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80054bc: f7fc fd02 bl 8001ec4 80054c0: 4602 mov r2, r0 80054c2: 693b ldr r3, [r7, #16] 80054c4: 1ad3 subs r3, r2, r3 80054c6: f241 3288 movw r2, #5000 @ 0x1388 80054ca: 4293 cmp r3, r2 80054cc: d901 bls.n 80054d2 { return HAL_TIMEOUT; 80054ce: 2303 movs r3, #3 80054d0: e0d7 b.n 8005682 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80054d2: 4b4b ldr r3, [pc, #300] @ (8005600 ) 80054d4: 6f1b ldr r3, [r3, #112] @ 0x70 80054d6: f003 0302 and.w r3, r3, #2 80054da: 2b00 cmp r3, #0 80054dc: d0ee beq.n 80054bc 80054de: e014 b.n 800550a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80054e0: f7fc fcf0 bl 8001ec4 80054e4: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80054e6: e00a b.n 80054fe { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80054e8: f7fc fcec bl 8001ec4 80054ec: 4602 mov r2, r0 80054ee: 693b ldr r3, [r7, #16] 80054f0: 1ad3 subs r3, r2, r3 80054f2: f241 3288 movw r2, #5000 @ 0x1388 80054f6: 4293 cmp r3, r2 80054f8: d901 bls.n 80054fe { return HAL_TIMEOUT; 80054fa: 2303 movs r3, #3 80054fc: e0c1 b.n 8005682 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80054fe: 4b40 ldr r3, [pc, #256] @ (8005600 ) 8005500: 6f1b ldr r3, [r3, #112] @ 0x70 8005502: f003 0302 and.w r3, r3, #2 8005506: 2b00 cmp r3, #0 8005508: d1ee bne.n 80054e8 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 800550a: 7dfb ldrb r3, [r7, #23] 800550c: 2b01 cmp r3, #1 800550e: d105 bne.n 800551c { __HAL_RCC_PWR_CLK_DISABLE(); 8005510: 4b3b ldr r3, [pc, #236] @ (8005600 ) 8005512: 6c1b ldr r3, [r3, #64] @ 0x40 8005514: 4a3a ldr r2, [pc, #232] @ (8005600 ) 8005516: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800551a: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800551c: 687b ldr r3, [r7, #4] 800551e: 699b ldr r3, [r3, #24] 8005520: 2b00 cmp r3, #0 8005522: f000 80ad beq.w 8005680 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 8005526: 4b36 ldr r3, [pc, #216] @ (8005600 ) 8005528: 689b ldr r3, [r3, #8] 800552a: f003 030c and.w r3, r3, #12 800552e: 2b08 cmp r3, #8 8005530: d060 beq.n 80055f4 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8005532: 687b ldr r3, [r7, #4] 8005534: 699b ldr r3, [r3, #24] 8005536: 2b02 cmp r3, #2 8005538: d145 bne.n 80055c6 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800553a: 4b33 ldr r3, [pc, #204] @ (8005608 ) 800553c: 2200 movs r2, #0 800553e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005540: f7fc fcc0 bl 8001ec4 8005544: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005546: e008 b.n 800555a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005548: f7fc fcbc bl 8001ec4 800554c: 4602 mov r2, r0 800554e: 693b ldr r3, [r7, #16] 8005550: 1ad3 subs r3, r2, r3 8005552: 2b02 cmp r3, #2 8005554: d901 bls.n 800555a { return HAL_TIMEOUT; 8005556: 2303 movs r3, #3 8005558: e093 b.n 8005682 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800555a: 4b29 ldr r3, [pc, #164] @ (8005600 ) 800555c: 681b ldr r3, [r3, #0] 800555e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005562: 2b00 cmp r3, #0 8005564: d1f0 bne.n 8005548 } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 8005566: 687b ldr r3, [r7, #4] 8005568: 69da ldr r2, [r3, #28] 800556a: 687b ldr r3, [r7, #4] 800556c: 6a1b ldr r3, [r3, #32] 800556e: 431a orrs r2, r3 8005570: 687b ldr r3, [r7, #4] 8005572: 6a5b ldr r3, [r3, #36] @ 0x24 8005574: 019b lsls r3, r3, #6 8005576: 431a orrs r2, r3 8005578: 687b ldr r3, [r7, #4] 800557a: 6a9b ldr r3, [r3, #40] @ 0x28 800557c: 085b lsrs r3, r3, #1 800557e: 3b01 subs r3, #1 8005580: 041b lsls r3, r3, #16 8005582: 431a orrs r2, r3 8005584: 687b ldr r3, [r7, #4] 8005586: 6adb ldr r3, [r3, #44] @ 0x2c 8005588: 061b lsls r3, r3, #24 800558a: 431a orrs r2, r3 800558c: 687b ldr r3, [r7, #4] 800558e: 6b1b ldr r3, [r3, #48] @ 0x30 8005590: 071b lsls r3, r3, #28 8005592: 491b ldr r1, [pc, #108] @ (8005600 ) 8005594: 4313 orrs r3, r2 8005596: 604b str r3, [r1, #4] (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8005598: 4b1b ldr r3, [pc, #108] @ (8005608 ) 800559a: 2201 movs r2, #1 800559c: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800559e: f7fc fc91 bl 8001ec4 80055a2: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80055a4: e008 b.n 80055b8 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80055a6: f7fc fc8d bl 8001ec4 80055aa: 4602 mov r2, r0 80055ac: 693b ldr r3, [r7, #16] 80055ae: 1ad3 subs r3, r2, r3 80055b0: 2b02 cmp r3, #2 80055b2: d901 bls.n 80055b8 { return HAL_TIMEOUT; 80055b4: 2303 movs r3, #3 80055b6: e064 b.n 8005682 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80055b8: 4b11 ldr r3, [pc, #68] @ (8005600 ) 80055ba: 681b ldr r3, [r3, #0] 80055bc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80055c0: 2b00 cmp r3, #0 80055c2: d0f0 beq.n 80055a6 80055c4: e05c b.n 8005680 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80055c6: 4b10 ldr r3, [pc, #64] @ (8005608 ) 80055c8: 2200 movs r2, #0 80055ca: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80055cc: f7fc fc7a bl 8001ec4 80055d0: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80055d2: e008 b.n 80055e6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80055d4: f7fc fc76 bl 8001ec4 80055d8: 4602 mov r2, r0 80055da: 693b ldr r3, [r7, #16] 80055dc: 1ad3 subs r3, r2, r3 80055de: 2b02 cmp r3, #2 80055e0: d901 bls.n 80055e6 { return HAL_TIMEOUT; 80055e2: 2303 movs r3, #3 80055e4: e04d b.n 8005682 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80055e6: 4b06 ldr r3, [pc, #24] @ (8005600 ) 80055e8: 681b ldr r3, [r3, #0] 80055ea: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80055ee: 2b00 cmp r3, #0 80055f0: d1f0 bne.n 80055d4 80055f2: e045 b.n 8005680 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80055f4: 687b ldr r3, [r7, #4] 80055f6: 699b ldr r3, [r3, #24] 80055f8: 2b01 cmp r3, #1 80055fa: d107 bne.n 800560c { return HAL_ERROR; 80055fc: 2301 movs r3, #1 80055fe: e040 b.n 8005682 8005600: 40023800 .word 0x40023800 8005604: 40007000 .word 0x40007000 8005608: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 800560c: 4b1f ldr r3, [pc, #124] @ (800568c ) 800560e: 685b ldr r3, [r3, #4] 8005610: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8005612: 687b ldr r3, [r7, #4] 8005614: 699b ldr r3, [r3, #24] 8005616: 2b01 cmp r3, #1 8005618: d030 beq.n 800567c (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800561a: 68fb ldr r3, [r7, #12] 800561c: f403 0280 and.w r2, r3, #4194304 @ 0x400000 8005620: 687b ldr r3, [r7, #4] 8005622: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8005624: 429a cmp r2, r3 8005626: d129 bne.n 800567c (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 8005628: 68fb ldr r3, [r7, #12] 800562a: f003 023f and.w r2, r3, #63 @ 0x3f 800562e: 687b ldr r3, [r7, #4] 8005630: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8005632: 429a cmp r2, r3 8005634: d122 bne.n 800567c (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 8005636: 68fa ldr r2, [r7, #12] 8005638: f647 73c0 movw r3, #32704 @ 0x7fc0 800563c: 4013 ands r3, r2 800563e: 687a ldr r2, [r7, #4] 8005640: 6a52 ldr r2, [r2, #36] @ 0x24 8005642: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 8005644: 4293 cmp r3, r2 8005646: d119 bne.n 800567c (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8005648: 68fb ldr r3, [r7, #12] 800564a: f403 3240 and.w r2, r3, #196608 @ 0x30000 800564e: 687b ldr r3, [r7, #4] 8005650: 6a9b ldr r3, [r3, #40] @ 0x28 8005652: 085b lsrs r3, r3, #1 8005654: 3b01 subs r3, #1 8005656: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 8005658: 429a cmp r2, r3 800565a: d10f bne.n 800567c (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 800565c: 68fb ldr r3, [r7, #12] 800565e: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 8005662: 687b ldr r3, [r7, #4] 8005664: 6adb ldr r3, [r3, #44] @ 0x2c 8005666: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8005668: 429a cmp r2, r3 800566a: d107 bne.n 800567c (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) 800566c: 68fb ldr r3, [r7, #12] 800566e: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000 8005672: 687b ldr r3, [r7, #4] 8005674: 6b1b ldr r3, [r3, #48] @ 0x30 8005676: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 8005678: 429a cmp r2, r3 800567a: d001 beq.n 8005680 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; 800567c: 2301 movs r3, #1 800567e: e000 b.n 8005682 } } } } return HAL_OK; 8005680: 2300 movs r3, #0 } 8005682: 4618 mov r0, r3 8005684: 3718 adds r7, #24 8005686: 46bd mov sp, r7 8005688: bd80 pop {r7, pc} 800568a: bf00 nop 800568c: 40023800 .word 0x40023800 08005690 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8005690: b580 push {r7, lr} 8005692: b082 sub sp, #8 8005694: af00 add r7, sp, #0 8005696: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8005698: 687b ldr r3, [r7, #4] 800569a: 2b00 cmp r3, #0 800569c: d101 bne.n 80056a2 { return HAL_ERROR; 800569e: 2301 movs r3, #1 80056a0: e041 b.n 8005726 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 80056a2: 687b ldr r3, [r7, #4] 80056a4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80056a8: b2db uxtb r3, r3 80056aa: 2b00 cmp r3, #0 80056ac: d106 bne.n 80056bc { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80056ae: 687b ldr r3, [r7, #4] 80056b0: 2200 movs r2, #0 80056b2: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 80056b6: 6878 ldr r0, [r7, #4] 80056b8: f000 f839 bl 800572e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80056bc: 687b ldr r3, [r7, #4] 80056be: 2202 movs r2, #2 80056c0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80056c4: 687b ldr r3, [r7, #4] 80056c6: 681a ldr r2, [r3, #0] 80056c8: 687b ldr r3, [r7, #4] 80056ca: 3304 adds r3, #4 80056cc: 4619 mov r1, r3 80056ce: 4610 mov r0, r2 80056d0: f000 fdae bl 8006230 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 80056d4: 687b ldr r3, [r7, #4] 80056d6: 2201 movs r2, #1 80056d8: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80056dc: 687b ldr r3, [r7, #4] 80056de: 2201 movs r2, #1 80056e0: f883 203e strb.w r2, [r3, #62] @ 0x3e 80056e4: 687b ldr r3, [r7, #4] 80056e6: 2201 movs r2, #1 80056e8: f883 203f strb.w r2, [r3, #63] @ 0x3f 80056ec: 687b ldr r3, [r7, #4] 80056ee: 2201 movs r2, #1 80056f0: f883 2040 strb.w r2, [r3, #64] @ 0x40 80056f4: 687b ldr r3, [r7, #4] 80056f6: 2201 movs r2, #1 80056f8: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80056fc: 687b ldr r3, [r7, #4] 80056fe: 2201 movs r2, #1 8005700: f883 2042 strb.w r2, [r3, #66] @ 0x42 8005704: 687b ldr r3, [r7, #4] 8005706: 2201 movs r2, #1 8005708: f883 2043 strb.w r2, [r3, #67] @ 0x43 800570c: 687b ldr r3, [r7, #4] 800570e: 2201 movs r2, #1 8005710: f883 2044 strb.w r2, [r3, #68] @ 0x44 8005714: 687b ldr r3, [r7, #4] 8005716: 2201 movs r2, #1 8005718: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800571c: 687b ldr r3, [r7, #4] 800571e: 2201 movs r2, #1 8005720: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8005724: 2300 movs r3, #0 } 8005726: 4618 mov r0, r3 8005728: 3708 adds r7, #8 800572a: 46bd mov sp, r7 800572c: bd80 pop {r7, pc} 0800572e : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 800572e: b480 push {r7} 8005730: b083 sub sp, #12 8005732: af00 add r7, sp, #0 8005734: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 8005736: bf00 nop 8005738: 370c adds r7, #12 800573a: 46bd mov sp, r7 800573c: f85d 7b04 ldr.w r7, [sp], #4 8005740: 4770 bx lr ... 08005744 : * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length) { 8005744: b580 push {r7, lr} 8005746: b086 sub sp, #24 8005748: af00 add r7, sp, #0 800574a: 60f8 str r0, [r7, #12] 800574c: 60b9 str r1, [r7, #8] 800574e: 607a str r2, [r7, #4] 8005750: 807b strh r3, [r7, #2] HAL_StatusTypeDef status = HAL_OK; 8005752: 2300 movs r3, #0 8005754: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) 8005756: 68bb ldr r3, [r7, #8] 8005758: 2b00 cmp r3, #0 800575a: d109 bne.n 8005770 800575c: 68fb ldr r3, [r7, #12] 800575e: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8005762: b2db uxtb r3, r3 8005764: 2b02 cmp r3, #2 8005766: bf0c ite eq 8005768: 2301 moveq r3, #1 800576a: 2300 movne r3, #0 800576c: b2db uxtb r3, r3 800576e: e022 b.n 80057b6 8005770: 68bb ldr r3, [r7, #8] 8005772: 2b04 cmp r3, #4 8005774: d109 bne.n 800578a 8005776: 68fb ldr r3, [r7, #12] 8005778: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800577c: b2db uxtb r3, r3 800577e: 2b02 cmp r3, #2 8005780: bf0c ite eq 8005782: 2301 moveq r3, #1 8005784: 2300 movne r3, #0 8005786: b2db uxtb r3, r3 8005788: e015 b.n 80057b6 800578a: 68bb ldr r3, [r7, #8] 800578c: 2b08 cmp r3, #8 800578e: d109 bne.n 80057a4 8005790: 68fb ldr r3, [r7, #12] 8005792: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8005796: b2db uxtb r3, r3 8005798: 2b02 cmp r3, #2 800579a: bf0c ite eq 800579c: 2301 moveq r3, #1 800579e: 2300 movne r3, #0 80057a0: b2db uxtb r3, r3 80057a2: e008 b.n 80057b6 80057a4: 68fb ldr r3, [r7, #12] 80057a6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80057aa: b2db uxtb r3, r3 80057ac: 2b02 cmp r3, #2 80057ae: bf0c ite eq 80057b0: 2301 moveq r3, #1 80057b2: 2300 movne r3, #0 80057b4: b2db uxtb r3, r3 80057b6: 2b00 cmp r3, #0 80057b8: d001 beq.n 80057be { return HAL_BUSY; 80057ba: 2302 movs r3, #2 80057bc: e171 b.n 8005aa2 } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) 80057be: 68bb ldr r3, [r7, #8] 80057c0: 2b00 cmp r3, #0 80057c2: d109 bne.n 80057d8 80057c4: 68fb ldr r3, [r7, #12] 80057c6: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 80057ca: b2db uxtb r3, r3 80057cc: 2b01 cmp r3, #1 80057ce: bf0c ite eq 80057d0: 2301 moveq r3, #1 80057d2: 2300 movne r3, #0 80057d4: b2db uxtb r3, r3 80057d6: e022 b.n 800581e 80057d8: 68bb ldr r3, [r7, #8] 80057da: 2b04 cmp r3, #4 80057dc: d109 bne.n 80057f2 80057de: 68fb ldr r3, [r7, #12] 80057e0: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 80057e4: b2db uxtb r3, r3 80057e6: 2b01 cmp r3, #1 80057e8: bf0c ite eq 80057ea: 2301 moveq r3, #1 80057ec: 2300 movne r3, #0 80057ee: b2db uxtb r3, r3 80057f0: e015 b.n 800581e 80057f2: 68bb ldr r3, [r7, #8] 80057f4: 2b08 cmp r3, #8 80057f6: d109 bne.n 800580c 80057f8: 68fb ldr r3, [r7, #12] 80057fa: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 80057fe: b2db uxtb r3, r3 8005800: 2b01 cmp r3, #1 8005802: bf0c ite eq 8005804: 2301 moveq r3, #1 8005806: 2300 movne r3, #0 8005808: b2db uxtb r3, r3 800580a: e008 b.n 800581e 800580c: 68fb ldr r3, [r7, #12] 800580e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005812: b2db uxtb r3, r3 8005814: 2b01 cmp r3, #1 8005816: bf0c ite eq 8005818: 2301 moveq r3, #1 800581a: 2300 movne r3, #0 800581c: b2db uxtb r3, r3 800581e: 2b00 cmp r3, #0 8005820: d024 beq.n 800586c { if ((pData == NULL) || (Length == 0U)) 8005822: 687b ldr r3, [r7, #4] 8005824: 2b00 cmp r3, #0 8005826: d002 beq.n 800582e 8005828: 887b ldrh r3, [r7, #2] 800582a: 2b00 cmp r3, #0 800582c: d101 bne.n 8005832 { return HAL_ERROR; 800582e: 2301 movs r3, #1 8005830: e137 b.n 8005aa2 } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8005832: 68bb ldr r3, [r7, #8] 8005834: 2b00 cmp r3, #0 8005836: d104 bne.n 8005842 8005838: 68fb ldr r3, [r7, #12] 800583a: 2202 movs r2, #2 800583c: f883 203e strb.w r2, [r3, #62] @ 0x3e 8005840: e016 b.n 8005870 8005842: 68bb ldr r3, [r7, #8] 8005844: 2b04 cmp r3, #4 8005846: d104 bne.n 8005852 8005848: 68fb ldr r3, [r7, #12] 800584a: 2202 movs r2, #2 800584c: f883 203f strb.w r2, [r3, #63] @ 0x3f 8005850: e00e b.n 8005870 8005852: 68bb ldr r3, [r7, #8] 8005854: 2b08 cmp r3, #8 8005856: d104 bne.n 8005862 8005858: 68fb ldr r3, [r7, #12] 800585a: 2202 movs r2, #2 800585c: f883 2040 strb.w r2, [r3, #64] @ 0x40 8005860: e006 b.n 8005870 8005862: 68fb ldr r3, [r7, #12] 8005864: 2202 movs r2, #2 8005866: f883 2041 strb.w r2, [r3, #65] @ 0x41 800586a: e001 b.n 8005870 } } else { return HAL_ERROR; 800586c: 2301 movs r3, #1 800586e: e118 b.n 8005aa2 } switch (Channel) 8005870: 68bb ldr r3, [r7, #8] 8005872: 2b0c cmp r3, #12 8005874: f200 80ae bhi.w 80059d4 8005878: a201 add r2, pc, #4 @ (adr r2, 8005880 ) 800587a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800587e: bf00 nop 8005880: 080058b5 .word 0x080058b5 8005884: 080059d5 .word 0x080059d5 8005888: 080059d5 .word 0x080059d5 800588c: 080059d5 .word 0x080059d5 8005890: 080058fd .word 0x080058fd 8005894: 080059d5 .word 0x080059d5 8005898: 080059d5 .word 0x080059d5 800589c: 080059d5 .word 0x080059d5 80058a0: 08005945 .word 0x08005945 80058a4: 080059d5 .word 0x080059d5 80058a8: 080059d5 .word 0x080059d5 80058ac: 080059d5 .word 0x080059d5 80058b0: 0800598d .word 0x0800598d { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 80058b4: 68fb ldr r3, [r7, #12] 80058b6: 6a5b ldr r3, [r3, #36] @ 0x24 80058b8: 4a7c ldr r2, [pc, #496] @ (8005aac ) 80058ba: 63da str r2, [r3, #60] @ 0x3c htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; 80058bc: 68fb ldr r3, [r7, #12] 80058be: 6a5b ldr r3, [r3, #36] @ 0x24 80058c0: 4a7b ldr r2, [pc, #492] @ (8005ab0 ) 80058c2: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 80058c4: 68fb ldr r3, [r7, #12] 80058c6: 6a5b ldr r3, [r3, #36] @ 0x24 80058c8: 4a7a ldr r2, [pc, #488] @ (8005ab4 ) 80058ca: 64da str r2, [r3, #76] @ 0x4c /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, 80058cc: 68fb ldr r3, [r7, #12] 80058ce: 6a58 ldr r0, [r3, #36] @ 0x24 80058d0: 6879 ldr r1, [r7, #4] 80058d2: 68fb ldr r3, [r7, #12] 80058d4: 681b ldr r3, [r3, #0] 80058d6: 3334 adds r3, #52 @ 0x34 80058d8: 461a mov r2, r3 80058da: 887b ldrh r3, [r7, #2] 80058dc: f7fc fce2 bl 80022a4 80058e0: 4603 mov r3, r0 80058e2: 2b00 cmp r3, #0 80058e4: d001 beq.n 80058ea Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; 80058e6: 2301 movs r3, #1 80058e8: e0db b.n 8005aa2 } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 80058ea: 68fb ldr r3, [r7, #12] 80058ec: 681b ldr r3, [r3, #0] 80058ee: 68da ldr r2, [r3, #12] 80058f0: 68fb ldr r3, [r7, #12] 80058f2: 681b ldr r3, [r3, #0] 80058f4: f442 7200 orr.w r2, r2, #512 @ 0x200 80058f8: 60da str r2, [r3, #12] break; 80058fa: e06e b.n 80059da } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 80058fc: 68fb ldr r3, [r7, #12] 80058fe: 6a9b ldr r3, [r3, #40] @ 0x28 8005900: 4a6a ldr r2, [pc, #424] @ (8005aac ) 8005902: 63da str r2, [r3, #60] @ 0x3c htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; 8005904: 68fb ldr r3, [r7, #12] 8005906: 6a9b ldr r3, [r3, #40] @ 0x28 8005908: 4a69 ldr r2, [pc, #420] @ (8005ab0 ) 800590a: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 800590c: 68fb ldr r3, [r7, #12] 800590e: 6a9b ldr r3, [r3, #40] @ 0x28 8005910: 4a68 ldr r2, [pc, #416] @ (8005ab4 ) 8005912: 64da str r2, [r3, #76] @ 0x4c /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, 8005914: 68fb ldr r3, [r7, #12] 8005916: 6a98 ldr r0, [r3, #40] @ 0x28 8005918: 6879 ldr r1, [r7, #4] 800591a: 68fb ldr r3, [r7, #12] 800591c: 681b ldr r3, [r3, #0] 800591e: 3338 adds r3, #56 @ 0x38 8005920: 461a mov r2, r3 8005922: 887b ldrh r3, [r7, #2] 8005924: f7fc fcbe bl 80022a4 8005928: 4603 mov r3, r0 800592a: 2b00 cmp r3, #0 800592c: d001 beq.n 8005932 Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; 800592e: 2301 movs r3, #1 8005930: e0b7 b.n 8005aa2 } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 8005932: 68fb ldr r3, [r7, #12] 8005934: 681b ldr r3, [r3, #0] 8005936: 68da ldr r2, [r3, #12] 8005938: 68fb ldr r3, [r7, #12] 800593a: 681b ldr r3, [r3, #0] 800593c: f442 6280 orr.w r2, r2, #1024 @ 0x400 8005940: 60da str r2, [r3, #12] break; 8005942: e04a b.n 80059da } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 8005944: 68fb ldr r3, [r7, #12] 8005946: 6adb ldr r3, [r3, #44] @ 0x2c 8005948: 4a58 ldr r2, [pc, #352] @ (8005aac ) 800594a: 63da str r2, [r3, #60] @ 0x3c htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; 800594c: 68fb ldr r3, [r7, #12] 800594e: 6adb ldr r3, [r3, #44] @ 0x2c 8005950: 4a57 ldr r2, [pc, #348] @ (8005ab0 ) 8005952: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 8005954: 68fb ldr r3, [r7, #12] 8005956: 6adb ldr r3, [r3, #44] @ 0x2c 8005958: 4a56 ldr r2, [pc, #344] @ (8005ab4 ) 800595a: 64da str r2, [r3, #76] @ 0x4c /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, 800595c: 68fb ldr r3, [r7, #12] 800595e: 6ad8 ldr r0, [r3, #44] @ 0x2c 8005960: 6879 ldr r1, [r7, #4] 8005962: 68fb ldr r3, [r7, #12] 8005964: 681b ldr r3, [r3, #0] 8005966: 333c adds r3, #60 @ 0x3c 8005968: 461a mov r2, r3 800596a: 887b ldrh r3, [r7, #2] 800596c: f7fc fc9a bl 80022a4 8005970: 4603 mov r3, r0 8005972: 2b00 cmp r3, #0 8005974: d001 beq.n 800597a Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; 8005976: 2301 movs r3, #1 8005978: e093 b.n 8005aa2 } /* Enable the TIM Output Capture/Compare 3 request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 800597a: 68fb ldr r3, [r7, #12] 800597c: 681b ldr r3, [r3, #0] 800597e: 68da ldr r2, [r3, #12] 8005980: 68fb ldr r3, [r7, #12] 8005982: 681b ldr r3, [r3, #0] 8005984: f442 6200 orr.w r2, r2, #2048 @ 0x800 8005988: 60da str r2, [r3, #12] break; 800598a: e026 b.n 80059da } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; 800598c: 68fb ldr r3, [r7, #12] 800598e: 6b1b ldr r3, [r3, #48] @ 0x30 8005990: 4a46 ldr r2, [pc, #280] @ (8005aac ) 8005992: 63da str r2, [r3, #60] @ 0x3c htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; 8005994: 68fb ldr r3, [r7, #12] 8005996: 6b1b ldr r3, [r3, #48] @ 0x30 8005998: 4a45 ldr r2, [pc, #276] @ (8005ab0 ) 800599a: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 800599c: 68fb ldr r3, [r7, #12] 800599e: 6b1b ldr r3, [r3, #48] @ 0x30 80059a0: 4a44 ldr r2, [pc, #272] @ (8005ab4 ) 80059a2: 64da str r2, [r3, #76] @ 0x4c /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, 80059a4: 68fb ldr r3, [r7, #12] 80059a6: 6b18 ldr r0, [r3, #48] @ 0x30 80059a8: 6879 ldr r1, [r7, #4] 80059aa: 68fb ldr r3, [r7, #12] 80059ac: 681b ldr r3, [r3, #0] 80059ae: 3340 adds r3, #64 @ 0x40 80059b0: 461a mov r2, r3 80059b2: 887b ldrh r3, [r7, #2] 80059b4: f7fc fc76 bl 80022a4 80059b8: 4603 mov r3, r0 80059ba: 2b00 cmp r3, #0 80059bc: d001 beq.n 80059c2 Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; 80059be: 2301 movs r3, #1 80059c0: e06f b.n 8005aa2 } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); 80059c2: 68fb ldr r3, [r7, #12] 80059c4: 681b ldr r3, [r3, #0] 80059c6: 68da ldr r2, [r3, #12] 80059c8: 68fb ldr r3, [r7, #12] 80059ca: 681b ldr r3, [r3, #0] 80059cc: f442 5280 orr.w r2, r2, #4096 @ 0x1000 80059d0: 60da str r2, [r3, #12] break; 80059d2: e002 b.n 80059da } default: status = HAL_ERROR; 80059d4: 2301 movs r3, #1 80059d6: 75fb strb r3, [r7, #23] break; 80059d8: bf00 nop } if (status == HAL_OK) 80059da: 7dfb ldrb r3, [r7, #23] 80059dc: 2b00 cmp r3, #0 80059de: d15f bne.n 8005aa0 { /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 80059e0: 68fb ldr r3, [r7, #12] 80059e2: 681b ldr r3, [r3, #0] 80059e4: 2201 movs r2, #1 80059e6: 68b9 ldr r1, [r7, #8] 80059e8: 4618 mov r0, r3 80059ea: f000 fe77 bl 80066dc if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 80059ee: 68fb ldr r3, [r7, #12] 80059f0: 681b ldr r3, [r3, #0] 80059f2: 4a31 ldr r2, [pc, #196] @ (8005ab8 ) 80059f4: 4293 cmp r3, r2 80059f6: d004 beq.n 8005a02 80059f8: 68fb ldr r3, [r7, #12] 80059fa: 681b ldr r3, [r3, #0] 80059fc: 4a2f ldr r2, [pc, #188] @ (8005abc ) 80059fe: 4293 cmp r3, r2 8005a00: d101 bne.n 8005a06 8005a02: 2301 movs r3, #1 8005a04: e000 b.n 8005a08 8005a06: 2300 movs r3, #0 8005a08: 2b00 cmp r3, #0 8005a0a: d007 beq.n 8005a1c { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 8005a0c: 68fb ldr r3, [r7, #12] 8005a0e: 681b ldr r3, [r3, #0] 8005a10: 6c5a ldr r2, [r3, #68] @ 0x44 8005a12: 68fb ldr r3, [r7, #12] 8005a14: 681b ldr r3, [r3, #0] 8005a16: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8005a1a: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005a1c: 68fb ldr r3, [r7, #12] 8005a1e: 681b ldr r3, [r3, #0] 8005a20: 4a25 ldr r2, [pc, #148] @ (8005ab8 ) 8005a22: 4293 cmp r3, r2 8005a24: d022 beq.n 8005a6c 8005a26: 68fb ldr r3, [r7, #12] 8005a28: 681b ldr r3, [r3, #0] 8005a2a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005a2e: d01d beq.n 8005a6c 8005a30: 68fb ldr r3, [r7, #12] 8005a32: 681b ldr r3, [r3, #0] 8005a34: 4a22 ldr r2, [pc, #136] @ (8005ac0 ) 8005a36: 4293 cmp r3, r2 8005a38: d018 beq.n 8005a6c 8005a3a: 68fb ldr r3, [r7, #12] 8005a3c: 681b ldr r3, [r3, #0] 8005a3e: 4a21 ldr r2, [pc, #132] @ (8005ac4 ) 8005a40: 4293 cmp r3, r2 8005a42: d013 beq.n 8005a6c 8005a44: 68fb ldr r3, [r7, #12] 8005a46: 681b ldr r3, [r3, #0] 8005a48: 4a1f ldr r2, [pc, #124] @ (8005ac8 ) 8005a4a: 4293 cmp r3, r2 8005a4c: d00e beq.n 8005a6c 8005a4e: 68fb ldr r3, [r7, #12] 8005a50: 681b ldr r3, [r3, #0] 8005a52: 4a1a ldr r2, [pc, #104] @ (8005abc ) 8005a54: 4293 cmp r3, r2 8005a56: d009 beq.n 8005a6c 8005a58: 68fb ldr r3, [r7, #12] 8005a5a: 681b ldr r3, [r3, #0] 8005a5c: 4a1b ldr r2, [pc, #108] @ (8005acc ) 8005a5e: 4293 cmp r3, r2 8005a60: d004 beq.n 8005a6c 8005a62: 68fb ldr r3, [r7, #12] 8005a64: 681b ldr r3, [r3, #0] 8005a66: 4a1a ldr r2, [pc, #104] @ (8005ad0 ) 8005a68: 4293 cmp r3, r2 8005a6a: d111 bne.n 8005a90 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8005a6c: 68fb ldr r3, [r7, #12] 8005a6e: 681b ldr r3, [r3, #0] 8005a70: 689b ldr r3, [r3, #8] 8005a72: f003 0307 and.w r3, r3, #7 8005a76: 613b str r3, [r7, #16] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005a78: 693b ldr r3, [r7, #16] 8005a7a: 2b06 cmp r3, #6 8005a7c: d010 beq.n 8005aa0 { __HAL_TIM_ENABLE(htim); 8005a7e: 68fb ldr r3, [r7, #12] 8005a80: 681b ldr r3, [r3, #0] 8005a82: 681a ldr r2, [r3, #0] 8005a84: 68fb ldr r3, [r7, #12] 8005a86: 681b ldr r3, [r3, #0] 8005a88: f042 0201 orr.w r2, r2, #1 8005a8c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005a8e: e007 b.n 8005aa0 } } else { __HAL_TIM_ENABLE(htim); 8005a90: 68fb ldr r3, [r7, #12] 8005a92: 681b ldr r3, [r3, #0] 8005a94: 681a ldr r2, [r3, #0] 8005a96: 68fb ldr r3, [r7, #12] 8005a98: 681b ldr r3, [r3, #0] 8005a9a: f042 0201 orr.w r2, r2, #1 8005a9e: 601a str r2, [r3, #0] } } /* Return function status */ return status; 8005aa0: 7dfb ldrb r3, [r7, #23] } 8005aa2: 4618 mov r0, r3 8005aa4: 3718 adds r7, #24 8005aa6: 46bd mov sp, r7 8005aa8: bd80 pop {r7, pc} 8005aaa: bf00 nop 8005aac: 0800611f .word 0x0800611f 8005ab0: 080061c7 .word 0x080061c7 8005ab4: 0800608d .word 0x0800608d 8005ab8: 40010000 .word 0x40010000 8005abc: 40010400 .word 0x40010400 8005ac0: 40000400 .word 0x40000400 8005ac4: 40000800 .word 0x40000800 8005ac8: 40000c00 .word 0x40000c00 8005acc: 40014000 .word 0x40014000 8005ad0: 40001800 .word 0x40001800 08005ad4 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { 8005ad4: b580 push {r7, lr} 8005ad6: b084 sub sp, #16 8005ad8: af00 add r7, sp, #0 8005ada: 6078 str r0, [r7, #4] 8005adc: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8005ade: 2300 movs r3, #0 8005ae0: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) 8005ae2: 683b ldr r3, [r7, #0] 8005ae4: 2b0c cmp r3, #12 8005ae6: d855 bhi.n 8005b94 8005ae8: a201 add r2, pc, #4 @ (adr r2, 8005af0 ) 8005aea: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005aee: bf00 nop 8005af0: 08005b25 .word 0x08005b25 8005af4: 08005b95 .word 0x08005b95 8005af8: 08005b95 .word 0x08005b95 8005afc: 08005b95 .word 0x08005b95 8005b00: 08005b41 .word 0x08005b41 8005b04: 08005b95 .word 0x08005b95 8005b08: 08005b95 .word 0x08005b95 8005b0c: 08005b95 .word 0x08005b95 8005b10: 08005b5d .word 0x08005b5d 8005b14: 08005b95 .word 0x08005b95 8005b18: 08005b95 .word 0x08005b95 8005b1c: 08005b95 .word 0x08005b95 8005b20: 08005b79 .word 0x08005b79 { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 8005b24: 687b ldr r3, [r7, #4] 8005b26: 681b ldr r3, [r3, #0] 8005b28: 68da ldr r2, [r3, #12] 8005b2a: 687b ldr r3, [r7, #4] 8005b2c: 681b ldr r3, [r3, #0] 8005b2e: f422 7200 bic.w r2, r2, #512 @ 0x200 8005b32: 60da str r2, [r3, #12] (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); 8005b34: 687b ldr r3, [r7, #4] 8005b36: 6a5b ldr r3, [r3, #36] @ 0x24 8005b38: 4618 mov r0, r3 8005b3a: f7fc fc7b bl 8002434 break; 8005b3e: e02c b.n 8005b9a } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 8005b40: 687b ldr r3, [r7, #4] 8005b42: 681b ldr r3, [r3, #0] 8005b44: 68da ldr r2, [r3, #12] 8005b46: 687b ldr r3, [r7, #4] 8005b48: 681b ldr r3, [r3, #0] 8005b4a: f422 6280 bic.w r2, r2, #1024 @ 0x400 8005b4e: 60da str r2, [r3, #12] (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); 8005b50: 687b ldr r3, [r7, #4] 8005b52: 6a9b ldr r3, [r3, #40] @ 0x28 8005b54: 4618 mov r0, r3 8005b56: f7fc fc6d bl 8002434 break; 8005b5a: e01e b.n 8005b9a } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 8005b5c: 687b ldr r3, [r7, #4] 8005b5e: 681b ldr r3, [r3, #0] 8005b60: 68da ldr r2, [r3, #12] 8005b62: 687b ldr r3, [r7, #4] 8005b64: 681b ldr r3, [r3, #0] 8005b66: f422 6200 bic.w r2, r2, #2048 @ 0x800 8005b6a: 60da str r2, [r3, #12] (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); 8005b6c: 687b ldr r3, [r7, #4] 8005b6e: 6adb ldr r3, [r3, #44] @ 0x2c 8005b70: 4618 mov r0, r3 8005b72: f7fc fc5f bl 8002434 break; 8005b76: e010 b.n 8005b9a } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); 8005b78: 687b ldr r3, [r7, #4] 8005b7a: 681b ldr r3, [r3, #0] 8005b7c: 68da ldr r2, [r3, #12] 8005b7e: 687b ldr r3, [r7, #4] 8005b80: 681b ldr r3, [r3, #0] 8005b82: f422 5280 bic.w r2, r2, #4096 @ 0x1000 8005b86: 60da str r2, [r3, #12] (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); 8005b88: 687b ldr r3, [r7, #4] 8005b8a: 6b1b ldr r3, [r3, #48] @ 0x30 8005b8c: 4618 mov r0, r3 8005b8e: f7fc fc51 bl 8002434 break; 8005b92: e002 b.n 8005b9a } default: status = HAL_ERROR; 8005b94: 2301 movs r3, #1 8005b96: 73fb strb r3, [r7, #15] break; 8005b98: bf00 nop } if (status == HAL_OK) 8005b9a: 7bfb ldrb r3, [r7, #15] 8005b9c: 2b00 cmp r3, #0 8005b9e: d161 bne.n 8005c64 { /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 8005ba0: 687b ldr r3, [r7, #4] 8005ba2: 681b ldr r3, [r3, #0] 8005ba4: 2200 movs r2, #0 8005ba6: 6839 ldr r1, [r7, #0] 8005ba8: 4618 mov r0, r3 8005baa: f000 fd97 bl 80066dc if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8005bae: 687b ldr r3, [r7, #4] 8005bb0: 681b ldr r3, [r3, #0] 8005bb2: 4a2f ldr r2, [pc, #188] @ (8005c70 ) 8005bb4: 4293 cmp r3, r2 8005bb6: d004 beq.n 8005bc2 8005bb8: 687b ldr r3, [r7, #4] 8005bba: 681b ldr r3, [r3, #0] 8005bbc: 4a2d ldr r2, [pc, #180] @ (8005c74 ) 8005bbe: 4293 cmp r3, r2 8005bc0: d101 bne.n 8005bc6 8005bc2: 2301 movs r3, #1 8005bc4: e000 b.n 8005bc8 8005bc6: 2300 movs r3, #0 8005bc8: 2b00 cmp r3, #0 8005bca: d017 beq.n 8005bfc { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); 8005bcc: 687b ldr r3, [r7, #4] 8005bce: 681b ldr r3, [r3, #0] 8005bd0: 6a1a ldr r2, [r3, #32] 8005bd2: f241 1311 movw r3, #4369 @ 0x1111 8005bd6: 4013 ands r3, r2 8005bd8: 2b00 cmp r3, #0 8005bda: d10f bne.n 8005bfc 8005bdc: 687b ldr r3, [r7, #4] 8005bde: 681b ldr r3, [r3, #0] 8005be0: 6a1a ldr r2, [r3, #32] 8005be2: f240 4344 movw r3, #1092 @ 0x444 8005be6: 4013 ands r3, r2 8005be8: 2b00 cmp r3, #0 8005bea: d107 bne.n 8005bfc 8005bec: 687b ldr r3, [r7, #4] 8005bee: 681b ldr r3, [r3, #0] 8005bf0: 6c5a ldr r2, [r3, #68] @ 0x44 8005bf2: 687b ldr r3, [r7, #4] 8005bf4: 681b ldr r3, [r3, #0] 8005bf6: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8005bfa: 645a str r2, [r3, #68] @ 0x44 } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 8005bfc: 687b ldr r3, [r7, #4] 8005bfe: 681b ldr r3, [r3, #0] 8005c00: 6a1a ldr r2, [r3, #32] 8005c02: f241 1311 movw r3, #4369 @ 0x1111 8005c06: 4013 ands r3, r2 8005c08: 2b00 cmp r3, #0 8005c0a: d10f bne.n 8005c2c 8005c0c: 687b ldr r3, [r7, #4] 8005c0e: 681b ldr r3, [r3, #0] 8005c10: 6a1a ldr r2, [r3, #32] 8005c12: f240 4344 movw r3, #1092 @ 0x444 8005c16: 4013 ands r3, r2 8005c18: 2b00 cmp r3, #0 8005c1a: d107 bne.n 8005c2c 8005c1c: 687b ldr r3, [r7, #4] 8005c1e: 681b ldr r3, [r3, #0] 8005c20: 681a ldr r2, [r3, #0] 8005c22: 687b ldr r3, [r7, #4] 8005c24: 681b ldr r3, [r3, #0] 8005c26: f022 0201 bic.w r2, r2, #1 8005c2a: 601a str r2, [r3, #0] /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); 8005c2c: 683b ldr r3, [r7, #0] 8005c2e: 2b00 cmp r3, #0 8005c30: d104 bne.n 8005c3c 8005c32: 687b ldr r3, [r7, #4] 8005c34: 2201 movs r2, #1 8005c36: f883 203e strb.w r2, [r3, #62] @ 0x3e 8005c3a: e013 b.n 8005c64 8005c3c: 683b ldr r3, [r7, #0] 8005c3e: 2b04 cmp r3, #4 8005c40: d104 bne.n 8005c4c 8005c42: 687b ldr r3, [r7, #4] 8005c44: 2201 movs r2, #1 8005c46: f883 203f strb.w r2, [r3, #63] @ 0x3f 8005c4a: e00b b.n 8005c64 8005c4c: 683b ldr r3, [r7, #0] 8005c4e: 2b08 cmp r3, #8 8005c50: d104 bne.n 8005c5c 8005c52: 687b ldr r3, [r7, #4] 8005c54: 2201 movs r2, #1 8005c56: f883 2040 strb.w r2, [r3, #64] @ 0x40 8005c5a: e003 b.n 8005c64 8005c5c: 687b ldr r3, [r7, #4] 8005c5e: 2201 movs r2, #1 8005c60: f883 2041 strb.w r2, [r3, #65] @ 0x41 } /* Return function status */ return status; 8005c64: 7bfb ldrb r3, [r7, #15] } 8005c66: 4618 mov r0, r3 8005c68: 3710 adds r7, #16 8005c6a: 46bd mov sp, r7 8005c6c: bd80 pop {r7, pc} 8005c6e: bf00 nop 8005c70: 40010000 .word 0x40010000 8005c74: 40010400 .word 0x40010400 08005c78 : * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { 8005c78: b580 push {r7, lr} 8005c7a: b086 sub sp, #24 8005c7c: af00 add r7, sp, #0 8005c7e: 6078 str r0, [r7, #4] 8005c80: 6039 str r1, [r7, #0] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) 8005c82: 687b ldr r3, [r7, #4] 8005c84: 2b00 cmp r3, #0 8005c86: d101 bne.n 8005c8c { return HAL_ERROR; 8005c88: 2301 movs r3, #1 8005c8a: e097 b.n 8005dbc assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) 8005c8c: 687b ldr r3, [r7, #4] 8005c8e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8005c92: b2db uxtb r3, r3 8005c94: 2b00 cmp r3, #0 8005c96: d106 bne.n 8005ca6 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005c98: 687b ldr r3, [r7, #4] 8005c9a: 2200 movs r2, #0 8005c9c: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); 8005ca0: 6878 ldr r0, [r7, #4] 8005ca2: f7fb fc95 bl 80015d0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005ca6: 687b ldr r3, [r7, #4] 8005ca8: 2202 movs r2, #2 8005caa: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); 8005cae: 687b ldr r3, [r7, #4] 8005cb0: 681b ldr r3, [r3, #0] 8005cb2: 689b ldr r3, [r3, #8] 8005cb4: 687a ldr r2, [r7, #4] 8005cb6: 6812 ldr r2, [r2, #0] 8005cb8: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8005cbc: f023 0307 bic.w r3, r3, #7 8005cc0: 6093 str r3, [r2, #8] /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005cc2: 687b ldr r3, [r7, #4] 8005cc4: 681a ldr r2, [r3, #0] 8005cc6: 687b ldr r3, [r7, #4] 8005cc8: 3304 adds r3, #4 8005cca: 4619 mov r1, r3 8005ccc: 4610 mov r0, r2 8005cce: f000 faaf bl 8006230 /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005cd2: 687b ldr r3, [r7, #4] 8005cd4: 681b ldr r3, [r3, #0] 8005cd6: 689b ldr r3, [r3, #8] 8005cd8: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; 8005cda: 687b ldr r3, [r7, #4] 8005cdc: 681b ldr r3, [r3, #0] 8005cde: 699b ldr r3, [r3, #24] 8005ce0: 613b str r3, [r7, #16] /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; 8005ce2: 687b ldr r3, [r7, #4] 8005ce4: 681b ldr r3, [r3, #0] 8005ce6: 6a1b ldr r3, [r3, #32] 8005ce8: 60fb str r3, [r7, #12] /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; 8005cea: 683b ldr r3, [r7, #0] 8005cec: 681b ldr r3, [r3, #0] 8005cee: 697a ldr r2, [r7, #20] 8005cf0: 4313 orrs r3, r2 8005cf2: 617b str r3, [r7, #20] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 8005cf4: 693b ldr r3, [r7, #16] 8005cf6: f423 7340 bic.w r3, r3, #768 @ 0x300 8005cfa: f023 0303 bic.w r3, r3, #3 8005cfe: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); 8005d00: 683b ldr r3, [r7, #0] 8005d02: 689a ldr r2, [r3, #8] 8005d04: 683b ldr r3, [r7, #0] 8005d06: 699b ldr r3, [r3, #24] 8005d08: 021b lsls r3, r3, #8 8005d0a: 4313 orrs r3, r2 8005d0c: 693a ldr r2, [r7, #16] 8005d0e: 4313 orrs r3, r2 8005d10: 613b str r3, [r7, #16] /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 8005d12: 693b ldr r3, [r7, #16] 8005d14: f423 6340 bic.w r3, r3, #3072 @ 0xc00 8005d18: f023 030c bic.w r3, r3, #12 8005d1c: 613b str r3, [r7, #16] tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 8005d1e: 693b ldr r3, [r7, #16] 8005d20: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8005d24: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8005d28: 613b str r3, [r7, #16] tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); 8005d2a: 683b ldr r3, [r7, #0] 8005d2c: 68da ldr r2, [r3, #12] 8005d2e: 683b ldr r3, [r7, #0] 8005d30: 69db ldr r3, [r3, #28] 8005d32: 021b lsls r3, r3, #8 8005d34: 4313 orrs r3, r2 8005d36: 693a ldr r2, [r7, #16] 8005d38: 4313 orrs r3, r2 8005d3a: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); 8005d3c: 683b ldr r3, [r7, #0] 8005d3e: 691b ldr r3, [r3, #16] 8005d40: 011a lsls r2, r3, #4 8005d42: 683b ldr r3, [r7, #0] 8005d44: 6a1b ldr r3, [r3, #32] 8005d46: 031b lsls r3, r3, #12 8005d48: 4313 orrs r3, r2 8005d4a: 693a ldr r2, [r7, #16] 8005d4c: 4313 orrs r3, r2 8005d4e: 613b str r3, [r7, #16] /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 8005d50: 68fb ldr r3, [r7, #12] 8005d52: f023 0322 bic.w r3, r3, #34 @ 0x22 8005d56: 60fb str r3, [r7, #12] tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 8005d58: 68fb ldr r3, [r7, #12] 8005d5a: f023 0388 bic.w r3, r3, #136 @ 0x88 8005d5e: 60fb str r3, [r7, #12] tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); 8005d60: 683b ldr r3, [r7, #0] 8005d62: 685a ldr r2, [r3, #4] 8005d64: 683b ldr r3, [r7, #0] 8005d66: 695b ldr r3, [r3, #20] 8005d68: 011b lsls r3, r3, #4 8005d6a: 4313 orrs r3, r2 8005d6c: 68fa ldr r2, [r7, #12] 8005d6e: 4313 orrs r3, r2 8005d70: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005d72: 687b ldr r3, [r7, #4] 8005d74: 681b ldr r3, [r3, #0] 8005d76: 697a ldr r2, [r7, #20] 8005d78: 609a str r2, [r3, #8] /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; 8005d7a: 687b ldr r3, [r7, #4] 8005d7c: 681b ldr r3, [r3, #0] 8005d7e: 693a ldr r2, [r7, #16] 8005d80: 619a str r2, [r3, #24] /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; 8005d82: 687b ldr r3, [r7, #4] 8005d84: 681b ldr r3, [r3, #0] 8005d86: 68fa ldr r2, [r7, #12] 8005d88: 621a str r2, [r3, #32] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005d8a: 687b ldr r3, [r7, #4] 8005d8c: 2201 movs r2, #1 8005d8e: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005d92: 687b ldr r3, [r7, #4] 8005d94: 2201 movs r2, #1 8005d96: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005d9a: 687b ldr r3, [r7, #4] 8005d9c: 2201 movs r2, #1 8005d9e: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005da2: 687b ldr r3, [r7, #4] 8005da4: 2201 movs r2, #1 8005da6: f883 2042 strb.w r2, [r3, #66] @ 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005daa: 687b ldr r3, [r7, #4] 8005dac: 2201 movs r2, #1 8005dae: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005db2: 687b ldr r3, [r7, #4] 8005db4: 2201 movs r2, #1 8005db6: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8005dba: 2300 movs r3, #0 } 8005dbc: 4618 mov r0, r3 8005dbe: 3718 adds r7, #24 8005dc0: 46bd mov sp, r7 8005dc2: bd80 pop {r7, pc} 08005dc4 : * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8005dc4: b580 push {r7, lr} 8005dc6: b084 sub sp, #16 8005dc8: af00 add r7, sp, #0 8005dca: 6078 str r0, [r7, #4] 8005dcc: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); 8005dce: 687b ldr r3, [r7, #4] 8005dd0: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8005dd4: 73fb strb r3, [r7, #15] HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); 8005dd6: 687b ldr r3, [r7, #4] 8005dd8: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8005ddc: 73bb strb r3, [r7, #14] HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); 8005dde: 687b ldr r3, [r7, #4] 8005de0: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8005de4: 737b strb r3, [r7, #13] HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); 8005de6: 687b ldr r3, [r7, #4] 8005de8: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 8005dec: 733b strb r3, [r7, #12] /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) 8005dee: 683b ldr r3, [r7, #0] 8005df0: 2b00 cmp r3, #0 8005df2: d110 bne.n 8005e16 { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005df4: 7bfb ldrb r3, [r7, #15] 8005df6: 2b01 cmp r3, #1 8005df8: d102 bne.n 8005e00 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) 8005dfa: 7b7b ldrb r3, [r7, #13] 8005dfc: 2b01 cmp r3, #1 8005dfe: d001 beq.n 8005e04 { return HAL_ERROR; 8005e00: 2301 movs r3, #1 8005e02: e069 b.n 8005ed8 } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005e04: 687b ldr r3, [r7, #4] 8005e06: 2202 movs r2, #2 8005e08: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005e0c: 687b ldr r3, [r7, #4] 8005e0e: 2202 movs r2, #2 8005e10: f883 2042 strb.w r2, [r3, #66] @ 0x42 8005e14: e031 b.n 8005e7a } } else if (Channel == TIM_CHANNEL_2) 8005e16: 683b ldr r3, [r7, #0] 8005e18: 2b04 cmp r3, #4 8005e1a: d110 bne.n 8005e3e { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) 8005e1c: 7bbb ldrb r3, [r7, #14] 8005e1e: 2b01 cmp r3, #1 8005e20: d102 bne.n 8005e28 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) 8005e22: 7b3b ldrb r3, [r7, #12] 8005e24: 2b01 cmp r3, #1 8005e26: d001 beq.n 8005e2c { return HAL_ERROR; 8005e28: 2301 movs r3, #1 8005e2a: e055 b.n 8005ed8 } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005e2c: 687b ldr r3, [r7, #4] 8005e2e: 2202 movs r2, #2 8005e30: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005e34: 687b ldr r3, [r7, #4] 8005e36: 2202 movs r2, #2 8005e38: f883 2043 strb.w r2, [r3, #67] @ 0x43 8005e3c: e01d b.n 8005e7a } } else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005e3e: 7bfb ldrb r3, [r7, #15] 8005e40: 2b01 cmp r3, #1 8005e42: d108 bne.n 8005e56 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) 8005e44: 7bbb ldrb r3, [r7, #14] 8005e46: 2b01 cmp r3, #1 8005e48: d105 bne.n 8005e56 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005e4a: 7b7b ldrb r3, [r7, #13] 8005e4c: 2b01 cmp r3, #1 8005e4e: d102 bne.n 8005e56 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) 8005e50: 7b3b ldrb r3, [r7, #12] 8005e52: 2b01 cmp r3, #1 8005e54: d001 beq.n 8005e5a { return HAL_ERROR; 8005e56: 2301 movs r3, #1 8005e58: e03e b.n 8005ed8 } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005e5a: 687b ldr r3, [r7, #4] 8005e5c: 2202 movs r2, #2 8005e5e: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005e62: 687b ldr r3, [r7, #4] 8005e64: 2202 movs r2, #2 8005e66: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005e6a: 687b ldr r3, [r7, #4] 8005e6c: 2202 movs r2, #2 8005e6e: f883 2042 strb.w r2, [r3, #66] @ 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005e72: 687b ldr r3, [r7, #4] 8005e74: 2202 movs r2, #2 8005e76: f883 2043 strb.w r2, [r3, #67] @ 0x43 } } /* Enable the encoder interface channels */ switch (Channel) 8005e7a: 683b ldr r3, [r7, #0] 8005e7c: 2b00 cmp r3, #0 8005e7e: d003 beq.n 8005e88 8005e80: 683b ldr r3, [r7, #0] 8005e82: 2b04 cmp r3, #4 8005e84: d008 beq.n 8005e98 8005e86: e00f b.n 8005ea8 { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 8005e88: 687b ldr r3, [r7, #4] 8005e8a: 681b ldr r3, [r3, #0] 8005e8c: 2201 movs r2, #1 8005e8e: 2100 movs r1, #0 8005e90: 4618 mov r0, r3 8005e92: f000 fc23 bl 80066dc break; 8005e96: e016 b.n 8005ec6 } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 8005e98: 687b ldr r3, [r7, #4] 8005e9a: 681b ldr r3, [r3, #0] 8005e9c: 2201 movs r2, #1 8005e9e: 2104 movs r1, #4 8005ea0: 4618 mov r0, r3 8005ea2: f000 fc1b bl 80066dc break; 8005ea6: e00e b.n 8005ec6 } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 8005ea8: 687b ldr r3, [r7, #4] 8005eaa: 681b ldr r3, [r3, #0] 8005eac: 2201 movs r2, #1 8005eae: 2100 movs r1, #0 8005eb0: 4618 mov r0, r3 8005eb2: f000 fc13 bl 80066dc TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 8005eb6: 687b ldr r3, [r7, #4] 8005eb8: 681b ldr r3, [r3, #0] 8005eba: 2201 movs r2, #1 8005ebc: 2104 movs r1, #4 8005ebe: 4618 mov r0, r3 8005ec0: f000 fc0c bl 80066dc break; 8005ec4: bf00 nop } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); 8005ec6: 687b ldr r3, [r7, #4] 8005ec8: 681b ldr r3, [r3, #0] 8005eca: 681a ldr r2, [r3, #0] 8005ecc: 687b ldr r3, [r7, #4] 8005ece: 681b ldr r3, [r3, #0] 8005ed0: f042 0201 orr.w r2, r2, #1 8005ed4: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 8005ed6: 2300 movs r3, #0 } 8005ed8: 4618 mov r0, r3 8005eda: 3710 adds r7, #16 8005edc: 46bd mov sp, r7 8005ede: bd80 pop {r7, pc} 08005ee0 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8005ee0: b580 push {r7, lr} 8005ee2: b086 sub sp, #24 8005ee4: af00 add r7, sp, #0 8005ee6: 60f8 str r0, [r7, #12] 8005ee8: 60b9 str r1, [r7, #8] 8005eea: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8005eec: 2300 movs r3, #0 8005eee: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8005ef0: 68fb ldr r3, [r7, #12] 8005ef2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005ef6: 2b01 cmp r3, #1 8005ef8: d101 bne.n 8005efe 8005efa: 2302 movs r3, #2 8005efc: e0ae b.n 800605c 8005efe: 68fb ldr r3, [r7, #12] 8005f00: 2201 movs r2, #1 8005f02: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8005f06: 687b ldr r3, [r7, #4] 8005f08: 2b0c cmp r3, #12 8005f0a: f200 809f bhi.w 800604c 8005f0e: a201 add r2, pc, #4 @ (adr r2, 8005f14 ) 8005f10: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005f14: 08005f49 .word 0x08005f49 8005f18: 0800604d .word 0x0800604d 8005f1c: 0800604d .word 0x0800604d 8005f20: 0800604d .word 0x0800604d 8005f24: 08005f89 .word 0x08005f89 8005f28: 0800604d .word 0x0800604d 8005f2c: 0800604d .word 0x0800604d 8005f30: 0800604d .word 0x0800604d 8005f34: 08005fcb .word 0x08005fcb 8005f38: 0800604d .word 0x0800604d 8005f3c: 0800604d .word 0x0800604d 8005f40: 0800604d .word 0x0800604d 8005f44: 0800600b .word 0x0800600b { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8005f48: 68fb ldr r3, [r7, #12] 8005f4a: 681b ldr r3, [r3, #0] 8005f4c: 68b9 ldr r1, [r7, #8] 8005f4e: 4618 mov r0, r3 8005f50: f000 fa14 bl 800637c /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8005f54: 68fb ldr r3, [r7, #12] 8005f56: 681b ldr r3, [r3, #0] 8005f58: 699a ldr r2, [r3, #24] 8005f5a: 68fb ldr r3, [r7, #12] 8005f5c: 681b ldr r3, [r3, #0] 8005f5e: f042 0208 orr.w r2, r2, #8 8005f62: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8005f64: 68fb ldr r3, [r7, #12] 8005f66: 681b ldr r3, [r3, #0] 8005f68: 699a ldr r2, [r3, #24] 8005f6a: 68fb ldr r3, [r7, #12] 8005f6c: 681b ldr r3, [r3, #0] 8005f6e: f022 0204 bic.w r2, r2, #4 8005f72: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8005f74: 68fb ldr r3, [r7, #12] 8005f76: 681b ldr r3, [r3, #0] 8005f78: 6999 ldr r1, [r3, #24] 8005f7a: 68bb ldr r3, [r7, #8] 8005f7c: 691a ldr r2, [r3, #16] 8005f7e: 68fb ldr r3, [r7, #12] 8005f80: 681b ldr r3, [r3, #0] 8005f82: 430a orrs r2, r1 8005f84: 619a str r2, [r3, #24] break; 8005f86: e064 b.n 8006052 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8005f88: 68fb ldr r3, [r7, #12] 8005f8a: 681b ldr r3, [r3, #0] 8005f8c: 68b9 ldr r1, [r7, #8] 8005f8e: 4618 mov r0, r3 8005f90: f000 fa64 bl 800645c /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8005f94: 68fb ldr r3, [r7, #12] 8005f96: 681b ldr r3, [r3, #0] 8005f98: 699a ldr r2, [r3, #24] 8005f9a: 68fb ldr r3, [r7, #12] 8005f9c: 681b ldr r3, [r3, #0] 8005f9e: f442 6200 orr.w r2, r2, #2048 @ 0x800 8005fa2: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8005fa4: 68fb ldr r3, [r7, #12] 8005fa6: 681b ldr r3, [r3, #0] 8005fa8: 699a ldr r2, [r3, #24] 8005faa: 68fb ldr r3, [r7, #12] 8005fac: 681b ldr r3, [r3, #0] 8005fae: f422 6280 bic.w r2, r2, #1024 @ 0x400 8005fb2: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8005fb4: 68fb ldr r3, [r7, #12] 8005fb6: 681b ldr r3, [r3, #0] 8005fb8: 6999 ldr r1, [r3, #24] 8005fba: 68bb ldr r3, [r7, #8] 8005fbc: 691b ldr r3, [r3, #16] 8005fbe: 021a lsls r2, r3, #8 8005fc0: 68fb ldr r3, [r7, #12] 8005fc2: 681b ldr r3, [r3, #0] 8005fc4: 430a orrs r2, r1 8005fc6: 619a str r2, [r3, #24] break; 8005fc8: e043 b.n 8006052 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8005fca: 68fb ldr r3, [r7, #12] 8005fcc: 681b ldr r3, [r3, #0] 8005fce: 68b9 ldr r1, [r7, #8] 8005fd0: 4618 mov r0, r3 8005fd2: f000 fab9 bl 8006548 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 8005fd6: 68fb ldr r3, [r7, #12] 8005fd8: 681b ldr r3, [r3, #0] 8005fda: 69da ldr r2, [r3, #28] 8005fdc: 68fb ldr r3, [r7, #12] 8005fde: 681b ldr r3, [r3, #0] 8005fe0: f042 0208 orr.w r2, r2, #8 8005fe4: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 8005fe6: 68fb ldr r3, [r7, #12] 8005fe8: 681b ldr r3, [r3, #0] 8005fea: 69da ldr r2, [r3, #28] 8005fec: 68fb ldr r3, [r7, #12] 8005fee: 681b ldr r3, [r3, #0] 8005ff0: f022 0204 bic.w r2, r2, #4 8005ff4: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 8005ff6: 68fb ldr r3, [r7, #12] 8005ff8: 681b ldr r3, [r3, #0] 8005ffa: 69d9 ldr r1, [r3, #28] 8005ffc: 68bb ldr r3, [r7, #8] 8005ffe: 691a ldr r2, [r3, #16] 8006000: 68fb ldr r3, [r7, #12] 8006002: 681b ldr r3, [r3, #0] 8006004: 430a orrs r2, r1 8006006: 61da str r2, [r3, #28] break; 8006008: e023 b.n 8006052 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 800600a: 68fb ldr r3, [r7, #12] 800600c: 681b ldr r3, [r3, #0] 800600e: 68b9 ldr r1, [r7, #8] 8006010: 4618 mov r0, r3 8006012: f000 fb0d bl 8006630 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 8006016: 68fb ldr r3, [r7, #12] 8006018: 681b ldr r3, [r3, #0] 800601a: 69da ldr r2, [r3, #28] 800601c: 68fb ldr r3, [r7, #12] 800601e: 681b ldr r3, [r3, #0] 8006020: f442 6200 orr.w r2, r2, #2048 @ 0x800 8006024: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 8006026: 68fb ldr r3, [r7, #12] 8006028: 681b ldr r3, [r3, #0] 800602a: 69da ldr r2, [r3, #28] 800602c: 68fb ldr r3, [r7, #12] 800602e: 681b ldr r3, [r3, #0] 8006030: f422 6280 bic.w r2, r2, #1024 @ 0x400 8006034: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 8006036: 68fb ldr r3, [r7, #12] 8006038: 681b ldr r3, [r3, #0] 800603a: 69d9 ldr r1, [r3, #28] 800603c: 68bb ldr r3, [r7, #8] 800603e: 691b ldr r3, [r3, #16] 8006040: 021a lsls r2, r3, #8 8006042: 68fb ldr r3, [r7, #12] 8006044: 681b ldr r3, [r3, #0] 8006046: 430a orrs r2, r1 8006048: 61da str r2, [r3, #28] break; 800604a: e002 b.n 8006052 } default: status = HAL_ERROR; 800604c: 2301 movs r3, #1 800604e: 75fb strb r3, [r7, #23] break; 8006050: bf00 nop } __HAL_UNLOCK(htim); 8006052: 68fb ldr r3, [r7, #12] 8006054: 2200 movs r2, #0 8006056: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800605a: 7dfb ldrb r3, [r7, #23] } 800605c: 4618 mov r0, r3 800605e: 3718 adds r7, #24 8006060: 46bd mov sp, r7 8006062: bd80 pop {r7, pc} 08006064 : * @brief PWM Pulse finished half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) { 8006064: b480 push {r7} 8006066: b083 sub sp, #12 8006068: af00 add r7, sp, #0 800606a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file */ } 800606c: bf00 nop 800606e: 370c adds r7, #12 8006070: 46bd mov sp, r7 8006072: f85d 7b04 ldr.w r7, [sp], #4 8006076: 4770 bx lr 08006078 : * @brief Timer error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) { 8006078: b480 push {r7} 800607a: b083 sub sp, #12 800607c: af00 add r7, sp, #0 800607e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_ErrorCallback could be implemented in the user file */ } 8006080: bf00 nop 8006082: 370c adds r7, #12 8006084: 46bd mov sp, r7 8006086: f85d 7b04 ldr.w r7, [sp], #4 800608a: 4770 bx lr 0800608c : * @brief TIM DMA error callback * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMAError(DMA_HandleTypeDef *hdma) { 800608c: b580 push {r7, lr} 800608e: b084 sub sp, #16 8006090: af00 add r7, sp, #0 8006092: 6078 str r0, [r7, #4] TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006094: 687b ldr r3, [r7, #4] 8006096: 6b9b ldr r3, [r3, #56] @ 0x38 8006098: 60fb str r3, [r7, #12] if (hdma == htim->hdma[TIM_DMA_ID_CC1]) 800609a: 68fb ldr r3, [r7, #12] 800609c: 6a5b ldr r3, [r3, #36] @ 0x24 800609e: 687a ldr r2, [r7, #4] 80060a0: 429a cmp r2, r3 80060a2: d107 bne.n 80060b4 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80060a4: 68fb ldr r3, [r7, #12] 80060a6: 2201 movs r2, #1 80060a8: 771a strb r2, [r3, #28] TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 80060aa: 68fb ldr r3, [r7, #12] 80060ac: 2201 movs r2, #1 80060ae: f883 203e strb.w r2, [r3, #62] @ 0x3e 80060b2: e02a b.n 800610a } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) 80060b4: 68fb ldr r3, [r7, #12] 80060b6: 6a9b ldr r3, [r3, #40] @ 0x28 80060b8: 687a ldr r2, [r7, #4] 80060ba: 429a cmp r2, r3 80060bc: d107 bne.n 80060ce { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80060be: 68fb ldr r3, [r7, #12] 80060c0: 2202 movs r2, #2 80060c2: 771a strb r2, [r3, #28] TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 80060c4: 68fb ldr r3, [r7, #12] 80060c6: 2201 movs r2, #1 80060c8: f883 203f strb.w r2, [r3, #63] @ 0x3f 80060cc: e01d b.n 800610a } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) 80060ce: 68fb ldr r3, [r7, #12] 80060d0: 6adb ldr r3, [r3, #44] @ 0x2c 80060d2: 687a ldr r2, [r7, #4] 80060d4: 429a cmp r2, r3 80060d6: d107 bne.n 80060e8 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 80060d8: 68fb ldr r3, [r7, #12] 80060da: 2204 movs r2, #4 80060dc: 771a strb r2, [r3, #28] TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); 80060de: 68fb ldr r3, [r7, #12] 80060e0: 2201 movs r2, #1 80060e2: f883 2040 strb.w r2, [r3, #64] @ 0x40 80060e6: e010 b.n 800610a } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) 80060e8: 68fb ldr r3, [r7, #12] 80060ea: 6b1b ldr r3, [r3, #48] @ 0x30 80060ec: 687a ldr r2, [r7, #4] 80060ee: 429a cmp r2, r3 80060f0: d107 bne.n 8006102 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80060f2: 68fb ldr r3, [r7, #12] 80060f4: 2208 movs r2, #8 80060f6: 771a strb r2, [r3, #28] TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); 80060f8: 68fb ldr r3, [r7, #12] 80060fa: 2201 movs r2, #1 80060fc: f883 2041 strb.w r2, [r3, #65] @ 0x41 8006100: e003 b.n 800610a } else { htim->State = HAL_TIM_STATE_READY; 8006102: 68fb ldr r3, [r7, #12] 8006104: 2201 movs r2, #1 8006106: f883 203d strb.w r2, [r3, #61] @ 0x3d } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); 800610a: 68f8 ldr r0, [r7, #12] 800610c: f7ff ffb4 bl 8006078 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8006110: 68fb ldr r3, [r7, #12] 8006112: 2200 movs r2, #0 8006114: 771a strb r2, [r3, #28] } 8006116: bf00 nop 8006118: 3710 adds r7, #16 800611a: 46bd mov sp, r7 800611c: bd80 pop {r7, pc} 0800611e : * @brief TIM DMA Delay Pulse complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { 800611e: b580 push {r7, lr} 8006120: b084 sub sp, #16 8006122: af00 add r7, sp, #0 8006124: 6078 str r0, [r7, #4] TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006126: 687b ldr r3, [r7, #4] 8006128: 6b9b ldr r3, [r3, #56] @ 0x38 800612a: 60fb str r3, [r7, #12] if (hdma == htim->hdma[TIM_DMA_ID_CC1]) 800612c: 68fb ldr r3, [r7, #12] 800612e: 6a5b ldr r3, [r3, #36] @ 0x24 8006130: 687a ldr r2, [r7, #4] 8006132: 429a cmp r2, r3 8006134: d10b bne.n 800614e { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8006136: 68fb ldr r3, [r7, #12] 8006138: 2201 movs r2, #1 800613a: 771a strb r2, [r3, #28] if (hdma->Init.Mode == DMA_NORMAL) 800613c: 687b ldr r3, [r7, #4] 800613e: 69db ldr r3, [r3, #28] 8006140: 2b00 cmp r3, #0 8006142: d136 bne.n 80061b2 { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8006144: 68fb ldr r3, [r7, #12] 8006146: 2201 movs r2, #1 8006148: f883 203e strb.w r2, [r3, #62] @ 0x3e 800614c: e031 b.n 80061b2 } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) 800614e: 68fb ldr r3, [r7, #12] 8006150: 6a9b ldr r3, [r3, #40] @ 0x28 8006152: 687a ldr r2, [r7, #4] 8006154: 429a cmp r2, r3 8006156: d10b bne.n 8006170 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8006158: 68fb ldr r3, [r7, #12] 800615a: 2202 movs r2, #2 800615c: 771a strb r2, [r3, #28] if (hdma->Init.Mode == DMA_NORMAL) 800615e: 687b ldr r3, [r7, #4] 8006160: 69db ldr r3, [r3, #28] 8006162: 2b00 cmp r3, #0 8006164: d125 bne.n 80061b2 { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8006166: 68fb ldr r3, [r7, #12] 8006168: 2201 movs r2, #1 800616a: f883 203f strb.w r2, [r3, #63] @ 0x3f 800616e: e020 b.n 80061b2 } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) 8006170: 68fb ldr r3, [r7, #12] 8006172: 6adb ldr r3, [r3, #44] @ 0x2c 8006174: 687a ldr r2, [r7, #4] 8006176: 429a cmp r2, r3 8006178: d10b bne.n 8006192 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800617a: 68fb ldr r3, [r7, #12] 800617c: 2204 movs r2, #4 800617e: 771a strb r2, [r3, #28] if (hdma->Init.Mode == DMA_NORMAL) 8006180: 687b ldr r3, [r7, #4] 8006182: 69db ldr r3, [r3, #28] 8006184: 2b00 cmp r3, #0 8006186: d114 bne.n 80061b2 { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); 8006188: 68fb ldr r3, [r7, #12] 800618a: 2201 movs r2, #1 800618c: f883 2040 strb.w r2, [r3, #64] @ 0x40 8006190: e00f b.n 80061b2 } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) 8006192: 68fb ldr r3, [r7, #12] 8006194: 6b1b ldr r3, [r3, #48] @ 0x30 8006196: 687a ldr r2, [r7, #4] 8006198: 429a cmp r2, r3 800619a: d10a bne.n 80061b2 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800619c: 68fb ldr r3, [r7, #12] 800619e: 2208 movs r2, #8 80061a0: 771a strb r2, [r3, #28] if (hdma->Init.Mode == DMA_NORMAL) 80061a2: 687b ldr r3, [r7, #4] 80061a4: 69db ldr r3, [r3, #28] 80061a6: 2b00 cmp r3, #0 80061a8: d103 bne.n 80061b2 { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); 80061aa: 68fb ldr r3, [r7, #12] 80061ac: 2201 movs r2, #1 80061ae: f883 2041 strb.w r2, [r3, #65] @ 0x41 } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_PWM_PulseFinishedCallback(htim); 80061b2: 68f8 ldr r0, [r7, #12] 80061b4: f7fb f9a4 bl 8001500 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80061b8: 68fb ldr r3, [r7, #12] 80061ba: 2200 movs r2, #0 80061bc: 771a strb r2, [r3, #28] } 80061be: bf00 nop 80061c0: 3710 adds r7, #16 80061c2: 46bd mov sp, r7 80061c4: bd80 pop {r7, pc} 080061c6 : * @brief TIM DMA Delay Pulse half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { 80061c6: b580 push {r7, lr} 80061c8: b084 sub sp, #16 80061ca: af00 add r7, sp, #0 80061cc: 6078 str r0, [r7, #4] TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80061ce: 687b ldr r3, [r7, #4] 80061d0: 6b9b ldr r3, [r3, #56] @ 0x38 80061d2: 60fb str r3, [r7, #12] if (hdma == htim->hdma[TIM_DMA_ID_CC1]) 80061d4: 68fb ldr r3, [r7, #12] 80061d6: 6a5b ldr r3, [r3, #36] @ 0x24 80061d8: 687a ldr r2, [r7, #4] 80061da: 429a cmp r2, r3 80061dc: d103 bne.n 80061e6 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80061de: 68fb ldr r3, [r7, #12] 80061e0: 2201 movs r2, #1 80061e2: 771a strb r2, [r3, #28] 80061e4: e019 b.n 800621a } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) 80061e6: 68fb ldr r3, [r7, #12] 80061e8: 6a9b ldr r3, [r3, #40] @ 0x28 80061ea: 687a ldr r2, [r7, #4] 80061ec: 429a cmp r2, r3 80061ee: d103 bne.n 80061f8 { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80061f0: 68fb ldr r3, [r7, #12] 80061f2: 2202 movs r2, #2 80061f4: 771a strb r2, [r3, #28] 80061f6: e010 b.n 800621a } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) 80061f8: 68fb ldr r3, [r7, #12] 80061fa: 6adb ldr r3, [r3, #44] @ 0x2c 80061fc: 687a ldr r2, [r7, #4] 80061fe: 429a cmp r2, r3 8006200: d103 bne.n 800620a { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8006202: 68fb ldr r3, [r7, #12] 8006204: 2204 movs r2, #4 8006206: 771a strb r2, [r3, #28] 8006208: e007 b.n 800621a } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) 800620a: 68fb ldr r3, [r7, #12] 800620c: 6b1b ldr r3, [r3, #48] @ 0x30 800620e: 687a ldr r2, [r7, #4] 8006210: 429a cmp r2, r3 8006212: d102 bne.n 800621a { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8006214: 68fb ldr r3, [r7, #12] 8006216: 2208 movs r2, #8 8006218: 771a strb r2, [r3, #28] } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedHalfCpltCallback(htim); #else HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); 800621a: 68f8 ldr r0, [r7, #12] 800621c: f7ff ff22 bl 8006064 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8006220: 68fb ldr r3, [r7, #12] 8006222: 2200 movs r2, #0 8006224: 771a strb r2, [r3, #28] } 8006226: bf00 nop 8006228: 3710 adds r7, #16 800622a: 46bd mov sp, r7 800622c: bd80 pop {r7, pc} ... 08006230 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8006230: b480 push {r7} 8006232: b085 sub sp, #20 8006234: af00 add r7, sp, #0 8006236: 6078 str r0, [r7, #4] 8006238: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800623a: 687b ldr r3, [r7, #4] 800623c: 681b ldr r3, [r3, #0] 800623e: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8006240: 687b ldr r3, [r7, #4] 8006242: 4a43 ldr r2, [pc, #268] @ (8006350 ) 8006244: 4293 cmp r3, r2 8006246: d013 beq.n 8006270 8006248: 687b ldr r3, [r7, #4] 800624a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800624e: d00f beq.n 8006270 8006250: 687b ldr r3, [r7, #4] 8006252: 4a40 ldr r2, [pc, #256] @ (8006354 ) 8006254: 4293 cmp r3, r2 8006256: d00b beq.n 8006270 8006258: 687b ldr r3, [r7, #4] 800625a: 4a3f ldr r2, [pc, #252] @ (8006358 ) 800625c: 4293 cmp r3, r2 800625e: d007 beq.n 8006270 8006260: 687b ldr r3, [r7, #4] 8006262: 4a3e ldr r2, [pc, #248] @ (800635c ) 8006264: 4293 cmp r3, r2 8006266: d003 beq.n 8006270 8006268: 687b ldr r3, [r7, #4] 800626a: 4a3d ldr r2, [pc, #244] @ (8006360 ) 800626c: 4293 cmp r3, r2 800626e: d108 bne.n 8006282 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8006270: 68fb ldr r3, [r7, #12] 8006272: f023 0370 bic.w r3, r3, #112 @ 0x70 8006276: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8006278: 683b ldr r3, [r7, #0] 800627a: 685b ldr r3, [r3, #4] 800627c: 68fa ldr r2, [r7, #12] 800627e: 4313 orrs r3, r2 8006280: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8006282: 687b ldr r3, [r7, #4] 8006284: 4a32 ldr r2, [pc, #200] @ (8006350 ) 8006286: 4293 cmp r3, r2 8006288: d02b beq.n 80062e2 800628a: 687b ldr r3, [r7, #4] 800628c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006290: d027 beq.n 80062e2 8006292: 687b ldr r3, [r7, #4] 8006294: 4a2f ldr r2, [pc, #188] @ (8006354 ) 8006296: 4293 cmp r3, r2 8006298: d023 beq.n 80062e2 800629a: 687b ldr r3, [r7, #4] 800629c: 4a2e ldr r2, [pc, #184] @ (8006358 ) 800629e: 4293 cmp r3, r2 80062a0: d01f beq.n 80062e2 80062a2: 687b ldr r3, [r7, #4] 80062a4: 4a2d ldr r2, [pc, #180] @ (800635c ) 80062a6: 4293 cmp r3, r2 80062a8: d01b beq.n 80062e2 80062aa: 687b ldr r3, [r7, #4] 80062ac: 4a2c ldr r2, [pc, #176] @ (8006360 ) 80062ae: 4293 cmp r3, r2 80062b0: d017 beq.n 80062e2 80062b2: 687b ldr r3, [r7, #4] 80062b4: 4a2b ldr r2, [pc, #172] @ (8006364 ) 80062b6: 4293 cmp r3, r2 80062b8: d013 beq.n 80062e2 80062ba: 687b ldr r3, [r7, #4] 80062bc: 4a2a ldr r2, [pc, #168] @ (8006368 ) 80062be: 4293 cmp r3, r2 80062c0: d00f beq.n 80062e2 80062c2: 687b ldr r3, [r7, #4] 80062c4: 4a29 ldr r2, [pc, #164] @ (800636c ) 80062c6: 4293 cmp r3, r2 80062c8: d00b beq.n 80062e2 80062ca: 687b ldr r3, [r7, #4] 80062cc: 4a28 ldr r2, [pc, #160] @ (8006370 ) 80062ce: 4293 cmp r3, r2 80062d0: d007 beq.n 80062e2 80062d2: 687b ldr r3, [r7, #4] 80062d4: 4a27 ldr r2, [pc, #156] @ (8006374 ) 80062d6: 4293 cmp r3, r2 80062d8: d003 beq.n 80062e2 80062da: 687b ldr r3, [r7, #4] 80062dc: 4a26 ldr r2, [pc, #152] @ (8006378 ) 80062de: 4293 cmp r3, r2 80062e0: d108 bne.n 80062f4 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80062e2: 68fb ldr r3, [r7, #12] 80062e4: f423 7340 bic.w r3, r3, #768 @ 0x300 80062e8: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80062ea: 683b ldr r3, [r7, #0] 80062ec: 68db ldr r3, [r3, #12] 80062ee: 68fa ldr r2, [r7, #12] 80062f0: 4313 orrs r3, r2 80062f2: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80062f4: 68fb ldr r3, [r7, #12] 80062f6: f023 0280 bic.w r2, r3, #128 @ 0x80 80062fa: 683b ldr r3, [r7, #0] 80062fc: 695b ldr r3, [r3, #20] 80062fe: 4313 orrs r3, r2 8006300: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8006302: 683b ldr r3, [r7, #0] 8006304: 689a ldr r2, [r3, #8] 8006306: 687b ldr r3, [r7, #4] 8006308: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800630a: 683b ldr r3, [r7, #0] 800630c: 681a ldr r2, [r3, #0] 800630e: 687b ldr r3, [r7, #4] 8006310: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8006312: 687b ldr r3, [r7, #4] 8006314: 4a0e ldr r2, [pc, #56] @ (8006350 ) 8006316: 4293 cmp r3, r2 8006318: d003 beq.n 8006322 800631a: 687b ldr r3, [r7, #4] 800631c: 4a10 ldr r2, [pc, #64] @ (8006360 ) 800631e: 4293 cmp r3, r2 8006320: d103 bne.n 800632a { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8006322: 683b ldr r3, [r7, #0] 8006324: 691a ldr r2, [r3, #16] 8006326: 687b ldr r3, [r7, #4] 8006328: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 800632a: 687b ldr r3, [r7, #4] 800632c: 681b ldr r3, [r3, #0] 800632e: f043 0204 orr.w r2, r3, #4 8006332: 687b ldr r3, [r7, #4] 8006334: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8006336: 687b ldr r3, [r7, #4] 8006338: 2201 movs r2, #1 800633a: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 800633c: 687b ldr r3, [r7, #4] 800633e: 68fa ldr r2, [r7, #12] 8006340: 601a str r2, [r3, #0] } 8006342: bf00 nop 8006344: 3714 adds r7, #20 8006346: 46bd mov sp, r7 8006348: f85d 7b04 ldr.w r7, [sp], #4 800634c: 4770 bx lr 800634e: bf00 nop 8006350: 40010000 .word 0x40010000 8006354: 40000400 .word 0x40000400 8006358: 40000800 .word 0x40000800 800635c: 40000c00 .word 0x40000c00 8006360: 40010400 .word 0x40010400 8006364: 40014000 .word 0x40014000 8006368: 40014400 .word 0x40014400 800636c: 40014800 .word 0x40014800 8006370: 40001800 .word 0x40001800 8006374: 40001c00 .word 0x40001c00 8006378: 40002000 .word 0x40002000 0800637c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800637c: b480 push {r7} 800637e: b087 sub sp, #28 8006380: af00 add r7, sp, #0 8006382: 6078 str r0, [r7, #4] 8006384: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8006386: 687b ldr r3, [r7, #4] 8006388: 6a1b ldr r3, [r3, #32] 800638a: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 800638c: 687b ldr r3, [r7, #4] 800638e: 6a1b ldr r3, [r3, #32] 8006390: f023 0201 bic.w r2, r3, #1 8006394: 687b ldr r3, [r7, #4] 8006396: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8006398: 687b ldr r3, [r7, #4] 800639a: 685b ldr r3, [r3, #4] 800639c: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800639e: 687b ldr r3, [r7, #4] 80063a0: 699b ldr r3, [r3, #24] 80063a2: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80063a4: 68fb ldr r3, [r7, #12] 80063a6: f023 0370 bic.w r3, r3, #112 @ 0x70 80063aa: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80063ac: 68fb ldr r3, [r7, #12] 80063ae: f023 0303 bic.w r3, r3, #3 80063b2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80063b4: 683b ldr r3, [r7, #0] 80063b6: 681b ldr r3, [r3, #0] 80063b8: 68fa ldr r2, [r7, #12] 80063ba: 4313 orrs r3, r2 80063bc: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 80063be: 697b ldr r3, [r7, #20] 80063c0: f023 0302 bic.w r3, r3, #2 80063c4: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 80063c6: 683b ldr r3, [r7, #0] 80063c8: 689b ldr r3, [r3, #8] 80063ca: 697a ldr r2, [r7, #20] 80063cc: 4313 orrs r3, r2 80063ce: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 80063d0: 687b ldr r3, [r7, #4] 80063d2: 4a20 ldr r2, [pc, #128] @ (8006454 ) 80063d4: 4293 cmp r3, r2 80063d6: d003 beq.n 80063e0 80063d8: 687b ldr r3, [r7, #4] 80063da: 4a1f ldr r2, [pc, #124] @ (8006458 ) 80063dc: 4293 cmp r3, r2 80063de: d10c bne.n 80063fa { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 80063e0: 697b ldr r3, [r7, #20] 80063e2: f023 0308 bic.w r3, r3, #8 80063e6: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 80063e8: 683b ldr r3, [r7, #0] 80063ea: 68db ldr r3, [r3, #12] 80063ec: 697a ldr r2, [r7, #20] 80063ee: 4313 orrs r3, r2 80063f0: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 80063f2: 697b ldr r3, [r7, #20] 80063f4: f023 0304 bic.w r3, r3, #4 80063f8: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80063fa: 687b ldr r3, [r7, #4] 80063fc: 4a15 ldr r2, [pc, #84] @ (8006454 ) 80063fe: 4293 cmp r3, r2 8006400: d003 beq.n 800640a 8006402: 687b ldr r3, [r7, #4] 8006404: 4a14 ldr r2, [pc, #80] @ (8006458 ) 8006406: 4293 cmp r3, r2 8006408: d111 bne.n 800642e /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 800640a: 693b ldr r3, [r7, #16] 800640c: f423 7380 bic.w r3, r3, #256 @ 0x100 8006410: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 8006412: 693b ldr r3, [r7, #16] 8006414: f423 7300 bic.w r3, r3, #512 @ 0x200 8006418: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 800641a: 683b ldr r3, [r7, #0] 800641c: 695b ldr r3, [r3, #20] 800641e: 693a ldr r2, [r7, #16] 8006420: 4313 orrs r3, r2 8006422: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8006424: 683b ldr r3, [r7, #0] 8006426: 699b ldr r3, [r3, #24] 8006428: 693a ldr r2, [r7, #16] 800642a: 4313 orrs r3, r2 800642c: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800642e: 687b ldr r3, [r7, #4] 8006430: 693a ldr r2, [r7, #16] 8006432: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8006434: 687b ldr r3, [r7, #4] 8006436: 68fa ldr r2, [r7, #12] 8006438: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 800643a: 683b ldr r3, [r7, #0] 800643c: 685a ldr r2, [r3, #4] 800643e: 687b ldr r3, [r7, #4] 8006440: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8006442: 687b ldr r3, [r7, #4] 8006444: 697a ldr r2, [r7, #20] 8006446: 621a str r2, [r3, #32] } 8006448: bf00 nop 800644a: 371c adds r7, #28 800644c: 46bd mov sp, r7 800644e: f85d 7b04 ldr.w r7, [sp], #4 8006452: 4770 bx lr 8006454: 40010000 .word 0x40010000 8006458: 40010400 .word 0x40010400 0800645c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800645c: b480 push {r7} 800645e: b087 sub sp, #28 8006460: af00 add r7, sp, #0 8006462: 6078 str r0, [r7, #4] 8006464: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8006466: 687b ldr r3, [r7, #4] 8006468: 6a1b ldr r3, [r3, #32] 800646a: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 800646c: 687b ldr r3, [r7, #4] 800646e: 6a1b ldr r3, [r3, #32] 8006470: f023 0210 bic.w r2, r3, #16 8006474: 687b ldr r3, [r7, #4] 8006476: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8006478: 687b ldr r3, [r7, #4] 800647a: 685b ldr r3, [r3, #4] 800647c: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800647e: 687b ldr r3, [r7, #4] 8006480: 699b ldr r3, [r3, #24] 8006482: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8006484: 68fb ldr r3, [r7, #12] 8006486: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800648a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 800648c: 68fb ldr r3, [r7, #12] 800648e: f423 7340 bic.w r3, r3, #768 @ 0x300 8006492: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8006494: 683b ldr r3, [r7, #0] 8006496: 681b ldr r3, [r3, #0] 8006498: 021b lsls r3, r3, #8 800649a: 68fa ldr r2, [r7, #12] 800649c: 4313 orrs r3, r2 800649e: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80064a0: 697b ldr r3, [r7, #20] 80064a2: f023 0320 bic.w r3, r3, #32 80064a6: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80064a8: 683b ldr r3, [r7, #0] 80064aa: 689b ldr r3, [r3, #8] 80064ac: 011b lsls r3, r3, #4 80064ae: 697a ldr r2, [r7, #20] 80064b0: 4313 orrs r3, r2 80064b2: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80064b4: 687b ldr r3, [r7, #4] 80064b6: 4a22 ldr r2, [pc, #136] @ (8006540 ) 80064b8: 4293 cmp r3, r2 80064ba: d003 beq.n 80064c4 80064bc: 687b ldr r3, [r7, #4] 80064be: 4a21 ldr r2, [pc, #132] @ (8006544 ) 80064c0: 4293 cmp r3, r2 80064c2: d10d bne.n 80064e0 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 80064c4: 697b ldr r3, [r7, #20] 80064c6: f023 0380 bic.w r3, r3, #128 @ 0x80 80064ca: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 80064cc: 683b ldr r3, [r7, #0] 80064ce: 68db ldr r3, [r3, #12] 80064d0: 011b lsls r3, r3, #4 80064d2: 697a ldr r2, [r7, #20] 80064d4: 4313 orrs r3, r2 80064d6: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 80064d8: 697b ldr r3, [r7, #20] 80064da: f023 0340 bic.w r3, r3, #64 @ 0x40 80064de: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80064e0: 687b ldr r3, [r7, #4] 80064e2: 4a17 ldr r2, [pc, #92] @ (8006540 ) 80064e4: 4293 cmp r3, r2 80064e6: d003 beq.n 80064f0 80064e8: 687b ldr r3, [r7, #4] 80064ea: 4a16 ldr r2, [pc, #88] @ (8006544 ) 80064ec: 4293 cmp r3, r2 80064ee: d113 bne.n 8006518 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 80064f0: 693b ldr r3, [r7, #16] 80064f2: f423 6380 bic.w r3, r3, #1024 @ 0x400 80064f6: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 80064f8: 693b ldr r3, [r7, #16] 80064fa: f423 6300 bic.w r3, r3, #2048 @ 0x800 80064fe: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8006500: 683b ldr r3, [r7, #0] 8006502: 695b ldr r3, [r3, #20] 8006504: 009b lsls r3, r3, #2 8006506: 693a ldr r2, [r7, #16] 8006508: 4313 orrs r3, r2 800650a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 800650c: 683b ldr r3, [r7, #0] 800650e: 699b ldr r3, [r3, #24] 8006510: 009b lsls r3, r3, #2 8006512: 693a ldr r2, [r7, #16] 8006514: 4313 orrs r3, r2 8006516: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8006518: 687b ldr r3, [r7, #4] 800651a: 693a ldr r2, [r7, #16] 800651c: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800651e: 687b ldr r3, [r7, #4] 8006520: 68fa ldr r2, [r7, #12] 8006522: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8006524: 683b ldr r3, [r7, #0] 8006526: 685a ldr r2, [r3, #4] 8006528: 687b ldr r3, [r7, #4] 800652a: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800652c: 687b ldr r3, [r7, #4] 800652e: 697a ldr r2, [r7, #20] 8006530: 621a str r2, [r3, #32] } 8006532: bf00 nop 8006534: 371c adds r7, #28 8006536: 46bd mov sp, r7 8006538: f85d 7b04 ldr.w r7, [sp], #4 800653c: 4770 bx lr 800653e: bf00 nop 8006540: 40010000 .word 0x40010000 8006544: 40010400 .word 0x40010400 08006548 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8006548: b480 push {r7} 800654a: b087 sub sp, #28 800654c: af00 add r7, sp, #0 800654e: 6078 str r0, [r7, #4] 8006550: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8006552: 687b ldr r3, [r7, #4] 8006554: 6a1b ldr r3, [r3, #32] 8006556: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8006558: 687b ldr r3, [r7, #4] 800655a: 6a1b ldr r3, [r3, #32] 800655c: f423 7280 bic.w r2, r3, #256 @ 0x100 8006560: 687b ldr r3, [r7, #4] 8006562: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8006564: 687b ldr r3, [r7, #4] 8006566: 685b ldr r3, [r3, #4] 8006568: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800656a: 687b ldr r3, [r7, #4] 800656c: 69db ldr r3, [r3, #28] 800656e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8006570: 68fb ldr r3, [r7, #12] 8006572: f023 0370 bic.w r3, r3, #112 @ 0x70 8006576: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8006578: 68fb ldr r3, [r7, #12] 800657a: f023 0303 bic.w r3, r3, #3 800657e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8006580: 683b ldr r3, [r7, #0] 8006582: 681b ldr r3, [r3, #0] 8006584: 68fa ldr r2, [r7, #12] 8006586: 4313 orrs r3, r2 8006588: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 800658a: 697b ldr r3, [r7, #20] 800658c: f423 7300 bic.w r3, r3, #512 @ 0x200 8006590: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8006592: 683b ldr r3, [r7, #0] 8006594: 689b ldr r3, [r3, #8] 8006596: 021b lsls r3, r3, #8 8006598: 697a ldr r2, [r7, #20] 800659a: 4313 orrs r3, r2 800659c: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 800659e: 687b ldr r3, [r7, #4] 80065a0: 4a21 ldr r2, [pc, #132] @ (8006628 ) 80065a2: 4293 cmp r3, r2 80065a4: d003 beq.n 80065ae 80065a6: 687b ldr r3, [r7, #4] 80065a8: 4a20 ldr r2, [pc, #128] @ (800662c ) 80065aa: 4293 cmp r3, r2 80065ac: d10d bne.n 80065ca { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 80065ae: 697b ldr r3, [r7, #20] 80065b0: f423 6300 bic.w r3, r3, #2048 @ 0x800 80065b4: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 80065b6: 683b ldr r3, [r7, #0] 80065b8: 68db ldr r3, [r3, #12] 80065ba: 021b lsls r3, r3, #8 80065bc: 697a ldr r2, [r7, #20] 80065be: 4313 orrs r3, r2 80065c0: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 80065c2: 697b ldr r3, [r7, #20] 80065c4: f423 6380 bic.w r3, r3, #1024 @ 0x400 80065c8: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80065ca: 687b ldr r3, [r7, #4] 80065cc: 4a16 ldr r2, [pc, #88] @ (8006628 ) 80065ce: 4293 cmp r3, r2 80065d0: d003 beq.n 80065da 80065d2: 687b ldr r3, [r7, #4] 80065d4: 4a15 ldr r2, [pc, #84] @ (800662c ) 80065d6: 4293 cmp r3, r2 80065d8: d113 bne.n 8006602 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 80065da: 693b ldr r3, [r7, #16] 80065dc: f423 5380 bic.w r3, r3, #4096 @ 0x1000 80065e0: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 80065e2: 693b ldr r3, [r7, #16] 80065e4: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80065e8: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 80065ea: 683b ldr r3, [r7, #0] 80065ec: 695b ldr r3, [r3, #20] 80065ee: 011b lsls r3, r3, #4 80065f0: 693a ldr r2, [r7, #16] 80065f2: 4313 orrs r3, r2 80065f4: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 80065f6: 683b ldr r3, [r7, #0] 80065f8: 699b ldr r3, [r3, #24] 80065fa: 011b lsls r3, r3, #4 80065fc: 693a ldr r2, [r7, #16] 80065fe: 4313 orrs r3, r2 8006600: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8006602: 687b ldr r3, [r7, #4] 8006604: 693a ldr r2, [r7, #16] 8006606: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8006608: 687b ldr r3, [r7, #4] 800660a: 68fa ldr r2, [r7, #12] 800660c: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 800660e: 683b ldr r3, [r7, #0] 8006610: 685a ldr r2, [r3, #4] 8006612: 687b ldr r3, [r7, #4] 8006614: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8006616: 687b ldr r3, [r7, #4] 8006618: 697a ldr r2, [r7, #20] 800661a: 621a str r2, [r3, #32] } 800661c: bf00 nop 800661e: 371c adds r7, #28 8006620: 46bd mov sp, r7 8006622: f85d 7b04 ldr.w r7, [sp], #4 8006626: 4770 bx lr 8006628: 40010000 .word 0x40010000 800662c: 40010400 .word 0x40010400 08006630 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8006630: b480 push {r7} 8006632: b087 sub sp, #28 8006634: af00 add r7, sp, #0 8006636: 6078 str r0, [r7, #4] 8006638: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800663a: 687b ldr r3, [r7, #4] 800663c: 6a1b ldr r3, [r3, #32] 800663e: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8006640: 687b ldr r3, [r7, #4] 8006642: 6a1b ldr r3, [r3, #32] 8006644: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8006648: 687b ldr r3, [r7, #4] 800664a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800664c: 687b ldr r3, [r7, #4] 800664e: 685b ldr r3, [r3, #4] 8006650: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8006652: 687b ldr r3, [r7, #4] 8006654: 69db ldr r3, [r3, #28] 8006656: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8006658: 68fb ldr r3, [r7, #12] 800665a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800665e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8006660: 68fb ldr r3, [r7, #12] 8006662: f423 7340 bic.w r3, r3, #768 @ 0x300 8006666: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8006668: 683b ldr r3, [r7, #0] 800666a: 681b ldr r3, [r3, #0] 800666c: 021b lsls r3, r3, #8 800666e: 68fa ldr r2, [r7, #12] 8006670: 4313 orrs r3, r2 8006672: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8006674: 693b ldr r3, [r7, #16] 8006676: f423 5300 bic.w r3, r3, #8192 @ 0x2000 800667a: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 800667c: 683b ldr r3, [r7, #0] 800667e: 689b ldr r3, [r3, #8] 8006680: 031b lsls r3, r3, #12 8006682: 693a ldr r2, [r7, #16] 8006684: 4313 orrs r3, r2 8006686: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006688: 687b ldr r3, [r7, #4] 800668a: 4a12 ldr r2, [pc, #72] @ (80066d4 ) 800668c: 4293 cmp r3, r2 800668e: d003 beq.n 8006698 8006690: 687b ldr r3, [r7, #4] 8006692: 4a11 ldr r2, [pc, #68] @ (80066d8 ) 8006694: 4293 cmp r3, r2 8006696: d109 bne.n 80066ac { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8006698: 697b ldr r3, [r7, #20] 800669a: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800669e: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 80066a0: 683b ldr r3, [r7, #0] 80066a2: 695b ldr r3, [r3, #20] 80066a4: 019b lsls r3, r3, #6 80066a6: 697a ldr r2, [r7, #20] 80066a8: 4313 orrs r3, r2 80066aa: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80066ac: 687b ldr r3, [r7, #4] 80066ae: 697a ldr r2, [r7, #20] 80066b0: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80066b2: 687b ldr r3, [r7, #4] 80066b4: 68fa ldr r2, [r7, #12] 80066b6: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 80066b8: 683b ldr r3, [r7, #0] 80066ba: 685a ldr r2, [r3, #4] 80066bc: 687b ldr r3, [r7, #4] 80066be: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80066c0: 687b ldr r3, [r7, #4] 80066c2: 693a ldr r2, [r7, #16] 80066c4: 621a str r2, [r3, #32] } 80066c6: bf00 nop 80066c8: 371c adds r7, #28 80066ca: 46bd mov sp, r7 80066cc: f85d 7b04 ldr.w r7, [sp], #4 80066d0: 4770 bx lr 80066d2: bf00 nop 80066d4: 40010000 .word 0x40010000 80066d8: 40010400 .word 0x40010400 080066dc : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 80066dc: b480 push {r7} 80066de: b087 sub sp, #28 80066e0: af00 add r7, sp, #0 80066e2: 60f8 str r0, [r7, #12] 80066e4: 60b9 str r1, [r7, #8] 80066e6: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 80066e8: 68bb ldr r3, [r7, #8] 80066ea: f003 031f and.w r3, r3, #31 80066ee: 2201 movs r2, #1 80066f0: fa02 f303 lsl.w r3, r2, r3 80066f4: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 80066f6: 68fb ldr r3, [r7, #12] 80066f8: 6a1a ldr r2, [r3, #32] 80066fa: 697b ldr r3, [r7, #20] 80066fc: 43db mvns r3, r3 80066fe: 401a ands r2, r3 8006700: 68fb ldr r3, [r7, #12] 8006702: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8006704: 68fb ldr r3, [r7, #12] 8006706: 6a1a ldr r2, [r3, #32] 8006708: 68bb ldr r3, [r7, #8] 800670a: f003 031f and.w r3, r3, #31 800670e: 6879 ldr r1, [r7, #4] 8006710: fa01 f303 lsl.w r3, r1, r3 8006714: 431a orrs r2, r3 8006716: 68fb ldr r3, [r7, #12] 8006718: 621a str r2, [r3, #32] } 800671a: bf00 nop 800671c: 371c adds r7, #28 800671e: 46bd mov sp, r7 8006720: f85d 7b04 ldr.w r7, [sp], #4 8006724: 4770 bx lr ... 08006728 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8006728: b480 push {r7} 800672a: b085 sub sp, #20 800672c: af00 add r7, sp, #0 800672e: 6078 str r0, [r7, #4] 8006730: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8006732: 687b ldr r3, [r7, #4] 8006734: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8006738: 2b01 cmp r3, #1 800673a: d101 bne.n 8006740 800673c: 2302 movs r3, #2 800673e: e05a b.n 80067f6 8006740: 687b ldr r3, [r7, #4] 8006742: 2201 movs r2, #1 8006744: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8006748: 687b ldr r3, [r7, #4] 800674a: 2202 movs r2, #2 800674c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8006750: 687b ldr r3, [r7, #4] 8006752: 681b ldr r3, [r3, #0] 8006754: 685b ldr r3, [r3, #4] 8006756: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8006758: 687b ldr r3, [r7, #4] 800675a: 681b ldr r3, [r3, #0] 800675c: 689b ldr r3, [r3, #8] 800675e: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8006760: 68fb ldr r3, [r7, #12] 8006762: f023 0370 bic.w r3, r3, #112 @ 0x70 8006766: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8006768: 683b ldr r3, [r7, #0] 800676a: 681b ldr r3, [r3, #0] 800676c: 68fa ldr r2, [r7, #12] 800676e: 4313 orrs r3, r2 8006770: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8006772: 687b ldr r3, [r7, #4] 8006774: 681b ldr r3, [r3, #0] 8006776: 68fa ldr r2, [r7, #12] 8006778: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800677a: 687b ldr r3, [r7, #4] 800677c: 681b ldr r3, [r3, #0] 800677e: 4a21 ldr r2, [pc, #132] @ (8006804 ) 8006780: 4293 cmp r3, r2 8006782: d022 beq.n 80067ca 8006784: 687b ldr r3, [r7, #4] 8006786: 681b ldr r3, [r3, #0] 8006788: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800678c: d01d beq.n 80067ca 800678e: 687b ldr r3, [r7, #4] 8006790: 681b ldr r3, [r3, #0] 8006792: 4a1d ldr r2, [pc, #116] @ (8006808 ) 8006794: 4293 cmp r3, r2 8006796: d018 beq.n 80067ca 8006798: 687b ldr r3, [r7, #4] 800679a: 681b ldr r3, [r3, #0] 800679c: 4a1b ldr r2, [pc, #108] @ (800680c ) 800679e: 4293 cmp r3, r2 80067a0: d013 beq.n 80067ca 80067a2: 687b ldr r3, [r7, #4] 80067a4: 681b ldr r3, [r3, #0] 80067a6: 4a1a ldr r2, [pc, #104] @ (8006810 ) 80067a8: 4293 cmp r3, r2 80067aa: d00e beq.n 80067ca 80067ac: 687b ldr r3, [r7, #4] 80067ae: 681b ldr r3, [r3, #0] 80067b0: 4a18 ldr r2, [pc, #96] @ (8006814 ) 80067b2: 4293 cmp r3, r2 80067b4: d009 beq.n 80067ca 80067b6: 687b ldr r3, [r7, #4] 80067b8: 681b ldr r3, [r3, #0] 80067ba: 4a17 ldr r2, [pc, #92] @ (8006818 ) 80067bc: 4293 cmp r3, r2 80067be: d004 beq.n 80067ca 80067c0: 687b ldr r3, [r7, #4] 80067c2: 681b ldr r3, [r3, #0] 80067c4: 4a15 ldr r2, [pc, #84] @ (800681c ) 80067c6: 4293 cmp r3, r2 80067c8: d10c bne.n 80067e4 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80067ca: 68bb ldr r3, [r7, #8] 80067cc: f023 0380 bic.w r3, r3, #128 @ 0x80 80067d0: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80067d2: 683b ldr r3, [r7, #0] 80067d4: 685b ldr r3, [r3, #4] 80067d6: 68ba ldr r2, [r7, #8] 80067d8: 4313 orrs r3, r2 80067da: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80067dc: 687b ldr r3, [r7, #4] 80067de: 681b ldr r3, [r3, #0] 80067e0: 68ba ldr r2, [r7, #8] 80067e2: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80067e4: 687b ldr r3, [r7, #4] 80067e6: 2201 movs r2, #1 80067e8: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80067ec: 687b ldr r3, [r7, #4] 80067ee: 2200 movs r2, #0 80067f0: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 80067f4: 2300 movs r3, #0 } 80067f6: 4618 mov r0, r3 80067f8: 3714 adds r7, #20 80067fa: 46bd mov sp, r7 80067fc: f85d 7b04 ldr.w r7, [sp], #4 8006800: 4770 bx lr 8006802: bf00 nop 8006804: 40010000 .word 0x40010000 8006808: 40000400 .word 0x40000400 800680c: 40000800 .word 0x40000800 8006810: 40000c00 .word 0x40000c00 8006814: 40010400 .word 0x40010400 8006818: 40014000 .word 0x40014000 800681c: 40001800 .word 0x40001800 08006820 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8006820: b580 push {r7, lr} 8006822: b082 sub sp, #8 8006824: af00 add r7, sp, #0 8006826: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8006828: 687b ldr r3, [r7, #4] 800682a: 2b00 cmp r3, #0 800682c: d101 bne.n 8006832 { return HAL_ERROR; 800682e: 2301 movs r3, #1 8006830: e042 b.n 80068b8 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 8006832: 687b ldr r3, [r7, #4] 8006834: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8006838: b2db uxtb r3, r3 800683a: 2b00 cmp r3, #0 800683c: d106 bne.n 800684c { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800683e: 687b ldr r3, [r7, #4] 8006840: 2200 movs r2, #0 8006842: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8006846: 6878 ldr r0, [r7, #4] 8006848: f7fa ffea bl 8001820 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 800684c: 687b ldr r3, [r7, #4] 800684e: 2224 movs r2, #36 @ 0x24 8006850: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8006854: 687b ldr r3, [r7, #4] 8006856: 681b ldr r3, [r3, #0] 8006858: 68da ldr r2, [r3, #12] 800685a: 687b ldr r3, [r7, #4] 800685c: 681b ldr r3, [r3, #0] 800685e: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8006862: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8006864: 6878 ldr r0, [r7, #4] 8006866: f000 ff63 bl 8007730 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 800686a: 687b ldr r3, [r7, #4] 800686c: 681b ldr r3, [r3, #0] 800686e: 691a ldr r2, [r3, #16] 8006870: 687b ldr r3, [r7, #4] 8006872: 681b ldr r3, [r3, #0] 8006874: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8006878: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 800687a: 687b ldr r3, [r7, #4] 800687c: 681b ldr r3, [r3, #0] 800687e: 695a ldr r2, [r3, #20] 8006880: 687b ldr r3, [r7, #4] 8006882: 681b ldr r3, [r3, #0] 8006884: f022 022a bic.w r2, r2, #42 @ 0x2a 8006888: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 800688a: 687b ldr r3, [r7, #4] 800688c: 681b ldr r3, [r3, #0] 800688e: 68da ldr r2, [r3, #12] 8006890: 687b ldr r3, [r7, #4] 8006892: 681b ldr r3, [r3, #0] 8006894: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8006898: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 800689a: 687b ldr r3, [r7, #4] 800689c: 2200 movs r2, #0 800689e: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 80068a0: 687b ldr r3, [r7, #4] 80068a2: 2220 movs r2, #32 80068a4: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 80068a8: 687b ldr r3, [r7, #4] 80068aa: 2220 movs r2, #32 80068ac: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 80068b0: 687b ldr r3, [r7, #4] 80068b2: 2200 movs r2, #0 80068b4: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 80068b6: 2300 movs r3, #0 } 80068b8: 4618 mov r0, r3 80068ba: 3708 adds r7, #8 80068bc: 46bd mov sp, r7 80068be: bd80 pop {r7, pc} 080068c0 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 80068c0: b580 push {r7, lr} 80068c2: b08c sub sp, #48 @ 0x30 80068c4: af00 add r7, sp, #0 80068c6: 60f8 str r0, [r7, #12] 80068c8: 60b9 str r1, [r7, #8] 80068ca: 4613 mov r3, r2 80068cc: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80068ce: 68fb ldr r3, [r7, #12] 80068d0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80068d4: b2db uxtb r3, r3 80068d6: 2b20 cmp r3, #32 80068d8: d162 bne.n 80069a0 { if ((pData == NULL) || (Size == 0U)) 80068da: 68bb ldr r3, [r7, #8] 80068dc: 2b00 cmp r3, #0 80068de: d002 beq.n 80068e6 80068e0: 88fb ldrh r3, [r7, #6] 80068e2: 2b00 cmp r3, #0 80068e4: d101 bne.n 80068ea { return HAL_ERROR; 80068e6: 2301 movs r3, #1 80068e8: e05b b.n 80069a2 } huart->pTxBuffPtr = pData; 80068ea: 68ba ldr r2, [r7, #8] 80068ec: 68fb ldr r3, [r7, #12] 80068ee: 621a str r2, [r3, #32] huart->TxXferSize = Size; 80068f0: 68fb ldr r3, [r7, #12] 80068f2: 88fa ldrh r2, [r7, #6] 80068f4: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 80068f6: 68fb ldr r3, [r7, #12] 80068f8: 88fa ldrh r2, [r7, #6] 80068fa: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 80068fc: 68fb ldr r3, [r7, #12] 80068fe: 2200 movs r2, #0 8006900: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 8006902: 68fb ldr r3, [r7, #12] 8006904: 2221 movs r2, #33 @ 0x21 8006906: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 800690a: 68fb ldr r3, [r7, #12] 800690c: 6b9b ldr r3, [r3, #56] @ 0x38 800690e: 4a27 ldr r2, [pc, #156] @ (80069ac ) 8006910: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8006912: 68fb ldr r3, [r7, #12] 8006914: 6b9b ldr r3, [r3, #56] @ 0x38 8006916: 4a26 ldr r2, [pc, #152] @ (80069b0 ) 8006918: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 800691a: 68fb ldr r3, [r7, #12] 800691c: 6b9b ldr r3, [r3, #56] @ 0x38 800691e: 4a25 ldr r2, [pc, #148] @ (80069b4 ) 8006920: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8006922: 68fb ldr r3, [r7, #12] 8006924: 6b9b ldr r3, [r3, #56] @ 0x38 8006926: 2200 movs r2, #0 8006928: 651a str r2, [r3, #80] @ 0x50 /* Enable the UART transmit DMA stream */ tmp = (const uint32_t *)&pData; 800692a: f107 0308 add.w r3, r7, #8 800692e: 62fb str r3, [r7, #44] @ 0x2c if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK) 8006930: 68fb ldr r3, [r7, #12] 8006932: 6b98 ldr r0, [r3, #56] @ 0x38 8006934: 6afb ldr r3, [r7, #44] @ 0x2c 8006936: 6819 ldr r1, [r3, #0] 8006938: 68fb ldr r3, [r7, #12] 800693a: 681b ldr r3, [r3, #0] 800693c: 3304 adds r3, #4 800693e: 461a mov r2, r3 8006940: 88fb ldrh r3, [r7, #6] 8006942: f7fb fcaf bl 80022a4 8006946: 4603 mov r3, r0 8006948: 2b00 cmp r3, #0 800694a: d008 beq.n 800695e { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 800694c: 68fb ldr r3, [r7, #12] 800694e: 2210 movs r2, #16 8006950: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; 8006952: 68fb ldr r3, [r7, #12] 8006954: 2220 movs r2, #32 8006956: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_ERROR; 800695a: 2301 movs r3, #1 800695c: e021 b.n 80069a2 } /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 800695e: 68fb ldr r3, [r7, #12] 8006960: 681b ldr r3, [r3, #0] 8006962: f06f 0240 mvn.w r2, #64 @ 0x40 8006966: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8006968: 68fb ldr r3, [r7, #12] 800696a: 681b ldr r3, [r3, #0] 800696c: 3314 adds r3, #20 800696e: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006970: 69bb ldr r3, [r7, #24] 8006972: e853 3f00 ldrex r3, [r3] 8006976: 617b str r3, [r7, #20] return(result); 8006978: 697b ldr r3, [r7, #20] 800697a: f043 0380 orr.w r3, r3, #128 @ 0x80 800697e: 62bb str r3, [r7, #40] @ 0x28 8006980: 68fb ldr r3, [r7, #12] 8006982: 681b ldr r3, [r3, #0] 8006984: 3314 adds r3, #20 8006986: 6aba ldr r2, [r7, #40] @ 0x28 8006988: 627a str r2, [r7, #36] @ 0x24 800698a: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800698c: 6a39 ldr r1, [r7, #32] 800698e: 6a7a ldr r2, [r7, #36] @ 0x24 8006990: e841 2300 strex r3, r2, [r1] 8006994: 61fb str r3, [r7, #28] return(result); 8006996: 69fb ldr r3, [r7, #28] 8006998: 2b00 cmp r3, #0 800699a: d1e5 bne.n 8006968 return HAL_OK; 800699c: 2300 movs r3, #0 800699e: e000 b.n 80069a2 } else { return HAL_BUSY; 80069a0: 2302 movs r3, #2 } } 80069a2: 4618 mov r0, r3 80069a4: 3730 adds r7, #48 @ 0x30 80069a6: 46bd mov sp, r7 80069a8: bd80 pop {r7, pc} 80069aa: bf00 nop 80069ac: 08006fad .word 0x08006fad 80069b0: 08007047 .word 0x08007047 80069b4: 080071cb .word 0x080071cb 080069b8 : * @param Size Amount of data elements (u8 or u16) to be received. * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80069b8: b580 push {r7, lr} 80069ba: b084 sub sp, #16 80069bc: af00 add r7, sp, #0 80069be: 60f8 str r0, [r7, #12] 80069c0: 60b9 str r1, [r7, #8] 80069c2: 4613 mov r3, r2 80069c4: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 80069c6: 68fb ldr r3, [r7, #12] 80069c8: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80069cc: b2db uxtb r3, r3 80069ce: 2b20 cmp r3, #32 80069d0: d112 bne.n 80069f8 { if ((pData == NULL) || (Size == 0U)) 80069d2: 68bb ldr r3, [r7, #8] 80069d4: 2b00 cmp r3, #0 80069d6: d002 beq.n 80069de 80069d8: 88fb ldrh r3, [r7, #6] 80069da: 2b00 cmp r3, #0 80069dc: d101 bne.n 80069e2 { return HAL_ERROR; 80069de: 2301 movs r3, #1 80069e0: e00b b.n 80069fa } /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80069e2: 68fb ldr r3, [r7, #12] 80069e4: 2200 movs r2, #0 80069e6: 631a str r2, [r3, #48] @ 0x30 return (UART_Start_Receive_DMA(huart, pData, Size)); 80069e8: 88fb ldrh r3, [r7, #6] 80069ea: 461a mov r2, r3 80069ec: 68b9 ldr r1, [r7, #8] 80069ee: 68f8 ldr r0, [r7, #12] 80069f0: f000 fc36 bl 8007260 80069f4: 4603 mov r3, r0 80069f6: e000 b.n 80069fa } else { return HAL_BUSY; 80069f8: 2302 movs r3, #2 } } 80069fa: 4618 mov r0, r3 80069fc: 3710 adds r7, #16 80069fe: 46bd mov sp, r7 8006a00: bd80 pop {r7, pc} ... 08006a04 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8006a04: b580 push {r7, lr} 8006a06: b0ba sub sp, #232 @ 0xe8 8006a08: af00 add r7, sp, #0 8006a0a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8006a0c: 687b ldr r3, [r7, #4] 8006a0e: 681b ldr r3, [r3, #0] 8006a10: 681b ldr r3, [r3, #0] 8006a12: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8006a16: 687b ldr r3, [r7, #4] 8006a18: 681b ldr r3, [r3, #0] 8006a1a: 68db ldr r3, [r3, #12] 8006a1c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8006a20: 687b ldr r3, [r7, #4] 8006a22: 681b ldr r3, [r3, #0] 8006a24: 695b ldr r3, [r3, #20] 8006a26: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8006a2a: 2300 movs r3, #0 8006a2c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8006a30: 2300 movs r3, #0 8006a32: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8006a36: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006a3a: f003 030f and.w r3, r3, #15 8006a3e: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 8006a42: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8006a46: 2b00 cmp r3, #0 8006a48: d10f bne.n 8006a6a { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8006a4a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006a4e: f003 0320 and.w r3, r3, #32 8006a52: 2b00 cmp r3, #0 8006a54: d009 beq.n 8006a6a 8006a56: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006a5a: f003 0320 and.w r3, r3, #32 8006a5e: 2b00 cmp r3, #0 8006a60: d003 beq.n 8006a6a { UART_Receive_IT(huart); 8006a62: 6878 ldr r0, [r7, #4] 8006a64: f000 fda6 bl 80075b4 return; 8006a68: e273 b.n 8006f52 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 8006a6a: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8006a6e: 2b00 cmp r3, #0 8006a70: f000 80de beq.w 8006c30 8006a74: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8006a78: f003 0301 and.w r3, r3, #1 8006a7c: 2b00 cmp r3, #0 8006a7e: d106 bne.n 8006a8e || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8006a80: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006a84: f403 7390 and.w r3, r3, #288 @ 0x120 8006a88: 2b00 cmp r3, #0 8006a8a: f000 80d1 beq.w 8006c30 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8006a8e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006a92: f003 0301 and.w r3, r3, #1 8006a96: 2b00 cmp r3, #0 8006a98: d00b beq.n 8006ab2 8006a9a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006a9e: f403 7380 and.w r3, r3, #256 @ 0x100 8006aa2: 2b00 cmp r3, #0 8006aa4: d005 beq.n 8006ab2 { huart->ErrorCode |= HAL_UART_ERROR_PE; 8006aa6: 687b ldr r3, [r7, #4] 8006aa8: 6c5b ldr r3, [r3, #68] @ 0x44 8006aaa: f043 0201 orr.w r2, r3, #1 8006aae: 687b ldr r3, [r7, #4] 8006ab0: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8006ab2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006ab6: f003 0304 and.w r3, r3, #4 8006aba: 2b00 cmp r3, #0 8006abc: d00b beq.n 8006ad6 8006abe: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8006ac2: f003 0301 and.w r3, r3, #1 8006ac6: 2b00 cmp r3, #0 8006ac8: d005 beq.n 8006ad6 { huart->ErrorCode |= HAL_UART_ERROR_NE; 8006aca: 687b ldr r3, [r7, #4] 8006acc: 6c5b ldr r3, [r3, #68] @ 0x44 8006ace: f043 0202 orr.w r2, r3, #2 8006ad2: 687b ldr r3, [r7, #4] 8006ad4: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8006ad6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006ada: f003 0302 and.w r3, r3, #2 8006ade: 2b00 cmp r3, #0 8006ae0: d00b beq.n 8006afa 8006ae2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8006ae6: f003 0301 and.w r3, r3, #1 8006aea: 2b00 cmp r3, #0 8006aec: d005 beq.n 8006afa { huart->ErrorCode |= HAL_UART_ERROR_FE; 8006aee: 687b ldr r3, [r7, #4] 8006af0: 6c5b ldr r3, [r3, #68] @ 0x44 8006af2: f043 0204 orr.w r2, r3, #4 8006af6: 687b ldr r3, [r7, #4] 8006af8: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8006afa: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006afe: f003 0308 and.w r3, r3, #8 8006b02: 2b00 cmp r3, #0 8006b04: d011 beq.n 8006b2a 8006b06: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006b0a: f003 0320 and.w r3, r3, #32 8006b0e: 2b00 cmp r3, #0 8006b10: d105 bne.n 8006b1e || ((cr3its & USART_CR3_EIE) != RESET))) 8006b12: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8006b16: f003 0301 and.w r3, r3, #1 8006b1a: 2b00 cmp r3, #0 8006b1c: d005 beq.n 8006b2a { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8006b1e: 687b ldr r3, [r7, #4] 8006b20: 6c5b ldr r3, [r3, #68] @ 0x44 8006b22: f043 0208 orr.w r2, r3, #8 8006b26: 687b ldr r3, [r7, #4] 8006b28: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8006b2a: 687b ldr r3, [r7, #4] 8006b2c: 6c5b ldr r3, [r3, #68] @ 0x44 8006b2e: 2b00 cmp r3, #0 8006b30: f000 820a beq.w 8006f48 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8006b34: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006b38: f003 0320 and.w r3, r3, #32 8006b3c: 2b00 cmp r3, #0 8006b3e: d008 beq.n 8006b52 8006b40: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006b44: f003 0320 and.w r3, r3, #32 8006b48: 2b00 cmp r3, #0 8006b4a: d002 beq.n 8006b52 { UART_Receive_IT(huart); 8006b4c: 6878 ldr r0, [r7, #4] 8006b4e: f000 fd31 bl 80075b4 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8006b52: 687b ldr r3, [r7, #4] 8006b54: 681b ldr r3, [r3, #0] 8006b56: 695b ldr r3, [r3, #20] 8006b58: f003 0340 and.w r3, r3, #64 @ 0x40 8006b5c: 2b40 cmp r3, #64 @ 0x40 8006b5e: bf0c ite eq 8006b60: 2301 moveq r3, #1 8006b62: 2300 movne r3, #0 8006b64: b2db uxtb r3, r3 8006b66: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8006b6a: 687b ldr r3, [r7, #4] 8006b6c: 6c5b ldr r3, [r3, #68] @ 0x44 8006b6e: f003 0308 and.w r3, r3, #8 8006b72: 2b00 cmp r3, #0 8006b74: d103 bne.n 8006b7e 8006b76: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8006b7a: 2b00 cmp r3, #0 8006b7c: d04f beq.n 8006c1e { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8006b7e: 6878 ldr r0, [r7, #4] 8006b80: f000 fc3c bl 80073fc /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006b84: 687b ldr r3, [r7, #4] 8006b86: 681b ldr r3, [r3, #0] 8006b88: 695b ldr r3, [r3, #20] 8006b8a: f003 0340 and.w r3, r3, #64 @ 0x40 8006b8e: 2b40 cmp r3, #64 @ 0x40 8006b90: d141 bne.n 8006c16 { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8006b92: 687b ldr r3, [r7, #4] 8006b94: 681b ldr r3, [r3, #0] 8006b96: 3314 adds r3, #20 8006b98: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006b9c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8006ba0: e853 3f00 ldrex r3, [r3] 8006ba4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8006ba8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8006bac: f023 0340 bic.w r3, r3, #64 @ 0x40 8006bb0: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8006bb4: 687b ldr r3, [r7, #4] 8006bb6: 681b ldr r3, [r3, #0] 8006bb8: 3314 adds r3, #20 8006bba: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8006bbe: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8006bc2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006bc6: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8006bca: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8006bce: e841 2300 strex r3, r2, [r1] 8006bd2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8006bd6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8006bda: 2b00 cmp r3, #0 8006bdc: d1d9 bne.n 8006b92 /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) 8006bde: 687b ldr r3, [r7, #4] 8006be0: 6bdb ldr r3, [r3, #60] @ 0x3c 8006be2: 2b00 cmp r3, #0 8006be4: d013 beq.n 8006c0e { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8006be6: 687b ldr r3, [r7, #4] 8006be8: 6bdb ldr r3, [r3, #60] @ 0x3c 8006bea: 4a8a ldr r2, [pc, #552] @ (8006e14 ) 8006bec: 651a str r2, [r3, #80] @ 0x50 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8006bee: 687b ldr r3, [r7, #4] 8006bf0: 6bdb ldr r3, [r3, #60] @ 0x3c 8006bf2: 4618 mov r0, r3 8006bf4: f7fb fc1e bl 8002434 8006bf8: 4603 mov r3, r0 8006bfa: 2b00 cmp r3, #0 8006bfc: d016 beq.n 8006c2c { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8006bfe: 687b ldr r3, [r7, #4] 8006c00: 6bdb ldr r3, [r3, #60] @ 0x3c 8006c02: 6d1b ldr r3, [r3, #80] @ 0x50 8006c04: 687a ldr r2, [r7, #4] 8006c06: 6bd2 ldr r2, [r2, #60] @ 0x3c 8006c08: 4610 mov r0, r2 8006c0a: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006c0c: e00e b.n 8006c2c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006c0e: 6878 ldr r0, [r7, #4] 8006c10: f7fa f958 bl 8000ec4 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006c14: e00a b.n 8006c2c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006c16: 6878 ldr r0, [r7, #4] 8006c18: f7fa f954 bl 8000ec4 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006c1c: e006 b.n 8006c2c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006c1e: 6878 ldr r0, [r7, #4] 8006c20: f7fa f950 bl 8000ec4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8006c24: 687b ldr r3, [r7, #4] 8006c26: 2200 movs r2, #0 8006c28: 645a str r2, [r3, #68] @ 0x44 } } return; 8006c2a: e18d b.n 8006f48 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006c2c: bf00 nop return; 8006c2e: e18b b.n 8006f48 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006c30: 687b ldr r3, [r7, #4] 8006c32: 6b1b ldr r3, [r3, #48] @ 0x30 8006c34: 2b01 cmp r3, #1 8006c36: f040 8167 bne.w 8006f08 && ((isrflags & USART_SR_IDLE) != 0U) 8006c3a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006c3e: f003 0310 and.w r3, r3, #16 8006c42: 2b00 cmp r3, #0 8006c44: f000 8160 beq.w 8006f08 && ((cr1its & USART_CR1_IDLEIE) != 0U)) 8006c48: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006c4c: f003 0310 and.w r3, r3, #16 8006c50: 2b00 cmp r3, #0 8006c52: f000 8159 beq.w 8006f08 { __HAL_UART_CLEAR_IDLEFLAG(huart); 8006c56: 2300 movs r3, #0 8006c58: 60bb str r3, [r7, #8] 8006c5a: 687b ldr r3, [r7, #4] 8006c5c: 681b ldr r3, [r3, #0] 8006c5e: 681b ldr r3, [r3, #0] 8006c60: 60bb str r3, [r7, #8] 8006c62: 687b ldr r3, [r7, #4] 8006c64: 681b ldr r3, [r3, #0] 8006c66: 685b ldr r3, [r3, #4] 8006c68: 60bb str r3, [r7, #8] 8006c6a: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006c6c: 687b ldr r3, [r7, #4] 8006c6e: 681b ldr r3, [r3, #0] 8006c70: 695b ldr r3, [r3, #20] 8006c72: f003 0340 and.w r3, r3, #64 @ 0x40 8006c76: 2b40 cmp r3, #64 @ 0x40 8006c78: f040 80ce bne.w 8006e18 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8006c7c: 687b ldr r3, [r7, #4] 8006c7e: 6bdb ldr r3, [r3, #60] @ 0x3c 8006c80: 681b ldr r3, [r3, #0] 8006c82: 685b ldr r3, [r3, #4] 8006c84: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8006c88: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8006c8c: 2b00 cmp r3, #0 8006c8e: f000 80a9 beq.w 8006de4 && (nb_remaining_rx_data < huart->RxXferSize)) 8006c92: 687b ldr r3, [r7, #4] 8006c94: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006c96: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8006c9a: 429a cmp r2, r3 8006c9c: f080 80a2 bcs.w 8006de4 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8006ca0: 687b ldr r3, [r7, #4] 8006ca2: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8006ca6: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8006ca8: 687b ldr r3, [r7, #4] 8006caa: 6bdb ldr r3, [r3, #60] @ 0x3c 8006cac: 69db ldr r3, [r3, #28] 8006cae: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006cb2: f000 8088 beq.w 8006dc6 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006cb6: 687b ldr r3, [r7, #4] 8006cb8: 681b ldr r3, [r3, #0] 8006cba: 330c adds r3, #12 8006cbc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006cc0: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8006cc4: e853 3f00 ldrex r3, [r3] 8006cc8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8006ccc: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8006cd0: f423 7380 bic.w r3, r3, #256 @ 0x100 8006cd4: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006cd8: 687b ldr r3, [r7, #4] 8006cda: 681b ldr r3, [r3, #0] 8006cdc: 330c adds r3, #12 8006cde: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 8006ce2: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8006ce6: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006cea: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8006cee: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8006cf2: e841 2300 strex r3, r2, [r1] 8006cf6: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8006cfa: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8006cfe: 2b00 cmp r3, #0 8006d00: d1d9 bne.n 8006cb6 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006d02: 687b ldr r3, [r7, #4] 8006d04: 681b ldr r3, [r3, #0] 8006d06: 3314 adds r3, #20 8006d08: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006d0a: 6f7b ldr r3, [r7, #116] @ 0x74 8006d0c: e853 3f00 ldrex r3, [r3] 8006d10: 673b str r3, [r7, #112] @ 0x70 return(result); 8006d12: 6f3b ldr r3, [r7, #112] @ 0x70 8006d14: f023 0301 bic.w r3, r3, #1 8006d18: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8006d1c: 687b ldr r3, [r7, #4] 8006d1e: 681b ldr r3, [r3, #0] 8006d20: 3314 adds r3, #20 8006d22: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8006d26: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8006d2a: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006d2c: 6ff9 ldr r1, [r7, #124] @ 0x7c 8006d2e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8006d32: e841 2300 strex r3, r2, [r1] 8006d36: 67bb str r3, [r7, #120] @ 0x78 return(result); 8006d38: 6fbb ldr r3, [r7, #120] @ 0x78 8006d3a: 2b00 cmp r3, #0 8006d3c: d1e1 bne.n 8006d02 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8006d3e: 687b ldr r3, [r7, #4] 8006d40: 681b ldr r3, [r3, #0] 8006d42: 3314 adds r3, #20 8006d44: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006d46: 6e3b ldr r3, [r7, #96] @ 0x60 8006d48: e853 3f00 ldrex r3, [r3] 8006d4c: 65fb str r3, [r7, #92] @ 0x5c return(result); 8006d4e: 6dfb ldr r3, [r7, #92] @ 0x5c 8006d50: f023 0340 bic.w r3, r3, #64 @ 0x40 8006d54: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8006d58: 687b ldr r3, [r7, #4] 8006d5a: 681b ldr r3, [r3, #0] 8006d5c: 3314 adds r3, #20 8006d5e: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8006d62: 66fa str r2, [r7, #108] @ 0x6c 8006d64: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006d66: 6eb9 ldr r1, [r7, #104] @ 0x68 8006d68: 6efa ldr r2, [r7, #108] @ 0x6c 8006d6a: e841 2300 strex r3, r2, [r1] 8006d6e: 667b str r3, [r7, #100] @ 0x64 return(result); 8006d70: 6e7b ldr r3, [r7, #100] @ 0x64 8006d72: 2b00 cmp r3, #0 8006d74: d1e3 bne.n 8006d3e /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006d76: 687b ldr r3, [r7, #4] 8006d78: 2220 movs r2, #32 8006d7a: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006d7e: 687b ldr r3, [r7, #4] 8006d80: 2200 movs r2, #0 8006d82: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006d84: 687b ldr r3, [r7, #4] 8006d86: 681b ldr r3, [r3, #0] 8006d88: 330c adds r3, #12 8006d8a: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006d8c: 6cfb ldr r3, [r7, #76] @ 0x4c 8006d8e: e853 3f00 ldrex r3, [r3] 8006d92: 64bb str r3, [r7, #72] @ 0x48 return(result); 8006d94: 6cbb ldr r3, [r7, #72] @ 0x48 8006d96: f023 0310 bic.w r3, r3, #16 8006d9a: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8006d9e: 687b ldr r3, [r7, #4] 8006da0: 681b ldr r3, [r3, #0] 8006da2: 330c adds r3, #12 8006da4: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 8006da8: 65ba str r2, [r7, #88] @ 0x58 8006daa: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006dac: 6d79 ldr r1, [r7, #84] @ 0x54 8006dae: 6dba ldr r2, [r7, #88] @ 0x58 8006db0: e841 2300 strex r3, r2, [r1] 8006db4: 653b str r3, [r7, #80] @ 0x50 return(result); 8006db6: 6d3b ldr r3, [r7, #80] @ 0x50 8006db8: 2b00 cmp r3, #0 8006dba: d1e3 bne.n 8006d84 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8006dbc: 687b ldr r3, [r7, #4] 8006dbe: 6bdb ldr r3, [r3, #60] @ 0x3c 8006dc0: 4618 mov r0, r3 8006dc2: f7fb fac7 bl 8002354 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006dc6: 687b ldr r3, [r7, #4] 8006dc8: 2202 movs r2, #2 8006dca: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8006dcc: 687b ldr r3, [r7, #4] 8006dce: 8d9a ldrh r2, [r3, #44] @ 0x2c 8006dd0: 687b ldr r3, [r7, #4] 8006dd2: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006dd4: b29b uxth r3, r3 8006dd6: 1ad3 subs r3, r2, r3 8006dd8: b29b uxth r3, r3 8006dda: 4619 mov r1, r3 8006ddc: 6878 ldr r0, [r7, #4] 8006dde: f000 f8d9 bl 8006f94 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 8006de2: e0b3 b.n 8006f4c if (nb_remaining_rx_data == huart->RxXferSize) 8006de4: 687b ldr r3, [r7, #4] 8006de6: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006de8: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8006dec: 429a cmp r2, r3 8006dee: f040 80ad bne.w 8006f4c if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) 8006df2: 687b ldr r3, [r7, #4] 8006df4: 6bdb ldr r3, [r3, #60] @ 0x3c 8006df6: 69db ldr r3, [r3, #28] 8006df8: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006dfc: f040 80a6 bne.w 8006f4c huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006e00: 687b ldr r3, [r7, #4] 8006e02: 2202 movs r2, #2 8006e04: 635a str r2, [r3, #52] @ 0x34 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006e06: 687b ldr r3, [r7, #4] 8006e08: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006e0a: 4619 mov r1, r3 8006e0c: 6878 ldr r0, [r7, #4] 8006e0e: f000 f8c1 bl 8006f94 return; 8006e12: e09b b.n 8006f4c 8006e14: 080074c3 .word 0x080074c3 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8006e18: 687b ldr r3, [r7, #4] 8006e1a: 8d9a ldrh r2, [r3, #44] @ 0x2c 8006e1c: 687b ldr r3, [r7, #4] 8006e1e: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006e20: b29b uxth r3, r3 8006e22: 1ad3 subs r3, r2, r3 8006e24: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8006e28: 687b ldr r3, [r7, #4] 8006e2a: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006e2c: b29b uxth r3, r3 8006e2e: 2b00 cmp r3, #0 8006e30: f000 808e beq.w 8006f50 && (nb_rx_data > 0U)) 8006e34: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8006e38: 2b00 cmp r3, #0 8006e3a: f000 8089 beq.w 8006f50 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8006e3e: 687b ldr r3, [r7, #4] 8006e40: 681b ldr r3, [r3, #0] 8006e42: 330c adds r3, #12 8006e44: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006e46: 6bbb ldr r3, [r7, #56] @ 0x38 8006e48: e853 3f00 ldrex r3, [r3] 8006e4c: 637b str r3, [r7, #52] @ 0x34 return(result); 8006e4e: 6b7b ldr r3, [r7, #52] @ 0x34 8006e50: f423 7390 bic.w r3, r3, #288 @ 0x120 8006e54: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8006e58: 687b ldr r3, [r7, #4] 8006e5a: 681b ldr r3, [r3, #0] 8006e5c: 330c adds r3, #12 8006e5e: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 8006e62: 647a str r2, [r7, #68] @ 0x44 8006e64: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006e66: 6c39 ldr r1, [r7, #64] @ 0x40 8006e68: 6c7a ldr r2, [r7, #68] @ 0x44 8006e6a: e841 2300 strex r3, r2, [r1] 8006e6e: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006e70: 6bfb ldr r3, [r7, #60] @ 0x3c 8006e72: 2b00 cmp r3, #0 8006e74: d1e3 bne.n 8006e3e /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006e76: 687b ldr r3, [r7, #4] 8006e78: 681b ldr r3, [r3, #0] 8006e7a: 3314 adds r3, #20 8006e7c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006e7e: 6a7b ldr r3, [r7, #36] @ 0x24 8006e80: e853 3f00 ldrex r3, [r3] 8006e84: 623b str r3, [r7, #32] return(result); 8006e86: 6a3b ldr r3, [r7, #32] 8006e88: f023 0301 bic.w r3, r3, #1 8006e8c: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8006e90: 687b ldr r3, [r7, #4] 8006e92: 681b ldr r3, [r3, #0] 8006e94: 3314 adds r3, #20 8006e96: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8006e9a: 633a str r2, [r7, #48] @ 0x30 8006e9c: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006e9e: 6af9 ldr r1, [r7, #44] @ 0x2c 8006ea0: 6b3a ldr r2, [r7, #48] @ 0x30 8006ea2: e841 2300 strex r3, r2, [r1] 8006ea6: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006ea8: 6abb ldr r3, [r7, #40] @ 0x28 8006eaa: 2b00 cmp r3, #0 8006eac: d1e3 bne.n 8006e76 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006eae: 687b ldr r3, [r7, #4] 8006eb0: 2220 movs r2, #32 8006eb2: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006eb6: 687b ldr r3, [r7, #4] 8006eb8: 2200 movs r2, #0 8006eba: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006ebc: 687b ldr r3, [r7, #4] 8006ebe: 681b ldr r3, [r3, #0] 8006ec0: 330c adds r3, #12 8006ec2: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006ec4: 693b ldr r3, [r7, #16] 8006ec6: e853 3f00 ldrex r3, [r3] 8006eca: 60fb str r3, [r7, #12] return(result); 8006ecc: 68fb ldr r3, [r7, #12] 8006ece: f023 0310 bic.w r3, r3, #16 8006ed2: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8006ed6: 687b ldr r3, [r7, #4] 8006ed8: 681b ldr r3, [r3, #0] 8006eda: 330c adds r3, #12 8006edc: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8006ee0: 61fa str r2, [r7, #28] 8006ee2: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006ee4: 69b9 ldr r1, [r7, #24] 8006ee6: 69fa ldr r2, [r7, #28] 8006ee8: e841 2300 strex r3, r2, [r1] 8006eec: 617b str r3, [r7, #20] return(result); 8006eee: 697b ldr r3, [r7, #20] 8006ef0: 2b00 cmp r3, #0 8006ef2: d1e3 bne.n 8006ebc /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006ef4: 687b ldr r3, [r7, #4] 8006ef6: 2202 movs r2, #2 8006ef8: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8006efa: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8006efe: 4619 mov r1, r3 8006f00: 6878 ldr r0, [r7, #4] 8006f02: f000 f847 bl 8006f94 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8006f06: e023 b.n 8006f50 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8006f08: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006f0c: f003 0380 and.w r3, r3, #128 @ 0x80 8006f10: 2b00 cmp r3, #0 8006f12: d009 beq.n 8006f28 8006f14: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006f18: f003 0380 and.w r3, r3, #128 @ 0x80 8006f1c: 2b00 cmp r3, #0 8006f1e: d003 beq.n 8006f28 { UART_Transmit_IT(huart); 8006f20: 6878 ldr r0, [r7, #4] 8006f22: f000 fadf bl 80074e4 return; 8006f26: e014 b.n 8006f52 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8006f28: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006f2c: f003 0340 and.w r3, r3, #64 @ 0x40 8006f30: 2b00 cmp r3, #0 8006f32: d00e beq.n 8006f52 8006f34: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006f38: f003 0340 and.w r3, r3, #64 @ 0x40 8006f3c: 2b00 cmp r3, #0 8006f3e: d008 beq.n 8006f52 { UART_EndTransmit_IT(huart); 8006f40: 6878 ldr r0, [r7, #4] 8006f42: f000 fb1f bl 8007584 return; 8006f46: e004 b.n 8006f52 return; 8006f48: bf00 nop 8006f4a: e002 b.n 8006f52 return; 8006f4c: bf00 nop 8006f4e: e000 b.n 8006f52 return; 8006f50: bf00 nop } } 8006f52: 37e8 adds r7, #232 @ 0xe8 8006f54: 46bd mov sp, r7 8006f56: bd80 pop {r7, pc} 08006f58 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8006f58: b480 push {r7} 8006f5a: b083 sub sp, #12 8006f5c: af00 add r7, sp, #0 8006f5e: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8006f60: bf00 nop 8006f62: 370c adds r7, #12 8006f64: 46bd mov sp, r7 8006f66: f85d 7b04 ldr.w r7, [sp], #4 8006f6a: 4770 bx lr 08006f6c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8006f6c: b480 push {r7} 8006f6e: b083 sub sp, #12 8006f70: af00 add r7, sp, #0 8006f72: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 8006f74: bf00 nop 8006f76: 370c adds r7, #12 8006f78: 46bd mov sp, r7 8006f7a: f85d 7b04 ldr.w r7, [sp], #4 8006f7e: 4770 bx lr 08006f80 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8006f80: b480 push {r7} 8006f82: b083 sub sp, #12 8006f84: af00 add r7, sp, #0 8006f86: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 8006f88: bf00 nop 8006f8a: 370c adds r7, #12 8006f8c: 46bd mov sp, r7 8006f8e: f85d 7b04 ldr.w r7, [sp], #4 8006f92: 4770 bx lr 08006f94 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 8006f94: b480 push {r7} 8006f96: b083 sub sp, #12 8006f98: af00 add r7, sp, #0 8006f9a: 6078 str r0, [r7, #4] 8006f9c: 460b mov r3, r1 8006f9e: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 8006fa0: bf00 nop 8006fa2: 370c adds r7, #12 8006fa4: 46bd mov sp, r7 8006fa6: f85d 7b04 ldr.w r7, [sp], #4 8006faa: 4770 bx lr 08006fac : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 8006fac: b580 push {r7, lr} 8006fae: b090 sub sp, #64 @ 0x40 8006fb0: af00 add r7, sp, #0 8006fb2: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006fb4: 687b ldr r3, [r7, #4] 8006fb6: 6b9b ldr r3, [r3, #56] @ 0x38 8006fb8: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 8006fba: 687b ldr r3, [r7, #4] 8006fbc: 681b ldr r3, [r3, #0] 8006fbe: 681b ldr r3, [r3, #0] 8006fc0: f403 7380 and.w r3, r3, #256 @ 0x100 8006fc4: 2b00 cmp r3, #0 8006fc6: d137 bne.n 8007038 { huart->TxXferCount = 0x00U; 8006fc8: 6bfb ldr r3, [r7, #60] @ 0x3c 8006fca: 2200 movs r2, #0 8006fcc: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8006fce: 6bfb ldr r3, [r7, #60] @ 0x3c 8006fd0: 681b ldr r3, [r3, #0] 8006fd2: 3314 adds r3, #20 8006fd4: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006fd6: 6a7b ldr r3, [r7, #36] @ 0x24 8006fd8: e853 3f00 ldrex r3, [r3] 8006fdc: 623b str r3, [r7, #32] return(result); 8006fde: 6a3b ldr r3, [r7, #32] 8006fe0: f023 0380 bic.w r3, r3, #128 @ 0x80 8006fe4: 63bb str r3, [r7, #56] @ 0x38 8006fe6: 6bfb ldr r3, [r7, #60] @ 0x3c 8006fe8: 681b ldr r3, [r3, #0] 8006fea: 3314 adds r3, #20 8006fec: 6bba ldr r2, [r7, #56] @ 0x38 8006fee: 633a str r2, [r7, #48] @ 0x30 8006ff0: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006ff2: 6af9 ldr r1, [r7, #44] @ 0x2c 8006ff4: 6b3a ldr r2, [r7, #48] @ 0x30 8006ff6: e841 2300 strex r3, r2, [r1] 8006ffa: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006ffc: 6abb ldr r3, [r7, #40] @ 0x28 8006ffe: 2b00 cmp r3, #0 8007000: d1e5 bne.n 8006fce /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8007002: 6bfb ldr r3, [r7, #60] @ 0x3c 8007004: 681b ldr r3, [r3, #0] 8007006: 330c adds r3, #12 8007008: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800700a: 693b ldr r3, [r7, #16] 800700c: e853 3f00 ldrex r3, [r3] 8007010: 60fb str r3, [r7, #12] return(result); 8007012: 68fb ldr r3, [r7, #12] 8007014: f043 0340 orr.w r3, r3, #64 @ 0x40 8007018: 637b str r3, [r7, #52] @ 0x34 800701a: 6bfb ldr r3, [r7, #60] @ 0x3c 800701c: 681b ldr r3, [r3, #0] 800701e: 330c adds r3, #12 8007020: 6b7a ldr r2, [r7, #52] @ 0x34 8007022: 61fa str r2, [r7, #28] 8007024: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007026: 69b9 ldr r1, [r7, #24] 8007028: 69fa ldr r2, [r7, #28] 800702a: e841 2300 strex r3, r2, [r1] 800702e: 617b str r3, [r7, #20] return(result); 8007030: 697b ldr r3, [r7, #20] 8007032: 2b00 cmp r3, #0 8007034: d1e5 bne.n 8007002 #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8007036: e002 b.n 800703e HAL_UART_TxCpltCallback(huart); 8007038: 6bf8 ldr r0, [r7, #60] @ 0x3c 800703a: f7ff ff8d bl 8006f58 } 800703e: bf00 nop 8007040: 3740 adds r7, #64 @ 0x40 8007042: 46bd mov sp, r7 8007044: bd80 pop {r7, pc} 08007046 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 8007046: b580 push {r7, lr} 8007048: b084 sub sp, #16 800704a: af00 add r7, sp, #0 800704c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800704e: 687b ldr r3, [r7, #4] 8007050: 6b9b ldr r3, [r3, #56] @ 0x38 8007052: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 8007054: 68f8 ldr r0, [r7, #12] 8007056: f7ff ff89 bl 8006f6c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800705a: bf00 nop 800705c: 3710 adds r7, #16 800705e: 46bd mov sp, r7 8007060: bd80 pop {r7, pc} 08007062 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 8007062: b580 push {r7, lr} 8007064: b09c sub sp, #112 @ 0x70 8007066: af00 add r7, sp, #0 8007068: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800706a: 687b ldr r3, [r7, #4] 800706c: 6b9b ldr r3, [r3, #56] @ 0x38 800706e: 66fb str r3, [r7, #108] @ 0x6c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 8007070: 687b ldr r3, [r7, #4] 8007072: 681b ldr r3, [r3, #0] 8007074: 681b ldr r3, [r3, #0] 8007076: f403 7380 and.w r3, r3, #256 @ 0x100 800707a: 2b00 cmp r3, #0 800707c: d172 bne.n 8007164 { huart->RxXferCount = 0U; 800707e: 6efb ldr r3, [r7, #108] @ 0x6c 8007080: 2200 movs r2, #0 8007082: 85da strh r2, [r3, #46] @ 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8007084: 6efb ldr r3, [r7, #108] @ 0x6c 8007086: 681b ldr r3, [r3, #0] 8007088: 330c adds r3, #12 800708a: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800708c: 6cfb ldr r3, [r7, #76] @ 0x4c 800708e: e853 3f00 ldrex r3, [r3] 8007092: 64bb str r3, [r7, #72] @ 0x48 return(result); 8007094: 6cbb ldr r3, [r7, #72] @ 0x48 8007096: f423 7380 bic.w r3, r3, #256 @ 0x100 800709a: 66bb str r3, [r7, #104] @ 0x68 800709c: 6efb ldr r3, [r7, #108] @ 0x6c 800709e: 681b ldr r3, [r3, #0] 80070a0: 330c adds r3, #12 80070a2: 6eba ldr r2, [r7, #104] @ 0x68 80070a4: 65ba str r2, [r7, #88] @ 0x58 80070a6: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80070a8: 6d79 ldr r1, [r7, #84] @ 0x54 80070aa: 6dba ldr r2, [r7, #88] @ 0x58 80070ac: e841 2300 strex r3, r2, [r1] 80070b0: 653b str r3, [r7, #80] @ 0x50 return(result); 80070b2: 6d3b ldr r3, [r7, #80] @ 0x50 80070b4: 2b00 cmp r3, #0 80070b6: d1e5 bne.n 8007084 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80070b8: 6efb ldr r3, [r7, #108] @ 0x6c 80070ba: 681b ldr r3, [r3, #0] 80070bc: 3314 adds r3, #20 80070be: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80070c0: 6bbb ldr r3, [r7, #56] @ 0x38 80070c2: e853 3f00 ldrex r3, [r3] 80070c6: 637b str r3, [r7, #52] @ 0x34 return(result); 80070c8: 6b7b ldr r3, [r7, #52] @ 0x34 80070ca: f023 0301 bic.w r3, r3, #1 80070ce: 667b str r3, [r7, #100] @ 0x64 80070d0: 6efb ldr r3, [r7, #108] @ 0x6c 80070d2: 681b ldr r3, [r3, #0] 80070d4: 3314 adds r3, #20 80070d6: 6e7a ldr r2, [r7, #100] @ 0x64 80070d8: 647a str r2, [r7, #68] @ 0x44 80070da: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80070dc: 6c39 ldr r1, [r7, #64] @ 0x40 80070de: 6c7a ldr r2, [r7, #68] @ 0x44 80070e0: e841 2300 strex r3, r2, [r1] 80070e4: 63fb str r3, [r7, #60] @ 0x3c return(result); 80070e6: 6bfb ldr r3, [r7, #60] @ 0x3c 80070e8: 2b00 cmp r3, #0 80070ea: d1e5 bne.n 80070b8 /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80070ec: 6efb ldr r3, [r7, #108] @ 0x6c 80070ee: 681b ldr r3, [r3, #0] 80070f0: 3314 adds r3, #20 80070f2: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80070f4: 6a7b ldr r3, [r7, #36] @ 0x24 80070f6: e853 3f00 ldrex r3, [r3] 80070fa: 623b str r3, [r7, #32] return(result); 80070fc: 6a3b ldr r3, [r7, #32] 80070fe: f023 0340 bic.w r3, r3, #64 @ 0x40 8007102: 663b str r3, [r7, #96] @ 0x60 8007104: 6efb ldr r3, [r7, #108] @ 0x6c 8007106: 681b ldr r3, [r3, #0] 8007108: 3314 adds r3, #20 800710a: 6e3a ldr r2, [r7, #96] @ 0x60 800710c: 633a str r2, [r7, #48] @ 0x30 800710e: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007110: 6af9 ldr r1, [r7, #44] @ 0x2c 8007112: 6b3a ldr r2, [r7, #48] @ 0x30 8007114: e841 2300 strex r3, r2, [r1] 8007118: 62bb str r3, [r7, #40] @ 0x28 return(result); 800711a: 6abb ldr r3, [r7, #40] @ 0x28 800711c: 2b00 cmp r3, #0 800711e: d1e5 bne.n 80070ec /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8007120: 6efb ldr r3, [r7, #108] @ 0x6c 8007122: 2220 movs r2, #32 8007124: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8007128: 6efb ldr r3, [r7, #108] @ 0x6c 800712a: 6b1b ldr r3, [r3, #48] @ 0x30 800712c: 2b01 cmp r3, #1 800712e: d119 bne.n 8007164 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8007130: 6efb ldr r3, [r7, #108] @ 0x6c 8007132: 681b ldr r3, [r3, #0] 8007134: 330c adds r3, #12 8007136: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007138: 693b ldr r3, [r7, #16] 800713a: e853 3f00 ldrex r3, [r3] 800713e: 60fb str r3, [r7, #12] return(result); 8007140: 68fb ldr r3, [r7, #12] 8007142: f023 0310 bic.w r3, r3, #16 8007146: 65fb str r3, [r7, #92] @ 0x5c 8007148: 6efb ldr r3, [r7, #108] @ 0x6c 800714a: 681b ldr r3, [r3, #0] 800714c: 330c adds r3, #12 800714e: 6dfa ldr r2, [r7, #92] @ 0x5c 8007150: 61fa str r2, [r7, #28] 8007152: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007154: 69b9 ldr r1, [r7, #24] 8007156: 69fa ldr r2, [r7, #28] 8007158: e841 2300 strex r3, r2, [r1] 800715c: 617b str r3, [r7, #20] return(result); 800715e: 697b ldr r3, [r7, #20] 8007160: 2b00 cmp r3, #0 8007162: d1e5 bne.n 8007130 } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8007164: 6efb ldr r3, [r7, #108] @ 0x6c 8007166: 2200 movs r2, #0 8007168: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800716a: 6efb ldr r3, [r7, #108] @ 0x6c 800716c: 6b1b ldr r3, [r3, #48] @ 0x30 800716e: 2b01 cmp r3, #1 8007170: d106 bne.n 8007180 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8007172: 6efb ldr r3, [r7, #108] @ 0x6c 8007174: 8d9b ldrh r3, [r3, #44] @ 0x2c 8007176: 4619 mov r1, r3 8007178: 6ef8 ldr r0, [r7, #108] @ 0x6c 800717a: f7ff ff0b bl 8006f94 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 800717e: e002 b.n 8007186 HAL_UART_RxCpltCallback(huart); 8007180: 6ef8 ldr r0, [r7, #108] @ 0x6c 8007182: f7f9 fe43 bl 8000e0c } 8007186: bf00 nop 8007188: 3770 adds r7, #112 @ 0x70 800718a: 46bd mov sp, r7 800718c: bd80 pop {r7, pc} 0800718e : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 800718e: b580 push {r7, lr} 8007190: b084 sub sp, #16 8007192: af00 add r7, sp, #0 8007194: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8007196: 687b ldr r3, [r7, #4] 8007198: 6b9b ldr r3, [r3, #56] @ 0x38 800719a: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 800719c: 68fb ldr r3, [r7, #12] 800719e: 2201 movs r2, #1 80071a0: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80071a2: 68fb ldr r3, [r7, #12] 80071a4: 6b1b ldr r3, [r3, #48] @ 0x30 80071a6: 2b01 cmp r3, #1 80071a8: d108 bne.n 80071bc #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 80071aa: 68fb ldr r3, [r7, #12] 80071ac: 8d9b ldrh r3, [r3, #44] @ 0x2c 80071ae: 085b lsrs r3, r3, #1 80071b0: b29b uxth r3, r3 80071b2: 4619 mov r1, r3 80071b4: 68f8 ldr r0, [r7, #12] 80071b6: f7ff feed bl 8006f94 #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 80071ba: e002 b.n 80071c2 HAL_UART_RxHalfCpltCallback(huart); 80071bc: 68f8 ldr r0, [r7, #12] 80071be: f7ff fedf bl 8006f80 } 80071c2: bf00 nop 80071c4: 3710 adds r7, #16 80071c6: 46bd mov sp, r7 80071c8: bd80 pop {r7, pc} 080071ca : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 80071ca: b580 push {r7, lr} 80071cc: b084 sub sp, #16 80071ce: af00 add r7, sp, #0 80071d0: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 80071d2: 2300 movs r3, #0 80071d4: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80071d6: 687b ldr r3, [r7, #4] 80071d8: 6b9b ldr r3, [r3, #56] @ 0x38 80071da: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 80071dc: 68bb ldr r3, [r7, #8] 80071de: 681b ldr r3, [r3, #0] 80071e0: 695b ldr r3, [r3, #20] 80071e2: f003 0380 and.w r3, r3, #128 @ 0x80 80071e6: 2b80 cmp r3, #128 @ 0x80 80071e8: bf0c ite eq 80071ea: 2301 moveq r3, #1 80071ec: 2300 movne r3, #0 80071ee: b2db uxtb r3, r3 80071f0: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 80071f2: 68bb ldr r3, [r7, #8] 80071f4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80071f8: b2db uxtb r3, r3 80071fa: 2b21 cmp r3, #33 @ 0x21 80071fc: d108 bne.n 8007210 80071fe: 68fb ldr r3, [r7, #12] 8007200: 2b00 cmp r3, #0 8007202: d005 beq.n 8007210 { huart->TxXferCount = 0x00U; 8007204: 68bb ldr r3, [r7, #8] 8007206: 2200 movs r2, #0 8007208: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 800720a: 68b8 ldr r0, [r7, #8] 800720c: f000 f8ce bl 80073ac } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8007210: 68bb ldr r3, [r7, #8] 8007212: 681b ldr r3, [r3, #0] 8007214: 695b ldr r3, [r3, #20] 8007216: f003 0340 and.w r3, r3, #64 @ 0x40 800721a: 2b40 cmp r3, #64 @ 0x40 800721c: bf0c ite eq 800721e: 2301 moveq r3, #1 8007220: 2300 movne r3, #0 8007222: b2db uxtb r3, r3 8007224: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8007226: 68bb ldr r3, [r7, #8] 8007228: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800722c: b2db uxtb r3, r3 800722e: 2b22 cmp r3, #34 @ 0x22 8007230: d108 bne.n 8007244 8007232: 68fb ldr r3, [r7, #12] 8007234: 2b00 cmp r3, #0 8007236: d005 beq.n 8007244 { huart->RxXferCount = 0x00U; 8007238: 68bb ldr r3, [r7, #8] 800723a: 2200 movs r2, #0 800723c: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 800723e: 68b8 ldr r0, [r7, #8] 8007240: f000 f8dc bl 80073fc } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8007244: 68bb ldr r3, [r7, #8] 8007246: 6c5b ldr r3, [r3, #68] @ 0x44 8007248: f043 0210 orr.w r2, r3, #16 800724c: 68bb ldr r3, [r7, #8] 800724e: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8007250: 68b8 ldr r0, [r7, #8] 8007252: f7f9 fe37 bl 8000ec4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8007256: bf00 nop 8007258: 3710 adds r7, #16 800725a: 46bd mov sp, r7 800725c: bd80 pop {r7, pc} ... 08007260 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8007260: b580 push {r7, lr} 8007262: b098 sub sp, #96 @ 0x60 8007264: af00 add r7, sp, #0 8007266: 60f8 str r0, [r7, #12] 8007268: 60b9 str r1, [r7, #8] 800726a: 4613 mov r3, r2 800726c: 80fb strh r3, [r7, #6] uint32_t *tmp; huart->pRxBuffPtr = pData; 800726e: 68ba ldr r2, [r7, #8] 8007270: 68fb ldr r3, [r7, #12] 8007272: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 8007274: 68fb ldr r3, [r7, #12] 8007276: 88fa ldrh r2, [r7, #6] 8007278: 859a strh r2, [r3, #44] @ 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 800727a: 68fb ldr r3, [r7, #12] 800727c: 2200 movs r2, #0 800727e: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8007280: 68fb ldr r3, [r7, #12] 8007282: 2222 movs r2, #34 @ 0x22 8007284: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 8007288: 68fb ldr r3, [r7, #12] 800728a: 6bdb ldr r3, [r3, #60] @ 0x3c 800728c: 4a44 ldr r2, [pc, #272] @ (80073a0 ) 800728e: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 8007290: 68fb ldr r3, [r7, #12] 8007292: 6bdb ldr r3, [r3, #60] @ 0x3c 8007294: 4a43 ldr r2, [pc, #268] @ (80073a4 ) 8007296: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 8007298: 68fb ldr r3, [r7, #12] 800729a: 6bdb ldr r3, [r3, #60] @ 0x3c 800729c: 4a42 ldr r2, [pc, #264] @ (80073a8 ) 800729e: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 80072a0: 68fb ldr r3, [r7, #12] 80072a2: 6bdb ldr r3, [r3, #60] @ 0x3c 80072a4: 2200 movs r2, #0 80072a6: 651a str r2, [r3, #80] @ 0x50 /* Enable the DMA stream */ tmp = (uint32_t *)&pData; 80072a8: f107 0308 add.w r3, r7, #8 80072ac: 65fb str r3, [r7, #92] @ 0x5c if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK) 80072ae: 68fb ldr r3, [r7, #12] 80072b0: 6bd8 ldr r0, [r3, #60] @ 0x3c 80072b2: 68fb ldr r3, [r7, #12] 80072b4: 681b ldr r3, [r3, #0] 80072b6: 3304 adds r3, #4 80072b8: 4619 mov r1, r3 80072ba: 6dfb ldr r3, [r7, #92] @ 0x5c 80072bc: 681a ldr r2, [r3, #0] 80072be: 88fb ldrh r3, [r7, #6] 80072c0: f7fa fff0 bl 80022a4 80072c4: 4603 mov r3, r0 80072c6: 2b00 cmp r3, #0 80072c8: d008 beq.n 80072dc { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 80072ca: 68fb ldr r3, [r7, #12] 80072cc: 2210 movs r2, #16 80072ce: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; 80072d0: 68fb ldr r3, [r7, #12] 80072d2: 2220 movs r2, #32 80072d4: f883 2042 strb.w r2, [r3, #66] @ 0x42 return HAL_ERROR; 80072d8: 2301 movs r3, #1 80072da: e05d b.n 8007398 } /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 80072dc: 2300 movs r3, #0 80072de: 613b str r3, [r7, #16] 80072e0: 68fb ldr r3, [r7, #12] 80072e2: 681b ldr r3, [r3, #0] 80072e4: 681b ldr r3, [r3, #0] 80072e6: 613b str r3, [r7, #16] 80072e8: 68fb ldr r3, [r7, #12] 80072ea: 681b ldr r3, [r3, #0] 80072ec: 685b ldr r3, [r3, #4] 80072ee: 613b str r3, [r7, #16] 80072f0: 693b ldr r3, [r7, #16] if (huart->Init.Parity != UART_PARITY_NONE) 80072f2: 68fb ldr r3, [r7, #12] 80072f4: 691b ldr r3, [r3, #16] 80072f6: 2b00 cmp r3, #0 80072f8: d019 beq.n 800732e { /* Enable the UART Parity Error Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80072fa: 68fb ldr r3, [r7, #12] 80072fc: 681b ldr r3, [r3, #0] 80072fe: 330c adds r3, #12 8007300: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007302: 6c3b ldr r3, [r7, #64] @ 0x40 8007304: e853 3f00 ldrex r3, [r3] 8007308: 63fb str r3, [r7, #60] @ 0x3c return(result); 800730a: 6bfb ldr r3, [r7, #60] @ 0x3c 800730c: f443 7380 orr.w r3, r3, #256 @ 0x100 8007310: 65bb str r3, [r7, #88] @ 0x58 8007312: 68fb ldr r3, [r7, #12] 8007314: 681b ldr r3, [r3, #0] 8007316: 330c adds r3, #12 8007318: 6dba ldr r2, [r7, #88] @ 0x58 800731a: 64fa str r2, [r7, #76] @ 0x4c 800731c: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800731e: 6cb9 ldr r1, [r7, #72] @ 0x48 8007320: 6cfa ldr r2, [r7, #76] @ 0x4c 8007322: e841 2300 strex r3, r2, [r1] 8007326: 647b str r3, [r7, #68] @ 0x44 return(result); 8007328: 6c7b ldr r3, [r7, #68] @ 0x44 800732a: 2b00 cmp r3, #0 800732c: d1e5 bne.n 80072fa } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 800732e: 68fb ldr r3, [r7, #12] 8007330: 681b ldr r3, [r3, #0] 8007332: 3314 adds r3, #20 8007334: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007336: 6afb ldr r3, [r7, #44] @ 0x2c 8007338: e853 3f00 ldrex r3, [r3] 800733c: 62bb str r3, [r7, #40] @ 0x28 return(result); 800733e: 6abb ldr r3, [r7, #40] @ 0x28 8007340: f043 0301 orr.w r3, r3, #1 8007344: 657b str r3, [r7, #84] @ 0x54 8007346: 68fb ldr r3, [r7, #12] 8007348: 681b ldr r3, [r3, #0] 800734a: 3314 adds r3, #20 800734c: 6d7a ldr r2, [r7, #84] @ 0x54 800734e: 63ba str r2, [r7, #56] @ 0x38 8007350: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007352: 6b79 ldr r1, [r7, #52] @ 0x34 8007354: 6bba ldr r2, [r7, #56] @ 0x38 8007356: e841 2300 strex r3, r2, [r1] 800735a: 633b str r3, [r7, #48] @ 0x30 return(result); 800735c: 6b3b ldr r3, [r7, #48] @ 0x30 800735e: 2b00 cmp r3, #0 8007360: d1e5 bne.n 800732e /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8007362: 68fb ldr r3, [r7, #12] 8007364: 681b ldr r3, [r3, #0] 8007366: 3314 adds r3, #20 8007368: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800736a: 69bb ldr r3, [r7, #24] 800736c: e853 3f00 ldrex r3, [r3] 8007370: 617b str r3, [r7, #20] return(result); 8007372: 697b ldr r3, [r7, #20] 8007374: f043 0340 orr.w r3, r3, #64 @ 0x40 8007378: 653b str r3, [r7, #80] @ 0x50 800737a: 68fb ldr r3, [r7, #12] 800737c: 681b ldr r3, [r3, #0] 800737e: 3314 adds r3, #20 8007380: 6d3a ldr r2, [r7, #80] @ 0x50 8007382: 627a str r2, [r7, #36] @ 0x24 8007384: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007386: 6a39 ldr r1, [r7, #32] 8007388: 6a7a ldr r2, [r7, #36] @ 0x24 800738a: e841 2300 strex r3, r2, [r1] 800738e: 61fb str r3, [r7, #28] return(result); 8007390: 69fb ldr r3, [r7, #28] 8007392: 2b00 cmp r3, #0 8007394: d1e5 bne.n 8007362 return HAL_OK; 8007396: 2300 movs r3, #0 } 8007398: 4618 mov r0, r3 800739a: 3760 adds r7, #96 @ 0x60 800739c: 46bd mov sp, r7 800739e: bd80 pop {r7, pc} 80073a0: 08007063 .word 0x08007063 80073a4: 0800718f .word 0x0800718f 80073a8: 080071cb .word 0x080071cb 080073ac : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 80073ac: b480 push {r7} 80073ae: b089 sub sp, #36 @ 0x24 80073b0: af00 add r7, sp, #0 80073b2: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 80073b4: 687b ldr r3, [r7, #4] 80073b6: 681b ldr r3, [r3, #0] 80073b8: 330c adds r3, #12 80073ba: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80073bc: 68fb ldr r3, [r7, #12] 80073be: e853 3f00 ldrex r3, [r3] 80073c2: 60bb str r3, [r7, #8] return(result); 80073c4: 68bb ldr r3, [r7, #8] 80073c6: f023 03c0 bic.w r3, r3, #192 @ 0xc0 80073ca: 61fb str r3, [r7, #28] 80073cc: 687b ldr r3, [r7, #4] 80073ce: 681b ldr r3, [r3, #0] 80073d0: 330c adds r3, #12 80073d2: 69fa ldr r2, [r7, #28] 80073d4: 61ba str r2, [r7, #24] 80073d6: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80073d8: 6979 ldr r1, [r7, #20] 80073da: 69ba ldr r2, [r7, #24] 80073dc: e841 2300 strex r3, r2, [r1] 80073e0: 613b str r3, [r7, #16] return(result); 80073e2: 693b ldr r3, [r7, #16] 80073e4: 2b00 cmp r3, #0 80073e6: d1e5 bne.n 80073b4 /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80073e8: 687b ldr r3, [r7, #4] 80073ea: 2220 movs r2, #32 80073ec: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 80073f0: bf00 nop 80073f2: 3724 adds r7, #36 @ 0x24 80073f4: 46bd mov sp, r7 80073f6: f85d 7b04 ldr.w r7, [sp], #4 80073fa: 4770 bx lr 080073fc : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 80073fc: b480 push {r7} 80073fe: b095 sub sp, #84 @ 0x54 8007400: af00 add r7, sp, #0 8007402: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8007404: 687b ldr r3, [r7, #4] 8007406: 681b ldr r3, [r3, #0] 8007408: 330c adds r3, #12 800740a: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800740c: 6b7b ldr r3, [r7, #52] @ 0x34 800740e: e853 3f00 ldrex r3, [r3] 8007412: 633b str r3, [r7, #48] @ 0x30 return(result); 8007414: 6b3b ldr r3, [r7, #48] @ 0x30 8007416: f423 7390 bic.w r3, r3, #288 @ 0x120 800741a: 64fb str r3, [r7, #76] @ 0x4c 800741c: 687b ldr r3, [r7, #4] 800741e: 681b ldr r3, [r3, #0] 8007420: 330c adds r3, #12 8007422: 6cfa ldr r2, [r7, #76] @ 0x4c 8007424: 643a str r2, [r7, #64] @ 0x40 8007426: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007428: 6bf9 ldr r1, [r7, #60] @ 0x3c 800742a: 6c3a ldr r2, [r7, #64] @ 0x40 800742c: e841 2300 strex r3, r2, [r1] 8007430: 63bb str r3, [r7, #56] @ 0x38 return(result); 8007432: 6bbb ldr r3, [r7, #56] @ 0x38 8007434: 2b00 cmp r3, #0 8007436: d1e5 bne.n 8007404 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8007438: 687b ldr r3, [r7, #4] 800743a: 681b ldr r3, [r3, #0] 800743c: 3314 adds r3, #20 800743e: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007440: 6a3b ldr r3, [r7, #32] 8007442: e853 3f00 ldrex r3, [r3] 8007446: 61fb str r3, [r7, #28] return(result); 8007448: 69fb ldr r3, [r7, #28] 800744a: f023 0301 bic.w r3, r3, #1 800744e: 64bb str r3, [r7, #72] @ 0x48 8007450: 687b ldr r3, [r7, #4] 8007452: 681b ldr r3, [r3, #0] 8007454: 3314 adds r3, #20 8007456: 6cba ldr r2, [r7, #72] @ 0x48 8007458: 62fa str r2, [r7, #44] @ 0x2c 800745a: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800745c: 6ab9 ldr r1, [r7, #40] @ 0x28 800745e: 6afa ldr r2, [r7, #44] @ 0x2c 8007460: e841 2300 strex r3, r2, [r1] 8007464: 627b str r3, [r7, #36] @ 0x24 return(result); 8007466: 6a7b ldr r3, [r7, #36] @ 0x24 8007468: 2b00 cmp r3, #0 800746a: d1e5 bne.n 8007438 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800746c: 687b ldr r3, [r7, #4] 800746e: 6b1b ldr r3, [r3, #48] @ 0x30 8007470: 2b01 cmp r3, #1 8007472: d119 bne.n 80074a8 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8007474: 687b ldr r3, [r7, #4] 8007476: 681b ldr r3, [r3, #0] 8007478: 330c adds r3, #12 800747a: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800747c: 68fb ldr r3, [r7, #12] 800747e: e853 3f00 ldrex r3, [r3] 8007482: 60bb str r3, [r7, #8] return(result); 8007484: 68bb ldr r3, [r7, #8] 8007486: f023 0310 bic.w r3, r3, #16 800748a: 647b str r3, [r7, #68] @ 0x44 800748c: 687b ldr r3, [r7, #4] 800748e: 681b ldr r3, [r3, #0] 8007490: 330c adds r3, #12 8007492: 6c7a ldr r2, [r7, #68] @ 0x44 8007494: 61ba str r2, [r7, #24] 8007496: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007498: 6979 ldr r1, [r7, #20] 800749a: 69ba ldr r2, [r7, #24] 800749c: e841 2300 strex r3, r2, [r1] 80074a0: 613b str r3, [r7, #16] return(result); 80074a2: 693b ldr r3, [r7, #16] 80074a4: 2b00 cmp r3, #0 80074a6: d1e5 bne.n 8007474 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80074a8: 687b ldr r3, [r7, #4] 80074aa: 2220 movs r2, #32 80074ac: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80074b0: 687b ldr r3, [r7, #4] 80074b2: 2200 movs r2, #0 80074b4: 631a str r2, [r3, #48] @ 0x30 } 80074b6: bf00 nop 80074b8: 3754 adds r7, #84 @ 0x54 80074ba: 46bd mov sp, r7 80074bc: f85d 7b04 ldr.w r7, [sp], #4 80074c0: 4770 bx lr 080074c2 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 80074c2: b580 push {r7, lr} 80074c4: b084 sub sp, #16 80074c6: af00 add r7, sp, #0 80074c8: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80074ca: 687b ldr r3, [r7, #4] 80074cc: 6b9b ldr r3, [r3, #56] @ 0x38 80074ce: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 80074d0: 68fb ldr r3, [r7, #12] 80074d2: 2200 movs r2, #0 80074d4: 85da strh r2, [r3, #46] @ 0x2e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80074d6: 68f8 ldr r0, [r7, #12] 80074d8: f7f9 fcf4 bl 8000ec4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80074dc: bf00 nop 80074de: 3710 adds r7, #16 80074e0: 46bd mov sp, r7 80074e2: bd80 pop {r7, pc} 080074e4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 80074e4: b480 push {r7} 80074e6: b085 sub sp, #20 80074e8: af00 add r7, sp, #0 80074ea: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80074ec: 687b ldr r3, [r7, #4] 80074ee: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80074f2: b2db uxtb r3, r3 80074f4: 2b21 cmp r3, #33 @ 0x21 80074f6: d13e bne.n 8007576 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80074f8: 687b ldr r3, [r7, #4] 80074fa: 689b ldr r3, [r3, #8] 80074fc: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8007500: d114 bne.n 800752c 8007502: 687b ldr r3, [r7, #4] 8007504: 691b ldr r3, [r3, #16] 8007506: 2b00 cmp r3, #0 8007508: d110 bne.n 800752c { tmp = (const uint16_t *) huart->pTxBuffPtr; 800750a: 687b ldr r3, [r7, #4] 800750c: 6a1b ldr r3, [r3, #32] 800750e: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8007510: 68fb ldr r3, [r7, #12] 8007512: 881b ldrh r3, [r3, #0] 8007514: 461a mov r2, r3 8007516: 687b ldr r3, [r7, #4] 8007518: 681b ldr r3, [r3, #0] 800751a: f3c2 0208 ubfx r2, r2, #0, #9 800751e: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8007520: 687b ldr r3, [r7, #4] 8007522: 6a1b ldr r3, [r3, #32] 8007524: 1c9a adds r2, r3, #2 8007526: 687b ldr r3, [r7, #4] 8007528: 621a str r2, [r3, #32] 800752a: e008 b.n 800753e } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 800752c: 687b ldr r3, [r7, #4] 800752e: 6a1b ldr r3, [r3, #32] 8007530: 1c59 adds r1, r3, #1 8007532: 687a ldr r2, [r7, #4] 8007534: 6211 str r1, [r2, #32] 8007536: 781a ldrb r2, [r3, #0] 8007538: 687b ldr r3, [r7, #4] 800753a: 681b ldr r3, [r3, #0] 800753c: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 800753e: 687b ldr r3, [r7, #4] 8007540: 8cdb ldrh r3, [r3, #38] @ 0x26 8007542: b29b uxth r3, r3 8007544: 3b01 subs r3, #1 8007546: b29b uxth r3, r3 8007548: 687a ldr r2, [r7, #4] 800754a: 4619 mov r1, r3 800754c: 84d1 strh r1, [r2, #38] @ 0x26 800754e: 2b00 cmp r3, #0 8007550: d10f bne.n 8007572 { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8007552: 687b ldr r3, [r7, #4] 8007554: 681b ldr r3, [r3, #0] 8007556: 68da ldr r2, [r3, #12] 8007558: 687b ldr r3, [r7, #4] 800755a: 681b ldr r3, [r3, #0] 800755c: f022 0280 bic.w r2, r2, #128 @ 0x80 8007560: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8007562: 687b ldr r3, [r7, #4] 8007564: 681b ldr r3, [r3, #0] 8007566: 68da ldr r2, [r3, #12] 8007568: 687b ldr r3, [r7, #4] 800756a: 681b ldr r3, [r3, #0] 800756c: f042 0240 orr.w r2, r2, #64 @ 0x40 8007570: 60da str r2, [r3, #12] } return HAL_OK; 8007572: 2300 movs r3, #0 8007574: e000 b.n 8007578 } else { return HAL_BUSY; 8007576: 2302 movs r3, #2 } } 8007578: 4618 mov r0, r3 800757a: 3714 adds r7, #20 800757c: 46bd mov sp, r7 800757e: f85d 7b04 ldr.w r7, [sp], #4 8007582: 4770 bx lr 08007584 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8007584: b580 push {r7, lr} 8007586: b082 sub sp, #8 8007588: af00 add r7, sp, #0 800758a: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 800758c: 687b ldr r3, [r7, #4] 800758e: 681b ldr r3, [r3, #0] 8007590: 68da ldr r2, [r3, #12] 8007592: 687b ldr r3, [r7, #4] 8007594: 681b ldr r3, [r3, #0] 8007596: f022 0240 bic.w r2, r2, #64 @ 0x40 800759a: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 800759c: 687b ldr r3, [r7, #4] 800759e: 2220 movs r2, #32 80075a0: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 80075a4: 6878 ldr r0, [r7, #4] 80075a6: f7ff fcd7 bl 8006f58 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 80075aa: 2300 movs r3, #0 } 80075ac: 4618 mov r0, r3 80075ae: 3708 adds r7, #8 80075b0: 46bd mov sp, r7 80075b2: bd80 pop {r7, pc} 080075b4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 80075b4: b580 push {r7, lr} 80075b6: b08c sub sp, #48 @ 0x30 80075b8: af00 add r7, sp, #0 80075ba: 6078 str r0, [r7, #4] uint8_t *pdata8bits = NULL; 80075bc: 2300 movs r3, #0 80075be: 62fb str r3, [r7, #44] @ 0x2c uint16_t *pdata16bits = NULL; 80075c0: 2300 movs r3, #0 80075c2: 62bb str r3, [r7, #40] @ 0x28 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80075c4: 687b ldr r3, [r7, #4] 80075c6: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80075ca: b2db uxtb r3, r3 80075cc: 2b22 cmp r3, #34 @ 0x22 80075ce: f040 80aa bne.w 8007726 { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80075d2: 687b ldr r3, [r7, #4] 80075d4: 689b ldr r3, [r3, #8] 80075d6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80075da: d115 bne.n 8007608 80075dc: 687b ldr r3, [r7, #4] 80075de: 691b ldr r3, [r3, #16] 80075e0: 2b00 cmp r3, #0 80075e2: d111 bne.n 8007608 { /* Unused pdata8bits */ UNUSED(pdata8bits); pdata16bits = (uint16_t *) huart->pRxBuffPtr; 80075e4: 687b ldr r3, [r7, #4] 80075e6: 6a9b ldr r3, [r3, #40] @ 0x28 80075e8: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 80075ea: 687b ldr r3, [r7, #4] 80075ec: 681b ldr r3, [r3, #0] 80075ee: 685b ldr r3, [r3, #4] 80075f0: b29b uxth r3, r3 80075f2: f3c3 0308 ubfx r3, r3, #0, #9 80075f6: b29a uxth r2, r3 80075f8: 6abb ldr r3, [r7, #40] @ 0x28 80075fa: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 80075fc: 687b ldr r3, [r7, #4] 80075fe: 6a9b ldr r3, [r3, #40] @ 0x28 8007600: 1c9a adds r2, r3, #2 8007602: 687b ldr r3, [r7, #4] 8007604: 629a str r2, [r3, #40] @ 0x28 8007606: e024 b.n 8007652 } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8007608: 687b ldr r3, [r7, #4] 800760a: 6a9b ldr r3, [r3, #40] @ 0x28 800760c: 62fb str r3, [r7, #44] @ 0x2c /* Unused pdata16bits */ UNUSED(pdata16bits); if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 800760e: 687b ldr r3, [r7, #4] 8007610: 689b ldr r3, [r3, #8] 8007612: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8007616: d007 beq.n 8007628 8007618: 687b ldr r3, [r7, #4] 800761a: 689b ldr r3, [r3, #8] 800761c: 2b00 cmp r3, #0 800761e: d10a bne.n 8007636 8007620: 687b ldr r3, [r7, #4] 8007622: 691b ldr r3, [r3, #16] 8007624: 2b00 cmp r3, #0 8007626: d106 bne.n 8007636 { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8007628: 687b ldr r3, [r7, #4] 800762a: 681b ldr r3, [r3, #0] 800762c: 685b ldr r3, [r3, #4] 800762e: b2da uxtb r2, r3 8007630: 6afb ldr r3, [r7, #44] @ 0x2c 8007632: 701a strb r2, [r3, #0] 8007634: e008 b.n 8007648 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8007636: 687b ldr r3, [r7, #4] 8007638: 681b ldr r3, [r3, #0] 800763a: 685b ldr r3, [r3, #4] 800763c: b2db uxtb r3, r3 800763e: f003 037f and.w r3, r3, #127 @ 0x7f 8007642: b2da uxtb r2, r3 8007644: 6afb ldr r3, [r7, #44] @ 0x2c 8007646: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 8007648: 687b ldr r3, [r7, #4] 800764a: 6a9b ldr r3, [r3, #40] @ 0x28 800764c: 1c5a adds r2, r3, #1 800764e: 687b ldr r3, [r7, #4] 8007650: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 8007652: 687b ldr r3, [r7, #4] 8007654: 8ddb ldrh r3, [r3, #46] @ 0x2e 8007656: b29b uxth r3, r3 8007658: 3b01 subs r3, #1 800765a: b29b uxth r3, r3 800765c: 687a ldr r2, [r7, #4] 800765e: 4619 mov r1, r3 8007660: 85d1 strh r1, [r2, #46] @ 0x2e 8007662: 2b00 cmp r3, #0 8007664: d15d bne.n 8007722 { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8007666: 687b ldr r3, [r7, #4] 8007668: 681b ldr r3, [r3, #0] 800766a: 68da ldr r2, [r3, #12] 800766c: 687b ldr r3, [r7, #4] 800766e: 681b ldr r3, [r3, #0] 8007670: f022 0220 bic.w r2, r2, #32 8007674: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8007676: 687b ldr r3, [r7, #4] 8007678: 681b ldr r3, [r3, #0] 800767a: 68da ldr r2, [r3, #12] 800767c: 687b ldr r3, [r7, #4] 800767e: 681b ldr r3, [r3, #0] 8007680: f422 7280 bic.w r2, r2, #256 @ 0x100 8007684: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8007686: 687b ldr r3, [r7, #4] 8007688: 681b ldr r3, [r3, #0] 800768a: 695a ldr r2, [r3, #20] 800768c: 687b ldr r3, [r7, #4] 800768e: 681b ldr r3, [r3, #0] 8007690: f022 0201 bic.w r2, r2, #1 8007694: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8007696: 687b ldr r3, [r7, #4] 8007698: 2220 movs r2, #32 800769a: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 800769e: 687b ldr r3, [r7, #4] 80076a0: 2200 movs r2, #0 80076a2: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80076a4: 687b ldr r3, [r7, #4] 80076a6: 6b1b ldr r3, [r3, #48] @ 0x30 80076a8: 2b01 cmp r3, #1 80076aa: d135 bne.n 8007718 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80076ac: 687b ldr r3, [r7, #4] 80076ae: 2200 movs r2, #0 80076b0: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80076b2: 687b ldr r3, [r7, #4] 80076b4: 681b ldr r3, [r3, #0] 80076b6: 330c adds r3, #12 80076b8: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80076ba: 697b ldr r3, [r7, #20] 80076bc: e853 3f00 ldrex r3, [r3] 80076c0: 613b str r3, [r7, #16] return(result); 80076c2: 693b ldr r3, [r7, #16] 80076c4: f023 0310 bic.w r3, r3, #16 80076c8: 627b str r3, [r7, #36] @ 0x24 80076ca: 687b ldr r3, [r7, #4] 80076cc: 681b ldr r3, [r3, #0] 80076ce: 330c adds r3, #12 80076d0: 6a7a ldr r2, [r7, #36] @ 0x24 80076d2: 623a str r2, [r7, #32] 80076d4: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80076d6: 69f9 ldr r1, [r7, #28] 80076d8: 6a3a ldr r2, [r7, #32] 80076da: e841 2300 strex r3, r2, [r1] 80076de: 61bb str r3, [r7, #24] return(result); 80076e0: 69bb ldr r3, [r7, #24] 80076e2: 2b00 cmp r3, #0 80076e4: d1e5 bne.n 80076b2 /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 80076e6: 687b ldr r3, [r7, #4] 80076e8: 681b ldr r3, [r3, #0] 80076ea: 681b ldr r3, [r3, #0] 80076ec: f003 0310 and.w r3, r3, #16 80076f0: 2b10 cmp r3, #16 80076f2: d10a bne.n 800770a { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 80076f4: 2300 movs r3, #0 80076f6: 60fb str r3, [r7, #12] 80076f8: 687b ldr r3, [r7, #4] 80076fa: 681b ldr r3, [r3, #0] 80076fc: 681b ldr r3, [r3, #0] 80076fe: 60fb str r3, [r7, #12] 8007700: 687b ldr r3, [r7, #4] 8007702: 681b ldr r3, [r3, #0] 8007704: 685b ldr r3, [r3, #4] 8007706: 60fb str r3, [r7, #12] 8007708: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800770a: 687b ldr r3, [r7, #4] 800770c: 8d9b ldrh r3, [r3, #44] @ 0x2c 800770e: 4619 mov r1, r3 8007710: 6878 ldr r0, [r7, #4] 8007712: f7ff fc3f bl 8006f94 8007716: e002 b.n 800771e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8007718: 6878 ldr r0, [r7, #4] 800771a: f7f9 fb77 bl 8000e0c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 800771e: 2300 movs r3, #0 8007720: e002 b.n 8007728 } return HAL_OK; 8007722: 2300 movs r3, #0 8007724: e000 b.n 8007728 } else { return HAL_BUSY; 8007726: 2302 movs r3, #2 } } 8007728: 4618 mov r0, r3 800772a: 3730 adds r7, #48 @ 0x30 800772c: 46bd mov sp, r7 800772e: bd80 pop {r7, pc} 08007730 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8007730: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8007734: b0c0 sub sp, #256 @ 0x100 8007736: af00 add r7, sp, #0 8007738: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4 assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 800773c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007740: 681b ldr r3, [r3, #0] 8007742: 691b ldr r3, [r3, #16] 8007744: f423 5040 bic.w r0, r3, #12288 @ 0x3000 8007748: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800774c: 68d9 ldr r1, [r3, #12] 800774e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007752: 681a ldr r2, [r3, #0] 8007754: ea40 0301 orr.w r3, r0, r1 8007758: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 800775a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800775e: 689a ldr r2, [r3, #8] 8007760: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007764: 691b ldr r3, [r3, #16] 8007766: 431a orrs r2, r3 8007768: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800776c: 695b ldr r3, [r3, #20] 800776e: 431a orrs r2, r3 8007770: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007774: 69db ldr r3, [r3, #28] 8007776: 4313 orrs r3, r2 8007778: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 MODIFY_REG(huart->Instance->CR1, 800777c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007780: 681b ldr r3, [r3, #0] 8007782: 68db ldr r3, [r3, #12] 8007784: f423 4116 bic.w r1, r3, #38400 @ 0x9600 8007788: f021 010c bic.w r1, r1, #12 800778c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007790: 681a ldr r2, [r3, #0] 8007792: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 8007796: 430b orrs r3, r1 8007798: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 800779a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800779e: 681b ldr r3, [r3, #0] 80077a0: 695b ldr r3, [r3, #20] 80077a2: f423 7040 bic.w r0, r3, #768 @ 0x300 80077a6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80077aa: 6999 ldr r1, [r3, #24] 80077ac: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80077b0: 681a ldr r2, [r3, #0] 80077b2: ea40 0301 orr.w r3, r0, r1 80077b6: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 80077b8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80077bc: 681a ldr r2, [r3, #0] 80077be: 4b8f ldr r3, [pc, #572] @ (80079fc ) 80077c0: 429a cmp r2, r3 80077c2: d005 beq.n 80077d0 80077c4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80077c8: 681a ldr r2, [r3, #0] 80077ca: 4b8d ldr r3, [pc, #564] @ (8007a00 ) 80077cc: 429a cmp r2, r3 80077ce: d104 bne.n 80077da { pclk = HAL_RCC_GetPCLK2Freq(); 80077d0: f7fc ff52 bl 8004678 80077d4: f8c7 00fc str.w r0, [r7, #252] @ 0xfc 80077d8: e003 b.n 80077e2 pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); 80077da: f7fc ff39 bl 8004650 80077de: f8c7 00fc str.w r0, [r7, #252] @ 0xfc } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 80077e2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80077e6: 69db ldr r3, [r3, #28] 80077e8: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80077ec: f040 810c bne.w 8007a08 { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 80077f0: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 80077f4: 2200 movs r2, #0 80077f6: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 80077fa: f8c7 20ec str.w r2, [r7, #236] @ 0xec 80077fe: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8 8007802: 4622 mov r2, r4 8007804: 462b mov r3, r5 8007806: 1891 adds r1, r2, r2 8007808: 65b9 str r1, [r7, #88] @ 0x58 800780a: 415b adcs r3, r3 800780c: 65fb str r3, [r7, #92] @ 0x5c 800780e: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8007812: 4621 mov r1, r4 8007814: eb12 0801 adds.w r8, r2, r1 8007818: 4629 mov r1, r5 800781a: eb43 0901 adc.w r9, r3, r1 800781e: f04f 0200 mov.w r2, #0 8007822: f04f 0300 mov.w r3, #0 8007826: ea4f 03c9 mov.w r3, r9, lsl #3 800782a: ea43 7358 orr.w r3, r3, r8, lsr #29 800782e: ea4f 02c8 mov.w r2, r8, lsl #3 8007832: 4690 mov r8, r2 8007834: 4699 mov r9, r3 8007836: 4623 mov r3, r4 8007838: eb18 0303 adds.w r3, r8, r3 800783c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 8007840: 462b mov r3, r5 8007842: eb49 0303 adc.w r3, r9, r3 8007846: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800784a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800784e: 685b ldr r3, [r3, #4] 8007850: 2200 movs r2, #0 8007852: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 8007856: f8c7 20dc str.w r2, [r7, #220] @ 0xdc 800785a: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 800785e: 460b mov r3, r1 8007860: 18db adds r3, r3, r3 8007862: 653b str r3, [r7, #80] @ 0x50 8007864: 4613 mov r3, r2 8007866: eb42 0303 adc.w r3, r2, r3 800786a: 657b str r3, [r7, #84] @ 0x54 800786c: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50 8007870: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0 8007874: f7f8 fcc6 bl 8000204 <__aeabi_uldivmod> 8007878: 4602 mov r2, r0 800787a: 460b mov r3, r1 800787c: 4b61 ldr r3, [pc, #388] @ (8007a04 ) 800787e: fba3 2302 umull r2, r3, r3, r2 8007882: 095b lsrs r3, r3, #5 8007884: 011c lsls r4, r3, #4 8007886: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 800788a: 2200 movs r2, #0 800788c: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8007890: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4 8007894: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0 8007898: 4642 mov r2, r8 800789a: 464b mov r3, r9 800789c: 1891 adds r1, r2, r2 800789e: 64b9 str r1, [r7, #72] @ 0x48 80078a0: 415b adcs r3, r3 80078a2: 64fb str r3, [r7, #76] @ 0x4c 80078a4: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 80078a8: 4641 mov r1, r8 80078aa: eb12 0a01 adds.w sl, r2, r1 80078ae: 4649 mov r1, r9 80078b0: eb43 0b01 adc.w fp, r3, r1 80078b4: f04f 0200 mov.w r2, #0 80078b8: f04f 0300 mov.w r3, #0 80078bc: ea4f 03cb mov.w r3, fp, lsl #3 80078c0: ea43 735a orr.w r3, r3, sl, lsr #29 80078c4: ea4f 02ca mov.w r2, sl, lsl #3 80078c8: 4692 mov sl, r2 80078ca: 469b mov fp, r3 80078cc: 4643 mov r3, r8 80078ce: eb1a 0303 adds.w r3, sl, r3 80078d2: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 80078d6: 464b mov r3, r9 80078d8: eb4b 0303 adc.w r3, fp, r3 80078dc: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 80078e0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80078e4: 685b ldr r3, [r3, #4] 80078e6: 2200 movs r2, #0 80078e8: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 80078ec: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4 80078f0: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 80078f4: 460b mov r3, r1 80078f6: 18db adds r3, r3, r3 80078f8: 643b str r3, [r7, #64] @ 0x40 80078fa: 4613 mov r3, r2 80078fc: eb42 0303 adc.w r3, r2, r3 8007900: 647b str r3, [r7, #68] @ 0x44 8007902: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40 8007906: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8 800790a: f7f8 fc7b bl 8000204 <__aeabi_uldivmod> 800790e: 4602 mov r2, r0 8007910: 460b mov r3, r1 8007912: 4611 mov r1, r2 8007914: 4b3b ldr r3, [pc, #236] @ (8007a04 ) 8007916: fba3 2301 umull r2, r3, r3, r1 800791a: 095b lsrs r3, r3, #5 800791c: 2264 movs r2, #100 @ 0x64 800791e: fb02 f303 mul.w r3, r2, r3 8007922: 1acb subs r3, r1, r3 8007924: 00db lsls r3, r3, #3 8007926: f103 0232 add.w r2, r3, #50 @ 0x32 800792a: 4b36 ldr r3, [pc, #216] @ (8007a04 ) 800792c: fba3 2302 umull r2, r3, r3, r2 8007930: 095b lsrs r3, r3, #5 8007932: 005b lsls r3, r3, #1 8007934: f403 73f8 and.w r3, r3, #496 @ 0x1f0 8007938: 441c add r4, r3 800793a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 800793e: 2200 movs r2, #0 8007940: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8007944: f8c7 20bc str.w r2, [r7, #188] @ 0xbc 8007948: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8 800794c: 4642 mov r2, r8 800794e: 464b mov r3, r9 8007950: 1891 adds r1, r2, r2 8007952: 63b9 str r1, [r7, #56] @ 0x38 8007954: 415b adcs r3, r3 8007956: 63fb str r3, [r7, #60] @ 0x3c 8007958: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38 800795c: 4641 mov r1, r8 800795e: 1851 adds r1, r2, r1 8007960: 6339 str r1, [r7, #48] @ 0x30 8007962: 4649 mov r1, r9 8007964: 414b adcs r3, r1 8007966: 637b str r3, [r7, #52] @ 0x34 8007968: f04f 0200 mov.w r2, #0 800796c: f04f 0300 mov.w r3, #0 8007970: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30 8007974: 4659 mov r1, fp 8007976: 00cb lsls r3, r1, #3 8007978: 4651 mov r1, sl 800797a: ea43 7351 orr.w r3, r3, r1, lsr #29 800797e: 4651 mov r1, sl 8007980: 00ca lsls r2, r1, #3 8007982: 4610 mov r0, r2 8007984: 4619 mov r1, r3 8007986: 4603 mov r3, r0 8007988: 4642 mov r2, r8 800798a: 189b adds r3, r3, r2 800798c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8007990: 464b mov r3, r9 8007992: 460a mov r2, r1 8007994: eb42 0303 adc.w r3, r2, r3 8007998: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800799c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80079a0: 685b ldr r3, [r3, #4] 80079a2: 2200 movs r2, #0 80079a4: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 80079a8: f8c7 20ac str.w r2, [r7, #172] @ 0xac 80079ac: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 80079b0: 460b mov r3, r1 80079b2: 18db adds r3, r3, r3 80079b4: 62bb str r3, [r7, #40] @ 0x28 80079b6: 4613 mov r3, r2 80079b8: eb42 0303 adc.w r3, r2, r3 80079bc: 62fb str r3, [r7, #44] @ 0x2c 80079be: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 80079c2: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0 80079c6: f7f8 fc1d bl 8000204 <__aeabi_uldivmod> 80079ca: 4602 mov r2, r0 80079cc: 460b mov r3, r1 80079ce: 4b0d ldr r3, [pc, #52] @ (8007a04 ) 80079d0: fba3 1302 umull r1, r3, r3, r2 80079d4: 095b lsrs r3, r3, #5 80079d6: 2164 movs r1, #100 @ 0x64 80079d8: fb01 f303 mul.w r3, r1, r3 80079dc: 1ad3 subs r3, r2, r3 80079de: 00db lsls r3, r3, #3 80079e0: 3332 adds r3, #50 @ 0x32 80079e2: 4a08 ldr r2, [pc, #32] @ (8007a04 ) 80079e4: fba2 2303 umull r2, r3, r2, r3 80079e8: 095b lsrs r3, r3, #5 80079ea: f003 0207 and.w r2, r3, #7 80079ee: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80079f2: 681b ldr r3, [r3, #0] 80079f4: 4422 add r2, r4 80079f6: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } 80079f8: e106 b.n 8007c08 80079fa: bf00 nop 80079fc: 40011000 .word 0x40011000 8007a00: 40011400 .word 0x40011400 8007a04: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8007a08: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8007a0c: 2200 movs r2, #0 8007a0e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 8007a12: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4 8007a16: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0 8007a1a: 4642 mov r2, r8 8007a1c: 464b mov r3, r9 8007a1e: 1891 adds r1, r2, r2 8007a20: 6239 str r1, [r7, #32] 8007a22: 415b adcs r3, r3 8007a24: 627b str r3, [r7, #36] @ 0x24 8007a26: e9d7 2308 ldrd r2, r3, [r7, #32] 8007a2a: 4641 mov r1, r8 8007a2c: 1854 adds r4, r2, r1 8007a2e: 4649 mov r1, r9 8007a30: eb43 0501 adc.w r5, r3, r1 8007a34: f04f 0200 mov.w r2, #0 8007a38: f04f 0300 mov.w r3, #0 8007a3c: 00eb lsls r3, r5, #3 8007a3e: ea43 7354 orr.w r3, r3, r4, lsr #29 8007a42: 00e2 lsls r2, r4, #3 8007a44: 4614 mov r4, r2 8007a46: 461d mov r5, r3 8007a48: 4643 mov r3, r8 8007a4a: 18e3 adds r3, r4, r3 8007a4c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8007a50: 464b mov r3, r9 8007a52: eb45 0303 adc.w r3, r5, r3 8007a56: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8007a5a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007a5e: 685b ldr r3, [r3, #4] 8007a60: 2200 movs r2, #0 8007a62: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8007a66: f8c7 2094 str.w r2, [r7, #148] @ 0x94 8007a6a: f04f 0200 mov.w r2, #0 8007a6e: f04f 0300 mov.w r3, #0 8007a72: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8007a76: 4629 mov r1, r5 8007a78: 008b lsls r3, r1, #2 8007a7a: 4621 mov r1, r4 8007a7c: ea43 7391 orr.w r3, r3, r1, lsr #30 8007a80: 4621 mov r1, r4 8007a82: 008a lsls r2, r1, #2 8007a84: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98 8007a88: f7f8 fbbc bl 8000204 <__aeabi_uldivmod> 8007a8c: 4602 mov r2, r0 8007a8e: 460b mov r3, r1 8007a90: 4b60 ldr r3, [pc, #384] @ (8007c14 ) 8007a92: fba3 2302 umull r2, r3, r3, r2 8007a96: 095b lsrs r3, r3, #5 8007a98: 011c lsls r4, r3, #4 8007a9a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8007a9e: 2200 movs r2, #0 8007aa0: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8007aa4: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8007aa8: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88 8007aac: 4642 mov r2, r8 8007aae: 464b mov r3, r9 8007ab0: 1891 adds r1, r2, r2 8007ab2: 61b9 str r1, [r7, #24] 8007ab4: 415b adcs r3, r3 8007ab6: 61fb str r3, [r7, #28] 8007ab8: e9d7 2306 ldrd r2, r3, [r7, #24] 8007abc: 4641 mov r1, r8 8007abe: 1851 adds r1, r2, r1 8007ac0: 6139 str r1, [r7, #16] 8007ac2: 4649 mov r1, r9 8007ac4: 414b adcs r3, r1 8007ac6: 617b str r3, [r7, #20] 8007ac8: f04f 0200 mov.w r2, #0 8007acc: f04f 0300 mov.w r3, #0 8007ad0: e9d7 ab04 ldrd sl, fp, [r7, #16] 8007ad4: 4659 mov r1, fp 8007ad6: 00cb lsls r3, r1, #3 8007ad8: 4651 mov r1, sl 8007ada: ea43 7351 orr.w r3, r3, r1, lsr #29 8007ade: 4651 mov r1, sl 8007ae0: 00ca lsls r2, r1, #3 8007ae2: 4610 mov r0, r2 8007ae4: 4619 mov r1, r3 8007ae6: 4603 mov r3, r0 8007ae8: 4642 mov r2, r8 8007aea: 189b adds r3, r3, r2 8007aec: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8007af0: 464b mov r3, r9 8007af2: 460a mov r2, r1 8007af4: eb42 0303 adc.w r3, r2, r3 8007af8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8007afc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007b00: 685b ldr r3, [r3, #4] 8007b02: 2200 movs r2, #0 8007b04: 67bb str r3, [r7, #120] @ 0x78 8007b06: 67fa str r2, [r7, #124] @ 0x7c 8007b08: f04f 0200 mov.w r2, #0 8007b0c: f04f 0300 mov.w r3, #0 8007b10: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78 8007b14: 4649 mov r1, r9 8007b16: 008b lsls r3, r1, #2 8007b18: 4641 mov r1, r8 8007b1a: ea43 7391 orr.w r3, r3, r1, lsr #30 8007b1e: 4641 mov r1, r8 8007b20: 008a lsls r2, r1, #2 8007b22: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80 8007b26: f7f8 fb6d bl 8000204 <__aeabi_uldivmod> 8007b2a: 4602 mov r2, r0 8007b2c: 460b mov r3, r1 8007b2e: 4611 mov r1, r2 8007b30: 4b38 ldr r3, [pc, #224] @ (8007c14 ) 8007b32: fba3 2301 umull r2, r3, r3, r1 8007b36: 095b lsrs r3, r3, #5 8007b38: 2264 movs r2, #100 @ 0x64 8007b3a: fb02 f303 mul.w r3, r2, r3 8007b3e: 1acb subs r3, r1, r3 8007b40: 011b lsls r3, r3, #4 8007b42: 3332 adds r3, #50 @ 0x32 8007b44: 4a33 ldr r2, [pc, #204] @ (8007c14 ) 8007b46: fba2 2303 umull r2, r3, r2, r3 8007b4a: 095b lsrs r3, r3, #5 8007b4c: f003 03f0 and.w r3, r3, #240 @ 0xf0 8007b50: 441c add r4, r3 8007b52: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8007b56: 2200 movs r2, #0 8007b58: 673b str r3, [r7, #112] @ 0x70 8007b5a: 677a str r2, [r7, #116] @ 0x74 8007b5c: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70 8007b60: 4642 mov r2, r8 8007b62: 464b mov r3, r9 8007b64: 1891 adds r1, r2, r2 8007b66: 60b9 str r1, [r7, #8] 8007b68: 415b adcs r3, r3 8007b6a: 60fb str r3, [r7, #12] 8007b6c: e9d7 2302 ldrd r2, r3, [r7, #8] 8007b70: 4641 mov r1, r8 8007b72: 1851 adds r1, r2, r1 8007b74: 6039 str r1, [r7, #0] 8007b76: 4649 mov r1, r9 8007b78: 414b adcs r3, r1 8007b7a: 607b str r3, [r7, #4] 8007b7c: f04f 0200 mov.w r2, #0 8007b80: f04f 0300 mov.w r3, #0 8007b84: e9d7 ab00 ldrd sl, fp, [r7] 8007b88: 4659 mov r1, fp 8007b8a: 00cb lsls r3, r1, #3 8007b8c: 4651 mov r1, sl 8007b8e: ea43 7351 orr.w r3, r3, r1, lsr #29 8007b92: 4651 mov r1, sl 8007b94: 00ca lsls r2, r1, #3 8007b96: 4610 mov r0, r2 8007b98: 4619 mov r1, r3 8007b9a: 4603 mov r3, r0 8007b9c: 4642 mov r2, r8 8007b9e: 189b adds r3, r3, r2 8007ba0: 66bb str r3, [r7, #104] @ 0x68 8007ba2: 464b mov r3, r9 8007ba4: 460a mov r2, r1 8007ba6: eb42 0303 adc.w r3, r2, r3 8007baa: 66fb str r3, [r7, #108] @ 0x6c 8007bac: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007bb0: 685b ldr r3, [r3, #4] 8007bb2: 2200 movs r2, #0 8007bb4: 663b str r3, [r7, #96] @ 0x60 8007bb6: 667a str r2, [r7, #100] @ 0x64 8007bb8: f04f 0200 mov.w r2, #0 8007bbc: f04f 0300 mov.w r3, #0 8007bc0: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60 8007bc4: 4649 mov r1, r9 8007bc6: 008b lsls r3, r1, #2 8007bc8: 4641 mov r1, r8 8007bca: ea43 7391 orr.w r3, r3, r1, lsr #30 8007bce: 4641 mov r1, r8 8007bd0: 008a lsls r2, r1, #2 8007bd2: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68 8007bd6: f7f8 fb15 bl 8000204 <__aeabi_uldivmod> 8007bda: 4602 mov r2, r0 8007bdc: 460b mov r3, r1 8007bde: 4b0d ldr r3, [pc, #52] @ (8007c14 ) 8007be0: fba3 1302 umull r1, r3, r3, r2 8007be4: 095b lsrs r3, r3, #5 8007be6: 2164 movs r1, #100 @ 0x64 8007be8: fb01 f303 mul.w r3, r1, r3 8007bec: 1ad3 subs r3, r2, r3 8007bee: 011b lsls r3, r3, #4 8007bf0: 3332 adds r3, #50 @ 0x32 8007bf2: 4a08 ldr r2, [pc, #32] @ (8007c14 ) 8007bf4: fba2 2303 umull r2, r3, r2, r3 8007bf8: 095b lsrs r3, r3, #5 8007bfa: f003 020f and.w r2, r3, #15 8007bfe: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007c02: 681b ldr r3, [r3, #0] 8007c04: 4422 add r2, r4 8007c06: 609a str r2, [r3, #8] } 8007c08: bf00 nop 8007c0a: f507 7780 add.w r7, r7, #256 @ 0x100 8007c0e: 46bd mov sp, r7 8007c10: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8007c14: 51eb851f .word 0x51eb851f 08007c18 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8007c18: b084 sub sp, #16 8007c1a: b580 push {r7, lr} 8007c1c: b084 sub sp, #16 8007c1e: af00 add r7, sp, #0 8007c20: 6078 str r0, [r7, #4] 8007c22: f107 001c add.w r0, r7, #28 8007c26: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8007c2a: f897 3021 ldrb.w r3, [r7, #33] @ 0x21 8007c2e: 2b01 cmp r3, #1 8007c30: d123 bne.n 8007c7a { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8007c32: 687b ldr r3, [r7, #4] 8007c34: 6b9b ldr r3, [r3, #56] @ 0x38 8007c36: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8007c3a: 687b ldr r3, [r7, #4] 8007c3c: 639a str r2, [r3, #56] @ 0x38 /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); 8007c3e: 687b ldr r3, [r7, #4] 8007c40: 68db ldr r3, [r3, #12] 8007c42: f423 0384 bic.w r3, r3, #4325376 @ 0x420000 8007c46: f023 0340 bic.w r3, r3, #64 @ 0x40 8007c4a: 687a ldr r2, [r7, #4] 8007c4c: 60d3 str r3, [r2, #12] /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); 8007c4e: 687b ldr r3, [r7, #4] 8007c50: 68db ldr r3, [r3, #12] 8007c52: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 8007c56: 687b ldr r3, [r7, #4] 8007c58: 60da str r2, [r3, #12] if (cfg.use_external_vbus == 1U) 8007c5a: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8007c5e: 2b01 cmp r3, #1 8007c60: d105 bne.n 8007c6e { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; 8007c62: 687b ldr r3, [r7, #4] 8007c64: 68db ldr r3, [r3, #12] 8007c66: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 8007c6a: 687b ldr r3, [r7, #4] 8007c6c: 60da str r2, [r3, #12] } /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8007c6e: 6878 ldr r0, [r7, #4] 8007c70: f001 fae2 bl 8009238 8007c74: 4603 mov r3, r0 8007c76: 73fb strb r3, [r7, #15] 8007c78: e01b b.n 8007cb2 } else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 8007c7a: 687b ldr r3, [r7, #4] 8007c7c: 68db ldr r3, [r3, #12] 8007c7e: f043 0240 orr.w r2, r3, #64 @ 0x40 8007c82: 687b ldr r3, [r7, #4] 8007c84: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8007c86: 6878 ldr r0, [r7, #4] 8007c88: f001 fad6 bl 8009238 8007c8c: 4603 mov r3, r0 8007c8e: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 8007c90: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 8007c94: 2b00 cmp r3, #0 8007c96: d106 bne.n 8007ca6 { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8007c98: 687b ldr r3, [r7, #4] 8007c9a: 6b9b ldr r3, [r3, #56] @ 0x38 8007c9c: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8007ca0: 687b ldr r3, [r7, #4] 8007ca2: 639a str r2, [r3, #56] @ 0x38 8007ca4: e005 b.n 8007cb2 } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8007ca6: 687b ldr r3, [r7, #4] 8007ca8: 6b9b ldr r3, [r3, #56] @ 0x38 8007caa: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8007cae: 687b ldr r3, [r7, #4] 8007cb0: 639a str r2, [r3, #56] @ 0x38 } } if (cfg.dma_enable == 1U) 8007cb2: 7fbb ldrb r3, [r7, #30] 8007cb4: 2b01 cmp r3, #1 8007cb6: d10b bne.n 8007cd0 { USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; 8007cb8: 687b ldr r3, [r7, #4] 8007cba: 689b ldr r3, [r3, #8] 8007cbc: f043 0206 orr.w r2, r3, #6 8007cc0: 687b ldr r3, [r7, #4] 8007cc2: 609a str r2, [r3, #8] USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; 8007cc4: 687b ldr r3, [r7, #4] 8007cc6: 689b ldr r3, [r3, #8] 8007cc8: f043 0220 orr.w r2, r3, #32 8007ccc: 687b ldr r3, [r7, #4] 8007cce: 609a str r2, [r3, #8] } return ret; 8007cd0: 7bfb ldrb r3, [r7, #15] } 8007cd2: 4618 mov r0, r3 8007cd4: 3710 adds r7, #16 8007cd6: 46bd mov sp, r7 8007cd8: e8bd 4080 ldmia.w sp!, {r7, lr} 8007cdc: b004 add sp, #16 8007cde: 4770 bx lr 08007ce0 : * @param hclk: AHB clock frequency * @retval USB turnaround time In PHY Clocks number */ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed) { 8007ce0: b480 push {r7} 8007ce2: b087 sub sp, #28 8007ce4: af00 add r7, sp, #0 8007ce6: 60f8 str r0, [r7, #12] 8007ce8: 60b9 str r1, [r7, #8] 8007cea: 4613 mov r3, r2 8007cec: 71fb strb r3, [r7, #7] /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ if (speed == USBD_FS_SPEED) 8007cee: 79fb ldrb r3, [r7, #7] 8007cf0: 2b02 cmp r3, #2 8007cf2: d165 bne.n 8007dc0 { if ((hclk >= 14200000U) && (hclk < 15000000U)) 8007cf4: 68bb ldr r3, [r7, #8] 8007cf6: 4a41 ldr r2, [pc, #260] @ (8007dfc ) 8007cf8: 4293 cmp r3, r2 8007cfa: d906 bls.n 8007d0a 8007cfc: 68bb ldr r3, [r7, #8] 8007cfe: 4a40 ldr r2, [pc, #256] @ (8007e00 ) 8007d00: 4293 cmp r3, r2 8007d02: d202 bcs.n 8007d0a { /* hclk Clock Range between 14.2-15 MHz */ UsbTrd = 0xFU; 8007d04: 230f movs r3, #15 8007d06: 617b str r3, [r7, #20] 8007d08: e062 b.n 8007dd0 } else if ((hclk >= 15000000U) && (hclk < 16000000U)) 8007d0a: 68bb ldr r3, [r7, #8] 8007d0c: 4a3c ldr r2, [pc, #240] @ (8007e00 ) 8007d0e: 4293 cmp r3, r2 8007d10: d306 bcc.n 8007d20 8007d12: 68bb ldr r3, [r7, #8] 8007d14: 4a3b ldr r2, [pc, #236] @ (8007e04 ) 8007d16: 4293 cmp r3, r2 8007d18: d202 bcs.n 8007d20 { /* hclk Clock Range between 15-16 MHz */ UsbTrd = 0xEU; 8007d1a: 230e movs r3, #14 8007d1c: 617b str r3, [r7, #20] 8007d1e: e057 b.n 8007dd0 } else if ((hclk >= 16000000U) && (hclk < 17200000U)) 8007d20: 68bb ldr r3, [r7, #8] 8007d22: 4a38 ldr r2, [pc, #224] @ (8007e04 ) 8007d24: 4293 cmp r3, r2 8007d26: d306 bcc.n 8007d36 8007d28: 68bb ldr r3, [r7, #8] 8007d2a: 4a37 ldr r2, [pc, #220] @ (8007e08 ) 8007d2c: 4293 cmp r3, r2 8007d2e: d202 bcs.n 8007d36 { /* hclk Clock Range between 16-17.2 MHz */ UsbTrd = 0xDU; 8007d30: 230d movs r3, #13 8007d32: 617b str r3, [r7, #20] 8007d34: e04c b.n 8007dd0 } else if ((hclk >= 17200000U) && (hclk < 18500000U)) 8007d36: 68bb ldr r3, [r7, #8] 8007d38: 4a33 ldr r2, [pc, #204] @ (8007e08 ) 8007d3a: 4293 cmp r3, r2 8007d3c: d306 bcc.n 8007d4c 8007d3e: 68bb ldr r3, [r7, #8] 8007d40: 4a32 ldr r2, [pc, #200] @ (8007e0c ) 8007d42: 4293 cmp r3, r2 8007d44: d802 bhi.n 8007d4c { /* hclk Clock Range between 17.2-18.5 MHz */ UsbTrd = 0xCU; 8007d46: 230c movs r3, #12 8007d48: 617b str r3, [r7, #20] 8007d4a: e041 b.n 8007dd0 } else if ((hclk >= 18500000U) && (hclk < 20000000U)) 8007d4c: 68bb ldr r3, [r7, #8] 8007d4e: 4a2f ldr r2, [pc, #188] @ (8007e0c ) 8007d50: 4293 cmp r3, r2 8007d52: d906 bls.n 8007d62 8007d54: 68bb ldr r3, [r7, #8] 8007d56: 4a2e ldr r2, [pc, #184] @ (8007e10 ) 8007d58: 4293 cmp r3, r2 8007d5a: d802 bhi.n 8007d62 { /* hclk Clock Range between 18.5-20 MHz */ UsbTrd = 0xBU; 8007d5c: 230b movs r3, #11 8007d5e: 617b str r3, [r7, #20] 8007d60: e036 b.n 8007dd0 } else if ((hclk >= 20000000U) && (hclk < 21800000U)) 8007d62: 68bb ldr r3, [r7, #8] 8007d64: 4a2a ldr r2, [pc, #168] @ (8007e10 ) 8007d66: 4293 cmp r3, r2 8007d68: d906 bls.n 8007d78 8007d6a: 68bb ldr r3, [r7, #8] 8007d6c: 4a29 ldr r2, [pc, #164] @ (8007e14 ) 8007d6e: 4293 cmp r3, r2 8007d70: d802 bhi.n 8007d78 { /* hclk Clock Range between 20-21.8 MHz */ UsbTrd = 0xAU; 8007d72: 230a movs r3, #10 8007d74: 617b str r3, [r7, #20] 8007d76: e02b b.n 8007dd0 } else if ((hclk >= 21800000U) && (hclk < 24000000U)) 8007d78: 68bb ldr r3, [r7, #8] 8007d7a: 4a26 ldr r2, [pc, #152] @ (8007e14 ) 8007d7c: 4293 cmp r3, r2 8007d7e: d906 bls.n 8007d8e 8007d80: 68bb ldr r3, [r7, #8] 8007d82: 4a25 ldr r2, [pc, #148] @ (8007e18 ) 8007d84: 4293 cmp r3, r2 8007d86: d202 bcs.n 8007d8e { /* hclk Clock Range between 21.8-24 MHz */ UsbTrd = 0x9U; 8007d88: 2309 movs r3, #9 8007d8a: 617b str r3, [r7, #20] 8007d8c: e020 b.n 8007dd0 } else if ((hclk >= 24000000U) && (hclk < 27700000U)) 8007d8e: 68bb ldr r3, [r7, #8] 8007d90: 4a21 ldr r2, [pc, #132] @ (8007e18 ) 8007d92: 4293 cmp r3, r2 8007d94: d306 bcc.n 8007da4 8007d96: 68bb ldr r3, [r7, #8] 8007d98: 4a20 ldr r2, [pc, #128] @ (8007e1c ) 8007d9a: 4293 cmp r3, r2 8007d9c: d802 bhi.n 8007da4 { /* hclk Clock Range between 24-27.7 MHz */ UsbTrd = 0x8U; 8007d9e: 2308 movs r3, #8 8007da0: 617b str r3, [r7, #20] 8007da2: e015 b.n 8007dd0 } else if ((hclk >= 27700000U) && (hclk < 32000000U)) 8007da4: 68bb ldr r3, [r7, #8] 8007da6: 4a1d ldr r2, [pc, #116] @ (8007e1c ) 8007da8: 4293 cmp r3, r2 8007daa: d906 bls.n 8007dba 8007dac: 68bb ldr r3, [r7, #8] 8007dae: 4a1c ldr r2, [pc, #112] @ (8007e20 ) 8007db0: 4293 cmp r3, r2 8007db2: d202 bcs.n 8007dba { /* hclk Clock Range between 27.7-32 MHz */ UsbTrd = 0x7U; 8007db4: 2307 movs r3, #7 8007db6: 617b str r3, [r7, #20] 8007db8: e00a b.n 8007dd0 } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ UsbTrd = 0x6U; 8007dba: 2306 movs r3, #6 8007dbc: 617b str r3, [r7, #20] 8007dbe: e007 b.n 8007dd0 } } else if (speed == USBD_HS_SPEED) 8007dc0: 79fb ldrb r3, [r7, #7] 8007dc2: 2b00 cmp r3, #0 8007dc4: d102 bne.n 8007dcc { UsbTrd = USBD_HS_TRDT_VALUE; 8007dc6: 2309 movs r3, #9 8007dc8: 617b str r3, [r7, #20] 8007dca: e001 b.n 8007dd0 } else { UsbTrd = USBD_DEFAULT_TRDT_VALUE; 8007dcc: 2309 movs r3, #9 8007dce: 617b str r3, [r7, #20] } USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; 8007dd0: 68fb ldr r3, [r7, #12] 8007dd2: 68db ldr r3, [r3, #12] 8007dd4: f423 5270 bic.w r2, r3, #15360 @ 0x3c00 8007dd8: 68fb ldr r3, [r7, #12] 8007dda: 60da str r2, [r3, #12] USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); 8007ddc: 68fb ldr r3, [r7, #12] 8007dde: 68da ldr r2, [r3, #12] 8007de0: 697b ldr r3, [r7, #20] 8007de2: 029b lsls r3, r3, #10 8007de4: f403 5370 and.w r3, r3, #15360 @ 0x3c00 8007de8: 431a orrs r2, r3 8007dea: 68fb ldr r3, [r7, #12] 8007dec: 60da str r2, [r3, #12] return HAL_OK; 8007dee: 2300 movs r3, #0 } 8007df0: 4618 mov r0, r3 8007df2: 371c adds r7, #28 8007df4: 46bd mov sp, r7 8007df6: f85d 7b04 ldr.w r7, [sp], #4 8007dfa: 4770 bx lr 8007dfc: 00d8acbf .word 0x00d8acbf 8007e00: 00e4e1c0 .word 0x00e4e1c0 8007e04: 00f42400 .word 0x00f42400 8007e08: 01067380 .word 0x01067380 8007e0c: 011a499f .word 0x011a499f 8007e10: 01312cff .word 0x01312cff 8007e14: 014ca43f .word 0x014ca43f 8007e18: 016e3600 .word 0x016e3600 8007e1c: 01a6ab1f .word 0x01a6ab1f 8007e20: 01e84800 .word 0x01e84800 08007e24 : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8007e24: b480 push {r7} 8007e26: b083 sub sp, #12 8007e28: af00 add r7, sp, #0 8007e2a: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 8007e2c: 687b ldr r3, [r7, #4] 8007e2e: 689b ldr r3, [r3, #8] 8007e30: f043 0201 orr.w r2, r3, #1 8007e34: 687b ldr r3, [r7, #4] 8007e36: 609a str r2, [r3, #8] return HAL_OK; 8007e38: 2300 movs r3, #0 } 8007e3a: 4618 mov r0, r3 8007e3c: 370c adds r7, #12 8007e3e: 46bd mov sp, r7 8007e40: f85d 7b04 ldr.w r7, [sp], #4 8007e44: 4770 bx lr 08007e46 : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8007e46: b480 push {r7} 8007e48: b083 sub sp, #12 8007e4a: af00 add r7, sp, #0 8007e4c: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 8007e4e: 687b ldr r3, [r7, #4] 8007e50: 689b ldr r3, [r3, #8] 8007e52: f023 0201 bic.w r2, r3, #1 8007e56: 687b ldr r3, [r7, #4] 8007e58: 609a str r2, [r3, #8] return HAL_OK; 8007e5a: 2300 movs r3, #0 } 8007e5c: 4618 mov r0, r3 8007e5e: 370c adds r7, #12 8007e60: 46bd mov sp, r7 8007e62: f85d 7b04 ldr.w r7, [sp], #4 8007e66: 4770 bx lr 08007e68 : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { 8007e68: b580 push {r7, lr} 8007e6a: b084 sub sp, #16 8007e6c: af00 add r7, sp, #0 8007e6e: 6078 str r0, [r7, #4] 8007e70: 460b mov r3, r1 8007e72: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 8007e74: 2300 movs r3, #0 8007e76: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 8007e78: 687b ldr r3, [r7, #4] 8007e7a: 68db ldr r3, [r3, #12] 8007e7c: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000 8007e80: 687b ldr r3, [r7, #4] 8007e82: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 8007e84: 78fb ldrb r3, [r7, #3] 8007e86: 2b01 cmp r3, #1 8007e88: d115 bne.n 8007eb6 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 8007e8a: 687b ldr r3, [r7, #4] 8007e8c: 68db ldr r3, [r3, #12] 8007e8e: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 8007e92: 687b ldr r3, [r7, #4] 8007e94: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8007e96: 200a movs r0, #10 8007e98: f7fa f820 bl 8001edc ms += 10U; 8007e9c: 68fb ldr r3, [r7, #12] 8007e9e: 330a adds r3, #10 8007ea0: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8007ea2: 6878 ldr r0, [r7, #4] 8007ea4: f001 f939 bl 800911a 8007ea8: 4603 mov r3, r0 8007eaa: 2b01 cmp r3, #1 8007eac: d01e beq.n 8007eec 8007eae: 68fb ldr r3, [r7, #12] 8007eb0: 2bc7 cmp r3, #199 @ 0xc7 8007eb2: d9f0 bls.n 8007e96 8007eb4: e01a b.n 8007eec } else if (mode == USB_DEVICE_MODE) 8007eb6: 78fb ldrb r3, [r7, #3] 8007eb8: 2b00 cmp r3, #0 8007eba: d115 bne.n 8007ee8 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 8007ebc: 687b ldr r3, [r7, #4] 8007ebe: 68db ldr r3, [r3, #12] 8007ec0: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000 8007ec4: 687b ldr r3, [r7, #4] 8007ec6: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8007ec8: 200a movs r0, #10 8007eca: f7fa f807 bl 8001edc ms += 10U; 8007ece: 68fb ldr r3, [r7, #12] 8007ed0: 330a adds r3, #10 8007ed2: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8007ed4: 6878 ldr r0, [r7, #4] 8007ed6: f001 f920 bl 800911a 8007eda: 4603 mov r3, r0 8007edc: 2b00 cmp r3, #0 8007ede: d005 beq.n 8007eec 8007ee0: 68fb ldr r3, [r7, #12] 8007ee2: 2bc7 cmp r3, #199 @ 0xc7 8007ee4: d9f0 bls.n 8007ec8 8007ee6: e001 b.n 8007eec } else { return HAL_ERROR; 8007ee8: 2301 movs r3, #1 8007eea: e005 b.n 8007ef8 } if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) 8007eec: 68fb ldr r3, [r7, #12] 8007eee: 2bc8 cmp r3, #200 @ 0xc8 8007ef0: d101 bne.n 8007ef6 { return HAL_ERROR; 8007ef2: 2301 movs r3, #1 8007ef4: e000 b.n 8007ef8 } return HAL_OK; 8007ef6: 2300 movs r3, #0 } 8007ef8: 4618 mov r0, r3 8007efa: 3710 adds r7, #16 8007efc: 46bd mov sp, r7 8007efe: bd80 pop {r7, pc} 08007f00 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8007f00: b084 sub sp, #16 8007f02: b580 push {r7, lr} 8007f04: b086 sub sp, #24 8007f06: af00 add r7, sp, #0 8007f08: 6078 str r0, [r7, #4] 8007f0a: f107 0024 add.w r0, r7, #36 @ 0x24 8007f0e: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 8007f12: 2300 movs r3, #0 8007f14: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8007f16: 687b ldr r3, [r7, #4] 8007f18: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 8007f1a: 2300 movs r3, #0 8007f1c: 613b str r3, [r7, #16] 8007f1e: e009 b.n 8007f34 { USBx->DIEPTXF[i] = 0U; 8007f20: 687a ldr r2, [r7, #4] 8007f22: 693b ldr r3, [r7, #16] 8007f24: 3340 adds r3, #64 @ 0x40 8007f26: 009b lsls r3, r3, #2 8007f28: 4413 add r3, r2 8007f2a: 2200 movs r2, #0 8007f2c: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 8007f2e: 693b ldr r3, [r7, #16] 8007f30: 3301 adds r3, #1 8007f32: 613b str r3, [r7, #16] 8007f34: 693b ldr r3, [r7, #16] 8007f36: 2b0e cmp r3, #14 8007f38: d9f2 bls.n 8007f20 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 8007f3a: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8007f3e: 2b00 cmp r3, #0 8007f40: d11c bne.n 8007f7c { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8007f42: 68fb ldr r3, [r7, #12] 8007f44: f503 6300 add.w r3, r3, #2048 @ 0x800 8007f48: 685b ldr r3, [r3, #4] 8007f4a: 68fa ldr r2, [r7, #12] 8007f4c: f502 6200 add.w r2, r2, #2048 @ 0x800 8007f50: f043 0302 orr.w r3, r3, #2 8007f54: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 8007f56: 687b ldr r3, [r7, #4] 8007f58: 6b9b ldr r3, [r3, #56] @ 0x38 8007f5a: f423 1200 bic.w r2, r3, #2097152 @ 0x200000 8007f5e: 687b ldr r3, [r7, #4] 8007f60: 639a str r2, [r3, #56] @ 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 8007f62: 687b ldr r3, [r7, #4] 8007f64: 681b ldr r3, [r3, #0] 8007f66: f043 0240 orr.w r2, r3, #64 @ 0x40 8007f6a: 687b ldr r3, [r7, #4] 8007f6c: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 8007f6e: 687b ldr r3, [r7, #4] 8007f70: 681b ldr r3, [r3, #0] 8007f72: f043 0280 orr.w r2, r3, #128 @ 0x80 8007f76: 687b ldr r3, [r7, #4] 8007f78: 601a str r2, [r3, #0] 8007f7a: e005 b.n 8007f88 } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 8007f7c: 687b ldr r3, [r7, #4] 8007f7e: 6b9b ldr r3, [r3, #56] @ 0x38 8007f80: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 8007f84: 687b ldr r3, [r7, #4] 8007f86: 639a str r2, [r3, #56] @ 0x38 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 8007f88: 68fb ldr r3, [r7, #12] 8007f8a: f503 6360 add.w r3, r3, #3584 @ 0xe00 8007f8e: 461a mov r2, r3 8007f90: 2300 movs r3, #0 8007f92: 6013 str r3, [r2, #0] if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8007f94: f897 3029 ldrb.w r3, [r7, #41] @ 0x29 8007f98: 2b01 cmp r3, #1 8007f9a: d10d bne.n 8007fb8 { if (cfg.speed == USBD_HS_SPEED) 8007f9c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8007fa0: 2b00 cmp r3, #0 8007fa2: d104 bne.n 8007fae { /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); 8007fa4: 2100 movs r1, #0 8007fa6: 6878 ldr r0, [r7, #4] 8007fa8: f000 f968 bl 800827c 8007fac: e008 b.n 8007fc0 } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); 8007fae: 2101 movs r1, #1 8007fb0: 6878 ldr r0, [r7, #4] 8007fb2: f000 f963 bl 800827c 8007fb6: e003 b.n 8007fc0 } } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 8007fb8: 2103 movs r1, #3 8007fba: 6878 ldr r0, [r7, #4] 8007fbc: f000 f95e bl 800827c } /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 8007fc0: 2110 movs r1, #16 8007fc2: 6878 ldr r0, [r7, #4] 8007fc4: f000 f8fa bl 80081bc 8007fc8: 4603 mov r3, r0 8007fca: 2b00 cmp r3, #0 8007fcc: d001 beq.n 8007fd2 { ret = HAL_ERROR; 8007fce: 2301 movs r3, #1 8007fd0: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 8007fd2: 6878 ldr r0, [r7, #4] 8007fd4: f000 f924 bl 8008220 8007fd8: 4603 mov r3, r0 8007fda: 2b00 cmp r3, #0 8007fdc: d001 beq.n 8007fe2 { ret = HAL_ERROR; 8007fde: 2301 movs r3, #1 8007fe0: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 8007fe2: 68fb ldr r3, [r7, #12] 8007fe4: f503 6300 add.w r3, r3, #2048 @ 0x800 8007fe8: 461a mov r2, r3 8007fea: 2300 movs r3, #0 8007fec: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 8007fee: 68fb ldr r3, [r7, #12] 8007ff0: f503 6300 add.w r3, r3, #2048 @ 0x800 8007ff4: 461a mov r2, r3 8007ff6: 2300 movs r3, #0 8007ff8: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 8007ffa: 68fb ldr r3, [r7, #12] 8007ffc: f503 6300 add.w r3, r3, #2048 @ 0x800 8008000: 461a mov r2, r3 8008002: 2300 movs r3, #0 8008004: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 8008006: 2300 movs r3, #0 8008008: 613b str r3, [r7, #16] 800800a: e043 b.n 8008094 { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 800800c: 693b ldr r3, [r7, #16] 800800e: 015a lsls r2, r3, #5 8008010: 68fb ldr r3, [r7, #12] 8008012: 4413 add r3, r2 8008014: f503 6310 add.w r3, r3, #2304 @ 0x900 8008018: 681b ldr r3, [r3, #0] 800801a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800801e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008022: d118 bne.n 8008056 { if (i == 0U) 8008024: 693b ldr r3, [r7, #16] 8008026: 2b00 cmp r3, #0 8008028: d10a bne.n 8008040 { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 800802a: 693b ldr r3, [r7, #16] 800802c: 015a lsls r2, r3, #5 800802e: 68fb ldr r3, [r7, #12] 8008030: 4413 add r3, r2 8008032: f503 6310 add.w r3, r3, #2304 @ 0x900 8008036: 461a mov r2, r3 8008038: f04f 6300 mov.w r3, #134217728 @ 0x8000000 800803c: 6013 str r3, [r2, #0] 800803e: e013 b.n 8008068 } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 8008040: 693b ldr r3, [r7, #16] 8008042: 015a lsls r2, r3, #5 8008044: 68fb ldr r3, [r7, #12] 8008046: 4413 add r3, r2 8008048: f503 6310 add.w r3, r3, #2304 @ 0x900 800804c: 461a mov r2, r3 800804e: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 8008052: 6013 str r3, [r2, #0] 8008054: e008 b.n 8008068 } } else { USBx_INEP(i)->DIEPCTL = 0U; 8008056: 693b ldr r3, [r7, #16] 8008058: 015a lsls r2, r3, #5 800805a: 68fb ldr r3, [r7, #12] 800805c: 4413 add r3, r2 800805e: f503 6310 add.w r3, r3, #2304 @ 0x900 8008062: 461a mov r2, r3 8008064: 2300 movs r3, #0 8008066: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 8008068: 693b ldr r3, [r7, #16] 800806a: 015a lsls r2, r3, #5 800806c: 68fb ldr r3, [r7, #12] 800806e: 4413 add r3, r2 8008070: f503 6310 add.w r3, r3, #2304 @ 0x900 8008074: 461a mov r2, r3 8008076: 2300 movs r3, #0 8008078: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 800807a: 693b ldr r3, [r7, #16] 800807c: 015a lsls r2, r3, #5 800807e: 68fb ldr r3, [r7, #12] 8008080: 4413 add r3, r2 8008082: f503 6310 add.w r3, r3, #2304 @ 0x900 8008086: 461a mov r2, r3 8008088: f64f 337f movw r3, #64383 @ 0xfb7f 800808c: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 800808e: 693b ldr r3, [r7, #16] 8008090: 3301 adds r3, #1 8008092: 613b str r3, [r7, #16] 8008094: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8008098: 461a mov r2, r3 800809a: 693b ldr r3, [r7, #16] 800809c: 4293 cmp r3, r2 800809e: d3b5 bcc.n 800800c } for (i = 0U; i < cfg.dev_endpoints; i++) 80080a0: 2300 movs r3, #0 80080a2: 613b str r3, [r7, #16] 80080a4: e043 b.n 800812e { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80080a6: 693b ldr r3, [r7, #16] 80080a8: 015a lsls r2, r3, #5 80080aa: 68fb ldr r3, [r7, #12] 80080ac: 4413 add r3, r2 80080ae: f503 6330 add.w r3, r3, #2816 @ 0xb00 80080b2: 681b ldr r3, [r3, #0] 80080b4: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80080b8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80080bc: d118 bne.n 80080f0 { if (i == 0U) 80080be: 693b ldr r3, [r7, #16] 80080c0: 2b00 cmp r3, #0 80080c2: d10a bne.n 80080da { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 80080c4: 693b ldr r3, [r7, #16] 80080c6: 015a lsls r2, r3, #5 80080c8: 68fb ldr r3, [r7, #12] 80080ca: 4413 add r3, r2 80080cc: f503 6330 add.w r3, r3, #2816 @ 0xb00 80080d0: 461a mov r2, r3 80080d2: f04f 6300 mov.w r3, #134217728 @ 0x8000000 80080d6: 6013 str r3, [r2, #0] 80080d8: e013 b.n 8008102 } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 80080da: 693b ldr r3, [r7, #16] 80080dc: 015a lsls r2, r3, #5 80080de: 68fb ldr r3, [r7, #12] 80080e0: 4413 add r3, r2 80080e2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80080e6: 461a mov r2, r3 80080e8: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 80080ec: 6013 str r3, [r2, #0] 80080ee: e008 b.n 8008102 } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 80080f0: 693b ldr r3, [r7, #16] 80080f2: 015a lsls r2, r3, #5 80080f4: 68fb ldr r3, [r7, #12] 80080f6: 4413 add r3, r2 80080f8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80080fc: 461a mov r2, r3 80080fe: 2300 movs r3, #0 8008100: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 8008102: 693b ldr r3, [r7, #16] 8008104: 015a lsls r2, r3, #5 8008106: 68fb ldr r3, [r7, #12] 8008108: 4413 add r3, r2 800810a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800810e: 461a mov r2, r3 8008110: 2300 movs r3, #0 8008112: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8008114: 693b ldr r3, [r7, #16] 8008116: 015a lsls r2, r3, #5 8008118: 68fb ldr r3, [r7, #12] 800811a: 4413 add r3, r2 800811c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008120: 461a mov r2, r3 8008122: f64f 337f movw r3, #64383 @ 0xfb7f 8008126: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8008128: 693b ldr r3, [r7, #16] 800812a: 3301 adds r3, #1 800812c: 613b str r3, [r7, #16] 800812e: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8008132: 461a mov r2, r3 8008134: 693b ldr r3, [r7, #16] 8008136: 4293 cmp r3, r2 8008138: d3b5 bcc.n 80080a6 } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 800813a: 68fb ldr r3, [r7, #12] 800813c: f503 6300 add.w r3, r3, #2048 @ 0x800 8008140: 691b ldr r3, [r3, #16] 8008142: 68fa ldr r2, [r7, #12] 8008144: f502 6200 add.w r2, r2, #2048 @ 0x800 8008148: f423 7380 bic.w r3, r3, #256 @ 0x100 800814c: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 800814e: 687b ldr r3, [r7, #4] 8008150: 2200 movs r2, #0 8008152: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 8008154: 687b ldr r3, [r7, #4] 8008156: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000 800815a: 615a str r2, [r3, #20] /* Enable the common interrupts */ if (cfg.dma_enable == 0U) 800815c: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8008160: 2b00 cmp r3, #0 8008162: d105 bne.n 8008170 { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 8008164: 687b ldr r3, [r7, #4] 8008166: 699b ldr r3, [r3, #24] 8008168: f043 0210 orr.w r2, r3, #16 800816c: 687b ldr r3, [r7, #4] 800816e: 619a str r2, [r3, #24] } /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 8008170: 687b ldr r3, [r7, #4] 8008172: 699a ldr r2, [r3, #24] 8008174: 4b10 ldr r3, [pc, #64] @ (80081b8 ) 8008176: 4313 orrs r3, r2 8008178: 687a ldr r2, [r7, #4] 800817a: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 800817c: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 8008180: 2b00 cmp r3, #0 8008182: d005 beq.n 8008190 { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 8008184: 687b ldr r3, [r7, #4] 8008186: 699b ldr r3, [r3, #24] 8008188: f043 0208 orr.w r2, r3, #8 800818c: 687b ldr r3, [r7, #4] 800818e: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 8008190: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8008194: 2b01 cmp r3, #1 8008196: d107 bne.n 80081a8 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 8008198: 687b ldr r3, [r7, #4] 800819a: 699b ldr r3, [r3, #24] 800819c: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80081a0: f043 0304 orr.w r3, r3, #4 80081a4: 687a ldr r2, [r7, #4] 80081a6: 6193 str r3, [r2, #24] } return ret; 80081a8: 7dfb ldrb r3, [r7, #23] } 80081aa: 4618 mov r0, r3 80081ac: 3718 adds r7, #24 80081ae: 46bd mov sp, r7 80081b0: e8bd 4080 ldmia.w sp!, {r7, lr} 80081b4: b004 add sp, #16 80081b6: 4770 bx lr 80081b8: 803c3800 .word 0x803c3800 080081bc : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 80081bc: b480 push {r7} 80081be: b085 sub sp, #20 80081c0: af00 add r7, sp, #0 80081c2: 6078 str r0, [r7, #4] 80081c4: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 80081c6: 2300 movs r3, #0 80081c8: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 80081ca: 68fb ldr r3, [r7, #12] 80081cc: 3301 adds r3, #1 80081ce: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80081d0: 68fb ldr r3, [r7, #12] 80081d2: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80081d6: d901 bls.n 80081dc { return HAL_TIMEOUT; 80081d8: 2303 movs r3, #3 80081da: e01b b.n 8008214 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 80081dc: 687b ldr r3, [r7, #4] 80081de: 691b ldr r3, [r3, #16] 80081e0: 2b00 cmp r3, #0 80081e2: daf2 bge.n 80081ca /* Flush TX Fifo */ count = 0U; 80081e4: 2300 movs r3, #0 80081e6: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 80081e8: 683b ldr r3, [r7, #0] 80081ea: 019b lsls r3, r3, #6 80081ec: f043 0220 orr.w r2, r3, #32 80081f0: 687b ldr r3, [r7, #4] 80081f2: 611a str r2, [r3, #16] do { count++; 80081f4: 68fb ldr r3, [r7, #12] 80081f6: 3301 adds r3, #1 80081f8: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80081fa: 68fb ldr r3, [r7, #12] 80081fc: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8008200: d901 bls.n 8008206 { return HAL_TIMEOUT; 8008202: 2303 movs r3, #3 8008204: e006 b.n 8008214 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 8008206: 687b ldr r3, [r7, #4] 8008208: 691b ldr r3, [r3, #16] 800820a: f003 0320 and.w r3, r3, #32 800820e: 2b20 cmp r3, #32 8008210: d0f0 beq.n 80081f4 return HAL_OK; 8008212: 2300 movs r3, #0 } 8008214: 4618 mov r0, r3 8008216: 3714 adds r7, #20 8008218: 46bd mov sp, r7 800821a: f85d 7b04 ldr.w r7, [sp], #4 800821e: 4770 bx lr 08008220 : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 8008220: b480 push {r7} 8008222: b085 sub sp, #20 8008224: af00 add r7, sp, #0 8008226: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8008228: 2300 movs r3, #0 800822a: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 800822c: 68fb ldr r3, [r7, #12] 800822e: 3301 adds r3, #1 8008230: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8008232: 68fb ldr r3, [r7, #12] 8008234: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8008238: d901 bls.n 800823e { return HAL_TIMEOUT; 800823a: 2303 movs r3, #3 800823c: e018 b.n 8008270 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 800823e: 687b ldr r3, [r7, #4] 8008240: 691b ldr r3, [r3, #16] 8008242: 2b00 cmp r3, #0 8008244: daf2 bge.n 800822c /* Flush RX Fifo */ count = 0U; 8008246: 2300 movs r3, #0 8008248: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 800824a: 687b ldr r3, [r7, #4] 800824c: 2210 movs r2, #16 800824e: 611a str r2, [r3, #16] do { count++; 8008250: 68fb ldr r3, [r7, #12] 8008252: 3301 adds r3, #1 8008254: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8008256: 68fb ldr r3, [r7, #12] 8008258: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 800825c: d901 bls.n 8008262 { return HAL_TIMEOUT; 800825e: 2303 movs r3, #3 8008260: e006 b.n 8008270 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 8008262: 687b ldr r3, [r7, #4] 8008264: 691b ldr r3, [r3, #16] 8008266: f003 0310 and.w r3, r3, #16 800826a: 2b10 cmp r3, #16 800826c: d0f0 beq.n 8008250 return HAL_OK; 800826e: 2300 movs r3, #0 } 8008270: 4618 mov r0, r3 8008272: 3714 adds r7, #20 8008274: 46bd mov sp, r7 8008276: f85d 7b04 ldr.w r7, [sp], #4 800827a: 4770 bx lr 0800827c : * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 800827c: b480 push {r7} 800827e: b085 sub sp, #20 8008280: af00 add r7, sp, #0 8008282: 6078 str r0, [r7, #4] 8008284: 460b mov r3, r1 8008286: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008288: 687b ldr r3, [r7, #4] 800828a: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 800828c: 68fb ldr r3, [r7, #12] 800828e: f503 6300 add.w r3, r3, #2048 @ 0x800 8008292: 681a ldr r2, [r3, #0] 8008294: 78fb ldrb r3, [r7, #3] 8008296: 68f9 ldr r1, [r7, #12] 8008298: f501 6100 add.w r1, r1, #2048 @ 0x800 800829c: 4313 orrs r3, r2 800829e: 600b str r3, [r1, #0] return HAL_OK; 80082a0: 2300 movs r3, #0 } 80082a2: 4618 mov r0, r3 80082a4: 3714 adds r7, #20 80082a6: 46bd mov sp, r7 80082a8: f85d 7b04 ldr.w r7, [sp], #4 80082ac: 4770 bx lr 080082ae : * This parameter can be one of these values: * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { 80082ae: b480 push {r7} 80082b0: b087 sub sp, #28 80082b2: af00 add r7, sp, #0 80082b4: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80082b6: 687b ldr r3, [r7, #4] 80082b8: 613b str r3, [r7, #16] uint8_t speed; uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; 80082ba: 693b ldr r3, [r7, #16] 80082bc: f503 6300 add.w r3, r3, #2048 @ 0x800 80082c0: 689b ldr r3, [r3, #8] 80082c2: f003 0306 and.w r3, r3, #6 80082c6: 60fb str r3, [r7, #12] if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 80082c8: 68fb ldr r3, [r7, #12] 80082ca: 2b00 cmp r3, #0 80082cc: d102 bne.n 80082d4 { speed = USBD_HS_SPEED; 80082ce: 2300 movs r3, #0 80082d0: 75fb strb r3, [r7, #23] 80082d2: e00a b.n 80082ea } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || 80082d4: 68fb ldr r3, [r7, #12] 80082d6: 2b02 cmp r3, #2 80082d8: d002 beq.n 80082e0 80082da: 68fb ldr r3, [r7, #12] 80082dc: 2b06 cmp r3, #6 80082de: d102 bne.n 80082e6 (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USBD_FS_SPEED; 80082e0: 2302 movs r3, #2 80082e2: 75fb strb r3, [r7, #23] 80082e4: e001 b.n 80082ea } else { speed = 0xFU; 80082e6: 230f movs r3, #15 80082e8: 75fb strb r3, [r7, #23] } return speed; 80082ea: 7dfb ldrb r3, [r7, #23] } 80082ec: 4618 mov r0, r3 80082ee: 371c adds r7, #28 80082f0: 46bd mov sp, r7 80082f2: f85d 7b04 ldr.w r7, [sp], #4 80082f6: 4770 bx lr 080082f8 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 80082f8: b480 push {r7} 80082fa: b085 sub sp, #20 80082fc: af00 add r7, sp, #0 80082fe: 6078 str r0, [r7, #4] 8008300: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8008302: 687b ldr r3, [r7, #4] 8008304: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8008306: 683b ldr r3, [r7, #0] 8008308: 781b ldrb r3, [r3, #0] 800830a: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 800830c: 683b ldr r3, [r7, #0] 800830e: 785b ldrb r3, [r3, #1] 8008310: 2b01 cmp r3, #1 8008312: d13a bne.n 800838a { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); 8008314: 68fb ldr r3, [r7, #12] 8008316: f503 6300 add.w r3, r3, #2048 @ 0x800 800831a: 69da ldr r2, [r3, #28] 800831c: 683b ldr r3, [r7, #0] 800831e: 781b ldrb r3, [r3, #0] 8008320: f003 030f and.w r3, r3, #15 8008324: 2101 movs r1, #1 8008326: fa01 f303 lsl.w r3, r1, r3 800832a: b29b uxth r3, r3 800832c: 68f9 ldr r1, [r7, #12] 800832e: f501 6100 add.w r1, r1, #2048 @ 0x800 8008332: 4313 orrs r3, r2 8008334: 61cb str r3, [r1, #28] if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) 8008336: 68bb ldr r3, [r7, #8] 8008338: 015a lsls r2, r3, #5 800833a: 68fb ldr r3, [r7, #12] 800833c: 4413 add r3, r2 800833e: f503 6310 add.w r3, r3, #2304 @ 0x900 8008342: 681b ldr r3, [r3, #0] 8008344: f403 4300 and.w r3, r3, #32768 @ 0x8000 8008348: 2b00 cmp r3, #0 800834a: d155 bne.n 80083f8 { USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 800834c: 68bb ldr r3, [r7, #8] 800834e: 015a lsls r2, r3, #5 8008350: 68fb ldr r3, [r7, #12] 8008352: 4413 add r3, r2 8008354: f503 6310 add.w r3, r3, #2304 @ 0x900 8008358: 681a ldr r2, [r3, #0] 800835a: 683b ldr r3, [r7, #0] 800835c: 689b ldr r3, [r3, #8] 800835e: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | (epnum << 22) | 8008362: 683b ldr r3, [r7, #0] 8008364: 791b ldrb r3, [r3, #4] 8008366: 049b lsls r3, r3, #18 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8008368: 4319 orrs r1, r3 ((uint32_t)ep->type << 18) | (epnum << 22) | 800836a: 68bb ldr r3, [r7, #8] 800836c: 059b lsls r3, r3, #22 800836e: 430b orrs r3, r1 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8008370: 4313 orrs r3, r2 8008372: 68ba ldr r2, [r7, #8] 8008374: 0151 lsls r1, r2, #5 8008376: 68fa ldr r2, [r7, #12] 8008378: 440a add r2, r1 800837a: f502 6210 add.w r2, r2, #2304 @ 0x900 800837e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008382: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8008386: 6013 str r3, [r2, #0] 8008388: e036 b.n 80083f8 USB_OTG_DIEPCTL_USBAEP; } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); 800838a: 68fb ldr r3, [r7, #12] 800838c: f503 6300 add.w r3, r3, #2048 @ 0x800 8008390: 69da ldr r2, [r3, #28] 8008392: 683b ldr r3, [r7, #0] 8008394: 781b ldrb r3, [r3, #0] 8008396: f003 030f and.w r3, r3, #15 800839a: 2101 movs r1, #1 800839c: fa01 f303 lsl.w r3, r1, r3 80083a0: 041b lsls r3, r3, #16 80083a2: 68f9 ldr r1, [r7, #12] 80083a4: f501 6100 add.w r1, r1, #2048 @ 0x800 80083a8: 4313 orrs r3, r2 80083aa: 61cb str r3, [r1, #28] if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) 80083ac: 68bb ldr r3, [r7, #8] 80083ae: 015a lsls r2, r3, #5 80083b0: 68fb ldr r3, [r7, #12] 80083b2: 4413 add r3, r2 80083b4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80083b8: 681b ldr r3, [r3, #0] 80083ba: f403 4300 and.w r3, r3, #32768 @ 0x8000 80083be: 2b00 cmp r3, #0 80083c0: d11a bne.n 80083f8 { USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 80083c2: 68bb ldr r3, [r7, #8] 80083c4: 015a lsls r2, r3, #5 80083c6: 68fb ldr r3, [r7, #12] 80083c8: 4413 add r3, r2 80083ca: f503 6330 add.w r3, r3, #2816 @ 0xb00 80083ce: 681a ldr r2, [r3, #0] 80083d0: 683b ldr r3, [r7, #0] 80083d2: 689b ldr r3, [r3, #8] 80083d4: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | 80083d8: 683b ldr r3, [r7, #0] 80083da: 791b ldrb r3, [r3, #4] 80083dc: 049b lsls r3, r3, #18 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 80083de: 430b orrs r3, r1 80083e0: 4313 orrs r3, r2 80083e2: 68ba ldr r2, [r7, #8] 80083e4: 0151 lsls r1, r2, #5 80083e6: 68fa ldr r2, [r7, #12] 80083e8: 440a add r2, r1 80083ea: f502 6230 add.w r2, r2, #2816 @ 0xb00 80083ee: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80083f2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80083f6: 6013 str r3, [r2, #0] USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; 80083f8: 2300 movs r3, #0 } 80083fa: 4618 mov r0, r3 80083fc: 3714 adds r7, #20 80083fe: 46bd mov sp, r7 8008400: f85d 7b04 ldr.w r7, [sp], #4 8008404: 4770 bx lr ... 08008408 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8008408: b480 push {r7} 800840a: b085 sub sp, #20 800840c: af00 add r7, sp, #0 800840e: 6078 str r0, [r7, #4] 8008410: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8008412: 687b ldr r3, [r7, #4] 8008414: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8008416: 683b ldr r3, [r7, #0] 8008418: 781b ldrb r3, [r3, #0] 800841a: 60bb str r3, [r7, #8] /* Read DEPCTLn register */ if (ep->is_in == 1U) 800841c: 683b ldr r3, [r7, #0] 800841e: 785b ldrb r3, [r3, #1] 8008420: 2b01 cmp r3, #1 8008422: d161 bne.n 80084e8 { if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8008424: 68bb ldr r3, [r7, #8] 8008426: 015a lsls r2, r3, #5 8008428: 68fb ldr r3, [r7, #12] 800842a: 4413 add r3, r2 800842c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008430: 681b ldr r3, [r3, #0] 8008432: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008436: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800843a: d11f bne.n 800847c { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 800843c: 68bb ldr r3, [r7, #8] 800843e: 015a lsls r2, r3, #5 8008440: 68fb ldr r3, [r7, #12] 8008442: 4413 add r3, r2 8008444: f503 6310 add.w r3, r3, #2304 @ 0x900 8008448: 681b ldr r3, [r3, #0] 800844a: 68ba ldr r2, [r7, #8] 800844c: 0151 lsls r1, r2, #5 800844e: 68fa ldr r2, [r7, #12] 8008450: 440a add r2, r1 8008452: f502 6210 add.w r2, r2, #2304 @ 0x900 8008456: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800845a: 6013 str r3, [r2, #0] USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; 800845c: 68bb ldr r3, [r7, #8] 800845e: 015a lsls r2, r3, #5 8008460: 68fb ldr r3, [r7, #12] 8008462: 4413 add r3, r2 8008464: f503 6310 add.w r3, r3, #2304 @ 0x900 8008468: 681b ldr r3, [r3, #0] 800846a: 68ba ldr r2, [r7, #8] 800846c: 0151 lsls r1, r2, #5 800846e: 68fa ldr r2, [r7, #12] 8008470: 440a add r2, r1 8008472: f502 6210 add.w r2, r2, #2304 @ 0x900 8008476: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800847a: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 800847c: 68fb ldr r3, [r7, #12] 800847e: f503 6300 add.w r3, r3, #2048 @ 0x800 8008482: 6bda ldr r2, [r3, #60] @ 0x3c 8008484: 683b ldr r3, [r7, #0] 8008486: 781b ldrb r3, [r3, #0] 8008488: f003 030f and.w r3, r3, #15 800848c: 2101 movs r1, #1 800848e: fa01 f303 lsl.w r3, r1, r3 8008492: b29b uxth r3, r3 8008494: 43db mvns r3, r3 8008496: 68f9 ldr r1, [r7, #12] 8008498: f501 6100 add.w r1, r1, #2048 @ 0x800 800849c: 4013 ands r3, r2 800849e: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 80084a0: 68fb ldr r3, [r7, #12] 80084a2: f503 6300 add.w r3, r3, #2048 @ 0x800 80084a6: 69da ldr r2, [r3, #28] 80084a8: 683b ldr r3, [r7, #0] 80084aa: 781b ldrb r3, [r3, #0] 80084ac: f003 030f and.w r3, r3, #15 80084b0: 2101 movs r1, #1 80084b2: fa01 f303 lsl.w r3, r1, r3 80084b6: b29b uxth r3, r3 80084b8: 43db mvns r3, r3 80084ba: 68f9 ldr r1, [r7, #12] 80084bc: f501 6100 add.w r1, r1, #2048 @ 0x800 80084c0: 4013 ands r3, r2 80084c2: 61cb str r3, [r1, #28] USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | 80084c4: 68bb ldr r3, [r7, #8] 80084c6: 015a lsls r2, r3, #5 80084c8: 68fb ldr r3, [r7, #12] 80084ca: 4413 add r3, r2 80084cc: f503 6310 add.w r3, r3, #2304 @ 0x900 80084d0: 681a ldr r2, [r3, #0] 80084d2: 68bb ldr r3, [r7, #8] 80084d4: 0159 lsls r1, r3, #5 80084d6: 68fb ldr r3, [r7, #12] 80084d8: 440b add r3, r1 80084da: f503 6310 add.w r3, r3, #2304 @ 0x900 80084de: 4619 mov r1, r3 80084e0: 4b35 ldr r3, [pc, #212] @ (80085b8 ) 80084e2: 4013 ands r3, r2 80084e4: 600b str r3, [r1, #0] 80084e6: e060 b.n 80085aa USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_EPTYP); } else { if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80084e8: 68bb ldr r3, [r7, #8] 80084ea: 015a lsls r2, r3, #5 80084ec: 68fb ldr r3, [r7, #12] 80084ee: 4413 add r3, r2 80084f0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80084f4: 681b ldr r3, [r3, #0] 80084f6: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80084fa: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80084fe: d11f bne.n 8008540 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 8008500: 68bb ldr r3, [r7, #8] 8008502: 015a lsls r2, r3, #5 8008504: 68fb ldr r3, [r7, #12] 8008506: 4413 add r3, r2 8008508: f503 6330 add.w r3, r3, #2816 @ 0xb00 800850c: 681b ldr r3, [r3, #0] 800850e: 68ba ldr r2, [r7, #8] 8008510: 0151 lsls r1, r2, #5 8008512: 68fa ldr r2, [r7, #12] 8008514: 440a add r2, r1 8008516: f502 6230 add.w r2, r2, #2816 @ 0xb00 800851a: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 800851e: 6013 str r3, [r2, #0] USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; 8008520: 68bb ldr r3, [r7, #8] 8008522: 015a lsls r2, r3, #5 8008524: 68fb ldr r3, [r7, #12] 8008526: 4413 add r3, r2 8008528: f503 6330 add.w r3, r3, #2816 @ 0xb00 800852c: 681b ldr r3, [r3, #0] 800852e: 68ba ldr r2, [r7, #8] 8008530: 0151 lsls r1, r2, #5 8008532: 68fa ldr r2, [r7, #12] 8008534: 440a add r2, r1 8008536: f502 6230 add.w r2, r2, #2816 @ 0xb00 800853a: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800853e: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 8008540: 68fb ldr r3, [r7, #12] 8008542: f503 6300 add.w r3, r3, #2048 @ 0x800 8008546: 6bda ldr r2, [r3, #60] @ 0x3c 8008548: 683b ldr r3, [r7, #0] 800854a: 781b ldrb r3, [r3, #0] 800854c: f003 030f and.w r3, r3, #15 8008550: 2101 movs r1, #1 8008552: fa01 f303 lsl.w r3, r1, r3 8008556: 041b lsls r3, r3, #16 8008558: 43db mvns r3, r3 800855a: 68f9 ldr r1, [r7, #12] 800855c: f501 6100 add.w r1, r1, #2048 @ 0x800 8008560: 4013 ands r3, r2 8008562: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 8008564: 68fb ldr r3, [r7, #12] 8008566: f503 6300 add.w r3, r3, #2048 @ 0x800 800856a: 69da ldr r2, [r3, #28] 800856c: 683b ldr r3, [r7, #0] 800856e: 781b ldrb r3, [r3, #0] 8008570: f003 030f and.w r3, r3, #15 8008574: 2101 movs r1, #1 8008576: fa01 f303 lsl.w r3, r1, r3 800857a: 041b lsls r3, r3, #16 800857c: 43db mvns r3, r3 800857e: 68f9 ldr r1, [r7, #12] 8008580: f501 6100 add.w r1, r1, #2048 @ 0x800 8008584: 4013 ands r3, r2 8008586: 61cb str r3, [r1, #28] USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | 8008588: 68bb ldr r3, [r7, #8] 800858a: 015a lsls r2, r3, #5 800858c: 68fb ldr r3, [r7, #12] 800858e: 4413 add r3, r2 8008590: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008594: 681a ldr r2, [r3, #0] 8008596: 68bb ldr r3, [r7, #8] 8008598: 0159 lsls r1, r3, #5 800859a: 68fb ldr r3, [r7, #12] 800859c: 440b add r3, r1 800859e: f503 6330 add.w r3, r3, #2816 @ 0xb00 80085a2: 4619 mov r1, r3 80085a4: 4b05 ldr r3, [pc, #20] @ (80085bc ) 80085a6: 4013 ands r3, r2 80085a8: 600b str r3, [r1, #0] USB_OTG_DOEPCTL_MPSIZ | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_EPTYP); } return HAL_OK; 80085aa: 2300 movs r3, #0 } 80085ac: 4618 mov r0, r3 80085ae: 3714 adds r7, #20 80085b0: 46bd mov sp, r7 80085b2: f85d 7b04 ldr.w r7, [sp], #4 80085b6: 4770 bx lr 80085b8: ec337800 .word 0xec337800 80085bc: eff37800 .word 0xeff37800 080085c0 : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 80085c0: b580 push {r7, lr} 80085c2: b08a sub sp, #40 @ 0x28 80085c4: af02 add r7, sp, #8 80085c6: 60f8 str r0, [r7, #12] 80085c8: 60b9 str r1, [r7, #8] 80085ca: 4613 mov r3, r2 80085cc: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 80085ce: 68fb ldr r3, [r7, #12] 80085d0: 61fb str r3, [r7, #28] uint32_t epnum = (uint32_t)ep->num; 80085d2: 68bb ldr r3, [r7, #8] 80085d4: 781b ldrb r3, [r3, #0] 80085d6: 61bb str r3, [r7, #24] uint16_t pktcnt; /* IN endpoint */ if (ep->is_in == 1U) 80085d8: 68bb ldr r3, [r7, #8] 80085da: 785b ldrb r3, [r3, #1] 80085dc: 2b01 cmp r3, #1 80085de: f040 817f bne.w 80088e0 { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 80085e2: 68bb ldr r3, [r7, #8] 80085e4: 691b ldr r3, [r3, #16] 80085e6: 2b00 cmp r3, #0 80085e8: d132 bne.n 8008650 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 80085ea: 69bb ldr r3, [r7, #24] 80085ec: 015a lsls r2, r3, #5 80085ee: 69fb ldr r3, [r7, #28] 80085f0: 4413 add r3, r2 80085f2: f503 6310 add.w r3, r3, #2304 @ 0x900 80085f6: 691b ldr r3, [r3, #16] 80085f8: 69ba ldr r2, [r7, #24] 80085fa: 0151 lsls r1, r2, #5 80085fc: 69fa ldr r2, [r7, #28] 80085fe: 440a add r2, r1 8008600: f502 6210 add.w r2, r2, #2304 @ 0x900 8008604: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8008608: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 800860c: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 800860e: 69bb ldr r3, [r7, #24] 8008610: 015a lsls r2, r3, #5 8008612: 69fb ldr r3, [r7, #28] 8008614: 4413 add r3, r2 8008616: f503 6310 add.w r3, r3, #2304 @ 0x900 800861a: 691b ldr r3, [r3, #16] 800861c: 69ba ldr r2, [r7, #24] 800861e: 0151 lsls r1, r2, #5 8008620: 69fa ldr r2, [r7, #28] 8008622: 440a add r2, r1 8008624: f502 6210 add.w r2, r2, #2304 @ 0x900 8008628: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800862c: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 800862e: 69bb ldr r3, [r7, #24] 8008630: 015a lsls r2, r3, #5 8008632: 69fb ldr r3, [r7, #28] 8008634: 4413 add r3, r2 8008636: f503 6310 add.w r3, r3, #2304 @ 0x900 800863a: 691b ldr r3, [r3, #16] 800863c: 69ba ldr r2, [r7, #24] 800863e: 0151 lsls r1, r2, #5 8008640: 69fa ldr r2, [r7, #28] 8008642: 440a add r2, r1 8008644: f502 6210 add.w r2, r2, #2304 @ 0x900 8008648: 0cdb lsrs r3, r3, #19 800864a: 04db lsls r3, r3, #19 800864c: 6113 str r3, [r2, #16] 800864e: e097 b.n 8008780 /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8008650: 69bb ldr r3, [r7, #24] 8008652: 015a lsls r2, r3, #5 8008654: 69fb ldr r3, [r7, #28] 8008656: 4413 add r3, r2 8008658: f503 6310 add.w r3, r3, #2304 @ 0x900 800865c: 691b ldr r3, [r3, #16] 800865e: 69ba ldr r2, [r7, #24] 8008660: 0151 lsls r1, r2, #5 8008662: 69fa ldr r2, [r7, #28] 8008664: 440a add r2, r1 8008666: f502 6210 add.w r2, r2, #2304 @ 0x900 800866a: 0cdb lsrs r3, r3, #19 800866c: 04db lsls r3, r3, #19 800866e: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8008670: 69bb ldr r3, [r7, #24] 8008672: 015a lsls r2, r3, #5 8008674: 69fb ldr r3, [r7, #28] 8008676: 4413 add r3, r2 8008678: f503 6310 add.w r3, r3, #2304 @ 0x900 800867c: 691b ldr r3, [r3, #16] 800867e: 69ba ldr r2, [r7, #24] 8008680: 0151 lsls r1, r2, #5 8008682: 69fa ldr r2, [r7, #28] 8008684: 440a add r2, r1 8008686: f502 6210 add.w r2, r2, #2304 @ 0x900 800868a: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 800868e: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8008692: 6113 str r3, [r2, #16] if (epnum == 0U) 8008694: 69bb ldr r3, [r7, #24] 8008696: 2b00 cmp r3, #0 8008698: d11a bne.n 80086d0 { if (ep->xfer_len > ep->maxpacket) 800869a: 68bb ldr r3, [r7, #8] 800869c: 691a ldr r2, [r3, #16] 800869e: 68bb ldr r3, [r7, #8] 80086a0: 689b ldr r3, [r3, #8] 80086a2: 429a cmp r2, r3 80086a4: d903 bls.n 80086ae { ep->xfer_len = ep->maxpacket; 80086a6: 68bb ldr r3, [r7, #8] 80086a8: 689a ldr r2, [r3, #8] 80086aa: 68bb ldr r3, [r7, #8] 80086ac: 611a str r2, [r3, #16] } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 80086ae: 69bb ldr r3, [r7, #24] 80086b0: 015a lsls r2, r3, #5 80086b2: 69fb ldr r3, [r7, #28] 80086b4: 4413 add r3, r2 80086b6: f503 6310 add.w r3, r3, #2304 @ 0x900 80086ba: 691b ldr r3, [r3, #16] 80086bc: 69ba ldr r2, [r7, #24] 80086be: 0151 lsls r1, r2, #5 80086c0: 69fa ldr r2, [r7, #28] 80086c2: 440a add r2, r1 80086c4: f502 6210 add.w r2, r2, #2304 @ 0x900 80086c8: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80086cc: 6113 str r3, [r2, #16] 80086ce: e044 b.n 800875a } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 80086d0: 68bb ldr r3, [r7, #8] 80086d2: 691a ldr r2, [r3, #16] 80086d4: 68bb ldr r3, [r7, #8] 80086d6: 689b ldr r3, [r3, #8] 80086d8: 4413 add r3, r2 80086da: 1e5a subs r2, r3, #1 80086dc: 68bb ldr r3, [r7, #8] 80086de: 689b ldr r3, [r3, #8] 80086e0: fbb2 f3f3 udiv r3, r2, r3 80086e4: 82fb strh r3, [r7, #22] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); 80086e6: 69bb ldr r3, [r7, #24] 80086e8: 015a lsls r2, r3, #5 80086ea: 69fb ldr r3, [r7, #28] 80086ec: 4413 add r3, r2 80086ee: f503 6310 add.w r3, r3, #2304 @ 0x900 80086f2: 691a ldr r2, [r3, #16] 80086f4: 8afb ldrh r3, [r7, #22] 80086f6: 04d9 lsls r1, r3, #19 80086f8: 4ba4 ldr r3, [pc, #656] @ (800898c ) 80086fa: 400b ands r3, r1 80086fc: 69b9 ldr r1, [r7, #24] 80086fe: 0148 lsls r0, r1, #5 8008700: 69f9 ldr r1, [r7, #28] 8008702: 4401 add r1, r0 8008704: f501 6110 add.w r1, r1, #2304 @ 0x900 8008708: 4313 orrs r3, r2 800870a: 610b str r3, [r1, #16] if (ep->type == EP_TYPE_ISOC) 800870c: 68bb ldr r3, [r7, #8] 800870e: 791b ldrb r3, [r3, #4] 8008710: 2b01 cmp r3, #1 8008712: d122 bne.n 800875a { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 8008714: 69bb ldr r3, [r7, #24] 8008716: 015a lsls r2, r3, #5 8008718: 69fb ldr r3, [r7, #28] 800871a: 4413 add r3, r2 800871c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008720: 691b ldr r3, [r3, #16] 8008722: 69ba ldr r2, [r7, #24] 8008724: 0151 lsls r1, r2, #5 8008726: 69fa ldr r2, [r7, #28] 8008728: 440a add r2, r1 800872a: f502 6210 add.w r2, r2, #2304 @ 0x900 800872e: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000 8008732: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); 8008734: 69bb ldr r3, [r7, #24] 8008736: 015a lsls r2, r3, #5 8008738: 69fb ldr r3, [r7, #28] 800873a: 4413 add r3, r2 800873c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008740: 691a ldr r2, [r3, #16] 8008742: 8afb ldrh r3, [r7, #22] 8008744: 075b lsls r3, r3, #29 8008746: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000 800874a: 69b9 ldr r1, [r7, #24] 800874c: 0148 lsls r0, r1, #5 800874e: 69f9 ldr r1, [r7, #28] 8008750: 4401 add r1, r0 8008752: f501 6110 add.w r1, r1, #2304 @ 0x900 8008756: 4313 orrs r3, r2 8008758: 610b str r3, [r1, #16] } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 800875a: 69bb ldr r3, [r7, #24] 800875c: 015a lsls r2, r3, #5 800875e: 69fb ldr r3, [r7, #28] 8008760: 4413 add r3, r2 8008762: f503 6310 add.w r3, r3, #2304 @ 0x900 8008766: 691a ldr r2, [r3, #16] 8008768: 68bb ldr r3, [r7, #8] 800876a: 691b ldr r3, [r3, #16] 800876c: f3c3 0312 ubfx r3, r3, #0, #19 8008770: 69b9 ldr r1, [r7, #24] 8008772: 0148 lsls r0, r1, #5 8008774: 69f9 ldr r1, [r7, #28] 8008776: 4401 add r1, r0 8008778: f501 6110 add.w r1, r1, #2304 @ 0x900 800877c: 4313 orrs r3, r2 800877e: 610b str r3, [r1, #16] } if (dma == 1U) 8008780: 79fb ldrb r3, [r7, #7] 8008782: 2b01 cmp r3, #1 8008784: d14b bne.n 800881e { if ((uint32_t)ep->dma_addr != 0U) 8008786: 68bb ldr r3, [r7, #8] 8008788: 69db ldr r3, [r3, #28] 800878a: 2b00 cmp r3, #0 800878c: d009 beq.n 80087a2 { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 800878e: 69bb ldr r3, [r7, #24] 8008790: 015a lsls r2, r3, #5 8008792: 69fb ldr r3, [r7, #28] 8008794: 4413 add r3, r2 8008796: f503 6310 add.w r3, r3, #2304 @ 0x900 800879a: 461a mov r2, r3 800879c: 68bb ldr r3, [r7, #8] 800879e: 69db ldr r3, [r3, #28] 80087a0: 6153 str r3, [r2, #20] } if (ep->type == EP_TYPE_ISOC) 80087a2: 68bb ldr r3, [r7, #8] 80087a4: 791b ldrb r3, [r3, #4] 80087a6: 2b01 cmp r3, #1 80087a8: d128 bne.n 80087fc { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 80087aa: 69fb ldr r3, [r7, #28] 80087ac: f503 6300 add.w r3, r3, #2048 @ 0x800 80087b0: 689b ldr r3, [r3, #8] 80087b2: f403 7380 and.w r3, r3, #256 @ 0x100 80087b6: 2b00 cmp r3, #0 80087b8: d110 bne.n 80087dc { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 80087ba: 69bb ldr r3, [r7, #24] 80087bc: 015a lsls r2, r3, #5 80087be: 69fb ldr r3, [r7, #28] 80087c0: 4413 add r3, r2 80087c2: f503 6310 add.w r3, r3, #2304 @ 0x900 80087c6: 681b ldr r3, [r3, #0] 80087c8: 69ba ldr r2, [r7, #24] 80087ca: 0151 lsls r1, r2, #5 80087cc: 69fa ldr r2, [r7, #28] 80087ce: 440a add r2, r1 80087d0: f502 6210 add.w r2, r2, #2304 @ 0x900 80087d4: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 80087d8: 6013 str r3, [r2, #0] 80087da: e00f b.n 80087fc } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 80087dc: 69bb ldr r3, [r7, #24] 80087de: 015a lsls r2, r3, #5 80087e0: 69fb ldr r3, [r7, #28] 80087e2: 4413 add r3, r2 80087e4: f503 6310 add.w r3, r3, #2304 @ 0x900 80087e8: 681b ldr r3, [r3, #0] 80087ea: 69ba ldr r2, [r7, #24] 80087ec: 0151 lsls r1, r2, #5 80087ee: 69fa ldr r2, [r7, #28] 80087f0: 440a add r2, r1 80087f2: f502 6210 add.w r2, r2, #2304 @ 0x900 80087f6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80087fa: 6013 str r3, [r2, #0] } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 80087fc: 69bb ldr r3, [r7, #24] 80087fe: 015a lsls r2, r3, #5 8008800: 69fb ldr r3, [r7, #28] 8008802: 4413 add r3, r2 8008804: f503 6310 add.w r3, r3, #2304 @ 0x900 8008808: 681b ldr r3, [r3, #0] 800880a: 69ba ldr r2, [r7, #24] 800880c: 0151 lsls r1, r2, #5 800880e: 69fa ldr r2, [r7, #28] 8008810: 440a add r2, r1 8008812: f502 6210 add.w r2, r2, #2304 @ 0x900 8008816: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 800881a: 6013 str r3, [r2, #0] 800881c: e166 b.n 8008aec } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 800881e: 69bb ldr r3, [r7, #24] 8008820: 015a lsls r2, r3, #5 8008822: 69fb ldr r3, [r7, #28] 8008824: 4413 add r3, r2 8008826: f503 6310 add.w r3, r3, #2304 @ 0x900 800882a: 681b ldr r3, [r3, #0] 800882c: 69ba ldr r2, [r7, #24] 800882e: 0151 lsls r1, r2, #5 8008830: 69fa ldr r2, [r7, #28] 8008832: 440a add r2, r1 8008834: f502 6210 add.w r2, r2, #2304 @ 0x900 8008838: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 800883c: 6013 str r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 800883e: 68bb ldr r3, [r7, #8] 8008840: 791b ldrb r3, [r3, #4] 8008842: 2b01 cmp r3, #1 8008844: d015 beq.n 8008872 { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 8008846: 68bb ldr r3, [r7, #8] 8008848: 691b ldr r3, [r3, #16] 800884a: 2b00 cmp r3, #0 800884c: f000 814e beq.w 8008aec { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 8008850: 69fb ldr r3, [r7, #28] 8008852: f503 6300 add.w r3, r3, #2048 @ 0x800 8008856: 6b5a ldr r2, [r3, #52] @ 0x34 8008858: 68bb ldr r3, [r7, #8] 800885a: 781b ldrb r3, [r3, #0] 800885c: f003 030f and.w r3, r3, #15 8008860: 2101 movs r1, #1 8008862: fa01 f303 lsl.w r3, r1, r3 8008866: 69f9 ldr r1, [r7, #28] 8008868: f501 6100 add.w r1, r1, #2048 @ 0x800 800886c: 4313 orrs r3, r2 800886e: 634b str r3, [r1, #52] @ 0x34 8008870: e13c b.n 8008aec } } else { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8008872: 69fb ldr r3, [r7, #28] 8008874: f503 6300 add.w r3, r3, #2048 @ 0x800 8008878: 689b ldr r3, [r3, #8] 800887a: f403 7380 and.w r3, r3, #256 @ 0x100 800887e: 2b00 cmp r3, #0 8008880: d110 bne.n 80088a4 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8008882: 69bb ldr r3, [r7, #24] 8008884: 015a lsls r2, r3, #5 8008886: 69fb ldr r3, [r7, #28] 8008888: 4413 add r3, r2 800888a: f503 6310 add.w r3, r3, #2304 @ 0x900 800888e: 681b ldr r3, [r3, #0] 8008890: 69ba ldr r2, [r7, #24] 8008892: 0151 lsls r1, r2, #5 8008894: 69fa ldr r2, [r7, #28] 8008896: 440a add r2, r1 8008898: f502 6210 add.w r2, r2, #2304 @ 0x900 800889c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 80088a0: 6013 str r3, [r2, #0] 80088a2: e00f b.n 80088c4 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 80088a4: 69bb ldr r3, [r7, #24] 80088a6: 015a lsls r2, r3, #5 80088a8: 69fb ldr r3, [r7, #28] 80088aa: 4413 add r3, r2 80088ac: f503 6310 add.w r3, r3, #2304 @ 0x900 80088b0: 681b ldr r3, [r3, #0] 80088b2: 69ba ldr r2, [r7, #24] 80088b4: 0151 lsls r1, r2, #5 80088b6: 69fa ldr r2, [r7, #28] 80088b8: 440a add r2, r1 80088ba: f502 6210 add.w r2, r2, #2304 @ 0x900 80088be: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80088c2: 6013 str r3, [r2, #0] } (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); 80088c4: 68bb ldr r3, [r7, #8] 80088c6: 68d9 ldr r1, [r3, #12] 80088c8: 68bb ldr r3, [r7, #8] 80088ca: 781a ldrb r2, [r3, #0] 80088cc: 68bb ldr r3, [r7, #8] 80088ce: 691b ldr r3, [r3, #16] 80088d0: b298 uxth r0, r3 80088d2: 79fb ldrb r3, [r7, #7] 80088d4: 9300 str r3, [sp, #0] 80088d6: 4603 mov r3, r0 80088d8: 68f8 ldr r0, [r7, #12] 80088da: f000 f9b9 bl 8008c50 80088de: e105 b.n 8008aec { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 80088e0: 69bb ldr r3, [r7, #24] 80088e2: 015a lsls r2, r3, #5 80088e4: 69fb ldr r3, [r7, #28] 80088e6: 4413 add r3, r2 80088e8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80088ec: 691b ldr r3, [r3, #16] 80088ee: 69ba ldr r2, [r7, #24] 80088f0: 0151 lsls r1, r2, #5 80088f2: 69fa ldr r2, [r7, #28] 80088f4: 440a add r2, r1 80088f6: f502 6230 add.w r2, r2, #2816 @ 0xb00 80088fa: 0cdb lsrs r3, r3, #19 80088fc: 04db lsls r3, r3, #19 80088fe: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 8008900: 69bb ldr r3, [r7, #24] 8008902: 015a lsls r2, r3, #5 8008904: 69fb ldr r3, [r7, #28] 8008906: 4413 add r3, r2 8008908: f503 6330 add.w r3, r3, #2816 @ 0xb00 800890c: 691b ldr r3, [r3, #16] 800890e: 69ba ldr r2, [r7, #24] 8008910: 0151 lsls r1, r2, #5 8008912: 69fa ldr r2, [r7, #28] 8008914: 440a add r2, r1 8008916: f502 6230 add.w r2, r2, #2816 @ 0xb00 800891a: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 800891e: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8008922: 6113 str r3, [r2, #16] if (epnum == 0U) 8008924: 69bb ldr r3, [r7, #24] 8008926: 2b00 cmp r3, #0 8008928: d132 bne.n 8008990 { if (ep->xfer_len > 0U) 800892a: 68bb ldr r3, [r7, #8] 800892c: 691b ldr r3, [r3, #16] 800892e: 2b00 cmp r3, #0 8008930: d003 beq.n 800893a { ep->xfer_len = ep->maxpacket; 8008932: 68bb ldr r3, [r7, #8] 8008934: 689a ldr r2, [r3, #8] 8008936: 68bb ldr r3, [r7, #8] 8008938: 611a str r2, [r3, #16] } /* Store transfer size, for EP0 this is equal to endpoint max packet size */ ep->xfer_size = ep->maxpacket; 800893a: 68bb ldr r3, [r7, #8] 800893c: 689a ldr r2, [r3, #8] 800893e: 68bb ldr r3, [r7, #8] 8008940: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); 8008942: 69bb ldr r3, [r7, #24] 8008944: 015a lsls r2, r3, #5 8008946: 69fb ldr r3, [r7, #28] 8008948: 4413 add r3, r2 800894a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800894e: 691a ldr r2, [r3, #16] 8008950: 68bb ldr r3, [r7, #8] 8008952: 6a1b ldr r3, [r3, #32] 8008954: f3c3 0312 ubfx r3, r3, #0, #19 8008958: 69b9 ldr r1, [r7, #24] 800895a: 0148 lsls r0, r1, #5 800895c: 69f9 ldr r1, [r7, #28] 800895e: 4401 add r1, r0 8008960: f501 6130 add.w r1, r1, #2816 @ 0xb00 8008964: 4313 orrs r3, r2 8008966: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8008968: 69bb ldr r3, [r7, #24] 800896a: 015a lsls r2, r3, #5 800896c: 69fb ldr r3, [r7, #28] 800896e: 4413 add r3, r2 8008970: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008974: 691b ldr r3, [r3, #16] 8008976: 69ba ldr r2, [r7, #24] 8008978: 0151 lsls r1, r2, #5 800897a: 69fa ldr r2, [r7, #28] 800897c: 440a add r2, r1 800897e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008982: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8008986: 6113 str r3, [r2, #16] 8008988: e062 b.n 8008a50 800898a: bf00 nop 800898c: 1ff80000 .word 0x1ff80000 } else { if (ep->xfer_len == 0U) 8008990: 68bb ldr r3, [r7, #8] 8008992: 691b ldr r3, [r3, #16] 8008994: 2b00 cmp r3, #0 8008996: d123 bne.n 80089e0 { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 8008998: 69bb ldr r3, [r7, #24] 800899a: 015a lsls r2, r3, #5 800899c: 69fb ldr r3, [r7, #28] 800899e: 4413 add r3, r2 80089a0: f503 6330 add.w r3, r3, #2816 @ 0xb00 80089a4: 691a ldr r2, [r3, #16] 80089a6: 68bb ldr r3, [r7, #8] 80089a8: 689b ldr r3, [r3, #8] 80089aa: f3c3 0312 ubfx r3, r3, #0, #19 80089ae: 69b9 ldr r1, [r7, #24] 80089b0: 0148 lsls r0, r1, #5 80089b2: 69f9 ldr r1, [r7, #28] 80089b4: 4401 add r1, r0 80089b6: f501 6130 add.w r1, r1, #2816 @ 0xb00 80089ba: 4313 orrs r3, r2 80089bc: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 80089be: 69bb ldr r3, [r7, #24] 80089c0: 015a lsls r2, r3, #5 80089c2: 69fb ldr r3, [r7, #28] 80089c4: 4413 add r3, r2 80089c6: f503 6330 add.w r3, r3, #2816 @ 0xb00 80089ca: 691b ldr r3, [r3, #16] 80089cc: 69ba ldr r2, [r7, #24] 80089ce: 0151 lsls r1, r2, #5 80089d0: 69fa ldr r2, [r7, #28] 80089d2: 440a add r2, r1 80089d4: f502 6230 add.w r2, r2, #2816 @ 0xb00 80089d8: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80089dc: 6113 str r3, [r2, #16] 80089de: e037 b.n 8008a50 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 80089e0: 68bb ldr r3, [r7, #8] 80089e2: 691a ldr r2, [r3, #16] 80089e4: 68bb ldr r3, [r7, #8] 80089e6: 689b ldr r3, [r3, #8] 80089e8: 4413 add r3, r2 80089ea: 1e5a subs r2, r3, #1 80089ec: 68bb ldr r3, [r7, #8] 80089ee: 689b ldr r3, [r3, #8] 80089f0: fbb2 f3f3 udiv r3, r2, r3 80089f4: 82fb strh r3, [r7, #22] ep->xfer_size = ep->maxpacket * pktcnt; 80089f6: 68bb ldr r3, [r7, #8] 80089f8: 689b ldr r3, [r3, #8] 80089fa: 8afa ldrh r2, [r7, #22] 80089fc: fb03 f202 mul.w r2, r3, r2 8008a00: 68bb ldr r3, [r7, #8] 8008a02: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); 8008a04: 69bb ldr r3, [r7, #24] 8008a06: 015a lsls r2, r3, #5 8008a08: 69fb ldr r3, [r7, #28] 8008a0a: 4413 add r3, r2 8008a0c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008a10: 691a ldr r2, [r3, #16] 8008a12: 8afb ldrh r3, [r7, #22] 8008a14: 04d9 lsls r1, r3, #19 8008a16: 4b38 ldr r3, [pc, #224] @ (8008af8 ) 8008a18: 400b ands r3, r1 8008a1a: 69b9 ldr r1, [r7, #24] 8008a1c: 0148 lsls r0, r1, #5 8008a1e: 69f9 ldr r1, [r7, #28] 8008a20: 4401 add r1, r0 8008a22: f501 6130 add.w r1, r1, #2816 @ 0xb00 8008a26: 4313 orrs r3, r2 8008a28: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; 8008a2a: 69bb ldr r3, [r7, #24] 8008a2c: 015a lsls r2, r3, #5 8008a2e: 69fb ldr r3, [r7, #28] 8008a30: 4413 add r3, r2 8008a32: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008a36: 691a ldr r2, [r3, #16] 8008a38: 68bb ldr r3, [r7, #8] 8008a3a: 6a1b ldr r3, [r3, #32] 8008a3c: f3c3 0312 ubfx r3, r3, #0, #19 8008a40: 69b9 ldr r1, [r7, #24] 8008a42: 0148 lsls r0, r1, #5 8008a44: 69f9 ldr r1, [r7, #28] 8008a46: 4401 add r1, r0 8008a48: f501 6130 add.w r1, r1, #2816 @ 0xb00 8008a4c: 4313 orrs r3, r2 8008a4e: 610b str r3, [r1, #16] } } if (dma == 1U) 8008a50: 79fb ldrb r3, [r7, #7] 8008a52: 2b01 cmp r3, #1 8008a54: d10d bne.n 8008a72 { if ((uint32_t)ep->xfer_buff != 0U) 8008a56: 68bb ldr r3, [r7, #8] 8008a58: 68db ldr r3, [r3, #12] 8008a5a: 2b00 cmp r3, #0 8008a5c: d009 beq.n 8008a72 { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 8008a5e: 68bb ldr r3, [r7, #8] 8008a60: 68d9 ldr r1, [r3, #12] 8008a62: 69bb ldr r3, [r7, #24] 8008a64: 015a lsls r2, r3, #5 8008a66: 69fb ldr r3, [r7, #28] 8008a68: 4413 add r3, r2 8008a6a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008a6e: 460a mov r2, r1 8008a70: 615a str r2, [r3, #20] } } if (ep->type == EP_TYPE_ISOC) 8008a72: 68bb ldr r3, [r7, #8] 8008a74: 791b ldrb r3, [r3, #4] 8008a76: 2b01 cmp r3, #1 8008a78: d128 bne.n 8008acc { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8008a7a: 69fb ldr r3, [r7, #28] 8008a7c: f503 6300 add.w r3, r3, #2048 @ 0x800 8008a80: 689b ldr r3, [r3, #8] 8008a82: f403 7380 and.w r3, r3, #256 @ 0x100 8008a86: 2b00 cmp r3, #0 8008a88: d110 bne.n 8008aac { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 8008a8a: 69bb ldr r3, [r7, #24] 8008a8c: 015a lsls r2, r3, #5 8008a8e: 69fb ldr r3, [r7, #28] 8008a90: 4413 add r3, r2 8008a92: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008a96: 681b ldr r3, [r3, #0] 8008a98: 69ba ldr r2, [r7, #24] 8008a9a: 0151 lsls r1, r2, #5 8008a9c: 69fa ldr r2, [r7, #28] 8008a9e: 440a add r2, r1 8008aa0: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008aa4: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8008aa8: 6013 str r3, [r2, #0] 8008aaa: e00f b.n 8008acc } else { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 8008aac: 69bb ldr r3, [r7, #24] 8008aae: 015a lsls r2, r3, #5 8008ab0: 69fb ldr r3, [r7, #28] 8008ab2: 4413 add r3, r2 8008ab4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008ab8: 681b ldr r3, [r3, #0] 8008aba: 69ba ldr r2, [r7, #24] 8008abc: 0151 lsls r1, r2, #5 8008abe: 69fa ldr r2, [r7, #28] 8008ac0: 440a add r2, r1 8008ac2: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008ac6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008aca: 6013 str r3, [r2, #0] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8008acc: 69bb ldr r3, [r7, #24] 8008ace: 015a lsls r2, r3, #5 8008ad0: 69fb ldr r3, [r7, #28] 8008ad2: 4413 add r3, r2 8008ad4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008ad8: 681b ldr r3, [r3, #0] 8008ada: 69ba ldr r2, [r7, #24] 8008adc: 0151 lsls r1, r2, #5 8008ade: 69fa ldr r2, [r7, #28] 8008ae0: 440a add r2, r1 8008ae2: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008ae6: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8008aea: 6013 str r3, [r2, #0] } return HAL_OK; 8008aec: 2300 movs r3, #0 } 8008aee: 4618 mov r0, r3 8008af0: 3720 adds r7, #32 8008af2: 46bd mov sp, r7 8008af4: bd80 pop {r7, pc} 8008af6: bf00 nop 8008af8: 1ff80000 .word 0x1ff80000 08008afc : * @param USBx usb device instance * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8008afc: b480 push {r7} 8008afe: b087 sub sp, #28 8008b00: af00 add r7, sp, #0 8008b02: 6078 str r0, [r7, #4] 8008b04: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8008b06: 2300 movs r3, #0 8008b08: 60fb str r3, [r7, #12] HAL_StatusTypeDef ret = HAL_OK; 8008b0a: 2300 movs r3, #0 8008b0c: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8008b0e: 687b ldr r3, [r7, #4] 8008b10: 613b str r3, [r7, #16] /* IN endpoint */ if (ep->is_in == 1U) 8008b12: 683b ldr r3, [r7, #0] 8008b14: 785b ldrb r3, [r3, #1] 8008b16: 2b01 cmp r3, #1 8008b18: d14a bne.n 8008bb0 { /* EP enable, IN data in FIFO */ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8008b1a: 683b ldr r3, [r7, #0] 8008b1c: 781b ldrb r3, [r3, #0] 8008b1e: 015a lsls r2, r3, #5 8008b20: 693b ldr r3, [r7, #16] 8008b22: 4413 add r3, r2 8008b24: f503 6310 add.w r3, r3, #2304 @ 0x900 8008b28: 681b ldr r3, [r3, #0] 8008b2a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008b2e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008b32: f040 8086 bne.w 8008c42 { USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); 8008b36: 683b ldr r3, [r7, #0] 8008b38: 781b ldrb r3, [r3, #0] 8008b3a: 015a lsls r2, r3, #5 8008b3c: 693b ldr r3, [r7, #16] 8008b3e: 4413 add r3, r2 8008b40: f503 6310 add.w r3, r3, #2304 @ 0x900 8008b44: 681b ldr r3, [r3, #0] 8008b46: 683a ldr r2, [r7, #0] 8008b48: 7812 ldrb r2, [r2, #0] 8008b4a: 0151 lsls r1, r2, #5 8008b4c: 693a ldr r2, [r7, #16] 8008b4e: 440a add r2, r1 8008b50: f502 6210 add.w r2, r2, #2304 @ 0x900 8008b54: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8008b58: 6013 str r3, [r2, #0] USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); 8008b5a: 683b ldr r3, [r7, #0] 8008b5c: 781b ldrb r3, [r3, #0] 8008b5e: 015a lsls r2, r3, #5 8008b60: 693b ldr r3, [r7, #16] 8008b62: 4413 add r3, r2 8008b64: f503 6310 add.w r3, r3, #2304 @ 0x900 8008b68: 681b ldr r3, [r3, #0] 8008b6a: 683a ldr r2, [r7, #0] 8008b6c: 7812 ldrb r2, [r2, #0] 8008b6e: 0151 lsls r1, r2, #5 8008b70: 693a ldr r2, [r7, #16] 8008b72: 440a add r2, r1 8008b74: f502 6210 add.w r2, r2, #2304 @ 0x900 8008b78: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8008b7c: 6013 str r3, [r2, #0] do { count++; 8008b7e: 68fb ldr r3, [r7, #12] 8008b80: 3301 adds r3, #1 8008b82: 60fb str r3, [r7, #12] if (count > 10000U) 8008b84: 68fb ldr r3, [r7, #12] 8008b86: f242 7210 movw r2, #10000 @ 0x2710 8008b8a: 4293 cmp r3, r2 8008b8c: d902 bls.n 8008b94 { ret = HAL_ERROR; 8008b8e: 2301 movs r3, #1 8008b90: 75fb strb r3, [r7, #23] break; 8008b92: e056 b.n 8008c42 } } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); 8008b94: 683b ldr r3, [r7, #0] 8008b96: 781b ldrb r3, [r3, #0] 8008b98: 015a lsls r2, r3, #5 8008b9a: 693b ldr r3, [r7, #16] 8008b9c: 4413 add r3, r2 8008b9e: f503 6310 add.w r3, r3, #2304 @ 0x900 8008ba2: 681b ldr r3, [r3, #0] 8008ba4: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008ba8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008bac: d0e7 beq.n 8008b7e 8008bae: e048 b.n 8008c42 } } else /* OUT endpoint */ { if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8008bb0: 683b ldr r3, [r7, #0] 8008bb2: 781b ldrb r3, [r3, #0] 8008bb4: 015a lsls r2, r3, #5 8008bb6: 693b ldr r3, [r7, #16] 8008bb8: 4413 add r3, r2 8008bba: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008bbe: 681b ldr r3, [r3, #0] 8008bc0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008bc4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008bc8: d13b bne.n 8008c42 { USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); 8008bca: 683b ldr r3, [r7, #0] 8008bcc: 781b ldrb r3, [r3, #0] 8008bce: 015a lsls r2, r3, #5 8008bd0: 693b ldr r3, [r7, #16] 8008bd2: 4413 add r3, r2 8008bd4: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008bd8: 681b ldr r3, [r3, #0] 8008bda: 683a ldr r2, [r7, #0] 8008bdc: 7812 ldrb r2, [r2, #0] 8008bde: 0151 lsls r1, r2, #5 8008be0: 693a ldr r2, [r7, #16] 8008be2: 440a add r2, r1 8008be4: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008be8: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8008bec: 6013 str r3, [r2, #0] USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); 8008bee: 683b ldr r3, [r7, #0] 8008bf0: 781b ldrb r3, [r3, #0] 8008bf2: 015a lsls r2, r3, #5 8008bf4: 693b ldr r3, [r7, #16] 8008bf6: 4413 add r3, r2 8008bf8: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008bfc: 681b ldr r3, [r3, #0] 8008bfe: 683a ldr r2, [r7, #0] 8008c00: 7812 ldrb r2, [r2, #0] 8008c02: 0151 lsls r1, r2, #5 8008c04: 693a ldr r2, [r7, #16] 8008c06: 440a add r2, r1 8008c08: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008c0c: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8008c10: 6013 str r3, [r2, #0] do { count++; 8008c12: 68fb ldr r3, [r7, #12] 8008c14: 3301 adds r3, #1 8008c16: 60fb str r3, [r7, #12] if (count > 10000U) 8008c18: 68fb ldr r3, [r7, #12] 8008c1a: f242 7210 movw r2, #10000 @ 0x2710 8008c1e: 4293 cmp r3, r2 8008c20: d902 bls.n 8008c28 { ret = HAL_ERROR; 8008c22: 2301 movs r3, #1 8008c24: 75fb strb r3, [r7, #23] break; 8008c26: e00c b.n 8008c42 } } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); 8008c28: 683b ldr r3, [r7, #0] 8008c2a: 781b ldrb r3, [r3, #0] 8008c2c: 015a lsls r2, r3, #5 8008c2e: 693b ldr r3, [r7, #16] 8008c30: 4413 add r3, r2 8008c32: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008c36: 681b ldr r3, [r3, #0] 8008c38: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008c3c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008c40: d0e7 beq.n 8008c12 } } return ret; 8008c42: 7dfb ldrb r3, [r7, #23] } 8008c44: 4618 mov r0, r3 8008c46: 371c adds r7, #28 8008c48: 46bd mov sp, r7 8008c4a: f85d 7b04 ldr.w r7, [sp], #4 8008c4e: 4770 bx lr 08008c50 : * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { 8008c50: b480 push {r7} 8008c52: b089 sub sp, #36 @ 0x24 8008c54: af00 add r7, sp, #0 8008c56: 60f8 str r0, [r7, #12] 8008c58: 60b9 str r1, [r7, #8] 8008c5a: 4611 mov r1, r2 8008c5c: 461a mov r2, r3 8008c5e: 460b mov r3, r1 8008c60: 71fb strb r3, [r7, #7] 8008c62: 4613 mov r3, r2 8008c64: 80bb strh r3, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008c66: 68fb ldr r3, [r7, #12] 8008c68: 617b str r3, [r7, #20] uint8_t *pSrc = src; 8008c6a: 68bb ldr r3, [r7, #8] 8008c6c: 61fb str r3, [r7, #28] uint32_t count32b; uint32_t i; if (dma == 0U) 8008c6e: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8008c72: 2b00 cmp r3, #0 8008c74: d123 bne.n 8008cbe { count32b = ((uint32_t)len + 3U) / 4U; 8008c76: 88bb ldrh r3, [r7, #4] 8008c78: 3303 adds r3, #3 8008c7a: 089b lsrs r3, r3, #2 8008c7c: 613b str r3, [r7, #16] for (i = 0U; i < count32b; i++) 8008c7e: 2300 movs r3, #0 8008c80: 61bb str r3, [r7, #24] 8008c82: e018 b.n 8008cb6 { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); 8008c84: 79fb ldrb r3, [r7, #7] 8008c86: 031a lsls r2, r3, #12 8008c88: 697b ldr r3, [r7, #20] 8008c8a: 4413 add r3, r2 8008c8c: f503 5380 add.w r3, r3, #4096 @ 0x1000 8008c90: 461a mov r2, r3 8008c92: 69fb ldr r3, [r7, #28] 8008c94: 681b ldr r3, [r3, #0] 8008c96: 6013 str r3, [r2, #0] pSrc++; 8008c98: 69fb ldr r3, [r7, #28] 8008c9a: 3301 adds r3, #1 8008c9c: 61fb str r3, [r7, #28] pSrc++; 8008c9e: 69fb ldr r3, [r7, #28] 8008ca0: 3301 adds r3, #1 8008ca2: 61fb str r3, [r7, #28] pSrc++; 8008ca4: 69fb ldr r3, [r7, #28] 8008ca6: 3301 adds r3, #1 8008ca8: 61fb str r3, [r7, #28] pSrc++; 8008caa: 69fb ldr r3, [r7, #28] 8008cac: 3301 adds r3, #1 8008cae: 61fb str r3, [r7, #28] for (i = 0U; i < count32b; i++) 8008cb0: 69bb ldr r3, [r7, #24] 8008cb2: 3301 adds r3, #1 8008cb4: 61bb str r3, [r7, #24] 8008cb6: 69ba ldr r2, [r7, #24] 8008cb8: 693b ldr r3, [r7, #16] 8008cba: 429a cmp r2, r3 8008cbc: d3e2 bcc.n 8008c84 } } return HAL_OK; 8008cbe: 2300 movs r3, #0 } 8008cc0: 4618 mov r0, r3 8008cc2: 3724 adds r7, #36 @ 0x24 8008cc4: 46bd mov sp, r7 8008cc6: f85d 7b04 ldr.w r7, [sp], #4 8008cca: 4770 bx lr 08008ccc : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 8008ccc: b480 push {r7} 8008cce: b08b sub sp, #44 @ 0x2c 8008cd0: af00 add r7, sp, #0 8008cd2: 60f8 str r0, [r7, #12] 8008cd4: 60b9 str r1, [r7, #8] 8008cd6: 4613 mov r3, r2 8008cd8: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 8008cda: 68fb ldr r3, [r7, #12] 8008cdc: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 8008cde: 68bb ldr r3, [r7, #8] 8008ce0: 627b str r3, [r7, #36] @ 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 8008ce2: 88fb ldrh r3, [r7, #6] 8008ce4: 089b lsrs r3, r3, #2 8008ce6: b29b uxth r3, r3 8008ce8: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 8008cea: 88fb ldrh r3, [r7, #6] 8008cec: f003 0303 and.w r3, r3, #3 8008cf0: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 8008cf2: 2300 movs r3, #0 8008cf4: 623b str r3, [r7, #32] 8008cf6: e014 b.n 8008d22 { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 8008cf8: 69bb ldr r3, [r7, #24] 8008cfa: f503 5380 add.w r3, r3, #4096 @ 0x1000 8008cfe: 681a ldr r2, [r3, #0] 8008d00: 6a7b ldr r3, [r7, #36] @ 0x24 8008d02: 601a str r2, [r3, #0] pDest++; 8008d04: 6a7b ldr r3, [r7, #36] @ 0x24 8008d06: 3301 adds r3, #1 8008d08: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008d0a: 6a7b ldr r3, [r7, #36] @ 0x24 8008d0c: 3301 adds r3, #1 8008d0e: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008d10: 6a7b ldr r3, [r7, #36] @ 0x24 8008d12: 3301 adds r3, #1 8008d14: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008d16: 6a7b ldr r3, [r7, #36] @ 0x24 8008d18: 3301 adds r3, #1 8008d1a: 627b str r3, [r7, #36] @ 0x24 for (i = 0U; i < count32b; i++) 8008d1c: 6a3b ldr r3, [r7, #32] 8008d1e: 3301 adds r3, #1 8008d20: 623b str r3, [r7, #32] 8008d22: 6a3a ldr r2, [r7, #32] 8008d24: 697b ldr r3, [r7, #20] 8008d26: 429a cmp r2, r3 8008d28: d3e6 bcc.n 8008cf8 } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 8008d2a: 8bfb ldrh r3, [r7, #30] 8008d2c: 2b00 cmp r3, #0 8008d2e: d01e beq.n 8008d6e { i = 0U; 8008d30: 2300 movs r3, #0 8008d32: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 8008d34: 69bb ldr r3, [r7, #24] 8008d36: f503 5380 add.w r3, r3, #4096 @ 0x1000 8008d3a: 461a mov r2, r3 8008d3c: f107 0310 add.w r3, r7, #16 8008d40: 6812 ldr r2, [r2, #0] 8008d42: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 8008d44: 693a ldr r2, [r7, #16] 8008d46: 6a3b ldr r3, [r7, #32] 8008d48: b2db uxtb r3, r3 8008d4a: 00db lsls r3, r3, #3 8008d4c: fa22 f303 lsr.w r3, r2, r3 8008d50: b2da uxtb r2, r3 8008d52: 6a7b ldr r3, [r7, #36] @ 0x24 8008d54: 701a strb r2, [r3, #0] i++; 8008d56: 6a3b ldr r3, [r7, #32] 8008d58: 3301 adds r3, #1 8008d5a: 623b str r3, [r7, #32] pDest++; 8008d5c: 6a7b ldr r3, [r7, #36] @ 0x24 8008d5e: 3301 adds r3, #1 8008d60: 627b str r3, [r7, #36] @ 0x24 remaining_bytes--; 8008d62: 8bfb ldrh r3, [r7, #30] 8008d64: 3b01 subs r3, #1 8008d66: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 8008d68: 8bfb ldrh r3, [r7, #30] 8008d6a: 2b00 cmp r3, #0 8008d6c: d1ea bne.n 8008d44 } return ((void *)pDest); 8008d6e: 6a7b ldr r3, [r7, #36] @ 0x24 } 8008d70: 4618 mov r0, r3 8008d72: 372c adds r7, #44 @ 0x2c 8008d74: 46bd mov sp, r7 8008d76: f85d 7b04 ldr.w r7, [sp], #4 8008d7a: 4770 bx lr 08008d7c : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8008d7c: b480 push {r7} 8008d7e: b085 sub sp, #20 8008d80: af00 add r7, sp, #0 8008d82: 6078 str r0, [r7, #4] 8008d84: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8008d86: 687b ldr r3, [r7, #4] 8008d88: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8008d8a: 683b ldr r3, [r7, #0] 8008d8c: 781b ldrb r3, [r3, #0] 8008d8e: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8008d90: 683b ldr r3, [r7, #0] 8008d92: 785b ldrb r3, [r3, #1] 8008d94: 2b01 cmp r3, #1 8008d96: d12c bne.n 8008df2 { if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) 8008d98: 68bb ldr r3, [r7, #8] 8008d9a: 015a lsls r2, r3, #5 8008d9c: 68fb ldr r3, [r7, #12] 8008d9e: 4413 add r3, r2 8008da0: f503 6310 add.w r3, r3, #2304 @ 0x900 8008da4: 681b ldr r3, [r3, #0] 8008da6: 2b00 cmp r3, #0 8008da8: db12 blt.n 8008dd0 8008daa: 68bb ldr r3, [r7, #8] 8008dac: 2b00 cmp r3, #0 8008dae: d00f beq.n 8008dd0 { USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 8008db0: 68bb ldr r3, [r7, #8] 8008db2: 015a lsls r2, r3, #5 8008db4: 68fb ldr r3, [r7, #12] 8008db6: 4413 add r3, r2 8008db8: f503 6310 add.w r3, r3, #2304 @ 0x900 8008dbc: 681b ldr r3, [r3, #0] 8008dbe: 68ba ldr r2, [r7, #8] 8008dc0: 0151 lsls r1, r2, #5 8008dc2: 68fa ldr r2, [r7, #12] 8008dc4: 440a add r2, r1 8008dc6: f502 6210 add.w r2, r2, #2304 @ 0x900 8008dca: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8008dce: 6013 str r3, [r2, #0] } USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 8008dd0: 68bb ldr r3, [r7, #8] 8008dd2: 015a lsls r2, r3, #5 8008dd4: 68fb ldr r3, [r7, #12] 8008dd6: 4413 add r3, r2 8008dd8: f503 6310 add.w r3, r3, #2304 @ 0x900 8008ddc: 681b ldr r3, [r3, #0] 8008dde: 68ba ldr r2, [r7, #8] 8008de0: 0151 lsls r1, r2, #5 8008de2: 68fa ldr r2, [r7, #12] 8008de4: 440a add r2, r1 8008de6: f502 6210 add.w r2, r2, #2304 @ 0x900 8008dea: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8008dee: 6013 str r3, [r2, #0] 8008df0: e02b b.n 8008e4a } else { if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) 8008df2: 68bb ldr r3, [r7, #8] 8008df4: 015a lsls r2, r3, #5 8008df6: 68fb ldr r3, [r7, #12] 8008df8: 4413 add r3, r2 8008dfa: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008dfe: 681b ldr r3, [r3, #0] 8008e00: 2b00 cmp r3, #0 8008e02: db12 blt.n 8008e2a 8008e04: 68bb ldr r3, [r7, #8] 8008e06: 2b00 cmp r3, #0 8008e08: d00f beq.n 8008e2a { USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 8008e0a: 68bb ldr r3, [r7, #8] 8008e0c: 015a lsls r2, r3, #5 8008e0e: 68fb ldr r3, [r7, #12] 8008e10: 4413 add r3, r2 8008e12: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008e16: 681b ldr r3, [r3, #0] 8008e18: 68ba ldr r2, [r7, #8] 8008e1a: 0151 lsls r1, r2, #5 8008e1c: 68fa ldr r2, [r7, #12] 8008e1e: 440a add r2, r1 8008e20: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008e24: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8008e28: 6013 str r3, [r2, #0] } USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 8008e2a: 68bb ldr r3, [r7, #8] 8008e2c: 015a lsls r2, r3, #5 8008e2e: 68fb ldr r3, [r7, #12] 8008e30: 4413 add r3, r2 8008e32: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008e36: 681b ldr r3, [r3, #0] 8008e38: 68ba ldr r2, [r7, #8] 8008e3a: 0151 lsls r1, r2, #5 8008e3c: 68fa ldr r2, [r7, #12] 8008e3e: 440a add r2, r1 8008e40: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008e44: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8008e48: 6013 str r3, [r2, #0] } return HAL_OK; 8008e4a: 2300 movs r3, #0 } 8008e4c: 4618 mov r0, r3 8008e4e: 3714 adds r7, #20 8008e50: 46bd mov sp, r7 8008e52: f85d 7b04 ldr.w r7, [sp], #4 8008e56: 4770 bx lr 08008e58 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8008e58: b480 push {r7} 8008e5a: b085 sub sp, #20 8008e5c: af00 add r7, sp, #0 8008e5e: 6078 str r0, [r7, #4] 8008e60: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8008e62: 687b ldr r3, [r7, #4] 8008e64: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8008e66: 683b ldr r3, [r7, #0] 8008e68: 781b ldrb r3, [r3, #0] 8008e6a: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8008e6c: 683b ldr r3, [r7, #0] 8008e6e: 785b ldrb r3, [r3, #1] 8008e70: 2b01 cmp r3, #1 8008e72: d128 bne.n 8008ec6 { USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 8008e74: 68bb ldr r3, [r7, #8] 8008e76: 015a lsls r2, r3, #5 8008e78: 68fb ldr r3, [r7, #12] 8008e7a: 4413 add r3, r2 8008e7c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008e80: 681b ldr r3, [r3, #0] 8008e82: 68ba ldr r2, [r7, #8] 8008e84: 0151 lsls r1, r2, #5 8008e86: 68fa ldr r2, [r7, #12] 8008e88: 440a add r2, r1 8008e8a: f502 6210 add.w r2, r2, #2304 @ 0x900 8008e8e: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8008e92: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8008e94: 683b ldr r3, [r7, #0] 8008e96: 791b ldrb r3, [r3, #4] 8008e98: 2b03 cmp r3, #3 8008e9a: d003 beq.n 8008ea4 8008e9c: 683b ldr r3, [r7, #0] 8008e9e: 791b ldrb r3, [r3, #4] 8008ea0: 2b02 cmp r3, #2 8008ea2: d138 bne.n 8008f16 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8008ea4: 68bb ldr r3, [r7, #8] 8008ea6: 015a lsls r2, r3, #5 8008ea8: 68fb ldr r3, [r7, #12] 8008eaa: 4413 add r3, r2 8008eac: f503 6310 add.w r3, r3, #2304 @ 0x900 8008eb0: 681b ldr r3, [r3, #0] 8008eb2: 68ba ldr r2, [r7, #8] 8008eb4: 0151 lsls r1, r2, #5 8008eb6: 68fa ldr r2, [r7, #12] 8008eb8: 440a add r2, r1 8008eba: f502 6210 add.w r2, r2, #2304 @ 0x900 8008ebe: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008ec2: 6013 str r3, [r2, #0] 8008ec4: e027 b.n 8008f16 } } else { USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 8008ec6: 68bb ldr r3, [r7, #8] 8008ec8: 015a lsls r2, r3, #5 8008eca: 68fb ldr r3, [r7, #12] 8008ecc: 4413 add r3, r2 8008ece: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008ed2: 681b ldr r3, [r3, #0] 8008ed4: 68ba ldr r2, [r7, #8] 8008ed6: 0151 lsls r1, r2, #5 8008ed8: 68fa ldr r2, [r7, #12] 8008eda: 440a add r2, r1 8008edc: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008ee0: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8008ee4: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8008ee6: 683b ldr r3, [r7, #0] 8008ee8: 791b ldrb r3, [r3, #4] 8008eea: 2b03 cmp r3, #3 8008eec: d003 beq.n 8008ef6 8008eee: 683b ldr r3, [r7, #0] 8008ef0: 791b ldrb r3, [r3, #4] 8008ef2: 2b02 cmp r3, #2 8008ef4: d10f bne.n 8008f16 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8008ef6: 68bb ldr r3, [r7, #8] 8008ef8: 015a lsls r2, r3, #5 8008efa: 68fb ldr r3, [r7, #12] 8008efc: 4413 add r3, r2 8008efe: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008f02: 681b ldr r3, [r3, #0] 8008f04: 68ba ldr r2, [r7, #8] 8008f06: 0151 lsls r1, r2, #5 8008f08: 68fa ldr r2, [r7, #12] 8008f0a: 440a add r2, r1 8008f0c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008f10: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008f14: 6013 str r3, [r2, #0] } } return HAL_OK; 8008f16: 2300 movs r3, #0 } 8008f18: 4618 mov r0, r3 8008f1a: 3714 adds r7, #20 8008f1c: 46bd mov sp, r7 8008f1e: f85d 7b04 ldr.w r7, [sp], #4 8008f22: 4770 bx lr 08008f24 : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { 8008f24: b480 push {r7} 8008f26: b085 sub sp, #20 8008f28: af00 add r7, sp, #0 8008f2a: 6078 str r0, [r7, #4] 8008f2c: 460b mov r3, r1 8008f2e: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008f30: 687b ldr r3, [r7, #4] 8008f32: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); 8008f34: 68fb ldr r3, [r7, #12] 8008f36: f503 6300 add.w r3, r3, #2048 @ 0x800 8008f3a: 681b ldr r3, [r3, #0] 8008f3c: 68fa ldr r2, [r7, #12] 8008f3e: f502 6200 add.w r2, r2, #2048 @ 0x800 8008f42: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 8008f46: 6013 str r3, [r2, #0] USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; 8008f48: 68fb ldr r3, [r7, #12] 8008f4a: f503 6300 add.w r3, r3, #2048 @ 0x800 8008f4e: 681a ldr r2, [r3, #0] 8008f50: 78fb ldrb r3, [r7, #3] 8008f52: 011b lsls r3, r3, #4 8008f54: f403 63fe and.w r3, r3, #2032 @ 0x7f0 8008f58: 68f9 ldr r1, [r7, #12] 8008f5a: f501 6100 add.w r1, r1, #2048 @ 0x800 8008f5e: 4313 orrs r3, r2 8008f60: 600b str r3, [r1, #0] return HAL_OK; 8008f62: 2300 movs r3, #0 } 8008f64: 4618 mov r0, r3 8008f66: 3714 adds r7, #20 8008f68: 46bd mov sp, r7 8008f6a: f85d 7b04 ldr.w r7, [sp], #4 8008f6e: 4770 bx lr 08008f70 : * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { 8008f70: b480 push {r7} 8008f72: b085 sub sp, #20 8008f74: af00 add r7, sp, #0 8008f76: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008f78: 687b ldr r3, [r7, #4] 8008f7a: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8008f7c: 68fb ldr r3, [r7, #12] 8008f7e: f503 6360 add.w r3, r3, #3584 @ 0xe00 8008f82: 681b ldr r3, [r3, #0] 8008f84: 68fa ldr r2, [r7, #12] 8008f86: f502 6260 add.w r2, r2, #3584 @ 0xe00 8008f8a: f023 0303 bic.w r3, r3, #3 8008f8e: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; 8008f90: 68fb ldr r3, [r7, #12] 8008f92: f503 6300 add.w r3, r3, #2048 @ 0x800 8008f96: 685b ldr r3, [r3, #4] 8008f98: 68fa ldr r2, [r7, #12] 8008f9a: f502 6200 add.w r2, r2, #2048 @ 0x800 8008f9e: f023 0302 bic.w r3, r3, #2 8008fa2: 6053 str r3, [r2, #4] return HAL_OK; 8008fa4: 2300 movs r3, #0 } 8008fa6: 4618 mov r0, r3 8008fa8: 3714 adds r7, #20 8008faa: 46bd mov sp, r7 8008fac: f85d 7b04 ldr.w r7, [sp], #4 8008fb0: 4770 bx lr 08008fb2 : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { 8008fb2: b480 push {r7} 8008fb4: b085 sub sp, #20 8008fb6: af00 add r7, sp, #0 8008fb8: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008fba: 687b ldr r3, [r7, #4] 8008fbc: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8008fbe: 68fb ldr r3, [r7, #12] 8008fc0: f503 6360 add.w r3, r3, #3584 @ 0xe00 8008fc4: 681b ldr r3, [r3, #0] 8008fc6: 68fa ldr r2, [r7, #12] 8008fc8: f502 6260 add.w r2, r2, #3584 @ 0xe00 8008fcc: f023 0303 bic.w r3, r3, #3 8008fd0: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8008fd2: 68fb ldr r3, [r7, #12] 8008fd4: f503 6300 add.w r3, r3, #2048 @ 0x800 8008fd8: 685b ldr r3, [r3, #4] 8008fda: 68fa ldr r2, [r7, #12] 8008fdc: f502 6200 add.w r2, r2, #2048 @ 0x800 8008fe0: f043 0302 orr.w r3, r3, #2 8008fe4: 6053 str r3, [r2, #4] return HAL_OK; 8008fe6: 2300 movs r3, #0 } 8008fe8: 4618 mov r0, r3 8008fea: 3714 adds r7, #20 8008fec: 46bd mov sp, r7 8008fee: f85d 7b04 ldr.w r7, [sp], #4 8008ff2: 4770 bx lr 08008ff4 : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { 8008ff4: b480 push {r7} 8008ff6: b085 sub sp, #20 8008ff8: af00 add r7, sp, #0 8008ffa: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 8008ffc: 687b ldr r3, [r7, #4] 8008ffe: 695b ldr r3, [r3, #20] 8009000: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 8009002: 687b ldr r3, [r7, #4] 8009004: 699b ldr r3, [r3, #24] 8009006: 68fa ldr r2, [r7, #12] 8009008: 4013 ands r3, r2 800900a: 60fb str r3, [r7, #12] return tmpreg; 800900c: 68fb ldr r3, [r7, #12] } 800900e: 4618 mov r0, r3 8009010: 3714 adds r7, #20 8009012: 46bd mov sp, r7 8009014: f85d 7b04 ldr.w r7, [sp], #4 8009018: 4770 bx lr 0800901a : * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device * @retval USB Device OUT EP interrupt status */ uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 800901a: b480 push {r7} 800901c: b085 sub sp, #20 800901e: af00 add r7, sp, #0 8009020: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8009022: 687b ldr r3, [r7, #4] 8009024: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8009026: 68fb ldr r3, [r7, #12] 8009028: f503 6300 add.w r3, r3, #2048 @ 0x800 800902c: 699b ldr r3, [r3, #24] 800902e: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 8009030: 68fb ldr r3, [r7, #12] 8009032: f503 6300 add.w r3, r3, #2048 @ 0x800 8009036: 69db ldr r3, [r3, #28] 8009038: 68ba ldr r2, [r7, #8] 800903a: 4013 ands r3, r2 800903c: 60bb str r3, [r7, #8] return ((tmpreg & 0xffff0000U) >> 16); 800903e: 68bb ldr r3, [r7, #8] 8009040: 0c1b lsrs r3, r3, #16 } 8009042: 4618 mov r0, r3 8009044: 3714 adds r7, #20 8009046: 46bd mov sp, r7 8009048: f85d 7b04 ldr.w r7, [sp], #4 800904c: 4770 bx lr 0800904e : * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device * @retval USB Device IN EP interrupt status */ uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 800904e: b480 push {r7} 8009050: b085 sub sp, #20 8009052: af00 add r7, sp, #0 8009054: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8009056: 687b ldr r3, [r7, #4] 8009058: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 800905a: 68fb ldr r3, [r7, #12] 800905c: f503 6300 add.w r3, r3, #2048 @ 0x800 8009060: 699b ldr r3, [r3, #24] 8009062: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 8009064: 68fb ldr r3, [r7, #12] 8009066: f503 6300 add.w r3, r3, #2048 @ 0x800 800906a: 69db ldr r3, [r3, #28] 800906c: 68ba ldr r2, [r7, #8] 800906e: 4013 ands r3, r2 8009070: 60bb str r3, [r7, #8] return ((tmpreg & 0xFFFFU)); 8009072: 68bb ldr r3, [r7, #8] 8009074: b29b uxth r3, r3 } 8009076: 4618 mov r0, r3 8009078: 3714 adds r7, #20 800907a: 46bd mov sp, r7 800907c: f85d 7b04 ldr.w r7, [sp], #4 8009080: 4770 bx lr 08009082 : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 8009082: b480 push {r7} 8009084: b085 sub sp, #20 8009086: af00 add r7, sp, #0 8009088: 6078 str r0, [r7, #4] 800908a: 460b mov r3, r1 800908c: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 800908e: 687b ldr r3, [r7, #4] 8009090: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; 8009092: 78fb ldrb r3, [r7, #3] 8009094: 015a lsls r2, r3, #5 8009096: 68fb ldr r3, [r7, #12] 8009098: 4413 add r3, r2 800909a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800909e: 689b ldr r3, [r3, #8] 80090a0: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DOEPMSK; 80090a2: 68fb ldr r3, [r7, #12] 80090a4: f503 6300 add.w r3, r3, #2048 @ 0x800 80090a8: 695b ldr r3, [r3, #20] 80090aa: 68ba ldr r2, [r7, #8] 80090ac: 4013 ands r3, r2 80090ae: 60bb str r3, [r7, #8] return tmpreg; 80090b0: 68bb ldr r3, [r7, #8] } 80090b2: 4618 mov r0, r3 80090b4: 3714 adds r7, #20 80090b6: 46bd mov sp, r7 80090b8: f85d 7b04 ldr.w r7, [sp], #4 80090bc: 4770 bx lr 080090be : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 80090be: b480 push {r7} 80090c0: b087 sub sp, #28 80090c2: af00 add r7, sp, #0 80090c4: 6078 str r0, [r7, #4] 80090c6: 460b mov r3, r1 80090c8: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80090ca: 687b ldr r3, [r7, #4] 80090cc: 617b str r3, [r7, #20] uint32_t tmpreg; uint32_t msk; uint32_t emp; msk = USBx_DEVICE->DIEPMSK; 80090ce: 697b ldr r3, [r7, #20] 80090d0: f503 6300 add.w r3, r3, #2048 @ 0x800 80090d4: 691b ldr r3, [r3, #16] 80090d6: 613b str r3, [r7, #16] emp = USBx_DEVICE->DIEPEMPMSK; 80090d8: 697b ldr r3, [r7, #20] 80090da: f503 6300 add.w r3, r3, #2048 @ 0x800 80090de: 6b5b ldr r3, [r3, #52] @ 0x34 80090e0: 60fb str r3, [r7, #12] msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; 80090e2: 78fb ldrb r3, [r7, #3] 80090e4: f003 030f and.w r3, r3, #15 80090e8: 68fa ldr r2, [r7, #12] 80090ea: fa22 f303 lsr.w r3, r2, r3 80090ee: 01db lsls r3, r3, #7 80090f0: b2db uxtb r3, r3 80090f2: 693a ldr r2, [r7, #16] 80090f4: 4313 orrs r3, r2 80090f6: 613b str r3, [r7, #16] tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; 80090f8: 78fb ldrb r3, [r7, #3] 80090fa: 015a lsls r2, r3, #5 80090fc: 697b ldr r3, [r7, #20] 80090fe: 4413 add r3, r2 8009100: f503 6310 add.w r3, r3, #2304 @ 0x900 8009104: 689b ldr r3, [r3, #8] 8009106: 693a ldr r2, [r7, #16] 8009108: 4013 ands r3, r2 800910a: 60bb str r3, [r7, #8] return tmpreg; 800910c: 68bb ldr r3, [r7, #8] } 800910e: 4618 mov r0, r3 8009110: 371c adds r7, #28 8009112: 46bd mov sp, r7 8009114: f85d 7b04 ldr.w r7, [sp], #4 8009118: 4770 bx lr 0800911a : * This parameter can be one of these values: * 1 : Host * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { 800911a: b480 push {r7} 800911c: b083 sub sp, #12 800911e: af00 add r7, sp, #0 8009120: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 8009122: 687b ldr r3, [r7, #4] 8009124: 695b ldr r3, [r3, #20] 8009126: f003 0301 and.w r3, r3, #1 } 800912a: 4618 mov r0, r3 800912c: 370c adds r7, #12 800912e: 46bd mov sp, r7 8009130: f85d 7b04 ldr.w r7, [sp], #4 8009134: 4770 bx lr 08009136 : * @brief Activate EP0 for Setup transactions * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { 8009136: b480 push {r7} 8009138: b085 sub sp, #20 800913a: af00 add r7, sp, #0 800913c: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800913e: 687b ldr r3, [r7, #4] 8009140: 60fb str r3, [r7, #12] /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 8009142: 68fb ldr r3, [r7, #12] 8009144: f503 6310 add.w r3, r3, #2304 @ 0x900 8009148: 681b ldr r3, [r3, #0] 800914a: 68fa ldr r2, [r7, #12] 800914c: f502 6210 add.w r2, r2, #2304 @ 0x900 8009150: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 8009154: f023 0307 bic.w r3, r3, #7 8009158: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 800915a: 68fb ldr r3, [r7, #12] 800915c: f503 6300 add.w r3, r3, #2048 @ 0x800 8009160: 685b ldr r3, [r3, #4] 8009162: 68fa ldr r2, [r7, #12] 8009164: f502 6200 add.w r2, r2, #2048 @ 0x800 8009168: f443 7380 orr.w r3, r3, #256 @ 0x100 800916c: 6053 str r3, [r2, #4] return HAL_OK; 800916e: 2300 movs r3, #0 } 8009170: 4618 mov r0, r3 8009172: 3714 adds r7, #20 8009174: 46bd mov sp, r7 8009176: f85d 7b04 ldr.w r7, [sp], #4 800917a: 4770 bx lr 0800917c : * 1 : DMA feature used * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { 800917c: b480 push {r7} 800917e: b087 sub sp, #28 8009180: af00 add r7, sp, #0 8009182: 60f8 str r0, [r7, #12] 8009184: 460b mov r3, r1 8009186: 607a str r2, [r7, #4] 8009188: 72fb strb r3, [r7, #11] uint32_t USBx_BASE = (uint32_t)USBx; 800918a: 68fb ldr r3, [r7, #12] 800918c: 617b str r3, [r7, #20] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 800918e: 68fb ldr r3, [r7, #12] 8009190: 333c adds r3, #60 @ 0x3c 8009192: 3304 adds r3, #4 8009194: 681b ldr r3, [r3, #0] 8009196: 613b str r3, [r7, #16] if (gSNPSiD > USB_OTG_CORE_ID_300A) 8009198: 693b ldr r3, [r7, #16] 800919a: 4a26 ldr r2, [pc, #152] @ (8009234 ) 800919c: 4293 cmp r3, r2 800919e: d90a bls.n 80091b6 { if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80091a0: 697b ldr r3, [r7, #20] 80091a2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80091a6: 681b ldr r3, [r3, #0] 80091a8: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80091ac: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80091b0: d101 bne.n 80091b6 { return HAL_OK; 80091b2: 2300 movs r3, #0 80091b4: e037 b.n 8009226 } } USBx_OUTEP(0U)->DOEPTSIZ = 0U; 80091b6: 697b ldr r3, [r7, #20] 80091b8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80091bc: 461a mov r2, r3 80091be: 2300 movs r3, #0 80091c0: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 80091c2: 697b ldr r3, [r7, #20] 80091c4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80091c8: 691b ldr r3, [r3, #16] 80091ca: 697a ldr r2, [r7, #20] 80091cc: f502 6230 add.w r2, r2, #2816 @ 0xb00 80091d0: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80091d4: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); 80091d6: 697b ldr r3, [r7, #20] 80091d8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80091dc: 691b ldr r3, [r3, #16] 80091de: 697a ldr r2, [r7, #20] 80091e0: f502 6230 add.w r2, r2, #2816 @ 0xb00 80091e4: f043 0318 orr.w r3, r3, #24 80091e8: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 80091ea: 697b ldr r3, [r7, #20] 80091ec: f503 6330 add.w r3, r3, #2816 @ 0xb00 80091f0: 691b ldr r3, [r3, #16] 80091f2: 697a ldr r2, [r7, #20] 80091f4: f502 6230 add.w r2, r2, #2816 @ 0xb00 80091f8: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000 80091fc: 6113 str r3, [r2, #16] if (dma == 1U) 80091fe: 7afb ldrb r3, [r7, #11] 8009200: 2b01 cmp r3, #1 8009202: d10f bne.n 8009224 { USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; 8009204: 697b ldr r3, [r7, #20] 8009206: f503 6330 add.w r3, r3, #2816 @ 0xb00 800920a: 461a mov r2, r3 800920c: 687b ldr r3, [r7, #4] 800920e: 6153 str r3, [r2, #20] /* EP enable */ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; 8009210: 697b ldr r3, [r7, #20] 8009212: f503 6330 add.w r3, r3, #2816 @ 0xb00 8009216: 681b ldr r3, [r3, #0] 8009218: 697a ldr r2, [r7, #20] 800921a: f502 6230 add.w r2, r2, #2816 @ 0xb00 800921e: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000 8009222: 6013 str r3, [r2, #0] } return HAL_OK; 8009224: 2300 movs r3, #0 } 8009226: 4618 mov r0, r3 8009228: 371c adds r7, #28 800922a: 46bd mov sp, r7 800922c: f85d 7b04 ldr.w r7, [sp], #4 8009230: 4770 bx lr 8009232: bf00 nop 8009234: 4f54300a .word 0x4f54300a 08009238 : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 8009238: b480 push {r7} 800923a: b085 sub sp, #20 800923c: af00 add r7, sp, #0 800923e: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8009240: 2300 movs r3, #0 8009242: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8009244: 68fb ldr r3, [r7, #12] 8009246: 3301 adds r3, #1 8009248: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800924a: 68fb ldr r3, [r7, #12] 800924c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8009250: d901 bls.n 8009256 { return HAL_TIMEOUT; 8009252: 2303 movs r3, #3 8009254: e022 b.n 800929c } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8009256: 687b ldr r3, [r7, #4] 8009258: 691b ldr r3, [r3, #16] 800925a: 2b00 cmp r3, #0 800925c: daf2 bge.n 8009244 count = 10U; 800925e: 230a movs r3, #10 8009260: 60fb str r3, [r7, #12] /* few cycles before setting core reset */ while (count > 0U) 8009262: e002 b.n 800926a { count--; 8009264: 68fb ldr r3, [r7, #12] 8009266: 3b01 subs r3, #1 8009268: 60fb str r3, [r7, #12] while (count > 0U) 800926a: 68fb ldr r3, [r7, #12] 800926c: 2b00 cmp r3, #0 800926e: d1f9 bne.n 8009264 } /* Core Soft Reset */ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 8009270: 687b ldr r3, [r7, #4] 8009272: 691b ldr r3, [r3, #16] 8009274: f043 0201 orr.w r2, r3, #1 8009278: 687b ldr r3, [r7, #4] 800927a: 611a str r2, [r3, #16] do { count++; 800927c: 68fb ldr r3, [r7, #12] 800927e: 3301 adds r3, #1 8009280: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8009282: 68fb ldr r3, [r7, #12] 8009284: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8009288: d901 bls.n 800928e { return HAL_TIMEOUT; 800928a: 2303 movs r3, #3 800928c: e006 b.n 800929c } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 800928e: 687b ldr r3, [r7, #4] 8009290: 691b ldr r3, [r3, #16] 8009292: f003 0301 and.w r3, r3, #1 8009296: 2b01 cmp r3, #1 8009298: d0f0 beq.n 800927c return HAL_OK; 800929a: 2300 movs r3, #0 } 800929c: 4618 mov r0, r3 800929e: 3714 adds r7, #20 80092a0: 46bd mov sp, r7 80092a2: f85d 7b04 ldr.w r7, [sp], #4 80092a6: 4770 bx lr 080092a8 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80092a8: b580 push {r7, lr} 80092aa: b084 sub sp, #16 80092ac: af00 add r7, sp, #0 80092ae: 6078 str r0, [r7, #4] 80092b0: 460b mov r3, r1 80092b2: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_HID_HandleTypeDef *hhid; hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); 80092b4: 2010 movs r0, #16 80092b6: f002 f9e3 bl 800b680 80092ba: 60f8 str r0, [r7, #12] if (hhid == NULL) 80092bc: 68fb ldr r3, [r7, #12] 80092be: 2b00 cmp r3, #0 80092c0: d109 bne.n 80092d6 { pdev->pClassDataCmsit[pdev->classId] = NULL; 80092c2: 687b ldr r3, [r7, #4] 80092c4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80092c8: 687b ldr r3, [r7, #4] 80092ca: 32b0 adds r2, #176 @ 0xb0 80092cc: 2100 movs r1, #0 80092ce: f843 1022 str.w r1, [r3, r2, lsl #2] return (uint8_t)USBD_EMEM; 80092d2: 2302 movs r3, #2 80092d4: e048 b.n 8009368 } pdev->pClassDataCmsit[pdev->classId] = (void *)hhid; 80092d6: 687b ldr r3, [r7, #4] 80092d8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80092dc: 687b ldr r3, [r7, #4] 80092de: 32b0 adds r2, #176 @ 0xb0 80092e0: 68f9 ldr r1, [r7, #12] 80092e2: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; 80092e6: 687b ldr r3, [r7, #4] 80092e8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80092ec: 687b ldr r3, [r7, #4] 80092ee: 32b0 adds r2, #176 @ 0xb0 80092f0: f853 2022 ldr.w r2, [r3, r2, lsl #2] 80092f4: 687b ldr r3, [r7, #4] 80092f6: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_speed == USBD_SPEED_HIGH) 80092fa: 687b ldr r3, [r7, #4] 80092fc: 7c1b ldrb r3, [r3, #16] 80092fe: 2b00 cmp r3, #0 8009300: d10d bne.n 800931e { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL; 8009302: 4b1b ldr r3, [pc, #108] @ (8009370 ) 8009304: 781b ldrb r3, [r3, #0] 8009306: f003 020f and.w r2, r3, #15 800930a: 6879 ldr r1, [r7, #4] 800930c: 4613 mov r3, r2 800930e: 009b lsls r3, r3, #2 8009310: 4413 add r3, r2 8009312: 009b lsls r3, r3, #2 8009314: 440b add r3, r1 8009316: 331c adds r3, #28 8009318: 2207 movs r2, #7 800931a: 601a str r2, [r3, #0] 800931c: e00c b.n 8009338 } else /* LOW and FULL-speed endpoints */ { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL; 800931e: 4b14 ldr r3, [pc, #80] @ (8009370 ) 8009320: 781b ldrb r3, [r3, #0] 8009322: f003 020f and.w r2, r3, #15 8009326: 6879 ldr r1, [r7, #4] 8009328: 4613 mov r3, r2 800932a: 009b lsls r3, r3, #2 800932c: 4413 add r3, r2 800932e: 009b lsls r3, r3, #2 8009330: 440b add r3, r1 8009332: 331c adds r3, #28 8009334: 220a movs r2, #10 8009336: 601a str r2, [r3, #0] } /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); 8009338: 4b0d ldr r3, [pc, #52] @ (8009370 ) 800933a: 7819 ldrb r1, [r3, #0] 800933c: 230e movs r3, #14 800933e: 2203 movs r2, #3 8009340: 6878 ldr r0, [r7, #4] 8009342: f002 f83e bl 800b3c2 pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U; 8009346: 4b0a ldr r3, [pc, #40] @ (8009370 ) 8009348: 781b ldrb r3, [r3, #0] 800934a: f003 020f and.w r2, r3, #15 800934e: 6879 ldr r1, [r7, #4] 8009350: 4613 mov r3, r2 8009352: 009b lsls r3, r3, #2 8009354: 4413 add r3, r2 8009356: 009b lsls r3, r3, #2 8009358: 440b add r3, r1 800935a: 3323 adds r3, #35 @ 0x23 800935c: 2201 movs r2, #1 800935e: 701a strb r2, [r3, #0] hhid->state = USBD_HID_IDLE; 8009360: 68fb ldr r3, [r7, #12] 8009362: 2200 movs r2, #0 8009364: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 8009366: 2300 movs r3, #0 } 8009368: 4618 mov r0, r3 800936a: 3710 adds r7, #16 800936c: 46bd mov sp, r7 800936e: bd80 pop {r7, pc} 8009370: 2000013d .word 0x2000013d 08009374 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8009374: b580 push {r7, lr} 8009376: b082 sub sp, #8 8009378: af00 add r7, sp, #0 800937a: 6078 str r0, [r7, #4] 800937c: 460b mov r3, r1 800937e: 70fb strb r3, [r7, #3] /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ /* Close HID EPs */ (void)USBD_LL_CloseEP(pdev, HIDInEpAdd); 8009380: 4b1f ldr r3, [pc, #124] @ (8009400 ) 8009382: 781b ldrb r3, [r3, #0] 8009384: 4619 mov r1, r3 8009386: 6878 ldr r0, [r7, #4] 8009388: f002 f841 bl 800b40e pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U; 800938c: 4b1c ldr r3, [pc, #112] @ (8009400 ) 800938e: 781b ldrb r3, [r3, #0] 8009390: f003 020f and.w r2, r3, #15 8009394: 6879 ldr r1, [r7, #4] 8009396: 4613 mov r3, r2 8009398: 009b lsls r3, r3, #2 800939a: 4413 add r3, r2 800939c: 009b lsls r3, r3, #2 800939e: 440b add r3, r1 80093a0: 3323 adds r3, #35 @ 0x23 80093a2: 2200 movs r2, #0 80093a4: 701a strb r2, [r3, #0] pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U; 80093a6: 4b16 ldr r3, [pc, #88] @ (8009400 ) 80093a8: 781b ldrb r3, [r3, #0] 80093aa: f003 020f and.w r2, r3, #15 80093ae: 6879 ldr r1, [r7, #4] 80093b0: 4613 mov r3, r2 80093b2: 009b lsls r3, r3, #2 80093b4: 4413 add r3, r2 80093b6: 009b lsls r3, r3, #2 80093b8: 440b add r3, r1 80093ba: 331c adds r3, #28 80093bc: 2200 movs r2, #0 80093be: 601a str r2, [r3, #0] /* Free allocated memory */ if (pdev->pClassDataCmsit[pdev->classId] != NULL) 80093c0: 687b ldr r3, [r7, #4] 80093c2: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80093c6: 687b ldr r3, [r7, #4] 80093c8: 32b0 adds r2, #176 @ 0xb0 80093ca: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80093ce: 2b00 cmp r3, #0 80093d0: d011 beq.n 80093f6 { (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); 80093d2: 687b ldr r3, [r7, #4] 80093d4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80093d8: 687b ldr r3, [r7, #4] 80093da: 32b0 adds r2, #176 @ 0xb0 80093dc: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80093e0: 4618 mov r0, r3 80093e2: f002 f95b bl 800b69c pdev->pClassDataCmsit[pdev->classId] = NULL; 80093e6: 687b ldr r3, [r7, #4] 80093e8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80093ec: 687b ldr r3, [r7, #4] 80093ee: 32b0 adds r2, #176 @ 0xb0 80093f0: 2100 movs r1, #0 80093f2: f843 1022 str.w r1, [r3, r2, lsl #2] } return (uint8_t)USBD_OK; 80093f6: 2300 movs r3, #0 } 80093f8: 4618 mov r0, r3 80093fa: 3708 adds r7, #8 80093fc: 46bd mov sp, r7 80093fe: bd80 pop {r7, pc} 8009400: 2000013d .word 0x2000013d 08009404 : * @param pdev: instance * @param req: usb requests * @retval status */ static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009404: b580 push {r7, lr} 8009406: b086 sub sp, #24 8009408: af00 add r7, sp, #0 800940a: 6078 str r0, [r7, #4] 800940c: 6039 str r1, [r7, #0] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 800940e: 687b ldr r3, [r7, #4] 8009410: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009414: 687b ldr r3, [r7, #4] 8009416: 32b0 adds r2, #176 @ 0xb0 8009418: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800941c: 60fb str r3, [r7, #12] USBD_StatusTypeDef ret = USBD_OK; 800941e: 2300 movs r3, #0 8009420: 75fb strb r3, [r7, #23] uint16_t len; uint8_t *pbuf; uint16_t status_info = 0U; 8009422: 2300 movs r3, #0 8009424: 817b strh r3, [r7, #10] if (hhid == NULL) 8009426: 68fb ldr r3, [r7, #12] 8009428: 2b00 cmp r3, #0 800942a: d101 bne.n 8009430 { return (uint8_t)USBD_FAIL; 800942c: 2303 movs r3, #3 800942e: e0e8 b.n 8009602 } switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009430: 683b ldr r3, [r7, #0] 8009432: 781b ldrb r3, [r3, #0] 8009434: f003 0360 and.w r3, r3, #96 @ 0x60 8009438: 2b00 cmp r3, #0 800943a: d046 beq.n 80094ca 800943c: 2b20 cmp r3, #32 800943e: f040 80d8 bne.w 80095f2 { case USB_REQ_TYPE_CLASS : switch (req->bRequest) 8009442: 683b ldr r3, [r7, #0] 8009444: 785b ldrb r3, [r3, #1] 8009446: 3b02 subs r3, #2 8009448: 2b09 cmp r3, #9 800944a: d836 bhi.n 80094ba 800944c: a201 add r2, pc, #4 @ (adr r2, 8009454 ) 800944e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009452: bf00 nop 8009454: 080094ab .word 0x080094ab 8009458: 0800948b .word 0x0800948b 800945c: 080094bb .word 0x080094bb 8009460: 080094bb .word 0x080094bb 8009464: 080094bb .word 0x080094bb 8009468: 080094bb .word 0x080094bb 800946c: 080094bb .word 0x080094bb 8009470: 080094bb .word 0x080094bb 8009474: 08009499 .word 0x08009499 8009478: 0800947d .word 0x0800947d { case USBD_HID_REQ_SET_PROTOCOL: hhid->Protocol = (uint8_t)(req->wValue); 800947c: 683b ldr r3, [r7, #0] 800947e: 885b ldrh r3, [r3, #2] 8009480: b2db uxtb r3, r3 8009482: 461a mov r2, r3 8009484: 68fb ldr r3, [r7, #12] 8009486: 601a str r2, [r3, #0] break; 8009488: e01e b.n 80094c8 case USBD_HID_REQ_GET_PROTOCOL: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); 800948a: 68fb ldr r3, [r7, #12] 800948c: 2201 movs r2, #1 800948e: 4619 mov r1, r3 8009490: 6878 ldr r0, [r7, #4] 8009492: f001 fc25 bl 800ace0 break; 8009496: e017 b.n 80094c8 case USBD_HID_REQ_SET_IDLE: hhid->IdleState = (uint8_t)(req->wValue >> 8); 8009498: 683b ldr r3, [r7, #0] 800949a: 885b ldrh r3, [r3, #2] 800949c: 0a1b lsrs r3, r3, #8 800949e: b29b uxth r3, r3 80094a0: b2db uxtb r3, r3 80094a2: 461a mov r2, r3 80094a4: 68fb ldr r3, [r7, #12] 80094a6: 605a str r2, [r3, #4] break; 80094a8: e00e b.n 80094c8 case USBD_HID_REQ_GET_IDLE: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); 80094aa: 68fb ldr r3, [r7, #12] 80094ac: 3304 adds r3, #4 80094ae: 2201 movs r2, #1 80094b0: 4619 mov r1, r3 80094b2: 6878 ldr r0, [r7, #4] 80094b4: f001 fc14 bl 800ace0 break; 80094b8: e006 b.n 80094c8 default: USBD_CtlError(pdev, req); 80094ba: 6839 ldr r1, [r7, #0] 80094bc: 6878 ldr r0, [r7, #4] 80094be: f001 fb92 bl 800abe6 ret = USBD_FAIL; 80094c2: 2303 movs r3, #3 80094c4: 75fb strb r3, [r7, #23] break; 80094c6: bf00 nop } break; 80094c8: e09a b.n 8009600 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80094ca: 683b ldr r3, [r7, #0] 80094cc: 785b ldrb r3, [r3, #1] 80094ce: 2b0b cmp r3, #11 80094d0: f200 8086 bhi.w 80095e0 80094d4: a201 add r2, pc, #4 @ (adr r2, 80094dc ) 80094d6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80094da: bf00 nop 80094dc: 0800950d .word 0x0800950d 80094e0: 080095ef .word 0x080095ef 80094e4: 080095e1 .word 0x080095e1 80094e8: 080095e1 .word 0x080095e1 80094ec: 080095e1 .word 0x080095e1 80094f0: 080095e1 .word 0x080095e1 80094f4: 08009537 .word 0x08009537 80094f8: 080095e1 .word 0x080095e1 80094fc: 080095e1 .word 0x080095e1 8009500: 080095e1 .word 0x080095e1 8009504: 0800958f .word 0x0800958f 8009508: 080095b9 .word 0x080095b9 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 800950c: 687b ldr r3, [r7, #4] 800950e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009512: b2db uxtb r3, r3 8009514: 2b03 cmp r3, #3 8009516: d107 bne.n 8009528 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 8009518: f107 030a add.w r3, r7, #10 800951c: 2202 movs r2, #2 800951e: 4619 mov r1, r3 8009520: 6878 ldr r0, [r7, #4] 8009522: f001 fbdd bl 800ace0 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8009526: e063 b.n 80095f0 USBD_CtlError(pdev, req); 8009528: 6839 ldr r1, [r7, #0] 800952a: 6878 ldr r0, [r7, #4] 800952c: f001 fb5b bl 800abe6 ret = USBD_FAIL; 8009530: 2303 movs r3, #3 8009532: 75fb strb r3, [r7, #23] break; 8009534: e05c b.n 80095f0 case USB_REQ_GET_DESCRIPTOR: if ((req->wValue >> 8) == HID_REPORT_DESC) 8009536: 683b ldr r3, [r7, #0] 8009538: 885b ldrh r3, [r3, #2] 800953a: 0a1b lsrs r3, r3, #8 800953c: b29b uxth r3, r3 800953e: 2b22 cmp r3, #34 @ 0x22 8009540: d108 bne.n 8009554 { len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); 8009542: 683b ldr r3, [r7, #0] 8009544: 88db ldrh r3, [r3, #6] 8009546: 2b2d cmp r3, #45 @ 0x2d 8009548: bf28 it cs 800954a: 232d movcs r3, #45 @ 0x2d 800954c: 82bb strh r3, [r7, #20] pbuf = HID_MOUSE_ReportDesc; 800954e: 4b2f ldr r3, [pc, #188] @ (800960c ) 8009550: 613b str r3, [r7, #16] 8009552: e015 b.n 8009580 } else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) 8009554: 683b ldr r3, [r7, #0] 8009556: 885b ldrh r3, [r3, #2] 8009558: 0a1b lsrs r3, r3, #8 800955a: b29b uxth r3, r3 800955c: 2b21 cmp r3, #33 @ 0x21 800955e: d108 bne.n 8009572 { pbuf = USBD_HID_Desc; 8009560: 4b2b ldr r3, [pc, #172] @ (8009610 ) 8009562: 613b str r3, [r7, #16] len = MIN(USB_HID_DESC_SIZ, req->wLength); 8009564: 683b ldr r3, [r7, #0] 8009566: 88db ldrh r3, [r3, #6] 8009568: 2b09 cmp r3, #9 800956a: bf28 it cs 800956c: 2309 movcs r3, #9 800956e: 82bb strh r3, [r7, #20] 8009570: e006 b.n 8009580 } else { USBD_CtlError(pdev, req); 8009572: 6839 ldr r1, [r7, #0] 8009574: 6878 ldr r0, [r7, #4] 8009576: f001 fb36 bl 800abe6 ret = USBD_FAIL; 800957a: 2303 movs r3, #3 800957c: 75fb strb r3, [r7, #23] break; 800957e: e037 b.n 80095f0 } (void)USBD_CtlSendData(pdev, pbuf, len); 8009580: 8abb ldrh r3, [r7, #20] 8009582: 461a mov r2, r3 8009584: 6939 ldr r1, [r7, #16] 8009586: 6878 ldr r0, [r7, #4] 8009588: f001 fbaa bl 800ace0 break; 800958c: e030 b.n 80095f0 case USB_REQ_GET_INTERFACE : if (pdev->dev_state == USBD_STATE_CONFIGURED) 800958e: 687b ldr r3, [r7, #4] 8009590: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009594: b2db uxtb r3, r3 8009596: 2b03 cmp r3, #3 8009598: d107 bne.n 80095aa { (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); 800959a: 68fb ldr r3, [r7, #12] 800959c: 3308 adds r3, #8 800959e: 2201 movs r2, #1 80095a0: 4619 mov r1, r3 80095a2: 6878 ldr r0, [r7, #4] 80095a4: f001 fb9c bl 800ace0 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 80095a8: e022 b.n 80095f0 USBD_CtlError(pdev, req); 80095aa: 6839 ldr r1, [r7, #0] 80095ac: 6878 ldr r0, [r7, #4] 80095ae: f001 fb1a bl 800abe6 ret = USBD_FAIL; 80095b2: 2303 movs r3, #3 80095b4: 75fb strb r3, [r7, #23] break; 80095b6: e01b b.n 80095f0 case USB_REQ_SET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 80095b8: 687b ldr r3, [r7, #4] 80095ba: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80095be: b2db uxtb r3, r3 80095c0: 2b03 cmp r3, #3 80095c2: d106 bne.n 80095d2 { hhid->AltSetting = (uint8_t)(req->wValue); 80095c4: 683b ldr r3, [r7, #0] 80095c6: 885b ldrh r3, [r3, #2] 80095c8: b2db uxtb r3, r3 80095ca: 461a mov r2, r3 80095cc: 68fb ldr r3, [r7, #12] 80095ce: 609a str r2, [r3, #8] else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 80095d0: e00e b.n 80095f0 USBD_CtlError(pdev, req); 80095d2: 6839 ldr r1, [r7, #0] 80095d4: 6878 ldr r0, [r7, #4] 80095d6: f001 fb06 bl 800abe6 ret = USBD_FAIL; 80095da: 2303 movs r3, #3 80095dc: 75fb strb r3, [r7, #23] break; 80095de: e007 b.n 80095f0 case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 80095e0: 6839 ldr r1, [r7, #0] 80095e2: 6878 ldr r0, [r7, #4] 80095e4: f001 faff bl 800abe6 ret = USBD_FAIL; 80095e8: 2303 movs r3, #3 80095ea: 75fb strb r3, [r7, #23] break; 80095ec: e000 b.n 80095f0 break; 80095ee: bf00 nop } break; 80095f0: e006 b.n 8009600 default: USBD_CtlError(pdev, req); 80095f2: 6839 ldr r1, [r7, #0] 80095f4: 6878 ldr r0, [r7, #4] 80095f6: f001 faf6 bl 800abe6 ret = USBD_FAIL; 80095fa: 2303 movs r3, #3 80095fc: 75fb strb r3, [r7, #23] break; 80095fe: bf00 nop } return (uint8_t)ret; 8009600: 7dfb ldrb r3, [r7, #23] } 8009602: 4618 mov r0, r3 8009604: 3718 adds r7, #24 8009606: 46bd mov sp, r7 8009608: bd80 pop {r7, pc} 800960a: bf00 nop 800960c: 20000110 .word 0x20000110 8009610: 200000f8 .word 0x200000f8 08009614 : uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId) { USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) { 8009614: b580 push {r7, lr} 8009616: b086 sub sp, #24 8009618: af00 add r7, sp, #0 800961a: 60f8 str r0, [r7, #12] 800961c: 60b9 str r1, [r7, #8] 800961e: 4613 mov r3, r2 8009620: 80fb strh r3, [r7, #6] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8009622: 68fb ldr r3, [r7, #12] 8009624: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009628: 68fb ldr r3, [r7, #12] 800962a: 32b0 adds r2, #176 @ 0xb0 800962c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009630: 617b str r3, [r7, #20] #endif /* USE_USBD_COMPOSITE */ if (hhid == NULL) 8009632: 697b ldr r3, [r7, #20] 8009634: 2b00 cmp r3, #0 8009636: d101 bne.n 800963c { return (uint8_t)USBD_FAIL; 8009638: 2303 movs r3, #3 800963a: e014 b.n 8009666 #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 800963c: 68fb ldr r3, [r7, #12] 800963e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009642: b2db uxtb r3, r3 8009644: 2b03 cmp r3, #3 8009646: d10d bne.n 8009664 { if (hhid->state == USBD_HID_IDLE) 8009648: 697b ldr r3, [r7, #20] 800964a: 7b1b ldrb r3, [r3, #12] 800964c: 2b00 cmp r3, #0 800964e: d109 bne.n 8009664 { hhid->state = USBD_HID_BUSY; 8009650: 697b ldr r3, [r7, #20] 8009652: 2201 movs r2, #1 8009654: 731a strb r2, [r3, #12] (void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len); 8009656: 4b06 ldr r3, [pc, #24] @ (8009670 ) 8009658: 7819 ldrb r1, [r3, #0] 800965a: 88fb ldrh r3, [r7, #6] 800965c: 68ba ldr r2, [r7, #8] 800965e: 68f8 ldr r0, [r7, #12] 8009660: f001 ff7d bl 800b55e } } return (uint8_t)USBD_OK; 8009664: 2300 movs r3, #0 } 8009666: 4618 mov r0, r3 8009668: 3718 adds r7, #24 800966a: 46bd mov sp, r7 800966c: bd80 pop {r7, pc} 800966e: bf00 nop 8009670: 2000013d .word 0x2000013d 08009674 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) { 8009674: b580 push {r7, lr} 8009676: b084 sub sp, #16 8009678: af00 add r7, sp, #0 800967a: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 800967c: 2181 movs r1, #129 @ 0x81 800967e: 4809 ldr r0, [pc, #36] @ (80096a4 ) 8009680: f000 fc4e bl 8009f20 8009684: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 8009686: 68fb ldr r3, [r7, #12] 8009688: 2b00 cmp r3, #0 800968a: d002 beq.n 8009692 { pEpDesc->bInterval = HID_FS_BINTERVAL; 800968c: 68fb ldr r3, [r7, #12] 800968e: 220a movs r2, #10 8009690: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 8009692: 687b ldr r3, [r7, #4] 8009694: 2222 movs r2, #34 @ 0x22 8009696: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8009698: 4b02 ldr r3, [pc, #8] @ (80096a4 ) } 800969a: 4618 mov r0, r3 800969c: 3710 adds r7, #16 800969e: 46bd mov sp, r7 80096a0: bd80 pop {r7, pc} 80096a2: bf00 nop 80096a4: 200000d4 .word 0x200000d4 080096a8 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) { 80096a8: b580 push {r7, lr} 80096aa: b084 sub sp, #16 80096ac: af00 add r7, sp, #0 80096ae: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 80096b0: 2181 movs r1, #129 @ 0x81 80096b2: 4809 ldr r0, [pc, #36] @ (80096d8 ) 80096b4: f000 fc34 bl 8009f20 80096b8: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 80096ba: 68fb ldr r3, [r7, #12] 80096bc: 2b00 cmp r3, #0 80096be: d002 beq.n 80096c6 { pEpDesc->bInterval = HID_HS_BINTERVAL; 80096c0: 68fb ldr r3, [r7, #12] 80096c2: 2207 movs r2, #7 80096c4: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 80096c6: 687b ldr r3, [r7, #4] 80096c8: 2222 movs r2, #34 @ 0x22 80096ca: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 80096cc: 4b02 ldr r3, [pc, #8] @ (80096d8 ) } 80096ce: 4618 mov r0, r3 80096d0: 3710 adds r7, #16 80096d2: 46bd mov sp, r7 80096d4: bd80 pop {r7, pc} 80096d6: bf00 nop 80096d8: 200000d4 .word 0x200000d4 080096dc : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) { 80096dc: b580 push {r7, lr} 80096de: b084 sub sp, #16 80096e0: af00 add r7, sp, #0 80096e2: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 80096e4: 2181 movs r1, #129 @ 0x81 80096e6: 4809 ldr r0, [pc, #36] @ (800970c ) 80096e8: f000 fc1a bl 8009f20 80096ec: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 80096ee: 68fb ldr r3, [r7, #12] 80096f0: 2b00 cmp r3, #0 80096f2: d002 beq.n 80096fa { pEpDesc->bInterval = HID_FS_BINTERVAL; 80096f4: 68fb ldr r3, [r7, #12] 80096f6: 220a movs r2, #10 80096f8: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 80096fa: 687b ldr r3, [r7, #4] 80096fc: 2222 movs r2, #34 @ 0x22 80096fe: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8009700: 4b02 ldr r3, [pc, #8] @ (800970c ) } 8009702: 4618 mov r0, r3 8009704: 3710 adds r7, #16 8009706: 46bd mov sp, r7 8009708: bd80 pop {r7, pc} 800970a: bf00 nop 800970c: 200000d4 .word 0x200000d4 08009710 : * @param pdev: device instance * @param epnum: endpoint index * @retval status */ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009710: b480 push {r7} 8009712: b083 sub sp, #12 8009714: af00 add r7, sp, #0 8009716: 6078 str r0, [r7, #4] 8009718: 460b mov r3, r1 800971a: 70fb strb r3, [r7, #3] UNUSED(epnum); /* Ensure that the FIFO is empty before a new transfer, this condition could be caused by a new transfer before the end of the previous transfer */ ((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE; 800971c: 687b ldr r3, [r7, #4] 800971e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009722: 687b ldr r3, [r7, #4] 8009724: 32b0 adds r2, #176 @ 0xb0 8009726: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800972a: 2200 movs r2, #0 800972c: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 800972e: 2300 movs r3, #0 } 8009730: 4618 mov r0, r3 8009732: 370c adds r7, #12 8009734: 46bd mov sp, r7 8009736: f85d 7b04 ldr.w r7, [sp], #4 800973a: 4770 bx lr 0800973c : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) { 800973c: b480 push {r7} 800973e: b083 sub sp, #12 8009740: af00 add r7, sp, #0 8009742: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); 8009744: 687b ldr r3, [r7, #4] 8009746: 220a movs r2, #10 8009748: 801a strh r2, [r3, #0] return USBD_HID_DeviceQualifierDesc; 800974a: 4b03 ldr r3, [pc, #12] @ (8009758 ) } 800974c: 4618 mov r0, r3 800974e: 370c adds r7, #12 8009750: 46bd mov sp, r7 8009752: f85d 7b04 ldr.w r7, [sp], #4 8009756: 4770 bx lr 8009758: 20000104 .word 0x20000104 0800975c : * @param id: Low level core index * @retval status: USBD Status */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 800975c: b580 push {r7, lr} 800975e: b086 sub sp, #24 8009760: af00 add r7, sp, #0 8009762: 60f8 str r0, [r7, #12] 8009764: 60b9 str r1, [r7, #8] 8009766: 4613 mov r3, r2 8009768: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 800976a: 68fb ldr r3, [r7, #12] 800976c: 2b00 cmp r3, #0 800976e: d101 bne.n 8009774 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8009770: 2303 movs r3, #3 8009772: e01f b.n 80097b4 pdev->NumClasses = 0; pdev->classId = 0; } #else /* Unlink previous class*/ pdev->pClass[0] = NULL; 8009774: 68fb ldr r3, [r7, #12] 8009776: 2200 movs r2, #0 8009778: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 pdev->pUserData[0] = NULL; 800977c: 68fb ldr r3, [r7, #12] 800977e: 2200 movs r2, #0 8009780: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4 #endif /* USE_USBD_COMPOSITE */ pdev->pConfDesc = NULL; 8009784: 68fb ldr r3, [r7, #12] 8009786: 2200 movs r2, #0 8009788: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 /* Assign USBD Descriptors */ if (pdesc != NULL) 800978c: 68bb ldr r3, [r7, #8] 800978e: 2b00 cmp r3, #0 8009790: d003 beq.n 800979a { pdev->pDesc = pdesc; 8009792: 68fb ldr r3, [r7, #12] 8009794: 68ba ldr r2, [r7, #8] 8009796: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 800979a: 68fb ldr r3, [r7, #12] 800979c: 2201 movs r2, #1 800979e: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->id = id; 80097a2: 68fb ldr r3, [r7, #12] 80097a4: 79fa ldrb r2, [r7, #7] 80097a6: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 80097a8: 68f8 ldr r0, [r7, #12] 80097aa: f001 fda3 bl 800b2f4 80097ae: 4603 mov r3, r0 80097b0: 75fb strb r3, [r7, #23] return ret; 80097b2: 7dfb ldrb r3, [r7, #23] } 80097b4: 4618 mov r0, r3 80097b6: 3718 adds r7, #24 80097b8: 46bd mov sp, r7 80097ba: bd80 pop {r7, pc} 080097bc : * @param pdev: Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 80097bc: b580 push {r7, lr} 80097be: b084 sub sp, #16 80097c0: af00 add r7, sp, #0 80097c2: 6078 str r0, [r7, #4] 80097c4: 6039 str r1, [r7, #0] uint16_t len = 0U; 80097c6: 2300 movs r3, #0 80097c8: 81fb strh r3, [r7, #14] if (pclass == NULL) 80097ca: 683b ldr r3, [r7, #0] 80097cc: 2b00 cmp r3, #0 80097ce: d101 bne.n 80097d4 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 80097d0: 2303 movs r3, #3 80097d2: e025 b.n 8009820 } /* link the class to the USB Device handle */ pdev->pClass[0] = pclass; 80097d4: 687b ldr r3, [r7, #4] 80097d6: 683a ldr r2, [r7, #0] 80097d8: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) 80097dc: 687b ldr r3, [r7, #4] 80097de: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80097e2: 687b ldr r3, [r7, #4] 80097e4: 32ae adds r2, #174 @ 0xae 80097e6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80097ea: 6adb ldr r3, [r3, #44] @ 0x2c 80097ec: 2b00 cmp r3, #0 80097ee: d00f beq.n 8009810 { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); 80097f0: 687b ldr r3, [r7, #4] 80097f2: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80097f6: 687b ldr r3, [r7, #4] 80097f8: 32ae adds r2, #174 @ 0xae 80097fa: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80097fe: 6adb ldr r3, [r3, #44] @ 0x2c 8009800: f107 020e add.w r2, r7, #14 8009804: 4610 mov r0, r2 8009806: 4798 blx r3 8009808: 4602 mov r2, r0 800980a: 687b ldr r3, [r7, #4] 800980c: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 } #endif /* USE_USB_FS */ /* Increment the NumClasses */ pdev->NumClasses++; 8009810: 687b ldr r3, [r7, #4] 8009812: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8009816: 1c5a adds r2, r3, #1 8009818: 687b ldr r3, [r7, #4] 800981a: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8 return USBD_OK; 800981e: 2300 movs r3, #0 } 8009820: 4618 mov r0, r3 8009822: 3710 adds r7, #16 8009824: 46bd mov sp, r7 8009826: bd80 pop {r7, pc} 08009828 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 8009828: b580 push {r7, lr} 800982a: b082 sub sp, #8 800982c: af00 add r7, sp, #0 800982e: 6078 str r0, [r7, #4] #ifdef USE_USBD_COMPOSITE pdev->classId = 0U; #endif /* USE_USBD_COMPOSITE */ /* Start the low level driver */ return USBD_LL_Start(pdev); 8009830: 6878 ldr r0, [r7, #4] 8009832: f001 fdab bl 800b38c 8009836: 4603 mov r3, r0 } 8009838: 4618 mov r0, r3 800983a: 3708 adds r7, #8 800983c: 46bd mov sp, r7 800983e: bd80 pop {r7, pc} 08009840 : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 8009840: b480 push {r7} 8009842: b083 sub sp, #12 8009844: af00 add r7, sp, #0 8009846: 6078 str r0, [r7, #4] return ret; #else /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8009848: 2300 movs r3, #0 #endif /* USBD_HS_TESTMODE_ENABLE */ } 800984a: 4618 mov r0, r3 800984c: 370c adds r7, #12 800984e: 46bd mov sp, r7 8009850: f85d 7b04 ldr.w r7, [sp], #4 8009854: 4770 bx lr 08009856 : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8009856: b580 push {r7, lr} 8009858: b084 sub sp, #16 800985a: af00 add r7, sp, #0 800985c: 6078 str r0, [r7, #4] 800985e: 460b mov r3, r1 8009860: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8009862: 2300 movs r3, #0 8009864: 73fb strb r3, [r7, #15] } } } } #else if (pdev->pClass[0] != NULL) 8009866: 687b ldr r3, [r7, #4] 8009868: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800986c: 2b00 cmp r3, #0 800986e: d009 beq.n 8009884 { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); 8009870: 687b ldr r3, [r7, #4] 8009872: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009876: 681b ldr r3, [r3, #0] 8009878: 78fa ldrb r2, [r7, #3] 800987a: 4611 mov r1, r2 800987c: 6878 ldr r0, [r7, #4] 800987e: 4798 blx r3 8009880: 4603 mov r3, r0 8009882: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8009884: 7bfb ldrb r3, [r7, #15] } 8009886: 4618 mov r0, r3 8009888: 3710 adds r7, #16 800988a: 46bd mov sp, r7 800988c: bd80 pop {r7, pc} 0800988e : * @param pdev: device instance * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 800988e: b580 push {r7, lr} 8009890: b084 sub sp, #16 8009892: af00 add r7, sp, #0 8009894: 6078 str r0, [r7, #4] 8009896: 460b mov r3, r1 8009898: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 800989a: 2300 movs r3, #0 800989c: 73fb strb r3, [r7, #15] } } } #else /* Clear configuration and De-initialize the Class process */ if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) 800989e: 687b ldr r3, [r7, #4] 80098a0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80098a4: 685b ldr r3, [r3, #4] 80098a6: 78fa ldrb r2, [r7, #3] 80098a8: 4611 mov r1, r2 80098aa: 6878 ldr r0, [r7, #4] 80098ac: 4798 blx r3 80098ae: 4603 mov r3, r0 80098b0: 2b00 cmp r3, #0 80098b2: d001 beq.n 80098b8 { ret = USBD_FAIL; 80098b4: 2303 movs r3, #3 80098b6: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 80098b8: 7bfb ldrb r3, [r7, #15] } 80098ba: 4618 mov r0, r3 80098bc: 3710 adds r7, #16 80098be: 46bd mov sp, r7 80098c0: bd80 pop {r7, pc} 080098c2 : * @param pdev: device instance * @param psetup: setup packet buffer pointer * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 80098c2: b580 push {r7, lr} 80098c4: b084 sub sp, #16 80098c6: af00 add r7, sp, #0 80098c8: 6078 str r0, [r7, #4] 80098ca: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 80098cc: 687b ldr r3, [r7, #4] 80098ce: f203 23aa addw r3, r3, #682 @ 0x2aa 80098d2: 6839 ldr r1, [r7, #0] 80098d4: 4618 mov r0, r3 80098d6: f001 f94c bl 800ab72 pdev->ep0_state = USBD_EP0_SETUP; 80098da: 687b ldr r3, [r7, #4] 80098dc: 2201 movs r2, #1 80098de: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep0_data_len = pdev->request.wLength; 80098e2: 687b ldr r3, [r7, #4] 80098e4: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0 80098e8: 461a mov r2, r3 80098ea: 687b ldr r3, [r7, #4] 80098ec: f8c3 2298 str.w r2, [r3, #664] @ 0x298 switch (pdev->request.bmRequest & 0x1FU) 80098f0: 687b ldr r3, [r7, #4] 80098f2: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 80098f6: f003 031f and.w r3, r3, #31 80098fa: 2b02 cmp r3, #2 80098fc: d01a beq.n 8009934 80098fe: 2b02 cmp r3, #2 8009900: d822 bhi.n 8009948 8009902: 2b00 cmp r3, #0 8009904: d002 beq.n 800990c 8009906: 2b01 cmp r3, #1 8009908: d00a beq.n 8009920 800990a: e01d b.n 8009948 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 800990c: 687b ldr r3, [r7, #4] 800990e: f203 23aa addw r3, r3, #682 @ 0x2aa 8009912: 4619 mov r1, r3 8009914: 6878 ldr r0, [r7, #4] 8009916: f000 fb77 bl 800a008 800991a: 4603 mov r3, r0 800991c: 73fb strb r3, [r7, #15] break; 800991e: e020 b.n 8009962 case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 8009920: 687b ldr r3, [r7, #4] 8009922: f203 23aa addw r3, r3, #682 @ 0x2aa 8009926: 4619 mov r1, r3 8009928: 6878 ldr r0, [r7, #4] 800992a: f000 fbdf bl 800a0ec 800992e: 4603 mov r3, r0 8009930: 73fb strb r3, [r7, #15] break; 8009932: e016 b.n 8009962 case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 8009934: 687b ldr r3, [r7, #4] 8009936: f203 23aa addw r3, r3, #682 @ 0x2aa 800993a: 4619 mov r1, r3 800993c: 6878 ldr r0, [r7, #4] 800993e: f000 fc41 bl 800a1c4 8009942: 4603 mov r3, r0 8009944: 73fb strb r3, [r7, #15] break; 8009946: e00c b.n 8009962 default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 8009948: 687b ldr r3, [r7, #4] 800994a: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 800994e: f023 037f bic.w r3, r3, #127 @ 0x7f 8009952: b2db uxtb r3, r3 8009954: 4619 mov r1, r3 8009956: 6878 ldr r0, [r7, #4] 8009958: f001 fd78 bl 800b44c 800995c: 4603 mov r3, r0 800995e: 73fb strb r3, [r7, #15] break; 8009960: bf00 nop } return ret; 8009962: 7bfb ldrb r3, [r7, #15] } 8009964: 4618 mov r0, r3 8009966: 3710 adds r7, #16 8009968: 46bd mov sp, r7 800996a: bd80 pop {r7, pc} 0800996c : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 800996c: b580 push {r7, lr} 800996e: b086 sub sp, #24 8009970: af00 add r7, sp, #0 8009972: 60f8 str r0, [r7, #12] 8009974: 460b mov r3, r1 8009976: 607a str r2, [r7, #4] 8009978: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret = USBD_OK; 800997a: 2300 movs r3, #0 800997c: 75fb strb r3, [r7, #23] uint8_t idx; UNUSED(pdata); if (epnum == 0U) 800997e: 7afb ldrb r3, [r7, #11] 8009980: 2b00 cmp r3, #0 8009982: d177 bne.n 8009a74 { pep = &pdev->ep_out[0]; 8009984: 68fb ldr r3, [r7, #12] 8009986: f503 73aa add.w r3, r3, #340 @ 0x154 800998a: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 800998c: 68fb ldr r3, [r7, #12] 800998e: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8009992: 2b03 cmp r3, #3 8009994: f040 80a1 bne.w 8009ada { if (pep->rem_length > pep->maxpacket) 8009998: 693b ldr r3, [r7, #16] 800999a: 685b ldr r3, [r3, #4] 800999c: 693a ldr r2, [r7, #16] 800999e: 8992 ldrh r2, [r2, #12] 80099a0: 4293 cmp r3, r2 80099a2: d91c bls.n 80099de { pep->rem_length -= pep->maxpacket; 80099a4: 693b ldr r3, [r7, #16] 80099a6: 685b ldr r3, [r3, #4] 80099a8: 693a ldr r2, [r7, #16] 80099aa: 8992 ldrh r2, [r2, #12] 80099ac: 1a9a subs r2, r3, r2 80099ae: 693b ldr r3, [r7, #16] 80099b0: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 80099b2: 693b ldr r3, [r7, #16] 80099b4: 691b ldr r3, [r3, #16] 80099b6: 693a ldr r2, [r7, #16] 80099b8: 8992 ldrh r2, [r2, #12] 80099ba: 441a add r2, r3 80099bc: 693b ldr r3, [r7, #16] 80099be: 611a str r2, [r3, #16] (void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket)); 80099c0: 693b ldr r3, [r7, #16] 80099c2: 6919 ldr r1, [r3, #16] 80099c4: 693b ldr r3, [r7, #16] 80099c6: 899b ldrh r3, [r3, #12] 80099c8: 461a mov r2, r3 80099ca: 693b ldr r3, [r7, #16] 80099cc: 685b ldr r3, [r3, #4] 80099ce: 4293 cmp r3, r2 80099d0: bf38 it cc 80099d2: 4613 movcc r3, r2 80099d4: 461a mov r2, r3 80099d6: 68f8 ldr r0, [r7, #12] 80099d8: f001 f9b1 bl 800ad3e 80099dc: e07d b.n 8009ada } else { /* Find the class ID relative to the current request */ switch (pdev->request.bmRequest & 0x1FU) 80099de: 68fb ldr r3, [r7, #12] 80099e0: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 80099e4: f003 031f and.w r3, r3, #31 80099e8: 2b02 cmp r3, #2 80099ea: d014 beq.n 8009a16 80099ec: 2b02 cmp r3, #2 80099ee: d81d bhi.n 8009a2c 80099f0: 2b00 cmp r3, #0 80099f2: d002 beq.n 80099fa 80099f4: 2b01 cmp r3, #1 80099f6: d003 beq.n 8009a00 80099f8: e018 b.n 8009a2c { case USB_REQ_RECIPIENT_DEVICE: /* Device requests must be managed by the first instantiated class (or duplicated by all classes for simplicity) */ idx = 0U; 80099fa: 2300 movs r3, #0 80099fc: 75bb strb r3, [r7, #22] break; 80099fe: e018 b.n 8009a32 case USB_REQ_RECIPIENT_INTERFACE: idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); 8009a00: 68fb ldr r3, [r7, #12] 8009a02: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8009a06: b2db uxtb r3, r3 8009a08: 4619 mov r1, r3 8009a0a: 68f8 ldr r0, [r7, #12] 8009a0c: f000 fa6e bl 8009eec 8009a10: 4603 mov r3, r0 8009a12: 75bb strb r3, [r7, #22] break; 8009a14: e00d b.n 8009a32 case USB_REQ_RECIPIENT_ENDPOINT: idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); 8009a16: 68fb ldr r3, [r7, #12] 8009a18: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8009a1c: b2db uxtb r3, r3 8009a1e: 4619 mov r1, r3 8009a20: 68f8 ldr r0, [r7, #12] 8009a22: f000 fa70 bl 8009f06 8009a26: 4603 mov r3, r0 8009a28: 75bb strb r3, [r7, #22] break; 8009a2a: e002 b.n 8009a32 default: /* Back to the first class in case of doubt */ idx = 0U; 8009a2c: 2300 movs r3, #0 8009a2e: 75bb strb r3, [r7, #22] break; 8009a30: bf00 nop } if (idx < USBD_MAX_SUPPORTED_CLASS) 8009a32: 7dbb ldrb r3, [r7, #22] 8009a34: 2b00 cmp r3, #0 8009a36: d119 bne.n 8009a6c { /* Setup the class ID and route the request to the relative class function */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009a38: 68fb ldr r3, [r7, #12] 8009a3a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009a3e: b2db uxtb r3, r3 8009a40: 2b03 cmp r3, #3 8009a42: d113 bne.n 8009a6c { if (pdev->pClass[idx]->EP0_RxReady != NULL) 8009a44: 7dba ldrb r2, [r7, #22] 8009a46: 68fb ldr r3, [r7, #12] 8009a48: 32ae adds r2, #174 @ 0xae 8009a4a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009a4e: 691b ldr r3, [r3, #16] 8009a50: 2b00 cmp r3, #0 8009a52: d00b beq.n 8009a6c { pdev->classId = idx; 8009a54: 7dba ldrb r2, [r7, #22] 8009a56: 68fb ldr r3, [r7, #12] 8009a58: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[idx]->EP0_RxReady(pdev); 8009a5c: 7dba ldrb r2, [r7, #22] 8009a5e: 68fb ldr r3, [r7, #12] 8009a60: 32ae adds r2, #174 @ 0xae 8009a62: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009a66: 691b ldr r3, [r3, #16] 8009a68: 68f8 ldr r0, [r7, #12] 8009a6a: 4798 blx r3 } } } (void)USBD_CtlSendStatus(pdev); 8009a6c: 68f8 ldr r0, [r7, #12] 8009a6e: f001 f977 bl 800ad60 8009a72: e032 b.n 8009ada } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); 8009a74: 7afb ldrb r3, [r7, #11] 8009a76: f003 037f and.w r3, r3, #127 @ 0x7f 8009a7a: b2db uxtb r3, r3 8009a7c: 4619 mov r1, r3 8009a7e: 68f8 ldr r0, [r7, #12] 8009a80: f000 fa41 bl 8009f06 8009a84: 4603 mov r3, r0 8009a86: 75bb strb r3, [r7, #22] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009a88: 7dbb ldrb r3, [r7, #22] 8009a8a: 2bff cmp r3, #255 @ 0xff 8009a8c: d025 beq.n 8009ada 8009a8e: 7dbb ldrb r3, [r7, #22] 8009a90: 2b00 cmp r3, #0 8009a92: d122 bne.n 8009ada { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009a94: 68fb ldr r3, [r7, #12] 8009a96: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009a9a: b2db uxtb r3, r3 8009a9c: 2b03 cmp r3, #3 8009a9e: d117 bne.n 8009ad0 { if (pdev->pClass[idx]->DataOut != NULL) 8009aa0: 7dba ldrb r2, [r7, #22] 8009aa2: 68fb ldr r3, [r7, #12] 8009aa4: 32ae adds r2, #174 @ 0xae 8009aa6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009aaa: 699b ldr r3, [r3, #24] 8009aac: 2b00 cmp r3, #0 8009aae: d00f beq.n 8009ad0 { pdev->classId = idx; 8009ab0: 7dba ldrb r2, [r7, #22] 8009ab2: 68fb ldr r3, [r7, #12] 8009ab4: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); 8009ab8: 7dba ldrb r2, [r7, #22] 8009aba: 68fb ldr r3, [r7, #12] 8009abc: 32ae adds r2, #174 @ 0xae 8009abe: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009ac2: 699b ldr r3, [r3, #24] 8009ac4: 7afa ldrb r2, [r7, #11] 8009ac6: 4611 mov r1, r2 8009ac8: 68f8 ldr r0, [r7, #12] 8009aca: 4798 blx r3 8009acc: 4603 mov r3, r0 8009ace: 75fb strb r3, [r7, #23] } } if (ret != USBD_OK) 8009ad0: 7dfb ldrb r3, [r7, #23] 8009ad2: 2b00 cmp r3, #0 8009ad4: d001 beq.n 8009ada { return ret; 8009ad6: 7dfb ldrb r3, [r7, #23] 8009ad8: e000 b.n 8009adc } } } return USBD_OK; 8009ada: 2300 movs r3, #0 } 8009adc: 4618 mov r0, r3 8009ade: 3718 adds r7, #24 8009ae0: 46bd mov sp, r7 8009ae2: bd80 pop {r7, pc} 08009ae4 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8009ae4: b580 push {r7, lr} 8009ae6: b086 sub sp, #24 8009ae8: af00 add r7, sp, #0 8009aea: 60f8 str r0, [r7, #12] 8009aec: 460b mov r3, r1 8009aee: 607a str r2, [r7, #4] 8009af0: 72fb strb r3, [r7, #11] USBD_StatusTypeDef ret; uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8009af2: 7afb ldrb r3, [r7, #11] 8009af4: 2b00 cmp r3, #0 8009af6: d178 bne.n 8009bea { pep = &pdev->ep_in[0]; 8009af8: 68fb ldr r3, [r7, #12] 8009afa: 3314 adds r3, #20 8009afc: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 8009afe: 68fb ldr r3, [r7, #12] 8009b00: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8009b04: 2b02 cmp r3, #2 8009b06: d163 bne.n 8009bd0 { if (pep->rem_length > pep->maxpacket) 8009b08: 693b ldr r3, [r7, #16] 8009b0a: 685b ldr r3, [r3, #4] 8009b0c: 693a ldr r2, [r7, #16] 8009b0e: 8992 ldrh r2, [r2, #12] 8009b10: 4293 cmp r3, r2 8009b12: d91c bls.n 8009b4e { pep->rem_length -= pep->maxpacket; 8009b14: 693b ldr r3, [r7, #16] 8009b16: 685b ldr r3, [r3, #4] 8009b18: 693a ldr r2, [r7, #16] 8009b1a: 8992 ldrh r2, [r2, #12] 8009b1c: 1a9a subs r2, r3, r2 8009b1e: 693b ldr r3, [r7, #16] 8009b20: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8009b22: 693b ldr r3, [r7, #16] 8009b24: 691b ldr r3, [r3, #16] 8009b26: 693a ldr r2, [r7, #16] 8009b28: 8992 ldrh r2, [r2, #12] 8009b2a: 441a add r2, r3 8009b2c: 693b ldr r3, [r7, #16] 8009b2e: 611a str r2, [r3, #16] (void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length); 8009b30: 693b ldr r3, [r7, #16] 8009b32: 6919 ldr r1, [r3, #16] 8009b34: 693b ldr r3, [r7, #16] 8009b36: 685b ldr r3, [r3, #4] 8009b38: 461a mov r2, r3 8009b3a: 68f8 ldr r0, [r7, #12] 8009b3c: f001 f8ee bl 800ad1c /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8009b40: 2300 movs r3, #0 8009b42: 2200 movs r2, #0 8009b44: 2100 movs r1, #0 8009b46: 68f8 ldr r0, [r7, #12] 8009b48: f001 fd2a bl 800b5a0 8009b4c: e040 b.n 8009bd0 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 8009b4e: 693b ldr r3, [r7, #16] 8009b50: 899b ldrh r3, [r3, #12] 8009b52: 461a mov r2, r3 8009b54: 693b ldr r3, [r7, #16] 8009b56: 685b ldr r3, [r3, #4] 8009b58: 429a cmp r2, r3 8009b5a: d11c bne.n 8009b96 (pep->total_length >= pep->maxpacket) && 8009b5c: 693b ldr r3, [r7, #16] 8009b5e: 681b ldr r3, [r3, #0] 8009b60: 693a ldr r2, [r7, #16] 8009b62: 8992 ldrh r2, [r2, #12] if ((pep->maxpacket == pep->rem_length) && 8009b64: 4293 cmp r3, r2 8009b66: d316 bcc.n 8009b96 (pep->total_length < pdev->ep0_data_len)) 8009b68: 693b ldr r3, [r7, #16] 8009b6a: 681a ldr r2, [r3, #0] 8009b6c: 68fb ldr r3, [r7, #12] 8009b6e: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 (pep->total_length >= pep->maxpacket) && 8009b72: 429a cmp r2, r3 8009b74: d20f bcs.n 8009b96 { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 8009b76: 2200 movs r2, #0 8009b78: 2100 movs r1, #0 8009b7a: 68f8 ldr r0, [r7, #12] 8009b7c: f001 f8ce bl 800ad1c pdev->ep0_data_len = 0U; 8009b80: 68fb ldr r3, [r7, #12] 8009b82: 2200 movs r2, #0 8009b84: f8c3 2298 str.w r2, [r3, #664] @ 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8009b88: 2300 movs r3, #0 8009b8a: 2200 movs r2, #0 8009b8c: 2100 movs r1, #0 8009b8e: 68f8 ldr r0, [r7, #12] 8009b90: f001 fd06 bl 800b5a0 8009b94: e01c b.n 8009bd0 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009b96: 68fb ldr r3, [r7, #12] 8009b98: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009b9c: b2db uxtb r3, r3 8009b9e: 2b03 cmp r3, #3 8009ba0: d10f bne.n 8009bc2 { if (pdev->pClass[0]->EP0_TxSent != NULL) 8009ba2: 68fb ldr r3, [r7, #12] 8009ba4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009ba8: 68db ldr r3, [r3, #12] 8009baa: 2b00 cmp r3, #0 8009bac: d009 beq.n 8009bc2 { pdev->classId = 0U; 8009bae: 68fb ldr r3, [r7, #12] 8009bb0: 2200 movs r2, #0 8009bb2: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[0]->EP0_TxSent(pdev); 8009bb6: 68fb ldr r3, [r7, #12] 8009bb8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009bbc: 68db ldr r3, [r3, #12] 8009bbe: 68f8 ldr r0, [r7, #12] 8009bc0: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 8009bc2: 2180 movs r1, #128 @ 0x80 8009bc4: 68f8 ldr r0, [r7, #12] 8009bc6: f001 fc41 bl 800b44c (void)USBD_CtlReceiveStatus(pdev); 8009bca: 68f8 ldr r0, [r7, #12] 8009bcc: f001 f8db bl 800ad86 } } } if (pdev->dev_test_mode != 0U) 8009bd0: 68fb ldr r3, [r7, #12] 8009bd2: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 8009bd6: 2b00 cmp r3, #0 8009bd8: d03a beq.n 8009c50 { (void)USBD_RunTestMode(pdev); 8009bda: 68f8 ldr r0, [r7, #12] 8009bdc: f7ff fe30 bl 8009840 pdev->dev_test_mode = 0U; 8009be0: 68fb ldr r3, [r7, #12] 8009be2: 2200 movs r2, #0 8009be4: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 8009be8: e032 b.n 8009c50 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); 8009bea: 7afb ldrb r3, [r7, #11] 8009bec: f063 037f orn r3, r3, #127 @ 0x7f 8009bf0: b2db uxtb r3, r3 8009bf2: 4619 mov r1, r3 8009bf4: 68f8 ldr r0, [r7, #12] 8009bf6: f000 f986 bl 8009f06 8009bfa: 4603 mov r3, r0 8009bfc: 75fb strb r3, [r7, #23] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009bfe: 7dfb ldrb r3, [r7, #23] 8009c00: 2bff cmp r3, #255 @ 0xff 8009c02: d025 beq.n 8009c50 8009c04: 7dfb ldrb r3, [r7, #23] 8009c06: 2b00 cmp r3, #0 8009c08: d122 bne.n 8009c50 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009c0a: 68fb ldr r3, [r7, #12] 8009c0c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009c10: b2db uxtb r3, r3 8009c12: 2b03 cmp r3, #3 8009c14: d11c bne.n 8009c50 { if (pdev->pClass[idx]->DataIn != NULL) 8009c16: 7dfa ldrb r2, [r7, #23] 8009c18: 68fb ldr r3, [r7, #12] 8009c1a: 32ae adds r2, #174 @ 0xae 8009c1c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009c20: 695b ldr r3, [r3, #20] 8009c22: 2b00 cmp r3, #0 8009c24: d014 beq.n 8009c50 { pdev->classId = idx; 8009c26: 7dfa ldrb r2, [r7, #23] 8009c28: 68fb ldr r3, [r7, #12] 8009c2a: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); 8009c2e: 7dfa ldrb r2, [r7, #23] 8009c30: 68fb ldr r3, [r7, #12] 8009c32: 32ae adds r2, #174 @ 0xae 8009c34: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009c38: 695b ldr r3, [r3, #20] 8009c3a: 7afa ldrb r2, [r7, #11] 8009c3c: 4611 mov r1, r2 8009c3e: 68f8 ldr r0, [r7, #12] 8009c40: 4798 blx r3 8009c42: 4603 mov r3, r0 8009c44: 75bb strb r3, [r7, #22] if (ret != USBD_OK) 8009c46: 7dbb ldrb r3, [r7, #22] 8009c48: 2b00 cmp r3, #0 8009c4a: d001 beq.n 8009c50 { return ret; 8009c4c: 7dbb ldrb r3, [r7, #22] 8009c4e: e000 b.n 8009c52 } } } } return USBD_OK; 8009c50: 2300 movs r3, #0 } 8009c52: 4618 mov r0, r3 8009c54: 3718 adds r7, #24 8009c56: 46bd mov sp, r7 8009c58: bd80 pop {r7, pc} 08009c5a : * Handle Reset event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 8009c5a: b580 push {r7, lr} 8009c5c: b084 sub sp, #16 8009c5e: af00 add r7, sp, #0 8009c60: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 8009c62: 2300 movs r3, #0 8009c64: 73fb strb r3, [r7, #15] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 8009c66: 687b ldr r3, [r7, #4] 8009c68: 2201 movs r2, #1 8009c6a: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->ep0_state = USBD_EP0_IDLE; 8009c6e: 687b ldr r3, [r7, #4] 8009c70: 2200 movs r2, #0 8009c72: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->dev_config = 0U; 8009c76: 687b ldr r3, [r7, #4] 8009c78: 2200 movs r2, #0 8009c7a: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 8009c7c: 687b ldr r3, [r7, #4] 8009c7e: 2200 movs r2, #0 8009c80: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 pdev->dev_test_mode = 0U; 8009c84: 687b ldr r3, [r7, #4] 8009c86: 2200 movs r2, #0 8009c88: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 } } } #else if (pdev->pClass[0] != NULL) 8009c8c: 687b ldr r3, [r7, #4] 8009c8e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009c92: 2b00 cmp r3, #0 8009c94: d014 beq.n 8009cc0 { if (pdev->pClass[0]->DeInit != NULL) 8009c96: 687b ldr r3, [r7, #4] 8009c98: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009c9c: 685b ldr r3, [r3, #4] 8009c9e: 2b00 cmp r3, #0 8009ca0: d00e beq.n 8009cc0 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) 8009ca2: 687b ldr r3, [r7, #4] 8009ca4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009ca8: 685b ldr r3, [r3, #4] 8009caa: 687a ldr r2, [r7, #4] 8009cac: 6852 ldr r2, [r2, #4] 8009cae: b2d2 uxtb r2, r2 8009cb0: 4611 mov r1, r2 8009cb2: 6878 ldr r0, [r7, #4] 8009cb4: 4798 blx r3 8009cb6: 4603 mov r3, r0 8009cb8: 2b00 cmp r3, #0 8009cba: d001 beq.n 8009cc0 { ret = USBD_FAIL; 8009cbc: 2303 movs r3, #3 8009cbe: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8009cc0: 2340 movs r3, #64 @ 0x40 8009cc2: 2200 movs r2, #0 8009cc4: 2100 movs r1, #0 8009cc6: 6878 ldr r0, [r7, #4] 8009cc8: f001 fb7b bl 800b3c2 pdev->ep_out[0x00U & 0xFU].is_used = 1U; 8009ccc: 687b ldr r3, [r7, #4] 8009cce: 2201 movs r2, #1 8009cd0: f883 2163 strb.w r2, [r3, #355] @ 0x163 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 8009cd4: 687b ldr r3, [r7, #4] 8009cd6: 2240 movs r2, #64 @ 0x40 8009cd8: f8a3 2160 strh.w r2, [r3, #352] @ 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8009cdc: 2340 movs r3, #64 @ 0x40 8009cde: 2200 movs r2, #0 8009ce0: 2180 movs r1, #128 @ 0x80 8009ce2: 6878 ldr r0, [r7, #4] 8009ce4: f001 fb6d bl 800b3c2 pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8009ce8: 687b ldr r3, [r7, #4] 8009cea: 2201 movs r2, #1 8009cec: f883 2023 strb.w r2, [r3, #35] @ 0x23 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8009cf0: 687b ldr r3, [r7, #4] 8009cf2: 2240 movs r2, #64 @ 0x40 8009cf4: 841a strh r2, [r3, #32] return ret; 8009cf6: 7bfb ldrb r3, [r7, #15] } 8009cf8: 4618 mov r0, r3 8009cfa: 3710 adds r7, #16 8009cfc: 46bd mov sp, r7 8009cfe: bd80 pop {r7, pc} 08009d00 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8009d00: b480 push {r7} 8009d02: b083 sub sp, #12 8009d04: af00 add r7, sp, #0 8009d06: 6078 str r0, [r7, #4] 8009d08: 460b mov r3, r1 8009d0a: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 8009d0c: 687b ldr r3, [r7, #4] 8009d0e: 78fa ldrb r2, [r7, #3] 8009d10: 741a strb r2, [r3, #16] return USBD_OK; 8009d12: 2300 movs r3, #0 } 8009d14: 4618 mov r0, r3 8009d16: 370c adds r7, #12 8009d18: 46bd mov sp, r7 8009d1a: f85d 7b04 ldr.w r7, [sp], #4 8009d1e: 4770 bx lr 08009d20 : * Handle Suspend event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 8009d20: b480 push {r7} 8009d22: b083 sub sp, #12 8009d24: af00 add r7, sp, #0 8009d26: 6078 str r0, [r7, #4] if (pdev->dev_state != USBD_STATE_SUSPENDED) 8009d28: 687b ldr r3, [r7, #4] 8009d2a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009d2e: b2db uxtb r3, r3 8009d30: 2b04 cmp r3, #4 8009d32: d006 beq.n 8009d42 { pdev->dev_old_state = pdev->dev_state; 8009d34: 687b ldr r3, [r7, #4] 8009d36: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009d3a: b2da uxtb r2, r3 8009d3c: 687b ldr r3, [r7, #4] 8009d3e: f883 229d strb.w r2, [r3, #669] @ 0x29d } pdev->dev_state = USBD_STATE_SUSPENDED; 8009d42: 687b ldr r3, [r7, #4] 8009d44: 2204 movs r2, #4 8009d46: f883 229c strb.w r2, [r3, #668] @ 0x29c return USBD_OK; 8009d4a: 2300 movs r3, #0 } 8009d4c: 4618 mov r0, r3 8009d4e: 370c adds r7, #12 8009d50: 46bd mov sp, r7 8009d52: f85d 7b04 ldr.w r7, [sp], #4 8009d56: 4770 bx lr 08009d58 : * Handle Resume event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 8009d58: b480 push {r7} 8009d5a: b083 sub sp, #12 8009d5c: af00 add r7, sp, #0 8009d5e: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 8009d60: 687b ldr r3, [r7, #4] 8009d62: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009d66: b2db uxtb r3, r3 8009d68: 2b04 cmp r3, #4 8009d6a: d106 bne.n 8009d7a { pdev->dev_state = pdev->dev_old_state; 8009d6c: 687b ldr r3, [r7, #4] 8009d6e: f893 329d ldrb.w r3, [r3, #669] @ 0x29d 8009d72: b2da uxtb r2, r3 8009d74: 687b ldr r3, [r7, #4] 8009d76: f883 229c strb.w r2, [r3, #668] @ 0x29c } return USBD_OK; 8009d7a: 2300 movs r3, #0 } 8009d7c: 4618 mov r0, r3 8009d7e: 370c adds r7, #12 8009d80: 46bd mov sp, r7 8009d82: f85d 7b04 ldr.w r7, [sp], #4 8009d86: 4770 bx lr 08009d88 : * Handle SOF event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 8009d88: b580 push {r7, lr} 8009d8a: b082 sub sp, #8 8009d8c: af00 add r7, sp, #0 8009d8e: 6078 str r0, [r7, #4] /* The SOF event can be distributed for all classes that support it */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009d90: 687b ldr r3, [r7, #4] 8009d92: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009d96: b2db uxtb r3, r3 8009d98: 2b03 cmp r3, #3 8009d9a: d110 bne.n 8009dbe } } } } #else if (pdev->pClass[0] != NULL) 8009d9c: 687b ldr r3, [r7, #4] 8009d9e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009da2: 2b00 cmp r3, #0 8009da4: d00b beq.n 8009dbe { if (pdev->pClass[0]->SOF != NULL) 8009da6: 687b ldr r3, [r7, #4] 8009da8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009dac: 69db ldr r3, [r3, #28] 8009dae: 2b00 cmp r3, #0 8009db0: d005 beq.n 8009dbe { (void)pdev->pClass[0]->SOF(pdev); 8009db2: 687b ldr r3, [r7, #4] 8009db4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009db8: 69db ldr r3, [r3, #28] 8009dba: 6878 ldr r0, [r7, #4] 8009dbc: 4798 blx r3 } } #endif /* USE_USBD_COMPOSITE */ } return USBD_OK; 8009dbe: 2300 movs r3, #0 } 8009dc0: 4618 mov r0, r3 8009dc2: 3708 adds r7, #8 8009dc4: 46bd mov sp, r7 8009dc6: bd80 pop {r7, pc} 08009dc8 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009dc8: b580 push {r7, lr} 8009dca: b082 sub sp, #8 8009dcc: af00 add r7, sp, #0 8009dce: 6078 str r0, [r7, #4] 8009dd0: 460b mov r3, r1 8009dd2: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009dd4: 687b ldr r3, [r7, #4] 8009dd6: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009dda: 687b ldr r3, [r7, #4] 8009ddc: 32ae adds r2, #174 @ 0xae 8009dde: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009de2: 2b00 cmp r3, #0 8009de4: d101 bne.n 8009dea { return USBD_FAIL; 8009de6: 2303 movs r3, #3 8009de8: e01c b.n 8009e24 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009dea: 687b ldr r3, [r7, #4] 8009dec: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009df0: b2db uxtb r3, r3 8009df2: 2b03 cmp r3, #3 8009df4: d115 bne.n 8009e22 { if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL) 8009df6: 687b ldr r3, [r7, #4] 8009df8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009dfc: 687b ldr r3, [r7, #4] 8009dfe: 32ae adds r2, #174 @ 0xae 8009e00: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009e04: 6a1b ldr r3, [r3, #32] 8009e06: 2b00 cmp r3, #0 8009e08: d00b beq.n 8009e22 { (void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum); 8009e0a: 687b ldr r3, [r7, #4] 8009e0c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009e10: 687b ldr r3, [r7, #4] 8009e12: 32ae adds r2, #174 @ 0xae 8009e14: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009e18: 6a1b ldr r3, [r3, #32] 8009e1a: 78fa ldrb r2, [r7, #3] 8009e1c: 4611 mov r1, r2 8009e1e: 6878 ldr r0, [r7, #4] 8009e20: 4798 blx r3 } } return USBD_OK; 8009e22: 2300 movs r3, #0 } 8009e24: 4618 mov r0, r3 8009e26: 3708 adds r7, #8 8009e28: 46bd mov sp, r7 8009e2a: bd80 pop {r7, pc} 08009e2c : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009e2c: b580 push {r7, lr} 8009e2e: b082 sub sp, #8 8009e30: af00 add r7, sp, #0 8009e32: 6078 str r0, [r7, #4] 8009e34: 460b mov r3, r1 8009e36: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009e38: 687b ldr r3, [r7, #4] 8009e3a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009e3e: 687b ldr r3, [r7, #4] 8009e40: 32ae adds r2, #174 @ 0xae 8009e42: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009e46: 2b00 cmp r3, #0 8009e48: d101 bne.n 8009e4e { return USBD_FAIL; 8009e4a: 2303 movs r3, #3 8009e4c: e01c b.n 8009e88 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009e4e: 687b ldr r3, [r7, #4] 8009e50: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009e54: b2db uxtb r3, r3 8009e56: 2b03 cmp r3, #3 8009e58: d115 bne.n 8009e86 { if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL) 8009e5a: 687b ldr r3, [r7, #4] 8009e5c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009e60: 687b ldr r3, [r7, #4] 8009e62: 32ae adds r2, #174 @ 0xae 8009e64: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009e68: 6a5b ldr r3, [r3, #36] @ 0x24 8009e6a: 2b00 cmp r3, #0 8009e6c: d00b beq.n 8009e86 { (void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum); 8009e6e: 687b ldr r3, [r7, #4] 8009e70: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009e74: 687b ldr r3, [r7, #4] 8009e76: 32ae adds r2, #174 @ 0xae 8009e78: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009e7c: 6a5b ldr r3, [r3, #36] @ 0x24 8009e7e: 78fa ldrb r2, [r7, #3] 8009e80: 4611 mov r1, r2 8009e82: 6878 ldr r0, [r7, #4] 8009e84: 4798 blx r3 } } return USBD_OK; 8009e86: 2300 movs r3, #0 } 8009e88: 4618 mov r0, r3 8009e8a: 3708 adds r7, #8 8009e8c: 46bd mov sp, r7 8009e8e: bd80 pop {r7, pc} 08009e90 : * Handle device connection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { 8009e90: b480 push {r7} 8009e92: b083 sub sp, #12 8009e94: af00 add r7, sp, #0 8009e96: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8009e98: 2300 movs r3, #0 } 8009e9a: 4618 mov r0, r3 8009e9c: 370c adds r7, #12 8009e9e: 46bd mov sp, r7 8009ea0: f85d 7b04 ldr.w r7, [sp], #4 8009ea4: 4770 bx lr 08009ea6 : * Handle device disconnection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { 8009ea6: b580 push {r7, lr} 8009ea8: b084 sub sp, #16 8009eaa: af00 add r7, sp, #0 8009eac: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 8009eae: 2300 movs r3, #0 8009eb0: 73fb strb r3, [r7, #15] /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; 8009eb2: 687b ldr r3, [r7, #4] 8009eb4: 2201 movs r2, #1 8009eb6: f883 229c strb.w r2, [r3, #668] @ 0x29c } } } } #else if (pdev->pClass[0] != NULL) 8009eba: 687b ldr r3, [r7, #4] 8009ebc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009ec0: 2b00 cmp r3, #0 8009ec2: d00e beq.n 8009ee2 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U) 8009ec4: 687b ldr r3, [r7, #4] 8009ec6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009eca: 685b ldr r3, [r3, #4] 8009ecc: 687a ldr r2, [r7, #4] 8009ece: 6852 ldr r2, [r2, #4] 8009ed0: b2d2 uxtb r2, r2 8009ed2: 4611 mov r1, r2 8009ed4: 6878 ldr r0, [r7, #4] 8009ed6: 4798 blx r3 8009ed8: 4603 mov r3, r0 8009eda: 2b00 cmp r3, #0 8009edc: d001 beq.n 8009ee2 { ret = USBD_FAIL; 8009ede: 2303 movs r3, #3 8009ee0: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ return ret; 8009ee2: 7bfb ldrb r3, [r7, #15] } 8009ee4: 4618 mov r0, r3 8009ee6: 3710 adds r7, #16 8009ee8: 46bd mov sp, r7 8009eea: bd80 pop {r7, pc} 08009eec : * @param pdev: device instance * @param index : selected interface number * @retval index of the class using the selected interface number. OxFF if no class found. */ uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) { 8009eec: b480 push {r7} 8009eee: b083 sub sp, #12 8009ef0: af00 add r7, sp, #0 8009ef2: 6078 str r0, [r7, #4] 8009ef4: 460b mov r3, r1 8009ef6: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009ef8: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8009efa: 4618 mov r0, r3 8009efc: 370c adds r7, #12 8009efe: 46bd mov sp, r7 8009f00: f85d 7b04 ldr.w r7, [sp], #4 8009f04: 4770 bx lr 08009f06 : * @param pdev: device instance * @param index : selected endpoint number * @retval index of the class using the selected endpoint number. 0xFF if no class found. */ uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) { 8009f06: b480 push {r7} 8009f08: b083 sub sp, #12 8009f0a: af00 add r7, sp, #0 8009f0c: 6078 str r0, [r7, #4] 8009f0e: 460b mov r3, r1 8009f10: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009f12: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8009f14: 4618 mov r0, r3 8009f16: 370c adds r7, #12 8009f18: 46bd mov sp, r7 8009f1a: f85d 7b04 ldr.w r7, [sp], #4 8009f1e: 4770 bx lr 08009f20 : * @param pConfDesc: pointer to Bos descriptor * @param EpAddr: endpoint address * @retval pointer to video endpoint descriptor */ void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) { 8009f20: b580 push {r7, lr} 8009f22: b086 sub sp, #24 8009f24: af00 add r7, sp, #0 8009f26: 6078 str r0, [r7, #4] 8009f28: 460b mov r3, r1 8009f2a: 70fb strb r3, [r7, #3] USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; 8009f2c: 687b ldr r3, [r7, #4] 8009f2e: 617b str r3, [r7, #20] USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; 8009f30: 687b ldr r3, [r7, #4] 8009f32: 60fb str r3, [r7, #12] USBD_EpDescTypeDef *pEpDesc = NULL; 8009f34: 2300 movs r3, #0 8009f36: 613b str r3, [r7, #16] uint16_t ptr; if (desc->wTotalLength > desc->bLength) 8009f38: 68fb ldr r3, [r7, #12] 8009f3a: 885b ldrh r3, [r3, #2] 8009f3c: b29b uxth r3, r3 8009f3e: 68fa ldr r2, [r7, #12] 8009f40: 7812 ldrb r2, [r2, #0] 8009f42: 4293 cmp r3, r2 8009f44: d91f bls.n 8009f86 { ptr = desc->bLength; 8009f46: 68fb ldr r3, [r7, #12] 8009f48: 781b ldrb r3, [r3, #0] 8009f4a: 817b strh r3, [r7, #10] while (ptr < desc->wTotalLength) 8009f4c: e013 b.n 8009f76 { pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); 8009f4e: f107 030a add.w r3, r7, #10 8009f52: 4619 mov r1, r3 8009f54: 6978 ldr r0, [r7, #20] 8009f56: f000 f81b bl 8009f90 8009f5a: 6178 str r0, [r7, #20] if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) 8009f5c: 697b ldr r3, [r7, #20] 8009f5e: 785b ldrb r3, [r3, #1] 8009f60: 2b05 cmp r3, #5 8009f62: d108 bne.n 8009f76 { pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; 8009f64: 697b ldr r3, [r7, #20] 8009f66: 613b str r3, [r7, #16] if (pEpDesc->bEndpointAddress == EpAddr) 8009f68: 693b ldr r3, [r7, #16] 8009f6a: 789b ldrb r3, [r3, #2] 8009f6c: 78fa ldrb r2, [r7, #3] 8009f6e: 429a cmp r2, r3 8009f70: d008 beq.n 8009f84 { break; } else { pEpDesc = NULL; 8009f72: 2300 movs r3, #0 8009f74: 613b str r3, [r7, #16] while (ptr < desc->wTotalLength) 8009f76: 68fb ldr r3, [r7, #12] 8009f78: 885b ldrh r3, [r3, #2] 8009f7a: b29a uxth r2, r3 8009f7c: 897b ldrh r3, [r7, #10] 8009f7e: 429a cmp r2, r3 8009f80: d8e5 bhi.n 8009f4e 8009f82: e000 b.n 8009f86 break; 8009f84: bf00 nop } } } } return (void *)pEpDesc; 8009f86: 693b ldr r3, [r7, #16] } 8009f88: 4618 mov r0, r3 8009f8a: 3718 adds r7, #24 8009f8c: 46bd mov sp, r7 8009f8e: bd80 pop {r7, pc} 08009f90 : * @param buf: Buffer where the descriptor is available * @param ptr: data pointer inside the descriptor * @retval next header */ USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) { 8009f90: b480 push {r7} 8009f92: b085 sub sp, #20 8009f94: af00 add r7, sp, #0 8009f96: 6078 str r0, [r7, #4] 8009f98: 6039 str r1, [r7, #0] USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; 8009f9a: 687b ldr r3, [r7, #4] 8009f9c: 60fb str r3, [r7, #12] *ptr += pnext->bLength; 8009f9e: 683b ldr r3, [r7, #0] 8009fa0: 881b ldrh r3, [r3, #0] 8009fa2: 68fa ldr r2, [r7, #12] 8009fa4: 7812 ldrb r2, [r2, #0] 8009fa6: 4413 add r3, r2 8009fa8: b29a uxth r2, r3 8009faa: 683b ldr r3, [r7, #0] 8009fac: 801a strh r2, [r3, #0] pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); 8009fae: 68fb ldr r3, [r7, #12] 8009fb0: 781b ldrb r3, [r3, #0] 8009fb2: 461a mov r2, r3 8009fb4: 687b ldr r3, [r7, #4] 8009fb6: 4413 add r3, r2 8009fb8: 60fb str r3, [r7, #12] return (pnext); 8009fba: 68fb ldr r3, [r7, #12] } 8009fbc: 4618 mov r0, r3 8009fbe: 3714 adds r7, #20 8009fc0: 46bd mov sp, r7 8009fc2: f85d 7b04 ldr.w r7, [sp], #4 8009fc6: 4770 bx lr 08009fc8 : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 8009fc8: b480 push {r7} 8009fca: b087 sub sp, #28 8009fcc: af00 add r7, sp, #0 8009fce: 6078 str r0, [r7, #4] uint16_t _SwapVal; uint16_t _Byte1; uint16_t _Byte2; uint8_t *_pbuff = addr; 8009fd0: 687b ldr r3, [r7, #4] 8009fd2: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 8009fd4: 697b ldr r3, [r7, #20] 8009fd6: 781b ldrb r3, [r3, #0] 8009fd8: 827b strh r3, [r7, #18] _pbuff++; 8009fda: 697b ldr r3, [r7, #20] 8009fdc: 3301 adds r3, #1 8009fde: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 8009fe0: 697b ldr r3, [r7, #20] 8009fe2: 781b ldrb r3, [r3, #0] 8009fe4: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 8009fe6: f9b7 3010 ldrsh.w r3, [r7, #16] 8009fea: 021b lsls r3, r3, #8 8009fec: b21a sxth r2, r3 8009fee: f9b7 3012 ldrsh.w r3, [r7, #18] 8009ff2: 4313 orrs r3, r2 8009ff4: b21b sxth r3, r3 8009ff6: 81fb strh r3, [r7, #14] return _SwapVal; 8009ff8: 89fb ldrh r3, [r7, #14] } 8009ffa: 4618 mov r0, r3 8009ffc: 371c adds r7, #28 8009ffe: 46bd mov sp, r7 800a000: f85d 7b04 ldr.w r7, [sp], #4 800a004: 4770 bx lr ... 0800a008 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a008: b580 push {r7, lr} 800a00a: b084 sub sp, #16 800a00c: af00 add r7, sp, #0 800a00e: 6078 str r0, [r7, #4] 800a010: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800a012: 2300 movs r3, #0 800a014: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 800a016: 683b ldr r3, [r7, #0] 800a018: 781b ldrb r3, [r3, #0] 800a01a: f003 0360 and.w r3, r3, #96 @ 0x60 800a01e: 2b40 cmp r3, #64 @ 0x40 800a020: d005 beq.n 800a02e 800a022: 2b40 cmp r3, #64 @ 0x40 800a024: d857 bhi.n 800a0d6 800a026: 2b00 cmp r3, #0 800a028: d00f beq.n 800a04a 800a02a: 2b20 cmp r3, #32 800a02c: d153 bne.n 800a0d6 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); 800a02e: 687b ldr r3, [r7, #4] 800a030: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800a034: 687b ldr r3, [r7, #4] 800a036: 32ae adds r2, #174 @ 0xae 800a038: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a03c: 689b ldr r3, [r3, #8] 800a03e: 6839 ldr r1, [r7, #0] 800a040: 6878 ldr r0, [r7, #4] 800a042: 4798 blx r3 800a044: 4603 mov r3, r0 800a046: 73fb strb r3, [r7, #15] break; 800a048: e04a b.n 800a0e0 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 800a04a: 683b ldr r3, [r7, #0] 800a04c: 785b ldrb r3, [r3, #1] 800a04e: 2b09 cmp r3, #9 800a050: d83b bhi.n 800a0ca 800a052: a201 add r2, pc, #4 @ (adr r2, 800a058 ) 800a054: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a058: 0800a0ad .word 0x0800a0ad 800a05c: 0800a0c1 .word 0x0800a0c1 800a060: 0800a0cb .word 0x0800a0cb 800a064: 0800a0b7 .word 0x0800a0b7 800a068: 0800a0cb .word 0x0800a0cb 800a06c: 0800a08b .word 0x0800a08b 800a070: 0800a081 .word 0x0800a081 800a074: 0800a0cb .word 0x0800a0cb 800a078: 0800a0a3 .word 0x0800a0a3 800a07c: 0800a095 .word 0x0800a095 { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 800a080: 6839 ldr r1, [r7, #0] 800a082: 6878 ldr r0, [r7, #4] 800a084: f000 fa3e bl 800a504 break; 800a088: e024 b.n 800a0d4 case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 800a08a: 6839 ldr r1, [r7, #0] 800a08c: 6878 ldr r0, [r7, #4] 800a08e: f000 fbcd bl 800a82c break; 800a092: e01f b.n 800a0d4 case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 800a094: 6839 ldr r1, [r7, #0] 800a096: 6878 ldr r0, [r7, #4] 800a098: f000 fc0c bl 800a8b4 800a09c: 4603 mov r3, r0 800a09e: 73fb strb r3, [r7, #15] break; 800a0a0: e018 b.n 800a0d4 case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 800a0a2: 6839 ldr r1, [r7, #0] 800a0a4: 6878 ldr r0, [r7, #4] 800a0a6: f000 fcaf bl 800aa08 break; 800a0aa: e013 b.n 800a0d4 case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 800a0ac: 6839 ldr r1, [r7, #0] 800a0ae: 6878 ldr r0, [r7, #4] 800a0b0: f000 fce0 bl 800aa74 break; 800a0b4: e00e b.n 800a0d4 case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 800a0b6: 6839 ldr r1, [r7, #0] 800a0b8: 6878 ldr r0, [r7, #4] 800a0ba: f000 fd0f bl 800aadc break; 800a0be: e009 b.n 800a0d4 case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 800a0c0: 6839 ldr r1, [r7, #0] 800a0c2: 6878 ldr r0, [r7, #4] 800a0c4: f000 fd33 bl 800ab2e break; 800a0c8: e004 b.n 800a0d4 default: USBD_CtlError(pdev, req); 800a0ca: 6839 ldr r1, [r7, #0] 800a0cc: 6878 ldr r0, [r7, #4] 800a0ce: f000 fd8a bl 800abe6 break; 800a0d2: bf00 nop } break; 800a0d4: e004 b.n 800a0e0 default: USBD_CtlError(pdev, req); 800a0d6: 6839 ldr r1, [r7, #0] 800a0d8: 6878 ldr r0, [r7, #4] 800a0da: f000 fd84 bl 800abe6 break; 800a0de: bf00 nop } return ret; 800a0e0: 7bfb ldrb r3, [r7, #15] } 800a0e2: 4618 mov r0, r3 800a0e4: 3710 adds r7, #16 800a0e6: 46bd mov sp, r7 800a0e8: bd80 pop {r7, pc} 800a0ea: bf00 nop 0800a0ec : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a0ec: b580 push {r7, lr} 800a0ee: b084 sub sp, #16 800a0f0: af00 add r7, sp, #0 800a0f2: 6078 str r0, [r7, #4] 800a0f4: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800a0f6: 2300 movs r3, #0 800a0f8: 73fb strb r3, [r7, #15] uint8_t idx; switch (req->bmRequest & USB_REQ_TYPE_MASK) 800a0fa: 683b ldr r3, [r7, #0] 800a0fc: 781b ldrb r3, [r3, #0] 800a0fe: f003 0360 and.w r3, r3, #96 @ 0x60 800a102: 2b40 cmp r3, #64 @ 0x40 800a104: d005 beq.n 800a112 800a106: 2b40 cmp r3, #64 @ 0x40 800a108: d852 bhi.n 800a1b0 800a10a: 2b00 cmp r3, #0 800a10c: d001 beq.n 800a112 800a10e: 2b20 cmp r3, #32 800a110: d14e bne.n 800a1b0 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 800a112: 687b ldr r3, [r7, #4] 800a114: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a118: b2db uxtb r3, r3 800a11a: 3b01 subs r3, #1 800a11c: 2b02 cmp r3, #2 800a11e: d840 bhi.n 800a1a2 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 800a120: 683b ldr r3, [r7, #0] 800a122: 889b ldrh r3, [r3, #4] 800a124: b2db uxtb r3, r3 800a126: 2b01 cmp r3, #1 800a128: d836 bhi.n 800a198 { /* Get the class index relative to this interface */ idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); 800a12a: 683b ldr r3, [r7, #0] 800a12c: 889b ldrh r3, [r3, #4] 800a12e: b2db uxtb r3, r3 800a130: 4619 mov r1, r3 800a132: 6878 ldr r0, [r7, #4] 800a134: f7ff feda bl 8009eec 800a138: 4603 mov r3, r0 800a13a: 73bb strb r3, [r7, #14] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800a13c: 7bbb ldrb r3, [r7, #14] 800a13e: 2bff cmp r3, #255 @ 0xff 800a140: d01d beq.n 800a17e 800a142: 7bbb ldrb r3, [r7, #14] 800a144: 2b00 cmp r3, #0 800a146: d11a bne.n 800a17e { /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 800a148: 7bba ldrb r2, [r7, #14] 800a14a: 687b ldr r3, [r7, #4] 800a14c: 32ae adds r2, #174 @ 0xae 800a14e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a152: 689b ldr r3, [r3, #8] 800a154: 2b00 cmp r3, #0 800a156: d00f beq.n 800a178 { pdev->classId = idx; 800a158: 7bba ldrb r2, [r7, #14] 800a15a: 687b ldr r3, [r7, #4] 800a15c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 800a160: 7bba ldrb r2, [r7, #14] 800a162: 687b ldr r3, [r7, #4] 800a164: 32ae adds r2, #174 @ 0xae 800a166: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a16a: 689b ldr r3, [r3, #8] 800a16c: 6839 ldr r1, [r7, #0] 800a16e: 6878 ldr r0, [r7, #4] 800a170: 4798 blx r3 800a172: 4603 mov r3, r0 800a174: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 800a176: e004 b.n 800a182 } else { /* should never reach this condition */ ret = USBD_FAIL; 800a178: 2303 movs r3, #3 800a17a: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 800a17c: e001 b.n 800a182 } } else { /* No relative interface found */ ret = USBD_FAIL; 800a17e: 2303 movs r3, #3 800a180: 73fb strb r3, [r7, #15] } if ((req->wLength == 0U) && (ret == USBD_OK)) 800a182: 683b ldr r3, [r7, #0] 800a184: 88db ldrh r3, [r3, #6] 800a186: 2b00 cmp r3, #0 800a188: d110 bne.n 800a1ac 800a18a: 7bfb ldrb r3, [r7, #15] 800a18c: 2b00 cmp r3, #0 800a18e: d10d bne.n 800a1ac { (void)USBD_CtlSendStatus(pdev); 800a190: 6878 ldr r0, [r7, #4] 800a192: f000 fde5 bl 800ad60 } else { USBD_CtlError(pdev, req); } break; 800a196: e009 b.n 800a1ac USBD_CtlError(pdev, req); 800a198: 6839 ldr r1, [r7, #0] 800a19a: 6878 ldr r0, [r7, #4] 800a19c: f000 fd23 bl 800abe6 break; 800a1a0: e004 b.n 800a1ac default: USBD_CtlError(pdev, req); 800a1a2: 6839 ldr r1, [r7, #0] 800a1a4: 6878 ldr r0, [r7, #4] 800a1a6: f000 fd1e bl 800abe6 break; 800a1aa: e000 b.n 800a1ae break; 800a1ac: bf00 nop } break; 800a1ae: e004 b.n 800a1ba default: USBD_CtlError(pdev, req); 800a1b0: 6839 ldr r1, [r7, #0] 800a1b2: 6878 ldr r0, [r7, #4] 800a1b4: f000 fd17 bl 800abe6 break; 800a1b8: bf00 nop } return ret; 800a1ba: 7bfb ldrb r3, [r7, #15] } 800a1bc: 4618 mov r0, r3 800a1be: 3710 adds r7, #16 800a1c0: 46bd mov sp, r7 800a1c2: bd80 pop {r7, pc} 0800a1c4 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a1c4: b580 push {r7, lr} 800a1c6: b084 sub sp, #16 800a1c8: af00 add r7, sp, #0 800a1ca: 6078 str r0, [r7, #4] 800a1cc: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; uint8_t idx; USBD_StatusTypeDef ret = USBD_OK; 800a1ce: 2300 movs r3, #0 800a1d0: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 800a1d2: 683b ldr r3, [r7, #0] 800a1d4: 889b ldrh r3, [r3, #4] 800a1d6: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 800a1d8: 683b ldr r3, [r7, #0] 800a1da: 781b ldrb r3, [r3, #0] 800a1dc: f003 0360 and.w r3, r3, #96 @ 0x60 800a1e0: 2b40 cmp r3, #64 @ 0x40 800a1e2: d007 beq.n 800a1f4 800a1e4: 2b40 cmp r3, #64 @ 0x40 800a1e6: f200 8181 bhi.w 800a4ec 800a1ea: 2b00 cmp r3, #0 800a1ec: d02a beq.n 800a244 800a1ee: 2b20 cmp r3, #32 800a1f0: f040 817c bne.w 800a4ec { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: /* Get the class index relative to this endpoint */ idx = USBD_CoreFindEP(pdev, ep_addr); 800a1f4: 7bbb ldrb r3, [r7, #14] 800a1f6: 4619 mov r1, r3 800a1f8: 6878 ldr r0, [r7, #4] 800a1fa: f7ff fe84 bl 8009f06 800a1fe: 4603 mov r3, r0 800a200: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800a202: 7b7b ldrb r3, [r7, #13] 800a204: 2bff cmp r3, #255 @ 0xff 800a206: f000 8176 beq.w 800a4f6 800a20a: 7b7b ldrb r3, [r7, #13] 800a20c: 2b00 cmp r3, #0 800a20e: f040 8172 bne.w 800a4f6 { pdev->classId = idx; 800a212: 7b7a ldrb r2, [r7, #13] 800a214: 687b ldr r3, [r7, #4] 800a216: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 800a21a: 7b7a ldrb r2, [r7, #13] 800a21c: 687b ldr r3, [r7, #4] 800a21e: 32ae adds r2, #174 @ 0xae 800a220: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a224: 689b ldr r3, [r3, #8] 800a226: 2b00 cmp r3, #0 800a228: f000 8165 beq.w 800a4f6 { ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); 800a22c: 7b7a ldrb r2, [r7, #13] 800a22e: 687b ldr r3, [r7, #4] 800a230: 32ae adds r2, #174 @ 0xae 800a232: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a236: 689b ldr r3, [r3, #8] 800a238: 6839 ldr r1, [r7, #0] 800a23a: 6878 ldr r0, [r7, #4] 800a23c: 4798 blx r3 800a23e: 4603 mov r3, r0 800a240: 73fb strb r3, [r7, #15] } } break; 800a242: e158 b.n 800a4f6 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 800a244: 683b ldr r3, [r7, #0] 800a246: 785b ldrb r3, [r3, #1] 800a248: 2b03 cmp r3, #3 800a24a: d008 beq.n 800a25e 800a24c: 2b03 cmp r3, #3 800a24e: f300 8147 bgt.w 800a4e0 800a252: 2b00 cmp r3, #0 800a254: f000 809b beq.w 800a38e 800a258: 2b01 cmp r3, #1 800a25a: d03c beq.n 800a2d6 800a25c: e140 b.n 800a4e0 { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 800a25e: 687b ldr r3, [r7, #4] 800a260: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a264: b2db uxtb r3, r3 800a266: 2b02 cmp r3, #2 800a268: d002 beq.n 800a270 800a26a: 2b03 cmp r3, #3 800a26c: d016 beq.n 800a29c 800a26e: e02c b.n 800a2ca { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 800a270: 7bbb ldrb r3, [r7, #14] 800a272: 2b00 cmp r3, #0 800a274: d00d beq.n 800a292 800a276: 7bbb ldrb r3, [r7, #14] 800a278: 2b80 cmp r3, #128 @ 0x80 800a27a: d00a beq.n 800a292 { (void)USBD_LL_StallEP(pdev, ep_addr); 800a27c: 7bbb ldrb r3, [r7, #14] 800a27e: 4619 mov r1, r3 800a280: 6878 ldr r0, [r7, #4] 800a282: f001 f8e3 bl 800b44c (void)USBD_LL_StallEP(pdev, 0x80U); 800a286: 2180 movs r1, #128 @ 0x80 800a288: 6878 ldr r0, [r7, #4] 800a28a: f001 f8df bl 800b44c 800a28e: bf00 nop } else { USBD_CtlError(pdev, req); } break; 800a290: e020 b.n 800a2d4 USBD_CtlError(pdev, req); 800a292: 6839 ldr r1, [r7, #0] 800a294: 6878 ldr r0, [r7, #4] 800a296: f000 fca6 bl 800abe6 break; 800a29a: e01b b.n 800a2d4 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 800a29c: 683b ldr r3, [r7, #0] 800a29e: 885b ldrh r3, [r3, #2] 800a2a0: 2b00 cmp r3, #0 800a2a2: d10e bne.n 800a2c2 { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 800a2a4: 7bbb ldrb r3, [r7, #14] 800a2a6: 2b00 cmp r3, #0 800a2a8: d00b beq.n 800a2c2 800a2aa: 7bbb ldrb r3, [r7, #14] 800a2ac: 2b80 cmp r3, #128 @ 0x80 800a2ae: d008 beq.n 800a2c2 800a2b0: 683b ldr r3, [r7, #0] 800a2b2: 88db ldrh r3, [r3, #6] 800a2b4: 2b00 cmp r3, #0 800a2b6: d104 bne.n 800a2c2 { (void)USBD_LL_StallEP(pdev, ep_addr); 800a2b8: 7bbb ldrb r3, [r7, #14] 800a2ba: 4619 mov r1, r3 800a2bc: 6878 ldr r0, [r7, #4] 800a2be: f001 f8c5 bl 800b44c } } (void)USBD_CtlSendStatus(pdev); 800a2c2: 6878 ldr r0, [r7, #4] 800a2c4: f000 fd4c bl 800ad60 break; 800a2c8: e004 b.n 800a2d4 default: USBD_CtlError(pdev, req); 800a2ca: 6839 ldr r1, [r7, #0] 800a2cc: 6878 ldr r0, [r7, #4] 800a2ce: f000 fc8a bl 800abe6 break; 800a2d2: bf00 nop } break; 800a2d4: e109 b.n 800a4ea case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 800a2d6: 687b ldr r3, [r7, #4] 800a2d8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a2dc: b2db uxtb r3, r3 800a2de: 2b02 cmp r3, #2 800a2e0: d002 beq.n 800a2e8 800a2e2: 2b03 cmp r3, #3 800a2e4: d016 beq.n 800a314 800a2e6: e04b b.n 800a380 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 800a2e8: 7bbb ldrb r3, [r7, #14] 800a2ea: 2b00 cmp r3, #0 800a2ec: d00d beq.n 800a30a 800a2ee: 7bbb ldrb r3, [r7, #14] 800a2f0: 2b80 cmp r3, #128 @ 0x80 800a2f2: d00a beq.n 800a30a { (void)USBD_LL_StallEP(pdev, ep_addr); 800a2f4: 7bbb ldrb r3, [r7, #14] 800a2f6: 4619 mov r1, r3 800a2f8: 6878 ldr r0, [r7, #4] 800a2fa: f001 f8a7 bl 800b44c (void)USBD_LL_StallEP(pdev, 0x80U); 800a2fe: 2180 movs r1, #128 @ 0x80 800a300: 6878 ldr r0, [r7, #4] 800a302: f001 f8a3 bl 800b44c 800a306: bf00 nop } else { USBD_CtlError(pdev, req); } break; 800a308: e040 b.n 800a38c USBD_CtlError(pdev, req); 800a30a: 6839 ldr r1, [r7, #0] 800a30c: 6878 ldr r0, [r7, #4] 800a30e: f000 fc6a bl 800abe6 break; 800a312: e03b b.n 800a38c case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 800a314: 683b ldr r3, [r7, #0] 800a316: 885b ldrh r3, [r3, #2] 800a318: 2b00 cmp r3, #0 800a31a: d136 bne.n 800a38a { if ((ep_addr & 0x7FU) != 0x00U) 800a31c: 7bbb ldrb r3, [r7, #14] 800a31e: f003 037f and.w r3, r3, #127 @ 0x7f 800a322: 2b00 cmp r3, #0 800a324: d004 beq.n 800a330 { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 800a326: 7bbb ldrb r3, [r7, #14] 800a328: 4619 mov r1, r3 800a32a: 6878 ldr r0, [r7, #4] 800a32c: f001 f8ad bl 800b48a } (void)USBD_CtlSendStatus(pdev); 800a330: 6878 ldr r0, [r7, #4] 800a332: f000 fd15 bl 800ad60 /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ep_addr); 800a336: 7bbb ldrb r3, [r7, #14] 800a338: 4619 mov r1, r3 800a33a: 6878 ldr r0, [r7, #4] 800a33c: f7ff fde3 bl 8009f06 800a340: 4603 mov r3, r0 800a342: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 800a344: 7b7b ldrb r3, [r7, #13] 800a346: 2bff cmp r3, #255 @ 0xff 800a348: d01f beq.n 800a38a 800a34a: 7b7b ldrb r3, [r7, #13] 800a34c: 2b00 cmp r3, #0 800a34e: d11c bne.n 800a38a { pdev->classId = idx; 800a350: 7b7a ldrb r2, [r7, #13] 800a352: 687b ldr r3, [r7, #4] 800a354: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 800a358: 7b7a ldrb r2, [r7, #13] 800a35a: 687b ldr r3, [r7, #4] 800a35c: 32ae adds r2, #174 @ 0xae 800a35e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a362: 689b ldr r3, [r3, #8] 800a364: 2b00 cmp r3, #0 800a366: d010 beq.n 800a38a { ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 800a368: 7b7a ldrb r2, [r7, #13] 800a36a: 687b ldr r3, [r7, #4] 800a36c: 32ae adds r2, #174 @ 0xae 800a36e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a372: 689b ldr r3, [r3, #8] 800a374: 6839 ldr r1, [r7, #0] 800a376: 6878 ldr r0, [r7, #4] 800a378: 4798 blx r3 800a37a: 4603 mov r3, r0 800a37c: 73fb strb r3, [r7, #15] } } } break; 800a37e: e004 b.n 800a38a default: USBD_CtlError(pdev, req); 800a380: 6839 ldr r1, [r7, #0] 800a382: 6878 ldr r0, [r7, #4] 800a384: f000 fc2f bl 800abe6 break; 800a388: e000 b.n 800a38c break; 800a38a: bf00 nop } break; 800a38c: e0ad b.n 800a4ea case USB_REQ_GET_STATUS: switch (pdev->dev_state) 800a38e: 687b ldr r3, [r7, #4] 800a390: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a394: b2db uxtb r3, r3 800a396: 2b02 cmp r3, #2 800a398: d002 beq.n 800a3a0 800a39a: 2b03 cmp r3, #3 800a39c: d033 beq.n 800a406 800a39e: e099 b.n 800a4d4 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 800a3a0: 7bbb ldrb r3, [r7, #14] 800a3a2: 2b00 cmp r3, #0 800a3a4: d007 beq.n 800a3b6 800a3a6: 7bbb ldrb r3, [r7, #14] 800a3a8: 2b80 cmp r3, #128 @ 0x80 800a3aa: d004 beq.n 800a3b6 { USBD_CtlError(pdev, req); 800a3ac: 6839 ldr r1, [r7, #0] 800a3ae: 6878 ldr r0, [r7, #4] 800a3b0: f000 fc19 bl 800abe6 break; 800a3b4: e093 b.n 800a4de } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800a3b6: f997 300e ldrsb.w r3, [r7, #14] 800a3ba: 2b00 cmp r3, #0 800a3bc: da0b bge.n 800a3d6 800a3be: 7bbb ldrb r3, [r7, #14] 800a3c0: f003 027f and.w r2, r3, #127 @ 0x7f 800a3c4: 4613 mov r3, r2 800a3c6: 009b lsls r3, r3, #2 800a3c8: 4413 add r3, r2 800a3ca: 009b lsls r3, r3, #2 800a3cc: 3310 adds r3, #16 800a3ce: 687a ldr r2, [r7, #4] 800a3d0: 4413 add r3, r2 800a3d2: 3304 adds r3, #4 800a3d4: e00b b.n 800a3ee &pdev->ep_out[ep_addr & 0x7FU]; 800a3d6: 7bbb ldrb r3, [r7, #14] 800a3d8: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800a3dc: 4613 mov r3, r2 800a3de: 009b lsls r3, r3, #2 800a3e0: 4413 add r3, r2 800a3e2: 009b lsls r3, r3, #2 800a3e4: f503 73a8 add.w r3, r3, #336 @ 0x150 800a3e8: 687a ldr r2, [r7, #4] 800a3ea: 4413 add r3, r2 800a3ec: 3304 adds r3, #4 800a3ee: 60bb str r3, [r7, #8] pep->status = 0x0000U; 800a3f0: 68bb ldr r3, [r7, #8] 800a3f2: 2200 movs r2, #0 800a3f4: 739a strb r2, [r3, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 800a3f6: 68bb ldr r3, [r7, #8] 800a3f8: 330e adds r3, #14 800a3fa: 2202 movs r2, #2 800a3fc: 4619 mov r1, r3 800a3fe: 6878 ldr r0, [r7, #4] 800a400: f000 fc6e bl 800ace0 break; 800a404: e06b b.n 800a4de case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 800a406: f997 300e ldrsb.w r3, [r7, #14] 800a40a: 2b00 cmp r3, #0 800a40c: da11 bge.n 800a432 { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 800a40e: 7bbb ldrb r3, [r7, #14] 800a410: f003 020f and.w r2, r3, #15 800a414: 6879 ldr r1, [r7, #4] 800a416: 4613 mov r3, r2 800a418: 009b lsls r3, r3, #2 800a41a: 4413 add r3, r2 800a41c: 009b lsls r3, r3, #2 800a41e: 440b add r3, r1 800a420: 3323 adds r3, #35 @ 0x23 800a422: 781b ldrb r3, [r3, #0] 800a424: 2b00 cmp r3, #0 800a426: d117 bne.n 800a458 { USBD_CtlError(pdev, req); 800a428: 6839 ldr r1, [r7, #0] 800a42a: 6878 ldr r0, [r7, #4] 800a42c: f000 fbdb bl 800abe6 break; 800a430: e055 b.n 800a4de } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 800a432: 7bbb ldrb r3, [r7, #14] 800a434: f003 020f and.w r2, r3, #15 800a438: 6879 ldr r1, [r7, #4] 800a43a: 4613 mov r3, r2 800a43c: 009b lsls r3, r3, #2 800a43e: 4413 add r3, r2 800a440: 009b lsls r3, r3, #2 800a442: 440b add r3, r1 800a444: f203 1363 addw r3, r3, #355 @ 0x163 800a448: 781b ldrb r3, [r3, #0] 800a44a: 2b00 cmp r3, #0 800a44c: d104 bne.n 800a458 { USBD_CtlError(pdev, req); 800a44e: 6839 ldr r1, [r7, #0] 800a450: 6878 ldr r0, [r7, #4] 800a452: f000 fbc8 bl 800abe6 break; 800a456: e042 b.n 800a4de } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800a458: f997 300e ldrsb.w r3, [r7, #14] 800a45c: 2b00 cmp r3, #0 800a45e: da0b bge.n 800a478 800a460: 7bbb ldrb r3, [r7, #14] 800a462: f003 027f and.w r2, r3, #127 @ 0x7f 800a466: 4613 mov r3, r2 800a468: 009b lsls r3, r3, #2 800a46a: 4413 add r3, r2 800a46c: 009b lsls r3, r3, #2 800a46e: 3310 adds r3, #16 800a470: 687a ldr r2, [r7, #4] 800a472: 4413 add r3, r2 800a474: 3304 adds r3, #4 800a476: e00b b.n 800a490 &pdev->ep_out[ep_addr & 0x7FU]; 800a478: 7bbb ldrb r3, [r7, #14] 800a47a: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800a47e: 4613 mov r3, r2 800a480: 009b lsls r3, r3, #2 800a482: 4413 add r3, r2 800a484: 009b lsls r3, r3, #2 800a486: f503 73a8 add.w r3, r3, #336 @ 0x150 800a48a: 687a ldr r2, [r7, #4] 800a48c: 4413 add r3, r2 800a48e: 3304 adds r3, #4 800a490: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 800a492: 7bbb ldrb r3, [r7, #14] 800a494: 2b00 cmp r3, #0 800a496: d002 beq.n 800a49e 800a498: 7bbb ldrb r3, [r7, #14] 800a49a: 2b80 cmp r3, #128 @ 0x80 800a49c: d103 bne.n 800a4a6 { pep->status = 0x0000U; 800a49e: 68bb ldr r3, [r7, #8] 800a4a0: 2200 movs r2, #0 800a4a2: 739a strb r2, [r3, #14] 800a4a4: e00e b.n 800a4c4 } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 800a4a6: 7bbb ldrb r3, [r7, #14] 800a4a8: 4619 mov r1, r3 800a4aa: 6878 ldr r0, [r7, #4] 800a4ac: f001 f80c bl 800b4c8 800a4b0: 4603 mov r3, r0 800a4b2: 2b00 cmp r3, #0 800a4b4: d003 beq.n 800a4be { pep->status = 0x0001U; 800a4b6: 68bb ldr r3, [r7, #8] 800a4b8: 2201 movs r2, #1 800a4ba: 739a strb r2, [r3, #14] 800a4bc: e002 b.n 800a4c4 } else { pep->status = 0x0000U; 800a4be: 68bb ldr r3, [r7, #8] 800a4c0: 2200 movs r2, #0 800a4c2: 739a strb r2, [r3, #14] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 800a4c4: 68bb ldr r3, [r7, #8] 800a4c6: 330e adds r3, #14 800a4c8: 2202 movs r2, #2 800a4ca: 4619 mov r1, r3 800a4cc: 6878 ldr r0, [r7, #4] 800a4ce: f000 fc07 bl 800ace0 break; 800a4d2: e004 b.n 800a4de default: USBD_CtlError(pdev, req); 800a4d4: 6839 ldr r1, [r7, #0] 800a4d6: 6878 ldr r0, [r7, #4] 800a4d8: f000 fb85 bl 800abe6 break; 800a4dc: bf00 nop } break; 800a4de: e004 b.n 800a4ea default: USBD_CtlError(pdev, req); 800a4e0: 6839 ldr r1, [r7, #0] 800a4e2: 6878 ldr r0, [r7, #4] 800a4e4: f000 fb7f bl 800abe6 break; 800a4e8: bf00 nop } break; 800a4ea: e005 b.n 800a4f8 default: USBD_CtlError(pdev, req); 800a4ec: 6839 ldr r1, [r7, #0] 800a4ee: 6878 ldr r0, [r7, #4] 800a4f0: f000 fb79 bl 800abe6 break; 800a4f4: e000 b.n 800a4f8 break; 800a4f6: bf00 nop } return ret; 800a4f8: 7bfb ldrb r3, [r7, #15] } 800a4fa: 4618 mov r0, r3 800a4fc: 3710 adds r7, #16 800a4fe: 46bd mov sp, r7 800a500: bd80 pop {r7, pc} ... 0800a504 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a504: b580 push {r7, lr} 800a506: b084 sub sp, #16 800a508: af00 add r7, sp, #0 800a50a: 6078 str r0, [r7, #4] 800a50c: 6039 str r1, [r7, #0] uint16_t len = 0U; 800a50e: 2300 movs r3, #0 800a510: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 800a512: 2300 movs r3, #0 800a514: 60fb str r3, [r7, #12] uint8_t err = 0U; 800a516: 2300 movs r3, #0 800a518: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 800a51a: 683b ldr r3, [r7, #0] 800a51c: 885b ldrh r3, [r3, #2] 800a51e: 0a1b lsrs r3, r3, #8 800a520: b29b uxth r3, r3 800a522: 3b01 subs r3, #1 800a524: 2b0e cmp r3, #14 800a526: f200 8152 bhi.w 800a7ce 800a52a: a201 add r2, pc, #4 @ (adr r2, 800a530 ) 800a52c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a530: 0800a5a1 .word 0x0800a5a1 800a534: 0800a5b9 .word 0x0800a5b9 800a538: 0800a5f9 .word 0x0800a5f9 800a53c: 0800a7cf .word 0x0800a7cf 800a540: 0800a7cf .word 0x0800a7cf 800a544: 0800a76f .word 0x0800a76f 800a548: 0800a79b .word 0x0800a79b 800a54c: 0800a7cf .word 0x0800a7cf 800a550: 0800a7cf .word 0x0800a7cf 800a554: 0800a7cf .word 0x0800a7cf 800a558: 0800a7cf .word 0x0800a7cf 800a55c: 0800a7cf .word 0x0800a7cf 800a560: 0800a7cf .word 0x0800a7cf 800a564: 0800a7cf .word 0x0800a7cf 800a568: 0800a56d .word 0x0800a56d { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) 800a56c: 687b ldr r3, [r7, #4] 800a56e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a572: 69db ldr r3, [r3, #28] 800a574: 2b00 cmp r3, #0 800a576: d00b beq.n 800a590 { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); 800a578: 687b ldr r3, [r7, #4] 800a57a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a57e: 69db ldr r3, [r3, #28] 800a580: 687a ldr r2, [r7, #4] 800a582: 7c12 ldrb r2, [r2, #16] 800a584: f107 0108 add.w r1, r7, #8 800a588: 4610 mov r0, r2 800a58a: 4798 blx r3 800a58c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a58e: e126 b.n 800a7de USBD_CtlError(pdev, req); 800a590: 6839 ldr r1, [r7, #0] 800a592: 6878 ldr r0, [r7, #4] 800a594: f000 fb27 bl 800abe6 err++; 800a598: 7afb ldrb r3, [r7, #11] 800a59a: 3301 adds r3, #1 800a59c: 72fb strb r3, [r7, #11] break; 800a59e: e11e b.n 800a7de #endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 800a5a0: 687b ldr r3, [r7, #4] 800a5a2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a5a6: 681b ldr r3, [r3, #0] 800a5a8: 687a ldr r2, [r7, #4] 800a5aa: 7c12 ldrb r2, [r2, #16] 800a5ac: f107 0108 add.w r1, r7, #8 800a5b0: 4610 mov r0, r2 800a5b2: 4798 blx r3 800a5b4: 60f8 str r0, [r7, #12] break; 800a5b6: e112 b.n 800a7de case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 800a5b8: 687b ldr r3, [r7, #4] 800a5ba: 7c1b ldrb r3, [r3, #16] 800a5bc: 2b00 cmp r3, #0 800a5be: d10d bne.n 800a5dc pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); 800a5c0: 687b ldr r3, [r7, #4] 800a5c2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800a5c6: 6a9b ldr r3, [r3, #40] @ 0x28 800a5c8: f107 0208 add.w r2, r7, #8 800a5cc: 4610 mov r0, r2 800a5ce: 4798 blx r3 800a5d0: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800a5d2: 68fb ldr r3, [r7, #12] 800a5d4: 3301 adds r3, #1 800a5d6: 2202 movs r2, #2 800a5d8: 701a strb r2, [r3, #0] { pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 800a5da: e100 b.n 800a7de pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); 800a5dc: 687b ldr r3, [r7, #4] 800a5de: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800a5e2: 6adb ldr r3, [r3, #44] @ 0x2c 800a5e4: f107 0208 add.w r2, r7, #8 800a5e8: 4610 mov r0, r2 800a5ea: 4798 blx r3 800a5ec: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800a5ee: 68fb ldr r3, [r7, #12] 800a5f0: 3301 adds r3, #1 800a5f2: 2202 movs r2, #2 800a5f4: 701a strb r2, [r3, #0] break; 800a5f6: e0f2 b.n 800a7de case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 800a5f8: 683b ldr r3, [r7, #0] 800a5fa: 885b ldrh r3, [r3, #2] 800a5fc: b2db uxtb r3, r3 800a5fe: 2b05 cmp r3, #5 800a600: f200 80ac bhi.w 800a75c 800a604: a201 add r2, pc, #4 @ (adr r2, 800a60c ) 800a606: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a60a: bf00 nop 800a60c: 0800a625 .word 0x0800a625 800a610: 0800a659 .word 0x0800a659 800a614: 0800a68d .word 0x0800a68d 800a618: 0800a6c1 .word 0x0800a6c1 800a61c: 0800a6f5 .word 0x0800a6f5 800a620: 0800a729 .word 0x0800a729 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 800a624: 687b ldr r3, [r7, #4] 800a626: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a62a: 685b ldr r3, [r3, #4] 800a62c: 2b00 cmp r3, #0 800a62e: d00b beq.n 800a648 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 800a630: 687b ldr r3, [r7, #4] 800a632: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a636: 685b ldr r3, [r3, #4] 800a638: 687a ldr r2, [r7, #4] 800a63a: 7c12 ldrb r2, [r2, #16] 800a63c: f107 0108 add.w r1, r7, #8 800a640: 4610 mov r0, r2 800a642: 4798 blx r3 800a644: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a646: e091 b.n 800a76c USBD_CtlError(pdev, req); 800a648: 6839 ldr r1, [r7, #0] 800a64a: 6878 ldr r0, [r7, #4] 800a64c: f000 facb bl 800abe6 err++; 800a650: 7afb ldrb r3, [r7, #11] 800a652: 3301 adds r3, #1 800a654: 72fb strb r3, [r7, #11] break; 800a656: e089 b.n 800a76c case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 800a658: 687b ldr r3, [r7, #4] 800a65a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a65e: 689b ldr r3, [r3, #8] 800a660: 2b00 cmp r3, #0 800a662: d00b beq.n 800a67c { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 800a664: 687b ldr r3, [r7, #4] 800a666: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a66a: 689b ldr r3, [r3, #8] 800a66c: 687a ldr r2, [r7, #4] 800a66e: 7c12 ldrb r2, [r2, #16] 800a670: f107 0108 add.w r1, r7, #8 800a674: 4610 mov r0, r2 800a676: 4798 blx r3 800a678: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a67a: e077 b.n 800a76c USBD_CtlError(pdev, req); 800a67c: 6839 ldr r1, [r7, #0] 800a67e: 6878 ldr r0, [r7, #4] 800a680: f000 fab1 bl 800abe6 err++; 800a684: 7afb ldrb r3, [r7, #11] 800a686: 3301 adds r3, #1 800a688: 72fb strb r3, [r7, #11] break; 800a68a: e06f b.n 800a76c case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 800a68c: 687b ldr r3, [r7, #4] 800a68e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a692: 68db ldr r3, [r3, #12] 800a694: 2b00 cmp r3, #0 800a696: d00b beq.n 800a6b0 { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 800a698: 687b ldr r3, [r7, #4] 800a69a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a69e: 68db ldr r3, [r3, #12] 800a6a0: 687a ldr r2, [r7, #4] 800a6a2: 7c12 ldrb r2, [r2, #16] 800a6a4: f107 0108 add.w r1, r7, #8 800a6a8: 4610 mov r0, r2 800a6aa: 4798 blx r3 800a6ac: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a6ae: e05d b.n 800a76c USBD_CtlError(pdev, req); 800a6b0: 6839 ldr r1, [r7, #0] 800a6b2: 6878 ldr r0, [r7, #4] 800a6b4: f000 fa97 bl 800abe6 err++; 800a6b8: 7afb ldrb r3, [r7, #11] 800a6ba: 3301 adds r3, #1 800a6bc: 72fb strb r3, [r7, #11] break; 800a6be: e055 b.n 800a76c case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 800a6c0: 687b ldr r3, [r7, #4] 800a6c2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a6c6: 691b ldr r3, [r3, #16] 800a6c8: 2b00 cmp r3, #0 800a6ca: d00b beq.n 800a6e4 { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 800a6cc: 687b ldr r3, [r7, #4] 800a6ce: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a6d2: 691b ldr r3, [r3, #16] 800a6d4: 687a ldr r2, [r7, #4] 800a6d6: 7c12 ldrb r2, [r2, #16] 800a6d8: f107 0108 add.w r1, r7, #8 800a6dc: 4610 mov r0, r2 800a6de: 4798 blx r3 800a6e0: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a6e2: e043 b.n 800a76c USBD_CtlError(pdev, req); 800a6e4: 6839 ldr r1, [r7, #0] 800a6e6: 6878 ldr r0, [r7, #4] 800a6e8: f000 fa7d bl 800abe6 err++; 800a6ec: 7afb ldrb r3, [r7, #11] 800a6ee: 3301 adds r3, #1 800a6f0: 72fb strb r3, [r7, #11] break; 800a6f2: e03b b.n 800a76c case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 800a6f4: 687b ldr r3, [r7, #4] 800a6f6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a6fa: 695b ldr r3, [r3, #20] 800a6fc: 2b00 cmp r3, #0 800a6fe: d00b beq.n 800a718 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 800a700: 687b ldr r3, [r7, #4] 800a702: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a706: 695b ldr r3, [r3, #20] 800a708: 687a ldr r2, [r7, #4] 800a70a: 7c12 ldrb r2, [r2, #16] 800a70c: f107 0108 add.w r1, r7, #8 800a710: 4610 mov r0, r2 800a712: 4798 blx r3 800a714: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a716: e029 b.n 800a76c USBD_CtlError(pdev, req); 800a718: 6839 ldr r1, [r7, #0] 800a71a: 6878 ldr r0, [r7, #4] 800a71c: f000 fa63 bl 800abe6 err++; 800a720: 7afb ldrb r3, [r7, #11] 800a722: 3301 adds r3, #1 800a724: 72fb strb r3, [r7, #11] break; 800a726: e021 b.n 800a76c case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 800a728: 687b ldr r3, [r7, #4] 800a72a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a72e: 699b ldr r3, [r3, #24] 800a730: 2b00 cmp r3, #0 800a732: d00b beq.n 800a74c { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 800a734: 687b ldr r3, [r7, #4] 800a736: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a73a: 699b ldr r3, [r3, #24] 800a73c: 687a ldr r2, [r7, #4] 800a73e: 7c12 ldrb r2, [r2, #16] 800a740: f107 0108 add.w r1, r7, #8 800a744: 4610 mov r0, r2 800a746: 4798 blx r3 800a748: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a74a: e00f b.n 800a76c USBD_CtlError(pdev, req); 800a74c: 6839 ldr r1, [r7, #0] 800a74e: 6878 ldr r0, [r7, #4] 800a750: f000 fa49 bl 800abe6 err++; 800a754: 7afb ldrb r3, [r7, #11] 800a756: 3301 adds r3, #1 800a758: 72fb strb r3, [r7, #11] break; 800a75a: e007 b.n 800a76c err++; } #endif /* USBD_SUPPORT_USER_STRING_DESC */ #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 800a75c: 6839 ldr r1, [r7, #0] 800a75e: 6878 ldr r0, [r7, #4] 800a760: f000 fa41 bl 800abe6 err++; 800a764: 7afb ldrb r3, [r7, #11] 800a766: 3301 adds r3, #1 800a768: 72fb strb r3, [r7, #11] #endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ break; 800a76a: bf00 nop } break; 800a76c: e037 b.n 800a7de case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 800a76e: 687b ldr r3, [r7, #4] 800a770: 7c1b ldrb r3, [r3, #16] 800a772: 2b00 cmp r3, #0 800a774: d109 bne.n 800a78a pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); 800a776: 687b ldr r3, [r7, #4] 800a778: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800a77c: 6b5b ldr r3, [r3, #52] @ 0x34 800a77e: f107 0208 add.w r2, r7, #8 800a782: 4610 mov r0, r2 800a784: 4798 blx r3 800a786: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a788: e029 b.n 800a7de USBD_CtlError(pdev, req); 800a78a: 6839 ldr r1, [r7, #0] 800a78c: 6878 ldr r0, [r7, #4] 800a78e: f000 fa2a bl 800abe6 err++; 800a792: 7afb ldrb r3, [r7, #11] 800a794: 3301 adds r3, #1 800a796: 72fb strb r3, [r7, #11] break; 800a798: e021 b.n 800a7de case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 800a79a: 687b ldr r3, [r7, #4] 800a79c: 7c1b ldrb r3, [r3, #16] 800a79e: 2b00 cmp r3, #0 800a7a0: d10d bne.n 800a7be pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); 800a7a2: 687b ldr r3, [r7, #4] 800a7a4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800a7a8: 6b1b ldr r3, [r3, #48] @ 0x30 800a7aa: f107 0208 add.w r2, r7, #8 800a7ae: 4610 mov r0, r2 800a7b0: 4798 blx r3 800a7b2: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 800a7b4: 68fb ldr r3, [r7, #12] 800a7b6: 3301 adds r3, #1 800a7b8: 2207 movs r2, #7 800a7ba: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 800a7bc: e00f b.n 800a7de USBD_CtlError(pdev, req); 800a7be: 6839 ldr r1, [r7, #0] 800a7c0: 6878 ldr r0, [r7, #4] 800a7c2: f000 fa10 bl 800abe6 err++; 800a7c6: 7afb ldrb r3, [r7, #11] 800a7c8: 3301 adds r3, #1 800a7ca: 72fb strb r3, [r7, #11] break; 800a7cc: e007 b.n 800a7de default: USBD_CtlError(pdev, req); 800a7ce: 6839 ldr r1, [r7, #0] 800a7d0: 6878 ldr r0, [r7, #4] 800a7d2: f000 fa08 bl 800abe6 err++; 800a7d6: 7afb ldrb r3, [r7, #11] 800a7d8: 3301 adds r3, #1 800a7da: 72fb strb r3, [r7, #11] break; 800a7dc: bf00 nop } if (err != 0U) 800a7de: 7afb ldrb r3, [r7, #11] 800a7e0: 2b00 cmp r3, #0 800a7e2: d11e bne.n 800a822 { return; } if (req->wLength != 0U) 800a7e4: 683b ldr r3, [r7, #0] 800a7e6: 88db ldrh r3, [r3, #6] 800a7e8: 2b00 cmp r3, #0 800a7ea: d016 beq.n 800a81a { if (len != 0U) 800a7ec: 893b ldrh r3, [r7, #8] 800a7ee: 2b00 cmp r3, #0 800a7f0: d00e beq.n 800a810 { len = MIN(len, req->wLength); 800a7f2: 683b ldr r3, [r7, #0] 800a7f4: 88da ldrh r2, [r3, #6] 800a7f6: 893b ldrh r3, [r7, #8] 800a7f8: 4293 cmp r3, r2 800a7fa: bf28 it cs 800a7fc: 4613 movcs r3, r2 800a7fe: b29b uxth r3, r3 800a800: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 800a802: 893b ldrh r3, [r7, #8] 800a804: 461a mov r2, r3 800a806: 68f9 ldr r1, [r7, #12] 800a808: 6878 ldr r0, [r7, #4] 800a80a: f000 fa69 bl 800ace0 800a80e: e009 b.n 800a824 } else { USBD_CtlError(pdev, req); 800a810: 6839 ldr r1, [r7, #0] 800a812: 6878 ldr r0, [r7, #4] 800a814: f000 f9e7 bl 800abe6 800a818: e004 b.n 800a824 } } else { (void)USBD_CtlSendStatus(pdev); 800a81a: 6878 ldr r0, [r7, #4] 800a81c: f000 faa0 bl 800ad60 800a820: e000 b.n 800a824 return; 800a822: bf00 nop } } 800a824: 3710 adds r7, #16 800a826: 46bd mov sp, r7 800a828: bd80 pop {r7, pc} 800a82a: bf00 nop 0800a82c : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a82c: b580 push {r7, lr} 800a82e: b084 sub sp, #16 800a830: af00 add r7, sp, #0 800a832: 6078 str r0, [r7, #4] 800a834: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 800a836: 683b ldr r3, [r7, #0] 800a838: 889b ldrh r3, [r3, #4] 800a83a: 2b00 cmp r3, #0 800a83c: d131 bne.n 800a8a2 800a83e: 683b ldr r3, [r7, #0] 800a840: 88db ldrh r3, [r3, #6] 800a842: 2b00 cmp r3, #0 800a844: d12d bne.n 800a8a2 800a846: 683b ldr r3, [r7, #0] 800a848: 885b ldrh r3, [r3, #2] 800a84a: 2b7f cmp r3, #127 @ 0x7f 800a84c: d829 bhi.n 800a8a2 { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 800a84e: 683b ldr r3, [r7, #0] 800a850: 885b ldrh r3, [r3, #2] 800a852: b2db uxtb r3, r3 800a854: f003 037f and.w r3, r3, #127 @ 0x7f 800a858: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 800a85a: 687b ldr r3, [r7, #4] 800a85c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a860: b2db uxtb r3, r3 800a862: 2b03 cmp r3, #3 800a864: d104 bne.n 800a870 { USBD_CtlError(pdev, req); 800a866: 6839 ldr r1, [r7, #0] 800a868: 6878 ldr r0, [r7, #4] 800a86a: f000 f9bc bl 800abe6 if (pdev->dev_state == USBD_STATE_CONFIGURED) 800a86e: e01d b.n 800a8ac } else { pdev->dev_address = dev_addr; 800a870: 687b ldr r3, [r7, #4] 800a872: 7bfa ldrb r2, [r7, #15] 800a874: f883 229e strb.w r2, [r3, #670] @ 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 800a878: 7bfb ldrb r3, [r7, #15] 800a87a: 4619 mov r1, r3 800a87c: 6878 ldr r0, [r7, #4] 800a87e: f000 fe4f bl 800b520 (void)USBD_CtlSendStatus(pdev); 800a882: 6878 ldr r0, [r7, #4] 800a884: f000 fa6c bl 800ad60 if (dev_addr != 0U) 800a888: 7bfb ldrb r3, [r7, #15] 800a88a: 2b00 cmp r3, #0 800a88c: d004 beq.n 800a898 { pdev->dev_state = USBD_STATE_ADDRESSED; 800a88e: 687b ldr r3, [r7, #4] 800a890: 2202 movs r2, #2 800a892: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 800a896: e009 b.n 800a8ac } else { pdev->dev_state = USBD_STATE_DEFAULT; 800a898: 687b ldr r3, [r7, #4] 800a89a: 2201 movs r2, #1 800a89c: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 800a8a0: e004 b.n 800a8ac } } } else { USBD_CtlError(pdev, req); 800a8a2: 6839 ldr r1, [r7, #0] 800a8a4: 6878 ldr r0, [r7, #4] 800a8a6: f000 f99e bl 800abe6 } } 800a8aa: bf00 nop 800a8ac: bf00 nop 800a8ae: 3710 adds r7, #16 800a8b0: 46bd mov sp, r7 800a8b2: bd80 pop {r7, pc} 0800a8b4 : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a8b4: b580 push {r7, lr} 800a8b6: b084 sub sp, #16 800a8b8: af00 add r7, sp, #0 800a8ba: 6078 str r0, [r7, #4] 800a8bc: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800a8be: 2300 movs r3, #0 800a8c0: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 800a8c2: 683b ldr r3, [r7, #0] 800a8c4: 885b ldrh r3, [r3, #2] 800a8c6: b2da uxtb r2, r3 800a8c8: 4b4e ldr r3, [pc, #312] @ (800aa04 ) 800a8ca: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 800a8cc: 4b4d ldr r3, [pc, #308] @ (800aa04 ) 800a8ce: 781b ldrb r3, [r3, #0] 800a8d0: 2b01 cmp r3, #1 800a8d2: d905 bls.n 800a8e0 { USBD_CtlError(pdev, req); 800a8d4: 6839 ldr r1, [r7, #0] 800a8d6: 6878 ldr r0, [r7, #4] 800a8d8: f000 f985 bl 800abe6 return USBD_FAIL; 800a8dc: 2303 movs r3, #3 800a8de: e08c b.n 800a9fa } switch (pdev->dev_state) 800a8e0: 687b ldr r3, [r7, #4] 800a8e2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a8e6: b2db uxtb r3, r3 800a8e8: 2b02 cmp r3, #2 800a8ea: d002 beq.n 800a8f2 800a8ec: 2b03 cmp r3, #3 800a8ee: d029 beq.n 800a944 800a8f0: e075 b.n 800a9de { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 800a8f2: 4b44 ldr r3, [pc, #272] @ (800aa04 ) 800a8f4: 781b ldrb r3, [r3, #0] 800a8f6: 2b00 cmp r3, #0 800a8f8: d020 beq.n 800a93c { pdev->dev_config = cfgidx; 800a8fa: 4b42 ldr r3, [pc, #264] @ (800aa04 ) 800a8fc: 781b ldrb r3, [r3, #0] 800a8fe: 461a mov r2, r3 800a900: 687b ldr r3, [r7, #4] 800a902: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 800a904: 4b3f ldr r3, [pc, #252] @ (800aa04 ) 800a906: 781b ldrb r3, [r3, #0] 800a908: 4619 mov r1, r3 800a90a: 6878 ldr r0, [r7, #4] 800a90c: f7fe ffa3 bl 8009856 800a910: 4603 mov r3, r0 800a912: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 800a914: 7bfb ldrb r3, [r7, #15] 800a916: 2b00 cmp r3, #0 800a918: d008 beq.n 800a92c { USBD_CtlError(pdev, req); 800a91a: 6839 ldr r1, [r7, #0] 800a91c: 6878 ldr r0, [r7, #4] 800a91e: f000 f962 bl 800abe6 pdev->dev_state = USBD_STATE_ADDRESSED; 800a922: 687b ldr r3, [r7, #4] 800a924: 2202 movs r2, #2 800a926: f883 229c strb.w r2, [r3, #668] @ 0x29c } else { (void)USBD_CtlSendStatus(pdev); } break; 800a92a: e065 b.n 800a9f8 (void)USBD_CtlSendStatus(pdev); 800a92c: 6878 ldr r0, [r7, #4] 800a92e: f000 fa17 bl 800ad60 pdev->dev_state = USBD_STATE_CONFIGURED; 800a932: 687b ldr r3, [r7, #4] 800a934: 2203 movs r2, #3 800a936: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 800a93a: e05d b.n 800a9f8 (void)USBD_CtlSendStatus(pdev); 800a93c: 6878 ldr r0, [r7, #4] 800a93e: f000 fa0f bl 800ad60 break; 800a942: e059 b.n 800a9f8 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 800a944: 4b2f ldr r3, [pc, #188] @ (800aa04 ) 800a946: 781b ldrb r3, [r3, #0] 800a948: 2b00 cmp r3, #0 800a94a: d112 bne.n 800a972 { pdev->dev_state = USBD_STATE_ADDRESSED; 800a94c: 687b ldr r3, [r7, #4] 800a94e: 2202 movs r2, #2 800a950: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->dev_config = cfgidx; 800a954: 4b2b ldr r3, [pc, #172] @ (800aa04 ) 800a956: 781b ldrb r3, [r3, #0] 800a958: 461a mov r2, r3 800a95a: 687b ldr r3, [r7, #4] 800a95c: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 800a95e: 4b29 ldr r3, [pc, #164] @ (800aa04 ) 800a960: 781b ldrb r3, [r3, #0] 800a962: 4619 mov r1, r3 800a964: 6878 ldr r0, [r7, #4] 800a966: f7fe ff92 bl 800988e (void)USBD_CtlSendStatus(pdev); 800a96a: 6878 ldr r0, [r7, #4] 800a96c: f000 f9f8 bl 800ad60 } else { (void)USBD_CtlSendStatus(pdev); } break; 800a970: e042 b.n 800a9f8 else if (cfgidx != pdev->dev_config) 800a972: 4b24 ldr r3, [pc, #144] @ (800aa04 ) 800a974: 781b ldrb r3, [r3, #0] 800a976: 461a mov r2, r3 800a978: 687b ldr r3, [r7, #4] 800a97a: 685b ldr r3, [r3, #4] 800a97c: 429a cmp r2, r3 800a97e: d02a beq.n 800a9d6 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 800a980: 687b ldr r3, [r7, #4] 800a982: 685b ldr r3, [r3, #4] 800a984: b2db uxtb r3, r3 800a986: 4619 mov r1, r3 800a988: 6878 ldr r0, [r7, #4] 800a98a: f7fe ff80 bl 800988e pdev->dev_config = cfgidx; 800a98e: 4b1d ldr r3, [pc, #116] @ (800aa04 ) 800a990: 781b ldrb r3, [r3, #0] 800a992: 461a mov r2, r3 800a994: 687b ldr r3, [r7, #4] 800a996: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 800a998: 4b1a ldr r3, [pc, #104] @ (800aa04 ) 800a99a: 781b ldrb r3, [r3, #0] 800a99c: 4619 mov r1, r3 800a99e: 6878 ldr r0, [r7, #4] 800a9a0: f7fe ff59 bl 8009856 800a9a4: 4603 mov r3, r0 800a9a6: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 800a9a8: 7bfb ldrb r3, [r7, #15] 800a9aa: 2b00 cmp r3, #0 800a9ac: d00f beq.n 800a9ce USBD_CtlError(pdev, req); 800a9ae: 6839 ldr r1, [r7, #0] 800a9b0: 6878 ldr r0, [r7, #4] 800a9b2: f000 f918 bl 800abe6 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 800a9b6: 687b ldr r3, [r7, #4] 800a9b8: 685b ldr r3, [r3, #4] 800a9ba: b2db uxtb r3, r3 800a9bc: 4619 mov r1, r3 800a9be: 6878 ldr r0, [r7, #4] 800a9c0: f7fe ff65 bl 800988e pdev->dev_state = USBD_STATE_ADDRESSED; 800a9c4: 687b ldr r3, [r7, #4] 800a9c6: 2202 movs r2, #2 800a9c8: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 800a9cc: e014 b.n 800a9f8 (void)USBD_CtlSendStatus(pdev); 800a9ce: 6878 ldr r0, [r7, #4] 800a9d0: f000 f9c6 bl 800ad60 break; 800a9d4: e010 b.n 800a9f8 (void)USBD_CtlSendStatus(pdev); 800a9d6: 6878 ldr r0, [r7, #4] 800a9d8: f000 f9c2 bl 800ad60 break; 800a9dc: e00c b.n 800a9f8 default: USBD_CtlError(pdev, req); 800a9de: 6839 ldr r1, [r7, #0] 800a9e0: 6878 ldr r0, [r7, #4] 800a9e2: f000 f900 bl 800abe6 (void)USBD_ClrClassConfig(pdev, cfgidx); 800a9e6: 4b07 ldr r3, [pc, #28] @ (800aa04 ) 800a9e8: 781b ldrb r3, [r3, #0] 800a9ea: 4619 mov r1, r3 800a9ec: 6878 ldr r0, [r7, #4] 800a9ee: f7fe ff4e bl 800988e ret = USBD_FAIL; 800a9f2: 2303 movs r3, #3 800a9f4: 73fb strb r3, [r7, #15] break; 800a9f6: bf00 nop } return ret; 800a9f8: 7bfb ldrb r3, [r7, #15] } 800a9fa: 4618 mov r0, r3 800a9fc: 3710 adds r7, #16 800a9fe: 46bd mov sp, r7 800aa00: bd80 pop {r7, pc} 800aa02: bf00 nop 800aa04: 20000f04 .word 0x20000f04 0800aa08 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800aa08: b580 push {r7, lr} 800aa0a: b082 sub sp, #8 800aa0c: af00 add r7, sp, #0 800aa0e: 6078 str r0, [r7, #4] 800aa10: 6039 str r1, [r7, #0] if (req->wLength != 1U) 800aa12: 683b ldr r3, [r7, #0] 800aa14: 88db ldrh r3, [r3, #6] 800aa16: 2b01 cmp r3, #1 800aa18: d004 beq.n 800aa24 { USBD_CtlError(pdev, req); 800aa1a: 6839 ldr r1, [r7, #0] 800aa1c: 6878 ldr r0, [r7, #4] 800aa1e: f000 f8e2 bl 800abe6 default: USBD_CtlError(pdev, req); break; } } } 800aa22: e023 b.n 800aa6c switch (pdev->dev_state) 800aa24: 687b ldr r3, [r7, #4] 800aa26: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800aa2a: b2db uxtb r3, r3 800aa2c: 2b02 cmp r3, #2 800aa2e: dc02 bgt.n 800aa36 800aa30: 2b00 cmp r3, #0 800aa32: dc03 bgt.n 800aa3c 800aa34: e015 b.n 800aa62 800aa36: 2b03 cmp r3, #3 800aa38: d00b beq.n 800aa52 800aa3a: e012 b.n 800aa62 pdev->dev_default_config = 0U; 800aa3c: 687b ldr r3, [r7, #4] 800aa3e: 2200 movs r2, #0 800aa40: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 800aa42: 687b ldr r3, [r7, #4] 800aa44: 3308 adds r3, #8 800aa46: 2201 movs r2, #1 800aa48: 4619 mov r1, r3 800aa4a: 6878 ldr r0, [r7, #4] 800aa4c: f000 f948 bl 800ace0 break; 800aa50: e00c b.n 800aa6c (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 800aa52: 687b ldr r3, [r7, #4] 800aa54: 3304 adds r3, #4 800aa56: 2201 movs r2, #1 800aa58: 4619 mov r1, r3 800aa5a: 6878 ldr r0, [r7, #4] 800aa5c: f000 f940 bl 800ace0 break; 800aa60: e004 b.n 800aa6c USBD_CtlError(pdev, req); 800aa62: 6839 ldr r1, [r7, #0] 800aa64: 6878 ldr r0, [r7, #4] 800aa66: f000 f8be bl 800abe6 break; 800aa6a: bf00 nop } 800aa6c: bf00 nop 800aa6e: 3708 adds r7, #8 800aa70: 46bd mov sp, r7 800aa72: bd80 pop {r7, pc} 0800aa74 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800aa74: b580 push {r7, lr} 800aa76: b082 sub sp, #8 800aa78: af00 add r7, sp, #0 800aa7a: 6078 str r0, [r7, #4] 800aa7c: 6039 str r1, [r7, #0] switch (pdev->dev_state) 800aa7e: 687b ldr r3, [r7, #4] 800aa80: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800aa84: b2db uxtb r3, r3 800aa86: 3b01 subs r3, #1 800aa88: 2b02 cmp r3, #2 800aa8a: d81e bhi.n 800aaca { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 800aa8c: 683b ldr r3, [r7, #0] 800aa8e: 88db ldrh r3, [r3, #6] 800aa90: 2b02 cmp r3, #2 800aa92: d004 beq.n 800aa9e { USBD_CtlError(pdev, req); 800aa94: 6839 ldr r1, [r7, #0] 800aa96: 6878 ldr r0, [r7, #4] 800aa98: f000 f8a5 bl 800abe6 break; 800aa9c: e01a b.n 800aad4 } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 800aa9e: 687b ldr r3, [r7, #4] 800aaa0: 2201 movs r2, #1 800aaa2: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif /* USBD_SELF_POWERED */ if (pdev->dev_remote_wakeup != 0U) 800aaa4: 687b ldr r3, [r7, #4] 800aaa6: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 800aaaa: 2b00 cmp r3, #0 800aaac: d005 beq.n 800aaba { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 800aaae: 687b ldr r3, [r7, #4] 800aab0: 68db ldr r3, [r3, #12] 800aab2: f043 0202 orr.w r2, r3, #2 800aab6: 687b ldr r3, [r7, #4] 800aab8: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 800aaba: 687b ldr r3, [r7, #4] 800aabc: 330c adds r3, #12 800aabe: 2202 movs r2, #2 800aac0: 4619 mov r1, r3 800aac2: 6878 ldr r0, [r7, #4] 800aac4: f000 f90c bl 800ace0 break; 800aac8: e004 b.n 800aad4 default: USBD_CtlError(pdev, req); 800aaca: 6839 ldr r1, [r7, #0] 800aacc: 6878 ldr r0, [r7, #4] 800aace: f000 f88a bl 800abe6 break; 800aad2: bf00 nop } } 800aad4: bf00 nop 800aad6: 3708 adds r7, #8 800aad8: 46bd mov sp, r7 800aada: bd80 pop {r7, pc} 0800aadc : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800aadc: b580 push {r7, lr} 800aade: b082 sub sp, #8 800aae0: af00 add r7, sp, #0 800aae2: 6078 str r0, [r7, #4] 800aae4: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 800aae6: 683b ldr r3, [r7, #0] 800aae8: 885b ldrh r3, [r3, #2] 800aaea: 2b01 cmp r3, #1 800aaec: d107 bne.n 800aafe { pdev->dev_remote_wakeup = 1U; 800aaee: 687b ldr r3, [r7, #4] 800aaf0: 2201 movs r2, #1 800aaf2: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 800aaf6: 6878 ldr r0, [r7, #4] 800aaf8: f000 f932 bl 800ad60 } else { USBD_CtlError(pdev, req); } } 800aafc: e013 b.n 800ab26 else if (req->wValue == USB_FEATURE_TEST_MODE) 800aafe: 683b ldr r3, [r7, #0] 800ab00: 885b ldrh r3, [r3, #2] 800ab02: 2b02 cmp r3, #2 800ab04: d10b bne.n 800ab1e pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); 800ab06: 683b ldr r3, [r7, #0] 800ab08: 889b ldrh r3, [r3, #4] 800ab0a: 0a1b lsrs r3, r3, #8 800ab0c: b29b uxth r3, r3 800ab0e: b2da uxtb r2, r3 800ab10: 687b ldr r3, [r7, #4] 800ab12: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 (void)USBD_CtlSendStatus(pdev); 800ab16: 6878 ldr r0, [r7, #4] 800ab18: f000 f922 bl 800ad60 } 800ab1c: e003 b.n 800ab26 USBD_CtlError(pdev, req); 800ab1e: 6839 ldr r1, [r7, #0] 800ab20: 6878 ldr r0, [r7, #4] 800ab22: f000 f860 bl 800abe6 } 800ab26: bf00 nop 800ab28: 3708 adds r7, #8 800ab2a: 46bd mov sp, r7 800ab2c: bd80 pop {r7, pc} 0800ab2e : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800ab2e: b580 push {r7, lr} 800ab30: b082 sub sp, #8 800ab32: af00 add r7, sp, #0 800ab34: 6078 str r0, [r7, #4] 800ab36: 6039 str r1, [r7, #0] switch (pdev->dev_state) 800ab38: 687b ldr r3, [r7, #4] 800ab3a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800ab3e: b2db uxtb r3, r3 800ab40: 3b01 subs r3, #1 800ab42: 2b02 cmp r3, #2 800ab44: d80b bhi.n 800ab5e { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 800ab46: 683b ldr r3, [r7, #0] 800ab48: 885b ldrh r3, [r3, #2] 800ab4a: 2b01 cmp r3, #1 800ab4c: d10c bne.n 800ab68 { pdev->dev_remote_wakeup = 0U; 800ab4e: 687b ldr r3, [r7, #4] 800ab50: 2200 movs r2, #0 800ab52: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 800ab56: 6878 ldr r0, [r7, #4] 800ab58: f000 f902 bl 800ad60 } break; 800ab5c: e004 b.n 800ab68 default: USBD_CtlError(pdev, req); 800ab5e: 6839 ldr r1, [r7, #0] 800ab60: 6878 ldr r0, [r7, #4] 800ab62: f000 f840 bl 800abe6 break; 800ab66: e000 b.n 800ab6a break; 800ab68: bf00 nop } } 800ab6a: bf00 nop 800ab6c: 3708 adds r7, #8 800ab6e: 46bd mov sp, r7 800ab70: bd80 pop {r7, pc} 0800ab72 : * @param req: usb request * @param pdata: setup data pointer * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 800ab72: b580 push {r7, lr} 800ab74: b084 sub sp, #16 800ab76: af00 add r7, sp, #0 800ab78: 6078 str r0, [r7, #4] 800ab7a: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 800ab7c: 683b ldr r3, [r7, #0] 800ab7e: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 800ab80: 68fb ldr r3, [r7, #12] 800ab82: 781a ldrb r2, [r3, #0] 800ab84: 687b ldr r3, [r7, #4] 800ab86: 701a strb r2, [r3, #0] pbuff++; 800ab88: 68fb ldr r3, [r7, #12] 800ab8a: 3301 adds r3, #1 800ab8c: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 800ab8e: 68fb ldr r3, [r7, #12] 800ab90: 781a ldrb r2, [r3, #0] 800ab92: 687b ldr r3, [r7, #4] 800ab94: 705a strb r2, [r3, #1] pbuff++; 800ab96: 68fb ldr r3, [r7, #12] 800ab98: 3301 adds r3, #1 800ab9a: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 800ab9c: 68f8 ldr r0, [r7, #12] 800ab9e: f7ff fa13 bl 8009fc8 800aba2: 4603 mov r3, r0 800aba4: 461a mov r2, r3 800aba6: 687b ldr r3, [r7, #4] 800aba8: 805a strh r2, [r3, #2] pbuff++; 800abaa: 68fb ldr r3, [r7, #12] 800abac: 3301 adds r3, #1 800abae: 60fb str r3, [r7, #12] pbuff++; 800abb0: 68fb ldr r3, [r7, #12] 800abb2: 3301 adds r3, #1 800abb4: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 800abb6: 68f8 ldr r0, [r7, #12] 800abb8: f7ff fa06 bl 8009fc8 800abbc: 4603 mov r3, r0 800abbe: 461a mov r2, r3 800abc0: 687b ldr r3, [r7, #4] 800abc2: 809a strh r2, [r3, #4] pbuff++; 800abc4: 68fb ldr r3, [r7, #12] 800abc6: 3301 adds r3, #1 800abc8: 60fb str r3, [r7, #12] pbuff++; 800abca: 68fb ldr r3, [r7, #12] 800abcc: 3301 adds r3, #1 800abce: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 800abd0: 68f8 ldr r0, [r7, #12] 800abd2: f7ff f9f9 bl 8009fc8 800abd6: 4603 mov r3, r0 800abd8: 461a mov r2, r3 800abda: 687b ldr r3, [r7, #4] 800abdc: 80da strh r2, [r3, #6] } 800abde: bf00 nop 800abe0: 3710 adds r7, #16 800abe2: 46bd mov sp, r7 800abe4: bd80 pop {r7, pc} 0800abe6 : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800abe6: b580 push {r7, lr} 800abe8: b082 sub sp, #8 800abea: af00 add r7, sp, #0 800abec: 6078 str r0, [r7, #4] 800abee: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 800abf0: 2180 movs r1, #128 @ 0x80 800abf2: 6878 ldr r0, [r7, #4] 800abf4: f000 fc2a bl 800b44c (void)USBD_LL_StallEP(pdev, 0U); 800abf8: 2100 movs r1, #0 800abfa: 6878 ldr r0, [r7, #4] 800abfc: f000 fc26 bl 800b44c } 800ac00: bf00 nop 800ac02: 3708 adds r7, #8 800ac04: 46bd mov sp, r7 800ac06: bd80 pop {r7, pc} 0800ac08 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 800ac08: b580 push {r7, lr} 800ac0a: b086 sub sp, #24 800ac0c: af00 add r7, sp, #0 800ac0e: 60f8 str r0, [r7, #12] 800ac10: 60b9 str r1, [r7, #8] 800ac12: 607a str r2, [r7, #4] uint8_t idx = 0U; 800ac14: 2300 movs r3, #0 800ac16: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 800ac18: 68fb ldr r3, [r7, #12] 800ac1a: 2b00 cmp r3, #0 800ac1c: d042 beq.n 800aca4 { return; } pdesc = desc; 800ac1e: 68fb ldr r3, [r7, #12] 800ac20: 613b str r3, [r7, #16] *len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U); 800ac22: 6938 ldr r0, [r7, #16] 800ac24: f000 f842 bl 800acac 800ac28: 4603 mov r3, r0 800ac2a: 3301 adds r3, #1 800ac2c: 005b lsls r3, r3, #1 800ac2e: f5b3 7f00 cmp.w r3, #512 @ 0x200 800ac32: d808 bhi.n 800ac46 800ac34: 6938 ldr r0, [r7, #16] 800ac36: f000 f839 bl 800acac 800ac3a: 4603 mov r3, r0 800ac3c: 3301 adds r3, #1 800ac3e: b29b uxth r3, r3 800ac40: 005b lsls r3, r3, #1 800ac42: b29a uxth r2, r3 800ac44: e001 b.n 800ac4a 800ac46: f44f 7200 mov.w r2, #512 @ 0x200 800ac4a: 687b ldr r3, [r7, #4] 800ac4c: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 800ac4e: 7dfb ldrb r3, [r7, #23] 800ac50: 68ba ldr r2, [r7, #8] 800ac52: 4413 add r3, r2 800ac54: 687a ldr r2, [r7, #4] 800ac56: 7812 ldrb r2, [r2, #0] 800ac58: 701a strb r2, [r3, #0] idx++; 800ac5a: 7dfb ldrb r3, [r7, #23] 800ac5c: 3301 adds r3, #1 800ac5e: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 800ac60: 7dfb ldrb r3, [r7, #23] 800ac62: 68ba ldr r2, [r7, #8] 800ac64: 4413 add r3, r2 800ac66: 2203 movs r2, #3 800ac68: 701a strb r2, [r3, #0] idx++; 800ac6a: 7dfb ldrb r3, [r7, #23] 800ac6c: 3301 adds r3, #1 800ac6e: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 800ac70: e013 b.n 800ac9a { unicode[idx] = *pdesc; 800ac72: 7dfb ldrb r3, [r7, #23] 800ac74: 68ba ldr r2, [r7, #8] 800ac76: 4413 add r3, r2 800ac78: 693a ldr r2, [r7, #16] 800ac7a: 7812 ldrb r2, [r2, #0] 800ac7c: 701a strb r2, [r3, #0] pdesc++; 800ac7e: 693b ldr r3, [r7, #16] 800ac80: 3301 adds r3, #1 800ac82: 613b str r3, [r7, #16] idx++; 800ac84: 7dfb ldrb r3, [r7, #23] 800ac86: 3301 adds r3, #1 800ac88: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 800ac8a: 7dfb ldrb r3, [r7, #23] 800ac8c: 68ba ldr r2, [r7, #8] 800ac8e: 4413 add r3, r2 800ac90: 2200 movs r2, #0 800ac92: 701a strb r2, [r3, #0] idx++; 800ac94: 7dfb ldrb r3, [r7, #23] 800ac96: 3301 adds r3, #1 800ac98: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 800ac9a: 693b ldr r3, [r7, #16] 800ac9c: 781b ldrb r3, [r3, #0] 800ac9e: 2b00 cmp r3, #0 800aca0: d1e7 bne.n 800ac72 800aca2: e000 b.n 800aca6 return; 800aca4: bf00 nop } } 800aca6: 3718 adds r7, #24 800aca8: 46bd mov sp, r7 800acaa: bd80 pop {r7, pc} 0800acac : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 800acac: b480 push {r7} 800acae: b085 sub sp, #20 800acb0: af00 add r7, sp, #0 800acb2: 6078 str r0, [r7, #4] uint8_t len = 0U; 800acb4: 2300 movs r3, #0 800acb6: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 800acb8: 687b ldr r3, [r7, #4] 800acba: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 800acbc: e005 b.n 800acca { len++; 800acbe: 7bfb ldrb r3, [r7, #15] 800acc0: 3301 adds r3, #1 800acc2: 73fb strb r3, [r7, #15] pbuff++; 800acc4: 68bb ldr r3, [r7, #8] 800acc6: 3301 adds r3, #1 800acc8: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 800acca: 68bb ldr r3, [r7, #8] 800accc: 781b ldrb r3, [r3, #0] 800acce: 2b00 cmp r3, #0 800acd0: d1f5 bne.n 800acbe } return len; 800acd2: 7bfb ldrb r3, [r7, #15] } 800acd4: 4618 mov r0, r3 800acd6: 3714 adds r7, #20 800acd8: 46bd mov sp, r7 800acda: f85d 7b04 ldr.w r7, [sp], #4 800acde: 4770 bx lr 0800ace0 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800ace0: b580 push {r7, lr} 800ace2: b084 sub sp, #16 800ace4: af00 add r7, sp, #0 800ace6: 60f8 str r0, [r7, #12] 800ace8: 60b9 str r1, [r7, #8] 800acea: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 800acec: 68fb ldr r3, [r7, #12] 800acee: 2202 movs r2, #2 800acf0: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_in[0].total_length = len; 800acf4: 68fb ldr r3, [r7, #12] 800acf6: 687a ldr r2, [r7, #4] 800acf8: 615a str r2, [r3, #20] pdev->ep_in[0].pbuffer = pbuf; 800acfa: 68fb ldr r3, [r7, #12] 800acfc: 68ba ldr r2, [r7, #8] 800acfe: 625a str r2, [r3, #36] @ 0x24 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 800ad00: 68fb ldr r3, [r7, #12] 800ad02: 687a ldr r2, [r7, #4] 800ad04: 619a str r2, [r3, #24] #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800ad06: 687b ldr r3, [r7, #4] 800ad08: 68ba ldr r2, [r7, #8] 800ad0a: 2100 movs r1, #0 800ad0c: 68f8 ldr r0, [r7, #12] 800ad0e: f000 fc26 bl 800b55e return USBD_OK; 800ad12: 2300 movs r3, #0 } 800ad14: 4618 mov r0, r3 800ad16: 3710 adds r7, #16 800ad18: 46bd mov sp, r7 800ad1a: bd80 pop {r7, pc} 0800ad1c : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800ad1c: b580 push {r7, lr} 800ad1e: b084 sub sp, #16 800ad20: af00 add r7, sp, #0 800ad22: 60f8 str r0, [r7, #12] 800ad24: 60b9 str r1, [r7, #8] 800ad26: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800ad28: 687b ldr r3, [r7, #4] 800ad2a: 68ba ldr r2, [r7, #8] 800ad2c: 2100 movs r1, #0 800ad2e: 68f8 ldr r0, [r7, #12] 800ad30: f000 fc15 bl 800b55e return USBD_OK; 800ad34: 2300 movs r3, #0 } 800ad36: 4618 mov r0, r3 800ad38: 3710 adds r7, #16 800ad3a: 46bd mov sp, r7 800ad3c: bd80 pop {r7, pc} 0800ad3e : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800ad3e: b580 push {r7, lr} 800ad40: b084 sub sp, #16 800ad42: af00 add r7, sp, #0 800ad44: 60f8 str r0, [r7, #12] 800ad46: 60b9 str r1, [r7, #8] 800ad48: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 800ad4a: 687b ldr r3, [r7, #4] 800ad4c: 68ba ldr r2, [r7, #8] 800ad4e: 2100 movs r1, #0 800ad50: 68f8 ldr r0, [r7, #12] 800ad52: f000 fc25 bl 800b5a0 return USBD_OK; 800ad56: 2300 movs r3, #0 } 800ad58: 4618 mov r0, r3 800ad5a: 3710 adds r7, #16 800ad5c: 46bd mov sp, r7 800ad5e: bd80 pop {r7, pc} 0800ad60 : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 800ad60: b580 push {r7, lr} 800ad62: b082 sub sp, #8 800ad64: af00 add r7, sp, #0 800ad66: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 800ad68: 687b ldr r3, [r7, #4] 800ad6a: 2204 movs r2, #4 800ad6c: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 800ad70: 2300 movs r3, #0 800ad72: 2200 movs r2, #0 800ad74: 2100 movs r1, #0 800ad76: 6878 ldr r0, [r7, #4] 800ad78: f000 fbf1 bl 800b55e return USBD_OK; 800ad7c: 2300 movs r3, #0 } 800ad7e: 4618 mov r0, r3 800ad80: 3708 adds r7, #8 800ad82: 46bd mov sp, r7 800ad84: bd80 pop {r7, pc} 0800ad86 : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 800ad86: b580 push {r7, lr} 800ad88: b082 sub sp, #8 800ad8a: af00 add r7, sp, #0 800ad8c: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 800ad8e: 687b ldr r3, [r7, #4] 800ad90: 2205 movs r2, #5 800ad92: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 800ad96: 2300 movs r3, #0 800ad98: 2200 movs r2, #0 800ad9a: 2100 movs r1, #0 800ad9c: 6878 ldr r0, [r7, #4] 800ad9e: f000 fbff bl 800b5a0 return USBD_OK; 800ada2: 2300 movs r3, #0 } 800ada4: 4618 mov r0, r3 800ada6: 3708 adds r7, #8 800ada8: 46bd mov sp, r7 800adaa: bd80 pop {r7, pc} 0800adac : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 800adac: b580 push {r7, lr} 800adae: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) 800adb0: 2200 movs r2, #0 800adb2: 490e ldr r1, [pc, #56] @ (800adec ) 800adb4: 480e ldr r0, [pc, #56] @ (800adf0 ) 800adb6: f7fe fcd1 bl 800975c 800adba: 4603 mov r3, r0 800adbc: 2b00 cmp r3, #0 800adbe: d001 beq.n 800adc4 { Error_Handler(); 800adc0: f7f6 fa68 bl 8001294 } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) 800adc4: 490b ldr r1, [pc, #44] @ (800adf4 ) 800adc6: 480a ldr r0, [pc, #40] @ (800adf0 ) 800adc8: f7fe fcf8 bl 80097bc 800adcc: 4603 mov r3, r0 800adce: 2b00 cmp r3, #0 800add0: d001 beq.n 800add6 { Error_Handler(); 800add2: f7f6 fa5f bl 8001294 } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) 800add6: 4806 ldr r0, [pc, #24] @ (800adf0 ) 800add8: f7fe fd26 bl 8009828 800addc: 4603 mov r3, r0 800adde: 2b00 cmp r3, #0 800ade0: d001 beq.n 800ade6 { Error_Handler(); 800ade2: f7f6 fa57 bl 8001294 } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 800ade6: bf00 nop 800ade8: bd80 pop {r7, pc} 800adea: bf00 nop 800adec: 20000140 .word 0x20000140 800adf0: 20000f08 .word 0x20000f08 800adf4: 2000009c .word 0x2000009c 0800adf8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800adf8: b480 push {r7} 800adfa: b083 sub sp, #12 800adfc: af00 add r7, sp, #0 800adfe: 4603 mov r3, r0 800ae00: 6039 str r1, [r7, #0] 800ae02: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_DeviceDesc); 800ae04: 683b ldr r3, [r7, #0] 800ae06: 2212 movs r2, #18 800ae08: 801a strh r2, [r3, #0] return USBD_FS_DeviceDesc; 800ae0a: 4b03 ldr r3, [pc, #12] @ (800ae18 ) } 800ae0c: 4618 mov r0, r3 800ae0e: 370c adds r7, #12 800ae10: 46bd mov sp, r7 800ae12: f85d 7b04 ldr.w r7, [sp], #4 800ae16: 4770 bx lr 800ae18: 20000160 .word 0x20000160 0800ae1c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800ae1c: b480 push {r7} 800ae1e: b083 sub sp, #12 800ae20: af00 add r7, sp, #0 800ae22: 4603 mov r3, r0 800ae24: 6039 str r1, [r7, #0] 800ae26: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 800ae28: 683b ldr r3, [r7, #0] 800ae2a: 2204 movs r2, #4 800ae2c: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 800ae2e: 4b03 ldr r3, [pc, #12] @ (800ae3c ) } 800ae30: 4618 mov r0, r3 800ae32: 370c adds r7, #12 800ae34: 46bd mov sp, r7 800ae36: f85d 7b04 ldr.w r7, [sp], #4 800ae3a: 4770 bx lr 800ae3c: 20000180 .word 0x20000180 0800ae40 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800ae40: b580 push {r7, lr} 800ae42: b082 sub sp, #8 800ae44: af00 add r7, sp, #0 800ae46: 4603 mov r3, r0 800ae48: 6039 str r1, [r7, #0] 800ae4a: 71fb strb r3, [r7, #7] if(speed == 0) 800ae4c: 79fb ldrb r3, [r7, #7] 800ae4e: 2b00 cmp r3, #0 800ae50: d105 bne.n 800ae5e { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800ae52: 683a ldr r2, [r7, #0] 800ae54: 4907 ldr r1, [pc, #28] @ (800ae74 ) 800ae56: 4808 ldr r0, [pc, #32] @ (800ae78 ) 800ae58: f7ff fed6 bl 800ac08 800ae5c: e004 b.n 800ae68 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800ae5e: 683a ldr r2, [r7, #0] 800ae60: 4904 ldr r1, [pc, #16] @ (800ae74 ) 800ae62: 4805 ldr r0, [pc, #20] @ (800ae78 ) 800ae64: f7ff fed0 bl 800ac08 } return USBD_StrDesc; 800ae68: 4b02 ldr r3, [pc, #8] @ (800ae74 ) } 800ae6a: 4618 mov r0, r3 800ae6c: 3708 adds r7, #8 800ae6e: 46bd mov sp, r7 800ae70: bd80 pop {r7, pc} 800ae72: bf00 nop 800ae74: 200011e4 .word 0x200011e4 800ae78: 0800b794 .word 0x0800b794 0800ae7c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800ae7c: b580 push {r7, lr} 800ae7e: b082 sub sp, #8 800ae80: af00 add r7, sp, #0 800ae82: 4603 mov r3, r0 800ae84: 6039 str r1, [r7, #0] 800ae86: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 800ae88: 683a ldr r2, [r7, #0] 800ae8a: 4904 ldr r1, [pc, #16] @ (800ae9c ) 800ae8c: 4804 ldr r0, [pc, #16] @ (800aea0 ) 800ae8e: f7ff febb bl 800ac08 return USBD_StrDesc; 800ae92: 4b02 ldr r3, [pc, #8] @ (800ae9c ) } 800ae94: 4618 mov r0, r3 800ae96: 3708 adds r7, #8 800ae98: 46bd mov sp, r7 800ae9a: bd80 pop {r7, pc} 800ae9c: 200011e4 .word 0x200011e4 800aea0: 0800b7a8 .word 0x0800b7a8 0800aea4 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800aea4: b580 push {r7, lr} 800aea6: b082 sub sp, #8 800aea8: af00 add r7, sp, #0 800aeaa: 4603 mov r3, r0 800aeac: 6039 str r1, [r7, #0] 800aeae: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 800aeb0: 683b ldr r3, [r7, #0] 800aeb2: 221a movs r2, #26 800aeb4: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 800aeb6: f000 f855 bl 800af64 /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ /* USER CODE END USBD_FS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 800aeba: 4b02 ldr r3, [pc, #8] @ (800aec4 ) } 800aebc: 4618 mov r0, r3 800aebe: 3708 adds r7, #8 800aec0: 46bd mov sp, r7 800aec2: bd80 pop {r7, pc} 800aec4: 20000184 .word 0x20000184 0800aec8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800aec8: b580 push {r7, lr} 800aeca: b082 sub sp, #8 800aecc: af00 add r7, sp, #0 800aece: 4603 mov r3, r0 800aed0: 6039 str r1, [r7, #0] 800aed2: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 800aed4: 79fb ldrb r3, [r7, #7] 800aed6: 2b00 cmp r3, #0 800aed8: d105 bne.n 800aee6 { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800aeda: 683a ldr r2, [r7, #0] 800aedc: 4907 ldr r1, [pc, #28] @ (800aefc ) 800aede: 4808 ldr r0, [pc, #32] @ (800af00 ) 800aee0: f7ff fe92 bl 800ac08 800aee4: e004 b.n 800aef0 } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800aee6: 683a ldr r2, [r7, #0] 800aee8: 4904 ldr r1, [pc, #16] @ (800aefc ) 800aeea: 4805 ldr r0, [pc, #20] @ (800af00 ) 800aeec: f7ff fe8c bl 800ac08 } return USBD_StrDesc; 800aef0: 4b02 ldr r3, [pc, #8] @ (800aefc ) } 800aef2: 4618 mov r0, r3 800aef4: 3708 adds r7, #8 800aef6: 46bd mov sp, r7 800aef8: bd80 pop {r7, pc} 800aefa: bf00 nop 800aefc: 200011e4 .word 0x200011e4 800af00: 0800b7b4 .word 0x0800b7b4 0800af04 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800af04: b580 push {r7, lr} 800af06: b082 sub sp, #8 800af08: af00 add r7, sp, #0 800af0a: 4603 mov r3, r0 800af0c: 6039 str r1, [r7, #0] 800af0e: 71fb strb r3, [r7, #7] if(speed == 0) 800af10: 79fb ldrb r3, [r7, #7] 800af12: 2b00 cmp r3, #0 800af14: d105 bne.n 800af22 { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800af16: 683a ldr r2, [r7, #0] 800af18: 4907 ldr r1, [pc, #28] @ (800af38 ) 800af1a: 4808 ldr r0, [pc, #32] @ (800af3c ) 800af1c: f7ff fe74 bl 800ac08 800af20: e004 b.n 800af2c } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800af22: 683a ldr r2, [r7, #0] 800af24: 4904 ldr r1, [pc, #16] @ (800af38 ) 800af26: 4805 ldr r0, [pc, #20] @ (800af3c ) 800af28: f7ff fe6e bl 800ac08 } return USBD_StrDesc; 800af2c: 4b02 ldr r3, [pc, #8] @ (800af38 ) } 800af2e: 4618 mov r0, r3 800af30: 3708 adds r7, #8 800af32: 46bd mov sp, r7 800af34: bd80 pop {r7, pc} 800af36: bf00 nop 800af38: 200011e4 .word 0x200011e4 800af3c: 0800b7c0 .word 0x0800b7c0 0800af40 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800af40: b480 push {r7} 800af42: b083 sub sp, #12 800af44: af00 add r7, sp, #0 800af46: 4603 mov r3, r0 800af48: 6039 str r1, [r7, #0] 800af4a: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_BOSDesc); 800af4c: 683b ldr r3, [r7, #0] 800af4e: 220c movs r2, #12 800af50: 801a strh r2, [r3, #0] return (uint8_t*)USBD_FS_BOSDesc; 800af52: 4b03 ldr r3, [pc, #12] @ (800af60 ) } 800af54: 4618 mov r0, r3 800af56: 370c adds r7, #12 800af58: 46bd mov sp, r7 800af5a: f85d 7b04 ldr.w r7, [sp], #4 800af5e: 4770 bx lr 800af60: 20000174 .word 0x20000174 0800af64 : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 800af64: b580 push {r7, lr} 800af66: b084 sub sp, #16 800af68: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 800af6a: 4b0f ldr r3, [pc, #60] @ (800afa8 ) 800af6c: 681b ldr r3, [r3, #0] 800af6e: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 800af70: 4b0e ldr r3, [pc, #56] @ (800afac ) 800af72: 681b ldr r3, [r3, #0] 800af74: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 800af76: 4b0e ldr r3, [pc, #56] @ (800afb0 ) 800af78: 681b ldr r3, [r3, #0] 800af7a: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 800af7c: 68fa ldr r2, [r7, #12] 800af7e: 687b ldr r3, [r7, #4] 800af80: 4413 add r3, r2 800af82: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 800af84: 68fb ldr r3, [r7, #12] 800af86: 2b00 cmp r3, #0 800af88: d009 beq.n 800af9e { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 800af8a: 2208 movs r2, #8 800af8c: 4909 ldr r1, [pc, #36] @ (800afb4 ) 800af8e: 68f8 ldr r0, [r7, #12] 800af90: f000 f814 bl 800afbc IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 800af94: 2204 movs r2, #4 800af96: 4908 ldr r1, [pc, #32] @ (800afb8 ) 800af98: 68b8 ldr r0, [r7, #8] 800af9a: f000 f80f bl 800afbc } } 800af9e: bf00 nop 800afa0: 3710 adds r7, #16 800afa2: 46bd mov sp, r7 800afa4: bd80 pop {r7, pc} 800afa6: bf00 nop 800afa8: 1fff7a10 .word 0x1fff7a10 800afac: 1fff7a14 .word 0x1fff7a14 800afb0: 1fff7a18 .word 0x1fff7a18 800afb4: 20000186 .word 0x20000186 800afb8: 20000196 .word 0x20000196 0800afbc : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 800afbc: b480 push {r7} 800afbe: b087 sub sp, #28 800afc0: af00 add r7, sp, #0 800afc2: 60f8 str r0, [r7, #12] 800afc4: 60b9 str r1, [r7, #8] 800afc6: 4613 mov r3, r2 800afc8: 71fb strb r3, [r7, #7] uint8_t idx = 0; 800afca: 2300 movs r3, #0 800afcc: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 800afce: 2300 movs r3, #0 800afd0: 75fb strb r3, [r7, #23] 800afd2: e027 b.n 800b024 { if (((value >> 28)) < 0xA) 800afd4: 68fb ldr r3, [r7, #12] 800afd6: 0f1b lsrs r3, r3, #28 800afd8: 2b09 cmp r3, #9 800afda: d80b bhi.n 800aff4 { pbuf[2 * idx] = (value >> 28) + '0'; 800afdc: 68fb ldr r3, [r7, #12] 800afde: 0f1b lsrs r3, r3, #28 800afe0: b2da uxtb r2, r3 800afe2: 7dfb ldrb r3, [r7, #23] 800afe4: 005b lsls r3, r3, #1 800afe6: 4619 mov r1, r3 800afe8: 68bb ldr r3, [r7, #8] 800afea: 440b add r3, r1 800afec: 3230 adds r2, #48 @ 0x30 800afee: b2d2 uxtb r2, r2 800aff0: 701a strb r2, [r3, #0] 800aff2: e00a b.n 800b00a } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 800aff4: 68fb ldr r3, [r7, #12] 800aff6: 0f1b lsrs r3, r3, #28 800aff8: b2da uxtb r2, r3 800affa: 7dfb ldrb r3, [r7, #23] 800affc: 005b lsls r3, r3, #1 800affe: 4619 mov r1, r3 800b000: 68bb ldr r3, [r7, #8] 800b002: 440b add r3, r1 800b004: 3237 adds r2, #55 @ 0x37 800b006: b2d2 uxtb r2, r2 800b008: 701a strb r2, [r3, #0] } value = value << 4; 800b00a: 68fb ldr r3, [r7, #12] 800b00c: 011b lsls r3, r3, #4 800b00e: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 800b010: 7dfb ldrb r3, [r7, #23] 800b012: 005b lsls r3, r3, #1 800b014: 3301 adds r3, #1 800b016: 68ba ldr r2, [r7, #8] 800b018: 4413 add r3, r2 800b01a: 2200 movs r2, #0 800b01c: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 800b01e: 7dfb ldrb r3, [r7, #23] 800b020: 3301 adds r3, #1 800b022: 75fb strb r3, [r7, #23] 800b024: 7dfa ldrb r2, [r7, #23] 800b026: 79fb ldrb r3, [r7, #7] 800b028: 429a cmp r2, r3 800b02a: d3d3 bcc.n 800afd4 } } 800b02c: bf00 nop 800b02e: bf00 nop 800b030: 371c adds r7, #28 800b032: 46bd mov sp, r7 800b034: f85d 7b04 ldr.w r7, [sp], #4 800b038: 4770 bx lr ... 0800b03c : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 800b03c: b580 push {r7, lr} 800b03e: b0a0 sub sp, #128 @ 0x80 800b040: af00 add r7, sp, #0 800b042: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800b044: f107 036c add.w r3, r7, #108 @ 0x6c 800b048: 2200 movs r2, #0 800b04a: 601a str r2, [r3, #0] 800b04c: 605a str r2, [r3, #4] 800b04e: 609a str r2, [r3, #8] 800b050: 60da str r2, [r3, #12] 800b052: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 800b054: f107 0310 add.w r3, r7, #16 800b058: 225c movs r2, #92 @ 0x5c 800b05a: 2100 movs r1, #0 800b05c: 4618 mov r0, r3 800b05e: f000 fb53 bl 800b708 if(pcdHandle->Instance==USB_OTG_FS) 800b062: 687b ldr r3, [r7, #4] 800b064: 681b ldr r3, [r3, #0] 800b066: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800b06a: d149 bne.n 800b100 /* USER CODE END USB_OTG_FS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; 800b06c: f44f 7380 mov.w r3, #256 @ 0x100 800b070: 613b str r3, [r7, #16] PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; 800b072: 2300 movs r3, #0 800b074: 667b str r3, [r7, #100] @ 0x64 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800b076: f107 0310 add.w r3, r7, #16 800b07a: 4618 mov r0, r3 800b07c: f7f9 fb10 bl 80046a0 800b080: 4603 mov r3, r0 800b082: 2b00 cmp r3, #0 800b084: d001 beq.n 800b08a { Error_Handler(); 800b086: f7f6 f905 bl 8001294 } __HAL_RCC_GPIOA_CLK_ENABLE(); 800b08a: 2300 movs r3, #0 800b08c: 60fb str r3, [r7, #12] 800b08e: 4b1e ldr r3, [pc, #120] @ (800b108 ) 800b090: 6b1b ldr r3, [r3, #48] @ 0x30 800b092: 4a1d ldr r2, [pc, #116] @ (800b108 ) 800b094: f043 0301 orr.w r3, r3, #1 800b098: 6313 str r3, [r2, #48] @ 0x30 800b09a: 4b1b ldr r3, [pc, #108] @ (800b108 ) 800b09c: 6b1b ldr r3, [r3, #48] @ 0x30 800b09e: f003 0301 and.w r3, r3, #1 800b0a2: 60fb str r3, [r7, #12] 800b0a4: 68fb ldr r3, [r7, #12] /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 800b0a6: f44f 53c0 mov.w r3, #6144 @ 0x1800 800b0aa: 66fb str r3, [r7, #108] @ 0x6c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800b0ac: 2302 movs r3, #2 800b0ae: 673b str r3, [r7, #112] @ 0x70 GPIO_InitStruct.Pull = GPIO_NOPULL; 800b0b0: 2300 movs r3, #0 800b0b2: 677b str r3, [r7, #116] @ 0x74 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800b0b4: 2303 movs r3, #3 800b0b6: 67bb str r3, [r7, #120] @ 0x78 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 800b0b8: 230a movs r3, #10 800b0ba: 67fb str r3, [r7, #124] @ 0x7c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800b0bc: f107 036c add.w r3, r7, #108 @ 0x6c 800b0c0: 4619 mov r1, r3 800b0c2: 4812 ldr r0, [pc, #72] @ (800b10c ) 800b0c4: f7f7 fc42 bl 800294c /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 800b0c8: 4b0f ldr r3, [pc, #60] @ (800b108 ) 800b0ca: 6b5b ldr r3, [r3, #52] @ 0x34 800b0cc: 4a0e ldr r2, [pc, #56] @ (800b108 ) 800b0ce: f043 0380 orr.w r3, r3, #128 @ 0x80 800b0d2: 6353 str r3, [r2, #52] @ 0x34 800b0d4: 2300 movs r3, #0 800b0d6: 60bb str r3, [r7, #8] 800b0d8: 4b0b ldr r3, [pc, #44] @ (800b108 ) 800b0da: 6c5b ldr r3, [r3, #68] @ 0x44 800b0dc: 4a0a ldr r2, [pc, #40] @ (800b108 ) 800b0de: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800b0e2: 6453 str r3, [r2, #68] @ 0x44 800b0e4: 4b08 ldr r3, [pc, #32] @ (800b108 ) 800b0e6: 6c5b ldr r3, [r3, #68] @ 0x44 800b0e8: f403 4380 and.w r3, r3, #16384 @ 0x4000 800b0ec: 60bb str r3, [r7, #8] 800b0ee: 68bb ldr r3, [r7, #8] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); 800b0f0: 2200 movs r2, #0 800b0f2: 2100 movs r1, #0 800b0f4: 2043 movs r0, #67 @ 0x43 800b0f6: f7f6 fff0 bl 80020da HAL_NVIC_EnableIRQ(OTG_FS_IRQn); 800b0fa: 2043 movs r0, #67 @ 0x43 800b0fc: f7f7 f809 bl 8002112 /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 800b100: bf00 nop 800b102: 3780 adds r7, #128 @ 0x80 800b104: 46bd mov sp, r7 800b106: bd80 pop {r7, pc} 800b108: 40023800 .word 0x40023800 800b10c: 40020000 .word 0x40020000 0800b110 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b110: b580 push {r7, lr} 800b112: b082 sub sp, #8 800b114: af00 add r7, sp, #0 800b116: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 800b118: 687b ldr r3, [r7, #4] 800b11a: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0 800b11e: 687b ldr r3, [r7, #4] 800b120: f203 439c addw r3, r3, #1180 @ 0x49c 800b124: 4619 mov r1, r3 800b126: 4610 mov r0, r2 800b128: f7fe fbcb bl 80098c2 } 800b12c: bf00 nop 800b12e: 3708 adds r7, #8 800b130: 46bd mov sp, r7 800b132: bd80 pop {r7, pc} 0800b134 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b134: b580 push {r7, lr} 800b136: b082 sub sp, #8 800b138: af00 add r7, sp, #0 800b13a: 6078 str r0, [r7, #4] 800b13c: 460b mov r3, r1 800b13e: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 800b140: 687b ldr r3, [r7, #4] 800b142: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800b146: 78fa ldrb r2, [r7, #3] 800b148: 6879 ldr r1, [r7, #4] 800b14a: 4613 mov r3, r2 800b14c: 00db lsls r3, r3, #3 800b14e: 4413 add r3, r2 800b150: 009b lsls r3, r3, #2 800b152: 440b add r3, r1 800b154: f503 7318 add.w r3, r3, #608 @ 0x260 800b158: 681a ldr r2, [r3, #0] 800b15a: 78fb ldrb r3, [r7, #3] 800b15c: 4619 mov r1, r3 800b15e: f7fe fc05 bl 800996c } 800b162: bf00 nop 800b164: 3708 adds r7, #8 800b166: 46bd mov sp, r7 800b168: bd80 pop {r7, pc} 0800b16a : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b16a: b580 push {r7, lr} 800b16c: b082 sub sp, #8 800b16e: af00 add r7, sp, #0 800b170: 6078 str r0, [r7, #4] 800b172: 460b mov r3, r1 800b174: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 800b176: 687b ldr r3, [r7, #4] 800b178: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800b17c: 78fa ldrb r2, [r7, #3] 800b17e: 6879 ldr r1, [r7, #4] 800b180: 4613 mov r3, r2 800b182: 00db lsls r3, r3, #3 800b184: 4413 add r3, r2 800b186: 009b lsls r3, r3, #2 800b188: 440b add r3, r1 800b18a: 3320 adds r3, #32 800b18c: 681a ldr r2, [r3, #0] 800b18e: 78fb ldrb r3, [r7, #3] 800b190: 4619 mov r1, r3 800b192: f7fe fca7 bl 8009ae4 } 800b196: bf00 nop 800b198: 3708 adds r7, #8 800b19a: 46bd mov sp, r7 800b19c: bd80 pop {r7, pc} 0800b19e : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b19e: b580 push {r7, lr} 800b1a0: b082 sub sp, #8 800b1a2: af00 add r7, sp, #0 800b1a4: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 800b1a6: 687b ldr r3, [r7, #4] 800b1a8: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b1ac: 4618 mov r0, r3 800b1ae: f7fe fdeb bl 8009d88 } 800b1b2: bf00 nop 800b1b4: 3708 adds r7, #8 800b1b6: 46bd mov sp, r7 800b1b8: bd80 pop {r7, pc} 0800b1ba : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b1ba: b580 push {r7, lr} 800b1bc: b084 sub sp, #16 800b1be: af00 add r7, sp, #0 800b1c0: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 800b1c2: 2301 movs r3, #1 800b1c4: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed == PCD_SPEED_HIGH) 800b1c6: 687b ldr r3, [r7, #4] 800b1c8: 79db ldrb r3, [r3, #7] 800b1ca: 2b00 cmp r3, #0 800b1cc: d102 bne.n 800b1d4 { speed = USBD_SPEED_HIGH; 800b1ce: 2300 movs r3, #0 800b1d0: 73fb strb r3, [r7, #15] 800b1d2: e008 b.n 800b1e6 } else if ( hpcd->Init.speed == PCD_SPEED_FULL) 800b1d4: 687b ldr r3, [r7, #4] 800b1d6: 79db ldrb r3, [r3, #7] 800b1d8: 2b02 cmp r3, #2 800b1da: d102 bne.n 800b1e2 { speed = USBD_SPEED_FULL; 800b1dc: 2301 movs r3, #1 800b1de: 73fb strb r3, [r7, #15] 800b1e0: e001 b.n 800b1e6 } else { Error_Handler(); 800b1e2: f7f6 f857 bl 8001294 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 800b1e6: 687b ldr r3, [r7, #4] 800b1e8: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b1ec: 7bfa ldrb r2, [r7, #15] 800b1ee: 4611 mov r1, r2 800b1f0: 4618 mov r0, r3 800b1f2: f7fe fd85 bl 8009d00 /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 800b1f6: 687b ldr r3, [r7, #4] 800b1f8: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b1fc: 4618 mov r0, r3 800b1fe: f7fe fd2c bl 8009c5a } 800b202: bf00 nop 800b204: 3710 adds r7, #16 800b206: 46bd mov sp, r7 800b208: bd80 pop {r7, pc} ... 0800b20c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b20c: b580 push {r7, lr} 800b20e: b082 sub sp, #8 800b210: af00 add r7, sp, #0 800b212: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 800b214: 687b ldr r3, [r7, #4] 800b216: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b21a: 4618 mov r0, r3 800b21c: f7fe fd80 bl 8009d20 __HAL_PCD_GATE_PHYCLOCK(hpcd); 800b220: 687b ldr r3, [r7, #4] 800b222: 681b ldr r3, [r3, #0] 800b224: f503 6360 add.w r3, r3, #3584 @ 0xe00 800b228: 681b ldr r3, [r3, #0] 800b22a: 687a ldr r2, [r7, #4] 800b22c: 6812 ldr r2, [r2, #0] 800b22e: f502 6260 add.w r2, r2, #3584 @ 0xe00 800b232: f043 0301 orr.w r3, r3, #1 800b236: 6013 str r3, [r2, #0] /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 800b238: 687b ldr r3, [r7, #4] 800b23a: 7adb ldrb r3, [r3, #11] 800b23c: 2b00 cmp r3, #0 800b23e: d005 beq.n 800b24c { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800b240: 4b04 ldr r3, [pc, #16] @ (800b254 ) 800b242: 691b ldr r3, [r3, #16] 800b244: 4a03 ldr r2, [pc, #12] @ (800b254 ) 800b246: f043 0306 orr.w r3, r3, #6 800b24a: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 800b24c: bf00 nop 800b24e: 3708 adds r7, #8 800b250: 46bd mov sp, r7 800b252: bd80 pop {r7, pc} 800b254: e000ed00 .word 0xe000ed00 0800b258 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b258: b580 push {r7, lr} 800b25a: b082 sub sp, #8 800b25c: af00 add r7, sp, #0 800b25e: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 800b260: 687b ldr r3, [r7, #4] 800b262: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b266: 4618 mov r0, r3 800b268: f7fe fd76 bl 8009d58 } 800b26c: bf00 nop 800b26e: 3708 adds r7, #8 800b270: 46bd mov sp, r7 800b272: bd80 pop {r7, pc} 0800b274 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b274: b580 push {r7, lr} 800b276: b082 sub sp, #8 800b278: af00 add r7, sp, #0 800b27a: 6078 str r0, [r7, #4] 800b27c: 460b mov r3, r1 800b27e: 70fb strb r3, [r7, #3] USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800b280: 687b ldr r3, [r7, #4] 800b282: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b286: 78fa ldrb r2, [r7, #3] 800b288: 4611 mov r1, r2 800b28a: 4618 mov r0, r3 800b28c: f7fe fdce bl 8009e2c } 800b290: bf00 nop 800b292: 3708 adds r7, #8 800b294: 46bd mov sp, r7 800b296: bd80 pop {r7, pc} 0800b298 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b298: b580 push {r7, lr} 800b29a: b082 sub sp, #8 800b29c: af00 add r7, sp, #0 800b29e: 6078 str r0, [r7, #4] 800b2a0: 460b mov r3, r1 800b2a2: 70fb strb r3, [r7, #3] USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800b2a4: 687b ldr r3, [r7, #4] 800b2a6: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b2aa: 78fa ldrb r2, [r7, #3] 800b2ac: 4611 mov r1, r2 800b2ae: 4618 mov r0, r3 800b2b0: f7fe fd8a bl 8009dc8 } 800b2b4: bf00 nop 800b2b6: 3708 adds r7, #8 800b2b8: 46bd mov sp, r7 800b2ba: bd80 pop {r7, pc} 0800b2bc : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b2bc: b580 push {r7, lr} 800b2be: b082 sub sp, #8 800b2c0: af00 add r7, sp, #0 800b2c2: 6078 str r0, [r7, #4] USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); 800b2c4: 687b ldr r3, [r7, #4] 800b2c6: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b2ca: 4618 mov r0, r3 800b2cc: f7fe fde0 bl 8009e90 } 800b2d0: bf00 nop 800b2d2: 3708 adds r7, #8 800b2d4: 46bd mov sp, r7 800b2d6: bd80 pop {r7, pc} 0800b2d8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800b2d8: b580 push {r7, lr} 800b2da: b082 sub sp, #8 800b2dc: af00 add r7, sp, #0 800b2de: 6078 str r0, [r7, #4] USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); 800b2e0: 687b ldr r3, [r7, #4] 800b2e2: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b2e6: 4618 mov r0, r3 800b2e8: f7fe fddd bl 8009ea6 } 800b2ec: bf00 nop 800b2ee: 3708 adds r7, #8 800b2f0: 46bd mov sp, r7 800b2f2: bd80 pop {r7, pc} 0800b2f4 : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 800b2f4: b580 push {r7, lr} 800b2f6: b082 sub sp, #8 800b2f8: af00 add r7, sp, #0 800b2fa: 6078 str r0, [r7, #4] /* Init USB Ip. */ if (pdev->id == DEVICE_FS) { 800b2fc: 687b ldr r3, [r7, #4] 800b2fe: 781b ldrb r3, [r3, #0] 800b300: 2b00 cmp r3, #0 800b302: d13c bne.n 800b37e /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; 800b304: 4a20 ldr r2, [pc, #128] @ (800b388 ) 800b306: 687b ldr r3, [r7, #4] 800b308: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0 pdev->pData = &hpcd_USB_OTG_FS; 800b30c: 687b ldr r3, [r7, #4] 800b30e: 4a1e ldr r2, [pc, #120] @ (800b388 ) 800b310: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8 hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 800b314: 4b1c ldr r3, [pc, #112] @ (800b388 ) 800b316: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 800b31a: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 6; 800b31c: 4b1a ldr r3, [pc, #104] @ (800b388 ) 800b31e: 2206 movs r2, #6 800b320: 711a strb r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 800b322: 4b19 ldr r3, [pc, #100] @ (800b388 ) 800b324: 2202 movs r2, #2 800b326: 71da strb r2, [r3, #7] hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; 800b328: 4b17 ldr r3, [pc, #92] @ (800b388 ) 800b32a: 2200 movs r2, #0 800b32c: 719a strb r2, [r3, #6] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 800b32e: 4b16 ldr r3, [pc, #88] @ (800b388 ) 800b330: 2202 movs r2, #2 800b332: 725a strb r2, [r3, #9] hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; 800b334: 4b14 ldr r3, [pc, #80] @ (800b388 ) 800b336: 2200 movs r2, #0 800b338: 729a strb r2, [r3, #10] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 800b33a: 4b13 ldr r3, [pc, #76] @ (800b388 ) 800b33c: 2200 movs r2, #0 800b33e: 72da strb r2, [r3, #11] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 800b340: 4b11 ldr r3, [pc, #68] @ (800b388 ) 800b342: 2200 movs r2, #0 800b344: 731a strb r2, [r3, #12] hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; 800b346: 4b10 ldr r3, [pc, #64] @ (800b388 ) 800b348: 2200 movs r2, #0 800b34a: 739a strb r2, [r3, #14] hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 800b34c: 4b0e ldr r3, [pc, #56] @ (800b388 ) 800b34e: 2200 movs r2, #0 800b350: 73da strb r2, [r3, #15] if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 800b352: 480d ldr r0, [pc, #52] @ (800b388 ) 800b354: f7f7 fe04 bl 8002f60 800b358: 4603 mov r3, r0 800b35a: 2b00 cmp r3, #0 800b35c: d001 beq.n 800b362 { Error_Handler( ); 800b35e: f7f5 ff99 bl 8001294 HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback); HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); 800b362: 2180 movs r1, #128 @ 0x80 800b364: 4808 ldr r0, [pc, #32] @ (800b388 ) 800b366: f7f9 f84c bl 8004402 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); 800b36a: 2240 movs r2, #64 @ 0x40 800b36c: 2100 movs r1, #0 800b36e: 4806 ldr r0, [pc, #24] @ (800b388 ) 800b370: f7f9 f800 bl 8004374 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); 800b374: 2280 movs r2, #128 @ 0x80 800b376: 2101 movs r1, #1 800b378: 4803 ldr r0, [pc, #12] @ (800b388 ) 800b37a: f7f8 fffb bl 8004374 } return USBD_OK; 800b37e: 2300 movs r3, #0 } 800b380: 4618 mov r0, r3 800b382: 3708 adds r7, #8 800b384: 46bd mov sp, r7 800b386: bd80 pop {r7, pc} 800b388: 200013e4 .word 0x200013e4 0800b38c : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 800b38c: b580 push {r7, lr} 800b38e: b084 sub sp, #16 800b390: af00 add r7, sp, #0 800b392: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 800b394: 2300 movs r3, #0 800b396: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b398: 2300 movs r3, #0 800b39a: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 800b39c: 687b ldr r3, [r7, #4] 800b39e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b3a2: 4618 mov r0, r3 800b3a4: f7f7 fef2 bl 800318c 800b3a8: 4603 mov r3, r0 800b3aa: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b3ac: 7bfb ldrb r3, [r7, #15] 800b3ae: 4618 mov r0, r3 800b3b0: f000 f97e bl 800b6b0 800b3b4: 4603 mov r3, r0 800b3b6: 73bb strb r3, [r7, #14] return usb_status; 800b3b8: 7bbb ldrb r3, [r7, #14] } 800b3ba: 4618 mov r0, r3 800b3bc: 3710 adds r7, #16 800b3be: 46bd mov sp, r7 800b3c0: bd80 pop {r7, pc} 0800b3c2 : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 800b3c2: b580 push {r7, lr} 800b3c4: b084 sub sp, #16 800b3c6: af00 add r7, sp, #0 800b3c8: 6078 str r0, [r7, #4] 800b3ca: 4608 mov r0, r1 800b3cc: 4611 mov r1, r2 800b3ce: 461a mov r2, r3 800b3d0: 4603 mov r3, r0 800b3d2: 70fb strb r3, [r7, #3] 800b3d4: 460b mov r3, r1 800b3d6: 70bb strb r3, [r7, #2] 800b3d8: 4613 mov r3, r2 800b3da: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 800b3dc: 2300 movs r3, #0 800b3de: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b3e0: 2300 movs r3, #0 800b3e2: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 800b3e4: 687b ldr r3, [r7, #4] 800b3e6: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800b3ea: 78bb ldrb r3, [r7, #2] 800b3ec: 883a ldrh r2, [r7, #0] 800b3ee: 78f9 ldrb r1, [r7, #3] 800b3f0: f7f8 fbf3 bl 8003bda 800b3f4: 4603 mov r3, r0 800b3f6: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b3f8: 7bfb ldrb r3, [r7, #15] 800b3fa: 4618 mov r0, r3 800b3fc: f000 f958 bl 800b6b0 800b400: 4603 mov r3, r0 800b402: 73bb strb r3, [r7, #14] return usb_status; 800b404: 7bbb ldrb r3, [r7, #14] } 800b406: 4618 mov r0, r3 800b408: 3710 adds r7, #16 800b40a: 46bd mov sp, r7 800b40c: bd80 pop {r7, pc} 0800b40e : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800b40e: b580 push {r7, lr} 800b410: b084 sub sp, #16 800b412: af00 add r7, sp, #0 800b414: 6078 str r0, [r7, #4] 800b416: 460b mov r3, r1 800b418: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800b41a: 2300 movs r3, #0 800b41c: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b41e: 2300 movs r3, #0 800b420: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 800b422: 687b ldr r3, [r7, #4] 800b424: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b428: 78fa ldrb r2, [r7, #3] 800b42a: 4611 mov r1, r2 800b42c: 4618 mov r0, r3 800b42e: f7f8 fc3e bl 8003cae 800b432: 4603 mov r3, r0 800b434: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b436: 7bfb ldrb r3, [r7, #15] 800b438: 4618 mov r0, r3 800b43a: f000 f939 bl 800b6b0 800b43e: 4603 mov r3, r0 800b440: 73bb strb r3, [r7, #14] return usb_status; 800b442: 7bbb ldrb r3, [r7, #14] } 800b444: 4618 mov r0, r3 800b446: 3710 adds r7, #16 800b448: 46bd mov sp, r7 800b44a: bd80 pop {r7, pc} 0800b44c : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800b44c: b580 push {r7, lr} 800b44e: b084 sub sp, #16 800b450: af00 add r7, sp, #0 800b452: 6078 str r0, [r7, #4] 800b454: 460b mov r3, r1 800b456: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800b458: 2300 movs r3, #0 800b45a: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b45c: 2300 movs r3, #0 800b45e: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 800b460: 687b ldr r3, [r7, #4] 800b462: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b466: 78fa ldrb r2, [r7, #3] 800b468: 4611 mov r1, r2 800b46a: 4618 mov r0, r3 800b46c: f7f8 fcde bl 8003e2c 800b470: 4603 mov r3, r0 800b472: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b474: 7bfb ldrb r3, [r7, #15] 800b476: 4618 mov r0, r3 800b478: f000 f91a bl 800b6b0 800b47c: 4603 mov r3, r0 800b47e: 73bb strb r3, [r7, #14] return usb_status; 800b480: 7bbb ldrb r3, [r7, #14] } 800b482: 4618 mov r0, r3 800b484: 3710 adds r7, #16 800b486: 46bd mov sp, r7 800b488: bd80 pop {r7, pc} 0800b48a : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800b48a: b580 push {r7, lr} 800b48c: b084 sub sp, #16 800b48e: af00 add r7, sp, #0 800b490: 6078 str r0, [r7, #4] 800b492: 460b mov r3, r1 800b494: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800b496: 2300 movs r3, #0 800b498: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b49a: 2300 movs r3, #0 800b49c: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 800b49e: 687b ldr r3, [r7, #4] 800b4a0: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b4a4: 78fa ldrb r2, [r7, #3] 800b4a6: 4611 mov r1, r2 800b4a8: 4618 mov r0, r3 800b4aa: f7f8 fd22 bl 8003ef2 800b4ae: 4603 mov r3, r0 800b4b0: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b4b2: 7bfb ldrb r3, [r7, #15] 800b4b4: 4618 mov r0, r3 800b4b6: f000 f8fb bl 800b6b0 800b4ba: 4603 mov r3, r0 800b4bc: 73bb strb r3, [r7, #14] return usb_status; 800b4be: 7bbb ldrb r3, [r7, #14] } 800b4c0: 4618 mov r0, r3 800b4c2: 3710 adds r7, #16 800b4c4: 46bd mov sp, r7 800b4c6: bd80 pop {r7, pc} 0800b4c8 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800b4c8: b480 push {r7} 800b4ca: b085 sub sp, #20 800b4cc: af00 add r7, sp, #0 800b4ce: 6078 str r0, [r7, #4] 800b4d0: 460b mov r3, r1 800b4d2: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 800b4d4: 687b ldr r3, [r7, #4] 800b4d6: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b4da: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 800b4dc: f997 3003 ldrsb.w r3, [r7, #3] 800b4e0: 2b00 cmp r3, #0 800b4e2: da0b bge.n 800b4fc { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 800b4e4: 78fb ldrb r3, [r7, #3] 800b4e6: f003 027f and.w r2, r3, #127 @ 0x7f 800b4ea: 68f9 ldr r1, [r7, #12] 800b4ec: 4613 mov r3, r2 800b4ee: 00db lsls r3, r3, #3 800b4f0: 4413 add r3, r2 800b4f2: 009b lsls r3, r3, #2 800b4f4: 440b add r3, r1 800b4f6: 3316 adds r3, #22 800b4f8: 781b ldrb r3, [r3, #0] 800b4fa: e00b b.n 800b514 } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 800b4fc: 78fb ldrb r3, [r7, #3] 800b4fe: f003 027f and.w r2, r3, #127 @ 0x7f 800b502: 68f9 ldr r1, [r7, #12] 800b504: 4613 mov r3, r2 800b506: 00db lsls r3, r3, #3 800b508: 4413 add r3, r2 800b50a: 009b lsls r3, r3, #2 800b50c: 440b add r3, r1 800b50e: f203 2356 addw r3, r3, #598 @ 0x256 800b512: 781b ldrb r3, [r3, #0] } } 800b514: 4618 mov r0, r3 800b516: 3714 adds r7, #20 800b518: 46bd mov sp, r7 800b51a: f85d 7b04 ldr.w r7, [sp], #4 800b51e: 4770 bx lr 0800b520 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 800b520: b580 push {r7, lr} 800b522: b084 sub sp, #16 800b524: af00 add r7, sp, #0 800b526: 6078 str r0, [r7, #4] 800b528: 460b mov r3, r1 800b52a: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800b52c: 2300 movs r3, #0 800b52e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b530: 2300 movs r3, #0 800b532: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 800b534: 687b ldr r3, [r7, #4] 800b536: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b53a: 78fa ldrb r2, [r7, #3] 800b53c: 4611 mov r1, r2 800b53e: 4618 mov r0, r3 800b540: f7f8 fb27 bl 8003b92 800b544: 4603 mov r3, r0 800b546: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b548: 7bfb ldrb r3, [r7, #15] 800b54a: 4618 mov r0, r3 800b54c: f000 f8b0 bl 800b6b0 800b550: 4603 mov r3, r0 800b552: 73bb strb r3, [r7, #14] return usb_status; 800b554: 7bbb ldrb r3, [r7, #14] } 800b556: 4618 mov r0, r3 800b558: 3710 adds r7, #16 800b55a: 46bd mov sp, r7 800b55c: bd80 pop {r7, pc} 0800b55e : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800b55e: b580 push {r7, lr} 800b560: b086 sub sp, #24 800b562: af00 add r7, sp, #0 800b564: 60f8 str r0, [r7, #12] 800b566: 607a str r2, [r7, #4] 800b568: 603b str r3, [r7, #0] 800b56a: 460b mov r3, r1 800b56c: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800b56e: 2300 movs r3, #0 800b570: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800b572: 2300 movs r3, #0 800b574: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 800b576: 68fb ldr r3, [r7, #12] 800b578: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800b57c: 7af9 ldrb r1, [r7, #11] 800b57e: 683b ldr r3, [r7, #0] 800b580: 687a ldr r2, [r7, #4] 800b582: f7f8 fc19 bl 8003db8 800b586: 4603 mov r3, r0 800b588: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800b58a: 7dfb ldrb r3, [r7, #23] 800b58c: 4618 mov r0, r3 800b58e: f000 f88f bl 800b6b0 800b592: 4603 mov r3, r0 800b594: 75bb strb r3, [r7, #22] return usb_status; 800b596: 7dbb ldrb r3, [r7, #22] } 800b598: 4618 mov r0, r3 800b59a: 3718 adds r7, #24 800b59c: 46bd mov sp, r7 800b59e: bd80 pop {r7, pc} 0800b5a0 : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800b5a0: b580 push {r7, lr} 800b5a2: b086 sub sp, #24 800b5a4: af00 add r7, sp, #0 800b5a6: 60f8 str r0, [r7, #12] 800b5a8: 607a str r2, [r7, #4] 800b5aa: 603b str r3, [r7, #0] 800b5ac: 460b mov r3, r1 800b5ae: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800b5b0: 2300 movs r3, #0 800b5b2: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800b5b4: 2300 movs r3, #0 800b5b6: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 800b5b8: 68fb ldr r3, [r7, #12] 800b5ba: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800b5be: 7af9 ldrb r1, [r7, #11] 800b5c0: 683b ldr r3, [r7, #0] 800b5c2: 687a ldr r2, [r7, #4] 800b5c4: f7f8 fbbd bl 8003d42 800b5c8: 4603 mov r3, r0 800b5ca: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800b5cc: 7dfb ldrb r3, [r7, #23] 800b5ce: 4618 mov r0, r3 800b5d0: f000 f86e bl 800b6b0 800b5d4: 4603 mov r3, r0 800b5d6: 75bb strb r3, [r7, #22] return usb_status; 800b5d8: 7dbb ldrb r3, [r7, #22] } 800b5da: 4618 mov r0, r3 800b5dc: 3718 adds r7, #24 800b5de: 46bd mov sp, r7 800b5e0: bd80 pop {r7, pc} ... 0800b5e4 : * @param hpcd: PCD handle * @param msg: LPM message * @retval None */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { 800b5e4: b580 push {r7, lr} 800b5e6: b082 sub sp, #8 800b5e8: af00 add r7, sp, #0 800b5ea: 6078 str r0, [r7, #4] 800b5ec: 460b mov r3, r1 800b5ee: 70fb strb r3, [r7, #3] switch (msg) 800b5f0: 78fb ldrb r3, [r7, #3] 800b5f2: 2b00 cmp r3, #0 800b5f4: d002 beq.n 800b5fc 800b5f6: 2b01 cmp r3, #1 800b5f8: d01f beq.n 800b63a /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } } 800b5fa: e03b b.n 800b674 if (hpcd->Init.low_power_enable) 800b5fc: 687b ldr r3, [r7, #4] 800b5fe: 7adb ldrb r3, [r3, #11] 800b600: 2b00 cmp r3, #0 800b602: d007 beq.n 800b614 SystemClock_Config(); 800b604: f7f5 fb96 bl 8000d34 SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800b608: 4b1c ldr r3, [pc, #112] @ (800b67c ) 800b60a: 691b ldr r3, [r3, #16] 800b60c: 4a1b ldr r2, [pc, #108] @ (800b67c ) 800b60e: f023 0306 bic.w r3, r3, #6 800b612: 6113 str r3, [r2, #16] __HAL_PCD_UNGATE_PHYCLOCK(hpcd); 800b614: 687b ldr r3, [r7, #4] 800b616: 681b ldr r3, [r3, #0] 800b618: f503 6360 add.w r3, r3, #3584 @ 0xe00 800b61c: 681b ldr r3, [r3, #0] 800b61e: 687a ldr r2, [r7, #4] 800b620: 6812 ldr r2, [r2, #0] 800b622: f502 6260 add.w r2, r2, #3584 @ 0xe00 800b626: f023 0301 bic.w r3, r3, #1 800b62a: 6013 str r3, [r2, #0] USBD_LL_Resume(hpcd->pData); 800b62c: 687b ldr r3, [r7, #4] 800b62e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b632: 4618 mov r0, r3 800b634: f7fe fb90 bl 8009d58 break; 800b638: e01c b.n 800b674 __HAL_PCD_GATE_PHYCLOCK(hpcd); 800b63a: 687b ldr r3, [r7, #4] 800b63c: 681b ldr r3, [r3, #0] 800b63e: f503 6360 add.w r3, r3, #3584 @ 0xe00 800b642: 681b ldr r3, [r3, #0] 800b644: 687a ldr r2, [r7, #4] 800b646: 6812 ldr r2, [r2, #0] 800b648: f502 6260 add.w r2, r2, #3584 @ 0xe00 800b64c: f043 0301 orr.w r3, r3, #1 800b650: 6013 str r3, [r2, #0] USBD_LL_Suspend(hpcd->pData); 800b652: 687b ldr r3, [r7, #4] 800b654: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b658: 4618 mov r0, r3 800b65a: f7fe fb61 bl 8009d20 if (hpcd->Init.low_power_enable) 800b65e: 687b ldr r3, [r7, #4] 800b660: 7adb ldrb r3, [r3, #11] 800b662: 2b00 cmp r3, #0 800b664: d005 beq.n 800b672 SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800b666: 4b05 ldr r3, [pc, #20] @ (800b67c ) 800b668: 691b ldr r3, [r3, #16] 800b66a: 4a04 ldr r2, [pc, #16] @ (800b67c ) 800b66c: f043 0306 orr.w r3, r3, #6 800b670: 6113 str r3, [r2, #16] break; 800b672: bf00 nop } 800b674: bf00 nop 800b676: 3708 adds r7, #8 800b678: 46bd mov sp, r7 800b67a: bd80 pop {r7, pc} 800b67c: e000ed00 .word 0xe000ed00 0800b680 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 800b680: b480 push {r7} 800b682: b083 sub sp, #12 800b684: af00 add r7, sp, #0 800b686: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 800b688: 4b03 ldr r3, [pc, #12] @ (800b698 ) } 800b68a: 4618 mov r0, r3 800b68c: 370c adds r7, #12 800b68e: 46bd mov sp, r7 800b690: f85d 7b04 ldr.w r7, [sp], #4 800b694: 4770 bx lr 800b696: bf00 nop 800b698: 200018c8 .word 0x200018c8 0800b69c : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 800b69c: b480 push {r7} 800b69e: b083 sub sp, #12 800b6a0: af00 add r7, sp, #0 800b6a2: 6078 str r0, [r7, #4] } 800b6a4: bf00 nop 800b6a6: 370c adds r7, #12 800b6a8: 46bd mov sp, r7 800b6aa: f85d 7b04 ldr.w r7, [sp], #4 800b6ae: 4770 bx lr 0800b6b0 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 800b6b0: b480 push {r7} 800b6b2: b085 sub sp, #20 800b6b4: af00 add r7, sp, #0 800b6b6: 4603 mov r3, r0 800b6b8: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 800b6ba: 2300 movs r3, #0 800b6bc: 73fb strb r3, [r7, #15] switch (hal_status) 800b6be: 79fb ldrb r3, [r7, #7] 800b6c0: 2b03 cmp r3, #3 800b6c2: d817 bhi.n 800b6f4 800b6c4: a201 add r2, pc, #4 @ (adr r2, 800b6cc ) 800b6c6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b6ca: bf00 nop 800b6cc: 0800b6dd .word 0x0800b6dd 800b6d0: 0800b6e3 .word 0x0800b6e3 800b6d4: 0800b6e9 .word 0x0800b6e9 800b6d8: 0800b6ef .word 0x0800b6ef { case HAL_OK : usb_status = USBD_OK; 800b6dc: 2300 movs r3, #0 800b6de: 73fb strb r3, [r7, #15] break; 800b6e0: e00b b.n 800b6fa case HAL_ERROR : usb_status = USBD_FAIL; 800b6e2: 2303 movs r3, #3 800b6e4: 73fb strb r3, [r7, #15] break; 800b6e6: e008 b.n 800b6fa case HAL_BUSY : usb_status = USBD_BUSY; 800b6e8: 2301 movs r3, #1 800b6ea: 73fb strb r3, [r7, #15] break; 800b6ec: e005 b.n 800b6fa case HAL_TIMEOUT : usb_status = USBD_FAIL; 800b6ee: 2303 movs r3, #3 800b6f0: 73fb strb r3, [r7, #15] break; 800b6f2: e002 b.n 800b6fa default : usb_status = USBD_FAIL; 800b6f4: 2303 movs r3, #3 800b6f6: 73fb strb r3, [r7, #15] break; 800b6f8: bf00 nop } return usb_status; 800b6fa: 7bfb ldrb r3, [r7, #15] } 800b6fc: 4618 mov r0, r3 800b6fe: 3714 adds r7, #20 800b700: 46bd mov sp, r7 800b702: f85d 7b04 ldr.w r7, [sp], #4 800b706: 4770 bx lr 0800b708 : 800b708: 4402 add r2, r0 800b70a: 4603 mov r3, r0 800b70c: 4293 cmp r3, r2 800b70e: d100 bne.n 800b712 800b710: 4770 bx lr 800b712: f803 1b01 strb.w r1, [r3], #1 800b716: e7f9 b.n 800b70c 0800b718 <__libc_init_array>: 800b718: b570 push {r4, r5, r6, lr} 800b71a: 4d0d ldr r5, [pc, #52] @ (800b750 <__libc_init_array+0x38>) 800b71c: 4c0d ldr r4, [pc, #52] @ (800b754 <__libc_init_array+0x3c>) 800b71e: 1b64 subs r4, r4, r5 800b720: 10a4 asrs r4, r4, #2 800b722: 2600 movs r6, #0 800b724: 42a6 cmp r6, r4 800b726: d109 bne.n 800b73c <__libc_init_array+0x24> 800b728: 4d0b ldr r5, [pc, #44] @ (800b758 <__libc_init_array+0x40>) 800b72a: 4c0c ldr r4, [pc, #48] @ (800b75c <__libc_init_array+0x44>) 800b72c: f000 f826 bl 800b77c <_init> 800b730: 1b64 subs r4, r4, r5 800b732: 10a4 asrs r4, r4, #2 800b734: 2600 movs r6, #0 800b736: 42a6 cmp r6, r4 800b738: d105 bne.n 800b746 <__libc_init_array+0x2e> 800b73a: bd70 pop {r4, r5, r6, pc} 800b73c: f855 3b04 ldr.w r3, [r5], #4 800b740: 4798 blx r3 800b742: 3601 adds r6, #1 800b744: e7ee b.n 800b724 <__libc_init_array+0xc> 800b746: f855 3b04 ldr.w r3, [r5], #4 800b74a: 4798 blx r3 800b74c: 3601 adds r6, #1 800b74e: e7f2 b.n 800b736 <__libc_init_array+0x1e> 800b750: 0800b7f8 .word 0x0800b7f8 800b754: 0800b7f8 .word 0x0800b7f8 800b758: 0800b7f8 .word 0x0800b7f8 800b75c: 0800b7fc .word 0x0800b7fc 0800b760 : 800b760: 440a add r2, r1 800b762: 4291 cmp r1, r2 800b764: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 800b768: d100 bne.n 800b76c 800b76a: 4770 bx lr 800b76c: b510 push {r4, lr} 800b76e: f811 4b01 ldrb.w r4, [r1], #1 800b772: f803 4f01 strb.w r4, [r3, #1]! 800b776: 4291 cmp r1, r2 800b778: d1f9 bne.n 800b76e 800b77a: bd10 pop {r4, pc} 0800b77c <_init>: 800b77c: b5f8 push {r3, r4, r5, r6, r7, lr} 800b77e: bf00 nop 800b780: bcf8 pop {r3, r4, r5, r6, r7} 800b782: bc08 pop {r3} 800b784: 469e mov lr, r3 800b786: 4770 bx lr 0800b788 <_fini>: 800b788: b5f8 push {r3, r4, r5, r6, r7, lr} 800b78a: bf00 nop 800b78c: bcf8 pop {r3, r4, r5, r6, r7} 800b78e: bc08 pop {r3} 800b790: 469e mov lr, r3 800b792: 4770 bx lr