67.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001c4 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000b238 080001c4 080001c4 000011c4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000005c 0800b3fc 0800b3fc 0000c3fc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800b458 0800b458 0000d214 2**0 CONTENTS, READONLY 4 .ARM 00000008 0800b458 0800b458 0000c458 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 0800b460 0800b460 0000d214 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 0800b460 0800b460 0000c460 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 0800b464 0800b464 0000c464 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 00000214 20000000 0800b468 0000d000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000015e8 20000214 0800b67c 0000d214 2**2 ALLOC 10 ._user_heap_stack 00000604 200017fc 0800b67c 0000d7fc 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000d214 2**0 CONTENTS, READONLY 12 .debug_info 0001be15 00000000 00000000 0000d244 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00004285 00000000 00000000 00029059 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000017f0 00000000 00000000 0002d2e0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00001291 00000000 00000000 0002ead0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 000262b3 00000000 00000000 0002fd61 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 000203fa 00000000 00000000 00056014 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000d8080 00000000 00000000 0007640e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0014e48e 2**0 CONTENTS, READONLY 20 .debug_frame 0000645c 00000000 00000000 0014e4d4 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000076 00000000 00000000 00154930 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001c4 <__do_global_dtors_aux>: 80001c4: b510 push {r4, lr} 80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>) 80001c8: 7823 ldrb r3, [r4, #0] 80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16> 80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>) 80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12> 80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>) 80001d2: f3af 8000 nop.w 80001d6: 2301 movs r3, #1 80001d8: 7023 strb r3, [r4, #0] 80001da: bd10 pop {r4, pc} 80001dc: 20000214 .word 0x20000214 80001e0: 00000000 .word 0x00000000 80001e4: 0800b3e4 .word 0x0800b3e4 080001e8 : 80001e8: b508 push {r3, lr} 80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 ) 80001ec: b11b cbz r3, 80001f6 80001ee: 4903 ldr r1, [pc, #12] @ (80001fc ) 80001f0: 4803 ldr r0, [pc, #12] @ (8000200 ) 80001f2: f3af 8000 nop.w 80001f6: bd08 pop {r3, pc} 80001f8: 00000000 .word 0x00000000 80001fc: 20000218 .word 0x20000218 8000200: 0800b3e4 .word 0x0800b3e4 08000204 <__aeabi_uldivmod>: 8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18> 8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18> 8000208: 2900 cmp r1, #0 800020a: bf08 it eq 800020c: 2800 cmpeq r0, #0 800020e: bf1c itt ne 8000210: f04f 31ff movne.w r1, #4294967295 8000214: f04f 30ff movne.w r0, #4294967295 8000218: f000 b988 b.w 800052c <__aeabi_idiv0> 800021c: f1ad 0c08 sub.w ip, sp, #8 8000220: e96d ce04 strd ip, lr, [sp, #-16]! 8000224: f000 f806 bl 8000234 <__udivmoddi4> 8000228: f8dd e004 ldr.w lr, [sp, #4] 800022c: e9dd 2302 ldrd r2, r3, [sp, #8] 8000230: b004 add sp, #16 8000232: 4770 bx lr 08000234 <__udivmoddi4>: 8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000238: 9d08 ldr r5, [sp, #32] 800023a: 468e mov lr, r1 800023c: 4604 mov r4, r0 800023e: 4688 mov r8, r1 8000240: 2b00 cmp r3, #0 8000242: d14a bne.n 80002da <__udivmoddi4+0xa6> 8000244: 428a cmp r2, r1 8000246: 4617 mov r7, r2 8000248: d962 bls.n 8000310 <__udivmoddi4+0xdc> 800024a: fab2 f682 clz r6, r2 800024e: b14e cbz r6, 8000264 <__udivmoddi4+0x30> 8000250: f1c6 0320 rsb r3, r6, #32 8000254: fa01 f806 lsl.w r8, r1, r6 8000258: fa20 f303 lsr.w r3, r0, r3 800025c: 40b7 lsls r7, r6 800025e: ea43 0808 orr.w r8, r3, r8 8000262: 40b4 lsls r4, r6 8000264: ea4f 4e17 mov.w lr, r7, lsr #16 8000268: fa1f fc87 uxth.w ip, r7 800026c: fbb8 f1fe udiv r1, r8, lr 8000270: 0c23 lsrs r3, r4, #16 8000272: fb0e 8811 mls r8, lr, r1, r8 8000276: ea43 4308 orr.w r3, r3, r8, lsl #16 800027a: fb01 f20c mul.w r2, r1, ip 800027e: 429a cmp r2, r3 8000280: d909 bls.n 8000296 <__udivmoddi4+0x62> 8000282: 18fb adds r3, r7, r3 8000284: f101 30ff add.w r0, r1, #4294967295 8000288: f080 80ea bcs.w 8000460 <__udivmoddi4+0x22c> 800028c: 429a cmp r2, r3 800028e: f240 80e7 bls.w 8000460 <__udivmoddi4+0x22c> 8000292: 3902 subs r1, #2 8000294: 443b add r3, r7 8000296: 1a9a subs r2, r3, r2 8000298: b2a3 uxth r3, r4 800029a: fbb2 f0fe udiv r0, r2, lr 800029e: fb0e 2210 mls r2, lr, r0, r2 80002a2: ea43 4302 orr.w r3, r3, r2, lsl #16 80002a6: fb00 fc0c mul.w ip, r0, ip 80002aa: 459c cmp ip, r3 80002ac: d909 bls.n 80002c2 <__udivmoddi4+0x8e> 80002ae: 18fb adds r3, r7, r3 80002b0: f100 32ff add.w r2, r0, #4294967295 80002b4: f080 80d6 bcs.w 8000464 <__udivmoddi4+0x230> 80002b8: 459c cmp ip, r3 80002ba: f240 80d3 bls.w 8000464 <__udivmoddi4+0x230> 80002be: 443b add r3, r7 80002c0: 3802 subs r0, #2 80002c2: ea40 4001 orr.w r0, r0, r1, lsl #16 80002c6: eba3 030c sub.w r3, r3, ip 80002ca: 2100 movs r1, #0 80002cc: b11d cbz r5, 80002d6 <__udivmoddi4+0xa2> 80002ce: 40f3 lsrs r3, r6 80002d0: 2200 movs r2, #0 80002d2: e9c5 3200 strd r3, r2, [r5] 80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002da: 428b cmp r3, r1 80002dc: d905 bls.n 80002ea <__udivmoddi4+0xb6> 80002de: b10d cbz r5, 80002e4 <__udivmoddi4+0xb0> 80002e0: e9c5 0100 strd r0, r1, [r5] 80002e4: 2100 movs r1, #0 80002e6: 4608 mov r0, r1 80002e8: e7f5 b.n 80002d6 <__udivmoddi4+0xa2> 80002ea: fab3 f183 clz r1, r3 80002ee: 2900 cmp r1, #0 80002f0: d146 bne.n 8000380 <__udivmoddi4+0x14c> 80002f2: 4573 cmp r3, lr 80002f4: d302 bcc.n 80002fc <__udivmoddi4+0xc8> 80002f6: 4282 cmp r2, r0 80002f8: f200 8105 bhi.w 8000506 <__udivmoddi4+0x2d2> 80002fc: 1a84 subs r4, r0, r2 80002fe: eb6e 0203 sbc.w r2, lr, r3 8000302: 2001 movs r0, #1 8000304: 4690 mov r8, r2 8000306: 2d00 cmp r5, #0 8000308: d0e5 beq.n 80002d6 <__udivmoddi4+0xa2> 800030a: e9c5 4800 strd r4, r8, [r5] 800030e: e7e2 b.n 80002d6 <__udivmoddi4+0xa2> 8000310: 2a00 cmp r2, #0 8000312: f000 8090 beq.w 8000436 <__udivmoddi4+0x202> 8000316: fab2 f682 clz r6, r2 800031a: 2e00 cmp r6, #0 800031c: f040 80a4 bne.w 8000468 <__udivmoddi4+0x234> 8000320: 1a8a subs r2, r1, r2 8000322: 0c03 lsrs r3, r0, #16 8000324: ea4f 4e17 mov.w lr, r7, lsr #16 8000328: b280 uxth r0, r0 800032a: b2bc uxth r4, r7 800032c: 2101 movs r1, #1 800032e: fbb2 fcfe udiv ip, r2, lr 8000332: fb0e 221c mls r2, lr, ip, r2 8000336: ea43 4302 orr.w r3, r3, r2, lsl #16 800033a: fb04 f20c mul.w r2, r4, ip 800033e: 429a cmp r2, r3 8000340: d907 bls.n 8000352 <__udivmoddi4+0x11e> 8000342: 18fb adds r3, r7, r3 8000344: f10c 38ff add.w r8, ip, #4294967295 8000348: d202 bcs.n 8000350 <__udivmoddi4+0x11c> 800034a: 429a cmp r2, r3 800034c: f200 80e0 bhi.w 8000510 <__udivmoddi4+0x2dc> 8000350: 46c4 mov ip, r8 8000352: 1a9b subs r3, r3, r2 8000354: fbb3 f2fe udiv r2, r3, lr 8000358: fb0e 3312 mls r3, lr, r2, r3 800035c: ea40 4303 orr.w r3, r0, r3, lsl #16 8000360: fb02 f404 mul.w r4, r2, r4 8000364: 429c cmp r4, r3 8000366: d907 bls.n 8000378 <__udivmoddi4+0x144> 8000368: 18fb adds r3, r7, r3 800036a: f102 30ff add.w r0, r2, #4294967295 800036e: d202 bcs.n 8000376 <__udivmoddi4+0x142> 8000370: 429c cmp r4, r3 8000372: f200 80ca bhi.w 800050a <__udivmoddi4+0x2d6> 8000376: 4602 mov r2, r0 8000378: 1b1b subs r3, r3, r4 800037a: ea42 400c orr.w r0, r2, ip, lsl #16 800037e: e7a5 b.n 80002cc <__udivmoddi4+0x98> 8000380: f1c1 0620 rsb r6, r1, #32 8000384: 408b lsls r3, r1 8000386: fa22 f706 lsr.w r7, r2, r6 800038a: 431f orrs r7, r3 800038c: fa0e f401 lsl.w r4, lr, r1 8000390: fa20 f306 lsr.w r3, r0, r6 8000394: fa2e fe06 lsr.w lr, lr, r6 8000398: ea4f 4917 mov.w r9, r7, lsr #16 800039c: 4323 orrs r3, r4 800039e: fa00 f801 lsl.w r8, r0, r1 80003a2: fa1f fc87 uxth.w ip, r7 80003a6: fbbe f0f9 udiv r0, lr, r9 80003aa: 0c1c lsrs r4, r3, #16 80003ac: fb09 ee10 mls lr, r9, r0, lr 80003b0: ea44 440e orr.w r4, r4, lr, lsl #16 80003b4: fb00 fe0c mul.w lr, r0, ip 80003b8: 45a6 cmp lr, r4 80003ba: fa02 f201 lsl.w r2, r2, r1 80003be: d909 bls.n 80003d4 <__udivmoddi4+0x1a0> 80003c0: 193c adds r4, r7, r4 80003c2: f100 3aff add.w sl, r0, #4294967295 80003c6: f080 809c bcs.w 8000502 <__udivmoddi4+0x2ce> 80003ca: 45a6 cmp lr, r4 80003cc: f240 8099 bls.w 8000502 <__udivmoddi4+0x2ce> 80003d0: 3802 subs r0, #2 80003d2: 443c add r4, r7 80003d4: eba4 040e sub.w r4, r4, lr 80003d8: fa1f fe83 uxth.w lr, r3 80003dc: fbb4 f3f9 udiv r3, r4, r9 80003e0: fb09 4413 mls r4, r9, r3, r4 80003e4: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003e8: fb03 fc0c mul.w ip, r3, ip 80003ec: 45a4 cmp ip, r4 80003ee: d908 bls.n 8000402 <__udivmoddi4+0x1ce> 80003f0: 193c adds r4, r7, r4 80003f2: f103 3eff add.w lr, r3, #4294967295 80003f6: f080 8082 bcs.w 80004fe <__udivmoddi4+0x2ca> 80003fa: 45a4 cmp ip, r4 80003fc: d97f bls.n 80004fe <__udivmoddi4+0x2ca> 80003fe: 3b02 subs r3, #2 8000400: 443c add r4, r7 8000402: ea43 4000 orr.w r0, r3, r0, lsl #16 8000406: eba4 040c sub.w r4, r4, ip 800040a: fba0 ec02 umull lr, ip, r0, r2 800040e: 4564 cmp r4, ip 8000410: 4673 mov r3, lr 8000412: 46e1 mov r9, ip 8000414: d362 bcc.n 80004dc <__udivmoddi4+0x2a8> 8000416: d05f beq.n 80004d8 <__udivmoddi4+0x2a4> 8000418: b15d cbz r5, 8000432 <__udivmoddi4+0x1fe> 800041a: ebb8 0203 subs.w r2, r8, r3 800041e: eb64 0409 sbc.w r4, r4, r9 8000422: fa04 f606 lsl.w r6, r4, r6 8000426: fa22 f301 lsr.w r3, r2, r1 800042a: 431e orrs r6, r3 800042c: 40cc lsrs r4, r1 800042e: e9c5 6400 strd r6, r4, [r5] 8000432: 2100 movs r1, #0 8000434: e74f b.n 80002d6 <__udivmoddi4+0xa2> 8000436: fbb1 fcf2 udiv ip, r1, r2 800043a: 0c01 lsrs r1, r0, #16 800043c: ea41 410e orr.w r1, r1, lr, lsl #16 8000440: b280 uxth r0, r0 8000442: ea40 4201 orr.w r2, r0, r1, lsl #16 8000446: 463b mov r3, r7 8000448: 4638 mov r0, r7 800044a: 463c mov r4, r7 800044c: 46b8 mov r8, r7 800044e: 46be mov lr, r7 8000450: 2620 movs r6, #32 8000452: fbb1 f1f7 udiv r1, r1, r7 8000456: eba2 0208 sub.w r2, r2, r8 800045a: ea41 410c orr.w r1, r1, ip, lsl #16 800045e: e766 b.n 800032e <__udivmoddi4+0xfa> 8000460: 4601 mov r1, r0 8000462: e718 b.n 8000296 <__udivmoddi4+0x62> 8000464: 4610 mov r0, r2 8000466: e72c b.n 80002c2 <__udivmoddi4+0x8e> 8000468: f1c6 0220 rsb r2, r6, #32 800046c: fa2e f302 lsr.w r3, lr, r2 8000470: 40b7 lsls r7, r6 8000472: 40b1 lsls r1, r6 8000474: fa20 f202 lsr.w r2, r0, r2 8000478: ea4f 4e17 mov.w lr, r7, lsr #16 800047c: 430a orrs r2, r1 800047e: fbb3 f8fe udiv r8, r3, lr 8000482: b2bc uxth r4, r7 8000484: fb0e 3318 mls r3, lr, r8, r3 8000488: 0c11 lsrs r1, r2, #16 800048a: ea41 4103 orr.w r1, r1, r3, lsl #16 800048e: fb08 f904 mul.w r9, r8, r4 8000492: 40b0 lsls r0, r6 8000494: 4589 cmp r9, r1 8000496: ea4f 4310 mov.w r3, r0, lsr #16 800049a: b280 uxth r0, r0 800049c: d93e bls.n 800051c <__udivmoddi4+0x2e8> 800049e: 1879 adds r1, r7, r1 80004a0: f108 3cff add.w ip, r8, #4294967295 80004a4: d201 bcs.n 80004aa <__udivmoddi4+0x276> 80004a6: 4589 cmp r9, r1 80004a8: d81f bhi.n 80004ea <__udivmoddi4+0x2b6> 80004aa: eba1 0109 sub.w r1, r1, r9 80004ae: fbb1 f9fe udiv r9, r1, lr 80004b2: fb09 f804 mul.w r8, r9, r4 80004b6: fb0e 1119 mls r1, lr, r9, r1 80004ba: b292 uxth r2, r2 80004bc: ea42 4201 orr.w r2, r2, r1, lsl #16 80004c0: 4542 cmp r2, r8 80004c2: d229 bcs.n 8000518 <__udivmoddi4+0x2e4> 80004c4: 18ba adds r2, r7, r2 80004c6: f109 31ff add.w r1, r9, #4294967295 80004ca: d2c4 bcs.n 8000456 <__udivmoddi4+0x222> 80004cc: 4542 cmp r2, r8 80004ce: d2c2 bcs.n 8000456 <__udivmoddi4+0x222> 80004d0: f1a9 0102 sub.w r1, r9, #2 80004d4: 443a add r2, r7 80004d6: e7be b.n 8000456 <__udivmoddi4+0x222> 80004d8: 45f0 cmp r8, lr 80004da: d29d bcs.n 8000418 <__udivmoddi4+0x1e4> 80004dc: ebbe 0302 subs.w r3, lr, r2 80004e0: eb6c 0c07 sbc.w ip, ip, r7 80004e4: 3801 subs r0, #1 80004e6: 46e1 mov r9, ip 80004e8: e796 b.n 8000418 <__udivmoddi4+0x1e4> 80004ea: eba7 0909 sub.w r9, r7, r9 80004ee: 4449 add r1, r9 80004f0: f1a8 0c02 sub.w ip, r8, #2 80004f4: fbb1 f9fe udiv r9, r1, lr 80004f8: fb09 f804 mul.w r8, r9, r4 80004fc: e7db b.n 80004b6 <__udivmoddi4+0x282> 80004fe: 4673 mov r3, lr 8000500: e77f b.n 8000402 <__udivmoddi4+0x1ce> 8000502: 4650 mov r0, sl 8000504: e766 b.n 80003d4 <__udivmoddi4+0x1a0> 8000506: 4608 mov r0, r1 8000508: e6fd b.n 8000306 <__udivmoddi4+0xd2> 800050a: 443b add r3, r7 800050c: 3a02 subs r2, #2 800050e: e733 b.n 8000378 <__udivmoddi4+0x144> 8000510: f1ac 0c02 sub.w ip, ip, #2 8000514: 443b add r3, r7 8000516: e71c b.n 8000352 <__udivmoddi4+0x11e> 8000518: 4649 mov r1, r9 800051a: e79c b.n 8000456 <__udivmoddi4+0x222> 800051c: eba1 0109 sub.w r1, r1, r9 8000520: 46c4 mov ip, r8 8000522: fbb1 f9fe udiv r9, r1, lr 8000526: fb09 f804 mul.w r8, r9, r4 800052a: e7c4 b.n 80004b6 <__udivmoddi4+0x282> 0800052c <__aeabi_idiv0>: 800052c: 4770 bx lr 800052e: bf00 nop 08000530 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 8000530: b580 push {r7, lr} 8000532: b082 sub sp, #8 8000534: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8000536: 2300 movs r3, #0 8000538: 607b str r3, [r7, #4] 800053a: 4b2f ldr r3, [pc, #188] @ (80005f8 ) 800053c: 6b1b ldr r3, [r3, #48] @ 0x30 800053e: 4a2e ldr r2, [pc, #184] @ (80005f8 ) 8000540: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000544: 6313 str r3, [r2, #48] @ 0x30 8000546: 4b2c ldr r3, [pc, #176] @ (80005f8 ) 8000548: 6b1b ldr r3, [r3, #48] @ 0x30 800054a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800054e: 607b str r3, [r7, #4] 8000550: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); 8000552: 2300 movs r3, #0 8000554: 603b str r3, [r7, #0] 8000556: 4b28 ldr r3, [pc, #160] @ (80005f8 ) 8000558: 6b1b ldr r3, [r3, #48] @ 0x30 800055a: 4a27 ldr r2, [pc, #156] @ (80005f8 ) 800055c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8000560: 6313 str r3, [r2, #48] @ 0x30 8000562: 4b25 ldr r3, [pc, #148] @ (80005f8 ) 8000564: 6b1b ldr r3, [r3, #48] @ 0x30 8000566: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800056a: 603b str r3, [r7, #0] 800056c: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); 800056e: 2200 movs r2, #0 8000570: 2100 movs r1, #0 8000572: 200b movs r0, #11 8000574: f001 fdf3 bl 800215e HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8000578: 200b movs r0, #11 800057a: f001 fe0c bl 8002196 /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); 800057e: 2200 movs r2, #0 8000580: 2100 movs r1, #0 8000582: 200d movs r0, #13 8000584: f001 fdeb bl 800215e HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8000588: 200d movs r0, #13 800058a: f001 fe04 bl 8002196 /* DMA1_Stream4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 0, 0); 800058e: 2200 movs r2, #0 8000590: 2100 movs r1, #0 8000592: 200f movs r0, #15 8000594: f001 fde3 bl 800215e HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); 8000598: 200f movs r0, #15 800059a: f001 fdfc bl 8002196 /* DMA1_Stream5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0); 800059e: 2200 movs r2, #0 80005a0: 2100 movs r1, #0 80005a2: 2010 movs r0, #16 80005a4: f001 fddb bl 800215e HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); 80005a8: 2010 movs r0, #16 80005aa: f001 fdf4 bl 8002196 /* DMA1_Stream6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0); 80005ae: 2200 movs r2, #0 80005b0: 2100 movs r1, #0 80005b2: 2011 movs r0, #17 80005b4: f001 fdd3 bl 800215e HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); 80005b8: 2011 movs r0, #17 80005ba: f001 fdec bl 8002196 /* DMA1_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0); 80005be: 2200 movs r2, #0 80005c0: 2100 movs r1, #0 80005c2: 202f movs r0, #47 @ 0x2f 80005c4: f001 fdcb bl 800215e HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); 80005c8: 202f movs r0, #47 @ 0x2f 80005ca: f001 fde4 bl 8002196 /* DMA2_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); 80005ce: 2200 movs r2, #0 80005d0: 2100 movs r1, #0 80005d2: 203a movs r0, #58 @ 0x3a 80005d4: f001 fdc3 bl 800215e HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); 80005d8: 203a movs r0, #58 @ 0x3a 80005da: f001 fddc bl 8002196 /* DMA2_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); 80005de: 2200 movs r2, #0 80005e0: 2100 movs r1, #0 80005e2: 2046 movs r0, #70 @ 0x46 80005e4: f001 fdbb bl 800215e HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 80005e8: 2046 movs r0, #70 @ 0x46 80005ea: f001 fdd4 bl 8002196 } 80005ee: bf00 nop 80005f0: 3708 adds r7, #8 80005f2: 46bd mov sp, r7 80005f4: bd80 pop {r7, pc} 80005f6: bf00 nop 80005f8: 40023800 .word 0x40023800 080005fc : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 80005fc: b580 push {r7, lr} 80005fe: b08a sub sp, #40 @ 0x28 8000600: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000602: f107 0314 add.w r3, r7, #20 8000606: 2200 movs r2, #0 8000608: 601a str r2, [r3, #0] 800060a: 605a str r2, [r3, #4] 800060c: 609a str r2, [r3, #8] 800060e: 60da str r2, [r3, #12] 8000610: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8000612: 2300 movs r3, #0 8000614: 613b str r3, [r7, #16] 8000616: 4b4d ldr r3, [pc, #308] @ (800074c ) 8000618: 6b1b ldr r3, [r3, #48] @ 0x30 800061a: 4a4c ldr r2, [pc, #304] @ (800074c ) 800061c: f043 0380 orr.w r3, r3, #128 @ 0x80 8000620: 6313 str r3, [r2, #48] @ 0x30 8000622: 4b4a ldr r3, [pc, #296] @ (800074c ) 8000624: 6b1b ldr r3, [r3, #48] @ 0x30 8000626: f003 0380 and.w r3, r3, #128 @ 0x80 800062a: 613b str r3, [r7, #16] 800062c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800062e: 2300 movs r3, #0 8000630: 60fb str r3, [r7, #12] 8000632: 4b46 ldr r3, [pc, #280] @ (800074c ) 8000634: 6b1b ldr r3, [r3, #48] @ 0x30 8000636: 4a45 ldr r2, [pc, #276] @ (800074c ) 8000638: f043 0301 orr.w r3, r3, #1 800063c: 6313 str r3, [r2, #48] @ 0x30 800063e: 4b43 ldr r3, [pc, #268] @ (800074c ) 8000640: 6b1b ldr r3, [r3, #48] @ 0x30 8000642: f003 0301 and.w r3, r3, #1 8000646: 60fb str r3, [r7, #12] 8000648: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); 800064a: 2300 movs r3, #0 800064c: 60bb str r3, [r7, #8] 800064e: 4b3f ldr r3, [pc, #252] @ (800074c ) 8000650: 6b1b ldr r3, [r3, #48] @ 0x30 8000652: 4a3e ldr r2, [pc, #248] @ (800074c ) 8000654: f043 0304 orr.w r3, r3, #4 8000658: 6313 str r3, [r2, #48] @ 0x30 800065a: 4b3c ldr r3, [pc, #240] @ (800074c ) 800065c: 6b1b ldr r3, [r3, #48] @ 0x30 800065e: f003 0304 and.w r3, r3, #4 8000662: 60bb str r3, [r7, #8] 8000664: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000666: 2300 movs r3, #0 8000668: 607b str r3, [r7, #4] 800066a: 4b38 ldr r3, [pc, #224] @ (800074c ) 800066c: 6b1b ldr r3, [r3, #48] @ 0x30 800066e: 4a37 ldr r2, [pc, #220] @ (800074c ) 8000670: f043 0302 orr.w r3, r3, #2 8000674: 6313 str r3, [r2, #48] @ 0x30 8000676: 4b35 ldr r3, [pc, #212] @ (800074c ) 8000678: 6b1b ldr r3, [r3, #48] @ 0x30 800067a: f003 0302 and.w r3, r3, #2 800067e: 607b str r3, [r7, #4] 8000680: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000682: 2300 movs r3, #0 8000684: 603b str r3, [r7, #0] 8000686: 4b31 ldr r3, [pc, #196] @ (800074c ) 8000688: 6b1b ldr r3, [r3, #48] @ 0x30 800068a: 4a30 ldr r2, [pc, #192] @ (800074c ) 800068c: f043 0308 orr.w r3, r3, #8 8000690: 6313 str r3, [r2, #48] @ 0x30 8000692: 4b2e ldr r3, [pc, #184] @ (800074c ) 8000694: 6b1b ldr r3, [r3, #48] @ 0x30 8000696: f003 0308 and.w r3, r3, #8 800069a: 603b str r3, [r7, #0] 800069c: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET); 800069e: 2200 movs r2, #0 80006a0: f44f 7170 mov.w r1, #960 @ 0x3c0 80006a4: 482a ldr r0, [pc, #168] @ (8000750 ) 80006a6: f002 fb3f bl 8002d28 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); 80006aa: 2200 movs r2, #0 80006ac: f44f 7180 mov.w r1, #256 @ 0x100 80006b0: 4828 ldr r0, [pc, #160] @ (8000754 ) 80006b2: f002 fb39 bl 8002d28 /*Configure GPIO pins : PC4 PC5 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_5; 80006b6: 2331 movs r3, #49 @ 0x31 80006b8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006ba: 2300 movs r3, #0 80006bc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006be: 2302 movs r3, #2 80006c0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006c2: f107 0314 add.w r3, r7, #20 80006c6: 4619 mov r1, r3 80006c8: 4821 ldr r0, [pc, #132] @ (8000750 ) 80006ca: f002 f981 bl 80029d0 /*Configure GPIO pins : PB0 PB1 PB2 PB10 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10; 80006ce: f240 4307 movw r3, #1031 @ 0x407 80006d2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006d4: 2300 movs r3, #0 80006d6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLDOWN; 80006d8: 2302 movs r3, #2 80006da: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80006dc: f107 0314 add.w r3, r7, #20 80006e0: 4619 mov r1, r3 80006e2: 481d ldr r0, [pc, #116] @ (8000758 ) 80006e4: f002 f974 bl 80029d0 /*Configure GPIO pins : PC6 PC7 PC8 PC9 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 80006e8: f44f 7370 mov.w r3, #960 @ 0x3c0 80006ec: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006ee: 2301 movs r3, #1 80006f0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80006f2: 2300 movs r3, #0 80006f4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80006f6: 2300 movs r3, #0 80006f8: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80006fa: f107 0314 add.w r3, r7, #20 80006fe: 4619 mov r1, r3 8000700: 4813 ldr r0, [pc, #76] @ (8000750 ) 8000702: f002 f965 bl 80029d0 GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14; 8000706: f44f 43c0 mov.w r3, #24576 @ 0x6000 800070a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800070c: 2301 movs r3, #1 800070e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000710: 2300 movs r3, #0 8000712: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000714: 2300 movs r3, #0 8000716: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000718: f107 0314 add.w r3, r7, #20 800071c: 4619 mov r1, r3 800071e: 480e ldr r0, [pc, #56] @ (8000758 ) 8000720: f002 f956 bl 80029d0 /*Configure GPIO pin : PA8 */ GPIO_InitStruct.Pin = GPIO_PIN_8; 8000724: f44f 7380 mov.w r3, #256 @ 0x100 8000728: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800072a: 2301 movs r3, #1 800072c: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800072e: 2300 movs r3, #0 8000730: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000732: 2300 movs r3, #0 8000734: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000736: f107 0314 add.w r3, r7, #20 800073a: 4619 mov r1, r3 800073c: 4805 ldr r0, [pc, #20] @ (8000754 ) 800073e: f002 f947 bl 80029d0 } 8000742: bf00 nop 8000744: 3728 adds r7, #40 @ 0x28 8000746: 46bd mov sp, r7 8000748: bd80 pop {r7, pc} 800074a: bf00 nop 800074c: 40023800 .word 0x40023800 8000750: 40020800 .word 0x40020800 8000754: 40020000 .word 0x40020000 8000758: 40020400 .word 0x40020400 0800075c : I2C_HandleTypeDef hi2c1; /* I2C1 init function */ void MX_I2C1_Init(void) { 800075c: b580 push {r7, lr} 800075e: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8000760: 4b12 ldr r3, [pc, #72] @ (80007ac ) 8000762: 4a13 ldr r2, [pc, #76] @ (80007b0 ) 8000764: 601a str r2, [r3, #0] hi2c1.Init.ClockSpeed = 100000; 8000766: 4b11 ldr r3, [pc, #68] @ (80007ac ) 8000768: 4a12 ldr r2, [pc, #72] @ (80007b4 ) 800076a: 605a str r2, [r3, #4] hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; 800076c: 4b0f ldr r3, [pc, #60] @ (80007ac ) 800076e: 2200 movs r2, #0 8000770: 609a str r2, [r3, #8] hi2c1.Init.OwnAddress1 = 0; 8000772: 4b0e ldr r3, [pc, #56] @ (80007ac ) 8000774: 2200 movs r2, #0 8000776: 60da str r2, [r3, #12] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8000778: 4b0c ldr r3, [pc, #48] @ (80007ac ) 800077a: f44f 4280 mov.w r2, #16384 @ 0x4000 800077e: 611a str r2, [r3, #16] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000780: 4b0a ldr r3, [pc, #40] @ (80007ac ) 8000782: 2200 movs r2, #0 8000784: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2 = 0; 8000786: 4b09 ldr r3, [pc, #36] @ (80007ac ) 8000788: 2200 movs r2, #0 800078a: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 800078c: 4b07 ldr r3, [pc, #28] @ (80007ac ) 800078e: 2200 movs r2, #0 8000790: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8000792: 4b06 ldr r3, [pc, #24] @ (80007ac ) 8000794: 2200 movs r2, #0 8000796: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8000798: 4804 ldr r0, [pc, #16] @ (80007ac ) 800079a: f002 fadf bl 8002d5c 800079e: 4603 mov r3, r0 80007a0: 2b00 cmp r3, #0 80007a2: d001 beq.n 80007a8 { Error_Handler(); 80007a4: f000 fd60 bl 8001268 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 80007a8: bf00 nop 80007aa: bd80 pop {r7, pc} 80007ac: 20000230 .word 0x20000230 80007b0: 40005400 .word 0x40005400 80007b4: 000186a0 .word 0x000186a0 080007b8 : void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) { 80007b8: b580 push {r7, lr} 80007ba: b08a sub sp, #40 @ 0x28 80007bc: af00 add r7, sp, #0 80007be: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007c0: f107 0314 add.w r3, r7, #20 80007c4: 2200 movs r2, #0 80007c6: 601a str r2, [r3, #0] 80007c8: 605a str r2, [r3, #4] 80007ca: 609a str r2, [r3, #8] 80007cc: 60da str r2, [r3, #12] 80007ce: 611a str r2, [r3, #16] if(i2cHandle->Instance==I2C1) 80007d0: 687b ldr r3, [r7, #4] 80007d2: 681b ldr r3, [r3, #0] 80007d4: 4a19 ldr r2, [pc, #100] @ (800083c ) 80007d6: 4293 cmp r3, r2 80007d8: d12b bne.n 8000832 { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80007da: 2300 movs r3, #0 80007dc: 613b str r3, [r7, #16] 80007de: 4b18 ldr r3, [pc, #96] @ (8000840 ) 80007e0: 6b1b ldr r3, [r3, #48] @ 0x30 80007e2: 4a17 ldr r2, [pc, #92] @ (8000840 ) 80007e4: f043 0302 orr.w r3, r3, #2 80007e8: 6313 str r3, [r2, #48] @ 0x30 80007ea: 4b15 ldr r3, [pc, #84] @ (8000840 ) 80007ec: 6b1b ldr r3, [r3, #48] @ 0x30 80007ee: f003 0302 and.w r3, r3, #2 80007f2: 613b str r3, [r7, #16] 80007f4: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80007f6: 23c0 movs r3, #192 @ 0xc0 80007f8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80007fa: 2312 movs r3, #18 80007fc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80007fe: 2300 movs r3, #0 8000800: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000802: 2303 movs r3, #3 8000804: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 8000806: 2304 movs r3, #4 8000808: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800080a: f107 0314 add.w r3, r7, #20 800080e: 4619 mov r1, r3 8000810: 480c ldr r0, [pc, #48] @ (8000844 ) 8000812: f002 f8dd bl 80029d0 /* I2C1 clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 8000816: 2300 movs r3, #0 8000818: 60fb str r3, [r7, #12] 800081a: 4b09 ldr r3, [pc, #36] @ (8000840 ) 800081c: 6c1b ldr r3, [r3, #64] @ 0x40 800081e: 4a08 ldr r2, [pc, #32] @ (8000840 ) 8000820: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8000824: 6413 str r3, [r2, #64] @ 0x40 8000826: 4b06 ldr r3, [pc, #24] @ (8000840 ) 8000828: 6c1b ldr r3, [r3, #64] @ 0x40 800082a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800082e: 60fb str r3, [r7, #12] 8000830: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8000832: bf00 nop 8000834: 3728 adds r7, #40 @ 0x28 8000836: 46bd mov sp, r7 8000838: bd80 pop {r7, pc} 800083a: bf00 nop 800083c: 40005400 .word 0x40005400 8000840: 40023800 .word 0x40023800 8000844: 40020400 .word 0x40020400 08000848 : volatile uint8_t tail; // accessed in ISR volatile uint8_t count; // optional, only if needed } PacketQueue; // Initialize void pq_init(PacketQueue *q){ 8000848: b480 push {r7} 800084a: b083 sub sp, #12 800084c: af00 add r7, sp, #0 800084e: 6078 str r0, [r7, #4] q->head = 0; 8000850: 687b ldr r3, [r7, #4] 8000852: 2200 movs r2, #0 8000854: f883 2180 strb.w r2, [r3, #384] @ 0x180 q->tail = 0; 8000858: 687b ldr r3, [r7, #4] 800085a: 2200 movs r2, #0 800085c: f883 2181 strb.w r2, [r3, #385] @ 0x181 q->count = 0; 8000860: 687b ldr r3, [r7, #4] 8000862: 2200 movs r2, #0 8000864: f883 2182 strb.w r2, [r3, #386] @ 0x182 } 8000868: bf00 nop 800086a: 370c adds r7, #12 800086c: 46bd mov sp, r7 800086e: f85d 7b04 ldr.w r7, [sp], #4 8000872: 4770 bx lr 08000874 : // Called from ISR bool pq_push(PacketQueue *q, const uint8_t packet[PACKET_SIZE]){ 8000874: b580 push {r7, lr} 8000876: b084 sub sp, #16 8000878: af00 add r7, sp, #0 800087a: 6078 str r0, [r7, #4] 800087c: 6039 str r1, [r7, #0] uint8_t nextTail = (q->tail + 1) % QUEUE_CAPACITY; 800087e: 687b ldr r3, [r7, #4] 8000880: f893 3181 ldrb.w r3, [r3, #385] @ 0x181 8000884: b2db uxtb r3, r3 8000886: 3301 adds r3, #1 8000888: 425a negs r2, r3 800088a: f003 031f and.w r3, r3, #31 800088e: f002 021f and.w r2, r2, #31 8000892: bf58 it pl 8000894: 4253 negpl r3, r2 8000896: 73fb strb r3, [r7, #15] if(nextTail == q->head) return false; // queue full 8000898: 687b ldr r3, [r7, #4] 800089a: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 800089e: b2db uxtb r3, r3 80008a0: 7bfa ldrb r2, [r7, #15] 80008a2: 429a cmp r2, r3 80008a4: d101 bne.n 80008aa 80008a6: 2300 movs r3, #0 80008a8: e014 b.n 80008d4 memcpy(q->data[q->tail], packet, PACKET_SIZE); 80008aa: 687b ldr r3, [r7, #4] 80008ac: f893 3181 ldrb.w r3, [r3, #385] @ 0x181 80008b0: b2db uxtb r3, r3 80008b2: 461a mov r2, r3 80008b4: 4613 mov r3, r2 80008b6: 005b lsls r3, r3, #1 80008b8: 4413 add r3, r2 80008ba: 009b lsls r3, r3, #2 80008bc: 687a ldr r2, [r7, #4] 80008be: 4413 add r3, r2 80008c0: 220c movs r2, #12 80008c2: 6839 ldr r1, [r7, #0] 80008c4: 4618 mov r0, r3 80008c6: f00a fd7f bl 800b3c8 q->tail = nextTail; 80008ca: 687b ldr r3, [r7, #4] 80008cc: 7bfa ldrb r2, [r7, #15] 80008ce: f883 2181 strb.w r2, [r3, #385] @ 0x181 return true; 80008d2: 2301 movs r3, #1 } 80008d4: 4618 mov r0, r3 80008d6: 3710 adds r7, #16 80008d8: 46bd mov sp, r7 80008da: bd80 pop {r7, pc} 080008dc : // Called from main bool pq_pop(PacketQueue *q, uint8_t out_packet[PACKET_SIZE]){ 80008dc: b580 push {r7, lr} 80008de: b082 sub sp, #8 80008e0: af00 add r7, sp, #0 80008e2: 6078 str r0, [r7, #4] 80008e4: 6039 str r1, [r7, #0] if(q->head == q->tail) return false; // queue empty 80008e6: 687b ldr r3, [r7, #4] 80008e8: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 80008ec: b2da uxtb r2, r3 80008ee: 687b ldr r3, [r7, #4] 80008f0: f893 3181 ldrb.w r3, [r3, #385] @ 0x181 80008f4: b2db uxtb r3, r3 80008f6: 429a cmp r2, r3 80008f8: d101 bne.n 80008fe 80008fa: 2300 movs r3, #0 80008fc: e020 b.n 8000940 memcpy(out_packet, q->data[q->head], PACKET_SIZE); 80008fe: 687b ldr r3, [r7, #4] 8000900: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 8000904: b2db uxtb r3, r3 8000906: 461a mov r2, r3 8000908: 4613 mov r3, r2 800090a: 005b lsls r3, r3, #1 800090c: 4413 add r3, r2 800090e: 009b lsls r3, r3, #2 8000910: 687a ldr r2, [r7, #4] 8000912: 4413 add r3, r2 8000914: 220c movs r2, #12 8000916: 4619 mov r1, r3 8000918: 6838 ldr r0, [r7, #0] 800091a: f00a fd55 bl 800b3c8 q->head = (q->head + 1) % QUEUE_CAPACITY; 800091e: 687b ldr r3, [r7, #4] 8000920: f893 3180 ldrb.w r3, [r3, #384] @ 0x180 8000924: b2db uxtb r3, r3 8000926: 3301 adds r3, #1 8000928: 425a negs r2, r3 800092a: f003 031f and.w r3, r3, #31 800092e: f002 021f and.w r2, r2, #31 8000932: bf58 it pl 8000934: 4253 negpl r3, r2 8000936: b2da uxtb r2, r3 8000938: 687b ldr r3, [r7, #4] 800093a: f883 2180 strb.w r2, [r3, #384] @ 0x180 return true; 800093e: 2301 movs r3, #1 } 8000940: 4618 mov r0, r3 8000942: 3708 adds r7, #8 8000944: 46bd mov sp, r7 8000946: bd80 pop {r7, pc} 08000948
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000948: b580 push {r7, lr} 800094a: b088 sub sp, #32 800094c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800094e: f001 fa95 bl 8001e7c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000952: f000 f97b bl 8000c4c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000956: f7ff fe51 bl 80005fc MX_DMA_Init();MX_PWM_Init(); 800095a: f7ff fde9 bl 8000530 800095e: f000 fc89 bl 8001274 MX_TIM2_Init(); 8000962: f000 fdab bl 80014bc MX_TIM3_Init(); 8000966: f000 fe01 bl 800156c MX_UART4_Init(); 800096a: f000 fef3 bl 8001754 MX_UART5_Init(); 800096e: f000 ff1b bl 80017a8 MX_USART1_UART_Init(); 8000972: f000 ff43 bl 80017fc MX_USART2_UART_Init(); 8000976: f000 ff6b bl 8001850 MX_I2C1_Init(); 800097a: f7ff feef bl 800075c MX_USB_DEVICE_Init(); 800097e: f00a f849 bl 800aa14 MX_PWM_Init(); 8000982: f000 fc77 bl 8001274 /* USER CODE BEGIN 2 */ //Enable UART RX DMA for all ports HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000986: 2210 movs r2, #16 8000988: 4958 ldr r1, [pc, #352] @ (8000aec ) 800098a: 4859 ldr r0, [pc, #356] @ (8000af0 ) 800098c: f005 fe48 bl 8006620 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000990: 2210 movs r2, #16 8000992: 4958 ldr r1, [pc, #352] @ (8000af4 ) 8000994: 4858 ldr r0, [pc, #352] @ (8000af8 ) 8000996: f005 fe43 bl 8006620 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 800099a: 2210 movs r2, #16 800099c: 4957 ldr r1, [pc, #348] @ (8000afc ) 800099e: 4858 ldr r0, [pc, #352] @ (8000b00 ) 80009a0: f005 fe3e bl 8006620 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 80009a4: 2210 movs r2, #16 80009a6: 4957 ldr r1, [pc, #348] @ (8000b04 ) 80009a8: 4857 ldr r0, [pc, #348] @ (8000b08 ) 80009aa: f005 fe39 bl 8006620 // Start TIM3 encoder (PA6/PA7) so we can read encoder delta HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL); 80009ae: 213c movs r1, #60 @ 0x3c 80009b0: 4856 ldr r0, [pc, #344] @ (8000b0c ) 80009b2: f005 f8c5 bl 8005b40 LAST_ENCODER_COUNT = __HAL_TIM_GET_COUNTER(&htim3); 80009b6: 4b55 ldr r3, [pc, #340] @ (8000b0c ) 80009b8: 681b ldr r3, [r3, #0] 80009ba: 6a5b ldr r3, [r3, #36] @ 0x24 80009bc: 461a mov r2, r3 80009be: 4b54 ldr r3, [pc, #336] @ (8000b10 ) 80009c0: 601a str r2, [r3, #0] //Prealloc Kestate matrix memset(KEYSTATE, 0, sizeof(KEYSTATE)); 80009c2: 224b movs r2, #75 @ 0x4b 80009c4: 2100 movs r1, #0 80009c6: 4853 ldr r0, [pc, #332] @ (8000b14 ) 80009c8: f00a fcd2 bl 800b370 pq_init(&huart1q); 80009cc: 4852 ldr r0, [pc, #328] @ (8000b18 ) 80009ce: f7ff ff3b bl 8000848 pq_init(&huart2q); 80009d2: 4852 ldr r0, [pc, #328] @ (8000b1c ) 80009d4: f7ff ff38 bl 8000848 pq_init(&huart4q); 80009d8: 4851 ldr r0, [pc, #324] @ (8000b20 ) 80009da: f7ff ff35 bl 8000848 pq_init(&huart5q); 80009de: 4851 ldr r0, [pc, #324] @ (8000b24 ) 80009e0: f7ff ff32 bl 8000848 PWM_Start(); 80009e4: f000 fc74 bl 80012d0 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { __HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_1, 67); 80009e8: 4b4f ldr r3, [pc, #316] @ (8000b28 ) 80009ea: 681b ldr r3, [r3, #0] 80009ec: 2243 movs r2, #67 @ 0x43 80009ee: 635a str r2, [r3, #52] @ 0x34 switch (MODE){ 80009f0: 4b4e ldr r3, [pc, #312] @ (8000b2c ) 80009f2: 781b ldrb r3, [r3, #0] 80009f4: b2db uxtb r3, r3 80009f6: 2b02 cmp r3, #2 80009f8: d006 beq.n 8000a08 80009fa: 2b02 cmp r3, #2 80009fc: dc6e bgt.n 8000adc 80009fe: 2b00 cmp r3, #0 8000a00: d027 beq.n 8000a52 8000a02: 2b01 cmp r3, #1 8000a04: d05c beq.n 8000ac0 encoderProcess(); USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); break; default: break; 8000a06: e069 b.n 8000adc KEYSTATE_CHANGED_FLAG = 1; 8000a08: 4b49 ldr r3, [pc, #292] @ (8000b30 ) 8000a0a: 2201 movs r2, #1 8000a0c: 701a strb r2, [r3, #0] resetReport(); 8000a0e: f000 fc1f bl 8001250 matrixScan(); 8000a12: f000 fb47 bl 80010a4 mergeChild(); 8000a16: f000 f895 bl 8000b44 encoderProcess(); 8000a1a: f000 fbbb bl 8001194 if(KEYSTATE_CHANGED_FLAG == 1){ 8000a1e: 4b44 ldr r3, [pc, #272] @ (8000b30 ) 8000a20: 781b ldrb r3, [r3, #0] 8000a22: 2b01 cmp r3, #1 8000a24: d15c bne.n 8000ae0 UARTREPORT.DEPTH = DEPTH; 8000a26: 4b43 ldr r3, [pc, #268] @ (8000b34 ) 8000a28: 881b ldrh r3, [r3, #0] 8000a2a: 823b strh r3, [r7, #16] UARTREPORT.TYPE = 0xEE; 8000a2c: 23ee movs r3, #238 @ 0xee 8000a2e: 827b strh r3, [r7, #18] memcpy(UARTREPORT.KEYPRESS, REPORT.KEYPRESS, sizeof(UARTREPORT.KEYPRESS)); 8000a30: 4a41 ldr r2, [pc, #260] @ (8000b38 ) 8000a32: f107 0314 add.w r3, r7, #20 8000a36: 3202 adds r2, #2 8000a38: 6810 ldr r0, [r2, #0] 8000a3a: 6851 ldr r1, [r2, #4] 8000a3c: 6892 ldr r2, [r2, #8] 8000a3e: c307 stmia r3!, {r0, r1, r2} HAL_UART_Transmit_DMA(PARENT, (uint8_t*)&UARTREPORT, sizeof(UARTREPORT)); 8000a40: 4b3e ldr r3, [pc, #248] @ (8000b3c ) 8000a42: 681b ldr r3, [r3, #0] 8000a44: f107 0110 add.w r1, r7, #16 8000a48: 2210 movs r2, #16 8000a4a: 4618 mov r0, r3 8000a4c: f005 fd6c bl 8006528 break; 8000a50: e046 b.n 8000ae0 if(hUsbDeviceFS.dev_state == USBD_STATE_CONFIGURED){ 8000a52: 4b3b ldr r3, [pc, #236] @ (8000b40 ) 8000a54: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8000a58: b2db uxtb r3, r3 8000a5a: 2b03 cmp r3, #3 8000a5c: d106 bne.n 8000a6c MODE = MODE_MAINBOARD; 8000a5e: 4b33 ldr r3, [pc, #204] @ (8000b2c ) 8000a60: 2201 movs r2, #1 8000a62: 701a strb r2, [r3, #0] DEPTH = 0; 8000a64: 4b33 ldr r3, [pc, #204] @ (8000b34 ) 8000a66: 2200 movs r2, #0 8000a68: 801a strh r2, [r3, #0] break; 8000a6a: e03a b.n 8000ae2 REQ.DEPTH = 0; 8000a6c: 2300 movs r3, #0 8000a6e: 803b strh r3, [r7, #0] REQ.TYPE = 0xFF; //Message code for request is 0xFF 8000a70: 23ff movs r3, #255 @ 0xff 8000a72: 807b strh r3, [r7, #2] memset(REQ.KEYPRESS, 0, sizeof(REQ.KEYPRESS)); 8000a74: 463b mov r3, r7 8000a76: 3304 adds r3, #4 8000a78: 220c movs r2, #12 8000a7a: 2100 movs r1, #0 8000a7c: 4618 mov r0, r3 8000a7e: f00a fc77 bl 800b370 HAL_UART_Transmit_DMA(&huart1, (uint8_t*)&REQ, sizeof(REQ)); 8000a82: 463b mov r3, r7 8000a84: 2210 movs r2, #16 8000a86: 4619 mov r1, r3 8000a88: 4819 ldr r0, [pc, #100] @ (8000af0 ) 8000a8a: f005 fd4d bl 8006528 HAL_UART_Transmit_DMA(&huart2, (uint8_t*)&REQ, sizeof(REQ)); 8000a8e: 463b mov r3, r7 8000a90: 2210 movs r2, #16 8000a92: 4619 mov r1, r3 8000a94: 4818 ldr r0, [pc, #96] @ (8000af8 ) 8000a96: f005 fd47 bl 8006528 HAL_UART_Transmit_DMA(&huart4, (uint8_t*)&REQ, sizeof(REQ)); 8000a9a: 463b mov r3, r7 8000a9c: 2210 movs r2, #16 8000a9e: 4619 mov r1, r3 8000aa0: 4817 ldr r0, [pc, #92] @ (8000b00 ) 8000aa2: f005 fd41 bl 8006528 HAL_UART_Transmit_DMA(&huart5, (uint8_t*)&REQ, sizeof(REQ)); 8000aa6: 463b mov r3, r7 8000aa8: 2210 movs r2, #16 8000aaa: 4619 mov r1, r3 8000aac: 4816 ldr r0, [pc, #88] @ (8000b08 ) 8000aae: f005 fd3b bl 8006528 HAL_Delay(500); 8000ab2: f44f 70fa mov.w r0, #500 @ 0x1f4 8000ab6: f001 fa53 bl 8001f60 findBestParent(); //So true... 8000aba: f000 f9db bl 8000e74 break; 8000abe: e010 b.n 8000ae2 resetReport(); 8000ac0: f000 fbc6 bl 8001250 matrixScan();//Something related to this making the key stick. Likely due to race conditions 8000ac4: f000 faee bl 80010a4 mergeChild(); 8000ac8: f000 f83c bl 8000b44 encoderProcess(); 8000acc: f000 fb62 bl 8001194 USBD_HID_SendReport(&hUsbDeviceFS, (uint8_t*)&REPORT, sizeof(REPORT)); 8000ad0: 220e movs r2, #14 8000ad2: 4919 ldr r1, [pc, #100] @ (8000b38 ) 8000ad4: 481a ldr r0, [pc, #104] @ (8000b40 ) 8000ad6: f008 fbd1 bl 800927c break; 8000ada: e002 b.n 8000ae2 break; 8000adc: bf00 nop 8000ade: e000 b.n 8000ae2 break; 8000ae0: bf00 nop } HAL_Delay(20); 8000ae2: 2014 movs r0, #20 8000ae4: f001 fa3c bl 8001f60 __HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_1, 67); 8000ae8: e77e b.n 80009e8 8000aea: bf00 nop 8000aec: 200002a4 .word 0x200002a4 8000af0: 20000a90 .word 0x20000a90 8000af4: 200002b4 .word 0x200002b4 8000af8: 20000ad8 .word 0x20000ad8 8000afc: 200002c4 .word 0x200002c4 8000b00: 20000a00 .word 0x20000a00 8000b04: 20000294 .word 0x20000294 8000b08: 20000a48 .word 0x20000a48 8000b0c: 200009b8 .word 0x200009b8 8000b10: 2000032c .word 0x2000032c 8000b14: 200002e0 .word 0x200002e0 8000b18: 20000360 .word 0x20000360 8000b1c: 200004e4 .word 0x200004e4 8000b20: 20000668 .word 0x20000668 8000b24: 200007ec .word 0x200007ec 8000b28: 20000970 .word 0x20000970 8000b2c: 2000032b .word 0x2000032b 8000b30: 200002dc .word 0x200002dc 8000b34: 200002d4 .word 0x200002d4 8000b38: 20000284 .word 0x20000284 8000b3c: 200002d8 .word 0x200002d8 8000b40: 20000e28 .word 0x20000e28 08000b44 : /* USER CODE BEGIN 3 */ } /* USER CODE END 3 */ } void mergeChild(){ 8000b44: b590 push {r4, r7, lr} 8000b46: b087 sub sp, #28 8000b48: af00 add r7, sp, #0 uint8_t packet[12]; if (pq_pop(&huart1q, packet)) { 8000b4a: 1d3b adds r3, r7, #4 8000b4c: 4619 mov r1, r3 8000b4e: 4838 ldr r0, [pc, #224] @ (8000c30 ) 8000b50: f7ff fec4 bl 80008dc 8000b54: 4603 mov r3, r0 8000b56: 2b00 cmp r3, #0 8000b58: d008 beq.n 8000b6c memcpy(UART_KEYSTATE[1], packet, 12); 8000b5a: 4b36 ldr r3, [pc, #216] @ (8000c34 ) 8000b5c: 330c adds r3, #12 8000b5e: 1d3a adds r2, r7, #4 8000b60: ca07 ldmia r2, {r0, r1, r2} 8000b62: e883 0007 stmia.w r3, {r0, r1, r2} KEYSTATE_CHANGED_FLAG = 1; 8000b66: 4b34 ldr r3, [pc, #208] @ (8000c38 ) 8000b68: 2201 movs r2, #1 8000b6a: 701a strb r2, [r3, #0] } if (pq_pop(&huart2q, packet)) { 8000b6c: 1d3b adds r3, r7, #4 8000b6e: 4619 mov r1, r3 8000b70: 4832 ldr r0, [pc, #200] @ (8000c3c ) 8000b72: f7ff feb3 bl 80008dc 8000b76: 4603 mov r3, r0 8000b78: 2b00 cmp r3, #0 8000b7a: d008 beq.n 8000b8e memcpy(UART_KEYSTATE[2], packet, 12); 8000b7c: 4b2d ldr r3, [pc, #180] @ (8000c34 ) 8000b7e: 3318 adds r3, #24 8000b80: 1d3a adds r2, r7, #4 8000b82: ca07 ldmia r2, {r0, r1, r2} 8000b84: e883 0007 stmia.w r3, {r0, r1, r2} KEYSTATE_CHANGED_FLAG = 1; 8000b88: 4b2b ldr r3, [pc, #172] @ (8000c38 ) 8000b8a: 2201 movs r2, #1 8000b8c: 701a strb r2, [r3, #0] } if (pq_pop(&huart4q, packet)) { 8000b8e: 1d3b adds r3, r7, #4 8000b90: 4619 mov r1, r3 8000b92: 482b ldr r0, [pc, #172] @ (8000c40 ) 8000b94: f7ff fea2 bl 80008dc 8000b98: 4603 mov r3, r0 8000b9a: 2b00 cmp r3, #0 8000b9c: d008 beq.n 8000bb0 memcpy(UART_KEYSTATE[3], packet, 12); 8000b9e: 4b25 ldr r3, [pc, #148] @ (8000c34 ) 8000ba0: 3324 adds r3, #36 @ 0x24 8000ba2: 1d3a adds r2, r7, #4 8000ba4: ca07 ldmia r2, {r0, r1, r2} 8000ba6: e883 0007 stmia.w r3, {r0, r1, r2} KEYSTATE_CHANGED_FLAG = 1; 8000baa: 4b23 ldr r3, [pc, #140] @ (8000c38 ) 8000bac: 2201 movs r2, #1 8000bae: 701a strb r2, [r3, #0] } if (pq_pop(&huart5q, packet)) { 8000bb0: 1d3b adds r3, r7, #4 8000bb2: 4619 mov r1, r3 8000bb4: 4823 ldr r0, [pc, #140] @ (8000c44 ) 8000bb6: f7ff fe91 bl 80008dc 8000bba: 4603 mov r3, r0 8000bbc: 2b00 cmp r3, #0 8000bbe: d009 beq.n 8000bd4 memcpy(UART_KEYSTATE[0], packet, 12); 8000bc0: 4b1c ldr r3, [pc, #112] @ (8000c34 ) 8000bc2: 461c mov r4, r3 8000bc4: 1d3b adds r3, r7, #4 8000bc6: e893 0007 ldmia.w r3, {r0, r1, r2} 8000bca: e884 0007 stmia.w r4, {r0, r1, r2} KEYSTATE_CHANGED_FLAG = 1; 8000bce: 4b1a ldr r3, [pc, #104] @ (8000c38 ) 8000bd0: 2201 movs r2, #1 8000bd2: 701a strb r2, [r3, #0] } for(int i = 0; i < 4; i++){ 8000bd4: 2300 movs r3, #0 8000bd6: 617b str r3, [r7, #20] 8000bd8: e022 b.n 8000c20 for(int j = 0; j < 12; j++){ 8000bda: 2300 movs r3, #0 8000bdc: 613b str r3, [r7, #16] 8000bde: e019 b.n 8000c14 REPORT.KEYPRESS[j] |= UART_KEYSTATE[i][j]; 8000be0: 4a19 ldr r2, [pc, #100] @ (8000c48 ) 8000be2: 693b ldr r3, [r7, #16] 8000be4: 4413 add r3, r2 8000be6: 3302 adds r3, #2 8000be8: 7819 ldrb r1, [r3, #0] 8000bea: 4812 ldr r0, [pc, #72] @ (8000c34 ) 8000bec: 697a ldr r2, [r7, #20] 8000bee: 4613 mov r3, r2 8000bf0: 005b lsls r3, r3, #1 8000bf2: 4413 add r3, r2 8000bf4: 009b lsls r3, r3, #2 8000bf6: 18c2 adds r2, r0, r3 8000bf8: 693b ldr r3, [r7, #16] 8000bfa: 4413 add r3, r2 8000bfc: 781b ldrb r3, [r3, #0] 8000bfe: 430b orrs r3, r1 8000c00: b2d9 uxtb r1, r3 8000c02: 4a11 ldr r2, [pc, #68] @ (8000c48 ) 8000c04: 693b ldr r3, [r7, #16] 8000c06: 4413 add r3, r2 8000c08: 3302 adds r3, #2 8000c0a: 460a mov r2, r1 8000c0c: 701a strb r2, [r3, #0] for(int j = 0; j < 12; j++){ 8000c0e: 693b ldr r3, [r7, #16] 8000c10: 3301 adds r3, #1 8000c12: 613b str r3, [r7, #16] 8000c14: 693b ldr r3, [r7, #16] 8000c16: 2b0b cmp r3, #11 8000c18: dde2 ble.n 8000be0 for(int i = 0; i < 4; i++){ 8000c1a: 697b ldr r3, [r7, #20] 8000c1c: 3301 adds r3, #1 8000c1e: 617b str r3, [r7, #20] 8000c20: 697b ldr r3, [r7, #20] 8000c22: 2b03 cmp r3, #3 8000c24: ddd9 ble.n 8000bda } } } 8000c26: bf00 nop 8000c28: bf00 nop 8000c2a: 371c adds r7, #28 8000c2c: 46bd mov sp, r7 8000c2e: bd90 pop {r4, r7, pc} 8000c30: 20000360 .word 0x20000360 8000c34: 20000330 .word 0x20000330 8000c38: 200002dc .word 0x200002dc 8000c3c: 200004e4 .word 0x200004e4 8000c40: 20000668 .word 0x20000668 8000c44: 200007ec .word 0x200007ec 8000c48: 20000284 .word 0x20000284 08000c4c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000c4c: b580 push {r7, lr} 8000c4e: b094 sub sp, #80 @ 0x50 8000c50: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000c52: f107 031c add.w r3, r7, #28 8000c56: 2234 movs r2, #52 @ 0x34 8000c58: 2100 movs r1, #0 8000c5a: 4618 mov r0, r3 8000c5c: f00a fb88 bl 800b370 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000c60: f107 0308 add.w r3, r7, #8 8000c64: 2200 movs r2, #0 8000c66: 601a str r2, [r3, #0] 8000c68: 605a str r2, [r3, #4] 8000c6a: 609a str r2, [r3, #8] 8000c6c: 60da str r2, [r3, #12] 8000c6e: 611a str r2, [r3, #16] /** Configure the main internal regulator out put voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 8000c70: 2300 movs r3, #0 8000c72: 607b str r3, [r7, #4] 8000c74: 4b29 ldr r3, [pc, #164] @ (8000d1c ) 8000c76: 6c1b ldr r3, [r3, #64] @ 0x40 8000c78: 4a28 ldr r2, [pc, #160] @ (8000d1c ) 8000c7a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000c7e: 6413 str r3, [r2, #64] @ 0x40 8000c80: 4b26 ldr r3, [pc, #152] @ (8000d1c ) 8000c82: 6c1b ldr r3, [r3, #64] @ 0x40 8000c84: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000c88: 607b str r3, [r7, #4] 8000c8a: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 8000c8c: 2300 movs r3, #0 8000c8e: 603b str r3, [r7, #0] 8000c90: 4b23 ldr r3, [pc, #140] @ (8000d20 ) 8000c92: 681b ldr r3, [r3, #0] 8000c94: f423 4340 bic.w r3, r3, #49152 @ 0xc000 8000c98: 4a21 ldr r2, [pc, #132] @ (8000d20 ) 8000c9a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000c9e: 6013 str r3, [r2, #0] 8000ca0: 4b1f ldr r3, [pc, #124] @ (8000d20 ) 8000ca2: 681b ldr r3, [r3, #0] 8000ca4: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000ca8: 603b str r3, [r7, #0] 8000caa: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000cac: 2301 movs r3, #1 8000cae: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000cb0: f44f 3380 mov.w r3, #65536 @ 0x10000 8000cb4: 623b str r3, [r7, #32] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000cb6: 2302 movs r3, #2 8000cb8: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000cba: f44f 0380 mov.w r3, #4194304 @ 0x400000 8000cbe: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLM = 4; 8000cc0: 2304 movs r3, #4 8000cc2: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLN = 96; 8000cc4: 2360 movs r3, #96 @ 0x60 8000cc6: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8000cc8: 2302 movs r3, #2 8000cca: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLQ = 4; 8000ccc: 2304 movs r3, #4 8000cce: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLR = 2; 8000cd0: 2302 movs r3, #2 8000cd2: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000cd4: f107 031c add.w r3, r7, #28 8000cd8: 4618 mov r0, r3 8000cda: f004 fa7d bl 80051d8 8000cde: 4603 mov r3, r0 8000ce0: 2b00 cmp r3, #0 8000ce2: d001 beq.n 8000ce8 { Error_Handler(); 8000ce4: f000 fac0 bl 8001268 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000ce8: 230f movs r3, #15 8000cea: 60bb str r3, [r7, #8] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000cec: 2302 movs r3, #2 8000cee: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; 8000cf0: 2380 movs r3, #128 @ 0x80 8000cf2: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000cf4: f44f 5380 mov.w r3, #4096 @ 0x1000 8000cf8: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000cfa: 2300 movs r3, #0 8000cfc: 61bb str r3, [r7, #24] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000cfe: f107 0308 add.w r3, r7, #8 8000d02: 2101 movs r1, #1 8000d04: 4618 mov r0, r3 8000d06: f003 fbf3 bl 80044f0 8000d0a: 4603 mov r3, r0 8000d0c: 2b00 cmp r3, #0 8000d0e: d001 beq.n 8000d14 { Error_Handler(); 8000d10: f000 faaa bl 8001268 } } 8000d14: bf00 nop 8000d16: 3750 adds r7, #80 @ 0x50 8000d18: 46bd mov sp, r7 8000d1a: bd80 pop {r7, pc} 8000d1c: 40023800 .word 0x40023800 8000d20: 40007000 .word 0x40007000 08000d24 : /* USER CODE BEGIN 4 */ // UART Message Requests Goes Here void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8000d24: b580 push {r7, lr} 8000d26: b082 sub sp, #8 8000d28: af00 add r7, sp, #0 8000d2a: 6078 str r0, [r7, #4] if (huart->Instance == USART1) { 8000d2c: 687b ldr r3, [r7, #4] 8000d2e: 681b ldr r3, [r3, #0] 8000d30: 4a1e ldr r2, [pc, #120] @ (8000dac ) 8000d32: 4293 cmp r3, r2 8000d34: d109 bne.n 8000d4a handleUARTMessages((uint8_t*)&RX1Msg, &huart1); 8000d36: 491e ldr r1, [pc, #120] @ (8000db0 ) 8000d38: 481e ldr r0, [pc, #120] @ (8000db4 ) 8000d3a: f000 f8dd bl 8000ef8 HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000d3e: 2210 movs r2, #16 8000d40: 491c ldr r1, [pc, #112] @ (8000db4 ) 8000d42: 481b ldr r0, [pc, #108] @ (8000db0 ) 8000d44: f005 fc6c bl 8006620 } else if (huart->Instance == UART5) { handleUARTMessages((uint8_t*)&RX5Msg, &huart5); HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000d48: e02b b.n 8000da2 else if (huart->Instance == USART2) { 8000d4a: 687b ldr r3, [r7, #4] 8000d4c: 681b ldr r3, [r3, #0] 8000d4e: 4a1a ldr r2, [pc, #104] @ (8000db8 ) 8000d50: 4293 cmp r3, r2 8000d52: d109 bne.n 8000d68 handleUARTMessages((uint8_t*)&RX2Msg, &huart2); 8000d54: 4919 ldr r1, [pc, #100] @ (8000dbc ) 8000d56: 481a ldr r0, [pc, #104] @ (8000dc0 ) 8000d58: f000 f8ce bl 8000ef8 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000d5c: 2210 movs r2, #16 8000d5e: 4918 ldr r1, [pc, #96] @ (8000dc0 ) 8000d60: 4816 ldr r0, [pc, #88] @ (8000dbc ) 8000d62: f005 fc5d bl 8006620 } 8000d66: e01c b.n 8000da2 else if (huart->Instance == UART4) { 8000d68: 687b ldr r3, [r7, #4] 8000d6a: 681b ldr r3, [r3, #0] 8000d6c: 4a15 ldr r2, [pc, #84] @ (8000dc4 ) 8000d6e: 4293 cmp r3, r2 8000d70: d109 bne.n 8000d86 handleUARTMessages((uint8_t*)&RX4Msg, &huart4); 8000d72: 4915 ldr r1, [pc, #84] @ (8000dc8 ) 8000d74: 4815 ldr r0, [pc, #84] @ (8000dcc ) 8000d76: f000 f8bf bl 8000ef8 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000d7a: 2210 movs r2, #16 8000d7c: 4913 ldr r1, [pc, #76] @ (8000dcc ) 8000d7e: 4812 ldr r0, [pc, #72] @ (8000dc8 ) 8000d80: f005 fc4e bl 8006620 } 8000d84: e00d b.n 8000da2 else if (huart->Instance == UART5) { 8000d86: 687b ldr r3, [r7, #4] 8000d88: 681b ldr r3, [r3, #0] 8000d8a: 4a11 ldr r2, [pc, #68] @ (8000dd0 ) 8000d8c: 4293 cmp r3, r2 8000d8e: d108 bne.n 8000da2 handleUARTMessages((uint8_t*)&RX5Msg, &huart5); 8000d90: 4910 ldr r1, [pc, #64] @ (8000dd4 ) 8000d92: 4811 ldr r0, [pc, #68] @ (8000dd8 ) 8000d94: f000 f8b0 bl 8000ef8 HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000d98: 2210 movs r2, #16 8000d9a: 490f ldr r1, [pc, #60] @ (8000dd8 ) 8000d9c: 480d ldr r0, [pc, #52] @ (8000dd4 ) 8000d9e: f005 fc3f bl 8006620 } 8000da2: bf00 nop 8000da4: 3708 adds r7, #8 8000da6: 46bd mov sp, r7 8000da8: bd80 pop {r7, pc} 8000daa: bf00 nop 8000dac: 40011000 .word 0x40011000 8000db0: 20000a90 .word 0x20000a90 8000db4: 200002a4 .word 0x200002a4 8000db8: 40004400 .word 0x40004400 8000dbc: 20000ad8 .word 0x20000ad8 8000dc0: 200002b4 .word 0x200002b4 8000dc4: 40004c00 .word 0x40004c00 8000dc8: 20000a00 .word 0x20000a00 8000dcc: 200002c4 .word 0x200002c4 8000dd0: 40005000 .word 0x40005000 8000dd4: 20000a48 .word 0x20000a48 8000dd8: 20000294 .word 0x20000294 08000ddc : void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8000ddc: b580 push {r7, lr} 8000dde: b082 sub sp, #8 8000de0: af00 add r7, sp, #0 8000de2: 6078 str r0, [r7, #4] // Restart DMA on error if (huart->Instance == USART1) { 8000de4: 687b ldr r3, [r7, #4] 8000de6: 681b ldr r3, [r3, #0] 8000de8: 4a16 ldr r2, [pc, #88] @ (8000e44 ) 8000dea: 4293 cmp r3, r2 8000dec: d105 bne.n 8000dfa HAL_UART_Receive_DMA(&huart1, (uint8_t*)&RX1Msg, sizeof(UARTMessage)); 8000dee: 2210 movs r2, #16 8000df0: 4915 ldr r1, [pc, #84] @ (8000e48 ) 8000df2: 4816 ldr r0, [pc, #88] @ (8000e4c ) 8000df4: f005 fc14 bl 8006620 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); } else if (huart->Instance == UART5) { HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); } } 8000df8: e01f b.n 8000e3a else if (huart->Instance == USART2) { 8000dfa: 687b ldr r3, [r7, #4] 8000dfc: 681b ldr r3, [r3, #0] 8000dfe: 4a14 ldr r2, [pc, #80] @ (8000e50 ) 8000e00: 4293 cmp r3, r2 8000e02: d105 bne.n 8000e10 HAL_UART_Receive_DMA(&huart2, (uint8_t*)&RX2Msg, sizeof(UARTMessage)); 8000e04: 2210 movs r2, #16 8000e06: 4913 ldr r1, [pc, #76] @ (8000e54 ) 8000e08: 4813 ldr r0, [pc, #76] @ (8000e58 ) 8000e0a: f005 fc09 bl 8006620 } 8000e0e: e014 b.n 8000e3a else if (huart->Instance == UART4) { 8000e10: 687b ldr r3, [r7, #4] 8000e12: 681b ldr r3, [r3, #0] 8000e14: 4a11 ldr r2, [pc, #68] @ (8000e5c ) 8000e16: 4293 cmp r3, r2 8000e18: d105 bne.n 8000e26 HAL_UART_Receive_DMA(&huart4, (uint8_t*)&RX4Msg, sizeof(UARTMessage)); 8000e1a: 2210 movs r2, #16 8000e1c: 4910 ldr r1, [pc, #64] @ (8000e60 ) 8000e1e: 4811 ldr r0, [pc, #68] @ (8000e64 ) 8000e20: f005 fbfe bl 8006620 } 8000e24: e009 b.n 8000e3a else if (huart->Instance == UART5) { 8000e26: 687b ldr r3, [r7, #4] 8000e28: 681b ldr r3, [r3, #0] 8000e2a: 4a0f ldr r2, [pc, #60] @ (8000e68 ) 8000e2c: 4293 cmp r3, r2 8000e2e: d104 bne.n 8000e3a HAL_UART_Receive_DMA(&huart5, (uint8_t*)&RX5Msg, sizeof(UARTMessage)); 8000e30: 2210 movs r2, #16 8000e32: 490e ldr r1, [pc, #56] @ (8000e6c ) 8000e34: 480e ldr r0, [pc, #56] @ (8000e70 ) 8000e36: f005 fbf3 bl 8006620 } 8000e3a: bf00 nop 8000e3c: 3708 adds r7, #8 8000e3e: 46bd mov sp, r7 8000e40: bd80 pop {r7, pc} 8000e42: bf00 nop 8000e44: 40011000 .word 0x40011000 8000e48: 200002a4 .word 0x200002a4 8000e4c: 20000a90 .word 0x20000a90 8000e50: 40004400 .word 0x40004400 8000e54: 200002b4 .word 0x200002b4 8000e58: 20000ad8 .word 0x20000ad8 8000e5c: 40004c00 .word 0x40004c00 8000e60: 200002c4 .word 0x200002c4 8000e64: 20000a00 .word 0x20000a00 8000e68: 40005000 .word 0x40005000 8000e6c: 20000294 .word 0x20000294 8000e70: 20000a48 .word 0x20000a48 08000e74 : void findBestParent(){ 8000e74: b580 push {r7, lr} 8000e76: b084 sub sp, #16 8000e78: af00 add r7, sp, #0 //Find least depth parent uint16_t least_val = 0xFF; 8000e7a: 23ff movs r3, #255 @ 0xff 8000e7c: 81fb strh r3, [r7, #14] UART_HandleTypeDef* least_port = NULL; 8000e7e: 2300 movs r3, #0 8000e80: 60bb str r3, [r7, #8] for(uint8_t i = 0; i < 4; i++){ 8000e82: 2300 movs r3, #0 8000e84: 71fb strb r3, [r7, #7] 8000e86: e013 b.n 8000eb0 if(PORT_DEPTH[i]) 8000e8c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000e90: 89fa ldrh r2, [r7, #14] 8000e92: 429a cmp r2, r3 8000e94: d909 bls.n 8000eaa least_port = PORTS[i]; 8000e96: 79fb ldrb r3, [r7, #7] 8000e98: 4a13 ldr r2, [pc, #76] @ (8000ee8 ) 8000e9a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000e9e: 60bb str r3, [r7, #8] least_val = PORT_DEPTH[i]; 8000ea0: 79fb ldrb r3, [r7, #7] 8000ea2: 4a10 ldr r2, [pc, #64] @ (8000ee4 ) 8000ea4: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000ea8: 81fb strh r3, [r7, #14] for(uint8_t i = 0; i < 4; i++){ 8000eaa: 79fb ldrb r3, [r7, #7] 8000eac: 3301 adds r3, #1 8000eae: 71fb strb r3, [r7, #7] 8000eb0: 79fb ldrb r3, [r7, #7] 8000eb2: 2b03 cmp r3, #3 8000eb4: d9e8 bls.n 8000e88 } } //Assign if valid if(least_val < 0xFF){ 8000eb6: 89fb ldrh r3, [r7, #14] 8000eb8: 2bfe cmp r3, #254 @ 0xfe 8000eba: d80e bhi.n 8000eda PARENT = least_port; 8000ebc: 4a0b ldr r2, [pc, #44] @ (8000eec ) 8000ebe: 68bb ldr r3, [r7, #8] 8000ec0: 6013 str r3, [r2, #0] DEPTH = least_val + 1; 8000ec2: 89fb ldrh r3, [r7, #14] 8000ec4: 3301 adds r3, #1 8000ec6: b29a uxth r2, r3 8000ec8: 4b09 ldr r3, [pc, #36] @ (8000ef0 ) 8000eca: 801a strh r2, [r3, #0] MODE = MODE_ACTIVE; 8000ecc: 4b09 ldr r3, [pc, #36] @ (8000ef4 ) 8000ece: 2202 movs r2, #2 8000ed0: 701a strb r2, [r3, #0] HAL_Delay(500); 8000ed2: f44f 70fa mov.w r0, #500 @ 0x1f4 8000ed6: f001 f843 bl 8001f60 } } 8000eda: bf00 nop 8000edc: 3710 adds r7, #16 8000ede: 46bd mov sp, r7 8000ee0: bd80 pop {r7, pc} 8000ee2: bf00 nop 8000ee4: 200000ec .word 0x200000ec 8000ee8: 200000f4 .word 0x200000f4 8000eec: 200002d8 .word 0x200002d8 8000ef0: 200002d4 .word 0x200002d4 8000ef4: 2000032b .word 0x2000032b 08000ef8 : // Called when UART RX interrupt completes void handleUARTMessages(uint8_t *data, UART_HandleTypeDef *sender) { 8000ef8: b590 push {r4, r7, lr} 8000efa: b08b sub sp, #44 @ 0x2c 8000efc: af00 add r7, sp, #0 8000efe: 6078 str r0, [r7, #4] 8000f00: 6039 str r1, [r7, #0] UARTMessage msg; UARTMessage reply; // Parse incoming message into struct memcpy(&msg, data, sizeof(UARTMessage)); 8000f02: 687b ldr r3, [r7, #4] 8000f04: f107 0418 add.w r4, r7, #24 8000f08: 6818 ldr r0, [r3, #0] 8000f0a: 6859 ldr r1, [r3, #4] 8000f0c: 689a ldr r2, [r3, #8] 8000f0e: 68db ldr r3, [r3, #12] 8000f10: c40f stmia r4!, {r0, r1, r2, r3} switch(msg.TYPE) { 8000f12: 8b7b ldrh r3, [r7, #26] 8000f14: 2bff cmp r3, #255 @ 0xff 8000f16: d026 beq.n 8000f66 8000f18: 2bff cmp r3, #255 @ 0xff 8000f1a: dc6e bgt.n 8000ffa 8000f1c: 2baa cmp r3, #170 @ 0xaa 8000f1e: d002 beq.n 8000f26 8000f20: 2bee cmp r3, #238 @ 0xee 8000f22: d03a beq.n 8000f9a } break; default: break; 8000f24: e069 b.n 8000ffa if(sender == &huart5) { 8000f26: 683b ldr r3, [r7, #0] 8000f28: 4a39 ldr r2, [pc, #228] @ (8001010 ) 8000f2a: 4293 cmp r3, r2 8000f2c: d103 bne.n 8000f36 PORT_DEPTH[0] = msg.DEPTH; 8000f2e: 8b3a ldrh r2, [r7, #24] 8000f30: 4b38 ldr r3, [pc, #224] @ (8001014 ) 8000f32: 801a strh r2, [r3, #0] break; 8000f34: e063 b.n 8000ffe } else if(sender == &huart1) { 8000f36: 683b ldr r3, [r7, #0] 8000f38: 4a37 ldr r2, [pc, #220] @ (8001018 ) 8000f3a: 4293 cmp r3, r2 8000f3c: d103 bne.n 8000f46 PORT_DEPTH[1] = msg.DEPTH; 8000f3e: 8b3a ldrh r2, [r7, #24] 8000f40: 4b34 ldr r3, [pc, #208] @ (8001014 ) 8000f42: 805a strh r2, [r3, #2] break; 8000f44: e05b b.n 8000ffe } else if(sender == &huart2) { 8000f46: 683b ldr r3, [r7, #0] 8000f48: 4a34 ldr r2, [pc, #208] @ (800101c ) 8000f4a: 4293 cmp r3, r2 8000f4c: d103 bne.n 8000f56 PORT_DEPTH[2] = msg.DEPTH; 8000f4e: 8b3a ldrh r2, [r7, #24] 8000f50: 4b30 ldr r3, [pc, #192] @ (8001014 ) 8000f52: 809a strh r2, [r3, #4] break; 8000f54: e053 b.n 8000ffe } else if(sender == &huart4) { 8000f56: 683b ldr r3, [r7, #0] 8000f58: 4a31 ldr r2, [pc, #196] @ (8001020 ) 8000f5a: 4293 cmp r3, r2 8000f5c: d14f bne.n 8000ffe PORT_DEPTH[3] = msg.DEPTH; 8000f5e: 8b3a ldrh r2, [r7, #24] 8000f60: 4b2c ldr r3, [pc, #176] @ (8001014 ) 8000f62: 80da strh r2, [r3, #6] break; 8000f64: e04b b.n 8000ffe if(MODE!=MODE_INACTIVE){ 8000f66: 4b2f ldr r3, [pc, #188] @ (8001024 ) 8000f68: 781b ldrb r3, [r3, #0] 8000f6a: b2db uxtb r3, r3 8000f6c: 2b00 cmp r3, #0 8000f6e: d048 beq.n 8001002 reply.TYPE = 0xAA; 8000f70: 23aa movs r3, #170 @ 0xaa 8000f72: 817b strh r3, [r7, #10] reply.DEPTH = DEPTH; // use your local DEPTH 8000f74: 4b2c ldr r3, [pc, #176] @ (8001028 ) 8000f76: 881b ldrh r3, [r3, #0] 8000f78: 813b strh r3, [r7, #8] memset(reply.KEYPRESS, 0, sizeof(reply.KEYPRESS)); 8000f7a: f107 0308 add.w r3, r7, #8 8000f7e: 3304 adds r3, #4 8000f80: 220c movs r2, #12 8000f82: 2100 movs r1, #0 8000f84: 4618 mov r0, r3 8000f86: f00a f9f3 bl 800b370 HAL_UART_Transmit_DMA(sender, (uint8_t*)&reply, sizeof(reply)); 8000f8a: f107 0308 add.w r3, r7, #8 8000f8e: 2210 movs r2, #16 8000f90: 4619 mov r1, r3 8000f92: 6838 ldr r0, [r7, #0] 8000f94: f005 fac8 bl 8006528 break; 8000f98: e033 b.n 8001002 if(sender == &huart5) { 8000f9a: 683b ldr r3, [r7, #0] 8000f9c: 4a1c ldr r2, [pc, #112] @ (8001010 ) 8000f9e: 4293 cmp r3, r2 8000fa0: d107 bne.n 8000fb2 pq_push(&huart5q, msg.KEYPRESS); 8000fa2: f107 0318 add.w r3, r7, #24 8000fa6: 3304 adds r3, #4 8000fa8: 4619 mov r1, r3 8000faa: 4820 ldr r0, [pc, #128] @ (800102c ) 8000fac: f7ff fc62 bl 8000874 break; 8000fb0: e029 b.n 8001006 } else if(sender == &huart1) { 8000fb2: 683b ldr r3, [r7, #0] 8000fb4: 4a18 ldr r2, [pc, #96] @ (8001018 ) 8000fb6: 4293 cmp r3, r2 8000fb8: d107 bne.n 8000fca pq_push(&huart1q, msg.KEYPRESS); 8000fba: f107 0318 add.w r3, r7, #24 8000fbe: 3304 adds r3, #4 8000fc0: 4619 mov r1, r3 8000fc2: 481b ldr r0, [pc, #108] @ (8001030 ) 8000fc4: f7ff fc56 bl 8000874 break; 8000fc8: e01d b.n 8001006 } else if(sender == &huart2) { 8000fca: 683b ldr r3, [r7, #0] 8000fcc: 4a13 ldr r2, [pc, #76] @ (800101c ) 8000fce: 4293 cmp r3, r2 8000fd0: d107 bne.n 8000fe2 pq_push(&huart2q, msg.KEYPRESS); 8000fd2: f107 0318 add.w r3, r7, #24 8000fd6: 3304 adds r3, #4 8000fd8: 4619 mov r1, r3 8000fda: 4816 ldr r0, [pc, #88] @ (8001034 ) 8000fdc: f7ff fc4a bl 8000874 break; 8000fe0: e011 b.n 8001006 } else if(sender == &huart4) { 8000fe2: 683b ldr r3, [r7, #0] 8000fe4: 4a0e ldr r2, [pc, #56] @ (8001020 ) 8000fe6: 4293 cmp r3, r2 8000fe8: d10d bne.n 8001006 pq_push(&huart4q, msg.KEYPRESS); 8000fea: f107 0318 add.w r3, r7, #24 8000fee: 3304 adds r3, #4 8000ff0: 4619 mov r1, r3 8000ff2: 4811 ldr r0, [pc, #68] @ (8001038 ) 8000ff4: f7ff fc3e bl 8000874 break; 8000ff8: e005 b.n 8001006 break; 8000ffa: bf00 nop 8000ffc: e004 b.n 8001008 break; 8000ffe: bf00 nop 8001000: e002 b.n 8001008 break; 8001002: bf00 nop 8001004: e000 b.n 8001008 break; 8001006: bf00 nop } } 8001008: bf00 nop 800100a: 372c adds r7, #44 @ 0x2c 800100c: 46bd mov sp, r7 800100e: bd90 pop {r4, r7, pc} 8001010: 20000a48 .word 0x20000a48 8001014: 200000ec .word 0x200000ec 8001018: 20000a90 .word 0x20000a90 800101c: 20000ad8 .word 0x20000ad8 8001020: 20000a00 .word 0x20000a00 8001024: 2000032b .word 0x2000032b 8001028: 200002d4 .word 0x200002d4 800102c: 200007ec .word 0x200007ec 8001030: 20000360 .word 0x20000360 8001034: 200004e4 .word 0x200004e4 8001038: 20000668 .word 0x20000668 0800103c : void addUSBReport(uint8_t usageID){ 800103c: b480 push {r7} 800103e: b085 sub sp, #20 8001040: af00 add r7, sp, #0 8001042: 4603 mov r3, r0 8001044: 71fb strb r3, [r7, #7] if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8001046: 79fb ldrb r3, [r7, #7] 8001048: 2b03 cmp r3, #3 800104a: d922 bls.n 8001092 800104c: 79fb ldrb r3, [r7, #7] 800104e: 2b73 cmp r3, #115 @ 0x73 8001050: d81f bhi.n 8001092 uint16_t bit_index = usageID - 0x04; //Offset, UsageID starts with 0x04. Gives us the actual value of the bit 8001052: 79fb ldrb r3, [r7, #7] 8001054: b29b uxth r3, r3 8001056: 3b04 subs r3, #4 8001058: 81fb strh r3, [r7, #14] uint8_t byte_index = bit_index/8; //Calculates which byte in the REPORT array 800105a: 89fb ldrh r3, [r7, #14] 800105c: 08db lsrs r3, r3, #3 800105e: b29b uxth r3, r3 8001060: 737b strb r3, [r7, #13] uint8_t bit_offset = bit_index%8; //Calculates which bits in the REPORT[byte_index] should be set/unset 8001062: 89fb ldrh r3, [r7, #14] 8001064: b2db uxtb r3, r3 8001066: f003 0307 and.w r3, r3, #7 800106a: 733b strb r3, [r7, #12] REPORT.KEYPRESS[byte_index] |= (1 << bit_offset); 800106c: 7b7b ldrb r3, [r7, #13] 800106e: 4a0c ldr r2, [pc, #48] @ (80010a0 ) 8001070: 4413 add r3, r2 8001072: 789b ldrb r3, [r3, #2] 8001074: b25a sxtb r2, r3 8001076: 7b3b ldrb r3, [r7, #12] 8001078: 2101 movs r1, #1 800107a: fa01 f303 lsl.w r3, r1, r3 800107e: b25b sxtb r3, r3 8001080: 4313 orrs r3, r2 8001082: b25a sxtb r2, r3 8001084: 7b7b ldrb r3, [r7, #13] 8001086: b2d1 uxtb r1, r2 8001088: 4a05 ldr r2, [pc, #20] @ (80010a0 ) 800108a: 4413 add r3, r2 800108c: 460a mov r2, r1 800108e: 709a strb r2, [r3, #2] 8001090: e000 b.n 8001094 if(usageID < 0x04 || usageID > 0x73) return; //Usage ID is out of bounds 8001092: bf00 nop } 8001094: 3714 adds r7, #20 8001096: 46bd mov sp, r7 8001098: f85d 7b04 ldr.w r7, [sp], #4 800109c: 4770 bx lr 800109e: bf00 nop 80010a0: 20000284 .word 0x20000284 080010a4 : void matrixScan(void){ 80010a4: b580 push {r7, lr} 80010a6: b082 sub sp, #8 80010a8: af00 add r7, sp, #0 for (uint8_t col = 0; col < COL; col++){ 80010aa: 2300 movs r3, #0 80010ac: 71fb strb r3, [r7, #7] 80010ae: e05f b.n 8001170 HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_SET); 80010b0: 79fb ldrb r3, [r7, #7] 80010b2: 4a33 ldr r2, [pc, #204] @ (8001180 ) 80010b4: f852 0033 ldr.w r0, [r2, r3, lsl #3] 80010b8: 79fb ldrb r3, [r7, #7] 80010ba: 4a31 ldr r2, [pc, #196] @ (8001180 ) 80010bc: 00db lsls r3, r3, #3 80010be: 4413 add r3, r2 80010c0: 889b ldrh r3, [r3, #4] 80010c2: 2201 movs r2, #1 80010c4: 4619 mov r1, r3 80010c6: f001 fe2f bl 8002d28 HAL_Delay(1); 80010ca: 2001 movs r0, #1 80010cc: f000 ff48 bl 8001f60 for(uint8_t row = 0; row < ROW; row++){ 80010d0: 2300 movs r3, #0 80010d2: 71bb strb r3, [r7, #6] 80010d4: e039 b.n 800114a uint8_t new_key = HAL_GPIO_ReadPin(ROW_PINS[row].GPIOx, ROW_PINS[row].PIN); 80010d6: 79bb ldrb r3, [r7, #6] 80010d8: 4a2a ldr r2, [pc, #168] @ (8001184 ) 80010da: f852 2033 ldr.w r2, [r2, r3, lsl #3] 80010de: 79bb ldrb r3, [r7, #6] 80010e0: 4928 ldr r1, [pc, #160] @ (8001184 ) 80010e2: 00db lsls r3, r3, #3 80010e4: 440b add r3, r1 80010e6: 889b ldrh r3, [r3, #4] 80010e8: 4619 mov r1, r3 80010ea: 4610 mov r0, r2 80010ec: f001 fe04 bl 8002cf8 80010f0: 4603 mov r3, r0 80010f2: 717b strb r3, [r7, #5] if(new_key != KEYSTATE[row][col]){ 80010f4: 79ba ldrb r2, [r7, #6] 80010f6: 79f9 ldrb r1, [r7, #7] 80010f8: 4823 ldr r0, [pc, #140] @ (8001188 ) 80010fa: 4613 mov r3, r2 80010fc: 011b lsls r3, r3, #4 80010fe: 1a9b subs r3, r3, r2 8001100: 4403 add r3, r0 8001102: 440b add r3, r1 8001104: 781b ldrb r3, [r3, #0] 8001106: 797a ldrb r2, [r7, #5] 8001108: 429a cmp r2, r3 800110a: d00c beq.n 8001126 KEYSTATE_CHANGED_FLAG = 1; 800110c: 4b1f ldr r3, [pc, #124] @ (800118c ) 800110e: 2201 movs r2, #1 8001110: 701a strb r2, [r3, #0] KEYSTATE[row][col] = new_key; 8001112: 79ba ldrb r2, [r7, #6] 8001114: 79f9 ldrb r1, [r7, #7] 8001116: 481c ldr r0, [pc, #112] @ (8001188 ) 8001118: 4613 mov r3, r2 800111a: 011b lsls r3, r3, #4 800111c: 1a9b subs r3, r3, r2 800111e: 4403 add r3, r0 8001120: 440b add r3, r1 8001122: 797a ldrb r2, [r7, #5] 8001124: 701a strb r2, [r3, #0] } if(new_key){ 8001126: 797b ldrb r3, [r7, #5] 8001128: 2b00 cmp r3, #0 800112a: d00b beq.n 8001144 addUSBReport(KEYCODES[row][col]); 800112c: 79ba ldrb r2, [r7, #6] 800112e: 79f9 ldrb r1, [r7, #7] 8001130: 4817 ldr r0, [pc, #92] @ (8001190 ) 8001132: 4613 mov r3, r2 8001134: 011b lsls r3, r3, #4 8001136: 1a9b subs r3, r3, r2 8001138: 4403 add r3, r0 800113a: 440b add r3, r1 800113c: 781b ldrb r3, [r3, #0] 800113e: 4618 mov r0, r3 8001140: f7ff ff7c bl 800103c for(uint8_t row = 0; row < ROW; row++){ 8001144: 79bb ldrb r3, [r7, #6] 8001146: 3301 adds r3, #1 8001148: 71bb strb r3, [r7, #6] 800114a: 79bb ldrb r3, [r7, #6] 800114c: 2b04 cmp r3, #4 800114e: d9c2 bls.n 80010d6 } } HAL_GPIO_WritePin(COLUMN_PINS[col].GPIOx, COLUMN_PINS[col].PIN, GPIO_PIN_RESET); 8001150: 79fb ldrb r3, [r7, #7] 8001152: 4a0b ldr r2, [pc, #44] @ (8001180 ) 8001154: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8001158: 79fb ldrb r3, [r7, #7] 800115a: 4a09 ldr r2, [pc, #36] @ (8001180 ) 800115c: 00db lsls r3, r3, #3 800115e: 4413 add r3, r2 8001160: 889b ldrh r3, [r3, #4] 8001162: 2200 movs r2, #0 8001164: 4619 mov r1, r3 8001166: f001 fddf bl 8002d28 for (uint8_t col = 0; col < COL; col++){ 800116a: 79fb ldrb r3, [r7, #7] 800116c: 3301 adds r3, #1 800116e: 71fb strb r3, [r7, #7] 8001170: 79fb ldrb r3, [r7, #7] 8001172: 2b0e cmp r3, #14 8001174: d99c bls.n 80010b0 } } 8001176: bf00 nop 8001178: bf00 nop 800117a: 3708 adds r7, #8 800117c: 46bd mov sp, r7 800117e: bd80 pop {r7, pc} 8001180: 20000028 .word 0x20000028 8001184: 20000000 .word 0x20000000 8001188: 200002e0 .word 0x200002e0 800118c: 200002dc .word 0x200002dc 8001190: 200000a0 .word 0x200000a0 08001194 : // Read TIM3 encoder counter, calculate delta and add corresponding keycodes void encoderProcess(void){ 8001194: b580 push {r7, lr} 8001196: b086 sub sp, #24 8001198: af00 add r7, sp, #0 int32_t cnt = (int32_t)__HAL_TIM_GET_COUNTER(&htim3); 800119a: 4b2a ldr r3, [pc, #168] @ (8001244 ) 800119c: 681b ldr r3, [r3, #0] 800119e: 6a5b ldr r3, [r3, #36] @ 0x24 80011a0: 603b str r3, [r7, #0] int32_t diff = cnt - LAST_ENCODER_COUNT; 80011a2: 4b29 ldr r3, [pc, #164] @ (8001248 ) 80011a4: 681b ldr r3, [r3, #0] 80011a6: 683a ldr r2, [r7, #0] 80011a8: 1ad3 subs r3, r2, r3 80011aa: 617b str r3, [r7, #20] // TIM3 configured as 16-bit counter (period 65535). Fix wrap-around. if(diff > 32767) diff -= 65536; 80011ac: 697b ldr r3, [r7, #20] 80011ae: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80011b2: db03 blt.n 80011bc 80011b4: 697b ldr r3, [r7, #20] 80011b6: f5a3 3380 sub.w r3, r3, #65536 @ 0x10000 80011ba: 617b str r3, [r7, #20] if(diff < -32768) diff += 65536; 80011bc: 697b ldr r3, [r7, #20] 80011be: f513 4f00 cmn.w r3, #32768 @ 0x8000 80011c2: da03 bge.n 80011cc 80011c4: 697b ldr r3, [r7, #20] 80011c6: f503 3380 add.w r3, r3, #65536 @ 0x10000 80011ca: 617b str r3, [r7, #20] if(diff > 0){ 80011cc: 697b ldr r3, [r7, #20] 80011ce: 2b00 cmp r3, #0 80011d0: dd17 ble.n 8001202 int steps = diff; 80011d2: 697b ldr r3, [r7, #20] 80011d4: 613b str r3, [r7, #16] if(steps > 10) steps = 10; // cap bursts 80011d6: 693b ldr r3, [r7, #16] 80011d8: 2b0a cmp r3, #10 80011da: dd01 ble.n 80011e0 80011dc: 230a movs r3, #10 80011de: 613b str r3, [r7, #16] for(int i = 0; i < steps; i++){ 80011e0: 2300 movs r3, #0 80011e2: 60fb str r3, [r7, #12] 80011e4: e008 b.n 80011f8 // CW -> KEYCODES[0][0] addUSBReport(KEYCODES[3][3]); 80011e6: 4b19 ldr r3, [pc, #100] @ (800124c ) 80011e8: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 80011ec: 4618 mov r0, r3 80011ee: f7ff ff25 bl 800103c for(int i = 0; i < steps; i++){ 80011f2: 68fb ldr r3, [r7, #12] 80011f4: 3301 adds r3, #1 80011f6: 60fb str r3, [r7, #12] 80011f8: 68fa ldr r2, [r7, #12] 80011fa: 693b ldr r3, [r7, #16] 80011fc: 429a cmp r2, r3 80011fe: dbf2 blt.n 80011e6 8001200: e019 b.n 8001236 } }else if(diff < 0){ 8001202: 697b ldr r3, [r7, #20] 8001204: 2b00 cmp r3, #0 8001206: da16 bge.n 8001236 int steps = -diff; 8001208: 697b ldr r3, [r7, #20] 800120a: 425b negs r3, r3 800120c: 60bb str r3, [r7, #8] if(steps > 10) steps = 10; 800120e: 68bb ldr r3, [r7, #8] 8001210: 2b0a cmp r3, #10 8001212: dd01 ble.n 8001218 8001214: 230a movs r3, #10 8001216: 60bb str r3, [r7, #8] for(int i = 0; i < steps; i++){ 8001218: 2300 movs r3, #0 800121a: 607b str r3, [r7, #4] 800121c: e007 b.n 800122e // CCW -> KEYCODES[0][1] addUSBReport(KEYCODES[2][1]); 800121e: 4b0b ldr r3, [pc, #44] @ (800124c ) 8001220: 7fdb ldrb r3, [r3, #31] 8001222: 4618 mov r0, r3 8001224: f7ff ff0a bl 800103c for(int i = 0; i < steps; i++){ 8001228: 687b ldr r3, [r7, #4] 800122a: 3301 adds r3, #1 800122c: 607b str r3, [r7, #4] 800122e: 687a ldr r2, [r7, #4] 8001230: 68bb ldr r3, [r7, #8] 8001232: 429a cmp r2, r3 8001234: dbf3 blt.n 800121e } } LAST_ENCODER_COUNT = cnt; 8001236: 4a04 ldr r2, [pc, #16] @ (8001248 ) 8001238: 683b ldr r3, [r7, #0] 800123a: 6013 str r3, [r2, #0] } 800123c: bf00 nop 800123e: 3718 adds r7, #24 8001240: 46bd mov sp, r7 8001242: bd80 pop {r7, pc} 8001244: 200009b8 .word 0x200009b8 8001248: 2000032c .word 0x2000032c 800124c: 200000a0 .word 0x200000a0 08001250 : void resetReport(void){ 8001250: b580 push {r7, lr} 8001252: af00 add r7, sp, #0 memset(REPORT.KEYPRESS, 0, sizeof(REPORT.KEYPRESS)); 8001254: 220c movs r2, #12 8001256: 2100 movs r1, #0 8001258: 4802 ldr r0, [pc, #8] @ (8001264 ) 800125a: f00a f889 bl 800b370 } 800125e: bf00 nop 8001260: bd80 pop {r7, pc} 8001262: bf00 nop 8001264: 20000286 .word 0x20000286 08001268 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001268: b480 push {r7} 800126a: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800126c: b672 cpsid i } 800126e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001270: bf00 nop 8001272: e7fd b.n 8001270 08001274 : #include "pwm.h" #include "tim.h" void MX_PWM_Init(void){ 8001274: b580 push {r7, lr} 8001276: b088 sub sp, #32 8001278: af00 add r7, sp, #0 TIM_OC_InitTypeDef sConfigOC = {0}; 800127a: 1d3b adds r3, r7, #4 800127c: 2200 movs r2, #0 800127e: 601a str r2, [r3, #0] 8001280: 605a str r2, [r3, #4] 8001282: 609a str r2, [r3, #8] 8001284: 60da str r2, [r3, #12] 8001286: 611a str r2, [r3, #16] 8001288: 615a str r2, [r3, #20] 800128a: 619a str r2, [r3, #24] // Initialize TIM2 for PWM (safe to call even if TIM2 was previously initialized for OC) if (HAL_TIM_PWM_Init(&htim2) != HAL_OK){ 800128c: 480f ldr r0, [pc, #60] @ (80012cc ) 800128e: f004 fa90 bl 80057b2 8001292: 4603 mov r3, r0 8001294: 2b00 cmp r3, #0 8001296: d001 beq.n 800129c Error_Handler(); 8001298: f7ff ffe6 bl 8001268 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800129c: 2360 movs r3, #96 @ 0x60 800129e: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 80012a0: 2300 movs r3, #0 80012a2: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 80012a4: 2300 movs r3, #0 80012a6: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 80012a8: 2300 movs r3, #0 80012aa: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK){ 80012ac: 1d3b adds r3, r7, #4 80012ae: 2200 movs r2, #0 80012b0: 4619 mov r1, r3 80012b2: 4806 ldr r0, [pc, #24] @ (80012cc ) 80012b4: f004 fd2e bl 8005d14 80012b8: 4603 mov r3, r0 80012ba: 2b00 cmp r3, #0 80012bc: d001 beq.n 80012c2 Error_Handler(); 80012be: f7ff ffd3 bl 8001268 } } 80012c2: bf00 nop 80012c4: 3720 adds r7, #32 80012c6: 46bd mov sp, r7 80012c8: bd80 pop {r7, pc} 80012ca: bf00 nop 80012cc: 20000970 .word 0x20000970 080012d0 : void PWM_Start(void){ 80012d0: b580 push {r7, lr} 80012d2: af00 add r7, sp, #0 HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); 80012d4: 2100 movs r1, #0 80012d6: 4802 ldr r0, [pc, #8] @ (80012e0 ) 80012d8: f004 fac4 bl 8005864 } 80012dc: bf00 nop 80012de: bd80 pop {r7, pc} 80012e0: 20000970 .word 0x20000970 080012e4 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80012e4: b480 push {r7} 80012e6: b083 sub sp, #12 80012e8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80012ea: 2300 movs r3, #0 80012ec: 607b str r3, [r7, #4] 80012ee: 4b10 ldr r3, [pc, #64] @ (8001330 ) 80012f0: 6c5b ldr r3, [r3, #68] @ 0x44 80012f2: 4a0f ldr r2, [pc, #60] @ (8001330 ) 80012f4: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80012f8: 6453 str r3, [r2, #68] @ 0x44 80012fa: 4b0d ldr r3, [pc, #52] @ (8001330 ) 80012fc: 6c5b ldr r3, [r3, #68] @ 0x44 80012fe: f403 4380 and.w r3, r3, #16384 @ 0x4000 8001302: 607b str r3, [r7, #4] 8001304: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8001306: 2300 movs r3, #0 8001308: 603b str r3, [r7, #0] 800130a: 4b09 ldr r3, [pc, #36] @ (8001330 ) 800130c: 6c1b ldr r3, [r3, #64] @ 0x40 800130e: 4a08 ldr r2, [pc, #32] @ (8001330 ) 8001310: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8001314: 6413 str r3, [r2, #64] @ 0x40 8001316: 4b06 ldr r3, [pc, #24] @ (8001330 ) 8001318: 6c1b ldr r3, [r3, #64] @ 0x40 800131a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800131e: 603b str r3, [r7, #0] 8001320: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001322: bf00 nop 8001324: 370c adds r7, #12 8001326: 46bd mov sp, r7 8001328: f85d 7b04 ldr.w r7, [sp], #4 800132c: 4770 bx lr 800132e: bf00 nop 8001330: 40023800 .word 0x40023800 08001334 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001334: b480 push {r7} 8001336: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8001338: bf00 nop 800133a: e7fd b.n 8001338 0800133c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800133c: b480 push {r7} 800133e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8001340: bf00 nop 8001342: e7fd b.n 8001340 08001344 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001344: b480 push {r7} 8001346: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8001348: bf00 nop 800134a: e7fd b.n 8001348 0800134c : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 800134c: b480 push {r7} 800134e: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8001350: bf00 nop 8001352: e7fd b.n 8001350 08001354 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001354: b480 push {r7} 8001356: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8001358: bf00 nop 800135a: e7fd b.n 8001358 0800135c : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800135c: b480 push {r7} 800135e: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8001360: bf00 nop 8001362: 46bd mov sp, r7 8001364: f85d 7b04 ldr.w r7, [sp], #4 8001368: 4770 bx lr 0800136a : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800136a: b480 push {r7} 800136c: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800136e: bf00 nop 8001370: 46bd mov sp, r7 8001372: f85d 7b04 ldr.w r7, [sp], #4 8001376: 4770 bx lr 08001378 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8001378: b480 push {r7} 800137a: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800137c: bf00 nop 800137e: 46bd mov sp, r7 8001380: f85d 7b04 ldr.w r7, [sp], #4 8001384: 4770 bx lr 08001386 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8001386: b580 push {r7, lr} 8001388: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800138a: f000 fdc9 bl 8001f20 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800138e: bf00 nop 8001390: bd80 pop {r7, pc} ... 08001394 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8001394: b580 push {r7, lr} 8001396: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_rx); 8001398: 4802 ldr r0, [pc, #8] @ (80013a4 ) 800139a: f001 f8af bl 80024fc /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 800139e: bf00 nop 80013a0: bd80 pop {r7, pc} 80013a2: bf00 nop 80013a4: 20000be0 .word 0x20000be0 080013a8 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 80013a8: b580 push {r7, lr} 80013aa: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_rx); 80013ac: 4802 ldr r0, [pc, #8] @ (80013b8 ) 80013ae: f001 f8a5 bl 80024fc /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 80013b2: bf00 nop 80013b4: bd80 pop {r7, pc} 80013b6: bf00 nop 80013b8: 20000b20 .word 0x20000b20 080013bc : /** * @brief This function handles DMA1 stream4 global interrupt. */ void DMA1_Stream4_IRQHandler(void) { 80013bc: b580 push {r7, lr} 80013be: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ /* USER CODE END DMA1_Stream4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart4_tx); 80013c0: 4802 ldr r0, [pc, #8] @ (80013cc ) 80013c2: f001 f89b bl 80024fc /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ /* USER CODE END DMA1_Stream4_IRQn 1 */ } 80013c6: bf00 nop 80013c8: bd80 pop {r7, pc} 80013ca: bf00 nop 80013cc: 20000b80 .word 0x20000b80 080013d0 : /** * @brief This function handles DMA1 stream5 global interrupt. */ void DMA1_Stream5_IRQHandler(void) { 80013d0: b580 push {r7, lr} 80013d2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ /* USER CODE END DMA1_Stream5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 80013d4: 4802 ldr r0, [pc, #8] @ (80013e0 ) 80013d6: f001 f891 bl 80024fc /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ /* USER CODE END DMA1_Stream5_IRQn 1 */ } 80013da: bf00 nop 80013dc: bd80 pop {r7, pc} 80013de: bf00 nop 80013e0: 20000d60 .word 0x20000d60 080013e4 : /** * @brief This function handles DMA1 stream6 global interrupt. */ void DMA1_Stream6_IRQHandler(void) { 80013e4: b580 push {r7, lr} 80013e6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ /* USER CODE END DMA1_Stream6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 80013e8: 4802 ldr r0, [pc, #8] @ (80013f4 ) 80013ea: f001 f887 bl 80024fc /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ /* USER CODE END DMA1_Stream6_IRQn 1 */ } 80013ee: bf00 nop 80013f0: bd80 pop {r7, pc} 80013f2: bf00 nop 80013f4: 20000dc0 .word 0x20000dc0 080013f8 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 80013f8: b580 push {r7, lr} 80013fa: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 80013fc: 4802 ldr r0, [pc, #8] @ (8001408 ) 80013fe: f005 f935 bl 800666c /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8001402: bf00 nop 8001404: bd80 pop {r7, pc} 8001406: bf00 nop 8001408: 20000a90 .word 0x20000a90 0800140c : /** * @brief This function handles USART2 global interrupt. */ void USART2_IRQHandler(void) { 800140c: b580 push {r7, lr} 800140e: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 8001410: 4802 ldr r0, [pc, #8] @ (800141c ) 8001412: f005 f92b bl 800666c /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 8001416: bf00 nop 8001418: bd80 pop {r7, pc} 800141a: bf00 nop 800141c: 20000ad8 .word 0x20000ad8 08001420 : /** * @brief This function handles DMA1 stream7 global interrupt. */ void DMA1_Stream7_IRQHandler(void) { 8001420: b580 push {r7, lr} 8001422: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ /* USER CODE END DMA1_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart5_tx); 8001424: 4802 ldr r0, [pc, #8] @ (8001430 ) 8001426: f001 f869 bl 80024fc /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ /* USER CODE END DMA1_Stream7_IRQn 1 */ } 800142a: bf00 nop 800142c: bd80 pop {r7, pc} 800142e: bf00 nop 8001430: 20000c40 .word 0x20000c40 08001434 : /** * @brief This function handles UART4 global interrupt. */ void UART4_IRQHandler(void) { 8001434: b580 push {r7, lr} 8001436: af00 add r7, sp, #0 /* USER CODE BEGIN UART4_IRQn 0 */ /* USER CODE END UART4_IRQn 0 */ HAL_UART_IRQHandler(&huart4); 8001438: 4802 ldr r0, [pc, #8] @ (8001444 ) 800143a: f005 f917 bl 800666c /* USER CODE BEGIN UART4_IRQn 1 */ /* USER CODE END UART4_IRQn 1 */ } 800143e: bf00 nop 8001440: bd80 pop {r7, pc} 8001442: bf00 nop 8001444: 20000a00 .word 0x20000a00 08001448 : /** * @brief This function handles UART5 global interrupt. */ void UART5_IRQHandler(void) { 8001448: b580 push {r7, lr} 800144a: af00 add r7, sp, #0 /* USER CODE BEGIN UART5_IRQn 0 */ /* USER CODE END UART5_IRQn 0 */ HAL_UART_IRQHandler(&huart5); 800144c: 4802 ldr r0, [pc, #8] @ (8001458 ) 800144e: f005 f90d bl 800666c /* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 1 */ } 8001452: bf00 nop 8001454: bd80 pop {r7, pc} 8001456: bf00 nop 8001458: 20000a48 .word 0x20000a48 0800145c : /** * @brief This function handles DMA2 stream2 global interrupt. */ void DMA2_Stream2_IRQHandler(void) { 800145c: b580 push {r7, lr} 800145e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ /* USER CODE END DMA2_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_rx); 8001460: 4802 ldr r0, [pc, #8] @ (800146c ) 8001462: f001 f84b bl 80024fc /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ /* USER CODE END DMA2_Stream2_IRQn 1 */ } 8001466: bf00 nop 8001468: bd80 pop {r7, pc} 800146a: bf00 nop 800146c: 20000ca0 .word 0x20000ca0 08001470 : /** * @brief This function handles USB On The Go FS global interrupt. */ void OTG_FS_IRQHandler(void) { 8001470: b580 push {r7, lr} 8001472: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_FS_IRQn 0 */ /* USER CODE END OTG_FS_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); 8001474: 4802 ldr r0, [pc, #8] @ (8001480 ) 8001476: f001 ff00 bl 800327a /* USER CODE BEGIN OTG_FS_IRQn 1 */ /* USER CODE END OTG_FS_IRQn 1 */ } 800147a: bf00 nop 800147c: bd80 pop {r7, pc} 800147e: bf00 nop 8001480: 20001304 .word 0x20001304 08001484 : /** * @brief This function handles DMA2 stream7 global interrupt. */ void DMA2_Stream7_IRQHandler(void) { 8001484: b580 push {r7, lr} 8001486: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ /* USER CODE END DMA2_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 8001488: 4802 ldr r0, [pc, #8] @ (8001494 ) 800148a: f001 f837 bl 80024fc /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ /* USER CODE END DMA2_Stream7_IRQn 1 */ } 800148e: bf00 nop 8001490: bd80 pop {r7, pc} 8001492: bf00 nop 8001494: 20000d00 .word 0x20000d00 08001498 : * configuration. * @param None * @retval None */ void SystemInit(void) { 8001498: b480 push {r7} 800149a: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 800149c: 4b06 ldr r3, [pc, #24] @ (80014b8 ) 800149e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80014a2: 4a05 ldr r2, [pc, #20] @ (80014b8 ) 80014a4: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 80014a8: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 80014ac: bf00 nop 80014ae: 46bd mov sp, r7 80014b0: f85d 7b04 ldr.w r7, [sp], #4 80014b4: 4770 bx lr 80014b6: bf00 nop 80014b8: e000ed00 .word 0xe000ed00 080014bc : TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; /* TIM2 init function */ void MX_TIM2_Init(void) { 80014bc: b580 push {r7, lr} 80014be: b08a sub sp, #40 @ 0x28 80014c0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 80014c2: f107 0320 add.w r3, r7, #32 80014c6: 2200 movs r2, #0 80014c8: 601a str r2, [r3, #0] 80014ca: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 80014cc: 1d3b adds r3, r7, #4 80014ce: 2200 movs r2, #0 80014d0: 601a str r2, [r3, #0] 80014d2: 605a str r2, [r3, #4] 80014d4: 609a str r2, [r3, #8] 80014d6: 60da str r2, [r3, #12] 80014d8: 611a str r2, [r3, #16] 80014da: 615a str r2, [r3, #20] 80014dc: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 80014de: 4b22 ldr r3, [pc, #136] @ (8001568 ) 80014e0: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 80014e4: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 80014e6: 4b20 ldr r3, [pc, #128] @ (8001568 ) 80014e8: 2200 movs r2, #0 80014ea: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80014ec: 4b1e ldr r3, [pc, #120] @ (8001568 ) 80014ee: 2200 movs r2, #0 80014f0: 609a str r2, [r3, #8] htim2.Init.Period = 4294967295; 80014f2: 4b1d ldr r3, [pc, #116] @ (8001568 ) 80014f4: f04f 32ff mov.w r2, #4294967295 80014f8: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80014fa: 4b1b ldr r3, [pc, #108] @ (8001568 ) 80014fc: 2200 movs r2, #0 80014fe: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001500: 4b19 ldr r3, [pc, #100] @ (8001568 ) 8001502: 2200 movs r2, #0 8001504: 619a str r2, [r3, #24] if (HAL_TIM_OC_Init(&htim2) != HAL_OK) 8001506: 4818 ldr r0, [pc, #96] @ (8001568 ) 8001508: f004 f904 bl 8005714 800150c: 4603 mov r3, r0 800150e: 2b00 cmp r3, #0 8001510: d001 beq.n 8001516 { Error_Handler(); 8001512: f7ff fea9 bl 8001268 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001516: 2300 movs r3, #0 8001518: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800151a: 2300 movs r3, #0 800151c: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 800151e: f107 0320 add.w r3, r7, #32 8001522: 4619 mov r1, r3 8001524: 4810 ldr r0, [pc, #64] @ (8001568 ) 8001526: f004 ff33 bl 8006390 800152a: 4603 mov r3, r0 800152c: 2b00 cmp r3, #0 800152e: d001 beq.n 8001534 { Error_Handler(); 8001530: f7ff fe9a bl 8001268 } sConfigOC.OCMode = TIM_OCMODE_FORCED_ACTIVE; 8001534: 2350 movs r3, #80 @ 0x50 8001536: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 8001538: 2300 movs r3, #0 800153a: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800153c: 2300 movs r3, #0 800153e: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001540: 2300 movs r3, #0 8001542: 617b str r3, [r7, #20] if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8001544: 1d3b adds r3, r7, #4 8001546: 2200 movs r2, #0 8001548: 4619 mov r1, r3 800154a: 4807 ldr r0, [pc, #28] @ (8001568 ) 800154c: f004 fb86 bl 8005c5c 8001550: 4603 mov r3, r0 8001552: 2b00 cmp r3, #0 8001554: d001 beq.n 800155a { Error_Handler(); 8001556: f7ff fe87 bl 8001268 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 800155a: 4803 ldr r0, [pc, #12] @ (8001568 ) 800155c: f000 f8c2 bl 80016e4 } 8001560: bf00 nop 8001562: 3728 adds r7, #40 @ 0x28 8001564: 46bd mov sp, r7 8001566: bd80 pop {r7, pc} 8001568: 20000970 .word 0x20000970 0800156c : /* TIM3 init function */ void MX_TIM3_Init(void) { 800156c: b580 push {r7, lr} 800156e: b08c sub sp, #48 @ 0x30 8001570: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_Encoder_InitTypeDef sConfig = {0}; 8001572: f107 030c add.w r3, r7, #12 8001576: 2224 movs r2, #36 @ 0x24 8001578: 2100 movs r1, #0 800157a: 4618 mov r0, r3 800157c: f009 fef8 bl 800b370 TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001580: 1d3b adds r3, r7, #4 8001582: 2200 movs r2, #0 8001584: 601a str r2, [r3, #0] 8001586: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8001588: 4b20 ldr r3, [pc, #128] @ (800160c ) 800158a: 4a21 ldr r2, [pc, #132] @ (8001610 ) 800158c: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 800158e: 4b1f ldr r3, [pc, #124] @ (800160c ) 8001590: 2200 movs r2, #0 8001592: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8001594: 4b1d ldr r3, [pc, #116] @ (800160c ) 8001596: 2200 movs r2, #0 8001598: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 800159a: 4b1c ldr r3, [pc, #112] @ (800160c ) 800159c: f64f 72ff movw r2, #65535 @ 0xffff 80015a0: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80015a2: 4b1a ldr r3, [pc, #104] @ (800160c ) 80015a4: 2200 movs r2, #0 80015a6: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80015a8: 4b18 ldr r3, [pc, #96] @ (800160c ) 80015aa: 2200 movs r2, #0 80015ac: 619a str r2, [r3, #24] sConfig.EncoderMode = TIM_ENCODERMODE_TI1; 80015ae: 2301 movs r3, #1 80015b0: 60fb str r3, [r7, #12] sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; 80015b2: 2300 movs r3, #0 80015b4: 613b str r3, [r7, #16] sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; 80015b6: 2301 movs r3, #1 80015b8: 617b str r3, [r7, #20] sConfig.IC1Prescaler = TIM_ICPSC_DIV1; 80015ba: 2300 movs r3, #0 80015bc: 61bb str r3, [r7, #24] sConfig.IC1Filter = 0; 80015be: 2300 movs r3, #0 80015c0: 61fb str r3, [r7, #28] sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; 80015c2: 2300 movs r3, #0 80015c4: 623b str r3, [r7, #32] sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; 80015c6: 2301 movs r3, #1 80015c8: 627b str r3, [r7, #36] @ 0x24 sConfig.IC2Prescaler = TIM_ICPSC_DIV1; 80015ca: 2300 movs r3, #0 80015cc: 62bb str r3, [r7, #40] @ 0x28 sConfig.IC2Filter = 0; 80015ce: 2300 movs r3, #0 80015d0: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) 80015d2: f107 030c add.w r3, r7, #12 80015d6: 4619 mov r1, r3 80015d8: 480c ldr r0, [pc, #48] @ (800160c ) 80015da: f004 fa0b bl 80059f4 80015de: 4603 mov r3, r0 80015e0: 2b00 cmp r3, #0 80015e2: d001 beq.n 80015e8 { Error_Handler(); 80015e4: f7ff fe40 bl 8001268 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80015e8: 2300 movs r3, #0 80015ea: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80015ec: 2300 movs r3, #0 80015ee: 60bb str r3, [r7, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80015f0: 1d3b adds r3, r7, #4 80015f2: 4619 mov r1, r3 80015f4: 4805 ldr r0, [pc, #20] @ (800160c ) 80015f6: f004 fecb bl 8006390 80015fa: 4603 mov r3, r0 80015fc: 2b00 cmp r3, #0 80015fe: d001 beq.n 8001604 { Error_Handler(); 8001600: f7ff fe32 bl 8001268 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8001604: bf00 nop 8001606: 3730 adds r7, #48 @ 0x30 8001608: 46bd mov sp, r7 800160a: bd80 pop {r7, pc} 800160c: 200009b8 .word 0x200009b8 8001610: 40000400 .word 0x40000400 08001614 : void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle) { 8001614: b480 push {r7} 8001616: b085 sub sp, #20 8001618: af00 add r7, sp, #0 800161a: 6078 str r0, [r7, #4] if(tim_ocHandle->Instance==TIM2) 800161c: 687b ldr r3, [r7, #4] 800161e: 681b ldr r3, [r3, #0] 8001620: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001624: d10d bne.n 8001642 { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* TIM2 clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 8001626: 2300 movs r3, #0 8001628: 60fb str r3, [r7, #12] 800162a: 4b09 ldr r3, [pc, #36] @ (8001650 ) 800162c: 6c1b ldr r3, [r3, #64] @ 0x40 800162e: 4a08 ldr r2, [pc, #32] @ (8001650 ) 8001630: f043 0301 orr.w r3, r3, #1 8001634: 6413 str r3, [r2, #64] @ 0x40 8001636: 4b06 ldr r3, [pc, #24] @ (8001650 ) 8001638: 6c1b ldr r3, [r3, #64] @ 0x40 800163a: f003 0301 and.w r3, r3, #1 800163e: 60fb str r3, [r7, #12] 8001640: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } } 8001642: bf00 nop 8001644: 3714 adds r7, #20 8001646: 46bd mov sp, r7 8001648: f85d 7b04 ldr.w r7, [sp], #4 800164c: 4770 bx lr 800164e: bf00 nop 8001650: 40023800 .word 0x40023800 08001654 : void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) { 8001654: b580 push {r7, lr} 8001656: b08a sub sp, #40 @ 0x28 8001658: af00 add r7, sp, #0 800165a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800165c: f107 0314 add.w r3, r7, #20 8001660: 2200 movs r2, #0 8001662: 601a str r2, [r3, #0] 8001664: 605a str r2, [r3, #4] 8001666: 609a str r2, [r3, #8] 8001668: 60da str r2, [r3, #12] 800166a: 611a str r2, [r3, #16] if(tim_encoderHandle->Instance==TIM3) 800166c: 687b ldr r3, [r7, #4] 800166e: 681b ldr r3, [r3, #0] 8001670: 4a19 ldr r2, [pc, #100] @ (80016d8 ) 8001672: 4293 cmp r3, r2 8001674: d12b bne.n 80016ce { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 8001676: 2300 movs r3, #0 8001678: 613b str r3, [r7, #16] 800167a: 4b18 ldr r3, [pc, #96] @ (80016dc ) 800167c: 6c1b ldr r3, [r3, #64] @ 0x40 800167e: 4a17 ldr r2, [pc, #92] @ (80016dc ) 8001680: f043 0302 orr.w r3, r3, #2 8001684: 6413 str r3, [r2, #64] @ 0x40 8001686: 4b15 ldr r3, [pc, #84] @ (80016dc ) 8001688: 6c1b ldr r3, [r3, #64] @ 0x40 800168a: f003 0302 and.w r3, r3, #2 800168e: 613b str r3, [r7, #16] 8001690: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001692: 2300 movs r3, #0 8001694: 60fb str r3, [r7, #12] 8001696: 4b11 ldr r3, [pc, #68] @ (80016dc ) 8001698: 6b1b ldr r3, [r3, #48] @ 0x30 800169a: 4a10 ldr r2, [pc, #64] @ (80016dc ) 800169c: f043 0301 orr.w r3, r3, #1 80016a0: 6313 str r3, [r2, #48] @ 0x30 80016a2: 4b0e ldr r3, [pc, #56] @ (80016dc ) 80016a4: 6b1b ldr r3, [r3, #48] @ 0x30 80016a6: f003 0301 and.w r3, r3, #1 80016aa: 60fb str r3, [r7, #12] 80016ac: 68fb ldr r3, [r7, #12] /**TIM3 GPIO Configuration PA6 ------> TIM3_CH1 PA7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 80016ae: 23c0 movs r3, #192 @ 0xc0 80016b0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80016b2: 2302 movs r3, #2 80016b4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80016b6: 2300 movs r3, #0 80016b8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80016ba: 2300 movs r3, #0 80016bc: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 80016be: 2302 movs r3, #2 80016c0: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80016c2: f107 0314 add.w r3, r7, #20 80016c6: 4619 mov r1, r3 80016c8: 4805 ldr r0, [pc, #20] @ (80016e0 ) 80016ca: f001 f981 bl 80029d0 /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 80016ce: bf00 nop 80016d0: 3728 adds r7, #40 @ 0x28 80016d2: 46bd mov sp, r7 80016d4: bd80 pop {r7, pc} 80016d6: bf00 nop 80016d8: 40000400 .word 0x40000400 80016dc: 40023800 .word 0x40023800 80016e0: 40020000 .word 0x40020000 080016e4 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 80016e4: b580 push {r7, lr} 80016e6: b088 sub sp, #32 80016e8: af00 add r7, sp, #0 80016ea: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80016ec: f107 030c add.w r3, r7, #12 80016f0: 2200 movs r2, #0 80016f2: 601a str r2, [r3, #0] 80016f4: 605a str r2, [r3, #4] 80016f6: 609a str r2, [r3, #8] 80016f8: 60da str r2, [r3, #12] 80016fa: 611a str r2, [r3, #16] if(timHandle->Instance==TIM2) 80016fc: 687b ldr r3, [r7, #4] 80016fe: 681b ldr r3, [r3, #0] 8001700: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001704: d11d bne.n 8001742 { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8001706: 2300 movs r3, #0 8001708: 60bb str r3, [r7, #8] 800170a: 4b10 ldr r3, [pc, #64] @ (800174c ) 800170c: 6b1b ldr r3, [r3, #48] @ 0x30 800170e: 4a0f ldr r2, [pc, #60] @ (800174c ) 8001710: f043 0301 orr.w r3, r3, #1 8001714: 6313 str r3, [r2, #48] @ 0x30 8001716: 4b0d ldr r3, [pc, #52] @ (800174c ) 8001718: 6b1b ldr r3, [r3, #48] @ 0x30 800171a: f003 0301 and.w r3, r3, #1 800171e: 60bb str r3, [r7, #8] 8001720: 68bb ldr r3, [r7, #8] /**TIM2 GPIO Configuration PA5 ------> TIM2_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_5; 8001722: 2320 movs r3, #32 8001724: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001726: 2302 movs r3, #2 8001728: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800172a: 2300 movs r3, #0 800172c: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800172e: 2300 movs r3, #0 8001730: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 8001732: 2301 movs r3, #1 8001734: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001736: f107 030c add.w r3, r7, #12 800173a: 4619 mov r1, r3 800173c: 4804 ldr r0, [pc, #16] @ (8001750 ) 800173e: f001 f947 bl 80029d0 /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8001742: bf00 nop 8001744: 3720 adds r7, #32 8001746: 46bd mov sp, r7 8001748: bd80 pop {r7, pc} 800174a: bf00 nop 800174c: 40023800 .word 0x40023800 8001750: 40020000 .word 0x40020000 08001754 : DMA_HandleTypeDef hdma_usart2_rx; DMA_HandleTypeDef hdma_usart2_tx; /* UART4 init function */ void MX_UART4_Init(void) { 8001754: b580 push {r7, lr} 8001756: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; 8001758: 4b11 ldr r3, [pc, #68] @ (80017a0 ) 800175a: 4a12 ldr r2, [pc, #72] @ (80017a4 ) 800175c: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; 800175e: 4b10 ldr r3, [pc, #64] @ (80017a0 ) 8001760: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001764: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; 8001766: 4b0e ldr r3, [pc, #56] @ (80017a0 ) 8001768: 2200 movs r2, #0 800176a: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; 800176c: 4b0c ldr r3, [pc, #48] @ (80017a0 ) 800176e: 2200 movs r2, #0 8001770: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; 8001772: 4b0b ldr r3, [pc, #44] @ (80017a0 ) 8001774: 2200 movs r2, #0 8001776: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; 8001778: 4b09 ldr r3, [pc, #36] @ (80017a0 ) 800177a: 220c movs r2, #12 800177c: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800177e: 4b08 ldr r3, [pc, #32] @ (80017a0 ) 8001780: 2200 movs r2, #0 8001782: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; 8001784: 4b06 ldr r3, [pc, #24] @ (80017a0 ) 8001786: 2200 movs r2, #0 8001788: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart4) != HAL_OK) 800178a: 4805 ldr r0, [pc, #20] @ (80017a0 ) 800178c: f004 fe7c bl 8006488 8001790: 4603 mov r3, r0 8001792: 2b00 cmp r3, #0 8001794: d001 beq.n 800179a { Error_Handler(); 8001796: f7ff fd67 bl 8001268 } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } 800179a: bf00 nop 800179c: bd80 pop {r7, pc} 800179e: bf00 nop 80017a0: 20000a00 .word 0x20000a00 80017a4: 40004c00 .word 0x40004c00 080017a8 : /* UART5 init function */ void MX_UART5_Init(void) { 80017a8: b580 push {r7, lr} 80017aa: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 80017ac: 4b11 ldr r3, [pc, #68] @ (80017f4 ) 80017ae: 4a12 ldr r2, [pc, #72] @ (80017f8 ) 80017b0: 601a str r2, [r3, #0] huart5.Init.BaudRate = 115200; 80017b2: 4b10 ldr r3, [pc, #64] @ (80017f4 ) 80017b4: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80017b8: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 80017ba: 4b0e ldr r3, [pc, #56] @ (80017f4 ) 80017bc: 2200 movs r2, #0 80017be: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 80017c0: 4b0c ldr r3, [pc, #48] @ (80017f4 ) 80017c2: 2200 movs r2, #0 80017c4: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 80017c6: 4b0b ldr r3, [pc, #44] @ (80017f4 ) 80017c8: 2200 movs r2, #0 80017ca: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 80017cc: 4b09 ldr r3, [pc, #36] @ (80017f4 ) 80017ce: 220c movs r2, #12 80017d0: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80017d2: 4b08 ldr r3, [pc, #32] @ (80017f4 ) 80017d4: 2200 movs r2, #0 80017d6: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 80017d8: 4b06 ldr r3, [pc, #24] @ (80017f4 ) 80017da: 2200 movs r2, #0 80017dc: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart5) != HAL_OK) 80017de: 4805 ldr r0, [pc, #20] @ (80017f4 ) 80017e0: f004 fe52 bl 8006488 80017e4: 4603 mov r3, r0 80017e6: 2b00 cmp r3, #0 80017e8: d001 beq.n 80017ee { Error_Handler(); 80017ea: f7ff fd3d bl 8001268 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 80017ee: bf00 nop 80017f0: bd80 pop {r7, pc} 80017f2: bf00 nop 80017f4: 20000a48 .word 0x20000a48 80017f8: 40005000 .word 0x40005000 080017fc : /* USART1 init function */ void MX_USART1_UART_Init(void) { 80017fc: b580 push {r7, lr} 80017fe: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8001800: 4b11 ldr r3, [pc, #68] @ (8001848 ) 8001802: 4a12 ldr r2, [pc, #72] @ (800184c ) 8001804: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8001806: 4b10 ldr r3, [pc, #64] @ (8001848 ) 8001808: f44f 32e1 mov.w r2, #115200 @ 0x1c200 800180c: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800180e: 4b0e ldr r3, [pc, #56] @ (8001848 ) 8001810: 2200 movs r2, #0 8001812: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8001814: 4b0c ldr r3, [pc, #48] @ (8001848 ) 8001816: 2200 movs r2, #0 8001818: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800181a: 4b0b ldr r3, [pc, #44] @ (8001848 ) 800181c: 2200 movs r2, #0 800181e: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001820: 4b09 ldr r3, [pc, #36] @ (8001848 ) 8001822: 220c movs r2, #12 8001824: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001826: 4b08 ldr r3, [pc, #32] @ (8001848 ) 8001828: 2200 movs r2, #0 800182a: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 800182c: 4b06 ldr r3, [pc, #24] @ (8001848 ) 800182e: 2200 movs r2, #0 8001830: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8001832: 4805 ldr r0, [pc, #20] @ (8001848 ) 8001834: f004 fe28 bl 8006488 8001838: 4603 mov r3, r0 800183a: 2b00 cmp r3, #0 800183c: d001 beq.n 8001842 { Error_Handler(); 800183e: f7ff fd13 bl 8001268 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8001842: bf00 nop 8001844: bd80 pop {r7, pc} 8001846: bf00 nop 8001848: 20000a90 .word 0x20000a90 800184c: 40011000 .word 0x40011000 08001850 : /* USART2 init function */ void MX_USART2_UART_Init(void) { 8001850: b580 push {r7, lr} 8001852: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8001854: 4b11 ldr r3, [pc, #68] @ (800189c ) 8001856: 4a12 ldr r2, [pc, #72] @ (80018a0 ) 8001858: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800185a: 4b10 ldr r3, [pc, #64] @ (800189c ) 800185c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001860: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8001862: 4b0e ldr r3, [pc, #56] @ (800189c ) 8001864: 2200 movs r2, #0 8001866: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8001868: 4b0c ldr r3, [pc, #48] @ (800189c ) 800186a: 2200 movs r2, #0 800186c: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800186e: 4b0b ldr r3, [pc, #44] @ (800189c ) 8001870: 2200 movs r2, #0 8001872: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8001874: 4b09 ldr r3, [pc, #36] @ (800189c ) 8001876: 220c movs r2, #12 8001878: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800187a: 4b08 ldr r3, [pc, #32] @ (800189c ) 800187c: 2200 movs r2, #0 800187e: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8001880: 4b06 ldr r3, [pc, #24] @ (800189c ) 8001882: 2200 movs r2, #0 8001884: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 8001886: 4805 ldr r0, [pc, #20] @ (800189c ) 8001888: f004 fdfe bl 8006488 800188c: 4603 mov r3, r0 800188e: 2b00 cmp r3, #0 8001890: d001 beq.n 8001896 { Error_Handler(); 8001892: f7ff fce9 bl 8001268 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8001896: bf00 nop 8001898: bd80 pop {r7, pc} 800189a: bf00 nop 800189c: 20000ad8 .word 0x20000ad8 80018a0: 40004400 .word 0x40004400 080018a4 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 80018a4: b580 push {r7, lr} 80018a6: b090 sub sp, #64 @ 0x40 80018a8: af00 add r7, sp, #0 80018aa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80018ac: f107 032c add.w r3, r7, #44 @ 0x2c 80018b0: 2200 movs r2, #0 80018b2: 601a str r2, [r3, #0] 80018b4: 605a str r2, [r3, #4] 80018b6: 609a str r2, [r3, #8] 80018b8: 60da str r2, [r3, #12] 80018ba: 611a str r2, [r3, #16] if(uartHandle->Instance==UART4) 80018bc: 687b ldr r3, [r7, #4] 80018be: 681b ldr r3, [r3, #0] 80018c0: 4a4a ldr r2, [pc, #296] @ (80019ec ) 80018c2: 4293 cmp r3, r2 80018c4: f040 80a0 bne.w 8001a08 { /* USER CODE BEGIN UART4_MspInit 0 */ /* USER CODE END UART4_MspInit 0 */ /* UART4 clock enable */ __HAL_RCC_UART4_CLK_ENABLE(); 80018c8: 2300 movs r3, #0 80018ca: 62bb str r3, [r7, #40] @ 0x28 80018cc: 4b48 ldr r3, [pc, #288] @ (80019f0 ) 80018ce: 6c1b ldr r3, [r3, #64] @ 0x40 80018d0: 4a47 ldr r2, [pc, #284] @ (80019f0 ) 80018d2: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80018d6: 6413 str r3, [r2, #64] @ 0x40 80018d8: 4b45 ldr r3, [pc, #276] @ (80019f0 ) 80018da: 6c1b ldr r3, [r3, #64] @ 0x40 80018dc: f403 2300 and.w r3, r3, #524288 @ 0x80000 80018e0: 62bb str r3, [r7, #40] @ 0x28 80018e2: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOA_CLK_ENABLE(); 80018e4: 2300 movs r3, #0 80018e6: 627b str r3, [r7, #36] @ 0x24 80018e8: 4b41 ldr r3, [pc, #260] @ (80019f0 ) 80018ea: 6b1b ldr r3, [r3, #48] @ 0x30 80018ec: 4a40 ldr r2, [pc, #256] @ (80019f0 ) 80018ee: f043 0301 orr.w r3, r3, #1 80018f2: 6313 str r3, [r2, #48] @ 0x30 80018f4: 4b3e ldr r3, [pc, #248] @ (80019f0 ) 80018f6: 6b1b ldr r3, [r3, #48] @ 0x30 80018f8: f003 0301 and.w r3, r3, #1 80018fc: 627b str r3, [r7, #36] @ 0x24 80018fe: 6a7b ldr r3, [r7, #36] @ 0x24 /**UART4 GPIO Configuration PA0-WKUP ------> UART4_TX PA1 ------> UART4_RX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8001900: 2303 movs r3, #3 8001902: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001904: 2302 movs r3, #2 8001906: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001908: 2300 movs r3, #0 800190a: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800190c: 2303 movs r3, #3 800190e: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 8001910: 2308 movs r3, #8 8001912: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001914: f107 032c add.w r3, r7, #44 @ 0x2c 8001918: 4619 mov r1, r3 800191a: 4836 ldr r0, [pc, #216] @ (80019f4 ) 800191c: f001 f858 bl 80029d0 /* UART4 DMA Init */ /* UART4_RX Init */ hdma_uart4_rx.Instance = DMA1_Stream2; 8001920: 4b35 ldr r3, [pc, #212] @ (80019f8 ) 8001922: 4a36 ldr r2, [pc, #216] @ (80019fc ) 8001924: 601a str r2, [r3, #0] hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4; 8001926: 4b34 ldr r3, [pc, #208] @ (80019f8 ) 8001928: f04f 6200 mov.w r2, #134217728 @ 0x8000000 800192c: 605a str r2, [r3, #4] hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800192e: 4b32 ldr r3, [pc, #200] @ (80019f8 ) 8001930: 2200 movs r2, #0 8001932: 609a str r2, [r3, #8] hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001934: 4b30 ldr r3, [pc, #192] @ (80019f8 ) 8001936: 2200 movs r2, #0 8001938: 60da str r2, [r3, #12] hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE; 800193a: 4b2f ldr r3, [pc, #188] @ (80019f8 ) 800193c: f44f 6280 mov.w r2, #1024 @ 0x400 8001940: 611a str r2, [r3, #16] hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001942: 4b2d ldr r3, [pc, #180] @ (80019f8 ) 8001944: 2200 movs r2, #0 8001946: 615a str r2, [r3, #20] hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001948: 4b2b ldr r3, [pc, #172] @ (80019f8 ) 800194a: 2200 movs r2, #0 800194c: 619a str r2, [r3, #24] hdma_uart4_rx.Init.Mode = DMA_NORMAL; 800194e: 4b2a ldr r3, [pc, #168] @ (80019f8 ) 8001950: 2200 movs r2, #0 8001952: 61da str r2, [r3, #28] hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW; 8001954: 4b28 ldr r3, [pc, #160] @ (80019f8 ) 8001956: 2200 movs r2, #0 8001958: 621a str r2, [r3, #32] hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800195a: 4b27 ldr r3, [pc, #156] @ (80019f8 ) 800195c: 2200 movs r2, #0 800195e: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK) 8001960: 4825 ldr r0, [pc, #148] @ (80019f8 ) 8001962: f000 fc33 bl 80021cc 8001966: 4603 mov r3, r0 8001968: 2b00 cmp r3, #0 800196a: d001 beq.n 8001970 { Error_Handler(); 800196c: f7ff fc7c bl 8001268 } __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx); 8001970: 687b ldr r3, [r7, #4] 8001972: 4a21 ldr r2, [pc, #132] @ (80019f8 ) 8001974: 63da str r2, [r3, #60] @ 0x3c 8001976: 4a20 ldr r2, [pc, #128] @ (80019f8 ) 8001978: 687b ldr r3, [r7, #4] 800197a: 6393 str r3, [r2, #56] @ 0x38 /* UART4_TX Init */ hdma_uart4_tx.Instance = DMA1_Stream4; 800197c: 4b20 ldr r3, [pc, #128] @ (8001a00 ) 800197e: 4a21 ldr r2, [pc, #132] @ (8001a04 ) 8001980: 601a str r2, [r3, #0] hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4; 8001982: 4b1f ldr r3, [pc, #124] @ (8001a00 ) 8001984: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001988: 605a str r2, [r3, #4] hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800198a: 4b1d ldr r3, [pc, #116] @ (8001a00 ) 800198c: 2240 movs r2, #64 @ 0x40 800198e: 609a str r2, [r3, #8] hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001990: 4b1b ldr r3, [pc, #108] @ (8001a00 ) 8001992: 2200 movs r2, #0 8001994: 60da str r2, [r3, #12] hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE; 8001996: 4b1a ldr r3, [pc, #104] @ (8001a00 ) 8001998: f44f 6280 mov.w r2, #1024 @ 0x400 800199c: 611a str r2, [r3, #16] hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800199e: 4b18 ldr r3, [pc, #96] @ (8001a00 ) 80019a0: 2200 movs r2, #0 80019a2: 615a str r2, [r3, #20] hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80019a4: 4b16 ldr r3, [pc, #88] @ (8001a00 ) 80019a6: 2200 movs r2, #0 80019a8: 619a str r2, [r3, #24] hdma_uart4_tx.Init.Mode = DMA_NORMAL; 80019aa: 4b15 ldr r3, [pc, #84] @ (8001a00 ) 80019ac: 2200 movs r2, #0 80019ae: 61da str r2, [r3, #28] hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW; 80019b0: 4b13 ldr r3, [pc, #76] @ (8001a00 ) 80019b2: 2200 movs r2, #0 80019b4: 621a str r2, [r3, #32] hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80019b6: 4b12 ldr r3, [pc, #72] @ (8001a00 ) 80019b8: 2200 movs r2, #0 80019ba: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK) 80019bc: 4810 ldr r0, [pc, #64] @ (8001a00 ) 80019be: f000 fc05 bl 80021cc 80019c2: 4603 mov r3, r0 80019c4: 2b00 cmp r3, #0 80019c6: d001 beq.n 80019cc { Error_Handler(); 80019c8: f7ff fc4e bl 8001268 } __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); 80019cc: 687b ldr r3, [r7, #4] 80019ce: 4a0c ldr r2, [pc, #48] @ (8001a00 ) 80019d0: 639a str r2, [r3, #56] @ 0x38 80019d2: 4a0b ldr r2, [pc, #44] @ (8001a00 ) 80019d4: 687b ldr r3, [r7, #4] 80019d6: 6393 str r3, [r2, #56] @ 0x38 /* UART4 interrupt Init */ HAL_NVIC_SetPriority(UART4_IRQn, 5, 0); 80019d8: 2200 movs r2, #0 80019da: 2105 movs r1, #5 80019dc: 2034 movs r0, #52 @ 0x34 80019de: f000 fbbe bl 800215e HAL_NVIC_EnableIRQ(UART4_IRQn); 80019e2: 2034 movs r0, #52 @ 0x34 80019e4: f000 fbd7 bl 8002196 HAL_NVIC_EnableIRQ(USART2_IRQn); /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 80019e8: e202 b.n 8001df0 80019ea: bf00 nop 80019ec: 40004c00 .word 0x40004c00 80019f0: 40023800 .word 0x40023800 80019f4: 40020000 .word 0x40020000 80019f8: 20000b20 .word 0x20000b20 80019fc: 40026040 .word 0x40026040 8001a00: 20000b80 .word 0x20000b80 8001a04: 40026070 .word 0x40026070 else if(uartHandle->Instance==UART5) 8001a08: 687b ldr r3, [r7, #4] 8001a0a: 681b ldr r3, [r3, #0] 8001a0c: 4a59 ldr r2, [pc, #356] @ (8001b74 ) 8001a0e: 4293 cmp r3, r2 8001a10: f040 80c0 bne.w 8001b94 __HAL_RCC_UART5_CLK_ENABLE(); 8001a14: 2300 movs r3, #0 8001a16: 623b str r3, [r7, #32] 8001a18: 4b57 ldr r3, [pc, #348] @ (8001b78 ) 8001a1a: 6c1b ldr r3, [r3, #64] @ 0x40 8001a1c: 4a56 ldr r2, [pc, #344] @ (8001b78 ) 8001a1e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8001a22: 6413 str r3, [r2, #64] @ 0x40 8001a24: 4b54 ldr r3, [pc, #336] @ (8001b78 ) 8001a26: 6c1b ldr r3, [r3, #64] @ 0x40 8001a28: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8001a2c: 623b str r3, [r7, #32] 8001a2e: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001a30: 2300 movs r3, #0 8001a32: 61fb str r3, [r7, #28] 8001a34: 4b50 ldr r3, [pc, #320] @ (8001b78 ) 8001a36: 6b1b ldr r3, [r3, #48] @ 0x30 8001a38: 4a4f ldr r2, [pc, #316] @ (8001b78 ) 8001a3a: f043 0304 orr.w r3, r3, #4 8001a3e: 6313 str r3, [r2, #48] @ 0x30 8001a40: 4b4d ldr r3, [pc, #308] @ (8001b78 ) 8001a42: 6b1b ldr r3, [r3, #48] @ 0x30 8001a44: f003 0304 and.w r3, r3, #4 8001a48: 61fb str r3, [r7, #28] 8001a4a: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001a4c: 2300 movs r3, #0 8001a4e: 61bb str r3, [r7, #24] 8001a50: 4b49 ldr r3, [pc, #292] @ (8001b78 ) 8001a52: 6b1b ldr r3, [r3, #48] @ 0x30 8001a54: 4a48 ldr r2, [pc, #288] @ (8001b78 ) 8001a56: f043 0308 orr.w r3, r3, #8 8001a5a: 6313 str r3, [r2, #48] @ 0x30 8001a5c: 4b46 ldr r3, [pc, #280] @ (8001b78 ) 8001a5e: 6b1b ldr r3, [r3, #48] @ 0x30 8001a60: f003 0308 and.w r3, r3, #8 8001a64: 61bb str r3, [r7, #24] 8001a66: 69bb ldr r3, [r7, #24] GPIO_InitStruct.Pin = GPIO_PIN_12; 8001a68: f44f 5380 mov.w r3, #4096 @ 0x1000 8001a6c: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001a6e: 2302 movs r3, #2 8001a70: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001a72: 2300 movs r3, #0 8001a74: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001a76: 2303 movs r3, #3 8001a78: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 8001a7a: 2308 movs r3, #8 8001a7c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8001a7e: f107 032c add.w r3, r7, #44 @ 0x2c 8001a82: 4619 mov r1, r3 8001a84: 483d ldr r0, [pc, #244] @ (8001b7c ) 8001a86: f000 ffa3 bl 80029d0 GPIO_InitStruct.Pin = GPIO_PIN_2; 8001a8a: 2304 movs r3, #4 8001a8c: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001a8e: 2302 movs r3, #2 8001a90: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001a92: 2300 movs r3, #0 8001a94: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001a96: 2303 movs r3, #3 8001a98: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF8_UART5; 8001a9a: 2308 movs r3, #8 8001a9c: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001a9e: f107 032c add.w r3, r7, #44 @ 0x2c 8001aa2: 4619 mov r1, r3 8001aa4: 4836 ldr r0, [pc, #216] @ (8001b80 ) 8001aa6: f000 ff93 bl 80029d0 hdma_uart5_rx.Instance = DMA1_Stream0; 8001aaa: 4b36 ldr r3, [pc, #216] @ (8001b84 ) 8001aac: 4a36 ldr r2, [pc, #216] @ (8001b88 ) 8001aae: 601a str r2, [r3, #0] hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4; 8001ab0: 4b34 ldr r3, [pc, #208] @ (8001b84 ) 8001ab2: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001ab6: 605a str r2, [r3, #4] hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001ab8: 4b32 ldr r3, [pc, #200] @ (8001b84 ) 8001aba: 2200 movs r2, #0 8001abc: 609a str r2, [r3, #8] hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001abe: 4b31 ldr r3, [pc, #196] @ (8001b84 ) 8001ac0: 2200 movs r2, #0 8001ac2: 60da str r2, [r3, #12] hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE; 8001ac4: 4b2f ldr r3, [pc, #188] @ (8001b84 ) 8001ac6: f44f 6280 mov.w r2, #1024 @ 0x400 8001aca: 611a str r2, [r3, #16] hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001acc: 4b2d ldr r3, [pc, #180] @ (8001b84 ) 8001ace: 2200 movs r2, #0 8001ad0: 615a str r2, [r3, #20] hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001ad2: 4b2c ldr r3, [pc, #176] @ (8001b84 ) 8001ad4: 2200 movs r2, #0 8001ad6: 619a str r2, [r3, #24] hdma_uart5_rx.Init.Mode = DMA_NORMAL; 8001ad8: 4b2a ldr r3, [pc, #168] @ (8001b84 ) 8001ada: 2200 movs r2, #0 8001adc: 61da str r2, [r3, #28] hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; 8001ade: 4b29 ldr r3, [pc, #164] @ (8001b84 ) 8001ae0: 2200 movs r2, #0 8001ae2: 621a str r2, [r3, #32] hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001ae4: 4b27 ldr r3, [pc, #156] @ (8001b84 ) 8001ae6: 2200 movs r2, #0 8001ae8: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) 8001aea: 4826 ldr r0, [pc, #152] @ (8001b84 ) 8001aec: f000 fb6e bl 80021cc 8001af0: 4603 mov r3, r0 8001af2: 2b00 cmp r3, #0 8001af4: d001 beq.n 8001afa Error_Handler(); 8001af6: f7ff fbb7 bl 8001268 __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx); 8001afa: 687b ldr r3, [r7, #4] 8001afc: 4a21 ldr r2, [pc, #132] @ (8001b84 ) 8001afe: 63da str r2, [r3, #60] @ 0x3c 8001b00: 4a20 ldr r2, [pc, #128] @ (8001b84 ) 8001b02: 687b ldr r3, [r7, #4] 8001b04: 6393 str r3, [r2, #56] @ 0x38 hdma_uart5_tx.Instance = DMA1_Stream7; 8001b06: 4b21 ldr r3, [pc, #132] @ (8001b8c ) 8001b08: 4a21 ldr r2, [pc, #132] @ (8001b90 ) 8001b0a: 601a str r2, [r3, #0] hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4; 8001b0c: 4b1f ldr r3, [pc, #124] @ (8001b8c ) 8001b0e: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001b12: 605a str r2, [r3, #4] hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001b14: 4b1d ldr r3, [pc, #116] @ (8001b8c ) 8001b16: 2240 movs r2, #64 @ 0x40 8001b18: 609a str r2, [r3, #8] hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001b1a: 4b1c ldr r3, [pc, #112] @ (8001b8c ) 8001b1c: 2200 movs r2, #0 8001b1e: 60da str r2, [r3, #12] hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE; 8001b20: 4b1a ldr r3, [pc, #104] @ (8001b8c ) 8001b22: f44f 6280 mov.w r2, #1024 @ 0x400 8001b26: 611a str r2, [r3, #16] hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001b28: 4b18 ldr r3, [pc, #96] @ (8001b8c ) 8001b2a: 2200 movs r2, #0 8001b2c: 615a str r2, [r3, #20] hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001b2e: 4b17 ldr r3, [pc, #92] @ (8001b8c ) 8001b30: 2200 movs r2, #0 8001b32: 619a str r2, [r3, #24] hdma_uart5_tx.Init.Mode = DMA_NORMAL; 8001b34: 4b15 ldr r3, [pc, #84] @ (8001b8c ) 8001b36: 2200 movs r2, #0 8001b38: 61da str r2, [r3, #28] hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; 8001b3a: 4b14 ldr r3, [pc, #80] @ (8001b8c ) 8001b3c: 2200 movs r2, #0 8001b3e: 621a str r2, [r3, #32] hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001b40: 4b12 ldr r3, [pc, #72] @ (8001b8c ) 8001b42: 2200 movs r2, #0 8001b44: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) 8001b46: 4811 ldr r0, [pc, #68] @ (8001b8c ) 8001b48: f000 fb40 bl 80021cc 8001b4c: 4603 mov r3, r0 8001b4e: 2b00 cmp r3, #0 8001b50: d001 beq.n 8001b56 Error_Handler(); 8001b52: f7ff fb89 bl 8001268 __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); 8001b56: 687b ldr r3, [r7, #4] 8001b58: 4a0c ldr r2, [pc, #48] @ (8001b8c ) 8001b5a: 639a str r2, [r3, #56] @ 0x38 8001b5c: 4a0b ldr r2, [pc, #44] @ (8001b8c ) 8001b5e: 687b ldr r3, [r7, #4] 8001b60: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); 8001b62: 2200 movs r2, #0 8001b64: 2105 movs r1, #5 8001b66: 2035 movs r0, #53 @ 0x35 8001b68: f000 faf9 bl 800215e HAL_NVIC_EnableIRQ(UART5_IRQn); 8001b6c: 2035 movs r0, #53 @ 0x35 8001b6e: f000 fb12 bl 8002196 } 8001b72: e13d b.n 8001df0 8001b74: 40005000 .word 0x40005000 8001b78: 40023800 .word 0x40023800 8001b7c: 40020800 .word 0x40020800 8001b80: 40020c00 .word 0x40020c00 8001b84: 20000be0 .word 0x20000be0 8001b88: 40026010 .word 0x40026010 8001b8c: 20000c40 .word 0x20000c40 8001b90: 400260b8 .word 0x400260b8 else if(uartHandle->Instance==USART1) 8001b94: 687b ldr r3, [r7, #4] 8001b96: 681b ldr r3, [r3, #0] 8001b98: 4a97 ldr r2, [pc, #604] @ (8001df8 ) 8001b9a: 4293 cmp r3, r2 8001b9c: f040 8092 bne.w 8001cc4 __HAL_RCC_USART1_CLK_ENABLE(); 8001ba0: 2300 movs r3, #0 8001ba2: 617b str r3, [r7, #20] 8001ba4: 4b95 ldr r3, [pc, #596] @ (8001dfc ) 8001ba6: 6c5b ldr r3, [r3, #68] @ 0x44 8001ba8: 4a94 ldr r2, [pc, #592] @ (8001dfc ) 8001baa: f043 0310 orr.w r3, r3, #16 8001bae: 6453 str r3, [r2, #68] @ 0x44 8001bb0: 4b92 ldr r3, [pc, #584] @ (8001dfc ) 8001bb2: 6c5b ldr r3, [r3, #68] @ 0x44 8001bb4: f003 0310 and.w r3, r3, #16 8001bb8: 617b str r3, [r7, #20] 8001bba: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001bbc: 2300 movs r3, #0 8001bbe: 613b str r3, [r7, #16] 8001bc0: 4b8e ldr r3, [pc, #568] @ (8001dfc ) 8001bc2: 6b1b ldr r3, [r3, #48] @ 0x30 8001bc4: 4a8d ldr r2, [pc, #564] @ (8001dfc ) 8001bc6: f043 0301 orr.w r3, r3, #1 8001bca: 6313 str r3, [r2, #48] @ 0x30 8001bcc: 4b8b ldr r3, [pc, #556] @ (8001dfc ) 8001bce: 6b1b ldr r3, [r3, #48] @ 0x30 8001bd0: f003 0301 and.w r3, r3, #1 8001bd4: 613b str r3, [r7, #16] 8001bd6: 693b ldr r3, [r7, #16] GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 8001bd8: f44f 63c0 mov.w r3, #1536 @ 0x600 8001bdc: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001bde: 2302 movs r3, #2 8001be0: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001be2: 2300 movs r3, #0 8001be4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001be6: 2303 movs r3, #3 8001be8: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 8001bea: 2307 movs r3, #7 8001bec: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001bee: f107 032c add.w r3, r7, #44 @ 0x2c 8001bf2: 4619 mov r1, r3 8001bf4: 4882 ldr r0, [pc, #520] @ (8001e00 ) 8001bf6: f000 feeb bl 80029d0 hdma_usart1_rx.Instance = DMA2_Stream2; 8001bfa: 4b82 ldr r3, [pc, #520] @ (8001e04 ) 8001bfc: 4a82 ldr r2, [pc, #520] @ (8001e08 ) 8001bfe: 601a str r2, [r3, #0] hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; 8001c00: 4b80 ldr r3, [pc, #512] @ (8001e04 ) 8001c02: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001c06: 605a str r2, [r3, #4] hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001c08: 4b7e ldr r3, [pc, #504] @ (8001e04 ) 8001c0a: 2200 movs r2, #0 8001c0c: 609a str r2, [r3, #8] hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001c0e: 4b7d ldr r3, [pc, #500] @ (8001e04 ) 8001c10: 2200 movs r2, #0 8001c12: 60da str r2, [r3, #12] hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 8001c14: 4b7b ldr r3, [pc, #492] @ (8001e04 ) 8001c16: f44f 6280 mov.w r2, #1024 @ 0x400 8001c1a: 611a str r2, [r3, #16] hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001c1c: 4b79 ldr r3, [pc, #484] @ (8001e04 ) 8001c1e: 2200 movs r2, #0 8001c20: 615a str r2, [r3, #20] hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001c22: 4b78 ldr r3, [pc, #480] @ (8001e04 ) 8001c24: 2200 movs r2, #0 8001c26: 619a str r2, [r3, #24] hdma_usart1_rx.Init.Mode = DMA_NORMAL; 8001c28: 4b76 ldr r3, [pc, #472] @ (8001e04 ) 8001c2a: 2200 movs r2, #0 8001c2c: 61da str r2, [r3, #28] hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; 8001c2e: 4b75 ldr r3, [pc, #468] @ (8001e04 ) 8001c30: 2200 movs r2, #0 8001c32: 621a str r2, [r3, #32] hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001c34: 4b73 ldr r3, [pc, #460] @ (8001e04 ) 8001c36: 2200 movs r2, #0 8001c38: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 8001c3a: 4872 ldr r0, [pc, #456] @ (8001e04 ) 8001c3c: f000 fac6 bl 80021cc 8001c40: 4603 mov r3, r0 8001c42: 2b00 cmp r3, #0 8001c44: d001 beq.n 8001c4a Error_Handler(); 8001c46: f7ff fb0f bl 8001268 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx); 8001c4a: 687b ldr r3, [r7, #4] 8001c4c: 4a6d ldr r2, [pc, #436] @ (8001e04 ) 8001c4e: 63da str r2, [r3, #60] @ 0x3c 8001c50: 4a6c ldr r2, [pc, #432] @ (8001e04 ) 8001c52: 687b ldr r3, [r7, #4] 8001c54: 6393 str r3, [r2, #56] @ 0x38 hdma_usart1_tx.Instance = DMA2_Stream7; 8001c56: 4b6d ldr r3, [pc, #436] @ (8001e0c ) 8001c58: 4a6d ldr r2, [pc, #436] @ (8001e10 ) 8001c5a: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; 8001c5c: 4b6b ldr r3, [pc, #428] @ (8001e0c ) 8001c5e: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001c62: 605a str r2, [r3, #4] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001c64: 4b69 ldr r3, [pc, #420] @ (8001e0c ) 8001c66: 2240 movs r2, #64 @ 0x40 8001c68: 609a str r2, [r3, #8] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001c6a: 4b68 ldr r3, [pc, #416] @ (8001e0c ) 8001c6c: 2200 movs r2, #0 8001c6e: 60da str r2, [r3, #12] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 8001c70: 4b66 ldr r3, [pc, #408] @ (8001e0c ) 8001c72: f44f 6280 mov.w r2, #1024 @ 0x400 8001c76: 611a str r2, [r3, #16] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001c78: 4b64 ldr r3, [pc, #400] @ (8001e0c ) 8001c7a: 2200 movs r2, #0 8001c7c: 615a str r2, [r3, #20] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001c7e: 4b63 ldr r3, [pc, #396] @ (8001e0c ) 8001c80: 2200 movs r2, #0 8001c82: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 8001c84: 4b61 ldr r3, [pc, #388] @ (8001e0c ) 8001c86: 2200 movs r2, #0 8001c88: 61da str r2, [r3, #28] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 8001c8a: 4b60 ldr r3, [pc, #384] @ (8001e0c ) 8001c8c: 2200 movs r2, #0 8001c8e: 621a str r2, [r3, #32] hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001c90: 4b5e ldr r3, [pc, #376] @ (8001e0c ) 8001c92: 2200 movs r2, #0 8001c94: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 8001c96: 485d ldr r0, [pc, #372] @ (8001e0c ) 8001c98: f000 fa98 bl 80021cc 8001c9c: 4603 mov r3, r0 8001c9e: 2b00 cmp r3, #0 8001ca0: d001 beq.n 8001ca6 Error_Handler(); 8001ca2: f7ff fae1 bl 8001268 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); 8001ca6: 687b ldr r3, [r7, #4] 8001ca8: 4a58 ldr r2, [pc, #352] @ (8001e0c ) 8001caa: 639a str r2, [r3, #56] @ 0x38 8001cac: 4a57 ldr r2, [pc, #348] @ (8001e0c ) 8001cae: 687b ldr r3, [r7, #4] 8001cb0: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 8001cb2: 2200 movs r2, #0 8001cb4: 2105 movs r1, #5 8001cb6: 2025 movs r0, #37 @ 0x25 8001cb8: f000 fa51 bl 800215e HAL_NVIC_EnableIRQ(USART1_IRQn); 8001cbc: 2025 movs r0, #37 @ 0x25 8001cbe: f000 fa6a bl 8002196 } 8001cc2: e095 b.n 8001df0 else if(uartHandle->Instance==USART2) 8001cc4: 687b ldr r3, [r7, #4] 8001cc6: 681b ldr r3, [r3, #0] 8001cc8: 4a52 ldr r2, [pc, #328] @ (8001e14 ) 8001cca: 4293 cmp r3, r2 8001ccc: f040 8090 bne.w 8001df0 __HAL_RCC_USART2_CLK_ENABLE(); 8001cd0: 2300 movs r3, #0 8001cd2: 60fb str r3, [r7, #12] 8001cd4: 4b49 ldr r3, [pc, #292] @ (8001dfc ) 8001cd6: 6c1b ldr r3, [r3, #64] @ 0x40 8001cd8: 4a48 ldr r2, [pc, #288] @ (8001dfc ) 8001cda: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001cde: 6413 str r3, [r2, #64] @ 0x40 8001ce0: 4b46 ldr r3, [pc, #280] @ (8001dfc ) 8001ce2: 6c1b ldr r3, [r3, #64] @ 0x40 8001ce4: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001ce8: 60fb str r3, [r7, #12] 8001cea: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001cec: 2300 movs r3, #0 8001cee: 60bb str r3, [r7, #8] 8001cf0: 4b42 ldr r3, [pc, #264] @ (8001dfc ) 8001cf2: 6b1b ldr r3, [r3, #48] @ 0x30 8001cf4: 4a41 ldr r2, [pc, #260] @ (8001dfc ) 8001cf6: f043 0301 orr.w r3, r3, #1 8001cfa: 6313 str r3, [r2, #48] @ 0x30 8001cfc: 4b3f ldr r3, [pc, #252] @ (8001dfc ) 8001cfe: 6b1b ldr r3, [r3, #48] @ 0x30 8001d00: f003 0301 and.w r3, r3, #1 8001d04: 60bb str r3, [r7, #8] 8001d06: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; 8001d08: 230c movs r3, #12 8001d0a: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001d0c: 2302 movs r3, #2 8001d0e: 633b str r3, [r7, #48] @ 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001d10: 2300 movs r3, #0 8001d12: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001d14: 2303 movs r3, #3 8001d16: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 8001d18: 2307 movs r3, #7 8001d1a: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001d1c: f107 032c add.w r3, r7, #44 @ 0x2c 8001d20: 4619 mov r1, r3 8001d22: 4837 ldr r0, [pc, #220] @ (8001e00 ) 8001d24: f000 fe54 bl 80029d0 hdma_usart2_rx.Instance = DMA1_Stream5; 8001d28: 4b3b ldr r3, [pc, #236] @ (8001e18 ) 8001d2a: 4a3c ldr r2, [pc, #240] @ (8001e1c ) 8001d2c: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; 8001d2e: 4b3a ldr r3, [pc, #232] @ (8001e18 ) 8001d30: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001d34: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001d36: 4b38 ldr r3, [pc, #224] @ (8001e18 ) 8001d38: 2200 movs r2, #0 8001d3a: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001d3c: 4b36 ldr r3, [pc, #216] @ (8001e18 ) 8001d3e: 2200 movs r2, #0 8001d40: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 8001d42: 4b35 ldr r3, [pc, #212] @ (8001e18 ) 8001d44: f44f 6280 mov.w r2, #1024 @ 0x400 8001d48: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001d4a: 4b33 ldr r3, [pc, #204] @ (8001e18 ) 8001d4c: 2200 movs r2, #0 8001d4e: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001d50: 4b31 ldr r3, [pc, #196] @ (8001e18 ) 8001d52: 2200 movs r2, #0 8001d54: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 8001d56: 4b30 ldr r3, [pc, #192] @ (8001e18 ) 8001d58: 2200 movs r2, #0 8001d5a: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; 8001d5c: 4b2e ldr r3, [pc, #184] @ (8001e18 ) 8001d5e: 2200 movs r2, #0 8001d60: 621a str r2, [r3, #32] hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001d62: 4b2d ldr r3, [pc, #180] @ (8001e18 ) 8001d64: 2200 movs r2, #0 8001d66: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 8001d68: 482b ldr r0, [pc, #172] @ (8001e18 ) 8001d6a: f000 fa2f bl 80021cc 8001d6e: 4603 mov r3, r0 8001d70: 2b00 cmp r3, #0 8001d72: d001 beq.n 8001d78 Error_Handler(); 8001d74: f7ff fa78 bl 8001268 __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); 8001d78: 687b ldr r3, [r7, #4] 8001d7a: 4a27 ldr r2, [pc, #156] @ (8001e18 ) 8001d7c: 63da str r2, [r3, #60] @ 0x3c 8001d7e: 4a26 ldr r2, [pc, #152] @ (8001e18 ) 8001d80: 687b ldr r3, [r7, #4] 8001d82: 6393 str r3, [r2, #56] @ 0x38 hdma_usart2_tx.Instance = DMA1_Stream6; 8001d84: 4b26 ldr r3, [pc, #152] @ (8001e20 ) 8001d86: 4a27 ldr r2, [pc, #156] @ (8001e24 ) 8001d88: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; 8001d8a: 4b25 ldr r3, [pc, #148] @ (8001e20 ) 8001d8c: f04f 6200 mov.w r2, #134217728 @ 0x8000000 8001d90: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001d92: 4b23 ldr r3, [pc, #140] @ (8001e20 ) 8001d94: 2240 movs r2, #64 @ 0x40 8001d96: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001d98: 4b21 ldr r3, [pc, #132] @ (8001e20 ) 8001d9a: 2200 movs r2, #0 8001d9c: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 8001d9e: 4b20 ldr r3, [pc, #128] @ (8001e20 ) 8001da0: f44f 6280 mov.w r2, #1024 @ 0x400 8001da4: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001da6: 4b1e ldr r3, [pc, #120] @ (8001e20 ) 8001da8: 2200 movs r2, #0 8001daa: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001dac: 4b1c ldr r3, [pc, #112] @ (8001e20 ) 8001dae: 2200 movs r2, #0 8001db0: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 8001db2: 4b1b ldr r3, [pc, #108] @ (8001e20 ) 8001db4: 2200 movs r2, #0 8001db6: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; 8001db8: 4b19 ldr r3, [pc, #100] @ (8001e20 ) 8001dba: 2200 movs r2, #0 8001dbc: 621a str r2, [r3, #32] hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001dbe: 4b18 ldr r3, [pc, #96] @ (8001e20 ) 8001dc0: 2200 movs r2, #0 8001dc2: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 8001dc4: 4816 ldr r0, [pc, #88] @ (8001e20 ) 8001dc6: f000 fa01 bl 80021cc 8001dca: 4603 mov r3, r0 8001dcc: 2b00 cmp r3, #0 8001dce: d001 beq.n 8001dd4 Error_Handler(); 8001dd0: f7ff fa4a bl 8001268 __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); 8001dd4: 687b ldr r3, [r7, #4] 8001dd6: 4a12 ldr r2, [pc, #72] @ (8001e20 ) 8001dd8: 639a str r2, [r3, #56] @ 0x38 8001dda: 4a11 ldr r2, [pc, #68] @ (8001e20 ) 8001ddc: 687b ldr r3, [r7, #4] 8001dde: 6393 str r3, [r2, #56] @ 0x38 HAL_NVIC_SetPriority(USART2_IRQn, 5, 0); 8001de0: 2200 movs r2, #0 8001de2: 2105 movs r1, #5 8001de4: 2026 movs r0, #38 @ 0x26 8001de6: f000 f9ba bl 800215e HAL_NVIC_EnableIRQ(USART2_IRQn); 8001dea: 2026 movs r0, #38 @ 0x26 8001dec: f000 f9d3 bl 8002196 } 8001df0: bf00 nop 8001df2: 3740 adds r7, #64 @ 0x40 8001df4: 46bd mov sp, r7 8001df6: bd80 pop {r7, pc} 8001df8: 40011000 .word 0x40011000 8001dfc: 40023800 .word 0x40023800 8001e00: 40020000 .word 0x40020000 8001e04: 20000ca0 .word 0x20000ca0 8001e08: 40026440 .word 0x40026440 8001e0c: 20000d00 .word 0x20000d00 8001e10: 400264b8 .word 0x400264b8 8001e14: 40004400 .word 0x40004400 8001e18: 20000d60 .word 0x20000d60 8001e1c: 40026088 .word 0x40026088 8001e20: 20000dc0 .word 0x20000dc0 8001e24: 400260a0 .word 0x400260a0 08001e28 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001e28: f8df d034 ldr.w sp, [pc, #52] @ 8001e60 /* Call the clock system initialization function.*/ bl SystemInit 8001e2c: f7ff fb34 bl 8001498 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001e30: 480c ldr r0, [pc, #48] @ (8001e64 ) ldr r1, =_edata 8001e32: 490d ldr r1, [pc, #52] @ (8001e68 ) ldr r2, =_sidata 8001e34: 4a0d ldr r2, [pc, #52] @ (8001e6c ) movs r3, #0 8001e36: 2300 movs r3, #0 b LoopCopyDataInit 8001e38: e002 b.n 8001e40 08001e3a : CopyDataInit: ldr r4, [r2, r3] 8001e3a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001e3c: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001e3e: 3304 adds r3, #4 08001e40 : LoopCopyDataInit: adds r4, r0, r3 8001e40: 18c4 adds r4, r0, r3 cmp r4, r1 8001e42: 428c cmp r4, r1 bcc CopyDataInit 8001e44: d3f9 bcc.n 8001e3a /* Zero fill the bss segment. */ ldr r2, =_sbss 8001e46: 4a0a ldr r2, [pc, #40] @ (8001e70 ) ldr r4, =_ebss 8001e48: 4c0a ldr r4, [pc, #40] @ (8001e74 ) movs r3, #0 8001e4a: 2300 movs r3, #0 b LoopFillZerobss 8001e4c: e001 b.n 8001e52 08001e4e : FillZerobss: str r3, [r2] 8001e4e: 6013 str r3, [r2, #0] adds r2, r2, #4 8001e50: 3204 adds r2, #4 08001e52 : LoopFillZerobss: cmp r2, r4 8001e52: 42a2 cmp r2, r4 bcc FillZerobss 8001e54: d3fb bcc.n 8001e4e /* Call static constructors */ bl __libc_init_array 8001e56: f009 fa93 bl 800b380 <__libc_init_array> /* Call the application's entry point.*/ bl main 8001e5a: f7fe fd75 bl 8000948
bx lr 8001e5e: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001e60: 20020000 .word 0x20020000 ldr r0, =_sdata 8001e64: 20000000 .word 0x20000000 ldr r1, =_edata 8001e68: 20000214 .word 0x20000214 ldr r2, =_sidata 8001e6c: 0800b468 .word 0x0800b468 ldr r2, =_sbss 8001e70: 20000214 .word 0x20000214 ldr r4, =_ebss 8001e74: 200017fc .word 0x200017fc 08001e78 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001e78: e7fe b.n 8001e78 ... 08001e7c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001e7c: b580 push {r7, lr} 8001e7e: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 8001e80: 4b0e ldr r3, [pc, #56] @ (8001ebc ) 8001e82: 681b ldr r3, [r3, #0] 8001e84: 4a0d ldr r2, [pc, #52] @ (8001ebc ) 8001e86: f443 7300 orr.w r3, r3, #512 @ 0x200 8001e8a: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 8001e8c: 4b0b ldr r3, [pc, #44] @ (8001ebc ) 8001e8e: 681b ldr r3, [r3, #0] 8001e90: 4a0a ldr r2, [pc, #40] @ (8001ebc ) 8001e92: f443 6380 orr.w r3, r3, #1024 @ 0x400 8001e96: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001e98: 4b08 ldr r3, [pc, #32] @ (8001ebc ) 8001e9a: 681b ldr r3, [r3, #0] 8001e9c: 4a07 ldr r2, [pc, #28] @ (8001ebc ) 8001e9e: f443 7380 orr.w r3, r3, #256 @ 0x100 8001ea2: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001ea4: 2003 movs r0, #3 8001ea6: f000 f94f bl 8002148 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8001eaa: 200f movs r0, #15 8001eac: f000 f808 bl 8001ec0 /* Init the low level hardware */ HAL_MspInit(); 8001eb0: f7ff fa18 bl 80012e4 /* Return function status */ return HAL_OK; 8001eb4: 2300 movs r3, #0 } 8001eb6: 4618 mov r0, r3 8001eb8: bd80 pop {r7, pc} 8001eba: bf00 nop 8001ebc: 40023c00 .word 0x40023c00 08001ec0 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001ec0: b580 push {r7, lr} 8001ec2: b082 sub sp, #8 8001ec4: af00 add r7, sp, #0 8001ec6: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8001ec8: 4b12 ldr r3, [pc, #72] @ (8001f14 ) 8001eca: 681a ldr r2, [r3, #0] 8001ecc: 4b12 ldr r3, [pc, #72] @ (8001f18 ) 8001ece: 781b ldrb r3, [r3, #0] 8001ed0: 4619 mov r1, r3 8001ed2: f44f 737a mov.w r3, #1000 @ 0x3e8 8001ed6: fbb3 f3f1 udiv r3, r3, r1 8001eda: fbb2 f3f3 udiv r3, r2, r3 8001ede: 4618 mov r0, r3 8001ee0: f000 f967 bl 80021b2 8001ee4: 4603 mov r3, r0 8001ee6: 2b00 cmp r3, #0 8001ee8: d001 beq.n 8001eee { return HAL_ERROR; 8001eea: 2301 movs r3, #1 8001eec: e00e b.n 8001f0c } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001eee: 687b ldr r3, [r7, #4] 8001ef0: 2b0f cmp r3, #15 8001ef2: d80a bhi.n 8001f0a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001ef4: 2200 movs r2, #0 8001ef6: 6879 ldr r1, [r7, #4] 8001ef8: f04f 30ff mov.w r0, #4294967295 8001efc: f000 f92f bl 800215e uwTickPrio = TickPriority; 8001f00: 4a06 ldr r2, [pc, #24] @ (8001f1c ) 8001f02: 687b ldr r3, [r7, #4] 8001f04: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8001f06: 2300 movs r3, #0 8001f08: e000 b.n 8001f0c return HAL_ERROR; 8001f0a: 2301 movs r3, #1 } 8001f0c: 4618 mov r0, r3 8001f0e: 3708 adds r7, #8 8001f10: 46bd mov sp, r7 8001f12: bd80 pop {r7, pc} 8001f14: 20000104 .word 0x20000104 8001f18: 2000010c .word 0x2000010c 8001f1c: 20000108 .word 0x20000108 08001f20 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001f20: b480 push {r7} 8001f22: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001f24: 4b06 ldr r3, [pc, #24] @ (8001f40 ) 8001f26: 781b ldrb r3, [r3, #0] 8001f28: 461a mov r2, r3 8001f2a: 4b06 ldr r3, [pc, #24] @ (8001f44 ) 8001f2c: 681b ldr r3, [r3, #0] 8001f2e: 4413 add r3, r2 8001f30: 4a04 ldr r2, [pc, #16] @ (8001f44 ) 8001f32: 6013 str r3, [r2, #0] } 8001f34: bf00 nop 8001f36: 46bd mov sp, r7 8001f38: f85d 7b04 ldr.w r7, [sp], #4 8001f3c: 4770 bx lr 8001f3e: bf00 nop 8001f40: 2000010c .word 0x2000010c 8001f44: 20000e20 .word 0x20000e20 08001f48 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001f48: b480 push {r7} 8001f4a: af00 add r7, sp, #0 return uwTick; 8001f4c: 4b03 ldr r3, [pc, #12] @ (8001f5c ) 8001f4e: 681b ldr r3, [r3, #0] } 8001f50: 4618 mov r0, r3 8001f52: 46bd mov sp, r7 8001f54: f85d 7b04 ldr.w r7, [sp], #4 8001f58: 4770 bx lr 8001f5a: bf00 nop 8001f5c: 20000e20 .word 0x20000e20 08001f60 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001f60: b580 push {r7, lr} 8001f62: b084 sub sp, #16 8001f64: af00 add r7, sp, #0 8001f66: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001f68: f7ff ffee bl 8001f48 8001f6c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001f6e: 687b ldr r3, [r7, #4] 8001f70: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001f72: 68fb ldr r3, [r7, #12] 8001f74: f1b3 3fff cmp.w r3, #4294967295 8001f78: d005 beq.n 8001f86 { wait += (uint32_t)(uwTickFreq); 8001f7a: 4b0a ldr r3, [pc, #40] @ (8001fa4 ) 8001f7c: 781b ldrb r3, [r3, #0] 8001f7e: 461a mov r2, r3 8001f80: 68fb ldr r3, [r7, #12] 8001f82: 4413 add r3, r2 8001f84: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8001f86: bf00 nop 8001f88: f7ff ffde bl 8001f48 8001f8c: 4602 mov r2, r0 8001f8e: 68bb ldr r3, [r7, #8] 8001f90: 1ad3 subs r3, r2, r3 8001f92: 68fa ldr r2, [r7, #12] 8001f94: 429a cmp r2, r3 8001f96: d8f7 bhi.n 8001f88 { } } 8001f98: bf00 nop 8001f9a: bf00 nop 8001f9c: 3710 adds r7, #16 8001f9e: 46bd mov sp, r7 8001fa0: bd80 pop {r7, pc} 8001fa2: bf00 nop 8001fa4: 2000010c .word 0x2000010c 08001fa8 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001fa8: b480 push {r7} 8001faa: b085 sub sp, #20 8001fac: af00 add r7, sp, #0 8001fae: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001fb0: 687b ldr r3, [r7, #4] 8001fb2: f003 0307 and.w r3, r3, #7 8001fb6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001fb8: 4b0c ldr r3, [pc, #48] @ (8001fec <__NVIC_SetPriorityGrouping+0x44>) 8001fba: 68db ldr r3, [r3, #12] 8001fbc: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001fbe: 68ba ldr r2, [r7, #8] 8001fc0: f64f 03ff movw r3, #63743 @ 0xf8ff 8001fc4: 4013 ands r3, r2 8001fc6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001fc8: 68fb ldr r3, [r7, #12] 8001fca: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001fcc: 68bb ldr r3, [r7, #8] 8001fce: 4313 orrs r3, r2 reg_value = (reg_value | 8001fd0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8001fd4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8001fd8: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001fda: 4a04 ldr r2, [pc, #16] @ (8001fec <__NVIC_SetPriorityGrouping+0x44>) 8001fdc: 68bb ldr r3, [r7, #8] 8001fde: 60d3 str r3, [r2, #12] } 8001fe0: bf00 nop 8001fe2: 3714 adds r7, #20 8001fe4: 46bd mov sp, r7 8001fe6: f85d 7b04 ldr.w r7, [sp], #4 8001fea: 4770 bx lr 8001fec: e000ed00 .word 0xe000ed00 08001ff0 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001ff0: b480 push {r7} 8001ff2: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001ff4: 4b04 ldr r3, [pc, #16] @ (8002008 <__NVIC_GetPriorityGrouping+0x18>) 8001ff6: 68db ldr r3, [r3, #12] 8001ff8: 0a1b lsrs r3, r3, #8 8001ffa: f003 0307 and.w r3, r3, #7 } 8001ffe: 4618 mov r0, r3 8002000: 46bd mov sp, r7 8002002: f85d 7b04 ldr.w r7, [sp], #4 8002006: 4770 bx lr 8002008: e000ed00 .word 0xe000ed00 0800200c <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 800200c: b480 push {r7} 800200e: b083 sub sp, #12 8002010: af00 add r7, sp, #0 8002012: 4603 mov r3, r0 8002014: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8002016: f997 3007 ldrsb.w r3, [r7, #7] 800201a: 2b00 cmp r3, #0 800201c: db0b blt.n 8002036 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800201e: 79fb ldrb r3, [r7, #7] 8002020: f003 021f and.w r2, r3, #31 8002024: 4907 ldr r1, [pc, #28] @ (8002044 <__NVIC_EnableIRQ+0x38>) 8002026: f997 3007 ldrsb.w r3, [r7, #7] 800202a: 095b lsrs r3, r3, #5 800202c: 2001 movs r0, #1 800202e: fa00 f202 lsl.w r2, r0, r2 8002032: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8002036: bf00 nop 8002038: 370c adds r7, #12 800203a: 46bd mov sp, r7 800203c: f85d 7b04 ldr.w r7, [sp], #4 8002040: 4770 bx lr 8002042: bf00 nop 8002044: e000e100 .word 0xe000e100 08002048 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8002048: b480 push {r7} 800204a: b083 sub sp, #12 800204c: af00 add r7, sp, #0 800204e: 4603 mov r3, r0 8002050: 6039 str r1, [r7, #0] 8002052: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8002054: f997 3007 ldrsb.w r3, [r7, #7] 8002058: 2b00 cmp r3, #0 800205a: db0a blt.n 8002072 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800205c: 683b ldr r3, [r7, #0] 800205e: b2da uxtb r2, r3 8002060: 490c ldr r1, [pc, #48] @ (8002094 <__NVIC_SetPriority+0x4c>) 8002062: f997 3007 ldrsb.w r3, [r7, #7] 8002066: 0112 lsls r2, r2, #4 8002068: b2d2 uxtb r2, r2 800206a: 440b add r3, r1 800206c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8002070: e00a b.n 8002088 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002072: 683b ldr r3, [r7, #0] 8002074: b2da uxtb r2, r3 8002076: 4908 ldr r1, [pc, #32] @ (8002098 <__NVIC_SetPriority+0x50>) 8002078: 79fb ldrb r3, [r7, #7] 800207a: f003 030f and.w r3, r3, #15 800207e: 3b04 subs r3, #4 8002080: 0112 lsls r2, r2, #4 8002082: b2d2 uxtb r2, r2 8002084: 440b add r3, r1 8002086: 761a strb r2, [r3, #24] } 8002088: bf00 nop 800208a: 370c adds r7, #12 800208c: 46bd mov sp, r7 800208e: f85d 7b04 ldr.w r7, [sp], #4 8002092: 4770 bx lr 8002094: e000e100 .word 0xe000e100 8002098: e000ed00 .word 0xe000ed00 0800209c : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 800209c: b480 push {r7} 800209e: b089 sub sp, #36 @ 0x24 80020a0: af00 add r7, sp, #0 80020a2: 60f8 str r0, [r7, #12] 80020a4: 60b9 str r1, [r7, #8] 80020a6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80020a8: 68fb ldr r3, [r7, #12] 80020aa: f003 0307 and.w r3, r3, #7 80020ae: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80020b0: 69fb ldr r3, [r7, #28] 80020b2: f1c3 0307 rsb r3, r3, #7 80020b6: 2b04 cmp r3, #4 80020b8: bf28 it cs 80020ba: 2304 movcs r3, #4 80020bc: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80020be: 69fb ldr r3, [r7, #28] 80020c0: 3304 adds r3, #4 80020c2: 2b06 cmp r3, #6 80020c4: d902 bls.n 80020cc 80020c6: 69fb ldr r3, [r7, #28] 80020c8: 3b03 subs r3, #3 80020ca: e000 b.n 80020ce 80020cc: 2300 movs r3, #0 80020ce: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80020d0: f04f 32ff mov.w r2, #4294967295 80020d4: 69bb ldr r3, [r7, #24] 80020d6: fa02 f303 lsl.w r3, r2, r3 80020da: 43da mvns r2, r3 80020dc: 68bb ldr r3, [r7, #8] 80020de: 401a ands r2, r3 80020e0: 697b ldr r3, [r7, #20] 80020e2: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80020e4: f04f 31ff mov.w r1, #4294967295 80020e8: 697b ldr r3, [r7, #20] 80020ea: fa01 f303 lsl.w r3, r1, r3 80020ee: 43d9 mvns r1, r3 80020f0: 687b ldr r3, [r7, #4] 80020f2: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80020f4: 4313 orrs r3, r2 ); } 80020f6: 4618 mov r0, r3 80020f8: 3724 adds r7, #36 @ 0x24 80020fa: 46bd mov sp, r7 80020fc: f85d 7b04 ldr.w r7, [sp], #4 8002100: 4770 bx lr ... 08002104 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8002104: b580 push {r7, lr} 8002106: b082 sub sp, #8 8002108: af00 add r7, sp, #0 800210a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800210c: 687b ldr r3, [r7, #4] 800210e: 3b01 subs r3, #1 8002110: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8002114: d301 bcc.n 800211a { return (1UL); /* Reload value impossible */ 8002116: 2301 movs r3, #1 8002118: e00f b.n 800213a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800211a: 4a0a ldr r2, [pc, #40] @ (8002144 ) 800211c: 687b ldr r3, [r7, #4] 800211e: 3b01 subs r3, #1 8002120: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8002122: 210f movs r1, #15 8002124: f04f 30ff mov.w r0, #4294967295 8002128: f7ff ff8e bl 8002048 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800212c: 4b05 ldr r3, [pc, #20] @ (8002144 ) 800212e: 2200 movs r2, #0 8002130: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8002132: 4b04 ldr r3, [pc, #16] @ (8002144 ) 8002134: 2207 movs r2, #7 8002136: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8002138: 2300 movs r3, #0 } 800213a: 4618 mov r0, r3 800213c: 3708 adds r7, #8 800213e: 46bd mov sp, r7 8002140: bd80 pop {r7, pc} 8002142: bf00 nop 8002144: e000e010 .word 0xe000e010 08002148 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002148: b580 push {r7, lr} 800214a: b082 sub sp, #8 800214c: af00 add r7, sp, #0 800214e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8002150: 6878 ldr r0, [r7, #4] 8002152: f7ff ff29 bl 8001fa8 <__NVIC_SetPriorityGrouping> } 8002156: bf00 nop 8002158: 3708 adds r7, #8 800215a: 46bd mov sp, r7 800215c: bd80 pop {r7, pc} 0800215e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800215e: b580 push {r7, lr} 8002160: b086 sub sp, #24 8002162: af00 add r7, sp, #0 8002164: 4603 mov r3, r0 8002166: 60b9 str r1, [r7, #8] 8002168: 607a str r2, [r7, #4] 800216a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800216c: 2300 movs r3, #0 800216e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8002170: f7ff ff3e bl 8001ff0 <__NVIC_GetPriorityGrouping> 8002174: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8002176: 687a ldr r2, [r7, #4] 8002178: 68b9 ldr r1, [r7, #8] 800217a: 6978 ldr r0, [r7, #20] 800217c: f7ff ff8e bl 800209c 8002180: 4602 mov r2, r0 8002182: f997 300f ldrsb.w r3, [r7, #15] 8002186: 4611 mov r1, r2 8002188: 4618 mov r0, r3 800218a: f7ff ff5d bl 8002048 <__NVIC_SetPriority> } 800218e: bf00 nop 8002190: 3718 adds r7, #24 8002192: 46bd mov sp, r7 8002194: bd80 pop {r7, pc} 08002196 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8002196: b580 push {r7, lr} 8002198: b082 sub sp, #8 800219a: af00 add r7, sp, #0 800219c: 4603 mov r3, r0 800219e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80021a0: f997 3007 ldrsb.w r3, [r7, #7] 80021a4: 4618 mov r0, r3 80021a6: f7ff ff31 bl 800200c <__NVIC_EnableIRQ> } 80021aa: bf00 nop 80021ac: 3708 adds r7, #8 80021ae: 46bd mov sp, r7 80021b0: bd80 pop {r7, pc} 080021b2 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80021b2: b580 push {r7, lr} 80021b4: b082 sub sp, #8 80021b6: af00 add r7, sp, #0 80021b8: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80021ba: 6878 ldr r0, [r7, #4] 80021bc: f7ff ffa2 bl 8002104 80021c0: 4603 mov r3, r0 } 80021c2: 4618 mov r0, r3 80021c4: 3708 adds r7, #8 80021c6: 46bd mov sp, r7 80021c8: bd80 pop {r7, pc} ... 080021cc : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 80021cc: b580 push {r7, lr} 80021ce: b086 sub sp, #24 80021d0: af00 add r7, sp, #0 80021d2: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 80021d4: 2300 movs r3, #0 80021d6: 617b str r3, [r7, #20] uint32_t tickstart = HAL_GetTick(); 80021d8: f7ff feb6 bl 8001f48 80021dc: 6138 str r0, [r7, #16] DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) 80021de: 687b ldr r3, [r7, #4] 80021e0: 2b00 cmp r3, #0 80021e2: d101 bne.n 80021e8 { return HAL_ERROR; 80021e4: 2301 movs r3, #1 80021e6: e099 b.n 800231c assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80021e8: 687b ldr r3, [r7, #4] 80021ea: 2202 movs r2, #2 80021ec: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 80021f0: 687b ldr r3, [r7, #4] 80021f2: 2200 movs r2, #0 80021f4: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 80021f8: 687b ldr r3, [r7, #4] 80021fa: 681b ldr r3, [r3, #0] 80021fc: 681a ldr r2, [r3, #0] 80021fe: 687b ldr r3, [r7, #4] 8002200: 681b ldr r3, [r3, #0] 8002202: f022 0201 bic.w r2, r2, #1 8002206: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8002208: e00f b.n 800222a { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 800220a: f7ff fe9d bl 8001f48 800220e: 4602 mov r2, r0 8002210: 693b ldr r3, [r7, #16] 8002212: 1ad3 subs r3, r2, r3 8002214: 2b05 cmp r3, #5 8002216: d908 bls.n 800222a { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8002218: 687b ldr r3, [r7, #4] 800221a: 2220 movs r2, #32 800221c: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 800221e: 687b ldr r3, [r7, #4] 8002220: 2203 movs r2, #3 8002222: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_TIMEOUT; 8002226: 2303 movs r3, #3 8002228: e078 b.n 800231c while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 800222a: 687b ldr r3, [r7, #4] 800222c: 681b ldr r3, [r3, #0] 800222e: 681b ldr r3, [r3, #0] 8002230: f003 0301 and.w r3, r3, #1 8002234: 2b00 cmp r3, #0 8002236: d1e8 bne.n 800220a } } /* Get the CR register value */ tmp = hdma->Instance->CR; 8002238: 687b ldr r3, [r7, #4] 800223a: 681b ldr r3, [r3, #0] 800223c: 681b ldr r3, [r3, #0] 800223e: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8002240: 697a ldr r2, [r7, #20] 8002242: 4b38 ldr r3, [pc, #224] @ (8002324 ) 8002244: 4013 ands r3, r2 8002246: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ tmp |= hdma->Init.Channel | hdma->Init.Direction | 8002248: 687b ldr r3, [r7, #4] 800224a: 685a ldr r2, [r3, #4] 800224c: 687b ldr r3, [r7, #4] 800224e: 689b ldr r3, [r3, #8] 8002250: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8002252: 687b ldr r3, [r7, #4] 8002254: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Channel | hdma->Init.Direction | 8002256: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8002258: 687b ldr r3, [r7, #4] 800225a: 691b ldr r3, [r3, #16] 800225c: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800225e: 687b ldr r3, [r7, #4] 8002260: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8002262: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002264: 687b ldr r3, [r7, #4] 8002266: 699b ldr r3, [r3, #24] 8002268: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800226a: 687b ldr r3, [r7, #4] 800226c: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800226e: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8002270: 687b ldr r3, [r7, #4] 8002272: 6a1b ldr r3, [r3, #32] 8002274: 4313 orrs r3, r2 tmp |= hdma->Init.Channel | hdma->Init.Direction | 8002276: 697a ldr r2, [r7, #20] 8002278: 4313 orrs r3, r2 800227a: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 800227c: 687b ldr r3, [r7, #4] 800227e: 6a5b ldr r3, [r3, #36] @ 0x24 8002280: 2b04 cmp r3, #4 8002282: d107 bne.n 8002294 { /* Get memory burst and peripheral burst */ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8002284: 687b ldr r3, [r7, #4] 8002286: 6ada ldr r2, [r3, #44] @ 0x2c 8002288: 687b ldr r3, [r7, #4] 800228a: 6b1b ldr r3, [r3, #48] @ 0x30 800228c: 4313 orrs r3, r2 800228e: 697a ldr r2, [r7, #20] 8002290: 4313 orrs r3, r2 8002292: 617b str r3, [r7, #20] } /* Write to DMA Stream CR register */ hdma->Instance->CR = tmp; 8002294: 687b ldr r3, [r7, #4] 8002296: 681b ldr r3, [r3, #0] 8002298: 697a ldr r2, [r7, #20] 800229a: 601a str r2, [r3, #0] /* Get the FCR register value */ tmp = hdma->Instance->FCR; 800229c: 687b ldr r3, [r7, #4] 800229e: 681b ldr r3, [r3, #0] 80022a0: 695b ldr r3, [r3, #20] 80022a2: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 80022a4: 697b ldr r3, [r7, #20] 80022a6: f023 0307 bic.w r3, r3, #7 80022aa: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ tmp |= hdma->Init.FIFOMode; 80022ac: 687b ldr r3, [r7, #4] 80022ae: 6a5b ldr r3, [r3, #36] @ 0x24 80022b0: 697a ldr r2, [r7, #20] 80022b2: 4313 orrs r3, r2 80022b4: 617b str r3, [r7, #20] /* The FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 80022b6: 687b ldr r3, [r7, #4] 80022b8: 6a5b ldr r3, [r3, #36] @ 0x24 80022ba: 2b04 cmp r3, #4 80022bc: d117 bne.n 80022ee { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; 80022be: 687b ldr r3, [r7, #4] 80022c0: 6a9b ldr r3, [r3, #40] @ 0x28 80022c2: 697a ldr r2, [r7, #20] 80022c4: 4313 orrs r3, r2 80022c6: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 bursts */ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) 80022c8: 687b ldr r3, [r7, #4] 80022ca: 6adb ldr r3, [r3, #44] @ 0x2c 80022cc: 2b00 cmp r3, #0 80022ce: d00e beq.n 80022ee { if (DMA_CheckFifoParam(hdma) != HAL_OK) 80022d0: 6878 ldr r0, [r7, #4] 80022d2: f000 fb01 bl 80028d8 80022d6: 4603 mov r3, r0 80022d8: 2b00 cmp r3, #0 80022da: d008 beq.n 80022ee { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 80022dc: 687b ldr r3, [r7, #4] 80022de: 2240 movs r2, #64 @ 0x40 80022e0: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80022e2: 687b ldr r3, [r7, #4] 80022e4: 2201 movs r2, #1 80022e6: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 80022ea: 2301 movs r3, #1 80022ec: e016 b.n 800231c } } } /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; 80022ee: 687b ldr r3, [r7, #4] 80022f0: 681b ldr r3, [r3, #0] 80022f2: 697a ldr r2, [r7, #20] 80022f4: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 80022f6: 6878 ldr r0, [r7, #4] 80022f8: f000 fab8 bl 800286c 80022fc: 4603 mov r3, r0 80022fe: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8002300: 687b ldr r3, [r7, #4] 8002302: 6ddb ldr r3, [r3, #92] @ 0x5c 8002304: 223f movs r2, #63 @ 0x3f 8002306: 409a lsls r2, r3 8002308: 68fb ldr r3, [r7, #12] 800230a: 609a str r2, [r3, #8] /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800230c: 687b ldr r3, [r7, #4] 800230e: 2200 movs r2, #0 8002310: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002312: 687b ldr r3, [r7, #4] 8002314: 2201 movs r2, #1 8002316: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 800231a: 2300 movs r3, #0 } 800231c: 4618 mov r0, r3 800231e: 3718 adds r7, #24 8002320: 46bd mov sp, r7 8002322: bd80 pop {r7, pc} 8002324: f010803f .word 0xf010803f 08002328 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002328: b580 push {r7, lr} 800232a: b086 sub sp, #24 800232c: af00 add r7, sp, #0 800232e: 60f8 str r0, [r7, #12] 8002330: 60b9 str r1, [r7, #8] 8002332: 607a str r2, [r7, #4] 8002334: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8002336: 2300 movs r3, #0 8002338: 75fb strb r3, [r7, #23] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800233a: 68fb ldr r3, [r7, #12] 800233c: 6d9b ldr r3, [r3, #88] @ 0x58 800233e: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8002340: 68fb ldr r3, [r7, #12] 8002342: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8002346: 2b01 cmp r3, #1 8002348: d101 bne.n 800234e 800234a: 2302 movs r3, #2 800234c: e040 b.n 80023d0 800234e: 68fb ldr r3, [r7, #12] 8002350: 2201 movs r2, #1 8002352: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8002356: 68fb ldr r3, [r7, #12] 8002358: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 800235c: b2db uxtb r3, r3 800235e: 2b01 cmp r3, #1 8002360: d12f bne.n 80023c2 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002362: 68fb ldr r3, [r7, #12] 8002364: 2202 movs r2, #2 8002366: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800236a: 68fb ldr r3, [r7, #12] 800236c: 2200 movs r2, #0 800236e: 655a str r2, [r3, #84] @ 0x54 /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8002370: 683b ldr r3, [r7, #0] 8002372: 687a ldr r2, [r7, #4] 8002374: 68b9 ldr r1, [r7, #8] 8002376: 68f8 ldr r0, [r7, #12] 8002378: f000 fa4a bl 8002810 /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 800237c: 68fb ldr r3, [r7, #12] 800237e: 6ddb ldr r3, [r3, #92] @ 0x5c 8002380: 223f movs r2, #63 @ 0x3f 8002382: 409a lsls r2, r3 8002384: 693b ldr r3, [r7, #16] 8002386: 609a str r2, [r3, #8] /* Enable Common interrupts*/ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; 8002388: 68fb ldr r3, [r7, #12] 800238a: 681b ldr r3, [r3, #0] 800238c: 681a ldr r2, [r3, #0] 800238e: 68fb ldr r3, [r7, #12] 8002390: 681b ldr r3, [r3, #0] 8002392: f042 0216 orr.w r2, r2, #22 8002396: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8002398: 68fb ldr r3, [r7, #12] 800239a: 6c1b ldr r3, [r3, #64] @ 0x40 800239c: 2b00 cmp r3, #0 800239e: d007 beq.n 80023b0 { hdma->Instance->CR |= DMA_IT_HT; 80023a0: 68fb ldr r3, [r7, #12] 80023a2: 681b ldr r3, [r3, #0] 80023a4: 681a ldr r2, [r3, #0] 80023a6: 68fb ldr r3, [r7, #12] 80023a8: 681b ldr r3, [r3, #0] 80023aa: f042 0208 orr.w r2, r2, #8 80023ae: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 80023b0: 68fb ldr r3, [r7, #12] 80023b2: 681b ldr r3, [r3, #0] 80023b4: 681a ldr r2, [r3, #0] 80023b6: 68fb ldr r3, [r7, #12] 80023b8: 681b ldr r3, [r3, #0] 80023ba: f042 0201 orr.w r2, r2, #1 80023be: 601a str r2, [r3, #0] 80023c0: e005 b.n 80023ce } else { /* Process unlocked */ __HAL_UNLOCK(hdma); 80023c2: 68fb ldr r3, [r7, #12] 80023c4: 2200 movs r2, #0 80023c6: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_BUSY; 80023ca: 2302 movs r3, #2 80023cc: 75fb strb r3, [r7, #23] } return status; 80023ce: 7dfb ldrb r3, [r7, #23] } 80023d0: 4618 mov r0, r3 80023d2: 3718 adds r7, #24 80023d4: 46bd mov sp, r7 80023d6: bd80 pop {r7, pc} 080023d8 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 80023d8: b580 push {r7, lr} 80023da: b084 sub sp, #16 80023dc: af00 add r7, sp, #0 80023de: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 80023e0: 687b ldr r3, [r7, #4] 80023e2: 6d9b ldr r3, [r3, #88] @ 0x58 80023e4: 60fb str r3, [r7, #12] uint32_t tickstart = HAL_GetTick(); 80023e6: f7ff fdaf bl 8001f48 80023ea: 60b8 str r0, [r7, #8] if(hdma->State != HAL_DMA_STATE_BUSY) 80023ec: 687b ldr r3, [r7, #4] 80023ee: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80023f2: b2db uxtb r3, r3 80023f4: 2b02 cmp r3, #2 80023f6: d008 beq.n 800240a { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80023f8: 687b ldr r3, [r7, #4] 80023fa: 2280 movs r2, #128 @ 0x80 80023fc: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80023fe: 687b ldr r3, [r7, #4] 8002400: 2200 movs r2, #0 8002402: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8002406: 2301 movs r3, #1 8002408: e052 b.n 80024b0 } else { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 800240a: 687b ldr r3, [r7, #4] 800240c: 681b ldr r3, [r3, #0] 800240e: 681a ldr r2, [r3, #0] 8002410: 687b ldr r3, [r7, #4] 8002412: 681b ldr r3, [r3, #0] 8002414: f022 0216 bic.w r2, r2, #22 8002418: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 800241a: 687b ldr r3, [r7, #4] 800241c: 681b ldr r3, [r3, #0] 800241e: 695a ldr r2, [r3, #20] 8002420: 687b ldr r3, [r7, #4] 8002422: 681b ldr r3, [r3, #0] 8002424: f022 0280 bic.w r2, r2, #128 @ 0x80 8002428: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 800242a: 687b ldr r3, [r7, #4] 800242c: 6c1b ldr r3, [r3, #64] @ 0x40 800242e: 2b00 cmp r3, #0 8002430: d103 bne.n 800243a 8002432: 687b ldr r3, [r7, #4] 8002434: 6c9b ldr r3, [r3, #72] @ 0x48 8002436: 2b00 cmp r3, #0 8002438: d007 beq.n 800244a { hdma->Instance->CR &= ~(DMA_IT_HT); 800243a: 687b ldr r3, [r7, #4] 800243c: 681b ldr r3, [r3, #0] 800243e: 681a ldr r2, [r3, #0] 8002440: 687b ldr r3, [r7, #4] 8002442: 681b ldr r3, [r3, #0] 8002444: f022 0208 bic.w r2, r2, #8 8002448: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800244a: 687b ldr r3, [r7, #4] 800244c: 681b ldr r3, [r3, #0] 800244e: 681a ldr r2, [r3, #0] 8002450: 687b ldr r3, [r7, #4] 8002452: 681b ldr r3, [r3, #0] 8002454: f022 0201 bic.w r2, r2, #1 8002458: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 800245a: e013 b.n 8002484 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 800245c: f7ff fd74 bl 8001f48 8002460: 4602 mov r2, r0 8002462: 68bb ldr r3, [r7, #8] 8002464: 1ad3 subs r3, r2, r3 8002466: 2b05 cmp r3, #5 8002468: d90c bls.n 8002484 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 800246a: 687b ldr r3, [r7, #4] 800246c: 2220 movs r2, #32 800246e: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 8002470: 687b ldr r3, [r7, #4] 8002472: 2203 movs r2, #3 8002474: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002478: 687b ldr r3, [r7, #4] 800247a: 2200 movs r2, #0 800247c: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_TIMEOUT; 8002480: 2303 movs r3, #3 8002482: e015 b.n 80024b0 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8002484: 687b ldr r3, [r7, #4] 8002486: 681b ldr r3, [r3, #0] 8002488: 681b ldr r3, [r3, #0] 800248a: f003 0301 and.w r3, r3, #1 800248e: 2b00 cmp r3, #0 8002490: d1e4 bne.n 800245c } } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 8002492: 687b ldr r3, [r7, #4] 8002494: 6ddb ldr r3, [r3, #92] @ 0x5c 8002496: 223f movs r2, #63 @ 0x3f 8002498: 409a lsls r2, r3 800249a: 68fb ldr r3, [r7, #12] 800249c: 609a str r2, [r3, #8] /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 800249e: 687b ldr r3, [r7, #4] 80024a0: 2201 movs r2, #1 80024a2: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80024a6: 687b ldr r3, [r7, #4] 80024a8: 2200 movs r2, #0 80024aa: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 80024ae: 2300 movs r3, #0 } 80024b0: 4618 mov r0, r3 80024b2: 3710 adds r7, #16 80024b4: 46bd mov sp, r7 80024b6: bd80 pop {r7, pc} 080024b8 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80024b8: b480 push {r7} 80024ba: b083 sub sp, #12 80024bc: af00 add r7, sp, #0 80024be: 6078 str r0, [r7, #4] if(hdma->State != HAL_DMA_STATE_BUSY) 80024c0: 687b ldr r3, [r7, #4] 80024c2: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80024c6: b2db uxtb r3, r3 80024c8: 2b02 cmp r3, #2 80024ca: d004 beq.n 80024d6 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80024cc: 687b ldr r3, [r7, #4] 80024ce: 2280 movs r2, #128 @ 0x80 80024d0: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 80024d2: 2301 movs r3, #1 80024d4: e00c b.n 80024f0 } else { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 80024d6: 687b ldr r3, [r7, #4] 80024d8: 2205 movs r2, #5 80024da: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80024de: 687b ldr r3, [r7, #4] 80024e0: 681b ldr r3, [r3, #0] 80024e2: 681a ldr r2, [r3, #0] 80024e4: 687b ldr r3, [r7, #4] 80024e6: 681b ldr r3, [r3, #0] 80024e8: f022 0201 bic.w r2, r2, #1 80024ec: 601a str r2, [r3, #0] } return HAL_OK; 80024ee: 2300 movs r3, #0 } 80024f0: 4618 mov r0, r3 80024f2: 370c adds r7, #12 80024f4: 46bd mov sp, r7 80024f6: f85d 7b04 ldr.w r7, [sp], #4 80024fa: 4770 bx lr 080024fc : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 80024fc: b580 push {r7, lr} 80024fe: b086 sub sp, #24 8002500: af00 add r7, sp, #0 8002502: 6078 str r0, [r7, #4] uint32_t tmpisr; __IO uint32_t count = 0U; 8002504: 2300 movs r3, #0 8002506: 60bb str r3, [r7, #8] uint32_t timeout = SystemCoreClock / 9600U; 8002508: 4b8e ldr r3, [pc, #568] @ (8002744 ) 800250a: 681b ldr r3, [r3, #0] 800250c: 4a8e ldr r2, [pc, #568] @ (8002748 ) 800250e: fba2 2303 umull r2, r3, r2, r3 8002512: 0a9b lsrs r3, r3, #10 8002514: 617b str r3, [r7, #20] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8002516: 687b ldr r3, [r7, #4] 8002518: 6d9b ldr r3, [r3, #88] @ 0x58 800251a: 613b str r3, [r7, #16] tmpisr = regs->ISR; 800251c: 693b ldr r3, [r7, #16] 800251e: 681b ldr r3, [r3, #0] 8002520: 60fb str r3, [r7, #12] /* Transfer Error Interrupt management ***************************************/ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) 8002522: 687b ldr r3, [r7, #4] 8002524: 6ddb ldr r3, [r3, #92] @ 0x5c 8002526: 2208 movs r2, #8 8002528: 409a lsls r2, r3 800252a: 68fb ldr r3, [r7, #12] 800252c: 4013 ands r3, r2 800252e: 2b00 cmp r3, #0 8002530: d01a beq.n 8002568 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) 8002532: 687b ldr r3, [r7, #4] 8002534: 681b ldr r3, [r3, #0] 8002536: 681b ldr r3, [r3, #0] 8002538: f003 0304 and.w r3, r3, #4 800253c: 2b00 cmp r3, #0 800253e: d013 beq.n 8002568 { /* Disable the transfer error interrupt */ hdma->Instance->CR &= ~(DMA_IT_TE); 8002540: 687b ldr r3, [r7, #4] 8002542: 681b ldr r3, [r3, #0] 8002544: 681a ldr r2, [r3, #0] 8002546: 687b ldr r3, [r7, #4] 8002548: 681b ldr r3, [r3, #0] 800254a: f022 0204 bic.w r2, r2, #4 800254e: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; 8002550: 687b ldr r3, [r7, #4] 8002552: 6ddb ldr r3, [r3, #92] @ 0x5c 8002554: 2208 movs r2, #8 8002556: 409a lsls r2, r3 8002558: 693b ldr r3, [r7, #16] 800255a: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 800255c: 687b ldr r3, [r7, #4] 800255e: 6d5b ldr r3, [r3, #84] @ 0x54 8002560: f043 0201 orr.w r2, r3, #1 8002564: 687b ldr r3, [r7, #4] 8002566: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) 8002568: 687b ldr r3, [r7, #4] 800256a: 6ddb ldr r3, [r3, #92] @ 0x5c 800256c: 2201 movs r2, #1 800256e: 409a lsls r2, r3 8002570: 68fb ldr r3, [r7, #12] 8002572: 4013 ands r3, r2 8002574: 2b00 cmp r3, #0 8002576: d012 beq.n 800259e { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) 8002578: 687b ldr r3, [r7, #4] 800257a: 681b ldr r3, [r3, #0] 800257c: 695b ldr r3, [r3, #20] 800257e: f003 0380 and.w r3, r3, #128 @ 0x80 8002582: 2b00 cmp r3, #0 8002584: d00b beq.n 800259e { /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; 8002586: 687b ldr r3, [r7, #4] 8002588: 6ddb ldr r3, [r3, #92] @ 0x5c 800258a: 2201 movs r2, #1 800258c: 409a lsls r2, r3 800258e: 693b ldr r3, [r7, #16] 8002590: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8002592: 687b ldr r3, [r7, #4] 8002594: 6d5b ldr r3, [r3, #84] @ 0x54 8002596: f043 0202 orr.w r2, r3, #2 800259a: 687b ldr r3, [r7, #4] 800259c: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) 800259e: 687b ldr r3, [r7, #4] 80025a0: 6ddb ldr r3, [r3, #92] @ 0x5c 80025a2: 2204 movs r2, #4 80025a4: 409a lsls r2, r3 80025a6: 68fb ldr r3, [r7, #12] 80025a8: 4013 ands r3, r2 80025aa: 2b00 cmp r3, #0 80025ac: d012 beq.n 80025d4 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) 80025ae: 687b ldr r3, [r7, #4] 80025b0: 681b ldr r3, [r3, #0] 80025b2: 681b ldr r3, [r3, #0] 80025b4: f003 0302 and.w r3, r3, #2 80025b8: 2b00 cmp r3, #0 80025ba: d00b beq.n 80025d4 { /* Clear the direct mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; 80025bc: 687b ldr r3, [r7, #4] 80025be: 6ddb ldr r3, [r3, #92] @ 0x5c 80025c0: 2204 movs r2, #4 80025c2: 409a lsls r2, r3 80025c4: 693b ldr r3, [r7, #16] 80025c6: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 80025c8: 687b ldr r3, [r7, #4] 80025ca: 6d5b ldr r3, [r3, #84] @ 0x54 80025cc: f043 0204 orr.w r2, r3, #4 80025d0: 687b ldr r3, [r7, #4] 80025d2: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) 80025d4: 687b ldr r3, [r7, #4] 80025d6: 6ddb ldr r3, [r3, #92] @ 0x5c 80025d8: 2210 movs r2, #16 80025da: 409a lsls r2, r3 80025dc: 68fb ldr r3, [r7, #12] 80025de: 4013 ands r3, r2 80025e0: 2b00 cmp r3, #0 80025e2: d043 beq.n 800266c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) 80025e4: 687b ldr r3, [r7, #4] 80025e6: 681b ldr r3, [r3, #0] 80025e8: 681b ldr r3, [r3, #0] 80025ea: f003 0308 and.w r3, r3, #8 80025ee: 2b00 cmp r3, #0 80025f0: d03c beq.n 800266c { /* Clear the half transfer complete flag */ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; 80025f2: 687b ldr r3, [r7, #4] 80025f4: 6ddb ldr r3, [r3, #92] @ 0x5c 80025f6: 2210 movs r2, #16 80025f8: 409a lsls r2, r3 80025fa: 693b ldr r3, [r7, #16] 80025fc: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 80025fe: 687b ldr r3, [r7, #4] 8002600: 681b ldr r3, [r3, #0] 8002602: 681b ldr r3, [r3, #0] 8002604: f403 2380 and.w r3, r3, #262144 @ 0x40000 8002608: 2b00 cmp r3, #0 800260a: d018 beq.n 800263e { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 800260c: 687b ldr r3, [r7, #4] 800260e: 681b ldr r3, [r3, #0] 8002610: 681b ldr r3, [r3, #0] 8002612: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002616: 2b00 cmp r3, #0 8002618: d108 bne.n 800262c { if(hdma->XferHalfCpltCallback != NULL) 800261a: 687b ldr r3, [r7, #4] 800261c: 6c1b ldr r3, [r3, #64] @ 0x40 800261e: 2b00 cmp r3, #0 8002620: d024 beq.n 800266c { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002622: 687b ldr r3, [r7, #4] 8002624: 6c1b ldr r3, [r3, #64] @ 0x40 8002626: 6878 ldr r0, [r7, #4] 8002628: 4798 blx r3 800262a: e01f b.n 800266c } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 800262c: 687b ldr r3, [r7, #4] 800262e: 6c9b ldr r3, [r3, #72] @ 0x48 8002630: 2b00 cmp r3, #0 8002632: d01b beq.n 800266c { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8002634: 687b ldr r3, [r7, #4] 8002636: 6c9b ldr r3, [r3, #72] @ 0x48 8002638: 6878 ldr r0, [r7, #4] 800263a: 4798 blx r3 800263c: e016 b.n 800266c } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 800263e: 687b ldr r3, [r7, #4] 8002640: 681b ldr r3, [r3, #0] 8002642: 681b ldr r3, [r3, #0] 8002644: f403 7380 and.w r3, r3, #256 @ 0x100 8002648: 2b00 cmp r3, #0 800264a: d107 bne.n 800265c { /* Disable the half transfer interrupt */ hdma->Instance->CR &= ~(DMA_IT_HT); 800264c: 687b ldr r3, [r7, #4] 800264e: 681b ldr r3, [r3, #0] 8002650: 681a ldr r2, [r3, #0] 8002652: 687b ldr r3, [r7, #4] 8002654: 681b ldr r3, [r3, #0] 8002656: f022 0208 bic.w r2, r2, #8 800265a: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 800265c: 687b ldr r3, [r7, #4] 800265e: 6c1b ldr r3, [r3, #64] @ 0x40 8002660: 2b00 cmp r3, #0 8002662: d003 beq.n 800266c { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002664: 687b ldr r3, [r7, #4] 8002666: 6c1b ldr r3, [r3, #64] @ 0x40 8002668: 6878 ldr r0, [r7, #4] 800266a: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) 800266c: 687b ldr r3, [r7, #4] 800266e: 6ddb ldr r3, [r3, #92] @ 0x5c 8002670: 2220 movs r2, #32 8002672: 409a lsls r2, r3 8002674: 68fb ldr r3, [r7, #12] 8002676: 4013 ands r3, r2 8002678: 2b00 cmp r3, #0 800267a: f000 808f beq.w 800279c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) 800267e: 687b ldr r3, [r7, #4] 8002680: 681b ldr r3, [r3, #0] 8002682: 681b ldr r3, [r3, #0] 8002684: f003 0310 and.w r3, r3, #16 8002688: 2b00 cmp r3, #0 800268a: f000 8087 beq.w 800279c { /* Clear the transfer complete flag */ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; 800268e: 687b ldr r3, [r7, #4] 8002690: 6ddb ldr r3, [r3, #92] @ 0x5c 8002692: 2220 movs r2, #32 8002694: 409a lsls r2, r3 8002696: 693b ldr r3, [r7, #16] 8002698: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 800269a: 687b ldr r3, [r7, #4] 800269c: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80026a0: b2db uxtb r3, r3 80026a2: 2b05 cmp r3, #5 80026a4: d136 bne.n 8002714 { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 80026a6: 687b ldr r3, [r7, #4] 80026a8: 681b ldr r3, [r3, #0] 80026aa: 681a ldr r2, [r3, #0] 80026ac: 687b ldr r3, [r7, #4] 80026ae: 681b ldr r3, [r3, #0] 80026b0: f022 0216 bic.w r2, r2, #22 80026b4: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 80026b6: 687b ldr r3, [r7, #4] 80026b8: 681b ldr r3, [r3, #0] 80026ba: 695a ldr r2, [r3, #20] 80026bc: 687b ldr r3, [r7, #4] 80026be: 681b ldr r3, [r3, #0] 80026c0: f022 0280 bic.w r2, r2, #128 @ 0x80 80026c4: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 80026c6: 687b ldr r3, [r7, #4] 80026c8: 6c1b ldr r3, [r3, #64] @ 0x40 80026ca: 2b00 cmp r3, #0 80026cc: d103 bne.n 80026d6 80026ce: 687b ldr r3, [r7, #4] 80026d0: 6c9b ldr r3, [r3, #72] @ 0x48 80026d2: 2b00 cmp r3, #0 80026d4: d007 beq.n 80026e6 { hdma->Instance->CR &= ~(DMA_IT_HT); 80026d6: 687b ldr r3, [r7, #4] 80026d8: 681b ldr r3, [r3, #0] 80026da: 681a ldr r2, [r3, #0] 80026dc: 687b ldr r3, [r7, #4] 80026de: 681b ldr r3, [r3, #0] 80026e0: f022 0208 bic.w r2, r2, #8 80026e4: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 80026e6: 687b ldr r3, [r7, #4] 80026e8: 6ddb ldr r3, [r3, #92] @ 0x5c 80026ea: 223f movs r2, #63 @ 0x3f 80026ec: 409a lsls r2, r3 80026ee: 693b ldr r3, [r7, #16] 80026f0: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80026f2: 687b ldr r3, [r7, #4] 80026f4: 2201 movs r2, #1 80026f6: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80026fa: 687b ldr r3, [r7, #4] 80026fc: 2200 movs r2, #0 80026fe: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 8002702: 687b ldr r3, [r7, #4] 8002704: 6d1b ldr r3, [r3, #80] @ 0x50 8002706: 2b00 cmp r3, #0 8002708: d07e beq.n 8002808 { hdma->XferAbortCallback(hdma); 800270a: 687b ldr r3, [r7, #4] 800270c: 6d1b ldr r3, [r3, #80] @ 0x50 800270e: 6878 ldr r0, [r7, #4] 8002710: 4798 blx r3 } return; 8002712: e079 b.n 8002808 } if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) 8002714: 687b ldr r3, [r7, #4] 8002716: 681b ldr r3, [r3, #0] 8002718: 681b ldr r3, [r3, #0] 800271a: f403 2380 and.w r3, r3, #262144 @ 0x40000 800271e: 2b00 cmp r3, #0 8002720: d01d beq.n 800275e { /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) 8002722: 687b ldr r3, [r7, #4] 8002724: 681b ldr r3, [r3, #0] 8002726: 681b ldr r3, [r3, #0] 8002728: f403 2300 and.w r3, r3, #524288 @ 0x80000 800272c: 2b00 cmp r3, #0 800272e: d10d bne.n 800274c { if(hdma->XferM1CpltCallback != NULL) 8002730: 687b ldr r3, [r7, #4] 8002732: 6c5b ldr r3, [r3, #68] @ 0x44 8002734: 2b00 cmp r3, #0 8002736: d031 beq.n 800279c { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 8002738: 687b ldr r3, [r7, #4] 800273a: 6c5b ldr r3, [r3, #68] @ 0x44 800273c: 6878 ldr r0, [r7, #4] 800273e: 4798 blx r3 8002740: e02c b.n 800279c 8002742: bf00 nop 8002744: 20000104 .word 0x20000104 8002748: 1b4e81b5 .word 0x1b4e81b5 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800274c: 687b ldr r3, [r7, #4] 800274e: 6bdb ldr r3, [r3, #60] @ 0x3c 8002750: 2b00 cmp r3, #0 8002752: d023 beq.n 800279c { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8002754: 687b ldr r3, [r7, #4] 8002756: 6bdb ldr r3, [r3, #60] @ 0x3c 8002758: 6878 ldr r0, [r7, #4] 800275a: 4798 blx r3 800275c: e01e b.n 800279c } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) 800275e: 687b ldr r3, [r7, #4] 8002760: 681b ldr r3, [r3, #0] 8002762: 681b ldr r3, [r3, #0] 8002764: f403 7380 and.w r3, r3, #256 @ 0x100 8002768: 2b00 cmp r3, #0 800276a: d10f bne.n 800278c { /* Disable the transfer complete interrupt */ hdma->Instance->CR &= ~(DMA_IT_TC); 800276c: 687b ldr r3, [r7, #4] 800276e: 681b ldr r3, [r3, #0] 8002770: 681a ldr r2, [r3, #0] 8002772: 687b ldr r3, [r7, #4] 8002774: 681b ldr r3, [r3, #0] 8002776: f022 0210 bic.w r2, r2, #16 800277a: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800277c: 687b ldr r3, [r7, #4] 800277e: 2201 movs r2, #1 8002780: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002784: 687b ldr r3, [r7, #4] 8002786: 2200 movs r2, #0 8002788: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800278c: 687b ldr r3, [r7, #4] 800278e: 6bdb ldr r3, [r3, #60] @ 0x3c 8002790: 2b00 cmp r3, #0 8002792: d003 beq.n 800279c { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8002794: 687b ldr r3, [r7, #4] 8002796: 6bdb ldr r3, [r3, #60] @ 0x3c 8002798: 6878 ldr r0, [r7, #4] 800279a: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 800279c: 687b ldr r3, [r7, #4] 800279e: 6d5b ldr r3, [r3, #84] @ 0x54 80027a0: 2b00 cmp r3, #0 80027a2: d032 beq.n 800280a { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) 80027a4: 687b ldr r3, [r7, #4] 80027a6: 6d5b ldr r3, [r3, #84] @ 0x54 80027a8: f003 0301 and.w r3, r3, #1 80027ac: 2b00 cmp r3, #0 80027ae: d022 beq.n 80027f6 { hdma->State = HAL_DMA_STATE_ABORT; 80027b0: 687b ldr r3, [r7, #4] 80027b2: 2205 movs r2, #5 80027b4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80027b8: 687b ldr r3, [r7, #4] 80027ba: 681b ldr r3, [r3, #0] 80027bc: 681a ldr r2, [r3, #0] 80027be: 687b ldr r3, [r7, #4] 80027c0: 681b ldr r3, [r3, #0] 80027c2: f022 0201 bic.w r2, r2, #1 80027c6: 601a str r2, [r3, #0] do { if (++count > timeout) 80027c8: 68bb ldr r3, [r7, #8] 80027ca: 3301 adds r3, #1 80027cc: 60bb str r3, [r7, #8] 80027ce: 697a ldr r2, [r7, #20] 80027d0: 429a cmp r2, r3 80027d2: d307 bcc.n 80027e4 { break; } } while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); 80027d4: 687b ldr r3, [r7, #4] 80027d6: 681b ldr r3, [r3, #0] 80027d8: 681b ldr r3, [r3, #0] 80027da: f003 0301 and.w r3, r3, #1 80027de: 2b00 cmp r3, #0 80027e0: d1f2 bne.n 80027c8 80027e2: e000 b.n 80027e6 break; 80027e4: bf00 nop /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80027e6: 687b ldr r3, [r7, #4] 80027e8: 2201 movs r2, #1 80027ea: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80027ee: 687b ldr r3, [r7, #4] 80027f0: 2200 movs r2, #0 80027f2: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 80027f6: 687b ldr r3, [r7, #4] 80027f8: 6cdb ldr r3, [r3, #76] @ 0x4c 80027fa: 2b00 cmp r3, #0 80027fc: d005 beq.n 800280a { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 80027fe: 687b ldr r3, [r7, #4] 8002800: 6cdb ldr r3, [r3, #76] @ 0x4c 8002802: 6878 ldr r0, [r7, #4] 8002804: 4798 blx r3 8002806: e000 b.n 800280a return; 8002808: bf00 nop } } } 800280a: 3718 adds r7, #24 800280c: 46bd mov sp, r7 800280e: bd80 pop {r7, pc} 08002810 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002810: b480 push {r7} 8002812: b085 sub sp, #20 8002814: af00 add r7, sp, #0 8002816: 60f8 str r0, [r7, #12] 8002818: 60b9 str r1, [r7, #8] 800281a: 607a str r2, [r7, #4] 800281c: 603b str r3, [r7, #0] /* Clear DBM bit */ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); 800281e: 68fb ldr r3, [r7, #12] 8002820: 681b ldr r3, [r3, #0] 8002822: 681a ldr r2, [r3, #0] 8002824: 68fb ldr r3, [r7, #12] 8002826: 681b ldr r3, [r3, #0] 8002828: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800282c: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; 800282e: 68fb ldr r3, [r7, #12] 8002830: 681b ldr r3, [r3, #0] 8002832: 683a ldr r2, [r7, #0] 8002834: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8002836: 68fb ldr r3, [r7, #12] 8002838: 689b ldr r3, [r3, #8] 800283a: 2b40 cmp r3, #64 @ 0x40 800283c: d108 bne.n 8002850 { /* Configure DMA Stream destination address */ hdma->Instance->PAR = DstAddress; 800283e: 68fb ldr r3, [r7, #12] 8002840: 681b ldr r3, [r3, #0] 8002842: 687a ldr r2, [r7, #4] 8002844: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; 8002846: 68fb ldr r3, [r7, #12] 8002848: 681b ldr r3, [r3, #0] 800284a: 68ba ldr r2, [r7, #8] 800284c: 60da str r2, [r3, #12] hdma->Instance->PAR = SrcAddress; /* Configure DMA Stream destination address */ hdma->Instance->M0AR = DstAddress; } } 800284e: e007 b.n 8002860 hdma->Instance->PAR = SrcAddress; 8002850: 68fb ldr r3, [r7, #12] 8002852: 681b ldr r3, [r3, #0] 8002854: 68ba ldr r2, [r7, #8] 8002856: 609a str r2, [r3, #8] hdma->Instance->M0AR = DstAddress; 8002858: 68fb ldr r3, [r7, #12] 800285a: 681b ldr r3, [r3, #0] 800285c: 687a ldr r2, [r7, #4] 800285e: 60da str r2, [r3, #12] } 8002860: bf00 nop 8002862: 3714 adds r7, #20 8002864: 46bd mov sp, r7 8002866: f85d 7b04 ldr.w r7, [sp], #4 800286a: 4770 bx lr 0800286c : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 800286c: b480 push {r7} 800286e: b085 sub sp, #20 8002870: af00 add r7, sp, #0 8002872: 6078 str r0, [r7, #4] uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; 8002874: 687b ldr r3, [r7, #4] 8002876: 681b ldr r3, [r3, #0] 8002878: b2db uxtb r3, r3 800287a: 3b10 subs r3, #16 800287c: 4a14 ldr r2, [pc, #80] @ (80028d0 ) 800287e: fba2 2303 umull r2, r3, r2, r3 8002882: 091b lsrs r3, r3, #4 8002884: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number]; 8002886: 4a13 ldr r2, [pc, #76] @ (80028d4 ) 8002888: 68fb ldr r3, [r7, #12] 800288a: 4413 add r3, r2 800288c: 781b ldrb r3, [r3, #0] 800288e: 461a mov r2, r3 8002890: 687b ldr r3, [r7, #4] 8002892: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 8002894: 68fb ldr r3, [r7, #12] 8002896: 2b03 cmp r3, #3 8002898: d909 bls.n 80028ae { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); 800289a: 687b ldr r3, [r7, #4] 800289c: 681b ldr r3, [r3, #0] 800289e: f423 737f bic.w r3, r3, #1020 @ 0x3fc 80028a2: f023 0303 bic.w r3, r3, #3 80028a6: 1d1a adds r2, r3, #4 80028a8: 687b ldr r3, [r7, #4] 80028aa: 659a str r2, [r3, #88] @ 0x58 80028ac: e007 b.n 80028be } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); 80028ae: 687b ldr r3, [r7, #4] 80028b0: 681b ldr r3, [r3, #0] 80028b2: f423 737f bic.w r3, r3, #1020 @ 0x3fc 80028b6: f023 0303 bic.w r3, r3, #3 80028ba: 687a ldr r2, [r7, #4] 80028bc: 6593 str r3, [r2, #88] @ 0x58 } return hdma->StreamBaseAddress; 80028be: 687b ldr r3, [r7, #4] 80028c0: 6d9b ldr r3, [r3, #88] @ 0x58 } 80028c2: 4618 mov r0, r3 80028c4: 3714 adds r7, #20 80028c6: 46bd mov sp, r7 80028c8: f85d 7b04 ldr.w r7, [sp], #4 80028cc: 4770 bx lr 80028ce: bf00 nop 80028d0: aaaaaaab .word 0xaaaaaaab 80028d4: 0800b450 .word 0x0800b450 080028d8 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 80028d8: b480 push {r7} 80028da: b085 sub sp, #20 80028dc: af00 add r7, sp, #0 80028de: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80028e0: 2300 movs r3, #0 80028e2: 73fb strb r3, [r7, #15] uint32_t tmp = hdma->Init.FIFOThreshold; 80028e4: 687b ldr r3, [r7, #4] 80028e6: 6a9b ldr r3, [r3, #40] @ 0x28 80028e8: 60bb str r3, [r7, #8] /* Memory Data size equal to Byte */ if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 80028ea: 687b ldr r3, [r7, #4] 80028ec: 699b ldr r3, [r3, #24] 80028ee: 2b00 cmp r3, #0 80028f0: d11f bne.n 8002932 { switch (tmp) 80028f2: 68bb ldr r3, [r7, #8] 80028f4: 2b03 cmp r3, #3 80028f6: d856 bhi.n 80029a6 80028f8: a201 add r2, pc, #4 @ (adr r2, 8002900 ) 80028fa: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80028fe: bf00 nop 8002900: 08002911 .word 0x08002911 8002904: 08002923 .word 0x08002923 8002908: 08002911 .word 0x08002911 800290c: 080029a7 .word 0x080029a7 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002910: 687b ldr r3, [r7, #4] 8002912: 6adb ldr r3, [r3, #44] @ 0x2c 8002914: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002918: 2b00 cmp r3, #0 800291a: d046 beq.n 80029aa { status = HAL_ERROR; 800291c: 2301 movs r3, #1 800291e: 73fb strb r3, [r7, #15] } break; 8002920: e043 b.n 80029aa case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8002922: 687b ldr r3, [r7, #4] 8002924: 6adb ldr r3, [r3, #44] @ 0x2c 8002926: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800292a: d140 bne.n 80029ae { status = HAL_ERROR; 800292c: 2301 movs r3, #1 800292e: 73fb strb r3, [r7, #15] } break; 8002930: e03d b.n 80029ae break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 8002932: 687b ldr r3, [r7, #4] 8002934: 699b ldr r3, [r3, #24] 8002936: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800293a: d121 bne.n 8002980 { switch (tmp) 800293c: 68bb ldr r3, [r7, #8] 800293e: 2b03 cmp r3, #3 8002940: d837 bhi.n 80029b2 8002942: a201 add r2, pc, #4 @ (adr r2, 8002948 ) 8002944: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002948: 08002959 .word 0x08002959 800294c: 0800295f .word 0x0800295f 8002950: 08002959 .word 0x08002959 8002954: 08002971 .word 0x08002971 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 8002958: 2301 movs r3, #1 800295a: 73fb strb r3, [r7, #15] break; 800295c: e030 b.n 80029c0 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800295e: 687b ldr r3, [r7, #4] 8002960: 6adb ldr r3, [r3, #44] @ 0x2c 8002962: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002966: 2b00 cmp r3, #0 8002968: d025 beq.n 80029b6 { status = HAL_ERROR; 800296a: 2301 movs r3, #1 800296c: 73fb strb r3, [r7, #15] } break; 800296e: e022 b.n 80029b6 case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8002970: 687b ldr r3, [r7, #4] 8002972: 6adb ldr r3, [r3, #44] @ 0x2c 8002974: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 8002978: d11f bne.n 80029ba { status = HAL_ERROR; 800297a: 2301 movs r3, #1 800297c: 73fb strb r3, [r7, #15] } break; 800297e: e01c b.n 80029ba } /* Memory Data size equal to Word */ else { switch (tmp) 8002980: 68bb ldr r3, [r7, #8] 8002982: 2b02 cmp r3, #2 8002984: d903 bls.n 800298e 8002986: 68bb ldr r3, [r7, #8] 8002988: 2b03 cmp r3, #3 800298a: d003 beq.n 8002994 { status = HAL_ERROR; } break; default: break; 800298c: e018 b.n 80029c0 status = HAL_ERROR; 800298e: 2301 movs r3, #1 8002990: 73fb strb r3, [r7, #15] break; 8002992: e015 b.n 80029c0 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8002994: 687b ldr r3, [r7, #4] 8002996: 6adb ldr r3, [r3, #44] @ 0x2c 8002998: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800299c: 2b00 cmp r3, #0 800299e: d00e beq.n 80029be status = HAL_ERROR; 80029a0: 2301 movs r3, #1 80029a2: 73fb strb r3, [r7, #15] break; 80029a4: e00b b.n 80029be break; 80029a6: bf00 nop 80029a8: e00a b.n 80029c0 break; 80029aa: bf00 nop 80029ac: e008 b.n 80029c0 break; 80029ae: bf00 nop 80029b0: e006 b.n 80029c0 break; 80029b2: bf00 nop 80029b4: e004 b.n 80029c0 break; 80029b6: bf00 nop 80029b8: e002 b.n 80029c0 break; 80029ba: bf00 nop 80029bc: e000 b.n 80029c0 break; 80029be: bf00 nop } } return status; 80029c0: 7bfb ldrb r3, [r7, #15] } 80029c2: 4618 mov r0, r3 80029c4: 3714 adds r7, #20 80029c6: 46bd mov sp, r7 80029c8: f85d 7b04 ldr.w r7, [sp], #4 80029cc: 4770 bx lr 80029ce: bf00 nop 080029d0 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80029d0: b480 push {r7} 80029d2: b089 sub sp, #36 @ 0x24 80029d4: af00 add r7, sp, #0 80029d6: 6078 str r0, [r7, #4] 80029d8: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 80029da: 2300 movs r3, #0 80029dc: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 80029de: 2300 movs r3, #0 80029e0: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 80029e2: 2300 movs r3, #0 80029e4: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 80029e6: 2300 movs r3, #0 80029e8: 61fb str r3, [r7, #28] 80029ea: e165 b.n 8002cb8 { /* Get the IO position */ ioposition = 0x01U << position; 80029ec: 2201 movs r2, #1 80029ee: 69fb ldr r3, [r7, #28] 80029f0: fa02 f303 lsl.w r3, r2, r3 80029f4: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80029f6: 683b ldr r3, [r7, #0] 80029f8: 681b ldr r3, [r3, #0] 80029fa: 697a ldr r2, [r7, #20] 80029fc: 4013 ands r3, r2 80029fe: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8002a00: 693a ldr r2, [r7, #16] 8002a02: 697b ldr r3, [r7, #20] 8002a04: 429a cmp r2, r3 8002a06: f040 8154 bne.w 8002cb2 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8002a0a: 683b ldr r3, [r7, #0] 8002a0c: 685b ldr r3, [r3, #4] 8002a0e: f003 0303 and.w r3, r3, #3 8002a12: 2b01 cmp r3, #1 8002a14: d005 beq.n 8002a22 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002a16: 683b ldr r3, [r7, #0] 8002a18: 685b ldr r3, [r3, #4] 8002a1a: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8002a1e: 2b02 cmp r3, #2 8002a20: d130 bne.n 8002a84 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8002a22: 687b ldr r3, [r7, #4] 8002a24: 689b ldr r3, [r3, #8] 8002a26: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8002a28: 69fb ldr r3, [r7, #28] 8002a2a: 005b lsls r3, r3, #1 8002a2c: 2203 movs r2, #3 8002a2e: fa02 f303 lsl.w r3, r2, r3 8002a32: 43db mvns r3, r3 8002a34: 69ba ldr r2, [r7, #24] 8002a36: 4013 ands r3, r2 8002a38: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8002a3a: 683b ldr r3, [r7, #0] 8002a3c: 68da ldr r2, [r3, #12] 8002a3e: 69fb ldr r3, [r7, #28] 8002a40: 005b lsls r3, r3, #1 8002a42: fa02 f303 lsl.w r3, r2, r3 8002a46: 69ba ldr r2, [r7, #24] 8002a48: 4313 orrs r3, r2 8002a4a: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8002a4c: 687b ldr r3, [r7, #4] 8002a4e: 69ba ldr r2, [r7, #24] 8002a50: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8002a52: 687b ldr r3, [r7, #4] 8002a54: 685b ldr r3, [r3, #4] 8002a56: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8002a58: 2201 movs r2, #1 8002a5a: 69fb ldr r3, [r7, #28] 8002a5c: fa02 f303 lsl.w r3, r2, r3 8002a60: 43db mvns r3, r3 8002a62: 69ba ldr r2, [r7, #24] 8002a64: 4013 ands r3, r2 8002a66: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8002a68: 683b ldr r3, [r7, #0] 8002a6a: 685b ldr r3, [r3, #4] 8002a6c: 091b lsrs r3, r3, #4 8002a6e: f003 0201 and.w r2, r3, #1 8002a72: 69fb ldr r3, [r7, #28] 8002a74: fa02 f303 lsl.w r3, r2, r3 8002a78: 69ba ldr r2, [r7, #24] 8002a7a: 4313 orrs r3, r2 8002a7c: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8002a7e: 687b ldr r3, [r7, #4] 8002a80: 69ba ldr r2, [r7, #24] 8002a82: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8002a84: 683b ldr r3, [r7, #0] 8002a86: 685b ldr r3, [r3, #4] 8002a88: f003 0303 and.w r3, r3, #3 8002a8c: 2b03 cmp r3, #3 8002a8e: d017 beq.n 8002ac0 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8002a90: 687b ldr r3, [r7, #4] 8002a92: 68db ldr r3, [r3, #12] 8002a94: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8002a96: 69fb ldr r3, [r7, #28] 8002a98: 005b lsls r3, r3, #1 8002a9a: 2203 movs r2, #3 8002a9c: fa02 f303 lsl.w r3, r2, r3 8002aa0: 43db mvns r3, r3 8002aa2: 69ba ldr r2, [r7, #24] 8002aa4: 4013 ands r3, r2 8002aa6: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8002aa8: 683b ldr r3, [r7, #0] 8002aaa: 689a ldr r2, [r3, #8] 8002aac: 69fb ldr r3, [r7, #28] 8002aae: 005b lsls r3, r3, #1 8002ab0: fa02 f303 lsl.w r3, r2, r3 8002ab4: 69ba ldr r2, [r7, #24] 8002ab6: 4313 orrs r3, r2 8002ab8: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8002aba: 687b ldr r3, [r7, #4] 8002abc: 69ba ldr r2, [r7, #24] 8002abe: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002ac0: 683b ldr r3, [r7, #0] 8002ac2: 685b ldr r3, [r3, #4] 8002ac4: f003 0303 and.w r3, r3, #3 8002ac8: 2b02 cmp r3, #2 8002aca: d123 bne.n 8002b14 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8002acc: 69fb ldr r3, [r7, #28] 8002ace: 08da lsrs r2, r3, #3 8002ad0: 687b ldr r3, [r7, #4] 8002ad2: 3208 adds r2, #8 8002ad4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8002ad8: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 8002ada: 69fb ldr r3, [r7, #28] 8002adc: f003 0307 and.w r3, r3, #7 8002ae0: 009b lsls r3, r3, #2 8002ae2: 220f movs r2, #15 8002ae4: fa02 f303 lsl.w r3, r2, r3 8002ae8: 43db mvns r3, r3 8002aea: 69ba ldr r2, [r7, #24] 8002aec: 4013 ands r3, r2 8002aee: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 8002af0: 683b ldr r3, [r7, #0] 8002af2: 691a ldr r2, [r3, #16] 8002af4: 69fb ldr r3, [r7, #28] 8002af6: f003 0307 and.w r3, r3, #7 8002afa: 009b lsls r3, r3, #2 8002afc: fa02 f303 lsl.w r3, r2, r3 8002b00: 69ba ldr r2, [r7, #24] 8002b02: 4313 orrs r3, r2 8002b04: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8002b06: 69fb ldr r3, [r7, #28] 8002b08: 08da lsrs r2, r3, #3 8002b0a: 687b ldr r3, [r7, #4] 8002b0c: 3208 adds r2, #8 8002b0e: 69b9 ldr r1, [r7, #24] 8002b10: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8002b14: 687b ldr r3, [r7, #4] 8002b16: 681b ldr r3, [r3, #0] 8002b18: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 8002b1a: 69fb ldr r3, [r7, #28] 8002b1c: 005b lsls r3, r3, #1 8002b1e: 2203 movs r2, #3 8002b20: fa02 f303 lsl.w r3, r2, r3 8002b24: 43db mvns r3, r3 8002b26: 69ba ldr r2, [r7, #24] 8002b28: 4013 ands r3, r2 8002b2a: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8002b2c: 683b ldr r3, [r7, #0] 8002b2e: 685b ldr r3, [r3, #4] 8002b30: f003 0203 and.w r2, r3, #3 8002b34: 69fb ldr r3, [r7, #28] 8002b36: 005b lsls r3, r3, #1 8002b38: fa02 f303 lsl.w r3, r2, r3 8002b3c: 69ba ldr r2, [r7, #24] 8002b3e: 4313 orrs r3, r2 8002b40: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8002b42: 687b ldr r3, [r7, #4] 8002b44: 69ba ldr r2, [r7, #24] 8002b46: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8002b48: 683b ldr r3, [r7, #0] 8002b4a: 685b ldr r3, [r3, #4] 8002b4c: f403 3340 and.w r3, r3, #196608 @ 0x30000 8002b50: 2b00 cmp r3, #0 8002b52: f000 80ae beq.w 8002cb2 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002b56: 2300 movs r3, #0 8002b58: 60fb str r3, [r7, #12] 8002b5a: 4b5d ldr r3, [pc, #372] @ (8002cd0 ) 8002b5c: 6c5b ldr r3, [r3, #68] @ 0x44 8002b5e: 4a5c ldr r2, [pc, #368] @ (8002cd0 ) 8002b60: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002b64: 6453 str r3, [r2, #68] @ 0x44 8002b66: 4b5a ldr r3, [pc, #360] @ (8002cd0 ) 8002b68: 6c5b ldr r3, [r3, #68] @ 0x44 8002b6a: f403 4380 and.w r3, r3, #16384 @ 0x4000 8002b6e: 60fb str r3, [r7, #12] 8002b70: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8002b72: 4a58 ldr r2, [pc, #352] @ (8002cd4 ) 8002b74: 69fb ldr r3, [r7, #28] 8002b76: 089b lsrs r3, r3, #2 8002b78: 3302 adds r3, #2 8002b7a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8002b7e: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8002b80: 69fb ldr r3, [r7, #28] 8002b82: f003 0303 and.w r3, r3, #3 8002b86: 009b lsls r3, r3, #2 8002b88: 220f movs r2, #15 8002b8a: fa02 f303 lsl.w r3, r2, r3 8002b8e: 43db mvns r3, r3 8002b90: 69ba ldr r2, [r7, #24] 8002b92: 4013 ands r3, r2 8002b94: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8002b96: 687b ldr r3, [r7, #4] 8002b98: 4a4f ldr r2, [pc, #316] @ (8002cd8 ) 8002b9a: 4293 cmp r3, r2 8002b9c: d025 beq.n 8002bea 8002b9e: 687b ldr r3, [r7, #4] 8002ba0: 4a4e ldr r2, [pc, #312] @ (8002cdc ) 8002ba2: 4293 cmp r3, r2 8002ba4: d01f beq.n 8002be6 8002ba6: 687b ldr r3, [r7, #4] 8002ba8: 4a4d ldr r2, [pc, #308] @ (8002ce0 ) 8002baa: 4293 cmp r3, r2 8002bac: d019 beq.n 8002be2 8002bae: 687b ldr r3, [r7, #4] 8002bb0: 4a4c ldr r2, [pc, #304] @ (8002ce4 ) 8002bb2: 4293 cmp r3, r2 8002bb4: d013 beq.n 8002bde 8002bb6: 687b ldr r3, [r7, #4] 8002bb8: 4a4b ldr r2, [pc, #300] @ (8002ce8 ) 8002bba: 4293 cmp r3, r2 8002bbc: d00d beq.n 8002bda 8002bbe: 687b ldr r3, [r7, #4] 8002bc0: 4a4a ldr r2, [pc, #296] @ (8002cec ) 8002bc2: 4293 cmp r3, r2 8002bc4: d007 beq.n 8002bd6 8002bc6: 687b ldr r3, [r7, #4] 8002bc8: 4a49 ldr r2, [pc, #292] @ (8002cf0 ) 8002bca: 4293 cmp r3, r2 8002bcc: d101 bne.n 8002bd2 8002bce: 2306 movs r3, #6 8002bd0: e00c b.n 8002bec 8002bd2: 2307 movs r3, #7 8002bd4: e00a b.n 8002bec 8002bd6: 2305 movs r3, #5 8002bd8: e008 b.n 8002bec 8002bda: 2304 movs r3, #4 8002bdc: e006 b.n 8002bec 8002bde: 2303 movs r3, #3 8002be0: e004 b.n 8002bec 8002be2: 2302 movs r3, #2 8002be4: e002 b.n 8002bec 8002be6: 2301 movs r3, #1 8002be8: e000 b.n 8002bec 8002bea: 2300 movs r3, #0 8002bec: 69fa ldr r2, [r7, #28] 8002bee: f002 0203 and.w r2, r2, #3 8002bf2: 0092 lsls r2, r2, #2 8002bf4: 4093 lsls r3, r2 8002bf6: 69ba ldr r2, [r7, #24] 8002bf8: 4313 orrs r3, r2 8002bfa: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8002bfc: 4935 ldr r1, [pc, #212] @ (8002cd4 ) 8002bfe: 69fb ldr r3, [r7, #28] 8002c00: 089b lsrs r3, r3, #2 8002c02: 3302 adds r3, #2 8002c04: 69ba ldr r2, [r7, #24] 8002c06: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8002c0a: 4b3a ldr r3, [pc, #232] @ (8002cf4 ) 8002c0c: 689b ldr r3, [r3, #8] 8002c0e: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002c10: 693b ldr r3, [r7, #16] 8002c12: 43db mvns r3, r3 8002c14: 69ba ldr r2, [r7, #24] 8002c16: 4013 ands r3, r2 8002c18: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8002c1a: 683b ldr r3, [r7, #0] 8002c1c: 685b ldr r3, [r3, #4] 8002c1e: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8002c22: 2b00 cmp r3, #0 8002c24: d003 beq.n 8002c2e { temp |= iocurrent; 8002c26: 69ba ldr r2, [r7, #24] 8002c28: 693b ldr r3, [r7, #16] 8002c2a: 4313 orrs r3, r2 8002c2c: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 8002c2e: 4a31 ldr r2, [pc, #196] @ (8002cf4 ) 8002c30: 69bb ldr r3, [r7, #24] 8002c32: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8002c34: 4b2f ldr r3, [pc, #188] @ (8002cf4 ) 8002c36: 68db ldr r3, [r3, #12] 8002c38: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002c3a: 693b ldr r3, [r7, #16] 8002c3c: 43db mvns r3, r3 8002c3e: 69ba ldr r2, [r7, #24] 8002c40: 4013 ands r3, r2 8002c42: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8002c44: 683b ldr r3, [r7, #0] 8002c46: 685b ldr r3, [r3, #4] 8002c48: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8002c4c: 2b00 cmp r3, #0 8002c4e: d003 beq.n 8002c58 { temp |= iocurrent; 8002c50: 69ba ldr r2, [r7, #24] 8002c52: 693b ldr r3, [r7, #16] 8002c54: 4313 orrs r3, r2 8002c56: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8002c58: 4a26 ldr r2, [pc, #152] @ (8002cf4 ) 8002c5a: 69bb ldr r3, [r7, #24] 8002c5c: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 8002c5e: 4b25 ldr r3, [pc, #148] @ (8002cf4 ) 8002c60: 685b ldr r3, [r3, #4] 8002c62: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002c64: 693b ldr r3, [r7, #16] 8002c66: 43db mvns r3, r3 8002c68: 69ba ldr r2, [r7, #24] 8002c6a: 4013 ands r3, r2 8002c6c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8002c6e: 683b ldr r3, [r7, #0] 8002c70: 685b ldr r3, [r3, #4] 8002c72: f403 3300 and.w r3, r3, #131072 @ 0x20000 8002c76: 2b00 cmp r3, #0 8002c78: d003 beq.n 8002c82 { temp |= iocurrent; 8002c7a: 69ba ldr r2, [r7, #24] 8002c7c: 693b ldr r3, [r7, #16] 8002c7e: 4313 orrs r3, r2 8002c80: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 8002c82: 4a1c ldr r2, [pc, #112] @ (8002cf4 ) 8002c84: 69bb ldr r3, [r7, #24] 8002c86: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8002c88: 4b1a ldr r3, [pc, #104] @ (8002cf4 ) 8002c8a: 681b ldr r3, [r3, #0] 8002c8c: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8002c8e: 693b ldr r3, [r7, #16] 8002c90: 43db mvns r3, r3 8002c92: 69ba ldr r2, [r7, #24] 8002c94: 4013 ands r3, r2 8002c96: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8002c98: 683b ldr r3, [r7, #0] 8002c9a: 685b ldr r3, [r3, #4] 8002c9c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8002ca0: 2b00 cmp r3, #0 8002ca2: d003 beq.n 8002cac { temp |= iocurrent; 8002ca4: 69ba ldr r2, [r7, #24] 8002ca6: 693b ldr r3, [r7, #16] 8002ca8: 4313 orrs r3, r2 8002caa: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 8002cac: 4a11 ldr r2, [pc, #68] @ (8002cf4 ) 8002cae: 69bb ldr r3, [r7, #24] 8002cb0: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 8002cb2: 69fb ldr r3, [r7, #28] 8002cb4: 3301 adds r3, #1 8002cb6: 61fb str r3, [r7, #28] 8002cb8: 69fb ldr r3, [r7, #28] 8002cba: 2b0f cmp r3, #15 8002cbc: f67f ae96 bls.w 80029ec } } } } 8002cc0: bf00 nop 8002cc2: bf00 nop 8002cc4: 3724 adds r7, #36 @ 0x24 8002cc6: 46bd mov sp, r7 8002cc8: f85d 7b04 ldr.w r7, [sp], #4 8002ccc: 4770 bx lr 8002cce: bf00 nop 8002cd0: 40023800 .word 0x40023800 8002cd4: 40013800 .word 0x40013800 8002cd8: 40020000 .word 0x40020000 8002cdc: 40020400 .word 0x40020400 8002ce0: 40020800 .word 0x40020800 8002ce4: 40020c00 .word 0x40020c00 8002ce8: 40021000 .word 0x40021000 8002cec: 40021400 .word 0x40021400 8002cf0: 40021800 .word 0x40021800 8002cf4: 40013c00 .word 0x40013c00 08002cf8 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8002cf8: b480 push {r7} 8002cfa: b085 sub sp, #20 8002cfc: af00 add r7, sp, #0 8002cfe: 6078 str r0, [r7, #4] 8002d00: 460b mov r3, r1 8002d02: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8002d04: 687b ldr r3, [r7, #4] 8002d06: 691a ldr r2, [r3, #16] 8002d08: 887b ldrh r3, [r7, #2] 8002d0a: 4013 ands r3, r2 8002d0c: 2b00 cmp r3, #0 8002d0e: d002 beq.n 8002d16 { bitstatus = GPIO_PIN_SET; 8002d10: 2301 movs r3, #1 8002d12: 73fb strb r3, [r7, #15] 8002d14: e001 b.n 8002d1a } else { bitstatus = GPIO_PIN_RESET; 8002d16: 2300 movs r3, #0 8002d18: 73fb strb r3, [r7, #15] } return bitstatus; 8002d1a: 7bfb ldrb r3, [r7, #15] } 8002d1c: 4618 mov r0, r3 8002d1e: 3714 adds r7, #20 8002d20: 46bd mov sp, r7 8002d22: f85d 7b04 ldr.w r7, [sp], #4 8002d26: 4770 bx lr 08002d28 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8002d28: b480 push {r7} 8002d2a: b083 sub sp, #12 8002d2c: af00 add r7, sp, #0 8002d2e: 6078 str r0, [r7, #4] 8002d30: 460b mov r3, r1 8002d32: 807b strh r3, [r7, #2] 8002d34: 4613 mov r3, r2 8002d36: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8002d38: 787b ldrb r3, [r7, #1] 8002d3a: 2b00 cmp r3, #0 8002d3c: d003 beq.n 8002d46 { GPIOx->BSRR = GPIO_Pin; 8002d3e: 887a ldrh r2, [r7, #2] 8002d40: 687b ldr r3, [r7, #4] 8002d42: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8002d44: e003 b.n 8002d4e GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8002d46: 887b ldrh r3, [r7, #2] 8002d48: 041a lsls r2, r3, #16 8002d4a: 687b ldr r3, [r7, #4] 8002d4c: 619a str r2, [r3, #24] } 8002d4e: bf00 nop 8002d50: 370c adds r7, #12 8002d52: 46bd mov sp, r7 8002d54: f85d 7b04 ldr.w r7, [sp], #4 8002d58: 4770 bx lr ... 08002d5c : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8002d5c: b580 push {r7, lr} 8002d5e: b084 sub sp, #16 8002d60: af00 add r7, sp, #0 8002d62: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8002d64: 687b ldr r3, [r7, #4] 8002d66: 2b00 cmp r3, #0 8002d68: d101 bne.n 8002d6e { return HAL_ERROR; 8002d6a: 2301 movs r3, #1 8002d6c: e12b b.n 8002fc6 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8002d6e: 687b ldr r3, [r7, #4] 8002d70: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8002d74: b2db uxtb r3, r3 8002d76: 2b00 cmp r3, #0 8002d78: d106 bne.n 8002d88 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8002d7a: 687b ldr r3, [r7, #4] 8002d7c: 2200 movs r2, #0 8002d7e: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8002d82: 6878 ldr r0, [r7, #4] 8002d84: f7fd fd18 bl 80007b8 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8002d88: 687b ldr r3, [r7, #4] 8002d8a: 2224 movs r2, #36 @ 0x24 8002d8c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8002d90: 687b ldr r3, [r7, #4] 8002d92: 681b ldr r3, [r3, #0] 8002d94: 681a ldr r2, [r3, #0] 8002d96: 687b ldr r3, [r7, #4] 8002d98: 681b ldr r3, [r3, #0] 8002d9a: f022 0201 bic.w r2, r2, #1 8002d9e: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8002da0: 687b ldr r3, [r7, #4] 8002da2: 681b ldr r3, [r3, #0] 8002da4: 681a ldr r2, [r3, #0] 8002da6: 687b ldr r3, [r7, #4] 8002da8: 681b ldr r3, [r3, #0] 8002daa: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8002dae: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 8002db0: 687b ldr r3, [r7, #4] 8002db2: 681b ldr r3, [r3, #0] 8002db4: 681a ldr r2, [r3, #0] 8002db6: 687b ldr r3, [r7, #4] 8002db8: 681b ldr r3, [r3, #0] 8002dba: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8002dbe: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 8002dc0: f001 fc88 bl 80046d4 8002dc4: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 8002dc6: 687b ldr r3, [r7, #4] 8002dc8: 685b ldr r3, [r3, #4] 8002dca: 4a81 ldr r2, [pc, #516] @ (8002fd0 ) 8002dcc: 4293 cmp r3, r2 8002dce: d807 bhi.n 8002de0 8002dd0: 68fb ldr r3, [r7, #12] 8002dd2: 4a80 ldr r2, [pc, #512] @ (8002fd4 ) 8002dd4: 4293 cmp r3, r2 8002dd6: bf94 ite ls 8002dd8: 2301 movls r3, #1 8002dda: 2300 movhi r3, #0 8002ddc: b2db uxtb r3, r3 8002dde: e006 b.n 8002dee 8002de0: 68fb ldr r3, [r7, #12] 8002de2: 4a7d ldr r2, [pc, #500] @ (8002fd8 ) 8002de4: 4293 cmp r3, r2 8002de6: bf94 ite ls 8002de8: 2301 movls r3, #1 8002dea: 2300 movhi r3, #0 8002dec: b2db uxtb r3, r3 8002dee: 2b00 cmp r3, #0 8002df0: d001 beq.n 8002df6 { return HAL_ERROR; 8002df2: 2301 movs r3, #1 8002df4: e0e7 b.n 8002fc6 } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 8002df6: 68fb ldr r3, [r7, #12] 8002df8: 4a78 ldr r2, [pc, #480] @ (8002fdc ) 8002dfa: fba2 2303 umull r2, r3, r2, r3 8002dfe: 0c9b lsrs r3, r3, #18 8002e00: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8002e02: 687b ldr r3, [r7, #4] 8002e04: 681b ldr r3, [r3, #0] 8002e06: 685b ldr r3, [r3, #4] 8002e08: f023 013f bic.w r1, r3, #63 @ 0x3f 8002e0c: 687b ldr r3, [r7, #4] 8002e0e: 681b ldr r3, [r3, #0] 8002e10: 68ba ldr r2, [r7, #8] 8002e12: 430a orrs r2, r1 8002e14: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 8002e16: 687b ldr r3, [r7, #4] 8002e18: 681b ldr r3, [r3, #0] 8002e1a: 6a1b ldr r3, [r3, #32] 8002e1c: f023 013f bic.w r1, r3, #63 @ 0x3f 8002e20: 687b ldr r3, [r7, #4] 8002e22: 685b ldr r3, [r3, #4] 8002e24: 4a6a ldr r2, [pc, #424] @ (8002fd0 ) 8002e26: 4293 cmp r3, r2 8002e28: d802 bhi.n 8002e30 8002e2a: 68bb ldr r3, [r7, #8] 8002e2c: 3301 adds r3, #1 8002e2e: e009 b.n 8002e44 8002e30: 68bb ldr r3, [r7, #8] 8002e32: f44f 7296 mov.w r2, #300 @ 0x12c 8002e36: fb02 f303 mul.w r3, r2, r3 8002e3a: 4a69 ldr r2, [pc, #420] @ (8002fe0 ) 8002e3c: fba2 2303 umull r2, r3, r2, r3 8002e40: 099b lsrs r3, r3, #6 8002e42: 3301 adds r3, #1 8002e44: 687a ldr r2, [r7, #4] 8002e46: 6812 ldr r2, [r2, #0] 8002e48: 430b orrs r3, r1 8002e4a: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 8002e4c: 687b ldr r3, [r7, #4] 8002e4e: 681b ldr r3, [r3, #0] 8002e50: 69db ldr r3, [r3, #28] 8002e52: f423 424f bic.w r2, r3, #52992 @ 0xcf00 8002e56: f022 02ff bic.w r2, r2, #255 @ 0xff 8002e5a: 687b ldr r3, [r7, #4] 8002e5c: 685b ldr r3, [r3, #4] 8002e5e: 495c ldr r1, [pc, #368] @ (8002fd0 ) 8002e60: 428b cmp r3, r1 8002e62: d819 bhi.n 8002e98 8002e64: 68fb ldr r3, [r7, #12] 8002e66: 1e59 subs r1, r3, #1 8002e68: 687b ldr r3, [r7, #4] 8002e6a: 685b ldr r3, [r3, #4] 8002e6c: 005b lsls r3, r3, #1 8002e6e: fbb1 f3f3 udiv r3, r1, r3 8002e72: 1c59 adds r1, r3, #1 8002e74: f640 73fc movw r3, #4092 @ 0xffc 8002e78: 400b ands r3, r1 8002e7a: 2b00 cmp r3, #0 8002e7c: d00a beq.n 8002e94 8002e7e: 68fb ldr r3, [r7, #12] 8002e80: 1e59 subs r1, r3, #1 8002e82: 687b ldr r3, [r7, #4] 8002e84: 685b ldr r3, [r3, #4] 8002e86: 005b lsls r3, r3, #1 8002e88: fbb1 f3f3 udiv r3, r1, r3 8002e8c: 3301 adds r3, #1 8002e8e: f3c3 030b ubfx r3, r3, #0, #12 8002e92: e051 b.n 8002f38 8002e94: 2304 movs r3, #4 8002e96: e04f b.n 8002f38 8002e98: 687b ldr r3, [r7, #4] 8002e9a: 689b ldr r3, [r3, #8] 8002e9c: 2b00 cmp r3, #0 8002e9e: d111 bne.n 8002ec4 8002ea0: 68fb ldr r3, [r7, #12] 8002ea2: 1e58 subs r0, r3, #1 8002ea4: 687b ldr r3, [r7, #4] 8002ea6: 6859 ldr r1, [r3, #4] 8002ea8: 460b mov r3, r1 8002eaa: 005b lsls r3, r3, #1 8002eac: 440b add r3, r1 8002eae: fbb0 f3f3 udiv r3, r0, r3 8002eb2: 3301 adds r3, #1 8002eb4: f3c3 030b ubfx r3, r3, #0, #12 8002eb8: 2b00 cmp r3, #0 8002eba: bf0c ite eq 8002ebc: 2301 moveq r3, #1 8002ebe: 2300 movne r3, #0 8002ec0: b2db uxtb r3, r3 8002ec2: e012 b.n 8002eea 8002ec4: 68fb ldr r3, [r7, #12] 8002ec6: 1e58 subs r0, r3, #1 8002ec8: 687b ldr r3, [r7, #4] 8002eca: 6859 ldr r1, [r3, #4] 8002ecc: 460b mov r3, r1 8002ece: 009b lsls r3, r3, #2 8002ed0: 440b add r3, r1 8002ed2: 0099 lsls r1, r3, #2 8002ed4: 440b add r3, r1 8002ed6: fbb0 f3f3 udiv r3, r0, r3 8002eda: 3301 adds r3, #1 8002edc: f3c3 030b ubfx r3, r3, #0, #12 8002ee0: 2b00 cmp r3, #0 8002ee2: bf0c ite eq 8002ee4: 2301 moveq r3, #1 8002ee6: 2300 movne r3, #0 8002ee8: b2db uxtb r3, r3 8002eea: 2b00 cmp r3, #0 8002eec: d001 beq.n 8002ef2 8002eee: 2301 movs r3, #1 8002ef0: e022 b.n 8002f38 8002ef2: 687b ldr r3, [r7, #4] 8002ef4: 689b ldr r3, [r3, #8] 8002ef6: 2b00 cmp r3, #0 8002ef8: d10e bne.n 8002f18 8002efa: 68fb ldr r3, [r7, #12] 8002efc: 1e58 subs r0, r3, #1 8002efe: 687b ldr r3, [r7, #4] 8002f00: 6859 ldr r1, [r3, #4] 8002f02: 460b mov r3, r1 8002f04: 005b lsls r3, r3, #1 8002f06: 440b add r3, r1 8002f08: fbb0 f3f3 udiv r3, r0, r3 8002f0c: 3301 adds r3, #1 8002f0e: f3c3 030b ubfx r3, r3, #0, #12 8002f12: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8002f16: e00f b.n 8002f38 8002f18: 68fb ldr r3, [r7, #12] 8002f1a: 1e58 subs r0, r3, #1 8002f1c: 687b ldr r3, [r7, #4] 8002f1e: 6859 ldr r1, [r3, #4] 8002f20: 460b mov r3, r1 8002f22: 009b lsls r3, r3, #2 8002f24: 440b add r3, r1 8002f26: 0099 lsls r1, r3, #2 8002f28: 440b add r3, r1 8002f2a: fbb0 f3f3 udiv r3, r0, r3 8002f2e: 3301 adds r3, #1 8002f30: f3c3 030b ubfx r3, r3, #0, #12 8002f34: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8002f38: 6879 ldr r1, [r7, #4] 8002f3a: 6809 ldr r1, [r1, #0] 8002f3c: 4313 orrs r3, r2 8002f3e: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8002f40: 687b ldr r3, [r7, #4] 8002f42: 681b ldr r3, [r3, #0] 8002f44: 681b ldr r3, [r3, #0] 8002f46: f023 01c0 bic.w r1, r3, #192 @ 0xc0 8002f4a: 687b ldr r3, [r7, #4] 8002f4c: 69da ldr r2, [r3, #28] 8002f4e: 687b ldr r3, [r7, #4] 8002f50: 6a1b ldr r3, [r3, #32] 8002f52: 431a orrs r2, r3 8002f54: 687b ldr r3, [r7, #4] 8002f56: 681b ldr r3, [r3, #0] 8002f58: 430a orrs r2, r1 8002f5a: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 8002f5c: 687b ldr r3, [r7, #4] 8002f5e: 681b ldr r3, [r3, #0] 8002f60: 689b ldr r3, [r3, #8] 8002f62: f423 4303 bic.w r3, r3, #33536 @ 0x8300 8002f66: f023 03ff bic.w r3, r3, #255 @ 0xff 8002f6a: 687a ldr r2, [r7, #4] 8002f6c: 6911 ldr r1, [r2, #16] 8002f6e: 687a ldr r2, [r7, #4] 8002f70: 68d2 ldr r2, [r2, #12] 8002f72: 4311 orrs r1, r2 8002f74: 687a ldr r2, [r7, #4] 8002f76: 6812 ldr r2, [r2, #0] 8002f78: 430b orrs r3, r1 8002f7a: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 8002f7c: 687b ldr r3, [r7, #4] 8002f7e: 681b ldr r3, [r3, #0] 8002f80: 68db ldr r3, [r3, #12] 8002f82: f023 01ff bic.w r1, r3, #255 @ 0xff 8002f86: 687b ldr r3, [r7, #4] 8002f88: 695a ldr r2, [r3, #20] 8002f8a: 687b ldr r3, [r7, #4] 8002f8c: 699b ldr r3, [r3, #24] 8002f8e: 431a orrs r2, r3 8002f90: 687b ldr r3, [r7, #4] 8002f92: 681b ldr r3, [r3, #0] 8002f94: 430a orrs r2, r1 8002f96: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8002f98: 687b ldr r3, [r7, #4] 8002f9a: 681b ldr r3, [r3, #0] 8002f9c: 681a ldr r2, [r3, #0] 8002f9e: 687b ldr r3, [r7, #4] 8002fa0: 681b ldr r3, [r3, #0] 8002fa2: f042 0201 orr.w r2, r2, #1 8002fa6: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8002fa8: 687b ldr r3, [r7, #4] 8002faa: 2200 movs r2, #0 8002fac: 641a str r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_READY; 8002fae: 687b ldr r3, [r7, #4] 8002fb0: 2220 movs r2, #32 8002fb2: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->PreviousState = I2C_STATE_NONE; 8002fb6: 687b ldr r3, [r7, #4] 8002fb8: 2200 movs r2, #0 8002fba: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8002fbc: 687b ldr r3, [r7, #4] 8002fbe: 2200 movs r2, #0 8002fc0: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 8002fc4: 2300 movs r3, #0 } 8002fc6: 4618 mov r0, r3 8002fc8: 3710 adds r7, #16 8002fca: 46bd mov sp, r7 8002fcc: bd80 pop {r7, pc} 8002fce: bf00 nop 8002fd0: 000186a0 .word 0x000186a0 8002fd4: 001e847f .word 0x001e847f 8002fd8: 003d08ff .word 0x003d08ff 8002fdc: 431bde83 .word 0x431bde83 8002fe0: 10624dd3 .word 0x10624dd3 08002fe4 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8002fe4: b580 push {r7, lr} 8002fe6: b086 sub sp, #24 8002fe8: af02 add r7, sp, #8 8002fea: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx; #endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8002fec: 687b ldr r3, [r7, #4] 8002fee: 2b00 cmp r3, #0 8002ff0: d101 bne.n 8002ff6 { return HAL_ERROR; 8002ff2: 2301 movs r3, #1 8002ff4: e108 b.n 8003208 /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); #if defined (USB_OTG_FS) USBx = hpcd->Instance; 8002ff6: 687b ldr r3, [r7, #4] 8002ff8: 681b ldr r3, [r3, #0] 8002ffa: 60bb str r3, [r7, #8] #endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) 8002ffc: 687b ldr r3, [r7, #4] 8002ffe: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495 8003002: b2db uxtb r3, r3 8003004: 2b00 cmp r3, #0 8003006: d106 bne.n 8003016 { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 8003008: 687b ldr r3, [r7, #4] 800300a: 2200 movs r2, #0 800300c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8003010: 6878 ldr r0, [r7, #4] 8003012: f007 fe47 bl 800aca4 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8003016: 687b ldr r3, [r7, #4] 8003018: 2203 movs r2, #3 800301a: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ if (USBx == USB_OTG_FS) 800301e: 68bb ldr r3, [r7, #8] 8003020: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8003024: d102 bne.n 800302c { hpcd->Init.dma_enable = 0U; 8003026: 687b ldr r3, [r7, #4] 8003028: 2200 movs r2, #0 800302a: 719a strb r2, [r3, #6] } #endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 800302c: 687b ldr r3, [r7, #4] 800302e: 681b ldr r3, [r3, #0] 8003030: 4618 mov r0, r3 8003032: f004 fd3c bl 8007aae /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8003036: 687b ldr r3, [r7, #4] 8003038: 6818 ldr r0, [r3, #0] 800303a: 687b ldr r3, [r7, #4] 800303c: 7c1a ldrb r2, [r3, #16] 800303e: f88d 2000 strb.w r2, [sp] 8003042: 3304 adds r3, #4 8003044: cb0e ldmia r3, {r1, r2, r3} 8003046: f004 fc1b bl 8007880 800304a: 4603 mov r3, r0 800304c: 2b00 cmp r3, #0 800304e: d005 beq.n 800305c { hpcd->State = HAL_PCD_STATE_ERROR; 8003050: 687b ldr r3, [r7, #4] 8003052: 2202 movs r2, #2 8003054: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8003058: 2301 movs r3, #1 800305a: e0d5 b.n 8003208 } /* Force Device Mode */ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) 800305c: 687b ldr r3, [r7, #4] 800305e: 681b ldr r3, [r3, #0] 8003060: 2100 movs r1, #0 8003062: 4618 mov r0, r3 8003064: f004 fd34 bl 8007ad0 8003068: 4603 mov r3, r0 800306a: 2b00 cmp r3, #0 800306c: d005 beq.n 800307a { hpcd->State = HAL_PCD_STATE_ERROR; 800306e: 687b ldr r3, [r7, #4] 8003070: 2202 movs r2, #2 8003072: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 8003076: 2301 movs r3, #1 8003078: e0c6 b.n 8003208 } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800307a: 2300 movs r3, #0 800307c: 73fb strb r3, [r7, #15] 800307e: e04a b.n 8003116 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8003080: 7bfa ldrb r2, [r7, #15] 8003082: 6879 ldr r1, [r7, #4] 8003084: 4613 mov r3, r2 8003086: 00db lsls r3, r3, #3 8003088: 4413 add r3, r2 800308a: 009b lsls r3, r3, #2 800308c: 440b add r3, r1 800308e: 3315 adds r3, #21 8003090: 2201 movs r2, #1 8003092: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8003094: 7bfa ldrb r2, [r7, #15] 8003096: 6879 ldr r1, [r7, #4] 8003098: 4613 mov r3, r2 800309a: 00db lsls r3, r3, #3 800309c: 4413 add r3, r2 800309e: 009b lsls r3, r3, #2 80030a0: 440b add r3, r1 80030a2: 3314 adds r3, #20 80030a4: 7bfa ldrb r2, [r7, #15] 80030a6: 701a strb r2, [r3, #0] hpcd->IN_ep[i].tx_fifo_num = i; 80030a8: 7bfa ldrb r2, [r7, #15] 80030aa: 7bfb ldrb r3, [r7, #15] 80030ac: b298 uxth r0, r3 80030ae: 6879 ldr r1, [r7, #4] 80030b0: 4613 mov r3, r2 80030b2: 00db lsls r3, r3, #3 80030b4: 4413 add r3, r2 80030b6: 009b lsls r3, r3, #2 80030b8: 440b add r3, r1 80030ba: 332e adds r3, #46 @ 0x2e 80030bc: 4602 mov r2, r0 80030be: 801a strh r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 80030c0: 7bfa ldrb r2, [r7, #15] 80030c2: 6879 ldr r1, [r7, #4] 80030c4: 4613 mov r3, r2 80030c6: 00db lsls r3, r3, #3 80030c8: 4413 add r3, r2 80030ca: 009b lsls r3, r3, #2 80030cc: 440b add r3, r1 80030ce: 3318 adds r3, #24 80030d0: 2200 movs r2, #0 80030d2: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 80030d4: 7bfa ldrb r2, [r7, #15] 80030d6: 6879 ldr r1, [r7, #4] 80030d8: 4613 mov r3, r2 80030da: 00db lsls r3, r3, #3 80030dc: 4413 add r3, r2 80030de: 009b lsls r3, r3, #2 80030e0: 440b add r3, r1 80030e2: 331c adds r3, #28 80030e4: 2200 movs r2, #0 80030e6: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 80030e8: 7bfa ldrb r2, [r7, #15] 80030ea: 6879 ldr r1, [r7, #4] 80030ec: 4613 mov r3, r2 80030ee: 00db lsls r3, r3, #3 80030f0: 4413 add r3, r2 80030f2: 009b lsls r3, r3, #2 80030f4: 440b add r3, r1 80030f6: 3320 adds r3, #32 80030f8: 2200 movs r2, #0 80030fa: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 80030fc: 7bfa ldrb r2, [r7, #15] 80030fe: 6879 ldr r1, [r7, #4] 8003100: 4613 mov r3, r2 8003102: 00db lsls r3, r3, #3 8003104: 4413 add r3, r2 8003106: 009b lsls r3, r3, #2 8003108: 440b add r3, r1 800310a: 3324 adds r3, #36 @ 0x24 800310c: 2200 movs r2, #0 800310e: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8003110: 7bfb ldrb r3, [r7, #15] 8003112: 3301 adds r3, #1 8003114: 73fb strb r3, [r7, #15] 8003116: 687b ldr r3, [r7, #4] 8003118: 791b ldrb r3, [r3, #4] 800311a: 7bfa ldrb r2, [r7, #15] 800311c: 429a cmp r2, r3 800311e: d3af bcc.n 8003080 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8003120: 2300 movs r3, #0 8003122: 73fb strb r3, [r7, #15] 8003124: e044 b.n 80031b0 { hpcd->OUT_ep[i].is_in = 0U; 8003126: 7bfa ldrb r2, [r7, #15] 8003128: 6879 ldr r1, [r7, #4] 800312a: 4613 mov r3, r2 800312c: 00db lsls r3, r3, #3 800312e: 4413 add r3, r2 8003130: 009b lsls r3, r3, #2 8003132: 440b add r3, r1 8003134: f203 2355 addw r3, r3, #597 @ 0x255 8003138: 2200 movs r2, #0 800313a: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 800313c: 7bfa ldrb r2, [r7, #15] 800313e: 6879 ldr r1, [r7, #4] 8003140: 4613 mov r3, r2 8003142: 00db lsls r3, r3, #3 8003144: 4413 add r3, r2 8003146: 009b lsls r3, r3, #2 8003148: 440b add r3, r1 800314a: f503 7315 add.w r3, r3, #596 @ 0x254 800314e: 7bfa ldrb r2, [r7, #15] 8003150: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8003152: 7bfa ldrb r2, [r7, #15] 8003154: 6879 ldr r1, [r7, #4] 8003156: 4613 mov r3, r2 8003158: 00db lsls r3, r3, #3 800315a: 4413 add r3, r2 800315c: 009b lsls r3, r3, #2 800315e: 440b add r3, r1 8003160: f503 7316 add.w r3, r3, #600 @ 0x258 8003164: 2200 movs r2, #0 8003166: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8003168: 7bfa ldrb r2, [r7, #15] 800316a: 6879 ldr r1, [r7, #4] 800316c: 4613 mov r3, r2 800316e: 00db lsls r3, r3, #3 8003170: 4413 add r3, r2 8003172: 009b lsls r3, r3, #2 8003174: 440b add r3, r1 8003176: f503 7317 add.w r3, r3, #604 @ 0x25c 800317a: 2200 movs r2, #0 800317c: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 800317e: 7bfa ldrb r2, [r7, #15] 8003180: 6879 ldr r1, [r7, #4] 8003182: 4613 mov r3, r2 8003184: 00db lsls r3, r3, #3 8003186: 4413 add r3, r2 8003188: 009b lsls r3, r3, #2 800318a: 440b add r3, r1 800318c: f503 7318 add.w r3, r3, #608 @ 0x260 8003190: 2200 movs r2, #0 8003192: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8003194: 7bfa ldrb r2, [r7, #15] 8003196: 6879 ldr r1, [r7, #4] 8003198: 4613 mov r3, r2 800319a: 00db lsls r3, r3, #3 800319c: 4413 add r3, r2 800319e: 009b lsls r3, r3, #2 80031a0: 440b add r3, r1 80031a2: f503 7319 add.w r3, r3, #612 @ 0x264 80031a6: 2200 movs r2, #0 80031a8: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80031aa: 7bfb ldrb r3, [r7, #15] 80031ac: 3301 adds r3, #1 80031ae: 73fb strb r3, [r7, #15] 80031b0: 687b ldr r3, [r7, #4] 80031b2: 791b ldrb r3, [r3, #4] 80031b4: 7bfa ldrb r2, [r7, #15] 80031b6: 429a cmp r2, r3 80031b8: d3b5 bcc.n 8003126 } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 80031ba: 687b ldr r3, [r7, #4] 80031bc: 6818 ldr r0, [r3, #0] 80031be: 687b ldr r3, [r7, #4] 80031c0: 7c1a ldrb r2, [r3, #16] 80031c2: f88d 2000 strb.w r2, [sp] 80031c6: 3304 adds r3, #4 80031c8: cb0e ldmia r3, {r1, r2, r3} 80031ca: f004 fccd bl 8007b68 80031ce: 4603 mov r3, r0 80031d0: 2b00 cmp r3, #0 80031d2: d005 beq.n 80031e0 { hpcd->State = HAL_PCD_STATE_ERROR; 80031d4: 687b ldr r3, [r7, #4] 80031d6: 2202 movs r2, #2 80031d8: f883 2495 strb.w r2, [r3, #1173] @ 0x495 return HAL_ERROR; 80031dc: 2301 movs r3, #1 80031de: e013 b.n 8003208 } hpcd->USB_Address = 0U; 80031e0: 687b ldr r3, [r7, #4] 80031e2: 2200 movs r2, #0 80031e4: 745a strb r2, [r3, #17] hpcd->State = HAL_PCD_STATE_READY; 80031e6: 687b ldr r3, [r7, #4] 80031e8: 2201 movs r2, #1 80031ea: f883 2495 strb.w r2, [r3, #1173] @ 0x495 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 80031ee: 687b ldr r3, [r7, #4] 80031f0: 7b1b ldrb r3, [r3, #12] 80031f2: 2b01 cmp r3, #1 80031f4: d102 bne.n 80031fc { (void)HAL_PCDEx_ActivateLPM(hpcd); 80031f6: 6878 ldr r0, [r7, #4] 80031f8: f001 f956 bl 80044a8 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); 80031fc: 687b ldr r3, [r7, #4] 80031fe: 681b ldr r3, [r3, #0] 8003200: 4618 mov r0, r3 8003202: f005 fd0a bl 8008c1a return HAL_OK; 8003206: 2300 movs r3, #0 } 8003208: 4618 mov r0, r3 800320a: 3710 adds r7, #16 800320c: 46bd mov sp, r7 800320e: bd80 pop {r7, pc} 08003210 : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 8003210: b580 push {r7, lr} 8003212: b084 sub sp, #16 8003214: af00 add r7, sp, #0 8003216: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003218: 687b ldr r3, [r7, #4] 800321a: 681b ldr r3, [r3, #0] 800321c: 60fb str r3, [r7, #12] __HAL_LOCK(hpcd); 800321e: 687b ldr r3, [r7, #4] 8003220: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003224: 2b01 cmp r3, #1 8003226: d101 bne.n 800322c 8003228: 2302 movs r3, #2 800322a: e022 b.n 8003272 800322c: 687b ldr r3, [r7, #4] 800322e: 2201 movs r2, #1 8003230: f883 2494 strb.w r2, [r3, #1172] @ 0x494 if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8003234: 68fb ldr r3, [r7, #12] 8003236: 68db ldr r3, [r3, #12] 8003238: f003 0340 and.w r3, r3, #64 @ 0x40 800323c: 2b00 cmp r3, #0 800323e: d009 beq.n 8003254 (hpcd->Init.battery_charging_enable == 1U)) 8003240: 687b ldr r3, [r7, #4] 8003242: 7b5b ldrb r3, [r3, #13] if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && 8003244: 2b01 cmp r3, #1 8003246: d105 bne.n 8003254 { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8003248: 68fb ldr r3, [r7, #12] 800324a: 6b9b ldr r3, [r3, #56] @ 0x38 800324c: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8003250: 68fb ldr r3, [r7, #12] 8003252: 639a str r2, [r3, #56] @ 0x38 } __HAL_PCD_ENABLE(hpcd); 8003254: 687b ldr r3, [r7, #4] 8003256: 681b ldr r3, [r3, #0] 8003258: 4618 mov r0, r3 800325a: f004 fc17 bl 8007a8c (void)USB_DevConnect(hpcd->Instance); 800325e: 687b ldr r3, [r7, #4] 8003260: 681b ldr r3, [r3, #0] 8003262: 4618 mov r0, r3 8003264: f005 fcb8 bl 8008bd8 __HAL_UNLOCK(hpcd); 8003268: 687b ldr r3, [r7, #4] 800326a: 2200 movs r2, #0 800326c: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003270: 2300 movs r3, #0 } 8003272: 4618 mov r0, r3 8003274: 3710 adds r7, #16 8003276: 46bd mov sp, r7 8003278: bd80 pop {r7, pc} 0800327a : * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 800327a: b590 push {r4, r7, lr} 800327c: b08d sub sp, #52 @ 0x34 800327e: af00 add r7, sp, #0 8003280: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003282: 687b ldr r3, [r7, #4] 8003284: 681b ldr r3, [r3, #0] 8003286: 623b str r3, [r7, #32] uint32_t USBx_BASE = (uint32_t)USBx; 8003288: 6a3b ldr r3, [r7, #32] 800328a: 61fb str r3, [r7, #28] uint32_t epnum; uint32_t fifoemptymsk; uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) 800328c: 687b ldr r3, [r7, #4] 800328e: 681b ldr r3, [r3, #0] 8003290: 4618 mov r0, r3 8003292: f005 fd76 bl 8008d82 8003296: 4603 mov r3, r0 8003298: 2b00 cmp r3, #0 800329a: f040 84b9 bne.w 8003c10 { /* avoid spurious interrupt */ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 800329e: 687b ldr r3, [r7, #4] 80032a0: 681b ldr r3, [r3, #0] 80032a2: 4618 mov r0, r3 80032a4: f005 fcda bl 8008c5c 80032a8: 4603 mov r3, r0 80032aa: 2b00 cmp r3, #0 80032ac: f000 84af beq.w 8003c0e { return; } /* store current frame number */ hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; 80032b0: 69fb ldr r3, [r7, #28] 80032b2: f503 6300 add.w r3, r3, #2048 @ 0x800 80032b6: 689b ldr r3, [r3, #8] 80032b8: 0a1b lsrs r3, r3, #8 80032ba: f3c3 020d ubfx r2, r3, #0, #14 80032be: 687b ldr r3, [r7, #4] 80032c0: f8c3 24d4 str.w r2, [r3, #1236] @ 0x4d4 if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) 80032c4: 687b ldr r3, [r7, #4] 80032c6: 681b ldr r3, [r3, #0] 80032c8: 4618 mov r0, r3 80032ca: f005 fcc7 bl 8008c5c 80032ce: 4603 mov r3, r0 80032d0: f003 0302 and.w r3, r3, #2 80032d4: 2b02 cmp r3, #2 80032d6: d107 bne.n 80032e8 { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); 80032d8: 687b ldr r3, [r7, #4] 80032da: 681b ldr r3, [r3, #0] 80032dc: 695a ldr r2, [r3, #20] 80032de: 687b ldr r3, [r7, #4] 80032e0: 681b ldr r3, [r3, #0] 80032e2: f002 0202 and.w r2, r2, #2 80032e6: 615a str r2, [r3, #20] } /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) 80032e8: 687b ldr r3, [r7, #4] 80032ea: 681b ldr r3, [r3, #0] 80032ec: 4618 mov r0, r3 80032ee: f005 fcb5 bl 8008c5c 80032f2: 4603 mov r3, r0 80032f4: f003 0310 and.w r3, r3, #16 80032f8: 2b10 cmp r3, #16 80032fa: d161 bne.n 80033c0 { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 80032fc: 687b ldr r3, [r7, #4] 80032fe: 681b ldr r3, [r3, #0] 8003300: 699a ldr r2, [r3, #24] 8003302: 687b ldr r3, [r7, #4] 8003304: 681b ldr r3, [r3, #0] 8003306: f022 0210 bic.w r2, r2, #16 800330a: 619a str r2, [r3, #24] RegVal = USBx->GRXSTSP; 800330c: 6a3b ldr r3, [r7, #32] 800330e: 6a1b ldr r3, [r3, #32] 8003310: 61bb str r3, [r7, #24] ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; 8003312: 69bb ldr r3, [r7, #24] 8003314: f003 020f and.w r2, r3, #15 8003318: 4613 mov r3, r2 800331a: 00db lsls r3, r3, #3 800331c: 4413 add r3, r2 800331e: 009b lsls r3, r3, #2 8003320: f503 7314 add.w r3, r3, #592 @ 0x250 8003324: 687a ldr r2, [r7, #4] 8003326: 4413 add r3, r2 8003328: 3304 adds r3, #4 800332a: 617b str r3, [r7, #20] if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) 800332c: 69bb ldr r3, [r7, #24] 800332e: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8003332: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8003336: d124 bne.n 8003382 { if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) 8003338: 69ba ldr r2, [r7, #24] 800333a: f647 73f0 movw r3, #32752 @ 0x7ff0 800333e: 4013 ands r3, r2 8003340: 2b00 cmp r3, #0 8003342: d035 beq.n 80033b0 { (void)USB_ReadPacket(USBx, ep->xfer_buff, 8003344: 697b ldr r3, [r7, #20] 8003346: 68d9 ldr r1, [r3, #12] (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); 8003348: 69bb ldr r3, [r7, #24] 800334a: 091b lsrs r3, r3, #4 800334c: b29b uxth r3, r3 (void)USB_ReadPacket(USBx, ep->xfer_buff, 800334e: f3c3 030a ubfx r3, r3, #0, #11 8003352: b29b uxth r3, r3 8003354: 461a mov r2, r3 8003356: 6a38 ldr r0, [r7, #32] 8003358: f005 faec bl 8008934 ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 800335c: 697b ldr r3, [r7, #20] 800335e: 68da ldr r2, [r3, #12] 8003360: 69bb ldr r3, [r7, #24] 8003362: 091b lsrs r3, r3, #4 8003364: f3c3 030a ubfx r3, r3, #0, #11 8003368: 441a add r2, r3 800336a: 697b ldr r3, [r7, #20] 800336c: 60da str r2, [r3, #12] ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 800336e: 697b ldr r3, [r7, #20] 8003370: 695a ldr r2, [r3, #20] 8003372: 69bb ldr r3, [r7, #24] 8003374: 091b lsrs r3, r3, #4 8003376: f3c3 030a ubfx r3, r3, #0, #11 800337a: 441a add r2, r3 800337c: 697b ldr r3, [r7, #20] 800337e: 615a str r2, [r3, #20] 8003380: e016 b.n 80033b0 } } else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) 8003382: 69bb ldr r3, [r7, #24] 8003384: f403 13f0 and.w r3, r3, #1966080 @ 0x1e0000 8003388: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 800338c: d110 bne.n 80033b0 { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); 800338e: 687b ldr r3, [r7, #4] 8003390: f203 439c addw r3, r3, #1180 @ 0x49c 8003394: 2208 movs r2, #8 8003396: 4619 mov r1, r3 8003398: 6a38 ldr r0, [r7, #32] 800339a: f005 facb bl 8008934 ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; 800339e: 697b ldr r3, [r7, #20] 80033a0: 695a ldr r2, [r3, #20] 80033a2: 69bb ldr r3, [r7, #24] 80033a4: 091b lsrs r3, r3, #4 80033a6: f3c3 030a ubfx r3, r3, #0, #11 80033aa: 441a add r2, r3 80033ac: 697b ldr r3, [r7, #20] 80033ae: 615a str r2, [r3, #20] else { /* ... */ } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 80033b0: 687b ldr r3, [r7, #4] 80033b2: 681b ldr r3, [r3, #0] 80033b4: 699a ldr r2, [r3, #24] 80033b6: 687b ldr r3, [r7, #4] 80033b8: 681b ldr r3, [r3, #0] 80033ba: f042 0210 orr.w r2, r2, #16 80033be: 619a str r2, [r3, #24] } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) 80033c0: 687b ldr r3, [r7, #4] 80033c2: 681b ldr r3, [r3, #0] 80033c4: 4618 mov r0, r3 80033c6: f005 fc49 bl 8008c5c 80033ca: 4603 mov r3, r0 80033cc: f403 2300 and.w r3, r3, #524288 @ 0x80000 80033d0: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 80033d4: f040 80a7 bne.w 8003526 { epnum = 0U; 80033d8: 2300 movs r3, #0 80033da: 627b str r3, [r7, #36] @ 0x24 /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); 80033dc: 687b ldr r3, [r7, #4] 80033de: 681b ldr r3, [r3, #0] 80033e0: 4618 mov r0, r3 80033e2: f005 fc4e bl 8008c82 80033e6: 62b8 str r0, [r7, #40] @ 0x28 while (ep_intr != 0U) 80033e8: e099 b.n 800351e { if ((ep_intr & 0x1U) != 0U) 80033ea: 6abb ldr r3, [r7, #40] @ 0x28 80033ec: f003 0301 and.w r3, r3, #1 80033f0: 2b00 cmp r3, #0 80033f2: f000 808e beq.w 8003512 { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); 80033f6: 687b ldr r3, [r7, #4] 80033f8: 681b ldr r3, [r3, #0] 80033fa: 6a7a ldr r2, [r7, #36] @ 0x24 80033fc: b2d2 uxtb r2, r2 80033fe: 4611 mov r1, r2 8003400: 4618 mov r0, r3 8003402: f005 fc72 bl 8008cea 8003406: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) 8003408: 693b ldr r3, [r7, #16] 800340a: f003 0301 and.w r3, r3, #1 800340e: 2b00 cmp r3, #0 8003410: d00c beq.n 800342c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); 8003412: 6a7b ldr r3, [r7, #36] @ 0x24 8003414: 015a lsls r2, r3, #5 8003416: 69fb ldr r3, [r7, #28] 8003418: 4413 add r3, r2 800341a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800341e: 461a mov r2, r3 8003420: 2301 movs r3, #1 8003422: 6093 str r3, [r2, #8] (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); 8003424: 6a79 ldr r1, [r7, #36] @ 0x24 8003426: 6878 ldr r0, [r7, #4] 8003428: f000 feb8 bl 800419c } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) 800342c: 693b ldr r3, [r7, #16] 800342e: f003 0308 and.w r3, r3, #8 8003432: 2b00 cmp r3, #0 8003434: d00c beq.n 8003450 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); 8003436: 6a7b ldr r3, [r7, #36] @ 0x24 8003438: 015a lsls r2, r3, #5 800343a: 69fb ldr r3, [r7, #28] 800343c: 4413 add r3, r2 800343e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003442: 461a mov r2, r3 8003444: 2308 movs r3, #8 8003446: 6093 str r3, [r2, #8] /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); 8003448: 6a79 ldr r1, [r7, #36] @ 0x24 800344a: 6878 ldr r0, [r7, #4] 800344c: f000 ff8e bl 800436c } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) 8003450: 693b ldr r3, [r7, #16] 8003452: f003 0310 and.w r3, r3, #16 8003456: 2b00 cmp r3, #0 8003458: d008 beq.n 800346c { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); 800345a: 6a7b ldr r3, [r7, #36] @ 0x24 800345c: 015a lsls r2, r3, #5 800345e: 69fb ldr r3, [r7, #28] 8003460: 4413 add r3, r2 8003462: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003466: 461a mov r2, r3 8003468: 2310 movs r3, #16 800346a: 6093 str r3, [r2, #8] } /* Clear OUT Endpoint disable interrupt */ if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) 800346c: 693b ldr r3, [r7, #16] 800346e: f003 0302 and.w r3, r3, #2 8003472: 2b00 cmp r3, #0 8003474: d030 beq.n 80034d8 { if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) 8003476: 6a3b ldr r3, [r7, #32] 8003478: 695b ldr r3, [r3, #20] 800347a: f003 0380 and.w r3, r3, #128 @ 0x80 800347e: 2b80 cmp r3, #128 @ 0x80 8003480: d109 bne.n 8003496 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; 8003482: 69fb ldr r3, [r7, #28] 8003484: f503 6300 add.w r3, r3, #2048 @ 0x800 8003488: 685b ldr r3, [r3, #4] 800348a: 69fa ldr r2, [r7, #28] 800348c: f502 6200 add.w r2, r2, #2048 @ 0x800 8003490: f443 6380 orr.w r3, r3, #1024 @ 0x400 8003494: 6053 str r3, [r2, #4] } ep = &hpcd->OUT_ep[epnum]; 8003496: 6a7a ldr r2, [r7, #36] @ 0x24 8003498: 4613 mov r3, r2 800349a: 00db lsls r3, r3, #3 800349c: 4413 add r3, r2 800349e: 009b lsls r3, r3, #2 80034a0: f503 7314 add.w r3, r3, #592 @ 0x250 80034a4: 687a ldr r2, [r7, #4] 80034a6: 4413 add r3, r2 80034a8: 3304 adds r3, #4 80034aa: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 80034ac: 697b ldr r3, [r7, #20] 80034ae: 78db ldrb r3, [r3, #3] 80034b0: 2b01 cmp r3, #1 80034b2: d108 bne.n 80034c6 { ep->is_iso_incomplete = 0U; 80034b4: 697b ldr r3, [r7, #20] 80034b6: 2200 movs r2, #0 80034b8: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); 80034ba: 6a7b ldr r3, [r7, #36] @ 0x24 80034bc: b2db uxtb r3, r3 80034be: 4619 mov r1, r3 80034c0: 6878 ldr r0, [r7, #4] 80034c2: f007 fd0b bl 800aedc #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); 80034c6: 6a7b ldr r3, [r7, #36] @ 0x24 80034c8: 015a lsls r2, r3, #5 80034ca: 69fb ldr r3, [r7, #28] 80034cc: 4413 add r3, r2 80034ce: f503 6330 add.w r3, r3, #2816 @ 0xb00 80034d2: 461a mov r2, r3 80034d4: 2302 movs r3, #2 80034d6: 6093 str r3, [r2, #8] } /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 80034d8: 693b ldr r3, [r7, #16] 80034da: f003 0320 and.w r3, r3, #32 80034de: 2b00 cmp r3, #0 80034e0: d008 beq.n 80034f4 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 80034e2: 6a7b ldr r3, [r7, #36] @ 0x24 80034e4: 015a lsls r2, r3, #5 80034e6: 69fb ldr r3, [r7, #28] 80034e8: 4413 add r3, r2 80034ea: f503 6330 add.w r3, r3, #2816 @ 0xb00 80034ee: 461a mov r2, r3 80034f0: 2320 movs r3, #32 80034f2: 6093 str r3, [r2, #8] } /* Clear OUT NAK interrupt */ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) 80034f4: 693b ldr r3, [r7, #16] 80034f6: f403 5300 and.w r3, r3, #8192 @ 0x2000 80034fa: 2b00 cmp r3, #0 80034fc: d009 beq.n 8003512 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); 80034fe: 6a7b ldr r3, [r7, #36] @ 0x24 8003500: 015a lsls r2, r3, #5 8003502: 69fb ldr r3, [r7, #28] 8003504: 4413 add r3, r2 8003506: f503 6330 add.w r3, r3, #2816 @ 0xb00 800350a: 461a mov r2, r3 800350c: f44f 5300 mov.w r3, #8192 @ 0x2000 8003510: 6093 str r3, [r2, #8] } } epnum++; 8003512: 6a7b ldr r3, [r7, #36] @ 0x24 8003514: 3301 adds r3, #1 8003516: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 8003518: 6abb ldr r3, [r7, #40] @ 0x28 800351a: 085b lsrs r3, r3, #1 800351c: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 800351e: 6abb ldr r3, [r7, #40] @ 0x28 8003520: 2b00 cmp r3, #0 8003522: f47f af62 bne.w 80033ea } } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) 8003526: 687b ldr r3, [r7, #4] 8003528: 681b ldr r3, [r3, #0] 800352a: 4618 mov r0, r3 800352c: f005 fb96 bl 8008c5c 8003530: 4603 mov r3, r0 8003532: f403 2380 and.w r3, r3, #262144 @ 0x40000 8003536: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800353a: f040 80db bne.w 80036f4 { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); 800353e: 687b ldr r3, [r7, #4] 8003540: 681b ldr r3, [r3, #0] 8003542: 4618 mov r0, r3 8003544: f005 fbb7 bl 8008cb6 8003548: 62b8 str r0, [r7, #40] @ 0x28 epnum = 0U; 800354a: 2300 movs r3, #0 800354c: 627b str r3, [r7, #36] @ 0x24 while (ep_intr != 0U) 800354e: e0cd b.n 80036ec { if ((ep_intr & 0x1U) != 0U) /* In ITR */ 8003550: 6abb ldr r3, [r7, #40] @ 0x28 8003552: f003 0301 and.w r3, r3, #1 8003556: 2b00 cmp r3, #0 8003558: f000 80c2 beq.w 80036e0 { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); 800355c: 687b ldr r3, [r7, #4] 800355e: 681b ldr r3, [r3, #0] 8003560: 6a7a ldr r2, [r7, #36] @ 0x24 8003562: b2d2 uxtb r2, r2 8003564: 4611 mov r1, r2 8003566: 4618 mov r0, r3 8003568: f005 fbdd bl 8008d26 800356c: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) 800356e: 693b ldr r3, [r7, #16] 8003570: f003 0301 and.w r3, r3, #1 8003574: 2b00 cmp r3, #0 8003576: d057 beq.n 8003628 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8003578: 6a7b ldr r3, [r7, #36] @ 0x24 800357a: f003 030f and.w r3, r3, #15 800357e: 2201 movs r2, #1 8003580: fa02 f303 lsl.w r3, r2, r3 8003584: 60fb str r3, [r7, #12] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8003586: 69fb ldr r3, [r7, #28] 8003588: f503 6300 add.w r3, r3, #2048 @ 0x800 800358c: 6b5a ldr r2, [r3, #52] @ 0x34 800358e: 68fb ldr r3, [r7, #12] 8003590: 43db mvns r3, r3 8003592: 69f9 ldr r1, [r7, #28] 8003594: f501 6100 add.w r1, r1, #2048 @ 0x800 8003598: 4013 ands r3, r2 800359a: 634b str r3, [r1, #52] @ 0x34 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); 800359c: 6a7b ldr r3, [r7, #36] @ 0x24 800359e: 015a lsls r2, r3, #5 80035a0: 69fb ldr r3, [r7, #28] 80035a2: 4413 add r3, r2 80035a4: f503 6310 add.w r3, r3, #2304 @ 0x900 80035a8: 461a mov r2, r3 80035aa: 2301 movs r3, #1 80035ac: 6093 str r3, [r2, #8] if (hpcd->Init.dma_enable == 1U) 80035ae: 687b ldr r3, [r7, #4] 80035b0: 799b ldrb r3, [r3, #6] 80035b2: 2b01 cmp r3, #1 80035b4: d132 bne.n 800361c { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 80035b6: 6879 ldr r1, [r7, #4] 80035b8: 6a7a ldr r2, [r7, #36] @ 0x24 80035ba: 4613 mov r3, r2 80035bc: 00db lsls r3, r3, #3 80035be: 4413 add r3, r2 80035c0: 009b lsls r3, r3, #2 80035c2: 440b add r3, r1 80035c4: 3320 adds r3, #32 80035c6: 6819 ldr r1, [r3, #0] 80035c8: 6878 ldr r0, [r7, #4] 80035ca: 6a7a ldr r2, [r7, #36] @ 0x24 80035cc: 4613 mov r3, r2 80035ce: 00db lsls r3, r3, #3 80035d0: 4413 add r3, r2 80035d2: 009b lsls r3, r3, #2 80035d4: 4403 add r3, r0 80035d6: 331c adds r3, #28 80035d8: 681b ldr r3, [r3, #0] 80035da: 4419 add r1, r3 80035dc: 6878 ldr r0, [r7, #4] 80035de: 6a7a ldr r2, [r7, #36] @ 0x24 80035e0: 4613 mov r3, r2 80035e2: 00db lsls r3, r3, #3 80035e4: 4413 add r3, r2 80035e6: 009b lsls r3, r3, #2 80035e8: 4403 add r3, r0 80035ea: 3320 adds r3, #32 80035ec: 6019 str r1, [r3, #0] /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) 80035ee: 6a7b ldr r3, [r7, #36] @ 0x24 80035f0: 2b00 cmp r3, #0 80035f2: d113 bne.n 800361c 80035f4: 6879 ldr r1, [r7, #4] 80035f6: 6a7a ldr r2, [r7, #36] @ 0x24 80035f8: 4613 mov r3, r2 80035fa: 00db lsls r3, r3, #3 80035fc: 4413 add r3, r2 80035fe: 009b lsls r3, r3, #2 8003600: 440b add r3, r1 8003602: 3324 adds r3, #36 @ 0x24 8003604: 681b ldr r3, [r3, #0] 8003606: 2b00 cmp r3, #0 8003608: d108 bne.n 800361c { /* prepare to rx more setup packets */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 800360a: 687b ldr r3, [r7, #4] 800360c: 6818 ldr r0, [r3, #0] 800360e: 687b ldr r3, [r7, #4] 8003610: f203 439c addw r3, r3, #1180 @ 0x49c 8003614: 461a mov r2, r3 8003616: 2101 movs r1, #1 8003618: f005 fbe4 bl 8008de4 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); 800361c: 6a7b ldr r3, [r7, #36] @ 0x24 800361e: b2db uxtb r3, r3 8003620: 4619 mov r1, r3 8003622: 6878 ldr r0, [r7, #4] 8003624: f007 fbd5 bl 800add2 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) 8003628: 693b ldr r3, [r7, #16] 800362a: f003 0308 and.w r3, r3, #8 800362e: 2b00 cmp r3, #0 8003630: d008 beq.n 8003644 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); 8003632: 6a7b ldr r3, [r7, #36] @ 0x24 8003634: 015a lsls r2, r3, #5 8003636: 69fb ldr r3, [r7, #28] 8003638: 4413 add r3, r2 800363a: f503 6310 add.w r3, r3, #2304 @ 0x900 800363e: 461a mov r2, r3 8003640: 2308 movs r3, #8 8003642: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) 8003644: 693b ldr r3, [r7, #16] 8003646: f003 0310 and.w r3, r3, #16 800364a: 2b00 cmp r3, #0 800364c: d008 beq.n 8003660 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); 800364e: 6a7b ldr r3, [r7, #36] @ 0x24 8003650: 015a lsls r2, r3, #5 8003652: 69fb ldr r3, [r7, #28] 8003654: 4413 add r3, r2 8003656: f503 6310 add.w r3, r3, #2304 @ 0x900 800365a: 461a mov r2, r3 800365c: 2310 movs r3, #16 800365e: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) 8003660: 693b ldr r3, [r7, #16] 8003662: f003 0340 and.w r3, r3, #64 @ 0x40 8003666: 2b00 cmp r3, #0 8003668: d008 beq.n 800367c { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); 800366a: 6a7b ldr r3, [r7, #36] @ 0x24 800366c: 015a lsls r2, r3, #5 800366e: 69fb ldr r3, [r7, #28] 8003670: 4413 add r3, r2 8003672: f503 6310 add.w r3, r3, #2304 @ 0x900 8003676: 461a mov r2, r3 8003678: 2340 movs r3, #64 @ 0x40 800367a: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) 800367c: 693b ldr r3, [r7, #16] 800367e: f003 0302 and.w r3, r3, #2 8003682: 2b00 cmp r3, #0 8003684: d023 beq.n 80036ce { (void)USB_FlushTxFifo(USBx, epnum); 8003686: 6a79 ldr r1, [r7, #36] @ 0x24 8003688: 6a38 ldr r0, [r7, #32] 800368a: f004 fbcb bl 8007e24 ep = &hpcd->IN_ep[epnum]; 800368e: 6a7a ldr r2, [r7, #36] @ 0x24 8003690: 4613 mov r3, r2 8003692: 00db lsls r3, r3, #3 8003694: 4413 add r3, r2 8003696: 009b lsls r3, r3, #2 8003698: 3310 adds r3, #16 800369a: 687a ldr r2, [r7, #4] 800369c: 4413 add r3, r2 800369e: 3304 adds r3, #4 80036a0: 617b str r3, [r7, #20] if (ep->is_iso_incomplete == 1U) 80036a2: 697b ldr r3, [r7, #20] 80036a4: 78db ldrb r3, [r3, #3] 80036a6: 2b01 cmp r3, #1 80036a8: d108 bne.n 80036bc { ep->is_iso_incomplete = 0U; 80036aa: 697b ldr r3, [r7, #20] 80036ac: 2200 movs r2, #0 80036ae: 70da strb r2, [r3, #3] #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); 80036b0: 6a7b ldr r3, [r7, #36] @ 0x24 80036b2: b2db uxtb r3, r3 80036b4: 4619 mov r1, r3 80036b6: 6878 ldr r0, [r7, #4] 80036b8: f007 fc22 bl 800af00 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); 80036bc: 6a7b ldr r3, [r7, #36] @ 0x24 80036be: 015a lsls r2, r3, #5 80036c0: 69fb ldr r3, [r7, #28] 80036c2: 4413 add r3, r2 80036c4: f503 6310 add.w r3, r3, #2304 @ 0x900 80036c8: 461a mov r2, r3 80036ca: 2302 movs r3, #2 80036cc: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) 80036ce: 693b ldr r3, [r7, #16] 80036d0: f003 0380 and.w r3, r3, #128 @ 0x80 80036d4: 2b00 cmp r3, #0 80036d6: d003 beq.n 80036e0 { (void)PCD_WriteEmptyTxFifo(hpcd, epnum); 80036d8: 6a79 ldr r1, [r7, #36] @ 0x24 80036da: 6878 ldr r0, [r7, #4] 80036dc: f000 fcd2 bl 8004084 } } epnum++; 80036e0: 6a7b ldr r3, [r7, #36] @ 0x24 80036e2: 3301 adds r3, #1 80036e4: 627b str r3, [r7, #36] @ 0x24 ep_intr >>= 1U; 80036e6: 6abb ldr r3, [r7, #40] @ 0x28 80036e8: 085b lsrs r3, r3, #1 80036ea: 62bb str r3, [r7, #40] @ 0x28 while (ep_intr != 0U) 80036ec: 6abb ldr r3, [r7, #40] @ 0x28 80036ee: 2b00 cmp r3, #0 80036f0: f47f af2e bne.w 8003550 } } /* Handle Resume Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) 80036f4: 687b ldr r3, [r7, #4] 80036f6: 681b ldr r3, [r3, #0] 80036f8: 4618 mov r0, r3 80036fa: f005 faaf bl 8008c5c 80036fe: 4603 mov r3, r0 8003700: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8003704: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8003708: d122 bne.n 8003750 { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 800370a: 69fb ldr r3, [r7, #28] 800370c: f503 6300 add.w r3, r3, #2048 @ 0x800 8003710: 685b ldr r3, [r3, #4] 8003712: 69fa ldr r2, [r7, #28] 8003714: f502 6200 add.w r2, r2, #2048 @ 0x800 8003718: f023 0301 bic.w r3, r3, #1 800371c: 6053 str r3, [r2, #4] if (hpcd->LPM_State == LPM_L1) 800371e: 687b ldr r3, [r7, #4] 8003720: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 8003724: 2b01 cmp r3, #1 8003726: d108 bne.n 800373a { hpcd->LPM_State = LPM_L0; 8003728: 687b ldr r3, [r7, #4] 800372a: 2200 movs r2, #0 800372c: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 8003730: 2100 movs r1, #0 8003732: 6878 ldr r0, [r7, #4] 8003734: f007 fd8a bl 800b24c 8003738: e002 b.n 8003740 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 800373a: 6878 ldr r0, [r7, #4] 800373c: f007 fbc0 bl 800aec0 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); 8003740: 687b ldr r3, [r7, #4] 8003742: 681b ldr r3, [r3, #0] 8003744: 695a ldr r2, [r3, #20] 8003746: 687b ldr r3, [r7, #4] 8003748: 681b ldr r3, [r3, #0] 800374a: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000 800374e: 615a str r2, [r3, #20] } /* Handle Suspend Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) 8003750: 687b ldr r3, [r7, #4] 8003752: 681b ldr r3, [r3, #0] 8003754: 4618 mov r0, r3 8003756: f005 fa81 bl 8008c5c 800375a: 4603 mov r3, r0 800375c: f403 6300 and.w r3, r3, #2048 @ 0x800 8003760: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8003764: d112 bne.n 800378c { if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 8003766: 69fb ldr r3, [r7, #28] 8003768: f503 6300 add.w r3, r3, #2048 @ 0x800 800376c: 689b ldr r3, [r3, #8] 800376e: f003 0301 and.w r3, r3, #1 8003772: 2b01 cmp r3, #1 8003774: d102 bne.n 800377c { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 8003776: 6878 ldr r0, [r7, #4] 8003778: f007 fb7c bl 800ae74 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); 800377c: 687b ldr r3, [r7, #4] 800377e: 681b ldr r3, [r3, #0] 8003780: 695a ldr r2, [r3, #20] 8003782: 687b ldr r3, [r7, #4] 8003784: 681b ldr r3, [r3, #0] 8003786: f402 6200 and.w r2, r2, #2048 @ 0x800 800378a: 615a str r2, [r3, #20] } #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) 800378c: 687b ldr r3, [r7, #4] 800378e: 681b ldr r3, [r3, #0] 8003790: 4618 mov r0, r3 8003792: f005 fa63 bl 8008c5c 8003796: 4603 mov r3, r0 8003798: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800379c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80037a0: d121 bne.n 80037e6 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); 80037a2: 687b ldr r3, [r7, #4] 80037a4: 681b ldr r3, [r3, #0] 80037a6: 695a ldr r2, [r3, #20] 80037a8: 687b ldr r3, [r7, #4] 80037aa: 681b ldr r3, [r3, #0] 80037ac: f002 6200 and.w r2, r2, #134217728 @ 0x8000000 80037b0: 615a str r2, [r3, #20] if (hpcd->LPM_State == LPM_L0) 80037b2: 687b ldr r3, [r7, #4] 80037b4: f893 34cc ldrb.w r3, [r3, #1228] @ 0x4cc 80037b8: 2b00 cmp r3, #0 80037ba: d111 bne.n 80037e0 { hpcd->LPM_State = LPM_L1; 80037bc: 687b ldr r3, [r7, #4] 80037be: 2201 movs r2, #1 80037c0: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; 80037c4: 687b ldr r3, [r7, #4] 80037c6: 681b ldr r3, [r3, #0] 80037c8: 6d5b ldr r3, [r3, #84] @ 0x54 80037ca: 089b lsrs r3, r3, #2 80037cc: f003 020f and.w r2, r3, #15 80037d0: 687b ldr r3, [r7, #4] 80037d2: f8c3 24d0 str.w r2, [r3, #1232] @ 0x4d0 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 80037d6: 2101 movs r1, #1 80037d8: 6878 ldr r0, [r7, #4] 80037da: f007 fd37 bl 800b24c 80037de: e002 b.n 80037e6 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 80037e0: 6878 ldr r0, [r7, #4] 80037e2: f007 fb47 bl 800ae74 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) 80037e6: 687b ldr r3, [r7, #4] 80037e8: 681b ldr r3, [r3, #0] 80037ea: 4618 mov r0, r3 80037ec: f005 fa36 bl 8008c5c 80037f0: 4603 mov r3, r0 80037f2: f403 5380 and.w r3, r3, #4096 @ 0x1000 80037f6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80037fa: f040 80b7 bne.w 800396c { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 80037fe: 69fb ldr r3, [r7, #28] 8003800: f503 6300 add.w r3, r3, #2048 @ 0x800 8003804: 685b ldr r3, [r3, #4] 8003806: 69fa ldr r2, [r7, #28] 8003808: f502 6200 add.w r2, r2, #2048 @ 0x800 800380c: f023 0301 bic.w r3, r3, #1 8003810: 6053 str r3, [r2, #4] (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); 8003812: 687b ldr r3, [r7, #4] 8003814: 681b ldr r3, [r3, #0] 8003816: 2110 movs r1, #16 8003818: 4618 mov r0, r3 800381a: f004 fb03 bl 8007e24 for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800381e: 2300 movs r3, #0 8003820: 62fb str r3, [r7, #44] @ 0x2c 8003822: e046 b.n 80038b2 { USBx_INEP(i)->DIEPINT = 0xFB7FU; 8003824: 6afb ldr r3, [r7, #44] @ 0x2c 8003826: 015a lsls r2, r3, #5 8003828: 69fb ldr r3, [r7, #28] 800382a: 4413 add r3, r2 800382c: f503 6310 add.w r3, r3, #2304 @ 0x900 8003830: 461a mov r2, r3 8003832: f64f 337f movw r3, #64383 @ 0xfb7f 8003836: 6093 str r3, [r2, #8] USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 8003838: 6afb ldr r3, [r7, #44] @ 0x2c 800383a: 015a lsls r2, r3, #5 800383c: 69fb ldr r3, [r7, #28] 800383e: 4413 add r3, r2 8003840: f503 6310 add.w r3, r3, #2304 @ 0x900 8003844: 681b ldr r3, [r3, #0] 8003846: 6afa ldr r2, [r7, #44] @ 0x2c 8003848: 0151 lsls r1, r2, #5 800384a: 69fa ldr r2, [r7, #28] 800384c: 440a add r2, r1 800384e: f502 6210 add.w r2, r2, #2304 @ 0x900 8003852: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8003856: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8003858: 6afb ldr r3, [r7, #44] @ 0x2c 800385a: 015a lsls r2, r3, #5 800385c: 69fb ldr r3, [r7, #28] 800385e: 4413 add r3, r2 8003860: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003864: 461a mov r2, r3 8003866: f64f 337f movw r3, #64383 @ 0xfb7f 800386a: 6093 str r3, [r2, #8] USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 800386c: 6afb ldr r3, [r7, #44] @ 0x2c 800386e: 015a lsls r2, r3, #5 8003870: 69fb ldr r3, [r7, #28] 8003872: 4413 add r3, r2 8003874: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003878: 681b ldr r3, [r3, #0] 800387a: 6afa ldr r2, [r7, #44] @ 0x2c 800387c: 0151 lsls r1, r2, #5 800387e: 69fa ldr r2, [r7, #28] 8003880: 440a add r2, r1 8003882: f502 6230 add.w r2, r2, #2816 @ 0xb00 8003886: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 800388a: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 800388c: 6afb ldr r3, [r7, #44] @ 0x2c 800388e: 015a lsls r2, r3, #5 8003890: 69fb ldr r3, [r7, #28] 8003892: 4413 add r3, r2 8003894: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003898: 681b ldr r3, [r3, #0] 800389a: 6afa ldr r2, [r7, #44] @ 0x2c 800389c: 0151 lsls r1, r2, #5 800389e: 69fa ldr r2, [r7, #28] 80038a0: 440a add r2, r1 80038a2: f502 6230 add.w r2, r2, #2816 @ 0xb00 80038a6: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 80038aa: 6013 str r3, [r2, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80038ac: 6afb ldr r3, [r7, #44] @ 0x2c 80038ae: 3301 adds r3, #1 80038b0: 62fb str r3, [r7, #44] @ 0x2c 80038b2: 687b ldr r3, [r7, #4] 80038b4: 791b ldrb r3, [r3, #4] 80038b6: 461a mov r2, r3 80038b8: 6afb ldr r3, [r7, #44] @ 0x2c 80038ba: 4293 cmp r3, r2 80038bc: d3b2 bcc.n 8003824 } USBx_DEVICE->DAINTMSK |= 0x10001U; 80038be: 69fb ldr r3, [r7, #28] 80038c0: f503 6300 add.w r3, r3, #2048 @ 0x800 80038c4: 69db ldr r3, [r3, #28] 80038c6: 69fa ldr r2, [r7, #28] 80038c8: f502 6200 add.w r2, r2, #2048 @ 0x800 80038cc: f043 1301 orr.w r3, r3, #65537 @ 0x10001 80038d0: 61d3 str r3, [r2, #28] if (hpcd->Init.use_dedicated_ep1 != 0U) 80038d2: 687b ldr r3, [r7, #4] 80038d4: 7bdb ldrb r3, [r3, #15] 80038d6: 2b00 cmp r3, #0 80038d8: d016 beq.n 8003908 { USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | 80038da: 69fb ldr r3, [r7, #28] 80038dc: f503 6300 add.w r3, r3, #2048 @ 0x800 80038e0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80038e4: 69fa ldr r2, [r7, #28] 80038e6: f502 6200 add.w r2, r2, #2048 @ 0x800 80038ea: f043 030b orr.w r3, r3, #11 80038ee: f8c2 3084 str.w r3, [r2, #132] @ 0x84 USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM; USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | 80038f2: 69fb ldr r3, [r7, #28] 80038f4: f503 6300 add.w r3, r3, #2048 @ 0x800 80038f8: 6c5b ldr r3, [r3, #68] @ 0x44 80038fa: 69fa ldr r2, [r7, #28] 80038fc: f502 6200 add.w r2, r2, #2048 @ 0x800 8003900: f043 030b orr.w r3, r3, #11 8003904: 6453 str r3, [r2, #68] @ 0x44 8003906: e015 b.n 8003934 USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } else { USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | 8003908: 69fb ldr r3, [r7, #28] 800390a: f503 6300 add.w r3, r3, #2048 @ 0x800 800390e: 695b ldr r3, [r3, #20] 8003910: 69fa ldr r2, [r7, #28] 8003912: f502 6200 add.w r2, r2, #2048 @ 0x800 8003916: f443 5300 orr.w r3, r3, #8192 @ 0x2000 800391a: f043 032b orr.w r3, r3, #43 @ 0x2b 800391e: 6153 str r3, [r2, #20] USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM | USB_OTG_DOEPMSK_NAKM; USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | 8003920: 69fb ldr r3, [r7, #28] 8003922: f503 6300 add.w r3, r3, #2048 @ 0x800 8003926: 691b ldr r3, [r3, #16] 8003928: 69fa ldr r2, [r7, #28] 800392a: f502 6200 add.w r2, r2, #2048 @ 0x800 800392e: f043 030b orr.w r3, r3, #11 8003932: 6113 str r3, [r2, #16] USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; 8003934: 69fb ldr r3, [r7, #28] 8003936: f503 6300 add.w r3, r3, #2048 @ 0x800 800393a: 681b ldr r3, [r3, #0] 800393c: 69fa ldr r2, [r7, #28] 800393e: f502 6200 add.w r2, r2, #2048 @ 0x800 8003942: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 8003946: 6013 str r3, [r2, #0] /* setup EP0 to receive SETUP packets */ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 8003948: 687b ldr r3, [r7, #4] 800394a: 6818 ldr r0, [r3, #0] 800394c: 687b ldr r3, [r7, #4] 800394e: 7999 ldrb r1, [r3, #6] (uint8_t *)hpcd->Setup); 8003950: 687b ldr r3, [r7, #4] 8003952: f203 439c addw r3, r3, #1180 @ 0x49c (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 8003956: 461a mov r2, r3 8003958: f005 fa44 bl 8008de4 __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); 800395c: 687b ldr r3, [r7, #4] 800395e: 681b ldr r3, [r3, #0] 8003960: 695a ldr r2, [r3, #20] 8003962: 687b ldr r3, [r7, #4] 8003964: 681b ldr r3, [r3, #0] 8003966: f402 5280 and.w r2, r2, #4096 @ 0x1000 800396a: 615a str r2, [r3, #20] } /* Handle Enumeration done Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) 800396c: 687b ldr r3, [r7, #4] 800396e: 681b ldr r3, [r3, #0] 8003970: 4618 mov r0, r3 8003972: f005 f973 bl 8008c5c 8003976: 4603 mov r3, r0 8003978: f403 5300 and.w r3, r3, #8192 @ 0x2000 800397c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8003980: d123 bne.n 80039ca { (void)USB_ActivateSetup(hpcd->Instance); 8003982: 687b ldr r3, [r7, #4] 8003984: 681b ldr r3, [r3, #0] 8003986: 4618 mov r0, r3 8003988: f005 fa09 bl 8008d9e hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); 800398c: 687b ldr r3, [r7, #4] 800398e: 681b ldr r3, [r3, #0] 8003990: 4618 mov r0, r3 8003992: f004 fac0 bl 8007f16 8003996: 4603 mov r3, r0 8003998: 461a mov r2, r3 800399a: 687b ldr r3, [r7, #4] 800399c: 71da strb r2, [r3, #7] /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, 800399e: 687b ldr r3, [r7, #4] 80039a0: 681c ldr r4, [r3, #0] 80039a2: f000 fe8b bl 80046bc 80039a6: 4601 mov r1, r0 HAL_RCC_GetHCLKFreq(), (uint8_t)hpcd->Init.speed); 80039a8: 687b ldr r3, [r7, #4] 80039aa: 79db ldrb r3, [r3, #7] (void)USB_SetTurnaroundTime(hpcd->Instance, 80039ac: 461a mov r2, r3 80039ae: 4620 mov r0, r4 80039b0: f003 ffca bl 8007948 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 80039b4: 6878 ldr r0, [r7, #4] 80039b6: f007 fa34 bl 800ae22 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); 80039ba: 687b ldr r3, [r7, #4] 80039bc: 681b ldr r3, [r3, #0] 80039be: 695a ldr r2, [r3, #20] 80039c0: 687b ldr r3, [r7, #4] 80039c2: 681b ldr r3, [r3, #0] 80039c4: f402 5200 and.w r2, r2, #8192 @ 0x2000 80039c8: 615a str r2, [r3, #20] } /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) 80039ca: 687b ldr r3, [r7, #4] 80039cc: 681b ldr r3, [r3, #0] 80039ce: 4618 mov r0, r3 80039d0: f005 f944 bl 8008c5c 80039d4: 4603 mov r3, r0 80039d6: f003 0308 and.w r3, r3, #8 80039da: 2b08 cmp r3, #8 80039dc: d10a bne.n 80039f4 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 80039de: 6878 ldr r0, [r7, #4] 80039e0: f007 fa11 bl 800ae06 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); 80039e4: 687b ldr r3, [r7, #4] 80039e6: 681b ldr r3, [r3, #0] 80039e8: 695a ldr r2, [r3, #20] 80039ea: 687b ldr r3, [r7, #4] 80039ec: 681b ldr r3, [r3, #0] 80039ee: f002 0208 and.w r2, r2, #8 80039f2: 615a str r2, [r3, #20] } /* Handle Global OUT NAK effective Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) 80039f4: 687b ldr r3, [r7, #4] 80039f6: 681b ldr r3, [r3, #0] 80039f8: 4618 mov r0, r3 80039fa: f005 f92f bl 8008c5c 80039fe: 4603 mov r3, r0 8003a00: f003 0380 and.w r3, r3, #128 @ 0x80 8003a04: 2b80 cmp r3, #128 @ 0x80 8003a06: d123 bne.n 8003a50 { USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; 8003a08: 6a3b ldr r3, [r7, #32] 8003a0a: 699b ldr r3, [r3, #24] 8003a0c: f023 0280 bic.w r2, r3, #128 @ 0x80 8003a10: 6a3b ldr r3, [r7, #32] 8003a12: 619a str r2, [r3, #24] for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003a14: 2301 movs r3, #1 8003a16: 627b str r3, [r7, #36] @ 0x24 8003a18: e014 b.n 8003a44 { if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) 8003a1a: 6879 ldr r1, [r7, #4] 8003a1c: 6a7a ldr r2, [r7, #36] @ 0x24 8003a1e: 4613 mov r3, r2 8003a20: 00db lsls r3, r3, #3 8003a22: 4413 add r3, r2 8003a24: 009b lsls r3, r3, #2 8003a26: 440b add r3, r1 8003a28: f203 2357 addw r3, r3, #599 @ 0x257 8003a2c: 781b ldrb r3, [r3, #0] 8003a2e: 2b01 cmp r3, #1 8003a30: d105 bne.n 8003a3e { /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); 8003a32: 6a7b ldr r3, [r7, #36] @ 0x24 8003a34: b2db uxtb r3, r3 8003a36: 4619 mov r1, r3 8003a38: 6878 ldr r0, [r7, #4] 8003a3a: f000 faf2 bl 8004022 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003a3e: 6a7b ldr r3, [r7, #36] @ 0x24 8003a40: 3301 adds r3, #1 8003a42: 627b str r3, [r7, #36] @ 0x24 8003a44: 687b ldr r3, [r7, #4] 8003a46: 791b ldrb r3, [r3, #4] 8003a48: 461a mov r2, r3 8003a4a: 6a7b ldr r3, [r7, #36] @ 0x24 8003a4c: 4293 cmp r3, r2 8003a4e: d3e4 bcc.n 8003a1a } } } /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) 8003a50: 687b ldr r3, [r7, #4] 8003a52: 681b ldr r3, [r3, #0] 8003a54: 4618 mov r0, r3 8003a56: f005 f901 bl 8008c5c 8003a5a: 4603 mov r3, r0 8003a5c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8003a60: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8003a64: d13c bne.n 8003ae0 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003a66: 2301 movs r3, #1 8003a68: 627b str r3, [r7, #36] @ 0x24 8003a6a: e02b b.n 8003ac4 { RegVal = USBx_INEP(epnum)->DIEPCTL; 8003a6c: 6a7b ldr r3, [r7, #36] @ 0x24 8003a6e: 015a lsls r2, r3, #5 8003a70: 69fb ldr r3, [r7, #28] 8003a72: 4413 add r3, r2 8003a74: f503 6310 add.w r3, r3, #2304 @ 0x900 8003a78: 681b ldr r3, [r3, #0] 8003a7a: 61bb str r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 8003a7c: 6879 ldr r1, [r7, #4] 8003a7e: 6a7a ldr r2, [r7, #36] @ 0x24 8003a80: 4613 mov r3, r2 8003a82: 00db lsls r3, r3, #3 8003a84: 4413 add r3, r2 8003a86: 009b lsls r3, r3, #2 8003a88: 440b add r3, r1 8003a8a: 3318 adds r3, #24 8003a8c: 781b ldrb r3, [r3, #0] 8003a8e: 2b01 cmp r3, #1 8003a90: d115 bne.n 8003abe ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) 8003a92: 69bb ldr r3, [r7, #24] if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && 8003a94: 2b00 cmp r3, #0 8003a96: da12 bge.n 8003abe { hpcd->IN_ep[epnum].is_iso_incomplete = 1U; 8003a98: 6879 ldr r1, [r7, #4] 8003a9a: 6a7a ldr r2, [r7, #36] @ 0x24 8003a9c: 4613 mov r3, r2 8003a9e: 00db lsls r3, r3, #3 8003aa0: 4413 add r3, r2 8003aa2: 009b lsls r3, r3, #2 8003aa4: 440b add r3, r1 8003aa6: 3317 adds r3, #23 8003aa8: 2201 movs r2, #1 8003aaa: 701a strb r2, [r3, #0] /* Abort current transaction and disable the EP */ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); 8003aac: 6a7b ldr r3, [r7, #36] @ 0x24 8003aae: b2db uxtb r3, r3 8003ab0: f063 037f orn r3, r3, #127 @ 0x7f 8003ab4: b2db uxtb r3, r3 8003ab6: 4619 mov r1, r3 8003ab8: 6878 ldr r0, [r7, #4] 8003aba: f000 fab2 bl 8004022 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003abe: 6a7b ldr r3, [r7, #36] @ 0x24 8003ac0: 3301 adds r3, #1 8003ac2: 627b str r3, [r7, #36] @ 0x24 8003ac4: 687b ldr r3, [r7, #4] 8003ac6: 791b ldrb r3, [r3, #4] 8003ac8: 461a mov r2, r3 8003aca: 6a7b ldr r3, [r7, #36] @ 0x24 8003acc: 4293 cmp r3, r2 8003ace: d3cd bcc.n 8003a6c } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); 8003ad0: 687b ldr r3, [r7, #4] 8003ad2: 681b ldr r3, [r3, #0] 8003ad4: 695a ldr r2, [r3, #20] 8003ad6: 687b ldr r3, [r7, #4] 8003ad8: 681b ldr r3, [r3, #0] 8003ada: f402 1280 and.w r2, r2, #1048576 @ 0x100000 8003ade: 615a str r2, [r3, #20] } /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 8003ae0: 687b ldr r3, [r7, #4] 8003ae2: 681b ldr r3, [r3, #0] 8003ae4: 4618 mov r0, r3 8003ae6: f005 f8b9 bl 8008c5c 8003aea: 4603 mov r3, r0 8003aec: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8003af0: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8003af4: d156 bne.n 8003ba4 { for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003af6: 2301 movs r3, #1 8003af8: 627b str r3, [r7, #36] @ 0x24 8003afa: e045 b.n 8003b88 { RegVal = USBx_OUTEP(epnum)->DOEPCTL; 8003afc: 6a7b ldr r3, [r7, #36] @ 0x24 8003afe: 015a lsls r2, r3, #5 8003b00: 69fb ldr r3, [r7, #28] 8003b02: 4413 add r3, r2 8003b04: f503 6330 add.w r3, r3, #2816 @ 0xb00 8003b08: 681b ldr r3, [r3, #0] 8003b0a: 61bb str r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 8003b0c: 6879 ldr r1, [r7, #4] 8003b0e: 6a7a ldr r2, [r7, #36] @ 0x24 8003b10: 4613 mov r3, r2 8003b12: 00db lsls r3, r3, #3 8003b14: 4413 add r3, r2 8003b16: 009b lsls r3, r3, #2 8003b18: 440b add r3, r1 8003b1a: f503 7316 add.w r3, r3, #600 @ 0x258 8003b1e: 781b ldrb r3, [r3, #0] 8003b20: 2b01 cmp r3, #1 8003b22: d12e bne.n 8003b82 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 8003b24: 69bb ldr r3, [r7, #24] if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && 8003b26: 2b00 cmp r3, #0 8003b28: da2b bge.n 8003b82 (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) 8003b2a: 69bb ldr r3, [r7, #24] 8003b2c: 0c1a lsrs r2, r3, #16 8003b2e: 687b ldr r3, [r7, #4] 8003b30: f8d3 34d4 ldr.w r3, [r3, #1236] @ 0x4d4 8003b34: 4053 eors r3, r2 8003b36: f003 0301 and.w r3, r3, #1 ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && 8003b3a: 2b00 cmp r3, #0 8003b3c: d121 bne.n 8003b82 { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; 8003b3e: 6879 ldr r1, [r7, #4] 8003b40: 6a7a ldr r2, [r7, #36] @ 0x24 8003b42: 4613 mov r3, r2 8003b44: 00db lsls r3, r3, #3 8003b46: 4413 add r3, r2 8003b48: 009b lsls r3, r3, #2 8003b4a: 440b add r3, r1 8003b4c: f203 2357 addw r3, r3, #599 @ 0x257 8003b50: 2201 movs r2, #1 8003b52: 701a strb r2, [r3, #0] USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; 8003b54: 6a3b ldr r3, [r7, #32] 8003b56: 699b ldr r3, [r3, #24] 8003b58: f043 0280 orr.w r2, r3, #128 @ 0x80 8003b5c: 6a3b ldr r3, [r7, #32] 8003b5e: 619a str r2, [r3, #24] if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) 8003b60: 6a3b ldr r3, [r7, #32] 8003b62: 695b ldr r3, [r3, #20] 8003b64: f003 0380 and.w r3, r3, #128 @ 0x80 8003b68: 2b00 cmp r3, #0 8003b6a: d10a bne.n 8003b82 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; 8003b6c: 69fb ldr r3, [r7, #28] 8003b6e: f503 6300 add.w r3, r3, #2048 @ 0x800 8003b72: 685b ldr r3, [r3, #4] 8003b74: 69fa ldr r2, [r7, #28] 8003b76: f502 6200 add.w r2, r2, #2048 @ 0x800 8003b7a: f443 7300 orr.w r3, r3, #512 @ 0x200 8003b7e: 6053 str r3, [r2, #4] break; 8003b80: e008 b.n 8003b94 for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) 8003b82: 6a7b ldr r3, [r7, #36] @ 0x24 8003b84: 3301 adds r3, #1 8003b86: 627b str r3, [r7, #36] @ 0x24 8003b88: 687b ldr r3, [r7, #4] 8003b8a: 791b ldrb r3, [r3, #4] 8003b8c: 461a mov r2, r3 8003b8e: 6a7b ldr r3, [r7, #36] @ 0x24 8003b90: 4293 cmp r3, r2 8003b92: d3b3 bcc.n 8003afc } } } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 8003b94: 687b ldr r3, [r7, #4] 8003b96: 681b ldr r3, [r3, #0] 8003b98: 695a ldr r2, [r3, #20] 8003b9a: 687b ldr r3, [r7, #4] 8003b9c: 681b ldr r3, [r3, #0] 8003b9e: f402 1200 and.w r2, r2, #2097152 @ 0x200000 8003ba2: 615a str r2, [r3, #20] } /* Handle Connection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) 8003ba4: 687b ldr r3, [r7, #4] 8003ba6: 681b ldr r3, [r3, #0] 8003ba8: 4618 mov r0, r3 8003baa: f005 f857 bl 8008c5c 8003bae: 4603 mov r3, r0 8003bb0: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8003bb4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8003bb8: d10a bne.n 8003bd0 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ConnectCallback(hpcd); #else HAL_PCD_ConnectCallback(hpcd); 8003bba: 6878 ldr r0, [r7, #4] 8003bbc: f007 f9b2 bl 800af24 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); 8003bc0: 687b ldr r3, [r7, #4] 8003bc2: 681b ldr r3, [r3, #0] 8003bc4: 695a ldr r2, [r3, #20] 8003bc6: 687b ldr r3, [r7, #4] 8003bc8: 681b ldr r3, [r3, #0] 8003bca: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 8003bce: 615a str r2, [r3, #20] } /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) 8003bd0: 687b ldr r3, [r7, #4] 8003bd2: 681b ldr r3, [r3, #0] 8003bd4: 4618 mov r0, r3 8003bd6: f005 f841 bl 8008c5c 8003bda: 4603 mov r3, r0 8003bdc: f003 0304 and.w r3, r3, #4 8003be0: 2b04 cmp r3, #4 8003be2: d115 bne.n 8003c10 { RegVal = hpcd->Instance->GOTGINT; 8003be4: 687b ldr r3, [r7, #4] 8003be6: 681b ldr r3, [r3, #0] 8003be8: 685b ldr r3, [r3, #4] 8003bea: 61bb str r3, [r7, #24] if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) 8003bec: 69bb ldr r3, [r7, #24] 8003bee: f003 0304 and.w r3, r3, #4 8003bf2: 2b00 cmp r3, #0 8003bf4: d002 beq.n 8003bfc { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); #else HAL_PCD_DisconnectCallback(hpcd); 8003bf6: 6878 ldr r0, [r7, #4] 8003bf8: f007 f9a2 bl 800af40 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= RegVal; 8003bfc: 687b ldr r3, [r7, #4] 8003bfe: 681b ldr r3, [r3, #0] 8003c00: 6859 ldr r1, [r3, #4] 8003c02: 687b ldr r3, [r7, #4] 8003c04: 681b ldr r3, [r3, #0] 8003c06: 69ba ldr r2, [r7, #24] 8003c08: 430a orrs r2, r1 8003c0a: 605a str r2, [r3, #4] 8003c0c: e000 b.n 8003c10 return; 8003c0e: bf00 nop } } } 8003c10: 3734 adds r7, #52 @ 0x34 8003c12: 46bd mov sp, r7 8003c14: bd90 pop {r4, r7, pc} 08003c16 : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 8003c16: b580 push {r7, lr} 8003c18: b082 sub sp, #8 8003c1a: af00 add r7, sp, #0 8003c1c: 6078 str r0, [r7, #4] 8003c1e: 460b mov r3, r1 8003c20: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 8003c22: 687b ldr r3, [r7, #4] 8003c24: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003c28: 2b01 cmp r3, #1 8003c2a: d101 bne.n 8003c30 8003c2c: 2302 movs r3, #2 8003c2e: e012 b.n 8003c56 8003c30: 687b ldr r3, [r7, #4] 8003c32: 2201 movs r2, #1 8003c34: f883 2494 strb.w r2, [r3, #1172] @ 0x494 hpcd->USB_Address = address; 8003c38: 687b ldr r3, [r7, #4] 8003c3a: 78fa ldrb r2, [r7, #3] 8003c3c: 745a strb r2, [r3, #17] (void)USB_SetDevAddress(hpcd->Instance, address); 8003c3e: 687b ldr r3, [r7, #4] 8003c40: 681b ldr r3, [r3, #0] 8003c42: 78fa ldrb r2, [r7, #3] 8003c44: 4611 mov r1, r2 8003c46: 4618 mov r0, r3 8003c48: f004 ffa0 bl 8008b8c __HAL_UNLOCK(hpcd); 8003c4c: 687b ldr r3, [r7, #4] 8003c4e: 2200 movs r2, #0 8003c50: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003c54: 2300 movs r3, #0 } 8003c56: 4618 mov r0, r3 8003c58: 3708 adds r7, #8 8003c5a: 46bd mov sp, r7 8003c5c: bd80 pop {r7, pc} 08003c5e : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 8003c5e: b580 push {r7, lr} 8003c60: b084 sub sp, #16 8003c62: af00 add r7, sp, #0 8003c64: 6078 str r0, [r7, #4] 8003c66: 4608 mov r0, r1 8003c68: 4611 mov r1, r2 8003c6a: 461a mov r2, r3 8003c6c: 4603 mov r3, r0 8003c6e: 70fb strb r3, [r7, #3] 8003c70: 460b mov r3, r1 8003c72: 803b strh r3, [r7, #0] 8003c74: 4613 mov r3, r2 8003c76: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 8003c78: 2300 movs r3, #0 8003c7a: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8003c7c: f997 3003 ldrsb.w r3, [r7, #3] 8003c80: 2b00 cmp r3, #0 8003c82: da0f bge.n 8003ca4 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003c84: 78fb ldrb r3, [r7, #3] 8003c86: f003 020f and.w r2, r3, #15 8003c8a: 4613 mov r3, r2 8003c8c: 00db lsls r3, r3, #3 8003c8e: 4413 add r3, r2 8003c90: 009b lsls r3, r3, #2 8003c92: 3310 adds r3, #16 8003c94: 687a ldr r2, [r7, #4] 8003c96: 4413 add r3, r2 8003c98: 3304 adds r3, #4 8003c9a: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003c9c: 68fb ldr r3, [r7, #12] 8003c9e: 2201 movs r2, #1 8003ca0: 705a strb r2, [r3, #1] 8003ca2: e00f b.n 8003cc4 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003ca4: 78fb ldrb r3, [r7, #3] 8003ca6: f003 020f and.w r2, r3, #15 8003caa: 4613 mov r3, r2 8003cac: 00db lsls r3, r3, #3 8003cae: 4413 add r3, r2 8003cb0: 009b lsls r3, r3, #2 8003cb2: f503 7314 add.w r3, r3, #592 @ 0x250 8003cb6: 687a ldr r2, [r7, #4] 8003cb8: 4413 add r3, r2 8003cba: 3304 adds r3, #4 8003cbc: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003cbe: 68fb ldr r3, [r7, #12] 8003cc0: 2200 movs r2, #0 8003cc2: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8003cc4: 78fb ldrb r3, [r7, #3] 8003cc6: f003 030f and.w r3, r3, #15 8003cca: b2da uxtb r2, r3 8003ccc: 68fb ldr r3, [r7, #12] 8003cce: 701a strb r2, [r3, #0] ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; 8003cd0: 883b ldrh r3, [r7, #0] 8003cd2: f3c3 020a ubfx r2, r3, #0, #11 8003cd6: 68fb ldr r3, [r7, #12] 8003cd8: 609a str r2, [r3, #8] ep->type = ep_type; 8003cda: 68fb ldr r3, [r7, #12] 8003cdc: 78ba ldrb r2, [r7, #2] 8003cde: 711a strb r2, [r3, #4] if (ep->is_in != 0U) 8003ce0: 68fb ldr r3, [r7, #12] 8003ce2: 785b ldrb r3, [r3, #1] 8003ce4: 2b00 cmp r3, #0 8003ce6: d004 beq.n 8003cf2 { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; 8003ce8: 68fb ldr r3, [r7, #12] 8003cea: 781b ldrb r3, [r3, #0] 8003cec: 461a mov r2, r3 8003cee: 68fb ldr r3, [r7, #12] 8003cf0: 835a strh r2, [r3, #26] } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 8003cf2: 78bb ldrb r3, [r7, #2] 8003cf4: 2b02 cmp r3, #2 8003cf6: d102 bne.n 8003cfe { ep->data_pid_start = 0U; 8003cf8: 68fb ldr r3, [r7, #12] 8003cfa: 2200 movs r2, #0 8003cfc: 715a strb r2, [r3, #5] } __HAL_LOCK(hpcd); 8003cfe: 687b ldr r3, [r7, #4] 8003d00: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003d04: 2b01 cmp r3, #1 8003d06: d101 bne.n 8003d0c 8003d08: 2302 movs r3, #2 8003d0a: e00e b.n 8003d2a 8003d0c: 687b ldr r3, [r7, #4] 8003d0e: 2201 movs r2, #1 8003d10: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_ActivateEndpoint(hpcd->Instance, ep); 8003d14: 687b ldr r3, [r7, #4] 8003d16: 681b ldr r3, [r3, #0] 8003d18: 68f9 ldr r1, [r7, #12] 8003d1a: 4618 mov r0, r3 8003d1c: f004 f920 bl 8007f60 __HAL_UNLOCK(hpcd); 8003d20: 687b ldr r3, [r7, #4] 8003d22: 2200 movs r2, #0 8003d24: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return ret; 8003d28: 7afb ldrb r3, [r7, #11] } 8003d2a: 4618 mov r0, r3 8003d2c: 3710 adds r7, #16 8003d2e: 46bd mov sp, r7 8003d30: bd80 pop {r7, pc} 08003d32 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003d32: b580 push {r7, lr} 8003d34: b084 sub sp, #16 8003d36: af00 add r7, sp, #0 8003d38: 6078 str r0, [r7, #4] 8003d3a: 460b mov r3, r1 8003d3c: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8003d3e: f997 3003 ldrsb.w r3, [r7, #3] 8003d42: 2b00 cmp r3, #0 8003d44: da0f bge.n 8003d66 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003d46: 78fb ldrb r3, [r7, #3] 8003d48: f003 020f and.w r2, r3, #15 8003d4c: 4613 mov r3, r2 8003d4e: 00db lsls r3, r3, #3 8003d50: 4413 add r3, r2 8003d52: 009b lsls r3, r3, #2 8003d54: 3310 adds r3, #16 8003d56: 687a ldr r2, [r7, #4] 8003d58: 4413 add r3, r2 8003d5a: 3304 adds r3, #4 8003d5c: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003d5e: 68fb ldr r3, [r7, #12] 8003d60: 2201 movs r2, #1 8003d62: 705a strb r2, [r3, #1] 8003d64: e00f b.n 8003d86 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003d66: 78fb ldrb r3, [r7, #3] 8003d68: f003 020f and.w r2, r3, #15 8003d6c: 4613 mov r3, r2 8003d6e: 00db lsls r3, r3, #3 8003d70: 4413 add r3, r2 8003d72: 009b lsls r3, r3, #2 8003d74: f503 7314 add.w r3, r3, #592 @ 0x250 8003d78: 687a ldr r2, [r7, #4] 8003d7a: 4413 add r3, r2 8003d7c: 3304 adds r3, #4 8003d7e: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003d80: 68fb ldr r3, [r7, #12] 8003d82: 2200 movs r2, #0 8003d84: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8003d86: 78fb ldrb r3, [r7, #3] 8003d88: f003 030f and.w r3, r3, #15 8003d8c: b2da uxtb r2, r3 8003d8e: 68fb ldr r3, [r7, #12] 8003d90: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003d92: 687b ldr r3, [r7, #4] 8003d94: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003d98: 2b01 cmp r3, #1 8003d9a: d101 bne.n 8003da0 8003d9c: 2302 movs r3, #2 8003d9e: e00e b.n 8003dbe 8003da0: 687b ldr r3, [r7, #4] 8003da2: 2201 movs r2, #1 8003da4: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 8003da8: 687b ldr r3, [r7, #4] 8003daa: 681b ldr r3, [r3, #0] 8003dac: 68f9 ldr r1, [r7, #12] 8003dae: 4618 mov r0, r3 8003db0: f004 f95e bl 8008070 __HAL_UNLOCK(hpcd); 8003db4: 687b ldr r3, [r7, #4] 8003db6: 2200 movs r2, #0 8003db8: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003dbc: 2300 movs r3, #0 } 8003dbe: 4618 mov r0, r3 8003dc0: 3710 adds r7, #16 8003dc2: 46bd mov sp, r7 8003dc4: bd80 pop {r7, pc} 08003dc6 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8003dc6: b580 push {r7, lr} 8003dc8: b086 sub sp, #24 8003dca: af00 add r7, sp, #0 8003dcc: 60f8 str r0, [r7, #12] 8003dce: 607a str r2, [r7, #4] 8003dd0: 603b str r3, [r7, #0] 8003dd2: 460b mov r3, r1 8003dd4: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003dd6: 7afb ldrb r3, [r7, #11] 8003dd8: f003 020f and.w r2, r3, #15 8003ddc: 4613 mov r3, r2 8003dde: 00db lsls r3, r3, #3 8003de0: 4413 add r3, r2 8003de2: 009b lsls r3, r3, #2 8003de4: f503 7314 add.w r3, r3, #592 @ 0x250 8003de8: 68fa ldr r2, [r7, #12] 8003dea: 4413 add r3, r2 8003dec: 3304 adds r3, #4 8003dee: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003df0: 697b ldr r3, [r7, #20] 8003df2: 687a ldr r2, [r7, #4] 8003df4: 60da str r2, [r3, #12] ep->xfer_len = len; 8003df6: 697b ldr r3, [r7, #20] 8003df8: 683a ldr r2, [r7, #0] 8003dfa: 611a str r2, [r3, #16] ep->xfer_count = 0U; 8003dfc: 697b ldr r3, [r7, #20] 8003dfe: 2200 movs r2, #0 8003e00: 615a str r2, [r3, #20] ep->is_in = 0U; 8003e02: 697b ldr r3, [r7, #20] 8003e04: 2200 movs r2, #0 8003e06: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8003e08: 7afb ldrb r3, [r7, #11] 8003e0a: f003 030f and.w r3, r3, #15 8003e0e: b2da uxtb r2, r3 8003e10: 697b ldr r3, [r7, #20] 8003e12: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003e14: 68fb ldr r3, [r7, #12] 8003e16: 799b ldrb r3, [r3, #6] 8003e18: 2b01 cmp r3, #1 8003e1a: d102 bne.n 8003e22 { ep->dma_addr = (uint32_t)pBuf; 8003e1c: 687a ldr r2, [r7, #4] 8003e1e: 697b ldr r3, [r7, #20] 8003e20: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003e22: 68fb ldr r3, [r7, #12] 8003e24: 6818 ldr r0, [r3, #0] 8003e26: 68fb ldr r3, [r7, #12] 8003e28: 799b ldrb r3, [r3, #6] 8003e2a: 461a mov r2, r3 8003e2c: 6979 ldr r1, [r7, #20] 8003e2e: f004 f9fb bl 8008228 return HAL_OK; 8003e32: 2300 movs r3, #0 } 8003e34: 4618 mov r0, r3 8003e36: 3718 adds r7, #24 8003e38: 46bd mov sp, r7 8003e3a: bd80 pop {r7, pc} 08003e3c : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8003e3c: b580 push {r7, lr} 8003e3e: b086 sub sp, #24 8003e40: af00 add r7, sp, #0 8003e42: 60f8 str r0, [r7, #12] 8003e44: 607a str r2, [r7, #4] 8003e46: 603b str r3, [r7, #0] 8003e48: 460b mov r3, r1 8003e4a: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003e4c: 7afb ldrb r3, [r7, #11] 8003e4e: f003 020f and.w r2, r3, #15 8003e52: 4613 mov r3, r2 8003e54: 00db lsls r3, r3, #3 8003e56: 4413 add r3, r2 8003e58: 009b lsls r3, r3, #2 8003e5a: 3310 adds r3, #16 8003e5c: 68fa ldr r2, [r7, #12] 8003e5e: 4413 add r3, r2 8003e60: 3304 adds r3, #4 8003e62: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8003e64: 697b ldr r3, [r7, #20] 8003e66: 687a ldr r2, [r7, #4] 8003e68: 60da str r2, [r3, #12] ep->xfer_len = len; 8003e6a: 697b ldr r3, [r7, #20] 8003e6c: 683a ldr r2, [r7, #0] 8003e6e: 611a str r2, [r3, #16] ep->xfer_count = 0U; 8003e70: 697b ldr r3, [r7, #20] 8003e72: 2200 movs r2, #0 8003e74: 615a str r2, [r3, #20] ep->is_in = 1U; 8003e76: 697b ldr r3, [r7, #20] 8003e78: 2201 movs r2, #1 8003e7a: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8003e7c: 7afb ldrb r3, [r7, #11] 8003e7e: f003 030f and.w r3, r3, #15 8003e82: b2da uxtb r2, r3 8003e84: 697b ldr r3, [r7, #20] 8003e86: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8003e88: 68fb ldr r3, [r7, #12] 8003e8a: 799b ldrb r3, [r3, #6] 8003e8c: 2b01 cmp r3, #1 8003e8e: d102 bne.n 8003e96 { ep->dma_addr = (uint32_t)pBuf; 8003e90: 687a ldr r2, [r7, #4] 8003e92: 697b ldr r3, [r7, #20] 8003e94: 61da str r2, [r3, #28] } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8003e96: 68fb ldr r3, [r7, #12] 8003e98: 6818 ldr r0, [r3, #0] 8003e9a: 68fb ldr r3, [r7, #12] 8003e9c: 799b ldrb r3, [r3, #6] 8003e9e: 461a mov r2, r3 8003ea0: 6979 ldr r1, [r7, #20] 8003ea2: f004 f9c1 bl 8008228 return HAL_OK; 8003ea6: 2300 movs r3, #0 } 8003ea8: 4618 mov r0, r3 8003eaa: 3718 adds r7, #24 8003eac: 46bd mov sp, r7 8003eae: bd80 pop {r7, pc} 08003eb0 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003eb0: b580 push {r7, lr} 8003eb2: b084 sub sp, #16 8003eb4: af00 add r7, sp, #0 8003eb6: 6078 str r0, [r7, #4] 8003eb8: 460b mov r3, r1 8003eba: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 8003ebc: 78fb ldrb r3, [r7, #3] 8003ebe: f003 030f and.w r3, r3, #15 8003ec2: 687a ldr r2, [r7, #4] 8003ec4: 7912 ldrb r2, [r2, #4] 8003ec6: 4293 cmp r3, r2 8003ec8: d901 bls.n 8003ece { return HAL_ERROR; 8003eca: 2301 movs r3, #1 8003ecc: e04f b.n 8003f6e } if ((0x80U & ep_addr) == 0x80U) 8003ece: f997 3003 ldrsb.w r3, [r7, #3] 8003ed2: 2b00 cmp r3, #0 8003ed4: da0f bge.n 8003ef6 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003ed6: 78fb ldrb r3, [r7, #3] 8003ed8: f003 020f and.w r2, r3, #15 8003edc: 4613 mov r3, r2 8003ede: 00db lsls r3, r3, #3 8003ee0: 4413 add r3, r2 8003ee2: 009b lsls r3, r3, #2 8003ee4: 3310 adds r3, #16 8003ee6: 687a ldr r2, [r7, #4] 8003ee8: 4413 add r3, r2 8003eea: 3304 adds r3, #4 8003eec: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003eee: 68fb ldr r3, [r7, #12] 8003ef0: 2201 movs r2, #1 8003ef2: 705a strb r2, [r3, #1] 8003ef4: e00d b.n 8003f12 } else { ep = &hpcd->OUT_ep[ep_addr]; 8003ef6: 78fa ldrb r2, [r7, #3] 8003ef8: 4613 mov r3, r2 8003efa: 00db lsls r3, r3, #3 8003efc: 4413 add r3, r2 8003efe: 009b lsls r3, r3, #2 8003f00: f503 7314 add.w r3, r3, #592 @ 0x250 8003f04: 687a ldr r2, [r7, #4] 8003f06: 4413 add r3, r2 8003f08: 3304 adds r3, #4 8003f0a: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003f0c: 68fb ldr r3, [r7, #12] 8003f0e: 2200 movs r2, #0 8003f10: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8003f12: 68fb ldr r3, [r7, #12] 8003f14: 2201 movs r2, #1 8003f16: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003f18: 78fb ldrb r3, [r7, #3] 8003f1a: f003 030f and.w r3, r3, #15 8003f1e: b2da uxtb r2, r3 8003f20: 68fb ldr r3, [r7, #12] 8003f22: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003f24: 687b ldr r3, [r7, #4] 8003f26: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003f2a: 2b01 cmp r3, #1 8003f2c: d101 bne.n 8003f32 8003f2e: 2302 movs r3, #2 8003f30: e01d b.n 8003f6e 8003f32: 687b ldr r3, [r7, #4] 8003f34: 2201 movs r2, #1 8003f36: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPSetStall(hpcd->Instance, ep); 8003f3a: 687b ldr r3, [r7, #4] 8003f3c: 681b ldr r3, [r3, #0] 8003f3e: 68f9 ldr r1, [r7, #12] 8003f40: 4618 mov r0, r3 8003f42: f004 fd4f bl 80089e4 if ((ep_addr & EP_ADDR_MSK) == 0U) 8003f46: 78fb ldrb r3, [r7, #3] 8003f48: f003 030f and.w r3, r3, #15 8003f4c: 2b00 cmp r3, #0 8003f4e: d109 bne.n 8003f64 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); 8003f50: 687b ldr r3, [r7, #4] 8003f52: 6818 ldr r0, [r3, #0] 8003f54: 687b ldr r3, [r7, #4] 8003f56: 7999 ldrb r1, [r3, #6] 8003f58: 687b ldr r3, [r7, #4] 8003f5a: f203 439c addw r3, r3, #1180 @ 0x49c 8003f5e: 461a mov r2, r3 8003f60: f004 ff40 bl 8008de4 } __HAL_UNLOCK(hpcd); 8003f64: 687b ldr r3, [r7, #4] 8003f66: 2200 movs r2, #0 8003f68: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8003f6c: 2300 movs r3, #0 } 8003f6e: 4618 mov r0, r3 8003f70: 3710 adds r7, #16 8003f72: 46bd mov sp, r7 8003f74: bd80 pop {r7, pc} 08003f76 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8003f76: b580 push {r7, lr} 8003f78: b084 sub sp, #16 8003f7a: af00 add r7, sp, #0 8003f7c: 6078 str r0, [r7, #4] 8003f7e: 460b mov r3, r1 8003f80: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8003f82: 78fb ldrb r3, [r7, #3] 8003f84: f003 030f and.w r3, r3, #15 8003f88: 687a ldr r2, [r7, #4] 8003f8a: 7912 ldrb r2, [r2, #4] 8003f8c: 4293 cmp r3, r2 8003f8e: d901 bls.n 8003f94 { return HAL_ERROR; 8003f90: 2301 movs r3, #1 8003f92: e042 b.n 800401a } if ((0x80U & ep_addr) == 0x80U) 8003f94: f997 3003 ldrsb.w r3, [r7, #3] 8003f98: 2b00 cmp r3, #0 8003f9a: da0f bge.n 8003fbc { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8003f9c: 78fb ldrb r3, [r7, #3] 8003f9e: f003 020f and.w r2, r3, #15 8003fa2: 4613 mov r3, r2 8003fa4: 00db lsls r3, r3, #3 8003fa6: 4413 add r3, r2 8003fa8: 009b lsls r3, r3, #2 8003faa: 3310 adds r3, #16 8003fac: 687a ldr r2, [r7, #4] 8003fae: 4413 add r3, r2 8003fb0: 3304 adds r3, #4 8003fb2: 60fb str r3, [r7, #12] ep->is_in = 1U; 8003fb4: 68fb ldr r3, [r7, #12] 8003fb6: 2201 movs r2, #1 8003fb8: 705a strb r2, [r3, #1] 8003fba: e00f b.n 8003fdc } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8003fbc: 78fb ldrb r3, [r7, #3] 8003fbe: f003 020f and.w r2, r3, #15 8003fc2: 4613 mov r3, r2 8003fc4: 00db lsls r3, r3, #3 8003fc6: 4413 add r3, r2 8003fc8: 009b lsls r3, r3, #2 8003fca: f503 7314 add.w r3, r3, #592 @ 0x250 8003fce: 687a ldr r2, [r7, #4] 8003fd0: 4413 add r3, r2 8003fd2: 3304 adds r3, #4 8003fd4: 60fb str r3, [r7, #12] ep->is_in = 0U; 8003fd6: 68fb ldr r3, [r7, #12] 8003fd8: 2200 movs r2, #0 8003fda: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8003fdc: 68fb ldr r3, [r7, #12] 8003fde: 2200 movs r2, #0 8003fe0: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8003fe2: 78fb ldrb r3, [r7, #3] 8003fe4: f003 030f and.w r3, r3, #15 8003fe8: b2da uxtb r2, r3 8003fea: 68fb ldr r3, [r7, #12] 8003fec: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8003fee: 687b ldr r3, [r7, #4] 8003ff0: f893 3494 ldrb.w r3, [r3, #1172] @ 0x494 8003ff4: 2b01 cmp r3, #1 8003ff6: d101 bne.n 8003ffc 8003ff8: 2302 movs r3, #2 8003ffa: e00e b.n 800401a 8003ffc: 687b ldr r3, [r7, #4] 8003ffe: 2201 movs r2, #1 8004000: f883 2494 strb.w r2, [r3, #1172] @ 0x494 (void)USB_EPClearStall(hpcd->Instance, ep); 8004004: 687b ldr r3, [r7, #4] 8004006: 681b ldr r3, [r3, #0] 8004008: 68f9 ldr r1, [r7, #12] 800400a: 4618 mov r0, r3 800400c: f004 fd58 bl 8008ac0 __HAL_UNLOCK(hpcd); 8004010: 687b ldr r3, [r7, #4] 8004012: 2200 movs r2, #0 8004014: f883 2494 strb.w r2, [r3, #1172] @ 0x494 return HAL_OK; 8004018: 2300 movs r3, #0 } 800401a: 4618 mov r0, r3 800401c: 3710 adds r7, #16 800401e: 46bd mov sp, r7 8004020: bd80 pop {r7, pc} 08004022 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8004022: b580 push {r7, lr} 8004024: b084 sub sp, #16 8004026: af00 add r7, sp, #0 8004028: 6078 str r0, [r7, #4] 800402a: 460b mov r3, r1 800402c: 70fb strb r3, [r7, #3] HAL_StatusTypeDef ret; PCD_EPTypeDef *ep; if ((0x80U & ep_addr) == 0x80U) 800402e: f997 3003 ldrsb.w r3, [r7, #3] 8004032: 2b00 cmp r3, #0 8004034: da0c bge.n 8004050 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8004036: 78fb ldrb r3, [r7, #3] 8004038: f003 020f and.w r2, r3, #15 800403c: 4613 mov r3, r2 800403e: 00db lsls r3, r3, #3 8004040: 4413 add r3, r2 8004042: 009b lsls r3, r3, #2 8004044: 3310 adds r3, #16 8004046: 687a ldr r2, [r7, #4] 8004048: 4413 add r3, r2 800404a: 3304 adds r3, #4 800404c: 60fb str r3, [r7, #12] 800404e: e00c b.n 800406a } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8004050: 78fb ldrb r3, [r7, #3] 8004052: f003 020f and.w r2, r3, #15 8004056: 4613 mov r3, r2 8004058: 00db lsls r3, r3, #3 800405a: 4413 add r3, r2 800405c: 009b lsls r3, r3, #2 800405e: f503 7314 add.w r3, r3, #592 @ 0x250 8004062: 687a ldr r2, [r7, #4] 8004064: 4413 add r3, r2 8004066: 3304 adds r3, #4 8004068: 60fb str r3, [r7, #12] } /* Stop Xfer */ ret = USB_EPStopXfer(hpcd->Instance, ep); 800406a: 687b ldr r3, [r7, #4] 800406c: 681b ldr r3, [r3, #0] 800406e: 68f9 ldr r1, [r7, #12] 8004070: 4618 mov r0, r3 8004072: f004 fb77 bl 8008764 8004076: 4603 mov r3, r0 8004078: 72fb strb r3, [r7, #11] return ret; 800407a: 7afb ldrb r3, [r7, #11] } 800407c: 4618 mov r0, r3 800407e: 3710 adds r7, #16 8004080: 46bd mov sp, r7 8004082: bd80 pop {r7, pc} 08004084 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8004084: b580 push {r7, lr} 8004086: b08a sub sp, #40 @ 0x28 8004088: af02 add r7, sp, #8 800408a: 6078 str r0, [r7, #4] 800408c: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 800408e: 687b ldr r3, [r7, #4] 8004090: 681b ldr r3, [r3, #0] 8004092: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8004094: 697b ldr r3, [r7, #20] 8004096: 613b str r3, [r7, #16] USB_OTG_EPTypeDef *ep; uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; 8004098: 683a ldr r2, [r7, #0] 800409a: 4613 mov r3, r2 800409c: 00db lsls r3, r3, #3 800409e: 4413 add r3, r2 80040a0: 009b lsls r3, r3, #2 80040a2: 3310 adds r3, #16 80040a4: 687a ldr r2, [r7, #4] 80040a6: 4413 add r3, r2 80040a8: 3304 adds r3, #4 80040aa: 60fb str r3, [r7, #12] if (ep->xfer_count > ep->xfer_len) 80040ac: 68fb ldr r3, [r7, #12] 80040ae: 695a ldr r2, [r3, #20] 80040b0: 68fb ldr r3, [r7, #12] 80040b2: 691b ldr r3, [r3, #16] 80040b4: 429a cmp r2, r3 80040b6: d901 bls.n 80040bc { return HAL_ERROR; 80040b8: 2301 movs r3, #1 80040ba: e06b b.n 8004194 } len = ep->xfer_len - ep->xfer_count; 80040bc: 68fb ldr r3, [r7, #12] 80040be: 691a ldr r2, [r3, #16] 80040c0: 68fb ldr r3, [r7, #12] 80040c2: 695b ldr r3, [r3, #20] 80040c4: 1ad3 subs r3, r2, r3 80040c6: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 80040c8: 68fb ldr r3, [r7, #12] 80040ca: 689b ldr r3, [r3, #8] 80040cc: 69fa ldr r2, [r7, #28] 80040ce: 429a cmp r2, r3 80040d0: d902 bls.n 80040d8 { len = ep->maxpacket; 80040d2: 68fb ldr r3, [r7, #12] 80040d4: 689b ldr r3, [r3, #8] 80040d6: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 80040d8: 69fb ldr r3, [r7, #28] 80040da: 3303 adds r3, #3 80040dc: 089b lsrs r3, r3, #2 80040de: 61bb str r3, [r7, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 80040e0: e02a b.n 8004138 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; 80040e2: 68fb ldr r3, [r7, #12] 80040e4: 691a ldr r2, [r3, #16] 80040e6: 68fb ldr r3, [r7, #12] 80040e8: 695b ldr r3, [r3, #20] 80040ea: 1ad3 subs r3, r2, r3 80040ec: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 80040ee: 68fb ldr r3, [r7, #12] 80040f0: 689b ldr r3, [r3, #8] 80040f2: 69fa ldr r2, [r7, #28] 80040f4: 429a cmp r2, r3 80040f6: d902 bls.n 80040fe { len = ep->maxpacket; 80040f8: 68fb ldr r3, [r7, #12] 80040fa: 689b ldr r3, [r3, #8] 80040fc: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 80040fe: 69fb ldr r3, [r7, #28] 8004100: 3303 adds r3, #3 8004102: 089b lsrs r3, r3, #2 8004104: 61bb str r3, [r7, #24] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8004106: 68fb ldr r3, [r7, #12] 8004108: 68d9 ldr r1, [r3, #12] 800410a: 683b ldr r3, [r7, #0] 800410c: b2da uxtb r2, r3 800410e: 69fb ldr r3, [r7, #28] 8004110: b298 uxth r0, r3 (uint8_t)hpcd->Init.dma_enable); 8004112: 687b ldr r3, [r7, #4] 8004114: 799b ldrb r3, [r3, #6] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8004116: 9300 str r3, [sp, #0] 8004118: 4603 mov r3, r0 800411a: 6978 ldr r0, [r7, #20] 800411c: f004 fbcc bl 80088b8 ep->xfer_buff += len; 8004120: 68fb ldr r3, [r7, #12] 8004122: 68da ldr r2, [r3, #12] 8004124: 69fb ldr r3, [r7, #28] 8004126: 441a add r2, r3 8004128: 68fb ldr r3, [r7, #12] 800412a: 60da str r2, [r3, #12] ep->xfer_count += len; 800412c: 68fb ldr r3, [r7, #12] 800412e: 695a ldr r2, [r3, #20] 8004130: 69fb ldr r3, [r7, #28] 8004132: 441a add r2, r3 8004134: 68fb ldr r3, [r7, #12] 8004136: 615a str r2, [r3, #20] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8004138: 683b ldr r3, [r7, #0] 800413a: 015a lsls r2, r3, #5 800413c: 693b ldr r3, [r7, #16] 800413e: 4413 add r3, r2 8004140: f503 6310 add.w r3, r3, #2304 @ 0x900 8004144: 699b ldr r3, [r3, #24] 8004146: b29b uxth r3, r3 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8004148: 69ba ldr r2, [r7, #24] 800414a: 429a cmp r2, r3 800414c: d809 bhi.n 8004162 800414e: 68fb ldr r3, [r7, #12] 8004150: 695a ldr r2, [r3, #20] 8004152: 68fb ldr r3, [r7, #12] 8004154: 691b ldr r3, [r3, #16] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8004156: 429a cmp r2, r3 8004158: d203 bcs.n 8004162 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 800415a: 68fb ldr r3, [r7, #12] 800415c: 691b ldr r3, [r3, #16] 800415e: 2b00 cmp r3, #0 8004160: d1bf bne.n 80040e2 } if (ep->xfer_len <= ep->xfer_count) 8004162: 68fb ldr r3, [r7, #12] 8004164: 691a ldr r2, [r3, #16] 8004166: 68fb ldr r3, [r7, #12] 8004168: 695b ldr r3, [r3, #20] 800416a: 429a cmp r2, r3 800416c: d811 bhi.n 8004192 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 800416e: 683b ldr r3, [r7, #0] 8004170: f003 030f and.w r3, r3, #15 8004174: 2201 movs r2, #1 8004176: fa02 f303 lsl.w r3, r2, r3 800417a: 60bb str r3, [r7, #8] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 800417c: 693b ldr r3, [r7, #16] 800417e: f503 6300 add.w r3, r3, #2048 @ 0x800 8004182: 6b5a ldr r2, [r3, #52] @ 0x34 8004184: 68bb ldr r3, [r7, #8] 8004186: 43db mvns r3, r3 8004188: 6939 ldr r1, [r7, #16] 800418a: f501 6100 add.w r1, r1, #2048 @ 0x800 800418e: 4013 ands r3, r2 8004190: 634b str r3, [r1, #52] @ 0x34 } return HAL_OK; 8004192: 2300 movs r3, #0 } 8004194: 4618 mov r0, r3 8004196: 3720 adds r7, #32 8004198: 46bd mov sp, r7 800419a: bd80 pop {r7, pc} 0800419c : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 800419c: b580 push {r7, lr} 800419e: b088 sub sp, #32 80041a0: af00 add r7, sp, #0 80041a2: 6078 str r0, [r7, #4] 80041a4: 6039 str r1, [r7, #0] USB_OTG_EPTypeDef *ep; const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 80041a6: 687b ldr r3, [r7, #4] 80041a8: 681b ldr r3, [r3, #0] 80041aa: 61fb str r3, [r7, #28] uint32_t USBx_BASE = (uint32_t)USBx; 80041ac: 69fb ldr r3, [r7, #28] 80041ae: 61bb str r3, [r7, #24] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 80041b0: 69fb ldr r3, [r7, #28] 80041b2: 333c adds r3, #60 @ 0x3c 80041b4: 3304 adds r3, #4 80041b6: 681b ldr r3, [r3, #0] 80041b8: 617b str r3, [r7, #20] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 80041ba: 683b ldr r3, [r7, #0] 80041bc: 015a lsls r2, r3, #5 80041be: 69bb ldr r3, [r7, #24] 80041c0: 4413 add r3, r2 80041c2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80041c6: 689b ldr r3, [r3, #8] 80041c8: 613b str r3, [r7, #16] if (hpcd->Init.dma_enable == 1U) 80041ca: 687b ldr r3, [r7, #4] 80041cc: 799b ldrb r3, [r3, #6] 80041ce: 2b01 cmp r3, #1 80041d0: d17b bne.n 80042ca { if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ 80041d2: 693b ldr r3, [r7, #16] 80041d4: f003 0308 and.w r3, r3, #8 80041d8: 2b00 cmp r3, #0 80041da: d015 beq.n 8004208 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 80041dc: 697b ldr r3, [r7, #20] 80041de: 4a61 ldr r2, [pc, #388] @ (8004364 ) 80041e0: 4293 cmp r3, r2 80041e2: f240 80b9 bls.w 8004358 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 80041e6: 693b ldr r3, [r7, #16] 80041e8: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 80041ec: 2b00 cmp r3, #0 80041ee: f000 80b3 beq.w 8004358 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 80041f2: 683b ldr r3, [r7, #0] 80041f4: 015a lsls r2, r3, #5 80041f6: 69bb ldr r3, [r7, #24] 80041f8: 4413 add r3, r2 80041fa: f503 6330 add.w r3, r3, #2816 @ 0xb00 80041fe: 461a mov r2, r3 8004200: f44f 4300 mov.w r3, #32768 @ 0x8000 8004204: 6093 str r3, [r2, #8] 8004206: e0a7 b.n 8004358 } } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ 8004208: 693b ldr r3, [r7, #16] 800420a: f003 0320 and.w r3, r3, #32 800420e: 2b00 cmp r3, #0 8004210: d009 beq.n 8004226 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8004212: 683b ldr r3, [r7, #0] 8004214: 015a lsls r2, r3, #5 8004216: 69bb ldr r3, [r7, #24] 8004218: 4413 add r3, r2 800421a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800421e: 461a mov r2, r3 8004220: 2320 movs r3, #32 8004222: 6093 str r3, [r2, #8] 8004224: e098 b.n 8004358 } else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) 8004226: 693b ldr r3, [r7, #16] 8004228: f003 0328 and.w r3, r3, #40 @ 0x28 800422c: 2b00 cmp r3, #0 800422e: f040 8093 bne.w 8004358 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8004232: 697b ldr r3, [r7, #20] 8004234: 4a4b ldr r2, [pc, #300] @ (8004364 ) 8004236: 4293 cmp r3, r2 8004238: d90f bls.n 800425a ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 800423a: 693b ldr r3, [r7, #16] 800423c: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8004240: 2b00 cmp r3, #0 8004242: d00a beq.n 800425a { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8004244: 683b ldr r3, [r7, #0] 8004246: 015a lsls r2, r3, #5 8004248: 69bb ldr r3, [r7, #24] 800424a: 4413 add r3, r2 800424c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004250: 461a mov r2, r3 8004252: f44f 4300 mov.w r3, #32768 @ 0x8000 8004256: 6093 str r3, [r2, #8] 8004258: e07e b.n 8004358 } else { ep = &hpcd->OUT_ep[epnum]; 800425a: 683a ldr r2, [r7, #0] 800425c: 4613 mov r3, r2 800425e: 00db lsls r3, r3, #3 8004260: 4413 add r3, r2 8004262: 009b lsls r3, r3, #2 8004264: f503 7314 add.w r3, r3, #592 @ 0x250 8004268: 687a ldr r2, [r7, #4] 800426a: 4413 add r3, r2 800426c: 3304 adds r3, #4 800426e: 60fb str r3, [r7, #12] /* out data packet received over EP */ ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 8004270: 68fb ldr r3, [r7, #12] 8004272: 6a1a ldr r2, [r3, #32] 8004274: 683b ldr r3, [r7, #0] 8004276: 0159 lsls r1, r3, #5 8004278: 69bb ldr r3, [r7, #24] 800427a: 440b add r3, r1 800427c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004280: 691b ldr r3, [r3, #16] 8004282: f3c3 0312 ubfx r3, r3, #0, #19 8004286: 1ad2 subs r2, r2, r3 8004288: 68fb ldr r3, [r7, #12] 800428a: 615a str r2, [r3, #20] if (epnum == 0U) 800428c: 683b ldr r3, [r7, #0] 800428e: 2b00 cmp r3, #0 8004290: d114 bne.n 80042bc { if (ep->xfer_len == 0U) 8004292: 68fb ldr r3, [r7, #12] 8004294: 691b ldr r3, [r3, #16] 8004296: 2b00 cmp r3, #0 8004298: d109 bne.n 80042ae { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 800429a: 687b ldr r3, [r7, #4] 800429c: 6818 ldr r0, [r3, #0] 800429e: 687b ldr r3, [r7, #4] 80042a0: f203 439c addw r3, r3, #1180 @ 0x49c 80042a4: 461a mov r2, r3 80042a6: 2101 movs r1, #1 80042a8: f004 fd9c bl 8008de4 80042ac: e006 b.n 80042bc } else { ep->xfer_buff += ep->xfer_count; 80042ae: 68fb ldr r3, [r7, #12] 80042b0: 68da ldr r2, [r3, #12] 80042b2: 68fb ldr r3, [r7, #12] 80042b4: 695b ldr r3, [r3, #20] 80042b6: 441a add r2, r3 80042b8: 68fb ldr r3, [r7, #12] 80042ba: 60da str r2, [r3, #12] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 80042bc: 683b ldr r3, [r7, #0] 80042be: b2db uxtb r3, r3 80042c0: 4619 mov r1, r3 80042c2: 6878 ldr r0, [r7, #4] 80042c4: f006 fd6a bl 800ad9c 80042c8: e046 b.n 8004358 /* ... */ } } else { if (gSNPSiD == USB_OTG_CORE_ID_310A) 80042ca: 697b ldr r3, [r7, #20] 80042cc: 4a26 ldr r2, [pc, #152] @ (8004368 ) 80042ce: 4293 cmp r3, r2 80042d0: d124 bne.n 800431c { /* StupPktRcvd = 1 this is a setup packet */ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) 80042d2: 693b ldr r3, [r7, #16] 80042d4: f403 4300 and.w r3, r3, #32768 @ 0x8000 80042d8: 2b00 cmp r3, #0 80042da: d00a beq.n 80042f2 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 80042dc: 683b ldr r3, [r7, #0] 80042de: 015a lsls r2, r3, #5 80042e0: 69bb ldr r3, [r7, #24] 80042e2: 4413 add r3, r2 80042e4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80042e8: 461a mov r2, r3 80042ea: f44f 4300 mov.w r3, #32768 @ 0x8000 80042ee: 6093 str r3, [r2, #8] 80042f0: e032 b.n 8004358 } else { if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 80042f2: 693b ldr r3, [r7, #16] 80042f4: f003 0320 and.w r3, r3, #32 80042f8: 2b00 cmp r3, #0 80042fa: d008 beq.n 800430e { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 80042fc: 683b ldr r3, [r7, #0] 80042fe: 015a lsls r2, r3, #5 8004300: 69bb ldr r3, [r7, #24] 8004302: 4413 add r3, r2 8004304: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004308: 461a mov r2, r3 800430a: 2320 movs r3, #32 800430c: 6093 str r3, [r2, #8] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 800430e: 683b ldr r3, [r7, #0] 8004310: b2db uxtb r3, r3 8004312: 4619 mov r1, r3 8004314: 6878 ldr r0, [r7, #4] 8004316: f006 fd41 bl 800ad9c 800431a: e01d b.n 8004358 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else { if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 800431c: 683b ldr r3, [r7, #0] 800431e: 2b00 cmp r3, #0 8004320: d114 bne.n 800434c 8004322: 6879 ldr r1, [r7, #4] 8004324: 683a ldr r2, [r7, #0] 8004326: 4613 mov r3, r2 8004328: 00db lsls r3, r3, #3 800432a: 4413 add r3, r2 800432c: 009b lsls r3, r3, #2 800432e: 440b add r3, r1 8004330: f503 7319 add.w r3, r3, #612 @ 0x264 8004334: 681b ldr r3, [r3, #0] 8004336: 2b00 cmp r3, #0 8004338: d108 bne.n 800434c { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); 800433a: 687b ldr r3, [r7, #4] 800433c: 6818 ldr r0, [r3, #0] 800433e: 687b ldr r3, [r7, #4] 8004340: f203 439c addw r3, r3, #1180 @ 0x49c 8004344: 461a mov r2, r3 8004346: 2100 movs r1, #0 8004348: f004 fd4c bl 8008de4 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 800434c: 683b ldr r3, [r7, #0] 800434e: b2db uxtb r3, r3 8004350: 4619 mov r1, r3 8004352: 6878 ldr r0, [r7, #4] 8004354: f006 fd22 bl 800ad9c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } return HAL_OK; 8004358: 2300 movs r3, #0 } 800435a: 4618 mov r0, r3 800435c: 3720 adds r7, #32 800435e: 46bd mov sp, r7 8004360: bd80 pop {r7, pc} 8004362: bf00 nop 8004364: 4f54300a .word 0x4f54300a 8004368: 4f54310a .word 0x4f54310a 0800436c : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 800436c: b580 push {r7, lr} 800436e: b086 sub sp, #24 8004370: af00 add r7, sp, #0 8004372: 6078 str r0, [r7, #4] 8004374: 6039 str r1, [r7, #0] const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8004376: 687b ldr r3, [r7, #4] 8004378: 681b ldr r3, [r3, #0] 800437a: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 800437c: 697b ldr r3, [r7, #20] 800437e: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8004380: 697b ldr r3, [r7, #20] 8004382: 333c adds r3, #60 @ 0x3c 8004384: 3304 adds r3, #4 8004386: 681b ldr r3, [r3, #0] 8004388: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 800438a: 683b ldr r3, [r7, #0] 800438c: 015a lsls r2, r3, #5 800438e: 693b ldr r3, [r7, #16] 8004390: 4413 add r3, r2 8004392: f503 6330 add.w r3, r3, #2816 @ 0xb00 8004396: 689b ldr r3, [r3, #8] 8004398: 60bb str r3, [r7, #8] if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 800439a: 68fb ldr r3, [r7, #12] 800439c: 4a15 ldr r2, [pc, #84] @ (80043f4 ) 800439e: 4293 cmp r3, r2 80043a0: d90e bls.n 80043c0 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 80043a2: 68bb ldr r3, [r7, #8] 80043a4: f403 4300 and.w r3, r3, #32768 @ 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 80043a8: 2b00 cmp r3, #0 80043aa: d009 beq.n 80043c0 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 80043ac: 683b ldr r3, [r7, #0] 80043ae: 015a lsls r2, r3, #5 80043b0: 693b ldr r3, [r7, #16] 80043b2: 4413 add r3, r2 80043b4: f503 6330 add.w r3, r3, #2816 @ 0xb00 80043b8: 461a mov r2, r3 80043ba: f44f 4300 mov.w r3, #32768 @ 0x8000 80043be: 6093 str r3, [r2, #8] /* Inform the upper layer that a setup packet is available */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 80043c0: 6878 ldr r0, [r7, #4] 80043c2: f006 fcd9 bl 800ad78 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) 80043c6: 68fb ldr r3, [r7, #12] 80043c8: 4a0a ldr r2, [pc, #40] @ (80043f4 ) 80043ca: 4293 cmp r3, r2 80043cc: d90c bls.n 80043e8 80043ce: 687b ldr r3, [r7, #4] 80043d0: 799b ldrb r3, [r3, #6] 80043d2: 2b01 cmp r3, #1 80043d4: d108 bne.n 80043e8 { (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 80043d6: 687b ldr r3, [r7, #4] 80043d8: 6818 ldr r0, [r3, #0] 80043da: 687b ldr r3, [r7, #4] 80043dc: f203 439c addw r3, r3, #1180 @ 0x49c 80043e0: 461a mov r2, r3 80043e2: 2101 movs r1, #1 80043e4: f004 fcfe bl 8008de4 } return HAL_OK; 80043e8: 2300 movs r3, #0 } 80043ea: 4618 mov r0, r3 80043ec: 3718 adds r7, #24 80043ee: 46bd mov sp, r7 80043f0: bd80 pop {r7, pc} 80043f2: bf00 nop 80043f4: 4f54300a .word 0x4f54300a 080043f8 : * @param fifo The number of Tx fifo * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { 80043f8: b480 push {r7} 80043fa: b085 sub sp, #20 80043fc: af00 add r7, sp, #0 80043fe: 6078 str r0, [r7, #4] 8004400: 460b mov r3, r1 8004402: 70fb strb r3, [r7, #3] 8004404: 4613 mov r3, r2 8004406: 803b strh r3, [r7, #0] --> Txn should be configured with the minimum space of 16 words The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ Tx_Offset = hpcd->Instance->GRXFSIZ; 8004408: 687b ldr r3, [r7, #4] 800440a: 681b ldr r3, [r3, #0] 800440c: 6a5b ldr r3, [r3, #36] @ 0x24 800440e: 60bb str r3, [r7, #8] if (fifo == 0U) 8004410: 78fb ldrb r3, [r7, #3] 8004412: 2b00 cmp r3, #0 8004414: d107 bne.n 8004426 { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; 8004416: 883b ldrh r3, [r7, #0] 8004418: 0419 lsls r1, r3, #16 800441a: 687b ldr r3, [r7, #4] 800441c: 681b ldr r3, [r3, #0] 800441e: 68ba ldr r2, [r7, #8] 8004420: 430a orrs r2, r1 8004422: 629a str r2, [r3, #40] @ 0x28 8004424: e028 b.n 8004478 } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; 8004426: 687b ldr r3, [r7, #4] 8004428: 681b ldr r3, [r3, #0] 800442a: 6a9b ldr r3, [r3, #40] @ 0x28 800442c: 0c1b lsrs r3, r3, #16 800442e: 68ba ldr r2, [r7, #8] 8004430: 4413 add r3, r2 8004432: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8004434: 2300 movs r3, #0 8004436: 73fb strb r3, [r7, #15] 8004438: e00d b.n 8004456 { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); 800443a: 687b ldr r3, [r7, #4] 800443c: 681a ldr r2, [r3, #0] 800443e: 7bfb ldrb r3, [r7, #15] 8004440: 3340 adds r3, #64 @ 0x40 8004442: 009b lsls r3, r3, #2 8004444: 4413 add r3, r2 8004446: 685b ldr r3, [r3, #4] 8004448: 0c1b lsrs r3, r3, #16 800444a: 68ba ldr r2, [r7, #8] 800444c: 4413 add r3, r2 800444e: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8004450: 7bfb ldrb r3, [r7, #15] 8004452: 3301 adds r3, #1 8004454: 73fb strb r3, [r7, #15] 8004456: 7bfa ldrb r2, [r7, #15] 8004458: 78fb ldrb r3, [r7, #3] 800445a: 3b01 subs r3, #1 800445c: 429a cmp r2, r3 800445e: d3ec bcc.n 800443a } /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; 8004460: 883b ldrh r3, [r7, #0] 8004462: 0418 lsls r0, r3, #16 8004464: 687b ldr r3, [r7, #4] 8004466: 6819 ldr r1, [r3, #0] 8004468: 78fb ldrb r3, [r7, #3] 800446a: 3b01 subs r3, #1 800446c: 68ba ldr r2, [r7, #8] 800446e: 4302 orrs r2, r0 8004470: 3340 adds r3, #64 @ 0x40 8004472: 009b lsls r3, r3, #2 8004474: 440b add r3, r1 8004476: 605a str r2, [r3, #4] } return HAL_OK; 8004478: 2300 movs r3, #0 } 800447a: 4618 mov r0, r3 800447c: 3714 adds r7, #20 800447e: 46bd mov sp, r7 8004480: f85d 7b04 ldr.w r7, [sp], #4 8004484: 4770 bx lr 08004486 : * @param hpcd PCD handle * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { 8004486: b480 push {r7} 8004488: b083 sub sp, #12 800448a: af00 add r7, sp, #0 800448c: 6078 str r0, [r7, #4] 800448e: 460b mov r3, r1 8004490: 807b strh r3, [r7, #2] hpcd->Instance->GRXFSIZ = size; 8004492: 687b ldr r3, [r7, #4] 8004494: 681b ldr r3, [r3, #0] 8004496: 887a ldrh r2, [r7, #2] 8004498: 625a str r2, [r3, #36] @ 0x24 return HAL_OK; 800449a: 2300 movs r3, #0 } 800449c: 4618 mov r0, r3 800449e: 370c adds r7, #12 80044a0: 46bd mov sp, r7 80044a2: f85d 7b04 ldr.w r7, [sp], #4 80044a6: 4770 bx lr 080044a8 : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 80044a8: b480 push {r7} 80044aa: b085 sub sp, #20 80044ac: af00 add r7, sp, #0 80044ae: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 80044b0: 687b ldr r3, [r7, #4] 80044b2: 681b ldr r3, [r3, #0] 80044b4: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 80044b6: 687b ldr r3, [r7, #4] 80044b8: 2201 movs r2, #1 80044ba: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8 hpcd->LPM_State = LPM_L0; 80044be: 687b ldr r3, [r7, #4] 80044c0: 2200 movs r2, #0 80044c2: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 80044c6: 68fb ldr r3, [r7, #12] 80044c8: 699b ldr r3, [r3, #24] 80044ca: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000 80044ce: 68fb ldr r3, [r7, #12] 80044d0: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 80044d2: 68fb ldr r3, [r7, #12] 80044d4: 6d5b ldr r3, [r3, #84] @ 0x54 80044d6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80044da: f043 0303 orr.w r3, r3, #3 80044de: 68fa ldr r2, [r7, #12] 80044e0: 6553 str r3, [r2, #84] @ 0x54 return HAL_OK; 80044e2: 2300 movs r3, #0 } 80044e4: 4618 mov r0, r3 80044e6: 3714 adds r7, #20 80044e8: 46bd mov sp, r7 80044ea: f85d 7b04 ldr.w r7, [sp], #4 80044ee: 4770 bx lr 080044f0 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80044f0: b580 push {r7, lr} 80044f2: b084 sub sp, #16 80044f4: af00 add r7, sp, #0 80044f6: 6078 str r0, [r7, #4] 80044f8: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 80044fa: 687b ldr r3, [r7, #4] 80044fc: 2b00 cmp r3, #0 80044fe: d101 bne.n 8004504 { return HAL_ERROR; 8004500: 2301 movs r3, #1 8004502: e0cc b.n 800469e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8004504: 4b68 ldr r3, [pc, #416] @ (80046a8 ) 8004506: 681b ldr r3, [r3, #0] 8004508: f003 030f and.w r3, r3, #15 800450c: 683a ldr r2, [r7, #0] 800450e: 429a cmp r2, r3 8004510: d90c bls.n 800452c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004512: 4b65 ldr r3, [pc, #404] @ (80046a8 ) 8004514: 683a ldr r2, [r7, #0] 8004516: b2d2 uxtb r2, r2 8004518: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800451a: 4b63 ldr r3, [pc, #396] @ (80046a8 ) 800451c: 681b ldr r3, [r3, #0] 800451e: f003 030f and.w r3, r3, #15 8004522: 683a ldr r2, [r7, #0] 8004524: 429a cmp r2, r3 8004526: d001 beq.n 800452c { return HAL_ERROR; 8004528: 2301 movs r3, #1 800452a: e0b8 b.n 800469e } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800452c: 687b ldr r3, [r7, #4] 800452e: 681b ldr r3, [r3, #0] 8004530: f003 0302 and.w r3, r3, #2 8004534: 2b00 cmp r3, #0 8004536: d020 beq.n 800457a { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004538: 687b ldr r3, [r7, #4] 800453a: 681b ldr r3, [r3, #0] 800453c: f003 0304 and.w r3, r3, #4 8004540: 2b00 cmp r3, #0 8004542: d005 beq.n 8004550 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8004544: 4b59 ldr r3, [pc, #356] @ (80046ac ) 8004546: 689b ldr r3, [r3, #8] 8004548: 4a58 ldr r2, [pc, #352] @ (80046ac ) 800454a: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 800454e: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004550: 687b ldr r3, [r7, #4] 8004552: 681b ldr r3, [r3, #0] 8004554: f003 0308 and.w r3, r3, #8 8004558: 2b00 cmp r3, #0 800455a: d005 beq.n 8004568 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 800455c: 4b53 ldr r3, [pc, #332] @ (80046ac ) 800455e: 689b ldr r3, [r3, #8] 8004560: 4a52 ldr r2, [pc, #328] @ (80046ac ) 8004562: f443 4360 orr.w r3, r3, #57344 @ 0xe000 8004566: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8004568: 4b50 ldr r3, [pc, #320] @ (80046ac ) 800456a: 689b ldr r3, [r3, #8] 800456c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8004570: 687b ldr r3, [r7, #4] 8004572: 689b ldr r3, [r3, #8] 8004574: 494d ldr r1, [pc, #308] @ (80046ac ) 8004576: 4313 orrs r3, r2 8004578: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800457a: 687b ldr r3, [r7, #4] 800457c: 681b ldr r3, [r3, #0] 800457e: f003 0301 and.w r3, r3, #1 8004582: 2b00 cmp r3, #0 8004584: d044 beq.n 8004610 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004586: 687b ldr r3, [r7, #4] 8004588: 685b ldr r3, [r3, #4] 800458a: 2b01 cmp r3, #1 800458c: d107 bne.n 800459e { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800458e: 4b47 ldr r3, [pc, #284] @ (80046ac ) 8004590: 681b ldr r3, [r3, #0] 8004592: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004596: 2b00 cmp r3, #0 8004598: d119 bne.n 80045ce { return HAL_ERROR; 800459a: 2301 movs r3, #1 800459c: e07f b.n 800469e } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 800459e: 687b ldr r3, [r7, #4] 80045a0: 685b ldr r3, [r3, #4] 80045a2: 2b02 cmp r3, #2 80045a4: d003 beq.n 80045ae (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 80045a6: 687b ldr r3, [r7, #4] 80045a8: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 80045aa: 2b03 cmp r3, #3 80045ac: d107 bne.n 80045be { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80045ae: 4b3f ldr r3, [pc, #252] @ (80046ac ) 80045b0: 681b ldr r3, [r3, #0] 80045b2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80045b6: 2b00 cmp r3, #0 80045b8: d109 bne.n 80045ce { return HAL_ERROR; 80045ba: 2301 movs r3, #1 80045bc: e06f b.n 800469e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80045be: 4b3b ldr r3, [pc, #236] @ (80046ac ) 80045c0: 681b ldr r3, [r3, #0] 80045c2: f003 0302 and.w r3, r3, #2 80045c6: 2b00 cmp r3, #0 80045c8: d101 bne.n 80045ce { return HAL_ERROR; 80045ca: 2301 movs r3, #1 80045cc: e067 b.n 800469e } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80045ce: 4b37 ldr r3, [pc, #220] @ (80046ac ) 80045d0: 689b ldr r3, [r3, #8] 80045d2: f023 0203 bic.w r2, r3, #3 80045d6: 687b ldr r3, [r7, #4] 80045d8: 685b ldr r3, [r3, #4] 80045da: 4934 ldr r1, [pc, #208] @ (80046ac ) 80045dc: 4313 orrs r3, r2 80045de: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 80045e0: f7fd fcb2 bl 8001f48 80045e4: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80045e6: e00a b.n 80045fe { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80045e8: f7fd fcae bl 8001f48 80045ec: 4602 mov r2, r0 80045ee: 68fb ldr r3, [r7, #12] 80045f0: 1ad3 subs r3, r2, r3 80045f2: f241 3288 movw r2, #5000 @ 0x1388 80045f6: 4293 cmp r3, r2 80045f8: d901 bls.n 80045fe { return HAL_TIMEOUT; 80045fa: 2303 movs r3, #3 80045fc: e04f b.n 800469e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80045fe: 4b2b ldr r3, [pc, #172] @ (80046ac ) 8004600: 689b ldr r3, [r3, #8] 8004602: f003 020c and.w r2, r3, #12 8004606: 687b ldr r3, [r7, #4] 8004608: 685b ldr r3, [r3, #4] 800460a: 009b lsls r3, r3, #2 800460c: 429a cmp r2, r3 800460e: d1eb bne.n 80045e8 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8004610: 4b25 ldr r3, [pc, #148] @ (80046a8 ) 8004612: 681b ldr r3, [r3, #0] 8004614: f003 030f and.w r3, r3, #15 8004618: 683a ldr r2, [r7, #0] 800461a: 429a cmp r2, r3 800461c: d20c bcs.n 8004638 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800461e: 4b22 ldr r3, [pc, #136] @ (80046a8 ) 8004620: 683a ldr r2, [r7, #0] 8004622: b2d2 uxtb r2, r2 8004624: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004626: 4b20 ldr r3, [pc, #128] @ (80046a8 ) 8004628: 681b ldr r3, [r3, #0] 800462a: f003 030f and.w r3, r3, #15 800462e: 683a ldr r2, [r7, #0] 8004630: 429a cmp r2, r3 8004632: d001 beq.n 8004638 { return HAL_ERROR; 8004634: 2301 movs r3, #1 8004636: e032 b.n 800469e } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004638: 687b ldr r3, [r7, #4] 800463a: 681b ldr r3, [r3, #0] 800463c: f003 0304 and.w r3, r3, #4 8004640: 2b00 cmp r3, #0 8004642: d008 beq.n 8004656 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8004644: 4b19 ldr r3, [pc, #100] @ (80046ac ) 8004646: 689b ldr r3, [r3, #8] 8004648: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 800464c: 687b ldr r3, [r7, #4] 800464e: 68db ldr r3, [r3, #12] 8004650: 4916 ldr r1, [pc, #88] @ (80046ac ) 8004652: 4313 orrs r3, r2 8004654: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004656: 687b ldr r3, [r7, #4] 8004658: 681b ldr r3, [r3, #0] 800465a: f003 0308 and.w r3, r3, #8 800465e: 2b00 cmp r3, #0 8004660: d009 beq.n 8004676 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8004662: 4b12 ldr r3, [pc, #72] @ (80046ac ) 8004664: 689b ldr r3, [r3, #8] 8004666: f423 4260 bic.w r2, r3, #57344 @ 0xe000 800466a: 687b ldr r3, [r7, #4] 800466c: 691b ldr r3, [r3, #16] 800466e: 00db lsls r3, r3, #3 8004670: 490e ldr r1, [pc, #56] @ (80046ac ) 8004672: 4313 orrs r3, r2 8004674: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8004676: f000 fb7f bl 8004d78 800467a: 4602 mov r2, r0 800467c: 4b0b ldr r3, [pc, #44] @ (80046ac ) 800467e: 689b ldr r3, [r3, #8] 8004680: 091b lsrs r3, r3, #4 8004682: f003 030f and.w r3, r3, #15 8004686: 490a ldr r1, [pc, #40] @ (80046b0 ) 8004688: 5ccb ldrb r3, [r1, r3] 800468a: fa22 f303 lsr.w r3, r2, r3 800468e: 4a09 ldr r2, [pc, #36] @ (80046b4 ) 8004690: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); 8004692: 4b09 ldr r3, [pc, #36] @ (80046b8 ) 8004694: 681b ldr r3, [r3, #0] 8004696: 4618 mov r0, r3 8004698: f7fd fc12 bl 8001ec0 return HAL_OK; 800469c: 2300 movs r3, #0 } 800469e: 4618 mov r0, r3 80046a0: 3710 adds r7, #16 80046a2: 46bd mov sp, r7 80046a4: bd80 pop {r7, pc} 80046a6: bf00 nop 80046a8: 40023c00 .word 0x40023c00 80046ac: 40023800 .word 0x40023800 80046b0: 0800b438 .word 0x0800b438 80046b4: 20000104 .word 0x20000104 80046b8: 20000108 .word 0x20000108 080046bc : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80046bc: b480 push {r7} 80046be: af00 add r7, sp, #0 return SystemCoreClock; 80046c0: 4b03 ldr r3, [pc, #12] @ (80046d0 ) 80046c2: 681b ldr r3, [r3, #0] } 80046c4: 4618 mov r0, r3 80046c6: 46bd mov sp, r7 80046c8: f85d 7b04 ldr.w r7, [sp], #4 80046cc: 4770 bx lr 80046ce: bf00 nop 80046d0: 20000104 .word 0x20000104 080046d4 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80046d4: b580 push {r7, lr} 80046d6: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 80046d8: f7ff fff0 bl 80046bc 80046dc: 4602 mov r2, r0 80046de: 4b05 ldr r3, [pc, #20] @ (80046f4 ) 80046e0: 689b ldr r3, [r3, #8] 80046e2: 0a9b lsrs r3, r3, #10 80046e4: f003 0307 and.w r3, r3, #7 80046e8: 4903 ldr r1, [pc, #12] @ (80046f8 ) 80046ea: 5ccb ldrb r3, [r1, r3] 80046ec: fa22 f303 lsr.w r3, r2, r3 } 80046f0: 4618 mov r0, r3 80046f2: bd80 pop {r7, pc} 80046f4: 40023800 .word 0x40023800 80046f8: 0800b448 .word 0x0800b448 080046fc : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 80046fc: b580 push {r7, lr} 80046fe: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8004700: f7ff ffdc bl 80046bc 8004704: 4602 mov r2, r0 8004706: 4b05 ldr r3, [pc, #20] @ (800471c ) 8004708: 689b ldr r3, [r3, #8] 800470a: 0b5b lsrs r3, r3, #13 800470c: f003 0307 and.w r3, r3, #7 8004710: 4903 ldr r1, [pc, #12] @ (8004720 ) 8004712: 5ccb ldrb r3, [r1, r3] 8004714: fa22 f303 lsr.w r3, r2, r3 } 8004718: 4618 mov r0, r3 800471a: bd80 pop {r7, pc} 800471c: 40023800 .word 0x40023800 8004720: 0800b448 .word 0x0800b448 08004724 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8004724: b580 push {r7, lr} 8004726: b08c sub sp, #48 @ 0x30 8004728: af00 add r7, sp, #0 800472a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800472c: 2300 movs r3, #0 800472e: 627b str r3, [r7, #36] @ 0x24 uint32_t tmpreg1 = 0U; 8004730: 2300 movs r3, #0 8004732: 623b str r3, [r7, #32] uint32_t plli2sp = 0U; 8004734: 2300 movs r3, #0 8004736: 61fb str r3, [r7, #28] uint32_t plli2sq = 0U; 8004738: 2300 movs r3, #0 800473a: 61bb str r3, [r7, #24] uint32_t plli2sr = 0U; 800473c: 2300 movs r3, #0 800473e: 617b str r3, [r7, #20] uint32_t pllsaip = 0U; 8004740: 2300 movs r3, #0 8004742: 613b str r3, [r7, #16] uint32_t pllsaiq = 0U; 8004744: 2300 movs r3, #0 8004746: 60fb str r3, [r7, #12] uint32_t plli2sused = 0U; 8004748: 2300 movs r3, #0 800474a: 62fb str r3, [r7, #44] @ 0x2c uint32_t pllsaiused = 0U; 800474c: 2300 movs r3, #0 800474e: 62bb str r3, [r7, #40] @ 0x28 /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------ I2S APB1 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) 8004750: 687b ldr r3, [r7, #4] 8004752: 681b ldr r3, [r3, #0] 8004754: f003 0301 and.w r3, r3, #1 8004758: 2b00 cmp r3, #0 800475a: d010 beq.n 800477e { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); 800475c: 4b6f ldr r3, [pc, #444] @ (800491c ) 800475e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004762: f023 62c0 bic.w r2, r3, #100663296 @ 0x6000000 8004766: 687b ldr r3, [r7, #4] 8004768: 6b9b ldr r3, [r3, #56] @ 0x38 800476a: 496c ldr r1, [pc, #432] @ (800491c ) 800476c: 4313 orrs r3, r2 800476e: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) 8004772: 687b ldr r3, [r7, #4] 8004774: 6b9b ldr r3, [r3, #56] @ 0x38 8004776: 2b00 cmp r3, #0 8004778: d101 bne.n 800477e { plli2sused = 1U; 800477a: 2301 movs r3, #1 800477c: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*---------------------------- I2S APB2 configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) 800477e: 687b ldr r3, [r7, #4] 8004780: 681b ldr r3, [r3, #0] 8004782: f003 0302 and.w r3, r3, #2 8004786: 2b00 cmp r3, #0 8004788: d010 beq.n 80047ac { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); 800478a: 4b64 ldr r3, [pc, #400] @ (800491c ) 800478c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004790: f023 52c0 bic.w r2, r3, #402653184 @ 0x18000000 8004794: 687b ldr r3, [r7, #4] 8004796: 6bdb ldr r3, [r3, #60] @ 0x3c 8004798: 4960 ldr r1, [pc, #384] @ (800491c ) 800479a: 4313 orrs r3, r2 800479c: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) 80047a0: 687b ldr r3, [r7, #4] 80047a2: 6bdb ldr r3, [r3, #60] @ 0x3c 80047a4: 2b00 cmp r3, #0 80047a6: d101 bne.n 80047ac { plli2sused = 1U; 80047a8: 2301 movs r3, #1 80047aa: 62fb str r3, [r7, #44] @ 0x2c } } /*--------------------------------------------------------------------------*/ /*--------------------------- SAI1 configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) 80047ac: 687b ldr r3, [r7, #4] 80047ae: 681b ldr r3, [r3, #0] 80047b0: f003 0304 and.w r3, r3, #4 80047b4: 2b00 cmp r3, #0 80047b6: d017 beq.n 80047e8 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 80047b8: 4b58 ldr r3, [pc, #352] @ (800491c ) 80047ba: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80047be: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 80047c2: 687b ldr r3, [r7, #4] 80047c4: 6b1b ldr r3, [r3, #48] @ 0x30 80047c6: 4955 ldr r1, [pc, #340] @ (800491c ) 80047c8: 4313 orrs r3, r2 80047ca: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) 80047ce: 687b ldr r3, [r7, #4] 80047d0: 6b1b ldr r3, [r3, #48] @ 0x30 80047d2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80047d6: d101 bne.n 80047dc { plli2sused = 1U; 80047d8: 2301 movs r3, #1 80047da: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) 80047dc: 687b ldr r3, [r7, #4] 80047de: 6b1b ldr r3, [r3, #48] @ 0x30 80047e0: 2b00 cmp r3, #0 80047e2: d101 bne.n 80047e8 { pllsaiused = 1U; 80047e4: 2301 movs r3, #1 80047e6: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*-------------------------- SAI2 configuration ----------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) 80047e8: 687b ldr r3, [r7, #4] 80047ea: 681b ldr r3, [r3, #0] 80047ec: f003 0308 and.w r3, r3, #8 80047f0: 2b00 cmp r3, #0 80047f2: d017 beq.n 8004824 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 80047f4: 4b49 ldr r3, [pc, #292] @ (800491c ) 80047f6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80047fa: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 80047fe: 687b ldr r3, [r7, #4] 8004800: 6b5b ldr r3, [r3, #52] @ 0x34 8004802: 4946 ldr r1, [pc, #280] @ (800491c ) 8004804: 4313 orrs r3, r2 8004806: f8c1 308c str.w r3, [r1, #140] @ 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) 800480a: 687b ldr r3, [r7, #4] 800480c: 6b5b ldr r3, [r3, #52] @ 0x34 800480e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004812: d101 bne.n 8004818 { plli2sused = 1U; 8004814: 2301 movs r3, #1 8004816: 62fb str r3, [r7, #44] @ 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) 8004818: 687b ldr r3, [r7, #4] 800481a: 6b5b ldr r3, [r3, #52] @ 0x34 800481c: 2b00 cmp r3, #0 800481e: d101 bne.n 8004824 { pllsaiused = 1U; 8004820: 2301 movs r3, #1 8004822: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- RTC configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 8004824: 687b ldr r3, [r7, #4] 8004826: 681b ldr r3, [r3, #0] 8004828: f003 0320 and.w r3, r3, #32 800482c: 2b00 cmp r3, #0 800482e: f000 808a beq.w 8004946 { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 8004832: 2300 movs r3, #0 8004834: 60bb str r3, [r7, #8] 8004836: 4b39 ldr r3, [pc, #228] @ (800491c ) 8004838: 6c1b ldr r3, [r3, #64] @ 0x40 800483a: 4a38 ldr r2, [pc, #224] @ (800491c ) 800483c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004840: 6413 str r3, [r2, #64] @ 0x40 8004842: 4b36 ldr r3, [pc, #216] @ (800491c ) 8004844: 6c1b ldr r3, [r3, #64] @ 0x40 8004846: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800484a: 60bb str r3, [r7, #8] 800484c: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; 800484e: 4b34 ldr r3, [pc, #208] @ (8004920 ) 8004850: 681b ldr r3, [r3, #0] 8004852: 4a33 ldr r2, [pc, #204] @ (8004920 ) 8004854: f443 7380 orr.w r3, r3, #256 @ 0x100 8004858: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 800485a: f7fd fb75 bl 8001f48 800485e: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR & PWR_CR_DBP) == RESET) 8004860: e008 b.n 8004874 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004862: f7fd fb71 bl 8001f48 8004866: 4602 mov r2, r0 8004868: 6a7b ldr r3, [r7, #36] @ 0x24 800486a: 1ad3 subs r3, r2, r3 800486c: 2b02 cmp r3, #2 800486e: d901 bls.n 8004874 { return HAL_TIMEOUT; 8004870: 2303 movs r3, #3 8004872: e278 b.n 8004d66 while ((PWR->CR & PWR_CR_DBP) == RESET) 8004874: 4b2a ldr r3, [pc, #168] @ (8004920 ) 8004876: 681b ldr r3, [r3, #0] 8004878: f403 7380 and.w r3, r3, #256 @ 0x100 800487c: 2b00 cmp r3, #0 800487e: d0f0 beq.n 8004862 } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); 8004880: 4b26 ldr r3, [pc, #152] @ (800491c ) 8004882: 6f1b ldr r3, [r3, #112] @ 0x70 8004884: f403 7340 and.w r3, r3, #768 @ 0x300 8004888: 623b str r3, [r7, #32] if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 800488a: 6a3b ldr r3, [r7, #32] 800488c: 2b00 cmp r3, #0 800488e: d02f beq.n 80048f0 8004890: 687b ldr r3, [r7, #4] 8004892: 6c1b ldr r3, [r3, #64] @ 0x40 8004894: f403 7340 and.w r3, r3, #768 @ 0x300 8004898: 6a3a ldr r2, [r7, #32] 800489a: 429a cmp r2, r3 800489c: d028 beq.n 80048f0 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800489e: 4b1f ldr r3, [pc, #124] @ (800491c ) 80048a0: 6f1b ldr r3, [r3, #112] @ 0x70 80048a2: f423 7340 bic.w r3, r3, #768 @ 0x300 80048a6: 623b str r3, [r7, #32] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80048a8: 4b1e ldr r3, [pc, #120] @ (8004924 ) 80048aa: 2201 movs r2, #1 80048ac: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 80048ae: 4b1d ldr r3, [pc, #116] @ (8004924 ) 80048b0: 2200 movs r2, #0 80048b2: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; 80048b4: 4a19 ldr r2, [pc, #100] @ (800491c ) 80048b6: 6a3b ldr r3, [r7, #32] 80048b8: 6713 str r3, [r2, #112] @ 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 80048ba: 4b18 ldr r3, [pc, #96] @ (800491c ) 80048bc: 6f1b ldr r3, [r3, #112] @ 0x70 80048be: f003 0301 and.w r3, r3, #1 80048c2: 2b01 cmp r3, #1 80048c4: d114 bne.n 80048f0 { /* Get tick */ tickstart = HAL_GetTick(); 80048c6: f7fd fb3f bl 8001f48 80048ca: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80048cc: e00a b.n 80048e4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80048ce: f7fd fb3b bl 8001f48 80048d2: 4602 mov r2, r0 80048d4: 6a7b ldr r3, [r7, #36] @ 0x24 80048d6: 1ad3 subs r3, r2, r3 80048d8: f241 3288 movw r2, #5000 @ 0x1388 80048dc: 4293 cmp r3, r2 80048de: d901 bls.n 80048e4 { return HAL_TIMEOUT; 80048e0: 2303 movs r3, #3 80048e2: e240 b.n 8004d66 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80048e4: 4b0d ldr r3, [pc, #52] @ (800491c ) 80048e6: 6f1b ldr r3, [r3, #112] @ 0x70 80048e8: f003 0302 and.w r3, r3, #2 80048ec: 2b00 cmp r3, #0 80048ee: d0ee beq.n 80048ce } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80048f0: 687b ldr r3, [r7, #4] 80048f2: 6c1b ldr r3, [r3, #64] @ 0x40 80048f4: f403 7340 and.w r3, r3, #768 @ 0x300 80048f8: f5b3 7f40 cmp.w r3, #768 @ 0x300 80048fc: d114 bne.n 8004928 80048fe: 4b07 ldr r3, [pc, #28] @ (800491c ) 8004900: 689b ldr r3, [r3, #8] 8004902: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000 8004906: 687b ldr r3, [r7, #4] 8004908: 6c1b ldr r3, [r3, #64] @ 0x40 800490a: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 800490e: f423 7340 bic.w r3, r3, #768 @ 0x300 8004912: 4902 ldr r1, [pc, #8] @ (800491c ) 8004914: 4313 orrs r3, r2 8004916: 608b str r3, [r1, #8] 8004918: e00c b.n 8004934 800491a: bf00 nop 800491c: 40023800 .word 0x40023800 8004920: 40007000 .word 0x40007000 8004924: 42470e40 .word 0x42470e40 8004928: 4b4a ldr r3, [pc, #296] @ (8004a54 ) 800492a: 689b ldr r3, [r3, #8] 800492c: 4a49 ldr r2, [pc, #292] @ (8004a54 ) 800492e: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000 8004932: 6093 str r3, [r2, #8] 8004934: 4b47 ldr r3, [pc, #284] @ (8004a54 ) 8004936: 6f1a ldr r2, [r3, #112] @ 0x70 8004938: 687b ldr r3, [r7, #4] 800493a: 6c1b ldr r3, [r3, #64] @ 0x40 800493c: f3c3 030b ubfx r3, r3, #0, #12 8004940: 4944 ldr r1, [pc, #272] @ (8004a54 ) 8004942: 4313 orrs r3, r2 8004944: 670b str r3, [r1, #112] @ 0x70 } /*--------------------------------------------------------------------------*/ /*---------------------------- TIM configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 8004946: 687b ldr r3, [r7, #4] 8004948: 681b ldr r3, [r3, #0] 800494a: f003 0310 and.w r3, r3, #16 800494e: 2b00 cmp r3, #0 8004950: d004 beq.n 800495c { /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8004952: 687b ldr r3, [r7, #4] 8004954: f893 2058 ldrb.w r2, [r3, #88] @ 0x58 8004958: 4b3f ldr r3, [pc, #252] @ (8004a58 ) 800495a: 601a str r2, [r3, #0] } /*--------------------------------------------------------------------------*/ /*---------------------------- FMPI2C1 Configuration -----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) 800495c: 687b ldr r3, [r7, #4] 800495e: 681b ldr r3, [r3, #0] 8004960: f003 0380 and.w r3, r3, #128 @ 0x80 8004964: 2b00 cmp r3, #0 8004966: d00a beq.n 800497e { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); 8004968: 4b3a ldr r3, [pc, #232] @ (8004a54 ) 800496a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800496e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 8004972: 687b ldr r3, [r7, #4] 8004974: 6cdb ldr r3, [r3, #76] @ 0x4c 8004976: 4937 ldr r1, [pc, #220] @ (8004a54 ) 8004978: 4313 orrs r3, r2 800497a: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ CEC Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800497e: 687b ldr r3, [r7, #4] 8004980: 681b ldr r3, [r3, #0] 8004982: f003 0340 and.w r3, r3, #64 @ 0x40 8004986: 2b00 cmp r3, #0 8004988: d00a beq.n 80049a0 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800498a: 4b32 ldr r3, [pc, #200] @ (8004a54 ) 800498c: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004990: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000 8004994: 687b ldr r3, [r7, #4] 8004996: 6c9b ldr r3, [r3, #72] @ 0x48 8004998: 492e ldr r1, [pc, #184] @ (8004a54 ) 800499a: 4313 orrs r3, r2 800499c: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*----------------------------- CLK48 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 80049a0: 687b ldr r3, [r7, #4] 80049a2: 681b ldr r3, [r3, #0] 80049a4: f403 7380 and.w r3, r3, #256 @ 0x100 80049a8: 2b00 cmp r3, #0 80049aa: d011 beq.n 80049d0 { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); 80049ac: 4b29 ldr r3, [pc, #164] @ (8004a54 ) 80049ae: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80049b2: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000 80049b6: 687b ldr r3, [r7, #4] 80049b8: 6d5b ldr r3, [r3, #84] @ 0x54 80049ba: 4926 ldr r1, [pc, #152] @ (8004a54 ) 80049bc: 4313 orrs r3, r2 80049be: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLSAI when it's used as clock source for CLK48 */ if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) 80049c2: 687b ldr r3, [r7, #4] 80049c4: 6d5b ldr r3, [r3, #84] @ 0x54 80049c6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80049ca: d101 bne.n 80049d0 { pllsaiused = 1U; 80049cc: 2301 movs r3, #1 80049ce: 62bb str r3, [r7, #40] @ 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- SDIO Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) 80049d0: 687b ldr r3, [r7, #4] 80049d2: 681b ldr r3, [r3, #0] 80049d4: f403 7300 and.w r3, r3, #512 @ 0x200 80049d8: 2b00 cmp r3, #0 80049da: d00a beq.n 80049f2 { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); 80049dc: 4b1d ldr r3, [pc, #116] @ (8004a54 ) 80049de: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80049e2: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000 80049e6: 687b ldr r3, [r7, #4] 80049e8: 6c5b ldr r3, [r3, #68] @ 0x44 80049ea: 491a ldr r1, [pc, #104] @ (8004a54 ) 80049ec: 4313 orrs r3, r2 80049ee: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ SPDIFRX Configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 80049f2: 687b ldr r3, [r7, #4] 80049f4: 681b ldr r3, [r3, #0] 80049f6: f403 6380 and.w r3, r3, #1024 @ 0x400 80049fa: 2b00 cmp r3, #0 80049fc: d011 beq.n 8004a22 { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); /* Configure the SPDIFRX clock source */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); 80049fe: 4b15 ldr r3, [pc, #84] @ (8004a54 ) 8004a00: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8004a04: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000 8004a08: 687b ldr r3, [r7, #4] 8004a0a: 6d1b ldr r3, [r3, #80] @ 0x50 8004a0c: 4911 ldr r1, [pc, #68] @ (8004a54 ) 8004a0e: 4313 orrs r3, r2 8004a10: f8c1 3094 str.w r3, [r1, #148] @ 0x94 /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) 8004a14: 687b ldr r3, [r7, #4] 8004a16: 6d1b ldr r3, [r3, #80] @ 0x50 8004a18: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004a1c: d101 bne.n 8004a22 { plli2sused = 1U; 8004a1e: 2301 movs r3, #1 8004a20: 62fb str r3, [r7, #44] @ 0x2c /*--------------------------------------------------------------------------*/ /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) 8004a22: 6afb ldr r3, [r7, #44] @ 0x2c 8004a24: 2b01 cmp r3, #1 8004a26: d005 beq.n 8004a34 8004a28: 687b ldr r3, [r7, #4] 8004a2a: 681b ldr r3, [r3, #0] 8004a2c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8004a30: f040 80ff bne.w 8004c32 { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 8004a34: 4b09 ldr r3, [pc, #36] @ (8004a5c ) 8004a36: 2200 movs r2, #0 8004a38: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004a3a: f7fd fa85 bl 8001f48 8004a3e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004a40: e00e b.n 8004a60 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004a42: f7fd fa81 bl 8001f48 8004a46: 4602 mov r2, r0 8004a48: 6a7b ldr r3, [r7, #36] @ 0x24 8004a4a: 1ad3 subs r3, r2, r3 8004a4c: 2b02 cmp r3, #2 8004a4e: d907 bls.n 8004a60 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004a50: 2303 movs r3, #3 8004a52: e188 b.n 8004d66 8004a54: 40023800 .word 0x40023800 8004a58: 424711e0 .word 0x424711e0 8004a5c: 42470068 .word 0x42470068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004a60: 4b7e ldr r3, [pc, #504] @ (8004c5c ) 8004a62: 681b ldr r3, [r3, #0] 8004a64: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004a68: 2b00 cmp r3, #0 8004a6a: d1ea bne.n 8004a42 /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) 8004a6c: 687b ldr r3, [r7, #4] 8004a6e: 681b ldr r3, [r3, #0] 8004a70: f003 0301 and.w r3, r3, #1 8004a74: 2b00 cmp r3, #0 8004a76: d003 beq.n 8004a80 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8004a78: 687b ldr r3, [r7, #4] 8004a7a: 6b9b ldr r3, [r3, #56] @ 0x38 8004a7c: 2b00 cmp r3, #0 8004a7e: d009 beq.n 8004a94 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 8004a80: 687b ldr r3, [r7, #4] 8004a82: 681b ldr r3, [r3, #0] 8004a84: f003 0302 and.w r3, r3, #2 && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8004a88: 2b00 cmp r3, #0 8004a8a: d028 beq.n 8004ade ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 8004a8c: 687b ldr r3, [r7, #4] 8004a8e: 6bdb ldr r3, [r3, #60] @ 0x3c 8004a90: 2b00 cmp r3, #0 8004a92: d124 bne.n 8004ade { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004a94: 4b71 ldr r3, [pc, #452] @ (8004c5c ) 8004a96: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004a9a: 0c1b lsrs r3, r3, #16 8004a9c: f003 0303 and.w r3, r3, #3 8004aa0: 3301 adds r3, #1 8004aa2: 005b lsls r3, r3, #1 8004aa4: 61fb str r3, [r7, #28] plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); 8004aa6: 4b6d ldr r3, [pc, #436] @ (8004c5c ) 8004aa8: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004aac: 0e1b lsrs r3, r3, #24 8004aae: f003 030f and.w r3, r3, #15 8004ab2: 61bb str r3, [r7, #24] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq, 8004ab4: 687b ldr r3, [r7, #4] 8004ab6: 685a ldr r2, [r3, #4] 8004ab8: 687b ldr r3, [r7, #4] 8004aba: 689b ldr r3, [r3, #8] 8004abc: 019b lsls r3, r3, #6 8004abe: 431a orrs r2, r3 8004ac0: 69fb ldr r3, [r7, #28] 8004ac2: 085b lsrs r3, r3, #1 8004ac4: 3b01 subs r3, #1 8004ac6: 041b lsls r3, r3, #16 8004ac8: 431a orrs r2, r3 8004aca: 69bb ldr r3, [r7, #24] 8004acc: 061b lsls r3, r3, #24 8004ace: 431a orrs r2, r3 8004ad0: 687b ldr r3, [r7, #4] 8004ad2: 695b ldr r3, [r3, #20] 8004ad4: 071b lsls r3, r3, #28 8004ad6: 4961 ldr r1, [pc, #388] @ (8004c5c ) 8004ad8: 4313 orrs r3, r2 8004ada: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SR); } /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8004ade: 687b ldr r3, [r7, #4] 8004ae0: 681b ldr r3, [r3, #0] 8004ae2: f003 0304 and.w r3, r3, #4 8004ae6: 2b00 cmp r3, #0 8004ae8: d004 beq.n 8004af4 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 8004aea: 687b ldr r3, [r7, #4] 8004aec: 6b1b ldr r3, [r3, #48] @ 0x30 8004aee: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8004af2: d00a beq.n 8004b0a ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8004af4: 687b ldr r3, [r7, #4] 8004af6: 681b ldr r3, [r3, #0] 8004af8: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 8004afc: 2b00 cmp r3, #0 8004afe: d035 beq.n 8004b6c ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 8004b00: 687b ldr r3, [r7, #4] 8004b02: 6b5b ldr r3, [r3, #52] @ 0x34 8004b04: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004b08: d130 bne.n 8004b6c assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004b0a: 4b54 ldr r3, [pc, #336] @ (8004c5c ) 8004b0c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004b10: 0c1b lsrs r3, r3, #16 8004b12: f003 0303 and.w r3, r3, #3 8004b16: 3301 adds r3, #1 8004b18: 005b lsls r3, r3, #1 8004b1a: 61fb str r3, [r7, #28] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004b1c: 4b4f ldr r3, [pc, #316] @ (8004c5c ) 8004b1e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004b22: 0f1b lsrs r3, r3, #28 8004b24: f003 0307 and.w r3, r3, #7 8004b28: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, 8004b2a: 687b ldr r3, [r7, #4] 8004b2c: 685a ldr r2, [r3, #4] 8004b2e: 687b ldr r3, [r7, #4] 8004b30: 689b ldr r3, [r3, #8] 8004b32: 019b lsls r3, r3, #6 8004b34: 431a orrs r2, r3 8004b36: 69fb ldr r3, [r7, #28] 8004b38: 085b lsrs r3, r3, #1 8004b3a: 3b01 subs r3, #1 8004b3c: 041b lsls r3, r3, #16 8004b3e: 431a orrs r2, r3 8004b40: 687b ldr r3, [r7, #4] 8004b42: 691b ldr r3, [r3, #16] 8004b44: 061b lsls r3, r3, #24 8004b46: 431a orrs r2, r3 8004b48: 697b ldr r3, [r7, #20] 8004b4a: 071b lsls r3, r3, #28 8004b4c: 4943 ldr r1, [pc, #268] @ (8004c5c ) 8004b4e: 4313 orrs r3, r2 8004b50: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 8004b54: 4b41 ldr r3, [pc, #260] @ (8004c5c ) 8004b56: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004b5a: f023 021f bic.w r2, r3, #31 8004b5e: 687b ldr r3, [r7, #4] 8004b60: 6a9b ldr r3, [r3, #40] @ 0x28 8004b62: 3b01 subs r3, #1 8004b64: 493d ldr r1, [pc, #244] @ (8004c5c ) 8004b66: 4313 orrs r3, r2 8004b68: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8004b6c: 687b ldr r3, [r7, #4] 8004b6e: 681b ldr r3, [r3, #0] 8004b70: f403 6380 and.w r3, r3, #1024 @ 0x400 8004b74: 2b00 cmp r3, #0 8004b76: d029 beq.n 8004bcc && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 8004b78: 687b ldr r3, [r7, #4] 8004b7a: 6d1b ldr r3, [r3, #80] @ 0x50 8004b7c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004b80: d124 bne.n 8004bcc { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8004b82: 4b36 ldr r3, [pc, #216] @ (8004c5c ) 8004b84: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004b88: 0c1b lsrs r3, r3, #16 8004b8a: f003 0303 and.w r3, r3, #3 8004b8e: 3301 adds r3, #1 8004b90: 005b lsls r3, r3, #1 8004b92: 61bb str r3, [r7, #24] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004b94: 4b31 ldr r3, [pc, #196] @ (8004c5c ) 8004b96: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004b9a: 0f1b lsrs r3, r3, #28 8004b9c: f003 0307 and.w r3, r3, #7 8004ba0: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 8004ba2: 687b ldr r3, [r7, #4] 8004ba4: 685a ldr r2, [r3, #4] 8004ba6: 687b ldr r3, [r7, #4] 8004ba8: 689b ldr r3, [r3, #8] 8004baa: 019b lsls r3, r3, #6 8004bac: 431a orrs r2, r3 8004bae: 687b ldr r3, [r7, #4] 8004bb0: 68db ldr r3, [r3, #12] 8004bb2: 085b lsrs r3, r3, #1 8004bb4: 3b01 subs r3, #1 8004bb6: 041b lsls r3, r3, #16 8004bb8: 431a orrs r2, r3 8004bba: 69bb ldr r3, [r7, #24] 8004bbc: 061b lsls r3, r3, #24 8004bbe: 431a orrs r2, r3 8004bc0: 697b ldr r3, [r7, #20] 8004bc2: 071b lsls r3, r3, #28 8004bc4: 4925 ldr r1, [pc, #148] @ (8004c5c ) 8004bc6: 4313 orrs r3, r2 8004bc8: f8c1 3084 str.w r3, [r1, #132] @ 0x84 plli2sq, plli2sr); } /*----------------- In Case of PLLI2S is just selected -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 8004bcc: 687b ldr r3, [r7, #4] 8004bce: 681b ldr r3, [r3, #0] 8004bd0: f403 6300 and.w r3, r3, #2048 @ 0x800 8004bd4: 2b00 cmp r3, #0 8004bd6: d016 beq.n 8004c06 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, 8004bd8: 687b ldr r3, [r7, #4] 8004bda: 685a ldr r2, [r3, #4] 8004bdc: 687b ldr r3, [r7, #4] 8004bde: 689b ldr r3, [r3, #8] 8004be0: 019b lsls r3, r3, #6 8004be2: 431a orrs r2, r3 8004be4: 687b ldr r3, [r7, #4] 8004be6: 68db ldr r3, [r3, #12] 8004be8: 085b lsrs r3, r3, #1 8004bea: 3b01 subs r3, #1 8004bec: 041b lsls r3, r3, #16 8004bee: 431a orrs r2, r3 8004bf0: 687b ldr r3, [r7, #4] 8004bf2: 691b ldr r3, [r3, #16] 8004bf4: 061b lsls r3, r3, #24 8004bf6: 431a orrs r2, r3 8004bf8: 687b ldr r3, [r7, #4] 8004bfa: 695b ldr r3, [r3, #20] 8004bfc: 071b lsls r3, r3, #28 8004bfe: 4917 ldr r1, [pc, #92] @ (8004c5c ) 8004c00: 4313 orrs r3, r2 8004c02: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 8004c06: 4b16 ldr r3, [pc, #88] @ (8004c60 ) 8004c08: 2201 movs r2, #1 8004c0a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004c0c: f7fd f99c bl 8001f48 8004c10: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004c12: e008 b.n 8004c26 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004c14: f7fd f998 bl 8001f48 8004c18: 4602 mov r2, r0 8004c1a: 6a7b ldr r3, [r7, #36] @ 0x24 8004c1c: 1ad3 subs r3, r2, r3 8004c1e: 2b02 cmp r3, #2 8004c20: d901 bls.n 8004c26 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004c22: 2303 movs r3, #3 8004c24: e09f b.n 8004d66 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004c26: 4b0d ldr r3, [pc, #52] @ (8004c5c ) 8004c28: 681b ldr r3, [r3, #0] 8004c2a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004c2e: 2b00 cmp r3, #0 8004c30: d0f0 beq.n 8004c14 } /*--------------------------------------------------------------------------*/ /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ if (pllsaiused == 1U) 8004c32: 6abb ldr r3, [r7, #40] @ 0x28 8004c34: 2b01 cmp r3, #1 8004c36: f040 8095 bne.w 8004d64 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 8004c3a: 4b0a ldr r3, [pc, #40] @ (8004c64 ) 8004c3c: 2200 movs r2, #0 8004c3e: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004c40: f7fd f982 bl 8001f48 8004c44: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is disabled */ while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004c46: e00f b.n 8004c68 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004c48: f7fd f97e bl 8001f48 8004c4c: 4602 mov r2, r0 8004c4e: 6a7b ldr r3, [r7, #36] @ 0x24 8004c50: 1ad3 subs r3, r2, r3 8004c52: 2b02 cmp r3, #2 8004c54: d908 bls.n 8004c68 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004c56: 2303 movs r3, #3 8004c58: e085 b.n 8004d66 8004c5a: bf00 nop 8004c5c: 40023800 .word 0x40023800 8004c60: 42470068 .word 0x42470068 8004c64: 42470070 .word 0x42470070 while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8004c68: 4b41 ldr r3, [pc, #260] @ (8004d70 ) 8004c6a: 681b ldr r3, [r3, #0] 8004c6c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004c70: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004c74: d0e8 beq.n 8004c48 /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8004c76: 687b ldr r3, [r7, #4] 8004c78: 681b ldr r3, [r3, #0] 8004c7a: f003 0304 and.w r3, r3, #4 8004c7e: 2b00 cmp r3, #0 8004c80: d003 beq.n 8004c8a && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8004c82: 687b ldr r3, [r7, #4] 8004c84: 6b1b ldr r3, [r3, #48] @ 0x30 8004c86: 2b00 cmp r3, #0 8004c88: d009 beq.n 8004c9e ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8004c8a: 687b ldr r3, [r7, #4] 8004c8c: 681b ldr r3, [r3, #0] 8004c8e: f003 0308 and.w r3, r3, #8 && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8004c92: 2b00 cmp r3, #0 8004c94: d02b beq.n 8004cee ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8004c96: 687b ldr r3, [r7, #4] 8004c98: 6b5b ldr r3, [r3, #52] @ 0x34 8004c9a: 2b00 cmp r3, #0 8004c9c: d127 bne.n 8004cee assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); 8004c9e: 4b34 ldr r3, [pc, #208] @ (8004d70 ) 8004ca0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004ca4: 0c1b lsrs r3, r3, #16 8004ca6: f003 0303 and.w r3, r3, #3 8004caa: 3301 adds r3, #1 8004cac: 005b lsls r3, r3, #1 8004cae: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, 8004cb0: 687b ldr r3, [r7, #4] 8004cb2: 699a ldr r2, [r3, #24] 8004cb4: 687b ldr r3, [r7, #4] 8004cb6: 69db ldr r3, [r3, #28] 8004cb8: 019b lsls r3, r3, #6 8004cba: 431a orrs r2, r3 8004cbc: 693b ldr r3, [r7, #16] 8004cbe: 085b lsrs r3, r3, #1 8004cc0: 3b01 subs r3, #1 8004cc2: 041b lsls r3, r3, #16 8004cc4: 431a orrs r2, r3 8004cc6: 687b ldr r3, [r7, #4] 8004cc8: 6a5b ldr r3, [r3, #36] @ 0x24 8004cca: 061b lsls r3, r3, #24 8004ccc: 4928 ldr r1, [pc, #160] @ (8004d70 ) 8004cce: 4313 orrs r3, r2 8004cd0: f8c1 3088 str.w r3, [r1, #136] @ 0x88 PeriphClkInit->PLLSAI.PLLSAIQ, 0U); /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 8004cd4: 4b26 ldr r3, [pc, #152] @ (8004d70 ) 8004cd6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004cda: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 8004cde: 687b ldr r3, [r7, #4] 8004ce0: 6adb ldr r3, [r3, #44] @ 0x2c 8004ce2: 3b01 subs r3, #1 8004ce4: 021b lsls r3, r3, #8 8004ce6: 4922 ldr r1, [pc, #136] @ (8004d70 ) 8004ce8: 4313 orrs r3, r2 8004cea: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ /* In Case of PLLI2S is selected as source clock for CLK48 */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 8004cee: 687b ldr r3, [r7, #4] 8004cf0: 681b ldr r3, [r3, #0] 8004cf2: f403 7380 and.w r3, r3, #256 @ 0x100 8004cf6: 2b00 cmp r3, #0 8004cf8: d01d beq.n 8004d36 && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) 8004cfa: 687b ldr r3, [r7, #4] 8004cfc: 6d5b ldr r3, [r3, #84] @ 0x54 8004cfe: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8004d02: d118 bne.n 8004d36 { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 8004d04: 4b1a ldr r3, [pc, #104] @ (8004d70 ) 8004d06: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004d0a: 0e1b lsrs r3, r3, #24 8004d0c: f003 030f and.w r3, r3, #15 8004d10: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, 8004d12: 687b ldr r3, [r7, #4] 8004d14: 699a ldr r2, [r3, #24] 8004d16: 687b ldr r3, [r7, #4] 8004d18: 69db ldr r3, [r3, #28] 8004d1a: 019b lsls r3, r3, #6 8004d1c: 431a orrs r2, r3 8004d1e: 687b ldr r3, [r7, #4] 8004d20: 6a1b ldr r3, [r3, #32] 8004d22: 085b lsrs r3, r3, #1 8004d24: 3b01 subs r3, #1 8004d26: 041b lsls r3, r3, #16 8004d28: 431a orrs r2, r3 8004d2a: 68fb ldr r3, [r7, #12] 8004d2c: 061b lsls r3, r3, #24 8004d2e: 4910 ldr r1, [pc, #64] @ (8004d70 ) 8004d30: 4313 orrs r3, r2 8004d32: f8c1 3088 str.w r3, [r1, #136] @ 0x88 pllsaiq, 0U); } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 8004d36: 4b0f ldr r3, [pc, #60] @ (8004d74 ) 8004d38: 2201 movs r2, #1 8004d3a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004d3c: f7fd f904 bl 8001f48 8004d40: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLLSAI is ready */ while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004d42: e008 b.n 8004d56 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8004d44: f7fd f900 bl 8001f48 8004d48: 4602 mov r2, r0 8004d4a: 6a7b ldr r3, [r7, #36] @ 0x24 8004d4c: 1ad3 subs r3, r2, r3 8004d4e: 2b02 cmp r3, #2 8004d50: d901 bls.n 8004d56 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004d52: 2303 movs r3, #3 8004d54: e007 b.n 8004d66 while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8004d56: 4b06 ldr r3, [pc, #24] @ (8004d70 ) 8004d58: 681b ldr r3, [r3, #0] 8004d5a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004d5e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004d62: d1ef bne.n 8004d44 } } } return HAL_OK; 8004d64: 2300 movs r3, #0 } 8004d66: 4618 mov r0, r3 8004d68: 3730 adds r7, #48 @ 0x30 8004d6a: 46bd mov sp, r7 8004d6c: bd80 pop {r7, pc} 8004d6e: bf00 nop 8004d70: 40023800 .word 0x40023800 8004d74: 42470070 .word 0x42470070 08004d78 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8004d78: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8004d7c: b0ae sub sp, #184 @ 0xb8 8004d7e: af00 add r7, sp, #0 uint32_t pllm = 0U; 8004d80: 2300 movs r3, #0 8004d82: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t pllvco = 0U; 8004d86: 2300 movs r3, #0 8004d88: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t pllp = 0U; 8004d8c: 2300 movs r3, #0 8004d8e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 uint32_t pllr = 0U; 8004d92: 2300 movs r3, #0 8004d94: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t sysclockfreq = 0U; 8004d98: 2300 movs r3, #0 8004d9a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8004d9e: 4bcb ldr r3, [pc, #812] @ (80050cc ) 8004da0: 689b ldr r3, [r3, #8] 8004da2: f003 030c and.w r3, r3, #12 8004da6: 2b0c cmp r3, #12 8004da8: f200 8206 bhi.w 80051b8 8004dac: a201 add r2, pc, #4 @ (adr r2, 8004db4 ) 8004dae: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004db2: bf00 nop 8004db4: 08004de9 .word 0x08004de9 8004db8: 080051b9 .word 0x080051b9 8004dbc: 080051b9 .word 0x080051b9 8004dc0: 080051b9 .word 0x080051b9 8004dc4: 08004df1 .word 0x08004df1 8004dc8: 080051b9 .word 0x080051b9 8004dcc: 080051b9 .word 0x080051b9 8004dd0: 080051b9 .word 0x080051b9 8004dd4: 08004df9 .word 0x08004df9 8004dd8: 080051b9 .word 0x080051b9 8004ddc: 080051b9 .word 0x080051b9 8004de0: 080051b9 .word 0x080051b9 8004de4: 08004fe9 .word 0x08004fe9 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8004de8: 4bb9 ldr r3, [pc, #740] @ (80050d0 ) 8004dea: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004dee: e1e7 b.n 80051c0 } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 8004df0: 4bb8 ldr r3, [pc, #736] @ (80050d4 ) 8004df2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004df6: e1e3 b.n 80051c0 } case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004df8: 4bb4 ldr r3, [pc, #720] @ (80050cc ) 8004dfa: 685b ldr r3, [r3, #4] 8004dfc: f003 033f and.w r3, r3, #63 @ 0x3f 8004e00: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004e04: 4bb1 ldr r3, [pc, #708] @ (80050cc ) 8004e06: 685b ldr r3, [r3, #4] 8004e08: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004e0c: 2b00 cmp r3, #0 8004e0e: d071 beq.n 8004ef4 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004e10: 4bae ldr r3, [pc, #696] @ (80050cc ) 8004e12: 685b ldr r3, [r3, #4] 8004e14: 099b lsrs r3, r3, #6 8004e16: 2200 movs r2, #0 8004e18: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8004e1c: f8c7 209c str.w r2, [r7, #156] @ 0x9c 8004e20: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8004e24: f3c3 0308 ubfx r3, r3, #0, #9 8004e28: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8004e2c: 2300 movs r3, #0 8004e2e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8004e32: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8004e36: 4622 mov r2, r4 8004e38: 462b mov r3, r5 8004e3a: f04f 0000 mov.w r0, #0 8004e3e: f04f 0100 mov.w r1, #0 8004e42: 0159 lsls r1, r3, #5 8004e44: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004e48: 0150 lsls r0, r2, #5 8004e4a: 4602 mov r2, r0 8004e4c: 460b mov r3, r1 8004e4e: 4621 mov r1, r4 8004e50: 1a51 subs r1, r2, r1 8004e52: 6439 str r1, [r7, #64] @ 0x40 8004e54: 4629 mov r1, r5 8004e56: eb63 0301 sbc.w r3, r3, r1 8004e5a: 647b str r3, [r7, #68] @ 0x44 8004e5c: f04f 0200 mov.w r2, #0 8004e60: f04f 0300 mov.w r3, #0 8004e64: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40 8004e68: 4649 mov r1, r9 8004e6a: 018b lsls r3, r1, #6 8004e6c: 4641 mov r1, r8 8004e6e: ea43 6391 orr.w r3, r3, r1, lsr #26 8004e72: 4641 mov r1, r8 8004e74: 018a lsls r2, r1, #6 8004e76: 4641 mov r1, r8 8004e78: 1a51 subs r1, r2, r1 8004e7a: 63b9 str r1, [r7, #56] @ 0x38 8004e7c: 4649 mov r1, r9 8004e7e: eb63 0301 sbc.w r3, r3, r1 8004e82: 63fb str r3, [r7, #60] @ 0x3c 8004e84: f04f 0200 mov.w r2, #0 8004e88: f04f 0300 mov.w r3, #0 8004e8c: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38 8004e90: 4649 mov r1, r9 8004e92: 00cb lsls r3, r1, #3 8004e94: 4641 mov r1, r8 8004e96: ea43 7351 orr.w r3, r3, r1, lsr #29 8004e9a: 4641 mov r1, r8 8004e9c: 00ca lsls r2, r1, #3 8004e9e: 4610 mov r0, r2 8004ea0: 4619 mov r1, r3 8004ea2: 4603 mov r3, r0 8004ea4: 4622 mov r2, r4 8004ea6: 189b adds r3, r3, r2 8004ea8: 633b str r3, [r7, #48] @ 0x30 8004eaa: 462b mov r3, r5 8004eac: 460a mov r2, r1 8004eae: eb42 0303 adc.w r3, r2, r3 8004eb2: 637b str r3, [r7, #52] @ 0x34 8004eb4: f04f 0200 mov.w r2, #0 8004eb8: f04f 0300 mov.w r3, #0 8004ebc: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 8004ec0: 4629 mov r1, r5 8004ec2: 024b lsls r3, r1, #9 8004ec4: 4621 mov r1, r4 8004ec6: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004eca: 4621 mov r1, r4 8004ecc: 024a lsls r2, r1, #9 8004ece: 4610 mov r0, r2 8004ed0: 4619 mov r1, r3 8004ed2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004ed6: 2200 movs r2, #0 8004ed8: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8004edc: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8004ee0: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88 8004ee4: f7fb f98e bl 8000204 <__aeabi_uldivmod> 8004ee8: 4602 mov r2, r0 8004eea: 460b mov r3, r1 8004eec: 4613 mov r3, r2 8004eee: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8004ef2: e067 b.n 8004fc4 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004ef4: 4b75 ldr r3, [pc, #468] @ (80050cc ) 8004ef6: 685b ldr r3, [r3, #4] 8004ef8: 099b lsrs r3, r3, #6 8004efa: 2200 movs r2, #0 8004efc: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8004f00: f8c7 2084 str.w r2, [r7, #132] @ 0x84 8004f04: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8004f08: f3c3 0308 ubfx r3, r3, #0, #9 8004f0c: 67bb str r3, [r7, #120] @ 0x78 8004f0e: 2300 movs r3, #0 8004f10: 67fb str r3, [r7, #124] @ 0x7c 8004f12: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78 8004f16: 4622 mov r2, r4 8004f18: 462b mov r3, r5 8004f1a: f04f 0000 mov.w r0, #0 8004f1e: f04f 0100 mov.w r1, #0 8004f22: 0159 lsls r1, r3, #5 8004f24: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004f28: 0150 lsls r0, r2, #5 8004f2a: 4602 mov r2, r0 8004f2c: 460b mov r3, r1 8004f2e: 4621 mov r1, r4 8004f30: 1a51 subs r1, r2, r1 8004f32: 62b9 str r1, [r7, #40] @ 0x28 8004f34: 4629 mov r1, r5 8004f36: eb63 0301 sbc.w r3, r3, r1 8004f3a: 62fb str r3, [r7, #44] @ 0x2c 8004f3c: f04f 0200 mov.w r2, #0 8004f40: f04f 0300 mov.w r3, #0 8004f44: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28 8004f48: 4649 mov r1, r9 8004f4a: 018b lsls r3, r1, #6 8004f4c: 4641 mov r1, r8 8004f4e: ea43 6391 orr.w r3, r3, r1, lsr #26 8004f52: 4641 mov r1, r8 8004f54: 018a lsls r2, r1, #6 8004f56: 4641 mov r1, r8 8004f58: ebb2 0a01 subs.w sl, r2, r1 8004f5c: 4649 mov r1, r9 8004f5e: eb63 0b01 sbc.w fp, r3, r1 8004f62: f04f 0200 mov.w r2, #0 8004f66: f04f 0300 mov.w r3, #0 8004f6a: ea4f 03cb mov.w r3, fp, lsl #3 8004f6e: ea43 735a orr.w r3, r3, sl, lsr #29 8004f72: ea4f 02ca mov.w r2, sl, lsl #3 8004f76: 4692 mov sl, r2 8004f78: 469b mov fp, r3 8004f7a: 4623 mov r3, r4 8004f7c: eb1a 0303 adds.w r3, sl, r3 8004f80: 623b str r3, [r7, #32] 8004f82: 462b mov r3, r5 8004f84: eb4b 0303 adc.w r3, fp, r3 8004f88: 627b str r3, [r7, #36] @ 0x24 8004f8a: f04f 0200 mov.w r2, #0 8004f8e: f04f 0300 mov.w r3, #0 8004f92: e9d7 4508 ldrd r4, r5, [r7, #32] 8004f96: 4629 mov r1, r5 8004f98: 028b lsls r3, r1, #10 8004f9a: 4621 mov r1, r4 8004f9c: ea43 5391 orr.w r3, r3, r1, lsr #22 8004fa0: 4621 mov r1, r4 8004fa2: 028a lsls r2, r1, #10 8004fa4: 4610 mov r0, r2 8004fa6: 4619 mov r1, r3 8004fa8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004fac: 2200 movs r2, #0 8004fae: 673b str r3, [r7, #112] @ 0x70 8004fb0: 677a str r2, [r7, #116] @ 0x74 8004fb2: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70 8004fb6: f7fb f925 bl 8000204 <__aeabi_uldivmod> 8004fba: 4602 mov r2, r0 8004fbc: 460b mov r3, r1 8004fbe: 4613 mov r3, r2 8004fc0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); 8004fc4: 4b41 ldr r3, [pc, #260] @ (80050cc ) 8004fc6: 685b ldr r3, [r3, #4] 8004fc8: 0c1b lsrs r3, r3, #16 8004fca: f003 0303 and.w r3, r3, #3 8004fce: 3301 adds r3, #1 8004fd0: 005b lsls r3, r3, #1 8004fd2: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 sysclockfreq = pllvco / pllp; 8004fd6: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8004fda: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8004fde: fbb2 f3f3 udiv r3, r2, r3 8004fe2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 8004fe6: e0eb b.n 80051c0 } case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004fe8: 4b38 ldr r3, [pc, #224] @ (80050cc ) 8004fea: 685b ldr r3, [r3, #4] 8004fec: f003 033f and.w r3, r3, #63 @ 0x3f 8004ff0: f8c7 30ac str.w r3, [r7, #172] @ 0xac if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004ff4: 4b35 ldr r3, [pc, #212] @ (80050cc ) 8004ff6: 685b ldr r3, [r3, #4] 8004ff8: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004ffc: 2b00 cmp r3, #0 8004ffe: d06b beq.n 80050d8 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8005000: 4b32 ldr r3, [pc, #200] @ (80050cc ) 8005002: 685b ldr r3, [r3, #4] 8005004: 099b lsrs r3, r3, #6 8005006: 2200 movs r2, #0 8005008: 66bb str r3, [r7, #104] @ 0x68 800500a: 66fa str r2, [r7, #108] @ 0x6c 800500c: 6ebb ldr r3, [r7, #104] @ 0x68 800500e: f3c3 0308 ubfx r3, r3, #0, #9 8005012: 663b str r3, [r7, #96] @ 0x60 8005014: 2300 movs r3, #0 8005016: 667b str r3, [r7, #100] @ 0x64 8005018: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60 800501c: 4622 mov r2, r4 800501e: 462b mov r3, r5 8005020: f04f 0000 mov.w r0, #0 8005024: f04f 0100 mov.w r1, #0 8005028: 0159 lsls r1, r3, #5 800502a: ea41 61d2 orr.w r1, r1, r2, lsr #27 800502e: 0150 lsls r0, r2, #5 8005030: 4602 mov r2, r0 8005032: 460b mov r3, r1 8005034: 4621 mov r1, r4 8005036: 1a51 subs r1, r2, r1 8005038: 61b9 str r1, [r7, #24] 800503a: 4629 mov r1, r5 800503c: eb63 0301 sbc.w r3, r3, r1 8005040: 61fb str r3, [r7, #28] 8005042: f04f 0200 mov.w r2, #0 8005046: f04f 0300 mov.w r3, #0 800504a: e9d7 ab06 ldrd sl, fp, [r7, #24] 800504e: 4659 mov r1, fp 8005050: 018b lsls r3, r1, #6 8005052: 4651 mov r1, sl 8005054: ea43 6391 orr.w r3, r3, r1, lsr #26 8005058: 4651 mov r1, sl 800505a: 018a lsls r2, r1, #6 800505c: 4651 mov r1, sl 800505e: ebb2 0801 subs.w r8, r2, r1 8005062: 4659 mov r1, fp 8005064: eb63 0901 sbc.w r9, r3, r1 8005068: f04f 0200 mov.w r2, #0 800506c: f04f 0300 mov.w r3, #0 8005070: ea4f 03c9 mov.w r3, r9, lsl #3 8005074: ea43 7358 orr.w r3, r3, r8, lsr #29 8005078: ea4f 02c8 mov.w r2, r8, lsl #3 800507c: 4690 mov r8, r2 800507e: 4699 mov r9, r3 8005080: 4623 mov r3, r4 8005082: eb18 0303 adds.w r3, r8, r3 8005086: 613b str r3, [r7, #16] 8005088: 462b mov r3, r5 800508a: eb49 0303 adc.w r3, r9, r3 800508e: 617b str r3, [r7, #20] 8005090: f04f 0200 mov.w r2, #0 8005094: f04f 0300 mov.w r3, #0 8005098: e9d7 4504 ldrd r4, r5, [r7, #16] 800509c: 4629 mov r1, r5 800509e: 024b lsls r3, r1, #9 80050a0: 4621 mov r1, r4 80050a2: ea43 53d1 orr.w r3, r3, r1, lsr #23 80050a6: 4621 mov r1, r4 80050a8: 024a lsls r2, r1, #9 80050aa: 4610 mov r0, r2 80050ac: 4619 mov r1, r3 80050ae: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80050b2: 2200 movs r2, #0 80050b4: 65bb str r3, [r7, #88] @ 0x58 80050b6: 65fa str r2, [r7, #92] @ 0x5c 80050b8: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 80050bc: f7fb f8a2 bl 8000204 <__aeabi_uldivmod> 80050c0: 4602 mov r2, r0 80050c2: 460b mov r3, r1 80050c4: 4613 mov r3, r2 80050c6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 80050ca: e065 b.n 8005198 80050cc: 40023800 .word 0x40023800 80050d0: 00f42400 .word 0x00f42400 80050d4: 007a1200 .word 0x007a1200 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 80050d8: 4b3d ldr r3, [pc, #244] @ (80051d0 ) 80050da: 685b ldr r3, [r3, #4] 80050dc: 099b lsrs r3, r3, #6 80050de: 2200 movs r2, #0 80050e0: 4618 mov r0, r3 80050e2: 4611 mov r1, r2 80050e4: f3c0 0308 ubfx r3, r0, #0, #9 80050e8: 653b str r3, [r7, #80] @ 0x50 80050ea: 2300 movs r3, #0 80050ec: 657b str r3, [r7, #84] @ 0x54 80050ee: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50 80050f2: 4642 mov r2, r8 80050f4: 464b mov r3, r9 80050f6: f04f 0000 mov.w r0, #0 80050fa: f04f 0100 mov.w r1, #0 80050fe: 0159 lsls r1, r3, #5 8005100: ea41 61d2 orr.w r1, r1, r2, lsr #27 8005104: 0150 lsls r0, r2, #5 8005106: 4602 mov r2, r0 8005108: 460b mov r3, r1 800510a: 4641 mov r1, r8 800510c: 1a51 subs r1, r2, r1 800510e: 60b9 str r1, [r7, #8] 8005110: 4649 mov r1, r9 8005112: eb63 0301 sbc.w r3, r3, r1 8005116: 60fb str r3, [r7, #12] 8005118: f04f 0200 mov.w r2, #0 800511c: f04f 0300 mov.w r3, #0 8005120: e9d7 ab02 ldrd sl, fp, [r7, #8] 8005124: 4659 mov r1, fp 8005126: 018b lsls r3, r1, #6 8005128: 4651 mov r1, sl 800512a: ea43 6391 orr.w r3, r3, r1, lsr #26 800512e: 4651 mov r1, sl 8005130: 018a lsls r2, r1, #6 8005132: 4651 mov r1, sl 8005134: 1a54 subs r4, r2, r1 8005136: 4659 mov r1, fp 8005138: eb63 0501 sbc.w r5, r3, r1 800513c: f04f 0200 mov.w r2, #0 8005140: f04f 0300 mov.w r3, #0 8005144: 00eb lsls r3, r5, #3 8005146: ea43 7354 orr.w r3, r3, r4, lsr #29 800514a: 00e2 lsls r2, r4, #3 800514c: 4614 mov r4, r2 800514e: 461d mov r5, r3 8005150: 4643 mov r3, r8 8005152: 18e3 adds r3, r4, r3 8005154: 603b str r3, [r7, #0] 8005156: 464b mov r3, r9 8005158: eb45 0303 adc.w r3, r5, r3 800515c: 607b str r3, [r7, #4] 800515e: f04f 0200 mov.w r2, #0 8005162: f04f 0300 mov.w r3, #0 8005166: e9d7 4500 ldrd r4, r5, [r7] 800516a: 4629 mov r1, r5 800516c: 028b lsls r3, r1, #10 800516e: 4621 mov r1, r4 8005170: ea43 5391 orr.w r3, r3, r1, lsr #22 8005174: 4621 mov r1, r4 8005176: 028a lsls r2, r1, #10 8005178: 4610 mov r0, r2 800517a: 4619 mov r1, r3 800517c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8005180: 2200 movs r2, #0 8005182: 64bb str r3, [r7, #72] @ 0x48 8005184: 64fa str r2, [r7, #76] @ 0x4c 8005186: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 800518a: f7fb f83b bl 8000204 <__aeabi_uldivmod> 800518e: 4602 mov r2, r0 8005190: 460b mov r3, r1 8005192: 4613 mov r3, r2 8005194: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 } pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); 8005198: 4b0d ldr r3, [pc, #52] @ (80051d0 ) 800519a: 685b ldr r3, [r3, #4] 800519c: 0f1b lsrs r3, r3, #28 800519e: f003 0307 and.w r3, r3, #7 80051a2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 sysclockfreq = pllvco / pllr; 80051a6: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 80051aa: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 80051ae: fbb2 f3f3 udiv r3, r2, r3 80051b2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 80051b6: e003 b.n 80051c0 } default: { sysclockfreq = HSI_VALUE; 80051b8: 4b06 ldr r3, [pc, #24] @ (80051d4 ) 80051ba: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 break; 80051be: bf00 nop } } return sysclockfreq; 80051c0: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 } 80051c4: 4618 mov r0, r3 80051c6: 37b8 adds r7, #184 @ 0xb8 80051c8: 46bd mov sp, r7 80051ca: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 80051ce: bf00 nop 80051d0: 40023800 .word 0x40023800 80051d4: 00f42400 .word 0x00f42400 080051d8 : * @note This function add the PLL/PLLR factor management during PLL configuration this feature * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 80051d8: b580 push {r7, lr} 80051da: b086 sub sp, #24 80051dc: af00 add r7, sp, #0 80051de: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 80051e0: 687b ldr r3, [r7, #4] 80051e2: 2b00 cmp r3, #0 80051e4: d101 bne.n 80051ea { return HAL_ERROR; 80051e6: 2301 movs r3, #1 80051e8: e28d b.n 8005706 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80051ea: 687b ldr r3, [r7, #4] 80051ec: 681b ldr r3, [r3, #0] 80051ee: f003 0301 and.w r3, r3, #1 80051f2: 2b00 cmp r3, #0 80051f4: f000 8083 beq.w 80052fe { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 80051f8: 4b94 ldr r3, [pc, #592] @ (800544c ) 80051fa: 689b ldr r3, [r3, #8] 80051fc: f003 030c and.w r3, r3, #12 8005200: 2b04 cmp r3, #4 8005202: d019 beq.n 8005238 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8005204: 4b91 ldr r3, [pc, #580] @ (800544c ) 8005206: 689b ldr r3, [r3, #8] 8005208: f003 030c and.w r3, r3, #12 || \ 800520c: 2b08 cmp r3, #8 800520e: d106 bne.n 800521e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8005210: 4b8e ldr r3, [pc, #568] @ (800544c ) 8005212: 685b ldr r3, [r3, #4] 8005214: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8005218: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800521c: d00c beq.n 8005238 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 800521e: 4b8b ldr r3, [pc, #556] @ (800544c ) 8005220: 689b ldr r3, [r3, #8] 8005222: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ 8005226: 2b0c cmp r3, #12 8005228: d112 bne.n 8005250 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 800522a: 4b88 ldr r3, [pc, #544] @ (800544c ) 800522c: 685b ldr r3, [r3, #4] 800522e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8005232: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8005236: d10b bne.n 8005250 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) #endif /* STM32F446xx */ { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8005238: 4b84 ldr r3, [pc, #528] @ (800544c ) 800523a: 681b ldr r3, [r3, #0] 800523c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005240: 2b00 cmp r3, #0 8005242: d05b beq.n 80052fc 8005244: 687b ldr r3, [r7, #4] 8005246: 685b ldr r3, [r3, #4] 8005248: 2b00 cmp r3, #0 800524a: d157 bne.n 80052fc { return HAL_ERROR; 800524c: 2301 movs r3, #1 800524e: e25a b.n 8005706 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8005250: 687b ldr r3, [r7, #4] 8005252: 685b ldr r3, [r3, #4] 8005254: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8005258: d106 bne.n 8005268 800525a: 4b7c ldr r3, [pc, #496] @ (800544c ) 800525c: 681b ldr r3, [r3, #0] 800525e: 4a7b ldr r2, [pc, #492] @ (800544c ) 8005260: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8005264: 6013 str r3, [r2, #0] 8005266: e01d b.n 80052a4 8005268: 687b ldr r3, [r7, #4] 800526a: 685b ldr r3, [r3, #4] 800526c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8005270: d10c bne.n 800528c 8005272: 4b76 ldr r3, [pc, #472] @ (800544c ) 8005274: 681b ldr r3, [r3, #0] 8005276: 4a75 ldr r2, [pc, #468] @ (800544c ) 8005278: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800527c: 6013 str r3, [r2, #0] 800527e: 4b73 ldr r3, [pc, #460] @ (800544c ) 8005280: 681b ldr r3, [r3, #0] 8005282: 4a72 ldr r2, [pc, #456] @ (800544c ) 8005284: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8005288: 6013 str r3, [r2, #0] 800528a: e00b b.n 80052a4 800528c: 4b6f ldr r3, [pc, #444] @ (800544c ) 800528e: 681b ldr r3, [r3, #0] 8005290: 4a6e ldr r2, [pc, #440] @ (800544c ) 8005292: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8005296: 6013 str r3, [r2, #0] 8005298: 4b6c ldr r3, [pc, #432] @ (800544c ) 800529a: 681b ldr r3, [r3, #0] 800529c: 4a6b ldr r2, [pc, #428] @ (800544c ) 800529e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 80052a2: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 80052a4: 687b ldr r3, [r7, #4] 80052a6: 685b ldr r3, [r3, #4] 80052a8: 2b00 cmp r3, #0 80052aa: d013 beq.n 80052d4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80052ac: f7fc fe4c bl 8001f48 80052b0: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80052b2: e008 b.n 80052c6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80052b4: f7fc fe48 bl 8001f48 80052b8: 4602 mov r2, r0 80052ba: 693b ldr r3, [r7, #16] 80052bc: 1ad3 subs r3, r2, r3 80052be: 2b64 cmp r3, #100 @ 0x64 80052c0: d901 bls.n 80052c6 { return HAL_TIMEOUT; 80052c2: 2303 movs r3, #3 80052c4: e21f b.n 8005706 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80052c6: 4b61 ldr r3, [pc, #388] @ (800544c ) 80052c8: 681b ldr r3, [r3, #0] 80052ca: f403 3300 and.w r3, r3, #131072 @ 0x20000 80052ce: 2b00 cmp r3, #0 80052d0: d0f0 beq.n 80052b4 80052d2: e014 b.n 80052fe } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80052d4: f7fc fe38 bl 8001f48 80052d8: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80052da: e008 b.n 80052ee { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80052dc: f7fc fe34 bl 8001f48 80052e0: 4602 mov r2, r0 80052e2: 693b ldr r3, [r7, #16] 80052e4: 1ad3 subs r3, r2, r3 80052e6: 2b64 cmp r3, #100 @ 0x64 80052e8: d901 bls.n 80052ee { return HAL_TIMEOUT; 80052ea: 2303 movs r3, #3 80052ec: e20b b.n 8005706 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80052ee: 4b57 ldr r3, [pc, #348] @ (800544c ) 80052f0: 681b ldr r3, [r3, #0] 80052f2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80052f6: 2b00 cmp r3, #0 80052f8: d1f0 bne.n 80052dc 80052fa: e000 b.n 80052fe if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80052fc: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80052fe: 687b ldr r3, [r7, #4] 8005300: 681b ldr r3, [r3, #0] 8005302: f003 0302 and.w r3, r3, #2 8005306: 2b00 cmp r3, #0 8005308: d06f beq.n 80053ea assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ #if defined(STM32F446xx) if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 800530a: 4b50 ldr r3, [pc, #320] @ (800544c ) 800530c: 689b ldr r3, [r3, #8] 800530e: f003 030c and.w r3, r3, #12 8005312: 2b00 cmp r3, #0 8005314: d017 beq.n 8005346 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8005316: 4b4d ldr r3, [pc, #308] @ (800544c ) 8005318: 689b ldr r3, [r3, #8] 800531a: f003 030c and.w r3, r3, #12 || \ 800531e: 2b08 cmp r3, #8 8005320: d105 bne.n 800532e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8005322: 4b4a ldr r3, [pc, #296] @ (800544c ) 8005324: 685b ldr r3, [r3, #4] 8005326: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800532a: 2b00 cmp r3, #0 800532c: d00b beq.n 8005346 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 800532e: 4b47 ldr r3, [pc, #284] @ (800544c ) 8005330: 689b ldr r3, [r3, #8] 8005332: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ 8005336: 2b0c cmp r3, #12 8005338: d11c bne.n 8005374 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 800533a: 4b44 ldr r3, [pc, #272] @ (800544c ) 800533c: 685b ldr r3, [r3, #4] 800533e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8005342: 2b00 cmp r3, #0 8005344: d116 bne.n 8005374 || \ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) #endif /* STM32F446xx */ { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8005346: 4b41 ldr r3, [pc, #260] @ (800544c ) 8005348: 681b ldr r3, [r3, #0] 800534a: f003 0302 and.w r3, r3, #2 800534e: 2b00 cmp r3, #0 8005350: d005 beq.n 800535e 8005352: 687b ldr r3, [r7, #4] 8005354: 68db ldr r3, [r3, #12] 8005356: 2b01 cmp r3, #1 8005358: d001 beq.n 800535e { return HAL_ERROR; 800535a: 2301 movs r3, #1 800535c: e1d3 b.n 8005706 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800535e: 4b3b ldr r3, [pc, #236] @ (800544c ) 8005360: 681b ldr r3, [r3, #0] 8005362: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8005366: 687b ldr r3, [r7, #4] 8005368: 691b ldr r3, [r3, #16] 800536a: 00db lsls r3, r3, #3 800536c: 4937 ldr r1, [pc, #220] @ (800544c ) 800536e: 4313 orrs r3, r2 8005370: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8005372: e03a b.n 80053ea } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8005374: 687b ldr r3, [r7, #4] 8005376: 68db ldr r3, [r3, #12] 8005378: 2b00 cmp r3, #0 800537a: d020 beq.n 80053be { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 800537c: 4b34 ldr r3, [pc, #208] @ (8005450 ) 800537e: 2201 movs r2, #1 8005380: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005382: f7fc fde1 bl 8001f48 8005386: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8005388: e008 b.n 800539c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800538a: f7fc fddd bl 8001f48 800538e: 4602 mov r2, r0 8005390: 693b ldr r3, [r7, #16] 8005392: 1ad3 subs r3, r2, r3 8005394: 2b02 cmp r3, #2 8005396: d901 bls.n 800539c { return HAL_TIMEOUT; 8005398: 2303 movs r3, #3 800539a: e1b4 b.n 8005706 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800539c: 4b2b ldr r3, [pc, #172] @ (800544c ) 800539e: 681b ldr r3, [r3, #0] 80053a0: f003 0302 and.w r3, r3, #2 80053a4: 2b00 cmp r3, #0 80053a6: d0f0 beq.n 800538a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80053a8: 4b28 ldr r3, [pc, #160] @ (800544c ) 80053aa: 681b ldr r3, [r3, #0] 80053ac: f023 02f8 bic.w r2, r3, #248 @ 0xf8 80053b0: 687b ldr r3, [r7, #4] 80053b2: 691b ldr r3, [r3, #16] 80053b4: 00db lsls r3, r3, #3 80053b6: 4925 ldr r1, [pc, #148] @ (800544c ) 80053b8: 4313 orrs r3, r2 80053ba: 600b str r3, [r1, #0] 80053bc: e015 b.n 80053ea } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80053be: 4b24 ldr r3, [pc, #144] @ (8005450 ) 80053c0: 2200 movs r2, #0 80053c2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80053c4: f7fc fdc0 bl 8001f48 80053c8: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80053ca: e008 b.n 80053de { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80053cc: f7fc fdbc bl 8001f48 80053d0: 4602 mov r2, r0 80053d2: 693b ldr r3, [r7, #16] 80053d4: 1ad3 subs r3, r2, r3 80053d6: 2b02 cmp r3, #2 80053d8: d901 bls.n 80053de { return HAL_TIMEOUT; 80053da: 2303 movs r3, #3 80053dc: e193 b.n 8005706 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80053de: 4b1b ldr r3, [pc, #108] @ (800544c ) 80053e0: 681b ldr r3, [r3, #0] 80053e2: f003 0302 and.w r3, r3, #2 80053e6: 2b00 cmp r3, #0 80053e8: d1f0 bne.n 80053cc } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80053ea: 687b ldr r3, [r7, #4] 80053ec: 681b ldr r3, [r3, #0] 80053ee: f003 0308 and.w r3, r3, #8 80053f2: 2b00 cmp r3, #0 80053f4: d036 beq.n 8005464 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 80053f6: 687b ldr r3, [r7, #4] 80053f8: 695b ldr r3, [r3, #20] 80053fa: 2b00 cmp r3, #0 80053fc: d016 beq.n 800542c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80053fe: 4b15 ldr r3, [pc, #84] @ (8005454 ) 8005400: 2201 movs r2, #1 8005402: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005404: f7fc fda0 bl 8001f48 8005408: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800540a: e008 b.n 800541e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800540c: f7fc fd9c bl 8001f48 8005410: 4602 mov r2, r0 8005412: 693b ldr r3, [r7, #16] 8005414: 1ad3 subs r3, r2, r3 8005416: 2b02 cmp r3, #2 8005418: d901 bls.n 800541e { return HAL_TIMEOUT; 800541a: 2303 movs r3, #3 800541c: e173 b.n 8005706 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800541e: 4b0b ldr r3, [pc, #44] @ (800544c ) 8005420: 6f5b ldr r3, [r3, #116] @ 0x74 8005422: f003 0302 and.w r3, r3, #2 8005426: 2b00 cmp r3, #0 8005428: d0f0 beq.n 800540c 800542a: e01b b.n 8005464 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800542c: 4b09 ldr r3, [pc, #36] @ (8005454 ) 800542e: 2200 movs r2, #0 8005430: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005432: f7fc fd89 bl 8001f48 8005436: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8005438: e00e b.n 8005458 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800543a: f7fc fd85 bl 8001f48 800543e: 4602 mov r2, r0 8005440: 693b ldr r3, [r7, #16] 8005442: 1ad3 subs r3, r2, r3 8005444: 2b02 cmp r3, #2 8005446: d907 bls.n 8005458 { return HAL_TIMEOUT; 8005448: 2303 movs r3, #3 800544a: e15c b.n 8005706 800544c: 40023800 .word 0x40023800 8005450: 42470000 .word 0x42470000 8005454: 42470e80 .word 0x42470e80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8005458: 4b8a ldr r3, [pc, #552] @ (8005684 ) 800545a: 6f5b ldr r3, [r3, #116] @ 0x74 800545c: f003 0302 and.w r3, r3, #2 8005460: 2b00 cmp r3, #0 8005462: d1ea bne.n 800543a } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8005464: 687b ldr r3, [r7, #4] 8005466: 681b ldr r3, [r3, #0] 8005468: f003 0304 and.w r3, r3, #4 800546c: 2b00 cmp r3, #0 800546e: f000 8097 beq.w 80055a0 { FlagStatus pwrclkchanged = RESET; 8005472: 2300 movs r3, #0 8005474: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8005476: 4b83 ldr r3, [pc, #524] @ (8005684 ) 8005478: 6c1b ldr r3, [r3, #64] @ 0x40 800547a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800547e: 2b00 cmp r3, #0 8005480: d10f bne.n 80054a2 { __HAL_RCC_PWR_CLK_ENABLE(); 8005482: 2300 movs r3, #0 8005484: 60bb str r3, [r7, #8] 8005486: 4b7f ldr r3, [pc, #508] @ (8005684 ) 8005488: 6c1b ldr r3, [r3, #64] @ 0x40 800548a: 4a7e ldr r2, [pc, #504] @ (8005684 ) 800548c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8005490: 6413 str r3, [r2, #64] @ 0x40 8005492: 4b7c ldr r3, [pc, #496] @ (8005684 ) 8005494: 6c1b ldr r3, [r3, #64] @ 0x40 8005496: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800549a: 60bb str r3, [r7, #8] 800549c: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800549e: 2301 movs r3, #1 80054a0: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80054a2: 4b79 ldr r3, [pc, #484] @ (8005688 ) 80054a4: 681b ldr r3, [r3, #0] 80054a6: f403 7380 and.w r3, r3, #256 @ 0x100 80054aa: 2b00 cmp r3, #0 80054ac: d118 bne.n 80054e0 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80054ae: 4b76 ldr r3, [pc, #472] @ (8005688 ) 80054b0: 681b ldr r3, [r3, #0] 80054b2: 4a75 ldr r2, [pc, #468] @ (8005688 ) 80054b4: f443 7380 orr.w r3, r3, #256 @ 0x100 80054b8: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80054ba: f7fc fd45 bl 8001f48 80054be: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80054c0: e008 b.n 80054d4 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80054c2: f7fc fd41 bl 8001f48 80054c6: 4602 mov r2, r0 80054c8: 693b ldr r3, [r7, #16] 80054ca: 1ad3 subs r3, r2, r3 80054cc: 2b02 cmp r3, #2 80054ce: d901 bls.n 80054d4 { return HAL_TIMEOUT; 80054d0: 2303 movs r3, #3 80054d2: e118 b.n 8005706 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80054d4: 4b6c ldr r3, [pc, #432] @ (8005688 ) 80054d6: 681b ldr r3, [r3, #0] 80054d8: f403 7380 and.w r3, r3, #256 @ 0x100 80054dc: 2b00 cmp r3, #0 80054de: d0f0 beq.n 80054c2 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80054e0: 687b ldr r3, [r7, #4] 80054e2: 689b ldr r3, [r3, #8] 80054e4: 2b01 cmp r3, #1 80054e6: d106 bne.n 80054f6 80054e8: 4b66 ldr r3, [pc, #408] @ (8005684 ) 80054ea: 6f1b ldr r3, [r3, #112] @ 0x70 80054ec: 4a65 ldr r2, [pc, #404] @ (8005684 ) 80054ee: f043 0301 orr.w r3, r3, #1 80054f2: 6713 str r3, [r2, #112] @ 0x70 80054f4: e01c b.n 8005530 80054f6: 687b ldr r3, [r7, #4] 80054f8: 689b ldr r3, [r3, #8] 80054fa: 2b05 cmp r3, #5 80054fc: d10c bne.n 8005518 80054fe: 4b61 ldr r3, [pc, #388] @ (8005684 ) 8005500: 6f1b ldr r3, [r3, #112] @ 0x70 8005502: 4a60 ldr r2, [pc, #384] @ (8005684 ) 8005504: f043 0304 orr.w r3, r3, #4 8005508: 6713 str r3, [r2, #112] @ 0x70 800550a: 4b5e ldr r3, [pc, #376] @ (8005684 ) 800550c: 6f1b ldr r3, [r3, #112] @ 0x70 800550e: 4a5d ldr r2, [pc, #372] @ (8005684 ) 8005510: f043 0301 orr.w r3, r3, #1 8005514: 6713 str r3, [r2, #112] @ 0x70 8005516: e00b b.n 8005530 8005518: 4b5a ldr r3, [pc, #360] @ (8005684 ) 800551a: 6f1b ldr r3, [r3, #112] @ 0x70 800551c: 4a59 ldr r2, [pc, #356] @ (8005684 ) 800551e: f023 0301 bic.w r3, r3, #1 8005522: 6713 str r3, [r2, #112] @ 0x70 8005524: 4b57 ldr r3, [pc, #348] @ (8005684 ) 8005526: 6f1b ldr r3, [r3, #112] @ 0x70 8005528: 4a56 ldr r2, [pc, #344] @ (8005684 ) 800552a: f023 0304 bic.w r3, r3, #4 800552e: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8005530: 687b ldr r3, [r7, #4] 8005532: 689b ldr r3, [r3, #8] 8005534: 2b00 cmp r3, #0 8005536: d015 beq.n 8005564 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005538: f7fc fd06 bl 8001f48 800553c: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800553e: e00a b.n 8005556 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005540: f7fc fd02 bl 8001f48 8005544: 4602 mov r2, r0 8005546: 693b ldr r3, [r7, #16] 8005548: 1ad3 subs r3, r2, r3 800554a: f241 3288 movw r2, #5000 @ 0x1388 800554e: 4293 cmp r3, r2 8005550: d901 bls.n 8005556 { return HAL_TIMEOUT; 8005552: 2303 movs r3, #3 8005554: e0d7 b.n 8005706 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005556: 4b4b ldr r3, [pc, #300] @ (8005684 ) 8005558: 6f1b ldr r3, [r3, #112] @ 0x70 800555a: f003 0302 and.w r3, r3, #2 800555e: 2b00 cmp r3, #0 8005560: d0ee beq.n 8005540 8005562: e014 b.n 800558e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005564: f7fc fcf0 bl 8001f48 8005568: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800556a: e00a b.n 8005582 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800556c: f7fc fcec bl 8001f48 8005570: 4602 mov r2, r0 8005572: 693b ldr r3, [r7, #16] 8005574: 1ad3 subs r3, r2, r3 8005576: f241 3288 movw r2, #5000 @ 0x1388 800557a: 4293 cmp r3, r2 800557c: d901 bls.n 8005582 { return HAL_TIMEOUT; 800557e: 2303 movs r3, #3 8005580: e0c1 b.n 8005706 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8005582: 4b40 ldr r3, [pc, #256] @ (8005684 ) 8005584: 6f1b ldr r3, [r3, #112] @ 0x70 8005586: f003 0302 and.w r3, r3, #2 800558a: 2b00 cmp r3, #0 800558c: d1ee bne.n 800556c } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 800558e: 7dfb ldrb r3, [r7, #23] 8005590: 2b01 cmp r3, #1 8005592: d105 bne.n 80055a0 { __HAL_RCC_PWR_CLK_DISABLE(); 8005594: 4b3b ldr r3, [pc, #236] @ (8005684 ) 8005596: 6c1b ldr r3, [r3, #64] @ 0x40 8005598: 4a3a ldr r2, [pc, #232] @ (8005684 ) 800559a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800559e: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80055a0: 687b ldr r3, [r7, #4] 80055a2: 699b ldr r3, [r3, #24] 80055a4: 2b00 cmp r3, #0 80055a6: f000 80ad beq.w 8005704 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 80055aa: 4b36 ldr r3, [pc, #216] @ (8005684 ) 80055ac: 689b ldr r3, [r3, #8] 80055ae: f003 030c and.w r3, r3, #12 80055b2: 2b08 cmp r3, #8 80055b4: d060 beq.n 8005678 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80055b6: 687b ldr r3, [r7, #4] 80055b8: 699b ldr r3, [r3, #24] 80055ba: 2b02 cmp r3, #2 80055bc: d145 bne.n 800564a assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80055be: 4b33 ldr r3, [pc, #204] @ (800568c ) 80055c0: 2200 movs r2, #0 80055c2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80055c4: f7fc fcc0 bl 8001f48 80055c8: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80055ca: e008 b.n 80055de { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80055cc: f7fc fcbc bl 8001f48 80055d0: 4602 mov r2, r0 80055d2: 693b ldr r3, [r7, #16] 80055d4: 1ad3 subs r3, r2, r3 80055d6: 2b02 cmp r3, #2 80055d8: d901 bls.n 80055de { return HAL_TIMEOUT; 80055da: 2303 movs r3, #3 80055dc: e093 b.n 8005706 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80055de: 4b29 ldr r3, [pc, #164] @ (8005684 ) 80055e0: 681b ldr r3, [r3, #0] 80055e2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80055e6: 2b00 cmp r3, #0 80055e8: d1f0 bne.n 80055cc } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 80055ea: 687b ldr r3, [r7, #4] 80055ec: 69da ldr r2, [r3, #28] 80055ee: 687b ldr r3, [r7, #4] 80055f0: 6a1b ldr r3, [r3, #32] 80055f2: 431a orrs r2, r3 80055f4: 687b ldr r3, [r7, #4] 80055f6: 6a5b ldr r3, [r3, #36] @ 0x24 80055f8: 019b lsls r3, r3, #6 80055fa: 431a orrs r2, r3 80055fc: 687b ldr r3, [r7, #4] 80055fe: 6a9b ldr r3, [r3, #40] @ 0x28 8005600: 085b lsrs r3, r3, #1 8005602: 3b01 subs r3, #1 8005604: 041b lsls r3, r3, #16 8005606: 431a orrs r2, r3 8005608: 687b ldr r3, [r7, #4] 800560a: 6adb ldr r3, [r3, #44] @ 0x2c 800560c: 061b lsls r3, r3, #24 800560e: 431a orrs r2, r3 8005610: 687b ldr r3, [r7, #4] 8005612: 6b1b ldr r3, [r3, #48] @ 0x30 8005614: 071b lsls r3, r3, #28 8005616: 491b ldr r1, [pc, #108] @ (8005684 ) 8005618: 4313 orrs r3, r2 800561a: 604b str r3, [r1, #4] (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800561c: 4b1b ldr r3, [pc, #108] @ (800568c ) 800561e: 2201 movs r2, #1 8005620: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005622: f7fc fc91 bl 8001f48 8005626: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8005628: e008 b.n 800563c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800562a: f7fc fc8d bl 8001f48 800562e: 4602 mov r2, r0 8005630: 693b ldr r3, [r7, #16] 8005632: 1ad3 subs r3, r2, r3 8005634: 2b02 cmp r3, #2 8005636: d901 bls.n 800563c { return HAL_TIMEOUT; 8005638: 2303 movs r3, #3 800563a: e064 b.n 8005706 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800563c: 4b11 ldr r3, [pc, #68] @ (8005684 ) 800563e: 681b ldr r3, [r3, #0] 8005640: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005644: 2b00 cmp r3, #0 8005646: d0f0 beq.n 800562a 8005648: e05c b.n 8005704 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800564a: 4b10 ldr r3, [pc, #64] @ (800568c ) 800564c: 2200 movs r2, #0 800564e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005650: f7fc fc7a bl 8001f48 8005654: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8005656: e008 b.n 800566a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005658: f7fc fc76 bl 8001f48 800565c: 4602 mov r2, r0 800565e: 693b ldr r3, [r7, #16] 8005660: 1ad3 subs r3, r2, r3 8005662: 2b02 cmp r3, #2 8005664: d901 bls.n 800566a { return HAL_TIMEOUT; 8005666: 2303 movs r3, #3 8005668: e04d b.n 8005706 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800566a: 4b06 ldr r3, [pc, #24] @ (8005684 ) 800566c: 681b ldr r3, [r3, #0] 800566e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005672: 2b00 cmp r3, #0 8005674: d1f0 bne.n 8005658 8005676: e045 b.n 8005704 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8005678: 687b ldr r3, [r7, #4] 800567a: 699b ldr r3, [r3, #24] 800567c: 2b01 cmp r3, #1 800567e: d107 bne.n 8005690 { return HAL_ERROR; 8005680: 2301 movs r3, #1 8005682: e040 b.n 8005706 8005684: 40023800 .word 0x40023800 8005688: 40007000 .word 0x40007000 800568c: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 8005690: 4b1f ldr r3, [pc, #124] @ (8005710 ) 8005692: 685b ldr r3, [r3, #4] 8005694: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8005696: 687b ldr r3, [r7, #4] 8005698: 699b ldr r3, [r3, #24] 800569a: 2b01 cmp r3, #1 800569c: d030 beq.n 8005700 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800569e: 68fb ldr r3, [r7, #12] 80056a0: f403 0280 and.w r2, r3, #4194304 @ 0x400000 80056a4: 687b ldr r3, [r7, #4] 80056a6: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80056a8: 429a cmp r2, r3 80056aa: d129 bne.n 8005700 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80056ac: 68fb ldr r3, [r7, #12] 80056ae: f003 023f and.w r2, r3, #63 @ 0x3f 80056b2: 687b ldr r3, [r7, #4] 80056b4: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80056b6: 429a cmp r2, r3 80056b8: d122 bne.n 8005700 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 80056ba: 68fa ldr r2, [r7, #12] 80056bc: f647 73c0 movw r3, #32704 @ 0x7fc0 80056c0: 4013 ands r3, r2 80056c2: 687a ldr r2, [r7, #4] 80056c4: 6a52 ldr r2, [r2, #36] @ 0x24 80056c6: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80056c8: 4293 cmp r3, r2 80056ca: d119 bne.n 8005700 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 80056cc: 68fb ldr r3, [r7, #12] 80056ce: f403 3240 and.w r2, r3, #196608 @ 0x30000 80056d2: 687b ldr r3, [r7, #4] 80056d4: 6a9b ldr r3, [r3, #40] @ 0x28 80056d6: 085b lsrs r3, r3, #1 80056d8: 3b01 subs r3, #1 80056da: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 80056dc: 429a cmp r2, r3 80056de: d10f bne.n 8005700 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 80056e0: 68fb ldr r3, [r7, #12] 80056e2: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 80056e6: 687b ldr r3, [r7, #4] 80056e8: 6adb ldr r3, [r3, #44] @ 0x2c 80056ea: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 80056ec: 429a cmp r2, r3 80056ee: d107 bne.n 8005700 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) 80056f0: 68fb ldr r3, [r7, #12] 80056f2: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000 80056f6: 687b ldr r3, [r7, #4] 80056f8: 6b1b ldr r3, [r3, #48] @ 0x30 80056fa: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 80056fc: 429a cmp r2, r3 80056fe: d001 beq.n 8005704 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; 8005700: 2301 movs r3, #1 8005702: e000 b.n 8005706 } } } } return HAL_OK; 8005704: 2300 movs r3, #0 } 8005706: 4618 mov r0, r3 8005708: 3718 adds r7, #24 800570a: 46bd mov sp, r7 800570c: bd80 pop {r7, pc} 800570e: bf00 nop 8005710: 40023800 .word 0x40023800 08005714 : * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { 8005714: b580 push {r7, lr} 8005716: b082 sub sp, #8 8005718: af00 add r7, sp, #0 800571a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800571c: 687b ldr r3, [r7, #4] 800571e: 2b00 cmp r3, #0 8005720: d101 bne.n 8005726 { return HAL_ERROR; 8005722: 2301 movs r3, #1 8005724: e041 b.n 80057aa assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8005726: 687b ldr r3, [r7, #4] 8005728: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800572c: b2db uxtb r3, r3 800572e: 2b00 cmp r3, #0 8005730: d106 bne.n 8005740 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005732: 687b ldr r3, [r7, #4] 8005734: 2200 movs r2, #0 8005736: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); 800573a: 6878 ldr r0, [r7, #4] 800573c: f7fb ff6a bl 8001614 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005740: 687b ldr r3, [r7, #4] 8005742: 2202 movs r2, #2 8005744: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005748: 687b ldr r3, [r7, #4] 800574a: 681a ldr r2, [r3, #0] 800574c: 687b ldr r3, [r7, #4] 800574e: 3304 adds r3, #4 8005750: 4619 mov r1, r3 8005752: 4610 mov r0, r2 8005754: f000 fba0 bl 8005e98 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005758: 687b ldr r3, [r7, #4] 800575a: 2201 movs r2, #1 800575c: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005760: 687b ldr r3, [r7, #4] 8005762: 2201 movs r2, #1 8005764: f883 203e strb.w r2, [r3, #62] @ 0x3e 8005768: 687b ldr r3, [r7, #4] 800576a: 2201 movs r2, #1 800576c: f883 203f strb.w r2, [r3, #63] @ 0x3f 8005770: 687b ldr r3, [r7, #4] 8005772: 2201 movs r2, #1 8005774: f883 2040 strb.w r2, [r3, #64] @ 0x40 8005778: 687b ldr r3, [r7, #4] 800577a: 2201 movs r2, #1 800577c: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005780: 687b ldr r3, [r7, #4] 8005782: 2201 movs r2, #1 8005784: f883 2042 strb.w r2, [r3, #66] @ 0x42 8005788: 687b ldr r3, [r7, #4] 800578a: 2201 movs r2, #1 800578c: f883 2043 strb.w r2, [r3, #67] @ 0x43 8005790: 687b ldr r3, [r7, #4] 8005792: 2201 movs r2, #1 8005794: f883 2044 strb.w r2, [r3, #68] @ 0x44 8005798: 687b ldr r3, [r7, #4] 800579a: 2201 movs r2, #1 800579c: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80057a0: 687b ldr r3, [r7, #4] 80057a2: 2201 movs r2, #1 80057a4: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80057a8: 2300 movs r3, #0 } 80057aa: 4618 mov r0, r3 80057ac: 3708 adds r7, #8 80057ae: 46bd mov sp, r7 80057b0: bd80 pop {r7, pc} 080057b2 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 80057b2: b580 push {r7, lr} 80057b4: b082 sub sp, #8 80057b6: af00 add r7, sp, #0 80057b8: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 80057ba: 687b ldr r3, [r7, #4] 80057bc: 2b00 cmp r3, #0 80057be: d101 bne.n 80057c4 { return HAL_ERROR; 80057c0: 2301 movs r3, #1 80057c2: e041 b.n 8005848 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 80057c4: 687b ldr r3, [r7, #4] 80057c6: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80057ca: b2db uxtb r3, r3 80057cc: 2b00 cmp r3, #0 80057ce: d106 bne.n 80057de { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80057d0: 687b ldr r3, [r7, #4] 80057d2: 2200 movs r2, #0 80057d4: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 80057d8: 6878 ldr r0, [r7, #4] 80057da: f000 f839 bl 8005850 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80057de: 687b ldr r3, [r7, #4] 80057e0: 2202 movs r2, #2 80057e2: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80057e6: 687b ldr r3, [r7, #4] 80057e8: 681a ldr r2, [r3, #0] 80057ea: 687b ldr r3, [r7, #4] 80057ec: 3304 adds r3, #4 80057ee: 4619 mov r1, r3 80057f0: 4610 mov r0, r2 80057f2: f000 fb51 bl 8005e98 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 80057f6: 687b ldr r3, [r7, #4] 80057f8: 2201 movs r2, #1 80057fa: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80057fe: 687b ldr r3, [r7, #4] 8005800: 2201 movs r2, #1 8005802: f883 203e strb.w r2, [r3, #62] @ 0x3e 8005806: 687b ldr r3, [r7, #4] 8005808: 2201 movs r2, #1 800580a: f883 203f strb.w r2, [r3, #63] @ 0x3f 800580e: 687b ldr r3, [r7, #4] 8005810: 2201 movs r2, #1 8005812: f883 2040 strb.w r2, [r3, #64] @ 0x40 8005816: 687b ldr r3, [r7, #4] 8005818: 2201 movs r2, #1 800581a: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800581e: 687b ldr r3, [r7, #4] 8005820: 2201 movs r2, #1 8005822: f883 2042 strb.w r2, [r3, #66] @ 0x42 8005826: 687b ldr r3, [r7, #4] 8005828: 2201 movs r2, #1 800582a: f883 2043 strb.w r2, [r3, #67] @ 0x43 800582e: 687b ldr r3, [r7, #4] 8005830: 2201 movs r2, #1 8005832: f883 2044 strb.w r2, [r3, #68] @ 0x44 8005836: 687b ldr r3, [r7, #4] 8005838: 2201 movs r2, #1 800583a: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800583e: 687b ldr r3, [r7, #4] 8005840: 2201 movs r2, #1 8005842: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8005846: 2300 movs r3, #0 } 8005848: 4618 mov r0, r3 800584a: 3708 adds r7, #8 800584c: 46bd mov sp, r7 800584e: bd80 pop {r7, pc} 08005850 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 8005850: b480 push {r7} 8005852: b083 sub sp, #12 8005854: af00 add r7, sp, #0 8005856: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 8005858: bf00 nop 800585a: 370c adds r7, #12 800585c: 46bd mov sp, r7 800585e: f85d 7b04 ldr.w r7, [sp], #4 8005862: 4770 bx lr 08005864 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8005864: b580 push {r7, lr} 8005866: b084 sub sp, #16 8005868: af00 add r7, sp, #0 800586a: 6078 str r0, [r7, #4] 800586c: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 800586e: 683b ldr r3, [r7, #0] 8005870: 2b00 cmp r3, #0 8005872: d109 bne.n 8005888 8005874: 687b ldr r3, [r7, #4] 8005876: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800587a: b2db uxtb r3, r3 800587c: 2b01 cmp r3, #1 800587e: bf14 ite ne 8005880: 2301 movne r3, #1 8005882: 2300 moveq r3, #0 8005884: b2db uxtb r3, r3 8005886: e022 b.n 80058ce 8005888: 683b ldr r3, [r7, #0] 800588a: 2b04 cmp r3, #4 800588c: d109 bne.n 80058a2 800588e: 687b ldr r3, [r7, #4] 8005890: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8005894: b2db uxtb r3, r3 8005896: 2b01 cmp r3, #1 8005898: bf14 ite ne 800589a: 2301 movne r3, #1 800589c: 2300 moveq r3, #0 800589e: b2db uxtb r3, r3 80058a0: e015 b.n 80058ce 80058a2: 683b ldr r3, [r7, #0] 80058a4: 2b08 cmp r3, #8 80058a6: d109 bne.n 80058bc 80058a8: 687b ldr r3, [r7, #4] 80058aa: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 80058ae: b2db uxtb r3, r3 80058b0: 2b01 cmp r3, #1 80058b2: bf14 ite ne 80058b4: 2301 movne r3, #1 80058b6: 2300 moveq r3, #0 80058b8: b2db uxtb r3, r3 80058ba: e008 b.n 80058ce 80058bc: 687b ldr r3, [r7, #4] 80058be: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80058c2: b2db uxtb r3, r3 80058c4: 2b01 cmp r3, #1 80058c6: bf14 ite ne 80058c8: 2301 movne r3, #1 80058ca: 2300 moveq r3, #0 80058cc: b2db uxtb r3, r3 80058ce: 2b00 cmp r3, #0 80058d0: d001 beq.n 80058d6 { return HAL_ERROR; 80058d2: 2301 movs r3, #1 80058d4: e07c b.n 80059d0 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 80058d6: 683b ldr r3, [r7, #0] 80058d8: 2b00 cmp r3, #0 80058da: d104 bne.n 80058e6 80058dc: 687b ldr r3, [r7, #4] 80058de: 2202 movs r2, #2 80058e0: f883 203e strb.w r2, [r3, #62] @ 0x3e 80058e4: e013 b.n 800590e 80058e6: 683b ldr r3, [r7, #0] 80058e8: 2b04 cmp r3, #4 80058ea: d104 bne.n 80058f6 80058ec: 687b ldr r3, [r7, #4] 80058ee: 2202 movs r2, #2 80058f0: f883 203f strb.w r2, [r3, #63] @ 0x3f 80058f4: e00b b.n 800590e 80058f6: 683b ldr r3, [r7, #0] 80058f8: 2b08 cmp r3, #8 80058fa: d104 bne.n 8005906 80058fc: 687b ldr r3, [r7, #4] 80058fe: 2202 movs r2, #2 8005900: f883 2040 strb.w r2, [r3, #64] @ 0x40 8005904: e003 b.n 800590e 8005906: 687b ldr r3, [r7, #4] 8005908: 2202 movs r2, #2 800590a: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800590e: 687b ldr r3, [r7, #4] 8005910: 681b ldr r3, [r3, #0] 8005912: 2201 movs r2, #1 8005914: 6839 ldr r1, [r7, #0] 8005916: 4618 mov r0, r3 8005918: f000 fd14 bl 8006344 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800591c: 687b ldr r3, [r7, #4] 800591e: 681b ldr r3, [r3, #0] 8005920: 4a2d ldr r2, [pc, #180] @ (80059d8 ) 8005922: 4293 cmp r3, r2 8005924: d004 beq.n 8005930 8005926: 687b ldr r3, [r7, #4] 8005928: 681b ldr r3, [r3, #0] 800592a: 4a2c ldr r2, [pc, #176] @ (80059dc ) 800592c: 4293 cmp r3, r2 800592e: d101 bne.n 8005934 8005930: 2301 movs r3, #1 8005932: e000 b.n 8005936 8005934: 2300 movs r3, #0 8005936: 2b00 cmp r3, #0 8005938: d007 beq.n 800594a { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 800593a: 687b ldr r3, [r7, #4] 800593c: 681b ldr r3, [r3, #0] 800593e: 6c5a ldr r2, [r3, #68] @ 0x44 8005940: 687b ldr r3, [r7, #4] 8005942: 681b ldr r3, [r3, #0] 8005944: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8005948: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800594a: 687b ldr r3, [r7, #4] 800594c: 681b ldr r3, [r3, #0] 800594e: 4a22 ldr r2, [pc, #136] @ (80059d8 ) 8005950: 4293 cmp r3, r2 8005952: d022 beq.n 800599a 8005954: 687b ldr r3, [r7, #4] 8005956: 681b ldr r3, [r3, #0] 8005958: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800595c: d01d beq.n 800599a 800595e: 687b ldr r3, [r7, #4] 8005960: 681b ldr r3, [r3, #0] 8005962: 4a1f ldr r2, [pc, #124] @ (80059e0 ) 8005964: 4293 cmp r3, r2 8005966: d018 beq.n 800599a 8005968: 687b ldr r3, [r7, #4] 800596a: 681b ldr r3, [r3, #0] 800596c: 4a1d ldr r2, [pc, #116] @ (80059e4 ) 800596e: 4293 cmp r3, r2 8005970: d013 beq.n 800599a 8005972: 687b ldr r3, [r7, #4] 8005974: 681b ldr r3, [r3, #0] 8005976: 4a1c ldr r2, [pc, #112] @ (80059e8 ) 8005978: 4293 cmp r3, r2 800597a: d00e beq.n 800599a 800597c: 687b ldr r3, [r7, #4] 800597e: 681b ldr r3, [r3, #0] 8005980: 4a16 ldr r2, [pc, #88] @ (80059dc ) 8005982: 4293 cmp r3, r2 8005984: d009 beq.n 800599a 8005986: 687b ldr r3, [r7, #4] 8005988: 681b ldr r3, [r3, #0] 800598a: 4a18 ldr r2, [pc, #96] @ (80059ec ) 800598c: 4293 cmp r3, r2 800598e: d004 beq.n 800599a 8005990: 687b ldr r3, [r7, #4] 8005992: 681b ldr r3, [r3, #0] 8005994: 4a16 ldr r2, [pc, #88] @ (80059f0 ) 8005996: 4293 cmp r3, r2 8005998: d111 bne.n 80059be { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800599a: 687b ldr r3, [r7, #4] 800599c: 681b ldr r3, [r3, #0] 800599e: 689b ldr r3, [r3, #8] 80059a0: f003 0307 and.w r3, r3, #7 80059a4: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80059a6: 68fb ldr r3, [r7, #12] 80059a8: 2b06 cmp r3, #6 80059aa: d010 beq.n 80059ce { __HAL_TIM_ENABLE(htim); 80059ac: 687b ldr r3, [r7, #4] 80059ae: 681b ldr r3, [r3, #0] 80059b0: 681a ldr r2, [r3, #0] 80059b2: 687b ldr r3, [r7, #4] 80059b4: 681b ldr r3, [r3, #0] 80059b6: f042 0201 orr.w r2, r2, #1 80059ba: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80059bc: e007 b.n 80059ce } } else { __HAL_TIM_ENABLE(htim); 80059be: 687b ldr r3, [r7, #4] 80059c0: 681b ldr r3, [r3, #0] 80059c2: 681a ldr r2, [r3, #0] 80059c4: 687b ldr r3, [r7, #4] 80059c6: 681b ldr r3, [r3, #0] 80059c8: f042 0201 orr.w r2, r2, #1 80059cc: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 80059ce: 2300 movs r3, #0 } 80059d0: 4618 mov r0, r3 80059d2: 3710 adds r7, #16 80059d4: 46bd mov sp, r7 80059d6: bd80 pop {r7, pc} 80059d8: 40010000 .word 0x40010000 80059dc: 40010400 .word 0x40010400 80059e0: 40000400 .word 0x40000400 80059e4: 40000800 .word 0x40000800 80059e8: 40000c00 .word 0x40000c00 80059ec: 40014000 .word 0x40014000 80059f0: 40001800 .word 0x40001800 080059f4 : * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { 80059f4: b580 push {r7, lr} 80059f6: b086 sub sp, #24 80059f8: af00 add r7, sp, #0 80059fa: 6078 str r0, [r7, #4] 80059fc: 6039 str r1, [r7, #0] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) 80059fe: 687b ldr r3, [r7, #4] 8005a00: 2b00 cmp r3, #0 8005a02: d101 bne.n 8005a08 { return HAL_ERROR; 8005a04: 2301 movs r3, #1 8005a06: e097 b.n 8005b38 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) 8005a08: 687b ldr r3, [r7, #4] 8005a0a: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8005a0e: b2db uxtb r3, r3 8005a10: 2b00 cmp r3, #0 8005a12: d106 bne.n 8005a22 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005a14: 687b ldr r3, [r7, #4] 8005a16: 2200 movs r2, #0 8005a18: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); 8005a1c: 6878 ldr r0, [r7, #4] 8005a1e: f7fb fe19 bl 8001654 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005a22: 687b ldr r3, [r7, #4] 8005a24: 2202 movs r2, #2 8005a26: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); 8005a2a: 687b ldr r3, [r7, #4] 8005a2c: 681b ldr r3, [r3, #0] 8005a2e: 689b ldr r3, [r3, #8] 8005a30: 687a ldr r2, [r7, #4] 8005a32: 6812 ldr r2, [r2, #0] 8005a34: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8005a38: f023 0307 bic.w r3, r3, #7 8005a3c: 6093 str r3, [r2, #8] /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005a3e: 687b ldr r3, [r7, #4] 8005a40: 681a ldr r2, [r3, #0] 8005a42: 687b ldr r3, [r7, #4] 8005a44: 3304 adds r3, #4 8005a46: 4619 mov r1, r3 8005a48: 4610 mov r0, r2 8005a4a: f000 fa25 bl 8005e98 /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005a4e: 687b ldr r3, [r7, #4] 8005a50: 681b ldr r3, [r3, #0] 8005a52: 689b ldr r3, [r3, #8] 8005a54: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; 8005a56: 687b ldr r3, [r7, #4] 8005a58: 681b ldr r3, [r3, #0] 8005a5a: 699b ldr r3, [r3, #24] 8005a5c: 613b str r3, [r7, #16] /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; 8005a5e: 687b ldr r3, [r7, #4] 8005a60: 681b ldr r3, [r3, #0] 8005a62: 6a1b ldr r3, [r3, #32] 8005a64: 60fb str r3, [r7, #12] /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; 8005a66: 683b ldr r3, [r7, #0] 8005a68: 681b ldr r3, [r3, #0] 8005a6a: 697a ldr r2, [r7, #20] 8005a6c: 4313 orrs r3, r2 8005a6e: 617b str r3, [r7, #20] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 8005a70: 693b ldr r3, [r7, #16] 8005a72: f423 7340 bic.w r3, r3, #768 @ 0x300 8005a76: f023 0303 bic.w r3, r3, #3 8005a7a: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); 8005a7c: 683b ldr r3, [r7, #0] 8005a7e: 689a ldr r2, [r3, #8] 8005a80: 683b ldr r3, [r7, #0] 8005a82: 699b ldr r3, [r3, #24] 8005a84: 021b lsls r3, r3, #8 8005a86: 4313 orrs r3, r2 8005a88: 693a ldr r2, [r7, #16] 8005a8a: 4313 orrs r3, r2 8005a8c: 613b str r3, [r7, #16] /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 8005a8e: 693b ldr r3, [r7, #16] 8005a90: f423 6340 bic.w r3, r3, #3072 @ 0xc00 8005a94: f023 030c bic.w r3, r3, #12 8005a98: 613b str r3, [r7, #16] tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 8005a9a: 693b ldr r3, [r7, #16] 8005a9c: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8005aa0: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8005aa4: 613b str r3, [r7, #16] tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); 8005aa6: 683b ldr r3, [r7, #0] 8005aa8: 68da ldr r2, [r3, #12] 8005aaa: 683b ldr r3, [r7, #0] 8005aac: 69db ldr r3, [r3, #28] 8005aae: 021b lsls r3, r3, #8 8005ab0: 4313 orrs r3, r2 8005ab2: 693a ldr r2, [r7, #16] 8005ab4: 4313 orrs r3, r2 8005ab6: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); 8005ab8: 683b ldr r3, [r7, #0] 8005aba: 691b ldr r3, [r3, #16] 8005abc: 011a lsls r2, r3, #4 8005abe: 683b ldr r3, [r7, #0] 8005ac0: 6a1b ldr r3, [r3, #32] 8005ac2: 031b lsls r3, r3, #12 8005ac4: 4313 orrs r3, r2 8005ac6: 693a ldr r2, [r7, #16] 8005ac8: 4313 orrs r3, r2 8005aca: 613b str r3, [r7, #16] /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 8005acc: 68fb ldr r3, [r7, #12] 8005ace: f023 0322 bic.w r3, r3, #34 @ 0x22 8005ad2: 60fb str r3, [r7, #12] tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 8005ad4: 68fb ldr r3, [r7, #12] 8005ad6: f023 0388 bic.w r3, r3, #136 @ 0x88 8005ada: 60fb str r3, [r7, #12] tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); 8005adc: 683b ldr r3, [r7, #0] 8005ade: 685a ldr r2, [r3, #4] 8005ae0: 683b ldr r3, [r7, #0] 8005ae2: 695b ldr r3, [r3, #20] 8005ae4: 011b lsls r3, r3, #4 8005ae6: 4313 orrs r3, r2 8005ae8: 68fa ldr r2, [r7, #12] 8005aea: 4313 orrs r3, r2 8005aec: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005aee: 687b ldr r3, [r7, #4] 8005af0: 681b ldr r3, [r3, #0] 8005af2: 697a ldr r2, [r7, #20] 8005af4: 609a str r2, [r3, #8] /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; 8005af6: 687b ldr r3, [r7, #4] 8005af8: 681b ldr r3, [r3, #0] 8005afa: 693a ldr r2, [r7, #16] 8005afc: 619a str r2, [r3, #24] /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; 8005afe: 687b ldr r3, [r7, #4] 8005b00: 681b ldr r3, [r3, #0] 8005b02: 68fa ldr r2, [r7, #12] 8005b04: 621a str r2, [r3, #32] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005b06: 687b ldr r3, [r7, #4] 8005b08: 2201 movs r2, #1 8005b0a: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005b0e: 687b ldr r3, [r7, #4] 8005b10: 2201 movs r2, #1 8005b12: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005b16: 687b ldr r3, [r7, #4] 8005b18: 2201 movs r2, #1 8005b1a: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005b1e: 687b ldr r3, [r7, #4] 8005b20: 2201 movs r2, #1 8005b22: f883 2042 strb.w r2, [r3, #66] @ 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005b26: 687b ldr r3, [r7, #4] 8005b28: 2201 movs r2, #1 8005b2a: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005b2e: 687b ldr r3, [r7, #4] 8005b30: 2201 movs r2, #1 8005b32: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8005b36: 2300 movs r3, #0 } 8005b38: 4618 mov r0, r3 8005b3a: 3718 adds r7, #24 8005b3c: 46bd mov sp, r7 8005b3e: bd80 pop {r7, pc} 08005b40 : * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 8005b40: b580 push {r7, lr} 8005b42: b084 sub sp, #16 8005b44: af00 add r7, sp, #0 8005b46: 6078 str r0, [r7, #4] 8005b48: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); 8005b4a: 687b ldr r3, [r7, #4] 8005b4c: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8005b50: 73fb strb r3, [r7, #15] HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); 8005b52: 687b ldr r3, [r7, #4] 8005b54: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8005b58: 73bb strb r3, [r7, #14] HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); 8005b5a: 687b ldr r3, [r7, #4] 8005b5c: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8005b60: 737b strb r3, [r7, #13] HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); 8005b62: 687b ldr r3, [r7, #4] 8005b64: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 8005b68: 733b strb r3, [r7, #12] /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) 8005b6a: 683b ldr r3, [r7, #0] 8005b6c: 2b00 cmp r3, #0 8005b6e: d110 bne.n 8005b92 { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005b70: 7bfb ldrb r3, [r7, #15] 8005b72: 2b01 cmp r3, #1 8005b74: d102 bne.n 8005b7c || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) 8005b76: 7b7b ldrb r3, [r7, #13] 8005b78: 2b01 cmp r3, #1 8005b7a: d001 beq.n 8005b80 { return HAL_ERROR; 8005b7c: 2301 movs r3, #1 8005b7e: e069 b.n 8005c54 } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005b80: 687b ldr r3, [r7, #4] 8005b82: 2202 movs r2, #2 8005b84: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005b88: 687b ldr r3, [r7, #4] 8005b8a: 2202 movs r2, #2 8005b8c: f883 2042 strb.w r2, [r3, #66] @ 0x42 8005b90: e031 b.n 8005bf6 } } else if (Channel == TIM_CHANNEL_2) 8005b92: 683b ldr r3, [r7, #0] 8005b94: 2b04 cmp r3, #4 8005b96: d110 bne.n 8005bba { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) 8005b98: 7bbb ldrb r3, [r7, #14] 8005b9a: 2b01 cmp r3, #1 8005b9c: d102 bne.n 8005ba4 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) 8005b9e: 7b3b ldrb r3, [r7, #12] 8005ba0: 2b01 cmp r3, #1 8005ba2: d001 beq.n 8005ba8 { return HAL_ERROR; 8005ba4: 2301 movs r3, #1 8005ba6: e055 b.n 8005c54 } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005ba8: 687b ldr r3, [r7, #4] 8005baa: 2202 movs r2, #2 8005bac: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005bb0: 687b ldr r3, [r7, #4] 8005bb2: 2202 movs r2, #2 8005bb4: f883 2043 strb.w r2, [r3, #67] @ 0x43 8005bb8: e01d b.n 8005bf6 } } else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005bba: 7bfb ldrb r3, [r7, #15] 8005bbc: 2b01 cmp r3, #1 8005bbe: d108 bne.n 8005bd2 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) 8005bc0: 7bbb ldrb r3, [r7, #14] 8005bc2: 2b01 cmp r3, #1 8005bc4: d105 bne.n 8005bd2 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005bc6: 7b7b ldrb r3, [r7, #13] 8005bc8: 2b01 cmp r3, #1 8005bca: d102 bne.n 8005bd2 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) 8005bcc: 7b3b ldrb r3, [r7, #12] 8005bce: 2b01 cmp r3, #1 8005bd0: d001 beq.n 8005bd6 { return HAL_ERROR; 8005bd2: 2301 movs r3, #1 8005bd4: e03e b.n 8005c54 } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005bd6: 687b ldr r3, [r7, #4] 8005bd8: 2202 movs r2, #2 8005bda: f883 203e strb.w r2, [r3, #62] @ 0x3e TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005bde: 687b ldr r3, [r7, #4] 8005be0: 2202 movs r2, #2 8005be2: f883 203f strb.w r2, [r3, #63] @ 0x3f TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005be6: 687b ldr r3, [r7, #4] 8005be8: 2202 movs r2, #2 8005bea: f883 2042 strb.w r2, [r3, #66] @ 0x42 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005bee: 687b ldr r3, [r7, #4] 8005bf0: 2202 movs r2, #2 8005bf2: f883 2043 strb.w r2, [r3, #67] @ 0x43 } } /* Enable the encoder interface channels */ switch (Channel) 8005bf6: 683b ldr r3, [r7, #0] 8005bf8: 2b00 cmp r3, #0 8005bfa: d003 beq.n 8005c04 8005bfc: 683b ldr r3, [r7, #0] 8005bfe: 2b04 cmp r3, #4 8005c00: d008 beq.n 8005c14 8005c02: e00f b.n 8005c24 { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 8005c04: 687b ldr r3, [r7, #4] 8005c06: 681b ldr r3, [r3, #0] 8005c08: 2201 movs r2, #1 8005c0a: 2100 movs r1, #0 8005c0c: 4618 mov r0, r3 8005c0e: f000 fb99 bl 8006344 break; 8005c12: e016 b.n 8005c42 } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 8005c14: 687b ldr r3, [r7, #4] 8005c16: 681b ldr r3, [r3, #0] 8005c18: 2201 movs r2, #1 8005c1a: 2104 movs r1, #4 8005c1c: 4618 mov r0, r3 8005c1e: f000 fb91 bl 8006344 break; 8005c22: e00e b.n 8005c42 } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 8005c24: 687b ldr r3, [r7, #4] 8005c26: 681b ldr r3, [r3, #0] 8005c28: 2201 movs r2, #1 8005c2a: 2100 movs r1, #0 8005c2c: 4618 mov r0, r3 8005c2e: f000 fb89 bl 8006344 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 8005c32: 687b ldr r3, [r7, #4] 8005c34: 681b ldr r3, [r3, #0] 8005c36: 2201 movs r2, #1 8005c38: 2104 movs r1, #4 8005c3a: 4618 mov r0, r3 8005c3c: f000 fb82 bl 8006344 break; 8005c40: bf00 nop } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); 8005c42: 687b ldr r3, [r7, #4] 8005c44: 681b ldr r3, [r3, #0] 8005c46: 681a ldr r2, [r3, #0] 8005c48: 687b ldr r3, [r7, #4] 8005c4a: 681b ldr r3, [r3, #0] 8005c4c: f042 0201 orr.w r2, r2, #1 8005c50: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 8005c52: 2300 movs r3, #0 } 8005c54: 4618 mov r0, r3 8005c56: 3710 adds r7, #16 8005c58: 46bd mov sp, r7 8005c5a: bd80 pop {r7, pc} 08005c5c : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8005c5c: b580 push {r7, lr} 8005c5e: b086 sub sp, #24 8005c60: af00 add r7, sp, #0 8005c62: 60f8 str r0, [r7, #12] 8005c64: 60b9 str r1, [r7, #8] 8005c66: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8005c68: 2300 movs r3, #0 8005c6a: 75fb strb r3, [r7, #23] assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); 8005c6c: 68fb ldr r3, [r7, #12] 8005c6e: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005c72: 2b01 cmp r3, #1 8005c74: d101 bne.n 8005c7a 8005c76: 2302 movs r3, #2 8005c78: e048 b.n 8005d0c 8005c7a: 68fb ldr r3, [r7, #12] 8005c7c: 2201 movs r2, #1 8005c7e: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8005c82: 687b ldr r3, [r7, #4] 8005c84: 2b0c cmp r3, #12 8005c86: d839 bhi.n 8005cfc 8005c88: a201 add r2, pc, #4 @ (adr r2, 8005c90 ) 8005c8a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005c8e: bf00 nop 8005c90: 08005cc5 .word 0x08005cc5 8005c94: 08005cfd .word 0x08005cfd 8005c98: 08005cfd .word 0x08005cfd 8005c9c: 08005cfd .word 0x08005cfd 8005ca0: 08005cd3 .word 0x08005cd3 8005ca4: 08005cfd .word 0x08005cfd 8005ca8: 08005cfd .word 0x08005cfd 8005cac: 08005cfd .word 0x08005cfd 8005cb0: 08005ce1 .word 0x08005ce1 8005cb4: 08005cfd .word 0x08005cfd 8005cb8: 08005cfd .word 0x08005cfd 8005cbc: 08005cfd .word 0x08005cfd 8005cc0: 08005cef .word 0x08005cef { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8005cc4: 68fb ldr r3, [r7, #12] 8005cc6: 681b ldr r3, [r3, #0] 8005cc8: 68b9 ldr r1, [r7, #8] 8005cca: 4618 mov r0, r3 8005ccc: f000 f98a bl 8005fe4 break; 8005cd0: e017 b.n 8005d02 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8005cd2: 68fb ldr r3, [r7, #12] 8005cd4: 681b ldr r3, [r3, #0] 8005cd6: 68b9 ldr r1, [r7, #8] 8005cd8: 4618 mov r0, r3 8005cda: f000 f9f3 bl 80060c4 break; 8005cde: e010 b.n 8005d02 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8005ce0: 68fb ldr r3, [r7, #12] 8005ce2: 681b ldr r3, [r3, #0] 8005ce4: 68b9 ldr r1, [r7, #8] 8005ce6: 4618 mov r0, r3 8005ce8: f000 fa62 bl 80061b0 break; 8005cec: e009 b.n 8005d02 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8005cee: 68fb ldr r3, [r7, #12] 8005cf0: 681b ldr r3, [r3, #0] 8005cf2: 68b9 ldr r1, [r7, #8] 8005cf4: 4618 mov r0, r3 8005cf6: f000 facf bl 8006298 break; 8005cfa: e002 b.n 8005d02 } default: status = HAL_ERROR; 8005cfc: 2301 movs r3, #1 8005cfe: 75fb strb r3, [r7, #23] break; 8005d00: bf00 nop } __HAL_UNLOCK(htim); 8005d02: 68fb ldr r3, [r7, #12] 8005d04: 2200 movs r2, #0 8005d06: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8005d0a: 7dfb ldrb r3, [r7, #23] } 8005d0c: 4618 mov r0, r3 8005d0e: 3718 adds r7, #24 8005d10: 46bd mov sp, r7 8005d12: bd80 pop {r7, pc} 08005d14 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8005d14: b580 push {r7, lr} 8005d16: b086 sub sp, #24 8005d18: af00 add r7, sp, #0 8005d1a: 60f8 str r0, [r7, #12] 8005d1c: 60b9 str r1, [r7, #8] 8005d1e: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8005d20: 2300 movs r3, #0 8005d22: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8005d24: 68fb ldr r3, [r7, #12] 8005d26: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005d2a: 2b01 cmp r3, #1 8005d2c: d101 bne.n 8005d32 8005d2e: 2302 movs r3, #2 8005d30: e0ae b.n 8005e90 8005d32: 68fb ldr r3, [r7, #12] 8005d34: 2201 movs r2, #1 8005d36: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8005d3a: 687b ldr r3, [r7, #4] 8005d3c: 2b0c cmp r3, #12 8005d3e: f200 809f bhi.w 8005e80 8005d42: a201 add r2, pc, #4 @ (adr r2, 8005d48 ) 8005d44: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005d48: 08005d7d .word 0x08005d7d 8005d4c: 08005e81 .word 0x08005e81 8005d50: 08005e81 .word 0x08005e81 8005d54: 08005e81 .word 0x08005e81 8005d58: 08005dbd .word 0x08005dbd 8005d5c: 08005e81 .word 0x08005e81 8005d60: 08005e81 .word 0x08005e81 8005d64: 08005e81 .word 0x08005e81 8005d68: 08005dff .word 0x08005dff 8005d6c: 08005e81 .word 0x08005e81 8005d70: 08005e81 .word 0x08005e81 8005d74: 08005e81 .word 0x08005e81 8005d78: 08005e3f .word 0x08005e3f { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8005d7c: 68fb ldr r3, [r7, #12] 8005d7e: 681b ldr r3, [r3, #0] 8005d80: 68b9 ldr r1, [r7, #8] 8005d82: 4618 mov r0, r3 8005d84: f000 f92e bl 8005fe4 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8005d88: 68fb ldr r3, [r7, #12] 8005d8a: 681b ldr r3, [r3, #0] 8005d8c: 699a ldr r2, [r3, #24] 8005d8e: 68fb ldr r3, [r7, #12] 8005d90: 681b ldr r3, [r3, #0] 8005d92: f042 0208 orr.w r2, r2, #8 8005d96: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8005d98: 68fb ldr r3, [r7, #12] 8005d9a: 681b ldr r3, [r3, #0] 8005d9c: 699a ldr r2, [r3, #24] 8005d9e: 68fb ldr r3, [r7, #12] 8005da0: 681b ldr r3, [r3, #0] 8005da2: f022 0204 bic.w r2, r2, #4 8005da6: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8005da8: 68fb ldr r3, [r7, #12] 8005daa: 681b ldr r3, [r3, #0] 8005dac: 6999 ldr r1, [r3, #24] 8005dae: 68bb ldr r3, [r7, #8] 8005db0: 691a ldr r2, [r3, #16] 8005db2: 68fb ldr r3, [r7, #12] 8005db4: 681b ldr r3, [r3, #0] 8005db6: 430a orrs r2, r1 8005db8: 619a str r2, [r3, #24] break; 8005dba: e064 b.n 8005e86 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8005dbc: 68fb ldr r3, [r7, #12] 8005dbe: 681b ldr r3, [r3, #0] 8005dc0: 68b9 ldr r1, [r7, #8] 8005dc2: 4618 mov r0, r3 8005dc4: f000 f97e bl 80060c4 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8005dc8: 68fb ldr r3, [r7, #12] 8005dca: 681b ldr r3, [r3, #0] 8005dcc: 699a ldr r2, [r3, #24] 8005dce: 68fb ldr r3, [r7, #12] 8005dd0: 681b ldr r3, [r3, #0] 8005dd2: f442 6200 orr.w r2, r2, #2048 @ 0x800 8005dd6: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8005dd8: 68fb ldr r3, [r7, #12] 8005dda: 681b ldr r3, [r3, #0] 8005ddc: 699a ldr r2, [r3, #24] 8005dde: 68fb ldr r3, [r7, #12] 8005de0: 681b ldr r3, [r3, #0] 8005de2: f422 6280 bic.w r2, r2, #1024 @ 0x400 8005de6: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8005de8: 68fb ldr r3, [r7, #12] 8005dea: 681b ldr r3, [r3, #0] 8005dec: 6999 ldr r1, [r3, #24] 8005dee: 68bb ldr r3, [r7, #8] 8005df0: 691b ldr r3, [r3, #16] 8005df2: 021a lsls r2, r3, #8 8005df4: 68fb ldr r3, [r7, #12] 8005df6: 681b ldr r3, [r3, #0] 8005df8: 430a orrs r2, r1 8005dfa: 619a str r2, [r3, #24] break; 8005dfc: e043 b.n 8005e86 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8005dfe: 68fb ldr r3, [r7, #12] 8005e00: 681b ldr r3, [r3, #0] 8005e02: 68b9 ldr r1, [r7, #8] 8005e04: 4618 mov r0, r3 8005e06: f000 f9d3 bl 80061b0 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 8005e0a: 68fb ldr r3, [r7, #12] 8005e0c: 681b ldr r3, [r3, #0] 8005e0e: 69da ldr r2, [r3, #28] 8005e10: 68fb ldr r3, [r7, #12] 8005e12: 681b ldr r3, [r3, #0] 8005e14: f042 0208 orr.w r2, r2, #8 8005e18: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 8005e1a: 68fb ldr r3, [r7, #12] 8005e1c: 681b ldr r3, [r3, #0] 8005e1e: 69da ldr r2, [r3, #28] 8005e20: 68fb ldr r3, [r7, #12] 8005e22: 681b ldr r3, [r3, #0] 8005e24: f022 0204 bic.w r2, r2, #4 8005e28: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 8005e2a: 68fb ldr r3, [r7, #12] 8005e2c: 681b ldr r3, [r3, #0] 8005e2e: 69d9 ldr r1, [r3, #28] 8005e30: 68bb ldr r3, [r7, #8] 8005e32: 691a ldr r2, [r3, #16] 8005e34: 68fb ldr r3, [r7, #12] 8005e36: 681b ldr r3, [r3, #0] 8005e38: 430a orrs r2, r1 8005e3a: 61da str r2, [r3, #28] break; 8005e3c: e023 b.n 8005e86 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8005e3e: 68fb ldr r3, [r7, #12] 8005e40: 681b ldr r3, [r3, #0] 8005e42: 68b9 ldr r1, [r7, #8] 8005e44: 4618 mov r0, r3 8005e46: f000 fa27 bl 8006298 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 8005e4a: 68fb ldr r3, [r7, #12] 8005e4c: 681b ldr r3, [r3, #0] 8005e4e: 69da ldr r2, [r3, #28] 8005e50: 68fb ldr r3, [r7, #12] 8005e52: 681b ldr r3, [r3, #0] 8005e54: f442 6200 orr.w r2, r2, #2048 @ 0x800 8005e58: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 8005e5a: 68fb ldr r3, [r7, #12] 8005e5c: 681b ldr r3, [r3, #0] 8005e5e: 69da ldr r2, [r3, #28] 8005e60: 68fb ldr r3, [r7, #12] 8005e62: 681b ldr r3, [r3, #0] 8005e64: f422 6280 bic.w r2, r2, #1024 @ 0x400 8005e68: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 8005e6a: 68fb ldr r3, [r7, #12] 8005e6c: 681b ldr r3, [r3, #0] 8005e6e: 69d9 ldr r1, [r3, #28] 8005e70: 68bb ldr r3, [r7, #8] 8005e72: 691b ldr r3, [r3, #16] 8005e74: 021a lsls r2, r3, #8 8005e76: 68fb ldr r3, [r7, #12] 8005e78: 681b ldr r3, [r3, #0] 8005e7a: 430a orrs r2, r1 8005e7c: 61da str r2, [r3, #28] break; 8005e7e: e002 b.n 8005e86 } default: status = HAL_ERROR; 8005e80: 2301 movs r3, #1 8005e82: 75fb strb r3, [r7, #23] break; 8005e84: bf00 nop } __HAL_UNLOCK(htim); 8005e86: 68fb ldr r3, [r7, #12] 8005e88: 2200 movs r2, #0 8005e8a: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8005e8e: 7dfb ldrb r3, [r7, #23] } 8005e90: 4618 mov r0, r3 8005e92: 3718 adds r7, #24 8005e94: 46bd mov sp, r7 8005e96: bd80 pop {r7, pc} 08005e98 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8005e98: b480 push {r7} 8005e9a: b085 sub sp, #20 8005e9c: af00 add r7, sp, #0 8005e9e: 6078 str r0, [r7, #4] 8005ea0: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8005ea2: 687b ldr r3, [r7, #4] 8005ea4: 681b ldr r3, [r3, #0] 8005ea6: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8005ea8: 687b ldr r3, [r7, #4] 8005eaa: 4a43 ldr r2, [pc, #268] @ (8005fb8 ) 8005eac: 4293 cmp r3, r2 8005eae: d013 beq.n 8005ed8 8005eb0: 687b ldr r3, [r7, #4] 8005eb2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005eb6: d00f beq.n 8005ed8 8005eb8: 687b ldr r3, [r7, #4] 8005eba: 4a40 ldr r2, [pc, #256] @ (8005fbc ) 8005ebc: 4293 cmp r3, r2 8005ebe: d00b beq.n 8005ed8 8005ec0: 687b ldr r3, [r7, #4] 8005ec2: 4a3f ldr r2, [pc, #252] @ (8005fc0 ) 8005ec4: 4293 cmp r3, r2 8005ec6: d007 beq.n 8005ed8 8005ec8: 687b ldr r3, [r7, #4] 8005eca: 4a3e ldr r2, [pc, #248] @ (8005fc4 ) 8005ecc: 4293 cmp r3, r2 8005ece: d003 beq.n 8005ed8 8005ed0: 687b ldr r3, [r7, #4] 8005ed2: 4a3d ldr r2, [pc, #244] @ (8005fc8 ) 8005ed4: 4293 cmp r3, r2 8005ed6: d108 bne.n 8005eea { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8005ed8: 68fb ldr r3, [r7, #12] 8005eda: f023 0370 bic.w r3, r3, #112 @ 0x70 8005ede: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8005ee0: 683b ldr r3, [r7, #0] 8005ee2: 685b ldr r3, [r3, #4] 8005ee4: 68fa ldr r2, [r7, #12] 8005ee6: 4313 orrs r3, r2 8005ee8: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8005eea: 687b ldr r3, [r7, #4] 8005eec: 4a32 ldr r2, [pc, #200] @ (8005fb8 ) 8005eee: 4293 cmp r3, r2 8005ef0: d02b beq.n 8005f4a 8005ef2: 687b ldr r3, [r7, #4] 8005ef4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005ef8: d027 beq.n 8005f4a 8005efa: 687b ldr r3, [r7, #4] 8005efc: 4a2f ldr r2, [pc, #188] @ (8005fbc ) 8005efe: 4293 cmp r3, r2 8005f00: d023 beq.n 8005f4a 8005f02: 687b ldr r3, [r7, #4] 8005f04: 4a2e ldr r2, [pc, #184] @ (8005fc0 ) 8005f06: 4293 cmp r3, r2 8005f08: d01f beq.n 8005f4a 8005f0a: 687b ldr r3, [r7, #4] 8005f0c: 4a2d ldr r2, [pc, #180] @ (8005fc4 ) 8005f0e: 4293 cmp r3, r2 8005f10: d01b beq.n 8005f4a 8005f12: 687b ldr r3, [r7, #4] 8005f14: 4a2c ldr r2, [pc, #176] @ (8005fc8 ) 8005f16: 4293 cmp r3, r2 8005f18: d017 beq.n 8005f4a 8005f1a: 687b ldr r3, [r7, #4] 8005f1c: 4a2b ldr r2, [pc, #172] @ (8005fcc ) 8005f1e: 4293 cmp r3, r2 8005f20: d013 beq.n 8005f4a 8005f22: 687b ldr r3, [r7, #4] 8005f24: 4a2a ldr r2, [pc, #168] @ (8005fd0 ) 8005f26: 4293 cmp r3, r2 8005f28: d00f beq.n 8005f4a 8005f2a: 687b ldr r3, [r7, #4] 8005f2c: 4a29 ldr r2, [pc, #164] @ (8005fd4 ) 8005f2e: 4293 cmp r3, r2 8005f30: d00b beq.n 8005f4a 8005f32: 687b ldr r3, [r7, #4] 8005f34: 4a28 ldr r2, [pc, #160] @ (8005fd8 ) 8005f36: 4293 cmp r3, r2 8005f38: d007 beq.n 8005f4a 8005f3a: 687b ldr r3, [r7, #4] 8005f3c: 4a27 ldr r2, [pc, #156] @ (8005fdc ) 8005f3e: 4293 cmp r3, r2 8005f40: d003 beq.n 8005f4a 8005f42: 687b ldr r3, [r7, #4] 8005f44: 4a26 ldr r2, [pc, #152] @ (8005fe0 ) 8005f46: 4293 cmp r3, r2 8005f48: d108 bne.n 8005f5c { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8005f4a: 68fb ldr r3, [r7, #12] 8005f4c: f423 7340 bic.w r3, r3, #768 @ 0x300 8005f50: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8005f52: 683b ldr r3, [r7, #0] 8005f54: 68db ldr r3, [r3, #12] 8005f56: 68fa ldr r2, [r7, #12] 8005f58: 4313 orrs r3, r2 8005f5a: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8005f5c: 68fb ldr r3, [r7, #12] 8005f5e: f023 0280 bic.w r2, r3, #128 @ 0x80 8005f62: 683b ldr r3, [r7, #0] 8005f64: 695b ldr r3, [r3, #20] 8005f66: 4313 orrs r3, r2 8005f68: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8005f6a: 683b ldr r3, [r7, #0] 8005f6c: 689a ldr r2, [r3, #8] 8005f6e: 687b ldr r3, [r7, #4] 8005f70: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8005f72: 683b ldr r3, [r7, #0] 8005f74: 681a ldr r2, [r3, #0] 8005f76: 687b ldr r3, [r7, #4] 8005f78: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8005f7a: 687b ldr r3, [r7, #4] 8005f7c: 4a0e ldr r2, [pc, #56] @ (8005fb8 ) 8005f7e: 4293 cmp r3, r2 8005f80: d003 beq.n 8005f8a 8005f82: 687b ldr r3, [r7, #4] 8005f84: 4a10 ldr r2, [pc, #64] @ (8005fc8 ) 8005f86: 4293 cmp r3, r2 8005f88: d103 bne.n 8005f92 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8005f8a: 683b ldr r3, [r7, #0] 8005f8c: 691a ldr r2, [r3, #16] 8005f8e: 687b ldr r3, [r7, #4] 8005f90: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 8005f92: 687b ldr r3, [r7, #4] 8005f94: 681b ldr r3, [r3, #0] 8005f96: f043 0204 orr.w r2, r3, #4 8005f9a: 687b ldr r3, [r7, #4] 8005f9c: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8005f9e: 687b ldr r3, [r7, #4] 8005fa0: 2201 movs r2, #1 8005fa2: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 8005fa4: 687b ldr r3, [r7, #4] 8005fa6: 68fa ldr r2, [r7, #12] 8005fa8: 601a str r2, [r3, #0] } 8005faa: bf00 nop 8005fac: 3714 adds r7, #20 8005fae: 46bd mov sp, r7 8005fb0: f85d 7b04 ldr.w r7, [sp], #4 8005fb4: 4770 bx lr 8005fb6: bf00 nop 8005fb8: 40010000 .word 0x40010000 8005fbc: 40000400 .word 0x40000400 8005fc0: 40000800 .word 0x40000800 8005fc4: 40000c00 .word 0x40000c00 8005fc8: 40010400 .word 0x40010400 8005fcc: 40014000 .word 0x40014000 8005fd0: 40014400 .word 0x40014400 8005fd4: 40014800 .word 0x40014800 8005fd8: 40001800 .word 0x40001800 8005fdc: 40001c00 .word 0x40001c00 8005fe0: 40002000 .word 0x40002000 08005fe4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005fe4: b480 push {r7} 8005fe6: b087 sub sp, #28 8005fe8: af00 add r7, sp, #0 8005fea: 6078 str r0, [r7, #4] 8005fec: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8005fee: 687b ldr r3, [r7, #4] 8005ff0: 6a1b ldr r3, [r3, #32] 8005ff2: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8005ff4: 687b ldr r3, [r7, #4] 8005ff6: 6a1b ldr r3, [r3, #32] 8005ff8: f023 0201 bic.w r2, r3, #1 8005ffc: 687b ldr r3, [r7, #4] 8005ffe: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8006000: 687b ldr r3, [r7, #4] 8006002: 685b ldr r3, [r3, #4] 8006004: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8006006: 687b ldr r3, [r7, #4] 8006008: 699b ldr r3, [r3, #24] 800600a: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 800600c: 68fb ldr r3, [r7, #12] 800600e: f023 0370 bic.w r3, r3, #112 @ 0x70 8006012: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8006014: 68fb ldr r3, [r7, #12] 8006016: f023 0303 bic.w r3, r3, #3 800601a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800601c: 683b ldr r3, [r7, #0] 800601e: 681b ldr r3, [r3, #0] 8006020: 68fa ldr r2, [r7, #12] 8006022: 4313 orrs r3, r2 8006024: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8006026: 697b ldr r3, [r7, #20] 8006028: f023 0302 bic.w r3, r3, #2 800602c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800602e: 683b ldr r3, [r7, #0] 8006030: 689b ldr r3, [r3, #8] 8006032: 697a ldr r2, [r7, #20] 8006034: 4313 orrs r3, r2 8006036: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8006038: 687b ldr r3, [r7, #4] 800603a: 4a20 ldr r2, [pc, #128] @ (80060bc ) 800603c: 4293 cmp r3, r2 800603e: d003 beq.n 8006048 8006040: 687b ldr r3, [r7, #4] 8006042: 4a1f ldr r2, [pc, #124] @ (80060c0 ) 8006044: 4293 cmp r3, r2 8006046: d10c bne.n 8006062 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8006048: 697b ldr r3, [r7, #20] 800604a: f023 0308 bic.w r3, r3, #8 800604e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8006050: 683b ldr r3, [r7, #0] 8006052: 68db ldr r3, [r3, #12] 8006054: 697a ldr r2, [r7, #20] 8006056: 4313 orrs r3, r2 8006058: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 800605a: 697b ldr r3, [r7, #20] 800605c: f023 0304 bic.w r3, r3, #4 8006060: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006062: 687b ldr r3, [r7, #4] 8006064: 4a15 ldr r2, [pc, #84] @ (80060bc ) 8006066: 4293 cmp r3, r2 8006068: d003 beq.n 8006072 800606a: 687b ldr r3, [r7, #4] 800606c: 4a14 ldr r2, [pc, #80] @ (80060c0 ) 800606e: 4293 cmp r3, r2 8006070: d111 bne.n 8006096 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8006072: 693b ldr r3, [r7, #16] 8006074: f423 7380 bic.w r3, r3, #256 @ 0x100 8006078: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 800607a: 693b ldr r3, [r7, #16] 800607c: f423 7300 bic.w r3, r3, #512 @ 0x200 8006080: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8006082: 683b ldr r3, [r7, #0] 8006084: 695b ldr r3, [r3, #20] 8006086: 693a ldr r2, [r7, #16] 8006088: 4313 orrs r3, r2 800608a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800608c: 683b ldr r3, [r7, #0] 800608e: 699b ldr r3, [r3, #24] 8006090: 693a ldr r2, [r7, #16] 8006092: 4313 orrs r3, r2 8006094: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8006096: 687b ldr r3, [r7, #4] 8006098: 693a ldr r2, [r7, #16] 800609a: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800609c: 687b ldr r3, [r7, #4] 800609e: 68fa ldr r2, [r7, #12] 80060a0: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 80060a2: 683b ldr r3, [r7, #0] 80060a4: 685a ldr r2, [r3, #4] 80060a6: 687b ldr r3, [r7, #4] 80060a8: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80060aa: 687b ldr r3, [r7, #4] 80060ac: 697a ldr r2, [r7, #20] 80060ae: 621a str r2, [r3, #32] } 80060b0: bf00 nop 80060b2: 371c adds r7, #28 80060b4: 46bd mov sp, r7 80060b6: f85d 7b04 ldr.w r7, [sp], #4 80060ba: 4770 bx lr 80060bc: 40010000 .word 0x40010000 80060c0: 40010400 .word 0x40010400 080060c4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80060c4: b480 push {r7} 80060c6: b087 sub sp, #28 80060c8: af00 add r7, sp, #0 80060ca: 6078 str r0, [r7, #4] 80060cc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80060ce: 687b ldr r3, [r7, #4] 80060d0: 6a1b ldr r3, [r3, #32] 80060d2: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 80060d4: 687b ldr r3, [r7, #4] 80060d6: 6a1b ldr r3, [r3, #32] 80060d8: f023 0210 bic.w r2, r3, #16 80060dc: 687b ldr r3, [r7, #4] 80060de: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80060e0: 687b ldr r3, [r7, #4] 80060e2: 685b ldr r3, [r3, #4] 80060e4: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80060e6: 687b ldr r3, [r7, #4] 80060e8: 699b ldr r3, [r3, #24] 80060ea: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80060ec: 68fb ldr r3, [r7, #12] 80060ee: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80060f2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80060f4: 68fb ldr r3, [r7, #12] 80060f6: f423 7340 bic.w r3, r3, #768 @ 0x300 80060fa: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80060fc: 683b ldr r3, [r7, #0] 80060fe: 681b ldr r3, [r3, #0] 8006100: 021b lsls r3, r3, #8 8006102: 68fa ldr r2, [r7, #12] 8006104: 4313 orrs r3, r2 8006106: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8006108: 697b ldr r3, [r7, #20] 800610a: f023 0320 bic.w r3, r3, #32 800610e: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8006110: 683b ldr r3, [r7, #0] 8006112: 689b ldr r3, [r3, #8] 8006114: 011b lsls r3, r3, #4 8006116: 697a ldr r2, [r7, #20] 8006118: 4313 orrs r3, r2 800611a: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 800611c: 687b ldr r3, [r7, #4] 800611e: 4a22 ldr r2, [pc, #136] @ (80061a8 ) 8006120: 4293 cmp r3, r2 8006122: d003 beq.n 800612c 8006124: 687b ldr r3, [r7, #4] 8006126: 4a21 ldr r2, [pc, #132] @ (80061ac ) 8006128: 4293 cmp r3, r2 800612a: d10d bne.n 8006148 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 800612c: 697b ldr r3, [r7, #20] 800612e: f023 0380 bic.w r3, r3, #128 @ 0x80 8006132: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8006134: 683b ldr r3, [r7, #0] 8006136: 68db ldr r3, [r3, #12] 8006138: 011b lsls r3, r3, #4 800613a: 697a ldr r2, [r7, #20] 800613c: 4313 orrs r3, r2 800613e: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8006140: 697b ldr r3, [r7, #20] 8006142: f023 0340 bic.w r3, r3, #64 @ 0x40 8006146: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006148: 687b ldr r3, [r7, #4] 800614a: 4a17 ldr r2, [pc, #92] @ (80061a8 ) 800614c: 4293 cmp r3, r2 800614e: d003 beq.n 8006158 8006150: 687b ldr r3, [r7, #4] 8006152: 4a16 ldr r2, [pc, #88] @ (80061ac ) 8006154: 4293 cmp r3, r2 8006156: d113 bne.n 8006180 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8006158: 693b ldr r3, [r7, #16] 800615a: f423 6380 bic.w r3, r3, #1024 @ 0x400 800615e: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8006160: 693b ldr r3, [r7, #16] 8006162: f423 6300 bic.w r3, r3, #2048 @ 0x800 8006166: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8006168: 683b ldr r3, [r7, #0] 800616a: 695b ldr r3, [r3, #20] 800616c: 009b lsls r3, r3, #2 800616e: 693a ldr r2, [r7, #16] 8006170: 4313 orrs r3, r2 8006172: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8006174: 683b ldr r3, [r7, #0] 8006176: 699b ldr r3, [r3, #24] 8006178: 009b lsls r3, r3, #2 800617a: 693a ldr r2, [r7, #16] 800617c: 4313 orrs r3, r2 800617e: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8006180: 687b ldr r3, [r7, #4] 8006182: 693a ldr r2, [r7, #16] 8006184: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8006186: 687b ldr r3, [r7, #4] 8006188: 68fa ldr r2, [r7, #12] 800618a: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 800618c: 683b ldr r3, [r7, #0] 800618e: 685a ldr r2, [r3, #4] 8006190: 687b ldr r3, [r7, #4] 8006192: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8006194: 687b ldr r3, [r7, #4] 8006196: 697a ldr r2, [r7, #20] 8006198: 621a str r2, [r3, #32] } 800619a: bf00 nop 800619c: 371c adds r7, #28 800619e: 46bd mov sp, r7 80061a0: f85d 7b04 ldr.w r7, [sp], #4 80061a4: 4770 bx lr 80061a6: bf00 nop 80061a8: 40010000 .word 0x40010000 80061ac: 40010400 .word 0x40010400 080061b0 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80061b0: b480 push {r7} 80061b2: b087 sub sp, #28 80061b4: af00 add r7, sp, #0 80061b6: 6078 str r0, [r7, #4] 80061b8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80061ba: 687b ldr r3, [r7, #4] 80061bc: 6a1b ldr r3, [r3, #32] 80061be: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 80061c0: 687b ldr r3, [r7, #4] 80061c2: 6a1b ldr r3, [r3, #32] 80061c4: f423 7280 bic.w r2, r3, #256 @ 0x100 80061c8: 687b ldr r3, [r7, #4] 80061ca: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80061cc: 687b ldr r3, [r7, #4] 80061ce: 685b ldr r3, [r3, #4] 80061d0: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80061d2: 687b ldr r3, [r7, #4] 80061d4: 69db ldr r3, [r3, #28] 80061d6: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 80061d8: 68fb ldr r3, [r7, #12] 80061da: f023 0370 bic.w r3, r3, #112 @ 0x70 80061de: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 80061e0: 68fb ldr r3, [r7, #12] 80061e2: f023 0303 bic.w r3, r3, #3 80061e6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80061e8: 683b ldr r3, [r7, #0] 80061ea: 681b ldr r3, [r3, #0] 80061ec: 68fa ldr r2, [r7, #12] 80061ee: 4313 orrs r3, r2 80061f0: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 80061f2: 697b ldr r3, [r7, #20] 80061f4: f423 7300 bic.w r3, r3, #512 @ 0x200 80061f8: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 80061fa: 683b ldr r3, [r7, #0] 80061fc: 689b ldr r3, [r3, #8] 80061fe: 021b lsls r3, r3, #8 8006200: 697a ldr r2, [r7, #20] 8006202: 4313 orrs r3, r2 8006204: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8006206: 687b ldr r3, [r7, #4] 8006208: 4a21 ldr r2, [pc, #132] @ (8006290 ) 800620a: 4293 cmp r3, r2 800620c: d003 beq.n 8006216 800620e: 687b ldr r3, [r7, #4] 8006210: 4a20 ldr r2, [pc, #128] @ (8006294 ) 8006212: 4293 cmp r3, r2 8006214: d10d bne.n 8006232 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8006216: 697b ldr r3, [r7, #20] 8006218: f423 6300 bic.w r3, r3, #2048 @ 0x800 800621c: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 800621e: 683b ldr r3, [r7, #0] 8006220: 68db ldr r3, [r3, #12] 8006222: 021b lsls r3, r3, #8 8006224: 697a ldr r2, [r7, #20] 8006226: 4313 orrs r3, r2 8006228: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 800622a: 697b ldr r3, [r7, #20] 800622c: f423 6380 bic.w r3, r3, #1024 @ 0x400 8006230: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006232: 687b ldr r3, [r7, #4] 8006234: 4a16 ldr r2, [pc, #88] @ (8006290 ) 8006236: 4293 cmp r3, r2 8006238: d003 beq.n 8006242 800623a: 687b ldr r3, [r7, #4] 800623c: 4a15 ldr r2, [pc, #84] @ (8006294 ) 800623e: 4293 cmp r3, r2 8006240: d113 bne.n 800626a /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8006242: 693b ldr r3, [r7, #16] 8006244: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8006248: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 800624a: 693b ldr r3, [r7, #16] 800624c: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8006250: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8006252: 683b ldr r3, [r7, #0] 8006254: 695b ldr r3, [r3, #20] 8006256: 011b lsls r3, r3, #4 8006258: 693a ldr r2, [r7, #16] 800625a: 4313 orrs r3, r2 800625c: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 800625e: 683b ldr r3, [r7, #0] 8006260: 699b ldr r3, [r3, #24] 8006262: 011b lsls r3, r3, #4 8006264: 693a ldr r2, [r7, #16] 8006266: 4313 orrs r3, r2 8006268: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800626a: 687b ldr r3, [r7, #4] 800626c: 693a ldr r2, [r7, #16] 800626e: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8006270: 687b ldr r3, [r7, #4] 8006272: 68fa ldr r2, [r7, #12] 8006274: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8006276: 683b ldr r3, [r7, #0] 8006278: 685a ldr r2, [r3, #4] 800627a: 687b ldr r3, [r7, #4] 800627c: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800627e: 687b ldr r3, [r7, #4] 8006280: 697a ldr r2, [r7, #20] 8006282: 621a str r2, [r3, #32] } 8006284: bf00 nop 8006286: 371c adds r7, #28 8006288: 46bd mov sp, r7 800628a: f85d 7b04 ldr.w r7, [sp], #4 800628e: 4770 bx lr 8006290: 40010000 .word 0x40010000 8006294: 40010400 .word 0x40010400 08006298 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8006298: b480 push {r7} 800629a: b087 sub sp, #28 800629c: af00 add r7, sp, #0 800629e: 6078 str r0, [r7, #4] 80062a0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80062a2: 687b ldr r3, [r7, #4] 80062a4: 6a1b ldr r3, [r3, #32] 80062a6: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 80062a8: 687b ldr r3, [r7, #4] 80062aa: 6a1b ldr r3, [r3, #32] 80062ac: f423 5280 bic.w r2, r3, #4096 @ 0x1000 80062b0: 687b ldr r3, [r7, #4] 80062b2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80062b4: 687b ldr r3, [r7, #4] 80062b6: 685b ldr r3, [r3, #4] 80062b8: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80062ba: 687b ldr r3, [r7, #4] 80062bc: 69db ldr r3, [r3, #28] 80062be: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 80062c0: 68fb ldr r3, [r7, #12] 80062c2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80062c6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 80062c8: 68fb ldr r3, [r7, #12] 80062ca: f423 7340 bic.w r3, r3, #768 @ 0x300 80062ce: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80062d0: 683b ldr r3, [r7, #0] 80062d2: 681b ldr r3, [r3, #0] 80062d4: 021b lsls r3, r3, #8 80062d6: 68fa ldr r2, [r7, #12] 80062d8: 4313 orrs r3, r2 80062da: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 80062dc: 693b ldr r3, [r7, #16] 80062de: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80062e2: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 80062e4: 683b ldr r3, [r7, #0] 80062e6: 689b ldr r3, [r3, #8] 80062e8: 031b lsls r3, r3, #12 80062ea: 693a ldr r2, [r7, #16] 80062ec: 4313 orrs r3, r2 80062ee: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 80062f0: 687b ldr r3, [r7, #4] 80062f2: 4a12 ldr r2, [pc, #72] @ (800633c ) 80062f4: 4293 cmp r3, r2 80062f6: d003 beq.n 8006300 80062f8: 687b ldr r3, [r7, #4] 80062fa: 4a11 ldr r2, [pc, #68] @ (8006340 ) 80062fc: 4293 cmp r3, r2 80062fe: d109 bne.n 8006314 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8006300: 697b ldr r3, [r7, #20] 8006302: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8006306: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8006308: 683b ldr r3, [r7, #0] 800630a: 695b ldr r3, [r3, #20] 800630c: 019b lsls r3, r3, #6 800630e: 697a ldr r2, [r7, #20] 8006310: 4313 orrs r3, r2 8006312: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8006314: 687b ldr r3, [r7, #4] 8006316: 697a ldr r2, [r7, #20] 8006318: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800631a: 687b ldr r3, [r7, #4] 800631c: 68fa ldr r2, [r7, #12] 800631e: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8006320: 683b ldr r3, [r7, #0] 8006322: 685a ldr r2, [r3, #4] 8006324: 687b ldr r3, [r7, #4] 8006326: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8006328: 687b ldr r3, [r7, #4] 800632a: 693a ldr r2, [r7, #16] 800632c: 621a str r2, [r3, #32] } 800632e: bf00 nop 8006330: 371c adds r7, #28 8006332: 46bd mov sp, r7 8006334: f85d 7b04 ldr.w r7, [sp], #4 8006338: 4770 bx lr 800633a: bf00 nop 800633c: 40010000 .word 0x40010000 8006340: 40010400 .word 0x40010400 08006344 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8006344: b480 push {r7} 8006346: b087 sub sp, #28 8006348: af00 add r7, sp, #0 800634a: 60f8 str r0, [r7, #12] 800634c: 60b9 str r1, [r7, #8] 800634e: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8006350: 68bb ldr r3, [r7, #8] 8006352: f003 031f and.w r3, r3, #31 8006356: 2201 movs r2, #1 8006358: fa02 f303 lsl.w r3, r2, r3 800635c: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 800635e: 68fb ldr r3, [r7, #12] 8006360: 6a1a ldr r2, [r3, #32] 8006362: 697b ldr r3, [r7, #20] 8006364: 43db mvns r3, r3 8006366: 401a ands r2, r3 8006368: 68fb ldr r3, [r7, #12] 800636a: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 800636c: 68fb ldr r3, [r7, #12] 800636e: 6a1a ldr r2, [r3, #32] 8006370: 68bb ldr r3, [r7, #8] 8006372: f003 031f and.w r3, r3, #31 8006376: 6879 ldr r1, [r7, #4] 8006378: fa01 f303 lsl.w r3, r1, r3 800637c: 431a orrs r2, r3 800637e: 68fb ldr r3, [r7, #12] 8006380: 621a str r2, [r3, #32] } 8006382: bf00 nop 8006384: 371c adds r7, #28 8006386: 46bd mov sp, r7 8006388: f85d 7b04 ldr.w r7, [sp], #4 800638c: 4770 bx lr ... 08006390 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8006390: b480 push {r7} 8006392: b085 sub sp, #20 8006394: af00 add r7, sp, #0 8006396: 6078 str r0, [r7, #4] 8006398: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800639a: 687b ldr r3, [r7, #4] 800639c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80063a0: 2b01 cmp r3, #1 80063a2: d101 bne.n 80063a8 80063a4: 2302 movs r3, #2 80063a6: e05a b.n 800645e 80063a8: 687b ldr r3, [r7, #4] 80063aa: 2201 movs r2, #1 80063ac: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 80063b0: 687b ldr r3, [r7, #4] 80063b2: 2202 movs r2, #2 80063b4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 80063b8: 687b ldr r3, [r7, #4] 80063ba: 681b ldr r3, [r3, #0] 80063bc: 685b ldr r3, [r3, #4] 80063be: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80063c0: 687b ldr r3, [r7, #4] 80063c2: 681b ldr r3, [r3, #0] 80063c4: 689b ldr r3, [r3, #8] 80063c6: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80063c8: 68fb ldr r3, [r7, #12] 80063ca: f023 0370 bic.w r3, r3, #112 @ 0x70 80063ce: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80063d0: 683b ldr r3, [r7, #0] 80063d2: 681b ldr r3, [r3, #0] 80063d4: 68fa ldr r2, [r7, #12] 80063d6: 4313 orrs r3, r2 80063d8: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80063da: 687b ldr r3, [r7, #4] 80063dc: 681b ldr r3, [r3, #0] 80063de: 68fa ldr r2, [r7, #12] 80063e0: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80063e2: 687b ldr r3, [r7, #4] 80063e4: 681b ldr r3, [r3, #0] 80063e6: 4a21 ldr r2, [pc, #132] @ (800646c ) 80063e8: 4293 cmp r3, r2 80063ea: d022 beq.n 8006432 80063ec: 687b ldr r3, [r7, #4] 80063ee: 681b ldr r3, [r3, #0] 80063f0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80063f4: d01d beq.n 8006432 80063f6: 687b ldr r3, [r7, #4] 80063f8: 681b ldr r3, [r3, #0] 80063fa: 4a1d ldr r2, [pc, #116] @ (8006470 ) 80063fc: 4293 cmp r3, r2 80063fe: d018 beq.n 8006432 8006400: 687b ldr r3, [r7, #4] 8006402: 681b ldr r3, [r3, #0] 8006404: 4a1b ldr r2, [pc, #108] @ (8006474 ) 8006406: 4293 cmp r3, r2 8006408: d013 beq.n 8006432 800640a: 687b ldr r3, [r7, #4] 800640c: 681b ldr r3, [r3, #0] 800640e: 4a1a ldr r2, [pc, #104] @ (8006478 ) 8006410: 4293 cmp r3, r2 8006412: d00e beq.n 8006432 8006414: 687b ldr r3, [r7, #4] 8006416: 681b ldr r3, [r3, #0] 8006418: 4a18 ldr r2, [pc, #96] @ (800647c ) 800641a: 4293 cmp r3, r2 800641c: d009 beq.n 8006432 800641e: 687b ldr r3, [r7, #4] 8006420: 681b ldr r3, [r3, #0] 8006422: 4a17 ldr r2, [pc, #92] @ (8006480 ) 8006424: 4293 cmp r3, r2 8006426: d004 beq.n 8006432 8006428: 687b ldr r3, [r7, #4] 800642a: 681b ldr r3, [r3, #0] 800642c: 4a15 ldr r2, [pc, #84] @ (8006484 ) 800642e: 4293 cmp r3, r2 8006430: d10c bne.n 800644c { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8006432: 68bb ldr r3, [r7, #8] 8006434: f023 0380 bic.w r3, r3, #128 @ 0x80 8006438: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 800643a: 683b ldr r3, [r7, #0] 800643c: 685b ldr r3, [r3, #4] 800643e: 68ba ldr r2, [r7, #8] 8006440: 4313 orrs r3, r2 8006442: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8006444: 687b ldr r3, [r7, #4] 8006446: 681b ldr r3, [r3, #0] 8006448: 68ba ldr r2, [r7, #8] 800644a: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 800644c: 687b ldr r3, [r7, #4] 800644e: 2201 movs r2, #1 8006450: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8006454: 687b ldr r3, [r7, #4] 8006456: 2200 movs r2, #0 8006458: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 800645c: 2300 movs r3, #0 } 800645e: 4618 mov r0, r3 8006460: 3714 adds r7, #20 8006462: 46bd mov sp, r7 8006464: f85d 7b04 ldr.w r7, [sp], #4 8006468: 4770 bx lr 800646a: bf00 nop 800646c: 40010000 .word 0x40010000 8006470: 40000400 .word 0x40000400 8006474: 40000800 .word 0x40000800 8006478: 40000c00 .word 0x40000c00 800647c: 40010400 .word 0x40010400 8006480: 40014000 .word 0x40014000 8006484: 40001800 .word 0x40001800 08006488 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8006488: b580 push {r7, lr} 800648a: b082 sub sp, #8 800648c: af00 add r7, sp, #0 800648e: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8006490: 687b ldr r3, [r7, #4] 8006492: 2b00 cmp r3, #0 8006494: d101 bne.n 800649a { return HAL_ERROR; 8006496: 2301 movs r3, #1 8006498: e042 b.n 8006520 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 800649a: 687b ldr r3, [r7, #4] 800649c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80064a0: b2db uxtb r3, r3 80064a2: 2b00 cmp r3, #0 80064a4: d106 bne.n 80064b4 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80064a6: 687b ldr r3, [r7, #4] 80064a8: 2200 movs r2, #0 80064aa: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 80064ae: 6878 ldr r0, [r7, #4] 80064b0: f7fb f9f8 bl 80018a4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 80064b4: 687b ldr r3, [r7, #4] 80064b6: 2224 movs r2, #36 @ 0x24 80064b8: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 80064bc: 687b ldr r3, [r7, #4] 80064be: 681b ldr r3, [r3, #0] 80064c0: 68da ldr r2, [r3, #12] 80064c2: 687b ldr r3, [r7, #4] 80064c4: 681b ldr r3, [r3, #0] 80064c6: f422 5200 bic.w r2, r2, #8192 @ 0x2000 80064ca: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 80064cc: 6878 ldr r0, [r7, #4] 80064ce: f000 ff63 bl 8007398 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80064d2: 687b ldr r3, [r7, #4] 80064d4: 681b ldr r3, [r3, #0] 80064d6: 691a ldr r2, [r3, #16] 80064d8: 687b ldr r3, [r7, #4] 80064da: 681b ldr r3, [r3, #0] 80064dc: f422 4290 bic.w r2, r2, #18432 @ 0x4800 80064e0: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80064e2: 687b ldr r3, [r7, #4] 80064e4: 681b ldr r3, [r3, #0] 80064e6: 695a ldr r2, [r3, #20] 80064e8: 687b ldr r3, [r7, #4] 80064ea: 681b ldr r3, [r3, #0] 80064ec: f022 022a bic.w r2, r2, #42 @ 0x2a 80064f0: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 80064f2: 687b ldr r3, [r7, #4] 80064f4: 681b ldr r3, [r3, #0] 80064f6: 68da ldr r2, [r3, #12] 80064f8: 687b ldr r3, [r7, #4] 80064fa: 681b ldr r3, [r3, #0] 80064fc: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8006500: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8006502: 687b ldr r3, [r7, #4] 8006504: 2200 movs r2, #0 8006506: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8006508: 687b ldr r3, [r7, #4] 800650a: 2220 movs r2, #32 800650c: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8006510: 687b ldr r3, [r7, #4] 8006512: 2220 movs r2, #32 8006514: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8006518: 687b ldr r3, [r7, #4] 800651a: 2200 movs r2, #0 800651c: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 800651e: 2300 movs r3, #0 } 8006520: 4618 mov r0, r3 8006522: 3708 adds r7, #8 8006524: 46bd mov sp, r7 8006526: bd80 pop {r7, pc} 08006528 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8006528: b580 push {r7, lr} 800652a: b08c sub sp, #48 @ 0x30 800652c: af00 add r7, sp, #0 800652e: 60f8 str r0, [r7, #12] 8006530: 60b9 str r1, [r7, #8] 8006532: 4613 mov r3, r2 8006534: 80fb strh r3, [r7, #6] const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8006536: 68fb ldr r3, [r7, #12] 8006538: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800653c: b2db uxtb r3, r3 800653e: 2b20 cmp r3, #32 8006540: d162 bne.n 8006608 { if ((pData == NULL) || (Size == 0U)) 8006542: 68bb ldr r3, [r7, #8] 8006544: 2b00 cmp r3, #0 8006546: d002 beq.n 800654e 8006548: 88fb ldrh r3, [r7, #6] 800654a: 2b00 cmp r3, #0 800654c: d101 bne.n 8006552 { return HAL_ERROR; 800654e: 2301 movs r3, #1 8006550: e05b b.n 800660a } huart->pTxBuffPtr = pData; 8006552: 68ba ldr r2, [r7, #8] 8006554: 68fb ldr r3, [r7, #12] 8006556: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8006558: 68fb ldr r3, [r7, #12] 800655a: 88fa ldrh r2, [r7, #6] 800655c: 849a strh r2, [r3, #36] @ 0x24 huart->TxXferCount = Size; 800655e: 68fb ldr r3, [r7, #12] 8006560: 88fa ldrh r2, [r7, #6] 8006562: 84da strh r2, [r3, #38] @ 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8006564: 68fb ldr r3, [r7, #12] 8006566: 2200 movs r2, #0 8006568: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_BUSY_TX; 800656a: 68fb ldr r3, [r7, #12] 800656c: 2221 movs r2, #33 @ 0x21 800656e: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 8006572: 68fb ldr r3, [r7, #12] 8006574: 6b9b ldr r3, [r3, #56] @ 0x38 8006576: 4a27 ldr r2, [pc, #156] @ (8006614 ) 8006578: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 800657a: 68fb ldr r3, [r7, #12] 800657c: 6b9b ldr r3, [r3, #56] @ 0x38 800657e: 4a26 ldr r2, [pc, #152] @ (8006618 ) 8006580: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 8006582: 68fb ldr r3, [r7, #12] 8006584: 6b9b ldr r3, [r3, #56] @ 0x38 8006586: 4a25 ldr r2, [pc, #148] @ (800661c ) 8006588: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 800658a: 68fb ldr r3, [r7, #12] 800658c: 6b9b ldr r3, [r3, #56] @ 0x38 800658e: 2200 movs r2, #0 8006590: 651a str r2, [r3, #80] @ 0x50 /* Enable the UART transmit DMA stream */ tmp = (const uint32_t *)&pData; 8006592: f107 0308 add.w r3, r7, #8 8006596: 62fb str r3, [r7, #44] @ 0x2c if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK) 8006598: 68fb ldr r3, [r7, #12] 800659a: 6b98 ldr r0, [r3, #56] @ 0x38 800659c: 6afb ldr r3, [r7, #44] @ 0x2c 800659e: 6819 ldr r1, [r3, #0] 80065a0: 68fb ldr r3, [r7, #12] 80065a2: 681b ldr r3, [r3, #0] 80065a4: 3304 adds r3, #4 80065a6: 461a mov r2, r3 80065a8: 88fb ldrh r3, [r7, #6] 80065aa: f7fb febd bl 8002328 80065ae: 4603 mov r3, r0 80065b0: 2b00 cmp r3, #0 80065b2: d008 beq.n 80065c6 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 80065b4: 68fb ldr r3, [r7, #12] 80065b6: 2210 movs r2, #16 80065b8: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; 80065ba: 68fb ldr r3, [r7, #12] 80065bc: 2220 movs r2, #32 80065be: f883 2041 strb.w r2, [r3, #65] @ 0x41 return HAL_ERROR; 80065c2: 2301 movs r3, #1 80065c4: e021 b.n 800660a } /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 80065c6: 68fb ldr r3, [r7, #12] 80065c8: 681b ldr r3, [r3, #0] 80065ca: f06f 0240 mvn.w r2, #64 @ 0x40 80065ce: 601a str r2, [r3, #0] /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 80065d0: 68fb ldr r3, [r7, #12] 80065d2: 681b ldr r3, [r3, #0] 80065d4: 3314 adds r3, #20 80065d6: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80065d8: 69bb ldr r3, [r7, #24] 80065da: e853 3f00 ldrex r3, [r3] 80065de: 617b str r3, [r7, #20] return(result); 80065e0: 697b ldr r3, [r7, #20] 80065e2: f043 0380 orr.w r3, r3, #128 @ 0x80 80065e6: 62bb str r3, [r7, #40] @ 0x28 80065e8: 68fb ldr r3, [r7, #12] 80065ea: 681b ldr r3, [r3, #0] 80065ec: 3314 adds r3, #20 80065ee: 6aba ldr r2, [r7, #40] @ 0x28 80065f0: 627a str r2, [r7, #36] @ 0x24 80065f2: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80065f4: 6a39 ldr r1, [r7, #32] 80065f6: 6a7a ldr r2, [r7, #36] @ 0x24 80065f8: e841 2300 strex r3, r2, [r1] 80065fc: 61fb str r3, [r7, #28] return(result); 80065fe: 69fb ldr r3, [r7, #28] 8006600: 2b00 cmp r3, #0 8006602: d1e5 bne.n 80065d0 return HAL_OK; 8006604: 2300 movs r3, #0 8006606: e000 b.n 800660a } else { return HAL_BUSY; 8006608: 2302 movs r3, #2 } } 800660a: 4618 mov r0, r3 800660c: 3730 adds r7, #48 @ 0x30 800660e: 46bd mov sp, r7 8006610: bd80 pop {r7, pc} 8006612: bf00 nop 8006614: 08006c15 .word 0x08006c15 8006618: 08006caf .word 0x08006caf 800661c: 08006e33 .word 0x08006e33 08006620 : * @param Size Amount of data elements (u8 or u16) to be received. * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8006620: b580 push {r7, lr} 8006622: b084 sub sp, #16 8006624: af00 add r7, sp, #0 8006626: 60f8 str r0, [r7, #12] 8006628: 60b9 str r1, [r7, #8] 800662a: 4613 mov r3, r2 800662c: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 800662e: 68fb ldr r3, [r7, #12] 8006630: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8006634: b2db uxtb r3, r3 8006636: 2b20 cmp r3, #32 8006638: d112 bne.n 8006660 { if ((pData == NULL) || (Size == 0U)) 800663a: 68bb ldr r3, [r7, #8] 800663c: 2b00 cmp r3, #0 800663e: d002 beq.n 8006646 8006640: 88fb ldrh r3, [r7, #6] 8006642: 2b00 cmp r3, #0 8006644: d101 bne.n 800664a { return HAL_ERROR; 8006646: 2301 movs r3, #1 8006648: e00b b.n 8006662 } /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800664a: 68fb ldr r3, [r7, #12] 800664c: 2200 movs r2, #0 800664e: 631a str r2, [r3, #48] @ 0x30 return (UART_Start_Receive_DMA(huart, pData, Size)); 8006650: 88fb ldrh r3, [r7, #6] 8006652: 461a mov r2, r3 8006654: 68b9 ldr r1, [r7, #8] 8006656: 68f8 ldr r0, [r7, #12] 8006658: f000 fc36 bl 8006ec8 800665c: 4603 mov r3, r0 800665e: e000 b.n 8006662 } else { return HAL_BUSY; 8006660: 2302 movs r3, #2 } } 8006662: 4618 mov r0, r3 8006664: 3710 adds r7, #16 8006666: 46bd mov sp, r7 8006668: bd80 pop {r7, pc} ... 0800666c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 800666c: b580 push {r7, lr} 800666e: b0ba sub sp, #232 @ 0xe8 8006670: af00 add r7, sp, #0 8006672: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8006674: 687b ldr r3, [r7, #4] 8006676: 681b ldr r3, [r3, #0] 8006678: 681b ldr r3, [r3, #0] 800667a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 800667e: 687b ldr r3, [r7, #4] 8006680: 681b ldr r3, [r3, #0] 8006682: 68db ldr r3, [r3, #12] 8006684: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8006688: 687b ldr r3, [r7, #4] 800668a: 681b ldr r3, [r3, #0] 800668c: 695b ldr r3, [r3, #20] 800668e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags = 0x00U; 8006692: 2300 movs r3, #0 8006694: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 uint32_t dmarequest = 0x00U; 8006698: 2300 movs r3, #0 800669a: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 800669e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80066a2: f003 030f and.w r3, r3, #15 80066a6: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == RESET) 80066aa: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80066ae: 2b00 cmp r3, #0 80066b0: d10f bne.n 80066d2 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80066b2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80066b6: f003 0320 and.w r3, r3, #32 80066ba: 2b00 cmp r3, #0 80066bc: d009 beq.n 80066d2 80066be: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80066c2: f003 0320 and.w r3, r3, #32 80066c6: 2b00 cmp r3, #0 80066c8: d003 beq.n 80066d2 { UART_Receive_IT(huart); 80066ca: 6878 ldr r0, [r7, #4] 80066cc: f000 fda6 bl 800721c return; 80066d0: e273 b.n 8006bba } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) 80066d2: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80066d6: 2b00 cmp r3, #0 80066d8: f000 80de beq.w 8006898 80066dc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80066e0: f003 0301 and.w r3, r3, #1 80066e4: 2b00 cmp r3, #0 80066e6: d106 bne.n 80066f6 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 80066e8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80066ec: f403 7390 and.w r3, r3, #288 @ 0x120 80066f0: 2b00 cmp r3, #0 80066f2: f000 80d1 beq.w 8006898 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 80066f6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80066fa: f003 0301 and.w r3, r3, #1 80066fe: 2b00 cmp r3, #0 8006700: d00b beq.n 800671a 8006702: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006706: f403 7380 and.w r3, r3, #256 @ 0x100 800670a: 2b00 cmp r3, #0 800670c: d005 beq.n 800671a { huart->ErrorCode |= HAL_UART_ERROR_PE; 800670e: 687b ldr r3, [r7, #4] 8006710: 6c5b ldr r3, [r3, #68] @ 0x44 8006712: f043 0201 orr.w r2, r3, #1 8006716: 687b ldr r3, [r7, #4] 8006718: 645a str r2, [r3, #68] @ 0x44 } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 800671a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800671e: f003 0304 and.w r3, r3, #4 8006722: 2b00 cmp r3, #0 8006724: d00b beq.n 800673e 8006726: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800672a: f003 0301 and.w r3, r3, #1 800672e: 2b00 cmp r3, #0 8006730: d005 beq.n 800673e { huart->ErrorCode |= HAL_UART_ERROR_NE; 8006732: 687b ldr r3, [r7, #4] 8006734: 6c5b ldr r3, [r3, #68] @ 0x44 8006736: f043 0202 orr.w r2, r3, #2 800673a: 687b ldr r3, [r7, #4] 800673c: 645a str r2, [r3, #68] @ 0x44 } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 800673e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006742: f003 0302 and.w r3, r3, #2 8006746: 2b00 cmp r3, #0 8006748: d00b beq.n 8006762 800674a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800674e: f003 0301 and.w r3, r3, #1 8006752: 2b00 cmp r3, #0 8006754: d005 beq.n 8006762 { huart->ErrorCode |= HAL_UART_ERROR_FE; 8006756: 687b ldr r3, [r7, #4] 8006758: 6c5b ldr r3, [r3, #68] @ 0x44 800675a: f043 0204 orr.w r2, r3, #4 800675e: 687b ldr r3, [r7, #4] 8006760: 645a str r2, [r3, #68] @ 0x44 } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) 8006762: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006766: f003 0308 and.w r3, r3, #8 800676a: 2b00 cmp r3, #0 800676c: d011 beq.n 8006792 800676e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006772: f003 0320 and.w r3, r3, #32 8006776: 2b00 cmp r3, #0 8006778: d105 bne.n 8006786 || ((cr3its & USART_CR3_EIE) != RESET))) 800677a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800677e: f003 0301 and.w r3, r3, #1 8006782: 2b00 cmp r3, #0 8006784: d005 beq.n 8006792 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8006786: 687b ldr r3, [r7, #4] 8006788: 6c5b ldr r3, [r3, #68] @ 0x44 800678a: f043 0208 orr.w r2, r3, #8 800678e: 687b ldr r3, [r7, #4] 8006790: 645a str r2, [r3, #68] @ 0x44 } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8006792: 687b ldr r3, [r7, #4] 8006794: 6c5b ldr r3, [r3, #68] @ 0x44 8006796: 2b00 cmp r3, #0 8006798: f000 820a beq.w 8006bb0 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 800679c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80067a0: f003 0320 and.w r3, r3, #32 80067a4: 2b00 cmp r3, #0 80067a6: d008 beq.n 80067ba 80067a8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80067ac: f003 0320 and.w r3, r3, #32 80067b0: 2b00 cmp r3, #0 80067b2: d002 beq.n 80067ba { UART_Receive_IT(huart); 80067b4: 6878 ldr r0, [r7, #4] 80067b6: f000 fd31 bl 800721c } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 80067ba: 687b ldr r3, [r7, #4] 80067bc: 681b ldr r3, [r3, #0] 80067be: 695b ldr r3, [r3, #20] 80067c0: f003 0340 and.w r3, r3, #64 @ 0x40 80067c4: 2b40 cmp r3, #64 @ 0x40 80067c6: bf0c ite eq 80067c8: 2301 moveq r3, #1 80067ca: 2300 movne r3, #0 80067cc: b2db uxtb r3, r3 80067ce: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 80067d2: 687b ldr r3, [r7, #4] 80067d4: 6c5b ldr r3, [r3, #68] @ 0x44 80067d6: f003 0308 and.w r3, r3, #8 80067da: 2b00 cmp r3, #0 80067dc: d103 bne.n 80067e6 80067de: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 80067e2: 2b00 cmp r3, #0 80067e4: d04f beq.n 8006886 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 80067e6: 6878 ldr r0, [r7, #4] 80067e8: f000 fc3c bl 8007064 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80067ec: 687b ldr r3, [r7, #4] 80067ee: 681b ldr r3, [r3, #0] 80067f0: 695b ldr r3, [r3, #20] 80067f2: f003 0340 and.w r3, r3, #64 @ 0x40 80067f6: 2b40 cmp r3, #64 @ 0x40 80067f8: d141 bne.n 800687e { ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80067fa: 687b ldr r3, [r7, #4] 80067fc: 681b ldr r3, [r3, #0] 80067fe: 3314 adds r3, #20 8006800: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006804: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8006808: e853 3f00 ldrex r3, [r3] 800680c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8006810: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8006814: f023 0340 bic.w r3, r3, #64 @ 0x40 8006818: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 800681c: 687b ldr r3, [r7, #4] 800681e: 681b ldr r3, [r3, #0] 8006820: 3314 adds r3, #20 8006822: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8006826: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 800682a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800682e: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8006832: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8006836: e841 2300 strex r3, r2, [r1] 800683a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 800683e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8006842: 2b00 cmp r3, #0 8006844: d1d9 bne.n 80067fa /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) 8006846: 687b ldr r3, [r7, #4] 8006848: 6bdb ldr r3, [r3, #60] @ 0x3c 800684a: 2b00 cmp r3, #0 800684c: d013 beq.n 8006876 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 800684e: 687b ldr r3, [r7, #4] 8006850: 6bdb ldr r3, [r3, #60] @ 0x3c 8006852: 4a8a ldr r2, [pc, #552] @ (8006a7c ) 8006854: 651a str r2, [r3, #80] @ 0x50 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8006856: 687b ldr r3, [r7, #4] 8006858: 6bdb ldr r3, [r3, #60] @ 0x3c 800685a: 4618 mov r0, r3 800685c: f7fb fe2c bl 80024b8 8006860: 4603 mov r3, r0 8006862: 2b00 cmp r3, #0 8006864: d016 beq.n 8006894 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8006866: 687b ldr r3, [r7, #4] 8006868: 6bdb ldr r3, [r3, #60] @ 0x3c 800686a: 6d1b ldr r3, [r3, #80] @ 0x50 800686c: 687a ldr r2, [r7, #4] 800686e: 6bd2 ldr r2, [r2, #60] @ 0x3c 8006870: 4610 mov r0, r2 8006872: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006874: e00e b.n 8006894 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006876: 6878 ldr r0, [r7, #4] 8006878: f7fa fab0 bl 8000ddc if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800687c: e00a b.n 8006894 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800687e: 6878 ldr r0, [r7, #4] 8006880: f7fa faac bl 8000ddc if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006884: e006 b.n 8006894 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006886: 6878 ldr r0, [r7, #4] 8006888: f7fa faa8 bl 8000ddc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 800688c: 687b ldr r3, [r7, #4] 800688e: 2200 movs r2, #0 8006890: 645a str r2, [r3, #68] @ 0x44 } } return; 8006892: e18d b.n 8006bb0 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8006894: bf00 nop return; 8006896: e18b b.n 8006bb0 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006898: 687b ldr r3, [r7, #4] 800689a: 6b1b ldr r3, [r3, #48] @ 0x30 800689c: 2b01 cmp r3, #1 800689e: f040 8167 bne.w 8006b70 && ((isrflags & USART_SR_IDLE) != 0U) 80068a2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80068a6: f003 0310 and.w r3, r3, #16 80068aa: 2b00 cmp r3, #0 80068ac: f000 8160 beq.w 8006b70 && ((cr1its & USART_CR1_IDLEIE) != 0U)) 80068b0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80068b4: f003 0310 and.w r3, r3, #16 80068b8: 2b00 cmp r3, #0 80068ba: f000 8159 beq.w 8006b70 { __HAL_UART_CLEAR_IDLEFLAG(huart); 80068be: 2300 movs r3, #0 80068c0: 60bb str r3, [r7, #8] 80068c2: 687b ldr r3, [r7, #4] 80068c4: 681b ldr r3, [r3, #0] 80068c6: 681b ldr r3, [r3, #0] 80068c8: 60bb str r3, [r7, #8] 80068ca: 687b ldr r3, [r7, #4] 80068cc: 681b ldr r3, [r3, #0] 80068ce: 685b ldr r3, [r3, #4] 80068d0: 60bb str r3, [r7, #8] 80068d2: 68bb ldr r3, [r7, #8] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80068d4: 687b ldr r3, [r7, #4] 80068d6: 681b ldr r3, [r3, #0] 80068d8: 695b ldr r3, [r3, #20] 80068da: f003 0340 and.w r3, r3, #64 @ 0x40 80068de: 2b40 cmp r3, #64 @ 0x40 80068e0: f040 80ce bne.w 8006a80 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 80068e4: 687b ldr r3, [r7, #4] 80068e6: 6bdb ldr r3, [r3, #60] @ 0x3c 80068e8: 681b ldr r3, [r3, #0] 80068ea: 685b ldr r3, [r3, #4] 80068ec: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 80068f0: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 80068f4: 2b00 cmp r3, #0 80068f6: f000 80a9 beq.w 8006a4c && (nb_remaining_rx_data < huart->RxXferSize)) 80068fa: 687b ldr r3, [r7, #4] 80068fc: 8d9b ldrh r3, [r3, #44] @ 0x2c 80068fe: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8006902: 429a cmp r2, r3 8006904: f080 80a2 bcs.w 8006a4c { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8006908: 687b ldr r3, [r7, #4] 800690a: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 800690e: 85da strh r2, [r3, #46] @ 0x2e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8006910: 687b ldr r3, [r7, #4] 8006912: 6bdb ldr r3, [r3, #60] @ 0x3c 8006914: 69db ldr r3, [r3, #28] 8006916: f5b3 7f80 cmp.w r3, #256 @ 0x100 800691a: f000 8088 beq.w 8006a2e { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800691e: 687b ldr r3, [r7, #4] 8006920: 681b ldr r3, [r3, #0] 8006922: 330c adds r3, #12 8006924: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006928: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800692c: e853 3f00 ldrex r3, [r3] 8006930: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8006934: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8006938: f423 7380 bic.w r3, r3, #256 @ 0x100 800693c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006940: 687b ldr r3, [r7, #4] 8006942: 681b ldr r3, [r3, #0] 8006944: 330c adds r3, #12 8006946: f8d7 20b8 ldr.w r2, [r7, #184] @ 0xb8 800694a: f8c7 2094 str.w r2, [r7, #148] @ 0x94 800694e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006952: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8006956: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 800695a: e841 2300 strex r3, r2, [r1] 800695e: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8006962: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8006966: 2b00 cmp r3, #0 8006968: d1d9 bne.n 800691e ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800696a: 687b ldr r3, [r7, #4] 800696c: 681b ldr r3, [r3, #0] 800696e: 3314 adds r3, #20 8006970: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006972: 6f7b ldr r3, [r7, #116] @ 0x74 8006974: e853 3f00 ldrex r3, [r3] 8006978: 673b str r3, [r7, #112] @ 0x70 return(result); 800697a: 6f3b ldr r3, [r7, #112] @ 0x70 800697c: f023 0301 bic.w r3, r3, #1 8006980: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8006984: 687b ldr r3, [r7, #4] 8006986: 681b ldr r3, [r3, #0] 8006988: 3314 adds r3, #20 800698a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 800698e: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8006992: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006994: 6ff9 ldr r1, [r7, #124] @ 0x7c 8006996: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 800699a: e841 2300 strex r3, r2, [r1] 800699e: 67bb str r3, [r7, #120] @ 0x78 return(result); 80069a0: 6fbb ldr r3, [r7, #120] @ 0x78 80069a2: 2b00 cmp r3, #0 80069a4: d1e1 bne.n 800696a /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80069a6: 687b ldr r3, [r7, #4] 80069a8: 681b ldr r3, [r3, #0] 80069aa: 3314 adds r3, #20 80069ac: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80069ae: 6e3b ldr r3, [r7, #96] @ 0x60 80069b0: e853 3f00 ldrex r3, [r3] 80069b4: 65fb str r3, [r7, #92] @ 0x5c return(result); 80069b6: 6dfb ldr r3, [r7, #92] @ 0x5c 80069b8: f023 0340 bic.w r3, r3, #64 @ 0x40 80069bc: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 80069c0: 687b ldr r3, [r7, #4] 80069c2: 681b ldr r3, [r3, #0] 80069c4: 3314 adds r3, #20 80069c6: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 80069ca: 66fa str r2, [r7, #108] @ 0x6c 80069cc: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80069ce: 6eb9 ldr r1, [r7, #104] @ 0x68 80069d0: 6efa ldr r2, [r7, #108] @ 0x6c 80069d2: e841 2300 strex r3, r2, [r1] 80069d6: 667b str r3, [r7, #100] @ 0x64 return(result); 80069d8: 6e7b ldr r3, [r7, #100] @ 0x64 80069da: 2b00 cmp r3, #0 80069dc: d1e3 bne.n 80069a6 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80069de: 687b ldr r3, [r7, #4] 80069e0: 2220 movs r2, #32 80069e2: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80069e6: 687b ldr r3, [r7, #4] 80069e8: 2200 movs r2, #0 80069ea: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80069ec: 687b ldr r3, [r7, #4] 80069ee: 681b ldr r3, [r3, #0] 80069f0: 330c adds r3, #12 80069f2: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80069f4: 6cfb ldr r3, [r7, #76] @ 0x4c 80069f6: e853 3f00 ldrex r3, [r3] 80069fa: 64bb str r3, [r7, #72] @ 0x48 return(result); 80069fc: 6cbb ldr r3, [r7, #72] @ 0x48 80069fe: f023 0310 bic.w r3, r3, #16 8006a02: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8006a06: 687b ldr r3, [r7, #4] 8006a08: 681b ldr r3, [r3, #0] 8006a0a: 330c adds r3, #12 8006a0c: f8d7 20ac ldr.w r2, [r7, #172] @ 0xac 8006a10: 65ba str r2, [r7, #88] @ 0x58 8006a12: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006a14: 6d79 ldr r1, [r7, #84] @ 0x54 8006a16: 6dba ldr r2, [r7, #88] @ 0x58 8006a18: e841 2300 strex r3, r2, [r1] 8006a1c: 653b str r3, [r7, #80] @ 0x50 return(result); 8006a1e: 6d3b ldr r3, [r7, #80] @ 0x50 8006a20: 2b00 cmp r3, #0 8006a22: d1e3 bne.n 80069ec /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8006a24: 687b ldr r3, [r7, #4] 8006a26: 6bdb ldr r3, [r3, #60] @ 0x3c 8006a28: 4618 mov r0, r3 8006a2a: f7fb fcd5 bl 80023d8 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006a2e: 687b ldr r3, [r7, #4] 8006a30: 2202 movs r2, #2 8006a32: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8006a34: 687b ldr r3, [r7, #4] 8006a36: 8d9a ldrh r2, [r3, #44] @ 0x2c 8006a38: 687b ldr r3, [r7, #4] 8006a3a: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006a3c: b29b uxth r3, r3 8006a3e: 1ad3 subs r3, r2, r3 8006a40: b29b uxth r3, r3 8006a42: 4619 mov r1, r3 8006a44: 6878 ldr r0, [r7, #4] 8006a46: f000 f8d9 bl 8006bfc HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 8006a4a: e0b3 b.n 8006bb4 if (nb_remaining_rx_data == huart->RxXferSize) 8006a4c: 687b ldr r3, [r7, #4] 8006a4e: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006a50: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8006a54: 429a cmp r2, r3 8006a56: f040 80ad bne.w 8006bb4 if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) 8006a5a: 687b ldr r3, [r7, #4] 8006a5c: 6bdb ldr r3, [r3, #60] @ 0x3c 8006a5e: 69db ldr r3, [r3, #28] 8006a60: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006a64: f040 80a6 bne.w 8006bb4 huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006a68: 687b ldr r3, [r7, #4] 8006a6a: 2202 movs r2, #2 8006a6c: 635a str r2, [r3, #52] @ 0x34 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006a6e: 687b ldr r3, [r7, #4] 8006a70: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006a72: 4619 mov r1, r3 8006a74: 6878 ldr r0, [r7, #4] 8006a76: f000 f8c1 bl 8006bfc return; 8006a7a: e09b b.n 8006bb4 8006a7c: 0800712b .word 0x0800712b else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8006a80: 687b ldr r3, [r7, #4] 8006a82: 8d9a ldrh r2, [r3, #44] @ 0x2c 8006a84: 687b ldr r3, [r7, #4] 8006a86: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006a88: b29b uxth r3, r3 8006a8a: 1ad3 subs r3, r2, r3 8006a8c: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8006a90: 687b ldr r3, [r7, #4] 8006a92: 8ddb ldrh r3, [r3, #46] @ 0x2e 8006a94: b29b uxth r3, r3 8006a96: 2b00 cmp r3, #0 8006a98: f000 808e beq.w 8006bb8 && (nb_rx_data > 0U)) 8006a9c: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8006aa0: 2b00 cmp r3, #0 8006aa2: f000 8089 beq.w 8006bb8 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8006aa6: 687b ldr r3, [r7, #4] 8006aa8: 681b ldr r3, [r3, #0] 8006aaa: 330c adds r3, #12 8006aac: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006aae: 6bbb ldr r3, [r7, #56] @ 0x38 8006ab0: e853 3f00 ldrex r3, [r3] 8006ab4: 637b str r3, [r7, #52] @ 0x34 return(result); 8006ab6: 6b7b ldr r3, [r7, #52] @ 0x34 8006ab8: f423 7390 bic.w r3, r3, #288 @ 0x120 8006abc: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8006ac0: 687b ldr r3, [r7, #4] 8006ac2: 681b ldr r3, [r3, #0] 8006ac4: 330c adds r3, #12 8006ac6: f8d7 20c8 ldr.w r2, [r7, #200] @ 0xc8 8006aca: 647a str r2, [r7, #68] @ 0x44 8006acc: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006ace: 6c39 ldr r1, [r7, #64] @ 0x40 8006ad0: 6c7a ldr r2, [r7, #68] @ 0x44 8006ad2: e841 2300 strex r3, r2, [r1] 8006ad6: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006ad8: 6bfb ldr r3, [r7, #60] @ 0x3c 8006ada: 2b00 cmp r3, #0 8006adc: d1e3 bne.n 8006aa6 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006ade: 687b ldr r3, [r7, #4] 8006ae0: 681b ldr r3, [r3, #0] 8006ae2: 3314 adds r3, #20 8006ae4: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006ae6: 6a7b ldr r3, [r7, #36] @ 0x24 8006ae8: e853 3f00 ldrex r3, [r3] 8006aec: 623b str r3, [r7, #32] return(result); 8006aee: 6a3b ldr r3, [r7, #32] 8006af0: f023 0301 bic.w r3, r3, #1 8006af4: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8006af8: 687b ldr r3, [r7, #4] 8006afa: 681b ldr r3, [r3, #0] 8006afc: 3314 adds r3, #20 8006afe: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8006b02: 633a str r2, [r7, #48] @ 0x30 8006b04: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006b06: 6af9 ldr r1, [r7, #44] @ 0x2c 8006b08: 6b3a ldr r2, [r7, #48] @ 0x30 8006b0a: e841 2300 strex r3, r2, [r1] 8006b0e: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006b10: 6abb ldr r3, [r7, #40] @ 0x28 8006b12: 2b00 cmp r3, #0 8006b14: d1e3 bne.n 8006ade /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006b16: 687b ldr r3, [r7, #4] 8006b18: 2220 movs r2, #32 8006b1a: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006b1e: 687b ldr r3, [r7, #4] 8006b20: 2200 movs r2, #0 8006b22: 631a str r2, [r3, #48] @ 0x30 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006b24: 687b ldr r3, [r7, #4] 8006b26: 681b ldr r3, [r3, #0] 8006b28: 330c adds r3, #12 8006b2a: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006b2c: 693b ldr r3, [r7, #16] 8006b2e: e853 3f00 ldrex r3, [r3] 8006b32: 60fb str r3, [r7, #12] return(result); 8006b34: 68fb ldr r3, [r7, #12] 8006b36: f023 0310 bic.w r3, r3, #16 8006b3a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8006b3e: 687b ldr r3, [r7, #4] 8006b40: 681b ldr r3, [r3, #0] 8006b42: 330c adds r3, #12 8006b44: f8d7 20c0 ldr.w r2, [r7, #192] @ 0xc0 8006b48: 61fa str r2, [r7, #28] 8006b4a: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006b4c: 69b9 ldr r1, [r7, #24] 8006b4e: 69fa ldr r2, [r7, #28] 8006b50: e841 2300 strex r3, r2, [r1] 8006b54: 617b str r3, [r7, #20] return(result); 8006b56: 697b ldr r3, [r7, #20] 8006b58: 2b00 cmp r3, #0 8006b5a: d1e3 bne.n 8006b24 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8006b5c: 687b ldr r3, [r7, #4] 8006b5e: 2202 movs r2, #2 8006b60: 635a str r2, [r3, #52] @ 0x34 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8006b62: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8006b66: 4619 mov r1, r3 8006b68: 6878 ldr r0, [r7, #4] 8006b6a: f000 f847 bl 8006bfc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; 8006b6e: e023 b.n 8006bb8 } } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8006b70: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006b74: f003 0380 and.w r3, r3, #128 @ 0x80 8006b78: 2b00 cmp r3, #0 8006b7a: d009 beq.n 8006b90 8006b7c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006b80: f003 0380 and.w r3, r3, #128 @ 0x80 8006b84: 2b00 cmp r3, #0 8006b86: d003 beq.n 8006b90 { UART_Transmit_IT(huart); 8006b88: 6878 ldr r0, [r7, #4] 8006b8a: f000 fadf bl 800714c return; 8006b8e: e014 b.n 8006bba } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8006b90: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8006b94: f003 0340 and.w r3, r3, #64 @ 0x40 8006b98: 2b00 cmp r3, #0 8006b9a: d00e beq.n 8006bba 8006b9c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8006ba0: f003 0340 and.w r3, r3, #64 @ 0x40 8006ba4: 2b00 cmp r3, #0 8006ba6: d008 beq.n 8006bba { UART_EndTransmit_IT(huart); 8006ba8: 6878 ldr r0, [r7, #4] 8006baa: f000 fb1f bl 80071ec return; 8006bae: e004 b.n 8006bba return; 8006bb0: bf00 nop 8006bb2: e002 b.n 8006bba return; 8006bb4: bf00 nop 8006bb6: e000 b.n 8006bba return; 8006bb8: bf00 nop } } 8006bba: 37e8 adds r7, #232 @ 0xe8 8006bbc: 46bd mov sp, r7 8006bbe: bd80 pop {r7, pc} 08006bc0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8006bc0: b480 push {r7} 8006bc2: b083 sub sp, #12 8006bc4: af00 add r7, sp, #0 8006bc6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8006bc8: bf00 nop 8006bca: 370c adds r7, #12 8006bcc: 46bd mov sp, r7 8006bce: f85d 7b04 ldr.w r7, [sp], #4 8006bd2: 4770 bx lr 08006bd4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8006bd4: b480 push {r7} 8006bd6: b083 sub sp, #12 8006bd8: af00 add r7, sp, #0 8006bda: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 8006bdc: bf00 nop 8006bde: 370c adds r7, #12 8006be0: 46bd mov sp, r7 8006be2: f85d 7b04 ldr.w r7, [sp], #4 8006be6: 4770 bx lr 08006be8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8006be8: b480 push {r7} 8006bea: b083 sub sp, #12 8006bec: af00 add r7, sp, #0 8006bee: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 8006bf0: bf00 nop 8006bf2: 370c adds r7, #12 8006bf4: 46bd mov sp, r7 8006bf6: f85d 7b04 ldr.w r7, [sp], #4 8006bfa: 4770 bx lr 08006bfc : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 8006bfc: b480 push {r7} 8006bfe: b083 sub sp, #12 8006c00: af00 add r7, sp, #0 8006c02: 6078 str r0, [r7, #4] 8006c04: 460b mov r3, r1 8006c06: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 8006c08: bf00 nop 8006c0a: 370c adds r7, #12 8006c0c: 46bd mov sp, r7 8006c0e: f85d 7b04 ldr.w r7, [sp], #4 8006c12: 4770 bx lr 08006c14 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 8006c14: b580 push {r7, lr} 8006c16: b090 sub sp, #64 @ 0x40 8006c18: af00 add r7, sp, #0 8006c1a: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006c1c: 687b ldr r3, [r7, #4] 8006c1e: 6b9b ldr r3, [r3, #56] @ 0x38 8006c20: 63fb str r3, [r7, #60] @ 0x3c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 8006c22: 687b ldr r3, [r7, #4] 8006c24: 681b ldr r3, [r3, #0] 8006c26: 681b ldr r3, [r3, #0] 8006c28: f403 7380 and.w r3, r3, #256 @ 0x100 8006c2c: 2b00 cmp r3, #0 8006c2e: d137 bne.n 8006ca0 { huart->TxXferCount = 0x00U; 8006c30: 6bfb ldr r3, [r7, #60] @ 0x3c 8006c32: 2200 movs r2, #0 8006c34: 84da strh r2, [r3, #38] @ 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8006c36: 6bfb ldr r3, [r7, #60] @ 0x3c 8006c38: 681b ldr r3, [r3, #0] 8006c3a: 3314 adds r3, #20 8006c3c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006c3e: 6a7b ldr r3, [r7, #36] @ 0x24 8006c40: e853 3f00 ldrex r3, [r3] 8006c44: 623b str r3, [r7, #32] return(result); 8006c46: 6a3b ldr r3, [r7, #32] 8006c48: f023 0380 bic.w r3, r3, #128 @ 0x80 8006c4c: 63bb str r3, [r7, #56] @ 0x38 8006c4e: 6bfb ldr r3, [r7, #60] @ 0x3c 8006c50: 681b ldr r3, [r3, #0] 8006c52: 3314 adds r3, #20 8006c54: 6bba ldr r2, [r7, #56] @ 0x38 8006c56: 633a str r2, [r7, #48] @ 0x30 8006c58: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006c5a: 6af9 ldr r1, [r7, #44] @ 0x2c 8006c5c: 6b3a ldr r2, [r7, #48] @ 0x30 8006c5e: e841 2300 strex r3, r2, [r1] 8006c62: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006c64: 6abb ldr r3, [r7, #40] @ 0x28 8006c66: 2b00 cmp r3, #0 8006c68: d1e5 bne.n 8006c36 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8006c6a: 6bfb ldr r3, [r7, #60] @ 0x3c 8006c6c: 681b ldr r3, [r3, #0] 8006c6e: 330c adds r3, #12 8006c70: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006c72: 693b ldr r3, [r7, #16] 8006c74: e853 3f00 ldrex r3, [r3] 8006c78: 60fb str r3, [r7, #12] return(result); 8006c7a: 68fb ldr r3, [r7, #12] 8006c7c: f043 0340 orr.w r3, r3, #64 @ 0x40 8006c80: 637b str r3, [r7, #52] @ 0x34 8006c82: 6bfb ldr r3, [r7, #60] @ 0x3c 8006c84: 681b ldr r3, [r3, #0] 8006c86: 330c adds r3, #12 8006c88: 6b7a ldr r2, [r7, #52] @ 0x34 8006c8a: 61fa str r2, [r7, #28] 8006c8c: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006c8e: 69b9 ldr r1, [r7, #24] 8006c90: 69fa ldr r2, [r7, #28] 8006c92: e841 2300 strex r3, r2, [r1] 8006c96: 617b str r3, [r7, #20] return(result); 8006c98: 697b ldr r3, [r7, #20] 8006c9a: 2b00 cmp r3, #0 8006c9c: d1e5 bne.n 8006c6a #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8006c9e: e002 b.n 8006ca6 HAL_UART_TxCpltCallback(huart); 8006ca0: 6bf8 ldr r0, [r7, #60] @ 0x3c 8006ca2: f7ff ff8d bl 8006bc0 } 8006ca6: bf00 nop 8006ca8: 3740 adds r7, #64 @ 0x40 8006caa: 46bd mov sp, r7 8006cac: bd80 pop {r7, pc} 08006cae : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 8006cae: b580 push {r7, lr} 8006cb0: b084 sub sp, #16 8006cb2: af00 add r7, sp, #0 8006cb4: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006cb6: 687b ldr r3, [r7, #4] 8006cb8: 6b9b ldr r3, [r3, #56] @ 0x38 8006cba: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 8006cbc: 68f8 ldr r0, [r7, #12] 8006cbe: f7ff ff89 bl 8006bd4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006cc2: bf00 nop 8006cc4: 3710 adds r7, #16 8006cc6: 46bd mov sp, r7 8006cc8: bd80 pop {r7, pc} 08006cca : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 8006cca: b580 push {r7, lr} 8006ccc: b09c sub sp, #112 @ 0x70 8006cce: af00 add r7, sp, #0 8006cd0: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006cd2: 687b ldr r3, [r7, #4] 8006cd4: 6b9b ldr r3, [r3, #56] @ 0x38 8006cd6: 66fb str r3, [r7, #108] @ 0x6c /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 8006cd8: 687b ldr r3, [r7, #4] 8006cda: 681b ldr r3, [r3, #0] 8006cdc: 681b ldr r3, [r3, #0] 8006cde: f403 7380 and.w r3, r3, #256 @ 0x100 8006ce2: 2b00 cmp r3, #0 8006ce4: d172 bne.n 8006dcc { huart->RxXferCount = 0U; 8006ce6: 6efb ldr r3, [r7, #108] @ 0x6c 8006ce8: 2200 movs r2, #0 8006cea: 85da strh r2, [r3, #46] @ 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006cec: 6efb ldr r3, [r7, #108] @ 0x6c 8006cee: 681b ldr r3, [r3, #0] 8006cf0: 330c adds r3, #12 8006cf2: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006cf4: 6cfb ldr r3, [r7, #76] @ 0x4c 8006cf6: e853 3f00 ldrex r3, [r3] 8006cfa: 64bb str r3, [r7, #72] @ 0x48 return(result); 8006cfc: 6cbb ldr r3, [r7, #72] @ 0x48 8006cfe: f423 7380 bic.w r3, r3, #256 @ 0x100 8006d02: 66bb str r3, [r7, #104] @ 0x68 8006d04: 6efb ldr r3, [r7, #108] @ 0x6c 8006d06: 681b ldr r3, [r3, #0] 8006d08: 330c adds r3, #12 8006d0a: 6eba ldr r2, [r7, #104] @ 0x68 8006d0c: 65ba str r2, [r7, #88] @ 0x58 8006d0e: 657b str r3, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006d10: 6d79 ldr r1, [r7, #84] @ 0x54 8006d12: 6dba ldr r2, [r7, #88] @ 0x58 8006d14: e841 2300 strex r3, r2, [r1] 8006d18: 653b str r3, [r7, #80] @ 0x50 return(result); 8006d1a: 6d3b ldr r3, [r7, #80] @ 0x50 8006d1c: 2b00 cmp r3, #0 8006d1e: d1e5 bne.n 8006cec ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006d20: 6efb ldr r3, [r7, #108] @ 0x6c 8006d22: 681b ldr r3, [r3, #0] 8006d24: 3314 adds r3, #20 8006d26: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006d28: 6bbb ldr r3, [r7, #56] @ 0x38 8006d2a: e853 3f00 ldrex r3, [r3] 8006d2e: 637b str r3, [r7, #52] @ 0x34 return(result); 8006d30: 6b7b ldr r3, [r7, #52] @ 0x34 8006d32: f023 0301 bic.w r3, r3, #1 8006d36: 667b str r3, [r7, #100] @ 0x64 8006d38: 6efb ldr r3, [r7, #108] @ 0x6c 8006d3a: 681b ldr r3, [r3, #0] 8006d3c: 3314 adds r3, #20 8006d3e: 6e7a ldr r2, [r7, #100] @ 0x64 8006d40: 647a str r2, [r7, #68] @ 0x44 8006d42: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006d44: 6c39 ldr r1, [r7, #64] @ 0x40 8006d46: 6c7a ldr r2, [r7, #68] @ 0x44 8006d48: e841 2300 strex r3, r2, [r1] 8006d4c: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006d4e: 6bfb ldr r3, [r7, #60] @ 0x3c 8006d50: 2b00 cmp r3, #0 8006d52: d1e5 bne.n 8006d20 /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8006d54: 6efb ldr r3, [r7, #108] @ 0x6c 8006d56: 681b ldr r3, [r3, #0] 8006d58: 3314 adds r3, #20 8006d5a: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006d5c: 6a7b ldr r3, [r7, #36] @ 0x24 8006d5e: e853 3f00 ldrex r3, [r3] 8006d62: 623b str r3, [r7, #32] return(result); 8006d64: 6a3b ldr r3, [r7, #32] 8006d66: f023 0340 bic.w r3, r3, #64 @ 0x40 8006d6a: 663b str r3, [r7, #96] @ 0x60 8006d6c: 6efb ldr r3, [r7, #108] @ 0x6c 8006d6e: 681b ldr r3, [r3, #0] 8006d70: 3314 adds r3, #20 8006d72: 6e3a ldr r2, [r7, #96] @ 0x60 8006d74: 633a str r2, [r7, #48] @ 0x30 8006d76: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006d78: 6af9 ldr r1, [r7, #44] @ 0x2c 8006d7a: 6b3a ldr r2, [r7, #48] @ 0x30 8006d7c: e841 2300 strex r3, r2, [r1] 8006d80: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006d82: 6abb ldr r3, [r7, #40] @ 0x28 8006d84: 2b00 cmp r3, #0 8006d86: d1e5 bne.n 8006d54 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006d88: 6efb ldr r3, [r7, #108] @ 0x6c 8006d8a: 2220 movs r2, #32 8006d8c: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006d90: 6efb ldr r3, [r7, #108] @ 0x6c 8006d92: 6b1b ldr r3, [r3, #48] @ 0x30 8006d94: 2b01 cmp r3, #1 8006d96: d119 bne.n 8006dcc { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006d98: 6efb ldr r3, [r7, #108] @ 0x6c 8006d9a: 681b ldr r3, [r3, #0] 8006d9c: 330c adds r3, #12 8006d9e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006da0: 693b ldr r3, [r7, #16] 8006da2: e853 3f00 ldrex r3, [r3] 8006da6: 60fb str r3, [r7, #12] return(result); 8006da8: 68fb ldr r3, [r7, #12] 8006daa: f023 0310 bic.w r3, r3, #16 8006dae: 65fb str r3, [r7, #92] @ 0x5c 8006db0: 6efb ldr r3, [r7, #108] @ 0x6c 8006db2: 681b ldr r3, [r3, #0] 8006db4: 330c adds r3, #12 8006db6: 6dfa ldr r2, [r7, #92] @ 0x5c 8006db8: 61fa str r2, [r7, #28] 8006dba: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006dbc: 69b9 ldr r1, [r7, #24] 8006dbe: 69fa ldr r2, [r7, #28] 8006dc0: e841 2300 strex r3, r2, [r1] 8006dc4: 617b str r3, [r7, #20] return(result); 8006dc6: 697b ldr r3, [r7, #20] 8006dc8: 2b00 cmp r3, #0 8006dca: d1e5 bne.n 8006d98 } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8006dcc: 6efb ldr r3, [r7, #108] @ 0x6c 8006dce: 2200 movs r2, #0 8006dd0: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006dd2: 6efb ldr r3, [r7, #108] @ 0x6c 8006dd4: 6b1b ldr r3, [r3, #48] @ 0x30 8006dd6: 2b01 cmp r3, #1 8006dd8: d106 bne.n 8006de8 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006dda: 6efb ldr r3, [r7, #108] @ 0x6c 8006ddc: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006dde: 4619 mov r1, r3 8006de0: 6ef8 ldr r0, [r7, #108] @ 0x6c 8006de2: f7ff ff0b bl 8006bfc #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8006de6: e002 b.n 8006dee HAL_UART_RxCpltCallback(huart); 8006de8: 6ef8 ldr r0, [r7, #108] @ 0x6c 8006dea: f7f9 ff9b bl 8000d24 } 8006dee: bf00 nop 8006df0: 3770 adds r7, #112 @ 0x70 8006df2: 46bd mov sp, r7 8006df4: bd80 pop {r7, pc} 08006df6 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 8006df6: b580 push {r7, lr} 8006df8: b084 sub sp, #16 8006dfa: af00 add r7, sp, #0 8006dfc: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006dfe: 687b ldr r3, [r7, #4] 8006e00: 6b9b ldr r3, [r3, #56] @ 0x38 8006e02: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 8006e04: 68fb ldr r3, [r7, #12] 8006e06: 2201 movs r2, #1 8006e08: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006e0a: 68fb ldr r3, [r7, #12] 8006e0c: 6b1b ldr r3, [r3, #48] @ 0x30 8006e0e: 2b01 cmp r3, #1 8006e10: d108 bne.n 8006e24 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); 8006e12: 68fb ldr r3, [r7, #12] 8006e14: 8d9b ldrh r3, [r3, #44] @ 0x2c 8006e16: 085b lsrs r3, r3, #1 8006e18: b29b uxth r3, r3 8006e1a: 4619 mov r1, r3 8006e1c: 68f8 ldr r0, [r7, #12] 8006e1e: f7ff feed bl 8006bfc #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8006e22: e002 b.n 8006e2a HAL_UART_RxHalfCpltCallback(huart); 8006e24: 68f8 ldr r0, [r7, #12] 8006e26: f7ff fedf bl 8006be8 } 8006e2a: bf00 nop 8006e2c: 3710 adds r7, #16 8006e2e: 46bd mov sp, r7 8006e30: bd80 pop {r7, pc} 08006e32 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8006e32: b580 push {r7, lr} 8006e34: b084 sub sp, #16 8006e36: af00 add r7, sp, #0 8006e38: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 8006e3a: 2300 movs r3, #0 8006e3c: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006e3e: 687b ldr r3, [r7, #4] 8006e40: 6b9b ldr r3, [r3, #56] @ 0x38 8006e42: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8006e44: 68bb ldr r3, [r7, #8] 8006e46: 681b ldr r3, [r3, #0] 8006e48: 695b ldr r3, [r3, #20] 8006e4a: f003 0380 and.w r3, r3, #128 @ 0x80 8006e4e: 2b80 cmp r3, #128 @ 0x80 8006e50: bf0c ite eq 8006e52: 2301 moveq r3, #1 8006e54: 2300 movne r3, #0 8006e56: b2db uxtb r3, r3 8006e58: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 8006e5a: 68bb ldr r3, [r7, #8] 8006e5c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8006e60: b2db uxtb r3, r3 8006e62: 2b21 cmp r3, #33 @ 0x21 8006e64: d108 bne.n 8006e78 8006e66: 68fb ldr r3, [r7, #12] 8006e68: 2b00 cmp r3, #0 8006e6a: d005 beq.n 8006e78 { huart->TxXferCount = 0x00U; 8006e6c: 68bb ldr r3, [r7, #8] 8006e6e: 2200 movs r2, #0 8006e70: 84da strh r2, [r3, #38] @ 0x26 UART_EndTxTransfer(huart); 8006e72: 68b8 ldr r0, [r7, #8] 8006e74: f000 f8ce bl 8007014 } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8006e78: 68bb ldr r3, [r7, #8] 8006e7a: 681b ldr r3, [r3, #0] 8006e7c: 695b ldr r3, [r3, #20] 8006e7e: f003 0340 and.w r3, r3, #64 @ 0x40 8006e82: 2b40 cmp r3, #64 @ 0x40 8006e84: bf0c ite eq 8006e86: 2301 moveq r3, #1 8006e88: 2300 movne r3, #0 8006e8a: b2db uxtb r3, r3 8006e8c: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8006e8e: 68bb ldr r3, [r7, #8] 8006e90: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8006e94: b2db uxtb r3, r3 8006e96: 2b22 cmp r3, #34 @ 0x22 8006e98: d108 bne.n 8006eac 8006e9a: 68fb ldr r3, [r7, #12] 8006e9c: 2b00 cmp r3, #0 8006e9e: d005 beq.n 8006eac { huart->RxXferCount = 0x00U; 8006ea0: 68bb ldr r3, [r7, #8] 8006ea2: 2200 movs r2, #0 8006ea4: 85da strh r2, [r3, #46] @ 0x2e UART_EndRxTransfer(huart); 8006ea6: 68b8 ldr r0, [r7, #8] 8006ea8: f000 f8dc bl 8007064 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8006eac: 68bb ldr r3, [r7, #8] 8006eae: 6c5b ldr r3, [r3, #68] @ 0x44 8006eb0: f043 0210 orr.w r2, r3, #16 8006eb4: 68bb ldr r3, [r7, #8] 8006eb6: 645a str r2, [r3, #68] @ 0x44 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006eb8: 68b8 ldr r0, [r7, #8] 8006eba: f7f9 ff8f bl 8000ddc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006ebe: bf00 nop 8006ec0: 3710 adds r7, #16 8006ec2: 46bd mov sp, r7 8006ec4: bd80 pop {r7, pc} ... 08006ec8 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8006ec8: b580 push {r7, lr} 8006eca: b098 sub sp, #96 @ 0x60 8006ecc: af00 add r7, sp, #0 8006ece: 60f8 str r0, [r7, #12] 8006ed0: 60b9 str r1, [r7, #8] 8006ed2: 4613 mov r3, r2 8006ed4: 80fb strh r3, [r7, #6] uint32_t *tmp; huart->pRxBuffPtr = pData; 8006ed6: 68ba ldr r2, [r7, #8] 8006ed8: 68fb ldr r3, [r7, #12] 8006eda: 629a str r2, [r3, #40] @ 0x28 huart->RxXferSize = Size; 8006edc: 68fb ldr r3, [r7, #12] 8006ede: 88fa ldrh r2, [r7, #6] 8006ee0: 859a strh r2, [r3, #44] @ 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 8006ee2: 68fb ldr r3, [r7, #12] 8006ee4: 2200 movs r2, #0 8006ee6: 645a str r2, [r3, #68] @ 0x44 huart->RxState = HAL_UART_STATE_BUSY_RX; 8006ee8: 68fb ldr r3, [r7, #12] 8006eea: 2222 movs r2, #34 @ 0x22 8006eec: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 8006ef0: 68fb ldr r3, [r7, #12] 8006ef2: 6bdb ldr r3, [r3, #60] @ 0x3c 8006ef4: 4a44 ldr r2, [pc, #272] @ (8007008 ) 8006ef6: 63da str r2, [r3, #60] @ 0x3c /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 8006ef8: 68fb ldr r3, [r7, #12] 8006efa: 6bdb ldr r3, [r3, #60] @ 0x3c 8006efc: 4a43 ldr r2, [pc, #268] @ (800700c ) 8006efe: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 8006f00: 68fb ldr r3, [r7, #12] 8006f02: 6bdb ldr r3, [r3, #60] @ 0x3c 8006f04: 4a42 ldr r2, [pc, #264] @ (8007010 ) 8006f06: 64da str r2, [r3, #76] @ 0x4c /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 8006f08: 68fb ldr r3, [r7, #12] 8006f0a: 6bdb ldr r3, [r3, #60] @ 0x3c 8006f0c: 2200 movs r2, #0 8006f0e: 651a str r2, [r3, #80] @ 0x50 /* Enable the DMA stream */ tmp = (uint32_t *)&pData; 8006f10: f107 0308 add.w r3, r7, #8 8006f14: 65fb str r3, [r7, #92] @ 0x5c if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK) 8006f16: 68fb ldr r3, [r7, #12] 8006f18: 6bd8 ldr r0, [r3, #60] @ 0x3c 8006f1a: 68fb ldr r3, [r7, #12] 8006f1c: 681b ldr r3, [r3, #0] 8006f1e: 3304 adds r3, #4 8006f20: 4619 mov r1, r3 8006f22: 6dfb ldr r3, [r7, #92] @ 0x5c 8006f24: 681a ldr r2, [r3, #0] 8006f26: 88fb ldrh r3, [r7, #6] 8006f28: f7fb f9fe bl 8002328 8006f2c: 4603 mov r3, r0 8006f2e: 2b00 cmp r3, #0 8006f30: d008 beq.n 8006f44 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 8006f32: 68fb ldr r3, [r7, #12] 8006f34: 2210 movs r2, #16 8006f36: 645a str r2, [r3, #68] @ 0x44 /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; 8006f38: 68fb ldr r3, [r7, #12] 8006f3a: 2220 movs r2, #32 8006f3c: f883 2042 strb.w r2, [r3, #66] @ 0x42 return HAL_ERROR; 8006f40: 2301 movs r3, #1 8006f42: e05d b.n 8007000 } /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 8006f44: 2300 movs r3, #0 8006f46: 613b str r3, [r7, #16] 8006f48: 68fb ldr r3, [r7, #12] 8006f4a: 681b ldr r3, [r3, #0] 8006f4c: 681b ldr r3, [r3, #0] 8006f4e: 613b str r3, [r7, #16] 8006f50: 68fb ldr r3, [r7, #12] 8006f52: 681b ldr r3, [r3, #0] 8006f54: 685b ldr r3, [r3, #4] 8006f56: 613b str r3, [r7, #16] 8006f58: 693b ldr r3, [r7, #16] if (huart->Init.Parity != UART_PARITY_NONE) 8006f5a: 68fb ldr r3, [r7, #12] 8006f5c: 691b ldr r3, [r3, #16] 8006f5e: 2b00 cmp r3, #0 8006f60: d019 beq.n 8006f96 { /* Enable the UART Parity Error Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006f62: 68fb ldr r3, [r7, #12] 8006f64: 681b ldr r3, [r3, #0] 8006f66: 330c adds r3, #12 8006f68: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006f6a: 6c3b ldr r3, [r7, #64] @ 0x40 8006f6c: e853 3f00 ldrex r3, [r3] 8006f70: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006f72: 6bfb ldr r3, [r7, #60] @ 0x3c 8006f74: f443 7380 orr.w r3, r3, #256 @ 0x100 8006f78: 65bb str r3, [r7, #88] @ 0x58 8006f7a: 68fb ldr r3, [r7, #12] 8006f7c: 681b ldr r3, [r3, #0] 8006f7e: 330c adds r3, #12 8006f80: 6dba ldr r2, [r7, #88] @ 0x58 8006f82: 64fa str r2, [r7, #76] @ 0x4c 8006f84: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006f86: 6cb9 ldr r1, [r7, #72] @ 0x48 8006f88: 6cfa ldr r2, [r7, #76] @ 0x4c 8006f8a: e841 2300 strex r3, r2, [r1] 8006f8e: 647b str r3, [r7, #68] @ 0x44 return(result); 8006f90: 6c7b ldr r3, [r7, #68] @ 0x44 8006f92: 2b00 cmp r3, #0 8006f94: d1e5 bne.n 8006f62 } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006f96: 68fb ldr r3, [r7, #12] 8006f98: 681b ldr r3, [r3, #0] 8006f9a: 3314 adds r3, #20 8006f9c: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006f9e: 6afb ldr r3, [r7, #44] @ 0x2c 8006fa0: e853 3f00 ldrex r3, [r3] 8006fa4: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006fa6: 6abb ldr r3, [r7, #40] @ 0x28 8006fa8: f043 0301 orr.w r3, r3, #1 8006fac: 657b str r3, [r7, #84] @ 0x54 8006fae: 68fb ldr r3, [r7, #12] 8006fb0: 681b ldr r3, [r3, #0] 8006fb2: 3314 adds r3, #20 8006fb4: 6d7a ldr r2, [r7, #84] @ 0x54 8006fb6: 63ba str r2, [r7, #56] @ 0x38 8006fb8: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006fba: 6b79 ldr r1, [r7, #52] @ 0x34 8006fbc: 6bba ldr r2, [r7, #56] @ 0x38 8006fbe: e841 2300 strex r3, r2, [r1] 8006fc2: 633b str r3, [r7, #48] @ 0x30 return(result); 8006fc4: 6b3b ldr r3, [r7, #48] @ 0x30 8006fc6: 2b00 cmp r3, #0 8006fc8: d1e5 bne.n 8006f96 /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8006fca: 68fb ldr r3, [r7, #12] 8006fcc: 681b ldr r3, [r3, #0] 8006fce: 3314 adds r3, #20 8006fd0: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006fd2: 69bb ldr r3, [r7, #24] 8006fd4: e853 3f00 ldrex r3, [r3] 8006fd8: 617b str r3, [r7, #20] return(result); 8006fda: 697b ldr r3, [r7, #20] 8006fdc: f043 0340 orr.w r3, r3, #64 @ 0x40 8006fe0: 653b str r3, [r7, #80] @ 0x50 8006fe2: 68fb ldr r3, [r7, #12] 8006fe4: 681b ldr r3, [r3, #0] 8006fe6: 3314 adds r3, #20 8006fe8: 6d3a ldr r2, [r7, #80] @ 0x50 8006fea: 627a str r2, [r7, #36] @ 0x24 8006fec: 623b str r3, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006fee: 6a39 ldr r1, [r7, #32] 8006ff0: 6a7a ldr r2, [r7, #36] @ 0x24 8006ff2: e841 2300 strex r3, r2, [r1] 8006ff6: 61fb str r3, [r7, #28] return(result); 8006ff8: 69fb ldr r3, [r7, #28] 8006ffa: 2b00 cmp r3, #0 8006ffc: d1e5 bne.n 8006fca return HAL_OK; 8006ffe: 2300 movs r3, #0 } 8007000: 4618 mov r0, r3 8007002: 3760 adds r7, #96 @ 0x60 8007004: 46bd mov sp, r7 8007006: bd80 pop {r7, pc} 8007008: 08006ccb .word 0x08006ccb 800700c: 08006df7 .word 0x08006df7 8007010: 08006e33 .word 0x08006e33 08007014 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 8007014: b480 push {r7} 8007016: b089 sub sp, #36 @ 0x24 8007018: af00 add r7, sp, #0 800701a: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 800701c: 687b ldr r3, [r7, #4] 800701e: 681b ldr r3, [r3, #0] 8007020: 330c adds r3, #12 8007022: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007024: 68fb ldr r3, [r7, #12] 8007026: e853 3f00 ldrex r3, [r3] 800702a: 60bb str r3, [r7, #8] return(result); 800702c: 68bb ldr r3, [r7, #8] 800702e: f023 03c0 bic.w r3, r3, #192 @ 0xc0 8007032: 61fb str r3, [r7, #28] 8007034: 687b ldr r3, [r7, #4] 8007036: 681b ldr r3, [r3, #0] 8007038: 330c adds r3, #12 800703a: 69fa ldr r2, [r7, #28] 800703c: 61ba str r2, [r7, #24] 800703e: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007040: 6979 ldr r1, [r7, #20] 8007042: 69ba ldr r2, [r7, #24] 8007044: e841 2300 strex r3, r2, [r1] 8007048: 613b str r3, [r7, #16] return(result); 800704a: 693b ldr r3, [r7, #16] 800704c: 2b00 cmp r3, #0 800704e: d1e5 bne.n 800701c /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8007050: 687b ldr r3, [r7, #4] 8007052: 2220 movs r2, #32 8007054: f883 2041 strb.w r2, [r3, #65] @ 0x41 } 8007058: bf00 nop 800705a: 3724 adds r7, #36 @ 0x24 800705c: 46bd mov sp, r7 800705e: f85d 7b04 ldr.w r7, [sp], #4 8007062: 4770 bx lr 08007064 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8007064: b480 push {r7} 8007066: b095 sub sp, #84 @ 0x54 8007068: af00 add r7, sp, #0 800706a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 800706c: 687b ldr r3, [r7, #4] 800706e: 681b ldr r3, [r3, #0] 8007070: 330c adds r3, #12 8007072: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007074: 6b7b ldr r3, [r7, #52] @ 0x34 8007076: e853 3f00 ldrex r3, [r3] 800707a: 633b str r3, [r7, #48] @ 0x30 return(result); 800707c: 6b3b ldr r3, [r7, #48] @ 0x30 800707e: f423 7390 bic.w r3, r3, #288 @ 0x120 8007082: 64fb str r3, [r7, #76] @ 0x4c 8007084: 687b ldr r3, [r7, #4] 8007086: 681b ldr r3, [r3, #0] 8007088: 330c adds r3, #12 800708a: 6cfa ldr r2, [r7, #76] @ 0x4c 800708c: 643a str r2, [r7, #64] @ 0x40 800708e: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007090: 6bf9 ldr r1, [r7, #60] @ 0x3c 8007092: 6c3a ldr r2, [r7, #64] @ 0x40 8007094: e841 2300 strex r3, r2, [r1] 8007098: 63bb str r3, [r7, #56] @ 0x38 return(result); 800709a: 6bbb ldr r3, [r7, #56] @ 0x38 800709c: 2b00 cmp r3, #0 800709e: d1e5 bne.n 800706c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80070a0: 687b ldr r3, [r7, #4] 80070a2: 681b ldr r3, [r3, #0] 80070a4: 3314 adds r3, #20 80070a6: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80070a8: 6a3b ldr r3, [r7, #32] 80070aa: e853 3f00 ldrex r3, [r3] 80070ae: 61fb str r3, [r7, #28] return(result); 80070b0: 69fb ldr r3, [r7, #28] 80070b2: f023 0301 bic.w r3, r3, #1 80070b6: 64bb str r3, [r7, #72] @ 0x48 80070b8: 687b ldr r3, [r7, #4] 80070ba: 681b ldr r3, [r3, #0] 80070bc: 3314 adds r3, #20 80070be: 6cba ldr r2, [r7, #72] @ 0x48 80070c0: 62fa str r2, [r7, #44] @ 0x2c 80070c2: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80070c4: 6ab9 ldr r1, [r7, #40] @ 0x28 80070c6: 6afa ldr r2, [r7, #44] @ 0x2c 80070c8: e841 2300 strex r3, r2, [r1] 80070cc: 627b str r3, [r7, #36] @ 0x24 return(result); 80070ce: 6a7b ldr r3, [r7, #36] @ 0x24 80070d0: 2b00 cmp r3, #0 80070d2: d1e5 bne.n 80070a0 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80070d4: 687b ldr r3, [r7, #4] 80070d6: 6b1b ldr r3, [r3, #48] @ 0x30 80070d8: 2b01 cmp r3, #1 80070da: d119 bne.n 8007110 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80070dc: 687b ldr r3, [r7, #4] 80070de: 681b ldr r3, [r3, #0] 80070e0: 330c adds r3, #12 80070e2: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80070e4: 68fb ldr r3, [r7, #12] 80070e6: e853 3f00 ldrex r3, [r3] 80070ea: 60bb str r3, [r7, #8] return(result); 80070ec: 68bb ldr r3, [r7, #8] 80070ee: f023 0310 bic.w r3, r3, #16 80070f2: 647b str r3, [r7, #68] @ 0x44 80070f4: 687b ldr r3, [r7, #4] 80070f6: 681b ldr r3, [r3, #0] 80070f8: 330c adds r3, #12 80070fa: 6c7a ldr r2, [r7, #68] @ 0x44 80070fc: 61ba str r2, [r7, #24] 80070fe: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8007100: 6979 ldr r1, [r7, #20] 8007102: 69ba ldr r2, [r7, #24] 8007104: e841 2300 strex r3, r2, [r1] 8007108: 613b str r3, [r7, #16] return(result); 800710a: 693b ldr r3, [r7, #16] 800710c: 2b00 cmp r3, #0 800710e: d1e5 bne.n 80070dc } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8007110: 687b ldr r3, [r7, #4] 8007112: 2220 movs r2, #32 8007114: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8007118: 687b ldr r3, [r7, #4] 800711a: 2200 movs r2, #0 800711c: 631a str r2, [r3, #48] @ 0x30 } 800711e: bf00 nop 8007120: 3754 adds r7, #84 @ 0x54 8007122: 46bd mov sp, r7 8007124: f85d 7b04 ldr.w r7, [sp], #4 8007128: 4770 bx lr 0800712a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 800712a: b580 push {r7, lr} 800712c: b084 sub sp, #16 800712e: af00 add r7, sp, #0 8007130: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8007132: 687b ldr r3, [r7, #4] 8007134: 6b9b ldr r3, [r3, #56] @ 0x38 8007136: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8007138: 68fb ldr r3, [r7, #12] 800713a: 2200 movs r2, #0 800713c: 85da strh r2, [r3, #46] @ 0x2e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800713e: 68f8 ldr r0, [r7, #12] 8007140: f7f9 fe4c bl 8000ddc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8007144: bf00 nop 8007146: 3710 adds r7, #16 8007148: 46bd mov sp, r7 800714a: bd80 pop {r7, pc} 0800714c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 800714c: b480 push {r7} 800714e: b085 sub sp, #20 8007150: af00 add r7, sp, #0 8007152: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8007154: 687b ldr r3, [r7, #4] 8007156: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800715a: b2db uxtb r3, r3 800715c: 2b21 cmp r3, #33 @ 0x21 800715e: d13e bne.n 80071de { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8007160: 687b ldr r3, [r7, #4] 8007162: 689b ldr r3, [r3, #8] 8007164: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8007168: d114 bne.n 8007194 800716a: 687b ldr r3, [r7, #4] 800716c: 691b ldr r3, [r3, #16] 800716e: 2b00 cmp r3, #0 8007170: d110 bne.n 8007194 { tmp = (const uint16_t *) huart->pTxBuffPtr; 8007172: 687b ldr r3, [r7, #4] 8007174: 6a1b ldr r3, [r3, #32] 8007176: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8007178: 68fb ldr r3, [r7, #12] 800717a: 881b ldrh r3, [r3, #0] 800717c: 461a mov r2, r3 800717e: 687b ldr r3, [r7, #4] 8007180: 681b ldr r3, [r3, #0] 8007182: f3c2 0208 ubfx r2, r2, #0, #9 8007186: 605a str r2, [r3, #4] huart->pTxBuffPtr += 2U; 8007188: 687b ldr r3, [r7, #4] 800718a: 6a1b ldr r3, [r3, #32] 800718c: 1c9a adds r2, r3, #2 800718e: 687b ldr r3, [r7, #4] 8007190: 621a str r2, [r3, #32] 8007192: e008 b.n 80071a6 } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8007194: 687b ldr r3, [r7, #4] 8007196: 6a1b ldr r3, [r3, #32] 8007198: 1c59 adds r1, r3, #1 800719a: 687a ldr r2, [r7, #4] 800719c: 6211 str r1, [r2, #32] 800719e: 781a ldrb r2, [r3, #0] 80071a0: 687b ldr r3, [r7, #4] 80071a2: 681b ldr r3, [r3, #0] 80071a4: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 80071a6: 687b ldr r3, [r7, #4] 80071a8: 8cdb ldrh r3, [r3, #38] @ 0x26 80071aa: b29b uxth r3, r3 80071ac: 3b01 subs r3, #1 80071ae: b29b uxth r3, r3 80071b0: 687a ldr r2, [r7, #4] 80071b2: 4619 mov r1, r3 80071b4: 84d1 strh r1, [r2, #38] @ 0x26 80071b6: 2b00 cmp r3, #0 80071b8: d10f bne.n 80071da { /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 80071ba: 687b ldr r3, [r7, #4] 80071bc: 681b ldr r3, [r3, #0] 80071be: 68da ldr r2, [r3, #12] 80071c0: 687b ldr r3, [r7, #4] 80071c2: 681b ldr r3, [r3, #0] 80071c4: f022 0280 bic.w r2, r2, #128 @ 0x80 80071c8: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 80071ca: 687b ldr r3, [r7, #4] 80071cc: 681b ldr r3, [r3, #0] 80071ce: 68da ldr r2, [r3, #12] 80071d0: 687b ldr r3, [r7, #4] 80071d2: 681b ldr r3, [r3, #0] 80071d4: f042 0240 orr.w r2, r2, #64 @ 0x40 80071d8: 60da str r2, [r3, #12] } return HAL_OK; 80071da: 2300 movs r3, #0 80071dc: e000 b.n 80071e0 } else { return HAL_BUSY; 80071de: 2302 movs r3, #2 } } 80071e0: 4618 mov r0, r3 80071e2: 3714 adds r7, #20 80071e4: 46bd mov sp, r7 80071e6: f85d 7b04 ldr.w r7, [sp], #4 80071ea: 4770 bx lr 080071ec : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80071ec: b580 push {r7, lr} 80071ee: b082 sub sp, #8 80071f0: af00 add r7, sp, #0 80071f2: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 80071f4: 687b ldr r3, [r7, #4] 80071f6: 681b ldr r3, [r3, #0] 80071f8: 68da ldr r2, [r3, #12] 80071fa: 687b ldr r3, [r7, #4] 80071fc: 681b ldr r3, [r3, #0] 80071fe: f022 0240 bic.w r2, r2, #64 @ 0x40 8007202: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8007204: 687b ldr r3, [r7, #4] 8007206: 2220 movs r2, #32 8007208: f883 2041 strb.w r2, [r3, #65] @ 0x41 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 800720c: 6878 ldr r0, [r7, #4] 800720e: f7ff fcd7 bl 8006bc0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8007212: 2300 movs r3, #0 } 8007214: 4618 mov r0, r3 8007216: 3708 adds r7, #8 8007218: 46bd mov sp, r7 800721a: bd80 pop {r7, pc} 0800721c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 800721c: b580 push {r7, lr} 800721e: b08c sub sp, #48 @ 0x30 8007220: af00 add r7, sp, #0 8007222: 6078 str r0, [r7, #4] uint8_t *pdata8bits = NULL; 8007224: 2300 movs r3, #0 8007226: 62fb str r3, [r7, #44] @ 0x2c uint16_t *pdata16bits = NULL; 8007228: 2300 movs r3, #0 800722a: 62bb str r3, [r7, #40] @ 0x28 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800722c: 687b ldr r3, [r7, #4] 800722e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8007232: b2db uxtb r3, r3 8007234: 2b22 cmp r3, #34 @ 0x22 8007236: f040 80aa bne.w 800738e { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800723a: 687b ldr r3, [r7, #4] 800723c: 689b ldr r3, [r3, #8] 800723e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8007242: d115 bne.n 8007270 8007244: 687b ldr r3, [r7, #4] 8007246: 691b ldr r3, [r3, #16] 8007248: 2b00 cmp r3, #0 800724a: d111 bne.n 8007270 { /* Unused pdata8bits */ UNUSED(pdata8bits); pdata16bits = (uint16_t *) huart->pRxBuffPtr; 800724c: 687b ldr r3, [r7, #4] 800724e: 6a9b ldr r3, [r3, #40] @ 0x28 8007250: 62bb str r3, [r7, #40] @ 0x28 *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8007252: 687b ldr r3, [r7, #4] 8007254: 681b ldr r3, [r3, #0] 8007256: 685b ldr r3, [r3, #4] 8007258: b29b uxth r3, r3 800725a: f3c3 0308 ubfx r3, r3, #0, #9 800725e: b29a uxth r2, r3 8007260: 6abb ldr r3, [r7, #40] @ 0x28 8007262: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8007264: 687b ldr r3, [r7, #4] 8007266: 6a9b ldr r3, [r3, #40] @ 0x28 8007268: 1c9a adds r2, r3, #2 800726a: 687b ldr r3, [r7, #4] 800726c: 629a str r2, [r3, #40] @ 0x28 800726e: e024 b.n 80072ba } else { pdata8bits = (uint8_t *) huart->pRxBuffPtr; 8007270: 687b ldr r3, [r7, #4] 8007272: 6a9b ldr r3, [r3, #40] @ 0x28 8007274: 62fb str r3, [r7, #44] @ 0x2c /* Unused pdata16bits */ UNUSED(pdata16bits); if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) 8007276: 687b ldr r3, [r7, #4] 8007278: 689b ldr r3, [r3, #8] 800727a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800727e: d007 beq.n 8007290 8007280: 687b ldr r3, [r7, #4] 8007282: 689b ldr r3, [r3, #8] 8007284: 2b00 cmp r3, #0 8007286: d10a bne.n 800729e 8007288: 687b ldr r3, [r7, #4] 800728a: 691b ldr r3, [r3, #16] 800728c: 2b00 cmp r3, #0 800728e: d106 bne.n 800729e { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8007290: 687b ldr r3, [r7, #4] 8007292: 681b ldr r3, [r3, #0] 8007294: 685b ldr r3, [r3, #4] 8007296: b2da uxtb r2, r3 8007298: 6afb ldr r3, [r7, #44] @ 0x2c 800729a: 701a strb r2, [r3, #0] 800729c: e008 b.n 80072b0 } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 800729e: 687b ldr r3, [r7, #4] 80072a0: 681b ldr r3, [r3, #0] 80072a2: 685b ldr r3, [r3, #4] 80072a4: b2db uxtb r3, r3 80072a6: f003 037f and.w r3, r3, #127 @ 0x7f 80072aa: b2da uxtb r2, r3 80072ac: 6afb ldr r3, [r7, #44] @ 0x2c 80072ae: 701a strb r2, [r3, #0] } huart->pRxBuffPtr += 1U; 80072b0: 687b ldr r3, [r7, #4] 80072b2: 6a9b ldr r3, [r3, #40] @ 0x28 80072b4: 1c5a adds r2, r3, #1 80072b6: 687b ldr r3, [r7, #4] 80072b8: 629a str r2, [r3, #40] @ 0x28 } if (--huart->RxXferCount == 0U) 80072ba: 687b ldr r3, [r7, #4] 80072bc: 8ddb ldrh r3, [r3, #46] @ 0x2e 80072be: b29b uxth r3, r3 80072c0: 3b01 subs r3, #1 80072c2: b29b uxth r3, r3 80072c4: 687a ldr r2, [r7, #4] 80072c6: 4619 mov r1, r3 80072c8: 85d1 strh r1, [r2, #46] @ 0x2e 80072ca: 2b00 cmp r3, #0 80072cc: d15d bne.n 800738a { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 80072ce: 687b ldr r3, [r7, #4] 80072d0: 681b ldr r3, [r3, #0] 80072d2: 68da ldr r2, [r3, #12] 80072d4: 687b ldr r3, [r7, #4] 80072d6: 681b ldr r3, [r3, #0] 80072d8: f022 0220 bic.w r2, r2, #32 80072dc: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 80072de: 687b ldr r3, [r7, #4] 80072e0: 681b ldr r3, [r3, #0] 80072e2: 68da ldr r2, [r3, #12] 80072e4: 687b ldr r3, [r7, #4] 80072e6: 681b ldr r3, [r3, #0] 80072e8: f422 7280 bic.w r2, r2, #256 @ 0x100 80072ec: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 80072ee: 687b ldr r3, [r7, #4] 80072f0: 681b ldr r3, [r3, #0] 80072f2: 695a ldr r2, [r3, #20] 80072f4: 687b ldr r3, [r7, #4] 80072f6: 681b ldr r3, [r3, #0] 80072f8: f022 0201 bic.w r2, r2, #1 80072fc: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80072fe: 687b ldr r3, [r7, #4] 8007300: 2220 movs r2, #32 8007302: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8007306: 687b ldr r3, [r7, #4] 8007308: 2200 movs r2, #0 800730a: 635a str r2, [r3, #52] @ 0x34 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800730c: 687b ldr r3, [r7, #4] 800730e: 6b1b ldr r3, [r3, #48] @ 0x30 8007310: 2b01 cmp r3, #1 8007312: d135 bne.n 8007380 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8007314: 687b ldr r3, [r7, #4] 8007316: 2200 movs r2, #0 8007318: 631a str r2, [r3, #48] @ 0x30 /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800731a: 687b ldr r3, [r7, #4] 800731c: 681b ldr r3, [r3, #0] 800731e: 330c adds r3, #12 8007320: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8007322: 697b ldr r3, [r7, #20] 8007324: e853 3f00 ldrex r3, [r3] 8007328: 613b str r3, [r7, #16] return(result); 800732a: 693b ldr r3, [r7, #16] 800732c: f023 0310 bic.w r3, r3, #16 8007330: 627b str r3, [r7, #36] @ 0x24 8007332: 687b ldr r3, [r7, #4] 8007334: 681b ldr r3, [r3, #0] 8007336: 330c adds r3, #12 8007338: 6a7a ldr r2, [r7, #36] @ 0x24 800733a: 623a str r2, [r7, #32] 800733c: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800733e: 69f9 ldr r1, [r7, #28] 8007340: 6a3a ldr r2, [r7, #32] 8007342: e841 2300 strex r3, r2, [r1] 8007346: 61bb str r3, [r7, #24] return(result); 8007348: 69bb ldr r3, [r7, #24] 800734a: 2b00 cmp r3, #0 800734c: d1e5 bne.n 800731a /* Check if IDLE flag is set */ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 800734e: 687b ldr r3, [r7, #4] 8007350: 681b ldr r3, [r3, #0] 8007352: 681b ldr r3, [r3, #0] 8007354: f003 0310 and.w r3, r3, #16 8007358: 2b10 cmp r3, #16 800735a: d10a bne.n 8007372 { /* Clear IDLE flag in ISR */ __HAL_UART_CLEAR_IDLEFLAG(huart); 800735c: 2300 movs r3, #0 800735e: 60fb str r3, [r7, #12] 8007360: 687b ldr r3, [r7, #4] 8007362: 681b ldr r3, [r3, #0] 8007364: 681b ldr r3, [r3, #0] 8007366: 60fb str r3, [r7, #12] 8007368: 687b ldr r3, [r7, #4] 800736a: 681b ldr r3, [r3, #0] 800736c: 685b ldr r3, [r3, #4] 800736e: 60fb str r3, [r7, #12] 8007370: 68fb ldr r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8007372: 687b ldr r3, [r7, #4] 8007374: 8d9b ldrh r3, [r3, #44] @ 0x2c 8007376: 4619 mov r1, r3 8007378: 6878 ldr r0, [r7, #4] 800737a: f7ff fc3f bl 8006bfc 800737e: e002 b.n 8007386 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8007380: 6878 ldr r0, [r7, #4] 8007382: f7f9 fccf bl 8000d24 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return HAL_OK; 8007386: 2300 movs r3, #0 8007388: e002 b.n 8007390 } return HAL_OK; 800738a: 2300 movs r3, #0 800738c: e000 b.n 8007390 } else { return HAL_BUSY; 800738e: 2302 movs r3, #2 } } 8007390: 4618 mov r0, r3 8007392: 3730 adds r7, #48 @ 0x30 8007394: 46bd mov sp, r7 8007396: bd80 pop {r7, pc} 08007398 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8007398: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800739c: b0c0 sub sp, #256 @ 0x100 800739e: af00 add r7, sp, #0 80073a0: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4 assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 80073a4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80073a8: 681b ldr r3, [r3, #0] 80073aa: 691b ldr r3, [r3, #16] 80073ac: f423 5040 bic.w r0, r3, #12288 @ 0x3000 80073b0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80073b4: 68d9 ldr r1, [r3, #12] 80073b6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80073ba: 681a ldr r2, [r3, #0] 80073bc: ea40 0301 orr.w r3, r0, r1 80073c0: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 80073c2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80073c6: 689a ldr r2, [r3, #8] 80073c8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80073cc: 691b ldr r3, [r3, #16] 80073ce: 431a orrs r2, r3 80073d0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80073d4: 695b ldr r3, [r3, #20] 80073d6: 431a orrs r2, r3 80073d8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80073dc: 69db ldr r3, [r3, #28] 80073de: 4313 orrs r3, r2 80073e0: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 MODIFY_REG(huart->Instance->CR1, 80073e4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80073e8: 681b ldr r3, [r3, #0] 80073ea: 68db ldr r3, [r3, #12] 80073ec: f423 4116 bic.w r1, r3, #38400 @ 0x9600 80073f0: f021 010c bic.w r1, r1, #12 80073f4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80073f8: 681a ldr r2, [r3, #0] 80073fa: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 80073fe: 430b orrs r3, r1 8007400: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8007402: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007406: 681b ldr r3, [r3, #0] 8007408: 695b ldr r3, [r3, #20] 800740a: f423 7040 bic.w r0, r3, #768 @ 0x300 800740e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007412: 6999 ldr r1, [r3, #24] 8007414: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007418: 681a ldr r2, [r3, #0] 800741a: ea40 0301 orr.w r3, r0, r1 800741e: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 8007420: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007424: 681a ldr r2, [r3, #0] 8007426: 4b8f ldr r3, [pc, #572] @ (8007664 ) 8007428: 429a cmp r2, r3 800742a: d005 beq.n 8007438 800742c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007430: 681a ldr r2, [r3, #0] 8007432: 4b8d ldr r3, [pc, #564] @ (8007668 ) 8007434: 429a cmp r2, r3 8007436: d104 bne.n 8007442 { pclk = HAL_RCC_GetPCLK2Freq(); 8007438: f7fd f960 bl 80046fc 800743c: f8c7 00fc str.w r0, [r7, #252] @ 0xfc 8007440: e003 b.n 800744a pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); 8007442: f7fd f947 bl 80046d4 8007446: f8c7 00fc str.w r0, [r7, #252] @ 0xfc } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800744a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800744e: 69db ldr r3, [r3, #28] 8007450: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8007454: f040 810c bne.w 8007670 { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8007458: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 800745c: 2200 movs r2, #0 800745e: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 8007462: f8c7 20ec str.w r2, [r7, #236] @ 0xec 8007466: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8 800746a: 4622 mov r2, r4 800746c: 462b mov r3, r5 800746e: 1891 adds r1, r2, r2 8007470: 65b9 str r1, [r7, #88] @ 0x58 8007472: 415b adcs r3, r3 8007474: 65fb str r3, [r7, #92] @ 0x5c 8007476: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 800747a: 4621 mov r1, r4 800747c: eb12 0801 adds.w r8, r2, r1 8007480: 4629 mov r1, r5 8007482: eb43 0901 adc.w r9, r3, r1 8007486: f04f 0200 mov.w r2, #0 800748a: f04f 0300 mov.w r3, #0 800748e: ea4f 03c9 mov.w r3, r9, lsl #3 8007492: ea43 7358 orr.w r3, r3, r8, lsr #29 8007496: ea4f 02c8 mov.w r2, r8, lsl #3 800749a: 4690 mov r8, r2 800749c: 4699 mov r9, r3 800749e: 4623 mov r3, r4 80074a0: eb18 0303 adds.w r3, r8, r3 80074a4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 80074a8: 462b mov r3, r5 80074aa: eb49 0303 adc.w r3, r9, r3 80074ae: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 80074b2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80074b6: 685b ldr r3, [r3, #4] 80074b8: 2200 movs r2, #0 80074ba: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 80074be: f8c7 20dc str.w r2, [r7, #220] @ 0xdc 80074c2: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 80074c6: 460b mov r3, r1 80074c8: 18db adds r3, r3, r3 80074ca: 653b str r3, [r7, #80] @ 0x50 80074cc: 4613 mov r3, r2 80074ce: eb42 0303 adc.w r3, r2, r3 80074d2: 657b str r3, [r7, #84] @ 0x54 80074d4: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50 80074d8: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0 80074dc: f7f8 fe92 bl 8000204 <__aeabi_uldivmod> 80074e0: 4602 mov r2, r0 80074e2: 460b mov r3, r1 80074e4: 4b61 ldr r3, [pc, #388] @ (800766c ) 80074e6: fba3 2302 umull r2, r3, r3, r2 80074ea: 095b lsrs r3, r3, #5 80074ec: 011c lsls r4, r3, #4 80074ee: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 80074f2: 2200 movs r2, #0 80074f4: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 80074f8: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4 80074fc: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0 8007500: 4642 mov r2, r8 8007502: 464b mov r3, r9 8007504: 1891 adds r1, r2, r2 8007506: 64b9 str r1, [r7, #72] @ 0x48 8007508: 415b adcs r3, r3 800750a: 64fb str r3, [r7, #76] @ 0x4c 800750c: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8007510: 4641 mov r1, r8 8007512: eb12 0a01 adds.w sl, r2, r1 8007516: 4649 mov r1, r9 8007518: eb43 0b01 adc.w fp, r3, r1 800751c: f04f 0200 mov.w r2, #0 8007520: f04f 0300 mov.w r3, #0 8007524: ea4f 03cb mov.w r3, fp, lsl #3 8007528: ea43 735a orr.w r3, r3, sl, lsr #29 800752c: ea4f 02ca mov.w r2, sl, lsl #3 8007530: 4692 mov sl, r2 8007532: 469b mov fp, r3 8007534: 4643 mov r3, r8 8007536: eb1a 0303 adds.w r3, sl, r3 800753a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800753e: 464b mov r3, r9 8007540: eb4b 0303 adc.w r3, fp, r3 8007544: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 8007548: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800754c: 685b ldr r3, [r3, #4] 800754e: 2200 movs r2, #0 8007550: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8007554: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4 8007558: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 800755c: 460b mov r3, r1 800755e: 18db adds r3, r3, r3 8007560: 643b str r3, [r7, #64] @ 0x40 8007562: 4613 mov r3, r2 8007564: eb42 0303 adc.w r3, r2, r3 8007568: 647b str r3, [r7, #68] @ 0x44 800756a: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40 800756e: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8 8007572: f7f8 fe47 bl 8000204 <__aeabi_uldivmod> 8007576: 4602 mov r2, r0 8007578: 460b mov r3, r1 800757a: 4611 mov r1, r2 800757c: 4b3b ldr r3, [pc, #236] @ (800766c ) 800757e: fba3 2301 umull r2, r3, r3, r1 8007582: 095b lsrs r3, r3, #5 8007584: 2264 movs r2, #100 @ 0x64 8007586: fb02 f303 mul.w r3, r2, r3 800758a: 1acb subs r3, r1, r3 800758c: 00db lsls r3, r3, #3 800758e: f103 0232 add.w r2, r3, #50 @ 0x32 8007592: 4b36 ldr r3, [pc, #216] @ (800766c ) 8007594: fba3 2302 umull r2, r3, r3, r2 8007598: 095b lsrs r3, r3, #5 800759a: 005b lsls r3, r3, #1 800759c: f403 73f8 and.w r3, r3, #496 @ 0x1f0 80075a0: 441c add r4, r3 80075a2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 80075a6: 2200 movs r2, #0 80075a8: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 80075ac: f8c7 20bc str.w r2, [r7, #188] @ 0xbc 80075b0: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8 80075b4: 4642 mov r2, r8 80075b6: 464b mov r3, r9 80075b8: 1891 adds r1, r2, r2 80075ba: 63b9 str r1, [r7, #56] @ 0x38 80075bc: 415b adcs r3, r3 80075be: 63fb str r3, [r7, #60] @ 0x3c 80075c0: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38 80075c4: 4641 mov r1, r8 80075c6: 1851 adds r1, r2, r1 80075c8: 6339 str r1, [r7, #48] @ 0x30 80075ca: 4649 mov r1, r9 80075cc: 414b adcs r3, r1 80075ce: 637b str r3, [r7, #52] @ 0x34 80075d0: f04f 0200 mov.w r2, #0 80075d4: f04f 0300 mov.w r3, #0 80075d8: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30 80075dc: 4659 mov r1, fp 80075de: 00cb lsls r3, r1, #3 80075e0: 4651 mov r1, sl 80075e2: ea43 7351 orr.w r3, r3, r1, lsr #29 80075e6: 4651 mov r1, sl 80075e8: 00ca lsls r2, r1, #3 80075ea: 4610 mov r0, r2 80075ec: 4619 mov r1, r3 80075ee: 4603 mov r3, r0 80075f0: 4642 mov r2, r8 80075f2: 189b adds r3, r3, r2 80075f4: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 80075f8: 464b mov r3, r9 80075fa: 460a mov r2, r1 80075fc: eb42 0303 adc.w r3, r2, r3 8007600: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8007604: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007608: 685b ldr r3, [r3, #4] 800760a: 2200 movs r2, #0 800760c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 8007610: f8c7 20ac str.w r2, [r7, #172] @ 0xac 8007614: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 8007618: 460b mov r3, r1 800761a: 18db adds r3, r3, r3 800761c: 62bb str r3, [r7, #40] @ 0x28 800761e: 4613 mov r3, r2 8007620: eb42 0303 adc.w r3, r2, r3 8007624: 62fb str r3, [r7, #44] @ 0x2c 8007626: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 800762a: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0 800762e: f7f8 fde9 bl 8000204 <__aeabi_uldivmod> 8007632: 4602 mov r2, r0 8007634: 460b mov r3, r1 8007636: 4b0d ldr r3, [pc, #52] @ (800766c ) 8007638: fba3 1302 umull r1, r3, r3, r2 800763c: 095b lsrs r3, r3, #5 800763e: 2164 movs r1, #100 @ 0x64 8007640: fb01 f303 mul.w r3, r1, r3 8007644: 1ad3 subs r3, r2, r3 8007646: 00db lsls r3, r3, #3 8007648: 3332 adds r3, #50 @ 0x32 800764a: 4a08 ldr r2, [pc, #32] @ (800766c ) 800764c: fba2 2303 umull r2, r3, r2, r3 8007650: 095b lsrs r3, r3, #5 8007652: f003 0207 and.w r2, r3, #7 8007656: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800765a: 681b ldr r3, [r3, #0] 800765c: 4422 add r2, r4 800765e: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } 8007660: e106 b.n 8007870 8007662: bf00 nop 8007664: 40011000 .word 0x40011000 8007668: 40011400 .word 0x40011400 800766c: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8007670: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8007674: 2200 movs r2, #0 8007676: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800767a: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4 800767e: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0 8007682: 4642 mov r2, r8 8007684: 464b mov r3, r9 8007686: 1891 adds r1, r2, r2 8007688: 6239 str r1, [r7, #32] 800768a: 415b adcs r3, r3 800768c: 627b str r3, [r7, #36] @ 0x24 800768e: e9d7 2308 ldrd r2, r3, [r7, #32] 8007692: 4641 mov r1, r8 8007694: 1854 adds r4, r2, r1 8007696: 4649 mov r1, r9 8007698: eb43 0501 adc.w r5, r3, r1 800769c: f04f 0200 mov.w r2, #0 80076a0: f04f 0300 mov.w r3, #0 80076a4: 00eb lsls r3, r5, #3 80076a6: ea43 7354 orr.w r3, r3, r4, lsr #29 80076aa: 00e2 lsls r2, r4, #3 80076ac: 4614 mov r4, r2 80076ae: 461d mov r5, r3 80076b0: 4643 mov r3, r8 80076b2: 18e3 adds r3, r4, r3 80076b4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 80076b8: 464b mov r3, r9 80076ba: eb45 0303 adc.w r3, r5, r3 80076be: f8c7 309c str.w r3, [r7, #156] @ 0x9c 80076c2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80076c6: 685b ldr r3, [r3, #4] 80076c8: 2200 movs r2, #0 80076ca: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80076ce: f8c7 2094 str.w r2, [r7, #148] @ 0x94 80076d2: f04f 0200 mov.w r2, #0 80076d6: f04f 0300 mov.w r3, #0 80076da: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 80076de: 4629 mov r1, r5 80076e0: 008b lsls r3, r1, #2 80076e2: 4621 mov r1, r4 80076e4: ea43 7391 orr.w r3, r3, r1, lsr #30 80076e8: 4621 mov r1, r4 80076ea: 008a lsls r2, r1, #2 80076ec: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98 80076f0: f7f8 fd88 bl 8000204 <__aeabi_uldivmod> 80076f4: 4602 mov r2, r0 80076f6: 460b mov r3, r1 80076f8: 4b60 ldr r3, [pc, #384] @ (800787c ) 80076fa: fba3 2302 umull r2, r3, r3, r2 80076fe: 095b lsrs r3, r3, #5 8007700: 011c lsls r4, r3, #4 8007702: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8007706: 2200 movs r2, #0 8007708: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800770c: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8007710: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88 8007714: 4642 mov r2, r8 8007716: 464b mov r3, r9 8007718: 1891 adds r1, r2, r2 800771a: 61b9 str r1, [r7, #24] 800771c: 415b adcs r3, r3 800771e: 61fb str r3, [r7, #28] 8007720: e9d7 2306 ldrd r2, r3, [r7, #24] 8007724: 4641 mov r1, r8 8007726: 1851 adds r1, r2, r1 8007728: 6139 str r1, [r7, #16] 800772a: 4649 mov r1, r9 800772c: 414b adcs r3, r1 800772e: 617b str r3, [r7, #20] 8007730: f04f 0200 mov.w r2, #0 8007734: f04f 0300 mov.w r3, #0 8007738: e9d7 ab04 ldrd sl, fp, [r7, #16] 800773c: 4659 mov r1, fp 800773e: 00cb lsls r3, r1, #3 8007740: 4651 mov r1, sl 8007742: ea43 7351 orr.w r3, r3, r1, lsr #29 8007746: 4651 mov r1, sl 8007748: 00ca lsls r2, r1, #3 800774a: 4610 mov r0, r2 800774c: 4619 mov r1, r3 800774e: 4603 mov r3, r0 8007750: 4642 mov r2, r8 8007752: 189b adds r3, r3, r2 8007754: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8007758: 464b mov r3, r9 800775a: 460a mov r2, r1 800775c: eb42 0303 adc.w r3, r2, r3 8007760: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8007764: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007768: 685b ldr r3, [r3, #4] 800776a: 2200 movs r2, #0 800776c: 67bb str r3, [r7, #120] @ 0x78 800776e: 67fa str r2, [r7, #124] @ 0x7c 8007770: f04f 0200 mov.w r2, #0 8007774: f04f 0300 mov.w r3, #0 8007778: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78 800777c: 4649 mov r1, r9 800777e: 008b lsls r3, r1, #2 8007780: 4641 mov r1, r8 8007782: ea43 7391 orr.w r3, r3, r1, lsr #30 8007786: 4641 mov r1, r8 8007788: 008a lsls r2, r1, #2 800778a: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80 800778e: f7f8 fd39 bl 8000204 <__aeabi_uldivmod> 8007792: 4602 mov r2, r0 8007794: 460b mov r3, r1 8007796: 4611 mov r1, r2 8007798: 4b38 ldr r3, [pc, #224] @ (800787c ) 800779a: fba3 2301 umull r2, r3, r3, r1 800779e: 095b lsrs r3, r3, #5 80077a0: 2264 movs r2, #100 @ 0x64 80077a2: fb02 f303 mul.w r3, r2, r3 80077a6: 1acb subs r3, r1, r3 80077a8: 011b lsls r3, r3, #4 80077aa: 3332 adds r3, #50 @ 0x32 80077ac: 4a33 ldr r2, [pc, #204] @ (800787c ) 80077ae: fba2 2303 umull r2, r3, r2, r3 80077b2: 095b lsrs r3, r3, #5 80077b4: f003 03f0 and.w r3, r3, #240 @ 0xf0 80077b8: 441c add r4, r3 80077ba: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 80077be: 2200 movs r2, #0 80077c0: 673b str r3, [r7, #112] @ 0x70 80077c2: 677a str r2, [r7, #116] @ 0x74 80077c4: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70 80077c8: 4642 mov r2, r8 80077ca: 464b mov r3, r9 80077cc: 1891 adds r1, r2, r2 80077ce: 60b9 str r1, [r7, #8] 80077d0: 415b adcs r3, r3 80077d2: 60fb str r3, [r7, #12] 80077d4: e9d7 2302 ldrd r2, r3, [r7, #8] 80077d8: 4641 mov r1, r8 80077da: 1851 adds r1, r2, r1 80077dc: 6039 str r1, [r7, #0] 80077de: 4649 mov r1, r9 80077e0: 414b adcs r3, r1 80077e2: 607b str r3, [r7, #4] 80077e4: f04f 0200 mov.w r2, #0 80077e8: f04f 0300 mov.w r3, #0 80077ec: e9d7 ab00 ldrd sl, fp, [r7] 80077f0: 4659 mov r1, fp 80077f2: 00cb lsls r3, r1, #3 80077f4: 4651 mov r1, sl 80077f6: ea43 7351 orr.w r3, r3, r1, lsr #29 80077fa: 4651 mov r1, sl 80077fc: 00ca lsls r2, r1, #3 80077fe: 4610 mov r0, r2 8007800: 4619 mov r1, r3 8007802: 4603 mov r3, r0 8007804: 4642 mov r2, r8 8007806: 189b adds r3, r3, r2 8007808: 66bb str r3, [r7, #104] @ 0x68 800780a: 464b mov r3, r9 800780c: 460a mov r2, r1 800780e: eb42 0303 adc.w r3, r2, r3 8007812: 66fb str r3, [r7, #108] @ 0x6c 8007814: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8007818: 685b ldr r3, [r3, #4] 800781a: 2200 movs r2, #0 800781c: 663b str r3, [r7, #96] @ 0x60 800781e: 667a str r2, [r7, #100] @ 0x64 8007820: f04f 0200 mov.w r2, #0 8007824: f04f 0300 mov.w r3, #0 8007828: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60 800782c: 4649 mov r1, r9 800782e: 008b lsls r3, r1, #2 8007830: 4641 mov r1, r8 8007832: ea43 7391 orr.w r3, r3, r1, lsr #30 8007836: 4641 mov r1, r8 8007838: 008a lsls r2, r1, #2 800783a: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68 800783e: f7f8 fce1 bl 8000204 <__aeabi_uldivmod> 8007842: 4602 mov r2, r0 8007844: 460b mov r3, r1 8007846: 4b0d ldr r3, [pc, #52] @ (800787c ) 8007848: fba3 1302 umull r1, r3, r3, r2 800784c: 095b lsrs r3, r3, #5 800784e: 2164 movs r1, #100 @ 0x64 8007850: fb01 f303 mul.w r3, r1, r3 8007854: 1ad3 subs r3, r2, r3 8007856: 011b lsls r3, r3, #4 8007858: 3332 adds r3, #50 @ 0x32 800785a: 4a08 ldr r2, [pc, #32] @ (800787c ) 800785c: fba2 2303 umull r2, r3, r2, r3 8007860: 095b lsrs r3, r3, #5 8007862: f003 020f and.w r2, r3, #15 8007866: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800786a: 681b ldr r3, [r3, #0] 800786c: 4422 add r2, r4 800786e: 609a str r2, [r3, #8] } 8007870: bf00 nop 8007872: f507 7780 add.w r7, r7, #256 @ 0x100 8007876: 46bd mov sp, r7 8007878: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800787c: 51eb851f .word 0x51eb851f 08007880 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8007880: b084 sub sp, #16 8007882: b580 push {r7, lr} 8007884: b084 sub sp, #16 8007886: af00 add r7, sp, #0 8007888: 6078 str r0, [r7, #4] 800788a: f107 001c add.w r0, r7, #28 800788e: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8007892: f897 3021 ldrb.w r3, [r7, #33] @ 0x21 8007896: 2b01 cmp r3, #1 8007898: d123 bne.n 80078e2 { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 800789a: 687b ldr r3, [r7, #4] 800789c: 6b9b ldr r3, [r3, #56] @ 0x38 800789e: f423 3280 bic.w r2, r3, #65536 @ 0x10000 80078a2: 687b ldr r3, [r7, #4] 80078a4: 639a str r2, [r3, #56] @ 0x38 /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); 80078a6: 687b ldr r3, [r7, #4] 80078a8: 68db ldr r3, [r3, #12] 80078aa: f423 0384 bic.w r3, r3, #4325376 @ 0x420000 80078ae: f023 0340 bic.w r3, r3, #64 @ 0x40 80078b2: 687a ldr r2, [r7, #4] 80078b4: 60d3 str r3, [r2, #12] /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); 80078b6: 687b ldr r3, [r7, #4] 80078b8: 68db ldr r3, [r3, #12] 80078ba: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 80078be: 687b ldr r3, [r7, #4] 80078c0: 60da str r2, [r3, #12] if (cfg.use_external_vbus == 1U) 80078c2: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 80078c6: 2b01 cmp r3, #1 80078c8: d105 bne.n 80078d6 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; 80078ca: 687b ldr r3, [r7, #4] 80078cc: 68db ldr r3, [r3, #12] 80078ce: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 80078d2: 687b ldr r3, [r7, #4] 80078d4: 60da str r2, [r3, #12] } /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 80078d6: 6878 ldr r0, [r7, #4] 80078d8: f001 fae2 bl 8008ea0 80078dc: 4603 mov r3, r0 80078de: 73fb strb r3, [r7, #15] 80078e0: e01b b.n 800791a } else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 80078e2: 687b ldr r3, [r7, #4] 80078e4: 68db ldr r3, [r3, #12] 80078e6: f043 0240 orr.w r2, r3, #64 @ 0x40 80078ea: 687b ldr r3, [r7, #4] 80078ec: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 80078ee: 6878 ldr r0, [r7, #4] 80078f0: f001 fad6 bl 8008ea0 80078f4: 4603 mov r3, r0 80078f6: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 80078f8: f897 3025 ldrb.w r3, [r7, #37] @ 0x25 80078fc: 2b00 cmp r3, #0 80078fe: d106 bne.n 800790e { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8007900: 687b ldr r3, [r7, #4] 8007902: 6b9b ldr r3, [r3, #56] @ 0x38 8007904: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8007908: 687b ldr r3, [r7, #4] 800790a: 639a str r2, [r3, #56] @ 0x38 800790c: e005 b.n 800791a } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 800790e: 687b ldr r3, [r7, #4] 8007910: 6b9b ldr r3, [r3, #56] @ 0x38 8007912: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8007916: 687b ldr r3, [r7, #4] 8007918: 639a str r2, [r3, #56] @ 0x38 } } if (cfg.dma_enable == 1U) 800791a: 7fbb ldrb r3, [r7, #30] 800791c: 2b01 cmp r3, #1 800791e: d10b bne.n 8007938 { USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; 8007920: 687b ldr r3, [r7, #4] 8007922: 689b ldr r3, [r3, #8] 8007924: f043 0206 orr.w r2, r3, #6 8007928: 687b ldr r3, [r7, #4] 800792a: 609a str r2, [r3, #8] USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; 800792c: 687b ldr r3, [r7, #4] 800792e: 689b ldr r3, [r3, #8] 8007930: f043 0220 orr.w r2, r3, #32 8007934: 687b ldr r3, [r7, #4] 8007936: 609a str r2, [r3, #8] } return ret; 8007938: 7bfb ldrb r3, [r7, #15] } 800793a: 4618 mov r0, r3 800793c: 3710 adds r7, #16 800793e: 46bd mov sp, r7 8007940: e8bd 4080 ldmia.w sp!, {r7, lr} 8007944: b004 add sp, #16 8007946: 4770 bx lr 08007948 : * @param hclk: AHB clock frequency * @retval USB turnaround time In PHY Clocks number */ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed) { 8007948: b480 push {r7} 800794a: b087 sub sp, #28 800794c: af00 add r7, sp, #0 800794e: 60f8 str r0, [r7, #12] 8007950: 60b9 str r1, [r7, #8] 8007952: 4613 mov r3, r2 8007954: 71fb strb r3, [r7, #7] /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ if (speed == USBD_FS_SPEED) 8007956: 79fb ldrb r3, [r7, #7] 8007958: 2b02 cmp r3, #2 800795a: d165 bne.n 8007a28 { if ((hclk >= 14200000U) && (hclk < 15000000U)) 800795c: 68bb ldr r3, [r7, #8] 800795e: 4a41 ldr r2, [pc, #260] @ (8007a64 ) 8007960: 4293 cmp r3, r2 8007962: d906 bls.n 8007972 8007964: 68bb ldr r3, [r7, #8] 8007966: 4a40 ldr r2, [pc, #256] @ (8007a68 ) 8007968: 4293 cmp r3, r2 800796a: d202 bcs.n 8007972 { /* hclk Clock Range between 14.2-15 MHz */ UsbTrd = 0xFU; 800796c: 230f movs r3, #15 800796e: 617b str r3, [r7, #20] 8007970: e062 b.n 8007a38 } else if ((hclk >= 15000000U) && (hclk < 16000000U)) 8007972: 68bb ldr r3, [r7, #8] 8007974: 4a3c ldr r2, [pc, #240] @ (8007a68 ) 8007976: 4293 cmp r3, r2 8007978: d306 bcc.n 8007988 800797a: 68bb ldr r3, [r7, #8] 800797c: 4a3b ldr r2, [pc, #236] @ (8007a6c ) 800797e: 4293 cmp r3, r2 8007980: d202 bcs.n 8007988 { /* hclk Clock Range between 15-16 MHz */ UsbTrd = 0xEU; 8007982: 230e movs r3, #14 8007984: 617b str r3, [r7, #20] 8007986: e057 b.n 8007a38 } else if ((hclk >= 16000000U) && (hclk < 17200000U)) 8007988: 68bb ldr r3, [r7, #8] 800798a: 4a38 ldr r2, [pc, #224] @ (8007a6c ) 800798c: 4293 cmp r3, r2 800798e: d306 bcc.n 800799e 8007990: 68bb ldr r3, [r7, #8] 8007992: 4a37 ldr r2, [pc, #220] @ (8007a70 ) 8007994: 4293 cmp r3, r2 8007996: d202 bcs.n 800799e { /* hclk Clock Range between 16-17.2 MHz */ UsbTrd = 0xDU; 8007998: 230d movs r3, #13 800799a: 617b str r3, [r7, #20] 800799c: e04c b.n 8007a38 } else if ((hclk >= 17200000U) && (hclk < 18500000U)) 800799e: 68bb ldr r3, [r7, #8] 80079a0: 4a33 ldr r2, [pc, #204] @ (8007a70 ) 80079a2: 4293 cmp r3, r2 80079a4: d306 bcc.n 80079b4 80079a6: 68bb ldr r3, [r7, #8] 80079a8: 4a32 ldr r2, [pc, #200] @ (8007a74 ) 80079aa: 4293 cmp r3, r2 80079ac: d802 bhi.n 80079b4 { /* hclk Clock Range between 17.2-18.5 MHz */ UsbTrd = 0xCU; 80079ae: 230c movs r3, #12 80079b0: 617b str r3, [r7, #20] 80079b2: e041 b.n 8007a38 } else if ((hclk >= 18500000U) && (hclk < 20000000U)) 80079b4: 68bb ldr r3, [r7, #8] 80079b6: 4a2f ldr r2, [pc, #188] @ (8007a74 ) 80079b8: 4293 cmp r3, r2 80079ba: d906 bls.n 80079ca 80079bc: 68bb ldr r3, [r7, #8] 80079be: 4a2e ldr r2, [pc, #184] @ (8007a78 ) 80079c0: 4293 cmp r3, r2 80079c2: d802 bhi.n 80079ca { /* hclk Clock Range between 18.5-20 MHz */ UsbTrd = 0xBU; 80079c4: 230b movs r3, #11 80079c6: 617b str r3, [r7, #20] 80079c8: e036 b.n 8007a38 } else if ((hclk >= 20000000U) && (hclk < 21800000U)) 80079ca: 68bb ldr r3, [r7, #8] 80079cc: 4a2a ldr r2, [pc, #168] @ (8007a78 ) 80079ce: 4293 cmp r3, r2 80079d0: d906 bls.n 80079e0 80079d2: 68bb ldr r3, [r7, #8] 80079d4: 4a29 ldr r2, [pc, #164] @ (8007a7c ) 80079d6: 4293 cmp r3, r2 80079d8: d802 bhi.n 80079e0 { /* hclk Clock Range between 20-21.8 MHz */ UsbTrd = 0xAU; 80079da: 230a movs r3, #10 80079dc: 617b str r3, [r7, #20] 80079de: e02b b.n 8007a38 } else if ((hclk >= 21800000U) && (hclk < 24000000U)) 80079e0: 68bb ldr r3, [r7, #8] 80079e2: 4a26 ldr r2, [pc, #152] @ (8007a7c ) 80079e4: 4293 cmp r3, r2 80079e6: d906 bls.n 80079f6 80079e8: 68bb ldr r3, [r7, #8] 80079ea: 4a25 ldr r2, [pc, #148] @ (8007a80 ) 80079ec: 4293 cmp r3, r2 80079ee: d202 bcs.n 80079f6 { /* hclk Clock Range between 21.8-24 MHz */ UsbTrd = 0x9U; 80079f0: 2309 movs r3, #9 80079f2: 617b str r3, [r7, #20] 80079f4: e020 b.n 8007a38 } else if ((hclk >= 24000000U) && (hclk < 27700000U)) 80079f6: 68bb ldr r3, [r7, #8] 80079f8: 4a21 ldr r2, [pc, #132] @ (8007a80 ) 80079fa: 4293 cmp r3, r2 80079fc: d306 bcc.n 8007a0c 80079fe: 68bb ldr r3, [r7, #8] 8007a00: 4a20 ldr r2, [pc, #128] @ (8007a84 ) 8007a02: 4293 cmp r3, r2 8007a04: d802 bhi.n 8007a0c { /* hclk Clock Range between 24-27.7 MHz */ UsbTrd = 0x8U; 8007a06: 2308 movs r3, #8 8007a08: 617b str r3, [r7, #20] 8007a0a: e015 b.n 8007a38 } else if ((hclk >= 27700000U) && (hclk < 32000000U)) 8007a0c: 68bb ldr r3, [r7, #8] 8007a0e: 4a1d ldr r2, [pc, #116] @ (8007a84 ) 8007a10: 4293 cmp r3, r2 8007a12: d906 bls.n 8007a22 8007a14: 68bb ldr r3, [r7, #8] 8007a16: 4a1c ldr r2, [pc, #112] @ (8007a88 ) 8007a18: 4293 cmp r3, r2 8007a1a: d202 bcs.n 8007a22 { /* hclk Clock Range between 27.7-32 MHz */ UsbTrd = 0x7U; 8007a1c: 2307 movs r3, #7 8007a1e: 617b str r3, [r7, #20] 8007a20: e00a b.n 8007a38 } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ UsbTrd = 0x6U; 8007a22: 2306 movs r3, #6 8007a24: 617b str r3, [r7, #20] 8007a26: e007 b.n 8007a38 } } else if (speed == USBD_HS_SPEED) 8007a28: 79fb ldrb r3, [r7, #7] 8007a2a: 2b00 cmp r3, #0 8007a2c: d102 bne.n 8007a34 { UsbTrd = USBD_HS_TRDT_VALUE; 8007a2e: 2309 movs r3, #9 8007a30: 617b str r3, [r7, #20] 8007a32: e001 b.n 8007a38 } else { UsbTrd = USBD_DEFAULT_TRDT_VALUE; 8007a34: 2309 movs r3, #9 8007a36: 617b str r3, [r7, #20] } USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; 8007a38: 68fb ldr r3, [r7, #12] 8007a3a: 68db ldr r3, [r3, #12] 8007a3c: f423 5270 bic.w r2, r3, #15360 @ 0x3c00 8007a40: 68fb ldr r3, [r7, #12] 8007a42: 60da str r2, [r3, #12] USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); 8007a44: 68fb ldr r3, [r7, #12] 8007a46: 68da ldr r2, [r3, #12] 8007a48: 697b ldr r3, [r7, #20] 8007a4a: 029b lsls r3, r3, #10 8007a4c: f403 5370 and.w r3, r3, #15360 @ 0x3c00 8007a50: 431a orrs r2, r3 8007a52: 68fb ldr r3, [r7, #12] 8007a54: 60da str r2, [r3, #12] return HAL_OK; 8007a56: 2300 movs r3, #0 } 8007a58: 4618 mov r0, r3 8007a5a: 371c adds r7, #28 8007a5c: 46bd mov sp, r7 8007a5e: f85d 7b04 ldr.w r7, [sp], #4 8007a62: 4770 bx lr 8007a64: 00d8acbf .word 0x00d8acbf 8007a68: 00e4e1c0 .word 0x00e4e1c0 8007a6c: 00f42400 .word 0x00f42400 8007a70: 01067380 .word 0x01067380 8007a74: 011a499f .word 0x011a499f 8007a78: 01312cff .word 0x01312cff 8007a7c: 014ca43f .word 0x014ca43f 8007a80: 016e3600 .word 0x016e3600 8007a84: 01a6ab1f .word 0x01a6ab1f 8007a88: 01e84800 .word 0x01e84800 08007a8c : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8007a8c: b480 push {r7} 8007a8e: b083 sub sp, #12 8007a90: af00 add r7, sp, #0 8007a92: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 8007a94: 687b ldr r3, [r7, #4] 8007a96: 689b ldr r3, [r3, #8] 8007a98: f043 0201 orr.w r2, r3, #1 8007a9c: 687b ldr r3, [r7, #4] 8007a9e: 609a str r2, [r3, #8] return HAL_OK; 8007aa0: 2300 movs r3, #0 } 8007aa2: 4618 mov r0, r3 8007aa4: 370c adds r7, #12 8007aa6: 46bd mov sp, r7 8007aa8: f85d 7b04 ldr.w r7, [sp], #4 8007aac: 4770 bx lr 08007aae : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8007aae: b480 push {r7} 8007ab0: b083 sub sp, #12 8007ab2: af00 add r7, sp, #0 8007ab4: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 8007ab6: 687b ldr r3, [r7, #4] 8007ab8: 689b ldr r3, [r3, #8] 8007aba: f023 0201 bic.w r2, r3, #1 8007abe: 687b ldr r3, [r7, #4] 8007ac0: 609a str r2, [r3, #8] return HAL_OK; 8007ac2: 2300 movs r3, #0 } 8007ac4: 4618 mov r0, r3 8007ac6: 370c adds r7, #12 8007ac8: 46bd mov sp, r7 8007aca: f85d 7b04 ldr.w r7, [sp], #4 8007ace: 4770 bx lr 08007ad0 : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { 8007ad0: b580 push {r7, lr} 8007ad2: b084 sub sp, #16 8007ad4: af00 add r7, sp, #0 8007ad6: 6078 str r0, [r7, #4] 8007ad8: 460b mov r3, r1 8007ada: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 8007adc: 2300 movs r3, #0 8007ade: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 8007ae0: 687b ldr r3, [r7, #4] 8007ae2: 68db ldr r3, [r3, #12] 8007ae4: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000 8007ae8: 687b ldr r3, [r7, #4] 8007aea: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 8007aec: 78fb ldrb r3, [r7, #3] 8007aee: 2b01 cmp r3, #1 8007af0: d115 bne.n 8007b1e { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 8007af2: 687b ldr r3, [r7, #4] 8007af4: 68db ldr r3, [r3, #12] 8007af6: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000 8007afa: 687b ldr r3, [r7, #4] 8007afc: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8007afe: 200a movs r0, #10 8007b00: f7fa fa2e bl 8001f60 ms += 10U; 8007b04: 68fb ldr r3, [r7, #12] 8007b06: 330a adds r3, #10 8007b08: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8007b0a: 6878 ldr r0, [r7, #4] 8007b0c: f001 f939 bl 8008d82 8007b10: 4603 mov r3, r0 8007b12: 2b01 cmp r3, #1 8007b14: d01e beq.n 8007b54 8007b16: 68fb ldr r3, [r7, #12] 8007b18: 2bc7 cmp r3, #199 @ 0xc7 8007b1a: d9f0 bls.n 8007afe 8007b1c: e01a b.n 8007b54 } else if (mode == USB_DEVICE_MODE) 8007b1e: 78fb ldrb r3, [r7, #3] 8007b20: 2b00 cmp r3, #0 8007b22: d115 bne.n 8007b50 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 8007b24: 687b ldr r3, [r7, #4] 8007b26: 68db ldr r3, [r3, #12] 8007b28: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000 8007b2c: 687b ldr r3, [r7, #4] 8007b2e: 60da str r2, [r3, #12] do { HAL_Delay(10U); 8007b30: 200a movs r0, #10 8007b32: f7fa fa15 bl 8001f60 ms += 10U; 8007b36: 68fb ldr r3, [r7, #12] 8007b38: 330a adds r3, #10 8007b3a: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); 8007b3c: 6878 ldr r0, [r7, #4] 8007b3e: f001 f920 bl 8008d82 8007b42: 4603 mov r3, r0 8007b44: 2b00 cmp r3, #0 8007b46: d005 beq.n 8007b54 8007b48: 68fb ldr r3, [r7, #12] 8007b4a: 2bc7 cmp r3, #199 @ 0xc7 8007b4c: d9f0 bls.n 8007b30 8007b4e: e001 b.n 8007b54 } else { return HAL_ERROR; 8007b50: 2301 movs r3, #1 8007b52: e005 b.n 8007b60 } if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) 8007b54: 68fb ldr r3, [r7, #12] 8007b56: 2bc8 cmp r3, #200 @ 0xc8 8007b58: d101 bne.n 8007b5e { return HAL_ERROR; 8007b5a: 2301 movs r3, #1 8007b5c: e000 b.n 8007b60 } return HAL_OK; 8007b5e: 2300 movs r3, #0 } 8007b60: 4618 mov r0, r3 8007b62: 3710 adds r7, #16 8007b64: 46bd mov sp, r7 8007b66: bd80 pop {r7, pc} 08007b68 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8007b68: b084 sub sp, #16 8007b6a: b580 push {r7, lr} 8007b6c: b086 sub sp, #24 8007b6e: af00 add r7, sp, #0 8007b70: 6078 str r0, [r7, #4] 8007b72: f107 0024 add.w r0, r7, #36 @ 0x24 8007b76: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 8007b7a: 2300 movs r3, #0 8007b7c: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8007b7e: 687b ldr r3, [r7, #4] 8007b80: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 8007b82: 2300 movs r3, #0 8007b84: 613b str r3, [r7, #16] 8007b86: e009 b.n 8007b9c { USBx->DIEPTXF[i] = 0U; 8007b88: 687a ldr r2, [r7, #4] 8007b8a: 693b ldr r3, [r7, #16] 8007b8c: 3340 adds r3, #64 @ 0x40 8007b8e: 009b lsls r3, r3, #2 8007b90: 4413 add r3, r2 8007b92: 2200 movs r2, #0 8007b94: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 8007b96: 693b ldr r3, [r7, #16] 8007b98: 3301 adds r3, #1 8007b9a: 613b str r3, [r7, #16] 8007b9c: 693b ldr r3, [r7, #16] 8007b9e: 2b0e cmp r3, #14 8007ba0: d9f2 bls.n 8007b88 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) \ || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) \ || defined(STM32F423xx) /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 8007ba2: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8007ba6: 2b00 cmp r3, #0 8007ba8: d11c bne.n 8007be4 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8007baa: 68fb ldr r3, [r7, #12] 8007bac: f503 6300 add.w r3, r3, #2048 @ 0x800 8007bb0: 685b ldr r3, [r3, #4] 8007bb2: 68fa ldr r2, [r7, #12] 8007bb4: f502 6200 add.w r2, r2, #2048 @ 0x800 8007bb8: f043 0302 orr.w r3, r3, #2 8007bbc: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 8007bbe: 687b ldr r3, [r7, #4] 8007bc0: 6b9b ldr r3, [r3, #56] @ 0x38 8007bc2: f423 1200 bic.w r2, r3, #2097152 @ 0x200000 8007bc6: 687b ldr r3, [r7, #4] 8007bc8: 639a str r2, [r3, #56] @ 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 8007bca: 687b ldr r3, [r7, #4] 8007bcc: 681b ldr r3, [r3, #0] 8007bce: f043 0240 orr.w r2, r3, #64 @ 0x40 8007bd2: 687b ldr r3, [r7, #4] 8007bd4: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 8007bd6: 687b ldr r3, [r7, #4] 8007bd8: 681b ldr r3, [r3, #0] 8007bda: f043 0280 orr.w r2, r3, #128 @ 0x80 8007bde: 687b ldr r3, [r7, #4] 8007be0: 601a str r2, [r3, #0] 8007be2: e005 b.n 8007bf0 } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 8007be4: 687b ldr r3, [r7, #4] 8007be6: 6b9b ldr r3, [r3, #56] @ 0x38 8007be8: f443 1200 orr.w r2, r3, #2097152 @ 0x200000 8007bec: 687b ldr r3, [r7, #4] 8007bee: 639a str r2, [r3, #56] @ 0x38 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 8007bf0: 68fb ldr r3, [r7, #12] 8007bf2: f503 6360 add.w r3, r3, #3584 @ 0xe00 8007bf6: 461a mov r2, r3 8007bf8: 2300 movs r3, #0 8007bfa: 6013 str r3, [r2, #0] if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8007bfc: f897 3029 ldrb.w r3, [r7, #41] @ 0x29 8007c00: 2b01 cmp r3, #1 8007c02: d10d bne.n 8007c20 { if (cfg.speed == USBD_HS_SPEED) 8007c04: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8007c08: 2b00 cmp r3, #0 8007c0a: d104 bne.n 8007c16 { /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); 8007c0c: 2100 movs r1, #0 8007c0e: 6878 ldr r0, [r7, #4] 8007c10: f000 f968 bl 8007ee4 8007c14: e008 b.n 8007c28 } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); 8007c16: 2101 movs r1, #1 8007c18: 6878 ldr r0, [r7, #4] 8007c1a: f000 f963 bl 8007ee4 8007c1e: e003 b.n 8007c28 } } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 8007c20: 2103 movs r1, #3 8007c22: 6878 ldr r0, [r7, #4] 8007c24: f000 f95e bl 8007ee4 } /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 8007c28: 2110 movs r1, #16 8007c2a: 6878 ldr r0, [r7, #4] 8007c2c: f000 f8fa bl 8007e24 8007c30: 4603 mov r3, r0 8007c32: 2b00 cmp r3, #0 8007c34: d001 beq.n 8007c3a { ret = HAL_ERROR; 8007c36: 2301 movs r3, #1 8007c38: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 8007c3a: 6878 ldr r0, [r7, #4] 8007c3c: f000 f924 bl 8007e88 8007c40: 4603 mov r3, r0 8007c42: 2b00 cmp r3, #0 8007c44: d001 beq.n 8007c4a { ret = HAL_ERROR; 8007c46: 2301 movs r3, #1 8007c48: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 8007c4a: 68fb ldr r3, [r7, #12] 8007c4c: f503 6300 add.w r3, r3, #2048 @ 0x800 8007c50: 461a mov r2, r3 8007c52: 2300 movs r3, #0 8007c54: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 8007c56: 68fb ldr r3, [r7, #12] 8007c58: f503 6300 add.w r3, r3, #2048 @ 0x800 8007c5c: 461a mov r2, r3 8007c5e: 2300 movs r3, #0 8007c60: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 8007c62: 68fb ldr r3, [r7, #12] 8007c64: f503 6300 add.w r3, r3, #2048 @ 0x800 8007c68: 461a mov r2, r3 8007c6a: 2300 movs r3, #0 8007c6c: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 8007c6e: 2300 movs r3, #0 8007c70: 613b str r3, [r7, #16] 8007c72: e043 b.n 8007cfc { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8007c74: 693b ldr r3, [r7, #16] 8007c76: 015a lsls r2, r3, #5 8007c78: 68fb ldr r3, [r7, #12] 8007c7a: 4413 add r3, r2 8007c7c: f503 6310 add.w r3, r3, #2304 @ 0x900 8007c80: 681b ldr r3, [r3, #0] 8007c82: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007c86: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007c8a: d118 bne.n 8007cbe { if (i == 0U) 8007c8c: 693b ldr r3, [r7, #16] 8007c8e: 2b00 cmp r3, #0 8007c90: d10a bne.n 8007ca8 { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 8007c92: 693b ldr r3, [r7, #16] 8007c94: 015a lsls r2, r3, #5 8007c96: 68fb ldr r3, [r7, #12] 8007c98: 4413 add r3, r2 8007c9a: f503 6310 add.w r3, r3, #2304 @ 0x900 8007c9e: 461a mov r2, r3 8007ca0: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8007ca4: 6013 str r3, [r2, #0] 8007ca6: e013 b.n 8007cd0 } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 8007ca8: 693b ldr r3, [r7, #16] 8007caa: 015a lsls r2, r3, #5 8007cac: 68fb ldr r3, [r7, #12] 8007cae: 4413 add r3, r2 8007cb0: f503 6310 add.w r3, r3, #2304 @ 0x900 8007cb4: 461a mov r2, r3 8007cb6: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 8007cba: 6013 str r3, [r2, #0] 8007cbc: e008 b.n 8007cd0 } } else { USBx_INEP(i)->DIEPCTL = 0U; 8007cbe: 693b ldr r3, [r7, #16] 8007cc0: 015a lsls r2, r3, #5 8007cc2: 68fb ldr r3, [r7, #12] 8007cc4: 4413 add r3, r2 8007cc6: f503 6310 add.w r3, r3, #2304 @ 0x900 8007cca: 461a mov r2, r3 8007ccc: 2300 movs r3, #0 8007cce: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 8007cd0: 693b ldr r3, [r7, #16] 8007cd2: 015a lsls r2, r3, #5 8007cd4: 68fb ldr r3, [r7, #12] 8007cd6: 4413 add r3, r2 8007cd8: f503 6310 add.w r3, r3, #2304 @ 0x900 8007cdc: 461a mov r2, r3 8007cde: 2300 movs r3, #0 8007ce0: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 8007ce2: 693b ldr r3, [r7, #16] 8007ce4: 015a lsls r2, r3, #5 8007ce6: 68fb ldr r3, [r7, #12] 8007ce8: 4413 add r3, r2 8007cea: f503 6310 add.w r3, r3, #2304 @ 0x900 8007cee: 461a mov r2, r3 8007cf0: f64f 337f movw r3, #64383 @ 0xfb7f 8007cf4: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8007cf6: 693b ldr r3, [r7, #16] 8007cf8: 3301 adds r3, #1 8007cfa: 613b str r3, [r7, #16] 8007cfc: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8007d00: 461a mov r2, r3 8007d02: 693b ldr r3, [r7, #16] 8007d04: 4293 cmp r3, r2 8007d06: d3b5 bcc.n 8007c74 } for (i = 0U; i < cfg.dev_endpoints; i++) 8007d08: 2300 movs r3, #0 8007d0a: 613b str r3, [r7, #16] 8007d0c: e043 b.n 8007d96 { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8007d0e: 693b ldr r3, [r7, #16] 8007d10: 015a lsls r2, r3, #5 8007d12: 68fb ldr r3, [r7, #12] 8007d14: 4413 add r3, r2 8007d16: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d1a: 681b ldr r3, [r3, #0] 8007d1c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007d20: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007d24: d118 bne.n 8007d58 { if (i == 0U) 8007d26: 693b ldr r3, [r7, #16] 8007d28: 2b00 cmp r3, #0 8007d2a: d10a bne.n 8007d42 { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 8007d2c: 693b ldr r3, [r7, #16] 8007d2e: 015a lsls r2, r3, #5 8007d30: 68fb ldr r3, [r7, #12] 8007d32: 4413 add r3, r2 8007d34: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d38: 461a mov r2, r3 8007d3a: f04f 6300 mov.w r3, #134217728 @ 0x8000000 8007d3e: 6013 str r3, [r2, #0] 8007d40: e013 b.n 8007d6a } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 8007d42: 693b ldr r3, [r7, #16] 8007d44: 015a lsls r2, r3, #5 8007d46: 68fb ldr r3, [r7, #12] 8007d48: 4413 add r3, r2 8007d4a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d4e: 461a mov r2, r3 8007d50: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 8007d54: 6013 str r3, [r2, #0] 8007d56: e008 b.n 8007d6a } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 8007d58: 693b ldr r3, [r7, #16] 8007d5a: 015a lsls r2, r3, #5 8007d5c: 68fb ldr r3, [r7, #12] 8007d5e: 4413 add r3, r2 8007d60: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d64: 461a mov r2, r3 8007d66: 2300 movs r3, #0 8007d68: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 8007d6a: 693b ldr r3, [r7, #16] 8007d6c: 015a lsls r2, r3, #5 8007d6e: 68fb ldr r3, [r7, #12] 8007d70: 4413 add r3, r2 8007d72: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d76: 461a mov r2, r3 8007d78: 2300 movs r3, #0 8007d7a: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 8007d7c: 693b ldr r3, [r7, #16] 8007d7e: 015a lsls r2, r3, #5 8007d80: 68fb ldr r3, [r7, #12] 8007d82: 4413 add r3, r2 8007d84: f503 6330 add.w r3, r3, #2816 @ 0xb00 8007d88: 461a mov r2, r3 8007d8a: f64f 337f movw r3, #64383 @ 0xfb7f 8007d8e: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8007d90: 693b ldr r3, [r7, #16] 8007d92: 3301 adds r3, #1 8007d94: 613b str r3, [r7, #16] 8007d96: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 8007d9a: 461a mov r2, r3 8007d9c: 693b ldr r3, [r7, #16] 8007d9e: 4293 cmp r3, r2 8007da0: d3b5 bcc.n 8007d0e } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 8007da2: 68fb ldr r3, [r7, #12] 8007da4: f503 6300 add.w r3, r3, #2048 @ 0x800 8007da8: 691b ldr r3, [r3, #16] 8007daa: 68fa ldr r2, [r7, #12] 8007dac: f502 6200 add.w r2, r2, #2048 @ 0x800 8007db0: f423 7380 bic.w r3, r3, #256 @ 0x100 8007db4: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 8007db6: 687b ldr r3, [r7, #4] 8007db8: 2200 movs r2, #0 8007dba: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 8007dbc: 687b ldr r3, [r7, #4] 8007dbe: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000 8007dc2: 615a str r2, [r3, #20] /* Enable the common interrupts */ if (cfg.dma_enable == 0U) 8007dc4: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8007dc8: 2b00 cmp r3, #0 8007dca: d105 bne.n 8007dd8 { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 8007dcc: 687b ldr r3, [r7, #4] 8007dce: 699b ldr r3, [r3, #24] 8007dd0: f043 0210 orr.w r2, r3, #16 8007dd4: 687b ldr r3, [r7, #4] 8007dd6: 619a str r2, [r3, #24] } /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 8007dd8: 687b ldr r3, [r7, #4] 8007dda: 699a ldr r2, [r3, #24] 8007ddc: 4b10 ldr r3, [pc, #64] @ (8007e20 ) 8007dde: 4313 orrs r3, r2 8007de0: 687a ldr r2, [r7, #4] 8007de2: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 8007de4: f897 302a ldrb.w r3, [r7, #42] @ 0x2a 8007de8: 2b00 cmp r3, #0 8007dea: d005 beq.n 8007df8 { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 8007dec: 687b ldr r3, [r7, #4] 8007dee: 699b ldr r3, [r3, #24] 8007df0: f043 0208 orr.w r2, r3, #8 8007df4: 687b ldr r3, [r7, #4] 8007df6: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 8007df8: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8007dfc: 2b01 cmp r3, #1 8007dfe: d107 bne.n 8007e10 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 8007e00: 687b ldr r3, [r7, #4] 8007e02: 699b ldr r3, [r3, #24] 8007e04: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007e08: f043 0304 orr.w r3, r3, #4 8007e0c: 687a ldr r2, [r7, #4] 8007e0e: 6193 str r3, [r2, #24] } return ret; 8007e10: 7dfb ldrb r3, [r7, #23] } 8007e12: 4618 mov r0, r3 8007e14: 3718 adds r7, #24 8007e16: 46bd mov sp, r7 8007e18: e8bd 4080 ldmia.w sp!, {r7, lr} 8007e1c: b004 add sp, #16 8007e1e: 4770 bx lr 8007e20: 803c3800 .word 0x803c3800 08007e24 : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 8007e24: b480 push {r7} 8007e26: b085 sub sp, #20 8007e28: af00 add r7, sp, #0 8007e2a: 6078 str r0, [r7, #4] 8007e2c: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8007e2e: 2300 movs r3, #0 8007e30: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8007e32: 68fb ldr r3, [r7, #12] 8007e34: 3301 adds r3, #1 8007e36: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007e38: 68fb ldr r3, [r7, #12] 8007e3a: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007e3e: d901 bls.n 8007e44 { return HAL_TIMEOUT; 8007e40: 2303 movs r3, #3 8007e42: e01b b.n 8007e7c } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8007e44: 687b ldr r3, [r7, #4] 8007e46: 691b ldr r3, [r3, #16] 8007e48: 2b00 cmp r3, #0 8007e4a: daf2 bge.n 8007e32 /* Flush TX Fifo */ count = 0U; 8007e4c: 2300 movs r3, #0 8007e4e: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 8007e50: 683b ldr r3, [r7, #0] 8007e52: 019b lsls r3, r3, #6 8007e54: f043 0220 orr.w r2, r3, #32 8007e58: 687b ldr r3, [r7, #4] 8007e5a: 611a str r2, [r3, #16] do { count++; 8007e5c: 68fb ldr r3, [r7, #12] 8007e5e: 3301 adds r3, #1 8007e60: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007e62: 68fb ldr r3, [r7, #12] 8007e64: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007e68: d901 bls.n 8007e6e { return HAL_TIMEOUT; 8007e6a: 2303 movs r3, #3 8007e6c: e006 b.n 8007e7c } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 8007e6e: 687b ldr r3, [r7, #4] 8007e70: 691b ldr r3, [r3, #16] 8007e72: f003 0320 and.w r3, r3, #32 8007e76: 2b20 cmp r3, #32 8007e78: d0f0 beq.n 8007e5c return HAL_OK; 8007e7a: 2300 movs r3, #0 } 8007e7c: 4618 mov r0, r3 8007e7e: 3714 adds r7, #20 8007e80: 46bd mov sp, r7 8007e82: f85d 7b04 ldr.w r7, [sp], #4 8007e86: 4770 bx lr 08007e88 : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 8007e88: b480 push {r7} 8007e8a: b085 sub sp, #20 8007e8c: af00 add r7, sp, #0 8007e8e: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8007e90: 2300 movs r3, #0 8007e92: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8007e94: 68fb ldr r3, [r7, #12] 8007e96: 3301 adds r3, #1 8007e98: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007e9a: 68fb ldr r3, [r7, #12] 8007e9c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007ea0: d901 bls.n 8007ea6 { return HAL_TIMEOUT; 8007ea2: 2303 movs r3, #3 8007ea4: e018 b.n 8007ed8 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8007ea6: 687b ldr r3, [r7, #4] 8007ea8: 691b ldr r3, [r3, #16] 8007eaa: 2b00 cmp r3, #0 8007eac: daf2 bge.n 8007e94 /* Flush RX Fifo */ count = 0U; 8007eae: 2300 movs r3, #0 8007eb0: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 8007eb2: 687b ldr r3, [r7, #4] 8007eb4: 2210 movs r2, #16 8007eb6: 611a str r2, [r3, #16] do { count++; 8007eb8: 68fb ldr r3, [r7, #12] 8007eba: 3301 adds r3, #1 8007ebc: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8007ebe: 68fb ldr r3, [r7, #12] 8007ec0: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8007ec4: d901 bls.n 8007eca { return HAL_TIMEOUT; 8007ec6: 2303 movs r3, #3 8007ec8: e006 b.n 8007ed8 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 8007eca: 687b ldr r3, [r7, #4] 8007ecc: 691b ldr r3, [r3, #16] 8007ece: f003 0310 and.w r3, r3, #16 8007ed2: 2b10 cmp r3, #16 8007ed4: d0f0 beq.n 8007eb8 return HAL_OK; 8007ed6: 2300 movs r3, #0 } 8007ed8: 4618 mov r0, r3 8007eda: 3714 adds r7, #20 8007edc: 46bd mov sp, r7 8007ede: f85d 7b04 ldr.w r7, [sp], #4 8007ee2: 4770 bx lr 08007ee4 : * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 8007ee4: b480 push {r7} 8007ee6: b085 sub sp, #20 8007ee8: af00 add r7, sp, #0 8007eea: 6078 str r0, [r7, #4] 8007eec: 460b mov r3, r1 8007eee: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8007ef0: 687b ldr r3, [r7, #4] 8007ef2: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 8007ef4: 68fb ldr r3, [r7, #12] 8007ef6: f503 6300 add.w r3, r3, #2048 @ 0x800 8007efa: 681a ldr r2, [r3, #0] 8007efc: 78fb ldrb r3, [r7, #3] 8007efe: 68f9 ldr r1, [r7, #12] 8007f00: f501 6100 add.w r1, r1, #2048 @ 0x800 8007f04: 4313 orrs r3, r2 8007f06: 600b str r3, [r1, #0] return HAL_OK; 8007f08: 2300 movs r3, #0 } 8007f0a: 4618 mov r0, r3 8007f0c: 3714 adds r7, #20 8007f0e: 46bd mov sp, r7 8007f10: f85d 7b04 ldr.w r7, [sp], #4 8007f14: 4770 bx lr 08007f16 : * This parameter can be one of these values: * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { 8007f16: b480 push {r7} 8007f18: b087 sub sp, #28 8007f1a: af00 add r7, sp, #0 8007f1c: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8007f1e: 687b ldr r3, [r7, #4] 8007f20: 613b str r3, [r7, #16] uint8_t speed; uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; 8007f22: 693b ldr r3, [r7, #16] 8007f24: f503 6300 add.w r3, r3, #2048 @ 0x800 8007f28: 689b ldr r3, [r3, #8] 8007f2a: f003 0306 and.w r3, r3, #6 8007f2e: 60fb str r3, [r7, #12] if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 8007f30: 68fb ldr r3, [r7, #12] 8007f32: 2b00 cmp r3, #0 8007f34: d102 bne.n 8007f3c { speed = USBD_HS_SPEED; 8007f36: 2300 movs r3, #0 8007f38: 75fb strb r3, [r7, #23] 8007f3a: e00a b.n 8007f52 } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || 8007f3c: 68fb ldr r3, [r7, #12] 8007f3e: 2b02 cmp r3, #2 8007f40: d002 beq.n 8007f48 8007f42: 68fb ldr r3, [r7, #12] 8007f44: 2b06 cmp r3, #6 8007f46: d102 bne.n 8007f4e (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USBD_FS_SPEED; 8007f48: 2302 movs r3, #2 8007f4a: 75fb strb r3, [r7, #23] 8007f4c: e001 b.n 8007f52 } else { speed = 0xFU; 8007f4e: 230f movs r3, #15 8007f50: 75fb strb r3, [r7, #23] } return speed; 8007f52: 7dfb ldrb r3, [r7, #23] } 8007f54: 4618 mov r0, r3 8007f56: 371c adds r7, #28 8007f58: 46bd mov sp, r7 8007f5a: f85d 7b04 ldr.w r7, [sp], #4 8007f5e: 4770 bx lr 08007f60 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8007f60: b480 push {r7} 8007f62: b085 sub sp, #20 8007f64: af00 add r7, sp, #0 8007f66: 6078 str r0, [r7, #4] 8007f68: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8007f6a: 687b ldr r3, [r7, #4] 8007f6c: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8007f6e: 683b ldr r3, [r7, #0] 8007f70: 781b ldrb r3, [r3, #0] 8007f72: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8007f74: 683b ldr r3, [r7, #0] 8007f76: 785b ldrb r3, [r3, #1] 8007f78: 2b01 cmp r3, #1 8007f7a: d13a bne.n 8007ff2 { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); 8007f7c: 68fb ldr r3, [r7, #12] 8007f7e: f503 6300 add.w r3, r3, #2048 @ 0x800 8007f82: 69da ldr r2, [r3, #28] 8007f84: 683b ldr r3, [r7, #0] 8007f86: 781b ldrb r3, [r3, #0] 8007f88: f003 030f and.w r3, r3, #15 8007f8c: 2101 movs r1, #1 8007f8e: fa01 f303 lsl.w r3, r1, r3 8007f92: b29b uxth r3, r3 8007f94: 68f9 ldr r1, [r7, #12] 8007f96: f501 6100 add.w r1, r1, #2048 @ 0x800 8007f9a: 4313 orrs r3, r2 8007f9c: 61cb str r3, [r1, #28] if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) 8007f9e: 68bb ldr r3, [r7, #8] 8007fa0: 015a lsls r2, r3, #5 8007fa2: 68fb ldr r3, [r7, #12] 8007fa4: 4413 add r3, r2 8007fa6: f503 6310 add.w r3, r3, #2304 @ 0x900 8007faa: 681b ldr r3, [r3, #0] 8007fac: f403 4300 and.w r3, r3, #32768 @ 0x8000 8007fb0: 2b00 cmp r3, #0 8007fb2: d155 bne.n 8008060 { USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8007fb4: 68bb ldr r3, [r7, #8] 8007fb6: 015a lsls r2, r3, #5 8007fb8: 68fb ldr r3, [r7, #12] 8007fba: 4413 add r3, r2 8007fbc: f503 6310 add.w r3, r3, #2304 @ 0x900 8007fc0: 681a ldr r2, [r3, #0] 8007fc2: 683b ldr r3, [r7, #0] 8007fc4: 689b ldr r3, [r3, #8] 8007fc6: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | (epnum << 22) | 8007fca: 683b ldr r3, [r7, #0] 8007fcc: 791b ldrb r3, [r3, #4] 8007fce: 049b lsls r3, r3, #18 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8007fd0: 4319 orrs r1, r3 ((uint32_t)ep->type << 18) | (epnum << 22) | 8007fd2: 68bb ldr r3, [r7, #8] 8007fd4: 059b lsls r3, r3, #22 8007fd6: 430b orrs r3, r1 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8007fd8: 4313 orrs r3, r2 8007fda: 68ba ldr r2, [r7, #8] 8007fdc: 0151 lsls r1, r2, #5 8007fde: 68fa ldr r2, [r7, #12] 8007fe0: 440a add r2, r1 8007fe2: f502 6210 add.w r2, r2, #2304 @ 0x900 8007fe6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8007fea: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8007fee: 6013 str r3, [r2, #0] 8007ff0: e036 b.n 8008060 USB_OTG_DIEPCTL_USBAEP; } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); 8007ff2: 68fb ldr r3, [r7, #12] 8007ff4: f503 6300 add.w r3, r3, #2048 @ 0x800 8007ff8: 69da ldr r2, [r3, #28] 8007ffa: 683b ldr r3, [r7, #0] 8007ffc: 781b ldrb r3, [r3, #0] 8007ffe: f003 030f and.w r3, r3, #15 8008002: 2101 movs r1, #1 8008004: fa01 f303 lsl.w r3, r1, r3 8008008: 041b lsls r3, r3, #16 800800a: 68f9 ldr r1, [r7, #12] 800800c: f501 6100 add.w r1, r1, #2048 @ 0x800 8008010: 4313 orrs r3, r2 8008012: 61cb str r3, [r1, #28] if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) 8008014: 68bb ldr r3, [r7, #8] 8008016: 015a lsls r2, r3, #5 8008018: 68fb ldr r3, [r7, #12] 800801a: 4413 add r3, r2 800801c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008020: 681b ldr r3, [r3, #0] 8008022: f403 4300 and.w r3, r3, #32768 @ 0x8000 8008026: 2b00 cmp r3, #0 8008028: d11a bne.n 8008060 { USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 800802a: 68bb ldr r3, [r7, #8] 800802c: 015a lsls r2, r3, #5 800802e: 68fb ldr r3, [r7, #12] 8008030: 4413 add r3, r2 8008032: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008036: 681a ldr r2, [r3, #0] 8008038: 683b ldr r3, [r7, #0] 800803a: 689b ldr r3, [r3, #8] 800803c: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | 8008040: 683b ldr r3, [r7, #0] 8008042: 791b ldrb r3, [r3, #4] 8008044: 049b lsls r3, r3, #18 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 8008046: 430b orrs r3, r1 8008048: 4313 orrs r3, r2 800804a: 68ba ldr r2, [r7, #8] 800804c: 0151 lsls r1, r2, #5 800804e: 68fa ldr r2, [r7, #12] 8008050: 440a add r2, r1 8008052: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008056: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800805a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800805e: 6013 str r3, [r2, #0] USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; 8008060: 2300 movs r3, #0 } 8008062: 4618 mov r0, r3 8008064: 3714 adds r7, #20 8008066: 46bd mov sp, r7 8008068: f85d 7b04 ldr.w r7, [sp], #4 800806c: 4770 bx lr ... 08008070 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8008070: b480 push {r7} 8008072: b085 sub sp, #20 8008074: af00 add r7, sp, #0 8008076: 6078 str r0, [r7, #4] 8008078: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 800807a: 687b ldr r3, [r7, #4] 800807c: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 800807e: 683b ldr r3, [r7, #0] 8008080: 781b ldrb r3, [r3, #0] 8008082: 60bb str r3, [r7, #8] /* Read DEPCTLn register */ if (ep->is_in == 1U) 8008084: 683b ldr r3, [r7, #0] 8008086: 785b ldrb r3, [r3, #1] 8008088: 2b01 cmp r3, #1 800808a: d161 bne.n 8008150 { if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 800808c: 68bb ldr r3, [r7, #8] 800808e: 015a lsls r2, r3, #5 8008090: 68fb ldr r3, [r7, #12] 8008092: 4413 add r3, r2 8008094: f503 6310 add.w r3, r3, #2304 @ 0x900 8008098: 681b ldr r3, [r3, #0] 800809a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800809e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80080a2: d11f bne.n 80080e4 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 80080a4: 68bb ldr r3, [r7, #8] 80080a6: 015a lsls r2, r3, #5 80080a8: 68fb ldr r3, [r7, #12] 80080aa: 4413 add r3, r2 80080ac: f503 6310 add.w r3, r3, #2304 @ 0x900 80080b0: 681b ldr r3, [r3, #0] 80080b2: 68ba ldr r2, [r7, #8] 80080b4: 0151 lsls r1, r2, #5 80080b6: 68fa ldr r2, [r7, #12] 80080b8: 440a add r2, r1 80080ba: f502 6210 add.w r2, r2, #2304 @ 0x900 80080be: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 80080c2: 6013 str r3, [r2, #0] USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; 80080c4: 68bb ldr r3, [r7, #8] 80080c6: 015a lsls r2, r3, #5 80080c8: 68fb ldr r3, [r7, #12] 80080ca: 4413 add r3, r2 80080cc: f503 6310 add.w r3, r3, #2304 @ 0x900 80080d0: 681b ldr r3, [r3, #0] 80080d2: 68ba ldr r2, [r7, #8] 80080d4: 0151 lsls r1, r2, #5 80080d6: 68fa ldr r2, [r7, #12] 80080d8: 440a add r2, r1 80080da: f502 6210 add.w r2, r2, #2304 @ 0x900 80080de: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80080e2: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 80080e4: 68fb ldr r3, [r7, #12] 80080e6: f503 6300 add.w r3, r3, #2048 @ 0x800 80080ea: 6bda ldr r2, [r3, #60] @ 0x3c 80080ec: 683b ldr r3, [r7, #0] 80080ee: 781b ldrb r3, [r3, #0] 80080f0: f003 030f and.w r3, r3, #15 80080f4: 2101 movs r1, #1 80080f6: fa01 f303 lsl.w r3, r1, r3 80080fa: b29b uxth r3, r3 80080fc: 43db mvns r3, r3 80080fe: 68f9 ldr r1, [r7, #12] 8008100: f501 6100 add.w r1, r1, #2048 @ 0x800 8008104: 4013 ands r3, r2 8008106: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 8008108: 68fb ldr r3, [r7, #12] 800810a: f503 6300 add.w r3, r3, #2048 @ 0x800 800810e: 69da ldr r2, [r3, #28] 8008110: 683b ldr r3, [r7, #0] 8008112: 781b ldrb r3, [r3, #0] 8008114: f003 030f and.w r3, r3, #15 8008118: 2101 movs r1, #1 800811a: fa01 f303 lsl.w r3, r1, r3 800811e: b29b uxth r3, r3 8008120: 43db mvns r3, r3 8008122: 68f9 ldr r1, [r7, #12] 8008124: f501 6100 add.w r1, r1, #2048 @ 0x800 8008128: 4013 ands r3, r2 800812a: 61cb str r3, [r1, #28] USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | 800812c: 68bb ldr r3, [r7, #8] 800812e: 015a lsls r2, r3, #5 8008130: 68fb ldr r3, [r7, #12] 8008132: 4413 add r3, r2 8008134: f503 6310 add.w r3, r3, #2304 @ 0x900 8008138: 681a ldr r2, [r3, #0] 800813a: 68bb ldr r3, [r7, #8] 800813c: 0159 lsls r1, r3, #5 800813e: 68fb ldr r3, [r7, #12] 8008140: 440b add r3, r1 8008142: f503 6310 add.w r3, r3, #2304 @ 0x900 8008146: 4619 mov r1, r3 8008148: 4b35 ldr r3, [pc, #212] @ (8008220 ) 800814a: 4013 ands r3, r2 800814c: 600b str r3, [r1, #0] 800814e: e060 b.n 8008212 USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_EPTYP); } else { if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8008150: 68bb ldr r3, [r7, #8] 8008152: 015a lsls r2, r3, #5 8008154: 68fb ldr r3, [r7, #12] 8008156: 4413 add r3, r2 8008158: f503 6330 add.w r3, r3, #2816 @ 0xb00 800815c: 681b ldr r3, [r3, #0] 800815e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008162: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008166: d11f bne.n 80081a8 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 8008168: 68bb ldr r3, [r7, #8] 800816a: 015a lsls r2, r3, #5 800816c: 68fb ldr r3, [r7, #12] 800816e: 4413 add r3, r2 8008170: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008174: 681b ldr r3, [r3, #0] 8008176: 68ba ldr r2, [r7, #8] 8008178: 0151 lsls r1, r2, #5 800817a: 68fa ldr r2, [r7, #12] 800817c: 440a add r2, r1 800817e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008182: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8008186: 6013 str r3, [r2, #0] USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; 8008188: 68bb ldr r3, [r7, #8] 800818a: 015a lsls r2, r3, #5 800818c: 68fb ldr r3, [r7, #12] 800818e: 4413 add r3, r2 8008190: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008194: 681b ldr r3, [r3, #0] 8008196: 68ba ldr r2, [r7, #8] 8008198: 0151 lsls r1, r2, #5 800819a: 68fa ldr r2, [r7, #12] 800819c: 440a add r2, r1 800819e: f502 6230 add.w r2, r2, #2816 @ 0xb00 80081a2: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80081a6: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 80081a8: 68fb ldr r3, [r7, #12] 80081aa: f503 6300 add.w r3, r3, #2048 @ 0x800 80081ae: 6bda ldr r2, [r3, #60] @ 0x3c 80081b0: 683b ldr r3, [r7, #0] 80081b2: 781b ldrb r3, [r3, #0] 80081b4: f003 030f and.w r3, r3, #15 80081b8: 2101 movs r1, #1 80081ba: fa01 f303 lsl.w r3, r1, r3 80081be: 041b lsls r3, r3, #16 80081c0: 43db mvns r3, r3 80081c2: 68f9 ldr r1, [r7, #12] 80081c4: f501 6100 add.w r1, r1, #2048 @ 0x800 80081c8: 4013 ands r3, r2 80081ca: 63cb str r3, [r1, #60] @ 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 80081cc: 68fb ldr r3, [r7, #12] 80081ce: f503 6300 add.w r3, r3, #2048 @ 0x800 80081d2: 69da ldr r2, [r3, #28] 80081d4: 683b ldr r3, [r7, #0] 80081d6: 781b ldrb r3, [r3, #0] 80081d8: f003 030f and.w r3, r3, #15 80081dc: 2101 movs r1, #1 80081de: fa01 f303 lsl.w r3, r1, r3 80081e2: 041b lsls r3, r3, #16 80081e4: 43db mvns r3, r3 80081e6: 68f9 ldr r1, [r7, #12] 80081e8: f501 6100 add.w r1, r1, #2048 @ 0x800 80081ec: 4013 ands r3, r2 80081ee: 61cb str r3, [r1, #28] USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | 80081f0: 68bb ldr r3, [r7, #8] 80081f2: 015a lsls r2, r3, #5 80081f4: 68fb ldr r3, [r7, #12] 80081f6: 4413 add r3, r2 80081f8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80081fc: 681a ldr r2, [r3, #0] 80081fe: 68bb ldr r3, [r7, #8] 8008200: 0159 lsls r1, r3, #5 8008202: 68fb ldr r3, [r7, #12] 8008204: 440b add r3, r1 8008206: f503 6330 add.w r3, r3, #2816 @ 0xb00 800820a: 4619 mov r1, r3 800820c: 4b05 ldr r3, [pc, #20] @ (8008224 ) 800820e: 4013 ands r3, r2 8008210: 600b str r3, [r1, #0] USB_OTG_DOEPCTL_MPSIZ | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_EPTYP); } return HAL_OK; 8008212: 2300 movs r3, #0 } 8008214: 4618 mov r0, r3 8008216: 3714 adds r7, #20 8008218: 46bd mov sp, r7 800821a: f85d 7b04 ldr.w r7, [sp], #4 800821e: 4770 bx lr 8008220: ec337800 .word 0xec337800 8008224: eff37800 .word 0xeff37800 08008228 : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 8008228: b580 push {r7, lr} 800822a: b08a sub sp, #40 @ 0x28 800822c: af02 add r7, sp, #8 800822e: 60f8 str r0, [r7, #12] 8008230: 60b9 str r1, [r7, #8] 8008232: 4613 mov r3, r2 8008234: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 8008236: 68fb ldr r3, [r7, #12] 8008238: 61fb str r3, [r7, #28] uint32_t epnum = (uint32_t)ep->num; 800823a: 68bb ldr r3, [r7, #8] 800823c: 781b ldrb r3, [r3, #0] 800823e: 61bb str r3, [r7, #24] uint16_t pktcnt; /* IN endpoint */ if (ep->is_in == 1U) 8008240: 68bb ldr r3, [r7, #8] 8008242: 785b ldrb r3, [r3, #1] 8008244: 2b01 cmp r3, #1 8008246: f040 817f bne.w 8008548 { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 800824a: 68bb ldr r3, [r7, #8] 800824c: 691b ldr r3, [r3, #16] 800824e: 2b00 cmp r3, #0 8008250: d132 bne.n 80082b8 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8008252: 69bb ldr r3, [r7, #24] 8008254: 015a lsls r2, r3, #5 8008256: 69fb ldr r3, [r7, #28] 8008258: 4413 add r3, r2 800825a: f503 6310 add.w r3, r3, #2304 @ 0x900 800825e: 691b ldr r3, [r3, #16] 8008260: 69ba ldr r2, [r7, #24] 8008262: 0151 lsls r1, r2, #5 8008264: 69fa ldr r2, [r7, #28] 8008266: 440a add r2, r1 8008268: f502 6210 add.w r2, r2, #2304 @ 0x900 800826c: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8008270: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 8008274: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8008276: 69bb ldr r3, [r7, #24] 8008278: 015a lsls r2, r3, #5 800827a: 69fb ldr r3, [r7, #28] 800827c: 4413 add r3, r2 800827e: f503 6310 add.w r3, r3, #2304 @ 0x900 8008282: 691b ldr r3, [r3, #16] 8008284: 69ba ldr r2, [r7, #24] 8008286: 0151 lsls r1, r2, #5 8008288: 69fa ldr r2, [r7, #28] 800828a: 440a add r2, r1 800828c: f502 6210 add.w r2, r2, #2304 @ 0x900 8008290: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8008294: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8008296: 69bb ldr r3, [r7, #24] 8008298: 015a lsls r2, r3, #5 800829a: 69fb ldr r3, [r7, #28] 800829c: 4413 add r3, r2 800829e: f503 6310 add.w r3, r3, #2304 @ 0x900 80082a2: 691b ldr r3, [r3, #16] 80082a4: 69ba ldr r2, [r7, #24] 80082a6: 0151 lsls r1, r2, #5 80082a8: 69fa ldr r2, [r7, #28] 80082aa: 440a add r2, r1 80082ac: f502 6210 add.w r2, r2, #2304 @ 0x900 80082b0: 0cdb lsrs r3, r3, #19 80082b2: 04db lsls r3, r3, #19 80082b4: 6113 str r3, [r2, #16] 80082b6: e097 b.n 80083e8 /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 80082b8: 69bb ldr r3, [r7, #24] 80082ba: 015a lsls r2, r3, #5 80082bc: 69fb ldr r3, [r7, #28] 80082be: 4413 add r3, r2 80082c0: f503 6310 add.w r3, r3, #2304 @ 0x900 80082c4: 691b ldr r3, [r3, #16] 80082c6: 69ba ldr r2, [r7, #24] 80082c8: 0151 lsls r1, r2, #5 80082ca: 69fa ldr r2, [r7, #28] 80082cc: 440a add r2, r1 80082ce: f502 6210 add.w r2, r2, #2304 @ 0x900 80082d2: 0cdb lsrs r3, r3, #19 80082d4: 04db lsls r3, r3, #19 80082d6: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 80082d8: 69bb ldr r3, [r7, #24] 80082da: 015a lsls r2, r3, #5 80082dc: 69fb ldr r3, [r7, #28] 80082de: 4413 add r3, r2 80082e0: f503 6310 add.w r3, r3, #2304 @ 0x900 80082e4: 691b ldr r3, [r3, #16] 80082e6: 69ba ldr r2, [r7, #24] 80082e8: 0151 lsls r1, r2, #5 80082ea: 69fa ldr r2, [r7, #28] 80082ec: 440a add r2, r1 80082ee: f502 6210 add.w r2, r2, #2304 @ 0x900 80082f2: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 80082f6: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 80082fa: 6113 str r3, [r2, #16] if (epnum == 0U) 80082fc: 69bb ldr r3, [r7, #24] 80082fe: 2b00 cmp r3, #0 8008300: d11a bne.n 8008338 { if (ep->xfer_len > ep->maxpacket) 8008302: 68bb ldr r3, [r7, #8] 8008304: 691a ldr r2, [r3, #16] 8008306: 68bb ldr r3, [r7, #8] 8008308: 689b ldr r3, [r3, #8] 800830a: 429a cmp r2, r3 800830c: d903 bls.n 8008316 { ep->xfer_len = ep->maxpacket; 800830e: 68bb ldr r3, [r7, #8] 8008310: 689a ldr r2, [r3, #8] 8008312: 68bb ldr r3, [r7, #8] 8008314: 611a str r2, [r3, #16] } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8008316: 69bb ldr r3, [r7, #24] 8008318: 015a lsls r2, r3, #5 800831a: 69fb ldr r3, [r7, #28] 800831c: 4413 add r3, r2 800831e: f503 6310 add.w r3, r3, #2304 @ 0x900 8008322: 691b ldr r3, [r3, #16] 8008324: 69ba ldr r2, [r7, #24] 8008326: 0151 lsls r1, r2, #5 8008328: 69fa ldr r2, [r7, #28] 800832a: 440a add r2, r1 800832c: f502 6210 add.w r2, r2, #2304 @ 0x900 8008330: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8008334: 6113 str r3, [r2, #16] 8008336: e044 b.n 80083c2 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8008338: 68bb ldr r3, [r7, #8] 800833a: 691a ldr r2, [r3, #16] 800833c: 68bb ldr r3, [r7, #8] 800833e: 689b ldr r3, [r3, #8] 8008340: 4413 add r3, r2 8008342: 1e5a subs r2, r3, #1 8008344: 68bb ldr r3, [r7, #8] 8008346: 689b ldr r3, [r3, #8] 8008348: fbb2 f3f3 udiv r3, r2, r3 800834c: 82fb strh r3, [r7, #22] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); 800834e: 69bb ldr r3, [r7, #24] 8008350: 015a lsls r2, r3, #5 8008352: 69fb ldr r3, [r7, #28] 8008354: 4413 add r3, r2 8008356: f503 6310 add.w r3, r3, #2304 @ 0x900 800835a: 691a ldr r2, [r3, #16] 800835c: 8afb ldrh r3, [r7, #22] 800835e: 04d9 lsls r1, r3, #19 8008360: 4ba4 ldr r3, [pc, #656] @ (80085f4 ) 8008362: 400b ands r3, r1 8008364: 69b9 ldr r1, [r7, #24] 8008366: 0148 lsls r0, r1, #5 8008368: 69f9 ldr r1, [r7, #28] 800836a: 4401 add r1, r0 800836c: f501 6110 add.w r1, r1, #2304 @ 0x900 8008370: 4313 orrs r3, r2 8008372: 610b str r3, [r1, #16] if (ep->type == EP_TYPE_ISOC) 8008374: 68bb ldr r3, [r7, #8] 8008376: 791b ldrb r3, [r3, #4] 8008378: 2b01 cmp r3, #1 800837a: d122 bne.n 80083c2 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 800837c: 69bb ldr r3, [r7, #24] 800837e: 015a lsls r2, r3, #5 8008380: 69fb ldr r3, [r7, #28] 8008382: 4413 add r3, r2 8008384: f503 6310 add.w r3, r3, #2304 @ 0x900 8008388: 691b ldr r3, [r3, #16] 800838a: 69ba ldr r2, [r7, #24] 800838c: 0151 lsls r1, r2, #5 800838e: 69fa ldr r2, [r7, #28] 8008390: 440a add r2, r1 8008392: f502 6210 add.w r2, r2, #2304 @ 0x900 8008396: f023 43c0 bic.w r3, r3, #1610612736 @ 0x60000000 800839a: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); 800839c: 69bb ldr r3, [r7, #24] 800839e: 015a lsls r2, r3, #5 80083a0: 69fb ldr r3, [r7, #28] 80083a2: 4413 add r3, r2 80083a4: f503 6310 add.w r3, r3, #2304 @ 0x900 80083a8: 691a ldr r2, [r3, #16] 80083aa: 8afb ldrh r3, [r7, #22] 80083ac: 075b lsls r3, r3, #29 80083ae: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000 80083b2: 69b9 ldr r1, [r7, #24] 80083b4: 0148 lsls r0, r1, #5 80083b6: 69f9 ldr r1, [r7, #28] 80083b8: 4401 add r1, r0 80083ba: f501 6110 add.w r1, r1, #2304 @ 0x900 80083be: 4313 orrs r3, r2 80083c0: 610b str r3, [r1, #16] } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 80083c2: 69bb ldr r3, [r7, #24] 80083c4: 015a lsls r2, r3, #5 80083c6: 69fb ldr r3, [r7, #28] 80083c8: 4413 add r3, r2 80083ca: f503 6310 add.w r3, r3, #2304 @ 0x900 80083ce: 691a ldr r2, [r3, #16] 80083d0: 68bb ldr r3, [r7, #8] 80083d2: 691b ldr r3, [r3, #16] 80083d4: f3c3 0312 ubfx r3, r3, #0, #19 80083d8: 69b9 ldr r1, [r7, #24] 80083da: 0148 lsls r0, r1, #5 80083dc: 69f9 ldr r1, [r7, #28] 80083de: 4401 add r1, r0 80083e0: f501 6110 add.w r1, r1, #2304 @ 0x900 80083e4: 4313 orrs r3, r2 80083e6: 610b str r3, [r1, #16] } if (dma == 1U) 80083e8: 79fb ldrb r3, [r7, #7] 80083ea: 2b01 cmp r3, #1 80083ec: d14b bne.n 8008486 { if ((uint32_t)ep->dma_addr != 0U) 80083ee: 68bb ldr r3, [r7, #8] 80083f0: 69db ldr r3, [r3, #28] 80083f2: 2b00 cmp r3, #0 80083f4: d009 beq.n 800840a { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 80083f6: 69bb ldr r3, [r7, #24] 80083f8: 015a lsls r2, r3, #5 80083fa: 69fb ldr r3, [r7, #28] 80083fc: 4413 add r3, r2 80083fe: f503 6310 add.w r3, r3, #2304 @ 0x900 8008402: 461a mov r2, r3 8008404: 68bb ldr r3, [r7, #8] 8008406: 69db ldr r3, [r3, #28] 8008408: 6153 str r3, [r2, #20] } if (ep->type == EP_TYPE_ISOC) 800840a: 68bb ldr r3, [r7, #8] 800840c: 791b ldrb r3, [r3, #4] 800840e: 2b01 cmp r3, #1 8008410: d128 bne.n 8008464 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8008412: 69fb ldr r3, [r7, #28] 8008414: f503 6300 add.w r3, r3, #2048 @ 0x800 8008418: 689b ldr r3, [r3, #8] 800841a: f403 7380 and.w r3, r3, #256 @ 0x100 800841e: 2b00 cmp r3, #0 8008420: d110 bne.n 8008444 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8008422: 69bb ldr r3, [r7, #24] 8008424: 015a lsls r2, r3, #5 8008426: 69fb ldr r3, [r7, #28] 8008428: 4413 add r3, r2 800842a: f503 6310 add.w r3, r3, #2304 @ 0x900 800842e: 681b ldr r3, [r3, #0] 8008430: 69ba ldr r2, [r7, #24] 8008432: 0151 lsls r1, r2, #5 8008434: 69fa ldr r2, [r7, #28] 8008436: 440a add r2, r1 8008438: f502 6210 add.w r2, r2, #2304 @ 0x900 800843c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8008440: 6013 str r3, [r2, #0] 8008442: e00f b.n 8008464 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8008444: 69bb ldr r3, [r7, #24] 8008446: 015a lsls r2, r3, #5 8008448: 69fb ldr r3, [r7, #28] 800844a: 4413 add r3, r2 800844c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008450: 681b ldr r3, [r3, #0] 8008452: 69ba ldr r2, [r7, #24] 8008454: 0151 lsls r1, r2, #5 8008456: 69fa ldr r2, [r7, #28] 8008458: 440a add r2, r1 800845a: f502 6210 add.w r2, r2, #2304 @ 0x900 800845e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008462: 6013 str r3, [r2, #0] } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8008464: 69bb ldr r3, [r7, #24] 8008466: 015a lsls r2, r3, #5 8008468: 69fb ldr r3, [r7, #28] 800846a: 4413 add r3, r2 800846c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008470: 681b ldr r3, [r3, #0] 8008472: 69ba ldr r2, [r7, #24] 8008474: 0151 lsls r1, r2, #5 8008476: 69fa ldr r2, [r7, #28] 8008478: 440a add r2, r1 800847a: f502 6210 add.w r2, r2, #2304 @ 0x900 800847e: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8008482: 6013 str r3, [r2, #0] 8008484: e166 b.n 8008754 } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8008486: 69bb ldr r3, [r7, #24] 8008488: 015a lsls r2, r3, #5 800848a: 69fb ldr r3, [r7, #28] 800848c: 4413 add r3, r2 800848e: f503 6310 add.w r3, r3, #2304 @ 0x900 8008492: 681b ldr r3, [r3, #0] 8008494: 69ba ldr r2, [r7, #24] 8008496: 0151 lsls r1, r2, #5 8008498: 69fa ldr r2, [r7, #28] 800849a: 440a add r2, r1 800849c: f502 6210 add.w r2, r2, #2304 @ 0x900 80084a0: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 80084a4: 6013 str r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 80084a6: 68bb ldr r3, [r7, #8] 80084a8: 791b ldrb r3, [r3, #4] 80084aa: 2b01 cmp r3, #1 80084ac: d015 beq.n 80084da { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 80084ae: 68bb ldr r3, [r7, #8] 80084b0: 691b ldr r3, [r3, #16] 80084b2: 2b00 cmp r3, #0 80084b4: f000 814e beq.w 8008754 { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 80084b8: 69fb ldr r3, [r7, #28] 80084ba: f503 6300 add.w r3, r3, #2048 @ 0x800 80084be: 6b5a ldr r2, [r3, #52] @ 0x34 80084c0: 68bb ldr r3, [r7, #8] 80084c2: 781b ldrb r3, [r3, #0] 80084c4: f003 030f and.w r3, r3, #15 80084c8: 2101 movs r1, #1 80084ca: fa01 f303 lsl.w r3, r1, r3 80084ce: 69f9 ldr r1, [r7, #28] 80084d0: f501 6100 add.w r1, r1, #2048 @ 0x800 80084d4: 4313 orrs r3, r2 80084d6: 634b str r3, [r1, #52] @ 0x34 80084d8: e13c b.n 8008754 } } else { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 80084da: 69fb ldr r3, [r7, #28] 80084dc: f503 6300 add.w r3, r3, #2048 @ 0x800 80084e0: 689b ldr r3, [r3, #8] 80084e2: f403 7380 and.w r3, r3, #256 @ 0x100 80084e6: 2b00 cmp r3, #0 80084e8: d110 bne.n 800850c { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 80084ea: 69bb ldr r3, [r7, #24] 80084ec: 015a lsls r2, r3, #5 80084ee: 69fb ldr r3, [r7, #28] 80084f0: 4413 add r3, r2 80084f2: f503 6310 add.w r3, r3, #2304 @ 0x900 80084f6: 681b ldr r3, [r3, #0] 80084f8: 69ba ldr r2, [r7, #24] 80084fa: 0151 lsls r1, r2, #5 80084fc: 69fa ldr r2, [r7, #28] 80084fe: 440a add r2, r1 8008500: f502 6210 add.w r2, r2, #2304 @ 0x900 8008504: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8008508: 6013 str r3, [r2, #0] 800850a: e00f b.n 800852c } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 800850c: 69bb ldr r3, [r7, #24] 800850e: 015a lsls r2, r3, #5 8008510: 69fb ldr r3, [r7, #28] 8008512: 4413 add r3, r2 8008514: f503 6310 add.w r3, r3, #2304 @ 0x900 8008518: 681b ldr r3, [r3, #0] 800851a: 69ba ldr r2, [r7, #24] 800851c: 0151 lsls r1, r2, #5 800851e: 69fa ldr r2, [r7, #28] 8008520: 440a add r2, r1 8008522: f502 6210 add.w r2, r2, #2304 @ 0x900 8008526: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800852a: 6013 str r3, [r2, #0] } (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); 800852c: 68bb ldr r3, [r7, #8] 800852e: 68d9 ldr r1, [r3, #12] 8008530: 68bb ldr r3, [r7, #8] 8008532: 781a ldrb r2, [r3, #0] 8008534: 68bb ldr r3, [r7, #8] 8008536: 691b ldr r3, [r3, #16] 8008538: b298 uxth r0, r3 800853a: 79fb ldrb r3, [r7, #7] 800853c: 9300 str r3, [sp, #0] 800853e: 4603 mov r3, r0 8008540: 68f8 ldr r0, [r7, #12] 8008542: f000 f9b9 bl 80088b8 8008546: e105 b.n 8008754 { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 8008548: 69bb ldr r3, [r7, #24] 800854a: 015a lsls r2, r3, #5 800854c: 69fb ldr r3, [r7, #28] 800854e: 4413 add r3, r2 8008550: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008554: 691b ldr r3, [r3, #16] 8008556: 69ba ldr r2, [r7, #24] 8008558: 0151 lsls r1, r2, #5 800855a: 69fa ldr r2, [r7, #28] 800855c: 440a add r2, r1 800855e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008562: 0cdb lsrs r3, r3, #19 8008564: 04db lsls r3, r3, #19 8008566: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 8008568: 69bb ldr r3, [r7, #24] 800856a: 015a lsls r2, r3, #5 800856c: 69fb ldr r3, [r7, #28] 800856e: 4413 add r3, r2 8008570: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008574: 691b ldr r3, [r3, #16] 8008576: 69ba ldr r2, [r7, #24] 8008578: 0151 lsls r1, r2, #5 800857a: 69fa ldr r2, [r7, #28] 800857c: 440a add r2, r1 800857e: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008582: f023 53ff bic.w r3, r3, #534773760 @ 0x1fe00000 8008586: f423 13c0 bic.w r3, r3, #1572864 @ 0x180000 800858a: 6113 str r3, [r2, #16] if (epnum == 0U) 800858c: 69bb ldr r3, [r7, #24] 800858e: 2b00 cmp r3, #0 8008590: d132 bne.n 80085f8 { if (ep->xfer_len > 0U) 8008592: 68bb ldr r3, [r7, #8] 8008594: 691b ldr r3, [r3, #16] 8008596: 2b00 cmp r3, #0 8008598: d003 beq.n 80085a2 { ep->xfer_len = ep->maxpacket; 800859a: 68bb ldr r3, [r7, #8] 800859c: 689a ldr r2, [r3, #8] 800859e: 68bb ldr r3, [r7, #8] 80085a0: 611a str r2, [r3, #16] } /* Store transfer size, for EP0 this is equal to endpoint max packet size */ ep->xfer_size = ep->maxpacket; 80085a2: 68bb ldr r3, [r7, #8] 80085a4: 689a ldr r2, [r3, #8] 80085a6: 68bb ldr r3, [r7, #8] 80085a8: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); 80085aa: 69bb ldr r3, [r7, #24] 80085ac: 015a lsls r2, r3, #5 80085ae: 69fb ldr r3, [r7, #28] 80085b0: 4413 add r3, r2 80085b2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80085b6: 691a ldr r2, [r3, #16] 80085b8: 68bb ldr r3, [r7, #8] 80085ba: 6a1b ldr r3, [r3, #32] 80085bc: f3c3 0312 ubfx r3, r3, #0, #19 80085c0: 69b9 ldr r1, [r7, #24] 80085c2: 0148 lsls r0, r1, #5 80085c4: 69f9 ldr r1, [r7, #28] 80085c6: 4401 add r1, r0 80085c8: f501 6130 add.w r1, r1, #2816 @ 0xb00 80085cc: 4313 orrs r3, r2 80085ce: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 80085d0: 69bb ldr r3, [r7, #24] 80085d2: 015a lsls r2, r3, #5 80085d4: 69fb ldr r3, [r7, #28] 80085d6: 4413 add r3, r2 80085d8: f503 6330 add.w r3, r3, #2816 @ 0xb00 80085dc: 691b ldr r3, [r3, #16] 80085de: 69ba ldr r2, [r7, #24] 80085e0: 0151 lsls r1, r2, #5 80085e2: 69fa ldr r2, [r7, #28] 80085e4: 440a add r2, r1 80085e6: f502 6230 add.w r2, r2, #2816 @ 0xb00 80085ea: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80085ee: 6113 str r3, [r2, #16] 80085f0: e062 b.n 80086b8 80085f2: bf00 nop 80085f4: 1ff80000 .word 0x1ff80000 } else { if (ep->xfer_len == 0U) 80085f8: 68bb ldr r3, [r7, #8] 80085fa: 691b ldr r3, [r3, #16] 80085fc: 2b00 cmp r3, #0 80085fe: d123 bne.n 8008648 { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 8008600: 69bb ldr r3, [r7, #24] 8008602: 015a lsls r2, r3, #5 8008604: 69fb ldr r3, [r7, #28] 8008606: 4413 add r3, r2 8008608: f503 6330 add.w r3, r3, #2816 @ 0xb00 800860c: 691a ldr r2, [r3, #16] 800860e: 68bb ldr r3, [r7, #8] 8008610: 689b ldr r3, [r3, #8] 8008612: f3c3 0312 ubfx r3, r3, #0, #19 8008616: 69b9 ldr r1, [r7, #24] 8008618: 0148 lsls r0, r1, #5 800861a: 69f9 ldr r1, [r7, #28] 800861c: 4401 add r1, r0 800861e: f501 6130 add.w r1, r1, #2816 @ 0xb00 8008622: 4313 orrs r3, r2 8008624: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8008626: 69bb ldr r3, [r7, #24] 8008628: 015a lsls r2, r3, #5 800862a: 69fb ldr r3, [r7, #28] 800862c: 4413 add r3, r2 800862e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008632: 691b ldr r3, [r3, #16] 8008634: 69ba ldr r2, [r7, #24] 8008636: 0151 lsls r1, r2, #5 8008638: 69fa ldr r2, [r7, #28] 800863a: 440a add r2, r1 800863c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008640: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8008644: 6113 str r3, [r2, #16] 8008646: e037 b.n 80086b8 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 8008648: 68bb ldr r3, [r7, #8] 800864a: 691a ldr r2, [r3, #16] 800864c: 68bb ldr r3, [r7, #8] 800864e: 689b ldr r3, [r3, #8] 8008650: 4413 add r3, r2 8008652: 1e5a subs r2, r3, #1 8008654: 68bb ldr r3, [r7, #8] 8008656: 689b ldr r3, [r3, #8] 8008658: fbb2 f3f3 udiv r3, r2, r3 800865c: 82fb strh r3, [r7, #22] ep->xfer_size = ep->maxpacket * pktcnt; 800865e: 68bb ldr r3, [r7, #8] 8008660: 689b ldr r3, [r3, #8] 8008662: 8afa ldrh r2, [r7, #22] 8008664: fb03 f202 mul.w r2, r3, r2 8008668: 68bb ldr r3, [r7, #8] 800866a: 621a str r2, [r3, #32] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); 800866c: 69bb ldr r3, [r7, #24] 800866e: 015a lsls r2, r3, #5 8008670: 69fb ldr r3, [r7, #28] 8008672: 4413 add r3, r2 8008674: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008678: 691a ldr r2, [r3, #16] 800867a: 8afb ldrh r3, [r7, #22] 800867c: 04d9 lsls r1, r3, #19 800867e: 4b38 ldr r3, [pc, #224] @ (8008760 ) 8008680: 400b ands r3, r1 8008682: 69b9 ldr r1, [r7, #24] 8008684: 0148 lsls r0, r1, #5 8008686: 69f9 ldr r1, [r7, #28] 8008688: 4401 add r1, r0 800868a: f501 6130 add.w r1, r1, #2816 @ 0xb00 800868e: 4313 orrs r3, r2 8008690: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; 8008692: 69bb ldr r3, [r7, #24] 8008694: 015a lsls r2, r3, #5 8008696: 69fb ldr r3, [r7, #28] 8008698: 4413 add r3, r2 800869a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800869e: 691a ldr r2, [r3, #16] 80086a0: 68bb ldr r3, [r7, #8] 80086a2: 6a1b ldr r3, [r3, #32] 80086a4: f3c3 0312 ubfx r3, r3, #0, #19 80086a8: 69b9 ldr r1, [r7, #24] 80086aa: 0148 lsls r0, r1, #5 80086ac: 69f9 ldr r1, [r7, #28] 80086ae: 4401 add r1, r0 80086b0: f501 6130 add.w r1, r1, #2816 @ 0xb00 80086b4: 4313 orrs r3, r2 80086b6: 610b str r3, [r1, #16] } } if (dma == 1U) 80086b8: 79fb ldrb r3, [r7, #7] 80086ba: 2b01 cmp r3, #1 80086bc: d10d bne.n 80086da { if ((uint32_t)ep->xfer_buff != 0U) 80086be: 68bb ldr r3, [r7, #8] 80086c0: 68db ldr r3, [r3, #12] 80086c2: 2b00 cmp r3, #0 80086c4: d009 beq.n 80086da { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 80086c6: 68bb ldr r3, [r7, #8] 80086c8: 68d9 ldr r1, [r3, #12] 80086ca: 69bb ldr r3, [r7, #24] 80086cc: 015a lsls r2, r3, #5 80086ce: 69fb ldr r3, [r7, #28] 80086d0: 4413 add r3, r2 80086d2: f503 6330 add.w r3, r3, #2816 @ 0xb00 80086d6: 460a mov r2, r1 80086d8: 615a str r2, [r3, #20] } } if (ep->type == EP_TYPE_ISOC) 80086da: 68bb ldr r3, [r7, #8] 80086dc: 791b ldrb r3, [r3, #4] 80086de: 2b01 cmp r3, #1 80086e0: d128 bne.n 8008734 { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 80086e2: 69fb ldr r3, [r7, #28] 80086e4: f503 6300 add.w r3, r3, #2048 @ 0x800 80086e8: 689b ldr r3, [r3, #8] 80086ea: f403 7380 and.w r3, r3, #256 @ 0x100 80086ee: 2b00 cmp r3, #0 80086f0: d110 bne.n 8008714 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 80086f2: 69bb ldr r3, [r7, #24] 80086f4: 015a lsls r2, r3, #5 80086f6: 69fb ldr r3, [r7, #28] 80086f8: 4413 add r3, r2 80086fa: f503 6330 add.w r3, r3, #2816 @ 0xb00 80086fe: 681b ldr r3, [r3, #0] 8008700: 69ba ldr r2, [r7, #24] 8008702: 0151 lsls r1, r2, #5 8008704: 69fa ldr r2, [r7, #28] 8008706: 440a add r2, r1 8008708: f502 6230 add.w r2, r2, #2816 @ 0xb00 800870c: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8008710: 6013 str r3, [r2, #0] 8008712: e00f b.n 8008734 } else { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 8008714: 69bb ldr r3, [r7, #24] 8008716: 015a lsls r2, r3, #5 8008718: 69fb ldr r3, [r7, #28] 800871a: 4413 add r3, r2 800871c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008720: 681b ldr r3, [r3, #0] 8008722: 69ba ldr r2, [r7, #24] 8008724: 0151 lsls r1, r2, #5 8008726: 69fa ldr r2, [r7, #28] 8008728: 440a add r2, r1 800872a: f502 6230 add.w r2, r2, #2816 @ 0xb00 800872e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008732: 6013 str r3, [r2, #0] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8008734: 69bb ldr r3, [r7, #24] 8008736: 015a lsls r2, r3, #5 8008738: 69fb ldr r3, [r7, #28] 800873a: 4413 add r3, r2 800873c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008740: 681b ldr r3, [r3, #0] 8008742: 69ba ldr r2, [r7, #24] 8008744: 0151 lsls r1, r2, #5 8008746: 69fa ldr r2, [r7, #28] 8008748: 440a add r2, r1 800874a: f502 6230 add.w r2, r2, #2816 @ 0xb00 800874e: f043 4304 orr.w r3, r3, #2214592512 @ 0x84000000 8008752: 6013 str r3, [r2, #0] } return HAL_OK; 8008754: 2300 movs r3, #0 } 8008756: 4618 mov r0, r3 8008758: 3720 adds r7, #32 800875a: 46bd mov sp, r7 800875c: bd80 pop {r7, pc} 800875e: bf00 nop 8008760: 1ff80000 .word 0x1ff80000 08008764 : * @param USBx usb device instance * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8008764: b480 push {r7} 8008766: b087 sub sp, #28 8008768: af00 add r7, sp, #0 800876a: 6078 str r0, [r7, #4] 800876c: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 800876e: 2300 movs r3, #0 8008770: 60fb str r3, [r7, #12] HAL_StatusTypeDef ret = HAL_OK; 8008772: 2300 movs r3, #0 8008774: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8008776: 687b ldr r3, [r7, #4] 8008778: 613b str r3, [r7, #16] /* IN endpoint */ if (ep->is_in == 1U) 800877a: 683b ldr r3, [r7, #0] 800877c: 785b ldrb r3, [r3, #1] 800877e: 2b01 cmp r3, #1 8008780: d14a bne.n 8008818 { /* EP enable, IN data in FIFO */ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8008782: 683b ldr r3, [r7, #0] 8008784: 781b ldrb r3, [r3, #0] 8008786: 015a lsls r2, r3, #5 8008788: 693b ldr r3, [r7, #16] 800878a: 4413 add r3, r2 800878c: f503 6310 add.w r3, r3, #2304 @ 0x900 8008790: 681b ldr r3, [r3, #0] 8008792: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008796: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800879a: f040 8086 bne.w 80088aa { USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); 800879e: 683b ldr r3, [r7, #0] 80087a0: 781b ldrb r3, [r3, #0] 80087a2: 015a lsls r2, r3, #5 80087a4: 693b ldr r3, [r7, #16] 80087a6: 4413 add r3, r2 80087a8: f503 6310 add.w r3, r3, #2304 @ 0x900 80087ac: 681b ldr r3, [r3, #0] 80087ae: 683a ldr r2, [r7, #0] 80087b0: 7812 ldrb r2, [r2, #0] 80087b2: 0151 lsls r1, r2, #5 80087b4: 693a ldr r2, [r7, #16] 80087b6: 440a add r2, r1 80087b8: f502 6210 add.w r2, r2, #2304 @ 0x900 80087bc: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 80087c0: 6013 str r3, [r2, #0] USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); 80087c2: 683b ldr r3, [r7, #0] 80087c4: 781b ldrb r3, [r3, #0] 80087c6: 015a lsls r2, r3, #5 80087c8: 693b ldr r3, [r7, #16] 80087ca: 4413 add r3, r2 80087cc: f503 6310 add.w r3, r3, #2304 @ 0x900 80087d0: 681b ldr r3, [r3, #0] 80087d2: 683a ldr r2, [r7, #0] 80087d4: 7812 ldrb r2, [r2, #0] 80087d6: 0151 lsls r1, r2, #5 80087d8: 693a ldr r2, [r7, #16] 80087da: 440a add r2, r1 80087dc: f502 6210 add.w r2, r2, #2304 @ 0x900 80087e0: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80087e4: 6013 str r3, [r2, #0] do { count++; 80087e6: 68fb ldr r3, [r7, #12] 80087e8: 3301 adds r3, #1 80087ea: 60fb str r3, [r7, #12] if (count > 10000U) 80087ec: 68fb ldr r3, [r7, #12] 80087ee: f242 7210 movw r2, #10000 @ 0x2710 80087f2: 4293 cmp r3, r2 80087f4: d902 bls.n 80087fc { ret = HAL_ERROR; 80087f6: 2301 movs r3, #1 80087f8: 75fb strb r3, [r7, #23] break; 80087fa: e056 b.n 80088aa } } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); 80087fc: 683b ldr r3, [r7, #0] 80087fe: 781b ldrb r3, [r3, #0] 8008800: 015a lsls r2, r3, #5 8008802: 693b ldr r3, [r7, #16] 8008804: 4413 add r3, r2 8008806: f503 6310 add.w r3, r3, #2304 @ 0x900 800880a: 681b ldr r3, [r3, #0] 800880c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008810: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008814: d0e7 beq.n 80087e6 8008816: e048 b.n 80088aa } } else /* OUT endpoint */ { if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8008818: 683b ldr r3, [r7, #0] 800881a: 781b ldrb r3, [r3, #0] 800881c: 015a lsls r2, r3, #5 800881e: 693b ldr r3, [r7, #16] 8008820: 4413 add r3, r2 8008822: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008826: 681b ldr r3, [r3, #0] 8008828: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800882c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008830: d13b bne.n 80088aa { USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); 8008832: 683b ldr r3, [r7, #0] 8008834: 781b ldrb r3, [r3, #0] 8008836: 015a lsls r2, r3, #5 8008838: 693b ldr r3, [r7, #16] 800883a: 4413 add r3, r2 800883c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008840: 681b ldr r3, [r3, #0] 8008842: 683a ldr r2, [r7, #0] 8008844: 7812 ldrb r2, [r2, #0] 8008846: 0151 lsls r1, r2, #5 8008848: 693a ldr r2, [r7, #16] 800884a: 440a add r2, r1 800884c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008850: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000 8008854: 6013 str r3, [r2, #0] USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); 8008856: 683b ldr r3, [r7, #0] 8008858: 781b ldrb r3, [r3, #0] 800885a: 015a lsls r2, r3, #5 800885c: 693b ldr r3, [r7, #16] 800885e: 4413 add r3, r2 8008860: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008864: 681b ldr r3, [r3, #0] 8008866: 683a ldr r2, [r7, #0] 8008868: 7812 ldrb r2, [r2, #0] 800886a: 0151 lsls r1, r2, #5 800886c: 693a ldr r2, [r7, #16] 800886e: 440a add r2, r1 8008870: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008874: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8008878: 6013 str r3, [r2, #0] do { count++; 800887a: 68fb ldr r3, [r7, #12] 800887c: 3301 adds r3, #1 800887e: 60fb str r3, [r7, #12] if (count > 10000U) 8008880: 68fb ldr r3, [r7, #12] 8008882: f242 7210 movw r2, #10000 @ 0x2710 8008886: 4293 cmp r3, r2 8008888: d902 bls.n 8008890 { ret = HAL_ERROR; 800888a: 2301 movs r3, #1 800888c: 75fb strb r3, [r7, #23] break; 800888e: e00c b.n 80088aa } } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); 8008890: 683b ldr r3, [r7, #0] 8008892: 781b ldrb r3, [r3, #0] 8008894: 015a lsls r2, r3, #5 8008896: 693b ldr r3, [r7, #16] 8008898: 4413 add r3, r2 800889a: f503 6330 add.w r3, r3, #2816 @ 0xb00 800889e: 681b ldr r3, [r3, #0] 80088a0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80088a4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80088a8: d0e7 beq.n 800887a } } return ret; 80088aa: 7dfb ldrb r3, [r7, #23] } 80088ac: 4618 mov r0, r3 80088ae: 371c adds r7, #28 80088b0: 46bd mov sp, r7 80088b2: f85d 7b04 ldr.w r7, [sp], #4 80088b6: 4770 bx lr 080088b8 : * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { 80088b8: b480 push {r7} 80088ba: b089 sub sp, #36 @ 0x24 80088bc: af00 add r7, sp, #0 80088be: 60f8 str r0, [r7, #12] 80088c0: 60b9 str r1, [r7, #8] 80088c2: 4611 mov r1, r2 80088c4: 461a mov r2, r3 80088c6: 460b mov r3, r1 80088c8: 71fb strb r3, [r7, #7] 80088ca: 4613 mov r3, r2 80088cc: 80bb strh r3, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80088ce: 68fb ldr r3, [r7, #12] 80088d0: 617b str r3, [r7, #20] uint8_t *pSrc = src; 80088d2: 68bb ldr r3, [r7, #8] 80088d4: 61fb str r3, [r7, #28] uint32_t count32b; uint32_t i; if (dma == 0U) 80088d6: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 80088da: 2b00 cmp r3, #0 80088dc: d123 bne.n 8008926 { count32b = ((uint32_t)len + 3U) / 4U; 80088de: 88bb ldrh r3, [r7, #4] 80088e0: 3303 adds r3, #3 80088e2: 089b lsrs r3, r3, #2 80088e4: 613b str r3, [r7, #16] for (i = 0U; i < count32b; i++) 80088e6: 2300 movs r3, #0 80088e8: 61bb str r3, [r7, #24] 80088ea: e018 b.n 800891e { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); 80088ec: 79fb ldrb r3, [r7, #7] 80088ee: 031a lsls r2, r3, #12 80088f0: 697b ldr r3, [r7, #20] 80088f2: 4413 add r3, r2 80088f4: f503 5380 add.w r3, r3, #4096 @ 0x1000 80088f8: 461a mov r2, r3 80088fa: 69fb ldr r3, [r7, #28] 80088fc: 681b ldr r3, [r3, #0] 80088fe: 6013 str r3, [r2, #0] pSrc++; 8008900: 69fb ldr r3, [r7, #28] 8008902: 3301 adds r3, #1 8008904: 61fb str r3, [r7, #28] pSrc++; 8008906: 69fb ldr r3, [r7, #28] 8008908: 3301 adds r3, #1 800890a: 61fb str r3, [r7, #28] pSrc++; 800890c: 69fb ldr r3, [r7, #28] 800890e: 3301 adds r3, #1 8008910: 61fb str r3, [r7, #28] pSrc++; 8008912: 69fb ldr r3, [r7, #28] 8008914: 3301 adds r3, #1 8008916: 61fb str r3, [r7, #28] for (i = 0U; i < count32b; i++) 8008918: 69bb ldr r3, [r7, #24] 800891a: 3301 adds r3, #1 800891c: 61bb str r3, [r7, #24] 800891e: 69ba ldr r2, [r7, #24] 8008920: 693b ldr r3, [r7, #16] 8008922: 429a cmp r2, r3 8008924: d3e2 bcc.n 80088ec } } return HAL_OK; 8008926: 2300 movs r3, #0 } 8008928: 4618 mov r0, r3 800892a: 3724 adds r7, #36 @ 0x24 800892c: 46bd mov sp, r7 800892e: f85d 7b04 ldr.w r7, [sp], #4 8008932: 4770 bx lr 08008934 : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 8008934: b480 push {r7} 8008936: b08b sub sp, #44 @ 0x2c 8008938: af00 add r7, sp, #0 800893a: 60f8 str r0, [r7, #12] 800893c: 60b9 str r1, [r7, #8] 800893e: 4613 mov r3, r2 8008940: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 8008942: 68fb ldr r3, [r7, #12] 8008944: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 8008946: 68bb ldr r3, [r7, #8] 8008948: 627b str r3, [r7, #36] @ 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 800894a: 88fb ldrh r3, [r7, #6] 800894c: 089b lsrs r3, r3, #2 800894e: b29b uxth r3, r3 8008950: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 8008952: 88fb ldrh r3, [r7, #6] 8008954: f003 0303 and.w r3, r3, #3 8008958: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 800895a: 2300 movs r3, #0 800895c: 623b str r3, [r7, #32] 800895e: e014 b.n 800898a { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 8008960: 69bb ldr r3, [r7, #24] 8008962: f503 5380 add.w r3, r3, #4096 @ 0x1000 8008966: 681a ldr r2, [r3, #0] 8008968: 6a7b ldr r3, [r7, #36] @ 0x24 800896a: 601a str r2, [r3, #0] pDest++; 800896c: 6a7b ldr r3, [r7, #36] @ 0x24 800896e: 3301 adds r3, #1 8008970: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008972: 6a7b ldr r3, [r7, #36] @ 0x24 8008974: 3301 adds r3, #1 8008976: 627b str r3, [r7, #36] @ 0x24 pDest++; 8008978: 6a7b ldr r3, [r7, #36] @ 0x24 800897a: 3301 adds r3, #1 800897c: 627b str r3, [r7, #36] @ 0x24 pDest++; 800897e: 6a7b ldr r3, [r7, #36] @ 0x24 8008980: 3301 adds r3, #1 8008982: 627b str r3, [r7, #36] @ 0x24 for (i = 0U; i < count32b; i++) 8008984: 6a3b ldr r3, [r7, #32] 8008986: 3301 adds r3, #1 8008988: 623b str r3, [r7, #32] 800898a: 6a3a ldr r2, [r7, #32] 800898c: 697b ldr r3, [r7, #20] 800898e: 429a cmp r2, r3 8008990: d3e6 bcc.n 8008960 } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 8008992: 8bfb ldrh r3, [r7, #30] 8008994: 2b00 cmp r3, #0 8008996: d01e beq.n 80089d6 { i = 0U; 8008998: 2300 movs r3, #0 800899a: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 800899c: 69bb ldr r3, [r7, #24] 800899e: f503 5380 add.w r3, r3, #4096 @ 0x1000 80089a2: 461a mov r2, r3 80089a4: f107 0310 add.w r3, r7, #16 80089a8: 6812 ldr r2, [r2, #0] 80089aa: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 80089ac: 693a ldr r2, [r7, #16] 80089ae: 6a3b ldr r3, [r7, #32] 80089b0: b2db uxtb r3, r3 80089b2: 00db lsls r3, r3, #3 80089b4: fa22 f303 lsr.w r3, r2, r3 80089b8: b2da uxtb r2, r3 80089ba: 6a7b ldr r3, [r7, #36] @ 0x24 80089bc: 701a strb r2, [r3, #0] i++; 80089be: 6a3b ldr r3, [r7, #32] 80089c0: 3301 adds r3, #1 80089c2: 623b str r3, [r7, #32] pDest++; 80089c4: 6a7b ldr r3, [r7, #36] @ 0x24 80089c6: 3301 adds r3, #1 80089c8: 627b str r3, [r7, #36] @ 0x24 remaining_bytes--; 80089ca: 8bfb ldrh r3, [r7, #30] 80089cc: 3b01 subs r3, #1 80089ce: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 80089d0: 8bfb ldrh r3, [r7, #30] 80089d2: 2b00 cmp r3, #0 80089d4: d1ea bne.n 80089ac } return ((void *)pDest); 80089d6: 6a7b ldr r3, [r7, #36] @ 0x24 } 80089d8: 4618 mov r0, r3 80089da: 372c adds r7, #44 @ 0x2c 80089dc: 46bd mov sp, r7 80089de: f85d 7b04 ldr.w r7, [sp], #4 80089e2: 4770 bx lr 080089e4 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 80089e4: b480 push {r7} 80089e6: b085 sub sp, #20 80089e8: af00 add r7, sp, #0 80089ea: 6078 str r0, [r7, #4] 80089ec: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80089ee: 687b ldr r3, [r7, #4] 80089f0: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80089f2: 683b ldr r3, [r7, #0] 80089f4: 781b ldrb r3, [r3, #0] 80089f6: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 80089f8: 683b ldr r3, [r7, #0] 80089fa: 785b ldrb r3, [r3, #1] 80089fc: 2b01 cmp r3, #1 80089fe: d12c bne.n 8008a5a { if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) 8008a00: 68bb ldr r3, [r7, #8] 8008a02: 015a lsls r2, r3, #5 8008a04: 68fb ldr r3, [r7, #12] 8008a06: 4413 add r3, r2 8008a08: f503 6310 add.w r3, r3, #2304 @ 0x900 8008a0c: 681b ldr r3, [r3, #0] 8008a0e: 2b00 cmp r3, #0 8008a10: db12 blt.n 8008a38 8008a12: 68bb ldr r3, [r7, #8] 8008a14: 2b00 cmp r3, #0 8008a16: d00f beq.n 8008a38 { USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 8008a18: 68bb ldr r3, [r7, #8] 8008a1a: 015a lsls r2, r3, #5 8008a1c: 68fb ldr r3, [r7, #12] 8008a1e: 4413 add r3, r2 8008a20: f503 6310 add.w r3, r3, #2304 @ 0x900 8008a24: 681b ldr r3, [r3, #0] 8008a26: 68ba ldr r2, [r7, #8] 8008a28: 0151 lsls r1, r2, #5 8008a2a: 68fa ldr r2, [r7, #12] 8008a2c: 440a add r2, r1 8008a2e: f502 6210 add.w r2, r2, #2304 @ 0x900 8008a32: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8008a36: 6013 str r3, [r2, #0] } USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 8008a38: 68bb ldr r3, [r7, #8] 8008a3a: 015a lsls r2, r3, #5 8008a3c: 68fb ldr r3, [r7, #12] 8008a3e: 4413 add r3, r2 8008a40: f503 6310 add.w r3, r3, #2304 @ 0x900 8008a44: 681b ldr r3, [r3, #0] 8008a46: 68ba ldr r2, [r7, #8] 8008a48: 0151 lsls r1, r2, #5 8008a4a: 68fa ldr r2, [r7, #12] 8008a4c: 440a add r2, r1 8008a4e: f502 6210 add.w r2, r2, #2304 @ 0x900 8008a52: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8008a56: 6013 str r3, [r2, #0] 8008a58: e02b b.n 8008ab2 } else { if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) 8008a5a: 68bb ldr r3, [r7, #8] 8008a5c: 015a lsls r2, r3, #5 8008a5e: 68fb ldr r3, [r7, #12] 8008a60: 4413 add r3, r2 8008a62: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008a66: 681b ldr r3, [r3, #0] 8008a68: 2b00 cmp r3, #0 8008a6a: db12 blt.n 8008a92 8008a6c: 68bb ldr r3, [r7, #8] 8008a6e: 2b00 cmp r3, #0 8008a70: d00f beq.n 8008a92 { USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 8008a72: 68bb ldr r3, [r7, #8] 8008a74: 015a lsls r2, r3, #5 8008a76: 68fb ldr r3, [r7, #12] 8008a78: 4413 add r3, r2 8008a7a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008a7e: 681b ldr r3, [r3, #0] 8008a80: 68ba ldr r2, [r7, #8] 8008a82: 0151 lsls r1, r2, #5 8008a84: 68fa ldr r2, [r7, #12] 8008a86: 440a add r2, r1 8008a88: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008a8c: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8008a90: 6013 str r3, [r2, #0] } USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 8008a92: 68bb ldr r3, [r7, #8] 8008a94: 015a lsls r2, r3, #5 8008a96: 68fb ldr r3, [r7, #12] 8008a98: 4413 add r3, r2 8008a9a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008a9e: 681b ldr r3, [r3, #0] 8008aa0: 68ba ldr r2, [r7, #8] 8008aa2: 0151 lsls r1, r2, #5 8008aa4: 68fa ldr r2, [r7, #12] 8008aa6: 440a add r2, r1 8008aa8: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008aac: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8008ab0: 6013 str r3, [r2, #0] } return HAL_OK; 8008ab2: 2300 movs r3, #0 } 8008ab4: 4618 mov r0, r3 8008ab6: 3714 adds r7, #20 8008ab8: 46bd mov sp, r7 8008aba: f85d 7b04 ldr.w r7, [sp], #4 8008abe: 4770 bx lr 08008ac0 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { 8008ac0: b480 push {r7} 8008ac2: b085 sub sp, #20 8008ac4: af00 add r7, sp, #0 8008ac6: 6078 str r0, [r7, #4] 8008ac8: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8008aca: 687b ldr r3, [r7, #4] 8008acc: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8008ace: 683b ldr r3, [r7, #0] 8008ad0: 781b ldrb r3, [r3, #0] 8008ad2: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8008ad4: 683b ldr r3, [r7, #0] 8008ad6: 785b ldrb r3, [r3, #1] 8008ad8: 2b01 cmp r3, #1 8008ada: d128 bne.n 8008b2e { USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 8008adc: 68bb ldr r3, [r7, #8] 8008ade: 015a lsls r2, r3, #5 8008ae0: 68fb ldr r3, [r7, #12] 8008ae2: 4413 add r3, r2 8008ae4: f503 6310 add.w r3, r3, #2304 @ 0x900 8008ae8: 681b ldr r3, [r3, #0] 8008aea: 68ba ldr r2, [r7, #8] 8008aec: 0151 lsls r1, r2, #5 8008aee: 68fa ldr r2, [r7, #12] 8008af0: 440a add r2, r1 8008af2: f502 6210 add.w r2, r2, #2304 @ 0x900 8008af6: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8008afa: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8008afc: 683b ldr r3, [r7, #0] 8008afe: 791b ldrb r3, [r3, #4] 8008b00: 2b03 cmp r3, #3 8008b02: d003 beq.n 8008b0c 8008b04: 683b ldr r3, [r7, #0] 8008b06: 791b ldrb r3, [r3, #4] 8008b08: 2b02 cmp r3, #2 8008b0a: d138 bne.n 8008b7e { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8008b0c: 68bb ldr r3, [r7, #8] 8008b0e: 015a lsls r2, r3, #5 8008b10: 68fb ldr r3, [r7, #12] 8008b12: 4413 add r3, r2 8008b14: f503 6310 add.w r3, r3, #2304 @ 0x900 8008b18: 681b ldr r3, [r3, #0] 8008b1a: 68ba ldr r2, [r7, #8] 8008b1c: 0151 lsls r1, r2, #5 8008b1e: 68fa ldr r2, [r7, #12] 8008b20: 440a add r2, r1 8008b22: f502 6210 add.w r2, r2, #2304 @ 0x900 8008b26: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008b2a: 6013 str r3, [r2, #0] 8008b2c: e027 b.n 8008b7e } } else { USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 8008b2e: 68bb ldr r3, [r7, #8] 8008b30: 015a lsls r2, r3, #5 8008b32: 68fb ldr r3, [r7, #12] 8008b34: 4413 add r3, r2 8008b36: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008b3a: 681b ldr r3, [r3, #0] 8008b3c: 68ba ldr r2, [r7, #8] 8008b3e: 0151 lsls r1, r2, #5 8008b40: 68fa ldr r2, [r7, #12] 8008b42: 440a add r2, r1 8008b44: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008b48: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8008b4c: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8008b4e: 683b ldr r3, [r7, #0] 8008b50: 791b ldrb r3, [r3, #4] 8008b52: 2b03 cmp r3, #3 8008b54: d003 beq.n 8008b5e 8008b56: 683b ldr r3, [r7, #0] 8008b58: 791b ldrb r3, [r3, #4] 8008b5a: 2b02 cmp r3, #2 8008b5c: d10f bne.n 8008b7e { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8008b5e: 68bb ldr r3, [r7, #8] 8008b60: 015a lsls r2, r3, #5 8008b62: 68fb ldr r3, [r7, #12] 8008b64: 4413 add r3, r2 8008b66: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008b6a: 681b ldr r3, [r3, #0] 8008b6c: 68ba ldr r2, [r7, #8] 8008b6e: 0151 lsls r1, r2, #5 8008b70: 68fa ldr r2, [r7, #12] 8008b72: 440a add r2, r1 8008b74: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008b78: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8008b7c: 6013 str r3, [r2, #0] } } return HAL_OK; 8008b7e: 2300 movs r3, #0 } 8008b80: 4618 mov r0, r3 8008b82: 3714 adds r7, #20 8008b84: 46bd mov sp, r7 8008b86: f85d 7b04 ldr.w r7, [sp], #4 8008b8a: 4770 bx lr 08008b8c : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { 8008b8c: b480 push {r7} 8008b8e: b085 sub sp, #20 8008b90: af00 add r7, sp, #0 8008b92: 6078 str r0, [r7, #4] 8008b94: 460b mov r3, r1 8008b96: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008b98: 687b ldr r3, [r7, #4] 8008b9a: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); 8008b9c: 68fb ldr r3, [r7, #12] 8008b9e: f503 6300 add.w r3, r3, #2048 @ 0x800 8008ba2: 681b ldr r3, [r3, #0] 8008ba4: 68fa ldr r2, [r7, #12] 8008ba6: f502 6200 add.w r2, r2, #2048 @ 0x800 8008baa: f423 63fe bic.w r3, r3, #2032 @ 0x7f0 8008bae: 6013 str r3, [r2, #0] USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; 8008bb0: 68fb ldr r3, [r7, #12] 8008bb2: f503 6300 add.w r3, r3, #2048 @ 0x800 8008bb6: 681a ldr r2, [r3, #0] 8008bb8: 78fb ldrb r3, [r7, #3] 8008bba: 011b lsls r3, r3, #4 8008bbc: f403 63fe and.w r3, r3, #2032 @ 0x7f0 8008bc0: 68f9 ldr r1, [r7, #12] 8008bc2: f501 6100 add.w r1, r1, #2048 @ 0x800 8008bc6: 4313 orrs r3, r2 8008bc8: 600b str r3, [r1, #0] return HAL_OK; 8008bca: 2300 movs r3, #0 } 8008bcc: 4618 mov r0, r3 8008bce: 3714 adds r7, #20 8008bd0: 46bd mov sp, r7 8008bd2: f85d 7b04 ldr.w r7, [sp], #4 8008bd6: 4770 bx lr 08008bd8 : * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { 8008bd8: b480 push {r7} 8008bda: b085 sub sp, #20 8008bdc: af00 add r7, sp, #0 8008bde: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008be0: 687b ldr r3, [r7, #4] 8008be2: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8008be4: 68fb ldr r3, [r7, #12] 8008be6: f503 6360 add.w r3, r3, #3584 @ 0xe00 8008bea: 681b ldr r3, [r3, #0] 8008bec: 68fa ldr r2, [r7, #12] 8008bee: f502 6260 add.w r2, r2, #3584 @ 0xe00 8008bf2: f023 0303 bic.w r3, r3, #3 8008bf6: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; 8008bf8: 68fb ldr r3, [r7, #12] 8008bfa: f503 6300 add.w r3, r3, #2048 @ 0x800 8008bfe: 685b ldr r3, [r3, #4] 8008c00: 68fa ldr r2, [r7, #12] 8008c02: f502 6200 add.w r2, r2, #2048 @ 0x800 8008c06: f023 0302 bic.w r3, r3, #2 8008c0a: 6053 str r3, [r2, #4] return HAL_OK; 8008c0c: 2300 movs r3, #0 } 8008c0e: 4618 mov r0, r3 8008c10: 3714 adds r7, #20 8008c12: 46bd mov sp, r7 8008c14: f85d 7b04 ldr.w r7, [sp], #4 8008c18: 4770 bx lr 08008c1a : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { 8008c1a: b480 push {r7} 8008c1c: b085 sub sp, #20 8008c1e: af00 add r7, sp, #0 8008c20: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008c22: 687b ldr r3, [r7, #4] 8008c24: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8008c26: 68fb ldr r3, [r7, #12] 8008c28: f503 6360 add.w r3, r3, #3584 @ 0xe00 8008c2c: 681b ldr r3, [r3, #0] 8008c2e: 68fa ldr r2, [r7, #12] 8008c30: f502 6260 add.w r2, r2, #3584 @ 0xe00 8008c34: f023 0303 bic.w r3, r3, #3 8008c38: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8008c3a: 68fb ldr r3, [r7, #12] 8008c3c: f503 6300 add.w r3, r3, #2048 @ 0x800 8008c40: 685b ldr r3, [r3, #4] 8008c42: 68fa ldr r2, [r7, #12] 8008c44: f502 6200 add.w r2, r2, #2048 @ 0x800 8008c48: f043 0302 orr.w r3, r3, #2 8008c4c: 6053 str r3, [r2, #4] return HAL_OK; 8008c4e: 2300 movs r3, #0 } 8008c50: 4618 mov r0, r3 8008c52: 3714 adds r7, #20 8008c54: 46bd mov sp, r7 8008c56: f85d 7b04 ldr.w r7, [sp], #4 8008c5a: 4770 bx lr 08008c5c : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { 8008c5c: b480 push {r7} 8008c5e: b085 sub sp, #20 8008c60: af00 add r7, sp, #0 8008c62: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 8008c64: 687b ldr r3, [r7, #4] 8008c66: 695b ldr r3, [r3, #20] 8008c68: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 8008c6a: 687b ldr r3, [r7, #4] 8008c6c: 699b ldr r3, [r3, #24] 8008c6e: 68fa ldr r2, [r7, #12] 8008c70: 4013 ands r3, r2 8008c72: 60fb str r3, [r7, #12] return tmpreg; 8008c74: 68fb ldr r3, [r7, #12] } 8008c76: 4618 mov r0, r3 8008c78: 3714 adds r7, #20 8008c7a: 46bd mov sp, r7 8008c7c: f85d 7b04 ldr.w r7, [sp], #4 8008c80: 4770 bx lr 08008c82 : * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device * @retval USB Device OUT EP interrupt status */ uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 8008c82: b480 push {r7} 8008c84: b085 sub sp, #20 8008c86: af00 add r7, sp, #0 8008c88: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008c8a: 687b ldr r3, [r7, #4] 8008c8c: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8008c8e: 68fb ldr r3, [r7, #12] 8008c90: f503 6300 add.w r3, r3, #2048 @ 0x800 8008c94: 699b ldr r3, [r3, #24] 8008c96: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 8008c98: 68fb ldr r3, [r7, #12] 8008c9a: f503 6300 add.w r3, r3, #2048 @ 0x800 8008c9e: 69db ldr r3, [r3, #28] 8008ca0: 68ba ldr r2, [r7, #8] 8008ca2: 4013 ands r3, r2 8008ca4: 60bb str r3, [r7, #8] return ((tmpreg & 0xffff0000U) >> 16); 8008ca6: 68bb ldr r3, [r7, #8] 8008ca8: 0c1b lsrs r3, r3, #16 } 8008caa: 4618 mov r0, r3 8008cac: 3714 adds r7, #20 8008cae: 46bd mov sp, r7 8008cb0: f85d 7b04 ldr.w r7, [sp], #4 8008cb4: 4770 bx lr 08008cb6 : * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device * @retval USB Device IN EP interrupt status */ uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 8008cb6: b480 push {r7} 8008cb8: b085 sub sp, #20 8008cba: af00 add r7, sp, #0 8008cbc: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008cbe: 687b ldr r3, [r7, #4] 8008cc0: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8008cc2: 68fb ldr r3, [r7, #12] 8008cc4: f503 6300 add.w r3, r3, #2048 @ 0x800 8008cc8: 699b ldr r3, [r3, #24] 8008cca: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 8008ccc: 68fb ldr r3, [r7, #12] 8008cce: f503 6300 add.w r3, r3, #2048 @ 0x800 8008cd2: 69db ldr r3, [r3, #28] 8008cd4: 68ba ldr r2, [r7, #8] 8008cd6: 4013 ands r3, r2 8008cd8: 60bb str r3, [r7, #8] return ((tmpreg & 0xFFFFU)); 8008cda: 68bb ldr r3, [r7, #8] 8008cdc: b29b uxth r3, r3 } 8008cde: 4618 mov r0, r3 8008ce0: 3714 adds r7, #20 8008ce2: 46bd mov sp, r7 8008ce4: f85d 7b04 ldr.w r7, [sp], #4 8008ce8: 4770 bx lr 08008cea : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 8008cea: b480 push {r7} 8008cec: b085 sub sp, #20 8008cee: af00 add r7, sp, #0 8008cf0: 6078 str r0, [r7, #4] 8008cf2: 460b mov r3, r1 8008cf4: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008cf6: 687b ldr r3, [r7, #4] 8008cf8: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; 8008cfa: 78fb ldrb r3, [r7, #3] 8008cfc: 015a lsls r2, r3, #5 8008cfe: 68fb ldr r3, [r7, #12] 8008d00: 4413 add r3, r2 8008d02: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008d06: 689b ldr r3, [r3, #8] 8008d08: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DOEPMSK; 8008d0a: 68fb ldr r3, [r7, #12] 8008d0c: f503 6300 add.w r3, r3, #2048 @ 0x800 8008d10: 695b ldr r3, [r3, #20] 8008d12: 68ba ldr r2, [r7, #8] 8008d14: 4013 ands r3, r2 8008d16: 60bb str r3, [r7, #8] return tmpreg; 8008d18: 68bb ldr r3, [r7, #8] } 8008d1a: 4618 mov r0, r3 8008d1c: 3714 adds r7, #20 8008d1e: 46bd mov sp, r7 8008d20: f85d 7b04 ldr.w r7, [sp], #4 8008d24: 4770 bx lr 08008d26 : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 8008d26: b480 push {r7} 8008d28: b087 sub sp, #28 8008d2a: af00 add r7, sp, #0 8008d2c: 6078 str r0, [r7, #4] 8008d2e: 460b mov r3, r1 8008d30: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8008d32: 687b ldr r3, [r7, #4] 8008d34: 617b str r3, [r7, #20] uint32_t tmpreg; uint32_t msk; uint32_t emp; msk = USBx_DEVICE->DIEPMSK; 8008d36: 697b ldr r3, [r7, #20] 8008d38: f503 6300 add.w r3, r3, #2048 @ 0x800 8008d3c: 691b ldr r3, [r3, #16] 8008d3e: 613b str r3, [r7, #16] emp = USBx_DEVICE->DIEPEMPMSK; 8008d40: 697b ldr r3, [r7, #20] 8008d42: f503 6300 add.w r3, r3, #2048 @ 0x800 8008d46: 6b5b ldr r3, [r3, #52] @ 0x34 8008d48: 60fb str r3, [r7, #12] msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; 8008d4a: 78fb ldrb r3, [r7, #3] 8008d4c: f003 030f and.w r3, r3, #15 8008d50: 68fa ldr r2, [r7, #12] 8008d52: fa22 f303 lsr.w r3, r2, r3 8008d56: 01db lsls r3, r3, #7 8008d58: b2db uxtb r3, r3 8008d5a: 693a ldr r2, [r7, #16] 8008d5c: 4313 orrs r3, r2 8008d5e: 613b str r3, [r7, #16] tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; 8008d60: 78fb ldrb r3, [r7, #3] 8008d62: 015a lsls r2, r3, #5 8008d64: 697b ldr r3, [r7, #20] 8008d66: 4413 add r3, r2 8008d68: f503 6310 add.w r3, r3, #2304 @ 0x900 8008d6c: 689b ldr r3, [r3, #8] 8008d6e: 693a ldr r2, [r7, #16] 8008d70: 4013 ands r3, r2 8008d72: 60bb str r3, [r7, #8] return tmpreg; 8008d74: 68bb ldr r3, [r7, #8] } 8008d76: 4618 mov r0, r3 8008d78: 371c adds r7, #28 8008d7a: 46bd mov sp, r7 8008d7c: f85d 7b04 ldr.w r7, [sp], #4 8008d80: 4770 bx lr 08008d82 : * This parameter can be one of these values: * 1 : Host * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { 8008d82: b480 push {r7} 8008d84: b083 sub sp, #12 8008d86: af00 add r7, sp, #0 8008d88: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 8008d8a: 687b ldr r3, [r7, #4] 8008d8c: 695b ldr r3, [r3, #20] 8008d8e: f003 0301 and.w r3, r3, #1 } 8008d92: 4618 mov r0, r3 8008d94: 370c adds r7, #12 8008d96: 46bd mov sp, r7 8008d98: f85d 7b04 ldr.w r7, [sp], #4 8008d9c: 4770 bx lr 08008d9e : * @brief Activate EP0 for Setup transactions * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { 8008d9e: b480 push {r7} 8008da0: b085 sub sp, #20 8008da2: af00 add r7, sp, #0 8008da4: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8008da6: 687b ldr r3, [r7, #4] 8008da8: 60fb str r3, [r7, #12] /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 8008daa: 68fb ldr r3, [r7, #12] 8008dac: f503 6310 add.w r3, r3, #2304 @ 0x900 8008db0: 681b ldr r3, [r3, #0] 8008db2: 68fa ldr r2, [r7, #12] 8008db4: f502 6210 add.w r2, r2, #2304 @ 0x900 8008db8: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 8008dbc: f023 0307 bic.w r3, r3, #7 8008dc0: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 8008dc2: 68fb ldr r3, [r7, #12] 8008dc4: f503 6300 add.w r3, r3, #2048 @ 0x800 8008dc8: 685b ldr r3, [r3, #4] 8008dca: 68fa ldr r2, [r7, #12] 8008dcc: f502 6200 add.w r2, r2, #2048 @ 0x800 8008dd0: f443 7380 orr.w r3, r3, #256 @ 0x100 8008dd4: 6053 str r3, [r2, #4] return HAL_OK; 8008dd6: 2300 movs r3, #0 } 8008dd8: 4618 mov r0, r3 8008dda: 3714 adds r7, #20 8008ddc: 46bd mov sp, r7 8008dde: f85d 7b04 ldr.w r7, [sp], #4 8008de2: 4770 bx lr 08008de4 : * 1 : DMA feature used * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { 8008de4: b480 push {r7} 8008de6: b087 sub sp, #28 8008de8: af00 add r7, sp, #0 8008dea: 60f8 str r0, [r7, #12] 8008dec: 460b mov r3, r1 8008dee: 607a str r2, [r7, #4] 8008df0: 72fb strb r3, [r7, #11] uint32_t USBx_BASE = (uint32_t)USBx; 8008df2: 68fb ldr r3, [r7, #12] 8008df4: 617b str r3, [r7, #20] uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); 8008df6: 68fb ldr r3, [r7, #12] 8008df8: 333c adds r3, #60 @ 0x3c 8008dfa: 3304 adds r3, #4 8008dfc: 681b ldr r3, [r3, #0] 8008dfe: 613b str r3, [r7, #16] if (gSNPSiD > USB_OTG_CORE_ID_300A) 8008e00: 693b ldr r3, [r7, #16] 8008e02: 4a26 ldr r2, [pc, #152] @ (8008e9c ) 8008e04: 4293 cmp r3, r2 8008e06: d90a bls.n 8008e1e { if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8008e08: 697b ldr r3, [r7, #20] 8008e0a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008e0e: 681b ldr r3, [r3, #0] 8008e10: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8008e14: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8008e18: d101 bne.n 8008e1e { return HAL_OK; 8008e1a: 2300 movs r3, #0 8008e1c: e037 b.n 8008e8e } } USBx_OUTEP(0U)->DOEPTSIZ = 0U; 8008e1e: 697b ldr r3, [r7, #20] 8008e20: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008e24: 461a mov r2, r3 8008e26: 2300 movs r3, #0 8008e28: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8008e2a: 697b ldr r3, [r7, #20] 8008e2c: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008e30: 691b ldr r3, [r3, #16] 8008e32: 697a ldr r2, [r7, #20] 8008e34: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008e38: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8008e3c: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); 8008e3e: 697b ldr r3, [r7, #20] 8008e40: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008e44: 691b ldr r3, [r3, #16] 8008e46: 697a ldr r2, [r7, #20] 8008e48: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008e4c: f043 0318 orr.w r3, r3, #24 8008e50: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 8008e52: 697b ldr r3, [r7, #20] 8008e54: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008e58: 691b ldr r3, [r3, #16] 8008e5a: 697a ldr r2, [r7, #20] 8008e5c: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008e60: f043 43c0 orr.w r3, r3, #1610612736 @ 0x60000000 8008e64: 6113 str r3, [r2, #16] if (dma == 1U) 8008e66: 7afb ldrb r3, [r7, #11] 8008e68: 2b01 cmp r3, #1 8008e6a: d10f bne.n 8008e8c { USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; 8008e6c: 697b ldr r3, [r7, #20] 8008e6e: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008e72: 461a mov r2, r3 8008e74: 687b ldr r3, [r7, #4] 8008e76: 6153 str r3, [r2, #20] /* EP enable */ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; 8008e78: 697b ldr r3, [r7, #20] 8008e7a: f503 6330 add.w r3, r3, #2816 @ 0xb00 8008e7e: 681b ldr r3, [r3, #0] 8008e80: 697a ldr r2, [r7, #20] 8008e82: f502 6230 add.w r2, r2, #2816 @ 0xb00 8008e86: f043 2380 orr.w r3, r3, #2147516416 @ 0x80008000 8008e8a: 6013 str r3, [r2, #0] } return HAL_OK; 8008e8c: 2300 movs r3, #0 } 8008e8e: 4618 mov r0, r3 8008e90: 371c adds r7, #28 8008e92: 46bd mov sp, r7 8008e94: f85d 7b04 ldr.w r7, [sp], #4 8008e98: 4770 bx lr 8008e9a: bf00 nop 8008e9c: 4f54300a .word 0x4f54300a 08008ea0 : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 8008ea0: b480 push {r7} 8008ea2: b085 sub sp, #20 8008ea4: af00 add r7, sp, #0 8008ea6: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8008ea8: 2300 movs r3, #0 8008eaa: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8008eac: 68fb ldr r3, [r7, #12] 8008eae: 3301 adds r3, #1 8008eb0: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8008eb2: 68fb ldr r3, [r7, #12] 8008eb4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8008eb8: d901 bls.n 8008ebe { return HAL_TIMEOUT; 8008eba: 2303 movs r3, #3 8008ebc: e022 b.n 8008f04 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8008ebe: 687b ldr r3, [r7, #4] 8008ec0: 691b ldr r3, [r3, #16] 8008ec2: 2b00 cmp r3, #0 8008ec4: daf2 bge.n 8008eac count = 10U; 8008ec6: 230a movs r3, #10 8008ec8: 60fb str r3, [r7, #12] /* few cycles before setting core reset */ while (count > 0U) 8008eca: e002 b.n 8008ed2 { count--; 8008ecc: 68fb ldr r3, [r7, #12] 8008ece: 3b01 subs r3, #1 8008ed0: 60fb str r3, [r7, #12] while (count > 0U) 8008ed2: 68fb ldr r3, [r7, #12] 8008ed4: 2b00 cmp r3, #0 8008ed6: d1f9 bne.n 8008ecc } /* Core Soft Reset */ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 8008ed8: 687b ldr r3, [r7, #4] 8008eda: 691b ldr r3, [r3, #16] 8008edc: f043 0201 orr.w r2, r3, #1 8008ee0: 687b ldr r3, [r7, #4] 8008ee2: 611a str r2, [r3, #16] do { count++; 8008ee4: 68fb ldr r3, [r7, #12] 8008ee6: 3301 adds r3, #1 8008ee8: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8008eea: 68fb ldr r3, [r7, #12] 8008eec: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8008ef0: d901 bls.n 8008ef6 { return HAL_TIMEOUT; 8008ef2: 2303 movs r3, #3 8008ef4: e006 b.n 8008f04 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 8008ef6: 687b ldr r3, [r7, #4] 8008ef8: 691b ldr r3, [r3, #16] 8008efa: f003 0301 and.w r3, r3, #1 8008efe: 2b01 cmp r3, #1 8008f00: d0f0 beq.n 8008ee4 return HAL_OK; 8008f02: 2300 movs r3, #0 } 8008f04: 4618 mov r0, r3 8008f06: 3714 adds r7, #20 8008f08: 46bd mov sp, r7 8008f0a: f85d 7b04 ldr.w r7, [sp], #4 8008f0e: 4770 bx lr 08008f10 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008f10: b580 push {r7, lr} 8008f12: b084 sub sp, #16 8008f14: af00 add r7, sp, #0 8008f16: 6078 str r0, [r7, #4] 8008f18: 460b mov r3, r1 8008f1a: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_HID_HandleTypeDef *hhid; hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); 8008f1c: 2010 movs r0, #16 8008f1e: f002 f9e3 bl 800b2e8 8008f22: 60f8 str r0, [r7, #12] if (hhid == NULL) 8008f24: 68fb ldr r3, [r7, #12] 8008f26: 2b00 cmp r3, #0 8008f28: d109 bne.n 8008f3e { pdev->pClassDataCmsit[pdev->classId] = NULL; 8008f2a: 687b ldr r3, [r7, #4] 8008f2c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008f30: 687b ldr r3, [r7, #4] 8008f32: 32b0 adds r2, #176 @ 0xb0 8008f34: 2100 movs r1, #0 8008f36: f843 1022 str.w r1, [r3, r2, lsl #2] return (uint8_t)USBD_EMEM; 8008f3a: 2302 movs r3, #2 8008f3c: e048 b.n 8008fd0 } pdev->pClassDataCmsit[pdev->classId] = (void *)hhid; 8008f3e: 687b ldr r3, [r7, #4] 8008f40: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008f44: 687b ldr r3, [r7, #4] 8008f46: 32b0 adds r2, #176 @ 0xb0 8008f48: 68f9 ldr r1, [r7, #12] 8008f4a: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; 8008f4e: 687b ldr r3, [r7, #4] 8008f50: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8008f54: 687b ldr r3, [r7, #4] 8008f56: 32b0 adds r2, #176 @ 0xb0 8008f58: f853 2022 ldr.w r2, [r3, r2, lsl #2] 8008f5c: 687b ldr r3, [r7, #4] 8008f5e: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_speed == USBD_SPEED_HIGH) 8008f62: 687b ldr r3, [r7, #4] 8008f64: 7c1b ldrb r3, [r3, #16] 8008f66: 2b00 cmp r3, #0 8008f68: d10d bne.n 8008f86 { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL; 8008f6a: 4b1b ldr r3, [pc, #108] @ (8008fd8 ) 8008f6c: 781b ldrb r3, [r3, #0] 8008f6e: f003 020f and.w r2, r3, #15 8008f72: 6879 ldr r1, [r7, #4] 8008f74: 4613 mov r3, r2 8008f76: 009b lsls r3, r3, #2 8008f78: 4413 add r3, r2 8008f7a: 009b lsls r3, r3, #2 8008f7c: 440b add r3, r1 8008f7e: 331c adds r3, #28 8008f80: 2207 movs r2, #7 8008f82: 601a str r2, [r3, #0] 8008f84: e00c b.n 8008fa0 } else /* LOW and FULL-speed endpoints */ { pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL; 8008f86: 4b14 ldr r3, [pc, #80] @ (8008fd8 ) 8008f88: 781b ldrb r3, [r3, #0] 8008f8a: f003 020f and.w r2, r3, #15 8008f8e: 6879 ldr r1, [r7, #4] 8008f90: 4613 mov r3, r2 8008f92: 009b lsls r3, r3, #2 8008f94: 4413 add r3, r2 8008f96: 009b lsls r3, r3, #2 8008f98: 440b add r3, r1 8008f9a: 331c adds r3, #28 8008f9c: 220a movs r2, #10 8008f9e: 601a str r2, [r3, #0] } /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); 8008fa0: 4b0d ldr r3, [pc, #52] @ (8008fd8 ) 8008fa2: 7819 ldrb r1, [r3, #0] 8008fa4: 230e movs r3, #14 8008fa6: 2203 movs r2, #3 8008fa8: 6878 ldr r0, [r7, #4] 8008faa: f002 f83e bl 800b02a pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U; 8008fae: 4b0a ldr r3, [pc, #40] @ (8008fd8 ) 8008fb0: 781b ldrb r3, [r3, #0] 8008fb2: f003 020f and.w r2, r3, #15 8008fb6: 6879 ldr r1, [r7, #4] 8008fb8: 4613 mov r3, r2 8008fba: 009b lsls r3, r3, #2 8008fbc: 4413 add r3, r2 8008fbe: 009b lsls r3, r3, #2 8008fc0: 440b add r3, r1 8008fc2: 3323 adds r3, #35 @ 0x23 8008fc4: 2201 movs r2, #1 8008fc6: 701a strb r2, [r3, #0] hhid->state = USBD_HID_IDLE; 8008fc8: 68fb ldr r3, [r7, #12] 8008fca: 2200 movs r2, #0 8008fcc: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 8008fce: 2300 movs r3, #0 } 8008fd0: 4618 mov r0, r3 8008fd2: 3710 adds r7, #16 8008fd4: 46bd mov sp, r7 8008fd6: bd80 pop {r7, pc} 8008fd8: 200001b1 .word 0x200001b1 08008fdc : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8008fdc: b580 push {r7, lr} 8008fde: b082 sub sp, #8 8008fe0: af00 add r7, sp, #0 8008fe2: 6078 str r0, [r7, #4] 8008fe4: 460b mov r3, r1 8008fe6: 70fb strb r3, [r7, #3] /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ /* Close HID EPs */ (void)USBD_LL_CloseEP(pdev, HIDInEpAdd); 8008fe8: 4b1f ldr r3, [pc, #124] @ (8009068 ) 8008fea: 781b ldrb r3, [r3, #0] 8008fec: 4619 mov r1, r3 8008fee: 6878 ldr r0, [r7, #4] 8008ff0: f002 f841 bl 800b076 pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U; 8008ff4: 4b1c ldr r3, [pc, #112] @ (8009068 ) 8008ff6: 781b ldrb r3, [r3, #0] 8008ff8: f003 020f and.w r2, r3, #15 8008ffc: 6879 ldr r1, [r7, #4] 8008ffe: 4613 mov r3, r2 8009000: 009b lsls r3, r3, #2 8009002: 4413 add r3, r2 8009004: 009b lsls r3, r3, #2 8009006: 440b add r3, r1 8009008: 3323 adds r3, #35 @ 0x23 800900a: 2200 movs r2, #0 800900c: 701a strb r2, [r3, #0] pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U; 800900e: 4b16 ldr r3, [pc, #88] @ (8009068 ) 8009010: 781b ldrb r3, [r3, #0] 8009012: f003 020f and.w r2, r3, #15 8009016: 6879 ldr r1, [r7, #4] 8009018: 4613 mov r3, r2 800901a: 009b lsls r3, r3, #2 800901c: 4413 add r3, r2 800901e: 009b lsls r3, r3, #2 8009020: 440b add r3, r1 8009022: 331c adds r3, #28 8009024: 2200 movs r2, #0 8009026: 601a str r2, [r3, #0] /* Free allocated memory */ if (pdev->pClassDataCmsit[pdev->classId] != NULL) 8009028: 687b ldr r3, [r7, #4] 800902a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800902e: 687b ldr r3, [r7, #4] 8009030: 32b0 adds r2, #176 @ 0xb0 8009032: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009036: 2b00 cmp r3, #0 8009038: d011 beq.n 800905e { (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); 800903a: 687b ldr r3, [r7, #4] 800903c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009040: 687b ldr r3, [r7, #4] 8009042: 32b0 adds r2, #176 @ 0xb0 8009044: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009048: 4618 mov r0, r3 800904a: f002 f95b bl 800b304 pdev->pClassDataCmsit[pdev->classId] = NULL; 800904e: 687b ldr r3, [r7, #4] 8009050: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009054: 687b ldr r3, [r7, #4] 8009056: 32b0 adds r2, #176 @ 0xb0 8009058: 2100 movs r1, #0 800905a: f843 1022 str.w r1, [r3, r2, lsl #2] } return (uint8_t)USBD_OK; 800905e: 2300 movs r3, #0 } 8009060: 4618 mov r0, r3 8009062: 3708 adds r7, #8 8009064: 46bd mov sp, r7 8009066: bd80 pop {r7, pc} 8009068: 200001b1 .word 0x200001b1 0800906c : * @param pdev: instance * @param req: usb requests * @retval status */ static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800906c: b580 push {r7, lr} 800906e: b086 sub sp, #24 8009070: af00 add r7, sp, #0 8009072: 6078 str r0, [r7, #4] 8009074: 6039 str r1, [r7, #0] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8009076: 687b ldr r3, [r7, #4] 8009078: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800907c: 687b ldr r3, [r7, #4] 800907e: 32b0 adds r2, #176 @ 0xb0 8009080: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009084: 60fb str r3, [r7, #12] USBD_StatusTypeDef ret = USBD_OK; 8009086: 2300 movs r3, #0 8009088: 75fb strb r3, [r7, #23] uint16_t len; uint8_t *pbuf; uint16_t status_info = 0U; 800908a: 2300 movs r3, #0 800908c: 817b strh r3, [r7, #10] if (hhid == NULL) 800908e: 68fb ldr r3, [r7, #12] 8009090: 2b00 cmp r3, #0 8009092: d101 bne.n 8009098 { return (uint8_t)USBD_FAIL; 8009094: 2303 movs r3, #3 8009096: e0e8 b.n 800926a } switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009098: 683b ldr r3, [r7, #0] 800909a: 781b ldrb r3, [r3, #0] 800909c: f003 0360 and.w r3, r3, #96 @ 0x60 80090a0: 2b00 cmp r3, #0 80090a2: d046 beq.n 8009132 80090a4: 2b20 cmp r3, #32 80090a6: f040 80d8 bne.w 800925a { case USB_REQ_TYPE_CLASS : switch (req->bRequest) 80090aa: 683b ldr r3, [r7, #0] 80090ac: 785b ldrb r3, [r3, #1] 80090ae: 3b02 subs r3, #2 80090b0: 2b09 cmp r3, #9 80090b2: d836 bhi.n 8009122 80090b4: a201 add r2, pc, #4 @ (adr r2, 80090bc ) 80090b6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80090ba: bf00 nop 80090bc: 08009113 .word 0x08009113 80090c0: 080090f3 .word 0x080090f3 80090c4: 08009123 .word 0x08009123 80090c8: 08009123 .word 0x08009123 80090cc: 08009123 .word 0x08009123 80090d0: 08009123 .word 0x08009123 80090d4: 08009123 .word 0x08009123 80090d8: 08009123 .word 0x08009123 80090dc: 08009101 .word 0x08009101 80090e0: 080090e5 .word 0x080090e5 { case USBD_HID_REQ_SET_PROTOCOL: hhid->Protocol = (uint8_t)(req->wValue); 80090e4: 683b ldr r3, [r7, #0] 80090e6: 885b ldrh r3, [r3, #2] 80090e8: b2db uxtb r3, r3 80090ea: 461a mov r2, r3 80090ec: 68fb ldr r3, [r7, #12] 80090ee: 601a str r2, [r3, #0] break; 80090f0: e01e b.n 8009130 case USBD_HID_REQ_GET_PROTOCOL: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); 80090f2: 68fb ldr r3, [r7, #12] 80090f4: 2201 movs r2, #1 80090f6: 4619 mov r1, r3 80090f8: 6878 ldr r0, [r7, #4] 80090fa: f001 fc25 bl 800a948 break; 80090fe: e017 b.n 8009130 case USBD_HID_REQ_SET_IDLE: hhid->IdleState = (uint8_t)(req->wValue >> 8); 8009100: 683b ldr r3, [r7, #0] 8009102: 885b ldrh r3, [r3, #2] 8009104: 0a1b lsrs r3, r3, #8 8009106: b29b uxth r3, r3 8009108: b2db uxtb r3, r3 800910a: 461a mov r2, r3 800910c: 68fb ldr r3, [r7, #12] 800910e: 605a str r2, [r3, #4] break; 8009110: e00e b.n 8009130 case USBD_HID_REQ_GET_IDLE: (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); 8009112: 68fb ldr r3, [r7, #12] 8009114: 3304 adds r3, #4 8009116: 2201 movs r2, #1 8009118: 4619 mov r1, r3 800911a: 6878 ldr r0, [r7, #4] 800911c: f001 fc14 bl 800a948 break; 8009120: e006 b.n 8009130 default: USBD_CtlError(pdev, req); 8009122: 6839 ldr r1, [r7, #0] 8009124: 6878 ldr r0, [r7, #4] 8009126: f001 fb92 bl 800a84e ret = USBD_FAIL; 800912a: 2303 movs r3, #3 800912c: 75fb strb r3, [r7, #23] break; 800912e: bf00 nop } break; 8009130: e09a b.n 8009268 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8009132: 683b ldr r3, [r7, #0] 8009134: 785b ldrb r3, [r3, #1] 8009136: 2b0b cmp r3, #11 8009138: f200 8086 bhi.w 8009248 800913c: a201 add r2, pc, #4 @ (adr r2, 8009144 ) 800913e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009142: bf00 nop 8009144: 08009175 .word 0x08009175 8009148: 08009257 .word 0x08009257 800914c: 08009249 .word 0x08009249 8009150: 08009249 .word 0x08009249 8009154: 08009249 .word 0x08009249 8009158: 08009249 .word 0x08009249 800915c: 0800919f .word 0x0800919f 8009160: 08009249 .word 0x08009249 8009164: 08009249 .word 0x08009249 8009168: 08009249 .word 0x08009249 800916c: 080091f7 .word 0x080091f7 8009170: 08009221 .word 0x08009221 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009174: 687b ldr r3, [r7, #4] 8009176: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800917a: b2db uxtb r3, r3 800917c: 2b03 cmp r3, #3 800917e: d107 bne.n 8009190 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 8009180: f107 030a add.w r3, r7, #10 8009184: 2202 movs r2, #2 8009186: 4619 mov r1, r3 8009188: 6878 ldr r0, [r7, #4] 800918a: f001 fbdd bl 800a948 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 800918e: e063 b.n 8009258 USBD_CtlError(pdev, req); 8009190: 6839 ldr r1, [r7, #0] 8009192: 6878 ldr r0, [r7, #4] 8009194: f001 fb5b bl 800a84e ret = USBD_FAIL; 8009198: 2303 movs r3, #3 800919a: 75fb strb r3, [r7, #23] break; 800919c: e05c b.n 8009258 case USB_REQ_GET_DESCRIPTOR: if ((req->wValue >> 8) == HID_REPORT_DESC) 800919e: 683b ldr r3, [r7, #0] 80091a0: 885b ldrh r3, [r3, #2] 80091a2: 0a1b lsrs r3, r3, #8 80091a4: b29b uxth r3, r3 80091a6: 2b22 cmp r3, #34 @ 0x22 80091a8: d108 bne.n 80091bc { len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); 80091aa: 683b ldr r3, [r7, #0] 80091ac: 88db ldrh r3, [r3, #6] 80091ae: 2b2d cmp r3, #45 @ 0x2d 80091b0: bf28 it cs 80091b2: 232d movcs r3, #45 @ 0x2d 80091b4: 82bb strh r3, [r7, #20] pbuf = HID_MOUSE_ReportDesc; 80091b6: 4b2f ldr r3, [pc, #188] @ (8009274 ) 80091b8: 613b str r3, [r7, #16] 80091ba: e015 b.n 80091e8 } else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) 80091bc: 683b ldr r3, [r7, #0] 80091be: 885b ldrh r3, [r3, #2] 80091c0: 0a1b lsrs r3, r3, #8 80091c2: b29b uxth r3, r3 80091c4: 2b21 cmp r3, #33 @ 0x21 80091c6: d108 bne.n 80091da { pbuf = USBD_HID_Desc; 80091c8: 4b2b ldr r3, [pc, #172] @ (8009278 ) 80091ca: 613b str r3, [r7, #16] len = MIN(USB_HID_DESC_SIZ, req->wLength); 80091cc: 683b ldr r3, [r7, #0] 80091ce: 88db ldrh r3, [r3, #6] 80091d0: 2b09 cmp r3, #9 80091d2: bf28 it cs 80091d4: 2309 movcs r3, #9 80091d6: 82bb strh r3, [r7, #20] 80091d8: e006 b.n 80091e8 } else { USBD_CtlError(pdev, req); 80091da: 6839 ldr r1, [r7, #0] 80091dc: 6878 ldr r0, [r7, #4] 80091de: f001 fb36 bl 800a84e ret = USBD_FAIL; 80091e2: 2303 movs r3, #3 80091e4: 75fb strb r3, [r7, #23] break; 80091e6: e037 b.n 8009258 } (void)USBD_CtlSendData(pdev, pbuf, len); 80091e8: 8abb ldrh r3, [r7, #20] 80091ea: 461a mov r2, r3 80091ec: 6939 ldr r1, [r7, #16] 80091ee: 6878 ldr r0, [r7, #4] 80091f0: f001 fbaa bl 800a948 break; 80091f4: e030 b.n 8009258 case USB_REQ_GET_INTERFACE : if (pdev->dev_state == USBD_STATE_CONFIGURED) 80091f6: 687b ldr r3, [r7, #4] 80091f8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80091fc: b2db uxtb r3, r3 80091fe: 2b03 cmp r3, #3 8009200: d107 bne.n 8009212 { (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); 8009202: 68fb ldr r3, [r7, #12] 8009204: 3308 adds r3, #8 8009206: 2201 movs r2, #1 8009208: 4619 mov r1, r3 800920a: 6878 ldr r0, [r7, #4] 800920c: f001 fb9c bl 800a948 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8009210: e022 b.n 8009258 USBD_CtlError(pdev, req); 8009212: 6839 ldr r1, [r7, #0] 8009214: 6878 ldr r0, [r7, #4] 8009216: f001 fb1a bl 800a84e ret = USBD_FAIL; 800921a: 2303 movs r3, #3 800921c: 75fb strb r3, [r7, #23] break; 800921e: e01b b.n 8009258 case USB_REQ_SET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009220: 687b ldr r3, [r7, #4] 8009222: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009226: b2db uxtb r3, r3 8009228: 2b03 cmp r3, #3 800922a: d106 bne.n 800923a { hhid->AltSetting = (uint8_t)(req->wValue); 800922c: 683b ldr r3, [r7, #0] 800922e: 885b ldrh r3, [r3, #2] 8009230: b2db uxtb r3, r3 8009232: 461a mov r2, r3 8009234: 68fb ldr r3, [r7, #12] 8009236: 609a str r2, [r3, #8] else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8009238: e00e b.n 8009258 USBD_CtlError(pdev, req); 800923a: 6839 ldr r1, [r7, #0] 800923c: 6878 ldr r0, [r7, #4] 800923e: f001 fb06 bl 800a84e ret = USBD_FAIL; 8009242: 2303 movs r3, #3 8009244: 75fb strb r3, [r7, #23] break; 8009246: e007 b.n 8009258 case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 8009248: 6839 ldr r1, [r7, #0] 800924a: 6878 ldr r0, [r7, #4] 800924c: f001 faff bl 800a84e ret = USBD_FAIL; 8009250: 2303 movs r3, #3 8009252: 75fb strb r3, [r7, #23] break; 8009254: e000 b.n 8009258 break; 8009256: bf00 nop } break; 8009258: e006 b.n 8009268 default: USBD_CtlError(pdev, req); 800925a: 6839 ldr r1, [r7, #0] 800925c: 6878 ldr r0, [r7, #4] 800925e: f001 faf6 bl 800a84e ret = USBD_FAIL; 8009262: 2303 movs r3, #3 8009264: 75fb strb r3, [r7, #23] break; 8009266: bf00 nop } return (uint8_t)ret; 8009268: 7dfb ldrb r3, [r7, #23] } 800926a: 4618 mov r0, r3 800926c: 3718 adds r7, #24 800926e: 46bd mov sp, r7 8009270: bd80 pop {r7, pc} 8009272: bf00 nop 8009274: 20000184 .word 0x20000184 8009278: 2000016c .word 0x2000016c 0800927c : uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId) { USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) { 800927c: b580 push {r7, lr} 800927e: b086 sub sp, #24 8009280: af00 add r7, sp, #0 8009282: 60f8 str r0, [r7, #12] 8009284: 60b9 str r1, [r7, #8] 8009286: 4613 mov r3, r2 8009288: 80fb strh r3, [r7, #6] USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 800928a: 68fb ldr r3, [r7, #12] 800928c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009290: 68fb ldr r3, [r7, #12] 8009292: 32b0 adds r2, #176 @ 0xb0 8009294: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009298: 617b str r3, [r7, #20] #endif /* USE_USBD_COMPOSITE */ if (hhid == NULL) 800929a: 697b ldr r3, [r7, #20] 800929c: 2b00 cmp r3, #0 800929e: d101 bne.n 80092a4 { return (uint8_t)USBD_FAIL; 80092a0: 2303 movs r3, #3 80092a2: e014 b.n 80092ce #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 80092a4: 68fb ldr r3, [r7, #12] 80092a6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80092aa: b2db uxtb r3, r3 80092ac: 2b03 cmp r3, #3 80092ae: d10d bne.n 80092cc { if (hhid->state == USBD_HID_IDLE) 80092b0: 697b ldr r3, [r7, #20] 80092b2: 7b1b ldrb r3, [r3, #12] 80092b4: 2b00 cmp r3, #0 80092b6: d109 bne.n 80092cc { hhid->state = USBD_HID_BUSY; 80092b8: 697b ldr r3, [r7, #20] 80092ba: 2201 movs r2, #1 80092bc: 731a strb r2, [r3, #12] (void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len); 80092be: 4b06 ldr r3, [pc, #24] @ (80092d8 ) 80092c0: 7819 ldrb r1, [r3, #0] 80092c2: 88fb ldrh r3, [r7, #6] 80092c4: 68ba ldr r2, [r7, #8] 80092c6: 68f8 ldr r0, [r7, #12] 80092c8: f001 ff7d bl 800b1c6 } } return (uint8_t)USBD_OK; 80092cc: 2300 movs r3, #0 } 80092ce: 4618 mov r0, r3 80092d0: 3718 adds r7, #24 80092d2: 46bd mov sp, r7 80092d4: bd80 pop {r7, pc} 80092d6: bf00 nop 80092d8: 200001b1 .word 0x200001b1 080092dc : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) { 80092dc: b580 push {r7, lr} 80092de: b084 sub sp, #16 80092e0: af00 add r7, sp, #0 80092e2: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 80092e4: 2181 movs r1, #129 @ 0x81 80092e6: 4809 ldr r0, [pc, #36] @ (800930c ) 80092e8: f000 fc4e bl 8009b88 80092ec: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 80092ee: 68fb ldr r3, [r7, #12] 80092f0: 2b00 cmp r3, #0 80092f2: d002 beq.n 80092fa { pEpDesc->bInterval = HID_FS_BINTERVAL; 80092f4: 68fb ldr r3, [r7, #12] 80092f6: 220a movs r2, #10 80092f8: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 80092fa: 687b ldr r3, [r7, #4] 80092fc: 2222 movs r2, #34 @ 0x22 80092fe: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8009300: 4b02 ldr r3, [pc, #8] @ (800930c ) } 8009302: 4618 mov r0, r3 8009304: 3710 adds r7, #16 8009306: 46bd mov sp, r7 8009308: bd80 pop {r7, pc} 800930a: bf00 nop 800930c: 20000148 .word 0x20000148 08009310 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) { 8009310: b580 push {r7, lr} 8009312: b084 sub sp, #16 8009314: af00 add r7, sp, #0 8009316: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 8009318: 2181 movs r1, #129 @ 0x81 800931a: 4809 ldr r0, [pc, #36] @ (8009340 ) 800931c: f000 fc34 bl 8009b88 8009320: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 8009322: 68fb ldr r3, [r7, #12] 8009324: 2b00 cmp r3, #0 8009326: d002 beq.n 800932e { pEpDesc->bInterval = HID_HS_BINTERVAL; 8009328: 68fb ldr r3, [r7, #12] 800932a: 2207 movs r2, #7 800932c: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 800932e: 687b ldr r3, [r7, #4] 8009330: 2222 movs r2, #34 @ 0x22 8009332: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8009334: 4b02 ldr r3, [pc, #8] @ (8009340 ) } 8009336: 4618 mov r0, r3 8009338: 3710 adds r7, #16 800933a: 46bd mov sp, r7 800933c: bd80 pop {r7, pc} 800933e: bf00 nop 8009340: 20000148 .word 0x20000148 08009344 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) { 8009344: b580 push {r7, lr} 8009346: b084 sub sp, #16 8009348: af00 add r7, sp, #0 800934a: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); 800934c: 2181 movs r1, #129 @ 0x81 800934e: 4809 ldr r0, [pc, #36] @ (8009374 ) 8009350: f000 fc1a bl 8009b88 8009354: 60f8 str r0, [r7, #12] if (pEpDesc != NULL) 8009356: 68fb ldr r3, [r7, #12] 8009358: 2b00 cmp r3, #0 800935a: d002 beq.n 8009362 { pEpDesc->bInterval = HID_FS_BINTERVAL; 800935c: 68fb ldr r3, [r7, #12] 800935e: 220a movs r2, #10 8009360: 719a strb r2, [r3, #6] } *length = (uint16_t)sizeof(USBD_HID_CfgDesc); 8009362: 687b ldr r3, [r7, #4] 8009364: 2222 movs r2, #34 @ 0x22 8009366: 801a strh r2, [r3, #0] return USBD_HID_CfgDesc; 8009368: 4b02 ldr r3, [pc, #8] @ (8009374 ) } 800936a: 4618 mov r0, r3 800936c: 3710 adds r7, #16 800936e: 46bd mov sp, r7 8009370: bd80 pop {r7, pc} 8009372: bf00 nop 8009374: 20000148 .word 0x20000148 08009378 : * @param pdev: device instance * @param epnum: endpoint index * @retval status */ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009378: b480 push {r7} 800937a: b083 sub sp, #12 800937c: af00 add r7, sp, #0 800937e: 6078 str r0, [r7, #4] 8009380: 460b mov r3, r1 8009382: 70fb strb r3, [r7, #3] UNUSED(epnum); /* Ensure that the FIFO is empty before a new transfer, this condition could be caused by a new transfer before the end of the previous transfer */ ((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE; 8009384: 687b ldr r3, [r7, #4] 8009386: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800938a: 687b ldr r3, [r7, #4] 800938c: 32b0 adds r2, #176 @ 0xb0 800938e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009392: 2200 movs r2, #0 8009394: 731a strb r2, [r3, #12] return (uint8_t)USBD_OK; 8009396: 2300 movs r3, #0 } 8009398: 4618 mov r0, r3 800939a: 370c adds r7, #12 800939c: 46bd mov sp, r7 800939e: f85d 7b04 ldr.w r7, [sp], #4 80093a2: 4770 bx lr 080093a4 : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) { 80093a4: b480 push {r7} 80093a6: b083 sub sp, #12 80093a8: af00 add r7, sp, #0 80093aa: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); 80093ac: 687b ldr r3, [r7, #4] 80093ae: 220a movs r2, #10 80093b0: 801a strh r2, [r3, #0] return USBD_HID_DeviceQualifierDesc; 80093b2: 4b03 ldr r3, [pc, #12] @ (80093c0 ) } 80093b4: 4618 mov r0, r3 80093b6: 370c adds r7, #12 80093b8: 46bd mov sp, r7 80093ba: f85d 7b04 ldr.w r7, [sp], #4 80093be: 4770 bx lr 80093c0: 20000178 .word 0x20000178 080093c4 : * @param id: Low level core index * @retval status: USBD Status */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 80093c4: b580 push {r7, lr} 80093c6: b086 sub sp, #24 80093c8: af00 add r7, sp, #0 80093ca: 60f8 str r0, [r7, #12] 80093cc: 60b9 str r1, [r7, #8] 80093ce: 4613 mov r3, r2 80093d0: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 80093d2: 68fb ldr r3, [r7, #12] 80093d4: 2b00 cmp r3, #0 80093d6: d101 bne.n 80093dc { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 80093d8: 2303 movs r3, #3 80093da: e01f b.n 800941c pdev->NumClasses = 0; pdev->classId = 0; } #else /* Unlink previous class*/ pdev->pClass[0] = NULL; 80093dc: 68fb ldr r3, [r7, #12] 80093de: 2200 movs r2, #0 80093e0: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 pdev->pUserData[0] = NULL; 80093e4: 68fb ldr r3, [r7, #12] 80093e6: 2200 movs r2, #0 80093e8: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4 #endif /* USE_USBD_COMPOSITE */ pdev->pConfDesc = NULL; 80093ec: 68fb ldr r3, [r7, #12] 80093ee: 2200 movs r2, #0 80093f0: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 /* Assign USBD Descriptors */ if (pdesc != NULL) 80093f4: 68bb ldr r3, [r7, #8] 80093f6: 2b00 cmp r3, #0 80093f8: d003 beq.n 8009402 { pdev->pDesc = pdesc; 80093fa: 68fb ldr r3, [r7, #12] 80093fc: 68ba ldr r2, [r7, #8] 80093fe: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 8009402: 68fb ldr r3, [r7, #12] 8009404: 2201 movs r2, #1 8009406: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->id = id; 800940a: 68fb ldr r3, [r7, #12] 800940c: 79fa ldrb r2, [r7, #7] 800940e: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 8009410: 68f8 ldr r0, [r7, #12] 8009412: f001 fda3 bl 800af5c 8009416: 4603 mov r3, r0 8009418: 75fb strb r3, [r7, #23] return ret; 800941a: 7dfb ldrb r3, [r7, #23] } 800941c: 4618 mov r0, r3 800941e: 3718 adds r7, #24 8009420: 46bd mov sp, r7 8009422: bd80 pop {r7, pc} 08009424 : * @param pdev: Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 8009424: b580 push {r7, lr} 8009426: b084 sub sp, #16 8009428: af00 add r7, sp, #0 800942a: 6078 str r0, [r7, #4] 800942c: 6039 str r1, [r7, #0] uint16_t len = 0U; 800942e: 2300 movs r3, #0 8009430: 81fb strh r3, [r7, #14] if (pclass == NULL) 8009432: 683b ldr r3, [r7, #0] 8009434: 2b00 cmp r3, #0 8009436: d101 bne.n 800943c { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8009438: 2303 movs r3, #3 800943a: e025 b.n 8009488 } /* link the class to the USB Device handle */ pdev->pClass[0] = pclass; 800943c: 687b ldr r3, [r7, #4] 800943e: 683a ldr r2, [r7, #0] 8009440: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) 8009444: 687b ldr r3, [r7, #4] 8009446: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800944a: 687b ldr r3, [r7, #4] 800944c: 32ae adds r2, #174 @ 0xae 800944e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009452: 6adb ldr r3, [r3, #44] @ 0x2c 8009454: 2b00 cmp r3, #0 8009456: d00f beq.n 8009478 { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); 8009458: 687b ldr r3, [r7, #4] 800945a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 800945e: 687b ldr r3, [r7, #4] 8009460: 32ae adds r2, #174 @ 0xae 8009462: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009466: 6adb ldr r3, [r3, #44] @ 0x2c 8009468: f107 020e add.w r2, r7, #14 800946c: 4610 mov r0, r2 800946e: 4798 blx r3 8009470: 4602 mov r2, r0 8009472: 687b ldr r3, [r7, #4] 8009474: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 } #endif /* USE_USB_FS */ /* Increment the NumClasses */ pdev->NumClasses++; 8009478: 687b ldr r3, [r7, #4] 800947a: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 800947e: 1c5a adds r2, r3, #1 8009480: 687b ldr r3, [r7, #4] 8009482: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8 return USBD_OK; 8009486: 2300 movs r3, #0 } 8009488: 4618 mov r0, r3 800948a: 3710 adds r7, #16 800948c: 46bd mov sp, r7 800948e: bd80 pop {r7, pc} 08009490 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 8009490: b580 push {r7, lr} 8009492: b082 sub sp, #8 8009494: af00 add r7, sp, #0 8009496: 6078 str r0, [r7, #4] #ifdef USE_USBD_COMPOSITE pdev->classId = 0U; #endif /* USE_USBD_COMPOSITE */ /* Start the low level driver */ return USBD_LL_Start(pdev); 8009498: 6878 ldr r0, [r7, #4] 800949a: f001 fdab bl 800aff4 800949e: 4603 mov r3, r0 } 80094a0: 4618 mov r0, r3 80094a2: 3708 adds r7, #8 80094a4: 46bd mov sp, r7 80094a6: bd80 pop {r7, pc} 080094a8 : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 80094a8: b480 push {r7} 80094aa: b083 sub sp, #12 80094ac: af00 add r7, sp, #0 80094ae: 6078 str r0, [r7, #4] return ret; #else /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 80094b0: 2300 movs r3, #0 #endif /* USBD_HS_TESTMODE_ENABLE */ } 80094b2: 4618 mov r0, r3 80094b4: 370c adds r7, #12 80094b6: 46bd mov sp, r7 80094b8: f85d 7b04 ldr.w r7, [sp], #4 80094bc: 4770 bx lr 080094be : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80094be: b580 push {r7, lr} 80094c0: b084 sub sp, #16 80094c2: af00 add r7, sp, #0 80094c4: 6078 str r0, [r7, #4] 80094c6: 460b mov r3, r1 80094c8: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 80094ca: 2300 movs r3, #0 80094cc: 73fb strb r3, [r7, #15] } } } } #else if (pdev->pClass[0] != NULL) 80094ce: 687b ldr r3, [r7, #4] 80094d0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80094d4: 2b00 cmp r3, #0 80094d6: d009 beq.n 80094ec { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); 80094d8: 687b ldr r3, [r7, #4] 80094da: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80094de: 681b ldr r3, [r3, #0] 80094e0: 78fa ldrb r2, [r7, #3] 80094e2: 4611 mov r1, r2 80094e4: 6878 ldr r0, [r7, #4] 80094e6: 4798 blx r3 80094e8: 4603 mov r3, r0 80094ea: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 80094ec: 7bfb ldrb r3, [r7, #15] } 80094ee: 4618 mov r0, r3 80094f0: 3710 adds r7, #16 80094f2: 46bd mov sp, r7 80094f4: bd80 pop {r7, pc} 080094f6 : * @param pdev: device instance * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80094f6: b580 push {r7, lr} 80094f8: b084 sub sp, #16 80094fa: af00 add r7, sp, #0 80094fc: 6078 str r0, [r7, #4] 80094fe: 460b mov r3, r1 8009500: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8009502: 2300 movs r3, #0 8009504: 73fb strb r3, [r7, #15] } } } #else /* Clear configuration and De-initialize the Class process */ if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) 8009506: 687b ldr r3, [r7, #4] 8009508: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800950c: 685b ldr r3, [r3, #4] 800950e: 78fa ldrb r2, [r7, #3] 8009510: 4611 mov r1, r2 8009512: 6878 ldr r0, [r7, #4] 8009514: 4798 blx r3 8009516: 4603 mov r3, r0 8009518: 2b00 cmp r3, #0 800951a: d001 beq.n 8009520 { ret = USBD_FAIL; 800951c: 2303 movs r3, #3 800951e: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8009520: 7bfb ldrb r3, [r7, #15] } 8009522: 4618 mov r0, r3 8009524: 3710 adds r7, #16 8009526: 46bd mov sp, r7 8009528: bd80 pop {r7, pc} 0800952a : * @param pdev: device instance * @param psetup: setup packet buffer pointer * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 800952a: b580 push {r7, lr} 800952c: b084 sub sp, #16 800952e: af00 add r7, sp, #0 8009530: 6078 str r0, [r7, #4] 8009532: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 8009534: 687b ldr r3, [r7, #4] 8009536: f203 23aa addw r3, r3, #682 @ 0x2aa 800953a: 6839 ldr r1, [r7, #0] 800953c: 4618 mov r0, r3 800953e: f001 f94c bl 800a7da pdev->ep0_state = USBD_EP0_SETUP; 8009542: 687b ldr r3, [r7, #4] 8009544: 2201 movs r2, #1 8009546: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep0_data_len = pdev->request.wLength; 800954a: 687b ldr r3, [r7, #4] 800954c: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0 8009550: 461a mov r2, r3 8009552: 687b ldr r3, [r7, #4] 8009554: f8c3 2298 str.w r2, [r3, #664] @ 0x298 switch (pdev->request.bmRequest & 0x1FU) 8009558: 687b ldr r3, [r7, #4] 800955a: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 800955e: f003 031f and.w r3, r3, #31 8009562: 2b02 cmp r3, #2 8009564: d01a beq.n 800959c 8009566: 2b02 cmp r3, #2 8009568: d822 bhi.n 80095b0 800956a: 2b00 cmp r3, #0 800956c: d002 beq.n 8009574 800956e: 2b01 cmp r3, #1 8009570: d00a beq.n 8009588 8009572: e01d b.n 80095b0 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 8009574: 687b ldr r3, [r7, #4] 8009576: f203 23aa addw r3, r3, #682 @ 0x2aa 800957a: 4619 mov r1, r3 800957c: 6878 ldr r0, [r7, #4] 800957e: f000 fb77 bl 8009c70 8009582: 4603 mov r3, r0 8009584: 73fb strb r3, [r7, #15] break; 8009586: e020 b.n 80095ca case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 8009588: 687b ldr r3, [r7, #4] 800958a: f203 23aa addw r3, r3, #682 @ 0x2aa 800958e: 4619 mov r1, r3 8009590: 6878 ldr r0, [r7, #4] 8009592: f000 fbdf bl 8009d54 8009596: 4603 mov r3, r0 8009598: 73fb strb r3, [r7, #15] break; 800959a: e016 b.n 80095ca case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 800959c: 687b ldr r3, [r7, #4] 800959e: f203 23aa addw r3, r3, #682 @ 0x2aa 80095a2: 4619 mov r1, r3 80095a4: 6878 ldr r0, [r7, #4] 80095a6: f000 fc41 bl 8009e2c 80095aa: 4603 mov r3, r0 80095ac: 73fb strb r3, [r7, #15] break; 80095ae: e00c b.n 80095ca default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 80095b0: 687b ldr r3, [r7, #4] 80095b2: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 80095b6: f023 037f bic.w r3, r3, #127 @ 0x7f 80095ba: b2db uxtb r3, r3 80095bc: 4619 mov r1, r3 80095be: 6878 ldr r0, [r7, #4] 80095c0: f001 fd78 bl 800b0b4 80095c4: 4603 mov r3, r0 80095c6: 73fb strb r3, [r7, #15] break; 80095c8: bf00 nop } return ret; 80095ca: 7bfb ldrb r3, [r7, #15] } 80095cc: 4618 mov r0, r3 80095ce: 3710 adds r7, #16 80095d0: 46bd mov sp, r7 80095d2: bd80 pop {r7, pc} 080095d4 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 80095d4: b580 push {r7, lr} 80095d6: b086 sub sp, #24 80095d8: af00 add r7, sp, #0 80095da: 60f8 str r0, [r7, #12] 80095dc: 460b mov r3, r1 80095de: 607a str r2, [r7, #4] 80095e0: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret = USBD_OK; 80095e2: 2300 movs r3, #0 80095e4: 75fb strb r3, [r7, #23] uint8_t idx; UNUSED(pdata); if (epnum == 0U) 80095e6: 7afb ldrb r3, [r7, #11] 80095e8: 2b00 cmp r3, #0 80095ea: d177 bne.n 80096dc { pep = &pdev->ep_out[0]; 80095ec: 68fb ldr r3, [r7, #12] 80095ee: f503 73aa add.w r3, r3, #340 @ 0x154 80095f2: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 80095f4: 68fb ldr r3, [r7, #12] 80095f6: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 80095fa: 2b03 cmp r3, #3 80095fc: f040 80a1 bne.w 8009742 { if (pep->rem_length > pep->maxpacket) 8009600: 693b ldr r3, [r7, #16] 8009602: 685b ldr r3, [r3, #4] 8009604: 693a ldr r2, [r7, #16] 8009606: 8992 ldrh r2, [r2, #12] 8009608: 4293 cmp r3, r2 800960a: d91c bls.n 8009646 { pep->rem_length -= pep->maxpacket; 800960c: 693b ldr r3, [r7, #16] 800960e: 685b ldr r3, [r3, #4] 8009610: 693a ldr r2, [r7, #16] 8009612: 8992 ldrh r2, [r2, #12] 8009614: 1a9a subs r2, r3, r2 8009616: 693b ldr r3, [r7, #16] 8009618: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 800961a: 693b ldr r3, [r7, #16] 800961c: 691b ldr r3, [r3, #16] 800961e: 693a ldr r2, [r7, #16] 8009620: 8992 ldrh r2, [r2, #12] 8009622: 441a add r2, r3 8009624: 693b ldr r3, [r7, #16] 8009626: 611a str r2, [r3, #16] (void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket)); 8009628: 693b ldr r3, [r7, #16] 800962a: 6919 ldr r1, [r3, #16] 800962c: 693b ldr r3, [r7, #16] 800962e: 899b ldrh r3, [r3, #12] 8009630: 461a mov r2, r3 8009632: 693b ldr r3, [r7, #16] 8009634: 685b ldr r3, [r3, #4] 8009636: 4293 cmp r3, r2 8009638: bf38 it cc 800963a: 4613 movcc r3, r2 800963c: 461a mov r2, r3 800963e: 68f8 ldr r0, [r7, #12] 8009640: f001 f9b1 bl 800a9a6 8009644: e07d b.n 8009742 } else { /* Find the class ID relative to the current request */ switch (pdev->request.bmRequest & 0x1FU) 8009646: 68fb ldr r3, [r7, #12] 8009648: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 800964c: f003 031f and.w r3, r3, #31 8009650: 2b02 cmp r3, #2 8009652: d014 beq.n 800967e 8009654: 2b02 cmp r3, #2 8009656: d81d bhi.n 8009694 8009658: 2b00 cmp r3, #0 800965a: d002 beq.n 8009662 800965c: 2b01 cmp r3, #1 800965e: d003 beq.n 8009668 8009660: e018 b.n 8009694 { case USB_REQ_RECIPIENT_DEVICE: /* Device requests must be managed by the first instantiated class (or duplicated by all classes for simplicity) */ idx = 0U; 8009662: 2300 movs r3, #0 8009664: 75bb strb r3, [r7, #22] break; 8009666: e018 b.n 800969a case USB_REQ_RECIPIENT_INTERFACE: idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); 8009668: 68fb ldr r3, [r7, #12] 800966a: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 800966e: b2db uxtb r3, r3 8009670: 4619 mov r1, r3 8009672: 68f8 ldr r0, [r7, #12] 8009674: f000 fa6e bl 8009b54 8009678: 4603 mov r3, r0 800967a: 75bb strb r3, [r7, #22] break; 800967c: e00d b.n 800969a case USB_REQ_RECIPIENT_ENDPOINT: idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); 800967e: 68fb ldr r3, [r7, #12] 8009680: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8009684: b2db uxtb r3, r3 8009686: 4619 mov r1, r3 8009688: 68f8 ldr r0, [r7, #12] 800968a: f000 fa70 bl 8009b6e 800968e: 4603 mov r3, r0 8009690: 75bb strb r3, [r7, #22] break; 8009692: e002 b.n 800969a default: /* Back to the first class in case of doubt */ idx = 0U; 8009694: 2300 movs r3, #0 8009696: 75bb strb r3, [r7, #22] break; 8009698: bf00 nop } if (idx < USBD_MAX_SUPPORTED_CLASS) 800969a: 7dbb ldrb r3, [r7, #22] 800969c: 2b00 cmp r3, #0 800969e: d119 bne.n 80096d4 { /* Setup the class ID and route the request to the relative class function */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 80096a0: 68fb ldr r3, [r7, #12] 80096a2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80096a6: b2db uxtb r3, r3 80096a8: 2b03 cmp r3, #3 80096aa: d113 bne.n 80096d4 { if (pdev->pClass[idx]->EP0_RxReady != NULL) 80096ac: 7dba ldrb r2, [r7, #22] 80096ae: 68fb ldr r3, [r7, #12] 80096b0: 32ae adds r2, #174 @ 0xae 80096b2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80096b6: 691b ldr r3, [r3, #16] 80096b8: 2b00 cmp r3, #0 80096ba: d00b beq.n 80096d4 { pdev->classId = idx; 80096bc: 7dba ldrb r2, [r7, #22] 80096be: 68fb ldr r3, [r7, #12] 80096c0: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[idx]->EP0_RxReady(pdev); 80096c4: 7dba ldrb r2, [r7, #22] 80096c6: 68fb ldr r3, [r7, #12] 80096c8: 32ae adds r2, #174 @ 0xae 80096ca: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80096ce: 691b ldr r3, [r3, #16] 80096d0: 68f8 ldr r0, [r7, #12] 80096d2: 4798 blx r3 } } } (void)USBD_CtlSendStatus(pdev); 80096d4: 68f8 ldr r0, [r7, #12] 80096d6: f001 f977 bl 800a9c8 80096da: e032 b.n 8009742 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); 80096dc: 7afb ldrb r3, [r7, #11] 80096de: f003 037f and.w r3, r3, #127 @ 0x7f 80096e2: b2db uxtb r3, r3 80096e4: 4619 mov r1, r3 80096e6: 68f8 ldr r0, [r7, #12] 80096e8: f000 fa41 bl 8009b6e 80096ec: 4603 mov r3, r0 80096ee: 75bb strb r3, [r7, #22] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 80096f0: 7dbb ldrb r3, [r7, #22] 80096f2: 2bff cmp r3, #255 @ 0xff 80096f4: d025 beq.n 8009742 80096f6: 7dbb ldrb r3, [r7, #22] 80096f8: 2b00 cmp r3, #0 80096fa: d122 bne.n 8009742 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 80096fc: 68fb ldr r3, [r7, #12] 80096fe: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009702: b2db uxtb r3, r3 8009704: 2b03 cmp r3, #3 8009706: d117 bne.n 8009738 { if (pdev->pClass[idx]->DataOut != NULL) 8009708: 7dba ldrb r2, [r7, #22] 800970a: 68fb ldr r3, [r7, #12] 800970c: 32ae adds r2, #174 @ 0xae 800970e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009712: 699b ldr r3, [r3, #24] 8009714: 2b00 cmp r3, #0 8009716: d00f beq.n 8009738 { pdev->classId = idx; 8009718: 7dba ldrb r2, [r7, #22] 800971a: 68fb ldr r3, [r7, #12] 800971c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); 8009720: 7dba ldrb r2, [r7, #22] 8009722: 68fb ldr r3, [r7, #12] 8009724: 32ae adds r2, #174 @ 0xae 8009726: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800972a: 699b ldr r3, [r3, #24] 800972c: 7afa ldrb r2, [r7, #11] 800972e: 4611 mov r1, r2 8009730: 68f8 ldr r0, [r7, #12] 8009732: 4798 blx r3 8009734: 4603 mov r3, r0 8009736: 75fb strb r3, [r7, #23] } } if (ret != USBD_OK) 8009738: 7dfb ldrb r3, [r7, #23] 800973a: 2b00 cmp r3, #0 800973c: d001 beq.n 8009742 { return ret; 800973e: 7dfb ldrb r3, [r7, #23] 8009740: e000 b.n 8009744 } } } return USBD_OK; 8009742: 2300 movs r3, #0 } 8009744: 4618 mov r0, r3 8009746: 3718 adds r7, #24 8009748: 46bd mov sp, r7 800974a: bd80 pop {r7, pc} 0800974c : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 800974c: b580 push {r7, lr} 800974e: b086 sub sp, #24 8009750: af00 add r7, sp, #0 8009752: 60f8 str r0, [r7, #12] 8009754: 460b mov r3, r1 8009756: 607a str r2, [r7, #4] 8009758: 72fb strb r3, [r7, #11] USBD_StatusTypeDef ret; uint8_t idx; UNUSED(pdata); if (epnum == 0U) 800975a: 7afb ldrb r3, [r7, #11] 800975c: 2b00 cmp r3, #0 800975e: d178 bne.n 8009852 { pep = &pdev->ep_in[0]; 8009760: 68fb ldr r3, [r7, #12] 8009762: 3314 adds r3, #20 8009764: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 8009766: 68fb ldr r3, [r7, #12] 8009768: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 800976c: 2b02 cmp r3, #2 800976e: d163 bne.n 8009838 { if (pep->rem_length > pep->maxpacket) 8009770: 693b ldr r3, [r7, #16] 8009772: 685b ldr r3, [r3, #4] 8009774: 693a ldr r2, [r7, #16] 8009776: 8992 ldrh r2, [r2, #12] 8009778: 4293 cmp r3, r2 800977a: d91c bls.n 80097b6 { pep->rem_length -= pep->maxpacket; 800977c: 693b ldr r3, [r7, #16] 800977e: 685b ldr r3, [r3, #4] 8009780: 693a ldr r2, [r7, #16] 8009782: 8992 ldrh r2, [r2, #12] 8009784: 1a9a subs r2, r3, r2 8009786: 693b ldr r3, [r7, #16] 8009788: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 800978a: 693b ldr r3, [r7, #16] 800978c: 691b ldr r3, [r3, #16] 800978e: 693a ldr r2, [r7, #16] 8009790: 8992 ldrh r2, [r2, #12] 8009792: 441a add r2, r3 8009794: 693b ldr r3, [r7, #16] 8009796: 611a str r2, [r3, #16] (void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length); 8009798: 693b ldr r3, [r7, #16] 800979a: 6919 ldr r1, [r3, #16] 800979c: 693b ldr r3, [r7, #16] 800979e: 685b ldr r3, [r3, #4] 80097a0: 461a mov r2, r3 80097a2: 68f8 ldr r0, [r7, #12] 80097a4: f001 f8ee bl 800a984 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 80097a8: 2300 movs r3, #0 80097aa: 2200 movs r2, #0 80097ac: 2100 movs r1, #0 80097ae: 68f8 ldr r0, [r7, #12] 80097b0: f001 fd2a bl 800b208 80097b4: e040 b.n 8009838 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 80097b6: 693b ldr r3, [r7, #16] 80097b8: 899b ldrh r3, [r3, #12] 80097ba: 461a mov r2, r3 80097bc: 693b ldr r3, [r7, #16] 80097be: 685b ldr r3, [r3, #4] 80097c0: 429a cmp r2, r3 80097c2: d11c bne.n 80097fe (pep->total_length >= pep->maxpacket) && 80097c4: 693b ldr r3, [r7, #16] 80097c6: 681b ldr r3, [r3, #0] 80097c8: 693a ldr r2, [r7, #16] 80097ca: 8992 ldrh r2, [r2, #12] if ((pep->maxpacket == pep->rem_length) && 80097cc: 4293 cmp r3, r2 80097ce: d316 bcc.n 80097fe (pep->total_length < pdev->ep0_data_len)) 80097d0: 693b ldr r3, [r7, #16] 80097d2: 681a ldr r2, [r3, #0] 80097d4: 68fb ldr r3, [r7, #12] 80097d6: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 (pep->total_length >= pep->maxpacket) && 80097da: 429a cmp r2, r3 80097dc: d20f bcs.n 80097fe { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 80097de: 2200 movs r2, #0 80097e0: 2100 movs r1, #0 80097e2: 68f8 ldr r0, [r7, #12] 80097e4: f001 f8ce bl 800a984 pdev->ep0_data_len = 0U; 80097e8: 68fb ldr r3, [r7, #12] 80097ea: 2200 movs r2, #0 80097ec: f8c3 2298 str.w r2, [r3, #664] @ 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 80097f0: 2300 movs r3, #0 80097f2: 2200 movs r2, #0 80097f4: 2100 movs r1, #0 80097f6: 68f8 ldr r0, [r7, #12] 80097f8: f001 fd06 bl 800b208 80097fc: e01c b.n 8009838 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 80097fe: 68fb ldr r3, [r7, #12] 8009800: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009804: b2db uxtb r3, r3 8009806: 2b03 cmp r3, #3 8009808: d10f bne.n 800982a { if (pdev->pClass[0]->EP0_TxSent != NULL) 800980a: 68fb ldr r3, [r7, #12] 800980c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009810: 68db ldr r3, [r3, #12] 8009812: 2b00 cmp r3, #0 8009814: d009 beq.n 800982a { pdev->classId = 0U; 8009816: 68fb ldr r3, [r7, #12] 8009818: 2200 movs r2, #0 800981a: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[0]->EP0_TxSent(pdev); 800981e: 68fb ldr r3, [r7, #12] 8009820: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009824: 68db ldr r3, [r3, #12] 8009826: 68f8 ldr r0, [r7, #12] 8009828: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 800982a: 2180 movs r1, #128 @ 0x80 800982c: 68f8 ldr r0, [r7, #12] 800982e: f001 fc41 bl 800b0b4 (void)USBD_CtlReceiveStatus(pdev); 8009832: 68f8 ldr r0, [r7, #12] 8009834: f001 f8db bl 800a9ee } } } if (pdev->dev_test_mode != 0U) 8009838: 68fb ldr r3, [r7, #12] 800983a: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 800983e: 2b00 cmp r3, #0 8009840: d03a beq.n 80098b8 { (void)USBD_RunTestMode(pdev); 8009842: 68f8 ldr r0, [r7, #12] 8009844: f7ff fe30 bl 80094a8 pdev->dev_test_mode = 0U; 8009848: 68fb ldr r3, [r7, #12] 800984a: 2200 movs r2, #0 800984c: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 8009850: e032 b.n 80098b8 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); 8009852: 7afb ldrb r3, [r7, #11] 8009854: f063 037f orn r3, r3, #127 @ 0x7f 8009858: b2db uxtb r3, r3 800985a: 4619 mov r1, r3 800985c: 68f8 ldr r0, [r7, #12] 800985e: f000 f986 bl 8009b6e 8009862: 4603 mov r3, r0 8009864: 75fb strb r3, [r7, #23] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009866: 7dfb ldrb r3, [r7, #23] 8009868: 2bff cmp r3, #255 @ 0xff 800986a: d025 beq.n 80098b8 800986c: 7dfb ldrb r3, [r7, #23] 800986e: 2b00 cmp r3, #0 8009870: d122 bne.n 80098b8 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009872: 68fb ldr r3, [r7, #12] 8009874: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009878: b2db uxtb r3, r3 800987a: 2b03 cmp r3, #3 800987c: d11c bne.n 80098b8 { if (pdev->pClass[idx]->DataIn != NULL) 800987e: 7dfa ldrb r2, [r7, #23] 8009880: 68fb ldr r3, [r7, #12] 8009882: 32ae adds r2, #174 @ 0xae 8009884: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009888: 695b ldr r3, [r3, #20] 800988a: 2b00 cmp r3, #0 800988c: d014 beq.n 80098b8 { pdev->classId = idx; 800988e: 7dfa ldrb r2, [r7, #23] 8009890: 68fb ldr r3, [r7, #12] 8009892: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); 8009896: 7dfa ldrb r2, [r7, #23] 8009898: 68fb ldr r3, [r7, #12] 800989a: 32ae adds r2, #174 @ 0xae 800989c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80098a0: 695b ldr r3, [r3, #20] 80098a2: 7afa ldrb r2, [r7, #11] 80098a4: 4611 mov r1, r2 80098a6: 68f8 ldr r0, [r7, #12] 80098a8: 4798 blx r3 80098aa: 4603 mov r3, r0 80098ac: 75bb strb r3, [r7, #22] if (ret != USBD_OK) 80098ae: 7dbb ldrb r3, [r7, #22] 80098b0: 2b00 cmp r3, #0 80098b2: d001 beq.n 80098b8 { return ret; 80098b4: 7dbb ldrb r3, [r7, #22] 80098b6: e000 b.n 80098ba } } } } return USBD_OK; 80098b8: 2300 movs r3, #0 } 80098ba: 4618 mov r0, r3 80098bc: 3718 adds r7, #24 80098be: 46bd mov sp, r7 80098c0: bd80 pop {r7, pc} 080098c2 : * Handle Reset event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 80098c2: b580 push {r7, lr} 80098c4: b084 sub sp, #16 80098c6: af00 add r7, sp, #0 80098c8: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 80098ca: 2300 movs r3, #0 80098cc: 73fb strb r3, [r7, #15] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 80098ce: 687b ldr r3, [r7, #4] 80098d0: 2201 movs r2, #1 80098d2: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->ep0_state = USBD_EP0_IDLE; 80098d6: 687b ldr r3, [r7, #4] 80098d8: 2200 movs r2, #0 80098da: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->dev_config = 0U; 80098de: 687b ldr r3, [r7, #4] 80098e0: 2200 movs r2, #0 80098e2: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 80098e4: 687b ldr r3, [r7, #4] 80098e6: 2200 movs r2, #0 80098e8: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 pdev->dev_test_mode = 0U; 80098ec: 687b ldr r3, [r7, #4] 80098ee: 2200 movs r2, #0 80098f0: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 } } } #else if (pdev->pClass[0] != NULL) 80098f4: 687b ldr r3, [r7, #4] 80098f6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80098fa: 2b00 cmp r3, #0 80098fc: d014 beq.n 8009928 { if (pdev->pClass[0]->DeInit != NULL) 80098fe: 687b ldr r3, [r7, #4] 8009900: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009904: 685b ldr r3, [r3, #4] 8009906: 2b00 cmp r3, #0 8009908: d00e beq.n 8009928 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) 800990a: 687b ldr r3, [r7, #4] 800990c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009910: 685b ldr r3, [r3, #4] 8009912: 687a ldr r2, [r7, #4] 8009914: 6852 ldr r2, [r2, #4] 8009916: b2d2 uxtb r2, r2 8009918: 4611 mov r1, r2 800991a: 6878 ldr r0, [r7, #4] 800991c: 4798 blx r3 800991e: 4603 mov r3, r0 8009920: 2b00 cmp r3, #0 8009922: d001 beq.n 8009928 { ret = USBD_FAIL; 8009924: 2303 movs r3, #3 8009926: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8009928: 2340 movs r3, #64 @ 0x40 800992a: 2200 movs r2, #0 800992c: 2100 movs r1, #0 800992e: 6878 ldr r0, [r7, #4] 8009930: f001 fb7b bl 800b02a pdev->ep_out[0x00U & 0xFU].is_used = 1U; 8009934: 687b ldr r3, [r7, #4] 8009936: 2201 movs r2, #1 8009938: f883 2163 strb.w r2, [r3, #355] @ 0x163 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 800993c: 687b ldr r3, [r7, #4] 800993e: 2240 movs r2, #64 @ 0x40 8009940: f8a3 2160 strh.w r2, [r3, #352] @ 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8009944: 2340 movs r3, #64 @ 0x40 8009946: 2200 movs r2, #0 8009948: 2180 movs r1, #128 @ 0x80 800994a: 6878 ldr r0, [r7, #4] 800994c: f001 fb6d bl 800b02a pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8009950: 687b ldr r3, [r7, #4] 8009952: 2201 movs r2, #1 8009954: f883 2023 strb.w r2, [r3, #35] @ 0x23 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8009958: 687b ldr r3, [r7, #4] 800995a: 2240 movs r2, #64 @ 0x40 800995c: 841a strh r2, [r3, #32] return ret; 800995e: 7bfb ldrb r3, [r7, #15] } 8009960: 4618 mov r0, r3 8009962: 3710 adds r7, #16 8009964: 46bd mov sp, r7 8009966: bd80 pop {r7, pc} 08009968 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8009968: b480 push {r7} 800996a: b083 sub sp, #12 800996c: af00 add r7, sp, #0 800996e: 6078 str r0, [r7, #4] 8009970: 460b mov r3, r1 8009972: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 8009974: 687b ldr r3, [r7, #4] 8009976: 78fa ldrb r2, [r7, #3] 8009978: 741a strb r2, [r3, #16] return USBD_OK; 800997a: 2300 movs r3, #0 } 800997c: 4618 mov r0, r3 800997e: 370c adds r7, #12 8009980: 46bd mov sp, r7 8009982: f85d 7b04 ldr.w r7, [sp], #4 8009986: 4770 bx lr 08009988 : * Handle Suspend event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 8009988: b480 push {r7} 800998a: b083 sub sp, #12 800998c: af00 add r7, sp, #0 800998e: 6078 str r0, [r7, #4] if (pdev->dev_state != USBD_STATE_SUSPENDED) 8009990: 687b ldr r3, [r7, #4] 8009992: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009996: b2db uxtb r3, r3 8009998: 2b04 cmp r3, #4 800999a: d006 beq.n 80099aa { pdev->dev_old_state = pdev->dev_state; 800999c: 687b ldr r3, [r7, #4] 800999e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80099a2: b2da uxtb r2, r3 80099a4: 687b ldr r3, [r7, #4] 80099a6: f883 229d strb.w r2, [r3, #669] @ 0x29d } pdev->dev_state = USBD_STATE_SUSPENDED; 80099aa: 687b ldr r3, [r7, #4] 80099ac: 2204 movs r2, #4 80099ae: f883 229c strb.w r2, [r3, #668] @ 0x29c return USBD_OK; 80099b2: 2300 movs r3, #0 } 80099b4: 4618 mov r0, r3 80099b6: 370c adds r7, #12 80099b8: 46bd mov sp, r7 80099ba: f85d 7b04 ldr.w r7, [sp], #4 80099be: 4770 bx lr 080099c0 : * Handle Resume event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 80099c0: b480 push {r7} 80099c2: b083 sub sp, #12 80099c4: af00 add r7, sp, #0 80099c6: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 80099c8: 687b ldr r3, [r7, #4] 80099ca: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80099ce: b2db uxtb r3, r3 80099d0: 2b04 cmp r3, #4 80099d2: d106 bne.n 80099e2 { pdev->dev_state = pdev->dev_old_state; 80099d4: 687b ldr r3, [r7, #4] 80099d6: f893 329d ldrb.w r3, [r3, #669] @ 0x29d 80099da: b2da uxtb r2, r3 80099dc: 687b ldr r3, [r7, #4] 80099de: f883 229c strb.w r2, [r3, #668] @ 0x29c } return USBD_OK; 80099e2: 2300 movs r3, #0 } 80099e4: 4618 mov r0, r3 80099e6: 370c adds r7, #12 80099e8: 46bd mov sp, r7 80099ea: f85d 7b04 ldr.w r7, [sp], #4 80099ee: 4770 bx lr 080099f0 : * Handle SOF event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 80099f0: b580 push {r7, lr} 80099f2: b082 sub sp, #8 80099f4: af00 add r7, sp, #0 80099f6: 6078 str r0, [r7, #4] /* The SOF event can be distributed for all classes that support it */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 80099f8: 687b ldr r3, [r7, #4] 80099fa: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80099fe: b2db uxtb r3, r3 8009a00: 2b03 cmp r3, #3 8009a02: d110 bne.n 8009a26 } } } } #else if (pdev->pClass[0] != NULL) 8009a04: 687b ldr r3, [r7, #4] 8009a06: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009a0a: 2b00 cmp r3, #0 8009a0c: d00b beq.n 8009a26 { if (pdev->pClass[0]->SOF != NULL) 8009a0e: 687b ldr r3, [r7, #4] 8009a10: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009a14: 69db ldr r3, [r3, #28] 8009a16: 2b00 cmp r3, #0 8009a18: d005 beq.n 8009a26 { (void)pdev->pClass[0]->SOF(pdev); 8009a1a: 687b ldr r3, [r7, #4] 8009a1c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009a20: 69db ldr r3, [r3, #28] 8009a22: 6878 ldr r0, [r7, #4] 8009a24: 4798 blx r3 } } #endif /* USE_USBD_COMPOSITE */ } return USBD_OK; 8009a26: 2300 movs r3, #0 } 8009a28: 4618 mov r0, r3 8009a2a: 3708 adds r7, #8 8009a2c: 46bd mov sp, r7 8009a2e: bd80 pop {r7, pc} 08009a30 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009a30: b580 push {r7, lr} 8009a32: b082 sub sp, #8 8009a34: af00 add r7, sp, #0 8009a36: 6078 str r0, [r7, #4] 8009a38: 460b mov r3, r1 8009a3a: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009a3c: 687b ldr r3, [r7, #4] 8009a3e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009a42: 687b ldr r3, [r7, #4] 8009a44: 32ae adds r2, #174 @ 0xae 8009a46: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009a4a: 2b00 cmp r3, #0 8009a4c: d101 bne.n 8009a52 { return USBD_FAIL; 8009a4e: 2303 movs r3, #3 8009a50: e01c b.n 8009a8c } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009a52: 687b ldr r3, [r7, #4] 8009a54: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009a58: b2db uxtb r3, r3 8009a5a: 2b03 cmp r3, #3 8009a5c: d115 bne.n 8009a8a { if (pdev->pClass[pdev->classId]->IsoINIncomplete != NULL) 8009a5e: 687b ldr r3, [r7, #4] 8009a60: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009a64: 687b ldr r3, [r7, #4] 8009a66: 32ae adds r2, #174 @ 0xae 8009a68: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009a6c: 6a1b ldr r3, [r3, #32] 8009a6e: 2b00 cmp r3, #0 8009a70: d00b beq.n 8009a8a { (void)pdev->pClass[pdev->classId]->IsoINIncomplete(pdev, epnum); 8009a72: 687b ldr r3, [r7, #4] 8009a74: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009a78: 687b ldr r3, [r7, #4] 8009a7a: 32ae adds r2, #174 @ 0xae 8009a7c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009a80: 6a1b ldr r3, [r3, #32] 8009a82: 78fa ldrb r2, [r7, #3] 8009a84: 4611 mov r1, r2 8009a86: 6878 ldr r0, [r7, #4] 8009a88: 4798 blx r3 } } return USBD_OK; 8009a8a: 2300 movs r3, #0 } 8009a8c: 4618 mov r0, r3 8009a8e: 3708 adds r7, #8 8009a90: 46bd mov sp, r7 8009a92: bd80 pop {r7, pc} 08009a94 : * @param epnum: Endpoint number * @retval status */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8009a94: b580 push {r7, lr} 8009a96: b082 sub sp, #8 8009a98: af00 add r7, sp, #0 8009a9a: 6078 str r0, [r7, #4] 8009a9c: 460b mov r3, r1 8009a9e: 70fb strb r3, [r7, #3] if (pdev->pClass[pdev->classId] == NULL) 8009aa0: 687b ldr r3, [r7, #4] 8009aa2: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009aa6: 687b ldr r3, [r7, #4] 8009aa8: 32ae adds r2, #174 @ 0xae 8009aaa: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009aae: 2b00 cmp r3, #0 8009ab0: d101 bne.n 8009ab6 { return USBD_FAIL; 8009ab2: 2303 movs r3, #3 8009ab4: e01c b.n 8009af0 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8009ab6: 687b ldr r3, [r7, #4] 8009ab8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009abc: b2db uxtb r3, r3 8009abe: 2b03 cmp r3, #3 8009ac0: d115 bne.n 8009aee { if (pdev->pClass[pdev->classId]->IsoOUTIncomplete != NULL) 8009ac2: 687b ldr r3, [r7, #4] 8009ac4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009ac8: 687b ldr r3, [r7, #4] 8009aca: 32ae adds r2, #174 @ 0xae 8009acc: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009ad0: 6a5b ldr r3, [r3, #36] @ 0x24 8009ad2: 2b00 cmp r3, #0 8009ad4: d00b beq.n 8009aee { (void)pdev->pClass[pdev->classId]->IsoOUTIncomplete(pdev, epnum); 8009ad6: 687b ldr r3, [r7, #4] 8009ad8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009adc: 687b ldr r3, [r7, #4] 8009ade: 32ae adds r2, #174 @ 0xae 8009ae0: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009ae4: 6a5b ldr r3, [r3, #36] @ 0x24 8009ae6: 78fa ldrb r2, [r7, #3] 8009ae8: 4611 mov r1, r2 8009aea: 6878 ldr r0, [r7, #4] 8009aec: 4798 blx r3 } } return USBD_OK; 8009aee: 2300 movs r3, #0 } 8009af0: 4618 mov r0, r3 8009af2: 3708 adds r7, #8 8009af4: 46bd mov sp, r7 8009af6: bd80 pop {r7, pc} 08009af8 : * Handle device connection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { 8009af8: b480 push {r7} 8009afa: b083 sub sp, #12 8009afc: af00 add r7, sp, #0 8009afe: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8009b00: 2300 movs r3, #0 } 8009b02: 4618 mov r0, r3 8009b04: 370c adds r7, #12 8009b06: 46bd mov sp, r7 8009b08: f85d 7b04 ldr.w r7, [sp], #4 8009b0c: 4770 bx lr 08009b0e : * Handle device disconnection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { 8009b0e: b580 push {r7, lr} 8009b10: b084 sub sp, #16 8009b12: af00 add r7, sp, #0 8009b14: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 8009b16: 2300 movs r3, #0 8009b18: 73fb strb r3, [r7, #15] /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; 8009b1a: 687b ldr r3, [r7, #4] 8009b1c: 2201 movs r2, #1 8009b1e: f883 229c strb.w r2, [r3, #668] @ 0x29c } } } } #else if (pdev->pClass[0] != NULL) 8009b22: 687b ldr r3, [r7, #4] 8009b24: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009b28: 2b00 cmp r3, #0 8009b2a: d00e beq.n 8009b4a { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != 0U) 8009b2c: 687b ldr r3, [r7, #4] 8009b2e: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8009b32: 685b ldr r3, [r3, #4] 8009b34: 687a ldr r2, [r7, #4] 8009b36: 6852 ldr r2, [r2, #4] 8009b38: b2d2 uxtb r2, r2 8009b3a: 4611 mov r1, r2 8009b3c: 6878 ldr r0, [r7, #4] 8009b3e: 4798 blx r3 8009b40: 4603 mov r3, r0 8009b42: 2b00 cmp r3, #0 8009b44: d001 beq.n 8009b4a { ret = USBD_FAIL; 8009b46: 2303 movs r3, #3 8009b48: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ return ret; 8009b4a: 7bfb ldrb r3, [r7, #15] } 8009b4c: 4618 mov r0, r3 8009b4e: 3710 adds r7, #16 8009b50: 46bd mov sp, r7 8009b52: bd80 pop {r7, pc} 08009b54 : * @param pdev: device instance * @param index : selected interface number * @retval index of the class using the selected interface number. OxFF if no class found. */ uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) { 8009b54: b480 push {r7} 8009b56: b083 sub sp, #12 8009b58: af00 add r7, sp, #0 8009b5a: 6078 str r0, [r7, #4] 8009b5c: 460b mov r3, r1 8009b5e: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009b60: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8009b62: 4618 mov r0, r3 8009b64: 370c adds r7, #12 8009b66: 46bd mov sp, r7 8009b68: f85d 7b04 ldr.w r7, [sp], #4 8009b6c: 4770 bx lr 08009b6e : * @param pdev: device instance * @param index : selected endpoint number * @retval index of the class using the selected endpoint number. 0xFF if no class found. */ uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) { 8009b6e: b480 push {r7} 8009b70: b083 sub sp, #12 8009b72: af00 add r7, sp, #0 8009b74: 6078 str r0, [r7, #4] 8009b76: 460b mov r3, r1 8009b78: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8009b7a: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8009b7c: 4618 mov r0, r3 8009b7e: 370c adds r7, #12 8009b80: 46bd mov sp, r7 8009b82: f85d 7b04 ldr.w r7, [sp], #4 8009b86: 4770 bx lr 08009b88 : * @param pConfDesc: pointer to Bos descriptor * @param EpAddr: endpoint address * @retval pointer to video endpoint descriptor */ void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) { 8009b88: b580 push {r7, lr} 8009b8a: b086 sub sp, #24 8009b8c: af00 add r7, sp, #0 8009b8e: 6078 str r0, [r7, #4] 8009b90: 460b mov r3, r1 8009b92: 70fb strb r3, [r7, #3] USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; 8009b94: 687b ldr r3, [r7, #4] 8009b96: 617b str r3, [r7, #20] USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; 8009b98: 687b ldr r3, [r7, #4] 8009b9a: 60fb str r3, [r7, #12] USBD_EpDescTypeDef *pEpDesc = NULL; 8009b9c: 2300 movs r3, #0 8009b9e: 613b str r3, [r7, #16] uint16_t ptr; if (desc->wTotalLength > desc->bLength) 8009ba0: 68fb ldr r3, [r7, #12] 8009ba2: 885b ldrh r3, [r3, #2] 8009ba4: b29b uxth r3, r3 8009ba6: 68fa ldr r2, [r7, #12] 8009ba8: 7812 ldrb r2, [r2, #0] 8009baa: 4293 cmp r3, r2 8009bac: d91f bls.n 8009bee { ptr = desc->bLength; 8009bae: 68fb ldr r3, [r7, #12] 8009bb0: 781b ldrb r3, [r3, #0] 8009bb2: 817b strh r3, [r7, #10] while (ptr < desc->wTotalLength) 8009bb4: e013 b.n 8009bde { pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); 8009bb6: f107 030a add.w r3, r7, #10 8009bba: 4619 mov r1, r3 8009bbc: 6978 ldr r0, [r7, #20] 8009bbe: f000 f81b bl 8009bf8 8009bc2: 6178 str r0, [r7, #20] if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) 8009bc4: 697b ldr r3, [r7, #20] 8009bc6: 785b ldrb r3, [r3, #1] 8009bc8: 2b05 cmp r3, #5 8009bca: d108 bne.n 8009bde { pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; 8009bcc: 697b ldr r3, [r7, #20] 8009bce: 613b str r3, [r7, #16] if (pEpDesc->bEndpointAddress == EpAddr) 8009bd0: 693b ldr r3, [r7, #16] 8009bd2: 789b ldrb r3, [r3, #2] 8009bd4: 78fa ldrb r2, [r7, #3] 8009bd6: 429a cmp r2, r3 8009bd8: d008 beq.n 8009bec { break; } else { pEpDesc = NULL; 8009bda: 2300 movs r3, #0 8009bdc: 613b str r3, [r7, #16] while (ptr < desc->wTotalLength) 8009bde: 68fb ldr r3, [r7, #12] 8009be0: 885b ldrh r3, [r3, #2] 8009be2: b29a uxth r2, r3 8009be4: 897b ldrh r3, [r7, #10] 8009be6: 429a cmp r2, r3 8009be8: d8e5 bhi.n 8009bb6 8009bea: e000 b.n 8009bee break; 8009bec: bf00 nop } } } } return (void *)pEpDesc; 8009bee: 693b ldr r3, [r7, #16] } 8009bf0: 4618 mov r0, r3 8009bf2: 3718 adds r7, #24 8009bf4: 46bd mov sp, r7 8009bf6: bd80 pop {r7, pc} 08009bf8 : * @param buf: Buffer where the descriptor is available * @param ptr: data pointer inside the descriptor * @retval next header */ USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) { 8009bf8: b480 push {r7} 8009bfa: b085 sub sp, #20 8009bfc: af00 add r7, sp, #0 8009bfe: 6078 str r0, [r7, #4] 8009c00: 6039 str r1, [r7, #0] USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; 8009c02: 687b ldr r3, [r7, #4] 8009c04: 60fb str r3, [r7, #12] *ptr += pnext->bLength; 8009c06: 683b ldr r3, [r7, #0] 8009c08: 881b ldrh r3, [r3, #0] 8009c0a: 68fa ldr r2, [r7, #12] 8009c0c: 7812 ldrb r2, [r2, #0] 8009c0e: 4413 add r3, r2 8009c10: b29a uxth r2, r3 8009c12: 683b ldr r3, [r7, #0] 8009c14: 801a strh r2, [r3, #0] pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); 8009c16: 68fb ldr r3, [r7, #12] 8009c18: 781b ldrb r3, [r3, #0] 8009c1a: 461a mov r2, r3 8009c1c: 687b ldr r3, [r7, #4] 8009c1e: 4413 add r3, r2 8009c20: 60fb str r3, [r7, #12] return (pnext); 8009c22: 68fb ldr r3, [r7, #12] } 8009c24: 4618 mov r0, r3 8009c26: 3714 adds r7, #20 8009c28: 46bd mov sp, r7 8009c2a: f85d 7b04 ldr.w r7, [sp], #4 8009c2e: 4770 bx lr 08009c30 : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 8009c30: b480 push {r7} 8009c32: b087 sub sp, #28 8009c34: af00 add r7, sp, #0 8009c36: 6078 str r0, [r7, #4] uint16_t _SwapVal; uint16_t _Byte1; uint16_t _Byte2; uint8_t *_pbuff = addr; 8009c38: 687b ldr r3, [r7, #4] 8009c3a: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 8009c3c: 697b ldr r3, [r7, #20] 8009c3e: 781b ldrb r3, [r3, #0] 8009c40: 827b strh r3, [r7, #18] _pbuff++; 8009c42: 697b ldr r3, [r7, #20] 8009c44: 3301 adds r3, #1 8009c46: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 8009c48: 697b ldr r3, [r7, #20] 8009c4a: 781b ldrb r3, [r3, #0] 8009c4c: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 8009c4e: f9b7 3010 ldrsh.w r3, [r7, #16] 8009c52: 021b lsls r3, r3, #8 8009c54: b21a sxth r2, r3 8009c56: f9b7 3012 ldrsh.w r3, [r7, #18] 8009c5a: 4313 orrs r3, r2 8009c5c: b21b sxth r3, r3 8009c5e: 81fb strh r3, [r7, #14] return _SwapVal; 8009c60: 89fb ldrh r3, [r7, #14] } 8009c62: 4618 mov r0, r3 8009c64: 371c adds r7, #28 8009c66: 46bd mov sp, r7 8009c68: f85d 7b04 ldr.w r7, [sp], #4 8009c6c: 4770 bx lr ... 08009c70 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009c70: b580 push {r7, lr} 8009c72: b084 sub sp, #16 8009c74: af00 add r7, sp, #0 8009c76: 6078 str r0, [r7, #4] 8009c78: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8009c7a: 2300 movs r3, #0 8009c7c: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009c7e: 683b ldr r3, [r7, #0] 8009c80: 781b ldrb r3, [r3, #0] 8009c82: f003 0360 and.w r3, r3, #96 @ 0x60 8009c86: 2b40 cmp r3, #64 @ 0x40 8009c88: d005 beq.n 8009c96 8009c8a: 2b40 cmp r3, #64 @ 0x40 8009c8c: d857 bhi.n 8009d3e 8009c8e: 2b00 cmp r3, #0 8009c90: d00f beq.n 8009cb2 8009c92: 2b20 cmp r3, #32 8009c94: d153 bne.n 8009d3e { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); 8009c96: 687b ldr r3, [r7, #4] 8009c98: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8009c9c: 687b ldr r3, [r7, #4] 8009c9e: 32ae adds r2, #174 @ 0xae 8009ca0: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009ca4: 689b ldr r3, [r3, #8] 8009ca6: 6839 ldr r1, [r7, #0] 8009ca8: 6878 ldr r0, [r7, #4] 8009caa: 4798 blx r3 8009cac: 4603 mov r3, r0 8009cae: 73fb strb r3, [r7, #15] break; 8009cb0: e04a b.n 8009d48 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8009cb2: 683b ldr r3, [r7, #0] 8009cb4: 785b ldrb r3, [r3, #1] 8009cb6: 2b09 cmp r3, #9 8009cb8: d83b bhi.n 8009d32 8009cba: a201 add r2, pc, #4 @ (adr r2, 8009cc0 ) 8009cbc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009cc0: 08009d15 .word 0x08009d15 8009cc4: 08009d29 .word 0x08009d29 8009cc8: 08009d33 .word 0x08009d33 8009ccc: 08009d1f .word 0x08009d1f 8009cd0: 08009d33 .word 0x08009d33 8009cd4: 08009cf3 .word 0x08009cf3 8009cd8: 08009ce9 .word 0x08009ce9 8009cdc: 08009d33 .word 0x08009d33 8009ce0: 08009d0b .word 0x08009d0b 8009ce4: 08009cfd .word 0x08009cfd { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 8009ce8: 6839 ldr r1, [r7, #0] 8009cea: 6878 ldr r0, [r7, #4] 8009cec: f000 fa3e bl 800a16c break; 8009cf0: e024 b.n 8009d3c case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 8009cf2: 6839 ldr r1, [r7, #0] 8009cf4: 6878 ldr r0, [r7, #4] 8009cf6: f000 fbcd bl 800a494 break; 8009cfa: e01f b.n 8009d3c case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 8009cfc: 6839 ldr r1, [r7, #0] 8009cfe: 6878 ldr r0, [r7, #4] 8009d00: f000 fc0c bl 800a51c 8009d04: 4603 mov r3, r0 8009d06: 73fb strb r3, [r7, #15] break; 8009d08: e018 b.n 8009d3c case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 8009d0a: 6839 ldr r1, [r7, #0] 8009d0c: 6878 ldr r0, [r7, #4] 8009d0e: f000 fcaf bl 800a670 break; 8009d12: e013 b.n 8009d3c case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 8009d14: 6839 ldr r1, [r7, #0] 8009d16: 6878 ldr r0, [r7, #4] 8009d18: f000 fce0 bl 800a6dc break; 8009d1c: e00e b.n 8009d3c case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 8009d1e: 6839 ldr r1, [r7, #0] 8009d20: 6878 ldr r0, [r7, #4] 8009d22: f000 fd0f bl 800a744 break; 8009d26: e009 b.n 8009d3c case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 8009d28: 6839 ldr r1, [r7, #0] 8009d2a: 6878 ldr r0, [r7, #4] 8009d2c: f000 fd33 bl 800a796 break; 8009d30: e004 b.n 8009d3c default: USBD_CtlError(pdev, req); 8009d32: 6839 ldr r1, [r7, #0] 8009d34: 6878 ldr r0, [r7, #4] 8009d36: f000 fd8a bl 800a84e break; 8009d3a: bf00 nop } break; 8009d3c: e004 b.n 8009d48 default: USBD_CtlError(pdev, req); 8009d3e: 6839 ldr r1, [r7, #0] 8009d40: 6878 ldr r0, [r7, #4] 8009d42: f000 fd84 bl 800a84e break; 8009d46: bf00 nop } return ret; 8009d48: 7bfb ldrb r3, [r7, #15] } 8009d4a: 4618 mov r0, r3 8009d4c: 3710 adds r7, #16 8009d4e: 46bd mov sp, r7 8009d50: bd80 pop {r7, pc} 8009d52: bf00 nop 08009d54 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009d54: b580 push {r7, lr} 8009d56: b084 sub sp, #16 8009d58: af00 add r7, sp, #0 8009d5a: 6078 str r0, [r7, #4] 8009d5c: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8009d5e: 2300 movs r3, #0 8009d60: 73fb strb r3, [r7, #15] uint8_t idx; switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009d62: 683b ldr r3, [r7, #0] 8009d64: 781b ldrb r3, [r3, #0] 8009d66: f003 0360 and.w r3, r3, #96 @ 0x60 8009d6a: 2b40 cmp r3, #64 @ 0x40 8009d6c: d005 beq.n 8009d7a 8009d6e: 2b40 cmp r3, #64 @ 0x40 8009d70: d852 bhi.n 8009e18 8009d72: 2b00 cmp r3, #0 8009d74: d001 beq.n 8009d7a 8009d76: 2b20 cmp r3, #32 8009d78: d14e bne.n 8009e18 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 8009d7a: 687b ldr r3, [r7, #4] 8009d7c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009d80: b2db uxtb r3, r3 8009d82: 3b01 subs r3, #1 8009d84: 2b02 cmp r3, #2 8009d86: d840 bhi.n 8009e0a { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 8009d88: 683b ldr r3, [r7, #0] 8009d8a: 889b ldrh r3, [r3, #4] 8009d8c: b2db uxtb r3, r3 8009d8e: 2b01 cmp r3, #1 8009d90: d836 bhi.n 8009e00 { /* Get the class index relative to this interface */ idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); 8009d92: 683b ldr r3, [r7, #0] 8009d94: 889b ldrh r3, [r3, #4] 8009d96: b2db uxtb r3, r3 8009d98: 4619 mov r1, r3 8009d9a: 6878 ldr r0, [r7, #4] 8009d9c: f7ff feda bl 8009b54 8009da0: 4603 mov r3, r0 8009da2: 73bb strb r3, [r7, #14] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009da4: 7bbb ldrb r3, [r7, #14] 8009da6: 2bff cmp r3, #255 @ 0xff 8009da8: d01d beq.n 8009de6 8009daa: 7bbb ldrb r3, [r7, #14] 8009dac: 2b00 cmp r3, #0 8009dae: d11a bne.n 8009de6 { /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8009db0: 7bba ldrb r2, [r7, #14] 8009db2: 687b ldr r3, [r7, #4] 8009db4: 32ae adds r2, #174 @ 0xae 8009db6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009dba: 689b ldr r3, [r3, #8] 8009dbc: 2b00 cmp r3, #0 8009dbe: d00f beq.n 8009de0 { pdev->classId = idx; 8009dc0: 7bba ldrb r2, [r7, #14] 8009dc2: 687b ldr r3, [r7, #4] 8009dc4: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 8009dc8: 7bba ldrb r2, [r7, #14] 8009dca: 687b ldr r3, [r7, #4] 8009dcc: 32ae adds r2, #174 @ 0xae 8009dce: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009dd2: 689b ldr r3, [r3, #8] 8009dd4: 6839 ldr r1, [r7, #0] 8009dd6: 6878 ldr r0, [r7, #4] 8009dd8: 4798 blx r3 8009dda: 4603 mov r3, r0 8009ddc: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 8009dde: e004 b.n 8009dea } else { /* should never reach this condition */ ret = USBD_FAIL; 8009de0: 2303 movs r3, #3 8009de2: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 8009de4: e001 b.n 8009dea } } else { /* No relative interface found */ ret = USBD_FAIL; 8009de6: 2303 movs r3, #3 8009de8: 73fb strb r3, [r7, #15] } if ((req->wLength == 0U) && (ret == USBD_OK)) 8009dea: 683b ldr r3, [r7, #0] 8009dec: 88db ldrh r3, [r3, #6] 8009dee: 2b00 cmp r3, #0 8009df0: d110 bne.n 8009e14 8009df2: 7bfb ldrb r3, [r7, #15] 8009df4: 2b00 cmp r3, #0 8009df6: d10d bne.n 8009e14 { (void)USBD_CtlSendStatus(pdev); 8009df8: 6878 ldr r0, [r7, #4] 8009dfa: f000 fde5 bl 800a9c8 } else { USBD_CtlError(pdev, req); } break; 8009dfe: e009 b.n 8009e14 USBD_CtlError(pdev, req); 8009e00: 6839 ldr r1, [r7, #0] 8009e02: 6878 ldr r0, [r7, #4] 8009e04: f000 fd23 bl 800a84e break; 8009e08: e004 b.n 8009e14 default: USBD_CtlError(pdev, req); 8009e0a: 6839 ldr r1, [r7, #0] 8009e0c: 6878 ldr r0, [r7, #4] 8009e0e: f000 fd1e bl 800a84e break; 8009e12: e000 b.n 8009e16 break; 8009e14: bf00 nop } break; 8009e16: e004 b.n 8009e22 default: USBD_CtlError(pdev, req); 8009e18: 6839 ldr r1, [r7, #0] 8009e1a: 6878 ldr r0, [r7, #4] 8009e1c: f000 fd17 bl 800a84e break; 8009e20: bf00 nop } return ret; 8009e22: 7bfb ldrb r3, [r7, #15] } 8009e24: 4618 mov r0, r3 8009e26: 3710 adds r7, #16 8009e28: 46bd mov sp, r7 8009e2a: bd80 pop {r7, pc} 08009e2c : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8009e2c: b580 push {r7, lr} 8009e2e: b084 sub sp, #16 8009e30: af00 add r7, sp, #0 8009e32: 6078 str r0, [r7, #4] 8009e34: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; uint8_t idx; USBD_StatusTypeDef ret = USBD_OK; 8009e36: 2300 movs r3, #0 8009e38: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 8009e3a: 683b ldr r3, [r7, #0] 8009e3c: 889b ldrh r3, [r3, #4] 8009e3e: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8009e40: 683b ldr r3, [r7, #0] 8009e42: 781b ldrb r3, [r3, #0] 8009e44: f003 0360 and.w r3, r3, #96 @ 0x60 8009e48: 2b40 cmp r3, #64 @ 0x40 8009e4a: d007 beq.n 8009e5c 8009e4c: 2b40 cmp r3, #64 @ 0x40 8009e4e: f200 8181 bhi.w 800a154 8009e52: 2b00 cmp r3, #0 8009e54: d02a beq.n 8009eac 8009e56: 2b20 cmp r3, #32 8009e58: f040 817c bne.w 800a154 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: /* Get the class index relative to this endpoint */ idx = USBD_CoreFindEP(pdev, ep_addr); 8009e5c: 7bbb ldrb r3, [r7, #14] 8009e5e: 4619 mov r1, r3 8009e60: 6878 ldr r0, [r7, #4] 8009e62: f7ff fe84 bl 8009b6e 8009e66: 4603 mov r3, r0 8009e68: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009e6a: 7b7b ldrb r3, [r7, #13] 8009e6c: 2bff cmp r3, #255 @ 0xff 8009e6e: f000 8176 beq.w 800a15e 8009e72: 7b7b ldrb r3, [r7, #13] 8009e74: 2b00 cmp r3, #0 8009e76: f040 8172 bne.w 800a15e { pdev->classId = idx; 8009e7a: 7b7a ldrb r2, [r7, #13] 8009e7c: 687b ldr r3, [r7, #4] 8009e7e: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8009e82: 7b7a ldrb r2, [r7, #13] 8009e84: 687b ldr r3, [r7, #4] 8009e86: 32ae adds r2, #174 @ 0xae 8009e88: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009e8c: 689b ldr r3, [r3, #8] 8009e8e: 2b00 cmp r3, #0 8009e90: f000 8165 beq.w 800a15e { ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); 8009e94: 7b7a ldrb r2, [r7, #13] 8009e96: 687b ldr r3, [r7, #4] 8009e98: 32ae adds r2, #174 @ 0xae 8009e9a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009e9e: 689b ldr r3, [r3, #8] 8009ea0: 6839 ldr r1, [r7, #0] 8009ea2: 6878 ldr r0, [r7, #4] 8009ea4: 4798 blx r3 8009ea6: 4603 mov r3, r0 8009ea8: 73fb strb r3, [r7, #15] } } break; 8009eaa: e158 b.n 800a15e case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8009eac: 683b ldr r3, [r7, #0] 8009eae: 785b ldrb r3, [r3, #1] 8009eb0: 2b03 cmp r3, #3 8009eb2: d008 beq.n 8009ec6 8009eb4: 2b03 cmp r3, #3 8009eb6: f300 8147 bgt.w 800a148 8009eba: 2b00 cmp r3, #0 8009ebc: f000 809b beq.w 8009ff6 8009ec0: 2b01 cmp r3, #1 8009ec2: d03c beq.n 8009f3e 8009ec4: e140 b.n 800a148 { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 8009ec6: 687b ldr r3, [r7, #4] 8009ec8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009ecc: b2db uxtb r3, r3 8009ece: 2b02 cmp r3, #2 8009ed0: d002 beq.n 8009ed8 8009ed2: 2b03 cmp r3, #3 8009ed4: d016 beq.n 8009f04 8009ed6: e02c b.n 8009f32 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8009ed8: 7bbb ldrb r3, [r7, #14] 8009eda: 2b00 cmp r3, #0 8009edc: d00d beq.n 8009efa 8009ede: 7bbb ldrb r3, [r7, #14] 8009ee0: 2b80 cmp r3, #128 @ 0x80 8009ee2: d00a beq.n 8009efa { (void)USBD_LL_StallEP(pdev, ep_addr); 8009ee4: 7bbb ldrb r3, [r7, #14] 8009ee6: 4619 mov r1, r3 8009ee8: 6878 ldr r0, [r7, #4] 8009eea: f001 f8e3 bl 800b0b4 (void)USBD_LL_StallEP(pdev, 0x80U); 8009eee: 2180 movs r1, #128 @ 0x80 8009ef0: 6878 ldr r0, [r7, #4] 8009ef2: f001 f8df bl 800b0b4 8009ef6: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8009ef8: e020 b.n 8009f3c USBD_CtlError(pdev, req); 8009efa: 6839 ldr r1, [r7, #0] 8009efc: 6878 ldr r0, [r7, #4] 8009efe: f000 fca6 bl 800a84e break; 8009f02: e01b b.n 8009f3c case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8009f04: 683b ldr r3, [r7, #0] 8009f06: 885b ldrh r3, [r3, #2] 8009f08: 2b00 cmp r3, #0 8009f0a: d10e bne.n 8009f2a { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 8009f0c: 7bbb ldrb r3, [r7, #14] 8009f0e: 2b00 cmp r3, #0 8009f10: d00b beq.n 8009f2a 8009f12: 7bbb ldrb r3, [r7, #14] 8009f14: 2b80 cmp r3, #128 @ 0x80 8009f16: d008 beq.n 8009f2a 8009f18: 683b ldr r3, [r7, #0] 8009f1a: 88db ldrh r3, [r3, #6] 8009f1c: 2b00 cmp r3, #0 8009f1e: d104 bne.n 8009f2a { (void)USBD_LL_StallEP(pdev, ep_addr); 8009f20: 7bbb ldrb r3, [r7, #14] 8009f22: 4619 mov r1, r3 8009f24: 6878 ldr r0, [r7, #4] 8009f26: f001 f8c5 bl 800b0b4 } } (void)USBD_CtlSendStatus(pdev); 8009f2a: 6878 ldr r0, [r7, #4] 8009f2c: f000 fd4c bl 800a9c8 break; 8009f30: e004 b.n 8009f3c default: USBD_CtlError(pdev, req); 8009f32: 6839 ldr r1, [r7, #0] 8009f34: 6878 ldr r0, [r7, #4] 8009f36: f000 fc8a bl 800a84e break; 8009f3a: bf00 nop } break; 8009f3c: e109 b.n 800a152 case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 8009f3e: 687b ldr r3, [r7, #4] 8009f40: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009f44: b2db uxtb r3, r3 8009f46: 2b02 cmp r3, #2 8009f48: d002 beq.n 8009f50 8009f4a: 2b03 cmp r3, #3 8009f4c: d016 beq.n 8009f7c 8009f4e: e04b b.n 8009fe8 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8009f50: 7bbb ldrb r3, [r7, #14] 8009f52: 2b00 cmp r3, #0 8009f54: d00d beq.n 8009f72 8009f56: 7bbb ldrb r3, [r7, #14] 8009f58: 2b80 cmp r3, #128 @ 0x80 8009f5a: d00a beq.n 8009f72 { (void)USBD_LL_StallEP(pdev, ep_addr); 8009f5c: 7bbb ldrb r3, [r7, #14] 8009f5e: 4619 mov r1, r3 8009f60: 6878 ldr r0, [r7, #4] 8009f62: f001 f8a7 bl 800b0b4 (void)USBD_LL_StallEP(pdev, 0x80U); 8009f66: 2180 movs r1, #128 @ 0x80 8009f68: 6878 ldr r0, [r7, #4] 8009f6a: f001 f8a3 bl 800b0b4 8009f6e: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8009f70: e040 b.n 8009ff4 USBD_CtlError(pdev, req); 8009f72: 6839 ldr r1, [r7, #0] 8009f74: 6878 ldr r0, [r7, #4] 8009f76: f000 fc6a bl 800a84e break; 8009f7a: e03b b.n 8009ff4 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8009f7c: 683b ldr r3, [r7, #0] 8009f7e: 885b ldrh r3, [r3, #2] 8009f80: 2b00 cmp r3, #0 8009f82: d136 bne.n 8009ff2 { if ((ep_addr & 0x7FU) != 0x00U) 8009f84: 7bbb ldrb r3, [r7, #14] 8009f86: f003 037f and.w r3, r3, #127 @ 0x7f 8009f8a: 2b00 cmp r3, #0 8009f8c: d004 beq.n 8009f98 { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 8009f8e: 7bbb ldrb r3, [r7, #14] 8009f90: 4619 mov r1, r3 8009f92: 6878 ldr r0, [r7, #4] 8009f94: f001 f8ad bl 800b0f2 } (void)USBD_CtlSendStatus(pdev); 8009f98: 6878 ldr r0, [r7, #4] 8009f9a: f000 fd15 bl 800a9c8 /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ep_addr); 8009f9e: 7bbb ldrb r3, [r7, #14] 8009fa0: 4619 mov r1, r3 8009fa2: 6878 ldr r0, [r7, #4] 8009fa4: f7ff fde3 bl 8009b6e 8009fa8: 4603 mov r3, r0 8009faa: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8009fac: 7b7b ldrb r3, [r7, #13] 8009fae: 2bff cmp r3, #255 @ 0xff 8009fb0: d01f beq.n 8009ff2 8009fb2: 7b7b ldrb r3, [r7, #13] 8009fb4: 2b00 cmp r3, #0 8009fb6: d11c bne.n 8009ff2 { pdev->classId = idx; 8009fb8: 7b7a ldrb r2, [r7, #13] 8009fba: 687b ldr r3, [r7, #4] 8009fbc: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8009fc0: 7b7a ldrb r2, [r7, #13] 8009fc2: 687b ldr r3, [r7, #4] 8009fc4: 32ae adds r2, #174 @ 0xae 8009fc6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009fca: 689b ldr r3, [r3, #8] 8009fcc: 2b00 cmp r3, #0 8009fce: d010 beq.n 8009ff2 { ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 8009fd0: 7b7a ldrb r2, [r7, #13] 8009fd2: 687b ldr r3, [r7, #4] 8009fd4: 32ae adds r2, #174 @ 0xae 8009fd6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8009fda: 689b ldr r3, [r3, #8] 8009fdc: 6839 ldr r1, [r7, #0] 8009fde: 6878 ldr r0, [r7, #4] 8009fe0: 4798 blx r3 8009fe2: 4603 mov r3, r0 8009fe4: 73fb strb r3, [r7, #15] } } } break; 8009fe6: e004 b.n 8009ff2 default: USBD_CtlError(pdev, req); 8009fe8: 6839 ldr r1, [r7, #0] 8009fea: 6878 ldr r0, [r7, #4] 8009fec: f000 fc2f bl 800a84e break; 8009ff0: e000 b.n 8009ff4 break; 8009ff2: bf00 nop } break; 8009ff4: e0ad b.n 800a152 case USB_REQ_GET_STATUS: switch (pdev->dev_state) 8009ff6: 687b ldr r3, [r7, #4] 8009ff8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8009ffc: b2db uxtb r3, r3 8009ffe: 2b02 cmp r3, #2 800a000: d002 beq.n 800a008 800a002: 2b03 cmp r3, #3 800a004: d033 beq.n 800a06e 800a006: e099 b.n 800a13c { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 800a008: 7bbb ldrb r3, [r7, #14] 800a00a: 2b00 cmp r3, #0 800a00c: d007 beq.n 800a01e 800a00e: 7bbb ldrb r3, [r7, #14] 800a010: 2b80 cmp r3, #128 @ 0x80 800a012: d004 beq.n 800a01e { USBD_CtlError(pdev, req); 800a014: 6839 ldr r1, [r7, #0] 800a016: 6878 ldr r0, [r7, #4] 800a018: f000 fc19 bl 800a84e break; 800a01c: e093 b.n 800a146 } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800a01e: f997 300e ldrsb.w r3, [r7, #14] 800a022: 2b00 cmp r3, #0 800a024: da0b bge.n 800a03e 800a026: 7bbb ldrb r3, [r7, #14] 800a028: f003 027f and.w r2, r3, #127 @ 0x7f 800a02c: 4613 mov r3, r2 800a02e: 009b lsls r3, r3, #2 800a030: 4413 add r3, r2 800a032: 009b lsls r3, r3, #2 800a034: 3310 adds r3, #16 800a036: 687a ldr r2, [r7, #4] 800a038: 4413 add r3, r2 800a03a: 3304 adds r3, #4 800a03c: e00b b.n 800a056 &pdev->ep_out[ep_addr & 0x7FU]; 800a03e: 7bbb ldrb r3, [r7, #14] 800a040: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800a044: 4613 mov r3, r2 800a046: 009b lsls r3, r3, #2 800a048: 4413 add r3, r2 800a04a: 009b lsls r3, r3, #2 800a04c: f503 73a8 add.w r3, r3, #336 @ 0x150 800a050: 687a ldr r2, [r7, #4] 800a052: 4413 add r3, r2 800a054: 3304 adds r3, #4 800a056: 60bb str r3, [r7, #8] pep->status = 0x0000U; 800a058: 68bb ldr r3, [r7, #8] 800a05a: 2200 movs r2, #0 800a05c: 739a strb r2, [r3, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 800a05e: 68bb ldr r3, [r7, #8] 800a060: 330e adds r3, #14 800a062: 2202 movs r2, #2 800a064: 4619 mov r1, r3 800a066: 6878 ldr r0, [r7, #4] 800a068: f000 fc6e bl 800a948 break; 800a06c: e06b b.n 800a146 case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 800a06e: f997 300e ldrsb.w r3, [r7, #14] 800a072: 2b00 cmp r3, #0 800a074: da11 bge.n 800a09a { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 800a076: 7bbb ldrb r3, [r7, #14] 800a078: f003 020f and.w r2, r3, #15 800a07c: 6879 ldr r1, [r7, #4] 800a07e: 4613 mov r3, r2 800a080: 009b lsls r3, r3, #2 800a082: 4413 add r3, r2 800a084: 009b lsls r3, r3, #2 800a086: 440b add r3, r1 800a088: 3323 adds r3, #35 @ 0x23 800a08a: 781b ldrb r3, [r3, #0] 800a08c: 2b00 cmp r3, #0 800a08e: d117 bne.n 800a0c0 { USBD_CtlError(pdev, req); 800a090: 6839 ldr r1, [r7, #0] 800a092: 6878 ldr r0, [r7, #4] 800a094: f000 fbdb bl 800a84e break; 800a098: e055 b.n 800a146 } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 800a09a: 7bbb ldrb r3, [r7, #14] 800a09c: f003 020f and.w r2, r3, #15 800a0a0: 6879 ldr r1, [r7, #4] 800a0a2: 4613 mov r3, r2 800a0a4: 009b lsls r3, r3, #2 800a0a6: 4413 add r3, r2 800a0a8: 009b lsls r3, r3, #2 800a0aa: 440b add r3, r1 800a0ac: f203 1363 addw r3, r3, #355 @ 0x163 800a0b0: 781b ldrb r3, [r3, #0] 800a0b2: 2b00 cmp r3, #0 800a0b4: d104 bne.n 800a0c0 { USBD_CtlError(pdev, req); 800a0b6: 6839 ldr r1, [r7, #0] 800a0b8: 6878 ldr r0, [r7, #4] 800a0ba: f000 fbc8 bl 800a84e break; 800a0be: e042 b.n 800a146 } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800a0c0: f997 300e ldrsb.w r3, [r7, #14] 800a0c4: 2b00 cmp r3, #0 800a0c6: da0b bge.n 800a0e0 800a0c8: 7bbb ldrb r3, [r7, #14] 800a0ca: f003 027f and.w r2, r3, #127 @ 0x7f 800a0ce: 4613 mov r3, r2 800a0d0: 009b lsls r3, r3, #2 800a0d2: 4413 add r3, r2 800a0d4: 009b lsls r3, r3, #2 800a0d6: 3310 adds r3, #16 800a0d8: 687a ldr r2, [r7, #4] 800a0da: 4413 add r3, r2 800a0dc: 3304 adds r3, #4 800a0de: e00b b.n 800a0f8 &pdev->ep_out[ep_addr & 0x7FU]; 800a0e0: 7bbb ldrb r3, [r7, #14] 800a0e2: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 800a0e6: 4613 mov r3, r2 800a0e8: 009b lsls r3, r3, #2 800a0ea: 4413 add r3, r2 800a0ec: 009b lsls r3, r3, #2 800a0ee: f503 73a8 add.w r3, r3, #336 @ 0x150 800a0f2: 687a ldr r2, [r7, #4] 800a0f4: 4413 add r3, r2 800a0f6: 3304 adds r3, #4 800a0f8: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 800a0fa: 7bbb ldrb r3, [r7, #14] 800a0fc: 2b00 cmp r3, #0 800a0fe: d002 beq.n 800a106 800a100: 7bbb ldrb r3, [r7, #14] 800a102: 2b80 cmp r3, #128 @ 0x80 800a104: d103 bne.n 800a10e { pep->status = 0x0000U; 800a106: 68bb ldr r3, [r7, #8] 800a108: 2200 movs r2, #0 800a10a: 739a strb r2, [r3, #14] 800a10c: e00e b.n 800a12c } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 800a10e: 7bbb ldrb r3, [r7, #14] 800a110: 4619 mov r1, r3 800a112: 6878 ldr r0, [r7, #4] 800a114: f001 f80c bl 800b130 800a118: 4603 mov r3, r0 800a11a: 2b00 cmp r3, #0 800a11c: d003 beq.n 800a126 { pep->status = 0x0001U; 800a11e: 68bb ldr r3, [r7, #8] 800a120: 2201 movs r2, #1 800a122: 739a strb r2, [r3, #14] 800a124: e002 b.n 800a12c } else { pep->status = 0x0000U; 800a126: 68bb ldr r3, [r7, #8] 800a128: 2200 movs r2, #0 800a12a: 739a strb r2, [r3, #14] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 800a12c: 68bb ldr r3, [r7, #8] 800a12e: 330e adds r3, #14 800a130: 2202 movs r2, #2 800a132: 4619 mov r1, r3 800a134: 6878 ldr r0, [r7, #4] 800a136: f000 fc07 bl 800a948 break; 800a13a: e004 b.n 800a146 default: USBD_CtlError(pdev, req); 800a13c: 6839 ldr r1, [r7, #0] 800a13e: 6878 ldr r0, [r7, #4] 800a140: f000 fb85 bl 800a84e break; 800a144: bf00 nop } break; 800a146: e004 b.n 800a152 default: USBD_CtlError(pdev, req); 800a148: 6839 ldr r1, [r7, #0] 800a14a: 6878 ldr r0, [r7, #4] 800a14c: f000 fb7f bl 800a84e break; 800a150: bf00 nop } break; 800a152: e005 b.n 800a160 default: USBD_CtlError(pdev, req); 800a154: 6839 ldr r1, [r7, #0] 800a156: 6878 ldr r0, [r7, #4] 800a158: f000 fb79 bl 800a84e break; 800a15c: e000 b.n 800a160 break; 800a15e: bf00 nop } return ret; 800a160: 7bfb ldrb r3, [r7, #15] } 800a162: 4618 mov r0, r3 800a164: 3710 adds r7, #16 800a166: 46bd mov sp, r7 800a168: bd80 pop {r7, pc} ... 0800a16c : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a16c: b580 push {r7, lr} 800a16e: b084 sub sp, #16 800a170: af00 add r7, sp, #0 800a172: 6078 str r0, [r7, #4] 800a174: 6039 str r1, [r7, #0] uint16_t len = 0U; 800a176: 2300 movs r3, #0 800a178: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 800a17a: 2300 movs r3, #0 800a17c: 60fb str r3, [r7, #12] uint8_t err = 0U; 800a17e: 2300 movs r3, #0 800a180: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 800a182: 683b ldr r3, [r7, #0] 800a184: 885b ldrh r3, [r3, #2] 800a186: 0a1b lsrs r3, r3, #8 800a188: b29b uxth r3, r3 800a18a: 3b01 subs r3, #1 800a18c: 2b0e cmp r3, #14 800a18e: f200 8152 bhi.w 800a436 800a192: a201 add r2, pc, #4 @ (adr r2, 800a198 ) 800a194: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a198: 0800a209 .word 0x0800a209 800a19c: 0800a221 .word 0x0800a221 800a1a0: 0800a261 .word 0x0800a261 800a1a4: 0800a437 .word 0x0800a437 800a1a8: 0800a437 .word 0x0800a437 800a1ac: 0800a3d7 .word 0x0800a3d7 800a1b0: 0800a403 .word 0x0800a403 800a1b4: 0800a437 .word 0x0800a437 800a1b8: 0800a437 .word 0x0800a437 800a1bc: 0800a437 .word 0x0800a437 800a1c0: 0800a437 .word 0x0800a437 800a1c4: 0800a437 .word 0x0800a437 800a1c8: 0800a437 .word 0x0800a437 800a1cc: 0800a437 .word 0x0800a437 800a1d0: 0800a1d5 .word 0x0800a1d5 { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) 800a1d4: 687b ldr r3, [r7, #4] 800a1d6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a1da: 69db ldr r3, [r3, #28] 800a1dc: 2b00 cmp r3, #0 800a1de: d00b beq.n 800a1f8 { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); 800a1e0: 687b ldr r3, [r7, #4] 800a1e2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a1e6: 69db ldr r3, [r3, #28] 800a1e8: 687a ldr r2, [r7, #4] 800a1ea: 7c12 ldrb r2, [r2, #16] 800a1ec: f107 0108 add.w r1, r7, #8 800a1f0: 4610 mov r0, r2 800a1f2: 4798 blx r3 800a1f4: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a1f6: e126 b.n 800a446 USBD_CtlError(pdev, req); 800a1f8: 6839 ldr r1, [r7, #0] 800a1fa: 6878 ldr r0, [r7, #4] 800a1fc: f000 fb27 bl 800a84e err++; 800a200: 7afb ldrb r3, [r7, #11] 800a202: 3301 adds r3, #1 800a204: 72fb strb r3, [r7, #11] break; 800a206: e11e b.n 800a446 #endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 800a208: 687b ldr r3, [r7, #4] 800a20a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a20e: 681b ldr r3, [r3, #0] 800a210: 687a ldr r2, [r7, #4] 800a212: 7c12 ldrb r2, [r2, #16] 800a214: f107 0108 add.w r1, r7, #8 800a218: 4610 mov r0, r2 800a21a: 4798 blx r3 800a21c: 60f8 str r0, [r7, #12] break; 800a21e: e112 b.n 800a446 case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 800a220: 687b ldr r3, [r7, #4] 800a222: 7c1b ldrb r3, [r3, #16] 800a224: 2b00 cmp r3, #0 800a226: d10d bne.n 800a244 pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); 800a228: 687b ldr r3, [r7, #4] 800a22a: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800a22e: 6a9b ldr r3, [r3, #40] @ 0x28 800a230: f107 0208 add.w r2, r7, #8 800a234: 4610 mov r0, r2 800a236: 4798 blx r3 800a238: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800a23a: 68fb ldr r3, [r7, #12] 800a23c: 3301 adds r3, #1 800a23e: 2202 movs r2, #2 800a240: 701a strb r2, [r3, #0] { pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 800a242: e100 b.n 800a446 pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); 800a244: 687b ldr r3, [r7, #4] 800a246: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800a24a: 6adb ldr r3, [r3, #44] @ 0x2c 800a24c: f107 0208 add.w r2, r7, #8 800a250: 4610 mov r0, r2 800a252: 4798 blx r3 800a254: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 800a256: 68fb ldr r3, [r7, #12] 800a258: 3301 adds r3, #1 800a25a: 2202 movs r2, #2 800a25c: 701a strb r2, [r3, #0] break; 800a25e: e0f2 b.n 800a446 case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 800a260: 683b ldr r3, [r7, #0] 800a262: 885b ldrh r3, [r3, #2] 800a264: b2db uxtb r3, r3 800a266: 2b05 cmp r3, #5 800a268: f200 80ac bhi.w 800a3c4 800a26c: a201 add r2, pc, #4 @ (adr r2, 800a274 ) 800a26e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a272: bf00 nop 800a274: 0800a28d .word 0x0800a28d 800a278: 0800a2c1 .word 0x0800a2c1 800a27c: 0800a2f5 .word 0x0800a2f5 800a280: 0800a329 .word 0x0800a329 800a284: 0800a35d .word 0x0800a35d 800a288: 0800a391 .word 0x0800a391 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 800a28c: 687b ldr r3, [r7, #4] 800a28e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a292: 685b ldr r3, [r3, #4] 800a294: 2b00 cmp r3, #0 800a296: d00b beq.n 800a2b0 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 800a298: 687b ldr r3, [r7, #4] 800a29a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a29e: 685b ldr r3, [r3, #4] 800a2a0: 687a ldr r2, [r7, #4] 800a2a2: 7c12 ldrb r2, [r2, #16] 800a2a4: f107 0108 add.w r1, r7, #8 800a2a8: 4610 mov r0, r2 800a2aa: 4798 blx r3 800a2ac: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a2ae: e091 b.n 800a3d4 USBD_CtlError(pdev, req); 800a2b0: 6839 ldr r1, [r7, #0] 800a2b2: 6878 ldr r0, [r7, #4] 800a2b4: f000 facb bl 800a84e err++; 800a2b8: 7afb ldrb r3, [r7, #11] 800a2ba: 3301 adds r3, #1 800a2bc: 72fb strb r3, [r7, #11] break; 800a2be: e089 b.n 800a3d4 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 800a2c0: 687b ldr r3, [r7, #4] 800a2c2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a2c6: 689b ldr r3, [r3, #8] 800a2c8: 2b00 cmp r3, #0 800a2ca: d00b beq.n 800a2e4 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 800a2cc: 687b ldr r3, [r7, #4] 800a2ce: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a2d2: 689b ldr r3, [r3, #8] 800a2d4: 687a ldr r2, [r7, #4] 800a2d6: 7c12 ldrb r2, [r2, #16] 800a2d8: f107 0108 add.w r1, r7, #8 800a2dc: 4610 mov r0, r2 800a2de: 4798 blx r3 800a2e0: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a2e2: e077 b.n 800a3d4 USBD_CtlError(pdev, req); 800a2e4: 6839 ldr r1, [r7, #0] 800a2e6: 6878 ldr r0, [r7, #4] 800a2e8: f000 fab1 bl 800a84e err++; 800a2ec: 7afb ldrb r3, [r7, #11] 800a2ee: 3301 adds r3, #1 800a2f0: 72fb strb r3, [r7, #11] break; 800a2f2: e06f b.n 800a3d4 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 800a2f4: 687b ldr r3, [r7, #4] 800a2f6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a2fa: 68db ldr r3, [r3, #12] 800a2fc: 2b00 cmp r3, #0 800a2fe: d00b beq.n 800a318 { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 800a300: 687b ldr r3, [r7, #4] 800a302: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a306: 68db ldr r3, [r3, #12] 800a308: 687a ldr r2, [r7, #4] 800a30a: 7c12 ldrb r2, [r2, #16] 800a30c: f107 0108 add.w r1, r7, #8 800a310: 4610 mov r0, r2 800a312: 4798 blx r3 800a314: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a316: e05d b.n 800a3d4 USBD_CtlError(pdev, req); 800a318: 6839 ldr r1, [r7, #0] 800a31a: 6878 ldr r0, [r7, #4] 800a31c: f000 fa97 bl 800a84e err++; 800a320: 7afb ldrb r3, [r7, #11] 800a322: 3301 adds r3, #1 800a324: 72fb strb r3, [r7, #11] break; 800a326: e055 b.n 800a3d4 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 800a328: 687b ldr r3, [r7, #4] 800a32a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a32e: 691b ldr r3, [r3, #16] 800a330: 2b00 cmp r3, #0 800a332: d00b beq.n 800a34c { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 800a334: 687b ldr r3, [r7, #4] 800a336: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a33a: 691b ldr r3, [r3, #16] 800a33c: 687a ldr r2, [r7, #4] 800a33e: 7c12 ldrb r2, [r2, #16] 800a340: f107 0108 add.w r1, r7, #8 800a344: 4610 mov r0, r2 800a346: 4798 blx r3 800a348: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a34a: e043 b.n 800a3d4 USBD_CtlError(pdev, req); 800a34c: 6839 ldr r1, [r7, #0] 800a34e: 6878 ldr r0, [r7, #4] 800a350: f000 fa7d bl 800a84e err++; 800a354: 7afb ldrb r3, [r7, #11] 800a356: 3301 adds r3, #1 800a358: 72fb strb r3, [r7, #11] break; 800a35a: e03b b.n 800a3d4 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 800a35c: 687b ldr r3, [r7, #4] 800a35e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a362: 695b ldr r3, [r3, #20] 800a364: 2b00 cmp r3, #0 800a366: d00b beq.n 800a380 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 800a368: 687b ldr r3, [r7, #4] 800a36a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a36e: 695b ldr r3, [r3, #20] 800a370: 687a ldr r2, [r7, #4] 800a372: 7c12 ldrb r2, [r2, #16] 800a374: f107 0108 add.w r1, r7, #8 800a378: 4610 mov r0, r2 800a37a: 4798 blx r3 800a37c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a37e: e029 b.n 800a3d4 USBD_CtlError(pdev, req); 800a380: 6839 ldr r1, [r7, #0] 800a382: 6878 ldr r0, [r7, #4] 800a384: f000 fa63 bl 800a84e err++; 800a388: 7afb ldrb r3, [r7, #11] 800a38a: 3301 adds r3, #1 800a38c: 72fb strb r3, [r7, #11] break; 800a38e: e021 b.n 800a3d4 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 800a390: 687b ldr r3, [r7, #4] 800a392: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a396: 699b ldr r3, [r3, #24] 800a398: 2b00 cmp r3, #0 800a39a: d00b beq.n 800a3b4 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 800a39c: 687b ldr r3, [r7, #4] 800a39e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 800a3a2: 699b ldr r3, [r3, #24] 800a3a4: 687a ldr r2, [r7, #4] 800a3a6: 7c12 ldrb r2, [r2, #16] 800a3a8: f107 0108 add.w r1, r7, #8 800a3ac: 4610 mov r0, r2 800a3ae: 4798 blx r3 800a3b0: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a3b2: e00f b.n 800a3d4 USBD_CtlError(pdev, req); 800a3b4: 6839 ldr r1, [r7, #0] 800a3b6: 6878 ldr r0, [r7, #4] 800a3b8: f000 fa49 bl 800a84e err++; 800a3bc: 7afb ldrb r3, [r7, #11] 800a3be: 3301 adds r3, #1 800a3c0: 72fb strb r3, [r7, #11] break; 800a3c2: e007 b.n 800a3d4 err++; } #endif /* USBD_SUPPORT_USER_STRING_DESC */ #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 800a3c4: 6839 ldr r1, [r7, #0] 800a3c6: 6878 ldr r0, [r7, #4] 800a3c8: f000 fa41 bl 800a84e err++; 800a3cc: 7afb ldrb r3, [r7, #11] 800a3ce: 3301 adds r3, #1 800a3d0: 72fb strb r3, [r7, #11] #endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ break; 800a3d2: bf00 nop } break; 800a3d4: e037 b.n 800a446 case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 800a3d6: 687b ldr r3, [r7, #4] 800a3d8: 7c1b ldrb r3, [r3, #16] 800a3da: 2b00 cmp r3, #0 800a3dc: d109 bne.n 800a3f2 pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); 800a3de: 687b ldr r3, [r7, #4] 800a3e0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800a3e4: 6b5b ldr r3, [r3, #52] @ 0x34 800a3e6: f107 0208 add.w r2, r7, #8 800a3ea: 4610 mov r0, r2 800a3ec: 4798 blx r3 800a3ee: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 800a3f0: e029 b.n 800a446 USBD_CtlError(pdev, req); 800a3f2: 6839 ldr r1, [r7, #0] 800a3f4: 6878 ldr r0, [r7, #4] 800a3f6: f000 fa2a bl 800a84e err++; 800a3fa: 7afb ldrb r3, [r7, #11] 800a3fc: 3301 adds r3, #1 800a3fe: 72fb strb r3, [r7, #11] break; 800a400: e021 b.n 800a446 case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 800a402: 687b ldr r3, [r7, #4] 800a404: 7c1b ldrb r3, [r3, #16] 800a406: 2b00 cmp r3, #0 800a408: d10d bne.n 800a426 pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); 800a40a: 687b ldr r3, [r7, #4] 800a40c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 800a410: 6b1b ldr r3, [r3, #48] @ 0x30 800a412: f107 0208 add.w r2, r7, #8 800a416: 4610 mov r0, r2 800a418: 4798 blx r3 800a41a: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 800a41c: 68fb ldr r3, [r7, #12] 800a41e: 3301 adds r3, #1 800a420: 2207 movs r2, #7 800a422: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 800a424: e00f b.n 800a446 USBD_CtlError(pdev, req); 800a426: 6839 ldr r1, [r7, #0] 800a428: 6878 ldr r0, [r7, #4] 800a42a: f000 fa10 bl 800a84e err++; 800a42e: 7afb ldrb r3, [r7, #11] 800a430: 3301 adds r3, #1 800a432: 72fb strb r3, [r7, #11] break; 800a434: e007 b.n 800a446 default: USBD_CtlError(pdev, req); 800a436: 6839 ldr r1, [r7, #0] 800a438: 6878 ldr r0, [r7, #4] 800a43a: f000 fa08 bl 800a84e err++; 800a43e: 7afb ldrb r3, [r7, #11] 800a440: 3301 adds r3, #1 800a442: 72fb strb r3, [r7, #11] break; 800a444: bf00 nop } if (err != 0U) 800a446: 7afb ldrb r3, [r7, #11] 800a448: 2b00 cmp r3, #0 800a44a: d11e bne.n 800a48a { return; } if (req->wLength != 0U) 800a44c: 683b ldr r3, [r7, #0] 800a44e: 88db ldrh r3, [r3, #6] 800a450: 2b00 cmp r3, #0 800a452: d016 beq.n 800a482 { if (len != 0U) 800a454: 893b ldrh r3, [r7, #8] 800a456: 2b00 cmp r3, #0 800a458: d00e beq.n 800a478 { len = MIN(len, req->wLength); 800a45a: 683b ldr r3, [r7, #0] 800a45c: 88da ldrh r2, [r3, #6] 800a45e: 893b ldrh r3, [r7, #8] 800a460: 4293 cmp r3, r2 800a462: bf28 it cs 800a464: 4613 movcs r3, r2 800a466: b29b uxth r3, r3 800a468: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 800a46a: 893b ldrh r3, [r7, #8] 800a46c: 461a mov r2, r3 800a46e: 68f9 ldr r1, [r7, #12] 800a470: 6878 ldr r0, [r7, #4] 800a472: f000 fa69 bl 800a948 800a476: e009 b.n 800a48c } else { USBD_CtlError(pdev, req); 800a478: 6839 ldr r1, [r7, #0] 800a47a: 6878 ldr r0, [r7, #4] 800a47c: f000 f9e7 bl 800a84e 800a480: e004 b.n 800a48c } } else { (void)USBD_CtlSendStatus(pdev); 800a482: 6878 ldr r0, [r7, #4] 800a484: f000 faa0 bl 800a9c8 800a488: e000 b.n 800a48c return; 800a48a: bf00 nop } } 800a48c: 3710 adds r7, #16 800a48e: 46bd mov sp, r7 800a490: bd80 pop {r7, pc} 800a492: bf00 nop 0800a494 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a494: b580 push {r7, lr} 800a496: b084 sub sp, #16 800a498: af00 add r7, sp, #0 800a49a: 6078 str r0, [r7, #4] 800a49c: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 800a49e: 683b ldr r3, [r7, #0] 800a4a0: 889b ldrh r3, [r3, #4] 800a4a2: 2b00 cmp r3, #0 800a4a4: d131 bne.n 800a50a 800a4a6: 683b ldr r3, [r7, #0] 800a4a8: 88db ldrh r3, [r3, #6] 800a4aa: 2b00 cmp r3, #0 800a4ac: d12d bne.n 800a50a 800a4ae: 683b ldr r3, [r7, #0] 800a4b0: 885b ldrh r3, [r3, #2] 800a4b2: 2b7f cmp r3, #127 @ 0x7f 800a4b4: d829 bhi.n 800a50a { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 800a4b6: 683b ldr r3, [r7, #0] 800a4b8: 885b ldrh r3, [r3, #2] 800a4ba: b2db uxtb r3, r3 800a4bc: f003 037f and.w r3, r3, #127 @ 0x7f 800a4c0: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 800a4c2: 687b ldr r3, [r7, #4] 800a4c4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a4c8: b2db uxtb r3, r3 800a4ca: 2b03 cmp r3, #3 800a4cc: d104 bne.n 800a4d8 { USBD_CtlError(pdev, req); 800a4ce: 6839 ldr r1, [r7, #0] 800a4d0: 6878 ldr r0, [r7, #4] 800a4d2: f000 f9bc bl 800a84e if (pdev->dev_state == USBD_STATE_CONFIGURED) 800a4d6: e01d b.n 800a514 } else { pdev->dev_address = dev_addr; 800a4d8: 687b ldr r3, [r7, #4] 800a4da: 7bfa ldrb r2, [r7, #15] 800a4dc: f883 229e strb.w r2, [r3, #670] @ 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 800a4e0: 7bfb ldrb r3, [r7, #15] 800a4e2: 4619 mov r1, r3 800a4e4: 6878 ldr r0, [r7, #4] 800a4e6: f000 fe4f bl 800b188 (void)USBD_CtlSendStatus(pdev); 800a4ea: 6878 ldr r0, [r7, #4] 800a4ec: f000 fa6c bl 800a9c8 if (dev_addr != 0U) 800a4f0: 7bfb ldrb r3, [r7, #15] 800a4f2: 2b00 cmp r3, #0 800a4f4: d004 beq.n 800a500 { pdev->dev_state = USBD_STATE_ADDRESSED; 800a4f6: 687b ldr r3, [r7, #4] 800a4f8: 2202 movs r2, #2 800a4fa: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 800a4fe: e009 b.n 800a514 } else { pdev->dev_state = USBD_STATE_DEFAULT; 800a500: 687b ldr r3, [r7, #4] 800a502: 2201 movs r2, #1 800a504: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 800a508: e004 b.n 800a514 } } } else { USBD_CtlError(pdev, req); 800a50a: 6839 ldr r1, [r7, #0] 800a50c: 6878 ldr r0, [r7, #4] 800a50e: f000 f99e bl 800a84e } } 800a512: bf00 nop 800a514: bf00 nop 800a516: 3710 adds r7, #16 800a518: 46bd mov sp, r7 800a51a: bd80 pop {r7, pc} 0800a51c : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a51c: b580 push {r7, lr} 800a51e: b084 sub sp, #16 800a520: af00 add r7, sp, #0 800a522: 6078 str r0, [r7, #4] 800a524: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 800a526: 2300 movs r3, #0 800a528: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 800a52a: 683b ldr r3, [r7, #0] 800a52c: 885b ldrh r3, [r3, #2] 800a52e: b2da uxtb r2, r3 800a530: 4b4e ldr r3, [pc, #312] @ (800a66c ) 800a532: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 800a534: 4b4d ldr r3, [pc, #308] @ (800a66c ) 800a536: 781b ldrb r3, [r3, #0] 800a538: 2b01 cmp r3, #1 800a53a: d905 bls.n 800a548 { USBD_CtlError(pdev, req); 800a53c: 6839 ldr r1, [r7, #0] 800a53e: 6878 ldr r0, [r7, #4] 800a540: f000 f985 bl 800a84e return USBD_FAIL; 800a544: 2303 movs r3, #3 800a546: e08c b.n 800a662 } switch (pdev->dev_state) 800a548: 687b ldr r3, [r7, #4] 800a54a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a54e: b2db uxtb r3, r3 800a550: 2b02 cmp r3, #2 800a552: d002 beq.n 800a55a 800a554: 2b03 cmp r3, #3 800a556: d029 beq.n 800a5ac 800a558: e075 b.n 800a646 { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 800a55a: 4b44 ldr r3, [pc, #272] @ (800a66c ) 800a55c: 781b ldrb r3, [r3, #0] 800a55e: 2b00 cmp r3, #0 800a560: d020 beq.n 800a5a4 { pdev->dev_config = cfgidx; 800a562: 4b42 ldr r3, [pc, #264] @ (800a66c ) 800a564: 781b ldrb r3, [r3, #0] 800a566: 461a mov r2, r3 800a568: 687b ldr r3, [r7, #4] 800a56a: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 800a56c: 4b3f ldr r3, [pc, #252] @ (800a66c ) 800a56e: 781b ldrb r3, [r3, #0] 800a570: 4619 mov r1, r3 800a572: 6878 ldr r0, [r7, #4] 800a574: f7fe ffa3 bl 80094be 800a578: 4603 mov r3, r0 800a57a: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 800a57c: 7bfb ldrb r3, [r7, #15] 800a57e: 2b00 cmp r3, #0 800a580: d008 beq.n 800a594 { USBD_CtlError(pdev, req); 800a582: 6839 ldr r1, [r7, #0] 800a584: 6878 ldr r0, [r7, #4] 800a586: f000 f962 bl 800a84e pdev->dev_state = USBD_STATE_ADDRESSED; 800a58a: 687b ldr r3, [r7, #4] 800a58c: 2202 movs r2, #2 800a58e: f883 229c strb.w r2, [r3, #668] @ 0x29c } else { (void)USBD_CtlSendStatus(pdev); } break; 800a592: e065 b.n 800a660 (void)USBD_CtlSendStatus(pdev); 800a594: 6878 ldr r0, [r7, #4] 800a596: f000 fa17 bl 800a9c8 pdev->dev_state = USBD_STATE_CONFIGURED; 800a59a: 687b ldr r3, [r7, #4] 800a59c: 2203 movs r2, #3 800a59e: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 800a5a2: e05d b.n 800a660 (void)USBD_CtlSendStatus(pdev); 800a5a4: 6878 ldr r0, [r7, #4] 800a5a6: f000 fa0f bl 800a9c8 break; 800a5aa: e059 b.n 800a660 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 800a5ac: 4b2f ldr r3, [pc, #188] @ (800a66c ) 800a5ae: 781b ldrb r3, [r3, #0] 800a5b0: 2b00 cmp r3, #0 800a5b2: d112 bne.n 800a5da { pdev->dev_state = USBD_STATE_ADDRESSED; 800a5b4: 687b ldr r3, [r7, #4] 800a5b6: 2202 movs r2, #2 800a5b8: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->dev_config = cfgidx; 800a5bc: 4b2b ldr r3, [pc, #172] @ (800a66c ) 800a5be: 781b ldrb r3, [r3, #0] 800a5c0: 461a mov r2, r3 800a5c2: 687b ldr r3, [r7, #4] 800a5c4: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 800a5c6: 4b29 ldr r3, [pc, #164] @ (800a66c ) 800a5c8: 781b ldrb r3, [r3, #0] 800a5ca: 4619 mov r1, r3 800a5cc: 6878 ldr r0, [r7, #4] 800a5ce: f7fe ff92 bl 80094f6 (void)USBD_CtlSendStatus(pdev); 800a5d2: 6878 ldr r0, [r7, #4] 800a5d4: f000 f9f8 bl 800a9c8 } else { (void)USBD_CtlSendStatus(pdev); } break; 800a5d8: e042 b.n 800a660 else if (cfgidx != pdev->dev_config) 800a5da: 4b24 ldr r3, [pc, #144] @ (800a66c ) 800a5dc: 781b ldrb r3, [r3, #0] 800a5de: 461a mov r2, r3 800a5e0: 687b ldr r3, [r7, #4] 800a5e2: 685b ldr r3, [r3, #4] 800a5e4: 429a cmp r2, r3 800a5e6: d02a beq.n 800a63e (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 800a5e8: 687b ldr r3, [r7, #4] 800a5ea: 685b ldr r3, [r3, #4] 800a5ec: b2db uxtb r3, r3 800a5ee: 4619 mov r1, r3 800a5f0: 6878 ldr r0, [r7, #4] 800a5f2: f7fe ff80 bl 80094f6 pdev->dev_config = cfgidx; 800a5f6: 4b1d ldr r3, [pc, #116] @ (800a66c ) 800a5f8: 781b ldrb r3, [r3, #0] 800a5fa: 461a mov r2, r3 800a5fc: 687b ldr r3, [r7, #4] 800a5fe: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 800a600: 4b1a ldr r3, [pc, #104] @ (800a66c ) 800a602: 781b ldrb r3, [r3, #0] 800a604: 4619 mov r1, r3 800a606: 6878 ldr r0, [r7, #4] 800a608: f7fe ff59 bl 80094be 800a60c: 4603 mov r3, r0 800a60e: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 800a610: 7bfb ldrb r3, [r7, #15] 800a612: 2b00 cmp r3, #0 800a614: d00f beq.n 800a636 USBD_CtlError(pdev, req); 800a616: 6839 ldr r1, [r7, #0] 800a618: 6878 ldr r0, [r7, #4] 800a61a: f000 f918 bl 800a84e (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 800a61e: 687b ldr r3, [r7, #4] 800a620: 685b ldr r3, [r3, #4] 800a622: b2db uxtb r3, r3 800a624: 4619 mov r1, r3 800a626: 6878 ldr r0, [r7, #4] 800a628: f7fe ff65 bl 80094f6 pdev->dev_state = USBD_STATE_ADDRESSED; 800a62c: 687b ldr r3, [r7, #4] 800a62e: 2202 movs r2, #2 800a630: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 800a634: e014 b.n 800a660 (void)USBD_CtlSendStatus(pdev); 800a636: 6878 ldr r0, [r7, #4] 800a638: f000 f9c6 bl 800a9c8 break; 800a63c: e010 b.n 800a660 (void)USBD_CtlSendStatus(pdev); 800a63e: 6878 ldr r0, [r7, #4] 800a640: f000 f9c2 bl 800a9c8 break; 800a644: e00c b.n 800a660 default: USBD_CtlError(pdev, req); 800a646: 6839 ldr r1, [r7, #0] 800a648: 6878 ldr r0, [r7, #4] 800a64a: f000 f900 bl 800a84e (void)USBD_ClrClassConfig(pdev, cfgidx); 800a64e: 4b07 ldr r3, [pc, #28] @ (800a66c ) 800a650: 781b ldrb r3, [r3, #0] 800a652: 4619 mov r1, r3 800a654: 6878 ldr r0, [r7, #4] 800a656: f7fe ff4e bl 80094f6 ret = USBD_FAIL; 800a65a: 2303 movs r3, #3 800a65c: 73fb strb r3, [r7, #15] break; 800a65e: bf00 nop } return ret; 800a660: 7bfb ldrb r3, [r7, #15] } 800a662: 4618 mov r0, r3 800a664: 3710 adds r7, #16 800a666: 46bd mov sp, r7 800a668: bd80 pop {r7, pc} 800a66a: bf00 nop 800a66c: 20000e24 .word 0x20000e24 0800a670 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a670: b580 push {r7, lr} 800a672: b082 sub sp, #8 800a674: af00 add r7, sp, #0 800a676: 6078 str r0, [r7, #4] 800a678: 6039 str r1, [r7, #0] if (req->wLength != 1U) 800a67a: 683b ldr r3, [r7, #0] 800a67c: 88db ldrh r3, [r3, #6] 800a67e: 2b01 cmp r3, #1 800a680: d004 beq.n 800a68c { USBD_CtlError(pdev, req); 800a682: 6839 ldr r1, [r7, #0] 800a684: 6878 ldr r0, [r7, #4] 800a686: f000 f8e2 bl 800a84e default: USBD_CtlError(pdev, req); break; } } } 800a68a: e023 b.n 800a6d4 switch (pdev->dev_state) 800a68c: 687b ldr r3, [r7, #4] 800a68e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a692: b2db uxtb r3, r3 800a694: 2b02 cmp r3, #2 800a696: dc02 bgt.n 800a69e 800a698: 2b00 cmp r3, #0 800a69a: dc03 bgt.n 800a6a4 800a69c: e015 b.n 800a6ca 800a69e: 2b03 cmp r3, #3 800a6a0: d00b beq.n 800a6ba 800a6a2: e012 b.n 800a6ca pdev->dev_default_config = 0U; 800a6a4: 687b ldr r3, [r7, #4] 800a6a6: 2200 movs r2, #0 800a6a8: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 800a6aa: 687b ldr r3, [r7, #4] 800a6ac: 3308 adds r3, #8 800a6ae: 2201 movs r2, #1 800a6b0: 4619 mov r1, r3 800a6b2: 6878 ldr r0, [r7, #4] 800a6b4: f000 f948 bl 800a948 break; 800a6b8: e00c b.n 800a6d4 (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 800a6ba: 687b ldr r3, [r7, #4] 800a6bc: 3304 adds r3, #4 800a6be: 2201 movs r2, #1 800a6c0: 4619 mov r1, r3 800a6c2: 6878 ldr r0, [r7, #4] 800a6c4: f000 f940 bl 800a948 break; 800a6c8: e004 b.n 800a6d4 USBD_CtlError(pdev, req); 800a6ca: 6839 ldr r1, [r7, #0] 800a6cc: 6878 ldr r0, [r7, #4] 800a6ce: f000 f8be bl 800a84e break; 800a6d2: bf00 nop } 800a6d4: bf00 nop 800a6d6: 3708 adds r7, #8 800a6d8: 46bd mov sp, r7 800a6da: bd80 pop {r7, pc} 0800a6dc : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a6dc: b580 push {r7, lr} 800a6de: b082 sub sp, #8 800a6e0: af00 add r7, sp, #0 800a6e2: 6078 str r0, [r7, #4] 800a6e4: 6039 str r1, [r7, #0] switch (pdev->dev_state) 800a6e6: 687b ldr r3, [r7, #4] 800a6e8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a6ec: b2db uxtb r3, r3 800a6ee: 3b01 subs r3, #1 800a6f0: 2b02 cmp r3, #2 800a6f2: d81e bhi.n 800a732 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 800a6f4: 683b ldr r3, [r7, #0] 800a6f6: 88db ldrh r3, [r3, #6] 800a6f8: 2b02 cmp r3, #2 800a6fa: d004 beq.n 800a706 { USBD_CtlError(pdev, req); 800a6fc: 6839 ldr r1, [r7, #0] 800a6fe: 6878 ldr r0, [r7, #4] 800a700: f000 f8a5 bl 800a84e break; 800a704: e01a b.n 800a73c } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 800a706: 687b ldr r3, [r7, #4] 800a708: 2201 movs r2, #1 800a70a: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif /* USBD_SELF_POWERED */ if (pdev->dev_remote_wakeup != 0U) 800a70c: 687b ldr r3, [r7, #4] 800a70e: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 800a712: 2b00 cmp r3, #0 800a714: d005 beq.n 800a722 { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 800a716: 687b ldr r3, [r7, #4] 800a718: 68db ldr r3, [r3, #12] 800a71a: f043 0202 orr.w r2, r3, #2 800a71e: 687b ldr r3, [r7, #4] 800a720: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 800a722: 687b ldr r3, [r7, #4] 800a724: 330c adds r3, #12 800a726: 2202 movs r2, #2 800a728: 4619 mov r1, r3 800a72a: 6878 ldr r0, [r7, #4] 800a72c: f000 f90c bl 800a948 break; 800a730: e004 b.n 800a73c default: USBD_CtlError(pdev, req); 800a732: 6839 ldr r1, [r7, #0] 800a734: 6878 ldr r0, [r7, #4] 800a736: f000 f88a bl 800a84e break; 800a73a: bf00 nop } } 800a73c: bf00 nop 800a73e: 3708 adds r7, #8 800a740: 46bd mov sp, r7 800a742: bd80 pop {r7, pc} 0800a744 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a744: b580 push {r7, lr} 800a746: b082 sub sp, #8 800a748: af00 add r7, sp, #0 800a74a: 6078 str r0, [r7, #4] 800a74c: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 800a74e: 683b ldr r3, [r7, #0] 800a750: 885b ldrh r3, [r3, #2] 800a752: 2b01 cmp r3, #1 800a754: d107 bne.n 800a766 { pdev->dev_remote_wakeup = 1U; 800a756: 687b ldr r3, [r7, #4] 800a758: 2201 movs r2, #1 800a75a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 800a75e: 6878 ldr r0, [r7, #4] 800a760: f000 f932 bl 800a9c8 } else { USBD_CtlError(pdev, req); } } 800a764: e013 b.n 800a78e else if (req->wValue == USB_FEATURE_TEST_MODE) 800a766: 683b ldr r3, [r7, #0] 800a768: 885b ldrh r3, [r3, #2] 800a76a: 2b02 cmp r3, #2 800a76c: d10b bne.n 800a786 pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); 800a76e: 683b ldr r3, [r7, #0] 800a770: 889b ldrh r3, [r3, #4] 800a772: 0a1b lsrs r3, r3, #8 800a774: b29b uxth r3, r3 800a776: b2da uxtb r2, r3 800a778: 687b ldr r3, [r7, #4] 800a77a: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 (void)USBD_CtlSendStatus(pdev); 800a77e: 6878 ldr r0, [r7, #4] 800a780: f000 f922 bl 800a9c8 } 800a784: e003 b.n 800a78e USBD_CtlError(pdev, req); 800a786: 6839 ldr r1, [r7, #0] 800a788: 6878 ldr r0, [r7, #4] 800a78a: f000 f860 bl 800a84e } 800a78e: bf00 nop 800a790: 3708 adds r7, #8 800a792: 46bd mov sp, r7 800a794: bd80 pop {r7, pc} 0800a796 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a796: b580 push {r7, lr} 800a798: b082 sub sp, #8 800a79a: af00 add r7, sp, #0 800a79c: 6078 str r0, [r7, #4] 800a79e: 6039 str r1, [r7, #0] switch (pdev->dev_state) 800a7a0: 687b ldr r3, [r7, #4] 800a7a2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 800a7a6: b2db uxtb r3, r3 800a7a8: 3b01 subs r3, #1 800a7aa: 2b02 cmp r3, #2 800a7ac: d80b bhi.n 800a7c6 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 800a7ae: 683b ldr r3, [r7, #0] 800a7b0: 885b ldrh r3, [r3, #2] 800a7b2: 2b01 cmp r3, #1 800a7b4: d10c bne.n 800a7d0 { pdev->dev_remote_wakeup = 0U; 800a7b6: 687b ldr r3, [r7, #4] 800a7b8: 2200 movs r2, #0 800a7ba: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 800a7be: 6878 ldr r0, [r7, #4] 800a7c0: f000 f902 bl 800a9c8 } break; 800a7c4: e004 b.n 800a7d0 default: USBD_CtlError(pdev, req); 800a7c6: 6839 ldr r1, [r7, #0] 800a7c8: 6878 ldr r0, [r7, #4] 800a7ca: f000 f840 bl 800a84e break; 800a7ce: e000 b.n 800a7d2 break; 800a7d0: bf00 nop } } 800a7d2: bf00 nop 800a7d4: 3708 adds r7, #8 800a7d6: 46bd mov sp, r7 800a7d8: bd80 pop {r7, pc} 0800a7da : * @param req: usb request * @param pdata: setup data pointer * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 800a7da: b580 push {r7, lr} 800a7dc: b084 sub sp, #16 800a7de: af00 add r7, sp, #0 800a7e0: 6078 str r0, [r7, #4] 800a7e2: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 800a7e4: 683b ldr r3, [r7, #0] 800a7e6: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 800a7e8: 68fb ldr r3, [r7, #12] 800a7ea: 781a ldrb r2, [r3, #0] 800a7ec: 687b ldr r3, [r7, #4] 800a7ee: 701a strb r2, [r3, #0] pbuff++; 800a7f0: 68fb ldr r3, [r7, #12] 800a7f2: 3301 adds r3, #1 800a7f4: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 800a7f6: 68fb ldr r3, [r7, #12] 800a7f8: 781a ldrb r2, [r3, #0] 800a7fa: 687b ldr r3, [r7, #4] 800a7fc: 705a strb r2, [r3, #1] pbuff++; 800a7fe: 68fb ldr r3, [r7, #12] 800a800: 3301 adds r3, #1 800a802: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 800a804: 68f8 ldr r0, [r7, #12] 800a806: f7ff fa13 bl 8009c30 800a80a: 4603 mov r3, r0 800a80c: 461a mov r2, r3 800a80e: 687b ldr r3, [r7, #4] 800a810: 805a strh r2, [r3, #2] pbuff++; 800a812: 68fb ldr r3, [r7, #12] 800a814: 3301 adds r3, #1 800a816: 60fb str r3, [r7, #12] pbuff++; 800a818: 68fb ldr r3, [r7, #12] 800a81a: 3301 adds r3, #1 800a81c: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 800a81e: 68f8 ldr r0, [r7, #12] 800a820: f7ff fa06 bl 8009c30 800a824: 4603 mov r3, r0 800a826: 461a mov r2, r3 800a828: 687b ldr r3, [r7, #4] 800a82a: 809a strh r2, [r3, #4] pbuff++; 800a82c: 68fb ldr r3, [r7, #12] 800a82e: 3301 adds r3, #1 800a830: 60fb str r3, [r7, #12] pbuff++; 800a832: 68fb ldr r3, [r7, #12] 800a834: 3301 adds r3, #1 800a836: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 800a838: 68f8 ldr r0, [r7, #12] 800a83a: f7ff f9f9 bl 8009c30 800a83e: 4603 mov r3, r0 800a840: 461a mov r2, r3 800a842: 687b ldr r3, [r7, #4] 800a844: 80da strh r2, [r3, #6] } 800a846: bf00 nop 800a848: 3710 adds r7, #16 800a84a: 46bd mov sp, r7 800a84c: bd80 pop {r7, pc} 0800a84e : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800a84e: b580 push {r7, lr} 800a850: b082 sub sp, #8 800a852: af00 add r7, sp, #0 800a854: 6078 str r0, [r7, #4] 800a856: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 800a858: 2180 movs r1, #128 @ 0x80 800a85a: 6878 ldr r0, [r7, #4] 800a85c: f000 fc2a bl 800b0b4 (void)USBD_LL_StallEP(pdev, 0U); 800a860: 2100 movs r1, #0 800a862: 6878 ldr r0, [r7, #4] 800a864: f000 fc26 bl 800b0b4 } 800a868: bf00 nop 800a86a: 3708 adds r7, #8 800a86c: 46bd mov sp, r7 800a86e: bd80 pop {r7, pc} 0800a870 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 800a870: b580 push {r7, lr} 800a872: b086 sub sp, #24 800a874: af00 add r7, sp, #0 800a876: 60f8 str r0, [r7, #12] 800a878: 60b9 str r1, [r7, #8] 800a87a: 607a str r2, [r7, #4] uint8_t idx = 0U; 800a87c: 2300 movs r3, #0 800a87e: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 800a880: 68fb ldr r3, [r7, #12] 800a882: 2b00 cmp r3, #0 800a884: d042 beq.n 800a90c { return; } pdesc = desc; 800a886: 68fb ldr r3, [r7, #12] 800a888: 613b str r3, [r7, #16] *len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U); 800a88a: 6938 ldr r0, [r7, #16] 800a88c: f000 f842 bl 800a914 800a890: 4603 mov r3, r0 800a892: 3301 adds r3, #1 800a894: 005b lsls r3, r3, #1 800a896: f5b3 7f00 cmp.w r3, #512 @ 0x200 800a89a: d808 bhi.n 800a8ae 800a89c: 6938 ldr r0, [r7, #16] 800a89e: f000 f839 bl 800a914 800a8a2: 4603 mov r3, r0 800a8a4: 3301 adds r3, #1 800a8a6: b29b uxth r3, r3 800a8a8: 005b lsls r3, r3, #1 800a8aa: b29a uxth r2, r3 800a8ac: e001 b.n 800a8b2 800a8ae: f44f 7200 mov.w r2, #512 @ 0x200 800a8b2: 687b ldr r3, [r7, #4] 800a8b4: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 800a8b6: 7dfb ldrb r3, [r7, #23] 800a8b8: 68ba ldr r2, [r7, #8] 800a8ba: 4413 add r3, r2 800a8bc: 687a ldr r2, [r7, #4] 800a8be: 7812 ldrb r2, [r2, #0] 800a8c0: 701a strb r2, [r3, #0] idx++; 800a8c2: 7dfb ldrb r3, [r7, #23] 800a8c4: 3301 adds r3, #1 800a8c6: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 800a8c8: 7dfb ldrb r3, [r7, #23] 800a8ca: 68ba ldr r2, [r7, #8] 800a8cc: 4413 add r3, r2 800a8ce: 2203 movs r2, #3 800a8d0: 701a strb r2, [r3, #0] idx++; 800a8d2: 7dfb ldrb r3, [r7, #23] 800a8d4: 3301 adds r3, #1 800a8d6: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 800a8d8: e013 b.n 800a902 { unicode[idx] = *pdesc; 800a8da: 7dfb ldrb r3, [r7, #23] 800a8dc: 68ba ldr r2, [r7, #8] 800a8de: 4413 add r3, r2 800a8e0: 693a ldr r2, [r7, #16] 800a8e2: 7812 ldrb r2, [r2, #0] 800a8e4: 701a strb r2, [r3, #0] pdesc++; 800a8e6: 693b ldr r3, [r7, #16] 800a8e8: 3301 adds r3, #1 800a8ea: 613b str r3, [r7, #16] idx++; 800a8ec: 7dfb ldrb r3, [r7, #23] 800a8ee: 3301 adds r3, #1 800a8f0: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 800a8f2: 7dfb ldrb r3, [r7, #23] 800a8f4: 68ba ldr r2, [r7, #8] 800a8f6: 4413 add r3, r2 800a8f8: 2200 movs r2, #0 800a8fa: 701a strb r2, [r3, #0] idx++; 800a8fc: 7dfb ldrb r3, [r7, #23] 800a8fe: 3301 adds r3, #1 800a900: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 800a902: 693b ldr r3, [r7, #16] 800a904: 781b ldrb r3, [r3, #0] 800a906: 2b00 cmp r3, #0 800a908: d1e7 bne.n 800a8da 800a90a: e000 b.n 800a90e return; 800a90c: bf00 nop } } 800a90e: 3718 adds r7, #24 800a910: 46bd mov sp, r7 800a912: bd80 pop {r7, pc} 0800a914 : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 800a914: b480 push {r7} 800a916: b085 sub sp, #20 800a918: af00 add r7, sp, #0 800a91a: 6078 str r0, [r7, #4] uint8_t len = 0U; 800a91c: 2300 movs r3, #0 800a91e: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 800a920: 687b ldr r3, [r7, #4] 800a922: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 800a924: e005 b.n 800a932 { len++; 800a926: 7bfb ldrb r3, [r7, #15] 800a928: 3301 adds r3, #1 800a92a: 73fb strb r3, [r7, #15] pbuff++; 800a92c: 68bb ldr r3, [r7, #8] 800a92e: 3301 adds r3, #1 800a930: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 800a932: 68bb ldr r3, [r7, #8] 800a934: 781b ldrb r3, [r3, #0] 800a936: 2b00 cmp r3, #0 800a938: d1f5 bne.n 800a926 } return len; 800a93a: 7bfb ldrb r3, [r7, #15] } 800a93c: 4618 mov r0, r3 800a93e: 3714 adds r7, #20 800a940: 46bd mov sp, r7 800a942: f85d 7b04 ldr.w r7, [sp], #4 800a946: 4770 bx lr 0800a948 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a948: b580 push {r7, lr} 800a94a: b084 sub sp, #16 800a94c: af00 add r7, sp, #0 800a94e: 60f8 str r0, [r7, #12] 800a950: 60b9 str r1, [r7, #8] 800a952: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 800a954: 68fb ldr r3, [r7, #12] 800a956: 2202 movs r2, #2 800a958: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_in[0].total_length = len; 800a95c: 68fb ldr r3, [r7, #12] 800a95e: 687a ldr r2, [r7, #4] 800a960: 615a str r2, [r3, #20] pdev->ep_in[0].pbuffer = pbuf; 800a962: 68fb ldr r3, [r7, #12] 800a964: 68ba ldr r2, [r7, #8] 800a966: 625a str r2, [r3, #36] @ 0x24 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 800a968: 68fb ldr r3, [r7, #12] 800a96a: 687a ldr r2, [r7, #4] 800a96c: 619a str r2, [r3, #24] #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800a96e: 687b ldr r3, [r7, #4] 800a970: 68ba ldr r2, [r7, #8] 800a972: 2100 movs r1, #0 800a974: 68f8 ldr r0, [r7, #12] 800a976: f000 fc26 bl 800b1c6 return USBD_OK; 800a97a: 2300 movs r3, #0 } 800a97c: 4618 mov r0, r3 800a97e: 3710 adds r7, #16 800a980: 46bd mov sp, r7 800a982: bd80 pop {r7, pc} 0800a984 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a984: b580 push {r7, lr} 800a986: b084 sub sp, #16 800a988: af00 add r7, sp, #0 800a98a: 60f8 str r0, [r7, #12] 800a98c: 60b9 str r1, [r7, #8] 800a98e: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 800a990: 687b ldr r3, [r7, #4] 800a992: 68ba ldr r2, [r7, #8] 800a994: 2100 movs r1, #0 800a996: 68f8 ldr r0, [r7, #12] 800a998: f000 fc15 bl 800b1c6 return USBD_OK; 800a99c: 2300 movs r3, #0 } 800a99e: 4618 mov r0, r3 800a9a0: 3710 adds r7, #16 800a9a2: 46bd mov sp, r7 800a9a4: bd80 pop {r7, pc} 0800a9a6 : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800a9a6: b580 push {r7, lr} 800a9a8: b084 sub sp, #16 800a9aa: af00 add r7, sp, #0 800a9ac: 60f8 str r0, [r7, #12] 800a9ae: 60b9 str r1, [r7, #8] 800a9b0: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 800a9b2: 687b ldr r3, [r7, #4] 800a9b4: 68ba ldr r2, [r7, #8] 800a9b6: 2100 movs r1, #0 800a9b8: 68f8 ldr r0, [r7, #12] 800a9ba: f000 fc25 bl 800b208 return USBD_OK; 800a9be: 2300 movs r3, #0 } 800a9c0: 4618 mov r0, r3 800a9c2: 3710 adds r7, #16 800a9c4: 46bd mov sp, r7 800a9c6: bd80 pop {r7, pc} 0800a9c8 : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 800a9c8: b580 push {r7, lr} 800a9ca: b082 sub sp, #8 800a9cc: af00 add r7, sp, #0 800a9ce: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 800a9d0: 687b ldr r3, [r7, #4] 800a9d2: 2204 movs r2, #4 800a9d4: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 800a9d8: 2300 movs r3, #0 800a9da: 2200 movs r2, #0 800a9dc: 2100 movs r1, #0 800a9de: 6878 ldr r0, [r7, #4] 800a9e0: f000 fbf1 bl 800b1c6 return USBD_OK; 800a9e4: 2300 movs r3, #0 } 800a9e6: 4618 mov r0, r3 800a9e8: 3708 adds r7, #8 800a9ea: 46bd mov sp, r7 800a9ec: bd80 pop {r7, pc} 0800a9ee : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 800a9ee: b580 push {r7, lr} 800a9f0: b082 sub sp, #8 800a9f2: af00 add r7, sp, #0 800a9f4: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 800a9f6: 687b ldr r3, [r7, #4] 800a9f8: 2205 movs r2, #5 800a9fa: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 800a9fe: 2300 movs r3, #0 800aa00: 2200 movs r2, #0 800aa02: 2100 movs r1, #0 800aa04: 6878 ldr r0, [r7, #4] 800aa06: f000 fbff bl 800b208 return USBD_OK; 800aa0a: 2300 movs r3, #0 } 800aa0c: 4618 mov r0, r3 800aa0e: 3708 adds r7, #8 800aa10: 46bd mov sp, r7 800aa12: bd80 pop {r7, pc} 0800aa14 : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 800aa14: b580 push {r7, lr} 800aa16: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) 800aa18: 2200 movs r2, #0 800aa1a: 490e ldr r1, [pc, #56] @ (800aa54 ) 800aa1c: 480e ldr r0, [pc, #56] @ (800aa58 ) 800aa1e: f7fe fcd1 bl 80093c4 800aa22: 4603 mov r3, r0 800aa24: 2b00 cmp r3, #0 800aa26: d001 beq.n 800aa2c { Error_Handler(); 800aa28: f7f6 fc1e bl 8001268 } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) 800aa2c: 490b ldr r1, [pc, #44] @ (800aa5c ) 800aa2e: 480a ldr r0, [pc, #40] @ (800aa58 ) 800aa30: f7fe fcf8 bl 8009424 800aa34: 4603 mov r3, r0 800aa36: 2b00 cmp r3, #0 800aa38: d001 beq.n 800aa3e { Error_Handler(); 800aa3a: f7f6 fc15 bl 8001268 } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) 800aa3e: 4806 ldr r0, [pc, #24] @ (800aa58 ) 800aa40: f7fe fd26 bl 8009490 800aa44: 4603 mov r3, r0 800aa46: 2b00 cmp r3, #0 800aa48: d001 beq.n 800aa4e { Error_Handler(); 800aa4a: f7f6 fc0d bl 8001268 } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 800aa4e: bf00 nop 800aa50: bd80 pop {r7, pc} 800aa52: bf00 nop 800aa54: 200001b4 .word 0x200001b4 800aa58: 20000e28 .word 0x20000e28 800aa5c: 20000110 .word 0x20000110 0800aa60 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800aa60: b480 push {r7} 800aa62: b083 sub sp, #12 800aa64: af00 add r7, sp, #0 800aa66: 4603 mov r3, r0 800aa68: 6039 str r1, [r7, #0] 800aa6a: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_DeviceDesc); 800aa6c: 683b ldr r3, [r7, #0] 800aa6e: 2212 movs r2, #18 800aa70: 801a strh r2, [r3, #0] return USBD_FS_DeviceDesc; 800aa72: 4b03 ldr r3, [pc, #12] @ (800aa80 ) } 800aa74: 4618 mov r0, r3 800aa76: 370c adds r7, #12 800aa78: 46bd mov sp, r7 800aa7a: f85d 7b04 ldr.w r7, [sp], #4 800aa7e: 4770 bx lr 800aa80: 200001d4 .word 0x200001d4 0800aa84 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800aa84: b480 push {r7} 800aa86: b083 sub sp, #12 800aa88: af00 add r7, sp, #0 800aa8a: 4603 mov r3, r0 800aa8c: 6039 str r1, [r7, #0] 800aa8e: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 800aa90: 683b ldr r3, [r7, #0] 800aa92: 2204 movs r2, #4 800aa94: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 800aa96: 4b03 ldr r3, [pc, #12] @ (800aaa4 ) } 800aa98: 4618 mov r0, r3 800aa9a: 370c adds r7, #12 800aa9c: 46bd mov sp, r7 800aa9e: f85d 7b04 ldr.w r7, [sp], #4 800aaa2: 4770 bx lr 800aaa4: 200001f4 .word 0x200001f4 0800aaa8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800aaa8: b580 push {r7, lr} 800aaaa: b082 sub sp, #8 800aaac: af00 add r7, sp, #0 800aaae: 4603 mov r3, r0 800aab0: 6039 str r1, [r7, #0] 800aab2: 71fb strb r3, [r7, #7] if(speed == 0) 800aab4: 79fb ldrb r3, [r7, #7] 800aab6: 2b00 cmp r3, #0 800aab8: d105 bne.n 800aac6 { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800aaba: 683a ldr r2, [r7, #0] 800aabc: 4907 ldr r1, [pc, #28] @ (800aadc ) 800aabe: 4808 ldr r0, [pc, #32] @ (800aae0 ) 800aac0: f7ff fed6 bl 800a870 800aac4: e004 b.n 800aad0 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800aac6: 683a ldr r2, [r7, #0] 800aac8: 4904 ldr r1, [pc, #16] @ (800aadc ) 800aaca: 4805 ldr r0, [pc, #20] @ (800aae0 ) 800aacc: f7ff fed0 bl 800a870 } return USBD_StrDesc; 800aad0: 4b02 ldr r3, [pc, #8] @ (800aadc ) } 800aad2: 4618 mov r0, r3 800aad4: 3708 adds r7, #8 800aad6: 46bd mov sp, r7 800aad8: bd80 pop {r7, pc} 800aada: bf00 nop 800aadc: 20001104 .word 0x20001104 800aae0: 0800b3fc .word 0x0800b3fc 0800aae4 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800aae4: b580 push {r7, lr} 800aae6: b082 sub sp, #8 800aae8: af00 add r7, sp, #0 800aaea: 4603 mov r3, r0 800aaec: 6039 str r1, [r7, #0] 800aaee: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 800aaf0: 683a ldr r2, [r7, #0] 800aaf2: 4904 ldr r1, [pc, #16] @ (800ab04 ) 800aaf4: 4804 ldr r0, [pc, #16] @ (800ab08 ) 800aaf6: f7ff febb bl 800a870 return USBD_StrDesc; 800aafa: 4b02 ldr r3, [pc, #8] @ (800ab04 ) } 800aafc: 4618 mov r0, r3 800aafe: 3708 adds r7, #8 800ab00: 46bd mov sp, r7 800ab02: bd80 pop {r7, pc} 800ab04: 20001104 .word 0x20001104 800ab08: 0800b410 .word 0x0800b410 0800ab0c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800ab0c: b580 push {r7, lr} 800ab0e: b082 sub sp, #8 800ab10: af00 add r7, sp, #0 800ab12: 4603 mov r3, r0 800ab14: 6039 str r1, [r7, #0] 800ab16: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 800ab18: 683b ldr r3, [r7, #0] 800ab1a: 221a movs r2, #26 800ab1c: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 800ab1e: f000 f855 bl 800abcc /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ /* USER CODE END USBD_FS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 800ab22: 4b02 ldr r3, [pc, #8] @ (800ab2c ) } 800ab24: 4618 mov r0, r3 800ab26: 3708 adds r7, #8 800ab28: 46bd mov sp, r7 800ab2a: bd80 pop {r7, pc} 800ab2c: 200001f8 .word 0x200001f8 0800ab30 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800ab30: b580 push {r7, lr} 800ab32: b082 sub sp, #8 800ab34: af00 add r7, sp, #0 800ab36: 4603 mov r3, r0 800ab38: 6039 str r1, [r7, #0] 800ab3a: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 800ab3c: 79fb ldrb r3, [r7, #7] 800ab3e: 2b00 cmp r3, #0 800ab40: d105 bne.n 800ab4e { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800ab42: 683a ldr r2, [r7, #0] 800ab44: 4907 ldr r1, [pc, #28] @ (800ab64 ) 800ab46: 4808 ldr r0, [pc, #32] @ (800ab68 ) 800ab48: f7ff fe92 bl 800a870 800ab4c: e004 b.n 800ab58 } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 800ab4e: 683a ldr r2, [r7, #0] 800ab50: 4904 ldr r1, [pc, #16] @ (800ab64 ) 800ab52: 4805 ldr r0, [pc, #20] @ (800ab68 ) 800ab54: f7ff fe8c bl 800a870 } return USBD_StrDesc; 800ab58: 4b02 ldr r3, [pc, #8] @ (800ab64 ) } 800ab5a: 4618 mov r0, r3 800ab5c: 3708 adds r7, #8 800ab5e: 46bd mov sp, r7 800ab60: bd80 pop {r7, pc} 800ab62: bf00 nop 800ab64: 20001104 .word 0x20001104 800ab68: 0800b41c .word 0x0800b41c 0800ab6c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800ab6c: b580 push {r7, lr} 800ab6e: b082 sub sp, #8 800ab70: af00 add r7, sp, #0 800ab72: 4603 mov r3, r0 800ab74: 6039 str r1, [r7, #0] 800ab76: 71fb strb r3, [r7, #7] if(speed == 0) 800ab78: 79fb ldrb r3, [r7, #7] 800ab7a: 2b00 cmp r3, #0 800ab7c: d105 bne.n 800ab8a { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800ab7e: 683a ldr r2, [r7, #0] 800ab80: 4907 ldr r1, [pc, #28] @ (800aba0 ) 800ab82: 4808 ldr r0, [pc, #32] @ (800aba4 ) 800ab84: f7ff fe74 bl 800a870 800ab88: e004 b.n 800ab94 } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 800ab8a: 683a ldr r2, [r7, #0] 800ab8c: 4904 ldr r1, [pc, #16] @ (800aba0 ) 800ab8e: 4805 ldr r0, [pc, #20] @ (800aba4 ) 800ab90: f7ff fe6e bl 800a870 } return USBD_StrDesc; 800ab94: 4b02 ldr r3, [pc, #8] @ (800aba0 ) } 800ab96: 4618 mov r0, r3 800ab98: 3708 adds r7, #8 800ab9a: 46bd mov sp, r7 800ab9c: bd80 pop {r7, pc} 800ab9e: bf00 nop 800aba0: 20001104 .word 0x20001104 800aba4: 0800b428 .word 0x0800b428 0800aba8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 800aba8: b480 push {r7} 800abaa: b083 sub sp, #12 800abac: af00 add r7, sp, #0 800abae: 4603 mov r3, r0 800abb0: 6039 str r1, [r7, #0] 800abb2: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_BOSDesc); 800abb4: 683b ldr r3, [r7, #0] 800abb6: 220c movs r2, #12 800abb8: 801a strh r2, [r3, #0] return (uint8_t*)USBD_FS_BOSDesc; 800abba: 4b03 ldr r3, [pc, #12] @ (800abc8 ) } 800abbc: 4618 mov r0, r3 800abbe: 370c adds r7, #12 800abc0: 46bd mov sp, r7 800abc2: f85d 7b04 ldr.w r7, [sp], #4 800abc6: 4770 bx lr 800abc8: 200001e8 .word 0x200001e8 0800abcc : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 800abcc: b580 push {r7, lr} 800abce: b084 sub sp, #16 800abd0: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 800abd2: 4b0f ldr r3, [pc, #60] @ (800ac10 ) 800abd4: 681b ldr r3, [r3, #0] 800abd6: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 800abd8: 4b0e ldr r3, [pc, #56] @ (800ac14 ) 800abda: 681b ldr r3, [r3, #0] 800abdc: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 800abde: 4b0e ldr r3, [pc, #56] @ (800ac18 ) 800abe0: 681b ldr r3, [r3, #0] 800abe2: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 800abe4: 68fa ldr r2, [r7, #12] 800abe6: 687b ldr r3, [r7, #4] 800abe8: 4413 add r3, r2 800abea: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 800abec: 68fb ldr r3, [r7, #12] 800abee: 2b00 cmp r3, #0 800abf0: d009 beq.n 800ac06 { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 800abf2: 2208 movs r2, #8 800abf4: 4909 ldr r1, [pc, #36] @ (800ac1c ) 800abf6: 68f8 ldr r0, [r7, #12] 800abf8: f000 f814 bl 800ac24 IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 800abfc: 2204 movs r2, #4 800abfe: 4908 ldr r1, [pc, #32] @ (800ac20 ) 800ac00: 68b8 ldr r0, [r7, #8] 800ac02: f000 f80f bl 800ac24 } } 800ac06: bf00 nop 800ac08: 3710 adds r7, #16 800ac0a: 46bd mov sp, r7 800ac0c: bd80 pop {r7, pc} 800ac0e: bf00 nop 800ac10: 1fff7a10 .word 0x1fff7a10 800ac14: 1fff7a14 .word 0x1fff7a14 800ac18: 1fff7a18 .word 0x1fff7a18 800ac1c: 200001fa .word 0x200001fa 800ac20: 2000020a .word 0x2000020a 0800ac24 : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 800ac24: b480 push {r7} 800ac26: b087 sub sp, #28 800ac28: af00 add r7, sp, #0 800ac2a: 60f8 str r0, [r7, #12] 800ac2c: 60b9 str r1, [r7, #8] 800ac2e: 4613 mov r3, r2 800ac30: 71fb strb r3, [r7, #7] uint8_t idx = 0; 800ac32: 2300 movs r3, #0 800ac34: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 800ac36: 2300 movs r3, #0 800ac38: 75fb strb r3, [r7, #23] 800ac3a: e027 b.n 800ac8c { if (((value >> 28)) < 0xA) 800ac3c: 68fb ldr r3, [r7, #12] 800ac3e: 0f1b lsrs r3, r3, #28 800ac40: 2b09 cmp r3, #9 800ac42: d80b bhi.n 800ac5c { pbuf[2 * idx] = (value >> 28) + '0'; 800ac44: 68fb ldr r3, [r7, #12] 800ac46: 0f1b lsrs r3, r3, #28 800ac48: b2da uxtb r2, r3 800ac4a: 7dfb ldrb r3, [r7, #23] 800ac4c: 005b lsls r3, r3, #1 800ac4e: 4619 mov r1, r3 800ac50: 68bb ldr r3, [r7, #8] 800ac52: 440b add r3, r1 800ac54: 3230 adds r2, #48 @ 0x30 800ac56: b2d2 uxtb r2, r2 800ac58: 701a strb r2, [r3, #0] 800ac5a: e00a b.n 800ac72 } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 800ac5c: 68fb ldr r3, [r7, #12] 800ac5e: 0f1b lsrs r3, r3, #28 800ac60: b2da uxtb r2, r3 800ac62: 7dfb ldrb r3, [r7, #23] 800ac64: 005b lsls r3, r3, #1 800ac66: 4619 mov r1, r3 800ac68: 68bb ldr r3, [r7, #8] 800ac6a: 440b add r3, r1 800ac6c: 3237 adds r2, #55 @ 0x37 800ac6e: b2d2 uxtb r2, r2 800ac70: 701a strb r2, [r3, #0] } value = value << 4; 800ac72: 68fb ldr r3, [r7, #12] 800ac74: 011b lsls r3, r3, #4 800ac76: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 800ac78: 7dfb ldrb r3, [r7, #23] 800ac7a: 005b lsls r3, r3, #1 800ac7c: 3301 adds r3, #1 800ac7e: 68ba ldr r2, [r7, #8] 800ac80: 4413 add r3, r2 800ac82: 2200 movs r2, #0 800ac84: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 800ac86: 7dfb ldrb r3, [r7, #23] 800ac88: 3301 adds r3, #1 800ac8a: 75fb strb r3, [r7, #23] 800ac8c: 7dfa ldrb r2, [r7, #23] 800ac8e: 79fb ldrb r3, [r7, #7] 800ac90: 429a cmp r2, r3 800ac92: d3d3 bcc.n 800ac3c } } 800ac94: bf00 nop 800ac96: bf00 nop 800ac98: 371c adds r7, #28 800ac9a: 46bd mov sp, r7 800ac9c: f85d 7b04 ldr.w r7, [sp], #4 800aca0: 4770 bx lr ... 0800aca4 : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 800aca4: b580 push {r7, lr} 800aca6: b0a0 sub sp, #128 @ 0x80 800aca8: af00 add r7, sp, #0 800acaa: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800acac: f107 036c add.w r3, r7, #108 @ 0x6c 800acb0: 2200 movs r2, #0 800acb2: 601a str r2, [r3, #0] 800acb4: 605a str r2, [r3, #4] 800acb6: 609a str r2, [r3, #8] 800acb8: 60da str r2, [r3, #12] 800acba: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 800acbc: f107 0310 add.w r3, r7, #16 800acc0: 225c movs r2, #92 @ 0x5c 800acc2: 2100 movs r1, #0 800acc4: 4618 mov r0, r3 800acc6: f000 fb53 bl 800b370 if(pcdHandle->Instance==USB_OTG_FS) 800acca: 687b ldr r3, [r7, #4] 800accc: 681b ldr r3, [r3, #0] 800acce: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800acd2: d149 bne.n 800ad68 /* USER CODE END USB_OTG_FS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; 800acd4: f44f 7380 mov.w r3, #256 @ 0x100 800acd8: 613b str r3, [r7, #16] PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ; 800acda: 2300 movs r3, #0 800acdc: 667b str r3, [r7, #100] @ 0x64 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800acde: f107 0310 add.w r3, r7, #16 800ace2: 4618 mov r0, r3 800ace4: f7f9 fd1e bl 8004724 800ace8: 4603 mov r3, r0 800acea: 2b00 cmp r3, #0 800acec: d001 beq.n 800acf2 { Error_Handler(); 800acee: f7f6 fabb bl 8001268 } __HAL_RCC_GPIOA_CLK_ENABLE(); 800acf2: 2300 movs r3, #0 800acf4: 60fb str r3, [r7, #12] 800acf6: 4b1e ldr r3, [pc, #120] @ (800ad70 ) 800acf8: 6b1b ldr r3, [r3, #48] @ 0x30 800acfa: 4a1d ldr r2, [pc, #116] @ (800ad70 ) 800acfc: f043 0301 orr.w r3, r3, #1 800ad00: 6313 str r3, [r2, #48] @ 0x30 800ad02: 4b1b ldr r3, [pc, #108] @ (800ad70 ) 800ad04: 6b1b ldr r3, [r3, #48] @ 0x30 800ad06: f003 0301 and.w r3, r3, #1 800ad0a: 60fb str r3, [r7, #12] 800ad0c: 68fb ldr r3, [r7, #12] /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 800ad0e: f44f 53c0 mov.w r3, #6144 @ 0x1800 800ad12: 66fb str r3, [r7, #108] @ 0x6c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800ad14: 2302 movs r3, #2 800ad16: 673b str r3, [r7, #112] @ 0x70 GPIO_InitStruct.Pull = GPIO_NOPULL; 800ad18: 2300 movs r3, #0 800ad1a: 677b str r3, [r7, #116] @ 0x74 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800ad1c: 2303 movs r3, #3 800ad1e: 67bb str r3, [r7, #120] @ 0x78 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 800ad20: 230a movs r3, #10 800ad22: 67fb str r3, [r7, #124] @ 0x7c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800ad24: f107 036c add.w r3, r7, #108 @ 0x6c 800ad28: 4619 mov r1, r3 800ad2a: 4812 ldr r0, [pc, #72] @ (800ad74 ) 800ad2c: f7f7 fe50 bl 80029d0 /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 800ad30: 4b0f ldr r3, [pc, #60] @ (800ad70 ) 800ad32: 6b5b ldr r3, [r3, #52] @ 0x34 800ad34: 4a0e ldr r2, [pc, #56] @ (800ad70 ) 800ad36: f043 0380 orr.w r3, r3, #128 @ 0x80 800ad3a: 6353 str r3, [r2, #52] @ 0x34 800ad3c: 2300 movs r3, #0 800ad3e: 60bb str r3, [r7, #8] 800ad40: 4b0b ldr r3, [pc, #44] @ (800ad70 ) 800ad42: 6c5b ldr r3, [r3, #68] @ 0x44 800ad44: 4a0a ldr r2, [pc, #40] @ (800ad70 ) 800ad46: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800ad4a: 6453 str r3, [r2, #68] @ 0x44 800ad4c: 4b08 ldr r3, [pc, #32] @ (800ad70 ) 800ad4e: 6c5b ldr r3, [r3, #68] @ 0x44 800ad50: f403 4380 and.w r3, r3, #16384 @ 0x4000 800ad54: 60bb str r3, [r7, #8] 800ad56: 68bb ldr r3, [r7, #8] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); 800ad58: 2200 movs r2, #0 800ad5a: 2100 movs r1, #0 800ad5c: 2043 movs r0, #67 @ 0x43 800ad5e: f7f7 f9fe bl 800215e HAL_NVIC_EnableIRQ(OTG_FS_IRQn); 800ad62: 2043 movs r0, #67 @ 0x43 800ad64: f7f7 fa17 bl 8002196 /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 800ad68: bf00 nop 800ad6a: 3780 adds r7, #128 @ 0x80 800ad6c: 46bd mov sp, r7 800ad6e: bd80 pop {r7, pc} 800ad70: 40023800 .word 0x40023800 800ad74: 40020000 .word 0x40020000 0800ad78 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800ad78: b580 push {r7, lr} 800ad7a: b082 sub sp, #8 800ad7c: af00 add r7, sp, #0 800ad7e: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 800ad80: 687b ldr r3, [r7, #4] 800ad82: f8d3 24e0 ldr.w r2, [r3, #1248] @ 0x4e0 800ad86: 687b ldr r3, [r7, #4] 800ad88: f203 439c addw r3, r3, #1180 @ 0x49c 800ad8c: 4619 mov r1, r3 800ad8e: 4610 mov r0, r2 800ad90: f7fe fbcb bl 800952a } 800ad94: bf00 nop 800ad96: 3708 adds r7, #8 800ad98: 46bd mov sp, r7 800ad9a: bd80 pop {r7, pc} 0800ad9c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800ad9c: b580 push {r7, lr} 800ad9e: b082 sub sp, #8 800ada0: af00 add r7, sp, #0 800ada2: 6078 str r0, [r7, #4] 800ada4: 460b mov r3, r1 800ada6: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 800ada8: 687b ldr r3, [r7, #4] 800adaa: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800adae: 78fa ldrb r2, [r7, #3] 800adb0: 6879 ldr r1, [r7, #4] 800adb2: 4613 mov r3, r2 800adb4: 00db lsls r3, r3, #3 800adb6: 4413 add r3, r2 800adb8: 009b lsls r3, r3, #2 800adba: 440b add r3, r1 800adbc: f503 7318 add.w r3, r3, #608 @ 0x260 800adc0: 681a ldr r2, [r3, #0] 800adc2: 78fb ldrb r3, [r7, #3] 800adc4: 4619 mov r1, r3 800adc6: f7fe fc05 bl 80095d4 } 800adca: bf00 nop 800adcc: 3708 adds r7, #8 800adce: 46bd mov sp, r7 800add0: bd80 pop {r7, pc} 0800add2 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800add2: b580 push {r7, lr} 800add4: b082 sub sp, #8 800add6: af00 add r7, sp, #0 800add8: 6078 str r0, [r7, #4] 800adda: 460b mov r3, r1 800addc: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 800adde: 687b ldr r3, [r7, #4] 800ade0: f8d3 04e0 ldr.w r0, [r3, #1248] @ 0x4e0 800ade4: 78fa ldrb r2, [r7, #3] 800ade6: 6879 ldr r1, [r7, #4] 800ade8: 4613 mov r3, r2 800adea: 00db lsls r3, r3, #3 800adec: 4413 add r3, r2 800adee: 009b lsls r3, r3, #2 800adf0: 440b add r3, r1 800adf2: 3320 adds r3, #32 800adf4: 681a ldr r2, [r3, #0] 800adf6: 78fb ldrb r3, [r7, #3] 800adf8: 4619 mov r1, r3 800adfa: f7fe fca7 bl 800974c } 800adfe: bf00 nop 800ae00: 3708 adds r7, #8 800ae02: 46bd mov sp, r7 800ae04: bd80 pop {r7, pc} 0800ae06 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800ae06: b580 push {r7, lr} 800ae08: b082 sub sp, #8 800ae0a: af00 add r7, sp, #0 800ae0c: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 800ae0e: 687b ldr r3, [r7, #4] 800ae10: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800ae14: 4618 mov r0, r3 800ae16: f7fe fdeb bl 80099f0 } 800ae1a: bf00 nop 800ae1c: 3708 adds r7, #8 800ae1e: 46bd mov sp, r7 800ae20: bd80 pop {r7, pc} 0800ae22 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800ae22: b580 push {r7, lr} 800ae24: b084 sub sp, #16 800ae26: af00 add r7, sp, #0 800ae28: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 800ae2a: 2301 movs r3, #1 800ae2c: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed == PCD_SPEED_HIGH) 800ae2e: 687b ldr r3, [r7, #4] 800ae30: 79db ldrb r3, [r3, #7] 800ae32: 2b00 cmp r3, #0 800ae34: d102 bne.n 800ae3c { speed = USBD_SPEED_HIGH; 800ae36: 2300 movs r3, #0 800ae38: 73fb strb r3, [r7, #15] 800ae3a: e008 b.n 800ae4e } else if ( hpcd->Init.speed == PCD_SPEED_FULL) 800ae3c: 687b ldr r3, [r7, #4] 800ae3e: 79db ldrb r3, [r3, #7] 800ae40: 2b02 cmp r3, #2 800ae42: d102 bne.n 800ae4a { speed = USBD_SPEED_FULL; 800ae44: 2301 movs r3, #1 800ae46: 73fb strb r3, [r7, #15] 800ae48: e001 b.n 800ae4e } else { Error_Handler(); 800ae4a: f7f6 fa0d bl 8001268 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 800ae4e: 687b ldr r3, [r7, #4] 800ae50: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800ae54: 7bfa ldrb r2, [r7, #15] 800ae56: 4611 mov r1, r2 800ae58: 4618 mov r0, r3 800ae5a: f7fe fd85 bl 8009968 /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 800ae5e: 687b ldr r3, [r7, #4] 800ae60: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800ae64: 4618 mov r0, r3 800ae66: f7fe fd2c bl 80098c2 } 800ae6a: bf00 nop 800ae6c: 3710 adds r7, #16 800ae6e: 46bd mov sp, r7 800ae70: bd80 pop {r7, pc} ... 0800ae74 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800ae74: b580 push {r7, lr} 800ae76: b082 sub sp, #8 800ae78: af00 add r7, sp, #0 800ae7a: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 800ae7c: 687b ldr r3, [r7, #4] 800ae7e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800ae82: 4618 mov r0, r3 800ae84: f7fe fd80 bl 8009988 __HAL_PCD_GATE_PHYCLOCK(hpcd); 800ae88: 687b ldr r3, [r7, #4] 800ae8a: 681b ldr r3, [r3, #0] 800ae8c: f503 6360 add.w r3, r3, #3584 @ 0xe00 800ae90: 681b ldr r3, [r3, #0] 800ae92: 687a ldr r2, [r7, #4] 800ae94: 6812 ldr r2, [r2, #0] 800ae96: f502 6260 add.w r2, r2, #3584 @ 0xe00 800ae9a: f043 0301 orr.w r3, r3, #1 800ae9e: 6013 str r3, [r2, #0] /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 800aea0: 687b ldr r3, [r7, #4] 800aea2: 7adb ldrb r3, [r3, #11] 800aea4: 2b00 cmp r3, #0 800aea6: d005 beq.n 800aeb4 { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800aea8: 4b04 ldr r3, [pc, #16] @ (800aebc ) 800aeaa: 691b ldr r3, [r3, #16] 800aeac: 4a03 ldr r2, [pc, #12] @ (800aebc ) 800aeae: f043 0306 orr.w r3, r3, #6 800aeb2: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 800aeb4: bf00 nop 800aeb6: 3708 adds r7, #8 800aeb8: 46bd mov sp, r7 800aeba: bd80 pop {r7, pc} 800aebc: e000ed00 .word 0xe000ed00 0800aec0 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800aec0: b580 push {r7, lr} 800aec2: b082 sub sp, #8 800aec4: af00 add r7, sp, #0 800aec6: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 800aec8: 687b ldr r3, [r7, #4] 800aeca: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800aece: 4618 mov r0, r3 800aed0: f7fe fd76 bl 80099c0 } 800aed4: bf00 nop 800aed6: 3708 adds r7, #8 800aed8: 46bd mov sp, r7 800aeda: bd80 pop {r7, pc} 0800aedc : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800aedc: b580 push {r7, lr} 800aede: b082 sub sp, #8 800aee0: af00 add r7, sp, #0 800aee2: 6078 str r0, [r7, #4] 800aee4: 460b mov r3, r1 800aee6: 70fb strb r3, [r7, #3] USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800aee8: 687b ldr r3, [r7, #4] 800aeea: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800aeee: 78fa ldrb r2, [r7, #3] 800aef0: 4611 mov r1, r2 800aef2: 4618 mov r0, r3 800aef4: f7fe fdce bl 8009a94 } 800aef8: bf00 nop 800aefa: 3708 adds r7, #8 800aefc: 46bd mov sp, r7 800aefe: bd80 pop {r7, pc} 0800af00 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800af00: b580 push {r7, lr} 800af02: b082 sub sp, #8 800af04: af00 add r7, sp, #0 800af06: 6078 str r0, [r7, #4] 800af08: 460b mov r3, r1 800af0a: 70fb strb r3, [r7, #3] USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 800af0c: 687b ldr r3, [r7, #4] 800af0e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800af12: 78fa ldrb r2, [r7, #3] 800af14: 4611 mov r1, r2 800af16: 4618 mov r0, r3 800af18: f7fe fd8a bl 8009a30 } 800af1c: bf00 nop 800af1e: 3708 adds r7, #8 800af20: 46bd mov sp, r7 800af22: bd80 pop {r7, pc} 0800af24 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800af24: b580 push {r7, lr} 800af26: b082 sub sp, #8 800af28: af00 add r7, sp, #0 800af2a: 6078 str r0, [r7, #4] USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); 800af2c: 687b ldr r3, [r7, #4] 800af2e: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800af32: 4618 mov r0, r3 800af34: f7fe fde0 bl 8009af8 } 800af38: bf00 nop 800af3a: 3708 adds r7, #8 800af3c: 46bd mov sp, r7 800af3e: bd80 pop {r7, pc} 0800af40 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800af40: b580 push {r7, lr} 800af42: b082 sub sp, #8 800af44: af00 add r7, sp, #0 800af46: 6078 str r0, [r7, #4] USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); 800af48: 687b ldr r3, [r7, #4] 800af4a: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800af4e: 4618 mov r0, r3 800af50: f7fe fddd bl 8009b0e } 800af54: bf00 nop 800af56: 3708 adds r7, #8 800af58: 46bd mov sp, r7 800af5a: bd80 pop {r7, pc} 0800af5c : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 800af5c: b580 push {r7, lr} 800af5e: b082 sub sp, #8 800af60: af00 add r7, sp, #0 800af62: 6078 str r0, [r7, #4] /* Init USB Ip. */ if (pdev->id == DEVICE_FS) { 800af64: 687b ldr r3, [r7, #4] 800af66: 781b ldrb r3, [r3, #0] 800af68: 2b00 cmp r3, #0 800af6a: d13c bne.n 800afe6 /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; 800af6c: 4a20 ldr r2, [pc, #128] @ (800aff0 ) 800af6e: 687b ldr r3, [r7, #4] 800af70: f8c2 34e0 str.w r3, [r2, #1248] @ 0x4e0 pdev->pData = &hpcd_USB_OTG_FS; 800af74: 687b ldr r3, [r7, #4] 800af76: 4a1e ldr r2, [pc, #120] @ (800aff0 ) 800af78: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8 hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 800af7c: 4b1c ldr r3, [pc, #112] @ (800aff0 ) 800af7e: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 800af82: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 6; 800af84: 4b1a ldr r3, [pc, #104] @ (800aff0 ) 800af86: 2206 movs r2, #6 800af88: 711a strb r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 800af8a: 4b19 ldr r3, [pc, #100] @ (800aff0 ) 800af8c: 2202 movs r2, #2 800af8e: 71da strb r2, [r3, #7] hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; 800af90: 4b17 ldr r3, [pc, #92] @ (800aff0 ) 800af92: 2200 movs r2, #0 800af94: 719a strb r2, [r3, #6] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 800af96: 4b16 ldr r3, [pc, #88] @ (800aff0 ) 800af98: 2202 movs r2, #2 800af9a: 725a strb r2, [r3, #9] hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; 800af9c: 4b14 ldr r3, [pc, #80] @ (800aff0 ) 800af9e: 2200 movs r2, #0 800afa0: 729a strb r2, [r3, #10] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 800afa2: 4b13 ldr r3, [pc, #76] @ (800aff0 ) 800afa4: 2200 movs r2, #0 800afa6: 72da strb r2, [r3, #11] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 800afa8: 4b11 ldr r3, [pc, #68] @ (800aff0 ) 800afaa: 2200 movs r2, #0 800afac: 731a strb r2, [r3, #12] hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; 800afae: 4b10 ldr r3, [pc, #64] @ (800aff0 ) 800afb0: 2200 movs r2, #0 800afb2: 739a strb r2, [r3, #14] hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 800afb4: 4b0e ldr r3, [pc, #56] @ (800aff0 ) 800afb6: 2200 movs r2, #0 800afb8: 73da strb r2, [r3, #15] if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 800afba: 480d ldr r0, [pc, #52] @ (800aff0 ) 800afbc: f7f8 f812 bl 8002fe4 800afc0: 4603 mov r3, r0 800afc2: 2b00 cmp r3, #0 800afc4: d001 beq.n 800afca { Error_Handler( ); 800afc6: f7f6 f94f bl 8001268 HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback); HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); 800afca: 2180 movs r1, #128 @ 0x80 800afcc: 4808 ldr r0, [pc, #32] @ (800aff0 ) 800afce: f7f9 fa5a bl 8004486 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); 800afd2: 2240 movs r2, #64 @ 0x40 800afd4: 2100 movs r1, #0 800afd6: 4806 ldr r0, [pc, #24] @ (800aff0 ) 800afd8: f7f9 fa0e bl 80043f8 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); 800afdc: 2280 movs r2, #128 @ 0x80 800afde: 2101 movs r1, #1 800afe0: 4803 ldr r0, [pc, #12] @ (800aff0 ) 800afe2: f7f9 fa09 bl 80043f8 } return USBD_OK; 800afe6: 2300 movs r3, #0 } 800afe8: 4618 mov r0, r3 800afea: 3708 adds r7, #8 800afec: 46bd mov sp, r7 800afee: bd80 pop {r7, pc} 800aff0: 20001304 .word 0x20001304 0800aff4 : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 800aff4: b580 push {r7, lr} 800aff6: b084 sub sp, #16 800aff8: af00 add r7, sp, #0 800affa: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 800affc: 2300 movs r3, #0 800affe: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b000: 2300 movs r3, #0 800b002: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 800b004: 687b ldr r3, [r7, #4] 800b006: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b00a: 4618 mov r0, r3 800b00c: f7f8 f900 bl 8003210 800b010: 4603 mov r3, r0 800b012: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b014: 7bfb ldrb r3, [r7, #15] 800b016: 4618 mov r0, r3 800b018: f000 f97e bl 800b318 800b01c: 4603 mov r3, r0 800b01e: 73bb strb r3, [r7, #14] return usb_status; 800b020: 7bbb ldrb r3, [r7, #14] } 800b022: 4618 mov r0, r3 800b024: 3710 adds r7, #16 800b026: 46bd mov sp, r7 800b028: bd80 pop {r7, pc} 0800b02a : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 800b02a: b580 push {r7, lr} 800b02c: b084 sub sp, #16 800b02e: af00 add r7, sp, #0 800b030: 6078 str r0, [r7, #4] 800b032: 4608 mov r0, r1 800b034: 4611 mov r1, r2 800b036: 461a mov r2, r3 800b038: 4603 mov r3, r0 800b03a: 70fb strb r3, [r7, #3] 800b03c: 460b mov r3, r1 800b03e: 70bb strb r3, [r7, #2] 800b040: 4613 mov r3, r2 800b042: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 800b044: 2300 movs r3, #0 800b046: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b048: 2300 movs r3, #0 800b04a: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 800b04c: 687b ldr r3, [r7, #4] 800b04e: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800b052: 78bb ldrb r3, [r7, #2] 800b054: 883a ldrh r2, [r7, #0] 800b056: 78f9 ldrb r1, [r7, #3] 800b058: f7f8 fe01 bl 8003c5e 800b05c: 4603 mov r3, r0 800b05e: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b060: 7bfb ldrb r3, [r7, #15] 800b062: 4618 mov r0, r3 800b064: f000 f958 bl 800b318 800b068: 4603 mov r3, r0 800b06a: 73bb strb r3, [r7, #14] return usb_status; 800b06c: 7bbb ldrb r3, [r7, #14] } 800b06e: 4618 mov r0, r3 800b070: 3710 adds r7, #16 800b072: 46bd mov sp, r7 800b074: bd80 pop {r7, pc} 0800b076 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800b076: b580 push {r7, lr} 800b078: b084 sub sp, #16 800b07a: af00 add r7, sp, #0 800b07c: 6078 str r0, [r7, #4] 800b07e: 460b mov r3, r1 800b080: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800b082: 2300 movs r3, #0 800b084: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b086: 2300 movs r3, #0 800b088: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 800b08a: 687b ldr r3, [r7, #4] 800b08c: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b090: 78fa ldrb r2, [r7, #3] 800b092: 4611 mov r1, r2 800b094: 4618 mov r0, r3 800b096: f7f8 fe4c bl 8003d32 800b09a: 4603 mov r3, r0 800b09c: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b09e: 7bfb ldrb r3, [r7, #15] 800b0a0: 4618 mov r0, r3 800b0a2: f000 f939 bl 800b318 800b0a6: 4603 mov r3, r0 800b0a8: 73bb strb r3, [r7, #14] return usb_status; 800b0aa: 7bbb ldrb r3, [r7, #14] } 800b0ac: 4618 mov r0, r3 800b0ae: 3710 adds r7, #16 800b0b0: 46bd mov sp, r7 800b0b2: bd80 pop {r7, pc} 0800b0b4 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800b0b4: b580 push {r7, lr} 800b0b6: b084 sub sp, #16 800b0b8: af00 add r7, sp, #0 800b0ba: 6078 str r0, [r7, #4] 800b0bc: 460b mov r3, r1 800b0be: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800b0c0: 2300 movs r3, #0 800b0c2: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b0c4: 2300 movs r3, #0 800b0c6: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 800b0c8: 687b ldr r3, [r7, #4] 800b0ca: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b0ce: 78fa ldrb r2, [r7, #3] 800b0d0: 4611 mov r1, r2 800b0d2: 4618 mov r0, r3 800b0d4: f7f8 feec bl 8003eb0 800b0d8: 4603 mov r3, r0 800b0da: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b0dc: 7bfb ldrb r3, [r7, #15] 800b0de: 4618 mov r0, r3 800b0e0: f000 f91a bl 800b318 800b0e4: 4603 mov r3, r0 800b0e6: 73bb strb r3, [r7, #14] return usb_status; 800b0e8: 7bbb ldrb r3, [r7, #14] } 800b0ea: 4618 mov r0, r3 800b0ec: 3710 adds r7, #16 800b0ee: 46bd mov sp, r7 800b0f0: bd80 pop {r7, pc} 0800b0f2 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800b0f2: b580 push {r7, lr} 800b0f4: b084 sub sp, #16 800b0f6: af00 add r7, sp, #0 800b0f8: 6078 str r0, [r7, #4] 800b0fa: 460b mov r3, r1 800b0fc: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800b0fe: 2300 movs r3, #0 800b100: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b102: 2300 movs r3, #0 800b104: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 800b106: 687b ldr r3, [r7, #4] 800b108: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b10c: 78fa ldrb r2, [r7, #3] 800b10e: 4611 mov r1, r2 800b110: 4618 mov r0, r3 800b112: f7f8 ff30 bl 8003f76 800b116: 4603 mov r3, r0 800b118: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b11a: 7bfb ldrb r3, [r7, #15] 800b11c: 4618 mov r0, r3 800b11e: f000 f8fb bl 800b318 800b122: 4603 mov r3, r0 800b124: 73bb strb r3, [r7, #14] return usb_status; 800b126: 7bbb ldrb r3, [r7, #14] } 800b128: 4618 mov r0, r3 800b12a: 3710 adds r7, #16 800b12c: 46bd mov sp, r7 800b12e: bd80 pop {r7, pc} 0800b130 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 800b130: b480 push {r7} 800b132: b085 sub sp, #20 800b134: af00 add r7, sp, #0 800b136: 6078 str r0, [r7, #4] 800b138: 460b mov r3, r1 800b13a: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 800b13c: 687b ldr r3, [r7, #4] 800b13e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b142: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 800b144: f997 3003 ldrsb.w r3, [r7, #3] 800b148: 2b00 cmp r3, #0 800b14a: da0b bge.n 800b164 { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 800b14c: 78fb ldrb r3, [r7, #3] 800b14e: f003 027f and.w r2, r3, #127 @ 0x7f 800b152: 68f9 ldr r1, [r7, #12] 800b154: 4613 mov r3, r2 800b156: 00db lsls r3, r3, #3 800b158: 4413 add r3, r2 800b15a: 009b lsls r3, r3, #2 800b15c: 440b add r3, r1 800b15e: 3316 adds r3, #22 800b160: 781b ldrb r3, [r3, #0] 800b162: e00b b.n 800b17c } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 800b164: 78fb ldrb r3, [r7, #3] 800b166: f003 027f and.w r2, r3, #127 @ 0x7f 800b16a: 68f9 ldr r1, [r7, #12] 800b16c: 4613 mov r3, r2 800b16e: 00db lsls r3, r3, #3 800b170: 4413 add r3, r2 800b172: 009b lsls r3, r3, #2 800b174: 440b add r3, r1 800b176: f203 2356 addw r3, r3, #598 @ 0x256 800b17a: 781b ldrb r3, [r3, #0] } } 800b17c: 4618 mov r0, r3 800b17e: 3714 adds r7, #20 800b180: 46bd mov sp, r7 800b182: f85d 7b04 ldr.w r7, [sp], #4 800b186: 4770 bx lr 0800b188 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 800b188: b580 push {r7, lr} 800b18a: b084 sub sp, #16 800b18c: af00 add r7, sp, #0 800b18e: 6078 str r0, [r7, #4] 800b190: 460b mov r3, r1 800b192: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 800b194: 2300 movs r3, #0 800b196: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 800b198: 2300 movs r3, #0 800b19a: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 800b19c: 687b ldr r3, [r7, #4] 800b19e: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 800b1a2: 78fa ldrb r2, [r7, #3] 800b1a4: 4611 mov r1, r2 800b1a6: 4618 mov r0, r3 800b1a8: f7f8 fd35 bl 8003c16 800b1ac: 4603 mov r3, r0 800b1ae: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 800b1b0: 7bfb ldrb r3, [r7, #15] 800b1b2: 4618 mov r0, r3 800b1b4: f000 f8b0 bl 800b318 800b1b8: 4603 mov r3, r0 800b1ba: 73bb strb r3, [r7, #14] return usb_status; 800b1bc: 7bbb ldrb r3, [r7, #14] } 800b1be: 4618 mov r0, r3 800b1c0: 3710 adds r7, #16 800b1c2: 46bd mov sp, r7 800b1c4: bd80 pop {r7, pc} 0800b1c6 : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800b1c6: b580 push {r7, lr} 800b1c8: b086 sub sp, #24 800b1ca: af00 add r7, sp, #0 800b1cc: 60f8 str r0, [r7, #12] 800b1ce: 607a str r2, [r7, #4] 800b1d0: 603b str r3, [r7, #0] 800b1d2: 460b mov r3, r1 800b1d4: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800b1d6: 2300 movs r3, #0 800b1d8: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800b1da: 2300 movs r3, #0 800b1dc: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 800b1de: 68fb ldr r3, [r7, #12] 800b1e0: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800b1e4: 7af9 ldrb r1, [r7, #11] 800b1e6: 683b ldr r3, [r7, #0] 800b1e8: 687a ldr r2, [r7, #4] 800b1ea: f7f8 fe27 bl 8003e3c 800b1ee: 4603 mov r3, r0 800b1f0: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800b1f2: 7dfb ldrb r3, [r7, #23] 800b1f4: 4618 mov r0, r3 800b1f6: f000 f88f bl 800b318 800b1fa: 4603 mov r3, r0 800b1fc: 75bb strb r3, [r7, #22] return usb_status; 800b1fe: 7dbb ldrb r3, [r7, #22] } 800b200: 4618 mov r0, r3 800b202: 3718 adds r7, #24 800b204: 46bd mov sp, r7 800b206: bd80 pop {r7, pc} 0800b208 : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 800b208: b580 push {r7, lr} 800b20a: b086 sub sp, #24 800b20c: af00 add r7, sp, #0 800b20e: 60f8 str r0, [r7, #12] 800b210: 607a str r2, [r7, #4] 800b212: 603b str r3, [r7, #0] 800b214: 460b mov r3, r1 800b216: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 800b218: 2300 movs r3, #0 800b21a: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 800b21c: 2300 movs r3, #0 800b21e: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 800b220: 68fb ldr r3, [r7, #12] 800b222: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 800b226: 7af9 ldrb r1, [r7, #11] 800b228: 683b ldr r3, [r7, #0] 800b22a: 687a ldr r2, [r7, #4] 800b22c: f7f8 fdcb bl 8003dc6 800b230: 4603 mov r3, r0 800b232: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 800b234: 7dfb ldrb r3, [r7, #23] 800b236: 4618 mov r0, r3 800b238: f000 f86e bl 800b318 800b23c: 4603 mov r3, r0 800b23e: 75bb strb r3, [r7, #22] return usb_status; 800b240: 7dbb ldrb r3, [r7, #22] } 800b242: 4618 mov r0, r3 800b244: 3718 adds r7, #24 800b246: 46bd mov sp, r7 800b248: bd80 pop {r7, pc} ... 0800b24c : * @param hpcd: PCD handle * @param msg: LPM message * @retval None */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { 800b24c: b580 push {r7, lr} 800b24e: b082 sub sp, #8 800b250: af00 add r7, sp, #0 800b252: 6078 str r0, [r7, #4] 800b254: 460b mov r3, r1 800b256: 70fb strb r3, [r7, #3] switch (msg) 800b258: 78fb ldrb r3, [r7, #3] 800b25a: 2b00 cmp r3, #0 800b25c: d002 beq.n 800b264 800b25e: 2b01 cmp r3, #1 800b260: d01f beq.n 800b2a2 /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } } 800b262: e03b b.n 800b2dc if (hpcd->Init.low_power_enable) 800b264: 687b ldr r3, [r7, #4] 800b266: 7adb ldrb r3, [r3, #11] 800b268: 2b00 cmp r3, #0 800b26a: d007 beq.n 800b27c SystemClock_Config(); 800b26c: f7f5 fcee bl 8000c4c SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800b270: 4b1c ldr r3, [pc, #112] @ (800b2e4 ) 800b272: 691b ldr r3, [r3, #16] 800b274: 4a1b ldr r2, [pc, #108] @ (800b2e4 ) 800b276: f023 0306 bic.w r3, r3, #6 800b27a: 6113 str r3, [r2, #16] __HAL_PCD_UNGATE_PHYCLOCK(hpcd); 800b27c: 687b ldr r3, [r7, #4] 800b27e: 681b ldr r3, [r3, #0] 800b280: f503 6360 add.w r3, r3, #3584 @ 0xe00 800b284: 681b ldr r3, [r3, #0] 800b286: 687a ldr r2, [r7, #4] 800b288: 6812 ldr r2, [r2, #0] 800b28a: f502 6260 add.w r2, r2, #3584 @ 0xe00 800b28e: f023 0301 bic.w r3, r3, #1 800b292: 6013 str r3, [r2, #0] USBD_LL_Resume(hpcd->pData); 800b294: 687b ldr r3, [r7, #4] 800b296: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b29a: 4618 mov r0, r3 800b29c: f7fe fb90 bl 80099c0 break; 800b2a0: e01c b.n 800b2dc __HAL_PCD_GATE_PHYCLOCK(hpcd); 800b2a2: 687b ldr r3, [r7, #4] 800b2a4: 681b ldr r3, [r3, #0] 800b2a6: f503 6360 add.w r3, r3, #3584 @ 0xe00 800b2aa: 681b ldr r3, [r3, #0] 800b2ac: 687a ldr r2, [r7, #4] 800b2ae: 6812 ldr r2, [r2, #0] 800b2b0: f502 6260 add.w r2, r2, #3584 @ 0xe00 800b2b4: f043 0301 orr.w r3, r3, #1 800b2b8: 6013 str r3, [r2, #0] USBD_LL_Suspend(hpcd->pData); 800b2ba: 687b ldr r3, [r7, #4] 800b2bc: f8d3 34e0 ldr.w r3, [r3, #1248] @ 0x4e0 800b2c0: 4618 mov r0, r3 800b2c2: f7fe fb61 bl 8009988 if (hpcd->Init.low_power_enable) 800b2c6: 687b ldr r3, [r7, #4] 800b2c8: 7adb ldrb r3, [r3, #11] 800b2ca: 2b00 cmp r3, #0 800b2cc: d005 beq.n 800b2da SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 800b2ce: 4b05 ldr r3, [pc, #20] @ (800b2e4 ) 800b2d0: 691b ldr r3, [r3, #16] 800b2d2: 4a04 ldr r2, [pc, #16] @ (800b2e4 ) 800b2d4: f043 0306 orr.w r3, r3, #6 800b2d8: 6113 str r3, [r2, #16] break; 800b2da: bf00 nop } 800b2dc: bf00 nop 800b2de: 3708 adds r7, #8 800b2e0: 46bd mov sp, r7 800b2e2: bd80 pop {r7, pc} 800b2e4: e000ed00 .word 0xe000ed00 0800b2e8 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 800b2e8: b480 push {r7} 800b2ea: b083 sub sp, #12 800b2ec: af00 add r7, sp, #0 800b2ee: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 800b2f0: 4b03 ldr r3, [pc, #12] @ (800b300 ) } 800b2f2: 4618 mov r0, r3 800b2f4: 370c adds r7, #12 800b2f6: 46bd mov sp, r7 800b2f8: f85d 7b04 ldr.w r7, [sp], #4 800b2fc: 4770 bx lr 800b2fe: bf00 nop 800b300: 200017e8 .word 0x200017e8 0800b304 : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 800b304: b480 push {r7} 800b306: b083 sub sp, #12 800b308: af00 add r7, sp, #0 800b30a: 6078 str r0, [r7, #4] } 800b30c: bf00 nop 800b30e: 370c adds r7, #12 800b310: 46bd mov sp, r7 800b312: f85d 7b04 ldr.w r7, [sp], #4 800b316: 4770 bx lr 0800b318 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 800b318: b480 push {r7} 800b31a: b085 sub sp, #20 800b31c: af00 add r7, sp, #0 800b31e: 4603 mov r3, r0 800b320: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 800b322: 2300 movs r3, #0 800b324: 73fb strb r3, [r7, #15] switch (hal_status) 800b326: 79fb ldrb r3, [r7, #7] 800b328: 2b03 cmp r3, #3 800b32a: d817 bhi.n 800b35c 800b32c: a201 add r2, pc, #4 @ (adr r2, 800b334 ) 800b32e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b332: bf00 nop 800b334: 0800b345 .word 0x0800b345 800b338: 0800b34b .word 0x0800b34b 800b33c: 0800b351 .word 0x0800b351 800b340: 0800b357 .word 0x0800b357 { case HAL_OK : usb_status = USBD_OK; 800b344: 2300 movs r3, #0 800b346: 73fb strb r3, [r7, #15] break; 800b348: e00b b.n 800b362 case HAL_ERROR : usb_status = USBD_FAIL; 800b34a: 2303 movs r3, #3 800b34c: 73fb strb r3, [r7, #15] break; 800b34e: e008 b.n 800b362 case HAL_BUSY : usb_status = USBD_BUSY; 800b350: 2301 movs r3, #1 800b352: 73fb strb r3, [r7, #15] break; 800b354: e005 b.n 800b362 case HAL_TIMEOUT : usb_status = USBD_FAIL; 800b356: 2303 movs r3, #3 800b358: 73fb strb r3, [r7, #15] break; 800b35a: e002 b.n 800b362 default : usb_status = USBD_FAIL; 800b35c: 2303 movs r3, #3 800b35e: 73fb strb r3, [r7, #15] break; 800b360: bf00 nop } return usb_status; 800b362: 7bfb ldrb r3, [r7, #15] } 800b364: 4618 mov r0, r3 800b366: 3714 adds r7, #20 800b368: 46bd mov sp, r7 800b36a: f85d 7b04 ldr.w r7, [sp], #4 800b36e: 4770 bx lr 0800b370 : 800b370: 4402 add r2, r0 800b372: 4603 mov r3, r0 800b374: 4293 cmp r3, r2 800b376: d100 bne.n 800b37a 800b378: 4770 bx lr 800b37a: f803 1b01 strb.w r1, [r3], #1 800b37e: e7f9 b.n 800b374 0800b380 <__libc_init_array>: 800b380: b570 push {r4, r5, r6, lr} 800b382: 4d0d ldr r5, [pc, #52] @ (800b3b8 <__libc_init_array+0x38>) 800b384: 4c0d ldr r4, [pc, #52] @ (800b3bc <__libc_init_array+0x3c>) 800b386: 1b64 subs r4, r4, r5 800b388: 10a4 asrs r4, r4, #2 800b38a: 2600 movs r6, #0 800b38c: 42a6 cmp r6, r4 800b38e: d109 bne.n 800b3a4 <__libc_init_array+0x24> 800b390: 4d0b ldr r5, [pc, #44] @ (800b3c0 <__libc_init_array+0x40>) 800b392: 4c0c ldr r4, [pc, #48] @ (800b3c4 <__libc_init_array+0x44>) 800b394: f000 f826 bl 800b3e4 <_init> 800b398: 1b64 subs r4, r4, r5 800b39a: 10a4 asrs r4, r4, #2 800b39c: 2600 movs r6, #0 800b39e: 42a6 cmp r6, r4 800b3a0: d105 bne.n 800b3ae <__libc_init_array+0x2e> 800b3a2: bd70 pop {r4, r5, r6, pc} 800b3a4: f855 3b04 ldr.w r3, [r5], #4 800b3a8: 4798 blx r3 800b3aa: 3601 adds r6, #1 800b3ac: e7ee b.n 800b38c <__libc_init_array+0xc> 800b3ae: f855 3b04 ldr.w r3, [r5], #4 800b3b2: 4798 blx r3 800b3b4: 3601 adds r6, #1 800b3b6: e7f2 b.n 800b39e <__libc_init_array+0x1e> 800b3b8: 0800b460 .word 0x0800b460 800b3bc: 0800b460 .word 0x0800b460 800b3c0: 0800b460 .word 0x0800b460 800b3c4: 0800b464 .word 0x0800b464 0800b3c8 : 800b3c8: 440a add r2, r1 800b3ca: 4291 cmp r1, r2 800b3cc: f100 33ff add.w r3, r0, #4294967295 800b3d0: d100 bne.n 800b3d4 800b3d2: 4770 bx lr 800b3d4: b510 push {r4, lr} 800b3d6: f811 4b01 ldrb.w r4, [r1], #1 800b3da: f803 4f01 strb.w r4, [r3, #1]! 800b3de: 4291 cmp r1, r2 800b3e0: d1f9 bne.n 800b3d6 800b3e2: bd10 pop {r4, pc} 0800b3e4 <_init>: 800b3e4: b5f8 push {r3, r4, r5, r6, r7, lr} 800b3e6: bf00 nop 800b3e8: bcf8 pop {r3, r4, r5, r6, r7} 800b3ea: bc08 pop {r3} 800b3ec: 469e mov lr, r3 800b3ee: 4770 bx lr 0800b3f0 <_fini>: 800b3f0: b5f8 push {r3, r4, r5, r6, r7, lr} 800b3f2: bf00 nop 800b3f4: bcf8 pop {r3, r4, r5, r6, r7} 800b3f6: bc08 pop {r3} 800b3f8: 469e mov lr, r3 800b3fa: 4770 bx lr